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996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
9ebbca7d GK |
2 | ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
3 | ;; 1999, 2000 Free Software Foundation, Inc. | |
996a5f59 | 4 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 RK |
5 | |
6 | ;; This file is part of GNU CC. | |
7 | ||
8 | ;; GNU CC is free software; you can redistribute it and/or modify | |
9 | ;; it under the terms of the GNU General Public License as published by | |
10 | ;; the Free Software Foundation; either version 2, or (at your option) | |
11 | ;; any later version. | |
12 | ||
13 | ;; GNU CC is distributed in the hope that it will be useful, | |
14 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | ;; GNU General Public License for more details. | |
17 | ||
18 | ;; You should have received a copy of the GNU General Public License | |
19 | ;; along with GNU CC; see the file COPYING. If not, write to | |
3f63df56 RK |
20 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, |
21 | ;; Boston, MA 02111-1307, USA. | |
1fd4e8c1 RK |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
9ebbca7d GK |
24 | |
25 | ;; `unspec' values used in rs6000.md: | |
26 | ;; Number Use | |
27 | ;; 0 frsp for POWER machines | |
28 | ;; 0/v blockage | |
29 | ;; 5 used to tie the stack contents and the stack pointer | |
30 | ;; 6 address of a word pointing to the TOC | |
31 | ;; 7 address of the TOC (more-or-less) | |
32 | ;; 8 movsi_got | |
33 | ;; 9/v eh_reg_restore | |
34 | ;; 10 fctiwz | |
35 | ;; 19 movesi_from_cr | |
36 | ;; 20 movesi_to_cr | |
1fd4e8c1 RK |
37 | \f |
38 | ;; Define an insn type attribute. This is used in function unit delay | |
39 | ;; computations. | |
3cb999d8 | 40 | (define_attr "type" "integer,load,store,fpload,fpstore,imul,lmul,idiv,ldiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg" |
1fd4e8c1 RK |
41 | (const_string "integer")) |
42 | ||
b19003d8 RK |
43 | ;; Length (in bytes). |
44 | (define_attr "length" "" | |
45 | (if_then_else (eq_attr "type" "branch") | |
46 | (if_then_else (and (ge (minus (pc) (match_dup 0)) | |
47 | (const_int -32768)) | |
48 | (lt (minus (pc) (match_dup 0)) | |
49 | (const_int 32767))) | |
50 | (const_int 8) | |
51 | (const_int 12)) | |
52 | (const_int 4))) | |
53 | ||
cfb557c4 RK |
54 | ;; Processor type -- this attribute must exactly match the processor_type |
55 | ;; enumeration in rs6000.h. | |
56 | ||
3cb999d8 | 57 | (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750" |
cfb557c4 RK |
58 | (const (symbol_ref "rs6000_cpu_attr"))) |
59 | ||
60 | ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY | |
61 | ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST]) | |
62 | ||
b7ff3d82 | 63 | ; Load/Store Unit -- pure PowerPC only |
51b8fc2c | 64 | ; (POWER and 601 use Integer Unit) |
cfb557c4 RK |
65 | (define_function_unit "lsu" 1 0 |
66 | (and (eq_attr "type" "load") | |
3cb999d8 | 67 | (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b6c9286a | 68 | 2 1) |
cfb557c4 RK |
69 | |
70 | (define_function_unit "lsu" 1 0 | |
b7ff3d82 | 71 | (and (eq_attr "type" "store,fpstore") |
3cb999d8 | 72 | (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b7ff3d82 | 73 | 1 1) |
b6c9286a MM |
74 | |
75 | (define_function_unit "lsu" 1 0 | |
76 | (and (eq_attr "type" "fpload") | |
bef84347 | 77 | (eq_attr "cpu" "mpccore,ppc603,ppc750")) |
b6c9286a | 78 | 2 1) |
cfb557c4 | 79 | |
b7ff3d82 DE |
80 | (define_function_unit "lsu" 1 0 |
81 | (and (eq_attr "type" "fpload") | |
3cb999d8 | 82 | (eq_attr "cpu" "rs64a,ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 DE |
83 | 3 1) |
84 | ||
cfb557c4 RK |
85 | (define_function_unit "iu" 1 0 |
86 | (and (eq_attr "type" "load") | |
b7ff3d82 | 87 | (eq_attr "cpu" "rios1,ppc403,ppc601")) |
b6c9286a | 88 | 2 1) |
cfb557c4 RK |
89 | |
90 | (define_function_unit "iu" 1 0 | |
b7ff3d82 DE |
91 | (and (eq_attr "type" "store,fpstore") |
92 | (eq_attr "cpu" "rios1,ppc403,ppc601")) | |
93 | 1 1) | |
94 | ||
95 | (define_function_unit "fpu" 1 0 | |
96 | (and (eq_attr "type" "fpstore") | |
3624a679 | 97 | (eq_attr "cpu" "rios1,ppc601")) |
b7ff3d82 | 98 | 0 1) |
cfb557c4 | 99 | |
49a0b204 | 100 | (define_function_unit "iu" 1 0 |
b7ff3d82 | 101 | (and (eq_attr "type" "fpload") |
b6c9286a | 102 | (eq_attr "cpu" "rios1")) |
b7ff3d82 DE |
103 | 2 1) |
104 | ||
105 | (define_function_unit "iu" 1 0 | |
106 | (and (eq_attr "type" "fpload") | |
107 | (eq_attr "cpu" "ppc601")) | |
108 | 3 1) | |
109 | ||
110 | (define_function_unit "iu2" 2 0 | |
111 | (and (eq_attr "type" "load,fpload") | |
112 | (eq_attr "cpu" "rios2")) | |
113 | 2 1) | |
114 | ||
115 | (define_function_unit "iu2" 2 0 | |
116 | (and (eq_attr "type" "store,fpstore") | |
117 | (eq_attr "cpu" "rios2")) | |
118 | 1 1) | |
119 | ||
3cb999d8 | 120 | ; Integer Unit (RIOS1, PPC601, PPC603, RS64a) |
b7ff3d82 DE |
121 | (define_function_unit "iu" 1 0 |
122 | (and (eq_attr "type" "integer") | |
3cb999d8 | 123 | (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc601,ppc603")) |
b7ff3d82 | 124 | 1 1) |
49a0b204 | 125 | |
da0ae67f MM |
126 | (define_function_unit "iu" 1 0 |
127 | (and (eq_attr "type" "imul") | |
128 | (eq_attr "cpu" "ppc403")) | |
129 | 4 4) | |
130 | ||
cfb557c4 RK |
131 | (define_function_unit "iu" 1 0 |
132 | (and (eq_attr "type" "imul") | |
b7ff3d82 | 133 | (eq_attr "cpu" "rios1,ppc601,ppc603")) |
51b8fc2c | 134 | 5 5) |
cfb557c4 | 135 | |
3cb999d8 DE |
136 | (define_function_unit "iu" 1 0 |
137 | (and (eq_attr "type" "imul") | |
138 | (eq_attr "cpu" "rs64a")) | |
139 | 20 14) | |
140 | ||
141 | (define_function_unit "iu" 1 0 | |
142 | (and (eq_attr "type" "lmul") | |
143 | (eq_attr "cpu" "rs64a")) | |
144 | 34 34) | |
145 | ||
cfb557c4 RK |
146 | (define_function_unit "iu" 1 0 |
147 | (and (eq_attr "type" "idiv") | |
ca7f5001 | 148 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 149 | 19 19) |
cfb557c4 | 150 | |
3cb999d8 DE |
151 | (define_function_unit "iu" 1 0 |
152 | (and (eq_attr "type" "idiv") | |
153 | (eq_attr "cpu" "rs64a")) | |
154 | 66 66) | |
155 | ||
156 | (define_function_unit "iu" 1 0 | |
157 | (and (eq_attr "type" "ldiv") | |
158 | (eq_attr "cpu" "rs64a")) | |
159 | 66 66) | |
160 | ||
cfb557c4 RK |
161 | (define_function_unit "iu" 1 0 |
162 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
163 | (eq_attr "cpu" "ppc403")) |
164 | 33 33) | |
51b8fc2c | 165 | |
da0ae67f MM |
166 | (define_function_unit "iu" 1 0 |
167 | (and (eq_attr "type" "idiv") | |
b7ff3d82 DE |
168 | (eq_attr "cpu" "ppc601")) |
169 | 36 36) | |
da0ae67f | 170 | |
51b8fc2c RK |
171 | (define_function_unit "iu" 1 0 |
172 | (and (eq_attr "type" "idiv") | |
b7ff3d82 | 173 | (eq_attr "cpu" "ppc603")) |
51b8fc2c RK |
174 | 37 36) |
175 | ||
176 | ; RIOS2 has two integer units: a primary one which can perform all | |
177 | ; operations and a secondary one which is fed in lock step with the first | |
b6c9286a MM |
178 | ; and can perform "simple" integer operations. |
179 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
180 | ; for the complex insns. | |
51b8fc2c RK |
181 | (define_function_unit "iu2" 2 0 |
182 | (and (eq_attr "type" "integer") | |
183 | (eq_attr "cpu" "rios2")) | |
b7ff3d82 | 184 | 1 1) |
b6c9286a MM |
185 | |
186 | (define_function_unit "iu2" 2 0 | |
187 | (and (eq_attr "type" "imul") | |
188 | (eq_attr "cpu" "rios2")) | |
189 | 2 2) | |
190 | ||
191 | (define_function_unit "iu2" 2 0 | |
192 | (and (eq_attr "type" "idiv") | |
193 | (eq_attr "cpu" "rios2")) | |
194 | 13 13) | |
51b8fc2c RK |
195 | |
196 | (define_function_unit "imuldiv" 1 0 | |
197 | (and (eq_attr "type" "imul") | |
198 | (eq_attr "cpu" "rios2")) | |
b6c9286a MM |
199 | 2 2) |
200 | ||
51b8fc2c RK |
201 | (define_function_unit "imuldiv" 1 0 |
202 | (and (eq_attr "type" "idiv") | |
203 | (eq_attr "cpu" "rios2")) | |
b6c9286a | 204 | 13 13) |
51b8fc2c | 205 | |
cf27b467 MM |
206 | ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions |
207 | ; Divide latency varies greatly from 2-11, use 6 as average | |
208 | (define_function_unit "imuldiv" 1 0 | |
209 | (and (eq_attr "type" "imul") | |
210 | (eq_attr "cpu" "mpccore")) | |
211 | 2 1) | |
212 | ||
213 | (define_function_unit "imuldiv" 1 0 | |
214 | (and (eq_attr "type" "idiv") | |
215 | (eq_attr "cpu" "mpccore")) | |
216 | 6 6) | |
217 | ||
cac8ce95 | 218 | ; PPC604{,e} has two units that perform integer operations |
b6c9286a MM |
219 | ; and one unit for divide/multiply operations (and move |
220 | ; from/to spr). | |
221 | (define_function_unit "iu2" 2 0 | |
51b8fc2c | 222 | (and (eq_attr "type" "integer") |
3cb999d8 | 223 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630")) |
b7ff3d82 | 224 | 1 1) |
51b8fc2c RK |
225 | |
226 | (define_function_unit "imuldiv" 1 0 | |
227 | (and (eq_attr "type" "imul") | |
3cb999d8 | 228 | (eq_attr "cpu" "ppc604")) |
b7ff3d82 | 229 | 4 2) |
51b8fc2c | 230 | |
3cb999d8 DE |
231 | (define_function_unit "imuldiv" 1 0 |
232 | (and (eq_attr "type" "imul") | |
233 | (eq_attr "cpu" "ppc620,ppc630")) | |
234 | 5 3) | |
235 | ||
236 | (define_function_unit "imuldiv" 1 0 | |
237 | (and (eq_attr "type" "lmul") | |
238 | (eq_attr "cpu" "ppc620,ppc630")) | |
239 | 5 3) | |
240 | ||
cac8ce95 DE |
241 | (define_function_unit "imuldiv" 1 0 |
242 | (and (eq_attr "type" "imul") | |
243 | (eq_attr "cpu" "ppc604e")) | |
244 | 2 1) | |
245 | ||
51b8fc2c RK |
246 | (define_function_unit "imuldiv" 1 0 |
247 | (and (eq_attr "type" "idiv") | |
3cb999d8 | 248 | (eq_attr "cpu" "ppc604,ppc604e")) |
b7ff3d82 | 249 | 20 19) |
cfb557c4 | 250 | |
3cb999d8 DE |
251 | (define_function_unit "imuldiv" 1 0 |
252 | (and (eq_attr "type" "idiv") | |
253 | (eq_attr "cpu" "ppc620")) | |
254 | 37 36) | |
255 | ||
256 | (define_function_unit "imuldiv" 1 0 | |
257 | (and (eq_attr "type" "idiv") | |
258 | (eq_attr "cpu" "ppc630")) | |
259 | 21 20) | |
260 | ||
261 | (define_function_unit "imuldiv" 1 0 | |
262 | (and (eq_attr "type" "ldiv") | |
263 | (eq_attr "cpu" "ppc620,ppc630")) | |
264 | 37 36) | |
265 | ||
bef84347 VM |
266 | ; PPC750 has two integer units: a primary one which can perform all |
267 | ; operations and a secondary one which is fed in lock step with the first | |
268 | ; and can perform "simple" integer operations. | |
269 | ; To catch this we define a 'dummy' imuldiv-unit that is also needed | |
270 | ; for the complex insns. | |
271 | (define_function_unit "iu2" 2 0 | |
272 | (and (eq_attr "type" "integer") | |
273 | (eq_attr "cpu" "ppc750")) | |
274 | 1 1) | |
275 | ||
276 | (define_function_unit "iu2" 2 0 | |
277 | (and (eq_attr "type" "imul") | |
278 | (eq_attr "cpu" "ppc750")) | |
279 | 4 2) | |
280 | ||
281 | (define_function_unit "imuldiv" 1 0 | |
282 | (and (eq_attr "type" "imul") | |
283 | (eq_attr "cpu" "ppc750")) | |
284 | 4 2) | |
285 | ||
286 | (define_function_unit "imuldiv" 1 0 | |
287 | (and (eq_attr "type" "idiv") | |
288 | (eq_attr "cpu" "ppc750")) | |
289 | 19 19) | |
290 | ||
b6c9286a | 291 | ; compare is done on integer unit, but feeds insns which |
acc5239d | 292 | ; execute on the branch unit. |
b6c9286a MM |
293 | (define_function_unit "iu" 1 0 |
294 | (and (eq_attr "type" "compare") | |
b7ff3d82 DE |
295 | (eq_attr "cpu" "rios1")) |
296 | 4 1) | |
297 | ||
298 | (define_function_unit "iu" 1 0 | |
299 | (and (eq_attr "type" "delayed_compare") | |
300 | (eq_attr "cpu" "rios1")) | |
301 | 5 1) | |
302 | ||
303 | (define_function_unit "iu" 1 0 | |
304 | (and (eq_attr "type" "compare,delayed_compare") | |
3cb999d8 | 305 | (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b7ff3d82 | 306 | 3 1) |
b6c9286a MM |
307 | |
308 | (define_function_unit "iu2" 2 0 | |
b7ff3d82 | 309 | (and (eq_attr "type" "compare,delayed_compare") |
b6c9286a | 310 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 311 | 3 1) |
b6c9286a | 312 | |
b6c9286a | 313 | (define_function_unit "iu2" 2 0 |
b7ff3d82 | 314 | (and (eq_attr "type" "compare,delayed_compare") |
3cb999d8 | 315 | (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750")) |
b6c9286a | 316 | 1 1) |
cfb557c4 | 317 | |
b6c9286a MM |
318 | ; fp compare uses fp unit |
319 | (define_function_unit "fpu" 1 0 | |
cfb557c4 | 320 | (and (eq_attr "type" "fpcompare") |
b6c9286a | 321 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 322 | 9 1) |
cfb557c4 | 323 | |
b6c9286a MM |
324 | ; rios1 and rios2 have different fpcompare delays |
325 | (define_function_unit "fpu2" 2 0 | |
cfb557c4 | 326 | (and (eq_attr "type" "fpcompare") |
3cb999d8 | 327 | (eq_attr "cpu" "rios2,ppc630")) |
b6c9286a MM |
328 | 5 1) |
329 | ||
330 | ; on ppc601 and ppc603, fpcompare takes also 2 cycles from | |
331 | ; the integer unit | |
332 | ; here we do not define delays, just occupy the unit. The dependencies | |
b7ff3d82 | 333 | ; will be assigned by the fpcompare definition in the fpu. |
b6c9286a MM |
334 | (define_function_unit "iu" 1 0 |
335 | (and (eq_attr "type" "fpcompare") | |
b7ff3d82 | 336 | (eq_attr "cpu" "ppc601,ppc603")) |
b6c9286a MM |
337 | 0 2) |
338 | ||
339 | ; fp compare uses fp unit | |
340 | (define_function_unit "fpu" 1 0 | |
341 | (and (eq_attr "type" "fpcompare") | |
3cb999d8 | 342 | (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750")) |
b6c9286a | 343 | 5 1) |
cfb557c4 | 344 | |
cf27b467 MM |
345 | (define_function_unit "fpu" 1 0 |
346 | (and (eq_attr "type" "fpcompare") | |
347 | (eq_attr "cpu" "mpccore")) | |
348 | 1 1) | |
349 | ||
cfb557c4 | 350 | (define_function_unit "bpu" 1 0 |
324e52cc | 351 | (and (eq_attr "type" "mtjmpr") |
3cb999d8 | 352 | (eq_attr "cpu" "rios1,rios2,rs64a")) |
b7ff3d82 | 353 | 5 1) |
cfb557c4 RK |
354 | |
355 | (define_function_unit "bpu" 1 0 | |
324e52cc | 356 | (and (eq_attr "type" "mtjmpr") |
3cb999d8 | 357 | (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750")) |
b7ff3d82 | 358 | 4 1) |
cfb557c4 | 359 | |
b6c9286a MM |
360 | ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines. |
361 | (define_function_unit "bpu" 1 0 | |
362 | (eq_attr "type" "jmpreg") | |
b7ff3d82 | 363 | 1 1) |
b6c9286a MM |
364 | |
365 | (define_function_unit "bpu" 1 0 | |
366 | (eq_attr "type" "branch") | |
b7ff3d82 | 367 | 1 1) |
b6c9286a | 368 | |
cf27b467 | 369 | ; Floating Point Unit |
cfb557c4 | 370 | (define_function_unit "fpu" 1 0 |
51b8fc2c | 371 | (and (eq_attr "type" "fp,dmul") |
2661cdd9 | 372 | (eq_attr "cpu" "rios1")) |
b7ff3d82 | 373 | 2 1) |
cfb557c4 | 374 | |
cf27b467 MM |
375 | (define_function_unit "fpu" 1 0 |
376 | (and (eq_attr "type" "fp") | |
3cb999d8 DE |
377 | (eq_attr "cpu" "rs64a,mpccore")) |
378 | 4 2) | |
cf27b467 | 379 | |
cfb557c4 RK |
380 | (define_function_unit "fpu" 1 0 |
381 | (and (eq_attr "type" "fp") | |
51b8fc2c | 382 | (eq_attr "cpu" "ppc601")) |
b7ff3d82 | 383 | 4 1) |
cfb557c4 | 384 | |
51b8fc2c RK |
385 | (define_function_unit "fpu" 1 0 |
386 | (and (eq_attr "type" "fp") | |
3cb999d8 | 387 | (eq_attr "cpu" "ppc603,ppc750,ppc604,ppc604e,ppc620")) |
b6c9286a | 388 | 3 1) |
51b8fc2c | 389 | |
3cb999d8 DE |
390 | (define_function_unit "fpu" 1 0 |
391 | (and (eq_attr "type" "dmul") | |
392 | (eq_attr "cpu" "rs64a")) | |
393 | 7 2) | |
394 | ||
cf27b467 MM |
395 | (define_function_unit "fpu" 1 0 |
396 | (and (eq_attr "type" "dmul") | |
397 | (eq_attr "cpu" "mpccore")) | |
398 | 5 5) | |
399 | ||
cfb557c4 RK |
400 | (define_function_unit "fpu" 1 0 |
401 | (and (eq_attr "type" "dmul") | |
51b8fc2c | 402 | (eq_attr "cpu" "ppc601")) |
b6c9286a | 403 | 5 2) |
cfb557c4 | 404 | |
b6c9286a | 405 | ; is this true? |
cfb557c4 RK |
406 | (define_function_unit "fpu" 1 0 |
407 | (and (eq_attr "type" "dmul") | |
bef84347 | 408 | (eq_attr "cpu" "ppc603,ppc750")) |
51b8fc2c | 409 | 4 2) |
cfb557c4 RK |
410 | |
411 | (define_function_unit "fpu" 1 0 | |
51b8fc2c | 412 | (and (eq_attr "type" "dmul") |
cac8ce95 | 413 | (eq_attr "cpu" "ppc604,ppc604e,ppc620")) |
b6c9286a | 414 | 3 1) |
51b8fc2c RK |
415 | |
416 | (define_function_unit "fpu" 1 0 | |
417 | (and (eq_attr "type" "sdiv,ddiv") | |
2661cdd9 | 418 | (eq_attr "cpu" "rios1")) |
51b8fc2c | 419 | 19 19) |
cfb557c4 | 420 | |
3cb999d8 DE |
421 | (define_function_unit "fpu" 1 0 |
422 | (and (eq_attr "type" "sdiv") | |
423 | (eq_attr "cpu" "rs64a")) | |
424 | 31 31) | |
425 | ||
cfb557c4 RK |
426 | (define_function_unit "fpu" 1 0 |
427 | (and (eq_attr "type" "sdiv") | |
51b8fc2c RK |
428 | (eq_attr "cpu" "ppc601")) |
429 | 17 17) | |
430 | ||
cf27b467 MM |
431 | (define_function_unit "fpu" 1 0 |
432 | (and (eq_attr "type" "sdiv") | |
433 | (eq_attr "cpu" "mpccore")) | |
434 | 10 10) | |
435 | ||
51b8fc2c RK |
436 | (define_function_unit "fpu" 1 0 |
437 | (and (eq_attr "type" "sdiv") | |
cac8ce95 | 438 | (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620")) |
51b8fc2c | 439 | 18 18) |
cfb557c4 | 440 | |
cf27b467 MM |
441 | (define_function_unit "fpu" 1 0 |
442 | (and (eq_attr "type" "ddiv") | |
443 | (eq_attr "cpu" "mpccore")) | |
444 | 17 17) | |
445 | ||
cfb557c4 RK |
446 | (define_function_unit "fpu" 1 0 |
447 | (and (eq_attr "type" "ddiv") | |
3cb999d8 | 448 | (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620")) |
51b8fc2c | 449 | 31 31) |
cfb557c4 RK |
450 | |
451 | (define_function_unit "fpu" 1 0 | |
452 | (and (eq_attr "type" "ddiv") | |
b7ff3d82 | 453 | (eq_attr "cpu" "ppc603")) |
51b8fc2c | 454 | 33 33) |
cfb557c4 RK |
455 | |
456 | (define_function_unit "fpu" 1 0 | |
457 | (and (eq_attr "type" "ssqrt") | |
a473029f | 458 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 459 | 31 31) |
cfb557c4 RK |
460 | |
461 | (define_function_unit "fpu" 1 0 | |
462 | (and (eq_attr "type" "dsqrt") | |
a473029f | 463 | (eq_attr "cpu" "ppc620")) |
51b8fc2c | 464 | 31 31) |
b73d04f2 | 465 | |
51b8fc2c | 466 | ; RIOS2 has two symmetric FPUs. |
cfb557c4 RK |
467 | (define_function_unit "fpu2" 2 0 |
468 | (and (eq_attr "type" "fp") | |
4652f1d4 | 469 | (eq_attr "cpu" "rios2")) |
b7ff3d82 | 470 | 2 1) |
cfb557c4 | 471 | |
3cb999d8 DE |
472 | (define_function_unit "fpu2" 2 0 |
473 | (and (eq_attr "type" "fp") | |
474 | (eq_attr "cpu" "ppc630")) | |
475 | 3 1) | |
476 | ||
cfb557c4 RK |
477 | (define_function_unit "fpu2" 2 0 |
478 | (and (eq_attr "type" "dmul") | |
479 | (eq_attr "cpu" "rios2")) | |
b7ff3d82 | 480 | 2 1) |
cfb557c4 | 481 | |
3cb999d8 DE |
482 | (define_function_unit "fpu2" 2 0 |
483 | (and (eq_attr "type" "dmul") | |
484 | (eq_attr "cpu" "ppc630")) | |
485 | 3 1) | |
486 | ||
cfb557c4 | 487 | (define_function_unit "fpu2" 2 0 |
51b8fc2c | 488 | (and (eq_attr "type" "sdiv,ddiv") |
cfb557c4 | 489 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 490 | 17 17) |
ca7f5001 | 491 | |
3cb999d8 DE |
492 | (define_function_unit "fpu2" 2 0 |
493 | (and (eq_attr "type" "sdiv") | |
494 | (eq_attr "cpu" "ppc630")) | |
495 | 17 17) | |
496 | ||
497 | (define_function_unit "fpu2" 2 0 | |
498 | (and (eq_attr "type" "ddiv") | |
499 | (eq_attr "cpu" "ppc630")) | |
500 | 21 21) | |
501 | ||
ca7f5001 | 502 | (define_function_unit "fpu2" 2 0 |
51b8fc2c | 503 | (and (eq_attr "type" "ssqrt,dsqrt") |
ca7f5001 | 504 | (eq_attr "cpu" "rios2")) |
51b8fc2c | 505 | 26 26) |
b6c9286a | 506 | |
3cb999d8 DE |
507 | (define_function_unit "fpu2" 2 0 |
508 | (and (eq_attr "type" "ssqrt") | |
509 | (eq_attr "cpu" "ppc630")) | |
510 | 18 18) | |
511 | ||
512 | (define_function_unit "fpu2" 2 0 | |
513 | (and (eq_attr "type" "dsqrt") | |
514 | (eq_attr "cpu" "ppc630")) | |
515 | 26 26) | |
516 | ||
1fd4e8c1 RK |
517 | \f |
518 | ;; Start with fixed-point load and store insns. Here we put only the more | |
519 | ;; complex forms. Basic data transfer is done later. | |
520 | ||
51b8fc2c RK |
521 | (define_expand "zero_extendqidi2" |
522 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
523 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
524 | "TARGET_POWERPC64" | |
525 | "") | |
526 | ||
527 | (define_insn "" | |
528 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
529 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
530 | "TARGET_POWERPC64" | |
531 | "@ | |
532 | lbz%U1%X1 %0,%1 | |
4371f8af | 533 | rldicl %0,%1,0,56" |
51b8fc2c RK |
534 | [(set_attr "type" "load,*")]) |
535 | ||
536 | (define_insn "" | |
9ebbca7d GK |
537 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
538 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 539 | (const_int 0))) |
9ebbca7d | 540 | (clobber (match_scratch:DI 2 "=r,r"))] |
29ae5b89 | 541 | "TARGET_POWERPC64" |
9ebbca7d GK |
542 | "@ |
543 | rldicl. %2,%1,0,56 | |
544 | #" | |
545 | [(set_attr "type" "compare") | |
546 | (set_attr "length" "4,8")]) | |
547 | ||
548 | (define_split | |
549 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
550 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
551 | (const_int 0))) | |
552 | (clobber (match_scratch:DI 2 ""))] | |
553 | "TARGET_POWERPC64 && reload_completed" | |
554 | [(set (match_dup 2) | |
555 | (zero_extend:DI (match_dup 1))) | |
556 | (set (match_dup 0) | |
557 | (compare:CC (match_dup 2) | |
558 | (const_int 0)))] | |
559 | "") | |
51b8fc2c RK |
560 | |
561 | (define_insn "" | |
9ebbca7d GK |
562 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
563 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 564 | (const_int 0))) |
9ebbca7d | 565 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 566 | (zero_extend:DI (match_dup 1)))] |
58e09803 | 567 | "TARGET_POWERPC64" |
9ebbca7d GK |
568 | "@ |
569 | rldicl. %0,%1,0,56 | |
570 | #" | |
571 | [(set_attr "type" "compare") | |
572 | (set_attr "length" "4,8")]) | |
573 | ||
574 | (define_split | |
575 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
576 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
577 | (const_int 0))) | |
578 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
579 | (zero_extend:DI (match_dup 1)))] | |
580 | "TARGET_POWERPC64 && reload_completed" | |
581 | [(set (match_dup 0) | |
582 | (zero_extend:DI (match_dup 1))) | |
583 | (set (match_dup 2) | |
584 | (compare:CC (match_dup 0) | |
585 | (const_int 0)))] | |
586 | "") | |
51b8fc2c | 587 | |
2bee0449 RK |
588 | (define_insn "extendqidi2" |
589 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
590 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 591 | "TARGET_POWERPC64" |
2bee0449 | 592 | "extsb %0,%1") |
51b8fc2c RK |
593 | |
594 | (define_insn "" | |
9ebbca7d GK |
595 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
596 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 597 | (const_int 0))) |
9ebbca7d | 598 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 599 | "TARGET_POWERPC64" |
9ebbca7d GK |
600 | "@ |
601 | extsb. %2,%1 | |
602 | #" | |
603 | [(set_attr "type" "compare") | |
604 | (set_attr "length" "4,8")]) | |
605 | ||
606 | (define_split | |
607 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
608 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
609 | (const_int 0))) | |
610 | (clobber (match_scratch:DI 2 ""))] | |
611 | "TARGET_POWERPC64 && reload_completed" | |
612 | [(set (match_dup 2) | |
613 | (sign_extend:DI (match_dup 1))) | |
614 | (set (match_dup 0) | |
615 | (compare:CC (match_dup 2) | |
616 | (const_int 0)))] | |
617 | "") | |
51b8fc2c RK |
618 | |
619 | (define_insn "" | |
9ebbca7d GK |
620 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
621 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 622 | (const_int 0))) |
9ebbca7d | 623 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
624 | (sign_extend:DI (match_dup 1)))] |
625 | "TARGET_POWERPC64" | |
9ebbca7d GK |
626 | "@ |
627 | extsb. %0,%1 | |
628 | #" | |
629 | [(set_attr "type" "compare") | |
630 | (set_attr "length" "4,8")]) | |
631 | ||
632 | (define_split | |
633 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
634 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
635 | (const_int 0))) | |
636 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
637 | (sign_extend:DI (match_dup 1)))] | |
638 | "TARGET_POWERPC64 && reload_completed" | |
639 | [(set (match_dup 0) | |
640 | (sign_extend:DI (match_dup 1))) | |
641 | (set (match_dup 2) | |
642 | (compare:CC (match_dup 0) | |
643 | (const_int 0)))] | |
644 | "") | |
51b8fc2c RK |
645 | |
646 | (define_expand "zero_extendhidi2" | |
647 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
648 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
649 | "TARGET_POWERPC64" | |
650 | "") | |
651 | ||
652 | (define_insn "" | |
653 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
654 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
655 | "TARGET_POWERPC64" | |
656 | "@ | |
657 | lhz%U1%X1 %0,%1 | |
4371f8af | 658 | rldicl %0,%1,0,48" |
51b8fc2c RK |
659 | [(set_attr "type" "load,*")]) |
660 | ||
661 | (define_insn "" | |
9ebbca7d GK |
662 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
663 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 664 | (const_int 0))) |
9ebbca7d | 665 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 666 | "TARGET_POWERPC64" |
9ebbca7d GK |
667 | "@ |
668 | rldicl. %2,%1,0,48 | |
669 | #" | |
670 | [(set_attr "type" "compare") | |
671 | (set_attr "length" "4,8")]) | |
672 | ||
673 | (define_split | |
674 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
675 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
676 | (const_int 0))) | |
677 | (clobber (match_scratch:DI 2 ""))] | |
678 | "TARGET_POWERPC64 && reload_completed" | |
679 | [(set (match_dup 2) | |
680 | (zero_extend:DI (match_dup 1))) | |
681 | (set (match_dup 0) | |
682 | (compare:CC (match_dup 2) | |
683 | (const_int 0)))] | |
684 | "") | |
51b8fc2c RK |
685 | |
686 | (define_insn "" | |
9ebbca7d GK |
687 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
688 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 689 | (const_int 0))) |
9ebbca7d | 690 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
691 | (zero_extend:DI (match_dup 1)))] |
692 | "TARGET_POWERPC64" | |
9ebbca7d GK |
693 | "@ |
694 | rldicl. %0,%1,0,48 | |
695 | #" | |
696 | [(set_attr "type" "compare") | |
697 | (set_attr "length" "4,8")]) | |
698 | ||
699 | (define_split | |
700 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
701 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
702 | (const_int 0))) | |
703 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
704 | (zero_extend:DI (match_dup 1)))] | |
705 | "TARGET_POWERPC64 && reload_completed" | |
706 | [(set (match_dup 0) | |
707 | (zero_extend:DI (match_dup 1))) | |
708 | (set (match_dup 2) | |
709 | (compare:CC (match_dup 0) | |
710 | (const_int 0)))] | |
711 | "") | |
51b8fc2c RK |
712 | |
713 | (define_expand "extendhidi2" | |
714 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
715 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
716 | "TARGET_POWERPC64" | |
717 | "") | |
718 | ||
719 | (define_insn "" | |
720 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
721 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
722 | "TARGET_POWERPC64" | |
723 | "@ | |
724 | lha%U1%X1 %0,%1 | |
725 | extsh %0,%1" | |
726 | [(set_attr "type" "load,*")]) | |
727 | ||
728 | (define_insn "" | |
9ebbca7d GK |
729 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
730 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 731 | (const_int 0))) |
9ebbca7d | 732 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 733 | "TARGET_POWERPC64" |
9ebbca7d GK |
734 | "@ |
735 | extsh. %2,%1 | |
736 | #" | |
737 | [(set_attr "type" "compare") | |
738 | (set_attr "length" "4,8")]) | |
739 | ||
740 | (define_split | |
741 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
742 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
743 | (const_int 0))) | |
744 | (clobber (match_scratch:DI 2 ""))] | |
745 | "TARGET_POWERPC64 && reload_completed" | |
746 | [(set (match_dup 2) | |
747 | (sign_extend:DI (match_dup 1))) | |
748 | (set (match_dup 0) | |
749 | (compare:CC (match_dup 2) | |
750 | (const_int 0)))] | |
751 | "") | |
51b8fc2c RK |
752 | |
753 | (define_insn "" | |
9ebbca7d GK |
754 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
755 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 756 | (const_int 0))) |
9ebbca7d | 757 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
758 | (sign_extend:DI (match_dup 1)))] |
759 | "TARGET_POWERPC64" | |
9ebbca7d GK |
760 | "@ |
761 | extsh. %0,%1 | |
762 | #" | |
763 | [(set_attr "type" "compare") | |
764 | (set_attr "length" "4,8")]) | |
765 | ||
766 | (define_split | |
767 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
768 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
769 | (const_int 0))) | |
770 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
771 | (sign_extend:DI (match_dup 1)))] | |
772 | "TARGET_POWERPC64 && reload_completed" | |
773 | [(set (match_dup 0) | |
774 | (sign_extend:DI (match_dup 1))) | |
775 | (set (match_dup 2) | |
776 | (compare:CC (match_dup 0) | |
777 | (const_int 0)))] | |
778 | "") | |
51b8fc2c RK |
779 | |
780 | (define_expand "zero_extendsidi2" | |
781 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
782 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
783 | "TARGET_POWERPC64" | |
784 | "") | |
785 | ||
786 | (define_insn "" | |
787 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
788 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
789 | "TARGET_POWERPC64" | |
790 | "@ | |
791 | lwz%U1%X1 %0,%1 | |
792 | rldicl %0,%1,0,32" | |
793 | [(set_attr "type" "load,*")]) | |
794 | ||
795 | (define_insn "" | |
9ebbca7d GK |
796 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
797 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 798 | (const_int 0))) |
9ebbca7d | 799 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 800 | "TARGET_POWERPC64" |
9ebbca7d GK |
801 | "@ |
802 | rldicl. %2,%1,0,32 | |
803 | #" | |
804 | [(set_attr "type" "compare") | |
805 | (set_attr "length" "4,8")]) | |
806 | ||
807 | (define_split | |
808 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
809 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
810 | (const_int 0))) | |
811 | (clobber (match_scratch:DI 2 ""))] | |
812 | "TARGET_POWERPC64 && reload_completed" | |
813 | [(set (match_dup 2) | |
814 | (zero_extend:DI (match_dup 1))) | |
815 | (set (match_dup 0) | |
816 | (compare:CC (match_dup 2) | |
817 | (const_int 0)))] | |
818 | "") | |
51b8fc2c RK |
819 | |
820 | (define_insn "" | |
9ebbca7d GK |
821 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
822 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 823 | (const_int 0))) |
9ebbca7d | 824 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
825 | (zero_extend:DI (match_dup 1)))] |
826 | "TARGET_POWERPC64" | |
9ebbca7d GK |
827 | "@ |
828 | rldicl. %0,%1,0,32 | |
829 | #" | |
830 | [(set_attr "type" "compare") | |
831 | (set_attr "length" "4,8")]) | |
832 | ||
833 | (define_split | |
834 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
835 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
836 | (const_int 0))) | |
837 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
838 | (zero_extend:DI (match_dup 1)))] | |
839 | "TARGET_POWERPC64 && reload_completed" | |
840 | [(set (match_dup 0) | |
841 | (zero_extend:DI (match_dup 1))) | |
842 | (set (match_dup 2) | |
843 | (compare:CC (match_dup 0) | |
844 | (const_int 0)))] | |
845 | "") | |
51b8fc2c RK |
846 | |
847 | (define_expand "extendsidi2" | |
848 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
849 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
850 | "TARGET_POWERPC64" | |
851 | "") | |
852 | ||
853 | (define_insn "" | |
854 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 855 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
856 | "TARGET_POWERPC64" |
857 | "@ | |
858 | lwa%U1%X1 %0,%1 | |
859 | extsw %0,%1" | |
860 | [(set_attr "type" "load,*")]) | |
861 | ||
862 | (define_insn "" | |
9ebbca7d GK |
863 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
864 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 865 | (const_int 0))) |
9ebbca7d | 866 | (clobber (match_scratch:DI 2 "=r,r"))] |
51b8fc2c | 867 | "TARGET_POWERPC64" |
9ebbca7d GK |
868 | "@ |
869 | extsw. %2,%1 | |
870 | #" | |
871 | [(set_attr "type" "compare") | |
872 | (set_attr "length" "4,8")]) | |
873 | ||
874 | (define_split | |
875 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
876 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
877 | (const_int 0))) | |
878 | (clobber (match_scratch:DI 2 ""))] | |
879 | "TARGET_POWERPC64 && reload_completed" | |
880 | [(set (match_dup 2) | |
881 | (sign_extend:DI (match_dup 1))) | |
882 | (set (match_dup 0) | |
883 | (compare:CC (match_dup 2) | |
884 | (const_int 0)))] | |
885 | "") | |
51b8fc2c RK |
886 | |
887 | (define_insn "" | |
9ebbca7d GK |
888 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
889 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 890 | (const_int 0))) |
9ebbca7d | 891 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
892 | (sign_extend:DI (match_dup 1)))] |
893 | "TARGET_POWERPC64" | |
9ebbca7d GK |
894 | "@ |
895 | extsw. %0,%1 | |
896 | #" | |
897 | [(set_attr "type" "compare") | |
898 | (set_attr "length" "4,8")]) | |
899 | ||
900 | (define_split | |
901 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
902 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
903 | (const_int 0))) | |
904 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
905 | (sign_extend:DI (match_dup 1)))] | |
906 | "TARGET_POWERPC64 && reload_completed" | |
907 | [(set (match_dup 0) | |
908 | (sign_extend:DI (match_dup 1))) | |
909 | (set (match_dup 2) | |
910 | (compare:CC (match_dup 0) | |
911 | (const_int 0)))] | |
912 | "") | |
51b8fc2c | 913 | |
1fd4e8c1 | 914 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
915 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
916 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
917 | "" |
918 | "") | |
919 | ||
920 | (define_insn "" | |
cd2b37d9 | 921 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
922 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
923 | "" | |
924 | "@ | |
925 | lbz%U1%X1 %0,%1 | |
005a35b9 | 926 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
927 | [(set_attr "type" "load,*")]) |
928 | ||
929 | (define_insn "" | |
9ebbca7d GK |
930 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
931 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 932 | (const_int 0))) |
9ebbca7d | 933 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 934 | "" |
9ebbca7d GK |
935 | "@ |
936 | {andil.|andi.} %2,%1,0xff | |
937 | #" | |
938 | [(set_attr "type" "compare") | |
939 | (set_attr "length" "4,8")]) | |
940 | ||
941 | (define_split | |
942 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
943 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
944 | (const_int 0))) | |
945 | (clobber (match_scratch:SI 2 ""))] | |
946 | "reload_completed" | |
947 | [(set (match_dup 2) | |
948 | (zero_extend:SI (match_dup 1))) | |
949 | (set (match_dup 0) | |
950 | (compare:CC (match_dup 2) | |
951 | (const_int 0)))] | |
952 | "") | |
1fd4e8c1 RK |
953 | |
954 | (define_insn "" | |
9ebbca7d GK |
955 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
956 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 957 | (const_int 0))) |
9ebbca7d | 958 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
959 | (zero_extend:SI (match_dup 1)))] |
960 | "" | |
9ebbca7d GK |
961 | "@ |
962 | {andil.|andi.} %0,%1,0xff | |
963 | #" | |
964 | [(set_attr "type" "compare") | |
965 | (set_attr "length" "4,8")]) | |
966 | ||
967 | (define_split | |
968 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
969 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
970 | (const_int 0))) | |
971 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
972 | (zero_extend:SI (match_dup 1)))] | |
973 | "reload_completed" | |
974 | [(set (match_dup 0) | |
975 | (zero_extend:SI (match_dup 1))) | |
976 | (set (match_dup 2) | |
977 | (compare:CC (match_dup 0) | |
978 | (const_int 0)))] | |
979 | "") | |
1fd4e8c1 | 980 | |
51b8fc2c RK |
981 | (define_expand "extendqisi2" |
982 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
983 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
984 | "" | |
985 | " | |
986 | { | |
987 | if (TARGET_POWERPC) | |
988 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
989 | else if (TARGET_POWER) | |
990 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
991 | else | |
992 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
993 | DONE; | |
994 | }") | |
995 | ||
996 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
997 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
998 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 999 | "TARGET_POWERPC" |
2bee0449 | 1000 | "extsb %0,%1") |
51b8fc2c RK |
1001 | |
1002 | (define_insn "" | |
9ebbca7d GK |
1003 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1004 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1005 | (const_int 0))) |
9ebbca7d | 1006 | (clobber (match_scratch:SI 2 "=r,r"))] |
51b8fc2c | 1007 | "TARGET_POWERPC" |
9ebbca7d GK |
1008 | "@ |
1009 | extsb. %2,%1 | |
1010 | #" | |
1011 | [(set_attr "type" "compare") | |
1012 | (set_attr "length" "4,8")]) | |
1013 | ||
1014 | (define_split | |
1015 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1016 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1017 | (const_int 0))) | |
1018 | (clobber (match_scratch:SI 2 ""))] | |
1019 | "TARGET_POWERPC && reload_completed" | |
1020 | [(set (match_dup 2) | |
1021 | (sign_extend:SI (match_dup 1))) | |
1022 | (set (match_dup 0) | |
1023 | (compare:CC (match_dup 2) | |
1024 | (const_int 0)))] | |
1025 | "") | |
51b8fc2c RK |
1026 | |
1027 | (define_insn "" | |
9ebbca7d GK |
1028 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1029 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1030 | (const_int 0))) |
9ebbca7d | 1031 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1032 | (sign_extend:SI (match_dup 1)))] |
1033 | "TARGET_POWERPC" | |
9ebbca7d GK |
1034 | "@ |
1035 | extsb. %0,%1 | |
1036 | #" | |
1037 | [(set_attr "type" "compare") | |
1038 | (set_attr "length" "4,8")]) | |
1039 | ||
1040 | (define_split | |
1041 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1042 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1043 | (const_int 0))) | |
1044 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1045 | (sign_extend:SI (match_dup 1)))] | |
1046 | "TARGET_POWERPC && reload_completed" | |
1047 | [(set (match_dup 0) | |
1048 | (sign_extend:SI (match_dup 1))) | |
1049 | (set (match_dup 2) | |
1050 | (compare:CC (match_dup 0) | |
1051 | (const_int 0)))] | |
1052 | "") | |
51b8fc2c RK |
1053 | |
1054 | (define_expand "extendqisi2_power" | |
1055 | [(parallel [(set (match_dup 2) | |
1056 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1057 | (const_int 24))) | |
1058 | (clobber (scratch:SI))]) | |
1059 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1060 | (ashiftrt:SI (match_dup 2) | |
1061 | (const_int 24))) | |
1062 | (clobber (scratch:SI))])] | |
1063 | "TARGET_POWER" | |
1064 | " | |
1065 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
1066 | operands[2] = gen_reg_rtx (SImode); }") | |
1067 | ||
1068 | (define_expand "extendqisi2_no_power" | |
1069 | [(set (match_dup 2) | |
1070 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1071 | (const_int 24))) | |
1072 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1073 | (ashiftrt:SI (match_dup 2) | |
1074 | (const_int 24)))] | |
1075 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1076 | " | |
1077 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
1078 | operands[2] = gen_reg_rtx (SImode); }") | |
1079 | ||
1fd4e8c1 | 1080 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
1081 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
1082 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1083 | "" |
1084 | "") | |
1085 | ||
1086 | (define_insn "" | |
cd2b37d9 | 1087 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1088 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
1089 | "" | |
1090 | "@ | |
1091 | lbz%U1%X1 %0,%1 | |
005a35b9 | 1092 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
1093 | [(set_attr "type" "load,*")]) |
1094 | ||
1095 | (define_insn "" | |
9ebbca7d GK |
1096 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1097 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1098 | (const_int 0))) |
9ebbca7d | 1099 | (clobber (match_scratch:HI 2 "=r,r"))] |
51b8fc2c | 1100 | "" |
9ebbca7d GK |
1101 | "@ |
1102 | {andil.|andi.} %2,%1,0xff | |
1103 | #" | |
1104 | [(set_attr "type" "compare") | |
1105 | (set_attr "length" "4,8")]) | |
1106 | ||
1107 | (define_split | |
1108 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1109 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1110 | (const_int 0))) | |
1111 | (clobber (match_scratch:HI 2 ""))] | |
1112 | "reload_completed" | |
1113 | [(set (match_dup 2) | |
1114 | (zero_extend:HI (match_dup 1))) | |
1115 | (set (match_dup 0) | |
1116 | (compare:CC (match_dup 2) | |
1117 | (const_int 0)))] | |
1118 | "") | |
1fd4e8c1 | 1119 | |
51b8fc2c | 1120 | (define_insn "" |
9ebbca7d GK |
1121 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1122 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1123 | (const_int 0))) |
9ebbca7d | 1124 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
1125 | (zero_extend:HI (match_dup 1)))] |
1126 | "" | |
9ebbca7d GK |
1127 | "@ |
1128 | {andil.|andi.} %0,%1,0xff | |
1129 | #" | |
1130 | [(set_attr "type" "compare") | |
1131 | (set_attr "length" "4,8")]) | |
1132 | ||
1133 | (define_split | |
1134 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1135 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1136 | (const_int 0))) | |
1137 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1138 | (zero_extend:HI (match_dup 1)))] | |
1139 | "reload_completed" | |
1140 | [(set (match_dup 0) | |
1141 | (zero_extend:HI (match_dup 1))) | |
1142 | (set (match_dup 2) | |
1143 | (compare:CC (match_dup 0) | |
1144 | (const_int 0)))] | |
1145 | "") | |
815cdc52 MM |
1146 | |
1147 | (define_expand "extendqihi2" | |
1148 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
1149 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
1150 | "" | |
1151 | " | |
1152 | { | |
1153 | if (TARGET_POWERPC) | |
1154 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
1155 | else if (TARGET_POWER) | |
1156 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
1157 | else | |
1158 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
1159 | DONE; | |
1160 | }") | |
1161 | ||
1162 | (define_insn "extendqihi2_ppc" | |
1163 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
1164 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
1165 | "TARGET_POWERPC" | |
1166 | "extsb %0,%1") | |
1167 | ||
1168 | (define_insn "" | |
9ebbca7d GK |
1169 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1170 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1171 | (const_int 0))) |
9ebbca7d | 1172 | (clobber (match_scratch:HI 2 "=r,r"))] |
815cdc52 | 1173 | "TARGET_POWERPC" |
9ebbca7d GK |
1174 | "@ |
1175 | extsb. %2,%1 | |
1176 | #" | |
1177 | [(set_attr "type" "compare") | |
1178 | (set_attr "length" "4,8")]) | |
1179 | ||
1180 | (define_split | |
1181 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1182 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1183 | (const_int 0))) | |
1184 | (clobber (match_scratch:HI 2 ""))] | |
1185 | "TARGET_POWERPC && reload_completed" | |
1186 | [(set (match_dup 2) | |
1187 | (sign_extend:HI (match_dup 1))) | |
1188 | (set (match_dup 0) | |
1189 | (compare:CC (match_dup 2) | |
1190 | (const_int 0)))] | |
1191 | "") | |
815cdc52 MM |
1192 | |
1193 | (define_insn "" | |
9ebbca7d GK |
1194 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1195 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 1196 | (const_int 0))) |
9ebbca7d | 1197 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
1198 | (sign_extend:HI (match_dup 1)))] |
1199 | "TARGET_POWERPC" | |
9ebbca7d GK |
1200 | "@ |
1201 | extsb. %0,%1 | |
1202 | #" | |
1203 | [(set_attr "type" "compare") | |
1204 | (set_attr "length" "4,8")]) | |
1205 | ||
1206 | (define_split | |
1207 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1208 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
1209 | (const_int 0))) | |
1210 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1211 | (sign_extend:HI (match_dup 1)))] | |
1212 | "TARGET_POWERPC && reload_completed" | |
1213 | [(set (match_dup 0) | |
1214 | (sign_extend:HI (match_dup 1))) | |
1215 | (set (match_dup 2) | |
1216 | (compare:CC (match_dup 0) | |
1217 | (const_int 0)))] | |
1218 | "") | |
51b8fc2c RK |
1219 | |
1220 | (define_expand "extendqihi2_power" | |
1221 | [(parallel [(set (match_dup 2) | |
1222 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1223 | (const_int 24))) | |
1224 | (clobber (scratch:SI))]) | |
1225 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
1226 | (ashiftrt:SI (match_dup 2) | |
1227 | (const_int 24))) | |
1228 | (clobber (scratch:SI))])] | |
1229 | "TARGET_POWER" | |
1230 | " | |
1231 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
1232 | operands[1] = gen_lowpart (SImode, operands[1]); | |
1233 | operands[2] = gen_reg_rtx (SImode); }") | |
1234 | ||
1235 | (define_expand "extendqihi2_no_power" | |
1236 | [(set (match_dup 2) | |
1237 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
1238 | (const_int 24))) | |
1239 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
1240 | (ashiftrt:SI (match_dup 2) | |
1241 | (const_int 24)))] | |
1242 | "! TARGET_POWER && ! TARGET_POWERPC" | |
1243 | " | |
1244 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
1245 | operands[1] = gen_lowpart (SImode, operands[1]); | |
1246 | operands[2] = gen_reg_rtx (SImode); }") | |
1247 | ||
1fd4e8c1 | 1248 | (define_expand "zero_extendhisi2" |
5f243543 | 1249 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 1250 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
1251 | "" |
1252 | "") | |
1253 | ||
1254 | (define_insn "" | |
cd2b37d9 | 1255 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1256 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
1257 | "" | |
1258 | "@ | |
1259 | lhz%U1%X1 %0,%1 | |
005a35b9 | 1260 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
1261 | [(set_attr "type" "load,*")]) |
1262 | ||
1263 | (define_insn "" | |
9ebbca7d GK |
1264 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1265 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1266 | (const_int 0))) |
9ebbca7d | 1267 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 1268 | "" |
9ebbca7d GK |
1269 | "@ |
1270 | {andil.|andi.} %2,%1,0xffff | |
1271 | #" | |
1272 | [(set_attr "type" "compare") | |
1273 | (set_attr "length" "4,8")]) | |
1274 | ||
1275 | (define_split | |
1276 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1277 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1278 | (const_int 0))) | |
1279 | (clobber (match_scratch:SI 2 ""))] | |
1280 | "reload_completed" | |
1281 | [(set (match_dup 2) | |
1282 | (zero_extend:SI (match_dup 1))) | |
1283 | (set (match_dup 0) | |
1284 | (compare:CC (match_dup 2) | |
1285 | (const_int 0)))] | |
1286 | "") | |
1fd4e8c1 RK |
1287 | |
1288 | (define_insn "" | |
9ebbca7d GK |
1289 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1290 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1291 | (const_int 0))) |
9ebbca7d | 1292 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1293 | (zero_extend:SI (match_dup 1)))] |
1294 | "" | |
9ebbca7d GK |
1295 | "@ |
1296 | {andil.|andi.} %0,%1,0xffff | |
1297 | #" | |
1298 | [(set_attr "type" "compare") | |
1299 | (set_attr "length" "4,8")]) | |
1300 | ||
1301 | (define_split | |
1302 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1303 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1304 | (const_int 0))) | |
1305 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1306 | (zero_extend:SI (match_dup 1)))] | |
1307 | "reload_completed" | |
1308 | [(set (match_dup 0) | |
1309 | (zero_extend:SI (match_dup 1))) | |
1310 | (set (match_dup 2) | |
1311 | (compare:CC (match_dup 0) | |
1312 | (const_int 0)))] | |
1313 | "") | |
1fd4e8c1 RK |
1314 | |
1315 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
1316 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1317 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
1318 | "" |
1319 | "") | |
1320 | ||
1321 | (define_insn "" | |
cd2b37d9 | 1322 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1323 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
1324 | "" | |
1325 | "@ | |
1326 | lha%U1%X1 %0,%1 | |
ca7f5001 | 1327 | {exts|extsh} %0,%1" |
1fd4e8c1 RK |
1328 | [(set_attr "type" "load,*")]) |
1329 | ||
1330 | (define_insn "" | |
9ebbca7d GK |
1331 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1332 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1333 | (const_int 0))) |
9ebbca7d | 1334 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 1335 | "" |
9ebbca7d GK |
1336 | "@ |
1337 | {exts.|extsh.} %2,%1 | |
1338 | #" | |
1339 | [(set_attr "type" "compare") | |
1340 | (set_attr "length" "4,8")]) | |
1341 | ||
1342 | (define_split | |
1343 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1344 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1345 | (const_int 0))) | |
1346 | (clobber (match_scratch:SI 2 ""))] | |
1347 | "reload_completed" | |
1348 | [(set (match_dup 2) | |
1349 | (sign_extend:SI (match_dup 1))) | |
1350 | (set (match_dup 0) | |
1351 | (compare:CC (match_dup 2) | |
1352 | (const_int 0)))] | |
1353 | "") | |
1fd4e8c1 RK |
1354 | |
1355 | (define_insn "" | |
9ebbca7d GK |
1356 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1357 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1358 | (const_int 0))) |
9ebbca7d | 1359 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1360 | (sign_extend:SI (match_dup 1)))] |
1361 | "" | |
9ebbca7d GK |
1362 | "@ |
1363 | {exts.|extsh.} %0,%1 | |
1364 | #" | |
1365 | [(set_attr "type" "compare") | |
1366 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1367 | \f |
9ebbca7d GK |
1368 | (define_split |
1369 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1370 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1371 | (const_int 0))) | |
1372 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1373 | (sign_extend:SI (match_dup 1)))] | |
1374 | "reload_completed" | |
1375 | [(set (match_dup 0) | |
1376 | (sign_extend:SI (match_dup 1))) | |
1377 | (set (match_dup 2) | |
1378 | (compare:CC (match_dup 0) | |
1379 | (const_int 0)))] | |
1380 | "") | |
1381 | ||
1fd4e8c1 | 1382 | ;; Fixed-point arithmetic insns. |
deb9225a RK |
1383 | |
1384 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
1385 | ;; allowing register zero as source. | |
7cd5235b MM |
1386 | (define_expand "addsi3" |
1387 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1388 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1389 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
1390 | "" | |
1391 | " | |
1392 | { | |
677a9668 DE |
1393 | if (GET_CODE (operands[2]) == CONST_INT |
1394 | && ! add_operand (operands[2], SImode)) | |
7cd5235b | 1395 | { |
677a9668 | 1396 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
1397 | ? operands[0] : gen_reg_rtx (SImode)); |
1398 | ||
1399 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; | |
1400 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
1401 | ||
1402 | if (low & 0x8000) | |
1403 | high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16; | |
1404 | ||
9ebbca7d GK |
1405 | /* The ordering here is important for the prolog expander. |
1406 | When space is allocated from the stack, adding 'low' first may | |
1407 | produce a temporary deallocation (which would be bad). */ | |
7cd5235b MM |
1408 | emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (high))); |
1409 | emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); | |
1410 | DONE; | |
1411 | } | |
1412 | }") | |
1413 | ||
1414 | (define_insn "*addsi3_internal1" | |
1415 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") | |
1416 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 1417 | (match_operand:SI 2 "add_operand" "r,I,I,L")))] |
1fd4e8c1 RK |
1418 | "" |
1419 | "@ | |
deb9225a RK |
1420 | {cax|add} %0,%1,%2 |
1421 | {cal %0,%2(%1)|addi %0,%1,%2} | |
1422 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
1423 | {cau|addis} %0,%1,%v2" |
1424 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 1425 | |
7cd5235b | 1426 | (define_insn "*addsi3_internal2" |
cb8cc086 MM |
1427 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1428 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1429 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1430 | (const_int 0))) |
cb8cc086 | 1431 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] |
0ad91047 | 1432 | "! TARGET_POWERPC64" |
deb9225a RK |
1433 | "@ |
1434 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
1435 | {ai.|addic.} %3,%1,%2 |
1436 | # | |
1437 | #" | |
1438 | [(set_attr "type" "compare") | |
1439 | (set_attr "length" "4,4,8,8")]) | |
1440 | ||
1441 | (define_split | |
1442 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1443 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1444 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1445 | (const_int 0))) | |
1446 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1447 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1448 | [(set (match_dup 3) |
1449 | (plus:SI (match_dup 1) | |
1450 | (match_dup 2))) | |
1451 | (set (match_dup 0) | |
1452 | (compare:CC (match_dup 3) | |
1453 | (const_int 0)))] | |
1454 | "") | |
7e69e155 | 1455 | |
7cd5235b | 1456 | (define_insn "*addsi3_internal3" |
cb8cc086 MM |
1457 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1458 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1459 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1460 | (const_int 0))) |
cb8cc086 MM |
1461 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1462 | (plus:SI (match_dup 1) | |
1463 | (match_dup 2)))] | |
0ad91047 | 1464 | "! TARGET_POWERPC64" |
deb9225a RK |
1465 | "@ |
1466 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
1467 | {ai.|addic.} %0,%1,%2 |
1468 | # | |
1469 | #" | |
1470 | [(set_attr "type" "compare") | |
1471 | (set_attr "length" "4,4,8,8")]) | |
1472 | ||
1473 | (define_split | |
1474 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1475 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1476 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1477 | (const_int 0))) | |
1478 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1479 | (plus:SI (match_dup 1) (match_dup 2)))] | |
0ad91047 | 1480 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1481 | [(set (match_dup 0) |
1482 | (plus:SI (match_dup 1) | |
1483 | (match_dup 2))) | |
1484 | (set (match_dup 3) | |
1485 | (compare:CC (match_dup 0) | |
1486 | (const_int 0)))] | |
1487 | "") | |
7e69e155 | 1488 | |
f357808b RK |
1489 | ;; Split an add that we can't do in one insn into two insns, each of which |
1490 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
1491 | ;; add should be last in case the result gets used in an address. | |
1492 | ||
1493 | (define_split | |
cd2b37d9 RK |
1494 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1495 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 1496 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
1fd4e8c1 | 1497 | "" |
f357808b RK |
1498 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
1499 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
1500 | " | |
1fd4e8c1 | 1501 | { |
e6ca2c17 DE |
1502 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; |
1503 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
1fd4e8c1 | 1504 | |
f357808b | 1505 | if (low & 0x8000) |
e6ca2c17 | 1506 | high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16; |
1fd4e8c1 | 1507 | |
e6ca2c17 DE |
1508 | operands[3] = GEN_INT (high); |
1509 | operands[4] = GEN_INT (low); | |
1fd4e8c1 RK |
1510 | }") |
1511 | ||
8de2a197 | 1512 | (define_insn "one_cmplsi2" |
cd2b37d9 RK |
1513 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1514 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1515 | "" |
ca7f5001 RK |
1516 | "nor %0,%1,%1") |
1517 | ||
1518 | (define_insn "" | |
52d3af72 DE |
1519 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1520 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1521 | (const_int 0))) |
52d3af72 | 1522 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 1523 | "! TARGET_POWERPC64" |
52d3af72 DE |
1524 | "@ |
1525 | nor. %2,%1,%1 | |
1526 | #" | |
1527 | [(set_attr "type" "compare") | |
1528 | (set_attr "length" "4,8")]) | |
1529 | ||
1530 | (define_split | |
1531 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1532 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1533 | (const_int 0))) | |
1534 | (clobber (match_scratch:SI 2 ""))] | |
0ad91047 | 1535 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1536 | [(set (match_dup 2) |
1537 | (not:SI (match_dup 1))) | |
1538 | (set (match_dup 0) | |
1539 | (compare:CC (match_dup 2) | |
1540 | (const_int 0)))] | |
1541 | "") | |
ca7f5001 RK |
1542 | |
1543 | (define_insn "" | |
52d3af72 DE |
1544 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1545 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1546 | (const_int 0))) |
52d3af72 | 1547 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1548 | (not:SI (match_dup 1)))] |
0ad91047 | 1549 | "! TARGET_POWERPC64" |
52d3af72 DE |
1550 | "@ |
1551 | nor. %0,%1,%1 | |
1552 | #" | |
1553 | [(set_attr "type" "compare") | |
1554 | (set_attr "length" "4,8")]) | |
1555 | ||
1556 | (define_split | |
1557 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1558 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1559 | (const_int 0))) | |
1560 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1561 | (not:SI (match_dup 1)))] | |
0ad91047 | 1562 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
1563 | [(set (match_dup 0) |
1564 | (not:SI (match_dup 1))) | |
1565 | (set (match_dup 2) | |
1566 | (compare:CC (match_dup 0) | |
1567 | (const_int 0)))] | |
1568 | "") | |
1fd4e8c1 RK |
1569 | |
1570 | (define_insn "" | |
3d91674b RK |
1571 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1572 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1573 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1574 | "! TARGET_POWERPC" |
ca7f5001 | 1575 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1576 | |
deb9225a RK |
1577 | (define_insn "" |
1578 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
1579 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") | |
1580 | (match_operand:SI 2 "gpc_reg_operand" "r,r")))] | |
1581 | "TARGET_POWERPC" | |
1582 | "@ | |
1583 | subf %0,%2,%1 | |
1584 | subfic %0,%2,%1") | |
1585 | ||
1fd4e8c1 | 1586 | (define_insn "" |
cb8cc086 MM |
1587 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1588 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1589 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1590 | (const_int 0))) |
cb8cc086 | 1591 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1592 | "! TARGET_POWERPC" |
cb8cc086 MM |
1593 | "@ |
1594 | {sf.|subfc.} %3,%2,%1 | |
1595 | #" | |
1596 | [(set_attr "type" "compare") | |
1597 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1598 | |
deb9225a | 1599 | (define_insn "" |
cb8cc086 MM |
1600 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1601 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1602 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1603 | (const_int 0))) |
cb8cc086 | 1604 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 1605 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
cb8cc086 MM |
1606 | "@ |
1607 | subf. %3,%2,%1 | |
1608 | #" | |
1609 | [(set_attr "type" "compare") | |
1610 | (set_attr "length" "4,8")]) | |
1611 | ||
1612 | (define_split | |
1613 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1614 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1615 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1616 | (const_int 0))) | |
1617 | (clobber (match_scratch:SI 3 ""))] | |
0ad91047 | 1618 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1619 | [(set (match_dup 3) |
1620 | (minus:SI (match_dup 1) | |
1621 | (match_dup 2))) | |
1622 | (set (match_dup 0) | |
1623 | (compare:CC (match_dup 3) | |
1624 | (const_int 0)))] | |
1625 | "") | |
deb9225a | 1626 | |
1fd4e8c1 | 1627 | (define_insn "" |
cb8cc086 MM |
1628 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1629 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1630 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1631 | (const_int 0))) |
cb8cc086 | 1632 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1633 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1634 | "! TARGET_POWERPC" |
cb8cc086 MM |
1635 | "@ |
1636 | {sf.|subfc.} %0,%2,%1 | |
1637 | #" | |
1638 | [(set_attr "type" "compare") | |
1639 | (set_attr "length" "4,8")]) | |
815cdc52 | 1640 | |
29ae5b89 | 1641 | (define_insn "" |
cb8cc086 MM |
1642 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1643 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1644 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1645 | (const_int 0))) |
cb8cc086 MM |
1646 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1647 | (minus:SI (match_dup 1) | |
1648 | (match_dup 2)))] | |
0ad91047 | 1649 | "TARGET_POWERPC && ! TARGET_POWERPC64" |
90612787 DE |
1650 | "@ |
1651 | subf. %0,%2,%1 | |
1652 | #" | |
cb8cc086 MM |
1653 | [(set_attr "type" "compare") |
1654 | (set_attr "length" "4,8")]) | |
1655 | ||
1656 | (define_split | |
1657 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1658 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1659 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1660 | (const_int 0))) | |
1661 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1662 | (minus:SI (match_dup 1) | |
1663 | (match_dup 2)))] | |
0ad91047 | 1664 | "! TARGET_POWERPC64 && reload_completed" |
cb8cc086 MM |
1665 | [(set (match_dup 0) |
1666 | (minus:SI (match_dup 1) | |
1667 | (match_dup 2))) | |
1668 | (set (match_dup 3) | |
1669 | (compare:CC (match_dup 0) | |
1670 | (const_int 0)))] | |
1671 | "") | |
deb9225a | 1672 | |
1fd4e8c1 | 1673 | (define_expand "subsi3" |
cd2b37d9 | 1674 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1675 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") |
1676 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
1677 | "" | |
a0044fb1 RK |
1678 | " |
1679 | { | |
1680 | if (GET_CODE (operands[2]) == CONST_INT) | |
1681 | { | |
1682 | emit_insn (gen_addsi3 (operands[0], operands[1], | |
1683 | negate_rtx (SImode, operands[2]))); | |
1684 | DONE; | |
1685 | } | |
1686 | }") | |
1fd4e8c1 RK |
1687 | |
1688 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
1689 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
1690 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
1691 | ;; combine. | |
1fd4e8c1 RK |
1692 | |
1693 | (define_expand "sminsi3" | |
1694 | [(set (match_dup 3) | |
cd2b37d9 | 1695 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1696 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1697 | (const_int 0) | |
1698 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1699 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1700 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 1701 | "TARGET_POWER" |
1fd4e8c1 RK |
1702 | " |
1703 | { operands[3] = gen_reg_rtx (SImode); }") | |
1704 | ||
95ac8e67 RK |
1705 | (define_split |
1706 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1707 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1708 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1709 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1710 | "TARGET_POWER" |
95ac8e67 RK |
1711 | [(set (match_dup 3) |
1712 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1713 | (const_int 0) | |
1714 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1715 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
1716 | "") | |
1717 | ||
1fd4e8c1 RK |
1718 | (define_expand "smaxsi3" |
1719 | [(set (match_dup 3) | |
cd2b37d9 | 1720 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1721 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1722 | (const_int 0) | |
1723 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1724 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1725 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 1726 | "TARGET_POWER" |
1fd4e8c1 RK |
1727 | " |
1728 | { operands[3] = gen_reg_rtx (SImode); }") | |
1729 | ||
95ac8e67 RK |
1730 | (define_split |
1731 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1732 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1733 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1734 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1735 | "TARGET_POWER" |
95ac8e67 RK |
1736 | [(set (match_dup 3) |
1737 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1738 | (const_int 0) | |
1739 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1740 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
1741 | "") | |
1742 | ||
1fd4e8c1 | 1743 | (define_expand "uminsi3" |
cd2b37d9 | 1744 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1745 | (match_dup 5))) |
cd2b37d9 | 1746 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1747 | (match_dup 5))) |
1fd4e8c1 RK |
1748 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1749 | (const_int 0) | |
1750 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1751 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1752 | (minus:SI (match_dup 2) (match_dup 3)))] |
ca7f5001 | 1753 | "TARGET_POWER" |
1fd4e8c1 | 1754 | " |
bb68ff55 MM |
1755 | { |
1756 | operands[3] = gen_reg_rtx (SImode); | |
1757 | operands[4] = gen_reg_rtx (SImode); | |
1758 | operands[5] = GEN_INT (-2147483647 - 1); | |
1759 | }") | |
1fd4e8c1 RK |
1760 | |
1761 | (define_expand "umaxsi3" | |
cd2b37d9 | 1762 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1763 | (match_dup 5))) |
cd2b37d9 | 1764 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1765 | (match_dup 5))) |
1fd4e8c1 RK |
1766 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1767 | (const_int 0) | |
1768 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1769 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1770 | (plus:SI (match_dup 3) (match_dup 1)))] |
ca7f5001 | 1771 | "TARGET_POWER" |
1fd4e8c1 | 1772 | " |
bb68ff55 MM |
1773 | { |
1774 | operands[3] = gen_reg_rtx (SImode); | |
1775 | operands[4] = gen_reg_rtx (SImode); | |
1776 | operands[5] = GEN_INT (-2147483647 - 1); | |
1777 | }") | |
1fd4e8c1 RK |
1778 | |
1779 | (define_insn "" | |
cd2b37d9 RK |
1780 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1781 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 1782 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
1783 | (const_int 0) |
1784 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1785 | "TARGET_POWER" |
1fd4e8c1 RK |
1786 | "doz%I2 %0,%1,%2") |
1787 | ||
1788 | (define_insn "" | |
9ebbca7d | 1789 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1790 | (compare:CC |
9ebbca7d GK |
1791 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1792 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1793 | (const_int 0) |
1794 | (minus:SI (match_dup 2) (match_dup 1))) | |
1795 | (const_int 0))) | |
9ebbca7d | 1796 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 1797 | "TARGET_POWER" |
9ebbca7d GK |
1798 | "@ |
1799 | doz%I2. %3,%1,%2 | |
1800 | #" | |
1801 | [(set_attr "type" "delayed_compare") | |
1802 | (set_attr "length" "4,8")]) | |
1803 | ||
1804 | (define_split | |
1805 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1806 | (compare:CC | |
1807 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1808 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1809 | (const_int 0) | |
1810 | (minus:SI (match_dup 2) (match_dup 1))) | |
1811 | (const_int 0))) | |
1812 | (clobber (match_scratch:SI 3 ""))] | |
1813 | "TARGET_POWER && reload_completed" | |
1814 | [(set (match_dup 3) | |
1815 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1816 | (const_int 0) | |
1817 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1818 | (set (match_dup 0) | |
1819 | (compare:CC (match_dup 3) | |
1820 | (const_int 0)))] | |
1821 | "") | |
1fd4e8c1 RK |
1822 | |
1823 | (define_insn "" | |
9ebbca7d | 1824 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1825 | (compare:CC |
9ebbca7d GK |
1826 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1827 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1828 | (const_int 0) |
1829 | (minus:SI (match_dup 2) (match_dup 1))) | |
1830 | (const_int 0))) | |
9ebbca7d | 1831 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1832 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
1833 | (const_int 0) | |
1834 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1835 | "TARGET_POWER" |
9ebbca7d GK |
1836 | "@ |
1837 | doz%I2. %0,%1,%2 | |
1838 | #" | |
1839 | [(set_attr "type" "delayed_compare") | |
1840 | (set_attr "length" "4,8")]) | |
1841 | ||
1842 | (define_split | |
1843 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1844 | (compare:CC | |
1845 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1846 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1847 | (const_int 0) | |
1848 | (minus:SI (match_dup 2) (match_dup 1))) | |
1849 | (const_int 0))) | |
1850 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1851 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1852 | (const_int 0) | |
1853 | (minus:SI (match_dup 2) (match_dup 1))))] | |
1854 | "TARGET_POWER && reload_completed" | |
1855 | [(set (match_dup 0) | |
1856 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1857 | (const_int 0) | |
1858 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1859 | (set (match_dup 3) | |
1860 | (compare:CC (match_dup 0) | |
1861 | (const_int 0)))] | |
1862 | "") | |
1fd4e8c1 RK |
1863 | |
1864 | ;; We don't need abs with condition code because such comparisons should | |
1865 | ;; never be done. | |
ea9be077 MM |
1866 | (define_expand "abssi2" |
1867 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1868 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1869 | "" | |
1870 | " | |
1871 | { | |
0ad91047 | 1872 | if (! TARGET_POWER) |
ea9be077 MM |
1873 | { |
1874 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
1875 | DONE; | |
1876 | } | |
1877 | }") | |
1878 | ||
1879 | (define_insn "abssi2_power" | |
cd2b37d9 RK |
1880 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1881 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 1882 | "TARGET_POWER" |
1fd4e8c1 RK |
1883 | "abs %0,%1") |
1884 | ||
ea9be077 MM |
1885 | (define_insn "abssi2_nopower" |
1886 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1887 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) | |
1888 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 1889 | "! TARGET_POWER" |
3595d104 MM |
1890 | "* |
1891 | { | |
1892 | return (TARGET_POWERPC) | |
1893 | ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\" | |
1894 | : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\"; | |
1895 | }" | |
ea9be077 MM |
1896 | [(set_attr "length" "12")]) |
1897 | ||
1898 | (define_split | |
1899 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1900 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) | |
1901 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 1902 | "! TARGET_POWER && reload_completed" |
ea9be077 MM |
1903 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1904 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1905 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
1906 | "") |
1907 | ||
463b558b | 1908 | (define_insn "*nabs_power" |
cd2b37d9 RK |
1909 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1910 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 1911 | "TARGET_POWER" |
1fd4e8c1 RK |
1912 | "nabs %0,%1") |
1913 | ||
463b558b | 1914 | (define_insn "*nabs_no_power" |
ea9be077 MM |
1915 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
1916 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) | |
1917 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 1918 | "! TARGET_POWER" |
3595d104 MM |
1919 | "* |
1920 | { | |
1921 | return (TARGET_POWERPC) | |
1922 | ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\" | |
1923 | : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\"; | |
1924 | }" | |
ea9be077 MM |
1925 | [(set_attr "length" "12")]) |
1926 | ||
1927 | (define_split | |
1928 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") | |
1929 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) | |
1930 | (clobber (match_scratch:SI 2 "=&r,&r"))] | |
0ad91047 | 1931 | "! TARGET_POWER && reload_completed" |
ea9be077 MM |
1932 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1933 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1934 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
1935 | "") |
1936 | ||
1fd4e8c1 | 1937 | (define_insn "negsi2" |
cd2b37d9 RK |
1938 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1939 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1940 | "" |
1941 | "neg %0,%1") | |
1942 | ||
1943 | (define_insn "" | |
9ebbca7d GK |
1944 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1945 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1946 | (const_int 0))) |
9ebbca7d | 1947 | (clobber (match_scratch:SI 2 "=r,r"))] |
0ad91047 | 1948 | "! TARGET_POWERPC64" |
9ebbca7d GK |
1949 | "@ |
1950 | neg. %2,%1 | |
1951 | #" | |
1952 | [(set_attr "type" "compare") | |
1953 | (set_attr "length" "4,8")]) | |
1954 | ||
1955 | (define_split | |
1956 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1957 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1958 | (const_int 0))) | |
1959 | (clobber (match_scratch:SI 2 ""))] | |
1960 | "! TARGET_POWERPC64 && reload_completed" | |
1961 | [(set (match_dup 2) | |
1962 | (neg:SI (match_dup 1))) | |
1963 | (set (match_dup 0) | |
1964 | (compare:CC (match_dup 2) | |
1965 | (const_int 0)))] | |
1966 | "") | |
1fd4e8c1 RK |
1967 | |
1968 | (define_insn "" | |
9ebbca7d GK |
1969 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1970 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1971 | (const_int 0))) |
9ebbca7d | 1972 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1973 | (neg:SI (match_dup 1)))] |
0ad91047 | 1974 | "! TARGET_POWERPC64" |
9ebbca7d GK |
1975 | "@ |
1976 | neg. %0,%1 | |
1977 | #" | |
1978 | [(set_attr "type" "compare") | |
1979 | (set_attr "length" "4,8")]) | |
1980 | ||
1981 | (define_split | |
1982 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1983 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1984 | (const_int 0))) | |
1985 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1986 | (neg:SI (match_dup 1)))] | |
1987 | "! TARGET_POWERPC64 && reload_completed" | |
1988 | [(set (match_dup 0) | |
1989 | (neg:SI (match_dup 1))) | |
1990 | (set (match_dup 2) | |
1991 | (compare:CC (match_dup 0) | |
1992 | (const_int 0)))] | |
1993 | "") | |
1fd4e8c1 RK |
1994 | |
1995 | (define_insn "ffssi2" | |
242e8072 RK |
1996 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
1997 | (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1998 | "" |
7f340546 | 1999 | "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32" |
b19003d8 | 2000 | [(set_attr "length" "16")]) |
1fd4e8c1 | 2001 | |
ca7f5001 RK |
2002 | (define_expand "mulsi3" |
2003 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
2004 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
2005 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
2006 | "" | |
2007 | " | |
2008 | { | |
2009 | if (TARGET_POWER) | |
68b40e7e | 2010 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 2011 | else |
68b40e7e | 2012 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
2013 | DONE; |
2014 | }") | |
2015 | ||
68b40e7e | 2016 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
2017 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2018 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
2019 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
2020 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
2021 | "TARGET_POWER" |
2022 | "@ | |
2023 | {muls|mullw} %0,%1,%2 | |
2024 | {muli|mulli} %0,%1,%2" | |
2025 | [(set_attr "type" "imul")]) | |
2026 | ||
68b40e7e | 2027 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
2028 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
2029 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2030 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 2031 | "! TARGET_POWER" |
1fd4e8c1 | 2032 | "@ |
d904e9ed RK |
2033 | {muls|mullw} %0,%1,%2 |
2034 | {muli|mulli} %0,%1,%2" | |
cfb557c4 | 2035 | [(set_attr "type" "imul")]) |
1fd4e8c1 RK |
2036 | |
2037 | (define_insn "" | |
9ebbca7d GK |
2038 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2039 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2040 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2041 | (const_int 0))) |
9ebbca7d GK |
2042 | (clobber (match_scratch:SI 3 "=r,r")) |
2043 | (clobber (match_scratch:SI 4 "=q,q"))] | |
ca7f5001 | 2044 | "TARGET_POWER" |
9ebbca7d GK |
2045 | "@ |
2046 | {muls.|mullw.} %3,%1,%2 | |
2047 | #" | |
2048 | [(set_attr "type" "delayed_compare") | |
2049 | (set_attr "length" "4,8")]) | |
2050 | ||
2051 | (define_split | |
2052 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2053 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2054 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2055 | (const_int 0))) | |
2056 | (clobber (match_scratch:SI 3 "")) | |
2057 | (clobber (match_scratch:SI 4 ""))] | |
2058 | "TARGET_POWER && reload_completed" | |
2059 | [(parallel [(set (match_dup 3) | |
2060 | (mult:SI (match_dup 1) (match_dup 2))) | |
2061 | (clobber (match_dup 4))]) | |
2062 | (set (match_dup 0) | |
2063 | (compare:CC (match_dup 3) | |
2064 | (const_int 0)))] | |
2065 | "") | |
ca7f5001 RK |
2066 | |
2067 | (define_insn "" | |
9ebbca7d GK |
2068 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2069 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2070 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 2071 | (const_int 0))) |
9ebbca7d | 2072 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 2073 | "! TARGET_POWER" |
9ebbca7d GK |
2074 | "@ |
2075 | {muls.|mullw.} %3,%1,%2 | |
2076 | #" | |
2077 | [(set_attr "type" "delayed_compare") | |
2078 | (set_attr "length" "4,8")]) | |
2079 | ||
2080 | (define_split | |
2081 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2082 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2083 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2084 | (const_int 0))) | |
2085 | (clobber (match_scratch:SI 3 ""))] | |
2086 | "! TARGET_POWER && reload_completed" | |
2087 | [(set (match_dup 3) | |
2088 | (mult:SI (match_dup 1) (match_dup 2))) | |
2089 | (set (match_dup 0) | |
2090 | (compare:CC (match_dup 3) | |
2091 | (const_int 0)))] | |
2092 | "") | |
1fd4e8c1 RK |
2093 | |
2094 | (define_insn "" | |
9ebbca7d GK |
2095 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2096 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2097 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 2098 | (const_int 0))) |
9ebbca7d | 2099 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2100 | (mult:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 2101 | (clobber (match_scratch:SI 4 "=q,q"))] |
ca7f5001 | 2102 | "TARGET_POWER" |
9ebbca7d GK |
2103 | "@ |
2104 | {muls.|mullw.} %0,%1,%2 | |
2105 | #" | |
2106 | [(set_attr "type" "delayed_compare") | |
2107 | (set_attr "length" "4,8")]) | |
2108 | ||
2109 | (define_split | |
2110 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2111 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2112 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2113 | (const_int 0))) | |
2114 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2115 | (mult:SI (match_dup 1) (match_dup 2))) | |
2116 | (clobber (match_scratch:SI 4 ""))] | |
2117 | "TARGET_POWER && reload_completed" | |
2118 | [(parallel [(set (match_dup 0) | |
2119 | (mult:SI (match_dup 1) (match_dup 2))) | |
2120 | (clobber (match_dup 4))]) | |
2121 | (set (match_dup 3) | |
2122 | (compare:CC (match_dup 0) | |
2123 | (const_int 0)))] | |
2124 | "") | |
ca7f5001 RK |
2125 | |
2126 | (define_insn "" | |
9ebbca7d GK |
2127 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2128 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2129 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 2130 | (const_int 0))) |
9ebbca7d | 2131 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 2132 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 2133 | "! TARGET_POWER" |
9ebbca7d GK |
2134 | "@ |
2135 | {muls.|mullw.} %0,%1,%2 | |
2136 | #" | |
2137 | [(set_attr "type" "delayed_compare") | |
2138 | (set_attr "length" "4,8")]) | |
2139 | ||
2140 | (define_split | |
2141 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2142 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2143 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2144 | (const_int 0))) | |
2145 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2146 | (mult:SI (match_dup 1) (match_dup 2)))] | |
2147 | "! TARGET_POWER && reload_completed" | |
2148 | [(set (match_dup 0) | |
2149 | (mult:SI (match_dup 1) (match_dup 2))) | |
2150 | (set (match_dup 3) | |
2151 | (compare:CC (match_dup 0) | |
2152 | (const_int 0)))] | |
2153 | "") | |
1fd4e8c1 RK |
2154 | |
2155 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
2156 | ;; 0 and remainder to operand 3. | |
2157 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
2158 | ||
8ffd9c51 RK |
2159 | (define_expand "divmodsi4" |
2160 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2161 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2162 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
2163 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
2164 | (mod:SI (match_dup 1) (match_dup 2)))])] | |
2165 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
2166 | " | |
2167 | { | |
2168 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
2169 | { | |
39403d82 DE |
2170 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2171 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2172 | emit_insn (gen_divss_call ()); |
39403d82 DE |
2173 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2174 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
2175 | DONE; |
2176 | } | |
2177 | }") | |
deb9225a | 2178 | |
fada905b | 2179 | (define_insn "" |
cd2b37d9 RK |
2180 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2181 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2182 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2183 | (set (match_operand:SI 3 "gpc_reg_operand" "=q") | |
1fd4e8c1 | 2184 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 2185 | "TARGET_POWER" |
cfb557c4 RK |
2186 | "divs %0,%1,%2" |
2187 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 2188 | |
8ffd9c51 RK |
2189 | (define_expand "udivsi3" |
2190 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
2191 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2192 | (match_operand:SI 2 "gpc_reg_operand" "")))] | |
2193 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" | |
2194 | " | |
2195 | { | |
2196 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
2197 | { | |
39403d82 DE |
2198 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2199 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2200 | emit_insn (gen_quous_call ()); |
39403d82 | 2201 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
2202 | DONE; |
2203 | } | |
f192bf8b DE |
2204 | else if (TARGET_POWER) |
2205 | { | |
2206 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
2207 | DONE; | |
2208 | } | |
8ffd9c51 | 2209 | }") |
deb9225a | 2210 | |
f192bf8b DE |
2211 | (define_insn "udivsi3_mq" |
2212 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2213 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2214 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2215 | (clobber (match_scratch:SI 3 "=q"))] | |
2216 | "TARGET_POWERPC && TARGET_POWER" | |
2217 | "divwu %0,%1,%2" | |
2218 | [(set_attr "type" "idiv")]) | |
2219 | ||
2220 | (define_insn "*udivsi3_no_mq" | |
ca7f5001 RK |
2221 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2222 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2223 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 2224 | "TARGET_POWERPC && ! TARGET_POWER" |
a473029f | 2225 | "divwu %0,%1,%2" |
ca7f5001 RK |
2226 | [(set_attr "type" "idiv")]) |
2227 | ||
1fd4e8c1 | 2228 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 2229 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
2230 | ;; used; for PowerPC, force operands into register and do a normal divide; |
2231 | ;; for AIX common-mode, use quoss call on register operands. | |
1fd4e8c1 | 2232 | (define_expand "divsi3" |
cd2b37d9 RK |
2233 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2234 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
2235 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
2236 | "" | |
2237 | " | |
2238 | { | |
ca7f5001 RK |
2239 | if (GET_CODE (operands[2]) == CONST_INT |
2240 | && exact_log2 (INTVAL (operands[2])) >= 0) | |
2241 | ; | |
b6c9286a | 2242 | else if (TARGET_POWERPC) |
f192bf8b DE |
2243 | { |
2244 | operands[2] = force_reg (SImode, operands[2]); | |
2245 | if (TARGET_POWER) | |
2246 | { | |
2247 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
2248 | DONE; | |
2249 | } | |
2250 | } | |
b6c9286a | 2251 | else if (TARGET_POWER) |
1fd4e8c1 | 2252 | FAIL; |
405c5495 | 2253 | else |
8ffd9c51 | 2254 | { |
39403d82 DE |
2255 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2256 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2257 | emit_insn (gen_quoss_call ()); |
39403d82 | 2258 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
2259 | DONE; |
2260 | } | |
1fd4e8c1 RK |
2261 | }") |
2262 | ||
f192bf8b DE |
2263 | (define_insn "divsi3_mq" |
2264 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2265 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2266 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2267 | (clobber (match_scratch:SI 3 "=q"))] | |
2268 | "TARGET_POWERPC && TARGET_POWER" | |
2269 | "divw %0,%1,%2" | |
2270 | [(set_attr "type" "idiv")]) | |
2271 | ||
2272 | (define_insn "*divsi3_no_mq" | |
2273 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2274 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2275 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
2276 | "TARGET_POWERPC && ! TARGET_POWER" | |
2277 | "divw %0,%1,%2" | |
2278 | [(set_attr "type" "idiv")]) | |
2279 | ||
1fd4e8c1 | 2280 | (define_expand "modsi3" |
85644414 RK |
2281 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) |
2282 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
405c5495 | 2283 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] |
39b52ba2 | 2284 | "" |
1fd4e8c1 RK |
2285 | " |
2286 | { | |
481c7efa | 2287 | int i; |
39b52ba2 RK |
2288 | rtx temp1; |
2289 | rtx temp2; | |
2290 | ||
481c7efa FS |
2291 | if (GET_CODE (operands[2]) != CONST_INT) |
2292 | FAIL; | |
2293 | ||
2294 | i = exact_log2 (INTVAL (operands[2])); | |
2295 | ||
2296 | if (i < 0) | |
39b52ba2 RK |
2297 | FAIL; |
2298 | ||
2299 | temp1 = gen_reg_rtx (SImode); | |
2300 | temp2 = gen_reg_rtx (SImode); | |
1fd4e8c1 | 2301 | |
85644414 | 2302 | emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); |
39b52ba2 | 2303 | emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); |
85644414 RK |
2304 | emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); |
2305 | DONE; | |
1fd4e8c1 RK |
2306 | }") |
2307 | ||
2308 | (define_insn "" | |
cd2b37d9 RK |
2309 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2310 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
2311 | (match_operand:SI 2 "const_int_operand" "N")))] |
2312 | "exact_log2 (INTVAL (operands[2])) >= 0" | |
ca7f5001 | 2313 | "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" |
b19003d8 | 2314 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
2315 | |
2316 | (define_insn "" | |
9ebbca7d GK |
2317 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
2318 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2319 | (match_operand:SI 2 "const_int_operand" "N,N")) | |
b6b12107 | 2320 | (const_int 0))) |
9ebbca7d | 2321 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 2322 | "exact_log2 (INTVAL (operands[2])) >= 0" |
9ebbca7d GK |
2323 | "@ |
2324 | {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3 | |
2325 | #" | |
b19003d8 | 2326 | [(set_attr "type" "compare") |
9ebbca7d GK |
2327 | (set_attr "length" "8,12")]) |
2328 | ||
2329 | (define_split | |
2330 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2331 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2332 | (match_operand:SI 2 "const_int_operand" "")) | |
2333 | (const_int 0))) | |
2334 | (clobber (match_scratch:SI 3 ""))] | |
2335 | "exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed" | |
2336 | [(set (match_dup 3) | |
2337 | (div:SI (match_dup 1) (match_dup 2))) | |
2338 | (set (match_dup 0) | |
2339 | (compare:CC (match_dup 3) | |
2340 | (const_int 0)))] | |
2341 | "") | |
1fd4e8c1 RK |
2342 | |
2343 | (define_insn "" | |
9ebbca7d GK |
2344 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2345 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2346 | (match_operand:SI 2 "const_int_operand" "N,N")) | |
b6b12107 | 2347 | (const_int 0))) |
9ebbca7d | 2348 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2349 | (div:SI (match_dup 1) (match_dup 2)))] |
1fd4e8c1 | 2350 | "exact_log2 (INTVAL (operands[2])) >= 0" |
9ebbca7d GK |
2351 | "@ |
2352 | {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0 | |
2353 | #" | |
b19003d8 | 2354 | [(set_attr "type" "compare") |
9ebbca7d GK |
2355 | (set_attr "length" "8,12")]) |
2356 | ||
2357 | (define_split | |
2358 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2359 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2360 | (match_operand:SI 2 "const_int_operand" "")) | |
2361 | (const_int 0))) | |
2362 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2363 | (div:SI (match_dup 1) (match_dup 2)))] | |
2364 | "exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed" | |
2365 | [(set (match_dup 0) | |
2366 | (div:SI (match_dup 1) (match_dup 2))) | |
2367 | (set (match_dup 3) | |
2368 | (compare:CC (match_dup 0) | |
2369 | (const_int 0)))] | |
2370 | "") | |
1fd4e8c1 RK |
2371 | |
2372 | (define_insn "" | |
cd2b37d9 | 2373 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2374 | (udiv:SI |
996a5f59 | 2375 | (plus:DI (ashift:DI |
cd2b37d9 | 2376 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 2377 | (const_int 32)) |
23a900dc | 2378 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 2379 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 2380 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 2381 | (umod:SI |
996a5f59 | 2382 | (plus:DI (ashift:DI |
1fd4e8c1 | 2383 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 2384 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 2385 | (match_dup 3)))] |
ca7f5001 | 2386 | "TARGET_POWER" |
cfb557c4 RK |
2387 | "div %0,%1,%3" |
2388 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
2389 | |
2390 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
2391 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
2392 | ;; have to worry about the branches. So make a few subroutines here. | |
2393 | ;; | |
2394 | ;; First comes the normal case. | |
2395 | (define_expand "udivmodsi4_normal" | |
2396 | [(set (match_dup 4) (const_int 0)) | |
2397 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 2398 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2399 | (const_int 32)) |
2400 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
2401 | (match_operand:SI 2 "" ""))) | |
2402 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 2403 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2404 | (const_int 32)) |
2405 | (zero_extend:DI (match_dup 1))) | |
2406 | (match_dup 2)))])] | |
ca7f5001 | 2407 | "TARGET_POWER" |
1fd4e8c1 RK |
2408 | " |
2409 | { operands[4] = gen_reg_rtx (SImode); }") | |
2410 | ||
2411 | ;; This handles the branches. | |
2412 | (define_expand "udivmodsi4_tests" | |
2413 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
2414 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
2415 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
2416 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
2417 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
2418 | (set (match_dup 0) (const_int 1)) | |
2419 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
2420 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
2421 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
2422 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 2423 | "TARGET_POWER" |
1fd4e8c1 RK |
2424 | " |
2425 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
2426 | operands[6] = gen_reg_rtx (CCmode); | |
2427 | }") | |
2428 | ||
2429 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
2430 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2431 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 2432 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 2433 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 2434 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 2435 | "" |
1fd4e8c1 RK |
2436 | " |
2437 | { | |
2438 | rtx label = 0; | |
2439 | ||
8ffd9c51 | 2440 | if (! TARGET_POWER) |
c4d38ccb MM |
2441 | { |
2442 | if (! TARGET_POWERPC) | |
2443 | { | |
39403d82 DE |
2444 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2445 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 2446 | emit_insn (gen_divus_call ()); |
39403d82 DE |
2447 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2448 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
2449 | DONE; |
2450 | } | |
2451 | else | |
2452 | FAIL; | |
2453 | } | |
0081a354 | 2454 | |
1fd4e8c1 RK |
2455 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
2456 | { | |
2457 | operands[2] = force_reg (SImode, operands[2]); | |
2458 | label = gen_label_rtx (); | |
2459 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
2460 | operands[3], label)); | |
2461 | } | |
2462 | else | |
2463 | operands[2] = force_reg (SImode, operands[2]); | |
2464 | ||
2465 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
2466 | operands[3])); | |
2467 | if (label) | |
2468 | emit_label (label); | |
2469 | ||
2470 | DONE; | |
2471 | }") | |
0081a354 | 2472 | |
fada905b MM |
2473 | ;; AIX architecture-independent common-mode multiply (DImode), |
2474 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
2475 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
2476 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
2477 | ;; assumed unused if generating common-mode, so ignore. | |
2478 | (define_insn "mulh_call" | |
2479 | [(set (reg:SI 3) | |
2480 | (truncate:SI | |
2481 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
2482 | (sign_extend:DI (reg:SI 4))) | |
2483 | (const_int 32)))) | |
cf27b467 | 2484 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 2485 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2486 | "bla __mulh" |
2487 | [(set_attr "type" "imul")]) | |
fada905b MM |
2488 | |
2489 | (define_insn "mull_call" | |
2490 | [(set (reg:DI 3) | |
2491 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
2492 | (sign_extend:DI (reg:SI 4)))) | |
2493 | (clobber (match_scratch:SI 0 "=l")) | |
2494 | (clobber (reg:SI 0))] | |
2495 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2496 | "bla __mull" |
2497 | [(set_attr "type" "imul")]) | |
fada905b MM |
2498 | |
2499 | (define_insn "divss_call" | |
2500 | [(set (reg:SI 3) | |
2501 | (div:SI (reg:SI 3) (reg:SI 4))) | |
2502 | (set (reg:SI 4) | |
2503 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
2504 | (clobber (match_scratch:SI 0 "=l")) | |
2505 | (clobber (reg:SI 0))] | |
2506 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2507 | "bla __divss" |
2508 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2509 | |
2510 | (define_insn "divus_call" | |
8ffd9c51 RK |
2511 | [(set (reg:SI 3) |
2512 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2513 | (set (reg:SI 4) | |
2514 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
2515 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
2516 | (clobber (reg:SI 0)) |
2517 | (clobber (match_scratch:CC 1 "=x")) | |
2518 | (clobber (reg:CC 69))] | |
2519 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2520 | "bla __divus" |
2521 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2522 | |
2523 | (define_insn "quoss_call" | |
2524 | [(set (reg:SI 3) | |
2525 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 2526 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 2527 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2528 | "bla __quoss" |
2529 | [(set_attr "type" "idiv")]) | |
0081a354 | 2530 | |
fada905b MM |
2531 | (define_insn "quous_call" |
2532 | [(set (reg:SI 3) | |
2533 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2534 | (clobber (match_scratch:SI 0 "=l")) | |
2535 | (clobber (reg:SI 0)) | |
2536 | (clobber (match_scratch:CC 1 "=x")) | |
2537 | (clobber (reg:CC 69))] | |
2538 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2539 | "bla __quous" |
2540 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 2541 | \f |
bb21487f | 2542 | ;; Logical instructions |
dfbdccdb GK |
2543 | ;; The logical instructions are mostly combined by using match_operator, |
2544 | ;; but the plain AND insns are somewhat different because there is no | |
2545 | ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all | |
2546 | ;; those rotate-and-mask operations. Thus, the AND insns come first. | |
2547 | ||
29ae5b89 JL |
2548 | (define_insn "andsi3" |
2549 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
2550 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
5f59ecb7 | 2551 | (match_operand:SI 2 "and_operand" "?r,T,K,L"))) |
29ae5b89 | 2552 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] |
1fd4e8c1 RK |
2553 | "" |
2554 | "@ | |
2555 | and %0,%1,%2 | |
ca7f5001 RK |
2556 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
2557 | {andil.|andi.} %0,%1,%b2 | |
9ebbca7d | 2558 | {andiu.|andis.} %0,%1,%u2") |
52d3af72 DE |
2559 | |
2560 | ;; Note to set cr's other than cr0 we do the and immediate and then | |
2561 | ;; the test again -- this avoids a mcrf which on the higher end | |
2562 | ;; machines causes an execution serialization | |
1fd4e8c1 | 2563 | |
7cd5235b | 2564 | (define_insn "*andsi3_internal2" |
52d3af72 DE |
2565 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2566 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2567 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
1fd4e8c1 | 2568 | (const_int 0))) |
52d3af72 DE |
2569 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) |
2570 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 2571 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2572 | "@ |
2573 | and. %3,%1,%2 | |
ca7f5001 RK |
2574 | {andil.|andi.} %3,%1,%b2 |
2575 | {andiu.|andis.} %3,%1,%u2 | |
52d3af72 DE |
2576 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 |
2577 | # | |
2578 | # | |
2579 | # | |
2580 | #" | |
2581 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2582 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1fd4e8c1 | 2583 | |
52d3af72 DE |
2584 | (define_split |
2585 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2586 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2587 | (match_operand:SI 2 "and_operand" "")) | |
1fd4e8c1 | 2588 | (const_int 0))) |
52d3af72 DE |
2589 | (clobber (match_scratch:SI 3 "")) |
2590 | (clobber (match_scratch:CC 4 ""))] | |
0ad91047 | 2591 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2592 | [(parallel [(set (match_dup 3) |
2593 | (and:SI (match_dup 1) | |
2594 | (match_dup 2))) | |
2595 | (clobber (match_dup 4))]) | |
2596 | (set (match_dup 0) | |
2597 | (compare:CC (match_dup 3) | |
2598 | (const_int 0)))] | |
2599 | "") | |
2600 | ||
2601 | (define_insn "*andsi3_internal3" | |
2602 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2603 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2604 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
52d3af72 DE |
2605 | (const_int 0))) |
2606 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2607 | (and:SI (match_dup 1) | |
2608 | (match_dup 2))) | |
2609 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
0ad91047 | 2610 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
2611 | "@ |
2612 | and. %0,%1,%2 | |
ca7f5001 RK |
2613 | {andil.|andi.} %0,%1,%b2 |
2614 | {andiu.|andis.} %0,%1,%u2 | |
52d3af72 DE |
2615 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 |
2616 | # | |
2617 | # | |
2618 | # | |
2619 | #" | |
2620 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2621 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
2622 | ||
2623 | (define_split | |
2624 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2625 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2626 | (match_operand:SI 2 "and_operand" "")) | |
2627 | (const_int 0))) | |
2628 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2629 | (and:SI (match_dup 1) | |
2630 | (match_dup 2))) | |
2631 | (clobber (match_scratch:CC 4 ""))] | |
0ad91047 | 2632 | "! TARGET_POWERPC64 && reload_completed" |
52d3af72 DE |
2633 | [(parallel [(set (match_dup 0) |
2634 | (and:SI (match_dup 1) | |
2635 | (match_dup 2))) | |
2636 | (clobber (match_dup 4))]) | |
2637 | (set (match_dup 3) | |
2638 | (compare:CC (match_dup 0) | |
2639 | (const_int 0)))] | |
2640 | "") | |
1fd4e8c1 | 2641 | |
7cd5235b | 2642 | (define_expand "iorsi3" |
cd2b37d9 | 2643 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b MM |
2644 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
2645 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
2646 | "" | |
f357808b RK |
2647 | " |
2648 | { | |
7cd5235b | 2649 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2650 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2651 | { |
2652 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2653 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2654 | ? operands[0] : gen_reg_rtx (SImode)); |
2655 | ||
a260abc9 DE |
2656 | emit_insn (gen_iorsi3 (tmp, operands[1], |
2657 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2658 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2659 | DONE; |
2660 | } | |
f357808b RK |
2661 | }") |
2662 | ||
7cd5235b | 2663 | (define_expand "xorsi3" |
cd2b37d9 | 2664 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b MM |
2665 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
2666 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
1fd4e8c1 | 2667 | "" |
7cd5235b | 2668 | " |
1fd4e8c1 | 2669 | { |
7cd5235b | 2670 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2671 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2672 | { |
2673 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2674 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2675 | ? operands[0] : gen_reg_rtx (SImode)); |
2676 | ||
a260abc9 DE |
2677 | emit_insn (gen_xorsi3 (tmp, operands[1], |
2678 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2679 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2680 | DONE; |
2681 | } | |
1fd4e8c1 RK |
2682 | }") |
2683 | ||
dfbdccdb | 2684 | (define_insn "*boolsi3_internal1" |
7cd5235b | 2685 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
dfbdccdb GK |
2686 | (match_operator:SI 3 "boolean_operator" |
2687 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") | |
2688 | (match_operand:SI 2 "logical_operand" "r,K,L")]))] | |
1fd4e8c1 RK |
2689 | "" |
2690 | "@ | |
dfbdccdb GK |
2691 | %q3 %0,%1,%2 |
2692 | {%q3il|%q3i} %0,%1,%b2 | |
2693 | {%q3iu|%q3is} %0,%1,%u2") | |
1fd4e8c1 | 2694 | |
dfbdccdb | 2695 | (define_insn "*boolsi3_internal2" |
52d3af72 | 2696 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2697 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2698 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2699 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2700 | (const_int 0))) | |
52d3af72 | 2701 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2702 | "! TARGET_POWERPC64" |
52d3af72 | 2703 | "@ |
dfbdccdb | 2704 | %q4. %3,%1,%2 |
52d3af72 DE |
2705 | #" |
2706 | [(set_attr "type" "compare") | |
2707 | (set_attr "length" "4,8")]) | |
2708 | ||
2709 | (define_split | |
2710 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
2711 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2712 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2713 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2714 | (const_int 0))) | |
52d3af72 | 2715 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2716 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2717 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2718 | (set (match_dup 0) |
2719 | (compare:CC (match_dup 3) | |
2720 | (const_int 0)))] | |
2721 | "") | |
815cdc52 | 2722 | |
dfbdccdb | 2723 | (define_insn "*boolsi3_internal3" |
52d3af72 | 2724 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2725 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2726 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2727 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2728 | (const_int 0))) | |
52d3af72 | 2729 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2730 | (match_dup 4))] |
0ad91047 | 2731 | "! TARGET_POWERPC64" |
52d3af72 | 2732 | "@ |
dfbdccdb | 2733 | %q4. %0,%1,%2 |
52d3af72 DE |
2734 | #" |
2735 | [(set_attr "type" "compare") | |
2736 | (set_attr "length" "4,8")]) | |
2737 | ||
2738 | (define_split | |
dfbdccdb GK |
2739 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2740 | (compare:CC (match_operator:SI 4 "boolean_operator" | |
2741 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2742 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2743 | (const_int 0))) | |
2744 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
2745 | (match_dup 4))] | |
0ad91047 | 2746 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2747 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2748 | (set (match_dup 3) |
2749 | (compare:CC (match_dup 0) | |
2750 | (const_int 0)))] | |
2751 | "") | |
1fd4e8c1 | 2752 | |
dfbdccdb GK |
2753 | ;; Split an logical operation that we can't do in one insn into two insns, |
2754 | ;; each of which does one 16-bit part. This is used by combine. | |
a260abc9 DE |
2755 | |
2756 | (define_split | |
2757 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
dfbdccdb GK |
2758 | (match_operator:SI 3 "boolean_operator" |
2759 | [(match_operand:SI 1 "gpc_reg_operand" "") | |
2760 | (match_operand:SI 2 "non_logical_cint_operand" "")]))] | |
a260abc9 | 2761 | "" |
dfbdccdb GK |
2762 | [(set (match_dup 0) (match_dup 4)) |
2763 | (set (match_dup 0) (match_dup 5))] | |
a260abc9 DE |
2764 | " |
2765 | { | |
dfbdccdb GK |
2766 | rtx i; |
2767 | i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
2768 | operands[4] = gen_rtx (GET_CODE (operands[3]), SImode, | |
2769 | operands[1], i); | |
2770 | i = GEN_INT (INTVAL (operands[2]) & 0xffff); | |
2771 | operands[5] = gen_rtx (GET_CODE (operands[3]), SImode, | |
2772 | operands[0], i); | |
a260abc9 DE |
2773 | }") |
2774 | ||
dfbdccdb | 2775 | (define_insn "*boolcsi3_internal1" |
cd2b37d9 | 2776 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2777 | (match_operator:SI 3 "boolean_operator" |
2778 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2779 | (match_operand:SI 2 "logical_operand" "r")]))] | |
1fd4e8c1 | 2780 | "" |
dfbdccdb | 2781 | "%q3 %0,%2,%1") |
1fd4e8c1 | 2782 | |
dfbdccdb | 2783 | (define_insn "*boolcsi3_internal2" |
52d3af72 | 2784 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2785 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2786 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2787 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2788 | (const_int 0))) | |
52d3af72 | 2789 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2790 | "! TARGET_POWERPC64" |
52d3af72 | 2791 | "@ |
dfbdccdb | 2792 | %q4. %3,%2,%1 |
52d3af72 DE |
2793 | #" |
2794 | [(set_attr "type" "compare") | |
2795 | (set_attr "length" "4,8")]) | |
2796 | ||
2797 | (define_split | |
2798 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
2799 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2800 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2801 | (match_operand:SI 2 "gpc_reg_operand" "r")]) | |
2802 | (const_int 0))) | |
52d3af72 | 2803 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2804 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2805 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2806 | (set (match_dup 0) |
2807 | (compare:CC (match_dup 3) | |
2808 | (const_int 0)))] | |
2809 | "") | |
1fd4e8c1 | 2810 | |
dfbdccdb | 2811 | (define_insn "*boolcsi3_internal3" |
52d3af72 | 2812 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2813 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2814 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2815 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2816 | (const_int 0))) | |
52d3af72 | 2817 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2818 | (match_dup 4))] |
0ad91047 | 2819 | "! TARGET_POWERPC64" |
52d3af72 | 2820 | "@ |
dfbdccdb | 2821 | %q4. %0,%2,%1 |
52d3af72 DE |
2822 | #" |
2823 | [(set_attr "type" "compare") | |
2824 | (set_attr "length" "4,8")]) | |
2825 | ||
2826 | (define_split | |
52d3af72 | 2827 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2828 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2829 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2830 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2831 | (const_int 0))) | |
52d3af72 | 2832 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2833 | (match_dup 4))] |
0ad91047 | 2834 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2835 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2836 | (set (match_dup 3) |
2837 | (compare:CC (match_dup 0) | |
2838 | (const_int 0)))] | |
2839 | "") | |
2840 | ||
dfbdccdb | 2841 | (define_insn "*boolccsi3_internal1" |
cd2b37d9 | 2842 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2843 | (match_operator:SI 3 "boolean_operator" |
2844 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2845 | (not:SI (match_operand:SI 2 "logical_operand" "r"))]))] | |
1fd4e8c1 | 2846 | "" |
dfbdccdb | 2847 | "%q3 %0,%1,%2") |
1fd4e8c1 | 2848 | |
dfbdccdb | 2849 | (define_insn "*boolccsi3_internal2" |
52d3af72 | 2850 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2851 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2852 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2853 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2854 | (const_int 0))) | |
52d3af72 | 2855 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 2856 | "! TARGET_POWERPC64" |
52d3af72 | 2857 | "@ |
dfbdccdb | 2858 | %q4. %3,%1,%2 |
52d3af72 DE |
2859 | #" |
2860 | [(set_attr "type" "compare") | |
2861 | (set_attr "length" "4,8")]) | |
2862 | ||
2863 | (define_split | |
2864 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
2865 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2866 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
2867 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]) | |
2868 | (const_int 0))) | |
52d3af72 | 2869 | (clobber (match_scratch:SI 3 ""))] |
0ad91047 | 2870 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2871 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2872 | (set (match_dup 0) |
2873 | (compare:CC (match_dup 3) | |
2874 | (const_int 0)))] | |
2875 | "") | |
1fd4e8c1 | 2876 | |
dfbdccdb | 2877 | (define_insn "*boolccsi3_internal3" |
52d3af72 | 2878 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2879 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2880 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2881 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2882 | (const_int 0))) | |
52d3af72 | 2883 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2884 | (match_dup 4))] |
0ad91047 | 2885 | "! TARGET_POWERPC64" |
52d3af72 | 2886 | "@ |
dfbdccdb | 2887 | %q4. %0,%1,%2 |
52d3af72 DE |
2888 | #" |
2889 | [(set_attr "type" "compare") | |
2890 | (set_attr "length" "4,8")]) | |
2891 | ||
2892 | (define_split | |
52d3af72 | 2893 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2894 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2895 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2896 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2897 | (const_int 0))) | |
52d3af72 | 2898 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2899 | (match_dup 4))] |
0ad91047 | 2900 | "! TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 2901 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2902 | (set (match_dup 3) |
2903 | (compare:CC (match_dup 0) | |
2904 | (const_int 0)))] | |
2905 | "") | |
1fd4e8c1 RK |
2906 | |
2907 | ;; maskir insn. We need four forms because things might be in arbitrary | |
2908 | ;; orders. Don't define forms that only set CR fields because these | |
2909 | ;; would modify an input register. | |
2910 | ||
7cd5235b | 2911 | (define_insn "*maskir_internal1" |
cd2b37d9 | 2912 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2913 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2914 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
2915 | (and:SI (match_dup 2) | |
cd2b37d9 | 2916 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 2917 | "TARGET_POWER" |
01def764 | 2918 | "maskir %0,%3,%2") |
1fd4e8c1 | 2919 | |
7cd5235b | 2920 | (define_insn "*maskir_internal2" |
242e8072 | 2921 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2922 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2923 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 2924 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 2925 | (match_dup 2))))] |
ca7f5001 | 2926 | "TARGET_POWER" |
01def764 | 2927 | "maskir %0,%3,%2") |
1fd4e8c1 | 2928 | |
7cd5235b | 2929 | (define_insn "*maskir_internal3" |
cd2b37d9 | 2930 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 2931 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 2932 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
2933 | (and:SI (not:SI (match_dup 2)) |
2934 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2935 | "TARGET_POWER" |
01def764 | 2936 | "maskir %0,%3,%2") |
1fd4e8c1 | 2937 | |
7cd5235b | 2938 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
2939 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2940 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
2941 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
2942 | (and:SI (not:SI (match_dup 2)) | |
2943 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2944 | "TARGET_POWER" |
01def764 | 2945 | "maskir %0,%3,%2") |
1fd4e8c1 | 2946 | |
7cd5235b | 2947 | (define_insn "*maskir_internal5" |
9ebbca7d | 2948 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2949 | (compare:CC |
9ebbca7d GK |
2950 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2951 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
01def764 | 2952 | (and:SI (match_dup 2) |
9ebbca7d | 2953 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 2954 | (const_int 0))) |
9ebbca7d | 2955 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2956 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2957 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 2958 | "TARGET_POWER" |
9ebbca7d GK |
2959 | "@ |
2960 | maskir. %0,%3,%2 | |
2961 | #" | |
2962 | [(set_attr "type" "compare") | |
2963 | (set_attr "length" "4,8")]) | |
2964 | ||
2965 | (define_split | |
2966 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2967 | (compare:CC | |
2968 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2969 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2970 | (and:SI (match_dup 2) | |
2971 | (match_operand:SI 3 "gpc_reg_operand" ""))) | |
2972 | (const_int 0))) | |
2973 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2974 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2975 | (and:SI (match_dup 2) (match_dup 3))))] | |
2976 | "TARGET_POWER && reload_completed" | |
2977 | [(set (match_dup 0) | |
2978 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2979 | (and:SI (match_dup 2) (match_dup 3)))) | |
2980 | (set (match_dup 4) | |
2981 | (compare:CC (match_dup 0) | |
2982 | (const_int 0)))] | |
2983 | "") | |
1fd4e8c1 | 2984 | |
7cd5235b | 2985 | (define_insn "*maskir_internal6" |
9ebbca7d | 2986 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2987 | (compare:CC |
9ebbca7d GK |
2988 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2989 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
2990 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") | |
01def764 | 2991 | (match_dup 2))) |
1fd4e8c1 | 2992 | (const_int 0))) |
9ebbca7d | 2993 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2994 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2995 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 2996 | "TARGET_POWER" |
9ebbca7d GK |
2997 | "@ |
2998 | maskir. %0,%3,%2 | |
2999 | #" | |
3000 | [(set_attr "type" "compare") | |
3001 | (set_attr "length" "4,8")]) | |
3002 | ||
3003 | (define_split | |
3004 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3005 | (compare:CC | |
3006 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
3007 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
3008 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
3009 | (match_dup 2))) | |
3010 | (const_int 0))) | |
3011 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3012 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3013 | (and:SI (match_dup 3) (match_dup 2))))] | |
3014 | "TARGET_POWER && reload_completed" | |
3015 | [(set (match_dup 0) | |
3016 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
3017 | (and:SI (match_dup 3) (match_dup 2)))) | |
3018 | (set (match_dup 4) | |
3019 | (compare:CC (match_dup 0) | |
3020 | (const_int 0)))] | |
3021 | "") | |
1fd4e8c1 | 3022 | |
7cd5235b | 3023 | (define_insn "*maskir_internal7" |
9ebbca7d | 3024 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
815cdc52 | 3025 | (compare:CC |
9ebbca7d GK |
3026 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") |
3027 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
815cdc52 | 3028 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 3029 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
815cdc52 | 3030 | (const_int 0))) |
9ebbca7d | 3031 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
3032 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
3033 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3034 | "TARGET_POWER" | |
9ebbca7d GK |
3035 | "@ |
3036 | maskir. %0,%3,%2 | |
3037 | #" | |
3038 | [(set_attr "type" "compare") | |
3039 | (set_attr "length" "4,8")]) | |
3040 | ||
3041 | (define_split | |
3042 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3043 | (compare:CC | |
3044 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") | |
3045 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
3046 | (and:SI (not:SI (match_dup 2)) | |
3047 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
3048 | (const_int 0))) | |
3049 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3050 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
3051 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3052 | "TARGET_POWER && reload_completed" | |
3053 | [(set (match_dup 0) | |
3054 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
3055 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
3056 | (set (match_dup 4) | |
3057 | (compare:CC (match_dup 0) | |
3058 | (const_int 0)))] | |
3059 | "") | |
1fd4e8c1 | 3060 | |
7cd5235b | 3061 | (define_insn "*maskir_internal8" |
9ebbca7d | 3062 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3063 | (compare:CC |
9ebbca7d GK |
3064 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") |
3065 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
01def764 | 3066 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 3067 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
1fd4e8c1 | 3068 | (const_int 0))) |
9ebbca7d | 3069 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
3070 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
3071 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 3072 | "TARGET_POWER" |
9ebbca7d GK |
3073 | "@ |
3074 | maskir. %0,%3,%2 | |
3075 | #" | |
3076 | [(set_attr "type" "compare") | |
3077 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 3078 | \f |
9ebbca7d GK |
3079 | (define_split |
3080 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3081 | (compare:CC | |
3082 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
3083 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
3084 | (and:SI (not:SI (match_dup 2)) | |
3085 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
3086 | (const_int 0))) | |
3087 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3088 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
3089 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
3090 | "TARGET_POWER && reload_completed" | |
3091 | [(set (match_dup 0) | |
3092 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
3093 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
3094 | (set (match_dup 4) | |
3095 | (compare:CC (match_dup 0) | |
3096 | (const_int 0)))] | |
3097 | "") | |
3098 | ||
1fd4e8c1 RK |
3099 | ;; Rotate and shift insns, in all their variants. These support shifts, |
3100 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 | 3101 | (define_expand "insv" |
0ad91047 DE |
3102 | [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") |
3103 | (match_operand:SI 1 "const_int_operand" "") | |
3104 | (match_operand:SI 2 "const_int_operand" "")) | |
3105 | (match_operand 3 "gpc_reg_operand" ""))] | |
034c1be0 MM |
3106 | "" |
3107 | " | |
3108 | { | |
3109 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3110 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3111 | compiler if the address of the structure is taken later. */ | |
3112 | if (GET_CODE (operands[0]) == SUBREG | |
3113 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3114 | FAIL; | |
a78e33fc DE |
3115 | |
3116 | if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) | |
3117 | emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); | |
3118 | else | |
3119 | emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); | |
3120 | DONE; | |
034c1be0 MM |
3121 | }") |
3122 | ||
a78e33fc | 3123 | (define_insn "insvsi" |
cd2b37d9 | 3124 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
3125 | (match_operand:SI 1 "const_int_operand" "i") |
3126 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 3127 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
3128 | "" |
3129 | "* | |
3130 | { | |
3131 | int start = INTVAL (operands[2]) & 31; | |
3132 | int size = INTVAL (operands[1]) & 31; | |
3133 | ||
89e9f3a8 MM |
3134 | operands[4] = GEN_INT (32 - start - size); |
3135 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3136 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
1fd4e8c1 RK |
3137 | }") |
3138 | ||
a78e33fc | 3139 | (define_insn "*insvsi_internal1" |
d56d506a RK |
3140 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3141 | (match_operand:SI 1 "const_int_operand" "i") | |
3142 | (match_operand:SI 2 "const_int_operand" "i")) | |
3143 | (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3144 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 3145 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3146 | "* |
3147 | { | |
3148 | int shift = INTVAL (operands[4]) & 31; | |
3149 | int start = INTVAL (operands[2]) & 31; | |
3150 | int size = INTVAL (operands[1]) & 31; | |
3151 | ||
89e9f3a8 MM |
3152 | operands[4] = GEN_INT (shift - start - size); |
3153 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3154 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3155 | }") |
3156 | ||
a78e33fc | 3157 | (define_insn "*insvsi_internal2" |
d56d506a RK |
3158 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3159 | (match_operand:SI 1 "const_int_operand" "i") | |
3160 | (match_operand:SI 2 "const_int_operand" "i")) | |
3161 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3162 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 3163 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3164 | "* |
3165 | { | |
3166 | int shift = INTVAL (operands[4]) & 31; | |
3167 | int start = INTVAL (operands[2]) & 31; | |
3168 | int size = INTVAL (operands[1]) & 31; | |
3169 | ||
89e9f3a8 MM |
3170 | operands[4] = GEN_INT (32 - shift - start - size); |
3171 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3172 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3173 | }") |
3174 | ||
a78e33fc | 3175 | (define_insn "*insvsi_internal3" |
d56d506a RK |
3176 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3177 | (match_operand:SI 1 "const_int_operand" "i") | |
3178 | (match_operand:SI 2 "const_int_operand" "i")) | |
3179 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3180 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 3181 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3182 | "* |
3183 | { | |
3184 | int shift = INTVAL (operands[4]) & 31; | |
3185 | int start = INTVAL (operands[2]) & 31; | |
3186 | int size = INTVAL (operands[1]) & 31; | |
3187 | ||
89e9f3a8 MM |
3188 | operands[4] = GEN_INT (32 - shift - start - size); |
3189 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3190 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
d56d506a RK |
3191 | }") |
3192 | ||
a78e33fc | 3193 | (define_insn "*insvsi_internal4" |
d56d506a RK |
3194 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3195 | (match_operand:SI 1 "const_int_operand" "i") | |
3196 | (match_operand:SI 2 "const_int_operand" "i")) | |
3197 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3198 | (match_operand:SI 4 "const_int_operand" "i") | |
3199 | (match_operand:SI 5 "const_int_operand" "i")))] | |
3200 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
3201 | "* | |
3202 | { | |
3203 | int extract_start = INTVAL (operands[5]) & 31; | |
3204 | int extract_size = INTVAL (operands[4]) & 31; | |
3205 | int insert_start = INTVAL (operands[2]) & 31; | |
3206 | int insert_size = INTVAL (operands[1]) & 31; | |
3207 | ||
3208 | /* Align extract field with insert field */ | |
3a598fbe | 3209 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 3210 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 3211 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
d56d506a RK |
3212 | }") |
3213 | ||
a78e33fc | 3214 | (define_insn "insvdi" |
685f3906 | 3215 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") |
a78e33fc DE |
3216 | (match_operand:SI 1 "const_int_operand" "i") |
3217 | (match_operand:SI 2 "const_int_operand" "i")) | |
685f3906 DE |
3218 | (match_operand:DI 3 "gpc_reg_operand" "r"))] |
3219 | "TARGET_POWERPC64" | |
3220 | "* | |
3221 | { | |
3222 | int start = INTVAL (operands[2]) & 63; | |
3223 | int size = INTVAL (operands[1]) & 63; | |
3224 | ||
a78e33fc DE |
3225 | operands[1] = GEN_INT (64 - start - size); |
3226 | return \"rldimi %0,%3,%H1,%H2\"; | |
685f3906 DE |
3227 | }") |
3228 | ||
034c1be0 | 3229 | (define_expand "extzv" |
0ad91047 DE |
3230 | [(set (match_operand 0 "gpc_reg_operand" "") |
3231 | (zero_extract (match_operand 1 "gpc_reg_operand" "") | |
3232 | (match_operand:SI 2 "const_int_operand" "") | |
3233 | (match_operand:SI 3 "const_int_operand" "")))] | |
034c1be0 MM |
3234 | "" |
3235 | " | |
3236 | { | |
3237 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3238 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3239 | compiler if the address of the structure is taken later. */ | |
3240 | if (GET_CODE (operands[0]) == SUBREG | |
3241 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3242 | FAIL; | |
a78e33fc DE |
3243 | |
3244 | if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) | |
3245 | emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); | |
3246 | else | |
3247 | emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); | |
3248 | DONE; | |
034c1be0 MM |
3249 | }") |
3250 | ||
a78e33fc | 3251 | (define_insn "extzvsi" |
cd2b37d9 RK |
3252 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3253 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3254 | (match_operand:SI 2 "const_int_operand" "i") |
3255 | (match_operand:SI 3 "const_int_operand" "i")))] | |
3256 | "" | |
3257 | "* | |
3258 | { | |
3259 | int start = INTVAL (operands[3]) & 31; | |
3260 | int size = INTVAL (operands[2]) & 31; | |
3261 | ||
3262 | if (start + size >= 32) | |
3263 | operands[3] = const0_rtx; | |
3264 | else | |
89e9f3a8 | 3265 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3266 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
3267 | }") |
3268 | ||
a78e33fc | 3269 | (define_insn "*extzvsi_internal1" |
9ebbca7d GK |
3270 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3271 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3272 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3273 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3274 | (const_int 0))) |
9ebbca7d | 3275 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 3276 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
3277 | "* |
3278 | { | |
3279 | int start = INTVAL (operands[3]) & 31; | |
3280 | int size = INTVAL (operands[2]) & 31; | |
3281 | ||
9ebbca7d GK |
3282 | /* Force split for non-cc0 compare. */ |
3283 | if (which_alternative == 1) | |
3284 | return \"#\"; | |
3285 | ||
a7a975e1 RK |
3286 | /* If the bitfield being tested fits in the upper or lower half of a |
3287 | word, it is possible to use andiu. or andil. to test it. This is | |
3288 | useful because the condition register set-use delay is smaller for | |
3289 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
3290 | position is 0 because the LT and GT bits may be set wrong. */ | |
3291 | ||
3292 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 3293 | { |
3a598fbe | 3294 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
3295 | - (1 << (16 - (start & 15) - size)))); |
3296 | if (start < 16) | |
ca7f5001 | 3297 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 3298 | else |
ca7f5001 | 3299 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 3300 | } |
7e69e155 | 3301 | |
1fd4e8c1 RK |
3302 | if (start + size >= 32) |
3303 | operands[3] = const0_rtx; | |
3304 | else | |
89e9f3a8 | 3305 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3306 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 3307 | }" |
9ebbca7d GK |
3308 | [(set_attr "type" "compare") |
3309 | (set_attr "length" "4,8")]) | |
3310 | ||
3311 | (define_split | |
3312 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3313 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3314 | (match_operand:SI 2 "const_int_operand" "") | |
3315 | (match_operand:SI 3 "const_int_operand" "")) | |
3316 | (const_int 0))) | |
3317 | (clobber (match_scratch:SI 4 ""))] | |
3318 | "! TARGET_POWERPC64 && reload_completed" | |
3319 | [(set (match_dup 4) | |
3320 | (zero_extract:SI (match_dup 1) (match_dup 2) | |
3321 | (match_dup 3))) | |
3322 | (set (match_dup 0) | |
3323 | (compare:CC (match_dup 4) | |
3324 | (const_int 0)))] | |
3325 | "") | |
1fd4e8c1 | 3326 | |
a78e33fc | 3327 | (define_insn "*extzvsi_internal2" |
9ebbca7d GK |
3328 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3329 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3330 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3331 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3332 | (const_int 0))) |
9ebbca7d | 3333 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3334 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
0ad91047 | 3335 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
3336 | "* |
3337 | { | |
3338 | int start = INTVAL (operands[3]) & 31; | |
3339 | int size = INTVAL (operands[2]) & 31; | |
3340 | ||
9ebbca7d GK |
3341 | /* Force split for non-cc0 compare. */ |
3342 | if (which_alternative == 1) | |
3343 | return \"#\"; | |
3344 | ||
a7a975e1 | 3345 | if (start >= 16 && start + size == 32) |
df031c43 | 3346 | { |
89e9f3a8 | 3347 | operands[3] = GEN_INT ((1 << (32 - start)) - 1); |
ca7f5001 | 3348 | return \"{andil.|andi.} %0,%1,%3\"; |
df031c43 | 3349 | } |
7e69e155 | 3350 | |
1fd4e8c1 RK |
3351 | if (start + size >= 32) |
3352 | operands[3] = const0_rtx; | |
3353 | else | |
89e9f3a8 | 3354 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3355 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 | 3356 | }" |
9ebbca7d GK |
3357 | [(set_attr "type" "delayed_compare") |
3358 | (set_attr "length" "4,8")]) | |
3359 | ||
3360 | (define_split | |
3361 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3362 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3363 | (match_operand:SI 2 "const_int_operand" "") | |
3364 | (match_operand:SI 3 "const_int_operand" "")) | |
3365 | (const_int 0))) | |
3366 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3367 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] | |
3368 | "! TARGET_POWERPC64 && reload_completed" | |
3369 | [(set (match_dup 0) | |
3370 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) | |
3371 | (set (match_dup 4) | |
3372 | (compare:CC (match_dup 0) | |
3373 | (const_int 0)))] | |
3374 | "") | |
1fd4e8c1 | 3375 | |
a78e33fc | 3376 | (define_insn "extzvdi" |
685f3906 DE |
3377 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
3378 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3379 | (match_operand:SI 2 "const_int_operand" "i") |
3380 | (match_operand:SI 3 "const_int_operand" "i")))] | |
685f3906 DE |
3381 | "TARGET_POWERPC64" |
3382 | "* | |
3383 | { | |
3384 | int start = INTVAL (operands[3]) & 63; | |
3385 | int size = INTVAL (operands[2]) & 63; | |
3386 | ||
3387 | if (start + size >= 64) | |
3388 | operands[3] = const0_rtx; | |
3389 | else | |
89e9f3a8 MM |
3390 | operands[3] = GEN_INT (start + size); |
3391 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3392 | return \"rldicl %0,%1,%3,%2\"; |
3393 | }") | |
3394 | ||
a78e33fc | 3395 | (define_insn "*extzvdi_internal1" |
29ae5b89 JL |
3396 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
3397 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3398 | (match_operand:SI 2 "const_int_operand" "i") |
3399 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3400 | (const_int 0))) |
29ae5b89 | 3401 | (clobber (match_scratch:DI 4 "=r"))] |
685f3906 DE |
3402 | "TARGET_POWERPC64" |
3403 | "* | |
3404 | { | |
3405 | int start = INTVAL (operands[3]) & 63; | |
3406 | int size = INTVAL (operands[2]) & 63; | |
3407 | ||
3408 | if (start + size >= 64) | |
3409 | operands[3] = const0_rtx; | |
3410 | else | |
89e9f3a8 MM |
3411 | operands[3] = GEN_INT (start + size); |
3412 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3413 | return \"rldicl. %4,%1,%3,%2\"; |
3414 | }") | |
3415 | ||
a78e33fc | 3416 | (define_insn "*extzvdi_internal2" |
29ae5b89 JL |
3417 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
3418 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3419 | (match_operand:SI 2 "const_int_operand" "i") |
3420 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3421 | (const_int 0))) |
29ae5b89 | 3422 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 DE |
3423 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
3424 | "TARGET_POWERPC64" | |
3425 | "* | |
3426 | { | |
3427 | int start = INTVAL (operands[3]) & 63; | |
3428 | int size = INTVAL (operands[2]) & 63; | |
3429 | ||
3430 | if (start + size >= 64) | |
3431 | operands[3] = const0_rtx; | |
3432 | else | |
89e9f3a8 MM |
3433 | operands[3] = GEN_INT (start + size); |
3434 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3435 | return \"rldicl. %0,%1,%3,%2\"; |
3436 | }") | |
3437 | ||
1fd4e8c1 | 3438 | (define_insn "rotlsi3" |
cd2b37d9 RK |
3439 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3440 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3441 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
3442 | "" | |
ca7f5001 | 3443 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 3444 | |
a260abc9 | 3445 | (define_insn "*rotlsi3_internal2" |
9ebbca7d GK |
3446 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3447 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3448 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3449 | (const_int 0))) |
9ebbca7d | 3450 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3451 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3452 | "@ |
3453 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff | |
3454 | #" | |
3455 | [(set_attr "type" "delayed_compare") | |
3456 | (set_attr "length" "4,8")]) | |
3457 | ||
3458 | (define_split | |
3459 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3460 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3461 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3462 | (const_int 0))) | |
3463 | (clobber (match_scratch:SI 3 ""))] | |
3464 | "! TARGET_POWERPC64 && reload_completed" | |
3465 | [(set (match_dup 3) | |
3466 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3467 | (set (match_dup 0) | |
3468 | (compare:CC (match_dup 3) | |
3469 | (const_int 0)))] | |
3470 | "") | |
1fd4e8c1 | 3471 | |
a260abc9 | 3472 | (define_insn "*rotlsi3_internal3" |
9ebbca7d GK |
3473 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3474 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3475 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3476 | (const_int 0))) |
9ebbca7d | 3477 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3478 | (rotate:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 3479 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3480 | "@ |
3481 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff | |
3482 | #" | |
3483 | [(set_attr "type" "delayed_compare") | |
3484 | (set_attr "length" "4,8")]) | |
3485 | ||
3486 | (define_split | |
3487 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3488 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3489 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3490 | (const_int 0))) | |
3491 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3492 | (rotate:SI (match_dup 1) (match_dup 2)))] | |
3493 | "! TARGET_POWERPC64 && reload_completed" | |
3494 | [(set (match_dup 0) | |
3495 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3496 | (set (match_dup 3) | |
3497 | (compare:CC (match_dup 0) | |
3498 | (const_int 0)))] | |
3499 | "") | |
1fd4e8c1 | 3500 | |
a260abc9 | 3501 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
3502 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3503 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3504 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
9615f239 | 3505 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 3506 | "" |
ca7f5001 | 3507 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 3508 | |
a260abc9 | 3509 | (define_insn "*rotlsi3_internal5" |
9ebbca7d | 3510 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3511 | (compare:CC (and:SI |
9ebbca7d GK |
3512 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3513 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
3514 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 3515 | (const_int 0))) |
9ebbca7d | 3516 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 3517 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3518 | "@ |
3519 | {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 | |
3520 | #" | |
3521 | [(set_attr "type" "delayed_compare") | |
3522 | (set_attr "length" "4,8")]) | |
3523 | ||
3524 | (define_split | |
3525 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3526 | (compare:CC (and:SI | |
3527 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3528 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3529 | (match_operand:SI 3 "mask_operand" "")) | |
3530 | (const_int 0))) | |
3531 | (clobber (match_scratch:SI 4 ""))] | |
3532 | "! TARGET_POWERPC64 && reload_completed" | |
3533 | [(set (match_dup 4) | |
3534 | (and:SI (rotate:SI (match_dup 1) | |
3535 | (match_dup 2)) | |
3536 | (match_dup 3))) | |
3537 | (set (match_dup 0) | |
3538 | (compare:CC (match_dup 4) | |
3539 | (const_int 0)))] | |
3540 | "") | |
1fd4e8c1 | 3541 | |
a260abc9 | 3542 | (define_insn "*rotlsi3_internal6" |
9ebbca7d | 3543 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3544 | (compare:CC (and:SI |
9ebbca7d GK |
3545 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3546 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
3547 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 3548 | (const_int 0))) |
9ebbca7d | 3549 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3550 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 3551 | "! TARGET_POWERPC64" |
9ebbca7d GK |
3552 | "@ |
3553 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 | |
3554 | #" | |
3555 | [(set_attr "type" "delayed_compare") | |
3556 | (set_attr "length" "4,8")]) | |
3557 | ||
3558 | (define_split | |
3559 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3560 | (compare:CC (and:SI | |
3561 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3562 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3563 | (match_operand:SI 3 "mask_operand" "")) | |
3564 | (const_int 0))) | |
3565 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3566 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
3567 | "! TARGET_POWERPC64 && reload_completed" | |
3568 | [(set (match_dup 0) | |
3569 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3570 | (set (match_dup 4) | |
3571 | (compare:CC (match_dup 0) | |
3572 | (const_int 0)))] | |
3573 | "") | |
1fd4e8c1 | 3574 | |
a260abc9 | 3575 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 3576 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3577 | (zero_extend:SI |
3578 | (subreg:QI | |
cd2b37d9 | 3579 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3580 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3581 | "" | |
ca7f5001 | 3582 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 3583 | |
a260abc9 | 3584 | (define_insn "*rotlsi3_internal8" |
9ebbca7d | 3585 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3586 | (compare:CC (zero_extend:SI |
3587 | (subreg:QI | |
9ebbca7d GK |
3588 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3589 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3590 | (const_int 0))) |
9ebbca7d | 3591 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3592 | "" |
9ebbca7d GK |
3593 | "@ |
3594 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff | |
3595 | #" | |
3596 | [(set_attr "type" "delayed_compare") | |
3597 | (set_attr "length" "4,8")]) | |
3598 | ||
3599 | (define_split | |
3600 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3601 | (compare:CC (zero_extend:SI | |
3602 | (subreg:QI | |
3603 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3604 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3605 | (const_int 0))) | |
3606 | (clobber (match_scratch:SI 3 ""))] | |
3607 | "reload_completed" | |
3608 | [(set (match_dup 3) | |
3609 | (zero_extend:SI (subreg:QI | |
3610 | (rotate:SI (match_dup 1) | |
3611 | (match_dup 2)) 0))) | |
3612 | (set (match_dup 0) | |
3613 | (compare:CC (match_dup 3) | |
3614 | (const_int 0)))] | |
3615 | "") | |
1fd4e8c1 | 3616 | |
a260abc9 | 3617 | (define_insn "*rotlsi3_internal9" |
9ebbca7d | 3618 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3619 | (compare:CC (zero_extend:SI |
3620 | (subreg:QI | |
9ebbca7d GK |
3621 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3622 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3623 | (const_int 0))) |
9ebbca7d | 3624 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3625 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3626 | "" | |
9ebbca7d GK |
3627 | "@ |
3628 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff | |
3629 | #" | |
3630 | [(set_attr "type" "delayed_compare") | |
3631 | (set_attr "length" "4,8")]) | |
3632 | ||
3633 | (define_split | |
3634 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3635 | (compare:CC (zero_extend:SI | |
3636 | (subreg:QI | |
3637 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3638 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3639 | (const_int 0))) | |
3640 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3641 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3642 | "reload_completed" | |
3643 | [(set (match_dup 0) | |
3644 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3645 | (set (match_dup 3) | |
3646 | (compare:CC (match_dup 0) | |
3647 | (const_int 0)))] | |
3648 | "") | |
1fd4e8c1 | 3649 | |
a260abc9 | 3650 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 3651 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3652 | (zero_extend:SI |
3653 | (subreg:HI | |
cd2b37d9 | 3654 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3655 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3656 | "" | |
ca7f5001 | 3657 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 3658 | |
a260abc9 | 3659 | (define_insn "*rotlsi3_internal11" |
9ebbca7d | 3660 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3661 | (compare:CC (zero_extend:SI |
3662 | (subreg:HI | |
9ebbca7d GK |
3663 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3664 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3665 | (const_int 0))) |
9ebbca7d | 3666 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3667 | "" |
9ebbca7d GK |
3668 | "@ |
3669 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff | |
3670 | #" | |
3671 | [(set_attr "type" "delayed_compare") | |
3672 | (set_attr "length" "4,8")]) | |
3673 | ||
3674 | (define_split | |
3675 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3676 | (compare:CC (zero_extend:SI | |
3677 | (subreg:HI | |
3678 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3679 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3680 | (const_int 0))) | |
3681 | (clobber (match_scratch:SI 3 ""))] | |
3682 | "reload_completed" | |
3683 | [(set (match_dup 3) | |
3684 | (zero_extend:SI (subreg:HI | |
3685 | (rotate:SI (match_dup 1) | |
3686 | (match_dup 2)) 0))) | |
3687 | (set (match_dup 0) | |
3688 | (compare:CC (match_dup 3) | |
3689 | (const_int 0)))] | |
3690 | "") | |
1fd4e8c1 | 3691 | |
a260abc9 | 3692 | (define_insn "*rotlsi3_internal12" |
9ebbca7d | 3693 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3694 | (compare:CC (zero_extend:SI |
3695 | (subreg:HI | |
9ebbca7d GK |
3696 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3697 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3698 | (const_int 0))) |
9ebbca7d | 3699 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3700 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3701 | "" | |
9ebbca7d GK |
3702 | "@ |
3703 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff | |
3704 | #" | |
3705 | [(set_attr "type" "delayed_compare") | |
3706 | (set_attr "length" "4,8")]) | |
3707 | ||
3708 | (define_split | |
3709 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3710 | (compare:CC (zero_extend:SI | |
3711 | (subreg:HI | |
3712 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3713 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3714 | (const_int 0))) | |
3715 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3716 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3717 | "reload_completed" | |
3718 | [(set (match_dup 0) | |
3719 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3720 | (set (match_dup 3) | |
3721 | (compare:CC (match_dup 0) | |
3722 | (const_int 0)))] | |
3723 | "") | |
1fd4e8c1 RK |
3724 | |
3725 | ;; Note that we use "sle." instead of "sl." so that we can set | |
3726 | ;; SHIFT_COUNT_TRUNCATED. | |
3727 | ||
ca7f5001 RK |
3728 | (define_expand "ashlsi3" |
3729 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3730 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3731 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3732 | "" | |
3733 | " | |
3734 | { | |
3735 | if (TARGET_POWER) | |
3736 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
3737 | else | |
25c341fa | 3738 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3739 | DONE; |
3740 | }") | |
3741 | ||
3742 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
3743 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3744 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3745 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3746 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3747 | "TARGET_POWER" |
1fd4e8c1 RK |
3748 | "@ |
3749 | sle %0,%1,%2 | |
9ebbca7d | 3750 | {sli|slwi} %0,%1,%h2") |
ca7f5001 | 3751 | |
25c341fa | 3752 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
3753 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3754 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3755 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 3756 | "! TARGET_POWER" |
9ebbca7d | 3757 | "{sl|slw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
3758 | |
3759 | (define_insn "" | |
9ebbca7d GK |
3760 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3761 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3762 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3763 | (const_int 0))) |
9ebbca7d GK |
3764 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
3765 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 3766 | "TARGET_POWER" |
1fd4e8c1 RK |
3767 | "@ |
3768 | sle. %3,%1,%2 | |
9ebbca7d GK |
3769 | {sli.|slwi.} %3,%1,%h2 |
3770 | # | |
3771 | #" | |
3772 | [(set_attr "type" "delayed_compare") | |
3773 | (set_attr "length" "4,4,8,8")]) | |
3774 | ||
3775 | (define_split | |
3776 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3777 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3778 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3779 | (const_int 0))) | |
3780 | (clobber (match_scratch:SI 3 "")) | |
3781 | (clobber (match_scratch:SI 4 ""))] | |
3782 | "TARGET_POWER && reload_completed" | |
3783 | [(parallel [(set (match_dup 3) | |
3784 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3785 | (clobber (match_dup 4))]) | |
3786 | (set (match_dup 0) | |
3787 | (compare:CC (match_dup 3) | |
3788 | (const_int 0)))] | |
3789 | "") | |
25c341fa | 3790 | |
ca7f5001 | 3791 | (define_insn "" |
9ebbca7d GK |
3792 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3793 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3794 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3795 | (const_int 0))) |
9ebbca7d | 3796 | (clobber (match_scratch:SI 3 "=r,r"))] |
0ad91047 | 3797 | "! TARGET_POWER && ! TARGET_POWERPC64" |
9ebbca7d GK |
3798 | "@ |
3799 | {sl|slw}%I2. %3,%1,%h2 | |
3800 | #" | |
3801 | [(set_attr "type" "delayed_compare") | |
3802 | (set_attr "length" "4,8")]) | |
3803 | ||
3804 | (define_split | |
3805 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3806 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3807 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3808 | (const_int 0))) | |
3809 | (clobber (match_scratch:SI 3 ""))] | |
3810 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
3811 | [(set (match_dup 3) | |
3812 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3813 | (set (match_dup 0) | |
3814 | (compare:CC (match_dup 3) | |
3815 | (const_int 0)))] | |
3816 | "") | |
1fd4e8c1 RK |
3817 | |
3818 | (define_insn "" | |
9ebbca7d GK |
3819 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3820 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3821 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3822 | (const_int 0))) |
9ebbca7d | 3823 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 3824 | (ashift:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3825 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 3826 | "TARGET_POWER" |
1fd4e8c1 RK |
3827 | "@ |
3828 | sle. %0,%1,%2 | |
9ebbca7d GK |
3829 | {sli.|slwi.} %0,%1,%h2 |
3830 | # | |
3831 | #" | |
3832 | [(set_attr "type" "delayed_compare") | |
3833 | (set_attr "length" "4,4,8,8")]) | |
3834 | ||
3835 | (define_split | |
3836 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3837 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3838 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3839 | (const_int 0))) | |
3840 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3841 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3842 | (clobber (match_scratch:SI 4 ""))] | |
3843 | "TARGET_POWER && reload_completed" | |
3844 | [(parallel [(set (match_dup 0) | |
3845 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3846 | (clobber (match_dup 4))]) | |
3847 | (set (match_dup 3) | |
3848 | (compare:CC (match_dup 0) | |
3849 | (const_int 0)))] | |
3850 | "") | |
25c341fa | 3851 | |
ca7f5001 | 3852 | (define_insn "" |
9ebbca7d GK |
3853 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3854 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3855 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3856 | (const_int 0))) |
9ebbca7d | 3857 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 3858 | (ashift:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 3859 | "! TARGET_POWER && ! TARGET_POWERPC64" |
9ebbca7d GK |
3860 | "@ |
3861 | {sl|slw}%I2. %0,%1,%h2 | |
3862 | #" | |
3863 | [(set_attr "type" "delayed_compare") | |
3864 | (set_attr "length" "4,8")]) | |
3865 | ||
3866 | (define_split | |
3867 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3868 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3869 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3870 | (const_int 0))) | |
3871 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3872 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
3873 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
3874 | [(set (match_dup 0) | |
3875 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3876 | (set (match_dup 3) | |
3877 | (compare:CC (match_dup 0) | |
3878 | (const_int 0)))] | |
3879 | "") | |
1fd4e8c1 RK |
3880 | |
3881 | (define_insn "" | |
cd2b37d9 RK |
3882 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3883 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3884 | (match_operand:SI 2 "const_int_operand" "i")) |
9615f239 | 3885 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 3886 | "includes_lshift_p (operands[2], operands[3])" |
d56d506a | 3887 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
3888 | |
3889 | (define_insn "" | |
9ebbca7d | 3890 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3891 | (compare:CC |
9ebbca7d GK |
3892 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3893 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
3894 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 3895 | (const_int 0))) |
9ebbca7d | 3896 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 3897 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3898 | "@ |
3899 | {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 | |
3900 | #" | |
3901 | [(set_attr "type" "delayed_compare") | |
3902 | (set_attr "length" "4,8")]) | |
3903 | ||
3904 | (define_split | |
3905 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3906 | (compare:CC | |
3907 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3908 | (match_operand:SI 2 "const_int_operand" "")) | |
3909 | (match_operand:SI 3 "mask_operand" "")) | |
3910 | (const_int 0))) | |
3911 | (clobber (match_scratch:SI 4 ""))] | |
3912 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed" | |
3913 | [(set (match_dup 4) | |
3914 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) | |
3915 | (match_dup 3))) | |
3916 | (set (match_dup 0) | |
3917 | (compare:CC (match_dup 4) | |
3918 | (const_int 0)))] | |
3919 | "") | |
1fd4e8c1 RK |
3920 | |
3921 | (define_insn "" | |
9ebbca7d | 3922 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3923 | (compare:CC |
9ebbca7d GK |
3924 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3925 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
3926 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 3927 | (const_int 0))) |
9ebbca7d | 3928 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3929 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 3930 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3931 | "@ |
3932 | {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 | |
3933 | #" | |
3934 | [(set_attr "type" "delayed_compare") | |
3935 | (set_attr "length" "4,8")]) | |
3936 | ||
3937 | (define_split | |
3938 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3939 | (compare:CC | |
3940 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3941 | (match_operand:SI 2 "const_int_operand" "")) | |
3942 | (match_operand:SI 3 "mask_operand" "")) | |
3943 | (const_int 0))) | |
3944 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3945 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
3946 | "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed" | |
3947 | [(set (match_dup 0) | |
3948 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3949 | (set (match_dup 4) | |
3950 | (compare:CC (match_dup 0) | |
3951 | (const_int 0)))] | |
3952 | "") | |
1fd4e8c1 | 3953 | |
ca7f5001 | 3954 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 3955 | ;; "sli x,x,0". |
ca7f5001 RK |
3956 | (define_expand "lshrsi3" |
3957 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3958 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3959 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3960 | "" | |
3961 | " | |
3962 | { | |
3963 | if (TARGET_POWER) | |
3964 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
3965 | else | |
25c341fa | 3966 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3967 | DONE; |
3968 | }") | |
3969 | ||
3970 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
3971 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
3972 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
3973 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
3974 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 3975 | "TARGET_POWER" |
1fd4e8c1 RK |
3976 | "@ |
3977 | sre %0,%1,%2 | |
bdf423cb | 3978 | mr %0,%1 |
ca7f5001 RK |
3979 | {s%A2i|s%A2wi} %0,%1,%h2") |
3980 | ||
25c341fa | 3981 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
3982 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3983 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3984 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 3985 | "! TARGET_POWER" |
bdf423cb MM |
3986 | "@ |
3987 | mr %0,%1 | |
3988 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
3989 | |
3990 | (define_insn "" | |
9ebbca7d GK |
3991 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") |
3992 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
3993 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 3994 | (const_int 0))) |
9ebbca7d GK |
3995 | (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) |
3996 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] | |
ca7f5001 | 3997 | "TARGET_POWER" |
1fd4e8c1 | 3998 | "@ |
29ae5b89 JL |
3999 | sre. %3,%1,%2 |
4000 | mr. %1,%1 | |
9ebbca7d GK |
4001 | {s%A2i.|s%A2wi.} %3,%1,%h2 |
4002 | # | |
4003 | # | |
4004 | #" | |
4005 | [(set_attr "type" "delayed_compare") | |
4006 | (set_attr "length" "4,4,4,8,8,8")]) | |
4007 | ||
4008 | (define_split | |
4009 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4010 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4011 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4012 | (const_int 0))) | |
4013 | (clobber (match_scratch:SI 3 "")) | |
4014 | (clobber (match_scratch:SI 4 ""))] | |
4015 | "TARGET_POWER && reload_completed" | |
4016 | [(parallel [(set (match_dup 3) | |
4017 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4018 | (clobber (match_dup 4))]) | |
4019 | (set (match_dup 0) | |
4020 | (compare:CC (match_dup 3) | |
4021 | (const_int 0)))] | |
4022 | "") | |
ca7f5001 RK |
4023 | |
4024 | (define_insn "" | |
9ebbca7d GK |
4025 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4026 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4027 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
ca7f5001 | 4028 | (const_int 0))) |
9ebbca7d | 4029 | (clobber (match_scratch:SI 3 "=X,r,X,r"))] |
0ad91047 | 4030 | "! TARGET_POWER && ! TARGET_POWERPC64" |
bdf423cb MM |
4031 | "@ |
4032 | mr. %1,%1 | |
9ebbca7d GK |
4033 | {sr|srw}%I2. %3,%1,%h2 |
4034 | # | |
4035 | #" | |
4036 | [(set_attr "type" "delayed_compare") | |
4037 | (set_attr "length" "4,4,8,8")]) | |
1fd4e8c1 | 4038 | |
9ebbca7d GK |
4039 | (define_split |
4040 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4041 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4042 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4043 | (const_int 0))) | |
4044 | (clobber (match_scratch:SI 3 ""))] | |
4045 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4046 | [(set (match_dup 3) | |
4047 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4048 | (set (match_dup 0) | |
4049 | (compare:CC (match_dup 3) | |
4050 | (const_int 0)))] | |
4051 | "") | |
4052 | ||
4053 | (define_insn "" | |
4054 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") | |
4055 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
4056 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 4057 | (const_int 0))) |
9ebbca7d | 4058 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
1fd4e8c1 | 4059 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4060 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] |
ca7f5001 | 4061 | "TARGET_POWER" |
1fd4e8c1 | 4062 | "@ |
29ae5b89 JL |
4063 | sre. %0,%1,%2 |
4064 | mr. %0,%1 | |
9ebbca7d GK |
4065 | {s%A2i.|s%A2wi.} %0,%1,%h2 |
4066 | # | |
4067 | # | |
4068 | #" | |
4069 | [(set_attr "type" "delayed_compare") | |
4070 | (set_attr "length" "4,4,4,8,8,8")]) | |
4071 | ||
4072 | (define_split | |
4073 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4074 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4075 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4076 | (const_int 0))) | |
4077 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4078 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4079 | (clobber (match_scratch:SI 4 ""))] | |
4080 | "TARGET_POWER && reload_completed" | |
4081 | [(parallel [(set (match_dup 0) | |
4082 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4083 | (clobber (match_dup 4))]) | |
4084 | (set (match_dup 3) | |
4085 | (compare:CC (match_dup 0) | |
4086 | (const_int 0)))] | |
4087 | "") | |
ca7f5001 RK |
4088 | |
4089 | (define_insn "" | |
9ebbca7d GK |
4090 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4091 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4092 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
815cdc52 | 4093 | (const_int 0))) |
9ebbca7d | 4094 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
29ae5b89 | 4095 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] |
0ad91047 | 4096 | "! TARGET_POWER && ! TARGET_POWERPC64" |
29ae5b89 JL |
4097 | "@ |
4098 | mr. %0,%1 | |
9ebbca7d GK |
4099 | {sr|srw}%I2. %0,%1,%h2 |
4100 | # | |
4101 | #" | |
4102 | [(set_attr "type" "delayed_compare") | |
4103 | (set_attr "length" "4,4,8,8")]) | |
4104 | ||
4105 | (define_split | |
4106 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4107 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4108 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4109 | (const_int 0))) | |
4110 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4111 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
4112 | "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed" | |
4113 | [(set (match_dup 0) | |
4114 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4115 | (set (match_dup 3) | |
4116 | (compare:CC (match_dup 0) | |
4117 | (const_int 0)))] | |
4118 | "") | |
1fd4e8c1 RK |
4119 | |
4120 | (define_insn "" | |
cd2b37d9 RK |
4121 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4122 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4123 | (match_operand:SI 2 "const_int_operand" "i")) |
9615f239 | 4124 | (match_operand:SI 3 "mask_operand" "T")))] |
1fd4e8c1 | 4125 | "includes_rshift_p (operands[2], operands[3])" |
ca7f5001 | 4126 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
4127 | |
4128 | (define_insn "" | |
9ebbca7d | 4129 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4130 | (compare:CC |
9ebbca7d GK |
4131 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4132 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4133 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4134 | (const_int 0))) |
9ebbca7d | 4135 | (clobber (match_scratch:SI 4 "=r,r"))] |
0ad91047 | 4136 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4137 | "@ |
4138 | {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 | |
4139 | #" | |
4140 | [(set_attr "type" "delayed_compare") | |
4141 | (set_attr "length" "4,8")]) | |
4142 | ||
4143 | (define_split | |
4144 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4145 | (compare:CC | |
4146 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4147 | (match_operand:SI 2 "const_int_operand" "")) | |
4148 | (match_operand:SI 3 "mask_operand" "")) | |
4149 | (const_int 0))) | |
4150 | (clobber (match_scratch:SI 4 ""))] | |
4151 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed" | |
4152 | [(set (match_dup 4) | |
4153 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) | |
4154 | (match_dup 3))) | |
4155 | (set (match_dup 0) | |
4156 | (compare:CC (match_dup 4) | |
4157 | (const_int 0)))] | |
4158 | "") | |
1fd4e8c1 RK |
4159 | |
4160 | (define_insn "" | |
9ebbca7d | 4161 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4162 | (compare:CC |
9ebbca7d GK |
4163 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4164 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4165 | (match_operand:SI 3 "mask_operand" "T,T")) | |
1fd4e8c1 | 4166 | (const_int 0))) |
9ebbca7d | 4167 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4168 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
0ad91047 | 4169 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4170 | "@ |
4171 | {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 | |
4172 | #" | |
4173 | [(set_attr "type" "delayed_compare") | |
4174 | (set_attr "length" "4,8")]) | |
4175 | ||
4176 | (define_split | |
4177 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4178 | (compare:CC | |
4179 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4180 | (match_operand:SI 2 "const_int_operand" "")) | |
4181 | (match_operand:SI 3 "mask_operand" "")) | |
4182 | (const_int 0))) | |
4183 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4184 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4185 | "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed" | |
4186 | [(set (match_dup 0) | |
4187 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4188 | (set (match_dup 4) | |
4189 | (compare:CC (match_dup 0) | |
4190 | (const_int 0)))] | |
4191 | "") | |
1fd4e8c1 RK |
4192 | |
4193 | (define_insn "" | |
cd2b37d9 | 4194 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4195 | (zero_extend:SI |
4196 | (subreg:QI | |
cd2b37d9 | 4197 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4198 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4199 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 4200 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
4201 | |
4202 | (define_insn "" | |
9ebbca7d | 4203 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4204 | (compare:CC |
4205 | (zero_extend:SI | |
4206 | (subreg:QI | |
9ebbca7d GK |
4207 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4208 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4209 | (const_int 0))) |
9ebbca7d | 4210 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4211 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4212 | "@ |
4213 | {rlinm.|rlwinm.} %3,%1,%s2,0xff | |
4214 | #" | |
4215 | [(set_attr "type" "delayed_compare") | |
4216 | (set_attr "length" "4,8")]) | |
4217 | ||
4218 | (define_split | |
4219 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4220 | (compare:CC | |
4221 | (zero_extend:SI | |
4222 | (subreg:QI | |
4223 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4224 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4225 | (const_int 0))) | |
4226 | (clobber (match_scratch:SI 3 ""))] | |
4227 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4228 | [(set (match_dup 3) | |
4229 | (zero_extend:SI (subreg:QI | |
4230 | (lshiftrt:SI (match_dup 1) | |
4231 | (match_dup 2)) 0))) | |
4232 | (set (match_dup 0) | |
4233 | (compare:CC (match_dup 3) | |
4234 | (const_int 0)))] | |
4235 | "") | |
1fd4e8c1 RK |
4236 | |
4237 | (define_insn "" | |
9ebbca7d | 4238 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4239 | (compare:CC |
4240 | (zero_extend:SI | |
4241 | (subreg:QI | |
9ebbca7d GK |
4242 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4243 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4244 | (const_int 0))) |
9ebbca7d | 4245 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4246 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4247 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4248 | "@ |
4249 | {rlinm.|rlwinm.} %0,%1,%s2,0xff | |
4250 | #" | |
4251 | [(set_attr "type" "delayed_compare") | |
4252 | (set_attr "length" "4,8")]) | |
4253 | ||
4254 | (define_split | |
4255 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4256 | (compare:CC | |
4257 | (zero_extend:SI | |
4258 | (subreg:QI | |
4259 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4260 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4261 | (const_int 0))) | |
4262 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4263 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4264 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4265 | [(set (match_dup 0) | |
4266 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4267 | (set (match_dup 3) | |
4268 | (compare:CC (match_dup 0) | |
4269 | (const_int 0)))] | |
4270 | "") | |
1fd4e8c1 RK |
4271 | |
4272 | (define_insn "" | |
cd2b37d9 | 4273 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4274 | (zero_extend:SI |
4275 | (subreg:HI | |
cd2b37d9 | 4276 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4277 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4278 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 4279 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
4280 | |
4281 | (define_insn "" | |
9ebbca7d | 4282 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4283 | (compare:CC |
4284 | (zero_extend:SI | |
4285 | (subreg:HI | |
9ebbca7d GK |
4286 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4287 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4288 | (const_int 0))) |
9ebbca7d | 4289 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4290 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4291 | "@ |
4292 | {rlinm.|rlwinm.} %3,%1,%s2,0xffff | |
4293 | #" | |
4294 | [(set_attr "type" "delayed_compare") | |
4295 | (set_attr "length" "4,8")]) | |
4296 | ||
4297 | (define_split | |
4298 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4299 | (compare:CC | |
4300 | (zero_extend:SI | |
4301 | (subreg:HI | |
4302 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4303 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4304 | (const_int 0))) | |
4305 | (clobber (match_scratch:SI 3 ""))] | |
4306 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4307 | [(set (match_dup 3) | |
4308 | (zero_extend:SI (subreg:HI | |
4309 | (lshiftrt:SI (match_dup 1) | |
4310 | (match_dup 2)) 0))) | |
4311 | (set (match_dup 0) | |
4312 | (compare:CC (match_dup 3) | |
4313 | (const_int 0)))] | |
4314 | "") | |
1fd4e8c1 RK |
4315 | |
4316 | (define_insn "" | |
9ebbca7d | 4317 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4318 | (compare:CC |
4319 | (zero_extend:SI | |
4320 | (subreg:HI | |
9ebbca7d GK |
4321 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4322 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4323 | (const_int 0))) |
9ebbca7d | 4324 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4325 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4326 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4327 | "@ |
4328 | {rlinm.|rlwinm.} %0,%1,%s2,0xffff | |
4329 | #" | |
4330 | [(set_attr "type" "delayed_compare") | |
4331 | (set_attr "length" "4,8")]) | |
4332 | ||
4333 | (define_split | |
4334 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4335 | (compare:CC | |
4336 | (zero_extend:SI | |
4337 | (subreg:HI | |
4338 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4339 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4340 | (const_int 0))) | |
4341 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4342 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4343 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4344 | [(set (match_dup 0) | |
4345 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4346 | (set (match_dup 3) | |
4347 | (compare:CC (match_dup 0) | |
4348 | (const_int 0)))] | |
4349 | "") | |
1fd4e8c1 RK |
4350 | |
4351 | (define_insn "" | |
cd2b37d9 | 4352 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4353 | (const_int 1) |
cd2b37d9 RK |
4354 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4355 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4356 | (const_int 31)))] |
ca7f5001 | 4357 | "TARGET_POWER" |
1fd4e8c1 RK |
4358 | "rrib %0,%1,%2") |
4359 | ||
4360 | (define_insn "" | |
cd2b37d9 | 4361 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4362 | (const_int 1) |
cd2b37d9 RK |
4363 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4364 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4365 | (const_int 31)))] |
ca7f5001 | 4366 | "TARGET_POWER" |
1fd4e8c1 RK |
4367 | "rrib %0,%1,%2") |
4368 | ||
4369 | (define_insn "" | |
cd2b37d9 | 4370 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4371 | (const_int 1) |
cd2b37d9 RK |
4372 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4373 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4374 | (const_int 1) |
4375 | (const_int 0)))] | |
ca7f5001 | 4376 | "TARGET_POWER" |
1fd4e8c1 RK |
4377 | "rrib %0,%1,%2") |
4378 | ||
ca7f5001 RK |
4379 | (define_expand "ashrsi3" |
4380 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4381 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4382 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4383 | "" | |
4384 | " | |
4385 | { | |
4386 | if (TARGET_POWER) | |
4387 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
4388 | else | |
25c341fa | 4389 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4390 | DONE; |
4391 | }") | |
4392 | ||
4393 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
4394 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4395 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4396 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
4397 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 4398 | "TARGET_POWER" |
1fd4e8c1 RK |
4399 | "@ |
4400 | srea %0,%1,%2 | |
ca7f5001 RK |
4401 | {srai|srawi} %0,%1,%h2") |
4402 | ||
25c341fa | 4403 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
4404 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4405 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4406 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4407 | "! TARGET_POWER" |
d904e9ed | 4408 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4409 | |
4410 | (define_insn "" | |
9ebbca7d GK |
4411 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4412 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4413 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4414 | (const_int 0))) |
9ebbca7d GK |
4415 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4416 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4417 | "TARGET_POWER" |
1fd4e8c1 RK |
4418 | "@ |
4419 | srea. %3,%1,%2 | |
9ebbca7d GK |
4420 | {srai.|srawi.} %3,%1,%h2 |
4421 | # | |
4422 | #" | |
4423 | [(set_attr "type" "delayed_compare") | |
4424 | (set_attr "length" "4,4,8,8")]) | |
4425 | ||
4426 | (define_split | |
4427 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4428 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4429 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4430 | (const_int 0))) | |
4431 | (clobber (match_scratch:SI 3 "")) | |
4432 | (clobber (match_scratch:SI 4 ""))] | |
4433 | "TARGET_POWER && reload_completed" | |
4434 | [(parallel [(set (match_dup 3) | |
4435 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4436 | (clobber (match_dup 4))]) | |
4437 | (set (match_dup 0) | |
4438 | (compare:CC (match_dup 3) | |
4439 | (const_int 0)))] | |
4440 | "") | |
ca7f5001 RK |
4441 | |
4442 | (define_insn "" | |
9ebbca7d GK |
4443 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4444 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4445 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4446 | (const_int 0))) |
9ebbca7d | 4447 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 4448 | "! TARGET_POWER" |
9ebbca7d GK |
4449 | "@ |
4450 | {sra|sraw}%I2. %3,%1,%h2 | |
4451 | #" | |
4452 | [(set_attr "type" "delayed_compare") | |
4453 | (set_attr "length" "4,8")]) | |
4454 | ||
4455 | (define_split | |
4456 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4457 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4458 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4459 | (const_int 0))) | |
4460 | (clobber (match_scratch:SI 3 ""))] | |
4461 | "! TARGET_POWER && reload_completed" | |
4462 | [(set (match_dup 3) | |
4463 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4464 | (set (match_dup 0) | |
4465 | (compare:CC (match_dup 3) | |
4466 | (const_int 0)))] | |
4467 | "") | |
1fd4e8c1 RK |
4468 | |
4469 | (define_insn "" | |
9ebbca7d GK |
4470 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4471 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4472 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4473 | (const_int 0))) |
9ebbca7d | 4474 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 4475 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4476 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 4477 | "TARGET_POWER" |
1fd4e8c1 RK |
4478 | "@ |
4479 | srea. %0,%1,%2 | |
9ebbca7d GK |
4480 | {srai.|srawi.} %0,%1,%h2 |
4481 | # | |
4482 | #" | |
4483 | [(set_attr "type" "delayed_compare") | |
4484 | (set_attr "length" "4,4,8,8")]) | |
4485 | ||
4486 | (define_split | |
4487 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4488 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4489 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4490 | (const_int 0))) | |
4491 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4492 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4493 | (clobber (match_scratch:SI 4 ""))] | |
4494 | "TARGET_POWER && reload_completed" | |
4495 | [(parallel [(set (match_dup 0) | |
4496 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4497 | (clobber (match_dup 4))]) | |
4498 | (set (match_dup 3) | |
4499 | (compare:CC (match_dup 0) | |
4500 | (const_int 0)))] | |
4501 | "") | |
1fd4e8c1 | 4502 | |
ca7f5001 | 4503 | (define_insn "" |
9ebbca7d GK |
4504 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4505 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4506 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4507 | (const_int 0))) |
9ebbca7d | 4508 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 4509 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 4510 | "! TARGET_POWER" |
9ebbca7d GK |
4511 | "@ |
4512 | {sra|sraw}%I2. %0,%1,%h2 | |
4513 | #" | |
4514 | [(set_attr "type" "delayed_compare") | |
4515 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 4516 | \f |
9ebbca7d GK |
4517 | (define_split |
4518 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4519 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4520 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4521 | (const_int 0))) | |
4522 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4523 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
4524 | "! TARGET_POWER && reload_completed" | |
4525 | [(set (match_dup 0) | |
4526 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4527 | (set (match_dup 3) | |
4528 | (compare:CC (match_dup 0) | |
4529 | (const_int 0)))] | |
4530 | "") | |
4531 | ||
1fd4e8c1 RK |
4532 | ;; Floating-point insns, excluding normal data motion. |
4533 | ;; | |
ca7f5001 RK |
4534 | ;; PowerPC has a full set of single-precision floating point instructions. |
4535 | ;; | |
4536 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
4537 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
4538 | ;; The only conversions we will do will be when storing to memory. In that | |
4539 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
4540 | ;; |
4541 | ;; Note that when we store into a single-precision memory location, we need to | |
4542 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
4543 | ;; need a scratch register for the frsp. But this is difficult when the store | |
4544 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
4545 | ;; this case, we just lose precision that we would have otherwise gotten but | |
4546 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
4547 | ||
e8112008 | 4548 | (define_insn "extendsfdf2" |
cd2b37d9 | 4549 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
e8112008 | 4550 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] |
d14a6d05 | 4551 | "TARGET_HARD_FLOAT" |
e8112008 | 4552 | "* |
5c30aff8 | 4553 | { |
e8112008 RK |
4554 | if (REGNO (operands[0]) == REGNO (operands[1])) |
4555 | return \"\"; | |
4556 | else | |
4557 | return \"fmr %0,%1\"; | |
4558 | }" | |
4559 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
4560 | |
4561 | (define_insn "truncdfsf2" | |
cd2b37d9 RK |
4562 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4563 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4564 | "TARGET_HARD_FLOAT" |
dcac138d | 4565 | "frsp %0,%1" |
1fd4e8c1 RK |
4566 | [(set_attr "type" "fp")]) |
4567 | ||
455350f4 RK |
4568 | (define_insn "aux_truncdfsf2" |
4569 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4570 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))] | |
4571 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" | |
4572 | "frsp %0,%1" | |
4573 | [(set_attr "type" "fp")]) | |
4574 | ||
1fd4e8c1 | 4575 | (define_insn "negsf2" |
cd2b37d9 RK |
4576 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4577 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4578 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4579 | "fneg %0,%1" |
4580 | [(set_attr "type" "fp")]) | |
4581 | ||
4582 | (define_insn "abssf2" | |
cd2b37d9 RK |
4583 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4584 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4585 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4586 | "fabs %0,%1" |
4587 | [(set_attr "type" "fp")]) | |
4588 | ||
4589 | (define_insn "" | |
cd2b37d9 RK |
4590 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4591 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
d14a6d05 | 4592 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4593 | "fnabs %0,%1" |
4594 | [(set_attr "type" "fp")]) | |
4595 | ||
ca7f5001 RK |
4596 | (define_expand "addsf3" |
4597 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4598 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4599 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4600 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4601 | "") |
4602 | ||
4603 | (define_insn "" | |
cd2b37d9 RK |
4604 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4605 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4606 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4607 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4608 | "fadds %0,%1,%2" |
ca7f5001 RK |
4609 | [(set_attr "type" "fp")]) |
4610 | ||
4611 | (define_insn "" | |
4612 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4613 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4614 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4615 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4616 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
4617 | [(set_attr "type" "fp")]) |
4618 | ||
4619 | (define_expand "subsf3" | |
4620 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4621 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4622 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4623 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4624 | "") |
4625 | ||
4626 | (define_insn "" | |
4627 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4628 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4629 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4630 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4631 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
4632 | [(set_attr "type" "fp")]) |
4633 | ||
ca7f5001 | 4634 | (define_insn "" |
cd2b37d9 RK |
4635 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4636 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4637 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4638 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4639 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
4640 | [(set_attr "type" "fp")]) |
4641 | ||
4642 | (define_expand "mulsf3" | |
4643 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4644 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4645 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4646 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4647 | "") |
4648 | ||
4649 | (define_insn "" | |
4650 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4651 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4652 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4653 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4654 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
4655 | [(set_attr "type" "fp")]) |
4656 | ||
ca7f5001 | 4657 | (define_insn "" |
cd2b37d9 RK |
4658 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4659 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4660 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4661 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4662 | "{fm|fmul} %0,%1,%2" |
0780f386 | 4663 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4664 | |
ca7f5001 RK |
4665 | (define_expand "divsf3" |
4666 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4667 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4668 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4669 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4670 | "") |
4671 | ||
4672 | (define_insn "" | |
cd2b37d9 RK |
4673 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4674 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4675 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4676 | "TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4677 | "fdivs %0,%1,%2" |
ca7f5001 RK |
4678 | [(set_attr "type" "sdiv")]) |
4679 | ||
4680 | (define_insn "" | |
4681 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4682 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4683 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4684 | "! TARGET_POWERPC && TARGET_HARD_FLOAT" |
b26c8351 | 4685 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 4686 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4687 | |
4688 | (define_insn "" | |
cd2b37d9 RK |
4689 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4690 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4691 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4692 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4693 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4694 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
4695 | [(set_attr "type" "fp")]) |
4696 | ||
4697 | (define_insn "" | |
4698 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4699 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4700 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4701 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4702 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4703 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 4704 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4705 | |
4706 | (define_insn "" | |
cd2b37d9 RK |
4707 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4708 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4709 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4710 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4711 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4712 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4713 | [(set_attr "type" "fp")]) |
4714 | ||
4715 | (define_insn "" | |
4716 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4717 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4718 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4719 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
38c1f2d7 | 4720 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4721 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 4722 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4723 | |
4724 | (define_insn "" | |
cd2b37d9 RK |
4725 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4726 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4727 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4728 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4729 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4730 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
4731 | [(set_attr "type" "fp")]) |
4732 | ||
4733 | (define_insn "" | |
4734 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4735 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4736 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4737 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4738 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4739 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 4740 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4741 | |
4742 | (define_insn "" | |
cd2b37d9 RK |
4743 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4744 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4745 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4746 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4747 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4748 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4749 | [(set_attr "type" "fp")]) |
4750 | ||
4751 | (define_insn "" | |
4752 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4753 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4754 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4755 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
38c1f2d7 | 4756 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
b26c8351 | 4757 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 4758 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4759 | |
ca7f5001 RK |
4760 | (define_expand "sqrtsf2" |
4761 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4762 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 4763 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" |
ca7f5001 RK |
4764 | "") |
4765 | ||
4766 | (define_insn "" | |
4767 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4768 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4769 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT" |
ca7f5001 RK |
4770 | "fsqrts %0,%1" |
4771 | [(set_attr "type" "ssqrt")]) | |
4772 | ||
4773 | (define_insn "" | |
4774 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4775 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4776 | "TARGET_POWER2 && TARGET_HARD_FLOAT" |
ca7f5001 RK |
4777 | "fsqrt %0,%1" |
4778 | [(set_attr "type" "dsqrt")]) | |
4779 | ||
94d7001a RK |
4780 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
4781 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
4782 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 RK |
4783 | ;; combine. |
4784 | (define_expand "maxsf3" | |
4785 | [(set (match_dup 3) | |
4786 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4787 | (match_operand:SF 2 "gpc_reg_operand" ""))) | |
4788 | (set (match_operand:SF 0 "gpc_reg_operand" "") | |
4789 | (if_then_else:SF (ge (match_dup 3) | |
4790 | (const_int 0)) | |
4791 | (match_dup 1) | |
4792 | (match_dup 2)))] | |
d14a6d05 | 4793 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
4794 | " |
4795 | { operands[3] = gen_reg_rtx (SFmode); }") | |
2f607b94 | 4796 | |
8e871c05 RK |
4797 | (define_split |
4798 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4799 | (smax:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
f63184ac | 4800 | (match_operand:SF 2 "gpc_reg_operand" ""))) |
8e871c05 | 4801 | (clobber (match_operand:SF 3 "gpc_reg_operand" ""))] |
d14a6d05 | 4802 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
4803 | [(set (match_dup 3) |
4804 | (minus:SF (match_dup 1) (match_dup 2))) | |
a81bd72f | 4805 | (set (match_dup 0) |
8e871c05 RK |
4806 | (if_then_else:SF (ge (match_dup 3) |
4807 | (const_int 0)) | |
4808 | (match_dup 1) | |
4809 | (match_dup 2)))] | |
4810 | "") | |
2f607b94 | 4811 | |
8e871c05 RK |
4812 | (define_expand "minsf3" |
4813 | [(set (match_dup 3) | |
4814 | (minus:SF (match_operand:SF 2 "gpc_reg_operand" "") | |
4815 | (match_operand:SF 1 "gpc_reg_operand" ""))) | |
4816 | (set (match_operand:SF 0 "gpc_reg_operand" "") | |
4817 | (if_then_else:SF (ge (match_dup 3) | |
4818 | (const_int 0)) | |
4819 | (match_dup 1) | |
4820 | (match_dup 2)))] | |
d14a6d05 | 4821 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
4822 | " |
4823 | { operands[3] = gen_reg_rtx (SFmode); }") | |
2f607b94 | 4824 | |
8e871c05 RK |
4825 | (define_split |
4826 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4827 | (smin:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
f63184ac | 4828 | (match_operand:SF 2 "gpc_reg_operand" ""))) |
8e871c05 | 4829 | (clobber (match_operand:SF 3 "gpc_reg_operand" ""))] |
d14a6d05 | 4830 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
4831 | [(set (match_dup 3) |
4832 | (minus:SF (match_dup 2) (match_dup 1))) | |
a81bd72f | 4833 | (set (match_dup 0) |
8e871c05 RK |
4834 | (if_then_else:SF (ge (match_dup 3) |
4835 | (const_int 0)) | |
4836 | (match_dup 1) | |
4837 | (match_dup 2)))] | |
4838 | "") | |
2f607b94 | 4839 | |
94d7001a | 4840 | (define_expand "movsfcc" |
0ad91047 | 4841 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
94d7001a | 4842 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
4843 | (match_operand:SF 2 "gpc_reg_operand" "") |
4844 | (match_operand:SF 3 "gpc_reg_operand" "")))] | |
d14a6d05 | 4845 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
4846 | " |
4847 | { | |
4848 | rtx temp, op0, op1; | |
4849 | enum rtx_code code = GET_CODE (operands[1]); | |
4850 | if (! rs6000_compare_fp_p) | |
4851 | FAIL; | |
4852 | switch (code) | |
4853 | { | |
4854 | case GE: case EQ: case NE: | |
4855 | op0 = rs6000_compare_op0; | |
4856 | op1 = rs6000_compare_op1; | |
4857 | break; | |
4858 | case GT: | |
4859 | op0 = rs6000_compare_op1; | |
4860 | op1 = rs6000_compare_op0; | |
4861 | temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; | |
4862 | break; | |
4863 | case LE: | |
4864 | op0 = rs6000_compare_op1; | |
4865 | op1 = rs6000_compare_op0; | |
4866 | break; | |
4867 | case LT: | |
4868 | op0 = rs6000_compare_op0; | |
4869 | op1 = rs6000_compare_op1; | |
4870 | temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; | |
4871 | break; | |
4872 | default: | |
4873 | FAIL; | |
4874 | } | |
4875 | if (GET_MODE (rs6000_compare_op0) == DFmode) | |
4876 | { | |
4877 | temp = gen_reg_rtx (DFmode); | |
4878 | emit_insn (gen_subdf3 (temp, op0, op1)); | |
4879 | emit_insn (gen_fseldfsf4 (operands[0], temp, operands[2], operands[3])); | |
4880 | if (code == EQ) | |
4881 | { | |
4882 | emit_insn (gen_negdf2 (temp, temp)); | |
4883 | emit_insn (gen_fseldfsf4 (operands[0], temp, operands[0], operands[3])); | |
4884 | } | |
a6c2a102 | 4885 | else if (code == NE) |
94d7001a RK |
4886 | { |
4887 | emit_insn (gen_negdf2 (temp, temp)); | |
4888 | emit_insn (gen_fseldfsf4 (operands[0], temp, operands[3], operands[0])); | |
4889 | } | |
4890 | } | |
4891 | else | |
4892 | { | |
4893 | temp = gen_reg_rtx (SFmode); | |
4894 | emit_insn (gen_subsf3 (temp, op0, op1)); | |
4895 | emit_insn (gen_fselsfsf4 (operands[0], temp, operands[2], operands[3])); | |
4896 | if (code == EQ) | |
4897 | { | |
4898 | emit_insn (gen_negsf2 (temp, temp)); | |
4899 | emit_insn (gen_fselsfsf4 (operands[0], temp, operands[0], operands[3])); | |
4900 | } | |
a6c2a102 | 4901 | else if (code == NE) |
94d7001a RK |
4902 | { |
4903 | emit_insn (gen_negsf2 (temp, temp)); | |
4904 | emit_insn (gen_fselsfsf4 (operands[0], temp, operands[3], operands[0])); | |
4905 | } | |
4906 | } | |
4907 | DONE; | |
4908 | }") | |
d56d506a | 4909 | |
94d7001a | 4910 | (define_insn "fselsfsf4" |
8e871c05 RK |
4911 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4912 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
4913 | (const_int 0)) | |
4914 | (match_operand:SF 2 "gpc_reg_operand" "f") | |
4915 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4916 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
4917 | "fsel %0,%1,%2,%3" |
4918 | [(set_attr "type" "fp")]) | |
2f607b94 | 4919 | |
94d7001a RK |
4920 | (define_insn "fseldfsf4" |
4921 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4922 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
4923 | (const_int 0)) | |
4924 | (match_operand:SF 2 "gpc_reg_operand" "f") | |
4925 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4926 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
4927 | "fsel %0,%1,%2,%3" |
4928 | [(set_attr "type" "fp")]) | |
d56d506a | 4929 | |
1fd4e8c1 | 4930 | (define_insn "negdf2" |
cd2b37d9 RK |
4931 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4932 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4933 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4934 | "fneg %0,%1" |
4935 | [(set_attr "type" "fp")]) | |
4936 | ||
4937 | (define_insn "absdf2" | |
cd2b37d9 RK |
4938 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4939 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4940 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4941 | "fabs %0,%1" |
4942 | [(set_attr "type" "fp")]) | |
4943 | ||
4944 | (define_insn "" | |
cd2b37d9 RK |
4945 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4946 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
d14a6d05 | 4947 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
4948 | "fnabs %0,%1" |
4949 | [(set_attr "type" "fp")]) | |
4950 | ||
4951 | (define_insn "adddf3" | |
cd2b37d9 RK |
4952 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4953 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4954 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4955 | "TARGET_HARD_FLOAT" |
ca7f5001 | 4956 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
4957 | [(set_attr "type" "fp")]) |
4958 | ||
4959 | (define_insn "subdf3" | |
cd2b37d9 RK |
4960 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4961 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4962 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4963 | "TARGET_HARD_FLOAT" |
ca7f5001 | 4964 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
4965 | [(set_attr "type" "fp")]) |
4966 | ||
4967 | (define_insn "muldf3" | |
cd2b37d9 RK |
4968 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4969 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4970 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4971 | "TARGET_HARD_FLOAT" |
ca7f5001 | 4972 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 4973 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4974 | |
4975 | (define_insn "divdf3" | |
cd2b37d9 RK |
4976 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4977 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4978 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 4979 | "TARGET_HARD_FLOAT" |
ca7f5001 | 4980 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 4981 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4982 | |
4983 | (define_insn "" | |
cd2b37d9 RK |
4984 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4985 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4986 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4987 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3b7e5ef4 | 4988 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 4989 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 4990 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4991 | |
4992 | (define_insn "" | |
cd2b37d9 RK |
4993 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4994 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4995 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4996 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
3b7e5ef4 | 4997 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 4998 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 4999 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5000 | |
5001 | (define_insn "" | |
cd2b37d9 RK |
5002 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5003 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5004 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5005 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
3b7e5ef4 | 5006 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 5007 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 5008 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5009 | |
5010 | (define_insn "" | |
cd2b37d9 RK |
5011 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5012 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5013 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5014 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
3b7e5ef4 | 5015 | "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" |
ca7f5001 | 5016 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 5017 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
5018 | |
5019 | (define_insn "sqrtdf2" | |
5020 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5021 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5022 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" |
ca7f5001 RK |
5023 | "fsqrt %0,%1" |
5024 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 5025 | |
94d7001a RK |
5026 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
5027 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
5028 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 | 5029 | ;; combine. |
b77dfefc | 5030 | |
8e871c05 RK |
5031 | (define_expand "maxdf3" |
5032 | [(set (match_dup 3) | |
5033 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
5034 | (match_operand:DF 2 "gpc_reg_operand" ""))) | |
5035 | (set (match_operand:DF 0 "gpc_reg_operand" "") | |
5036 | (if_then_else:DF (ge (match_dup 3) | |
5037 | (const_int 0)) | |
5038 | (match_dup 1) | |
5039 | (match_dup 2)))] | |
d14a6d05 | 5040 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
5041 | " |
5042 | { operands[3] = gen_reg_rtx (DFmode); }") | |
b77dfefc | 5043 | |
8e871c05 RK |
5044 | (define_split |
5045 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5046 | (smax:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
f63184ac | 5047 | (match_operand:DF 2 "gpc_reg_operand" ""))) |
8e871c05 | 5048 | (clobber (match_operand:DF 3 "gpc_reg_operand" ""))] |
d14a6d05 | 5049 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
5050 | [(set (match_dup 3) |
5051 | (minus:DF (match_dup 1) (match_dup 2))) | |
a81bd72f | 5052 | (set (match_dup 0) |
8e871c05 RK |
5053 | (if_then_else:DF (ge (match_dup 3) |
5054 | (const_int 0)) | |
5055 | (match_dup 1) | |
5056 | (match_dup 2)))] | |
5057 | "") | |
b77dfefc | 5058 | |
8e871c05 RK |
5059 | (define_expand "mindf3" |
5060 | [(set (match_dup 3) | |
5061 | (minus:DF (match_operand:DF 2 "gpc_reg_operand" "") | |
5062 | (match_operand:DF 1 "gpc_reg_operand" ""))) | |
5063 | (set (match_operand:DF 0 "gpc_reg_operand" "") | |
5064 | (if_then_else:DF (ge (match_dup 3) | |
5065 | (const_int 0)) | |
5066 | (match_dup 1) | |
5067 | (match_dup 2)))] | |
d14a6d05 | 5068 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
5069 | " |
5070 | { operands[3] = gen_reg_rtx (DFmode); }") | |
b77dfefc | 5071 | |
8e871c05 RK |
5072 | (define_split |
5073 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5074 | (smin:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
f63184ac | 5075 | (match_operand:DF 2 "gpc_reg_operand" ""))) |
8e871c05 | 5076 | (clobber (match_operand:DF 3 "gpc_reg_operand" ""))] |
d14a6d05 | 5077 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
5078 | [(set (match_dup 3) |
5079 | (minus:DF (match_dup 2) (match_dup 1))) | |
a81bd72f | 5080 | (set (match_dup 0) |
8e871c05 RK |
5081 | (if_then_else:DF (ge (match_dup 3) |
5082 | (const_int 0)) | |
5083 | (match_dup 1) | |
5084 | (match_dup 2)))] | |
5085 | "") | |
b77dfefc | 5086 | |
94d7001a | 5087 | (define_expand "movdfcc" |
0ad91047 | 5088 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
94d7001a | 5089 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
5090 | (match_operand:DF 2 "gpc_reg_operand" "") |
5091 | (match_operand:DF 3 "gpc_reg_operand" "")))] | |
d14a6d05 | 5092 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
94d7001a RK |
5093 | " |
5094 | { | |
5095 | rtx temp, op0, op1; | |
5096 | enum rtx_code code = GET_CODE (operands[1]); | |
5097 | if (! rs6000_compare_fp_p) | |
5098 | FAIL; | |
5099 | switch (code) | |
5100 | { | |
5101 | case GE: case EQ: case NE: | |
5102 | op0 = rs6000_compare_op0; | |
5103 | op1 = rs6000_compare_op1; | |
5104 | break; | |
5105 | case GT: | |
5106 | op0 = rs6000_compare_op1; | |
5107 | op1 = rs6000_compare_op0; | |
5108 | temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; | |
5109 | break; | |
5110 | case LE: | |
5111 | op0 = rs6000_compare_op1; | |
5112 | op1 = rs6000_compare_op0; | |
5113 | break; | |
5114 | case LT: | |
5115 | op0 = rs6000_compare_op0; | |
5116 | op1 = rs6000_compare_op1; | |
5117 | temp = operands[2]; operands[2] = operands[3]; operands[3] = temp; | |
5118 | break; | |
5119 | default: | |
5120 | FAIL; | |
5121 | } | |
5122 | if (GET_MODE (rs6000_compare_op0) == DFmode) | |
5123 | { | |
5124 | temp = gen_reg_rtx (DFmode); | |
5125 | emit_insn (gen_subdf3 (temp, op0, op1)); | |
5126 | emit_insn (gen_fseldfdf4 (operands[0], temp, operands[2], operands[3])); | |
5127 | if (code == EQ) | |
5128 | { | |
5129 | emit_insn (gen_negdf2 (temp, temp)); | |
5130 | emit_insn (gen_fseldfdf4 (operands[0], temp, operands[0], operands[3])); | |
5131 | } | |
a6c2a102 | 5132 | else if (code == NE) |
94d7001a RK |
5133 | { |
5134 | emit_insn (gen_negdf2 (temp, temp)); | |
5135 | emit_insn (gen_fseldfdf4 (operands[0], temp, operands[3], operands[0])); | |
5136 | } | |
5137 | } | |
5138 | else | |
5139 | { | |
5140 | temp = gen_reg_rtx (SFmode); | |
5141 | emit_insn (gen_subsf3 (temp, op0, op1)); | |
5142 | emit_insn (gen_fselsfdf4 (operands[0], temp, operands[2], operands[3])); | |
5143 | if (code == EQ) | |
5144 | { | |
5145 | emit_insn (gen_negsf2 (temp, temp)); | |
5146 | emit_insn (gen_fselsfdf4 (operands[0], temp, operands[0], operands[3])); | |
5147 | } | |
a6c2a102 | 5148 | else if (code == NE) |
94d7001a RK |
5149 | { |
5150 | emit_insn (gen_negsf2 (temp, temp)); | |
5151 | emit_insn (gen_fselsfdf4 (operands[0], temp, operands[3], operands[0])); | |
5152 | } | |
5153 | } | |
5154 | DONE; | |
5155 | }") | |
d56d506a | 5156 | |
94d7001a | 5157 | (define_insn "fseldfdf4" |
8e871c05 RK |
5158 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5159 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
5160 | (const_int 0)) | |
5161 | (match_operand:DF 2 "gpc_reg_operand" "f") | |
5162 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5163 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" |
8e871c05 RK |
5164 | "fsel %0,%1,%2,%3" |
5165 | [(set_attr "type" "fp")]) | |
d56d506a | 5166 | |
94d7001a RK |
5167 | (define_insn "fselsfdf4" |
5168 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5169 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
5170 | (const_int 0)) | |
5171 | (match_operand:DF 2 "gpc_reg_operand" "f") | |
5172 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
5173 | "TARGET_PPC_GFXOPT" | |
5174 | "fsel %0,%1,%2,%3" | |
5175 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
5176 | \f |
5177 | ;; Conversions to and from floating-point. | |
802a0058 | 5178 | |
9ebbca7d GK |
5179 | ; For each of these conversions, there is a define_expand, a define_insn |
5180 | ; with a '#' template, and a define_split (with C code). The idea is | |
5181 | ; to allow constant folding with the template of the define_insn, | |
5182 | ; then to have the insns split later (between sched1 and final). | |
5183 | ||
1fd4e8c1 | 5184 | (define_expand "floatsidf2" |
802a0058 MM |
5185 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5186 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5187 | (use (match_dup 2)) | |
5188 | (use (match_dup 3)) | |
208c89ce | 5189 | (clobber (match_dup 4)) |
a7df97e6 | 5190 | (clobber (match_dup 5)) |
9ebbca7d | 5191 | (clobber (match_dup 6))])] |
31bfaa0b | 5192 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5193 | " |
5194 | { | |
802a0058 MM |
5195 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5196 | operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode)); | |
9ebbca7d GK |
5197 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5198 | operands[5] = gen_reg_rtx (DFmode); | |
5199 | operands[6] = gen_reg_rtx (SImode); | |
1fd4e8c1 RK |
5200 | }") |
5201 | ||
802a0058 MM |
5202 | (define_insn "*floatsidf2_internal" |
5203 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5204 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5205 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5206 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d GK |
5207 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
5208 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=f")) | |
5209 | (clobber (match_operand:SI 6 "gpc_reg_operand" "=r"))] | |
31bfaa0b | 5210 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
802a0058 | 5211 | "#" |
a7df97e6 | 5212 | [(set_attr "length" "24")]) |
802a0058 MM |
5213 | |
5214 | (define_split | |
dbe3df29 | 5215 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
802a0058 MM |
5216 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) |
5217 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5218 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5219 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5220 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5221 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
31bfaa0b | 5222 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
9ebbca7d GK |
5223 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5224 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5225 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5226 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5227 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5228 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5229 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
208c89ce MM |
5230 | " |
5231 | { | |
9ebbca7d GK |
5232 | rtx lowword, highword; |
5233 | if (GET_CODE (operands[4]) != MEM) | |
5234 | abort(); | |
5235 | highword = XEXP (operands[4], 0); | |
5236 | lowword = plus_constant (highword, 4); | |
5237 | if (! WORDS_BIG_ENDIAN) | |
5238 | { | |
5239 | rtx tmp; | |
5240 | tmp = highword; highword = lowword; lowword = tmp; | |
5241 | } | |
5242 | ||
5243 | emit_insn (gen_xorsi3 (operands[6], operands[1], | |
5244 | GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); | |
5245 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]); | |
5246 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5247 | emit_move_insn (operands[5], operands[4]); | |
5248 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5249 | DONE; | |
208c89ce | 5250 | }") |
802a0058 MM |
5251 | |
5252 | (define_expand "floatunssidf2" | |
5253 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5254 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5255 | (use (match_dup 2)) | |
5256 | (use (match_dup 3)) | |
a7df97e6 | 5257 | (clobber (match_dup 4)) |
9ebbca7d | 5258 | (clobber (match_dup 5))])] |
31bfaa0b | 5259 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5260 | " |
5261 | { | |
802a0058 MM |
5262 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5263 | operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode)); | |
9ebbca7d GK |
5264 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5265 | operands[5] = gen_reg_rtx (DFmode); | |
1fd4e8c1 RK |
5266 | }") |
5267 | ||
802a0058 MM |
5268 | (define_insn "*floatunssidf2_internal" |
5269 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5270 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5271 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5272 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d GK |
5273 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
5274 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))] | |
31bfaa0b | 5275 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
802a0058 | 5276 | "#" |
a7df97e6 | 5277 | [(set_attr "length" "20")]) |
802a0058 MM |
5278 | |
5279 | (define_split | |
5280 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5281 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5282 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5283 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5284 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5285 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
31bfaa0b | 5286 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
9ebbca7d GK |
5287 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5288 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5289 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5290 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5291 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5292 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
5293 | " | |
802a0058 | 5294 | { |
9ebbca7d GK |
5295 | rtx lowword, highword; |
5296 | if (GET_CODE (operands[4]) != MEM) | |
5297 | abort(); | |
5298 | highword = XEXP (operands[4], 0); | |
5299 | lowword = plus_constant (highword, 4); | |
5300 | if (! WORDS_BIG_ENDIAN) | |
f6968f59 | 5301 | { |
9ebbca7d GK |
5302 | rtx tmp; |
5303 | tmp = highword; highword = lowword; lowword = tmp; | |
f6968f59 | 5304 | } |
802a0058 | 5305 | |
9ebbca7d GK |
5306 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]); |
5307 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5308 | emit_move_insn (operands[5], operands[4]); | |
5309 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5310 | DONE; | |
5311 | }") | |
1fd4e8c1 | 5312 | |
1fd4e8c1 | 5313 | (define_expand "fix_truncdfsi2" |
802a0058 MM |
5314 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
5315 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) | |
5316 | (clobber (match_dup 2)) | |
9ebbca7d | 5317 | (clobber (match_dup 3))])] |
d14a6d05 | 5318 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5319 | " |
5320 | { | |
31bfaa0b | 5321 | if (! TARGET_POWER2 && ! TARGET_POWERPC) |
8ffd9c51 RK |
5322 | { |
5323 | emit_insn (gen_trunc_call (operands[0], operands[1], | |
39403d82 | 5324 | gen_rtx_SYMBOL_REF (Pmode, RS6000_ITRUNC))); |
8ffd9c51 RK |
5325 | DONE; |
5326 | } | |
802a0058 MM |
5327 | |
5328 | operands[2] = gen_reg_rtx (DImode); | |
9ebbca7d | 5329 | operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); |
1fd4e8c1 RK |
5330 | }") |
5331 | ||
802a0058 MM |
5332 | (define_insn "*fix_truncdfsi2_internal" |
5333 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5334 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
5335 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) | |
9ebbca7d | 5336 | (clobber (match_operand:DI 3 "memory_operand" "=o"))] |
802a0058 MM |
5337 | "TARGET_HARD_FLOAT" |
5338 | "#" | |
9ebbca7d | 5339 | [(set_attr "length" "16")]) |
802a0058 MM |
5340 | |
5341 | (define_split | |
5342 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5343 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
5344 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) | |
9ebbca7d | 5345 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] |
802a0058 | 5346 | "TARGET_HARD_FLOAT" |
9ebbca7d GK |
5347 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
5348 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
5349 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) | |
5350 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] | |
5351 | " | |
802a0058 | 5352 | { |
9ebbca7d GK |
5353 | rtx lowword; |
5354 | if (GET_CODE (operands[3]) != MEM) | |
5355 | abort(); | |
5356 | lowword = XEXP (operands[3], 0); | |
5357 | if (WORDS_BIG_ENDIAN) | |
5358 | lowword = plus_constant (lowword, 4); | |
802a0058 | 5359 | |
9ebbca7d GK |
5360 | emit_insn (gen_fctiwz (operands[2], operands[1])); |
5361 | emit_move_insn (operands[3], operands[2]); | |
5362 | emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); | |
5363 | DONE; | |
5364 | }") | |
802a0058 | 5365 | |
1fd4e8c1 | 5366 | (define_expand "fixuns_truncdfsi2" |
cd2b37d9 | 5367 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
b542afe9 | 5368 | (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))] |
d14a6d05 | 5369 | "! TARGET_POWER2 && ! TARGET_POWERPC && TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5370 | " |
5371 | { | |
5372 | emit_insn (gen_trunc_call (operands[0], operands[1], | |
39403d82 | 5373 | gen_rtx_SYMBOL_REF (Pmode, RS6000_UITRUNC))); |
1fd4e8c1 RK |
5374 | DONE; |
5375 | }") | |
5376 | ||
1fd4e8c1 RK |
5377 | (define_expand "trunc_call" |
5378 | [(parallel [(set (match_operand:SI 0 "" "") | |
b542afe9 | 5379 | (fix:SI (match_operand:DF 1 "" ""))) |
1fd4e8c1 | 5380 | (use (match_operand:SI 2 "" ""))])] |
d14a6d05 | 5381 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
5382 | " |
5383 | { | |
5384 | rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]); | |
5385 | rtx first = XVECEXP (insns, 0, 0); | |
5386 | rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1); | |
5387 | ||
39403d82 | 5388 | REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last, |
c5c76735 | 5389 | REG_NOTES (first)); |
39403d82 | 5390 | REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last)); |
1fd4e8c1 RK |
5391 | |
5392 | emit_insn (insns); | |
5393 | DONE; | |
5394 | }") | |
5395 | ||
5396 | (define_expand "trunc_call_rtl" | |
cd2b37d9 | 5397 | [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" "")) |
1fd4e8c1 RK |
5398 | (use (reg:DF 33)) |
5399 | (parallel [(set (reg:SI 3) | |
5400 | (call (mem:SI (match_operand 2 "" "")) (const_int 0))) | |
4697a36c | 5401 | (use (const_int 0)) |
1fd4e8c1 | 5402 | (clobber (scratch:SI))]) |
cd2b37d9 | 5403 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 5404 | (reg:SI 3))] |
d14a6d05 | 5405 | "TARGET_HARD_FLOAT" |
1fd4e8c1 | 5406 | " |
7e69e155 | 5407 | { |
1fd4e8c1 RK |
5408 | rs6000_trunc_used = 1; |
5409 | }") | |
a473029f | 5410 | |
9ebbca7d GK |
5411 | ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] 10)) |
5412 | ; rather than (set (subreg:SI (reg)) (fix:SI ...)) | |
5413 | ; because the first makes it clear that operand 0 is not live | |
5414 | ; before the instruction. | |
5415 | (define_insn "fctiwz" | |
5416 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") | |
5417 | (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))] | |
a260abc9 DE |
5418 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" |
5419 | "{fcirz|fctiwz} %0,%1" | |
5420 | [(set_attr "type" "fp")]) | |
5421 | ||
a473029f RK |
5422 | (define_insn "floatdidf2" |
5423 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5424 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5425 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
a473029f RK |
5426 | "fcfid %0,%1" |
5427 | [(set_attr "type" "fp")]) | |
5428 | ||
5429 | (define_insn "fix_truncdfdi2" | |
5430 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") | |
5431 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
d14a6d05 | 5432 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT" |
a473029f RK |
5433 | "fctidz %0,%1" |
5434 | [(set_attr "type" "fp")]) | |
1fd4e8c1 RK |
5435 | \f |
5436 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
5437 | ;; of instructions. The & constraints are to prevent the register |
5438 | ;; allocator from allocating registers that overlap with the inputs | |
5439 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 5440 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 5441 | |
266eb58a | 5442 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
5443 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
5444 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
5445 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 5446 | "! TARGET_POWERPC64" |
0f645302 MM |
5447 | "* |
5448 | { | |
5449 | if (WORDS_BIG_ENDIAN) | |
5450 | return (GET_CODE (operands[2])) != CONST_INT | |
5451 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
5452 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
5453 | else | |
5454 | return (GET_CODE (operands[2])) != CONST_INT | |
5455 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
5456 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
5457 | }" | |
b19003d8 | 5458 | [(set_attr "length" "8")]) |
1fd4e8c1 | 5459 | |
266eb58a | 5460 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
5461 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
5462 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
5463 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 5464 | "! TARGET_POWERPC64" |
5502823b RK |
5465 | "* |
5466 | { | |
0f645302 MM |
5467 | if (WORDS_BIG_ENDIAN) |
5468 | return (GET_CODE (operands[1]) != CONST_INT) | |
5469 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
5470 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
5471 | else | |
5472 | return (GET_CODE (operands[1]) != CONST_INT) | |
5473 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
5474 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 5475 | }" |
ca7f5001 RK |
5476 | [(set_attr "length" "8")]) |
5477 | ||
266eb58a | 5478 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
5479 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5480 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 5481 | "! TARGET_POWERPC64" |
5502823b RK |
5482 | "* |
5483 | { | |
5484 | return (WORDS_BIG_ENDIAN) | |
5485 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
5486 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
5487 | }" | |
ca7f5001 RK |
5488 | [(set_attr "length" "8")]) |
5489 | ||
8ffd9c51 RK |
5490 | (define_expand "mulsidi3" |
5491 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5492 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5493 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 5494 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
5495 | " |
5496 | { | |
5497 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5498 | { | |
39403d82 DE |
5499 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5500 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5501 | emit_insn (gen_mull_call ()); |
cf27b467 | 5502 | if (WORDS_BIG_ENDIAN) |
39403d82 | 5503 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
5504 | else |
5505 | { | |
5506 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 5507 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 5508 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 5509 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 5510 | } |
8ffd9c51 RK |
5511 | DONE; |
5512 | } | |
5513 | else if (TARGET_POWER) | |
5514 | { | |
5515 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
5516 | DONE; | |
5517 | } | |
5518 | }") | |
deb9225a | 5519 | |
8ffd9c51 | 5520 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 5521 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 5522 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 5523 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 5524 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 5525 | "TARGET_POWER" |
b19003d8 | 5526 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
5527 | [(set_attr "type" "imul") |
5528 | (set_attr "length" "8")]) | |
deb9225a | 5529 | |
f192bf8b | 5530 | (define_insn "*mulsidi3_no_mq" |
425c176f | 5531 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
5532 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
5533 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5534 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
5535 | "* |
5536 | { | |
5537 | return (WORDS_BIG_ENDIAN) | |
5538 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
5539 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
5540 | }" | |
8ffd9c51 RK |
5541 | [(set_attr "type" "imul") |
5542 | (set_attr "length" "8")]) | |
deb9225a | 5543 | |
ebedb4dd MM |
5544 | (define_split |
5545 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5546 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5547 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5548 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5549 | [(set (match_dup 3) |
5550 | (truncate:SI | |
5551 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
5552 | (sign_extend:DI (match_dup 2))) | |
5553 | (const_int 32)))) | |
5554 | (set (match_dup 4) | |
5555 | (mult:SI (match_dup 1) | |
5556 | (match_dup 2)))] | |
5557 | " | |
5558 | { | |
5559 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5560 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5561 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5562 | }") | |
5563 | ||
f192bf8b DE |
5564 | (define_expand "umulsidi3" |
5565 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5566 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5567 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
5568 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
5569 | " | |
5570 | { | |
5571 | if (TARGET_POWER) | |
5572 | { | |
5573 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
5574 | DONE; | |
5575 | } | |
5576 | }") | |
5577 | ||
5578 | (define_insn "umulsidi3_mq" | |
5579 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5580 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5581 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
5582 | (clobber (match_scratch:SI 3 "=q"))] | |
5583 | "TARGET_POWERPC && TARGET_POWER" | |
5584 | "* | |
5585 | { | |
5586 | return (WORDS_BIG_ENDIAN) | |
5587 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5588 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5589 | }" | |
5590 | [(set_attr "type" "imul") | |
5591 | (set_attr "length" "8")]) | |
5592 | ||
5593 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
5594 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
5595 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5596 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5597 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
5598 | "* |
5599 | { | |
5600 | return (WORDS_BIG_ENDIAN) | |
5601 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5602 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5603 | }" | |
5604 | [(set_attr "type" "imul") | |
5605 | (set_attr "length" "8")]) | |
5606 | ||
ebedb4dd MM |
5607 | (define_split |
5608 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5609 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5610 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5611 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5612 | [(set (match_dup 3) |
5613 | (truncate:SI | |
5614 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
5615 | (zero_extend:DI (match_dup 2))) | |
5616 | (const_int 32)))) | |
5617 | (set (match_dup 4) | |
5618 | (mult:SI (match_dup 1) | |
5619 | (match_dup 2)))] | |
5620 | " | |
5621 | { | |
5622 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5623 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5624 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5625 | }") | |
5626 | ||
8ffd9c51 RK |
5627 | (define_expand "smulsi3_highpart" |
5628 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5629 | (truncate:SI | |
5630 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
5631 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5632 | (sign_extend:DI | |
5633 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5634 | (const_int 32))))] | |
5635 | "" | |
5636 | " | |
5637 | { | |
5638 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5639 | { | |
39403d82 DE |
5640 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5641 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5642 | emit_insn (gen_mulh_call ()); |
39403d82 | 5643 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
5644 | DONE; |
5645 | } | |
5646 | else if (TARGET_POWER) | |
5647 | { | |
5648 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5649 | DONE; | |
5650 | } | |
5651 | }") | |
deb9225a | 5652 | |
8ffd9c51 RK |
5653 | (define_insn "smulsi3_highpart_mq" |
5654 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5655 | (truncate:SI | |
fada905b MM |
5656 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5657 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5658 | (sign_extend:DI | |
5659 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
5660 | (const_int 32)))) |
5661 | (clobber (match_scratch:SI 3 "=q"))] | |
5662 | "TARGET_POWER" | |
5663 | "mul %0,%1,%2" | |
5664 | [(set_attr "type" "imul")]) | |
deb9225a | 5665 | |
f192bf8b | 5666 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
5667 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5668 | (truncate:SI | |
fada905b MM |
5669 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5670 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5671 | (sign_extend:DI | |
5672 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 5673 | (const_int 32))))] |
f192bf8b | 5674 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
5675 | "mulhw %0,%1,%2" |
5676 | [(set_attr "type" "imul")]) | |
deb9225a | 5677 | |
f192bf8b DE |
5678 | (define_expand "umulsi3_highpart" |
5679 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5680 | (truncate:SI | |
5681 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5682 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
5683 | (zero_extend:DI | |
5684 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
5685 | (const_int 32))))] | |
5686 | "TARGET_POWERPC" | |
5687 | " | |
5688 | { | |
5689 | if (TARGET_POWER) | |
5690 | { | |
5691 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5692 | DONE; | |
5693 | } | |
5694 | }") | |
5695 | ||
5696 | (define_insn "umulsi3_highpart_mq" | |
5697 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5698 | (truncate:SI | |
5699 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5700 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5701 | (zero_extend:DI | |
5702 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5703 | (const_int 32)))) | |
5704 | (clobber (match_scratch:SI 3 "=q"))] | |
5705 | "TARGET_POWERPC && TARGET_POWER" | |
5706 | "mulhwu %0,%1,%2" | |
5707 | [(set_attr "type" "imul")]) | |
5708 | ||
5709 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
5710 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5711 | (truncate:SI | |
5712 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5713 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5714 | (zero_extend:DI | |
5715 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5716 | (const_int 32))))] | |
f192bf8b | 5717 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
5718 | "mulhwu %0,%1,%2" |
5719 | [(set_attr "type" "imul")]) | |
5720 | ||
5721 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
5722 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
5723 | ;; why we have the strange constraints below. | |
5724 | (define_insn "ashldi3_power" | |
5725 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
5726 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
5727 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5728 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5729 | "TARGET_POWER" | |
5730 | "@ | |
5731 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
5732 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5733 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5734 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
5735 | [(set_attr "length" "8")]) | |
5736 | ||
5737 | (define_insn "lshrdi3_power" | |
47ad8c61 | 5738 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
5739 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
5740 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5741 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5742 | "TARGET_POWER" | |
5743 | "@ | |
47ad8c61 | 5744 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
5745 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
5746 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
5747 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
5748 | [(set_attr "length" "8")]) | |
5749 | ||
5750 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
5751 | ;; just handle shifts by constants. | |
5752 | (define_insn "ashrdi3_power" | |
7093ddee | 5753 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
5754 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
5755 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
5756 | (clobber (match_scratch:SI 3 "=X,q"))] | |
5757 | "TARGET_POWER" | |
5758 | "@ | |
5759 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5760 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
5761 | [(set_attr "length" "8")]) | |
5762 | \f | |
5763 | ;; PowerPC64 DImode operations. | |
5764 | ||
5765 | (define_expand "adddi3" | |
5766 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5767 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
a260abc9 | 5768 | (match_operand:DI 2 "reg_or_cint_operand" "")))] |
266eb58a DE |
5769 | "" |
5770 | " | |
5771 | { | |
a260abc9 DE |
5772 | if (! TARGET_POWERPC64) |
5773 | { | |
5774 | if (non_short_cint_operand (operands[2], DImode)) | |
5775 | FAIL; | |
5776 | } | |
5777 | else | |
5778 | if (GET_CODE (operands[2]) == CONST_INT | |
677a9668 | 5779 | && ! add_operand (operands[2], DImode)) |
a260abc9 | 5780 | { |
677a9668 | 5781 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
5782 | ? operands[0] : gen_reg_rtx (DImode)); |
5783 | ||
5784 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; | |
5785 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
5786 | ||
5787 | if (low & 0x8000) | |
5788 | high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16; | |
5789 | ||
5790 | emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (high))); | |
5791 | emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low))); | |
5792 | DONE; | |
5793 | } | |
266eb58a DE |
5794 | }") |
5795 | ||
5796 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
5797 | ;; allowing register zero as source. | |
5798 | ||
a260abc9 | 5799 | (define_insn "*adddi3_internal1" |
266eb58a DE |
5800 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r") |
5801 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 5802 | (match_operand:DI 2 "add_operand" "r,I,I,L")))] |
266eb58a DE |
5803 | "TARGET_POWERPC64" |
5804 | "@ | |
5805 | add %0,%1,%2 | |
5806 | addi %0,%1,%2 | |
5807 | addic %0,%1,%2 | |
802a0058 | 5808 | addis %0,%1,%v2") |
266eb58a | 5809 | |
a260abc9 | 5810 | (define_insn "*adddi3_internal2" |
9ebbca7d GK |
5811 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
5812 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5813 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5814 | (const_int 0))) |
9ebbca7d | 5815 | (clobber (match_scratch:DI 3 "=r,r,r,r"))] |
266eb58a DE |
5816 | "TARGET_POWERPC64" |
5817 | "@ | |
5818 | add. %3,%1,%2 | |
9ebbca7d GK |
5819 | addic. %3,%1,%2 |
5820 | # | |
5821 | #" | |
5822 | [(set_attr "type" "compare") | |
5823 | (set_attr "length" "4,4,8,8")]) | |
5824 | ||
5825 | (define_split | |
5826 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5827 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5828 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5829 | (const_int 0))) | |
5830 | (clobber (match_scratch:DI 3 ""))] | |
5831 | "TARGET_POWERPC64 && reload_completed" | |
5832 | [(set (match_dup 3) | |
5833 | (plus:DI (match_dup 1) (match_dup 2))) | |
5834 | (set (match_dup 0) | |
5835 | (compare:CC (match_dup 3) | |
5836 | (const_int 0)))] | |
5837 | "") | |
266eb58a | 5838 | |
a260abc9 | 5839 | (define_insn "*adddi3_internal3" |
9ebbca7d GK |
5840 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
5841 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5842 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5843 | (const_int 0))) |
9ebbca7d | 5844 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
266eb58a DE |
5845 | (plus:DI (match_dup 1) (match_dup 2)))] |
5846 | "TARGET_POWERPC64" | |
5847 | "@ | |
5848 | add. %0,%1,%2 | |
9ebbca7d GK |
5849 | addic. %0,%1,%2 |
5850 | # | |
5851 | #" | |
5852 | [(set_attr "type" "compare") | |
5853 | (set_attr "length" "4,4,8,8")]) | |
5854 | ||
5855 | (define_split | |
5856 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5857 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5858 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5859 | (const_int 0))) | |
5860 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5861 | (plus:DI (match_dup 1) (match_dup 2)))] | |
5862 | "TARGET_POWERPC64 && reload_completed" | |
5863 | [(set (match_dup 0) | |
5864 | (plus:DI (match_dup 1) (match_dup 2))) | |
5865 | (set (match_dup 3) | |
5866 | (compare:CC (match_dup 0) | |
5867 | (const_int 0)))] | |
5868 | "") | |
266eb58a DE |
5869 | |
5870 | ;; Split an add that we can't do in one insn into two insns, each of which | |
5871 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
5872 | ;; add should be last in case the result gets used in an address. | |
5873 | ||
5874 | (define_split | |
5875 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5876 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5877 | (match_operand:DI 2 "non_add_cint_operand" "")))] | |
5878 | "TARGET_POWERPC64" | |
5879 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) | |
5880 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] | |
5881 | " | |
5882 | { | |
e6ca2c17 DE |
5883 | HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff; |
5884 | HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff); | |
266eb58a DE |
5885 | |
5886 | if (low & 0x8000) | |
e6ca2c17 | 5887 | high+=0x10000, low |= ((HOST_WIDE_INT) -1) << 16; |
266eb58a | 5888 | |
e6ca2c17 DE |
5889 | operands[3] = GEN_INT (high); |
5890 | operands[4] = GEN_INT (low); | |
266eb58a DE |
5891 | }") |
5892 | ||
5893 | (define_insn "one_cmpldi2" | |
5894 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5895 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5896 | "TARGET_POWERPC64" | |
5897 | "nor %0,%1,%1") | |
5898 | ||
5899 | (define_insn "" | |
9ebbca7d GK |
5900 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5901 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5902 | (const_int 0))) |
9ebbca7d | 5903 | (clobber (match_scratch:DI 2 "=r,r"))] |
266eb58a | 5904 | "TARGET_POWERPC64" |
9ebbca7d GK |
5905 | "@ |
5906 | nor. %2,%1,%1 | |
5907 | #" | |
5908 | [(set_attr "type" "compare") | |
5909 | (set_attr "length" "4,8")]) | |
5910 | ||
5911 | (define_split | |
5912 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5913 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5914 | (const_int 0))) | |
5915 | (clobber (match_scratch:DI 2 ""))] | |
5916 | "TARGET_POWERPC64 && reload_completed" | |
5917 | [(set (match_dup 2) | |
5918 | (not:DI (match_dup 1))) | |
5919 | (set (match_dup 0) | |
5920 | (compare:CC (match_dup 2) | |
5921 | (const_int 0)))] | |
5922 | "") | |
266eb58a DE |
5923 | |
5924 | (define_insn "" | |
9ebbca7d GK |
5925 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
5926 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5927 | (const_int 0))) |
9ebbca7d | 5928 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
5929 | (not:DI (match_dup 1)))] |
5930 | "TARGET_POWERPC64" | |
9ebbca7d GK |
5931 | "@ |
5932 | nor. %0,%1,%1 | |
5933 | #" | |
5934 | [(set_attr "type" "compare") | |
5935 | (set_attr "length" "4,8")]) | |
5936 | ||
5937 | (define_split | |
5938 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
5939 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5940 | (const_int 0))) | |
5941 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5942 | (not:DI (match_dup 1)))] | |
5943 | "TARGET_POWERPC64 && reload_completed" | |
5944 | [(set (match_dup 0) | |
5945 | (not:DI (match_dup 1))) | |
5946 | (set (match_dup 2) | |
5947 | (compare:CC (match_dup 0) | |
5948 | (const_int 0)))] | |
5949 | "") | |
266eb58a DE |
5950 | |
5951 | (define_insn "" | |
5952 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
5953 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") | |
5954 | (match_operand:DI 2 "gpc_reg_operand" "r,r")))] | |
5955 | "TARGET_POWERPC64" | |
5956 | "@ | |
5957 | subf %0,%2,%1 | |
5958 | subfic %0,%2,%1") | |
5959 | ||
5960 | (define_insn "" | |
9ebbca7d GK |
5961 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5962 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5963 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 5964 | (const_int 0))) |
9ebbca7d | 5965 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 5966 | "TARGET_POWERPC64" |
9ebbca7d GK |
5967 | "@ |
5968 | subf. %3,%2,%1 | |
5969 | #" | |
5970 | [(set_attr "type" "compare") | |
5971 | (set_attr "length" "4,8")]) | |
5972 | ||
5973 | (define_split | |
5974 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5975 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5976 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5977 | (const_int 0))) | |
5978 | (clobber (match_scratch:DI 3 ""))] | |
5979 | "TARGET_POWERPC64 && reload_completed" | |
5980 | [(set (match_dup 3) | |
5981 | (minus:DI (match_dup 1) (match_dup 2))) | |
5982 | (set (match_dup 0) | |
5983 | (compare:CC (match_dup 3) | |
5984 | (const_int 0)))] | |
5985 | "") | |
266eb58a DE |
5986 | |
5987 | (define_insn "" | |
9ebbca7d GK |
5988 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
5989 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5990 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 5991 | (const_int 0))) |
9ebbca7d | 5992 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
5993 | (minus:DI (match_dup 1) (match_dup 2)))] |
5994 | "TARGET_POWERPC64" | |
9ebbca7d GK |
5995 | "@ |
5996 | subf. %0,%2,%1 | |
5997 | #" | |
5998 | [(set_attr "type" "compare") | |
5999 | (set_attr "length" "4,8")]) | |
6000 | ||
6001 | (define_split | |
6002 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6003 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6004 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6005 | (const_int 0))) | |
6006 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6007 | (minus:DI (match_dup 1) (match_dup 2)))] | |
6008 | "TARGET_POWERPC64 && reload_completed" | |
6009 | [(set (match_dup 0) | |
6010 | (minus:DI (match_dup 1) (match_dup 2))) | |
6011 | (set (match_dup 3) | |
6012 | (compare:CC (match_dup 0) | |
6013 | (const_int 0)))] | |
6014 | "") | |
266eb58a DE |
6015 | |
6016 | (define_expand "subdi3" | |
6017 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6018 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") | |
6019 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
6020 | "" | |
6021 | " | |
6022 | { | |
6023 | if (GET_CODE (operands[2]) == CONST_INT) | |
6024 | { | |
6025 | emit_insn (gen_adddi3 (operands[0], operands[1], | |
6026 | negate_rtx (DImode, operands[2]))); | |
6027 | DONE; | |
6028 | } | |
6029 | }") | |
6030 | ||
6031 | (define_insn "absdi2" | |
6032 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
6033 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) | |
6034 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
6035 | "TARGET_POWERPC64" | |
a260abc9 | 6036 | "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0" |
266eb58a DE |
6037 | [(set_attr "length" "12")]) |
6038 | ||
6039 | (define_split | |
6040 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
6041 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) | |
6042 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
6043 | "TARGET_POWERPC64 && reload_completed" | |
a260abc9 | 6044 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 6045 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 6046 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
6047 | "") |
6048 | ||
19ba8161 | 6049 | (define_insn "*nabsdi2" |
266eb58a DE |
6050 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
6051 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) | |
6052 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
6053 | "TARGET_POWERPC64" | |
a260abc9 | 6054 | "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2" |
266eb58a DE |
6055 | [(set_attr "length" "12")]) |
6056 | ||
6057 | (define_split | |
6058 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") | |
6059 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) | |
6060 | (clobber (match_scratch:DI 2 "=&r,&r"))] | |
6061 | "TARGET_POWERPC64 && reload_completed" | |
a260abc9 | 6062 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 6063 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
19ba8161 | 6064 | (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] |
266eb58a DE |
6065 | "") |
6066 | ||
6067 | (define_expand "negdi2" | |
6068 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6069 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))] | |
6070 | "" | |
6071 | "") | |
6072 | ||
6073 | (define_insn "" | |
6074 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6075 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6076 | "TARGET_POWERPC64" | |
6077 | "neg %0,%1") | |
6078 | ||
6079 | (define_insn "" | |
9ebbca7d GK |
6080 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6081 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 6082 | (const_int 0))) |
9ebbca7d | 6083 | (clobber (match_scratch:DI 2 "=r,r"))] |
29ae5b89 | 6084 | "TARGET_POWERPC64" |
9ebbca7d GK |
6085 | "@ |
6086 | neg. %2,%1 | |
6087 | #" | |
6088 | [(set_attr "type" "compare") | |
6089 | (set_attr "length" "4,8")]) | |
6090 | ||
6091 | (define_split | |
6092 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6093 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6094 | (const_int 0))) | |
6095 | (clobber (match_scratch:DI 2 ""))] | |
6096 | "TARGET_POWERPC64 && reload_completed" | |
6097 | [(set (match_dup 2) | |
6098 | (neg:DI (match_dup 1))) | |
6099 | (set (match_dup 0) | |
6100 | (compare:CC (match_dup 2) | |
6101 | (const_int 0)))] | |
6102 | "") | |
815cdc52 | 6103 | |
29ae5b89 | 6104 | (define_insn "" |
9ebbca7d GK |
6105 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
6106 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 6107 | (const_int 0))) |
9ebbca7d | 6108 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 6109 | (neg:DI (match_dup 1)))] |
29ae5b89 | 6110 | "TARGET_POWERPC64" |
9ebbca7d GK |
6111 | "@ |
6112 | neg. %0,%1 | |
6113 | #" | |
6114 | [(set_attr "type" "compare") | |
6115 | (set_attr "length" "4,8")]) | |
6116 | ||
6117 | (define_split | |
6118 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
6119 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6120 | (const_int 0))) | |
6121 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6122 | (neg:DI (match_dup 1)))] | |
6123 | "TARGET_POWERPC64 && reload_completed" | |
6124 | [(set (match_dup 0) | |
6125 | (neg:DI (match_dup 1))) | |
6126 | (set (match_dup 2) | |
6127 | (compare:CC (match_dup 0) | |
6128 | (const_int 0)))] | |
6129 | "") | |
266eb58a DE |
6130 | |
6131 | (define_insn "ffsdi2" | |
6132 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
6133 | (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6134 | "TARGET_POWERPC64" | |
6135 | "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64" | |
6136 | [(set_attr "length" "16")]) | |
6137 | ||
6138 | (define_insn "muldi3" | |
6139 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6140 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
6141 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6142 | "TARGET_POWERPC64" | |
6143 | "mulld %0,%1,%2" | |
3cb999d8 | 6144 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6145 | |
6146 | (define_insn "smuldi3_highpart" | |
6147 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6148 | (truncate:DI | |
6149 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
6150 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6151 | (sign_extend:TI | |
6152 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6153 | (const_int 64))))] | |
6154 | "TARGET_POWERPC64" | |
6155 | "mulhd %0,%1,%2" | |
3cb999d8 | 6156 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6157 | |
6158 | (define_insn "umuldi3_highpart" | |
6159 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6160 | (truncate:DI | |
6161 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
6162 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6163 | (zero_extend:TI | |
6164 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6165 | (const_int 64))))] | |
6166 | "TARGET_POWERPC64" | |
6167 | "mulhdu %0,%1,%2" | |
3cb999d8 | 6168 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6169 | |
6170 | (define_expand "divdi3" | |
6171 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6172 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6173 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
6174 | "TARGET_POWERPC64" | |
6175 | " | |
6176 | { | |
6177 | if (GET_CODE (operands[2]) == CONST_INT | |
6178 | && exact_log2 (INTVAL (operands[2])) >= 0) | |
6179 | ; | |
6180 | else | |
6181 | operands[2] = force_reg (DImode, operands[2]); | |
6182 | }") | |
6183 | ||
6184 | (define_expand "moddi3" | |
6185 | [(use (match_operand:DI 0 "gpc_reg_operand" "")) | |
6186 | (use (match_operand:DI 1 "gpc_reg_operand" "")) | |
6187 | (use (match_operand:DI 2 "reg_or_cint_operand" ""))] | |
6188 | "TARGET_POWERPC64" | |
6189 | " | |
6190 | { | |
6191 | int i = exact_log2 (INTVAL (operands[2])); | |
6192 | rtx temp1; | |
6193 | rtx temp2; | |
6194 | ||
6195 | if (GET_CODE (operands[2]) != CONST_INT || i < 0) | |
6196 | FAIL; | |
6197 | ||
6198 | temp1 = gen_reg_rtx (DImode); | |
6199 | temp2 = gen_reg_rtx (DImode); | |
6200 | ||
6201 | emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); | |
6202 | emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); | |
6203 | emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); | |
6204 | DONE; | |
6205 | }") | |
6206 | ||
6207 | (define_insn "" | |
6208 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6209 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6210 | (match_operand:DI 2 "const_int_operand" "N")))] | |
6211 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0" | |
6212 | "sradi %0,%1,%p2\;addze %0,%0" | |
6213 | [(set_attr "length" "8")]) | |
6214 | ||
6215 | (define_insn "" | |
9ebbca7d GK |
6216 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6217 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6218 | (match_operand:DI 2 "const_int_operand" "N,N")) | |
266eb58a | 6219 | (const_int 0))) |
9ebbca7d | 6220 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6221 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0" |
9ebbca7d GK |
6222 | "@ |
6223 | sradi %3,%1,%p2\;addze. %3,%3 | |
6224 | #" | |
266eb58a | 6225 | [(set_attr "type" "compare") |
9ebbca7d GK |
6226 | (set_attr "length" "8,12")]) |
6227 | ||
6228 | (define_split | |
6229 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6230 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6231 | (match_operand:DI 2 "const_int_operand" "")) | |
6232 | (const_int 0))) | |
6233 | (clobber (match_scratch:DI 3 ""))] | |
6234 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed" | |
6235 | [(set (match_dup 3) | |
6236 | (div:DI (match_dup 1) (match_dup 2))) | |
6237 | (set (match_dup 0) | |
6238 | (compare:CC (match_dup 3) | |
6239 | (const_int 0)))] | |
6240 | "") | |
266eb58a DE |
6241 | |
6242 | (define_insn "" | |
9ebbca7d GK |
6243 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6244 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6245 | (match_operand:DI 2 "const_int_operand" "N,N")) | |
266eb58a | 6246 | (const_int 0))) |
9ebbca7d | 6247 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6248 | (div:DI (match_dup 1) (match_dup 2)))] |
6249 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0" | |
9ebbca7d GK |
6250 | "@ |
6251 | sradi %0,%1,%p2\;addze. %0,%0 | |
6252 | #" | |
266eb58a | 6253 | [(set_attr "type" "compare") |
9ebbca7d | 6254 | (set_attr "length" "8,12")]) |
266eb58a | 6255 | |
9ebbca7d GK |
6256 | (define_split |
6257 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6258 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6259 | (match_operand:DI 2 "const_int_operand" "")) | |
6260 | (const_int 0))) | |
6261 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6262 | (div:DI (match_dup 1) (match_dup 2)))] | |
6263 | "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0 && reload_completed" | |
6264 | [(set (match_dup 0) | |
6265 | (div:DI (match_dup 1) (match_dup 2))) | |
6266 | (set (match_dup 3) | |
6267 | (compare:CC (match_dup 0) | |
6268 | (const_int 0)))] | |
6269 | "") | |
6270 | ||
6271 | (define_insn "" | |
6272 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
266eb58a | 6273 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
a260abc9 | 6274 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
266eb58a DE |
6275 | "TARGET_POWERPC64" |
6276 | "divd %0,%1,%2" | |
3cb999d8 | 6277 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6278 | |
6279 | (define_insn "udivdi3" | |
6280 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6281 | (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6282 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6283 | "TARGET_POWERPC64" | |
6284 | "divdu %0,%1,%2" | |
3cb999d8 | 6285 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6286 | |
6287 | (define_insn "rotldi3" | |
6288 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6289 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6290 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
6291 | "TARGET_POWERPC64" | |
a66078ee | 6292 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 6293 | |
a260abc9 | 6294 | (define_insn "*rotldi3_internal2" |
9ebbca7d GK |
6295 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6296 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6297 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6298 | (const_int 0))) |
9ebbca7d | 6299 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6300 | "TARGET_POWERPC64" |
9ebbca7d GK |
6301 | "@ |
6302 | rld%I2cl. %3,%1,%H2,0 | |
6303 | #" | |
6304 | [(set_attr "type" "delayed_compare") | |
6305 | (set_attr "length" "4,8")]) | |
6306 | ||
6307 | (define_split | |
6308 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6309 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6310 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6311 | (const_int 0))) | |
6312 | (clobber (match_scratch:DI 3 ""))] | |
6313 | "TARGET_POWERPC64 && reload_completed" | |
6314 | [(set (match_dup 3) | |
6315 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6316 | (set (match_dup 0) | |
6317 | (compare:CC (match_dup 3) | |
6318 | (const_int 0)))] | |
6319 | "") | |
266eb58a | 6320 | |
a260abc9 | 6321 | (define_insn "*rotldi3_internal3" |
9ebbca7d GK |
6322 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6323 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6324 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6325 | (const_int 0))) |
9ebbca7d | 6326 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6327 | (rotate:DI (match_dup 1) (match_dup 2)))] |
6328 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6329 | "@ |
6330 | rld%I2cl. %0,%1,%H2,0 | |
6331 | #" | |
6332 | [(set_attr "type" "delayed_compare") | |
6333 | (set_attr "length" "4,8")]) | |
6334 | ||
6335 | (define_split | |
6336 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6337 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6338 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6339 | (const_int 0))) | |
6340 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6341 | (rotate:DI (match_dup 1) (match_dup 2)))] | |
6342 | "TARGET_POWERPC64 && reload_completed" | |
6343 | [(set (match_dup 0) | |
6344 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6345 | (set (match_dup 3) | |
6346 | (compare:CC (match_dup 0) | |
6347 | (const_int 0)))] | |
6348 | "") | |
266eb58a | 6349 | |
a260abc9 DE |
6350 | (define_insn "*rotldi3_internal4" |
6351 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6352 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6353 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
6354 | (match_operand:DI 3 "mask64_operand" "S")))] | |
6355 | "TARGET_POWERPC64" | |
6356 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
6357 | ||
6358 | (define_insn "*rotldi3_internal5" | |
9ebbca7d | 6359 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 | 6360 | (compare:CC (and:DI |
9ebbca7d GK |
6361 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6362 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
6363 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
a260abc9 | 6364 | (const_int 0))) |
9ebbca7d | 6365 | (clobber (match_scratch:DI 4 "=r,r"))] |
a260abc9 | 6366 | "TARGET_POWERPC64" |
9ebbca7d GK |
6367 | "@ |
6368 | rld%I2c%B3. %4,%1,%H2,%S3 | |
6369 | #" | |
6370 | [(set_attr "type" "delayed_compare") | |
6371 | (set_attr "length" "4,8")]) | |
6372 | ||
6373 | (define_split | |
6374 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6375 | (compare:CC (and:DI | |
6376 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6377 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6378 | (match_operand:DI 3 "mask64_operand" "")) | |
6379 | (const_int 0))) | |
6380 | (clobber (match_scratch:DI 4 ""))] | |
6381 | "TARGET_POWERPC64 && reload_completed" | |
6382 | [(set (match_dup 4) | |
6383 | (and:DI (rotate:DI (match_dup 1) | |
6384 | (match_dup 2)) | |
6385 | (match_dup 3))) | |
6386 | (set (match_dup 0) | |
6387 | (compare:CC (match_dup 4) | |
6388 | (const_int 0)))] | |
6389 | "") | |
a260abc9 DE |
6390 | |
6391 | (define_insn "*rotldi3_internal6" | |
9ebbca7d | 6392 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 | 6393 | (compare:CC (and:DI |
9ebbca7d GK |
6394 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6395 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
6396 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
a260abc9 | 6397 | (const_int 0))) |
9ebbca7d | 6398 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6399 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
6400 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6401 | "@ |
6402 | rld%I2c%B3. %0,%1,%H2,%S3 | |
6403 | #" | |
6404 | [(set_attr "type" "delayed_compare") | |
6405 | (set_attr "length" "4,8")]) | |
6406 | ||
6407 | (define_split | |
6408 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6409 | (compare:CC (and:DI | |
6410 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6411 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6412 | (match_operand:DI 3 "mask64_operand" "")) | |
6413 | (const_int 0))) | |
6414 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6415 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6416 | "TARGET_POWERPC64 && reload_completed" | |
6417 | [(set (match_dup 0) | |
6418 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
6419 | (set (match_dup 4) | |
6420 | (compare:CC (match_dup 0) | |
6421 | (const_int 0)))] | |
6422 | "") | |
a260abc9 DE |
6423 | |
6424 | (define_insn "*rotldi3_internal7" | |
6425 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6426 | (zero_extend:DI | |
6427 | (subreg:QI | |
6428 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6429 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6430 | "TARGET_POWERPC64" | |
6431 | "rld%I2cl %0,%1,%H2,56") | |
6432 | ||
6433 | (define_insn "*rotldi3_internal8" | |
9ebbca7d | 6434 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6435 | (compare:CC (zero_extend:DI |
6436 | (subreg:QI | |
9ebbca7d GK |
6437 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6438 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6439 | (const_int 0))) |
9ebbca7d | 6440 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6441 | "TARGET_POWERPC64" |
9ebbca7d GK |
6442 | "@ |
6443 | rld%I2cl. %3,%1,%H2,56 | |
6444 | #" | |
6445 | [(set_attr "type" "delayed_compare") | |
6446 | (set_attr "length" "4,8")]) | |
6447 | ||
6448 | (define_split | |
6449 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6450 | (compare:CC (zero_extend:DI | |
6451 | (subreg:QI | |
6452 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6453 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6454 | (const_int 0))) | |
6455 | (clobber (match_scratch:DI 3 ""))] | |
6456 | "TARGET_POWERPC64 && reload_completed" | |
6457 | [(set (match_dup 3) | |
6458 | (zero_extend:DI (subreg:QI | |
6459 | (rotate:DI (match_dup 1) | |
6460 | (match_dup 2)) 0))) | |
6461 | (set (match_dup 0) | |
6462 | (compare:CC (match_dup 3) | |
6463 | (const_int 0)))] | |
6464 | "") | |
a260abc9 DE |
6465 | |
6466 | (define_insn "*rotldi3_internal9" | |
9ebbca7d | 6467 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6468 | (compare:CC (zero_extend:DI |
6469 | (subreg:QI | |
9ebbca7d GK |
6470 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6471 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6472 | (const_int 0))) |
9ebbca7d | 6473 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6474 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6475 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6476 | "@ |
6477 | rld%I2cl. %0,%1,%H2,56 | |
6478 | #" | |
6479 | [(set_attr "type" "delayed_compare") | |
6480 | (set_attr "length" "4,8")]) | |
6481 | ||
6482 | (define_split | |
6483 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6484 | (compare:CC (zero_extend:DI | |
6485 | (subreg:QI | |
6486 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6487 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6488 | (const_int 0))) | |
6489 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6490 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6491 | "TARGET_POWERPC64 && reload_completed" | |
6492 | [(set (match_dup 0) | |
6493 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6494 | (set (match_dup 3) | |
6495 | (compare:CC (match_dup 0) | |
6496 | (const_int 0)))] | |
6497 | "") | |
a260abc9 DE |
6498 | |
6499 | (define_insn "*rotldi3_internal10" | |
6500 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6501 | (zero_extend:DI | |
6502 | (subreg:HI | |
6503 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6504 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6505 | "TARGET_POWERPC64" | |
6506 | "rld%I2cl %0,%1,%H2,48") | |
6507 | ||
6508 | (define_insn "*rotldi3_internal11" | |
9ebbca7d | 6509 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6510 | (compare:CC (zero_extend:DI |
6511 | (subreg:HI | |
9ebbca7d GK |
6512 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6513 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6514 | (const_int 0))) |
9ebbca7d | 6515 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6516 | "TARGET_POWERPC64" |
9ebbca7d GK |
6517 | "@ |
6518 | rld%I2cl. %3,%1,%H2,48 | |
6519 | #" | |
6520 | [(set_attr "type" "delayed_compare") | |
6521 | (set_attr "length" "4,8")]) | |
6522 | ||
6523 | (define_split | |
6524 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6525 | (compare:CC (zero_extend:DI | |
6526 | (subreg:HI | |
6527 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6528 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6529 | (const_int 0))) | |
6530 | (clobber (match_scratch:DI 3 ""))] | |
6531 | "TARGET_POWERPC64 && reload_completed" | |
6532 | [(set (match_dup 3) | |
6533 | (zero_extend:DI (subreg:HI | |
6534 | (rotate:DI (match_dup 1) | |
6535 | (match_dup 2)) 0))) | |
6536 | (set (match_dup 0) | |
6537 | (compare:CC (match_dup 3) | |
6538 | (const_int 0)))] | |
6539 | "") | |
a260abc9 DE |
6540 | |
6541 | (define_insn "*rotldi3_internal12" | |
9ebbca7d | 6542 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6543 | (compare:CC (zero_extend:DI |
6544 | (subreg:HI | |
9ebbca7d GK |
6545 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6546 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6547 | (const_int 0))) |
9ebbca7d | 6548 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6549 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6550 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6551 | "@ |
6552 | rld%I2cl. %0,%1,%H2,48 | |
6553 | #" | |
6554 | [(set_attr "type" "delayed_compare") | |
6555 | (set_attr "length" "4,8")]) | |
6556 | ||
6557 | (define_split | |
6558 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6559 | (compare:CC (zero_extend:DI | |
6560 | (subreg:HI | |
6561 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6562 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6563 | (const_int 0))) | |
6564 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6565 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6566 | "TARGET_POWERPC64 && reload_completed" | |
6567 | [(set (match_dup 0) | |
6568 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6569 | (set (match_dup 3) | |
6570 | (compare:CC (match_dup 0) | |
6571 | (const_int 0)))] | |
6572 | "") | |
a260abc9 DE |
6573 | |
6574 | (define_insn "*rotldi3_internal13" | |
6575 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6576 | (zero_extend:DI | |
6577 | (subreg:SI | |
6578 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6579 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6580 | "TARGET_POWERPC64" | |
6581 | "rld%I2cl %0,%1,%H2,32") | |
6582 | ||
6583 | (define_insn "*rotldi3_internal14" | |
9ebbca7d | 6584 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6585 | (compare:CC (zero_extend:DI |
6586 | (subreg:SI | |
9ebbca7d GK |
6587 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6588 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6589 | (const_int 0))) |
9ebbca7d | 6590 | (clobber (match_scratch:DI 3 "=r,r"))] |
a260abc9 | 6591 | "TARGET_POWERPC64" |
9ebbca7d GK |
6592 | "@ |
6593 | rld%I2cl. %3,%1,%H2,32 | |
6594 | #" | |
6595 | [(set_attr "type" "delayed_compare") | |
6596 | (set_attr "length" "4,8")]) | |
6597 | ||
6598 | (define_split | |
6599 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6600 | (compare:CC (zero_extend:DI | |
6601 | (subreg:SI | |
6602 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6603 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6604 | (const_int 0))) | |
6605 | (clobber (match_scratch:DI 3 ""))] | |
6606 | "TARGET_POWERPC64 && reload_completed" | |
6607 | [(set (match_dup 3) | |
6608 | (zero_extend:DI (subreg:SI | |
6609 | (rotate:DI (match_dup 1) | |
6610 | (match_dup 2)) 0))) | |
6611 | (set (match_dup 0) | |
6612 | (compare:CC (match_dup 3) | |
6613 | (const_int 0)))] | |
6614 | "") | |
a260abc9 DE |
6615 | |
6616 | (define_insn "*rotldi3_internal15" | |
9ebbca7d | 6617 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6618 | (compare:CC (zero_extend:DI |
6619 | (subreg:SI | |
9ebbca7d GK |
6620 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6621 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6622 | (const_int 0))) |
9ebbca7d | 6623 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
6624 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
6625 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6626 | "@ |
6627 | rld%I2cl. %0,%1,%H2,32 | |
6628 | #" | |
6629 | [(set_attr "type" "delayed_compare") | |
6630 | (set_attr "length" "4,8")]) | |
6631 | ||
6632 | (define_split | |
6633 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6634 | (compare:CC (zero_extend:DI | |
6635 | (subreg:SI | |
6636 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6637 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6638 | (const_int 0))) | |
6639 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6640 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6641 | "TARGET_POWERPC64 && reload_completed" | |
6642 | [(set (match_dup 0) | |
6643 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6644 | (set (match_dup 3) | |
6645 | (compare:CC (match_dup 0) | |
6646 | (const_int 0)))] | |
6647 | "") | |
a260abc9 | 6648 | |
266eb58a DE |
6649 | (define_expand "ashldi3" |
6650 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6651 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6652 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6653 | "TARGET_POWERPC64 || TARGET_POWER" | |
6654 | " | |
6655 | { | |
6656 | if (TARGET_POWERPC64) | |
6657 | ; | |
6658 | else if (TARGET_POWER) | |
6659 | { | |
6660 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
6661 | DONE; | |
6662 | } | |
6663 | else | |
6664 | FAIL; | |
6665 | }") | |
6666 | ||
6667 | (define_insn "" | |
6668 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6669 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6670 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6671 | "TARGET_POWERPC64" | |
a66078ee | 6672 | "sld%I2 %0,%1,%H2" |
266eb58a DE |
6673 | [(set_attr "length" "8")]) |
6674 | ||
6675 | (define_insn "" | |
9ebbca7d GK |
6676 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6677 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6678 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6679 | (const_int 0))) |
9ebbca7d | 6680 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6681 | "TARGET_POWERPC64" |
9ebbca7d GK |
6682 | "@ |
6683 | sld%I2. %3,%1,%H2 | |
6684 | #" | |
6685 | [(set_attr "type" "delayed_compare") | |
6686 | (set_attr "length" "4,8")]) | |
29ae5b89 | 6687 | |
9ebbca7d GK |
6688 | (define_split |
6689 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6690 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6691 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6692 | (const_int 0))) | |
6693 | (clobber (match_scratch:DI 3 ""))] | |
6694 | "TARGET_POWERPC64 && reload_completed" | |
6695 | [(set (match_dup 3) | |
6696 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6697 | (set (match_dup 0) | |
6698 | (compare:CC (match_dup 3) | |
6699 | (const_int 0)))] | |
6700 | "") | |
6701 | ||
266eb58a | 6702 | (define_insn "" |
9ebbca7d GK |
6703 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6704 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6705 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6706 | (const_int 0))) |
9ebbca7d | 6707 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6708 | (ashift:DI (match_dup 1) (match_dup 2)))] |
6709 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6710 | "@ |
6711 | sld%I2. %0,%1,%H2 | |
6712 | #" | |
6713 | [(set_attr "type" "delayed_compare") | |
6714 | (set_attr "length" "4,8")]) | |
6715 | ||
6716 | (define_split | |
6717 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6718 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6719 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6720 | (const_int 0))) | |
6721 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6722 | (ashift:DI (match_dup 1) (match_dup 2)))] | |
6723 | "TARGET_POWERPC64 && reload_completed" | |
6724 | [(set (match_dup 0) | |
6725 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6726 | (set (match_dup 3) | |
6727 | (compare:CC (match_dup 0) | |
6728 | (const_int 0)))] | |
6729 | "") | |
266eb58a | 6730 | |
3cb999d8 DE |
6731 | (define_insn "" |
6732 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6733 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6734 | (match_operand:SI 2 "const_int_operand" "i")) | |
6735 | (match_operand:DI 3 "mask64_operand" "S")))] | |
6736 | "((GET_CODE (operands[3]) == CONST_INT | |
6737 | ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1" | |
6738 | "rldic %0,%1,%H2,%S3") | |
6739 | ||
6740 | (define_insn "" | |
9ebbca7d | 6741 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6742 | (compare:CC |
9ebbca7d GK |
6743 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6744 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
6745 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
3cb999d8 | 6746 | (const_int 0))) |
9ebbca7d | 6747 | (clobber (match_scratch:DI 4 "=r,r"))] |
3cb999d8 DE |
6748 | "((GET_CODE (operands[3]) == CONST_INT |
6749 | ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1" | |
9ebbca7d GK |
6750 | "@ |
6751 | rldic. %0,%1,%H2,%S3 | |
6752 | #" | |
6753 | [(set_attr "type" "delayed_compare") | |
6754 | (set_attr "length" "4,8")]) | |
6755 | ||
6756 | (define_split | |
6757 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6758 | (compare:CC | |
6759 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6760 | (match_operand:SI 2 "const_int_operand" "")) | |
6761 | (match_operand:DI 3 "mask64_operand" "")) | |
6762 | (const_int 0))) | |
6763 | (clobber (match_scratch:DI 4 ""))] | |
6764 | "((GET_CODE (operands[3]) == CONST_INT | |
6765 | ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1 | |
6766 | && reload_completed" | |
6767 | [(set (match_dup 4) | |
6768 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6769 | (match_dup 3))) | |
6770 | (set (match_dup 0) | |
6771 | (compare:CC (match_dup 4) | |
6772 | (const_int 0)))] | |
6773 | "") | |
3cb999d8 DE |
6774 | |
6775 | (define_insn "" | |
9ebbca7d | 6776 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6777 | (compare:CC |
9ebbca7d GK |
6778 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6779 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
6780 | (match_operand:DI 3 "mask64_operand" "S,S")) | |
3cb999d8 | 6781 | (const_int 0))) |
9ebbca7d | 6782 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3cb999d8 DE |
6783 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
6784 | "((GET_CODE (operands[3]) == CONST_INT | |
6785 | ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1" | |
9ebbca7d GK |
6786 | "@ |
6787 | rldic. %0,%1,%H2,%S3 | |
6788 | #" | |
6789 | [(set_attr "type" "delayed_compare") | |
6790 | (set_attr "length" "4,8")]) | |
6791 | ||
6792 | (define_split | |
6793 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6794 | (compare:CC | |
6795 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6796 | (match_operand:SI 2 "const_int_operand" "")) | |
6797 | (match_operand:DI 3 "mask64_operand" "")) | |
6798 | (const_int 0))) | |
6799 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6800 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6801 | "((GET_CODE (operands[3]) == CONST_INT | |
6802 | ? INTVAL (operands[3]) : CONST_DOUBLE_LOW (operands[3])) & 1) == 1 | |
6803 | && reload_completed" | |
6804 | [(set (match_dup 0) | |
6805 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
6806 | (set (match_dup 4) | |
6807 | (compare:CC (match_dup 0) | |
6808 | (const_int 0)))] | |
6809 | "") | |
6810 | ||
6811 | (define_expand "lshrdi3" | |
266eb58a DE |
6812 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
6813 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6814 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6815 | "TARGET_POWERPC64 || TARGET_POWER" | |
6816 | " | |
6817 | { | |
6818 | if (TARGET_POWERPC64) | |
6819 | ; | |
6820 | else if (TARGET_POWER) | |
6821 | { | |
6822 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
6823 | DONE; | |
6824 | } | |
6825 | else | |
6826 | FAIL; | |
6827 | }") | |
6828 | ||
6829 | (define_insn "" | |
6830 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6831 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6832 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6833 | "TARGET_POWERPC64" | |
a66078ee | 6834 | "srd%I2 %0,%1,%H2") |
266eb58a DE |
6835 | |
6836 | (define_insn "" | |
9ebbca7d GK |
6837 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6838 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6839 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
29ae5b89 | 6840 | (const_int 0))) |
9ebbca7d | 6841 | (clobber (match_scratch:DI 3 "=r,r"))] |
29ae5b89 | 6842 | "TARGET_POWERPC64" |
9ebbca7d GK |
6843 | "@ |
6844 | srd%I2. %3,%1,%H2 | |
6845 | #" | |
6846 | [(set_attr "type" "delayed_compare") | |
6847 | (set_attr "length" "4,8")]) | |
6848 | ||
6849 | (define_split | |
6850 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6851 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6852 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6853 | (const_int 0))) | |
6854 | (clobber (match_scratch:DI 3 ""))] | |
6855 | "TARGET_POWERPC64 && reload_completed" | |
6856 | [(set (match_dup 3) | |
6857 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6858 | (set (match_dup 0) | |
6859 | (compare:CC (match_dup 3) | |
6860 | (const_int 0)))] | |
6861 | "") | |
266eb58a | 6862 | |
29ae5b89 | 6863 | (define_insn "" |
9ebbca7d GK |
6864 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6865 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6866 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6867 | (const_int 0))) |
9ebbca7d | 6868 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 JL |
6869 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] |
6870 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6871 | "@ |
6872 | srd%I2. %0,%1,%H2 | |
6873 | #" | |
6874 | [(set_attr "type" "delayed_compare") | |
6875 | (set_attr "length" "4,8")]) | |
6876 | ||
6877 | (define_split | |
6878 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6879 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6880 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6881 | (const_int 0))) | |
6882 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6883 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
6884 | "TARGET_POWERPC64 && reload_completed" | |
6885 | [(set (match_dup 0) | |
6886 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6887 | (set (match_dup 3) | |
6888 | (compare:CC (match_dup 0) | |
6889 | (const_int 0)))] | |
6890 | "") | |
266eb58a DE |
6891 | |
6892 | (define_expand "ashrdi3" | |
6893 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6894 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6895 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6896 | "TARGET_POWERPC64 || TARGET_POWER" | |
6897 | " | |
6898 | { | |
6899 | if (TARGET_POWERPC64) | |
6900 | ; | |
6901 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
6902 | { | |
6903 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
6904 | DONE; | |
6905 | } | |
6906 | else | |
6907 | FAIL; | |
6908 | }") | |
6909 | ||
6910 | (define_insn "" | |
6911 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6912 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6913 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6914 | "TARGET_POWERPC64" | |
375490e0 | 6915 | "srad%I2 %0,%1,%H2") |
266eb58a DE |
6916 | |
6917 | (define_insn "" | |
9ebbca7d GK |
6918 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6919 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6920 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6921 | (const_int 0))) |
9ebbca7d | 6922 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 6923 | "TARGET_POWERPC64" |
9ebbca7d GK |
6924 | "@ |
6925 | srad%I2. %3,%1,%H2 | |
6926 | #" | |
6927 | [(set_attr "type" "delayed_compare") | |
6928 | (set_attr "length" "4,8")]) | |
6929 | ||
6930 | (define_split | |
6931 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6932 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6933 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6934 | (const_int 0))) | |
6935 | (clobber (match_scratch:DI 3 ""))] | |
6936 | "TARGET_POWERPC64 && reload_completed" | |
6937 | [(set (match_dup 3) | |
6938 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
6939 | (set (match_dup 0) | |
6940 | (compare:CC (match_dup 3) | |
6941 | (const_int 0)))] | |
6942 | "") | |
266eb58a DE |
6943 | |
6944 | (define_insn "" | |
9ebbca7d GK |
6945 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6946 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6947 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6948 | (const_int 0))) |
9ebbca7d | 6949 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a DE |
6950 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6951 | "TARGET_POWERPC64" | |
9ebbca7d GK |
6952 | "@ |
6953 | srad%I2. %0,%1,%H2 | |
6954 | #" | |
6955 | [(set_attr "type" "delayed_compare") | |
6956 | (set_attr "length" "4,8")]) | |
6957 | ||
6958 | (define_split | |
6959 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6960 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6961 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6962 | (const_int 0))) | |
6963 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6964 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
6965 | "TARGET_POWERPC64 && reload_completed" | |
6966 | [(set (match_dup 0) | |
6967 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
6968 | (set (match_dup 3) | |
6969 | (compare:CC (match_dup 0) | |
6970 | (const_int 0)))] | |
6971 | "") | |
815cdc52 | 6972 | |
29ae5b89 JL |
6973 | (define_insn "anddi3" |
6974 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") | |
6975 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
6976 | (match_operand:DI 2 "and64_operand" "?r,S,K,J"))) | |
6977 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] | |
6ffc8580 | 6978 | "TARGET_POWERPC64" |
266eb58a DE |
6979 | "@ |
6980 | and %0,%1,%2 | |
29ae5b89 JL |
6981 | rldic%B2 %0,%1,0,%S2 |
6982 | andi. %0,%1,%b2 | |
6983 | andis. %0,%1,%u2") | |
266eb58a | 6984 | |
a260abc9 | 6985 | (define_insn "*anddi3_internal2" |
9ebbca7d GK |
6986 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
6987 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,") | |
6988 | (match_operand:DI 2 "and64_operand" "r,K,J,S,r,K,J,S")) | |
266eb58a | 6989 | (const_int 0))) |
9ebbca7d GK |
6990 | (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r")) |
6991 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
6ffc8580 | 6992 | "TARGET_POWERPC64" |
266eb58a DE |
6993 | "@ |
6994 | and. %3,%1,%2 | |
6ffc8580 MM |
6995 | andi. %3,%1,%b2 |
6996 | andis. %3,%1,%u2 | |
9ebbca7d GK |
6997 | rldic%B2. %3,%1,0,%S2 |
6998 | # | |
6999 | # | |
7000 | # | |
7001 | #" | |
7002 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,delayed_compare") | |
7003 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
7004 | ||
7005 | (define_split | |
7006 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7007 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7008 | (match_operand:DI 2 "and64_operand" "")) | |
7009 | (const_int 0))) | |
7010 | (clobber (match_scratch:DI 3 "")) | |
7011 | (clobber (match_scratch:CC 4 ""))] | |
7012 | "TARGET_POWERPC64 && reload_completed" | |
7013 | [(parallel [(set (match_dup 3) | |
7014 | (and:DI (match_dup 1) | |
7015 | (match_dup 2))) | |
7016 | (clobber (match_dup 4))]) | |
7017 | (set (match_dup 0) | |
7018 | (compare:CC (match_dup 3) | |
7019 | (const_int 0)))] | |
7020 | "") | |
266eb58a | 7021 | |
a260abc9 | 7022 | (define_insn "*anddi3_internal3" |
9ebbca7d GK |
7023 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
7024 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
7025 | (match_operand:DI 2 "and64_operand" "r,K,J,S,r,K,J,S")) | |
266eb58a | 7026 | (const_int 0))) |
9ebbca7d GK |
7027 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") |
7028 | (and:DI (match_dup 1) (match_dup 2))) | |
7029 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
6ffc8580 | 7030 | "TARGET_POWERPC64" |
266eb58a DE |
7031 | "@ |
7032 | and. %0,%1,%2 | |
6ffc8580 MM |
7033 | andi. %0,%1,%b2 |
7034 | andis. %0,%1,%u2 | |
9ebbca7d GK |
7035 | rldic%B2. %0,%1,0,%S2 |
7036 | # | |
7037 | # | |
7038 | # | |
7039 | #" | |
7040 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,delayed_compare") | |
7041 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
7042 | ||
7043 | (define_split | |
7044 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7045 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7046 | (match_operand:DI 2 "and64_operand" "")) | |
7047 | (const_int 0))) | |
7048 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7049 | (and:DI (match_dup 1) (match_dup 2))) | |
7050 | (clobber (match_scratch:CC 4 ""))] | |
7051 | "TARGET_POWERPC64 && reload_completed" | |
7052 | [(parallel [(set (match_dup 0) | |
7053 | (and:DI (match_dup 1) (match_dup 2))) | |
7054 | (clobber (match_dup 4))]) | |
7055 | (set (match_dup 3) | |
7056 | (compare:CC (match_dup 0) | |
7057 | (const_int 0)))] | |
7058 | "") | |
266eb58a | 7059 | |
a260abc9 | 7060 | (define_expand "iordi3" |
266eb58a | 7061 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 | 7062 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
dfbdccdb | 7063 | (match_operand:DI 2 "reg_or_cint_operand" "")))] |
266eb58a | 7064 | "TARGET_POWERPC64" |
266eb58a DE |
7065 | " |
7066 | { | |
dfbdccdb | 7067 | if (non_logical_cint_operand (operands[2], DImode)) |
266eb58a | 7068 | { |
dfbdccdb | 7069 | HOST_WIDE_INT value; |
677a9668 | 7070 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 | 7071 | ? operands[0] : gen_reg_rtx (DImode)); |
266eb58a | 7072 | |
dfbdccdb GK |
7073 | if (GET_CODE (operands[2]) == CONST_INT) |
7074 | { | |
7075 | value = INTVAL (operands[2]); | |
7076 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7077 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7078 | } | |
7079 | else if (GET_CODE (operands[2]) == CONST_DOUBLE) | |
7080 | { | |
7081 | value = CONST_DOUBLE_LOW (operands[2]); | |
7082 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7083 | immed_double_const (value | |
7084 | & (~ (HOST_WIDE_INT) 0xffff), | |
7085 | 0, DImode))); | |
7086 | } | |
9ebbca7d GK |
7087 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7088 | DONE; | |
7089 | } | |
266eb58a DE |
7090 | }") |
7091 | ||
a260abc9 DE |
7092 | (define_expand "xordi3" |
7093 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7094 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
dfbdccdb | 7095 | (match_operand:DI 2 "reg_or_cint_operand" "")))] |
a260abc9 DE |
7096 | "TARGET_POWERPC64" |
7097 | " | |
7098 | { | |
dfbdccdb | 7099 | if (non_logical_cint_operand (operands[2], DImode)) |
a260abc9 | 7100 | { |
dfbdccdb | 7101 | HOST_WIDE_INT value; |
677a9668 | 7102 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
7103 | ? operands[0] : gen_reg_rtx (DImode)); |
7104 | ||
dfbdccdb GK |
7105 | if (GET_CODE (operands[2]) == CONST_INT) |
7106 | { | |
7107 | value = INTVAL (operands[2]); | |
7108 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7109 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7110 | } | |
7111 | else if (GET_CODE (operands[2]) == CONST_DOUBLE) | |
7112 | { | |
7113 | value = CONST_DOUBLE_LOW (operands[2]); | |
7114 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7115 | immed_double_const (value | |
7116 | & (~ (HOST_WIDE_INT) 0xffff), | |
7117 | 0, DImode))); | |
7118 | } | |
9ebbca7d GK |
7119 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7120 | DONE; | |
7121 | } | |
a260abc9 DE |
7122 | }") |
7123 | ||
dfbdccdb | 7124 | (define_insn "*booldi3_internal1" |
266eb58a | 7125 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
dfbdccdb GK |
7126 | (match_operator:DI 3 "boolean_operator" |
7127 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") | |
7128 | (match_operand:DI 2 "logical_operand" "r,K,JF")]))] | |
266eb58a | 7129 | "TARGET_POWERPC64" |
1fd4e8c1 | 7130 | "@ |
dfbdccdb GK |
7131 | %q3 %0,%1,%2 |
7132 | %q3i %0,%1,%b2 | |
7133 | %q3is %0,%1,%u2") | |
1fd4e8c1 | 7134 | |
dfbdccdb | 7135 | (define_insn "*booldi3_internal2" |
9ebbca7d | 7136 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7137 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7138 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7139 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7140 | (const_int 0))) | |
9ebbca7d | 7141 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7142 | "TARGET_POWERPC64" |
9ebbca7d | 7143 | "@ |
dfbdccdb | 7144 | %q4. %3,%1,%2 |
9ebbca7d GK |
7145 | #" |
7146 | [(set_attr "type" "compare") | |
7147 | (set_attr "length" "4,8")]) | |
7148 | ||
7149 | (define_split | |
7150 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
7151 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7152 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7153 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7154 | (const_int 0))) | |
9ebbca7d GK |
7155 | (clobber (match_scratch:DI 3 ""))] |
7156 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7157 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7158 | (set (match_dup 0) |
7159 | (compare:CC (match_dup 3) | |
7160 | (const_int 0)))] | |
7161 | "") | |
1fd4e8c1 | 7162 | |
dfbdccdb | 7163 | (define_insn "*booldi3_internal3" |
9ebbca7d | 7164 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7165 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7166 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7167 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7168 | (const_int 0))) | |
9ebbca7d | 7169 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7170 | (match_dup 4))] |
266eb58a | 7171 | "TARGET_POWERPC64" |
9ebbca7d | 7172 | "@ |
dfbdccdb | 7173 | %q4. %0,%1,%2 |
9ebbca7d GK |
7174 | #" |
7175 | [(set_attr "type" "compare") | |
7176 | (set_attr "length" "4,8")]) | |
7177 | ||
7178 | (define_split | |
dfbdccdb GK |
7179 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
7180 | (compare:CC (match_operator:DI 4 "boolean_operator" | |
7181 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7182 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7183 | (const_int 0))) | |
7184 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
7185 | (match_dup 4))] | |
9ebbca7d | 7186 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7187 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7188 | (set (match_dup 3) |
7189 | (compare:CC (match_dup 0) | |
7190 | (const_int 0)))] | |
7191 | "") | |
1fd4e8c1 | 7192 | |
dfbdccdb GK |
7193 | ;; Split an logical operation that we can't do in one insn into two insns, |
7194 | ;; each of which does one 16-bit part. This is used by combine. | |
266eb58a DE |
7195 | |
7196 | (define_split | |
7197 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
dfbdccdb GK |
7198 | (match_operator:DI 3 "boolean_operator" |
7199 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
7200 | (match_operand:DI 2 "non_logical_cint_operand" "")]))] | |
266eb58a | 7201 | "TARGET_POWERPC64" |
dfbdccdb GK |
7202 | [(set (match_dup 0) (match_dup 4)) |
7203 | (set (match_dup 0) (match_dup 5))] | |
266eb58a DE |
7204 | " |
7205 | { | |
dfbdccdb GK |
7206 | rtx i3,i4; |
7207 | ||
9ebbca7d GK |
7208 | if (GET_CODE (operands[2]) == CONST_DOUBLE) |
7209 | { | |
7210 | HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); | |
dfbdccdb | 7211 | i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), |
9ebbca7d | 7212 | 0, DImode); |
dfbdccdb | 7213 | i4 = GEN_INT (value & 0xffff); |
9ebbca7d GK |
7214 | } |
7215 | else | |
7216 | { | |
dfbdccdb | 7217 | i3 = GEN_INT (INTVAL (operands[2]) |
9ebbca7d | 7218 | & (~ (HOST_WIDE_INT) 0xffff)); |
dfbdccdb | 7219 | i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); |
9ebbca7d | 7220 | } |
dfbdccdb GK |
7221 | operands[4] = gen_rtx (GET_CODE (operands[3]), DImode, |
7222 | operands[1], i3); | |
7223 | operands[5] = gen_rtx (GET_CODE (operands[3]), DImode, | |
7224 | operands[0], i4); | |
1fd4e8c1 RK |
7225 | }") |
7226 | ||
dfbdccdb | 7227 | (define_insn "*boolcdi3_internal1" |
9ebbca7d | 7228 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7229 | (match_operator:DI 3 "boolean_operator" |
7230 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
7231 | (match_operand:DI 2 "logical_operand" "r")]))] | |
a473029f | 7232 | "TARGET_POWERPC64" |
dfbdccdb | 7233 | "%q3 %0,%1,%2") |
a473029f | 7234 | |
dfbdccdb | 7235 | (define_insn "*boolcdi3_internal2" |
9ebbca7d | 7236 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7237 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7238 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7239 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7240 | (const_int 0))) | |
9ebbca7d | 7241 | (clobber (match_scratch:DI 3 "=r,r"))] |
a473029f | 7242 | "TARGET_POWERPC64" |
9ebbca7d | 7243 | "@ |
dfbdccdb | 7244 | %q4. %3,%1,%2 |
9ebbca7d GK |
7245 | #" |
7246 | [(set_attr "type" "compare") | |
7247 | (set_attr "length" "4,8")]) | |
7248 | ||
7249 | (define_split | |
7250 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
7251 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7252 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
7253 | (match_operand:DI 2 "gpc_reg_operand" "r")]) | |
7254 | (const_int 0))) | |
9ebbca7d GK |
7255 | (clobber (match_scratch:DI 3 ""))] |
7256 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7257 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7258 | (set (match_dup 0) |
7259 | (compare:CC (match_dup 3) | |
7260 | (const_int 0)))] | |
7261 | "") | |
a473029f | 7262 | |
dfbdccdb | 7263 | (define_insn "*boolcdi3_internal3" |
9ebbca7d | 7264 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7265 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7266 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7267 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7268 | (const_int 0))) | |
9ebbca7d | 7269 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7270 | (match_dup 4))] |
a473029f | 7271 | "TARGET_POWERPC64" |
9ebbca7d | 7272 | "@ |
dfbdccdb | 7273 | %q4. %0,%1,%2 |
9ebbca7d GK |
7274 | #" |
7275 | [(set_attr "type" "compare") | |
7276 | (set_attr "length" "4,8")]) | |
7277 | ||
7278 | (define_split | |
9ebbca7d | 7279 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7280 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7281 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7282 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7283 | (const_int 0))) | |
9ebbca7d | 7284 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7285 | (match_dup 4))] |
9ebbca7d | 7286 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7287 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7288 | (set (match_dup 3) |
7289 | (compare:CC (match_dup 0) | |
7290 | (const_int 0)))] | |
7291 | "") | |
266eb58a | 7292 | |
dfbdccdb | 7293 | (define_insn "*boolccdi3_internal1" |
a473029f | 7294 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7295 | (match_operator:DI 3 "boolean_operator" |
7296 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
7297 | (not:DI (match_operand:DI 2 "logical_operand" "r"))]))] | |
a473029f | 7298 | "TARGET_POWERPC64" |
dfbdccdb | 7299 | "%q3 %0,%1,%2") |
a473029f | 7300 | |
dfbdccdb | 7301 | (define_insn "*boolccdi3_internal2" |
9ebbca7d | 7302 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7303 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7304 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7305 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7306 | (const_int 0))) | |
9ebbca7d | 7307 | (clobber (match_scratch:DI 3 "=r,r"))] |
266eb58a | 7308 | "TARGET_POWERPC64" |
9ebbca7d | 7309 | "@ |
dfbdccdb | 7310 | %q4. %3,%1,%2 |
9ebbca7d GK |
7311 | #" |
7312 | [(set_attr "type" "compare") | |
7313 | (set_attr "length" "4,8")]) | |
7314 | ||
7315 | (define_split | |
7316 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb GK |
7317 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7318 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
7319 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]) | |
7320 | (const_int 0))) | |
9ebbca7d GK |
7321 | (clobber (match_scratch:DI 3 ""))] |
7322 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7323 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7324 | (set (match_dup 0) |
7325 | (compare:CC (match_dup 3) | |
7326 | (const_int 0)))] | |
7327 | "") | |
266eb58a | 7328 | |
dfbdccdb | 7329 | (define_insn "*boolccdi3_internal3" |
9ebbca7d | 7330 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7331 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7332 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7333 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7334 | (const_int 0))) | |
9ebbca7d | 7335 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7336 | (match_dup 4))] |
29ae5b89 | 7337 | "TARGET_POWERPC64" |
9ebbca7d | 7338 | "@ |
dfbdccdb | 7339 | %q4. %0,%1,%2 |
9ebbca7d GK |
7340 | #" |
7341 | [(set_attr "type" "compare") | |
7342 | (set_attr "length" "4,8")]) | |
7343 | ||
7344 | (define_split | |
9ebbca7d | 7345 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7346 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7347 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7348 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7349 | (const_int 0))) | |
9ebbca7d | 7350 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7351 | (match_dup 4))] |
9ebbca7d | 7352 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7353 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7354 | (set (match_dup 3) |
7355 | (compare:CC (match_dup 0) | |
7356 | (const_int 0)))] | |
7357 | "") | |
dfbdccdb | 7358 | \f |
1fd4e8c1 | 7359 | ;; Now define ways of moving data around. |
4697a36c MM |
7360 | |
7361 | ;; Elf specific ways of loading addresses for non-PIC code. | |
9ebbca7d GK |
7362 | ;; The output of this could be r0, but we make a very strong |
7363 | ;; preference for a base register because it will usually | |
7364 | ;; be needed there. | |
4697a36c | 7365 | (define_insn "elf_high" |
9ebbca7d | 7366 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") |
4697a36c | 7367 | (high:SI (match_operand 1 "" "")))] |
0ad91047 | 7368 | "TARGET_ELF && ! TARGET_64BIT" |
a6c2a102 | 7369 | "{liu|lis} %0,%1@ha") |
4697a36c MM |
7370 | |
7371 | (define_insn "elf_low" | |
9ebbca7d GK |
7372 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
7373 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
4697a36c | 7374 | (match_operand 2 "" "")))] |
0ad91047 | 7375 | "TARGET_ELF && ! TARGET_64BIT" |
9ebbca7d GK |
7376 | "@ |
7377 | {cal|la} %0,%2@l(%1) | |
81eace42 | 7378 | {ai|addic} %0,%1,%K2") |
4697a36c | 7379 | |
766a866c MM |
7380 | ;; Set up a register with a value from the GOT table |
7381 | ||
7382 | (define_expand "movsi_got" | |
52d3af72 | 7383 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d GK |
7384 | (unspec:SI [(match_operand:SI 1 "got_operand" "") |
7385 | (match_dup 2)] 8))] | |
58307bcd | 7386 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1" |
766a866c MM |
7387 | " |
7388 | { | |
38c1f2d7 MM |
7389 | if (GET_CODE (operands[1]) == CONST) |
7390 | { | |
7391 | rtx offset = const0_rtx; | |
7392 | HOST_WIDE_INT value; | |
7393 | ||
7394 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
7395 | value = INTVAL (offset); | |
7396 | if (value != 0) | |
7397 | { | |
677a9668 | 7398 | rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); |
38c1f2d7 MM |
7399 | emit_insn (gen_movsi_got (tmp, operands[1])); |
7400 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
7401 | DONE; | |
7402 | } | |
7403 | } | |
7404 | ||
c4c40373 | 7405 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
7406 | }") |
7407 | ||
84f414bc | 7408 | (define_insn "*movsi_got_internal" |
52d3af72 | 7409 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d GK |
7410 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
7411 | (match_operand:SI 2 "gpc_reg_operand" "b")] 8))] | |
c81bebd7 | 7412 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1" |
766a866c MM |
7413 | "{l|lwz} %0,%a1@got(%2)" |
7414 | [(set_attr "type" "load")]) | |
7415 | ||
b22b9b3e JL |
7416 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg |
7417 | ;; didn't get allocated to a hard register. | |
7418 | (define_split | |
52d3af72 | 7419 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d GK |
7420 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
7421 | (match_operand:SI 2 "memory_operand" "m")] 8))] | |
b22b9b3e JL |
7422 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
7423 | && flag_pic == 1 | |
7424 | && (reload_in_progress || reload_completed)" | |
7425 | [(set (match_dup 0) (match_dup 2)) | |
9ebbca7d | 7426 | (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 8))] |
b22b9b3e JL |
7427 | "") |
7428 | ||
1fd4e8c1 RK |
7429 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
7430 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
7431 | ;; and this is even supposed to be faster, but it is simpler not to get | |
7432 | ;; integers in the TOC. | |
7433 | (define_expand "movsi" | |
7434 | [(set (match_operand:SI 0 "general_operand" "") | |
7435 | (match_operand:SI 1 "any_operand" ""))] | |
7436 | "" | |
7437 | " | |
7438 | { | |
9ebbca7d | 7439 | if (! no_new_pseudos && GET_CODE (operands[0]) != REG) |
1fd4e8c1 RK |
7440 | operands[1] = force_reg (SImode, operands[1]); |
7441 | ||
ef0e171b RK |
7442 | /* Convert a move of a CONST_DOUBLE into a CONST_INT */ |
7443 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
7444 | operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
7445 | ||
34792e82 | 7446 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 7447 | if (GET_CODE (operands[1]) == CONSTANT_P_RTX) |
34792e82 JL |
7448 | { |
7449 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
7450 | DONE; | |
7451 | } | |
7452 | ||
88228c4b MM |
7453 | /* Use default pattern for address of ELF small data */ |
7454 | if (TARGET_ELF | |
c81bebd7 | 7455 | && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
88228c4b | 7456 | && (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST) |
e98bb982 | 7457 | && small_data_operand (operands[1], SImode)) |
88228c4b | 7458 | { |
39403d82 | 7459 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); |
88228c4b MM |
7460 | DONE; |
7461 | } | |
7462 | ||
c81bebd7 | 7463 | if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
84f414bc | 7464 | && flag_pic == 1 && got_operand (operands[1], SImode)) |
766a866c MM |
7465 | { |
7466 | emit_insn (gen_movsi_got (operands[0], operands[1])); | |
7467 | DONE; | |
7468 | } | |
7469 | ||
677a9668 DE |
7470 | if (TARGET_ELF && TARGET_NO_TOC && ! TARGET_64BIT |
7471 | && ! flag_pic | |
4697a36c MM |
7472 | && CONSTANT_P (operands[1]) |
7473 | && GET_CODE (operands[1]) != HIGH | |
34792e82 | 7474 | && GET_CODE (operands[1]) != CONST_INT) |
4697a36c | 7475 | { |
677a9668 | 7476 | rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (SImode)); |
4697a36c | 7477 | |
9ebbca7d | 7478 | /* If this is a function address on -mcall-aixdesc, |
b6c9286a | 7479 | convert it to the address of the descriptor. */ |
9ebbca7d | 7480 | if (DEFAULT_ABI == ABI_AIX |
b6c9286a MM |
7481 | && GET_CODE (operands[1]) == SYMBOL_REF |
7482 | && XSTR (operands[1], 0)[0] == '.') | |
7483 | { | |
9ebbca7d | 7484 | char *name = XSTR (operands[1], 0); |
b6c9286a MM |
7485 | rtx new_ref; |
7486 | while (*name == '.') | |
7487 | name++; | |
39403d82 | 7488 | new_ref = gen_rtx_SYMBOL_REF (Pmode, name); |
c5c76735 JL |
7489 | CONSTANT_POOL_ADDRESS_P (new_ref) |
7490 | = CONSTANT_POOL_ADDRESS_P (operands[1]); | |
b6c9286a MM |
7491 | SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]); |
7492 | SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]); | |
7493 | operands[1] = new_ref; | |
7494 | } | |
7495 | ||
4697a36c MM |
7496 | emit_insn (gen_elf_high (target, operands[1])); |
7497 | emit_insn (gen_elf_low (operands[0], target, operands[1])); | |
7498 | DONE; | |
7499 | } | |
7500 | ||
9ebbca7d | 7501 | if (CONSTANT_P (operands[1]) |
4697a36c MM |
7502 | && GET_CODE (operands[1]) != CONST_INT |
7503 | && GET_CODE (operands[1]) != HIGH | |
9ebbca7d GK |
7504 | && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]) |
7505 | && ! TOC_RELATIVE_EXPR_P (operands[1])) | |
b45863ec | 7506 | { |
d302f4f2 MM |
7507 | /* Emit a USE operation so that the constant isn't deleted if |
7508 | expensive optimizations are turned on because nobody | |
e0350319 MM |
7509 | references it. This should only be done for operands that |
7510 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
7511 | This should not be done for operands that contain LABEL_REFs. | |
7512 | For now, we just handle the obvious case. */ | |
7513 | if (GET_CODE (operands[1]) != LABEL_REF) | |
39403d82 | 7514 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); |
d302f4f2 | 7515 | |
30a4619d RK |
7516 | /* If we are to limit the number of things we put in the TOC and |
7517 | this is a symbol plus a constant we can add in one insn, | |
abc95ed3 | 7518 | just put the symbol in the TOC and add the constant. Don't do |
30a4619d RK |
7519 | this if reload is in progress. */ |
7520 | if (GET_CODE (operands[1]) == CONST | |
7521 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
7522 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
7523 | && add_operand (XEXP (XEXP (operands[1], 0), 1), SImode) | |
7524 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF | |
7525 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
7526 | && ! side_effects_p (operands[0])) | |
7527 | { | |
7528 | rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[1], 0), 0)); | |
7529 | rtx other = XEXP (XEXP (operands[1], 0), 1); | |
7530 | ||
7531 | emit_insn (gen_addsi3 (operands[0], force_reg (SImode, sym), other)); | |
7532 | DONE; | |
7533 | } | |
7534 | ||
b45863ec | 7535 | operands[1] = force_const_mem (SImode, operands[1]); |
9ebbca7d GK |
7536 | |
7537 | if (TARGET_TOC | |
7538 | && CONSTANT_POOL_EXPR_P (XEXP (operands[1], 0)) | |
7539 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant ( | |
7540 | XEXP (operands[1], 0)))) | |
7541 | { | |
f176e826 GK |
7542 | operands[1] = gen_rtx_MEM (SImode, |
7543 | create_TOC_reference (XEXP (operands[1], 0))); | |
9ebbca7d GK |
7544 | MEM_ALIAS_SET (operands[1]) = get_TOC_alias_set (); |
7545 | RTX_UNCHANGING_P (operands[1]) = 1; | |
7546 | } | |
7547 | ||
b45863ec RK |
7548 | if (! memory_address_p (SImode, XEXP (operands[1], 0)) |
7549 | && ! reload_in_progress) | |
7550 | operands[1] = change_address (operands[1], SImode, | |
7551 | XEXP (operands[1], 0)); | |
7552 | } | |
1fd4e8c1 RK |
7553 | }") |
7554 | ||
acad7ed3 | 7555 | (define_insn "*movsi_internal1" |
a260abc9 | 7556 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h") |
9615f239 | 7557 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,0"))] |
19d5775a RK |
7558 | "gpc_reg_operand (operands[0], SImode) |
7559 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 7560 | "@ |
deb9225a | 7561 | mr %0,%1 |
b9442c72 | 7562 | {cal|la} %0,%a1 |
ca7f5001 RK |
7563 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7564 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 7565 | {lil|li} %0,%1 |
802a0058 | 7566 | {liu|lis} %0,%v1 |
beaec479 | 7567 | # |
57fa6739 | 7568 | {cal|la} %0,%1(%*) |
1fd4e8c1 | 7569 | mf%1 %0 |
5c23c401 | 7570 | mt%0 %1 |
e76e75bb RK |
7571 | mt%0 %1 |
7572 | cror 0,0,0" | |
a260abc9 DE |
7573 | [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*") |
7574 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4")]) | |
1fd4e8c1 | 7575 | |
77fa0940 RK |
7576 | ;; Split a load of a large constant into the appropriate two-insn |
7577 | ;; sequence. | |
7578 | ||
7579 | (define_split | |
7580 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
7581 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 7582 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
7583 | && (INTVAL (operands[1]) & 0xffff) != 0" |
7584 | [(set (match_dup 0) | |
7585 | (match_dup 2)) | |
7586 | (set (match_dup 0) | |
7587 | (ior:SI (match_dup 0) | |
7588 | (match_dup 3)))] | |
7589 | " | |
7590 | { | |
5f59ecb7 | 7591 | operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff)); |
89e9f3a8 | 7592 | operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); |
77fa0940 RK |
7593 | }") |
7594 | ||
acad7ed3 | 7595 | (define_insn "*movsi_internal2" |
9ebbca7d GK |
7596 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
7597 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 7598 | (const_int 0))) |
9ebbca7d | 7599 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] |
0ad91047 | 7600 | "! TARGET_POWERPC64" |
9ebbca7d GK |
7601 | "@ |
7602 | mr. %0,%1 | |
7603 | #" | |
7604 | [(set_attr "type" "compare") | |
7605 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 7606 | \f |
9ebbca7d GK |
7607 | (define_split |
7608 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
7609 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") | |
7610 | (const_int 0))) | |
7611 | (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] | |
7612 | "! TARGET_POWERPC64 && reload_completed" | |
7613 | [(set (match_dup 0) (match_dup 1)) | |
7614 | (set (match_dup 2) | |
7615 | (compare:CC (match_dup 0) | |
7616 | (const_int 0)))] | |
7617 | "") | |
7618 | ||
1fd4e8c1 RK |
7619 | (define_expand "movhi" |
7620 | [(set (match_operand:HI 0 "general_operand" "") | |
7621 | (match_operand:HI 1 "any_operand" ""))] | |
7622 | "" | |
7623 | " | |
7624 | { | |
9ebbca7d | 7625 | if (! no_new_pseudos && GET_CODE (operands[0]) != REG) |
1fd4e8c1 RK |
7626 | operands[1] = force_reg (HImode, operands[1]); |
7627 | ||
3345af62 | 7628 | if (CONSTANT_P (operands[1]) |
34792e82 | 7629 | && GET_CODE (operands[1]) != CONST_INT) |
b45863ec RK |
7630 | { |
7631 | operands[1] = force_const_mem (HImode, operands[1]); | |
7632 | if (! memory_address_p (HImode, XEXP (operands[1], 0)) | |
7633 | && ! reload_in_progress) | |
7634 | operands[1] = change_address (operands[1], HImode, | |
7635 | XEXP (operands[1], 0)); | |
7636 | } | |
1fd4e8c1 RK |
7637 | }") |
7638 | ||
7639 | (define_insn "" | |
fb81d7ce RK |
7640 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7641 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7642 | "gpc_reg_operand (operands[0], HImode) |
7643 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 7644 | "@ |
deb9225a | 7645 | mr %0,%1 |
1fd4e8c1 RK |
7646 | lhz%U1%X1 %0,%1 |
7647 | sth%U0%X0 %1,%0 | |
19d5775a | 7648 | {lil|li} %0,%w1 |
1fd4e8c1 | 7649 | mf%1 %0 |
e76e75bb | 7650 | mt%0 %1 |
fb81d7ce | 7651 | mt%0 %1 |
e76e75bb | 7652 | cror 0,0,0" |
b7ff3d82 | 7653 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7654 | |
7655 | (define_expand "movqi" | |
7656 | [(set (match_operand:QI 0 "general_operand" "") | |
7657 | (match_operand:QI 1 "any_operand" ""))] | |
7658 | "" | |
7659 | " | |
7660 | { | |
9ebbca7d | 7661 | if (! no_new_pseudos && GET_CODE (operands[0]) != REG) |
1fd4e8c1 RK |
7662 | operands[1] = force_reg (QImode, operands[1]); |
7663 | ||
3345af62 | 7664 | if (CONSTANT_P (operands[1]) |
34792e82 | 7665 | && GET_CODE (operands[1]) != CONST_INT) |
b45863ec RK |
7666 | { |
7667 | operands[1] = force_const_mem (QImode, operands[1]); | |
7668 | if (! memory_address_p (QImode, XEXP (operands[1], 0)) | |
7669 | && ! reload_in_progress) | |
7670 | operands[1] = change_address (operands[1], QImode, | |
7671 | XEXP (operands[1], 0)); | |
7672 | } | |
1fd4e8c1 RK |
7673 | }") |
7674 | ||
7675 | (define_insn "" | |
fb81d7ce RK |
7676 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7677 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7678 | "gpc_reg_operand (operands[0], QImode) |
7679 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 7680 | "@ |
deb9225a | 7681 | mr %0,%1 |
1fd4e8c1 RK |
7682 | lbz%U1%X1 %0,%1 |
7683 | stb%U0%X0 %1,%0 | |
19d5775a | 7684 | {lil|li} %0,%1 |
1fd4e8c1 | 7685 | mf%1 %0 |
e76e75bb | 7686 | mt%0 %1 |
fb81d7ce | 7687 | mt%0 %1 |
e76e75bb | 7688 | cror 0,0,0" |
b7ff3d82 | 7689 | [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7690 | \f |
7691 | ;; Here is how to move condition codes around. When we store CC data in | |
7692 | ;; an integer register or memory, we store just the high-order 4 bits. | |
7693 | ;; This lets us not shift in the most common case of CR0. | |
7694 | (define_expand "movcc" | |
7695 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
7696 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
7697 | "" | |
7698 | "") | |
7699 | ||
7700 | (define_insn "" | |
7701 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m") | |
7702 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))] | |
7703 | "register_operand (operands[0], CCmode) | |
7704 | || register_operand (operands[1], CCmode)" | |
7705 | "@ | |
7706 | mcrf %0,%1 | |
7707 | mtcrf 128,%1 | |
ca7f5001 | 7708 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
1fd4e8c1 | 7709 | mfcr %0 |
ca7f5001 | 7710 | mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 |
deb9225a | 7711 | mr %0,%1 |
ca7f5001 RK |
7712 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7713 | {st%U0%U1|stw%U0%U1} %1,%0" | |
b7ff3d82 | 7714 | [(set_attr "type" "*,*,*,compare,*,*,load,store") |
b19003d8 | 7715 | (set_attr "length" "*,*,12,*,8,*,*,*")]) |
1fd4e8c1 | 7716 | \f |
e52e05ca MM |
7717 | ;; For floating-point, we normally deal with the floating-point registers |
7718 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
7719 | ;; can produce floating-point values in fixed-point registers. Unless the | |
7720 | ;; value is a simple constant or already in memory, we deal with this by | |
7721 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
7722 | (define_expand "movsf" |
7723 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
7724 | (match_operand:SF 1 "any_operand" ""))] | |
7725 | "" | |
7726 | " | |
7727 | { | |
7728 | /* If we are called from reload, we might be getting a SUBREG of a hard | |
7729 | reg. So expand it. */ | |
7730 | if (GET_CODE (operands[0]) == SUBREG | |
7731 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
62961522 GK |
7732 | && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER |
7733 | && (! REG_FUNCTION_VALUE_P (SUBREG_REG (operands[0])) | |
7734 | || ! rtx_equal_function_value_matters)) | |
1fd4e8c1 RK |
7735 | operands[0] = alter_subreg (operands[0]); |
7736 | if (GET_CODE (operands[1]) == SUBREG | |
7737 | && GET_CODE (SUBREG_REG (operands[1])) == REG | |
7738 | && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER) | |
7739 | operands[1] = alter_subreg (operands[1]); | |
7740 | ||
f99f88e0 | 7741 | if (GET_CODE (operands[0]) == MEM) |
1fd4e8c1 | 7742 | { |
f99f88e0 DE |
7743 | /* If operands[1] is a register, it may have double-precision data |
7744 | in it, so truncate it to single precision. We need not do | |
7745 | this for POWERPC. */ | |
7746 | if (! TARGET_POWERPC && TARGET_HARD_FLOAT | |
7747 | && GET_CODE (operands[1]) == REG | |
7748 | && (FP_REGNO_P (REGNO (operands[1])) | |
7749 | || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)) | |
f2974b07 | 7750 | { |
677a9668 | 7751 | rtx newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (SFmode)); |
f99f88e0 DE |
7752 | emit_insn (gen_aux_truncdfsf2 (newreg, operands[1])); |
7753 | operands[1] = newreg; | |
f2974b07 RK |
7754 | } |
7755 | ||
f99f88e0 | 7756 | operands[1] = force_reg (SFmode, operands[1]); |
1fd4e8c1 RK |
7757 | } |
7758 | ||
22e228e7 JL |
7759 | if (CONSTANT_P (operands[1]) && TARGET_HARD_FLOAT |
7760 | && ! easy_fp_constant (operands[1], SFmode)) | |
1fd4e8c1 RK |
7761 | { |
7762 | operands[1] = force_const_mem (SFmode, operands[1]); | |
7763 | if (! memory_address_p (SFmode, XEXP (operands[1], 0)) | |
7764 | && ! reload_in_progress) | |
7765 | operands[1] = change_address (operands[1], SFmode, | |
7766 | XEXP (operands[1], 0)); | |
7767 | } | |
7768 | }") | |
7769 | ||
1fd4e8c1 | 7770 | (define_split |
cd2b37d9 | 7771 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 7772 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 7773 | "reload_completed |
5ae4759c MM |
7774 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7775 | || (GET_CODE (operands[0]) == SUBREG | |
7776 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7777 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 7778 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
7779 | " |
7780 | { | |
7781 | long l; | |
7782 | REAL_VALUE_TYPE rv; | |
7783 | ||
7784 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7785 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 7786 | |
f99f88e0 DE |
7787 | if (! TARGET_POWERPC64) |
7788 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
7789 | else | |
7790 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 7791 | |
a260abc9 DE |
7792 | operands[3] = GEN_INT(l); |
7793 | }") | |
7794 | ||
c4c40373 | 7795 | (define_insn "*movsf_hardfloat" |
f99f88e0 DE |
7796 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r") |
7797 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))] | |
d14a6d05 MM |
7798 | "(gpc_reg_operand (operands[0], SFmode) |
7799 | || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT" | |
1fd4e8c1 | 7800 | "@ |
f99f88e0 DE |
7801 | mr %0,%1 |
7802 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7803 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
7804 | fmr %0,%1 |
7805 | lfs%U1%X1 %0,%1 | |
c4c40373 MM |
7806 | stfs%U0%X0 %1,%0 |
7807 | # | |
7808 | #" | |
f99f88e0 DE |
7809 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*") |
7810 | (set_attr "length" "4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7811 | |
c4c40373 MM |
7812 | (define_insn "*movsf_softfloat" |
7813 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r") | |
9615f239 | 7814 | (match_operand:SF 1 "input_operand" "r,m,r,I,L,R,G,Fn"))] |
d14a6d05 MM |
7815 | "(gpc_reg_operand (operands[0], SFmode) |
7816 | || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT" | |
7817 | "@ | |
7818 | mr %0,%1 | |
7819 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7820 | {st%U0%X0|stw%U0%X0} %1,%0 | |
7821 | {lil|li} %0,%1 | |
802a0058 | 7822 | {liu|lis} %0,%v1 |
c4c40373 MM |
7823 | {cal|la} %0,%1(%*) |
7824 | # | |
7825 | #" | |
7826 | [(set_attr "type" "*,load,store,*,*,*,*,*") | |
7827 | (set_attr "length" "4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7828 | |
1fd4e8c1 RK |
7829 | \f |
7830 | (define_expand "movdf" | |
7831 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
7832 | (match_operand:DF 1 "any_operand" ""))] | |
7833 | "" | |
7834 | " | |
7835 | { | |
e7113111 RK |
7836 | if (GET_CODE (operands[0]) != REG) |
7837 | operands[1] = force_reg (DFmode, operands[1]); | |
1fd4e8c1 | 7838 | |
e7113111 | 7839 | if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode)) |
1fd4e8c1 RK |
7840 | { |
7841 | operands[1] = force_const_mem (DFmode, operands[1]); | |
7842 | if (! memory_address_p (DFmode, XEXP (operands[1], 0)) | |
7843 | && ! reload_in_progress) | |
7844 | operands[1] = change_address (operands[1], DFmode, | |
7845 | XEXP (operands[1], 0)); | |
7846 | } | |
e7113111 | 7847 | }") |
1fd4e8c1 RK |
7848 | |
7849 | (define_split | |
cd2b37d9 | 7850 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 7851 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 7852 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7853 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7854 | || (GET_CODE (operands[0]) == SUBREG | |
7855 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7856 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7857 | [(set (match_dup 2) (match_dup 4)) |
7858 | (set (match_dup 3) (match_dup 1))] | |
7859 | " | |
7860 | { | |
5ae4759c | 7861 | int endian = (WORDS_BIG_ENDIAN == 0); |
5f59ecb7 DE |
7862 | HOST_WIDE_INT value = INTVAL (operands[1]); |
7863 | ||
5ae4759c MM |
7864 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7865 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
5f59ecb7 DE |
7866 | #if HOST_BITS_PER_WIDE_INT == 32 |
7867 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
7868 | #else | |
7869 | operands[4] = GEN_INT (value >> 32); | |
7870 | operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000)); | |
7871 | #endif | |
c4c40373 MM |
7872 | }") |
7873 | ||
c4c40373 MM |
7874 | (define_split |
7875 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
7876 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 7877 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7878 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7879 | || (GET_CODE (operands[0]) == SUBREG | |
7880 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7881 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7882 | [(set (match_dup 2) (match_dup 4)) |
7883 | (set (match_dup 3) (match_dup 5))] | |
7884 | " | |
7885 | { | |
5ae4759c | 7886 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
7887 | long l[2]; |
7888 | REAL_VALUE_TYPE rv; | |
7889 | ||
7890 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7891 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7892 | ||
5ae4759c MM |
7893 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7894 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
47ad8c61 MM |
7895 | operands[4] = GEN_INT (l[endian]); |
7896 | operands[5] = GEN_INT (l[1 - endian]); | |
c4c40373 MM |
7897 | }") |
7898 | ||
efc08378 DE |
7899 | (define_split |
7900 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
685f3906 | 7901 | (match_operand:DF 1 "easy_fp_constant" ""))] |
a260abc9 | 7902 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7903 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7904 | || (GET_CODE (operands[0]) == SUBREG | |
7905 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7906 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 7907 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 7908 | " |
a260abc9 DE |
7909 | { |
7910 | int endian = (WORDS_BIG_ENDIAN == 0); | |
7911 | long l[2]; | |
7912 | REAL_VALUE_TYPE rv; | |
7913 | ||
7914 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7915 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7916 | ||
7917 | operands[2] = gen_lowpart (DImode, operands[0]); | |
7918 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
7919 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); | |
7920 | }") | |
efc08378 | 7921 | |
4eae5fe1 | 7922 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 7923 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
7924 | ;; a non-offsettable memref, but also it is less efficient than loading |
7925 | ;; the constant into an FP register, since it will probably be used there. | |
7926 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
7927 | ;; of handling these non-offsettable values. | |
c4c40373 | 7928 | (define_insn "*movdf_hardfloat32" |
000034eb DE |
7929 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") |
7930 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] | |
dc4f83ca | 7931 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT |
52d3af72 DE |
7932 | && (gpc_reg_operand (operands[0], DFmode) |
7933 | || gpc_reg_operand (operands[1], DFmode))" | |
e7113111 RK |
7934 | "* |
7935 | { | |
7936 | switch (which_alternative) | |
7937 | { | |
a260abc9 | 7938 | default: |
a6c2a102 | 7939 | abort (); |
e7113111 RK |
7940 | case 0: |
7941 | /* We normally copy the low-numbered register first. However, if | |
000034eb DE |
7942 | the first register operand 0 is the same as the second register |
7943 | of operand 1, we must copy in the opposite order. */ | |
e7113111 | 7944 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) |
deb9225a | 7945 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 7946 | else |
deb9225a | 7947 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 | 7948 | case 1: |
2b97222d DE |
7949 | if (offsettable_memref_p (operands[1]) |
7950 | || (GET_CODE (operands[1]) == MEM | |
69f51a21 DE |
7951 | && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM |
7952 | || GET_CODE (XEXP (operands[1], 0)) == PRE_INC | |
7953 | || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))) | |
000034eb DE |
7954 | { |
7955 | /* If the low-address word is used in the address, we must load | |
7956 | it last. Otherwise, load it first. Note that we cannot have | |
7957 | auto-increment in that case since the address register is | |
7958 | known to be dead. */ | |
7959 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
7960 | operands[1], 0)) | |
7961 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
7962 | else | |
7963 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
7964 | } | |
e7113111 | 7965 | else |
000034eb DE |
7966 | { |
7967 | rtx addreg; | |
7968 | ||
000034eb DE |
7969 | addreg = find_addr_reg (XEXP (operands[1], 0)); |
7970 | if (refers_to_regno_p (REGNO (operands[0]), | |
7971 | REGNO (operands[0]) + 1, | |
7972 | operands[1], 0)) | |
7973 | { | |
7974 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); | |
2b97222d | 7975 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb | 7976 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
2b97222d | 7977 | return \"{lx|lwzx} %0,%1\"; |
000034eb DE |
7978 | } |
7979 | else | |
7980 | { | |
2b97222d | 7981 | output_asm_insn (\"{lx|lwzx} %0,%1\", operands); |
000034eb | 7982 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 7983 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb DE |
7984 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
7985 | return \"\"; | |
7986 | } | |
7987 | } | |
e7113111 | 7988 | case 2: |
2b97222d DE |
7989 | if (offsettable_memref_p (operands[0]) |
7990 | || (GET_CODE (operands[0]) == MEM | |
69f51a21 DE |
7991 | && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM |
7992 | || GET_CODE (XEXP (operands[0], 0)) == PRE_INC | |
7993 | || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC))) | |
000034eb DE |
7994 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
7995 | else | |
7996 | { | |
7997 | rtx addreg; | |
7998 | ||
000034eb | 7999 | addreg = find_addr_reg (XEXP (operands[0], 0)); |
2b97222d | 8000 | output_asm_insn (\"{stx|stwx} %1,%0\", operands); |
000034eb | 8001 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8002 | output_asm_insn (\"{stx|stwx} %L1,%0\", operands); |
000034eb DE |
8003 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8004 | return \"\"; | |
8005 | } | |
e7113111 | 8006 | case 3: |
e7113111 | 8007 | case 4: |
e7113111 | 8008 | case 5: |
c4c40373 | 8009 | return \"#\"; |
e7113111 | 8010 | case 6: |
c4c40373 MM |
8011 | return \"fmr %0,%1\"; |
8012 | case 7: | |
8013 | return \"lfd%U1%X1 %0,%1\"; | |
8014 | case 8: | |
e7113111 RK |
8015 | return \"stfd%U0%X0 %1,%0\"; |
8016 | } | |
8017 | }" | |
c4c40373 | 8018 | [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") |
2f76d42c | 8019 | (set_attr "length" "8,16,16,8,12,16,*,*,*")]) |
51b8fc2c | 8020 | |
c4c40373 | 8021 | (define_insn "*movdf_softfloat32" |
1427100a DE |
8022 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
8023 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
dc4f83ca | 8024 | "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT |
52d3af72 DE |
8025 | && (gpc_reg_operand (operands[0], DFmode) |
8026 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
8027 | "* |
8028 | { | |
8029 | switch (which_alternative) | |
8030 | { | |
a260abc9 | 8031 | default: |
a6c2a102 | 8032 | abort (); |
dc4f83ca MM |
8033 | case 0: |
8034 | /* We normally copy the low-numbered register first. However, if | |
8035 | the first register operand 0 is the same as the second register of | |
8036 | operand 1, we must copy in the opposite order. */ | |
8037 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8038 | return \"mr %L0,%L1\;mr %0,%1\"; | |
8039 | else | |
8040 | return \"mr %0,%1\;mr %L0,%L1\"; | |
8041 | case 1: | |
3cb999d8 DE |
8042 | /* If the low-address word is used in the address, we must load |
8043 | it last. Otherwise, load it first. Note that we cannot have | |
8044 | auto-increment in that case since the address register is | |
8045 | known to be dead. */ | |
dc4f83ca | 8046 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, |
3cb999d8 | 8047 | operands[1], 0)) |
dc4f83ca MM |
8048 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
8049 | else | |
8050 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
8051 | case 2: | |
8052 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
8053 | case 3: | |
c4c40373 MM |
8054 | case 4: |
8055 | case 5: | |
dc4f83ca MM |
8056 | return \"#\"; |
8057 | } | |
8058 | }" | |
c4c40373 MM |
8059 | [(set_attr "type" "*,load,store,*,*,*") |
8060 | (set_attr "length" "8,8,8,8,12,16")]) | |
dc4f83ca | 8061 | |
c4c40373 | 8062 | (define_insn "*movdf_hardfloat64" |
1427100a DE |
8063 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") |
8064 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] | |
dc4f83ca | 8065 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT |
52d3af72 DE |
8066 | && (gpc_reg_operand (operands[0], DFmode) |
8067 | || gpc_reg_operand (operands[1], DFmode))" | |
51b8fc2c | 8068 | "@ |
3d5570cb RK |
8069 | mr %0,%1 |
8070 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8071 | std%U0%X0 %1,%0 |
3d5570cb | 8072 | # |
c4c40373 MM |
8073 | # |
8074 | # | |
3d5570cb | 8075 | fmr %0,%1 |
f63184ac | 8076 | lfd%U1%X1 %0,%1 |
3d5570cb | 8077 | stfd%U0%X0 %1,%0" |
c4c40373 MM |
8078 | [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") |
8079 | (set_attr "length" "4,4,4,8,12,16,4,4,4")]) | |
dc4f83ca | 8080 | |
c4c40373 | 8081 | (define_insn "*movdf_softfloat64" |
1427100a DE |
8082 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
8083 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
dc4f83ca | 8084 | "TARGET_POWERPC64 && TARGET_SOFT_FLOAT |
52d3af72 DE |
8085 | && (gpc_reg_operand (operands[0], DFmode) |
8086 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
8087 | "@ |
8088 | mr %0,%1 | |
8089 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8090 | std%U0%X0 %1,%0 |
c4c40373 MM |
8091 | # |
8092 | # | |
dc4f83ca | 8093 | #" |
c4c40373 MM |
8094 | [(set_attr "type" "*,load,store,*,*,*") |
8095 | (set_attr "length" "*,*,*,8,12,16")]) | |
1fd4e8c1 RK |
8096 | \f |
8097 | ;; Next come the multi-word integer load and store and the load and store | |
8098 | ;; multiple insns. | |
8099 | (define_expand "movdi" | |
8100 | [(set (match_operand:DI 0 "general_operand" "") | |
e6ca2c17 | 8101 | (match_operand:DI 1 "any_operand" ""))] |
1fd4e8c1 RK |
8102 | "" |
8103 | " | |
8104 | { | |
9ebbca7d | 8105 | if (! no_new_pseudos && GET_CODE (operands[0]) != REG) |
6b6ccd10 RK |
8106 | operands[1] = force_reg (DImode, operands[1]); |
8107 | ||
a260abc9 DE |
8108 | /* Convert a move of a CONST_DOUBLE into a CONST_INT |
8109 | only if sign-extended lower-half for 32-bit host. */ | |
8110 | if (GET_CODE (operands[1]) == CONST_DOUBLE | |
e8d791dd | 8111 | #if HOST_BITS_PER_WIDE_INT == 32 |
a260abc9 DE |
8112 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 |
8113 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0) | |
d330fd93 | 8114 | || (CONST_DOUBLE_HIGH (operands[1]) == (HOST_WIDE_INT) 0xffffffff |
a260abc9 | 8115 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0)) |
e8d791dd | 8116 | #endif |
a260abc9 DE |
8117 | ) |
8118 | operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
6b6ccd10 | 8119 | |
34792e82 | 8120 | /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */ |
01b4cf2b | 8121 | if (GET_CODE (operands[1]) == CONSTANT_P_RTX) |
34792e82 JL |
8122 | { |
8123 | emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); | |
8124 | DONE; | |
8125 | } | |
8126 | ||
a260abc9 DE |
8127 | if (TARGET_64BIT |
8128 | && CONSTANT_P (operands[1]) | |
8129 | #if HOST_BITS_PER_WIDE_INT == 32 | |
8130 | && GET_CODE (operands[1]) != CONST_INT | |
8131 | #endif | |
8132 | && ! easy_fp_constant (operands[1], DImode) | |
9ebbca7d GK |
8133 | && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]) |
8134 | && ! TOC_RELATIVE_EXPR_P (operands[1])) | |
a260abc9 DE |
8135 | { |
8136 | /* Emit a USE operation so that the constant isn't deleted if | |
8137 | expensive optimizations are turned on because nobody | |
8138 | references it. This should only be done for operands that | |
8139 | contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set. | |
8140 | This should not be done for operands that contain LABEL_REFs. | |
8141 | For now, we just handle the obvious case. */ | |
8142 | if (GET_CODE (operands[1]) != LABEL_REF) | |
39403d82 | 8143 | emit_insn (gen_rtx_USE (VOIDmode, operands[1])); |
062284d8 | 8144 | |
a260abc9 DE |
8145 | /* If we are to limit the number of things we put in the TOC and |
8146 | this is a symbol plus a constant we can add in one insn, | |
8147 | just put the symbol in the TOC and add the constant. Don't do | |
8148 | this if reload is in progress. */ | |
8149 | if (GET_CODE (operands[1]) == CONST | |
8150 | && TARGET_NO_SUM_IN_TOC && ! reload_in_progress | |
8151 | && GET_CODE (XEXP (operands[1], 0)) == PLUS | |
8152 | && add_operand (XEXP (XEXP (operands[1], 0), 1), DImode) | |
8153 | && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF | |
8154 | || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF) | |
8155 | && ! side_effects_p (operands[0])) | |
8156 | { | |
8157 | rtx sym = force_const_mem (DImode, XEXP (XEXP (operands[1], 0), 0)); | |
8158 | rtx other = XEXP (XEXP (operands[1], 0), 1); | |
a473029f | 8159 | |
a260abc9 DE |
8160 | emit_insn (gen_adddi3 (operands[0], force_reg (DImode, sym), other)); |
8161 | DONE; | |
8162 | } | |
a473029f | 8163 | |
a260abc9 | 8164 | operands[1] = force_const_mem (DImode, operands[1]); |
f176e826 GK |
8165 | |
8166 | if (TARGET_TOC | |
8167 | && CONSTANT_POOL_EXPR_P (XEXP (operands[1], 0)) | |
8168 | && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant ( | |
8169 | XEXP (operands[1], 0)))) | |
9ebbca7d | 8170 | { |
f176e826 GK |
8171 | operands[1] = gen_rtx_MEM (DImode, |
8172 | create_TOC_reference (XEXP (operands[1], 0))); | |
8173 | ||
9ebbca7d GK |
8174 | MEM_ALIAS_SET (operands[1]) = get_TOC_alias_set (); |
8175 | RTX_UNCHANGING_P (operands[1]) = 1; | |
8176 | } | |
f176e826 | 8177 | |
a260abc9 DE |
8178 | if (! memory_address_p (DImode, XEXP (operands[1], 0)) |
8179 | && ! reload_in_progress) | |
8180 | operands[1] = change_address (operands[1], DImode, | |
8181 | XEXP (operands[1], 0)); | |
a473029f | 8182 | } |
1fd4e8c1 RK |
8183 | }") |
8184 | ||
acad7ed3 | 8185 | (define_insn "*movdi_internal32" |
4e74d8ec MM |
8186 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r") |
8187 | (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))] | |
a260abc9 | 8188 | "! TARGET_POWERPC64 |
4e74d8ec MM |
8189 | && (gpc_reg_operand (operands[0], DImode) |
8190 | || gpc_reg_operand (operands[1], DImode))" | |
1fd4e8c1 RK |
8191 | "* |
8192 | { | |
8193 | switch (which_alternative) | |
8194 | { | |
a260abc9 | 8195 | default: |
a6c2a102 | 8196 | abort (); |
1fd4e8c1 RK |
8197 | case 0: |
8198 | /* We normally copy the low-numbered register first. However, if | |
8199 | the first register operand 0 is the same as the second register of | |
8200 | operand 1, we must copy in the opposite order. */ | |
8201 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
deb9225a | 8202 | return \"mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 8203 | else |
deb9225a | 8204 | return \"mr %0,%1\;mr %L0,%L1\"; |
1fd4e8c1 RK |
8205 | case 1: |
8206 | /* If the low-address word is used in the address, we must load it | |
8207 | last. Otherwise, load it first. Note that we cannot have | |
8208 | auto-increment in that case since the address register is known to be | |
8209 | dead. */ | |
8210 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 8211 | operands[1], 0)) |
ca7f5001 | 8212 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
1fd4e8c1 | 8213 | else |
ca7f5001 | 8214 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 | 8215 | case 2: |
ca7f5001 | 8216 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8ffd9c51 RK |
8217 | case 3: |
8218 | return \"fmr %0,%1\"; | |
8219 | case 4: | |
8220 | return \"lfd%U1%X1 %0,%1\"; | |
8221 | case 5: | |
8222 | return \"stfd%U0%X0 %1,%0\"; | |
4e74d8ec MM |
8223 | case 6: |
8224 | case 7: | |
8225 | case 8: | |
8226 | case 9: | |
8227 | case 10: | |
8228 | return \"#\"; | |
1fd4e8c1 RK |
8229 | } |
8230 | }" | |
4e74d8ec MM |
8231 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*") |
8232 | (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")]) | |
8233 | ||
8234 | (define_split | |
8235 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8236 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 8237 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
8238 | [(set (match_dup 2) (match_dup 4)) |
8239 | (set (match_dup 3) (match_dup 1))] | |
8240 | " | |
8241 | { | |
5f59ecb7 | 8242 | HOST_WIDE_INT value = INTVAL (operands[1]); |
39403d82 DE |
8243 | operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0); |
8244 | operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0); | |
75d39459 | 8245 | #if HOST_BITS_PER_WIDE_INT == 32 |
5f59ecb7 | 8246 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 | 8247 | #else |
5f59ecb7 DE |
8248 | operands[4] = GEN_INT (value >> 32); |
8249 | operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000)); | |
75d39459 | 8250 | #endif |
4e74d8ec MM |
8251 | }") |
8252 | ||
4e74d8ec MM |
8253 | (define_split |
8254 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8255 | (match_operand:DI 1 "const_double_operand" ""))] | |
75d39459 | 8256 | "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
8257 | [(set (match_dup 2) (match_dup 4)) |
8258 | (set (match_dup 3) (match_dup 5))] | |
8259 | " | |
8260 | { | |
39403d82 DE |
8261 | operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0); |
8262 | operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0); | |
f6968f59 MM |
8263 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); |
8264 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
4e74d8ec MM |
8265 | }") |
8266 | ||
acad7ed3 | 8267 | (define_insn "*movdi_internal64" |
e6ca2c17 | 8268 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h") |
9615f239 | 8269 | (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 8270 | "TARGET_POWERPC64 |
4e74d8ec MM |
8271 | && (gpc_reg_operand (operands[0], DImode) |
8272 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 8273 | "@ |
3d5570cb RK |
8274 | mr %0,%1 |
8275 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8276 | std%U0%X0 %1,%0 |
3d5570cb | 8277 | li %0,%1 |
802a0058 | 8278 | lis %0,%v1 |
e6ca2c17 | 8279 | # |
57fa6739 | 8280 | {cal|la} %0,%1(%*) |
3d5570cb RK |
8281 | fmr %0,%1 |
8282 | lfd%U1%X1 %0,%1 | |
8283 | stfd%U0%X0 %1,%0 | |
8284 | mf%1 %0 | |
08075ead DE |
8285 | mt%0 %1 |
8286 | cror 0,0,0" | |
b7ff3d82 | 8287 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*") |
e6ca2c17 DE |
8288 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
8289 | ||
5f59ecb7 | 8290 | ;; immediate value valid for a single instruction hiding in a const_double |
a260abc9 DE |
8291 | (define_insn "" |
8292 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
8293 | (match_operand:DI 1 "const_double_operand" "F"))] | |
5f59ecb7 DE |
8294 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
8295 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
a260abc9 DE |
8296 | && num_insns_constant (operands[1], DImode) == 1" |
8297 | "* | |
8298 | { | |
8299 | return ((unsigned HOST_WIDE_INT) | |
8300 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
8301 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
8302 | }") | |
8303 | ||
5f59ecb7 | 8304 | ;; sign-extended 32-bit value |
a260abc9 DE |
8305 | (define_split |
8306 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8307 | (match_operand:DI 1 "const_int_operand" ""))] | |
8308 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 | |
8309 | && num_insns_constant (operands[1], DImode) > 1" | |
8310 | [(set (match_dup 0) | |
8311 | (match_dup 2)) | |
8312 | (set (match_dup 0) | |
8313 | (ior:DI (match_dup 0) | |
8314 | (match_dup 3)))] | |
8315 | " | |
8316 | { | |
8317 | operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000); | |
8318 | operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); | |
8319 | }") | |
e6ca2c17 DE |
8320 | |
8321 | (define_split | |
8322 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8323 | (match_operand:DI 1 "const_double_operand" ""))] | |
a260abc9 DE |
8324 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
8325 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
8326 | && ((CONST_DOUBLE_HIGH (operands[1]) == 0 | |
8327 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0) | |
5f59ecb7 | 8328 | || (CONST_DOUBLE_HIGH (operands[1]) == -1 |
a260abc9 | 8329 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))" |
e6ca2c17 DE |
8330 | [(set (match_dup 0) |
8331 | (match_dup 2)) | |
8332 | (set (match_dup 0) | |
8333 | (ior:DI (match_dup 0) | |
a260abc9 DE |
8334 | (match_dup 3)))] |
8335 | " | |
8336 | { | |
8337 | operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xffff0000); | |
8338 | operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xffff); | |
8339 | }") | |
8340 | ||
5f59ecb7 DE |
8341 | (define_split |
8342 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8343 | (match_operand:DI 1 "const_int_operand" ""))] | |
8344 | "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64 | |
8345 | && GET_CODE (operands[1]) == CONST_INT | |
8346 | && (((INTVAL (operands[1]) >> 32) == 0 | |
8347 | && (INTVAL (operands[1]) & 0x80000000) == 0) | |
8348 | || ((INTVAL (operands[1]) >> 32) == -1 | |
8349 | && (INTVAL (operands[1]) & 0x80000000) != 0)) | |
8350 | && num_insns_constant (operands[1], DImode) > 1" | |
8351 | [(set (match_dup 0) | |
8352 | (match_dup 2)) | |
8353 | (set (match_dup 0) | |
8354 | (ior:DI (match_dup 0) | |
8355 | (match_dup 3)))] | |
8356 | " | |
8357 | { | |
8358 | operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000); | |
8359 | operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); | |
8360 | }") | |
8361 | ||
8362 | ;; zero-extended 32-bit value | |
a260abc9 DE |
8363 | (define_split |
8364 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8365 | (match_operand:DI 1 "const_double_operand" ""))] | |
8366 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 | |
8367 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
8368 | && CONST_DOUBLE_HIGH (operands[1]) == 0 | |
8369 | && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0" | |
8370 | [(set (match_dup 0) | |
8371 | (match_dup 2)) | |
8372 | (set (match_dup 0) | |
8373 | (zero_extend:DI (subreg:SI (match_dup 0) 0)))] | |
8374 | " | |
8375 | { operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); }") | |
8376 | ||
5f59ecb7 DE |
8377 | (define_split |
8378 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8379 | (match_operand:DI 1 "const_int_operand" ""))] | |
8380 | "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64 | |
8381 | && GET_CODE (operands[1]) == CONST_INT | |
8382 | && INTVAL (operands[1]) >> 32 == 0 | |
8383 | && (INTVAL (operands[1]) & 0x80000000) != 0 | |
8384 | && num_insns_constant (operands[1], DImode) > 1" | |
8385 | [(set (match_dup 0) | |
8386 | (match_dup 2)) | |
8387 | (set (match_dup 0) | |
8388 | (zero_extend:DI (subreg:SI (match_dup 0) 0)))] | |
8389 | " | |
9ebbca7d GK |
8390 | { |
8391 | #if HOST_BITS_PER_WIDE_INT != 32 | |
8392 | operands[2] = GEN_INT ((INTVAL (operands[1]) << 32) >> 32); | |
8393 | #endif | |
8394 | }") | |
5f59ecb7 DE |
8395 | |
8396 | ;; 32-bit value in upper half of doubleword | |
a260abc9 DE |
8397 | (define_split |
8398 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8399 | (match_operand:DI 1 "const_double_operand" ""))] | |
8400 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 | |
8401 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
8402 | && CONST_DOUBLE_LOW (operands[1]) == 0" | |
8403 | [(set (match_dup 0) | |
8404 | (match_dup 2)) | |
e6ca2c17 DE |
8405 | (set (match_dup 0) |
8406 | (ashift:DI (match_dup 0) | |
a260abc9 DE |
8407 | (const_int 32)))] |
8408 | " | |
8409 | { operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); }") | |
8410 | ||
5f59ecb7 DE |
8411 | (define_split |
8412 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8413 | (match_operand:DI 1 "const_int_operand" ""))] | |
8414 | "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64 | |
8415 | && GET_CODE (operands[1]) == CONST_INT | |
9ebbca7d | 8416 | && (INTVAL (operands[1]) & 0xffffffff) == 0" |
5f59ecb7 DE |
8417 | [(set (match_dup 0) |
8418 | (match_dup 2)) | |
8419 | (set (match_dup 0) | |
8420 | (ashift:DI (match_dup 0) | |
8421 | (const_int 32)))] | |
8422 | " | |
9ebbca7d GK |
8423 | { |
8424 | #if HOST_BITS_PER_WIDE_INT != 32 | |
8425 | operands[2] = GEN_INT (INTVAL (operands[1]) >> 32); | |
8426 | #endif | |
8427 | }") | |
5f59ecb7 | 8428 | |
a260abc9 DE |
8429 | ;; Generate all one-bits and clear left or right. |
8430 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
8431 | (define_split | |
8432 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8433 | (match_operand:DI 1 "mask64_operand" ""))] | |
8434 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8435 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 8436 | (set (match_dup 0) |
a260abc9 DE |
8437 | (and:DI (rotate:DI (match_dup 0) |
8438 | (const_int 0)) | |
8439 | (match_dup 1)))] | |
8440 | "") | |
8441 | ||
8442 | ;; Split a load of a large constant into the appropriate five-instruction | |
8443 | ;; sequence. Handle anything in a constant number of insns. | |
8444 | ;; When non-easy constants can go in the TOC, this should use | |
8445 | ;; easy_fp_constant predicate. | |
8446 | (define_split | |
8447 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8448 | (match_operand:DI 1 "const_double_operand" ""))] | |
5f59ecb7 DE |
8449 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
8450 | && num_insns_constant (operands[1], DImode) > 1" | |
a260abc9 DE |
8451 | [(set (match_dup 0) |
8452 | (match_dup 2)) | |
8453 | (set (match_dup 0) | |
8454 | (ashift:DI (match_dup 0) | |
8455 | (const_int 32))) | |
e6ca2c17 DE |
8456 | (set (match_dup 0) |
8457 | (ior:DI (match_dup 0) | |
a260abc9 | 8458 | (match_dup 3)))] |
e6ca2c17 DE |
8459 | " |
8460 | { | |
e6ca2c17 DE |
8461 | if (GET_CODE (operands[1]) == CONST_DOUBLE) |
8462 | { | |
5f59ecb7 | 8463 | operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); |
9ebbca7d GK |
8464 | operands[3] = immed_double_const (CONST_DOUBLE_LOW (operands[1]), |
8465 | 0, DImode); | |
e6ca2c17 | 8466 | } |
e8d791dd | 8467 | else |
e6ca2c17 | 8468 | { |
5f59ecb7 DE |
8469 | HOST_WIDE_INT value = INTVAL (operands[1]); |
8470 | operands[2] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
9ebbca7d | 8471 | operands[3] = immed_double_const (value, 0, DImode); |
e6ca2c17 | 8472 | } |
5f59ecb7 | 8473 | }") |
e6ca2c17 | 8474 | |
5f59ecb7 DE |
8475 | (define_split |
8476 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8477 | (match_operand:DI 1 "const_int_operand" ""))] | |
8478 | "HOST_BITS_PER_WIDE_INT != 32 && TARGET_POWERPC64 | |
8479 | && num_insns_constant (operands[1], DImode) > 1" | |
8480 | [(set (match_dup 0) | |
8481 | (match_dup 2)) | |
8482 | (set (match_dup 0) | |
8483 | (ashift:DI (match_dup 0) | |
8484 | (const_int 32))) | |
8485 | (set (match_dup 0) | |
8486 | (ior:DI (match_dup 0) | |
8487 | (match_dup 3)))] | |
8488 | " | |
8489 | { | |
9ebbca7d | 8490 | #if HOST_BITS_PER_WIDE_INT != 32 |
5f59ecb7 DE |
8491 | HOST_WIDE_INT value = INTVAL (operands[1]); |
8492 | operands[2] = GEN_INT (value >> 32); | |
8493 | operands[3] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000)); | |
9ebbca7d | 8494 | #endif |
e6ca2c17 | 8495 | }") |
08075ead | 8496 | |
acad7ed3 | 8497 | (define_insn "*movdi_internal2" |
9ebbca7d GK |
8498 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
8499 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
08075ead | 8500 | (const_int 0))) |
9ebbca7d | 8501 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))] |
08075ead | 8502 | "TARGET_POWERPC64" |
9ebbca7d GK |
8503 | "@ |
8504 | mr. %0,%1 | |
8505 | #" | |
8506 | [(set_attr "type" "compare") | |
8507 | (set_attr "length" "4,8")]) | |
acad7ed3 | 8508 | |
9ebbca7d GK |
8509 | (define_split |
8510 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
8511 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "") | |
8512 | (const_int 0))) | |
8513 | (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))] | |
8514 | "TARGET_POWERPC64 && reload_completed" | |
8515 | [(set (match_dup 0) (match_dup 1)) | |
8516 | (set (match_dup 2) | |
8517 | (compare:CC (match_dup 0) | |
8518 | (const_int 0)))] | |
8519 | "") | |
acad7ed3 | 8520 | \f |
1fd4e8c1 RK |
8521 | ;; TImode is similar, except that we usually want to compute the address into |
8522 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 8523 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
8524 | (define_expand "movti" |
8525 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
8526 | (match_operand:TI 1 "general_operand" "")) | |
8527 | (clobber (scratch:SI))])] | |
7e69e155 | 8528 | "TARGET_STRING || TARGET_POWERPC64" |
1fd4e8c1 RK |
8529 | " |
8530 | { | |
8531 | if (GET_CODE (operands[0]) == MEM) | |
8532 | operands[1] = force_reg (TImode, operands[1]); | |
8533 | ||
8534 | if (GET_CODE (operands[0]) == MEM | |
8535 | && GET_CODE (XEXP (operands[0], 0)) != REG | |
8536 | && ! reload_in_progress) | |
8537 | operands[0] = change_address (operands[0], TImode, | |
8538 | copy_addr_to_reg (XEXP (operands[0], 0))); | |
8539 | ||
8540 | if (GET_CODE (operands[1]) == MEM | |
8541 | && GET_CODE (XEXP (operands[1], 0)) != REG | |
8542 | && ! reload_in_progress) | |
8543 | operands[1] = change_address (operands[1], TImode, | |
8544 | copy_addr_to_reg (XEXP (operands[1], 0))); | |
8545 | }") | |
8546 | ||
8547 | ;; We say that MQ is clobbered in the last alternative because the first | |
8548 | ;; alternative would never get used otherwise since it would need a reload | |
8549 | ;; while the 2nd alternative would not. We put memory cases first so they | |
8550 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
8551 | ;; giving the SCRATCH mq. | |
a260abc9 | 8552 | (define_insn "*movti_power" |
e1469d0d | 8553 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
1fd4e8c1 RK |
8554 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) |
8555 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] | |
7e69e155 | 8556 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 8557 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
8558 | "* |
8559 | { | |
8560 | switch (which_alternative) | |
8561 | { | |
dc4f83ca MM |
8562 | default: |
8563 | abort (); | |
8564 | ||
1fd4e8c1 | 8565 | case 0: |
ca7f5001 | 8566 | return \"{stsi|stswi} %1,%P0,16\"; |
1fd4e8c1 RK |
8567 | |
8568 | case 1: | |
ca7f5001 | 8569 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; |
1fd4e8c1 RK |
8570 | |
8571 | case 2: | |
8572 | /* Normally copy registers with lowest numbered register copied first. | |
8573 | But copy in the other order if the first register of the output | |
8574 | is the second, third, or fourth register in the input. */ | |
8575 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
8576 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
deb9225a | 8577 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; |
1fd4e8c1 | 8578 | else |
deb9225a | 8579 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; |
1fd4e8c1 RK |
8580 | case 3: |
8581 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8582 | fall through to generating four loads. */ | |
8583 | if (! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 8584 | return \"{lsi|lswi} %0,%P1,16\"; |
1fd4e8c1 RK |
8585 | /* ... fall through ... */ |
8586 | case 4: | |
8587 | /* If the address register is the same as the register for the lowest- | |
8588 | addressed word, load it last. Similarly for the next two words. | |
8589 | Otherwise load lowest address to highest. */ | |
8590 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8591 | operands[1], 0)) | |
ca7f5001 | 8592 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; |
1fd4e8c1 RK |
8593 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, |
8594 | REGNO (operands[0]) + 2, operands[1], 0)) | |
ca7f5001 | 8595 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; |
1fd4e8c1 RK |
8596 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, |
8597 | REGNO (operands[0]) + 3, operands[1], 0)) | |
ca7f5001 | 8598 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; |
1fd4e8c1 | 8599 | else |
ca7f5001 | 8600 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; |
1fd4e8c1 RK |
8601 | } |
8602 | }" | |
b7ff3d82 | 8603 | [(set_attr "type" "store,store,*,load,load") |
b19003d8 | 8604 | (set_attr "length" "*,16,16,*,16")]) |
51b8fc2c | 8605 | |
a260abc9 | 8606 | (define_insn "*movti_string" |
dc4f83ca MM |
8607 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r") |
8608 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,m")) | |
8609 | (clobber (match_scratch:SI 2 "=X,X,X"))] | |
0ad91047 | 8610 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
8611 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
8612 | "* | |
8613 | { | |
8614 | switch (which_alternative) | |
8615 | { | |
8616 | default: | |
8617 | abort (); | |
8618 | ||
8619 | case 0: | |
8620 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; | |
8621 | ||
8622 | case 1: | |
8623 | /* Normally copy registers with lowest numbered register copied first. | |
8624 | But copy in the other order if the first register of the output | |
8625 | is the second, third, or fourth register in the input. */ | |
8626 | if (REGNO (operands[0]) >= REGNO (operands[1]) + 1 | |
8627 | && REGNO (operands[0]) <= REGNO (operands[1]) + 3) | |
8628 | return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; | |
8629 | else | |
8630 | return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; | |
8631 | case 2: | |
8632 | /* If the address register is the same as the register for the lowest- | |
8633 | addressed word, load it last. Similarly for the next two words. | |
8634 | Otherwise load lowest address to highest. */ | |
8635 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8636 | operands[1], 0)) | |
8637 | return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\"; | |
8638 | else if (refers_to_regno_p (REGNO (operands[0]) + 1, | |
8639 | REGNO (operands[0]) + 2, operands[1], 0)) | |
8640 | return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\"; | |
8641 | else if (refers_to_regno_p (REGNO (operands[0]) + 2, | |
8642 | REGNO (operands[0]) + 3, operands[1], 0)) | |
8643 | return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\"; | |
8644 | else | |
8645 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; | |
8646 | } | |
8647 | }" | |
b7ff3d82 | 8648 | [(set_attr "type" "store,*,load") |
dc4f83ca MM |
8649 | (set_attr "length" "16,16,16")]) |
8650 | ||
a260abc9 | 8651 | (define_insn "*movti_ppc64" |
51b8fc2c RK |
8652 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") |
8653 | (match_operand:TI 1 "input_operand" "r,m,r"))] | |
8654 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) | |
8655 | || gpc_reg_operand (operands[1], TImode))" | |
8656 | "* | |
8657 | { | |
8658 | switch (which_alternative) | |
8659 | { | |
a260abc9 | 8660 | default: |
a6c2a102 | 8661 | abort (); |
51b8fc2c RK |
8662 | case 0: |
8663 | /* We normally copy the low-numbered register first. However, if | |
8664 | the first register operand 0 is the same as the second register of | |
8665 | operand 1, we must copy in the opposite order. */ | |
8666 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8667 | return \"mr %L0,%L1\;mr %0,%1\"; | |
8668 | else | |
8669 | return \"mr %0,%1\;mr %L0,%L1\"; | |
8670 | case 1: | |
8671 | /* If the low-address word is used in the address, we must load it | |
8672 | last. Otherwise, load it first. Note that we cannot have | |
8673 | auto-increment in that case since the address register is known to be | |
8674 | dead. */ | |
8675 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
3cb999d8 | 8676 | operands[1], 0)) |
51b8fc2c RK |
8677 | return \"ld %L0,%L1\;ld %0,%1\"; |
8678 | else | |
8679 | return \"ld%U1 %0,%1\;ld %L0,%L1\"; | |
8680 | case 2: | |
8681 | return \"std%U0 %1,%0\;std %L1,%L0\"; | |
8682 | } | |
8683 | }" | |
b7ff3d82 | 8684 | [(set_attr "type" "*,load,store") |
51b8fc2c | 8685 | (set_attr "length" "8,8,8")]) |
1fd4e8c1 RK |
8686 | \f |
8687 | (define_expand "load_multiple" | |
2f622005 RK |
8688 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8689 | (match_operand:SI 1 "" "")) | |
8690 | (use (match_operand:SI 2 "" ""))])] | |
7e69e155 | 8691 | "TARGET_STRING" |
1fd4e8c1 RK |
8692 | " |
8693 | { | |
8694 | int regno; | |
8695 | int count; | |
8696 | rtx from; | |
8697 | int i; | |
8698 | ||
8699 | /* Support only loading a constant number of fixed-point registers from | |
8700 | memory and only bother with this if more than two; the machine | |
8701 | doesn't support more than eight. */ | |
8702 | if (GET_CODE (operands[2]) != CONST_INT | |
8703 | || INTVAL (operands[2]) <= 2 | |
8704 | || INTVAL (operands[2]) > 8 | |
8705 | || GET_CODE (operands[1]) != MEM | |
8706 | || GET_CODE (operands[0]) != REG | |
8707 | || REGNO (operands[0]) >= 32) | |
8708 | FAIL; | |
8709 | ||
8710 | count = INTVAL (operands[2]); | |
8711 | regno = REGNO (operands[0]); | |
8712 | ||
39403d82 | 8713 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
1fd4e8c1 RK |
8714 | from = force_reg (SImode, XEXP (operands[1], 0)); |
8715 | ||
8716 | for (i = 0; i < count; i++) | |
8717 | XVECEXP (operands[3], 0, i) | |
39403d82 | 8718 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
c5c76735 JL |
8719 | change_address (operands[1], SImode, |
8720 | plus_constant (from, i * 4))); | |
1fd4e8c1 RK |
8721 | }") |
8722 | ||
8723 | (define_insn "" | |
8724 | [(match_parallel 0 "load_multiple_operation" | |
cd2b37d9 | 8725 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") |
52d3af72 | 8726 | (mem:SI (match_operand:SI 2 "gpc_reg_operand" "b")))])] |
7e69e155 | 8727 | "TARGET_STRING" |
1fd4e8c1 RK |
8728 | "* |
8729 | { | |
8730 | /* We have to handle the case where the pseudo used to contain the address | |
e82ee4cc RK |
8731 | is assigned to one of the output registers. */ |
8732 | int i, j; | |
8733 | int words = XVECLEN (operands[0], 0); | |
8734 | rtx xop[10]; | |
8735 | ||
8736 | if (XVECLEN (operands[0], 0) == 1) | |
8737 | return \"{l|lwz} %1,0(%2)\"; | |
1fd4e8c1 | 8738 | |
e82ee4cc | 8739 | for (i = 0; i < words; i++) |
1fd4e8c1 RK |
8740 | if (refers_to_regno_p (REGNO (operands[1]) + i, |
8741 | REGNO (operands[1]) + i + 1, operands[2], 0)) | |
8742 | { | |
e82ee4cc RK |
8743 | if (i == words-1) |
8744 | { | |
8745 | xop[0] = operands[1]; | |
8746 | xop[1] = operands[2]; | |
8747 | xop[2] = GEN_INT (4 * (words-1)); | |
d89ddcfd | 8748 | output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop); |
e82ee4cc RK |
8749 | return \"\"; |
8750 | } | |
8751 | else if (i == 0) | |
8752 | { | |
8753 | xop[0] = operands[1]; | |
39403d82 | 8754 | xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); |
e82ee4cc RK |
8755 | xop[2] = GEN_INT (4 * (words-1)); |
8756 | output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop); | |
8757 | return \"\"; | |
8758 | } | |
8759 | else | |
8760 | { | |
8761 | for (j = 0; j < words; j++) | |
8762 | if (j != i) | |
8763 | { | |
39403d82 | 8764 | xop[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + j); |
e82ee4cc RK |
8765 | xop[1] = operands[2]; |
8766 | xop[2] = GEN_INT (j * 4); | |
8767 | output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop); | |
8768 | } | |
8769 | xop[0] = operands[2]; | |
8770 | xop[1] = GEN_INT (i * 4); | |
8771 | output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop); | |
8772 | return \"\"; | |
8773 | } | |
1fd4e8c1 RK |
8774 | } |
8775 | ||
e82ee4cc | 8776 | return \"{lsi|lswi} %1,%2,%N0\"; |
1fd4e8c1 | 8777 | }" |
b19003d8 | 8778 | [(set_attr "type" "load") |
e82ee4cc | 8779 | (set_attr "length" "32")]) |
b19003d8 | 8780 | |
b7ff3d82 | 8781 | \f |
1fd4e8c1 | 8782 | (define_expand "store_multiple" |
2f622005 RK |
8783 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8784 | (match_operand:SI 1 "" "")) | |
8785 | (clobber (scratch:SI)) | |
8786 | (use (match_operand:SI 2 "" ""))])] | |
7e69e155 | 8787 | "TARGET_STRING" |
1fd4e8c1 RK |
8788 | " |
8789 | { | |
8790 | int regno; | |
8791 | int count; | |
8792 | rtx to; | |
8793 | int i; | |
8794 | ||
8795 | /* Support only storing a constant number of fixed-point registers to | |
8796 | memory and only bother with this if more than two; the machine | |
8797 | doesn't support more than eight. */ | |
8798 | if (GET_CODE (operands[2]) != CONST_INT | |
8799 | || INTVAL (operands[2]) <= 2 | |
8800 | || INTVAL (operands[2]) > 8 | |
8801 | || GET_CODE (operands[0]) != MEM | |
8802 | || GET_CODE (operands[1]) != REG | |
8803 | || REGNO (operands[1]) >= 32) | |
8804 | FAIL; | |
8805 | ||
8806 | count = INTVAL (operands[2]); | |
8807 | regno = REGNO (operands[1]); | |
8808 | ||
39403d82 | 8809 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 RK |
8810 | to = force_reg (SImode, XEXP (operands[0], 0)); |
8811 | ||
8812 | XVECEXP (operands[3], 0, 0) | |
39403d82 | 8813 | = gen_rtx_SET (VOIDmode, change_address (operands[0], SImode, to), |
c5c76735 | 8814 | operands[1]); |
39403d82 | 8815 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
c5c76735 | 8816 | gen_rtx_SCRATCH (SImode)); |
1fd4e8c1 RK |
8817 | |
8818 | for (i = 1; i < count; i++) | |
8819 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 8820 | = gen_rtx_SET (VOIDmode, |
c5c76735 JL |
8821 | change_address (operands[0], SImode, |
8822 | plus_constant (to, i * 4)), | |
8823 | gen_rtx_REG (SImode, regno + i)); | |
1fd4e8c1 RK |
8824 | }") |
8825 | ||
8826 | (define_insn "" | |
8827 | [(match_parallel 0 "store_multiple_operation" | |
8828 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 8829 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 8830 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 8831 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
8832 | "{stsi|stswi} %2,%P1,%O0" |
8833 | [(set_attr "type" "store")]) | |
d14a6d05 MM |
8834 | |
8835 | (define_insn "" | |
8836 | [(match_parallel 0 "store_multiple_operation" | |
52d3af72 | 8837 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
d14a6d05 MM |
8838 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
8839 | (clobber (match_scratch:SI 3 "X"))])] | |
0ad91047 | 8840 | "TARGET_STRING && ! TARGET_POWER" |
b7ff3d82 DE |
8841 | "{stsi|stswi} %2,%1,%O0" |
8842 | [(set_attr "type" "store")]) | |
7e69e155 MM |
8843 | |
8844 | \f | |
8845 | ;; String/block move insn. | |
8846 | ;; Argument 0 is the destination | |
8847 | ;; Argument 1 is the source | |
8848 | ;; Argument 2 is the length | |
8849 | ;; Argument 3 is the alignment | |
8850 | ||
8851 | (define_expand "movstrsi" | |
b6c9286a MM |
8852 | [(parallel [(set (match_operand:BLK 0 "" "") |
8853 | (match_operand:BLK 1 "" "")) | |
8854 | (use (match_operand:SI 2 "" "")) | |
8855 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
8856 | "" |
8857 | " | |
8858 | { | |
8859 | if (expand_block_move (operands)) | |
8860 | DONE; | |
8861 | else | |
8862 | FAIL; | |
8863 | }") | |
8864 | ||
8865 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
8866 | ;; register allocator doesn't have a clue about allocating 8 word registers. |
8867 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 8868 | (define_expand "movstrsi_8reg" |
b6c9286a MM |
8869 | [(parallel [(set (match_operand 0 "" "") |
8870 | (match_operand 1 "" "")) | |
8871 | (use (match_operand 2 "" "")) | |
8872 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
8873 | (clobber (reg:SI 5)) |
8874 | (clobber (reg:SI 6)) | |
8875 | (clobber (reg:SI 7)) | |
8876 | (clobber (reg:SI 8)) | |
8877 | (clobber (reg:SI 9)) | |
8878 | (clobber (reg:SI 10)) | |
8879 | (clobber (reg:SI 11)) | |
8880 | (clobber (reg:SI 12)) | |
3c67b673 | 8881 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8882 | "TARGET_STRING" |
8883 | "") | |
8884 | ||
8885 | (define_insn "" | |
52d3af72 DE |
8886 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8887 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8888 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8889 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8890 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
8891 | (clobber (reg:SI 6)) |
8892 | (clobber (reg:SI 7)) | |
8893 | (clobber (reg:SI 8)) | |
8894 | (clobber (reg:SI 9)) | |
8895 | (clobber (reg:SI 10)) | |
8896 | (clobber (reg:SI 11)) | |
8897 | (clobber (reg:SI 12)) | |
3c67b673 | 8898 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 | 8899 | "TARGET_STRING && TARGET_POWER |
f9562f27 DE |
8900 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
8901 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
8902 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
8903 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
8904 | && REGNO (operands[4]) == 5" |
8905 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8906 | [(set_attr "type" "load") |
8907 | (set_attr "length" "8")]) | |
7e69e155 MM |
8908 | |
8909 | (define_insn "" | |
52d3af72 DE |
8910 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8911 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8912 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8913 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8914 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
8915 | (clobber (reg:SI 6)) |
8916 | (clobber (reg:SI 7)) | |
8917 | (clobber (reg:SI 8)) | |
8918 | (clobber (reg:SI 9)) | |
8919 | (clobber (reg:SI 10)) | |
8920 | (clobber (reg:SI 11)) | |
8921 | (clobber (reg:SI 12)) | |
3c67b673 | 8922 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8923 | "TARGET_STRING && ! TARGET_POWER |
f9562f27 DE |
8924 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
8925 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
8926 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
8927 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
8928 | && REGNO (operands[4]) == 5" |
8929 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8930 | [(set_attr "type" "load") |
8931 | (set_attr "length" "8")]) | |
7e69e155 MM |
8932 | |
8933 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
8934 | ;; register allocator doesn't have a clue about allocating 6 word registers. |
8935 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 8936 | (define_expand "movstrsi_6reg" |
b6c9286a MM |
8937 | [(parallel [(set (match_operand 0 "" "") |
8938 | (match_operand 1 "" "")) | |
8939 | (use (match_operand 2 "" "")) | |
8940 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
8941 | (clobber (reg:SI 5)) |
8942 | (clobber (reg:SI 6)) | |
7e69e155 MM |
8943 | (clobber (reg:SI 7)) |
8944 | (clobber (reg:SI 8)) | |
8945 | (clobber (reg:SI 9)) | |
8946 | (clobber (reg:SI 10)) | |
3c67b673 | 8947 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8948 | "TARGET_STRING" |
8949 | "") | |
8950 | ||
8951 | (define_insn "" | |
52d3af72 DE |
8952 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8953 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8954 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8955 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8956 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8957 | (clobber (reg:SI 6)) |
8958 | (clobber (reg:SI 7)) | |
7e69e155 MM |
8959 | (clobber (reg:SI 8)) |
8960 | (clobber (reg:SI 9)) | |
8961 | (clobber (reg:SI 10)) | |
3c67b673 | 8962 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
8963 | "TARGET_STRING && TARGET_POWER |
8964 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
f9562f27 DE |
8965 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
8966 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
8967 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8968 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8969 | [(set_attr "type" "load") |
8970 | (set_attr "length" "8")]) | |
7e69e155 MM |
8971 | |
8972 | (define_insn "" | |
52d3af72 DE |
8973 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8974 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8975 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8976 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8977 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8978 | (clobber (reg:SI 6)) |
8979 | (clobber (reg:SI 7)) | |
7e69e155 MM |
8980 | (clobber (reg:SI 8)) |
8981 | (clobber (reg:SI 9)) | |
8982 | (clobber (reg:SI 10)) | |
3c67b673 | 8983 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8984 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8985 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 |
f9562f27 DE |
8986 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
8987 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
8988 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8989 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8990 | [(set_attr "type" "load") |
8991 | (set_attr "length" "8")]) | |
7e69e155 | 8992 | |
f9562f27 DE |
8993 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill |
8994 | ;; problems with TImode. | |
8995 | ;; rD/rS = r5 is preferred, efficient form. | |
7e69e155 | 8996 | (define_expand "movstrsi_4reg" |
b6c9286a MM |
8997 | [(parallel [(set (match_operand 0 "" "") |
8998 | (match_operand 1 "" "")) | |
8999 | (use (match_operand 2 "" "")) | |
9000 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9001 | (clobber (reg:SI 5)) |
9002 | (clobber (reg:SI 6)) | |
9003 | (clobber (reg:SI 7)) | |
9004 | (clobber (reg:SI 8)) | |
3c67b673 | 9005 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9006 | "TARGET_STRING" |
9007 | "") | |
9008 | ||
9009 | (define_insn "" | |
52d3af72 DE |
9010 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9011 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9012 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9013 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9014 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9015 | (clobber (reg:SI 6)) |
9016 | (clobber (reg:SI 7)) | |
9017 | (clobber (reg:SI 8)) | |
3c67b673 | 9018 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9019 | "TARGET_STRING && TARGET_POWER |
9020 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
f9562f27 DE |
9021 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9022 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9023 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9024 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9025 | [(set_attr "type" "load") |
9026 | (set_attr "length" "8")]) | |
7e69e155 MM |
9027 | |
9028 | (define_insn "" | |
52d3af72 DE |
9029 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9030 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9031 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9032 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9033 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9034 | (clobber (reg:SI 6)) |
9035 | (clobber (reg:SI 7)) | |
9036 | (clobber (reg:SI 8)) | |
3c67b673 | 9037 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9038 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9039 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 |
f9562f27 DE |
9040 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9041 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9042 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9043 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9044 | [(set_attr "type" "load") |
9045 | (set_attr "length" "8")]) | |
7e69e155 MM |
9046 | |
9047 | ;; Move up to 8 bytes at a time. | |
9048 | (define_expand "movstrsi_2reg" | |
b6c9286a MM |
9049 | [(parallel [(set (match_operand 0 "" "") |
9050 | (match_operand 1 "" "")) | |
9051 | (use (match_operand 2 "" "")) | |
9052 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9053 | (clobber (match_scratch:DI 4 "")) |
9054 | (clobber (match_scratch:SI 5 ""))])] | |
f9562f27 | 9055 | "TARGET_STRING && ! TARGET_POWERPC64" |
7e69e155 MM |
9056 | "") |
9057 | ||
9058 | (define_insn "" | |
52d3af72 DE |
9059 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9060 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9061 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9062 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9063 | (clobber (match_scratch:DI 4 "=&r")) | |
9064 | (clobber (match_scratch:SI 5 "=q"))] | |
f9562f27 | 9065 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
3c67b673 RK |
9066 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
9067 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9068 | [(set_attr "type" "load") |
9069 | (set_attr "length" "8")]) | |
7e69e155 MM |
9070 | |
9071 | (define_insn "" | |
52d3af72 DE |
9072 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9073 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9074 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9075 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9076 | (clobber (match_scratch:DI 4 "=&r")) | |
9077 | (clobber (match_scratch:SI 5 "X"))] | |
f9562f27 | 9078 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
7e69e155 | 9079 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
3c67b673 | 9080 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9081 | [(set_attr "type" "load") |
9082 | (set_attr "length" "8")]) | |
7e69e155 MM |
9083 | |
9084 | ;; Move up to 4 bytes at a time. | |
9085 | (define_expand "movstrsi_1reg" | |
b6c9286a MM |
9086 | [(parallel [(set (match_operand 0 "" "") |
9087 | (match_operand 1 "" "")) | |
9088 | (use (match_operand 2 "" "")) | |
9089 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9090 | (clobber (match_scratch:SI 4 "")) |
9091 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
9092 | "TARGET_STRING" |
9093 | "") | |
9094 | ||
9095 | (define_insn "" | |
52d3af72 DE |
9096 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9097 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9098 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9099 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9100 | (clobber (match_scratch:SI 4 "=&r")) | |
9101 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
9102 | "TARGET_STRING && TARGET_POWER |
9103 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9104 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9105 | [(set_attr "type" "load") |
9106 | (set_attr "length" "8")]) | |
7e69e155 MM |
9107 | |
9108 | (define_insn "" | |
52d3af72 DE |
9109 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9110 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9111 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9112 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9113 | (clobber (match_scratch:SI 4 "=&r")) | |
9114 | (clobber (match_scratch:SI 5 "X"))] | |
0ad91047 | 9115 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9116 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" |
3c67b673 | 9117 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9118 | [(set_attr "type" "load") |
9119 | (set_attr "length" "8")]) | |
7e69e155 | 9120 | |
1fd4e8c1 | 9121 | \f |
7e69e155 | 9122 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
9123 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
9124 | ;; do cases where the increment is not the size of the object. | |
9125 | ;; | |
9126 | ;; In all these cases, we use operands 0 and 1 for the register being | |
9127 | ;; incremented because those are the operands that local-alloc will | |
9128 | ;; tie and these are the pair most likely to be tieable (and the ones | |
9129 | ;; that will benefit the most). | |
9130 | ||
38c1f2d7 | 9131 | (define_insn "*movdi_update1" |
51b8fc2c | 9132 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 9133 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
51b8fc2c RK |
9134 | (match_operand:DI 2 "reg_or_short_operand" "r,I")))) |
9135 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
9136 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9137 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9138 | "@ |
9139 | ldux %3,%0,%2 | |
9140 | ldu %3,%2(%0)" | |
9141 | [(set_attr "type" "load")]) | |
9142 | ||
38c1f2d7 | 9143 | (define_insn "*movdi_update2" |
287f13ff RK |
9144 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") |
9145 | (sign_extend:DI | |
9146 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
9147 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
9148 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
9149 | (plus:DI (match_dup 1) (match_dup 2)))] | |
9150 | "TARGET_POWERPC64" | |
9151 | "lwaux %3,%0,%2" | |
9152 | [(set_attr "type" "load")]) | |
9153 | ||
4697a36c | 9154 | (define_insn "movdi_update" |
51b8fc2c RK |
9155 | [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
9156 | (match_operand:DI 2 "reg_or_short_operand" "r,I"))) | |
9157 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) | |
9158 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") | |
9159 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9160 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9161 | "@ |
9162 | stdux %3,%0,%2 | |
b7ff3d82 DE |
9163 | stdu %3,%2(%0)" |
9164 | [(set_attr "type" "store")]) | |
51b8fc2c | 9165 | |
38c1f2d7 | 9166 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
9167 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
9168 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9169 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9170 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 RK |
9171 | (plus:SI (match_dup 1) (match_dup 2)))] |
9172 | "" | |
9173 | "@ | |
ca7f5001 RK |
9174 | {lux|lwzux} %3,%0,%2 |
9175 | {lu|lwzu} %3,%2(%0)" | |
cfb557c4 | 9176 | [(set_attr "type" "load")]) |
1fd4e8c1 | 9177 | |
4697a36c | 9178 | (define_insn "movsi_update" |
cd2b37d9 | 9179 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9180 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9181 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
9182 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9183 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9184 | "TARGET_UPDATE" |
1fd4e8c1 | 9185 | "@ |
ca7f5001 | 9186 | {stux|stwux} %3,%0,%2 |
b7ff3d82 DE |
9187 | {stu|stwu} %3,%2(%0)" |
9188 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 9189 | |
38c1f2d7 | 9190 | (define_insn "*movhi_update" |
cd2b37d9 RK |
9191 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
9192 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9193 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9194 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9195 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9196 | "TARGET_UPDATE" |
1fd4e8c1 | 9197 | "@ |
5f243543 RK |
9198 | lhzux %3,%0,%2 |
9199 | lhzu %3,%2(%0)" | |
cfb557c4 | 9200 | [(set_attr "type" "load")]) |
1fd4e8c1 | 9201 | |
38c1f2d7 | 9202 | (define_insn "*movhi_update2" |
cd2b37d9 | 9203 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9204 | (zero_extend:SI |
cd2b37d9 | 9205 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9206 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9207 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9208 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9209 | "TARGET_UPDATE" |
1fd4e8c1 | 9210 | "@ |
5f243543 RK |
9211 | lhzux %3,%0,%2 |
9212 | lhzu %3,%2(%0)" | |
cfb557c4 | 9213 | [(set_attr "type" "load")]) |
1fd4e8c1 | 9214 | |
38c1f2d7 | 9215 | (define_insn "*movhi_update3" |
cd2b37d9 | 9216 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9217 | (sign_extend:SI |
cd2b37d9 | 9218 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9219 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9220 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9221 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9222 | "TARGET_UPDATE" |
1fd4e8c1 | 9223 | "@ |
5f243543 RK |
9224 | lhaux %3,%0,%2 |
9225 | lhau %3,%2(%0)" | |
cfb557c4 | 9226 | [(set_attr "type" "load")]) |
1fd4e8c1 | 9227 | |
38c1f2d7 | 9228 | (define_insn "*movhi_update4" |
cd2b37d9 | 9229 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9230 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9231 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
9232 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9233 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9234 | "TARGET_UPDATE" |
1fd4e8c1 | 9235 | "@ |
5f243543 | 9236 | sthux %3,%0,%2 |
b7ff3d82 DE |
9237 | sthu %3,%2(%0)" |
9238 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 9239 | |
38c1f2d7 | 9240 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
9241 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
9242 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9243 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9244 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9245 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9246 | "TARGET_UPDATE" |
1fd4e8c1 | 9247 | "@ |
5f243543 RK |
9248 | lbzux %3,%0,%2 |
9249 | lbzu %3,%2(%0)" | |
cfb557c4 | 9250 | [(set_attr "type" "load")]) |
1fd4e8c1 | 9251 | |
38c1f2d7 | 9252 | (define_insn "*movqi_update2" |
cd2b37d9 | 9253 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9254 | (zero_extend:SI |
cd2b37d9 | 9255 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9256 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9257 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9258 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9259 | "TARGET_UPDATE" |
1fd4e8c1 | 9260 | "@ |
5f243543 RK |
9261 | lbzux %3,%0,%2 |
9262 | lbzu %3,%2(%0)" | |
cfb557c4 | 9263 | [(set_attr "type" "load")]) |
1fd4e8c1 | 9264 | |
38c1f2d7 | 9265 | (define_insn "*movqi_update3" |
cd2b37d9 | 9266 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9267 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9268 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
9269 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9270 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9271 | "TARGET_UPDATE" |
1fd4e8c1 | 9272 | "@ |
5f243543 | 9273 | stbux %3,%0,%2 |
b7ff3d82 DE |
9274 | stbu %3,%2(%0)" |
9275 | [(set_attr "type" "store")]) | |
1fd4e8c1 | 9276 | |
38c1f2d7 | 9277 | (define_insn "*movsf_update1" |
cd2b37d9 | 9278 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 9279 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9280 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9281 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9282 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9283 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 9284 | "@ |
5f243543 RK |
9285 | lfsux %3,%0,%2 |
9286 | lfsu %3,%2(%0)" | |
cfb557c4 | 9287 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 9288 | |
38c1f2d7 | 9289 | (define_insn "*movsf_update2" |
cd2b37d9 | 9290 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9291 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9292 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
9293 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9294 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9295 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 9296 | "@ |
85fff2f3 | 9297 | stfsux %3,%0,%2 |
b7ff3d82 DE |
9298 | stfsu %3,%2(%0)" |
9299 | [(set_attr "type" "fpstore")]) | |
1fd4e8c1 | 9300 | |
38c1f2d7 MM |
9301 | (define_insn "*movsf_update3" |
9302 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
9303 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9304 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
9305 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9306 | (plus:SI (match_dup 1) (match_dup 2)))] | |
9307 | "TARGET_SOFT_FLOAT && TARGET_UPDATE" | |
9308 | "@ | |
9309 | {lux|lwzux} %3,%0,%2 | |
9310 | {lu|lwzu} %3,%2(%0)" | |
9311 | [(set_attr "type" "load")]) | |
9312 | ||
9313 | (define_insn "*movsf_update4" | |
9314 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9315 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
9316 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
9317 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9318 | (plus:SI (match_dup 1) (match_dup 2)))] | |
9319 | "TARGET_SOFT_FLOAT && TARGET_UPDATE" | |
9320 | "@ | |
9321 | {stux|stwux} %3,%0,%2 | |
9322 | {stu|stwu} %3,%2(%0)" | |
9323 | [(set_attr "type" "store")]) | |
9324 | ||
9325 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
9326 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
9327 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9328 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9329 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9330 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9331 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 9332 | "@ |
5f243543 RK |
9333 | lfdux %3,%0,%2 |
9334 | lfdu %3,%2(%0)" | |
cfb557c4 | 9335 | [(set_attr "type" "fpload")]) |
1fd4e8c1 | 9336 | |
38c1f2d7 | 9337 | (define_insn "*movdf_update2" |
cd2b37d9 | 9338 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9339 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9340 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
9341 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9342 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9343 | "TARGET_HARD_FLOAT && TARGET_UPDATE" |
1fd4e8c1 | 9344 | "@ |
5f243543 | 9345 | stfdux %3,%0,%2 |
b7ff3d82 DE |
9346 | stfdu %3,%2(%0)" |
9347 | [(set_attr "type" "fpstore")]) | |
4c70a4f3 RK |
9348 | |
9349 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
9350 | ||
9351 | (define_peephole | |
9352 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
9353 | (match_operand:DF 1 "memory_operand" "")) | |
9354 | (set (match_operand:DF 2 "gpc_reg_operand" "=f") | |
9355 | (match_operand:DF 3 "memory_operand" ""))] | |
9356 | "TARGET_POWER2 | |
d14a6d05 | 9357 | && TARGET_HARD_FLOAT |
4c70a4f3 RK |
9358 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
9359 | && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3]) | |
9360 | && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" | |
9361 | "lfq%U1%X1 %0,%1") | |
9362 | ||
9363 | (define_peephole | |
9364 | [(set (match_operand:DF 0 "memory_operand" "") | |
9365 | (match_operand:DF 1 "gpc_reg_operand" "f")) | |
9366 | (set (match_operand:DF 2 "memory_operand" "") | |
9367 | (match_operand:DF 3 "gpc_reg_operand" "f"))] | |
9368 | "TARGET_POWER2 | |
d14a6d05 | 9369 | && TARGET_HARD_FLOAT |
4c70a4f3 RK |
9370 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
9371 | && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2]) | |
9372 | && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" | |
9373 | "stfq%U0%X0 %1,%0") | |
1fd4e8c1 RK |
9374 | \f |
9375 | ;; Next come insns related to the calling sequence. | |
9376 | ;; | |
9377 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 9378 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
9379 | |
9380 | (define_expand "allocate_stack" | |
52d3af72 | 9381 | [(set (match_operand 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
9382 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) |
9383 | (set (reg 1) | |
9384 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
9385 | "" |
9386 | " | |
4697a36c | 9387 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 9388 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 9389 | rtx neg_op0; |
1fd4e8c1 RK |
9390 | |
9391 | emit_move_insn (chain, stack_bot); | |
4697a36c | 9392 | |
a157febd GK |
9393 | /* Check stack bounds if necessary. */ |
9394 | if (current_function_limit_stack) | |
9395 | { | |
9396 | rtx available; | |
9397 | available = expand_binop (Pmode, sub_optab, | |
9398 | stack_pointer_rtx, stack_limit_rtx, | |
9399 | NULL_RTX, 1, OPTAB_WIDEN); | |
9400 | emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); | |
9401 | } | |
9402 | ||
e9a25f70 JL |
9403 | if (GET_CODE (operands[1]) != CONST_INT |
9404 | || INTVAL (operands[1]) < -32767 | |
9405 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
9406 | { |
9407 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 9408 | if (TARGET_32BIT) |
e9a25f70 | 9409 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 9410 | else |
e9a25f70 | 9411 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
9412 | } |
9413 | else | |
e9a25f70 | 9414 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 9415 | |
38c1f2d7 MM |
9416 | if (TARGET_UPDATE) |
9417 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update)) | |
9418 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); | |
4697a36c | 9419 | |
38c1f2d7 MM |
9420 | else |
9421 | { | |
9422 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
9423 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 9424 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 9425 | } |
e9a25f70 JL |
9426 | |
9427 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
9428 | DONE; |
9429 | }") | |
59257ff7 RK |
9430 | |
9431 | ;; These patterns say how to save and restore the stack pointer. We need not | |
9432 | ;; save the stack pointer at function level since we are careful to | |
9433 | ;; preserve the backchain. At block level, we have to restore the backchain | |
9434 | ;; when we restore the stack pointer. | |
9435 | ;; | |
9436 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
9437 | ;; backchain and restore both. Note that in the nonlocal case, the | |
9438 | ;; save area is a memory location. | |
9439 | ||
9440 | (define_expand "save_stack_function" | |
ff381587 MM |
9441 | [(match_operand 0 "any_operand" "") |
9442 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9443 | "" |
ff381587 | 9444 | "DONE;") |
59257ff7 RK |
9445 | |
9446 | (define_expand "restore_stack_function" | |
ff381587 MM |
9447 | [(match_operand 0 "any_operand" "") |
9448 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9449 | "" |
ff381587 | 9450 | "DONE;") |
59257ff7 RK |
9451 | |
9452 | (define_expand "restore_stack_block" | |
dfdfa60f DE |
9453 | [(use (match_operand 0 "register_operand" "")) |
9454 | (set (match_dup 2) (match_dup 3)) | |
a260abc9 | 9455 | (set (match_dup 0) (match_operand 1 "register_operand" "")) |
dfdfa60f | 9456 | (set (match_dup 3) (match_dup 2))] |
59257ff7 RK |
9457 | "" |
9458 | " | |
dfdfa60f DE |
9459 | { |
9460 | operands[2] = gen_reg_rtx (Pmode); | |
39403d82 | 9461 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); |
dfdfa60f | 9462 | }") |
59257ff7 RK |
9463 | |
9464 | (define_expand "save_stack_nonlocal" | |
a260abc9 DE |
9465 | [(match_operand 0 "memory_operand" "") |
9466 | (match_operand 1 "register_operand" "")] | |
59257ff7 RK |
9467 | "" |
9468 | " | |
9469 | { | |
a260abc9 | 9470 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
9471 | |
9472 | /* Copy the backchain to the first word, sp to the second. */ | |
39403d82 | 9473 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
c5c76735 JL |
9474 | emit_move_insn (operand_subword (operands[0], 0, 0, |
9475 | (TARGET_32BIT ? DImode : TImode)), | |
a260abc9 DE |
9476 | temp); |
9477 | emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)), | |
9478 | operands[1]); | |
59257ff7 RK |
9479 | DONE; |
9480 | }") | |
7e69e155 | 9481 | |
59257ff7 | 9482 | (define_expand "restore_stack_nonlocal" |
a260abc9 DE |
9483 | [(match_operand 0 "register_operand" "") |
9484 | (match_operand 1 "memory_operand" "")] | |
59257ff7 RK |
9485 | "" |
9486 | " | |
9487 | { | |
a260abc9 | 9488 | rtx temp = gen_reg_rtx (Pmode); |
59257ff7 RK |
9489 | |
9490 | /* Restore the backchain from the first word, sp from the second. */ | |
a260abc9 DE |
9491 | emit_move_insn (temp, |
9492 | operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode))); | |
9493 | emit_move_insn (operands[0], | |
c5c76735 JL |
9494 | operand_subword (operands[1], 1, 0, |
9495 | (TARGET_32BIT ? DImode : TImode))); | |
39403d82 | 9496 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
59257ff7 RK |
9497 | DONE; |
9498 | }") | |
9ebbca7d GK |
9499 | \f |
9500 | ;; TOC register handling. | |
b6c9286a | 9501 | |
9ebbca7d | 9502 | ;; Code to initialize the TOC register... |
f0f6a223 | 9503 | |
9ebbca7d GK |
9504 | (define_insn "load_toc_aix_si" |
9505 | [(set (match_operand:SI 0 "register_operand" "=r") | |
9506 | (unspec:SI [(const_int 0)] 7))] | |
9507 | "! TARGET_ELF && TARGET_32BIT" | |
f0f6a223 RK |
9508 | "* |
9509 | { | |
9ebbca7d GK |
9510 | char buf[30]; |
9511 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
9512 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (buf, -1)); | |
9513 | operands[2] = gen_rtx_REG (Pmode, 2); | |
9514 | return \"{l|lwz} %0,%1(%2)\"; | |
f0f6a223 RK |
9515 | }" |
9516 | [(set_attr "type" "load")]) | |
9ebbca7d GK |
9517 | |
9518 | (define_insn "load_toc_aix_di" | |
9519 | [(set (match_operand:DI 0 "register_operand" "=r") | |
9520 | (unspec:DI [(const_int 0)] 7))] | |
9521 | "! TARGET_ELF && TARGET_64BIT" | |
9522 | "* | |
9523 | { | |
9524 | char buf[30]; | |
9525 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
9526 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (buf, -1)); | |
9527 | operands[2] = gen_rtx_REG (Pmode, 2); | |
9528 | return \"ld %0,%1(%2)\"; | |
9529 | }" | |
9530 | [(set_attr "type" "load")]) | |
9531 | ||
9532 | (define_insn "load_toc_v4_pic_si" | |
9533 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9534 | (unspec:SI [(const_int 0)] 7))] | |
9535 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1 | |
9536 | && TARGET_32BIT" | |
9537 | "bl _GLOBAL_OFFSET_TABLE_@local-4" | |
9538 | [(set_attr "type" "branch") | |
9539 | (set_attr "length" "4")]) | |
9540 | ||
9541 | (define_insn "load_toc_v4_pic_di" | |
9542 | [(set (match_operand:DI 0 "register_operand" "=l") | |
9543 | (unspec:DI [(const_int 0)] 7))] | |
9544 | "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1 | |
9545 | && TARGET_64BIT" | |
9546 | "bl _GLOBAL_OFFSET_TABLE_@local-4" | |
9547 | [(set_attr "type" "branch") | |
9548 | (set_attr "length" "4")]) | |
9549 | ||
9550 | (define_insn "load_toc_v4_PIC_1" | |
9551 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9552 | (match_operand:SI 1 "immediate_operand" "s")) | |
9553 | (unspec [(match_dup 1)] 7)] | |
9554 | "TARGET_ELF && flag_pic == 2" | |
9555 | "bl %1\\n%1:" | |
9556 | [(set_attr "type" "branch") | |
9557 | (set_attr "length" "4")]) | |
9558 | ||
9559 | (define_insn "load_toc_v4_PIC_1b" | |
9560 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9561 | (match_operand:SI 1 "immediate_operand" "s")) | |
9562 | (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)] | |
9563 | "TARGET_ELF && flag_pic == 2" | |
9564 | "bl %1\\n\\t.long %2-%1+4\\n%1:" | |
9565 | [(set_attr "type" "branch") | |
9566 | (set_attr "length" "8")]) | |
9567 | ||
9568 | (define_insn "load_toc_v4_PIC_2" | |
9569 | [(set (match_operand:SI 0 "register_operand" "=r") | |
9570 | (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r") | |
9571 | (minus:SI (match_operand:SI 2 "immediate_operand" "s") | |
9572 | (match_operand:SI 3 "immediate_operand" "s")))))] | |
9573 | "TARGET_ELF && flag_pic == 2" | |
9574 | "{l|lwz} %0,%2-%3(%1)" | |
9575 | [(set_attr "type" "load")]) | |
9576 | ||
9577 | ;; If the TOC is shared over a translation unit, as happens with all | |
9578 | ;; the kinds of PIC that we support, we need to restore the TOC | |
9579 | ;; pointer only when jumping over units of translation. | |
9580 | ||
9581 | (define_expand "builtin_setjmp_receiver" | |
9582 | [(use (label_ref (match_operand 0 "" "")))] | |
9583 | "((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1) | |
9584 | || (TARGET_TOC && TARGET_MINIMAL_TOC)" | |
9585 | " | |
9586 | { | |
9587 | rs6000_emit_load_toc_table (FALSE); | |
9588 | DONE; | |
9589 | }") | |
9590 | \f | |
9591 | ;; A function pointer under AIX is a pointer to a data area whose first word | |
9592 | ;; contains the actual address of the function, whose second word contains a | |
b6c9286a MM |
9593 | ;; pointer to its TOC, and whose third word contains a value to place in the |
9594 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 RK |
9595 | ;; "trampoline" need not have any executable code. |
9596 | ;; | |
b6c9286a MM |
9597 | ;; operands[0] is a register pointing to the 3 word descriptor (aka, the function address) |
9598 | ;; operands[1] is the stack size to clean up | |
9599 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for AIX) | |
9600 | ;; operands[3] is location to store the TOC | |
9601 | ;; operands[4] is the TOC register | |
9602 | ;; operands[5] is the static chain register | |
9603 | ;; | |
9604 | ;; We do not break this into separate insns, so that the scheduler will not try | |
9605 | ;; to move the load of the new TOC before any loads from the TOC. | |
9606 | ||
a260abc9 | 9607 | (define_insn "call_indirect_aix32" |
52d3af72 | 9608 | [(call (mem:SI (match_operand:SI 0 "gpc_reg_operand" "b")) |
b6c9286a | 9609 | (match_operand 1 "const_int_operand" "n")) |
6a4cee5f | 9610 | (use (match_operand 2 "const_int_operand" "n")) |
97f6e72f | 9611 | (use (match_operand 3 "offsettable_mem_operand" "o")) |
52d3af72 DE |
9612 | (use (match_operand 4 "gpc_reg_operand" "r")) |
9613 | (clobber (match_operand 5 "gpc_reg_operand" "=r")) | |
b6c9286a MM |
9614 | (clobber (match_scratch:SI 6 "=&r")) |
9615 | (clobber (match_scratch:SI 7 "=l"))] | |
6a4cee5f MM |
9616 | "DEFAULT_ABI == ABI_AIX |
9617 | && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)" | |
97f6e72f | 9618 | "{st|stw} %4,%3\;{l|lwz} %6,0(%0)\;{l|lwz} %4,4(%0)\;mt%7 %6\;{l|lwz} %5,8(%0)\;{brl|blrl}\;{l|lwz} %4,%3" |
b7ff3d82 DE |
9619 | [(set_attr "type" "load") |
9620 | (set_attr "length" "28")]) | |
b6c9286a | 9621 | |
a260abc9 | 9622 | (define_insn "call_indirect_aix64" |
52d3af72 | 9623 | [(call (mem:SI (match_operand:DI 0 "gpc_reg_operand" "b")) |
a260abc9 DE |
9624 | (match_operand 1 "const_int_operand" "n")) |
9625 | (use (match_operand 2 "const_int_operand" "n")) | |
97f6e72f | 9626 | (use (match_operand 3 "offsettable_mem_operand" "o")) |
52d3af72 DE |
9627 | (use (match_operand 4 "gpc_reg_operand" "r")) |
9628 | (clobber (match_operand 5 "gpc_reg_operand" "=r")) | |
a260abc9 DE |
9629 | (clobber (match_scratch:SI 6 "=&r")) |
9630 | (clobber (match_scratch:SI 7 "=l"))] | |
9631 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX | |
9632 | && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)" | |
97f6e72f | 9633 | "std %4,%3\;ld %6,0(%0)\;ld %4,8(%0)\;mt%7 %6\;ld %5,16(%0)\;blrl\;ld %4,%3" |
a260abc9 DE |
9634 | [(set_attr "type" "load") |
9635 | (set_attr "length" "28")]) | |
9636 | ||
9637 | (define_insn "call_value_indirect_aix32" | |
2d1086d8 | 9638 | [(set (match_operand 0 "" "") |
52d3af72 | 9639 | (call (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
b6c9286a | 9640 | (match_operand 2 "const_int_operand" "n"))) |
6a4cee5f | 9641 | (use (match_operand 3 "const_int_operand" "n")) |
97f6e72f | 9642 | (use (match_operand 4 "offsettable_mem_operand" "o")) |
52d3af72 DE |
9643 | (use (match_operand 5 "gpc_reg_operand" "r")) |
9644 | (clobber (match_operand 6 "gpc_reg_operand" "=r")) | |
b6c9286a MM |
9645 | (clobber (match_scratch:SI 7 "=&r")) |
9646 | (clobber (match_scratch:SI 8 "=l"))] | |
6a4cee5f MM |
9647 | "DEFAULT_ABI == ABI_AIX |
9648 | && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)" | |
97f6e72f | 9649 | "{st|stw} %5,%4\;{l|lwz} %7,0(%1)\;{l|lwz} %5,4(%1)\;mt%8 %7\;{l|lwz} %6,8(%1)\;{brl|blrl}\;{l|lwz} %5,%4" |
a260abc9 DE |
9650 | [(set_attr "type" "load") |
9651 | (set_attr "length" "28")]) | |
9652 | ||
9653 | (define_insn "call_value_indirect_aix64" | |
2d1086d8 | 9654 | [(set (match_operand 0 "" "") |
52d3af72 | 9655 | (call (mem:SI (match_operand:DI 1 "gpc_reg_operand" "b")) |
a260abc9 DE |
9656 | (match_operand 2 "const_int_operand" "n"))) |
9657 | (use (match_operand 3 "const_int_operand" "n")) | |
97f6e72f | 9658 | (use (match_operand 4 "offsettable_mem_operand" "o")) |
52d3af72 DE |
9659 | (use (match_operand 5 "gpc_reg_operand" "r")) |
9660 | (clobber (match_operand 6 "gpc_reg_operand" "=r")) | |
a260abc9 DE |
9661 | (clobber (match_scratch:SI 7 "=&r")) |
9662 | (clobber (match_scratch:SI 8 "=l"))] | |
9663 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX | |
9664 | && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)" | |
97f6e72f | 9665 | "std %5,%4\;ld %7,0(%1)\;ld %5,8(%1)\;mt%8 %7\;ld %6,16(%1)\;blrl\;ld %5,%4" |
b7ff3d82 DE |
9666 | [(set_attr "type" "load") |
9667 | (set_attr "length" "28")]) | |
b6c9286a | 9668 | |
b6c9286a MM |
9669 | ;; A function pointer under System V is just a normal pointer |
9670 | ;; operands[0] is the function pointer | |
9671 | ;; operands[1] is the stack size to clean up | |
9672 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument which indicates how to set cr1 | |
9673 | ||
9674 | (define_insn "call_indirect_sysv" | |
9675 | [(call (mem:SI (match_operand:SI 0 "register_operand" "l,l")) | |
9676 | (match_operand 1 "const_int_operand" "n,n")) | |
9677 | (use (match_operand 2 "const_int_operand" "O,n")) | |
9678 | (clobber (match_scratch:SI 3 "=l,l"))] | |
c81bebd7 | 9679 | "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC" |
b6c9286a MM |
9680 | "* |
9681 | { | |
6a4cee5f MM |
9682 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
9683 | output_asm_insn (\"crxor 6,6,6\", operands); | |
1fd4e8c1 | 9684 | |
6a4cee5f MM |
9685 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
9686 | output_asm_insn (\"creqv 6,6,6\", operands); | |
b6c9286a MM |
9687 | |
9688 | return \"{brl|blrl}\"; | |
9689 | }" | |
b7ff3d82 DE |
9690 | [(set_attr "type" "jmpreg") |
9691 | (set_attr "length" "4,8")]) | |
b6c9286a MM |
9692 | |
9693 | (define_insn "call_value_indirect_sysv" | |
9694 | [(set (match_operand 0 "register_operand" "=fg,fg") | |
9695 | (call (mem:SI (match_operand:SI 1 "register_operand" "l,l")) | |
9696 | (match_operand 2 "const_int_operand" "n,n"))) | |
9697 | (use (match_operand 3 "const_int_operand" "O,n")) | |
9698 | (clobber (match_scratch:SI 4 "=l,l"))] | |
c81bebd7 | 9699 | "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC" |
b6c9286a MM |
9700 | "* |
9701 | { | |
6a4cee5f MM |
9702 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
9703 | output_asm_insn (\"crxor 6,6,6\", operands); | |
b6c9286a | 9704 | |
6a4cee5f MM |
9705 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) |
9706 | output_asm_insn (\"creqv 6,6,6\", operands); | |
b6c9286a MM |
9707 | |
9708 | return \"{brl|blrl}\"; | |
9709 | }" | |
b7ff3d82 DE |
9710 | [(set_attr "type" "jmpreg") |
9711 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 9712 | |
b6c9286a | 9713 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 9714 | (define_expand "call" |
a260abc9 | 9715 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 9716 | (match_operand 1 "" "")) |
4697a36c | 9717 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
9718 | (clobber (scratch:SI))])] |
9719 | "" | |
9720 | " | |
9721 | { | |
9722 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) | |
9723 | abort (); | |
9724 | ||
9725 | operands[0] = XEXP (operands[0], 0); | |
7509c759 | 9726 | |
6a4cee5f MM |
9727 | if (GET_CODE (operands[0]) != SYMBOL_REF |
9728 | || (INTVAL (operands[2]) & CALL_LONG) != 0) | |
1fd4e8c1 | 9729 | { |
6a4cee5f MM |
9730 | if (INTVAL (operands[2]) & CALL_LONG) |
9731 | operands[0] = rs6000_longcall_ref (operands[0]); | |
9732 | ||
c81bebd7 | 9733 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS) |
b6c9286a MM |
9734 | emit_call_insn (gen_call_indirect_sysv (force_reg (Pmode, operands[0]), |
9735 | operands[1], operands[2])); | |
9736 | else | |
9737 | { | |
39403d82 | 9738 | rtx toc_reg = gen_rtx_REG (Pmode, 2); |
b6c9286a | 9739 | rtx toc_addr = RS6000_SAVE_TOC; |
1fd4e8c1 | 9740 | |
b6c9286a MM |
9741 | if (DEFAULT_ABI == ABI_AIX) |
9742 | { | |
c5c76735 JL |
9743 | /* AIX function pointers are really pointers to a three word |
9744 | area. */ | |
39403d82 | 9745 | rtx static_chain = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); |
a260abc9 DE |
9746 | emit_call_insn (TARGET_32BIT |
9747 | ? gen_call_indirect_aix32 (force_reg (Pmode, operands[0]), | |
9748 | operands[1], operands[2], | |
9749 | toc_addr, toc_reg, static_chain) | |
9750 | : gen_call_indirect_aix64 (force_reg (Pmode, operands[0]), | |
9751 | operands[1], operands[2], | |
9752 | toc_addr, toc_reg, static_chain)); | |
b6c9286a | 9753 | } |
b6c9286a MM |
9754 | else |
9755 | abort (); | |
9756 | } | |
9757 | DONE; | |
1fd4e8c1 RK |
9758 | } |
9759 | }") | |
9760 | ||
9761 | (define_expand "call_value" | |
9762 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 9763 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 9764 | (match_operand 2 "" ""))) |
4697a36c | 9765 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
9766 | (clobber (scratch:SI))])] |
9767 | "" | |
9768 | " | |
9769 | { | |
9770 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) | |
9771 | abort (); | |
9772 | ||
9773 | operands[1] = XEXP (operands[1], 0); | |
7509c759 | 9774 | |
6a4cee5f MM |
9775 | if (GET_CODE (operands[1]) != SYMBOL_REF |
9776 | || (INTVAL (operands[3]) & CALL_LONG) != 0) | |
1fd4e8c1 | 9777 | { |
6756293c | 9778 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
9779 | operands[1] = rs6000_longcall_ref (operands[1]); |
9780 | ||
c81bebd7 | 9781 | if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS) |
b6c9286a MM |
9782 | emit_call_insn (gen_call_value_indirect_sysv (operands[0], operands[1], |
9783 | operands[2], operands[3])); | |
9784 | else | |
9785 | { | |
39403d82 | 9786 | rtx toc_reg = gen_rtx_REG (Pmode, 2); |
b6c9286a | 9787 | rtx toc_addr = RS6000_SAVE_TOC; |
1fd4e8c1 | 9788 | |
b6c9286a MM |
9789 | if (DEFAULT_ABI == ABI_AIX) |
9790 | { | |
c5c76735 JL |
9791 | /* AIX function pointers are really pointers to a three word |
9792 | area. */ | |
39403d82 | 9793 | rtx static_chain = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); |
a260abc9 DE |
9794 | emit_call_insn (TARGET_32BIT |
9795 | ? gen_call_value_indirect_aix32 (operands[0], | |
9796 | force_reg (Pmode, operands[1]), | |
9797 | operands[2], operands[3], | |
9798 | toc_addr, toc_reg, static_chain) | |
9799 | : gen_call_value_indirect_aix64 (operands[0], | |
9800 | force_reg (Pmode, operands[1]), | |
9801 | operands[2], operands[3], | |
9802 | toc_addr, toc_reg, static_chain)); | |
b6c9286a | 9803 | } |
b6c9286a MM |
9804 | else |
9805 | abort (); | |
9806 | } | |
9807 | DONE; | |
1fd4e8c1 RK |
9808 | } |
9809 | }") | |
9810 | ||
04780ee7 | 9811 | ;; Call to function in current module. No TOC pointer reload needed. |
4697a36c MM |
9812 | ;; Operand2 is non-zero if we are using the V.4 calling sequence and |
9813 | ;; either the function was not prototyped, or it was prototyped as a | |
9814 | ;; variable argument function. It is > 0 if FP registers were passed | |
9815 | ;; and < 0 if they were not. | |
04780ee7 | 9816 | |
a260abc9 | 9817 | (define_insn "*call_local32" |
4697a36c MM |
9818 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
9819 | (match_operand 1 "" "g,g")) | |
9820 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
9821 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 9822 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
9823 | "* |
9824 | { | |
6a4cee5f MM |
9825 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
9826 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9827 | ||
9828 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
9829 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 9830 | |
a226df46 | 9831 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 9832 | }" |
b7ff3d82 DE |
9833 | [(set_attr "type" "branch") |
9834 | (set_attr "length" "4,8")]) | |
04780ee7 | 9835 | |
a260abc9 DE |
9836 | (define_insn "*call_local64" |
9837 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
9838 | (match_operand 1 "" "g,g")) | |
9839 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
9840 | (clobber (match_scratch:SI 3 "=l,l"))] | |
9841 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
9842 | "* | |
9843 | { | |
9844 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
9845 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9846 | ||
9847 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
9848 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9849 | ||
9850 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
9851 | }" | |
9852 | [(set_attr "type" "branch") | |
9853 | (set_attr "length" "4,8")]) | |
9854 | ||
9855 | (define_insn "*ret_call_local32" | |
9856 | [(set (match_operand 0 "" "=fg,fg") | |
9857 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) | |
9858 | (match_operand 2 "" "g,g"))) | |
9859 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
9860 | (clobber (match_scratch:SI 4 "=l,l"))] | |
9861 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
9862 | "* | |
9863 | { | |
9864 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
9865 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9866 | ||
9867 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9868 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9869 | ||
9870 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
9871 | }" | |
9872 | [(set_attr "type" "branch") | |
9873 | (set_attr "length" "4,8")]) | |
9874 | ||
9875 | ||
9876 | (define_insn "*ret_call_local64" | |
9877 | [(set (match_operand 0 "" "=fg,fg") | |
9878 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) | |
9879 | (match_operand 2 "" "g,g"))) | |
9880 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
9881 | (clobber (match_scratch:SI 4 "=l,l"))] | |
9882 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
9883 | "* | |
9884 | { | |
9885 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
9886 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9887 | ||
9888 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9889 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9890 | ||
9891 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
9892 | }" | |
9893 | [(set_attr "type" "branch") | |
9894 | (set_attr "length" "4,8")]) | |
9895 | ||
04780ee7 | 9896 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 9897 | ;; pointer (r2) after the call unless this is System V. |
4697a36c MM |
9898 | ;; Operand2 is non-zero if we are using the V.4 calling sequence and |
9899 | ;; either the function was not prototyped, or it was prototyped as a | |
9900 | ;; variable argument function. It is > 0 if FP registers were passed | |
9901 | ;; and < 0 if they were not. | |
04780ee7 | 9902 | |
a260abc9 | 9903 | (define_insn "*call_nonlocal_aix32" |
b6c9286a MM |
9904 | [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s")) |
9905 | (match_operand 1 "" "fg,fg")) | |
9906 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
9907 | (clobber (match_scratch:SI 3 "=l,l"))] | |
9ebbca7d | 9908 | "DEFAULT_ABI == ABI_AIX |
5a19791c | 9909 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
911f679c MM |
9910 | "* |
9911 | { | |
b6c9286a | 9912 | /* Indirect calls should go through call_indirect */ |
0f07e76c | 9913 | if (GET_CODE (operands[0]) == REG) |
b6c9286a | 9914 | abort (); |
911f679c | 9915 | |
6a4cee5f MM |
9916 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
9917 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9918 | ||
9919 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
9920 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 9921 | |
9ebbca7d | 9922 | return \"bl %z0\;%.\"; |
b6c9286a | 9923 | }" |
b7ff3d82 DE |
9924 | [(set_attr "type" "branch") |
9925 | (set_attr "length" "8,12")]) | |
59313e4e | 9926 | |
a260abc9 DE |
9927 | (define_insn "*call_nonlocal_aix64" |
9928 | [(call (mem:SI (match_operand:DI 0 "call_operand" "s,s")) | |
9929 | (match_operand 1 "" "fg,fg")) | |
9930 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
9931 | (clobber (match_scratch:SI 3 "=l,l"))] | |
9ebbca7d GK |
9932 | "TARGET_64BIT |
9933 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 DE |
9934 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
9935 | "* | |
9936 | { | |
9937 | /* Indirect calls should go through call_indirect */ | |
9938 | if (GET_CODE (operands[0]) == REG) | |
9939 | abort (); | |
9940 | ||
9941 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
9942 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9943 | ||
9944 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
9945 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9946 | ||
9ebbca7d | 9947 | return \"bl %z0\;%.\"; |
a260abc9 DE |
9948 | }" |
9949 | [(set_attr "type" "branch") | |
9950 | (set_attr "length" "8,12")]) | |
9951 | ||
9952 | (define_insn "*call_nonlocal_sysv" | |
b6c9286a MM |
9953 | [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s")) |
9954 | (match_operand 1 "" "fg,fg")) | |
9955 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
9956 | (clobber (match_scratch:SI 3 "=l,l"))] | |
c81bebd7 | 9957 | "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
5a19791c | 9958 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
b6c9286a MM |
9959 | "* |
9960 | { | |
b6c9286a | 9961 | /* Indirect calls should go through call_indirect */ |
0f07e76c | 9962 | if (GET_CODE (operands[0]) == REG) |
b6c9286a | 9963 | abort (); |
59313e4e | 9964 | |
6a4cee5f MM |
9965 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
9966 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9967 | ||
9968 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
9969 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 9970 | |
a226df46 | 9971 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@plt\" : \"bl %z0\"; |
911f679c | 9972 | }" |
b7ff3d82 DE |
9973 | [(set_attr "type" "branch") |
9974 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 9975 | |
a260abc9 | 9976 | (define_insn "*ret_call_nonlocal_aix32" |
4697a36c | 9977 | [(set (match_operand 0 "" "=fg,fg") |
a260abc9 DE |
9978 | (call (mem:SI (match_operand:SI 1 "call_operand" "s,s")) |
9979 | (match_operand 2 "" "fg,fg"))) | |
4697a36c MM |
9980 | (use (match_operand:SI 3 "immediate_operand" "O,n")) |
9981 | (clobber (match_scratch:SI 4 "=l,l"))] | |
9ebbca7d | 9982 | "DEFAULT_ABI == ABI_AIX |
a260abc9 | 9983 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
4697a36c MM |
9984 | "* |
9985 | { | |
a260abc9 DE |
9986 | /* This should be handled by call_value_indirect */ |
9987 | if (GET_CODE (operands[1]) == REG) | |
9988 | abort (); | |
9989 | ||
6a4cee5f MM |
9990 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
9991 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9992 | ||
9993 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9994 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 9995 | |
9ebbca7d | 9996 | return \"bl %z1\;%.\"; |
4697a36c | 9997 | }" |
b7ff3d82 | 9998 | [(set_attr "type" "branch") |
a260abc9 | 9999 | (set_attr "length" "8,12")]) |
04780ee7 | 10000 | |
a260abc9 | 10001 | (define_insn "*ret_call_nonlocal_aix64" |
b6c9286a | 10002 | [(set (match_operand 0 "" "=fg,fg") |
a260abc9 | 10003 | (call (mem:SI (match_operand:DI 1 "call_operand" "s,s")) |
b6c9286a MM |
10004 | (match_operand 2 "" "fg,fg"))) |
10005 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10006 | (clobber (match_scratch:SI 4 "=l,l"))] | |
9ebbca7d GK |
10007 | "TARGET_64BIT |
10008 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 10009 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
911f679c MM |
10010 | "* |
10011 | { | |
b6c9286a | 10012 | /* This should be handled by call_value_indirect */ |
59313e4e | 10013 | if (GET_CODE (operands[1]) == REG) |
b6c9286a MM |
10014 | abort (); |
10015 | ||
6a4cee5f MM |
10016 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
10017 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10018 | ||
10019 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10020 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 10021 | |
9ebbca7d | 10022 | return \"bl %z1\;%.\"; |
b6c9286a | 10023 | }" |
b7ff3d82 DE |
10024 | [(set_attr "type" "branch") |
10025 | (set_attr "length" "8,12")]) | |
b6c9286a | 10026 | |
a260abc9 | 10027 | (define_insn "*ret_call_nonlocal_sysv" |
b6c9286a MM |
10028 | [(set (match_operand 0 "" "=fg,fg") |
10029 | (call (mem:SI (match_operand:SI 1 "call_operand" "s,s")) | |
10030 | (match_operand 2 "" "fg,fg"))) | |
10031 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10032 | (clobber (match_scratch:SI 4 "=l,l"))] | |
c81bebd7 | 10033 | "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) |
5a19791c | 10034 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
b6c9286a MM |
10035 | "* |
10036 | { | |
b6c9286a | 10037 | /* This should be handled by call_value_indirect */ |
59313e4e | 10038 | if (GET_CODE (operands[1]) == REG) |
b6c9286a | 10039 | abort (); |
59313e4e | 10040 | |
6a4cee5f MM |
10041 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
10042 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10043 | ||
10044 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10045 | output_asm_insn (\"creqv 6,6,6\", operands); | |
7509c759 | 10046 | |
a226df46 | 10047 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@plt\" : \"bl %z1\"; |
911f679c | 10048 | }" |
b7ff3d82 DE |
10049 | [(set_attr "type" "branch") |
10050 | (set_attr "length" "4,8")]) | |
e6f948e3 RK |
10051 | |
10052 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
10053 | (define_expand "untyped_call" |
10054 | [(parallel [(call (match_operand 0 "" "") | |
10055 | (const_int 0)) | |
10056 | (match_operand 1 "" "") | |
10057 | (match_operand 2 "" "")])] | |
10058 | "" | |
10059 | " | |
10060 | { | |
10061 | int i; | |
10062 | ||
4697a36c | 10063 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
10064 | |
10065 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
10066 | { | |
10067 | rtx set = XVECEXP (operands[2], 0, i); | |
10068 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
10069 | } | |
10070 | ||
10071 | /* The optimizer does not know that the call sets the function value | |
10072 | registers we stored in the result block. We avoid problems by | |
10073 | claiming that all hard registers are used and clobbered at this | |
10074 | point. */ | |
10075 | emit_insn (gen_blockage ()); | |
10076 | ||
10077 | DONE; | |
10078 | }") | |
10079 | ||
10080 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
10081 | ;; all of memory. This blocks insns from being moved across this point. | |
10082 | ||
10083 | (define_insn "blockage" | |
10084 | [(unspec_volatile [(const_int 0)] 0)] | |
10085 | "" | |
10086 | "") | |
1fd4e8c1 RK |
10087 | \f |
10088 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 10089 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
10090 | ;; |
10091 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
10092 | ;; insns, and branches. We store the operands of compares until we see | |
10093 | ;; how it is used. | |
10094 | (define_expand "cmpsi" | |
10095 | [(set (cc0) | |
cd2b37d9 | 10096 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10097 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
10098 | "" | |
10099 | " | |
10100 | { | |
10101 | /* Take care of the possibility that operands[1] might be negative but | |
10102 | this might be a logical operation. That insn doesn't exist. */ | |
10103 | if (GET_CODE (operands[1]) == CONST_INT | |
10104 | && INTVAL (operands[1]) < 0) | |
10105 | operands[1] = force_reg (SImode, operands[1]); | |
10106 | ||
10107 | rs6000_compare_op0 = operands[0]; | |
10108 | rs6000_compare_op1 = operands[1]; | |
10109 | rs6000_compare_fp_p = 0; | |
10110 | DONE; | |
10111 | }") | |
10112 | ||
266eb58a DE |
10113 | (define_expand "cmpdi" |
10114 | [(set (cc0) | |
10115 | (compare (match_operand:DI 0 "gpc_reg_operand" "") | |
10116 | (match_operand:DI 1 "reg_or_short_operand" "")))] | |
10117 | "TARGET_POWERPC64" | |
10118 | " | |
10119 | { | |
10120 | /* Take care of the possibility that operands[1] might be negative but | |
10121 | this might be a logical operation. That insn doesn't exist. */ | |
10122 | if (GET_CODE (operands[1]) == CONST_INT | |
10123 | && INTVAL (operands[1]) < 0) | |
10124 | operands[1] = force_reg (DImode, operands[1]); | |
10125 | ||
10126 | rs6000_compare_op0 = operands[0]; | |
10127 | rs6000_compare_op1 = operands[1]; | |
10128 | rs6000_compare_fp_p = 0; | |
10129 | DONE; | |
10130 | }") | |
10131 | ||
1fd4e8c1 | 10132 | (define_expand "cmpsf" |
cd2b37d9 RK |
10133 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
10134 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 10135 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10136 | " |
10137 | { | |
10138 | rs6000_compare_op0 = operands[0]; | |
10139 | rs6000_compare_op1 = operands[1]; | |
10140 | rs6000_compare_fp_p = 1; | |
10141 | DONE; | |
10142 | }") | |
10143 | ||
10144 | (define_expand "cmpdf" | |
cd2b37d9 RK |
10145 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
10146 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 10147 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10148 | " |
10149 | { | |
10150 | rs6000_compare_op0 = operands[0]; | |
10151 | rs6000_compare_op1 = operands[1]; | |
10152 | rs6000_compare_fp_p = 1; | |
10153 | DONE; | |
10154 | }") | |
10155 | ||
10156 | (define_expand "beq" | |
10157 | [(set (match_dup 2) (match_dup 1)) | |
10158 | (set (pc) | |
10159 | (if_then_else (eq (match_dup 2) | |
10160 | (const_int 0)) | |
10161 | (label_ref (match_operand 0 "" "")) | |
10162 | (pc)))] | |
10163 | "" | |
10164 | " | |
10165 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 10166 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 10167 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
10168 | operands[2] = gen_reg_rtx (mode); |
10169 | }") | |
10170 | ||
10171 | (define_expand "bne" | |
10172 | [(set (match_dup 2) (match_dup 1)) | |
10173 | (set (pc) | |
10174 | (if_then_else (ne (match_dup 2) | |
10175 | (const_int 0)) | |
10176 | (label_ref (match_operand 0 "" "")) | |
10177 | (pc)))] | |
10178 | "" | |
10179 | " | |
10180 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 10181 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 10182 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
10183 | operands[2] = gen_reg_rtx (mode); |
10184 | }") | |
10185 | ||
10186 | (define_expand "blt" | |
10187 | [(set (match_dup 2) (match_dup 1)) | |
10188 | (set (pc) | |
10189 | (if_then_else (lt (match_dup 2) | |
10190 | (const_int 0)) | |
10191 | (label_ref (match_operand 0 "" "")) | |
10192 | (pc)))] | |
10193 | "" | |
10194 | " | |
10195 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 10196 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 10197 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
10198 | operands[2] = gen_reg_rtx (mode); |
10199 | }") | |
10200 | ||
10201 | (define_expand "bgt" | |
10202 | [(set (match_dup 2) (match_dup 1)) | |
10203 | (set (pc) | |
10204 | (if_then_else (gt (match_dup 2) | |
10205 | (const_int 0)) | |
10206 | (label_ref (match_operand 0 "" "")) | |
10207 | (pc)))] | |
10208 | "" | |
10209 | " | |
10210 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 10211 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 10212 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
10213 | operands[2] = gen_reg_rtx (mode); |
10214 | }") | |
10215 | ||
10216 | (define_expand "ble" | |
10217 | [(set (match_dup 2) (match_dup 1)) | |
10218 | (set (pc) | |
10219 | (if_then_else (le (match_dup 2) | |
10220 | (const_int 0)) | |
10221 | (label_ref (match_operand 0 "" "")) | |
10222 | (pc)))] | |
10223 | "" | |
10224 | " | |
10225 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 10226 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 10227 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
10228 | operands[2] = gen_reg_rtx (mode); |
10229 | }") | |
10230 | ||
10231 | (define_expand "bge" | |
10232 | [(set (match_dup 2) (match_dup 1)) | |
10233 | (set (pc) | |
10234 | (if_then_else (ge (match_dup 2) | |
10235 | (const_int 0)) | |
10236 | (label_ref (match_operand 0 "" "")) | |
10237 | (pc)))] | |
10238 | "" | |
10239 | " | |
10240 | { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode; | |
39403d82 | 10241 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 10242 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
10243 | operands[2] = gen_reg_rtx (mode); |
10244 | }") | |
10245 | ||
10246 | (define_expand "bgtu" | |
10247 | [(set (match_dup 2) (match_dup 1)) | |
10248 | (set (pc) | |
10249 | (if_then_else (gtu (match_dup 2) | |
10250 | (const_int 0)) | |
10251 | (label_ref (match_operand 0 "" "")) | |
10252 | (pc)))] | |
10253 | "" | |
10254 | " | |
39403d82 | 10255 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
c5c76735 | 10256 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
10257 | operands[2] = gen_reg_rtx (CCUNSmode); |
10258 | }") | |
10259 | ||
10260 | (define_expand "bltu" | |
10261 | [(set (match_dup 2) (match_dup 1)) | |
10262 | (set (pc) | |
10263 | (if_then_else (ltu (match_dup 2) | |
10264 | (const_int 0)) | |
10265 | (label_ref (match_operand 0 "" "")) | |
10266 | (pc)))] | |
10267 | "" | |
10268 | " | |
39403d82 | 10269 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
c5c76735 | 10270 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
10271 | operands[2] = gen_reg_rtx (CCUNSmode); |
10272 | }") | |
10273 | ||
10274 | (define_expand "bgeu" | |
10275 | [(set (match_dup 2) (match_dup 1)) | |
10276 | (set (pc) | |
10277 | (if_then_else (geu (match_dup 2) | |
10278 | (const_int 0)) | |
10279 | (label_ref (match_operand 0 "" "")) | |
10280 | (pc)))] | |
10281 | "" | |
10282 | " | |
39403d82 | 10283 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
c5c76735 | 10284 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
10285 | operands[2] = gen_reg_rtx (CCUNSmode); |
10286 | }") | |
10287 | ||
10288 | (define_expand "bleu" | |
10289 | [(set (match_dup 2) (match_dup 1)) | |
10290 | (set (pc) | |
10291 | (if_then_else (leu (match_dup 2) | |
10292 | (const_int 0)) | |
10293 | (label_ref (match_operand 0 "" "")) | |
10294 | (pc)))] | |
10295 | "" | |
10296 | " | |
39403d82 | 10297 | { operands[1] = gen_rtx_COMPARE (CCUNSmode, |
c5c76735 | 10298 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 RK |
10299 | operands[2] = gen_reg_rtx (CCUNSmode); |
10300 | }") | |
10301 | ||
1c882ea4 GK |
10302 | (define_expand "bunordered" |
10303 | [(set (match_dup 2) (match_dup 1)) | |
10304 | (set (pc) | |
10305 | (if_then_else (unordered (match_dup 2) | |
10306 | (const_int 0)) | |
10307 | (label_ref (match_operand 0 "" "")) | |
10308 | (pc)))] | |
10309 | "" | |
10310 | " | |
10311 | { if (!rs6000_compare_fp_p) FAIL; | |
10312 | operands[1] = gen_rtx_COMPARE (CCFPmode, | |
10313 | rs6000_compare_op0, rs6000_compare_op1); | |
10314 | operands[2] = gen_reg_rtx (CCFPmode); | |
10315 | }") | |
10316 | ||
10317 | (define_expand "bordered" | |
10318 | [(set (match_dup 2) (match_dup 1)) | |
10319 | (set (pc) | |
10320 | (if_then_else (ordered (match_dup 2) | |
10321 | (const_int 0)) | |
10322 | (label_ref (match_operand 0 "" "")) | |
10323 | (pc)))] | |
10324 | "" | |
10325 | " | |
10326 | { if (!rs6000_compare_fp_p) FAIL; | |
10327 | operands[1] = gen_rtx_COMPARE (CCFPmode, | |
10328 | rs6000_compare_op0, rs6000_compare_op1); | |
10329 | operands[2] = gen_reg_rtx (CCFPmode); | |
10330 | }") | |
10331 | ||
10332 | (define_expand "buneq" | |
10333 | [(set (match_dup 2) (match_dup 1)) | |
10334 | (set (pc) | |
10335 | (if_then_else (uneq (match_dup 2) | |
10336 | (const_int 0)) | |
10337 | (label_ref (match_operand 0 "" "")) | |
10338 | (pc)))] | |
10339 | "" | |
10340 | " | |
10341 | { if (!rs6000_compare_fp_p) FAIL; | |
10342 | operands[1] = gen_rtx_COMPARE (CCFPmode, | |
10343 | rs6000_compare_op0, rs6000_compare_op1); | |
10344 | operands[2] = gen_reg_rtx (CCFPmode); | |
10345 | }") | |
10346 | ||
10347 | (define_expand "bunge" | |
10348 | [(set (match_dup 2) (match_dup 1)) | |
10349 | (set (pc) | |
10350 | (if_then_else (unge (match_dup 2) | |
10351 | (const_int 0)) | |
10352 | (label_ref (match_operand 0 "" "")) | |
10353 | (pc)))] | |
10354 | "" | |
10355 | " | |
10356 | { if (!rs6000_compare_fp_p) FAIL; | |
10357 | operands[1] = gen_rtx_COMPARE (CCFPmode, | |
10358 | rs6000_compare_op0, rs6000_compare_op1); | |
10359 | operands[2] = gen_reg_rtx (CCFPmode); | |
10360 | }") | |
10361 | ||
10362 | (define_expand "bungt" | |
10363 | [(set (match_dup 2) (match_dup 1)) | |
10364 | (set (pc) | |
10365 | (if_then_else (ungt (match_dup 2) | |
10366 | (const_int 0)) | |
10367 | (label_ref (match_operand 0 "" "")) | |
10368 | (pc)))] | |
10369 | "" | |
10370 | " | |
10371 | { if (!rs6000_compare_fp_p) FAIL; | |
10372 | operands[1] = gen_rtx_COMPARE (CCFPmode, | |
10373 | rs6000_compare_op0, rs6000_compare_op1); | |
10374 | operands[2] = gen_reg_rtx (CCFPmode); | |
10375 | }") | |
10376 | ||
10377 | (define_expand "bunle" | |
10378 | [(set (match_dup 2) (match_dup 1)) | |
10379 | (set (pc) | |
10380 | (if_then_else (unle (match_dup 2) | |
10381 | (const_int 0)) | |
10382 | (label_ref (match_operand 0 "" "")) | |
10383 | (pc)))] | |
10384 | "" | |
10385 | " | |
10386 | { if (!rs6000_compare_fp_p) FAIL; | |
10387 | operands[1] = gen_rtx_COMPARE (CCFPmode, | |
10388 | rs6000_compare_op0, rs6000_compare_op1); | |
10389 | operands[2] = gen_reg_rtx (CCFPmode); | |
10390 | }") | |
10391 | ||
10392 | (define_expand "bunlt" | |
10393 | [(set (match_dup 2) (match_dup 1)) | |
10394 | (set (pc) | |
10395 | (if_then_else (unlt (match_dup 2) | |
10396 | (const_int 0)) | |
10397 | (label_ref (match_operand 0 "" "")) | |
10398 | (pc)))] | |
10399 | "" | |
10400 | " | |
10401 | { if (!rs6000_compare_fp_p) FAIL; | |
10402 | operands[1] = gen_rtx_COMPARE (CCFPmode, | |
10403 | rs6000_compare_op0, rs6000_compare_op1); | |
10404 | operands[2] = gen_reg_rtx (CCFPmode); | |
10405 | }") | |
10406 | ||
10407 | (define_expand "bltgt" | |
10408 | [(set (match_dup 2) (match_dup 1)) | |
10409 | (set (pc) | |
10410 | (if_then_else (ltgt (match_dup 2) | |
10411 | (const_int 0)) | |
10412 | (label_ref (match_operand 0 "" "")) | |
10413 | (pc)))] | |
10414 | "" | |
10415 | " | |
10416 | { if (!rs6000_compare_fp_p) FAIL; | |
10417 | operands[1] = gen_rtx_COMPARE (CCFPmode, | |
10418 | rs6000_compare_op0, rs6000_compare_op1); | |
10419 | operands[2] = gen_reg_rtx (CCFPmode); | |
10420 | }") | |
10421 | ||
1fd4e8c1 RK |
10422 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. |
10423 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
10424 | ;; with an scc insns. However, due to the order that combine see the | |
10425 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
10426 | ;; the cases we don't want to handle. | |
10427 | (define_expand "seq" | |
10428 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 10429 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10430 | (eq:SI (match_dup 2) (const_int 0)))] |
10431 | "" | |
10432 | " | |
9ebbca7d | 10433 | { enum machine_mode op_mode, mode = rs6000_compare_fp_p ? CCFPmode : CCmode; |
39403d82 | 10434 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 10435 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 | 10436 | operands[2] = gen_reg_rtx (mode); |
9ebbca7d GK |
10437 | |
10438 | op_mode = GET_MODE (rs6000_compare_op0); | |
10439 | if (op_mode == VOIDmode) | |
10440 | op_mode = GET_MODE (rs6000_compare_op1); | |
10441 | ||
10442 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
10443 | { | |
10444 | emit_insn (gen_rtx_SET (VOIDmode, operands[2], operands[1])); | |
10445 | convert_move (operands[0], | |
10446 | gen_rtx_EQ (DImode, operands[2], const0_rtx), 0); | |
10447 | DONE; | |
10448 | } | |
1fd4e8c1 RK |
10449 | }") |
10450 | ||
10451 | (define_expand "sne" | |
10452 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 10453 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10454 | (ne:SI (match_dup 2) (const_int 0)))] |
10455 | "" | |
10456 | " | |
10457 | { if (! rs6000_compare_fp_p) | |
10458 | FAIL; | |
10459 | ||
39403d82 | 10460 | operands[1] = gen_rtx_COMPARE (CCFPmode, |
c5c76735 | 10461 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 | 10462 | operands[2] = gen_reg_rtx (CCFPmode); |
9ebbca7d GK |
10463 | |
10464 | if (TARGET_POWERPC64) | |
10465 | { | |
10466 | emit_insn (gen_rtx_SET (VOIDmode, operands[2], operands[1])); | |
10467 | convert_move (operands[0], | |
10468 | gen_rtx_NE (DImode, operands[2], const0_rtx), 0); | |
10469 | DONE; | |
10470 | } | |
1fd4e8c1 RK |
10471 | }") |
10472 | ||
10473 | ;; A > 0 is best done using the portable sequence, so fail in that case. | |
10474 | (define_expand "sgt" | |
10475 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 10476 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10477 | (gt:SI (match_dup 2) (const_int 0)))] |
10478 | "" | |
10479 | " | |
9ebbca7d | 10480 | { enum machine_mode op_mode, mode = rs6000_compare_fp_p ? CCFPmode : CCmode; |
1fd4e8c1 RK |
10481 | |
10482 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) | |
10483 | FAIL; | |
10484 | ||
39403d82 | 10485 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 10486 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 | 10487 | operands[2] = gen_reg_rtx (mode); |
9ebbca7d GK |
10488 | |
10489 | op_mode = GET_MODE (rs6000_compare_op0); | |
10490 | if (op_mode == VOIDmode) | |
10491 | op_mode = GET_MODE (rs6000_compare_op1); | |
10492 | ||
10493 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
10494 | { | |
10495 | emit_insn (gen_rtx_SET (VOIDmode, operands[2], operands[1])); | |
10496 | convert_move (operands[0], | |
10497 | gen_rtx_GT (DImode, operands[2], const0_rtx), 0); | |
10498 | DONE; | |
10499 | } | |
1fd4e8c1 RK |
10500 | }") |
10501 | ||
10502 | ;; A < 0 is best done in the portable way for A an integer. | |
10503 | (define_expand "slt" | |
10504 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 10505 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10506 | (lt:SI (match_dup 2) (const_int 0)))] |
10507 | "" | |
10508 | " | |
9ebbca7d | 10509 | { enum machine_mode op_mode, mode = rs6000_compare_fp_p ? CCFPmode : CCmode; |
1fd4e8c1 RK |
10510 | |
10511 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) | |
10512 | FAIL; | |
10513 | ||
39403d82 | 10514 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 10515 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 | 10516 | operands[2] = gen_reg_rtx (mode); |
9ebbca7d GK |
10517 | |
10518 | op_mode = GET_MODE (rs6000_compare_op0); | |
10519 | if (op_mode == VOIDmode) | |
10520 | op_mode = GET_MODE (rs6000_compare_op1); | |
10521 | ||
10522 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
10523 | { | |
10524 | emit_insn (gen_rtx_SET (VOIDmode, operands[2], operands[1])); | |
10525 | convert_move (operands[0], | |
10526 | gen_rtx_LT (DImode, operands[2], const0_rtx), 0); | |
10527 | DONE; | |
10528 | } | |
1fd4e8c1 RK |
10529 | }") |
10530 | ||
10531 | (define_expand "sge" | |
10532 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 10533 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10534 | (ge:SI (match_dup 2) (const_int 0)))] |
10535 | "" | |
10536 | " | |
9ebbca7d | 10537 | { enum machine_mode op_mode, mode = rs6000_compare_fp_p ? CCFPmode : CCmode; |
39403d82 | 10538 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 10539 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 | 10540 | operands[2] = gen_reg_rtx (mode); |
9ebbca7d GK |
10541 | |
10542 | op_mode = GET_MODE (rs6000_compare_op0); | |
10543 | if (op_mode == VOIDmode) | |
10544 | op_mode = GET_MODE (rs6000_compare_op1); | |
10545 | ||
10546 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
10547 | { | |
10548 | emit_insn (gen_rtx_SET (VOIDmode, operands[2], operands[1])); | |
10549 | convert_move (operands[0], | |
10550 | gen_rtx_GE (DImode, operands[2], const0_rtx), 0); | |
10551 | DONE; | |
10552 | } | |
1fd4e8c1 RK |
10553 | }") |
10554 | ||
10555 | ;; A <= 0 is best done the portable way for A an integer. | |
10556 | (define_expand "sle" | |
10557 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 10558 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10559 | (le:SI (match_dup 2) (const_int 0)))] |
10560 | "" | |
10561 | " | |
9ebbca7d | 10562 | { enum machine_mode op_mode, mode = rs6000_compare_fp_p ? CCFPmode : CCmode; |
1fd4e8c1 RK |
10563 | |
10564 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) | |
10565 | FAIL; | |
10566 | ||
39403d82 | 10567 | operands[1] = gen_rtx_COMPARE (mode, |
c5c76735 | 10568 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 | 10569 | operands[2] = gen_reg_rtx (mode); |
9ebbca7d GK |
10570 | |
10571 | op_mode = GET_MODE (rs6000_compare_op0); | |
10572 | if (op_mode == VOIDmode) | |
10573 | op_mode = GET_MODE (rs6000_compare_op1); | |
10574 | ||
10575 | if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p)) | |
10576 | { | |
10577 | emit_insn (gen_rtx_SET (VOIDmode, operands[2], operands[1])); | |
10578 | convert_move (operands[0], | |
10579 | gen_rtx_LE (DImode, operands[2], const0_rtx), 0); | |
10580 | DONE; | |
10581 | } | |
1fd4e8c1 RK |
10582 | }") |
10583 | ||
10584 | (define_expand "sgtu" | |
10585 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 10586 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10587 | (gtu:SI (match_dup 2) (const_int 0)))] |
10588 | "" | |
10589 | " | |
9ebbca7d GK |
10590 | { enum machine_mode op_mode; |
10591 | ||
10592 | operands[1] = gen_rtx_COMPARE (CCUNSmode, | |
c5c76735 | 10593 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 | 10594 | operands[2] = gen_reg_rtx (CCUNSmode); |
9ebbca7d GK |
10595 | |
10596 | op_mode = GET_MODE (rs6000_compare_op0); | |
10597 | if (op_mode == VOIDmode) | |
10598 | op_mode = GET_MODE (rs6000_compare_op1); | |
10599 | ||
10600 | if (TARGET_POWERPC64 && op_mode == DImode) | |
10601 | { | |
10602 | emit_insn (gen_rtx_SET (VOIDmode, operands[2], operands[1])); | |
10603 | convert_move (operands[0], | |
10604 | gen_rtx_GTU (DImode, operands[2], const0_rtx), 0); | |
10605 | DONE; | |
10606 | } | |
1fd4e8c1 RK |
10607 | }") |
10608 | ||
10609 | (define_expand "sltu" | |
10610 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 10611 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10612 | (ltu:SI (match_dup 2) (const_int 0)))] |
10613 | "" | |
10614 | " | |
9ebbca7d GK |
10615 | { enum machine_mode op_mode; |
10616 | ||
10617 | operands[1] = gen_rtx_COMPARE (CCUNSmode, | |
c5c76735 | 10618 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 | 10619 | operands[2] = gen_reg_rtx (CCUNSmode); |
9ebbca7d GK |
10620 | |
10621 | op_mode = GET_MODE (rs6000_compare_op0); | |
10622 | if (op_mode == VOIDmode) | |
10623 | op_mode = GET_MODE (rs6000_compare_op1); | |
10624 | ||
10625 | if (TARGET_POWERPC64 && op_mode == DImode) | |
10626 | { | |
10627 | emit_insn (gen_rtx_SET (VOIDmode, operands[2], operands[1])); | |
10628 | convert_move (operands[0], | |
10629 | gen_rtx_LTU (DImode, operands[2], const0_rtx), 0); | |
10630 | DONE; | |
10631 | } | |
1fd4e8c1 RK |
10632 | }") |
10633 | ||
10634 | (define_expand "sgeu" | |
10635 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 10636 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10637 | (geu:SI (match_dup 2) (const_int 0)))] |
10638 | "" | |
10639 | " | |
9ebbca7d GK |
10640 | { enum machine_mode op_mode; |
10641 | ||
10642 | operands[1] = gen_rtx_COMPARE (CCUNSmode, | |
c5c76735 | 10643 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 | 10644 | operands[2] = gen_reg_rtx (CCUNSmode); |
9ebbca7d GK |
10645 | |
10646 | op_mode = GET_MODE (rs6000_compare_op0); | |
10647 | if (op_mode == VOIDmode) | |
10648 | op_mode = GET_MODE (rs6000_compare_op1); | |
10649 | ||
10650 | if (TARGET_POWERPC64 && op_mode == DImode) | |
10651 | { | |
10652 | emit_insn (gen_rtx_SET (VOIDmode, operands[2], operands[1])); | |
10653 | convert_move (operands[0], | |
10654 | gen_rtx_GEU (DImode, operands[2], const0_rtx), 0); | |
10655 | DONE; | |
10656 | } | |
1fd4e8c1 RK |
10657 | }") |
10658 | ||
10659 | (define_expand "sleu" | |
10660 | [(set (match_dup 2) (match_dup 1)) | |
cd2b37d9 | 10661 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10662 | (leu:SI (match_dup 2) (const_int 0)))] |
10663 | "" | |
10664 | " | |
9ebbca7d GK |
10665 | { enum machine_mode op_mode; |
10666 | ||
10667 | operands[1] = gen_rtx_COMPARE (CCUNSmode, | |
c5c76735 | 10668 | rs6000_compare_op0, rs6000_compare_op1); |
1fd4e8c1 | 10669 | operands[2] = gen_reg_rtx (CCUNSmode); |
9ebbca7d GK |
10670 | |
10671 | op_mode = GET_MODE (rs6000_compare_op0); | |
10672 | if (op_mode == VOIDmode) | |
10673 | op_mode = GET_MODE (rs6000_compare_op1); | |
10674 | ||
10675 | if (TARGET_POWERPC64 && op_mode == DImode) | |
10676 | { | |
10677 | emit_insn (gen_rtx_SET (VOIDmode, operands[2], operands[1])); | |
10678 | convert_move (operands[0], | |
10679 | gen_rtx_LEU (DImode, operands[2], const0_rtx), 0); | |
10680 | DONE; | |
10681 | } | |
1fd4e8c1 RK |
10682 | }") |
10683 | \f | |
10684 | ;; Here are the actual compare insns. | |
acad7ed3 | 10685 | (define_insn "*cmpsi_internal1" |
1fd4e8c1 | 10686 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
cd2b37d9 | 10687 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
10688 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
10689 | "" | |
7f340546 | 10690 | "{cmp%I2|cmpw%I2} %0,%1,%2" |
1fd4e8c1 RK |
10691 | [(set_attr "type" "compare")]) |
10692 | ||
acad7ed3 | 10693 | (define_insn "*cmpdi_internal1" |
266eb58a DE |
10694 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
10695 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
10696 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
10697 | "TARGET_POWERPC64" | |
10698 | "cmpd%I2 %0,%1,%2" | |
10699 | [(set_attr "type" "compare")]) | |
10700 | ||
f357808b RK |
10701 | ;; If we are comparing a register for equality with a large constant, |
10702 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
10703 | ;; register for the result of the XOR. | |
10704 | ||
10705 | (define_split | |
10706 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 10707 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 10708 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 10709 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
10710 | "find_single_use (operands[0], insn, 0) |
10711 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
10712 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
10713 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
10714 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
10715 | " | |
10716 | { | |
10717 | /* Get the constant we are comparing against, C, and see what it looks like | |
10718 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
10719 | with C to get the sign-extended value. */ | |
10720 | ||
5f59ecb7 DE |
10721 | HOST_WIDE_INT c = INTVAL (operands[2]); |
10722 | HOST_WIDE_INT sextc = (c & 0x7fff) - (c & 0x8000); | |
10723 | HOST_WIDE_INT xorv = c ^ sextc; | |
f357808b | 10724 | |
89e9f3a8 MM |
10725 | operands[4] = GEN_INT (xorv); |
10726 | operands[5] = GEN_INT (sextc); | |
f357808b RK |
10727 | }") |
10728 | ||
acad7ed3 | 10729 | (define_insn "*cmpsi_internal2" |
1fd4e8c1 | 10730 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
cd2b37d9 | 10731 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
9ebbca7d | 10732 | (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] |
1fd4e8c1 | 10733 | "" |
7f340546 | 10734 | "{cmpl%I2|cmplw%I2} %0,%1,%W2" |
1fd4e8c1 RK |
10735 | [(set_attr "type" "compare")]) |
10736 | ||
acad7ed3 | 10737 | (define_insn "*cmpdi_internal2" |
266eb58a DE |
10738 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
10739 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
9ebbca7d | 10740 | (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] |
266eb58a DE |
10741 | "" |
10742 | "cmpld%I2 %0,%1,%W2" | |
10743 | [(set_attr "type" "compare")]) | |
10744 | ||
1fd4e8c1 RK |
10745 | ;; The following two insns don't exist as single insns, but if we provide |
10746 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
10747 | ;; of the required delay between a compare and branch. We generate code for | |
10748 | ;; them by splitting. | |
10749 | ||
10750 | (define_insn "" | |
10751 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 10752 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 10753 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 10754 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10755 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
10756 | "" | |
baf97f86 RK |
10757 | "#" |
10758 | [(set_attr "length" "8")]) | |
7e69e155 | 10759 | |
1fd4e8c1 RK |
10760 | (define_insn "" |
10761 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 10762 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 10763 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 10764 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10765 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
10766 | "" | |
baf97f86 RK |
10767 | "#" |
10768 | [(set_attr "length" "8")]) | |
7e69e155 | 10769 | |
1fd4e8c1 RK |
10770 | (define_split |
10771 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 10772 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 10773 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 10774 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10775 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
10776 | "" | |
10777 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
10778 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
10779 | ||
10780 | (define_split | |
10781 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 10782 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 10783 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 10784 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10785 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
10786 | "" | |
10787 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
10788 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
10789 | ||
acad7ed3 | 10790 | (define_insn "*cmpsf_internal1" |
1fd4e8c1 | 10791 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
10792 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
10793 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 10794 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10795 | "fcmpu %0,%1,%2" |
10796 | [(set_attr "type" "fpcompare")]) | |
10797 | ||
acad7ed3 | 10798 | (define_insn "*cmpdf_internal1" |
1fd4e8c1 | 10799 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
10800 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
10801 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
d14a6d05 | 10802 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10803 | "fcmpu %0,%1,%2" |
10804 | [(set_attr "type" "fpcompare")]) | |
10805 | \f | |
10806 | ;; Now we have the scc insns. We can do some combinations because of the | |
10807 | ;; way the machine works. | |
10808 | ;; | |
10809 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
10810 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
10811 | ;; cases the insns below which don't use an intermediate CR field will | |
10812 | ;; be used instead. | |
1fd4e8c1 | 10813 | (define_insn "" |
cd2b37d9 | 10814 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10815 | (match_operator:SI 1 "scc_comparison_operator" |
10816 | [(match_operand 2 "cc_reg_operand" "y") | |
10817 | (const_int 0)]))] | |
10818 | "" | |
ca7f5001 | 10819 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" |
b19003d8 | 10820 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
10821 | |
10822 | (define_insn "" | |
9ebbca7d GK |
10823 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
10824 | (match_operator:DI 1 "scc_comparison_operator" | |
10825 | [(match_operand 2 "cc_reg_operand" "y") | |
10826 | (const_int 0)]))] | |
10827 | "TARGET_POWERPC64" | |
10828 | "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" | |
10829 | [(set_attr "length" "12")]) | |
10830 | ||
10831 | (define_insn "" | |
10832 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 10833 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" |
9ebbca7d | 10834 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 RK |
10835 | (const_int 0)]) |
10836 | (const_int 0))) | |
9ebbca7d | 10837 | (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 10838 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
0ad91047 | 10839 | "! TARGET_POWERPC64" |
9ebbca7d GK |
10840 | "@ |
10841 | %D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1 | |
10842 | #" | |
b19003d8 | 10843 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
10844 | (set_attr "length" "12,16")]) |
10845 | ||
10846 | (define_split | |
10847 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10848 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
10849 | [(match_operand 2 "cc_reg_operand" "") | |
10850 | (const_int 0)]) | |
10851 | (const_int 0))) | |
10852 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
10853 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] | |
10854 | "! TARGET_POWERPC64 && reload_completed" | |
10855 | [(set (match_dup 3) | |
10856 | (match_op_dup 1 [(match_dup 2) (const_int 0)])) | |
10857 | (set (match_dup 0) | |
10858 | (compare:CC (match_dup 3) | |
10859 | (const_int 0)))] | |
10860 | "") | |
1fd4e8c1 RK |
10861 | |
10862 | (define_insn "" | |
cd2b37d9 | 10863 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10864 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
10865 | [(match_operand 2 "cc_reg_operand" "y") | |
10866 | (const_int 0)]) | |
10867 | (match_operand:SI 3 "const_int_operand" "n")))] | |
10868 | "" | |
10869 | "* | |
10870 | { | |
10871 | int is_bit = ccr_bit (operands[1], 1); | |
10872 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
10873 | int count; | |
10874 | ||
10875 | if (is_bit >= put_bit) | |
10876 | count = is_bit - put_bit; | |
10877 | else | |
10878 | count = 32 - (put_bit - is_bit); | |
10879 | ||
89e9f3a8 MM |
10880 | operands[4] = GEN_INT (count); |
10881 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 10882 | |
ca7f5001 | 10883 | return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 RK |
10884 | }" |
10885 | [(set_attr "length" "12")]) | |
1fd4e8c1 RK |
10886 | |
10887 | (define_insn "" | |
9ebbca7d | 10888 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
10889 | (compare:CC |
10890 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
9ebbca7d | 10891 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 | 10892 | (const_int 0)]) |
9ebbca7d | 10893 | (match_operand:SI 3 "const_int_operand" "n,n")) |
1fd4e8c1 | 10894 | (const_int 0))) |
9ebbca7d | 10895 | (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
10896 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
10897 | (match_dup 3)))] | |
9ebbca7d | 10898 | "! TARGET_POWERPC64" |
1fd4e8c1 RK |
10899 | "* |
10900 | { | |
10901 | int is_bit = ccr_bit (operands[1], 1); | |
10902 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
10903 | int count; | |
10904 | ||
9ebbca7d GK |
10905 | /* Force split for non-cc0 compare. */ |
10906 | if (which_alternative == 1) | |
10907 | return \"#\"; | |
10908 | ||
1fd4e8c1 RK |
10909 | if (is_bit >= put_bit) |
10910 | count = is_bit - put_bit; | |
10911 | else | |
10912 | count = 32 - (put_bit - is_bit); | |
10913 | ||
89e9f3a8 MM |
10914 | operands[5] = GEN_INT (count); |
10915 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 10916 | |
ca7f5001 | 10917 | return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 10918 | }" |
b19003d8 | 10919 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
10920 | (set_attr "length" "12,16")]) |
10921 | ||
10922 | (define_split | |
10923 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
10924 | (compare:CC | |
10925 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
10926 | [(match_operand 2 "cc_reg_operand" "") | |
10927 | (const_int 0)]) | |
10928 | (match_operand:SI 3 "const_int_operand" "")) | |
10929 | (const_int 0))) | |
10930 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
10931 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
10932 | (match_dup 3)))] | |
10933 | "! TARGET_POWERPC64 && reload_completed" | |
10934 | [(set (match_dup 4) | |
10935 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
10936 | (match_dup 3))) | |
10937 | (set (match_dup 0) | |
10938 | (compare:CC (match_dup 4) | |
10939 | (const_int 0)))] | |
10940 | "") | |
1fd4e8c1 | 10941 | |
c5defebb RK |
10942 | ;; If we are comparing the result of two comparisons, this can be done |
10943 | ;; using creqv or crxor. | |
10944 | ||
10945 | (define_insn "" | |
10946 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
10947 | (compare:CCEQ (match_operator 1 "scc_comparison_operator" | |
10948 | [(match_operand 2 "cc_reg_operand" "y") | |
10949 | (const_int 0)]) | |
10950 | (match_operator 3 "scc_comparison_operator" | |
10951 | [(match_operand 4 "cc_reg_operand" "y") | |
10952 | (const_int 0)])))] | |
10953 | "REGNO (operands[2]) != REGNO (operands[4])" | |
10954 | "* | |
10955 | { | |
10956 | enum rtx_code code1, code2; | |
10957 | ||
10958 | code1 = GET_CODE (operands[1]); | |
10959 | code2 = GET_CODE (operands[3]); | |
10960 | ||
10961 | if ((code1 == EQ || code1 == LT || code1 == GT | |
10962 | || code1 == LTU || code1 == GTU | |
10963 | || (code1 != NE && GET_MODE (operands[2]) == CCFPmode)) | |
10964 | != | |
10965 | (code2 == EQ || code2 == LT || code2 == GT | |
10966 | || code2 == LTU || code2 == GTU | |
10967 | || (code2 != NE && GET_MODE (operands[4]) == CCFPmode))) | |
10968 | return \"%C1%C3crxor %E0,%j1,%j3\"; | |
10969 | else | |
10970 | return \"%C1%C3creqv %E0,%j1,%j3\"; | |
b19003d8 RK |
10971 | }" |
10972 | [(set_attr "length" "12")]) | |
c5defebb RK |
10973 | |
10974 | ;; There is a 3 cycle delay between consecutive mfcr instructions | |
10975 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
10976 | ||
10977 | (define_peephole | |
cd2b37d9 | 10978 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
10979 | (match_operator:SI 1 "scc_comparison_operator" |
10980 | [(match_operand 2 "cc_reg_operand" "y") | |
10981 | (const_int 0)])) | |
cd2b37d9 | 10982 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
10983 | (match_operator:SI 4 "scc_comparison_operator" |
10984 | [(match_operand 5 "cc_reg_operand" "y") | |
10985 | (const_int 0)]))] | |
10986 | "REGNO (operands[2]) != REGNO (operands[5])" | |
ca7f5001 | 10987 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b19003d8 | 10988 | [(set_attr "length" "20")]) |
c5defebb | 10989 | |
9ebbca7d GK |
10990 | (define_peephole |
10991 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
10992 | (match_operator:DI 1 "scc_comparison_operator" | |
10993 | [(match_operand 2 "cc_reg_operand" "y") | |
10994 | (const_int 0)])) | |
10995 | (set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
10996 | (match_operator:DI 4 "scc_comparison_operator" | |
10997 | [(match_operand 5 "cc_reg_operand" "y") | |
10998 | (const_int 0)]))] | |
10999 | "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" | |
11000 | "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" | |
11001 | [(set_attr "length" "20")]) | |
11002 | ||
1fd4e8c1 RK |
11003 | ;; There are some scc insns that can be done directly, without a compare. |
11004 | ;; These are faster because they don't involve the communications between | |
11005 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
11006 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
11007 | ;; | |
11008 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
11009 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
11010 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
11011 | ;; cases where it is no more expensive than (neg (scc ..)). | |
11012 | ||
11013 | ;; Have reload force a constant into a register for the simple insns that | |
11014 | ;; otherwise won't accept constants. We do this because it is faster than | |
11015 | ;; the cmp/mfcr sequence we would otherwise generate. | |
11016 | ||
11017 | (define_insn "" | |
cd2b37d9 RK |
11018 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
11019 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 11020 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) |
1fd4e8c1 | 11021 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] |
f9562f27 | 11022 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11023 | "@ |
ca7f5001 | 11024 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
71d2371f | 11025 | {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 |
ca7f5001 RK |
11026 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
11027 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 | |
11028 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" | |
b19003d8 | 11029 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 11030 | |
a260abc9 DE |
11031 | (define_insn "" |
11032 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") | |
11033 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
11034 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) | |
11035 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] | |
11036 | "TARGET_POWERPC64" | |
11037 | "@ | |
11038 | xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11039 | subfic %3,%1,0\;adde %0,%3,%1 | |
11040 | xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11041 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11042 | subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" | |
11043 | [(set_attr "length" "12,8,12,12,12")]) | |
11044 | ||
1fd4e8c1 | 11045 | (define_insn "" |
9ebbca7d | 11046 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11047 | (compare:CC |
9ebbca7d GK |
11048 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11049 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
1fd4e8c1 | 11050 | (const_int 0))) |
9ebbca7d | 11051 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 11052 | (eq:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11053 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
f9562f27 | 11054 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11055 | "@ |
ca7f5001 RK |
11056 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
11057 | {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 | |
11058 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
11059 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
9ebbca7d GK |
11060 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
11061 | # | |
11062 | # | |
11063 | # | |
11064 | # | |
11065 | #" | |
b19003d8 | 11066 | [(set_attr "type" "compare") |
9ebbca7d GK |
11067 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11068 | ||
11069 | (define_split | |
11070 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11071 | (compare:CC | |
11072 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11073 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11074 | (const_int 0))) | |
11075 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11076 | (eq:SI (match_dup 1) (match_dup 2))) | |
11077 | (clobber (match_scratch:SI 3 ""))] | |
11078 | "! TARGET_POWERPC64 && reload_completed" | |
11079 | [(parallel [(set (match_dup 0) | |
11080 | (eq:SI (match_dup 1) (match_dup 2))) | |
11081 | (clobber (match_dup 3))]) | |
11082 | (set (match_dup 4) | |
11083 | (compare:CC (match_dup 0) | |
11084 | (const_int 0)))] | |
11085 | "") | |
b19003d8 | 11086 | |
a260abc9 | 11087 | (define_insn "" |
9ebbca7d | 11088 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
a260abc9 | 11089 | (compare:CC |
9ebbca7d GK |
11090 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11091 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) | |
a260abc9 | 11092 | (const_int 0))) |
9ebbca7d | 11093 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
a260abc9 | 11094 | (eq:DI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11095 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
a260abc9 DE |
11096 | "TARGET_POWERPC64" |
11097 | "@ | |
11098 | xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
11099 | subfic %3,%1,0\;adde. %0,%3,%1 | |
11100 | xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
11101 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
9ebbca7d GK |
11102 | subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 |
11103 | # | |
11104 | # | |
11105 | # | |
11106 | # | |
11107 | #" | |
a260abc9 | 11108 | [(set_attr "type" "compare") |
9ebbca7d GK |
11109 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11110 | ||
11111 | (define_split | |
11112 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11113 | (compare:CC | |
11114 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11115 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
11116 | (const_int 0))) | |
11117 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11118 | (eq:DI (match_dup 1) (match_dup 2))) | |
11119 | (clobber (match_scratch:DI 3 ""))] | |
11120 | "TARGET_POWERPC64 && reload_completed" | |
11121 | [(parallel [(set (match_dup 0) | |
11122 | (eq:DI (match_dup 1) (match_dup 2))) | |
11123 | (clobber (match_dup 3))]) | |
11124 | (set (match_dup 4) | |
11125 | (compare:CC (match_dup 0) | |
11126 | (const_int 0)))] | |
11127 | "") | |
a260abc9 | 11128 | |
b19003d8 RK |
11129 | ;; We have insns of the form shown by the first define_insn below. If |
11130 | ;; there is something inside the comparison operation, we must split it. | |
11131 | (define_split | |
11132 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
11133 | (plus:SI (match_operator 1 "comparison_operator" | |
11134 | [(match_operand:SI 2 "" "") | |
11135 | (match_operand:SI 3 | |
11136 | "reg_or_cint_operand" "")]) | |
11137 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
11138 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
11139 | "! gpc_reg_operand (operands[2], SImode)" | |
11140 | [(set (match_dup 5) (match_dup 2)) | |
11141 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
11142 | (match_dup 4)))]) | |
1fd4e8c1 RK |
11143 | |
11144 | (define_insn "" | |
cd2b37d9 RK |
11145 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
11146 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 11147 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) |
cd2b37d9 | 11148 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))) |
1fd4e8c1 | 11149 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] |
f9562f27 | 11150 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11151 | "@ |
ca7f5001 RK |
11152 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 |
11153 | {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3 | |
11154 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 | |
11155 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 | |
d9d934ef | 11156 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" |
b19003d8 | 11157 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
11158 | |
11159 | (define_insn "" | |
9ebbca7d | 11160 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11161 | (compare:CC |
1fd4e8c1 | 11162 | (plus:SI |
9ebbca7d GK |
11163 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11164 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
11165 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 11166 | (const_int 0))) |
9ebbca7d | 11167 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
f9562f27 | 11168 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11169 | "@ |
ca7f5001 | 11170 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 11171 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
11172 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11173 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
9ebbca7d GK |
11174 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11175 | # | |
11176 | # | |
11177 | # | |
11178 | # | |
11179 | #" | |
b19003d8 | 11180 | [(set_attr "type" "compare") |
9ebbca7d GK |
11181 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11182 | ||
11183 | (define_split | |
11184 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11185 | (compare:CC | |
11186 | (plus:SI | |
11187 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11188 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11189 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11190 | (const_int 0))) | |
11191 | (clobber (match_scratch:SI 4 ""))] | |
11192 | "! TARGET_POWERPC64 && reload_completed" | |
11193 | [(set (match_dup 4) | |
11194 | (plus:SI (eq:SI (match_dup 1) | |
11195 | (match_dup 2)) | |
11196 | (match_dup 3))) | |
11197 | (set (match_dup 0) | |
11198 | (compare:CC (match_dup 4) | |
11199 | (const_int 0)))] | |
11200 | "") | |
1fd4e8c1 RK |
11201 | |
11202 | (define_insn "" | |
9ebbca7d | 11203 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11204 | (compare:CC |
1fd4e8c1 | 11205 | (plus:SI |
9ebbca7d GK |
11206 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11207 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
11208 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 11209 | (const_int 0))) |
9ebbca7d | 11210 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 11211 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11212 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
f9562f27 | 11213 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11214 | "@ |
ca7f5001 | 11215 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
19378cf8 | 11216 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %0,%3 |
ca7f5001 RK |
11217 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
11218 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
11219 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
11220 | # | |
11221 | # | |
11222 | # | |
11223 | # | |
11224 | #" | |
11225 | [(set_attr "type" "compare") | |
11226 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) | |
11227 | ||
11228 | (define_split | |
11229 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11230 | (compare:CC | |
11231 | (plus:SI | |
11232 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11233 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11234 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11235 | (const_int 0))) | |
11236 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11237 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11238 | (clobber (match_scratch:SI 4 ""))] | |
11239 | "! TARGET_POWERPC64 && reload_completed" | |
11240 | [(parallel [(set (match_dup 0) | |
11241 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11242 | (clobber (match_dup 4))]) | |
11243 | (set (match_dup 5) | |
11244 | (compare:CC (match_dup 0) | |
11245 | (const_int 0)))] | |
11246 | "") | |
11247 | ||
1fd4e8c1 | 11248 | (define_insn "" |
cd2b37d9 | 11249 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 11250 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 11251 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))] |
f9562f27 | 11252 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11253 | "@ |
ca7f5001 RK |
11254 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
11255 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
11256 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11257 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11258 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 11259 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 11260 | |
ea9be077 MM |
11261 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
11262 | ;; since it nabs/sr is just as fast. | |
463b558b | 11263 | (define_insn "*ne0" |
b4e95693 | 11264 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
11265 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
11266 | (const_int 31))) | |
11267 | (clobber (match_scratch:SI 2 "=&r"))] | |
9ebbca7d | 11268 | "! TARGET_POWER && ! TARGET_POWERPC64" |
ea9be077 MM |
11269 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" |
11270 | [(set_attr "length" "8")]) | |
11271 | ||
a260abc9 DE |
11272 | (define_insn "" |
11273 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11274 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11275 | (const_int 63))) | |
11276 | (clobber (match_scratch:DI 2 "=&r"))] | |
11277 | "TARGET_POWERPC64" | |
11278 | "addic %2,%1,-1\;subfe %0,%2,%1" | |
11279 | [(set_attr "length" "8")]) | |
11280 | ||
1fd4e8c1 RK |
11281 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
11282 | (define_insn "" | |
cd2b37d9 | 11283 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 11284 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 11285 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11286 | (const_int 31)) |
cd2b37d9 | 11287 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11288 | (clobber (match_scratch:SI 3 "=&r"))] |
f9562f27 | 11289 | "! TARGET_POWERPC64" |
ca7f5001 | 11290 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
b19003d8 | 11291 | [(set_attr "length" "8")]) |
1fd4e8c1 | 11292 | |
a260abc9 DE |
11293 | (define_insn "" |
11294 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11295 | (plus:DI (lshiftrt:DI | |
11296 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11297 | (const_int 63)) | |
11298 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
11299 | (clobber (match_scratch:DI 3 "=&r"))] | |
11300 | "TARGET_POWERPC64" | |
11301 | "addic %3,%1,-1\;addze %0,%2" | |
11302 | [(set_attr "length" "8")]) | |
11303 | ||
1fd4e8c1 | 11304 | (define_insn "" |
9ebbca7d | 11305 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11306 | (compare:CC |
11307 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11308 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11309 | (const_int 31)) |
9ebbca7d | 11310 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11311 | (const_int 0))) |
9ebbca7d | 11312 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 11313 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11314 | "@ |
11315 | {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 | |
11316 | #" | |
b19003d8 | 11317 | [(set_attr "type" "compare") |
9ebbca7d GK |
11318 | (set_attr "length" "8,12")]) |
11319 | ||
11320 | (define_split | |
11321 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11322 | (compare:CC | |
11323 | (plus:SI (lshiftrt:SI | |
11324 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11325 | (const_int 31)) | |
11326 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11327 | (const_int 0))) | |
11328 | (clobber (match_scratch:SI 3 ""))] | |
11329 | "! TARGET_POWERPC64 && reload_completed" | |
11330 | [(set (match_dup 3) | |
11331 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) | |
11332 | (const_int 31)) | |
11333 | (match_dup 2))) | |
11334 | (set (match_dup 0) | |
11335 | (compare:CC (match_dup 3) | |
11336 | (const_int 0)))] | |
11337 | "") | |
1fd4e8c1 | 11338 | |
a260abc9 | 11339 | (define_insn "" |
9ebbca7d | 11340 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11341 | (compare:CC |
11342 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11343 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11344 | (const_int 63)) |
9ebbca7d | 11345 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11346 | (const_int 0))) |
9ebbca7d | 11347 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
a260abc9 | 11348 | "TARGET_POWERPC64" |
9ebbca7d GK |
11349 | "@ |
11350 | addic %3,%1,-1\;addze. %3,%2 | |
11351 | #" | |
a260abc9 | 11352 | [(set_attr "type" "compare") |
9ebbca7d GK |
11353 | (set_attr "length" "8,12")]) |
11354 | ||
11355 | (define_split | |
11356 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11357 | (compare:CC | |
11358 | (plus:DI (lshiftrt:DI | |
11359 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11360 | (const_int 63)) | |
11361 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11362 | (const_int 0))) | |
11363 | (clobber (match_scratch:DI 3 ""))] | |
11364 | "TARGET_POWERPC64 && reload_completed" | |
11365 | [(set (match_dup 3) | |
11366 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) | |
11367 | (const_int 63)) | |
11368 | (match_dup 2))) | |
11369 | (set (match_dup 0) | |
11370 | (compare:CC (match_dup 3) | |
11371 | (const_int 0)))] | |
11372 | "") | |
a260abc9 | 11373 | |
1fd4e8c1 | 11374 | (define_insn "" |
9ebbca7d | 11375 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11376 | (compare:CC |
11377 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11378 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11379 | (const_int 31)) |
9ebbca7d | 11380 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11381 | (const_int 0))) |
9ebbca7d | 11382 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11383 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
11384 | (match_dup 2))) | |
9ebbca7d | 11385 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 11386 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11387 | "@ |
11388 | {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 | |
11389 | #" | |
b19003d8 | 11390 | [(set_attr "type" "compare") |
9ebbca7d GK |
11391 | (set_attr "length" "8,12")]) |
11392 | ||
11393 | (define_split | |
11394 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11395 | (compare:CC | |
11396 | (plus:SI (lshiftrt:SI | |
11397 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11398 | (const_int 31)) | |
11399 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11400 | (const_int 0))) | |
11401 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11402 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11403 | (match_dup 2))) | |
11404 | (clobber (match_scratch:SI 3 ""))] | |
11405 | "! TARGET_POWERPC64 && reload_completed" | |
11406 | [(parallel [(set (match_dup 0) | |
11407 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11408 | (match_dup 2))) | |
11409 | (clobber (match_dup 3))]) | |
11410 | (set (match_dup 4) | |
11411 | (compare:CC (match_dup 0) | |
11412 | (const_int 0)))] | |
11413 | "") | |
1fd4e8c1 | 11414 | |
a260abc9 | 11415 | (define_insn "" |
9ebbca7d | 11416 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11417 | (compare:CC |
11418 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11419 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11420 | (const_int 63)) |
9ebbca7d | 11421 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11422 | (const_int 0))) |
9ebbca7d | 11423 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
11424 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
11425 | (match_dup 2))) | |
9ebbca7d | 11426 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
a260abc9 | 11427 | "TARGET_POWERPC64" |
9ebbca7d GK |
11428 | "@ |
11429 | addic %3,%1,-1\;addze. %0,%2 | |
11430 | #" | |
a260abc9 | 11431 | [(set_attr "type" "compare") |
9ebbca7d GK |
11432 | (set_attr "length" "8,12")]) |
11433 | ||
11434 | (define_split | |
11435 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11436 | (compare:CC | |
11437 | (plus:DI (lshiftrt:DI | |
11438 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11439 | (const_int 63)) | |
11440 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11441 | (const_int 0))) | |
11442 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11443 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11444 | (match_dup 2))) | |
11445 | (clobber (match_scratch:DI 3 ""))] | |
11446 | "TARGET_POWERPC64 && reload_completed" | |
11447 | [(parallel [(set (match_dup 0) | |
11448 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11449 | (match_dup 2))) | |
11450 | (clobber (match_dup 3))]) | |
11451 | (set (match_dup 4) | |
11452 | (compare:CC (match_dup 0) | |
11453 | (const_int 0)))] | |
11454 | "") | |
a260abc9 | 11455 | |
1fd4e8c1 | 11456 | (define_insn "" |
cd2b37d9 RK |
11457 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11458 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
11459 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
11460 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 11461 | "TARGET_POWER" |
1fd4e8c1 | 11462 | "@ |
ca7f5001 | 11463 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 11464 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11465 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11466 | |
11467 | (define_insn "" | |
9ebbca7d | 11468 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11469 | (compare:CC |
9ebbca7d GK |
11470 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11471 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
1fd4e8c1 | 11472 | (const_int 0))) |
9ebbca7d | 11473 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11474 | (le:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11475 | (clobber (match_scratch:SI 3 "=r,X,r,X"))] |
ca7f5001 | 11476 | "TARGET_POWER" |
1fd4e8c1 | 11477 | "@ |
ca7f5001 | 11478 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
9ebbca7d GK |
11479 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 |
11480 | # | |
11481 | #" | |
11482 | [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") | |
11483 | (set_attr "length" "12,12,16,16")]) | |
11484 | ||
11485 | (define_split | |
11486 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11487 | (compare:CC | |
11488 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11489 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11490 | (const_int 0))) | |
11491 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11492 | (le:SI (match_dup 1) (match_dup 2))) | |
11493 | (clobber (match_scratch:SI 3 ""))] | |
11494 | "TARGET_POWER && reload_completed" | |
11495 | [(parallel [(set (match_dup 0) | |
11496 | (le:SI (match_dup 1) (match_dup 2))) | |
11497 | (clobber (match_dup 3))]) | |
11498 | (set (match_dup 4) | |
11499 | (compare:CC (match_dup 0) | |
11500 | (const_int 0)))] | |
11501 | "") | |
1fd4e8c1 RK |
11502 | |
11503 | (define_insn "" | |
cd2b37d9 RK |
11504 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11505 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11506 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
cd2b37d9 | 11507 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11508 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11509 | "TARGET_POWER" |
1fd4e8c1 | 11510 | "@ |
ca7f5001 RK |
11511 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3 |
11512 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3" | |
b19003d8 | 11513 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11514 | |
11515 | (define_insn "" | |
9ebbca7d | 11516 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11517 | (compare:CC |
9ebbca7d GK |
11518 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11519 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
11520 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11521 | (const_int 0))) |
9ebbca7d | 11522 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 11523 | "TARGET_POWER" |
1fd4e8c1 | 11524 | "@ |
ca7f5001 | 11525 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
11526 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 |
11527 | # | |
11528 | #" | |
b19003d8 | 11529 | [(set_attr "type" "compare") |
9ebbca7d GK |
11530 | (set_attr "length" "12,12,16,16")]) |
11531 | ||
11532 | (define_split | |
11533 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11534 | (compare:CC | |
11535 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11536 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11537 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11538 | (const_int 0))) | |
11539 | (clobber (match_scratch:SI 4 ""))] | |
11540 | "TARGET_POWER && reload_completed" | |
11541 | [(set (match_dup 4) | |
11542 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) | |
11543 | (match_dup 3))) | |
11544 | (set (match_dup 0) | |
11545 | (compare:CC (match_dup 4) | |
11546 | (const_int 0)))] | |
11547 | "") | |
1fd4e8c1 RK |
11548 | |
11549 | (define_insn "" | |
9ebbca7d | 11550 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11551 | (compare:CC |
9ebbca7d GK |
11552 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11553 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
11554 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11555 | (const_int 0))) |
9ebbca7d | 11556 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11557 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11558 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 11559 | "TARGET_POWER" |
1fd4e8c1 | 11560 | "@ |
ca7f5001 | 11561 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 |
9ebbca7d GK |
11562 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3 |
11563 | # | |
11564 | #" | |
b19003d8 | 11565 | [(set_attr "type" "compare") |
9ebbca7d GK |
11566 | (set_attr "length" "12,12,16,16")]) |
11567 | ||
11568 | (define_split | |
11569 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11570 | (compare:CC | |
11571 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11572 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11573 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11574 | (const_int 0))) | |
11575 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11576 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11577 | (clobber (match_scratch:SI 4 ""))] | |
11578 | "TARGET_POWER && reload_completed" | |
11579 | [(parallel [(set (match_dup 0) | |
11580 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11581 | (clobber (match_dup 4))]) | |
11582 | (set (match_dup 5) | |
11583 | (compare:CC (match_dup 0) | |
11584 | (const_int 0)))] | |
11585 | "") | |
1fd4e8c1 RK |
11586 | |
11587 | (define_insn "" | |
cd2b37d9 RK |
11588 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11589 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11590 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 11591 | "TARGET_POWER" |
1fd4e8c1 | 11592 | "@ |
ca7f5001 RK |
11593 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
11594 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 11595 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11596 | |
11597 | (define_insn "" | |
cd2b37d9 RK |
11598 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11599 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11600 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
f9562f27 | 11601 | "! TARGET_POWERPC64" |
ca7f5001 | 11602 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
b19003d8 | 11603 | [(set_attr "length" "12")]) |
1fd4e8c1 | 11604 | |
f9562f27 DE |
11605 | (define_insn "" |
11606 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11607 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
11608 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
11609 | "TARGET_POWERPC64" | |
11610 | "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" | |
11611 | [(set_attr "length" "12")]) | |
11612 | ||
11613 | (define_insn "" | |
9ebbca7d | 11614 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 11615 | (compare:CC |
9ebbca7d GK |
11616 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
11617 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 11618 | (const_int 0))) |
9ebbca7d | 11619 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
11620 | (leu:DI (match_dup 1) (match_dup 2)))] |
11621 | "TARGET_POWERPC64" | |
9ebbca7d GK |
11622 | "@ |
11623 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
11624 | #" | |
f9562f27 | 11625 | [(set_attr "type" "compare") |
9ebbca7d GK |
11626 | (set_attr "length" "12,16")]) |
11627 | ||
11628 | (define_split | |
11629 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11630 | (compare:CC | |
11631 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11632 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
11633 | (const_int 0))) | |
11634 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11635 | (leu:DI (match_dup 1) (match_dup 2)))] | |
11636 | "TARGET_POWERPC64 && reload_completed" | |
11637 | [(set (match_dup 0) | |
11638 | (leu:DI (match_dup 1) (match_dup 2))) | |
11639 | (set (match_dup 3) | |
11640 | (compare:CC (match_dup 0) | |
11641 | (const_int 0)))] | |
11642 | "") | |
f9562f27 | 11643 | |
1fd4e8c1 | 11644 | (define_insn "" |
9ebbca7d | 11645 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11646 | (compare:CC |
9ebbca7d GK |
11647 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11648 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11649 | (const_int 0))) |
9ebbca7d | 11650 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11651 | (leu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 11652 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11653 | "@ |
11654 | {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 | |
11655 | #" | |
b19003d8 | 11656 | [(set_attr "type" "compare") |
9ebbca7d GK |
11657 | (set_attr "length" "12,16")]) |
11658 | ||
11659 | (define_split | |
11660 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11661 | (compare:CC | |
11662 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11663 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11664 | (const_int 0))) | |
11665 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11666 | (leu:SI (match_dup 1) (match_dup 2)))] | |
11667 | "! TARGET_POWERPC64 && reload_completed" | |
11668 | [(set (match_dup 0) | |
11669 | (leu:SI (match_dup 1) (match_dup 2))) | |
11670 | (set (match_dup 3) | |
11671 | (compare:CC (match_dup 0) | |
11672 | (const_int 0)))] | |
11673 | "") | |
1fd4e8c1 | 11674 | |
f9562f27 | 11675 | (define_insn "" |
9ebbca7d | 11676 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 11677 | (compare:CC |
9ebbca7d GK |
11678 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
11679 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 11680 | (const_int 0))) |
9ebbca7d | 11681 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
11682 | (leu:DI (match_dup 1) (match_dup 2)))] |
11683 | "TARGET_POWERPC64" | |
9ebbca7d GK |
11684 | "@ |
11685 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
11686 | #" | |
f9562f27 | 11687 | [(set_attr "type" "compare") |
9ebbca7d | 11688 | (set_attr "length" "12,16")]) |
f9562f27 | 11689 | |
1fd4e8c1 | 11690 | (define_insn "" |
cd2b37d9 RK |
11691 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11692 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11693 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 11694 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11695 | (clobber (match_scratch:SI 4 "=&r"))] |
f9562f27 | 11696 | "! TARGET_POWERPC64" |
ca7f5001 | 11697 | "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3" |
b19003d8 | 11698 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
11699 | |
11700 | (define_insn "" | |
9ebbca7d | 11701 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11702 | (compare:CC |
9ebbca7d GK |
11703 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11704 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11705 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11706 | (const_int 0))) |
9ebbca7d | 11707 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11708 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11709 | "@ |
11710 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 | |
11711 | #" | |
b19003d8 | 11712 | [(set_attr "type" "compare") |
9ebbca7d GK |
11713 | (set_attr "length" "8,12")]) |
11714 | ||
11715 | (define_split | |
11716 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11717 | (compare:CC | |
11718 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11719 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11720 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11721 | (const_int 0))) | |
11722 | (clobber (match_scratch:SI 4 ""))] | |
11723 | "! TARGET_POWERPC64 && reload_completed" | |
11724 | [(set (match_dup 4) | |
11725 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) | |
11726 | (match_dup 3))) | |
11727 | (set (match_dup 0) | |
11728 | (compare:CC (match_dup 4) | |
11729 | (const_int 0)))] | |
11730 | "") | |
1fd4e8c1 RK |
11731 | |
11732 | (define_insn "" | |
9ebbca7d | 11733 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11734 | (compare:CC |
9ebbca7d GK |
11735 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11736 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11737 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11738 | (const_int 0))) |
9ebbca7d | 11739 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11740 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11741 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11742 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11743 | "@ |
11744 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3 | |
11745 | #" | |
b19003d8 | 11746 | [(set_attr "type" "compare") |
9ebbca7d GK |
11747 | (set_attr "length" "8,12")]) |
11748 | ||
11749 | (define_split | |
11750 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11751 | (compare:CC | |
11752 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11753 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11754 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11755 | (const_int 0))) | |
11756 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11757 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11758 | (clobber (match_scratch:SI 4 ""))] | |
11759 | "! TARGET_POWERPC64 && reload_completed" | |
11760 | [(parallel [(set (match_dup 0) | |
11761 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11762 | (clobber (match_dup 4))]) | |
11763 | (set (match_dup 5) | |
11764 | (compare:CC (match_dup 0) | |
11765 | (const_int 0)))] | |
11766 | "") | |
1fd4e8c1 RK |
11767 | |
11768 | (define_insn "" | |
cd2b37d9 RK |
11769 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11770 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11771 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
f9562f27 | 11772 | "! TARGET_POWERPC64" |
ca7f5001 | 11773 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
b19003d8 | 11774 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11775 | |
11776 | (define_insn "" | |
cd2b37d9 | 11777 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 11778 | (and:SI (neg:SI |
cd2b37d9 | 11779 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11780 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
cd2b37d9 | 11781 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11782 | (clobber (match_scratch:SI 4 "=&r"))] |
f9562f27 | 11783 | "! TARGET_POWERPC64" |
ca7f5001 | 11784 | "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" |
b19003d8 | 11785 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11786 | |
11787 | (define_insn "" | |
9ebbca7d | 11788 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11789 | (compare:CC |
11790 | (and:SI (neg:SI | |
9ebbca7d GK |
11791 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11792 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
11793 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11794 | (const_int 0))) |
9ebbca7d | 11795 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11796 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11797 | "@ |
11798 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 | |
11799 | #" | |
11800 | [(set_attr "type" "compare") | |
11801 | (set_attr "length" "12,16")]) | |
11802 | ||
11803 | (define_split | |
11804 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11805 | (compare:CC | |
11806 | (and:SI (neg:SI | |
11807 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11808 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
11809 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11810 | (const_int 0))) | |
11811 | (clobber (match_scratch:SI 4 ""))] | |
11812 | "! TARGET_POWERPC64 && reload_completed" | |
11813 | [(set (match_dup 4) | |
11814 | (and:SI (neg:SI (leu:SI (match_dup 1) | |
11815 | (match_dup 2))) | |
11816 | (match_dup 3))) | |
11817 | (set (match_dup 0) | |
11818 | (compare:CC (match_dup 4) | |
11819 | (const_int 0)))] | |
11820 | "") | |
1fd4e8c1 RK |
11821 | |
11822 | (define_insn "" | |
9ebbca7d | 11823 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11824 | (compare:CC |
11825 | (and:SI (neg:SI | |
9ebbca7d GK |
11826 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11827 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
11828 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11829 | (const_int 0))) |
9ebbca7d | 11830 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11831 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
9ebbca7d | 11832 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 11833 | "! TARGET_POWERPC64" |
9ebbca7d GK |
11834 | "@ |
11835 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 | |
11836 | #" | |
b19003d8 | 11837 | [(set_attr "type" "compare") |
9ebbca7d GK |
11838 | (set_attr "length" "12,16")]) |
11839 | ||
11840 | (define_split | |
11841 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11842 | (compare:CC | |
11843 | (and:SI (neg:SI | |
11844 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11845 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
11846 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11847 | (const_int 0))) | |
11848 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11849 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
11850 | (clobber (match_scratch:SI 4 ""))] | |
11851 | "! TARGET_POWERPC64 && reload_completed" | |
11852 | [(parallel [(set (match_dup 0) | |
11853 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
11854 | (clobber (match_dup 4))]) | |
11855 | (set (match_dup 5) | |
11856 | (compare:CC (match_dup 0) | |
11857 | (const_int 0)))] | |
11858 | "") | |
1fd4e8c1 RK |
11859 | |
11860 | (define_insn "" | |
cd2b37d9 RK |
11861 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11862 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11863 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 11864 | "TARGET_POWER" |
7f340546 | 11865 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11866 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11867 | |
11868 | (define_insn "" | |
9ebbca7d | 11869 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11870 | (compare:CC |
9ebbca7d GK |
11871 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11872 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11873 | (const_int 0))) |
9ebbca7d | 11874 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11875 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 11876 | "TARGET_POWER" |
9ebbca7d GK |
11877 | "@ |
11878 | doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
11879 | #" | |
29ae5b89 | 11880 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11881 | (set_attr "length" "12,16")]) |
11882 | ||
11883 | (define_split | |
11884 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11885 | (compare:CC | |
11886 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11887 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11888 | (const_int 0))) | |
11889 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11890 | (lt:SI (match_dup 1) (match_dup 2)))] | |
11891 | "TARGET_POWER && reload_completed" | |
11892 | [(set (match_dup 0) | |
11893 | (lt:SI (match_dup 1) (match_dup 2))) | |
11894 | (set (match_dup 3) | |
11895 | (compare:CC (match_dup 0) | |
11896 | (const_int 0)))] | |
11897 | "") | |
1fd4e8c1 RK |
11898 | |
11899 | (define_insn "" | |
cd2b37d9 RK |
11900 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11901 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11902 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 11903 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11904 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
11905 | "TARGET_POWER" |
11906 | "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" | |
b19003d8 | 11907 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11908 | |
11909 | (define_insn "" | |
9ebbca7d | 11910 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11911 | (compare:CC |
9ebbca7d GK |
11912 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11913 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11914 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11915 | (const_int 0))) |
9ebbca7d | 11916 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11917 | "TARGET_POWER" |
9ebbca7d GK |
11918 | "@ |
11919 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
11920 | #" | |
b19003d8 | 11921 | [(set_attr "type" "compare") |
9ebbca7d GK |
11922 | (set_attr "length" "12,16")]) |
11923 | ||
11924 | (define_split | |
11925 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11926 | (compare:CC | |
11927 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11928 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11929 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11930 | (const_int 0))) | |
11931 | (clobber (match_scratch:SI 4 ""))] | |
11932 | "TARGET_POWER && reload_completed" | |
11933 | [(set (match_dup 4) | |
11934 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) | |
11935 | (match_dup 3))) | |
11936 | (set (match_dup 0) | |
11937 | (compare:CC (match_dup 4) | |
11938 | (const_int 0)))] | |
11939 | "") | |
1fd4e8c1 RK |
11940 | |
11941 | (define_insn "" | |
9ebbca7d | 11942 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11943 | (compare:CC |
9ebbca7d GK |
11944 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11945 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11946 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11947 | (const_int 0))) |
9ebbca7d | 11948 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11949 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 11950 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 11951 | "TARGET_POWER" |
9ebbca7d GK |
11952 | "@ |
11953 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3 | |
11954 | #" | |
b19003d8 | 11955 | [(set_attr "type" "compare") |
9ebbca7d GK |
11956 | (set_attr "length" "12,16")]) |
11957 | ||
11958 | (define_split | |
11959 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
11960 | (compare:CC | |
11961 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11962 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11963 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11964 | (const_int 0))) | |
11965 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11966 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11967 | (clobber (match_scratch:SI 4 ""))] | |
11968 | "TARGET_POWER && reload_completed" | |
11969 | [(parallel [(set (match_dup 0) | |
11970 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
11971 | (clobber (match_dup 4))]) | |
11972 | (set (match_dup 5) | |
11973 | (compare:CC (match_dup 0) | |
11974 | (const_int 0)))] | |
11975 | "") | |
1fd4e8c1 RK |
11976 | |
11977 | (define_insn "" | |
cd2b37d9 RK |
11978 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11979 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11980 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
11981 | "TARGET_POWER" |
11982 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 11983 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11984 | |
11985 | (define_insn "" | |
cd2b37d9 RK |
11986 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11987 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11988 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
f9562f27 | 11989 | "! TARGET_POWERPC64" |
1fd4e8c1 | 11990 | "@ |
ca7f5001 RK |
11991 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0 |
11992 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" | |
b19003d8 | 11993 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11994 | |
11995 | (define_insn "" | |
9ebbca7d | 11996 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11997 | (compare:CC |
9ebbca7d GK |
11998 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11999 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12000 | (const_int 0))) |
9ebbca7d | 12001 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12002 | (ltu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 12003 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12004 | "@ |
ca7f5001 | 12005 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
9ebbca7d GK |
12006 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
12007 | # | |
12008 | #" | |
b19003d8 | 12009 | [(set_attr "type" "compare") |
9ebbca7d GK |
12010 | (set_attr "length" "12,12,16,16")]) |
12011 | ||
12012 | (define_split | |
12013 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12014 | (compare:CC | |
12015 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12016 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12017 | (const_int 0))) | |
12018 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12019 | (ltu:SI (match_dup 1) (match_dup 2)))] | |
12020 | "! TARGET_POWERPC64 && reload_completed" | |
12021 | [(set (match_dup 0) | |
12022 | (ltu:SI (match_dup 1) (match_dup 2))) | |
12023 | (set (match_dup 3) | |
12024 | (compare:CC (match_dup 0) | |
12025 | (const_int 0)))] | |
12026 | "") | |
1fd4e8c1 RK |
12027 | |
12028 | (define_insn "" | |
19378cf8 MM |
12029 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12030 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
12031 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
12032 | (match_operand:SI 3 "reg_or_short_operand" "rI,rI"))) | |
12033 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
f9562f27 | 12034 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12035 | "@ |
ca7f5001 | 12036 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3 |
04be6346 | 12037 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" |
b19003d8 | 12038 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12039 | |
12040 | (define_insn "" | |
9ebbca7d | 12041 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12042 | (compare:CC |
9ebbca7d GK |
12043 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12044 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12045 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12046 | (const_int 0))) |
9ebbca7d | 12047 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12048 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12049 | "@ |
ca7f5001 | 12050 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
9ebbca7d GK |
12051 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
12052 | # | |
12053 | #" | |
b19003d8 | 12054 | [(set_attr "type" "compare") |
9ebbca7d GK |
12055 | (set_attr "length" "12,12,16,16")]) |
12056 | ||
12057 | (define_split | |
12058 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12059 | (compare:CC | |
12060 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12061 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12062 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12063 | (const_int 0))) | |
12064 | (clobber (match_scratch:SI 4 ""))] | |
12065 | "! TARGET_POWERPC64 && reload_completed" | |
12066 | [(set (match_dup 4) | |
12067 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) | |
12068 | (match_dup 3))) | |
12069 | (set (match_dup 0) | |
12070 | (compare:CC (match_dup 4) | |
12071 | (const_int 0)))] | |
12072 | "") | |
1fd4e8c1 RK |
12073 | |
12074 | (define_insn "" | |
9ebbca7d | 12075 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12076 | (compare:CC |
9ebbca7d GK |
12077 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12078 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12079 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12080 | (const_int 0))) |
9ebbca7d | 12081 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12082 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 12083 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12084 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12085 | "@ |
ca7f5001 | 12086 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
9ebbca7d GK |
12087 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
12088 | # | |
12089 | #" | |
b19003d8 | 12090 | [(set_attr "type" "compare") |
9ebbca7d GK |
12091 | (set_attr "length" "12,12,16,16")]) |
12092 | ||
12093 | (define_split | |
12094 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
12095 | (compare:CC | |
12096 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12097 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12098 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12099 | (const_int 0))) | |
12100 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12101 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12102 | (clobber (match_scratch:SI 4 ""))] | |
12103 | "! TARGET_POWERPC64 && reload_completed" | |
12104 | [(parallel [(set (match_dup 0) | |
12105 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12106 | (clobber (match_dup 4))]) | |
12107 | (set (match_dup 5) | |
12108 | (compare:CC (match_dup 0) | |
12109 | (const_int 0)))] | |
12110 | "") | |
1fd4e8c1 RK |
12111 | |
12112 | (define_insn "" | |
cd2b37d9 RK |
12113 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12114 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12115 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
f9562f27 | 12116 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12117 | "@ |
ca7f5001 RK |
12118 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
12119 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 12120 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
12121 | |
12122 | (define_insn "" | |
cd2b37d9 RK |
12123 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12124 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
12125 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
12126 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
12127 | "TARGET_POWER" |
12128 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 12129 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12130 | |
12131 | (define_insn "" | |
9ebbca7d GK |
12132 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12133 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
12134 | (const_int 0)))] | |
12135 | "! TARGET_POWER && ! TARGET_POWERPC64" | |
12136 | "nand %0,%1,%1\;{sri|srwi} %0,%0,31" | |
12137 | [(set_attr "length" "8")]) | |
12138 | ||
12139 | (define_insn "" | |
12140 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12141 | (ge:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12142 | (const_int 0)))] | |
12143 | "TARGET_POWERPC64" | |
12144 | "nand %0,%1,%1\;srdi %0,%0,63" | |
12145 | [(set_attr "length" "8")]) | |
12146 | ||
12147 | (define_insn "" | |
12148 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 12149 | (compare:CC |
9ebbca7d GK |
12150 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12151 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12152 | (const_int 0))) |
9ebbca7d | 12153 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12154 | (ge:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 12155 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 12156 | "TARGET_POWER" |
9ebbca7d GK |
12157 | "@ |
12158 | doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 | |
12159 | #" | |
12160 | [(set_attr "type" "compare") | |
12161 | (set_attr "length" "12,16")]) | |
12162 | ||
12163 | (define_split | |
12164 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12165 | (compare:CC | |
12166 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12167 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12168 | (const_int 0))) | |
12169 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12170 | (ge:SI (match_dup 1) (match_dup 2))) | |
12171 | (clobber (match_scratch:SI 3 ""))] | |
12172 | "TARGET_POWER && reload_completed" | |
12173 | [(parallel [(set (match_dup 0) | |
12174 | (ge:SI (match_dup 1) (match_dup 2))) | |
12175 | (clobber (match_dup 3))]) | |
12176 | (set (match_dup 4) | |
12177 | (compare:CC (match_dup 0) | |
12178 | (const_int 0)))] | |
12179 | "") | |
12180 | ||
12181 | (define_insn "" | |
12182 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
12183 | (compare:CC | |
12184 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
12185 | (const_int 0)) | |
12186 | (const_int 0))) | |
12187 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
12188 | (ge:SI (match_dup 1) (const_int 0)))] | |
12189 | "! TARGET_POWER" | |
12190 | "@ | |
12191 | nand %0,%1,%1\;{sri.|srwi.} %0,%0,31 | |
12192 | #" | |
12193 | [(set_attr "type" "compare") | |
12194 | (set_attr "length" "8,12")]) | |
12195 | ||
12196 | (define_split | |
12197 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12198 | (compare:CC | |
12199 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12200 | (const_int 0)) | |
12201 | (const_int 0))) | |
12202 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12203 | (ge:SI (match_dup 1) (const_int 0)))] | |
12204 | "! TARGET_POWER && reload_completed" | |
12205 | [(set (match_dup 0) | |
12206 | (ge:SI (match_dup 1) (const_int 0))) | |
12207 | (set (match_dup 4) | |
12208 | (compare:CC (match_dup 0) | |
12209 | (const_int 0)))] | |
12210 | "") | |
12211 | ||
12212 | (define_insn "" | |
12213 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
12214 | (compare:CC | |
12215 | (ge:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12216 | (const_int 0)) | |
12217 | (const_int 0))) | |
12218 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12219 | (ge:DI (match_dup 1) (const_int 0)))] | |
12220 | "TARGET_POWERPC64" | |
12221 | "@ | |
12222 | nand %0,%1,%1\;srdi. %0,%0,63 | |
12223 | #" | |
b19003d8 | 12224 | [(set_attr "type" "compare") |
9ebbca7d GK |
12225 | (set_attr "length" "8,12")]) |
12226 | ||
12227 | (define_split | |
12228 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12229 | (compare:CC | |
12230 | (ge:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12231 | (const_int 0)) | |
12232 | (const_int 0))) | |
12233 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12234 | (ge:DI (match_dup 1) (const_int 0)))] | |
12235 | "TARGET_POWERPC64 && reload_completed" | |
12236 | [(set (match_dup 0) | |
12237 | (ge:DI (match_dup 1) (const_int 0))) | |
12238 | (set (match_dup 4) | |
12239 | (compare:CC (match_dup 0) | |
12240 | (const_int 0)))] | |
12241 | "") | |
1fd4e8c1 RK |
12242 | |
12243 | (define_insn "" | |
cd2b37d9 RK |
12244 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12245 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12246 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
cd2b37d9 | 12247 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 12248 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
12249 | "TARGET_POWER" |
12250 | "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3" | |
b19003d8 | 12251 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12252 | |
12253 | (define_insn "" | |
9ebbca7d | 12254 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12255 | (compare:CC |
9ebbca7d GK |
12256 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12257 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12258 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12259 | (const_int 0))) |
9ebbca7d | 12260 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12261 | "TARGET_POWER" |
9ebbca7d GK |
12262 | "@ |
12263 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
12264 | #" | |
b19003d8 | 12265 | [(set_attr "type" "compare") |
9ebbca7d GK |
12266 | (set_attr "length" "12,16")]) |
12267 | ||
12268 | (define_split | |
12269 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12270 | (compare:CC | |
12271 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12272 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12273 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12274 | (const_int 0))) | |
12275 | (clobber (match_scratch:SI 4 ""))] | |
12276 | "TARGET_POWER && reload_completed" | |
12277 | [(set (match_dup 4) | |
12278 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) | |
12279 | (match_dup 3))) | |
12280 | (set (match_dup 0) | |
12281 | (compare:CC (match_dup 4) | |
12282 | (const_int 0)))] | |
12283 | "") | |
1fd4e8c1 RK |
12284 | |
12285 | (define_insn "" | |
9ebbca7d | 12286 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12287 | (compare:CC |
9ebbca7d GK |
12288 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12289 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12290 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12291 | (const_int 0))) |
9ebbca7d | 12292 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12293 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 12294 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12295 | "TARGET_POWER" |
9ebbca7d GK |
12296 | "@ |
12297 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3 | |
12298 | #" | |
b19003d8 | 12299 | [(set_attr "type" "compare") |
9ebbca7d GK |
12300 | (set_attr "length" "12,16")]) |
12301 | ||
12302 | (define_split | |
12303 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
12304 | (compare:CC | |
12305 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12306 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12307 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12308 | (const_int 0))) | |
12309 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12310 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12311 | (clobber (match_scratch:SI 4 ""))] | |
12312 | "TARGET_POWER && reload_completed" | |
12313 | [(parallel [(set (match_dup 0) | |
12314 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12315 | (clobber (match_dup 4))]) | |
12316 | (set (match_dup 5) | |
12317 | (compare:CC (match_dup 0) | |
12318 | (const_int 0)))] | |
12319 | "") | |
1fd4e8c1 RK |
12320 | |
12321 | (define_insn "" | |
cd2b37d9 RK |
12322 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12323 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12324 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12325 | "TARGET_POWER" |
12326 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 12327 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12328 | |
12329 | ;; This is (and (neg (ge X (const_int 0))) Y). | |
f9562f27 | 12330 | ;; srawi sign-extends, so these patterrns are 64-bit safe. |
1fd4e8c1 | 12331 | (define_insn "" |
cd2b37d9 | 12332 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
12333 | (and:SI (neg:SI |
12334 | (lshiftrt:SI | |
cd2b37d9 | 12335 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 12336 | (const_int 31))) |
cd2b37d9 | 12337 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 RK |
12338 | (clobber (match_scratch:SI 3 "=&r"))] |
12339 | "" | |
ca7f5001 | 12340 | "{srai|srawi} %3,%1,31\;andc %0,%2,%3" |
b19003d8 | 12341 | [(set_attr "length" "8")]) |
1fd4e8c1 | 12342 | |
f9562f27 DE |
12343 | (define_insn "" |
12344 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12345 | (and:DI (neg:DI | |
12346 | (lshiftrt:DI | |
12347 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
12348 | (const_int 63))) | |
12349 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
12350 | (clobber (match_scratch:DI 3 "=&r"))] | |
12351 | "TARGET_POWERPC64" | |
12352 | "sradi %3,%1,63\;andc %0,%2,%3" | |
12353 | [(set_attr "length" "8")]) | |
12354 | ||
1fd4e8c1 | 12355 | (define_insn "" |
9ebbca7d | 12356 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12357 | (compare:CC |
12358 | (and:SI (neg:SI | |
12359 | (lshiftrt:SI | |
9ebbca7d | 12360 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 12361 | (const_int 31))) |
9ebbca7d | 12362 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 12363 | (const_int 0))) |
9ebbca7d | 12364 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
1fd4e8c1 | 12365 | "" |
9ebbca7d GK |
12366 | "@ |
12367 | {srai|srawi} %3,%1,31\;andc. %3,%2,%3 | |
12368 | #" | |
b19003d8 | 12369 | [(set_attr "type" "compare") |
9ebbca7d GK |
12370 | (set_attr "length" "8,12")]) |
12371 | ||
12372 | (define_split | |
12373 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12374 | (compare:CC | |
12375 | (and:SI (neg:SI | |
12376 | (lshiftrt:SI | |
12377 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
12378 | (const_int 31))) | |
12379 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
12380 | (const_int 0))) | |
12381 | (clobber (match_scratch:SI 3 ""))] | |
12382 | "reload_completed" | |
12383 | [(set (match_dup 3) | |
12384 | (and:SI (neg:SI (lshiftrt:SI | |
12385 | (not:SI (match_dup 1)) | |
12386 | (const_int 31))) | |
12387 | (match_dup 2))) | |
12388 | (set (match_dup 0) | |
12389 | (compare:CC (match_dup 3) | |
12390 | (const_int 0)))] | |
12391 | "") | |
1fd4e8c1 | 12392 | |
f9562f27 | 12393 | (define_insn "" |
9ebbca7d | 12394 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
f9562f27 DE |
12395 | (compare:CC |
12396 | (and:DI (neg:DI | |
12397 | (lshiftrt:DI | |
9ebbca7d | 12398 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) |
f9562f27 | 12399 | (const_int 63))) |
9ebbca7d | 12400 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 12401 | (const_int 0))) |
9ebbca7d | 12402 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
f9562f27 | 12403 | "TARGET_POWERPC64" |
9ebbca7d GK |
12404 | "@ |
12405 | sradi %3,%1,63\;andc. %3,%2,%3 | |
12406 | #" | |
f9562f27 | 12407 | [(set_attr "type" "compare") |
9ebbca7d GK |
12408 | (set_attr "length" "8,12")]) |
12409 | ||
12410 | (define_split | |
12411 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12412 | (compare:CC | |
12413 | (and:DI (neg:DI | |
12414 | (lshiftrt:DI | |
12415 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
12416 | (const_int 63))) | |
12417 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
12418 | (const_int 0))) | |
12419 | (clobber (match_scratch:DI 3 ""))] | |
12420 | "TARGET_POWERPC64 && reload_completed" | |
12421 | [(set (match_dup 3) | |
12422 | (and:DI (neg:DI (lshiftrt:DI | |
12423 | (not:DI (match_dup 1)) | |
12424 | (const_int 63))) | |
12425 | (match_dup 2))) | |
12426 | (set (match_dup 0) | |
12427 | (compare:CC (match_dup 3) | |
12428 | (const_int 0)))] | |
12429 | "") | |
f9562f27 | 12430 | |
1fd4e8c1 | 12431 | (define_insn "" |
9ebbca7d GK |
12432 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
12433 | (compare:CC | |
12434 | (and:SI (neg:SI | |
12435 | (lshiftrt:SI | |
12436 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
12437 | (const_int 31))) | |
12438 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
12439 | (const_int 0))) | |
12440 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
12441 | (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1)) | |
12442 | (const_int 31))) | |
12443 | (match_dup 2))) | |
12444 | (clobber (match_scratch:SI 3 "=&r,&r"))] | |
12445 | "" | |
12446 | "@ | |
12447 | {srai|srawi} %3,%1,31\;andc. %0,%2,%3 | |
12448 | #" | |
12449 | [(set_attr "type" "compare") | |
12450 | (set_attr "length" "8,12")]) | |
12451 | ||
12452 | (define_split | |
12453 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
1fd4e8c1 RK |
12454 | (compare:CC |
12455 | (and:SI (neg:SI | |
12456 | (lshiftrt:SI | |
9ebbca7d | 12457 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
1fd4e8c1 | 12458 | (const_int 31))) |
9ebbca7d | 12459 | (match_operand:SI 2 "gpc_reg_operand" "")) |
1fd4e8c1 | 12460 | (const_int 0))) |
9ebbca7d | 12461 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
12462 | (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1)) |
12463 | (const_int 31))) | |
12464 | (match_dup 2))) | |
9ebbca7d GK |
12465 | (clobber (match_scratch:SI 3 ""))] |
12466 | "reload_completed" | |
12467 | [(parallel [(set (match_dup 0) | |
12468 | (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1)) | |
12469 | (const_int 31))) | |
12470 | (match_dup 2))) | |
12471 | (clobber (match_dup 3))]) | |
12472 | (set (match_dup 4) | |
12473 | (compare:CC (match_dup 0) | |
12474 | (const_int 0)))] | |
12475 | "") | |
1fd4e8c1 | 12476 | |
f9562f27 | 12477 | (define_insn "" |
9ebbca7d | 12478 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
f9562f27 DE |
12479 | (compare:CC |
12480 | (and:DI (neg:DI | |
12481 | (lshiftrt:DI | |
9ebbca7d | 12482 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) |
f9562f27 | 12483 | (const_int 63))) |
9ebbca7d | 12484 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 12485 | (const_int 0))) |
9ebbca7d | 12486 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
12487 | (and:DI (neg:DI (lshiftrt:SI (not:DI (match_dup 1)) |
12488 | (const_int 63))) | |
12489 | (match_dup 2))) | |
9ebbca7d | 12490 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 12491 | "TARGET_POWERPC64" |
9ebbca7d GK |
12492 | "@ |
12493 | sradi %3,%1,63\;andc. %0,%2,%3 | |
12494 | #" | |
f9562f27 | 12495 | [(set_attr "type" "compare") |
9ebbca7d GK |
12496 | (set_attr "length" "8,12")]) |
12497 | ||
12498 | (define_split | |
12499 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12500 | (compare:CC | |
12501 | (and:DI (neg:DI | |
12502 | (lshiftrt:DI | |
12503 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
12504 | (const_int 63))) | |
12505 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
12506 | (const_int 0))) | |
12507 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12508 | (and:DI (neg:DI (lshiftrt:SI (not:DI (match_dup 1)) | |
12509 | (const_int 63))) | |
12510 | (match_dup 2))) | |
12511 | (clobber (match_scratch:SI 3 ""))] | |
12512 | "TARGET_POWERPC64 && reload_completed" | |
12513 | [(parallel [(set (match_dup 0) | |
12514 | (and:DI (neg:DI (lshiftrt:SI (not:DI (match_dup 1)) | |
12515 | (const_int 63))) | |
12516 | (match_dup 2))) | |
12517 | (clobber (match_dup 3))]) | |
12518 | (set (match_dup 4) | |
12519 | (compare:CC (match_dup 0) | |
12520 | (const_int 0)))] | |
12521 | "") | |
f9562f27 | 12522 | |
1fd4e8c1 | 12523 | (define_insn "" |
cd2b37d9 RK |
12524 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12525 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12526 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
f9562f27 | 12527 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12528 | "@ |
ca7f5001 RK |
12529 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
12530 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
b19003d8 | 12531 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12532 | |
f9562f27 DE |
12533 | (define_insn "" |
12534 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12535 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12536 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
12537 | "TARGET_POWERPC64" | |
12538 | "@ | |
12539 | subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 | |
12540 | addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" | |
12541 | [(set_attr "length" "12")]) | |
12542 | ||
1fd4e8c1 | 12543 | (define_insn "" |
9ebbca7d | 12544 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12545 | (compare:CC |
9ebbca7d GK |
12546 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12547 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12548 | (const_int 0))) |
9ebbca7d | 12549 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12550 | (geu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 12551 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12552 | "@ |
ca7f5001 | 12553 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
9ebbca7d GK |
12554 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
12555 | # | |
12556 | #" | |
b19003d8 | 12557 | [(set_attr "type" "compare") |
9ebbca7d GK |
12558 | (set_attr "length" "12,12,16,16")]) |
12559 | ||
12560 | (define_split | |
12561 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12562 | (compare:CC | |
12563 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12564 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12565 | (const_int 0))) | |
12566 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12567 | (geu:SI (match_dup 1) (match_dup 2)))] | |
12568 | "! TARGET_POWERPC64 && reload_completed" | |
12569 | [(set (match_dup 0) | |
12570 | (geu:SI (match_dup 1) (match_dup 2))) | |
12571 | (set (match_dup 3) | |
12572 | (compare:CC (match_dup 0) | |
12573 | (const_int 0)))] | |
12574 | "") | |
1fd4e8c1 | 12575 | |
f9562f27 | 12576 | (define_insn "" |
9ebbca7d | 12577 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12578 | (compare:CC |
9ebbca7d GK |
12579 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12580 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
f9562f27 | 12581 | (const_int 0))) |
9ebbca7d | 12582 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 DE |
12583 | (geu:DI (match_dup 1) (match_dup 2)))] |
12584 | "TARGET_POWERPC64" | |
12585 | "@ | |
12586 | subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 | |
9ebbca7d GK |
12587 | addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 |
12588 | # | |
12589 | #" | |
f9562f27 | 12590 | [(set_attr "type" "compare") |
9ebbca7d GK |
12591 | (set_attr "length" "12,12,16,16")]) |
12592 | ||
12593 | (define_split | |
12594 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12595 | (compare:CC | |
12596 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12597 | (match_operand:DI 2 "reg_or_neg_short_operand" "")) | |
12598 | (const_int 0))) | |
12599 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12600 | (geu:DI (match_dup 1) (match_dup 2)))] | |
12601 | "TARGET_POWERPC64 && reload_completed" | |
12602 | [(set (match_dup 0) | |
12603 | (geu:DI (match_dup 1) (match_dup 2))) | |
12604 | (set (match_dup 3) | |
12605 | (compare:CC (match_dup 0) | |
12606 | (const_int 0)))] | |
12607 | "") | |
f9562f27 | 12608 | |
1fd4e8c1 | 12609 | (define_insn "" |
cd2b37d9 RK |
12610 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12611 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12612 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
cd2b37d9 | 12613 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 12614 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 12615 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12616 | "@ |
ca7f5001 RK |
12617 | {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3 |
12618 | {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3" | |
b19003d8 | 12619 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
12620 | |
12621 | (define_insn "" | |
9ebbca7d | 12622 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12623 | (compare:CC |
9ebbca7d GK |
12624 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12625 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12626 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12627 | (const_int 0))) |
9ebbca7d | 12628 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12629 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12630 | "@ |
ca7f5001 | 12631 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12632 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 |
12633 | # | |
12634 | #" | |
b19003d8 | 12635 | [(set_attr "type" "compare") |
9ebbca7d GK |
12636 | (set_attr "length" "8,8,12,12")]) |
12637 | ||
12638 | (define_split | |
12639 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12640 | (compare:CC | |
12641 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12642 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12643 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12644 | (const_int 0))) | |
12645 | (clobber (match_scratch:SI 4 ""))] | |
12646 | "! TARGET_POWERPC64 && reload_completed" | |
12647 | [(set (match_dup 4) | |
12648 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) | |
12649 | (match_dup 3))) | |
12650 | (set (match_dup 0) | |
12651 | (compare:CC (match_dup 4) | |
12652 | (const_int 0)))] | |
12653 | "") | |
1fd4e8c1 RK |
12654 | |
12655 | (define_insn "" | |
9ebbca7d | 12656 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12657 | (compare:CC |
9ebbca7d GK |
12658 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12659 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12660 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12661 | (const_int 0))) |
9ebbca7d | 12662 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12663 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 12664 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12665 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12666 | "@ |
ca7f5001 | 12667 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3 |
9ebbca7d GK |
12668 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %0,%3 |
12669 | # | |
12670 | #" | |
b19003d8 | 12671 | [(set_attr "type" "compare") |
9ebbca7d GK |
12672 | (set_attr "length" "8,8,12,12")]) |
12673 | ||
12674 | (define_split | |
12675 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
12676 | (compare:CC | |
12677 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12678 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12679 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12680 | (const_int 0))) | |
12681 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12682 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12683 | (clobber (match_scratch:SI 4 ""))] | |
12684 | "! TARGET_POWERPC64 && reload_completed" | |
12685 | [(parallel [(set (match_dup 0) | |
12686 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
12687 | (clobber (match_dup 4))]) | |
12688 | (set (match_dup 5) | |
12689 | (compare:CC (match_dup 0) | |
12690 | (const_int 0)))] | |
12691 | "") | |
1fd4e8c1 RK |
12692 | |
12693 | (define_insn "" | |
cd2b37d9 RK |
12694 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12695 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12696 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
f9562f27 | 12697 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12698 | "@ |
ca7f5001 | 12699 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 12700 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 12701 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12702 | |
12703 | (define_insn "" | |
cd2b37d9 | 12704 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12705 | (and:SI (neg:SI |
cd2b37d9 | 12706 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12707 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
cd2b37d9 | 12708 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 12709 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
f9562f27 | 12710 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12711 | "@ |
ca7f5001 RK |
12712 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4 |
12713 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4" | |
b19003d8 | 12714 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12715 | |
12716 | (define_insn "" | |
9ebbca7d | 12717 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12718 | (compare:CC |
12719 | (and:SI (neg:SI | |
9ebbca7d GK |
12720 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12721 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12722 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12723 | (const_int 0))) |
9ebbca7d | 12724 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12725 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12726 | "@ |
ca7f5001 | 12727 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
9ebbca7d GK |
12728 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
12729 | # | |
12730 | #" | |
b19003d8 | 12731 | [(set_attr "type" "compare") |
9ebbca7d GK |
12732 | (set_attr "length" "12,12,16,16")]) |
12733 | ||
12734 | (define_split | |
12735 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12736 | (compare:CC | |
12737 | (and:SI (neg:SI | |
12738 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12739 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
12740 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12741 | (const_int 0))) | |
12742 | (clobber (match_scratch:SI 4 ""))] | |
12743 | "! TARGET_POWERPC64 && reload_completed" | |
12744 | [(set (match_dup 4) | |
12745 | (and:SI (neg:SI (geu:SI (match_dup 1) | |
12746 | (match_dup 2))) | |
12747 | (match_dup 3))) | |
12748 | (set (match_dup 0) | |
12749 | (compare:CC (match_dup 4) | |
12750 | (const_int 0)))] | |
12751 | "") | |
1fd4e8c1 RK |
12752 | |
12753 | (define_insn "" | |
9ebbca7d | 12754 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12755 | (compare:CC |
12756 | (and:SI (neg:SI | |
9ebbca7d GK |
12757 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12758 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12759 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12760 | (const_int 0))) |
9ebbca7d | 12761 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12762 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
9ebbca7d | 12763 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 12764 | "! TARGET_POWERPC64" |
1fd4e8c1 | 12765 | "@ |
ca7f5001 | 12766 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 |
9ebbca7d GK |
12767 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4 |
12768 | # | |
12769 | #" | |
b19003d8 | 12770 | [(set_attr "type" "compare") |
9ebbca7d GK |
12771 | (set_attr "length" "12,12,16,16")]) |
12772 | ||
12773 | (define_split | |
12774 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
12775 | (compare:CC | |
12776 | (and:SI (neg:SI | |
12777 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12778 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
12779 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12780 | (const_int 0))) | |
12781 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12782 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
12783 | (clobber (match_scratch:SI 4 ""))] | |
12784 | "! TARGET_POWERPC64 && reload_completed" | |
12785 | [(parallel [(set (match_dup 0) | |
12786 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) | |
12787 | (clobber (match_dup 4))]) | |
12788 | (set (match_dup 5) | |
12789 | (compare:CC (match_dup 0) | |
12790 | (const_int 0)))] | |
12791 | "") | |
1fd4e8c1 RK |
12792 | |
12793 | (define_insn "" | |
cd2b37d9 RK |
12794 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12795 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12796 | (const_int 0)))] |
f9562f27 | 12797 | "! TARGET_POWERPC64" |
ca7f5001 | 12798 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 12799 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12800 | |
f9562f27 DE |
12801 | (define_insn "" |
12802 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12803 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12804 | (const_int 0)))] | |
12805 | "TARGET_POWERPC64" | |
12806 | "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63" | |
12807 | [(set_attr "length" "12")]) | |
12808 | ||
1fd4e8c1 | 12809 | (define_insn "" |
9ebbca7d | 12810 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12811 | (compare:CC |
9ebbca7d | 12812 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
12813 | (const_int 0)) |
12814 | (const_int 0))) | |
9ebbca7d | 12815 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12816 | (gt:SI (match_dup 1) (const_int 0)))] |
f9562f27 | 12817 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12818 | "@ |
12819 | {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31 | |
12820 | #" | |
29ae5b89 | 12821 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12822 | (set_attr "length" "12,16")]) |
12823 | ||
12824 | (define_split | |
12825 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
12826 | (compare:CC | |
12827 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12828 | (const_int 0)) | |
12829 | (const_int 0))) | |
12830 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12831 | (gt:SI (match_dup 1) (const_int 0)))] | |
12832 | "! TARGET_POWERPC64 && reload_completed" | |
12833 | [(set (match_dup 0) | |
12834 | (gt:SI (match_dup 1) (const_int 0))) | |
12835 | (set (match_dup 2) | |
12836 | (compare:CC (match_dup 0) | |
12837 | (const_int 0)))] | |
12838 | "") | |
1fd4e8c1 | 12839 | |
f9562f27 | 12840 | (define_insn "" |
9ebbca7d | 12841 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
f9562f27 | 12842 | (compare:CC |
9ebbca7d | 12843 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 DE |
12844 | (const_int 0)) |
12845 | (const_int 0))) | |
9ebbca7d | 12846 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
12847 | (gt:DI (match_dup 1) (const_int 0)))] |
12848 | "TARGET_POWERPC64" | |
9ebbca7d GK |
12849 | "@ |
12850 | subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63 | |
12851 | #" | |
f9562f27 | 12852 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12853 | (set_attr "length" "12,16")]) |
12854 | ||
12855 | (define_split | |
12856 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
12857 | (compare:CC | |
12858 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12859 | (const_int 0)) | |
12860 | (const_int 0))) | |
12861 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12862 | (gt:DI (match_dup 1) (const_int 0)))] | |
12863 | "TARGET_POWERPC64 && reload_completed" | |
12864 | [(set (match_dup 0) | |
12865 | (gt:DI (match_dup 1) (const_int 0))) | |
12866 | (set (match_dup 2) | |
12867 | (compare:CC (match_dup 0) | |
12868 | (const_int 0)))] | |
12869 | "") | |
f9562f27 | 12870 | |
1fd4e8c1 | 12871 | (define_insn "" |
cd2b37d9 RK |
12872 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12873 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12874 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
12875 | "TARGET_POWER" |
12876 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 12877 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12878 | |
12879 | (define_insn "" | |
9ebbca7d | 12880 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12881 | (compare:CC |
9ebbca7d GK |
12882 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12883 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
1fd4e8c1 | 12884 | (const_int 0))) |
9ebbca7d | 12885 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12886 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 12887 | "TARGET_POWER" |
9ebbca7d GK |
12888 | "@ |
12889 | doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
12890 | #" | |
29ae5b89 | 12891 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12892 | (set_attr "length" "12,16")]) |
12893 | ||
12894 | (define_split | |
12895 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12896 | (compare:CC | |
12897 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12898 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12899 | (const_int 0))) | |
12900 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12901 | (gt:SI (match_dup 1) (match_dup 2)))] | |
12902 | "TARGET_POWER && reload_completed" | |
12903 | [(set (match_dup 0) | |
12904 | (gt:SI (match_dup 1) (match_dup 2))) | |
12905 | (set (match_dup 3) | |
12906 | (compare:CC (match_dup 0) | |
12907 | (const_int 0)))] | |
12908 | "") | |
1fd4e8c1 RK |
12909 | |
12910 | (define_insn "" | |
cd2b37d9 RK |
12911 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12912 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12913 | (const_int 0)) |
cd2b37d9 | 12914 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 12915 | (clobber (match_scratch:SI 3 "=&r"))] |
f9562f27 | 12916 | "! TARGET_POWERPC64" |
ca7f5001 | 12917 | "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2" |
b19003d8 | 12918 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12919 | |
f9562f27 DE |
12920 | (define_insn "" |
12921 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12922 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12923 | (const_int 0)) | |
12924 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
12925 | (clobber (match_scratch:DI 3 "=&r"))] | |
12926 | "TARGET_POWERPC64" | |
12927 | "addc %3,%1,%1\;subfe %3,%1,%3\;addze %0,%2" | |
12928 | [(set_attr "length" "12")]) | |
12929 | ||
1fd4e8c1 | 12930 | (define_insn "" |
9ebbca7d | 12931 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12932 | (compare:CC |
9ebbca7d | 12933 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12934 | (const_int 0)) |
9ebbca7d | 12935 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 12936 | (const_int 0))) |
9ebbca7d | 12937 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
f9562f27 | 12938 | "! TARGET_POWERPC64" |
9ebbca7d GK |
12939 | "@ |
12940 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 | |
12941 | #" | |
b19003d8 | 12942 | [(set_attr "type" "compare") |
9ebbca7d GK |
12943 | (set_attr "length" "12,16")]) |
12944 | ||
12945 | (define_split | |
12946 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12947 | (compare:CC | |
12948 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12949 | (const_int 0)) | |
12950 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
12951 | (const_int 0))) | |
12952 | (clobber (match_scratch:SI 3 ""))] | |
12953 | "! TARGET_POWERPC64 && reload_completed" | |
12954 | [(set (match_dup 3) | |
12955 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) | |
12956 | (match_dup 2))) | |
12957 | (set (match_dup 0) | |
12958 | (compare:CC (match_dup 3) | |
12959 | (const_int 0)))] | |
12960 | "") | |
1fd4e8c1 | 12961 | |
f9562f27 | 12962 | (define_insn "" |
9ebbca7d | 12963 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
f9562f27 | 12964 | (compare:CC |
9ebbca7d | 12965 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 12966 | (const_int 0)) |
9ebbca7d | 12967 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 12968 | (const_int 0))) |
9ebbca7d | 12969 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
f9562f27 | 12970 | "TARGET_POWERPC64" |
9ebbca7d GK |
12971 | "@ |
12972 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 | |
12973 | #" | |
f9562f27 | 12974 | [(set_attr "type" "compare") |
9ebbca7d GK |
12975 | (set_attr "length" "12,16")]) |
12976 | ||
12977 | (define_split | |
12978 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12979 | (compare:CC | |
12980 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12981 | (const_int 0)) | |
12982 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
12983 | (const_int 0))) | |
12984 | (clobber (match_scratch:DI 3 ""))] | |
12985 | "TARGET_POWERPC64 && reload_completed" | |
12986 | [(set (match_dup 3) | |
12987 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) | |
12988 | (match_dup 2))) | |
12989 | (set (match_dup 0) | |
12990 | (compare:CC (match_dup 3) | |
12991 | (const_int 0)))] | |
12992 | "") | |
f9562f27 | 12993 | |
1fd4e8c1 | 12994 | (define_insn "" |
9ebbca7d GK |
12995 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
12996 | (compare:CC | |
12997 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
12998 | (const_int 0)) | |
12999 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
13000 | (const_int 0))) | |
13001 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
13002 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) | |
13003 | (clobber (match_scratch:SI 3 "=&r,&r"))] | |
13004 | "! TARGET_POWERPC64" | |
13005 | "@ | |
13006 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %0,%2 | |
13007 | #" | |
13008 | [(set_attr "type" "compare") | |
13009 | (set_attr "length" "12,16")]) | |
13010 | ||
13011 | (define_split | |
13012 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
1fd4e8c1 | 13013 | (compare:CC |
9ebbca7d | 13014 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 13015 | (const_int 0)) |
9ebbca7d | 13016 | (match_operand:SI 2 "gpc_reg_operand" "")) |
1fd4e8c1 | 13017 | (const_int 0))) |
9ebbca7d | 13018 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 13019 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
9ebbca7d GK |
13020 | (clobber (match_scratch:SI 3 ""))] |
13021 | "! TARGET_POWERPC64 && reload_completed" | |
13022 | [(parallel [(set (match_dup 0) | |
13023 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) | |
13024 | (clobber (match_dup 3))]) | |
13025 | (set (match_dup 4) | |
13026 | (compare:CC (match_dup 0) | |
13027 | (const_int 0)))] | |
13028 | "") | |
1fd4e8c1 | 13029 | |
f9562f27 | 13030 | (define_insn "" |
9ebbca7d | 13031 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
f9562f27 | 13032 | (compare:CC |
9ebbca7d | 13033 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 13034 | (const_int 0)) |
9ebbca7d | 13035 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 13036 | (const_int 0))) |
9ebbca7d | 13037 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 13038 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) |
9ebbca7d | 13039 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
f9562f27 | 13040 | "TARGET_POWERPC64" |
9ebbca7d GK |
13041 | "@ |
13042 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %0,%2 | |
13043 | #" | |
f9562f27 | 13044 | [(set_attr "type" "compare") |
9ebbca7d GK |
13045 | (set_attr "length" "12,16")]) |
13046 | ||
13047 | (define_split | |
13048 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
13049 | (compare:CC | |
13050 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13051 | (const_int 0)) | |
13052 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
13053 | (const_int 0))) | |
13054 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13055 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) | |
13056 | (clobber (match_scratch:DI 3 ""))] | |
13057 | "TARGET_POWERPC64 && reload_completed" | |
13058 | [(parallel [(set (match_dup 0) | |
13059 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) | |
13060 | (clobber (match_dup 3))]) | |
13061 | (set (match_dup 4) | |
13062 | (compare:CC (match_dup 0) | |
13063 | (const_int 0)))] | |
13064 | "") | |
f9562f27 | 13065 | |
1fd4e8c1 | 13066 | (define_insn "" |
cd2b37d9 RK |
13067 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13068 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13069 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
cd2b37d9 | 13070 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 13071 | (clobber (match_scratch:SI 4 "=&r"))] |
ca7f5001 RK |
13072 | "TARGET_POWER" |
13073 | "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3" | |
b19003d8 | 13074 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13075 | |
13076 | (define_insn "" | |
9ebbca7d | 13077 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13078 | (compare:CC |
9ebbca7d GK |
13079 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13080 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
13081 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13082 | (const_int 0))) |
9ebbca7d | 13083 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 13084 | "TARGET_POWER" |
9ebbca7d GK |
13085 | "@ |
13086 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
13087 | #" | |
b19003d8 | 13088 | [(set_attr "type" "compare") |
9ebbca7d GK |
13089 | (set_attr "length" "12,16")]) |
13090 | ||
13091 | (define_split | |
13092 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13093 | (compare:CC | |
13094 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13095 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13096 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13097 | (const_int 0))) | |
13098 | (clobber (match_scratch:SI 4 ""))] | |
13099 | "TARGET_POWER && reload_completed" | |
13100 | [(set (match_dup 4) | |
13101 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) | |
13102 | (match_dup 3))) | |
13103 | (set (match_dup 0) | |
13104 | (compare:CC (match_dup 4) | |
13105 | (const_int 0)))] | |
13106 | "") | |
1fd4e8c1 RK |
13107 | |
13108 | (define_insn "" | |
9ebbca7d | 13109 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13110 | (compare:CC |
9ebbca7d GK |
13111 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13112 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
13113 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13114 | (const_int 0))) |
9ebbca7d | 13115 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13116 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 13117 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 13118 | "TARGET_POWER" |
9ebbca7d GK |
13119 | "@ |
13120 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3 | |
13121 | #" | |
b19003d8 | 13122 | [(set_attr "type" "compare") |
9ebbca7d GK |
13123 | (set_attr "length" "12,16")]) |
13124 | ||
13125 | (define_split | |
13126 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
13127 | (compare:CC | |
13128 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13129 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13130 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13131 | (const_int 0))) | |
13132 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13133 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
13134 | (clobber (match_scratch:SI 4 ""))] | |
13135 | "TARGET_POWER && reload_completed" | |
13136 | [(parallel [(set (match_dup 0) | |
13137 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
13138 | (clobber (match_dup 4))]) | |
13139 | (set (match_dup 5) | |
13140 | (compare:CC (match_dup 0) | |
13141 | (const_int 0)))] | |
13142 | "") | |
1fd4e8c1 RK |
13143 | |
13144 | (define_insn "" | |
cd2b37d9 RK |
13145 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13146 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13147 | (const_int 0))))] |
f9562f27 | 13148 | "! TARGET_POWERPC64" |
ca7f5001 | 13149 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
b19003d8 | 13150 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13151 | |
f9562f27 DE |
13152 | (define_insn "" |
13153 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13154 | (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13155 | (const_int 0))))] | |
13156 | "TARGET_POWERPC64" | |
13157 | "subfic %0,%1,0\;addme %0,%0\;sradi} %0,%0,63" | |
13158 | [(set_attr "length" "12")]) | |
13159 | ||
1fd4e8c1 | 13160 | (define_insn "" |
cd2b37d9 RK |
13161 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13162 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13163 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
13164 | "TARGET_POWER" |
13165 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 13166 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13167 | |
13168 | (define_insn "" | |
cd2b37d9 RK |
13169 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13170 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13171 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
f9562f27 | 13172 | "! TARGET_POWERPC64" |
ca7f5001 | 13173 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0" |
b19003d8 | 13174 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13175 | |
f9562f27 DE |
13176 | (define_insn "" |
13177 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13178 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13179 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
13180 | "TARGET_POWERPC64" | |
13181 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0" | |
13182 | [(set_attr "length" "12")]) | |
13183 | ||
1fd4e8c1 | 13184 | (define_insn "" |
9ebbca7d | 13185 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13186 | (compare:CC |
9ebbca7d GK |
13187 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13188 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 13189 | (const_int 0))) |
9ebbca7d | 13190 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13191 | (gtu:SI (match_dup 1) (match_dup 2)))] |
f9562f27 | 13192 | "! TARGET_POWERPC64" |
9ebbca7d GK |
13193 | "@ |
13194 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 | |
13195 | #" | |
b19003d8 | 13196 | [(set_attr "type" "compare") |
9ebbca7d GK |
13197 | (set_attr "length" "12,16")]) |
13198 | ||
13199 | (define_split | |
13200 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13201 | (compare:CC | |
13202 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13203 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13204 | (const_int 0))) | |
13205 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13206 | (gtu:SI (match_dup 1) (match_dup 2)))] | |
13207 | "! TARGET_POWERPC64 && reload_completed" | |
13208 | [(set (match_dup 0) | |
13209 | (gtu:SI (match_dup 1) (match_dup 2))) | |
13210 | (set (match_dup 3) | |
13211 | (compare:CC (match_dup 0) | |
13212 | (const_int 0)))] | |
13213 | "") | |
1fd4e8c1 | 13214 | |
f9562f27 | 13215 | (define_insn "" |
9ebbca7d | 13216 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13217 | (compare:CC |
9ebbca7d GK |
13218 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
13219 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 13220 | (const_int 0))) |
9ebbca7d | 13221 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 DE |
13222 | (gtu:DI (match_dup 1) (match_dup 2)))] |
13223 | "TARGET_POWERPC64" | |
9ebbca7d GK |
13224 | "@ |
13225 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0 | |
13226 | #" | |
f9562f27 | 13227 | [(set_attr "type" "compare") |
9ebbca7d GK |
13228 | (set_attr "length" "12,16")]) |
13229 | ||
13230 | (define_split | |
13231 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13232 | (compare:CC | |
13233 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13234 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13235 | (const_int 0))) | |
13236 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13237 | (gtu:DI (match_dup 1) (match_dup 2)))] | |
13238 | "TARGET_POWERPC64 && reload_completed" | |
13239 | [(set (match_dup 0) | |
13240 | (gtu:DI (match_dup 1) (match_dup 2))) | |
13241 | (set (match_dup 3) | |
13242 | (compare:CC (match_dup 0) | |
13243 | (const_int 0)))] | |
13244 | "") | |
f9562f27 | 13245 | |
1fd4e8c1 | 13246 | (define_insn "" |
19378cf8 MM |
13247 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
13248 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
13249 | (match_operand:SI 2 "reg_or_short_operand" "I,rI")) | |
13250 | (match_operand:SI 3 "reg_or_short_operand" "r,rI"))) | |
13251 | (clobber (match_scratch:SI 4 "=&r,&r"))] | |
f9562f27 | 13252 | "! TARGET_POWERPC64" |
00751805 | 13253 | "@ |
ca7f5001 | 13254 | {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3 |
ca7f5001 | 13255 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3" |
19378cf8 | 13256 | [(set_attr "length" "8,12")]) |
1fd4e8c1 | 13257 | |
f9562f27 DE |
13258 | (define_insn "" |
13259 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
13260 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
13261 | (match_operand:DI 2 "reg_or_short_operand" "I,rI")) | |
13262 | (match_operand:DI 3 "reg_or_short_operand" "r,rI"))) | |
13263 | (clobber (match_scratch:DI 4 "=&r,&r"))] | |
13264 | "TARGET_POWERPC64" | |
13265 | "@ | |
13266 | addic %4,%1,%k2\;addze %0,%3 | |
13267 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf%I3c %0,%4,%3" | |
13268 | [(set_attr "length" "8,12")]) | |
13269 | ||
1fd4e8c1 | 13270 | (define_insn "" |
9ebbca7d | 13271 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13272 | (compare:CC |
9ebbca7d GK |
13273 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13274 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13275 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13276 | (const_int 0))) |
9ebbca7d | 13277 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 13278 | "! TARGET_POWERPC64" |
00751805 | 13279 | "@ |
19378cf8 | 13280 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
13281 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3 |
13282 | # | |
13283 | #" | |
b19003d8 | 13284 | [(set_attr "type" "compare") |
9ebbca7d GK |
13285 | (set_attr "length" "8,12,12,16")]) |
13286 | ||
13287 | (define_split | |
13288 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13289 | (compare:CC | |
13290 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13291 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13292 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13293 | (const_int 0))) | |
13294 | (clobber (match_scratch:SI 4 ""))] | |
13295 | "! TARGET_POWERPC64 && reload_completed" | |
13296 | [(set (match_dup 4) | |
13297 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) | |
13298 | (match_dup 3))) | |
13299 | (set (match_dup 0) | |
13300 | (compare:CC (match_dup 4) | |
13301 | (const_int 0)))] | |
13302 | "") | |
1fd4e8c1 | 13303 | |
f9562f27 | 13304 | (define_insn "" |
9ebbca7d | 13305 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13306 | (compare:CC |
9ebbca7d GK |
13307 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13308 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13309 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13310 | (const_int 0))) |
9ebbca7d | 13311 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
f9562f27 DE |
13312 | "TARGET_POWERPC64" |
13313 | "@ | |
13314 | addic %4,%1,%k2\;addze. %4,%3 | |
9ebbca7d GK |
13315 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3 |
13316 | # | |
13317 | #" | |
f9562f27 | 13318 | [(set_attr "type" "compare") |
9ebbca7d GK |
13319 | (set_attr "length" "8,12,12,16")]) |
13320 | ||
13321 | (define_split | |
13322 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13323 | (compare:CC | |
13324 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13325 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13326 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13327 | (const_int 0))) | |
13328 | (clobber (match_scratch:DI 4 ""))] | |
13329 | "TARGET_POWERPC64 && reload_completed" | |
13330 | [(set (match_dup 4) | |
13331 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) | |
13332 | (match_dup 3))) | |
13333 | (set (match_dup 0) | |
13334 | (compare:CC (match_dup 4) | |
13335 | (const_int 0)))] | |
13336 | "") | |
f9562f27 | 13337 | |
1fd4e8c1 | 13338 | (define_insn "" |
9ebbca7d | 13339 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13340 | (compare:CC |
9ebbca7d GK |
13341 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13342 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13343 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13344 | (const_int 0))) |
9ebbca7d | 13345 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 13346 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 13347 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
f9562f27 | 13348 | "! TARGET_POWERPC64" |
00751805 | 13349 | "@ |
ca7f5001 | 13350 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3 |
9ebbca7d GK |
13351 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3 |
13352 | # | |
13353 | #" | |
b19003d8 | 13354 | [(set_attr "type" "compare") |
9ebbca7d GK |
13355 | (set_attr "length" "8,12,12,16")]) |
13356 | ||
13357 | (define_split | |
13358 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
13359 | (compare:CC | |
13360 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13361 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13362 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13363 | (const_int 0))) | |
13364 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13365 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
13366 | (clobber (match_scratch:SI 4 ""))] | |
13367 | "! TARGET_POWERPC64 && reload_completed" | |
13368 | [(parallel [(set (match_dup 0) | |
13369 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
13370 | (clobber (match_dup 4))]) | |
13371 | (set (match_dup 5) | |
13372 | (compare:CC (match_dup 0) | |
13373 | (const_int 0)))] | |
13374 | "") | |
1fd4e8c1 | 13375 | |
f9562f27 | 13376 | (define_insn "" |
9ebbca7d | 13377 | [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13378 | (compare:CC |
9ebbca7d GK |
13379 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13380 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13381 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13382 | (const_int 0))) |
9ebbca7d | 13383 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 | 13384 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d | 13385 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
f9562f27 DE |
13386 | "TARGET_POWERPC64" |
13387 | "@ | |
13388 | addic %4,%1,%k2\;addze. %0,%3 | |
9ebbca7d GK |
13389 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %0,%4,%3 |
13390 | # | |
13391 | #" | |
f9562f27 | 13392 | [(set_attr "type" "compare") |
9ebbca7d GK |
13393 | (set_attr "length" "8,12,12,16")]) |
13394 | ||
13395 | (define_split | |
13396 | [(set (match_operand:CC 5 "cc_reg_not_cr0_operand" "") | |
13397 | (compare:CC | |
13398 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13399 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13400 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13401 | (const_int 0))) | |
13402 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13403 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
13404 | (clobber (match_scratch:DI 4 ""))] | |
13405 | "TARGET_POWERPC64 && reload_completed" | |
13406 | [(parallel [(set (match_dup 0) | |
13407 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
13408 | (clobber (match_dup 4))]) | |
13409 | (set (match_dup 5) | |
13410 | (compare:CC (match_dup 0) | |
13411 | (const_int 0)))] | |
13412 | "") | |
f9562f27 | 13413 | |
1fd4e8c1 | 13414 | (define_insn "" |
cd2b37d9 RK |
13415 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13416 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13417 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
f9562f27 | 13418 | "! TARGET_POWERPC64" |
ca7f5001 | 13419 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 13420 | [(set_attr "length" "8")]) |
f9562f27 DE |
13421 | |
13422 | (define_insn "" | |
13423 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13424 | (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13425 | (match_operand:DI 2 "reg_or_short_operand" "rI"))))] | |
13426 | "TARGET_POWERPC64" | |
13427 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0" | |
13428 | [(set_attr "length" "8")]) | |
1fd4e8c1 RK |
13429 | \f |
13430 | ;; Define both directions of branch and return. If we need a reload | |
13431 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
13432 | ;; register CC value to there. | |
13433 | ||
13434 | (define_insn "" | |
13435 | [(set (pc) | |
13436 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13437 | [(match_operand 2 | |
13438 | "cc_reg_operand" "x,?y") | |
13439 | (const_int 0)]) | |
13440 | (label_ref (match_operand 0 "" "")) | |
13441 | (pc)))] | |
13442 | "" | |
b19003d8 RK |
13443 | "* |
13444 | { | |
12a4e8c5 | 13445 | return output_cbranch (operands[1], \"%l0\", 0, insn); |
b19003d8 RK |
13446 | }" |
13447 | [(set_attr "type" "branch")]) | |
13448 | ||
1fd4e8c1 RK |
13449 | (define_insn "" |
13450 | [(set (pc) | |
13451 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13452 | [(match_operand 1 | |
13453 | "cc_reg_operand" "x,?y") | |
13454 | (const_int 0)]) | |
13455 | (return) | |
13456 | (pc)))] | |
13457 | "direct_return ()" | |
12a4e8c5 GK |
13458 | "* |
13459 | { | |
13460 | return output_cbranch (operands[0], NULL, 0, insn); | |
13461 | }" | |
b7ff3d82 DE |
13462 | [(set_attr "type" "branch") |
13463 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
13464 | |
13465 | (define_insn "" | |
13466 | [(set (pc) | |
13467 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13468 | [(match_operand 2 | |
13469 | "cc_reg_operand" "x,?y") | |
13470 | (const_int 0)]) | |
13471 | (pc) | |
13472 | (label_ref (match_operand 0 "" ""))))] | |
13473 | "" | |
b19003d8 RK |
13474 | "* |
13475 | { | |
12a4e8c5 | 13476 | return output_cbranch (operands[1], \"%l0\", 1, insn); |
b19003d8 RK |
13477 | }" |
13478 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13479 | |
13480 | (define_insn "" | |
13481 | [(set (pc) | |
13482 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13483 | [(match_operand 1 | |
13484 | "cc_reg_operand" "x,?y") | |
13485 | (const_int 0)]) | |
13486 | (pc) | |
13487 | (return)))] | |
13488 | "direct_return ()" | |
12a4e8c5 GK |
13489 | "* |
13490 | { | |
13491 | return output_cbranch (operands[0], NULL, 1, insn); | |
13492 | }" | |
b7ff3d82 DE |
13493 | [(set_attr "type" "branch") |
13494 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
13495 | |
13496 | ;; Unconditional branch and return. | |
13497 | ||
13498 | (define_insn "jump" | |
13499 | [(set (pc) | |
13500 | (label_ref (match_operand 0 "" "")))] | |
13501 | "" | |
b7ff3d82 DE |
13502 | "b %l0" |
13503 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13504 | |
13505 | (define_insn "return" | |
13506 | [(return)] | |
13507 | "direct_return ()" | |
324e52cc TG |
13508 | "{br|blr}" |
13509 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 13510 | |
0ad91047 DE |
13511 | (define_expand "indirect_jump" |
13512 | [(set (pc) (match_operand 0 "register_operand" ""))] | |
1fd4e8c1 | 13513 | "" |
0ad91047 DE |
13514 | " |
13515 | { | |
13516 | if (TARGET_32BIT) | |
13517 | emit_jump_insn (gen_indirect_jumpsi (operands[0])); | |
13518 | else | |
13519 | emit_jump_insn (gen_indirect_jumpdi (operands[0])); | |
13520 | DONE; | |
13521 | }") | |
13522 | ||
13523 | (define_insn "indirect_jumpsi" | |
13524 | [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))] | |
13525 | "TARGET_32BIT" | |
1fd4e8c1 RK |
13526 | "@ |
13527 | bctr | |
324e52cc TG |
13528 | {br|blr}" |
13529 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 13530 | |
0ad91047 | 13531 | (define_insn "indirect_jumpdi" |
266eb58a | 13532 | [(set (pc) (match_operand:DI 0 "register_operand" "c,l"))] |
0ad91047 | 13533 | "TARGET_64BIT" |
266eb58a DE |
13534 | "@ |
13535 | bctr | |
13536 | {br|blr}" | |
13537 | [(set_attr "type" "jmpreg")]) | |
13538 | ||
1fd4e8c1 RK |
13539 | ;; Table jump for switch statements: |
13540 | (define_expand "tablejump" | |
e6ca2c17 DE |
13541 | [(use (match_operand 0 "" "")) |
13542 | (use (label_ref (match_operand 1 "" "")))] | |
13543 | "" | |
13544 | " | |
13545 | { | |
13546 | if (TARGET_32BIT) | |
13547 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
13548 | else | |
13549 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
13550 | DONE; | |
13551 | }") | |
13552 | ||
13553 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
13554 | [(set (match_dup 3) |
13555 | (plus:SI (match_operand:SI 0 "" "") | |
13556 | (match_dup 2))) | |
13557 | (parallel [(set (pc) (match_dup 3)) | |
13558 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13559 | "TARGET_32BIT" |
1fd4e8c1 RK |
13560 | " |
13561 | { operands[0] = force_reg (SImode, operands[0]); | |
c5c76735 | 13562 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); |
1fd4e8c1 RK |
13563 | operands[3] = gen_reg_rtx (SImode); |
13564 | }") | |
13565 | ||
e6ca2c17 | 13566 | (define_expand "tablejumpdi" |
9ebbca7d GK |
13567 | [(set (match_dup 4) |
13568 | (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) | |
13569 | (set (match_dup 3) | |
13570 | (plus:DI (match_dup 4) | |
e6ca2c17 DE |
13571 | (match_dup 2))) |
13572 | (parallel [(set (pc) (match_dup 3)) | |
13573 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13574 | "TARGET_64BIT" |
e6ca2c17 | 13575 | " |
9ebbca7d | 13576 | { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); |
e6ca2c17 | 13577 | operands[3] = gen_reg_rtx (DImode); |
9ebbca7d | 13578 | operands[4] = gen_reg_rtx (DImode); |
e6ca2c17 DE |
13579 | }") |
13580 | ||
1fd4e8c1 RK |
13581 | (define_insn "" |
13582 | [(set (pc) | |
740ab4a2 | 13583 | (match_operand:SI 0 "register_operand" "c,l")) |
1fd4e8c1 | 13584 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 13585 | "TARGET_32BIT" |
1fd4e8c1 RK |
13586 | "@ |
13587 | bctr | |
a6845123 RK |
13588 | {br|blr}" |
13589 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 13590 | |
266eb58a DE |
13591 | (define_insn "" |
13592 | [(set (pc) | |
13593 | (match_operand:DI 0 "register_operand" "c,l")) | |
13594 | (use (label_ref (match_operand 1 "" "")))] | |
0ad91047 | 13595 | "TARGET_64BIT" |
266eb58a DE |
13596 | "@ |
13597 | bctr | |
13598 | {br|blr}" | |
13599 | [(set_attr "type" "jmpreg")]) | |
13600 | ||
1fd4e8c1 RK |
13601 | (define_insn "nop" |
13602 | [(const_int 0)] | |
13603 | "" | |
ca7f5001 | 13604 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 13605 | \f |
7e69e155 | 13606 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
13607 | ;; so loop.c knows what to generate. |
13608 | ||
b6c9286a | 13609 | (define_expand "decrement_and_branch_on_count" |
0ad91047 DE |
13610 | [(use (match_operand 0 "register_operand" "")) |
13611 | (use (label_ref (match_operand 1 "" "")))] | |
13612 | "" | |
13613 | " | |
13614 | { | |
13615 | if (TARGET_POWERPC64) | |
13616 | emit_jump_insn (gen_ctrdi (operands[0], operands[1])); | |
13617 | else | |
13618 | emit_jump_insn (gen_ctrsi (operands[0], operands[1])); | |
13619 | DONE; | |
13620 | }") | |
13621 | ||
13622 | (define_expand "ctrsi" | |
3cb999d8 DE |
13623 | [(parallel [(set (pc) |
13624 | (if_then_else (ne (match_operand:SI 0 "register_operand" "") | |
13625 | (const_int 1)) | |
13626 | (label_ref (match_operand 1 "" "")) | |
13627 | (pc))) | |
b6c9286a MM |
13628 | (set (match_dup 0) |
13629 | (plus:SI (match_dup 0) | |
13630 | (const_int -1))) | |
5f81043f RK |
13631 | (clobber (match_scratch:CC 2 "")) |
13632 | (clobber (match_scratch:SI 3 ""))])] | |
0ad91047 DE |
13633 | "! TARGET_POWERPC64" |
13634 | "") | |
13635 | ||
13636 | (define_expand "ctrdi" | |
3cb999d8 DE |
13637 | [(parallel [(set (pc) |
13638 | (if_then_else (ne (match_operand:DI 0 "register_operand" "") | |
13639 | (const_int 1)) | |
13640 | (label_ref (match_operand 1 "" "")) | |
13641 | (pc))) | |
0ad91047 DE |
13642 | (set (match_dup 0) |
13643 | (plus:DI (match_dup 0) | |
13644 | (const_int -1))) | |
13645 | (clobber (match_scratch:CC 2 "")) | |
13646 | (clobber (match_scratch:DI 3 ""))])] | |
13647 | "TARGET_POWERPC64" | |
c225ba7b RK |
13648 | "") |
13649 | ||
1fd4e8c1 RK |
13650 | ;; We need to be able to do this for any operand, including MEM, or we |
13651 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 13652 | ;; JUMP_INSNs. |
0ad91047 | 13653 | ;; For the length attribute to be calculated correctly, the |
5f81043f RK |
13654 | ;; label MUST be operand 0. |
13655 | ||
0ad91047 | 13656 | (define_insn "*ctrsi_internal1" |
1fd4e8c1 | 13657 | [(set (pc) |
5f81043f | 13658 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 13659 | (const_int 1)) |
a6845123 | 13660 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 13661 | (pc))) |
5f81043f RK |
13662 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
13663 | (plus:SI (match_dup 1) | |
13664 | (const_int -1))) | |
1fd4e8c1 RK |
13665 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
13666 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 13667 | "! TARGET_POWERPC64" |
b19003d8 RK |
13668 | "* |
13669 | { | |
af87a13e | 13670 | if (which_alternative != 0) |
b19003d8 RK |
13671 | return \"#\"; |
13672 | else if (get_attr_length (insn) == 8) | |
a6845123 | 13673 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 13674 | else |
c81bebd7 | 13675 | return \"bdz %$+8\;b %l0\"; |
b19003d8 | 13676 | }" |
baf97f86 RK |
13677 | [(set_attr "type" "branch") |
13678 | (set_attr "length" "*,12,16")]) | |
7e69e155 | 13679 | |
0ad91047 | 13680 | (define_insn "*ctrsi_internal2" |
5f81043f RK |
13681 | [(set (pc) |
13682 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r") | |
13683 | (const_int 1)) | |
13684 | (pc) | |
13685 | (label_ref (match_operand 0 "" "")))) | |
13686 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
13687 | (plus:SI (match_dup 1) | |
13688 | (const_int -1))) | |
13689 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
13690 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
13691 | "! TARGET_POWERPC64" |
13692 | "* | |
13693 | { | |
13694 | if (which_alternative != 0) | |
13695 | return \"#\"; | |
13696 | else if (get_attr_length (insn) == 8) | |
13697 | return \"bdz %l0\"; | |
13698 | else | |
13699 | return \"{bdn|bdnz} %$+8\;b %l0\"; | |
13700 | }" | |
13701 | [(set_attr "type" "branch") | |
13702 | (set_attr "length" "*,12,16")]) | |
13703 | ||
13704 | (define_insn "*ctrdi_internal1" | |
13705 | [(set (pc) | |
13706 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") | |
13707 | (const_int 1)) | |
13708 | (label_ref (match_operand 0 "" "")) | |
13709 | (pc))) | |
13710 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
13711 | (plus:DI (match_dup 1) | |
13712 | (const_int -1))) | |
13713 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
13714 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
13715 | "TARGET_POWERPC64" | |
13716 | "* | |
13717 | { | |
13718 | if (which_alternative != 0) | |
13719 | return \"#\"; | |
13720 | else if (get_attr_length (insn) == 8) | |
13721 | return \"{bdn|bdnz} %l0\"; | |
13722 | else | |
13723 | return \"bdz %$+8\;b %l0\"; | |
13724 | }" | |
13725 | [(set_attr "type" "branch") | |
13726 | (set_attr "length" "*,12,16")]) | |
13727 | ||
13728 | (define_insn "*ctrdi_internal2" | |
13729 | [(set (pc) | |
13730 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r") | |
13731 | (const_int 1)) | |
13732 | (pc) | |
13733 | (label_ref (match_operand 0 "" "")))) | |
13734 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
13735 | (plus:DI (match_dup 1) | |
13736 | (const_int -1))) | |
13737 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
13738 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
13739 | "TARGET_POWERPC64" | |
5f81043f RK |
13740 | "* |
13741 | { | |
13742 | if (which_alternative != 0) | |
13743 | return \"#\"; | |
13744 | else if (get_attr_length (insn) == 8) | |
13745 | return \"bdz %l0\"; | |
13746 | else | |
c81bebd7 | 13747 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
5f81043f RK |
13748 | }" |
13749 | [(set_attr "type" "branch") | |
13750 | (set_attr "length" "*,12,16")]) | |
13751 | ||
c225ba7b | 13752 | ;; Similar, but we can use GE since we have a REG_NONNEG. |
0ad91047 DE |
13753 | |
13754 | (define_insn "*ctrsi_internal3" | |
1fd4e8c1 | 13755 | [(set (pc) |
5f81043f | 13756 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
1fd4e8c1 | 13757 | (const_int 0)) |
a6845123 | 13758 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 13759 | (pc))) |
5f81043f RK |
13760 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
13761 | (plus:SI (match_dup 1) | |
13762 | (const_int -1))) | |
1fd4e8c1 RK |
13763 | (clobber (match_scratch:CC 3 "=X,&x,&X")) |
13764 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 13765 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
b19003d8 RK |
13766 | "* |
13767 | { | |
af87a13e | 13768 | if (which_alternative != 0) |
b19003d8 RK |
13769 | return \"#\"; |
13770 | else if (get_attr_length (insn) == 8) | |
a6845123 | 13771 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 13772 | else |
c81bebd7 | 13773 | return \"bdz %$+8\;b %l0\"; |
b19003d8 | 13774 | }" |
baf97f86 RK |
13775 | [(set_attr "type" "branch") |
13776 | (set_attr "length" "*,12,16")]) | |
7e69e155 | 13777 | |
0ad91047 | 13778 | (define_insn "*ctrsi_internal4" |
1fd4e8c1 | 13779 | [(set (pc) |
5f81043f RK |
13780 | (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r") |
13781 | (const_int 0)) | |
13782 | (pc) | |
13783 | (label_ref (match_operand 0 "" "")))) | |
13784 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
13785 | (plus:SI (match_dup 1) | |
13786 | (const_int -1))) | |
13787 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
13788 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 13789 | "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" |
5f81043f RK |
13790 | "* |
13791 | { | |
13792 | if (which_alternative != 0) | |
13793 | return \"#\"; | |
13794 | else if (get_attr_length (insn) == 8) | |
13795 | return \"bdz %l0\"; | |
13796 | else | |
c81bebd7 | 13797 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
5f81043f RK |
13798 | }" |
13799 | [(set_attr "type" "branch") | |
13800 | (set_attr "length" "*,12,16")]) | |
13801 | ||
0ad91047 DE |
13802 | (define_insn "*ctrdi_internal3" |
13803 | [(set (pc) | |
13804 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") | |
13805 | (const_int 0)) | |
13806 | (label_ref (match_operand 0 "" "")) | |
13807 | (pc))) | |
13808 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
13809 | (plus:DI (match_dup 1) | |
13810 | (const_int -1))) | |
13811 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
13812 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
13813 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" | |
13814 | "* | |
13815 | { | |
13816 | if (which_alternative != 0) | |
13817 | return \"#\"; | |
13818 | else if (get_attr_length (insn) == 8) | |
13819 | return \"{bdn|bdnz} %l0\"; | |
13820 | else | |
13821 | return \"bdz %$+8\;b %l0\"; | |
13822 | }" | |
13823 | [(set_attr "type" "branch") | |
13824 | (set_attr "length" "*,12,16")]) | |
13825 | ||
13826 | (define_insn "*ctrdi_internal4" | |
13827 | [(set (pc) | |
13828 | (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r") | |
13829 | (const_int 0)) | |
13830 | (pc) | |
13831 | (label_ref (match_operand 0 "" "")))) | |
13832 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
13833 | (plus:DI (match_dup 1) | |
13834 | (const_int -1))) | |
13835 | (clobber (match_scratch:CC 3 "=X,&x,&X")) | |
13836 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
13837 | "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)" | |
13838 | "* | |
13839 | { | |
13840 | if (which_alternative != 0) | |
13841 | return \"#\"; | |
13842 | else if (get_attr_length (insn) == 8) | |
13843 | return \"bdz %l0\"; | |
13844 | else | |
13845 | return \"{bdn|bdnz} %$+8\;b %l0\"; | |
13846 | }" | |
13847 | [(set_attr "type" "branch") | |
13848 | (set_attr "length" "*,12,16")]) | |
13849 | ||
13850 | ;; Similar but use EQ | |
13851 | ||
13852 | (define_insn "*ctrsi_internal5" | |
5f81043f RK |
13853 | [(set (pc) |
13854 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
1fd4e8c1 | 13855 | (const_int 1)) |
a6845123 | 13856 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 13857 | (pc))) |
5f81043f RK |
13858 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") |
13859 | (plus:SI (match_dup 1) | |
13860 | (const_int -1))) | |
1fd4e8c1 RK |
13861 | (clobber (match_scratch:CC 3 "=X,&x,&x")) |
13862 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 | 13863 | "! TARGET_POWERPC64" |
b19003d8 RK |
13864 | "* |
13865 | { | |
af87a13e | 13866 | if (which_alternative != 0) |
b19003d8 RK |
13867 | return \"#\"; |
13868 | else if (get_attr_length (insn) == 8) | |
a6845123 | 13869 | return \"bdz %l0\"; |
b19003d8 | 13870 | else |
c81bebd7 | 13871 | return \"{bdn|bdnz} %$+8\;b %l0\"; |
b19003d8 | 13872 | }" |
baf97f86 RK |
13873 | [(set_attr "type" "branch") |
13874 | (set_attr "length" "*,12,16")]) | |
1fd4e8c1 | 13875 | |
0ad91047 | 13876 | (define_insn "*ctrsi_internal6" |
5f81043f RK |
13877 | [(set (pc) |
13878 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r") | |
13879 | (const_int 1)) | |
13880 | (pc) | |
13881 | (label_ref (match_operand 0 "" "")))) | |
13882 | (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l") | |
13883 | (plus:SI (match_dup 1) | |
13884 | (const_int -1))) | |
13885 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
13886 | (clobber (match_scratch:SI 4 "=X,X,r"))] | |
0ad91047 DE |
13887 | "! TARGET_POWERPC64" |
13888 | "* | |
13889 | { | |
13890 | if (which_alternative != 0) | |
13891 | return \"#\"; | |
13892 | else if (get_attr_length (insn) == 8) | |
13893 | return \"{bdn|bdnz} %l0\"; | |
13894 | else | |
13895 | return \"bdz %$+8\;b %l0\"; | |
13896 | }" | |
13897 | [(set_attr "type" "branch") | |
13898 | (set_attr "length" "*,12,16")]) | |
13899 | ||
13900 | (define_insn "*ctrdi_internal5" | |
13901 | [(set (pc) | |
13902 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") | |
13903 | (const_int 1)) | |
13904 | (label_ref (match_operand 0 "" "")) | |
13905 | (pc))) | |
13906 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
13907 | (plus:DI (match_dup 1) | |
13908 | (const_int -1))) | |
13909 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
13910 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
13911 | "TARGET_POWERPC64" | |
13912 | "* | |
13913 | { | |
13914 | if (which_alternative != 0) | |
13915 | return \"#\"; | |
13916 | else if (get_attr_length (insn) == 8) | |
13917 | return \"bdz %l0\"; | |
13918 | else | |
13919 | return \"{bdn|bdnz} %$+8\;b %l0\"; | |
13920 | }" | |
13921 | [(set_attr "type" "branch") | |
13922 | (set_attr "length" "*,12,16")]) | |
13923 | ||
13924 | (define_insn "*ctrdi_internal6" | |
13925 | [(set (pc) | |
13926 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r") | |
13927 | (const_int 1)) | |
13928 | (pc) | |
13929 | (label_ref (match_operand 0 "" "")))) | |
13930 | (set (match_operand:DI 2 "register_operand" "=1,*r,m*q*c*l") | |
13931 | (plus:DI (match_dup 1) | |
13932 | (const_int -1))) | |
13933 | (clobber (match_scratch:CC 3 "=X,&x,&x")) | |
13934 | (clobber (match_scratch:DI 4 "=X,X,r"))] | |
13935 | "TARGET_POWERPC64" | |
5f81043f RK |
13936 | "* |
13937 | { | |
13938 | if (which_alternative != 0) | |
13939 | return \"#\"; | |
13940 | else if (get_attr_length (insn) == 8) | |
13941 | return \"{bdn|bdnz} %l0\"; | |
13942 | else | |
c81bebd7 | 13943 | return \"bdz %$+8\;b %l0\"; |
5f81043f RK |
13944 | }" |
13945 | [(set_attr "type" "branch") | |
13946 | (set_attr "length" "*,12,16")]) | |
13947 | ||
0ad91047 DE |
13948 | ;; Now the splitters if we could not allocate the CTR register |
13949 | ||
1fd4e8c1 RK |
13950 | (define_split |
13951 | [(set (pc) | |
13952 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 13953 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
13954 | (const_int 1)]) |
13955 | (match_operand 5 "" "") | |
13956 | (match_operand 6 "" ""))) | |
cd2b37d9 | 13957 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
5f81043f RK |
13958 | (plus:SI (match_dup 1) |
13959 | (const_int -1))) | |
1fd4e8c1 RK |
13960 | (clobber (match_scratch:CC 3 "")) |
13961 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 | 13962 | "! TARGET_POWERPC64 && reload_completed" |
1fd4e8c1 | 13963 | [(parallel [(set (match_dup 3) |
5f81043f RK |
13964 | (compare:CC (plus:SI (match_dup 1) |
13965 | (const_int -1)) | |
1fd4e8c1 | 13966 | (const_int 0))) |
5f81043f RK |
13967 | (set (match_dup 0) |
13968 | (plus:SI (match_dup 1) | |
13969 | (const_int -1)))]) | |
13970 | (set (pc) (if_then_else (match_dup 7) | |
13971 | (match_dup 5) | |
13972 | (match_dup 6)))] | |
1fd4e8c1 RK |
13973 | " |
13974 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
13975 | const0_rtx); }") | |
13976 | ||
13977 | (define_split | |
13978 | [(set (pc) | |
13979 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 13980 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
13981 | (const_int 1)]) |
13982 | (match_operand 5 "" "") | |
13983 | (match_operand 6 "" ""))) | |
9ebbca7d | 13984 | (set (match_operand:SI 0 "nonimmediate_operand" "") |
1fd4e8c1 RK |
13985 | (plus:SI (match_dup 1) (const_int -1))) |
13986 | (clobber (match_scratch:CC 3 "")) | |
13987 | (clobber (match_scratch:SI 4 ""))] | |
0ad91047 DE |
13988 | "! TARGET_POWERPC64 && reload_completed |
13989 | && ! gpc_reg_operand (operands[0], SImode)" | |
1fd4e8c1 | 13990 | [(parallel [(set (match_dup 3) |
5f81043f RK |
13991 | (compare:CC (plus:SI (match_dup 1) |
13992 | (const_int -1)) | |
1fd4e8c1 | 13993 | (const_int 0))) |
5f81043f RK |
13994 | (set (match_dup 4) |
13995 | (plus:SI (match_dup 1) | |
13996 | (const_int -1)))]) | |
13997 | (set (match_dup 0) | |
13998 | (match_dup 4)) | |
13999 | (set (pc) (if_then_else (match_dup 7) | |
14000 | (match_dup 5) | |
14001 | (match_dup 6)))] | |
1fd4e8c1 RK |
14002 | " |
14003 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
14004 | const0_rtx); }") | |
0ad91047 DE |
14005 | (define_split |
14006 | [(set (pc) | |
14007 | (if_then_else (match_operator 2 "comparison_operator" | |
14008 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
14009 | (const_int 1)]) | |
14010 | (match_operand 5 "" "") | |
14011 | (match_operand 6 "" ""))) | |
14012 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
14013 | (plus:DI (match_dup 1) | |
14014 | (const_int -1))) | |
14015 | (clobber (match_scratch:CC 3 "")) | |
14016 | (clobber (match_scratch:DI 4 ""))] | |
14017 | "TARGET_POWERPC64 && reload_completed" | |
14018 | [(parallel [(set (match_dup 3) | |
14019 | (compare:CC (plus:DI (match_dup 1) | |
14020 | (const_int -1)) | |
14021 | (const_int 0))) | |
14022 | (set (match_dup 0) | |
14023 | (plus:DI (match_dup 1) | |
14024 | (const_int -1)))]) | |
14025 | (set (pc) (if_then_else (match_dup 7) | |
14026 | (match_dup 5) | |
14027 | (match_dup 6)))] | |
14028 | " | |
14029 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
14030 | const0_rtx); }") | |
14031 | ||
14032 | (define_split | |
14033 | [(set (pc) | |
14034 | (if_then_else (match_operator 2 "comparison_operator" | |
14035 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
14036 | (const_int 1)]) | |
14037 | (match_operand 5 "" "") | |
14038 | (match_operand 6 "" ""))) | |
9ebbca7d | 14039 | (set (match_operand:DI 0 "nonimmediate_operand" "") |
0ad91047 DE |
14040 | (plus:DI (match_dup 1) (const_int -1))) |
14041 | (clobber (match_scratch:CC 3 "")) | |
14042 | (clobber (match_scratch:DI 4 ""))] | |
14043 | "TARGET_POWERPC64 && reload_completed | |
14044 | && ! gpc_reg_operand (operands[0], DImode)" | |
14045 | [(parallel [(set (match_dup 3) | |
14046 | (compare:CC (plus:DI (match_dup 1) | |
14047 | (const_int -1)) | |
14048 | (const_int 0))) | |
14049 | (set (match_dup 4) | |
14050 | (plus:DI (match_dup 1) | |
14051 | (const_int -1)))]) | |
14052 | (set (match_dup 0) | |
14053 | (match_dup 4)) | |
14054 | (set (pc) (if_then_else (match_dup 7) | |
14055 | (match_dup 5) | |
14056 | (match_dup 6)))] | |
14057 | " | |
14058 | { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3], | |
14059 | const0_rtx); }") | |
e0cd0770 JC |
14060 | \f |
14061 | (define_insn "trap" | |
14062 | [(trap_if (const_int 1) (const_int 0))] | |
14063 | "" | |
14064 | "{t 31,0,0|trap}") | |
14065 | ||
14066 | (define_expand "conditional_trap" | |
14067 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14068 | [(match_dup 2) (match_dup 3)]) | |
14069 | (match_operand 1 "const_int_operand" ""))] | |
14070 | "" | |
14071 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
14072 | operands[2] = rs6000_compare_op0; | |
14073 | operands[3] = rs6000_compare_op1;") | |
14074 | ||
14075 | (define_insn "" | |
14076 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14077 | [(match_operand:SI 1 "register_operand" "r") | |
14078 | (match_operand:SI 2 "reg_or_short_operand" "rI")]) | |
14079 | (const_int 0))] | |
14080 | "" | |
a157febd GK |
14081 | "{t|tw}%V0%I2 %1,%2") |
14082 | ||
14083 | (define_insn "" | |
14084 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14085 | [(match_operand:DI 1 "register_operand" "r") | |
14086 | (match_operand:DI 2 "reg_or_short_operand" "rI")]) | |
14087 | (const_int 0))] | |
14088 | "TARGET_POWERPC64" | |
14089 | "td%V0%I2 %1,%2") | |
9ebbca7d GK |
14090 | \f |
14091 | ;; Insns related to generating the function prologue and epilogue. | |
14092 | ||
14093 | (define_expand "prologue" | |
14094 | [(use (const_int 0))] | |
14095 | "TARGET_SCHED_PROLOG" | |
14096 | " | |
14097 | { | |
14098 | rs6000_emit_prologue (); | |
14099 | DONE; | |
14100 | }") | |
14101 | ||
14102 | (define_insn "movesi_from_cr" | |
14103 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
14104 | (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) | |
14105 | (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 19))] | |
14106 | "" | |
14107 | "mfcr %0") | |
14108 | ||
14109 | (define_insn "*stmw" | |
14110 | [(match_parallel 0 "stmw_operation" | |
14111 | [(set (match_operand:SI 1 "memory_operand" "=m") | |
14112 | (match_operand:SI 2 "gpc_reg_operand" "r"))])] | |
14113 | "TARGET_MULTIPLE" | |
14114 | "{stm|stmw} %2,%1") | |
14115 | ||
14116 | (define_insn "*save_fpregs_si" | |
14117 | [(match_parallel 0 "any_operand" | |
14118 | [(clobber (match_operand:SI 1 "register_operand" "=l")) | |
14119 | (use (match_operand:SI 2 "call_operand" "s")) | |
14120 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14121 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14122 | "TARGET_32BIT" | |
14123 | "bl %z2") | |
14124 | ||
14125 | (define_insn "*save_fpregs_di" | |
14126 | [(match_parallel 0 "any_operand" | |
14127 | [(clobber (match_operand:DI 1 "register_operand" "=l")) | |
14128 | (use (match_operand:DI 2 "call_operand" "s")) | |
14129 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14130 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14131 | "TARGET_64BIT" | |
14132 | "bl %z2") | |
14133 | ||
14134 | ; These are to explain that changes to the stack pointer should | |
14135 | ; not be moved over stores to stack memory. | |
14136 | (define_insn "stack_tie" | |
14137 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
14138 | (unspec:BLK [(match_dup 0)] 5))] | |
14139 | "" | |
14140 | "" | |
14141 | [(set_attr "length" "0")]) | |
14142 | ||
14143 | ||
14144 | (define_expand "epilogue" | |
14145 | [(use (const_int 0))] | |
14146 | "TARGET_SCHED_PROLOG" | |
14147 | " | |
14148 | { | |
14149 | rs6000_emit_epilogue (FALSE); | |
14150 | DONE; | |
14151 | }") | |
14152 | ||
14153 | ; On some processors, doing the mtcrf one CC register at a time is | |
14154 | ; faster (like on the 604e). On others, doing them all at once is | |
14155 | ; faster; for instance, on the 601 and 750. | |
14156 | ||
14157 | (define_expand "movsi_to_cr_one" | |
14158 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
14159 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
14160 | (match_dup 2)] 20))] | |
14161 | "" | |
14162 | "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") | |
14163 | ||
14164 | (define_insn "*movsi_to_cr" | |
14165 | [(match_parallel 0 "mtcrf_operation" | |
14166 | [(use (match_operand 1 "immediate_operand" "n")) | |
14167 | (set (match_operand:CC 2 "cc_reg_operand" "=y") | |
14168 | (unspec:CC [(match_operand:SI 3 "gpc_reg_operand" "r") | |
14169 | (match_operand 4 "immediate_operand" "n")] | |
14170 | 20))])] | |
14171 | "" | |
14172 | "mtcrf %1,%3") | |
14173 | ||
14174 | (define_insn "" | |
14175 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
14176 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
14177 | (match_operand 2 "immediate_operand" "n")] 20))] | |
14178 | "GET_CODE (operands[0]) == REG | |
14179 | && CR_REGNO_P (REGNO (operands[0])) | |
14180 | && GET_CODE (operands[2]) == CONST_INT | |
14181 | && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" | |
14182 | "mtcrf %R0,%1") | |
14183 | ||
14184 | ; The load-multiple instructions have similar properties. | |
14185 | ; Note that "load_multiple" is a name known to the machine-independent | |
14186 | ; code that actually corresponds to the powerpc load-string. | |
14187 | ||
14188 | (define_insn "*lmw" | |
14189 | [(match_parallel 0 "lmw_operation" | |
14190 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
14191 | (match_operand:SI 2 "memory_operand" "m"))])] | |
14192 | "TARGET_MULTIPLE" | |
14193 | "{lm|lmw} %1,%2") | |
14194 | ||
14195 | (define_insn "*return_internal_si" | |
14196 | [(use (match_operand:SI 0 "register_operand" "l,c")) | |
14197 | (return)] | |
14198 | "TARGET_32BIT" | |
14199 | "@ | |
14200 | {br|blr} | |
14201 | bctr" | |
14202 | [(set_attr "type" "jmpreg")]) | |
14203 | ||
14204 | (define_insn "*return_internal_di" | |
14205 | [(use (match_operand:DI 0 "register_operand" "l,c")) | |
14206 | (return)] | |
14207 | "TARGET_64BIT" | |
14208 | "@ | |
14209 | {br|blr} | |
14210 | bctr" | |
14211 | [(set_attr "type" "jmpreg")]) | |
14212 | ||
14213 | ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall | |
14214 | ; stuff was in GCC. Oh, and "any_operand" is a bit flexible... | |
14215 | ||
14216 | (define_insn "*return_and_restore_fpregs_si" | |
14217 | [(match_parallel 0 "any_operand" | |
14218 | [(use (match_operand:SI 1 "register_operand" "l")) | |
14219 | (return) | |
14220 | (use (match_operand:SI 2 "call_operand" "s")) | |
14221 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
14222 | (match_operand:DF 4 "memory_operand" "m"))])] | |
14223 | "TARGET_32BIT" | |
14224 | "b %z2") | |
14225 | ||
14226 | (define_insn "*return_and_restore_fpregs_di" | |
14227 | [(match_parallel 0 "any_operand" | |
14228 | [(use (match_operand:DI 1 "register_operand" "l")) | |
14229 | (return) | |
14230 | (use (match_operand:DI 2 "call_operand" "s")) | |
14231 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
14232 | (match_operand:DF 4 "memory_operand" "m"))])] | |
14233 | "TARGET_64BIT" | |
14234 | "b %z2") | |
14235 | ||
14236 | ; This is used in compiling the routines __throw and __rethrow. | |
14237 | ; It's a little different to the usual definition... | |
14238 | ||
14239 | (define_expand "eh_epilogue" | |
14240 | [(use (match_operand 0 "general_operand" "r")) | |
14241 | (use (match_operand 1 "general_operand" "r")) | |
14242 | (use (match_operand 2 "general_operand" "c"))] | |
14243 | "" | |
14244 | " | |
14245 | { | |
14246 | rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
14247 | rtx insn; | |
14248 | ||
14249 | /* This is required for binary compatibility. If it's wrong, | |
14250 | it probably means that eh_regs() in except.c is broken. */ | |
14251 | if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 3) | |
14252 | abort(); | |
14253 | ||
14254 | /* These can be anything that doesn't interfere with the epilogue. */ | |
14255 | if (GET_CODE (operands[1]) != REG || REGNO (operands[1]) != 4) | |
14256 | { | |
14257 | rtx r = gen_rtx_REG (Pmode, 4); | |
14258 | emit_move_insn (r, operands[1]); | |
14259 | operands[1] = r; | |
14260 | } | |
14261 | ||
14262 | if (GET_CODE (operands[2]) != REG | |
14263 | || REGNO (operands[2]) != COUNT_REGISTER_REGNUM) | |
14264 | { | |
14265 | rtx r = gen_rtx_REG (Pmode, COUNT_REGISTER_REGNUM); | |
14266 | emit_move_insn (r, operands[2]); | |
14267 | operands[2] = r; | |
14268 | } | |
14269 | ||
14270 | #if TARGET_AIX | |
14271 | rs6000_emit_eh_toc_restore (operands[1]); | |
14272 | #endif | |
14273 | ||
14274 | emit_insn (gen_eh_reg_restore ()); | |
14275 | ||
14276 | if (Pmode == SImode) | |
14277 | emit_insn (gen_addsi3 (stack_reg, stack_reg, operands[1])); | |
14278 | else | |
14279 | emit_insn (gen_adddi3 (stack_reg, stack_reg, operands[1])); | |
14280 | ||
14281 | if (Pmode == SImode) | |
14282 | insn = emit_jump_insn (gen_return_eh_si (operands[2])); | |
14283 | else | |
14284 | insn = emit_jump_insn (gen_return_eh_di (operands[2])); | |
14285 | emit_barrier_after (insn); | |
14286 | ||
14287 | DONE; | |
14288 | }") | |
14289 | ||
14290 | ; We can't expand this before we know which registers are restored, | |
14291 | ; but we do want to expand it before flow2 because that way flow2 can | |
14292 | ; remove the redundant loads of the link register. | |
14293 | (define_expand "eh_reg_restore" | |
14294 | [(unspec_volatile [(const_int 0)] 9)] | |
14295 | "" | |
14296 | "") | |
14297 | ||
14298 | (define_split | |
14299 | [(unspec_volatile [(const_int 0)] 9)] | |
14300 | "reload_completed && TARGET_SCHED_PROLOG" | |
14301 | [(unspec_volatile [(const_int 0)] 9)] | |
14302 | " | |
14303 | { | |
14304 | rs6000_emit_epilogue (TRUE); | |
14305 | DONE; | |
14306 | }") | |
14307 | ||
14308 | (define_insn "" | |
14309 | [(unspec_volatile [(const_int 0)] 9)] | |
14310 | "" | |
14311 | "* | |
14312 | { | |
14313 | if (TARGET_SCHED_PROLOG) | |
14314 | return \"#\"; | |
14315 | ||
14316 | /* This is slightly ugly, but at least we don't have multiple | |
14317 | copies of the epilogue-emitting code. */ | |
14318 | start_sequence (); | |
14319 | ||
14320 | /* A NOTE_INSN_DELETED is supposed to be at the start | |
14321 | and end of the \"toplevel\" insn chain. */ | |
14322 | emit_note (0, NOTE_INSN_DELETED); | |
14323 | rs6000_emit_epilogue (TRUE); | |
14324 | emit_note (0, NOTE_INSN_DELETED); | |
14325 | ||
14326 | if (TARGET_DEBUG_STACK) | |
14327 | debug_rtx_list (get_insns(), 100); | |
14328 | final (get_insns(), asm_out_file, FALSE, FALSE); | |
14329 | end_sequence (); | |
14330 | return \"\"; | |
14331 | }") | |
14332 | ||
14333 | ||
14334 | (define_insn "return_eh_si" | |
14335 | [(use (match_operand:SI 0 "register_operand" "l,c")) | |
14336 | (return) | |
14337 | (use (reg:SI 2)) | |
14338 | (use (reg:SI 3))] | |
14339 | "TARGET_32BIT" | |
14340 | "@ | |
14341 | {br|blr} | |
14342 | bctr" | |
14343 | [(set_attr "type" "jmpreg")]) | |
14344 | ||
14345 | (define_insn "return_eh_di" | |
14346 | [(use (match_operand:DI 0 "register_operand" "l,c")) | |
14347 | (return) | |
14348 | (use (reg:DI 2)) | |
14349 | (use (reg:DI 3))] | |
14350 | "TARGET_64BIT" | |
14351 | "@ | |
14352 | {br|blr} | |
14353 | bctr" | |
14354 | [(set_attr "type" "jmpreg")]) |