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996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
d24652ee | 2 | ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
affad9a4 | 3 | ;; 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. |
996a5f59 | 4 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 | 5 | |
5de601cf | 6 | ;; This file is part of GCC. |
1fd4e8c1 | 7 | |
5de601cf NC |
8 | ;; GCC is free software; you can redistribute it and/or modify it |
9 | ;; under the terms of the GNU General Public License as published | |
10 | ;; by the Free Software Foundation; either version 2, or (at your | |
11 | ;; option) any later version. | |
1fd4e8c1 | 12 | |
5de601cf NC |
13 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | ;; License for more details. | |
1fd4e8c1 RK |
17 | |
18 | ;; You should have received a copy of the GNU General Public License | |
5de601cf NC |
19 | ;; along with GCC; see the file COPYING. If not, write to the |
20 | ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston, | |
21 | ;; MA 02111-1307, USA. | |
1fd4e8c1 RK |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
9ebbca7d | 24 | |
615158e2 JJ |
25 | ;; |
26 | ;; UNSPEC usage | |
27 | ;; | |
28 | ||
29 | (define_constants | |
30 | [(UNSPEC_FRSP 0) ; frsp for POWER machines | |
31 | (UNSPEC_TIE 5) ; tie stack contents and stack pointer | |
32 | (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC | |
33 | (UNSPEC_TOC 7) ; address of the TOC (more-or-less) | |
34 | (UNSPEC_MOVSI_GOT 8) | |
35 | (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit | |
36 | (UNSPEC_FCTIWZ 10) | |
37 | (UNSPEC_LD_MPIC 15) ; load_macho_picbase | |
38 | (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic | |
39 | (UNSPEC_TLSGD 17) | |
40 | (UNSPEC_TLSLD 18) | |
41 | (UNSPEC_MOVESI_FROM_CR 19) | |
42 | (UNSPEC_MOVESI_TO_CR 20) | |
43 | (UNSPEC_TLSDTPREL 21) | |
44 | (UNSPEC_TLSDTPRELHA 22) | |
45 | (UNSPEC_TLSDTPRELLO 23) | |
46 | (UNSPEC_TLSGOTDTPREL 24) | |
47 | (UNSPEC_TLSTPREL 25) | |
48 | (UNSPEC_TLSTPRELHA 26) | |
49 | (UNSPEC_TLSTPRELLO 27) | |
50 | (UNSPEC_TLSGOTTPREL 28) | |
51 | (UNSPEC_TLSTLS 29) | |
ecb62ae7 | 52 | (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero |
6b1fedc3 | 53 | (UNSPEC_MV_CR_EQ 31) ; move_from_CR_eq_bit |
615158e2 JJ |
54 | ]) |
55 | ||
56 | ;; | |
57 | ;; UNSPEC_VOLATILE usage | |
58 | ;; | |
59 | ||
60 | (define_constants | |
61 | [(UNSPECV_BLOCK 0) | |
62 | (UNSPECV_EH_RR 9) ; eh_reg_restore | |
63 | ]) | |
1fd4e8c1 RK |
64 | \f |
65 | ;; Define an insn type attribute. This is used in function unit delay | |
66 | ;; computations. | |
2c4a9cff | 67 | (define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv" |
1fd4e8c1 RK |
68 | (const_string "integer")) |
69 | ||
b19003d8 | 70 | ;; Length (in bytes). |
6ae08853 | 71 | ; '(pc)' in the following doesn't include the instruction itself; it is |
6cbadf36 | 72 | ; calculated as if the instruction had zero size. |
b19003d8 RK |
73 | (define_attr "length" "" |
74 | (if_then_else (eq_attr "type" "branch") | |
6cbadf36 | 75 | (if_then_else (and (ge (minus (match_dup 0) (pc)) |
b19003d8 | 76 | (const_int -32768)) |
6cbadf36 GK |
77 | (lt (minus (match_dup 0) (pc)) |
78 | (const_int 32764))) | |
39a10a29 GK |
79 | (const_int 4) |
80 | (const_int 8)) | |
b19003d8 RK |
81 | (const_int 4))) |
82 | ||
cfb557c4 RK |
83 | ;; Processor type -- this attribute must exactly match the processor_type |
84 | ;; enumeration in rs6000.h. | |
85 | ||
ec507f2d | 86 | (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5" |
cfb557c4 RK |
87 | (const (symbol_ref "rs6000_cpu_attr"))) |
88 | ||
b54cf83a DE |
89 | (automata_option "ndfa") |
90 | ||
91 | (include "rios1.md") | |
92 | (include "rios2.md") | |
93 | (include "rs64.md") | |
94 | (include "mpc.md") | |
95 | (include "40x.md") | |
02ca7595 | 96 | (include "440.md") |
b54cf83a DE |
97 | (include "603.md") |
98 | (include "6xx.md") | |
99 | (include "7xx.md") | |
100 | (include "7450.md") | |
5e8006fa | 101 | (include "8540.md") |
b54cf83a | 102 | (include "power4.md") |
ec507f2d | 103 | (include "power5.md") |
ac9e2cff | 104 | (include "darwin.md") |
309323c2 | 105 | |
1fd4e8c1 | 106 | \f |
2e6c9641 FJ |
107 | ;; This mode macro allows :P to be used for patterns that operate on |
108 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. | |
109 | (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) | |
110 | ||
1fd4e8c1 RK |
111 | ;; Start with fixed-point load and store insns. Here we put only the more |
112 | ;; complex forms. Basic data transfer is done later. | |
113 | ||
51b8fc2c RK |
114 | (define_expand "zero_extendqidi2" |
115 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
116 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
117 | "TARGET_POWERPC64" | |
118 | "") | |
119 | ||
120 | (define_insn "" | |
121 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
122 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
123 | "TARGET_POWERPC64" | |
124 | "@ | |
125 | lbz%U1%X1 %0,%1 | |
4371f8af | 126 | rldicl %0,%1,0,56" |
51b8fc2c RK |
127 | [(set_attr "type" "load,*")]) |
128 | ||
129 | (define_insn "" | |
9ebbca7d GK |
130 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
131 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 132 | (const_int 0))) |
9ebbca7d | 133 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 134 | "TARGET_64BIT" |
9ebbca7d GK |
135 | "@ |
136 | rldicl. %2,%1,0,56 | |
137 | #" | |
138 | [(set_attr "type" "compare") | |
139 | (set_attr "length" "4,8")]) | |
140 | ||
141 | (define_split | |
142 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
143 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
144 | (const_int 0))) | |
145 | (clobber (match_scratch:DI 2 ""))] | |
146 | "TARGET_POWERPC64 && reload_completed" | |
147 | [(set (match_dup 2) | |
148 | (zero_extend:DI (match_dup 1))) | |
149 | (set (match_dup 0) | |
150 | (compare:CC (match_dup 2) | |
151 | (const_int 0)))] | |
152 | "") | |
51b8fc2c RK |
153 | |
154 | (define_insn "" | |
9ebbca7d GK |
155 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
156 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 157 | (const_int 0))) |
9ebbca7d | 158 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 159 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 160 | "TARGET_64BIT" |
9ebbca7d GK |
161 | "@ |
162 | rldicl. %0,%1,0,56 | |
163 | #" | |
164 | [(set_attr "type" "compare") | |
165 | (set_attr "length" "4,8")]) | |
166 | ||
167 | (define_split | |
168 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
169 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
170 | (const_int 0))) | |
171 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
172 | (zero_extend:DI (match_dup 1)))] | |
173 | "TARGET_POWERPC64 && reload_completed" | |
174 | [(set (match_dup 0) | |
175 | (zero_extend:DI (match_dup 1))) | |
176 | (set (match_dup 2) | |
177 | (compare:CC (match_dup 0) | |
178 | (const_int 0)))] | |
179 | "") | |
51b8fc2c | 180 | |
2bee0449 RK |
181 | (define_insn "extendqidi2" |
182 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
183 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 184 | "TARGET_POWERPC64" |
2bee0449 | 185 | "extsb %0,%1") |
51b8fc2c RK |
186 | |
187 | (define_insn "" | |
9ebbca7d GK |
188 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
189 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 190 | (const_int 0))) |
9ebbca7d | 191 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 192 | "TARGET_64BIT" |
9ebbca7d GK |
193 | "@ |
194 | extsb. %2,%1 | |
195 | #" | |
196 | [(set_attr "type" "compare") | |
197 | (set_attr "length" "4,8")]) | |
198 | ||
199 | (define_split | |
200 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
201 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
202 | (const_int 0))) | |
203 | (clobber (match_scratch:DI 2 ""))] | |
204 | "TARGET_POWERPC64 && reload_completed" | |
205 | [(set (match_dup 2) | |
206 | (sign_extend:DI (match_dup 1))) | |
207 | (set (match_dup 0) | |
208 | (compare:CC (match_dup 2) | |
209 | (const_int 0)))] | |
210 | "") | |
51b8fc2c RK |
211 | |
212 | (define_insn "" | |
9ebbca7d GK |
213 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
214 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 215 | (const_int 0))) |
9ebbca7d | 216 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 217 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 218 | "TARGET_64BIT" |
9ebbca7d GK |
219 | "@ |
220 | extsb. %0,%1 | |
221 | #" | |
222 | [(set_attr "type" "compare") | |
223 | (set_attr "length" "4,8")]) | |
224 | ||
225 | (define_split | |
226 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
227 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
228 | (const_int 0))) | |
229 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
230 | (sign_extend:DI (match_dup 1)))] | |
231 | "TARGET_POWERPC64 && reload_completed" | |
232 | [(set (match_dup 0) | |
233 | (sign_extend:DI (match_dup 1))) | |
234 | (set (match_dup 2) | |
235 | (compare:CC (match_dup 0) | |
236 | (const_int 0)))] | |
237 | "") | |
51b8fc2c RK |
238 | |
239 | (define_expand "zero_extendhidi2" | |
240 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
241 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
242 | "TARGET_POWERPC64" | |
243 | "") | |
244 | ||
245 | (define_insn "" | |
246 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
247 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
248 | "TARGET_POWERPC64" | |
249 | "@ | |
250 | lhz%U1%X1 %0,%1 | |
4371f8af | 251 | rldicl %0,%1,0,48" |
51b8fc2c RK |
252 | [(set_attr "type" "load,*")]) |
253 | ||
254 | (define_insn "" | |
9ebbca7d GK |
255 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
256 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 257 | (const_int 0))) |
9ebbca7d | 258 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 259 | "TARGET_64BIT" |
9ebbca7d GK |
260 | "@ |
261 | rldicl. %2,%1,0,48 | |
262 | #" | |
263 | [(set_attr "type" "compare") | |
264 | (set_attr "length" "4,8")]) | |
265 | ||
266 | (define_split | |
267 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
268 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
269 | (const_int 0))) | |
270 | (clobber (match_scratch:DI 2 ""))] | |
271 | "TARGET_POWERPC64 && reload_completed" | |
272 | [(set (match_dup 2) | |
273 | (zero_extend:DI (match_dup 1))) | |
274 | (set (match_dup 0) | |
275 | (compare:CC (match_dup 2) | |
276 | (const_int 0)))] | |
277 | "") | |
51b8fc2c RK |
278 | |
279 | (define_insn "" | |
9ebbca7d GK |
280 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
281 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 282 | (const_int 0))) |
9ebbca7d | 283 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 284 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 285 | "TARGET_64BIT" |
9ebbca7d GK |
286 | "@ |
287 | rldicl. %0,%1,0,48 | |
288 | #" | |
289 | [(set_attr "type" "compare") | |
290 | (set_attr "length" "4,8")]) | |
291 | ||
292 | (define_split | |
293 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
294 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
295 | (const_int 0))) | |
296 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
297 | (zero_extend:DI (match_dup 1)))] | |
298 | "TARGET_POWERPC64 && reload_completed" | |
299 | [(set (match_dup 0) | |
300 | (zero_extend:DI (match_dup 1))) | |
301 | (set (match_dup 2) | |
302 | (compare:CC (match_dup 0) | |
303 | (const_int 0)))] | |
304 | "") | |
51b8fc2c RK |
305 | |
306 | (define_expand "extendhidi2" | |
307 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
308 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
309 | "TARGET_POWERPC64" | |
310 | "") | |
311 | ||
312 | (define_insn "" | |
313 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
314 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
315 | "TARGET_POWERPC64" | |
316 | "@ | |
317 | lha%U1%X1 %0,%1 | |
318 | extsh %0,%1" | |
b54cf83a | 319 | [(set_attr "type" "load_ext,*")]) |
51b8fc2c RK |
320 | |
321 | (define_insn "" | |
9ebbca7d GK |
322 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
323 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 324 | (const_int 0))) |
9ebbca7d | 325 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 326 | "TARGET_64BIT" |
9ebbca7d GK |
327 | "@ |
328 | extsh. %2,%1 | |
329 | #" | |
330 | [(set_attr "type" "compare") | |
331 | (set_attr "length" "4,8")]) | |
332 | ||
333 | (define_split | |
334 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
335 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
336 | (const_int 0))) | |
337 | (clobber (match_scratch:DI 2 ""))] | |
338 | "TARGET_POWERPC64 && reload_completed" | |
339 | [(set (match_dup 2) | |
340 | (sign_extend:DI (match_dup 1))) | |
341 | (set (match_dup 0) | |
342 | (compare:CC (match_dup 2) | |
343 | (const_int 0)))] | |
344 | "") | |
51b8fc2c RK |
345 | |
346 | (define_insn "" | |
9ebbca7d GK |
347 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
348 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 349 | (const_int 0))) |
9ebbca7d | 350 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 351 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 352 | "TARGET_64BIT" |
9ebbca7d GK |
353 | "@ |
354 | extsh. %0,%1 | |
355 | #" | |
356 | [(set_attr "type" "compare") | |
357 | (set_attr "length" "4,8")]) | |
358 | ||
359 | (define_split | |
360 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
361 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
362 | (const_int 0))) | |
363 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
364 | (sign_extend:DI (match_dup 1)))] | |
365 | "TARGET_POWERPC64 && reload_completed" | |
366 | [(set (match_dup 0) | |
367 | (sign_extend:DI (match_dup 1))) | |
368 | (set (match_dup 2) | |
369 | (compare:CC (match_dup 0) | |
370 | (const_int 0)))] | |
371 | "") | |
51b8fc2c RK |
372 | |
373 | (define_expand "zero_extendsidi2" | |
374 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
375 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
376 | "TARGET_POWERPC64" | |
377 | "") | |
378 | ||
379 | (define_insn "" | |
380 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
381 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
382 | "TARGET_POWERPC64" | |
383 | "@ | |
384 | lwz%U1%X1 %0,%1 | |
385 | rldicl %0,%1,0,32" | |
386 | [(set_attr "type" "load,*")]) | |
387 | ||
388 | (define_insn "" | |
9ebbca7d GK |
389 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
390 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 391 | (const_int 0))) |
9ebbca7d | 392 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 393 | "TARGET_64BIT" |
9ebbca7d GK |
394 | "@ |
395 | rldicl. %2,%1,0,32 | |
396 | #" | |
397 | [(set_attr "type" "compare") | |
398 | (set_attr "length" "4,8")]) | |
399 | ||
400 | (define_split | |
401 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
402 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
403 | (const_int 0))) | |
404 | (clobber (match_scratch:DI 2 ""))] | |
405 | "TARGET_POWERPC64 && reload_completed" | |
406 | [(set (match_dup 2) | |
407 | (zero_extend:DI (match_dup 1))) | |
408 | (set (match_dup 0) | |
409 | (compare:CC (match_dup 2) | |
410 | (const_int 0)))] | |
411 | "") | |
51b8fc2c RK |
412 | |
413 | (define_insn "" | |
9ebbca7d GK |
414 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
415 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 416 | (const_int 0))) |
9ebbca7d | 417 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 418 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 419 | "TARGET_64BIT" |
9ebbca7d GK |
420 | "@ |
421 | rldicl. %0,%1,0,32 | |
422 | #" | |
423 | [(set_attr "type" "compare") | |
424 | (set_attr "length" "4,8")]) | |
425 | ||
426 | (define_split | |
427 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
428 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
429 | (const_int 0))) | |
430 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
431 | (zero_extend:DI (match_dup 1)))] | |
432 | "TARGET_POWERPC64 && reload_completed" | |
433 | [(set (match_dup 0) | |
434 | (zero_extend:DI (match_dup 1))) | |
435 | (set (match_dup 2) | |
436 | (compare:CC (match_dup 0) | |
437 | (const_int 0)))] | |
438 | "") | |
51b8fc2c RK |
439 | |
440 | (define_expand "extendsidi2" | |
441 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
442 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
443 | "TARGET_POWERPC64" | |
444 | "") | |
445 | ||
446 | (define_insn "" | |
447 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 448 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
449 | "TARGET_POWERPC64" |
450 | "@ | |
451 | lwa%U1%X1 %0,%1 | |
452 | extsw %0,%1" | |
b54cf83a | 453 | [(set_attr "type" "load_ext,*")]) |
51b8fc2c RK |
454 | |
455 | (define_insn "" | |
9ebbca7d GK |
456 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
457 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 458 | (const_int 0))) |
9ebbca7d | 459 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 460 | "TARGET_64BIT" |
9ebbca7d GK |
461 | "@ |
462 | extsw. %2,%1 | |
463 | #" | |
464 | [(set_attr "type" "compare") | |
465 | (set_attr "length" "4,8")]) | |
466 | ||
467 | (define_split | |
468 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
469 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
470 | (const_int 0))) | |
471 | (clobber (match_scratch:DI 2 ""))] | |
472 | "TARGET_POWERPC64 && reload_completed" | |
473 | [(set (match_dup 2) | |
474 | (sign_extend:DI (match_dup 1))) | |
475 | (set (match_dup 0) | |
476 | (compare:CC (match_dup 2) | |
477 | (const_int 0)))] | |
478 | "") | |
51b8fc2c RK |
479 | |
480 | (define_insn "" | |
9ebbca7d GK |
481 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
482 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 483 | (const_int 0))) |
9ebbca7d | 484 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 485 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 486 | "TARGET_64BIT" |
9ebbca7d GK |
487 | "@ |
488 | extsw. %0,%1 | |
489 | #" | |
490 | [(set_attr "type" "compare") | |
491 | (set_attr "length" "4,8")]) | |
492 | ||
493 | (define_split | |
494 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
495 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
496 | (const_int 0))) | |
497 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
498 | (sign_extend:DI (match_dup 1)))] | |
499 | "TARGET_POWERPC64 && reload_completed" | |
500 | [(set (match_dup 0) | |
501 | (sign_extend:DI (match_dup 1))) | |
502 | (set (match_dup 2) | |
503 | (compare:CC (match_dup 0) | |
504 | (const_int 0)))] | |
505 | "") | |
51b8fc2c | 506 | |
1fd4e8c1 | 507 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
508 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
509 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
510 | "" |
511 | "") | |
512 | ||
513 | (define_insn "" | |
cd2b37d9 | 514 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
515 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
516 | "" | |
517 | "@ | |
518 | lbz%U1%X1 %0,%1 | |
005a35b9 | 519 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
520 | [(set_attr "type" "load,*")]) |
521 | ||
522 | (define_insn "" | |
9ebbca7d GK |
523 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
524 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 525 | (const_int 0))) |
9ebbca7d | 526 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 527 | "" |
9ebbca7d GK |
528 | "@ |
529 | {andil.|andi.} %2,%1,0xff | |
530 | #" | |
531 | [(set_attr "type" "compare") | |
532 | (set_attr "length" "4,8")]) | |
533 | ||
534 | (define_split | |
535 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
536 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
537 | (const_int 0))) | |
538 | (clobber (match_scratch:SI 2 ""))] | |
539 | "reload_completed" | |
540 | [(set (match_dup 2) | |
541 | (zero_extend:SI (match_dup 1))) | |
542 | (set (match_dup 0) | |
543 | (compare:CC (match_dup 2) | |
544 | (const_int 0)))] | |
545 | "") | |
1fd4e8c1 RK |
546 | |
547 | (define_insn "" | |
9ebbca7d GK |
548 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
549 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 550 | (const_int 0))) |
9ebbca7d | 551 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
552 | (zero_extend:SI (match_dup 1)))] |
553 | "" | |
9ebbca7d GK |
554 | "@ |
555 | {andil.|andi.} %0,%1,0xff | |
556 | #" | |
557 | [(set_attr "type" "compare") | |
558 | (set_attr "length" "4,8")]) | |
559 | ||
560 | (define_split | |
561 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
562 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
563 | (const_int 0))) | |
564 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
565 | (zero_extend:SI (match_dup 1)))] | |
566 | "reload_completed" | |
567 | [(set (match_dup 0) | |
568 | (zero_extend:SI (match_dup 1))) | |
569 | (set (match_dup 2) | |
570 | (compare:CC (match_dup 0) | |
571 | (const_int 0)))] | |
572 | "") | |
1fd4e8c1 | 573 | |
51b8fc2c RK |
574 | (define_expand "extendqisi2" |
575 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
576 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
577 | "" | |
578 | " | |
579 | { | |
580 | if (TARGET_POWERPC) | |
581 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
582 | else if (TARGET_POWER) | |
583 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
584 | else | |
585 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
586 | DONE; | |
587 | }") | |
588 | ||
589 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
590 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
591 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 592 | "TARGET_POWERPC" |
2bee0449 | 593 | "extsb %0,%1") |
51b8fc2c RK |
594 | |
595 | (define_insn "" | |
9ebbca7d GK |
596 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
597 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 598 | (const_int 0))) |
9ebbca7d | 599 | (clobber (match_scratch:SI 2 "=r,r"))] |
51b8fc2c | 600 | "TARGET_POWERPC" |
9ebbca7d GK |
601 | "@ |
602 | extsb. %2,%1 | |
603 | #" | |
604 | [(set_attr "type" "compare") | |
605 | (set_attr "length" "4,8")]) | |
606 | ||
607 | (define_split | |
608 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
609 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
610 | (const_int 0))) | |
611 | (clobber (match_scratch:SI 2 ""))] | |
612 | "TARGET_POWERPC && reload_completed" | |
613 | [(set (match_dup 2) | |
614 | (sign_extend:SI (match_dup 1))) | |
615 | (set (match_dup 0) | |
616 | (compare:CC (match_dup 2) | |
617 | (const_int 0)))] | |
618 | "") | |
51b8fc2c RK |
619 | |
620 | (define_insn "" | |
9ebbca7d GK |
621 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
622 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 623 | (const_int 0))) |
9ebbca7d | 624 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
625 | (sign_extend:SI (match_dup 1)))] |
626 | "TARGET_POWERPC" | |
9ebbca7d GK |
627 | "@ |
628 | extsb. %0,%1 | |
629 | #" | |
630 | [(set_attr "type" "compare") | |
631 | (set_attr "length" "4,8")]) | |
632 | ||
633 | (define_split | |
634 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
635 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
636 | (const_int 0))) | |
637 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
638 | (sign_extend:SI (match_dup 1)))] | |
639 | "TARGET_POWERPC && reload_completed" | |
640 | [(set (match_dup 0) | |
641 | (sign_extend:SI (match_dup 1))) | |
642 | (set (match_dup 2) | |
643 | (compare:CC (match_dup 0) | |
644 | (const_int 0)))] | |
645 | "") | |
51b8fc2c RK |
646 | |
647 | (define_expand "extendqisi2_power" | |
648 | [(parallel [(set (match_dup 2) | |
649 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
650 | (const_int 24))) | |
651 | (clobber (scratch:SI))]) | |
652 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
653 | (ashiftrt:SI (match_dup 2) | |
654 | (const_int 24))) | |
655 | (clobber (scratch:SI))])] | |
656 | "TARGET_POWER" | |
657 | " | |
658 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
659 | operands[2] = gen_reg_rtx (SImode); }") | |
660 | ||
661 | (define_expand "extendqisi2_no_power" | |
662 | [(set (match_dup 2) | |
663 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
664 | (const_int 24))) | |
665 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
666 | (ashiftrt:SI (match_dup 2) | |
667 | (const_int 24)))] | |
668 | "! TARGET_POWER && ! TARGET_POWERPC" | |
669 | " | |
670 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
671 | operands[2] = gen_reg_rtx (SImode); }") | |
672 | ||
1fd4e8c1 | 673 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
674 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
675 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
676 | "" |
677 | "") | |
678 | ||
679 | (define_insn "" | |
cd2b37d9 | 680 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
681 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
682 | "" | |
683 | "@ | |
684 | lbz%U1%X1 %0,%1 | |
005a35b9 | 685 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
686 | [(set_attr "type" "load,*")]) |
687 | ||
688 | (define_insn "" | |
9ebbca7d GK |
689 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
690 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 691 | (const_int 0))) |
9ebbca7d | 692 | (clobber (match_scratch:HI 2 "=r,r"))] |
51b8fc2c | 693 | "" |
9ebbca7d GK |
694 | "@ |
695 | {andil.|andi.} %2,%1,0xff | |
696 | #" | |
697 | [(set_attr "type" "compare") | |
698 | (set_attr "length" "4,8")]) | |
699 | ||
700 | (define_split | |
701 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
702 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
703 | (const_int 0))) | |
704 | (clobber (match_scratch:HI 2 ""))] | |
705 | "reload_completed" | |
706 | [(set (match_dup 2) | |
707 | (zero_extend:HI (match_dup 1))) | |
708 | (set (match_dup 0) | |
709 | (compare:CC (match_dup 2) | |
710 | (const_int 0)))] | |
711 | "") | |
1fd4e8c1 | 712 | |
51b8fc2c | 713 | (define_insn "" |
9ebbca7d GK |
714 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
715 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 716 | (const_int 0))) |
9ebbca7d | 717 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
718 | (zero_extend:HI (match_dup 1)))] |
719 | "" | |
9ebbca7d GK |
720 | "@ |
721 | {andil.|andi.} %0,%1,0xff | |
722 | #" | |
723 | [(set_attr "type" "compare") | |
724 | (set_attr "length" "4,8")]) | |
725 | ||
726 | (define_split | |
727 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
728 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
729 | (const_int 0))) | |
730 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
731 | (zero_extend:HI (match_dup 1)))] | |
732 | "reload_completed" | |
733 | [(set (match_dup 0) | |
734 | (zero_extend:HI (match_dup 1))) | |
735 | (set (match_dup 2) | |
736 | (compare:CC (match_dup 0) | |
737 | (const_int 0)))] | |
738 | "") | |
815cdc52 MM |
739 | |
740 | (define_expand "extendqihi2" | |
741 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
742 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
743 | "" | |
744 | " | |
745 | { | |
746 | if (TARGET_POWERPC) | |
747 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
748 | else if (TARGET_POWER) | |
749 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
750 | else | |
751 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
752 | DONE; | |
753 | }") | |
754 | ||
755 | (define_insn "extendqihi2_ppc" | |
756 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
757 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
758 | "TARGET_POWERPC" | |
759 | "extsb %0,%1") | |
760 | ||
761 | (define_insn "" | |
9ebbca7d GK |
762 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
763 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 764 | (const_int 0))) |
9ebbca7d | 765 | (clobber (match_scratch:HI 2 "=r,r"))] |
815cdc52 | 766 | "TARGET_POWERPC" |
9ebbca7d GK |
767 | "@ |
768 | extsb. %2,%1 | |
769 | #" | |
770 | [(set_attr "type" "compare") | |
771 | (set_attr "length" "4,8")]) | |
772 | ||
773 | (define_split | |
774 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
775 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
776 | (const_int 0))) | |
777 | (clobber (match_scratch:HI 2 ""))] | |
778 | "TARGET_POWERPC && reload_completed" | |
779 | [(set (match_dup 2) | |
780 | (sign_extend:HI (match_dup 1))) | |
781 | (set (match_dup 0) | |
782 | (compare:CC (match_dup 2) | |
783 | (const_int 0)))] | |
784 | "") | |
815cdc52 MM |
785 | |
786 | (define_insn "" | |
9ebbca7d GK |
787 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
788 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 789 | (const_int 0))) |
9ebbca7d | 790 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
791 | (sign_extend:HI (match_dup 1)))] |
792 | "TARGET_POWERPC" | |
9ebbca7d GK |
793 | "@ |
794 | extsb. %0,%1 | |
795 | #" | |
796 | [(set_attr "type" "compare") | |
797 | (set_attr "length" "4,8")]) | |
798 | ||
799 | (define_split | |
800 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
801 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
802 | (const_int 0))) | |
803 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
804 | (sign_extend:HI (match_dup 1)))] | |
805 | "TARGET_POWERPC && reload_completed" | |
806 | [(set (match_dup 0) | |
807 | (sign_extend:HI (match_dup 1))) | |
808 | (set (match_dup 2) | |
809 | (compare:CC (match_dup 0) | |
810 | (const_int 0)))] | |
811 | "") | |
51b8fc2c RK |
812 | |
813 | (define_expand "extendqihi2_power" | |
814 | [(parallel [(set (match_dup 2) | |
815 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
816 | (const_int 24))) | |
817 | (clobber (scratch:SI))]) | |
818 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
819 | (ashiftrt:SI (match_dup 2) | |
820 | (const_int 24))) | |
821 | (clobber (scratch:SI))])] | |
822 | "TARGET_POWER" | |
823 | " | |
824 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
825 | operands[1] = gen_lowpart (SImode, operands[1]); | |
826 | operands[2] = gen_reg_rtx (SImode); }") | |
827 | ||
828 | (define_expand "extendqihi2_no_power" | |
829 | [(set (match_dup 2) | |
830 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
831 | (const_int 24))) | |
832 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
833 | (ashiftrt:SI (match_dup 2) | |
834 | (const_int 24)))] | |
835 | "! TARGET_POWER && ! TARGET_POWERPC" | |
836 | " | |
837 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
838 | operands[1] = gen_lowpart (SImode, operands[1]); | |
839 | operands[2] = gen_reg_rtx (SImode); }") | |
840 | ||
1fd4e8c1 | 841 | (define_expand "zero_extendhisi2" |
5f243543 | 842 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 843 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
844 | "" |
845 | "") | |
846 | ||
847 | (define_insn "" | |
cd2b37d9 | 848 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
849 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
850 | "" | |
851 | "@ | |
852 | lhz%U1%X1 %0,%1 | |
005a35b9 | 853 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
854 | [(set_attr "type" "load,*")]) |
855 | ||
856 | (define_insn "" | |
9ebbca7d GK |
857 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
858 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 859 | (const_int 0))) |
9ebbca7d | 860 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 861 | "" |
9ebbca7d GK |
862 | "@ |
863 | {andil.|andi.} %2,%1,0xffff | |
864 | #" | |
865 | [(set_attr "type" "compare") | |
866 | (set_attr "length" "4,8")]) | |
867 | ||
868 | (define_split | |
869 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
870 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
871 | (const_int 0))) | |
872 | (clobber (match_scratch:SI 2 ""))] | |
873 | "reload_completed" | |
874 | [(set (match_dup 2) | |
875 | (zero_extend:SI (match_dup 1))) | |
876 | (set (match_dup 0) | |
877 | (compare:CC (match_dup 2) | |
878 | (const_int 0)))] | |
879 | "") | |
1fd4e8c1 RK |
880 | |
881 | (define_insn "" | |
9ebbca7d GK |
882 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
883 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 884 | (const_int 0))) |
9ebbca7d | 885 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
886 | (zero_extend:SI (match_dup 1)))] |
887 | "" | |
9ebbca7d GK |
888 | "@ |
889 | {andil.|andi.} %0,%1,0xffff | |
890 | #" | |
891 | [(set_attr "type" "compare") | |
892 | (set_attr "length" "4,8")]) | |
893 | ||
894 | (define_split | |
895 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
896 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
897 | (const_int 0))) | |
898 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
899 | (zero_extend:SI (match_dup 1)))] | |
900 | "reload_completed" | |
901 | [(set (match_dup 0) | |
902 | (zero_extend:SI (match_dup 1))) | |
903 | (set (match_dup 2) | |
904 | (compare:CC (match_dup 0) | |
905 | (const_int 0)))] | |
906 | "") | |
1fd4e8c1 RK |
907 | |
908 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
909 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
910 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
911 | "" |
912 | "") | |
913 | ||
914 | (define_insn "" | |
cd2b37d9 | 915 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
916 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
917 | "" | |
918 | "@ | |
919 | lha%U1%X1 %0,%1 | |
ca7f5001 | 920 | {exts|extsh} %0,%1" |
b54cf83a | 921 | [(set_attr "type" "load_ext,*")]) |
1fd4e8c1 RK |
922 | |
923 | (define_insn "" | |
9ebbca7d GK |
924 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
925 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 926 | (const_int 0))) |
9ebbca7d | 927 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 928 | "" |
9ebbca7d GK |
929 | "@ |
930 | {exts.|extsh.} %2,%1 | |
931 | #" | |
932 | [(set_attr "type" "compare") | |
933 | (set_attr "length" "4,8")]) | |
934 | ||
935 | (define_split | |
936 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
937 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
938 | (const_int 0))) | |
939 | (clobber (match_scratch:SI 2 ""))] | |
940 | "reload_completed" | |
941 | [(set (match_dup 2) | |
942 | (sign_extend:SI (match_dup 1))) | |
943 | (set (match_dup 0) | |
944 | (compare:CC (match_dup 2) | |
945 | (const_int 0)))] | |
946 | "") | |
1fd4e8c1 RK |
947 | |
948 | (define_insn "" | |
9ebbca7d GK |
949 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
950 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 951 | (const_int 0))) |
9ebbca7d | 952 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
953 | (sign_extend:SI (match_dup 1)))] |
954 | "" | |
9ebbca7d GK |
955 | "@ |
956 | {exts.|extsh.} %0,%1 | |
957 | #" | |
958 | [(set_attr "type" "compare") | |
959 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 960 | \f |
9ebbca7d GK |
961 | (define_split |
962 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
963 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
964 | (const_int 0))) | |
965 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
966 | (sign_extend:SI (match_dup 1)))] | |
967 | "reload_completed" | |
968 | [(set (match_dup 0) | |
969 | (sign_extend:SI (match_dup 1))) | |
970 | (set (match_dup 2) | |
971 | (compare:CC (match_dup 0) | |
972 | (const_int 0)))] | |
973 | "") | |
974 | ||
1fd4e8c1 | 975 | ;; Fixed-point arithmetic insns. |
deb9225a RK |
976 | |
977 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
978 | ;; allowing register zero as source. | |
7cd5235b MM |
979 | (define_expand "addsi3" |
980 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
981 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f6bf7de2 | 982 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
7cd5235b MM |
983 | "" |
984 | " | |
985 | { | |
677a9668 DE |
986 | if (GET_CODE (operands[2]) == CONST_INT |
987 | && ! add_operand (operands[2], SImode)) | |
7cd5235b | 988 | { |
677a9668 | 989 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
990 | ? operands[0] : gen_reg_rtx (SImode)); |
991 | ||
2bfcf297 | 992 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 993 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 994 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); |
7cd5235b | 995 | |
9ebbca7d GK |
996 | /* The ordering here is important for the prolog expander. |
997 | When space is allocated from the stack, adding 'low' first may | |
998 | produce a temporary deallocation (which would be bad). */ | |
2bfcf297 | 999 | emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest))); |
7cd5235b MM |
1000 | emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low))); |
1001 | DONE; | |
1002 | } | |
1003 | }") | |
1004 | ||
1005 | (define_insn "*addsi3_internal1" | |
1006 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r") | |
1007 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 1008 | (match_operand:SI 2 "add_operand" "r,I,I,L")))] |
1fd4e8c1 RK |
1009 | "" |
1010 | "@ | |
deb9225a RK |
1011 | {cax|add} %0,%1,%2 |
1012 | {cal %0,%2(%1)|addi %0,%1,%2} | |
1013 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
1014 | {cau|addis} %0,%1,%v2" |
1015 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 1016 | |
ee890fe2 SS |
1017 | (define_insn "addsi3_high" |
1018 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") | |
1019 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
1020 | (high:SI (match_operand 2 "" ""))))] | |
1021 | "TARGET_MACHO && !TARGET_64BIT" | |
1022 | "{cau|addis} %0,%1,ha16(%2)" | |
1023 | [(set_attr "length" "4")]) | |
1024 | ||
7cd5235b | 1025 | (define_insn "*addsi3_internal2" |
cb8cc086 MM |
1026 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1027 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1028 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1029 | (const_int 0))) |
cb8cc086 | 1030 | (clobber (match_scratch:SI 3 "=r,r,r,r"))] |
4b8a63d6 | 1031 | "TARGET_32BIT" |
deb9225a RK |
1032 | "@ |
1033 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
1034 | {ai.|addic.} %3,%1,%2 |
1035 | # | |
1036 | #" | |
a62bfff2 | 1037 | [(set_attr "type" "fast_compare,compare,compare,compare") |
cb8cc086 MM |
1038 | (set_attr "length" "4,4,8,8")]) |
1039 | ||
1040 | (define_split | |
1041 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1042 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1043 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1044 | (const_int 0))) | |
1045 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 1046 | "TARGET_32BIT && reload_completed" |
cb8cc086 MM |
1047 | [(set (match_dup 3) |
1048 | (plus:SI (match_dup 1) | |
1049 | (match_dup 2))) | |
1050 | (set (match_dup 0) | |
1051 | (compare:CC (match_dup 3) | |
1052 | (const_int 0)))] | |
1053 | "") | |
7e69e155 | 1054 | |
7cd5235b | 1055 | (define_insn "*addsi3_internal3" |
cb8cc086 MM |
1056 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1057 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
1058 | (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1059 | (const_int 0))) |
cb8cc086 MM |
1060 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1061 | (plus:SI (match_dup 1) | |
1062 | (match_dup 2)))] | |
4b8a63d6 | 1063 | "TARGET_32BIT" |
deb9225a RK |
1064 | "@ |
1065 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
1066 | {ai.|addic.} %0,%1,%2 |
1067 | # | |
1068 | #" | |
a62bfff2 | 1069 | [(set_attr "type" "fast_compare,compare,compare,compare") |
cb8cc086 MM |
1070 | (set_attr "length" "4,4,8,8")]) |
1071 | ||
1072 | (define_split | |
1073 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1074 | (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1075 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1076 | (const_int 0))) | |
1077 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1078 | (plus:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 1079 | "TARGET_32BIT && reload_completed" |
cb8cc086 MM |
1080 | [(set (match_dup 0) |
1081 | (plus:SI (match_dup 1) | |
1082 | (match_dup 2))) | |
1083 | (set (match_dup 3) | |
1084 | (compare:CC (match_dup 0) | |
1085 | (const_int 0)))] | |
1086 | "") | |
7e69e155 | 1087 | |
f357808b RK |
1088 | ;; Split an add that we can't do in one insn into two insns, each of which |
1089 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
1090 | ;; add should be last in case the result gets used in an address. | |
1091 | ||
1092 | (define_split | |
cd2b37d9 RK |
1093 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1094 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
f357808b | 1095 | (match_operand:SI 2 "non_add_cint_operand" "")))] |
1fd4e8c1 | 1096 | "" |
f357808b RK |
1097 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) |
1098 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] | |
1099 | " | |
1fd4e8c1 | 1100 | { |
2bfcf297 | 1101 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 1102 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 1103 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); |
1fd4e8c1 | 1104 | |
2bfcf297 | 1105 | operands[3] = GEN_INT (rest); |
e6ca2c17 | 1106 | operands[4] = GEN_INT (low); |
1fd4e8c1 RK |
1107 | }") |
1108 | ||
8de2a197 | 1109 | (define_insn "one_cmplsi2" |
cd2b37d9 RK |
1110 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1111 | (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1112 | "" |
ca7f5001 RK |
1113 | "nor %0,%1,%1") |
1114 | ||
1115 | (define_insn "" | |
52d3af72 DE |
1116 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1117 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1118 | (const_int 0))) |
52d3af72 | 1119 | (clobber (match_scratch:SI 2 "=r,r"))] |
4b8a63d6 | 1120 | "TARGET_32BIT" |
52d3af72 DE |
1121 | "@ |
1122 | nor. %2,%1,%1 | |
1123 | #" | |
1124 | [(set_attr "type" "compare") | |
1125 | (set_attr "length" "4,8")]) | |
1126 | ||
1127 | (define_split | |
1128 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1129 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1130 | (const_int 0))) | |
1131 | (clobber (match_scratch:SI 2 ""))] | |
4b8a63d6 | 1132 | "TARGET_32BIT && reload_completed" |
52d3af72 DE |
1133 | [(set (match_dup 2) |
1134 | (not:SI (match_dup 1))) | |
1135 | (set (match_dup 0) | |
1136 | (compare:CC (match_dup 2) | |
1137 | (const_int 0)))] | |
1138 | "") | |
ca7f5001 RK |
1139 | |
1140 | (define_insn "" | |
52d3af72 DE |
1141 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1142 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1143 | (const_int 0))) |
52d3af72 | 1144 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1145 | (not:SI (match_dup 1)))] |
4b8a63d6 | 1146 | "TARGET_32BIT" |
52d3af72 DE |
1147 | "@ |
1148 | nor. %0,%1,%1 | |
1149 | #" | |
1150 | [(set_attr "type" "compare") | |
1151 | (set_attr "length" "4,8")]) | |
1152 | ||
1153 | (define_split | |
1154 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1155 | (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1156 | (const_int 0))) | |
1cb18e3c | 1157 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
52d3af72 | 1158 | (not:SI (match_dup 1)))] |
4b8a63d6 | 1159 | "TARGET_32BIT && reload_completed" |
52d3af72 DE |
1160 | [(set (match_dup 0) |
1161 | (not:SI (match_dup 1))) | |
1162 | (set (match_dup 2) | |
1163 | (compare:CC (match_dup 0) | |
1164 | (const_int 0)))] | |
1165 | "") | |
1fd4e8c1 RK |
1166 | |
1167 | (define_insn "" | |
3d91674b RK |
1168 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1169 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1170 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1171 | "! TARGET_POWERPC" |
ca7f5001 | 1172 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1173 | |
deb9225a RK |
1174 | (define_insn "" |
1175 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
1176 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") | |
1177 | (match_operand:SI 2 "gpc_reg_operand" "r,r")))] | |
1178 | "TARGET_POWERPC" | |
1179 | "@ | |
1180 | subf %0,%2,%1 | |
1181 | subfic %0,%2,%1") | |
1182 | ||
1fd4e8c1 | 1183 | (define_insn "" |
cb8cc086 MM |
1184 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1185 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1186 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1187 | (const_int 0))) |
cb8cc086 | 1188 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1189 | "! TARGET_POWERPC" |
cb8cc086 MM |
1190 | "@ |
1191 | {sf.|subfc.} %3,%2,%1 | |
1192 | #" | |
1193 | [(set_attr "type" "compare") | |
1194 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1195 | |
deb9225a | 1196 | (define_insn "" |
cb8cc086 MM |
1197 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1198 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1199 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1200 | (const_int 0))) |
cb8cc086 | 1201 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 1202 | "TARGET_POWERPC && TARGET_32BIT" |
cb8cc086 MM |
1203 | "@ |
1204 | subf. %3,%2,%1 | |
1205 | #" | |
a62bfff2 | 1206 | [(set_attr "type" "fast_compare") |
cb8cc086 MM |
1207 | (set_attr "length" "4,8")]) |
1208 | ||
1209 | (define_split | |
1210 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1211 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1212 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1213 | (const_int 0))) | |
1214 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 1215 | "TARGET_32BIT && reload_completed" |
cb8cc086 MM |
1216 | [(set (match_dup 3) |
1217 | (minus:SI (match_dup 1) | |
1218 | (match_dup 2))) | |
1219 | (set (match_dup 0) | |
1220 | (compare:CC (match_dup 3) | |
1221 | (const_int 0)))] | |
1222 | "") | |
deb9225a | 1223 | |
1fd4e8c1 | 1224 | (define_insn "" |
cb8cc086 MM |
1225 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1226 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1227 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1228 | (const_int 0))) |
cb8cc086 | 1229 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1230 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1231 | "! TARGET_POWERPC" |
cb8cc086 MM |
1232 | "@ |
1233 | {sf.|subfc.} %0,%2,%1 | |
1234 | #" | |
1235 | [(set_attr "type" "compare") | |
1236 | (set_attr "length" "4,8")]) | |
815cdc52 | 1237 | |
29ae5b89 | 1238 | (define_insn "" |
cb8cc086 MM |
1239 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1240 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1241 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1242 | (const_int 0))) |
cb8cc086 MM |
1243 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1244 | (minus:SI (match_dup 1) | |
1245 | (match_dup 2)))] | |
4b8a63d6 | 1246 | "TARGET_POWERPC && TARGET_32BIT" |
90612787 DE |
1247 | "@ |
1248 | subf. %0,%2,%1 | |
1249 | #" | |
a62bfff2 | 1250 | [(set_attr "type" "fast_compare") |
cb8cc086 MM |
1251 | (set_attr "length" "4,8")]) |
1252 | ||
1253 | (define_split | |
1254 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1255 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1256 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1257 | (const_int 0))) | |
1258 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1259 | (minus:SI (match_dup 1) | |
1260 | (match_dup 2)))] | |
4b8a63d6 | 1261 | "TARGET_32BIT && reload_completed" |
cb8cc086 MM |
1262 | [(set (match_dup 0) |
1263 | (minus:SI (match_dup 1) | |
1264 | (match_dup 2))) | |
1265 | (set (match_dup 3) | |
1266 | (compare:CC (match_dup 0) | |
1267 | (const_int 0)))] | |
1268 | "") | |
deb9225a | 1269 | |
1fd4e8c1 | 1270 | (define_expand "subsi3" |
cd2b37d9 | 1271 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1272 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") |
f6bf7de2 | 1273 | (match_operand:SI 2 "reg_or_arith_cint_operand" "")))] |
1fd4e8c1 | 1274 | "" |
a0044fb1 RK |
1275 | " |
1276 | { | |
1277 | if (GET_CODE (operands[2]) == CONST_INT) | |
1278 | { | |
1279 | emit_insn (gen_addsi3 (operands[0], operands[1], | |
1280 | negate_rtx (SImode, operands[2]))); | |
1281 | DONE; | |
1282 | } | |
1283 | }") | |
1fd4e8c1 RK |
1284 | |
1285 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
1286 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
1287 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
1288 | ;; combine. | |
1fd4e8c1 RK |
1289 | |
1290 | (define_expand "sminsi3" | |
1291 | [(set (match_dup 3) | |
cd2b37d9 | 1292 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1293 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1294 | (const_int 0) | |
1295 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1296 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1297 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 1298 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1299 | " |
a3170dc6 AH |
1300 | { |
1301 | if (TARGET_ISEL) | |
1302 | { | |
1303 | operands[2] = force_reg (SImode, operands[2]); | |
1304 | rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); | |
1305 | DONE; | |
1306 | } | |
1307 | ||
1308 | operands[3] = gen_reg_rtx (SImode); | |
1309 | }") | |
1fd4e8c1 | 1310 | |
95ac8e67 RK |
1311 | (define_split |
1312 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1313 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1314 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1315 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1316 | "TARGET_POWER" |
95ac8e67 RK |
1317 | [(set (match_dup 3) |
1318 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1319 | (const_int 0) | |
1320 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1321 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
1322 | "") | |
1323 | ||
1fd4e8c1 RK |
1324 | (define_expand "smaxsi3" |
1325 | [(set (match_dup 3) | |
cd2b37d9 | 1326 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1327 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1328 | (const_int 0) | |
1329 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1330 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1331 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 1332 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1333 | " |
a3170dc6 AH |
1334 | { |
1335 | if (TARGET_ISEL) | |
1336 | { | |
1337 | operands[2] = force_reg (SImode, operands[2]); | |
1338 | rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); | |
1339 | DONE; | |
1340 | } | |
1341 | operands[3] = gen_reg_rtx (SImode); | |
1342 | }") | |
1fd4e8c1 | 1343 | |
95ac8e67 RK |
1344 | (define_split |
1345 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1346 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1347 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1348 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1349 | "TARGET_POWER" |
95ac8e67 RK |
1350 | [(set (match_dup 3) |
1351 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1352 | (const_int 0) | |
1353 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1354 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
1355 | "") | |
1356 | ||
1fd4e8c1 | 1357 | (define_expand "uminsi3" |
cd2b37d9 | 1358 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1359 | (match_dup 5))) |
cd2b37d9 | 1360 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1361 | (match_dup 5))) |
1fd4e8c1 RK |
1362 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1363 | (const_int 0) | |
1364 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1365 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1366 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 1367 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1368 | " |
bb68ff55 | 1369 | { |
a3170dc6 AH |
1370 | if (TARGET_ISEL) |
1371 | { | |
1372 | rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]); | |
1373 | DONE; | |
1374 | } | |
bb68ff55 MM |
1375 | operands[3] = gen_reg_rtx (SImode); |
1376 | operands[4] = gen_reg_rtx (SImode); | |
1377 | operands[5] = GEN_INT (-2147483647 - 1); | |
1378 | }") | |
1fd4e8c1 RK |
1379 | |
1380 | (define_expand "umaxsi3" | |
cd2b37d9 | 1381 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1382 | (match_dup 5))) |
cd2b37d9 | 1383 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1384 | (match_dup 5))) |
1fd4e8c1 RK |
1385 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1386 | (const_int 0) | |
1387 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1388 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1389 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 1390 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1391 | " |
bb68ff55 | 1392 | { |
a3170dc6 AH |
1393 | if (TARGET_ISEL) |
1394 | { | |
1395 | rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]); | |
1396 | DONE; | |
1397 | } | |
bb68ff55 MM |
1398 | operands[3] = gen_reg_rtx (SImode); |
1399 | operands[4] = gen_reg_rtx (SImode); | |
1400 | operands[5] = GEN_INT (-2147483647 - 1); | |
1401 | }") | |
1fd4e8c1 RK |
1402 | |
1403 | (define_insn "" | |
cd2b37d9 RK |
1404 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1405 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 1406 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
1407 | (const_int 0) |
1408 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1409 | "TARGET_POWER" |
1fd4e8c1 RK |
1410 | "doz%I2 %0,%1,%2") |
1411 | ||
1412 | (define_insn "" | |
9ebbca7d | 1413 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1414 | (compare:CC |
9ebbca7d GK |
1415 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1416 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1417 | (const_int 0) |
1418 | (minus:SI (match_dup 2) (match_dup 1))) | |
1419 | (const_int 0))) | |
9ebbca7d | 1420 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 1421 | "TARGET_POWER" |
9ebbca7d GK |
1422 | "@ |
1423 | doz%I2. %3,%1,%2 | |
1424 | #" | |
1425 | [(set_attr "type" "delayed_compare") | |
1426 | (set_attr "length" "4,8")]) | |
1427 | ||
1428 | (define_split | |
1429 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1430 | (compare:CC | |
1431 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1432 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1433 | (const_int 0) | |
1434 | (minus:SI (match_dup 2) (match_dup 1))) | |
1435 | (const_int 0))) | |
1436 | (clobber (match_scratch:SI 3 ""))] | |
1437 | "TARGET_POWER && reload_completed" | |
1438 | [(set (match_dup 3) | |
1439 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1440 | (const_int 0) | |
1441 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1442 | (set (match_dup 0) | |
1443 | (compare:CC (match_dup 3) | |
1444 | (const_int 0)))] | |
1445 | "") | |
1fd4e8c1 RK |
1446 | |
1447 | (define_insn "" | |
9ebbca7d | 1448 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1449 | (compare:CC |
9ebbca7d GK |
1450 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1451 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1452 | (const_int 0) |
1453 | (minus:SI (match_dup 2) (match_dup 1))) | |
1454 | (const_int 0))) | |
9ebbca7d | 1455 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1456 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
1457 | (const_int 0) | |
1458 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1459 | "TARGET_POWER" |
9ebbca7d GK |
1460 | "@ |
1461 | doz%I2. %0,%1,%2 | |
1462 | #" | |
1463 | [(set_attr "type" "delayed_compare") | |
1464 | (set_attr "length" "4,8")]) | |
1465 | ||
1466 | (define_split | |
1467 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1468 | (compare:CC | |
1469 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1470 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1471 | (const_int 0) | |
1472 | (minus:SI (match_dup 2) (match_dup 1))) | |
1473 | (const_int 0))) | |
1474 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1475 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1476 | (const_int 0) | |
1477 | (minus:SI (match_dup 2) (match_dup 1))))] | |
1478 | "TARGET_POWER && reload_completed" | |
1479 | [(set (match_dup 0) | |
1480 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1481 | (const_int 0) | |
1482 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1483 | (set (match_dup 3) | |
1484 | (compare:CC (match_dup 0) | |
1485 | (const_int 0)))] | |
1486 | "") | |
1fd4e8c1 RK |
1487 | |
1488 | ;; We don't need abs with condition code because such comparisons should | |
1489 | ;; never be done. | |
ea9be077 MM |
1490 | (define_expand "abssi2" |
1491 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1492 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1493 | "" | |
1494 | " | |
1495 | { | |
a3170dc6 AH |
1496 | if (TARGET_ISEL) |
1497 | { | |
1498 | emit_insn (gen_abssi2_isel (operands[0], operands[1])); | |
1499 | DONE; | |
1500 | } | |
1501 | else if (! TARGET_POWER) | |
ea9be077 MM |
1502 | { |
1503 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
1504 | DONE; | |
1505 | } | |
1506 | }") | |
1507 | ||
ea112fc4 | 1508 | (define_insn "*abssi2_power" |
cd2b37d9 RK |
1509 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1510 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 1511 | "TARGET_POWER" |
1fd4e8c1 RK |
1512 | "abs %0,%1") |
1513 | ||
a3170dc6 AH |
1514 | (define_insn_and_split "abssi2_isel" |
1515 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1516 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8c48b6f5 | 1517 | (clobber (match_scratch:SI 2 "=&b")) |
a3170dc6 AH |
1518 | (clobber (match_scratch:CC 3 "=y"))] |
1519 | "TARGET_ISEL" | |
1520 | "#" | |
1521 | "&& reload_completed" | |
1522 | [(set (match_dup 2) (neg:SI (match_dup 1))) | |
1523 | (set (match_dup 3) | |
1524 | (compare:CC (match_dup 1) | |
1525 | (const_int 0))) | |
1526 | (set (match_dup 0) | |
1527 | (if_then_else:SI (ge (match_dup 3) | |
1528 | (const_int 0)) | |
1529 | (match_dup 1) | |
1530 | (match_dup 2)))] | |
1531 | "") | |
1532 | ||
ea112fc4 | 1533 | (define_insn_and_split "abssi2_nopower" |
ea9be077 | 1534 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 1535 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) |
ea9be077 | 1536 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
a3170dc6 | 1537 | "! TARGET_POWER && ! TARGET_ISEL" |
ea112fc4 DE |
1538 | "#" |
1539 | "&& reload_completed" | |
ea9be077 MM |
1540 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1541 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1542 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
1543 | "") |
1544 | ||
463b558b | 1545 | (define_insn "*nabs_power" |
cd2b37d9 RK |
1546 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1547 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 1548 | "TARGET_POWER" |
1fd4e8c1 RK |
1549 | "nabs %0,%1") |
1550 | ||
ea112fc4 | 1551 | (define_insn_and_split "*nabs_nopower" |
ea9be077 | 1552 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 1553 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) |
ea9be077 | 1554 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
0ad91047 | 1555 | "! TARGET_POWER" |
ea112fc4 DE |
1556 | "#" |
1557 | "&& reload_completed" | |
ea9be077 MM |
1558 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1559 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1560 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
1561 | "") |
1562 | ||
1fd4e8c1 | 1563 | (define_insn "negsi2" |
cd2b37d9 RK |
1564 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1565 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1566 | "" |
1567 | "neg %0,%1") | |
1568 | ||
1569 | (define_insn "" | |
9ebbca7d GK |
1570 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1571 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1572 | (const_int 0))) |
9ebbca7d | 1573 | (clobber (match_scratch:SI 2 "=r,r"))] |
4b8a63d6 | 1574 | "TARGET_32BIT" |
9ebbca7d GK |
1575 | "@ |
1576 | neg. %2,%1 | |
1577 | #" | |
a62bfff2 | 1578 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
1579 | (set_attr "length" "4,8")]) |
1580 | ||
1581 | (define_split | |
1582 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1583 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1584 | (const_int 0))) | |
1585 | (clobber (match_scratch:SI 2 ""))] | |
4b8a63d6 | 1586 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
1587 | [(set (match_dup 2) |
1588 | (neg:SI (match_dup 1))) | |
1589 | (set (match_dup 0) | |
1590 | (compare:CC (match_dup 2) | |
1591 | (const_int 0)))] | |
1592 | "") | |
1fd4e8c1 RK |
1593 | |
1594 | (define_insn "" | |
9ebbca7d GK |
1595 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1596 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1597 | (const_int 0))) |
9ebbca7d | 1598 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 1599 | (neg:SI (match_dup 1)))] |
4b8a63d6 | 1600 | "TARGET_32BIT" |
9ebbca7d GK |
1601 | "@ |
1602 | neg. %0,%1 | |
1603 | #" | |
a62bfff2 | 1604 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
1605 | (set_attr "length" "4,8")]) |
1606 | ||
1607 | (define_split | |
1608 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1609 | (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "")) | |
1610 | (const_int 0))) | |
1611 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1612 | (neg:SI (match_dup 1)))] | |
4b8a63d6 | 1613 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
1614 | [(set (match_dup 0) |
1615 | (neg:SI (match_dup 1))) | |
1616 | (set (match_dup 2) | |
1617 | (compare:CC (match_dup 0) | |
1618 | (const_int 0)))] | |
1619 | "") | |
1fd4e8c1 | 1620 | |
1b1edcfa DE |
1621 | (define_insn "clzsi2" |
1622 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1623 | (clz:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
1624 | "" | |
1625 | "{cntlz|cntlzw} %0,%1") | |
1626 | ||
1627 | (define_expand "ctzsi2" | |
4977bab6 | 1628 | [(set (match_dup 2) |
1b1edcfa | 1629 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
4977bab6 | 1630 | (parallel [(set (match_dup 3) (and:SI (match_dup 1) |
1b1edcfa DE |
1631 | (match_dup 2))) |
1632 | (clobber (scratch:CC))]) | |
d865b122 | 1633 | (set (match_dup 4) (clz:SI (match_dup 3))) |
4977bab6 | 1634 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1b1edcfa | 1635 | (minus:SI (const_int 31) (match_dup 4)))] |
1fd4e8c1 | 1636 | "" |
4977bab6 ZW |
1637 | { |
1638 | operands[2] = gen_reg_rtx (SImode); | |
1639 | operands[3] = gen_reg_rtx (SImode); | |
1640 | operands[4] = gen_reg_rtx (SImode); | |
1641 | }) | |
6ae08853 | 1642 | |
1b1edcfa DE |
1643 | (define_expand "ffssi2" |
1644 | [(set (match_dup 2) | |
1645 | (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
1646 | (parallel [(set (match_dup 3) (and:SI (match_dup 1) | |
1647 | (match_dup 2))) | |
1648 | (clobber (scratch:CC))]) | |
1649 | (set (match_dup 4) (clz:SI (match_dup 3))) | |
1650 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1651 | (minus:SI (const_int 32) (match_dup 4)))] | |
4977bab6 | 1652 | "" |
1b1edcfa DE |
1653 | { |
1654 | operands[2] = gen_reg_rtx (SImode); | |
1655 | operands[3] = gen_reg_rtx (SImode); | |
1656 | operands[4] = gen_reg_rtx (SImode); | |
1657 | }) | |
6ae08853 | 1658 | |
ca7f5001 RK |
1659 | (define_expand "mulsi3" |
1660 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1661 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
1662 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
1663 | "" | |
1664 | " | |
1665 | { | |
1666 | if (TARGET_POWER) | |
68b40e7e | 1667 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 1668 | else |
68b40e7e | 1669 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
1670 | DONE; |
1671 | }") | |
1672 | ||
68b40e7e | 1673 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
1674 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1675 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
1676 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
1677 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
1678 | "TARGET_POWER" |
1679 | "@ | |
1680 | {muls|mullw} %0,%1,%2 | |
1681 | {muli|mulli} %0,%1,%2" | |
6ae08853 | 1682 | [(set (attr "type") |
c859cda6 DJ |
1683 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") |
1684 | (const_string "imul3") | |
6ae08853 | 1685 | (match_operand:SI 2 "short_cint_operand" "") |
c859cda6 DJ |
1686 | (const_string "imul2")] |
1687 | (const_string "imul")))]) | |
ca7f5001 | 1688 | |
68b40e7e | 1689 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
1690 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1691 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1692 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 1693 | "! TARGET_POWER" |
1fd4e8c1 | 1694 | "@ |
d904e9ed RK |
1695 | {muls|mullw} %0,%1,%2 |
1696 | {muli|mulli} %0,%1,%2" | |
6ae08853 | 1697 | [(set (attr "type") |
c859cda6 DJ |
1698 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") |
1699 | (const_string "imul3") | |
6ae08853 | 1700 | (match_operand:SI 2 "short_cint_operand" "") |
c859cda6 DJ |
1701 | (const_string "imul2")] |
1702 | (const_string "imul")))]) | |
1fd4e8c1 | 1703 | |
9259f3b0 | 1704 | (define_insn "*mulsi3_mq_internal1" |
9ebbca7d GK |
1705 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1706 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1707 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1708 | (const_int 0))) |
9ebbca7d GK |
1709 | (clobber (match_scratch:SI 3 "=r,r")) |
1710 | (clobber (match_scratch:SI 4 "=q,q"))] | |
ca7f5001 | 1711 | "TARGET_POWER" |
9ebbca7d GK |
1712 | "@ |
1713 | {muls.|mullw.} %3,%1,%2 | |
1714 | #" | |
9259f3b0 | 1715 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1716 | (set_attr "length" "4,8")]) |
1717 | ||
1718 | (define_split | |
1719 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1720 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1721 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1722 | (const_int 0))) | |
1723 | (clobber (match_scratch:SI 3 "")) | |
1724 | (clobber (match_scratch:SI 4 ""))] | |
1725 | "TARGET_POWER && reload_completed" | |
1726 | [(parallel [(set (match_dup 3) | |
1727 | (mult:SI (match_dup 1) (match_dup 2))) | |
1728 | (clobber (match_dup 4))]) | |
1729 | (set (match_dup 0) | |
1730 | (compare:CC (match_dup 3) | |
1731 | (const_int 0)))] | |
1732 | "") | |
ca7f5001 | 1733 | |
9259f3b0 | 1734 | (define_insn "*mulsi3_no_mq_internal1" |
9ebbca7d GK |
1735 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1736 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1737 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1738 | (const_int 0))) |
9ebbca7d | 1739 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 1740 | "! TARGET_POWER" |
9ebbca7d GK |
1741 | "@ |
1742 | {muls.|mullw.} %3,%1,%2 | |
1743 | #" | |
9259f3b0 | 1744 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1745 | (set_attr "length" "4,8")]) |
1746 | ||
1747 | (define_split | |
1748 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1749 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1750 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1751 | (const_int 0))) | |
1752 | (clobber (match_scratch:SI 3 ""))] | |
1753 | "! TARGET_POWER && reload_completed" | |
1754 | [(set (match_dup 3) | |
1755 | (mult:SI (match_dup 1) (match_dup 2))) | |
1756 | (set (match_dup 0) | |
1757 | (compare:CC (match_dup 3) | |
1758 | (const_int 0)))] | |
1759 | "") | |
1fd4e8c1 | 1760 | |
9259f3b0 | 1761 | (define_insn "*mulsi3_mq_internal2" |
9ebbca7d GK |
1762 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1763 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1764 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1765 | (const_int 0))) |
9ebbca7d | 1766 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 1767 | (mult:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 1768 | (clobber (match_scratch:SI 4 "=q,q"))] |
ca7f5001 | 1769 | "TARGET_POWER" |
9ebbca7d GK |
1770 | "@ |
1771 | {muls.|mullw.} %0,%1,%2 | |
1772 | #" | |
9259f3b0 | 1773 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1774 | (set_attr "length" "4,8")]) |
1775 | ||
1776 | (define_split | |
1777 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1778 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1779 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1780 | (const_int 0))) | |
1781 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1782 | (mult:SI (match_dup 1) (match_dup 2))) | |
1783 | (clobber (match_scratch:SI 4 ""))] | |
1784 | "TARGET_POWER && reload_completed" | |
1785 | [(parallel [(set (match_dup 0) | |
1786 | (mult:SI (match_dup 1) (match_dup 2))) | |
1787 | (clobber (match_dup 4))]) | |
1788 | (set (match_dup 3) | |
1789 | (compare:CC (match_dup 0) | |
1790 | (const_int 0)))] | |
1791 | "") | |
ca7f5001 | 1792 | |
9259f3b0 | 1793 | (define_insn "*mulsi3_no_mq_internal2" |
9ebbca7d GK |
1794 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1795 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1796 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1797 | (const_int 0))) |
9ebbca7d | 1798 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 1799 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 1800 | "! TARGET_POWER" |
9ebbca7d GK |
1801 | "@ |
1802 | {muls.|mullw.} %0,%1,%2 | |
1803 | #" | |
9259f3b0 | 1804 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1805 | (set_attr "length" "4,8")]) |
1806 | ||
1807 | (define_split | |
1808 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1809 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1810 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1811 | (const_int 0))) | |
1812 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1813 | (mult:SI (match_dup 1) (match_dup 2)))] | |
1814 | "! TARGET_POWER && reload_completed" | |
1815 | [(set (match_dup 0) | |
1816 | (mult:SI (match_dup 1) (match_dup 2))) | |
1817 | (set (match_dup 3) | |
1818 | (compare:CC (match_dup 0) | |
1819 | (const_int 0)))] | |
1820 | "") | |
1fd4e8c1 RK |
1821 | |
1822 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
1823 | ;; 0 and remainder to operand 3. | |
1824 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
1825 | ||
8ffd9c51 RK |
1826 | (define_expand "divmodsi4" |
1827 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1828 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1829 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
bb157ff4 | 1830 | (set (match_operand:SI 3 "register_operand" "") |
8ffd9c51 RK |
1831 | (mod:SI (match_dup 1) (match_dup 2)))])] |
1832 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1833 | " | |
1834 | { | |
1835 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1836 | { | |
39403d82 DE |
1837 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1838 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1839 | emit_insn (gen_divss_call ()); |
39403d82 DE |
1840 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
1841 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
1842 | DONE; |
1843 | } | |
1844 | }") | |
deb9225a | 1845 | |
bb157ff4 | 1846 | (define_insn "*divmodsi4_internal" |
cd2b37d9 RK |
1847 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1848 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1849 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
bb157ff4 | 1850 | (set (match_operand:SI 3 "register_operand" "=q") |
1fd4e8c1 | 1851 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 1852 | "TARGET_POWER" |
cfb557c4 RK |
1853 | "divs %0,%1,%2" |
1854 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 1855 | |
8ffd9c51 RK |
1856 | (define_expand "udivsi3" |
1857 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1858 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1859 | (match_operand:SI 2 "gpc_reg_operand" "")))] | |
1860 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1861 | " | |
1862 | { | |
1863 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1864 | { | |
39403d82 DE |
1865 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1866 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1867 | emit_insn (gen_quous_call ()); |
39403d82 | 1868 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1869 | DONE; |
1870 | } | |
f192bf8b DE |
1871 | else if (TARGET_POWER) |
1872 | { | |
1873 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
1874 | DONE; | |
1875 | } | |
8ffd9c51 | 1876 | }") |
deb9225a | 1877 | |
f192bf8b DE |
1878 | (define_insn "udivsi3_mq" |
1879 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1880 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1881 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1882 | (clobber (match_scratch:SI 3 "=q"))] | |
1883 | "TARGET_POWERPC && TARGET_POWER" | |
1884 | "divwu %0,%1,%2" | |
1885 | [(set_attr "type" "idiv")]) | |
1886 | ||
1887 | (define_insn "*udivsi3_no_mq" | |
ca7f5001 RK |
1888 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1889 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1890 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 1891 | "TARGET_POWERPC && ! TARGET_POWER" |
a473029f | 1892 | "divwu %0,%1,%2" |
ca7f5001 RK |
1893 | [(set_attr "type" "idiv")]) |
1894 | ||
1fd4e8c1 | 1895 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 1896 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
1897 | ;; used; for PowerPC, force operands into register and do a normal divide; |
1898 | ;; for AIX common-mode, use quoss call on register operands. | |
1fd4e8c1 | 1899 | (define_expand "divsi3" |
cd2b37d9 RK |
1900 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
1901 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 RK |
1902 | (match_operand:SI 2 "reg_or_cint_operand" "")))] |
1903 | "" | |
1904 | " | |
1905 | { | |
ca7f5001 | 1906 | if (GET_CODE (operands[2]) == CONST_INT |
2bfcf297 | 1907 | && INTVAL (operands[2]) > 0 |
ca7f5001 RK |
1908 | && exact_log2 (INTVAL (operands[2])) >= 0) |
1909 | ; | |
b6c9286a | 1910 | else if (TARGET_POWERPC) |
f192bf8b DE |
1911 | { |
1912 | operands[2] = force_reg (SImode, operands[2]); | |
1913 | if (TARGET_POWER) | |
1914 | { | |
1915 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
1916 | DONE; | |
1917 | } | |
1918 | } | |
b6c9286a | 1919 | else if (TARGET_POWER) |
1fd4e8c1 | 1920 | FAIL; |
405c5495 | 1921 | else |
8ffd9c51 | 1922 | { |
39403d82 DE |
1923 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1924 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1925 | emit_insn (gen_quoss_call ()); |
39403d82 | 1926 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1927 | DONE; |
1928 | } | |
1fd4e8c1 RK |
1929 | }") |
1930 | ||
f192bf8b DE |
1931 | (define_insn "divsi3_mq" |
1932 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1933 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1934 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1935 | (clobber (match_scratch:SI 3 "=q"))] | |
1936 | "TARGET_POWERPC && TARGET_POWER" | |
1937 | "divw %0,%1,%2" | |
1938 | [(set_attr "type" "idiv")]) | |
1939 | ||
1940 | (define_insn "*divsi3_no_mq" | |
1941 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1942 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1943 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
1944 | "TARGET_POWERPC && ! TARGET_POWER" | |
1945 | "divw %0,%1,%2" | |
1946 | [(set_attr "type" "idiv")]) | |
1947 | ||
1fd4e8c1 | 1948 | (define_expand "modsi3" |
85644414 RK |
1949 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) |
1950 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
405c5495 | 1951 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] |
39b52ba2 | 1952 | "" |
1fd4e8c1 RK |
1953 | " |
1954 | { | |
481c7efa | 1955 | int i; |
39b52ba2 RK |
1956 | rtx temp1; |
1957 | rtx temp2; | |
1958 | ||
2bfcf297 | 1959 | if (GET_CODE (operands[2]) != CONST_INT |
a65c591c | 1960 | || INTVAL (operands[2]) <= 0 |
2bfcf297 | 1961 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) |
39b52ba2 RK |
1962 | FAIL; |
1963 | ||
1964 | temp1 = gen_reg_rtx (SImode); | |
1965 | temp2 = gen_reg_rtx (SImode); | |
1fd4e8c1 | 1966 | |
85644414 | 1967 | emit_insn (gen_divsi3 (temp1, operands[1], operands[2])); |
39b52ba2 | 1968 | emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i))); |
85644414 RK |
1969 | emit_insn (gen_subsi3 (operands[0], operands[1], temp2)); |
1970 | DONE; | |
1fd4e8c1 RK |
1971 | }") |
1972 | ||
1973 | (define_insn "" | |
cd2b37d9 RK |
1974 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1975 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
1976 | (match_operand:SI 2 "exact_log2_cint_operand" "N")))] |
1977 | "" | |
ca7f5001 | 1978 | "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0" |
b19003d8 | 1979 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
1980 | |
1981 | (define_insn "" | |
9ebbca7d GK |
1982 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1983 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 1984 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 1985 | (const_int 0))) |
9ebbca7d | 1986 | (clobber (match_scratch:SI 3 "=r,r"))] |
2bfcf297 | 1987 | "" |
9ebbca7d GK |
1988 | "@ |
1989 | {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3 | |
1990 | #" | |
b19003d8 | 1991 | [(set_attr "type" "compare") |
9ebbca7d GK |
1992 | (set_attr "length" "8,12")]) |
1993 | ||
1994 | (define_split | |
1995 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1996 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 1997 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
1998 | (const_int 0))) |
1999 | (clobber (match_scratch:SI 3 ""))] | |
2bfcf297 | 2000 | "reload_completed" |
9ebbca7d GK |
2001 | [(set (match_dup 3) |
2002 | (div:SI (match_dup 1) (match_dup 2))) | |
2003 | (set (match_dup 0) | |
2004 | (compare:CC (match_dup 3) | |
2005 | (const_int 0)))] | |
2006 | "") | |
1fd4e8c1 RK |
2007 | |
2008 | (define_insn "" | |
9ebbca7d GK |
2009 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
2010 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 2011 | (match_operand:SI 2 "exact_log2_cint_operand" "N,N")) |
b6b12107 | 2012 | (const_int 0))) |
9ebbca7d | 2013 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 2014 | (div:SI (match_dup 1) (match_dup 2)))] |
2bfcf297 | 2015 | "" |
9ebbca7d GK |
2016 | "@ |
2017 | {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0 | |
2018 | #" | |
b19003d8 | 2019 | [(set_attr "type" "compare") |
9ebbca7d GK |
2020 | (set_attr "length" "8,12")]) |
2021 | ||
2022 | (define_split | |
2023 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2024 | (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2bfcf297 | 2025 | (match_operand:SI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
2026 | (const_int 0))) |
2027 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2028 | (div:SI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 2029 | "reload_completed" |
9ebbca7d GK |
2030 | [(set (match_dup 0) |
2031 | (div:SI (match_dup 1) (match_dup 2))) | |
2032 | (set (match_dup 3) | |
2033 | (compare:CC (match_dup 0) | |
2034 | (const_int 0)))] | |
2035 | "") | |
1fd4e8c1 RK |
2036 | |
2037 | (define_insn "" | |
cd2b37d9 | 2038 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2039 | (udiv:SI |
996a5f59 | 2040 | (plus:DI (ashift:DI |
cd2b37d9 | 2041 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 2042 | (const_int 32)) |
23a900dc | 2043 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 2044 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 2045 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 2046 | (umod:SI |
996a5f59 | 2047 | (plus:DI (ashift:DI |
1fd4e8c1 | 2048 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 2049 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 2050 | (match_dup 3)))] |
ca7f5001 | 2051 | "TARGET_POWER" |
cfb557c4 RK |
2052 | "div %0,%1,%3" |
2053 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
2054 | |
2055 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
2056 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
2057 | ;; have to worry about the branches. So make a few subroutines here. | |
2058 | ;; | |
2059 | ;; First comes the normal case. | |
2060 | (define_expand "udivmodsi4_normal" | |
2061 | [(set (match_dup 4) (const_int 0)) | |
2062 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 2063 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2064 | (const_int 32)) |
2065 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
2066 | (match_operand:SI 2 "" ""))) | |
2067 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 2068 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2069 | (const_int 32)) |
2070 | (zero_extend:DI (match_dup 1))) | |
2071 | (match_dup 2)))])] | |
ca7f5001 | 2072 | "TARGET_POWER" |
1fd4e8c1 RK |
2073 | " |
2074 | { operands[4] = gen_reg_rtx (SImode); }") | |
2075 | ||
2076 | ;; This handles the branches. | |
2077 | (define_expand "udivmodsi4_tests" | |
2078 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
2079 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
2080 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
2081 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
2082 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
2083 | (set (match_dup 0) (const_int 1)) | |
2084 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
2085 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
2086 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
2087 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 2088 | "TARGET_POWER" |
1fd4e8c1 RK |
2089 | " |
2090 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
2091 | operands[6] = gen_reg_rtx (CCmode); | |
2092 | }") | |
2093 | ||
2094 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
2095 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2096 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 2097 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 2098 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 2099 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 2100 | "" |
1fd4e8c1 RK |
2101 | " |
2102 | { | |
2103 | rtx label = 0; | |
2104 | ||
8ffd9c51 | 2105 | if (! TARGET_POWER) |
c4d38ccb MM |
2106 | { |
2107 | if (! TARGET_POWERPC) | |
2108 | { | |
39403d82 DE |
2109 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2110 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 2111 | emit_insn (gen_divus_call ()); |
39403d82 DE |
2112 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2113 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
2114 | DONE; |
2115 | } | |
2116 | else | |
2117 | FAIL; | |
2118 | } | |
0081a354 | 2119 | |
1fd4e8c1 RK |
2120 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
2121 | { | |
2122 | operands[2] = force_reg (SImode, operands[2]); | |
2123 | label = gen_label_rtx (); | |
2124 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
2125 | operands[3], label)); | |
2126 | } | |
2127 | else | |
2128 | operands[2] = force_reg (SImode, operands[2]); | |
2129 | ||
2130 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
2131 | operands[3])); | |
2132 | if (label) | |
2133 | emit_label (label); | |
2134 | ||
2135 | DONE; | |
2136 | }") | |
0081a354 | 2137 | |
fada905b MM |
2138 | ;; AIX architecture-independent common-mode multiply (DImode), |
2139 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
2140 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
2141 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
2142 | ;; assumed unused if generating common-mode, so ignore. | |
2143 | (define_insn "mulh_call" | |
2144 | [(set (reg:SI 3) | |
2145 | (truncate:SI | |
2146 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
2147 | (sign_extend:DI (reg:SI 4))) | |
2148 | (const_int 32)))) | |
cf27b467 | 2149 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 2150 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2151 | "bla __mulh" |
2152 | [(set_attr "type" "imul")]) | |
fada905b MM |
2153 | |
2154 | (define_insn "mull_call" | |
2155 | [(set (reg:DI 3) | |
2156 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
2157 | (sign_extend:DI (reg:SI 4)))) | |
2158 | (clobber (match_scratch:SI 0 "=l")) | |
2159 | (clobber (reg:SI 0))] | |
2160 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2161 | "bla __mull" |
2162 | [(set_attr "type" "imul")]) | |
fada905b MM |
2163 | |
2164 | (define_insn "divss_call" | |
2165 | [(set (reg:SI 3) | |
2166 | (div:SI (reg:SI 3) (reg:SI 4))) | |
2167 | (set (reg:SI 4) | |
2168 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
2169 | (clobber (match_scratch:SI 0 "=l")) | |
2170 | (clobber (reg:SI 0))] | |
2171 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2172 | "bla __divss" |
2173 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2174 | |
2175 | (define_insn "divus_call" | |
8ffd9c51 RK |
2176 | [(set (reg:SI 3) |
2177 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2178 | (set (reg:SI 4) | |
2179 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
2180 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
2181 | (clobber (reg:SI 0)) |
2182 | (clobber (match_scratch:CC 1 "=x")) | |
2183 | (clobber (reg:CC 69))] | |
2184 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2185 | "bla __divus" |
2186 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2187 | |
2188 | (define_insn "quoss_call" | |
2189 | [(set (reg:SI 3) | |
2190 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 2191 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 2192 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2193 | "bla __quoss" |
2194 | [(set_attr "type" "idiv")]) | |
0081a354 | 2195 | |
fada905b MM |
2196 | (define_insn "quous_call" |
2197 | [(set (reg:SI 3) | |
2198 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2199 | (clobber (match_scratch:SI 0 "=l")) | |
2200 | (clobber (reg:SI 0)) | |
2201 | (clobber (match_scratch:CC 1 "=x")) | |
2202 | (clobber (reg:CC 69))] | |
2203 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2204 | "bla __quous" |
2205 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 2206 | \f |
bb21487f | 2207 | ;; Logical instructions |
dfbdccdb GK |
2208 | ;; The logical instructions are mostly combined by using match_operator, |
2209 | ;; but the plain AND insns are somewhat different because there is no | |
2210 | ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all | |
2211 | ;; those rotate-and-mask operations. Thus, the AND insns come first. | |
2212 | ||
29ae5b89 JL |
2213 | (define_insn "andsi3" |
2214 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
2215 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
5f59ecb7 | 2216 | (match_operand:SI 2 "and_operand" "?r,T,K,L"))) |
29ae5b89 | 2217 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] |
1fd4e8c1 RK |
2218 | "" |
2219 | "@ | |
2220 | and %0,%1,%2 | |
ca7f5001 RK |
2221 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
2222 | {andil.|andi.} %0,%1,%b2 | |
520308bc DE |
2223 | {andiu.|andis.} %0,%1,%u2" |
2224 | [(set_attr "type" "*,*,compare,compare")]) | |
52d3af72 DE |
2225 | |
2226 | ;; Note to set cr's other than cr0 we do the and immediate and then | |
0ba1b2ff | 2227 | ;; the test again -- this avoids a mfcr which on the higher end |
52d3af72 | 2228 | ;; machines causes an execution serialization |
1fd4e8c1 | 2229 | |
7cd5235b | 2230 | (define_insn "*andsi3_internal2" |
52d3af72 DE |
2231 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2232 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2233 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
1fd4e8c1 | 2234 | (const_int 0))) |
52d3af72 DE |
2235 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) |
2236 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
4b8a63d6 | 2237 | "TARGET_32BIT" |
1fd4e8c1 RK |
2238 | "@ |
2239 | and. %3,%1,%2 | |
ca7f5001 RK |
2240 | {andil.|andi.} %3,%1,%b2 |
2241 | {andiu.|andis.} %3,%1,%u2 | |
52d3af72 DE |
2242 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 |
2243 | # | |
2244 | # | |
2245 | # | |
2246 | #" | |
2247 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2248 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1fd4e8c1 | 2249 | |
0ba1b2ff AM |
2250 | (define_insn "*andsi3_internal3" |
2251 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2252 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2253 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2254 | (const_int 0))) | |
2255 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) | |
2256 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
683bdff7 | 2257 | "TARGET_64BIT" |
0ba1b2ff AM |
2258 | "@ |
2259 | # | |
2260 | {andil.|andi.} %3,%1,%b2 | |
2261 | {andiu.|andis.} %3,%1,%u2 | |
2262 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 | |
2263 | # | |
2264 | # | |
2265 | # | |
2266 | #" | |
2267 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2268 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2269 | ||
52d3af72 DE |
2270 | (define_split |
2271 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
2272 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2273 | (match_operand:SI 2 "and_operand" "")) | |
1fd4e8c1 | 2274 | (const_int 0))) |
52d3af72 DE |
2275 | (clobber (match_scratch:SI 3 "")) |
2276 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 2277 | "reload_completed" |
52d3af72 DE |
2278 | [(parallel [(set (match_dup 3) |
2279 | (and:SI (match_dup 1) | |
2280 | (match_dup 2))) | |
2281 | (clobber (match_dup 4))]) | |
2282 | (set (match_dup 0) | |
2283 | (compare:CC (match_dup 3) | |
2284 | (const_int 0)))] | |
2285 | "") | |
2286 | ||
0ba1b2ff AM |
2287 | ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the |
2288 | ;; whole 64 bit reg, and we don't know what is in the high 32 bits. | |
2289 | ||
2290 | (define_split | |
2291 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
2292 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2293 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2294 | (const_int 0))) | |
2295 | (clobber (match_scratch:SI 3 "")) | |
2296 | (clobber (match_scratch:CC 4 ""))] | |
2297 | "TARGET_POWERPC64 && reload_completed" | |
2298 | [(parallel [(set (match_dup 3) | |
2299 | (and:SI (match_dup 1) | |
2300 | (match_dup 2))) | |
2301 | (clobber (match_dup 4))]) | |
2302 | (set (match_dup 0) | |
2303 | (compare:CC (match_dup 3) | |
2304 | (const_int 0)))] | |
2305 | "") | |
2306 | ||
2307 | (define_insn "*andsi3_internal4" | |
52d3af72 DE |
2308 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2309 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2310 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
52d3af72 DE |
2311 | (const_int 0))) |
2312 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2313 | (and:SI (match_dup 1) | |
2314 | (match_dup 2))) | |
2315 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
4b8a63d6 | 2316 | "TARGET_32BIT" |
1fd4e8c1 RK |
2317 | "@ |
2318 | and. %0,%1,%2 | |
ca7f5001 RK |
2319 | {andil.|andi.} %0,%1,%b2 |
2320 | {andiu.|andis.} %0,%1,%u2 | |
52d3af72 DE |
2321 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 |
2322 | # | |
2323 | # | |
2324 | # | |
2325 | #" | |
2326 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2327 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
2328 | ||
0ba1b2ff AM |
2329 | (define_insn "*andsi3_internal5" |
2330 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2331 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2332 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2333 | (const_int 0))) | |
2334 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2335 | (and:SI (match_dup 1) | |
2336 | (match_dup 2))) | |
2337 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
683bdff7 | 2338 | "TARGET_64BIT" |
0ba1b2ff AM |
2339 | "@ |
2340 | # | |
2341 | {andil.|andi.} %0,%1,%b2 | |
2342 | {andiu.|andis.} %0,%1,%u2 | |
2343 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 | |
2344 | # | |
2345 | # | |
2346 | # | |
2347 | #" | |
2348 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2349 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2350 | ||
52d3af72 DE |
2351 | (define_split |
2352 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2353 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2354 | (match_operand:SI 2 "and_operand" "")) | |
2355 | (const_int 0))) | |
2356 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2357 | (and:SI (match_dup 1) | |
2358 | (match_dup 2))) | |
2359 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 2360 | "reload_completed" |
52d3af72 DE |
2361 | [(parallel [(set (match_dup 0) |
2362 | (and:SI (match_dup 1) | |
2363 | (match_dup 2))) | |
2364 | (clobber (match_dup 4))]) | |
2365 | (set (match_dup 3) | |
2366 | (compare:CC (match_dup 0) | |
2367 | (const_int 0)))] | |
2368 | "") | |
1fd4e8c1 | 2369 | |
0ba1b2ff AM |
2370 | (define_split |
2371 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
2372 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2373 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2374 | (const_int 0))) | |
2375 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2376 | (and:SI (match_dup 1) | |
2377 | (match_dup 2))) | |
2378 | (clobber (match_scratch:CC 4 ""))] | |
2379 | "TARGET_POWERPC64 && reload_completed" | |
2380 | [(parallel [(set (match_dup 0) | |
2381 | (and:SI (match_dup 1) | |
2382 | (match_dup 2))) | |
2383 | (clobber (match_dup 4))]) | |
2384 | (set (match_dup 3) | |
2385 | (compare:CC (match_dup 0) | |
2386 | (const_int 0)))] | |
2387 | "") | |
2388 | ||
2389 | ;; Handle the PowerPC64 rlwinm corner case | |
2390 | ||
2391 | (define_insn_and_split "*andsi3_internal6" | |
2392 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2393 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2394 | (match_operand:SI 2 "mask_operand_wrap" "i")))] | |
2395 | "TARGET_POWERPC64" | |
2396 | "#" | |
2397 | "TARGET_POWERPC64" | |
2398 | [(set (match_dup 0) | |
2399 | (and:SI (rotate:SI (match_dup 1) (match_dup 3)) | |
2400 | (match_dup 4))) | |
2401 | (set (match_dup 0) | |
2402 | (rotate:SI (match_dup 0) (match_dup 5)))] | |
2403 | " | |
2404 | { | |
2405 | int mb = extract_MB (operands[2]); | |
2406 | int me = extract_ME (operands[2]); | |
2407 | operands[3] = GEN_INT (me + 1); | |
2408 | operands[5] = GEN_INT (32 - (me + 1)); | |
2409 | operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
2410 | }" | |
2411 | [(set_attr "length" "8")]) | |
2412 | ||
2413 | (define_insn_and_split "*andsi3_internal7" | |
2414 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") | |
2415 | (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r") | |
2416 | (match_operand:SI 1 "mask_operand_wrap" "i,i")) | |
2417 | (const_int 0))) | |
2418 | (clobber (match_scratch:SI 3 "=r,r"))] | |
2419 | "TARGET_POWERPC64" | |
2420 | "#" | |
2421 | "TARGET_POWERPC64" | |
2422 | [(parallel [(set (match_dup 2) | |
2423 | (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4)) | |
2424 | (match_dup 5)) | |
2425 | (const_int 0))) | |
2426 | (clobber (match_dup 3))])] | |
2427 | " | |
2428 | { | |
2429 | int mb = extract_MB (operands[1]); | |
2430 | int me = extract_ME (operands[1]); | |
2431 | operands[4] = GEN_INT (me + 1); | |
2432 | operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
2433 | }" | |
2434 | [(set_attr "type" "delayed_compare,compare") | |
2435 | (set_attr "length" "4,8")]) | |
2436 | ||
2437 | (define_insn_and_split "*andsi3_internal8" | |
2438 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y") | |
2439 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
2440 | (match_operand:SI 2 "mask_operand_wrap" "i,i")) | |
2441 | (const_int 0))) | |
2442 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
2443 | (and:SI (match_dup 1) | |
2444 | (match_dup 2)))] | |
2445 | "TARGET_POWERPC64" | |
2446 | "#" | |
2447 | "TARGET_POWERPC64" | |
bba11b5f | 2448 | [(set (match_dup 0) |
0ba1b2ff | 2449 | (and:SI (rotate:SI (match_dup 1) (match_dup 4)) |
bba11b5f FJ |
2450 | (match_dup 5))) |
2451 | (parallel [(set (match_dup 3) | |
2452 | (compare:CC (rotate:SI (match_dup 0) (match_dup 6)) | |
2453 | (const_int 0))) | |
2454 | (set (match_dup 0) | |
2455 | (rotate:SI (match_dup 0) (match_dup 6)))])] | |
0ba1b2ff AM |
2456 | " |
2457 | { | |
2458 | int mb = extract_MB (operands[2]); | |
2459 | int me = extract_ME (operands[2]); | |
2460 | operands[4] = GEN_INT (me + 1); | |
2461 | operands[6] = GEN_INT (32 - (me + 1)); | |
2462 | operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
2463 | }" | |
2464 | [(set_attr "type" "delayed_compare,compare") | |
2465 | (set_attr "length" "8,12")]) | |
2466 | ||
7cd5235b | 2467 | (define_expand "iorsi3" |
cd2b37d9 | 2468 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2469 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2470 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
7cd5235b | 2471 | "" |
f357808b RK |
2472 | " |
2473 | { | |
7cd5235b | 2474 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2475 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2476 | { |
2477 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2478 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2479 | ? operands[0] : gen_reg_rtx (SImode)); |
2480 | ||
a260abc9 DE |
2481 | emit_insn (gen_iorsi3 (tmp, operands[1], |
2482 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2483 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2484 | DONE; |
2485 | } | |
f357808b RK |
2486 | }") |
2487 | ||
7cd5235b | 2488 | (define_expand "xorsi3" |
cd2b37d9 | 2489 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2490 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2491 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
1fd4e8c1 | 2492 | "" |
7cd5235b | 2493 | " |
1fd4e8c1 | 2494 | { |
7cd5235b | 2495 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2496 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2497 | { |
2498 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2499 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2500 | ? operands[0] : gen_reg_rtx (SImode)); |
2501 | ||
a260abc9 DE |
2502 | emit_insn (gen_xorsi3 (tmp, operands[1], |
2503 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2504 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2505 | DONE; |
2506 | } | |
1fd4e8c1 RK |
2507 | }") |
2508 | ||
dfbdccdb | 2509 | (define_insn "*boolsi3_internal1" |
7cd5235b | 2510 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 2511 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2512 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") |
2513 | (match_operand:SI 2 "logical_operand" "r,K,L")]))] | |
1fd4e8c1 RK |
2514 | "" |
2515 | "@ | |
dfbdccdb GK |
2516 | %q3 %0,%1,%2 |
2517 | {%q3il|%q3i} %0,%1,%b2 | |
2518 | {%q3iu|%q3is} %0,%1,%u2") | |
1fd4e8c1 | 2519 | |
dfbdccdb | 2520 | (define_insn "*boolsi3_internal2" |
52d3af72 | 2521 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 2522 | (compare:CC (match_operator:SI 4 "boolean_or_operator" |
dfbdccdb GK |
2523 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") |
2524 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2525 | (const_int 0))) | |
52d3af72 | 2526 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2527 | "TARGET_32BIT" |
52d3af72 | 2528 | "@ |
dfbdccdb | 2529 | %q4. %3,%1,%2 |
52d3af72 DE |
2530 | #" |
2531 | [(set_attr "type" "compare") | |
2532 | (set_attr "length" "4,8")]) | |
2533 | ||
2534 | (define_split | |
2535 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2536 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2537 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2538 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2539 | (const_int 0))) |
52d3af72 | 2540 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2541 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2542 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2543 | (set (match_dup 0) |
2544 | (compare:CC (match_dup 3) | |
2545 | (const_int 0)))] | |
2546 | "") | |
815cdc52 | 2547 | |
dfbdccdb | 2548 | (define_insn "*boolsi3_internal3" |
52d3af72 | 2549 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2550 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2551 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2552 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2553 | (const_int 0))) | |
52d3af72 | 2554 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2555 | (match_dup 4))] |
4b8a63d6 | 2556 | "TARGET_32BIT" |
52d3af72 | 2557 | "@ |
dfbdccdb | 2558 | %q4. %0,%1,%2 |
52d3af72 DE |
2559 | #" |
2560 | [(set_attr "type" "compare") | |
2561 | (set_attr "length" "4,8")]) | |
2562 | ||
2563 | (define_split | |
e72247f4 | 2564 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2565 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2566 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2567 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2568 | (const_int 0))) |
75540af0 | 2569 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2570 | (match_dup 4))] |
4b8a63d6 | 2571 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2572 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2573 | (set (match_dup 3) |
2574 | (compare:CC (match_dup 0) | |
2575 | (const_int 0)))] | |
2576 | "") | |
1fd4e8c1 | 2577 | |
6ae08853 | 2578 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 2579 | ;; each of which does one 16-bit part. This is used by combine. |
a260abc9 DE |
2580 | |
2581 | (define_split | |
2582 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1d328b19 | 2583 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2584 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2585 | (match_operand:SI 2 "non_logical_cint_operand" "")]))] | |
a260abc9 | 2586 | "" |
dfbdccdb GK |
2587 | [(set (match_dup 0) (match_dup 4)) |
2588 | (set (match_dup 0) (match_dup 5))] | |
a260abc9 DE |
2589 | " |
2590 | { | |
dfbdccdb GK |
2591 | rtx i; |
2592 | i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
1c563bed | 2593 | operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
0f4c242b | 2594 | operands[1], i); |
dfbdccdb | 2595 | i = GEN_INT (INTVAL (operands[2]) & 0xffff); |
1c563bed | 2596 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
0f4c242b | 2597 | operands[0], i); |
a260abc9 DE |
2598 | }") |
2599 | ||
dfbdccdb | 2600 | (define_insn "*boolcsi3_internal1" |
cd2b37d9 | 2601 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2602 | (match_operator:SI 3 "boolean_operator" |
2603 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2604 | (match_operand:SI 2 "gpc_reg_operand" "r")]))] |
1fd4e8c1 | 2605 | "" |
dfbdccdb | 2606 | "%q3 %0,%2,%1") |
1fd4e8c1 | 2607 | |
dfbdccdb | 2608 | (define_insn "*boolcsi3_internal2" |
52d3af72 | 2609 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2610 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2611 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2612 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2613 | (const_int 0))) | |
52d3af72 | 2614 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2615 | "TARGET_32BIT" |
52d3af72 | 2616 | "@ |
dfbdccdb | 2617 | %q4. %3,%2,%1 |
52d3af72 DE |
2618 | #" |
2619 | [(set_attr "type" "compare") | |
2620 | (set_attr "length" "4,8")]) | |
2621 | ||
2622 | (define_split | |
2623 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2624 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2625 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2626 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2627 | (const_int 0))) |
52d3af72 | 2628 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2629 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2630 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2631 | (set (match_dup 0) |
2632 | (compare:CC (match_dup 3) | |
2633 | (const_int 0)))] | |
2634 | "") | |
1fd4e8c1 | 2635 | |
dfbdccdb | 2636 | (define_insn "*boolcsi3_internal3" |
52d3af72 | 2637 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2638 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2639 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2640 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2641 | (const_int 0))) | |
52d3af72 | 2642 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2643 | (match_dup 4))] |
4b8a63d6 | 2644 | "TARGET_32BIT" |
52d3af72 | 2645 | "@ |
dfbdccdb | 2646 | %q4. %0,%2,%1 |
52d3af72 DE |
2647 | #" |
2648 | [(set_attr "type" "compare") | |
2649 | (set_attr "length" "4,8")]) | |
2650 | ||
2651 | (define_split | |
e72247f4 | 2652 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2653 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2654 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2655 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2656 | (const_int 0))) |
75540af0 | 2657 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2658 | (match_dup 4))] |
4b8a63d6 | 2659 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2660 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2661 | (set (match_dup 3) |
2662 | (compare:CC (match_dup 0) | |
2663 | (const_int 0)))] | |
2664 | "") | |
2665 | ||
dfbdccdb | 2666 | (define_insn "*boolccsi3_internal1" |
cd2b37d9 | 2667 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2668 | (match_operator:SI 3 "boolean_operator" |
2669 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2670 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))] |
1fd4e8c1 | 2671 | "" |
dfbdccdb | 2672 | "%q3 %0,%1,%2") |
1fd4e8c1 | 2673 | |
dfbdccdb | 2674 | (define_insn "*boolccsi3_internal2" |
52d3af72 | 2675 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2676 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2677 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2678 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2679 | (const_int 0))) | |
52d3af72 | 2680 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2681 | "TARGET_32BIT" |
52d3af72 | 2682 | "@ |
dfbdccdb | 2683 | %q4. %3,%1,%2 |
52d3af72 DE |
2684 | #" |
2685 | [(set_attr "type" "compare") | |
2686 | (set_attr "length" "4,8")]) | |
2687 | ||
2688 | (define_split | |
2689 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2690 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2691 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2692 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2693 | (const_int 0))) |
52d3af72 | 2694 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2695 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2696 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2697 | (set (match_dup 0) |
2698 | (compare:CC (match_dup 3) | |
2699 | (const_int 0)))] | |
2700 | "") | |
1fd4e8c1 | 2701 | |
dfbdccdb | 2702 | (define_insn "*boolccsi3_internal3" |
52d3af72 | 2703 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2704 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2705 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2706 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2707 | (const_int 0))) | |
52d3af72 | 2708 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2709 | (match_dup 4))] |
4b8a63d6 | 2710 | "TARGET_32BIT" |
52d3af72 | 2711 | "@ |
dfbdccdb | 2712 | %q4. %0,%1,%2 |
52d3af72 DE |
2713 | #" |
2714 | [(set_attr "type" "compare") | |
2715 | (set_attr "length" "4,8")]) | |
2716 | ||
2717 | (define_split | |
e72247f4 | 2718 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2719 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2720 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2721 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2722 | (const_int 0))) |
75540af0 | 2723 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2724 | (match_dup 4))] |
4b8a63d6 | 2725 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2726 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2727 | (set (match_dup 3) |
2728 | (compare:CC (match_dup 0) | |
2729 | (const_int 0)))] | |
2730 | "") | |
1fd4e8c1 RK |
2731 | |
2732 | ;; maskir insn. We need four forms because things might be in arbitrary | |
2733 | ;; orders. Don't define forms that only set CR fields because these | |
2734 | ;; would modify an input register. | |
2735 | ||
7cd5235b | 2736 | (define_insn "*maskir_internal1" |
cd2b37d9 | 2737 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2738 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2739 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
2740 | (and:SI (match_dup 2) | |
cd2b37d9 | 2741 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 2742 | "TARGET_POWER" |
01def764 | 2743 | "maskir %0,%3,%2") |
1fd4e8c1 | 2744 | |
7cd5235b | 2745 | (define_insn "*maskir_internal2" |
242e8072 | 2746 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2747 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2748 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 2749 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 2750 | (match_dup 2))))] |
ca7f5001 | 2751 | "TARGET_POWER" |
01def764 | 2752 | "maskir %0,%3,%2") |
1fd4e8c1 | 2753 | |
7cd5235b | 2754 | (define_insn "*maskir_internal3" |
cd2b37d9 | 2755 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 2756 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 2757 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
2758 | (and:SI (not:SI (match_dup 2)) |
2759 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2760 | "TARGET_POWER" |
01def764 | 2761 | "maskir %0,%3,%2") |
1fd4e8c1 | 2762 | |
7cd5235b | 2763 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
2764 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2765 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
2766 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
2767 | (and:SI (not:SI (match_dup 2)) | |
2768 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2769 | "TARGET_POWER" |
01def764 | 2770 | "maskir %0,%3,%2") |
1fd4e8c1 | 2771 | |
7cd5235b | 2772 | (define_insn "*maskir_internal5" |
9ebbca7d | 2773 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2774 | (compare:CC |
9ebbca7d GK |
2775 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2776 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
01def764 | 2777 | (and:SI (match_dup 2) |
9ebbca7d | 2778 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 2779 | (const_int 0))) |
9ebbca7d | 2780 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2781 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2782 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 2783 | "TARGET_POWER" |
9ebbca7d GK |
2784 | "@ |
2785 | maskir. %0,%3,%2 | |
2786 | #" | |
2787 | [(set_attr "type" "compare") | |
2788 | (set_attr "length" "4,8")]) | |
2789 | ||
2790 | (define_split | |
2791 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2792 | (compare:CC | |
2793 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2794 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2795 | (and:SI (match_dup 2) | |
2796 | (match_operand:SI 3 "gpc_reg_operand" ""))) | |
2797 | (const_int 0))) | |
2798 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2799 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2800 | (and:SI (match_dup 2) (match_dup 3))))] | |
2801 | "TARGET_POWER && reload_completed" | |
2802 | [(set (match_dup 0) | |
2803 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2804 | (and:SI (match_dup 2) (match_dup 3)))) | |
2805 | (set (match_dup 4) | |
2806 | (compare:CC (match_dup 0) | |
2807 | (const_int 0)))] | |
2808 | "") | |
1fd4e8c1 | 2809 | |
7cd5235b | 2810 | (define_insn "*maskir_internal6" |
9ebbca7d | 2811 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2812 | (compare:CC |
9ebbca7d GK |
2813 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2814 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
2815 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") | |
01def764 | 2816 | (match_dup 2))) |
1fd4e8c1 | 2817 | (const_int 0))) |
9ebbca7d | 2818 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2819 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2820 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 2821 | "TARGET_POWER" |
9ebbca7d GK |
2822 | "@ |
2823 | maskir. %0,%3,%2 | |
2824 | #" | |
2825 | [(set_attr "type" "compare") | |
2826 | (set_attr "length" "4,8")]) | |
2827 | ||
2828 | (define_split | |
2829 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2830 | (compare:CC | |
2831 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2832 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2833 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
2834 | (match_dup 2))) | |
2835 | (const_int 0))) | |
2836 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2837 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2838 | (and:SI (match_dup 3) (match_dup 2))))] | |
2839 | "TARGET_POWER && reload_completed" | |
2840 | [(set (match_dup 0) | |
2841 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2842 | (and:SI (match_dup 3) (match_dup 2)))) | |
2843 | (set (match_dup 4) | |
2844 | (compare:CC (match_dup 0) | |
2845 | (const_int 0)))] | |
2846 | "") | |
1fd4e8c1 | 2847 | |
7cd5235b | 2848 | (define_insn "*maskir_internal7" |
9ebbca7d | 2849 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
815cdc52 | 2850 | (compare:CC |
9ebbca7d GK |
2851 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") |
2852 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
815cdc52 | 2853 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 2854 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
815cdc52 | 2855 | (const_int 0))) |
9ebbca7d | 2856 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
2857 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
2858 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2859 | "TARGET_POWER" | |
9ebbca7d GK |
2860 | "@ |
2861 | maskir. %0,%3,%2 | |
2862 | #" | |
2863 | [(set_attr "type" "compare") | |
2864 | (set_attr "length" "4,8")]) | |
2865 | ||
2866 | (define_split | |
2867 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2868 | (compare:CC | |
2869 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") | |
2870 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
2871 | (and:SI (not:SI (match_dup 2)) | |
2872 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2873 | (const_int 0))) | |
2874 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2875 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
2876 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2877 | "TARGET_POWER && reload_completed" | |
2878 | [(set (match_dup 0) | |
2879 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
2880 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
2881 | (set (match_dup 4) | |
2882 | (compare:CC (match_dup 0) | |
2883 | (const_int 0)))] | |
2884 | "") | |
1fd4e8c1 | 2885 | |
7cd5235b | 2886 | (define_insn "*maskir_internal8" |
9ebbca7d | 2887 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2888 | (compare:CC |
9ebbca7d GK |
2889 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") |
2890 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
01def764 | 2891 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 2892 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
1fd4e8c1 | 2893 | (const_int 0))) |
9ebbca7d | 2894 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2895 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
2896 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 2897 | "TARGET_POWER" |
9ebbca7d GK |
2898 | "@ |
2899 | maskir. %0,%3,%2 | |
2900 | #" | |
2901 | [(set_attr "type" "compare") | |
2902 | (set_attr "length" "4,8")]) | |
fcce224d | 2903 | |
9ebbca7d GK |
2904 | (define_split |
2905 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2906 | (compare:CC | |
2907 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
2908 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2909 | (and:SI (not:SI (match_dup 2)) | |
2910 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2911 | (const_int 0))) | |
2912 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2913 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
2914 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2915 | "TARGET_POWER && reload_completed" | |
2916 | [(set (match_dup 0) | |
2917 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
2918 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
2919 | (set (match_dup 4) | |
2920 | (compare:CC (match_dup 0) | |
2921 | (const_int 0)))] | |
2922 | "") | |
fcce224d | 2923 | \f |
1fd4e8c1 RK |
2924 | ;; Rotate and shift insns, in all their variants. These support shifts, |
2925 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 | 2926 | (define_expand "insv" |
0ad91047 DE |
2927 | [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") |
2928 | (match_operand:SI 1 "const_int_operand" "") | |
2929 | (match_operand:SI 2 "const_int_operand" "")) | |
2930 | (match_operand 3 "gpc_reg_operand" ""))] | |
034c1be0 MM |
2931 | "" |
2932 | " | |
2933 | { | |
2934 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
2935 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
2936 | compiler if the address of the structure is taken later. */ | |
2937 | if (GET_CODE (operands[0]) == SUBREG | |
2938 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
2939 | FAIL; | |
a78e33fc DE |
2940 | |
2941 | if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) | |
2942 | emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); | |
2943 | else | |
2944 | emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); | |
2945 | DONE; | |
034c1be0 MM |
2946 | }") |
2947 | ||
a78e33fc | 2948 | (define_insn "insvsi" |
cd2b37d9 | 2949 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
2950 | (match_operand:SI 1 "const_int_operand" "i") |
2951 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 2952 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
2953 | "" |
2954 | "* | |
2955 | { | |
2956 | int start = INTVAL (operands[2]) & 31; | |
2957 | int size = INTVAL (operands[1]) & 31; | |
2958 | ||
89e9f3a8 MM |
2959 | operands[4] = GEN_INT (32 - start - size); |
2960 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2961 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2962 | }" |
2963 | [(set_attr "type" "insert_word")]) | |
1fd4e8c1 | 2964 | |
a78e33fc | 2965 | (define_insn "*insvsi_internal1" |
d56d506a RK |
2966 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2967 | (match_operand:SI 1 "const_int_operand" "i") | |
2968 | (match_operand:SI 2 "const_int_operand" "i")) | |
2969 | (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2970 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2971 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2972 | "* |
2973 | { | |
2974 | int shift = INTVAL (operands[4]) & 31; | |
2975 | int start = INTVAL (operands[2]) & 31; | |
2976 | int size = INTVAL (operands[1]) & 31; | |
2977 | ||
89e9f3a8 MM |
2978 | operands[4] = GEN_INT (shift - start - size); |
2979 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2980 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
2981 | }" |
2982 | [(set_attr "type" "insert_word")]) | |
d56d506a | 2983 | |
a78e33fc | 2984 | (define_insn "*insvsi_internal2" |
d56d506a RK |
2985 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
2986 | (match_operand:SI 1 "const_int_operand" "i") | |
2987 | (match_operand:SI 2 "const_int_operand" "i")) | |
2988 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
2989 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 2990 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
2991 | "* |
2992 | { | |
2993 | int shift = INTVAL (operands[4]) & 31; | |
2994 | int start = INTVAL (operands[2]) & 31; | |
2995 | int size = INTVAL (operands[1]) & 31; | |
2996 | ||
89e9f3a8 MM |
2997 | operands[4] = GEN_INT (32 - shift - start - size); |
2998 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 2999 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
3000 | }" |
3001 | [(set_attr "type" "insert_word")]) | |
d56d506a | 3002 | |
a78e33fc | 3003 | (define_insn "*insvsi_internal3" |
d56d506a RK |
3004 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3005 | (match_operand:SI 1 "const_int_operand" "i") | |
3006 | (match_operand:SI 2 "const_int_operand" "i")) | |
3007 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3008 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 3009 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3010 | "* |
3011 | { | |
3012 | int shift = INTVAL (operands[4]) & 31; | |
3013 | int start = INTVAL (operands[2]) & 31; | |
3014 | int size = INTVAL (operands[1]) & 31; | |
3015 | ||
89e9f3a8 MM |
3016 | operands[4] = GEN_INT (32 - shift - start - size); |
3017 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3018 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
3019 | }" |
3020 | [(set_attr "type" "insert_word")]) | |
d56d506a | 3021 | |
a78e33fc | 3022 | (define_insn "*insvsi_internal4" |
d56d506a RK |
3023 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3024 | (match_operand:SI 1 "const_int_operand" "i") | |
3025 | (match_operand:SI 2 "const_int_operand" "i")) | |
3026 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3027 | (match_operand:SI 4 "const_int_operand" "i") | |
3028 | (match_operand:SI 5 "const_int_operand" "i")))] | |
3029 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
3030 | "* | |
3031 | { | |
3032 | int extract_start = INTVAL (operands[5]) & 31; | |
3033 | int extract_size = INTVAL (operands[4]) & 31; | |
3034 | int insert_start = INTVAL (operands[2]) & 31; | |
3035 | int insert_size = INTVAL (operands[1]) & 31; | |
3036 | ||
3037 | /* Align extract field with insert field */ | |
3a598fbe | 3038 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 3039 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 3040 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
8e8238f1 DE |
3041 | }" |
3042 | [(set_attr "type" "insert_word")]) | |
d56d506a | 3043 | |
f241bf89 EC |
3044 | ;; combine patterns for rlwimi |
3045 | (define_insn "*insvsi_internal5" | |
3046 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
3047 | (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0") | |
3048 | (match_operand:SI 1 "mask_operand" "i")) | |
3049 | (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3050 | (match_operand:SI 2 "const_int_operand" "i")) | |
3051 | (match_operand:SI 5 "mask_operand" "i"))))] | |
3052 | "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])" | |
3053 | "* | |
3054 | { | |
3055 | int me = extract_ME(operands[5]); | |
3056 | int mb = extract_MB(operands[5]); | |
3057 | operands[4] = GEN_INT(32 - INTVAL(operands[2])); | |
3058 | operands[2] = GEN_INT(mb); | |
3059 | operands[1] = GEN_INT(me); | |
3060 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; | |
3061 | }" | |
3062 | [(set_attr "type" "insert_word")]) | |
3063 | ||
3064 | (define_insn "*insvsi_internal6" | |
3065 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
3066 | (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3067 | (match_operand:SI 2 "const_int_operand" "i")) | |
3068 | (match_operand:SI 5 "mask_operand" "i")) | |
3069 | (and:SI (match_operand:SI 4 "gpc_reg_operand" "0") | |
3070 | (match_operand:SI 1 "mask_operand" "i"))))] | |
3071 | "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])" | |
3072 | "* | |
3073 | { | |
3074 | int me = extract_ME(operands[5]); | |
3075 | int mb = extract_MB(operands[5]); | |
3076 | operands[4] = GEN_INT(32 - INTVAL(operands[2])); | |
3077 | operands[2] = GEN_INT(mb); | |
3078 | operands[1] = GEN_INT(me); | |
3079 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; | |
3080 | }" | |
3081 | [(set_attr "type" "insert_word")]) | |
3082 | ||
a78e33fc | 3083 | (define_insn "insvdi" |
685f3906 | 3084 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") |
a78e33fc DE |
3085 | (match_operand:SI 1 "const_int_operand" "i") |
3086 | (match_operand:SI 2 "const_int_operand" "i")) | |
685f3906 DE |
3087 | (match_operand:DI 3 "gpc_reg_operand" "r"))] |
3088 | "TARGET_POWERPC64" | |
3089 | "* | |
3090 | { | |
3091 | int start = INTVAL (operands[2]) & 63; | |
3092 | int size = INTVAL (operands[1]) & 63; | |
3093 | ||
a78e33fc DE |
3094 | operands[1] = GEN_INT (64 - start - size); |
3095 | return \"rldimi %0,%3,%H1,%H2\"; | |
685f3906 DE |
3096 | }") |
3097 | ||
11ac38b2 DE |
3098 | (define_insn "*insvdi_internal2" |
3099 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") | |
3100 | (match_operand:SI 1 "const_int_operand" "i") | |
3101 | (match_operand:SI 2 "const_int_operand" "i")) | |
3102 | (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r") | |
3103 | (match_operand:SI 4 "const_int_operand" "i")))] | |
3104 | "TARGET_POWERPC64 | |
3105 | && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])" | |
3106 | "* | |
3107 | { | |
3108 | int shift = INTVAL (operands[4]) & 63; | |
3109 | int start = (INTVAL (operands[2]) & 63) - 32; | |
3110 | int size = INTVAL (operands[1]) & 63; | |
3111 | ||
3112 | operands[4] = GEN_INT (64 - shift - start - size); | |
3113 | operands[2] = GEN_INT (start); | |
3114 | operands[1] = GEN_INT (start + size - 1); | |
3115 | return \"rlwimi %0,%3,%h4,%h2,%h1\"; | |
3116 | }") | |
3117 | ||
3118 | (define_insn "*insvdi_internal3" | |
3119 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") | |
3120 | (match_operand:SI 1 "const_int_operand" "i") | |
3121 | (match_operand:SI 2 "const_int_operand" "i")) | |
3122 | (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r") | |
3123 | (match_operand:SI 4 "const_int_operand" "i")))] | |
3124 | "TARGET_POWERPC64 | |
3125 | && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])" | |
3126 | "* | |
3127 | { | |
3128 | int shift = INTVAL (operands[4]) & 63; | |
3129 | int start = (INTVAL (operands[2]) & 63) - 32; | |
3130 | int size = INTVAL (operands[1]) & 63; | |
3131 | ||
3132 | operands[4] = GEN_INT (64 - shift - start - size); | |
3133 | operands[2] = GEN_INT (start); | |
3134 | operands[1] = GEN_INT (start + size - 1); | |
3135 | return \"rlwimi %0,%3,%h4,%h2,%h1\"; | |
3136 | }") | |
3137 | ||
034c1be0 | 3138 | (define_expand "extzv" |
0ad91047 DE |
3139 | [(set (match_operand 0 "gpc_reg_operand" "") |
3140 | (zero_extract (match_operand 1 "gpc_reg_operand" "") | |
3141 | (match_operand:SI 2 "const_int_operand" "") | |
3142 | (match_operand:SI 3 "const_int_operand" "")))] | |
034c1be0 MM |
3143 | "" |
3144 | " | |
3145 | { | |
3146 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3147 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3148 | compiler if the address of the structure is taken later. */ | |
3149 | if (GET_CODE (operands[0]) == SUBREG | |
3150 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3151 | FAIL; | |
a78e33fc DE |
3152 | |
3153 | if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) | |
3154 | emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); | |
3155 | else | |
3156 | emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); | |
3157 | DONE; | |
034c1be0 MM |
3158 | }") |
3159 | ||
a78e33fc | 3160 | (define_insn "extzvsi" |
cd2b37d9 RK |
3161 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3162 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3163 | (match_operand:SI 2 "const_int_operand" "i") |
3164 | (match_operand:SI 3 "const_int_operand" "i")))] | |
3165 | "" | |
3166 | "* | |
3167 | { | |
3168 | int start = INTVAL (operands[3]) & 31; | |
3169 | int size = INTVAL (operands[2]) & 31; | |
3170 | ||
3171 | if (start + size >= 32) | |
3172 | operands[3] = const0_rtx; | |
3173 | else | |
89e9f3a8 | 3174 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3175 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
3176 | }") |
3177 | ||
a78e33fc | 3178 | (define_insn "*extzvsi_internal1" |
9ebbca7d GK |
3179 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3180 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3181 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3182 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3183 | (const_int 0))) |
9ebbca7d | 3184 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3185 | "" |
1fd4e8c1 RK |
3186 | "* |
3187 | { | |
3188 | int start = INTVAL (operands[3]) & 31; | |
3189 | int size = INTVAL (operands[2]) & 31; | |
3190 | ||
9ebbca7d GK |
3191 | /* Force split for non-cc0 compare. */ |
3192 | if (which_alternative == 1) | |
3193 | return \"#\"; | |
3194 | ||
43a88a8c | 3195 | /* If the bit-field being tested fits in the upper or lower half of a |
a7a975e1 RK |
3196 | word, it is possible to use andiu. or andil. to test it. This is |
3197 | useful because the condition register set-use delay is smaller for | |
3198 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
3199 | position is 0 because the LT and GT bits may be set wrong. */ | |
3200 | ||
3201 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 3202 | { |
3a598fbe | 3203 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
3204 | - (1 << (16 - (start & 15) - size)))); |
3205 | if (start < 16) | |
ca7f5001 | 3206 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 3207 | else |
ca7f5001 | 3208 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 3209 | } |
7e69e155 | 3210 | |
1fd4e8c1 RK |
3211 | if (start + size >= 32) |
3212 | operands[3] = const0_rtx; | |
3213 | else | |
89e9f3a8 | 3214 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3215 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 3216 | }" |
9ebbca7d GK |
3217 | [(set_attr "type" "compare") |
3218 | (set_attr "length" "4,8")]) | |
3219 | ||
3220 | (define_split | |
3221 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3222 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3223 | (match_operand:SI 2 "const_int_operand" "") | |
3224 | (match_operand:SI 3 "const_int_operand" "")) | |
3225 | (const_int 0))) | |
3226 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3227 | "reload_completed" |
9ebbca7d GK |
3228 | [(set (match_dup 4) |
3229 | (zero_extract:SI (match_dup 1) (match_dup 2) | |
3230 | (match_dup 3))) | |
3231 | (set (match_dup 0) | |
3232 | (compare:CC (match_dup 4) | |
3233 | (const_int 0)))] | |
3234 | "") | |
1fd4e8c1 | 3235 | |
a78e33fc | 3236 | (define_insn "*extzvsi_internal2" |
9ebbca7d GK |
3237 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3238 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3239 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3240 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3241 | (const_int 0))) |
9ebbca7d | 3242 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3243 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
ce71f754 | 3244 | "" |
1fd4e8c1 RK |
3245 | "* |
3246 | { | |
3247 | int start = INTVAL (operands[3]) & 31; | |
3248 | int size = INTVAL (operands[2]) & 31; | |
3249 | ||
9ebbca7d GK |
3250 | /* Force split for non-cc0 compare. */ |
3251 | if (which_alternative == 1) | |
3252 | return \"#\"; | |
3253 | ||
bc401279 | 3254 | /* Since we are using the output value, we can't ignore any need for |
43a88a8c | 3255 | a shift. The bit-field must end at the LSB. */ |
bc401279 | 3256 | if (start >= 16 && start + size == 32) |
df031c43 | 3257 | { |
bc401279 AM |
3258 | operands[3] = GEN_INT ((1 << size) - 1); |
3259 | return \"{andil.|andi.} %0,%1,%3\"; | |
df031c43 | 3260 | } |
7e69e155 | 3261 | |
1fd4e8c1 RK |
3262 | if (start + size >= 32) |
3263 | operands[3] = const0_rtx; | |
3264 | else | |
89e9f3a8 | 3265 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3266 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 | 3267 | }" |
ce71f754 | 3268 | [(set_attr "type" "compare") |
9ebbca7d GK |
3269 | (set_attr "length" "4,8")]) |
3270 | ||
3271 | (define_split | |
3272 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3273 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3274 | (match_operand:SI 2 "const_int_operand" "") | |
3275 | (match_operand:SI 3 "const_int_operand" "")) | |
3276 | (const_int 0))) | |
3277 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3278 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] | |
ce71f754 | 3279 | "reload_completed" |
9ebbca7d GK |
3280 | [(set (match_dup 0) |
3281 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) | |
3282 | (set (match_dup 4) | |
3283 | (compare:CC (match_dup 0) | |
3284 | (const_int 0)))] | |
3285 | "") | |
1fd4e8c1 | 3286 | |
a78e33fc | 3287 | (define_insn "extzvdi" |
685f3906 DE |
3288 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
3289 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3290 | (match_operand:SI 2 "const_int_operand" "i") |
3291 | (match_operand:SI 3 "const_int_operand" "i")))] | |
685f3906 DE |
3292 | "TARGET_POWERPC64" |
3293 | "* | |
3294 | { | |
3295 | int start = INTVAL (operands[3]) & 63; | |
3296 | int size = INTVAL (operands[2]) & 63; | |
3297 | ||
3298 | if (start + size >= 64) | |
3299 | operands[3] = const0_rtx; | |
3300 | else | |
89e9f3a8 MM |
3301 | operands[3] = GEN_INT (start + size); |
3302 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3303 | return \"rldicl %0,%1,%3,%2\"; |
3304 | }") | |
3305 | ||
a78e33fc | 3306 | (define_insn "*extzvdi_internal1" |
29ae5b89 JL |
3307 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
3308 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3309 | (match_operand:SI 2 "const_int_operand" "i") |
3310 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3311 | (const_int 0))) |
29ae5b89 | 3312 | (clobber (match_scratch:DI 4 "=r"))] |
683bdff7 | 3313 | "TARGET_64BIT" |
685f3906 DE |
3314 | "* |
3315 | { | |
3316 | int start = INTVAL (operands[3]) & 63; | |
3317 | int size = INTVAL (operands[2]) & 63; | |
3318 | ||
3319 | if (start + size >= 64) | |
3320 | operands[3] = const0_rtx; | |
3321 | else | |
89e9f3a8 MM |
3322 | operands[3] = GEN_INT (start + size); |
3323 | operands[2] = GEN_INT (64 - size); | |
685f3906 | 3324 | return \"rldicl. %4,%1,%3,%2\"; |
9a3c428b DE |
3325 | }" |
3326 | [(set_attr "type" "compare")]) | |
685f3906 | 3327 | |
a78e33fc | 3328 | (define_insn "*extzvdi_internal2" |
29ae5b89 JL |
3329 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
3330 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3331 | (match_operand:SI 2 "const_int_operand" "i") |
3332 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3333 | (const_int 0))) |
29ae5b89 | 3334 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 | 3335 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
683bdff7 | 3336 | "TARGET_64BIT" |
685f3906 DE |
3337 | "* |
3338 | { | |
3339 | int start = INTVAL (operands[3]) & 63; | |
3340 | int size = INTVAL (operands[2]) & 63; | |
3341 | ||
3342 | if (start + size >= 64) | |
3343 | operands[3] = const0_rtx; | |
3344 | else | |
89e9f3a8 MM |
3345 | operands[3] = GEN_INT (start + size); |
3346 | operands[2] = GEN_INT (64 - size); | |
685f3906 | 3347 | return \"rldicl. %0,%1,%3,%2\"; |
9a3c428b DE |
3348 | }" |
3349 | [(set_attr "type" "compare")]) | |
685f3906 | 3350 | |
1fd4e8c1 | 3351 | (define_insn "rotlsi3" |
cd2b37d9 RK |
3352 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3353 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3354 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
3355 | "" | |
ca7f5001 | 3356 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 3357 | |
a260abc9 | 3358 | (define_insn "*rotlsi3_internal2" |
9ebbca7d GK |
3359 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3360 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3361 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3362 | (const_int 0))) |
9ebbca7d | 3363 | (clobber (match_scratch:SI 3 "=r,r"))] |
ce71f754 | 3364 | "" |
9ebbca7d GK |
3365 | "@ |
3366 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff | |
3367 | #" | |
3368 | [(set_attr "type" "delayed_compare") | |
3369 | (set_attr "length" "4,8")]) | |
3370 | ||
3371 | (define_split | |
3372 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3373 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3374 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3375 | (const_int 0))) | |
3376 | (clobber (match_scratch:SI 3 ""))] | |
ce71f754 | 3377 | "reload_completed" |
9ebbca7d GK |
3378 | [(set (match_dup 3) |
3379 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3380 | (set (match_dup 0) | |
3381 | (compare:CC (match_dup 3) | |
3382 | (const_int 0)))] | |
3383 | "") | |
1fd4e8c1 | 3384 | |
a260abc9 | 3385 | (define_insn "*rotlsi3_internal3" |
9ebbca7d GK |
3386 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3387 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3388 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3389 | (const_int 0))) |
9ebbca7d | 3390 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3391 | (rotate:SI (match_dup 1) (match_dup 2)))] |
ce71f754 | 3392 | "" |
9ebbca7d GK |
3393 | "@ |
3394 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff | |
3395 | #" | |
3396 | [(set_attr "type" "delayed_compare") | |
3397 | (set_attr "length" "4,8")]) | |
3398 | ||
3399 | (define_split | |
3400 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3401 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3402 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3403 | (const_int 0))) | |
3404 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3405 | (rotate:SI (match_dup 1) (match_dup 2)))] | |
ce71f754 | 3406 | "reload_completed" |
9ebbca7d GK |
3407 | [(set (match_dup 0) |
3408 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3409 | (set (match_dup 3) | |
3410 | (compare:CC (match_dup 0) | |
3411 | (const_int 0)))] | |
3412 | "") | |
1fd4e8c1 | 3413 | |
a260abc9 | 3414 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
3415 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3416 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3417 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
ce71f754 | 3418 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3419 | "" |
ca7f5001 | 3420 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 3421 | |
a260abc9 | 3422 | (define_insn "*rotlsi3_internal5" |
9ebbca7d | 3423 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3424 | (compare:CC (and:SI |
9ebbca7d GK |
3425 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3426 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 3427 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3428 | (const_int 0))) |
9ebbca7d | 3429 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3430 | "" |
9ebbca7d GK |
3431 | "@ |
3432 | {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 | |
3433 | #" | |
3434 | [(set_attr "type" "delayed_compare") | |
3435 | (set_attr "length" "4,8")]) | |
3436 | ||
3437 | (define_split | |
3438 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3439 | (compare:CC (and:SI | |
3440 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3441 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3442 | (match_operand:SI 3 "mask_operand" "")) | |
3443 | (const_int 0))) | |
3444 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3445 | "reload_completed" |
9ebbca7d GK |
3446 | [(set (match_dup 4) |
3447 | (and:SI (rotate:SI (match_dup 1) | |
3448 | (match_dup 2)) | |
3449 | (match_dup 3))) | |
3450 | (set (match_dup 0) | |
3451 | (compare:CC (match_dup 4) | |
3452 | (const_int 0)))] | |
3453 | "") | |
1fd4e8c1 | 3454 | |
a260abc9 | 3455 | (define_insn "*rotlsi3_internal6" |
9ebbca7d | 3456 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3457 | (compare:CC (and:SI |
9ebbca7d GK |
3458 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3459 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 3460 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3461 | (const_int 0))) |
9ebbca7d | 3462 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3463 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3464 | "" |
9ebbca7d GK |
3465 | "@ |
3466 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 | |
3467 | #" | |
3468 | [(set_attr "type" "delayed_compare") | |
3469 | (set_attr "length" "4,8")]) | |
3470 | ||
3471 | (define_split | |
3472 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3473 | (compare:CC (and:SI | |
3474 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3475 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3476 | (match_operand:SI 3 "mask_operand" "")) | |
3477 | (const_int 0))) | |
3478 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3479 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 3480 | "reload_completed" |
9ebbca7d GK |
3481 | [(set (match_dup 0) |
3482 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3483 | (set (match_dup 4) | |
3484 | (compare:CC (match_dup 0) | |
3485 | (const_int 0)))] | |
3486 | "") | |
1fd4e8c1 | 3487 | |
a260abc9 | 3488 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 3489 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3490 | (zero_extend:SI |
3491 | (subreg:QI | |
cd2b37d9 | 3492 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3493 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3494 | "" | |
ca7f5001 | 3495 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 3496 | |
a260abc9 | 3497 | (define_insn "*rotlsi3_internal8" |
9ebbca7d | 3498 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3499 | (compare:CC (zero_extend:SI |
3500 | (subreg:QI | |
9ebbca7d GK |
3501 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3502 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3503 | (const_int 0))) |
9ebbca7d | 3504 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3505 | "" |
9ebbca7d GK |
3506 | "@ |
3507 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff | |
3508 | #" | |
3509 | [(set_attr "type" "delayed_compare") | |
3510 | (set_attr "length" "4,8")]) | |
3511 | ||
3512 | (define_split | |
3513 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3514 | (compare:CC (zero_extend:SI | |
3515 | (subreg:QI | |
3516 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3517 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3518 | (const_int 0))) | |
3519 | (clobber (match_scratch:SI 3 ""))] | |
3520 | "reload_completed" | |
3521 | [(set (match_dup 3) | |
3522 | (zero_extend:SI (subreg:QI | |
3523 | (rotate:SI (match_dup 1) | |
3524 | (match_dup 2)) 0))) | |
3525 | (set (match_dup 0) | |
3526 | (compare:CC (match_dup 3) | |
3527 | (const_int 0)))] | |
3528 | "") | |
1fd4e8c1 | 3529 | |
a260abc9 | 3530 | (define_insn "*rotlsi3_internal9" |
9ebbca7d | 3531 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3532 | (compare:CC (zero_extend:SI |
3533 | (subreg:QI | |
9ebbca7d GK |
3534 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3535 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3536 | (const_int 0))) |
9ebbca7d | 3537 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3538 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3539 | "" | |
9ebbca7d GK |
3540 | "@ |
3541 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff | |
3542 | #" | |
3543 | [(set_attr "type" "delayed_compare") | |
3544 | (set_attr "length" "4,8")]) | |
3545 | ||
3546 | (define_split | |
3547 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3548 | (compare:CC (zero_extend:SI | |
3549 | (subreg:QI | |
3550 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3551 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3552 | (const_int 0))) | |
3553 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3554 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3555 | "reload_completed" | |
3556 | [(set (match_dup 0) | |
3557 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3558 | (set (match_dup 3) | |
3559 | (compare:CC (match_dup 0) | |
3560 | (const_int 0)))] | |
3561 | "") | |
1fd4e8c1 | 3562 | |
a260abc9 | 3563 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 3564 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3565 | (zero_extend:SI |
3566 | (subreg:HI | |
cd2b37d9 | 3567 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3568 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3569 | "" | |
ca7f5001 | 3570 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 3571 | |
a260abc9 | 3572 | (define_insn "*rotlsi3_internal11" |
9ebbca7d | 3573 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3574 | (compare:CC (zero_extend:SI |
3575 | (subreg:HI | |
9ebbca7d GK |
3576 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3577 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3578 | (const_int 0))) |
9ebbca7d | 3579 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3580 | "" |
9ebbca7d GK |
3581 | "@ |
3582 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff | |
3583 | #" | |
3584 | [(set_attr "type" "delayed_compare") | |
3585 | (set_attr "length" "4,8")]) | |
3586 | ||
3587 | (define_split | |
3588 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3589 | (compare:CC (zero_extend:SI | |
3590 | (subreg:HI | |
3591 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3592 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3593 | (const_int 0))) | |
3594 | (clobber (match_scratch:SI 3 ""))] | |
3595 | "reload_completed" | |
3596 | [(set (match_dup 3) | |
3597 | (zero_extend:SI (subreg:HI | |
3598 | (rotate:SI (match_dup 1) | |
3599 | (match_dup 2)) 0))) | |
3600 | (set (match_dup 0) | |
3601 | (compare:CC (match_dup 3) | |
3602 | (const_int 0)))] | |
3603 | "") | |
1fd4e8c1 | 3604 | |
a260abc9 | 3605 | (define_insn "*rotlsi3_internal12" |
9ebbca7d | 3606 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3607 | (compare:CC (zero_extend:SI |
3608 | (subreg:HI | |
9ebbca7d GK |
3609 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3610 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3611 | (const_int 0))) |
9ebbca7d | 3612 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3613 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3614 | "" | |
9ebbca7d GK |
3615 | "@ |
3616 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff | |
3617 | #" | |
3618 | [(set_attr "type" "delayed_compare") | |
3619 | (set_attr "length" "4,8")]) | |
3620 | ||
3621 | (define_split | |
3622 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3623 | (compare:CC (zero_extend:SI | |
3624 | (subreg:HI | |
3625 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3626 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3627 | (const_int 0))) | |
3628 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3629 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3630 | "reload_completed" | |
3631 | [(set (match_dup 0) | |
3632 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3633 | (set (match_dup 3) | |
3634 | (compare:CC (match_dup 0) | |
3635 | (const_int 0)))] | |
3636 | "") | |
1fd4e8c1 RK |
3637 | |
3638 | ;; Note that we use "sle." instead of "sl." so that we can set | |
3639 | ;; SHIFT_COUNT_TRUNCATED. | |
3640 | ||
ca7f5001 RK |
3641 | (define_expand "ashlsi3" |
3642 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3643 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3644 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3645 | "" | |
3646 | " | |
3647 | { | |
3648 | if (TARGET_POWER) | |
3649 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
3650 | else | |
25c341fa | 3651 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3652 | DONE; |
3653 | }") | |
3654 | ||
3655 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
3656 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3657 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3658 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3659 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3660 | "TARGET_POWER" |
1fd4e8c1 RK |
3661 | "@ |
3662 | sle %0,%1,%2 | |
9ebbca7d | 3663 | {sli|slwi} %0,%1,%h2") |
ca7f5001 | 3664 | |
25c341fa | 3665 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
3666 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3667 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3668 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 3669 | "! TARGET_POWER" |
9ebbca7d | 3670 | "{sl|slw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
3671 | |
3672 | (define_insn "" | |
9ebbca7d GK |
3673 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3674 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3675 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3676 | (const_int 0))) |
9ebbca7d GK |
3677 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
3678 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 3679 | "TARGET_POWER" |
1fd4e8c1 RK |
3680 | "@ |
3681 | sle. %3,%1,%2 | |
9ebbca7d GK |
3682 | {sli.|slwi.} %3,%1,%h2 |
3683 | # | |
3684 | #" | |
3685 | [(set_attr "type" "delayed_compare") | |
3686 | (set_attr "length" "4,4,8,8")]) | |
3687 | ||
3688 | (define_split | |
3689 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3690 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3691 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3692 | (const_int 0))) | |
3693 | (clobber (match_scratch:SI 3 "")) | |
3694 | (clobber (match_scratch:SI 4 ""))] | |
3695 | "TARGET_POWER && reload_completed" | |
3696 | [(parallel [(set (match_dup 3) | |
3697 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3698 | (clobber (match_dup 4))]) | |
3699 | (set (match_dup 0) | |
3700 | (compare:CC (match_dup 3) | |
3701 | (const_int 0)))] | |
3702 | "") | |
25c341fa | 3703 | |
ca7f5001 | 3704 | (define_insn "" |
9ebbca7d GK |
3705 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3706 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3707 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3708 | (const_int 0))) |
9ebbca7d | 3709 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 3710 | "! TARGET_POWER && TARGET_32BIT" |
9ebbca7d GK |
3711 | "@ |
3712 | {sl|slw}%I2. %3,%1,%h2 | |
3713 | #" | |
3714 | [(set_attr "type" "delayed_compare") | |
3715 | (set_attr "length" "4,8")]) | |
3716 | ||
3717 | (define_split | |
3718 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3719 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3720 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3721 | (const_int 0))) | |
3722 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 3723 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3724 | [(set (match_dup 3) |
3725 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3726 | (set (match_dup 0) | |
3727 | (compare:CC (match_dup 3) | |
3728 | (const_int 0)))] | |
3729 | "") | |
1fd4e8c1 RK |
3730 | |
3731 | (define_insn "" | |
9ebbca7d GK |
3732 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3733 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3734 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3735 | (const_int 0))) |
9ebbca7d | 3736 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 3737 | (ashift:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3738 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 3739 | "TARGET_POWER" |
1fd4e8c1 RK |
3740 | "@ |
3741 | sle. %0,%1,%2 | |
9ebbca7d GK |
3742 | {sli.|slwi.} %0,%1,%h2 |
3743 | # | |
3744 | #" | |
3745 | [(set_attr "type" "delayed_compare") | |
3746 | (set_attr "length" "4,4,8,8")]) | |
3747 | ||
3748 | (define_split | |
3749 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3750 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3751 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3752 | (const_int 0))) | |
3753 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3754 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3755 | (clobber (match_scratch:SI 4 ""))] | |
3756 | "TARGET_POWER && reload_completed" | |
3757 | [(parallel [(set (match_dup 0) | |
3758 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3759 | (clobber (match_dup 4))]) | |
3760 | (set (match_dup 3) | |
3761 | (compare:CC (match_dup 0) | |
3762 | (const_int 0)))] | |
3763 | "") | |
25c341fa | 3764 | |
ca7f5001 | 3765 | (define_insn "" |
9ebbca7d GK |
3766 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3767 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3768 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3769 | (const_int 0))) |
9ebbca7d | 3770 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 3771 | (ashift:SI (match_dup 1) (match_dup 2)))] |
4b8a63d6 | 3772 | "! TARGET_POWER && TARGET_32BIT" |
9ebbca7d GK |
3773 | "@ |
3774 | {sl|slw}%I2. %0,%1,%h2 | |
3775 | #" | |
3776 | [(set_attr "type" "delayed_compare") | |
3777 | (set_attr "length" "4,8")]) | |
3778 | ||
3779 | (define_split | |
3780 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3781 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3782 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3783 | (const_int 0))) | |
3784 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3785 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 3786 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3787 | [(set (match_dup 0) |
3788 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3789 | (set (match_dup 3) | |
3790 | (compare:CC (match_dup 0) | |
3791 | (const_int 0)))] | |
3792 | "") | |
1fd4e8c1 RK |
3793 | |
3794 | (define_insn "" | |
cd2b37d9 RK |
3795 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3796 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3797 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 3798 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3799 | "includes_lshift_p (operands[2], operands[3])" |
d56d506a | 3800 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
3801 | |
3802 | (define_insn "" | |
9ebbca7d | 3803 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3804 | (compare:CC |
9ebbca7d GK |
3805 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3806 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3807 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3808 | (const_int 0))) |
9ebbca7d | 3809 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3810 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3811 | "@ |
3812 | {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 | |
3813 | #" | |
3814 | [(set_attr "type" "delayed_compare") | |
3815 | (set_attr "length" "4,8")]) | |
3816 | ||
3817 | (define_split | |
3818 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3819 | (compare:CC | |
3820 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3821 | (match_operand:SI 2 "const_int_operand" "")) | |
3822 | (match_operand:SI 3 "mask_operand" "")) | |
3823 | (const_int 0))) | |
3824 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3825 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3826 | [(set (match_dup 4) |
3827 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) | |
3828 | (match_dup 3))) | |
3829 | (set (match_dup 0) | |
3830 | (compare:CC (match_dup 4) | |
3831 | (const_int 0)))] | |
3832 | "") | |
1fd4e8c1 RK |
3833 | |
3834 | (define_insn "" | |
9ebbca7d | 3835 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3836 | (compare:CC |
9ebbca7d GK |
3837 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3838 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3839 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3840 | (const_int 0))) |
9ebbca7d | 3841 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3842 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3843 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3844 | "@ |
3845 | {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 | |
3846 | #" | |
3847 | [(set_attr "type" "delayed_compare") | |
3848 | (set_attr "length" "4,8")]) | |
3849 | ||
3850 | (define_split | |
3851 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3852 | (compare:CC | |
3853 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3854 | (match_operand:SI 2 "const_int_operand" "")) | |
3855 | (match_operand:SI 3 "mask_operand" "")) | |
3856 | (const_int 0))) | |
3857 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3858 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 3859 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3860 | [(set (match_dup 0) |
3861 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3862 | (set (match_dup 4) | |
3863 | (compare:CC (match_dup 0) | |
3864 | (const_int 0)))] | |
3865 | "") | |
1fd4e8c1 | 3866 | |
ca7f5001 | 3867 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 3868 | ;; "sli x,x,0". |
ca7f5001 RK |
3869 | (define_expand "lshrsi3" |
3870 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3871 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3872 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3873 | "" | |
3874 | " | |
3875 | { | |
3876 | if (TARGET_POWER) | |
3877 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
3878 | else | |
25c341fa | 3879 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3880 | DONE; |
3881 | }") | |
3882 | ||
3883 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
3884 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
3885 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
3886 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
3887 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 3888 | "TARGET_POWER" |
1fd4e8c1 RK |
3889 | "@ |
3890 | sre %0,%1,%2 | |
bdf423cb | 3891 | mr %0,%1 |
ca7f5001 RK |
3892 | {s%A2i|s%A2wi} %0,%1,%h2") |
3893 | ||
25c341fa | 3894 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
3895 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3896 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3897 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 3898 | "! TARGET_POWER" |
bdf423cb MM |
3899 | "@ |
3900 | mr %0,%1 | |
3901 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
3902 | |
3903 | (define_insn "" | |
9ebbca7d GK |
3904 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") |
3905 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
3906 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 3907 | (const_int 0))) |
9ebbca7d GK |
3908 | (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) |
3909 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] | |
ca7f5001 | 3910 | "TARGET_POWER" |
1fd4e8c1 | 3911 | "@ |
29ae5b89 JL |
3912 | sre. %3,%1,%2 |
3913 | mr. %1,%1 | |
9ebbca7d GK |
3914 | {s%A2i.|s%A2wi.} %3,%1,%h2 |
3915 | # | |
3916 | # | |
3917 | #" | |
3918 | [(set_attr "type" "delayed_compare") | |
3919 | (set_attr "length" "4,4,4,8,8,8")]) | |
3920 | ||
3921 | (define_split | |
3922 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3923 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3924 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3925 | (const_int 0))) | |
3926 | (clobber (match_scratch:SI 3 "")) | |
3927 | (clobber (match_scratch:SI 4 ""))] | |
3928 | "TARGET_POWER && reload_completed" | |
3929 | [(parallel [(set (match_dup 3) | |
3930 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3931 | (clobber (match_dup 4))]) | |
3932 | (set (match_dup 0) | |
3933 | (compare:CC (match_dup 3) | |
3934 | (const_int 0)))] | |
3935 | "") | |
ca7f5001 RK |
3936 | |
3937 | (define_insn "" | |
9ebbca7d GK |
3938 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3939 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3940 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
ca7f5001 | 3941 | (const_int 0))) |
9ebbca7d | 3942 | (clobber (match_scratch:SI 3 "=X,r,X,r"))] |
4b8a63d6 | 3943 | "! TARGET_POWER && TARGET_32BIT" |
bdf423cb MM |
3944 | "@ |
3945 | mr. %1,%1 | |
9ebbca7d GK |
3946 | {sr|srw}%I2. %3,%1,%h2 |
3947 | # | |
3948 | #" | |
3949 | [(set_attr "type" "delayed_compare") | |
3950 | (set_attr "length" "4,4,8,8")]) | |
1fd4e8c1 | 3951 | |
9ebbca7d GK |
3952 | (define_split |
3953 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3954 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3955 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3956 | (const_int 0))) | |
3957 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 3958 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3959 | [(set (match_dup 3) |
3960 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3961 | (set (match_dup 0) | |
3962 | (compare:CC (match_dup 3) | |
3963 | (const_int 0)))] | |
3964 | "") | |
3965 | ||
3966 | (define_insn "" | |
3967 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") | |
3968 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
3969 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 3970 | (const_int 0))) |
9ebbca7d | 3971 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
1fd4e8c1 | 3972 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3973 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] |
ca7f5001 | 3974 | "TARGET_POWER" |
1fd4e8c1 | 3975 | "@ |
29ae5b89 JL |
3976 | sre. %0,%1,%2 |
3977 | mr. %0,%1 | |
9ebbca7d GK |
3978 | {s%A2i.|s%A2wi.} %0,%1,%h2 |
3979 | # | |
3980 | # | |
3981 | #" | |
3982 | [(set_attr "type" "delayed_compare") | |
3983 | (set_attr "length" "4,4,4,8,8,8")]) | |
3984 | ||
3985 | (define_split | |
3986 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3987 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3988 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3989 | (const_int 0))) | |
3990 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3991 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3992 | (clobber (match_scratch:SI 4 ""))] | |
3993 | "TARGET_POWER && reload_completed" | |
3994 | [(parallel [(set (match_dup 0) | |
3995 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3996 | (clobber (match_dup 4))]) | |
3997 | (set (match_dup 3) | |
3998 | (compare:CC (match_dup 0) | |
3999 | (const_int 0)))] | |
4000 | "") | |
ca7f5001 RK |
4001 | |
4002 | (define_insn "" | |
9ebbca7d GK |
4003 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4004 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4005 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
815cdc52 | 4006 | (const_int 0))) |
9ebbca7d | 4007 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
29ae5b89 | 4008 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] |
4b8a63d6 | 4009 | "! TARGET_POWER && TARGET_32BIT" |
29ae5b89 JL |
4010 | "@ |
4011 | mr. %0,%1 | |
9ebbca7d GK |
4012 | {sr|srw}%I2. %0,%1,%h2 |
4013 | # | |
4014 | #" | |
4015 | [(set_attr "type" "delayed_compare") | |
4016 | (set_attr "length" "4,4,8,8")]) | |
4017 | ||
4018 | (define_split | |
4019 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4020 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4021 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4022 | (const_int 0))) | |
4023 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4024 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 4025 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
4026 | [(set (match_dup 0) |
4027 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4028 | (set (match_dup 3) | |
4029 | (compare:CC (match_dup 0) | |
4030 | (const_int 0)))] | |
4031 | "") | |
1fd4e8c1 RK |
4032 | |
4033 | (define_insn "" | |
cd2b37d9 RK |
4034 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4035 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4036 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 4037 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 4038 | "includes_rshift_p (operands[2], operands[3])" |
ca7f5001 | 4039 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
4040 | |
4041 | (define_insn "" | |
9ebbca7d | 4042 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4043 | (compare:CC |
9ebbca7d GK |
4044 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4045 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 4046 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 4047 | (const_int 0))) |
9ebbca7d | 4048 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 4049 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4050 | "@ |
4051 | {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 | |
4052 | #" | |
4053 | [(set_attr "type" "delayed_compare") | |
4054 | (set_attr "length" "4,8")]) | |
4055 | ||
4056 | (define_split | |
4057 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4058 | (compare:CC | |
4059 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4060 | (match_operand:SI 2 "const_int_operand" "")) | |
4061 | (match_operand:SI 3 "mask_operand" "")) | |
4062 | (const_int 0))) | |
4063 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 4064 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
4065 | [(set (match_dup 4) |
4066 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) | |
4067 | (match_dup 3))) | |
4068 | (set (match_dup 0) | |
4069 | (compare:CC (match_dup 4) | |
4070 | (const_int 0)))] | |
4071 | "") | |
1fd4e8c1 RK |
4072 | |
4073 | (define_insn "" | |
9ebbca7d | 4074 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4075 | (compare:CC |
9ebbca7d GK |
4076 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4077 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 4078 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 4079 | (const_int 0))) |
9ebbca7d | 4080 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4081 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 4082 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4083 | "@ |
4084 | {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 | |
4085 | #" | |
4086 | [(set_attr "type" "delayed_compare") | |
4087 | (set_attr "length" "4,8")]) | |
4088 | ||
4089 | (define_split | |
4090 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4091 | (compare:CC | |
4092 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4093 | (match_operand:SI 2 "const_int_operand" "")) | |
4094 | (match_operand:SI 3 "mask_operand" "")) | |
4095 | (const_int 0))) | |
4096 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4097 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 4098 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
4099 | [(set (match_dup 0) |
4100 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4101 | (set (match_dup 4) | |
4102 | (compare:CC (match_dup 0) | |
4103 | (const_int 0)))] | |
4104 | "") | |
1fd4e8c1 RK |
4105 | |
4106 | (define_insn "" | |
cd2b37d9 | 4107 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4108 | (zero_extend:SI |
4109 | (subreg:QI | |
cd2b37d9 | 4110 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4111 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4112 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 4113 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
4114 | |
4115 | (define_insn "" | |
9ebbca7d | 4116 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4117 | (compare:CC |
4118 | (zero_extend:SI | |
4119 | (subreg:QI | |
9ebbca7d GK |
4120 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4121 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4122 | (const_int 0))) |
9ebbca7d | 4123 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4124 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4125 | "@ |
4126 | {rlinm.|rlwinm.} %3,%1,%s2,0xff | |
4127 | #" | |
4128 | [(set_attr "type" "delayed_compare") | |
4129 | (set_attr "length" "4,8")]) | |
4130 | ||
4131 | (define_split | |
4132 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4133 | (compare:CC | |
4134 | (zero_extend:SI | |
4135 | (subreg:QI | |
4136 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4137 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4138 | (const_int 0))) | |
4139 | (clobber (match_scratch:SI 3 ""))] | |
4140 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4141 | [(set (match_dup 3) | |
4142 | (zero_extend:SI (subreg:QI | |
4143 | (lshiftrt:SI (match_dup 1) | |
4144 | (match_dup 2)) 0))) | |
4145 | (set (match_dup 0) | |
4146 | (compare:CC (match_dup 3) | |
4147 | (const_int 0)))] | |
4148 | "") | |
1fd4e8c1 RK |
4149 | |
4150 | (define_insn "" | |
9ebbca7d | 4151 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4152 | (compare:CC |
4153 | (zero_extend:SI | |
4154 | (subreg:QI | |
9ebbca7d GK |
4155 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4156 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4157 | (const_int 0))) |
9ebbca7d | 4158 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4159 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4160 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4161 | "@ |
4162 | {rlinm.|rlwinm.} %0,%1,%s2,0xff | |
4163 | #" | |
4164 | [(set_attr "type" "delayed_compare") | |
4165 | (set_attr "length" "4,8")]) | |
4166 | ||
4167 | (define_split | |
4168 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4169 | (compare:CC | |
4170 | (zero_extend:SI | |
4171 | (subreg:QI | |
4172 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4173 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4174 | (const_int 0))) | |
4175 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4176 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4177 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4178 | [(set (match_dup 0) | |
4179 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4180 | (set (match_dup 3) | |
4181 | (compare:CC (match_dup 0) | |
4182 | (const_int 0)))] | |
4183 | "") | |
1fd4e8c1 RK |
4184 | |
4185 | (define_insn "" | |
cd2b37d9 | 4186 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4187 | (zero_extend:SI |
4188 | (subreg:HI | |
cd2b37d9 | 4189 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4190 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4191 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 4192 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
4193 | |
4194 | (define_insn "" | |
9ebbca7d | 4195 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4196 | (compare:CC |
4197 | (zero_extend:SI | |
4198 | (subreg:HI | |
9ebbca7d GK |
4199 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4200 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4201 | (const_int 0))) |
9ebbca7d | 4202 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4203 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4204 | "@ |
4205 | {rlinm.|rlwinm.} %3,%1,%s2,0xffff | |
4206 | #" | |
4207 | [(set_attr "type" "delayed_compare") | |
4208 | (set_attr "length" "4,8")]) | |
4209 | ||
4210 | (define_split | |
4211 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4212 | (compare:CC | |
4213 | (zero_extend:SI | |
4214 | (subreg:HI | |
4215 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4216 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4217 | (const_int 0))) | |
4218 | (clobber (match_scratch:SI 3 ""))] | |
4219 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4220 | [(set (match_dup 3) | |
4221 | (zero_extend:SI (subreg:HI | |
4222 | (lshiftrt:SI (match_dup 1) | |
4223 | (match_dup 2)) 0))) | |
4224 | (set (match_dup 0) | |
4225 | (compare:CC (match_dup 3) | |
4226 | (const_int 0)))] | |
4227 | "") | |
1fd4e8c1 RK |
4228 | |
4229 | (define_insn "" | |
9ebbca7d | 4230 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4231 | (compare:CC |
4232 | (zero_extend:SI | |
4233 | (subreg:HI | |
9ebbca7d GK |
4234 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4235 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4236 | (const_int 0))) |
9ebbca7d | 4237 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4238 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4239 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4240 | "@ |
4241 | {rlinm.|rlwinm.} %0,%1,%s2,0xffff | |
4242 | #" | |
4243 | [(set_attr "type" "delayed_compare") | |
4244 | (set_attr "length" "4,8")]) | |
4245 | ||
4246 | (define_split | |
4247 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4248 | (compare:CC | |
4249 | (zero_extend:SI | |
4250 | (subreg:HI | |
4251 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4252 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4253 | (const_int 0))) | |
4254 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4255 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4256 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4257 | [(set (match_dup 0) | |
4258 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4259 | (set (match_dup 3) | |
4260 | (compare:CC (match_dup 0) | |
4261 | (const_int 0)))] | |
4262 | "") | |
1fd4e8c1 RK |
4263 | |
4264 | (define_insn "" | |
cd2b37d9 | 4265 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4266 | (const_int 1) |
cd2b37d9 RK |
4267 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4268 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4269 | (const_int 31)))] |
ca7f5001 | 4270 | "TARGET_POWER" |
1fd4e8c1 RK |
4271 | "rrib %0,%1,%2") |
4272 | ||
4273 | (define_insn "" | |
cd2b37d9 | 4274 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4275 | (const_int 1) |
cd2b37d9 RK |
4276 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4277 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4278 | (const_int 31)))] |
ca7f5001 | 4279 | "TARGET_POWER" |
1fd4e8c1 RK |
4280 | "rrib %0,%1,%2") |
4281 | ||
4282 | (define_insn "" | |
cd2b37d9 | 4283 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4284 | (const_int 1) |
cd2b37d9 RK |
4285 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4286 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4287 | (const_int 1) |
4288 | (const_int 0)))] | |
ca7f5001 | 4289 | "TARGET_POWER" |
1fd4e8c1 RK |
4290 | "rrib %0,%1,%2") |
4291 | ||
ca7f5001 RK |
4292 | (define_expand "ashrsi3" |
4293 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4294 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4295 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4296 | "" | |
4297 | " | |
4298 | { | |
4299 | if (TARGET_POWER) | |
4300 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
4301 | else | |
25c341fa | 4302 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4303 | DONE; |
4304 | }") | |
4305 | ||
4306 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
4307 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4308 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4309 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
4310 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 4311 | "TARGET_POWER" |
1fd4e8c1 RK |
4312 | "@ |
4313 | srea %0,%1,%2 | |
ca7f5001 RK |
4314 | {srai|srawi} %0,%1,%h2") |
4315 | ||
25c341fa | 4316 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
4317 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4318 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4319 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4320 | "! TARGET_POWER" |
d904e9ed | 4321 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4322 | |
4323 | (define_insn "" | |
9ebbca7d GK |
4324 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4325 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4326 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4327 | (const_int 0))) |
9ebbca7d GK |
4328 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4329 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4330 | "TARGET_POWER" |
1fd4e8c1 RK |
4331 | "@ |
4332 | srea. %3,%1,%2 | |
9ebbca7d GK |
4333 | {srai.|srawi.} %3,%1,%h2 |
4334 | # | |
4335 | #" | |
4336 | [(set_attr "type" "delayed_compare") | |
4337 | (set_attr "length" "4,4,8,8")]) | |
4338 | ||
4339 | (define_split | |
4340 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4341 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4342 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4343 | (const_int 0))) | |
4344 | (clobber (match_scratch:SI 3 "")) | |
4345 | (clobber (match_scratch:SI 4 ""))] | |
4346 | "TARGET_POWER && reload_completed" | |
4347 | [(parallel [(set (match_dup 3) | |
4348 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4349 | (clobber (match_dup 4))]) | |
4350 | (set (match_dup 0) | |
4351 | (compare:CC (match_dup 3) | |
4352 | (const_int 0)))] | |
4353 | "") | |
ca7f5001 RK |
4354 | |
4355 | (define_insn "" | |
9ebbca7d GK |
4356 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4357 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4358 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4359 | (const_int 0))) |
9ebbca7d | 4360 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 4361 | "! TARGET_POWER" |
9ebbca7d GK |
4362 | "@ |
4363 | {sra|sraw}%I2. %3,%1,%h2 | |
4364 | #" | |
4365 | [(set_attr "type" "delayed_compare") | |
4366 | (set_attr "length" "4,8")]) | |
4367 | ||
4368 | (define_split | |
4369 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4370 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4371 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4372 | (const_int 0))) | |
4373 | (clobber (match_scratch:SI 3 ""))] | |
4374 | "! TARGET_POWER && reload_completed" | |
4375 | [(set (match_dup 3) | |
4376 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4377 | (set (match_dup 0) | |
4378 | (compare:CC (match_dup 3) | |
4379 | (const_int 0)))] | |
4380 | "") | |
1fd4e8c1 RK |
4381 | |
4382 | (define_insn "" | |
9ebbca7d GK |
4383 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4384 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4385 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4386 | (const_int 0))) |
9ebbca7d | 4387 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 4388 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4389 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 4390 | "TARGET_POWER" |
1fd4e8c1 RK |
4391 | "@ |
4392 | srea. %0,%1,%2 | |
9ebbca7d GK |
4393 | {srai.|srawi.} %0,%1,%h2 |
4394 | # | |
4395 | #" | |
4396 | [(set_attr "type" "delayed_compare") | |
4397 | (set_attr "length" "4,4,8,8")]) | |
4398 | ||
4399 | (define_split | |
4400 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4401 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4402 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4403 | (const_int 0))) | |
4404 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4405 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4406 | (clobber (match_scratch:SI 4 ""))] | |
4407 | "TARGET_POWER && reload_completed" | |
4408 | [(parallel [(set (match_dup 0) | |
4409 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4410 | (clobber (match_dup 4))]) | |
4411 | (set (match_dup 3) | |
4412 | (compare:CC (match_dup 0) | |
4413 | (const_int 0)))] | |
4414 | "") | |
1fd4e8c1 | 4415 | |
ca7f5001 | 4416 | (define_insn "" |
9ebbca7d GK |
4417 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4418 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4419 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4420 | (const_int 0))) |
9ebbca7d | 4421 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 4422 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 4423 | "! TARGET_POWER" |
9ebbca7d GK |
4424 | "@ |
4425 | {sra|sraw}%I2. %0,%1,%h2 | |
4426 | #" | |
4427 | [(set_attr "type" "delayed_compare") | |
4428 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 4429 | \f |
9ebbca7d GK |
4430 | (define_split |
4431 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4432 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4433 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4434 | (const_int 0))) | |
4435 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4436 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
4437 | "! TARGET_POWER && reload_completed" | |
4438 | [(set (match_dup 0) | |
4439 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4440 | (set (match_dup 3) | |
4441 | (compare:CC (match_dup 0) | |
4442 | (const_int 0)))] | |
4443 | "") | |
4444 | ||
1fd4e8c1 RK |
4445 | ;; Floating-point insns, excluding normal data motion. |
4446 | ;; | |
ca7f5001 RK |
4447 | ;; PowerPC has a full set of single-precision floating point instructions. |
4448 | ;; | |
4449 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
4450 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
4451 | ;; The only conversions we will do will be when storing to memory. In that | |
4452 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
4453 | ;; |
4454 | ;; Note that when we store into a single-precision memory location, we need to | |
4455 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
4456 | ;; need a scratch register for the frsp. But this is difficult when the store | |
4457 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
4458 | ;; this case, we just lose precision that we would have otherwise gotten but | |
4459 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
4460 | ||
11ac38b2 DE |
4461 | (define_insn_and_split "extendsfdf2" |
4462 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f") | |
4463 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "0,f")))] | |
a3170dc6 | 4464 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
11ac38b2 DE |
4465 | "@ |
4466 | # | |
4467 | fmr %0,%1" | |
4468 | "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])" | |
4469 | [(const_int 0)] | |
5c30aff8 | 4470 | { |
11ac38b2 DE |
4471 | emit_note (NOTE_INSN_DELETED); |
4472 | DONE; | |
4473 | } | |
e8112008 | 4474 | [(set_attr "type" "fp")]) |
1fd4e8c1 | 4475 | |
7a2f7870 AH |
4476 | (define_expand "truncdfsf2" |
4477 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4478 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))] | |
4479 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4480 | "") | |
4481 | ||
4482 | (define_insn "fpr_truncdfsf2" | |
cd2b37d9 RK |
4483 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4484 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4485 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
dcac138d | 4486 | "frsp %0,%1" |
1fd4e8c1 RK |
4487 | [(set_attr "type" "fp")]) |
4488 | ||
455350f4 RK |
4489 | (define_insn "aux_truncdfsf2" |
4490 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
615158e2 | 4491 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))] |
a3170dc6 | 4492 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
455350f4 RK |
4493 | "frsp %0,%1" |
4494 | [(set_attr "type" "fp")]) | |
4495 | ||
a3170dc6 AH |
4496 | (define_expand "negsf2" |
4497 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4498 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4499 | "TARGET_HARD_FLOAT" | |
4500 | "") | |
4501 | ||
4502 | (define_insn "*negsf2" | |
cd2b37d9 RK |
4503 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4504 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4505 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4506 | "fneg %0,%1" |
4507 | [(set_attr "type" "fp")]) | |
4508 | ||
a3170dc6 AH |
4509 | (define_expand "abssf2" |
4510 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4511 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4512 | "TARGET_HARD_FLOAT" | |
4513 | "") | |
4514 | ||
4515 | (define_insn "*abssf2" | |
cd2b37d9 RK |
4516 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4517 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4518 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4519 | "fabs %0,%1" |
4520 | [(set_attr "type" "fp")]) | |
4521 | ||
4522 | (define_insn "" | |
cd2b37d9 RK |
4523 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4524 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4525 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4526 | "fnabs %0,%1" |
4527 | [(set_attr "type" "fp")]) | |
4528 | ||
ca7f5001 RK |
4529 | (define_expand "addsf3" |
4530 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4531 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4532 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4533 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4534 | "") |
4535 | ||
4536 | (define_insn "" | |
cd2b37d9 RK |
4537 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4538 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4539 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4540 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4541 | "fadds %0,%1,%2" |
ca7f5001 RK |
4542 | [(set_attr "type" "fp")]) |
4543 | ||
4544 | (define_insn "" | |
4545 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4546 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4547 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4548 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4549 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
4550 | [(set_attr "type" "fp")]) |
4551 | ||
4552 | (define_expand "subsf3" | |
4553 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4554 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4555 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4556 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4557 | "") |
4558 | ||
4559 | (define_insn "" | |
4560 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4561 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4562 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4563 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4564 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
4565 | [(set_attr "type" "fp")]) |
4566 | ||
ca7f5001 | 4567 | (define_insn "" |
cd2b37d9 RK |
4568 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4569 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4570 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4571 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4572 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
4573 | [(set_attr "type" "fp")]) |
4574 | ||
4575 | (define_expand "mulsf3" | |
4576 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4577 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4578 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4579 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4580 | "") |
4581 | ||
4582 | (define_insn "" | |
4583 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4584 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4585 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4586 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4587 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
4588 | [(set_attr "type" "fp")]) |
4589 | ||
ca7f5001 | 4590 | (define_insn "" |
cd2b37d9 RK |
4591 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4592 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4593 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4594 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4595 | "{fm|fmul} %0,%1,%2" |
0780f386 | 4596 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4597 | |
ca7f5001 RK |
4598 | (define_expand "divsf3" |
4599 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4600 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4601 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4602 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4603 | "") |
4604 | ||
4605 | (define_insn "" | |
cd2b37d9 RK |
4606 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4607 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4608 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4609 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4610 | "fdivs %0,%1,%2" |
ca7f5001 RK |
4611 | [(set_attr "type" "sdiv")]) |
4612 | ||
4613 | (define_insn "" | |
4614 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4615 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4616 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4617 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4618 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 4619 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4620 | |
4621 | (define_insn "" | |
cd2b37d9 RK |
4622 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4623 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4624 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4625 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4626 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4627 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
4628 | [(set_attr "type" "fp")]) |
4629 | ||
4630 | (define_insn "" | |
4631 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4632 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4633 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4634 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4635 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4636 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 4637 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4638 | |
4639 | (define_insn "" | |
cd2b37d9 RK |
4640 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4641 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4642 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4643 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4644 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4645 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4646 | [(set_attr "type" "fp")]) |
4647 | ||
4648 | (define_insn "" | |
4649 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4650 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4651 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4652 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4653 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4654 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 4655 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4656 | |
4657 | (define_insn "" | |
cd2b37d9 RK |
4658 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4659 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4660 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4661 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4662 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4663 | && HONOR_SIGNED_ZEROS (SFmode)" | |
4664 | "fnmadds %0,%1,%2,%3" | |
4665 | [(set_attr "type" "fp")]) | |
4666 | ||
4667 | (define_insn "" | |
4668 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4669 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
4670 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4671 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
4672 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4673 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 4674 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
4675 | [(set_attr "type" "fp")]) |
4676 | ||
4677 | (define_insn "" | |
4678 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4679 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4680 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4681 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4682 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4683 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 4684 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4685 | |
16823694 GK |
4686 | (define_insn "" |
4687 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4688 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
4689 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4690 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
4691 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4692 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
4693 | "{fnma|fnmadd} %0,%1,%2,%3" | |
4694 | [(set_attr "type" "dmul")]) | |
4695 | ||
1fd4e8c1 | 4696 | (define_insn "" |
cd2b37d9 RK |
4697 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4698 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4699 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4700 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4701 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4702 | && HONOR_SIGNED_ZEROS (SFmode)" | |
4703 | "fnmsubs %0,%1,%2,%3" | |
4704 | [(set_attr "type" "fp")]) | |
4705 | ||
4706 | (define_insn "" | |
4707 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4708 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
4709 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4710 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
4711 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4712 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 4713 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4714 | [(set_attr "type" "fp")]) |
4715 | ||
4716 | (define_insn "" | |
4717 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4718 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4719 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4720 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4721 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4722 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 4723 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4724 | |
16823694 GK |
4725 | (define_insn "" |
4726 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4727 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
4728 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4729 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
4730 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4731 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
4732 | "{fnms|fnmsub} %0,%1,%2,%3" | |
4733 | [(set_attr "type" "fp")]) | |
4734 | ||
ca7f5001 RK |
4735 | (define_expand "sqrtsf2" |
4736 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4737 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
a3170dc6 | 4738 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4739 | "") |
4740 | ||
4741 | (define_insn "" | |
4742 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4743 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4744 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4745 | "fsqrts %0,%1" |
4746 | [(set_attr "type" "ssqrt")]) | |
4747 | ||
4748 | (define_insn "" | |
4749 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4750 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4751 | "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4752 | "fsqrt %0,%1" |
4753 | [(set_attr "type" "dsqrt")]) | |
4754 | ||
94d7001a RK |
4755 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
4756 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
4757 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 RK |
4758 | ;; combine. |
4759 | (define_expand "maxsf3" | |
8e871c05 | 4760 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
50a0b056 GK |
4761 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") |
4762 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
4763 | (match_dup 1) |
4764 | (match_dup 2)))] | |
89e73849 | 4765 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 4766 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
2f607b94 | 4767 | |
8e871c05 | 4768 | (define_expand "minsf3" |
50a0b056 GK |
4769 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
4770 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") | |
4771 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
4772 | (match_dup 2) | |
4773 | (match_dup 1)))] | |
89e73849 | 4774 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 4775 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
2f607b94 | 4776 | |
8e871c05 RK |
4777 | (define_split |
4778 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
4779 | (match_operator:SF 3 "min_max_operator" |
4780 | [(match_operand:SF 1 "gpc_reg_operand" "") | |
4781 | (match_operand:SF 2 "gpc_reg_operand" "")]))] | |
89e73849 | 4782 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 GK |
4783 | [(const_int 0)] |
4784 | " | |
6ae08853 | 4785 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), |
50a0b056 GK |
4786 | operands[1], operands[2]); |
4787 | DONE; | |
4788 | }") | |
2f607b94 | 4789 | |
a3170dc6 AH |
4790 | (define_expand "movsicc" |
4791 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4792 | (if_then_else:SI (match_operand 1 "comparison_operator" "") | |
4793 | (match_operand:SI 2 "gpc_reg_operand" "") | |
4794 | (match_operand:SI 3 "gpc_reg_operand" "")))] | |
4795 | "TARGET_ISEL" | |
4796 | " | |
4797 | { | |
4798 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) | |
4799 | DONE; | |
4800 | else | |
4801 | FAIL; | |
4802 | }") | |
4803 | ||
4804 | ;; We use the BASE_REGS for the isel input operands because, if rA is | |
4805 | ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB | |
4806 | ;; because we may switch the operands and rB may end up being rA. | |
4807 | ;; | |
4808 | ;; We need 2 patterns: an unsigned and a signed pattern. We could | |
4809 | ;; leave out the mode in operand 4 and use one pattern, but reload can | |
4810 | ;; change the mode underneath our feet and then gets confused trying | |
4811 | ;; to reload the value. | |
4812 | (define_insn "isel_signed" | |
4813 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4814 | (if_then_else:SI | |
4815 | (match_operator 1 "comparison_operator" | |
4816 | [(match_operand:CC 4 "cc_reg_operand" "y") | |
4817 | (const_int 0)]) | |
4818 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
4819 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
4820 | "TARGET_ISEL" | |
4821 | "* | |
4822 | { return output_isel (operands); }" | |
4823 | [(set_attr "length" "4")]) | |
4824 | ||
4825 | (define_insn "isel_unsigned" | |
4826 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4827 | (if_then_else:SI | |
4828 | (match_operator 1 "comparison_operator" | |
4829 | [(match_operand:CCUNS 4 "cc_reg_operand" "y") | |
4830 | (const_int 0)]) | |
4831 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
4832 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
4833 | "TARGET_ISEL" | |
4834 | "* | |
4835 | { return output_isel (operands); }" | |
4836 | [(set_attr "length" "4")]) | |
4837 | ||
94d7001a | 4838 | (define_expand "movsfcc" |
0ad91047 | 4839 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
94d7001a | 4840 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
4841 | (match_operand:SF 2 "gpc_reg_operand" "") |
4842 | (match_operand:SF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 4843 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4844 | " |
4845 | { | |
50a0b056 GK |
4846 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
4847 | DONE; | |
94d7001a | 4848 | else |
50a0b056 | 4849 | FAIL; |
94d7001a | 4850 | }") |
d56d506a | 4851 | |
50a0b056 | 4852 | (define_insn "*fselsfsf4" |
8e871c05 RK |
4853 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4854 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 4855 | (match_operand:SF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
4856 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4857 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4858 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
4859 | "fsel %0,%1,%2,%3" |
4860 | [(set_attr "type" "fp")]) | |
2f607b94 | 4861 | |
50a0b056 | 4862 | (define_insn "*fseldfsf4" |
94d7001a RK |
4863 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4864 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
d365ba42 | 4865 | (match_operand:DF 4 "zero_fp_constant" "F")) |
94d7001a RK |
4866 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4867 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4868 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4869 | "fsel %0,%1,%2,%3" |
4870 | [(set_attr "type" "fp")]) | |
d56d506a | 4871 | |
7a2f7870 AH |
4872 | (define_expand "negdf2" |
4873 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4874 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))] | |
4875 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4876 | "") | |
4877 | ||
4878 | (define_insn "fpr_negdf2" | |
cd2b37d9 RK |
4879 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4880 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4881 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4882 | "fneg %0,%1" |
4883 | [(set_attr "type" "fp")]) | |
4884 | ||
7a2f7870 AH |
4885 | (define_expand "absdf2" |
4886 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4887 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))] | |
4888 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4889 | "") | |
4890 | ||
4891 | (define_insn "fpr_absdf2" | |
cd2b37d9 RK |
4892 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4893 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4894 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4895 | "fabs %0,%1" |
4896 | [(set_attr "type" "fp")]) | |
4897 | ||
7a2f7870 | 4898 | (define_insn "fpr_nabsdf2" |
cd2b37d9 RK |
4899 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4900 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4901 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4902 | "fnabs %0,%1" |
4903 | [(set_attr "type" "fp")]) | |
4904 | ||
7a2f7870 AH |
4905 | (define_expand "adddf3" |
4906 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4907 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
4908 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
4909 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4910 | "") | |
4911 | ||
4912 | (define_insn "fpr_adddf3" | |
cd2b37d9 RK |
4913 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4914 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4915 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4916 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4917 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
4918 | [(set_attr "type" "fp")]) |
4919 | ||
7a2f7870 AH |
4920 | (define_expand "subdf3" |
4921 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4922 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
4923 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
4924 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4925 | "") | |
4926 | ||
4927 | (define_insn "fpr_subdf3" | |
cd2b37d9 RK |
4928 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4929 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4930 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4931 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4932 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
4933 | [(set_attr "type" "fp")]) |
4934 | ||
7a2f7870 AH |
4935 | (define_expand "muldf3" |
4936 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4937 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
4938 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
4939 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4940 | "") | |
4941 | ||
4942 | (define_insn "fpr_muldf3" | |
cd2b37d9 RK |
4943 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4944 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4945 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4946 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4947 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 4948 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4949 | |
7a2f7870 AH |
4950 | (define_expand "divdf3" |
4951 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4952 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
4953 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
4954 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4955 | "") | |
4956 | ||
4957 | (define_insn "fpr_divdf3" | |
cd2b37d9 RK |
4958 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4959 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
4960 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4961 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 4962 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 4963 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4964 | |
4965 | (define_insn "" | |
cd2b37d9 RK |
4966 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4967 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4968 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4969 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4970 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 4971 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 4972 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4973 | |
4974 | (define_insn "" | |
cd2b37d9 RK |
4975 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4976 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4977 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4978 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4979 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 4980 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 4981 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4982 | |
4983 | (define_insn "" | |
cd2b37d9 RK |
4984 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4985 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
4986 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4987 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4988 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4989 | && HONOR_SIGNED_ZEROS (DFmode)" | |
4990 | "{fnma|fnmadd} %0,%1,%2,%3" | |
4991 | [(set_attr "type" "dmul")]) | |
4992 | ||
4993 | (define_insn "" | |
4994 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
4995 | (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")) | |
4996 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
4997 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
4998 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4999 | && ! HONOR_SIGNED_ZEROS (DFmode)" | |
ca7f5001 | 5000 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 5001 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5002 | |
5003 | (define_insn "" | |
cd2b37d9 RK |
5004 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5005 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5006 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5007 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
5008 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
5009 | && HONOR_SIGNED_ZEROS (DFmode)" | |
5010 | "{fnms|fnmsub} %0,%1,%2,%3" | |
5011 | [(set_attr "type" "dmul")]) | |
5012 | ||
5013 | (define_insn "" | |
5014 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5015 | (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f") | |
5016 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5017 | (match_operand:DF 2 "gpc_reg_operand" "f"))))] | |
6ae08853 | 5018 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
16823694 | 5019 | && ! HONOR_SIGNED_ZEROS (DFmode)" |
ca7f5001 | 5020 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 5021 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
5022 | |
5023 | (define_insn "sqrtdf2" | |
5024 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5025 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5026 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
5027 | "fsqrt %0,%1" |
5028 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 5029 | |
50a0b056 | 5030 | ;; The conditional move instructions allow us to perform max and min |
6ae08853 | 5031 | ;; operations even when |
b77dfefc | 5032 | |
8e871c05 | 5033 | (define_expand "maxdf3" |
8e871c05 | 5034 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
50a0b056 GK |
5035 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") |
5036 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
5037 | (match_dup 1) |
5038 | (match_dup 2)))] | |
89e73849 | 5039 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 5040 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
b77dfefc | 5041 | |
8e871c05 | 5042 | (define_expand "mindf3" |
50a0b056 GK |
5043 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5044 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") | |
5045 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
5046 | (match_dup 2) | |
5047 | (match_dup 1)))] | |
89e73849 | 5048 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 5049 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
b77dfefc | 5050 | |
8e871c05 RK |
5051 | (define_split |
5052 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
5053 | (match_operator:DF 3 "min_max_operator" |
5054 | [(match_operand:DF 1 "gpc_reg_operand" "") | |
5055 | (match_operand:DF 2 "gpc_reg_operand" "")]))] | |
89e73849 | 5056 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 GK |
5057 | [(const_int 0)] |
5058 | " | |
6ae08853 | 5059 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), |
50a0b056 GK |
5060 | operands[1], operands[2]); |
5061 | DONE; | |
5062 | }") | |
b77dfefc | 5063 | |
94d7001a | 5064 | (define_expand "movdfcc" |
0ad91047 | 5065 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
94d7001a | 5066 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
5067 | (match_operand:DF 2 "gpc_reg_operand" "") |
5068 | (match_operand:DF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 5069 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
5070 | " |
5071 | { | |
50a0b056 GK |
5072 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
5073 | DONE; | |
94d7001a | 5074 | else |
50a0b056 | 5075 | FAIL; |
94d7001a | 5076 | }") |
d56d506a | 5077 | |
50a0b056 | 5078 | (define_insn "*fseldfdf4" |
8e871c05 RK |
5079 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5080 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5081 | (match_operand:DF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
5082 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5083 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5084 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
5085 | "fsel %0,%1,%2,%3" |
5086 | [(set_attr "type" "fp")]) | |
d56d506a | 5087 | |
50a0b056 | 5088 | (define_insn "*fselsfdf4" |
94d7001a RK |
5089 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5090 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5091 | (match_operand:SF 4 "zero_fp_constant" "F")) |
94d7001a RK |
5092 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5093 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
5094 | "TARGET_PPC_GFXOPT" | |
5095 | "fsel %0,%1,%2,%3" | |
5096 | [(set_attr "type" "fp")]) | |
1fd4e8c1 | 5097 | \f |
d095928f AH |
5098 | ;; Conversions to and from floating-point. |
5099 | ||
5100 | (define_expand "fixuns_truncsfsi2" | |
5101 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5102 | (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] | |
5103 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5104 | "") | |
5105 | ||
5106 | (define_expand "fix_truncsfsi2" | |
5107 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5108 | (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] | |
5109 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5110 | "") | |
5111 | ||
9ebbca7d GK |
5112 | ; For each of these conversions, there is a define_expand, a define_insn |
5113 | ; with a '#' template, and a define_split (with C code). The idea is | |
5114 | ; to allow constant folding with the template of the define_insn, | |
5115 | ; then to have the insns split later (between sched1 and final). | |
5116 | ||
1fd4e8c1 | 5117 | (define_expand "floatsidf2" |
802a0058 MM |
5118 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5119 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5120 | (use (match_dup 2)) | |
5121 | (use (match_dup 3)) | |
208c89ce | 5122 | (clobber (match_dup 4)) |
a7df97e6 | 5123 | (clobber (match_dup 5)) |
9ebbca7d | 5124 | (clobber (match_dup 6))])] |
a3170dc6 | 5125 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5126 | " |
5127 | { | |
05d49501 AM |
5128 | if (TARGET_POWERPC64) |
5129 | { | |
5130 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5131 | rtx t1 = gen_reg_rtx (DImode); | |
5132 | rtx t2 = gen_reg_rtx (DImode); | |
5133 | emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2)); | |
5134 | DONE; | |
5135 | } | |
5136 | ||
802a0058 | 5137 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5138 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode)); |
9ebbca7d GK |
5139 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5140 | operands[5] = gen_reg_rtx (DFmode); | |
5141 | operands[6] = gen_reg_rtx (SImode); | |
1fd4e8c1 RK |
5142 | }") |
5143 | ||
802a0058 MM |
5144 | (define_insn "*floatsidf2_internal" |
5145 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5146 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5147 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5148 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5149 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 DJ |
5150 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f")) |
5151 | (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))] | |
a3170dc6 | 5152 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5153 | "#" |
a7df97e6 | 5154 | [(set_attr "length" "24")]) |
802a0058 MM |
5155 | |
5156 | (define_split | |
dbe3df29 | 5157 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
802a0058 MM |
5158 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) |
5159 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5160 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5161 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5162 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5163 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
a3170dc6 | 5164 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d GK |
5165 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5166 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5167 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5168 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5169 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5170 | (clobber (match_operand:DF 5 "gpc_reg_operand" "")) | |
5171 | (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] | |
208c89ce MM |
5172 | " |
5173 | { | |
9ebbca7d GK |
5174 | rtx lowword, highword; |
5175 | if (GET_CODE (operands[4]) != MEM) | |
5176 | abort(); | |
5177 | highword = XEXP (operands[4], 0); | |
5178 | lowword = plus_constant (highword, 4); | |
5179 | if (! WORDS_BIG_ENDIAN) | |
5180 | { | |
5181 | rtx tmp; | |
5182 | tmp = highword; highword = lowword; lowword = tmp; | |
5183 | } | |
5184 | ||
6ae08853 | 5185 | emit_insn (gen_xorsi3 (operands[6], operands[1], |
9ebbca7d GK |
5186 | GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); |
5187 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]); | |
5188 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5189 | emit_move_insn (operands[5], operands[4]); | |
5190 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5191 | DONE; | |
208c89ce | 5192 | }") |
802a0058 | 5193 | |
a3170dc6 AH |
5194 | (define_expand "floatunssisf2" |
5195 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5196 | (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5197 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5198 | "") | |
5199 | ||
802a0058 MM |
5200 | (define_expand "floatunssidf2" |
5201 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5202 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5203 | (use (match_dup 2)) | |
5204 | (use (match_dup 3)) | |
a7df97e6 | 5205 | (clobber (match_dup 4)) |
9ebbca7d | 5206 | (clobber (match_dup 5))])] |
a3170dc6 | 5207 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5208 | " |
5209 | { | |
05d49501 AM |
5210 | if (TARGET_POWERPC64) |
5211 | { | |
5212 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5213 | rtx t1 = gen_reg_rtx (DImode); | |
5214 | rtx t2 = gen_reg_rtx (DImode); | |
5215 | emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem, | |
5216 | t1, t2)); | |
5217 | DONE; | |
5218 | } | |
5219 | ||
802a0058 | 5220 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5221 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode)); |
9ebbca7d GK |
5222 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5223 | operands[5] = gen_reg_rtx (DFmode); | |
1fd4e8c1 RK |
5224 | }") |
5225 | ||
802a0058 MM |
5226 | (define_insn "*floatunssidf2_internal" |
5227 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") | |
5228 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5229 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5230 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5231 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 | 5232 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))] |
a3170dc6 | 5233 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5234 | "#" |
a7df97e6 | 5235 | [(set_attr "length" "20")]) |
802a0058 MM |
5236 | |
5237 | (define_split | |
5238 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5239 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5240 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5241 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
9ebbca7d GK |
5242 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) |
5243 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
a3170dc6 | 5244 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d GK |
5245 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5246 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5247 | (use (match_operand:SI 2 "gpc_reg_operand" "")) | |
5248 | (use (match_operand:DF 3 "gpc_reg_operand" "")) | |
5249 | (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) | |
5250 | (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] | |
5251 | " | |
802a0058 | 5252 | { |
9ebbca7d GK |
5253 | rtx lowword, highword; |
5254 | if (GET_CODE (operands[4]) != MEM) | |
5255 | abort(); | |
5256 | highword = XEXP (operands[4], 0); | |
5257 | lowword = plus_constant (highword, 4); | |
5258 | if (! WORDS_BIG_ENDIAN) | |
f6968f59 | 5259 | { |
9ebbca7d GK |
5260 | rtx tmp; |
5261 | tmp = highword; highword = lowword; lowword = tmp; | |
f6968f59 | 5262 | } |
802a0058 | 5263 | |
9ebbca7d GK |
5264 | emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]); |
5265 | emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]); | |
5266 | emit_move_insn (operands[5], operands[4]); | |
5267 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5268 | DONE; | |
5269 | }") | |
1fd4e8c1 | 5270 | |
1fd4e8c1 | 5271 | (define_expand "fix_truncdfsi2" |
802a0058 MM |
5272 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
5273 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) | |
5274 | (clobber (match_dup 2)) | |
9ebbca7d | 5275 | (clobber (match_dup 3))])] |
a3170dc6 | 5276 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5277 | " |
5278 | { | |
802a0058 | 5279 | operands[2] = gen_reg_rtx (DImode); |
9ebbca7d | 5280 | operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); |
1fd4e8c1 RK |
5281 | }") |
5282 | ||
802a0058 MM |
5283 | (define_insn "*fix_truncdfsi2_internal" |
5284 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5285 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
e3485bbc | 5286 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) |
9ebbca7d | 5287 | (clobber (match_operand:DI 3 "memory_operand" "=o"))] |
a3170dc6 | 5288 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5289 | "#" |
9ebbca7d | 5290 | [(set_attr "length" "16")]) |
802a0058 MM |
5291 | |
5292 | (define_split | |
5293 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
75540af0 | 5294 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
802a0058 | 5295 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
9ebbca7d | 5296 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] |
a3170dc6 | 5297 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
9ebbca7d | 5298 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
75540af0 | 5299 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
9ebbca7d GK |
5300 | (clobber (match_operand:DI 2 "gpc_reg_operand" "")) |
5301 | (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] | |
5302 | " | |
802a0058 | 5303 | { |
9ebbca7d GK |
5304 | rtx lowword; |
5305 | if (GET_CODE (operands[3]) != MEM) | |
5306 | abort(); | |
5307 | lowword = XEXP (operands[3], 0); | |
5308 | if (WORDS_BIG_ENDIAN) | |
5309 | lowword = plus_constant (lowword, 4); | |
802a0058 | 5310 | |
9ebbca7d GK |
5311 | emit_insn (gen_fctiwz (operands[2], operands[1])); |
5312 | emit_move_insn (operands[3], operands[2]); | |
5313 | emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); | |
5314 | DONE; | |
5315 | }") | |
802a0058 | 5316 | |
615158e2 | 5317 | ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ)) |
9ebbca7d GK |
5318 | ; rather than (set (subreg:SI (reg)) (fix:SI ...)) |
5319 | ; because the first makes it clear that operand 0 is not live | |
5320 | ; before the instruction. | |
5321 | (define_insn "fctiwz" | |
61c07d3c | 5322 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
615158e2 JJ |
5323 | (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] |
5324 | UNSPEC_FCTIWZ))] | |
a3170dc6 | 5325 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
a260abc9 DE |
5326 | "{fcirz|fctiwz} %0,%1" |
5327 | [(set_attr "type" "fp")]) | |
5328 | ||
a3170dc6 AH |
5329 | (define_expand "floatsisf2" |
5330 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5331 | (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5332 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5333 | "") | |
5334 | ||
a473029f RK |
5335 | (define_insn "floatdidf2" |
5336 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 5337 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))] |
a3170dc6 | 5338 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5339 | "fcfid %0,%1" |
5340 | [(set_attr "type" "fp")]) | |
5341 | ||
05d49501 AM |
5342 | (define_insn_and_split "floatsidf_ppc64" |
5343 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5344 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5345 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5346 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5347 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5348 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 | 5349 | "#" |
ecb62ae7 | 5350 | "&& 1" |
05d49501 AM |
5351 | [(set (match_dup 3) (sign_extend:DI (match_dup 1))) |
5352 | (set (match_dup 2) (match_dup 3)) | |
5353 | (set (match_dup 4) (match_dup 2)) | |
5354 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5355 | "") | |
5356 | ||
5357 | (define_insn_and_split "floatunssidf_ppc64" | |
5358 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5359 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5360 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5361 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5362 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5363 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 | 5364 | "#" |
ecb62ae7 | 5365 | "&& 1" |
05d49501 AM |
5366 | [(set (match_dup 3) (zero_extend:DI (match_dup 1))) |
5367 | (set (match_dup 2) (match_dup 3)) | |
5368 | (set (match_dup 4) (match_dup 2)) | |
5369 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5370 | "") | |
5371 | ||
a473029f | 5372 | (define_insn "fix_truncdfdi2" |
61c07d3c | 5373 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
a473029f | 5374 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] |
a3170dc6 | 5375 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5376 | "fctidz %0,%1" |
5377 | [(set_attr "type" "fp")]) | |
ea112fc4 | 5378 | |
678b7733 AM |
5379 | (define_expand "floatdisf2" |
5380 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5381 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] | |
683bdff7 | 5382 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS" |
678b7733 AM |
5383 | " |
5384 | { | |
5385 | if (!flag_unsafe_math_optimizations) | |
5386 | { | |
5387 | rtx label = gen_label_rtx (); | |
5388 | emit_insn (gen_floatdisf2_internal2 (operands[1], label)); | |
5389 | emit_label (label); | |
5390 | } | |
5391 | emit_insn (gen_floatdisf2_internal1 (operands[0], operands[1])); | |
5392 | DONE; | |
5393 | }") | |
5394 | ||
5395 | ;; This is not IEEE compliant if rounding mode is "round to nearest". | |
5396 | ;; If the DI->DF conversion is inexact, then it's possible to suffer | |
5397 | ;; from double rounding. | |
5398 | (define_insn_and_split "floatdisf2_internal1" | |
ea112fc4 | 5399 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
61c07d3c | 5400 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f"))) |
ea112fc4 | 5401 | (clobber (match_scratch:DF 2 "=f"))] |
678b7733 | 5402 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ea112fc4 DE |
5403 | "#" |
5404 | "&& reload_completed" | |
5405 | [(set (match_dup 2) | |
5406 | (float:DF (match_dup 1))) | |
5407 | (set (match_dup 0) | |
5408 | (float_truncate:SF (match_dup 2)))] | |
5409 | "") | |
678b7733 AM |
5410 | |
5411 | ;; Twiddles bits to avoid double rounding. | |
b6d08ca1 | 5412 | ;; Bits that might be truncated when converting to DFmode are replaced |
678b7733 AM |
5413 | ;; by a bit that won't be lost at that stage, but is below the SFmode |
5414 | ;; rounding position. | |
5415 | (define_expand "floatdisf2_internal2" | |
42a6388c AM |
5416 | [(parallel [(set (match_dup 4) |
5417 | (compare:CC (and:DI (match_operand:DI 0 "" "") | |
5418 | (const_int 2047)) | |
5419 | (const_int 0))) | |
5420 | (set (match_dup 2) (and:DI (match_dup 0) (const_int 2047))) | |
5421 | (clobber (match_scratch:CC 7 ""))]) | |
678b7733 AM |
5422 | (set (match_dup 3) (ashiftrt:DI (match_dup 0) (const_int 53))) |
5423 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1))) | |
5424 | (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) | |
5425 | (label_ref (match_operand:DI 1 "" "")) | |
5426 | (pc))) | |
5427 | (set (match_dup 5) (compare:CCUNS (match_dup 3) (const_int 2))) | |
5428 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
5429 | (label_ref (match_dup 1)) | |
5430 | (pc))) | |
5431 | (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 2))) | |
5432 | (set (match_dup 0) (ior:DI (match_dup 0) (const_int 2048)))] | |
683bdff7 | 5433 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_FPRS" |
678b7733 AM |
5434 | " |
5435 | { | |
5436 | operands[2] = gen_reg_rtx (DImode); | |
5437 | operands[3] = gen_reg_rtx (DImode); | |
5438 | operands[4] = gen_reg_rtx (CCmode); | |
5439 | operands[5] = gen_reg_rtx (CCUNSmode); | |
5440 | }") | |
1fd4e8c1 RK |
5441 | \f |
5442 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
5443 | ;; of instructions. The & constraints are to prevent the register |
5444 | ;; allocator from allocating registers that overlap with the inputs | |
5445 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 5446 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 5447 | |
266eb58a | 5448 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
5449 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
5450 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
5451 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 5452 | "! TARGET_POWERPC64" |
0f645302 MM |
5453 | "* |
5454 | { | |
5455 | if (WORDS_BIG_ENDIAN) | |
5456 | return (GET_CODE (operands[2])) != CONST_INT | |
5457 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
5458 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
5459 | else | |
5460 | return (GET_CODE (operands[2])) != CONST_INT | |
5461 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
5462 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
5463 | }" | |
b19003d8 | 5464 | [(set_attr "length" "8")]) |
1fd4e8c1 | 5465 | |
266eb58a | 5466 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
5467 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
5468 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
5469 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 5470 | "! TARGET_POWERPC64" |
5502823b RK |
5471 | "* |
5472 | { | |
0f645302 MM |
5473 | if (WORDS_BIG_ENDIAN) |
5474 | return (GET_CODE (operands[1]) != CONST_INT) | |
5475 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
5476 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
5477 | else | |
5478 | return (GET_CODE (operands[1]) != CONST_INT) | |
5479 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
5480 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 5481 | }" |
ca7f5001 RK |
5482 | [(set_attr "length" "8")]) |
5483 | ||
266eb58a | 5484 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
5485 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5486 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 5487 | "! TARGET_POWERPC64" |
5502823b RK |
5488 | "* |
5489 | { | |
5490 | return (WORDS_BIG_ENDIAN) | |
5491 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
5492 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
5493 | }" | |
ca7f5001 RK |
5494 | [(set_attr "length" "8")]) |
5495 | ||
8ffd9c51 RK |
5496 | (define_expand "mulsidi3" |
5497 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5498 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5499 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 5500 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
5501 | " |
5502 | { | |
5503 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5504 | { | |
39403d82 DE |
5505 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5506 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5507 | emit_insn (gen_mull_call ()); |
cf27b467 | 5508 | if (WORDS_BIG_ENDIAN) |
39403d82 | 5509 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
5510 | else |
5511 | { | |
5512 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 5513 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 5514 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 5515 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 5516 | } |
8ffd9c51 RK |
5517 | DONE; |
5518 | } | |
5519 | else if (TARGET_POWER) | |
5520 | { | |
5521 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
5522 | DONE; | |
5523 | } | |
5524 | }") | |
deb9225a | 5525 | |
8ffd9c51 | 5526 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 5527 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 5528 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 5529 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 5530 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 5531 | "TARGET_POWER" |
b19003d8 | 5532 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
5533 | [(set_attr "type" "imul") |
5534 | (set_attr "length" "8")]) | |
deb9225a | 5535 | |
f192bf8b | 5536 | (define_insn "*mulsidi3_no_mq" |
425c176f | 5537 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
5538 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
5539 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5540 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
5541 | "* |
5542 | { | |
5543 | return (WORDS_BIG_ENDIAN) | |
5544 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
5545 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
5546 | }" | |
8ffd9c51 RK |
5547 | [(set_attr "type" "imul") |
5548 | (set_attr "length" "8")]) | |
deb9225a | 5549 | |
ebedb4dd MM |
5550 | (define_split |
5551 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5552 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5553 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5554 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5555 | [(set (match_dup 3) |
5556 | (truncate:SI | |
5557 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
5558 | (sign_extend:DI (match_dup 2))) | |
5559 | (const_int 32)))) | |
5560 | (set (match_dup 4) | |
5561 | (mult:SI (match_dup 1) | |
5562 | (match_dup 2)))] | |
5563 | " | |
5564 | { | |
5565 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5566 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5567 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5568 | }") | |
5569 | ||
f192bf8b DE |
5570 | (define_expand "umulsidi3" |
5571 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5572 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5573 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
5574 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
5575 | " | |
5576 | { | |
5577 | if (TARGET_POWER) | |
5578 | { | |
5579 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
5580 | DONE; | |
5581 | } | |
5582 | }") | |
5583 | ||
5584 | (define_insn "umulsidi3_mq" | |
5585 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5586 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5587 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
5588 | (clobber (match_scratch:SI 3 "=q"))] | |
5589 | "TARGET_POWERPC && TARGET_POWER" | |
5590 | "* | |
5591 | { | |
5592 | return (WORDS_BIG_ENDIAN) | |
5593 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5594 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5595 | }" | |
5596 | [(set_attr "type" "imul") | |
5597 | (set_attr "length" "8")]) | |
5598 | ||
5599 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
5600 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
5601 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5602 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5603 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
5604 | "* |
5605 | { | |
5606 | return (WORDS_BIG_ENDIAN) | |
5607 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5608 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5609 | }" | |
5610 | [(set_attr "type" "imul") | |
5611 | (set_attr "length" "8")]) | |
5612 | ||
ebedb4dd MM |
5613 | (define_split |
5614 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5615 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5616 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5617 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5618 | [(set (match_dup 3) |
5619 | (truncate:SI | |
5620 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
5621 | (zero_extend:DI (match_dup 2))) | |
5622 | (const_int 32)))) | |
5623 | (set (match_dup 4) | |
5624 | (mult:SI (match_dup 1) | |
5625 | (match_dup 2)))] | |
5626 | " | |
5627 | { | |
5628 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5629 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5630 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5631 | }") | |
5632 | ||
8ffd9c51 RK |
5633 | (define_expand "smulsi3_highpart" |
5634 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5635 | (truncate:SI | |
5636 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
5637 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5638 | (sign_extend:DI | |
5639 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5640 | (const_int 32))))] | |
5641 | "" | |
5642 | " | |
5643 | { | |
5644 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5645 | { | |
39403d82 DE |
5646 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5647 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5648 | emit_insn (gen_mulh_call ()); |
39403d82 | 5649 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
5650 | DONE; |
5651 | } | |
5652 | else if (TARGET_POWER) | |
5653 | { | |
5654 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5655 | DONE; | |
5656 | } | |
5657 | }") | |
deb9225a | 5658 | |
8ffd9c51 RK |
5659 | (define_insn "smulsi3_highpart_mq" |
5660 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5661 | (truncate:SI | |
fada905b MM |
5662 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5663 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5664 | (sign_extend:DI | |
5665 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
5666 | (const_int 32)))) |
5667 | (clobber (match_scratch:SI 3 "=q"))] | |
5668 | "TARGET_POWER" | |
5669 | "mul %0,%1,%2" | |
5670 | [(set_attr "type" "imul")]) | |
deb9225a | 5671 | |
f192bf8b | 5672 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
5673 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5674 | (truncate:SI | |
fada905b MM |
5675 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5676 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5677 | (sign_extend:DI | |
5678 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 5679 | (const_int 32))))] |
f192bf8b | 5680 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
5681 | "mulhw %0,%1,%2" |
5682 | [(set_attr "type" "imul")]) | |
deb9225a | 5683 | |
f192bf8b DE |
5684 | (define_expand "umulsi3_highpart" |
5685 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5686 | (truncate:SI | |
5687 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5688 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
5689 | (zero_extend:DI | |
5690 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
5691 | (const_int 32))))] | |
5692 | "TARGET_POWERPC" | |
5693 | " | |
5694 | { | |
5695 | if (TARGET_POWER) | |
5696 | { | |
5697 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5698 | DONE; | |
5699 | } | |
5700 | }") | |
5701 | ||
5702 | (define_insn "umulsi3_highpart_mq" | |
5703 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5704 | (truncate:SI | |
5705 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5706 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5707 | (zero_extend:DI | |
5708 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5709 | (const_int 32)))) | |
5710 | (clobber (match_scratch:SI 3 "=q"))] | |
5711 | "TARGET_POWERPC && TARGET_POWER" | |
5712 | "mulhwu %0,%1,%2" | |
5713 | [(set_attr "type" "imul")]) | |
5714 | ||
5715 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
5716 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5717 | (truncate:SI | |
5718 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5719 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5720 | (zero_extend:DI | |
5721 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5722 | (const_int 32))))] | |
f192bf8b | 5723 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
5724 | "mulhwu %0,%1,%2" |
5725 | [(set_attr "type" "imul")]) | |
5726 | ||
5727 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
5728 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
5729 | ;; why we have the strange constraints below. | |
5730 | (define_insn "ashldi3_power" | |
5731 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
5732 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
5733 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5734 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5735 | "TARGET_POWER" | |
5736 | "@ | |
5737 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
5738 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5739 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5740 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
5741 | [(set_attr "length" "8")]) | |
5742 | ||
5743 | (define_insn "lshrdi3_power" | |
47ad8c61 | 5744 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
5745 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
5746 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5747 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5748 | "TARGET_POWER" | |
5749 | "@ | |
47ad8c61 | 5750 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
5751 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
5752 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
5753 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
5754 | [(set_attr "length" "8")]) | |
5755 | ||
5756 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
5757 | ;; just handle shifts by constants. | |
5758 | (define_insn "ashrdi3_power" | |
7093ddee | 5759 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
5760 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
5761 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
5762 | (clobber (match_scratch:SI 3 "=X,q"))] | |
5763 | "TARGET_POWER" | |
5764 | "@ | |
5765 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5766 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
5767 | [(set_attr "length" "8")]) | |
4aa74a4f FS |
5768 | |
5769 | (define_insn "ashrdi3_no_power" | |
5770 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") | |
5771 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5772 | (match_operand:SI 2 "const_int_operand" "M,i")))] | |
97727e85 | 5773 | "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN" |
4aa74a4f FS |
5774 | "@ |
5775 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5776 | {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2" | |
5777 | [(set_attr "length" "8,12")]) | |
683bdff7 FJ |
5778 | |
5779 | (define_insn "*ashrdisi3_noppc64" | |
5780 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
6ae08853 | 5781 | (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
683bdff7 FJ |
5782 | (const_int 32)) 4))] |
5783 | "TARGET_32BIT && !TARGET_POWERPC64" | |
5784 | "* | |
5785 | { | |
5786 | if (REGNO (operands[0]) == REGNO (operands[1])) | |
5787 | return \"\"; | |
5788 | else | |
5789 | return \"mr %0,%1\"; | |
5790 | }" | |
6ae08853 | 5791 | [(set_attr "length" "4")]) |
683bdff7 | 5792 | |
266eb58a DE |
5793 | \f |
5794 | ;; PowerPC64 DImode operations. | |
5795 | ||
5796 | (define_expand "adddi3" | |
5797 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5798 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 5799 | (match_operand:DI 2 "reg_or_add_cint64_operand" "")))] |
266eb58a DE |
5800 | "" |
5801 | " | |
5802 | { | |
a260abc9 DE |
5803 | if (! TARGET_POWERPC64) |
5804 | { | |
5805 | if (non_short_cint_operand (operands[2], DImode)) | |
5806 | FAIL; | |
5807 | } | |
5808 | else | |
5809 | if (GET_CODE (operands[2]) == CONST_INT | |
677a9668 | 5810 | && ! add_operand (operands[2], DImode)) |
a260abc9 | 5811 | { |
677a9668 | 5812 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
5813 | ? operands[0] : gen_reg_rtx (DImode)); |
5814 | ||
2bfcf297 | 5815 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 5816 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 5817 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); |
a260abc9 | 5818 | |
2bfcf297 DB |
5819 | if (!CONST_OK_FOR_LETTER_P (rest, 'L')) |
5820 | FAIL; | |
a260abc9 | 5821 | |
2bfcf297 DB |
5822 | /* The ordering here is important for the prolog expander. |
5823 | When space is allocated from the stack, adding 'low' first may | |
5824 | produce a temporary deallocation (which would be bad). */ | |
5825 | emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest))); | |
a260abc9 DE |
5826 | emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low))); |
5827 | DONE; | |
5828 | } | |
266eb58a DE |
5829 | }") |
5830 | ||
5831 | ;; Discourage ai/addic because of carry but provide it in an alternative | |
5832 | ;; allowing register zero as source. | |
5833 | ||
a260abc9 | 5834 | (define_insn "*adddi3_internal1" |
266eb58a DE |
5835 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r") |
5836 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b") | |
9615f239 | 5837 | (match_operand:DI 2 "add_operand" "r,I,I,L")))] |
266eb58a DE |
5838 | "TARGET_POWERPC64" |
5839 | "@ | |
5840 | add %0,%1,%2 | |
5841 | addi %0,%1,%2 | |
5842 | addic %0,%1,%2 | |
802a0058 | 5843 | addis %0,%1,%v2") |
266eb58a | 5844 | |
a260abc9 | 5845 | (define_insn "*adddi3_internal2" |
9ebbca7d GK |
5846 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
5847 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5848 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5849 | (const_int 0))) |
9ebbca7d | 5850 | (clobber (match_scratch:DI 3 "=r,r,r,r"))] |
683bdff7 | 5851 | "TARGET_64BIT" |
266eb58a DE |
5852 | "@ |
5853 | add. %3,%1,%2 | |
9ebbca7d GK |
5854 | addic. %3,%1,%2 |
5855 | # | |
5856 | #" | |
a62bfff2 | 5857 | [(set_attr "type" "fast_compare,compare,compare,compare") |
9ebbca7d GK |
5858 | (set_attr "length" "4,4,8,8")]) |
5859 | ||
5860 | (define_split | |
5861 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5862 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5863 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5864 | (const_int 0))) | |
5865 | (clobber (match_scratch:DI 3 ""))] | |
5866 | "TARGET_POWERPC64 && reload_completed" | |
5867 | [(set (match_dup 3) | |
5868 | (plus:DI (match_dup 1) (match_dup 2))) | |
5869 | (set (match_dup 0) | |
5870 | (compare:CC (match_dup 3) | |
5871 | (const_int 0)))] | |
5872 | "") | |
266eb58a | 5873 | |
a260abc9 | 5874 | (define_insn "*adddi3_internal3" |
9ebbca7d GK |
5875 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
5876 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") | |
5877 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")) | |
266eb58a | 5878 | (const_int 0))) |
9ebbca7d | 5879 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
266eb58a | 5880 | (plus:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 5881 | "TARGET_64BIT" |
266eb58a DE |
5882 | "@ |
5883 | add. %0,%1,%2 | |
9ebbca7d GK |
5884 | addic. %0,%1,%2 |
5885 | # | |
5886 | #" | |
a62bfff2 | 5887 | [(set_attr "type" "fast_compare,compare,compare,compare") |
9ebbca7d GK |
5888 | (set_attr "length" "4,4,8,8")]) |
5889 | ||
5890 | (define_split | |
5891 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5892 | (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5893 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
5894 | (const_int 0))) | |
5895 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5896 | (plus:DI (match_dup 1) (match_dup 2)))] | |
5897 | "TARGET_POWERPC64 && reload_completed" | |
5898 | [(set (match_dup 0) | |
5899 | (plus:DI (match_dup 1) (match_dup 2))) | |
5900 | (set (match_dup 3) | |
5901 | (compare:CC (match_dup 0) | |
5902 | (const_int 0)))] | |
5903 | "") | |
266eb58a DE |
5904 | |
5905 | ;; Split an add that we can't do in one insn into two insns, each of which | |
5906 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
5907 | ;; add should be last in case the result gets used in an address. | |
5908 | ||
5909 | (define_split | |
5910 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5911 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5912 | (match_operand:DI 2 "non_add_cint_operand" "")))] | |
5913 | "TARGET_POWERPC64" | |
5914 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) | |
5915 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] | |
5916 | " | |
5917 | { | |
2bfcf297 | 5918 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 5919 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
2bfcf297 | 5920 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); |
266eb58a | 5921 | |
2bfcf297 DB |
5922 | operands[4] = GEN_INT (low); |
5923 | if (CONST_OK_FOR_LETTER_P (rest, 'L')) | |
5924 | operands[3] = GEN_INT (rest); | |
5925 | else if (! no_new_pseudos) | |
38886f37 | 5926 | { |
2bfcf297 DB |
5927 | operands[3] = gen_reg_rtx (DImode); |
5928 | emit_move_insn (operands[3], operands[2]); | |
5929 | emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); | |
5930 | DONE; | |
38886f37 | 5931 | } |
2bfcf297 DB |
5932 | else |
5933 | FAIL; | |
266eb58a DE |
5934 | }") |
5935 | ||
5936 | (define_insn "one_cmpldi2" | |
5937 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5938 | (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
5939 | "TARGET_POWERPC64" | |
5940 | "nor %0,%1,%1") | |
5941 | ||
5942 | (define_insn "" | |
9ebbca7d GK |
5943 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
5944 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5945 | (const_int 0))) |
9ebbca7d | 5946 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 5947 | "TARGET_64BIT" |
9ebbca7d GK |
5948 | "@ |
5949 | nor. %2,%1,%1 | |
5950 | #" | |
5951 | [(set_attr "type" "compare") | |
5952 | (set_attr "length" "4,8")]) | |
5953 | ||
5954 | (define_split | |
5955 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5956 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5957 | (const_int 0))) | |
5958 | (clobber (match_scratch:DI 2 ""))] | |
5959 | "TARGET_POWERPC64 && reload_completed" | |
5960 | [(set (match_dup 2) | |
5961 | (not:DI (match_dup 1))) | |
5962 | (set (match_dup 0) | |
5963 | (compare:CC (match_dup 2) | |
5964 | (const_int 0)))] | |
5965 | "") | |
266eb58a DE |
5966 | |
5967 | (define_insn "" | |
9ebbca7d GK |
5968 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
5969 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 5970 | (const_int 0))) |
9ebbca7d | 5971 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 5972 | (not:DI (match_dup 1)))] |
683bdff7 | 5973 | "TARGET_64BIT" |
9ebbca7d GK |
5974 | "@ |
5975 | nor. %0,%1,%1 | |
5976 | #" | |
5977 | [(set_attr "type" "compare") | |
5978 | (set_attr "length" "4,8")]) | |
5979 | ||
5980 | (define_split | |
5981 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
5982 | (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
5983 | (const_int 0))) | |
5984 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
5985 | (not:DI (match_dup 1)))] | |
5986 | "TARGET_POWERPC64 && reload_completed" | |
5987 | [(set (match_dup 0) | |
5988 | (not:DI (match_dup 1))) | |
5989 | (set (match_dup 2) | |
5990 | (compare:CC (match_dup 0) | |
5991 | (const_int 0)))] | |
5992 | "") | |
266eb58a DE |
5993 | |
5994 | (define_insn "" | |
5995 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
5996 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I") | |
5997 | (match_operand:DI 2 "gpc_reg_operand" "r,r")))] | |
5998 | "TARGET_POWERPC64" | |
5999 | "@ | |
6000 | subf %0,%2,%1 | |
6001 | subfic %0,%2,%1") | |
6002 | ||
6003 | (define_insn "" | |
9ebbca7d GK |
6004 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6005 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6006 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 6007 | (const_int 0))) |
9ebbca7d | 6008 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6009 | "TARGET_64BIT" |
9ebbca7d GK |
6010 | "@ |
6011 | subf. %3,%2,%1 | |
6012 | #" | |
a62bfff2 | 6013 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
6014 | (set_attr "length" "4,8")]) |
6015 | ||
6016 | (define_split | |
6017 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6018 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6019 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6020 | (const_int 0))) | |
6021 | (clobber (match_scratch:DI 3 ""))] | |
6022 | "TARGET_POWERPC64 && reload_completed" | |
6023 | [(set (match_dup 3) | |
6024 | (minus:DI (match_dup 1) (match_dup 2))) | |
6025 | (set (match_dup 0) | |
6026 | (compare:CC (match_dup 3) | |
6027 | (const_int 0)))] | |
6028 | "") | |
266eb58a DE |
6029 | |
6030 | (define_insn "" | |
9ebbca7d GK |
6031 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6032 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6033 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
266eb58a | 6034 | (const_int 0))) |
9ebbca7d | 6035 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6036 | (minus:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6037 | "TARGET_64BIT" |
9ebbca7d GK |
6038 | "@ |
6039 | subf. %0,%2,%1 | |
6040 | #" | |
a62bfff2 | 6041 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
6042 | (set_attr "length" "4,8")]) |
6043 | ||
6044 | (define_split | |
6045 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6046 | (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6047 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6048 | (const_int 0))) | |
6049 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6050 | (minus:DI (match_dup 1) (match_dup 2)))] | |
6051 | "TARGET_POWERPC64 && reload_completed" | |
6052 | [(set (match_dup 0) | |
6053 | (minus:DI (match_dup 1) (match_dup 2))) | |
6054 | (set (match_dup 3) | |
6055 | (compare:CC (match_dup 0) | |
6056 | (const_int 0)))] | |
6057 | "") | |
266eb58a DE |
6058 | |
6059 | (define_expand "subdi3" | |
6060 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6061 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "") | |
2bfcf297 | 6062 | (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))] |
266eb58a DE |
6063 | "" |
6064 | " | |
6065 | { | |
6066 | if (GET_CODE (operands[2]) == CONST_INT) | |
6067 | { | |
6068 | emit_insn (gen_adddi3 (operands[0], operands[1], | |
6069 | negate_rtx (DImode, operands[2]))); | |
6070 | DONE; | |
6071 | } | |
6072 | }") | |
6073 | ||
ea112fc4 | 6074 | (define_insn_and_split "absdi2" |
266eb58a | 6075 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 6076 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) |
266eb58a DE |
6077 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
6078 | "TARGET_POWERPC64" | |
ea112fc4 DE |
6079 | "#" |
6080 | "&& reload_completed" | |
a260abc9 | 6081 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 6082 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 6083 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
6084 | "") |
6085 | ||
ea112fc4 | 6086 | (define_insn_and_split "*nabsdi2" |
266eb58a | 6087 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 6088 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) |
266eb58a DE |
6089 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
6090 | "TARGET_POWERPC64" | |
ea112fc4 DE |
6091 | "#" |
6092 | "&& reload_completed" | |
a260abc9 | 6093 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 6094 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
19ba8161 | 6095 | (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] |
266eb58a DE |
6096 | "") |
6097 | ||
6098 | (define_expand "negdi2" | |
6099 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6100 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))] | |
6101 | "" | |
6102 | "") | |
6103 | ||
6104 | (define_insn "" | |
6105 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6106 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6107 | "TARGET_POWERPC64" | |
6108 | "neg %0,%1") | |
6109 | ||
6110 | (define_insn "" | |
9ebbca7d GK |
6111 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6112 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
266eb58a | 6113 | (const_int 0))) |
9ebbca7d | 6114 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 6115 | "TARGET_64BIT" |
9ebbca7d GK |
6116 | "@ |
6117 | neg. %2,%1 | |
6118 | #" | |
a62bfff2 | 6119 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
6120 | (set_attr "length" "4,8")]) |
6121 | ||
6122 | (define_split | |
6123 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6124 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6125 | (const_int 0))) | |
6126 | (clobber (match_scratch:DI 2 ""))] | |
6127 | "TARGET_POWERPC64 && reload_completed" | |
6128 | [(set (match_dup 2) | |
6129 | (neg:DI (match_dup 1))) | |
6130 | (set (match_dup 0) | |
6131 | (compare:CC (match_dup 2) | |
6132 | (const_int 0)))] | |
6133 | "") | |
815cdc52 | 6134 | |
29ae5b89 | 6135 | (define_insn "" |
9ebbca7d GK |
6136 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
6137 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 6138 | (const_int 0))) |
9ebbca7d | 6139 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
815cdc52 | 6140 | (neg:DI (match_dup 1)))] |
683bdff7 | 6141 | "TARGET_64BIT" |
9ebbca7d GK |
6142 | "@ |
6143 | neg. %0,%1 | |
6144 | #" | |
a62bfff2 | 6145 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
6146 | (set_attr "length" "4,8")]) |
6147 | ||
6148 | (define_split | |
6149 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
6150 | (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")) | |
6151 | (const_int 0))) | |
6152 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6153 | (neg:DI (match_dup 1)))] | |
6154 | "TARGET_POWERPC64 && reload_completed" | |
6155 | [(set (match_dup 0) | |
6156 | (neg:DI (match_dup 1))) | |
6157 | (set (match_dup 2) | |
6158 | (compare:CC (match_dup 0) | |
6159 | (const_int 0)))] | |
6160 | "") | |
266eb58a | 6161 | |
1b1edcfa DE |
6162 | (define_insn "clzdi2" |
6163 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6164 | (clz:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] | |
6165 | "TARGET_POWERPC64" | |
6166 | "cntlzd %0,%1") | |
6167 | ||
6168 | (define_expand "ctzdi2" | |
4977bab6 | 6169 | [(set (match_dup 2) |
1b1edcfa | 6170 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) |
6ae08853 AM |
6171 | (parallel [(set (match_dup 3) (and:DI (match_dup 1) |
6172 | (match_dup 2))) | |
1b1edcfa | 6173 | (clobber (scratch:CC))]) |
d865b122 | 6174 | (set (match_dup 4) (clz:DI (match_dup 3))) |
4977bab6 | 6175 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
1b1edcfa | 6176 | (minus:DI (const_int 63) (match_dup 4)))] |
266eb58a | 6177 | "TARGET_POWERPC64" |
4977bab6 | 6178 | { |
6ae08853 | 6179 | operands[2] = gen_reg_rtx (DImode); |
4977bab6 ZW |
6180 | operands[3] = gen_reg_rtx (DImode); |
6181 | operands[4] = gen_reg_rtx (DImode); | |
6182 | }) | |
6183 | ||
1b1edcfa DE |
6184 | (define_expand "ffsdi2" |
6185 | [(set (match_dup 2) | |
6186 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
6ae08853 AM |
6187 | (parallel [(set (match_dup 3) (and:DI (match_dup 1) |
6188 | (match_dup 2))) | |
1b1edcfa DE |
6189 | (clobber (scratch:CC))]) |
6190 | (set (match_dup 4) (clz:DI (match_dup 3))) | |
6191 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6192 | (minus:DI (const_int 64) (match_dup 4)))] | |
4977bab6 | 6193 | "TARGET_POWERPC64" |
1b1edcfa | 6194 | { |
6ae08853 | 6195 | operands[2] = gen_reg_rtx (DImode); |
1b1edcfa DE |
6196 | operands[3] = gen_reg_rtx (DImode); |
6197 | operands[4] = gen_reg_rtx (DImode); | |
6198 | }) | |
266eb58a DE |
6199 | |
6200 | (define_insn "muldi3" | |
6201 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6202 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
6203 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6204 | "TARGET_POWERPC64" | |
6205 | "mulld %0,%1,%2" | |
3cb999d8 | 6206 | [(set_attr "type" "lmul")]) |
266eb58a | 6207 | |
9259f3b0 DE |
6208 | (define_insn "*muldi3_internal1" |
6209 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
6210 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
6211 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
6212 | (const_int 0))) | |
6213 | (clobber (match_scratch:DI 3 "=r,r"))] | |
6214 | "TARGET_POWERPC64" | |
6215 | "@ | |
6216 | mulld. %3,%1,%2 | |
6217 | #" | |
6218 | [(set_attr "type" "lmul_compare") | |
6219 | (set_attr "length" "4,8")]) | |
6220 | ||
6221 | (define_split | |
6222 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6223 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6224 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6225 | (const_int 0))) | |
6226 | (clobber (match_scratch:DI 3 ""))] | |
6227 | "TARGET_POWERPC64 && reload_completed" | |
6228 | [(set (match_dup 3) | |
6229 | (mult:DI (match_dup 1) (match_dup 2))) | |
6230 | (set (match_dup 0) | |
6231 | (compare:CC (match_dup 3) | |
6232 | (const_int 0)))] | |
6233 | "") | |
6234 | ||
6235 | (define_insn "*muldi3_internal2" | |
6236 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") | |
6237 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
6238 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
6239 | (const_int 0))) | |
6240 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6241 | (mult:DI (match_dup 1) (match_dup 2)))] | |
6242 | "TARGET_POWERPC64" | |
6243 | "@ | |
6244 | mulld. %0,%1,%2 | |
6245 | #" | |
6246 | [(set_attr "type" "lmul_compare") | |
6247 | (set_attr "length" "4,8")]) | |
6248 | ||
6249 | (define_split | |
6250 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6251 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6252 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6253 | (const_int 0))) | |
6254 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6255 | (mult:DI (match_dup 1) (match_dup 2)))] | |
6256 | "TARGET_POWERPC64 && reload_completed" | |
6257 | [(set (match_dup 0) | |
6258 | (mult:DI (match_dup 1) (match_dup 2))) | |
6259 | (set (match_dup 3) | |
6260 | (compare:CC (match_dup 0) | |
6261 | (const_int 0)))] | |
6262 | "") | |
6263 | ||
266eb58a DE |
6264 | (define_insn "smuldi3_highpart" |
6265 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6266 | (truncate:DI | |
6267 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
6268 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6269 | (sign_extend:TI | |
6270 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6271 | (const_int 64))))] | |
6272 | "TARGET_POWERPC64" | |
6273 | "mulhd %0,%1,%2" | |
3cb999d8 | 6274 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6275 | |
6276 | (define_insn "umuldi3_highpart" | |
6277 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6278 | (truncate:DI | |
6279 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
6280 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6281 | (zero_extend:TI | |
6282 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6283 | (const_int 64))))] | |
6284 | "TARGET_POWERPC64" | |
6285 | "mulhdu %0,%1,%2" | |
3cb999d8 | 6286 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6287 | |
6288 | (define_expand "divdi3" | |
6289 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6290 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6291 | (match_operand:DI 2 "reg_or_cint_operand" "")))] | |
6292 | "TARGET_POWERPC64" | |
6293 | " | |
6294 | { | |
6295 | if (GET_CODE (operands[2]) == CONST_INT | |
2bfcf297 | 6296 | && INTVAL (operands[2]) > 0 |
266eb58a DE |
6297 | && exact_log2 (INTVAL (operands[2])) >= 0) |
6298 | ; | |
6299 | else | |
6300 | operands[2] = force_reg (DImode, operands[2]); | |
6301 | }") | |
6302 | ||
6303 | (define_expand "moddi3" | |
6304 | [(use (match_operand:DI 0 "gpc_reg_operand" "")) | |
6305 | (use (match_operand:DI 1 "gpc_reg_operand" "")) | |
6306 | (use (match_operand:DI 2 "reg_or_cint_operand" ""))] | |
6307 | "TARGET_POWERPC64" | |
6308 | " | |
6309 | { | |
2bfcf297 | 6310 | int i; |
266eb58a DE |
6311 | rtx temp1; |
6312 | rtx temp2; | |
6313 | ||
2bfcf297 DB |
6314 | if (GET_CODE (operands[2]) != CONST_INT |
6315 | || INTVAL (operands[2]) <= 0 | |
6316 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) | |
266eb58a DE |
6317 | FAIL; |
6318 | ||
6319 | temp1 = gen_reg_rtx (DImode); | |
6320 | temp2 = gen_reg_rtx (DImode); | |
6321 | ||
6322 | emit_insn (gen_divdi3 (temp1, operands[1], operands[2])); | |
6323 | emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i))); | |
6324 | emit_insn (gen_subdi3 (operands[0], operands[1], temp2)); | |
6325 | DONE; | |
6326 | }") | |
6327 | ||
6328 | (define_insn "" | |
6329 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6330 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
2bfcf297 DB |
6331 | (match_operand:DI 2 "exact_log2_cint_operand" "N")))] |
6332 | "TARGET_POWERPC64" | |
266eb58a DE |
6333 | "sradi %0,%1,%p2\;addze %0,%0" |
6334 | [(set_attr "length" "8")]) | |
6335 | ||
6336 | (define_insn "" | |
9ebbca7d GK |
6337 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6338 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6339 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6340 | (const_int 0))) |
9ebbca7d | 6341 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6342 | "TARGET_64BIT" |
9ebbca7d GK |
6343 | "@ |
6344 | sradi %3,%1,%p2\;addze. %3,%3 | |
6345 | #" | |
266eb58a | 6346 | [(set_attr "type" "compare") |
9ebbca7d GK |
6347 | (set_attr "length" "8,12")]) |
6348 | ||
6349 | (define_split | |
6350 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6351 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6352 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6353 | (const_int 0))) |
6354 | (clobber (match_scratch:DI 3 ""))] | |
2bfcf297 | 6355 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6356 | [(set (match_dup 3) |
6357 | (div:DI (match_dup 1) (match_dup 2))) | |
6358 | (set (match_dup 0) | |
6359 | (compare:CC (match_dup 3) | |
6360 | (const_int 0)))] | |
6361 | "") | |
266eb58a DE |
6362 | |
6363 | (define_insn "" | |
9ebbca7d GK |
6364 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6365 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
2bfcf297 | 6366 | (match_operand:DI 2 "exact_log2_cint_operand" "N,N")) |
266eb58a | 6367 | (const_int 0))) |
9ebbca7d | 6368 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6369 | (div:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6370 | "TARGET_64BIT" |
9ebbca7d GK |
6371 | "@ |
6372 | sradi %0,%1,%p2\;addze. %0,%0 | |
6373 | #" | |
266eb58a | 6374 | [(set_attr "type" "compare") |
9ebbca7d | 6375 | (set_attr "length" "8,12")]) |
266eb58a | 6376 | |
9ebbca7d GK |
6377 | (define_split |
6378 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6379 | (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
2bfcf297 | 6380 | (match_operand:DI 2 "exact_log2_cint_operand" "")) |
9ebbca7d GK |
6381 | (const_int 0))) |
6382 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6383 | (div:DI (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 6384 | "TARGET_POWERPC64 && reload_completed" |
9ebbca7d GK |
6385 | [(set (match_dup 0) |
6386 | (div:DI (match_dup 1) (match_dup 2))) | |
6387 | (set (match_dup 3) | |
6388 | (compare:CC (match_dup 0) | |
6389 | (const_int 0)))] | |
6390 | "") | |
6391 | ||
6392 | (define_insn "" | |
6393 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
266eb58a | 6394 | (div:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
a260abc9 | 6395 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
266eb58a DE |
6396 | "TARGET_POWERPC64" |
6397 | "divd %0,%1,%2" | |
3cb999d8 | 6398 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6399 | |
6400 | (define_insn "udivdi3" | |
6401 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6402 | (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6403 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
6404 | "TARGET_POWERPC64" | |
6405 | "divdu %0,%1,%2" | |
3cb999d8 | 6406 | [(set_attr "type" "ldiv")]) |
266eb58a DE |
6407 | |
6408 | (define_insn "rotldi3" | |
6409 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6410 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6411 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
6412 | "TARGET_POWERPC64" | |
a66078ee | 6413 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 6414 | |
a260abc9 | 6415 | (define_insn "*rotldi3_internal2" |
9ebbca7d GK |
6416 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6417 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6418 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6419 | (const_int 0))) |
9ebbca7d | 6420 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6421 | "TARGET_64BIT" |
9ebbca7d GK |
6422 | "@ |
6423 | rld%I2cl. %3,%1,%H2,0 | |
6424 | #" | |
6425 | [(set_attr "type" "delayed_compare") | |
6426 | (set_attr "length" "4,8")]) | |
6427 | ||
6428 | (define_split | |
6429 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6430 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6431 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6432 | (const_int 0))) | |
6433 | (clobber (match_scratch:DI 3 ""))] | |
6434 | "TARGET_POWERPC64 && reload_completed" | |
6435 | [(set (match_dup 3) | |
6436 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6437 | (set (match_dup 0) | |
6438 | (compare:CC (match_dup 3) | |
6439 | (const_int 0)))] | |
6440 | "") | |
266eb58a | 6441 | |
a260abc9 | 6442 | (define_insn "*rotldi3_internal3" |
9ebbca7d GK |
6443 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6444 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6445 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6446 | (const_int 0))) |
9ebbca7d | 6447 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6448 | (rotate:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6449 | "TARGET_64BIT" |
9ebbca7d GK |
6450 | "@ |
6451 | rld%I2cl. %0,%1,%H2,0 | |
6452 | #" | |
6453 | [(set_attr "type" "delayed_compare") | |
6454 | (set_attr "length" "4,8")]) | |
6455 | ||
6456 | (define_split | |
6457 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6458 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6459 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6460 | (const_int 0))) | |
6461 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6462 | (rotate:DI (match_dup 1) (match_dup 2)))] | |
6463 | "TARGET_POWERPC64 && reload_completed" | |
6464 | [(set (match_dup 0) | |
6465 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6466 | (set (match_dup 3) | |
6467 | (compare:CC (match_dup 0) | |
6468 | (const_int 0)))] | |
6469 | "") | |
266eb58a | 6470 | |
a260abc9 DE |
6471 | (define_insn "*rotldi3_internal4" |
6472 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6473 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6474 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
ce71f754 | 6475 | (match_operand:DI 3 "mask64_operand" "n")))] |
a260abc9 DE |
6476 | "TARGET_POWERPC64" |
6477 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
6478 | ||
6479 | (define_insn "*rotldi3_internal5" | |
9ebbca7d | 6480 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 | 6481 | (compare:CC (and:DI |
9ebbca7d GK |
6482 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6483 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 6484 | (match_operand:DI 3 "mask64_operand" "n,n")) |
a260abc9 | 6485 | (const_int 0))) |
9ebbca7d | 6486 | (clobber (match_scratch:DI 4 "=r,r"))] |
683bdff7 | 6487 | "TARGET_64BIT" |
9ebbca7d GK |
6488 | "@ |
6489 | rld%I2c%B3. %4,%1,%H2,%S3 | |
6490 | #" | |
6491 | [(set_attr "type" "delayed_compare") | |
6492 | (set_attr "length" "4,8")]) | |
6493 | ||
6494 | (define_split | |
6495 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6496 | (compare:CC (and:DI | |
6497 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6498 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6499 | (match_operand:DI 3 "mask64_operand" "")) | |
6500 | (const_int 0))) | |
6501 | (clobber (match_scratch:DI 4 ""))] | |
6502 | "TARGET_POWERPC64 && reload_completed" | |
6503 | [(set (match_dup 4) | |
6504 | (and:DI (rotate:DI (match_dup 1) | |
6505 | (match_dup 2)) | |
6506 | (match_dup 3))) | |
6507 | (set (match_dup 0) | |
6508 | (compare:CC (match_dup 4) | |
6509 | (const_int 0)))] | |
6510 | "") | |
a260abc9 DE |
6511 | |
6512 | (define_insn "*rotldi3_internal6" | |
9ebbca7d | 6513 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 | 6514 | (compare:CC (and:DI |
9ebbca7d GK |
6515 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6516 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 6517 | (match_operand:DI 3 "mask64_operand" "n,n")) |
a260abc9 | 6518 | (const_int 0))) |
9ebbca7d | 6519 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6520 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 6521 | "TARGET_64BIT" |
9ebbca7d GK |
6522 | "@ |
6523 | rld%I2c%B3. %0,%1,%H2,%S3 | |
6524 | #" | |
6525 | [(set_attr "type" "delayed_compare") | |
6526 | (set_attr "length" "4,8")]) | |
6527 | ||
6528 | (define_split | |
6529 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6530 | (compare:CC (and:DI | |
6531 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6532 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6533 | (match_operand:DI 3 "mask64_operand" "")) | |
6534 | (const_int 0))) | |
6535 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6536 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6537 | "TARGET_POWERPC64 && reload_completed" | |
6538 | [(set (match_dup 0) | |
6539 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
6540 | (set (match_dup 4) | |
6541 | (compare:CC (match_dup 0) | |
6542 | (const_int 0)))] | |
6543 | "") | |
a260abc9 DE |
6544 | |
6545 | (define_insn "*rotldi3_internal7" | |
6546 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6547 | (zero_extend:DI | |
6548 | (subreg:QI | |
6549 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6550 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6551 | "TARGET_POWERPC64" | |
6552 | "rld%I2cl %0,%1,%H2,56") | |
6553 | ||
6554 | (define_insn "*rotldi3_internal8" | |
9ebbca7d | 6555 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6556 | (compare:CC (zero_extend:DI |
6557 | (subreg:QI | |
9ebbca7d GK |
6558 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6559 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6560 | (const_int 0))) |
9ebbca7d | 6561 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6562 | "TARGET_64BIT" |
9ebbca7d GK |
6563 | "@ |
6564 | rld%I2cl. %3,%1,%H2,56 | |
6565 | #" | |
6566 | [(set_attr "type" "delayed_compare") | |
6567 | (set_attr "length" "4,8")]) | |
6568 | ||
6569 | (define_split | |
6570 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6571 | (compare:CC (zero_extend:DI | |
6572 | (subreg:QI | |
6573 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6574 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6575 | (const_int 0))) | |
6576 | (clobber (match_scratch:DI 3 ""))] | |
6577 | "TARGET_POWERPC64 && reload_completed" | |
6578 | [(set (match_dup 3) | |
6579 | (zero_extend:DI (subreg:QI | |
6580 | (rotate:DI (match_dup 1) | |
6581 | (match_dup 2)) 0))) | |
6582 | (set (match_dup 0) | |
6583 | (compare:CC (match_dup 3) | |
6584 | (const_int 0)))] | |
6585 | "") | |
a260abc9 DE |
6586 | |
6587 | (define_insn "*rotldi3_internal9" | |
9ebbca7d | 6588 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6589 | (compare:CC (zero_extend:DI |
6590 | (subreg:QI | |
9ebbca7d GK |
6591 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6592 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6593 | (const_int 0))) |
9ebbca7d | 6594 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6595 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6596 | "TARGET_64BIT" |
9ebbca7d GK |
6597 | "@ |
6598 | rld%I2cl. %0,%1,%H2,56 | |
6599 | #" | |
6600 | [(set_attr "type" "delayed_compare") | |
6601 | (set_attr "length" "4,8")]) | |
6602 | ||
6603 | (define_split | |
6604 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6605 | (compare:CC (zero_extend:DI | |
6606 | (subreg:QI | |
6607 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6608 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6609 | (const_int 0))) | |
6610 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6611 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6612 | "TARGET_POWERPC64 && reload_completed" | |
6613 | [(set (match_dup 0) | |
6614 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6615 | (set (match_dup 3) | |
6616 | (compare:CC (match_dup 0) | |
6617 | (const_int 0)))] | |
6618 | "") | |
a260abc9 DE |
6619 | |
6620 | (define_insn "*rotldi3_internal10" | |
6621 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6622 | (zero_extend:DI | |
6623 | (subreg:HI | |
6624 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6625 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6626 | "TARGET_POWERPC64" | |
6627 | "rld%I2cl %0,%1,%H2,48") | |
6628 | ||
6629 | (define_insn "*rotldi3_internal11" | |
9ebbca7d | 6630 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6631 | (compare:CC (zero_extend:DI |
6632 | (subreg:HI | |
9ebbca7d GK |
6633 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6634 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6635 | (const_int 0))) |
9ebbca7d | 6636 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6637 | "TARGET_64BIT" |
9ebbca7d GK |
6638 | "@ |
6639 | rld%I2cl. %3,%1,%H2,48 | |
6640 | #" | |
6641 | [(set_attr "type" "delayed_compare") | |
6642 | (set_attr "length" "4,8")]) | |
6643 | ||
6644 | (define_split | |
6645 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6646 | (compare:CC (zero_extend:DI | |
6647 | (subreg:HI | |
6648 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6649 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6650 | (const_int 0))) | |
6651 | (clobber (match_scratch:DI 3 ""))] | |
6652 | "TARGET_POWERPC64 && reload_completed" | |
6653 | [(set (match_dup 3) | |
6654 | (zero_extend:DI (subreg:HI | |
6655 | (rotate:DI (match_dup 1) | |
6656 | (match_dup 2)) 0))) | |
6657 | (set (match_dup 0) | |
6658 | (compare:CC (match_dup 3) | |
6659 | (const_int 0)))] | |
6660 | "") | |
a260abc9 DE |
6661 | |
6662 | (define_insn "*rotldi3_internal12" | |
9ebbca7d | 6663 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6664 | (compare:CC (zero_extend:DI |
6665 | (subreg:HI | |
9ebbca7d GK |
6666 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6667 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6668 | (const_int 0))) |
9ebbca7d | 6669 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6670 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6671 | "TARGET_64BIT" |
9ebbca7d GK |
6672 | "@ |
6673 | rld%I2cl. %0,%1,%H2,48 | |
6674 | #" | |
6675 | [(set_attr "type" "delayed_compare") | |
6676 | (set_attr "length" "4,8")]) | |
6677 | ||
6678 | (define_split | |
6679 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6680 | (compare:CC (zero_extend:DI | |
6681 | (subreg:HI | |
6682 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6683 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6684 | (const_int 0))) | |
6685 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6686 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6687 | "TARGET_POWERPC64 && reload_completed" | |
6688 | [(set (match_dup 0) | |
6689 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6690 | (set (match_dup 3) | |
6691 | (compare:CC (match_dup 0) | |
6692 | (const_int 0)))] | |
6693 | "") | |
a260abc9 DE |
6694 | |
6695 | (define_insn "*rotldi3_internal13" | |
6696 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6697 | (zero_extend:DI | |
6698 | (subreg:SI | |
6699 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6700 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6701 | "TARGET_POWERPC64" | |
6702 | "rld%I2cl %0,%1,%H2,32") | |
6703 | ||
6704 | (define_insn "*rotldi3_internal14" | |
9ebbca7d | 6705 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6706 | (compare:CC (zero_extend:DI |
6707 | (subreg:SI | |
9ebbca7d GK |
6708 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6709 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6710 | (const_int 0))) |
9ebbca7d | 6711 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6712 | "TARGET_64BIT" |
9ebbca7d GK |
6713 | "@ |
6714 | rld%I2cl. %3,%1,%H2,32 | |
6715 | #" | |
6716 | [(set_attr "type" "delayed_compare") | |
6717 | (set_attr "length" "4,8")]) | |
6718 | ||
6719 | (define_split | |
6720 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6721 | (compare:CC (zero_extend:DI | |
6722 | (subreg:SI | |
6723 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6724 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6725 | (const_int 0))) | |
6726 | (clobber (match_scratch:DI 3 ""))] | |
6727 | "TARGET_POWERPC64 && reload_completed" | |
6728 | [(set (match_dup 3) | |
6729 | (zero_extend:DI (subreg:SI | |
6730 | (rotate:DI (match_dup 1) | |
6731 | (match_dup 2)) 0))) | |
6732 | (set (match_dup 0) | |
6733 | (compare:CC (match_dup 3) | |
6734 | (const_int 0)))] | |
6735 | "") | |
a260abc9 DE |
6736 | |
6737 | (define_insn "*rotldi3_internal15" | |
9ebbca7d | 6738 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6739 | (compare:CC (zero_extend:DI |
6740 | (subreg:SI | |
9ebbca7d GK |
6741 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6742 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6743 | (const_int 0))) |
9ebbca7d | 6744 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6745 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6746 | "TARGET_64BIT" |
9ebbca7d GK |
6747 | "@ |
6748 | rld%I2cl. %0,%1,%H2,32 | |
6749 | #" | |
6750 | [(set_attr "type" "delayed_compare") | |
6751 | (set_attr "length" "4,8")]) | |
6752 | ||
6753 | (define_split | |
6754 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6755 | (compare:CC (zero_extend:DI | |
6756 | (subreg:SI | |
6757 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6758 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6759 | (const_int 0))) | |
6760 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6761 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6762 | "TARGET_POWERPC64 && reload_completed" | |
6763 | [(set (match_dup 0) | |
6764 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6765 | (set (match_dup 3) | |
6766 | (compare:CC (match_dup 0) | |
6767 | (const_int 0)))] | |
6768 | "") | |
a260abc9 | 6769 | |
266eb58a DE |
6770 | (define_expand "ashldi3" |
6771 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6772 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6773 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6774 | "TARGET_POWERPC64 || TARGET_POWER" | |
6775 | " | |
6776 | { | |
6777 | if (TARGET_POWERPC64) | |
6778 | ; | |
6779 | else if (TARGET_POWER) | |
6780 | { | |
6781 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
6782 | DONE; | |
6783 | } | |
6784 | else | |
6785 | FAIL; | |
6786 | }") | |
6787 | ||
e2c953b6 | 6788 | (define_insn "*ashldi3_internal1" |
266eb58a DE |
6789 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6790 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6791 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6792 | "TARGET_POWERPC64" | |
a66078ee | 6793 | "sld%I2 %0,%1,%H2" |
266eb58a | 6794 | [(set_attr "length" "8")]) |
6ae08853 | 6795 | |
e2c953b6 | 6796 | (define_insn "*ashldi3_internal2" |
9ebbca7d GK |
6797 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6798 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6799 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6800 | (const_int 0))) |
9ebbca7d | 6801 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6802 | "TARGET_64BIT" |
9ebbca7d GK |
6803 | "@ |
6804 | sld%I2. %3,%1,%H2 | |
6805 | #" | |
6806 | [(set_attr "type" "delayed_compare") | |
6807 | (set_attr "length" "4,8")]) | |
6ae08853 | 6808 | |
9ebbca7d GK |
6809 | (define_split |
6810 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6811 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6812 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6813 | (const_int 0))) | |
6814 | (clobber (match_scratch:DI 3 ""))] | |
6815 | "TARGET_POWERPC64 && reload_completed" | |
6816 | [(set (match_dup 3) | |
6817 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6818 | (set (match_dup 0) | |
6819 | (compare:CC (match_dup 3) | |
6820 | (const_int 0)))] | |
6821 | "") | |
6822 | ||
e2c953b6 | 6823 | (define_insn "*ashldi3_internal3" |
9ebbca7d GK |
6824 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6825 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6826 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6827 | (const_int 0))) |
9ebbca7d | 6828 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6829 | (ashift:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6830 | "TARGET_64BIT" |
9ebbca7d GK |
6831 | "@ |
6832 | sld%I2. %0,%1,%H2 | |
6833 | #" | |
6834 | [(set_attr "type" "delayed_compare") | |
6835 | (set_attr "length" "4,8")]) | |
6836 | ||
6837 | (define_split | |
6838 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6839 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6840 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6841 | (const_int 0))) | |
6842 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6843 | (ashift:DI (match_dup 1) (match_dup 2)))] | |
6844 | "TARGET_POWERPC64 && reload_completed" | |
6845 | [(set (match_dup 0) | |
6846 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6847 | (set (match_dup 3) | |
6848 | (compare:CC (match_dup 0) | |
6849 | (const_int 0)))] | |
6850 | "") | |
266eb58a | 6851 | |
e2c953b6 | 6852 | (define_insn "*ashldi3_internal4" |
3cb999d8 DE |
6853 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6854 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6855 | (match_operand:SI 2 "const_int_operand" "i")) | |
c5059423 AM |
6856 | (match_operand:DI 3 "const_int_operand" "n")))] |
6857 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" | |
e2c953b6 | 6858 | "rldic %0,%1,%H2,%W3") |
3cb999d8 | 6859 | |
e2c953b6 | 6860 | (define_insn "ashldi3_internal5" |
9ebbca7d | 6861 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6862 | (compare:CC |
9ebbca7d GK |
6863 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6864 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6865 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6866 | (const_int 0))) |
9ebbca7d | 6867 | (clobber (match_scratch:DI 4 "=r,r"))] |
683bdff7 | 6868 | "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6869 | "@ |
e2c953b6 | 6870 | rldic. %4,%1,%H2,%W3 |
9ebbca7d GK |
6871 | #" |
6872 | [(set_attr "type" "delayed_compare") | |
6873 | (set_attr "length" "4,8")]) | |
6874 | ||
6875 | (define_split | |
6876 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6877 | (compare:CC | |
6878 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6879 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6880 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6881 | (const_int 0))) |
6882 | (clobber (match_scratch:DI 4 ""))] | |
c5059423 AM |
6883 | "TARGET_POWERPC64 && reload_completed |
6884 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
9ebbca7d GK |
6885 | [(set (match_dup 4) |
6886 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
e2c953b6 | 6887 | (match_dup 3))) |
9ebbca7d GK |
6888 | (set (match_dup 0) |
6889 | (compare:CC (match_dup 4) | |
6890 | (const_int 0)))] | |
6891 | "") | |
3cb999d8 | 6892 | |
e2c953b6 | 6893 | (define_insn "*ashldi3_internal6" |
9ebbca7d | 6894 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6895 | (compare:CC |
9ebbca7d GK |
6896 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6897 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6898 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6899 | (const_int 0))) |
9ebbca7d | 6900 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3cb999d8 | 6901 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 6902 | "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6903 | "@ |
e2c953b6 | 6904 | rldic. %0,%1,%H2,%W3 |
9ebbca7d GK |
6905 | #" |
6906 | [(set_attr "type" "delayed_compare") | |
6907 | (set_attr "length" "4,8")]) | |
6908 | ||
6909 | (define_split | |
6910 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6911 | (compare:CC | |
6912 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6913 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6914 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6915 | (const_int 0))) |
6916 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6917 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
c5059423 AM |
6918 | "TARGET_POWERPC64 && reload_completed |
6919 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
6920 | [(set (match_dup 0) | |
6921 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6922 | (match_dup 3))) | |
6923 | (set (match_dup 4) | |
6924 | (compare:CC (match_dup 0) | |
6925 | (const_int 0)))] | |
6926 | "") | |
6927 | ||
6928 | (define_insn "*ashldi3_internal7" | |
6929 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6930 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6931 | (match_operand:SI 2 "const_int_operand" "i")) | |
ce71f754 | 6932 | (match_operand:DI 3 "mask64_operand" "n")))] |
c5059423 AM |
6933 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" |
6934 | "rldicr %0,%1,%H2,%S3") | |
6935 | ||
6936 | (define_insn "ashldi3_internal8" | |
6937 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
6938 | (compare:CC | |
6939 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6940 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 6941 | (match_operand:DI 3 "mask64_operand" "n,n")) |
c5059423 AM |
6942 | (const_int 0))) |
6943 | (clobber (match_scratch:DI 4 "=r,r"))] | |
683bdff7 | 6944 | "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" |
c5059423 AM |
6945 | "@ |
6946 | rldicr. %4,%1,%H2,%S3 | |
6947 | #" | |
6948 | [(set_attr "type" "delayed_compare") | |
6949 | (set_attr "length" "4,8")]) | |
6950 | ||
6951 | (define_split | |
6952 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6953 | (compare:CC | |
6954 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6955 | (match_operand:SI 2 "const_int_operand" "")) | |
6956 | (match_operand:DI 3 "mask64_operand" "")) | |
6957 | (const_int 0))) | |
6958 | (clobber (match_scratch:DI 4 ""))] | |
6959 | "TARGET_POWERPC64 && reload_completed | |
6960 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6961 | [(set (match_dup 4) | |
6962 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6963 | (match_dup 3))) | |
6964 | (set (match_dup 0) | |
6965 | (compare:CC (match_dup 4) | |
6966 | (const_int 0)))] | |
6967 | "") | |
6968 | ||
6969 | (define_insn "*ashldi3_internal9" | |
6970 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
6971 | (compare:CC | |
6972 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6973 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 6974 | (match_operand:DI 3 "mask64_operand" "n,n")) |
c5059423 AM |
6975 | (const_int 0))) |
6976 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6977 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 6978 | "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" |
c5059423 AM |
6979 | "@ |
6980 | rldicr. %0,%1,%H2,%S3 | |
6981 | #" | |
6982 | [(set_attr "type" "delayed_compare") | |
6983 | (set_attr "length" "4,8")]) | |
6984 | ||
6985 | (define_split | |
6986 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6987 | (compare:CC | |
6988 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6989 | (match_operand:SI 2 "const_int_operand" "")) | |
6990 | (match_operand:DI 3 "mask64_operand" "")) | |
6991 | (const_int 0))) | |
6992 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6993 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6994 | "TARGET_POWERPC64 && reload_completed | |
6995 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
9ebbca7d | 6996 | [(set (match_dup 0) |
e2c953b6 DE |
6997 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) |
6998 | (match_dup 3))) | |
9ebbca7d GK |
6999 | (set (match_dup 4) |
7000 | (compare:CC (match_dup 0) | |
7001 | (const_int 0)))] | |
7002 | "") | |
7003 | ||
7004 | (define_expand "lshrdi3" | |
266eb58a DE |
7005 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
7006 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7007 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
7008 | "TARGET_POWERPC64 || TARGET_POWER" | |
7009 | " | |
7010 | { | |
7011 | if (TARGET_POWERPC64) | |
7012 | ; | |
7013 | else if (TARGET_POWER) | |
7014 | { | |
7015 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
7016 | DONE; | |
7017 | } | |
7018 | else | |
7019 | FAIL; | |
7020 | }") | |
7021 | ||
e2c953b6 | 7022 | (define_insn "*lshrdi3_internal1" |
266eb58a DE |
7023 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
7024 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7025 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
7026 | "TARGET_POWERPC64" | |
a66078ee | 7027 | "srd%I2 %0,%1,%H2") |
266eb58a | 7028 | |
e2c953b6 | 7029 | (define_insn "*lshrdi3_internal2" |
9ebbca7d GK |
7030 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
7031 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7032 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
29ae5b89 | 7033 | (const_int 0))) |
9ebbca7d | 7034 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7035 | "TARGET_64BIT " |
9ebbca7d GK |
7036 | "@ |
7037 | srd%I2. %3,%1,%H2 | |
7038 | #" | |
7039 | [(set_attr "type" "delayed_compare") | |
7040 | (set_attr "length" "4,8")]) | |
7041 | ||
7042 | (define_split | |
7043 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7044 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7045 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7046 | (const_int 0))) | |
7047 | (clobber (match_scratch:DI 3 ""))] | |
7048 | "TARGET_POWERPC64 && reload_completed" | |
7049 | [(set (match_dup 3) | |
7050 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
7051 | (set (match_dup 0) | |
7052 | (compare:CC (match_dup 3) | |
7053 | (const_int 0)))] | |
7054 | "") | |
266eb58a | 7055 | |
e2c953b6 | 7056 | (define_insn "*lshrdi3_internal3" |
9ebbca7d GK |
7057 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
7058 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7059 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7060 | (const_int 0))) |
9ebbca7d | 7061 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 7062 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 7063 | "TARGET_64BIT" |
9ebbca7d GK |
7064 | "@ |
7065 | srd%I2. %0,%1,%H2 | |
7066 | #" | |
7067 | [(set_attr "type" "delayed_compare") | |
7068 | (set_attr "length" "4,8")]) | |
7069 | ||
7070 | (define_split | |
7071 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7072 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7073 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7074 | (const_int 0))) | |
7075 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7076 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
7077 | "TARGET_POWERPC64 && reload_completed" | |
7078 | [(set (match_dup 0) | |
7079 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
7080 | (set (match_dup 3) | |
7081 | (compare:CC (match_dup 0) | |
7082 | (const_int 0)))] | |
7083 | "") | |
266eb58a DE |
7084 | |
7085 | (define_expand "ashrdi3" | |
7086 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7087 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7088 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
97727e85 | 7089 | "WORDS_BIG_ENDIAN" |
266eb58a DE |
7090 | " |
7091 | { | |
7092 | if (TARGET_POWERPC64) | |
7093 | ; | |
7094 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
7095 | { | |
7096 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
7097 | DONE; | |
7098 | } | |
97727e85 AH |
7099 | else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT |
7100 | && WORDS_BIG_ENDIAN) | |
4aa74a4f FS |
7101 | { |
7102 | emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); | |
7103 | DONE; | |
7104 | } | |
266eb58a DE |
7105 | else |
7106 | FAIL; | |
7107 | }") | |
7108 | ||
e2c953b6 | 7109 | (define_insn "*ashrdi3_internal1" |
266eb58a DE |
7110 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
7111 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
7112 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
7113 | "TARGET_POWERPC64" | |
375490e0 | 7114 | "srad%I2 %0,%1,%H2") |
266eb58a | 7115 | |
e2c953b6 | 7116 | (define_insn "*ashrdi3_internal2" |
9ebbca7d GK |
7117 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
7118 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7119 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7120 | (const_int 0))) |
9ebbca7d | 7121 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7122 | "TARGET_64BIT" |
9ebbca7d GK |
7123 | "@ |
7124 | srad%I2. %3,%1,%H2 | |
7125 | #" | |
7126 | [(set_attr "type" "delayed_compare") | |
7127 | (set_attr "length" "4,8")]) | |
7128 | ||
7129 | (define_split | |
7130 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7131 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7132 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7133 | (const_int 0))) | |
7134 | (clobber (match_scratch:DI 3 ""))] | |
7135 | "TARGET_POWERPC64 && reload_completed" | |
7136 | [(set (match_dup 3) | |
7137 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
7138 | (set (match_dup 0) | |
7139 | (compare:CC (match_dup 3) | |
7140 | (const_int 0)))] | |
7141 | "") | |
266eb58a | 7142 | |
e2c953b6 | 7143 | (define_insn "*ashrdi3_internal3" |
9ebbca7d GK |
7144 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
7145 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
7146 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 7147 | (const_int 0))) |
9ebbca7d | 7148 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 7149 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 7150 | "TARGET_64BIT" |
9ebbca7d GK |
7151 | "@ |
7152 | srad%I2. %0,%1,%H2 | |
7153 | #" | |
7154 | [(set_attr "type" "delayed_compare") | |
7155 | (set_attr "length" "4,8")]) | |
7156 | ||
7157 | (define_split | |
7158 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7159 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7160 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
7161 | (const_int 0))) | |
7162 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7163 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
7164 | "TARGET_POWERPC64 && reload_completed" | |
7165 | [(set (match_dup 0) | |
7166 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
7167 | (set (match_dup 3) | |
7168 | (compare:CC (match_dup 0) | |
7169 | (const_int 0)))] | |
7170 | "") | |
815cdc52 | 7171 | |
29ae5b89 | 7172 | (define_insn "anddi3" |
0ba1b2ff AM |
7173 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") |
7174 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
7175 | (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t"))) | |
7176 | (clobber (match_scratch:CC 3 "=X,X,x,x,X"))] | |
6ffc8580 | 7177 | "TARGET_POWERPC64" |
266eb58a DE |
7178 | "@ |
7179 | and %0,%1,%2 | |
29ae5b89 JL |
7180 | rldic%B2 %0,%1,0,%S2 |
7181 | andi. %0,%1,%b2 | |
0ba1b2ff AM |
7182 | andis. %0,%1,%u2 |
7183 | #" | |
520308bc DE |
7184 | [(set_attr "type" "*,*,compare,compare,*") |
7185 | (set_attr "length" "4,4,4,4,8")]) | |
0ba1b2ff AM |
7186 | |
7187 | (define_split | |
7188 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7189 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7190 | (match_operand:DI 2 "mask64_2_operand" ""))) | |
7191 | (clobber (match_scratch:CC 3 ""))] | |
7192 | "TARGET_POWERPC64 | |
7193 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7194 | && !mask64_operand (operands[2], DImode)" | |
7195 | [(set (match_dup 0) | |
7196 | (and:DI (rotate:DI (match_dup 1) | |
7197 | (match_dup 4)) | |
7198 | (match_dup 5))) | |
7199 | (set (match_dup 0) | |
7200 | (and:DI (rotate:DI (match_dup 0) | |
7201 | (match_dup 6)) | |
7202 | (match_dup 7)))] | |
7203 | " | |
7204 | { | |
7205 | build_mask64_2_operands (operands[2], &operands[4]); | |
7206 | }") | |
266eb58a | 7207 | |
a260abc9 | 7208 | (define_insn "*anddi3_internal2" |
0ba1b2ff AM |
7209 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
7210 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
7211 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 7212 | (const_int 0))) |
0ba1b2ff AM |
7213 | (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r")) |
7214 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] | |
683bdff7 | 7215 | "TARGET_64BIT" |
266eb58a DE |
7216 | "@ |
7217 | and. %3,%1,%2 | |
6c873122 | 7218 | rldic%B2. %3,%1,0,%S2 |
6ffc8580 MM |
7219 | andi. %3,%1,%b2 |
7220 | andis. %3,%1,%u2 | |
9ebbca7d GK |
7221 | # |
7222 | # | |
7223 | # | |
0ba1b2ff AM |
7224 | # |
7225 | # | |
9ebbca7d | 7226 | #" |
0ba1b2ff AM |
7227 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
7228 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
7229 | |
7230 | (define_split | |
7231 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
7232 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7233 | (match_operand:DI 2 "and64_operand" "")) | |
7234 | (const_int 0))) | |
7235 | (clobber (match_scratch:DI 3 "")) | |
7236 | (clobber (match_scratch:CC 4 ""))] | |
7237 | "TARGET_POWERPC64 && reload_completed" | |
7238 | [(parallel [(set (match_dup 3) | |
7239 | (and:DI (match_dup 1) | |
7240 | (match_dup 2))) | |
7241 | (clobber (match_dup 4))]) | |
7242 | (set (match_dup 0) | |
7243 | (compare:CC (match_dup 3) | |
7244 | (const_int 0)))] | |
7245 | "") | |
266eb58a | 7246 | |
0ba1b2ff AM |
7247 | (define_split |
7248 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
7249 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7250 | (match_operand:DI 2 "mask64_2_operand" "")) | |
7251 | (const_int 0))) | |
7252 | (clobber (match_scratch:DI 3 "")) | |
7253 | (clobber (match_scratch:CC 4 ""))] | |
7254 | "TARGET_POWERPC64 && reload_completed | |
7255 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7256 | && !mask64_operand (operands[2], DImode)" | |
7257 | [(set (match_dup 3) | |
7258 | (and:DI (rotate:DI (match_dup 1) | |
7259 | (match_dup 5)) | |
7260 | (match_dup 6))) | |
7261 | (parallel [(set (match_dup 0) | |
7262 | (compare:CC (and:DI (rotate:DI (match_dup 3) | |
7263 | (match_dup 7)) | |
7264 | (match_dup 8)) | |
7265 | (const_int 0))) | |
7266 | (clobber (match_dup 3))])] | |
7267 | " | |
7268 | { | |
7269 | build_mask64_2_operands (operands[2], &operands[5]); | |
7270 | }") | |
7271 | ||
a260abc9 | 7272 | (define_insn "*anddi3_internal3" |
0ba1b2ff AM |
7273 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
7274 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
7275 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 7276 | (const_int 0))) |
0ba1b2ff | 7277 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
9ebbca7d | 7278 | (and:DI (match_dup 1) (match_dup 2))) |
0ba1b2ff | 7279 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] |
683bdff7 | 7280 | "TARGET_64BIT" |
266eb58a DE |
7281 | "@ |
7282 | and. %0,%1,%2 | |
6c873122 | 7283 | rldic%B2. %0,%1,0,%S2 |
6ffc8580 MM |
7284 | andi. %0,%1,%b2 |
7285 | andis. %0,%1,%u2 | |
9ebbca7d GK |
7286 | # |
7287 | # | |
7288 | # | |
0ba1b2ff AM |
7289 | # |
7290 | # | |
9ebbca7d | 7291 | #" |
0ba1b2ff AM |
7292 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
7293 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
7294 | |
7295 | (define_split | |
7296 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
7297 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7298 | (match_operand:DI 2 "and64_operand" "")) | |
7299 | (const_int 0))) | |
7300 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7301 | (and:DI (match_dup 1) (match_dup 2))) | |
7302 | (clobber (match_scratch:CC 4 ""))] | |
7303 | "TARGET_POWERPC64 && reload_completed" | |
7304 | [(parallel [(set (match_dup 0) | |
7305 | (and:DI (match_dup 1) (match_dup 2))) | |
7306 | (clobber (match_dup 4))]) | |
7307 | (set (match_dup 3) | |
7308 | (compare:CC (match_dup 0) | |
7309 | (const_int 0)))] | |
7310 | "") | |
266eb58a | 7311 | |
0ba1b2ff AM |
7312 | (define_split |
7313 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
7314 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
7315 | (match_operand:DI 2 "mask64_2_operand" "")) | |
7316 | (const_int 0))) | |
7317 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
7318 | (and:DI (match_dup 1) (match_dup 2))) | |
7319 | (clobber (match_scratch:CC 4 ""))] | |
7320 | "TARGET_POWERPC64 && reload_completed | |
7321 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
7322 | && !mask64_operand (operands[2], DImode)" | |
7323 | [(set (match_dup 0) | |
7324 | (and:DI (rotate:DI (match_dup 1) | |
7325 | (match_dup 5)) | |
7326 | (match_dup 6))) | |
7327 | (parallel [(set (match_dup 3) | |
7328 | (compare:CC (and:DI (rotate:DI (match_dup 0) | |
7329 | (match_dup 7)) | |
7330 | (match_dup 8)) | |
7331 | (const_int 0))) | |
7332 | (set (match_dup 0) | |
7333 | (and:DI (rotate:DI (match_dup 0) | |
7334 | (match_dup 7)) | |
7335 | (match_dup 8)))])] | |
7336 | " | |
7337 | { | |
7338 | build_mask64_2_operands (operands[2], &operands[5]); | |
7339 | }") | |
7340 | ||
a260abc9 | 7341 | (define_expand "iordi3" |
266eb58a | 7342 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 | 7343 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
1d328b19 | 7344 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
266eb58a | 7345 | "TARGET_POWERPC64" |
266eb58a DE |
7346 | " |
7347 | { | |
dfbdccdb | 7348 | if (non_logical_cint_operand (operands[2], DImode)) |
266eb58a | 7349 | { |
dfbdccdb | 7350 | HOST_WIDE_INT value; |
677a9668 | 7351 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 | 7352 | ? operands[0] : gen_reg_rtx (DImode)); |
266eb58a | 7353 | |
dfbdccdb GK |
7354 | if (GET_CODE (operands[2]) == CONST_INT) |
7355 | { | |
7356 | value = INTVAL (operands[2]); | |
7357 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7358 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7359 | } | |
e2c953b6 | 7360 | else |
dfbdccdb GK |
7361 | { |
7362 | value = CONST_DOUBLE_LOW (operands[2]); | |
7363 | emit_insn (gen_iordi3 (tmp, operands[1], | |
7364 | immed_double_const (value | |
7365 | & (~ (HOST_WIDE_INT) 0xffff), | |
7366 | 0, DImode))); | |
7367 | } | |
e2c953b6 | 7368 | |
9ebbca7d GK |
7369 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7370 | DONE; | |
7371 | } | |
266eb58a DE |
7372 | }") |
7373 | ||
a260abc9 DE |
7374 | (define_expand "xordi3" |
7375 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
7376 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
1d328b19 | 7377 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
a260abc9 DE |
7378 | "TARGET_POWERPC64" |
7379 | " | |
7380 | { | |
dfbdccdb | 7381 | if (non_logical_cint_operand (operands[2], DImode)) |
a260abc9 | 7382 | { |
dfbdccdb | 7383 | HOST_WIDE_INT value; |
677a9668 | 7384 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
7385 | ? operands[0] : gen_reg_rtx (DImode)); |
7386 | ||
dfbdccdb GK |
7387 | if (GET_CODE (operands[2]) == CONST_INT) |
7388 | { | |
7389 | value = INTVAL (operands[2]); | |
7390 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7391 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7392 | } | |
e2c953b6 | 7393 | else |
dfbdccdb GK |
7394 | { |
7395 | value = CONST_DOUBLE_LOW (operands[2]); | |
7396 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7397 | immed_double_const (value | |
7398 | & (~ (HOST_WIDE_INT) 0xffff), | |
7399 | 0, DImode))); | |
7400 | } | |
e2c953b6 | 7401 | |
9ebbca7d GK |
7402 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7403 | DONE; | |
7404 | } | |
a260abc9 DE |
7405 | }") |
7406 | ||
dfbdccdb | 7407 | (define_insn "*booldi3_internal1" |
266eb58a | 7408 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 7409 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7410 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") |
7411 | (match_operand:DI 2 "logical_operand" "r,K,JF")]))] | |
266eb58a | 7412 | "TARGET_POWERPC64" |
1fd4e8c1 | 7413 | "@ |
dfbdccdb GK |
7414 | %q3 %0,%1,%2 |
7415 | %q3i %0,%1,%b2 | |
7416 | %q3is %0,%1,%u2") | |
1fd4e8c1 | 7417 | |
dfbdccdb | 7418 | (define_insn "*booldi3_internal2" |
9ebbca7d | 7419 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 7420 | (compare:CC (match_operator:DI 4 "boolean_or_operator" |
dfbdccdb GK |
7421 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") |
7422 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7423 | (const_int 0))) | |
9ebbca7d | 7424 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7425 | "TARGET_64BIT" |
9ebbca7d | 7426 | "@ |
dfbdccdb | 7427 | %q4. %3,%1,%2 |
9ebbca7d GK |
7428 | #" |
7429 | [(set_attr "type" "compare") | |
7430 | (set_attr "length" "4,8")]) | |
7431 | ||
7432 | (define_split | |
7433 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7434 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7435 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7436 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7437 | (const_int 0))) |
9ebbca7d GK |
7438 | (clobber (match_scratch:DI 3 ""))] |
7439 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7440 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7441 | (set (match_dup 0) |
7442 | (compare:CC (match_dup 3) | |
7443 | (const_int 0)))] | |
7444 | "") | |
1fd4e8c1 | 7445 | |
dfbdccdb | 7446 | (define_insn "*booldi3_internal3" |
9ebbca7d | 7447 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7448 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7449 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7450 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7451 | (const_int 0))) | |
9ebbca7d | 7452 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7453 | (match_dup 4))] |
683bdff7 | 7454 | "TARGET_64BIT" |
9ebbca7d | 7455 | "@ |
dfbdccdb | 7456 | %q4. %0,%1,%2 |
9ebbca7d GK |
7457 | #" |
7458 | [(set_attr "type" "compare") | |
7459 | (set_attr "length" "4,8")]) | |
7460 | ||
7461 | (define_split | |
e72247f4 | 7462 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7463 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7464 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7465 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7466 | (const_int 0))) |
75540af0 | 7467 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7468 | (match_dup 4))] |
9ebbca7d | 7469 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7470 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7471 | (set (match_dup 3) |
7472 | (compare:CC (match_dup 0) | |
7473 | (const_int 0)))] | |
7474 | "") | |
1fd4e8c1 | 7475 | |
6ae08853 | 7476 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 7477 | ;; each of which does one 16-bit part. This is used by combine. |
266eb58a DE |
7478 | |
7479 | (define_split | |
7480 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1d328b19 | 7481 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7482 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7483 | (match_operand:DI 2 "non_logical_cint_operand" "")]))] | |
266eb58a | 7484 | "TARGET_POWERPC64" |
dfbdccdb GK |
7485 | [(set (match_dup 0) (match_dup 4)) |
7486 | (set (match_dup 0) (match_dup 5))] | |
266eb58a DE |
7487 | " |
7488 | { | |
dfbdccdb | 7489 | rtx i3,i4; |
6ae08853 | 7490 | |
9ebbca7d GK |
7491 | if (GET_CODE (operands[2]) == CONST_DOUBLE) |
7492 | { | |
7493 | HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); | |
dfbdccdb | 7494 | i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), |
9ebbca7d | 7495 | 0, DImode); |
dfbdccdb | 7496 | i4 = GEN_INT (value & 0xffff); |
9ebbca7d GK |
7497 | } |
7498 | else | |
7499 | { | |
dfbdccdb | 7500 | i3 = GEN_INT (INTVAL (operands[2]) |
9ebbca7d | 7501 | & (~ (HOST_WIDE_INT) 0xffff)); |
dfbdccdb | 7502 | i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); |
9ebbca7d | 7503 | } |
1c563bed | 7504 | operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, |
0f4c242b | 7505 | operands[1], i3); |
1c563bed | 7506 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, |
0f4c242b | 7507 | operands[0], i4); |
1fd4e8c1 RK |
7508 | }") |
7509 | ||
dfbdccdb | 7510 | (define_insn "*boolcdi3_internal1" |
9ebbca7d | 7511 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7512 | (match_operator:DI 3 "boolean_operator" |
7513 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7514 | (match_operand:DI 2 "gpc_reg_operand" "r")]))] |
a473029f | 7515 | "TARGET_POWERPC64" |
1d328b19 | 7516 | "%q3 %0,%2,%1") |
a473029f | 7517 | |
dfbdccdb | 7518 | (define_insn "*boolcdi3_internal2" |
9ebbca7d | 7519 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7520 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7521 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7522 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7523 | (const_int 0))) | |
9ebbca7d | 7524 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7525 | "TARGET_64BIT" |
9ebbca7d | 7526 | "@ |
1d328b19 | 7527 | %q4. %3,%2,%1 |
9ebbca7d GK |
7528 | #" |
7529 | [(set_attr "type" "compare") | |
7530 | (set_attr "length" "4,8")]) | |
7531 | ||
7532 | (define_split | |
7533 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7534 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7535 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7536 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7537 | (const_int 0))) |
9ebbca7d GK |
7538 | (clobber (match_scratch:DI 3 ""))] |
7539 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7540 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7541 | (set (match_dup 0) |
7542 | (compare:CC (match_dup 3) | |
7543 | (const_int 0)))] | |
7544 | "") | |
a473029f | 7545 | |
dfbdccdb | 7546 | (define_insn "*boolcdi3_internal3" |
9ebbca7d | 7547 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7548 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7549 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7550 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7551 | (const_int 0))) | |
9ebbca7d | 7552 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7553 | (match_dup 4))] |
683bdff7 | 7554 | "TARGET_64BIT" |
9ebbca7d | 7555 | "@ |
1d328b19 | 7556 | %q4. %0,%2,%1 |
9ebbca7d GK |
7557 | #" |
7558 | [(set_attr "type" "compare") | |
7559 | (set_attr "length" "4,8")]) | |
7560 | ||
7561 | (define_split | |
e72247f4 | 7562 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7563 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7564 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7565 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7566 | (const_int 0))) |
75540af0 | 7567 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7568 | (match_dup 4))] |
9ebbca7d | 7569 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7570 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7571 | (set (match_dup 3) |
7572 | (compare:CC (match_dup 0) | |
7573 | (const_int 0)))] | |
7574 | "") | |
266eb58a | 7575 | |
dfbdccdb | 7576 | (define_insn "*boolccdi3_internal1" |
a473029f | 7577 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7578 | (match_operator:DI 3 "boolean_operator" |
7579 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7580 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))] |
a473029f | 7581 | "TARGET_POWERPC64" |
dfbdccdb | 7582 | "%q3 %0,%1,%2") |
a473029f | 7583 | |
dfbdccdb | 7584 | (define_insn "*boolccdi3_internal2" |
9ebbca7d | 7585 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7586 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7587 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7588 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7589 | (const_int 0))) | |
9ebbca7d | 7590 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7591 | "TARGET_64BIT" |
9ebbca7d | 7592 | "@ |
dfbdccdb | 7593 | %q4. %3,%1,%2 |
9ebbca7d GK |
7594 | #" |
7595 | [(set_attr "type" "compare") | |
7596 | (set_attr "length" "4,8")]) | |
7597 | ||
7598 | (define_split | |
7599 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7600 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7601 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7602 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7603 | (const_int 0))) |
9ebbca7d GK |
7604 | (clobber (match_scratch:DI 3 ""))] |
7605 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7606 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7607 | (set (match_dup 0) |
7608 | (compare:CC (match_dup 3) | |
7609 | (const_int 0)))] | |
7610 | "") | |
266eb58a | 7611 | |
dfbdccdb | 7612 | (define_insn "*boolccdi3_internal3" |
9ebbca7d | 7613 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7614 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7615 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7616 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7617 | (const_int 0))) | |
9ebbca7d | 7618 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7619 | (match_dup 4))] |
683bdff7 | 7620 | "TARGET_64BIT" |
9ebbca7d | 7621 | "@ |
dfbdccdb | 7622 | %q4. %0,%1,%2 |
9ebbca7d GK |
7623 | #" |
7624 | [(set_attr "type" "compare") | |
7625 | (set_attr "length" "4,8")]) | |
7626 | ||
7627 | (define_split | |
e72247f4 | 7628 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7629 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7630 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7631 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7632 | (const_int 0))) |
75540af0 | 7633 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7634 | (match_dup 4))] |
9ebbca7d | 7635 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7636 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7637 | (set (match_dup 3) |
7638 | (compare:CC (match_dup 0) | |
7639 | (const_int 0)))] | |
7640 | "") | |
dfbdccdb | 7641 | \f |
1fd4e8c1 | 7642 | ;; Now define ways of moving data around. |
4697a36c MM |
7643 | |
7644 | ;; Elf specific ways of loading addresses for non-PIC code. | |
9ebbca7d GK |
7645 | ;; The output of this could be r0, but we make a very strong |
7646 | ;; preference for a base register because it will usually | |
7647 | ;; be needed there. | |
4697a36c | 7648 | (define_insn "elf_high" |
9ebbca7d | 7649 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") |
4697a36c | 7650 | (high:SI (match_operand 1 "" "")))] |
0ad91047 | 7651 | "TARGET_ELF && ! TARGET_64BIT" |
a6c2a102 | 7652 | "{liu|lis} %0,%1@ha") |
4697a36c MM |
7653 | |
7654 | (define_insn "elf_low" | |
9ebbca7d GK |
7655 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
7656 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
4697a36c | 7657 | (match_operand 2 "" "")))] |
0ad91047 | 7658 | "TARGET_ELF && ! TARGET_64BIT" |
9ebbca7d GK |
7659 | "@ |
7660 | {cal|la} %0,%2@l(%1) | |
81eace42 | 7661 | {ai|addic} %0,%1,%K2") |
4697a36c | 7662 | |
ee890fe2 | 7663 | |
766a866c MM |
7664 | ;; Set up a register with a value from the GOT table |
7665 | ||
7666 | (define_expand "movsi_got" | |
52d3af72 | 7667 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7668 | (unspec:SI [(match_operand:SI 1 "got_operand" "") |
615158e2 | 7669 | (match_dup 2)] UNSPEC_MOVSI_GOT))] |
f607bc57 | 7670 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7671 | " |
7672 | { | |
38c1f2d7 MM |
7673 | if (GET_CODE (operands[1]) == CONST) |
7674 | { | |
7675 | rtx offset = const0_rtx; | |
7676 | HOST_WIDE_INT value; | |
7677 | ||
7678 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
7679 | value = INTVAL (offset); | |
7680 | if (value != 0) | |
7681 | { | |
677a9668 | 7682 | rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); |
38c1f2d7 MM |
7683 | emit_insn (gen_movsi_got (tmp, operands[1])); |
7684 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
7685 | DONE; | |
7686 | } | |
7687 | } | |
7688 | ||
c4c40373 | 7689 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
7690 | }") |
7691 | ||
84f414bc | 7692 | (define_insn "*movsi_got_internal" |
52d3af72 | 7693 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d | 7694 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
615158e2 JJ |
7695 | (match_operand:SI 2 "gpc_reg_operand" "b")] |
7696 | UNSPEC_MOVSI_GOT))] | |
f607bc57 | 7697 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7698 | "{l|lwz} %0,%a1@got(%2)" |
7699 | [(set_attr "type" "load")]) | |
7700 | ||
b22b9b3e JL |
7701 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg |
7702 | ;; didn't get allocated to a hard register. | |
6ae08853 | 7703 | (define_split |
75540af0 | 7704 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7705 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
615158e2 JJ |
7706 | (match_operand:SI 2 "memory_operand" "")] |
7707 | UNSPEC_MOVSI_GOT))] | |
f607bc57 | 7708 | "DEFAULT_ABI == ABI_V4 |
b22b9b3e JL |
7709 | && flag_pic == 1 |
7710 | && (reload_in_progress || reload_completed)" | |
7711 | [(set (match_dup 0) (match_dup 2)) | |
615158e2 JJ |
7712 | (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] |
7713 | UNSPEC_MOVSI_GOT))] | |
b22b9b3e JL |
7714 | "") |
7715 | ||
1fd4e8c1 RK |
7716 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
7717 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
7718 | ;; and this is even supposed to be faster, but it is simpler not to get | |
7719 | ;; integers in the TOC. | |
7720 | (define_expand "movsi" | |
7721 | [(set (match_operand:SI 0 "general_operand" "") | |
7722 | (match_operand:SI 1 "any_operand" ""))] | |
7723 | "" | |
fb4d4348 | 7724 | "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }") |
1fd4e8c1 | 7725 | |
ee890fe2 SS |
7726 | (define_insn "movsi_low" |
7727 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
f585a356 | 7728 | (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
ee890fe2 SS |
7729 | (match_operand 2 "" ""))))] |
7730 | "TARGET_MACHO && ! TARGET_64BIT" | |
7731 | "{l|lwz} %0,lo16(%2)(%1)" | |
7732 | [(set_attr "type" "load") | |
7733 | (set_attr "length" "4")]) | |
7734 | ||
acad7ed3 | 7735 | (define_insn "*movsi_internal1" |
a004eb82 AH |
7736 | [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h") |
7737 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))] | |
19d5775a RK |
7738 | "gpc_reg_operand (operands[0], SImode) |
7739 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 7740 | "@ |
deb9225a | 7741 | mr %0,%1 |
b9442c72 | 7742 | {cal|la} %0,%a1 |
ca7f5001 RK |
7743 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7744 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 7745 | {lil|li} %0,%1 |
802a0058 | 7746 | {liu|lis} %0,%v1 |
beaec479 | 7747 | # |
aee86b38 | 7748 | {cal|la} %0,%a1 |
1fd4e8c1 | 7749 | mf%1 %0 |
5c23c401 | 7750 | mt%0 %1 |
e76e75bb | 7751 | mt%0 %1 |
a004eb82 | 7752 | mt%0 %1 |
e34eaae5 | 7753 | {cror 0,0,0|nop}" |
02ca7595 | 7754 | [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*") |
a004eb82 | 7755 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) |
1fd4e8c1 | 7756 | |
77fa0940 RK |
7757 | ;; Split a load of a large constant into the appropriate two-insn |
7758 | ;; sequence. | |
7759 | ||
7760 | (define_split | |
7761 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
7762 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 7763 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
7764 | && (INTVAL (operands[1]) & 0xffff) != 0" |
7765 | [(set (match_dup 0) | |
7766 | (match_dup 2)) | |
7767 | (set (match_dup 0) | |
7768 | (ior:SI (match_dup 0) | |
7769 | (match_dup 3)))] | |
7770 | " | |
af8cb5c5 DE |
7771 | { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2); |
7772 | ||
7773 | if (tem == operands[0]) | |
7774 | DONE; | |
7775 | else | |
7776 | FAIL; | |
77fa0940 RK |
7777 | }") |
7778 | ||
acad7ed3 | 7779 | (define_insn "*movsi_internal2" |
bb84cb12 DE |
7780 | [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") |
7781 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "0,r,r") | |
1fd4e8c1 | 7782 | (const_int 0))) |
bb84cb12 | 7783 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] |
4b8a63d6 | 7784 | "TARGET_32BIT" |
9ebbca7d | 7785 | "@ |
bb84cb12 | 7786 | {cmpi|cmpwi} %2,%0,0 |
9ebbca7d GK |
7787 | mr. %0,%1 |
7788 | #" | |
bb84cb12 DE |
7789 | [(set_attr "type" "cmp,compare,cmp") |
7790 | (set_attr "length" "4,4,8")]) | |
7791 | ||
9ebbca7d GK |
7792 | (define_split |
7793 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
7794 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") | |
7795 | (const_int 0))) | |
7796 | (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))] | |
4b8a63d6 | 7797 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
7798 | [(set (match_dup 0) (match_dup 1)) |
7799 | (set (match_dup 2) | |
7800 | (compare:CC (match_dup 0) | |
7801 | (const_int 0)))] | |
7802 | "") | |
bb84cb12 | 7803 | \f |
1fd4e8c1 RK |
7804 | (define_expand "movhi" |
7805 | [(set (match_operand:HI 0 "general_operand" "") | |
7806 | (match_operand:HI 1 "any_operand" ""))] | |
7807 | "" | |
fb4d4348 | 7808 | "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }") |
1fd4e8c1 | 7809 | |
e34eaae5 | 7810 | (define_insn "*movhi_internal" |
fb81d7ce RK |
7811 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7812 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7813 | "gpc_reg_operand (operands[0], HImode) |
7814 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 7815 | "@ |
deb9225a | 7816 | mr %0,%1 |
1fd4e8c1 RK |
7817 | lhz%U1%X1 %0,%1 |
7818 | sth%U0%X0 %1,%0 | |
19d5775a | 7819 | {lil|li} %0,%w1 |
1fd4e8c1 | 7820 | mf%1 %0 |
e76e75bb | 7821 | mt%0 %1 |
fb81d7ce | 7822 | mt%0 %1 |
e34eaae5 | 7823 | {cror 0,0,0|nop}" |
02ca7595 | 7824 | [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7825 | |
7826 | (define_expand "movqi" | |
7827 | [(set (match_operand:QI 0 "general_operand" "") | |
7828 | (match_operand:QI 1 "any_operand" ""))] | |
7829 | "" | |
fb4d4348 | 7830 | "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }") |
1fd4e8c1 | 7831 | |
e34eaae5 | 7832 | (define_insn "*movqi_internal" |
fb81d7ce RK |
7833 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7834 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7835 | "gpc_reg_operand (operands[0], QImode) |
7836 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 7837 | "@ |
deb9225a | 7838 | mr %0,%1 |
1fd4e8c1 RK |
7839 | lbz%U1%X1 %0,%1 |
7840 | stb%U0%X0 %1,%0 | |
19d5775a | 7841 | {lil|li} %0,%1 |
1fd4e8c1 | 7842 | mf%1 %0 |
e76e75bb | 7843 | mt%0 %1 |
fb81d7ce | 7844 | mt%0 %1 |
e34eaae5 | 7845 | {cror 0,0,0|nop}" |
02ca7595 | 7846 | [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7847 | \f |
7848 | ;; Here is how to move condition codes around. When we store CC data in | |
7849 | ;; an integer register or memory, we store just the high-order 4 bits. | |
7850 | ;; This lets us not shift in the most common case of CR0. | |
7851 | (define_expand "movcc" | |
7852 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
7853 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
7854 | "" | |
7855 | "") | |
7856 | ||
a65c591c | 7857 | (define_insn "*movcc_internal1" |
b54cf83a DE |
7858 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m") |
7859 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))] | |
1fd4e8c1 RK |
7860 | "register_operand (operands[0], CCmode) |
7861 | || register_operand (operands[1], CCmode)" | |
7862 | "@ | |
7863 | mcrf %0,%1 | |
7864 | mtcrf 128,%1 | |
ca7f5001 | 7865 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
2c4a9cff DE |
7866 | mfcr %0%Q1 |
7867 | mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 | |
deb9225a | 7868 | mr %0,%1 |
b54cf83a | 7869 | mf%1 %0 |
b991a865 GK |
7870 | mt%0 %1 |
7871 | mt%0 %1 | |
ca7f5001 RK |
7872 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7873 | {st%U0%U1|stw%U0%U1} %1,%0" | |
2c4a9cff DE |
7874 | [(set (attr "type") |
7875 | (cond [(eq_attr "alternative" "0") | |
7876 | (const_string "cr_logical") | |
7877 | (eq_attr "alternative" "1,2") | |
7878 | (const_string "mtcr") | |
7879 | (eq_attr "alternative" "5,7") | |
7880 | (const_string "integer") | |
7881 | (eq_attr "alternative" "6") | |
7882 | (const_string "mfjmpr") | |
7883 | (eq_attr "alternative" "8") | |
7884 | (const_string "mtjmpr") | |
7885 | (eq_attr "alternative" "9") | |
7886 | (const_string "load") | |
7887 | (eq_attr "alternative" "10") | |
7888 | (const_string "store") | |
7889 | (ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
7890 | (const_string "mfcrf") | |
7891 | ] | |
7892 | (const_string "mfcr"))) | |
b991a865 | 7893 | (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")]) |
1fd4e8c1 | 7894 | \f |
e52e05ca MM |
7895 | ;; For floating-point, we normally deal with the floating-point registers |
7896 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
7897 | ;; can produce floating-point values in fixed-point registers. Unless the | |
7898 | ;; value is a simple constant or already in memory, we deal with this by | |
7899 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
7900 | (define_expand "movsf" |
7901 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
7902 | (match_operand:SF 1 "any_operand" ""))] | |
7903 | "" | |
fb4d4348 | 7904 | "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") |
1fd4e8c1 | 7905 | |
1fd4e8c1 | 7906 | (define_split |
cd2b37d9 | 7907 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 7908 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 7909 | "reload_completed |
5ae4759c MM |
7910 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7911 | || (GET_CODE (operands[0]) == SUBREG | |
7912 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7913 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 7914 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
7915 | " |
7916 | { | |
7917 | long l; | |
7918 | REAL_VALUE_TYPE rv; | |
7919 | ||
7920 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7921 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 7922 | |
f99f88e0 DE |
7923 | if (! TARGET_POWERPC64) |
7924 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
7925 | else | |
7926 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 7927 | |
2496c7bd | 7928 | operands[3] = gen_int_mode (l, SImode); |
a260abc9 DE |
7929 | }") |
7930 | ||
c4c40373 | 7931 | (define_insn "*movsf_hardfloat" |
ae6669e7 DJ |
7932 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r") |
7933 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))] | |
d14a6d05 | 7934 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
7935 | || gpc_reg_operand (operands[1], SFmode)) |
7936 | && (TARGET_HARD_FLOAT && TARGET_FPRS)" | |
1fd4e8c1 | 7937 | "@ |
f99f88e0 DE |
7938 | mr %0,%1 |
7939 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7940 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
7941 | fmr %0,%1 |
7942 | lfs%U1%X1 %0,%1 | |
c4c40373 | 7943 | stfs%U0%X0 %1,%0 |
b991a865 GK |
7944 | mt%0 %1 |
7945 | mt%0 %1 | |
7946 | mf%1 %0 | |
e0740893 | 7947 | {cror 0,0,0|nop} |
c4c40373 MM |
7948 | # |
7949 | #" | |
ae6669e7 DJ |
7950 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*") |
7951 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7952 | |
c4c40373 | 7953 | (define_insn "*movsf_softfloat" |
dd0fbae2 MK |
7954 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h") |
7955 | (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))] | |
d14a6d05 | 7956 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
7957 | || gpc_reg_operand (operands[1], SFmode)) |
7958 | && (TARGET_SOFT_FLOAT || !TARGET_FPRS)" | |
d14a6d05 MM |
7959 | "@ |
7960 | mr %0,%1 | |
b991a865 GK |
7961 | mt%0 %1 |
7962 | mt%0 %1 | |
7963 | mf%1 %0 | |
d14a6d05 MM |
7964 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7965 | {st%U0%X0|stw%U0%X0} %1,%0 | |
7966 | {lil|li} %0,%1 | |
802a0058 | 7967 | {liu|lis} %0,%v1 |
aee86b38 | 7968 | {cal|la} %0,%a1 |
c4c40373 | 7969 | # |
dd0fbae2 MK |
7970 | # |
7971 | {cror 0,0,0|nop}" | |
7972 | [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*") | |
7973 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")]) | |
d14a6d05 | 7974 | |
1fd4e8c1 RK |
7975 | \f |
7976 | (define_expand "movdf" | |
7977 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
7978 | (match_operand:DF 1 "any_operand" ""))] | |
7979 | "" | |
fb4d4348 | 7980 | "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") |
1fd4e8c1 RK |
7981 | |
7982 | (define_split | |
cd2b37d9 | 7983 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 7984 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 7985 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7986 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7987 | || (GET_CODE (operands[0]) == SUBREG | |
7988 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7989 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7990 | [(set (match_dup 2) (match_dup 4)) |
7991 | (set (match_dup 3) (match_dup 1))] | |
7992 | " | |
7993 | { | |
5ae4759c | 7994 | int endian = (WORDS_BIG_ENDIAN == 0); |
5f59ecb7 DE |
7995 | HOST_WIDE_INT value = INTVAL (operands[1]); |
7996 | ||
5ae4759c MM |
7997 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7998 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
5f59ecb7 DE |
7999 | #if HOST_BITS_PER_WIDE_INT == 32 |
8000 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
8001 | #else | |
8002 | operands[4] = GEN_INT (value >> 32); | |
a65c591c | 8003 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
5f59ecb7 | 8004 | #endif |
c4c40373 MM |
8005 | }") |
8006 | ||
c4c40373 MM |
8007 | (define_split |
8008 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
8009 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 8010 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
8011 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
8012 | || (GET_CODE (operands[0]) == SUBREG | |
8013 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8014 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
8015 | [(set (match_dup 2) (match_dup 4)) |
8016 | (set (match_dup 3) (match_dup 5))] | |
8017 | " | |
8018 | { | |
5ae4759c | 8019 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
8020 | long l[2]; |
8021 | REAL_VALUE_TYPE rv; | |
8022 | ||
8023 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8024 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
8025 | ||
5ae4759c MM |
8026 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
8027 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
2496c7bd LB |
8028 | operands[4] = gen_int_mode (l[endian], SImode); |
8029 | operands[5] = gen_int_mode (l[1 - endian], SImode); | |
c4c40373 MM |
8030 | }") |
8031 | ||
efc08378 DE |
8032 | (define_split |
8033 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
685f3906 | 8034 | (match_operand:DF 1 "easy_fp_constant" ""))] |
a260abc9 | 8035 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
8036 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
8037 | || (GET_CODE (operands[0]) == SUBREG | |
8038 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
8039 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 8040 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 8041 | " |
a260abc9 DE |
8042 | { |
8043 | int endian = (WORDS_BIG_ENDIAN == 0); | |
8044 | long l[2]; | |
8045 | REAL_VALUE_TYPE rv; | |
4977bab6 | 8046 | #if HOST_BITS_PER_WIDE_INT >= 64 |
5b029315 | 8047 | HOST_WIDE_INT val; |
4977bab6 | 8048 | #endif |
a260abc9 DE |
8049 | |
8050 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
8051 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
8052 | ||
8053 | operands[2] = gen_lowpart (DImode, operands[0]); | |
8054 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
5b029315 | 8055 | #if HOST_BITS_PER_WIDE_INT >= 64 |
a2419b96 DE |
8056 | val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 |
8057 | | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); | |
5b029315 | 8058 | |
f5264b52 | 8059 | operands[3] = gen_int_mode (val, DImode); |
5b029315 | 8060 | #else |
a260abc9 | 8061 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); |
5b029315 | 8062 | #endif |
a260abc9 | 8063 | }") |
efc08378 | 8064 | |
4eae5fe1 | 8065 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 8066 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
8067 | ;; a non-offsettable memref, but also it is less efficient than loading |
8068 | ;; the constant into an FP register, since it will probably be used there. | |
8069 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
8070 | ;; of handling these non-offsettable values. | |
c4c40373 | 8071 | (define_insn "*movdf_hardfloat32" |
914a7297 DE |
8072 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") |
8073 | (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] | |
a3170dc6 | 8074 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
8075 | && (gpc_reg_operand (operands[0], DFmode) |
8076 | || gpc_reg_operand (operands[1], DFmode))" | |
e7113111 RK |
8077 | "* |
8078 | { | |
8079 | switch (which_alternative) | |
8080 | { | |
a260abc9 | 8081 | default: |
a6c2a102 | 8082 | abort (); |
e7113111 RK |
8083 | case 0: |
8084 | /* We normally copy the low-numbered register first. However, if | |
000034eb DE |
8085 | the first register operand 0 is the same as the second register |
8086 | of operand 1, we must copy in the opposite order. */ | |
e7113111 | 8087 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) |
deb9225a | 8088 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 8089 | else |
deb9225a | 8090 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 | 8091 | case 1: |
819e019c EC |
8092 | if (GET_CODE (operands[1]) == MEM |
8093 | && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0), | |
8094 | reload_completed || reload_in_progress) | |
8095 | || GET_CODE (XEXP (operands[1], 0)) == REG | |
8096 | || GET_CODE (XEXP (operands[1], 0)) == LO_SUM | |
69f51a21 | 8097 | || GET_CODE (XEXP (operands[1], 0)) == PRE_INC |
819e019c | 8098 | || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)) |
000034eb DE |
8099 | { |
8100 | /* If the low-address word is used in the address, we must load | |
8101 | it last. Otherwise, load it first. Note that we cannot have | |
8102 | auto-increment in that case since the address register is | |
8103 | known to be dead. */ | |
8104 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
8105 | operands[1], 0)) | |
8106 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
8107 | else | |
8108 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
8109 | } | |
e7113111 | 8110 | else |
000034eb DE |
8111 | { |
8112 | rtx addreg; | |
8113 | ||
000034eb DE |
8114 | addreg = find_addr_reg (XEXP (operands[1], 0)); |
8115 | if (refers_to_regno_p (REGNO (operands[0]), | |
8116 | REGNO (operands[0]) + 1, | |
8117 | operands[1], 0)) | |
8118 | { | |
8119 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); | |
2b97222d | 8120 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb | 8121 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
2b97222d | 8122 | return \"{lx|lwzx} %0,%1\"; |
000034eb DE |
8123 | } |
8124 | else | |
8125 | { | |
2b97222d | 8126 | output_asm_insn (\"{lx|lwzx} %0,%1\", operands); |
000034eb | 8127 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8128 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb DE |
8129 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8130 | return \"\"; | |
8131 | } | |
8132 | } | |
e7113111 | 8133 | case 2: |
819e019c EC |
8134 | if (GET_CODE (operands[0]) == MEM |
8135 | && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0), | |
8136 | reload_completed || reload_in_progress) | |
8137 | || GET_CODE (XEXP (operands[0], 0)) == REG | |
8138 | || GET_CODE (XEXP (operands[0], 0)) == LO_SUM | |
69f51a21 | 8139 | || GET_CODE (XEXP (operands[0], 0)) == PRE_INC |
819e019c | 8140 | || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)) |
000034eb DE |
8141 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
8142 | else | |
8143 | { | |
8144 | rtx addreg; | |
8145 | ||
000034eb | 8146 | addreg = find_addr_reg (XEXP (operands[0], 0)); |
2b97222d | 8147 | output_asm_insn (\"{stx|stwx} %1,%0\", operands); |
000034eb | 8148 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 8149 | output_asm_insn (\"{stx|stwx} %L1,%0\", operands); |
000034eb DE |
8150 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
8151 | return \"\"; | |
8152 | } | |
e7113111 | 8153 | case 3: |
914a7297 | 8154 | return \"fmr %0,%1\"; |
e7113111 | 8155 | case 4: |
914a7297 | 8156 | return \"lfd%U1%X1 %0,%1\"; |
e7113111 | 8157 | case 5: |
914a7297 | 8158 | return \"stfd%U0%X0 %1,%0\"; |
e7113111 | 8159 | case 6: |
c4c40373 | 8160 | case 7: |
c4c40373 | 8161 | case 8: |
914a7297 | 8162 | return \"#\"; |
e7113111 RK |
8163 | } |
8164 | }" | |
914a7297 DE |
8165 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*") |
8166 | (set_attr "length" "8,16,16,4,4,4,8,12,16")]) | |
51b8fc2c | 8167 | |
c4c40373 | 8168 | (define_insn "*movdf_softfloat32" |
1427100a DE |
8169 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
8170 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
7a2f7870 | 8171 | "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE) |
52d3af72 DE |
8172 | && (gpc_reg_operand (operands[0], DFmode) |
8173 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
8174 | "* |
8175 | { | |
8176 | switch (which_alternative) | |
8177 | { | |
a260abc9 | 8178 | default: |
a6c2a102 | 8179 | abort (); |
dc4f83ca MM |
8180 | case 0: |
8181 | /* We normally copy the low-numbered register first. However, if | |
8182 | the first register operand 0 is the same as the second register of | |
8183 | operand 1, we must copy in the opposite order. */ | |
8184 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8185 | return \"mr %L0,%L1\;mr %0,%1\"; | |
8186 | else | |
8187 | return \"mr %0,%1\;mr %L0,%L1\"; | |
8188 | case 1: | |
3cb999d8 DE |
8189 | /* If the low-address word is used in the address, we must load |
8190 | it last. Otherwise, load it first. Note that we cannot have | |
8191 | auto-increment in that case since the address register is | |
8192 | known to be dead. */ | |
dc4f83ca | 8193 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, |
3cb999d8 | 8194 | operands[1], 0)) |
dc4f83ca MM |
8195 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
8196 | else | |
8197 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
8198 | case 2: | |
8199 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
8200 | case 3: | |
c4c40373 MM |
8201 | case 4: |
8202 | case 5: | |
dc4f83ca MM |
8203 | return \"#\"; |
8204 | } | |
8205 | }" | |
c4c40373 MM |
8206 | [(set_attr "type" "*,load,store,*,*,*") |
8207 | (set_attr "length" "8,8,8,8,12,16")]) | |
dc4f83ca | 8208 | |
d2288d5d HP |
8209 | ; ld/std require word-aligned displacements -> 'Y' constraint. |
8210 | ; List Y->r and r->Y before r->r for reload. | |
c4c40373 | 8211 | (define_insn "*movdf_hardfloat64" |
ae6669e7 DJ |
8212 | [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r") |
8213 | (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))] | |
a3170dc6 | 8214 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
8215 | && (gpc_reg_operand (operands[0], DFmode) |
8216 | || gpc_reg_operand (operands[1], DFmode))" | |
51b8fc2c | 8217 | "@ |
96bb8ed3 | 8218 | std%U0%X0 %1,%0 |
3364872d FJ |
8219 | ld%U1%X1 %0,%1 |
8220 | mr %0,%1 | |
3d5570cb | 8221 | fmr %0,%1 |
f63184ac | 8222 | lfd%U1%X1 %0,%1 |
914a7297 DE |
8223 | stfd%U0%X0 %1,%0 |
8224 | mt%0 %1 | |
8225 | mf%1 %0 | |
e0740893 | 8226 | {cror 0,0,0|nop} |
914a7297 DE |
8227 | # |
8228 | # | |
8229 | #" | |
ae6669e7 DJ |
8230 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*") |
8231 | (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")]) | |
dc4f83ca | 8232 | |
c4c40373 | 8233 | (define_insn "*movdf_softfloat64" |
d2288d5d HP |
8234 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h") |
8235 | (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))] | |
a3170dc6 | 8236 | "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) |
52d3af72 DE |
8237 | && (gpc_reg_operand (operands[0], DFmode) |
8238 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca | 8239 | "@ |
d2288d5d HP |
8240 | ld%U1%X1 %0,%1 |
8241 | std%U0%X0 %1,%0 | |
dc4f83ca | 8242 | mr %0,%1 |
914a7297 DE |
8243 | mt%0 %1 |
8244 | mf%1 %0 | |
c4c40373 MM |
8245 | # |
8246 | # | |
e2d0915c | 8247 | # |
e0740893 | 8248 | {cror 0,0,0|nop}" |
d2288d5d | 8249 | [(set_attr "type" "load,store,*,*,*,*,*,*,*") |
e2d0915c | 8250 | (set_attr "length" "4,4,4,4,4,8,12,16,4")]) |
1fd4e8c1 | 8251 | \f |
06f4e019 DE |
8252 | (define_expand "movtf" |
8253 | [(set (match_operand:TF 0 "general_operand" "") | |
8254 | (match_operand:TF 1 "any_operand" ""))] | |
39e63627 GK |
8255 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8256 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8257 | "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }") |
8258 | ||
a9baceb1 GK |
8259 | ; It's important to list the o->f and f->o moves before f->f because |
8260 | ; otherwise reload, given m->f, will try to pick f->f and reload it, | |
112ccb83 | 8261 | ; which doesn't make progress. Likewise r->o<> must be before r->r. |
a9baceb1 | 8262 | (define_insn_and_split "*movtf_internal" |
112ccb83 GK |
8263 | [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,o<>,r") |
8264 | (match_operand:TF 1 "input_operand" "f,o,f,mGHF,r,r"))] | |
39e63627 GK |
8265 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8266 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 | |
06f4e019 DE |
8267 | && (gpc_reg_operand (operands[0], TFmode) |
8268 | || gpc_reg_operand (operands[1], TFmode))" | |
a9baceb1 | 8269 | "#" |
ecb62ae7 | 8270 | "&& reload_completed" |
a9baceb1 GK |
8271 | [(pc)] |
8272 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } | |
112ccb83 | 8273 | [(set_attr "length" "8,8,8,20,20,16")]) |
06f4e019 | 8274 | |
ecb62ae7 GK |
8275 | (define_expand "extenddftf2" |
8276 | [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
8277 | (float_extend:TF (match_operand:DF 1 "input_operand" ""))) | |
8278 | (use (match_dup 2))])] | |
39e63627 GK |
8279 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8280 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 8281 | { |
ecb62ae7 GK |
8282 | operands[2] = CONST0_RTX (DFmode); |
8283 | }) | |
06f4e019 | 8284 | |
ecb62ae7 GK |
8285 | (define_insn_and_split "*extenddftf2_internal" |
8286 | [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r") | |
8287 | (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF"))) | |
8288 | (use (match_operand:DF 2 "input_operand" "rf,m,f,n"))] | |
39e63627 GK |
8289 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8290 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
ecb62ae7 GK |
8291 | "#" |
8292 | "&& reload_completed" | |
8293 | [(pc)] | |
06f4e019 | 8294 | { |
ecb62ae7 GK |
8295 | const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; |
8296 | const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); | |
8297 | emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word), | |
8298 | operands[1]); | |
8299 | emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word), | |
8300 | operands[2]); | |
8301 | DONE; | |
6ae08853 | 8302 | }) |
ecb62ae7 GK |
8303 | |
8304 | (define_expand "extendsftf2" | |
8305 | [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
8306 | (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
8307 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
8308 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
8309 | { | |
8310 | rtx tmp = gen_reg_rtx (DFmode); | |
8311 | emit_insn (gen_extendsfdf2 (tmp, operands[1])); | |
8312 | emit_insn (gen_extenddftf2 (operands[0], tmp)); | |
8313 | DONE; | |
8314 | }) | |
06f4e019 DE |
8315 | |
8316 | (define_insn "trunctfdf2" | |
8317 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
8318 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
39e63627 GK |
8319 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8320 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8321 | "fadd %0,%1,%L1" |
8322 | [(set_attr "type" "fp") | |
ecb62ae7 | 8323 | (set_attr "length" "4")]) |
06f4e019 DE |
8324 | |
8325 | (define_insn_and_split "trunctfsf2" | |
8326 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
ea112fc4 DE |
8327 | (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f"))) |
8328 | (clobber (match_scratch:DF 2 "=f"))] | |
39e63627 GK |
8329 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8330 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 8331 | "#" |
ea112fc4 | 8332 | "&& reload_completed" |
06f4e019 DE |
8333 | [(set (match_dup 2) |
8334 | (float_truncate:DF (match_dup 1))) | |
8335 | (set (match_dup 0) | |
8336 | (float_truncate:SF (match_dup 2)))] | |
ea112fc4 | 8337 | "") |
06f4e019 | 8338 | |
0c90aa3c | 8339 | (define_expand "floatsitf2" |
ea112fc4 | 8340 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
0c90aa3c | 8341 | (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))] |
39e63627 GK |
8342 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8343 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
0c90aa3c GK |
8344 | { |
8345 | rtx tmp = gen_reg_rtx (DFmode); | |
8346 | expand_float (tmp, operands[1], false); | |
8347 | emit_insn (gen_extenddftf2 (operands[0], tmp)); | |
8348 | DONE; | |
8349 | }) | |
06f4e019 | 8350 | |
ecb62ae7 GK |
8351 | ; fadd, but rounding towards zero. |
8352 | ; This is probably not the optimal code sequence. | |
8353 | (define_insn "fix_trunc_helper" | |
8354 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
8355 | (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")] | |
8356 | UNSPEC_FIX_TRUNC_TF)) | |
8357 | (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))] | |
8358 | "TARGET_HARD_FLOAT && TARGET_FPRS" | |
8359 | "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2" | |
8360 | [(set_attr "type" "fp") | |
8361 | (set_attr "length" "20")]) | |
8362 | ||
0c90aa3c | 8363 | (define_expand "fix_trunctfsi2" |
ecb62ae7 GK |
8364 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
8365 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" ""))) | |
8366 | (clobber (match_dup 2)) | |
8367 | (clobber (match_dup 3)) | |
8368 | (clobber (match_dup 4)) | |
8369 | (clobber (match_dup 5))])] | |
8370 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
8371 | && (TARGET_POWER2 || TARGET_POWERPC) | |
8372 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
8373 | { | |
8374 | operands[2] = gen_reg_rtx (DFmode); | |
8375 | operands[3] = gen_reg_rtx (DFmode); | |
8376 | operands[4] = gen_reg_rtx (DImode); | |
8377 | operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
8378 | }) | |
8379 | ||
8380 | (define_insn_and_split "*fix_trunctfsi2_internal" | |
61c07d3c | 8381 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
ecb62ae7 GK |
8382 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f"))) |
8383 | (clobber (match_operand:DF 2 "gpc_reg_operand" "=f")) | |
8384 | (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f")) | |
8385 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f")) | |
8386 | (clobber (match_operand:DI 5 "memory_operand" "=o"))] | |
39e63627 GK |
8387 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8388 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
ecb62ae7 GK |
8389 | "#" |
8390 | "&& reload_completed" | |
8391 | [(pc)] | |
0c90aa3c | 8392 | { |
ecb62ae7 GK |
8393 | rtx lowword; |
8394 | emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3])); | |
8395 | ||
8396 | if (GET_CODE (operands[5]) != MEM) | |
8397 | abort(); | |
8398 | lowword = XEXP (operands[5], 0); | |
8399 | if (WORDS_BIG_ENDIAN) | |
8400 | lowword = plus_constant (lowword, 4); | |
8401 | ||
8402 | emit_insn (gen_fctiwz (operands[4], operands[2])); | |
8403 | emit_move_insn (operands[5], operands[4]); | |
8404 | emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword)); | |
0c90aa3c GK |
8405 | DONE; |
8406 | }) | |
06f4e019 DE |
8407 | |
8408 | (define_insn "negtf2" | |
8409 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8410 | (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
39e63627 GK |
8411 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8412 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8413 | "* |
8414 | { | |
8415 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8416 | return \"fneg %L0,%L1\;fneg %0,%1\"; | |
8417 | else | |
8418 | return \"fneg %0,%1\;fneg %L0,%L1\"; | |
8419 | }" | |
8420 | [(set_attr "type" "fp") | |
8421 | (set_attr "length" "8")]) | |
8422 | ||
1a402dc1 | 8423 | (define_expand "abstf2" |
06f4e019 DE |
8424 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
8425 | (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
39e63627 GK |
8426 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8427 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
1a402dc1 | 8428 | " |
06f4e019 | 8429 | { |
1a402dc1 AM |
8430 | rtx label = gen_label_rtx (); |
8431 | emit_insn (gen_abstf2_internal (operands[0], operands[1], label)); | |
8432 | emit_label (label); | |
8433 | DONE; | |
8434 | }") | |
06f4e019 | 8435 | |
1a402dc1 | 8436 | (define_expand "abstf2_internal" |
06f4e019 | 8437 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
1a402dc1 AM |
8438 | (match_operand:TF 1 "gpc_reg_operand" "f")) |
8439 | (set (match_dup 3) (match_dup 5)) | |
8440 | (set (match_dup 5) (abs:DF (match_dup 5))) | |
8441 | (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5))) | |
8442 | (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) | |
8443 | (label_ref (match_operand 2 "" "")) | |
8444 | (pc))) | |
8445 | (set (match_dup 6) (neg:DF (match_dup 6)))] | |
39e63627 GK |
8446 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8447 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
1a402dc1 | 8448 | " |
06f4e019 | 8449 | { |
1a402dc1 AM |
8450 | const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); |
8451 | const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; | |
8452 | operands[3] = gen_reg_rtx (DFmode); | |
8453 | operands[4] = gen_reg_rtx (CCFPmode); | |
8454 | operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word); | |
8455 | operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word); | |
8456 | }") | |
06f4e019 | 8457 | \f |
1fd4e8c1 RK |
8458 | ;; Next come the multi-word integer load and store and the load and store |
8459 | ;; multiple insns. | |
8460 | (define_expand "movdi" | |
8461 | [(set (match_operand:DI 0 "general_operand" "") | |
e6ca2c17 | 8462 | (match_operand:DI 1 "any_operand" ""))] |
1fd4e8c1 | 8463 | "" |
fb4d4348 | 8464 | "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }") |
1fd4e8c1 | 8465 | |
112ccb83 GK |
8466 | ; List r->r after r->"o<>", otherwise reload will try to reload a |
8467 | ; non-offsettable address by using r->r which won't make progress. | |
acad7ed3 | 8468 | (define_insn "*movdi_internal32" |
112ccb83 GK |
8469 | [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,f,f,m,r") |
8470 | (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))] | |
a260abc9 | 8471 | "! TARGET_POWERPC64 |
4e74d8ec MM |
8472 | && (gpc_reg_operand (operands[0], DImode) |
8473 | || gpc_reg_operand (operands[1], DImode))" | |
112ccb83 GK |
8474 | "@ |
8475 | # | |
8476 | # | |
8477 | # | |
8478 | fmr %0,%1 | |
8479 | lfd%U1%X1 %0,%1 | |
8480 | stfd%U0%X0 %1,%0 | |
8481 | #" | |
8482 | [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")]) | |
4e74d8ec MM |
8483 | |
8484 | (define_split | |
8485 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8486 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 8487 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
8488 | [(set (match_dup 2) (match_dup 4)) |
8489 | (set (match_dup 3) (match_dup 1))] | |
8490 | " | |
8491 | { | |
5f59ecb7 | 8492 | HOST_WIDE_INT value = INTVAL (operands[1]); |
bdaa0181 GK |
8493 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
8494 | DImode); | |
8495 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8496 | DImode); | |
75d39459 | 8497 | #if HOST_BITS_PER_WIDE_INT == 32 |
5f59ecb7 | 8498 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 | 8499 | #else |
5f59ecb7 | 8500 | operands[4] = GEN_INT (value >> 32); |
a65c591c | 8501 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
75d39459 | 8502 | #endif |
4e74d8ec MM |
8503 | }") |
8504 | ||
3a1f863f DE |
8505 | (define_split |
8506 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
8507 | (match_operand:DI 1 "input_operand" ""))] | |
6ae08853 | 8508 | "reload_completed && !TARGET_POWERPC64 |
3a1f863f | 8509 | && gpr_or_gpr_p (operands[0], operands[1])" |
a9baceb1 GK |
8510 | [(pc)] |
8511 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) | |
3a1f863f | 8512 | |
6fc19dc9 AM |
8513 | (define_split |
8514 | [(set (match_operand:TI 0 "gpc_reg_operand" "") | |
8515 | (match_operand:TI 1 "const_double_operand" ""))] | |
8516 | "TARGET_POWERPC64" | |
8517 | [(set (match_dup 2) (match_dup 4)) | |
8518 | (set (match_dup 3) (match_dup 5))] | |
8519 | " | |
8520 | { | |
8521 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, | |
8522 | TImode); | |
8523 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8524 | TImode); | |
8525 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
8526 | { | |
8527 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); | |
8528 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
8529 | } | |
8530 | else if (GET_CODE (operands[1]) == CONST_INT) | |
8531 | { | |
8532 | operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0)); | |
8533 | operands[5] = operands[1]; | |
8534 | } | |
8535 | else | |
8536 | FAIL; | |
8537 | }") | |
8538 | ||
acad7ed3 | 8539 | (define_insn "*movdi_internal64" |
fa0a2ae5 | 8540 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,??f,f,m,r,*h,*h") |
9615f239 | 8541 | (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 8542 | "TARGET_POWERPC64 |
4e74d8ec MM |
8543 | && (gpc_reg_operand (operands[0], DImode) |
8544 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 8545 | "@ |
3d5570cb RK |
8546 | mr %0,%1 |
8547 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8548 | std%U0%X0 %1,%0 |
3d5570cb | 8549 | li %0,%1 |
802a0058 | 8550 | lis %0,%v1 |
e6ca2c17 | 8551 | # |
aee86b38 | 8552 | {cal|la} %0,%a1 |
3d5570cb RK |
8553 | fmr %0,%1 |
8554 | lfd%U1%X1 %0,%1 | |
8555 | stfd%U0%X0 %1,%0 | |
8556 | mf%1 %0 | |
08075ead | 8557 | mt%0 %1 |
e34eaae5 | 8558 | {cror 0,0,0|nop}" |
02ca7595 | 8559 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*") |
e6ca2c17 DE |
8560 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
8561 | ||
5f59ecb7 | 8562 | ;; immediate value valid for a single instruction hiding in a const_double |
a260abc9 DE |
8563 | (define_insn "" |
8564 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
8565 | (match_operand:DI 1 "const_double_operand" "F"))] | |
5f59ecb7 DE |
8566 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
8567 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
a260abc9 DE |
8568 | && num_insns_constant (operands[1], DImode) == 1" |
8569 | "* | |
8570 | { | |
8571 | return ((unsigned HOST_WIDE_INT) | |
8572 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
8573 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
8574 | }") | |
8575 | ||
a260abc9 DE |
8576 | ;; Generate all one-bits and clear left or right. |
8577 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
8578 | (define_split | |
8579 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8580 | (match_operand:DI 1 "mask64_operand" ""))] | |
8581 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8582 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 8583 | (set (match_dup 0) |
a260abc9 DE |
8584 | (and:DI (rotate:DI (match_dup 0) |
8585 | (const_int 0)) | |
8586 | (match_dup 1)))] | |
8587 | "") | |
8588 | ||
8589 | ;; Split a load of a large constant into the appropriate five-instruction | |
8590 | ;; sequence. Handle anything in a constant number of insns. | |
8591 | ;; When non-easy constants can go in the TOC, this should use | |
8592 | ;; easy_fp_constant predicate. | |
8593 | (define_split | |
8594 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8595 | (match_operand:DI 1 "const_int_operand" ""))] |
8596 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8597 | [(set (match_dup 0) (match_dup 2)) | |
8598 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
e6ca2c17 | 8599 | " |
2bfcf297 DB |
8600 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8601 | ||
8602 | if (tem == operands[0]) | |
8603 | DONE; | |
e8d791dd | 8604 | else |
2bfcf297 | 8605 | FAIL; |
5f59ecb7 | 8606 | }") |
e6ca2c17 | 8607 | |
5f59ecb7 DE |
8608 | (define_split |
8609 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8610 | (match_operand:DI 1 "const_double_operand" ""))] |
8611 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8612 | [(set (match_dup 0) (match_dup 2)) | |
8613 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
5f59ecb7 | 8614 | " |
2bfcf297 DB |
8615 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8616 | ||
8617 | if (tem == operands[0]) | |
8618 | DONE; | |
8619 | else | |
8620 | FAIL; | |
e6ca2c17 | 8621 | }") |
08075ead | 8622 | |
acad7ed3 | 8623 | (define_insn "*movdi_internal2" |
bb84cb12 DE |
8624 | [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") |
8625 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "0,r,r") | |
08075ead | 8626 | (const_int 0))) |
bb84cb12 | 8627 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] |
683bdff7 | 8628 | "TARGET_64BIT" |
9ebbca7d | 8629 | "@ |
bb84cb12 | 8630 | cmpdi %2,%0,0 |
9ebbca7d GK |
8631 | mr. %0,%1 |
8632 | #" | |
bb84cb12 DE |
8633 | [(set_attr "type" "cmp,compare,cmp") |
8634 | (set_attr "length" "4,4,8")]) | |
acad7ed3 | 8635 | |
9ebbca7d GK |
8636 | (define_split |
8637 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
8638 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "") | |
8639 | (const_int 0))) | |
8640 | (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))] | |
8641 | "TARGET_POWERPC64 && reload_completed" | |
8642 | [(set (match_dup 0) (match_dup 1)) | |
8643 | (set (match_dup 2) | |
8644 | (compare:CC (match_dup 0) | |
8645 | (const_int 0)))] | |
8646 | "") | |
acad7ed3 | 8647 | \f |
1fd4e8c1 RK |
8648 | ;; TImode is similar, except that we usually want to compute the address into |
8649 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 8650 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
8651 | (define_expand "movti" |
8652 | [(parallel [(set (match_operand:TI 0 "general_operand" "") | |
8653 | (match_operand:TI 1 "general_operand" "")) | |
8654 | (clobber (scratch:SI))])] | |
3a1f863f | 8655 | "" |
fb4d4348 | 8656 | "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }") |
1fd4e8c1 RK |
8657 | |
8658 | ;; We say that MQ is clobbered in the last alternative because the first | |
8659 | ;; alternative would never get used otherwise since it would need a reload | |
8660 | ;; while the 2nd alternative would not. We put memory cases first so they | |
8661 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
8662 | ;; giving the SCRATCH mq. | |
3a1f863f | 8663 | |
a260abc9 | 8664 | (define_insn "*movti_power" |
e1469d0d | 8665 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") |
1fd4e8c1 RK |
8666 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) |
8667 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] | |
6ae08853 | 8668 | "TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 8669 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
8670 | "* |
8671 | { | |
8672 | switch (which_alternative) | |
8673 | { | |
dc4f83ca MM |
8674 | default: |
8675 | abort (); | |
8676 | ||
1fd4e8c1 | 8677 | case 0: |
3a1f863f DE |
8678 | if (TARGET_STRING) |
8679 | return \"{stsi|stswi} %1,%P0,16\"; | |
1fd4e8c1 | 8680 | case 1: |
1fd4e8c1 | 8681 | case 2: |
3a1f863f | 8682 | return \"#\"; |
1fd4e8c1 RK |
8683 | case 3: |
8684 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8685 | fall through to generating four loads. */ | |
e876481c DE |
8686 | if (TARGET_STRING |
8687 | && ! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 8688 | return \"{lsi|lswi} %0,%P1,16\"; |
82e41834 | 8689 | /* ... fall through ... */ |
1fd4e8c1 | 8690 | case 4: |
3a1f863f | 8691 | return \"#\"; |
1fd4e8c1 RK |
8692 | } |
8693 | }" | |
3a1f863f | 8694 | [(set_attr "type" "store,store,*,load,load")]) |
51b8fc2c | 8695 | |
a260abc9 | 8696 | (define_insn "*movti_string" |
112ccb83 | 8697 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r") |
27dc0551 | 8698 | (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))] |
3a1f863f | 8699 | "! TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
8700 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
8701 | "* | |
8702 | { | |
8703 | switch (which_alternative) | |
8704 | { | |
8705 | default: | |
8706 | abort (); | |
dc4f83ca | 8707 | case 0: |
3a1f863f DE |
8708 | if (TARGET_STRING) |
8709 | return \"{stsi|stswi} %1,%P0,16\"; | |
dc4f83ca | 8710 | case 1: |
cd1d3445 | 8711 | case 2: |
3a1f863f | 8712 | return \"#\"; |
cd1d3445 DE |
8713 | case 3: |
8714 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8715 | fall through to generating four loads. */ | |
6ae08853 | 8716 | if (TARGET_STRING |
3a1f863f | 8717 | && ! reg_overlap_mentioned_p (operands[0], operands[1])) |
cd1d3445 DE |
8718 | return \"{lsi|lswi} %0,%P1,16\"; |
8719 | /* ... fall through ... */ | |
8720 | case 4: | |
3a1f863f | 8721 | return \"#\"; |
dc4f83ca MM |
8722 | } |
8723 | }" | |
3a1f863f | 8724 | [(set_attr "type" "store,store,*,load,load")]) |
dc4f83ca | 8725 | |
a260abc9 | 8726 | (define_insn "*movti_ppc64" |
112ccb83 GK |
8727 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r") |
8728 | (match_operand:TI 1 "input_operand" "r,r,m"))] | |
51b8fc2c RK |
8729 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) |
8730 | || gpc_reg_operand (operands[1], TImode))" | |
112ccb83 | 8731 | "#" |
3a1f863f DE |
8732 | [(set_attr "type" "*,load,store")]) |
8733 | ||
8734 | (define_split | |
8735 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
8736 | (match_operand:TI 1 "input_operand" ""))] | |
a9baceb1 | 8737 | "reload_completed |
3a1f863f | 8738 | && gpr_or_gpr_p (operands[0], operands[1])" |
a9baceb1 GK |
8739 | [(pc)] |
8740 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) | |
1fd4e8c1 RK |
8741 | \f |
8742 | (define_expand "load_multiple" | |
2f622005 RK |
8743 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8744 | (match_operand:SI 1 "" "")) | |
8745 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8746 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8747 | " |
8748 | { | |
8749 | int regno; | |
8750 | int count; | |
792760b9 | 8751 | rtx op1; |
1fd4e8c1 RK |
8752 | int i; |
8753 | ||
8754 | /* Support only loading a constant number of fixed-point registers from | |
8755 | memory and only bother with this if more than two; the machine | |
8756 | doesn't support more than eight. */ | |
8757 | if (GET_CODE (operands[2]) != CONST_INT | |
8758 | || INTVAL (operands[2]) <= 2 | |
8759 | || INTVAL (operands[2]) > 8 | |
8760 | || GET_CODE (operands[1]) != MEM | |
8761 | || GET_CODE (operands[0]) != REG | |
8762 | || REGNO (operands[0]) >= 32) | |
8763 | FAIL; | |
8764 | ||
8765 | count = INTVAL (operands[2]); | |
8766 | regno = REGNO (operands[0]); | |
8767 | ||
39403d82 | 8768 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
792760b9 RK |
8769 | op1 = replace_equiv_address (operands[1], |
8770 | force_reg (SImode, XEXP (operands[1], 0))); | |
1fd4e8c1 RK |
8771 | |
8772 | for (i = 0; i < count; i++) | |
8773 | XVECEXP (operands[3], 0, i) | |
39403d82 | 8774 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
7ef788f0 | 8775 | adjust_address_nv (op1, SImode, i * 4)); |
1fd4e8c1 RK |
8776 | }") |
8777 | ||
9caa3eb2 | 8778 | (define_insn "*ldmsi8" |
1fd4e8c1 | 8779 | [(match_parallel 0 "load_multiple_operation" |
9caa3eb2 DE |
8780 | [(set (match_operand:SI 2 "gpc_reg_operand" "") |
8781 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8782 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8783 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8784 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8785 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8786 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8787 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8788 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8789 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8790 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8791 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
8792 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
8793 | (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
8794 | (set (match_operand:SI 9 "gpc_reg_operand" "") | |
8795 | (mem:SI (plus:SI (match_dup 1) (const_int 28))))])] | |
8796 | "TARGET_STRING && XVECLEN (operands[0], 0) == 8" | |
1fd4e8c1 | 8797 | "* |
9caa3eb2 DE |
8798 | { return rs6000_output_load_multiple (operands); }" |
8799 | [(set_attr "type" "load") | |
8800 | (set_attr "length" "32")]) | |
1fd4e8c1 | 8801 | |
9caa3eb2 DE |
8802 | (define_insn "*ldmsi7" |
8803 | [(match_parallel 0 "load_multiple_operation" | |
8804 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8805 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8806 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8807 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8808 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8809 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8810 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8811 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8812 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8813 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8814 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8815 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
8816 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
8817 | (mem:SI (plus:SI (match_dup 1) (const_int 24))))])] | |
8818 | "TARGET_STRING && XVECLEN (operands[0], 0) == 7" | |
8819 | "* | |
8820 | { return rs6000_output_load_multiple (operands); }" | |
8821 | [(set_attr "type" "load") | |
8822 | (set_attr "length" "32")]) | |
8823 | ||
8824 | (define_insn "*ldmsi6" | |
8825 | [(match_parallel 0 "load_multiple_operation" | |
8826 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8827 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8828 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8829 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8830 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8831 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8832 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8833 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8834 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8835 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8836 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8837 | (mem:SI (plus:SI (match_dup 1) (const_int 20))))])] | |
8838 | "TARGET_STRING && XVECLEN (operands[0], 0) == 6" | |
8839 | "* | |
8840 | { return rs6000_output_load_multiple (operands); }" | |
8841 | [(set_attr "type" "load") | |
8842 | (set_attr "length" "32")]) | |
8843 | ||
8844 | (define_insn "*ldmsi5" | |
8845 | [(match_parallel 0 "load_multiple_operation" | |
8846 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8847 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8848 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8849 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8850 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8851 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8852 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8853 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8854 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8855 | (mem:SI (plus:SI (match_dup 1) (const_int 16))))])] | |
8856 | "TARGET_STRING && XVECLEN (operands[0], 0) == 5" | |
8857 | "* | |
8858 | { return rs6000_output_load_multiple (operands); }" | |
8859 | [(set_attr "type" "load") | |
8860 | (set_attr "length" "32")]) | |
8861 | ||
8862 | (define_insn "*ldmsi4" | |
8863 | [(match_parallel 0 "load_multiple_operation" | |
8864 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8865 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8866 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8867 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8868 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8869 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8870 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8871 | (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] | |
8872 | "TARGET_STRING && XVECLEN (operands[0], 0) == 4" | |
8873 | "* | |
8874 | { return rs6000_output_load_multiple (operands); }" | |
8875 | [(set_attr "type" "load") | |
8876 | (set_attr "length" "32")]) | |
8877 | ||
8878 | (define_insn "*ldmsi3" | |
8879 | [(match_parallel 0 "load_multiple_operation" | |
8880 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8881 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8882 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8883 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8884 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8885 | (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] | |
8886 | "TARGET_STRING && XVECLEN (operands[0], 0) == 3" | |
8887 | "* | |
8888 | { return rs6000_output_load_multiple (operands); }" | |
b19003d8 | 8889 | [(set_attr "type" "load") |
e82ee4cc | 8890 | (set_attr "length" "32")]) |
b19003d8 | 8891 | |
1fd4e8c1 | 8892 | (define_expand "store_multiple" |
2f622005 RK |
8893 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8894 | (match_operand:SI 1 "" "")) | |
8895 | (clobber (scratch:SI)) | |
8896 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8897 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8898 | " |
8899 | { | |
8900 | int regno; | |
8901 | int count; | |
8902 | rtx to; | |
792760b9 | 8903 | rtx op0; |
1fd4e8c1 RK |
8904 | int i; |
8905 | ||
8906 | /* Support only storing a constant number of fixed-point registers to | |
8907 | memory and only bother with this if more than two; the machine | |
8908 | doesn't support more than eight. */ | |
8909 | if (GET_CODE (operands[2]) != CONST_INT | |
8910 | || INTVAL (operands[2]) <= 2 | |
8911 | || INTVAL (operands[2]) > 8 | |
8912 | || GET_CODE (operands[0]) != MEM | |
8913 | || GET_CODE (operands[1]) != REG | |
8914 | || REGNO (operands[1]) >= 32) | |
8915 | FAIL; | |
8916 | ||
8917 | count = INTVAL (operands[2]); | |
8918 | regno = REGNO (operands[1]); | |
8919 | ||
39403d82 | 8920 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 | 8921 | to = force_reg (SImode, XEXP (operands[0], 0)); |
792760b9 | 8922 | op0 = replace_equiv_address (operands[0], to); |
1fd4e8c1 RK |
8923 | |
8924 | XVECEXP (operands[3], 0, 0) | |
7ef788f0 | 8925 | = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]); |
39403d82 | 8926 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
c5c76735 | 8927 | gen_rtx_SCRATCH (SImode)); |
1fd4e8c1 RK |
8928 | |
8929 | for (i = 1; i < count; i++) | |
8930 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 8931 | = gen_rtx_SET (VOIDmode, |
7ef788f0 | 8932 | adjust_address_nv (op0, SImode, i * 4), |
c5c76735 | 8933 | gen_rtx_REG (SImode, regno + i)); |
1fd4e8c1 RK |
8934 | }") |
8935 | ||
9caa3eb2 | 8936 | (define_insn "*store_multiple_power" |
1fd4e8c1 RK |
8937 | [(match_parallel 0 "store_multiple_operation" |
8938 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 8939 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 8940 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 8941 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
8942 | "{stsi|stswi} %2,%P1,%O0" |
8943 | [(set_attr "type" "store")]) | |
d14a6d05 | 8944 | |
e46e3130 | 8945 | (define_insn "*stmsi8" |
d14a6d05 | 8946 | [(match_parallel 0 "store_multiple_operation" |
e46e3130 DJ |
8947 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
8948 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8949 | (clobber (match_scratch:SI 3 "X")) | |
8950 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8951 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8952 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8953 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8954 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8955 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8956 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8957 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
8958 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
8959 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
8960 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
8961 | (match_operand:SI 9 "gpc_reg_operand" "r")) | |
8962 | (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
8963 | (match_operand:SI 10 "gpc_reg_operand" "r"))])] | |
8964 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9" | |
8965 | "{stsi|stswi} %2,%1,%O0" | |
8966 | [(set_attr "type" "store")]) | |
8967 | ||
8968 | (define_insn "*stmsi7" | |
8969 | [(match_parallel 0 "store_multiple_operation" | |
8970 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8971 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8972 | (clobber (match_scratch:SI 3 "X")) | |
8973 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8974 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8975 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8976 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8977 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8978 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8979 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8980 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
8981 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
8982 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
8983 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
8984 | (match_operand:SI 9 "gpc_reg_operand" "r"))])] | |
8985 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8" | |
8986 | "{stsi|stswi} %2,%1,%O0" | |
8987 | [(set_attr "type" "store")]) | |
8988 | ||
8989 | (define_insn "*stmsi6" | |
8990 | [(match_parallel 0 "store_multiple_operation" | |
8991 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8992 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8993 | (clobber (match_scratch:SI 3 "X")) | |
8994 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8995 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8996 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8997 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8998 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8999 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9000 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9001 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
9002 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
9003 | (match_operand:SI 8 "gpc_reg_operand" "r"))])] | |
9004 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7" | |
9005 | "{stsi|stswi} %2,%1,%O0" | |
9006 | [(set_attr "type" "store")]) | |
9007 | ||
9008 | (define_insn "*stmsi5" | |
9009 | [(match_parallel 0 "store_multiple_operation" | |
9010 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9011 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9012 | (clobber (match_scratch:SI 3 "X")) | |
9013 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9014 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9015 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9016 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9017 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9018 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
9019 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
9020 | (match_operand:SI 7 "gpc_reg_operand" "r"))])] | |
9021 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6" | |
9022 | "{stsi|stswi} %2,%1,%O0" | |
9023 | [(set_attr "type" "store")]) | |
9024 | ||
9025 | (define_insn "*stmsi4" | |
9026 | [(match_parallel 0 "store_multiple_operation" | |
9027 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9028 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9029 | (clobber (match_scratch:SI 3 "X")) | |
9030 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9031 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9032 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9033 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
9034 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
9035 | (match_operand:SI 6 "gpc_reg_operand" "r"))])] | |
9036 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5" | |
b7ff3d82 DE |
9037 | "{stsi|stswi} %2,%1,%O0" |
9038 | [(set_attr "type" "store")]) | |
7e69e155 | 9039 | |
e46e3130 DJ |
9040 | (define_insn "*stmsi3" |
9041 | [(match_parallel 0 "store_multiple_operation" | |
9042 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
9043 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
9044 | (clobber (match_scratch:SI 3 "X")) | |
9045 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
9046 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
9047 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
9048 | (match_operand:SI 5 "gpc_reg_operand" "r"))])] | |
9049 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4" | |
9050 | "{stsi|stswi} %2,%1,%O0" | |
9051 | [(set_attr "type" "store")]) | |
7e69e155 | 9052 | \f |
fba73eb1 DE |
9053 | (define_expand "clrmemsi" |
9054 | [(parallel [(set (match_operand:BLK 0 "" "") | |
9055 | (const_int 0)) | |
9056 | (use (match_operand:SI 1 "" "")) | |
9057 | (use (match_operand:SI 2 "" ""))])] | |
9058 | "" | |
9059 | " | |
9060 | { | |
9061 | if (expand_block_clear (operands)) | |
9062 | DONE; | |
9063 | else | |
9064 | FAIL; | |
9065 | }") | |
9066 | ||
7e69e155 MM |
9067 | ;; String/block move insn. |
9068 | ;; Argument 0 is the destination | |
9069 | ;; Argument 1 is the source | |
9070 | ;; Argument 2 is the length | |
9071 | ;; Argument 3 is the alignment | |
9072 | ||
70128ad9 | 9073 | (define_expand "movmemsi" |
b6c9286a MM |
9074 | [(parallel [(set (match_operand:BLK 0 "" "") |
9075 | (match_operand:BLK 1 "" "")) | |
9076 | (use (match_operand:SI 2 "" "")) | |
9077 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
9078 | "" |
9079 | " | |
9080 | { | |
9081 | if (expand_block_move (operands)) | |
9082 | DONE; | |
9083 | else | |
9084 | FAIL; | |
9085 | }") | |
9086 | ||
9087 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
9088 | ;; register allocator doesn't have a clue about allocating 8 word registers. |
9089 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 9090 | (define_expand "movmemsi_8reg" |
b6c9286a MM |
9091 | [(parallel [(set (match_operand 0 "" "") |
9092 | (match_operand 1 "" "")) | |
9093 | (use (match_operand 2 "" "")) | |
9094 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
9095 | (clobber (reg:SI 5)) |
9096 | (clobber (reg:SI 6)) | |
9097 | (clobber (reg:SI 7)) | |
9098 | (clobber (reg:SI 8)) | |
9099 | (clobber (reg:SI 9)) | |
9100 | (clobber (reg:SI 10)) | |
9101 | (clobber (reg:SI 11)) | |
9102 | (clobber (reg:SI 12)) | |
3c67b673 | 9103 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9104 | "TARGET_STRING" |
9105 | "") | |
9106 | ||
9107 | (define_insn "" | |
52d3af72 DE |
9108 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9109 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9110 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9111 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9112 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
9113 | (clobber (reg:SI 6)) |
9114 | (clobber (reg:SI 7)) | |
9115 | (clobber (reg:SI 8)) | |
9116 | (clobber (reg:SI 9)) | |
9117 | (clobber (reg:SI 10)) | |
9118 | (clobber (reg:SI 11)) | |
9119 | (clobber (reg:SI 12)) | |
3c67b673 | 9120 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 | 9121 | "TARGET_STRING && TARGET_POWER |
f9562f27 DE |
9122 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
9123 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
9124 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
9125 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
9126 | && REGNO (operands[4]) == 5" |
9127 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9128 | [(set_attr "type" "load") |
9129 | (set_attr "length" "8")]) | |
7e69e155 MM |
9130 | |
9131 | (define_insn "" | |
52d3af72 DE |
9132 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9133 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9134 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9135 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9136 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
9137 | (clobber (reg:SI 6)) |
9138 | (clobber (reg:SI 7)) | |
9139 | (clobber (reg:SI 8)) | |
9140 | (clobber (reg:SI 9)) | |
9141 | (clobber (reg:SI 10)) | |
9142 | (clobber (reg:SI 11)) | |
9143 | (clobber (reg:SI 12)) | |
3c67b673 | 9144 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9145 | "TARGET_STRING && ! TARGET_POWER |
f9562f27 DE |
9146 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
9147 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
9148 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
9149 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
9150 | && REGNO (operands[4]) == 5" |
9151 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9152 | [(set_attr "type" "load") |
9153 | (set_attr "length" "8")]) | |
7e69e155 | 9154 | |
09a625f7 TR |
9155 | (define_insn "" |
9156 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9157 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9158 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9159 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9160 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9161 | (clobber (reg:SI 6)) | |
9162 | (clobber (reg:SI 7)) | |
9163 | (clobber (reg:SI 8)) | |
9164 | (clobber (reg:SI 9)) | |
9165 | (clobber (reg:SI 10)) | |
9166 | (clobber (reg:SI 11)) | |
9167 | (clobber (reg:SI 12)) | |
9168 | (clobber (match_scratch:SI 5 "X"))] | |
9169 | "TARGET_STRING && TARGET_POWERPC64 | |
9170 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) | |
9171 | || INTVAL (operands[2]) == 0) | |
9172 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) | |
9173 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
9174 | && REGNO (operands[4]) == 5" | |
9175 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9176 | [(set_attr "type" "load") | |
9177 | (set_attr "length" "8")]) | |
9178 | ||
7e69e155 | 9179 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the |
f9562f27 DE |
9180 | ;; register allocator doesn't have a clue about allocating 6 word registers. |
9181 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 9182 | (define_expand "movmemsi_6reg" |
b6c9286a MM |
9183 | [(parallel [(set (match_operand 0 "" "") |
9184 | (match_operand 1 "" "")) | |
9185 | (use (match_operand 2 "" "")) | |
9186 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9187 | (clobber (reg:SI 5)) |
9188 | (clobber (reg:SI 6)) | |
7e69e155 MM |
9189 | (clobber (reg:SI 7)) |
9190 | (clobber (reg:SI 8)) | |
9191 | (clobber (reg:SI 9)) | |
9192 | (clobber (reg:SI 10)) | |
3c67b673 | 9193 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9194 | "TARGET_STRING" |
9195 | "") | |
9196 | ||
9197 | (define_insn "" | |
52d3af72 DE |
9198 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9199 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9200 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9201 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9202 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9203 | (clobber (reg:SI 6)) |
9204 | (clobber (reg:SI 7)) | |
7e69e155 MM |
9205 | (clobber (reg:SI 8)) |
9206 | (clobber (reg:SI 9)) | |
9207 | (clobber (reg:SI 10)) | |
3c67b673 | 9208 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9209 | "TARGET_STRING && TARGET_POWER |
9210 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
f9562f27 DE |
9211 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
9212 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9213 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9214 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9215 | [(set_attr "type" "load") |
9216 | (set_attr "length" "8")]) | |
7e69e155 MM |
9217 | |
9218 | (define_insn "" | |
52d3af72 DE |
9219 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9220 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9221 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9222 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9223 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9224 | (clobber (reg:SI 6)) |
9225 | (clobber (reg:SI 7)) | |
7e69e155 MM |
9226 | (clobber (reg:SI 8)) |
9227 | (clobber (reg:SI 9)) | |
9228 | (clobber (reg:SI 10)) | |
3c67b673 | 9229 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9230 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9231 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 |
f9562f27 DE |
9232 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
9233 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9234 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9235 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9236 | [(set_attr "type" "load") |
9237 | (set_attr "length" "8")]) | |
7e69e155 | 9238 | |
09a625f7 TR |
9239 | (define_insn "" |
9240 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9241 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9242 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9243 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9244 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9245 | (clobber (reg:SI 6)) | |
9246 | (clobber (reg:SI 7)) | |
9247 | (clobber (reg:SI 8)) | |
9248 | (clobber (reg:SI 9)) | |
9249 | (clobber (reg:SI 10)) | |
9250 | (clobber (match_scratch:SI 5 "X"))] | |
9251 | "TARGET_STRING && TARGET_POWERPC64 | |
9252 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 | |
9253 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) | |
9254 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
9255 | && REGNO (operands[4]) == 5" | |
9256 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9257 | [(set_attr "type" "load") | |
9258 | (set_attr "length" "8")]) | |
9259 | ||
f9562f27 DE |
9260 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill |
9261 | ;; problems with TImode. | |
9262 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 9263 | (define_expand "movmemsi_4reg" |
b6c9286a MM |
9264 | [(parallel [(set (match_operand 0 "" "") |
9265 | (match_operand 1 "" "")) | |
9266 | (use (match_operand 2 "" "")) | |
9267 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
9268 | (clobber (reg:SI 5)) |
9269 | (clobber (reg:SI 6)) | |
9270 | (clobber (reg:SI 7)) | |
9271 | (clobber (reg:SI 8)) | |
3c67b673 | 9272 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
9273 | "TARGET_STRING" |
9274 | "") | |
9275 | ||
9276 | (define_insn "" | |
52d3af72 DE |
9277 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9278 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9279 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9280 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9281 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9282 | (clobber (reg:SI 6)) |
9283 | (clobber (reg:SI 7)) | |
9284 | (clobber (reg:SI 8)) | |
3c67b673 | 9285 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
9286 | "TARGET_STRING && TARGET_POWER |
9287 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
f9562f27 DE |
9288 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9289 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9290 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9291 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9292 | [(set_attr "type" "load") |
9293 | (set_attr "length" "8")]) | |
7e69e155 MM |
9294 | |
9295 | (define_insn "" | |
52d3af72 DE |
9296 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9297 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9298 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9299 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 9300 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
9301 | (clobber (reg:SI 6)) |
9302 | (clobber (reg:SI 7)) | |
9303 | (clobber (reg:SI 8)) | |
3c67b673 | 9304 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 9305 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9306 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 |
f9562f27 DE |
9307 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
9308 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9309 | && REGNO (operands[4]) == 5" | |
3c67b673 | 9310 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9311 | [(set_attr "type" "load") |
9312 | (set_attr "length" "8")]) | |
7e69e155 | 9313 | |
09a625f7 TR |
9314 | (define_insn "" |
9315 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9316 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9317 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9318 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9319 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) | |
9320 | (clobber (reg:SI 6)) | |
9321 | (clobber (reg:SI 7)) | |
9322 | (clobber (reg:SI 8)) | |
9323 | (clobber (match_scratch:SI 5 "X"))] | |
9324 | "TARGET_STRING && TARGET_POWERPC64 | |
9325 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
9326 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) | |
9327 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
9328 | && REGNO (operands[4]) == 5" | |
9329 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
9330 | [(set_attr "type" "load") | |
9331 | (set_attr "length" "8")]) | |
9332 | ||
7e69e155 | 9333 | ;; Move up to 8 bytes at a time. |
70128ad9 | 9334 | (define_expand "movmemsi_2reg" |
b6c9286a MM |
9335 | [(parallel [(set (match_operand 0 "" "") |
9336 | (match_operand 1 "" "")) | |
9337 | (use (match_operand 2 "" "")) | |
9338 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9339 | (clobber (match_scratch:DI 4 "")) |
9340 | (clobber (match_scratch:SI 5 ""))])] | |
f9562f27 | 9341 | "TARGET_STRING && ! TARGET_POWERPC64" |
7e69e155 MM |
9342 | "") |
9343 | ||
9344 | (define_insn "" | |
52d3af72 DE |
9345 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9346 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9347 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9348 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9349 | (clobber (match_scratch:DI 4 "=&r")) | |
9350 | (clobber (match_scratch:SI 5 "=q"))] | |
f9562f27 | 9351 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
3c67b673 RK |
9352 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
9353 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
9354 | [(set_attr "type" "load") |
9355 | (set_attr "length" "8")]) | |
7e69e155 MM |
9356 | |
9357 | (define_insn "" | |
52d3af72 DE |
9358 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9359 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9360 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9361 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9362 | (clobber (match_scratch:DI 4 "=&r")) | |
9363 | (clobber (match_scratch:SI 5 "X"))] | |
f9562f27 | 9364 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
7e69e155 | 9365 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
3c67b673 | 9366 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9367 | [(set_attr "type" "load") |
9368 | (set_attr "length" "8")]) | |
7e69e155 MM |
9369 | |
9370 | ;; Move up to 4 bytes at a time. | |
70128ad9 | 9371 | (define_expand "movmemsi_1reg" |
b6c9286a MM |
9372 | [(parallel [(set (match_operand 0 "" "") |
9373 | (match_operand 1 "" "")) | |
9374 | (use (match_operand 2 "" "")) | |
9375 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
9376 | (clobber (match_scratch:SI 4 "")) |
9377 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
9378 | "TARGET_STRING" |
9379 | "") | |
9380 | ||
9381 | (define_insn "" | |
52d3af72 DE |
9382 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9383 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9384 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9385 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9386 | (clobber (match_scratch:SI 4 "=&r")) | |
9387 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
9388 | "TARGET_STRING && TARGET_POWER |
9389 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9390 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9391 | [(set_attr "type" "load") |
9392 | (set_attr "length" "8")]) | |
7e69e155 MM |
9393 | |
9394 | (define_insn "" | |
52d3af72 DE |
9395 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
9396 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
9397 | (use (match_operand:SI 2 "immediate_operand" "i")) |
9398 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9399 | (clobber (match_scratch:SI 4 "=&r")) | |
9400 | (clobber (match_scratch:SI 5 "X"))] | |
0ad91047 | 9401 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 9402 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" |
09a625f7 TR |
9403 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
9404 | [(set_attr "type" "load") | |
9405 | (set_attr "length" "8")]) | |
9406 | ||
9407 | (define_insn "" | |
9408 | [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b")) | |
9409 | (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b"))) | |
9410 | (use (match_operand:SI 2 "immediate_operand" "i")) | |
9411 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
9412 | (clobber (match_scratch:SI 4 "=&r")) | |
9413 | (clobber (match_scratch:SI 5 "X"))] | |
9414 | "TARGET_STRING && TARGET_POWERPC64 | |
9415 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 9416 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
9417 | [(set_attr "type" "load") |
9418 | (set_attr "length" "8")]) | |
7e69e155 | 9419 | |
1fd4e8c1 | 9420 | \f |
7e69e155 | 9421 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
9422 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
9423 | ;; do cases where the increment is not the size of the object. | |
9424 | ;; | |
9425 | ;; In all these cases, we use operands 0 and 1 for the register being | |
9426 | ;; incremented because those are the operands that local-alloc will | |
9427 | ;; tie and these are the pair most likely to be tieable (and the ones | |
9428 | ;; that will benefit the most). | |
9429 | ||
38c1f2d7 | 9430 | (define_insn "*movdi_update1" |
51b8fc2c | 9431 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 9432 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
768070a0 | 9433 | (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))) |
51b8fc2c RK |
9434 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") |
9435 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9436 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9437 | "@ |
9438 | ldux %3,%0,%2 | |
9439 | ldu %3,%2(%0)" | |
b54cf83a | 9440 | [(set_attr "type" "load_ux,load_u")]) |
287f13ff | 9441 | |
2e6c9641 FJ |
9442 | (define_insn "movdi_<mode>_update" |
9443 | [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") | |
9444 | (match_operand:P 2 "reg_or_aligned_short_operand" "r,I"))) | |
51b8fc2c | 9445 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) |
2e6c9641 FJ |
9446 | (set (match_operand:P 0 "gpc_reg_operand" "=b,b") |
9447 | (plus:P (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 9448 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
9449 | "@ |
9450 | stdux %3,%0,%2 | |
b7ff3d82 | 9451 | stdu %3,%2(%0)" |
b54cf83a | 9452 | [(set_attr "type" "store_ux,store_u")]) |
51b8fc2c | 9453 | |
38c1f2d7 | 9454 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
9455 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
9456 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9457 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9458 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9459 | (plus:SI (match_dup 1) (match_dup 2)))] |
f7b3ab8a | 9460 | "TARGET_UPDATE" |
1fd4e8c1 | 9461 | "@ |
ca7f5001 RK |
9462 | {lux|lwzux} %3,%0,%2 |
9463 | {lu|lwzu} %3,%2(%0)" | |
b54cf83a DE |
9464 | [(set_attr "type" "load_ux,load_u")]) |
9465 | ||
9466 | (define_insn "*movsi_update2" | |
9467 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
9468 | (sign_extend:DI | |
9469 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
9470 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
9471 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
9472 | (plus:DI (match_dup 1) (match_dup 2)))] | |
9473 | "TARGET_POWERPC64" | |
9474 | "lwaux %3,%0,%2" | |
9475 | [(set_attr "type" "load_ext_ux")]) | |
1fd4e8c1 | 9476 | |
4697a36c | 9477 | (define_insn "movsi_update" |
cd2b37d9 | 9478 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9479 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9480 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
9481 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9482 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9483 | "TARGET_UPDATE" |
1fd4e8c1 | 9484 | "@ |
ca7f5001 | 9485 | {stux|stwux} %3,%0,%2 |
b7ff3d82 | 9486 | {stu|stwu} %3,%2(%0)" |
b54cf83a | 9487 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9488 | |
b54cf83a | 9489 | (define_insn "*movhi_update1" |
cd2b37d9 RK |
9490 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
9491 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9492 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9493 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9494 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9495 | "TARGET_UPDATE" |
1fd4e8c1 | 9496 | "@ |
5f243543 RK |
9497 | lhzux %3,%0,%2 |
9498 | lhzu %3,%2(%0)" | |
b54cf83a | 9499 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9500 | |
38c1f2d7 | 9501 | (define_insn "*movhi_update2" |
cd2b37d9 | 9502 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9503 | (zero_extend:SI |
cd2b37d9 | 9504 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9505 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9506 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9507 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9508 | "TARGET_UPDATE" |
1fd4e8c1 | 9509 | "@ |
5f243543 RK |
9510 | lhzux %3,%0,%2 |
9511 | lhzu %3,%2(%0)" | |
b54cf83a | 9512 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9513 | |
38c1f2d7 | 9514 | (define_insn "*movhi_update3" |
cd2b37d9 | 9515 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9516 | (sign_extend:SI |
cd2b37d9 | 9517 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9518 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9519 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9520 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9521 | "TARGET_UPDATE" |
1fd4e8c1 | 9522 | "@ |
5f243543 RK |
9523 | lhaux %3,%0,%2 |
9524 | lhau %3,%2(%0)" | |
b54cf83a | 9525 | [(set_attr "type" "load_ext_ux,load_ext_u")]) |
1fd4e8c1 | 9526 | |
38c1f2d7 | 9527 | (define_insn "*movhi_update4" |
cd2b37d9 | 9528 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9529 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9530 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
9531 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9532 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9533 | "TARGET_UPDATE" |
1fd4e8c1 | 9534 | "@ |
5f243543 | 9535 | sthux %3,%0,%2 |
b7ff3d82 | 9536 | sthu %3,%2(%0)" |
b54cf83a | 9537 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9538 | |
38c1f2d7 | 9539 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
9540 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
9541 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9542 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9543 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9544 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9545 | "TARGET_UPDATE" |
1fd4e8c1 | 9546 | "@ |
5f243543 RK |
9547 | lbzux %3,%0,%2 |
9548 | lbzu %3,%2(%0)" | |
b54cf83a | 9549 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9550 | |
38c1f2d7 | 9551 | (define_insn "*movqi_update2" |
cd2b37d9 | 9552 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9553 | (zero_extend:SI |
cd2b37d9 | 9554 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9555 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9556 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9557 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9558 | "TARGET_UPDATE" |
1fd4e8c1 | 9559 | "@ |
5f243543 RK |
9560 | lbzux %3,%0,%2 |
9561 | lbzu %3,%2(%0)" | |
b54cf83a | 9562 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9563 | |
38c1f2d7 | 9564 | (define_insn "*movqi_update3" |
cd2b37d9 | 9565 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9566 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9567 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
9568 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9569 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9570 | "TARGET_UPDATE" |
1fd4e8c1 | 9571 | "@ |
5f243543 | 9572 | stbux %3,%0,%2 |
b7ff3d82 | 9573 | stbu %3,%2(%0)" |
b54cf83a | 9574 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9575 | |
38c1f2d7 | 9576 | (define_insn "*movsf_update1" |
cd2b37d9 | 9577 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 9578 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9579 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9580 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9581 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9582 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9583 | "@ |
5f243543 RK |
9584 | lfsux %3,%0,%2 |
9585 | lfsu %3,%2(%0)" | |
b54cf83a | 9586 | [(set_attr "type" "fpload_ux,fpload_u")]) |
1fd4e8c1 | 9587 | |
38c1f2d7 | 9588 | (define_insn "*movsf_update2" |
cd2b37d9 | 9589 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9590 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9591 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
9592 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9593 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9594 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9595 | "@ |
85fff2f3 | 9596 | stfsux %3,%0,%2 |
b7ff3d82 | 9597 | stfsu %3,%2(%0)" |
b54cf83a | 9598 | [(set_attr "type" "fpstore_ux,fpstore_u")]) |
1fd4e8c1 | 9599 | |
38c1f2d7 MM |
9600 | (define_insn "*movsf_update3" |
9601 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
9602 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9603 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
9604 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9605 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 9606 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
9607 | "@ |
9608 | {lux|lwzux} %3,%0,%2 | |
9609 | {lu|lwzu} %3,%2(%0)" | |
b54cf83a | 9610 | [(set_attr "type" "load_ux,load_u")]) |
38c1f2d7 MM |
9611 | |
9612 | (define_insn "*movsf_update4" | |
9613 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9614 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
9615 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
9616 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9617 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 9618 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
9619 | "@ |
9620 | {stux|stwux} %3,%0,%2 | |
9621 | {stu|stwu} %3,%2(%0)" | |
b54cf83a | 9622 | [(set_attr "type" "store_ux,store_u")]) |
38c1f2d7 MM |
9623 | |
9624 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
9625 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
9626 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9627 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9628 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9629 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9630 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9631 | "@ |
5f243543 RK |
9632 | lfdux %3,%0,%2 |
9633 | lfdu %3,%2(%0)" | |
b54cf83a | 9634 | [(set_attr "type" "fpload_ux,fpload_u")]) |
1fd4e8c1 | 9635 | |
38c1f2d7 | 9636 | (define_insn "*movdf_update2" |
cd2b37d9 | 9637 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9638 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9639 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
9640 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9641 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9642 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9643 | "@ |
5f243543 | 9644 | stfdux %3,%0,%2 |
b7ff3d82 | 9645 | stfdu %3,%2(%0)" |
b54cf83a | 9646 | [(set_attr "type" "fpstore_ux,fpstore_u")]) |
4c70a4f3 RK |
9647 | |
9648 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
9649 | ||
90f81f99 AP |
9650 | (define_insn "*lfq_power2" |
9651 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
9652 | (match_operand:TF 1 "memory_operand" ""))] | |
9653 | "TARGET_POWER2 | |
9654 | && TARGET_HARD_FLOAT && TARGET_FPRS" | |
9655 | "lfq%U1%X1 %0,%1") | |
9656 | ||
9657 | (define_peephole2 | |
9658 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4c70a4f3 | 9659 | (match_operand:DF 1 "memory_operand" "")) |
90f81f99 | 9660 | (set (match_operand:DF 2 "gpc_reg_operand" "") |
4c70a4f3 RK |
9661 | (match_operand:DF 3 "memory_operand" ""))] |
9662 | "TARGET_POWER2 | |
a3170dc6 | 9663 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 | 9664 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
90f81f99 AP |
9665 | && mems_ok_for_quad_peep (operands[1], operands[3])" |
9666 | [(set (match_dup 0) | |
9667 | (match_dup 1))] | |
9668 | "operands[1] = widen_memory_access (operands[1], TFmode, 0); | |
9669 | operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));") | |
4c70a4f3 | 9670 | |
90f81f99 AP |
9671 | (define_insn "*stfq_power2" |
9672 | [(set (match_operand:TF 0 "memory_operand" "") | |
9673 | (match_operand:TF 1 "gpc_reg_operand" "f"))] | |
9674 | "TARGET_POWER2 | |
9675 | && TARGET_HARD_FLOAT && TARGET_FPRS" | |
9676 | "stfq%U0%X0 %1,%0") | |
9677 | ||
9678 | ||
9679 | (define_peephole2 | |
4c70a4f3 | 9680 | [(set (match_operand:DF 0 "memory_operand" "") |
90f81f99 | 9681 | (match_operand:DF 1 "gpc_reg_operand" "")) |
4c70a4f3 | 9682 | (set (match_operand:DF 2 "memory_operand" "") |
90f81f99 | 9683 | (match_operand:DF 3 "gpc_reg_operand" ""))] |
4c70a4f3 | 9684 | "TARGET_POWER2 |
a3170dc6 | 9685 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 | 9686 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
90f81f99 AP |
9687 | && mems_ok_for_quad_peep (operands[0], operands[2])" |
9688 | [(set (match_dup 0) | |
9689 | (match_dup 1))] | |
9690 | "operands[0] = widen_memory_access (operands[0], TFmode, 0); | |
9691 | operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));") | |
1fd4e8c1 | 9692 | \f |
c4501e62 JJ |
9693 | ;; TLS support. |
9694 | ||
9695 | ;; "b" output constraint here and on tls_ld to support tls linker optimization. | |
9696 | (define_insn "tls_gd_32" | |
b150f4f3 DE |
9697 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9698 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9699 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9700 | UNSPEC_TLSGD))] | |
9701 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9702 | "addi %0,%1,%2@got@tlsgd") | |
9703 | ||
9704 | (define_insn "tls_gd_64" | |
b150f4f3 DE |
9705 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9706 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9707 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9708 | UNSPEC_TLSGD))] | |
9709 | "HAVE_AS_TLS && TARGET_64BIT" | |
9710 | "addi %0,%1,%2@got@tlsgd") | |
9711 | ||
9712 | (define_insn "tls_ld_32" | |
b150f4f3 DE |
9713 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9714 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")] | |
c4501e62 JJ |
9715 | UNSPEC_TLSLD))] |
9716 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9717 | "addi %0,%1,%&@got@tlsld") | |
9718 | ||
9719 | (define_insn "tls_ld_64" | |
b150f4f3 DE |
9720 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9721 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")] | |
c4501e62 JJ |
9722 | UNSPEC_TLSLD))] |
9723 | "HAVE_AS_TLS && TARGET_64BIT" | |
9724 | "addi %0,%1,%&@got@tlsld") | |
9725 | ||
9726 | (define_insn "tls_dtprel_32" | |
b150f4f3 DE |
9727 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9728 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9729 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9730 | UNSPEC_TLSDTPREL))] | |
9731 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9732 | "addi %0,%1,%2@dtprel") | |
9733 | ||
9734 | (define_insn "tls_dtprel_64" | |
b150f4f3 DE |
9735 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9736 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9737 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9738 | UNSPEC_TLSDTPREL))] | |
9739 | "HAVE_AS_TLS && TARGET_64BIT" | |
9740 | "addi %0,%1,%2@dtprel") | |
9741 | ||
9742 | (define_insn "tls_dtprel_ha_32" | |
b150f4f3 DE |
9743 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9744 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9745 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9746 | UNSPEC_TLSDTPRELHA))] | |
9747 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9748 | "addis %0,%1,%2@dtprel@ha") | |
9749 | ||
9750 | (define_insn "tls_dtprel_ha_64" | |
b150f4f3 DE |
9751 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9752 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9753 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9754 | UNSPEC_TLSDTPRELHA))] | |
9755 | "HAVE_AS_TLS && TARGET_64BIT" | |
9756 | "addis %0,%1,%2@dtprel@ha") | |
9757 | ||
9758 | (define_insn "tls_dtprel_lo_32" | |
b150f4f3 DE |
9759 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9760 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9761 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9762 | UNSPEC_TLSDTPRELLO))] | |
9763 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9764 | "addi %0,%1,%2@dtprel@l") | |
9765 | ||
9766 | (define_insn "tls_dtprel_lo_64" | |
b150f4f3 DE |
9767 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9768 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9769 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9770 | UNSPEC_TLSDTPRELLO))] | |
9771 | "HAVE_AS_TLS && TARGET_64BIT" | |
9772 | "addi %0,%1,%2@dtprel@l") | |
9773 | ||
9774 | (define_insn "tls_got_dtprel_32" | |
b150f4f3 DE |
9775 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9776 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9777 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9778 | UNSPEC_TLSGOTDTPREL))] | |
9779 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9780 | "lwz %0,%2@got@dtprel(%1)") | |
9781 | ||
9782 | (define_insn "tls_got_dtprel_64" | |
b150f4f3 DE |
9783 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9784 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9785 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9786 | UNSPEC_TLSGOTDTPREL))] | |
9787 | "HAVE_AS_TLS && TARGET_64BIT" | |
9788 | "ld %0,%2@got@dtprel(%1)") | |
9789 | ||
9790 | (define_insn "tls_tprel_32" | |
b150f4f3 DE |
9791 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9792 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9793 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9794 | UNSPEC_TLSTPREL))] | |
9795 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9796 | "addi %0,%1,%2@tprel") | |
9797 | ||
9798 | (define_insn "tls_tprel_64" | |
b150f4f3 DE |
9799 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9800 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9801 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9802 | UNSPEC_TLSTPREL))] | |
9803 | "HAVE_AS_TLS && TARGET_64BIT" | |
9804 | "addi %0,%1,%2@tprel") | |
9805 | ||
9806 | (define_insn "tls_tprel_ha_32" | |
b150f4f3 DE |
9807 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9808 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9809 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9810 | UNSPEC_TLSTPRELHA))] | |
9811 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9812 | "addis %0,%1,%2@tprel@ha") | |
9813 | ||
9814 | (define_insn "tls_tprel_ha_64" | |
b150f4f3 DE |
9815 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9816 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9817 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9818 | UNSPEC_TLSTPRELHA))] | |
9819 | "HAVE_AS_TLS && TARGET_64BIT" | |
9820 | "addis %0,%1,%2@tprel@ha") | |
9821 | ||
9822 | (define_insn "tls_tprel_lo_32" | |
b150f4f3 DE |
9823 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9824 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9825 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9826 | UNSPEC_TLSTPRELLO))] | |
9827 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9828 | "addi %0,%1,%2@tprel@l") | |
9829 | ||
9830 | (define_insn "tls_tprel_lo_64" | |
b150f4f3 DE |
9831 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9832 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9833 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9834 | UNSPEC_TLSTPRELLO))] | |
9835 | "HAVE_AS_TLS && TARGET_64BIT" | |
9836 | "addi %0,%1,%2@tprel@l") | |
9837 | ||
c1207243 | 9838 | ;; "b" output constraint here and on tls_tls input to support linker tls |
c4501e62 JJ |
9839 | ;; optimization. The linker may edit the instructions emitted by a |
9840 | ;; tls_got_tprel/tls_tls pair to addis,addi. | |
9841 | (define_insn "tls_got_tprel_32" | |
b150f4f3 DE |
9842 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9843 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9844 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9845 | UNSPEC_TLSGOTTPREL))] | |
9846 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9847 | "lwz %0,%2@got@tprel(%1)") | |
9848 | ||
9849 | (define_insn "tls_got_tprel_64" | |
b150f4f3 DE |
9850 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9851 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9852 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9853 | UNSPEC_TLSGOTTPREL))] | |
9854 | "HAVE_AS_TLS && TARGET_64BIT" | |
9855 | "ld %0,%2@got@tprel(%1)") | |
9856 | ||
9857 | (define_insn "tls_tls_32" | |
b150f4f3 DE |
9858 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9859 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9860 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9861 | UNSPEC_TLSTLS))] | |
9862 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9863 | "add %0,%1,%2@tls") | |
9864 | ||
9865 | (define_insn "tls_tls_64" | |
b150f4f3 DE |
9866 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9867 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9868 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9869 | UNSPEC_TLSTLS))] | |
9870 | "HAVE_AS_TLS && TARGET_64BIT" | |
9871 | "add %0,%1,%2@tls") | |
9872 | \f | |
1fd4e8c1 RK |
9873 | ;; Next come insns related to the calling sequence. |
9874 | ;; | |
9875 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 9876 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
9877 | |
9878 | (define_expand "allocate_stack" | |
52d3af72 | 9879 | [(set (match_operand 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
9880 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) |
9881 | (set (reg 1) | |
9882 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
9883 | "" |
9884 | " | |
4697a36c | 9885 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 9886 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 9887 | rtx neg_op0; |
1fd4e8c1 RK |
9888 | |
9889 | emit_move_insn (chain, stack_bot); | |
4697a36c | 9890 | |
a157febd GK |
9891 | /* Check stack bounds if necessary. */ |
9892 | if (current_function_limit_stack) | |
9893 | { | |
9894 | rtx available; | |
6ae08853 | 9895 | available = expand_binop (Pmode, sub_optab, |
a157febd GK |
9896 | stack_pointer_rtx, stack_limit_rtx, |
9897 | NULL_RTX, 1, OPTAB_WIDEN); | |
9898 | emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); | |
9899 | } | |
9900 | ||
e9a25f70 JL |
9901 | if (GET_CODE (operands[1]) != CONST_INT |
9902 | || INTVAL (operands[1]) < -32767 | |
9903 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
9904 | { |
9905 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 9906 | if (TARGET_32BIT) |
e9a25f70 | 9907 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 9908 | else |
e9a25f70 | 9909 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
9910 | } |
9911 | else | |
e9a25f70 | 9912 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 9913 | |
38c1f2d7 | 9914 | if (TARGET_UPDATE) |
2e6c9641 | 9915 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update)) |
38c1f2d7 | 9916 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); |
4697a36c | 9917 | |
38c1f2d7 MM |
9918 | else |
9919 | { | |
9920 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
9921 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 9922 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 9923 | } |
e9a25f70 JL |
9924 | |
9925 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
9926 | DONE; |
9927 | }") | |
59257ff7 RK |
9928 | |
9929 | ;; These patterns say how to save and restore the stack pointer. We need not | |
9930 | ;; save the stack pointer at function level since we are careful to | |
9931 | ;; preserve the backchain. At block level, we have to restore the backchain | |
9932 | ;; when we restore the stack pointer. | |
9933 | ;; | |
9934 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
9935 | ;; backchain and restore both. Note that in the nonlocal case, the | |
9936 | ;; save area is a memory location. | |
9937 | ||
9938 | (define_expand "save_stack_function" | |
ff381587 MM |
9939 | [(match_operand 0 "any_operand" "") |
9940 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9941 | "" |
ff381587 | 9942 | "DONE;") |
59257ff7 RK |
9943 | |
9944 | (define_expand "restore_stack_function" | |
ff381587 MM |
9945 | [(match_operand 0 "any_operand" "") |
9946 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9947 | "" |
ff381587 | 9948 | "DONE;") |
59257ff7 RK |
9949 | |
9950 | (define_expand "restore_stack_block" | |
dfdfa60f DE |
9951 | [(use (match_operand 0 "register_operand" "")) |
9952 | (set (match_dup 2) (match_dup 3)) | |
a260abc9 | 9953 | (set (match_dup 0) (match_operand 1 "register_operand" "")) |
dfdfa60f | 9954 | (set (match_dup 3) (match_dup 2))] |
59257ff7 RK |
9955 | "" |
9956 | " | |
dfdfa60f DE |
9957 | { |
9958 | operands[2] = gen_reg_rtx (Pmode); | |
39403d82 | 9959 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); |
dfdfa60f | 9960 | }") |
59257ff7 RK |
9961 | |
9962 | (define_expand "save_stack_nonlocal" | |
a260abc9 DE |
9963 | [(match_operand 0 "memory_operand" "") |
9964 | (match_operand 1 "register_operand" "")] | |
59257ff7 RK |
9965 | "" |
9966 | " | |
9967 | { | |
a260abc9 | 9968 | rtx temp = gen_reg_rtx (Pmode); |
11b25716 | 9969 | int units_per_word = (TARGET_32BIT) ? 4 : 8; |
59257ff7 RK |
9970 | |
9971 | /* Copy the backchain to the first word, sp to the second. */ | |
39403d82 | 9972 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
39e453d7 DE |
9973 | emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp); |
9974 | emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word), | |
a260abc9 | 9975 | operands[1]); |
59257ff7 RK |
9976 | DONE; |
9977 | }") | |
7e69e155 | 9978 | |
59257ff7 | 9979 | (define_expand "restore_stack_nonlocal" |
a260abc9 DE |
9980 | [(match_operand 0 "register_operand" "") |
9981 | (match_operand 1 "memory_operand" "")] | |
59257ff7 RK |
9982 | "" |
9983 | " | |
9984 | { | |
a260abc9 | 9985 | rtx temp = gen_reg_rtx (Pmode); |
11b25716 | 9986 | int units_per_word = (TARGET_32BIT) ? 4 : 8; |
59257ff7 RK |
9987 | |
9988 | /* Restore the backchain from the first word, sp from the second. */ | |
a260abc9 | 9989 | emit_move_insn (temp, |
39e453d7 | 9990 | adjust_address_nv (operands[1], Pmode, 0)); |
a260abc9 | 9991 | emit_move_insn (operands[0], |
39e453d7 | 9992 | adjust_address_nv (operands[1], Pmode, units_per_word)); |
39403d82 | 9993 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
59257ff7 RK |
9994 | DONE; |
9995 | }") | |
9ebbca7d GK |
9996 | \f |
9997 | ;; TOC register handling. | |
b6c9286a | 9998 | |
9ebbca7d | 9999 | ;; Code to initialize the TOC register... |
f0f6a223 | 10000 | |
9ebbca7d | 10001 | (define_insn "load_toc_aix_si" |
e72247f4 | 10002 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
615158e2 | 10003 | (unspec:SI [(const_int 0)] UNSPEC_TOC)) |
46aaf10d | 10004 | (use (reg:SI 2))])] |
2bfcf297 | 10005 | "DEFAULT_ABI == ABI_AIX && TARGET_32BIT" |
f0f6a223 RK |
10006 | "* |
10007 | { | |
9ebbca7d GK |
10008 | char buf[30]; |
10009 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
a8a05998 | 10010 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
10011 | operands[2] = gen_rtx_REG (Pmode, 2); |
10012 | return \"{l|lwz} %0,%1(%2)\"; | |
f0f6a223 RK |
10013 | }" |
10014 | [(set_attr "type" "load")]) | |
9ebbca7d GK |
10015 | |
10016 | (define_insn "load_toc_aix_di" | |
e72247f4 | 10017 | [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
615158e2 | 10018 | (unspec:DI [(const_int 0)] UNSPEC_TOC)) |
46aaf10d | 10019 | (use (reg:DI 2))])] |
2bfcf297 | 10020 | "DEFAULT_ABI == ABI_AIX && TARGET_64BIT" |
9ebbca7d GK |
10021 | "* |
10022 | { | |
10023 | char buf[30]; | |
f585a356 DE |
10024 | #ifdef TARGET_RELOCATABLE |
10025 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", | |
10026 | !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE); | |
10027 | #else | |
9ebbca7d | 10028 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); |
f585a356 | 10029 | #endif |
2bfcf297 DB |
10030 | if (TARGET_ELF) |
10031 | strcat (buf, \"@toc\"); | |
a8a05998 | 10032 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
10033 | operands[2] = gen_rtx_REG (Pmode, 2); |
10034 | return \"ld %0,%1(%2)\"; | |
10035 | }" | |
10036 | [(set_attr "type" "load")]) | |
10037 | ||
10038 | (define_insn "load_toc_v4_pic_si" | |
10039 | [(set (match_operand:SI 0 "register_operand" "=l") | |
615158e2 | 10040 | (unspec:SI [(const_int 0)] UNSPEC_TOC))] |
f607bc57 | 10041 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT" |
9ebbca7d GK |
10042 | "bl _GLOBAL_OFFSET_TABLE_@local-4" |
10043 | [(set_attr "type" "branch") | |
10044 | (set_attr "length" "4")]) | |
10045 | ||
9ebbca7d GK |
10046 | (define_insn "load_toc_v4_PIC_1" |
10047 | [(set (match_operand:SI 0 "register_operand" "=l") | |
10048 | (match_operand:SI 1 "immediate_operand" "s")) | |
c4501e62 | 10049 | (use (unspec [(match_dup 1)] UNSPEC_TOC))] |
20b71b17 | 10050 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
df7a8989 | 10051 | "bcl 20,31,%1\\n%1:" |
9ebbca7d GK |
10052 | [(set_attr "type" "branch") |
10053 | (set_attr "length" "4")]) | |
10054 | ||
10055 | (define_insn "load_toc_v4_PIC_1b" | |
10056 | [(set (match_operand:SI 0 "register_operand" "=l") | |
10057 | (match_operand:SI 1 "immediate_operand" "s")) | |
c4501e62 JJ |
10058 | (use (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] |
10059 | UNSPEC_TOCPTR))] | |
20b71b17 | 10060 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
c4501e62 | 10061 | "bcl 20,31,%1+4\\n%1:\\n\\t.long %2-%1" |
9ebbca7d GK |
10062 | [(set_attr "type" "branch") |
10063 | (set_attr "length" "8")]) | |
10064 | ||
10065 | (define_insn "load_toc_v4_PIC_2" | |
f585a356 | 10066 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
a2900460 | 10067 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
9ebbca7d GK |
10068 | (minus:SI (match_operand:SI 2 "immediate_operand" "s") |
10069 | (match_operand:SI 3 "immediate_operand" "s")))))] | |
20b71b17 | 10070 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
9ebbca7d GK |
10071 | "{l|lwz} %0,%2-%3(%1)" |
10072 | [(set_attr "type" "load")]) | |
10073 | ||
f51eee6a | 10074 | |
9ebbca7d GK |
10075 | ;; If the TOC is shared over a translation unit, as happens with all |
10076 | ;; the kinds of PIC that we support, we need to restore the TOC | |
10077 | ;; pointer only when jumping over units of translation. | |
f51eee6a | 10078 | ;; On Darwin, we need to reload the picbase. |
9ebbca7d GK |
10079 | |
10080 | (define_expand "builtin_setjmp_receiver" | |
10081 | [(use (label_ref (match_operand 0 "" "")))] | |
f607bc57 | 10082 | "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
f51eee6a GK |
10083 | || (TARGET_TOC && TARGET_MINIMAL_TOC) |
10084 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)" | |
9ebbca7d GK |
10085 | " |
10086 | { | |
84d7dd4a | 10087 | #if TARGET_MACHO |
f51eee6a GK |
10088 | if (DEFAULT_ABI == ABI_DARWIN) |
10089 | { | |
d24652ee | 10090 | const char *picbase = machopic_function_base_name (); |
485bad26 | 10091 | rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase)); |
f51eee6a GK |
10092 | rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
10093 | rtx tmplabrtx; | |
10094 | char tmplab[20]; | |
10095 | ||
10096 | ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\", | |
10097 | CODE_LABEL_NUMBER (operands[0])); | |
485bad26 | 10098 | tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab)); |
f51eee6a | 10099 | |
b8a55285 AP |
10100 | emit_insn (gen_load_macho_picbase (picreg, tmplabrtx)); |
10101 | emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx)); | |
f51eee6a GK |
10102 | } |
10103 | else | |
84d7dd4a | 10104 | #endif |
f51eee6a | 10105 | rs6000_emit_load_toc_table (FALSE); |
9ebbca7d GK |
10106 | DONE; |
10107 | }") | |
10108 | \f | |
10109 | ;; A function pointer under AIX is a pointer to a data area whose first word | |
10110 | ;; contains the actual address of the function, whose second word contains a | |
b6c9286a MM |
10111 | ;; pointer to its TOC, and whose third word contains a value to place in the |
10112 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 | 10113 | ;; "trampoline" need not have any executable code. |
b6c9286a | 10114 | |
cccf3bdc DE |
10115 | (define_expand "call_indirect_aix32" |
10116 | [(set (match_dup 2) | |
10117 | (mem:SI (match_operand:SI 0 "gpc_reg_operand" ""))) | |
10118 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
10119 | (reg:SI 2)) | |
10120 | (set (reg:SI 2) | |
10121 | (mem:SI (plus:SI (match_dup 0) | |
10122 | (const_int 4)))) | |
10123 | (set (reg:SI 11) | |
10124 | (mem:SI (plus:SI (match_dup 0) | |
10125 | (const_int 8)))) | |
10126 | (parallel [(call (mem:SI (match_dup 2)) | |
10127 | (match_operand 1 "" "")) | |
10128 | (use (reg:SI 2)) | |
10129 | (use (reg:SI 11)) | |
10130 | (set (reg:SI 2) | |
10131 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10132 | (clobber (scratch:SI))])] | |
10133 | "TARGET_32BIT" | |
10134 | " | |
10135 | { operands[2] = gen_reg_rtx (SImode); }") | |
b6c9286a | 10136 | |
cccf3bdc DE |
10137 | (define_expand "call_indirect_aix64" |
10138 | [(set (match_dup 2) | |
10139 | (mem:DI (match_operand:DI 0 "gpc_reg_operand" ""))) | |
10140 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
10141 | (reg:DI 2)) | |
10142 | (set (reg:DI 2) | |
10143 | (mem:DI (plus:DI (match_dup 0) | |
10144 | (const_int 8)))) | |
10145 | (set (reg:DI 11) | |
10146 | (mem:DI (plus:DI (match_dup 0) | |
10147 | (const_int 16)))) | |
10148 | (parallel [(call (mem:SI (match_dup 2)) | |
10149 | (match_operand 1 "" "")) | |
10150 | (use (reg:DI 2)) | |
10151 | (use (reg:DI 11)) | |
10152 | (set (reg:DI 2) | |
10153 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10154 | (clobber (scratch:SI))])] | |
10155 | "TARGET_64BIT" | |
10156 | " | |
10157 | { operands[2] = gen_reg_rtx (DImode); }") | |
b6c9286a | 10158 | |
cccf3bdc DE |
10159 | (define_expand "call_value_indirect_aix32" |
10160 | [(set (match_dup 3) | |
10161 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
10162 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
10163 | (reg:SI 2)) | |
10164 | (set (reg:SI 2) | |
10165 | (mem:SI (plus:SI (match_dup 1) | |
10166 | (const_int 4)))) | |
10167 | (set (reg:SI 11) | |
10168 | (mem:SI (plus:SI (match_dup 1) | |
10169 | (const_int 8)))) | |
10170 | (parallel [(set (match_operand 0 "" "") | |
10171 | (call (mem:SI (match_dup 3)) | |
10172 | (match_operand 2 "" ""))) | |
10173 | (use (reg:SI 2)) | |
10174 | (use (reg:SI 11)) | |
10175 | (set (reg:SI 2) | |
10176 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10177 | (clobber (scratch:SI))])] | |
10178 | "TARGET_32BIT" | |
10179 | " | |
10180 | { operands[3] = gen_reg_rtx (SImode); }") | |
b6c9286a | 10181 | |
cccf3bdc DE |
10182 | (define_expand "call_value_indirect_aix64" |
10183 | [(set (match_dup 3) | |
10184 | (mem:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
10185 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
10186 | (reg:DI 2)) | |
10187 | (set (reg:DI 2) | |
10188 | (mem:DI (plus:DI (match_dup 1) | |
10189 | (const_int 8)))) | |
10190 | (set (reg:DI 11) | |
10191 | (mem:DI (plus:DI (match_dup 1) | |
10192 | (const_int 16)))) | |
10193 | (parallel [(set (match_operand 0 "" "") | |
10194 | (call (mem:SI (match_dup 3)) | |
10195 | (match_operand 2 "" ""))) | |
10196 | (use (reg:DI 2)) | |
10197 | (use (reg:DI 11)) | |
10198 | (set (reg:DI 2) | |
10199 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10200 | (clobber (scratch:SI))])] | |
10201 | "TARGET_64BIT" | |
10202 | " | |
10203 | { operands[3] = gen_reg_rtx (DImode); }") | |
1fd4e8c1 | 10204 | |
b6c9286a | 10205 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 10206 | (define_expand "call" |
a260abc9 | 10207 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 10208 | (match_operand 1 "" "")) |
4697a36c | 10209 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
10210 | (clobber (scratch:SI))])] |
10211 | "" | |
10212 | " | |
10213 | { | |
ee890fe2 | 10214 | #if TARGET_MACHO |
ab82a49f | 10215 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
10216 | operands[0] = machopic_indirect_call_target (operands[0]); |
10217 | #endif | |
10218 | ||
1fd4e8c1 RK |
10219 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) |
10220 | abort (); | |
10221 | ||
10222 | operands[0] = XEXP (operands[0], 0); | |
7509c759 | 10223 | |
6a4cee5f | 10224 | if (GET_CODE (operands[0]) != SYMBOL_REF |
473f51b6 | 10225 | || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0])) |
efdba735 | 10226 | || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0)) |
1fd4e8c1 | 10227 | { |
6a4cee5f MM |
10228 | if (INTVAL (operands[2]) & CALL_LONG) |
10229 | operands[0] = rs6000_longcall_ref (operands[0]); | |
10230 | ||
cccf3bdc | 10231 | if (DEFAULT_ABI == ABI_V4 |
f607bc57 | 10232 | || DEFAULT_ABI == ABI_DARWIN) |
bbf294a5 | 10233 | operands[0] = force_reg (Pmode, operands[0]); |
1fd4e8c1 | 10234 | |
cccf3bdc DE |
10235 | else if (DEFAULT_ABI == ABI_AIX) |
10236 | { | |
10237 | /* AIX function pointers are really pointers to a three word | |
10238 | area. */ | |
10239 | emit_call_insn (TARGET_32BIT | |
10240 | ? gen_call_indirect_aix32 (force_reg (SImode, | |
10241 | operands[0]), | |
10242 | operands[1]) | |
10243 | : gen_call_indirect_aix64 (force_reg (DImode, | |
10244 | operands[0]), | |
10245 | operands[1])); | |
10246 | DONE; | |
b6c9286a | 10247 | } |
cccf3bdc DE |
10248 | else |
10249 | abort (); | |
1fd4e8c1 RK |
10250 | } |
10251 | }") | |
10252 | ||
10253 | (define_expand "call_value" | |
10254 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 10255 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 10256 | (match_operand 2 "" ""))) |
4697a36c | 10257 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
10258 | (clobber (scratch:SI))])] |
10259 | "" | |
10260 | " | |
10261 | { | |
ee890fe2 | 10262 | #if TARGET_MACHO |
ab82a49f | 10263 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
10264 | operands[1] = machopic_indirect_call_target (operands[1]); |
10265 | #endif | |
10266 | ||
1fd4e8c1 RK |
10267 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) |
10268 | abort (); | |
10269 | ||
10270 | operands[1] = XEXP (operands[1], 0); | |
7509c759 | 10271 | |
6a4cee5f | 10272 | if (GET_CODE (operands[1]) != SYMBOL_REF |
473f51b6 | 10273 | || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1])) |
efdba735 | 10274 | || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0)) |
1fd4e8c1 | 10275 | { |
6756293c | 10276 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
10277 | operands[1] = rs6000_longcall_ref (operands[1]); |
10278 | ||
cccf3bdc | 10279 | if (DEFAULT_ABI == ABI_V4 |
f607bc57 | 10280 | || DEFAULT_ABI == ABI_DARWIN) |
bbf294a5 | 10281 | operands[1] = force_reg (Pmode, operands[1]); |
1fd4e8c1 | 10282 | |
cccf3bdc DE |
10283 | else if (DEFAULT_ABI == ABI_AIX) |
10284 | { | |
10285 | /* AIX function pointers are really pointers to a three word | |
10286 | area. */ | |
10287 | emit_call_insn (TARGET_32BIT | |
10288 | ? gen_call_value_indirect_aix32 (operands[0], | |
10289 | force_reg (SImode, | |
10290 | operands[1]), | |
10291 | operands[2]) | |
10292 | : gen_call_value_indirect_aix64 (operands[0], | |
10293 | force_reg (DImode, | |
10294 | operands[1]), | |
10295 | operands[2])); | |
10296 | DONE; | |
b6c9286a | 10297 | } |
cccf3bdc DE |
10298 | else |
10299 | abort (); | |
1fd4e8c1 RK |
10300 | } |
10301 | }") | |
10302 | ||
04780ee7 | 10303 | ;; Call to function in current module. No TOC pointer reload needed. |
a0ab749a | 10304 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
10305 | ;; either the function was not prototyped, or it was prototyped as a |
10306 | ;; variable argument function. It is > 0 if FP registers were passed | |
10307 | ;; and < 0 if they were not. | |
04780ee7 | 10308 | |
a260abc9 | 10309 | (define_insn "*call_local32" |
4697a36c MM |
10310 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
10311 | (match_operand 1 "" "g,g")) | |
10312 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10313 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 10314 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
10315 | "* |
10316 | { | |
6a4cee5f MM |
10317 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
10318 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10319 | ||
10320 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10321 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 10322 | |
a226df46 | 10323 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 10324 | }" |
b7ff3d82 DE |
10325 | [(set_attr "type" "branch") |
10326 | (set_attr "length" "4,8")]) | |
04780ee7 | 10327 | |
a260abc9 DE |
10328 | (define_insn "*call_local64" |
10329 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
10330 | (match_operand 1 "" "g,g")) | |
10331 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10332 | (clobber (match_scratch:SI 3 "=l,l"))] | |
10333 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10334 | "* | |
10335 | { | |
10336 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10337 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10338 | ||
10339 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10340 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10341 | ||
10342 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
10343 | }" | |
10344 | [(set_attr "type" "branch") | |
10345 | (set_attr "length" "4,8")]) | |
10346 | ||
cccf3bdc | 10347 | (define_insn "*call_value_local32" |
d18dba68 | 10348 | [(set (match_operand 0 "" "") |
a260abc9 DE |
10349 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) |
10350 | (match_operand 2 "" "g,g"))) | |
10351 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10352 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10353 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
10354 | "* | |
10355 | { | |
10356 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10357 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10358 | ||
10359 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10360 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10361 | ||
10362 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
10363 | }" | |
10364 | [(set_attr "type" "branch") | |
10365 | (set_attr "length" "4,8")]) | |
10366 | ||
10367 | ||
cccf3bdc | 10368 | (define_insn "*call_value_local64" |
d18dba68 | 10369 | [(set (match_operand 0 "" "") |
a260abc9 DE |
10370 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) |
10371 | (match_operand 2 "" "g,g"))) | |
10372 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10373 | (clobber (match_scratch:SI 4 "=l,l"))] | |
10374 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10375 | "* | |
10376 | { | |
10377 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10378 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10379 | ||
10380 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10381 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10382 | ||
10383 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
10384 | }" | |
10385 | [(set_attr "type" "branch") | |
10386 | (set_attr "length" "4,8")]) | |
10387 | ||
04780ee7 | 10388 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 10389 | ;; pointer (r2) after the call unless this is System V. |
a0ab749a | 10390 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
10391 | ;; either the function was not prototyped, or it was prototyped as a |
10392 | ;; variable argument function. It is > 0 if FP registers were passed | |
10393 | ;; and < 0 if they were not. | |
04780ee7 | 10394 | |
cccf3bdc DE |
10395 | (define_insn "*call_indirect_nonlocal_aix32" |
10396 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl")) | |
10397 | (match_operand 1 "" "g")) | |
10398 | (use (reg:SI 2)) | |
10399 | (use (reg:SI 11)) | |
10400 | (set (reg:SI 2) | |
10401 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
c77e04ae | 10402 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
10403 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" |
10404 | "b%T0l\;{l|lwz} 2,20(1)" | |
10405 | [(set_attr "type" "jmpreg") | |
10406 | (set_attr "length" "8")]) | |
10407 | ||
a260abc9 | 10408 | (define_insn "*call_nonlocal_aix32" |
cc4d5fec | 10409 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10410 | (match_operand 1 "" "g")) |
10411 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10412 | (clobber (match_scratch:SI 3 "=l"))] | |
10413 | "TARGET_32BIT | |
10414 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 10415 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10416 | "bl %z0\;%." |
b7ff3d82 | 10417 | [(set_attr "type" "branch") |
cccf3bdc DE |
10418 | (set_attr "length" "8")]) |
10419 | ||
10420 | (define_insn "*call_indirect_nonlocal_aix64" | |
10421 | [(call (mem:SI (match_operand:DI 0 "register_operand" "cl")) | |
10422 | (match_operand 1 "" "g")) | |
10423 | (use (reg:DI 2)) | |
10424 | (use (reg:DI 11)) | |
10425 | (set (reg:DI 2) | |
10426 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
c77e04ae | 10427 | (clobber (match_scratch:SI 2 "=l"))] |
cccf3bdc DE |
10428 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" |
10429 | "b%T0l\;ld 2,40(1)" | |
10430 | [(set_attr "type" "jmpreg") | |
10431 | (set_attr "length" "8")]) | |
59313e4e | 10432 | |
a260abc9 | 10433 | (define_insn "*call_nonlocal_aix64" |
cc4d5fec | 10434 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10435 | (match_operand 1 "" "g")) |
10436 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10437 | (clobber (match_scratch:SI 3 "=l"))] | |
6ae08853 | 10438 | "TARGET_64BIT |
9ebbca7d | 10439 | && DEFAULT_ABI == ABI_AIX |
a260abc9 | 10440 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10441 | "bl %z0\;%." |
a260abc9 | 10442 | [(set_attr "type" "branch") |
cccf3bdc | 10443 | (set_attr "length" "8")]) |
7509c759 | 10444 | |
cccf3bdc | 10445 | (define_insn "*call_value_indirect_nonlocal_aix32" |
d18dba68 | 10446 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10447 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl")) |
10448 | (match_operand 2 "" "g"))) | |
10449 | (use (reg:SI 2)) | |
10450 | (use (reg:SI 11)) | |
10451 | (set (reg:SI 2) | |
10452 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
10453 | (clobber (match_scratch:SI 3 "=l"))] | |
10454 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" | |
10455 | "b%T1l\;{l|lwz} 2,20(1)" | |
10456 | [(set_attr "type" "jmpreg") | |
10457 | (set_attr "length" "8")]) | |
1fd4e8c1 | 10458 | |
cccf3bdc | 10459 | (define_insn "*call_value_nonlocal_aix32" |
d18dba68 | 10460 | [(set (match_operand 0 "" "") |
cc4d5fec | 10461 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10462 | (match_operand 2 "" "g"))) |
10463 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10464 | (clobber (match_scratch:SI 4 "=l"))] | |
10465 | "TARGET_32BIT | |
10466 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 10467 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc | 10468 | "bl %z1\;%." |
b7ff3d82 | 10469 | [(set_attr "type" "branch") |
cccf3bdc | 10470 | (set_attr "length" "8")]) |
04780ee7 | 10471 | |
cccf3bdc | 10472 | (define_insn "*call_value_indirect_nonlocal_aix64" |
d18dba68 | 10473 | [(set (match_operand 0 "" "") |
cccf3bdc DE |
10474 | (call (mem:SI (match_operand:DI 1 "register_operand" "cl")) |
10475 | (match_operand 2 "" "g"))) | |
10476 | (use (reg:DI 2)) | |
10477 | (use (reg:DI 11)) | |
10478 | (set (reg:DI 2) | |
10479 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
10480 | (clobber (match_scratch:SI 3 "=l"))] | |
10481 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" | |
10482 | "b%T1l\;ld 2,40(1)" | |
10483 | [(set_attr "type" "jmpreg") | |
10484 | (set_attr "length" "8")]) | |
10485 | ||
10486 | (define_insn "*call_value_nonlocal_aix64" | |
d18dba68 | 10487 | [(set (match_operand 0 "" "") |
cc4d5fec | 10488 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10489 | (match_operand 2 "" "g"))) |
10490 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10491 | (clobber (match_scratch:SI 4 "=l"))] | |
6ae08853 | 10492 | "TARGET_64BIT |
9ebbca7d | 10493 | && DEFAULT_ABI == ABI_AIX |
5a19791c | 10494 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc DE |
10495 | "bl %z1\;%." |
10496 | [(set_attr "type" "branch") | |
10497 | (set_attr "length" "8")]) | |
10498 | ||
10499 | ;; A function pointer under System V is just a normal pointer | |
10500 | ;; operands[0] is the function pointer | |
10501 | ;; operands[1] is the stack size to clean up | |
10502 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument | |
10503 | ;; which indicates how to set cr1 | |
10504 | ||
a5c76ee6 ZW |
10505 | (define_insn "*call_indirect_nonlocal_sysv" |
10506 | [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl")) | |
10507 | (match_operand 1 "" "g,g")) | |
10508 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10509 | (clobber (match_scratch:SI 3 "=l,l"))] | |
50d440bc | 10510 | "DEFAULT_ABI == ABI_V4 |
f607bc57 | 10511 | || DEFAULT_ABI == ABI_DARWIN" |
911f679c | 10512 | { |
cccf3bdc | 10513 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10514 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f | 10515 | |
cccf3bdc | 10516 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
a5c76ee6 | 10517 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10518 | |
a5c76ee6 ZW |
10519 | return "b%T0l"; |
10520 | } | |
10521 | [(set_attr "type" "jmpreg,jmpreg") | |
10522 | (set_attr "length" "4,8")]) | |
cccf3bdc | 10523 | |
a5c76ee6 ZW |
10524 | (define_insn "*call_nonlocal_sysv" |
10525 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10526 | (match_operand 1 "" "g,g")) | |
10527 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10528 | (clobber (match_scratch:SI 3 "=l,l"))] | |
efdba735 SH |
10529 | "(DEFAULT_ABI == ABI_DARWIN |
10530 | || (DEFAULT_ABI == ABI_V4 | |
10531 | && (INTVAL (operands[2]) & CALL_LONG) == 0))" | |
a5c76ee6 ZW |
10532 | { |
10533 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10534 | output_asm_insn ("crxor 6,6,6", operands); | |
10535 | ||
10536 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10537 | output_asm_insn ("creqv 6,6,6", operands); | |
10538 | ||
c989f2f7 | 10539 | #if TARGET_MACHO |
efdba735 SH |
10540 | return output_call(insn, operands, 0, 2); |
10541 | #else | |
a5c76ee6 | 10542 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0"; |
6ae08853 | 10543 | #endif |
a5c76ee6 ZW |
10544 | } |
10545 | [(set_attr "type" "branch,branch") | |
10546 | (set_attr "length" "4,8")]) | |
10547 | ||
10548 | (define_insn "*call_value_indirect_nonlocal_sysv" | |
d18dba68 | 10549 | [(set (match_operand 0 "" "") |
a5c76ee6 ZW |
10550 | (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl")) |
10551 | (match_operand 2 "" "g,g"))) | |
10552 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10553 | (clobber (match_scratch:SI 4 "=l,l"))] | |
50d440bc | 10554 | "DEFAULT_ABI == ABI_V4 |
f607bc57 | 10555 | || DEFAULT_ABI == ABI_DARWIN" |
b6c9286a | 10556 | { |
6a4cee5f | 10557 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10558 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f MM |
10559 | |
10560 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
a5c76ee6 | 10561 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10562 | |
a5c76ee6 ZW |
10563 | return "b%T1l"; |
10564 | } | |
10565 | [(set_attr "type" "jmpreg,jmpreg") | |
10566 | (set_attr "length" "4,8")]) | |
10567 | ||
10568 | (define_insn "*call_value_nonlocal_sysv" | |
10569 | [(set (match_operand 0 "" "") | |
10570 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10571 | (match_operand 2 "" "g,g"))) | |
10572 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10573 | (clobber (match_scratch:SI 4 "=l,l"))] | |
efdba735 SH |
10574 | "(DEFAULT_ABI == ABI_DARWIN |
10575 | || (DEFAULT_ABI == ABI_V4 | |
10576 | && (INTVAL (operands[3]) & CALL_LONG) == 0))" | |
a5c76ee6 ZW |
10577 | { |
10578 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10579 | output_asm_insn ("crxor 6,6,6", operands); | |
10580 | ||
10581 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10582 | output_asm_insn ("creqv 6,6,6", operands); | |
10583 | ||
c989f2f7 | 10584 | #if TARGET_MACHO |
efdba735 SH |
10585 | return output_call(insn, operands, 1, 3); |
10586 | #else | |
a5c76ee6 | 10587 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1"; |
6ae08853 | 10588 | #endif |
a5c76ee6 ZW |
10589 | } |
10590 | [(set_attr "type" "branch,branch") | |
10591 | (set_attr "length" "4,8")]) | |
e6f948e3 RK |
10592 | |
10593 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
10594 | (define_expand "untyped_call" |
10595 | [(parallel [(call (match_operand 0 "" "") | |
10596 | (const_int 0)) | |
10597 | (match_operand 1 "" "") | |
10598 | (match_operand 2 "" "")])] | |
10599 | "" | |
10600 | " | |
10601 | { | |
10602 | int i; | |
10603 | ||
7d70b8b2 | 10604 | emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
10605 | |
10606 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
10607 | { | |
10608 | rtx set = XVECEXP (operands[2], 0, i); | |
10609 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
10610 | } | |
10611 | ||
10612 | /* The optimizer does not know that the call sets the function value | |
10613 | registers we stored in the result block. We avoid problems by | |
10614 | claiming that all hard registers are used and clobbered at this | |
10615 | point. */ | |
10616 | emit_insn (gen_blockage ()); | |
10617 | ||
10618 | DONE; | |
10619 | }") | |
10620 | ||
5e1bf043 DJ |
10621 | ;; sibling call patterns |
10622 | (define_expand "sibcall" | |
10623 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) | |
10624 | (match_operand 1 "" "")) | |
10625 | (use (match_operand 2 "" "")) | |
fe352c29 | 10626 | (use (match_operand 3 "" "")) |
5e1bf043 DJ |
10627 | (return)])] |
10628 | "" | |
10629 | " | |
10630 | { | |
10631 | #if TARGET_MACHO | |
ab82a49f | 10632 | if (MACHOPIC_INDIRECT) |
5e1bf043 DJ |
10633 | operands[0] = machopic_indirect_call_target (operands[0]); |
10634 | #endif | |
10635 | ||
10636 | if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) | |
10637 | abort (); | |
10638 | ||
10639 | operands[0] = XEXP (operands[0], 0); | |
fe352c29 | 10640 | operands[3] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
10641 | |
10642 | }") | |
10643 | ||
10644 | ;; this and similar patterns must be marked as using LR, otherwise | |
10645 | ;; dataflow will try to delete the store into it. This is true | |
10646 | ;; even when the actual reg to jump to is in CTR, when LR was | |
10647 | ;; saved and restored around the PIC-setting BCL. | |
10648 | (define_insn "*sibcall_local32" | |
10649 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) | |
10650 | (match_operand 1 "" "g,g")) | |
10651 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 10652 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10653 | (return)] |
10654 | "(INTVAL (operands[2]) & CALL_LONG) == 0" | |
10655 | "* | |
10656 | { | |
10657 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10658 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10659 | ||
10660 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10661 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10662 | ||
10663 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
10664 | }" | |
10665 | [(set_attr "type" "branch") | |
10666 | (set_attr "length" "4,8")]) | |
10667 | ||
10668 | (define_insn "*sibcall_local64" | |
10669 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
10670 | (match_operand 1 "" "g,g")) | |
10671 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 10672 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10673 | (return)] |
10674 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10675 | "* | |
10676 | { | |
10677 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10678 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10679 | ||
10680 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10681 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10682 | ||
10683 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
10684 | }" | |
10685 | [(set_attr "type" "branch") | |
10686 | (set_attr "length" "4,8")]) | |
10687 | ||
10688 | (define_insn "*sibcall_value_local32" | |
10689 | [(set (match_operand 0 "" "") | |
10690 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) | |
10691 | (match_operand 2 "" "g,g"))) | |
10692 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10693 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10694 | (return)] |
10695 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
10696 | "* | |
10697 | { | |
10698 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10699 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10700 | ||
10701 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10702 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10703 | ||
10704 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
10705 | }" | |
10706 | [(set_attr "type" "branch") | |
10707 | (set_attr "length" "4,8")]) | |
10708 | ||
10709 | ||
10710 | (define_insn "*sibcall_value_local64" | |
10711 | [(set (match_operand 0 "" "") | |
10712 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) | |
10713 | (match_operand 2 "" "g,g"))) | |
10714 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10715 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10716 | (return)] |
10717 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10718 | "* | |
10719 | { | |
10720 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10721 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10722 | ||
10723 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10724 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10725 | ||
10726 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
10727 | }" | |
10728 | [(set_attr "type" "branch") | |
10729 | (set_attr "length" "4,8")]) | |
10730 | ||
10731 | (define_insn "*sibcall_nonlocal_aix32" | |
10732 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) | |
10733 | (match_operand 1 "" "g")) | |
10734 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 10735 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 DJ |
10736 | (return)] |
10737 | "TARGET_32BIT | |
10738 | && DEFAULT_ABI == ABI_AIX | |
10739 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10740 | "b %z0" | |
10741 | [(set_attr "type" "branch") | |
10742 | (set_attr "length" "4")]) | |
10743 | ||
10744 | (define_insn "*sibcall_nonlocal_aix64" | |
10745 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) | |
10746 | (match_operand 1 "" "g")) | |
10747 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 10748 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 | 10749 | (return)] |
6ae08853 | 10750 | "TARGET_64BIT |
5e1bf043 DJ |
10751 | && DEFAULT_ABI == ABI_AIX |
10752 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10753 | "b %z0" | |
10754 | [(set_attr "type" "branch") | |
10755 | (set_attr "length" "4")]) | |
10756 | ||
10757 | (define_insn "*sibcall_value_nonlocal_aix32" | |
10758 | [(set (match_operand 0 "" "") | |
10759 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) | |
10760 | (match_operand 2 "" "g"))) | |
10761 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 10762 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 DJ |
10763 | (return)] |
10764 | "TARGET_32BIT | |
10765 | && DEFAULT_ABI == ABI_AIX | |
10766 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10767 | "b %z1" | |
10768 | [(set_attr "type" "branch") | |
10769 | (set_attr "length" "4")]) | |
10770 | ||
10771 | (define_insn "*sibcall_value_nonlocal_aix64" | |
10772 | [(set (match_operand 0 "" "") | |
10773 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) | |
10774 | (match_operand 2 "" "g"))) | |
10775 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 10776 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 | 10777 | (return)] |
6ae08853 | 10778 | "TARGET_64BIT |
5e1bf043 DJ |
10779 | && DEFAULT_ABI == ABI_AIX |
10780 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10781 | "b %z1" | |
10782 | [(set_attr "type" "branch") | |
10783 | (set_attr "length" "4")]) | |
10784 | ||
10785 | (define_insn "*sibcall_nonlocal_sysv" | |
10786 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10787 | (match_operand 1 "" "")) | |
10788 | (use (match_operand 2 "immediate_operand" "O,n")) | |
fe352c29 | 10789 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10790 | (return)] |
10791 | "(DEFAULT_ABI == ABI_DARWIN | |
50d440bc | 10792 | || DEFAULT_ABI == ABI_V4) |
5e1bf043 DJ |
10793 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
10794 | "* | |
10795 | { | |
10796 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10797 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10798 | ||
10799 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10800 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10801 | ||
10802 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\"; | |
10803 | }" | |
10804 | [(set_attr "type" "branch,branch") | |
10805 | (set_attr "length" "4,8")]) | |
10806 | ||
10807 | (define_expand "sibcall_value" | |
10808 | [(parallel [(set (match_operand 0 "register_operand" "") | |
10809 | (call (mem:SI (match_operand 1 "address_operand" "")) | |
10810 | (match_operand 2 "" ""))) | |
10811 | (use (match_operand 3 "" "")) | |
fe352c29 | 10812 | (use (match_operand 4 "" "")) |
5e1bf043 DJ |
10813 | (return)])] |
10814 | "" | |
10815 | " | |
10816 | { | |
10817 | #if TARGET_MACHO | |
ab82a49f | 10818 | if (MACHOPIC_INDIRECT) |
5e1bf043 DJ |
10819 | operands[1] = machopic_indirect_call_target (operands[1]); |
10820 | #endif | |
10821 | ||
10822 | if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) | |
10823 | abort (); | |
10824 | ||
10825 | operands[1] = XEXP (operands[1], 0); | |
fe352c29 | 10826 | operands[4] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
10827 | |
10828 | }") | |
10829 | ||
10830 | (define_insn "*sibcall_value_nonlocal_sysv" | |
10831 | [(set (match_operand 0 "" "") | |
10832 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10833 | (match_operand 2 "" ""))) | |
10834 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10835 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10836 | (return)] |
10837 | "(DEFAULT_ABI == ABI_DARWIN | |
50d440bc | 10838 | || DEFAULT_ABI == ABI_V4) |
5e1bf043 DJ |
10839 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
10840 | "* | |
10841 | { | |
10842 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10843 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10844 | ||
10845 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10846 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10847 | ||
10848 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\"; | |
10849 | }" | |
10850 | [(set_attr "type" "branch,branch") | |
10851 | (set_attr "length" "4,8")]) | |
10852 | ||
10853 | (define_expand "sibcall_epilogue" | |
10854 | [(use (const_int 0))] | |
10855 | "TARGET_SCHED_PROLOG" | |
10856 | " | |
10857 | { | |
10858 | rs6000_emit_epilogue (TRUE); | |
10859 | DONE; | |
10860 | }") | |
10861 | ||
e6f948e3 RK |
10862 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and |
10863 | ;; all of memory. This blocks insns from being moved across this point. | |
10864 | ||
10865 | (define_insn "blockage" | |
615158e2 | 10866 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)] |
e6f948e3 RK |
10867 | "" |
10868 | "") | |
1fd4e8c1 RK |
10869 | \f |
10870 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 10871 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
10872 | ;; |
10873 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
10874 | ;; insns, and branches. We store the operands of compares until we see | |
10875 | ;; how it is used. | |
10876 | (define_expand "cmpsi" | |
10877 | [(set (cc0) | |
cd2b37d9 | 10878 | (compare (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10879 | (match_operand:SI 1 "reg_or_short_operand" "")))] |
10880 | "" | |
10881 | " | |
10882 | { | |
10883 | /* Take care of the possibility that operands[1] might be negative but | |
10884 | this might be a logical operation. That insn doesn't exist. */ | |
10885 | if (GET_CODE (operands[1]) == CONST_INT | |
10886 | && INTVAL (operands[1]) < 0) | |
10887 | operands[1] = force_reg (SImode, operands[1]); | |
10888 | ||
10889 | rs6000_compare_op0 = operands[0]; | |
10890 | rs6000_compare_op1 = operands[1]; | |
10891 | rs6000_compare_fp_p = 0; | |
10892 | DONE; | |
10893 | }") | |
10894 | ||
266eb58a DE |
10895 | (define_expand "cmpdi" |
10896 | [(set (cc0) | |
10897 | (compare (match_operand:DI 0 "gpc_reg_operand" "") | |
10898 | (match_operand:DI 1 "reg_or_short_operand" "")))] | |
10899 | "TARGET_POWERPC64" | |
10900 | " | |
10901 | { | |
10902 | /* Take care of the possibility that operands[1] might be negative but | |
10903 | this might be a logical operation. That insn doesn't exist. */ | |
10904 | if (GET_CODE (operands[1]) == CONST_INT | |
10905 | && INTVAL (operands[1]) < 0) | |
10906 | operands[1] = force_reg (DImode, operands[1]); | |
10907 | ||
10908 | rs6000_compare_op0 = operands[0]; | |
10909 | rs6000_compare_op1 = operands[1]; | |
10910 | rs6000_compare_fp_p = 0; | |
10911 | DONE; | |
10912 | }") | |
10913 | ||
1fd4e8c1 | 10914 | (define_expand "cmpsf" |
cd2b37d9 RK |
10915 | [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") |
10916 | (match_operand:SF 1 "gpc_reg_operand" "")))] | |
d14a6d05 | 10917 | "TARGET_HARD_FLOAT" |
1fd4e8c1 RK |
10918 | " |
10919 | { | |
10920 | rs6000_compare_op0 = operands[0]; | |
10921 | rs6000_compare_op1 = operands[1]; | |
10922 | rs6000_compare_fp_p = 1; | |
10923 | DONE; | |
10924 | }") | |
10925 | ||
10926 | (define_expand "cmpdf" | |
cd2b37d9 RK |
10927 | [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") |
10928 | (match_operand:DF 1 "gpc_reg_operand" "")))] | |
7a2f7870 | 10929 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" |
1fd4e8c1 RK |
10930 | " |
10931 | { | |
10932 | rs6000_compare_op0 = operands[0]; | |
10933 | rs6000_compare_op1 = operands[1]; | |
10934 | rs6000_compare_fp_p = 1; | |
10935 | DONE; | |
10936 | }") | |
10937 | ||
d6f99ca4 | 10938 | (define_expand "cmptf" |
e7a4130e DE |
10939 | [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "") |
10940 | (match_operand:TF 1 "gpc_reg_operand" "")))] | |
39e63627 GK |
10941 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
10942 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
d6f99ca4 DE |
10943 | " |
10944 | { | |
10945 | rs6000_compare_op0 = operands[0]; | |
10946 | rs6000_compare_op1 = operands[1]; | |
10947 | rs6000_compare_fp_p = 1; | |
10948 | DONE; | |
10949 | }") | |
10950 | ||
1fd4e8c1 | 10951 | (define_expand "beq" |
39a10a29 | 10952 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10953 | "" |
39a10a29 | 10954 | "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
10955 | |
10956 | (define_expand "bne" | |
39a10a29 | 10957 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10958 | "" |
39a10a29 | 10959 | "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }") |
1fd4e8c1 | 10960 | |
39a10a29 GK |
10961 | (define_expand "bge" |
10962 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10963 | "" |
39a10a29 | 10964 | "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }") |
1fd4e8c1 RK |
10965 | |
10966 | (define_expand "bgt" | |
39a10a29 | 10967 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10968 | "" |
39a10a29 | 10969 | "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }") |
1fd4e8c1 RK |
10970 | |
10971 | (define_expand "ble" | |
39a10a29 | 10972 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10973 | "" |
39a10a29 | 10974 | "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }") |
1fd4e8c1 | 10975 | |
39a10a29 GK |
10976 | (define_expand "blt" |
10977 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10978 | "" |
39a10a29 | 10979 | "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }") |
1fd4e8c1 | 10980 | |
39a10a29 GK |
10981 | (define_expand "bgeu" |
10982 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10983 | "" |
39a10a29 | 10984 | "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }") |
1fd4e8c1 | 10985 | |
39a10a29 GK |
10986 | (define_expand "bgtu" |
10987 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10988 | "" |
39a10a29 | 10989 | "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 10990 | |
39a10a29 GK |
10991 | (define_expand "bleu" |
10992 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10993 | "" |
39a10a29 | 10994 | "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }") |
1fd4e8c1 | 10995 | |
39a10a29 GK |
10996 | (define_expand "bltu" |
10997 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10998 | "" |
39a10a29 | 10999 | "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 11000 | |
1c882ea4 | 11001 | (define_expand "bunordered" |
39a10a29 | 11002 | [(use (match_operand 0 "" ""))] |
7a1bf2f9 | 11003 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
39a10a29 | 11004 | "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
11005 | |
11006 | (define_expand "bordered" | |
39a10a29 | 11007 | [(use (match_operand 0 "" ""))] |
7a1bf2f9 | 11008 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
39a10a29 | 11009 | "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
11010 | |
11011 | (define_expand "buneq" | |
39a10a29 | 11012 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11013 | "" |
39a10a29 | 11014 | "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }") |
1c882ea4 GK |
11015 | |
11016 | (define_expand "bunge" | |
39a10a29 | 11017 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11018 | "" |
39a10a29 | 11019 | "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }") |
1c882ea4 GK |
11020 | |
11021 | (define_expand "bungt" | |
39a10a29 | 11022 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11023 | "" |
39a10a29 | 11024 | "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }") |
1c882ea4 GK |
11025 | |
11026 | (define_expand "bunle" | |
39a10a29 | 11027 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11028 | "" |
39a10a29 | 11029 | "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }") |
1c882ea4 GK |
11030 | |
11031 | (define_expand "bunlt" | |
39a10a29 | 11032 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11033 | "" |
39a10a29 | 11034 | "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }") |
1c882ea4 GK |
11035 | |
11036 | (define_expand "bltgt" | |
39a10a29 | 11037 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 11038 | "" |
39a10a29 | 11039 | "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }") |
1c882ea4 | 11040 | |
1fd4e8c1 RK |
11041 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. |
11042 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
11043 | ;; with an scc insns. However, due to the order that combine see the | |
11044 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
11045 | ;; the cases we don't want to handle. | |
11046 | (define_expand "seq" | |
39a10a29 | 11047 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11048 | "" |
39a10a29 | 11049 | "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
11050 | |
11051 | (define_expand "sne" | |
39a10a29 | 11052 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11053 | "" |
11054 | " | |
6ae08853 | 11055 | { |
39a10a29 | 11056 | if (! rs6000_compare_fp_p) |
1fd4e8c1 RK |
11057 | FAIL; |
11058 | ||
6ae08853 | 11059 | rs6000_emit_sCOND (NE, operands[0]); |
39a10a29 | 11060 | DONE; |
1fd4e8c1 RK |
11061 | }") |
11062 | ||
b7053a3f GK |
11063 | ;; A >= 0 is best done the portable way for A an integer. |
11064 | (define_expand "sge" | |
39a10a29 | 11065 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11066 | "" |
11067 | " | |
5638268e DE |
11068 | { |
11069 | if (! rs6000_compare_fp_p | |
11070 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
1fd4e8c1 RK |
11071 | FAIL; |
11072 | ||
b7053a3f | 11073 | rs6000_emit_sCOND (GE, operands[0]); |
39a10a29 | 11074 | DONE; |
1fd4e8c1 RK |
11075 | }") |
11076 | ||
b7053a3f GK |
11077 | ;; A > 0 is best done using the portable sequence, so fail in that case. |
11078 | (define_expand "sgt" | |
39a10a29 | 11079 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11080 | "" |
11081 | " | |
5638268e | 11082 | { |
b7053a3f | 11083 | if (! rs6000_compare_fp_p |
5638268e | 11084 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) |
1fd4e8c1 RK |
11085 | FAIL; |
11086 | ||
6ae08853 | 11087 | rs6000_emit_sCOND (GT, operands[0]); |
39a10a29 | 11088 | DONE; |
1fd4e8c1 RK |
11089 | }") |
11090 | ||
b7053a3f GK |
11091 | ;; A <= 0 is best done the portable way for A an integer. |
11092 | (define_expand "sle" | |
39a10a29 | 11093 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11094 | "" |
5638268e DE |
11095 | " |
11096 | { | |
11097 | if (! rs6000_compare_fp_p | |
11098 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) | |
11099 | FAIL; | |
11100 | ||
6ae08853 | 11101 | rs6000_emit_sCOND (LE, operands[0]); |
5638268e DE |
11102 | DONE; |
11103 | }") | |
1fd4e8c1 | 11104 | |
b7053a3f GK |
11105 | ;; A < 0 is best done in the portable way for A an integer. |
11106 | (define_expand "slt" | |
39a10a29 | 11107 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
11108 | "" |
11109 | " | |
5638268e | 11110 | { |
6ae08853 | 11111 | if (! rs6000_compare_fp_p |
5638268e | 11112 | && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx)) |
1fd4e8c1 RK |
11113 | FAIL; |
11114 | ||
6ae08853 | 11115 | rs6000_emit_sCOND (LT, operands[0]); |
39a10a29 | 11116 | DONE; |
1fd4e8c1 RK |
11117 | }") |
11118 | ||
b7053a3f GK |
11119 | (define_expand "sgeu" |
11120 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11121 | "" | |
11122 | "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }") | |
11123 | ||
1fd4e8c1 | 11124 | (define_expand "sgtu" |
39a10a29 | 11125 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11126 | "" |
39a10a29 | 11127 | "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 11128 | |
b7053a3f GK |
11129 | (define_expand "sleu" |
11130 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11131 | "" | |
11132 | "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }") | |
11133 | ||
1fd4e8c1 | 11134 | (define_expand "sltu" |
39a10a29 | 11135 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11136 | "" |
39a10a29 | 11137 | "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 11138 | |
b7053a3f | 11139 | (define_expand "sunordered" |
39a10a29 | 11140 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11141 | "" |
b7053a3f | 11142 | "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }") |
1fd4e8c1 | 11143 | |
b7053a3f | 11144 | (define_expand "sordered" |
39a10a29 | 11145 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 11146 | "" |
b7053a3f GK |
11147 | "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }") |
11148 | ||
11149 | (define_expand "suneq" | |
11150 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11151 | "" | |
11152 | "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }") | |
11153 | ||
11154 | (define_expand "sunge" | |
11155 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11156 | "" | |
11157 | "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }") | |
11158 | ||
11159 | (define_expand "sungt" | |
11160 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11161 | "" | |
11162 | "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }") | |
11163 | ||
11164 | (define_expand "sunle" | |
11165 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11166 | "" | |
11167 | "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }") | |
11168 | ||
11169 | (define_expand "sunlt" | |
11170 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11171 | "" | |
11172 | "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }") | |
11173 | ||
11174 | (define_expand "sltgt" | |
11175 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
11176 | "" | |
11177 | "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }") | |
11178 | ||
1fd4e8c1 RK |
11179 | \f |
11180 | ;; Here are the actual compare insns. | |
acad7ed3 | 11181 | (define_insn "*cmpsi_internal1" |
1fd4e8c1 | 11182 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
cd2b37d9 | 11183 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
11184 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
11185 | "" | |
7f340546 | 11186 | "{cmp%I2|cmpw%I2} %0,%1,%2" |
b54cf83a | 11187 | [(set_attr "type" "cmp")]) |
1fd4e8c1 | 11188 | |
acad7ed3 | 11189 | (define_insn "*cmpdi_internal1" |
266eb58a DE |
11190 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
11191 | (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r") | |
11192 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
11193 | "TARGET_POWERPC64" | |
11194 | "cmpd%I2 %0,%1,%2" | |
b54cf83a | 11195 | [(set_attr "type" "cmp")]) |
266eb58a | 11196 | |
f357808b RK |
11197 | ;; If we are comparing a register for equality with a large constant, |
11198 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
11199 | ;; register for the result of the XOR. | |
11200 | ||
11201 | (define_split | |
11202 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 11203 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 11204 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 11205 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
11206 | "find_single_use (operands[0], insn, 0) |
11207 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
11208 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
11209 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
11210 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
11211 | " | |
11212 | { | |
11213 | /* Get the constant we are comparing against, C, and see what it looks like | |
11214 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
11215 | with C to get the sign-extended value. */ | |
11216 | ||
5f59ecb7 | 11217 | HOST_WIDE_INT c = INTVAL (operands[2]); |
a65c591c | 11218 | HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000; |
5f59ecb7 | 11219 | HOST_WIDE_INT xorv = c ^ sextc; |
f357808b | 11220 | |
89e9f3a8 MM |
11221 | operands[4] = GEN_INT (xorv); |
11222 | operands[5] = GEN_INT (sextc); | |
f357808b RK |
11223 | }") |
11224 | ||
acad7ed3 | 11225 | (define_insn "*cmpsi_internal2" |
1fd4e8c1 | 11226 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
cd2b37d9 | 11227 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
9ebbca7d | 11228 | (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] |
1fd4e8c1 | 11229 | "" |
e2c953b6 | 11230 | "{cmpl%I2|cmplw%I2} %0,%1,%b2" |
b54cf83a | 11231 | [(set_attr "type" "cmp")]) |
1fd4e8c1 | 11232 | |
acad7ed3 | 11233 | (define_insn "*cmpdi_internal2" |
266eb58a DE |
11234 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
11235 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
9ebbca7d | 11236 | (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] |
266eb58a | 11237 | "" |
e2c953b6 | 11238 | "cmpld%I2 %0,%1,%b2" |
b54cf83a | 11239 | [(set_attr "type" "cmp")]) |
266eb58a | 11240 | |
1fd4e8c1 RK |
11241 | ;; The following two insns don't exist as single insns, but if we provide |
11242 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
11243 | ;; of the required delay between a compare and branch. We generate code for | |
11244 | ;; them by splitting. | |
11245 | ||
11246 | (define_insn "" | |
11247 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 11248 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11249 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 11250 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11251 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
11252 | "" | |
baf97f86 RK |
11253 | "#" |
11254 | [(set_attr "length" "8")]) | |
7e69e155 | 11255 | |
1fd4e8c1 RK |
11256 | (define_insn "" |
11257 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 11258 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11259 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 11260 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11261 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
11262 | "" | |
baf97f86 RK |
11263 | "#" |
11264 | [(set_attr "length" "8")]) | |
7e69e155 | 11265 | |
1fd4e8c1 RK |
11266 | (define_split |
11267 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 11268 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11269 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 11270 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
11271 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
11272 | "" | |
11273 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
11274 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
11275 | ||
11276 | (define_split | |
11277 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 11278 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 11279 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 11280 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
11281 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
11282 | "" | |
11283 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
11284 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
11285 | ||
acad7ed3 | 11286 | (define_insn "*cmpsf_internal1" |
1fd4e8c1 | 11287 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
11288 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
11289 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 11290 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
11291 | "fcmpu %0,%1,%2" |
11292 | [(set_attr "type" "fpcompare")]) | |
11293 | ||
acad7ed3 | 11294 | (define_insn "*cmpdf_internal1" |
1fd4e8c1 | 11295 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
11296 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
11297 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 11298 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
11299 | "fcmpu %0,%1,%2" |
11300 | [(set_attr "type" "fpcompare")]) | |
d6f99ca4 DE |
11301 | |
11302 | ;; Only need to compare second words if first words equal | |
11303 | (define_insn "*cmptf_internal1" | |
11304 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
11305 | (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") | |
11306 | (match_operand:TF 2 "gpc_reg_operand" "f")))] | |
39e63627 GK |
11307 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
11308 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
ecb62ae7 | 11309 | "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2" |
d6f99ca4 DE |
11310 | [(set_attr "type" "fpcompare") |
11311 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
11312 | \f |
11313 | ;; Now we have the scc insns. We can do some combinations because of the | |
11314 | ;; way the machine works. | |
11315 | ;; | |
11316 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
11317 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
11318 | ;; cases the insns below which don't use an intermediate CR field will | |
11319 | ;; be used instead. | |
1fd4e8c1 | 11320 | (define_insn "" |
cd2b37d9 | 11321 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11322 | (match_operator:SI 1 "scc_comparison_operator" |
11323 | [(match_operand 2 "cc_reg_operand" "y") | |
11324 | (const_int 0)]))] | |
11325 | "" | |
2c4a9cff DE |
11326 | "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" |
11327 | [(set (attr "type") | |
11328 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
11329 | (const_string "mfcrf") | |
11330 | ] | |
11331 | (const_string "mfcr"))) | |
c1618c0c | 11332 | (set_attr "length" "8")]) |
1fd4e8c1 | 11333 | |
423c1189 | 11334 | ;; Same as above, but get the GT bit. |
6b1fedc3 | 11335 | (define_insn "move_from_CR_eq_bit" |
423c1189 | 11336 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
6b1fedc3 | 11337 | (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_EQ))] |
423c1189 AH |
11338 | "TARGET_E500" |
11339 | "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,1" | |
11340 | [(set_attr "type" "mfcr") | |
c1618c0c | 11341 | (set_attr "length" "8")]) |
423c1189 | 11342 | |
a3170dc6 AH |
11343 | ;; Same as above, but get the OV/ORDERED bit. |
11344 | (define_insn "move_from_CR_ov_bit" | |
11345 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
615158e2 | 11346 | (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))] |
a3170dc6 | 11347 | "TARGET_ISEL" |
b7053a3f | 11348 | "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1" |
b54cf83a | 11349 | [(set_attr "type" "mfcr") |
c1618c0c | 11350 | (set_attr "length" "8")]) |
a3170dc6 | 11351 | |
1fd4e8c1 | 11352 | (define_insn "" |
9ebbca7d GK |
11353 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
11354 | (match_operator:DI 1 "scc_comparison_operator" | |
11355 | [(match_operand 2 "cc_reg_operand" "y") | |
11356 | (const_int 0)]))] | |
11357 | "TARGET_POWERPC64" | |
2c4a9cff DE |
11358 | "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" |
11359 | [(set (attr "type") | |
11360 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
11361 | (const_string "mfcrf") | |
11362 | ] | |
11363 | (const_string "mfcr"))) | |
c1618c0c | 11364 | (set_attr "length" "8")]) |
9ebbca7d GK |
11365 | |
11366 | (define_insn "" | |
11367 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 11368 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" |
9ebbca7d | 11369 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 RK |
11370 | (const_int 0)]) |
11371 | (const_int 0))) | |
9ebbca7d | 11372 | (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11373 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
4b8a63d6 | 11374 | "TARGET_32BIT" |
9ebbca7d | 11375 | "@ |
2c4a9cff | 11376 | mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1 |
9ebbca7d | 11377 | #" |
b19003d8 | 11378 | [(set_attr "type" "delayed_compare") |
c1618c0c | 11379 | (set_attr "length" "8,16")]) |
9ebbca7d GK |
11380 | |
11381 | (define_split | |
11382 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11383 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
11384 | [(match_operand 2 "cc_reg_operand" "") | |
11385 | (const_int 0)]) | |
11386 | (const_int 0))) | |
11387 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
11388 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] | |
4b8a63d6 | 11389 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11390 | [(set (match_dup 3) |
11391 | (match_op_dup 1 [(match_dup 2) (const_int 0)])) | |
11392 | (set (match_dup 0) | |
11393 | (compare:CC (match_dup 3) | |
11394 | (const_int 0)))] | |
11395 | "") | |
1fd4e8c1 RK |
11396 | |
11397 | (define_insn "" | |
cd2b37d9 | 11398 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11399 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
11400 | [(match_operand 2 "cc_reg_operand" "y") | |
11401 | (const_int 0)]) | |
11402 | (match_operand:SI 3 "const_int_operand" "n")))] | |
11403 | "" | |
11404 | "* | |
11405 | { | |
11406 | int is_bit = ccr_bit (operands[1], 1); | |
11407 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11408 | int count; | |
11409 | ||
11410 | if (is_bit >= put_bit) | |
11411 | count = is_bit - put_bit; | |
11412 | else | |
11413 | count = 32 - (put_bit - is_bit); | |
11414 | ||
89e9f3a8 MM |
11415 | operands[4] = GEN_INT (count); |
11416 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 11417 | |
2c4a9cff | 11418 | return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 | 11419 | }" |
2c4a9cff DE |
11420 | [(set (attr "type") |
11421 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
11422 | (const_string "mfcrf") | |
11423 | ] | |
11424 | (const_string "mfcr"))) | |
c1618c0c | 11425 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
11426 | |
11427 | (define_insn "" | |
9ebbca7d | 11428 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11429 | (compare:CC |
11430 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
9ebbca7d | 11431 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 | 11432 | (const_int 0)]) |
9ebbca7d | 11433 | (match_operand:SI 3 "const_int_operand" "n,n")) |
1fd4e8c1 | 11434 | (const_int 0))) |
9ebbca7d | 11435 | (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11436 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
11437 | (match_dup 3)))] | |
ce71f754 | 11438 | "" |
1fd4e8c1 RK |
11439 | "* |
11440 | { | |
11441 | int is_bit = ccr_bit (operands[1], 1); | |
11442 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11443 | int count; | |
11444 | ||
9ebbca7d GK |
11445 | /* Force split for non-cc0 compare. */ |
11446 | if (which_alternative == 1) | |
11447 | return \"#\"; | |
11448 | ||
1fd4e8c1 RK |
11449 | if (is_bit >= put_bit) |
11450 | count = is_bit - put_bit; | |
11451 | else | |
11452 | count = 32 - (put_bit - is_bit); | |
11453 | ||
89e9f3a8 MM |
11454 | operands[5] = GEN_INT (count); |
11455 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 11456 | |
2c4a9cff | 11457 | return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 11458 | }" |
b19003d8 | 11459 | [(set_attr "type" "delayed_compare") |
c1618c0c | 11460 | (set_attr "length" "8,16")]) |
9ebbca7d GK |
11461 | |
11462 | (define_split | |
11463 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11464 | (compare:CC | |
11465 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
11466 | [(match_operand 2 "cc_reg_operand" "") | |
11467 | (const_int 0)]) | |
11468 | (match_operand:SI 3 "const_int_operand" "")) | |
11469 | (const_int 0))) | |
11470 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
11471 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11472 | (match_dup 3)))] | |
ce71f754 | 11473 | "reload_completed" |
9ebbca7d GK |
11474 | [(set (match_dup 4) |
11475 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11476 | (match_dup 3))) | |
11477 | (set (match_dup 0) | |
11478 | (compare:CC (match_dup 4) | |
11479 | (const_int 0)))] | |
11480 | "") | |
1fd4e8c1 | 11481 | |
c5defebb RK |
11482 | ;; There is a 3 cycle delay between consecutive mfcr instructions |
11483 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
11484 | ||
11485 | (define_peephole | |
cd2b37d9 | 11486 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
11487 | (match_operator:SI 1 "scc_comparison_operator" |
11488 | [(match_operand 2 "cc_reg_operand" "y") | |
11489 | (const_int 0)])) | |
cd2b37d9 | 11490 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
11491 | (match_operator:SI 4 "scc_comparison_operator" |
11492 | [(match_operand 5 "cc_reg_operand" "y") | |
11493 | (const_int 0)]))] | |
309323c2 | 11494 | "REGNO (operands[2]) != REGNO (operands[5])" |
b7053a3f | 11495 | "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b54cf83a | 11496 | [(set_attr "type" "mfcr") |
c1618c0c | 11497 | (set_attr "length" "12")]) |
c5defebb | 11498 | |
9ebbca7d GK |
11499 | (define_peephole |
11500 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11501 | (match_operator:DI 1 "scc_comparison_operator" | |
11502 | [(match_operand 2 "cc_reg_operand" "y") | |
11503 | (const_int 0)])) | |
11504 | (set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
11505 | (match_operator:DI 4 "scc_comparison_operator" | |
11506 | [(match_operand 5 "cc_reg_operand" "y") | |
11507 | (const_int 0)]))] | |
309323c2 | 11508 | "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" |
b7053a3f | 11509 | "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b54cf83a | 11510 | [(set_attr "type" "mfcr") |
c1618c0c | 11511 | (set_attr "length" "12")]) |
9ebbca7d | 11512 | |
1fd4e8c1 RK |
11513 | ;; There are some scc insns that can be done directly, without a compare. |
11514 | ;; These are faster because they don't involve the communications between | |
11515 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
11516 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
11517 | ;; | |
11518 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
11519 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
11520 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
11521 | ;; cases where it is no more expensive than (neg (scc ..)). | |
11522 | ||
11523 | ;; Have reload force a constant into a register for the simple insns that | |
11524 | ;; otherwise won't accept constants. We do this because it is faster than | |
11525 | ;; the cmp/mfcr sequence we would otherwise generate. | |
11526 | ||
11527 | (define_insn "" | |
cd2b37d9 RK |
11528 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
11529 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
5f59ecb7 | 11530 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))) |
1fd4e8c1 | 11531 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] |
683bdff7 | 11532 | "TARGET_32BIT" |
1fd4e8c1 | 11533 | "@ |
ca7f5001 | 11534 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
71d2371f | 11535 | {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1 |
ca7f5001 RK |
11536 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 |
11537 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0 | |
11538 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0" | |
b19003d8 | 11539 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 11540 | |
a260abc9 DE |
11541 | (define_insn "" |
11542 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") | |
11543 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") | |
11544 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I"))) | |
11545 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))] | |
683bdff7 | 11546 | "TARGET_64BIT" |
a260abc9 DE |
11547 | "@ |
11548 | xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11549 | subfic %3,%1,0\;adde %0,%3,%1 | |
11550 | xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11551 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0 | |
11552 | subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0" | |
11553 | [(set_attr "length" "12,8,12,12,12")]) | |
11554 | ||
1fd4e8c1 | 11555 | (define_insn "" |
9ebbca7d | 11556 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11557 | (compare:CC |
9ebbca7d GK |
11558 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11559 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
1fd4e8c1 | 11560 | (const_int 0))) |
9ebbca7d | 11561 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
1fd4e8c1 | 11562 | (eq:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11563 | (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
683bdff7 | 11564 | "TARGET_32BIT" |
1fd4e8c1 | 11565 | "@ |
ca7f5001 RK |
11566 | xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
11567 | {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1 | |
11568 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
11569 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 | |
9ebbca7d GK |
11570 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0 |
11571 | # | |
11572 | # | |
11573 | # | |
11574 | # | |
11575 | #" | |
b19003d8 | 11576 | [(set_attr "type" "compare") |
9ebbca7d GK |
11577 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11578 | ||
11579 | (define_split | |
11580 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11581 | (compare:CC | |
11582 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11583 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11584 | (const_int 0))) | |
11585 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11586 | (eq:SI (match_dup 1) (match_dup 2))) | |
11587 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 11588 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11589 | [(parallel [(set (match_dup 0) |
11590 | (eq:SI (match_dup 1) (match_dup 2))) | |
11591 | (clobber (match_dup 3))]) | |
11592 | (set (match_dup 4) | |
11593 | (compare:CC (match_dup 0) | |
11594 | (const_int 0)))] | |
11595 | "") | |
b19003d8 | 11596 | |
a260abc9 | 11597 | (define_insn "" |
9ebbca7d | 11598 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
a260abc9 | 11599 | (compare:CC |
9ebbca7d GK |
11600 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11601 | (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I")) | |
a260abc9 | 11602 | (const_int 0))) |
9ebbca7d | 11603 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
a260abc9 | 11604 | (eq:DI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11605 | (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))] |
683bdff7 | 11606 | "TARGET_64BIT" |
a260abc9 DE |
11607 | "@ |
11608 | xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
11609 | subfic %3,%1,0\;adde. %0,%3,%1 | |
11610 | xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
11611 | xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0 | |
9ebbca7d GK |
11612 | subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0 |
11613 | # | |
11614 | # | |
11615 | # | |
11616 | # | |
11617 | #" | |
a260abc9 | 11618 | [(set_attr "type" "compare") |
9ebbca7d GK |
11619 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11620 | ||
11621 | (define_split | |
11622 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11623 | (compare:CC | |
11624 | (eq:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11625 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
11626 | (const_int 0))) | |
11627 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11628 | (eq:DI (match_dup 1) (match_dup 2))) | |
11629 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 11630 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11631 | [(parallel [(set (match_dup 0) |
11632 | (eq:DI (match_dup 1) (match_dup 2))) | |
11633 | (clobber (match_dup 3))]) | |
11634 | (set (match_dup 4) | |
11635 | (compare:CC (match_dup 0) | |
11636 | (const_int 0)))] | |
11637 | "") | |
a260abc9 | 11638 | |
b19003d8 RK |
11639 | ;; We have insns of the form shown by the first define_insn below. If |
11640 | ;; there is something inside the comparison operation, we must split it. | |
11641 | (define_split | |
11642 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
11643 | (plus:SI (match_operator 1 "comparison_operator" | |
11644 | [(match_operand:SI 2 "" "") | |
11645 | (match_operand:SI 3 | |
11646 | "reg_or_cint_operand" "")]) | |
11647 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
11648 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
11649 | "! gpc_reg_operand (operands[2], SImode)" | |
11650 | [(set (match_dup 5) (match_dup 2)) | |
11651 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
11652 | (match_dup 4)))]) | |
1fd4e8c1 RK |
11653 | |
11654 | (define_insn "" | |
5276df18 | 11655 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r") |
cd2b37d9 | 11656 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 11657 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")) |
5276df18 | 11658 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))] |
683bdff7 | 11659 | "TARGET_32BIT" |
1fd4e8c1 | 11660 | "@ |
5276df18 DE |
11661 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
11662 | {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3 | |
11663 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11664 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11665 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" | |
b19003d8 | 11666 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 RK |
11667 | |
11668 | (define_insn "" | |
9ebbca7d | 11669 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11670 | (compare:CC |
1fd4e8c1 | 11671 | (plus:SI |
9ebbca7d GK |
11672 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11673 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
11674 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 11675 | (const_int 0))) |
9ebbca7d | 11676 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
683bdff7 | 11677 | "TARGET_32BIT" |
1fd4e8c1 | 11678 | "@ |
ca7f5001 | 11679 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 11680 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
11681 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11682 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
9ebbca7d GK |
11683 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11684 | # | |
11685 | # | |
11686 | # | |
11687 | # | |
11688 | #" | |
b19003d8 | 11689 | [(set_attr "type" "compare") |
9ebbca7d GK |
11690 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11691 | ||
11692 | (define_split | |
11693 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11694 | (compare:CC | |
11695 | (plus:SI | |
11696 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11697 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11698 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11699 | (const_int 0))) | |
11700 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 11701 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11702 | [(set (match_dup 4) |
11703 | (plus:SI (eq:SI (match_dup 1) | |
11704 | (match_dup 2)) | |
11705 | (match_dup 3))) | |
11706 | (set (match_dup 0) | |
11707 | (compare:CC (match_dup 4) | |
11708 | (const_int 0)))] | |
11709 | "") | |
1fd4e8c1 RK |
11710 | |
11711 | (define_insn "" | |
0387639b | 11712 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11713 | (compare:CC |
1fd4e8c1 | 11714 | (plus:SI |
9ebbca7d GK |
11715 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
11716 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I")) | |
11717 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) | |
1fd4e8c1 | 11718 | (const_int 0))) |
0387639b DE |
11719 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r") |
11720 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 11721 | "TARGET_32BIT" |
1fd4e8c1 | 11722 | "@ |
0387639b DE |
11723 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
11724 | {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3 | |
11725 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11726 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11727 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
11728 | # |
11729 | # | |
11730 | # | |
11731 | # | |
11732 | #" | |
11733 | [(set_attr "type" "compare") | |
11734 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) | |
11735 | ||
11736 | (define_split | |
0387639b | 11737 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11738 | (compare:CC |
11739 | (plus:SI | |
11740 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11741 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
11742 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11743 | (const_int 0))) | |
11744 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
0387639b | 11745 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 11746 | "TARGET_32BIT && reload_completed" |
0387639b | 11747 | [(set (match_dup 0) |
9ebbca7d | 11748 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
0387639b | 11749 | (set (match_dup 4) |
9ebbca7d GK |
11750 | (compare:CC (match_dup 0) |
11751 | (const_int 0)))] | |
11752 | "") | |
11753 | ||
1fd4e8c1 | 11754 | (define_insn "" |
cd2b37d9 | 11755 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 11756 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
5f59ecb7 | 11757 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))] |
683bdff7 | 11758 | "TARGET_32BIT" |
1fd4e8c1 | 11759 | "@ |
ca7f5001 RK |
11760 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
11761 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
11762 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11763 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11764 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 11765 | [(set_attr "length" "12,8,12,12,12")]) |
1fd4e8c1 | 11766 | |
ea9be077 MM |
11767 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
11768 | ;; since it nabs/sr is just as fast. | |
463b558b | 11769 | (define_insn "*ne0" |
b4e95693 | 11770 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
11771 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
11772 | (const_int 31))) | |
11773 | (clobber (match_scratch:SI 2 "=&r"))] | |
683bdff7 | 11774 | "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL" |
ea9be077 MM |
11775 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" |
11776 | [(set_attr "length" "8")]) | |
11777 | ||
a260abc9 DE |
11778 | (define_insn "" |
11779 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11780 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11781 | (const_int 63))) | |
11782 | (clobber (match_scratch:DI 2 "=&r"))] | |
683bdff7 | 11783 | "TARGET_64BIT" |
a260abc9 DE |
11784 | "addic %2,%1,-1\;subfe %0,%2,%1" |
11785 | [(set_attr "length" "8")]) | |
11786 | ||
1fd4e8c1 RK |
11787 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
11788 | (define_insn "" | |
cd2b37d9 | 11789 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 11790 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 11791 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11792 | (const_int 31)) |
cd2b37d9 | 11793 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11794 | (clobber (match_scratch:SI 3 "=&r"))] |
683bdff7 | 11795 | "TARGET_32BIT" |
ca7f5001 | 11796 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
b19003d8 | 11797 | [(set_attr "length" "8")]) |
1fd4e8c1 | 11798 | |
a260abc9 DE |
11799 | (define_insn "" |
11800 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11801 | (plus:DI (lshiftrt:DI | |
11802 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11803 | (const_int 63)) | |
11804 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
11805 | (clobber (match_scratch:DI 3 "=&r"))] | |
683bdff7 | 11806 | "TARGET_64BIT" |
a260abc9 DE |
11807 | "addic %3,%1,-1\;addze %0,%2" |
11808 | [(set_attr "length" "8")]) | |
11809 | ||
1fd4e8c1 | 11810 | (define_insn "" |
9ebbca7d | 11811 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11812 | (compare:CC |
11813 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11814 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11815 | (const_int 31)) |
9ebbca7d | 11816 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11817 | (const_int 0))) |
889b90a1 GK |
11818 | (clobber (match_scratch:SI 3 "=&r,&r")) |
11819 | (clobber (match_scratch:SI 4 "=X,&r"))] | |
683bdff7 | 11820 | "TARGET_32BIT" |
9ebbca7d GK |
11821 | "@ |
11822 | {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 | |
11823 | #" | |
b19003d8 | 11824 | [(set_attr "type" "compare") |
9ebbca7d GK |
11825 | (set_attr "length" "8,12")]) |
11826 | ||
11827 | (define_split | |
11828 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11829 | (compare:CC | |
11830 | (plus:SI (lshiftrt:SI | |
11831 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11832 | (const_int 31)) | |
11833 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11834 | (const_int 0))) | |
889b90a1 GK |
11835 | (clobber (match_scratch:SI 3 "")) |
11836 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 11837 | "TARGET_32BIT && reload_completed" |
889b90a1 | 11838 | [(parallel [(set (match_dup 3) |
ce71f754 AM |
11839 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) |
11840 | (const_int 31)) | |
11841 | (match_dup 2))) | |
889b90a1 | 11842 | (clobber (match_dup 4))]) |
9ebbca7d GK |
11843 | (set (match_dup 0) |
11844 | (compare:CC (match_dup 3) | |
11845 | (const_int 0)))] | |
11846 | "") | |
1fd4e8c1 | 11847 | |
a260abc9 | 11848 | (define_insn "" |
9ebbca7d | 11849 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11850 | (compare:CC |
11851 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11852 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11853 | (const_int 63)) |
9ebbca7d | 11854 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11855 | (const_int 0))) |
9ebbca7d | 11856 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 11857 | "TARGET_64BIT" |
9ebbca7d GK |
11858 | "@ |
11859 | addic %3,%1,-1\;addze. %3,%2 | |
11860 | #" | |
a260abc9 | 11861 | [(set_attr "type" "compare") |
9ebbca7d GK |
11862 | (set_attr "length" "8,12")]) |
11863 | ||
11864 | (define_split | |
11865 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11866 | (compare:CC | |
11867 | (plus:DI (lshiftrt:DI | |
11868 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11869 | (const_int 63)) | |
11870 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11871 | (const_int 0))) | |
11872 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 11873 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11874 | [(set (match_dup 3) |
11875 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) | |
11876 | (const_int 63)) | |
11877 | (match_dup 2))) | |
11878 | (set (match_dup 0) | |
11879 | (compare:CC (match_dup 3) | |
11880 | (const_int 0)))] | |
11881 | "") | |
a260abc9 | 11882 | |
1fd4e8c1 | 11883 | (define_insn "" |
9ebbca7d | 11884 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11885 | (compare:CC |
11886 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11887 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11888 | (const_int 31)) |
9ebbca7d | 11889 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11890 | (const_int 0))) |
9ebbca7d | 11891 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11892 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
11893 | (match_dup 2))) | |
9ebbca7d | 11894 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
683bdff7 | 11895 | "TARGET_32BIT" |
9ebbca7d GK |
11896 | "@ |
11897 | {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 | |
11898 | #" | |
b19003d8 | 11899 | [(set_attr "type" "compare") |
9ebbca7d GK |
11900 | (set_attr "length" "8,12")]) |
11901 | ||
11902 | (define_split | |
11903 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11904 | (compare:CC | |
11905 | (plus:SI (lshiftrt:SI | |
11906 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11907 | (const_int 31)) | |
11908 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11909 | (const_int 0))) | |
11910 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11911 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11912 | (match_dup 2))) | |
11913 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 11914 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11915 | [(parallel [(set (match_dup 0) |
11916 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11917 | (match_dup 2))) | |
11918 | (clobber (match_dup 3))]) | |
11919 | (set (match_dup 4) | |
11920 | (compare:CC (match_dup 0) | |
11921 | (const_int 0)))] | |
11922 | "") | |
1fd4e8c1 | 11923 | |
a260abc9 | 11924 | (define_insn "" |
9ebbca7d | 11925 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11926 | (compare:CC |
11927 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11928 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11929 | (const_int 63)) |
9ebbca7d | 11930 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11931 | (const_int 0))) |
9ebbca7d | 11932 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
11933 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
11934 | (match_dup 2))) | |
9ebbca7d | 11935 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 11936 | "TARGET_64BIT" |
9ebbca7d GK |
11937 | "@ |
11938 | addic %3,%1,-1\;addze. %0,%2 | |
11939 | #" | |
a260abc9 | 11940 | [(set_attr "type" "compare") |
9ebbca7d GK |
11941 | (set_attr "length" "8,12")]) |
11942 | ||
11943 | (define_split | |
11944 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11945 | (compare:CC | |
11946 | (plus:DI (lshiftrt:DI | |
11947 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11948 | (const_int 63)) | |
11949 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11950 | (const_int 0))) | |
11951 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11952 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11953 | (match_dup 2))) | |
11954 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 11955 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11956 | [(parallel [(set (match_dup 0) |
11957 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11958 | (match_dup 2))) | |
11959 | (clobber (match_dup 3))]) | |
11960 | (set (match_dup 4) | |
11961 | (compare:CC (match_dup 0) | |
11962 | (const_int 0)))] | |
11963 | "") | |
a260abc9 | 11964 | |
1fd4e8c1 | 11965 | (define_insn "" |
cd2b37d9 RK |
11966 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11967 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
11968 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
11969 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 11970 | "TARGET_POWER" |
1fd4e8c1 | 11971 | "@ |
ca7f5001 | 11972 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 11973 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11974 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11975 | |
11976 | (define_insn "" | |
9ebbca7d | 11977 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11978 | (compare:CC |
9ebbca7d GK |
11979 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11980 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
1fd4e8c1 | 11981 | (const_int 0))) |
9ebbca7d | 11982 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11983 | (le:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11984 | (clobber (match_scratch:SI 3 "=r,X,r,X"))] |
ca7f5001 | 11985 | "TARGET_POWER" |
1fd4e8c1 | 11986 | "@ |
ca7f5001 | 11987 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
9ebbca7d GK |
11988 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 |
11989 | # | |
11990 | #" | |
11991 | [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") | |
11992 | (set_attr "length" "12,12,16,16")]) | |
11993 | ||
11994 | (define_split | |
11995 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11996 | (compare:CC | |
11997 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11998 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11999 | (const_int 0))) | |
12000 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12001 | (le:SI (match_dup 1) (match_dup 2))) | |
12002 | (clobber (match_scratch:SI 3 ""))] | |
12003 | "TARGET_POWER && reload_completed" | |
12004 | [(parallel [(set (match_dup 0) | |
12005 | (le:SI (match_dup 1) (match_dup 2))) | |
12006 | (clobber (match_dup 3))]) | |
12007 | (set (match_dup 4) | |
12008 | (compare:CC (match_dup 0) | |
12009 | (const_int 0)))] | |
12010 | "") | |
1fd4e8c1 RK |
12011 | |
12012 | (define_insn "" | |
097657c3 | 12013 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 12014 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12015 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
097657c3 | 12016 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
ca7f5001 | 12017 | "TARGET_POWER" |
1fd4e8c1 | 12018 | "@ |
097657c3 AM |
12019 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
12020 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3" | |
b19003d8 | 12021 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12022 | |
12023 | (define_insn "" | |
9ebbca7d | 12024 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12025 | (compare:CC |
9ebbca7d GK |
12026 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12027 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
12028 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12029 | (const_int 0))) |
9ebbca7d | 12030 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 12031 | "TARGET_POWER" |
1fd4e8c1 | 12032 | "@ |
ca7f5001 | 12033 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12034 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 |
12035 | # | |
12036 | #" | |
b19003d8 | 12037 | [(set_attr "type" "compare") |
9ebbca7d GK |
12038 | (set_attr "length" "12,12,16,16")]) |
12039 | ||
12040 | (define_split | |
12041 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12042 | (compare:CC | |
12043 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12044 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12045 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12046 | (const_int 0))) | |
12047 | (clobber (match_scratch:SI 4 ""))] | |
12048 | "TARGET_POWER && reload_completed" | |
12049 | [(set (match_dup 4) | |
12050 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12051 | (match_dup 3))) |
9ebbca7d GK |
12052 | (set (match_dup 0) |
12053 | (compare:CC (match_dup 4) | |
12054 | (const_int 0)))] | |
12055 | "") | |
1fd4e8c1 RK |
12056 | |
12057 | (define_insn "" | |
097657c3 | 12058 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12059 | (compare:CC |
9ebbca7d GK |
12060 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12061 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
12062 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12063 | (const_int 0))) |
097657c3 AM |
12064 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12065 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12066 | "TARGET_POWER" |
1fd4e8c1 | 12067 | "@ |
097657c3 AM |
12068 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
12069 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
12070 | # |
12071 | #" | |
b19003d8 | 12072 | [(set_attr "type" "compare") |
9ebbca7d GK |
12073 | (set_attr "length" "12,12,16,16")]) |
12074 | ||
12075 | (define_split | |
097657c3 | 12076 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12077 | (compare:CC |
12078 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12079 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12080 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12081 | (const_int 0))) | |
12082 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12083 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12084 | "TARGET_POWER && reload_completed" |
097657c3 | 12085 | [(set (match_dup 0) |
9ebbca7d | 12086 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12087 | (set (match_dup 4) |
9ebbca7d GK |
12088 | (compare:CC (match_dup 0) |
12089 | (const_int 0)))] | |
12090 | "") | |
1fd4e8c1 RK |
12091 | |
12092 | (define_insn "" | |
cd2b37d9 RK |
12093 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12094 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12095 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 12096 | "TARGET_POWER" |
1fd4e8c1 | 12097 | "@ |
ca7f5001 RK |
12098 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
12099 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12100 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12101 | |
12102 | (define_insn "" | |
cd2b37d9 RK |
12103 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12104 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12105 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
4b8a63d6 | 12106 | "TARGET_32BIT" |
ca7f5001 | 12107 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
b19003d8 | 12108 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12109 | |
f9562f27 DE |
12110 | (define_insn "" |
12111 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12112 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12113 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
683bdff7 | 12114 | "TARGET_64BIT" |
f9562f27 DE |
12115 | "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" |
12116 | [(set_attr "length" "12")]) | |
12117 | ||
12118 | (define_insn "" | |
9ebbca7d | 12119 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 12120 | (compare:CC |
9ebbca7d GK |
12121 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
12122 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 12123 | (const_int 0))) |
9ebbca7d | 12124 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 12125 | (leu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12126 | "TARGET_64BIT" |
9ebbca7d GK |
12127 | "@ |
12128 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
12129 | #" | |
f9562f27 | 12130 | [(set_attr "type" "compare") |
9ebbca7d GK |
12131 | (set_attr "length" "12,16")]) |
12132 | ||
12133 | (define_split | |
12134 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12135 | (compare:CC | |
12136 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12137 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
12138 | (const_int 0))) | |
12139 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12140 | (leu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12141 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
12142 | [(set (match_dup 0) |
12143 | (leu:DI (match_dup 1) (match_dup 2))) | |
12144 | (set (match_dup 3) | |
12145 | (compare:CC (match_dup 0) | |
12146 | (const_int 0)))] | |
12147 | "") | |
f9562f27 | 12148 | |
1fd4e8c1 | 12149 | (define_insn "" |
9ebbca7d | 12150 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12151 | (compare:CC |
9ebbca7d GK |
12152 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12153 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12154 | (const_int 0))) |
9ebbca7d | 12155 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12156 | (leu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12157 | "TARGET_32BIT" |
9ebbca7d GK |
12158 | "@ |
12159 | {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 | |
12160 | #" | |
b19003d8 | 12161 | [(set_attr "type" "compare") |
9ebbca7d GK |
12162 | (set_attr "length" "12,16")]) |
12163 | ||
12164 | (define_split | |
12165 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12166 | (compare:CC | |
12167 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12168 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12169 | (const_int 0))) | |
12170 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12171 | (leu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12172 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12173 | [(set (match_dup 0) |
12174 | (leu:SI (match_dup 1) (match_dup 2))) | |
12175 | (set (match_dup 3) | |
12176 | (compare:CC (match_dup 0) | |
12177 | (const_int 0)))] | |
12178 | "") | |
1fd4e8c1 RK |
12179 | |
12180 | (define_insn "" | |
80103f96 | 12181 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12182 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12183 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
80103f96 | 12184 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
683bdff7 | 12185 | "TARGET_32BIT" |
80103f96 | 12186 | "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3" |
b19003d8 | 12187 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
12188 | |
12189 | (define_insn "" | |
9ebbca7d | 12190 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12191 | (compare:CC |
9ebbca7d GK |
12192 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12193 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12194 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12195 | (const_int 0))) |
9ebbca7d | 12196 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
683bdff7 | 12197 | "TARGET_32BIT" |
9ebbca7d GK |
12198 | "@ |
12199 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 | |
12200 | #" | |
b19003d8 | 12201 | [(set_attr "type" "compare") |
9ebbca7d GK |
12202 | (set_attr "length" "8,12")]) |
12203 | ||
12204 | (define_split | |
12205 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12206 | (compare:CC | |
12207 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12208 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12209 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12210 | (const_int 0))) | |
12211 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12212 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12213 | [(set (match_dup 4) |
12214 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) | |
12215 | (match_dup 3))) | |
12216 | (set (match_dup 0) | |
12217 | (compare:CC (match_dup 4) | |
12218 | (const_int 0)))] | |
12219 | "") | |
1fd4e8c1 RK |
12220 | |
12221 | (define_insn "" | |
097657c3 | 12222 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12223 | (compare:CC |
9ebbca7d GK |
12224 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12225 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12226 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12227 | (const_int 0))) |
097657c3 AM |
12228 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12229 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 12230 | "TARGET_32BIT" |
9ebbca7d | 12231 | "@ |
097657c3 | 12232 | {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3 |
9ebbca7d | 12233 | #" |
b19003d8 | 12234 | [(set_attr "type" "compare") |
9ebbca7d GK |
12235 | (set_attr "length" "8,12")]) |
12236 | ||
12237 | (define_split | |
097657c3 | 12238 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12239 | (compare:CC |
12240 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12241 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12242 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12243 | (const_int 0))) | |
12244 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12245 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 12246 | "TARGET_32BIT && reload_completed" |
097657c3 | 12247 | [(set (match_dup 0) |
9ebbca7d | 12248 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12249 | (set (match_dup 4) |
9ebbca7d GK |
12250 | (compare:CC (match_dup 0) |
12251 | (const_int 0)))] | |
12252 | "") | |
1fd4e8c1 RK |
12253 | |
12254 | (define_insn "" | |
cd2b37d9 RK |
12255 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12256 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12257 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
683bdff7 | 12258 | "TARGET_32BIT" |
ca7f5001 | 12259 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
b19003d8 | 12260 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12261 | |
12262 | (define_insn "" | |
097657c3 | 12263 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
1fd4e8c1 | 12264 | (and:SI (neg:SI |
cd2b37d9 | 12265 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12266 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
097657c3 | 12267 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
683bdff7 | 12268 | "TARGET_32BIT" |
097657c3 | 12269 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" |
b19003d8 | 12270 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12271 | |
12272 | (define_insn "" | |
9ebbca7d | 12273 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12274 | (compare:CC |
12275 | (and:SI (neg:SI | |
9ebbca7d GK |
12276 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12277 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
12278 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12279 | (const_int 0))) |
9ebbca7d | 12280 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
683bdff7 | 12281 | "TARGET_32BIT" |
9ebbca7d GK |
12282 | "@ |
12283 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 | |
12284 | #" | |
12285 | [(set_attr "type" "compare") | |
12286 | (set_attr "length" "12,16")]) | |
12287 | ||
12288 | (define_split | |
12289 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12290 | (compare:CC | |
12291 | (and:SI (neg:SI | |
12292 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12293 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
12294 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12295 | (const_int 0))) | |
12296 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12297 | "TARGET_32BIT && reload_completed" |
9ebbca7d | 12298 | [(set (match_dup 4) |
097657c3 AM |
12299 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) |
12300 | (match_dup 3))) | |
9ebbca7d GK |
12301 | (set (match_dup 0) |
12302 | (compare:CC (match_dup 4) | |
12303 | (const_int 0)))] | |
12304 | "") | |
1fd4e8c1 RK |
12305 | |
12306 | (define_insn "" | |
097657c3 | 12307 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
12308 | (compare:CC |
12309 | (and:SI (neg:SI | |
9ebbca7d GK |
12310 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12311 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
12312 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12313 | (const_int 0))) |
097657c3 AM |
12314 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12315 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
683bdff7 | 12316 | "TARGET_32BIT" |
9ebbca7d | 12317 | "@ |
097657c3 | 12318 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
9ebbca7d | 12319 | #" |
b19003d8 | 12320 | [(set_attr "type" "compare") |
9ebbca7d GK |
12321 | (set_attr "length" "12,16")]) |
12322 | ||
12323 | (define_split | |
097657c3 | 12324 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12325 | (compare:CC |
12326 | (and:SI (neg:SI | |
12327 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12328 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
12329 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12330 | (const_int 0))) | |
12331 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12332 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
683bdff7 | 12333 | "TARGET_32BIT && reload_completed" |
097657c3 AM |
12334 | [(set (match_dup 0) |
12335 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) | |
12336 | (match_dup 3))) | |
12337 | (set (match_dup 4) | |
9ebbca7d GK |
12338 | (compare:CC (match_dup 0) |
12339 | (const_int 0)))] | |
12340 | "") | |
1fd4e8c1 RK |
12341 | |
12342 | (define_insn "" | |
cd2b37d9 RK |
12343 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12344 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12345 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 12346 | "TARGET_POWER" |
7f340546 | 12347 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 12348 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12349 | |
12350 | (define_insn "" | |
9ebbca7d | 12351 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12352 | (compare:CC |
9ebbca7d GK |
12353 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12354 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12355 | (const_int 0))) |
9ebbca7d | 12356 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12357 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 12358 | "TARGET_POWER" |
9ebbca7d GK |
12359 | "@ |
12360 | doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
12361 | #" | |
29ae5b89 | 12362 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12363 | (set_attr "length" "12,16")]) |
12364 | ||
12365 | (define_split | |
12366 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12367 | (compare:CC | |
12368 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12369 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12370 | (const_int 0))) | |
12371 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12372 | (lt:SI (match_dup 1) (match_dup 2)))] | |
12373 | "TARGET_POWER && reload_completed" | |
12374 | [(set (match_dup 0) | |
12375 | (lt:SI (match_dup 1) (match_dup 2))) | |
12376 | (set (match_dup 3) | |
12377 | (compare:CC (match_dup 0) | |
12378 | (const_int 0)))] | |
12379 | "") | |
1fd4e8c1 RK |
12380 | |
12381 | (define_insn "" | |
097657c3 | 12382 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12383 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12384 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12385 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12386 | "TARGET_POWER" |
097657c3 | 12387 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 12388 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12389 | |
12390 | (define_insn "" | |
9ebbca7d | 12391 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12392 | (compare:CC |
9ebbca7d GK |
12393 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12394 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12395 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12396 | (const_int 0))) |
9ebbca7d | 12397 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12398 | "TARGET_POWER" |
9ebbca7d GK |
12399 | "@ |
12400 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
12401 | #" | |
b19003d8 | 12402 | [(set_attr "type" "compare") |
9ebbca7d GK |
12403 | (set_attr "length" "12,16")]) |
12404 | ||
12405 | (define_split | |
12406 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12407 | (compare:CC | |
12408 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12409 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12410 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12411 | (const_int 0))) | |
12412 | (clobber (match_scratch:SI 4 ""))] | |
12413 | "TARGET_POWER && reload_completed" | |
12414 | [(set (match_dup 4) | |
12415 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12416 | (match_dup 3))) |
9ebbca7d GK |
12417 | (set (match_dup 0) |
12418 | (compare:CC (match_dup 4) | |
12419 | (const_int 0)))] | |
12420 | "") | |
1fd4e8c1 RK |
12421 | |
12422 | (define_insn "" | |
097657c3 | 12423 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12424 | (compare:CC |
9ebbca7d GK |
12425 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12426 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12427 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12428 | (const_int 0))) |
097657c3 AM |
12429 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12430 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12431 | "TARGET_POWER" |
9ebbca7d | 12432 | "@ |
097657c3 | 12433 | doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 12434 | #" |
b19003d8 | 12435 | [(set_attr "type" "compare") |
9ebbca7d GK |
12436 | (set_attr "length" "12,16")]) |
12437 | ||
12438 | (define_split | |
097657c3 | 12439 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12440 | (compare:CC |
12441 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12442 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12443 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12444 | (const_int 0))) | |
12445 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12446 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12447 | "TARGET_POWER && reload_completed" |
097657c3 | 12448 | [(set (match_dup 0) |
9ebbca7d | 12449 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12450 | (set (match_dup 4) |
9ebbca7d GK |
12451 | (compare:CC (match_dup 0) |
12452 | (const_int 0)))] | |
12453 | "") | |
1fd4e8c1 RK |
12454 | |
12455 | (define_insn "" | |
cd2b37d9 RK |
12456 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12457 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12458 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12459 | "TARGET_POWER" |
12460 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12461 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12462 | |
c0600ecd | 12463 | (define_insn_and_split "" |
cd2b37d9 RK |
12464 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12465 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12466 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
683bdff7 | 12467 | "TARGET_32BIT" |
c0600ecd DE |
12468 | "#" |
12469 | "TARGET_32BIT" | |
12470 | [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2)))) | |
12471 | (set (match_dup 0) (neg:SI (match_dup 0)))] | |
12472 | "") | |
12473 | ||
12474 | (define_insn_and_split "" | |
12475 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12476 | (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12477 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
12478 | "TARGET_64BIT" | |
12479 | "#" | |
12480 | "TARGET_64BIT" | |
12481 | [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2)))) | |
12482 | (set (match_dup 0) (neg:DI (match_dup 0)))] | |
12483 | "") | |
1fd4e8c1 RK |
12484 | |
12485 | (define_insn "" | |
9ebbca7d | 12486 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12487 | (compare:CC |
9ebbca7d GK |
12488 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12489 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12490 | (const_int 0))) |
9ebbca7d | 12491 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12492 | (ltu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12493 | "TARGET_32BIT" |
1fd4e8c1 | 12494 | "@ |
ca7f5001 | 12495 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
9ebbca7d GK |
12496 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
12497 | # | |
12498 | #" | |
b19003d8 | 12499 | [(set_attr "type" "compare") |
9ebbca7d GK |
12500 | (set_attr "length" "12,12,16,16")]) |
12501 | ||
12502 | (define_split | |
12503 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12504 | (compare:CC | |
12505 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12506 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12507 | (const_int 0))) | |
12508 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12509 | (ltu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12510 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12511 | [(set (match_dup 0) |
12512 | (ltu:SI (match_dup 1) (match_dup 2))) | |
12513 | (set (match_dup 3) | |
12514 | (compare:CC (match_dup 0) | |
12515 | (const_int 0)))] | |
12516 | "") | |
1fd4e8c1 | 12517 | |
c0600ecd DE |
12518 | (define_insn_and_split "" |
12519 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
12520 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
12521 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
12522 | (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))] | |
683bdff7 | 12523 | "TARGET_32BIT" |
c0600ecd DE |
12524 | "#" |
12525 | "TARGET_32BIT" | |
12526 | [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2)))) | |
12527 | (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))] | |
12528 | "") | |
12529 | ||
12530 | (define_insn_and_split "" | |
12531 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12532 | (plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12533 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")) | |
12534 | (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))] | |
12535 | "TARGET_64BIT" | |
12536 | "#" | |
12537 | "TARGET_64BIT" | |
12538 | [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2)))) | |
12539 | (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))] | |
12540 | "") | |
1fd4e8c1 RK |
12541 | |
12542 | (define_insn "" | |
9ebbca7d | 12543 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12544 | (compare:CC |
9ebbca7d GK |
12545 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12546 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12547 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12548 | (const_int 0))) |
9ebbca7d | 12549 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12550 | "TARGET_32BIT" |
1fd4e8c1 | 12551 | "@ |
c9dbf840 DE |
12552 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3 |
12553 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3 | |
9ebbca7d GK |
12554 | # |
12555 | #" | |
b19003d8 | 12556 | [(set_attr "type" "compare") |
9ebbca7d GK |
12557 | (set_attr "length" "12,12,16,16")]) |
12558 | ||
12559 | (define_split | |
12560 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12561 | (compare:CC | |
12562 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12563 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12564 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12565 | (const_int 0))) | |
12566 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12567 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12568 | [(set (match_dup 4) |
12569 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12570 | (match_dup 3))) |
9ebbca7d GK |
12571 | (set (match_dup 0) |
12572 | (compare:CC (match_dup 4) | |
12573 | (const_int 0)))] | |
12574 | "") | |
1fd4e8c1 RK |
12575 | |
12576 | (define_insn "" | |
097657c3 | 12577 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12578 | (compare:CC |
9ebbca7d GK |
12579 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12580 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12581 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12582 | (const_int 0))) |
097657c3 AM |
12583 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12584 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 12585 | "TARGET_32BIT" |
1fd4e8c1 | 12586 | "@ |
c9dbf840 DE |
12587 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 |
12588 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 | |
9ebbca7d GK |
12589 | # |
12590 | #" | |
b19003d8 | 12591 | [(set_attr "type" "compare") |
9ebbca7d GK |
12592 | (set_attr "length" "12,12,16,16")]) |
12593 | ||
12594 | (define_split | |
097657c3 | 12595 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12596 | (compare:CC |
12597 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12598 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12599 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12600 | (const_int 0))) | |
12601 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12602 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 12603 | "TARGET_32BIT && reload_completed" |
097657c3 | 12604 | [(set (match_dup 0) |
9ebbca7d | 12605 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12606 | (set (match_dup 4) |
9ebbca7d GK |
12607 | (compare:CC (match_dup 0) |
12608 | (const_int 0)))] | |
12609 | "") | |
1fd4e8c1 RK |
12610 | |
12611 | (define_insn "" | |
cd2b37d9 RK |
12612 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12613 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12614 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
683bdff7 | 12615 | "TARGET_32BIT" |
1fd4e8c1 | 12616 | "@ |
ca7f5001 RK |
12617 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
12618 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
c0600ecd DE |
12619 | [(set_attr "type" "insert_word") |
12620 | (set_attr "length" "8")]) | |
12621 | ||
12622 | (define_insn "" | |
12623 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12624 | (neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12625 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))] | |
12626 | "TARGET_64BIT" | |
12627 | "@ | |
12628 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 | |
12629 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
12630 | [(set_attr "type" "insert_word") | |
12631 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
12632 | |
12633 | (define_insn "" | |
cd2b37d9 RK |
12634 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12635 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
12636 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
12637 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
12638 | "TARGET_POWER" |
12639 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 12640 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12641 | |
9ebbca7d GK |
12642 | (define_insn "" |
12643 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 12644 | (compare:CC |
9ebbca7d GK |
12645 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12646 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12647 | (const_int 0))) |
9ebbca7d | 12648 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12649 | (ge:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 12650 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 12651 | "TARGET_POWER" |
9ebbca7d GK |
12652 | "@ |
12653 | doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 | |
12654 | #" | |
12655 | [(set_attr "type" "compare") | |
12656 | (set_attr "length" "12,16")]) | |
12657 | ||
12658 | (define_split | |
12659 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12660 | (compare:CC | |
12661 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12662 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12663 | (const_int 0))) | |
12664 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12665 | (ge:SI (match_dup 1) (match_dup 2))) | |
12666 | (clobber (match_scratch:SI 3 ""))] | |
12667 | "TARGET_POWER && reload_completed" | |
12668 | [(parallel [(set (match_dup 0) | |
097657c3 AM |
12669 | (ge:SI (match_dup 1) (match_dup 2))) |
12670 | (clobber (match_dup 3))]) | |
9ebbca7d GK |
12671 | (set (match_dup 4) |
12672 | (compare:CC (match_dup 0) | |
12673 | (const_int 0)))] | |
12674 | "") | |
12675 | ||
1fd4e8c1 | 12676 | (define_insn "" |
097657c3 | 12677 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12678 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12679 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12680 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12681 | "TARGET_POWER" |
097657c3 | 12682 | "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" |
b19003d8 | 12683 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12684 | |
12685 | (define_insn "" | |
9ebbca7d | 12686 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12687 | (compare:CC |
9ebbca7d GK |
12688 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12689 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12690 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12691 | (const_int 0))) |
9ebbca7d | 12692 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12693 | "TARGET_POWER" |
9ebbca7d GK |
12694 | "@ |
12695 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
12696 | #" | |
b19003d8 | 12697 | [(set_attr "type" "compare") |
9ebbca7d GK |
12698 | (set_attr "length" "12,16")]) |
12699 | ||
12700 | (define_split | |
12701 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12702 | (compare:CC | |
12703 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12704 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12705 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12706 | (const_int 0))) | |
12707 | (clobber (match_scratch:SI 4 ""))] | |
12708 | "TARGET_POWER && reload_completed" | |
12709 | [(set (match_dup 4) | |
12710 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12711 | (match_dup 3))) |
9ebbca7d GK |
12712 | (set (match_dup 0) |
12713 | (compare:CC (match_dup 4) | |
12714 | (const_int 0)))] | |
12715 | "") | |
1fd4e8c1 RK |
12716 | |
12717 | (define_insn "" | |
097657c3 | 12718 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12719 | (compare:CC |
9ebbca7d GK |
12720 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12721 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12722 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12723 | (const_int 0))) |
097657c3 AM |
12724 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12725 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12726 | "TARGET_POWER" |
9ebbca7d | 12727 | "@ |
097657c3 | 12728 | doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
9ebbca7d | 12729 | #" |
b19003d8 | 12730 | [(set_attr "type" "compare") |
9ebbca7d GK |
12731 | (set_attr "length" "12,16")]) |
12732 | ||
12733 | (define_split | |
097657c3 | 12734 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12735 | (compare:CC |
12736 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12737 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12738 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12739 | (const_int 0))) | |
12740 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12741 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12742 | "TARGET_POWER && reload_completed" |
097657c3 | 12743 | [(set (match_dup 0) |
9ebbca7d | 12744 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12745 | (set (match_dup 4) |
9ebbca7d GK |
12746 | (compare:CC (match_dup 0) |
12747 | (const_int 0)))] | |
12748 | "") | |
1fd4e8c1 RK |
12749 | |
12750 | (define_insn "" | |
cd2b37d9 RK |
12751 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12752 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12753 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12754 | "TARGET_POWER" |
12755 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 12756 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12757 | |
1fd4e8c1 | 12758 | (define_insn "" |
cd2b37d9 RK |
12759 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12760 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12761 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
683bdff7 | 12762 | "TARGET_32BIT" |
1fd4e8c1 | 12763 | "@ |
ca7f5001 RK |
12764 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
12765 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
b19003d8 | 12766 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12767 | |
f9562f27 DE |
12768 | (define_insn "" |
12769 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12770 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12771 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
683bdff7 | 12772 | "TARGET_64BIT" |
f9562f27 DE |
12773 | "@ |
12774 | subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 | |
12775 | addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" | |
12776 | [(set_attr "length" "12")]) | |
12777 | ||
1fd4e8c1 | 12778 | (define_insn "" |
9ebbca7d | 12779 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12780 | (compare:CC |
9ebbca7d GK |
12781 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12782 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12783 | (const_int 0))) |
9ebbca7d | 12784 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12785 | (geu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12786 | "TARGET_32BIT" |
1fd4e8c1 | 12787 | "@ |
ca7f5001 | 12788 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
9ebbca7d GK |
12789 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
12790 | # | |
12791 | #" | |
b19003d8 | 12792 | [(set_attr "type" "compare") |
9ebbca7d GK |
12793 | (set_attr "length" "12,12,16,16")]) |
12794 | ||
12795 | (define_split | |
12796 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12797 | (compare:CC | |
12798 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12799 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12800 | (const_int 0))) | |
12801 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12802 | (geu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12803 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12804 | [(set (match_dup 0) |
12805 | (geu:SI (match_dup 1) (match_dup 2))) | |
12806 | (set (match_dup 3) | |
12807 | (compare:CC (match_dup 0) | |
12808 | (const_int 0)))] | |
12809 | "") | |
1fd4e8c1 | 12810 | |
f9562f27 | 12811 | (define_insn "" |
9ebbca7d | 12812 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12813 | (compare:CC |
9ebbca7d GK |
12814 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12815 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
f9562f27 | 12816 | (const_int 0))) |
9ebbca7d | 12817 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 | 12818 | (geu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12819 | "TARGET_64BIT" |
f9562f27 DE |
12820 | "@ |
12821 | subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 | |
9ebbca7d GK |
12822 | addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 |
12823 | # | |
12824 | #" | |
f9562f27 | 12825 | [(set_attr "type" "compare") |
9ebbca7d GK |
12826 | (set_attr "length" "12,12,16,16")]) |
12827 | ||
12828 | (define_split | |
12829 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12830 | (compare:CC | |
12831 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12832 | (match_operand:DI 2 "reg_or_neg_short_operand" "")) | |
12833 | (const_int 0))) | |
12834 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12835 | (geu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12836 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
12837 | [(set (match_dup 0) |
12838 | (geu:DI (match_dup 1) (match_dup 2))) | |
12839 | (set (match_dup 3) | |
12840 | (compare:CC (match_dup 0) | |
12841 | (const_int 0)))] | |
12842 | "") | |
f9562f27 | 12843 | |
1fd4e8c1 | 12844 | (define_insn "" |
80103f96 | 12845 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 12846 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12847 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
80103f96 | 12848 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
683bdff7 | 12849 | "TARGET_32BIT" |
1fd4e8c1 | 12850 | "@ |
80103f96 FS |
12851 | {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3 |
12852 | {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3" | |
b19003d8 | 12853 | [(set_attr "length" "8")]) |
1fd4e8c1 RK |
12854 | |
12855 | (define_insn "" | |
9ebbca7d | 12856 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12857 | (compare:CC |
9ebbca7d GK |
12858 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12859 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12860 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12861 | (const_int 0))) |
9ebbca7d | 12862 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12863 | "TARGET_32BIT" |
1fd4e8c1 | 12864 | "@ |
ca7f5001 | 12865 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12866 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 |
12867 | # | |
12868 | #" | |
b19003d8 | 12869 | [(set_attr "type" "compare") |
9ebbca7d GK |
12870 | (set_attr "length" "8,8,12,12")]) |
12871 | ||
12872 | (define_split | |
12873 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12874 | (compare:CC | |
12875 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12876 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12877 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12878 | (const_int 0))) | |
12879 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12880 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12881 | [(set (match_dup 4) |
12882 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) | |
12883 | (match_dup 3))) | |
12884 | (set (match_dup 0) | |
12885 | (compare:CC (match_dup 4) | |
12886 | (const_int 0)))] | |
12887 | "") | |
1fd4e8c1 RK |
12888 | |
12889 | (define_insn "" | |
097657c3 | 12890 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12891 | (compare:CC |
9ebbca7d GK |
12892 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12893 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12894 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12895 | (const_int 0))) |
097657c3 AM |
12896 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12897 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 12898 | "TARGET_32BIT" |
1fd4e8c1 | 12899 | "@ |
097657c3 AM |
12900 | {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3 |
12901 | {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
12902 | # |
12903 | #" | |
b19003d8 | 12904 | [(set_attr "type" "compare") |
9ebbca7d GK |
12905 | (set_attr "length" "8,8,12,12")]) |
12906 | ||
12907 | (define_split | |
097657c3 | 12908 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12909 | (compare:CC |
12910 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12911 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12912 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12913 | (const_int 0))) | |
12914 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12915 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 12916 | "TARGET_32BIT && reload_completed" |
097657c3 | 12917 | [(set (match_dup 0) |
9ebbca7d | 12918 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12919 | (set (match_dup 4) |
9ebbca7d GK |
12920 | (compare:CC (match_dup 0) |
12921 | (const_int 0)))] | |
12922 | "") | |
1fd4e8c1 RK |
12923 | |
12924 | (define_insn "" | |
cd2b37d9 RK |
12925 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12926 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12927 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
683bdff7 | 12928 | "TARGET_32BIT" |
1fd4e8c1 | 12929 | "@ |
ca7f5001 | 12930 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 12931 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
b19003d8 | 12932 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12933 | |
12934 | (define_insn "" | |
097657c3 | 12935 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
1fd4e8c1 | 12936 | (and:SI (neg:SI |
cd2b37d9 | 12937 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12938 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
097657c3 | 12939 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
683bdff7 | 12940 | "TARGET_32BIT" |
1fd4e8c1 | 12941 | "@ |
097657c3 AM |
12942 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 |
12943 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" | |
b19003d8 | 12944 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12945 | |
12946 | (define_insn "" | |
9ebbca7d | 12947 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12948 | (compare:CC |
12949 | (and:SI (neg:SI | |
9ebbca7d GK |
12950 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12951 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12952 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12953 | (const_int 0))) |
9ebbca7d | 12954 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12955 | "TARGET_32BIT" |
1fd4e8c1 | 12956 | "@ |
ca7f5001 | 12957 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
9ebbca7d GK |
12958 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
12959 | # | |
12960 | #" | |
b19003d8 | 12961 | [(set_attr "type" "compare") |
9ebbca7d GK |
12962 | (set_attr "length" "12,12,16,16")]) |
12963 | ||
12964 | (define_split | |
12965 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12966 | (compare:CC | |
12967 | (and:SI (neg:SI | |
12968 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12969 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
12970 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12971 | (const_int 0))) | |
12972 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12973 | "TARGET_32BIT && reload_completed" |
9ebbca7d | 12974 | [(set (match_dup 4) |
097657c3 AM |
12975 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) |
12976 | (match_dup 3))) | |
9ebbca7d GK |
12977 | (set (match_dup 0) |
12978 | (compare:CC (match_dup 4) | |
12979 | (const_int 0)))] | |
12980 | "") | |
1fd4e8c1 RK |
12981 | |
12982 | (define_insn "" | |
097657c3 | 12983 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12984 | (compare:CC |
12985 | (and:SI (neg:SI | |
9ebbca7d GK |
12986 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12987 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12988 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12989 | (const_int 0))) |
097657c3 AM |
12990 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12991 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
683bdff7 | 12992 | "TARGET_32BIT" |
1fd4e8c1 | 12993 | "@ |
097657c3 AM |
12994 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
12995 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 | |
9ebbca7d GK |
12996 | # |
12997 | #" | |
b19003d8 | 12998 | [(set_attr "type" "compare") |
9ebbca7d GK |
12999 | (set_attr "length" "12,12,16,16")]) |
13000 | ||
13001 | (define_split | |
097657c3 | 13002 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13003 | (compare:CC |
13004 | (and:SI (neg:SI | |
13005 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13006 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
13007 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13008 | (const_int 0))) | |
13009 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13010 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
683bdff7 | 13011 | "TARGET_32BIT && reload_completed" |
097657c3 | 13012 | [(set (match_dup 0) |
9ebbca7d | 13013 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
097657c3 | 13014 | (set (match_dup 4) |
9ebbca7d GK |
13015 | (compare:CC (match_dup 0) |
13016 | (const_int 0)))] | |
13017 | "") | |
1fd4e8c1 RK |
13018 | |
13019 | (define_insn "" | |
cd2b37d9 RK |
13020 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13021 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13022 | (const_int 0)))] |
683bdff7 | 13023 | "TARGET_32BIT" |
ca7f5001 | 13024 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 13025 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13026 | |
f9562f27 DE |
13027 | (define_insn "" |
13028 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13029 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13030 | (const_int 0)))] | |
683bdff7 | 13031 | "TARGET_64BIT" |
f9562f27 DE |
13032 | "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63" |
13033 | [(set_attr "length" "12")]) | |
13034 | ||
1fd4e8c1 | 13035 | (define_insn "" |
9ebbca7d | 13036 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13037 | (compare:CC |
9ebbca7d | 13038 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
13039 | (const_int 0)) |
13040 | (const_int 0))) | |
9ebbca7d | 13041 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13042 | (gt:SI (match_dup 1) (const_int 0)))] |
683bdff7 | 13043 | "TARGET_32BIT" |
9ebbca7d GK |
13044 | "@ |
13045 | {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31 | |
13046 | #" | |
29ae5b89 | 13047 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
13048 | (set_attr "length" "12,16")]) |
13049 | ||
13050 | (define_split | |
13051 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
13052 | (compare:CC | |
13053 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13054 | (const_int 0)) | |
13055 | (const_int 0))) | |
13056 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13057 | (gt:SI (match_dup 1) (const_int 0)))] | |
683bdff7 | 13058 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13059 | [(set (match_dup 0) |
13060 | (gt:SI (match_dup 1) (const_int 0))) | |
13061 | (set (match_dup 2) | |
13062 | (compare:CC (match_dup 0) | |
13063 | (const_int 0)))] | |
13064 | "") | |
1fd4e8c1 | 13065 | |
f9562f27 | 13066 | (define_insn "" |
9ebbca7d | 13067 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
f9562f27 | 13068 | (compare:CC |
9ebbca7d | 13069 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 DE |
13070 | (const_int 0)) |
13071 | (const_int 0))) | |
9ebbca7d | 13072 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 13073 | (gt:DI (match_dup 1) (const_int 0)))] |
683bdff7 | 13074 | "TARGET_64BIT" |
9ebbca7d GK |
13075 | "@ |
13076 | subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63 | |
13077 | #" | |
f9562f27 | 13078 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
13079 | (set_attr "length" "12,16")]) |
13080 | ||
13081 | (define_split | |
13082 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
13083 | (compare:CC | |
13084 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13085 | (const_int 0)) | |
13086 | (const_int 0))) | |
13087 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13088 | (gt:DI (match_dup 1) (const_int 0)))] | |
683bdff7 | 13089 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13090 | [(set (match_dup 0) |
13091 | (gt:DI (match_dup 1) (const_int 0))) | |
13092 | (set (match_dup 2) | |
13093 | (compare:CC (match_dup 0) | |
13094 | (const_int 0)))] | |
13095 | "") | |
f9562f27 | 13096 | |
1fd4e8c1 | 13097 | (define_insn "" |
cd2b37d9 RK |
13098 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13099 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13100 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
13101 | "TARGET_POWER" |
13102 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 13103 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13104 | |
13105 | (define_insn "" | |
9ebbca7d | 13106 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13107 | (compare:CC |
9ebbca7d GK |
13108 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13109 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
1fd4e8c1 | 13110 | (const_int 0))) |
9ebbca7d | 13111 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13112 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 13113 | "TARGET_POWER" |
9ebbca7d GK |
13114 | "@ |
13115 | doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
13116 | #" | |
29ae5b89 | 13117 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
13118 | (set_attr "length" "12,16")]) |
13119 | ||
13120 | (define_split | |
13121 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13122 | (compare:CC | |
13123 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13124 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13125 | (const_int 0))) | |
13126 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13127 | (gt:SI (match_dup 1) (match_dup 2)))] | |
13128 | "TARGET_POWER && reload_completed" | |
13129 | [(set (match_dup 0) | |
13130 | (gt:SI (match_dup 1) (match_dup 2))) | |
13131 | (set (match_dup 3) | |
13132 | (compare:CC (match_dup 0) | |
13133 | (const_int 0)))] | |
13134 | "") | |
1fd4e8c1 RK |
13135 | |
13136 | (define_insn "" | |
80103f96 | 13137 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 13138 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 13139 | (const_int 0)) |
80103f96 | 13140 | (match_operand:SI 2 "gpc_reg_operand" "r")))] |
683bdff7 | 13141 | "TARGET_32BIT" |
80103f96 | 13142 | "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2" |
b19003d8 | 13143 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13144 | |
f9562f27 | 13145 | (define_insn "" |
097657c3 | 13146 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
f9562f27 DE |
13147 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
13148 | (const_int 0)) | |
097657c3 | 13149 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
683bdff7 | 13150 | "TARGET_64BIT" |
097657c3 | 13151 | "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2" |
f9562f27 DE |
13152 | [(set_attr "length" "12")]) |
13153 | ||
1fd4e8c1 | 13154 | (define_insn "" |
9ebbca7d | 13155 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13156 | (compare:CC |
9ebbca7d | 13157 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 13158 | (const_int 0)) |
9ebbca7d | 13159 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 13160 | (const_int 0))) |
9ebbca7d | 13161 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
683bdff7 | 13162 | "TARGET_32BIT" |
9ebbca7d GK |
13163 | "@ |
13164 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 | |
13165 | #" | |
b19003d8 | 13166 | [(set_attr "type" "compare") |
9ebbca7d GK |
13167 | (set_attr "length" "12,16")]) |
13168 | ||
13169 | (define_split | |
13170 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13171 | (compare:CC | |
13172 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13173 | (const_int 0)) | |
13174 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
13175 | (const_int 0))) | |
13176 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 13177 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13178 | [(set (match_dup 3) |
13179 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) | |
13180 | (match_dup 2))) | |
13181 | (set (match_dup 0) | |
13182 | (compare:CC (match_dup 3) | |
13183 | (const_int 0)))] | |
13184 | "") | |
1fd4e8c1 | 13185 | |
f9562f27 | 13186 | (define_insn "" |
9ebbca7d | 13187 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
f9562f27 | 13188 | (compare:CC |
9ebbca7d | 13189 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 13190 | (const_int 0)) |
9ebbca7d | 13191 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 13192 | (const_int 0))) |
9ebbca7d | 13193 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 13194 | "TARGET_64BIT" |
9ebbca7d GK |
13195 | "@ |
13196 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 | |
13197 | #" | |
f9562f27 | 13198 | [(set_attr "type" "compare") |
9ebbca7d GK |
13199 | (set_attr "length" "12,16")]) |
13200 | ||
13201 | (define_split | |
13202 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13203 | (compare:CC | |
13204 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13205 | (const_int 0)) | |
13206 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
13207 | (const_int 0))) | |
13208 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 13209 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13210 | [(set (match_dup 3) |
13211 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) | |
097657c3 | 13212 | (match_dup 2))) |
9ebbca7d GK |
13213 | (set (match_dup 0) |
13214 | (compare:CC (match_dup 3) | |
13215 | (const_int 0)))] | |
13216 | "") | |
f9562f27 | 13217 | |
1fd4e8c1 | 13218 | (define_insn "" |
097657c3 | 13219 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
9ebbca7d GK |
13220 | (compare:CC |
13221 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
13222 | (const_int 0)) | |
13223 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
13224 | (const_int 0))) | |
097657c3 AM |
13225 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
13226 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
683bdff7 | 13227 | "TARGET_32BIT" |
9ebbca7d | 13228 | "@ |
097657c3 | 13229 | {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2 |
9ebbca7d GK |
13230 | #" |
13231 | [(set_attr "type" "compare") | |
13232 | (set_attr "length" "12,16")]) | |
13233 | ||
13234 | (define_split | |
097657c3 | 13235 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
1fd4e8c1 | 13236 | (compare:CC |
9ebbca7d | 13237 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 13238 | (const_int 0)) |
9ebbca7d | 13239 | (match_operand:SI 2 "gpc_reg_operand" "")) |
1fd4e8c1 | 13240 | (const_int 0))) |
9ebbca7d | 13241 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
097657c3 | 13242 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] |
683bdff7 | 13243 | "TARGET_32BIT && reload_completed" |
097657c3 | 13244 | [(set (match_dup 0) |
9ebbca7d | 13245 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 13246 | (set (match_dup 3) |
9ebbca7d GK |
13247 | (compare:CC (match_dup 0) |
13248 | (const_int 0)))] | |
13249 | "") | |
1fd4e8c1 | 13250 | |
f9562f27 | 13251 | (define_insn "" |
097657c3 | 13252 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13253 | (compare:CC |
9ebbca7d | 13254 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 13255 | (const_int 0)) |
9ebbca7d | 13256 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 13257 | (const_int 0))) |
097657c3 AM |
13258 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") |
13259 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
683bdff7 | 13260 | "TARGET_64BIT" |
9ebbca7d | 13261 | "@ |
097657c3 | 13262 | addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 |
9ebbca7d | 13263 | #" |
f9562f27 | 13264 | [(set_attr "type" "compare") |
9ebbca7d GK |
13265 | (set_attr "length" "12,16")]) |
13266 | ||
13267 | (define_split | |
097657c3 | 13268 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13269 | (compare:CC |
13270 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13271 | (const_int 0)) | |
13272 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
13273 | (const_int 0))) | |
13274 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 13275 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] |
683bdff7 | 13276 | "TARGET_64BIT && reload_completed" |
097657c3 | 13277 | [(set (match_dup 0) |
9ebbca7d | 13278 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 13279 | (set (match_dup 3) |
9ebbca7d GK |
13280 | (compare:CC (match_dup 0) |
13281 | (const_int 0)))] | |
13282 | "") | |
f9562f27 | 13283 | |
1fd4e8c1 | 13284 | (define_insn "" |
097657c3 | 13285 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 13286 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 13287 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
097657c3 | 13288 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 13289 | "TARGET_POWER" |
097657c3 | 13290 | "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 13291 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
13292 | |
13293 | (define_insn "" | |
9ebbca7d | 13294 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13295 | (compare:CC |
9ebbca7d GK |
13296 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13297 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
13298 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13299 | (const_int 0))) |
9ebbca7d | 13300 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 13301 | "TARGET_POWER" |
9ebbca7d GK |
13302 | "@ |
13303 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
13304 | #" | |
b19003d8 | 13305 | [(set_attr "type" "compare") |
9ebbca7d GK |
13306 | (set_attr "length" "12,16")]) |
13307 | ||
13308 | (define_split | |
13309 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13310 | (compare:CC | |
13311 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13312 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13313 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13314 | (const_int 0))) | |
13315 | (clobber (match_scratch:SI 4 ""))] | |
13316 | "TARGET_POWER && reload_completed" | |
13317 | [(set (match_dup 4) | |
097657c3 | 13318 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d GK |
13319 | (set (match_dup 0) |
13320 | (compare:CC (match_dup 4) | |
13321 | (const_int 0)))] | |
13322 | "") | |
1fd4e8c1 RK |
13323 | |
13324 | (define_insn "" | |
097657c3 | 13325 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13326 | (compare:CC |
9ebbca7d GK |
13327 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13328 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
13329 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 13330 | (const_int 0))) |
097657c3 AM |
13331 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
13332 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 13333 | "TARGET_POWER" |
9ebbca7d | 13334 | "@ |
097657c3 | 13335 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 13336 | #" |
b19003d8 | 13337 | [(set_attr "type" "compare") |
9ebbca7d GK |
13338 | (set_attr "length" "12,16")]) |
13339 | ||
13340 | (define_split | |
097657c3 | 13341 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13342 | (compare:CC |
13343 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13344 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13345 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13346 | (const_int 0))) | |
13347 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13348 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 13349 | "TARGET_POWER && reload_completed" |
097657c3 | 13350 | [(set (match_dup 0) |
9ebbca7d | 13351 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13352 | (set (match_dup 4) |
9ebbca7d GK |
13353 | (compare:CC (match_dup 0) |
13354 | (const_int 0)))] | |
13355 | "") | |
1fd4e8c1 RK |
13356 | |
13357 | (define_insn "" | |
cd2b37d9 RK |
13358 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13359 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13360 | (const_int 0))))] |
683bdff7 | 13361 | "TARGET_32BIT" |
ca7f5001 | 13362 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
b19003d8 | 13363 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13364 | |
f9562f27 DE |
13365 | (define_insn "" |
13366 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13367 | (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13368 | (const_int 0))))] | |
683bdff7 | 13369 | "TARGET_64BIT" |
8377288b | 13370 | "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63" |
f9562f27 DE |
13371 | [(set_attr "length" "12")]) |
13372 | ||
1fd4e8c1 | 13373 | (define_insn "" |
cd2b37d9 RK |
13374 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13375 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13376 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
13377 | "TARGET_POWER" |
13378 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 13379 | [(set_attr "length" "12")]) |
1fd4e8c1 | 13380 | |
c0600ecd | 13381 | (define_insn_and_split "" |
cd2b37d9 | 13382 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c0600ecd DE |
13383 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
13384 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13385 | "TARGET_32BIT" |
c0600ecd DE |
13386 | "#" |
13387 | "TARGET_32BIT" | |
13388 | [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2)))) | |
13389 | (set (match_dup 0) (neg:SI (match_dup 0)))] | |
13390 | "") | |
1fd4e8c1 | 13391 | |
c0600ecd | 13392 | (define_insn_and_split "" |
f9562f27 | 13393 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
c0600ecd DE |
13394 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
13395 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13396 | "TARGET_64BIT" |
c0600ecd DE |
13397 | "#" |
13398 | "TARGET_64BIT" | |
13399 | [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2)))) | |
13400 | (set (match_dup 0) (neg:DI (match_dup 0)))] | |
13401 | "") | |
f9562f27 | 13402 | |
1fd4e8c1 | 13403 | (define_insn "" |
9ebbca7d | 13404 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13405 | (compare:CC |
9ebbca7d GK |
13406 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13407 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 13408 | (const_int 0))) |
9ebbca7d | 13409 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13410 | (gtu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 13411 | "TARGET_32BIT" |
9ebbca7d GK |
13412 | "@ |
13413 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 | |
13414 | #" | |
b19003d8 | 13415 | [(set_attr "type" "compare") |
9ebbca7d GK |
13416 | (set_attr "length" "12,16")]) |
13417 | ||
13418 | (define_split | |
13419 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13420 | (compare:CC | |
13421 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13422 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13423 | (const_int 0))) | |
13424 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13425 | (gtu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 13426 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13427 | [(set (match_dup 0) |
13428 | (gtu:SI (match_dup 1) (match_dup 2))) | |
13429 | (set (match_dup 3) | |
13430 | (compare:CC (match_dup 0) | |
13431 | (const_int 0)))] | |
13432 | "") | |
1fd4e8c1 | 13433 | |
f9562f27 | 13434 | (define_insn "" |
9ebbca7d | 13435 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13436 | (compare:CC |
9ebbca7d GK |
13437 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
13438 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 13439 | (const_int 0))) |
9ebbca7d | 13440 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 13441 | (gtu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 13442 | "TARGET_64BIT" |
9ebbca7d GK |
13443 | "@ |
13444 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0 | |
13445 | #" | |
f9562f27 | 13446 | [(set_attr "type" "compare") |
9ebbca7d GK |
13447 | (set_attr "length" "12,16")]) |
13448 | ||
13449 | (define_split | |
13450 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13451 | (compare:CC | |
13452 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13453 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13454 | (const_int 0))) | |
13455 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13456 | (gtu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 13457 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13458 | [(set (match_dup 0) |
13459 | (gtu:DI (match_dup 1) (match_dup 2))) | |
13460 | (set (match_dup 3) | |
13461 | (compare:CC (match_dup 0) | |
13462 | (const_int 0)))] | |
13463 | "") | |
f9562f27 | 13464 | |
c0600ecd DE |
13465 | (define_insn_and_split "" |
13466 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
13467 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
13468 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
13469 | (match_operand:SI 3 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13470 | "TARGET_32BIT" |
c0600ecd DE |
13471 | "#" |
13472 | "TARGET_32BIT" | |
13473 | [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2)))) | |
13474 | (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))] | |
13475 | "") | |
1fd4e8c1 | 13476 | |
c0600ecd DE |
13477 | (define_insn_and_split "" |
13478 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13479 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13480 | (match_operand:DI 2 "reg_or_short_operand" "rI")) | |
13481 | (match_operand:DI 3 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13482 | "TARGET_64BIT" |
c0600ecd DE |
13483 | "#" |
13484 | "TARGET_64BIT" | |
13485 | [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2)))) | |
13486 | (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))] | |
13487 | "") | |
f9562f27 | 13488 | |
1fd4e8c1 | 13489 | (define_insn "" |
9ebbca7d | 13490 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13491 | (compare:CC |
9ebbca7d GK |
13492 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13493 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13494 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13495 | (const_int 0))) |
9ebbca7d | 13496 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 13497 | "TARGET_32BIT" |
00751805 | 13498 | "@ |
19378cf8 | 13499 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 |
c9dbf840 | 13500 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3 |
9ebbca7d GK |
13501 | # |
13502 | #" | |
b19003d8 | 13503 | [(set_attr "type" "compare") |
9ebbca7d GK |
13504 | (set_attr "length" "8,12,12,16")]) |
13505 | ||
13506 | (define_split | |
13507 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13508 | (compare:CC | |
13509 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13510 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13511 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13512 | (const_int 0))) | |
13513 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 13514 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13515 | [(set (match_dup 4) |
13516 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 13517 | (match_dup 3))) |
9ebbca7d GK |
13518 | (set (match_dup 0) |
13519 | (compare:CC (match_dup 4) | |
13520 | (const_int 0)))] | |
13521 | "") | |
1fd4e8c1 | 13522 | |
f9562f27 | 13523 | (define_insn "" |
9ebbca7d | 13524 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13525 | (compare:CC |
9ebbca7d GK |
13526 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13527 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13528 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13529 | (const_int 0))) |
9ebbca7d | 13530 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 13531 | "TARGET_64BIT" |
f9562f27 DE |
13532 | "@ |
13533 | addic %4,%1,%k2\;addze. %4,%3 | |
c9dbf840 | 13534 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3 |
9ebbca7d GK |
13535 | # |
13536 | #" | |
f9562f27 | 13537 | [(set_attr "type" "compare") |
9ebbca7d GK |
13538 | (set_attr "length" "8,12,12,16")]) |
13539 | ||
13540 | (define_split | |
13541 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13542 | (compare:CC | |
13543 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13544 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13545 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13546 | (const_int 0))) | |
13547 | (clobber (match_scratch:DI 4 ""))] | |
683bdff7 | 13548 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13549 | [(set (match_dup 4) |
13550 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) | |
13551 | (match_dup 3))) | |
13552 | (set (match_dup 0) | |
13553 | (compare:CC (match_dup 4) | |
13554 | (const_int 0)))] | |
13555 | "") | |
f9562f27 | 13556 | |
1fd4e8c1 | 13557 | (define_insn "" |
097657c3 | 13558 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13559 | (compare:CC |
9ebbca7d GK |
13560 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13561 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13562 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13563 | (const_int 0))) |
097657c3 AM |
13564 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13565 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 13566 | "TARGET_32BIT" |
00751805 | 13567 | "@ |
097657c3 | 13568 | {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3 |
c9dbf840 | 13569 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 |
9ebbca7d GK |
13570 | # |
13571 | #" | |
b19003d8 | 13572 | [(set_attr "type" "compare") |
9ebbca7d GK |
13573 | (set_attr "length" "8,12,12,16")]) |
13574 | ||
13575 | (define_split | |
097657c3 | 13576 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13577 | (compare:CC |
13578 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13579 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13580 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13581 | (const_int 0))) | |
13582 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13583 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 13584 | "TARGET_32BIT && reload_completed" |
097657c3 | 13585 | [(set (match_dup 0) |
9ebbca7d | 13586 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13587 | (set (match_dup 4) |
9ebbca7d GK |
13588 | (compare:CC (match_dup 0) |
13589 | (const_int 0)))] | |
13590 | "") | |
1fd4e8c1 | 13591 | |
f9562f27 | 13592 | (define_insn "" |
097657c3 | 13593 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13594 | (compare:CC |
9ebbca7d GK |
13595 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13596 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13597 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13598 | (const_int 0))) |
097657c3 AM |
13599 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13600 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 13601 | "TARGET_64BIT" |
f9562f27 | 13602 | "@ |
097657c3 | 13603 | addic %0,%1,%k2\;addze. %0,%3 |
c9dbf840 | 13604 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3 |
9ebbca7d GK |
13605 | # |
13606 | #" | |
f9562f27 | 13607 | [(set_attr "type" "compare") |
9ebbca7d GK |
13608 | (set_attr "length" "8,12,12,16")]) |
13609 | ||
13610 | (define_split | |
097657c3 | 13611 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13612 | (compare:CC |
13613 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13614 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13615 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13616 | (const_int 0))) | |
13617 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 13618 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 13619 | "TARGET_64BIT && reload_completed" |
097657c3 | 13620 | [(set (match_dup 0) |
9ebbca7d | 13621 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13622 | (set (match_dup 4) |
9ebbca7d GK |
13623 | (compare:CC (match_dup 0) |
13624 | (const_int 0)))] | |
13625 | "") | |
f9562f27 | 13626 | |
1fd4e8c1 | 13627 | (define_insn "" |
cd2b37d9 RK |
13628 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13629 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13630 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
683bdff7 | 13631 | "TARGET_32BIT" |
ca7f5001 | 13632 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
c0600ecd DE |
13633 | [(set_attr "type" "insert_word") |
13634 | (set_attr "length" "8")]) | |
f9562f27 DE |
13635 | |
13636 | (define_insn "" | |
13637 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13638 | (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13639 | (match_operand:DI 2 "reg_or_short_operand" "rI"))))] | |
683bdff7 | 13640 | "TARGET_64BIT" |
f9562f27 | 13641 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0" |
c0600ecd DE |
13642 | [(set_attr "type" "insert_word") |
13643 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
13644 | \f |
13645 | ;; Define both directions of branch and return. If we need a reload | |
13646 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
13647 | ;; register CC value to there. | |
13648 | ||
13649 | (define_insn "" | |
13650 | [(set (pc) | |
13651 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13652 | [(match_operand 2 | |
b54cf83a | 13653 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13654 | (const_int 0)]) |
13655 | (label_ref (match_operand 0 "" "")) | |
13656 | (pc)))] | |
13657 | "" | |
b19003d8 RK |
13658 | "* |
13659 | { | |
12a4e8c5 | 13660 | return output_cbranch (operands[1], \"%l0\", 0, insn); |
b19003d8 RK |
13661 | }" |
13662 | [(set_attr "type" "branch")]) | |
13663 | ||
1fd4e8c1 RK |
13664 | (define_insn "" |
13665 | [(set (pc) | |
13666 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13667 | [(match_operand 1 | |
b54cf83a | 13668 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13669 | (const_int 0)]) |
13670 | (return) | |
13671 | (pc)))] | |
13672 | "direct_return ()" | |
12a4e8c5 GK |
13673 | "* |
13674 | { | |
13675 | return output_cbranch (operands[0], NULL, 0, insn); | |
13676 | }" | |
b7ff3d82 | 13677 | [(set_attr "type" "branch") |
39a10a29 | 13678 | (set_attr "length" "4")]) |
1fd4e8c1 RK |
13679 | |
13680 | (define_insn "" | |
13681 | [(set (pc) | |
13682 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13683 | [(match_operand 2 | |
b54cf83a | 13684 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13685 | (const_int 0)]) |
13686 | (pc) | |
13687 | (label_ref (match_operand 0 "" ""))))] | |
13688 | "" | |
b19003d8 RK |
13689 | "* |
13690 | { | |
12a4e8c5 | 13691 | return output_cbranch (operands[1], \"%l0\", 1, insn); |
b19003d8 RK |
13692 | }" |
13693 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13694 | |
13695 | (define_insn "" | |
13696 | [(set (pc) | |
13697 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13698 | [(match_operand 1 | |
b54cf83a | 13699 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13700 | (const_int 0)]) |
13701 | (pc) | |
13702 | (return)))] | |
13703 | "direct_return ()" | |
12a4e8c5 GK |
13704 | "* |
13705 | { | |
13706 | return output_cbranch (operands[0], NULL, 1, insn); | |
13707 | }" | |
b7ff3d82 | 13708 | [(set_attr "type" "branch") |
39a10a29 GK |
13709 | (set_attr "length" "4")]) |
13710 | ||
13711 | ;; Logic on condition register values. | |
13712 | ||
13713 | ; This pattern matches things like | |
13714 | ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) | |
13715 | ; (eq:SI (reg:CCFP 68) (const_int 0))) | |
13716 | ; (const_int 1))) | |
13717 | ; which are generated by the branch logic. | |
b54cf83a | 13718 | ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB) |
39a10a29 | 13719 | |
423c1189 | 13720 | (define_insn "*cceq_ior_compare" |
b54cf83a | 13721 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
39a10a29 | 13722 | (compare:CCEQ (match_operator:SI 1 "boolean_operator" |
b54cf83a | 13723 | [(match_operator:SI 2 |
39a10a29 GK |
13724 | "branch_positive_comparison_operator" |
13725 | [(match_operand 3 | |
b54cf83a | 13726 | "cc_reg_operand" "y,y") |
39a10a29 | 13727 | (const_int 0)]) |
b54cf83a | 13728 | (match_operator:SI 4 |
39a10a29 GK |
13729 | "branch_positive_comparison_operator" |
13730 | [(match_operand 5 | |
b54cf83a | 13731 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13732 | (const_int 0)])]) |
13733 | (const_int 1)))] | |
24fab1d3 | 13734 | "" |
39a10a29 | 13735 | "cr%q1 %E0,%j2,%j4" |
b54cf83a | 13736 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
13737 | |
13738 | ; Why is the constant -1 here, but 1 in the previous pattern? | |
13739 | ; Because ~1 has all but the low bit set. | |
13740 | (define_insn "" | |
b54cf83a | 13741 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
39a10a29 | 13742 | (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" |
b54cf83a | 13743 | [(not:SI (match_operator:SI 2 |
39a10a29 GK |
13744 | "branch_positive_comparison_operator" |
13745 | [(match_operand 3 | |
b54cf83a | 13746 | "cc_reg_operand" "y,y") |
39a10a29 GK |
13747 | (const_int 0)])) |
13748 | (match_operator:SI 4 | |
13749 | "branch_positive_comparison_operator" | |
13750 | [(match_operand 5 | |
b54cf83a | 13751 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13752 | (const_int 0)])]) |
13753 | (const_int -1)))] | |
13754 | "" | |
13755 | "cr%q1 %E0,%j2,%j4" | |
b54cf83a | 13756 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 | 13757 | |
423c1189 | 13758 | (define_insn "*cceq_rev_compare" |
b54cf83a | 13759 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
6c873122 | 13760 | (compare:CCEQ (match_operator:SI 1 |
39a10a29 | 13761 | "branch_positive_comparison_operator" |
6c873122 | 13762 | [(match_operand 2 |
b54cf83a | 13763 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13764 | (const_int 0)]) |
13765 | (const_int 0)))] | |
423c1189 | 13766 | "" |
251b3667 | 13767 | "{crnor %E0,%j1,%j1|crnot %E0,%j1}" |
b54cf83a | 13768 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
13769 | |
13770 | ;; If we are comparing the result of two comparisons, this can be done | |
13771 | ;; using creqv or crxor. | |
13772 | ||
13773 | (define_insn_and_split "" | |
13774 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
13775 | (compare:CCEQ (match_operator 1 "branch_comparison_operator" | |
13776 | [(match_operand 2 "cc_reg_operand" "y") | |
13777 | (const_int 0)]) | |
13778 | (match_operator 3 "branch_comparison_operator" | |
13779 | [(match_operand 4 "cc_reg_operand" "y") | |
13780 | (const_int 0)])))] | |
13781 | "" | |
13782 | "#" | |
13783 | "" | |
13784 | [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) | |
13785 | (match_dup 5)))] | |
13786 | " | |
13787 | { | |
13788 | int positive_1, positive_2; | |
13789 | ||
13790 | positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode); | |
13791 | positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode); | |
13792 | ||
13793 | if (! positive_1) | |
1c563bed | 13794 | operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]), |
0f4c242b KH |
13795 | GET_CODE (operands[1])), |
13796 | SImode, | |
13797 | operands[2], const0_rtx); | |
39a10a29 | 13798 | else if (GET_MODE (operands[1]) != SImode) |
0f4c242b KH |
13799 | operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, |
13800 | operands[2], const0_rtx); | |
39a10a29 GK |
13801 | |
13802 | if (! positive_2) | |
1c563bed | 13803 | operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]), |
0f4c242b KH |
13804 | GET_CODE (operands[3])), |
13805 | SImode, | |
13806 | operands[4], const0_rtx); | |
39a10a29 | 13807 | else if (GET_MODE (operands[3]) != SImode) |
0f4c242b KH |
13808 | operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
13809 | operands[4], const0_rtx); | |
39a10a29 GK |
13810 | |
13811 | if (positive_1 == positive_2) | |
251b3667 DE |
13812 | { |
13813 | operands[1] = gen_rtx_NOT (SImode, operands[1]); | |
13814 | operands[5] = constm1_rtx; | |
13815 | } | |
13816 | else | |
13817 | { | |
13818 | operands[5] = const1_rtx; | |
13819 | } | |
39a10a29 | 13820 | }") |
1fd4e8c1 RK |
13821 | |
13822 | ;; Unconditional branch and return. | |
13823 | ||
13824 | (define_insn "jump" | |
13825 | [(set (pc) | |
13826 | (label_ref (match_operand 0 "" "")))] | |
13827 | "" | |
b7ff3d82 DE |
13828 | "b %l0" |
13829 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13830 | |
13831 | (define_insn "return" | |
13832 | [(return)] | |
13833 | "direct_return ()" | |
324e52cc TG |
13834 | "{br|blr}" |
13835 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 13836 | |
0ad91047 DE |
13837 | (define_expand "indirect_jump" |
13838 | [(set (pc) (match_operand 0 "register_operand" ""))] | |
1fd4e8c1 | 13839 | "" |
0ad91047 DE |
13840 | " |
13841 | { | |
13842 | if (TARGET_32BIT) | |
13843 | emit_jump_insn (gen_indirect_jumpsi (operands[0])); | |
13844 | else | |
13845 | emit_jump_insn (gen_indirect_jumpdi (operands[0])); | |
13846 | DONE; | |
13847 | }") | |
13848 | ||
13849 | (define_insn "indirect_jumpsi" | |
b92b324d | 13850 | [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))] |
0ad91047 | 13851 | "TARGET_32BIT" |
b92b324d DE |
13852 | "@ |
13853 | bctr | |
13854 | {br|blr}" | |
324e52cc | 13855 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 13856 | |
0ad91047 | 13857 | (define_insn "indirect_jumpdi" |
b92b324d | 13858 | [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))] |
0ad91047 | 13859 | "TARGET_64BIT" |
b92b324d DE |
13860 | "@ |
13861 | bctr | |
13862 | blr" | |
266eb58a DE |
13863 | [(set_attr "type" "jmpreg")]) |
13864 | ||
1fd4e8c1 RK |
13865 | ;; Table jump for switch statements: |
13866 | (define_expand "tablejump" | |
e6ca2c17 DE |
13867 | [(use (match_operand 0 "" "")) |
13868 | (use (label_ref (match_operand 1 "" "")))] | |
13869 | "" | |
13870 | " | |
13871 | { | |
13872 | if (TARGET_32BIT) | |
13873 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
13874 | else | |
13875 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
13876 | DONE; | |
13877 | }") | |
13878 | ||
13879 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
13880 | [(set (match_dup 3) |
13881 | (plus:SI (match_operand:SI 0 "" "") | |
13882 | (match_dup 2))) | |
13883 | (parallel [(set (pc) (match_dup 3)) | |
13884 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13885 | "TARGET_32BIT" |
1fd4e8c1 RK |
13886 | " |
13887 | { operands[0] = force_reg (SImode, operands[0]); | |
c5c76735 | 13888 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); |
1fd4e8c1 RK |
13889 | operands[3] = gen_reg_rtx (SImode); |
13890 | }") | |
13891 | ||
e6ca2c17 | 13892 | (define_expand "tablejumpdi" |
6ae08853 | 13893 | [(set (match_dup 4) |
9ebbca7d GK |
13894 | (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) |
13895 | (set (match_dup 3) | |
13896 | (plus:DI (match_dup 4) | |
e6ca2c17 DE |
13897 | (match_dup 2))) |
13898 | (parallel [(set (pc) (match_dup 3)) | |
13899 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13900 | "TARGET_64BIT" |
e6ca2c17 | 13901 | " |
9ebbca7d | 13902 | { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); |
e6ca2c17 | 13903 | operands[3] = gen_reg_rtx (DImode); |
9ebbca7d | 13904 | operands[4] = gen_reg_rtx (DImode); |
e6ca2c17 DE |
13905 | }") |
13906 | ||
1fd4e8c1 RK |
13907 | (define_insn "" |
13908 | [(set (pc) | |
c859cda6 | 13909 | (match_operand:SI 0 "register_operand" "c,*l")) |
1fd4e8c1 | 13910 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 13911 | "TARGET_32BIT" |
c859cda6 DJ |
13912 | "@ |
13913 | bctr | |
13914 | {br|blr}" | |
a6845123 | 13915 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 | 13916 | |
266eb58a DE |
13917 | (define_insn "" |
13918 | [(set (pc) | |
c859cda6 | 13919 | (match_operand:DI 0 "register_operand" "c,*l")) |
266eb58a | 13920 | (use (label_ref (match_operand 1 "" "")))] |
0ad91047 | 13921 | "TARGET_64BIT" |
c859cda6 DJ |
13922 | "@ |
13923 | bctr | |
13924 | blr" | |
266eb58a DE |
13925 | [(set_attr "type" "jmpreg")]) |
13926 | ||
1fd4e8c1 RK |
13927 | (define_insn "nop" |
13928 | [(const_int 0)] | |
13929 | "" | |
ca7f5001 | 13930 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 13931 | \f |
7e69e155 | 13932 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
13933 | ;; so loop.c knows what to generate. |
13934 | ||
5527bf14 RH |
13935 | (define_expand "doloop_end" |
13936 | [(use (match_operand 0 "" "")) ; loop pseudo | |
13937 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
13938 | (use (match_operand 2 "" "")) ; max iterations | |
13939 | (use (match_operand 3 "" "")) ; loop level | |
13940 | (use (match_operand 4 "" ""))] ; label | |
0ad91047 DE |
13941 | "" |
13942 | " | |
13943 | { | |
5527bf14 RH |
13944 | /* Only use this on innermost loops. */ |
13945 | if (INTVAL (operands[3]) > 1) | |
13946 | FAIL; | |
683bdff7 | 13947 | if (TARGET_64BIT) |
5527bf14 RH |
13948 | { |
13949 | if (GET_MODE (operands[0]) != DImode) | |
13950 | FAIL; | |
13951 | emit_jump_insn (gen_ctrdi (operands[0], operands[4])); | |
13952 | } | |
0ad91047 | 13953 | else |
5527bf14 RH |
13954 | { |
13955 | if (GET_MODE (operands[0]) != SImode) | |
13956 | FAIL; | |
13957 | emit_jump_insn (gen_ctrsi (operands[0], operands[4])); | |
13958 | } | |
0ad91047 DE |
13959 | DONE; |
13960 | }") | |
13961 | ||
13962 | (define_expand "ctrsi" | |
3cb999d8 DE |
13963 | [(parallel [(set (pc) |
13964 | (if_then_else (ne (match_operand:SI 0 "register_operand" "") | |
13965 | (const_int 1)) | |
13966 | (label_ref (match_operand 1 "" "")) | |
13967 | (pc))) | |
b6c9286a MM |
13968 | (set (match_dup 0) |
13969 | (plus:SI (match_dup 0) | |
13970 | (const_int -1))) | |
5f81043f RK |
13971 | (clobber (match_scratch:CC 2 "")) |
13972 | (clobber (match_scratch:SI 3 ""))])] | |
683bdff7 | 13973 | "TARGET_32BIT" |
0ad91047 DE |
13974 | "") |
13975 | ||
13976 | (define_expand "ctrdi" | |
3cb999d8 DE |
13977 | [(parallel [(set (pc) |
13978 | (if_then_else (ne (match_operand:DI 0 "register_operand" "") | |
13979 | (const_int 1)) | |
13980 | (label_ref (match_operand 1 "" "")) | |
13981 | (pc))) | |
0ad91047 DE |
13982 | (set (match_dup 0) |
13983 | (plus:DI (match_dup 0) | |
13984 | (const_int -1))) | |
13985 | (clobber (match_scratch:CC 2 "")) | |
61c07d3c | 13986 | (clobber (match_scratch:DI 3 ""))])] |
683bdff7 | 13987 | "TARGET_64BIT" |
61c07d3c | 13988 | "") |
c225ba7b | 13989 | |
1fd4e8c1 RK |
13990 | ;; We need to be able to do this for any operand, including MEM, or we |
13991 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 13992 | ;; JUMP_INSNs. |
0ad91047 | 13993 | ;; For the length attribute to be calculated correctly, the |
5f81043f RK |
13994 | ;; label MUST be operand 0. |
13995 | ||
0ad91047 | 13996 | (define_insn "*ctrsi_internal1" |
1fd4e8c1 | 13997 | [(set (pc) |
43b68ce5 | 13998 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
1fd4e8c1 | 13999 | (const_int 1)) |
a6845123 | 14000 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 14001 | (pc))) |
b150f4f3 | 14002 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
14003 | (plus:SI (match_dup 1) |
14004 | (const_int -1))) | |
43b68ce5 DE |
14005 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14006 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 14007 | "TARGET_32BIT" |
b19003d8 RK |
14008 | "* |
14009 | { | |
af87a13e | 14010 | if (which_alternative != 0) |
b19003d8 | 14011 | return \"#\"; |
856a6884 | 14012 | else if (get_attr_length (insn) == 4) |
a6845123 | 14013 | return \"{bdn|bdnz} %l0\"; |
b19003d8 | 14014 | else |
f607bc57 | 14015 | return \"bdz $+8\;b %l0\"; |
b19003d8 | 14016 | }" |
baf97f86 | 14017 | [(set_attr "type" "branch") |
5a195cb5 | 14018 | (set_attr "length" "*,12,16,16")]) |
7e69e155 | 14019 | |
0ad91047 | 14020 | (define_insn "*ctrsi_internal2" |
5f81043f | 14021 | [(set (pc) |
43b68ce5 | 14022 | (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
5f81043f RK |
14023 | (const_int 1)) |
14024 | (pc) | |
14025 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 14026 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
14027 | (plus:SI (match_dup 1) |
14028 | (const_int -1))) | |
43b68ce5 DE |
14029 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14030 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 14031 | "TARGET_32BIT" |
0ad91047 DE |
14032 | "* |
14033 | { | |
14034 | if (which_alternative != 0) | |
14035 | return \"#\"; | |
856a6884 | 14036 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14037 | return \"bdz %l0\"; |
14038 | else | |
f607bc57 | 14039 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
14040 | }" |
14041 | [(set_attr "type" "branch") | |
5a195cb5 | 14042 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
14043 | |
14044 | (define_insn "*ctrdi_internal1" | |
14045 | [(set (pc) | |
43b68ce5 | 14046 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
14047 | (const_int 1)) |
14048 | (label_ref (match_operand 0 "" "")) | |
14049 | (pc))) | |
b150f4f3 | 14050 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14051 | (plus:DI (match_dup 1) |
14052 | (const_int -1))) | |
43b68ce5 DE |
14053 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14054 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14055 | "TARGET_64BIT" |
0ad91047 DE |
14056 | "* |
14057 | { | |
14058 | if (which_alternative != 0) | |
14059 | return \"#\"; | |
856a6884 | 14060 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14061 | return \"{bdn|bdnz} %l0\"; |
14062 | else | |
f607bc57 | 14063 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
14064 | }" |
14065 | [(set_attr "type" "branch") | |
5a195cb5 | 14066 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
14067 | |
14068 | (define_insn "*ctrdi_internal2" | |
14069 | [(set (pc) | |
43b68ce5 | 14070 | (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
14071 | (const_int 1)) |
14072 | (pc) | |
14073 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 14074 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14075 | (plus:DI (match_dup 1) |
14076 | (const_int -1))) | |
43b68ce5 DE |
14077 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14078 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14079 | "TARGET_64BIT" |
5f81043f RK |
14080 | "* |
14081 | { | |
14082 | if (which_alternative != 0) | |
14083 | return \"#\"; | |
856a6884 | 14084 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
14085 | return \"bdz %l0\"; |
14086 | else | |
f607bc57 | 14087 | return \"{bdn|bdnz} $+8\;b %l0\"; |
5f81043f RK |
14088 | }" |
14089 | [(set_attr "type" "branch") | |
5a195cb5 | 14090 | (set_attr "length" "*,12,16,16")]) |
5f81043f | 14091 | |
0ad91047 DE |
14092 | ;; Similar but use EQ |
14093 | ||
14094 | (define_insn "*ctrsi_internal5" | |
5f81043f | 14095 | [(set (pc) |
43b68ce5 | 14096 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
1fd4e8c1 | 14097 | (const_int 1)) |
a6845123 | 14098 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 14099 | (pc))) |
b150f4f3 | 14100 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
14101 | (plus:SI (match_dup 1) |
14102 | (const_int -1))) | |
43b68ce5 DE |
14103 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14104 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 14105 | "TARGET_32BIT" |
b19003d8 RK |
14106 | "* |
14107 | { | |
af87a13e | 14108 | if (which_alternative != 0) |
b19003d8 | 14109 | return \"#\"; |
856a6884 | 14110 | else if (get_attr_length (insn) == 4) |
a6845123 | 14111 | return \"bdz %l0\"; |
b19003d8 | 14112 | else |
f607bc57 | 14113 | return \"{bdn|bdnz} $+8\;b %l0\"; |
b19003d8 | 14114 | }" |
baf97f86 | 14115 | [(set_attr "type" "branch") |
5a195cb5 | 14116 | (set_attr "length" "*,12,16,16")]) |
1fd4e8c1 | 14117 | |
0ad91047 | 14118 | (define_insn "*ctrsi_internal6" |
5f81043f | 14119 | [(set (pc) |
43b68ce5 | 14120 | (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r,*r") |
5f81043f RK |
14121 | (const_int 1)) |
14122 | (pc) | |
14123 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 14124 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
5f81043f RK |
14125 | (plus:SI (match_dup 1) |
14126 | (const_int -1))) | |
43b68ce5 DE |
14127 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14128 | (clobber (match_scratch:SI 4 "=X,X,&r,r"))] | |
683bdff7 | 14129 | "TARGET_32BIT" |
0ad91047 DE |
14130 | "* |
14131 | { | |
14132 | if (which_alternative != 0) | |
14133 | return \"#\"; | |
856a6884 | 14134 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14135 | return \"{bdn|bdnz} %l0\"; |
14136 | else | |
f607bc57 | 14137 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
14138 | }" |
14139 | [(set_attr "type" "branch") | |
5a195cb5 | 14140 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
14141 | |
14142 | (define_insn "*ctrdi_internal5" | |
14143 | [(set (pc) | |
43b68ce5 | 14144 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
14145 | (const_int 1)) |
14146 | (label_ref (match_operand 0 "" "")) | |
14147 | (pc))) | |
b150f4f3 | 14148 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14149 | (plus:DI (match_dup 1) |
14150 | (const_int -1))) | |
43b68ce5 DE |
14151 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14152 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14153 | "TARGET_64BIT" |
0ad91047 DE |
14154 | "* |
14155 | { | |
14156 | if (which_alternative != 0) | |
14157 | return \"#\"; | |
856a6884 | 14158 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
14159 | return \"bdz %l0\"; |
14160 | else | |
f607bc57 | 14161 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
14162 | }" |
14163 | [(set_attr "type" "branch") | |
5a195cb5 | 14164 | (set_attr "length" "*,12,16,16")]) |
0ad91047 DE |
14165 | |
14166 | (define_insn "*ctrdi_internal6" | |
14167 | [(set (pc) | |
43b68ce5 | 14168 | (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
14169 | (const_int 1)) |
14170 | (pc) | |
14171 | (label_ref (match_operand 0 "" "")))) | |
b150f4f3 | 14172 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,*r,m,*c*l") |
0ad91047 DE |
14173 | (plus:DI (match_dup 1) |
14174 | (const_int -1))) | |
43b68ce5 DE |
14175 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
14176 | (clobber (match_scratch:DI 4 "=X,X,&r,r"))] | |
683bdff7 | 14177 | "TARGET_64BIT" |
5f81043f RK |
14178 | "* |
14179 | { | |
14180 | if (which_alternative != 0) | |
14181 | return \"#\"; | |
856a6884 | 14182 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
14183 | return \"{bdn|bdnz} %l0\"; |
14184 | else | |
f607bc57 | 14185 | return \"bdz $+8\;b %l0\"; |
5f81043f RK |
14186 | }" |
14187 | [(set_attr "type" "branch") | |
5a195cb5 | 14188 | (set_attr "length" "*,12,16,16")]) |
5f81043f | 14189 | |
0ad91047 DE |
14190 | ;; Now the splitters if we could not allocate the CTR register |
14191 | ||
1fd4e8c1 RK |
14192 | (define_split |
14193 | [(set (pc) | |
14194 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 14195 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
14196 | (const_int 1)]) |
14197 | (match_operand 5 "" "") | |
14198 | (match_operand 6 "" ""))) | |
cd2b37d9 | 14199 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
5f81043f RK |
14200 | (plus:SI (match_dup 1) |
14201 | (const_int -1))) | |
1fd4e8c1 RK |
14202 | (clobber (match_scratch:CC 3 "")) |
14203 | (clobber (match_scratch:SI 4 ""))] | |
4b8a63d6 | 14204 | "TARGET_32BIT && reload_completed" |
1fd4e8c1 | 14205 | [(parallel [(set (match_dup 3) |
5f81043f RK |
14206 | (compare:CC (plus:SI (match_dup 1) |
14207 | (const_int -1)) | |
1fd4e8c1 | 14208 | (const_int 0))) |
5f81043f RK |
14209 | (set (match_dup 0) |
14210 | (plus:SI (match_dup 1) | |
14211 | (const_int -1)))]) | |
14212 | (set (pc) (if_then_else (match_dup 7) | |
14213 | (match_dup 5) | |
14214 | (match_dup 6)))] | |
1fd4e8c1 | 14215 | " |
0f4c242b KH |
14216 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14217 | operands[3], const0_rtx); }") | |
1fd4e8c1 RK |
14218 | |
14219 | (define_split | |
14220 | [(set (pc) | |
14221 | (if_then_else (match_operator 2 "comparison_operator" | |
cd2b37d9 | 14222 | [(match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
14223 | (const_int 1)]) |
14224 | (match_operand 5 "" "") | |
14225 | (match_operand 6 "" ""))) | |
9ebbca7d | 14226 | (set (match_operand:SI 0 "nonimmediate_operand" "") |
1fd4e8c1 RK |
14227 | (plus:SI (match_dup 1) (const_int -1))) |
14228 | (clobber (match_scratch:CC 3 "")) | |
14229 | (clobber (match_scratch:SI 4 ""))] | |
4b8a63d6 | 14230 | "TARGET_32BIT && reload_completed |
0ad91047 | 14231 | && ! gpc_reg_operand (operands[0], SImode)" |
1fd4e8c1 | 14232 | [(parallel [(set (match_dup 3) |
5f81043f RK |
14233 | (compare:CC (plus:SI (match_dup 1) |
14234 | (const_int -1)) | |
1fd4e8c1 | 14235 | (const_int 0))) |
5f81043f RK |
14236 | (set (match_dup 4) |
14237 | (plus:SI (match_dup 1) | |
14238 | (const_int -1)))]) | |
14239 | (set (match_dup 0) | |
14240 | (match_dup 4)) | |
14241 | (set (pc) (if_then_else (match_dup 7) | |
14242 | (match_dup 5) | |
14243 | (match_dup 6)))] | |
1fd4e8c1 | 14244 | " |
0f4c242b KH |
14245 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14246 | operands[3], const0_rtx); }") | |
0ad91047 DE |
14247 | (define_split |
14248 | [(set (pc) | |
14249 | (if_then_else (match_operator 2 "comparison_operator" | |
14250 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
14251 | (const_int 1)]) | |
61c07d3c DE |
14252 | (match_operand 5 "" "") |
14253 | (match_operand 6 "" ""))) | |
0ad91047 DE |
14254 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
14255 | (plus:DI (match_dup 1) | |
14256 | (const_int -1))) | |
14257 | (clobber (match_scratch:CC 3 "")) | |
61c07d3c | 14258 | (clobber (match_scratch:DI 4 ""))] |
683bdff7 | 14259 | "TARGET_64BIT && reload_completed" |
0ad91047 DE |
14260 | [(parallel [(set (match_dup 3) |
14261 | (compare:CC (plus:DI (match_dup 1) | |
14262 | (const_int -1)) | |
14263 | (const_int 0))) | |
14264 | (set (match_dup 0) | |
14265 | (plus:DI (match_dup 1) | |
14266 | (const_int -1)))]) | |
61c07d3c DE |
14267 | (set (pc) (if_then_else (match_dup 7) |
14268 | (match_dup 5) | |
14269 | (match_dup 6)))] | |
0ad91047 | 14270 | " |
0f4c242b KH |
14271 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14272 | operands[3], const0_rtx); }") | |
0ad91047 DE |
14273 | |
14274 | (define_split | |
14275 | [(set (pc) | |
14276 | (if_then_else (match_operator 2 "comparison_operator" | |
14277 | [(match_operand:DI 1 "gpc_reg_operand" "") | |
14278 | (const_int 1)]) | |
61c07d3c DE |
14279 | (match_operand 5 "" "") |
14280 | (match_operand 6 "" ""))) | |
9ebbca7d | 14281 | (set (match_operand:DI 0 "nonimmediate_operand" "") |
0ad91047 DE |
14282 | (plus:DI (match_dup 1) (const_int -1))) |
14283 | (clobber (match_scratch:CC 3 "")) | |
61c07d3c | 14284 | (clobber (match_scratch:DI 4 ""))] |
683bdff7 | 14285 | "TARGET_64BIT && reload_completed |
0ad91047 DE |
14286 | && ! gpc_reg_operand (operands[0], DImode)" |
14287 | [(parallel [(set (match_dup 3) | |
14288 | (compare:CC (plus:DI (match_dup 1) | |
14289 | (const_int -1)) | |
14290 | (const_int 0))) | |
14291 | (set (match_dup 4) | |
14292 | (plus:DI (match_dup 1) | |
14293 | (const_int -1)))]) | |
14294 | (set (match_dup 0) | |
14295 | (match_dup 4)) | |
61c07d3c DE |
14296 | (set (pc) (if_then_else (match_dup 7) |
14297 | (match_dup 5) | |
14298 | (match_dup 6)))] | |
0ad91047 | 14299 | " |
0f4c242b KH |
14300 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
14301 | operands[3], const0_rtx); }") | |
e0cd0770 JC |
14302 | \f |
14303 | (define_insn "trap" | |
14304 | [(trap_if (const_int 1) (const_int 0))] | |
14305 | "" | |
14306 | "{t 31,0,0|trap}") | |
14307 | ||
14308 | (define_expand "conditional_trap" | |
14309 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14310 | [(match_dup 2) (match_dup 3)]) | |
14311 | (match_operand 1 "const_int_operand" ""))] | |
14312 | "" | |
14313 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
14314 | operands[2] = rs6000_compare_op0; | |
14315 | operands[3] = rs6000_compare_op1;") | |
14316 | ||
14317 | (define_insn "" | |
14318 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14319 | [(match_operand:SI 1 "register_operand" "r") | |
14320 | (match_operand:SI 2 "reg_or_short_operand" "rI")]) | |
14321 | (const_int 0))] | |
14322 | "" | |
a157febd GK |
14323 | "{t|tw}%V0%I2 %1,%2") |
14324 | ||
14325 | (define_insn "" | |
14326 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
14327 | [(match_operand:DI 1 "register_operand" "r") | |
14328 | (match_operand:DI 2 "reg_or_short_operand" "rI")]) | |
14329 | (const_int 0))] | |
14330 | "TARGET_POWERPC64" | |
14331 | "td%V0%I2 %1,%2") | |
9ebbca7d GK |
14332 | \f |
14333 | ;; Insns related to generating the function prologue and epilogue. | |
14334 | ||
14335 | (define_expand "prologue" | |
14336 | [(use (const_int 0))] | |
14337 | "TARGET_SCHED_PROLOG" | |
14338 | " | |
14339 | { | |
14340 | rs6000_emit_prologue (); | |
14341 | DONE; | |
14342 | }") | |
14343 | ||
2c4a9cff DE |
14344 | (define_insn "*movesi_from_cr_one" |
14345 | [(match_parallel 0 "mfcr_operation" | |
14346 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
14347 | (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y") | |
14348 | (match_operand 3 "immediate_operand" "n")] | |
14349 | UNSPEC_MOVESI_FROM_CR))])] | |
14350 | "TARGET_MFCRF" | |
14351 | "* | |
14352 | { | |
14353 | int mask = 0; | |
14354 | int i; | |
14355 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
14356 | { | |
14357 | mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
14358 | operands[4] = GEN_INT (mask); | |
14359 | output_asm_insn (\"mfcr %1,%4\", operands); | |
14360 | } | |
14361 | return \"\"; | |
14362 | }" | |
14363 | [(set_attr "type" "mfcrf")]) | |
14364 | ||
9ebbca7d GK |
14365 | (define_insn "movesi_from_cr" |
14366 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
6ae08853 | 14367 | (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) |
615158e2 JJ |
14368 | (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] |
14369 | UNSPEC_MOVESI_FROM_CR))] | |
9ebbca7d | 14370 | "" |
309323c2 | 14371 | "mfcr %0" |
b54cf83a | 14372 | [(set_attr "type" "mfcr")]) |
9ebbca7d GK |
14373 | |
14374 | (define_insn "*stmw" | |
e033a023 DE |
14375 | [(match_parallel 0 "stmw_operation" |
14376 | [(set (match_operand:SI 1 "memory_operand" "=m") | |
14377 | (match_operand:SI 2 "gpc_reg_operand" "r"))])] | |
14378 | "TARGET_MULTIPLE" | |
14379 | "{stm|stmw} %2,%1") | |
6ae08853 | 14380 | |
9ebbca7d | 14381 | (define_insn "*save_fpregs_si" |
85d346f1 | 14382 | [(match_parallel 0 "any_parallel_operand" |
e033a023 DE |
14383 | [(clobber (match_operand:SI 1 "register_operand" "=l")) |
14384 | (use (match_operand:SI 2 "call_operand" "s")) | |
14385 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14386 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14387 | "TARGET_32BIT" | |
14388 | "bl %z2" | |
14389 | [(set_attr "type" "branch") | |
14390 | (set_attr "length" "4")]) | |
9ebbca7d GK |
14391 | |
14392 | (define_insn "*save_fpregs_di" | |
85d346f1 | 14393 | [(match_parallel 0 "any_parallel_operand" |
e033a023 DE |
14394 | [(clobber (match_operand:DI 1 "register_operand" "=l")) |
14395 | (use (match_operand:DI 2 "call_operand" "s")) | |
14396 | (set (match_operand:DF 3 "memory_operand" "=m") | |
14397 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
14398 | "TARGET_64BIT" | |
14399 | "bl %z2" | |
14400 | [(set_attr "type" "branch") | |
14401 | (set_attr "length" "4")]) | |
9ebbca7d GK |
14402 | |
14403 | ; These are to explain that changes to the stack pointer should | |
14404 | ; not be moved over stores to stack memory. | |
14405 | (define_insn "stack_tie" | |
14406 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
615158e2 | 14407 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] |
9ebbca7d GK |
14408 | "" |
14409 | "" | |
14410 | [(set_attr "length" "0")]) | |
14411 | ||
14412 | ||
14413 | (define_expand "epilogue" | |
14414 | [(use (const_int 0))] | |
14415 | "TARGET_SCHED_PROLOG" | |
14416 | " | |
14417 | { | |
14418 | rs6000_emit_epilogue (FALSE); | |
14419 | DONE; | |
14420 | }") | |
14421 | ||
14422 | ; On some processors, doing the mtcrf one CC register at a time is | |
14423 | ; faster (like on the 604e). On others, doing them all at once is | |
14424 | ; faster; for instance, on the 601 and 750. | |
14425 | ||
14426 | (define_expand "movsi_to_cr_one" | |
35aba846 DE |
14427 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
14428 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
615158e2 | 14429 | (match_dup 2)] UNSPEC_MOVESI_TO_CR))] |
35aba846 DE |
14430 | "" |
14431 | "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") | |
9ebbca7d GK |
14432 | |
14433 | (define_insn "*movsi_to_cr" | |
35aba846 DE |
14434 | [(match_parallel 0 "mtcrf_operation" |
14435 | [(set (match_operand:CC 1 "cc_reg_operand" "=y") | |
14436 | (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") | |
14437 | (match_operand 3 "immediate_operand" "n")] | |
615158e2 | 14438 | UNSPEC_MOVESI_TO_CR))])] |
9ebbca7d | 14439 | "" |
e35b9579 GK |
14440 | "* |
14441 | { | |
14442 | int mask = 0; | |
14443 | int i; | |
14444 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
14445 | mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
14446 | operands[4] = GEN_INT (mask); | |
14447 | return \"mtcrf %4,%2\"; | |
309323c2 | 14448 | }" |
b54cf83a | 14449 | [(set_attr "type" "mtcr")]) |
9ebbca7d | 14450 | |
b54cf83a | 14451 | (define_insn "*mtcrfsi" |
309323c2 DE |
14452 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
14453 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
615158e2 JJ |
14454 | (match_operand 2 "immediate_operand" "n")] |
14455 | UNSPEC_MOVESI_TO_CR))] | |
6ae08853 | 14456 | "GET_CODE (operands[0]) == REG |
309323c2 DE |
14457 | && CR_REGNO_P (REGNO (operands[0])) |
14458 | && GET_CODE (operands[2]) == CONST_INT | |
14459 | && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" | |
14460 | "mtcrf %R0,%1" | |
b54cf83a | 14461 | [(set_attr "type" "mtcr")]) |
9ebbca7d GK |
14462 | |
14463 | ; The load-multiple instructions have similar properties. | |
14464 | ; Note that "load_multiple" is a name known to the machine-independent | |
14465 | ; code that actually corresponds to the powerpc load-string. | |
14466 | ||
14467 | (define_insn "*lmw" | |
35aba846 DE |
14468 | [(match_parallel 0 "lmw_operation" |
14469 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
14470 | (match_operand:SI 2 "memory_operand" "m"))])] | |
14471 | "TARGET_MULTIPLE" | |
14472 | "{lm|lmw} %1,%2") | |
6ae08853 | 14473 | |
9ebbca7d | 14474 | (define_insn "*return_internal_si" |
e35b9579 GK |
14475 | [(return) |
14476 | (use (match_operand:SI 0 "register_operand" "lc"))] | |
9ebbca7d | 14477 | "TARGET_32BIT" |
cccf3bdc | 14478 | "b%T0" |
9ebbca7d GK |
14479 | [(set_attr "type" "jmpreg")]) |
14480 | ||
14481 | (define_insn "*return_internal_di" | |
e35b9579 GK |
14482 | [(return) |
14483 | (use (match_operand:DI 0 "register_operand" "lc"))] | |
9ebbca7d | 14484 | "TARGET_64BIT" |
cccf3bdc | 14485 | "b%T0" |
9ebbca7d GK |
14486 | [(set_attr "type" "jmpreg")]) |
14487 | ||
14488 | ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall | |
85d346f1 | 14489 | ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible... |
9ebbca7d GK |
14490 | |
14491 | (define_insn "*return_and_restore_fpregs_si" | |
85d346f1 | 14492 | [(match_parallel 0 "any_parallel_operand" |
e35b9579 GK |
14493 | [(return) |
14494 | (use (match_operand:SI 1 "register_operand" "l")) | |
9ebbca7d GK |
14495 | (use (match_operand:SI 2 "call_operand" "s")) |
14496 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
14497 | (match_operand:DF 4 "memory_operand" "m"))])] | |
14498 | "TARGET_32BIT" | |
14499 | "b %z2") | |
14500 | ||
14501 | (define_insn "*return_and_restore_fpregs_di" | |
85d346f1 | 14502 | [(match_parallel 0 "any_parallel_operand" |
e35b9579 GK |
14503 | [(return) |
14504 | (use (match_operand:DI 1 "register_operand" "l")) | |
9ebbca7d GK |
14505 | (use (match_operand:DI 2 "call_operand" "s")) |
14506 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") | |
14507 | (match_operand:DF 4 "memory_operand" "m"))])] | |
14508 | "TARGET_64BIT" | |
14509 | "b %z2") | |
14510 | ||
83720594 RH |
14511 | ; This is used in compiling the unwind routines. |
14512 | (define_expand "eh_return" | |
34dc173c | 14513 | [(use (match_operand 0 "general_operand" ""))] |
9ebbca7d GK |
14514 | "" |
14515 | " | |
14516 | { | |
83720594 | 14517 | if (TARGET_32BIT) |
34dc173c | 14518 | emit_insn (gen_eh_set_lr_si (operands[0])); |
9ebbca7d | 14519 | else |
34dc173c | 14520 | emit_insn (gen_eh_set_lr_di (operands[0])); |
9ebbca7d GK |
14521 | DONE; |
14522 | }") | |
14523 | ||
83720594 RH |
14524 | ; We can't expand this before we know where the link register is stored. |
14525 | (define_insn "eh_set_lr_si" | |
615158e2 JJ |
14526 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] |
14527 | UNSPECV_EH_RR) | |
466eb3e0 | 14528 | (clobber (match_scratch:SI 1 "=&b"))] |
83720594 RH |
14529 | "TARGET_32BIT" |
14530 | "#") | |
14531 | ||
14532 | (define_insn "eh_set_lr_di" | |
615158e2 JJ |
14533 | [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] |
14534 | UNSPECV_EH_RR) | |
466eb3e0 | 14535 | (clobber (match_scratch:DI 1 "=&b"))] |
83720594 RH |
14536 | "TARGET_64BIT" |
14537 | "#") | |
9ebbca7d GK |
14538 | |
14539 | (define_split | |
615158e2 | 14540 | [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR) |
83720594 RH |
14541 | (clobber (match_scratch 1 ""))] |
14542 | "reload_completed" | |
14543 | [(const_int 0)] | |
9ebbca7d GK |
14544 | " |
14545 | { | |
d1d0c603 | 14546 | rs6000_emit_eh_reg_restore (operands[0], operands[1]); |
83720594 RH |
14547 | DONE; |
14548 | }") | |
0ac081f6 | 14549 | |
01a2ccd0 DE |
14550 | (define_insn "prefetch" |
14551 | [(prefetch (match_operand:V4SI 0 "address_operand" "p") | |
6041bf2f DE |
14552 | (match_operand:SI 1 "const_int_operand" "n") |
14553 | (match_operand:SI 2 "const_int_operand" "n"))] | |
01a2ccd0 | 14554 | "TARGET_POWERPC" |
6041bf2f DE |
14555 | "* |
14556 | { | |
01a2ccd0 DE |
14557 | if (GET_CODE (operands[0]) == REG) |
14558 | return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\"; | |
14559 | return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; | |
6041bf2f DE |
14560 | }" |
14561 | [(set_attr "type" "load")]) | |
a3170dc6 | 14562 | |
10ed84db | 14563 | (include "altivec.md") |
a3170dc6 | 14564 | (include "spe.md") |