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996a5f59 | 1 | ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler |
d24652ee | 2 | ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, |
409f61cd | 3 | ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
996a5f59 | 4 | ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) |
1fd4e8c1 | 5 | |
5de601cf | 6 | ;; This file is part of GCC. |
1fd4e8c1 | 7 | |
5de601cf NC |
8 | ;; GCC is free software; you can redistribute it and/or modify it |
9 | ;; under the terms of the GNU General Public License as published | |
10 | ;; by the Free Software Foundation; either version 2, or (at your | |
11 | ;; option) any later version. | |
1fd4e8c1 | 12 | |
5de601cf NC |
13 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT |
14 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | ;; License for more details. | |
1fd4e8c1 RK |
17 | |
18 | ;; You should have received a copy of the GNU General Public License | |
5de601cf | 19 | ;; along with GCC; see the file COPYING. If not, write to the |
39d14dda KC |
20 | ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, |
21 | ;; MA 02110-1301, USA. | |
1fd4e8c1 RK |
22 | |
23 | ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. | |
9ebbca7d | 24 | |
615158e2 JJ |
25 | ;; |
26 | ;; UNSPEC usage | |
27 | ;; | |
28 | ||
29 | (define_constants | |
30 | [(UNSPEC_FRSP 0) ; frsp for POWER machines | |
31 | (UNSPEC_TIE 5) ; tie stack contents and stack pointer | |
32 | (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC | |
33 | (UNSPEC_TOC 7) ; address of the TOC (more-or-less) | |
34 | (UNSPEC_MOVSI_GOT 8) | |
35 | (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit | |
36 | (UNSPEC_FCTIWZ 10) | |
37 | (UNSPEC_LD_MPIC 15) ; load_macho_picbase | |
38 | (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic | |
39 | (UNSPEC_TLSGD 17) | |
40 | (UNSPEC_TLSLD 18) | |
41 | (UNSPEC_MOVESI_FROM_CR 19) | |
42 | (UNSPEC_MOVESI_TO_CR 20) | |
43 | (UNSPEC_TLSDTPREL 21) | |
44 | (UNSPEC_TLSDTPRELHA 22) | |
45 | (UNSPEC_TLSDTPRELLO 23) | |
46 | (UNSPEC_TLSGOTDTPREL 24) | |
47 | (UNSPEC_TLSTPREL 25) | |
48 | (UNSPEC_TLSTPRELHA 26) | |
49 | (UNSPEC_TLSTPRELLO 27) | |
50 | (UNSPEC_TLSGOTTPREL 28) | |
51 | (UNSPEC_TLSTLS 29) | |
ecb62ae7 | 52 | (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero |
64022b5d | 53 | (UNSPEC_MV_CR_GT 31) ; move_from_CR_eq_bit |
da4c340c | 54 | (UNSPEC_STFIWX 32) |
915167f5 GK |
55 | (UNSPEC_SYNC 33) |
56 | (UNSPEC_SYNC_OP 34) | |
57 | (UNSPEC_SYNC_SWAP 35) | |
58 | (UNSPEC_LWSYNC 36) | |
59 | (UNSPEC_ISYNC 37) | |
432218ba | 60 | (UNSPEC_POPCNTB 38) |
ef765ea9 | 61 | (UNSPEC_FRES 39) |
615158e2 JJ |
62 | ]) |
63 | ||
64 | ;; | |
65 | ;; UNSPEC_VOLATILE usage | |
66 | ;; | |
67 | ||
68 | (define_constants | |
69 | [(UNSPECV_BLOCK 0) | |
70 | (UNSPECV_EH_RR 9) ; eh_reg_restore | |
71 | ]) | |
1fd4e8c1 RK |
72 | \f |
73 | ;; Define an insn type attribute. This is used in function unit delay | |
74 | ;; computations. | |
943c15ed | 75 | (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv" |
1fd4e8c1 RK |
76 | (const_string "integer")) |
77 | ||
b19003d8 | 78 | ;; Length (in bytes). |
6ae08853 | 79 | ; '(pc)' in the following doesn't include the instruction itself; it is |
6cbadf36 | 80 | ; calculated as if the instruction had zero size. |
b19003d8 RK |
81 | (define_attr "length" "" |
82 | (if_then_else (eq_attr "type" "branch") | |
6cbadf36 | 83 | (if_then_else (and (ge (minus (match_dup 0) (pc)) |
b19003d8 | 84 | (const_int -32768)) |
6cbadf36 GK |
85 | (lt (minus (match_dup 0) (pc)) |
86 | (const_int 32764))) | |
39a10a29 GK |
87 | (const_int 4) |
88 | (const_int 8)) | |
b19003d8 RK |
89 | (const_int 4))) |
90 | ||
cfb557c4 RK |
91 | ;; Processor type -- this attribute must exactly match the processor_type |
92 | ;; enumeration in rs6000.h. | |
93 | ||
ec507f2d | 94 | (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4,power5" |
cfb557c4 RK |
95 | (const (symbol_ref "rs6000_cpu_attr"))) |
96 | ||
b54cf83a DE |
97 | (automata_option "ndfa") |
98 | ||
99 | (include "rios1.md") | |
100 | (include "rios2.md") | |
101 | (include "rs64.md") | |
102 | (include "mpc.md") | |
103 | (include "40x.md") | |
02ca7595 | 104 | (include "440.md") |
b54cf83a DE |
105 | (include "603.md") |
106 | (include "6xx.md") | |
107 | (include "7xx.md") | |
108 | (include "7450.md") | |
5e8006fa | 109 | (include "8540.md") |
b54cf83a | 110 | (include "power4.md") |
ec507f2d | 111 | (include "power5.md") |
48d72335 DE |
112 | |
113 | (include "predicates.md") | |
114 | ||
ac9e2cff | 115 | (include "darwin.md") |
309323c2 | 116 | |
1fd4e8c1 | 117 | \f |
915167f5 GK |
118 | ;; Mode macros |
119 | ||
120 | ; This mode macro allows :GPR to be used to indicate the allowable size | |
121 | ; of whole values in GPRs. | |
122 | (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")]) | |
123 | ||
0354e5d8 | 124 | ; Any supported integer mode. |
915167f5 GK |
125 | (define_mode_macro INT [QI HI SI DI TI]) |
126 | ||
0354e5d8 | 127 | ; Any supported integer mode that fits in one register. |
915167f5 GK |
128 | (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")]) |
129 | ||
0354e5d8 GK |
130 | ; SImode or DImode, even if DImode doesn't fit in GPRs. |
131 | (define_mode_macro SDI [SI DI]) | |
132 | ||
133 | ; The size of a pointer. Also, the size of the value that a record-condition | |
134 | ; (one with a '.') will compare. | |
135 | (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")]) | |
2e6c9641 | 136 | |
4ae234b0 GK |
137 | ; Any hardware-supported floating-point mode |
138 | (define_mode_macro FP [(SF "TARGET_HARD_FLOAT") | |
139 | (DF "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)") | |
140 | (TF "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
141 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128")]) | |
142 | ||
915167f5 | 143 | ; Various instructions that come in SI and DI forms. |
0354e5d8 GK |
144 | ; A generic w/d attribute, for things like cmpw/cmpd. |
145 | (define_mode_attr wd [(SI "w") (DI "d")]) | |
915167f5 GK |
146 | |
147 | \f | |
1fd4e8c1 RK |
148 | ;; Start with fixed-point load and store insns. Here we put only the more |
149 | ;; complex forms. Basic data transfer is done later. | |
150 | ||
51b8fc2c RK |
151 | (define_expand "zero_extendqidi2" |
152 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
153 | (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
154 | "TARGET_POWERPC64" | |
155 | "") | |
156 | ||
157 | (define_insn "" | |
158 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
159 | (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] | |
160 | "TARGET_POWERPC64" | |
161 | "@ | |
162 | lbz%U1%X1 %0,%1 | |
4371f8af | 163 | rldicl %0,%1,0,56" |
51b8fc2c RK |
164 | [(set_attr "type" "load,*")]) |
165 | ||
166 | (define_insn "" | |
9ebbca7d GK |
167 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
168 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 169 | (const_int 0))) |
9ebbca7d | 170 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 171 | "TARGET_64BIT" |
9ebbca7d GK |
172 | "@ |
173 | rldicl. %2,%1,0,56 | |
174 | #" | |
175 | [(set_attr "type" "compare") | |
176 | (set_attr "length" "4,8")]) | |
177 | ||
178 | (define_split | |
179 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
180 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
181 | (const_int 0))) | |
182 | (clobber (match_scratch:DI 2 ""))] | |
183 | "TARGET_POWERPC64 && reload_completed" | |
184 | [(set (match_dup 2) | |
185 | (zero_extend:DI (match_dup 1))) | |
186 | (set (match_dup 0) | |
187 | (compare:CC (match_dup 2) | |
188 | (const_int 0)))] | |
189 | "") | |
51b8fc2c RK |
190 | |
191 | (define_insn "" | |
9ebbca7d GK |
192 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
193 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 194 | (const_int 0))) |
9ebbca7d | 195 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 196 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 197 | "TARGET_64BIT" |
9ebbca7d GK |
198 | "@ |
199 | rldicl. %0,%1,0,56 | |
200 | #" | |
201 | [(set_attr "type" "compare") | |
202 | (set_attr "length" "4,8")]) | |
203 | ||
204 | (define_split | |
205 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
206 | (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
207 | (const_int 0))) | |
208 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
209 | (zero_extend:DI (match_dup 1)))] | |
210 | "TARGET_POWERPC64 && reload_completed" | |
211 | [(set (match_dup 0) | |
212 | (zero_extend:DI (match_dup 1))) | |
213 | (set (match_dup 2) | |
214 | (compare:CC (match_dup 0) | |
215 | (const_int 0)))] | |
216 | "") | |
51b8fc2c | 217 | |
2bee0449 RK |
218 | (define_insn "extendqidi2" |
219 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
220 | (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 221 | "TARGET_POWERPC64" |
2bee0449 | 222 | "extsb %0,%1") |
51b8fc2c RK |
223 | |
224 | (define_insn "" | |
9ebbca7d GK |
225 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
226 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 227 | (const_int 0))) |
9ebbca7d | 228 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 229 | "TARGET_64BIT" |
9ebbca7d GK |
230 | "@ |
231 | extsb. %2,%1 | |
232 | #" | |
233 | [(set_attr "type" "compare") | |
234 | (set_attr "length" "4,8")]) | |
235 | ||
236 | (define_split | |
237 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
238 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
239 | (const_int 0))) | |
240 | (clobber (match_scratch:DI 2 ""))] | |
241 | "TARGET_POWERPC64 && reload_completed" | |
242 | [(set (match_dup 2) | |
243 | (sign_extend:DI (match_dup 1))) | |
244 | (set (match_dup 0) | |
245 | (compare:CC (match_dup 2) | |
246 | (const_int 0)))] | |
247 | "") | |
51b8fc2c RK |
248 | |
249 | (define_insn "" | |
9ebbca7d GK |
250 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
251 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 252 | (const_int 0))) |
9ebbca7d | 253 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 254 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 255 | "TARGET_64BIT" |
9ebbca7d GK |
256 | "@ |
257 | extsb. %0,%1 | |
258 | #" | |
259 | [(set_attr "type" "compare") | |
260 | (set_attr "length" "4,8")]) | |
261 | ||
262 | (define_split | |
263 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
264 | (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) | |
265 | (const_int 0))) | |
266 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
267 | (sign_extend:DI (match_dup 1)))] | |
268 | "TARGET_POWERPC64 && reload_completed" | |
269 | [(set (match_dup 0) | |
270 | (sign_extend:DI (match_dup 1))) | |
271 | (set (match_dup 2) | |
272 | (compare:CC (match_dup 0) | |
273 | (const_int 0)))] | |
274 | "") | |
51b8fc2c RK |
275 | |
276 | (define_expand "zero_extendhidi2" | |
277 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
278 | (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
279 | "TARGET_POWERPC64" | |
280 | "") | |
281 | ||
282 | (define_insn "" | |
283 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
284 | (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
285 | "TARGET_POWERPC64" | |
286 | "@ | |
287 | lhz%U1%X1 %0,%1 | |
4371f8af | 288 | rldicl %0,%1,0,48" |
51b8fc2c RK |
289 | [(set_attr "type" "load,*")]) |
290 | ||
291 | (define_insn "" | |
9ebbca7d GK |
292 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
293 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 294 | (const_int 0))) |
9ebbca7d | 295 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 296 | "TARGET_64BIT" |
9ebbca7d GK |
297 | "@ |
298 | rldicl. %2,%1,0,48 | |
299 | #" | |
300 | [(set_attr "type" "compare") | |
301 | (set_attr "length" "4,8")]) | |
302 | ||
303 | (define_split | |
304 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
305 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
306 | (const_int 0))) | |
307 | (clobber (match_scratch:DI 2 ""))] | |
308 | "TARGET_POWERPC64 && reload_completed" | |
309 | [(set (match_dup 2) | |
310 | (zero_extend:DI (match_dup 1))) | |
311 | (set (match_dup 0) | |
312 | (compare:CC (match_dup 2) | |
313 | (const_int 0)))] | |
314 | "") | |
51b8fc2c RK |
315 | |
316 | (define_insn "" | |
9ebbca7d GK |
317 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
318 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 319 | (const_int 0))) |
9ebbca7d | 320 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 321 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 322 | "TARGET_64BIT" |
9ebbca7d GK |
323 | "@ |
324 | rldicl. %0,%1,0,48 | |
325 | #" | |
326 | [(set_attr "type" "compare") | |
327 | (set_attr "length" "4,8")]) | |
328 | ||
329 | (define_split | |
330 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
331 | (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
332 | (const_int 0))) | |
333 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
334 | (zero_extend:DI (match_dup 1)))] | |
335 | "TARGET_POWERPC64 && reload_completed" | |
336 | [(set (match_dup 0) | |
337 | (zero_extend:DI (match_dup 1))) | |
338 | (set (match_dup 2) | |
339 | (compare:CC (match_dup 0) | |
340 | (const_int 0)))] | |
341 | "") | |
51b8fc2c RK |
342 | |
343 | (define_expand "extendhidi2" | |
344 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
345 | (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
346 | "TARGET_POWERPC64" | |
347 | "") | |
348 | ||
349 | (define_insn "" | |
350 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
351 | (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] | |
352 | "TARGET_POWERPC64" | |
353 | "@ | |
354 | lha%U1%X1 %0,%1 | |
355 | extsh %0,%1" | |
b54cf83a | 356 | [(set_attr "type" "load_ext,*")]) |
51b8fc2c RK |
357 | |
358 | (define_insn "" | |
9ebbca7d GK |
359 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
360 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 361 | (const_int 0))) |
9ebbca7d | 362 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 363 | "TARGET_64BIT" |
9ebbca7d GK |
364 | "@ |
365 | extsh. %2,%1 | |
366 | #" | |
367 | [(set_attr "type" "compare") | |
368 | (set_attr "length" "4,8")]) | |
369 | ||
370 | (define_split | |
371 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
372 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
373 | (const_int 0))) | |
374 | (clobber (match_scratch:DI 2 ""))] | |
375 | "TARGET_POWERPC64 && reload_completed" | |
376 | [(set (match_dup 2) | |
377 | (sign_extend:DI (match_dup 1))) | |
378 | (set (match_dup 0) | |
379 | (compare:CC (match_dup 2) | |
380 | (const_int 0)))] | |
381 | "") | |
51b8fc2c RK |
382 | |
383 | (define_insn "" | |
9ebbca7d GK |
384 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
385 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 386 | (const_int 0))) |
9ebbca7d | 387 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 388 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 389 | "TARGET_64BIT" |
9ebbca7d GK |
390 | "@ |
391 | extsh. %0,%1 | |
392 | #" | |
393 | [(set_attr "type" "compare") | |
394 | (set_attr "length" "4,8")]) | |
395 | ||
396 | (define_split | |
397 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
398 | (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) | |
399 | (const_int 0))) | |
400 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
401 | (sign_extend:DI (match_dup 1)))] | |
402 | "TARGET_POWERPC64 && reload_completed" | |
403 | [(set (match_dup 0) | |
404 | (sign_extend:DI (match_dup 1))) | |
405 | (set (match_dup 2) | |
406 | (compare:CC (match_dup 0) | |
407 | (const_int 0)))] | |
408 | "") | |
51b8fc2c RK |
409 | |
410 | (define_expand "zero_extendsidi2" | |
411 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
412 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
413 | "TARGET_POWERPC64" | |
414 | "") | |
415 | ||
416 | (define_insn "" | |
417 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
418 | (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))] | |
419 | "TARGET_POWERPC64" | |
420 | "@ | |
421 | lwz%U1%X1 %0,%1 | |
422 | rldicl %0,%1,0,32" | |
423 | [(set_attr "type" "load,*")]) | |
424 | ||
425 | (define_insn "" | |
9ebbca7d GK |
426 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
427 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 428 | (const_int 0))) |
9ebbca7d | 429 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 430 | "TARGET_64BIT" |
9ebbca7d GK |
431 | "@ |
432 | rldicl. %2,%1,0,32 | |
433 | #" | |
434 | [(set_attr "type" "compare") | |
435 | (set_attr "length" "4,8")]) | |
436 | ||
437 | (define_split | |
438 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
439 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
440 | (const_int 0))) | |
441 | (clobber (match_scratch:DI 2 ""))] | |
442 | "TARGET_POWERPC64 && reload_completed" | |
443 | [(set (match_dup 2) | |
444 | (zero_extend:DI (match_dup 1))) | |
445 | (set (match_dup 0) | |
446 | (compare:CC (match_dup 2) | |
447 | (const_int 0)))] | |
448 | "") | |
51b8fc2c RK |
449 | |
450 | (define_insn "" | |
9ebbca7d GK |
451 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
452 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 453 | (const_int 0))) |
9ebbca7d | 454 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 455 | (zero_extend:DI (match_dup 1)))] |
683bdff7 | 456 | "TARGET_64BIT" |
9ebbca7d GK |
457 | "@ |
458 | rldicl. %0,%1,0,32 | |
459 | #" | |
460 | [(set_attr "type" "compare") | |
461 | (set_attr "length" "4,8")]) | |
462 | ||
463 | (define_split | |
464 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
465 | (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
466 | (const_int 0))) | |
467 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
468 | (zero_extend:DI (match_dup 1)))] | |
469 | "TARGET_POWERPC64 && reload_completed" | |
470 | [(set (match_dup 0) | |
471 | (zero_extend:DI (match_dup 1))) | |
472 | (set (match_dup 2) | |
473 | (compare:CC (match_dup 0) | |
474 | (const_int 0)))] | |
475 | "") | |
51b8fc2c RK |
476 | |
477 | (define_expand "extendsidi2" | |
478 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
479 | (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
480 | "TARGET_POWERPC64" | |
481 | "") | |
482 | ||
483 | (define_insn "" | |
484 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
287f13ff | 485 | (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))] |
51b8fc2c RK |
486 | "TARGET_POWERPC64" |
487 | "@ | |
488 | lwa%U1%X1 %0,%1 | |
489 | extsw %0,%1" | |
b54cf83a | 490 | [(set_attr "type" "load_ext,*")]) |
51b8fc2c RK |
491 | |
492 | (define_insn "" | |
9ebbca7d GK |
493 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
494 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 495 | (const_int 0))) |
9ebbca7d | 496 | (clobber (match_scratch:DI 2 "=r,r"))] |
683bdff7 | 497 | "TARGET_64BIT" |
9ebbca7d GK |
498 | "@ |
499 | extsw. %2,%1 | |
500 | #" | |
501 | [(set_attr "type" "compare") | |
502 | (set_attr "length" "4,8")]) | |
503 | ||
504 | (define_split | |
505 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
506 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
507 | (const_int 0))) | |
508 | (clobber (match_scratch:DI 2 ""))] | |
509 | "TARGET_POWERPC64 && reload_completed" | |
510 | [(set (match_dup 2) | |
511 | (sign_extend:DI (match_dup 1))) | |
512 | (set (match_dup 0) | |
513 | (compare:CC (match_dup 2) | |
514 | (const_int 0)))] | |
515 | "") | |
51b8fc2c RK |
516 | |
517 | (define_insn "" | |
9ebbca7d GK |
518 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
519 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 520 | (const_int 0))) |
9ebbca7d | 521 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c | 522 | (sign_extend:DI (match_dup 1)))] |
683bdff7 | 523 | "TARGET_64BIT" |
9ebbca7d GK |
524 | "@ |
525 | extsw. %0,%1 | |
526 | #" | |
527 | [(set_attr "type" "compare") | |
528 | (set_attr "length" "4,8")]) | |
529 | ||
530 | (define_split | |
531 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
532 | (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
533 | (const_int 0))) | |
534 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
535 | (sign_extend:DI (match_dup 1)))] | |
536 | "TARGET_POWERPC64 && reload_completed" | |
537 | [(set (match_dup 0) | |
538 | (sign_extend:DI (match_dup 1))) | |
539 | (set (match_dup 2) | |
540 | (compare:CC (match_dup 0) | |
541 | (const_int 0)))] | |
542 | "") | |
51b8fc2c | 543 | |
1fd4e8c1 | 544 | (define_expand "zero_extendqisi2" |
cd2b37d9 RK |
545 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
546 | (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
547 | "" |
548 | "") | |
549 | ||
550 | (define_insn "" | |
cd2b37d9 | 551 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
552 | (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
553 | "" | |
554 | "@ | |
555 | lbz%U1%X1 %0,%1 | |
005a35b9 | 556 | {rlinm|rlwinm} %0,%1,0,0xff" |
1fd4e8c1 RK |
557 | [(set_attr "type" "load,*")]) |
558 | ||
559 | (define_insn "" | |
9ebbca7d GK |
560 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
561 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 562 | (const_int 0))) |
9ebbca7d | 563 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 564 | "" |
9ebbca7d GK |
565 | "@ |
566 | {andil.|andi.} %2,%1,0xff | |
567 | #" | |
568 | [(set_attr "type" "compare") | |
569 | (set_attr "length" "4,8")]) | |
570 | ||
571 | (define_split | |
572 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
573 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
574 | (const_int 0))) | |
575 | (clobber (match_scratch:SI 2 ""))] | |
576 | "reload_completed" | |
577 | [(set (match_dup 2) | |
578 | (zero_extend:SI (match_dup 1))) | |
579 | (set (match_dup 0) | |
580 | (compare:CC (match_dup 2) | |
581 | (const_int 0)))] | |
582 | "") | |
1fd4e8c1 RK |
583 | |
584 | (define_insn "" | |
9ebbca7d GK |
585 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
586 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 587 | (const_int 0))) |
9ebbca7d | 588 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
589 | (zero_extend:SI (match_dup 1)))] |
590 | "" | |
9ebbca7d GK |
591 | "@ |
592 | {andil.|andi.} %0,%1,0xff | |
593 | #" | |
594 | [(set_attr "type" "compare") | |
595 | (set_attr "length" "4,8")]) | |
596 | ||
597 | (define_split | |
598 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
599 | (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
600 | (const_int 0))) | |
601 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
602 | (zero_extend:SI (match_dup 1)))] | |
603 | "reload_completed" | |
604 | [(set (match_dup 0) | |
605 | (zero_extend:SI (match_dup 1))) | |
606 | (set (match_dup 2) | |
607 | (compare:CC (match_dup 0) | |
608 | (const_int 0)))] | |
609 | "") | |
1fd4e8c1 | 610 | |
51b8fc2c RK |
611 | (define_expand "extendqisi2" |
612 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
613 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
614 | "" | |
615 | " | |
616 | { | |
617 | if (TARGET_POWERPC) | |
618 | emit_insn (gen_extendqisi2_ppc (operands[0], operands[1])); | |
619 | else if (TARGET_POWER) | |
620 | emit_insn (gen_extendqisi2_power (operands[0], operands[1])); | |
621 | else | |
622 | emit_insn (gen_extendqisi2_no_power (operands[0], operands[1])); | |
623 | DONE; | |
624 | }") | |
625 | ||
626 | (define_insn "extendqisi2_ppc" | |
2bee0449 RK |
627 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
628 | (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
51b8fc2c | 629 | "TARGET_POWERPC" |
2bee0449 | 630 | "extsb %0,%1") |
51b8fc2c RK |
631 | |
632 | (define_insn "" | |
9ebbca7d GK |
633 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
634 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 635 | (const_int 0))) |
9ebbca7d | 636 | (clobber (match_scratch:SI 2 "=r,r"))] |
51b8fc2c | 637 | "TARGET_POWERPC" |
9ebbca7d GK |
638 | "@ |
639 | extsb. %2,%1 | |
640 | #" | |
641 | [(set_attr "type" "compare") | |
642 | (set_attr "length" "4,8")]) | |
643 | ||
644 | (define_split | |
645 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
646 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
647 | (const_int 0))) | |
648 | (clobber (match_scratch:SI 2 ""))] | |
649 | "TARGET_POWERPC && reload_completed" | |
650 | [(set (match_dup 2) | |
651 | (sign_extend:SI (match_dup 1))) | |
652 | (set (match_dup 0) | |
653 | (compare:CC (match_dup 2) | |
654 | (const_int 0)))] | |
655 | "") | |
51b8fc2c RK |
656 | |
657 | (define_insn "" | |
9ebbca7d GK |
658 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
659 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 660 | (const_int 0))) |
9ebbca7d | 661 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
662 | (sign_extend:SI (match_dup 1)))] |
663 | "TARGET_POWERPC" | |
9ebbca7d GK |
664 | "@ |
665 | extsb. %0,%1 | |
666 | #" | |
667 | [(set_attr "type" "compare") | |
668 | (set_attr "length" "4,8")]) | |
669 | ||
670 | (define_split | |
671 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
672 | (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) | |
673 | (const_int 0))) | |
674 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
675 | (sign_extend:SI (match_dup 1)))] | |
676 | "TARGET_POWERPC && reload_completed" | |
677 | [(set (match_dup 0) | |
678 | (sign_extend:SI (match_dup 1))) | |
679 | (set (match_dup 2) | |
680 | (compare:CC (match_dup 0) | |
681 | (const_int 0)))] | |
682 | "") | |
51b8fc2c RK |
683 | |
684 | (define_expand "extendqisi2_power" | |
685 | [(parallel [(set (match_dup 2) | |
686 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
687 | (const_int 24))) | |
688 | (clobber (scratch:SI))]) | |
689 | (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
690 | (ashiftrt:SI (match_dup 2) | |
691 | (const_int 24))) | |
692 | (clobber (scratch:SI))])] | |
693 | "TARGET_POWER" | |
694 | " | |
695 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
696 | operands[2] = gen_reg_rtx (SImode); }") | |
697 | ||
698 | (define_expand "extendqisi2_no_power" | |
699 | [(set (match_dup 2) | |
700 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
701 | (const_int 24))) | |
702 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
703 | (ashiftrt:SI (match_dup 2) | |
704 | (const_int 24)))] | |
705 | "! TARGET_POWER && ! TARGET_POWERPC" | |
706 | " | |
707 | { operands[1] = gen_lowpart (SImode, operands[1]); | |
708 | operands[2] = gen_reg_rtx (SImode); }") | |
709 | ||
1fd4e8c1 | 710 | (define_expand "zero_extendqihi2" |
cd2b37d9 RK |
711 | [(set (match_operand:HI 0 "gpc_reg_operand" "") |
712 | (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
713 | "" |
714 | "") | |
715 | ||
716 | (define_insn "" | |
cd2b37d9 | 717 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
718 | (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] |
719 | "" | |
720 | "@ | |
721 | lbz%U1%X1 %0,%1 | |
005a35b9 | 722 | {rlinm|rlwinm} %0,%1,0,0xff" |
51b8fc2c RK |
723 | [(set_attr "type" "load,*")]) |
724 | ||
725 | (define_insn "" | |
9ebbca7d GK |
726 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
727 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 728 | (const_int 0))) |
9ebbca7d | 729 | (clobber (match_scratch:HI 2 "=r,r"))] |
51b8fc2c | 730 | "" |
9ebbca7d GK |
731 | "@ |
732 | {andil.|andi.} %2,%1,0xff | |
733 | #" | |
734 | [(set_attr "type" "compare") | |
735 | (set_attr "length" "4,8")]) | |
736 | ||
737 | (define_split | |
738 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
739 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
740 | (const_int 0))) | |
741 | (clobber (match_scratch:HI 2 ""))] | |
742 | "reload_completed" | |
743 | [(set (match_dup 2) | |
744 | (zero_extend:HI (match_dup 1))) | |
745 | (set (match_dup 0) | |
746 | (compare:CC (match_dup 2) | |
747 | (const_int 0)))] | |
748 | "") | |
1fd4e8c1 | 749 | |
51b8fc2c | 750 | (define_insn "" |
9ebbca7d GK |
751 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
752 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 753 | (const_int 0))) |
9ebbca7d | 754 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
755 | (zero_extend:HI (match_dup 1)))] |
756 | "" | |
9ebbca7d GK |
757 | "@ |
758 | {andil.|andi.} %0,%1,0xff | |
759 | #" | |
760 | [(set_attr "type" "compare") | |
761 | (set_attr "length" "4,8")]) | |
762 | ||
763 | (define_split | |
764 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
765 | (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
766 | (const_int 0))) | |
767 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
768 | (zero_extend:HI (match_dup 1)))] | |
769 | "reload_completed" | |
770 | [(set (match_dup 0) | |
771 | (zero_extend:HI (match_dup 1))) | |
772 | (set (match_dup 2) | |
773 | (compare:CC (match_dup 0) | |
774 | (const_int 0)))] | |
775 | "") | |
815cdc52 MM |
776 | |
777 | (define_expand "extendqihi2" | |
778 | [(use (match_operand:HI 0 "gpc_reg_operand" "")) | |
779 | (use (match_operand:QI 1 "gpc_reg_operand" ""))] | |
780 | "" | |
781 | " | |
782 | { | |
783 | if (TARGET_POWERPC) | |
784 | emit_insn (gen_extendqihi2_ppc (operands[0], operands[1])); | |
785 | else if (TARGET_POWER) | |
786 | emit_insn (gen_extendqihi2_power (operands[0], operands[1])); | |
787 | else | |
788 | emit_insn (gen_extendqihi2_no_power (operands[0], operands[1])); | |
789 | DONE; | |
790 | }") | |
791 | ||
792 | (define_insn "extendqihi2_ppc" | |
793 | [(set (match_operand:HI 0 "gpc_reg_operand" "=r") | |
794 | (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] | |
795 | "TARGET_POWERPC" | |
796 | "extsb %0,%1") | |
797 | ||
798 | (define_insn "" | |
9ebbca7d GK |
799 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
800 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
815cdc52 | 801 | (const_int 0))) |
9ebbca7d | 802 | (clobber (match_scratch:HI 2 "=r,r"))] |
815cdc52 | 803 | "TARGET_POWERPC" |
9ebbca7d GK |
804 | "@ |
805 | extsb. %2,%1 | |
806 | #" | |
807 | [(set_attr "type" "compare") | |
808 | (set_attr "length" "4,8")]) | |
809 | ||
810 | (define_split | |
811 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
812 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
813 | (const_int 0))) | |
814 | (clobber (match_scratch:HI 2 ""))] | |
815 | "TARGET_POWERPC && reload_completed" | |
816 | [(set (match_dup 2) | |
817 | (sign_extend:HI (match_dup 1))) | |
818 | (set (match_dup 0) | |
819 | (compare:CC (match_dup 2) | |
820 | (const_int 0)))] | |
821 | "") | |
815cdc52 MM |
822 | |
823 | (define_insn "" | |
9ebbca7d GK |
824 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
825 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) | |
51b8fc2c | 826 | (const_int 0))) |
9ebbca7d | 827 | (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") |
51b8fc2c RK |
828 | (sign_extend:HI (match_dup 1)))] |
829 | "TARGET_POWERPC" | |
9ebbca7d GK |
830 | "@ |
831 | extsb. %0,%1 | |
832 | #" | |
833 | [(set_attr "type" "compare") | |
834 | (set_attr "length" "4,8")]) | |
835 | ||
836 | (define_split | |
837 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
838 | (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) | |
839 | (const_int 0))) | |
840 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
841 | (sign_extend:HI (match_dup 1)))] | |
842 | "TARGET_POWERPC && reload_completed" | |
843 | [(set (match_dup 0) | |
844 | (sign_extend:HI (match_dup 1))) | |
845 | (set (match_dup 2) | |
846 | (compare:CC (match_dup 0) | |
847 | (const_int 0)))] | |
848 | "") | |
51b8fc2c RK |
849 | |
850 | (define_expand "extendqihi2_power" | |
851 | [(parallel [(set (match_dup 2) | |
852 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
853 | (const_int 24))) | |
854 | (clobber (scratch:SI))]) | |
855 | (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") | |
856 | (ashiftrt:SI (match_dup 2) | |
857 | (const_int 24))) | |
858 | (clobber (scratch:SI))])] | |
859 | "TARGET_POWER" | |
860 | " | |
861 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
862 | operands[1] = gen_lowpart (SImode, operands[1]); | |
863 | operands[2] = gen_reg_rtx (SImode); }") | |
864 | ||
865 | (define_expand "extendqihi2_no_power" | |
866 | [(set (match_dup 2) | |
867 | (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") | |
868 | (const_int 24))) | |
869 | (set (match_operand:HI 0 "gpc_reg_operand" "") | |
870 | (ashiftrt:SI (match_dup 2) | |
871 | (const_int 24)))] | |
872 | "! TARGET_POWER && ! TARGET_POWERPC" | |
873 | " | |
874 | { operands[0] = gen_lowpart (SImode, operands[0]); | |
875 | operands[1] = gen_lowpart (SImode, operands[1]); | |
876 | operands[2] = gen_reg_rtx (SImode); }") | |
877 | ||
1fd4e8c1 | 878 | (define_expand "zero_extendhisi2" |
5f243543 | 879 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
cd2b37d9 | 880 | (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] |
1fd4e8c1 RK |
881 | "" |
882 | "") | |
883 | ||
884 | (define_insn "" | |
cd2b37d9 | 885 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
886 | (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
887 | "" | |
888 | "@ | |
889 | lhz%U1%X1 %0,%1 | |
005a35b9 | 890 | {rlinm|rlwinm} %0,%1,0,0xffff" |
1fd4e8c1 RK |
891 | [(set_attr "type" "load,*")]) |
892 | ||
893 | (define_insn "" | |
9ebbca7d GK |
894 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
895 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 896 | (const_int 0))) |
9ebbca7d | 897 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 898 | "" |
9ebbca7d GK |
899 | "@ |
900 | {andil.|andi.} %2,%1,0xffff | |
901 | #" | |
902 | [(set_attr "type" "compare") | |
903 | (set_attr "length" "4,8")]) | |
904 | ||
905 | (define_split | |
906 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
907 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
908 | (const_int 0))) | |
909 | (clobber (match_scratch:SI 2 ""))] | |
910 | "reload_completed" | |
911 | [(set (match_dup 2) | |
912 | (zero_extend:SI (match_dup 1))) | |
913 | (set (match_dup 0) | |
914 | (compare:CC (match_dup 2) | |
915 | (const_int 0)))] | |
916 | "") | |
1fd4e8c1 RK |
917 | |
918 | (define_insn "" | |
9ebbca7d GK |
919 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
920 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 921 | (const_int 0))) |
9ebbca7d | 922 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
923 | (zero_extend:SI (match_dup 1)))] |
924 | "" | |
9ebbca7d GK |
925 | "@ |
926 | {andil.|andi.} %0,%1,0xffff | |
927 | #" | |
928 | [(set_attr "type" "compare") | |
929 | (set_attr "length" "4,8")]) | |
930 | ||
931 | (define_split | |
932 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
933 | (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
934 | (const_int 0))) | |
935 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
936 | (zero_extend:SI (match_dup 1)))] | |
937 | "reload_completed" | |
938 | [(set (match_dup 0) | |
939 | (zero_extend:SI (match_dup 1))) | |
940 | (set (match_dup 2) | |
941 | (compare:CC (match_dup 0) | |
942 | (const_int 0)))] | |
943 | "") | |
1fd4e8c1 RK |
944 | |
945 | (define_expand "extendhisi2" | |
cd2b37d9 RK |
946 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
947 | (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] | |
1fd4e8c1 RK |
948 | "" |
949 | "") | |
950 | ||
951 | (define_insn "" | |
cd2b37d9 | 952 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
953 | (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] |
954 | "" | |
955 | "@ | |
956 | lha%U1%X1 %0,%1 | |
ca7f5001 | 957 | {exts|extsh} %0,%1" |
b54cf83a | 958 | [(set_attr "type" "load_ext,*")]) |
1fd4e8c1 RK |
959 | |
960 | (define_insn "" | |
9ebbca7d GK |
961 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
962 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 963 | (const_int 0))) |
9ebbca7d | 964 | (clobber (match_scratch:SI 2 "=r,r"))] |
1fd4e8c1 | 965 | "" |
9ebbca7d GK |
966 | "@ |
967 | {exts.|extsh.} %2,%1 | |
968 | #" | |
969 | [(set_attr "type" "compare") | |
970 | (set_attr "length" "4,8")]) | |
971 | ||
972 | (define_split | |
973 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
974 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
975 | (const_int 0))) | |
976 | (clobber (match_scratch:SI 2 ""))] | |
977 | "reload_completed" | |
978 | [(set (match_dup 2) | |
979 | (sign_extend:SI (match_dup 1))) | |
980 | (set (match_dup 0) | |
981 | (compare:CC (match_dup 2) | |
982 | (const_int 0)))] | |
983 | "") | |
1fd4e8c1 RK |
984 | |
985 | (define_insn "" | |
9ebbca7d GK |
986 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
987 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 988 | (const_int 0))) |
9ebbca7d | 989 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
990 | (sign_extend:SI (match_dup 1)))] |
991 | "" | |
9ebbca7d GK |
992 | "@ |
993 | {exts.|extsh.} %0,%1 | |
994 | #" | |
995 | [(set_attr "type" "compare") | |
996 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 997 | \f |
9ebbca7d GK |
998 | (define_split |
999 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
1000 | (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) | |
1001 | (const_int 0))) | |
1002 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1003 | (sign_extend:SI (match_dup 1)))] | |
1004 | "reload_completed" | |
1005 | [(set (match_dup 0) | |
1006 | (sign_extend:SI (match_dup 1))) | |
1007 | (set (match_dup 2) | |
1008 | (compare:CC (match_dup 0) | |
1009 | (const_int 0)))] | |
1010 | "") | |
1011 | ||
1fd4e8c1 | 1012 | ;; Fixed-point arithmetic insns. |
deb9225a | 1013 | |
0354e5d8 GK |
1014 | (define_expand "add<mode>3" |
1015 | [(set (match_operand:SDI 0 "gpc_reg_operand" "") | |
1016 | (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "") | |
4ae234b0 | 1017 | (match_operand:SDI 2 "reg_or_add_cint_operand" "")))] |
7cd5235b MM |
1018 | "" |
1019 | " | |
1020 | { | |
0354e5d8 GK |
1021 | if (<MODE>mode == DImode && ! TARGET_POWERPC64) |
1022 | { | |
1023 | if (non_short_cint_operand (operands[2], DImode)) | |
1024 | FAIL; | |
1025 | } | |
1026 | else if (GET_CODE (operands[2]) == CONST_INT | |
1027 | && ! add_operand (operands[2], <MODE>mode)) | |
7cd5235b | 1028 | { |
677a9668 | 1029 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
0354e5d8 | 1030 | ? operands[0] : gen_reg_rtx (<MODE>mode)); |
7cd5235b | 1031 | |
2bfcf297 | 1032 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 1033 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
0354e5d8 GK |
1034 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode); |
1035 | ||
1036 | if (<MODE>mode == DImode && !CONST_OK_FOR_LETTER_P (rest, 'L')) | |
1037 | FAIL; | |
7cd5235b | 1038 | |
9ebbca7d GK |
1039 | /* The ordering here is important for the prolog expander. |
1040 | When space is allocated from the stack, adding 'low' first may | |
1041 | produce a temporary deallocation (which would be bad). */ | |
0354e5d8 GK |
1042 | emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest))); |
1043 | emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low))); | |
7cd5235b MM |
1044 | DONE; |
1045 | } | |
1046 | }") | |
1047 | ||
0354e5d8 GK |
1048 | ;; Discourage ai/addic because of carry but provide it in an alternative |
1049 | ;; allowing register zero as source. | |
1050 | (define_insn "*add<mode>3_internal1" | |
1051 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r") | |
1052 | (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b") | |
1053 | (match_operand:GPR 2 "add_operand" "r,I,I,L")))] | |
1fd4e8c1 RK |
1054 | "" |
1055 | "@ | |
deb9225a RK |
1056 | {cax|add} %0,%1,%2 |
1057 | {cal %0,%2(%1)|addi %0,%1,%2} | |
1058 | {ai|addic} %0,%1,%2 | |
7cd5235b MM |
1059 | {cau|addis} %0,%1,%v2" |
1060 | [(set_attr "length" "4,4,4,4")]) | |
1fd4e8c1 | 1061 | |
ee890fe2 SS |
1062 | (define_insn "addsi3_high" |
1063 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") | |
1064 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
1065 | (high:SI (match_operand 2 "" ""))))] | |
1066 | "TARGET_MACHO && !TARGET_64BIT" | |
1067 | "{cau|addis} %0,%1,ha16(%2)" | |
1068 | [(set_attr "length" "4")]) | |
1069 | ||
0354e5d8 | 1070 | (define_insn "*add<mode>3_internal2" |
cb8cc086 | 1071 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
0354e5d8 GK |
1072 | (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r") |
1073 | (match_operand:P 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1074 | (const_int 0))) |
0354e5d8 GK |
1075 | (clobber (match_scratch:P 3 "=r,r,r,r"))] |
1076 | "" | |
deb9225a RK |
1077 | "@ |
1078 | {cax.|add.} %3,%1,%2 | |
cb8cc086 MM |
1079 | {ai.|addic.} %3,%1,%2 |
1080 | # | |
1081 | #" | |
a62bfff2 | 1082 | [(set_attr "type" "fast_compare,compare,compare,compare") |
cb8cc086 MM |
1083 | (set_attr "length" "4,4,8,8")]) |
1084 | ||
1085 | (define_split | |
1086 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
0354e5d8 GK |
1087 | (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "") |
1088 | (match_operand:GPR 2 "reg_or_short_operand" "")) | |
cb8cc086 | 1089 | (const_int 0))) |
0354e5d8 GK |
1090 | (clobber (match_scratch:GPR 3 ""))] |
1091 | "reload_completed" | |
cb8cc086 | 1092 | [(set (match_dup 3) |
0354e5d8 | 1093 | (plus:GPR (match_dup 1) |
cb8cc086 MM |
1094 | (match_dup 2))) |
1095 | (set (match_dup 0) | |
1096 | (compare:CC (match_dup 3) | |
1097 | (const_int 0)))] | |
1098 | "") | |
7e69e155 | 1099 | |
0354e5d8 | 1100 | (define_insn "*add<mode>3_internal3" |
cb8cc086 | 1101 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
0354e5d8 GK |
1102 | (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r") |
1103 | (match_operand:P 2 "reg_or_short_operand" "r,I,r,I")) | |
1fd4e8c1 | 1104 | (const_int 0))) |
0354e5d8 GK |
1105 | (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r") |
1106 | (plus:P (match_dup 1) | |
1107 | (match_dup 2)))] | |
1108 | "" | |
deb9225a RK |
1109 | "@ |
1110 | {cax.|add.} %0,%1,%2 | |
cb8cc086 MM |
1111 | {ai.|addic.} %0,%1,%2 |
1112 | # | |
1113 | #" | |
a62bfff2 | 1114 | [(set_attr "type" "fast_compare,compare,compare,compare") |
cb8cc086 MM |
1115 | (set_attr "length" "4,4,8,8")]) |
1116 | ||
1117 | (define_split | |
1118 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
0354e5d8 GK |
1119 | (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "") |
1120 | (match_operand:P 2 "reg_or_short_operand" "")) | |
cb8cc086 | 1121 | (const_int 0))) |
0354e5d8 GK |
1122 | (set (match_operand:P 0 "gpc_reg_operand" "") |
1123 | (plus:P (match_dup 1) (match_dup 2)))] | |
1124 | "reload_completed" | |
cb8cc086 | 1125 | [(set (match_dup 0) |
0354e5d8 GK |
1126 | (plus:P (match_dup 1) |
1127 | (match_dup 2))) | |
cb8cc086 MM |
1128 | (set (match_dup 3) |
1129 | (compare:CC (match_dup 0) | |
1130 | (const_int 0)))] | |
1131 | "") | |
7e69e155 | 1132 | |
f357808b RK |
1133 | ;; Split an add that we can't do in one insn into two insns, each of which |
1134 | ;; does one 16-bit part. This is used by combine. Note that the low-order | |
1135 | ;; add should be last in case the result gets used in an address. | |
1136 | ||
1137 | (define_split | |
0354e5d8 GK |
1138 | [(set (match_operand:GPR 0 "gpc_reg_operand" "") |
1139 | (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "") | |
1140 | (match_operand:GPR 2 "non_add_cint_operand" "")))] | |
1fd4e8c1 | 1141 | "" |
0354e5d8 GK |
1142 | [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3))) |
1143 | (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))] | |
f357808b | 1144 | " |
1fd4e8c1 | 1145 | { |
2bfcf297 | 1146 | HOST_WIDE_INT val = INTVAL (operands[2]); |
a65c591c | 1147 | HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; |
0354e5d8 | 1148 | HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode); |
1fd4e8c1 | 1149 | |
e6ca2c17 | 1150 | operands[4] = GEN_INT (low); |
0354e5d8 GK |
1151 | if (<MODE>mode == SImode || CONST_OK_FOR_LETTER_P (rest, 'L')) |
1152 | operands[3] = GEN_INT (rest); | |
1153 | else if (! no_new_pseudos) | |
1154 | { | |
1155 | operands[3] = gen_reg_rtx (DImode); | |
1156 | emit_move_insn (operands[3], operands[2]); | |
1157 | emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); | |
1158 | DONE; | |
1159 | } | |
1160 | else | |
1161 | FAIL; | |
1fd4e8c1 RK |
1162 | }") |
1163 | ||
0354e5d8 GK |
1164 | (define_insn "one_cmpl<mode>2" |
1165 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1166 | (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 | 1167 | "" |
ca7f5001 RK |
1168 | "nor %0,%1,%1") |
1169 | ||
1170 | (define_insn "" | |
52d3af72 | 1171 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
0354e5d8 | 1172 | (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r")) |
ca7f5001 | 1173 | (const_int 0))) |
0354e5d8 GK |
1174 | (clobber (match_scratch:P 2 "=r,r"))] |
1175 | "" | |
52d3af72 DE |
1176 | "@ |
1177 | nor. %2,%1,%1 | |
1178 | #" | |
1179 | [(set_attr "type" "compare") | |
1180 | (set_attr "length" "4,8")]) | |
1181 | ||
1182 | (define_split | |
1183 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
0354e5d8 | 1184 | (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "")) |
52d3af72 | 1185 | (const_int 0))) |
0354e5d8 GK |
1186 | (clobber (match_scratch:P 2 ""))] |
1187 | "reload_completed" | |
52d3af72 | 1188 | [(set (match_dup 2) |
0354e5d8 | 1189 | (not:P (match_dup 1))) |
52d3af72 DE |
1190 | (set (match_dup 0) |
1191 | (compare:CC (match_dup 2) | |
1192 | (const_int 0)))] | |
1193 | "") | |
ca7f5001 RK |
1194 | |
1195 | (define_insn "" | |
52d3af72 | 1196 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
0354e5d8 | 1197 | (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r")) |
815cdc52 | 1198 | (const_int 0))) |
0354e5d8 GK |
1199 | (set (match_operand:P 0 "gpc_reg_operand" "=r,r") |
1200 | (not:P (match_dup 1)))] | |
1201 | "" | |
52d3af72 DE |
1202 | "@ |
1203 | nor. %0,%1,%1 | |
1204 | #" | |
1205 | [(set_attr "type" "compare") | |
1206 | (set_attr "length" "4,8")]) | |
1207 | ||
1208 | (define_split | |
1209 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
0354e5d8 | 1210 | (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "")) |
52d3af72 | 1211 | (const_int 0))) |
0354e5d8 GK |
1212 | (set (match_operand:P 0 "gpc_reg_operand" "") |
1213 | (not:P (match_dup 1)))] | |
1214 | "reload_completed" | |
52d3af72 | 1215 | [(set (match_dup 0) |
0354e5d8 | 1216 | (not:P (match_dup 1))) |
52d3af72 DE |
1217 | (set (match_dup 2) |
1218 | (compare:CC (match_dup 0) | |
1219 | (const_int 0)))] | |
1220 | "") | |
1fd4e8c1 RK |
1221 | |
1222 | (define_insn "" | |
3d91674b RK |
1223 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1224 | (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI") | |
1225 | (match_operand:SI 2 "gpc_reg_operand" "r")))] | |
deb9225a | 1226 | "! TARGET_POWERPC" |
ca7f5001 | 1227 | "{sf%I1|subf%I1c} %0,%2,%1") |
1fd4e8c1 | 1228 | |
deb9225a | 1229 | (define_insn "" |
0354e5d8 GK |
1230 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") |
1231 | (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I") | |
1232 | (match_operand:GPR 2 "gpc_reg_operand" "r,r")))] | |
deb9225a RK |
1233 | "TARGET_POWERPC" |
1234 | "@ | |
1235 | subf %0,%2,%1 | |
1236 | subfic %0,%2,%1") | |
1237 | ||
1fd4e8c1 | 1238 | (define_insn "" |
cb8cc086 MM |
1239 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1240 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1241 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1242 | (const_int 0))) |
cb8cc086 | 1243 | (clobber (match_scratch:SI 3 "=r,r"))] |
deb9225a | 1244 | "! TARGET_POWERPC" |
cb8cc086 MM |
1245 | "@ |
1246 | {sf.|subfc.} %3,%2,%1 | |
1247 | #" | |
1248 | [(set_attr "type" "compare") | |
1249 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 1250 | |
deb9225a | 1251 | (define_insn "" |
cb8cc086 | 1252 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
0354e5d8 GK |
1253 | (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r") |
1254 | (match_operand:P 2 "gpc_reg_operand" "r,r")) | |
deb9225a | 1255 | (const_int 0))) |
0354e5d8 GK |
1256 | (clobber (match_scratch:P 3 "=r,r"))] |
1257 | "TARGET_POWERPC" | |
cb8cc086 MM |
1258 | "@ |
1259 | subf. %3,%2,%1 | |
1260 | #" | |
a62bfff2 | 1261 | [(set_attr "type" "fast_compare") |
cb8cc086 MM |
1262 | (set_attr "length" "4,8")]) |
1263 | ||
1264 | (define_split | |
1265 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
0354e5d8 GK |
1266 | (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "") |
1267 | (match_operand:P 2 "gpc_reg_operand" "")) | |
cb8cc086 | 1268 | (const_int 0))) |
0354e5d8 GK |
1269 | (clobber (match_scratch:P 3 ""))] |
1270 | "reload_completed" | |
cb8cc086 | 1271 | [(set (match_dup 3) |
0354e5d8 | 1272 | (minus:P (match_dup 1) |
cb8cc086 MM |
1273 | (match_dup 2))) |
1274 | (set (match_dup 0) | |
1275 | (compare:CC (match_dup 3) | |
1276 | (const_int 0)))] | |
1277 | "") | |
deb9225a | 1278 | |
1fd4e8c1 | 1279 | (define_insn "" |
cb8cc086 MM |
1280 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1281 | (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1282 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1283 | (const_int 0))) |
cb8cc086 | 1284 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 1285 | (minus:SI (match_dup 1) (match_dup 2)))] |
deb9225a | 1286 | "! TARGET_POWERPC" |
cb8cc086 MM |
1287 | "@ |
1288 | {sf.|subfc.} %0,%2,%1 | |
1289 | #" | |
1290 | [(set_attr "type" "compare") | |
1291 | (set_attr "length" "4,8")]) | |
815cdc52 | 1292 | |
29ae5b89 | 1293 | (define_insn "" |
cb8cc086 | 1294 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
0354e5d8 GK |
1295 | (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r") |
1296 | (match_operand:P 2 "gpc_reg_operand" "r,r")) | |
815cdc52 | 1297 | (const_int 0))) |
0354e5d8 GK |
1298 | (set (match_operand:P 0 "gpc_reg_operand" "=r,r") |
1299 | (minus:P (match_dup 1) | |
cb8cc086 | 1300 | (match_dup 2)))] |
0354e5d8 | 1301 | "TARGET_POWERPC" |
90612787 DE |
1302 | "@ |
1303 | subf. %0,%2,%1 | |
1304 | #" | |
a62bfff2 | 1305 | [(set_attr "type" "fast_compare") |
cb8cc086 MM |
1306 | (set_attr "length" "4,8")]) |
1307 | ||
1308 | (define_split | |
1309 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
0354e5d8 GK |
1310 | (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "") |
1311 | (match_operand:P 2 "gpc_reg_operand" "")) | |
cb8cc086 | 1312 | (const_int 0))) |
0354e5d8 GK |
1313 | (set (match_operand:P 0 "gpc_reg_operand" "") |
1314 | (minus:P (match_dup 1) | |
cb8cc086 | 1315 | (match_dup 2)))] |
0354e5d8 | 1316 | "reload_completed" |
cb8cc086 | 1317 | [(set (match_dup 0) |
0354e5d8 | 1318 | (minus:P (match_dup 1) |
cb8cc086 MM |
1319 | (match_dup 2))) |
1320 | (set (match_dup 3) | |
1321 | (compare:CC (match_dup 0) | |
1322 | (const_int 0)))] | |
1323 | "") | |
deb9225a | 1324 | |
0354e5d8 GK |
1325 | (define_expand "sub<mode>3" |
1326 | [(set (match_operand:SDI 0 "gpc_reg_operand" "") | |
1327 | (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "") | |
4ae234b0 | 1328 | (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))] |
1fd4e8c1 | 1329 | "" |
a0044fb1 RK |
1330 | " |
1331 | { | |
1332 | if (GET_CODE (operands[2]) == CONST_INT) | |
1333 | { | |
0354e5d8 GK |
1334 | emit_insn (gen_add<mode>3 (operands[0], operands[1], |
1335 | negate_rtx (<MODE>mode, operands[2]))); | |
a0044fb1 RK |
1336 | DONE; |
1337 | } | |
1338 | }") | |
1fd4e8c1 RK |
1339 | |
1340 | ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] | |
1341 | ;; instruction and some auxiliary computations. Then we just have a single | |
95ac8e67 RK |
1342 | ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by |
1343 | ;; combine. | |
1fd4e8c1 RK |
1344 | |
1345 | (define_expand "sminsi3" | |
1346 | [(set (match_dup 3) | |
cd2b37d9 | 1347 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1348 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1349 | (const_int 0) | |
1350 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1351 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1352 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 1353 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1354 | " |
a3170dc6 AH |
1355 | { |
1356 | if (TARGET_ISEL) | |
1357 | { | |
1358 | operands[2] = force_reg (SImode, operands[2]); | |
1359 | rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); | |
1360 | DONE; | |
1361 | } | |
1362 | ||
1363 | operands[3] = gen_reg_rtx (SImode); | |
1364 | }") | |
1fd4e8c1 | 1365 | |
95ac8e67 RK |
1366 | (define_split |
1367 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1368 | (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1369 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1370 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1371 | "TARGET_POWER" |
95ac8e67 RK |
1372 | [(set (match_dup 3) |
1373 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1374 | (const_int 0) | |
1375 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1376 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] | |
1377 | "") | |
1378 | ||
1fd4e8c1 RK |
1379 | (define_expand "smaxsi3" |
1380 | [(set (match_dup 3) | |
cd2b37d9 | 1381 | (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 RK |
1382 | (match_operand:SI 2 "reg_or_short_operand" "")) |
1383 | (const_int 0) | |
1384 | (minus:SI (match_dup 2) (match_dup 1)))) | |
cd2b37d9 | 1385 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1386 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 1387 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1388 | " |
a3170dc6 AH |
1389 | { |
1390 | if (TARGET_ISEL) | |
1391 | { | |
1392 | operands[2] = force_reg (SImode, operands[2]); | |
1393 | rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); | |
1394 | DONE; | |
1395 | } | |
1396 | operands[3] = gen_reg_rtx (SImode); | |
1397 | }") | |
1fd4e8c1 | 1398 | |
95ac8e67 RK |
1399 | (define_split |
1400 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1401 | (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1402 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
1403 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] | |
ca7f5001 | 1404 | "TARGET_POWER" |
95ac8e67 RK |
1405 | [(set (match_dup 3) |
1406 | (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) | |
1407 | (const_int 0) | |
1408 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1409 | (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] | |
1410 | "") | |
1411 | ||
1fd4e8c1 | 1412 | (define_expand "uminsi3" |
cd2b37d9 | 1413 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1414 | (match_dup 5))) |
cd2b37d9 | 1415 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1416 | (match_dup 5))) |
1fd4e8c1 RK |
1417 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1418 | (const_int 0) | |
1419 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1420 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1421 | (minus:SI (match_dup 2) (match_dup 3)))] |
a3170dc6 | 1422 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1423 | " |
bb68ff55 | 1424 | { |
a3170dc6 AH |
1425 | if (TARGET_ISEL) |
1426 | { | |
1427 | rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]); | |
1428 | DONE; | |
1429 | } | |
bb68ff55 MM |
1430 | operands[3] = gen_reg_rtx (SImode); |
1431 | operands[4] = gen_reg_rtx (SImode); | |
1432 | operands[5] = GEN_INT (-2147483647 - 1); | |
1433 | }") | |
1fd4e8c1 RK |
1434 | |
1435 | (define_expand "umaxsi3" | |
cd2b37d9 | 1436 | [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
bb68ff55 | 1437 | (match_dup 5))) |
cd2b37d9 | 1438 | (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") |
bb68ff55 | 1439 | (match_dup 5))) |
1fd4e8c1 RK |
1440 | (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) |
1441 | (const_int 0) | |
1442 | (minus:SI (match_dup 4) (match_dup 3)))) | |
cd2b37d9 | 1443 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 | 1444 | (plus:SI (match_dup 3) (match_dup 1)))] |
a3170dc6 | 1445 | "TARGET_POWER || TARGET_ISEL" |
1fd4e8c1 | 1446 | " |
bb68ff55 | 1447 | { |
a3170dc6 AH |
1448 | if (TARGET_ISEL) |
1449 | { | |
1450 | rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]); | |
1451 | DONE; | |
1452 | } | |
bb68ff55 MM |
1453 | operands[3] = gen_reg_rtx (SImode); |
1454 | operands[4] = gen_reg_rtx (SImode); | |
1455 | operands[5] = GEN_INT (-2147483647 - 1); | |
1456 | }") | |
1fd4e8c1 RK |
1457 | |
1458 | (define_insn "" | |
cd2b37d9 RK |
1459 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1460 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") | |
5c23c401 | 1461 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
1fd4e8c1 RK |
1462 | (const_int 0) |
1463 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1464 | "TARGET_POWER" |
1fd4e8c1 RK |
1465 | "doz%I2 %0,%1,%2") |
1466 | ||
1467 | (define_insn "" | |
9ebbca7d | 1468 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1469 | (compare:CC |
9ebbca7d GK |
1470 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1471 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1472 | (const_int 0) |
1473 | (minus:SI (match_dup 2) (match_dup 1))) | |
1474 | (const_int 0))) | |
9ebbca7d | 1475 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 1476 | "TARGET_POWER" |
9ebbca7d GK |
1477 | "@ |
1478 | doz%I2. %3,%1,%2 | |
1479 | #" | |
1480 | [(set_attr "type" "delayed_compare") | |
1481 | (set_attr "length" "4,8")]) | |
1482 | ||
1483 | (define_split | |
1484 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1485 | (compare:CC | |
1486 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1487 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1488 | (const_int 0) | |
1489 | (minus:SI (match_dup 2) (match_dup 1))) | |
1490 | (const_int 0))) | |
1491 | (clobber (match_scratch:SI 3 ""))] | |
1492 | "TARGET_POWER && reload_completed" | |
1493 | [(set (match_dup 3) | |
1494 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1495 | (const_int 0) | |
1496 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1497 | (set (match_dup 0) | |
1498 | (compare:CC (match_dup 3) | |
1499 | (const_int 0)))] | |
1500 | "") | |
1fd4e8c1 RK |
1501 | |
1502 | (define_insn "" | |
9ebbca7d | 1503 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 1504 | (compare:CC |
9ebbca7d GK |
1505 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1506 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 RK |
1507 | (const_int 0) |
1508 | (minus:SI (match_dup 2) (match_dup 1))) | |
1509 | (const_int 0))) | |
9ebbca7d | 1510 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
1511 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) |
1512 | (const_int 0) | |
1513 | (minus:SI (match_dup 2) (match_dup 1))))] | |
ca7f5001 | 1514 | "TARGET_POWER" |
9ebbca7d GK |
1515 | "@ |
1516 | doz%I2. %0,%1,%2 | |
1517 | #" | |
1518 | [(set_attr "type" "delayed_compare") | |
1519 | (set_attr "length" "4,8")]) | |
1520 | ||
1521 | (define_split | |
1522 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1523 | (compare:CC | |
1524 | (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "") | |
1525 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
1526 | (const_int 0) | |
1527 | (minus:SI (match_dup 2) (match_dup 1))) | |
1528 | (const_int 0))) | |
1529 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1530 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1531 | (const_int 0) | |
1532 | (minus:SI (match_dup 2) (match_dup 1))))] | |
1533 | "TARGET_POWER && reload_completed" | |
1534 | [(set (match_dup 0) | |
1535 | (if_then_else:SI (gt (match_dup 1) (match_dup 2)) | |
1536 | (const_int 0) | |
1537 | (minus:SI (match_dup 2) (match_dup 1)))) | |
1538 | (set (match_dup 3) | |
1539 | (compare:CC (match_dup 0) | |
1540 | (const_int 0)))] | |
1541 | "") | |
1fd4e8c1 RK |
1542 | |
1543 | ;; We don't need abs with condition code because such comparisons should | |
1544 | ;; never be done. | |
ea9be077 MM |
1545 | (define_expand "abssi2" |
1546 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1547 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))] | |
1548 | "" | |
1549 | " | |
1550 | { | |
a3170dc6 AH |
1551 | if (TARGET_ISEL) |
1552 | { | |
1553 | emit_insn (gen_abssi2_isel (operands[0], operands[1])); | |
1554 | DONE; | |
1555 | } | |
1556 | else if (! TARGET_POWER) | |
ea9be077 MM |
1557 | { |
1558 | emit_insn (gen_abssi2_nopower (operands[0], operands[1])); | |
1559 | DONE; | |
1560 | } | |
1561 | }") | |
1562 | ||
ea112fc4 | 1563 | (define_insn "*abssi2_power" |
cd2b37d9 RK |
1564 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1565 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
ca7f5001 | 1566 | "TARGET_POWER" |
1fd4e8c1 RK |
1567 | "abs %0,%1") |
1568 | ||
a3170dc6 AH |
1569 | (define_insn_and_split "abssi2_isel" |
1570 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1571 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8c48b6f5 | 1572 | (clobber (match_scratch:SI 2 "=&b")) |
a3170dc6 AH |
1573 | (clobber (match_scratch:CC 3 "=y"))] |
1574 | "TARGET_ISEL" | |
1575 | "#" | |
1576 | "&& reload_completed" | |
1577 | [(set (match_dup 2) (neg:SI (match_dup 1))) | |
1578 | (set (match_dup 3) | |
1579 | (compare:CC (match_dup 1) | |
1580 | (const_int 0))) | |
1581 | (set (match_dup 0) | |
1582 | (if_then_else:SI (ge (match_dup 3) | |
1583 | (const_int 0)) | |
1584 | (match_dup 1) | |
1585 | (match_dup 2)))] | |
1586 | "") | |
1587 | ||
ea112fc4 | 1588 | (define_insn_and_split "abssi2_nopower" |
ea9be077 | 1589 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 1590 | (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) |
ea9be077 | 1591 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
a3170dc6 | 1592 | "! TARGET_POWER && ! TARGET_ISEL" |
ea112fc4 DE |
1593 | "#" |
1594 | "&& reload_completed" | |
ea9be077 MM |
1595 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1596 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1597 | (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] |
ea9be077 MM |
1598 | "") |
1599 | ||
463b558b | 1600 | (define_insn "*nabs_power" |
cd2b37d9 RK |
1601 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1602 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] | |
ca7f5001 | 1603 | "TARGET_POWER" |
1fd4e8c1 RK |
1604 | "nabs %0,%1") |
1605 | ||
ea112fc4 | 1606 | (define_insn_and_split "*nabs_nopower" |
ea9be077 | 1607 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 1608 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) |
ea9be077 | 1609 | (clobber (match_scratch:SI 2 "=&r,&r"))] |
0ad91047 | 1610 | "! TARGET_POWER" |
ea112fc4 DE |
1611 | "#" |
1612 | "&& reload_completed" | |
ea9be077 MM |
1613 | [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) |
1614 | (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) | |
7093ddee | 1615 | (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] |
ea9be077 MM |
1616 | "") |
1617 | ||
0354e5d8 GK |
1618 | (define_expand "neg<mode>2" |
1619 | [(set (match_operand:SDI 0 "gpc_reg_operand" "") | |
1620 | (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))] | |
1621 | "" | |
1622 | "") | |
1623 | ||
1624 | (define_insn "*neg<mode>2_internal" | |
1625 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1626 | (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] | |
1fd4e8c1 RK |
1627 | "" |
1628 | "neg %0,%1") | |
1629 | ||
1630 | (define_insn "" | |
9ebbca7d | 1631 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
0354e5d8 | 1632 | (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 1633 | (const_int 0))) |
0354e5d8 GK |
1634 | (clobber (match_scratch:P 2 "=r,r"))] |
1635 | "" | |
9ebbca7d GK |
1636 | "@ |
1637 | neg. %2,%1 | |
1638 | #" | |
a62bfff2 | 1639 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
1640 | (set_attr "length" "4,8")]) |
1641 | ||
1642 | (define_split | |
1643 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
0354e5d8 | 1644 | (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "")) |
9ebbca7d | 1645 | (const_int 0))) |
0354e5d8 GK |
1646 | (clobber (match_scratch:P 2 ""))] |
1647 | "reload_completed" | |
9ebbca7d | 1648 | [(set (match_dup 2) |
0354e5d8 | 1649 | (neg:P (match_dup 1))) |
9ebbca7d GK |
1650 | (set (match_dup 0) |
1651 | (compare:CC (match_dup 2) | |
1652 | (const_int 0)))] | |
1653 | "") | |
1fd4e8c1 RK |
1654 | |
1655 | (define_insn "" | |
9ebbca7d | 1656 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
0354e5d8 | 1657 | (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r")) |
815cdc52 | 1658 | (const_int 0))) |
0354e5d8 GK |
1659 | (set (match_operand:P 0 "gpc_reg_operand" "=r,r") |
1660 | (neg:P (match_dup 1)))] | |
1661 | "" | |
9ebbca7d GK |
1662 | "@ |
1663 | neg. %0,%1 | |
1664 | #" | |
a62bfff2 | 1665 | [(set_attr "type" "fast_compare") |
9ebbca7d GK |
1666 | (set_attr "length" "4,8")]) |
1667 | ||
1668 | (define_split | |
1669 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
0354e5d8 | 1670 | (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "")) |
9ebbca7d | 1671 | (const_int 0))) |
0354e5d8 GK |
1672 | (set (match_operand:P 0 "gpc_reg_operand" "") |
1673 | (neg:P (match_dup 1)))] | |
66859ace | 1674 | "reload_completed" |
9ebbca7d | 1675 | [(set (match_dup 0) |
0354e5d8 | 1676 | (neg:P (match_dup 1))) |
9ebbca7d GK |
1677 | (set (match_dup 2) |
1678 | (compare:CC (match_dup 0) | |
1679 | (const_int 0)))] | |
1680 | "") | |
1fd4e8c1 | 1681 | |
0354e5d8 GK |
1682 | (define_insn "clz<mode>2" |
1683 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1684 | (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] | |
1b1edcfa | 1685 | "" |
0354e5d8 | 1686 | "{cntlz|cntlz<wd>} %0,%1") |
1b1edcfa | 1687 | |
0354e5d8 | 1688 | (define_expand "ctz<mode>2" |
4977bab6 | 1689 | [(set (match_dup 2) |
0354e5d8 GK |
1690 | (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))) |
1691 | (parallel [(set (match_dup 3) (and:GPR (match_dup 1) | |
1692 | (match_dup 2))) | |
1b1edcfa | 1693 | (clobber (scratch:CC))]) |
0354e5d8 GK |
1694 | (set (match_dup 4) (clz:GPR (match_dup 3))) |
1695 | (set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1696 | (minus:GPR (match_dup 5) (match_dup 4)))] | |
1fd4e8c1 | 1697 | "" |
4977bab6 | 1698 | { |
0354e5d8 GK |
1699 | operands[2] = gen_reg_rtx (<MODE>mode); |
1700 | operands[3] = gen_reg_rtx (<MODE>mode); | |
1701 | operands[4] = gen_reg_rtx (<MODE>mode); | |
1702 | operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1); | |
4977bab6 | 1703 | }) |
6ae08853 | 1704 | |
0354e5d8 | 1705 | (define_expand "ffs<mode>2" |
1b1edcfa | 1706 | [(set (match_dup 2) |
0354e5d8 GK |
1707 | (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r"))) |
1708 | (parallel [(set (match_dup 3) (and:GPR (match_dup 1) | |
1709 | (match_dup 2))) | |
1b1edcfa | 1710 | (clobber (scratch:CC))]) |
0354e5d8 GK |
1711 | (set (match_dup 4) (clz:GPR (match_dup 3))) |
1712 | (set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1713 | (minus:GPR (match_dup 5) (match_dup 4)))] | |
4977bab6 | 1714 | "" |
1b1edcfa | 1715 | { |
0354e5d8 GK |
1716 | operands[2] = gen_reg_rtx (<MODE>mode); |
1717 | operands[3] = gen_reg_rtx (<MODE>mode); | |
1718 | operands[4] = gen_reg_rtx (<MODE>mode); | |
1719 | operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)); | |
1b1edcfa | 1720 | }) |
6ae08853 | 1721 | |
432218ba DE |
1722 | (define_expand "popcount<mode>2" |
1723 | [(set (match_dup 2) | |
1724 | (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] | |
1725 | UNSPEC_POPCNTB)) | |
1726 | (set (match_dup 3) | |
1727 | (mult:GPR (match_dup 2) (match_dup 4))) | |
1728 | (set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1729 | (lshiftrt:GPR (match_dup 3) (match_dup 5)))] | |
1730 | "TARGET_POPCNTB" | |
1731 | { | |
1732 | operands[2] = gen_reg_rtx (<MODE>mode); | |
1733 | operands[3] = gen_reg_rtx (<MODE>mode); | |
1e0aa44a DE |
1734 | operands[4] = force_reg (<MODE>mode, |
1735 | <MODE>mode == SImode | |
1736 | ? GEN_INT (0x01010101) | |
1737 | : GEN_INT ((HOST_WIDE_INT) | |
1738 | 0x01010101 << 32 | 0x01010101)); | |
432218ba DE |
1739 | operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 8); |
1740 | }) | |
1741 | ||
1742 | (define_insn "popcntb<mode>2" | |
1743 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
1744 | (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] | |
1745 | UNSPEC_POPCNTB))] | |
1746 | "TARGET_POPCNTB" | |
1747 | "popcntb %0,%1") | |
1748 | ||
ca7f5001 RK |
1749 | (define_expand "mulsi3" |
1750 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
1751 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
1752 | (use (match_operand:SI 2 "reg_or_short_operand" ""))] | |
1753 | "" | |
1754 | " | |
1755 | { | |
1756 | if (TARGET_POWER) | |
68b40e7e | 1757 | emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2])); |
ca7f5001 | 1758 | else |
68b40e7e | 1759 | emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
1760 | DONE; |
1761 | }") | |
1762 | ||
68b40e7e | 1763 | (define_insn "mulsi3_mq" |
cd2b37d9 RK |
1764 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1765 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1fd4e8c1 RK |
1766 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
1767 | (clobber (match_scratch:SI 3 "=q,q"))] | |
ca7f5001 RK |
1768 | "TARGET_POWER" |
1769 | "@ | |
1770 | {muls|mullw} %0,%1,%2 | |
1771 | {muli|mulli} %0,%1,%2" | |
6ae08853 | 1772 | [(set (attr "type") |
c859cda6 DJ |
1773 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") |
1774 | (const_string "imul3") | |
6ae08853 | 1775 | (match_operand:SI 2 "short_cint_operand" "") |
c859cda6 DJ |
1776 | (const_string "imul2")] |
1777 | (const_string "imul")))]) | |
ca7f5001 | 1778 | |
68b40e7e | 1779 | (define_insn "mulsi3_no_mq" |
ca7f5001 RK |
1780 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1781 | (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1782 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))] | |
68b40e7e | 1783 | "! TARGET_POWER" |
1fd4e8c1 | 1784 | "@ |
d904e9ed RK |
1785 | {muls|mullw} %0,%1,%2 |
1786 | {muli|mulli} %0,%1,%2" | |
6ae08853 | 1787 | [(set (attr "type") |
c859cda6 DJ |
1788 | (cond [(match_operand:SI 2 "s8bit_cint_operand" "") |
1789 | (const_string "imul3") | |
6ae08853 | 1790 | (match_operand:SI 2 "short_cint_operand" "") |
c859cda6 DJ |
1791 | (const_string "imul2")] |
1792 | (const_string "imul")))]) | |
1fd4e8c1 | 1793 | |
9259f3b0 | 1794 | (define_insn "*mulsi3_mq_internal1" |
9ebbca7d GK |
1795 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1796 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1797 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1798 | (const_int 0))) |
9ebbca7d GK |
1799 | (clobber (match_scratch:SI 3 "=r,r")) |
1800 | (clobber (match_scratch:SI 4 "=q,q"))] | |
ca7f5001 | 1801 | "TARGET_POWER" |
9ebbca7d GK |
1802 | "@ |
1803 | {muls.|mullw.} %3,%1,%2 | |
1804 | #" | |
9259f3b0 | 1805 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1806 | (set_attr "length" "4,8")]) |
1807 | ||
1808 | (define_split | |
1809 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1810 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1811 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1812 | (const_int 0))) | |
1813 | (clobber (match_scratch:SI 3 "")) | |
1814 | (clobber (match_scratch:SI 4 ""))] | |
1815 | "TARGET_POWER && reload_completed" | |
1816 | [(parallel [(set (match_dup 3) | |
1817 | (mult:SI (match_dup 1) (match_dup 2))) | |
1818 | (clobber (match_dup 4))]) | |
1819 | (set (match_dup 0) | |
1820 | (compare:CC (match_dup 3) | |
1821 | (const_int 0)))] | |
1822 | "") | |
ca7f5001 | 1823 | |
9259f3b0 | 1824 | (define_insn "*mulsi3_no_mq_internal1" |
9ebbca7d GK |
1825 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1826 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1827 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1828 | (const_int 0))) |
9ebbca7d | 1829 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 1830 | "! TARGET_POWER" |
9ebbca7d GK |
1831 | "@ |
1832 | {muls.|mullw.} %3,%1,%2 | |
1833 | #" | |
9259f3b0 | 1834 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1835 | (set_attr "length" "4,8")]) |
1836 | ||
1837 | (define_split | |
1838 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
1839 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1840 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1841 | (const_int 0))) | |
1842 | (clobber (match_scratch:SI 3 ""))] | |
1843 | "! TARGET_POWER && reload_completed" | |
1844 | [(set (match_dup 3) | |
1845 | (mult:SI (match_dup 1) (match_dup 2))) | |
1846 | (set (match_dup 0) | |
1847 | (compare:CC (match_dup 3) | |
1848 | (const_int 0)))] | |
1849 | "") | |
1fd4e8c1 | 1850 | |
9259f3b0 | 1851 | (define_insn "*mulsi3_mq_internal2" |
9ebbca7d GK |
1852 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1853 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1854 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 1855 | (const_int 0))) |
9ebbca7d | 1856 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 1857 | (mult:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 1858 | (clobber (match_scratch:SI 4 "=q,q"))] |
ca7f5001 | 1859 | "TARGET_POWER" |
9ebbca7d GK |
1860 | "@ |
1861 | {muls.|mullw.} %0,%1,%2 | |
1862 | #" | |
9259f3b0 | 1863 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1864 | (set_attr "length" "4,8")]) |
1865 | ||
1866 | (define_split | |
1867 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1868 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1869 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1870 | (const_int 0))) | |
1871 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1872 | (mult:SI (match_dup 1) (match_dup 2))) | |
1873 | (clobber (match_scratch:SI 4 ""))] | |
1874 | "TARGET_POWER && reload_completed" | |
1875 | [(parallel [(set (match_dup 0) | |
1876 | (mult:SI (match_dup 1) (match_dup 2))) | |
1877 | (clobber (match_dup 4))]) | |
1878 | (set (match_dup 3) | |
1879 | (compare:CC (match_dup 0) | |
1880 | (const_int 0)))] | |
1881 | "") | |
ca7f5001 | 1882 | |
9259f3b0 | 1883 | (define_insn "*mulsi3_no_mq_internal2" |
9ebbca7d GK |
1884 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1885 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
1886 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
ca7f5001 | 1887 | (const_int 0))) |
9ebbca7d | 1888 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 1889 | (mult:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 1890 | "! TARGET_POWER" |
9ebbca7d GK |
1891 | "@ |
1892 | {muls.|mullw.} %0,%1,%2 | |
1893 | #" | |
9259f3b0 | 1894 | [(set_attr "type" "imul_compare") |
9ebbca7d GK |
1895 | (set_attr "length" "4,8")]) |
1896 | ||
1897 | (define_split | |
1898 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
1899 | (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1900 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
1901 | (const_int 0))) | |
1902 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
1903 | (mult:SI (match_dup 1) (match_dup 2)))] | |
1904 | "! TARGET_POWER && reload_completed" | |
1905 | [(set (match_dup 0) | |
1906 | (mult:SI (match_dup 1) (match_dup 2))) | |
1907 | (set (match_dup 3) | |
1908 | (compare:CC (match_dup 0) | |
1909 | (const_int 0)))] | |
1910 | "") | |
1fd4e8c1 RK |
1911 | |
1912 | ;; Operand 1 is divided by operand 2; quotient goes to operand | |
1913 | ;; 0 and remainder to operand 3. | |
1914 | ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). | |
1915 | ||
8ffd9c51 RK |
1916 | (define_expand "divmodsi4" |
1917 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1918 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1919 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
bb157ff4 | 1920 | (set (match_operand:SI 3 "register_operand" "") |
8ffd9c51 RK |
1921 | (mod:SI (match_dup 1) (match_dup 2)))])] |
1922 | "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)" | |
1923 | " | |
1924 | { | |
1925 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1926 | { | |
39403d82 DE |
1927 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1928 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1929 | emit_insn (gen_divss_call ()); |
39403d82 DE |
1930 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
1931 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
8ffd9c51 RK |
1932 | DONE; |
1933 | } | |
1934 | }") | |
deb9225a | 1935 | |
bb157ff4 | 1936 | (define_insn "*divmodsi4_internal" |
cd2b37d9 RK |
1937 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1938 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1939 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
bb157ff4 | 1940 | (set (match_operand:SI 3 "register_operand" "=q") |
1fd4e8c1 | 1941 | (mod:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 1942 | "TARGET_POWER" |
cfb557c4 RK |
1943 | "divs %0,%1,%2" |
1944 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 | 1945 | |
4ae234b0 GK |
1946 | (define_expand "udiv<mode>3" |
1947 | [(set (match_operand:GPR 0 "gpc_reg_operand" "") | |
1948 | (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "") | |
1949 | (match_operand:GPR 2 "gpc_reg_operand" "")))] | |
8ffd9c51 RK |
1950 | "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)" |
1951 | " | |
1952 | { | |
1953 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
1954 | { | |
39403d82 DE |
1955 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
1956 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 1957 | emit_insn (gen_quous_call ()); |
39403d82 | 1958 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
1959 | DONE; |
1960 | } | |
f192bf8b DE |
1961 | else if (TARGET_POWER) |
1962 | { | |
1963 | emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2])); | |
1964 | DONE; | |
1965 | } | |
8ffd9c51 | 1966 | }") |
deb9225a | 1967 | |
f192bf8b DE |
1968 | (define_insn "udivsi3_mq" |
1969 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
1970 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1971 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
1972 | (clobber (match_scratch:SI 3 "=q"))] | |
1973 | "TARGET_POWERPC && TARGET_POWER" | |
1974 | "divwu %0,%1,%2" | |
1975 | [(set_attr "type" "idiv")]) | |
1976 | ||
1977 | (define_insn "*udivsi3_no_mq" | |
4ae234b0 GK |
1978 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") |
1979 | (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") | |
1980 | (match_operand:GPR 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 1981 | "TARGET_POWERPC && ! TARGET_POWER" |
4ae234b0 | 1982 | "div<wd>u %0,%1,%2" |
ca7f5001 RK |
1983 | [(set_attr "type" "idiv")]) |
1984 | ||
1fd4e8c1 | 1985 | ;; For powers of two we can do srai/aze for divide and then adjust for |
ca7f5001 | 1986 | ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be |
8ffd9c51 RK |
1987 | ;; used; for PowerPC, force operands into register and do a normal divide; |
1988 | ;; for AIX common-mode, use quoss call on register operands. | |
4ae234b0 GK |
1989 | (define_expand "div<mode>3" |
1990 | [(set (match_operand:GPR 0 "gpc_reg_operand" "") | |
1991 | (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") | |
1992 | (match_operand:GPR 2 "reg_or_cint_operand" "")))] | |
1fd4e8c1 RK |
1993 | "" |
1994 | " | |
1995 | { | |
ca7f5001 | 1996 | if (GET_CODE (operands[2]) == CONST_INT |
2bfcf297 | 1997 | && INTVAL (operands[2]) > 0 |
ca7f5001 RK |
1998 | && exact_log2 (INTVAL (operands[2])) >= 0) |
1999 | ; | |
b6c9286a | 2000 | else if (TARGET_POWERPC) |
f192bf8b DE |
2001 | { |
2002 | operands[2] = force_reg (SImode, operands[2]); | |
2003 | if (TARGET_POWER) | |
2004 | { | |
2005 | emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2])); | |
2006 | DONE; | |
2007 | } | |
2008 | } | |
b6c9286a | 2009 | else if (TARGET_POWER) |
1fd4e8c1 | 2010 | FAIL; |
405c5495 | 2011 | else |
8ffd9c51 | 2012 | { |
39403d82 DE |
2013 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2014 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 2015 | emit_insn (gen_quoss_call ()); |
39403d82 | 2016 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
2017 | DONE; |
2018 | } | |
1fd4e8c1 RK |
2019 | }") |
2020 | ||
f192bf8b DE |
2021 | (define_insn "divsi3_mq" |
2022 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2023 | (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2024 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
2025 | (clobber (match_scratch:SI 3 "=q"))] | |
2026 | "TARGET_POWERPC && TARGET_POWER" | |
2027 | "divw %0,%1,%2" | |
2028 | [(set_attr "type" "idiv")]) | |
2029 | ||
4ae234b0 GK |
2030 | (define_insn "*div<mode>3_no_mq" |
2031 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
2032 | (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") | |
2033 | (match_operand:GPR 2 "gpc_reg_operand" "r")))] | |
f192bf8b | 2034 | "TARGET_POWERPC && ! TARGET_POWER" |
4ae234b0 | 2035 | "div<wd> %0,%1,%2" |
f192bf8b DE |
2036 | [(set_attr "type" "idiv")]) |
2037 | ||
4ae234b0 GK |
2038 | (define_expand "mod<mode>3" |
2039 | [(use (match_operand:GPR 0 "gpc_reg_operand" "")) | |
2040 | (use (match_operand:GPR 1 "gpc_reg_operand" "")) | |
2041 | (use (match_operand:GPR 2 "reg_or_cint_operand" ""))] | |
39b52ba2 | 2042 | "" |
1fd4e8c1 RK |
2043 | " |
2044 | { | |
481c7efa | 2045 | int i; |
39b52ba2 RK |
2046 | rtx temp1; |
2047 | rtx temp2; | |
2048 | ||
2bfcf297 | 2049 | if (GET_CODE (operands[2]) != CONST_INT |
a65c591c | 2050 | || INTVAL (operands[2]) <= 0 |
2bfcf297 | 2051 | || (i = exact_log2 (INTVAL (operands[2]))) < 0) |
39b52ba2 RK |
2052 | FAIL; |
2053 | ||
4ae234b0 GK |
2054 | temp1 = gen_reg_rtx (<MODE>mode); |
2055 | temp2 = gen_reg_rtx (<MODE>mode); | |
1fd4e8c1 | 2056 | |
4ae234b0 GK |
2057 | emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2])); |
2058 | emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i))); | |
2059 | emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2)); | |
85644414 | 2060 | DONE; |
1fd4e8c1 RK |
2061 | }") |
2062 | ||
2063 | (define_insn "" | |
4ae234b0 GK |
2064 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") |
2065 | (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") | |
2066 | (match_operand:GPR 2 "exact_log2_cint_operand" "N")))] | |
2bfcf297 | 2067 | "" |
4ae234b0 | 2068 | "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0" |
943c15ed DE |
2069 | [(set_attr "type" "two") |
2070 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
2071 | |
2072 | (define_insn "" | |
9ebbca7d | 2073 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4ae234b0 GK |
2074 | (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r") |
2075 | (match_operand:P 2 "exact_log2_cint_operand" "N,N")) | |
b6b12107 | 2076 | (const_int 0))) |
4ae234b0 | 2077 | (clobber (match_scratch:P 3 "=r,r"))] |
2bfcf297 | 2078 | "" |
9ebbca7d | 2079 | "@ |
4ae234b0 | 2080 | {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3 |
9ebbca7d | 2081 | #" |
b19003d8 | 2082 | [(set_attr "type" "compare") |
9ebbca7d GK |
2083 | (set_attr "length" "8,12")]) |
2084 | ||
2085 | (define_split | |
2086 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4ae234b0 GK |
2087 | (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") |
2088 | (match_operand:GPR 2 "exact_log2_cint_operand" | |
2089 | "")) | |
9ebbca7d | 2090 | (const_int 0))) |
4ae234b0 | 2091 | (clobber (match_scratch:GPR 3 ""))] |
2bfcf297 | 2092 | "reload_completed" |
9ebbca7d | 2093 | [(set (match_dup 3) |
4ae234b0 | 2094 | (div:<MODE> (match_dup 1) (match_dup 2))) |
9ebbca7d GK |
2095 | (set (match_dup 0) |
2096 | (compare:CC (match_dup 3) | |
2097 | (const_int 0)))] | |
2098 | "") | |
1fd4e8c1 RK |
2099 | |
2100 | (define_insn "" | |
9ebbca7d | 2101 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4ae234b0 GK |
2102 | (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r") |
2103 | (match_operand:P 2 "exact_log2_cint_operand" "N,N")) | |
b6b12107 | 2104 | (const_int 0))) |
4ae234b0 GK |
2105 | (set (match_operand:P 0 "gpc_reg_operand" "=r,r") |
2106 | (div:P (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 2107 | "" |
9ebbca7d | 2108 | "@ |
4ae234b0 | 2109 | {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0 |
9ebbca7d | 2110 | #" |
b19003d8 | 2111 | [(set_attr "type" "compare") |
9ebbca7d GK |
2112 | (set_attr "length" "8,12")]) |
2113 | ||
2114 | (define_split | |
2115 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4ae234b0 GK |
2116 | (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") |
2117 | (match_operand:GPR 2 "exact_log2_cint_operand" | |
2118 | "")) | |
9ebbca7d | 2119 | (const_int 0))) |
4ae234b0 GK |
2120 | (set (match_operand:GPR 0 "gpc_reg_operand" "") |
2121 | (div:GPR (match_dup 1) (match_dup 2)))] | |
2bfcf297 | 2122 | "reload_completed" |
9ebbca7d | 2123 | [(set (match_dup 0) |
4ae234b0 | 2124 | (div:<MODE> (match_dup 1) (match_dup 2))) |
9ebbca7d GK |
2125 | (set (match_dup 3) |
2126 | (compare:CC (match_dup 0) | |
2127 | (const_int 0)))] | |
2128 | "") | |
1fd4e8c1 RK |
2129 | |
2130 | (define_insn "" | |
cd2b37d9 | 2131 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 2132 | (udiv:SI |
996a5f59 | 2133 | (plus:DI (ashift:DI |
cd2b37d9 | 2134 | (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) |
1fd4e8c1 | 2135 | (const_int 32)) |
23a900dc | 2136 | (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) |
cd2b37d9 | 2137 | (match_operand:SI 3 "gpc_reg_operand" "r"))) |
740ab4a2 | 2138 | (set (match_operand:SI 2 "register_operand" "=*q") |
1fd4e8c1 | 2139 | (umod:SI |
996a5f59 | 2140 | (plus:DI (ashift:DI |
1fd4e8c1 | 2141 | (zero_extend:DI (match_dup 1)) (const_int 32)) |
740ab4a2 | 2142 | (zero_extend:DI (match_dup 4))) |
1fd4e8c1 | 2143 | (match_dup 3)))] |
ca7f5001 | 2144 | "TARGET_POWER" |
cfb557c4 RK |
2145 | "div %0,%1,%3" |
2146 | [(set_attr "type" "idiv")]) | |
1fd4e8c1 RK |
2147 | |
2148 | ;; To do unsigned divide we handle the cases of the divisor looking like a | |
2149 | ;; negative number. If it is a constant that is less than 2**31, we don't | |
2150 | ;; have to worry about the branches. So make a few subroutines here. | |
2151 | ;; | |
2152 | ;; First comes the normal case. | |
2153 | (define_expand "udivmodsi4_normal" | |
2154 | [(set (match_dup 4) (const_int 0)) | |
2155 | (parallel [(set (match_operand:SI 0 "" "") | |
996a5f59 | 2156 | (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2157 | (const_int 32)) |
2158 | (zero_extend:DI (match_operand:SI 1 "" ""))) | |
2159 | (match_operand:SI 2 "" ""))) | |
2160 | (set (match_operand:SI 3 "" "") | |
996a5f59 | 2161 | (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4)) |
1fd4e8c1 RK |
2162 | (const_int 32)) |
2163 | (zero_extend:DI (match_dup 1))) | |
2164 | (match_dup 2)))])] | |
ca7f5001 | 2165 | "TARGET_POWER" |
1fd4e8c1 RK |
2166 | " |
2167 | { operands[4] = gen_reg_rtx (SImode); }") | |
2168 | ||
2169 | ;; This handles the branches. | |
2170 | (define_expand "udivmodsi4_tests" | |
2171 | [(set (match_operand:SI 0 "" "") (const_int 0)) | |
2172 | (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" "")) | |
2173 | (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" ""))) | |
2174 | (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) | |
2175 | (label_ref (match_operand:SI 4 "" "")) (pc))) | |
2176 | (set (match_dup 0) (const_int 1)) | |
2177 | (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2))) | |
2178 | (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0))) | |
2179 | (set (pc) (if_then_else (lt (match_dup 6) (const_int 0)) | |
2180 | (label_ref (match_dup 4)) (pc)))] | |
ca7f5001 | 2181 | "TARGET_POWER" |
1fd4e8c1 RK |
2182 | " |
2183 | { operands[5] = gen_reg_rtx (CCUNSmode); | |
2184 | operands[6] = gen_reg_rtx (CCmode); | |
2185 | }") | |
2186 | ||
2187 | (define_expand "udivmodsi4" | |
cd2b37d9 RK |
2188 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
2189 | (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
1fd4e8c1 | 2190 | (match_operand:SI 2 "reg_or_cint_operand" ""))) |
cd2b37d9 | 2191 | (set (match_operand:SI 3 "gpc_reg_operand" "") |
1fd4e8c1 | 2192 | (umod:SI (match_dup 1) (match_dup 2)))])] |
8ffd9c51 | 2193 | "" |
1fd4e8c1 RK |
2194 | " |
2195 | { | |
2196 | rtx label = 0; | |
2197 | ||
8ffd9c51 | 2198 | if (! TARGET_POWER) |
c4d38ccb MM |
2199 | { |
2200 | if (! TARGET_POWERPC) | |
2201 | { | |
39403d82 DE |
2202 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
2203 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
c4d38ccb | 2204 | emit_insn (gen_divus_call ()); |
39403d82 DE |
2205 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
2206 | emit_move_insn (operands[3], gen_rtx_REG (SImode, 4)); | |
c4d38ccb MM |
2207 | DONE; |
2208 | } | |
2209 | else | |
2210 | FAIL; | |
2211 | } | |
0081a354 | 2212 | |
1fd4e8c1 RK |
2213 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0) |
2214 | { | |
2215 | operands[2] = force_reg (SImode, operands[2]); | |
2216 | label = gen_label_rtx (); | |
2217 | emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2], | |
2218 | operands[3], label)); | |
2219 | } | |
2220 | else | |
2221 | operands[2] = force_reg (SImode, operands[2]); | |
2222 | ||
2223 | emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2], | |
2224 | operands[3])); | |
2225 | if (label) | |
2226 | emit_label (label); | |
2227 | ||
2228 | DONE; | |
2229 | }") | |
0081a354 | 2230 | |
fada905b MM |
2231 | ;; AIX architecture-independent common-mode multiply (DImode), |
2232 | ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and | |
2233 | ;; R4; results in R3 and sometimes R4; link register always clobbered by bla | |
2234 | ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but | |
2235 | ;; assumed unused if generating common-mode, so ignore. | |
2236 | (define_insn "mulh_call" | |
2237 | [(set (reg:SI 3) | |
2238 | (truncate:SI | |
2239 | (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3)) | |
2240 | (sign_extend:DI (reg:SI 4))) | |
2241 | (const_int 32)))) | |
cf27b467 | 2242 | (clobber (match_scratch:SI 0 "=l"))] |
fada905b | 2243 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2244 | "bla __mulh" |
2245 | [(set_attr "type" "imul")]) | |
fada905b MM |
2246 | |
2247 | (define_insn "mull_call" | |
2248 | [(set (reg:DI 3) | |
2249 | (mult:DI (sign_extend:DI (reg:SI 3)) | |
2250 | (sign_extend:DI (reg:SI 4)))) | |
2251 | (clobber (match_scratch:SI 0 "=l")) | |
2252 | (clobber (reg:SI 0))] | |
2253 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2254 | "bla __mull" |
2255 | [(set_attr "type" "imul")]) | |
fada905b MM |
2256 | |
2257 | (define_insn "divss_call" | |
2258 | [(set (reg:SI 3) | |
2259 | (div:SI (reg:SI 3) (reg:SI 4))) | |
2260 | (set (reg:SI 4) | |
2261 | (mod:SI (reg:SI 3) (reg:SI 4))) | |
2262 | (clobber (match_scratch:SI 0 "=l")) | |
2263 | (clobber (reg:SI 0))] | |
2264 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2265 | "bla __divss" |
2266 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2267 | |
2268 | (define_insn "divus_call" | |
8ffd9c51 RK |
2269 | [(set (reg:SI 3) |
2270 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2271 | (set (reg:SI 4) | |
2272 | (umod:SI (reg:SI 3) (reg:SI 4))) | |
2273 | (clobber (match_scratch:SI 0 "=l")) | |
fada905b MM |
2274 | (clobber (reg:SI 0)) |
2275 | (clobber (match_scratch:CC 1 "=x")) | |
2276 | (clobber (reg:CC 69))] | |
2277 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2278 | "bla __divus" |
2279 | [(set_attr "type" "idiv")]) | |
fada905b MM |
2280 | |
2281 | (define_insn "quoss_call" | |
2282 | [(set (reg:SI 3) | |
2283 | (div:SI (reg:SI 3) (reg:SI 4))) | |
cf27b467 | 2284 | (clobber (match_scratch:SI 0 "=l"))] |
8ffd9c51 | 2285 | "! TARGET_POWER && ! TARGET_POWERPC" |
b7ff3d82 DE |
2286 | "bla __quoss" |
2287 | [(set_attr "type" "idiv")]) | |
0081a354 | 2288 | |
fada905b MM |
2289 | (define_insn "quous_call" |
2290 | [(set (reg:SI 3) | |
2291 | (udiv:SI (reg:SI 3) (reg:SI 4))) | |
2292 | (clobber (match_scratch:SI 0 "=l")) | |
2293 | (clobber (reg:SI 0)) | |
2294 | (clobber (match_scratch:CC 1 "=x")) | |
2295 | (clobber (reg:CC 69))] | |
2296 | "! TARGET_POWER && ! TARGET_POWERPC" | |
b7ff3d82 DE |
2297 | "bla __quous" |
2298 | [(set_attr "type" "idiv")]) | |
8ffd9c51 | 2299 | \f |
bb21487f | 2300 | ;; Logical instructions |
dfbdccdb GK |
2301 | ;; The logical instructions are mostly combined by using match_operator, |
2302 | ;; but the plain AND insns are somewhat different because there is no | |
2303 | ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all | |
2304 | ;; those rotate-and-mask operations. Thus, the AND insns come first. | |
2305 | ||
29ae5b89 JL |
2306 | (define_insn "andsi3" |
2307 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") | |
2308 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") | |
5f59ecb7 | 2309 | (match_operand:SI 2 "and_operand" "?r,T,K,L"))) |
29ae5b89 | 2310 | (clobber (match_scratch:CC 3 "=X,X,x,x"))] |
1fd4e8c1 RK |
2311 | "" |
2312 | "@ | |
2313 | and %0,%1,%2 | |
ca7f5001 RK |
2314 | {rlinm|rlwinm} %0,%1,0,%m2,%M2 |
2315 | {andil.|andi.} %0,%1,%b2 | |
520308bc DE |
2316 | {andiu.|andis.} %0,%1,%u2" |
2317 | [(set_attr "type" "*,*,compare,compare")]) | |
52d3af72 DE |
2318 | |
2319 | ;; Note to set cr's other than cr0 we do the and immediate and then | |
0ba1b2ff | 2320 | ;; the test again -- this avoids a mfcr which on the higher end |
52d3af72 | 2321 | ;; machines causes an execution serialization |
1fd4e8c1 | 2322 | |
7cd5235b | 2323 | (define_insn "*andsi3_internal2" |
52d3af72 DE |
2324 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2325 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2326 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
1fd4e8c1 | 2327 | (const_int 0))) |
52d3af72 DE |
2328 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) |
2329 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
4b8a63d6 | 2330 | "TARGET_32BIT" |
1fd4e8c1 RK |
2331 | "@ |
2332 | and. %3,%1,%2 | |
ca7f5001 RK |
2333 | {andil.|andi.} %3,%1,%b2 |
2334 | {andiu.|andis.} %3,%1,%u2 | |
52d3af72 DE |
2335 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 |
2336 | # | |
2337 | # | |
2338 | # | |
2339 | #" | |
2340 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2341 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
1fd4e8c1 | 2342 | |
0ba1b2ff AM |
2343 | (define_insn "*andsi3_internal3" |
2344 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2345 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2346 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2347 | (const_int 0))) | |
2348 | (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) | |
2349 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
683bdff7 | 2350 | "TARGET_64BIT" |
0ba1b2ff AM |
2351 | "@ |
2352 | # | |
2353 | {andil.|andi.} %3,%1,%b2 | |
2354 | {andiu.|andis.} %3,%1,%u2 | |
2355 | {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 | |
2356 | # | |
2357 | # | |
2358 | # | |
2359 | #" | |
2360 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2361 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2362 | ||
52d3af72 DE |
2363 | (define_split |
2364 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4ae234b0 GK |
2365 | (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "") |
2366 | (match_operand:GPR 2 "and_operand" "")) | |
1fd4e8c1 | 2367 | (const_int 0))) |
4ae234b0 | 2368 | (clobber (match_scratch:GPR 3 "")) |
52d3af72 | 2369 | (clobber (match_scratch:CC 4 ""))] |
0ba1b2ff | 2370 | "reload_completed" |
52d3af72 | 2371 | [(parallel [(set (match_dup 3) |
4ae234b0 GK |
2372 | (and:<MODE> (match_dup 1) |
2373 | (match_dup 2))) | |
52d3af72 DE |
2374 | (clobber (match_dup 4))]) |
2375 | (set (match_dup 0) | |
2376 | (compare:CC (match_dup 3) | |
2377 | (const_int 0)))] | |
2378 | "") | |
2379 | ||
0ba1b2ff AM |
2380 | ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the |
2381 | ;; whole 64 bit reg, and we don't know what is in the high 32 bits. | |
2382 | ||
2383 | (define_split | |
2384 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
2385 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2386 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2387 | (const_int 0))) | |
2388 | (clobber (match_scratch:SI 3 "")) | |
2389 | (clobber (match_scratch:CC 4 ""))] | |
2390 | "TARGET_POWERPC64 && reload_completed" | |
2391 | [(parallel [(set (match_dup 3) | |
2392 | (and:SI (match_dup 1) | |
2393 | (match_dup 2))) | |
2394 | (clobber (match_dup 4))]) | |
2395 | (set (match_dup 0) | |
2396 | (compare:CC (match_dup 3) | |
2397 | (const_int 0)))] | |
2398 | "") | |
2399 | ||
2400 | (define_insn "*andsi3_internal4" | |
52d3af72 DE |
2401 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") |
2402 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
5f59ecb7 | 2403 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) |
52d3af72 DE |
2404 | (const_int 0))) |
2405 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2406 | (and:SI (match_dup 1) | |
2407 | (match_dup 2))) | |
2408 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
4b8a63d6 | 2409 | "TARGET_32BIT" |
1fd4e8c1 RK |
2410 | "@ |
2411 | and. %0,%1,%2 | |
ca7f5001 RK |
2412 | {andil.|andi.} %0,%1,%b2 |
2413 | {andiu.|andis.} %0,%1,%u2 | |
52d3af72 DE |
2414 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 |
2415 | # | |
2416 | # | |
2417 | # | |
2418 | #" | |
2419 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2420 | (set_attr "length" "4,4,4,4,8,8,8,8")]) | |
2421 | ||
0ba1b2ff AM |
2422 | (define_insn "*andsi3_internal5" |
2423 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") | |
2424 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") | |
2425 | (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) | |
2426 | (const_int 0))) | |
2427 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") | |
2428 | (and:SI (match_dup 1) | |
2429 | (match_dup 2))) | |
2430 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] | |
683bdff7 | 2431 | "TARGET_64BIT" |
0ba1b2ff AM |
2432 | "@ |
2433 | # | |
2434 | {andil.|andi.} %0,%1,%b2 | |
2435 | {andiu.|andis.} %0,%1,%u2 | |
2436 | {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 | |
2437 | # | |
2438 | # | |
2439 | # | |
2440 | #" | |
2441 | [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") | |
2442 | (set_attr "length" "8,4,4,4,8,8,8,8")]) | |
2443 | ||
52d3af72 DE |
2444 | (define_split |
2445 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
2446 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2447 | (match_operand:SI 2 "and_operand" "")) | |
2448 | (const_int 0))) | |
2449 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2450 | (and:SI (match_dup 1) | |
2451 | (match_dup 2))) | |
2452 | (clobber (match_scratch:CC 4 ""))] | |
0ba1b2ff | 2453 | "reload_completed" |
52d3af72 DE |
2454 | [(parallel [(set (match_dup 0) |
2455 | (and:SI (match_dup 1) | |
2456 | (match_dup 2))) | |
2457 | (clobber (match_dup 4))]) | |
2458 | (set (match_dup 3) | |
2459 | (compare:CC (match_dup 0) | |
2460 | (const_int 0)))] | |
2461 | "") | |
1fd4e8c1 | 2462 | |
0ba1b2ff AM |
2463 | (define_split |
2464 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
2465 | (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
2466 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2467 | (const_int 0))) | |
2468 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2469 | (and:SI (match_dup 1) | |
2470 | (match_dup 2))) | |
2471 | (clobber (match_scratch:CC 4 ""))] | |
2472 | "TARGET_POWERPC64 && reload_completed" | |
2473 | [(parallel [(set (match_dup 0) | |
2474 | (and:SI (match_dup 1) | |
2475 | (match_dup 2))) | |
2476 | (clobber (match_dup 4))]) | |
2477 | (set (match_dup 3) | |
2478 | (compare:CC (match_dup 0) | |
2479 | (const_int 0)))] | |
2480 | "") | |
2481 | ||
2482 | ;; Handle the PowerPC64 rlwinm corner case | |
2483 | ||
2484 | (define_insn_and_split "*andsi3_internal6" | |
2485 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
2486 | (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
2487 | (match_operand:SI 2 "mask_operand_wrap" "i")))] | |
2488 | "TARGET_POWERPC64" | |
2489 | "#" | |
2490 | "TARGET_POWERPC64" | |
2491 | [(set (match_dup 0) | |
2492 | (and:SI (rotate:SI (match_dup 1) (match_dup 3)) | |
2493 | (match_dup 4))) | |
2494 | (set (match_dup 0) | |
2495 | (rotate:SI (match_dup 0) (match_dup 5)))] | |
2496 | " | |
2497 | { | |
2498 | int mb = extract_MB (operands[2]); | |
2499 | int me = extract_ME (operands[2]); | |
2500 | operands[3] = GEN_INT (me + 1); | |
2501 | operands[5] = GEN_INT (32 - (me + 1)); | |
2502 | operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); | |
2503 | }" | |
2504 | [(set_attr "length" "8")]) | |
2505 | ||
7cd5235b | 2506 | (define_expand "iorsi3" |
cd2b37d9 | 2507 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2508 | (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2509 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
7cd5235b | 2510 | "" |
f357808b RK |
2511 | " |
2512 | { | |
7cd5235b | 2513 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2514 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2515 | { |
2516 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2517 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2518 | ? operands[0] : gen_reg_rtx (SImode)); |
2519 | ||
a260abc9 DE |
2520 | emit_insn (gen_iorsi3 (tmp, operands[1], |
2521 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2522 | emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2523 | DONE; |
2524 | } | |
f357808b RK |
2525 | }") |
2526 | ||
7cd5235b | 2527 | (define_expand "xorsi3" |
cd2b37d9 | 2528 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7cd5235b | 2529 | (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1d328b19 | 2530 | (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] |
1fd4e8c1 | 2531 | "" |
7cd5235b | 2532 | " |
1fd4e8c1 | 2533 | { |
7cd5235b | 2534 | if (GET_CODE (operands[2]) == CONST_INT |
677a9668 | 2535 | && ! logical_operand (operands[2], SImode)) |
7cd5235b MM |
2536 | { |
2537 | HOST_WIDE_INT value = INTVAL (operands[2]); | |
677a9668 | 2538 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
7cd5235b MM |
2539 | ? operands[0] : gen_reg_rtx (SImode)); |
2540 | ||
a260abc9 DE |
2541 | emit_insn (gen_xorsi3 (tmp, operands[1], |
2542 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
2543 | emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); | |
7cd5235b MM |
2544 | DONE; |
2545 | } | |
1fd4e8c1 RK |
2546 | }") |
2547 | ||
dfbdccdb | 2548 | (define_insn "*boolsi3_internal1" |
7cd5235b | 2549 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 2550 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2551 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") |
2552 | (match_operand:SI 2 "logical_operand" "r,K,L")]))] | |
1fd4e8c1 RK |
2553 | "" |
2554 | "@ | |
dfbdccdb GK |
2555 | %q3 %0,%1,%2 |
2556 | {%q3il|%q3i} %0,%1,%b2 | |
2557 | {%q3iu|%q3is} %0,%1,%u2") | |
1fd4e8c1 | 2558 | |
dfbdccdb | 2559 | (define_insn "*boolsi3_internal2" |
52d3af72 | 2560 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 2561 | (compare:CC (match_operator:SI 4 "boolean_or_operator" |
dfbdccdb GK |
2562 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") |
2563 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2564 | (const_int 0))) | |
52d3af72 | 2565 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2566 | "TARGET_32BIT" |
52d3af72 | 2567 | "@ |
dfbdccdb | 2568 | %q4. %3,%1,%2 |
52d3af72 DE |
2569 | #" |
2570 | [(set_attr "type" "compare") | |
2571 | (set_attr "length" "4,8")]) | |
2572 | ||
2573 | (define_split | |
2574 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2575 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2576 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2577 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2578 | (const_int 0))) |
52d3af72 | 2579 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2580 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2581 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2582 | (set (match_dup 0) |
2583 | (compare:CC (match_dup 3) | |
2584 | (const_int 0)))] | |
2585 | "") | |
815cdc52 | 2586 | |
dfbdccdb | 2587 | (define_insn "*boolsi3_internal3" |
52d3af72 | 2588 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2589 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2590 | [(match_operand:SI 1 "gpc_reg_operand" "%r,r") | |
2591 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2592 | (const_int 0))) | |
52d3af72 | 2593 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2594 | (match_dup 4))] |
4b8a63d6 | 2595 | "TARGET_32BIT" |
52d3af72 | 2596 | "@ |
dfbdccdb | 2597 | %q4. %0,%1,%2 |
52d3af72 DE |
2598 | #" |
2599 | [(set_attr "type" "compare") | |
2600 | (set_attr "length" "4,8")]) | |
2601 | ||
2602 | (define_split | |
e72247f4 | 2603 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2604 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2605 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2606 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2607 | (const_int 0))) |
75540af0 | 2608 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2609 | (match_dup 4))] |
4b8a63d6 | 2610 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2611 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2612 | (set (match_dup 3) |
2613 | (compare:CC (match_dup 0) | |
2614 | (const_int 0)))] | |
2615 | "") | |
1fd4e8c1 | 2616 | |
6ae08853 | 2617 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 2618 | ;; each of which does one 16-bit part. This is used by combine. |
a260abc9 DE |
2619 | |
2620 | (define_split | |
2621 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
1d328b19 | 2622 | (match_operator:SI 3 "boolean_or_operator" |
dfbdccdb GK |
2623 | [(match_operand:SI 1 "gpc_reg_operand" "") |
2624 | (match_operand:SI 2 "non_logical_cint_operand" "")]))] | |
a260abc9 | 2625 | "" |
dfbdccdb GK |
2626 | [(set (match_dup 0) (match_dup 4)) |
2627 | (set (match_dup 0) (match_dup 5))] | |
a260abc9 DE |
2628 | " |
2629 | { | |
dfbdccdb GK |
2630 | rtx i; |
2631 | i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); | |
1c563bed | 2632 | operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
0f4c242b | 2633 | operands[1], i); |
dfbdccdb | 2634 | i = GEN_INT (INTVAL (operands[2]) & 0xffff); |
1c563bed | 2635 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
0f4c242b | 2636 | operands[0], i); |
a260abc9 DE |
2637 | }") |
2638 | ||
dfbdccdb | 2639 | (define_insn "*boolcsi3_internal1" |
cd2b37d9 | 2640 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2641 | (match_operator:SI 3 "boolean_operator" |
2642 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2643 | (match_operand:SI 2 "gpc_reg_operand" "r")]))] |
1fd4e8c1 | 2644 | "" |
dfbdccdb | 2645 | "%q3 %0,%2,%1") |
1fd4e8c1 | 2646 | |
dfbdccdb | 2647 | (define_insn "*boolcsi3_internal2" |
52d3af72 | 2648 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2649 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2650 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2651 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2652 | (const_int 0))) | |
52d3af72 | 2653 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2654 | "TARGET_32BIT" |
52d3af72 | 2655 | "@ |
dfbdccdb | 2656 | %q4. %3,%2,%1 |
52d3af72 DE |
2657 | #" |
2658 | [(set_attr "type" "compare") | |
2659 | (set_attr "length" "4,8")]) | |
2660 | ||
2661 | (define_split | |
2662 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2663 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2664 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2665 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2666 | (const_int 0))) |
52d3af72 | 2667 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2668 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2669 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2670 | (set (match_dup 0) |
2671 | (compare:CC (match_dup 3) | |
2672 | (const_int 0)))] | |
2673 | "") | |
1fd4e8c1 | 2674 | |
dfbdccdb | 2675 | (define_insn "*boolcsi3_internal3" |
52d3af72 | 2676 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2677 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2678 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2679 | (match_operand:SI 2 "gpc_reg_operand" "r,r")]) | |
2680 | (const_int 0))) | |
52d3af72 | 2681 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2682 | (match_dup 4))] |
4b8a63d6 | 2683 | "TARGET_32BIT" |
52d3af72 | 2684 | "@ |
dfbdccdb | 2685 | %q4. %0,%2,%1 |
52d3af72 DE |
2686 | #" |
2687 | [(set_attr "type" "compare") | |
2688 | (set_attr "length" "4,8")]) | |
2689 | ||
2690 | (define_split | |
e72247f4 | 2691 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2692 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2693 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2694 | (match_operand:SI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 2695 | (const_int 0))) |
75540af0 | 2696 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2697 | (match_dup 4))] |
4b8a63d6 | 2698 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2699 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2700 | (set (match_dup 3) |
2701 | (compare:CC (match_dup 0) | |
2702 | (const_int 0)))] | |
2703 | "") | |
2704 | ||
dfbdccdb | 2705 | (define_insn "*boolccsi3_internal1" |
cd2b37d9 | 2706 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
2707 | (match_operator:SI 3 "boolean_operator" |
2708 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) | |
40501e5f | 2709 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))] |
1fd4e8c1 | 2710 | "" |
dfbdccdb | 2711 | "%q3 %0,%1,%2") |
1fd4e8c1 | 2712 | |
dfbdccdb | 2713 | (define_insn "*boolccsi3_internal2" |
52d3af72 | 2714 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2715 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2716 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) | |
2717 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2718 | (const_int 0))) | |
52d3af72 | 2719 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 2720 | "TARGET_32BIT" |
52d3af72 | 2721 | "@ |
dfbdccdb | 2722 | %q4. %3,%1,%2 |
52d3af72 DE |
2723 | #" |
2724 | [(set_attr "type" "compare") | |
2725 | (set_attr "length" "4,8")]) | |
2726 | ||
2727 | (define_split | |
2728 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 2729 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2730 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2731 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2732 | (const_int 0))) |
52d3af72 | 2733 | (clobber (match_scratch:SI 3 ""))] |
4b8a63d6 | 2734 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2735 | [(set (match_dup 3) (match_dup 4)) |
52d3af72 DE |
2736 | (set (match_dup 0) |
2737 | (compare:CC (match_dup 3) | |
2738 | (const_int 0)))] | |
2739 | "") | |
1fd4e8c1 | 2740 | |
dfbdccdb | 2741 | (define_insn "*boolccsi3_internal3" |
52d3af72 | 2742 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
2743 | (compare:CC (match_operator:SI 4 "boolean_operator" |
2744 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) | |
2745 | (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) | |
2746 | (const_int 0))) | |
52d3af72 | 2747 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 2748 | (match_dup 4))] |
4b8a63d6 | 2749 | "TARGET_32BIT" |
52d3af72 | 2750 | "@ |
dfbdccdb | 2751 | %q4. %0,%1,%2 |
52d3af72 DE |
2752 | #" |
2753 | [(set_attr "type" "compare") | |
2754 | (set_attr "length" "4,8")]) | |
2755 | ||
2756 | (define_split | |
e72247f4 | 2757 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 2758 | (compare:CC (match_operator:SI 4 "boolean_operator" |
75540af0 JH |
2759 | [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) |
2760 | (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 2761 | (const_int 0))) |
75540af0 | 2762 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
dfbdccdb | 2763 | (match_dup 4))] |
4b8a63d6 | 2764 | "TARGET_32BIT && reload_completed" |
dfbdccdb | 2765 | [(set (match_dup 0) (match_dup 4)) |
52d3af72 DE |
2766 | (set (match_dup 3) |
2767 | (compare:CC (match_dup 0) | |
2768 | (const_int 0)))] | |
2769 | "") | |
1fd4e8c1 RK |
2770 | |
2771 | ;; maskir insn. We need four forms because things might be in arbitrary | |
2772 | ;; orders. Don't define forms that only set CR fields because these | |
2773 | ;; would modify an input register. | |
2774 | ||
7cd5235b | 2775 | (define_insn "*maskir_internal1" |
cd2b37d9 | 2776 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2777 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2778 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
2779 | (and:SI (match_dup 2) | |
cd2b37d9 | 2780 | (match_operand:SI 3 "gpc_reg_operand" "r"))))] |
ca7f5001 | 2781 | "TARGET_POWER" |
01def764 | 2782 | "maskir %0,%3,%2") |
1fd4e8c1 | 2783 | |
7cd5235b | 2784 | (define_insn "*maskir_internal2" |
242e8072 | 2785 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 RK |
2786 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) |
2787 | (match_operand:SI 1 "gpc_reg_operand" "0")) | |
cd2b37d9 | 2788 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
01def764 | 2789 | (match_dup 2))))] |
ca7f5001 | 2790 | "TARGET_POWER" |
01def764 | 2791 | "maskir %0,%3,%2") |
1fd4e8c1 | 2792 | |
7cd5235b | 2793 | (define_insn "*maskir_internal3" |
cd2b37d9 | 2794 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
01def764 | 2795 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") |
cd2b37d9 | 2796 | (match_operand:SI 3 "gpc_reg_operand" "r")) |
01def764 RK |
2797 | (and:SI (not:SI (match_dup 2)) |
2798 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2799 | "TARGET_POWER" |
01def764 | 2800 | "maskir %0,%3,%2") |
1fd4e8c1 | 2801 | |
7cd5235b | 2802 | (define_insn "*maskir_internal4" |
cd2b37d9 RK |
2803 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
2804 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
01def764 RK |
2805 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
2806 | (and:SI (not:SI (match_dup 2)) | |
2807 | (match_operand:SI 1 "gpc_reg_operand" "0"))))] | |
ca7f5001 | 2808 | "TARGET_POWER" |
01def764 | 2809 | "maskir %0,%3,%2") |
1fd4e8c1 | 2810 | |
7cd5235b | 2811 | (define_insn "*maskir_internal5" |
9ebbca7d | 2812 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2813 | (compare:CC |
9ebbca7d GK |
2814 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2815 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
01def764 | 2816 | (and:SI (match_dup 2) |
9ebbca7d | 2817 | (match_operand:SI 3 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 2818 | (const_int 0))) |
9ebbca7d | 2819 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2820 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2821 | (and:SI (match_dup 2) (match_dup 3))))] | |
ca7f5001 | 2822 | "TARGET_POWER" |
9ebbca7d GK |
2823 | "@ |
2824 | maskir. %0,%3,%2 | |
2825 | #" | |
2826 | [(set_attr "type" "compare") | |
2827 | (set_attr "length" "4,8")]) | |
2828 | ||
2829 | (define_split | |
2830 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2831 | (compare:CC | |
2832 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2833 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2834 | (and:SI (match_dup 2) | |
2835 | (match_operand:SI 3 "gpc_reg_operand" ""))) | |
2836 | (const_int 0))) | |
2837 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2838 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2839 | (and:SI (match_dup 2) (match_dup 3))))] | |
2840 | "TARGET_POWER && reload_completed" | |
2841 | [(set (match_dup 0) | |
2842 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2843 | (and:SI (match_dup 2) (match_dup 3)))) | |
2844 | (set (match_dup 4) | |
2845 | (compare:CC (match_dup 0) | |
2846 | (const_int 0)))] | |
2847 | "") | |
1fd4e8c1 | 2848 | |
7cd5235b | 2849 | (define_insn "*maskir_internal6" |
9ebbca7d | 2850 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2851 | (compare:CC |
9ebbca7d GK |
2852 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
2853 | (match_operand:SI 1 "gpc_reg_operand" "0,0")) | |
2854 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") | |
01def764 | 2855 | (match_dup 2))) |
1fd4e8c1 | 2856 | (const_int 0))) |
9ebbca7d | 2857 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2858 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) |
2859 | (and:SI (match_dup 3) (match_dup 2))))] | |
ca7f5001 | 2860 | "TARGET_POWER" |
9ebbca7d GK |
2861 | "@ |
2862 | maskir. %0,%3,%2 | |
2863 | #" | |
2864 | [(set_attr "type" "compare") | |
2865 | (set_attr "length" "4,8")]) | |
2866 | ||
2867 | (define_split | |
2868 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2869 | (compare:CC | |
2870 | (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "")) | |
2871 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
2872 | (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
2873 | (match_dup 2))) | |
2874 | (const_int 0))) | |
2875 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2876 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2877 | (and:SI (match_dup 3) (match_dup 2))))] | |
2878 | "TARGET_POWER && reload_completed" | |
2879 | [(set (match_dup 0) | |
2880 | (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) | |
2881 | (and:SI (match_dup 3) (match_dup 2)))) | |
2882 | (set (match_dup 4) | |
2883 | (compare:CC (match_dup 0) | |
2884 | (const_int 0)))] | |
2885 | "") | |
1fd4e8c1 | 2886 | |
7cd5235b | 2887 | (define_insn "*maskir_internal7" |
9ebbca7d | 2888 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
815cdc52 | 2889 | (compare:CC |
9ebbca7d GK |
2890 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r") |
2891 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
815cdc52 | 2892 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 2893 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
815cdc52 | 2894 | (const_int 0))) |
9ebbca7d | 2895 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
815cdc52 MM |
2896 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) |
2897 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2898 | "TARGET_POWER" | |
9ebbca7d GK |
2899 | "@ |
2900 | maskir. %0,%3,%2 | |
2901 | #" | |
2902 | [(set_attr "type" "compare") | |
2903 | (set_attr "length" "4,8")]) | |
2904 | ||
2905 | (define_split | |
2906 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2907 | (compare:CC | |
2908 | (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "") | |
2909 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
2910 | (and:SI (not:SI (match_dup 2)) | |
2911 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2912 | (const_int 0))) | |
2913 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2914 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
2915 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2916 | "TARGET_POWER && reload_completed" | |
2917 | [(set (match_dup 0) | |
2918 | (ior:SI (and:SI (match_dup 2) (match_dup 3)) | |
2919 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
2920 | (set (match_dup 4) | |
2921 | (compare:CC (match_dup 0) | |
2922 | (const_int 0)))] | |
2923 | "") | |
1fd4e8c1 | 2924 | |
7cd5235b | 2925 | (define_insn "*maskir_internal8" |
9ebbca7d | 2926 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 2927 | (compare:CC |
9ebbca7d GK |
2928 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r") |
2929 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
01def764 | 2930 | (and:SI (not:SI (match_dup 2)) |
9ebbca7d | 2931 | (match_operand:SI 1 "gpc_reg_operand" "0,0"))) |
1fd4e8c1 | 2932 | (const_int 0))) |
9ebbca7d | 2933 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
01def764 RK |
2934 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) |
2935 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
ca7f5001 | 2936 | "TARGET_POWER" |
9ebbca7d GK |
2937 | "@ |
2938 | maskir. %0,%3,%2 | |
2939 | #" | |
2940 | [(set_attr "type" "compare") | |
2941 | (set_attr "length" "4,8")]) | |
fcce224d | 2942 | |
9ebbca7d GK |
2943 | (define_split |
2944 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
2945 | (compare:CC | |
2946 | (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "") | |
2947 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
2948 | (and:SI (not:SI (match_dup 2)) | |
2949 | (match_operand:SI 1 "gpc_reg_operand" ""))) | |
2950 | (const_int 0))) | |
2951 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
2952 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
2953 | (and:SI (not:SI (match_dup 2)) (match_dup 1))))] | |
2954 | "TARGET_POWER && reload_completed" | |
2955 | [(set (match_dup 0) | |
2956 | (ior:SI (and:SI (match_dup 3) (match_dup 2)) | |
2957 | (and:SI (not:SI (match_dup 2)) (match_dup 1)))) | |
2958 | (set (match_dup 4) | |
2959 | (compare:CC (match_dup 0) | |
2960 | (const_int 0)))] | |
2961 | "") | |
fcce224d | 2962 | \f |
1fd4e8c1 RK |
2963 | ;; Rotate and shift insns, in all their variants. These support shifts, |
2964 | ;; field inserts and extracts, and various combinations thereof. | |
034c1be0 | 2965 | (define_expand "insv" |
0ad91047 DE |
2966 | [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") |
2967 | (match_operand:SI 1 "const_int_operand" "") | |
2968 | (match_operand:SI 2 "const_int_operand" "")) | |
2969 | (match_operand 3 "gpc_reg_operand" ""))] | |
034c1be0 MM |
2970 | "" |
2971 | " | |
2972 | { | |
2973 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
2974 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
2975 | compiler if the address of the structure is taken later. */ | |
2976 | if (GET_CODE (operands[0]) == SUBREG | |
2977 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
2978 | FAIL; | |
a78e33fc DE |
2979 | |
2980 | if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) | |
2981 | emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3])); | |
2982 | else | |
2983 | emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3])); | |
2984 | DONE; | |
034c1be0 MM |
2985 | }") |
2986 | ||
a78e33fc | 2987 | (define_insn "insvsi" |
cd2b37d9 | 2988 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 RK |
2989 | (match_operand:SI 1 "const_int_operand" "i") |
2990 | (match_operand:SI 2 "const_int_operand" "i")) | |
cd2b37d9 | 2991 | (match_operand:SI 3 "gpc_reg_operand" "r"))] |
1fd4e8c1 RK |
2992 | "" |
2993 | "* | |
2994 | { | |
2995 | int start = INTVAL (operands[2]) & 31; | |
2996 | int size = INTVAL (operands[1]) & 31; | |
2997 | ||
89e9f3a8 MM |
2998 | operands[4] = GEN_INT (32 - start - size); |
2999 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3000 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
3001 | }" |
3002 | [(set_attr "type" "insert_word")]) | |
1fd4e8c1 | 3003 | |
a78e33fc | 3004 | (define_insn "*insvsi_internal1" |
d56d506a RK |
3005 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3006 | (match_operand:SI 1 "const_int_operand" "i") | |
3007 | (match_operand:SI 2 "const_int_operand" "i")) | |
6d0a8091 | 3008 | (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r") |
d56d506a | 3009 | (match_operand:SI 4 "const_int_operand" "i")))] |
f0dc3f49 | 3010 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3011 | "* |
3012 | { | |
3013 | int shift = INTVAL (operands[4]) & 31; | |
3014 | int start = INTVAL (operands[2]) & 31; | |
3015 | int size = INTVAL (operands[1]) & 31; | |
3016 | ||
89e9f3a8 | 3017 | operands[4] = GEN_INT (shift - start - size); |
6d0a8091 | 3018 | operands[1] = GEN_INT (start + size - 1); |
a66078ee | 3019 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
3020 | }" |
3021 | [(set_attr "type" "insert_word")]) | |
d56d506a | 3022 | |
a78e33fc | 3023 | (define_insn "*insvsi_internal2" |
d56d506a RK |
3024 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3025 | (match_operand:SI 1 "const_int_operand" "i") | |
3026 | (match_operand:SI 2 "const_int_operand" "i")) | |
3027 | (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3028 | (match_operand:SI 4 "const_int_operand" "i")))] | |
f0dc3f49 | 3029 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3030 | "* |
3031 | { | |
3032 | int shift = INTVAL (operands[4]) & 31; | |
3033 | int start = INTVAL (operands[2]) & 31; | |
3034 | int size = INTVAL (operands[1]) & 31; | |
3035 | ||
89e9f3a8 MM |
3036 | operands[4] = GEN_INT (32 - shift - start - size); |
3037 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3038 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
3039 | }" |
3040 | [(set_attr "type" "insert_word")]) | |
d56d506a | 3041 | |
a78e33fc | 3042 | (define_insn "*insvsi_internal3" |
d56d506a RK |
3043 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3044 | (match_operand:SI 1 "const_int_operand" "i") | |
3045 | (match_operand:SI 2 "const_int_operand" "i")) | |
3046 | (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3047 | (match_operand:SI 4 "const_int_operand" "i")))] | |
95e8f2f3 | 3048 | "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" |
d56d506a RK |
3049 | "* |
3050 | { | |
3051 | int shift = INTVAL (operands[4]) & 31; | |
3052 | int start = INTVAL (operands[2]) & 31; | |
3053 | int size = INTVAL (operands[1]) & 31; | |
3054 | ||
89e9f3a8 MM |
3055 | operands[4] = GEN_INT (32 - shift - start - size); |
3056 | operands[1] = GEN_INT (start + size - 1); | |
a66078ee | 3057 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; |
8e8238f1 DE |
3058 | }" |
3059 | [(set_attr "type" "insert_word")]) | |
d56d506a | 3060 | |
a78e33fc | 3061 | (define_insn "*insvsi_internal4" |
d56d506a RK |
3062 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
3063 | (match_operand:SI 1 "const_int_operand" "i") | |
3064 | (match_operand:SI 2 "const_int_operand" "i")) | |
3065 | (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3066 | (match_operand:SI 4 "const_int_operand" "i") | |
3067 | (match_operand:SI 5 "const_int_operand" "i")))] | |
3068 | "INTVAL (operands[4]) >= INTVAL (operands[1])" | |
3069 | "* | |
3070 | { | |
3071 | int extract_start = INTVAL (operands[5]) & 31; | |
3072 | int extract_size = INTVAL (operands[4]) & 31; | |
3073 | int insert_start = INTVAL (operands[2]) & 31; | |
3074 | int insert_size = INTVAL (operands[1]) & 31; | |
3075 | ||
3076 | /* Align extract field with insert field */ | |
3a598fbe | 3077 | operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); |
89e9f3a8 | 3078 | operands[1] = GEN_INT (insert_start + insert_size - 1); |
a66078ee | 3079 | return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\"; |
8e8238f1 DE |
3080 | }" |
3081 | [(set_attr "type" "insert_word")]) | |
d56d506a | 3082 | |
f241bf89 EC |
3083 | ;; combine patterns for rlwimi |
3084 | (define_insn "*insvsi_internal5" | |
3085 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
3086 | (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0") | |
3087 | (match_operand:SI 1 "mask_operand" "i")) | |
3088 | (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3089 | (match_operand:SI 2 "const_int_operand" "i")) | |
3090 | (match_operand:SI 5 "mask_operand" "i"))))] | |
3091 | "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])" | |
3092 | "* | |
3093 | { | |
3094 | int me = extract_ME(operands[5]); | |
3095 | int mb = extract_MB(operands[5]); | |
3096 | operands[4] = GEN_INT(32 - INTVAL(operands[2])); | |
3097 | operands[2] = GEN_INT(mb); | |
3098 | operands[1] = GEN_INT(me); | |
3099 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; | |
3100 | }" | |
3101 | [(set_attr "type" "insert_word")]) | |
3102 | ||
3103 | (define_insn "*insvsi_internal6" | |
3104 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
3105 | (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") | |
3106 | (match_operand:SI 2 "const_int_operand" "i")) | |
3107 | (match_operand:SI 5 "mask_operand" "i")) | |
3108 | (and:SI (match_operand:SI 4 "gpc_reg_operand" "0") | |
3109 | (match_operand:SI 1 "mask_operand" "i"))))] | |
3110 | "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])" | |
3111 | "* | |
3112 | { | |
3113 | int me = extract_ME(operands[5]); | |
3114 | int mb = extract_MB(operands[5]); | |
3115 | operands[4] = GEN_INT(32 - INTVAL(operands[2])); | |
3116 | operands[2] = GEN_INT(mb); | |
3117 | operands[1] = GEN_INT(me); | |
3118 | return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\"; | |
3119 | }" | |
3120 | [(set_attr "type" "insert_word")]) | |
3121 | ||
a78e33fc | 3122 | (define_insn "insvdi" |
685f3906 | 3123 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") |
a78e33fc DE |
3124 | (match_operand:SI 1 "const_int_operand" "i") |
3125 | (match_operand:SI 2 "const_int_operand" "i")) | |
685f3906 DE |
3126 | (match_operand:DI 3 "gpc_reg_operand" "r"))] |
3127 | "TARGET_POWERPC64" | |
3128 | "* | |
3129 | { | |
3130 | int start = INTVAL (operands[2]) & 63; | |
3131 | int size = INTVAL (operands[1]) & 63; | |
3132 | ||
a78e33fc DE |
3133 | operands[1] = GEN_INT (64 - start - size); |
3134 | return \"rldimi %0,%3,%H1,%H2\"; | |
685f3906 DE |
3135 | }") |
3136 | ||
11ac38b2 DE |
3137 | (define_insn "*insvdi_internal2" |
3138 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") | |
3139 | (match_operand:SI 1 "const_int_operand" "i") | |
3140 | (match_operand:SI 2 "const_int_operand" "i")) | |
3141 | (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r") | |
3142 | (match_operand:SI 4 "const_int_operand" "i")))] | |
3143 | "TARGET_POWERPC64 | |
3144 | && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])" | |
3145 | "* | |
3146 | { | |
3147 | int shift = INTVAL (operands[4]) & 63; | |
3148 | int start = (INTVAL (operands[2]) & 63) - 32; | |
3149 | int size = INTVAL (operands[1]) & 63; | |
3150 | ||
3151 | operands[4] = GEN_INT (64 - shift - start - size); | |
3152 | operands[2] = GEN_INT (start); | |
3153 | operands[1] = GEN_INT (start + size - 1); | |
3154 | return \"rlwimi %0,%3,%h4,%h2,%h1\"; | |
3155 | }") | |
3156 | ||
3157 | (define_insn "*insvdi_internal3" | |
3158 | [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") | |
3159 | (match_operand:SI 1 "const_int_operand" "i") | |
3160 | (match_operand:SI 2 "const_int_operand" "i")) | |
3161 | (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r") | |
3162 | (match_operand:SI 4 "const_int_operand" "i")))] | |
3163 | "TARGET_POWERPC64 | |
3164 | && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])" | |
3165 | "* | |
3166 | { | |
3167 | int shift = INTVAL (operands[4]) & 63; | |
3168 | int start = (INTVAL (operands[2]) & 63) - 32; | |
3169 | int size = INTVAL (operands[1]) & 63; | |
3170 | ||
3171 | operands[4] = GEN_INT (64 - shift - start - size); | |
3172 | operands[2] = GEN_INT (start); | |
3173 | operands[1] = GEN_INT (start + size - 1); | |
3174 | return \"rlwimi %0,%3,%h4,%h2,%h1\"; | |
3175 | }") | |
3176 | ||
034c1be0 | 3177 | (define_expand "extzv" |
0ad91047 DE |
3178 | [(set (match_operand 0 "gpc_reg_operand" "") |
3179 | (zero_extract (match_operand 1 "gpc_reg_operand" "") | |
3180 | (match_operand:SI 2 "const_int_operand" "") | |
3181 | (match_operand:SI 3 "const_int_operand" "")))] | |
034c1be0 MM |
3182 | "" |
3183 | " | |
3184 | { | |
3185 | /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since | |
3186 | the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the | |
3187 | compiler if the address of the structure is taken later. */ | |
3188 | if (GET_CODE (operands[0]) == SUBREG | |
3189 | && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) | |
3190 | FAIL; | |
a78e33fc DE |
3191 | |
3192 | if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) | |
3193 | emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3])); | |
3194 | else | |
3195 | emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3])); | |
3196 | DONE; | |
034c1be0 MM |
3197 | }") |
3198 | ||
a78e33fc | 3199 | (define_insn "extzvsi" |
cd2b37d9 RK |
3200 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3201 | (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3202 | (match_operand:SI 2 "const_int_operand" "i") |
3203 | (match_operand:SI 3 "const_int_operand" "i")))] | |
3204 | "" | |
3205 | "* | |
3206 | { | |
3207 | int start = INTVAL (operands[3]) & 31; | |
3208 | int size = INTVAL (operands[2]) & 31; | |
3209 | ||
3210 | if (start + size >= 32) | |
3211 | operands[3] = const0_rtx; | |
3212 | else | |
89e9f3a8 | 3213 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3214 | return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\"; |
1fd4e8c1 RK |
3215 | }") |
3216 | ||
a78e33fc | 3217 | (define_insn "*extzvsi_internal1" |
9ebbca7d GK |
3218 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3219 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3220 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3221 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3222 | (const_int 0))) |
9ebbca7d | 3223 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3224 | "" |
1fd4e8c1 RK |
3225 | "* |
3226 | { | |
3227 | int start = INTVAL (operands[3]) & 31; | |
3228 | int size = INTVAL (operands[2]) & 31; | |
3229 | ||
9ebbca7d GK |
3230 | /* Force split for non-cc0 compare. */ |
3231 | if (which_alternative == 1) | |
3232 | return \"#\"; | |
3233 | ||
43a88a8c | 3234 | /* If the bit-field being tested fits in the upper or lower half of a |
a7a975e1 RK |
3235 | word, it is possible to use andiu. or andil. to test it. This is |
3236 | useful because the condition register set-use delay is smaller for | |
3237 | andi[ul]. than for rlinm. This doesn't work when the starting bit | |
3238 | position is 0 because the LT and GT bits may be set wrong. */ | |
3239 | ||
3240 | if ((start > 0 && start + size <= 16) || start >= 16) | |
df031c43 | 3241 | { |
3a598fbe | 3242 | operands[3] = GEN_INT (((1 << (16 - (start & 15))) |
df031c43 RK |
3243 | - (1 << (16 - (start & 15) - size)))); |
3244 | if (start < 16) | |
ca7f5001 | 3245 | return \"{andiu.|andis.} %4,%1,%3\"; |
df031c43 | 3246 | else |
ca7f5001 | 3247 | return \"{andil.|andi.} %4,%1,%3\"; |
df031c43 | 3248 | } |
7e69e155 | 3249 | |
1fd4e8c1 RK |
3250 | if (start + size >= 32) |
3251 | operands[3] = const0_rtx; | |
3252 | else | |
89e9f3a8 | 3253 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3254 | return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\"; |
1fd4e8c1 | 3255 | }" |
9ebbca7d GK |
3256 | [(set_attr "type" "compare") |
3257 | (set_attr "length" "4,8")]) | |
3258 | ||
3259 | (define_split | |
3260 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3261 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3262 | (match_operand:SI 2 "const_int_operand" "") | |
3263 | (match_operand:SI 3 "const_int_operand" "")) | |
3264 | (const_int 0))) | |
3265 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3266 | "reload_completed" |
9ebbca7d GK |
3267 | [(set (match_dup 4) |
3268 | (zero_extract:SI (match_dup 1) (match_dup 2) | |
3269 | (match_dup 3))) | |
3270 | (set (match_dup 0) | |
3271 | (compare:CC (match_dup 4) | |
3272 | (const_int 0)))] | |
3273 | "") | |
1fd4e8c1 | 3274 | |
a78e33fc | 3275 | (define_insn "*extzvsi_internal2" |
9ebbca7d GK |
3276 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3277 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3278 | (match_operand:SI 2 "const_int_operand" "i,i") | |
3279 | (match_operand:SI 3 "const_int_operand" "i,i")) | |
1fd4e8c1 | 3280 | (const_int 0))) |
9ebbca7d | 3281 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3282 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] |
ce71f754 | 3283 | "" |
1fd4e8c1 RK |
3284 | "* |
3285 | { | |
3286 | int start = INTVAL (operands[3]) & 31; | |
3287 | int size = INTVAL (operands[2]) & 31; | |
3288 | ||
9ebbca7d GK |
3289 | /* Force split for non-cc0 compare. */ |
3290 | if (which_alternative == 1) | |
3291 | return \"#\"; | |
3292 | ||
bc401279 | 3293 | /* Since we are using the output value, we can't ignore any need for |
43a88a8c | 3294 | a shift. The bit-field must end at the LSB. */ |
bc401279 | 3295 | if (start >= 16 && start + size == 32) |
df031c43 | 3296 | { |
bc401279 AM |
3297 | operands[3] = GEN_INT ((1 << size) - 1); |
3298 | return \"{andil.|andi.} %0,%1,%3\"; | |
df031c43 | 3299 | } |
7e69e155 | 3300 | |
1fd4e8c1 RK |
3301 | if (start + size >= 32) |
3302 | operands[3] = const0_rtx; | |
3303 | else | |
89e9f3a8 | 3304 | operands[3] = GEN_INT (start + size); |
ca7f5001 | 3305 | return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; |
1fd4e8c1 | 3306 | }" |
ce71f754 | 3307 | [(set_attr "type" "compare") |
9ebbca7d GK |
3308 | (set_attr "length" "4,8")]) |
3309 | ||
3310 | (define_split | |
3311 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3312 | (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3313 | (match_operand:SI 2 "const_int_operand" "") | |
3314 | (match_operand:SI 3 "const_int_operand" "")) | |
3315 | (const_int 0))) | |
3316 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3317 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] | |
ce71f754 | 3318 | "reload_completed" |
9ebbca7d GK |
3319 | [(set (match_dup 0) |
3320 | (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) | |
3321 | (set (match_dup 4) | |
3322 | (compare:CC (match_dup 0) | |
3323 | (const_int 0)))] | |
3324 | "") | |
1fd4e8c1 | 3325 | |
a78e33fc | 3326 | (define_insn "extzvdi" |
685f3906 DE |
3327 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
3328 | (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3329 | (match_operand:SI 2 "const_int_operand" "i") |
3330 | (match_operand:SI 3 "const_int_operand" "i")))] | |
685f3906 DE |
3331 | "TARGET_POWERPC64" |
3332 | "* | |
3333 | { | |
3334 | int start = INTVAL (operands[3]) & 63; | |
3335 | int size = INTVAL (operands[2]) & 63; | |
3336 | ||
3337 | if (start + size >= 64) | |
3338 | operands[3] = const0_rtx; | |
3339 | else | |
89e9f3a8 MM |
3340 | operands[3] = GEN_INT (start + size); |
3341 | operands[2] = GEN_INT (64 - size); | |
685f3906 DE |
3342 | return \"rldicl %0,%1,%3,%2\"; |
3343 | }") | |
3344 | ||
a78e33fc | 3345 | (define_insn "*extzvdi_internal1" |
29ae5b89 JL |
3346 | [(set (match_operand:CC 0 "gpc_reg_operand" "=x") |
3347 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3348 | (match_operand:SI 2 "const_int_operand" "i") |
3349 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3350 | (const_int 0))) |
29ae5b89 | 3351 | (clobber (match_scratch:DI 4 "=r"))] |
683bdff7 | 3352 | "TARGET_64BIT" |
685f3906 DE |
3353 | "* |
3354 | { | |
3355 | int start = INTVAL (operands[3]) & 63; | |
3356 | int size = INTVAL (operands[2]) & 63; | |
3357 | ||
3358 | if (start + size >= 64) | |
3359 | operands[3] = const0_rtx; | |
3360 | else | |
89e9f3a8 MM |
3361 | operands[3] = GEN_INT (start + size); |
3362 | operands[2] = GEN_INT (64 - size); | |
685f3906 | 3363 | return \"rldicl. %4,%1,%3,%2\"; |
9a3c428b DE |
3364 | }" |
3365 | [(set_attr "type" "compare")]) | |
685f3906 | 3366 | |
a78e33fc | 3367 | (define_insn "*extzvdi_internal2" |
29ae5b89 JL |
3368 | [(set (match_operand:CC 4 "gpc_reg_operand" "=x") |
3369 | (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
a78e33fc DE |
3370 | (match_operand:SI 2 "const_int_operand" "i") |
3371 | (match_operand:SI 3 "const_int_operand" "i")) | |
685f3906 | 3372 | (const_int 0))) |
29ae5b89 | 3373 | (set (match_operand:DI 0 "gpc_reg_operand" "=r") |
685f3906 | 3374 | (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] |
683bdff7 | 3375 | "TARGET_64BIT" |
685f3906 DE |
3376 | "* |
3377 | { | |
3378 | int start = INTVAL (operands[3]) & 63; | |
3379 | int size = INTVAL (operands[2]) & 63; | |
3380 | ||
3381 | if (start + size >= 64) | |
3382 | operands[3] = const0_rtx; | |
3383 | else | |
89e9f3a8 MM |
3384 | operands[3] = GEN_INT (start + size); |
3385 | operands[2] = GEN_INT (64 - size); | |
685f3906 | 3386 | return \"rldicl. %0,%1,%3,%2\"; |
9a3c428b DE |
3387 | }" |
3388 | [(set_attr "type" "compare")]) | |
685f3906 | 3389 | |
1fd4e8c1 | 3390 | (define_insn "rotlsi3" |
cd2b37d9 RK |
3391 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3392 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
3393 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] |
3394 | "" | |
ca7f5001 | 3395 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff") |
1fd4e8c1 | 3396 | |
a260abc9 | 3397 | (define_insn "*rotlsi3_internal2" |
9ebbca7d GK |
3398 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3399 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3400 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3401 | (const_int 0))) |
9ebbca7d | 3402 | (clobber (match_scratch:SI 3 "=r,r"))] |
ce71f754 | 3403 | "" |
9ebbca7d GK |
3404 | "@ |
3405 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff | |
3406 | #" | |
3407 | [(set_attr "type" "delayed_compare") | |
3408 | (set_attr "length" "4,8")]) | |
3409 | ||
3410 | (define_split | |
3411 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3412 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3413 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3414 | (const_int 0))) | |
3415 | (clobber (match_scratch:SI 3 ""))] | |
ce71f754 | 3416 | "reload_completed" |
9ebbca7d GK |
3417 | [(set (match_dup 3) |
3418 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3419 | (set (match_dup 0) | |
3420 | (compare:CC (match_dup 3) | |
3421 | (const_int 0)))] | |
3422 | "") | |
1fd4e8c1 | 3423 | |
a260abc9 | 3424 | (define_insn "*rotlsi3_internal3" |
9ebbca7d GK |
3425 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3426 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3427 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
1fd4e8c1 | 3428 | (const_int 0))) |
9ebbca7d | 3429 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3430 | (rotate:SI (match_dup 1) (match_dup 2)))] |
ce71f754 | 3431 | "" |
9ebbca7d GK |
3432 | "@ |
3433 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff | |
3434 | #" | |
3435 | [(set_attr "type" "delayed_compare") | |
3436 | (set_attr "length" "4,8")]) | |
3437 | ||
3438 | (define_split | |
3439 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3440 | (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3441 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3442 | (const_int 0))) | |
3443 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3444 | (rotate:SI (match_dup 1) (match_dup 2)))] | |
ce71f754 | 3445 | "reload_completed" |
9ebbca7d GK |
3446 | [(set (match_dup 0) |
3447 | (rotate:SI (match_dup 1) (match_dup 2))) | |
3448 | (set (match_dup 3) | |
3449 | (compare:CC (match_dup 0) | |
3450 | (const_int 0)))] | |
3451 | "") | |
1fd4e8c1 | 3452 | |
a260abc9 | 3453 | (define_insn "*rotlsi3_internal4" |
cd2b37d9 RK |
3454 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3455 | (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3456 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) |
ce71f754 | 3457 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3458 | "" |
ca7f5001 | 3459 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 | 3460 | |
a260abc9 | 3461 | (define_insn "*rotlsi3_internal5" |
9ebbca7d | 3462 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3463 | (compare:CC (and:SI |
9ebbca7d GK |
3464 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3465 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 3466 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3467 | (const_int 0))) |
9ebbca7d | 3468 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3469 | "" |
9ebbca7d GK |
3470 | "@ |
3471 | {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 | |
3472 | #" | |
3473 | [(set_attr "type" "delayed_compare") | |
3474 | (set_attr "length" "4,8")]) | |
3475 | ||
3476 | (define_split | |
3477 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3478 | (compare:CC (and:SI | |
3479 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3480 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3481 | (match_operand:SI 3 "mask_operand" "")) | |
3482 | (const_int 0))) | |
3483 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3484 | "reload_completed" |
9ebbca7d GK |
3485 | [(set (match_dup 4) |
3486 | (and:SI (rotate:SI (match_dup 1) | |
3487 | (match_dup 2)) | |
3488 | (match_dup 3))) | |
3489 | (set (match_dup 0) | |
3490 | (compare:CC (match_dup 4) | |
3491 | (const_int 0)))] | |
3492 | "") | |
1fd4e8c1 | 3493 | |
a260abc9 | 3494 | (define_insn "*rotlsi3_internal6" |
9ebbca7d | 3495 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3496 | (compare:CC (and:SI |
9ebbca7d GK |
3497 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3498 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ce71f754 | 3499 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3500 | (const_int 0))) |
9ebbca7d | 3501 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3502 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3503 | "" |
9ebbca7d GK |
3504 | "@ |
3505 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 | |
3506 | #" | |
3507 | [(set_attr "type" "delayed_compare") | |
3508 | (set_attr "length" "4,8")]) | |
3509 | ||
3510 | (define_split | |
3511 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3512 | (compare:CC (and:SI | |
3513 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3514 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3515 | (match_operand:SI 3 "mask_operand" "")) | |
3516 | (const_int 0))) | |
3517 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3518 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 3519 | "reload_completed" |
9ebbca7d GK |
3520 | [(set (match_dup 0) |
3521 | (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3522 | (set (match_dup 4) | |
3523 | (compare:CC (match_dup 0) | |
3524 | (const_int 0)))] | |
3525 | "") | |
1fd4e8c1 | 3526 | |
a260abc9 | 3527 | (define_insn "*rotlsi3_internal7" |
cd2b37d9 | 3528 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3529 | (zero_extend:SI |
3530 | (subreg:QI | |
cd2b37d9 | 3531 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3532 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3533 | "" | |
ca7f5001 | 3534 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff") |
1fd4e8c1 | 3535 | |
a260abc9 | 3536 | (define_insn "*rotlsi3_internal8" |
9ebbca7d | 3537 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3538 | (compare:CC (zero_extend:SI |
3539 | (subreg:QI | |
9ebbca7d GK |
3540 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3541 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3542 | (const_int 0))) |
9ebbca7d | 3543 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3544 | "" |
9ebbca7d GK |
3545 | "@ |
3546 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff | |
3547 | #" | |
3548 | [(set_attr "type" "delayed_compare") | |
3549 | (set_attr "length" "4,8")]) | |
3550 | ||
3551 | (define_split | |
3552 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3553 | (compare:CC (zero_extend:SI | |
3554 | (subreg:QI | |
3555 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3556 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3557 | (const_int 0))) | |
3558 | (clobber (match_scratch:SI 3 ""))] | |
3559 | "reload_completed" | |
3560 | [(set (match_dup 3) | |
3561 | (zero_extend:SI (subreg:QI | |
3562 | (rotate:SI (match_dup 1) | |
3563 | (match_dup 2)) 0))) | |
3564 | (set (match_dup 0) | |
3565 | (compare:CC (match_dup 3) | |
3566 | (const_int 0)))] | |
3567 | "") | |
1fd4e8c1 | 3568 | |
a260abc9 | 3569 | (define_insn "*rotlsi3_internal9" |
9ebbca7d | 3570 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3571 | (compare:CC (zero_extend:SI |
3572 | (subreg:QI | |
9ebbca7d GK |
3573 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3574 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3575 | (const_int 0))) |
9ebbca7d | 3576 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3577 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3578 | "" | |
9ebbca7d GK |
3579 | "@ |
3580 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff | |
3581 | #" | |
3582 | [(set_attr "type" "delayed_compare") | |
3583 | (set_attr "length" "4,8")]) | |
3584 | ||
3585 | (define_split | |
3586 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3587 | (compare:CC (zero_extend:SI | |
3588 | (subreg:QI | |
3589 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3590 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3591 | (const_int 0))) | |
3592 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3593 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3594 | "reload_completed" | |
3595 | [(set (match_dup 0) | |
3596 | (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3597 | (set (match_dup 3) | |
3598 | (compare:CC (match_dup 0) | |
3599 | (const_int 0)))] | |
3600 | "") | |
1fd4e8c1 | 3601 | |
a260abc9 | 3602 | (define_insn "*rotlsi3_internal10" |
cd2b37d9 | 3603 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
3604 | (zero_extend:SI |
3605 | (subreg:HI | |
cd2b37d9 | 3606 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 RK |
3607 | (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] |
3608 | "" | |
ca7f5001 | 3609 | "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff") |
1fd4e8c1 | 3610 | |
a260abc9 | 3611 | (define_insn "*rotlsi3_internal11" |
9ebbca7d | 3612 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3613 | (compare:CC (zero_extend:SI |
3614 | (subreg:HI | |
9ebbca7d GK |
3615 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3616 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3617 | (const_int 0))) |
9ebbca7d | 3618 | (clobber (match_scratch:SI 3 "=r,r"))] |
1fd4e8c1 | 3619 | "" |
9ebbca7d GK |
3620 | "@ |
3621 | {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff | |
3622 | #" | |
3623 | [(set_attr "type" "delayed_compare") | |
3624 | (set_attr "length" "4,8")]) | |
3625 | ||
3626 | (define_split | |
3627 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3628 | (compare:CC (zero_extend:SI | |
3629 | (subreg:HI | |
3630 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3631 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3632 | (const_int 0))) | |
3633 | (clobber (match_scratch:SI 3 ""))] | |
3634 | "reload_completed" | |
3635 | [(set (match_dup 3) | |
3636 | (zero_extend:SI (subreg:HI | |
3637 | (rotate:SI (match_dup 1) | |
3638 | (match_dup 2)) 0))) | |
3639 | (set (match_dup 0) | |
3640 | (compare:CC (match_dup 3) | |
3641 | (const_int 0)))] | |
3642 | "") | |
1fd4e8c1 | 3643 | |
a260abc9 | 3644 | (define_insn "*rotlsi3_internal12" |
9ebbca7d | 3645 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
3646 | (compare:CC (zero_extend:SI |
3647 | (subreg:HI | |
9ebbca7d GK |
3648 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3649 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
1fd4e8c1 | 3650 | (const_int 0))) |
9ebbca7d | 3651 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
3652 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] |
3653 | "" | |
9ebbca7d GK |
3654 | "@ |
3655 | {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff | |
3656 | #" | |
3657 | [(set_attr "type" "delayed_compare") | |
3658 | (set_attr "length" "4,8")]) | |
3659 | ||
3660 | (define_split | |
3661 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3662 | (compare:CC (zero_extend:SI | |
3663 | (subreg:HI | |
3664 | (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3665 | (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) | |
3666 | (const_int 0))) | |
3667 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3668 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] | |
3669 | "reload_completed" | |
3670 | [(set (match_dup 0) | |
3671 | (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) | |
3672 | (set (match_dup 3) | |
3673 | (compare:CC (match_dup 0) | |
3674 | (const_int 0)))] | |
3675 | "") | |
1fd4e8c1 RK |
3676 | |
3677 | ;; Note that we use "sle." instead of "sl." so that we can set | |
3678 | ;; SHIFT_COUNT_TRUNCATED. | |
3679 | ||
ca7f5001 RK |
3680 | (define_expand "ashlsi3" |
3681 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3682 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3683 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3684 | "" | |
3685 | " | |
3686 | { | |
3687 | if (TARGET_POWER) | |
3688 | emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2])); | |
3689 | else | |
25c341fa | 3690 | emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3691 | DONE; |
3692 | }") | |
3693 | ||
3694 | (define_insn "ashlsi3_power" | |
cd2b37d9 RK |
3695 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3696 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
3697 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
3698 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 3699 | "TARGET_POWER" |
1fd4e8c1 RK |
3700 | "@ |
3701 | sle %0,%1,%2 | |
9ebbca7d | 3702 | {sli|slwi} %0,%1,%h2") |
ca7f5001 | 3703 | |
25c341fa | 3704 | (define_insn "ashlsi3_no_power" |
ca7f5001 RK |
3705 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3706 | (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
3707 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 3708 | "! TARGET_POWER" |
9ebbca7d | 3709 | "{sl|slw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
3710 | |
3711 | (define_insn "" | |
9ebbca7d GK |
3712 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3713 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3714 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3715 | (const_int 0))) |
9ebbca7d GK |
3716 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
3717 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 3718 | "TARGET_POWER" |
1fd4e8c1 RK |
3719 | "@ |
3720 | sle. %3,%1,%2 | |
9ebbca7d GK |
3721 | {sli.|slwi.} %3,%1,%h2 |
3722 | # | |
3723 | #" | |
3724 | [(set_attr "type" "delayed_compare") | |
3725 | (set_attr "length" "4,4,8,8")]) | |
3726 | ||
3727 | (define_split | |
3728 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3729 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3730 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3731 | (const_int 0))) | |
3732 | (clobber (match_scratch:SI 3 "")) | |
3733 | (clobber (match_scratch:SI 4 ""))] | |
3734 | "TARGET_POWER && reload_completed" | |
3735 | [(parallel [(set (match_dup 3) | |
3736 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3737 | (clobber (match_dup 4))]) | |
3738 | (set (match_dup 0) | |
3739 | (compare:CC (match_dup 3) | |
3740 | (const_int 0)))] | |
3741 | "") | |
25c341fa | 3742 | |
ca7f5001 | 3743 | (define_insn "" |
9ebbca7d GK |
3744 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3745 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3746 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3747 | (const_int 0))) |
9ebbca7d | 3748 | (clobber (match_scratch:SI 3 "=r,r"))] |
4b8a63d6 | 3749 | "! TARGET_POWER && TARGET_32BIT" |
9ebbca7d GK |
3750 | "@ |
3751 | {sl|slw}%I2. %3,%1,%h2 | |
3752 | #" | |
3753 | [(set_attr "type" "delayed_compare") | |
3754 | (set_attr "length" "4,8")]) | |
3755 | ||
3756 | (define_split | |
3757 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3758 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3759 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3760 | (const_int 0))) | |
3761 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 3762 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3763 | [(set (match_dup 3) |
3764 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3765 | (set (match_dup 0) | |
3766 | (compare:CC (match_dup 3) | |
3767 | (const_int 0)))] | |
3768 | "") | |
1fd4e8c1 RK |
3769 | |
3770 | (define_insn "" | |
9ebbca7d GK |
3771 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
3772 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3773 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 3774 | (const_int 0))) |
9ebbca7d | 3775 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 3776 | (ashift:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 3777 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 3778 | "TARGET_POWER" |
1fd4e8c1 RK |
3779 | "@ |
3780 | sle. %0,%1,%2 | |
9ebbca7d GK |
3781 | {sli.|slwi.} %0,%1,%h2 |
3782 | # | |
3783 | #" | |
3784 | [(set_attr "type" "delayed_compare") | |
3785 | (set_attr "length" "4,4,8,8")]) | |
3786 | ||
3787 | (define_split | |
3788 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3789 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3790 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3791 | (const_int 0))) | |
3792 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3793 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3794 | (clobber (match_scratch:SI 4 ""))] | |
3795 | "TARGET_POWER && reload_completed" | |
3796 | [(parallel [(set (match_dup 0) | |
3797 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3798 | (clobber (match_dup 4))]) | |
3799 | (set (match_dup 3) | |
3800 | (compare:CC (match_dup 0) | |
3801 | (const_int 0)))] | |
3802 | "") | |
25c341fa | 3803 | |
ca7f5001 | 3804 | (define_insn "" |
9ebbca7d GK |
3805 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
3806 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3807 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 3808 | (const_int 0))) |
9ebbca7d | 3809 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 3810 | (ashift:SI (match_dup 1) (match_dup 2)))] |
4b8a63d6 | 3811 | "! TARGET_POWER && TARGET_32BIT" |
9ebbca7d GK |
3812 | "@ |
3813 | {sl|slw}%I2. %0,%1,%h2 | |
3814 | #" | |
3815 | [(set_attr "type" "delayed_compare") | |
3816 | (set_attr "length" "4,8")]) | |
3817 | ||
3818 | (define_split | |
3819 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
3820 | (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3821 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3822 | (const_int 0))) | |
3823 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3824 | (ashift:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 3825 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3826 | [(set (match_dup 0) |
3827 | (ashift:SI (match_dup 1) (match_dup 2))) | |
3828 | (set (match_dup 3) | |
3829 | (compare:CC (match_dup 0) | |
3830 | (const_int 0)))] | |
3831 | "") | |
1fd4e8c1 | 3832 | |
915167f5 | 3833 | (define_insn "rlwinm" |
cd2b37d9 RK |
3834 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
3835 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 3836 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 3837 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 3838 | "includes_lshift_p (operands[2], operands[3])" |
d56d506a | 3839 | "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") |
1fd4e8c1 RK |
3840 | |
3841 | (define_insn "" | |
9ebbca7d | 3842 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3843 | (compare:CC |
9ebbca7d GK |
3844 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3845 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3846 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3847 | (const_int 0))) |
9ebbca7d | 3848 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 3849 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3850 | "@ |
3851 | {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 | |
3852 | #" | |
3853 | [(set_attr "type" "delayed_compare") | |
3854 | (set_attr "length" "4,8")]) | |
3855 | ||
3856 | (define_split | |
3857 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3858 | (compare:CC | |
3859 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3860 | (match_operand:SI 2 "const_int_operand" "")) | |
3861 | (match_operand:SI 3 "mask_operand" "")) | |
3862 | (const_int 0))) | |
3863 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 3864 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3865 | [(set (match_dup 4) |
3866 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) | |
3867 | (match_dup 3))) | |
3868 | (set (match_dup 0) | |
3869 | (compare:CC (match_dup 4) | |
3870 | (const_int 0)))] | |
3871 | "") | |
1fd4e8c1 RK |
3872 | |
3873 | (define_insn "" | |
9ebbca7d | 3874 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 3875 | (compare:CC |
9ebbca7d GK |
3876 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
3877 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 3878 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 3879 | (const_int 0))) |
9ebbca7d | 3880 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 3881 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 3882 | "includes_lshift_p (operands[2], operands[3])" |
9ebbca7d GK |
3883 | "@ |
3884 | {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 | |
3885 | #" | |
3886 | [(set_attr "type" "delayed_compare") | |
3887 | (set_attr "length" "4,8")]) | |
3888 | ||
3889 | (define_split | |
3890 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
3891 | (compare:CC | |
3892 | (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3893 | (match_operand:SI 2 "const_int_operand" "")) | |
3894 | (match_operand:SI 3 "mask_operand" "")) | |
3895 | (const_int 0))) | |
3896 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
3897 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 3898 | "includes_lshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
3899 | [(set (match_dup 0) |
3900 | (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
3901 | (set (match_dup 4) | |
3902 | (compare:CC (match_dup 0) | |
3903 | (const_int 0)))] | |
3904 | "") | |
1fd4e8c1 | 3905 | |
ca7f5001 | 3906 | ;; The AIX assembler mis-handles "sri x,x,0", so write that case as |
5c23c401 | 3907 | ;; "sli x,x,0". |
ca7f5001 RK |
3908 | (define_expand "lshrsi3" |
3909 | [(use (match_operand:SI 0 "gpc_reg_operand" "")) | |
3910 | (use (match_operand:SI 1 "gpc_reg_operand" "")) | |
3911 | (use (match_operand:SI 2 "reg_or_cint_operand" ""))] | |
3912 | "" | |
3913 | " | |
3914 | { | |
3915 | if (TARGET_POWER) | |
3916 | emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2])); | |
3917 | else | |
25c341fa | 3918 | emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
3919 | DONE; |
3920 | }") | |
3921 | ||
3922 | (define_insn "lshrsi3_power" | |
bdf423cb MM |
3923 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") |
3924 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") | |
3925 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i"))) | |
3926 | (clobber (match_scratch:SI 3 "=q,X,X"))] | |
ca7f5001 | 3927 | "TARGET_POWER" |
1fd4e8c1 RK |
3928 | "@ |
3929 | sre %0,%1,%2 | |
bdf423cb | 3930 | mr %0,%1 |
ca7f5001 RK |
3931 | {s%A2i|s%A2wi} %0,%1,%h2") |
3932 | ||
25c341fa | 3933 | (define_insn "lshrsi3_no_power" |
bdf423cb MM |
3934 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
3935 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
3936 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))] | |
25c341fa | 3937 | "! TARGET_POWER" |
bdf423cb MM |
3938 | "@ |
3939 | mr %0,%1 | |
3940 | {sr|srw}%I2 %0,%1,%h2") | |
1fd4e8c1 RK |
3941 | |
3942 | (define_insn "" | |
9ebbca7d GK |
3943 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") |
3944 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
3945 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 3946 | (const_int 0))) |
9ebbca7d GK |
3947 | (clobber (match_scratch:SI 3 "=r,X,r,r,X,r")) |
3948 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] | |
ca7f5001 | 3949 | "TARGET_POWER" |
1fd4e8c1 | 3950 | "@ |
29ae5b89 JL |
3951 | sre. %3,%1,%2 |
3952 | mr. %1,%1 | |
9ebbca7d GK |
3953 | {s%A2i.|s%A2wi.} %3,%1,%h2 |
3954 | # | |
3955 | # | |
3956 | #" | |
3957 | [(set_attr "type" "delayed_compare") | |
3958 | (set_attr "length" "4,4,4,8,8,8")]) | |
3959 | ||
3960 | (define_split | |
3961 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3962 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3963 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3964 | (const_int 0))) | |
3965 | (clobber (match_scratch:SI 3 "")) | |
3966 | (clobber (match_scratch:SI 4 ""))] | |
3967 | "TARGET_POWER && reload_completed" | |
3968 | [(parallel [(set (match_dup 3) | |
3969 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
3970 | (clobber (match_dup 4))]) | |
3971 | (set (match_dup 0) | |
3972 | (compare:CC (match_dup 3) | |
3973 | (const_int 0)))] | |
3974 | "") | |
ca7f5001 RK |
3975 | |
3976 | (define_insn "" | |
9ebbca7d GK |
3977 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
3978 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
3979 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
ca7f5001 | 3980 | (const_int 0))) |
9ebbca7d | 3981 | (clobber (match_scratch:SI 3 "=X,r,X,r"))] |
4b8a63d6 | 3982 | "! TARGET_POWER && TARGET_32BIT" |
bdf423cb MM |
3983 | "@ |
3984 | mr. %1,%1 | |
9ebbca7d GK |
3985 | {sr|srw}%I2. %3,%1,%h2 |
3986 | # | |
3987 | #" | |
3988 | [(set_attr "type" "delayed_compare") | |
3989 | (set_attr "length" "4,4,8,8")]) | |
1fd4e8c1 | 3990 | |
9ebbca7d GK |
3991 | (define_split |
3992 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
3993 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
3994 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
3995 | (const_int 0))) | |
3996 | (clobber (match_scratch:SI 3 ""))] | |
4b8a63d6 | 3997 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
3998 | [(set (match_dup 3) |
3999 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4000 | (set (match_dup 0) | |
4001 | (compare:CC (match_dup 3) | |
4002 | (const_int 0)))] | |
4003 | "") | |
4004 | ||
4005 | (define_insn "" | |
4006 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") | |
4007 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") | |
4008 | (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i")) | |
1fd4e8c1 | 4009 | (const_int 0))) |
9ebbca7d | 4010 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
1fd4e8c1 | 4011 | (lshiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4012 | (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))] |
ca7f5001 | 4013 | "TARGET_POWER" |
1fd4e8c1 | 4014 | "@ |
29ae5b89 JL |
4015 | sre. %0,%1,%2 |
4016 | mr. %0,%1 | |
9ebbca7d GK |
4017 | {s%A2i.|s%A2wi.} %0,%1,%h2 |
4018 | # | |
4019 | # | |
4020 | #" | |
4021 | [(set_attr "type" "delayed_compare") | |
4022 | (set_attr "length" "4,4,4,8,8,8")]) | |
4023 | ||
4024 | (define_split | |
4025 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4026 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4027 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4028 | (const_int 0))) | |
4029 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4030 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4031 | (clobber (match_scratch:SI 4 ""))] | |
4032 | "TARGET_POWER && reload_completed" | |
4033 | [(parallel [(set (match_dup 0) | |
4034 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4035 | (clobber (match_dup 4))]) | |
4036 | (set (match_dup 3) | |
4037 | (compare:CC (match_dup 0) | |
4038 | (const_int 0)))] | |
4039 | "") | |
ca7f5001 RK |
4040 | |
4041 | (define_insn "" | |
9ebbca7d GK |
4042 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4043 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4044 | (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri")) | |
815cdc52 | 4045 | (const_int 0))) |
9ebbca7d | 4046 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
29ae5b89 | 4047 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] |
4b8a63d6 | 4048 | "! TARGET_POWER && TARGET_32BIT" |
29ae5b89 JL |
4049 | "@ |
4050 | mr. %0,%1 | |
9ebbca7d GK |
4051 | {sr|srw}%I2. %0,%1,%h2 |
4052 | # | |
4053 | #" | |
4054 | [(set_attr "type" "delayed_compare") | |
4055 | (set_attr "length" "4,4,8,8")]) | |
4056 | ||
4057 | (define_split | |
4058 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4059 | (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4060 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4061 | (const_int 0))) | |
4062 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4063 | (lshiftrt:SI (match_dup 1) (match_dup 2)))] | |
4b8a63d6 | 4064 | "! TARGET_POWER && TARGET_32BIT && reload_completed" |
9ebbca7d GK |
4065 | [(set (match_dup 0) |
4066 | (lshiftrt:SI (match_dup 1) (match_dup 2))) | |
4067 | (set (match_dup 3) | |
4068 | (compare:CC (match_dup 0) | |
4069 | (const_int 0)))] | |
4070 | "") | |
1fd4e8c1 RK |
4071 | |
4072 | (define_insn "" | |
cd2b37d9 RK |
4073 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4074 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4075 | (match_operand:SI 2 "const_int_operand" "i")) |
ce71f754 | 4076 | (match_operand:SI 3 "mask_operand" "n")))] |
1fd4e8c1 | 4077 | "includes_rshift_p (operands[2], operands[3])" |
ca7f5001 | 4078 | "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") |
1fd4e8c1 RK |
4079 | |
4080 | (define_insn "" | |
9ebbca7d | 4081 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4082 | (compare:CC |
9ebbca7d GK |
4083 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4084 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 4085 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 4086 | (const_int 0))) |
9ebbca7d | 4087 | (clobber (match_scratch:SI 4 "=r,r"))] |
ce71f754 | 4088 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4089 | "@ |
4090 | {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 | |
4091 | #" | |
4092 | [(set_attr "type" "delayed_compare") | |
4093 | (set_attr "length" "4,8")]) | |
4094 | ||
4095 | (define_split | |
4096 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4097 | (compare:CC | |
4098 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4099 | (match_operand:SI 2 "const_int_operand" "")) | |
4100 | (match_operand:SI 3 "mask_operand" "")) | |
4101 | (const_int 0))) | |
4102 | (clobber (match_scratch:SI 4 ""))] | |
ce71f754 | 4103 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
4104 | [(set (match_dup 4) |
4105 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) | |
4106 | (match_dup 3))) | |
4107 | (set (match_dup 0) | |
4108 | (compare:CC (match_dup 4) | |
4109 | (const_int 0)))] | |
4110 | "") | |
1fd4e8c1 RK |
4111 | |
4112 | (define_insn "" | |
9ebbca7d | 4113 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 4114 | (compare:CC |
9ebbca7d GK |
4115 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4116 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
ce71f754 | 4117 | (match_operand:SI 3 "mask_operand" "n,n")) |
1fd4e8c1 | 4118 | (const_int 0))) |
9ebbca7d | 4119 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4120 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
ce71f754 | 4121 | "includes_rshift_p (operands[2], operands[3])" |
9ebbca7d GK |
4122 | "@ |
4123 | {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 | |
4124 | #" | |
4125 | [(set_attr "type" "delayed_compare") | |
4126 | (set_attr "length" "4,8")]) | |
4127 | ||
4128 | (define_split | |
4129 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
4130 | (compare:CC | |
4131 | (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4132 | (match_operand:SI 2 "const_int_operand" "")) | |
4133 | (match_operand:SI 3 "mask_operand" "")) | |
4134 | (const_int 0))) | |
4135 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4136 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ce71f754 | 4137 | "includes_rshift_p (operands[2], operands[3]) && reload_completed" |
9ebbca7d GK |
4138 | [(set (match_dup 0) |
4139 | (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
4140 | (set (match_dup 4) | |
4141 | (compare:CC (match_dup 0) | |
4142 | (const_int 0)))] | |
4143 | "") | |
1fd4e8c1 RK |
4144 | |
4145 | (define_insn "" | |
cd2b37d9 | 4146 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4147 | (zero_extend:SI |
4148 | (subreg:QI | |
cd2b37d9 | 4149 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4150 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4151 | "includes_rshift_p (operands[2], GEN_INT (255))" |
ca7f5001 | 4152 | "{rlinm|rlwinm} %0,%1,%s2,0xff") |
1fd4e8c1 RK |
4153 | |
4154 | (define_insn "" | |
9ebbca7d | 4155 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4156 | (compare:CC |
4157 | (zero_extend:SI | |
4158 | (subreg:QI | |
9ebbca7d GK |
4159 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4160 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4161 | (const_int 0))) |
9ebbca7d | 4162 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4163 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4164 | "@ |
4165 | {rlinm.|rlwinm.} %3,%1,%s2,0xff | |
4166 | #" | |
4167 | [(set_attr "type" "delayed_compare") | |
4168 | (set_attr "length" "4,8")]) | |
4169 | ||
4170 | (define_split | |
4171 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4172 | (compare:CC | |
4173 | (zero_extend:SI | |
4174 | (subreg:QI | |
4175 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4176 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4177 | (const_int 0))) | |
4178 | (clobber (match_scratch:SI 3 ""))] | |
4179 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4180 | [(set (match_dup 3) | |
4181 | (zero_extend:SI (subreg:QI | |
4182 | (lshiftrt:SI (match_dup 1) | |
4183 | (match_dup 2)) 0))) | |
4184 | (set (match_dup 0) | |
4185 | (compare:CC (match_dup 3) | |
4186 | (const_int 0)))] | |
4187 | "") | |
1fd4e8c1 RK |
4188 | |
4189 | (define_insn "" | |
9ebbca7d | 4190 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4191 | (compare:CC |
4192 | (zero_extend:SI | |
4193 | (subreg:QI | |
9ebbca7d GK |
4194 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4195 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4196 | (const_int 0))) |
9ebbca7d | 4197 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4198 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4199 | "includes_rshift_p (operands[2], GEN_INT (255))" |
9ebbca7d GK |
4200 | "@ |
4201 | {rlinm.|rlwinm.} %0,%1,%s2,0xff | |
4202 | #" | |
4203 | [(set_attr "type" "delayed_compare") | |
4204 | (set_attr "length" "4,8")]) | |
4205 | ||
4206 | (define_split | |
4207 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4208 | (compare:CC | |
4209 | (zero_extend:SI | |
4210 | (subreg:QI | |
4211 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4212 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4213 | (const_int 0))) | |
4214 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4215 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4216 | "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" | |
4217 | [(set (match_dup 0) | |
4218 | (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4219 | (set (match_dup 3) | |
4220 | (compare:CC (match_dup 0) | |
4221 | (const_int 0)))] | |
4222 | "") | |
1fd4e8c1 RK |
4223 | |
4224 | (define_insn "" | |
cd2b37d9 | 4225 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
4226 | (zero_extend:SI |
4227 | (subreg:HI | |
cd2b37d9 | 4228 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 4229 | (match_operand:SI 2 "const_int_operand" "i")) 0)))] |
89e9f3a8 | 4230 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
ca7f5001 | 4231 | "{rlinm|rlwinm} %0,%1,%s2,0xffff") |
1fd4e8c1 RK |
4232 | |
4233 | (define_insn "" | |
9ebbca7d | 4234 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4235 | (compare:CC |
4236 | (zero_extend:SI | |
4237 | (subreg:HI | |
9ebbca7d GK |
4238 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4239 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4240 | (const_int 0))) |
9ebbca7d | 4241 | (clobber (match_scratch:SI 3 "=r,r"))] |
89e9f3a8 | 4242 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4243 | "@ |
4244 | {rlinm.|rlwinm.} %3,%1,%s2,0xffff | |
4245 | #" | |
4246 | [(set_attr "type" "delayed_compare") | |
4247 | (set_attr "length" "4,8")]) | |
4248 | ||
4249 | (define_split | |
4250 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4251 | (compare:CC | |
4252 | (zero_extend:SI | |
4253 | (subreg:HI | |
4254 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4255 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4256 | (const_int 0))) | |
4257 | (clobber (match_scratch:SI 3 ""))] | |
4258 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4259 | [(set (match_dup 3) | |
4260 | (zero_extend:SI (subreg:HI | |
4261 | (lshiftrt:SI (match_dup 1) | |
4262 | (match_dup 2)) 0))) | |
4263 | (set (match_dup 0) | |
4264 | (compare:CC (match_dup 3) | |
4265 | (const_int 0)))] | |
4266 | "") | |
1fd4e8c1 RK |
4267 | |
4268 | (define_insn "" | |
9ebbca7d | 4269 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
4270 | (compare:CC |
4271 | (zero_extend:SI | |
4272 | (subreg:HI | |
9ebbca7d GK |
4273 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
4274 | (match_operand:SI 2 "const_int_operand" "i,i")) 0)) | |
1fd4e8c1 | 4275 | (const_int 0))) |
9ebbca7d | 4276 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 4277 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] |
89e9f3a8 | 4278 | "includes_rshift_p (operands[2], GEN_INT (65535))" |
9ebbca7d GK |
4279 | "@ |
4280 | {rlinm.|rlwinm.} %0,%1,%s2,0xffff | |
4281 | #" | |
4282 | [(set_attr "type" "delayed_compare") | |
4283 | (set_attr "length" "4,8")]) | |
4284 | ||
4285 | (define_split | |
4286 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4287 | (compare:CC | |
4288 | (zero_extend:SI | |
4289 | (subreg:HI | |
4290 | (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4291 | (match_operand:SI 2 "const_int_operand" "")) 0)) | |
4292 | (const_int 0))) | |
4293 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4294 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] | |
4295 | "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" | |
4296 | [(set (match_dup 0) | |
4297 | (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) | |
4298 | (set (match_dup 3) | |
4299 | (compare:CC (match_dup 0) | |
4300 | (const_int 0)))] | |
4301 | "") | |
1fd4e8c1 RK |
4302 | |
4303 | (define_insn "" | |
cd2b37d9 | 4304 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4305 | (const_int 1) |
cd2b37d9 RK |
4306 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4307 | (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4308 | (const_int 31)))] |
ca7f5001 | 4309 | "TARGET_POWER" |
1fd4e8c1 RK |
4310 | "rrib %0,%1,%2") |
4311 | ||
4312 | (define_insn "" | |
cd2b37d9 | 4313 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4314 | (const_int 1) |
cd2b37d9 RK |
4315 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4316 | (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 | 4317 | (const_int 31)))] |
ca7f5001 | 4318 | "TARGET_POWER" |
1fd4e8c1 RK |
4319 | "rrib %0,%1,%2") |
4320 | ||
4321 | (define_insn "" | |
cd2b37d9 | 4322 | [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") |
1fd4e8c1 | 4323 | (const_int 1) |
cd2b37d9 RK |
4324 | (match_operand:SI 1 "gpc_reg_operand" "r")) |
4325 | (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
4326 | (const_int 1) |
4327 | (const_int 0)))] | |
ca7f5001 | 4328 | "TARGET_POWER" |
1fd4e8c1 RK |
4329 | "rrib %0,%1,%2") |
4330 | ||
ca7f5001 RK |
4331 | (define_expand "ashrsi3" |
4332 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4333 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4334 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
4335 | "" | |
4336 | " | |
4337 | { | |
4338 | if (TARGET_POWER) | |
4339 | emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2])); | |
4340 | else | |
25c341fa | 4341 | emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2])); |
ca7f5001 RK |
4342 | DONE; |
4343 | }") | |
4344 | ||
4345 | (define_insn "ashrsi3_power" | |
cd2b37d9 RK |
4346 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
4347 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
4348 | (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) |
4349 | (clobber (match_scratch:SI 3 "=q,X"))] | |
ca7f5001 | 4350 | "TARGET_POWER" |
1fd4e8c1 RK |
4351 | "@ |
4352 | srea %0,%1,%2 | |
ca7f5001 RK |
4353 | {srai|srawi} %0,%1,%h2") |
4354 | ||
25c341fa | 4355 | (define_insn "ashrsi3_no_power" |
ca7f5001 RK |
4356 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
4357 | (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
4358 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
25c341fa | 4359 | "! TARGET_POWER" |
d904e9ed | 4360 | "{sra|sraw}%I2 %0,%1,%h2") |
1fd4e8c1 RK |
4361 | |
4362 | (define_insn "" | |
9ebbca7d GK |
4363 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
4364 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4365 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4366 | (const_int 0))) |
9ebbca7d GK |
4367 | (clobber (match_scratch:SI 3 "=r,r,r,r")) |
4368 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] | |
ca7f5001 | 4369 | "TARGET_POWER" |
1fd4e8c1 RK |
4370 | "@ |
4371 | srea. %3,%1,%2 | |
9ebbca7d GK |
4372 | {srai.|srawi.} %3,%1,%h2 |
4373 | # | |
4374 | #" | |
4375 | [(set_attr "type" "delayed_compare") | |
4376 | (set_attr "length" "4,4,8,8")]) | |
4377 | ||
4378 | (define_split | |
4379 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4380 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4381 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4382 | (const_int 0))) | |
4383 | (clobber (match_scratch:SI 3 "")) | |
4384 | (clobber (match_scratch:SI 4 ""))] | |
4385 | "TARGET_POWER && reload_completed" | |
4386 | [(parallel [(set (match_dup 3) | |
4387 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4388 | (clobber (match_dup 4))]) | |
4389 | (set (match_dup 0) | |
4390 | (compare:CC (match_dup 3) | |
4391 | (const_int 0)))] | |
4392 | "") | |
ca7f5001 RK |
4393 | |
4394 | (define_insn "" | |
9ebbca7d GK |
4395 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
4396 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4397 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4398 | (const_int 0))) |
9ebbca7d | 4399 | (clobber (match_scratch:SI 3 "=r,r"))] |
25c341fa | 4400 | "! TARGET_POWER" |
9ebbca7d GK |
4401 | "@ |
4402 | {sra|sraw}%I2. %3,%1,%h2 | |
4403 | #" | |
4404 | [(set_attr "type" "delayed_compare") | |
4405 | (set_attr "length" "4,8")]) | |
4406 | ||
4407 | (define_split | |
4408 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
4409 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4410 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4411 | (const_int 0))) | |
4412 | (clobber (match_scratch:SI 3 ""))] | |
4413 | "! TARGET_POWER && reload_completed" | |
4414 | [(set (match_dup 3) | |
4415 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4416 | (set (match_dup 0) | |
4417 | (compare:CC (match_dup 3) | |
4418 | (const_int 0)))] | |
4419 | "") | |
1fd4e8c1 RK |
4420 | |
4421 | (define_insn "" | |
9ebbca7d GK |
4422 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
4423 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") | |
4424 | (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) | |
1fd4e8c1 | 4425 | (const_int 0))) |
9ebbca7d | 4426 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 4427 | (ashiftrt:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 4428 | (clobber (match_scratch:SI 4 "=q,X,q,X"))] |
ca7f5001 | 4429 | "TARGET_POWER" |
1fd4e8c1 RK |
4430 | "@ |
4431 | srea. %0,%1,%2 | |
9ebbca7d GK |
4432 | {srai.|srawi.} %0,%1,%h2 |
4433 | # | |
4434 | #" | |
4435 | [(set_attr "type" "delayed_compare") | |
4436 | (set_attr "length" "4,4,8,8")]) | |
4437 | ||
4438 | (define_split | |
4439 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4440 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4441 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4442 | (const_int 0))) | |
4443 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4444 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4445 | (clobber (match_scratch:SI 4 ""))] | |
4446 | "TARGET_POWER && reload_completed" | |
4447 | [(parallel [(set (match_dup 0) | |
4448 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4449 | (clobber (match_dup 4))]) | |
4450 | (set (match_dup 3) | |
4451 | (compare:CC (match_dup 0) | |
4452 | (const_int 0)))] | |
4453 | "") | |
1fd4e8c1 | 4454 | |
ca7f5001 | 4455 | (define_insn "" |
9ebbca7d GK |
4456 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
4457 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
4458 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
ca7f5001 | 4459 | (const_int 0))) |
9ebbca7d | 4460 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
ca7f5001 | 4461 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
25c341fa | 4462 | "! TARGET_POWER" |
9ebbca7d GK |
4463 | "@ |
4464 | {sra|sraw}%I2. %0,%1,%h2 | |
4465 | #" | |
4466 | [(set_attr "type" "delayed_compare") | |
4467 | (set_attr "length" "4,8")]) | |
1fd4e8c1 | 4468 | \f |
9ebbca7d GK |
4469 | (define_split |
4470 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
4471 | (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
4472 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
4473 | (const_int 0))) | |
4474 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
4475 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] | |
4476 | "! TARGET_POWER && reload_completed" | |
4477 | [(set (match_dup 0) | |
4478 | (ashiftrt:SI (match_dup 1) (match_dup 2))) | |
4479 | (set (match_dup 3) | |
4480 | (compare:CC (match_dup 0) | |
4481 | (const_int 0)))] | |
4482 | "") | |
4483 | ||
1fd4e8c1 RK |
4484 | ;; Floating-point insns, excluding normal data motion. |
4485 | ;; | |
ca7f5001 RK |
4486 | ;; PowerPC has a full set of single-precision floating point instructions. |
4487 | ;; | |
4488 | ;; For the POWER architecture, we pretend that we have both SFmode and | |
4489 | ;; DFmode insns, while, in fact, all fp insns are actually done in double. | |
4490 | ;; The only conversions we will do will be when storing to memory. In that | |
4491 | ;; case, we will use the "frsp" instruction before storing. | |
1fd4e8c1 RK |
4492 | ;; |
4493 | ;; Note that when we store into a single-precision memory location, we need to | |
4494 | ;; use the frsp insn first. If the register being stored isn't dead, we | |
4495 | ;; need a scratch register for the frsp. But this is difficult when the store | |
4496 | ;; is done by reload. It is not incorrect to do the frsp on the register in | |
4497 | ;; this case, we just lose precision that we would have otherwise gotten but | |
4498 | ;; is not guaranteed. Perhaps this should be tightened up at some point. | |
4499 | ||
99176a91 AH |
4500 | (define_expand "extendsfdf2" |
4501 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
97c54d9a | 4502 | (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))] |
99176a91 AH |
4503 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" |
4504 | "") | |
4505 | ||
4506 | (define_insn_and_split "*extendsfdf2_fpr" | |
97c54d9a DE |
4507 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f,f") |
4508 | (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))] | |
a3170dc6 | 4509 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
11ac38b2 DE |
4510 | "@ |
4511 | # | |
97c54d9a DE |
4512 | fmr %0,%1 |
4513 | lfs%U1%X1 %0,%1" | |
d7b1468b | 4514 | "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])" |
11ac38b2 | 4515 | [(const_int 0)] |
5c30aff8 | 4516 | { |
11ac38b2 DE |
4517 | emit_note (NOTE_INSN_DELETED); |
4518 | DONE; | |
4519 | } | |
97c54d9a | 4520 | [(set_attr "type" "fp,fp,fpload")]) |
1fd4e8c1 | 4521 | |
7a2f7870 AH |
4522 | (define_expand "truncdfsf2" |
4523 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4524 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))] | |
4525 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4526 | "") | |
4527 | ||
99176a91 | 4528 | (define_insn "*truncdfsf2_fpr" |
cd2b37d9 RK |
4529 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4530 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4531 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
dcac138d | 4532 | "frsp %0,%1" |
1fd4e8c1 RK |
4533 | [(set_attr "type" "fp")]) |
4534 | ||
455350f4 RK |
4535 | (define_insn "aux_truncdfsf2" |
4536 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
615158e2 | 4537 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))] |
a3170dc6 | 4538 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
455350f4 RK |
4539 | "frsp %0,%1" |
4540 | [(set_attr "type" "fp")]) | |
4541 | ||
a3170dc6 AH |
4542 | (define_expand "negsf2" |
4543 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4544 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4545 | "TARGET_HARD_FLOAT" | |
4546 | "") | |
4547 | ||
4548 | (define_insn "*negsf2" | |
cd2b37d9 RK |
4549 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4550 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4551 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4552 | "fneg %0,%1" |
4553 | [(set_attr "type" "fp")]) | |
4554 | ||
a3170dc6 AH |
4555 | (define_expand "abssf2" |
4556 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4557 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
4558 | "TARGET_HARD_FLOAT" | |
4559 | "") | |
4560 | ||
4561 | (define_insn "*abssf2" | |
cd2b37d9 RK |
4562 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4563 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4564 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4565 | "fabs %0,%1" |
4566 | [(set_attr "type" "fp")]) | |
4567 | ||
4568 | (define_insn "" | |
cd2b37d9 RK |
4569 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4570 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4571 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4572 | "fnabs %0,%1" |
4573 | [(set_attr "type" "fp")]) | |
4574 | ||
ca7f5001 RK |
4575 | (define_expand "addsf3" |
4576 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4577 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4578 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4579 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4580 | "") |
4581 | ||
4582 | (define_insn "" | |
cd2b37d9 RK |
4583 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4584 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4585 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4586 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4587 | "fadds %0,%1,%2" |
ca7f5001 RK |
4588 | [(set_attr "type" "fp")]) |
4589 | ||
4590 | (define_insn "" | |
4591 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4592 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4593 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4594 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4595 | "{fa|fadd} %0,%1,%2" |
ca7f5001 RK |
4596 | [(set_attr "type" "fp")]) |
4597 | ||
4598 | (define_expand "subsf3" | |
4599 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4600 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4601 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4602 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4603 | "") |
4604 | ||
4605 | (define_insn "" | |
4606 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4607 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4608 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4609 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4610 | "fsubs %0,%1,%2" |
1fd4e8c1 RK |
4611 | [(set_attr "type" "fp")]) |
4612 | ||
ca7f5001 | 4613 | (define_insn "" |
cd2b37d9 RK |
4614 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4615 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4616 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4617 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4618 | "{fs|fsub} %0,%1,%2" |
ca7f5001 RK |
4619 | [(set_attr "type" "fp")]) |
4620 | ||
4621 | (define_expand "mulsf3" | |
4622 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4623 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4624 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4625 | "TARGET_HARD_FLOAT" |
ca7f5001 RK |
4626 | "") |
4627 | ||
4628 | (define_insn "" | |
4629 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4630 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4631 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4632 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4633 | "fmuls %0,%1,%2" |
1fd4e8c1 RK |
4634 | [(set_attr "type" "fp")]) |
4635 | ||
ca7f5001 | 4636 | (define_insn "" |
cd2b37d9 RK |
4637 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4638 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4639 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4640 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4641 | "{fm|fmul} %0,%1,%2" |
0780f386 | 4642 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4643 | |
ef765ea9 DE |
4644 | (define_insn "fres" |
4645 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4646 | (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))] | |
4647 | "TARGET_PPC_GFXOPT && flag_finite_math_only" | |
4648 | "fres %0,%1" | |
4649 | [(set_attr "type" "fp")]) | |
4650 | ||
ca7f5001 RK |
4651 | (define_expand "divsf3" |
4652 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4653 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "") | |
4654 | (match_operand:SF 2 "gpc_reg_operand" "")))] | |
d14a6d05 | 4655 | "TARGET_HARD_FLOAT" |
ef765ea9 DE |
4656 | { |
4657 | if (swdiv && !optimize_size && TARGET_PPC_GFXOPT | |
4658 | && flag_finite_math_only && !flag_trapping_math) | |
4659 | { | |
4660 | rs6000_emit_swdivsf (operands[0], operands[1], operands[2]); | |
4661 | DONE; | |
4662 | } | |
4663 | }) | |
ca7f5001 RK |
4664 | |
4665 | (define_insn "" | |
cd2b37d9 RK |
4666 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4667 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4668 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4669 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4670 | "fdivs %0,%1,%2" |
ca7f5001 RK |
4671 | [(set_attr "type" "sdiv")]) |
4672 | ||
4673 | (define_insn "" | |
4674 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4675 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") | |
4676 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4677 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" |
b26c8351 | 4678 | "{fd|fdiv} %0,%1,%2" |
0780f386 | 4679 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
4680 | |
4681 | (define_insn "" | |
cd2b37d9 RK |
4682 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4683 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4684 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4685 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4686 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4687 | "fmadds %0,%1,%2,%3" |
ca7f5001 RK |
4688 | [(set_attr "type" "fp")]) |
4689 | ||
4690 | (define_insn "" | |
4691 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4692 | (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4693 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4694 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4695 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4696 | "{fma|fmadd} %0,%1,%2,%3" |
cf27b467 | 4697 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4698 | |
4699 | (define_insn "" | |
cd2b37d9 RK |
4700 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4701 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4702 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4703 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4704 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4705 | "fmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4706 | [(set_attr "type" "fp")]) |
4707 | ||
4708 | (define_insn "" | |
4709 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4710 | (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4711 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4712 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4713 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4714 | "{fms|fmsub} %0,%1,%2,%3" |
cf27b467 | 4715 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
4716 | |
4717 | (define_insn "" | |
cd2b37d9 RK |
4718 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4719 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4720 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4721 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4722 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4723 | && HONOR_SIGNED_ZEROS (SFmode)" | |
4724 | "fnmadds %0,%1,%2,%3" | |
4725 | [(set_attr "type" "fp")]) | |
4726 | ||
4727 | (define_insn "" | |
4728 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4729 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
4730 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4731 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
4732 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4733 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 4734 | "fnmadds %0,%1,%2,%3" |
ca7f5001 RK |
4735 | [(set_attr "type" "fp")]) |
4736 | ||
4737 | (define_insn "" | |
4738 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4739 | (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4740 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4741 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4742 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4743 | "{fnma|fnmadd} %0,%1,%2,%3" |
cf27b467 | 4744 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4745 | |
16823694 GK |
4746 | (define_insn "" |
4747 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4748 | (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) | |
4749 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4750 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
4751 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4752 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
4753 | "{fnma|fnmadd} %0,%1,%2,%3" | |
4754 | [(set_attr "type" "dmul")]) | |
4755 | ||
1fd4e8c1 | 4756 | (define_insn "" |
cd2b37d9 RK |
4757 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4758 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4759 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4760 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
4761 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
4762 | && HONOR_SIGNED_ZEROS (SFmode)" | |
4763 | "fnmsubs %0,%1,%2,%3" | |
4764 | [(set_attr "type" "fp")]) | |
4765 | ||
4766 | (define_insn "" | |
4767 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4768 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
4769 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4770 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
4771 | "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4772 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
b26c8351 | 4773 | "fnmsubs %0,%1,%2,%3" |
ca7f5001 RK |
4774 | [(set_attr "type" "fp")]) |
4775 | ||
4776 | (define_insn "" | |
4777 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4778 | (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4779 | (match_operand:SF 2 "gpc_reg_operand" "f")) | |
4780 | (match_operand:SF 3 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4781 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
b26c8351 | 4782 | "{fnms|fnmsub} %0,%1,%2,%3" |
cf27b467 | 4783 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 4784 | |
16823694 GK |
4785 | (define_insn "" |
4786 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4787 | (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") | |
4788 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") | |
4789 | (match_operand:SF 2 "gpc_reg_operand" "f"))))] | |
4790 | "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
4791 | && ! HONOR_SIGNED_ZEROS (SFmode)" | |
4792 | "{fnms|fnmsub} %0,%1,%2,%3" | |
4793 | [(set_attr "type" "fp")]) | |
4794 | ||
ca7f5001 RK |
4795 | (define_expand "sqrtsf2" |
4796 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
4797 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
a3170dc6 | 4798 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4799 | "") |
4800 | ||
4801 | (define_insn "" | |
4802 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4803 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4804 | "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4805 | "fsqrts %0,%1" |
4806 | [(set_attr "type" "ssqrt")]) | |
4807 | ||
4808 | (define_insn "" | |
4809 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
4810 | (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4811 | "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
4812 | "fsqrt %0,%1" |
4813 | [(set_attr "type" "dsqrt")]) | |
4814 | ||
0530bc70 AP |
4815 | (define_expand "copysignsf3" |
4816 | [(set (match_dup 3) | |
4817 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" ""))) | |
4818 | (set (match_dup 4) | |
4819 | (neg:SF (abs:SF (match_dup 1)))) | |
4820 | (set (match_operand:SF 0 "gpc_reg_operand" "") | |
4821 | (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "") | |
4822 | (match_dup 5)) | |
4823 | (match_dup 3) | |
4824 | (match_dup 4)))] | |
4825 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS | |
4826 | && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)" | |
4827 | { | |
4828 | operands[3] = gen_reg_rtx (SFmode); | |
4829 | operands[4] = gen_reg_rtx (SFmode); | |
4830 | operands[5] = CONST0_RTX (SFmode); | |
4831 | }) | |
4832 | ||
4833 | (define_expand "copysigndf3" | |
4834 | [(set (match_dup 3) | |
4835 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" ""))) | |
4836 | (set (match_dup 4) | |
4837 | (neg:DF (abs:DF (match_dup 1)))) | |
4838 | (set (match_operand:DF 0 "gpc_reg_operand" "") | |
4839 | (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "") | |
4840 | (match_dup 5)) | |
4841 | (match_dup 3) | |
4842 | (match_dup 4)))] | |
4843 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS | |
4844 | && !HONOR_NANS (DFmode) && !HONOR_SIGNED_ZEROS (DFmode)" | |
4845 | { | |
4846 | operands[3] = gen_reg_rtx (DFmode); | |
4847 | operands[4] = gen_reg_rtx (DFmode); | |
4848 | operands[5] = CONST0_RTX (DFmode); | |
4849 | }) | |
4850 | ||
94d7001a RK |
4851 | ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a |
4852 | ;; fsel instruction and some auxiliary computations. Then we just have a | |
4853 | ;; single DEFINE_INSN for fsel and the define_splits to make them if made by | |
8e871c05 | 4854 | ;; combine. |
7ae4d8d4 | 4855 | (define_expand "smaxsf3" |
8e871c05 | 4856 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
50a0b056 GK |
4857 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") |
4858 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
4859 | (match_dup 1) |
4860 | (match_dup 2)))] | |
89e73849 | 4861 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 4862 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
2f607b94 | 4863 | |
7ae4d8d4 | 4864 | (define_expand "sminsf3" |
50a0b056 GK |
4865 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
4866 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "") | |
4867 | (match_operand:SF 2 "gpc_reg_operand" "")) | |
4868 | (match_dup 2) | |
4869 | (match_dup 1)))] | |
89e73849 | 4870 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 4871 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
2f607b94 | 4872 | |
8e871c05 RK |
4873 | (define_split |
4874 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
4875 | (match_operator:SF 3 "min_max_operator" |
4876 | [(match_operand:SF 1 "gpc_reg_operand" "") | |
4877 | (match_operand:SF 2 "gpc_reg_operand" "")]))] | |
89e73849 | 4878 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 GK |
4879 | [(const_int 0)] |
4880 | " | |
6ae08853 | 4881 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), |
50a0b056 GK |
4882 | operands[1], operands[2]); |
4883 | DONE; | |
4884 | }") | |
2f607b94 | 4885 | |
a3170dc6 AH |
4886 | (define_expand "movsicc" |
4887 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
4888 | (if_then_else:SI (match_operand 1 "comparison_operator" "") | |
4889 | (match_operand:SI 2 "gpc_reg_operand" "") | |
4890 | (match_operand:SI 3 "gpc_reg_operand" "")))] | |
4891 | "TARGET_ISEL" | |
4892 | " | |
4893 | { | |
4894 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) | |
4895 | DONE; | |
4896 | else | |
4897 | FAIL; | |
4898 | }") | |
4899 | ||
4900 | ;; We use the BASE_REGS for the isel input operands because, if rA is | |
4901 | ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB | |
4902 | ;; because we may switch the operands and rB may end up being rA. | |
4903 | ;; | |
4904 | ;; We need 2 patterns: an unsigned and a signed pattern. We could | |
4905 | ;; leave out the mode in operand 4 and use one pattern, but reload can | |
4906 | ;; change the mode underneath our feet and then gets confused trying | |
4907 | ;; to reload the value. | |
4908 | (define_insn "isel_signed" | |
4909 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4910 | (if_then_else:SI | |
4911 | (match_operator 1 "comparison_operator" | |
4912 | [(match_operand:CC 4 "cc_reg_operand" "y") | |
4913 | (const_int 0)]) | |
4914 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
4915 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
4916 | "TARGET_ISEL" | |
4917 | "* | |
4918 | { return output_isel (operands); }" | |
4919 | [(set_attr "length" "4")]) | |
4920 | ||
4921 | (define_insn "isel_unsigned" | |
4922 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
4923 | (if_then_else:SI | |
4924 | (match_operator 1 "comparison_operator" | |
4925 | [(match_operand:CCUNS 4 "cc_reg_operand" "y") | |
4926 | (const_int 0)]) | |
4927 | (match_operand:SI 2 "gpc_reg_operand" "b") | |
4928 | (match_operand:SI 3 "gpc_reg_operand" "b")))] | |
4929 | "TARGET_ISEL" | |
4930 | "* | |
4931 | { return output_isel (operands); }" | |
4932 | [(set_attr "length" "4")]) | |
4933 | ||
94d7001a | 4934 | (define_expand "movsfcc" |
0ad91047 | 4935 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
94d7001a | 4936 | (if_then_else:SF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
4937 | (match_operand:SF 2 "gpc_reg_operand" "") |
4938 | (match_operand:SF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 4939 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4940 | " |
4941 | { | |
50a0b056 GK |
4942 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
4943 | DONE; | |
94d7001a | 4944 | else |
50a0b056 | 4945 | FAIL; |
94d7001a | 4946 | }") |
d56d506a | 4947 | |
50a0b056 | 4948 | (define_insn "*fselsfsf4" |
8e871c05 RK |
4949 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4950 | (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 4951 | (match_operand:SF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
4952 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4953 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4954 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
4955 | "fsel %0,%1,%2,%3" |
4956 | [(set_attr "type" "fp")]) | |
2f607b94 | 4957 | |
50a0b056 | 4958 | (define_insn "*fseldfsf4" |
94d7001a RK |
4959 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
4960 | (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
d365ba42 | 4961 | (match_operand:DF 4 "zero_fp_constant" "F")) |
94d7001a RK |
4962 | (match_operand:SF 2 "gpc_reg_operand" "f") |
4963 | (match_operand:SF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4964 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
4965 | "fsel %0,%1,%2,%3" |
4966 | [(set_attr "type" "fp")]) | |
d56d506a | 4967 | |
7a2f7870 AH |
4968 | (define_expand "negdf2" |
4969 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4970 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))] | |
4971 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4972 | "") | |
4973 | ||
99176a91 | 4974 | (define_insn "*negdf2_fpr" |
cd2b37d9 RK |
4975 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4976 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4977 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4978 | "fneg %0,%1" |
4979 | [(set_attr "type" "fp")]) | |
4980 | ||
7a2f7870 AH |
4981 | (define_expand "absdf2" |
4982 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4983 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))] | |
4984 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
4985 | "") | |
4986 | ||
99176a91 | 4987 | (define_insn "*absdf2_fpr" |
cd2b37d9 RK |
4988 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4989 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 4990 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4991 | "fabs %0,%1" |
4992 | [(set_attr "type" "fp")]) | |
4993 | ||
99176a91 | 4994 | (define_insn "*nabsdf2_fpr" |
cd2b37d9 RK |
4995 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
4996 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] | |
a3170dc6 | 4997 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
4998 | "fnabs %0,%1" |
4999 | [(set_attr "type" "fp")]) | |
5000 | ||
7a2f7870 AH |
5001 | (define_expand "adddf3" |
5002 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5003 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
5004 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
5005 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
5006 | "") | |
5007 | ||
99176a91 | 5008 | (define_insn "*adddf3_fpr" |
cd2b37d9 RK |
5009 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5010 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5011 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5012 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 5013 | "{fa|fadd} %0,%1,%2" |
1fd4e8c1 RK |
5014 | [(set_attr "type" "fp")]) |
5015 | ||
7a2f7870 AH |
5016 | (define_expand "subdf3" |
5017 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5018 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
5019 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
5020 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
5021 | "") | |
5022 | ||
99176a91 | 5023 | (define_insn "*subdf3_fpr" |
cd2b37d9 RK |
5024 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5025 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
5026 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5027 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 5028 | "{fs|fsub} %0,%1,%2" |
1fd4e8c1 RK |
5029 | [(set_attr "type" "fp")]) |
5030 | ||
7a2f7870 AH |
5031 | (define_expand "muldf3" |
5032 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5033 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
5034 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
5035 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
5036 | "") | |
5037 | ||
99176a91 | 5038 | (define_insn "*muldf3_fpr" |
cd2b37d9 RK |
5039 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5040 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5041 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5042 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 5043 | "{fm|fmul} %0,%1,%2" |
cfb557c4 | 5044 | [(set_attr "type" "dmul")]) |
1fd4e8c1 | 5045 | |
ef765ea9 DE |
5046 | (define_insn "fred" |
5047 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5048 | (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))] | |
5049 | "TARGET_POPCNTB && flag_finite_math_only" | |
5050 | "fre %0,%1" | |
5051 | [(set_attr "type" "fp")]) | |
5052 | ||
7a2f7870 AH |
5053 | (define_expand "divdf3" |
5054 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5055 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "") | |
5056 | (match_operand:DF 2 "gpc_reg_operand" "")))] | |
5057 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
ef765ea9 DE |
5058 | { |
5059 | if (swdiv && !optimize_size && TARGET_POPCNTB | |
5060 | && flag_finite_math_only && !flag_trapping_math) | |
5061 | { | |
5062 | rs6000_emit_swdivdf (operands[0], operands[1], operands[2]); | |
5063 | DONE; | |
5064 | } | |
5065 | }) | |
7a2f7870 | 5066 | |
99176a91 | 5067 | (define_insn "*divdf3_fpr" |
cd2b37d9 RK |
5068 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5069 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") | |
5070 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5071 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 | 5072 | "{fd|fdiv} %0,%1,%2" |
cfb557c4 | 5073 | [(set_attr "type" "ddiv")]) |
1fd4e8c1 RK |
5074 | |
5075 | (define_insn "" | |
cd2b37d9 RK |
5076 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5077 | (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5078 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5079 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5080 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 5081 | "{fma|fmadd} %0,%1,%2,%3" |
cfb557c4 | 5082 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5083 | |
5084 | (define_insn "" | |
cd2b37d9 RK |
5085 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5086 | (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5087 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5088 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5089 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" |
ca7f5001 | 5090 | "{fms|fmsub} %0,%1,%2,%3" |
cfb557c4 | 5091 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5092 | |
5093 | (define_insn "" | |
cd2b37d9 RK |
5094 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5095 | (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5096 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5097 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
5098 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
5099 | && HONOR_SIGNED_ZEROS (DFmode)" | |
5100 | "{fnma|fnmadd} %0,%1,%2,%3" | |
5101 | [(set_attr "type" "dmul")]) | |
5102 | ||
5103 | (define_insn "" | |
5104 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5105 | (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")) | |
5106 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5107 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
5108 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD | |
5109 | && ! HONOR_SIGNED_ZEROS (DFmode)" | |
ca7f5001 | 5110 | "{fnma|fnmadd} %0,%1,%2,%3" |
cfb557c4 | 5111 | [(set_attr "type" "dmul")]) |
1fd4e8c1 RK |
5112 | |
5113 | (define_insn "" | |
cd2b37d9 RK |
5114 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5115 | (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5116 | (match_operand:DF 2 "gpc_reg_operand" "f")) | |
5117 | (match_operand:DF 3 "gpc_reg_operand" "f"))))] | |
16823694 GK |
5118 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
5119 | && HONOR_SIGNED_ZEROS (DFmode)" | |
5120 | "{fnms|fnmsub} %0,%1,%2,%3" | |
5121 | [(set_attr "type" "dmul")]) | |
5122 | ||
5123 | (define_insn "" | |
5124 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5125 | (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f") | |
5126 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") | |
5127 | (match_operand:DF 2 "gpc_reg_operand" "f"))))] | |
6ae08853 | 5128 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD |
16823694 | 5129 | && ! HONOR_SIGNED_ZEROS (DFmode)" |
ca7f5001 | 5130 | "{fnms|fnmsub} %0,%1,%2,%3" |
cfb557c4 | 5131 | [(set_attr "type" "dmul")]) |
ca7f5001 RK |
5132 | |
5133 | (define_insn "sqrtdf2" | |
5134 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5135 | (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5136 | "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" |
ca7f5001 RK |
5137 | "fsqrt %0,%1" |
5138 | [(set_attr "type" "dsqrt")]) | |
b77dfefc | 5139 | |
50a0b056 | 5140 | ;; The conditional move instructions allow us to perform max and min |
6ae08853 | 5141 | ;; operations even when |
b77dfefc | 5142 | |
7ae4d8d4 | 5143 | (define_expand "smaxdf3" |
8e871c05 | 5144 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
50a0b056 GK |
5145 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") |
5146 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
8e871c05 RK |
5147 | (match_dup 1) |
5148 | (match_dup 2)))] | |
89e73849 | 5149 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 5150 | "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") |
b77dfefc | 5151 | |
7ae4d8d4 | 5152 | (define_expand "smindf3" |
50a0b056 GK |
5153 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5154 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "") | |
5155 | (match_operand:DF 2 "gpc_reg_operand" "")) | |
5156 | (match_dup 2) | |
5157 | (match_dup 1)))] | |
89e73849 | 5158 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 | 5159 | "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") |
b77dfefc | 5160 | |
8e871c05 RK |
5161 | (define_split |
5162 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
50a0b056 GK |
5163 | (match_operator:DF 3 "min_max_operator" |
5164 | [(match_operand:DF 1 "gpc_reg_operand" "") | |
5165 | (match_operand:DF 2 "gpc_reg_operand" "")]))] | |
89e73849 | 5166 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && !flag_trapping_math" |
50a0b056 GK |
5167 | [(const_int 0)] |
5168 | " | |
6ae08853 | 5169 | { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), |
50a0b056 GK |
5170 | operands[1], operands[2]); |
5171 | DONE; | |
5172 | }") | |
b77dfefc | 5173 | |
94d7001a | 5174 | (define_expand "movdfcc" |
0ad91047 | 5175 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
94d7001a | 5176 | (if_then_else:DF (match_operand 1 "comparison_operator" "") |
0ad91047 DE |
5177 | (match_operand:DF 2 "gpc_reg_operand" "") |
5178 | (match_operand:DF 3 "gpc_reg_operand" "")))] | |
a3170dc6 | 5179 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
94d7001a RK |
5180 | " |
5181 | { | |
50a0b056 GK |
5182 | if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) |
5183 | DONE; | |
94d7001a | 5184 | else |
50a0b056 | 5185 | FAIL; |
94d7001a | 5186 | }") |
d56d506a | 5187 | |
50a0b056 | 5188 | (define_insn "*fseldfdf4" |
8e871c05 RK |
5189 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5190 | (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5191 | (match_operand:DF 4 "zero_fp_constant" "F")) |
8e871c05 RK |
5192 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5193 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
a3170dc6 | 5194 | "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" |
8e871c05 RK |
5195 | "fsel %0,%1,%2,%3" |
5196 | [(set_attr "type" "fp")]) | |
d56d506a | 5197 | |
50a0b056 | 5198 | (define_insn "*fselsfdf4" |
94d7001a RK |
5199 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") |
5200 | (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") | |
50a0b056 | 5201 | (match_operand:SF 4 "zero_fp_constant" "F")) |
94d7001a RK |
5202 | (match_operand:DF 2 "gpc_reg_operand" "f") |
5203 | (match_operand:DF 3 "gpc_reg_operand" "f")))] | |
5204 | "TARGET_PPC_GFXOPT" | |
5205 | "fsel %0,%1,%2,%3" | |
5206 | [(set_attr "type" "fp")]) | |
1fd4e8c1 | 5207 | \f |
d095928f AH |
5208 | ;; Conversions to and from floating-point. |
5209 | ||
5210 | (define_expand "fixuns_truncsfsi2" | |
5211 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5212 | (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] | |
5213 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5214 | "") | |
5215 | ||
5216 | (define_expand "fix_truncsfsi2" | |
5217 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5218 | (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] | |
5219 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5220 | "") | |
5221 | ||
9ebbca7d GK |
5222 | ; For each of these conversions, there is a define_expand, a define_insn |
5223 | ; with a '#' template, and a define_split (with C code). The idea is | |
5224 | ; to allow constant folding with the template of the define_insn, | |
5225 | ; then to have the insns split later (between sched1 and final). | |
5226 | ||
1fd4e8c1 | 5227 | (define_expand "floatsidf2" |
802a0058 MM |
5228 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") |
5229 | (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5230 | (use (match_dup 2)) | |
5231 | (use (match_dup 3)) | |
208c89ce | 5232 | (clobber (match_dup 4)) |
a7df97e6 | 5233 | (clobber (match_dup 5)) |
9ebbca7d | 5234 | (clobber (match_dup 6))])] |
a3170dc6 | 5235 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
5236 | " |
5237 | { | |
99176a91 AH |
5238 | if (TARGET_E500_DOUBLE) |
5239 | { | |
5240 | emit_insn (gen_spe_floatsidf2 (operands[0], operands[1])); | |
5241 | DONE; | |
5242 | } | |
05d49501 AM |
5243 | if (TARGET_POWERPC64) |
5244 | { | |
5245 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5246 | rtx t1 = gen_reg_rtx (DImode); | |
5247 | rtx t2 = gen_reg_rtx (DImode); | |
5248 | emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2)); | |
5249 | DONE; | |
5250 | } | |
5251 | ||
802a0058 | 5252 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5253 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode)); |
9ebbca7d GK |
5254 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5255 | operands[5] = gen_reg_rtx (DFmode); | |
5256 | operands[6] = gen_reg_rtx (SImode); | |
1fd4e8c1 RK |
5257 | }") |
5258 | ||
230215f5 | 5259 | (define_insn_and_split "*floatsidf2_internal" |
802a0058 MM |
5260 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") |
5261 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5262 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5263 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5264 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 DJ |
5265 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f")) |
5266 | (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))] | |
a3170dc6 | 5267 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5268 | "#" |
230215f5 GK |
5269 | "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))" |
5270 | [(pc)] | |
208c89ce MM |
5271 | " |
5272 | { | |
9ebbca7d | 5273 | rtx lowword, highword; |
230215f5 GK |
5274 | gcc_assert (MEM_P (operands[4])); |
5275 | highword = adjust_address (operands[4], SImode, 0); | |
5276 | lowword = adjust_address (operands[4], SImode, 4); | |
9ebbca7d GK |
5277 | if (! WORDS_BIG_ENDIAN) |
5278 | { | |
5279 | rtx tmp; | |
5280 | tmp = highword; highword = lowword; lowword = tmp; | |
5281 | } | |
5282 | ||
6ae08853 | 5283 | emit_insn (gen_xorsi3 (operands[6], operands[1], |
9ebbca7d | 5284 | GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); |
230215f5 GK |
5285 | emit_move_insn (lowword, operands[6]); |
5286 | emit_move_insn (highword, operands[2]); | |
9ebbca7d GK |
5287 | emit_move_insn (operands[5], operands[4]); |
5288 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5289 | DONE; | |
230215f5 GK |
5290 | }" |
5291 | [(set_attr "length" "24")]) | |
802a0058 | 5292 | |
a3170dc6 AH |
5293 | (define_expand "floatunssisf2" |
5294 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5295 | (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5296 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5297 | "") | |
5298 | ||
802a0058 MM |
5299 | (define_expand "floatunssidf2" |
5300 | [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
5301 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) | |
5302 | (use (match_dup 2)) | |
5303 | (use (match_dup 3)) | |
a7df97e6 | 5304 | (clobber (match_dup 4)) |
9ebbca7d | 5305 | (clobber (match_dup 5))])] |
99176a91 | 5306 | "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" |
1fd4e8c1 RK |
5307 | " |
5308 | { | |
99176a91 AH |
5309 | if (TARGET_E500_DOUBLE) |
5310 | { | |
5311 | emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1])); | |
5312 | DONE; | |
5313 | } | |
05d49501 AM |
5314 | if (TARGET_POWERPC64) |
5315 | { | |
5316 | rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
5317 | rtx t1 = gen_reg_rtx (DImode); | |
5318 | rtx t2 = gen_reg_rtx (DImode); | |
5319 | emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem, | |
5320 | t1, t2)); | |
5321 | DONE; | |
5322 | } | |
5323 | ||
802a0058 | 5324 | operands[2] = force_reg (SImode, GEN_INT (0x43300000)); |
5692c7bc | 5325 | operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode)); |
9ebbca7d GK |
5326 | operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); |
5327 | operands[5] = gen_reg_rtx (DFmode); | |
1fd4e8c1 RK |
5328 | }") |
5329 | ||
230215f5 | 5330 | (define_insn_and_split "*floatunssidf2_internal" |
802a0058 MM |
5331 | [(set (match_operand:DF 0 "gpc_reg_operand" "=&f") |
5332 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5333 | (use (match_operand:SI 2 "gpc_reg_operand" "r")) | |
5334 | (use (match_operand:DF 3 "gpc_reg_operand" "f")) | |
9ebbca7d | 5335 | (clobber (match_operand:DF 4 "memory_operand" "=o")) |
6f9c81f5 | 5336 | (clobber (match_operand:DF 5 "gpc_reg_operand" "=&f"))] |
a3170dc6 | 5337 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5338 | "#" |
230215f5 GK |
5339 | "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[4]))" |
5340 | [(pc)] | |
9ebbca7d | 5341 | " |
802a0058 | 5342 | { |
9ebbca7d | 5343 | rtx lowword, highword; |
230215f5 GK |
5344 | gcc_assert (MEM_P (operands[4])); |
5345 | highword = adjust_address (operands[4], SImode, 0); | |
5346 | lowword = adjust_address (operands[4], SImode, 4); | |
9ebbca7d | 5347 | if (! WORDS_BIG_ENDIAN) |
f6968f59 | 5348 | { |
9ebbca7d GK |
5349 | rtx tmp; |
5350 | tmp = highword; highword = lowword; lowword = tmp; | |
f6968f59 | 5351 | } |
802a0058 | 5352 | |
230215f5 GK |
5353 | emit_move_insn (lowword, operands[1]); |
5354 | emit_move_insn (highword, operands[2]); | |
9ebbca7d GK |
5355 | emit_move_insn (operands[5], operands[4]); |
5356 | emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); | |
5357 | DONE; | |
230215f5 GK |
5358 | }" |
5359 | [(set_attr "length" "20")]) | |
1fd4e8c1 | 5360 | |
1fd4e8c1 | 5361 | (define_expand "fix_truncdfsi2" |
045a8eb3 | 5362 | [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "") |
802a0058 MM |
5363 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) |
5364 | (clobber (match_dup 2)) | |
9ebbca7d | 5365 | (clobber (match_dup 3))])] |
99176a91 AH |
5366 | "(TARGET_POWER2 || TARGET_POWERPC) |
5367 | && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)" | |
1fd4e8c1 RK |
5368 | " |
5369 | { | |
99176a91 AH |
5370 | if (TARGET_E500_DOUBLE) |
5371 | { | |
5372 | emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1])); | |
5373 | DONE; | |
5374 | } | |
802a0058 | 5375 | operands[2] = gen_reg_rtx (DImode); |
da4c340c GK |
5376 | if (TARGET_PPC_GFXOPT) |
5377 | { | |
5378 | rtx orig_dest = operands[0]; | |
045a8eb3 | 5379 | if (! memory_operand (orig_dest, GET_MODE (orig_dest))) |
da4c340c GK |
5380 | operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0); |
5381 | emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1], | |
5382 | operands[2])); | |
5383 | if (operands[0] != orig_dest) | |
5384 | emit_move_insn (orig_dest, operands[0]); | |
5385 | DONE; | |
5386 | } | |
9ebbca7d | 5387 | operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); |
1fd4e8c1 RK |
5388 | }") |
5389 | ||
da4c340c | 5390 | (define_insn_and_split "*fix_truncdfsi2_internal" |
802a0058 MM |
5391 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5392 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
e3485bbc | 5393 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) |
9ebbca7d | 5394 | (clobber (match_operand:DI 3 "memory_operand" "=o"))] |
a3170dc6 | 5395 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
802a0058 | 5396 | "#" |
230215f5 | 5397 | "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[3]))" |
da4c340c | 5398 | [(pc)] |
9ebbca7d | 5399 | " |
802a0058 | 5400 | { |
9ebbca7d | 5401 | rtx lowword; |
230215f5 GK |
5402 | gcc_assert (MEM_P (operands[3])); |
5403 | lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0); | |
802a0058 | 5404 | |
9ebbca7d GK |
5405 | emit_insn (gen_fctiwz (operands[2], operands[1])); |
5406 | emit_move_insn (operands[3], operands[2]); | |
230215f5 | 5407 | emit_move_insn (operands[0], lowword); |
9ebbca7d | 5408 | DONE; |
da4c340c GK |
5409 | }" |
5410 | [(set_attr "length" "16")]) | |
5411 | ||
5412 | (define_insn_and_split "fix_truncdfsi2_internal_gfxopt" | |
5413 | [(set (match_operand:SI 0 "memory_operand" "=Z") | |
5414 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) | |
5415 | (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))] | |
5416 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS | |
5417 | && TARGET_PPC_GFXOPT" | |
5418 | "#" | |
5419 | "&& 1" | |
5420 | [(pc)] | |
5421 | " | |
5422 | { | |
5423 | emit_insn (gen_fctiwz (operands[2], operands[1])); | |
5424 | emit_insn (gen_stfiwx (operands[0], operands[2])); | |
5425 | DONE; | |
5426 | }" | |
5427 | [(set_attr "length" "16")]) | |
802a0058 | 5428 | |
615158e2 | 5429 | ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ)) |
9ebbca7d GK |
5430 | ; rather than (set (subreg:SI (reg)) (fix:SI ...)) |
5431 | ; because the first makes it clear that operand 0 is not live | |
5432 | ; before the instruction. | |
5433 | (define_insn "fctiwz" | |
da4c340c | 5434 | [(set (match_operand:DI 0 "gpc_reg_operand" "=f") |
615158e2 JJ |
5435 | (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] |
5436 | UNSPEC_FCTIWZ))] | |
a3170dc6 | 5437 | "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" |
a260abc9 DE |
5438 | "{fcirz|fctiwz} %0,%1" |
5439 | [(set_attr "type" "fp")]) | |
5440 | ||
da4c340c GK |
5441 | ; An UNSPEC is used so we don't have to support SImode in FP registers. |
5442 | (define_insn "stfiwx" | |
5443 | [(set (match_operand:SI 0 "memory_operand" "=Z") | |
5444 | (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "f")] | |
5445 | UNSPEC_STFIWX))] | |
5446 | "TARGET_PPC_GFXOPT" | |
5447 | "stfiwx %1,%y0" | |
5448 | [(set_attr "type" "fpstore")]) | |
5449 | ||
a3170dc6 AH |
5450 | (define_expand "floatsisf2" |
5451 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5452 | (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] | |
5453 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
5454 | "") | |
5455 | ||
a473029f RK |
5456 | (define_insn "floatdidf2" |
5457 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
61c07d3c | 5458 | (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))] |
a3170dc6 | 5459 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5460 | "fcfid %0,%1" |
5461 | [(set_attr "type" "fp")]) | |
5462 | ||
05d49501 AM |
5463 | (define_insn_and_split "floatsidf_ppc64" |
5464 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5465 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5466 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5467 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5468 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5469 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 | 5470 | "#" |
ecb62ae7 | 5471 | "&& 1" |
05d49501 AM |
5472 | [(set (match_dup 3) (sign_extend:DI (match_dup 1))) |
5473 | (set (match_dup 2) (match_dup 3)) | |
5474 | (set (match_dup 4) (match_dup 2)) | |
5475 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5476 | "") | |
5477 | ||
5478 | (define_insn_and_split "floatunssidf_ppc64" | |
5479 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
5480 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
5481 | (clobber (match_operand:DI 2 "memory_operand" "=o")) | |
5482 | (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) | |
5483 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] | |
a3170dc6 | 5484 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
05d49501 | 5485 | "#" |
ecb62ae7 | 5486 | "&& 1" |
05d49501 AM |
5487 | [(set (match_dup 3) (zero_extend:DI (match_dup 1))) |
5488 | (set (match_dup 2) (match_dup 3)) | |
5489 | (set (match_dup 4) (match_dup 2)) | |
5490 | (set (match_dup 0) (float:DF (match_dup 4)))] | |
5491 | "") | |
5492 | ||
a473029f | 5493 | (define_insn "fix_truncdfdi2" |
61c07d3c | 5494 | [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") |
a473029f | 5495 | (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] |
a3170dc6 | 5496 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
a473029f RK |
5497 | "fctidz %0,%1" |
5498 | [(set_attr "type" "fp")]) | |
ea112fc4 | 5499 | |
678b7733 AM |
5500 | (define_expand "floatdisf2" |
5501 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
5502 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] | |
994cf173 | 5503 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
678b7733 AM |
5504 | " |
5505 | { | |
994cf173 | 5506 | rtx val = operands[1]; |
678b7733 AM |
5507 | if (!flag_unsafe_math_optimizations) |
5508 | { | |
5509 | rtx label = gen_label_rtx (); | |
994cf173 AM |
5510 | val = gen_reg_rtx (DImode); |
5511 | emit_insn (gen_floatdisf2_internal2 (val, operands[1], label)); | |
678b7733 AM |
5512 | emit_label (label); |
5513 | } | |
994cf173 | 5514 | emit_insn (gen_floatdisf2_internal1 (operands[0], val)); |
678b7733 AM |
5515 | DONE; |
5516 | }") | |
5517 | ||
5518 | ;; This is not IEEE compliant if rounding mode is "round to nearest". | |
5519 | ;; If the DI->DF conversion is inexact, then it's possible to suffer | |
5520 | ;; from double rounding. | |
5521 | (define_insn_and_split "floatdisf2_internal1" | |
ea112fc4 | 5522 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") |
61c07d3c | 5523 | (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f"))) |
ea112fc4 | 5524 | (clobber (match_scratch:DF 2 "=f"))] |
678b7733 | 5525 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" |
ea112fc4 DE |
5526 | "#" |
5527 | "&& reload_completed" | |
5528 | [(set (match_dup 2) | |
5529 | (float:DF (match_dup 1))) | |
5530 | (set (match_dup 0) | |
5531 | (float_truncate:SF (match_dup 2)))] | |
5532 | "") | |
678b7733 AM |
5533 | |
5534 | ;; Twiddles bits to avoid double rounding. | |
b6d08ca1 | 5535 | ;; Bits that might be truncated when converting to DFmode are replaced |
678b7733 AM |
5536 | ;; by a bit that won't be lost at that stage, but is below the SFmode |
5537 | ;; rounding position. | |
5538 | (define_expand "floatdisf2_internal2" | |
994cf173 AM |
5539 | [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "") |
5540 | (const_int 53))) | |
5541 | (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1) | |
5542 | (const_int 2047))) | |
5543 | (clobber (scratch:CC))]) | |
5544 | (set (match_dup 3) (plus:DI (match_dup 3) | |
5545 | (const_int 1))) | |
5546 | (set (match_dup 0) (plus:DI (match_dup 0) | |
5547 | (const_int 2047))) | |
5548 | (set (match_dup 4) (compare:CCUNS (match_dup 3) | |
5549 | (const_int 3))) | |
5550 | (set (match_dup 0) (ior:DI (match_dup 0) | |
5551 | (match_dup 1))) | |
5552 | (parallel [(set (match_dup 0) (and:DI (match_dup 0) | |
5553 | (const_int -2048))) | |
5554 | (clobber (scratch:CC))]) | |
5555 | (set (pc) (if_then_else (geu (match_dup 4) (const_int 0)) | |
5556 | (label_ref (match_operand:DI 2 "" "")) | |
678b7733 | 5557 | (pc))) |
994cf173 AM |
5558 | (set (match_dup 0) (match_dup 1))] |
5559 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" | |
678b7733 AM |
5560 | " |
5561 | { | |
678b7733 | 5562 | operands[3] = gen_reg_rtx (DImode); |
994cf173 | 5563 | operands[4] = gen_reg_rtx (CCUNSmode); |
678b7733 | 5564 | }") |
1fd4e8c1 RK |
5565 | \f |
5566 | ;; Define the DImode operations that can be done in a small number | |
a6ec530c RK |
5567 | ;; of instructions. The & constraints are to prevent the register |
5568 | ;; allocator from allocating registers that overlap with the inputs | |
5569 | ;; (for example, having an input in 7,8 and an output in 6,7). We | |
38e01259 | 5570 | ;; also allow for the output being the same as one of the inputs. |
a6ec530c | 5571 | |
266eb58a | 5572 | (define_insn "*adddi3_noppc64" |
a6ec530c RK |
5573 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") |
5574 | (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") | |
5575 | (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] | |
e1f83b4d | 5576 | "! TARGET_POWERPC64" |
0f645302 MM |
5577 | "* |
5578 | { | |
5579 | if (WORDS_BIG_ENDIAN) | |
5580 | return (GET_CODE (operands[2])) != CONST_INT | |
5581 | ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\" | |
5582 | : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\"; | |
5583 | else | |
5584 | return (GET_CODE (operands[2])) != CONST_INT | |
5585 | ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\" | |
5586 | : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\"; | |
5587 | }" | |
943c15ed DE |
5588 | [(set_attr "type" "two") |
5589 | (set_attr "length" "8")]) | |
1fd4e8c1 | 5590 | |
266eb58a | 5591 | (define_insn "*subdi3_noppc64" |
e7e5df70 RK |
5592 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") |
5593 | (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") | |
5594 | (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] | |
266eb58a | 5595 | "! TARGET_POWERPC64" |
5502823b RK |
5596 | "* |
5597 | { | |
0f645302 MM |
5598 | if (WORDS_BIG_ENDIAN) |
5599 | return (GET_CODE (operands[1]) != CONST_INT) | |
5600 | ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\" | |
5601 | : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\"; | |
5602 | else | |
5603 | return (GET_CODE (operands[1]) != CONST_INT) | |
5604 | ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\" | |
5605 | : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\"; | |
5502823b | 5606 | }" |
943c15ed DE |
5607 | [(set_attr "type" "two") |
5608 | (set_attr "length" "8")]) | |
ca7f5001 | 5609 | |
266eb58a | 5610 | (define_insn "*negdi2_noppc64" |
a6ec530c RK |
5611 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
5612 | (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] | |
51b8fc2c | 5613 | "! TARGET_POWERPC64" |
5502823b RK |
5614 | "* |
5615 | { | |
5616 | return (WORDS_BIG_ENDIAN) | |
5617 | ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\" | |
5618 | : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\"; | |
5619 | }" | |
943c15ed DE |
5620 | [(set_attr "type" "two") |
5621 | (set_attr "length" "8")]) | |
ca7f5001 | 5622 | |
8ffd9c51 RK |
5623 | (define_expand "mulsidi3" |
5624 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5625 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5626 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
a2f270cc | 5627 | "! TARGET_POWERPC64" |
8ffd9c51 RK |
5628 | " |
5629 | { | |
5630 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5631 | { | |
39403d82 DE |
5632 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5633 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5634 | emit_insn (gen_mull_call ()); |
cf27b467 | 5635 | if (WORDS_BIG_ENDIAN) |
39403d82 | 5636 | emit_move_insn (operands[0], gen_rtx_REG (DImode, 3)); |
cf27b467 MM |
5637 | else |
5638 | { | |
5639 | emit_move_insn (operand_subword (operands[0], 0, 0, DImode), | |
39403d82 | 5640 | gen_rtx_REG (SImode, 3)); |
cf27b467 | 5641 | emit_move_insn (operand_subword (operands[0], 1, 0, DImode), |
39403d82 | 5642 | gen_rtx_REG (SImode, 4)); |
cf27b467 | 5643 | } |
8ffd9c51 RK |
5644 | DONE; |
5645 | } | |
5646 | else if (TARGET_POWER) | |
5647 | { | |
5648 | emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2])); | |
5649 | DONE; | |
5650 | } | |
5651 | }") | |
deb9225a | 5652 | |
8ffd9c51 | 5653 | (define_insn "mulsidi3_mq" |
cd2b37d9 | 5654 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
8ffd9c51 | 5655 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
cd2b37d9 | 5656 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) |
1fd4e8c1 | 5657 | (clobber (match_scratch:SI 3 "=q"))] |
ca7f5001 | 5658 | "TARGET_POWER" |
b19003d8 | 5659 | "mul %0,%1,%2\;mfmq %L0" |
8ffd9c51 RK |
5660 | [(set_attr "type" "imul") |
5661 | (set_attr "length" "8")]) | |
deb9225a | 5662 | |
f192bf8b | 5663 | (define_insn "*mulsidi3_no_mq" |
425c176f | 5664 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
8ffd9c51 RK |
5665 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) |
5666 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5667 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
5502823b RK |
5668 | "* |
5669 | { | |
5670 | return (WORDS_BIG_ENDIAN) | |
5671 | ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" | |
5672 | : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; | |
5673 | }" | |
8ffd9c51 RK |
5674 | [(set_attr "type" "imul") |
5675 | (set_attr "length" "8")]) | |
deb9225a | 5676 | |
ebedb4dd MM |
5677 | (define_split |
5678 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5679 | (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5680 | (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5681 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5682 | [(set (match_dup 3) |
5683 | (truncate:SI | |
5684 | (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) | |
5685 | (sign_extend:DI (match_dup 2))) | |
5686 | (const_int 32)))) | |
5687 | (set (match_dup 4) | |
5688 | (mult:SI (match_dup 1) | |
5689 | (match_dup 2)))] | |
5690 | " | |
5691 | { | |
5692 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5693 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5694 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5695 | }") | |
5696 | ||
f192bf8b DE |
5697 | (define_expand "umulsidi3" |
5698 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5699 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5700 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
5701 | "TARGET_POWERPC && ! TARGET_POWERPC64" | |
5702 | " | |
5703 | { | |
5704 | if (TARGET_POWER) | |
5705 | { | |
5706 | emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2])); | |
5707 | DONE; | |
5708 | } | |
5709 | }") | |
5710 | ||
5711 | (define_insn "umulsidi3_mq" | |
5712 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") | |
5713 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5714 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
5715 | (clobber (match_scratch:SI 3 "=q"))] | |
5716 | "TARGET_POWERPC && TARGET_POWER" | |
5717 | "* | |
5718 | { | |
5719 | return (WORDS_BIG_ENDIAN) | |
5720 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5721 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5722 | }" | |
5723 | [(set_attr "type" "imul") | |
5724 | (set_attr "length" "8")]) | |
5725 | ||
5726 | (define_insn "*umulsidi3_no_mq" | |
8106dc08 MM |
5727 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
5728 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5729 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] | |
f192bf8b | 5730 | "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64" |
8106dc08 MM |
5731 | "* |
5732 | { | |
5733 | return (WORDS_BIG_ENDIAN) | |
5734 | ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" | |
5735 | : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; | |
5736 | }" | |
5737 | [(set_attr "type" "imul") | |
5738 | (set_attr "length" "8")]) | |
5739 | ||
ebedb4dd MM |
5740 | (define_split |
5741 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
5742 | (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) | |
5743 | (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] | |
cf27b467 | 5744 | "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed" |
ebedb4dd MM |
5745 | [(set (match_dup 3) |
5746 | (truncate:SI | |
5747 | (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) | |
5748 | (zero_extend:DI (match_dup 2))) | |
5749 | (const_int 32)))) | |
5750 | (set (match_dup 4) | |
5751 | (mult:SI (match_dup 1) | |
5752 | (match_dup 2)))] | |
5753 | " | |
5754 | { | |
5755 | int endian = (WORDS_BIG_ENDIAN == 0); | |
5756 | operands[3] = operand_subword (operands[0], endian, 0, DImode); | |
5757 | operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); | |
5758 | }") | |
5759 | ||
8ffd9c51 RK |
5760 | (define_expand "smulsi3_highpart" |
5761 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5762 | (truncate:SI | |
5763 | (lshiftrt:DI (mult:DI (sign_extend:DI | |
5764 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5765 | (sign_extend:DI | |
5766 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5767 | (const_int 32))))] | |
5768 | "" | |
5769 | " | |
5770 | { | |
5771 | if (! TARGET_POWER && ! TARGET_POWERPC) | |
5772 | { | |
39403d82 DE |
5773 | emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]); |
5774 | emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]); | |
fada905b | 5775 | emit_insn (gen_mulh_call ()); |
39403d82 | 5776 | emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); |
8ffd9c51 RK |
5777 | DONE; |
5778 | } | |
5779 | else if (TARGET_POWER) | |
5780 | { | |
5781 | emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5782 | DONE; | |
5783 | } | |
5784 | }") | |
deb9225a | 5785 | |
8ffd9c51 RK |
5786 | (define_insn "smulsi3_highpart_mq" |
5787 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5788 | (truncate:SI | |
fada905b MM |
5789 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5790 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5791 | (sign_extend:DI | |
5792 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 RK |
5793 | (const_int 32)))) |
5794 | (clobber (match_scratch:SI 3 "=q"))] | |
5795 | "TARGET_POWER" | |
5796 | "mul %0,%1,%2" | |
5797 | [(set_attr "type" "imul")]) | |
deb9225a | 5798 | |
f192bf8b | 5799 | (define_insn "*smulsi3_highpart_no_mq" |
8ffd9c51 RK |
5800 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5801 | (truncate:SI | |
fada905b MM |
5802 | (lshiftrt:DI (mult:DI (sign_extend:DI |
5803 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5804 | (sign_extend:DI | |
5805 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
8ffd9c51 | 5806 | (const_int 32))))] |
f192bf8b | 5807 | "TARGET_POWERPC && ! TARGET_POWER" |
8ffd9c51 RK |
5808 | "mulhw %0,%1,%2" |
5809 | [(set_attr "type" "imul")]) | |
deb9225a | 5810 | |
f192bf8b DE |
5811 | (define_expand "umulsi3_highpart" |
5812 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
5813 | (truncate:SI | |
5814 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5815 | (match_operand:SI 1 "gpc_reg_operand" "")) | |
5816 | (zero_extend:DI | |
5817 | (match_operand:SI 2 "gpc_reg_operand" ""))) | |
5818 | (const_int 32))))] | |
5819 | "TARGET_POWERPC" | |
5820 | " | |
5821 | { | |
5822 | if (TARGET_POWER) | |
5823 | { | |
5824 | emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2])); | |
5825 | DONE; | |
5826 | } | |
5827 | }") | |
5828 | ||
5829 | (define_insn "umulsi3_highpart_mq" | |
5830 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
5831 | (truncate:SI | |
5832 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5833 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5834 | (zero_extend:DI | |
5835 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5836 | (const_int 32)))) | |
5837 | (clobber (match_scratch:SI 3 "=q"))] | |
5838 | "TARGET_POWERPC && TARGET_POWER" | |
5839 | "mulhwu %0,%1,%2" | |
5840 | [(set_attr "type" "imul")]) | |
5841 | ||
5842 | (define_insn "*umulsi3_highpart_no_mq" | |
266eb58a DE |
5843 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
5844 | (truncate:SI | |
5845 | (lshiftrt:DI (mult:DI (zero_extend:DI | |
5846 | (match_operand:SI 1 "gpc_reg_operand" "%r")) | |
5847 | (zero_extend:DI | |
5848 | (match_operand:SI 2 "gpc_reg_operand" "r"))) | |
5849 | (const_int 32))))] | |
f192bf8b | 5850 | "TARGET_POWERPC && ! TARGET_POWER" |
266eb58a DE |
5851 | "mulhwu %0,%1,%2" |
5852 | [(set_attr "type" "imul")]) | |
5853 | ||
5854 | ;; If operands 0 and 2 are in the same register, we have a problem. But | |
5855 | ;; operands 0 and 1 (the usual case) can be in the same register. That's | |
5856 | ;; why we have the strange constraints below. | |
5857 | (define_insn "ashldi3_power" | |
5858 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") | |
5859 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") | |
5860 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5861 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5862 | "TARGET_POWER" | |
5863 | "@ | |
5864 | {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0} | |
5865 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5866 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 | |
5867 | sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2" | |
5868 | [(set_attr "length" "8")]) | |
5869 | ||
5870 | (define_insn "lshrdi3_power" | |
47ad8c61 | 5871 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") |
266eb58a DE |
5872 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") |
5873 | (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) | |
5874 | (clobber (match_scratch:SI 3 "=X,q,q,q"))] | |
5875 | "TARGET_POWER" | |
5876 | "@ | |
47ad8c61 | 5877 | {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0} |
266eb58a DE |
5878 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 |
5879 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 | |
5880 | sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2" | |
5881 | [(set_attr "length" "8")]) | |
5882 | ||
5883 | ;; Shift by a variable amount is too complex to be worth open-coding. We | |
5884 | ;; just handle shifts by constants. | |
5885 | (define_insn "ashrdi3_power" | |
7093ddee | 5886 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
266eb58a DE |
5887 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
5888 | (match_operand:SI 2 "const_int_operand" "M,i"))) | |
5889 | (clobber (match_scratch:SI 3 "=X,q"))] | |
5890 | "TARGET_POWER" | |
5891 | "@ | |
5892 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5893 | sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" | |
5894 | [(set_attr "length" "8")]) | |
4aa74a4f FS |
5895 | |
5896 | (define_insn "ashrdi3_no_power" | |
5897 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") | |
5898 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
5899 | (match_operand:SI 2 "const_int_operand" "M,i")))] | |
97727e85 | 5900 | "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN" |
4aa74a4f FS |
5901 | "@ |
5902 | {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 | |
5903 | {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2" | |
943c15ed DE |
5904 | [(set_attr "type" "two,three") |
5905 | (set_attr "length" "8,12")]) | |
683bdff7 FJ |
5906 | |
5907 | (define_insn "*ashrdisi3_noppc64" | |
5908 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
6ae08853 | 5909 | (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
683bdff7 FJ |
5910 | (const_int 32)) 4))] |
5911 | "TARGET_32BIT && !TARGET_POWERPC64" | |
5912 | "* | |
5913 | { | |
5914 | if (REGNO (operands[0]) == REGNO (operands[1])) | |
5915 | return \"\"; | |
5916 | else | |
5917 | return \"mr %0,%1\"; | |
5918 | }" | |
6ae08853 | 5919 | [(set_attr "length" "4")]) |
683bdff7 | 5920 | |
266eb58a DE |
5921 | \f |
5922 | ;; PowerPC64 DImode operations. | |
5923 | ||
ea112fc4 | 5924 | (define_insn_and_split "absdi2" |
266eb58a | 5925 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 5926 | (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) |
266eb58a DE |
5927 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
5928 | "TARGET_POWERPC64" | |
ea112fc4 DE |
5929 | "#" |
5930 | "&& reload_completed" | |
a260abc9 | 5931 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 5932 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
a238cd8b | 5933 | (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] |
266eb58a DE |
5934 | "") |
5935 | ||
ea112fc4 | 5936 | (define_insn_and_split "*nabsdi2" |
266eb58a | 5937 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
ea112fc4 | 5938 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) |
266eb58a DE |
5939 | (clobber (match_scratch:DI 2 "=&r,&r"))] |
5940 | "TARGET_POWERPC64" | |
ea112fc4 DE |
5941 | "#" |
5942 | "&& reload_completed" | |
a260abc9 | 5943 | [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) |
266eb58a | 5944 | (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) |
19ba8161 | 5945 | (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] |
266eb58a DE |
5946 | "") |
5947 | ||
266eb58a DE |
5948 | (define_insn "muldi3" |
5949 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
5950 | (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r") | |
5951 | (match_operand:DI 2 "gpc_reg_operand" "r")))] | |
5952 | "TARGET_POWERPC64" | |
5953 | "mulld %0,%1,%2" | |
3cb999d8 | 5954 | [(set_attr "type" "lmul")]) |
266eb58a | 5955 | |
9259f3b0 DE |
5956 | (define_insn "*muldi3_internal1" |
5957 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
5958 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
5959 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
5960 | (const_int 0))) | |
5961 | (clobber (match_scratch:DI 3 "=r,r"))] | |
5962 | "TARGET_POWERPC64" | |
5963 | "@ | |
5964 | mulld. %3,%1,%2 | |
5965 | #" | |
5966 | [(set_attr "type" "lmul_compare") | |
5967 | (set_attr "length" "4,8")]) | |
5968 | ||
5969 | (define_split | |
5970 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
5971 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
5972 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
5973 | (const_int 0))) | |
5974 | (clobber (match_scratch:DI 3 ""))] | |
5975 | "TARGET_POWERPC64 && reload_completed" | |
5976 | [(set (match_dup 3) | |
5977 | (mult:DI (match_dup 1) (match_dup 2))) | |
5978 | (set (match_dup 0) | |
5979 | (compare:CC (match_dup 3) | |
5980 | (const_int 0)))] | |
5981 | "") | |
5982 | ||
5983 | (define_insn "*muldi3_internal2" | |
5984 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") | |
5985 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
5986 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) | |
5987 | (const_int 0))) | |
5988 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
5989 | (mult:DI (match_dup 1) (match_dup 2)))] | |
5990 | "TARGET_POWERPC64" | |
5991 | "@ | |
5992 | mulld. %0,%1,%2 | |
5993 | #" | |
5994 | [(set_attr "type" "lmul_compare") | |
5995 | (set_attr "length" "4,8")]) | |
5996 | ||
5997 | (define_split | |
5998 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
5999 | (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6000 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
6001 | (const_int 0))) | |
6002 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6003 | (mult:DI (match_dup 1) (match_dup 2)))] | |
6004 | "TARGET_POWERPC64 && reload_completed" | |
6005 | [(set (match_dup 0) | |
6006 | (mult:DI (match_dup 1) (match_dup 2))) | |
6007 | (set (match_dup 3) | |
6008 | (compare:CC (match_dup 0) | |
6009 | (const_int 0)))] | |
6010 | "") | |
6011 | ||
266eb58a DE |
6012 | (define_insn "smuldi3_highpart" |
6013 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6014 | (truncate:DI | |
6015 | (lshiftrt:TI (mult:TI (sign_extend:TI | |
6016 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6017 | (sign_extend:TI | |
6018 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6019 | (const_int 64))))] | |
6020 | "TARGET_POWERPC64" | |
6021 | "mulhd %0,%1,%2" | |
3cb999d8 | 6022 | [(set_attr "type" "lmul")]) |
266eb58a DE |
6023 | |
6024 | (define_insn "umuldi3_highpart" | |
6025 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6026 | (truncate:DI | |
6027 | (lshiftrt:TI (mult:TI (zero_extend:TI | |
6028 | (match_operand:DI 1 "gpc_reg_operand" "%r")) | |
6029 | (zero_extend:TI | |
6030 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
6031 | (const_int 64))))] | |
6032 | "TARGET_POWERPC64" | |
6033 | "mulhdu %0,%1,%2" | |
3cb999d8 | 6034 | [(set_attr "type" "lmul")]) |
266eb58a | 6035 | |
266eb58a DE |
6036 | (define_insn "rotldi3" |
6037 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6038 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6039 | (match_operand:DI 2 "reg_or_cint_operand" "ri")))] | |
6040 | "TARGET_POWERPC64" | |
a66078ee | 6041 | "rld%I2cl %0,%1,%H2,0") |
266eb58a | 6042 | |
a260abc9 | 6043 | (define_insn "*rotldi3_internal2" |
9ebbca7d GK |
6044 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6045 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6046 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6047 | (const_int 0))) |
9ebbca7d | 6048 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6049 | "TARGET_64BIT" |
9ebbca7d GK |
6050 | "@ |
6051 | rld%I2cl. %3,%1,%H2,0 | |
6052 | #" | |
6053 | [(set_attr "type" "delayed_compare") | |
6054 | (set_attr "length" "4,8")]) | |
6055 | ||
6056 | (define_split | |
6057 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6058 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6059 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6060 | (const_int 0))) | |
6061 | (clobber (match_scratch:DI 3 ""))] | |
6062 | "TARGET_POWERPC64 && reload_completed" | |
6063 | [(set (match_dup 3) | |
6064 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6065 | (set (match_dup 0) | |
6066 | (compare:CC (match_dup 3) | |
6067 | (const_int 0)))] | |
6068 | "") | |
266eb58a | 6069 | |
a260abc9 | 6070 | (define_insn "*rotldi3_internal3" |
9ebbca7d GK |
6071 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6072 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6073 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6074 | (const_int 0))) |
9ebbca7d | 6075 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6076 | (rotate:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6077 | "TARGET_64BIT" |
9ebbca7d GK |
6078 | "@ |
6079 | rld%I2cl. %0,%1,%H2,0 | |
6080 | #" | |
6081 | [(set_attr "type" "delayed_compare") | |
6082 | (set_attr "length" "4,8")]) | |
6083 | ||
6084 | (define_split | |
6085 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6086 | (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6087 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
6088 | (const_int 0))) | |
6089 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6090 | (rotate:DI (match_dup 1) (match_dup 2)))] | |
6091 | "TARGET_POWERPC64 && reload_completed" | |
6092 | [(set (match_dup 0) | |
6093 | (rotate:DI (match_dup 1) (match_dup 2))) | |
6094 | (set (match_dup 3) | |
6095 | (compare:CC (match_dup 0) | |
6096 | (const_int 0)))] | |
6097 | "") | |
266eb58a | 6098 | |
a260abc9 DE |
6099 | (define_insn "*rotldi3_internal4" |
6100 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6101 | (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6102 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) | |
4ae234b0 | 6103 | (match_operand:DI 3 "mask_operand" "n")))] |
a260abc9 DE |
6104 | "TARGET_POWERPC64" |
6105 | "rld%I2c%B3 %0,%1,%H2,%S3") | |
6106 | ||
6107 | (define_insn "*rotldi3_internal5" | |
9ebbca7d | 6108 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 | 6109 | (compare:CC (and:DI |
9ebbca7d GK |
6110 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6111 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
4ae234b0 | 6112 | (match_operand:DI 3 "mask_operand" "n,n")) |
a260abc9 | 6113 | (const_int 0))) |
9ebbca7d | 6114 | (clobber (match_scratch:DI 4 "=r,r"))] |
683bdff7 | 6115 | "TARGET_64BIT" |
9ebbca7d GK |
6116 | "@ |
6117 | rld%I2c%B3. %4,%1,%H2,%S3 | |
6118 | #" | |
6119 | [(set_attr "type" "delayed_compare") | |
6120 | (set_attr "length" "4,8")]) | |
6121 | ||
6122 | (define_split | |
6123 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6124 | (compare:CC (and:DI | |
6125 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6126 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
4ae234b0 | 6127 | (match_operand:DI 3 "mask_operand" "")) |
9ebbca7d GK |
6128 | (const_int 0))) |
6129 | (clobber (match_scratch:DI 4 ""))] | |
6130 | "TARGET_POWERPC64 && reload_completed" | |
6131 | [(set (match_dup 4) | |
6132 | (and:DI (rotate:DI (match_dup 1) | |
6133 | (match_dup 2)) | |
6134 | (match_dup 3))) | |
6135 | (set (match_dup 0) | |
6136 | (compare:CC (match_dup 4) | |
6137 | (const_int 0)))] | |
6138 | "") | |
a260abc9 DE |
6139 | |
6140 | (define_insn "*rotldi3_internal6" | |
9ebbca7d | 6141 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 | 6142 | (compare:CC (and:DI |
9ebbca7d GK |
6143 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6144 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) | |
4ae234b0 | 6145 | (match_operand:DI 3 "mask_operand" "n,n")) |
a260abc9 | 6146 | (const_int 0))) |
9ebbca7d | 6147 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6148 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 6149 | "TARGET_64BIT" |
9ebbca7d GK |
6150 | "@ |
6151 | rld%I2c%B3. %0,%1,%H2,%S3 | |
6152 | #" | |
6153 | [(set_attr "type" "delayed_compare") | |
6154 | (set_attr "length" "4,8")]) | |
6155 | ||
6156 | (define_split | |
6157 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6158 | (compare:CC (and:DI | |
6159 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6160 | (match_operand:DI 2 "reg_or_cint_operand" "")) | |
4ae234b0 | 6161 | (match_operand:DI 3 "mask_operand" "")) |
9ebbca7d GK |
6162 | (const_int 0))) |
6163 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6164 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6165 | "TARGET_POWERPC64 && reload_completed" | |
6166 | [(set (match_dup 0) | |
6167 | (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) | |
6168 | (set (match_dup 4) | |
6169 | (compare:CC (match_dup 0) | |
6170 | (const_int 0)))] | |
6171 | "") | |
a260abc9 DE |
6172 | |
6173 | (define_insn "*rotldi3_internal7" | |
6174 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6175 | (zero_extend:DI | |
6176 | (subreg:QI | |
6177 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6178 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6179 | "TARGET_POWERPC64" | |
6180 | "rld%I2cl %0,%1,%H2,56") | |
6181 | ||
6182 | (define_insn "*rotldi3_internal8" | |
9ebbca7d | 6183 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6184 | (compare:CC (zero_extend:DI |
6185 | (subreg:QI | |
9ebbca7d GK |
6186 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6187 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6188 | (const_int 0))) |
9ebbca7d | 6189 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6190 | "TARGET_64BIT" |
9ebbca7d GK |
6191 | "@ |
6192 | rld%I2cl. %3,%1,%H2,56 | |
6193 | #" | |
6194 | [(set_attr "type" "delayed_compare") | |
6195 | (set_attr "length" "4,8")]) | |
6196 | ||
6197 | (define_split | |
6198 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6199 | (compare:CC (zero_extend:DI | |
6200 | (subreg:QI | |
6201 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6202 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6203 | (const_int 0))) | |
6204 | (clobber (match_scratch:DI 3 ""))] | |
6205 | "TARGET_POWERPC64 && reload_completed" | |
6206 | [(set (match_dup 3) | |
6207 | (zero_extend:DI (subreg:QI | |
6208 | (rotate:DI (match_dup 1) | |
6209 | (match_dup 2)) 0))) | |
6210 | (set (match_dup 0) | |
6211 | (compare:CC (match_dup 3) | |
6212 | (const_int 0)))] | |
6213 | "") | |
a260abc9 DE |
6214 | |
6215 | (define_insn "*rotldi3_internal9" | |
9ebbca7d | 6216 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6217 | (compare:CC (zero_extend:DI |
6218 | (subreg:QI | |
9ebbca7d GK |
6219 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6220 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6221 | (const_int 0))) |
9ebbca7d | 6222 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6223 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6224 | "TARGET_64BIT" |
9ebbca7d GK |
6225 | "@ |
6226 | rld%I2cl. %0,%1,%H2,56 | |
6227 | #" | |
6228 | [(set_attr "type" "delayed_compare") | |
6229 | (set_attr "length" "4,8")]) | |
6230 | ||
6231 | (define_split | |
6232 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6233 | (compare:CC (zero_extend:DI | |
6234 | (subreg:QI | |
6235 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6236 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6237 | (const_int 0))) | |
6238 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6239 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6240 | "TARGET_POWERPC64 && reload_completed" | |
6241 | [(set (match_dup 0) | |
6242 | (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6243 | (set (match_dup 3) | |
6244 | (compare:CC (match_dup 0) | |
6245 | (const_int 0)))] | |
6246 | "") | |
a260abc9 DE |
6247 | |
6248 | (define_insn "*rotldi3_internal10" | |
6249 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6250 | (zero_extend:DI | |
6251 | (subreg:HI | |
6252 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6253 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6254 | "TARGET_POWERPC64" | |
6255 | "rld%I2cl %0,%1,%H2,48") | |
6256 | ||
6257 | (define_insn "*rotldi3_internal11" | |
9ebbca7d | 6258 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6259 | (compare:CC (zero_extend:DI |
6260 | (subreg:HI | |
9ebbca7d GK |
6261 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6262 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6263 | (const_int 0))) |
9ebbca7d | 6264 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6265 | "TARGET_64BIT" |
9ebbca7d GK |
6266 | "@ |
6267 | rld%I2cl. %3,%1,%H2,48 | |
6268 | #" | |
6269 | [(set_attr "type" "delayed_compare") | |
6270 | (set_attr "length" "4,8")]) | |
6271 | ||
6272 | (define_split | |
6273 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6274 | (compare:CC (zero_extend:DI | |
6275 | (subreg:HI | |
6276 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6277 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6278 | (const_int 0))) | |
6279 | (clobber (match_scratch:DI 3 ""))] | |
6280 | "TARGET_POWERPC64 && reload_completed" | |
6281 | [(set (match_dup 3) | |
6282 | (zero_extend:DI (subreg:HI | |
6283 | (rotate:DI (match_dup 1) | |
6284 | (match_dup 2)) 0))) | |
6285 | (set (match_dup 0) | |
6286 | (compare:CC (match_dup 3) | |
6287 | (const_int 0)))] | |
6288 | "") | |
a260abc9 DE |
6289 | |
6290 | (define_insn "*rotldi3_internal12" | |
9ebbca7d | 6291 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6292 | (compare:CC (zero_extend:DI |
6293 | (subreg:HI | |
9ebbca7d GK |
6294 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6295 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6296 | (const_int 0))) |
9ebbca7d | 6297 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6298 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6299 | "TARGET_64BIT" |
9ebbca7d GK |
6300 | "@ |
6301 | rld%I2cl. %0,%1,%H2,48 | |
6302 | #" | |
6303 | [(set_attr "type" "delayed_compare") | |
6304 | (set_attr "length" "4,8")]) | |
6305 | ||
6306 | (define_split | |
6307 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6308 | (compare:CC (zero_extend:DI | |
6309 | (subreg:HI | |
6310 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6311 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6312 | (const_int 0))) | |
6313 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6314 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6315 | "TARGET_POWERPC64 && reload_completed" | |
6316 | [(set (match_dup 0) | |
6317 | (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6318 | (set (match_dup 3) | |
6319 | (compare:CC (match_dup 0) | |
6320 | (const_int 0)))] | |
6321 | "") | |
a260abc9 DE |
6322 | |
6323 | (define_insn "*rotldi3_internal13" | |
6324 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6325 | (zero_extend:DI | |
6326 | (subreg:SI | |
6327 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6328 | (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))] | |
6329 | "TARGET_POWERPC64" | |
6330 | "rld%I2cl %0,%1,%H2,32") | |
6331 | ||
6332 | (define_insn "*rotldi3_internal14" | |
9ebbca7d | 6333 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6334 | (compare:CC (zero_extend:DI |
6335 | (subreg:SI | |
9ebbca7d GK |
6336 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6337 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6338 | (const_int 0))) |
9ebbca7d | 6339 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6340 | "TARGET_64BIT" |
9ebbca7d GK |
6341 | "@ |
6342 | rld%I2cl. %3,%1,%H2,32 | |
6343 | #" | |
6344 | [(set_attr "type" "delayed_compare") | |
6345 | (set_attr "length" "4,8")]) | |
6346 | ||
6347 | (define_split | |
6348 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6349 | (compare:CC (zero_extend:DI | |
6350 | (subreg:SI | |
6351 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6352 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6353 | (const_int 0))) | |
6354 | (clobber (match_scratch:DI 3 ""))] | |
6355 | "TARGET_POWERPC64 && reload_completed" | |
6356 | [(set (match_dup 3) | |
6357 | (zero_extend:DI (subreg:SI | |
6358 | (rotate:DI (match_dup 1) | |
6359 | (match_dup 2)) 0))) | |
6360 | (set (match_dup 0) | |
6361 | (compare:CC (match_dup 3) | |
6362 | (const_int 0)))] | |
6363 | "") | |
a260abc9 DE |
6364 | |
6365 | (define_insn "*rotldi3_internal15" | |
9ebbca7d | 6366 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
6367 | (compare:CC (zero_extend:DI |
6368 | (subreg:SI | |
9ebbca7d GK |
6369 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6370 | (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0)) | |
a260abc9 | 6371 | (const_int 0))) |
9ebbca7d | 6372 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 | 6373 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] |
683bdff7 | 6374 | "TARGET_64BIT" |
9ebbca7d GK |
6375 | "@ |
6376 | rld%I2cl. %0,%1,%H2,32 | |
6377 | #" | |
6378 | [(set_attr "type" "delayed_compare") | |
6379 | (set_attr "length" "4,8")]) | |
6380 | ||
6381 | (define_split | |
6382 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6383 | (compare:CC (zero_extend:DI | |
6384 | (subreg:SI | |
6385 | (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6386 | (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) | |
6387 | (const_int 0))) | |
6388 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6389 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] | |
6390 | "TARGET_POWERPC64 && reload_completed" | |
6391 | [(set (match_dup 0) | |
6392 | (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) | |
6393 | (set (match_dup 3) | |
6394 | (compare:CC (match_dup 0) | |
6395 | (const_int 0)))] | |
6396 | "") | |
a260abc9 | 6397 | |
266eb58a DE |
6398 | (define_expand "ashldi3" |
6399 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6400 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6401 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6402 | "TARGET_POWERPC64 || TARGET_POWER" | |
6403 | " | |
6404 | { | |
6405 | if (TARGET_POWERPC64) | |
6406 | ; | |
6407 | else if (TARGET_POWER) | |
6408 | { | |
6409 | emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2])); | |
6410 | DONE; | |
6411 | } | |
6412 | else | |
6413 | FAIL; | |
6414 | }") | |
6415 | ||
e2c953b6 | 6416 | (define_insn "*ashldi3_internal1" |
266eb58a DE |
6417 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6418 | (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6419 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6420 | "TARGET_POWERPC64" | |
943c15ed | 6421 | "sld%I2 %0,%1,%H2") |
6ae08853 | 6422 | |
e2c953b6 | 6423 | (define_insn "*ashldi3_internal2" |
9ebbca7d GK |
6424 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6425 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6426 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6427 | (const_int 0))) |
9ebbca7d | 6428 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6429 | "TARGET_64BIT" |
9ebbca7d GK |
6430 | "@ |
6431 | sld%I2. %3,%1,%H2 | |
6432 | #" | |
6433 | [(set_attr "type" "delayed_compare") | |
6434 | (set_attr "length" "4,8")]) | |
6ae08853 | 6435 | |
9ebbca7d GK |
6436 | (define_split |
6437 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6438 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6439 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6440 | (const_int 0))) | |
6441 | (clobber (match_scratch:DI 3 ""))] | |
6442 | "TARGET_POWERPC64 && reload_completed" | |
6443 | [(set (match_dup 3) | |
6444 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6445 | (set (match_dup 0) | |
6446 | (compare:CC (match_dup 3) | |
6447 | (const_int 0)))] | |
6448 | "") | |
6449 | ||
e2c953b6 | 6450 | (define_insn "*ashldi3_internal3" |
9ebbca7d GK |
6451 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6452 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6453 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6454 | (const_int 0))) |
9ebbca7d | 6455 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6456 | (ashift:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6457 | "TARGET_64BIT" |
9ebbca7d GK |
6458 | "@ |
6459 | sld%I2. %0,%1,%H2 | |
6460 | #" | |
6461 | [(set_attr "type" "delayed_compare") | |
6462 | (set_attr "length" "4,8")]) | |
6463 | ||
6464 | (define_split | |
6465 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6466 | (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6467 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6468 | (const_int 0))) | |
6469 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6470 | (ashift:DI (match_dup 1) (match_dup 2)))] | |
6471 | "TARGET_POWERPC64 && reload_completed" | |
6472 | [(set (match_dup 0) | |
6473 | (ashift:DI (match_dup 1) (match_dup 2))) | |
6474 | (set (match_dup 3) | |
6475 | (compare:CC (match_dup 0) | |
6476 | (const_int 0)))] | |
6477 | "") | |
266eb58a | 6478 | |
e2c953b6 | 6479 | (define_insn "*ashldi3_internal4" |
3cb999d8 DE |
6480 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6481 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6482 | (match_operand:SI 2 "const_int_operand" "i")) | |
c5059423 AM |
6483 | (match_operand:DI 3 "const_int_operand" "n")))] |
6484 | "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" | |
e2c953b6 | 6485 | "rldic %0,%1,%H2,%W3") |
3cb999d8 | 6486 | |
e2c953b6 | 6487 | (define_insn "ashldi3_internal5" |
9ebbca7d | 6488 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6489 | (compare:CC |
9ebbca7d GK |
6490 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6491 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6492 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6493 | (const_int 0))) |
9ebbca7d | 6494 | (clobber (match_scratch:DI 4 "=r,r"))] |
683bdff7 | 6495 | "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6496 | "@ |
e2c953b6 | 6497 | rldic. %4,%1,%H2,%W3 |
9ebbca7d GK |
6498 | #" |
6499 | [(set_attr "type" "delayed_compare") | |
6500 | (set_attr "length" "4,8")]) | |
6501 | ||
6502 | (define_split | |
6503 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6504 | (compare:CC | |
6505 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6506 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6507 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6508 | (const_int 0))) |
6509 | (clobber (match_scratch:DI 4 ""))] | |
c5059423 AM |
6510 | "TARGET_POWERPC64 && reload_completed |
6511 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
9ebbca7d GK |
6512 | [(set (match_dup 4) |
6513 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
e2c953b6 | 6514 | (match_dup 3))) |
9ebbca7d GK |
6515 | (set (match_dup 0) |
6516 | (compare:CC (match_dup 4) | |
6517 | (const_int 0)))] | |
6518 | "") | |
3cb999d8 | 6519 | |
e2c953b6 | 6520 | (define_insn "*ashldi3_internal6" |
9ebbca7d | 6521 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
3cb999d8 | 6522 | (compare:CC |
9ebbca7d GK |
6523 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
6524 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
c5059423 | 6525 | (match_operand:DI 3 "const_int_operand" "n,n")) |
3cb999d8 | 6526 | (const_int 0))) |
9ebbca7d | 6527 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
3cb999d8 | 6528 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 6529 | "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" |
9ebbca7d | 6530 | "@ |
e2c953b6 | 6531 | rldic. %0,%1,%H2,%W3 |
9ebbca7d GK |
6532 | #" |
6533 | [(set_attr "type" "delayed_compare") | |
6534 | (set_attr "length" "4,8")]) | |
6535 | ||
6536 | (define_split | |
6537 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6538 | (compare:CC | |
6539 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6540 | (match_operand:SI 2 "const_int_operand" "")) | |
c5059423 | 6541 | (match_operand:DI 3 "const_int_operand" "")) |
9ebbca7d GK |
6542 | (const_int 0))) |
6543 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6544 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
c5059423 AM |
6545 | "TARGET_POWERPC64 && reload_completed |
6546 | && includes_rldic_lshift_p (operands[2], operands[3])" | |
6547 | [(set (match_dup 0) | |
6548 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6549 | (match_dup 3))) | |
6550 | (set (match_dup 4) | |
6551 | (compare:CC (match_dup 0) | |
6552 | (const_int 0)))] | |
6553 | "") | |
6554 | ||
6555 | (define_insn "*ashldi3_internal7" | |
6556 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
6557 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6558 | (match_operand:SI 2 "const_int_operand" "i")) | |
4ae234b0 | 6559 | (match_operand:DI 3 "mask_operand" "n")))] |
c5059423 AM |
6560 | "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" |
6561 | "rldicr %0,%1,%H2,%S3") | |
6562 | ||
6563 | (define_insn "ashldi3_internal8" | |
6564 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
6565 | (compare:CC | |
6566 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6567 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4ae234b0 | 6568 | (match_operand:DI 3 "mask_operand" "n,n")) |
c5059423 AM |
6569 | (const_int 0))) |
6570 | (clobber (match_scratch:DI 4 "=r,r"))] | |
683bdff7 | 6571 | "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" |
c5059423 AM |
6572 | "@ |
6573 | rldicr. %4,%1,%H2,%S3 | |
6574 | #" | |
6575 | [(set_attr "type" "delayed_compare") | |
6576 | (set_attr "length" "4,8")]) | |
6577 | ||
6578 | (define_split | |
6579 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6580 | (compare:CC | |
6581 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6582 | (match_operand:SI 2 "const_int_operand" "")) | |
4ae234b0 | 6583 | (match_operand:DI 3 "mask_operand" "")) |
c5059423 AM |
6584 | (const_int 0))) |
6585 | (clobber (match_scratch:DI 4 ""))] | |
6586 | "TARGET_POWERPC64 && reload_completed | |
6587 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
6588 | [(set (match_dup 4) | |
6589 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) | |
6590 | (match_dup 3))) | |
6591 | (set (match_dup 0) | |
6592 | (compare:CC (match_dup 4) | |
6593 | (const_int 0)))] | |
6594 | "") | |
6595 | ||
6596 | (define_insn "*ashldi3_internal9" | |
6597 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
6598 | (compare:CC | |
6599 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6600 | (match_operand:SI 2 "const_int_operand" "i,i")) | |
4ae234b0 | 6601 | (match_operand:DI 3 "mask_operand" "n,n")) |
c5059423 AM |
6602 | (const_int 0))) |
6603 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
6604 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 6605 | "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" |
c5059423 AM |
6606 | "@ |
6607 | rldicr. %0,%1,%H2,%S3 | |
6608 | #" | |
6609 | [(set_attr "type" "delayed_compare") | |
6610 | (set_attr "length" "4,8")]) | |
6611 | ||
6612 | (define_split | |
6613 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
6614 | (compare:CC | |
6615 | (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6616 | (match_operand:SI 2 "const_int_operand" "")) | |
4ae234b0 | 6617 | (match_operand:DI 3 "mask_operand" "")) |
c5059423 AM |
6618 | (const_int 0))) |
6619 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6620 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
6621 | "TARGET_POWERPC64 && reload_completed | |
6622 | && includes_rldicr_lshift_p (operands[2], operands[3])" | |
9ebbca7d | 6623 | [(set (match_dup 0) |
e2c953b6 DE |
6624 | (and:DI (ashift:DI (match_dup 1) (match_dup 2)) |
6625 | (match_dup 3))) | |
9ebbca7d GK |
6626 | (set (match_dup 4) |
6627 | (compare:CC (match_dup 0) | |
6628 | (const_int 0)))] | |
6629 | "") | |
6630 | ||
6631 | (define_expand "lshrdi3" | |
266eb58a DE |
6632 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
6633 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6634 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
6635 | "TARGET_POWERPC64 || TARGET_POWER" | |
6636 | " | |
6637 | { | |
6638 | if (TARGET_POWERPC64) | |
6639 | ; | |
6640 | else if (TARGET_POWER) | |
6641 | { | |
6642 | emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2])); | |
6643 | DONE; | |
6644 | } | |
6645 | else | |
6646 | FAIL; | |
6647 | }") | |
6648 | ||
e2c953b6 | 6649 | (define_insn "*lshrdi3_internal1" |
266eb58a DE |
6650 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6651 | (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6652 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6653 | "TARGET_POWERPC64" | |
a66078ee | 6654 | "srd%I2 %0,%1,%H2") |
266eb58a | 6655 | |
e2c953b6 | 6656 | (define_insn "*lshrdi3_internal2" |
9ebbca7d GK |
6657 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6658 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6659 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
29ae5b89 | 6660 | (const_int 0))) |
9ebbca7d | 6661 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6662 | "TARGET_64BIT " |
9ebbca7d GK |
6663 | "@ |
6664 | srd%I2. %3,%1,%H2 | |
6665 | #" | |
6666 | [(set_attr "type" "delayed_compare") | |
6667 | (set_attr "length" "4,8")]) | |
6668 | ||
6669 | (define_split | |
6670 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6671 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6672 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6673 | (const_int 0))) | |
6674 | (clobber (match_scratch:DI 3 ""))] | |
6675 | "TARGET_POWERPC64 && reload_completed" | |
6676 | [(set (match_dup 3) | |
6677 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6678 | (set (match_dup 0) | |
6679 | (compare:CC (match_dup 3) | |
6680 | (const_int 0)))] | |
6681 | "") | |
266eb58a | 6682 | |
e2c953b6 | 6683 | (define_insn "*lshrdi3_internal3" |
9ebbca7d GK |
6684 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6685 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6686 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6687 | (const_int 0))) |
9ebbca7d | 6688 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
29ae5b89 | 6689 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6690 | "TARGET_64BIT" |
9ebbca7d GK |
6691 | "@ |
6692 | srd%I2. %0,%1,%H2 | |
6693 | #" | |
6694 | [(set_attr "type" "delayed_compare") | |
6695 | (set_attr "length" "4,8")]) | |
6696 | ||
6697 | (define_split | |
6698 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6699 | (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6700 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6701 | (const_int 0))) | |
6702 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6703 | (lshiftrt:DI (match_dup 1) (match_dup 2)))] | |
6704 | "TARGET_POWERPC64 && reload_completed" | |
6705 | [(set (match_dup 0) | |
6706 | (lshiftrt:DI (match_dup 1) (match_dup 2))) | |
6707 | (set (match_dup 3) | |
6708 | (compare:CC (match_dup 0) | |
6709 | (const_int 0)))] | |
6710 | "") | |
266eb58a DE |
6711 | |
6712 | (define_expand "ashrdi3" | |
6713 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6714 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6715 | (match_operand:SI 2 "reg_or_cint_operand" "")))] | |
97727e85 | 6716 | "WORDS_BIG_ENDIAN" |
266eb58a DE |
6717 | " |
6718 | { | |
6719 | if (TARGET_POWERPC64) | |
6720 | ; | |
6721 | else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT) | |
6722 | { | |
6723 | emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); | |
6724 | DONE; | |
6725 | } | |
97727e85 AH |
6726 | else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT |
6727 | && WORDS_BIG_ENDIAN) | |
4aa74a4f FS |
6728 | { |
6729 | emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); | |
6730 | DONE; | |
6731 | } | |
266eb58a DE |
6732 | else |
6733 | FAIL; | |
6734 | }") | |
6735 | ||
e2c953b6 | 6736 | (define_insn "*ashrdi3_internal1" |
266eb58a DE |
6737 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
6738 | (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
6739 | (match_operand:SI 2 "reg_or_cint_operand" "ri")))] | |
6740 | "TARGET_POWERPC64" | |
375490e0 | 6741 | "srad%I2 %0,%1,%H2") |
266eb58a | 6742 | |
e2c953b6 | 6743 | (define_insn "*ashrdi3_internal2" |
9ebbca7d GK |
6744 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
6745 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6746 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6747 | (const_int 0))) |
9ebbca7d | 6748 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 6749 | "TARGET_64BIT" |
9ebbca7d GK |
6750 | "@ |
6751 | srad%I2. %3,%1,%H2 | |
6752 | #" | |
6753 | [(set_attr "type" "delayed_compare") | |
6754 | (set_attr "length" "4,8")]) | |
6755 | ||
6756 | (define_split | |
6757 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
6758 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6759 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6760 | (const_int 0))) | |
6761 | (clobber (match_scratch:DI 3 ""))] | |
6762 | "TARGET_POWERPC64 && reload_completed" | |
6763 | [(set (match_dup 3) | |
6764 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
6765 | (set (match_dup 0) | |
6766 | (compare:CC (match_dup 3) | |
6767 | (const_int 0)))] | |
6768 | "") | |
266eb58a | 6769 | |
e2c953b6 | 6770 | (define_insn "*ashrdi3_internal3" |
9ebbca7d GK |
6771 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
6772 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
6773 | (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) | |
266eb58a | 6774 | (const_int 0))) |
9ebbca7d | 6775 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
266eb58a | 6776 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 6777 | "TARGET_64BIT" |
9ebbca7d GK |
6778 | "@ |
6779 | srad%I2. %0,%1,%H2 | |
6780 | #" | |
6781 | [(set_attr "type" "delayed_compare") | |
6782 | (set_attr "length" "4,8")]) | |
6783 | ||
6784 | (define_split | |
6785 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6786 | (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6787 | (match_operand:SI 2 "reg_or_cint_operand" "")) | |
6788 | (const_int 0))) | |
6789 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6790 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] | |
6791 | "TARGET_POWERPC64 && reload_completed" | |
6792 | [(set (match_dup 0) | |
6793 | (ashiftrt:DI (match_dup 1) (match_dup 2))) | |
6794 | (set (match_dup 3) | |
6795 | (compare:CC (match_dup 0) | |
6796 | (const_int 0)))] | |
6797 | "") | |
815cdc52 | 6798 | |
29ae5b89 | 6799 | (define_insn "anddi3" |
e1e2e653 NS |
6800 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r") |
6801 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r") | |
6802 | (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t"))) | |
6803 | (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))] | |
6ffc8580 | 6804 | "TARGET_POWERPC64" |
266eb58a DE |
6805 | "@ |
6806 | and %0,%1,%2 | |
29ae5b89 | 6807 | rldic%B2 %0,%1,0,%S2 |
e1e2e653 | 6808 | rlwinm %0,%1,0,%m2,%M2 |
29ae5b89 | 6809 | andi. %0,%1,%b2 |
0ba1b2ff AM |
6810 | andis. %0,%1,%u2 |
6811 | #" | |
e1e2e653 NS |
6812 | [(set_attr "type" "*,*,*,compare,compare,*") |
6813 | (set_attr "length" "4,4,4,4,4,8")]) | |
0ba1b2ff AM |
6814 | |
6815 | (define_split | |
6816 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6817 | (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6818 | (match_operand:DI 2 "mask64_2_operand" ""))) | |
6819 | (clobber (match_scratch:CC 3 ""))] | |
6820 | "TARGET_POWERPC64 | |
6821 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
4ae234b0 | 6822 | && !mask_operand (operands[2], DImode)" |
0ba1b2ff AM |
6823 | [(set (match_dup 0) |
6824 | (and:DI (rotate:DI (match_dup 1) | |
6825 | (match_dup 4)) | |
6826 | (match_dup 5))) | |
6827 | (set (match_dup 0) | |
6828 | (and:DI (rotate:DI (match_dup 0) | |
6829 | (match_dup 6)) | |
6830 | (match_dup 7)))] | |
0ba1b2ff AM |
6831 | { |
6832 | build_mask64_2_operands (operands[2], &operands[4]); | |
e1e2e653 | 6833 | }) |
266eb58a | 6834 | |
a260abc9 | 6835 | (define_insn "*anddi3_internal2" |
0ba1b2ff AM |
6836 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
6837 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
6838 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 6839 | (const_int 0))) |
0ba1b2ff AM |
6840 | (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r")) |
6841 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] | |
683bdff7 | 6842 | "TARGET_64BIT" |
266eb58a DE |
6843 | "@ |
6844 | and. %3,%1,%2 | |
6c873122 | 6845 | rldic%B2. %3,%1,0,%S2 |
6ffc8580 MM |
6846 | andi. %3,%1,%b2 |
6847 | andis. %3,%1,%u2 | |
9ebbca7d GK |
6848 | # |
6849 | # | |
6850 | # | |
0ba1b2ff AM |
6851 | # |
6852 | # | |
9ebbca7d | 6853 | #" |
0ba1b2ff AM |
6854 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
6855 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d | 6856 | |
0ba1b2ff AM |
6857 | (define_split |
6858 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
6859 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6860 | (match_operand:DI 2 "mask64_2_operand" "")) | |
6861 | (const_int 0))) | |
6862 | (clobber (match_scratch:DI 3 "")) | |
6863 | (clobber (match_scratch:CC 4 ""))] | |
6864 | "TARGET_POWERPC64 && reload_completed | |
6865 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
4ae234b0 | 6866 | && !mask_operand (operands[2], DImode)" |
0ba1b2ff AM |
6867 | [(set (match_dup 3) |
6868 | (and:DI (rotate:DI (match_dup 1) | |
6869 | (match_dup 5)) | |
6870 | (match_dup 6))) | |
6871 | (parallel [(set (match_dup 0) | |
6872 | (compare:CC (and:DI (rotate:DI (match_dup 3) | |
6873 | (match_dup 7)) | |
6874 | (match_dup 8)) | |
6875 | (const_int 0))) | |
6876 | (clobber (match_dup 3))])] | |
6877 | " | |
6878 | { | |
6879 | build_mask64_2_operands (operands[2], &operands[5]); | |
6880 | }") | |
6881 | ||
a260abc9 | 6882 | (define_insn "*anddi3_internal3" |
0ba1b2ff AM |
6883 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") |
6884 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") | |
6885 | (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) | |
266eb58a | 6886 | (const_int 0))) |
0ba1b2ff | 6887 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") |
9ebbca7d | 6888 | (and:DI (match_dup 1) (match_dup 2))) |
0ba1b2ff | 6889 | (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] |
683bdff7 | 6890 | "TARGET_64BIT" |
266eb58a DE |
6891 | "@ |
6892 | and. %0,%1,%2 | |
6c873122 | 6893 | rldic%B2. %0,%1,0,%S2 |
6ffc8580 MM |
6894 | andi. %0,%1,%b2 |
6895 | andis. %0,%1,%u2 | |
9ebbca7d GK |
6896 | # |
6897 | # | |
6898 | # | |
0ba1b2ff AM |
6899 | # |
6900 | # | |
9ebbca7d | 6901 | #" |
0ba1b2ff AM |
6902 | [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") |
6903 | (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) | |
9ebbca7d GK |
6904 | |
6905 | (define_split | |
6906 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
6907 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
4ae234b0 | 6908 | (match_operand:DI 2 "and_operand" "")) |
9ebbca7d GK |
6909 | (const_int 0))) |
6910 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6911 | (and:DI (match_dup 1) (match_dup 2))) | |
6912 | (clobber (match_scratch:CC 4 ""))] | |
6913 | "TARGET_POWERPC64 && reload_completed" | |
6914 | [(parallel [(set (match_dup 0) | |
6915 | (and:DI (match_dup 1) (match_dup 2))) | |
6916 | (clobber (match_dup 4))]) | |
6917 | (set (match_dup 3) | |
6918 | (compare:CC (match_dup 0) | |
6919 | (const_int 0)))] | |
6920 | "") | |
266eb58a | 6921 | |
0ba1b2ff AM |
6922 | (define_split |
6923 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
6924 | (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
6925 | (match_operand:DI 2 "mask64_2_operand" "")) | |
6926 | (const_int 0))) | |
6927 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
6928 | (and:DI (match_dup 1) (match_dup 2))) | |
6929 | (clobber (match_scratch:CC 4 ""))] | |
6930 | "TARGET_POWERPC64 && reload_completed | |
6931 | && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) | |
4ae234b0 | 6932 | && !mask_operand (operands[2], DImode)" |
0ba1b2ff AM |
6933 | [(set (match_dup 0) |
6934 | (and:DI (rotate:DI (match_dup 1) | |
6935 | (match_dup 5)) | |
6936 | (match_dup 6))) | |
6937 | (parallel [(set (match_dup 3) | |
6938 | (compare:CC (and:DI (rotate:DI (match_dup 0) | |
6939 | (match_dup 7)) | |
6940 | (match_dup 8)) | |
6941 | (const_int 0))) | |
6942 | (set (match_dup 0) | |
6943 | (and:DI (rotate:DI (match_dup 0) | |
6944 | (match_dup 7)) | |
6945 | (match_dup 8)))])] | |
6946 | " | |
6947 | { | |
6948 | build_mask64_2_operands (operands[2], &operands[5]); | |
6949 | }") | |
6950 | ||
a260abc9 | 6951 | (define_expand "iordi3" |
266eb58a | 6952 | [(set (match_operand:DI 0 "gpc_reg_operand" "") |
a260abc9 | 6953 | (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") |
1d328b19 | 6954 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
266eb58a | 6955 | "TARGET_POWERPC64" |
266eb58a DE |
6956 | " |
6957 | { | |
dfbdccdb | 6958 | if (non_logical_cint_operand (operands[2], DImode)) |
266eb58a | 6959 | { |
dfbdccdb | 6960 | HOST_WIDE_INT value; |
677a9668 | 6961 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 | 6962 | ? operands[0] : gen_reg_rtx (DImode)); |
266eb58a | 6963 | |
dfbdccdb GK |
6964 | if (GET_CODE (operands[2]) == CONST_INT) |
6965 | { | |
6966 | value = INTVAL (operands[2]); | |
6967 | emit_insn (gen_iordi3 (tmp, operands[1], | |
6968 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
6969 | } | |
e2c953b6 | 6970 | else |
dfbdccdb GK |
6971 | { |
6972 | value = CONST_DOUBLE_LOW (operands[2]); | |
6973 | emit_insn (gen_iordi3 (tmp, operands[1], | |
6974 | immed_double_const (value | |
6975 | & (~ (HOST_WIDE_INT) 0xffff), | |
6976 | 0, DImode))); | |
6977 | } | |
e2c953b6 | 6978 | |
9ebbca7d GK |
6979 | emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
6980 | DONE; | |
6981 | } | |
266eb58a DE |
6982 | }") |
6983 | ||
a260abc9 DE |
6984 | (define_expand "xordi3" |
6985 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
6986 | (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
1d328b19 | 6987 | (match_operand:DI 2 "reg_or_logical_cint_operand" "")))] |
a260abc9 DE |
6988 | "TARGET_POWERPC64" |
6989 | " | |
6990 | { | |
dfbdccdb | 6991 | if (non_logical_cint_operand (operands[2], DImode)) |
a260abc9 | 6992 | { |
dfbdccdb | 6993 | HOST_WIDE_INT value; |
677a9668 | 6994 | rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1])) |
a260abc9 DE |
6995 | ? operands[0] : gen_reg_rtx (DImode)); |
6996 | ||
dfbdccdb GK |
6997 | if (GET_CODE (operands[2]) == CONST_INT) |
6998 | { | |
6999 | value = INTVAL (operands[2]); | |
7000 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7001 | GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); | |
7002 | } | |
e2c953b6 | 7003 | else |
dfbdccdb GK |
7004 | { |
7005 | value = CONST_DOUBLE_LOW (operands[2]); | |
7006 | emit_insn (gen_xordi3 (tmp, operands[1], | |
7007 | immed_double_const (value | |
7008 | & (~ (HOST_WIDE_INT) 0xffff), | |
7009 | 0, DImode))); | |
7010 | } | |
e2c953b6 | 7011 | |
9ebbca7d GK |
7012 | emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); |
7013 | DONE; | |
7014 | } | |
a260abc9 DE |
7015 | }") |
7016 | ||
dfbdccdb | 7017 | (define_insn "*booldi3_internal1" |
266eb58a | 7018 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") |
1d328b19 | 7019 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7020 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") |
7021 | (match_operand:DI 2 "logical_operand" "r,K,JF")]))] | |
266eb58a | 7022 | "TARGET_POWERPC64" |
1fd4e8c1 | 7023 | "@ |
dfbdccdb GK |
7024 | %q3 %0,%1,%2 |
7025 | %q3i %0,%1,%b2 | |
7026 | %q3is %0,%1,%u2") | |
1fd4e8c1 | 7027 | |
dfbdccdb | 7028 | (define_insn "*booldi3_internal2" |
9ebbca7d | 7029 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1d328b19 | 7030 | (compare:CC (match_operator:DI 4 "boolean_or_operator" |
dfbdccdb GK |
7031 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") |
7032 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7033 | (const_int 0))) | |
9ebbca7d | 7034 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7035 | "TARGET_64BIT" |
9ebbca7d | 7036 | "@ |
dfbdccdb | 7037 | %q4. %3,%1,%2 |
9ebbca7d GK |
7038 | #" |
7039 | [(set_attr "type" "compare") | |
7040 | (set_attr "length" "4,8")]) | |
7041 | ||
7042 | (define_split | |
7043 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7044 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7045 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7046 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7047 | (const_int 0))) |
9ebbca7d GK |
7048 | (clobber (match_scratch:DI 3 ""))] |
7049 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7050 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7051 | (set (match_dup 0) |
7052 | (compare:CC (match_dup 3) | |
7053 | (const_int 0)))] | |
7054 | "") | |
1fd4e8c1 | 7055 | |
dfbdccdb | 7056 | (define_insn "*booldi3_internal3" |
9ebbca7d | 7057 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7058 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7059 | [(match_operand:DI 1 "gpc_reg_operand" "%r,r") | |
7060 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7061 | (const_int 0))) | |
9ebbca7d | 7062 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7063 | (match_dup 4))] |
683bdff7 | 7064 | "TARGET_64BIT" |
9ebbca7d | 7065 | "@ |
dfbdccdb | 7066 | %q4. %0,%1,%2 |
9ebbca7d GK |
7067 | #" |
7068 | [(set_attr "type" "compare") | |
7069 | (set_attr "length" "4,8")]) | |
7070 | ||
7071 | (define_split | |
e72247f4 | 7072 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7073 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7074 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7075 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7076 | (const_int 0))) |
75540af0 | 7077 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7078 | (match_dup 4))] |
9ebbca7d | 7079 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7080 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7081 | (set (match_dup 3) |
7082 | (compare:CC (match_dup 0) | |
7083 | (const_int 0)))] | |
7084 | "") | |
1fd4e8c1 | 7085 | |
6ae08853 | 7086 | ;; Split a logical operation that we can't do in one insn into two insns, |
dfbdccdb | 7087 | ;; each of which does one 16-bit part. This is used by combine. |
266eb58a DE |
7088 | |
7089 | (define_split | |
7090 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
1d328b19 | 7091 | (match_operator:DI 3 "boolean_or_operator" |
dfbdccdb GK |
7092 | [(match_operand:DI 1 "gpc_reg_operand" "") |
7093 | (match_operand:DI 2 "non_logical_cint_operand" "")]))] | |
266eb58a | 7094 | "TARGET_POWERPC64" |
dfbdccdb GK |
7095 | [(set (match_dup 0) (match_dup 4)) |
7096 | (set (match_dup 0) (match_dup 5))] | |
266eb58a DE |
7097 | " |
7098 | { | |
dfbdccdb | 7099 | rtx i3,i4; |
6ae08853 | 7100 | |
9ebbca7d GK |
7101 | if (GET_CODE (operands[2]) == CONST_DOUBLE) |
7102 | { | |
7103 | HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); | |
dfbdccdb | 7104 | i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), |
9ebbca7d | 7105 | 0, DImode); |
dfbdccdb | 7106 | i4 = GEN_INT (value & 0xffff); |
9ebbca7d GK |
7107 | } |
7108 | else | |
7109 | { | |
dfbdccdb | 7110 | i3 = GEN_INT (INTVAL (operands[2]) |
9ebbca7d | 7111 | & (~ (HOST_WIDE_INT) 0xffff)); |
dfbdccdb | 7112 | i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); |
9ebbca7d | 7113 | } |
1c563bed | 7114 | operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, |
0f4c242b | 7115 | operands[1], i3); |
1c563bed | 7116 | operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, |
0f4c242b | 7117 | operands[0], i4); |
1fd4e8c1 RK |
7118 | }") |
7119 | ||
dfbdccdb | 7120 | (define_insn "*boolcdi3_internal1" |
9ebbca7d | 7121 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7122 | (match_operator:DI 3 "boolean_operator" |
7123 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7124 | (match_operand:DI 2 "gpc_reg_operand" "r")]))] |
a473029f | 7125 | "TARGET_POWERPC64" |
1d328b19 | 7126 | "%q3 %0,%2,%1") |
a473029f | 7127 | |
dfbdccdb | 7128 | (define_insn "*boolcdi3_internal2" |
9ebbca7d | 7129 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7130 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7131 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7132 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7133 | (const_int 0))) | |
9ebbca7d | 7134 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7135 | "TARGET_64BIT" |
9ebbca7d | 7136 | "@ |
1d328b19 | 7137 | %q4. %3,%2,%1 |
9ebbca7d GK |
7138 | #" |
7139 | [(set_attr "type" "compare") | |
7140 | (set_attr "length" "4,8")]) | |
7141 | ||
7142 | (define_split | |
7143 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7144 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7145 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7146 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7147 | (const_int 0))) |
9ebbca7d GK |
7148 | (clobber (match_scratch:DI 3 ""))] |
7149 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7150 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7151 | (set (match_dup 0) |
7152 | (compare:CC (match_dup 3) | |
7153 | (const_int 0)))] | |
7154 | "") | |
a473029f | 7155 | |
dfbdccdb | 7156 | (define_insn "*boolcdi3_internal3" |
9ebbca7d | 7157 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7158 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7159 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7160 | (match_operand:DI 2 "gpc_reg_operand" "r,r")]) | |
7161 | (const_int 0))) | |
9ebbca7d | 7162 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7163 | (match_dup 4))] |
683bdff7 | 7164 | "TARGET_64BIT" |
9ebbca7d | 7165 | "@ |
1d328b19 | 7166 | %q4. %0,%2,%1 |
9ebbca7d GK |
7167 | #" |
7168 | [(set_attr "type" "compare") | |
7169 | (set_attr "length" "4,8")]) | |
7170 | ||
7171 | (define_split | |
e72247f4 | 7172 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7173 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7174 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7175 | (match_operand:DI 2 "gpc_reg_operand" "")]) | |
dfbdccdb | 7176 | (const_int 0))) |
75540af0 | 7177 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7178 | (match_dup 4))] |
9ebbca7d | 7179 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7180 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7181 | (set (match_dup 3) |
7182 | (compare:CC (match_dup 0) | |
7183 | (const_int 0)))] | |
7184 | "") | |
266eb58a | 7185 | |
dfbdccdb | 7186 | (define_insn "*boolccdi3_internal1" |
a473029f | 7187 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
dfbdccdb GK |
7188 | (match_operator:DI 3 "boolean_operator" |
7189 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) | |
40501e5f | 7190 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))] |
a473029f | 7191 | "TARGET_POWERPC64" |
dfbdccdb | 7192 | "%q3 %0,%1,%2") |
a473029f | 7193 | |
dfbdccdb | 7194 | (define_insn "*boolccdi3_internal2" |
9ebbca7d | 7195 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7196 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7197 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) | |
7198 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7199 | (const_int 0))) | |
9ebbca7d | 7200 | (clobber (match_scratch:DI 3 "=r,r"))] |
683bdff7 | 7201 | "TARGET_64BIT" |
9ebbca7d | 7202 | "@ |
dfbdccdb | 7203 | %q4. %3,%1,%2 |
9ebbca7d GK |
7204 | #" |
7205 | [(set_attr "type" "compare") | |
7206 | (set_attr "length" "4,8")]) | |
7207 | ||
7208 | (define_split | |
7209 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
dfbdccdb | 7210 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7211 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7212 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7213 | (const_int 0))) |
9ebbca7d GK |
7214 | (clobber (match_scratch:DI 3 ""))] |
7215 | "TARGET_POWERPC64 && reload_completed" | |
dfbdccdb | 7216 | [(set (match_dup 3) (match_dup 4)) |
9ebbca7d GK |
7217 | (set (match_dup 0) |
7218 | (compare:CC (match_dup 3) | |
7219 | (const_int 0)))] | |
7220 | "") | |
266eb58a | 7221 | |
dfbdccdb | 7222 | (define_insn "*boolccdi3_internal3" |
9ebbca7d | 7223 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
dfbdccdb GK |
7224 | (compare:CC (match_operator:DI 4 "boolean_operator" |
7225 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) | |
7226 | (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) | |
7227 | (const_int 0))) | |
9ebbca7d | 7228 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
dfbdccdb | 7229 | (match_dup 4))] |
683bdff7 | 7230 | "TARGET_64BIT" |
9ebbca7d | 7231 | "@ |
dfbdccdb | 7232 | %q4. %0,%1,%2 |
9ebbca7d GK |
7233 | #" |
7234 | [(set_attr "type" "compare") | |
7235 | (set_attr "length" "4,8")]) | |
7236 | ||
7237 | (define_split | |
e72247f4 | 7238 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
dfbdccdb | 7239 | (compare:CC (match_operator:DI 4 "boolean_operator" |
75540af0 JH |
7240 | [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) |
7241 | (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) | |
dfbdccdb | 7242 | (const_int 0))) |
75540af0 | 7243 | (set (match_operand:DI 0 "gpc_reg_operand" "") |
dfbdccdb | 7244 | (match_dup 4))] |
9ebbca7d | 7245 | "TARGET_POWERPC64 && reload_completed" |
dfbdccdb | 7246 | [(set (match_dup 0) (match_dup 4)) |
9ebbca7d GK |
7247 | (set (match_dup 3) |
7248 | (compare:CC (match_dup 0) | |
7249 | (const_int 0)))] | |
7250 | "") | |
dfbdccdb | 7251 | \f |
1fd4e8c1 | 7252 | ;; Now define ways of moving data around. |
4697a36c | 7253 | |
766a866c MM |
7254 | ;; Set up a register with a value from the GOT table |
7255 | ||
7256 | (define_expand "movsi_got" | |
52d3af72 | 7257 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7258 | (unspec:SI [(match_operand:SI 1 "got_operand" "") |
615158e2 | 7259 | (match_dup 2)] UNSPEC_MOVSI_GOT))] |
f607bc57 | 7260 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7261 | " |
7262 | { | |
38c1f2d7 MM |
7263 | if (GET_CODE (operands[1]) == CONST) |
7264 | { | |
7265 | rtx offset = const0_rtx; | |
7266 | HOST_WIDE_INT value; | |
7267 | ||
7268 | operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); | |
7269 | value = INTVAL (offset); | |
7270 | if (value != 0) | |
7271 | { | |
677a9668 | 7272 | rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode)); |
38c1f2d7 MM |
7273 | emit_insn (gen_movsi_got (tmp, operands[1])); |
7274 | emit_insn (gen_addsi3 (operands[0], tmp, offset)); | |
7275 | DONE; | |
7276 | } | |
7277 | } | |
7278 | ||
c4c40373 | 7279 | operands[2] = rs6000_got_register (operands[1]); |
766a866c MM |
7280 | }") |
7281 | ||
84f414bc | 7282 | (define_insn "*movsi_got_internal" |
52d3af72 | 7283 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9ebbca7d | 7284 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
615158e2 JJ |
7285 | (match_operand:SI 2 "gpc_reg_operand" "b")] |
7286 | UNSPEC_MOVSI_GOT))] | |
f607bc57 | 7287 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1" |
766a866c MM |
7288 | "{l|lwz} %0,%a1@got(%2)" |
7289 | [(set_attr "type" "load")]) | |
7290 | ||
b22b9b3e JL |
7291 | ;; Used by sched, shorten_branches and final when the GOT pseudo reg |
7292 | ;; didn't get allocated to a hard register. | |
6ae08853 | 7293 | (define_split |
75540af0 | 7294 | [(set (match_operand:SI 0 "gpc_reg_operand" "") |
9ebbca7d | 7295 | (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") |
615158e2 JJ |
7296 | (match_operand:SI 2 "memory_operand" "")] |
7297 | UNSPEC_MOVSI_GOT))] | |
f607bc57 | 7298 | "DEFAULT_ABI == ABI_V4 |
b22b9b3e JL |
7299 | && flag_pic == 1 |
7300 | && (reload_in_progress || reload_completed)" | |
7301 | [(set (match_dup 0) (match_dup 2)) | |
615158e2 JJ |
7302 | (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] |
7303 | UNSPEC_MOVSI_GOT))] | |
b22b9b3e JL |
7304 | "") |
7305 | ||
1fd4e8c1 RK |
7306 | ;; For SI, we special-case integers that can't be loaded in one insn. We |
7307 | ;; do the load 16-bits at a time. We could do this by loading from memory, | |
7308 | ;; and this is even supposed to be faster, but it is simpler not to get | |
7309 | ;; integers in the TOC. | |
ee890fe2 SS |
7310 | (define_insn "movsi_low" |
7311 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
f585a356 | 7312 | (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
ee890fe2 SS |
7313 | (match_operand 2 "" ""))))] |
7314 | "TARGET_MACHO && ! TARGET_64BIT" | |
7315 | "{l|lwz} %0,lo16(%2)(%1)" | |
7316 | [(set_attr "type" "load") | |
7317 | (set_attr "length" "4")]) | |
7318 | ||
acad7ed3 | 7319 | (define_insn "*movsi_internal1" |
165a5bad | 7320 | [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h") |
a004eb82 | 7321 | (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))] |
19d5775a RK |
7322 | "gpc_reg_operand (operands[0], SImode) |
7323 | || gpc_reg_operand (operands[1], SImode)" | |
1fd4e8c1 | 7324 | "@ |
deb9225a | 7325 | mr %0,%1 |
b9442c72 | 7326 | {cal|la} %0,%a1 |
ca7f5001 RK |
7327 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7328 | {st%U0%X0|stw%U0%X0} %1,%0 | |
19d5775a | 7329 | {lil|li} %0,%1 |
802a0058 | 7330 | {liu|lis} %0,%v1 |
beaec479 | 7331 | # |
aee86b38 | 7332 | {cal|la} %0,%a1 |
1fd4e8c1 | 7333 | mf%1 %0 |
5c23c401 | 7334 | mt%0 %1 |
e76e75bb | 7335 | mt%0 %1 |
a004eb82 | 7336 | mt%0 %1 |
e34eaae5 | 7337 | {cror 0,0,0|nop}" |
02ca7595 | 7338 | [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*") |
a004eb82 | 7339 | (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) |
1fd4e8c1 | 7340 | |
77fa0940 RK |
7341 | ;; Split a load of a large constant into the appropriate two-insn |
7342 | ;; sequence. | |
7343 | ||
7344 | (define_split | |
7345 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
7346 | (match_operand:SI 1 "const_int_operand" ""))] | |
bb21487f | 7347 | "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 |
77fa0940 RK |
7348 | && (INTVAL (operands[1]) & 0xffff) != 0" |
7349 | [(set (match_dup 0) | |
7350 | (match_dup 2)) | |
7351 | (set (match_dup 0) | |
7352 | (ior:SI (match_dup 0) | |
7353 | (match_dup 3)))] | |
7354 | " | |
af8cb5c5 DE |
7355 | { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2); |
7356 | ||
7357 | if (tem == operands[0]) | |
7358 | DONE; | |
7359 | else | |
7360 | FAIL; | |
77fa0940 RK |
7361 | }") |
7362 | ||
4ae234b0 | 7363 | (define_insn "*mov<mode>_internal2" |
bb84cb12 | 7364 | [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") |
4ae234b0 | 7365 | (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r") |
1fd4e8c1 | 7366 | (const_int 0))) |
4ae234b0 GK |
7367 | (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] |
7368 | "" | |
9ebbca7d | 7369 | "@ |
4ae234b0 | 7370 | {cmpi|cmp<wd>i} %2,%0,0 |
9ebbca7d GK |
7371 | mr. %0,%1 |
7372 | #" | |
bb84cb12 DE |
7373 | [(set_attr "type" "cmp,compare,cmp") |
7374 | (set_attr "length" "4,4,8")]) | |
7375 | ||
9ebbca7d GK |
7376 | (define_split |
7377 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
4ae234b0 | 7378 | (compare:CC (match_operand:P 1 "gpc_reg_operand" "") |
9ebbca7d | 7379 | (const_int 0))) |
4ae234b0 GK |
7380 | (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))] |
7381 | "reload_completed" | |
9ebbca7d GK |
7382 | [(set (match_dup 0) (match_dup 1)) |
7383 | (set (match_dup 2) | |
7384 | (compare:CC (match_dup 0) | |
7385 | (const_int 0)))] | |
7386 | "") | |
bb84cb12 | 7387 | \f |
e34eaae5 | 7388 | (define_insn "*movhi_internal" |
fb81d7ce RK |
7389 | [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7390 | (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7391 | "gpc_reg_operand (operands[0], HImode) |
7392 | || gpc_reg_operand (operands[1], HImode)" | |
1fd4e8c1 | 7393 | "@ |
deb9225a | 7394 | mr %0,%1 |
1fd4e8c1 RK |
7395 | lhz%U1%X1 %0,%1 |
7396 | sth%U0%X0 %1,%0 | |
19d5775a | 7397 | {lil|li} %0,%w1 |
1fd4e8c1 | 7398 | mf%1 %0 |
e76e75bb | 7399 | mt%0 %1 |
fb81d7ce | 7400 | mt%0 %1 |
e34eaae5 | 7401 | {cror 0,0,0|nop}" |
02ca7595 | 7402 | [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) |
1fd4e8c1 | 7403 | |
4ae234b0 GK |
7404 | (define_expand "mov<mode>" |
7405 | [(set (match_operand:INT 0 "general_operand" "") | |
7406 | (match_operand:INT 1 "any_operand" ""))] | |
1fd4e8c1 | 7407 | "" |
4ae234b0 | 7408 | "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }") |
1fd4e8c1 | 7409 | |
e34eaae5 | 7410 | (define_insn "*movqi_internal" |
fb81d7ce RK |
7411 | [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") |
7412 | (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] | |
19d5775a RK |
7413 | "gpc_reg_operand (operands[0], QImode) |
7414 | || gpc_reg_operand (operands[1], QImode)" | |
1fd4e8c1 | 7415 | "@ |
deb9225a | 7416 | mr %0,%1 |
1fd4e8c1 RK |
7417 | lbz%U1%X1 %0,%1 |
7418 | stb%U0%X0 %1,%0 | |
19d5775a | 7419 | {lil|li} %0,%1 |
1fd4e8c1 | 7420 | mf%1 %0 |
e76e75bb | 7421 | mt%0 %1 |
fb81d7ce | 7422 | mt%0 %1 |
e34eaae5 | 7423 | {cror 0,0,0|nop}" |
02ca7595 | 7424 | [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")]) |
1fd4e8c1 RK |
7425 | \f |
7426 | ;; Here is how to move condition codes around. When we store CC data in | |
7427 | ;; an integer register or memory, we store just the high-order 4 bits. | |
7428 | ;; This lets us not shift in the most common case of CR0. | |
7429 | (define_expand "movcc" | |
7430 | [(set (match_operand:CC 0 "nonimmediate_operand" "") | |
7431 | (match_operand:CC 1 "nonimmediate_operand" ""))] | |
7432 | "" | |
7433 | "") | |
7434 | ||
a65c591c | 7435 | (define_insn "*movcc_internal1" |
b54cf83a DE |
7436 | [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,r,r,r,r,q,cl,r,m") |
7437 | (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,h,r,r,m,r"))] | |
1fd4e8c1 RK |
7438 | "register_operand (operands[0], CCmode) |
7439 | || register_operand (operands[1], CCmode)" | |
7440 | "@ | |
7441 | mcrf %0,%1 | |
7442 | mtcrf 128,%1 | |
ca7f5001 | 7443 | {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff |
2c4a9cff DE |
7444 | mfcr %0%Q1 |
7445 | mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 | |
deb9225a | 7446 | mr %0,%1 |
b54cf83a | 7447 | mf%1 %0 |
b991a865 GK |
7448 | mt%0 %1 |
7449 | mt%0 %1 | |
ca7f5001 RK |
7450 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7451 | {st%U0%U1|stw%U0%U1} %1,%0" | |
2c4a9cff DE |
7452 | [(set (attr "type") |
7453 | (cond [(eq_attr "alternative" "0") | |
7454 | (const_string "cr_logical") | |
7455 | (eq_attr "alternative" "1,2") | |
7456 | (const_string "mtcr") | |
7457 | (eq_attr "alternative" "5,7") | |
7458 | (const_string "integer") | |
7459 | (eq_attr "alternative" "6") | |
7460 | (const_string "mfjmpr") | |
7461 | (eq_attr "alternative" "8") | |
7462 | (const_string "mtjmpr") | |
7463 | (eq_attr "alternative" "9") | |
7464 | (const_string "load") | |
7465 | (eq_attr "alternative" "10") | |
7466 | (const_string "store") | |
7467 | (ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
7468 | (const_string "mfcrf") | |
7469 | ] | |
7470 | (const_string "mfcr"))) | |
b991a865 | 7471 | (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")]) |
1fd4e8c1 | 7472 | \f |
e52e05ca MM |
7473 | ;; For floating-point, we normally deal with the floating-point registers |
7474 | ;; unless -msoft-float is used. The sole exception is that parameter passing | |
7475 | ;; can produce floating-point values in fixed-point registers. Unless the | |
7476 | ;; value is a simple constant or already in memory, we deal with this by | |
7477 | ;; allocating memory and copying the value explicitly via that memory location. | |
1fd4e8c1 RK |
7478 | (define_expand "movsf" |
7479 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
7480 | (match_operand:SF 1 "any_operand" ""))] | |
7481 | "" | |
fb4d4348 | 7482 | "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }") |
1fd4e8c1 | 7483 | |
1fd4e8c1 | 7484 | (define_split |
cd2b37d9 | 7485 | [(set (match_operand:SF 0 "gpc_reg_operand" "") |
c4c40373 | 7486 | (match_operand:SF 1 "const_double_operand" ""))] |
f99f88e0 | 7487 | "reload_completed |
5ae4759c MM |
7488 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7489 | || (GET_CODE (operands[0]) == SUBREG | |
7490 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7491 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 | 7492 | [(set (match_dup 2) (match_dup 3))] |
685f3906 DE |
7493 | " |
7494 | { | |
7495 | long l; | |
7496 | REAL_VALUE_TYPE rv; | |
7497 | ||
7498 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7499 | REAL_VALUE_TO_TARGET_SINGLE (rv, l); | |
c4c40373 | 7500 | |
f99f88e0 DE |
7501 | if (! TARGET_POWERPC64) |
7502 | operands[2] = operand_subword (operands[0], 0, 0, SFmode); | |
7503 | else | |
7504 | operands[2] = gen_lowpart (SImode, operands[0]); | |
a260abc9 | 7505 | |
2496c7bd | 7506 | operands[3] = gen_int_mode (l, SImode); |
a260abc9 DE |
7507 | }") |
7508 | ||
c4c40373 | 7509 | (define_insn "*movsf_hardfloat" |
ae6669e7 DJ |
7510 | [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r") |
7511 | (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))] | |
d14a6d05 | 7512 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
7513 | || gpc_reg_operand (operands[1], SFmode)) |
7514 | && (TARGET_HARD_FLOAT && TARGET_FPRS)" | |
1fd4e8c1 | 7515 | "@ |
f99f88e0 DE |
7516 | mr %0,%1 |
7517 | {l%U1%X1|lwz%U1%X1} %0,%1 | |
7518 | {st%U0%X0|stw%U0%X0} %1,%0 | |
1fd4e8c1 RK |
7519 | fmr %0,%1 |
7520 | lfs%U1%X1 %0,%1 | |
c4c40373 | 7521 | stfs%U0%X0 %1,%0 |
b991a865 GK |
7522 | mt%0 %1 |
7523 | mt%0 %1 | |
7524 | mf%1 %0 | |
e0740893 | 7525 | {cror 0,0,0|nop} |
c4c40373 MM |
7526 | # |
7527 | #" | |
ae6669e7 DJ |
7528 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*") |
7529 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")]) | |
d14a6d05 | 7530 | |
c4c40373 | 7531 | (define_insn "*movsf_softfloat" |
dd0fbae2 MK |
7532 | [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h") |
7533 | (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))] | |
d14a6d05 | 7534 | "(gpc_reg_operand (operands[0], SFmode) |
a3170dc6 AH |
7535 | || gpc_reg_operand (operands[1], SFmode)) |
7536 | && (TARGET_SOFT_FLOAT || !TARGET_FPRS)" | |
d14a6d05 MM |
7537 | "@ |
7538 | mr %0,%1 | |
b991a865 GK |
7539 | mt%0 %1 |
7540 | mt%0 %1 | |
7541 | mf%1 %0 | |
d14a6d05 MM |
7542 | {l%U1%X1|lwz%U1%X1} %0,%1 |
7543 | {st%U0%X0|stw%U0%X0} %1,%0 | |
7544 | {lil|li} %0,%1 | |
802a0058 | 7545 | {liu|lis} %0,%v1 |
aee86b38 | 7546 | {cal|la} %0,%a1 |
c4c40373 | 7547 | # |
dd0fbae2 MK |
7548 | # |
7549 | {cror 0,0,0|nop}" | |
7550 | [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*") | |
7551 | (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")]) | |
d14a6d05 | 7552 | |
1fd4e8c1 RK |
7553 | \f |
7554 | (define_expand "movdf" | |
7555 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
7556 | (match_operand:DF 1 "any_operand" ""))] | |
7557 | "" | |
fb4d4348 | 7558 | "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }") |
1fd4e8c1 RK |
7559 | |
7560 | (define_split | |
cd2b37d9 | 7561 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
c4c40373 | 7562 | (match_operand:DF 1 "const_int_operand" ""))] |
a260abc9 | 7563 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7564 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7565 | || (GET_CODE (operands[0]) == SUBREG | |
7566 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7567 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7568 | [(set (match_dup 2) (match_dup 4)) |
7569 | (set (match_dup 3) (match_dup 1))] | |
7570 | " | |
7571 | { | |
5ae4759c | 7572 | int endian = (WORDS_BIG_ENDIAN == 0); |
5f59ecb7 DE |
7573 | HOST_WIDE_INT value = INTVAL (operands[1]); |
7574 | ||
5ae4759c MM |
7575 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7576 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
5f59ecb7 DE |
7577 | #if HOST_BITS_PER_WIDE_INT == 32 |
7578 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; | |
7579 | #else | |
7580 | operands[4] = GEN_INT (value >> 32); | |
a65c591c | 7581 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
5f59ecb7 | 7582 | #endif |
c4c40373 MM |
7583 | }") |
7584 | ||
c4c40373 MM |
7585 | (define_split |
7586 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
7587 | (match_operand:DF 1 "const_double_operand" ""))] | |
a260abc9 | 7588 | "! TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7589 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7590 | || (GET_CODE (operands[0]) == SUBREG | |
7591 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7592 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
c4c40373 MM |
7593 | [(set (match_dup 2) (match_dup 4)) |
7594 | (set (match_dup 3) (match_dup 5))] | |
7595 | " | |
7596 | { | |
5ae4759c | 7597 | int endian = (WORDS_BIG_ENDIAN == 0); |
47ad8c61 MM |
7598 | long l[2]; |
7599 | REAL_VALUE_TYPE rv; | |
7600 | ||
7601 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7602 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7603 | ||
5ae4759c MM |
7604 | operands[2] = operand_subword (operands[0], endian, 0, DFmode); |
7605 | operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); | |
2496c7bd LB |
7606 | operands[4] = gen_int_mode (l[endian], SImode); |
7607 | operands[5] = gen_int_mode (l[1 - endian], SImode); | |
c4c40373 MM |
7608 | }") |
7609 | ||
efc08378 DE |
7610 | (define_split |
7611 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
685f3906 | 7612 | (match_operand:DF 1 "easy_fp_constant" ""))] |
a260abc9 | 7613 | "TARGET_POWERPC64 && reload_completed |
5ae4759c MM |
7614 | && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) |
7615 | || (GET_CODE (operands[0]) == SUBREG | |
7616 | && GET_CODE (SUBREG_REG (operands[0])) == REG | |
7617 | && REGNO (SUBREG_REG (operands[0])) <= 31))" | |
a260abc9 | 7618 | [(set (match_dup 2) (match_dup 3))] |
5ae4759c | 7619 | " |
a260abc9 DE |
7620 | { |
7621 | int endian = (WORDS_BIG_ENDIAN == 0); | |
7622 | long l[2]; | |
7623 | REAL_VALUE_TYPE rv; | |
4977bab6 | 7624 | #if HOST_BITS_PER_WIDE_INT >= 64 |
5b029315 | 7625 | HOST_WIDE_INT val; |
4977bab6 | 7626 | #endif |
a260abc9 DE |
7627 | |
7628 | REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); | |
7629 | REAL_VALUE_TO_TARGET_DOUBLE (rv, l); | |
7630 | ||
7631 | operands[2] = gen_lowpart (DImode, operands[0]); | |
7632 | /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ | |
5b029315 | 7633 | #if HOST_BITS_PER_WIDE_INT >= 64 |
a2419b96 DE |
7634 | val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 |
7635 | | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); | |
5b029315 | 7636 | |
f5264b52 | 7637 | operands[3] = gen_int_mode (val, DImode); |
5b029315 | 7638 | #else |
a260abc9 | 7639 | operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); |
5b029315 | 7640 | #endif |
a260abc9 | 7641 | }") |
efc08378 | 7642 | |
4eae5fe1 | 7643 | ;; Don't have reload use general registers to load a constant. First, |
1427100a | 7644 | ;; it might not work if the output operand is the equivalent of |
4eae5fe1 RK |
7645 | ;; a non-offsettable memref, but also it is less efficient than loading |
7646 | ;; the constant into an FP register, since it will probably be used there. | |
7647 | ;; The "??" is a kludge until we can figure out a more reasonable way | |
7648 | ;; of handling these non-offsettable values. | |
c4c40373 | 7649 | (define_insn "*movdf_hardfloat32" |
914a7297 DE |
7650 | [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") |
7651 | (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] | |
a3170dc6 | 7652 | "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
7653 | && (gpc_reg_operand (operands[0], DFmode) |
7654 | || gpc_reg_operand (operands[1], DFmode))" | |
e7113111 RK |
7655 | "* |
7656 | { | |
7657 | switch (which_alternative) | |
7658 | { | |
a260abc9 | 7659 | default: |
37409796 | 7660 | gcc_unreachable (); |
e7113111 RK |
7661 | case 0: |
7662 | /* We normally copy the low-numbered register first. However, if | |
000034eb DE |
7663 | the first register operand 0 is the same as the second register |
7664 | of operand 1, we must copy in the opposite order. */ | |
e7113111 | 7665 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) |
deb9225a | 7666 | return \"mr %L0,%L1\;mr %0,%1\"; |
e7113111 | 7667 | else |
deb9225a | 7668 | return \"mr %0,%1\;mr %L0,%L1\"; |
e7113111 | 7669 | case 1: |
819e019c EC |
7670 | if (GET_CODE (operands[1]) == MEM |
7671 | && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[1], 0), | |
7672 | reload_completed || reload_in_progress) | |
7673 | || GET_CODE (XEXP (operands[1], 0)) == REG | |
7674 | || GET_CODE (XEXP (operands[1], 0)) == LO_SUM | |
69f51a21 | 7675 | || GET_CODE (XEXP (operands[1], 0)) == PRE_INC |
819e019c | 7676 | || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)) |
000034eb DE |
7677 | { |
7678 | /* If the low-address word is used in the address, we must load | |
7679 | it last. Otherwise, load it first. Note that we cannot have | |
7680 | auto-increment in that case since the address register is | |
7681 | known to be dead. */ | |
7682 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
7683 | operands[1], 0)) | |
7684 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
7685 | else | |
7686 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
7687 | } | |
e7113111 | 7688 | else |
000034eb DE |
7689 | { |
7690 | rtx addreg; | |
7691 | ||
000034eb DE |
7692 | addreg = find_addr_reg (XEXP (operands[1], 0)); |
7693 | if (refers_to_regno_p (REGNO (operands[0]), | |
7694 | REGNO (operands[0]) + 1, | |
7695 | operands[1], 0)) | |
7696 | { | |
7697 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); | |
2b97222d | 7698 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb | 7699 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
2b97222d | 7700 | return \"{lx|lwzx} %0,%1\"; |
000034eb DE |
7701 | } |
7702 | else | |
7703 | { | |
2b97222d | 7704 | output_asm_insn (\"{lx|lwzx} %0,%1\", operands); |
000034eb | 7705 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 7706 | output_asm_insn (\"{lx|lwzx} %L0,%1\", operands); |
000034eb DE |
7707 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
7708 | return \"\"; | |
7709 | } | |
7710 | } | |
e7113111 | 7711 | case 2: |
819e019c EC |
7712 | if (GET_CODE (operands[0]) == MEM |
7713 | && (rs6000_legitimate_offset_address_p (DFmode, XEXP (operands[0], 0), | |
7714 | reload_completed || reload_in_progress) | |
7715 | || GET_CODE (XEXP (operands[0], 0)) == REG | |
7716 | || GET_CODE (XEXP (operands[0], 0)) == LO_SUM | |
69f51a21 | 7717 | || GET_CODE (XEXP (operands[0], 0)) == PRE_INC |
819e019c | 7718 | || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)) |
000034eb DE |
7719 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; |
7720 | else | |
7721 | { | |
7722 | rtx addreg; | |
7723 | ||
000034eb | 7724 | addreg = find_addr_reg (XEXP (operands[0], 0)); |
2b97222d | 7725 | output_asm_insn (\"{stx|stwx} %1,%0\", operands); |
000034eb | 7726 | output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg); |
2b97222d | 7727 | output_asm_insn (\"{stx|stwx} %L1,%0\", operands); |
000034eb DE |
7728 | output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg); |
7729 | return \"\"; | |
7730 | } | |
e7113111 | 7731 | case 3: |
914a7297 | 7732 | return \"fmr %0,%1\"; |
e7113111 | 7733 | case 4: |
914a7297 | 7734 | return \"lfd%U1%X1 %0,%1\"; |
e7113111 | 7735 | case 5: |
914a7297 | 7736 | return \"stfd%U0%X0 %1,%0\"; |
e7113111 | 7737 | case 6: |
c4c40373 | 7738 | case 7: |
c4c40373 | 7739 | case 8: |
914a7297 | 7740 | return \"#\"; |
e7113111 RK |
7741 | } |
7742 | }" | |
943c15ed | 7743 | [(set_attr "type" "two,load,store,fp,fpload,fpstore,*,*,*") |
914a7297 | 7744 | (set_attr "length" "8,16,16,4,4,4,8,12,16")]) |
51b8fc2c | 7745 | |
c4c40373 | 7746 | (define_insn "*movdf_softfloat32" |
1427100a DE |
7747 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") |
7748 | (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] | |
7a2f7870 | 7749 | "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || TARGET_E500_SINGLE) |
52d3af72 DE |
7750 | && (gpc_reg_operand (operands[0], DFmode) |
7751 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca MM |
7752 | "* |
7753 | { | |
7754 | switch (which_alternative) | |
7755 | { | |
a260abc9 | 7756 | default: |
37409796 | 7757 | gcc_unreachable (); |
dc4f83ca MM |
7758 | case 0: |
7759 | /* We normally copy the low-numbered register first. However, if | |
7760 | the first register operand 0 is the same as the second register of | |
7761 | operand 1, we must copy in the opposite order. */ | |
7762 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
7763 | return \"mr %L0,%L1\;mr %0,%1\"; | |
7764 | else | |
7765 | return \"mr %0,%1\;mr %L0,%L1\"; | |
7766 | case 1: | |
3cb999d8 DE |
7767 | /* If the low-address word is used in the address, we must load |
7768 | it last. Otherwise, load it first. Note that we cannot have | |
7769 | auto-increment in that case since the address register is | |
7770 | known to be dead. */ | |
dc4f83ca | 7771 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, |
3cb999d8 | 7772 | operands[1], 0)) |
dc4f83ca MM |
7773 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; |
7774 | else | |
7775 | return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\"; | |
7776 | case 2: | |
7777 | return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\"; | |
7778 | case 3: | |
c4c40373 MM |
7779 | case 4: |
7780 | case 5: | |
dc4f83ca MM |
7781 | return \"#\"; |
7782 | } | |
7783 | }" | |
943c15ed | 7784 | [(set_attr "type" "two,load,store,*,*,*") |
c4c40373 | 7785 | (set_attr "length" "8,8,8,8,12,16")]) |
dc4f83ca | 7786 | |
d2288d5d HP |
7787 | ; ld/std require word-aligned displacements -> 'Y' constraint. |
7788 | ; List Y->r and r->Y before r->r for reload. | |
c4c40373 | 7789 | (define_insn "*movdf_hardfloat64" |
ae6669e7 DJ |
7790 | [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r") |
7791 | (match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))] | |
a3170dc6 | 7792 | "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS |
52d3af72 DE |
7793 | && (gpc_reg_operand (operands[0], DFmode) |
7794 | || gpc_reg_operand (operands[1], DFmode))" | |
51b8fc2c | 7795 | "@ |
96bb8ed3 | 7796 | std%U0%X0 %1,%0 |
3364872d FJ |
7797 | ld%U1%X1 %0,%1 |
7798 | mr %0,%1 | |
3d5570cb | 7799 | fmr %0,%1 |
f63184ac | 7800 | lfd%U1%X1 %0,%1 |
914a7297 DE |
7801 | stfd%U0%X0 %1,%0 |
7802 | mt%0 %1 | |
7803 | mf%1 %0 | |
e0740893 | 7804 | {cror 0,0,0|nop} |
914a7297 DE |
7805 | # |
7806 | # | |
7807 | #" | |
ae6669e7 DJ |
7808 | [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*") |
7809 | (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")]) | |
dc4f83ca | 7810 | |
c4c40373 | 7811 | (define_insn "*movdf_softfloat64" |
d2288d5d HP |
7812 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h") |
7813 | (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))] | |
a3170dc6 | 7814 | "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) |
52d3af72 DE |
7815 | && (gpc_reg_operand (operands[0], DFmode) |
7816 | || gpc_reg_operand (operands[1], DFmode))" | |
dc4f83ca | 7817 | "@ |
d2288d5d HP |
7818 | ld%U1%X1 %0,%1 |
7819 | std%U0%X0 %1,%0 | |
dc4f83ca | 7820 | mr %0,%1 |
914a7297 DE |
7821 | mt%0 %1 |
7822 | mf%1 %0 | |
c4c40373 MM |
7823 | # |
7824 | # | |
e2d0915c | 7825 | # |
e0740893 | 7826 | {cror 0,0,0|nop}" |
d2288d5d | 7827 | [(set_attr "type" "load,store,*,*,*,*,*,*,*") |
e2d0915c | 7828 | (set_attr "length" "4,4,4,4,4,8,12,16,4")]) |
1fd4e8c1 | 7829 | \f |
06f4e019 DE |
7830 | (define_expand "movtf" |
7831 | [(set (match_operand:TF 0 "general_operand" "") | |
7832 | (match_operand:TF 1 "any_operand" ""))] | |
39e63627 GK |
7833 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7834 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
7835 | "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }") |
7836 | ||
a9baceb1 GK |
7837 | ; It's important to list the o->f and f->o moves before f->f because |
7838 | ; otherwise reload, given m->f, will try to pick f->f and reload it, | |
409f61cd | 7839 | ; which doesn't make progress. Likewise r->Y must be before r->r. |
a9baceb1 | 7840 | (define_insn_and_split "*movtf_internal" |
409f61cd AM |
7841 | [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,f,r,Y,r") |
7842 | (match_operand:TF 1 "input_operand" "f,o,f,YGHF,r,r"))] | |
39e63627 GK |
7843 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7844 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128 | |
06f4e019 DE |
7845 | && (gpc_reg_operand (operands[0], TFmode) |
7846 | || gpc_reg_operand (operands[1], TFmode))" | |
a9baceb1 | 7847 | "#" |
ecb62ae7 | 7848 | "&& reload_completed" |
a9baceb1 GK |
7849 | [(pc)] |
7850 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; } | |
112ccb83 | 7851 | [(set_attr "length" "8,8,8,20,20,16")]) |
06f4e019 | 7852 | |
ecb62ae7 GK |
7853 | (define_expand "extenddftf2" |
7854 | [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
7855 | (float_extend:TF (match_operand:DF 1 "input_operand" ""))) | |
7856 | (use (match_dup 2))])] | |
39e63627 GK |
7857 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7858 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 7859 | { |
ecb62ae7 GK |
7860 | operands[2] = CONST0_RTX (DFmode); |
7861 | }) | |
06f4e019 | 7862 | |
ecb62ae7 GK |
7863 | (define_insn_and_split "*extenddftf2_internal" |
7864 | [(set (match_operand:TF 0 "nonimmediate_operand" "=o,f,&f,r") | |
7865 | (float_extend:TF (match_operand:DF 1 "input_operand" "fr,mf,mf,rmGHF"))) | |
97c54d9a | 7866 | (use (match_operand:DF 2 "zero_reg_mem_operand" "rf,m,f,n"))] |
39e63627 GK |
7867 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7868 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
ecb62ae7 GK |
7869 | "#" |
7870 | "&& reload_completed" | |
7871 | [(pc)] | |
06f4e019 | 7872 | { |
ecb62ae7 GK |
7873 | const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; |
7874 | const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); | |
7875 | emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word), | |
7876 | operands[1]); | |
7877 | emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word), | |
7878 | operands[2]); | |
7879 | DONE; | |
6ae08853 | 7880 | }) |
ecb62ae7 GK |
7881 | |
7882 | (define_expand "extendsftf2" | |
7883 | [(set (match_operand:TF 0 "nonimmediate_operand" "") | |
7884 | (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))] | |
7885 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
7886 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
7887 | { | |
7888 | rtx tmp = gen_reg_rtx (DFmode); | |
7889 | emit_insn (gen_extendsfdf2 (tmp, operands[1])); | |
7890 | emit_insn (gen_extenddftf2 (operands[0], tmp)); | |
7891 | DONE; | |
7892 | }) | |
06f4e019 | 7893 | |
8cb320b8 | 7894 | (define_expand "trunctfdf2" |
589b3fda DE |
7895 | [(set (match_operand:DF 0 "gpc_reg_operand" "") |
7896 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))] | |
39e63627 GK |
7897 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7898 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
589b3fda | 7899 | "") |
8cb320b8 DE |
7900 | |
7901 | (define_insn_and_split "trunctfdf2_internal1" | |
7902 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f") | |
7903 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,f")))] | |
7904 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT | |
7905 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
7906 | "@ | |
7907 | # | |
7908 | fmr %0,%1" | |
7909 | "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])" | |
7910 | [(const_int 0)] | |
7911 | { | |
7912 | emit_note (NOTE_INSN_DELETED); | |
7913 | DONE; | |
7914 | } | |
7915 | [(set_attr "type" "fp")]) | |
7916 | ||
7917 | (define_insn "trunctfdf2_internal2" | |
7918 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
7919 | (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
7920 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT | |
7921 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 7922 | "fadd %0,%1,%L1" |
8cb320b8 | 7923 | [(set_attr "type" "fp")]) |
06f4e019 DE |
7924 | |
7925 | (define_insn_and_split "trunctfsf2" | |
7926 | [(set (match_operand:SF 0 "gpc_reg_operand" "=f") | |
ea112fc4 DE |
7927 | (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f"))) |
7928 | (clobber (match_scratch:DF 2 "=f"))] | |
39e63627 GK |
7929 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7930 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 | 7931 | "#" |
ea112fc4 | 7932 | "&& reload_completed" |
06f4e019 DE |
7933 | [(set (match_dup 2) |
7934 | (float_truncate:DF (match_dup 1))) | |
7935 | (set (match_dup 0) | |
7936 | (float_truncate:SF (match_dup 2)))] | |
ea112fc4 | 7937 | "") |
06f4e019 | 7938 | |
0c90aa3c | 7939 | (define_expand "floatsitf2" |
ea112fc4 | 7940 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
0c90aa3c | 7941 | (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))] |
39e63627 GK |
7942 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7943 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
0c90aa3c GK |
7944 | { |
7945 | rtx tmp = gen_reg_rtx (DFmode); | |
7946 | expand_float (tmp, operands[1], false); | |
7947 | emit_insn (gen_extenddftf2 (operands[0], tmp)); | |
7948 | DONE; | |
7949 | }) | |
06f4e019 | 7950 | |
ecb62ae7 GK |
7951 | ; fadd, but rounding towards zero. |
7952 | ; This is probably not the optimal code sequence. | |
7953 | (define_insn "fix_trunc_helper" | |
7954 | [(set (match_operand:DF 0 "gpc_reg_operand" "=f") | |
7955 | (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "f")] | |
7956 | UNSPEC_FIX_TRUNC_TF)) | |
7957 | (clobber (match_operand:DF 2 "gpc_reg_operand" "=&f"))] | |
7958 | "TARGET_HARD_FLOAT && TARGET_FPRS" | |
7959 | "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2" | |
7960 | [(set_attr "type" "fp") | |
7961 | (set_attr "length" "20")]) | |
7962 | ||
0c90aa3c | 7963 | (define_expand "fix_trunctfsi2" |
ecb62ae7 GK |
7964 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") |
7965 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" ""))) | |
7966 | (clobber (match_dup 2)) | |
7967 | (clobber (match_dup 3)) | |
7968 | (clobber (match_dup 4)) | |
7969 | (clobber (match_dup 5))])] | |
7970 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) | |
7971 | && (TARGET_POWER2 || TARGET_POWERPC) | |
7972 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
7973 | { | |
7974 | operands[2] = gen_reg_rtx (DFmode); | |
7975 | operands[3] = gen_reg_rtx (DFmode); | |
7976 | operands[4] = gen_reg_rtx (DImode); | |
7977 | operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0); | |
7978 | }) | |
7979 | ||
7980 | (define_insn_and_split "*fix_trunctfsi2_internal" | |
61c07d3c | 7981 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
ecb62ae7 GK |
7982 | (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f"))) |
7983 | (clobber (match_operand:DF 2 "gpc_reg_operand" "=f")) | |
7984 | (clobber (match_operand:DF 3 "gpc_reg_operand" "=&f")) | |
7985 | (clobber (match_operand:DI 4 "gpc_reg_operand" "=f")) | |
7986 | (clobber (match_operand:DI 5 "memory_operand" "=o"))] | |
39e63627 GK |
7987 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
7988 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
ecb62ae7 | 7989 | "#" |
230215f5 | 7990 | "&& (!no_new_pseudos || offsettable_nonstrict_memref_p (operands[5]))" |
ecb62ae7 | 7991 | [(pc)] |
0c90aa3c | 7992 | { |
ecb62ae7 GK |
7993 | rtx lowword; |
7994 | emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3])); | |
7995 | ||
230215f5 GK |
7996 | gcc_assert (MEM_P (operands[5])); |
7997 | lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0); | |
ecb62ae7 GK |
7998 | |
7999 | emit_insn (gen_fctiwz (operands[4], operands[2])); | |
8000 | emit_move_insn (operands[5], operands[4]); | |
230215f5 | 8001 | emit_move_insn (operands[0], lowword); |
0c90aa3c GK |
8002 | DONE; |
8003 | }) | |
06f4e019 DE |
8004 | |
8005 | (define_insn "negtf2" | |
8006 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
8007 | (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
39e63627 GK |
8008 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8009 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
06f4e019 DE |
8010 | "* |
8011 | { | |
8012 | if (REGNO (operands[0]) == REGNO (operands[1]) + 1) | |
8013 | return \"fneg %L0,%L1\;fneg %0,%1\"; | |
8014 | else | |
8015 | return \"fneg %0,%1\;fneg %L0,%L1\"; | |
8016 | }" | |
8017 | [(set_attr "type" "fp") | |
8018 | (set_attr "length" "8")]) | |
8019 | ||
1a402dc1 | 8020 | (define_expand "abstf2" |
06f4e019 DE |
8021 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
8022 | (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] | |
39e63627 GK |
8023 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8024 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
1a402dc1 | 8025 | " |
06f4e019 | 8026 | { |
1a402dc1 AM |
8027 | rtx label = gen_label_rtx (); |
8028 | emit_insn (gen_abstf2_internal (operands[0], operands[1], label)); | |
8029 | emit_label (label); | |
8030 | DONE; | |
8031 | }") | |
06f4e019 | 8032 | |
1a402dc1 | 8033 | (define_expand "abstf2_internal" |
06f4e019 | 8034 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") |
1a402dc1 AM |
8035 | (match_operand:TF 1 "gpc_reg_operand" "f")) |
8036 | (set (match_dup 3) (match_dup 5)) | |
8037 | (set (match_dup 5) (abs:DF (match_dup 5))) | |
8038 | (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5))) | |
8039 | (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) | |
8040 | (label_ref (match_operand 2 "" "")) | |
8041 | (pc))) | |
8042 | (set (match_dup 6) (neg:DF (match_dup 6)))] | |
39e63627 GK |
8043 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) |
8044 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
1a402dc1 | 8045 | " |
06f4e019 | 8046 | { |
1a402dc1 AM |
8047 | const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); |
8048 | const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; | |
8049 | operands[3] = gen_reg_rtx (DFmode); | |
8050 | operands[4] = gen_reg_rtx (CCFPmode); | |
8051 | operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word); | |
8052 | operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word); | |
8053 | }") | |
06f4e019 | 8054 | \f |
1fd4e8c1 RK |
8055 | ;; Next come the multi-word integer load and store and the load and store |
8056 | ;; multiple insns. | |
1fd4e8c1 | 8057 | |
112ccb83 GK |
8058 | ; List r->r after r->"o<>", otherwise reload will try to reload a |
8059 | ; non-offsettable address by using r->r which won't make progress. | |
acad7ed3 | 8060 | (define_insn "*movdi_internal32" |
343f6bbf | 8061 | [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,r,r,*f,*f,m,r") |
112ccb83 | 8062 | (match_operand:DI 1 "input_operand" "r,r,m,f,m,f,IJKnGHF"))] |
a260abc9 | 8063 | "! TARGET_POWERPC64 |
4e74d8ec MM |
8064 | && (gpc_reg_operand (operands[0], DImode) |
8065 | || gpc_reg_operand (operands[1], DImode))" | |
112ccb83 GK |
8066 | "@ |
8067 | # | |
8068 | # | |
8069 | # | |
8070 | fmr %0,%1 | |
8071 | lfd%U1%X1 %0,%1 | |
8072 | stfd%U0%X0 %1,%0 | |
8073 | #" | |
8074 | [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")]) | |
4e74d8ec MM |
8075 | |
8076 | (define_split | |
8077 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
8078 | (match_operand:DI 1 "const_int_operand" ""))] | |
a260abc9 | 8079 | "! TARGET_POWERPC64 && reload_completed" |
4e74d8ec MM |
8080 | [(set (match_dup 2) (match_dup 4)) |
8081 | (set (match_dup 3) (match_dup 1))] | |
8082 | " | |
8083 | { | |
5f59ecb7 | 8084 | HOST_WIDE_INT value = INTVAL (operands[1]); |
bdaa0181 GK |
8085 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, |
8086 | DImode); | |
8087 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8088 | DImode); | |
75d39459 | 8089 | #if HOST_BITS_PER_WIDE_INT == 32 |
5f59ecb7 | 8090 | operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; |
75d39459 | 8091 | #else |
5f59ecb7 | 8092 | operands[4] = GEN_INT (value >> 32); |
a65c591c | 8093 | operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); |
75d39459 | 8094 | #endif |
4e74d8ec MM |
8095 | }") |
8096 | ||
3a1f863f DE |
8097 | (define_split |
8098 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
8099 | (match_operand:DI 1 "input_operand" ""))] | |
6ae08853 | 8100 | "reload_completed && !TARGET_POWERPC64 |
3a1f863f | 8101 | && gpr_or_gpr_p (operands[0], operands[1])" |
a9baceb1 GK |
8102 | [(pc)] |
8103 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) | |
3a1f863f | 8104 | |
acad7ed3 | 8105 | (define_insn "*movdi_internal64" |
343f6bbf | 8106 | [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*f,*f,m,r,*h,*h") |
9615f239 | 8107 | (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] |
a260abc9 | 8108 | "TARGET_POWERPC64 |
4e74d8ec MM |
8109 | && (gpc_reg_operand (operands[0], DImode) |
8110 | || gpc_reg_operand (operands[1], DImode))" | |
51b8fc2c | 8111 | "@ |
3d5570cb RK |
8112 | mr %0,%1 |
8113 | ld%U1%X1 %0,%1 | |
96bb8ed3 | 8114 | std%U0%X0 %1,%0 |
3d5570cb | 8115 | li %0,%1 |
802a0058 | 8116 | lis %0,%v1 |
e6ca2c17 | 8117 | # |
aee86b38 | 8118 | {cal|la} %0,%a1 |
3d5570cb RK |
8119 | fmr %0,%1 |
8120 | lfd%U1%X1 %0,%1 | |
8121 | stfd%U0%X0 %1,%0 | |
8122 | mf%1 %0 | |
08075ead | 8123 | mt%0 %1 |
e34eaae5 | 8124 | {cror 0,0,0|nop}" |
02ca7595 | 8125 | [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*") |
e6ca2c17 DE |
8126 | (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) |
8127 | ||
5f59ecb7 | 8128 | ;; immediate value valid for a single instruction hiding in a const_double |
a260abc9 DE |
8129 | (define_insn "" |
8130 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
8131 | (match_operand:DI 1 "const_double_operand" "F"))] | |
5f59ecb7 DE |
8132 | "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 |
8133 | && GET_CODE (operands[1]) == CONST_DOUBLE | |
a260abc9 DE |
8134 | && num_insns_constant (operands[1], DImode) == 1" |
8135 | "* | |
8136 | { | |
8137 | return ((unsigned HOST_WIDE_INT) | |
8138 | (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) | |
8139 | ? \"li %0,%1\" : \"lis %0,%v1\"; | |
8140 | }") | |
8141 | ||
a260abc9 DE |
8142 | ;; Generate all one-bits and clear left or right. |
8143 | ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. | |
8144 | (define_split | |
8145 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
4ae234b0 | 8146 | (match_operand:DI 1 "mask_operand" ""))] |
a260abc9 DE |
8147 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" |
8148 | [(set (match_dup 0) (const_int -1)) | |
e6ca2c17 | 8149 | (set (match_dup 0) |
a260abc9 DE |
8150 | (and:DI (rotate:DI (match_dup 0) |
8151 | (const_int 0)) | |
8152 | (match_dup 1)))] | |
8153 | "") | |
8154 | ||
8155 | ;; Split a load of a large constant into the appropriate five-instruction | |
8156 | ;; sequence. Handle anything in a constant number of insns. | |
8157 | ;; When non-easy constants can go in the TOC, this should use | |
8158 | ;; easy_fp_constant predicate. | |
8159 | (define_split | |
8160 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8161 | (match_operand:DI 1 "const_int_operand" ""))] |
8162 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8163 | [(set (match_dup 0) (match_dup 2)) | |
8164 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
e6ca2c17 | 8165 | " |
2bfcf297 DB |
8166 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8167 | ||
8168 | if (tem == operands[0]) | |
8169 | DONE; | |
e8d791dd | 8170 | else |
2bfcf297 | 8171 | FAIL; |
5f59ecb7 | 8172 | }") |
e6ca2c17 | 8173 | |
5f59ecb7 DE |
8174 | (define_split |
8175 | [(set (match_operand:DI 0 "gpc_reg_operand" "") | |
2bfcf297 DB |
8176 | (match_operand:DI 1 "const_double_operand" ""))] |
8177 | "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" | |
8178 | [(set (match_dup 0) (match_dup 2)) | |
8179 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] | |
5f59ecb7 | 8180 | " |
2bfcf297 DB |
8181 | { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); |
8182 | ||
8183 | if (tem == operands[0]) | |
8184 | DONE; | |
8185 | else | |
8186 | FAIL; | |
e6ca2c17 | 8187 | }") |
acad7ed3 | 8188 | \f |
1fd4e8c1 RK |
8189 | ;; TImode is similar, except that we usually want to compute the address into |
8190 | ;; a register and use lsi/stsi (the exception is during reload). MQ is also | |
ca7f5001 | 8191 | ;; clobbered in stsi for POWER, so we need a SCRATCH for it. |
1fd4e8c1 RK |
8192 | |
8193 | ;; We say that MQ is clobbered in the last alternative because the first | |
8194 | ;; alternative would never get used otherwise since it would need a reload | |
8195 | ;; while the 2nd alternative would not. We put memory cases first so they | |
8196 | ;; are preferred. Otherwise, we'd try to reload the output instead of | |
8197 | ;; giving the SCRATCH mq. | |
3a1f863f | 8198 | |
a260abc9 | 8199 | (define_insn "*movti_power" |
7f514158 AM |
8200 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r") |
8201 | (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n")) | |
8202 | (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))] | |
6ae08853 | 8203 | "TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca | 8204 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
1fd4e8c1 RK |
8205 | "* |
8206 | { | |
8207 | switch (which_alternative) | |
8208 | { | |
dc4f83ca | 8209 | default: |
37409796 | 8210 | gcc_unreachable (); |
dc4f83ca | 8211 | |
1fd4e8c1 | 8212 | case 0: |
3a1f863f DE |
8213 | if (TARGET_STRING) |
8214 | return \"{stsi|stswi} %1,%P0,16\"; | |
1fd4e8c1 | 8215 | case 1: |
1fd4e8c1 | 8216 | case 2: |
3a1f863f | 8217 | return \"#\"; |
1fd4e8c1 RK |
8218 | case 3: |
8219 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8220 | fall through to generating four loads. */ | |
e876481c DE |
8221 | if (TARGET_STRING |
8222 | && ! reg_overlap_mentioned_p (operands[0], operands[1])) | |
ca7f5001 | 8223 | return \"{lsi|lswi} %0,%P1,16\"; |
82e41834 | 8224 | /* ... fall through ... */ |
1fd4e8c1 | 8225 | case 4: |
7f514158 | 8226 | case 5: |
3a1f863f | 8227 | return \"#\"; |
1fd4e8c1 RK |
8228 | } |
8229 | }" | |
7f514158 | 8230 | [(set_attr "type" "store,store,*,load,load,*")]) |
51b8fc2c | 8231 | |
a260abc9 | 8232 | (define_insn "*movti_string" |
7f514158 AM |
8233 | [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r") |
8234 | (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))] | |
3a1f863f | 8235 | "! TARGET_POWER && ! TARGET_POWERPC64 |
dc4f83ca MM |
8236 | && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" |
8237 | "* | |
8238 | { | |
8239 | switch (which_alternative) | |
8240 | { | |
8241 | default: | |
37409796 | 8242 | gcc_unreachable (); |
dc4f83ca | 8243 | case 0: |
3a1f863f DE |
8244 | if (TARGET_STRING) |
8245 | return \"{stsi|stswi} %1,%P0,16\"; | |
dc4f83ca | 8246 | case 1: |
cd1d3445 | 8247 | case 2: |
3a1f863f | 8248 | return \"#\"; |
cd1d3445 DE |
8249 | case 3: |
8250 | /* If the address is not used in the output, we can use lsi. Otherwise, | |
8251 | fall through to generating four loads. */ | |
6ae08853 | 8252 | if (TARGET_STRING |
3a1f863f | 8253 | && ! reg_overlap_mentioned_p (operands[0], operands[1])) |
cd1d3445 DE |
8254 | return \"{lsi|lswi} %0,%P1,16\"; |
8255 | /* ... fall through ... */ | |
8256 | case 4: | |
7f514158 | 8257 | case 5: |
3a1f863f | 8258 | return \"#\"; |
dc4f83ca MM |
8259 | } |
8260 | }" | |
7f514158 | 8261 | [(set_attr "type" "store,store,*,load,load,*")]) |
dc4f83ca | 8262 | |
a260abc9 | 8263 | (define_insn "*movti_ppc64" |
112ccb83 GK |
8264 | [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r") |
8265 | (match_operand:TI 1 "input_operand" "r,r,m"))] | |
51b8fc2c RK |
8266 | "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) |
8267 | || gpc_reg_operand (operands[1], TImode))" | |
112ccb83 | 8268 | "#" |
3a1f863f DE |
8269 | [(set_attr "type" "*,load,store")]) |
8270 | ||
7f514158 AM |
8271 | (define_split |
8272 | [(set (match_operand:TI 0 "gpc_reg_operand" "") | |
8273 | (match_operand:TI 1 "const_double_operand" ""))] | |
8274 | "TARGET_POWERPC64" | |
8275 | [(set (match_dup 2) (match_dup 4)) | |
8276 | (set (match_dup 3) (match_dup 5))] | |
8277 | " | |
8278 | { | |
8279 | operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, | |
8280 | TImode); | |
8281 | operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, | |
8282 | TImode); | |
8283 | if (GET_CODE (operands[1]) == CONST_DOUBLE) | |
8284 | { | |
8285 | operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); | |
8286 | operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); | |
8287 | } | |
8288 | else if (GET_CODE (operands[1]) == CONST_INT) | |
8289 | { | |
8290 | operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0)); | |
8291 | operands[5] = operands[1]; | |
8292 | } | |
8293 | else | |
8294 | FAIL; | |
8295 | }") | |
8296 | ||
3a1f863f DE |
8297 | (define_split |
8298 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
8299 | (match_operand:TI 1 "input_operand" ""))] | |
a9baceb1 | 8300 | "reload_completed |
3a1f863f | 8301 | && gpr_or_gpr_p (operands[0], operands[1])" |
a9baceb1 GK |
8302 | [(pc)] |
8303 | { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) | |
1fd4e8c1 RK |
8304 | \f |
8305 | (define_expand "load_multiple" | |
2f622005 RK |
8306 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8307 | (match_operand:SI 1 "" "")) | |
8308 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8309 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8310 | " |
8311 | { | |
8312 | int regno; | |
8313 | int count; | |
792760b9 | 8314 | rtx op1; |
1fd4e8c1 RK |
8315 | int i; |
8316 | ||
8317 | /* Support only loading a constant number of fixed-point registers from | |
8318 | memory and only bother with this if more than two; the machine | |
8319 | doesn't support more than eight. */ | |
8320 | if (GET_CODE (operands[2]) != CONST_INT | |
8321 | || INTVAL (operands[2]) <= 2 | |
8322 | || INTVAL (operands[2]) > 8 | |
8323 | || GET_CODE (operands[1]) != MEM | |
8324 | || GET_CODE (operands[0]) != REG | |
8325 | || REGNO (operands[0]) >= 32) | |
8326 | FAIL; | |
8327 | ||
8328 | count = INTVAL (operands[2]); | |
8329 | regno = REGNO (operands[0]); | |
8330 | ||
39403d82 | 8331 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); |
792760b9 RK |
8332 | op1 = replace_equiv_address (operands[1], |
8333 | force_reg (SImode, XEXP (operands[1], 0))); | |
1fd4e8c1 RK |
8334 | |
8335 | for (i = 0; i < count; i++) | |
8336 | XVECEXP (operands[3], 0, i) | |
39403d82 | 8337 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), |
7ef788f0 | 8338 | adjust_address_nv (op1, SImode, i * 4)); |
1fd4e8c1 RK |
8339 | }") |
8340 | ||
9caa3eb2 | 8341 | (define_insn "*ldmsi8" |
1fd4e8c1 | 8342 | [(match_parallel 0 "load_multiple_operation" |
9caa3eb2 DE |
8343 | [(set (match_operand:SI 2 "gpc_reg_operand" "") |
8344 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8345 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8346 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8347 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8348 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8349 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8350 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8351 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8352 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8353 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8354 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
8355 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
8356 | (mem:SI (plus:SI (match_dup 1) (const_int 24)))) | |
8357 | (set (match_operand:SI 9 "gpc_reg_operand" "") | |
8358 | (mem:SI (plus:SI (match_dup 1) (const_int 28))))])] | |
8359 | "TARGET_STRING && XVECLEN (operands[0], 0) == 8" | |
1fd4e8c1 | 8360 | "* |
9caa3eb2 DE |
8361 | { return rs6000_output_load_multiple (operands); }" |
8362 | [(set_attr "type" "load") | |
8363 | (set_attr "length" "32")]) | |
1fd4e8c1 | 8364 | |
9caa3eb2 DE |
8365 | (define_insn "*ldmsi7" |
8366 | [(match_parallel 0 "load_multiple_operation" | |
8367 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8368 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8369 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8370 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8371 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8372 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8373 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8374 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8375 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8376 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8377 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8378 | (mem:SI (plus:SI (match_dup 1) (const_int 20)))) | |
8379 | (set (match_operand:SI 8 "gpc_reg_operand" "") | |
8380 | (mem:SI (plus:SI (match_dup 1) (const_int 24))))])] | |
8381 | "TARGET_STRING && XVECLEN (operands[0], 0) == 7" | |
8382 | "* | |
8383 | { return rs6000_output_load_multiple (operands); }" | |
8384 | [(set_attr "type" "load") | |
8385 | (set_attr "length" "32")]) | |
8386 | ||
8387 | (define_insn "*ldmsi6" | |
8388 | [(match_parallel 0 "load_multiple_operation" | |
8389 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8390 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8391 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8392 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8393 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8394 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8395 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8396 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8397 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8398 | (mem:SI (plus:SI (match_dup 1) (const_int 16)))) | |
8399 | (set (match_operand:SI 7 "gpc_reg_operand" "") | |
8400 | (mem:SI (plus:SI (match_dup 1) (const_int 20))))])] | |
8401 | "TARGET_STRING && XVECLEN (operands[0], 0) == 6" | |
8402 | "* | |
8403 | { return rs6000_output_load_multiple (operands); }" | |
8404 | [(set_attr "type" "load") | |
8405 | (set_attr "length" "32")]) | |
8406 | ||
8407 | (define_insn "*ldmsi5" | |
8408 | [(match_parallel 0 "load_multiple_operation" | |
8409 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8410 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8411 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8412 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8413 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8414 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8415 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8416 | (mem:SI (plus:SI (match_dup 1) (const_int 12)))) | |
8417 | (set (match_operand:SI 6 "gpc_reg_operand" "") | |
8418 | (mem:SI (plus:SI (match_dup 1) (const_int 16))))])] | |
8419 | "TARGET_STRING && XVECLEN (operands[0], 0) == 5" | |
8420 | "* | |
8421 | { return rs6000_output_load_multiple (operands); }" | |
8422 | [(set_attr "type" "load") | |
8423 | (set_attr "length" "32")]) | |
8424 | ||
8425 | (define_insn "*ldmsi4" | |
8426 | [(match_parallel 0 "load_multiple_operation" | |
8427 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8428 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8429 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8430 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8431 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8432 | (mem:SI (plus:SI (match_dup 1) (const_int 8)))) | |
8433 | (set (match_operand:SI 5 "gpc_reg_operand" "") | |
8434 | (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] | |
8435 | "TARGET_STRING && XVECLEN (operands[0], 0) == 4" | |
8436 | "* | |
8437 | { return rs6000_output_load_multiple (operands); }" | |
8438 | [(set_attr "type" "load") | |
8439 | (set_attr "length" "32")]) | |
8440 | ||
8441 | (define_insn "*ldmsi3" | |
8442 | [(match_parallel 0 "load_multiple_operation" | |
8443 | [(set (match_operand:SI 2 "gpc_reg_operand" "") | |
8444 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
8445 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
8446 | (mem:SI (plus:SI (match_dup 1) (const_int 4)))) | |
8447 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
8448 | (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] | |
8449 | "TARGET_STRING && XVECLEN (operands[0], 0) == 3" | |
8450 | "* | |
8451 | { return rs6000_output_load_multiple (operands); }" | |
b19003d8 | 8452 | [(set_attr "type" "load") |
e82ee4cc | 8453 | (set_attr "length" "32")]) |
b19003d8 | 8454 | |
1fd4e8c1 | 8455 | (define_expand "store_multiple" |
2f622005 RK |
8456 | [(match_par_dup 3 [(set (match_operand:SI 0 "" "") |
8457 | (match_operand:SI 1 "" "")) | |
8458 | (clobber (scratch:SI)) | |
8459 | (use (match_operand:SI 2 "" ""))])] | |
09a625f7 | 8460 | "TARGET_STRING && !TARGET_POWERPC64" |
1fd4e8c1 RK |
8461 | " |
8462 | { | |
8463 | int regno; | |
8464 | int count; | |
8465 | rtx to; | |
792760b9 | 8466 | rtx op0; |
1fd4e8c1 RK |
8467 | int i; |
8468 | ||
8469 | /* Support only storing a constant number of fixed-point registers to | |
8470 | memory and only bother with this if more than two; the machine | |
8471 | doesn't support more than eight. */ | |
8472 | if (GET_CODE (operands[2]) != CONST_INT | |
8473 | || INTVAL (operands[2]) <= 2 | |
8474 | || INTVAL (operands[2]) > 8 | |
8475 | || GET_CODE (operands[0]) != MEM | |
8476 | || GET_CODE (operands[1]) != REG | |
8477 | || REGNO (operands[1]) >= 32) | |
8478 | FAIL; | |
8479 | ||
8480 | count = INTVAL (operands[2]); | |
8481 | regno = REGNO (operands[1]); | |
8482 | ||
39403d82 | 8483 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); |
1fd4e8c1 | 8484 | to = force_reg (SImode, XEXP (operands[0], 0)); |
792760b9 | 8485 | op0 = replace_equiv_address (operands[0], to); |
1fd4e8c1 RK |
8486 | |
8487 | XVECEXP (operands[3], 0, 0) | |
7ef788f0 | 8488 | = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]); |
39403d82 | 8489 | XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, |
c5c76735 | 8490 | gen_rtx_SCRATCH (SImode)); |
1fd4e8c1 RK |
8491 | |
8492 | for (i = 1; i < count; i++) | |
8493 | XVECEXP (operands[3], 0, i + 1) | |
39403d82 | 8494 | = gen_rtx_SET (VOIDmode, |
7ef788f0 | 8495 | adjust_address_nv (op0, SImode, i * 4), |
c5c76735 | 8496 | gen_rtx_REG (SImode, regno + i)); |
1fd4e8c1 RK |
8497 | }") |
8498 | ||
9caa3eb2 | 8499 | (define_insn "*store_multiple_power" |
1fd4e8c1 RK |
8500 | [(match_parallel 0 "store_multiple_operation" |
8501 | [(set (match_operand:SI 1 "indirect_operand" "=Q") | |
cd2b37d9 | 8502 | (match_operand:SI 2 "gpc_reg_operand" "r")) |
1fd4e8c1 | 8503 | (clobber (match_scratch:SI 3 "=q"))])] |
7e69e155 | 8504 | "TARGET_STRING && TARGET_POWER" |
b7ff3d82 DE |
8505 | "{stsi|stswi} %2,%P1,%O0" |
8506 | [(set_attr "type" "store")]) | |
d14a6d05 | 8507 | |
e46e3130 | 8508 | (define_insn "*stmsi8" |
d14a6d05 | 8509 | [(match_parallel 0 "store_multiple_operation" |
e46e3130 DJ |
8510 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) |
8511 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8512 | (clobber (match_scratch:SI 3 "X")) | |
8513 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8514 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8515 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8516 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8517 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8518 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8519 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8520 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
8521 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
8522 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
8523 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
8524 | (match_operand:SI 9 "gpc_reg_operand" "r")) | |
8525 | (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) | |
8526 | (match_operand:SI 10 "gpc_reg_operand" "r"))])] | |
8527 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9" | |
8528 | "{stsi|stswi} %2,%1,%O0" | |
8529 | [(set_attr "type" "store")]) | |
8530 | ||
8531 | (define_insn "*stmsi7" | |
8532 | [(match_parallel 0 "store_multiple_operation" | |
8533 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8534 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8535 | (clobber (match_scratch:SI 3 "X")) | |
8536 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8537 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8538 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8539 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8540 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8541 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8542 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8543 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
8544 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
8545 | (match_operand:SI 8 "gpc_reg_operand" "r")) | |
8546 | (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) | |
8547 | (match_operand:SI 9 "gpc_reg_operand" "r"))])] | |
8548 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8" | |
8549 | "{stsi|stswi} %2,%1,%O0" | |
8550 | [(set_attr "type" "store")]) | |
8551 | ||
8552 | (define_insn "*stmsi6" | |
8553 | [(match_parallel 0 "store_multiple_operation" | |
8554 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8555 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8556 | (clobber (match_scratch:SI 3 "X")) | |
8557 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8558 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8559 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8560 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8561 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8562 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8563 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8564 | (match_operand:SI 7 "gpc_reg_operand" "r")) | |
8565 | (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) | |
8566 | (match_operand:SI 8 "gpc_reg_operand" "r"))])] | |
8567 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7" | |
8568 | "{stsi|stswi} %2,%1,%O0" | |
8569 | [(set_attr "type" "store")]) | |
8570 | ||
8571 | (define_insn "*stmsi5" | |
8572 | [(match_parallel 0 "store_multiple_operation" | |
8573 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8574 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8575 | (clobber (match_scratch:SI 3 "X")) | |
8576 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8577 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8578 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8579 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8580 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8581 | (match_operand:SI 6 "gpc_reg_operand" "r")) | |
8582 | (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) | |
8583 | (match_operand:SI 7 "gpc_reg_operand" "r"))])] | |
8584 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6" | |
8585 | "{stsi|stswi} %2,%1,%O0" | |
8586 | [(set_attr "type" "store")]) | |
8587 | ||
8588 | (define_insn "*stmsi4" | |
8589 | [(match_parallel 0 "store_multiple_operation" | |
8590 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8591 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8592 | (clobber (match_scratch:SI 3 "X")) | |
8593 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8594 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8595 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8596 | (match_operand:SI 5 "gpc_reg_operand" "r")) | |
8597 | (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) | |
8598 | (match_operand:SI 6 "gpc_reg_operand" "r"))])] | |
8599 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5" | |
b7ff3d82 DE |
8600 | "{stsi|stswi} %2,%1,%O0" |
8601 | [(set_attr "type" "store")]) | |
7e69e155 | 8602 | |
e46e3130 DJ |
8603 | (define_insn "*stmsi3" |
8604 | [(match_parallel 0 "store_multiple_operation" | |
8605 | [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) | |
8606 | (match_operand:SI 2 "gpc_reg_operand" "r")) | |
8607 | (clobber (match_scratch:SI 3 "X")) | |
8608 | (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) | |
8609 | (match_operand:SI 4 "gpc_reg_operand" "r")) | |
8610 | (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) | |
8611 | (match_operand:SI 5 "gpc_reg_operand" "r"))])] | |
8612 | "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4" | |
8613 | "{stsi|stswi} %2,%1,%O0" | |
8614 | [(set_attr "type" "store")]) | |
7e69e155 | 8615 | \f |
57e84f18 | 8616 | (define_expand "setmemsi" |
fba73eb1 | 8617 | [(parallel [(set (match_operand:BLK 0 "" "") |
98843c92 | 8618 | (match_operand 2 "const_int_operand" "")) |
fba73eb1 | 8619 | (use (match_operand:SI 1 "" "")) |
57e84f18 | 8620 | (use (match_operand:SI 3 "" ""))])] |
fba73eb1 DE |
8621 | "" |
8622 | " | |
8623 | { | |
57e84f18 AS |
8624 | /* If value to set is not zero, use the library routine. */ |
8625 | if (operand[2] != const0_rtx) | |
8626 | FAIL; | |
8627 | ||
fba73eb1 DE |
8628 | if (expand_block_clear (operands)) |
8629 | DONE; | |
8630 | else | |
8631 | FAIL; | |
8632 | }") | |
8633 | ||
7e69e155 MM |
8634 | ;; String/block move insn. |
8635 | ;; Argument 0 is the destination | |
8636 | ;; Argument 1 is the source | |
8637 | ;; Argument 2 is the length | |
8638 | ;; Argument 3 is the alignment | |
8639 | ||
70128ad9 | 8640 | (define_expand "movmemsi" |
b6c9286a MM |
8641 | [(parallel [(set (match_operand:BLK 0 "" "") |
8642 | (match_operand:BLK 1 "" "")) | |
8643 | (use (match_operand:SI 2 "" "")) | |
8644 | (use (match_operand:SI 3 "" ""))])] | |
7e69e155 MM |
8645 | "" |
8646 | " | |
8647 | { | |
8648 | if (expand_block_move (operands)) | |
8649 | DONE; | |
8650 | else | |
8651 | FAIL; | |
8652 | }") | |
8653 | ||
8654 | ;; Move up to 32 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
8655 | ;; register allocator doesn't have a clue about allocating 8 word registers. |
8656 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 8657 | (define_expand "movmemsi_8reg" |
b6c9286a MM |
8658 | [(parallel [(set (match_operand 0 "" "") |
8659 | (match_operand 1 "" "")) | |
8660 | (use (match_operand 2 "" "")) | |
8661 | (use (match_operand 3 "" "")) | |
7e69e155 MM |
8662 | (clobber (reg:SI 5)) |
8663 | (clobber (reg:SI 6)) | |
8664 | (clobber (reg:SI 7)) | |
8665 | (clobber (reg:SI 8)) | |
8666 | (clobber (reg:SI 9)) | |
8667 | (clobber (reg:SI 10)) | |
8668 | (clobber (reg:SI 11)) | |
8669 | (clobber (reg:SI 12)) | |
3c67b673 | 8670 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8671 | "TARGET_STRING" |
8672 | "") | |
8673 | ||
8674 | (define_insn "" | |
52d3af72 DE |
8675 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8676 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8677 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8678 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8679 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
8680 | (clobber (reg:SI 6)) |
8681 | (clobber (reg:SI 7)) | |
8682 | (clobber (reg:SI 8)) | |
8683 | (clobber (reg:SI 9)) | |
8684 | (clobber (reg:SI 10)) | |
8685 | (clobber (reg:SI 11)) | |
8686 | (clobber (reg:SI 12)) | |
3c67b673 | 8687 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 | 8688 | "TARGET_STRING && TARGET_POWER |
f9562f27 DE |
8689 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
8690 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
8691 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
8692 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
8693 | && REGNO (operands[4]) == 5" |
8694 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8695 | [(set_attr "type" "load") |
8696 | (set_attr "length" "8")]) | |
7e69e155 MM |
8697 | |
8698 | (define_insn "" | |
4ae234b0 GK |
8699 | [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) |
8700 | (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8701 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8702 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8703 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
7e69e155 MM |
8704 | (clobber (reg:SI 6)) |
8705 | (clobber (reg:SI 7)) | |
8706 | (clobber (reg:SI 8)) | |
8707 | (clobber (reg:SI 9)) | |
8708 | (clobber (reg:SI 10)) | |
8709 | (clobber (reg:SI 11)) | |
8710 | (clobber (reg:SI 12)) | |
3c67b673 | 8711 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8712 | "TARGET_STRING && ! TARGET_POWER |
f9562f27 DE |
8713 | && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) |
8714 | || INTVAL (operands[2]) == 0) | |
7e69e155 MM |
8715 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) |
8716 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) | |
3c67b673 RK |
8717 | && REGNO (operands[4]) == 5" |
8718 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8719 | [(set_attr "type" "load") |
8720 | (set_attr "length" "8")]) | |
7e69e155 MM |
8721 | |
8722 | ;; Move up to 24 bytes at a time. The fixed registers are needed because the | |
f9562f27 DE |
8723 | ;; register allocator doesn't have a clue about allocating 6 word registers. |
8724 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 8725 | (define_expand "movmemsi_6reg" |
b6c9286a MM |
8726 | [(parallel [(set (match_operand 0 "" "") |
8727 | (match_operand 1 "" "")) | |
8728 | (use (match_operand 2 "" "")) | |
8729 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
8730 | (clobber (reg:SI 5)) |
8731 | (clobber (reg:SI 6)) | |
7e69e155 MM |
8732 | (clobber (reg:SI 7)) |
8733 | (clobber (reg:SI 8)) | |
8734 | (clobber (reg:SI 9)) | |
8735 | (clobber (reg:SI 10)) | |
3c67b673 | 8736 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8737 | "TARGET_STRING" |
8738 | "") | |
8739 | ||
8740 | (define_insn "" | |
52d3af72 DE |
8741 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8742 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8743 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8744 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8745 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8746 | (clobber (reg:SI 6)) |
8747 | (clobber (reg:SI 7)) | |
7e69e155 MM |
8748 | (clobber (reg:SI 8)) |
8749 | (clobber (reg:SI 9)) | |
8750 | (clobber (reg:SI 10)) | |
3c67b673 | 8751 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
8752 | "TARGET_STRING && TARGET_POWER |
8753 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24 | |
f9562f27 DE |
8754 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
8755 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
8756 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8757 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8758 | [(set_attr "type" "load") |
8759 | (set_attr "length" "8")]) | |
7e69e155 MM |
8760 | |
8761 | (define_insn "" | |
4ae234b0 GK |
8762 | [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) |
8763 | (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8764 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8765 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8766 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8767 | (clobber (reg:SI 6)) |
8768 | (clobber (reg:SI 7)) | |
7e69e155 MM |
8769 | (clobber (reg:SI 8)) |
8770 | (clobber (reg:SI 9)) | |
8771 | (clobber (reg:SI 10)) | |
3c67b673 | 8772 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8773 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8774 | && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 |
f9562f27 DE |
8775 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) |
8776 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) | |
8777 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8778 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8779 | [(set_attr "type" "load") |
8780 | (set_attr "length" "8")]) | |
7e69e155 | 8781 | |
f9562f27 DE |
8782 | ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill |
8783 | ;; problems with TImode. | |
8784 | ;; rD/rS = r5 is preferred, efficient form. | |
70128ad9 | 8785 | (define_expand "movmemsi_4reg" |
b6c9286a MM |
8786 | [(parallel [(set (match_operand 0 "" "") |
8787 | (match_operand 1 "" "")) | |
8788 | (use (match_operand 2 "" "")) | |
8789 | (use (match_operand 3 "" "")) | |
f9562f27 DE |
8790 | (clobber (reg:SI 5)) |
8791 | (clobber (reg:SI 6)) | |
8792 | (clobber (reg:SI 7)) | |
8793 | (clobber (reg:SI 8)) | |
3c67b673 | 8794 | (clobber (match_scratch:SI 4 ""))])] |
7e69e155 MM |
8795 | "TARGET_STRING" |
8796 | "") | |
8797 | ||
8798 | (define_insn "" | |
52d3af72 DE |
8799 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8800 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8801 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8802 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8803 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8804 | (clobber (reg:SI 6)) |
8805 | (clobber (reg:SI 7)) | |
8806 | (clobber (reg:SI 8)) | |
3c67b673 | 8807 | (clobber (match_scratch:SI 5 "=q"))] |
7e69e155 MM |
8808 | "TARGET_STRING && TARGET_POWER |
8809 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 | |
f9562f27 DE |
8810 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
8811 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
8812 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8813 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8814 | [(set_attr "type" "load") |
8815 | (set_attr "length" "8")]) | |
7e69e155 MM |
8816 | |
8817 | (define_insn "" | |
4ae234b0 GK |
8818 | [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) |
8819 | (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8820 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8821 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
52d3af72 | 8822 | (clobber (match_operand:SI 4 "gpc_reg_operand" "=r")) |
f9562f27 DE |
8823 | (clobber (reg:SI 6)) |
8824 | (clobber (reg:SI 7)) | |
8825 | (clobber (reg:SI 8)) | |
3c67b673 | 8826 | (clobber (match_scratch:SI 5 "X"))] |
0ad91047 | 8827 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8828 | && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 |
f9562f27 DE |
8829 | && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) |
8830 | && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) | |
8831 | && REGNO (operands[4]) == 5" | |
3c67b673 | 8832 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8833 | [(set_attr "type" "load") |
8834 | (set_attr "length" "8")]) | |
7e69e155 MM |
8835 | |
8836 | ;; Move up to 8 bytes at a time. | |
70128ad9 | 8837 | (define_expand "movmemsi_2reg" |
b6c9286a MM |
8838 | [(parallel [(set (match_operand 0 "" "") |
8839 | (match_operand 1 "" "")) | |
8840 | (use (match_operand 2 "" "")) | |
8841 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
8842 | (clobber (match_scratch:DI 4 "")) |
8843 | (clobber (match_scratch:SI 5 ""))])] | |
f9562f27 | 8844 | "TARGET_STRING && ! TARGET_POWERPC64" |
7e69e155 MM |
8845 | "") |
8846 | ||
8847 | (define_insn "" | |
52d3af72 DE |
8848 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8849 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8850 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8851 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8852 | (clobber (match_scratch:DI 4 "=&r")) | |
8853 | (clobber (match_scratch:SI 5 "=q"))] | |
f9562f27 | 8854 | "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64 |
3c67b673 RK |
8855 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
8856 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" | |
b7ff3d82 DE |
8857 | [(set_attr "type" "load") |
8858 | (set_attr "length" "8")]) | |
7e69e155 MM |
8859 | |
8860 | (define_insn "" | |
52d3af72 DE |
8861 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8862 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8863 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8864 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8865 | (clobber (match_scratch:DI 4 "=&r")) | |
8866 | (clobber (match_scratch:SI 5 "X"))] | |
f9562f27 | 8867 | "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 |
7e69e155 | 8868 | && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" |
3c67b673 | 8869 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8870 | [(set_attr "type" "load") |
8871 | (set_attr "length" "8")]) | |
7e69e155 MM |
8872 | |
8873 | ;; Move up to 4 bytes at a time. | |
70128ad9 | 8874 | (define_expand "movmemsi_1reg" |
b6c9286a MM |
8875 | [(parallel [(set (match_operand 0 "" "") |
8876 | (match_operand 1 "" "")) | |
8877 | (use (match_operand 2 "" "")) | |
8878 | (use (match_operand 3 "" "")) | |
3c67b673 RK |
8879 | (clobber (match_scratch:SI 4 "")) |
8880 | (clobber (match_scratch:SI 5 ""))])] | |
7e69e155 MM |
8881 | "TARGET_STRING" |
8882 | "") | |
8883 | ||
8884 | (define_insn "" | |
52d3af72 DE |
8885 | [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) |
8886 | (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8887 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8888 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8889 | (clobber (match_scratch:SI 4 "=&r")) | |
8890 | (clobber (match_scratch:SI 5 "=q"))] | |
7e69e155 MM |
8891 | "TARGET_STRING && TARGET_POWER |
8892 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" | |
3c67b673 | 8893 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
b7ff3d82 DE |
8894 | [(set_attr "type" "load") |
8895 | (set_attr "length" "8")]) | |
7e69e155 MM |
8896 | |
8897 | (define_insn "" | |
4ae234b0 GK |
8898 | [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) |
8899 | (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) | |
3c67b673 RK |
8900 | (use (match_operand:SI 2 "immediate_operand" "i")) |
8901 | (use (match_operand:SI 3 "immediate_operand" "i")) | |
8902 | (clobber (match_scratch:SI 4 "=&r")) | |
8903 | (clobber (match_scratch:SI 5 "X"))] | |
0ad91047 | 8904 | "TARGET_STRING && ! TARGET_POWER |
7e69e155 | 8905 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" |
09a625f7 TR |
8906 | "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2" |
8907 | [(set_attr "type" "load") | |
8908 | (set_attr "length" "8")]) | |
1fd4e8c1 | 8909 | \f |
7e69e155 | 8910 | ;; Define insns that do load or store with update. Some of these we can |
1fd4e8c1 RK |
8911 | ;; get by using pre-decrement or pre-increment, but the hardware can also |
8912 | ;; do cases where the increment is not the size of the object. | |
8913 | ;; | |
8914 | ;; In all these cases, we use operands 0 and 1 for the register being | |
8915 | ;; incremented because those are the operands that local-alloc will | |
8916 | ;; tie and these are the pair most likely to be tieable (and the ones | |
8917 | ;; that will benefit the most). | |
8918 | ||
38c1f2d7 | 8919 | (define_insn "*movdi_update1" |
51b8fc2c | 8920 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") |
ad8bd902 | 8921 | (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") |
768070a0 | 8922 | (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))) |
51b8fc2c RK |
8923 | (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") |
8924 | (plus:DI (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 8925 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
8926 | "@ |
8927 | ldux %3,%0,%2 | |
8928 | ldu %3,%2(%0)" | |
b54cf83a | 8929 | [(set_attr "type" "load_ux,load_u")]) |
287f13ff | 8930 | |
2e6c9641 FJ |
8931 | (define_insn "movdi_<mode>_update" |
8932 | [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") | |
8933 | (match_operand:P 2 "reg_or_aligned_short_operand" "r,I"))) | |
51b8fc2c | 8934 | (match_operand:DI 3 "gpc_reg_operand" "r,r")) |
2e6c9641 FJ |
8935 | (set (match_operand:P 0 "gpc_reg_operand" "=b,b") |
8936 | (plus:P (match_dup 1) (match_dup 2)))] | |
38c1f2d7 | 8937 | "TARGET_POWERPC64 && TARGET_UPDATE" |
51b8fc2c RK |
8938 | "@ |
8939 | stdux %3,%0,%2 | |
b7ff3d82 | 8940 | stdu %3,%2(%0)" |
b54cf83a | 8941 | [(set_attr "type" "store_ux,store_u")]) |
51b8fc2c | 8942 | |
38c1f2d7 | 8943 | (define_insn "*movsi_update1" |
cd2b37d9 RK |
8944 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
8945 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 8946 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8947 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8948 | (plus:SI (match_dup 1) (match_dup 2)))] |
f7b3ab8a | 8949 | "TARGET_UPDATE" |
1fd4e8c1 | 8950 | "@ |
ca7f5001 RK |
8951 | {lux|lwzux} %3,%0,%2 |
8952 | {lu|lwzu} %3,%2(%0)" | |
b54cf83a DE |
8953 | [(set_attr "type" "load_ux,load_u")]) |
8954 | ||
8955 | (define_insn "*movsi_update2" | |
8956 | [(set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
8957 | (sign_extend:DI | |
8958 | (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") | |
8959 | (match_operand:DI 2 "gpc_reg_operand" "r"))))) | |
8960 | (set (match_operand:DI 0 "gpc_reg_operand" "=b") | |
8961 | (plus:DI (match_dup 1) (match_dup 2)))] | |
8962 | "TARGET_POWERPC64" | |
8963 | "lwaux %3,%0,%2" | |
8964 | [(set_attr "type" "load_ext_ux")]) | |
1fd4e8c1 | 8965 | |
4697a36c | 8966 | (define_insn "movsi_update" |
cd2b37d9 | 8967 | [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8968 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
8969 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) |
8970 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 8971 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8972 | "TARGET_UPDATE" |
1fd4e8c1 | 8973 | "@ |
ca7f5001 | 8974 | {stux|stwux} %3,%0,%2 |
b7ff3d82 | 8975 | {stu|stwu} %3,%2(%0)" |
b54cf83a | 8976 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 8977 | |
b54cf83a | 8978 | (define_insn "*movhi_update1" |
cd2b37d9 RK |
8979 | [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") |
8980 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 8981 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 8982 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8983 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8984 | "TARGET_UPDATE" |
1fd4e8c1 | 8985 | "@ |
5f243543 RK |
8986 | lhzux %3,%0,%2 |
8987 | lhzu %3,%2(%0)" | |
b54cf83a | 8988 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 8989 | |
38c1f2d7 | 8990 | (define_insn "*movhi_update2" |
cd2b37d9 | 8991 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 8992 | (zero_extend:SI |
cd2b37d9 | 8993 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 8994 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 8995 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 8996 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 8997 | "TARGET_UPDATE" |
1fd4e8c1 | 8998 | "@ |
5f243543 RK |
8999 | lhzux %3,%0,%2 |
9000 | lhzu %3,%2(%0)" | |
b54cf83a | 9001 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9002 | |
38c1f2d7 | 9003 | (define_insn "*movhi_update3" |
cd2b37d9 | 9004 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9005 | (sign_extend:SI |
cd2b37d9 | 9006 | (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9007 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9008 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9009 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9010 | "TARGET_UPDATE" |
1fd4e8c1 | 9011 | "@ |
5f243543 RK |
9012 | lhaux %3,%0,%2 |
9013 | lhau %3,%2(%0)" | |
b54cf83a | 9014 | [(set_attr "type" "load_ext_ux,load_ext_u")]) |
1fd4e8c1 | 9015 | |
38c1f2d7 | 9016 | (define_insn "*movhi_update4" |
cd2b37d9 | 9017 | [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9018 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9019 | (match_operand:HI 3 "gpc_reg_operand" "r,r")) |
9020 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9021 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9022 | "TARGET_UPDATE" |
1fd4e8c1 | 9023 | "@ |
5f243543 | 9024 | sthux %3,%0,%2 |
b7ff3d82 | 9025 | sthu %3,%2(%0)" |
b54cf83a | 9026 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9027 | |
38c1f2d7 | 9028 | (define_insn "*movqi_update1" |
cd2b37d9 RK |
9029 | [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") |
9030 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9031 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9032 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9033 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9034 | "TARGET_UPDATE" |
1fd4e8c1 | 9035 | "@ |
5f243543 RK |
9036 | lbzux %3,%0,%2 |
9037 | lbzu %3,%2(%0)" | |
b54cf83a | 9038 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9039 | |
38c1f2d7 | 9040 | (define_insn "*movqi_update2" |
cd2b37d9 | 9041 | [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 9042 | (zero_extend:SI |
cd2b37d9 | 9043 | (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9044 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) |
cd2b37d9 | 9045 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9046 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9047 | "TARGET_UPDATE" |
1fd4e8c1 | 9048 | "@ |
5f243543 RK |
9049 | lbzux %3,%0,%2 |
9050 | lbzu %3,%2(%0)" | |
b54cf83a | 9051 | [(set_attr "type" "load_ux,load_u")]) |
1fd4e8c1 | 9052 | |
38c1f2d7 | 9053 | (define_insn "*movqi_update3" |
cd2b37d9 | 9054 | [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9055 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9056 | (match_operand:QI 3 "gpc_reg_operand" "r,r")) |
9057 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9058 | (plus:SI (match_dup 1) (match_dup 2)))] |
38c1f2d7 | 9059 | "TARGET_UPDATE" |
1fd4e8c1 | 9060 | "@ |
5f243543 | 9061 | stbux %3,%0,%2 |
b7ff3d82 | 9062 | stbu %3,%2(%0)" |
b54cf83a | 9063 | [(set_attr "type" "store_ux,store_u")]) |
1fd4e8c1 | 9064 | |
38c1f2d7 | 9065 | (define_insn "*movsf_update1" |
cd2b37d9 | 9066 | [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") |
df8b713c | 9067 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9068 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9069 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9070 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9071 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9072 | "@ |
5f243543 RK |
9073 | lfsux %3,%0,%2 |
9074 | lfsu %3,%2(%0)" | |
b54cf83a | 9075 | [(set_attr "type" "fpload_ux,fpload_u")]) |
1fd4e8c1 | 9076 | |
38c1f2d7 | 9077 | (define_insn "*movsf_update2" |
cd2b37d9 | 9078 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9079 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9080 | (match_operand:SF 3 "gpc_reg_operand" "f,f")) |
9081 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9082 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9083 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9084 | "@ |
85fff2f3 | 9085 | stfsux %3,%0,%2 |
b7ff3d82 | 9086 | stfsu %3,%2(%0)" |
b54cf83a | 9087 | [(set_attr "type" "fpstore_ux,fpstore_u")]) |
1fd4e8c1 | 9088 | |
38c1f2d7 MM |
9089 | (define_insn "*movsf_update3" |
9090 | [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") | |
9091 | (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9092 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) | |
9093 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9094 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 9095 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
9096 | "@ |
9097 | {lux|lwzux} %3,%0,%2 | |
9098 | {lu|lwzu} %3,%2(%0)" | |
b54cf83a | 9099 | [(set_attr "type" "load_ux,load_u")]) |
38c1f2d7 MM |
9100 | |
9101 | (define_insn "*movsf_update4" | |
9102 | [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
9103 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) | |
9104 | (match_operand:SF 3 "gpc_reg_operand" "r,r")) | |
9105 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
9106 | (plus:SI (match_dup 1) (match_dup 2)))] | |
a3170dc6 | 9107 | "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" |
38c1f2d7 MM |
9108 | "@ |
9109 | {stux|stwux} %3,%0,%2 | |
9110 | {stu|stwu} %3,%2(%0)" | |
b54cf83a | 9111 | [(set_attr "type" "store_ux,store_u")]) |
38c1f2d7 MM |
9112 | |
9113 | (define_insn "*movdf_update1" | |
cd2b37d9 RK |
9114 | [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") |
9115 | (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") | |
1fd4e8c1 | 9116 | (match_operand:SI 2 "reg_or_short_operand" "r,I")))) |
cd2b37d9 | 9117 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") |
1fd4e8c1 | 9118 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9119 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9120 | "@ |
5f243543 RK |
9121 | lfdux %3,%0,%2 |
9122 | lfdu %3,%2(%0)" | |
b54cf83a | 9123 | [(set_attr "type" "fpload_ux,fpload_u")]) |
1fd4e8c1 | 9124 | |
38c1f2d7 | 9125 | (define_insn "*movdf_update2" |
cd2b37d9 | 9126 | [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") |
1fd4e8c1 | 9127 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))) |
cd2b37d9 RK |
9128 | (match_operand:DF 3 "gpc_reg_operand" "f,f")) |
9129 | (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") | |
1fd4e8c1 | 9130 | (plus:SI (match_dup 1) (match_dup 2)))] |
a3170dc6 | 9131 | "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" |
1fd4e8c1 | 9132 | "@ |
5f243543 | 9133 | stfdux %3,%0,%2 |
b7ff3d82 | 9134 | stfdu %3,%2(%0)" |
b54cf83a | 9135 | [(set_attr "type" "fpstore_ux,fpstore_u")]) |
4c70a4f3 RK |
9136 | |
9137 | ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq. | |
9138 | ||
90f81f99 AP |
9139 | (define_insn "*lfq_power2" |
9140 | [(set (match_operand:TF 0 "gpc_reg_operand" "=f") | |
9141 | (match_operand:TF 1 "memory_operand" ""))] | |
9142 | "TARGET_POWER2 | |
9143 | && TARGET_HARD_FLOAT && TARGET_FPRS" | |
9144 | "lfq%U1%X1 %0,%1") | |
9145 | ||
9146 | (define_peephole2 | |
9147 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
4c70a4f3 | 9148 | (match_operand:DF 1 "memory_operand" "")) |
90f81f99 | 9149 | (set (match_operand:DF 2 "gpc_reg_operand" "") |
4c70a4f3 RK |
9150 | (match_operand:DF 3 "memory_operand" ""))] |
9151 | "TARGET_POWER2 | |
a3170dc6 | 9152 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 | 9153 | && registers_ok_for_quad_peep (operands[0], operands[2]) |
90f81f99 AP |
9154 | && mems_ok_for_quad_peep (operands[1], operands[3])" |
9155 | [(set (match_dup 0) | |
9156 | (match_dup 1))] | |
9157 | "operands[1] = widen_memory_access (operands[1], TFmode, 0); | |
9158 | operands[0] = gen_rtx_REG (TFmode, REGNO (operands[0]));") | |
4c70a4f3 | 9159 | |
90f81f99 AP |
9160 | (define_insn "*stfq_power2" |
9161 | [(set (match_operand:TF 0 "memory_operand" "") | |
9162 | (match_operand:TF 1 "gpc_reg_operand" "f"))] | |
9163 | "TARGET_POWER2 | |
9164 | && TARGET_HARD_FLOAT && TARGET_FPRS" | |
9165 | "stfq%U0%X0 %1,%0") | |
9166 | ||
9167 | ||
9168 | (define_peephole2 | |
4c70a4f3 | 9169 | [(set (match_operand:DF 0 "memory_operand" "") |
90f81f99 | 9170 | (match_operand:DF 1 "gpc_reg_operand" "")) |
4c70a4f3 | 9171 | (set (match_operand:DF 2 "memory_operand" "") |
90f81f99 | 9172 | (match_operand:DF 3 "gpc_reg_operand" ""))] |
4c70a4f3 | 9173 | "TARGET_POWER2 |
a3170dc6 | 9174 | && TARGET_HARD_FLOAT && TARGET_FPRS |
4c70a4f3 | 9175 | && registers_ok_for_quad_peep (operands[1], operands[3]) |
90f81f99 AP |
9176 | && mems_ok_for_quad_peep (operands[0], operands[2])" |
9177 | [(set (match_dup 0) | |
9178 | (match_dup 1))] | |
9179 | "operands[0] = widen_memory_access (operands[0], TFmode, 0); | |
9180 | operands[1] = gen_rtx_REG (TFmode, REGNO (operands[1]));") | |
2f4d9502 NS |
9181 | |
9182 | ;; after inserting conditional returns we can sometimes have | |
9183 | ;; unnecessary register moves. Unfortunately we cannot have a | |
9184 | ;; modeless peephole here, because some single SImode sets have early | |
9185 | ;; clobber outputs. Although those sets expand to multi-ppc-insn | |
9186 | ;; sequences, using get_attr_length here will smash the operands | |
9187 | ;; array. Neither is there an early_cobbler_p predicate. | |
9188 | (define_peephole2 | |
9189 | [(set (match_operand:DF 0 "gpc_reg_operand" "") | |
9190 | (match_operand:DF 1 "any_operand" "")) | |
9191 | (set (match_operand:DF 2 "gpc_reg_operand" "") | |
9192 | (match_dup 0))] | |
9193 | "peep2_reg_dead_p (2, operands[0])" | |
9194 | [(set (match_dup 2) (match_dup 1))]) | |
9195 | ||
9196 | (define_peephole2 | |
9197 | [(set (match_operand:SF 0 "gpc_reg_operand" "") | |
9198 | (match_operand:SF 1 "any_operand" "")) | |
9199 | (set (match_operand:SF 2 "gpc_reg_operand" "") | |
9200 | (match_dup 0))] | |
9201 | "peep2_reg_dead_p (2, operands[0])" | |
9202 | [(set (match_dup 2) (match_dup 1))]) | |
9203 | ||
1fd4e8c1 | 9204 | \f |
c4501e62 JJ |
9205 | ;; TLS support. |
9206 | ||
9207 | ;; "b" output constraint here and on tls_ld to support tls linker optimization. | |
9208 | (define_insn "tls_gd_32" | |
b150f4f3 DE |
9209 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9210 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9211 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9212 | UNSPEC_TLSGD))] | |
9213 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9214 | "addi %0,%1,%2@got@tlsgd") | |
9215 | ||
9216 | (define_insn "tls_gd_64" | |
b150f4f3 DE |
9217 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9218 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9219 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9220 | UNSPEC_TLSGD))] | |
9221 | "HAVE_AS_TLS && TARGET_64BIT" | |
9222 | "addi %0,%1,%2@got@tlsgd") | |
9223 | ||
9224 | (define_insn "tls_ld_32" | |
b150f4f3 DE |
9225 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9226 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b")] | |
c4501e62 JJ |
9227 | UNSPEC_TLSLD))] |
9228 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9229 | "addi %0,%1,%&@got@tlsld") | |
9230 | ||
9231 | (define_insn "tls_ld_64" | |
b150f4f3 DE |
9232 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9233 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b")] | |
c4501e62 JJ |
9234 | UNSPEC_TLSLD))] |
9235 | "HAVE_AS_TLS && TARGET_64BIT" | |
9236 | "addi %0,%1,%&@got@tlsld") | |
9237 | ||
9238 | (define_insn "tls_dtprel_32" | |
b150f4f3 DE |
9239 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9240 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9241 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9242 | UNSPEC_TLSDTPREL))] | |
9243 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9244 | "addi %0,%1,%2@dtprel") | |
9245 | ||
9246 | (define_insn "tls_dtprel_64" | |
b150f4f3 DE |
9247 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9248 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9249 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9250 | UNSPEC_TLSDTPREL))] | |
9251 | "HAVE_AS_TLS && TARGET_64BIT" | |
9252 | "addi %0,%1,%2@dtprel") | |
9253 | ||
9254 | (define_insn "tls_dtprel_ha_32" | |
b150f4f3 DE |
9255 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9256 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9257 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9258 | UNSPEC_TLSDTPRELHA))] | |
9259 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9260 | "addis %0,%1,%2@dtprel@ha") | |
9261 | ||
9262 | (define_insn "tls_dtprel_ha_64" | |
b150f4f3 DE |
9263 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9264 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9265 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9266 | UNSPEC_TLSDTPRELHA))] | |
9267 | "HAVE_AS_TLS && TARGET_64BIT" | |
9268 | "addis %0,%1,%2@dtprel@ha") | |
9269 | ||
9270 | (define_insn "tls_dtprel_lo_32" | |
b150f4f3 DE |
9271 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9272 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9273 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9274 | UNSPEC_TLSDTPRELLO))] | |
9275 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9276 | "addi %0,%1,%2@dtprel@l") | |
9277 | ||
9278 | (define_insn "tls_dtprel_lo_64" | |
b150f4f3 DE |
9279 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9280 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9281 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9282 | UNSPEC_TLSDTPRELLO))] | |
9283 | "HAVE_AS_TLS && TARGET_64BIT" | |
9284 | "addi %0,%1,%2@dtprel@l") | |
9285 | ||
9286 | (define_insn "tls_got_dtprel_32" | |
b150f4f3 DE |
9287 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9288 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9289 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9290 | UNSPEC_TLSGOTDTPREL))] | |
9291 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9292 | "lwz %0,%2@got@dtprel(%1)") | |
9293 | ||
9294 | (define_insn "tls_got_dtprel_64" | |
b150f4f3 DE |
9295 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9296 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9297 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9298 | UNSPEC_TLSGOTDTPREL))] | |
9299 | "HAVE_AS_TLS && TARGET_64BIT" | |
9300 | "ld %0,%2@got@dtprel(%1)") | |
9301 | ||
9302 | (define_insn "tls_tprel_32" | |
b150f4f3 DE |
9303 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9304 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9305 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9306 | UNSPEC_TLSTPREL))] | |
9307 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9308 | "addi %0,%1,%2@tprel") | |
9309 | ||
9310 | (define_insn "tls_tprel_64" | |
b150f4f3 DE |
9311 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9312 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9313 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9314 | UNSPEC_TLSTPREL))] | |
9315 | "HAVE_AS_TLS && TARGET_64BIT" | |
9316 | "addi %0,%1,%2@tprel") | |
9317 | ||
9318 | (define_insn "tls_tprel_ha_32" | |
b150f4f3 DE |
9319 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9320 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9321 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9322 | UNSPEC_TLSTPRELHA))] | |
9323 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9324 | "addis %0,%1,%2@tprel@ha") | |
9325 | ||
9326 | (define_insn "tls_tprel_ha_64" | |
b150f4f3 DE |
9327 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9328 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9329 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9330 | UNSPEC_TLSTPRELHA))] | |
9331 | "HAVE_AS_TLS && TARGET_64BIT" | |
9332 | "addis %0,%1,%2@tprel@ha") | |
9333 | ||
9334 | (define_insn "tls_tprel_lo_32" | |
b150f4f3 DE |
9335 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9336 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9337 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9338 | UNSPEC_TLSTPRELLO))] | |
9339 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9340 | "addi %0,%1,%2@tprel@l") | |
9341 | ||
9342 | (define_insn "tls_tprel_lo_64" | |
b150f4f3 DE |
9343 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9344 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9345 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9346 | UNSPEC_TLSTPRELLO))] | |
9347 | "HAVE_AS_TLS && TARGET_64BIT" | |
9348 | "addi %0,%1,%2@tprel@l") | |
9349 | ||
c1207243 | 9350 | ;; "b" output constraint here and on tls_tls input to support linker tls |
c4501e62 JJ |
9351 | ;; optimization. The linker may edit the instructions emitted by a |
9352 | ;; tls_got_tprel/tls_tls pair to addis,addi. | |
9353 | (define_insn "tls_got_tprel_32" | |
b150f4f3 DE |
9354 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") |
9355 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9356 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9357 | UNSPEC_TLSGOTTPREL))] | |
9358 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9359 | "lwz %0,%2@got@tprel(%1)") | |
9360 | ||
9361 | (define_insn "tls_got_tprel_64" | |
b150f4f3 DE |
9362 | [(set (match_operand:DI 0 "gpc_reg_operand" "=b") |
9363 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9364 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9365 | UNSPEC_TLSGOTTPREL))] | |
9366 | "HAVE_AS_TLS && TARGET_64BIT" | |
9367 | "ld %0,%2@got@tprel(%1)") | |
9368 | ||
9369 | (define_insn "tls_tls_32" | |
b150f4f3 DE |
9370 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
9371 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9372 | (match_operand:SI 2 "rs6000_tls_symbol_ref" "")] |
9373 | UNSPEC_TLSTLS))] | |
9374 | "HAVE_AS_TLS && !TARGET_64BIT" | |
9375 | "add %0,%1,%2@tls") | |
9376 | ||
9377 | (define_insn "tls_tls_64" | |
b150f4f3 DE |
9378 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
9379 | (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "b") | |
c4501e62 JJ |
9380 | (match_operand:DI 2 "rs6000_tls_symbol_ref" "")] |
9381 | UNSPEC_TLSTLS))] | |
9382 | "HAVE_AS_TLS && TARGET_64BIT" | |
9383 | "add %0,%1,%2@tls") | |
9384 | \f | |
1fd4e8c1 RK |
9385 | ;; Next come insns related to the calling sequence. |
9386 | ;; | |
9387 | ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). | |
7e69e155 | 9388 | ;; We move the back-chain and decrement the stack pointer. |
1fd4e8c1 RK |
9389 | |
9390 | (define_expand "allocate_stack" | |
52d3af72 | 9391 | [(set (match_operand 0 "gpc_reg_operand" "=r") |
a260abc9 DE |
9392 | (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) |
9393 | (set (reg 1) | |
9394 | (minus (reg 1) (match_dup 1)))] | |
1fd4e8c1 RK |
9395 | "" |
9396 | " | |
4697a36c | 9397 | { rtx chain = gen_reg_rtx (Pmode); |
39403d82 | 9398 | rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
4697a36c | 9399 | rtx neg_op0; |
1fd4e8c1 RK |
9400 | |
9401 | emit_move_insn (chain, stack_bot); | |
4697a36c | 9402 | |
a157febd GK |
9403 | /* Check stack bounds if necessary. */ |
9404 | if (current_function_limit_stack) | |
9405 | { | |
9406 | rtx available; | |
6ae08853 | 9407 | available = expand_binop (Pmode, sub_optab, |
a157febd GK |
9408 | stack_pointer_rtx, stack_limit_rtx, |
9409 | NULL_RTX, 1, OPTAB_WIDEN); | |
9410 | emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); | |
9411 | } | |
9412 | ||
e9a25f70 JL |
9413 | if (GET_CODE (operands[1]) != CONST_INT |
9414 | || INTVAL (operands[1]) < -32767 | |
9415 | || INTVAL (operands[1]) > 32768) | |
4697a36c MM |
9416 | { |
9417 | neg_op0 = gen_reg_rtx (Pmode); | |
e6ca2c17 | 9418 | if (TARGET_32BIT) |
e9a25f70 | 9419 | emit_insn (gen_negsi2 (neg_op0, operands[1])); |
e6ca2c17 | 9420 | else |
e9a25f70 | 9421 | emit_insn (gen_negdi2 (neg_op0, operands[1])); |
4697a36c MM |
9422 | } |
9423 | else | |
e9a25f70 | 9424 | neg_op0 = GEN_INT (- INTVAL (operands[1])); |
4697a36c | 9425 | |
38c1f2d7 | 9426 | if (TARGET_UPDATE) |
2e6c9641 | 9427 | emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_di_update)) |
38c1f2d7 | 9428 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain)); |
4697a36c | 9429 | |
38c1f2d7 MM |
9430 | else |
9431 | { | |
9432 | emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3)) | |
9433 | (stack_pointer_rtx, stack_pointer_rtx, neg_op0)); | |
39403d82 | 9434 | emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain); |
38c1f2d7 | 9435 | } |
e9a25f70 JL |
9436 | |
9437 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
1fd4e8c1 RK |
9438 | DONE; |
9439 | }") | |
59257ff7 RK |
9440 | |
9441 | ;; These patterns say how to save and restore the stack pointer. We need not | |
9442 | ;; save the stack pointer at function level since we are careful to | |
9443 | ;; preserve the backchain. At block level, we have to restore the backchain | |
9444 | ;; when we restore the stack pointer. | |
9445 | ;; | |
9446 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
9447 | ;; backchain and restore both. Note that in the nonlocal case, the | |
9448 | ;; save area is a memory location. | |
9449 | ||
9450 | (define_expand "save_stack_function" | |
ff381587 MM |
9451 | [(match_operand 0 "any_operand" "") |
9452 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9453 | "" |
ff381587 | 9454 | "DONE;") |
59257ff7 RK |
9455 | |
9456 | (define_expand "restore_stack_function" | |
ff381587 MM |
9457 | [(match_operand 0 "any_operand" "") |
9458 | (match_operand 1 "any_operand" "")] | |
59257ff7 | 9459 | "" |
ff381587 | 9460 | "DONE;") |
59257ff7 RK |
9461 | |
9462 | (define_expand "restore_stack_block" | |
dfdfa60f DE |
9463 | [(use (match_operand 0 "register_operand" "")) |
9464 | (set (match_dup 2) (match_dup 3)) | |
a260abc9 | 9465 | (set (match_dup 0) (match_operand 1 "register_operand" "")) |
dfdfa60f | 9466 | (set (match_dup 3) (match_dup 2))] |
59257ff7 RK |
9467 | "" |
9468 | " | |
dfdfa60f DE |
9469 | { |
9470 | operands[2] = gen_reg_rtx (Pmode); | |
39403d82 | 9471 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); |
dfdfa60f | 9472 | }") |
59257ff7 RK |
9473 | |
9474 | (define_expand "save_stack_nonlocal" | |
a260abc9 DE |
9475 | [(match_operand 0 "memory_operand" "") |
9476 | (match_operand 1 "register_operand" "")] | |
59257ff7 RK |
9477 | "" |
9478 | " | |
9479 | { | |
a260abc9 | 9480 | rtx temp = gen_reg_rtx (Pmode); |
11b25716 | 9481 | int units_per_word = (TARGET_32BIT) ? 4 : 8; |
59257ff7 RK |
9482 | |
9483 | /* Copy the backchain to the first word, sp to the second. */ | |
39403d82 | 9484 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
39e453d7 DE |
9485 | emit_move_insn (adjust_address_nv (operands[0], Pmode, 0), temp); |
9486 | emit_move_insn (adjust_address_nv (operands[0], Pmode, units_per_word), | |
a260abc9 | 9487 | operands[1]); |
59257ff7 RK |
9488 | DONE; |
9489 | }") | |
7e69e155 | 9490 | |
59257ff7 | 9491 | (define_expand "restore_stack_nonlocal" |
a260abc9 DE |
9492 | [(match_operand 0 "register_operand" "") |
9493 | (match_operand 1 "memory_operand" "")] | |
59257ff7 RK |
9494 | "" |
9495 | " | |
9496 | { | |
a260abc9 | 9497 | rtx temp = gen_reg_rtx (Pmode); |
11b25716 | 9498 | int units_per_word = (TARGET_32BIT) ? 4 : 8; |
59257ff7 RK |
9499 | |
9500 | /* Restore the backchain from the first word, sp from the second. */ | |
a260abc9 | 9501 | emit_move_insn (temp, |
39e453d7 | 9502 | adjust_address_nv (operands[1], Pmode, 0)); |
a260abc9 | 9503 | emit_move_insn (operands[0], |
39e453d7 | 9504 | adjust_address_nv (operands[1], Pmode, units_per_word)); |
39403d82 | 9505 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
59257ff7 RK |
9506 | DONE; |
9507 | }") | |
9ebbca7d GK |
9508 | \f |
9509 | ;; TOC register handling. | |
b6c9286a | 9510 | |
9ebbca7d | 9511 | ;; Code to initialize the TOC register... |
f0f6a223 | 9512 | |
9ebbca7d | 9513 | (define_insn "load_toc_aix_si" |
e72247f4 | 9514 | [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
615158e2 | 9515 | (unspec:SI [(const_int 0)] UNSPEC_TOC)) |
46aaf10d | 9516 | (use (reg:SI 2))])] |
2bfcf297 | 9517 | "DEFAULT_ABI == ABI_AIX && TARGET_32BIT" |
f0f6a223 RK |
9518 | "* |
9519 | { | |
9ebbca7d GK |
9520 | char buf[30]; |
9521 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); | |
a8a05998 | 9522 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
9523 | operands[2] = gen_rtx_REG (Pmode, 2); |
9524 | return \"{l|lwz} %0,%1(%2)\"; | |
f0f6a223 RK |
9525 | }" |
9526 | [(set_attr "type" "load")]) | |
9ebbca7d GK |
9527 | |
9528 | (define_insn "load_toc_aix_di" | |
e72247f4 | 9529 | [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
615158e2 | 9530 | (unspec:DI [(const_int 0)] UNSPEC_TOC)) |
46aaf10d | 9531 | (use (reg:DI 2))])] |
2bfcf297 | 9532 | "DEFAULT_ABI == ABI_AIX && TARGET_64BIT" |
9ebbca7d GK |
9533 | "* |
9534 | { | |
9535 | char buf[30]; | |
f585a356 DE |
9536 | #ifdef TARGET_RELOCATABLE |
9537 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", | |
9538 | !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE); | |
9539 | #else | |
9ebbca7d | 9540 | ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); |
f585a356 | 9541 | #endif |
2bfcf297 DB |
9542 | if (TARGET_ELF) |
9543 | strcat (buf, \"@toc\"); | |
a8a05998 | 9544 | operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); |
9ebbca7d GK |
9545 | operands[2] = gen_rtx_REG (Pmode, 2); |
9546 | return \"ld %0,%1(%2)\"; | |
9547 | }" | |
9548 | [(set_attr "type" "load")]) | |
9549 | ||
9550 | (define_insn "load_toc_v4_pic_si" | |
9551 | [(set (match_operand:SI 0 "register_operand" "=l") | |
615158e2 | 9552 | (unspec:SI [(const_int 0)] UNSPEC_TOC))] |
f607bc57 | 9553 | "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT" |
9ebbca7d GK |
9554 | "bl _GLOBAL_OFFSET_TABLE_@local-4" |
9555 | [(set_attr "type" "branch") | |
9556 | (set_attr "length" "4")]) | |
9557 | ||
9ebbca7d GK |
9558 | (define_insn "load_toc_v4_PIC_1" |
9559 | [(set (match_operand:SI 0 "register_operand" "=l") | |
9560 | (match_operand:SI 1 "immediate_operand" "s")) | |
c4501e62 | 9561 | (use (unspec [(match_dup 1)] UNSPEC_TOC))] |
7f970b70 AM |
9562 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX |
9563 | && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))" | |
df7a8989 | 9564 | "bcl 20,31,%1\\n%1:" |
9ebbca7d GK |
9565 | [(set_attr "type" "branch") |
9566 | (set_attr "length" "4")]) | |
9567 | ||
9568 | (define_insn "load_toc_v4_PIC_1b" | |
9569 | [(set (match_operand:SI 0 "register_operand" "=l") | |
0e5be35b | 9570 | (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")] |
c4501e62 | 9571 | UNSPEC_TOCPTR))] |
20b71b17 | 9572 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
0e5be35b | 9573 | "bcl 20,31,$+8\\n\\t.long %1-$" |
9ebbca7d GK |
9574 | [(set_attr "type" "branch") |
9575 | (set_attr "length" "8")]) | |
9576 | ||
9577 | (define_insn "load_toc_v4_PIC_2" | |
f585a356 | 9578 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
a2900460 | 9579 | (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") |
9ebbca7d GK |
9580 | (minus:SI (match_operand:SI 2 "immediate_operand" "s") |
9581 | (match_operand:SI 3 "immediate_operand" "s")))))] | |
20b71b17 | 9582 | "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" |
9ebbca7d GK |
9583 | "{l|lwz} %0,%2-%3(%1)" |
9584 | [(set_attr "type" "load")]) | |
9585 | ||
7f970b70 AM |
9586 | (define_insn "load_toc_v4_PIC_3b" |
9587 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b") | |
9588 | (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
9589 | (high:SI | |
9590 | (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s") | |
9591 | (match_operand:SI 3 "symbol_ref_operand" "s")))))] | |
9592 | "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic" | |
9593 | "{cau|addis} %0,%1,%2-%3@ha") | |
9594 | ||
9595 | (define_insn "load_toc_v4_PIC_3c" | |
9596 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
9597 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
9598 | (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s") | |
9599 | (match_operand:SI 3 "symbol_ref_operand" "s"))))] | |
9600 | "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic" | |
9601 | "{cal|addi} %0,%1,%2-%3@l") | |
f51eee6a | 9602 | |
9ebbca7d GK |
9603 | ;; If the TOC is shared over a translation unit, as happens with all |
9604 | ;; the kinds of PIC that we support, we need to restore the TOC | |
9605 | ;; pointer only when jumping over units of translation. | |
f51eee6a | 9606 | ;; On Darwin, we need to reload the picbase. |
9ebbca7d GK |
9607 | |
9608 | (define_expand "builtin_setjmp_receiver" | |
9609 | [(use (label_ref (match_operand 0 "" "")))] | |
f607bc57 | 9610 | "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) |
f51eee6a GK |
9611 | || (TARGET_TOC && TARGET_MINIMAL_TOC) |
9612 | || (DEFAULT_ABI == ABI_DARWIN && flag_pic)" | |
9ebbca7d GK |
9613 | " |
9614 | { | |
84d7dd4a | 9615 | #if TARGET_MACHO |
f51eee6a GK |
9616 | if (DEFAULT_ABI == ABI_DARWIN) |
9617 | { | |
d24652ee | 9618 | const char *picbase = machopic_function_base_name (); |
485bad26 | 9619 | rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (picbase)); |
f51eee6a GK |
9620 | rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); |
9621 | rtx tmplabrtx; | |
9622 | char tmplab[20]; | |
9623 | ||
9624 | ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\", | |
9625 | CODE_LABEL_NUMBER (operands[0])); | |
485bad26 | 9626 | tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab)); |
f51eee6a | 9627 | |
b8a55285 AP |
9628 | emit_insn (gen_load_macho_picbase (picreg, tmplabrtx)); |
9629 | emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx)); | |
f51eee6a GK |
9630 | } |
9631 | else | |
84d7dd4a | 9632 | #endif |
f51eee6a | 9633 | rs6000_emit_load_toc_table (FALSE); |
9ebbca7d GK |
9634 | DONE; |
9635 | }") | |
7f970b70 AM |
9636 | |
9637 | ;; Elf specific ways of loading addresses for non-PIC code. | |
9638 | ;; The output of this could be r0, but we make a very strong | |
9639 | ;; preference for a base register because it will usually | |
9640 | ;; be needed there. | |
9641 | (define_insn "elf_high" | |
9642 | [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") | |
9643 | (high:SI (match_operand 1 "" "")))] | |
9644 | "TARGET_ELF && ! TARGET_64BIT" | |
9645 | "{liu|lis} %0,%1@ha") | |
9646 | ||
9647 | (define_insn "elf_low" | |
9648 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") | |
9649 | (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") | |
9650 | (match_operand 2 "" "")))] | |
9651 | "TARGET_ELF && ! TARGET_64BIT" | |
9652 | "@ | |
9653 | {cal|la} %0,%2@l(%1) | |
9654 | {ai|addic} %0,%1,%K2") | |
9ebbca7d GK |
9655 | \f |
9656 | ;; A function pointer under AIX is a pointer to a data area whose first word | |
9657 | ;; contains the actual address of the function, whose second word contains a | |
b6c9286a MM |
9658 | ;; pointer to its TOC, and whose third word contains a value to place in the |
9659 | ;; static chain register (r11). Note that if we load the static chain, our | |
1fd4e8c1 | 9660 | ;; "trampoline" need not have any executable code. |
b6c9286a | 9661 | |
cccf3bdc DE |
9662 | (define_expand "call_indirect_aix32" |
9663 | [(set (match_dup 2) | |
9664 | (mem:SI (match_operand:SI 0 "gpc_reg_operand" ""))) | |
9665 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
9666 | (reg:SI 2)) | |
9667 | (set (reg:SI 2) | |
9668 | (mem:SI (plus:SI (match_dup 0) | |
9669 | (const_int 4)))) | |
9670 | (set (reg:SI 11) | |
9671 | (mem:SI (plus:SI (match_dup 0) | |
9672 | (const_int 8)))) | |
9673 | (parallel [(call (mem:SI (match_dup 2)) | |
9674 | (match_operand 1 "" "")) | |
9675 | (use (reg:SI 2)) | |
9676 | (use (reg:SI 11)) | |
9677 | (set (reg:SI 2) | |
9678 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9679 | (clobber (scratch:SI))])] | |
9680 | "TARGET_32BIT" | |
9681 | " | |
9682 | { operands[2] = gen_reg_rtx (SImode); }") | |
b6c9286a | 9683 | |
cccf3bdc DE |
9684 | (define_expand "call_indirect_aix64" |
9685 | [(set (match_dup 2) | |
9686 | (mem:DI (match_operand:DI 0 "gpc_reg_operand" ""))) | |
9687 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
9688 | (reg:DI 2)) | |
9689 | (set (reg:DI 2) | |
9690 | (mem:DI (plus:DI (match_dup 0) | |
9691 | (const_int 8)))) | |
9692 | (set (reg:DI 11) | |
9693 | (mem:DI (plus:DI (match_dup 0) | |
9694 | (const_int 16)))) | |
9695 | (parallel [(call (mem:SI (match_dup 2)) | |
9696 | (match_operand 1 "" "")) | |
9697 | (use (reg:DI 2)) | |
9698 | (use (reg:DI 11)) | |
9699 | (set (reg:DI 2) | |
9700 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
9701 | (clobber (scratch:SI))])] | |
9702 | "TARGET_64BIT" | |
9703 | " | |
9704 | { operands[2] = gen_reg_rtx (DImode); }") | |
b6c9286a | 9705 | |
cccf3bdc DE |
9706 | (define_expand "call_value_indirect_aix32" |
9707 | [(set (match_dup 3) | |
9708 | (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
9709 | (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) | |
9710 | (reg:SI 2)) | |
9711 | (set (reg:SI 2) | |
9712 | (mem:SI (plus:SI (match_dup 1) | |
9713 | (const_int 4)))) | |
9714 | (set (reg:SI 11) | |
9715 | (mem:SI (plus:SI (match_dup 1) | |
9716 | (const_int 8)))) | |
9717 | (parallel [(set (match_operand 0 "" "") | |
9718 | (call (mem:SI (match_dup 3)) | |
9719 | (match_operand 2 "" ""))) | |
9720 | (use (reg:SI 2)) | |
9721 | (use (reg:SI 11)) | |
9722 | (set (reg:SI 2) | |
9723 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
9724 | (clobber (scratch:SI))])] | |
9725 | "TARGET_32BIT" | |
9726 | " | |
9727 | { operands[3] = gen_reg_rtx (SImode); }") | |
b6c9286a | 9728 | |
cccf3bdc DE |
9729 | (define_expand "call_value_indirect_aix64" |
9730 | [(set (match_dup 3) | |
9731 | (mem:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
9732 | (set (mem:DI (plus:DI (reg:DI 1) (const_int 40))) | |
9733 | (reg:DI 2)) | |
9734 | (set (reg:DI 2) | |
9735 | (mem:DI (plus:DI (match_dup 1) | |
9736 | (const_int 8)))) | |
9737 | (set (reg:DI 11) | |
9738 | (mem:DI (plus:DI (match_dup 1) | |
9739 | (const_int 16)))) | |
9740 | (parallel [(set (match_operand 0 "" "") | |
9741 | (call (mem:SI (match_dup 3)) | |
9742 | (match_operand 2 "" ""))) | |
9743 | (use (reg:DI 2)) | |
9744 | (use (reg:DI 11)) | |
9745 | (set (reg:DI 2) | |
9746 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
9747 | (clobber (scratch:SI))])] | |
9748 | "TARGET_64BIT" | |
9749 | " | |
9750 | { operands[3] = gen_reg_rtx (DImode); }") | |
1fd4e8c1 | 9751 | |
b6c9286a | 9752 | ;; Now the definitions for the call and call_value insns |
1fd4e8c1 | 9753 | (define_expand "call" |
a260abc9 | 9754 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) |
1fd4e8c1 | 9755 | (match_operand 1 "" "")) |
4697a36c | 9756 | (use (match_operand 2 "" "")) |
1fd4e8c1 RK |
9757 | (clobber (scratch:SI))])] |
9758 | "" | |
9759 | " | |
9760 | { | |
ee890fe2 | 9761 | #if TARGET_MACHO |
ab82a49f | 9762 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
9763 | operands[0] = machopic_indirect_call_target (operands[0]); |
9764 | #endif | |
9765 | ||
37409796 NS |
9766 | gcc_assert (GET_CODE (operands[0]) == MEM); |
9767 | gcc_assert (GET_CODE (operands[1]) == CONST_INT); | |
1fd4e8c1 RK |
9768 | |
9769 | operands[0] = XEXP (operands[0], 0); | |
7509c759 | 9770 | |
7f970b70 AM |
9771 | if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT |
9772 | && flag_pic | |
9773 | && GET_CODE (operands[0]) == SYMBOL_REF | |
9774 | && !SYMBOL_REF_LOCAL_P (operands[0])) | |
9775 | { | |
9776 | rtx call; | |
9777 | rtvec tmp; | |
9778 | ||
9779 | tmp = gen_rtvec (3, | |
9780 | gen_rtx_CALL (VOIDmode, | |
9781 | gen_rtx_MEM (SImode, operands[0]), | |
9782 | operands[1]), | |
9783 | gen_rtx_USE (VOIDmode, operands[2]), | |
9784 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode))); | |
9785 | call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp)); | |
9786 | use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx); | |
9787 | DONE; | |
9788 | } | |
9789 | ||
6a4cee5f | 9790 | if (GET_CODE (operands[0]) != SYMBOL_REF |
473f51b6 | 9791 | || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0])) |
efdba735 | 9792 | || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0)) |
1fd4e8c1 | 9793 | { |
6a4cee5f MM |
9794 | if (INTVAL (operands[2]) & CALL_LONG) |
9795 | operands[0] = rs6000_longcall_ref (operands[0]); | |
9796 | ||
37409796 NS |
9797 | switch (DEFAULT_ABI) |
9798 | { | |
9799 | case ABI_V4: | |
9800 | case ABI_DARWIN: | |
9801 | operands[0] = force_reg (Pmode, operands[0]); | |
9802 | break; | |
1fd4e8c1 | 9803 | |
37409796 | 9804 | case ABI_AIX: |
cccf3bdc DE |
9805 | /* AIX function pointers are really pointers to a three word |
9806 | area. */ | |
9807 | emit_call_insn (TARGET_32BIT | |
9808 | ? gen_call_indirect_aix32 (force_reg (SImode, | |
9809 | operands[0]), | |
9810 | operands[1]) | |
9811 | : gen_call_indirect_aix64 (force_reg (DImode, | |
9812 | operands[0]), | |
9813 | operands[1])); | |
9814 | DONE; | |
37409796 NS |
9815 | |
9816 | default: | |
9817 | gcc_unreachable (); | |
b6c9286a | 9818 | } |
1fd4e8c1 RK |
9819 | } |
9820 | }") | |
9821 | ||
9822 | (define_expand "call_value" | |
9823 | [(parallel [(set (match_operand 0 "" "") | |
a260abc9 | 9824 | (call (mem:SI (match_operand 1 "address_operand" "")) |
1fd4e8c1 | 9825 | (match_operand 2 "" ""))) |
4697a36c | 9826 | (use (match_operand 3 "" "")) |
1fd4e8c1 RK |
9827 | (clobber (scratch:SI))])] |
9828 | "" | |
9829 | " | |
9830 | { | |
ee890fe2 | 9831 | #if TARGET_MACHO |
ab82a49f | 9832 | if (MACHOPIC_INDIRECT) |
ee890fe2 SS |
9833 | operands[1] = machopic_indirect_call_target (operands[1]); |
9834 | #endif | |
9835 | ||
37409796 NS |
9836 | gcc_assert (GET_CODE (operands[1]) == MEM); |
9837 | gcc_assert (GET_CODE (operands[2]) == CONST_INT); | |
1fd4e8c1 RK |
9838 | |
9839 | operands[1] = XEXP (operands[1], 0); | |
7509c759 | 9840 | |
7f970b70 AM |
9841 | if (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT |
9842 | && flag_pic | |
9843 | && GET_CODE (operands[1]) == SYMBOL_REF | |
9844 | && !SYMBOL_REF_LOCAL_P (operands[1])) | |
9845 | { | |
9846 | rtx call; | |
9847 | rtvec tmp; | |
9848 | ||
9849 | tmp = gen_rtvec (3, | |
9850 | gen_rtx_SET (VOIDmode, | |
9851 | operands[0], | |
9852 | gen_rtx_CALL (VOIDmode, | |
9853 | gen_rtx_MEM (SImode, | |
9854 | operands[1]), | |
9855 | operands[2])), | |
9856 | gen_rtx_USE (VOIDmode, operands[3]), | |
9857 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode))); | |
9858 | call = emit_call_insn (gen_rtx_PARALLEL (VOIDmode, tmp)); | |
9859 | use_reg (&CALL_INSN_FUNCTION_USAGE (call), pic_offset_table_rtx); | |
9860 | DONE; | |
9861 | } | |
9862 | ||
6a4cee5f | 9863 | if (GET_CODE (operands[1]) != SYMBOL_REF |
473f51b6 | 9864 | || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1])) |
efdba735 | 9865 | || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0)) |
1fd4e8c1 | 9866 | { |
6756293c | 9867 | if (INTVAL (operands[3]) & CALL_LONG) |
6a4cee5f MM |
9868 | operands[1] = rs6000_longcall_ref (operands[1]); |
9869 | ||
37409796 NS |
9870 | switch (DEFAULT_ABI) |
9871 | { | |
9872 | case ABI_V4: | |
9873 | case ABI_DARWIN: | |
9874 | operands[1] = force_reg (Pmode, operands[1]); | |
9875 | break; | |
1fd4e8c1 | 9876 | |
37409796 | 9877 | case ABI_AIX: |
cccf3bdc DE |
9878 | /* AIX function pointers are really pointers to a three word |
9879 | area. */ | |
9880 | emit_call_insn (TARGET_32BIT | |
9881 | ? gen_call_value_indirect_aix32 (operands[0], | |
9882 | force_reg (SImode, | |
9883 | operands[1]), | |
9884 | operands[2]) | |
9885 | : gen_call_value_indirect_aix64 (operands[0], | |
9886 | force_reg (DImode, | |
9887 | operands[1]), | |
9888 | operands[2])); | |
9889 | DONE; | |
37409796 NS |
9890 | |
9891 | default: | |
9892 | gcc_unreachable (); | |
b6c9286a | 9893 | } |
1fd4e8c1 RK |
9894 | } |
9895 | }") | |
9896 | ||
04780ee7 | 9897 | ;; Call to function in current module. No TOC pointer reload needed. |
a0ab749a | 9898 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
9899 | ;; either the function was not prototyped, or it was prototyped as a |
9900 | ;; variable argument function. It is > 0 if FP registers were passed | |
9901 | ;; and < 0 if they were not. | |
04780ee7 | 9902 | |
a260abc9 | 9903 | (define_insn "*call_local32" |
4697a36c MM |
9904 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) |
9905 | (match_operand 1 "" "g,g")) | |
9906 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
9907 | (clobber (match_scratch:SI 3 "=l,l"))] | |
5a19791c | 9908 | "(INTVAL (operands[2]) & CALL_LONG) == 0" |
4697a36c MM |
9909 | "* |
9910 | { | |
6a4cee5f MM |
9911 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
9912 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9913 | ||
9914 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
9915 | output_asm_insn (\"creqv 6,6,6\", operands); | |
4697a36c | 9916 | |
a226df46 | 9917 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; |
4697a36c | 9918 | }" |
b7ff3d82 DE |
9919 | [(set_attr "type" "branch") |
9920 | (set_attr "length" "4,8")]) | |
04780ee7 | 9921 | |
a260abc9 DE |
9922 | (define_insn "*call_local64" |
9923 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
9924 | (match_operand 1 "" "g,g")) | |
9925 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
9926 | (clobber (match_scratch:SI 3 "=l,l"))] | |
9927 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
9928 | "* | |
9929 | { | |
9930 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
9931 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9932 | ||
9933 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
9934 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9935 | ||
9936 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; | |
9937 | }" | |
9938 | [(set_attr "type" "branch") | |
9939 | (set_attr "length" "4,8")]) | |
9940 | ||
cccf3bdc | 9941 | (define_insn "*call_value_local32" |
d18dba68 | 9942 | [(set (match_operand 0 "" "") |
a260abc9 DE |
9943 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) |
9944 | (match_operand 2 "" "g,g"))) | |
9945 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
9946 | (clobber (match_scratch:SI 4 "=l,l"))] | |
9947 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
9948 | "* | |
9949 | { | |
9950 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
9951 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9952 | ||
9953 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9954 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9955 | ||
9956 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
9957 | }" | |
9958 | [(set_attr "type" "branch") | |
9959 | (set_attr "length" "4,8")]) | |
9960 | ||
9961 | ||
cccf3bdc | 9962 | (define_insn "*call_value_local64" |
d18dba68 | 9963 | [(set (match_operand 0 "" "") |
a260abc9 DE |
9964 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) |
9965 | (match_operand 2 "" "g,g"))) | |
9966 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
9967 | (clobber (match_scratch:SI 4 "=l,l"))] | |
9968 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
9969 | "* | |
9970 | { | |
9971 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
9972 | output_asm_insn (\"crxor 6,6,6\", operands); | |
9973 | ||
9974 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
9975 | output_asm_insn (\"creqv 6,6,6\", operands); | |
9976 | ||
9977 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; | |
9978 | }" | |
9979 | [(set_attr "type" "branch") | |
9980 | (set_attr "length" "4,8")]) | |
9981 | ||
04780ee7 | 9982 | ;; Call to function which may be in another module. Restore the TOC |
911f679c | 9983 | ;; pointer (r2) after the call unless this is System V. |
a0ab749a | 9984 | ;; Operand2 is nonzero if we are using the V.4 calling sequence and |
4697a36c MM |
9985 | ;; either the function was not prototyped, or it was prototyped as a |
9986 | ;; variable argument function. It is > 0 if FP registers were passed | |
9987 | ;; and < 0 if they were not. | |
04780ee7 | 9988 | |
cccf3bdc | 9989 | (define_insn "*call_indirect_nonlocal_aix32" |
70ae0191 DE |
9990 | [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l")) |
9991 | (match_operand 1 "" "g,g")) | |
cccf3bdc DE |
9992 | (use (reg:SI 2)) |
9993 | (use (reg:SI 11)) | |
9994 | (set (reg:SI 2) | |
9995 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
70ae0191 | 9996 | (clobber (match_scratch:SI 2 "=l,l"))] |
cccf3bdc DE |
9997 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" |
9998 | "b%T0l\;{l|lwz} 2,20(1)" | |
9999 | [(set_attr "type" "jmpreg") | |
10000 | (set_attr "length" "8")]) | |
10001 | ||
a260abc9 | 10002 | (define_insn "*call_nonlocal_aix32" |
cc4d5fec | 10003 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10004 | (match_operand 1 "" "g")) |
10005 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10006 | (clobber (match_scratch:SI 3 "=l"))] | |
10007 | "TARGET_32BIT | |
10008 | && DEFAULT_ABI == ABI_AIX | |
5a19791c | 10009 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10010 | "bl %z0\;%." |
b7ff3d82 | 10011 | [(set_attr "type" "branch") |
cccf3bdc DE |
10012 | (set_attr "length" "8")]) |
10013 | ||
10014 | (define_insn "*call_indirect_nonlocal_aix64" | |
70ae0191 DE |
10015 | [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l")) |
10016 | (match_operand 1 "" "g,g")) | |
cccf3bdc DE |
10017 | (use (reg:DI 2)) |
10018 | (use (reg:DI 11)) | |
10019 | (set (reg:DI 2) | |
10020 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
70ae0191 | 10021 | (clobber (match_scratch:SI 2 "=l,l"))] |
cccf3bdc DE |
10022 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" |
10023 | "b%T0l\;ld 2,40(1)" | |
10024 | [(set_attr "type" "jmpreg") | |
10025 | (set_attr "length" "8")]) | |
59313e4e | 10026 | |
a260abc9 | 10027 | (define_insn "*call_nonlocal_aix64" |
cc4d5fec | 10028 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10029 | (match_operand 1 "" "g")) |
10030 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
10031 | (clobber (match_scratch:SI 3 "=l"))] | |
6ae08853 | 10032 | "TARGET_64BIT |
9ebbca7d | 10033 | && DEFAULT_ABI == ABI_AIX |
a260abc9 | 10034 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
cccf3bdc | 10035 | "bl %z0\;%." |
a260abc9 | 10036 | [(set_attr "type" "branch") |
cccf3bdc | 10037 | (set_attr "length" "8")]) |
7509c759 | 10038 | |
cccf3bdc | 10039 | (define_insn "*call_value_indirect_nonlocal_aix32" |
d18dba68 | 10040 | [(set (match_operand 0 "" "") |
70ae0191 DE |
10041 | (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l")) |
10042 | (match_operand 2 "" "g,g"))) | |
cccf3bdc DE |
10043 | (use (reg:SI 2)) |
10044 | (use (reg:SI 11)) | |
10045 | (set (reg:SI 2) | |
10046 | (mem:SI (plus:SI (reg:SI 1) (const_int 20)))) | |
70ae0191 | 10047 | (clobber (match_scratch:SI 3 "=l,l"))] |
cccf3bdc DE |
10048 | "TARGET_32BIT && DEFAULT_ABI == ABI_AIX" |
10049 | "b%T1l\;{l|lwz} 2,20(1)" | |
10050 | [(set_attr "type" "jmpreg") | |
10051 | (set_attr "length" "8")]) | |
1fd4e8c1 | 10052 | |
cccf3bdc | 10053 | (define_insn "*call_value_nonlocal_aix32" |
d18dba68 | 10054 | [(set (match_operand 0 "" "") |
cc4d5fec | 10055 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10056 | (match_operand 2 "" "g"))) |
10057 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10058 | (clobber (match_scratch:SI 4 "=l"))] | |
10059 | "TARGET_32BIT | |
10060 | && DEFAULT_ABI == ABI_AIX | |
a260abc9 | 10061 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc | 10062 | "bl %z1\;%." |
b7ff3d82 | 10063 | [(set_attr "type" "branch") |
cccf3bdc | 10064 | (set_attr "length" "8")]) |
04780ee7 | 10065 | |
cccf3bdc | 10066 | (define_insn "*call_value_indirect_nonlocal_aix64" |
d18dba68 | 10067 | [(set (match_operand 0 "" "") |
70ae0191 DE |
10068 | (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l")) |
10069 | (match_operand 2 "" "g,g"))) | |
cccf3bdc DE |
10070 | (use (reg:DI 2)) |
10071 | (use (reg:DI 11)) | |
10072 | (set (reg:DI 2) | |
10073 | (mem:DI (plus:DI (reg:DI 1) (const_int 40)))) | |
70ae0191 | 10074 | (clobber (match_scratch:SI 3 "=l,l"))] |
cccf3bdc DE |
10075 | "TARGET_64BIT && DEFAULT_ABI == ABI_AIX" |
10076 | "b%T1l\;ld 2,40(1)" | |
10077 | [(set_attr "type" "jmpreg") | |
10078 | (set_attr "length" "8")]) | |
10079 | ||
10080 | (define_insn "*call_value_nonlocal_aix64" | |
d18dba68 | 10081 | [(set (match_operand 0 "" "") |
cc4d5fec | 10082 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) |
cccf3bdc DE |
10083 | (match_operand 2 "" "g"))) |
10084 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
10085 | (clobber (match_scratch:SI 4 "=l"))] | |
6ae08853 | 10086 | "TARGET_64BIT |
9ebbca7d | 10087 | && DEFAULT_ABI == ABI_AIX |
5a19791c | 10088 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
cccf3bdc DE |
10089 | "bl %z1\;%." |
10090 | [(set_attr "type" "branch") | |
10091 | (set_attr "length" "8")]) | |
10092 | ||
10093 | ;; A function pointer under System V is just a normal pointer | |
10094 | ;; operands[0] is the function pointer | |
10095 | ;; operands[1] is the stack size to clean up | |
10096 | ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument | |
10097 | ;; which indicates how to set cr1 | |
10098 | ||
a5c76ee6 | 10099 | (define_insn "*call_indirect_nonlocal_sysv" |
6d0a8091 DJ |
10100 | [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l,c,*l")) |
10101 | (match_operand 1 "" "g,g,g,g")) | |
10102 | (use (match_operand:SI 2 "immediate_operand" "O,O,n,n")) | |
10103 | (clobber (match_scratch:SI 3 "=l,l,l,l"))] | |
50d440bc | 10104 | "DEFAULT_ABI == ABI_V4 |
f607bc57 | 10105 | || DEFAULT_ABI == ABI_DARWIN" |
911f679c | 10106 | { |
cccf3bdc | 10107 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10108 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f | 10109 | |
cccf3bdc | 10110 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) |
a5c76ee6 | 10111 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10112 | |
a5c76ee6 ZW |
10113 | return "b%T0l"; |
10114 | } | |
6d0a8091 DJ |
10115 | [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg") |
10116 | (set_attr "length" "4,4,8,8")]) | |
cccf3bdc | 10117 | |
a5c76ee6 ZW |
10118 | (define_insn "*call_nonlocal_sysv" |
10119 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10120 | (match_operand 1 "" "g,g")) | |
10121 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
10122 | (clobber (match_scratch:SI 3 "=l,l"))] | |
efdba735 SH |
10123 | "(DEFAULT_ABI == ABI_DARWIN |
10124 | || (DEFAULT_ABI == ABI_V4 | |
10125 | && (INTVAL (operands[2]) & CALL_LONG) == 0))" | |
a5c76ee6 ZW |
10126 | { |
10127 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10128 | output_asm_insn ("crxor 6,6,6", operands); | |
10129 | ||
10130 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10131 | output_asm_insn ("creqv 6,6,6", operands); | |
10132 | ||
c989f2f7 | 10133 | #if TARGET_MACHO |
efdba735 SH |
10134 | return output_call(insn, operands, 0, 2); |
10135 | #else | |
7f970b70 AM |
10136 | if (DEFAULT_ABI == ABI_V4 && flag_pic) |
10137 | { | |
10138 | if (TARGET_SECURE_PLT && flag_pic == 2) | |
10139 | /* The magic 32768 offset here and in the other sysv call insns | |
10140 | corresponds to the offset of r30 in .got2, as given by LCTOC1. | |
10141 | See sysv4.h:toc_section. */ | |
10142 | return "bl %z0+32768@plt"; | |
10143 | else | |
10144 | return "bl %z0@plt"; | |
10145 | } | |
10146 | else | |
10147 | return "bl %z0"; | |
6ae08853 | 10148 | #endif |
a5c76ee6 ZW |
10149 | } |
10150 | [(set_attr "type" "branch,branch") | |
10151 | (set_attr "length" "4,8")]) | |
10152 | ||
10153 | (define_insn "*call_value_indirect_nonlocal_sysv" | |
d18dba68 | 10154 | [(set (match_operand 0 "" "") |
6d0a8091 DJ |
10155 | (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l,c,*l")) |
10156 | (match_operand 2 "" "g,g,g,g"))) | |
10157 | (use (match_operand:SI 3 "immediate_operand" "O,O,n,n")) | |
10158 | (clobber (match_scratch:SI 4 "=l,l,l,l"))] | |
50d440bc | 10159 | "DEFAULT_ABI == ABI_V4 |
f607bc57 | 10160 | || DEFAULT_ABI == ABI_DARWIN" |
b6c9286a | 10161 | { |
6a4cee5f | 10162 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) |
a5c76ee6 | 10163 | output_asm_insn ("crxor 6,6,6", operands); |
6a4cee5f MM |
10164 | |
10165 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
a5c76ee6 | 10166 | output_asm_insn ("creqv 6,6,6", operands); |
7509c759 | 10167 | |
a5c76ee6 ZW |
10168 | return "b%T1l"; |
10169 | } | |
6d0a8091 DJ |
10170 | [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg") |
10171 | (set_attr "length" "4,4,8,8")]) | |
a5c76ee6 ZW |
10172 | |
10173 | (define_insn "*call_value_nonlocal_sysv" | |
10174 | [(set (match_operand 0 "" "") | |
10175 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10176 | (match_operand 2 "" "g,g"))) | |
10177 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
10178 | (clobber (match_scratch:SI 4 "=l,l"))] | |
efdba735 SH |
10179 | "(DEFAULT_ABI == ABI_DARWIN |
10180 | || (DEFAULT_ABI == ABI_V4 | |
10181 | && (INTVAL (operands[3]) & CALL_LONG) == 0))" | |
a5c76ee6 ZW |
10182 | { |
10183 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10184 | output_asm_insn ("crxor 6,6,6", operands); | |
10185 | ||
10186 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10187 | output_asm_insn ("creqv 6,6,6", operands); | |
10188 | ||
c989f2f7 | 10189 | #if TARGET_MACHO |
efdba735 SH |
10190 | return output_call(insn, operands, 1, 3); |
10191 | #else | |
7f970b70 AM |
10192 | if (DEFAULT_ABI == ABI_V4 && flag_pic) |
10193 | { | |
10194 | if (TARGET_SECURE_PLT && flag_pic == 2) | |
10195 | return "bl %z1+32768@plt"; | |
10196 | else | |
10197 | return "bl %z1@plt"; | |
10198 | } | |
10199 | else | |
10200 | return "bl %z1"; | |
6ae08853 | 10201 | #endif |
a5c76ee6 ZW |
10202 | } |
10203 | [(set_attr "type" "branch,branch") | |
10204 | (set_attr "length" "4,8")]) | |
e6f948e3 RK |
10205 | |
10206 | ;; Call subroutine returning any type. | |
e6f948e3 RK |
10207 | (define_expand "untyped_call" |
10208 | [(parallel [(call (match_operand 0 "" "") | |
10209 | (const_int 0)) | |
10210 | (match_operand 1 "" "") | |
10211 | (match_operand 2 "" "")])] | |
10212 | "" | |
10213 | " | |
10214 | { | |
10215 | int i; | |
10216 | ||
7d70b8b2 | 10217 | emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); |
e6f948e3 RK |
10218 | |
10219 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
10220 | { | |
10221 | rtx set = XVECEXP (operands[2], 0, i); | |
10222 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
10223 | } | |
10224 | ||
10225 | /* The optimizer does not know that the call sets the function value | |
10226 | registers we stored in the result block. We avoid problems by | |
10227 | claiming that all hard registers are used and clobbered at this | |
10228 | point. */ | |
10229 | emit_insn (gen_blockage ()); | |
10230 | ||
10231 | DONE; | |
10232 | }") | |
10233 | ||
5e1bf043 DJ |
10234 | ;; sibling call patterns |
10235 | (define_expand "sibcall" | |
10236 | [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) | |
10237 | (match_operand 1 "" "")) | |
10238 | (use (match_operand 2 "" "")) | |
fe352c29 | 10239 | (use (match_operand 3 "" "")) |
5e1bf043 DJ |
10240 | (return)])] |
10241 | "" | |
10242 | " | |
10243 | { | |
10244 | #if TARGET_MACHO | |
ab82a49f | 10245 | if (MACHOPIC_INDIRECT) |
5e1bf043 DJ |
10246 | operands[0] = machopic_indirect_call_target (operands[0]); |
10247 | #endif | |
10248 | ||
37409796 NS |
10249 | gcc_assert (GET_CODE (operands[0]) == MEM); |
10250 | gcc_assert (GET_CODE (operands[1]) == CONST_INT); | |
5e1bf043 DJ |
10251 | |
10252 | operands[0] = XEXP (operands[0], 0); | |
fe352c29 | 10253 | operands[3] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
10254 | |
10255 | }") | |
10256 | ||
10257 | ;; this and similar patterns must be marked as using LR, otherwise | |
10258 | ;; dataflow will try to delete the store into it. This is true | |
10259 | ;; even when the actual reg to jump to is in CTR, when LR was | |
10260 | ;; saved and restored around the PIC-setting BCL. | |
10261 | (define_insn "*sibcall_local32" | |
10262 | [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) | |
10263 | (match_operand 1 "" "g,g")) | |
10264 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 10265 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10266 | (return)] |
10267 | "(INTVAL (operands[2]) & CALL_LONG) == 0" | |
10268 | "* | |
10269 | { | |
10270 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10271 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10272 | ||
10273 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10274 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10275 | ||
10276 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
10277 | }" | |
10278 | [(set_attr "type" "branch") | |
10279 | (set_attr "length" "4,8")]) | |
10280 | ||
10281 | (define_insn "*sibcall_local64" | |
10282 | [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) | |
10283 | (match_operand 1 "" "g,g")) | |
10284 | (use (match_operand:SI 2 "immediate_operand" "O,n")) | |
fe352c29 | 10285 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10286 | (return)] |
10287 | "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10288 | "* | |
10289 | { | |
10290 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10291 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10292 | ||
10293 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10294 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10295 | ||
10296 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; | |
10297 | }" | |
10298 | [(set_attr "type" "branch") | |
10299 | (set_attr "length" "4,8")]) | |
10300 | ||
10301 | (define_insn "*sibcall_value_local32" | |
10302 | [(set (match_operand 0 "" "") | |
10303 | (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) | |
10304 | (match_operand 2 "" "g,g"))) | |
10305 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10306 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10307 | (return)] |
10308 | "(INTVAL (operands[3]) & CALL_LONG) == 0" | |
10309 | "* | |
10310 | { | |
10311 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10312 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10313 | ||
10314 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10315 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10316 | ||
10317 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
10318 | }" | |
10319 | [(set_attr "type" "branch") | |
10320 | (set_attr "length" "4,8")]) | |
10321 | ||
10322 | ||
10323 | (define_insn "*sibcall_value_local64" | |
10324 | [(set (match_operand 0 "" "") | |
10325 | (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) | |
10326 | (match_operand 2 "" "g,g"))) | |
10327 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10328 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10329 | (return)] |
10330 | "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10331 | "* | |
10332 | { | |
10333 | if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) | |
10334 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10335 | ||
10336 | else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) | |
10337 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10338 | ||
10339 | return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; | |
10340 | }" | |
10341 | [(set_attr "type" "branch") | |
10342 | (set_attr "length" "4,8")]) | |
10343 | ||
10344 | (define_insn "*sibcall_nonlocal_aix32" | |
10345 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) | |
10346 | (match_operand 1 "" "g")) | |
10347 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 10348 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 DJ |
10349 | (return)] |
10350 | "TARGET_32BIT | |
10351 | && DEFAULT_ABI == ABI_AIX | |
10352 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10353 | "b %z0" | |
10354 | [(set_attr "type" "branch") | |
10355 | (set_attr "length" "4")]) | |
10356 | ||
10357 | (define_insn "*sibcall_nonlocal_aix64" | |
10358 | [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) | |
10359 | (match_operand 1 "" "g")) | |
10360 | (use (match_operand:SI 2 "immediate_operand" "O")) | |
fe352c29 | 10361 | (use (match_operand:SI 3 "register_operand" "l")) |
5e1bf043 | 10362 | (return)] |
6ae08853 | 10363 | "TARGET_64BIT |
5e1bf043 DJ |
10364 | && DEFAULT_ABI == ABI_AIX |
10365 | && (INTVAL (operands[2]) & CALL_LONG) == 0" | |
10366 | "b %z0" | |
10367 | [(set_attr "type" "branch") | |
10368 | (set_attr "length" "4")]) | |
10369 | ||
10370 | (define_insn "*sibcall_value_nonlocal_aix32" | |
10371 | [(set (match_operand 0 "" "") | |
10372 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) | |
10373 | (match_operand 2 "" "g"))) | |
10374 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 10375 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 DJ |
10376 | (return)] |
10377 | "TARGET_32BIT | |
10378 | && DEFAULT_ABI == ABI_AIX | |
10379 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10380 | "b %z1" | |
10381 | [(set_attr "type" "branch") | |
10382 | (set_attr "length" "4")]) | |
10383 | ||
10384 | (define_insn "*sibcall_value_nonlocal_aix64" | |
10385 | [(set (match_operand 0 "" "") | |
10386 | (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) | |
10387 | (match_operand 2 "" "g"))) | |
10388 | (use (match_operand:SI 3 "immediate_operand" "O")) | |
fe352c29 | 10389 | (use (match_operand:SI 4 "register_operand" "l")) |
5e1bf043 | 10390 | (return)] |
6ae08853 | 10391 | "TARGET_64BIT |
5e1bf043 DJ |
10392 | && DEFAULT_ABI == ABI_AIX |
10393 | && (INTVAL (operands[3]) & CALL_LONG) == 0" | |
10394 | "b %z1" | |
10395 | [(set_attr "type" "branch") | |
10396 | (set_attr "length" "4")]) | |
10397 | ||
10398 | (define_insn "*sibcall_nonlocal_sysv" | |
10399 | [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) | |
10400 | (match_operand 1 "" "")) | |
10401 | (use (match_operand 2 "immediate_operand" "O,n")) | |
fe352c29 | 10402 | (use (match_operand:SI 3 "register_operand" "l,l")) |
5e1bf043 DJ |
10403 | (return)] |
10404 | "(DEFAULT_ABI == ABI_DARWIN | |
50d440bc | 10405 | || DEFAULT_ABI == ABI_V4) |
5e1bf043 DJ |
10406 | && (INTVAL (operands[2]) & CALL_LONG) == 0" |
10407 | "* | |
10408 | { | |
10409 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10410 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10411 | ||
10412 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10413 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10414 | ||
7f970b70 AM |
10415 | if (DEFAULT_ABI == ABI_V4 && flag_pic) |
10416 | { | |
10417 | if (TARGET_SECURE_PLT && flag_pic == 2) | |
10418 | return \"b %z0+32768@plt\"; | |
10419 | else | |
10420 | return \"b %z0@plt\"; | |
10421 | } | |
10422 | else | |
10423 | return \"b %z0\"; | |
5e1bf043 DJ |
10424 | }" |
10425 | [(set_attr "type" "branch,branch") | |
10426 | (set_attr "length" "4,8")]) | |
10427 | ||
10428 | (define_expand "sibcall_value" | |
10429 | [(parallel [(set (match_operand 0 "register_operand" "") | |
10430 | (call (mem:SI (match_operand 1 "address_operand" "")) | |
10431 | (match_operand 2 "" ""))) | |
10432 | (use (match_operand 3 "" "")) | |
fe352c29 | 10433 | (use (match_operand 4 "" "")) |
5e1bf043 DJ |
10434 | (return)])] |
10435 | "" | |
10436 | " | |
10437 | { | |
10438 | #if TARGET_MACHO | |
ab82a49f | 10439 | if (MACHOPIC_INDIRECT) |
5e1bf043 DJ |
10440 | operands[1] = machopic_indirect_call_target (operands[1]); |
10441 | #endif | |
10442 | ||
37409796 NS |
10443 | gcc_assert (GET_CODE (operands[1]) == MEM); |
10444 | gcc_assert (GET_CODE (operands[2]) == CONST_INT); | |
5e1bf043 DJ |
10445 | |
10446 | operands[1] = XEXP (operands[1], 0); | |
fe352c29 | 10447 | operands[4] = gen_reg_rtx (SImode); |
5e1bf043 DJ |
10448 | |
10449 | }") | |
10450 | ||
10451 | (define_insn "*sibcall_value_nonlocal_sysv" | |
10452 | [(set (match_operand 0 "" "") | |
10453 | (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) | |
10454 | (match_operand 2 "" ""))) | |
10455 | (use (match_operand:SI 3 "immediate_operand" "O,n")) | |
fe352c29 | 10456 | (use (match_operand:SI 4 "register_operand" "l,l")) |
5e1bf043 DJ |
10457 | (return)] |
10458 | "(DEFAULT_ABI == ABI_DARWIN | |
50d440bc | 10459 | || DEFAULT_ABI == ABI_V4) |
5e1bf043 DJ |
10460 | && (INTVAL (operands[3]) & CALL_LONG) == 0" |
10461 | "* | |
10462 | { | |
10463 | if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) | |
10464 | output_asm_insn (\"crxor 6,6,6\", operands); | |
10465 | ||
10466 | else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) | |
10467 | output_asm_insn (\"creqv 6,6,6\", operands); | |
10468 | ||
7f970b70 AM |
10469 | if (DEFAULT_ABI == ABI_V4 && flag_pic) |
10470 | { | |
10471 | if (TARGET_SECURE_PLT && flag_pic == 2) | |
10472 | return \"b %z1+32768@plt\"; | |
10473 | else | |
10474 | return \"b %z1@plt\"; | |
10475 | } | |
10476 | else | |
10477 | return \"b %z1\"; | |
5e1bf043 DJ |
10478 | }" |
10479 | [(set_attr "type" "branch,branch") | |
10480 | (set_attr "length" "4,8")]) | |
10481 | ||
10482 | (define_expand "sibcall_epilogue" | |
10483 | [(use (const_int 0))] | |
10484 | "TARGET_SCHED_PROLOG" | |
10485 | " | |
10486 | { | |
10487 | rs6000_emit_epilogue (TRUE); | |
10488 | DONE; | |
10489 | }") | |
10490 | ||
e6f948e3 RK |
10491 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and |
10492 | ;; all of memory. This blocks insns from being moved across this point. | |
10493 | ||
10494 | (define_insn "blockage" | |
615158e2 | 10495 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)] |
e6f948e3 RK |
10496 | "" |
10497 | "") | |
1fd4e8c1 RK |
10498 | \f |
10499 | ;; Compare insns are next. Note that the RS/6000 has two types of compares, | |
7e69e155 | 10500 | ;; signed & unsigned, and one type of branch. |
1fd4e8c1 RK |
10501 | ;; |
10502 | ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc | |
10503 | ;; insns, and branches. We store the operands of compares until we see | |
10504 | ;; how it is used. | |
4ae234b0 | 10505 | (define_expand "cmp<mode>" |
1fd4e8c1 | 10506 | [(set (cc0) |
4ae234b0 GK |
10507 | (compare (match_operand:GPR 0 "gpc_reg_operand" "") |
10508 | (match_operand:GPR 1 "reg_or_short_operand" "")))] | |
1fd4e8c1 RK |
10509 | "" |
10510 | " | |
10511 | { | |
10512 | /* Take care of the possibility that operands[1] might be negative but | |
10513 | this might be a logical operation. That insn doesn't exist. */ | |
10514 | if (GET_CODE (operands[1]) == CONST_INT | |
10515 | && INTVAL (operands[1]) < 0) | |
4ae234b0 | 10516 | operands[1] = force_reg (<MODE>mode, operands[1]); |
1fd4e8c1 RK |
10517 | |
10518 | rs6000_compare_op0 = operands[0]; | |
10519 | rs6000_compare_op1 = operands[1]; | |
10520 | rs6000_compare_fp_p = 0; | |
10521 | DONE; | |
10522 | }") | |
10523 | ||
4ae234b0 GK |
10524 | (define_expand "cmp<mode>" |
10525 | [(set (cc0) (compare (match_operand:FP 0 "gpc_reg_operand" "") | |
10526 | (match_operand:FP 1 "gpc_reg_operand" "")))] | |
10527 | "" | |
d6f99ca4 DE |
10528 | " |
10529 | { | |
10530 | rs6000_compare_op0 = operands[0]; | |
10531 | rs6000_compare_op1 = operands[1]; | |
10532 | rs6000_compare_fp_p = 1; | |
10533 | DONE; | |
10534 | }") | |
10535 | ||
1fd4e8c1 | 10536 | (define_expand "beq" |
39a10a29 | 10537 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10538 | "" |
39a10a29 | 10539 | "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
10540 | |
10541 | (define_expand "bne" | |
39a10a29 | 10542 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10543 | "" |
39a10a29 | 10544 | "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }") |
1fd4e8c1 | 10545 | |
39a10a29 GK |
10546 | (define_expand "bge" |
10547 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10548 | "" |
39a10a29 | 10549 | "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }") |
1fd4e8c1 RK |
10550 | |
10551 | (define_expand "bgt" | |
39a10a29 | 10552 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10553 | "" |
39a10a29 | 10554 | "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }") |
1fd4e8c1 RK |
10555 | |
10556 | (define_expand "ble" | |
39a10a29 | 10557 | [(use (match_operand 0 "" ""))] |
1fd4e8c1 | 10558 | "" |
39a10a29 | 10559 | "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }") |
1fd4e8c1 | 10560 | |
39a10a29 GK |
10561 | (define_expand "blt" |
10562 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10563 | "" |
39a10a29 | 10564 | "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }") |
1fd4e8c1 | 10565 | |
39a10a29 GK |
10566 | (define_expand "bgeu" |
10567 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10568 | "" |
39a10a29 | 10569 | "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }") |
1fd4e8c1 | 10570 | |
39a10a29 GK |
10571 | (define_expand "bgtu" |
10572 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10573 | "" |
39a10a29 | 10574 | "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 10575 | |
39a10a29 GK |
10576 | (define_expand "bleu" |
10577 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10578 | "" |
39a10a29 | 10579 | "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }") |
1fd4e8c1 | 10580 | |
39a10a29 GK |
10581 | (define_expand "bltu" |
10582 | [(use (match_operand 0 "" ""))] | |
1fd4e8c1 | 10583 | "" |
39a10a29 | 10584 | "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 10585 | |
1c882ea4 | 10586 | (define_expand "bunordered" |
39a10a29 | 10587 | [(use (match_operand 0 "" ""))] |
7a1bf2f9 | 10588 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
39a10a29 | 10589 | "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
10590 | |
10591 | (define_expand "bordered" | |
39a10a29 | 10592 | [(use (match_operand 0 "" ""))] |
7a1bf2f9 | 10593 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
39a10a29 | 10594 | "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }") |
1c882ea4 GK |
10595 | |
10596 | (define_expand "buneq" | |
39a10a29 | 10597 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10598 | "" |
39a10a29 | 10599 | "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }") |
1c882ea4 GK |
10600 | |
10601 | (define_expand "bunge" | |
39a10a29 | 10602 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10603 | "" |
39a10a29 | 10604 | "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }") |
1c882ea4 GK |
10605 | |
10606 | (define_expand "bungt" | |
39a10a29 | 10607 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10608 | "" |
39a10a29 | 10609 | "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }") |
1c882ea4 GK |
10610 | |
10611 | (define_expand "bunle" | |
39a10a29 | 10612 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10613 | "" |
39a10a29 | 10614 | "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }") |
1c882ea4 GK |
10615 | |
10616 | (define_expand "bunlt" | |
39a10a29 | 10617 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10618 | "" |
39a10a29 | 10619 | "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }") |
1c882ea4 GK |
10620 | |
10621 | (define_expand "bltgt" | |
39a10a29 | 10622 | [(use (match_operand 0 "" ""))] |
1c882ea4 | 10623 | "" |
39a10a29 | 10624 | "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }") |
1c882ea4 | 10625 | |
1fd4e8c1 RK |
10626 | ;; For SNE, we would prefer that the xor/abs sequence be used for integers. |
10627 | ;; For SEQ, likewise, except that comparisons with zero should be done | |
10628 | ;; with an scc insns. However, due to the order that combine see the | |
10629 | ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in | |
10630 | ;; the cases we don't want to handle. | |
10631 | (define_expand "seq" | |
39a10a29 | 10632 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10633 | "" |
39a10a29 | 10634 | "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }") |
1fd4e8c1 RK |
10635 | |
10636 | (define_expand "sne" | |
39a10a29 | 10637 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10638 | "" |
10639 | " | |
6ae08853 | 10640 | { |
39a10a29 | 10641 | if (! rs6000_compare_fp_p) |
1fd4e8c1 RK |
10642 | FAIL; |
10643 | ||
6ae08853 | 10644 | rs6000_emit_sCOND (NE, operands[0]); |
39a10a29 | 10645 | DONE; |
1fd4e8c1 RK |
10646 | }") |
10647 | ||
b7053a3f GK |
10648 | ;; A >= 0 is best done the portable way for A an integer. |
10649 | (define_expand "sge" | |
39a10a29 | 10650 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10651 | "" |
10652 | " | |
5638268e | 10653 | { |
e56d7409 | 10654 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) |
1fd4e8c1 RK |
10655 | FAIL; |
10656 | ||
b7053a3f | 10657 | rs6000_emit_sCOND (GE, operands[0]); |
39a10a29 | 10658 | DONE; |
1fd4e8c1 RK |
10659 | }") |
10660 | ||
b7053a3f GK |
10661 | ;; A > 0 is best done using the portable sequence, so fail in that case. |
10662 | (define_expand "sgt" | |
39a10a29 | 10663 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10664 | "" |
10665 | " | |
5638268e | 10666 | { |
e56d7409 | 10667 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) |
1fd4e8c1 RK |
10668 | FAIL; |
10669 | ||
6ae08853 | 10670 | rs6000_emit_sCOND (GT, operands[0]); |
39a10a29 | 10671 | DONE; |
1fd4e8c1 RK |
10672 | }") |
10673 | ||
b7053a3f GK |
10674 | ;; A <= 0 is best done the portable way for A an integer. |
10675 | (define_expand "sle" | |
39a10a29 | 10676 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10677 | "" |
5638268e DE |
10678 | " |
10679 | { | |
e56d7409 | 10680 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) |
5638268e DE |
10681 | FAIL; |
10682 | ||
6ae08853 | 10683 | rs6000_emit_sCOND (LE, operands[0]); |
5638268e DE |
10684 | DONE; |
10685 | }") | |
1fd4e8c1 | 10686 | |
b7053a3f GK |
10687 | ;; A < 0 is best done in the portable way for A an integer. |
10688 | (define_expand "slt" | |
39a10a29 | 10689 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 RK |
10690 | "" |
10691 | " | |
5638268e | 10692 | { |
e56d7409 | 10693 | if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx) |
1fd4e8c1 RK |
10694 | FAIL; |
10695 | ||
6ae08853 | 10696 | rs6000_emit_sCOND (LT, operands[0]); |
39a10a29 | 10697 | DONE; |
1fd4e8c1 RK |
10698 | }") |
10699 | ||
b7053a3f GK |
10700 | (define_expand "sgeu" |
10701 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10702 | "" | |
10703 | "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }") | |
10704 | ||
1fd4e8c1 | 10705 | (define_expand "sgtu" |
39a10a29 | 10706 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10707 | "" |
39a10a29 | 10708 | "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }") |
1fd4e8c1 | 10709 | |
b7053a3f GK |
10710 | (define_expand "sleu" |
10711 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10712 | "" | |
10713 | "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }") | |
10714 | ||
1fd4e8c1 | 10715 | (define_expand "sltu" |
39a10a29 | 10716 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
1fd4e8c1 | 10717 | "" |
39a10a29 | 10718 | "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }") |
1fd4e8c1 | 10719 | |
b7053a3f | 10720 | (define_expand "sunordered" |
39a10a29 | 10721 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
7836a61f | 10722 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
b7053a3f | 10723 | "{ rs6000_emit_sCOND (UNORDERED, operands[0]); DONE; }") |
1fd4e8c1 | 10724 | |
b7053a3f | 10725 | (define_expand "sordered" |
39a10a29 | 10726 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] |
7836a61f | 10727 | "! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)" |
b7053a3f GK |
10728 | "{ rs6000_emit_sCOND (ORDERED, operands[0]); DONE; }") |
10729 | ||
10730 | (define_expand "suneq" | |
10731 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10732 | "" | |
10733 | "{ rs6000_emit_sCOND (UNEQ, operands[0]); DONE; }") | |
10734 | ||
10735 | (define_expand "sunge" | |
10736 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10737 | "" | |
10738 | "{ rs6000_emit_sCOND (UNGE, operands[0]); DONE; }") | |
10739 | ||
10740 | (define_expand "sungt" | |
10741 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10742 | "" | |
10743 | "{ rs6000_emit_sCOND (UNGT, operands[0]); DONE; }") | |
10744 | ||
10745 | (define_expand "sunle" | |
10746 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10747 | "" | |
10748 | "{ rs6000_emit_sCOND (UNLE, operands[0]); DONE; }") | |
10749 | ||
10750 | (define_expand "sunlt" | |
10751 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10752 | "" | |
10753 | "{ rs6000_emit_sCOND (UNLT, operands[0]); DONE; }") | |
10754 | ||
10755 | (define_expand "sltgt" | |
10756 | [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))] | |
10757 | "" | |
10758 | "{ rs6000_emit_sCOND (LTGT, operands[0]); DONE; }") | |
10759 | ||
1fd4e8c1 RK |
10760 | \f |
10761 | ;; Here are the actual compare insns. | |
4ae234b0 | 10762 | (define_insn "*cmp<mode>_internal1" |
1fd4e8c1 | 10763 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
4ae234b0 GK |
10764 | (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r") |
10765 | (match_operand:GPR 2 "reg_or_short_operand" "rI")))] | |
1fd4e8c1 | 10766 | "" |
4ae234b0 | 10767 | "{cmp%I2|cmp<wd>%I2} %0,%1,%2" |
b54cf83a | 10768 | [(set_attr "type" "cmp")]) |
266eb58a | 10769 | |
f357808b RK |
10770 | ;; If we are comparing a register for equality with a large constant, |
10771 | ;; we can do this with an XOR followed by a compare. But we need a scratch | |
10772 | ;; register for the result of the XOR. | |
10773 | ||
10774 | (define_split | |
10775 | [(set (match_operand:CC 0 "cc_reg_operand" "") | |
cd2b37d9 | 10776 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
f357808b | 10777 | (match_operand:SI 2 "non_short_cint_operand" ""))) |
cd2b37d9 | 10778 | (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] |
f357808b RK |
10779 | "find_single_use (operands[0], insn, 0) |
10780 | && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ | |
10781 | || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" | |
10782 | [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) | |
10783 | (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] | |
10784 | " | |
10785 | { | |
10786 | /* Get the constant we are comparing against, C, and see what it looks like | |
10787 | sign-extended to 16 bits. Then see what constant could be XOR'ed | |
10788 | with C to get the sign-extended value. */ | |
10789 | ||
5f59ecb7 | 10790 | HOST_WIDE_INT c = INTVAL (operands[2]); |
a65c591c | 10791 | HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000; |
5f59ecb7 | 10792 | HOST_WIDE_INT xorv = c ^ sextc; |
f357808b | 10793 | |
89e9f3a8 MM |
10794 | operands[4] = GEN_INT (xorv); |
10795 | operands[5] = GEN_INT (sextc); | |
f357808b RK |
10796 | }") |
10797 | ||
acad7ed3 | 10798 | (define_insn "*cmpsi_internal2" |
1fd4e8c1 | 10799 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
cd2b37d9 | 10800 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
9ebbca7d | 10801 | (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] |
1fd4e8c1 | 10802 | "" |
e2c953b6 | 10803 | "{cmpl%I2|cmplw%I2} %0,%1,%b2" |
b54cf83a | 10804 | [(set_attr "type" "cmp")]) |
1fd4e8c1 | 10805 | |
acad7ed3 | 10806 | (define_insn "*cmpdi_internal2" |
266eb58a DE |
10807 | [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") |
10808 | (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") | |
9ebbca7d | 10809 | (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] |
266eb58a | 10810 | "" |
e2c953b6 | 10811 | "cmpld%I2 %0,%1,%b2" |
b54cf83a | 10812 | [(set_attr "type" "cmp")]) |
266eb58a | 10813 | |
1fd4e8c1 RK |
10814 | ;; The following two insns don't exist as single insns, but if we provide |
10815 | ;; them, we can swap an add and compare, which will enable us to overlap more | |
10816 | ;; of the required delay between a compare and branch. We generate code for | |
10817 | ;; them by splitting. | |
10818 | ||
10819 | (define_insn "" | |
10820 | [(set (match_operand:CC 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 10821 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 10822 | (match_operand:SI 2 "short_cint_operand" "i"))) |
cd2b37d9 | 10823 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10824 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
10825 | "" | |
baf97f86 RK |
10826 | "#" |
10827 | [(set_attr "length" "8")]) | |
7e69e155 | 10828 | |
1fd4e8c1 RK |
10829 | (define_insn "" |
10830 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") | |
cd2b37d9 | 10831 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 10832 | (match_operand:SI 2 "u_short_cint_operand" "i"))) |
cd2b37d9 | 10833 | (set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10834 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] |
10835 | "" | |
baf97f86 RK |
10836 | "#" |
10837 | [(set_attr "length" "8")]) | |
7e69e155 | 10838 | |
1fd4e8c1 RK |
10839 | (define_split |
10840 | [(set (match_operand:CC 3 "cc_reg_operand" "") | |
cd2b37d9 | 10841 | (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 10842 | (match_operand:SI 2 "short_cint_operand" ""))) |
cd2b37d9 | 10843 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10844 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
10845 | "" | |
10846 | [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) | |
10847 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
10848 | ||
10849 | (define_split | |
10850 | [(set (match_operand:CCUNS 3 "cc_reg_operand" "") | |
cd2b37d9 | 10851 | (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 10852 | (match_operand:SI 2 "u_short_cint_operand" ""))) |
cd2b37d9 | 10853 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
1fd4e8c1 RK |
10854 | (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] |
10855 | "" | |
10856 | [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) | |
10857 | (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) | |
10858 | ||
acad7ed3 | 10859 | (define_insn "*cmpsf_internal1" |
1fd4e8c1 | 10860 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
10861 | (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") |
10862 | (match_operand:SF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 10863 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
10864 | "fcmpu %0,%1,%2" |
10865 | [(set_attr "type" "fpcompare")]) | |
10866 | ||
acad7ed3 | 10867 | (define_insn "*cmpdf_internal1" |
1fd4e8c1 | 10868 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
cd2b37d9 RK |
10869 | (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") |
10870 | (match_operand:DF 2 "gpc_reg_operand" "f")))] | |
a3170dc6 | 10871 | "TARGET_HARD_FLOAT && TARGET_FPRS" |
1fd4e8c1 RK |
10872 | "fcmpu %0,%1,%2" |
10873 | [(set_attr "type" "fpcompare")]) | |
d6f99ca4 DE |
10874 | |
10875 | ;; Only need to compare second words if first words equal | |
10876 | (define_insn "*cmptf_internal1" | |
10877 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
10878 | (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") | |
10879 | (match_operand:TF 2 "gpc_reg_operand" "f")))] | |
de17c25f | 10880 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && !TARGET_XL_COMPAT |
39e63627 | 10881 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" |
ecb62ae7 | 10882 | "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2" |
d6f99ca4 DE |
10883 | [(set_attr "type" "fpcompare") |
10884 | (set_attr "length" "12")]) | |
de17c25f DE |
10885 | |
10886 | (define_insn_and_split "*cmptf_internal2" | |
10887 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
10888 | (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") | |
10889 | (match_operand:TF 2 "gpc_reg_operand" "f"))) | |
10890 | (clobber (match_scratch:DF 3 "=f")) | |
10891 | (clobber (match_scratch:DF 4 "=f")) | |
10892 | (clobber (match_scratch:DF 5 "=f")) | |
10893 | (clobber (match_scratch:DF 6 "=f")) | |
10894 | (clobber (match_scratch:DF 7 "=f")) | |
10895 | (clobber (match_scratch:DF 8 "=f")) | |
10896 | (clobber (match_scratch:DF 9 "=f")) | |
10897 | (clobber (match_scratch:DF 10 "=f"))] | |
10898 | "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) && TARGET_XL_COMPAT | |
10899 | && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" | |
10900 | "#" | |
10901 | "&& reload_completed" | |
10902 | [(set (match_dup 3) (match_dup 13)) | |
10903 | (set (match_dup 4) (match_dup 14)) | |
10904 | (set (match_dup 9) (abs:DF (match_dup 5))) | |
10905 | (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3))) | |
10906 | (set (pc) (if_then_else (ne (match_dup 0) (const_int 0)) | |
10907 | (label_ref (match_dup 11)) | |
10908 | (pc))) | |
10909 | (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7))) | |
10910 | (set (pc) (label_ref (match_dup 12))) | |
10911 | (match_dup 11) | |
10912 | (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7))) | |
10913 | (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8))) | |
10914 | (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9))) | |
10915 | (set (match_dup 0) (compare:CCFP (match_dup 7) (match_dup 4))) | |
10916 | (match_dup 12)] | |
10917 | { | |
10918 | REAL_VALUE_TYPE rv; | |
10919 | const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0; | |
10920 | const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode); | |
10921 | ||
10922 | operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word); | |
10923 | operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word); | |
10924 | operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word); | |
10925 | operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word); | |
10926 | operands[11] = gen_label_rtx (); | |
10927 | operands[12] = gen_label_rtx (); | |
10928 | real_inf (&rv); | |
10929 | operands[13] = force_const_mem (DFmode, | |
10930 | CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode)); | |
10931 | operands[14] = force_const_mem (DFmode, | |
10932 | CONST_DOUBLE_FROM_REAL_VALUE (dconst0, | |
10933 | DFmode)); | |
10934 | if (TARGET_TOC) | |
10935 | { | |
10936 | operands[13] = gen_const_mem (DFmode, | |
10937 | create_TOC_reference (XEXP (operands[13], 0))); | |
10938 | operands[14] = gen_const_mem (DFmode, | |
10939 | create_TOC_reference (XEXP (operands[14], 0))); | |
10940 | set_mem_alias_set (operands[13], get_TOC_alias_set ()); | |
10941 | set_mem_alias_set (operands[14], get_TOC_alias_set ()); | |
10942 | } | |
10943 | }) | |
1fd4e8c1 RK |
10944 | \f |
10945 | ;; Now we have the scc insns. We can do some combinations because of the | |
10946 | ;; way the machine works. | |
10947 | ;; | |
10948 | ;; Note that this is probably faster if we can put an insn between the | |
c5defebb RK |
10949 | ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most |
10950 | ;; cases the insns below which don't use an intermediate CR field will | |
10951 | ;; be used instead. | |
1fd4e8c1 | 10952 | (define_insn "" |
cd2b37d9 | 10953 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
10954 | (match_operator:SI 1 "scc_comparison_operator" |
10955 | [(match_operand 2 "cc_reg_operand" "y") | |
10956 | (const_int 0)]))] | |
10957 | "" | |
2c4a9cff DE |
10958 | "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" |
10959 | [(set (attr "type") | |
10960 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
10961 | (const_string "mfcrf") | |
10962 | ] | |
10963 | (const_string "mfcr"))) | |
c1618c0c | 10964 | (set_attr "length" "8")]) |
1fd4e8c1 | 10965 | |
423c1189 | 10966 | ;; Same as above, but get the GT bit. |
64022b5d | 10967 | (define_insn "move_from_CR_gt_bit" |
423c1189 | 10968 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
64022b5d | 10969 | (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))] |
423c1189 | 10970 | "TARGET_E500" |
64022b5d | 10971 | "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31" |
423c1189 | 10972 | [(set_attr "type" "mfcr") |
c1618c0c | 10973 | (set_attr "length" "8")]) |
423c1189 | 10974 | |
a3170dc6 AH |
10975 | ;; Same as above, but get the OV/ORDERED bit. |
10976 | (define_insn "move_from_CR_ov_bit" | |
10977 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
615158e2 | 10978 | (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))] |
a3170dc6 | 10979 | "TARGET_ISEL" |
b7053a3f | 10980 | "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1" |
b54cf83a | 10981 | [(set_attr "type" "mfcr") |
c1618c0c | 10982 | (set_attr "length" "8")]) |
a3170dc6 | 10983 | |
1fd4e8c1 | 10984 | (define_insn "" |
9ebbca7d GK |
10985 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
10986 | (match_operator:DI 1 "scc_comparison_operator" | |
10987 | [(match_operand 2 "cc_reg_operand" "y") | |
10988 | (const_int 0)]))] | |
10989 | "TARGET_POWERPC64" | |
2c4a9cff DE |
10990 | "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1" |
10991 | [(set (attr "type") | |
10992 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
10993 | (const_string "mfcrf") | |
10994 | ] | |
10995 | (const_string "mfcr"))) | |
c1618c0c | 10996 | (set_attr "length" "8")]) |
9ebbca7d GK |
10997 | |
10998 | (define_insn "" | |
10999 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 11000 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" |
9ebbca7d | 11001 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 RK |
11002 | (const_int 0)]) |
11003 | (const_int 0))) | |
9ebbca7d | 11004 | (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11005 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] |
4b8a63d6 | 11006 | "TARGET_32BIT" |
9ebbca7d | 11007 | "@ |
2c4a9cff | 11008 | mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1 |
9ebbca7d | 11009 | #" |
b19003d8 | 11010 | [(set_attr "type" "delayed_compare") |
c1618c0c | 11011 | (set_attr "length" "8,16")]) |
9ebbca7d GK |
11012 | |
11013 | (define_split | |
11014 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11015 | (compare:CC (match_operator:SI 1 "scc_comparison_operator" | |
11016 | [(match_operand 2 "cc_reg_operand" "") | |
11017 | (const_int 0)]) | |
11018 | (const_int 0))) | |
11019 | (set (match_operand:SI 3 "gpc_reg_operand" "") | |
11020 | (match_op_dup 1 [(match_dup 2) (const_int 0)]))] | |
4b8a63d6 | 11021 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11022 | [(set (match_dup 3) |
11023 | (match_op_dup 1 [(match_dup 2) (const_int 0)])) | |
11024 | (set (match_dup 0) | |
11025 | (compare:CC (match_dup 3) | |
11026 | (const_int 0)))] | |
11027 | "") | |
1fd4e8c1 RK |
11028 | |
11029 | (define_insn "" | |
cd2b37d9 | 11030 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 RK |
11031 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" |
11032 | [(match_operand 2 "cc_reg_operand" "y") | |
11033 | (const_int 0)]) | |
11034 | (match_operand:SI 3 "const_int_operand" "n")))] | |
11035 | "" | |
11036 | "* | |
11037 | { | |
11038 | int is_bit = ccr_bit (operands[1], 1); | |
11039 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11040 | int count; | |
11041 | ||
11042 | if (is_bit >= put_bit) | |
11043 | count = is_bit - put_bit; | |
11044 | else | |
11045 | count = 32 - (put_bit - is_bit); | |
11046 | ||
89e9f3a8 MM |
11047 | operands[4] = GEN_INT (count); |
11048 | operands[5] = GEN_INT (put_bit); | |
1fd4e8c1 | 11049 | |
2c4a9cff | 11050 | return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; |
b19003d8 | 11051 | }" |
2c4a9cff DE |
11052 | [(set (attr "type") |
11053 | (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0)) | |
11054 | (const_string "mfcrf") | |
11055 | ] | |
11056 | (const_string "mfcr"))) | |
c1618c0c | 11057 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
11058 | |
11059 | (define_insn "" | |
9ebbca7d | 11060 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11061 | (compare:CC |
11062 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
9ebbca7d | 11063 | [(match_operand 2 "cc_reg_operand" "y,y") |
1fd4e8c1 | 11064 | (const_int 0)]) |
9ebbca7d | 11065 | (match_operand:SI 3 "const_int_operand" "n,n")) |
1fd4e8c1 | 11066 | (const_int 0))) |
9ebbca7d | 11067 | (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11068 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) |
11069 | (match_dup 3)))] | |
ce71f754 | 11070 | "" |
1fd4e8c1 RK |
11071 | "* |
11072 | { | |
11073 | int is_bit = ccr_bit (operands[1], 1); | |
11074 | int put_bit = 31 - (INTVAL (operands[3]) & 31); | |
11075 | int count; | |
11076 | ||
9ebbca7d GK |
11077 | /* Force split for non-cc0 compare. */ |
11078 | if (which_alternative == 1) | |
11079 | return \"#\"; | |
11080 | ||
1fd4e8c1 RK |
11081 | if (is_bit >= put_bit) |
11082 | count = is_bit - put_bit; | |
11083 | else | |
11084 | count = 32 - (put_bit - is_bit); | |
11085 | ||
89e9f3a8 MM |
11086 | operands[5] = GEN_INT (count); |
11087 | operands[6] = GEN_INT (put_bit); | |
1fd4e8c1 | 11088 | |
2c4a9cff | 11089 | return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\"; |
1fd4e8c1 | 11090 | }" |
b19003d8 | 11091 | [(set_attr "type" "delayed_compare") |
c1618c0c | 11092 | (set_attr "length" "8,16")]) |
9ebbca7d GK |
11093 | |
11094 | (define_split | |
11095 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11096 | (compare:CC | |
11097 | (ashift:SI (match_operator:SI 1 "scc_comparison_operator" | |
11098 | [(match_operand 2 "cc_reg_operand" "") | |
11099 | (const_int 0)]) | |
11100 | (match_operand:SI 3 "const_int_operand" "")) | |
11101 | (const_int 0))) | |
11102 | (set (match_operand:SI 4 "gpc_reg_operand" "") | |
11103 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11104 | (match_dup 3)))] | |
ce71f754 | 11105 | "reload_completed" |
9ebbca7d GK |
11106 | [(set (match_dup 4) |
11107 | (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
11108 | (match_dup 3))) | |
11109 | (set (match_dup 0) | |
11110 | (compare:CC (match_dup 4) | |
11111 | (const_int 0)))] | |
11112 | "") | |
1fd4e8c1 | 11113 | |
c5defebb RK |
11114 | ;; There is a 3 cycle delay between consecutive mfcr instructions |
11115 | ;; so it is useful to combine 2 scc instructions to use only one mfcr. | |
11116 | ||
11117 | (define_peephole | |
cd2b37d9 | 11118 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c5defebb RK |
11119 | (match_operator:SI 1 "scc_comparison_operator" |
11120 | [(match_operand 2 "cc_reg_operand" "y") | |
11121 | (const_int 0)])) | |
cd2b37d9 | 11122 | (set (match_operand:SI 3 "gpc_reg_operand" "=r") |
c5defebb RK |
11123 | (match_operator:SI 4 "scc_comparison_operator" |
11124 | [(match_operand 5 "cc_reg_operand" "y") | |
11125 | (const_int 0)]))] | |
309323c2 | 11126 | "REGNO (operands[2]) != REGNO (operands[5])" |
b7053a3f | 11127 | "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b54cf83a | 11128 | [(set_attr "type" "mfcr") |
c1618c0c | 11129 | (set_attr "length" "12")]) |
c5defebb | 11130 | |
9ebbca7d GK |
11131 | (define_peephole |
11132 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11133 | (match_operator:DI 1 "scc_comparison_operator" | |
11134 | [(match_operand 2 "cc_reg_operand" "y") | |
11135 | (const_int 0)])) | |
11136 | (set (match_operand:DI 3 "gpc_reg_operand" "=r") | |
11137 | (match_operator:DI 4 "scc_comparison_operator" | |
11138 | [(match_operand 5 "cc_reg_operand" "y") | |
11139 | (const_int 0)]))] | |
309323c2 | 11140 | "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" |
b7053a3f | 11141 | "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" |
b54cf83a | 11142 | [(set_attr "type" "mfcr") |
c1618c0c | 11143 | (set_attr "length" "12")]) |
9ebbca7d | 11144 | |
1fd4e8c1 RK |
11145 | ;; There are some scc insns that can be done directly, without a compare. |
11146 | ;; These are faster because they don't involve the communications between | |
11147 | ;; the FXU and branch units. In fact, we will be replacing all of the | |
11148 | ;; integer scc insns here or in the portable methods in emit_store_flag. | |
11149 | ;; | |
11150 | ;; Also support (neg (scc ..)) since that construct is used to replace | |
11151 | ;; branches, (plus (scc ..) ..) since that construct is common and | |
11152 | ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the | |
11153 | ;; cases where it is no more expensive than (neg (scc ..)). | |
11154 | ||
11155 | ;; Have reload force a constant into a register for the simple insns that | |
11156 | ;; otherwise won't accept constants. We do this because it is faster than | |
11157 | ;; the cmp/mfcr sequence we would otherwise generate. | |
11158 | ||
e9441276 DE |
11159 | (define_mode_attr scc_eq_op2 [(SI "rKLI") |
11160 | (DI "rKJI")]) | |
a260abc9 | 11161 | |
e9441276 DE |
11162 | (define_insn_and_split "*eq<mode>" |
11163 | [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") | |
11164 | (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") | |
11165 | (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>"))) | |
11166 | (clobber (match_scratch:GPR 3 "=r")) | |
11167 | (clobber (match_scratch:GPR 4 "=r"))] | |
70ae0191 | 11168 | "" |
e9441276 DE |
11169 | "#" |
11170 | "reload_completed" | |
11171 | [(set (match_dup 3) | |
11172 | (clz:GPR (match_dup 4))) | |
70ae0191 | 11173 | (set (match_dup 0) |
e9441276 | 11174 | (lshiftrt:GPR (match_dup 3) (match_dup 5)))] |
70ae0191 | 11175 | { |
e9441276 DE |
11176 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0) |
11177 | { | |
11178 | if (logical_operand (operands[2], <MODE>mode)) | |
11179 | emit_insn (gen_rtx_SET (VOIDmode, operands[4], | |
11180 | gen_rtx_XOR (<MODE>mode, | |
11181 | operands[1], operands[2]))); | |
11182 | else | |
11183 | emit_insn (gen_rtx_SET (VOIDmode, operands[4], | |
11184 | gen_rtx_PLUS (<MODE>mode, operands[1], | |
11185 | negate_rtx (<MODE>mode, | |
11186 | operands[2])))); | |
11187 | } | |
11188 | else | |
11189 | operands[4] = operands[1]; | |
9ebbca7d | 11190 | |
e9441276 DE |
11191 | operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode))); |
11192 | }) | |
a260abc9 | 11193 | |
e9441276 DE |
11194 | (define_insn_and_split "*eq<mode>_compare" |
11195 | [(set (match_operand:CC 5 "cc_reg_operand" "=y") | |
70ae0191 | 11196 | (compare:CC |
1fa5c709 DE |
11197 | (eq:P (match_operand:P 1 "gpc_reg_operand" "=r") |
11198 | (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>")) | |
70ae0191 | 11199 | (const_int 0))) |
1fa5c709 DE |
11200 | (set (match_operand:P 0 "gpc_reg_operand" "=r") |
11201 | (eq:P (match_dup 1) (match_dup 2))) | |
11202 | (clobber (match_scratch:P 3 "=r")) | |
11203 | (clobber (match_scratch:P 4 "=r"))] | |
70ae0191 | 11204 | "" |
e9441276 DE |
11205 | "#" |
11206 | "reload_completed" | |
11207 | [(set (match_dup 3) | |
1fa5c709 | 11208 | (clz:P (match_dup 4))) |
e9441276 | 11209 | (parallel [(set (match_dup 5) |
1fa5c709 | 11210 | (compare:CC (lshiftrt:P (match_dup 3) (match_dup 6)) |
70ae0191 DE |
11211 | (const_int 0))) |
11212 | (set (match_dup 0) | |
1fa5c709 | 11213 | (lshiftrt:P (match_dup 3) (match_dup 6)))])] |
70ae0191 | 11214 | { |
e9441276 DE |
11215 | if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0) |
11216 | { | |
11217 | if (logical_operand (operands[2], <MODE>mode)) | |
11218 | emit_insn (gen_rtx_SET (VOIDmode, operands[4], | |
11219 | gen_rtx_XOR (<MODE>mode, | |
11220 | operands[1], operands[2]))); | |
11221 | else | |
11222 | emit_insn (gen_rtx_SET (VOIDmode, operands[4], | |
11223 | gen_rtx_PLUS (<MODE>mode, operands[1], | |
11224 | negate_rtx (<MODE>mode, | |
11225 | operands[2])))); | |
11226 | } | |
11227 | else | |
11228 | operands[4] = operands[1]; | |
11229 | ||
11230 | operands[6] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode))); | |
70ae0191 DE |
11231 | }) |
11232 | ||
b19003d8 RK |
11233 | ;; We have insns of the form shown by the first define_insn below. If |
11234 | ;; there is something inside the comparison operation, we must split it. | |
11235 | (define_split | |
11236 | [(set (match_operand:SI 0 "gpc_reg_operand" "") | |
11237 | (plus:SI (match_operator 1 "comparison_operator" | |
11238 | [(match_operand:SI 2 "" "") | |
11239 | (match_operand:SI 3 | |
11240 | "reg_or_cint_operand" "")]) | |
11241 | (match_operand:SI 4 "gpc_reg_operand" ""))) | |
11242 | (clobber (match_operand:SI 5 "register_operand" ""))] | |
11243 | "! gpc_reg_operand (operands[2], SImode)" | |
11244 | [(set (match_dup 5) (match_dup 2)) | |
11245 | (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) | |
11246 | (match_dup 4)))]) | |
1fd4e8c1 RK |
11247 | |
11248 | (define_insn "" | |
5276df18 | 11249 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r") |
cd2b37d9 | 11250 | (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
56fc483e | 11251 | (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I")) |
5276df18 | 11252 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))] |
683bdff7 | 11253 | "TARGET_32BIT" |
1fd4e8c1 | 11254 | "@ |
5276df18 DE |
11255 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
11256 | {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3 | |
11257 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11258 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 | |
11259 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" | |
943c15ed DE |
11260 | [(set_attr "type" "three,two,three,three,three") |
11261 | (set_attr "length" "12,8,12,12,12")]) | |
1fd4e8c1 RK |
11262 | |
11263 | (define_insn "" | |
9ebbca7d | 11264 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11265 | (compare:CC |
1fd4e8c1 | 11266 | (plus:SI |
9ebbca7d | 11267 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
56fc483e | 11268 | (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I")) |
9ebbca7d | 11269 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) |
1fd4e8c1 | 11270 | (const_int 0))) |
9ebbca7d | 11271 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] |
683bdff7 | 11272 | "TARGET_32BIT" |
1fd4e8c1 | 11273 | "@ |
ca7f5001 | 11274 | xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
19378cf8 | 11275 | {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3 |
ca7f5001 RK |
11276 | {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11277 | {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
9ebbca7d GK |
11278 | {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
11279 | # | |
11280 | # | |
11281 | # | |
11282 | # | |
11283 | #" | |
b19003d8 | 11284 | [(set_attr "type" "compare") |
9ebbca7d GK |
11285 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) |
11286 | ||
11287 | (define_split | |
11288 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11289 | (compare:CC | |
11290 | (plus:SI | |
11291 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
56fc483e | 11292 | (match_operand:SI 2 "scc_eq_operand" "")) |
9ebbca7d GK |
11293 | (match_operand:SI 3 "gpc_reg_operand" "")) |
11294 | (const_int 0))) | |
11295 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 11296 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11297 | [(set (match_dup 4) |
11298 | (plus:SI (eq:SI (match_dup 1) | |
11299 | (match_dup 2)) | |
11300 | (match_dup 3))) | |
11301 | (set (match_dup 0) | |
11302 | (compare:CC (match_dup 4) | |
11303 | (const_int 0)))] | |
11304 | "") | |
1fd4e8c1 RK |
11305 | |
11306 | (define_insn "" | |
0387639b | 11307 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") |
7e69e155 | 11308 | (compare:CC |
1fd4e8c1 | 11309 | (plus:SI |
9ebbca7d | 11310 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") |
56fc483e | 11311 | (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I")) |
9ebbca7d | 11312 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) |
1fd4e8c1 | 11313 | (const_int 0))) |
0387639b DE |
11314 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r") |
11315 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 11316 | "TARGET_32BIT" |
1fd4e8c1 | 11317 | "@ |
0387639b DE |
11318 | xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
11319 | {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3 | |
11320 | {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11321 | {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
11322 | {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
11323 | # |
11324 | # | |
11325 | # | |
11326 | # | |
11327 | #" | |
11328 | [(set_attr "type" "compare") | |
11329 | (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) | |
11330 | ||
11331 | (define_split | |
0387639b | 11332 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11333 | (compare:CC |
11334 | (plus:SI | |
11335 | (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
56fc483e | 11336 | (match_operand:SI 2 "scc_eq_operand" "")) |
9ebbca7d GK |
11337 | (match_operand:SI 3 "gpc_reg_operand" "")) |
11338 | (const_int 0))) | |
11339 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
0387639b | 11340 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 11341 | "TARGET_32BIT && reload_completed" |
0387639b | 11342 | [(set (match_dup 0) |
9ebbca7d | 11343 | (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
0387639b | 11344 | (set (match_dup 4) |
9ebbca7d GK |
11345 | (compare:CC (match_dup 0) |
11346 | (const_int 0)))] | |
11347 | "") | |
11348 | ||
1fd4e8c1 | 11349 | (define_insn "" |
cd2b37d9 | 11350 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") |
deb9225a | 11351 | (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") |
56fc483e | 11352 | (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))))] |
683bdff7 | 11353 | "TARGET_32BIT" |
1fd4e8c1 | 11354 | "@ |
ca7f5001 RK |
11355 | xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
11356 | {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0 | |
11357 | {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11358 | {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 | |
11359 | {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
943c15ed DE |
11360 | [(set_attr "type" "three,two,three,three,three") |
11361 | (set_attr "length" "12,8,12,12,12")]) | |
1fd4e8c1 | 11362 | |
ea9be077 MM |
11363 | ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power, |
11364 | ;; since it nabs/sr is just as fast. | |
463b558b | 11365 | (define_insn "*ne0" |
b4e95693 | 11366 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
ea9be077 MM |
11367 | (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
11368 | (const_int 31))) | |
11369 | (clobber (match_scratch:SI 2 "=&r"))] | |
683bdff7 | 11370 | "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL" |
ea9be077 | 11371 | "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" |
943c15ed DE |
11372 | [(set_attr "type" "two") |
11373 | (set_attr "length" "8")]) | |
ea9be077 | 11374 | |
a260abc9 DE |
11375 | (define_insn "" |
11376 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11377 | (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11378 | (const_int 63))) | |
11379 | (clobber (match_scratch:DI 2 "=&r"))] | |
683bdff7 | 11380 | "TARGET_64BIT" |
a260abc9 | 11381 | "addic %2,%1,-1\;subfe %0,%2,%1" |
943c15ed DE |
11382 | [(set_attr "type" "two") |
11383 | (set_attr "length" "8")]) | |
a260abc9 | 11384 | |
1fd4e8c1 RK |
11385 | ;; This is what (plus (ne X (const_int 0)) Y) looks like. |
11386 | (define_insn "" | |
cd2b37d9 | 11387 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
1fd4e8c1 | 11388 | (plus:SI (lshiftrt:SI |
cd2b37d9 | 11389 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11390 | (const_int 31)) |
cd2b37d9 | 11391 | (match_operand:SI 2 "gpc_reg_operand" "r"))) |
1fd4e8c1 | 11392 | (clobber (match_scratch:SI 3 "=&r"))] |
683bdff7 | 11393 | "TARGET_32BIT" |
ca7f5001 | 11394 | "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2" |
943c15ed DE |
11395 | [(set_attr "type" "two") |
11396 | (set_attr "length" "8")]) | |
1fd4e8c1 | 11397 | |
a260abc9 DE |
11398 | (define_insn "" |
11399 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11400 | (plus:DI (lshiftrt:DI | |
11401 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r"))) | |
11402 | (const_int 63)) | |
11403 | (match_operand:DI 2 "gpc_reg_operand" "r"))) | |
11404 | (clobber (match_scratch:DI 3 "=&r"))] | |
683bdff7 | 11405 | "TARGET_64BIT" |
a260abc9 | 11406 | "addic %3,%1,-1\;addze %0,%2" |
943c15ed DE |
11407 | [(set_attr "type" "two") |
11408 | (set_attr "length" "8")]) | |
a260abc9 | 11409 | |
1fd4e8c1 | 11410 | (define_insn "" |
9ebbca7d | 11411 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11412 | (compare:CC |
11413 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11414 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11415 | (const_int 31)) |
9ebbca7d | 11416 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11417 | (const_int 0))) |
889b90a1 GK |
11418 | (clobber (match_scratch:SI 3 "=&r,&r")) |
11419 | (clobber (match_scratch:SI 4 "=X,&r"))] | |
683bdff7 | 11420 | "TARGET_32BIT" |
9ebbca7d GK |
11421 | "@ |
11422 | {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2 | |
11423 | #" | |
b19003d8 | 11424 | [(set_attr "type" "compare") |
9ebbca7d GK |
11425 | (set_attr "length" "8,12")]) |
11426 | ||
11427 | (define_split | |
11428 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11429 | (compare:CC | |
11430 | (plus:SI (lshiftrt:SI | |
11431 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11432 | (const_int 31)) | |
11433 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11434 | (const_int 0))) | |
889b90a1 GK |
11435 | (clobber (match_scratch:SI 3 "")) |
11436 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 11437 | "TARGET_32BIT && reload_completed" |
889b90a1 | 11438 | [(parallel [(set (match_dup 3) |
ce71f754 AM |
11439 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) |
11440 | (const_int 31)) | |
11441 | (match_dup 2))) | |
889b90a1 | 11442 | (clobber (match_dup 4))]) |
9ebbca7d GK |
11443 | (set (match_dup 0) |
11444 | (compare:CC (match_dup 3) | |
11445 | (const_int 0)))] | |
11446 | "") | |
1fd4e8c1 | 11447 | |
a260abc9 | 11448 | (define_insn "" |
9ebbca7d | 11449 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11450 | (compare:CC |
11451 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11452 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11453 | (const_int 63)) |
9ebbca7d | 11454 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11455 | (const_int 0))) |
9ebbca7d | 11456 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 11457 | "TARGET_64BIT" |
9ebbca7d GK |
11458 | "@ |
11459 | addic %3,%1,-1\;addze. %3,%2 | |
11460 | #" | |
a260abc9 | 11461 | [(set_attr "type" "compare") |
9ebbca7d GK |
11462 | (set_attr "length" "8,12")]) |
11463 | ||
11464 | (define_split | |
11465 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11466 | (compare:CC | |
11467 | (plus:DI (lshiftrt:DI | |
11468 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11469 | (const_int 63)) | |
11470 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11471 | (const_int 0))) | |
11472 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 11473 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11474 | [(set (match_dup 3) |
11475 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) | |
11476 | (const_int 63)) | |
11477 | (match_dup 2))) | |
11478 | (set (match_dup 0) | |
11479 | (compare:CC (match_dup 3) | |
11480 | (const_int 0)))] | |
11481 | "") | |
a260abc9 | 11482 | |
1fd4e8c1 | 11483 | (define_insn "" |
9ebbca7d | 11484 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11485 | (compare:CC |
11486 | (plus:SI (lshiftrt:SI | |
9ebbca7d | 11487 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))) |
1fd4e8c1 | 11488 | (const_int 31)) |
9ebbca7d | 11489 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 11490 | (const_int 0))) |
9ebbca7d | 11491 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 RK |
11492 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) |
11493 | (match_dup 2))) | |
9ebbca7d | 11494 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
683bdff7 | 11495 | "TARGET_32BIT" |
9ebbca7d GK |
11496 | "@ |
11497 | {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2 | |
11498 | #" | |
b19003d8 | 11499 | [(set_attr "type" "compare") |
9ebbca7d GK |
11500 | (set_attr "length" "8,12")]) |
11501 | ||
11502 | (define_split | |
11503 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11504 | (compare:CC | |
11505 | (plus:SI (lshiftrt:SI | |
11506 | (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) | |
11507 | (const_int 31)) | |
11508 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
11509 | (const_int 0))) | |
11510 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11511 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11512 | (match_dup 2))) | |
11513 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 11514 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11515 | [(parallel [(set (match_dup 0) |
11516 | (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) | |
11517 | (match_dup 2))) | |
11518 | (clobber (match_dup 3))]) | |
11519 | (set (match_dup 4) | |
11520 | (compare:CC (match_dup 0) | |
11521 | (const_int 0)))] | |
11522 | "") | |
1fd4e8c1 | 11523 | |
a260abc9 | 11524 | (define_insn "" |
9ebbca7d | 11525 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
a260abc9 DE |
11526 | (compare:CC |
11527 | (plus:DI (lshiftrt:DI | |
9ebbca7d | 11528 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))) |
a260abc9 | 11529 | (const_int 63)) |
9ebbca7d | 11530 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
a260abc9 | 11531 | (const_int 0))) |
9ebbca7d | 11532 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
a260abc9 DE |
11533 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) |
11534 | (match_dup 2))) | |
9ebbca7d | 11535 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 11536 | "TARGET_64BIT" |
9ebbca7d GK |
11537 | "@ |
11538 | addic %3,%1,-1\;addze. %0,%2 | |
11539 | #" | |
a260abc9 | 11540 | [(set_attr "type" "compare") |
9ebbca7d GK |
11541 | (set_attr "length" "8,12")]) |
11542 | ||
11543 | (define_split | |
11544 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11545 | (compare:CC | |
11546 | (plus:DI (lshiftrt:DI | |
11547 | (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) | |
11548 | (const_int 63)) | |
11549 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
11550 | (const_int 0))) | |
11551 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11552 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11553 | (match_dup 2))) | |
11554 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 11555 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11556 | [(parallel [(set (match_dup 0) |
11557 | (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63)) | |
11558 | (match_dup 2))) | |
11559 | (clobber (match_dup 3))]) | |
11560 | (set (match_dup 4) | |
11561 | (compare:CC (match_dup 0) | |
11562 | (const_int 0)))] | |
11563 | "") | |
a260abc9 | 11564 | |
1fd4e8c1 | 11565 | (define_insn "" |
cd2b37d9 RK |
11566 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11567 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 RK |
11568 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))) |
11569 | (clobber (match_scratch:SI 3 "=r,X"))] | |
ca7f5001 | 11570 | "TARGET_POWER" |
1fd4e8c1 | 11571 | "@ |
ca7f5001 | 11572 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3 |
7f340546 | 11573 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11574 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11575 | |
11576 | (define_insn "" | |
9ebbca7d | 11577 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11578 | (compare:CC |
9ebbca7d GK |
11579 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11580 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
1fd4e8c1 | 11581 | (const_int 0))) |
9ebbca7d | 11582 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 11583 | (le:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 11584 | (clobber (match_scratch:SI 3 "=r,X,r,X"))] |
ca7f5001 | 11585 | "TARGET_POWER" |
1fd4e8c1 | 11586 | "@ |
ca7f5001 | 11587 | doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 |
9ebbca7d GK |
11588 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31 |
11589 | # | |
11590 | #" | |
11591 | [(set_attr "type" "compare,delayed_compare,compare,delayed_compare") | |
11592 | (set_attr "length" "12,12,16,16")]) | |
11593 | ||
11594 | (define_split | |
11595 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
11596 | (compare:CC | |
11597 | (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11598 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11599 | (const_int 0))) | |
11600 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11601 | (le:SI (match_dup 1) (match_dup 2))) | |
11602 | (clobber (match_scratch:SI 3 ""))] | |
11603 | "TARGET_POWER && reload_completed" | |
11604 | [(parallel [(set (match_dup 0) | |
11605 | (le:SI (match_dup 1) (match_dup 2))) | |
11606 | (clobber (match_dup 3))]) | |
11607 | (set (match_dup 4) | |
11608 | (compare:CC (match_dup 0) | |
11609 | (const_int 0)))] | |
11610 | "") | |
1fd4e8c1 RK |
11611 | |
11612 | (define_insn "" | |
097657c3 | 11613 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 11614 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 11615 | (match_operand:SI 2 "reg_or_short_operand" "r,O")) |
097657c3 | 11616 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
ca7f5001 | 11617 | "TARGET_POWER" |
1fd4e8c1 | 11618 | "@ |
097657c3 AM |
11619 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3 |
11620 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3" | |
b19003d8 | 11621 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11622 | |
11623 | (define_insn "" | |
9ebbca7d | 11624 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11625 | (compare:CC |
9ebbca7d GK |
11626 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11627 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
11628 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11629 | (const_int 0))) |
9ebbca7d | 11630 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
ca7f5001 | 11631 | "TARGET_POWER" |
1fd4e8c1 | 11632 | "@ |
ca7f5001 | 11633 | doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
11634 | {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3 |
11635 | # | |
11636 | #" | |
b19003d8 | 11637 | [(set_attr "type" "compare") |
9ebbca7d GK |
11638 | (set_attr "length" "12,12,16,16")]) |
11639 | ||
11640 | (define_split | |
11641 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11642 | (compare:CC | |
11643 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11644 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11645 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11646 | (const_int 0))) | |
11647 | (clobber (match_scratch:SI 4 ""))] | |
11648 | "TARGET_POWER && reload_completed" | |
11649 | [(set (match_dup 4) | |
11650 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 11651 | (match_dup 3))) |
9ebbca7d GK |
11652 | (set (match_dup 0) |
11653 | (compare:CC (match_dup 4) | |
11654 | (const_int 0)))] | |
11655 | "") | |
1fd4e8c1 RK |
11656 | |
11657 | (define_insn "" | |
097657c3 | 11658 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 11659 | (compare:CC |
9ebbca7d GK |
11660 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
11661 | (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O")) | |
11662 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 11663 | (const_int 0))) |
097657c3 AM |
11664 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
11665 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 11666 | "TARGET_POWER" |
1fd4e8c1 | 11667 | "@ |
097657c3 AM |
11668 | doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
11669 | {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
11670 | # |
11671 | #" | |
b19003d8 | 11672 | [(set_attr "type" "compare") |
9ebbca7d GK |
11673 | (set_attr "length" "12,12,16,16")]) |
11674 | ||
11675 | (define_split | |
097657c3 | 11676 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11677 | (compare:CC |
11678 | (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11679 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11680 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11681 | (const_int 0))) | |
11682 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 11683 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 11684 | "TARGET_POWER && reload_completed" |
097657c3 | 11685 | [(set (match_dup 0) |
9ebbca7d | 11686 | (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 11687 | (set (match_dup 4) |
9ebbca7d GK |
11688 | (compare:CC (match_dup 0) |
11689 | (const_int 0)))] | |
11690 | "") | |
1fd4e8c1 RK |
11691 | |
11692 | (define_insn "" | |
cd2b37d9 RK |
11693 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
11694 | (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 11695 | (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] |
ca7f5001 | 11696 | "TARGET_POWER" |
1fd4e8c1 | 11697 | "@ |
ca7f5001 RK |
11698 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0 |
11699 | {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 11700 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11701 | |
11702 | (define_insn "" | |
cd2b37d9 RK |
11703 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11704 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11705 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
4b8a63d6 | 11706 | "TARGET_32BIT" |
ca7f5001 | 11707 | "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" |
943c15ed DE |
11708 | [(set_attr "type" "three") |
11709 | (set_attr "length" "12")]) | |
1fd4e8c1 | 11710 | |
f9562f27 DE |
11711 | (define_insn "" |
11712 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
11713 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
11714 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
683bdff7 | 11715 | "TARGET_64BIT" |
f9562f27 | 11716 | "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" |
943c15ed DE |
11717 | [(set_attr "type" "three") |
11718 | (set_attr "length" "12")]) | |
f9562f27 DE |
11719 | |
11720 | (define_insn "" | |
9ebbca7d | 11721 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 11722 | (compare:CC |
9ebbca7d GK |
11723 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
11724 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 11725 | (const_int 0))) |
9ebbca7d | 11726 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 11727 | (leu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 11728 | "TARGET_64BIT" |
9ebbca7d GK |
11729 | "@ |
11730 | subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 | |
11731 | #" | |
f9562f27 | 11732 | [(set_attr "type" "compare") |
9ebbca7d GK |
11733 | (set_attr "length" "12,16")]) |
11734 | ||
11735 | (define_split | |
11736 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11737 | (compare:CC | |
11738 | (leu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
11739 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
11740 | (const_int 0))) | |
11741 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
11742 | (leu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 11743 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
11744 | [(set (match_dup 0) |
11745 | (leu:DI (match_dup 1) (match_dup 2))) | |
11746 | (set (match_dup 3) | |
11747 | (compare:CC (match_dup 0) | |
11748 | (const_int 0)))] | |
11749 | "") | |
f9562f27 | 11750 | |
1fd4e8c1 | 11751 | (define_insn "" |
9ebbca7d | 11752 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11753 | (compare:CC |
9ebbca7d GK |
11754 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11755 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11756 | (const_int 0))) |
9ebbca7d | 11757 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11758 | (leu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 11759 | "TARGET_32BIT" |
9ebbca7d GK |
11760 | "@ |
11761 | {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 | |
11762 | #" | |
b19003d8 | 11763 | [(set_attr "type" "compare") |
9ebbca7d GK |
11764 | (set_attr "length" "12,16")]) |
11765 | ||
11766 | (define_split | |
11767 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11768 | (compare:CC | |
11769 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11770 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11771 | (const_int 0))) | |
11772 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11773 | (leu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 11774 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11775 | [(set (match_dup 0) |
11776 | (leu:SI (match_dup 1) (match_dup 2))) | |
11777 | (set (match_dup 3) | |
11778 | (compare:CC (match_dup 0) | |
11779 | (const_int 0)))] | |
11780 | "") | |
1fd4e8c1 RK |
11781 | |
11782 | (define_insn "" | |
80103f96 | 11783 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 11784 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11785 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
80103f96 | 11786 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
683bdff7 | 11787 | "TARGET_32BIT" |
80103f96 | 11788 | "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3" |
943c15ed DE |
11789 | [(set_attr "type" "two") |
11790 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
11791 | |
11792 | (define_insn "" | |
9ebbca7d | 11793 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11794 | (compare:CC |
9ebbca7d GK |
11795 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11796 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11797 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11798 | (const_int 0))) |
9ebbca7d | 11799 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
683bdff7 | 11800 | "TARGET_32BIT" |
9ebbca7d GK |
11801 | "@ |
11802 | {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3 | |
11803 | #" | |
b19003d8 | 11804 | [(set_attr "type" "compare") |
9ebbca7d GK |
11805 | (set_attr "length" "8,12")]) |
11806 | ||
11807 | (define_split | |
11808 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11809 | (compare:CC | |
11810 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11811 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11812 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11813 | (const_int 0))) | |
11814 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 11815 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
11816 | [(set (match_dup 4) |
11817 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) | |
11818 | (match_dup 3))) | |
11819 | (set (match_dup 0) | |
11820 | (compare:CC (match_dup 4) | |
11821 | (const_int 0)))] | |
11822 | "") | |
1fd4e8c1 RK |
11823 | |
11824 | (define_insn "" | |
097657c3 | 11825 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11826 | (compare:CC |
9ebbca7d GK |
11827 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11828 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
11829 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11830 | (const_int 0))) |
097657c3 AM |
11831 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
11832 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 11833 | "TARGET_32BIT" |
9ebbca7d | 11834 | "@ |
097657c3 | 11835 | {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3 |
9ebbca7d | 11836 | #" |
b19003d8 | 11837 | [(set_attr "type" "compare") |
9ebbca7d GK |
11838 | (set_attr "length" "8,12")]) |
11839 | ||
11840 | (define_split | |
097657c3 | 11841 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11842 | (compare:CC |
11843 | (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11844 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11845 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11846 | (const_int 0))) | |
11847 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 11848 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 11849 | "TARGET_32BIT && reload_completed" |
097657c3 | 11850 | [(set (match_dup 0) |
9ebbca7d | 11851 | (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 11852 | (set (match_dup 4) |
9ebbca7d GK |
11853 | (compare:CC (match_dup 0) |
11854 | (const_int 0)))] | |
11855 | "") | |
1fd4e8c1 RK |
11856 | |
11857 | (define_insn "" | |
cd2b37d9 RK |
11858 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11859 | (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11860 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
683bdff7 | 11861 | "TARGET_32BIT" |
ca7f5001 | 11862 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0" |
943c15ed DE |
11863 | [(set_attr "type" "three") |
11864 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
11865 | |
11866 | (define_insn "" | |
097657c3 | 11867 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
1fd4e8c1 | 11868 | (and:SI (neg:SI |
cd2b37d9 | 11869 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11870 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
097657c3 | 11871 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
683bdff7 | 11872 | "TARGET_32BIT" |
097657c3 | 11873 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" |
943c15ed DE |
11874 | [(set_attr "type" "three") |
11875 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
11876 | |
11877 | (define_insn "" | |
9ebbca7d | 11878 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11879 | (compare:CC |
11880 | (and:SI (neg:SI | |
9ebbca7d GK |
11881 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11882 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
11883 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11884 | (const_int 0))) |
9ebbca7d | 11885 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
683bdff7 | 11886 | "TARGET_32BIT" |
9ebbca7d GK |
11887 | "@ |
11888 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 | |
11889 | #" | |
11890 | [(set_attr "type" "compare") | |
11891 | (set_attr "length" "12,16")]) | |
11892 | ||
11893 | (define_split | |
11894 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
11895 | (compare:CC | |
11896 | (and:SI (neg:SI | |
11897 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11898 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
11899 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11900 | (const_int 0))) | |
11901 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 11902 | "TARGET_32BIT && reload_completed" |
9ebbca7d | 11903 | [(set (match_dup 4) |
097657c3 AM |
11904 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) |
11905 | (match_dup 3))) | |
9ebbca7d GK |
11906 | (set (match_dup 0) |
11907 | (compare:CC (match_dup 4) | |
11908 | (const_int 0)))] | |
11909 | "") | |
1fd4e8c1 RK |
11910 | |
11911 | (define_insn "" | |
097657c3 | 11912 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 RK |
11913 | (compare:CC |
11914 | (and:SI (neg:SI | |
9ebbca7d GK |
11915 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11916 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) | |
11917 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 11918 | (const_int 0))) |
097657c3 AM |
11919 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
11920 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
683bdff7 | 11921 | "TARGET_32BIT" |
9ebbca7d | 11922 | "@ |
097657c3 | 11923 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
9ebbca7d | 11924 | #" |
b19003d8 | 11925 | [(set_attr "type" "compare") |
9ebbca7d GK |
11926 | (set_attr "length" "12,16")]) |
11927 | ||
11928 | (define_split | |
097657c3 | 11929 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
11930 | (compare:CC |
11931 | (and:SI (neg:SI | |
11932 | (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11933 | (match_operand:SI 2 "reg_or_short_operand" ""))) | |
11934 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
11935 | (const_int 0))) | |
11936 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 11937 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
683bdff7 | 11938 | "TARGET_32BIT && reload_completed" |
097657c3 AM |
11939 | [(set (match_dup 0) |
11940 | (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) | |
11941 | (match_dup 3))) | |
11942 | (set (match_dup 4) | |
9ebbca7d GK |
11943 | (compare:CC (match_dup 0) |
11944 | (const_int 0)))] | |
11945 | "") | |
1fd4e8c1 RK |
11946 | |
11947 | (define_insn "" | |
cd2b37d9 RK |
11948 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
11949 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 11950 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] |
ca7f5001 | 11951 | "TARGET_POWER" |
7f340546 | 11952 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31" |
b19003d8 | 11953 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11954 | |
11955 | (define_insn "" | |
9ebbca7d | 11956 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11957 | (compare:CC |
9ebbca7d GK |
11958 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11959 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 11960 | (const_int 0))) |
9ebbca7d | 11961 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 11962 | (lt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 11963 | "TARGET_POWER" |
9ebbca7d GK |
11964 | "@ |
11965 | doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
11966 | #" | |
29ae5b89 | 11967 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
11968 | (set_attr "length" "12,16")]) |
11969 | ||
11970 | (define_split | |
11971 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
11972 | (compare:CC | |
11973 | (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
11974 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
11975 | (const_int 0))) | |
11976 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
11977 | (lt:SI (match_dup 1) (match_dup 2)))] | |
11978 | "TARGET_POWER && reload_completed" | |
11979 | [(set (match_dup 0) | |
11980 | (lt:SI (match_dup 1) (match_dup 2))) | |
11981 | (set (match_dup 3) | |
11982 | (compare:CC (match_dup 0) | |
11983 | (const_int 0)))] | |
11984 | "") | |
1fd4e8c1 RK |
11985 | |
11986 | (define_insn "" | |
097657c3 | 11987 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 11988 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 11989 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 11990 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 11991 | "TARGET_POWER" |
097657c3 | 11992 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 11993 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
11994 | |
11995 | (define_insn "" | |
9ebbca7d | 11996 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 11997 | (compare:CC |
9ebbca7d GK |
11998 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
11999 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12000 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12001 | (const_int 0))) |
9ebbca7d | 12002 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12003 | "TARGET_POWER" |
9ebbca7d GK |
12004 | "@ |
12005 | doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
12006 | #" | |
b19003d8 | 12007 | [(set_attr "type" "compare") |
9ebbca7d GK |
12008 | (set_attr "length" "12,16")]) |
12009 | ||
12010 | (define_split | |
12011 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12012 | (compare:CC | |
12013 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12014 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12015 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12016 | (const_int 0))) | |
12017 | (clobber (match_scratch:SI 4 ""))] | |
12018 | "TARGET_POWER && reload_completed" | |
12019 | [(set (match_dup 4) | |
12020 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12021 | (match_dup 3))) |
9ebbca7d GK |
12022 | (set (match_dup 0) |
12023 | (compare:CC (match_dup 4) | |
12024 | (const_int 0)))] | |
12025 | "") | |
1fd4e8c1 RK |
12026 | |
12027 | (define_insn "" | |
097657c3 | 12028 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12029 | (compare:CC |
9ebbca7d GK |
12030 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12031 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12032 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12033 | (const_int 0))) |
097657c3 AM |
12034 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12035 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12036 | "TARGET_POWER" |
9ebbca7d | 12037 | "@ |
097657c3 | 12038 | doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 12039 | #" |
b19003d8 | 12040 | [(set_attr "type" "compare") |
9ebbca7d GK |
12041 | (set_attr "length" "12,16")]) |
12042 | ||
12043 | (define_split | |
097657c3 | 12044 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12045 | (compare:CC |
12046 | (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12047 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12048 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12049 | (const_int 0))) | |
12050 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12051 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12052 | "TARGET_POWER && reload_completed" |
097657c3 | 12053 | [(set (match_dup 0) |
9ebbca7d | 12054 | (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12055 | (set (match_dup 4) |
9ebbca7d GK |
12056 | (compare:CC (match_dup 0) |
12057 | (const_int 0)))] | |
12058 | "") | |
1fd4e8c1 RK |
12059 | |
12060 | (define_insn "" | |
cd2b37d9 RK |
12061 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12062 | (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12063 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12064 | "TARGET_POWER" |
12065 | "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12066 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12067 | |
c0600ecd | 12068 | (define_insn_and_split "" |
cd2b37d9 RK |
12069 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12070 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12071 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
683bdff7 | 12072 | "TARGET_32BIT" |
c0600ecd DE |
12073 | "#" |
12074 | "TARGET_32BIT" | |
12075 | [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2)))) | |
12076 | (set (match_dup 0) (neg:SI (match_dup 0)))] | |
12077 | "") | |
12078 | ||
12079 | (define_insn_and_split "" | |
12080 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12081 | (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12082 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
12083 | "TARGET_64BIT" | |
12084 | "#" | |
12085 | "TARGET_64BIT" | |
12086 | [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2)))) | |
12087 | (set (match_dup 0) (neg:DI (match_dup 0)))] | |
12088 | "") | |
1fd4e8c1 RK |
12089 | |
12090 | (define_insn "" | |
9ebbca7d | 12091 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12092 | (compare:CC |
9ebbca7d GK |
12093 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12094 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12095 | (const_int 0))) |
9ebbca7d | 12096 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12097 | (ltu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12098 | "TARGET_32BIT" |
1fd4e8c1 | 12099 | "@ |
ca7f5001 | 12100 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
9ebbca7d GK |
12101 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 |
12102 | # | |
12103 | #" | |
b19003d8 | 12104 | [(set_attr "type" "compare") |
9ebbca7d GK |
12105 | (set_attr "length" "12,12,16,16")]) |
12106 | ||
12107 | (define_split | |
12108 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12109 | (compare:CC | |
12110 | (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12111 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12112 | (const_int 0))) | |
12113 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12114 | (ltu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12115 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12116 | [(set (match_dup 0) |
12117 | (ltu:SI (match_dup 1) (match_dup 2))) | |
12118 | (set (match_dup 3) | |
12119 | (compare:CC (match_dup 0) | |
12120 | (const_int 0)))] | |
12121 | "") | |
1fd4e8c1 | 12122 | |
c0600ecd | 12123 | (define_insn_and_split "" |
04fa46cf | 12124 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") |
c0600ecd DE |
12125 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12126 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) | |
12127 | (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))] | |
683bdff7 | 12128 | "TARGET_32BIT" |
c0600ecd | 12129 | "#" |
04fa46cf | 12130 | "&& !reg_overlap_mentioned_p (operands[0], operands[3])" |
c0600ecd DE |
12131 | [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2)))) |
12132 | (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))] | |
12133 | "") | |
12134 | ||
12135 | (define_insn_and_split "" | |
04fa46cf | 12136 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") |
c0600ecd DE |
12137 | (plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
12138 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")) | |
12139 | (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))] | |
12140 | "TARGET_64BIT" | |
12141 | "#" | |
04fa46cf | 12142 | "&& !reg_overlap_mentioned_p (operands[0], operands[3])" |
c0600ecd DE |
12143 | [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2)))) |
12144 | (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))] | |
12145 | "") | |
1fd4e8c1 RK |
12146 | |
12147 | (define_insn "" | |
9ebbca7d | 12148 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12149 | (compare:CC |
9ebbca7d GK |
12150 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12151 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12152 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12153 | (const_int 0))) |
9ebbca7d | 12154 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12155 | "TARGET_32BIT" |
1fd4e8c1 | 12156 | "@ |
c9dbf840 DE |
12157 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3 |
12158 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3 | |
9ebbca7d GK |
12159 | # |
12160 | #" | |
b19003d8 | 12161 | [(set_attr "type" "compare") |
9ebbca7d GK |
12162 | (set_attr "length" "12,12,16,16")]) |
12163 | ||
12164 | (define_split | |
12165 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12166 | (compare:CC | |
12167 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12168 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12169 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12170 | (const_int 0))) | |
12171 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12172 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12173 | [(set (match_dup 4) |
12174 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12175 | (match_dup 3))) |
9ebbca7d GK |
12176 | (set (match_dup 0) |
12177 | (compare:CC (match_dup 4) | |
12178 | (const_int 0)))] | |
12179 | "") | |
1fd4e8c1 RK |
12180 | |
12181 | (define_insn "" | |
097657c3 | 12182 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12183 | (compare:CC |
9ebbca7d GK |
12184 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12185 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12186 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12187 | (const_int 0))) |
097657c3 AM |
12188 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12189 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 12190 | "TARGET_32BIT" |
1fd4e8c1 | 12191 | "@ |
c9dbf840 DE |
12192 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 |
12193 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 | |
9ebbca7d GK |
12194 | # |
12195 | #" | |
b19003d8 | 12196 | [(set_attr "type" "compare") |
9ebbca7d GK |
12197 | (set_attr "length" "12,12,16,16")]) |
12198 | ||
12199 | (define_split | |
097657c3 | 12200 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12201 | (compare:CC |
12202 | (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12203 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12204 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12205 | (const_int 0))) | |
12206 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12207 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 12208 | "TARGET_32BIT && reload_completed" |
097657c3 | 12209 | [(set (match_dup 0) |
9ebbca7d | 12210 | (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12211 | (set (match_dup 4) |
9ebbca7d GK |
12212 | (compare:CC (match_dup 0) |
12213 | (const_int 0)))] | |
12214 | "") | |
1fd4e8c1 RK |
12215 | |
12216 | (define_insn "" | |
cd2b37d9 RK |
12217 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12218 | (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12219 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] |
683bdff7 | 12220 | "TARGET_32BIT" |
1fd4e8c1 | 12221 | "@ |
ca7f5001 RK |
12222 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 |
12223 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
943c15ed | 12224 | [(set_attr "type" "two") |
c0600ecd DE |
12225 | (set_attr "length" "8")]) |
12226 | ||
12227 | (define_insn "" | |
12228 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12229 | (neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12230 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))] | |
12231 | "TARGET_64BIT" | |
12232 | "@ | |
12233 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0 | |
12234 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0" | |
943c15ed | 12235 | [(set_attr "type" "two") |
c0600ecd | 12236 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
12237 | |
12238 | (define_insn "" | |
cd2b37d9 RK |
12239 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12240 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 RK |
12241 | (match_operand:SI 2 "reg_or_short_operand" "rI"))) |
12242 | (clobber (match_scratch:SI 3 "=r"))] | |
ca7f5001 RK |
12243 | "TARGET_POWER" |
12244 | "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3" | |
b19003d8 | 12245 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12246 | |
9ebbca7d GK |
12247 | (define_insn "" |
12248 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") | |
1fd4e8c1 | 12249 | (compare:CC |
9ebbca7d GK |
12250 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12251 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 12252 | (const_int 0))) |
9ebbca7d | 12253 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12254 | (ge:SI (match_dup 1) (match_dup 2))) |
9ebbca7d | 12255 | (clobber (match_scratch:SI 3 "=r,r"))] |
ca7f5001 | 12256 | "TARGET_POWER" |
9ebbca7d GK |
12257 | "@ |
12258 | doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3 | |
12259 | #" | |
12260 | [(set_attr "type" "compare") | |
12261 | (set_attr "length" "12,16")]) | |
12262 | ||
12263 | (define_split | |
12264 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") | |
12265 | (compare:CC | |
12266 | (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12267 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12268 | (const_int 0))) | |
12269 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12270 | (ge:SI (match_dup 1) (match_dup 2))) | |
12271 | (clobber (match_scratch:SI 3 ""))] | |
12272 | "TARGET_POWER && reload_completed" | |
12273 | [(parallel [(set (match_dup 0) | |
097657c3 AM |
12274 | (ge:SI (match_dup 1) (match_dup 2))) |
12275 | (clobber (match_dup 3))]) | |
9ebbca7d GK |
12276 | (set (match_dup 4) |
12277 | (compare:CC (match_dup 0) | |
12278 | (const_int 0)))] | |
12279 | "") | |
12280 | ||
1fd4e8c1 | 12281 | (define_insn "" |
097657c3 | 12282 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12283 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12284 | (match_operand:SI 2 "reg_or_short_operand" "rI")) |
097657c3 | 12285 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12286 | "TARGET_POWER" |
097657c3 | 12287 | "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3" |
b19003d8 | 12288 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12289 | |
12290 | (define_insn "" | |
9ebbca7d | 12291 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12292 | (compare:CC |
9ebbca7d GK |
12293 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12294 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12295 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12296 | (const_int 0))) |
9ebbca7d | 12297 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12298 | "TARGET_POWER" |
9ebbca7d GK |
12299 | "@ |
12300 | doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3 | |
12301 | #" | |
b19003d8 | 12302 | [(set_attr "type" "compare") |
9ebbca7d GK |
12303 | (set_attr "length" "12,16")]) |
12304 | ||
12305 | (define_split | |
12306 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12307 | (compare:CC | |
12308 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12309 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12310 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12311 | (const_int 0))) | |
12312 | (clobber (match_scratch:SI 4 ""))] | |
12313 | "TARGET_POWER && reload_completed" | |
12314 | [(set (match_dup 4) | |
12315 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 12316 | (match_dup 3))) |
9ebbca7d GK |
12317 | (set (match_dup 0) |
12318 | (compare:CC (match_dup 4) | |
12319 | (const_int 0)))] | |
12320 | "") | |
1fd4e8c1 RK |
12321 | |
12322 | (define_insn "" | |
097657c3 | 12323 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12324 | (compare:CC |
9ebbca7d GK |
12325 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12326 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
12327 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12328 | (const_int 0))) |
097657c3 AM |
12329 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12330 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12331 | "TARGET_POWER" |
9ebbca7d | 12332 | "@ |
097657c3 | 12333 | doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3 |
9ebbca7d | 12334 | #" |
b19003d8 | 12335 | [(set_attr "type" "compare") |
9ebbca7d GK |
12336 | (set_attr "length" "12,16")]) |
12337 | ||
12338 | (define_split | |
097657c3 | 12339 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12340 | (compare:CC |
12341 | (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12342 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12343 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12344 | (const_int 0))) | |
12345 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12346 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12347 | "TARGET_POWER && reload_completed" |
097657c3 | 12348 | [(set (match_dup 0) |
9ebbca7d | 12349 | (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12350 | (set (match_dup 4) |
9ebbca7d GK |
12351 | (compare:CC (match_dup 0) |
12352 | (const_int 0)))] | |
12353 | "") | |
1fd4e8c1 RK |
12354 | |
12355 | (define_insn "" | |
cd2b37d9 RK |
12356 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12357 | (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12358 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
ca7f5001 RK |
12359 | "TARGET_POWER" |
12360 | "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0" | |
b19003d8 | 12361 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12362 | |
1fd4e8c1 | 12363 | (define_insn "" |
cd2b37d9 RK |
12364 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12365 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12366 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] |
683bdff7 | 12367 | "TARGET_32BIT" |
1fd4e8c1 | 12368 | "@ |
ca7f5001 RK |
12369 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0 |
12370 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0" | |
943c15ed DE |
12371 | [(set_attr "type" "three") |
12372 | (set_attr "length" "12")]) | |
1fd4e8c1 | 12373 | |
f9562f27 DE |
12374 | (define_insn "" |
12375 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") | |
12376 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") | |
12377 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))] | |
683bdff7 | 12378 | "TARGET_64BIT" |
f9562f27 DE |
12379 | "@ |
12380 | subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 | |
12381 | addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" | |
943c15ed DE |
12382 | [(set_attr "type" "three") |
12383 | (set_attr "length" "12")]) | |
f9562f27 | 12384 | |
1fd4e8c1 | 12385 | (define_insn "" |
9ebbca7d | 12386 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12387 | (compare:CC |
9ebbca7d GK |
12388 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12389 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
1fd4e8c1 | 12390 | (const_int 0))) |
9ebbca7d | 12391 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") |
1fd4e8c1 | 12392 | (geu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12393 | "TARGET_32BIT" |
1fd4e8c1 | 12394 | "@ |
ca7f5001 | 12395 | {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
9ebbca7d GK |
12396 | {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0 |
12397 | # | |
12398 | #" | |
b19003d8 | 12399 | [(set_attr "type" "compare") |
9ebbca7d GK |
12400 | (set_attr "length" "12,12,16,16")]) |
12401 | ||
12402 | (define_split | |
12403 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12404 | (compare:CC | |
12405 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12406 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12407 | (const_int 0))) | |
12408 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12409 | (geu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12410 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12411 | [(set (match_dup 0) |
12412 | (geu:SI (match_dup 1) (match_dup 2))) | |
12413 | (set (match_dup 3) | |
12414 | (compare:CC (match_dup 0) | |
12415 | (const_int 0)))] | |
12416 | "") | |
1fd4e8c1 | 12417 | |
f9562f27 | 12418 | (define_insn "" |
9ebbca7d | 12419 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 12420 | (compare:CC |
9ebbca7d GK |
12421 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
12422 | (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
f9562f27 | 12423 | (const_int 0))) |
9ebbca7d | 12424 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") |
f9562f27 | 12425 | (geu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 12426 | "TARGET_64BIT" |
f9562f27 DE |
12427 | "@ |
12428 | subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 | |
9ebbca7d GK |
12429 | addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 |
12430 | # | |
12431 | #" | |
f9562f27 | 12432 | [(set_attr "type" "compare") |
9ebbca7d GK |
12433 | (set_attr "length" "12,12,16,16")]) |
12434 | ||
12435 | (define_split | |
12436 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12437 | (compare:CC | |
12438 | (geu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12439 | (match_operand:DI 2 "reg_or_neg_short_operand" "")) | |
12440 | (const_int 0))) | |
12441 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12442 | (geu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 12443 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
12444 | [(set (match_dup 0) |
12445 | (geu:DI (match_dup 1) (match_dup 2))) | |
12446 | (set (match_dup 3) | |
12447 | (compare:CC (match_dup 0) | |
12448 | (const_int 0)))] | |
12449 | "") | |
f9562f27 | 12450 | |
1fd4e8c1 | 12451 | (define_insn "" |
80103f96 | 12452 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
cd2b37d9 | 12453 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12454 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) |
80103f96 | 12455 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
683bdff7 | 12456 | "TARGET_32BIT" |
1fd4e8c1 | 12457 | "@ |
80103f96 FS |
12458 | {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3 |
12459 | {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3" | |
943c15ed DE |
12460 | [(set_attr "type" "two") |
12461 | (set_attr "length" "8")]) | |
1fd4e8c1 RK |
12462 | |
12463 | (define_insn "" | |
9ebbca7d | 12464 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12465 | (compare:CC |
9ebbca7d GK |
12466 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12467 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12468 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12469 | (const_int 0))) |
9ebbca7d | 12470 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12471 | "TARGET_32BIT" |
1fd4e8c1 | 12472 | "@ |
ca7f5001 | 12473 | {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3 |
9ebbca7d GK |
12474 | {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3 |
12475 | # | |
12476 | #" | |
b19003d8 | 12477 | [(set_attr "type" "compare") |
9ebbca7d GK |
12478 | (set_attr "length" "8,8,12,12")]) |
12479 | ||
12480 | (define_split | |
12481 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12482 | (compare:CC | |
12483 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12484 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12485 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12486 | (const_int 0))) | |
12487 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12488 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12489 | [(set (match_dup 4) |
12490 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) | |
12491 | (match_dup 3))) | |
12492 | (set (match_dup 0) | |
12493 | (compare:CC (match_dup 4) | |
12494 | (const_int 0)))] | |
12495 | "") | |
1fd4e8c1 RK |
12496 | |
12497 | (define_insn "" | |
097657c3 | 12498 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 12499 | (compare:CC |
9ebbca7d GK |
12500 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12501 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) | |
12502 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12503 | (const_int 0))) |
097657c3 AM |
12504 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12505 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 12506 | "TARGET_32BIT" |
1fd4e8c1 | 12507 | "@ |
097657c3 AM |
12508 | {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3 |
12509 | {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3 | |
9ebbca7d GK |
12510 | # |
12511 | #" | |
b19003d8 | 12512 | [(set_attr "type" "compare") |
9ebbca7d GK |
12513 | (set_attr "length" "8,8,12,12")]) |
12514 | ||
12515 | (define_split | |
097657c3 | 12516 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12517 | (compare:CC |
12518 | (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12519 | (match_operand:SI 2 "reg_or_neg_short_operand" "")) | |
12520 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12521 | (const_int 0))) | |
12522 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12523 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 12524 | "TARGET_32BIT && reload_completed" |
097657c3 | 12525 | [(set (match_dup 0) |
9ebbca7d | 12526 | (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12527 | (set (match_dup 4) |
9ebbca7d GK |
12528 | (compare:CC (match_dup 0) |
12529 | (const_int 0)))] | |
12530 | "") | |
1fd4e8c1 RK |
12531 | |
12532 | (define_insn "" | |
cd2b37d9 RK |
12533 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
12534 | (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
1fd4e8c1 | 12535 | (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] |
683bdff7 | 12536 | "TARGET_32BIT" |
1fd4e8c1 | 12537 | "@ |
ca7f5001 | 12538 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0 |
8106dc08 | 12539 | {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0" |
943c15ed DE |
12540 | [(set_attr "type" "three") |
12541 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
12542 | |
12543 | (define_insn "" | |
097657c3 | 12544 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
1fd4e8c1 | 12545 | (and:SI (neg:SI |
cd2b37d9 | 12546 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12547 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) |
097657c3 | 12548 | (match_operand:SI 3 "gpc_reg_operand" "r,r")))] |
683bdff7 | 12549 | "TARGET_32BIT" |
1fd4e8c1 | 12550 | "@ |
097657c3 AM |
12551 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0 |
12552 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0" | |
943c15ed DE |
12553 | [(set_attr "type" "three") |
12554 | (set_attr "length" "12")]) | |
1fd4e8c1 RK |
12555 | |
12556 | (define_insn "" | |
9ebbca7d | 12557 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12558 | (compare:CC |
12559 | (and:SI (neg:SI | |
9ebbca7d GK |
12560 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12561 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12562 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12563 | (const_int 0))) |
9ebbca7d | 12564 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 12565 | "TARGET_32BIT" |
1fd4e8c1 | 12566 | "@ |
ca7f5001 | 12567 | {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
9ebbca7d GK |
12568 | {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4 |
12569 | # | |
12570 | #" | |
b19003d8 | 12571 | [(set_attr "type" "compare") |
9ebbca7d GK |
12572 | (set_attr "length" "12,12,16,16")]) |
12573 | ||
12574 | (define_split | |
12575 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12576 | (compare:CC | |
12577 | (and:SI (neg:SI | |
12578 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12579 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
12580 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12581 | (const_int 0))) | |
12582 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 12583 | "TARGET_32BIT && reload_completed" |
9ebbca7d | 12584 | [(set (match_dup 4) |
097657c3 AM |
12585 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) |
12586 | (match_dup 3))) | |
9ebbca7d GK |
12587 | (set (match_dup 0) |
12588 | (compare:CC (match_dup 4) | |
12589 | (const_int 0)))] | |
12590 | "") | |
1fd4e8c1 RK |
12591 | |
12592 | (define_insn "" | |
097657c3 | 12593 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 RK |
12594 | (compare:CC |
12595 | (and:SI (neg:SI | |
9ebbca7d GK |
12596 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
12597 | (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) | |
12598 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 12599 | (const_int 0))) |
097657c3 AM |
12600 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
12601 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] | |
683bdff7 | 12602 | "TARGET_32BIT" |
1fd4e8c1 | 12603 | "@ |
097657c3 AM |
12604 | {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 |
12605 | {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0 | |
9ebbca7d GK |
12606 | # |
12607 | #" | |
b19003d8 | 12608 | [(set_attr "type" "compare") |
9ebbca7d GK |
12609 | (set_attr "length" "12,12,16,16")]) |
12610 | ||
12611 | (define_split | |
097657c3 | 12612 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12613 | (compare:CC |
12614 | (and:SI (neg:SI | |
12615 | (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12616 | (match_operand:SI 2 "reg_or_neg_short_operand" ""))) | |
12617 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12618 | (const_int 0))) | |
12619 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12620 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] |
683bdff7 | 12621 | "TARGET_32BIT && reload_completed" |
097657c3 | 12622 | [(set (match_dup 0) |
9ebbca7d | 12623 | (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) |
097657c3 | 12624 | (set (match_dup 4) |
9ebbca7d GK |
12625 | (compare:CC (match_dup 0) |
12626 | (const_int 0)))] | |
12627 | "") | |
1fd4e8c1 RK |
12628 | |
12629 | (define_insn "" | |
cd2b37d9 RK |
12630 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12631 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12632 | (const_int 0)))] |
683bdff7 | 12633 | "TARGET_32BIT" |
ca7f5001 | 12634 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31" |
943c15ed DE |
12635 | [(set_attr "type" "three") |
12636 | (set_attr "length" "12")]) | |
1fd4e8c1 | 12637 | |
f9562f27 DE |
12638 | (define_insn "" |
12639 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12640 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12641 | (const_int 0)))] | |
683bdff7 | 12642 | "TARGET_64BIT" |
f9562f27 | 12643 | "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63" |
943c15ed DE |
12644 | [(set_attr "type" "three") |
12645 | (set_attr "length" "12")]) | |
f9562f27 | 12646 | |
1fd4e8c1 | 12647 | (define_insn "" |
9ebbca7d | 12648 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12649 | (compare:CC |
9ebbca7d | 12650 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 RK |
12651 | (const_int 0)) |
12652 | (const_int 0))) | |
9ebbca7d | 12653 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12654 | (gt:SI (match_dup 1) (const_int 0)))] |
683bdff7 | 12655 | "TARGET_32BIT" |
9ebbca7d GK |
12656 | "@ |
12657 | {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31 | |
12658 | #" | |
29ae5b89 | 12659 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12660 | (set_attr "length" "12,16")]) |
12661 | ||
12662 | (define_split | |
12663 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
12664 | (compare:CC | |
12665 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12666 | (const_int 0)) | |
12667 | (const_int 0))) | |
12668 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12669 | (gt:SI (match_dup 1) (const_int 0)))] | |
683bdff7 | 12670 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12671 | [(set (match_dup 0) |
12672 | (gt:SI (match_dup 1) (const_int 0))) | |
12673 | (set (match_dup 2) | |
12674 | (compare:CC (match_dup 0) | |
12675 | (const_int 0)))] | |
12676 | "") | |
1fd4e8c1 | 12677 | |
f9562f27 | 12678 | (define_insn "" |
9ebbca7d | 12679 | [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") |
f9562f27 | 12680 | (compare:CC |
9ebbca7d | 12681 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 DE |
12682 | (const_int 0)) |
12683 | (const_int 0))) | |
9ebbca7d | 12684 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 12685 | (gt:DI (match_dup 1) (const_int 0)))] |
683bdff7 | 12686 | "TARGET_64BIT" |
9ebbca7d GK |
12687 | "@ |
12688 | subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63 | |
12689 | #" | |
f9562f27 | 12690 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12691 | (set_attr "length" "12,16")]) |
12692 | ||
12693 | (define_split | |
12694 | [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") | |
12695 | (compare:CC | |
12696 | (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12697 | (const_int 0)) | |
12698 | (const_int 0))) | |
12699 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
12700 | (gt:DI (match_dup 1) (const_int 0)))] | |
683bdff7 | 12701 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
12702 | [(set (match_dup 0) |
12703 | (gt:DI (match_dup 1) (const_int 0))) | |
12704 | (set (match_dup 2) | |
12705 | (compare:CC (match_dup 0) | |
12706 | (const_int 0)))] | |
12707 | "") | |
f9562f27 | 12708 | |
1fd4e8c1 | 12709 | (define_insn "" |
cd2b37d9 RK |
12710 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12711 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12712 | (match_operand:SI 2 "reg_or_short_operand" "r")))] |
ca7f5001 RK |
12713 | "TARGET_POWER" |
12714 | "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31" | |
b19003d8 | 12715 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12716 | |
12717 | (define_insn "" | |
9ebbca7d | 12718 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12719 | (compare:CC |
9ebbca7d GK |
12720 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12721 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
1fd4e8c1 | 12722 | (const_int 0))) |
9ebbca7d | 12723 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 12724 | (gt:SI (match_dup 1) (match_dup 2)))] |
ca7f5001 | 12725 | "TARGET_POWER" |
9ebbca7d GK |
12726 | "@ |
12727 | doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31 | |
12728 | #" | |
29ae5b89 | 12729 | [(set_attr "type" "delayed_compare") |
9ebbca7d GK |
12730 | (set_attr "length" "12,16")]) |
12731 | ||
12732 | (define_split | |
12733 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
12734 | (compare:CC | |
12735 | (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12736 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12737 | (const_int 0))) | |
12738 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
12739 | (gt:SI (match_dup 1) (match_dup 2)))] | |
12740 | "TARGET_POWER && reload_completed" | |
12741 | [(set (match_dup 0) | |
12742 | (gt:SI (match_dup 1) (match_dup 2))) | |
12743 | (set (match_dup 3) | |
12744 | (compare:CC (match_dup 0) | |
12745 | (const_int 0)))] | |
12746 | "") | |
1fd4e8c1 RK |
12747 | |
12748 | (define_insn "" | |
80103f96 | 12749 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12750 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12751 | (const_int 0)) |
80103f96 | 12752 | (match_operand:SI 2 "gpc_reg_operand" "r")))] |
683bdff7 | 12753 | "TARGET_32BIT" |
80103f96 | 12754 | "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2" |
943c15ed DE |
12755 | [(set_attr "type" "three") |
12756 | (set_attr "length" "12")]) | |
1fd4e8c1 | 12757 | |
f9562f27 | 12758 | (define_insn "" |
097657c3 | 12759 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
f9562f27 DE |
12760 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
12761 | (const_int 0)) | |
097657c3 | 12762 | (match_operand:DI 2 "gpc_reg_operand" "r")))] |
683bdff7 | 12763 | "TARGET_64BIT" |
097657c3 | 12764 | "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2" |
943c15ed DE |
12765 | [(set_attr "type" "three") |
12766 | (set_attr "length" "12")]) | |
f9562f27 | 12767 | |
1fd4e8c1 | 12768 | (define_insn "" |
9ebbca7d | 12769 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12770 | (compare:CC |
9ebbca7d | 12771 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
1fd4e8c1 | 12772 | (const_int 0)) |
9ebbca7d | 12773 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) |
1fd4e8c1 | 12774 | (const_int 0))) |
9ebbca7d | 12775 | (clobber (match_scratch:SI 3 "=&r,&r"))] |
683bdff7 | 12776 | "TARGET_32BIT" |
9ebbca7d GK |
12777 | "@ |
12778 | {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2 | |
12779 | #" | |
b19003d8 | 12780 | [(set_attr "type" "compare") |
9ebbca7d GK |
12781 | (set_attr "length" "12,16")]) |
12782 | ||
12783 | (define_split | |
12784 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12785 | (compare:CC | |
12786 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12787 | (const_int 0)) | |
12788 | (match_operand:SI 2 "gpc_reg_operand" "")) | |
12789 | (const_int 0))) | |
12790 | (clobber (match_scratch:SI 3 ""))] | |
683bdff7 | 12791 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
12792 | [(set (match_dup 3) |
12793 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) | |
12794 | (match_dup 2))) | |
12795 | (set (match_dup 0) | |
12796 | (compare:CC (match_dup 3) | |
12797 | (const_int 0)))] | |
12798 | "") | |
1fd4e8c1 | 12799 | |
f9562f27 | 12800 | (define_insn "" |
9ebbca7d | 12801 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
f9562f27 | 12802 | (compare:CC |
9ebbca7d | 12803 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 12804 | (const_int 0)) |
9ebbca7d | 12805 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 12806 | (const_int 0))) |
9ebbca7d | 12807 | (clobber (match_scratch:DI 3 "=&r,&r"))] |
683bdff7 | 12808 | "TARGET_64BIT" |
9ebbca7d GK |
12809 | "@ |
12810 | addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 | |
12811 | #" | |
f9562f27 | 12812 | [(set_attr "type" "compare") |
9ebbca7d GK |
12813 | (set_attr "length" "12,16")]) |
12814 | ||
12815 | (define_split | |
12816 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12817 | (compare:CC | |
12818 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12819 | (const_int 0)) | |
12820 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
12821 | (const_int 0))) | |
12822 | (clobber (match_scratch:DI 3 ""))] | |
683bdff7 | 12823 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
12824 | [(set (match_dup 3) |
12825 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) | |
097657c3 | 12826 | (match_dup 2))) |
9ebbca7d GK |
12827 | (set (match_dup 0) |
12828 | (compare:CC (match_dup 3) | |
12829 | (const_int 0)))] | |
12830 | "") | |
f9562f27 | 12831 | |
1fd4e8c1 | 12832 | (define_insn "" |
097657c3 | 12833 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
9ebbca7d GK |
12834 | (compare:CC |
12835 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") | |
12836 | (const_int 0)) | |
12837 | (match_operand:SI 2 "gpc_reg_operand" "r,r")) | |
12838 | (const_int 0))) | |
097657c3 AM |
12839 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12840 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
683bdff7 | 12841 | "TARGET_32BIT" |
9ebbca7d | 12842 | "@ |
097657c3 | 12843 | {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2 |
9ebbca7d GK |
12844 | #" |
12845 | [(set_attr "type" "compare") | |
12846 | (set_attr "length" "12,16")]) | |
12847 | ||
12848 | (define_split | |
097657c3 | 12849 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
1fd4e8c1 | 12850 | (compare:CC |
9ebbca7d | 12851 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") |
1fd4e8c1 | 12852 | (const_int 0)) |
9ebbca7d | 12853 | (match_operand:SI 2 "gpc_reg_operand" "")) |
1fd4e8c1 | 12854 | (const_int 0))) |
9ebbca7d | 12855 | (set (match_operand:SI 0 "gpc_reg_operand" "") |
097657c3 | 12856 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] |
683bdff7 | 12857 | "TARGET_32BIT && reload_completed" |
097657c3 | 12858 | [(set (match_dup 0) |
9ebbca7d | 12859 | (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 12860 | (set (match_dup 3) |
9ebbca7d GK |
12861 | (compare:CC (match_dup 0) |
12862 | (const_int 0)))] | |
12863 | "") | |
1fd4e8c1 | 12864 | |
f9562f27 | 12865 | (define_insn "" |
097657c3 | 12866 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 12867 | (compare:CC |
9ebbca7d | 12868 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
f9562f27 | 12869 | (const_int 0)) |
9ebbca7d | 12870 | (match_operand:DI 2 "gpc_reg_operand" "r,r")) |
f9562f27 | 12871 | (const_int 0))) |
097657c3 AM |
12872 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") |
12873 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] | |
683bdff7 | 12874 | "TARGET_64BIT" |
9ebbca7d | 12875 | "@ |
097657c3 | 12876 | addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 |
9ebbca7d | 12877 | #" |
f9562f27 | 12878 | [(set_attr "type" "compare") |
9ebbca7d GK |
12879 | (set_attr "length" "12,16")]) |
12880 | ||
12881 | (define_split | |
097657c3 | 12882 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12883 | (compare:CC |
12884 | (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
12885 | (const_int 0)) | |
12886 | (match_operand:DI 2 "gpc_reg_operand" "")) | |
12887 | (const_int 0))) | |
12888 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 12889 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] |
683bdff7 | 12890 | "TARGET_64BIT && reload_completed" |
097657c3 | 12891 | [(set (match_dup 0) |
9ebbca7d | 12892 | (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) |
097657c3 | 12893 | (set (match_dup 3) |
9ebbca7d GK |
12894 | (compare:CC (match_dup 0) |
12895 | (const_int 0)))] | |
12896 | "") | |
f9562f27 | 12897 | |
1fd4e8c1 | 12898 | (define_insn "" |
097657c3 | 12899 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
cd2b37d9 | 12900 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
1fd4e8c1 | 12901 | (match_operand:SI 2 "reg_or_short_operand" "r")) |
097657c3 | 12902 | (match_operand:SI 3 "gpc_reg_operand" "r")))] |
ca7f5001 | 12903 | "TARGET_POWER" |
097657c3 | 12904 | "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3" |
b19003d8 | 12905 | [(set_attr "length" "12")]) |
1fd4e8c1 RK |
12906 | |
12907 | (define_insn "" | |
9ebbca7d | 12908 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12909 | (compare:CC |
9ebbca7d GK |
12910 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12911 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
12912 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12913 | (const_int 0))) |
9ebbca7d | 12914 | (clobber (match_scratch:SI 4 "=&r,&r"))] |
ca7f5001 | 12915 | "TARGET_POWER" |
9ebbca7d GK |
12916 | "@ |
12917 | doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3 | |
12918 | #" | |
b19003d8 | 12919 | [(set_attr "type" "compare") |
9ebbca7d GK |
12920 | (set_attr "length" "12,16")]) |
12921 | ||
12922 | (define_split | |
12923 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
12924 | (compare:CC | |
12925 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12926 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12927 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12928 | (const_int 0))) | |
12929 | (clobber (match_scratch:SI 4 ""))] | |
12930 | "TARGET_POWER && reload_completed" | |
12931 | [(set (match_dup 4) | |
097657c3 | 12932 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
9ebbca7d GK |
12933 | (set (match_dup 0) |
12934 | (compare:CC (match_dup 4) | |
12935 | (const_int 0)))] | |
12936 | "") | |
1fd4e8c1 RK |
12937 | |
12938 | (define_insn "" | |
097657c3 | 12939 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 12940 | (compare:CC |
9ebbca7d GK |
12941 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
12942 | (match_operand:SI 2 "reg_or_short_operand" "r,r")) | |
12943 | (match_operand:SI 3 "gpc_reg_operand" "r,r")) | |
1fd4e8c1 | 12944 | (const_int 0))) |
097657c3 AM |
12945 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") |
12946 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
ca7f5001 | 12947 | "TARGET_POWER" |
9ebbca7d | 12948 | "@ |
097657c3 | 12949 | doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3 |
9ebbca7d | 12950 | #" |
b19003d8 | 12951 | [(set_attr "type" "compare") |
9ebbca7d GK |
12952 | (set_attr "length" "12,16")]) |
12953 | ||
12954 | (define_split | |
097657c3 | 12955 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
12956 | (compare:CC |
12957 | (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
12958 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
12959 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
12960 | (const_int 0))) | |
12961 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 12962 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
9ebbca7d | 12963 | "TARGET_POWER && reload_completed" |
097657c3 | 12964 | [(set (match_dup 0) |
9ebbca7d | 12965 | (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 12966 | (set (match_dup 4) |
9ebbca7d GK |
12967 | (compare:CC (match_dup 0) |
12968 | (const_int 0)))] | |
12969 | "") | |
1fd4e8c1 RK |
12970 | |
12971 | (define_insn "" | |
cd2b37d9 RK |
12972 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12973 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12974 | (const_int 0))))] |
683bdff7 | 12975 | "TARGET_32BIT" |
ca7f5001 | 12976 | "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31" |
943c15ed DE |
12977 | [(set_attr "type" "three") |
12978 | (set_attr "length" "12")]) | |
1fd4e8c1 | 12979 | |
f9562f27 DE |
12980 | (define_insn "" |
12981 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
12982 | (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
12983 | (const_int 0))))] | |
683bdff7 | 12984 | "TARGET_64BIT" |
8377288b | 12985 | "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63" |
943c15ed DE |
12986 | [(set_attr "type" "three") |
12987 | (set_attr "length" "12")]) | |
f9562f27 | 12988 | |
1fd4e8c1 | 12989 | (define_insn "" |
cd2b37d9 RK |
12990 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
12991 | (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 12992 | (match_operand:SI 2 "reg_or_short_operand" "r"))))] |
ca7f5001 RK |
12993 | "TARGET_POWER" |
12994 | "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31" | |
b19003d8 | 12995 | [(set_attr "length" "12")]) |
1fd4e8c1 | 12996 | |
c0600ecd | 12997 | (define_insn_and_split "" |
cd2b37d9 | 12998 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
c0600ecd DE |
12999 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
13000 | (match_operand:SI 2 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13001 | "TARGET_32BIT" |
c0600ecd DE |
13002 | "#" |
13003 | "TARGET_32BIT" | |
13004 | [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2)))) | |
13005 | (set (match_dup 0) (neg:SI (match_dup 0)))] | |
13006 | "") | |
1fd4e8c1 | 13007 | |
c0600ecd | 13008 | (define_insn_and_split "" |
f9562f27 | 13009 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") |
c0600ecd DE |
13010 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
13011 | (match_operand:DI 2 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13012 | "TARGET_64BIT" |
c0600ecd DE |
13013 | "#" |
13014 | "TARGET_64BIT" | |
13015 | [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2)))) | |
13016 | (set (match_dup 0) (neg:DI (match_dup 0)))] | |
13017 | "") | |
f9562f27 | 13018 | |
1fd4e8c1 | 13019 | (define_insn "" |
9ebbca7d | 13020 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
1fd4e8c1 | 13021 | (compare:CC |
9ebbca7d GK |
13022 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") |
13023 | (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) | |
1fd4e8c1 | 13024 | (const_int 0))) |
9ebbca7d | 13025 | (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") |
1fd4e8c1 | 13026 | (gtu:SI (match_dup 1) (match_dup 2)))] |
683bdff7 | 13027 | "TARGET_32BIT" |
9ebbca7d GK |
13028 | "@ |
13029 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0 | |
13030 | #" | |
b19003d8 | 13031 | [(set_attr "type" "compare") |
9ebbca7d GK |
13032 | (set_attr "length" "12,16")]) |
13033 | ||
13034 | (define_split | |
13035 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13036 | (compare:CC | |
13037 | (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13038 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13039 | (const_int 0))) | |
13040 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
13041 | (gtu:SI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 13042 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13043 | [(set (match_dup 0) |
13044 | (gtu:SI (match_dup 1) (match_dup 2))) | |
13045 | (set (match_dup 3) | |
13046 | (compare:CC (match_dup 0) | |
13047 | (const_int 0)))] | |
13048 | "") | |
1fd4e8c1 | 13049 | |
f9562f27 | 13050 | (define_insn "" |
9ebbca7d | 13051 | [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") |
f9562f27 | 13052 | (compare:CC |
9ebbca7d GK |
13053 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") |
13054 | (match_operand:DI 2 "reg_or_short_operand" "rI,rI")) | |
f9562f27 | 13055 | (const_int 0))) |
9ebbca7d | 13056 | (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") |
f9562f27 | 13057 | (gtu:DI (match_dup 1) (match_dup 2)))] |
683bdff7 | 13058 | "TARGET_64BIT" |
9ebbca7d GK |
13059 | "@ |
13060 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0 | |
13061 | #" | |
f9562f27 | 13062 | [(set_attr "type" "compare") |
9ebbca7d GK |
13063 | (set_attr "length" "12,16")]) |
13064 | ||
13065 | (define_split | |
13066 | [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") | |
13067 | (compare:CC | |
13068 | (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13069 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13070 | (const_int 0))) | |
13071 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
13072 | (gtu:DI (match_dup 1) (match_dup 2)))] | |
683bdff7 | 13073 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13074 | [(set (match_dup 0) |
13075 | (gtu:DI (match_dup 1) (match_dup 2))) | |
13076 | (set (match_dup 3) | |
13077 | (compare:CC (match_dup 0) | |
13078 | (const_int 0)))] | |
13079 | "") | |
f9562f27 | 13080 | |
c0600ecd | 13081 | (define_insn_and_split "" |
04fa46cf | 13082 | [(set (match_operand:SI 0 "gpc_reg_operand" "=&r") |
c0600ecd DE |
13083 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") |
13084 | (match_operand:SI 2 "reg_or_short_operand" "rI")) | |
13085 | (match_operand:SI 3 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13086 | "TARGET_32BIT" |
c0600ecd | 13087 | "#" |
04fa46cf | 13088 | "&& !reg_overlap_mentioned_p (operands[0], operands[3])" |
c0600ecd DE |
13089 | [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2)))) |
13090 | (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))] | |
13091 | "") | |
1fd4e8c1 | 13092 | |
c0600ecd | 13093 | (define_insn_and_split "" |
04fa46cf | 13094 | [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") |
c0600ecd DE |
13095 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") |
13096 | (match_operand:DI 2 "reg_or_short_operand" "rI")) | |
13097 | (match_operand:DI 3 "reg_or_short_operand" "rI")))] | |
683bdff7 | 13098 | "TARGET_64BIT" |
c0600ecd | 13099 | "#" |
04fa46cf | 13100 | "&& !reg_overlap_mentioned_p (operands[0], operands[3])" |
c0600ecd DE |
13101 | [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2)))) |
13102 | (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))] | |
13103 | "") | |
f9562f27 | 13104 | |
1fd4e8c1 | 13105 | (define_insn "" |
9ebbca7d | 13106 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13107 | (compare:CC |
9ebbca7d GK |
13108 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13109 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13110 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13111 | (const_int 0))) |
9ebbca7d | 13112 | (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 13113 | "TARGET_32BIT" |
00751805 | 13114 | "@ |
19378cf8 | 13115 | {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3 |
c9dbf840 | 13116 | {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subf.} %4,%4,%3 |
9ebbca7d GK |
13117 | # |
13118 | #" | |
b19003d8 | 13119 | [(set_attr "type" "compare") |
9ebbca7d GK |
13120 | (set_attr "length" "8,12,12,16")]) |
13121 | ||
13122 | (define_split | |
13123 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13124 | (compare:CC | |
13125 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13126 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13127 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13128 | (const_int 0))) | |
13129 | (clobber (match_scratch:SI 4 ""))] | |
683bdff7 | 13130 | "TARGET_32BIT && reload_completed" |
9ebbca7d GK |
13131 | [(set (match_dup 4) |
13132 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) | |
097657c3 | 13133 | (match_dup 3))) |
9ebbca7d GK |
13134 | (set (match_dup 0) |
13135 | (compare:CC (match_dup 4) | |
13136 | (const_int 0)))] | |
13137 | "") | |
1fd4e8c1 | 13138 | |
f9562f27 | 13139 | (define_insn "" |
9ebbca7d | 13140 | [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13141 | (compare:CC |
9ebbca7d GK |
13142 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13143 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13144 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13145 | (const_int 0))) |
9ebbca7d | 13146 | (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))] |
683bdff7 | 13147 | "TARGET_64BIT" |
f9562f27 DE |
13148 | "@ |
13149 | addic %4,%1,%k2\;addze. %4,%3 | |
c9dbf840 | 13150 | subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subf. %4,%4,%3 |
9ebbca7d GK |
13151 | # |
13152 | #" | |
f9562f27 | 13153 | [(set_attr "type" "compare") |
9ebbca7d GK |
13154 | (set_attr "length" "8,12,12,16")]) |
13155 | ||
13156 | (define_split | |
13157 | [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") | |
13158 | (compare:CC | |
13159 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13160 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13161 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13162 | (const_int 0))) | |
13163 | (clobber (match_scratch:DI 4 ""))] | |
683bdff7 | 13164 | "TARGET_64BIT && reload_completed" |
9ebbca7d GK |
13165 | [(set (match_dup 4) |
13166 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) | |
13167 | (match_dup 3))) | |
13168 | (set (match_dup 0) | |
13169 | (compare:CC (match_dup 4) | |
13170 | (const_int 0)))] | |
13171 | "") | |
f9562f27 | 13172 | |
1fd4e8c1 | 13173 | (define_insn "" |
097657c3 | 13174 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
1fd4e8c1 | 13175 | (compare:CC |
9ebbca7d GK |
13176 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") |
13177 | (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r")) | |
13178 | (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) | |
1fd4e8c1 | 13179 | (const_int 0))) |
097657c3 AM |
13180 | (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13181 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 13182 | "TARGET_32BIT" |
00751805 | 13183 | "@ |
097657c3 | 13184 | {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3 |
c9dbf840 | 13185 | {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subf.} %0,%0,%3 |
9ebbca7d GK |
13186 | # |
13187 | #" | |
b19003d8 | 13188 | [(set_attr "type" "compare") |
9ebbca7d GK |
13189 | (set_attr "length" "8,12,12,16")]) |
13190 | ||
13191 | (define_split | |
097657c3 | 13192 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13193 | (compare:CC |
13194 | (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "") | |
13195 | (match_operand:SI 2 "reg_or_short_operand" "")) | |
13196 | (match_operand:SI 3 "gpc_reg_operand" "")) | |
13197 | (const_int 0))) | |
13198 | (set (match_operand:SI 0 "gpc_reg_operand" "") | |
097657c3 | 13199 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 13200 | "TARGET_32BIT && reload_completed" |
097657c3 | 13201 | [(set (match_dup 0) |
9ebbca7d | 13202 | (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13203 | (set (match_dup 4) |
9ebbca7d GK |
13204 | (compare:CC (match_dup 0) |
13205 | (const_int 0)))] | |
13206 | "") | |
1fd4e8c1 | 13207 | |
f9562f27 | 13208 | (define_insn "" |
097657c3 | 13209 | [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") |
f9562f27 | 13210 | (compare:CC |
9ebbca7d GK |
13211 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") |
13212 | (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r")) | |
13213 | (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r")) | |
f9562f27 | 13214 | (const_int 0))) |
097657c3 AM |
13215 | (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r") |
13216 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
683bdff7 | 13217 | "TARGET_64BIT" |
f9562f27 | 13218 | "@ |
097657c3 | 13219 | addic %0,%1,%k2\;addze. %0,%3 |
c9dbf840 | 13220 | subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf. %0,%0,%3 |
9ebbca7d GK |
13221 | # |
13222 | #" | |
f9562f27 | 13223 | [(set_attr "type" "compare") |
9ebbca7d GK |
13224 | (set_attr "length" "8,12,12,16")]) |
13225 | ||
13226 | (define_split | |
097657c3 | 13227 | [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") |
9ebbca7d GK |
13228 | (compare:CC |
13229 | (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "") | |
13230 | (match_operand:DI 2 "reg_or_short_operand" "")) | |
13231 | (match_operand:DI 3 "gpc_reg_operand" "")) | |
13232 | (const_int 0))) | |
13233 | (set (match_operand:DI 0 "gpc_reg_operand" "") | |
097657c3 | 13234 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] |
683bdff7 | 13235 | "TARGET_64BIT && reload_completed" |
097657c3 | 13236 | [(set (match_dup 0) |
9ebbca7d | 13237 | (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3))) |
097657c3 | 13238 | (set (match_dup 4) |
9ebbca7d GK |
13239 | (compare:CC (match_dup 0) |
13240 | (const_int 0)))] | |
13241 | "") | |
f9562f27 | 13242 | |
1fd4e8c1 | 13243 | (define_insn "" |
cd2b37d9 RK |
13244 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
13245 | (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") | |
1fd4e8c1 | 13246 | (match_operand:SI 2 "reg_or_short_operand" "rI"))))] |
683bdff7 | 13247 | "TARGET_32BIT" |
ca7f5001 | 13248 | "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0" |
943c15ed | 13249 | [(set_attr "type" "two") |
c0600ecd | 13250 | (set_attr "length" "8")]) |
f9562f27 DE |
13251 | |
13252 | (define_insn "" | |
13253 | [(set (match_operand:DI 0 "gpc_reg_operand" "=r") | |
13254 | (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r") | |
13255 | (match_operand:DI 2 "reg_or_short_operand" "rI"))))] | |
683bdff7 | 13256 | "TARGET_64BIT" |
f9562f27 | 13257 | "subf%I2c %0,%1,%2\;subfe %0,%0,%0" |
943c15ed | 13258 | [(set_attr "type" "two") |
c0600ecd | 13259 | (set_attr "length" "8")]) |
1fd4e8c1 RK |
13260 | \f |
13261 | ;; Define both directions of branch and return. If we need a reload | |
13262 | ;; register, we'd rather use CR0 since it is much easier to copy a | |
13263 | ;; register CC value to there. | |
13264 | ||
13265 | (define_insn "" | |
13266 | [(set (pc) | |
13267 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13268 | [(match_operand 2 | |
b54cf83a | 13269 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13270 | (const_int 0)]) |
13271 | (label_ref (match_operand 0 "" "")) | |
13272 | (pc)))] | |
13273 | "" | |
b19003d8 RK |
13274 | "* |
13275 | { | |
12a4e8c5 | 13276 | return output_cbranch (operands[1], \"%l0\", 0, insn); |
b19003d8 RK |
13277 | }" |
13278 | [(set_attr "type" "branch")]) | |
13279 | ||
1fd4e8c1 RK |
13280 | (define_insn "" |
13281 | [(set (pc) | |
13282 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13283 | [(match_operand 1 | |
b54cf83a | 13284 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13285 | (const_int 0)]) |
13286 | (return) | |
13287 | (pc)))] | |
13288 | "direct_return ()" | |
12a4e8c5 GK |
13289 | "* |
13290 | { | |
13291 | return output_cbranch (operands[0], NULL, 0, insn); | |
13292 | }" | |
b7ff3d82 | 13293 | [(set_attr "type" "branch") |
39a10a29 | 13294 | (set_attr "length" "4")]) |
1fd4e8c1 RK |
13295 | |
13296 | (define_insn "" | |
13297 | [(set (pc) | |
13298 | (if_then_else (match_operator 1 "branch_comparison_operator" | |
13299 | [(match_operand 2 | |
b54cf83a | 13300 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13301 | (const_int 0)]) |
13302 | (pc) | |
13303 | (label_ref (match_operand 0 "" ""))))] | |
13304 | "" | |
b19003d8 RK |
13305 | "* |
13306 | { | |
12a4e8c5 | 13307 | return output_cbranch (operands[1], \"%l0\", 1, insn); |
b19003d8 RK |
13308 | }" |
13309 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13310 | |
13311 | (define_insn "" | |
13312 | [(set (pc) | |
13313 | (if_then_else (match_operator 0 "branch_comparison_operator" | |
13314 | [(match_operand 1 | |
b54cf83a | 13315 | "cc_reg_operand" "y") |
1fd4e8c1 RK |
13316 | (const_int 0)]) |
13317 | (pc) | |
13318 | (return)))] | |
13319 | "direct_return ()" | |
12a4e8c5 GK |
13320 | "* |
13321 | { | |
13322 | return output_cbranch (operands[0], NULL, 1, insn); | |
13323 | }" | |
b7ff3d82 | 13324 | [(set_attr "type" "branch") |
39a10a29 GK |
13325 | (set_attr "length" "4")]) |
13326 | ||
13327 | ;; Logic on condition register values. | |
13328 | ||
13329 | ; This pattern matches things like | |
13330 | ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) | |
13331 | ; (eq:SI (reg:CCFP 68) (const_int 0))) | |
13332 | ; (const_int 1))) | |
13333 | ; which are generated by the branch logic. | |
b54cf83a | 13334 | ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB) |
39a10a29 | 13335 | |
423c1189 | 13336 | (define_insn "*cceq_ior_compare" |
b54cf83a | 13337 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
39a10a29 | 13338 | (compare:CCEQ (match_operator:SI 1 "boolean_operator" |
b54cf83a | 13339 | [(match_operator:SI 2 |
39a10a29 GK |
13340 | "branch_positive_comparison_operator" |
13341 | [(match_operand 3 | |
b54cf83a | 13342 | "cc_reg_operand" "y,y") |
39a10a29 | 13343 | (const_int 0)]) |
b54cf83a | 13344 | (match_operator:SI 4 |
39a10a29 GK |
13345 | "branch_positive_comparison_operator" |
13346 | [(match_operand 5 | |
b54cf83a | 13347 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13348 | (const_int 0)])]) |
13349 | (const_int 1)))] | |
24fab1d3 | 13350 | "" |
39a10a29 | 13351 | "cr%q1 %E0,%j2,%j4" |
b54cf83a | 13352 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
13353 | |
13354 | ; Why is the constant -1 here, but 1 in the previous pattern? | |
13355 | ; Because ~1 has all but the low bit set. | |
13356 | (define_insn "" | |
b54cf83a | 13357 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
39a10a29 | 13358 | (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" |
b54cf83a | 13359 | [(not:SI (match_operator:SI 2 |
39a10a29 GK |
13360 | "branch_positive_comparison_operator" |
13361 | [(match_operand 3 | |
b54cf83a | 13362 | "cc_reg_operand" "y,y") |
39a10a29 GK |
13363 | (const_int 0)])) |
13364 | (match_operator:SI 4 | |
13365 | "branch_positive_comparison_operator" | |
13366 | [(match_operand 5 | |
b54cf83a | 13367 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13368 | (const_int 0)])]) |
13369 | (const_int -1)))] | |
13370 | "" | |
13371 | "cr%q1 %E0,%j2,%j4" | |
b54cf83a | 13372 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 | 13373 | |
423c1189 | 13374 | (define_insn "*cceq_rev_compare" |
b54cf83a | 13375 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") |
6c873122 | 13376 | (compare:CCEQ (match_operator:SI 1 |
39a10a29 | 13377 | "branch_positive_comparison_operator" |
6c873122 | 13378 | [(match_operand 2 |
b54cf83a | 13379 | "cc_reg_operand" "0,y") |
39a10a29 GK |
13380 | (const_int 0)]) |
13381 | (const_int 0)))] | |
423c1189 | 13382 | "" |
251b3667 | 13383 | "{crnor %E0,%j1,%j1|crnot %E0,%j1}" |
b54cf83a | 13384 | [(set_attr "type" "cr_logical,delayed_cr")]) |
39a10a29 GK |
13385 | |
13386 | ;; If we are comparing the result of two comparisons, this can be done | |
13387 | ;; using creqv or crxor. | |
13388 | ||
13389 | (define_insn_and_split "" | |
13390 | [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") | |
13391 | (compare:CCEQ (match_operator 1 "branch_comparison_operator" | |
13392 | [(match_operand 2 "cc_reg_operand" "y") | |
13393 | (const_int 0)]) | |
13394 | (match_operator 3 "branch_comparison_operator" | |
13395 | [(match_operand 4 "cc_reg_operand" "y") | |
13396 | (const_int 0)])))] | |
13397 | "" | |
13398 | "#" | |
13399 | "" | |
13400 | [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) | |
13401 | (match_dup 5)))] | |
13402 | " | |
13403 | { | |
13404 | int positive_1, positive_2; | |
13405 | ||
364849ee DE |
13406 | positive_1 = branch_positive_comparison_operator (operands[1], |
13407 | GET_MODE (operands[1])); | |
13408 | positive_2 = branch_positive_comparison_operator (operands[3], | |
13409 | GET_MODE (operands[3])); | |
39a10a29 GK |
13410 | |
13411 | if (! positive_1) | |
1c563bed | 13412 | operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]), |
0f4c242b KH |
13413 | GET_CODE (operands[1])), |
13414 | SImode, | |
13415 | operands[2], const0_rtx); | |
39a10a29 | 13416 | else if (GET_MODE (operands[1]) != SImode) |
0f4c242b KH |
13417 | operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, |
13418 | operands[2], const0_rtx); | |
39a10a29 GK |
13419 | |
13420 | if (! positive_2) | |
1c563bed | 13421 | operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]), |
0f4c242b KH |
13422 | GET_CODE (operands[3])), |
13423 | SImode, | |
13424 | operands[4], const0_rtx); | |
39a10a29 | 13425 | else if (GET_MODE (operands[3]) != SImode) |
0f4c242b KH |
13426 | operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, |
13427 | operands[4], const0_rtx); | |
39a10a29 GK |
13428 | |
13429 | if (positive_1 == positive_2) | |
251b3667 DE |
13430 | { |
13431 | operands[1] = gen_rtx_NOT (SImode, operands[1]); | |
13432 | operands[5] = constm1_rtx; | |
13433 | } | |
13434 | else | |
13435 | { | |
13436 | operands[5] = const1_rtx; | |
13437 | } | |
39a10a29 | 13438 | }") |
1fd4e8c1 RK |
13439 | |
13440 | ;; Unconditional branch and return. | |
13441 | ||
13442 | (define_insn "jump" | |
13443 | [(set (pc) | |
13444 | (label_ref (match_operand 0 "" "")))] | |
13445 | "" | |
b7ff3d82 DE |
13446 | "b %l0" |
13447 | [(set_attr "type" "branch")]) | |
1fd4e8c1 RK |
13448 | |
13449 | (define_insn "return" | |
13450 | [(return)] | |
13451 | "direct_return ()" | |
324e52cc TG |
13452 | "{br|blr}" |
13453 | [(set_attr "type" "jmpreg")]) | |
1fd4e8c1 | 13454 | |
0ad91047 | 13455 | (define_expand "indirect_jump" |
4ae234b0 | 13456 | [(set (pc) (match_operand 0 "register_operand" ""))]) |
0ad91047 | 13457 | |
4ae234b0 GK |
13458 | (define_insn "*indirect_jump<mode>" |
13459 | [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))] | |
13460 | "" | |
b92b324d DE |
13461 | "@ |
13462 | bctr | |
13463 | {br|blr}" | |
324e52cc | 13464 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 RK |
13465 | |
13466 | ;; Table jump for switch statements: | |
13467 | (define_expand "tablejump" | |
e6ca2c17 DE |
13468 | [(use (match_operand 0 "" "")) |
13469 | (use (label_ref (match_operand 1 "" "")))] | |
13470 | "" | |
13471 | " | |
13472 | { | |
13473 | if (TARGET_32BIT) | |
13474 | emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); | |
13475 | else | |
13476 | emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); | |
13477 | DONE; | |
13478 | }") | |
13479 | ||
13480 | (define_expand "tablejumpsi" | |
1fd4e8c1 RK |
13481 | [(set (match_dup 3) |
13482 | (plus:SI (match_operand:SI 0 "" "") | |
13483 | (match_dup 2))) | |
13484 | (parallel [(set (pc) (match_dup 3)) | |
13485 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13486 | "TARGET_32BIT" |
1fd4e8c1 RK |
13487 | " |
13488 | { operands[0] = force_reg (SImode, operands[0]); | |
c5c76735 | 13489 | operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); |
1fd4e8c1 RK |
13490 | operands[3] = gen_reg_rtx (SImode); |
13491 | }") | |
13492 | ||
e6ca2c17 | 13493 | (define_expand "tablejumpdi" |
6ae08853 | 13494 | [(set (match_dup 4) |
9ebbca7d GK |
13495 | (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm"))) |
13496 | (set (match_dup 3) | |
13497 | (plus:DI (match_dup 4) | |
e6ca2c17 DE |
13498 | (match_dup 2))) |
13499 | (parallel [(set (pc) (match_dup 3)) | |
13500 | (use (label_ref (match_operand 1 "" "")))])] | |
0ad91047 | 13501 | "TARGET_64BIT" |
e6ca2c17 | 13502 | " |
9ebbca7d | 13503 | { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); |
e6ca2c17 | 13504 | operands[3] = gen_reg_rtx (DImode); |
9ebbca7d | 13505 | operands[4] = gen_reg_rtx (DImode); |
e6ca2c17 DE |
13506 | }") |
13507 | ||
1fd4e8c1 RK |
13508 | (define_insn "" |
13509 | [(set (pc) | |
4ae234b0 | 13510 | (match_operand:P 0 "register_operand" "c,*l")) |
1fd4e8c1 | 13511 | (use (label_ref (match_operand 1 "" "")))] |
4ae234b0 | 13512 | "" |
c859cda6 DJ |
13513 | "@ |
13514 | bctr | |
13515 | {br|blr}" | |
a6845123 | 13516 | [(set_attr "type" "jmpreg")]) |
1fd4e8c1 RK |
13517 | |
13518 | (define_insn "nop" | |
13519 | [(const_int 0)] | |
13520 | "" | |
ca7f5001 | 13521 | "{cror 0,0,0|nop}") |
1fd4e8c1 | 13522 | \f |
7e69e155 | 13523 | ;; Define the subtract-one-and-jump insns, starting with the template |
c225ba7b RK |
13524 | ;; so loop.c knows what to generate. |
13525 | ||
5527bf14 RH |
13526 | (define_expand "doloop_end" |
13527 | [(use (match_operand 0 "" "")) ; loop pseudo | |
13528 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
13529 | (use (match_operand 2 "" "")) ; max iterations | |
13530 | (use (match_operand 3 "" "")) ; loop level | |
13531 | (use (match_operand 4 "" ""))] ; label | |
0ad91047 DE |
13532 | "" |
13533 | " | |
13534 | { | |
5527bf14 RH |
13535 | /* Only use this on innermost loops. */ |
13536 | if (INTVAL (operands[3]) > 1) | |
13537 | FAIL; | |
683bdff7 | 13538 | if (TARGET_64BIT) |
5527bf14 RH |
13539 | { |
13540 | if (GET_MODE (operands[0]) != DImode) | |
13541 | FAIL; | |
13542 | emit_jump_insn (gen_ctrdi (operands[0], operands[4])); | |
13543 | } | |
0ad91047 | 13544 | else |
5527bf14 RH |
13545 | { |
13546 | if (GET_MODE (operands[0]) != SImode) | |
13547 | FAIL; | |
13548 | emit_jump_insn (gen_ctrsi (operands[0], operands[4])); | |
13549 | } | |
0ad91047 DE |
13550 | DONE; |
13551 | }") | |
13552 | ||
4ae234b0 | 13553 | (define_expand "ctr<mode>" |
3cb999d8 | 13554 | [(parallel [(set (pc) |
4ae234b0 | 13555 | (if_then_else (ne (match_operand:P 0 "register_operand" "") |
3cb999d8 DE |
13556 | (const_int 1)) |
13557 | (label_ref (match_operand 1 "" "")) | |
13558 | (pc))) | |
b6c9286a | 13559 | (set (match_dup 0) |
4ae234b0 | 13560 | (plus:P (match_dup 0) |
b6c9286a | 13561 | (const_int -1))) |
5f81043f | 13562 | (clobber (match_scratch:CC 2 "")) |
4ae234b0 GK |
13563 | (clobber (match_scratch:P 3 ""))])] |
13564 | "" | |
61c07d3c | 13565 | "") |
c225ba7b | 13566 | |
1fd4e8c1 RK |
13567 | ;; We need to be able to do this for any operand, including MEM, or we |
13568 | ;; will cause reload to blow up since we don't allow output reloads on | |
7e69e155 | 13569 | ;; JUMP_INSNs. |
0ad91047 | 13570 | ;; For the length attribute to be calculated correctly, the |
5f81043f RK |
13571 | ;; label MUST be operand 0. |
13572 | ||
4ae234b0 | 13573 | (define_insn "*ctr<mode>_internal1" |
0ad91047 | 13574 | [(set (pc) |
4ae234b0 | 13575 | (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
13576 | (const_int 1)) |
13577 | (label_ref (match_operand 0 "" "")) | |
13578 | (pc))) | |
4ae234b0 GK |
13579 | (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
13580 | (plus:P (match_dup 1) | |
0ad91047 | 13581 | (const_int -1))) |
43b68ce5 | 13582 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
4ae234b0 GK |
13583 | (clobber (match_scratch:P 4 "=X,X,&r,r"))] |
13584 | "" | |
0ad91047 DE |
13585 | "* |
13586 | { | |
13587 | if (which_alternative != 0) | |
13588 | return \"#\"; | |
856a6884 | 13589 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13590 | return \"{bdn|bdnz} %l0\"; |
13591 | else | |
f607bc57 | 13592 | return \"bdz $+8\;b %l0\"; |
0ad91047 DE |
13593 | }" |
13594 | [(set_attr "type" "branch") | |
5a195cb5 | 13595 | (set_attr "length" "*,12,16,16")]) |
0ad91047 | 13596 | |
4ae234b0 | 13597 | (define_insn "*ctr<mode>_internal2" |
0ad91047 | 13598 | [(set (pc) |
4ae234b0 | 13599 | (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
13600 | (const_int 1)) |
13601 | (pc) | |
13602 | (label_ref (match_operand 0 "" "")))) | |
4ae234b0 GK |
13603 | (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
13604 | (plus:P (match_dup 1) | |
0ad91047 | 13605 | (const_int -1))) |
43b68ce5 | 13606 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
4ae234b0 GK |
13607 | (clobber (match_scratch:P 4 "=X,X,&r,r"))] |
13608 | "" | |
5f81043f RK |
13609 | "* |
13610 | { | |
13611 | if (which_alternative != 0) | |
13612 | return \"#\"; | |
856a6884 | 13613 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
13614 | return \"bdz %l0\"; |
13615 | else | |
f607bc57 | 13616 | return \"{bdn|bdnz} $+8\;b %l0\"; |
5f81043f RK |
13617 | }" |
13618 | [(set_attr "type" "branch") | |
5a195cb5 | 13619 | (set_attr "length" "*,12,16,16")]) |
5f81043f | 13620 | |
0ad91047 DE |
13621 | ;; Similar but use EQ |
13622 | ||
4ae234b0 | 13623 | (define_insn "*ctr<mode>_internal5" |
5f81043f | 13624 | [(set (pc) |
4ae234b0 | 13625 | (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r") |
1fd4e8c1 | 13626 | (const_int 1)) |
a6845123 | 13627 | (label_ref (match_operand 0 "" "")) |
1fd4e8c1 | 13628 | (pc))) |
4ae234b0 GK |
13629 | (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
13630 | (plus:P (match_dup 1) | |
0ad91047 | 13631 | (const_int -1))) |
43b68ce5 | 13632 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
4ae234b0 GK |
13633 | (clobber (match_scratch:P 4 "=X,X,&r,r"))] |
13634 | "" | |
0ad91047 DE |
13635 | "* |
13636 | { | |
13637 | if (which_alternative != 0) | |
13638 | return \"#\"; | |
856a6884 | 13639 | else if (get_attr_length (insn) == 4) |
0ad91047 DE |
13640 | return \"bdz %l0\"; |
13641 | else | |
f607bc57 | 13642 | return \"{bdn|bdnz} $+8\;b %l0\"; |
0ad91047 DE |
13643 | }" |
13644 | [(set_attr "type" "branch") | |
5a195cb5 | 13645 | (set_attr "length" "*,12,16,16")]) |
0ad91047 | 13646 | |
4ae234b0 | 13647 | (define_insn "*ctr<mode>_internal6" |
0ad91047 | 13648 | [(set (pc) |
4ae234b0 | 13649 | (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r") |
0ad91047 DE |
13650 | (const_int 1)) |
13651 | (pc) | |
13652 | (label_ref (match_operand 0 "" "")))) | |
4ae234b0 GK |
13653 | (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l") |
13654 | (plus:P (match_dup 1) | |
0ad91047 | 13655 | (const_int -1))) |
43b68ce5 | 13656 | (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) |
4ae234b0 GK |
13657 | (clobber (match_scratch:P 4 "=X,X,&r,r"))] |
13658 | "" | |
5f81043f RK |
13659 | "* |
13660 | { | |
13661 | if (which_alternative != 0) | |
13662 | return \"#\"; | |
856a6884 | 13663 | else if (get_attr_length (insn) == 4) |
5f81043f RK |
13664 | return \"{bdn|bdnz} %l0\"; |
13665 | else | |
f607bc57 | 13666 | return \"bdz $+8\;b %l0\"; |
5f81043f RK |
13667 | }" |
13668 | [(set_attr "type" "branch") | |
5a195cb5 | 13669 | (set_attr "length" "*,12,16,16")]) |
5f81043f | 13670 | |
0ad91047 DE |
13671 | ;; Now the splitters if we could not allocate the CTR register |
13672 | ||
1fd4e8c1 RK |
13673 | (define_split |
13674 | [(set (pc) | |
13675 | (if_then_else (match_operator 2 "comparison_operator" | |
4ae234b0 | 13676 | [(match_operand:P 1 "gpc_reg_operand" "") |
0ad91047 | 13677 | (const_int 1)]) |
61c07d3c DE |
13678 | (match_operand 5 "" "") |
13679 | (match_operand 6 "" ""))) | |
4ae234b0 GK |
13680 | (set (match_operand:P 0 "gpc_reg_operand" "") |
13681 | (plus:P (match_dup 1) (const_int -1))) | |
0ad91047 | 13682 | (clobber (match_scratch:CC 3 "")) |
4ae234b0 GK |
13683 | (clobber (match_scratch:P 4 ""))] |
13684 | "reload_completed" | |
0ad91047 | 13685 | [(parallel [(set (match_dup 3) |
4ae234b0 | 13686 | (compare:CC (plus:P (match_dup 1) |
0ad91047 DE |
13687 | (const_int -1)) |
13688 | (const_int 0))) | |
13689 | (set (match_dup 0) | |
4ae234b0 | 13690 | (plus:P (match_dup 1) |
0ad91047 | 13691 | (const_int -1)))]) |
61c07d3c DE |
13692 | (set (pc) (if_then_else (match_dup 7) |
13693 | (match_dup 5) | |
13694 | (match_dup 6)))] | |
0ad91047 | 13695 | " |
0f4c242b KH |
13696 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
13697 | operands[3], const0_rtx); }") | |
0ad91047 DE |
13698 | |
13699 | (define_split | |
13700 | [(set (pc) | |
13701 | (if_then_else (match_operator 2 "comparison_operator" | |
4ae234b0 | 13702 | [(match_operand:P 1 "gpc_reg_operand" "") |
0ad91047 | 13703 | (const_int 1)]) |
61c07d3c DE |
13704 | (match_operand 5 "" "") |
13705 | (match_operand 6 "" ""))) | |
4ae234b0 GK |
13706 | (set (match_operand:P 0 "nonimmediate_operand" "") |
13707 | (plus:P (match_dup 1) (const_int -1))) | |
0ad91047 | 13708 | (clobber (match_scratch:CC 3 "")) |
4ae234b0 GK |
13709 | (clobber (match_scratch:P 4 ""))] |
13710 | "reload_completed && ! gpc_reg_operand (operands[0], SImode)" | |
0ad91047 | 13711 | [(parallel [(set (match_dup 3) |
4ae234b0 | 13712 | (compare:CC (plus:P (match_dup 1) |
0ad91047 DE |
13713 | (const_int -1)) |
13714 | (const_int 0))) | |
13715 | (set (match_dup 4) | |
4ae234b0 | 13716 | (plus:P (match_dup 1) |
0ad91047 DE |
13717 | (const_int -1)))]) |
13718 | (set (match_dup 0) | |
13719 | (match_dup 4)) | |
61c07d3c DE |
13720 | (set (pc) (if_then_else (match_dup 7) |
13721 | (match_dup 5) | |
13722 | (match_dup 6)))] | |
0ad91047 | 13723 | " |
0f4c242b KH |
13724 | { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, |
13725 | operands[3], const0_rtx); }") | |
e0cd0770 JC |
13726 | \f |
13727 | (define_insn "trap" | |
13728 | [(trap_if (const_int 1) (const_int 0))] | |
13729 | "" | |
13730 | "{t 31,0,0|trap}") | |
13731 | ||
13732 | (define_expand "conditional_trap" | |
13733 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
13734 | [(match_dup 2) (match_dup 3)]) | |
13735 | (match_operand 1 "const_int_operand" ""))] | |
13736 | "" | |
13737 | "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL; | |
13738 | operands[2] = rs6000_compare_op0; | |
13739 | operands[3] = rs6000_compare_op1;") | |
13740 | ||
13741 | (define_insn "" | |
13742 | [(trap_if (match_operator 0 "trap_comparison_operator" | |
4ae234b0 GK |
13743 | [(match_operand:GPR 1 "register_operand" "r") |
13744 | (match_operand:GPR 2 "reg_or_short_operand" "rI")]) | |
e0cd0770 JC |
13745 | (const_int 0))] |
13746 | "" | |
4ae234b0 | 13747 | "{t|t<wd>}%V0%I2 %1,%2") |
9ebbca7d GK |
13748 | \f |
13749 | ;; Insns related to generating the function prologue and epilogue. | |
13750 | ||
13751 | (define_expand "prologue" | |
13752 | [(use (const_int 0))] | |
13753 | "TARGET_SCHED_PROLOG" | |
13754 | " | |
13755 | { | |
13756 | rs6000_emit_prologue (); | |
13757 | DONE; | |
13758 | }") | |
13759 | ||
2c4a9cff DE |
13760 | (define_insn "*movesi_from_cr_one" |
13761 | [(match_parallel 0 "mfcr_operation" | |
13762 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
13763 | (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y") | |
13764 | (match_operand 3 "immediate_operand" "n")] | |
13765 | UNSPEC_MOVESI_FROM_CR))])] | |
13766 | "TARGET_MFCRF" | |
13767 | "* | |
13768 | { | |
13769 | int mask = 0; | |
13770 | int i; | |
13771 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
13772 | { | |
13773 | mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
13774 | operands[4] = GEN_INT (mask); | |
13775 | output_asm_insn (\"mfcr %1,%4\", operands); | |
13776 | } | |
13777 | return \"\"; | |
13778 | }" | |
13779 | [(set_attr "type" "mfcrf")]) | |
13780 | ||
9ebbca7d GK |
13781 | (define_insn "movesi_from_cr" |
13782 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
6ae08853 | 13783 | (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) |
615158e2 JJ |
13784 | (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] |
13785 | UNSPEC_MOVESI_FROM_CR))] | |
9ebbca7d | 13786 | "" |
309323c2 | 13787 | "mfcr %0" |
b54cf83a | 13788 | [(set_attr "type" "mfcr")]) |
9ebbca7d GK |
13789 | |
13790 | (define_insn "*stmw" | |
e033a023 DE |
13791 | [(match_parallel 0 "stmw_operation" |
13792 | [(set (match_operand:SI 1 "memory_operand" "=m") | |
13793 | (match_operand:SI 2 "gpc_reg_operand" "r"))])] | |
13794 | "TARGET_MULTIPLE" | |
13795 | "{stm|stmw} %2,%1") | |
6ae08853 | 13796 | |
4ae234b0 | 13797 | (define_insn "*save_fpregs_<mode>" |
85d346f1 | 13798 | [(match_parallel 0 "any_parallel_operand" |
4ae234b0 GK |
13799 | [(clobber (match_operand:P 1 "register_operand" "=l")) |
13800 | (use (match_operand:P 2 "call_operand" "s")) | |
e033a023 DE |
13801 | (set (match_operand:DF 3 "memory_operand" "=m") |
13802 | (match_operand:DF 4 "gpc_reg_operand" "f"))])] | |
4ae234b0 | 13803 | "" |
e033a023 DE |
13804 | "bl %z2" |
13805 | [(set_attr "type" "branch") | |
13806 | (set_attr "length" "4")]) | |
9ebbca7d GK |
13807 | |
13808 | ; These are to explain that changes to the stack pointer should | |
13809 | ; not be moved over stores to stack memory. | |
13810 | (define_insn "stack_tie" | |
13811 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
615158e2 | 13812 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] |
9ebbca7d GK |
13813 | "" |
13814 | "" | |
13815 | [(set_attr "length" "0")]) | |
13816 | ||
13817 | ||
13818 | (define_expand "epilogue" | |
13819 | [(use (const_int 0))] | |
13820 | "TARGET_SCHED_PROLOG" | |
13821 | " | |
13822 | { | |
13823 | rs6000_emit_epilogue (FALSE); | |
13824 | DONE; | |
13825 | }") | |
13826 | ||
13827 | ; On some processors, doing the mtcrf one CC register at a time is | |
13828 | ; faster (like on the 604e). On others, doing them all at once is | |
13829 | ; faster; for instance, on the 601 and 750. | |
13830 | ||
13831 | (define_expand "movsi_to_cr_one" | |
35aba846 DE |
13832 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
13833 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
615158e2 | 13834 | (match_dup 2)] UNSPEC_MOVESI_TO_CR))] |
35aba846 DE |
13835 | "" |
13836 | "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") | |
9ebbca7d GK |
13837 | |
13838 | (define_insn "*movsi_to_cr" | |
35aba846 DE |
13839 | [(match_parallel 0 "mtcrf_operation" |
13840 | [(set (match_operand:CC 1 "cc_reg_operand" "=y") | |
13841 | (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") | |
13842 | (match_operand 3 "immediate_operand" "n")] | |
615158e2 | 13843 | UNSPEC_MOVESI_TO_CR))])] |
9ebbca7d | 13844 | "" |
e35b9579 GK |
13845 | "* |
13846 | { | |
13847 | int mask = 0; | |
13848 | int i; | |
13849 | for (i = 0; i < XVECLEN (operands[0], 0); i++) | |
13850 | mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); | |
13851 | operands[4] = GEN_INT (mask); | |
13852 | return \"mtcrf %4,%2\"; | |
309323c2 | 13853 | }" |
b54cf83a | 13854 | [(set_attr "type" "mtcr")]) |
9ebbca7d | 13855 | |
b54cf83a | 13856 | (define_insn "*mtcrfsi" |
309323c2 DE |
13857 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") |
13858 | (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") | |
615158e2 JJ |
13859 | (match_operand 2 "immediate_operand" "n")] |
13860 | UNSPEC_MOVESI_TO_CR))] | |
6ae08853 | 13861 | "GET_CODE (operands[0]) == REG |
309323c2 DE |
13862 | && CR_REGNO_P (REGNO (operands[0])) |
13863 | && GET_CODE (operands[2]) == CONST_INT | |
13864 | && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" | |
13865 | "mtcrf %R0,%1" | |
b54cf83a | 13866 | [(set_attr "type" "mtcr")]) |
9ebbca7d GK |
13867 | |
13868 | ; The load-multiple instructions have similar properties. | |
13869 | ; Note that "load_multiple" is a name known to the machine-independent | |
13870 | ; code that actually corresponds to the powerpc load-string. | |
13871 | ||
13872 | (define_insn "*lmw" | |
35aba846 DE |
13873 | [(match_parallel 0 "lmw_operation" |
13874 | [(set (match_operand:SI 1 "gpc_reg_operand" "=r") | |
13875 | (match_operand:SI 2 "memory_operand" "m"))])] | |
13876 | "TARGET_MULTIPLE" | |
13877 | "{lm|lmw} %1,%2") | |
6ae08853 | 13878 | |
4ae234b0 | 13879 | (define_insn "*return_internal_<mode>" |
e35b9579 | 13880 | [(return) |
4ae234b0 GK |
13881 | (use (match_operand:P 0 "register_operand" "lc"))] |
13882 | "" | |
cccf3bdc | 13883 | "b%T0" |
9ebbca7d GK |
13884 | [(set_attr "type" "jmpreg")]) |
13885 | ||
13886 | ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall | |
85d346f1 | 13887 | ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible... |
9ebbca7d | 13888 | |
4ae234b0 | 13889 | (define_insn "*return_and_restore_fpregs_<mode>" |
85d346f1 | 13890 | [(match_parallel 0 "any_parallel_operand" |
e35b9579 | 13891 | [(return) |
4ae234b0 GK |
13892 | (use (match_operand:P 1 "register_operand" "l")) |
13893 | (use (match_operand:P 2 "call_operand" "s")) | |
9ebbca7d GK |
13894 | (set (match_operand:DF 3 "gpc_reg_operand" "=f") |
13895 | (match_operand:DF 4 "memory_operand" "m"))])] | |
4ae234b0 | 13896 | "" |
9ebbca7d GK |
13897 | "b %z2") |
13898 | ||
83720594 RH |
13899 | ; This is used in compiling the unwind routines. |
13900 | (define_expand "eh_return" | |
34dc173c | 13901 | [(use (match_operand 0 "general_operand" ""))] |
9ebbca7d GK |
13902 | "" |
13903 | " | |
13904 | { | |
83720594 | 13905 | if (TARGET_32BIT) |
34dc173c | 13906 | emit_insn (gen_eh_set_lr_si (operands[0])); |
9ebbca7d | 13907 | else |
34dc173c | 13908 | emit_insn (gen_eh_set_lr_di (operands[0])); |
9ebbca7d GK |
13909 | DONE; |
13910 | }") | |
13911 | ||
83720594 | 13912 | ; We can't expand this before we know where the link register is stored. |
4ae234b0 GK |
13913 | (define_insn "eh_set_lr_<mode>" |
13914 | [(unspec_volatile [(match_operand:P 0 "register_operand" "r")] | |
615158e2 | 13915 | UNSPECV_EH_RR) |
4ae234b0 GK |
13916 | (clobber (match_scratch:P 1 "=&b"))] |
13917 | "" | |
83720594 | 13918 | "#") |
9ebbca7d GK |
13919 | |
13920 | (define_split | |
615158e2 | 13921 | [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR) |
83720594 RH |
13922 | (clobber (match_scratch 1 ""))] |
13923 | "reload_completed" | |
13924 | [(const_int 0)] | |
9ebbca7d GK |
13925 | " |
13926 | { | |
d1d0c603 | 13927 | rs6000_emit_eh_reg_restore (operands[0], operands[1]); |
83720594 RH |
13928 | DONE; |
13929 | }") | |
0ac081f6 | 13930 | |
01a2ccd0 DE |
13931 | (define_insn "prefetch" |
13932 | [(prefetch (match_operand:V4SI 0 "address_operand" "p") | |
6041bf2f DE |
13933 | (match_operand:SI 1 "const_int_operand" "n") |
13934 | (match_operand:SI 2 "const_int_operand" "n"))] | |
01a2ccd0 | 13935 | "TARGET_POWERPC" |
6041bf2f DE |
13936 | "* |
13937 | { | |
01a2ccd0 DE |
13938 | if (GET_CODE (operands[0]) == REG) |
13939 | return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\"; | |
13940 | return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; | |
6041bf2f DE |
13941 | }" |
13942 | [(set_attr "type" "load")]) | |
915167f5 | 13943 | \f |
a3170dc6 | 13944 | |
f565b0a1 | 13945 | (include "sync.md") |
10ed84db | 13946 | (include "altivec.md") |
a3170dc6 | 13947 | (include "spe.md") |