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[thirdparty/gcc.git] / gcc / config / rs6000 / rs6000.opt

; Options for the rs6000 port of the compiler
;
; Copyright (C) 2005-2023 Free Software Foundation, Inc.
; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
;
; This file is part of GCC.
;
; GCC is free software; you can redistribute it and/or modify it under
; the terms of the GNU General Public License as published by the Free
; Software Foundation; either version 3, or (at your option) any later
; version.
;
; GCC is distributed in the hope that it will be useful, but WITHOUT
; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
; License for more details.
;
; You should have received a copy of the GNU General Public License
; along with GCC; see the file COPYING3.  If not see
; <http://www.gnu.org/licenses/>.

HeaderInclude
config/rs6000/rs6000-opts.h

;; ISA flag bits (on/off)
Variable
HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT

TargetSave
HOST_WIDE_INT x_rs6000_isa_flags

;; Miscellaneous flag bits that were set explicitly by the user
Variable
HOST_WIDE_INT rs6000_isa_flags_explicit

TargetSave
HOST_WIDE_INT x_rs6000_isa_flags_explicit

;; Current processor
TargetVariable
enum processor_type rs6000_cpu = PROCESSOR_PPC603

;; Current tuning
TargetVariable
enum processor_type rs6000_tune = PROCESSOR_PPC603

;; Always emit branch hint bits.
TargetVariable
unsigned char rs6000_always_hint

;; Schedule instructions for group formation.
TargetVariable
unsigned char rs6000_sched_groups

;; Align branch targets.
TargetVariable
unsigned char rs6000_align_branch_targets

;; Support for -msched-costly-dep option.
TargetVariable
enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly

;; Support for -minsert-sched-nops option.
TargetVariable
enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none

;; Non-zero to allow overriding loop alignment.
TargetVariable
unsigned char can_override_loop_align

;; Which small data model to use (for System V targets only)
TargetVariable
enum rs6000_sdata_type rs6000_sdata = SDATA_DATA

;; Bit size of immediate TLS offsets and string from which it is decoded.
TargetVariable
int rs6000_tls_size = 32

;; ABI enumeration available for subtarget to use.
TargetVariable
enum rs6000_abi rs6000_current_abi = ABI_NONE

;; Type of traceback to use.
TargetVariable
enum rs6000_traceback_type rs6000_traceback = traceback_default

;; Control alignment for fields within structures.
TargetVariable
unsigned char rs6000_alignment_flags

;; Code model for 64-bit linux.
TargetVariable
enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL

;; What type of reciprocal estimation instructions to generate
TargetVariable
unsigned int rs6000_recip_control

;; Debug flags
TargetVariable
unsigned int rs6000_debug

;; Whether to enable the -mfloat128 stuff without necessarily enabling the
;; __float128 keyword.
TargetSave
unsigned char x_TARGET_FLOAT128_TYPE

Variable
unsigned char TARGET_FLOAT128_TYPE

;; This option existed in the past, but now is always on.
mpowerpc
Target RejectNegative Undocumented Ignore

mpowerpc64
Target Mask(POWERPC64) Var(rs6000_isa_flags)
Use PowerPC-64 instruction set.

mpowerpc-gpopt
Target Mask(PPC_GPOPT) Var(rs6000_isa_flags)
Use PowerPC General Purpose group optional instructions.

mpowerpc-gfxopt
Target Mask(PPC_GFXOPT) Var(rs6000_isa_flags)
Use PowerPC Graphics group optional instructions.

mmfcrf
Target Mask(MFCRF) Var(rs6000_isa_flags)
Use PowerPC V2.01 single field mfcr instruction.

mpopcntb
Target Mask(POPCNTB) Var(rs6000_isa_flags)
Use PowerPC V2.02 popcntb instruction.

mfprnd
Target Mask(FPRND) Var(rs6000_isa_flags)
Use PowerPC V2.02 floating point rounding instructions.

mcmpb
Target Mask(CMPB) Var(rs6000_isa_flags)
Use PowerPC V2.05 compare bytes instruction.

;; This option existed in the past, but now is always off.
mno-mfpgpr
Target RejectNegative Undocumented Ignore

mmfpgpr
Target RejectNegative Undocumented WarnRemoved

maltivec
Target Mask(ALTIVEC) Var(rs6000_isa_flags)
Use AltiVec instructions.

mhard-dfp
Target Mask(DFP) Var(rs6000_isa_flags)
Use decimal floating point instructions.

mmulhw
Target Mask(MULHW) Var(rs6000_isa_flags)
Use 4xx half-word multiply instructions.

mdlmzb
Target Mask(DLMZB) Var(rs6000_isa_flags)
Use 4xx string-search dlmzb instruction.

mmultiple
Target Mask(MULTIPLE) Var(rs6000_isa_flags)
Generate load/store multiple instructions.

;; This option existed in the past, but now is always off.
mno-string
Target RejectNegative Undocumented Ignore

mstring
Target RejectNegative Undocumented WarnRemoved

msoft-float
Target RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags)
Do not use hardware floating point.

mhard-float
Target RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags)
Use hardware floating point.

mpopcntd
Target Mask(POPCNTD) Var(rs6000_isa_flags)
Use PowerPC V2.06 popcntd instruction.

mfriz
Target Var(TARGET_FRIZ) Init(-1) Save
Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions.

mveclibabi=
Target RejectNegative Joined Var(rs6000_veclibabi_name)
Vector library ABI to use.

mvsx
Target Mask(VSX) Var(rs6000_isa_flags)
Use vector/scalar (VSX) instructions.

mvsx-align-128
Target Undocumented Var(TARGET_VSX_ALIGN_128) Save
; If -mvsx, set alignment to 128 bits instead of 32/64

mallow-movmisalign
Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save
; Allow the movmisalign in DF/DI vectors

mefficient-unaligned-vsx
Target Undocumented Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags)
; Consider unaligned VSX vector and fp accesses to be efficient

msched-groups
Target Undocumented Var(TARGET_SCHED_GROUPS) Init(-1) Save
; Explicitly set rs6000_sched_groups

malways-hint
Target Undocumented Var(TARGET_ALWAYS_HINT) Init(-1) Save
; Explicitly set rs6000_always_hint

malign-branch-targets
Target Undocumented Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save
; Explicitly set rs6000_align_branch_targets

mno-update
Target RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags)
Do not generate load/store with update instructions.

mupdate
Target RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags)
Generate load/store with update instructions.

msingle-pic-base
Target Var(TARGET_SINGLE_PIC_BASE) Init(0)
Do not load the PIC register in function prologues.

mavoid-indexed-addresses
Target Var(TARGET_AVOID_XFORM) Init(-1) Save
Avoid generation of indexed load/store instructions when possible.

msched-epilog
Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save

msched-prolog
Target Var(TARGET_SCHED_PROLOG) Save
Schedule the start and end of the procedure.

maix-struct-return
Target RejectNegative Var(aix_struct_return) Save
Return all structures in memory (AIX default).

msvr4-struct-return
Target RejectNegative Var(aix_struct_return,0) Save
Return small structures in registers (SVR4 default).

mxl-compat
Target Var(TARGET_XL_COMPAT) Save
Conform more closely to IBM XLC semantics.

mrecip
Target
Generate software reciprocal divide and square root for better throughput.

mrecip=
Target RejectNegative Joined Var(rs6000_recip_name)
Generate software reciprocal divide and square root for better throughput.

mrecip-precision
Target Mask(RECIP_PRECISION) Var(rs6000_isa_flags)
Assume that the reciprocal estimate instructions provide more accuracy.

mno-fp-in-toc
Target RejectNegative Var(TARGET_NO_FP_IN_TOC) Save
Do not place floating point constants in TOC.

mfp-in-toc
Target RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save
Place floating point constants in TOC.

mno-sum-in-toc
Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save
Do not place symbol+offset constants in TOC.

msum-in-toc
Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save
Place symbol+offset constants in TOC.

;  Output only one TOC entry per module.  Normally linking fails if
;   there are more than 16K unique variables/constants in an executable.  With
;   this option, linking fails only if there are more than 16K modules, or
;   if there are more than 16K unique variables/constant in a single module.
;
;   This is at the cost of having 2 extra loads and one extra store per
;   function, and one less allocable register.
mminimal-toc
Target Mask(MINIMAL_TOC) Var(rs6000_isa_flags)
Use only one TOC entry per procedure.

mfull-toc
Target
Put everything in the regular TOC.

mvrsave
Target Var(TARGET_ALTIVEC_VRSAVE) Save
Generate VRSAVE instructions when generating AltiVec code.

mvrsave=no
Target RejectNegative Alias(mvrsave) NegativeAlias Warn(%<-mvrsave=no%> is deprecated; use %<-mno-vrsave%> instead)
Deprecated option.  Use -mno-vrsave instead.

mvrsave=yes
Target RejectNegative Alias(mvrsave) Warn(%<-mvrsave=yes%> is deprecated; use %<-mvrsave%> instead)
Deprecated option.  Use -mvrsave instead.

mblock-move-inline-limit=
Target Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save
Max number of bytes to move inline.

mblock-ops-unaligned-vsx
Target Mask(BLOCK_OPS_UNALIGNED_VSX) Var(rs6000_isa_flags)
Generate unaligned VSX load/store for inline expansion of memcpy/memmove.

mblock-ops-vector-pair
Target Undocumented Mask(BLOCK_OPS_VECTOR_PAIR) Var(rs6000_isa_flags)
Generate unaligned VSX vector pair load/store for inline expansion of memcpy/memmove.

mblock-compare-inline-limit=
Target Var(rs6000_block_compare_inline_limit) Init(63) RejectNegative Joined UInteger Save
Max number of bytes to compare without loops.

mblock-compare-inline-loop-limit=
Target Var(rs6000_block_compare_inline_loop_limit) Init(-1) RejectNegative Joined UInteger Save
Max number of bytes to compare with loops.

mstring-compare-inline-limit=
Target Var(rs6000_string_compare_inline_limit) Init(64) RejectNegative Joined UInteger Save
Max number of bytes to compare.

misel
Target Mask(ISEL) Var(rs6000_isa_flags)
Generate isel instructions.

mdebug=
Target RejectNegative Joined
-mdebug=	Enable debug output.

; Altivec ABI
mabi=altivec
Target RejectNegative Var(rs6000_altivec_abi) Save
Use the AltiVec ABI extensions.

mabi=no-altivec
Target RejectNegative Var(rs6000_altivec_abi, 0)
Do not use the AltiVec ABI extensions.

; AIX Extended vector ABI
mabi=vec-extabi
Target RejectNegative Var(rs6000_aix_extabi, 1) Save
Use the AIX Vector Extended ABI.

mabi=vec-default
Target RejectNegative Var(rs6000_aix_extabi, 0)
Do not use the AIX Vector Extended ABI.

; PPC64 Linux ELF ABI
mabi=elfv1
Target RejectNegative Var(rs6000_elf_abi, 1) Save
Use the ELFv1 ABI.

mabi=elfv2
Target RejectNegative Var(rs6000_elf_abi, 2)
Use the ELFv2 ABI.

; These are here for testing during development only, do not document
; in the manual please.

; If we want Darwin's struct-by-value-in-regs ABI.
mabi=d64
Target RejectNegative Undocumented Warn(using darwin64 ABI) Var(rs6000_darwin64_abi) Save

mabi=d32
Target RejectNegative Undocumented Warn(using old darwin ABI) Var(rs6000_darwin64_abi, 0)

mabi=ieeelongdouble
Target RejectNegative Var(rs6000_ieeequad) Save

mabi=ibmlongdouble
Target RejectNegative Var(rs6000_ieeequad, 0)

mcpu=
Target RejectNegative Joined Var(rs6000_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
-mcpu=	Use features of and schedule code for given CPU.

mtune=
Target RejectNegative Joined Var(rs6000_tune_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
-mtune=	Schedule code for given CPU.

mtraceback=
Target RejectNegative Joined Enum(rs6000_traceback_type) Var(rs6000_traceback)
-mtraceback=[full,part,no]	Select type of traceback table.

Enum
Name(rs6000_traceback_type) Type(enum rs6000_traceback_type)

EnumValue
Enum(rs6000_traceback_type) String(full) Value(traceback_full)

EnumValue
Enum(rs6000_traceback_type) String(part) Value(traceback_part)

EnumValue
Enum(rs6000_traceback_type) String(no) Value(traceback_none)

mlongcall
Target Var(rs6000_default_long_calls) Save
Avoid all range limits on call instructions.

; This option existed in the past, but now is always on.
mgen-cell-microcode
Target RejectNegative Undocumented Ignore

mwarn-altivec-long
Target Var(rs6000_warn_altivec_long) Init(1) Save
Warn about deprecated 'vector long ...' AltiVec type usage.

mlong-double-
Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save
Use -mlong-double-64 for 64-bit IEEE floating point format.  Use
-mlong-double-128 for 128-bit floating point format (either IEEE or IBM).

; This option existed in the past, but now is always on.
mlra
Target RejectNegative Undocumented Ignore

msched-costly-dep=
Target RejectNegative Joined Var(rs6000_sched_costly_dep_str)
Determine which dependences between insns are considered costly.

minsert-sched-nops=
Target RejectNegative Joined Var(rs6000_sched_insert_nops_str)
Specify which post scheduling nop insertion scheme to apply.

malign-
Target RejectNegative Joined Enum(rs6000_alignment_flags) Var(rs6000_alignment_flags)
Specify alignment of structure fields default/natural.

Enum
Name(rs6000_alignment_flags) Type(unsigned char)
Valid arguments to -malign-:

EnumValue
Enum(rs6000_alignment_flags) String(power) Value(MASK_ALIGN_POWER)

EnumValue
Enum(rs6000_alignment_flags) String(natural) Value(MASK_ALIGN_NATURAL)

mprioritize-restricted-insns=
Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save
Specify scheduling priority for dispatch slot restricted insns.

mpointers-to-nested-functions
Target Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save
Use r11 to hold the static link in calls to functions via pointers.

msave-toc-indirect
Target Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags)
Save the TOC in the prologue for indirect calls rather than inline.

; This option existed in the past, but now is always the same as -mvsx.
mvsx-timode
Target RejectNegative Undocumented Ignore

mpower8-fusion
Target Mask(P8_FUSION) Var(rs6000_isa_flags)
Fuse certain integer operations together for better performance on power8.

mpower8-fusion-sign
Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags)
Allow sign extension in fusion operations.

mpower8-vector
Target Mask(P8_VECTOR) Var(rs6000_isa_flags)
Use vector and scalar instructions added in ISA 2.07.

mpower10-fusion
Target Undocumented Mask(P10_FUSION) Var(rs6000_isa_flags)
Fuse certain integer operations together for better performance on power10.

mcrypto
Target Mask(CRYPTO) Var(rs6000_isa_flags)
Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions.

mdirect-move
Target Undocumented Mask(DIRECT_MOVE) Var(rs6000_isa_flags) WarnRemoved

mhtm
Target Mask(HTM) Var(rs6000_isa_flags)
Use ISA 2.07 transactional memory (HTM) instructions.

mquad-memory
Target Mask(QUAD_MEMORY) Var(rs6000_isa_flags)
Generate the quad word memory instructions (lq/stq).

mquad-memory-atomic
Target Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags)
Generate the quad word memory atomic instructions (lqarx/stqcx).

mcompat-align-parm
Target Var(rs6000_compat_align_parm) Init(0) Save
Generate aggregate parameter passing code with at most 64-bit alignment.

moptimize-swaps
Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save
Analyze and remove doubleword swaps from VSX computations.

munroll-only-small-loops
Target Undocumented Var(unroll_only_small_loops) Init(0) Save
; Use conservative small loop unrolling.

mpower9-misc
Target Undocumented Mask(P9_MISC) Var(rs6000_isa_flags)
Use certain scalar instructions added in ISA 3.0.

mpower9-vector
Target Undocumented Mask(P9_VECTOR) Var(rs6000_isa_flags)
Use vector instructions added in ISA 3.0.

mpower9-minmax
Target Undocumented Mask(P9_MINMAX) Var(rs6000_isa_flags)
Use the new min/max instructions defined in ISA 3.0.

mmodulo
Target Undocumented Mask(MODULO) Var(rs6000_isa_flags)
Generate the integer modulo instructions.

mfloat128
Target Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags)
Enable IEEE 128-bit floating point via the __float128 keyword.

mfloat128-hardware
Target Mask(FLOAT128_HW) Var(rs6000_isa_flags)
Enable using IEEE 128-bit floating point instructions.

mfloat128-convert
Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags)
Enable default conversions between __float128 & long double.

mstack-protector-guard=
Target RejectNegative Joined Enum(stack_protector_guard) Var(rs6000_stack_protector_guard) Init(SSP_TLS)
Use given stack-protector guard.

Enum
Name(stack_protector_guard) Type(enum stack_protector_guard)
Valid arguments to -mstack-protector-guard=:

EnumValue
Enum(stack_protector_guard) String(tls) Value(SSP_TLS)

EnumValue
Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)

mstack-protector-guard-reg=
Target RejectNegative Joined Var(rs6000_stack_protector_guard_reg_str)
Use the given base register for addressing the stack-protector guard.

TargetVariable
int rs6000_stack_protector_guard_reg = 0

mstack-protector-guard-offset=
Target RejectNegative Joined Integer Var(rs6000_stack_protector_guard_offset_str)
Use the given offset for addressing the stack-protector guard.

TargetVariable
long rs6000_stack_protector_guard_offset = 0

;; -mno-speculate-indirect-jumps adds deliberate misprediction to indirect
;; branches via the CTR.
mspeculate-indirect-jumps
Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save

mpower10
Target Undocumented Mask(POWER10) Var(rs6000_isa_flags) WarnRemoved

mprefixed
Target Mask(PREFIXED) Var(rs6000_isa_flags)
Generate (do not generate) prefixed memory instructions.

mpcrel
Target Mask(PCREL) Var(rs6000_isa_flags)
Generate (do not generate) pc-relative memory addressing.

mpcrel-opt
Target Undocumented Mask(PCREL_OPT) Var(rs6000_isa_flags)
Generate (do not generate) pc-relative memory optimizations for externals.

mmma
Target Mask(MMA) Var(rs6000_isa_flags)
Generate (do not generate) MMA instructions.

mrelative-jumptables
Target Undocumented Var(rs6000_relative_jumptables) Init(1) Save

mrop-protect
Target Var(rs6000_rop_protect) Init(0)
Enable instructions that guard against return-oriented programming attacks.

mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.

msplat-word-constant
Target Var(TARGET_SPLAT_WORD_CONSTANT) Init(1) Save
Generate (do not generate) code that uses the XXSPLTIW instruction.

msplat-float-constant
Target Var(TARGET_SPLAT_FLOAT_CONSTANT) Init(1) Save
Generate (do not generate) code that uses the XXSPLTIDP instruction.

mieee128-constant
Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save
Generate (do not generate) code that uses the LXVKQ instruction.

; Documented parameters

-param=rs6000-vect-unroll-limit=
Target Joined UInteger Var(rs6000_vect_unroll_limit) Init(4) IntegerRange(1, 64) Param
Used to limit unroll factor which indicates how much the autovectorizer may
unroll a loop.  The default value is 4.

; Undocumented parameters
-param=rs6000-density-pct-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param
When costing for loop vectorization, we probably need to penalize the loop body
cost if the existing cost model may not adequately reflect delays from
unavailable vector resources.  We collect the cost for vectorized statements
and non-vectorized statements separately, check the proportion of vec_cost to
total cost of vec_cost and non vec_cost, and penalize only if the proportion
exceeds the threshold specified by this parameter.  The default value is 85.

-param=rs6000-density-size-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_size_threshold) Init(70) IntegerRange(0, 1000) Param
Like parameter rs6000-density-pct-threshold, we also check the total sum of
vec_cost and non vec_cost, and penalize only if the sum exceeds the threshold
specified by this parameter.  The default value is 70.

-param=rs6000-density-penalty=
Target Undocumented Joined UInteger Var(rs6000_density_penalty) Init(10) IntegerRange(0, 1000) Param
When both heuristics with rs6000-density-pct-threshold and
rs6000-density-size-threshold are satisfied, we decide to penalize the loop
body cost by the value which is specified by this parameter.  The default
value is 10.

-param=rs6000-density-load-pct-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_load_pct_threshold) Init(45) IntegerRange(0, 100) Param
When costing for loop vectorization, we probably need to penalize the loop body
cost by accounting for excess strided or elementwise loads.  We collect the
numbers for general statements and load statements according to the information
for statements to be vectorized, check the proportion of load statements, and
penalize only if the proportion exceeds the threshold specified by this
parameter.  The default value is 45.

-param=rs6000-density-load-num-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_load_num_threshold) Init(20) IntegerRange(0, 1000) Param
Like parameter rs6000-density-load-pct-threshold, we also check if the total
number of load statements exceeds the threshold specified by this parameter,
and penalize only if it's satisfied.  The default value is 20.

-param=rs6000-vect-unroll-issue=
Target Undocumented Joined UInteger Var(rs6000_vect_unroll_issue) Init(4) IntegerRange(1, 128) Param
Indicate how many non memory access vector instructions can be issued per
cycle, it's used in unroll factor determination for autovectorizer.  The
default value is 4.

-param=rs6000-vect-unroll-reduc-threshold=
Target Undocumented Joined UInteger Var(rs6000_vect_unroll_reduc_threshold) Init(1) Param
When reduction factor computed for a loop exceeds the threshold specified by
this parameter, prefer to unroll this loop.  The default value is 1.