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Commit | Line | Data |
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78f5898b AH |
1 | ; Options for the rs6000 port of the compiler |
2 | ; | |
688e4919 MM |
3 | ; Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010 Free Software |
4 | ; Foundation, Inc. | |
78f5898b AH |
5 | ; Contributed by Aldy Hernandez <aldy@quesejoda.com>. |
6 | ; | |
7 | ; This file is part of GCC. | |
8 | ; | |
9 | ; GCC is free software; you can redistribute it and/or modify it under | |
10 | ; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | ; Software Foundation; either version 3, or (at your option) any later |
78f5898b AH |
12 | ; version. |
13 | ; | |
14 | ; GCC is distributed in the hope that it will be useful, but WITHOUT | |
15 | ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
16 | ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
17 | ; License for more details. | |
18 | ; | |
19 | ; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ; along with GCC; see the file COPYING3. If not see |
21 | ; <http://www.gnu.org/licenses/>. | |
78f5898b AH |
22 | |
23 | mpower | |
24 | Target Report RejectNegative Mask(POWER) | |
25 | Use POWER instruction set | |
26 | ||
27 | mno-power | |
28 | Target Report RejectNegative | |
29 | Do not use POWER instruction set | |
30 | ||
31 | mpower2 | |
32 | Target Report Mask(POWER2) | |
33 | Use POWER2 instruction set | |
34 | ||
35 | mpowerpc | |
36 | Target Report RejectNegative Mask(POWERPC) | |
37 | Use PowerPC instruction set | |
38 | ||
39 | mno-powerpc | |
40 | Target Report RejectNegative | |
41 | Do not use PowerPC instruction set | |
42 | ||
43 | mpowerpc64 | |
44 | Target Report Mask(POWERPC64) | |
45 | Use PowerPC-64 instruction set | |
46 | ||
432218ba DE |
47 | mpowerpc-gpopt |
48 | Target Report Mask(PPC_GPOPT) | |
49 | Use PowerPC General Purpose group optional instructions | |
50 | ||
51 | mpowerpc-gfxopt | |
52 | Target Report Mask(PPC_GFXOPT) | |
53 | Use PowerPC Graphics group optional instructions | |
54 | ||
55 | mmfcrf | |
56 | Target Report Mask(MFCRF) | |
9719f3b7 | 57 | Use PowerPC V2.01 single field mfcr instruction |
432218ba DE |
58 | |
59 | mpopcntb | |
60 | Target Report Mask(POPCNTB) | |
9719f3b7 DE |
61 | Use PowerPC V2.02 popcntb instruction |
62 | ||
63 | mfprnd | |
64 | Target Report Mask(FPRND) | |
65 | Use PowerPC V2.02 floating point rounding instructions | |
432218ba | 66 | |
b639c3c2 JJ |
67 | mcmpb |
68 | Target Report Mask(CMPB) | |
69 | Use PowerPC V2.05 compare bytes instruction | |
70 | ||
44cd321e PS |
71 | mmfpgpr |
72 | Target Report Mask(MFPGPR) | |
73 | Use extended PowerPC V2.05 move floating point to/from GPR instructions | |
74 | ||
78f5898b AH |
75 | maltivec |
76 | Target Report Mask(ALTIVEC) | |
77 | Use AltiVec instructions | |
78 | ||
47d94c1a | 79 | mhard-dfp |
b639c3c2 JJ |
80 | Target Report Mask(DFP) |
81 | Use decimal floating point instructions | |
82 | ||
131aeb82 JM |
83 | mmulhw |
84 | Target Report Mask(MULHW) | |
85 | Use 4xx half-word multiply instructions | |
86 | ||
716019c0 JM |
87 | mdlmzb |
88 | Target Report Mask(DLMZB) | |
89 | Use 4xx string-search dlmzb instruction | |
90 | ||
432218ba DE |
91 | mmultiple |
92 | Target Report Mask(MULTIPLE) | |
93 | Generate load/store multiple instructions | |
94 | ||
95 | mstring | |
96 | Target Report Mask(STRING) | |
97 | Generate string instructions for block moves | |
98 | ||
78f5898b AH |
99 | mnew-mnemonics |
100 | Target Report RejectNegative Mask(NEW_MNEMONICS) | |
101 | Use new mnemonics for PowerPC architecture | |
102 | ||
103 | mold-mnemonics | |
104 | Target Report RejectNegative InverseMask(NEW_MNEMONICS) | |
105 | Use old mnemonics for PowerPC architecture | |
106 | ||
78f5898b AH |
107 | msoft-float |
108 | Target Report RejectNegative Mask(SOFT_FLOAT) | |
109 | Do not use hardware floating point | |
110 | ||
111 | mhard-float | |
112 | Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) | |
113 | Use hardware floating point | |
114 | ||
cacf1ca8 MM |
115 | mpopcntd |
116 | Target Report Mask(POPCNTD) | |
117 | Use PowerPC V2.06 popcntd instruction | |
118 | ||
688e4919 MM |
119 | mfriz |
120 | Target Report Var(TARGET_FRIZ) Init(-1) | |
121 | Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions | |
122 | ||
b36cf9d2 MM |
123 | mveclibabi= |
124 | Target RejectNegative Joined Var(rs6000_veclibabi_name) | |
125 | Vector library ABI to use | |
8bcc0304 | 126 | |
cacf1ca8 MM |
127 | mvsx |
128 | Target Report Mask(VSX) | |
129 | Use vector/scalar (VSX) instructions | |
78f5898b | 130 | |
a72c65c7 MM |
131 | mvsx-scalar-double |
132 | Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(-1) | |
133 | ; If -mvsx, use VSX arithmetic instructions for scalar double (on by default) | |
134 | ||
135 | mvsx-scalar-memory | |
136 | Target Undocumented Report Var(TARGET_VSX_SCALAR_MEMORY) | |
137 | ; If -mvsx, use VSX scalar memory reference instructions for scalar double (off by default) | |
138 | ||
139 | mvsx-align-128 | |
140 | Target Undocumented Report Var(TARGET_VSX_ALIGN_128) | |
141 | ; If -mvsx, set alignment to 128 bits instead of 32/64 | |
142 | ||
143 | mallow-movmisalign | |
144 | Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) | |
145 | ; Allow/disallow the movmisalign in DF/DI vectors | |
146 | ||
147 | mallow-df-permute | |
148 | Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE) | |
149 | ; Allow/disallow permutation of DF/DI vectors | |
150 | ||
151 | msched-groups | |
152 | Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) | |
153 | ; Explicitly set/unset whether rs6000_sched_groups is set | |
154 | ||
155 | malways-hint | |
156 | Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) | |
157 | ; Explicitly set/unset whether rs6000_always_hint is set | |
158 | ||
159 | malign-branch-targets | |
160 | Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) | |
161 | ; Explicitly set/unset whether rs6000_align_branch_targets is set | |
162 | ||
29e6733c MM |
163 | mvectorize-builtins |
164 | Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1) | |
165 | ; Explicitly control whether we vectorize the builtins or not. | |
166 | ||
ebde32fd BE |
167 | mno-update |
168 | Target Report RejectNegative Mask(NO_UPDATE) | |
169 | Do not generate load/store with update instructions | |
170 | ||
78f5898b | 171 | mupdate |
ebde32fd | 172 | Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) |
78f5898b AH |
173 | Generate load/store with update instructions |
174 | ||
001b9eb6 PH |
175 | mavoid-indexed-addresses |
176 | Target Report Var(TARGET_AVOID_XFORM) Init(-1) | |
177 | Avoid generation of indexed load/store instructions when possible | |
178 | ||
78f5898b | 179 | mfused-madd |
cacf1ca8 | 180 | Target Report Var(TARGET_FUSED_MADD) Init(1) |
78f5898b AH |
181 | Generate fused multiply/add instructions |
182 | ||
9752c4ad AM |
183 | mtls-markers |
184 | Target Report Var(tls_markers) Init(1) | |
185 | Mark __tls_get_addr calls with argument info | |
186 | ||
df4ba119 ILT |
187 | msched-epilog |
188 | Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) | |
189 | ||
78f5898b | 190 | msched-prolog |
f0036cca | 191 | Target Report Var(TARGET_SCHED_PROLOG) |
78f5898b AH |
192 | Schedule the start and end of the procedure |
193 | ||
78f5898b | 194 | maix-struct-return |
df01da37 | 195 | Target Report RejectNegative Var(aix_struct_return) |
78f5898b AH |
196 | Return all structures in memory (AIX default) |
197 | ||
198 | msvr4-struct-return | |
f0036cca | 199 | Target Report RejectNegative Var(aix_struct_return,0) |
78f5898b AH |
200 | Return small structures in registers (SVR4 default) |
201 | ||
432218ba | 202 | mxl-compat |
df01da37 | 203 | Target Report Var(TARGET_XL_COMPAT) |
432218ba | 204 | Conform more closely to IBM XLC semantics |
78f5898b | 205 | |
9c78b944 | 206 | mrecip |
92902797 MM |
207 | Target Report |
208 | Generate software reciprocal divide and square root for better throughput. | |
209 | ||
210 | mrecip= | |
211 | Target Report RejectNegative Joined | |
212 | Generate software reciprocal divide and square root for better throughput. | |
213 | ||
214 | mrecip-precision | |
215 | Target Report Mask(RECIP_PRECISION) | |
216 | Assume that the reciprocal estimate instructions provide more accuracy. | |
ef765ea9 | 217 | |
432218ba | 218 | mno-fp-in-toc |
d2894ab5 | 219 | Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) |
432218ba | 220 | Do not place floating point constants in TOC |
78f5898b | 221 | |
432218ba | 222 | mfp-in-toc |
95dc56a4 | 223 | Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) |
432218ba DE |
224 | Place floating point constants in TOC |
225 | ||
226 | mno-sum-in-toc | |
d2894ab5 | 227 | Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) |
432218ba DE |
228 | Do not place symbol+offset constants in TOC |
229 | ||
230 | msum-in-toc | |
f0036cca | 231 | Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) |
432218ba DE |
232 | Place symbol+offset constants in TOC |
233 | ||
234 | ; Output only one TOC entry per module. Normally linking fails if | |
235 | ; there are more than 16K unique variables/constants in an executable. With | |
236 | ; this option, linking fails only if there are more than 16K modules, or | |
237 | ; if there are more than 16K unique variables/constant in a single module. | |
238 | ; | |
239 | ; This is at the cost of having 2 extra loads and one extra store per | |
240 | ; function, and one less allocable register. | |
241 | mminimal-toc | |
242 | Target Report Mask(MINIMAL_TOC) | |
243 | Use only one TOC entry per procedure | |
78f5898b AH |
244 | |
245 | mfull-toc | |
246 | Target Report | |
247 | Put everything in the regular TOC | |
248 | ||
249 | mvrsave | |
250 | Target Report Var(TARGET_ALTIVEC_VRSAVE) | |
251 | Generate VRSAVE instructions when generating AltiVec code | |
252 | ||
253 | mvrsave= | |
254 | Target RejectNegative Joined | |
c85ce869 | 255 | -mvrsave=yes/no Deprecated option. Use -mvrsave/-mno-vrsave instead |
78f5898b | 256 | |
d95016e0 NF |
257 | mblock-move-inline-limit= |
258 | Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger | |
259 | Specify how many bytes should be moved inline before calling out to memcpy/memmove | |
260 | ||
78f5898b | 261 | misel |
cacf1ca8 | 262 | Target Report Mask(ISEL) |
78f5898b AH |
263 | Generate isel instructions |
264 | ||
265 | misel= | |
266 | Target RejectNegative Joined | |
267 | -misel=yes/no Deprecated option. Use -misel/-mno-isel instead | |
268 | ||
269 | mspe | |
94f4765c | 270 | Target |
78f5898b AH |
271 | Generate SPE SIMD instructions on E500 |
272 | ||
96038623 DE |
273 | mpaired |
274 | Target Var(rs6000_paired_float) | |
275 | Generate PPC750CL paired-single instructions | |
276 | ||
78f5898b AH |
277 | mspe= |
278 | Target RejectNegative Joined | |
279 | -mspe=yes/no Deprecated option. Use -mspe/-mno-spe instead | |
280 | ||
281 | mdebug= | |
282 | Target RejectNegative Joined | |
283 | -mdebug= Enable debug output | |
284 | ||
285 | mabi= | |
286 | Target RejectNegative Joined | |
287 | -mabi= Specify ABI to use | |
288 | ||
289 | mcpu= | |
290 | Target RejectNegative Joined | |
291 | -mcpu= Use features of and schedule code for given CPU | |
292 | ||
293 | mtune= | |
294 | Target RejectNegative Joined | |
295 | -mtune= Schedule code for given CPU | |
296 | ||
297 | mtraceback= | |
298 | Target RejectNegative Joined | |
299 | -mtraceback= Select full, part, or no traceback table | |
300 | ||
301 | mlongcall | |
302 | Target Report Var(rs6000_default_long_calls) | |
303 | Avoid all range limits on call instructions | |
304 | ||
c921bad8 AP |
305 | mgen-cell-microcode |
306 | Target Report Var(rs6000_gen_cell_microcode) Init(-1) | |
307 | Generate Cell microcode | |
308 | ||
309 | mwarn-cell-microcode | |
310 | Target Var(rs6000_warn_cell_microcode) Init(0) Warning | |
13233302 | 311 | Warn when a Cell microcoded instruction is emitted |
c921bad8 | 312 | |
78f5898b AH |
313 | mwarn-altivec-long |
314 | Target Var(rs6000_warn_altivec_long) Init(1) | |
315 | Warn about deprecated 'vector long ...' AltiVec type usage | |
316 | ||
317 | mfloat-gprs= | |
318 | Target RejectNegative Joined | |
c85ce869 | 319 | -mfloat-gprs= Select GPR floating point method |
78f5898b AH |
320 | |
321 | mlong-double- | |
322 | Target RejectNegative Joined UInteger | |
323 | -mlong-double-<n> Specify size of long double (64 or 128 bits) | |
324 | ||
325 | msched-costly-dep= | |
326 | Target RejectNegative Joined | |
327 | Determine which dependences between insns are considered costly | |
328 | ||
329 | minsert-sched-nops= | |
330 | Target RejectNegative Joined | |
331 | Specify which post scheduling nop insertion scheme to apply | |
332 | ||
333 | malign- | |
334 | Target RejectNegative Joined | |
335 | Specify alignment of structure fields default/natural | |
336 | ||
337 | mprioritize-restricted-insns= | |
2f828272 | 338 | Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) |
78f5898b | 339 | Specify scheduling priority for dispatch slot restricted insns |
696e45ba ME |
340 | |
341 | msingle-float | |
342 | Target RejectNegative Var(rs6000_single_float) | |
343 | Single-precision floating point unit | |
344 | ||
345 | mdouble-float | |
346 | Target RejectNegative Var(rs6000_double_float) | |
347 | Double-precision floating point unit | |
348 | ||
349 | msimple-fpu | |
350 | Target RejectNegative Var(rs6000_simple_fpu) | |
351 | Floating point unit does not support divide & sqrt | |
4849e836 DE |
352 | |
353 | mfpu= | |
354 | Target RejectNegative Joined | |
355 | -mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu) | |
356 | ||
357 | mxilinx-fpu | |
358 | Target Var(rs6000_xilinx_fpu) | |
359 | Specify Xilinx FPU. | |
360 | ||
361 |