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Commit | Line | Data |
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16ac04e7 | 1 | ; Options for the rs6000 port of the compiler |
2 | ; | |
fbd26352 | 3 | ; Copyright (C) 2005-2019 Free Software Foundation, Inc. |
16ac04e7 | 4 | ; Contributed by Aldy Hernandez <aldy@quesejoda.com>. |
5 | ; | |
6 | ; This file is part of GCC. | |
7 | ; | |
8 | ; GCC is free software; you can redistribute it and/or modify it under | |
9 | ; the terms of the GNU General Public License as published by the Free | |
038d1e19 | 10 | ; Software Foundation; either version 3, or (at your option) any later |
16ac04e7 | 11 | ; version. |
12 | ; | |
13 | ; GCC is distributed in the hope that it will be useful, but WITHOUT | |
14 | ; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
15 | ; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
16 | ; License for more details. | |
17 | ; | |
18 | ; You should have received a copy of the GNU General Public License | |
038d1e19 | 19 | ; along with GCC; see the file COPYING3. If not see |
20 | ; <http://www.gnu.org/licenses/>. | |
16ac04e7 | 21 | |
755fa783 | 22 | HeaderInclude |
23 | config/rs6000/rs6000-opts.h | |
24 | ||
62b54165 | 25 | ;; ISA flag bits (on/off) |
26 | Variable | |
27 | HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT | |
28 | ||
29 | TargetSave | |
30 | HOST_WIDE_INT x_rs6000_isa_flags | |
31 | ||
32 | ;; Miscellaneous flag bits that were set explicitly by the user | |
7511df0c | 33 | Variable |
34 | HOST_WIDE_INT rs6000_isa_flags_explicit | |
35 | ||
62b54165 | 36 | TargetSave |
37 | HOST_WIDE_INT x_rs6000_isa_flags_explicit | |
38 | ||
755fa783 | 39 | ;; Current processor |
40 | TargetVariable | |
01eb32e7 | 41 | enum processor_type rs6000_cpu = PROCESSOR_PPC603 |
755fa783 | 42 | |
93213c80 | 43 | ;; Current tuning |
44 | TargetVariable | |
45 | enum processor_type rs6000_tune = PROCESSOR_PPC603 | |
46 | ||
755fa783 | 47 | ;; Always emit branch hint bits. |
48 | TargetVariable | |
49 | unsigned char rs6000_always_hint | |
50 | ||
51 | ;; Schedule instructions for group formation. | |
52 | TargetVariable | |
53 | unsigned char rs6000_sched_groups | |
54 | ||
55 | ;; Align branch targets. | |
56 | TargetVariable | |
57 | unsigned char rs6000_align_branch_targets | |
58 | ||
59 | ;; Support for -msched-costly-dep option. | |
60 | TargetVariable | |
61 | enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly | |
62 | ||
63 | ;; Support for -minsert-sched-nops option. | |
64 | TargetVariable | |
65 | enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none | |
66 | ||
755fa783 | 67 | ;; Non-zero to allow overriding loop alignment. |
68 | TargetVariable | |
69 | unsigned char can_override_loop_align | |
70 | ||
71 | ;; Which small data model to use (for System V targets only) | |
72 | TargetVariable | |
73 | enum rs6000_sdata_type rs6000_sdata = SDATA_DATA | |
74 | ||
75 | ;; Bit size of immediate TLS offsets and string from which it is decoded. | |
76 | TargetVariable | |
77 | int rs6000_tls_size = 32 | |
78 | ||
79 | ;; ABI enumeration available for subtarget to use. | |
80 | TargetVariable | |
81 | enum rs6000_abi rs6000_current_abi = ABI_NONE | |
82 | ||
83 | ;; Type of traceback to use. | |
84 | TargetVariable | |
85 | enum rs6000_traceback_type rs6000_traceback = traceback_default | |
86 | ||
87 | ;; Control alignment for fields within structures. | |
88 | TargetVariable | |
89 | unsigned char rs6000_alignment_flags | |
90 | ||
91 | ;; Code model for 64-bit linux. | |
92 | TargetVariable | |
93 | enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL | |
94 | ||
95 | ;; What type of reciprocal estimation instructions to generate | |
96 | TargetVariable | |
97 | unsigned int rs6000_recip_control | |
98 | ||
0375b229 | 99 | ;; Mask of what builtin functions are allowed |
100 | TargetVariable | |
8ce9ff04 | 101 | HOST_WIDE_INT rs6000_builtin_mask |
0375b229 | 102 | |
755fa783 | 103 | ;; Debug flags |
104 | TargetVariable | |
105 | unsigned int rs6000_debug | |
106 | ||
9959b729 | 107 | ;; Whether to enable the -mfloat128 stuff without necessarily enabling the |
108 | ;; __float128 keyword. | |
109 | TargetSave | |
110 | unsigned char x_TARGET_FLOAT128_TYPE | |
111 | ||
112 | Variable | |
113 | unsigned char TARGET_FLOAT128_TYPE | |
114 | ||
34c34d94 | 115 | ;; This option existed in the past, but now is always on. |
16ac04e7 | 116 | mpowerpc |
34c34d94 | 117 | Target RejectNegative Undocumented Ignore |
16ac04e7 | 118 | |
119 | mpowerpc64 | |
62b54165 | 120 | Target Report Mask(POWERPC64) Var(rs6000_isa_flags) |
8fb42bbc | 121 | Use PowerPC-64 instruction set. |
16ac04e7 | 122 | |
a8bb341c | 123 | mpowerpc-gpopt |
62b54165 | 124 | Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags) |
8fb42bbc | 125 | Use PowerPC General Purpose group optional instructions. |
a8bb341c | 126 | |
127 | mpowerpc-gfxopt | |
62b54165 | 128 | Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags) |
8fb42bbc | 129 | Use PowerPC Graphics group optional instructions. |
a8bb341c | 130 | |
131 | mmfcrf | |
62b54165 | 132 | Target Report Mask(MFCRF) Var(rs6000_isa_flags) |
8fb42bbc | 133 | Use PowerPC V2.01 single field mfcr instruction. |
a8bb341c | 134 | |
135 | mpopcntb | |
62b54165 | 136 | Target Report Mask(POPCNTB) Var(rs6000_isa_flags) |
8fb42bbc | 137 | Use PowerPC V2.02 popcntb instruction. |
a6018579 | 138 | |
139 | mfprnd | |
62b54165 | 140 | Target Report Mask(FPRND) Var(rs6000_isa_flags) |
8fb42bbc | 141 | Use PowerPC V2.02 floating point rounding instructions. |
a8bb341c | 142 | |
3230b740 | 143 | mcmpb |
62b54165 | 144 | Target Report Mask(CMPB) Var(rs6000_isa_flags) |
8fb42bbc | 145 | Use PowerPC V2.05 compare bytes instruction. |
3230b740 | 146 | |
c15fcd1f | 147 | mmfpgpr |
62b54165 | 148 | Target Report Mask(MFPGPR) Var(rs6000_isa_flags) |
8fb42bbc | 149 | Use extended PowerPC V2.05 move floating point to/from GPR instructions. |
c15fcd1f | 150 | |
16ac04e7 | 151 | maltivec |
62b54165 | 152 | Target Report Mask(ALTIVEC) Var(rs6000_isa_flags) |
8fb42bbc | 153 | Use AltiVec instructions. |
16ac04e7 | 154 | |
dfbe5314 | 155 | mfold-gimple |
156 | Target Report Var(rs6000_fold_gimple) Init(1) | |
157 | Enable early gimple folding of builtins. | |
158 | ||
b44d7d37 | 159 | mhard-dfp |
62b54165 | 160 | Target Report Mask(DFP) Var(rs6000_isa_flags) |
8fb42bbc | 161 | Use decimal floating point instructions. |
3230b740 | 162 | |
624e1eec | 163 | mmulhw |
62b54165 | 164 | Target Report Mask(MULHW) Var(rs6000_isa_flags) |
8fb42bbc | 165 | Use 4xx half-word multiply instructions. |
624e1eec | 166 | |
671169ac | 167 | mdlmzb |
62b54165 | 168 | Target Report Mask(DLMZB) Var(rs6000_isa_flags) |
8fb42bbc | 169 | Use 4xx string-search dlmzb instruction. |
671169ac | 170 | |
a8bb341c | 171 | mmultiple |
62b54165 | 172 | Target Report Mask(MULTIPLE) Var(rs6000_isa_flags) |
8fb42bbc | 173 | Generate load/store multiple instructions. |
a8bb341c | 174 | |
9599990a | 175 | ;; This option existed in the past, but now is always off. |
176 | mno-string | |
177 | Target RejectNegative Undocumented Ignore | |
178 | ||
a8bb341c | 179 | mstring |
0c46a085 | 180 | Target RejectNegative Undocumented Deprecated |
a8bb341c | 181 | |
16ac04e7 | 182 | msoft-float |
62b54165 | 183 | Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags) |
8fb42bbc | 184 | Do not use hardware floating point. |
16ac04e7 | 185 | |
186 | mhard-float | |
62b54165 | 187 | Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags) |
8fb42bbc | 188 | Use hardware floating point. |
16ac04e7 | 189 | |
9c878e1b | 190 | mpopcntd |
62b54165 | 191 | Target Report Mask(POPCNTD) Var(rs6000_isa_flags) |
8fb42bbc | 192 | Use PowerPC V2.06 popcntd instruction. |
9c878e1b | 193 | |
eaf1b5fc | 194 | mfriz |
755fa783 | 195 | Target Report Var(TARGET_FRIZ) Init(-1) Save |
8fb42bbc | 196 | Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions. |
eaf1b5fc | 197 | |
ac3fd8d3 | 198 | mveclibabi= |
199 | Target RejectNegative Joined Var(rs6000_veclibabi_name) | |
8fb42bbc | 200 | Vector library ABI to use. |
79676f03 | 201 | |
9c878e1b | 202 | mvsx |
62b54165 | 203 | Target Report Mask(VSX) Var(rs6000_isa_flags) |
8fb42bbc | 204 | Use vector/scalar (VSX) instructions. |
16ac04e7 | 205 | |
702c5d85 | 206 | mvsx-align-128 |
7990e5de | 207 | Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save |
702c5d85 | 208 | ; If -mvsx, set alignment to 128 bits instead of 32/64 |
209 | ||
210 | mallow-movmisalign | |
7990e5de | 211 | Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save |
cb81f4b8 | 212 | ; Allow the movmisalign in DF/DI vectors |
702c5d85 | 213 | |
b1b27d3b | 214 | mefficient-unaligned-vsx |
9fb5a144 | 215 | Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags) |
b1b27d3b | 216 | ; Consider unaligned VSX vector and fp accesses to be efficient |
69a88c20 | 217 | |
702c5d85 | 218 | msched-groups |
7990e5de | 219 | Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Save |
cb81f4b8 | 220 | ; Explicitly set rs6000_sched_groups |
702c5d85 | 221 | |
222 | malways-hint | |
7990e5de | 223 | Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Save |
cb81f4b8 | 224 | ; Explicitly set rs6000_always_hint |
702c5d85 | 225 | |
226 | malign-branch-targets | |
7990e5de | 227 | Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save |
cb81f4b8 | 228 | ; Explicitly set rs6000_align_branch_targets |
702c5d85 | 229 | |
80c8ed02 | 230 | mno-update |
62b54165 | 231 | Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags) |
8fb42bbc | 232 | Do not generate load/store with update instructions. |
80c8ed02 | 233 | |
16ac04e7 | 234 | mupdate |
62b54165 | 235 | Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags) |
8fb42bbc | 236 | Generate load/store with update instructions. |
16ac04e7 | 237 | |
a20ee7a1 | 238 | msingle-pic-base |
239 | Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0) | |
8fb42bbc | 240 | Do not load the PIC register in function prologues. |
a20ee7a1 | 241 | |
2fdf186f | 242 | mavoid-indexed-addresses |
755fa783 | 243 | Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save |
8fb42bbc | 244 | Avoid generation of indexed load/store instructions when possible. |
2fdf186f | 245 | |
d46ea878 | 246 | mtls-markers |
755fa783 | 247 | Target Report Var(tls_markers) Init(1) Save |
8fb42bbc | 248 | Mark __tls_get_addr calls with argument info. |
d46ea878 | 249 | |
d6cf890d | 250 | msched-epilog |
755fa783 | 251 | Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save |
d6cf890d | 252 | |
16ac04e7 | 253 | msched-prolog |
755fa783 | 254 | Target Report Var(TARGET_SCHED_PROLOG) Save |
8fb42bbc | 255 | Schedule the start and end of the procedure. |
16ac04e7 | 256 | |
16ac04e7 | 257 | maix-struct-return |
755fa783 | 258 | Target Report RejectNegative Var(aix_struct_return) Save |
8fb42bbc | 259 | Return all structures in memory (AIX default). |
16ac04e7 | 260 | |
261 | msvr4-struct-return | |
755fa783 | 262 | Target Report RejectNegative Var(aix_struct_return,0) Save |
8fb42bbc | 263 | Return small structures in registers (SVR4 default). |
16ac04e7 | 264 | |
a8bb341c | 265 | mxl-compat |
755fa783 | 266 | Target Report Var(TARGET_XL_COMPAT) Save |
8fb42bbc | 267 | Conform more closely to IBM XLC semantics. |
16ac04e7 | 268 | |
7679d16d | 269 | mrecip |
0eac26de | 270 | Target Report |
271 | Generate software reciprocal divide and square root for better throughput. | |
272 | ||
273 | mrecip= | |
a4a5a0e9 | 274 | Target Report RejectNegative Joined Var(rs6000_recip_name) |
0eac26de | 275 | Generate software reciprocal divide and square root for better throughput. |
276 | ||
277 | mrecip-precision | |
62b54165 | 278 | Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags) |
0eac26de | 279 | Assume that the reciprocal estimate instructions provide more accuracy. |
f782d9e9 | 280 | |
a8bb341c | 281 | mno-fp-in-toc |
755fa783 | 282 | Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save |
8fb42bbc | 283 | Do not place floating point constants in TOC. |
16ac04e7 | 284 | |
a8bb341c | 285 | mfp-in-toc |
755fa783 | 286 | Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save |
8fb42bbc | 287 | Place floating point constants in TOC. |
a8bb341c | 288 | |
289 | mno-sum-in-toc | |
755fa783 | 290 | Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save |
8fb42bbc | 291 | Do not place symbol+offset constants in TOC. |
a8bb341c | 292 | |
293 | msum-in-toc | |
755fa783 | 294 | Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save |
8fb42bbc | 295 | Place symbol+offset constants in TOC. |
a8bb341c | 296 | |
297 | ; Output only one TOC entry per module. Normally linking fails if | |
298 | ; there are more than 16K unique variables/constants in an executable. With | |
299 | ; this option, linking fails only if there are more than 16K modules, or | |
300 | ; if there are more than 16K unique variables/constant in a single module. | |
301 | ; | |
302 | ; This is at the cost of having 2 extra loads and one extra store per | |
303 | ; function, and one less allocable register. | |
304 | mminimal-toc | |
62b54165 | 305 | Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags) |
8fb42bbc | 306 | Use only one TOC entry per procedure. |
16ac04e7 | 307 | |
308 | mfull-toc | |
309 | Target Report | |
8fb42bbc | 310 | Put everything in the regular TOC. |
16ac04e7 | 311 | |
312 | mvrsave | |
755fa783 | 313 | Target Report Var(TARGET_ALTIVEC_VRSAVE) Save |
8fb42bbc | 314 | Generate VRSAVE instructions when generating AltiVec code. |
16ac04e7 | 315 | |
4e775b8e | 316 | mvrsave=no |
e7038c57 | 317 | Target RejectNegative Alias(mvrsave) NegativeAlias Warn(%<-mvrsave=no%> is deprecated; use %<-mno-vrsave%> instead) |
8fb42bbc | 318 | Deprecated option. Use -mno-vrsave instead. |
4e775b8e | 319 | |
320 | mvrsave=yes | |
e7038c57 | 321 | Target RejectNegative Alias(mvrsave) Warn(%<-mvrsave=yes%> is deprecated; use %<-mvrsave%> instead) |
8fb42bbc | 322 | Deprecated option. Use -mvrsave instead. |
16ac04e7 | 323 | |
6b9ad50f | 324 | mblock-move-inline-limit= |
755fa783 | 325 | Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save |
079d9a87 | 326 | Max number of bytes to move inline. |
6b9ad50f | 327 | |
4157acef | 328 | mblock-compare-inline-limit= |
4d2cdcb1 | 329 | Target Report Var(rs6000_block_compare_inline_limit) Init(63) RejectNegative Joined UInteger Save |
079d9a87 | 330 | Max number of bytes to compare without loops. |
30803887 | 331 | |
332 | mblock-compare-inline-loop-limit= | |
333 | Target Report Var(rs6000_block_compare_inline_loop_limit) Init(-1) RejectNegative Joined UInteger Save | |
079d9a87 | 334 | Max number of bytes to compare with loops. |
4157acef | 335 | |
5618a0a9 | 336 | mstring-compare-inline-limit= |
d73e8cba | 337 | Target Report Var(rs6000_string_compare_inline_limit) Init(64) RejectNegative Joined UInteger Save |
338 | Max number of bytes to compare. | |
5618a0a9 | 339 | |
16ac04e7 | 340 | misel |
62b54165 | 341 | Target Report Mask(ISEL) Var(rs6000_isa_flags) |
8fb42bbc | 342 | Generate isel instructions. |
16ac04e7 | 343 | |
16ac04e7 | 344 | mdebug= |
345 | Target RejectNegative Joined | |
8fb42bbc | 346 | -mdebug= Enable debug output. |
16ac04e7 | 347 | |
b9f8199f | 348 | mabi=altivec |
349 | Target RejectNegative Var(rs6000_altivec_abi) Save | |
8fb42bbc | 350 | Use the AltiVec ABI extensions. |
b9f8199f | 351 | |
352 | mabi=no-altivec | |
353 | Target RejectNegative Var(rs6000_altivec_abi, 0) | |
8fb42bbc | 354 | Do not use the AltiVec ABI extensions. |
b9f8199f | 355 | |
238f342d | 356 | mabi=elfv1 |
357 | Target RejectNegative Var(rs6000_elf_abi, 1) Save | |
8fb42bbc | 358 | Use the ELFv1 ABI. |
238f342d | 359 | |
360 | mabi=elfv2 | |
361 | Target RejectNegative Var(rs6000_elf_abi, 2) | |
8fb42bbc | 362 | Use the ELFv2 ABI. |
238f342d | 363 | |
b9f8199f | 364 | ; These are here for testing during development only, do not document |
365 | ; in the manual please. | |
366 | ||
367 | ; If we want Darwin's struct-by-value-in-regs ABI. | |
368 | mabi=d64 | |
369 | Target RejectNegative Undocumented Warn(using darwin64 ABI) Var(rs6000_darwin64_abi) Save | |
370 | ||
371 | mabi=d32 | |
372 | Target RejectNegative Undocumented Warn(using old darwin ABI) Var(rs6000_darwin64_abi, 0) | |
373 | ||
374 | mabi=ieeelongdouble | |
2f89b19d | 375 | Target RejectNegative Var(rs6000_ieeequad) Save |
b9f8199f | 376 | |
377 | mabi=ibmlongdouble | |
2f89b19d | 378 | Target RejectNegative Var(rs6000_ieeequad, 0) |
16ac04e7 | 379 | |
380 | mcpu= | |
d41a5879 | 381 | Target RejectNegative Joined Var(rs6000_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save |
8fb42bbc | 382 | -mcpu= Use features of and schedule code for given CPU. |
16ac04e7 | 383 | |
384 | mtune= | |
d41a5879 | 385 | Target RejectNegative Joined Var(rs6000_tune_index) Init(-1) Enum(rs6000_cpu_opt_value) Save |
8fb42bbc | 386 | -mtune= Schedule code for given CPU. |
16ac04e7 | 387 | |
388 | mtraceback= | |
a4a5a0e9 | 389 | Target RejectNegative Joined Enum(rs6000_traceback_type) Var(rs6000_traceback) |
74fc2c55 | 390 | -mtraceback=[full,part,no] Select type of traceback table. |
16ac04e7 | 391 | |
a4a5a0e9 | 392 | Enum |
393 | Name(rs6000_traceback_type) Type(enum rs6000_traceback_type) | |
394 | ||
395 | EnumValue | |
396 | Enum(rs6000_traceback_type) String(full) Value(traceback_full) | |
397 | ||
398 | EnumValue | |
399 | Enum(rs6000_traceback_type) String(part) Value(traceback_part) | |
400 | ||
401 | EnumValue | |
402 | Enum(rs6000_traceback_type) String(no) Value(traceback_none) | |
403 | ||
16ac04e7 | 404 | mlongcall |
755fa783 | 405 | Target Report Var(rs6000_default_long_calls) Save |
8fb42bbc | 406 | Avoid all range limits on call instructions. |
16ac04e7 | 407 | |
460ff77d | 408 | ; This option existed in the past, but now is always on. |
14ffb23e | 409 | mgen-cell-microcode |
460ff77d | 410 | Target RejectNegative Undocumented Ignore |
14ffb23e | 411 | |
16ac04e7 | 412 | mwarn-altivec-long |
755fa783 | 413 | Target Var(rs6000_warn_altivec_long) Init(1) Save |
8fb42bbc | 414 | Warn about deprecated 'vector long ...' AltiVec type usage. |
16ac04e7 | 415 | |
16ac04e7 | 416 | mlong-double- |
a4a5a0e9 | 417 | Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save |
74fc2c55 | 418 | -mlong-double-[64,128] Specify size of long double. |
16ac04e7 | 419 | |
c9fcbe2f | 420 | ; This option existed in the past, but now is always on. |
bcdf945c | 421 | mlra |
c9fcbe2f | 422 | Target RejectNegative Undocumented Ignore |
bcdf945c | 423 | |
16ac04e7 | 424 | msched-costly-dep= |
a4a5a0e9 | 425 | Target RejectNegative Joined Var(rs6000_sched_costly_dep_str) |
8fb42bbc | 426 | Determine which dependences between insns are considered costly. |
16ac04e7 | 427 | |
428 | minsert-sched-nops= | |
a4a5a0e9 | 429 | Target RejectNegative Joined Var(rs6000_sched_insert_nops_str) |
8fb42bbc | 430 | Specify which post scheduling nop insertion scheme to apply. |
16ac04e7 | 431 | |
432 | malign- | |
a4a5a0e9 | 433 | Target RejectNegative Joined Enum(rs6000_alignment_flags) Var(rs6000_alignment_flags) |
8fb42bbc | 434 | Specify alignment of structure fields default/natural. |
16ac04e7 | 435 | |
a4a5a0e9 | 436 | Enum |
437 | Name(rs6000_alignment_flags) Type(unsigned char) | |
438 | Valid arguments to -malign-: | |
439 | ||
440 | EnumValue | |
441 | Enum(rs6000_alignment_flags) String(power) Value(MASK_ALIGN_POWER) | |
442 | ||
443 | EnumValue | |
444 | Enum(rs6000_alignment_flags) String(natural) Value(MASK_ALIGN_NATURAL) | |
445 | ||
16ac04e7 | 446 | mprioritize-restricted-insns= |
755fa783 | 447 | Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save |
8fb42bbc | 448 | Specify scheduling priority for dispatch slot restricted insns. |
3f5debcf | 449 | |
0763918e | 450 | mpointers-to-nested-functions |
451 | Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save | |
cb81f4b8 | 452 | Use r11 to hold the static link in calls to functions via pointers. |
9d855c8d | 453 | |
e2502ff1 | 454 | msave-toc-indirect |
7990e5de | 455 | Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags) |
cb81f4b8 | 456 | Save the TOC in the prologue for indirect calls rather than inline. |
33a2d887 | 457 | |
1da51dfb | 458 | ; This option existed in the past, but now is always the same as -mvsx. |
33a2d887 | 459 | mvsx-timode |
1da51dfb | 460 | Target RejectNegative Undocumented Ignore |
81f0e7d0 | 461 | |
462 | mpower8-fusion | |
463 | Target Report Mask(P8_FUSION) Var(rs6000_isa_flags) | |
8fb42bbc | 464 | Fuse certain integer operations together for better performance on power8. |
81f0e7d0 | 465 | |
466 | mpower8-fusion-sign | |
467 | Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags) | |
8fb42bbc | 468 | Allow sign extension in fusion operations. |
81f0e7d0 | 469 | |
470 | mpower8-vector | |
471 | Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags) | |
cb81f4b8 | 472 | Use vector and scalar instructions added in ISA 2.07. |
81f0e7d0 | 473 | |
474 | mcrypto | |
475 | Target Report Mask(CRYPTO) Var(rs6000_isa_flags) | |
8fb42bbc | 476 | Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions. |
81f0e7d0 | 477 | |
478 | mdirect-move | |
1a78f0f4 | 479 | Target Undocumented Mask(DIRECT_MOVE) Var(rs6000_isa_flags) Deprecated |
81f0e7d0 | 480 | |
5088e479 | 481 | mhtm |
482 | Target Report Mask(HTM) Var(rs6000_isa_flags) | |
8fb42bbc | 483 | Use ISA 2.07 transactional memory (HTM) instructions. |
5088e479 | 484 | |
81f0e7d0 | 485 | mquad-memory |
486 | Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags) | |
1c09f133 | 487 | Generate the quad word memory instructions (lq/stq). |
488 | ||
489 | mquad-memory-atomic | |
490 | Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags) | |
491 | Generate the quad word memory atomic instructions (lqarx/stqcx). | |
f2e80d2c | 492 | |
493 | mcompat-align-parm | |
494 | Target Report Var(rs6000_compat_align_parm) Init(0) Save | |
495 | Generate aggregate parameter passing code with at most 64-bit alignment. | |
fbacd2bf | 496 | |
1b66c2db | 497 | moptimize-swaps |
498 | Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save | |
499 | Analyze and remove doubleword swaps from VSX computations. | |
94f623e1 | 500 | |
17c32c4a | 501 | mpower9-misc |
502 | Target Undocumented Report Mask(P9_MISC) Var(rs6000_isa_flags) | |
cb81f4b8 | 503 | Use certain scalar instructions added in ISA 3.0. |
17c32c4a | 504 | |
a875ad2e | 505 | mpower9-vector |
60ed5c80 | 506 | Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags) |
cb81f4b8 | 507 | Use vector instructions added in ISA 3.0. |
a875ad2e | 508 | |
a875ad2e | 509 | mpower9-minmax |
510 | Target Undocumented Mask(P9_MINMAX) Var(rs6000_isa_flags) | |
cb81f4b8 | 511 | Use the new min/max instructions defined in ISA 3.0. |
a875ad2e | 512 | |
513 | mtoc-fusion | |
514 | Target Undocumented Mask(TOC_FUSION) Var(rs6000_isa_flags) | |
515 | Fuse medium/large code model toc references with the memory instruction. | |
516 | ||
517 | mmodulo | |
60ed5c80 | 518 | Target Undocumented Report Mask(MODULO) Var(rs6000_isa_flags) |
a875ad2e | 519 | Generate the integer modulo instructions. |
520 | ||
3f2bdc95 | 521 | mfloat128 |
7d29bba9 | 522 | Target Report Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags) |
cb81f4b8 | 523 | Enable IEEE 128-bit floating point via the __float128 keyword. |
a875ad2e | 524 | |
525 | mfloat128-hardware | |
526 | Target Report Mask(FLOAT128_HW) Var(rs6000_isa_flags) | |
cb81f4b8 | 527 | Enable using IEEE 128-bit floating point instructions. |
3d19def3 | 528 | |
529 | mfloat128-convert | |
530 | Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags) | |
cb81f4b8 | 531 | Enable default conversions between __float128 & long double. |
d59ca9c8 | 532 | |
88db15fe | 533 | mstack-protector-guard= |
534 | Target RejectNegative Joined Enum(stack_protector_guard) Var(rs6000_stack_protector_guard) Init(SSP_TLS) | |
535 | Use given stack-protector guard. | |
536 | ||
537 | Enum | |
538 | Name(stack_protector_guard) Type(enum stack_protector_guard) | |
539 | Valid arguments to -mstack-protector-guard=: | |
540 | ||
541 | EnumValue | |
542 | Enum(stack_protector_guard) String(tls) Value(SSP_TLS) | |
543 | ||
544 | EnumValue | |
545 | Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL) | |
546 | ||
547 | mstack-protector-guard-reg= | |
548 | Target RejectNegative Joined Var(rs6000_stack_protector_guard_reg_str) | |
549 | Use the given base register for addressing the stack-protector guard. | |
550 | ||
551 | TargetVariable | |
552 | int rs6000_stack_protector_guard_reg = 0 | |
553 | ||
554 | mstack-protector-guard-offset= | |
555 | Target RejectNegative Joined Integer Var(rs6000_stack_protector_guard_offset_str) | |
556 | Use the given offset for addressing the stack-protector guard. | |
557 | ||
558 | TargetVariable | |
559 | long rs6000_stack_protector_guard_offset = 0 | |
3fccde8c | 560 | |
561 | ;; -mno-speculate-indirect-jumps adds deliberate misprediction to indirect | |
562 | ;; branches via the CTR. | |
563 | mspeculate-indirect-jumps | |
564 | Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save |