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16ac04e7 1; Options for the rs6000 port of the compiler
2;
fbd26352 3; Copyright (C) 2005-2019 Free Software Foundation, Inc.
16ac04e7 4; Contributed by Aldy Hernandez <aldy@quesejoda.com>.
5;
6; This file is part of GCC.
7;
8; GCC is free software; you can redistribute it and/or modify it under
9; the terms of the GNU General Public License as published by the Free
038d1e19 10; Software Foundation; either version 3, or (at your option) any later
16ac04e7 11; version.
12;
13; GCC is distributed in the hope that it will be useful, but WITHOUT
14; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16; License for more details.
17;
18; You should have received a copy of the GNU General Public License
038d1e19 19; along with GCC; see the file COPYING3. If not see
20; <http://www.gnu.org/licenses/>.
16ac04e7 21
755fa783 22HeaderInclude
23config/rs6000/rs6000-opts.h
24
62b54165 25;; ISA flag bits (on/off)
26Variable
27HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT
28
29TargetSave
30HOST_WIDE_INT x_rs6000_isa_flags
31
32;; Miscellaneous flag bits that were set explicitly by the user
7511df0c 33Variable
34HOST_WIDE_INT rs6000_isa_flags_explicit
35
62b54165 36TargetSave
37HOST_WIDE_INT x_rs6000_isa_flags_explicit
38
755fa783 39;; Current processor
40TargetVariable
01eb32e7 41enum processor_type rs6000_cpu = PROCESSOR_PPC603
755fa783 42
93213c80 43;; Current tuning
44TargetVariable
45enum processor_type rs6000_tune = PROCESSOR_PPC603
46
755fa783 47;; Always emit branch hint bits.
48TargetVariable
49unsigned char rs6000_always_hint
50
51;; Schedule instructions for group formation.
52TargetVariable
53unsigned char rs6000_sched_groups
54
55;; Align branch targets.
56TargetVariable
57unsigned char rs6000_align_branch_targets
58
59;; Support for -msched-costly-dep option.
60TargetVariable
61enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly
62
63;; Support for -minsert-sched-nops option.
64TargetVariable
65enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none
66
755fa783 67;; Non-zero to allow overriding loop alignment.
68TargetVariable
69unsigned char can_override_loop_align
70
71;; Which small data model to use (for System V targets only)
72TargetVariable
73enum rs6000_sdata_type rs6000_sdata = SDATA_DATA
74
75;; Bit size of immediate TLS offsets and string from which it is decoded.
76TargetVariable
77int rs6000_tls_size = 32
78
79;; ABI enumeration available for subtarget to use.
80TargetVariable
81enum rs6000_abi rs6000_current_abi = ABI_NONE
82
83;; Type of traceback to use.
84TargetVariable
85enum rs6000_traceback_type rs6000_traceback = traceback_default
86
87;; Control alignment for fields within structures.
88TargetVariable
89unsigned char rs6000_alignment_flags
90
91;; Code model for 64-bit linux.
92TargetVariable
93enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL
94
95;; What type of reciprocal estimation instructions to generate
96TargetVariable
97unsigned int rs6000_recip_control
98
0375b229 99;; Mask of what builtin functions are allowed
100TargetVariable
8ce9ff04 101HOST_WIDE_INT rs6000_builtin_mask
0375b229 102
755fa783 103;; Debug flags
104TargetVariable
105unsigned int rs6000_debug
106
9959b729 107;; Whether to enable the -mfloat128 stuff without necessarily enabling the
108;; __float128 keyword.
109TargetSave
110unsigned char x_TARGET_FLOAT128_TYPE
111
112Variable
113unsigned char TARGET_FLOAT128_TYPE
114
34c34d94 115;; This option existed in the past, but now is always on.
16ac04e7 116mpowerpc
34c34d94 117Target RejectNegative Undocumented Ignore
16ac04e7 118
119mpowerpc64
62b54165 120Target Report Mask(POWERPC64) Var(rs6000_isa_flags)
8fb42bbc 121Use PowerPC-64 instruction set.
16ac04e7 122
a8bb341c 123mpowerpc-gpopt
62b54165 124Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags)
8fb42bbc 125Use PowerPC General Purpose group optional instructions.
a8bb341c 126
127mpowerpc-gfxopt
62b54165 128Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags)
8fb42bbc 129Use PowerPC Graphics group optional instructions.
a8bb341c 130
131mmfcrf
62b54165 132Target Report Mask(MFCRF) Var(rs6000_isa_flags)
8fb42bbc 133Use PowerPC V2.01 single field mfcr instruction.
a8bb341c 134
135mpopcntb
62b54165 136Target Report Mask(POPCNTB) Var(rs6000_isa_flags)
8fb42bbc 137Use PowerPC V2.02 popcntb instruction.
a6018579 138
139mfprnd
62b54165 140Target Report Mask(FPRND) Var(rs6000_isa_flags)
8fb42bbc 141Use PowerPC V2.02 floating point rounding instructions.
a8bb341c 142
3230b740 143mcmpb
62b54165 144Target Report Mask(CMPB) Var(rs6000_isa_flags)
8fb42bbc 145Use PowerPC V2.05 compare bytes instruction.
3230b740 146
c15fcd1f 147mmfpgpr
62b54165 148Target Report Mask(MFPGPR) Var(rs6000_isa_flags)
8fb42bbc 149Use extended PowerPC V2.05 move floating point to/from GPR instructions.
c15fcd1f 150
16ac04e7 151maltivec
62b54165 152Target Report Mask(ALTIVEC) Var(rs6000_isa_flags)
8fb42bbc 153Use AltiVec instructions.
16ac04e7 154
dfbe5314 155mfold-gimple
156Target Report Var(rs6000_fold_gimple) Init(1)
157Enable early gimple folding of builtins.
158
b44d7d37 159mhard-dfp
62b54165 160Target Report Mask(DFP) Var(rs6000_isa_flags)
8fb42bbc 161Use decimal floating point instructions.
3230b740 162
624e1eec 163mmulhw
62b54165 164Target Report Mask(MULHW) Var(rs6000_isa_flags)
8fb42bbc 165Use 4xx half-word multiply instructions.
624e1eec 166
671169ac 167mdlmzb
62b54165 168Target Report Mask(DLMZB) Var(rs6000_isa_flags)
8fb42bbc 169Use 4xx string-search dlmzb instruction.
671169ac 170
a8bb341c 171mmultiple
62b54165 172Target Report Mask(MULTIPLE) Var(rs6000_isa_flags)
8fb42bbc 173Generate load/store multiple instructions.
a8bb341c 174
9599990a 175;; This option existed in the past, but now is always off.
176mno-string
177Target RejectNegative Undocumented Ignore
178
a8bb341c 179mstring
0c46a085 180Target RejectNegative Undocumented Deprecated
a8bb341c 181
16ac04e7 182msoft-float
62b54165 183Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags)
8fb42bbc 184Do not use hardware floating point.
16ac04e7 185
186mhard-float
62b54165 187Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags)
8fb42bbc 188Use hardware floating point.
16ac04e7 189
9c878e1b 190mpopcntd
62b54165 191Target Report Mask(POPCNTD) Var(rs6000_isa_flags)
8fb42bbc 192Use PowerPC V2.06 popcntd instruction.
9c878e1b 193
eaf1b5fc 194mfriz
755fa783 195Target Report Var(TARGET_FRIZ) Init(-1) Save
8fb42bbc 196Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions.
eaf1b5fc 197
ac3fd8d3 198mveclibabi=
199Target RejectNegative Joined Var(rs6000_veclibabi_name)
8fb42bbc 200Vector library ABI to use.
79676f03 201
9c878e1b 202mvsx
62b54165 203Target Report Mask(VSX) Var(rs6000_isa_flags)
8fb42bbc 204Use vector/scalar (VSX) instructions.
16ac04e7 205
702c5d85 206mvsx-align-128
7990e5de 207Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save
702c5d85 208; If -mvsx, set alignment to 128 bits instead of 32/64
209
210mallow-movmisalign
7990e5de 211Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save
cb81f4b8 212; Allow the movmisalign in DF/DI vectors
702c5d85 213
b1b27d3b 214mefficient-unaligned-vsx
9fb5a144 215Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags)
b1b27d3b 216; Consider unaligned VSX vector and fp accesses to be efficient
69a88c20 217
702c5d85 218msched-groups
7990e5de 219Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Save
cb81f4b8 220; Explicitly set rs6000_sched_groups
702c5d85 221
222malways-hint
7990e5de 223Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Save
cb81f4b8 224; Explicitly set rs6000_always_hint
702c5d85 225
226malign-branch-targets
7990e5de 227Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save
cb81f4b8 228; Explicitly set rs6000_align_branch_targets
702c5d85 229
80c8ed02 230mno-update
62b54165 231Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags)
8fb42bbc 232Do not generate load/store with update instructions.
80c8ed02 233
16ac04e7 234mupdate
62b54165 235Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags)
8fb42bbc 236Generate load/store with update instructions.
16ac04e7 237
a20ee7a1 238msingle-pic-base
239Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0)
8fb42bbc 240Do not load the PIC register in function prologues.
a20ee7a1 241
2fdf186f 242mavoid-indexed-addresses
755fa783 243Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save
8fb42bbc 244Avoid generation of indexed load/store instructions when possible.
2fdf186f 245
d46ea878 246mtls-markers
755fa783 247Target Report Var(tls_markers) Init(1) Save
8fb42bbc 248Mark __tls_get_addr calls with argument info.
d46ea878 249
d6cf890d 250msched-epilog
755fa783 251Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save
d6cf890d 252
16ac04e7 253msched-prolog
755fa783 254Target Report Var(TARGET_SCHED_PROLOG) Save
8fb42bbc 255Schedule the start and end of the procedure.
16ac04e7 256
16ac04e7 257maix-struct-return
755fa783 258Target Report RejectNegative Var(aix_struct_return) Save
8fb42bbc 259Return all structures in memory (AIX default).
16ac04e7 260
261msvr4-struct-return
755fa783 262Target Report RejectNegative Var(aix_struct_return,0) Save
8fb42bbc 263Return small structures in registers (SVR4 default).
16ac04e7 264
a8bb341c 265mxl-compat
755fa783 266Target Report Var(TARGET_XL_COMPAT) Save
8fb42bbc 267Conform more closely to IBM XLC semantics.
16ac04e7 268
7679d16d 269mrecip
0eac26de 270Target Report
271Generate software reciprocal divide and square root for better throughput.
272
273mrecip=
a4a5a0e9 274Target Report RejectNegative Joined Var(rs6000_recip_name)
0eac26de 275Generate software reciprocal divide and square root for better throughput.
276
277mrecip-precision
62b54165 278Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags)
0eac26de 279Assume that the reciprocal estimate instructions provide more accuracy.
f782d9e9 280
a8bb341c 281mno-fp-in-toc
755fa783 282Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save
8fb42bbc 283Do not place floating point constants in TOC.
16ac04e7 284
a8bb341c 285mfp-in-toc
755fa783 286Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save
8fb42bbc 287Place floating point constants in TOC.
a8bb341c 288
289mno-sum-in-toc
755fa783 290Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save
8fb42bbc 291Do not place symbol+offset constants in TOC.
a8bb341c 292
293msum-in-toc
755fa783 294Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save
8fb42bbc 295Place symbol+offset constants in TOC.
a8bb341c 296
297; Output only one TOC entry per module. Normally linking fails if
298; there are more than 16K unique variables/constants in an executable. With
299; this option, linking fails only if there are more than 16K modules, or
300; if there are more than 16K unique variables/constant in a single module.
301;
302; This is at the cost of having 2 extra loads and one extra store per
303; function, and one less allocable register.
304mminimal-toc
62b54165 305Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags)
8fb42bbc 306Use only one TOC entry per procedure.
16ac04e7 307
308mfull-toc
309Target Report
8fb42bbc 310Put everything in the regular TOC.
16ac04e7 311
312mvrsave
755fa783 313Target Report Var(TARGET_ALTIVEC_VRSAVE) Save
8fb42bbc 314Generate VRSAVE instructions when generating AltiVec code.
16ac04e7 315
4e775b8e 316mvrsave=no
e7038c57 317Target RejectNegative Alias(mvrsave) NegativeAlias Warn(%<-mvrsave=no%> is deprecated; use %<-mno-vrsave%> instead)
8fb42bbc 318Deprecated option. Use -mno-vrsave instead.
4e775b8e 319
320mvrsave=yes
e7038c57 321Target RejectNegative Alias(mvrsave) Warn(%<-mvrsave=yes%> is deprecated; use %<-mvrsave%> instead)
8fb42bbc 322Deprecated option. Use -mvrsave instead.
16ac04e7 323
6b9ad50f 324mblock-move-inline-limit=
755fa783 325Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save
079d9a87 326Max number of bytes to move inline.
6b9ad50f 327
4157acef 328mblock-compare-inline-limit=
4d2cdcb1 329Target Report Var(rs6000_block_compare_inline_limit) Init(63) RejectNegative Joined UInteger Save
079d9a87 330Max number of bytes to compare without loops.
30803887 331
332mblock-compare-inline-loop-limit=
333Target Report Var(rs6000_block_compare_inline_loop_limit) Init(-1) RejectNegative Joined UInteger Save
079d9a87 334Max number of bytes to compare with loops.
4157acef 335
5618a0a9 336mstring-compare-inline-limit=
d73e8cba 337Target Report Var(rs6000_string_compare_inline_limit) Init(64) RejectNegative Joined UInteger Save
338Max number of bytes to compare.
5618a0a9 339
16ac04e7 340misel
62b54165 341Target Report Mask(ISEL) Var(rs6000_isa_flags)
8fb42bbc 342Generate isel instructions.
16ac04e7 343
16ac04e7 344mdebug=
345Target RejectNegative Joined
8fb42bbc 346-mdebug= Enable debug output.
16ac04e7 347
b9f8199f 348mabi=altivec
349Target RejectNegative Var(rs6000_altivec_abi) Save
8fb42bbc 350Use the AltiVec ABI extensions.
b9f8199f 351
352mabi=no-altivec
353Target RejectNegative Var(rs6000_altivec_abi, 0)
8fb42bbc 354Do not use the AltiVec ABI extensions.
b9f8199f 355
238f342d 356mabi=elfv1
357Target RejectNegative Var(rs6000_elf_abi, 1) Save
8fb42bbc 358Use the ELFv1 ABI.
238f342d 359
360mabi=elfv2
361Target RejectNegative Var(rs6000_elf_abi, 2)
8fb42bbc 362Use the ELFv2 ABI.
238f342d 363
b9f8199f 364; These are here for testing during development only, do not document
365; in the manual please.
366
367; If we want Darwin's struct-by-value-in-regs ABI.
368mabi=d64
369Target RejectNegative Undocumented Warn(using darwin64 ABI) Var(rs6000_darwin64_abi) Save
370
371mabi=d32
372Target RejectNegative Undocumented Warn(using old darwin ABI) Var(rs6000_darwin64_abi, 0)
373
374mabi=ieeelongdouble
2f89b19d 375Target RejectNegative Var(rs6000_ieeequad) Save
b9f8199f 376
377mabi=ibmlongdouble
2f89b19d 378Target RejectNegative Var(rs6000_ieeequad, 0)
16ac04e7 379
380mcpu=
d41a5879 381Target RejectNegative Joined Var(rs6000_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
8fb42bbc 382-mcpu= Use features of and schedule code for given CPU.
16ac04e7 383
384mtune=
d41a5879 385Target RejectNegative Joined Var(rs6000_tune_index) Init(-1) Enum(rs6000_cpu_opt_value) Save
8fb42bbc 386-mtune= Schedule code for given CPU.
16ac04e7 387
388mtraceback=
a4a5a0e9 389Target RejectNegative Joined Enum(rs6000_traceback_type) Var(rs6000_traceback)
74fc2c55 390-mtraceback=[full,part,no] Select type of traceback table.
16ac04e7 391
a4a5a0e9 392Enum
393Name(rs6000_traceback_type) Type(enum rs6000_traceback_type)
394
395EnumValue
396Enum(rs6000_traceback_type) String(full) Value(traceback_full)
397
398EnumValue
399Enum(rs6000_traceback_type) String(part) Value(traceback_part)
400
401EnumValue
402Enum(rs6000_traceback_type) String(no) Value(traceback_none)
403
16ac04e7 404mlongcall
755fa783 405Target Report Var(rs6000_default_long_calls) Save
8fb42bbc 406Avoid all range limits on call instructions.
16ac04e7 407
460ff77d 408; This option existed in the past, but now is always on.
14ffb23e 409mgen-cell-microcode
460ff77d 410Target RejectNegative Undocumented Ignore
14ffb23e 411
16ac04e7 412mwarn-altivec-long
755fa783 413Target Var(rs6000_warn_altivec_long) Init(1) Save
8fb42bbc 414Warn about deprecated 'vector long ...' AltiVec type usage.
16ac04e7 415
16ac04e7 416mlong-double-
a4a5a0e9 417Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save
74fc2c55 418-mlong-double-[64,128] Specify size of long double.
16ac04e7 419
c9fcbe2f 420; This option existed in the past, but now is always on.
bcdf945c 421mlra
c9fcbe2f 422Target RejectNegative Undocumented Ignore
bcdf945c 423
16ac04e7 424msched-costly-dep=
a4a5a0e9 425Target RejectNegative Joined Var(rs6000_sched_costly_dep_str)
8fb42bbc 426Determine which dependences between insns are considered costly.
16ac04e7 427
428minsert-sched-nops=
a4a5a0e9 429Target RejectNegative Joined Var(rs6000_sched_insert_nops_str)
8fb42bbc 430Specify which post scheduling nop insertion scheme to apply.
16ac04e7 431
432malign-
a4a5a0e9 433Target RejectNegative Joined Enum(rs6000_alignment_flags) Var(rs6000_alignment_flags)
8fb42bbc 434Specify alignment of structure fields default/natural.
16ac04e7 435
a4a5a0e9 436Enum
437Name(rs6000_alignment_flags) Type(unsigned char)
438Valid arguments to -malign-:
439
440EnumValue
441Enum(rs6000_alignment_flags) String(power) Value(MASK_ALIGN_POWER)
442
443EnumValue
444Enum(rs6000_alignment_flags) String(natural) Value(MASK_ALIGN_NATURAL)
445
16ac04e7 446mprioritize-restricted-insns=
755fa783 447Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save
8fb42bbc 448Specify scheduling priority for dispatch slot restricted insns.
3f5debcf 449
0763918e 450mpointers-to-nested-functions
451Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save
cb81f4b8 452Use r11 to hold the static link in calls to functions via pointers.
9d855c8d 453
e2502ff1 454msave-toc-indirect
7990e5de 455Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags)
cb81f4b8 456Save the TOC in the prologue for indirect calls rather than inline.
33a2d887 457
1da51dfb 458; This option existed in the past, but now is always the same as -mvsx.
33a2d887 459mvsx-timode
1da51dfb 460Target RejectNegative Undocumented Ignore
81f0e7d0 461
462mpower8-fusion
463Target Report Mask(P8_FUSION) Var(rs6000_isa_flags)
8fb42bbc 464Fuse certain integer operations together for better performance on power8.
81f0e7d0 465
466mpower8-fusion-sign
467Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags)
8fb42bbc 468Allow sign extension in fusion operations.
81f0e7d0 469
470mpower8-vector
471Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags)
cb81f4b8 472Use vector and scalar instructions added in ISA 2.07.
81f0e7d0 473
474mcrypto
475Target Report Mask(CRYPTO) Var(rs6000_isa_flags)
8fb42bbc 476Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions.
81f0e7d0 477
478mdirect-move
1a78f0f4 479Target Undocumented Mask(DIRECT_MOVE) Var(rs6000_isa_flags) Deprecated
81f0e7d0 480
5088e479 481mhtm
482Target Report Mask(HTM) Var(rs6000_isa_flags)
8fb42bbc 483Use ISA 2.07 transactional memory (HTM) instructions.
5088e479 484
81f0e7d0 485mquad-memory
486Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags)
1c09f133 487Generate the quad word memory instructions (lq/stq).
488
489mquad-memory-atomic
490Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags)
491Generate the quad word memory atomic instructions (lqarx/stqcx).
f2e80d2c 492
493mcompat-align-parm
494Target Report Var(rs6000_compat_align_parm) Init(0) Save
495Generate aggregate parameter passing code with at most 64-bit alignment.
fbacd2bf 496
1b66c2db 497moptimize-swaps
498Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save
499Analyze and remove doubleword swaps from VSX computations.
94f623e1 500
17c32c4a 501mpower9-misc
502Target Undocumented Report Mask(P9_MISC) Var(rs6000_isa_flags)
cb81f4b8 503Use certain scalar instructions added in ISA 3.0.
17c32c4a 504
a875ad2e 505mpower9-vector
60ed5c80 506Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
cb81f4b8 507Use vector instructions added in ISA 3.0.
a875ad2e 508
a875ad2e 509mpower9-minmax
510Target Undocumented Mask(P9_MINMAX) Var(rs6000_isa_flags)
cb81f4b8 511Use the new min/max instructions defined in ISA 3.0.
a875ad2e 512
513mtoc-fusion
514Target Undocumented Mask(TOC_FUSION) Var(rs6000_isa_flags)
515Fuse medium/large code model toc references with the memory instruction.
516
517mmodulo
60ed5c80 518Target Undocumented Report Mask(MODULO) Var(rs6000_isa_flags)
a875ad2e 519Generate the integer modulo instructions.
520
3f2bdc95 521mfloat128
7d29bba9 522Target Report Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags)
cb81f4b8 523Enable IEEE 128-bit floating point via the __float128 keyword.
a875ad2e 524
525mfloat128-hardware
526Target Report Mask(FLOAT128_HW) Var(rs6000_isa_flags)
cb81f4b8 527Enable using IEEE 128-bit floating point instructions.
3d19def3 528
529mfloat128-convert
530Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags)
cb81f4b8 531Enable default conversions between __float128 & long double.
d59ca9c8 532
88db15fe 533mstack-protector-guard=
534Target RejectNegative Joined Enum(stack_protector_guard) Var(rs6000_stack_protector_guard) Init(SSP_TLS)
535Use given stack-protector guard.
536
537Enum
538Name(stack_protector_guard) Type(enum stack_protector_guard)
539Valid arguments to -mstack-protector-guard=:
540
541EnumValue
542Enum(stack_protector_guard) String(tls) Value(SSP_TLS)
543
544EnumValue
545Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)
546
547mstack-protector-guard-reg=
548Target RejectNegative Joined Var(rs6000_stack_protector_guard_reg_str)
549Use the given base register for addressing the stack-protector guard.
550
551TargetVariable
552int rs6000_stack_protector_guard_reg = 0
553
554mstack-protector-guard-offset=
555Target RejectNegative Joined Integer Var(rs6000_stack_protector_guard_offset_str)
556Use the given offset for addressing the stack-protector guard.
557
558TargetVariable
559long rs6000_stack_protector_guard_offset = 0
3fccde8c 560
561;; -mno-speculate-indirect-jumps adds deliberate misprediction to indirect
562;; branches via the CTR.
563mspeculate-indirect-jumps
564Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save