]> git.ipfire.org Git - thirdparty/gcc.git/blame - gcc/config/rs6000/spe.md
projects / thirdparty / gcc.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Daily bump.
[thirdparty/gcc.git] / gcc / config / rs6000 / spe.md
CommitLineData
a3170dc6 1;; e500 SPE description
5b86a469 2;; Copyright (C) 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
a3170dc6
AH		 3;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
4
5de601cf 5;; This file is part of GCC.
a3170dc6 6
5de601cf
NC		 7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
9;; by the Free Software Foundation; either version 2, or (at your
10;; option) any later version.
a3170dc6 11
5de601cf
NC		 12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15;; License for more details.
a3170dc6
AH		 16
17;; You should have received a copy of the GNU General Public License
5de601cf
NC		 18;; along with GCC; see the file COPYING. If not, write to the
19;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
20;; MA 02111-1307, USA.
a3170dc6
AH		 21
22(define_constants
23 [(SPE_ACC_REGNO 111)
4d4cbc0e
AH		 24 (SPEFSCR_REGNO 112)
25
26 (CMPDFEQ_GPR 1006)
27 (TSTDFEQ_GPR 1007)
28 (CMPDFGT_GPR 1008)
29 (TSTDFGT_GPR 1009)
30 (CMPDFLT_GPR 1010)
31 (TSTDFLT_GPR 1011)
32 ])
a3170dc6
AH		 33
34(define_insn "*negsf2_gpr"
35 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
36 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
37 "TARGET_HARD_FLOAT && !TARGET_FPRS"
38 "efsneg %0,%1"
5e8006fa 39 [(set_attr "type" "fpsimple")])
a3170dc6
AH		 40
41(define_insn "*abssf2_gpr"
42 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
43 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
44 "TARGET_HARD_FLOAT && !TARGET_FPRS"
45 "efsabs %0,%1"
5e8006fa 46 [(set_attr "type" "fpsimple")])
a3170dc6 47
fe9c3a97
AH		 48(define_insn "*nabssf2_gpr"
49 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
50 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r"))))]
51 "TARGET_HARD_FLOAT && !TARGET_FPRS"
52 "efsnabs %0,%1"
53 [(set_attr "type" "fpsimple")])
54
a3170dc6
AH		 55(define_insn "*addsf3_gpr"
56 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
57 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
58 (match_operand:SF 2 "gpc_reg_operand" "r")))]
59 "TARGET_HARD_FLOAT && !TARGET_FPRS"
60 "efsadd %0,%1,%2"
61 [(set_attr "type" "fp")])
62
63(define_insn "*subsf3_gpr"
64 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
65 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "r")
66 (match_operand:SF 2 "gpc_reg_operand" "r")))]
67 "TARGET_HARD_FLOAT && !TARGET_FPRS"
68 "efssub %0,%1,%2"
69 [(set_attr "type" "fp")])
70
71(define_insn "*mulsf3_gpr"
72 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
73 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
74 (match_operand:SF 2 "gpc_reg_operand" "r")))]
75 "TARGET_HARD_FLOAT && !TARGET_FPRS"
76 "efsmul %0,%1,%2"
77 [(set_attr "type" "fp")])
78
79(define_insn "*divsf3_gpr"
80 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
81 (div:SF (match_operand:SF 1 "gpc_reg_operand" "r")
82 (match_operand:SF 2 "gpc_reg_operand" "r")))]
83 "TARGET_HARD_FLOAT && !TARGET_FPRS"
84 "efsdiv %0,%1,%2"
5e8006fa 85 [(set_attr "type" "vecfdiv")])
a3170dc6 86
7a2f7870
AH		 87;; Floating point conversion instructions.
88
89(define_insn "fixuns_truncdfsi2"
90 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
91 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
92 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
93 "efdctuiz %0,%1"
94 [(set_attr "type" "fp")])
95
7a2f7870
AH		 96(define_insn "spe_extendsfdf2"
97 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
98 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "r")))]
99 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
100 "efdcfs %0,%1"
101 [(set_attr "type" "fp")])
102
d095928f 103(define_insn "spe_fixuns_truncsfsi2"
a3170dc6 104 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
d095928f 105 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
a3170dc6
AH		 106 "TARGET_HARD_FLOAT && !TARGET_FPRS"
107 "efsctuiz %0,%1"
108 [(set_attr "type" "fp")])
109
d095928f
AH		 110(define_insn "spe_fix_truncsfsi2"
111 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
112 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
113 "TARGET_HARD_FLOAT && !TARGET_FPRS"
114 "efsctsiz %0,%1"
115 [(set_attr "type" "fp")])
a3170dc6 116
7a2f7870
AH		 117(define_insn "spe_fix_truncdfsi2"
118 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
119 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
120 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
121 "efdctsiz %0,%1"
122 [(set_attr "type" "fp")])
123
a3170dc6
AH		 124(define_insn "spe_floatunssisf2"
125 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
126 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
127 "TARGET_HARD_FLOAT && !TARGET_FPRS"
128 "efscfui %0,%1"
129 [(set_attr "type" "fp")])
130
7a2f7870
AH		 131(define_insn "spe_floatunssidf2"
132 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
133 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
134 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
135 "efdcfui %0,%1"
136 [(set_attr "type" "fp")])
137
a3170dc6
AH		 138(define_insn "spe_floatsisf2"
139 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
140 (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
141 "TARGET_HARD_FLOAT && !TARGET_FPRS"
142 "efscfsi %0,%1"
143 [(set_attr "type" "fp")])
144
7a2f7870
AH		 145(define_insn "spe_floatsidf2"
146 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
147 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
148 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
149 "efdcfsi %0,%1"
150 [(set_attr "type" "fp")])
a3170dc6
AH		 151
152;; SPE SIMD instructions
153
154(define_insn "spe_evabs"
155 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
156 (abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
157 "TARGET_SPE"
158 "evabs %0,%1"
159 [(set_attr "type" "vecsimple")
160 (set_attr "length" "4")])
161
162(define_insn "spe_evandc"
163 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
164 (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
165 (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
166 "TARGET_SPE"
167 "evandc %0,%1,%2"
168 [(set_attr "type" "vecsimple")
169 (set_attr "length" "4")])
170
171(define_insn "spe_evand"
172 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
173 (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
174 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
175 "TARGET_SPE"
176 "evand %0,%1,%2"
177 [(set_attr "type" "vecsimple")
178 (set_attr "length" "4")])
179
180;; Vector compare instructions
181
182(define_insn "spe_evcmpeq"
183 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
184 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
185 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 500))]
186 "TARGET_SPE"
187 "evcmpeq %0,%1,%2"
188 [(set_attr "type" "veccmp")
189 (set_attr "length" "4")])
190
191(define_insn "spe_evcmpgts"
192 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
193 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
194 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 501))]
195 "TARGET_SPE"
196 "evcmpgts %0,%1,%2"
197 [(set_attr "type" "veccmp")
198 (set_attr "length" "4")])
199
200(define_insn "spe_evcmpgtu"
201 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
202 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
203 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 502))]
204 "TARGET_SPE"
205 "evcmpgtu %0,%1,%2"
206 [(set_attr "type" "veccmp")
207 (set_attr "length" "4")])
208
209(define_insn "spe_evcmplts"
210 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
211 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
212 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 503))]
213 "TARGET_SPE"
214 "evcmplts %0,%1,%2"
215 [(set_attr "type" "veccmp")
216 (set_attr "length" "4")])
217
218(define_insn "spe_evcmpltu"
219 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
220 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
221 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 504))]
222 "TARGET_SPE"
223 "evcmpltu %0,%1,%2"
224 [(set_attr "type" "veccmp")
225 (set_attr "length" "4")])
226
227;; Floating point vector compare instructions
228
229(define_insn "spe_evfscmpeq"
230 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
231 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
232 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 538))
233 (clobber (reg:SI SPEFSCR_REGNO))]
234 "TARGET_SPE"
235 "evfscmpeq %0,%1,%2"
236 [(set_attr "type" "veccmp")
237 (set_attr "length" "4")])
238
239(define_insn "spe_evfscmpgt"
240 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
241 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
242 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 539))
243 (clobber (reg:SI SPEFSCR_REGNO))]
244 "TARGET_SPE"
245 "evfscmpgt %0,%1,%2"
246 [(set_attr "type" "veccmp")
247 (set_attr "length" "4")])
248
249(define_insn "spe_evfscmplt"
250 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
251 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
252 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 540))
253 (clobber (reg:SI SPEFSCR_REGNO))]
254 "TARGET_SPE"
255 "evfscmplt %0,%1,%2"
256 [(set_attr "type" "veccmp")
257 (set_attr "length" "4")])
258
259(define_insn "spe_evfststeq"
260 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
261 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
262 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 541))]
263 "TARGET_SPE"
264 "evfststeq %0,%1,%2"
265 [(set_attr "type" "veccmp")
266 (set_attr "length" "4")])
267
268(define_insn "spe_evfststgt"
269 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
270 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
271 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 542))]
272 "TARGET_SPE"
273 "evfststgt %0,%1,%2"
274 [(set_attr "type" "veccmp")
275 (set_attr "length" "4")])
276
277(define_insn "spe_evfststlt"
278 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
279 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
280 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 543))]
281 "TARGET_SPE"
282 "evfststlt %0,%1,%2"
283 [(set_attr "type" "veccmp")
284 (set_attr "length" "4")])
285
286;; End of vector compare instructions
287
288(define_insn "spe_evcntlsw"
289 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
290 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 505))]
291 "TARGET_SPE"
292 "evcntlsw %0,%1"
293 [(set_attr "type" "vecsimple")
294 (set_attr "length" "4")])
295
296(define_insn "spe_evcntlzw"
297 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
298 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 506))]
299 "TARGET_SPE"
300 "evcntlzw %0,%1"
301 [(set_attr "type" "vecsimple")
302 (set_attr "length" "4")])
303
304(define_insn "spe_eveqv"
305 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
306 (not:V2SI (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
307 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
308 "TARGET_SPE"
309 "eveqv %0,%1,%2"
310 [(set_attr "type" "vecsimple")
311 (set_attr "length" "4")])
312
313(define_insn "spe_evextsb"
314 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
315 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 507))]
316 "TARGET_SPE"
317 "evextsb %0,%1"
318 [(set_attr "type" "vecsimple")
319 (set_attr "length" "4")])
320
321(define_insn "spe_evextsh"
322 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
323 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 508))]
324 "TARGET_SPE"
325 "evextsh %0,%1"
326 [(set_attr "type" "vecsimple")
327 (set_attr "length" "4")])
328
329(define_insn "spe_evlhhesplat"
626098f9
AH		 330 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
331 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
a3170dc6
AH		 332 (match_operand:QI 2 "immediate_operand" "i"))))
333 (unspec [(const_int 0)] 509)]
626098f9
AH		 334 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
335 "evlhhesplat %0,%2*2(%1)"
a3170dc6
AH		 336 [(set_attr "type" "vecload")
337 (set_attr "length" "4")])
338
339(define_insn "spe_evlhhesplatx"
340 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
341 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
342 (match_operand:SI 2 "gpc_reg_operand" "r"))))
343 (unspec [(const_int 0)] 510)]
344 "TARGET_SPE"
345 "evlhhesplatx %0,%1,%2"
346 [(set_attr "type" "vecload")
347 (set_attr "length" "4")])
348
349(define_insn "spe_evlhhossplat"
350 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
351 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
352 (match_operand:QI 2 "immediate_operand" "i"))))
353 (unspec [(const_int 0)] 511)]
626098f9
AH		 354 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
355 "evlhhossplat %0,%2*2(%1)"
a3170dc6
AH		 356 [(set_attr "type" "vecload")
357 (set_attr "length" "4")])
358
359(define_insn "spe_evlhhossplatx"
360 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
361 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
362 (match_operand:SI 2 "gpc_reg_operand" "r"))))
363 (unspec [(const_int 0)] 512)]
364 "TARGET_SPE"
365 "evlhhossplatx %0,%1,%2"
366 [(set_attr "type" "vecload")
367 (set_attr "length" "4")])
368
369(define_insn "spe_evlhhousplat"
370 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
371 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
372 (match_operand:QI 2 "immediate_operand" "i"))))
373 (unspec [(const_int 0)] 513)]
626098f9
AH		 374 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
375 "evlhhousplat %0,%2*2(%1)"
a3170dc6
AH		 376 [(set_attr "type" "vecload")
377 (set_attr "length" "4")])
378
379(define_insn "spe_evlhhousplatx"
380 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
381 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
382 (match_operand:SI 2 "gpc_reg_operand" "r"))))
383 (unspec [(const_int 0)] 514)]
384 "TARGET_SPE"
385 "evlhhousplatx %0,%1,%2"
386 [(set_attr "type" "vecload")
387 (set_attr "length" "4")])
388
389(define_insn "spe_evlwhsplat"
390 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
391 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
392 (match_operand:QI 2 "immediate_operand" "i"))))
393 (unspec [(const_int 0)] 515)]
626098f9
AH		 394 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
395 "evlwhsplat %0,%2*4(%1)"
a3170dc6
AH		 396 [(set_attr "type" "vecload")
397 (set_attr "length" "4")])
398
399(define_insn "spe_evlwhsplatx"
400 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
401 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
402 (match_operand:SI 2 "gpc_reg_operand" "r"))))
403 (unspec [(const_int 0)] 516)]
404 "TARGET_SPE"
405 "evlwhsplatx %0,%1,%2"
406 [(set_attr "type" "vecload")
407 (set_attr "length" "4")])
408
409(define_insn "spe_evlwwsplat"
410 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
411 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
412 (match_operand:QI 2 "immediate_operand" "i"))))
413 (unspec [(const_int 0)] 517)]
626098f9
AH		 414 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
415 "evlwwsplat %0,%2*4(%1)"
a3170dc6
AH		 416 [(set_attr "type" "vecload")
417 (set_attr "length" "4")])
418
419(define_insn "spe_evlwwsplatx"
420 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
421 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
422 (match_operand:SI 2 "gpc_reg_operand" "r"))))
423 (unspec [(const_int 0)] 518)]
424 "TARGET_SPE"
425 "evlwwsplatx %0,%1,%2"
426 [(set_attr "type" "vecload")
427 (set_attr "length" "4")])
428
429(define_insn "spe_evmergehi"
430 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
431 (vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
432 (vec_select:V2SI
433 (match_operand:V2SI 2 "gpc_reg_operand" "r")
434 (parallel [(const_int 1)
435 (const_int 0)]))
436 (const_int 2)))]
437 "TARGET_SPE"
438 "evmergehi %0,%1,%2"
439 [(set_attr "type" "vecsimple")
440 (set_attr "length" "4")])
441
442(define_insn "spe_evmergehilo"
443 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
444 (vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
445 (match_operand:V2SI 2 "gpc_reg_operand" "r")
446 (const_int 2)))]
447 "TARGET_SPE"
448 "evmergehilo %0,%1,%2"
449 [(set_attr "type" "vecsimple")
450 (set_attr "length" "4")])
451
452(define_insn "spe_evmergelo"
453 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
454 (vec_merge:V2SI (vec_select:V2SI
455 (match_operand:V2SI 1 "gpc_reg_operand" "r")
456 (parallel [(const_int 1)
457 (const_int 0)]))
458 (match_operand:V2SI 2 "gpc_reg_operand" "r")
459 (const_int 2)))]
460 "TARGET_SPE"
461 "evmergelo %0,%1,%2"
462 [(set_attr "type" "vecsimple")
463 (set_attr "length" "4")])
464
465(define_insn "spe_evmergelohi"
466 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
467 (vec_merge:V2SI (vec_select:V2SI
468 (match_operand:V2SI 1 "gpc_reg_operand" "r")
469 (parallel [(const_int 1)
470 (const_int 0)]))
471 (vec_select:V2SI
472 (match_operand:V2SI 2 "gpc_reg_operand" "r")
473 (parallel [(const_int 1)
474 (const_int 0)]))
475 (const_int 2)))]
476 "TARGET_SPE"
477 "evmergelohi %0,%1,%2"
478 [(set_attr "type" "vecsimple")
479 (set_attr "length" "4")])
480
481(define_insn "spe_evnand"
482 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
483 (not:V2SI (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
484 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
485 "TARGET_SPE"
486 "evnand %0,%1,%2"
487 [(set_attr "type" "vecsimple")
488 (set_attr "length" "4")])
489
6a599451 490(define_insn "negv2si2"
a3170dc6
AH		 491 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
492 (neg:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
493 "TARGET_SPE"
494 "evneg %0,%1"
495 [(set_attr "type" "vecsimple")
496 (set_attr "length" "4")])
497
498(define_insn "spe_evnor"
499 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
500 (not:V2SI (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
501 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
502 "TARGET_SPE"
503 "evnor %0,%1,%2"
504 [(set_attr "type" "vecsimple")
505 (set_attr "length" "4")])
506
507(define_insn "spe_evorc"
508 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
509 (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
510 (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
511 "TARGET_SPE"
512 "evorc %0,%1,%2"
513 [(set_attr "type" "vecsimple")
514 (set_attr "length" "4")])
515
516(define_insn "spe_evor"
517 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
518 (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
519 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
520 "TARGET_SPE"
521 "evor %0,%1,%2"
522 [(set_attr "type" "vecsimple")
523 (set_attr "length" "4")])
524
525(define_insn "spe_evrlwi"
526 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
527 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
528 (match_operand:QI 2 "immediate_operand" "i")] 519))]
529 "TARGET_SPE"
78872ad9 530 "evrlwi %0,%1,%2"
a3170dc6
AH		 531 [(set_attr "type" "vecsimple")
532 (set_attr "length" "4")])
533
534(define_insn "spe_evrlw"
535 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
536 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
537 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 520))]
538 "TARGET_SPE"
539 "evrlw %0,%1,%2"
540 [(set_attr "type" "veccomplex")
541 (set_attr "length" "4")])
542
543(define_insn "spe_evrndw"
544 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
545 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 521))]
546 "TARGET_SPE"
547 "evrndw %0,%1"
548 [(set_attr "type" "vecsimple")
549 (set_attr "length" "4")])
550
551(define_insn "spe_evsel"
552 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
553 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
554 (match_operand:V2SI 2 "gpc_reg_operand" "r")
555 (match_operand:CC 3 "cc_reg_operand" "y")] 522))]
556 "TARGET_SPE"
557 "evsel %0,%1,%2,%3"
558 [(set_attr "type" "veccmp")
559 (set_attr "length" "4")])
560
561(define_insn "spe_evsel_fs"
562 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
563 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")
564 (match_operand:V2SF 2 "gpc_reg_operand" "r")
565 (match_operand:CC 3 "cc_reg_operand" "y")] 725))]
566 "TARGET_SPE"
567 "evsel %0,%1,%2,%3"
568 [(set_attr "type" "veccmp")
569 (set_attr "length" "4")])
570
571(define_insn "spe_evslwi"
572 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
573 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
574 (match_operand:QI 2 "immediate_operand" "i")]
575 523))]
576 "TARGET_SPE"
577 "evslwi %0,%1,%2"
578 [(set_attr "type" "vecsimple")
579 (set_attr "length" "4")])
580
581(define_insn "spe_evslw"
582 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
583 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
584 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 524))]
585 "TARGET_SPE"
586 "evslw %0,%1,%2"
587 [(set_attr "type" "vecsimple")
588 (set_attr "length" "4")])
589
590(define_insn "spe_evsrwis"
591 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
592 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
593 (match_operand:QI 2 "immediate_operand" "i")]
594 525))]
595 "TARGET_SPE"
596 "evsrwis %0,%1,%2"
597 [(set_attr "type" "vecsimple")
598 (set_attr "length" "4")])
599
600(define_insn "spe_evsrwiu"
601 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
602 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
603 (match_operand:QI 2 "immediate_operand" "i")]
604 526))]
605 "TARGET_SPE"
606 "evsrwiu %0,%1,%2"
607 [(set_attr "type" "vecsimple")
608 (set_attr "length" "4")])
609
610(define_insn "spe_evsrws"
611 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
612 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
613 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 527))]
614 "TARGET_SPE"
615 "evsrws %0,%1,%2"
616 [(set_attr "type" "vecsimple")
617 (set_attr "length" "4")])
618
619(define_insn "spe_evsrwu"
620 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
621 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
622 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 528))]
623 "TARGET_SPE"
624 "evsrwu %0,%1,%2"
625 [(set_attr "type" "vecsimple")
626 (set_attr "length" "4")])
627
626098f9
AH		 628;; vector xors
629
630(define_insn "xorv2si3"
a3170dc6
AH		 631 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
632 (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
633 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
634 "TARGET_SPE"
635 "evxor %0,%1,%2"
636 [(set_attr "type" "vecsimple")
637 (set_attr "length" "4")])
638
626098f9
AH		 639(define_insn "xorv4hi3"
640 [(set (match_operand:V4HI 0 "gpc_reg_operand" "=r")
641 (xor:V4HI (match_operand:V4HI 1 "gpc_reg_operand" "r")
642 (match_operand:V4HI 2 "gpc_reg_operand" "r")))]
643 "TARGET_SPE"
644 "evxor %0,%1,%2"
645 [(set_attr "type" "vecsimple")
646 (set_attr "length" "4")])
647
648(define_insn "xorv1di3"
649 [(set (match_operand:V1DI 0 "gpc_reg_operand" "=r")
650 (xor:V1DI (match_operand:V1DI 1 "gpc_reg_operand" "r")
651 (match_operand:V1DI 2 "gpc_reg_operand" "r")))]
652 "TARGET_SPE"
653 "evxor %0,%1,%2"
654 [(set_attr "type" "vecsimple")
655 (set_attr "length" "4")])
656
657;; end of vector xors
658
a3170dc6
AH		 659(define_insn "spe_evfsabs"
660 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
661 (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
662 "TARGET_SPE"
663 "evfsabs %0,%1"
5e8006fa 664 [(set_attr "type" "vecsimple")
a3170dc6
AH		 665 (set_attr "length" "4")])
666
667(define_insn "spe_evfsadd"
668 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
669 (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
670 (match_operand:V2SF 2 "gpc_reg_operand" "r")))
671 (clobber (reg:SI SPEFSCR_REGNO))]
672 "TARGET_SPE"
673 "evfsadd %0,%1,%2"
674 [(set_attr "type" "vecfloat")
675 (set_attr "length" "4")])
676
677(define_insn "spe_evfscfsf"
678 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
679 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 529))]
680 "TARGET_SPE"
681 "evfscfsf %0,%1"
682 [(set_attr "type" "vecfloat")
683 (set_attr "length" "4")])
684
685(define_insn "spe_evfscfsi"
e7a9b208
AH		 686 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
687 (float:V2SF (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
a3170dc6
AH		 688 "TARGET_SPE"
689 "evfscfsi %0,%1"
690 [(set_attr "type" "vecfloat")
691 (set_attr "length" "4")])
692
693(define_insn "spe_evfscfuf"
694 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
695 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 530))]
696 "TARGET_SPE"
697 "evfscfuf %0,%1"
698 [(set_attr "type" "vecfloat")
699 (set_attr "length" "4")])
700
701(define_insn "spe_evfscfui"
702 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
703 (unspec:V2SF [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 701))]
704 "TARGET_SPE"
705 "evfscfui %0,%1"
706 [(set_attr "type" "vecfloat")
707 (set_attr "length" "4")])
708
709(define_insn "spe_evfsctsf"
710 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
711 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 531))]
712 "TARGET_SPE"
713 "evfsctsf %0,%1"
714 [(set_attr "type" "vecfloat")
715 (set_attr "length" "4")])
716
717(define_insn "spe_evfsctsi"
718 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
719 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 532))]
720 "TARGET_SPE"
721 "evfsctsi %0,%1"
722 [(set_attr "type" "vecfloat")
723 (set_attr "length" "4")])
724
725(define_insn "spe_evfsctsiz"
726 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
727 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 533))]
728 "TARGET_SPE"
729 "evfsctsiz %0,%1"
730 [(set_attr "type" "vecfloat")
731 (set_attr "length" "4")])
732
733(define_insn "spe_evfsctuf"
734 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
735 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 534))]
736 "TARGET_SPE"
737 "evfsctuf %0,%1"
738 [(set_attr "type" "vecfloat")
739 (set_attr "length" "4")])
740
741(define_insn "spe_evfsctui"
742 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
743 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 535))]
744 "TARGET_SPE"
745 "evfsctui %0,%1"
746 [(set_attr "type" "vecfloat")
747 (set_attr "length" "4")])
748
749(define_insn "spe_evfsctuiz"
750 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
751 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 536))]
752 "TARGET_SPE"
753 "evfsctuiz %0,%1"
754 [(set_attr "type" "vecfloat")
755 (set_attr "length" "4")])
756
757(define_insn "spe_evfsdiv"
758 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
759 (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
760 (match_operand:V2SF 2 "gpc_reg_operand" "r")))
761 (clobber (reg:SI SPEFSCR_REGNO))]
762 "TARGET_SPE"
763 "evfsdiv %0,%1,%2"
5e8006fa 764 [(set_attr "type" "vecfdiv")
a3170dc6
AH		 765 (set_attr "length" "4")])
766
767(define_insn "spe_evfsmul"
768 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
769 (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
770 (match_operand:V2SF 2 "gpc_reg_operand" "r")))
771 (clobber (reg:SI SPEFSCR_REGNO))]
772 "TARGET_SPE"
773 "evfsmul %0,%1,%2"
774 [(set_attr "type" "vecfloat")
775 (set_attr "length" "4")])
776
777(define_insn "spe_evfsnabs"
778 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
779 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 537))]
780 "TARGET_SPE"
781 "evfsnabs %0,%1"
5e8006fa 782 [(set_attr "type" "vecsimple")
a3170dc6
AH		 783 (set_attr "length" "4")])
784
785(define_insn "spe_evfsneg"
786 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
787 (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
788 "TARGET_SPE"
789 "evfsneg %0,%1"
5e8006fa 790 [(set_attr "type" "vecsimple")
a3170dc6
AH		 791 (set_attr "length" "4")])
792
793(define_insn "spe_evfssub"
794 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
795 (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
796 (match_operand:V2SF 2 "gpc_reg_operand" "r")))
797 (clobber (reg:SI SPEFSCR_REGNO))]
798 "TARGET_SPE"
799 "evfssub %0,%1,%2"
800 [(set_attr "type" "vecfloat")
801 (set_attr "length" "4")])
802
803;; SPE SIMD load instructions.
804
b6d08ca1 805;; Only the hardware engineer who designed the SPE understands the
a3170dc6
AH		 806;; plethora of load and store instructions ;-). We have no way of
807;; differentiating between them with RTL so use an unspec of const_int 0
808;; to avoid identical RTL.
809
810(define_insn "spe_evldd"
811 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
812 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
813 (match_operand:QI 2 "immediate_operand" "i"))))
814 (unspec [(const_int 0)] 544)]
815 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
626098f9 816 "evldd %0,%2*8(%1)"
a3170dc6
AH		 817 [(set_attr "type" "vecload")
818 (set_attr "length" "4")])
819
820(define_insn "spe_evlddx"
821 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
822 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
823 (match_operand:SI 2 "gpc_reg_operand" "r"))))
824 (unspec [(const_int 0)] 545)]
825 "TARGET_SPE"
826 "evlddx %0,%1,%2"
827 [(set_attr "type" "vecload")
828 (set_attr "length" "4")])
829
830(define_insn "spe_evldh"
831 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
832 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
833 (match_operand:QI 2 "immediate_operand" "i"))))
834 (unspec [(const_int 0)] 546)]
835 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
626098f9 836 "evldh %0,%2*8(%1)"
a3170dc6
AH		 837 [(set_attr "type" "vecload")
838 (set_attr "length" "4")])
839
840(define_insn "spe_evldhx"
841 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
842 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
843 (match_operand:SI 2 "gpc_reg_operand" "r"))))
844 (unspec [(const_int 0)] 547)]
845 "TARGET_SPE"
846 "evldhx %0,%1,%2"
847 [(set_attr "type" "vecload")
848 (set_attr "length" "4")])
849
850(define_insn "spe_evldw"
851 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
852 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
853 (match_operand:QI 2 "immediate_operand" "i"))))
854 (unspec [(const_int 0)] 548)]
626098f9
AH		 855 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
856 "evldw %0,%2*8(%1)"
a3170dc6
AH		 857 [(set_attr "type" "vecload")
858 (set_attr "length" "4")])
859
860(define_insn "spe_evldwx"
861 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
862 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
863 (match_operand:SI 2 "gpc_reg_operand" "r"))))
864 (unspec [(const_int 0)] 549)]
865 "TARGET_SPE"
866 "evldwx %0,%1,%2"
867 [(set_attr "type" "vecload")
868 (set_attr "length" "4")])
869
870(define_insn "spe_evlwhe"
871 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
872 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
873 (match_operand:QI 2 "immediate_operand" "i"))))
874 (unspec [(const_int 0)] 550)]
626098f9
AH		 875 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
876 "evlwhe %0,%2*4(%1)"
a3170dc6
AH		 877 [(set_attr "type" "vecload")
878 (set_attr "length" "4")])
879
880(define_insn "spe_evlwhex"
881 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
882 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
883 (match_operand:SI 2 "gpc_reg_operand" "r"))))
884 (unspec [(const_int 0)] 551)]
885 "TARGET_SPE"
886 "evlwhex %0,%1,%2"
887 [(set_attr "type" "vecload")
888 (set_attr "length" "4")])
889
890(define_insn "spe_evlwhos"
891 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
892 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
893 (match_operand:QI 2 "immediate_operand" "i"))))
894 (unspec [(const_int 0)] 552)]
626098f9
AH		 895 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
896 "evlwhos %0,%2*4(%1)"
a3170dc6
AH		 897 [(set_attr "type" "vecload")
898 (set_attr "length" "4")])
899
900(define_insn "spe_evlwhosx"
901 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
902 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
903 (match_operand:SI 2 "gpc_reg_operand" "r"))))
904 (unspec [(const_int 0)] 553)]
905 "TARGET_SPE"
906 "evlwhosx %0,%1,%2"
907 [(set_attr "type" "vecload")
908 (set_attr "length" "4")])
909
910(define_insn "spe_evlwhou"
911 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
912 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
913 (match_operand:QI 2 "immediate_operand" "i"))))
914 (unspec [(const_int 0)] 554)]
626098f9
AH		 915 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
916 "evlwhou %0,%2*4(%1)"
a3170dc6
AH		 917 [(set_attr "type" "vecload")
918 (set_attr "length" "4")])
919
920(define_insn "spe_evlwhoux"
921 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
922 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
923 (match_operand:SI 2 "gpc_reg_operand" "r"))))
924 (unspec [(const_int 0)] 555)]
925 "TARGET_SPE"
926 "evlwhoux %0,%1,%2"
927 [(set_attr "type" "vecload")
928 (set_attr "length" "4")])
929
930(define_insn "spe_brinc"
931 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
932 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "r")
933 (match_operand:SI 2 "gpc_reg_operand" "r")] 556))]
934 "TARGET_SPE"
935 "brinc %0,%1,%2"
5e8006fa 936 [(set_attr "type" "brinc")
a3170dc6
AH		 937 (set_attr "length" "4")])
938
939(define_insn "spe_evmhegsmfaa"
940 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
941 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
942 (match_operand:V2SI 2 "gpc_reg_operand" "r")
943 (reg:V2SI SPE_ACC_REGNO)] 557))
54da776f 944 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 945 "TARGET_SPE"
946 "evmhegsmfaa %0,%1,%2"
947 [(set_attr "type" "veccomplex")
948 (set_attr "length" "4")])
949
950(define_insn "spe_evmhegsmfan"
951 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
952 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
953 (match_operand:V2SI 2 "gpc_reg_operand" "r")
954 (reg:V2SI SPE_ACC_REGNO)] 558))
54da776f 955 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 956 "TARGET_SPE"
957 "evmhegsmfan %0,%1,%2"
958 [(set_attr "type" "veccomplex")
959 (set_attr "length" "4")])
960
961(define_insn "spe_evmhegsmiaa"
962 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
963 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
964 (match_operand:V2SI 2 "gpc_reg_operand" "r")
965 (reg:V2SI SPE_ACC_REGNO)] 559))
54da776f 966 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 967 "TARGET_SPE"
968 "evmhegsmiaa %0,%1,%2"
969 [(set_attr "type" "veccomplex")
970 (set_attr "length" "4")])
971
972(define_insn "spe_evmhegsmian"
973 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
974 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
975 (match_operand:V2SI 2 "gpc_reg_operand" "r")
976 (reg:V2SI SPE_ACC_REGNO)] 560))
54da776f 977 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 978 "TARGET_SPE"
979 "evmhegsmian %0,%1,%2"
980 [(set_attr "type" "veccomplex")
981 (set_attr "length" "4")])
982
983(define_insn "spe_evmhegumiaa"
984 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
985 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
986 (match_operand:V2SI 2 "gpc_reg_operand" "r")
987 (reg:V2SI SPE_ACC_REGNO)] 561))
54da776f 988 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 989 "TARGET_SPE"
990 "evmhegumiaa %0,%1,%2"
991 [(set_attr "type" "veccomplex")
992 (set_attr "length" "4")])
993
994(define_insn "spe_evmhegumian"
995 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
996 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
997 (match_operand:V2SI 2 "gpc_reg_operand" "r")
998 (reg:V2SI SPE_ACC_REGNO)] 562))
54da776f 999 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1000 "TARGET_SPE"
1001 "evmhegumian %0,%1,%2"
1002 [(set_attr "type" "veccomplex")
1003 (set_attr "length" "4")])
1004
1005(define_insn "spe_evmhesmfaaw"
1006 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1007 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1008 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1009 (reg:V2SI SPE_ACC_REGNO)] 563))
54da776f 1010 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1011 "TARGET_SPE"
1012 "evmhesmfaaw %0,%1,%2"
1013 [(set_attr "type" "veccomplex")
1014 (set_attr "length" "4")])
1015
1016(define_insn "spe_evmhesmfanw"
1017 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1018 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1019 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1020 (reg:V2SI SPE_ACC_REGNO)] 564))
54da776f 1021 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1022 "TARGET_SPE"
1023 "evmhesmfanw %0,%1,%2"
1024 [(set_attr "type" "veccomplex")
1025 (set_attr "length" "4")])
1026
1027(define_insn "spe_evmhesmfa"
1028 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1029 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1030 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 565))
54da776f 1031 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1032 "TARGET_SPE"
1033 "evmhesmfa %0,%1,%2"
1034 [(set_attr "type" "veccomplex")
1035 (set_attr "length" "4")])
1036
1037(define_insn "spe_evmhesmf"
1038 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1039 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1040 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 566))]
1041 "TARGET_SPE"
1042 "evmhesmf %0,%1,%2"
1043 [(set_attr "type" "veccomplex")
1044 (set_attr "length" "4")])
1045
1046(define_insn "spe_evmhesmiaaw"
1047 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1048 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1049 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1050 (reg:V2SI SPE_ACC_REGNO)] 567))
54da776f 1051 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1052 "TARGET_SPE"
1053 "evmhesmiaaw %0,%1,%2"
1054 [(set_attr "type" "veccomplex")
1055 (set_attr "length" "4")])
1056
1057(define_insn "spe_evmhesmianw"
1058 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1059 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1060 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1061 (reg:V2SI SPE_ACC_REGNO)] 568))
54da776f 1062 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1063 "TARGET_SPE"
1064 "evmhesmianw %0,%1,%2"
1065 [(set_attr "type" "veccomplex")
1066 (set_attr "length" "4")])
1067
1068(define_insn "spe_evmhesmia"
1069 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1070 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1071 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 569))
54da776f 1072 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1073 "TARGET_SPE"
1074 "evmhesmia %0,%1,%2"
1075 [(set_attr "type" "veccomplex")
1076 (set_attr "length" "4")])
1077
1078(define_insn "spe_evmhesmi"
1079 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1080 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1081 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 570))]
1082 "TARGET_SPE"
1083 "evmhesmi %0,%1,%2"
1084 [(set_attr "type" "veccomplex")
1085 (set_attr "length" "4")])
1086
1087(define_insn "spe_evmhessfaaw"
1088 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1089 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1090 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1091 (reg:V2SI SPE_ACC_REGNO)] 571))
1092 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1093 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1094 "TARGET_SPE"
1095 "evmhessfaaw %0,%1,%2"
1096 [(set_attr "type" "veccomplex")
1097 (set_attr "length" "4")])
1098
1099(define_insn "spe_evmhessfanw"
1100 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1101 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1102 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1103 (reg:V2SI SPE_ACC_REGNO)] 572))
1104 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1105 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1106 "TARGET_SPE"
1107 "evmhessfanw %0,%1,%2"
1108 [(set_attr "type" "veccomplex")
1109 (set_attr "length" "4")])
1110
1111(define_insn "spe_evmhessfa"
1112 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1113 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1114 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 573))
1115 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1116 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1117 "TARGET_SPE"
1118 "evmhessfa %0,%1,%2"
1119 [(set_attr "type" "veccomplex")
1120 (set_attr "length" "4")])
1121
1122(define_insn "spe_evmhessf"
1123 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1124 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1125 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 574))
1126 (clobber (reg:SI SPEFSCR_REGNO))]
1127 "TARGET_SPE"
1128 "evmhessf %0,%1,%2"
1129 [(set_attr "type" "veccomplex")
1130 (set_attr "length" "4")])
1131
1132(define_insn "spe_evmhessiaaw"
1133 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1134 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1135 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1136 (reg:V2SI SPE_ACC_REGNO)] 575))
1137 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1138 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6 1139 "TARGET_SPE"
c9b93e1a 1140 "evmhessiaaw %0,%1,%2"
a3170dc6
AH		 1141 [(set_attr "type" "veccomplex")
1142 (set_attr "length" "4")])
1143
1144(define_insn "spe_evmhessianw"
1145 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1146 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1147 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1148 (reg:V2SI SPE_ACC_REGNO)] 576))
1149 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1150 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1151 "TARGET_SPE"
1152 "evmhessianw %0,%1,%2"
1153 [(set_attr "type" "veccomplex")
1154 (set_attr "length" "4")])
1155
1156(define_insn "spe_evmheumiaaw"
1157 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1158 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1159 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1160 (reg:V2SI SPE_ACC_REGNO)] 577))
54da776f 1161 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1162 "TARGET_SPE"
1163 "evmheumiaaw %0,%1,%2"
1164 [(set_attr "type" "veccomplex")
1165 (set_attr "length" "4")])
1166
1167(define_insn "spe_evmheumianw"
1168 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1169 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1170 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1171 (reg:V2SI SPE_ACC_REGNO)] 578))
54da776f 1172 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1173 "TARGET_SPE"
1174 "evmheumianw %0,%1,%2"
1175 [(set_attr "type" "veccomplex")
1176 (set_attr "length" "4")])
1177
1178(define_insn "spe_evmheumia"
1179 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1180 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1181 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 579))
54da776f 1182 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1183 "TARGET_SPE"
1184 "evmheumia %0,%1,%2"
1185 [(set_attr "type" "veccomplex")
1186 (set_attr "length" "4")])
1187
1188(define_insn "spe_evmheumi"
1189 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1190 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1191 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 580))]
1192 "TARGET_SPE"
1193 "evmheumi %0,%1,%2"
1194 [(set_attr "type" "veccomplex")
1195 (set_attr "length" "4")])
1196
1197(define_insn "spe_evmheusiaaw"
1198 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1199 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1200 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1201 (reg:V2SI SPE_ACC_REGNO)] 581))
1202 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1203 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1204 "TARGET_SPE"
1205 "evmheusiaaw %0,%1,%2"
1206 [(set_attr "type" "veccomplex")
1207 (set_attr "length" "4")])
1208
1209(define_insn "spe_evmheusianw"
1210 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1211 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1212 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1213 (reg:V2SI SPE_ACC_REGNO)] 582))
1214 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1215 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1216 "TARGET_SPE"
1217 "evmheusianw %0,%1,%2"
1218 [(set_attr "type" "veccomplex")
1219 (set_attr "length" "4")])
1220
1221(define_insn "spe_evmhogsmfaa"
1222 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1223 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1224 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1225 (reg:V2SI SPE_ACC_REGNO)] 583))
54da776f 1226 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1227 "TARGET_SPE"
1228 "evmhogsmfaa %0,%1,%2"
1229 [(set_attr "type" "veccomplex")
1230 (set_attr "length" "4")])
1231
1232(define_insn "spe_evmhogsmfan"
1233 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1234 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1235 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1236 (reg:V2SI SPE_ACC_REGNO)] 584))
54da776f 1237 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1238 "TARGET_SPE"
1239 "evmhogsmfan %0,%1,%2"
1240 [(set_attr "type" "veccomplex")
1241 (set_attr "length" "4")])
1242
1243(define_insn "spe_evmhogsmiaa"
1244 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1245 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1246 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1247 (reg:V2SI SPE_ACC_REGNO)] 585))
54da776f 1248 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1249 "TARGET_SPE"
1250 "evmhogsmiaa %0,%1,%2"
1251 [(set_attr "type" "veccomplex")
1252 (set_attr "length" "4")])
1253
1254(define_insn "spe_evmhogsmian"
1255 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1256 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1257 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1258 (reg:V2SI SPE_ACC_REGNO)] 586))
54da776f 1259 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1260 "TARGET_SPE"
1261 "evmhogsmian %0,%1,%2"
1262 [(set_attr "type" "veccomplex")
1263 (set_attr "length" "4")])
1264
1265(define_insn "spe_evmhogumiaa"
1266 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1267 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1268 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1269 (reg:V2SI SPE_ACC_REGNO)] 587))
54da776f 1270 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1271 "TARGET_SPE"
1272 "evmhogumiaa %0,%1,%2"
1273 [(set_attr "type" "veccomplex")
1274 (set_attr "length" "4")])
1275
1276(define_insn "spe_evmhogumian"
1277 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1278 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1279 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1280 (reg:V2SI SPE_ACC_REGNO)] 588))
54da776f 1281 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1282 "TARGET_SPE"
1283 "evmhogumian %0,%1,%2"
1284 [(set_attr "type" "veccomplex")
1285 (set_attr "length" "4")])
1286
1287(define_insn "spe_evmhosmfaaw"
1288 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1289 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1290 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1291 (reg:V2SI SPE_ACC_REGNO)] 589))
54da776f 1292 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1293 "TARGET_SPE"
1294 "evmhosmfaaw %0,%1,%2"
1295 [(set_attr "type" "veccomplex")
1296 (set_attr "length" "4")])
1297
1298(define_insn "spe_evmhosmfanw"
1299 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1300 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1301 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1302 (reg:V2SI SPE_ACC_REGNO)] 590))
54da776f 1303 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1304 "TARGET_SPE"
1305 "evmhosmfanw %0,%1,%2"
1306 [(set_attr "type" "veccomplex")
1307 (set_attr "length" "4")])
1308
1309(define_insn "spe_evmhosmfa"
1310 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1311 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1312 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 591))]
1313 "TARGET_SPE"
1314 "evmhosmfa %0,%1,%2"
1315 [(set_attr "type" "veccomplex")
1316 (set_attr "length" "4")])
1317
1318(define_insn "spe_evmhosmf"
1319 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1320 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1321 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 592))
54da776f 1322 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1323 "TARGET_SPE"
1324 "evmhosmf %0,%1,%2"
1325 [(set_attr "type" "veccomplex")
1326 (set_attr "length" "4")])
1327
1328(define_insn "spe_evmhosmiaaw"
1329 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1330 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1331 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1332 (reg:V2SI SPE_ACC_REGNO)] 593))
54da776f 1333 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1334 "TARGET_SPE"
1335 "evmhosmiaaw %0,%1,%2"
1336 [(set_attr "type" "veccomplex")
1337 (set_attr "length" "4")])
1338
1339(define_insn "spe_evmhosmianw"
1340 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1341 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1342 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1343 (reg:V2SI SPE_ACC_REGNO)] 594))
54da776f 1344 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1345 "TARGET_SPE"
1346 "evmhosmianw %0,%1,%2"
1347 [(set_attr "type" "veccomplex")
1348 (set_attr "length" "4")])
1349
1350(define_insn "spe_evmhosmia"
1351 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1352 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1353 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 595))
54da776f 1354 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1355 "TARGET_SPE"
1356 "evmhosmia %0,%1,%2"
1357 [(set_attr "type" "veccomplex")
1358 (set_attr "length" "4")])
1359
1360(define_insn "spe_evmhosmi"
1361 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1362 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1363 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 596))]
1364 "TARGET_SPE"
1365 "evmhosmi %0,%1,%2"
1366 [(set_attr "type" "veccomplex")
1367 (set_attr "length" "4")])
1368
1369(define_insn "spe_evmhossfaaw"
1370 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1371 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1372 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1373 (reg:V2SI SPE_ACC_REGNO)] 597))
1374 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1375 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1376 "TARGET_SPE"
1377 "evmhossfaaw %0,%1,%2"
1378 [(set_attr "type" "veccomplex")
1379 (set_attr "length" "4")])
1380
1381(define_insn "spe_evmhossfanw"
1382 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1383 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1384 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1385 (reg:V2SI SPE_ACC_REGNO)] 598))
1386 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1387 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1388 "TARGET_SPE"
1389 "evmhossfanw %0,%1,%2"
1390 [(set_attr "type" "veccomplex")
1391 (set_attr "length" "4")])
1392
1393(define_insn "spe_evmhossfa"
1394 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1395 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1396 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1397 (reg:V2SI SPE_ACC_REGNO)] 599))
1398 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1399 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1400 "TARGET_SPE"
1401 "evmhossfa %0,%1,%2"
1402 [(set_attr "type" "veccomplex")
1403 (set_attr "length" "4")])
1404
1405(define_insn "spe_evmhossf"
1406 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1407 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1408 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 600))
1409 (clobber (reg:SI SPEFSCR_REGNO))]
1410 "TARGET_SPE"
1411 "evmhossf %0,%1,%2"
1412 [(set_attr "type" "veccomplex")
1413 (set_attr "length" "4")])
1414
1415(define_insn "spe_evmhossiaaw"
1416 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1417 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1418 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1419 (reg:V2SI SPE_ACC_REGNO)] 601))
1420 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1421 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1422 "TARGET_SPE"
1423 "evmhossiaaw %0,%1,%2"
1424 [(set_attr "type" "veccomplex")
1425 (set_attr "length" "4")])
1426
1427(define_insn "spe_evmhossianw"
1428 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1429 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1430 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1431 (reg:V2SI SPE_ACC_REGNO)] 602))
1432 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1433 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1434 "TARGET_SPE"
1435 "evmhossianw %0,%1,%2"
1436 [(set_attr "type" "veccomplex")
1437 (set_attr "length" "4")])
1438
1439(define_insn "spe_evmhoumiaaw"
1440 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1441 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1442 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1443 (reg:V2SI SPE_ACC_REGNO)] 603))
54da776f 1444 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1445 "TARGET_SPE"
1446 "evmhoumiaaw %0,%1,%2"
1447 [(set_attr "type" "veccomplex")
1448 (set_attr "length" "4")])
1449
1450(define_insn "spe_evmhoumianw"
1451 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1452 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1453 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1454 (reg:V2SI SPE_ACC_REGNO)] 604))
54da776f 1455 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1456 "TARGET_SPE"
1457 "evmhoumianw %0,%1,%2"
1458 [(set_attr "type" "veccomplex")
1459 (set_attr "length" "4")])
1460
1461(define_insn "spe_evmhoumia"
1462 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1463 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1464 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 605))
54da776f 1465 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1466 "TARGET_SPE"
1467 "evmhoumia %0,%1,%2"
1468 [(set_attr "type" "veccomplex")
1469 (set_attr "length" "4")])
1470
1471(define_insn "spe_evmhoumi"
1472 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1473 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1474 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 606))]
1475 "TARGET_SPE"
1476 "evmhoumi %0,%1,%2"
1477 [(set_attr "type" "veccomplex")
1478 (set_attr "length" "4")])
1479
1480(define_insn "spe_evmhousiaaw"
1481 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1482 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1483 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1484 (reg:V2SI SPE_ACC_REGNO)] 607))
1485 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1486 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1487 "TARGET_SPE"
1488 "evmhousiaaw %0,%1,%2"
1489 [(set_attr "type" "veccomplex")
1490 (set_attr "length" "4")])
1491
1492(define_insn "spe_evmhousianw"
1493 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1494 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1495 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1496 (reg:V2SI SPE_ACC_REGNO)] 608))
1497 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1498 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1499 "TARGET_SPE"
1500 "evmhousianw %0,%1,%2"
1501 [(set_attr "type" "veccomplex")
1502 (set_attr "length" "4")])
1503
1504(define_insn "spe_evmmlssfa"
1505 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1506 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1507 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 609))]
1508 "TARGET_SPE"
1509 "evmmlssfa %0,%1,%2"
1510 [(set_attr "type" "veccomplex")
1511 (set_attr "length" "4")])
1512
1513(define_insn "spe_evmmlssf"
1514 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1515 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1516 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 610))]
1517 "TARGET_SPE"
1518 "evmmlssf %0,%1,%2"
1519 [(set_attr "type" "veccomplex")
1520 (set_attr "length" "4")])
1521
1522(define_insn "spe_evmwhsmfa"
1523 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1524 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1525 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 611))
54da776f 1526 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1527 "TARGET_SPE"
1528 "evmwhsmfa %0,%1,%2"
1529 [(set_attr "type" "veccomplex")
1530 (set_attr "length" "4")])
1531
1532(define_insn "spe_evmwhsmf"
1533 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1534 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1535 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 612))]
1536 "TARGET_SPE"
1537 "evmwhsmf %0,%1,%2"
1538 [(set_attr "type" "veccomplex")
1539 (set_attr "length" "4")])
1540
1541(define_insn "spe_evmwhsmia"
1542 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1543 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1544 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 613))
54da776f 1545 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1546 "TARGET_SPE"
1547 "evmwhsmia %0,%1,%2"
1548 [(set_attr "type" "veccomplex")
1549 (set_attr "length" "4")])
1550
1551(define_insn "spe_evmwhsmi"
1552 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1553 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1554 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 614))]
1555 "TARGET_SPE"
1556 "evmwhsmi %0,%1,%2"
1557 [(set_attr "type" "veccomplex")
1558 (set_attr "length" "4")])
1559
1560(define_insn "spe_evmwhssfa"
1561 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1562 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1563 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 615))
1564 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1565 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1566 "TARGET_SPE"
1567 "evmwhssfa %0,%1,%2"
1568 [(set_attr "type" "veccomplex")
1569 (set_attr "length" "4")])
1570
1571(define_insn "spe_evmwhusian"
1572 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1573 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1574 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 626))]
1575 "TARGET_SPE"
1576 "evmwhusian %0,%1,%2"
1577 [(set_attr "type" "veccomplex")
1578 (set_attr "length" "4")])
1579
1580(define_insn "spe_evmwhssf"
1581 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1582 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1583 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 628))
1584 (clobber (reg:SI SPEFSCR_REGNO))]
1585 "TARGET_SPE"
1586 "evmwhssf %0,%1,%2"
1587 [(set_attr "type" "veccomplex")
1588 (set_attr "length" "4")])
1589
1590(define_insn "spe_evmwhumia"
1591 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1592 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1593 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 629))
54da776f 1594 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1595 "TARGET_SPE"
1596 "evmwhumia %0,%1,%2"
1597 [(set_attr "type" "veccomplex")
1598 (set_attr "length" "4")])
1599
1600(define_insn "spe_evmwhumi"
1601 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1602 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1603 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 630))]
1604 "TARGET_SPE"
1605 "evmwhumi %0,%1,%2"
1606 [(set_attr "type" "veccomplex")
1607 (set_attr "length" "4")])
1608
a3170dc6
AH		 1609(define_insn "spe_evmwlsmiaaw"
1610 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1611 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1612 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1613 (reg:V2SI SPE_ACC_REGNO)] 635))
54da776f 1614 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1615 "TARGET_SPE"
1616 "evmwlsmiaaw %0,%1,%2"
1617 [(set_attr "type" "veccomplex")
1618 (set_attr "length" "4")])
1619
1620(define_insn "spe_evmwlsmianw"
1621 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1622 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1623 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1624 (reg:V2SI SPE_ACC_REGNO)] 636))
54da776f 1625 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1626 "TARGET_SPE"
1627 "evmwlsmianw %0,%1,%2"
a3170dc6
AH		 1628 [(set_attr "type" "veccomplex")
1629 (set_attr "length" "4")])
1630
1631(define_insn "spe_evmwlssiaaw"
1632 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1633 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1634 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1635 (reg:V2SI SPE_ACC_REGNO)] 641))
1636 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1637 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1638 "TARGET_SPE"
1639 "evmwlssiaaw %0,%1,%2"
1640 [(set_attr "type" "veccomplex")
1641 (set_attr "length" "4")])
1642
1643(define_insn "spe_evmwlssianw"
1644 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1645 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1646 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1647 (reg:V2SI SPE_ACC_REGNO)] 642))
1648 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1649 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1650 "TARGET_SPE"
1651 "evmwlssianw %0,%1,%2"
1652 [(set_attr "type" "veccomplex")
1653 (set_attr "length" "4")])
1654
1655(define_insn "spe_evmwlumiaaw"
1656 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1657 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1658 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1659 (reg:V2SI SPE_ACC_REGNO)] 643))
54da776f 1660 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1661 "TARGET_SPE"
1662 "evmwlumiaaw %0,%1,%2"
1663 [(set_attr "type" "veccomplex")
1664 (set_attr "length" "4")])
1665
1666(define_insn "spe_evmwlumianw"
1667 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1668 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1669 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1670 (reg:V2SI SPE_ACC_REGNO)] 644))
54da776f 1671 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1672 "TARGET_SPE"
1673 "evmwlumianw %0,%1,%2"
1674 [(set_attr "type" "veccomplex")
1675 (set_attr "length" "4")])
1676
1677(define_insn "spe_evmwlumia"
1678 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1679 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1680 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 645))
54da776f 1681 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1682 "TARGET_SPE"
1683 "evmwlumia %0,%1,%2"
1684 [(set_attr "type" "veccomplex")
1685 (set_attr "length" "4")])
1686
1687(define_insn "spe_evmwlumi"
1688 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1689 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1690 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 646))]
1691 "TARGET_SPE"
1692 "evmwlumi %0,%1,%2"
1693 [(set_attr "type" "veccomplex")
1694 (set_attr "length" "4")])
1695
1696(define_insn "spe_evmwlusiaaw"
1697 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1698 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1699 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1700 (reg:V2SI SPE_ACC_REGNO)] 647))
1701 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1702 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1703 "TARGET_SPE"
1704 "evmwlusiaaw %0,%1,%2"
1705 [(set_attr "type" "veccomplex")
1706 (set_attr "length" "4")])
1707
1708(define_insn "spe_evmwlusianw"
1709 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1710 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1711 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1712 (reg:V2SI SPE_ACC_REGNO)] 648))
1713 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1714 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1715 "TARGET_SPE"
1716 "evmwlusianw %0,%1,%2"
1717 [(set_attr "type" "veccomplex")
1718 (set_attr "length" "4")])
1719
1720(define_insn "spe_evmwsmfaa"
1721 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1722 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1723 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1724 (reg:V2SI SPE_ACC_REGNO)] 649))
54da776f 1725 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1726 "TARGET_SPE"
1727 "evmwsmfaa %0,%1,%2"
1728 [(set_attr "type" "veccomplex")
1729 (set_attr "length" "4")])
1730
1731(define_insn "spe_evmwsmfan"
1732 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1733 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1734 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1735 (reg:V2SI SPE_ACC_REGNO)] 650))
54da776f 1736 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1737 "TARGET_SPE"
1738 "evmwsmfan %0,%1,%2"
1739 [(set_attr "type" "veccomplex")
1740 (set_attr "length" "4")])
1741
1742(define_insn "spe_evmwsmfa"
1743 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1744 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1745 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 651))
54da776f 1746 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1747 "TARGET_SPE"
1748 "evmwsmfa %0,%1,%2"
1749 [(set_attr "type" "veccomplex")
1750 (set_attr "length" "4")])
1751
1752(define_insn "spe_evmwsmf"
1753 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1754 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1755 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 652))]
1756 "TARGET_SPE"
1757 "evmwsmf %0,%1,%2"
1758 [(set_attr "type" "veccomplex")
1759 (set_attr "length" "4")])
1760
1761(define_insn "spe_evmwsmiaa"
1762 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1763 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1764 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1765 (reg:V2SI SPE_ACC_REGNO)] 653))
54da776f 1766 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1767 "TARGET_SPE"
1768 "evmwsmiaa %0,%1,%2"
1769 [(set_attr "type" "veccomplex")
1770 (set_attr "length" "4")])
1771
1772(define_insn "spe_evmwsmian"
1773 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1774 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1775 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1776 (reg:V2SI SPE_ACC_REGNO)] 654))
54da776f 1777 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1778 "TARGET_SPE"
1779 "evmwsmian %0,%1,%2"
1780 [(set_attr "type" "veccomplex")
1781 (set_attr "length" "4")])
1782
1783(define_insn "spe_evmwsmia"
1784 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1785 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1786 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 655))
54da776f 1787 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1788 "TARGET_SPE"
1789 "evmwsmia %0,%1,%2"
1790 [(set_attr "type" "veccomplex")
1791 (set_attr "length" "4")])
1792
1793(define_insn "spe_evmwsmi"
1794 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1795 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1796 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 656))]
1797 "TARGET_SPE"
1798 "evmwsmi %0,%1,%2"
1799 [(set_attr "type" "veccomplex")
1800 (set_attr "length" "4")])
1801
1802(define_insn "spe_evmwssfaa"
1803 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1804 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1805 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1806 (reg:V2SI SPE_ACC_REGNO)] 657))
1807 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1808 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1809 "TARGET_SPE"
1810 "evmwssfaa %0,%1,%2"
1811 [(set_attr "type" "veccomplex")
1812 (set_attr "length" "4")])
1813
1814(define_insn "spe_evmwssfan"
1815 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1816 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1817 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1818 (reg:V2SI SPE_ACC_REGNO)] 658))
1819 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1820 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1821 "TARGET_SPE"
1822 "evmwssfan %0,%1,%2"
1823 [(set_attr "type" "veccomplex")
1824 (set_attr "length" "4")])
1825
1826(define_insn "spe_evmwssfa"
1827 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1828 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1829 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 659))
1830 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1831 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1832 "TARGET_SPE"
1833 "evmwssfa %0,%1,%2"
1834 [(set_attr "type" "veccomplex")
1835 (set_attr "length" "4")])
1836
1837(define_insn "spe_evmwssf"
1838 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1839 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1840 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 660))
1841 (clobber (reg:SI SPEFSCR_REGNO))]
1842 "TARGET_SPE"
1843 "evmwssf %0,%1,%2"
1844 [(set_attr "type" "veccomplex")
1845 (set_attr "length" "4")])
1846
1847(define_insn "spe_evmwumiaa"
1848 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1849 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1850 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1851 (reg:V2SI SPE_ACC_REGNO)] 661))
54da776f 1852 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1853 "TARGET_SPE"
1854 "evmwumiaa %0,%1,%2"
1855 [(set_attr "type" "veccomplex")
1856 (set_attr "length" "4")])
1857
1858(define_insn "spe_evmwumian"
1859 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1860 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1861 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1862 (reg:V2SI SPE_ACC_REGNO)] 662))
54da776f 1863 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1864 "TARGET_SPE"
1865 "evmwumian %0,%1,%2"
1866 [(set_attr "type" "veccomplex")
1867 (set_attr "length" "4")])
1868
1869(define_insn "spe_evmwumia"
1870 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1871 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1872 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 663))
54da776f 1873 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1874 "TARGET_SPE"
1875 "evmwumia %0,%1,%2"
1876 [(set_attr "type" "veccomplex")
1877 (set_attr "length" "4")])
1878
1879(define_insn "spe_evmwumi"
1880 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1881 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1882 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 664))]
1883 "TARGET_SPE"
1884 "evmwumi %0,%1,%2"
1885 [(set_attr "type" "veccomplex")
1886 (set_attr "length" "4")])
1887
1888(define_insn "spe_evaddw"
1889 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1890 (plus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
1891 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
1892 "TARGET_SPE"
1893 "evaddw %0,%1,%2"
5e8006fa 1894 [(set_attr "type" "vecsimple")
a3170dc6
AH		 1895 (set_attr "length" "4")])
1896
1897(define_insn "spe_evaddusiaaw"
1898 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1899 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1900 (reg:V2SI SPE_ACC_REGNO)] 673))
1901 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1902 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1903 "TARGET_SPE"
1904 "evaddusiaaw %0,%1"
1905 [(set_attr "type" "veccomplex")
1906 (set_attr "length" "4")])
1907
1908(define_insn "spe_evaddumiaaw"
1909 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1910 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1911 (reg:V2SI SPE_ACC_REGNO)] 674))
54da776f 1912 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1913 "TARGET_SPE"
1914 "evaddumiaaw %0,%1"
1915 [(set_attr "type" "veccomplex")
1916 (set_attr "length" "4")])
1917
1918(define_insn "spe_evaddssiaaw"
1919 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1920 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1921 (reg:V2SI SPE_ACC_REGNO)] 675))
1922 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1923 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1924 "TARGET_SPE"
1925 "evaddssiaaw %0,%1"
1926 [(set_attr "type" "veccomplex")
1927 (set_attr "length" "4")])
1928
1929(define_insn "spe_evaddsmiaaw"
1930 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1931 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1932 (reg:V2SI SPE_ACC_REGNO)] 676))
54da776f 1933 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1934 "TARGET_SPE"
1935 "evaddsmiaaw %0,%1"
1936 [(set_attr "type" "veccomplex")
1937 (set_attr "length" "4")])
1938
1939(define_insn "spe_evaddiw"
1940 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1941 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1942 (match_operand:QI 2 "immediate_operand" "i")] 677))]
1943 "TARGET_SPE"
1944 "evaddiw %0,%1,%2"
5e8006fa 1945 [(set_attr "type" "vecsimple")
a3170dc6
AH		 1946 (set_attr "length" "4")])
1947
1948(define_insn "spe_evsubifw"
1949 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1950 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1951 (match_operand:QI 2 "immediate_operand" "i")] 678))]
1952 "TARGET_SPE"
1953 "evsubifw %0,%2,%1"
1954 [(set_attr "type" "veccomplex")
1955 (set_attr "length" "4")])
1956
1957(define_insn "spe_evsubfw"
1958 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1959 (minus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
1960 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
1961 "TARGET_SPE"
12850cf2 1962 "evsubfw %0,%2,%1"
a3170dc6
AH		 1963 [(set_attr "type" "veccomplex")
1964 (set_attr "length" "4")])
1965
1966(define_insn "spe_evsubfusiaaw"
1967 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1968 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1969 (reg:V2SI SPE_ACC_REGNO)] 679))
1970 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1971 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1972 "TARGET_SPE"
1973 "evsubfusiaaw %0,%1"
1974 [(set_attr "type" "veccomplex")
1975 (set_attr "length" "4")])
1976
1977(define_insn "spe_evsubfumiaaw"
1978 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1979 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1980 (reg:V2SI SPE_ACC_REGNO)] 680))
54da776f 1981 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1982 "TARGET_SPE"
1983 "evsubfumiaaw %0,%1"
1984 [(set_attr "type" "veccomplex")
1985 (set_attr "length" "4")])
1986
1987(define_insn "spe_evsubfssiaaw"
1988 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1989 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1990 (reg:V2SI SPE_ACC_REGNO)] 681))
1991 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1992 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1993 "TARGET_SPE"
1994 "evsubfssiaaw %0,%1"
1995 [(set_attr "type" "veccomplex")
1996 (set_attr "length" "4")])
1997
1998(define_insn "spe_evsubfsmiaaw"
1999 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2000 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2001 (reg:V2SI SPE_ACC_REGNO)] 682))
54da776f 2002 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2003 "TARGET_SPE"
2004 "evsubfsmiaaw %0,%1"
2005 [(set_attr "type" "veccomplex")
2006 (set_attr "length" "4")])
2007
2008(define_insn "spe_evmra"
2009 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2010 (match_operand:V2SI 1 "gpc_reg_operand" "r"))
c3021e5d
AH		 2011 (set (reg:V2SI SPE_ACC_REGNO)
2012 (unspec:V2SI [(match_dup 1)] 726))]
a3170dc6
AH		 2013 "TARGET_SPE"
2014 "evmra %0,%1"
2015 [(set_attr "type" "veccomplex")
2016 (set_attr "length" "4")])
2017
2018(define_insn "spe_evdivws"
2019 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2020 (div:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
2021 (match_operand:V2SI 2 "gpc_reg_operand" "r")))
2022 (clobber (reg:SI SPEFSCR_REGNO))]
2023 "TARGET_SPE"
2024 "evdivws %0,%1,%2"
5e8006fa 2025 [(set_attr "type" "vecdiv")
a3170dc6
AH		 2026 (set_attr "length" "4")])
2027
2028(define_insn "spe_evdivwu"
2029 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2030 (udiv:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
2031 (match_operand:V2SI 2 "gpc_reg_operand" "r")))
2032 (clobber (reg:SI SPEFSCR_REGNO))]
2033 "TARGET_SPE"
2034 "evdivwu %0,%1,%2"
5e8006fa 2035 [(set_attr "type" "vecdiv")
a3170dc6
AH		 2036 (set_attr "length" "4")])
2037
2038(define_insn "spe_evsplatfi"
2039 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2040 (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 684))]
2041 "TARGET_SPE"
c9b93e1a 2042 "evsplatfi %0,%1"
a3170dc6
AH		 2043 [(set_attr "type" "vecperm")
2044 (set_attr "length" "4")])
2045
2046(define_insn "spe_evsplati"
2047 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2048 (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 685))]
2049 "TARGET_SPE"
c9b93e1a 2050 "evsplati %0,%1"
a3170dc6
AH		 2051 [(set_attr "type" "vecperm")
2052 (set_attr "length" "4")])
2053
2054(define_insn "spe_evstdd"
2055 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2056 (match_operand:QI 1 "immediate_operand" "i")))
2057 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2058 (unspec [(const_int 0)] 686)]
626098f9
AH		 2059 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2060 "evstdd %2,%1*8(%0)"
a3170dc6
AH		 2061 [(set_attr "type" "vecstore")
2062 (set_attr "length" "4")])
2063
2064(define_insn "spe_evstddx"
2065 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2066 (match_operand:SI 1 "gpc_reg_operand" "r")))
2067 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2068 (unspec [(const_int 0)] 687)]
2069 "TARGET_SPE"
2070 "evstddx %2,%0,%1"
2071 [(set_attr "type" "vecstore")
2072 (set_attr "length" "4")])
2073
2074(define_insn "spe_evstdh"
2075 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2076 (match_operand:QI 1 "immediate_operand" "i")))
2077 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2078 (unspec [(const_int 0)] 688)]
626098f9
AH		 2079 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2080 "evstdh %2,%1*8(%0)"
a3170dc6
AH		 2081 [(set_attr "type" "vecstore")
2082 (set_attr "length" "4")])
2083
2084(define_insn "spe_evstdhx"
2085 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2086 (match_operand:SI 1 "gpc_reg_operand" "r")))
2087 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2088 (unspec [(const_int 0)] 689)]
2089 "TARGET_SPE"
2090 "evstdhx %2,%0,%1"
2091 [(set_attr "type" "vecstore")
2092 (set_attr "length" "4")])
2093
2094(define_insn "spe_evstdw"
2095 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2096 (match_operand:QI 1 "immediate_operand" "i")))
2097 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2098 (unspec [(const_int 0)] 690)]
626098f9
AH		 2099 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2100 "evstdw %2,%1*8(%0)"
a3170dc6
AH		 2101 [(set_attr "type" "vecstore")
2102 (set_attr "length" "4")])
2103
2104(define_insn "spe_evstdwx"
2105 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2106 (match_operand:SI 1 "gpc_reg_operand" "r")))
2107 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2108 (unspec [(const_int 0)] 691)]
2109 "TARGET_SPE"
2110 "evstdwx %2,%0,%1"
2111 [(set_attr "type" "vecstore")
2112 (set_attr "length" "4")])
2113
2114(define_insn "spe_evstwhe"
2115 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2116 (match_operand:QI 1 "immediate_operand" "i")))
2117 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2118 (unspec [(const_int 0)] 692)]
626098f9
AH		 2119 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2120 "evstwhe %2,%1*4(%0)"
a3170dc6
AH		 2121 [(set_attr "type" "vecstore")
2122 (set_attr "length" "4")])
2123
2124(define_insn "spe_evstwhex"
2125 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2126 (match_operand:SI 1 "gpc_reg_operand" "r")))
2127 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2128 (unspec [(const_int 0)] 693)]
2129 "TARGET_SPE"
2130 "evstwhex %2,%0,%1"
2131 [(set_attr "type" "vecstore")
2132 (set_attr "length" "4")])
2133
2134(define_insn "spe_evstwho"
2135 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2136 (match_operand:QI 1 "immediate_operand" "i")))
2137 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2138 (unspec [(const_int 0)] 694)]
626098f9
AH		 2139 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2140 "evstwho %2,%1*4(%0)"
a3170dc6
AH		 2141 [(set_attr "type" "vecstore")
2142 (set_attr "length" "4")])
2143
2144(define_insn "spe_evstwhox"
2145 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2146 (match_operand:SI 1 "gpc_reg_operand" "r")))
2147 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2148 (unspec [(const_int 0)] 695)]
2149 "TARGET_SPE"
2150 "evstwhox %2,%0,%1"
2151 [(set_attr "type" "vecstore")
2152 (set_attr "length" "4")])
2153
2154(define_insn "spe_evstwwe"
2155 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2156 (match_operand:QI 1 "immediate_operand" "i")))
2157 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2158 (unspec [(const_int 0)] 696)]
626098f9
AH		 2159 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2160 "evstwwe %2,%1*4(%0)"
a3170dc6
AH		 2161 [(set_attr "type" "vecstore")
2162 (set_attr "length" "4")])
2163
2164(define_insn "spe_evstwwex"
2165 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2166 (match_operand:SI 1 "gpc_reg_operand" "r")))
2167 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2168 (unspec [(const_int 0)] 697)]
2169 "TARGET_SPE"
2170 "evstwwex %2,%0,%1"
2171 [(set_attr "type" "vecstore")
2172 (set_attr "length" "4")])
2173
2174(define_insn "spe_evstwwo"
2175 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2176 (match_operand:QI 1 "immediate_operand" "i")))
2177 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2178 (unspec [(const_int 0)] 698)]
626098f9
AH		 2179 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2180 "evstwwo %2,%1*4(%0)"
a3170dc6
AH		 2181 [(set_attr "type" "vecstore")
2182 (set_attr "length" "4")])
2183
2184(define_insn "spe_evstwwox"
2185 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2186 (match_operand:SI 1 "gpc_reg_operand" "r")))
2187 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2188 (unspec [(const_int 0)] 699)]
2189 "TARGET_SPE"
2190 "evstwwox %2,%0,%1"
2191 [(set_attr "type" "vecstore")
2192 (set_attr "length" "4")])
2193
7a2f7870 2194;; Double-precision floating point instructions.
54b695e7
AH		 2195
2196;; FIXME: Add o=r option.
2197(define_insn "*frob_df_di"
2198 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r")
2199 (subreg:DF (match_operand:DI 1 "input_operand" "r,m") 0))]
2200 "TARGET_E500_DOUBLE"
2201 "@
2202 evmergelo %0,%H1,%L1
2203 evldd%X1 %0,%y1")
2204
2205(define_insn "*frob_di_df"
2206 [(set (match_operand:DI 0 "nonimmediate_operand" "=&r")
2207 (subreg:DI (match_operand:DF 1 "input_operand" "r") 0))]
2208 "TARGET_E500_DOUBLE" /*one of these can be an mr */
2209 "evmergehi %H0,%1,%1\;evmergelo %L0,%1,%1"
2210 [(set_attr "length" "8")])
2211
2212(define_insn "*frob_di_df_2"
2213 [(set (subreg:DF (match_operand:DI 0 "register_operand" "=&r") 0)
2214 (match_operand:DF 1 "register_operand" "r"))]
2215 "TARGET_E500_DOUBLE"
2216 "evmergehi %H0,%1,%1\;evmergelo %L0,%1,%1"
2217 [(set_attr "length" "8")])
2218
2219(define_insn "*mov_sidf_e500_subreg0"
2220 [(set (subreg:SI (match_operand:DF 0 "register_operand" "+r") 0)
2221 (match_operand:SI 1 "register_operand" "r"))]
2222 "TARGET_E500_DOUBLE"
2223 "evmergelo %0,%1,%0")
2224
2225(define_insn "*mov_sidf_e500_subreg4"
2226 [(set (subreg:SI (match_operand:DF 0 "register_operand" "+r") 4)
2227 (match_operand:SI 1 "register_operand" "r"))]
2228 "TARGET_E500_DOUBLE"
2229 "mr %0,%1")
2230
2231;; FIXME: Allow r=CONST0.
7a2f7870 2232(define_insn "*movdf_e500_double"
165a5bad 2233 [(set (match_operand:DF 0 "rs6000_nonimmediate_operand" "=r,r,m")
7a2f7870
AH		 2234 (match_operand:DF 1 "input_operand" "r,m,r"))]
2235 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
2236 && (gpc_reg_operand (operands[0], DFmode)
2237 || gpc_reg_operand (operands[1], DFmode))"
2238 "*
2239 {
2240 switch (which_alternative)
2241 {
2242 case 0:
2243 return \"evor %0,%1,%1\";
2244 case 1:
2245 return \"evldd%X1 %0,%y1\";
2246 case 2:
2247 return \"evstdd%X0 %1,%y0\";
2248 default:
2249 abort ();
2250 }
2251 }"
2252 [(set_attr "type" "*,vecload,vecstore")
2253 (set_attr "length" "*,*,*")])
2254
2255(define_insn "spe_truncdfsf2"
2256 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
2257 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "r")))]
2258 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2259 "efscfd %0,%1")
2260
2261(define_insn "spe_absdf2"
2262 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2263 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
2264 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2265 "efdabs %0,%1")
2266
2267(define_insn "spe_nabsdf2"
2268 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2269 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r"))))]
2270 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2271 "efdnabs %0,%1")
2272
2273(define_insn "spe_negdf2"
2274 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2275 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
2276 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2277 "efdneg %0,%1")
2278
2279(define_insn "spe_adddf3"
2280 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2281 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2282 (match_operand:DF 2 "gpc_reg_operand" "r")))]
2283 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2284 "efdadd %0,%1,%2")
2285
2286(define_insn "spe_subdf3"
2287 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2288 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2289 (match_operand:DF 2 "gpc_reg_operand" "r")))]
2290 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2291 "efdsub %0,%1,%2")
2292
2293(define_insn "spe_muldf3"
2294 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2295 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2296 (match_operand:DF 2 "gpc_reg_operand" "r")))]
2297 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2298 "efdmul %0,%1,%2")
2299
2300(define_insn "spe_divdf3"
2301 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2302 (div:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2303 (match_operand:DF 2 "gpc_reg_operand" "r")))]
2304 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2305 "efddiv %0,%1,%2")
2306
a3170dc6
AH		 2307;; Vector move instructions.
2308
2309(define_expand "movv2si"
2310 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
2311 (match_operand:V2SI 1 "any_operand" ""))]
2312 "TARGET_SPE"
2313 "{ rs6000_emit_move (operands[0], operands[1], V2SImode); DONE; }")
2314
a3170dc6 2315(define_insn "*movv2si_internal"
d744e06e
AH		 2316 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=m,r,r,r")
2317 (match_operand:V2SI 1 "input_operand" "r,m,r,W"))]
e66b2fcf
AH		 2318 "TARGET_SPE
2319 && (gpc_reg_operand (operands[0], V2SImode)
2320 || gpc_reg_operand (operands[1], V2SImode))"
d744e06e
AH		 2321 "*
2322{
2323 switch (which_alternative)
2324 {
2325 case 0: return \"evstdd%X0 %1,%y0\";
2326 case 1: return \"evldd%X1 %0,%y1\";
2327 case 2: return \"evor %0,%1,%1\";
2328 case 3: return output_vec_const_move (operands);
2329 default: abort ();
2330 }
2331}"
2332 [(set_attr "type" "vecload,vecstore,*,*")
2333 (set_attr "length" "*,*,*,12")])
2334
2335(define_split
2336 [(set (match_operand:V2SI 0 "register_operand" "")
2337 (match_operand:V2SI 1 "zero_constant" ""))]
2338 "TARGET_SPE && reload_completed"
2339 [(set (match_dup 0)
2340 (xor:V2SI (match_dup 0) (match_dup 0)))]
2341 "")
a3170dc6 2342
00a892b8
NC		 2343(define_expand "movv1di"
2344 [(set (match_operand:V1DI 0 "nonimmediate_operand" "")
2345 (match_operand:V1DI 1 "any_operand" ""))]
2346 "TARGET_SPE"
2347 "{ rs6000_emit_move (operands[0], operands[1], V1DImode); DONE; }")
2348
2349(define_insn "*movv1di_internal"
d744e06e
AH		 2350 [(set (match_operand:V1DI 0 "nonimmediate_operand" "=m,r,r,r")
2351 (match_operand:V1DI 1 "input_operand" "r,m,r,W"))]
e66b2fcf
AH		 2352 "TARGET_SPE
2353 && (gpc_reg_operand (operands[0], V1DImode)
2354 || gpc_reg_operand (operands[1], V1DImode))"
00a892b8
NC		 2355 "@
2356 evstdd%X0 %1,%y0
2357 evldd%X1 %0,%y1
d744e06e
AH		 2358 evor %0,%1,%1
2359 evxor %0,%0,%0"
2360 [(set_attr "type" "vecload,vecstore,*,*")
2361 (set_attr "length" "*,*,*,*")])
00a892b8 2362
a3170dc6
AH		 2363(define_expand "movv4hi"
2364 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
2365 (match_operand:V4HI 1 "any_operand" ""))]
2366 "TARGET_SPE"
2367 "{ rs6000_emit_move (operands[0], operands[1], V4HImode); DONE; }")
2368
2369(define_insn "*movv4hi_internal"
2370 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=m,r,r")
2371 (match_operand:V4HI 1 "input_operand" "r,m,r"))]
e66b2fcf
AH		 2372 "TARGET_SPE
2373 && (gpc_reg_operand (operands[0], V4HImode)
2374 || gpc_reg_operand (operands[1], V4HImode))"
a3170dc6
AH		 2375 "@
2376 evstdd%X0 %1,%y0
2377 evldd%X1 %0,%y1
2378 evor %0,%1,%1"
d744e06e 2379 [(set_attr "type" "vecload")])
a3170dc6
AH		 2380
2381(define_expand "movv2sf"
2382 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
2383 (match_operand:V2SF 1 "any_operand" ""))]
2384 "TARGET_SPE"
2385 "{ rs6000_emit_move (operands[0], operands[1], V2SFmode); DONE; }")
2386
2387(define_insn "*movv2sf_internal"
d744e06e
AH		 2388 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,r,r,r")
2389 (match_operand:V2SF 1 "input_operand" "r,m,r,W"))]
e66b2fcf
AH		 2390 "TARGET_SPE
2391 && (gpc_reg_operand (operands[0], V2SFmode)
2392 || gpc_reg_operand (operands[1], V2SFmode))"
a3170dc6
AH		 2393 "@
2394 evstdd%X0 %1,%y0
2395 evldd%X1 %0,%y1
d744e06e
AH		 2396 evor %0,%1,%1
2397 evxor %0,%0,%0"
2398 [(set_attr "type" "vecload,vecstore,*,*")
2399 (set_attr "length" "*,*,*,*")])
a3170dc6 2400
e66b2fcf
AH		 2401;; End of vector move instructions.
2402
a3170dc6
AH		 2403(define_insn "spe_evmwhssfaa"
2404 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2405 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2406 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 702))
2407 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2408 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2409 "TARGET_SPE"
2410 "evmwhssfaa %0,%1,%2"
2411 [(set_attr "type" "veccomplex")
2412 (set_attr "length" "4")])
2413
2414(define_insn "spe_evmwhssmaa"
2415 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2416 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2417 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 703))
2418 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2419 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2420 "TARGET_SPE"
2421 "evmwhssmaa %0,%1,%2"
2422 [(set_attr "type" "veccomplex")
2423 (set_attr "length" "4")])
2424
2425(define_insn "spe_evmwhsmfaa"
2426 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2427 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2428 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 704))
54da776f 2429 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2430 "TARGET_SPE"
2431 "evmwhsmfaa %0,%1,%2"
2432 [(set_attr "type" "veccomplex")
2433 (set_attr "length" "4")])
2434
2435(define_insn "spe_evmwhsmiaa"
2436 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2437 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2438 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 705))
54da776f 2439 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2440 "TARGET_SPE"
2441 "evmwhsmiaa %0,%1,%2"
2442 [(set_attr "type" "veccomplex")
2443 (set_attr "length" "4")])
2444
2445(define_insn "spe_evmwhusiaa"
2446 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2447 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2448 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 706))
2449 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2450 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2451 "TARGET_SPE"
2452 "evmwhusiaa %0,%1,%2"
2453 [(set_attr "type" "veccomplex")
2454 (set_attr "length" "4")])
2455
2456(define_insn "spe_evmwhumiaa"
2457 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2458 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2459 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 707))
54da776f 2460 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2461 "TARGET_SPE"
2462 "evmwhumiaa %0,%1,%2"
2463 [(set_attr "type" "veccomplex")
2464 (set_attr "length" "4")])
2465
2466(define_insn "spe_evmwhssfan"
2467 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2468 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2469 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 708))
2470 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2471 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2472 "TARGET_SPE"
2473 "evmwhssfan %0,%1,%2"
2474 [(set_attr "type" "veccomplex")
2475 (set_attr "length" "4")])
2476
2477(define_insn "spe_evmwhssian"
2478 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2479 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2480 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 709))
2481 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2482 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2483 "TARGET_SPE"
2484 "evmwhssian %0,%1,%2"
2485 [(set_attr "type" "veccomplex")
2486 (set_attr "length" "4")])
2487
2488(define_insn "spe_evmwhsmfan"
2489 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2490 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2491 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 710))
54da776f 2492 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2493 "TARGET_SPE"
2494 "evmwhsmfan %0,%1,%2"
2495 [(set_attr "type" "veccomplex")
2496 (set_attr "length" "4")])
2497
2498(define_insn "spe_evmwhsmian"
2499 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2500 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2501 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 711))
54da776f 2502 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2503 "TARGET_SPE"
2504 "evmwhsmian %0,%1,%2"
2505 [(set_attr "type" "veccomplex")
2506 (set_attr "length" "4")])
2507
2508(define_insn "spe_evmwhumian"
2509 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2510 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2511 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 713))
54da776f 2512 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2513 "TARGET_SPE"
2514 "evmwhumian %0,%1,%2"
2515 [(set_attr "type" "veccomplex")
2516 (set_attr "length" "4")])
2517
2518(define_insn "spe_evmwhgssfaa"
2519 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2520 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2521 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 714))
2522 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2523 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2524 "TARGET_SPE"
2525 "evmwhgssfaa %0,%1,%2"
2526 [(set_attr "type" "veccomplex")
2527 (set_attr "length" "4")])
2528
2529(define_insn "spe_evmwhgsmfaa"
2530 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2531 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2532 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 715))
54da776f 2533 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2534 "TARGET_SPE"
2535 "evmwhgsmfaa %0,%1,%2"
2536 [(set_attr "type" "veccomplex")
2537 (set_attr "length" "4")])
2538
2539(define_insn "spe_evmwhgsmiaa"
2540 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2541 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2542 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 716))
54da776f 2543 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2544 "TARGET_SPE"
2545 "evmwhgsmiaa %0,%1,%2"
2546 [(set_attr "type" "veccomplex")
2547 (set_attr "length" "4")])
2548
2549(define_insn "spe_evmwhgumiaa"
2550 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2551 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2552 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 717))
54da776f 2553 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2554 "TARGET_SPE"
2555 "evmwhgumiaa %0,%1,%2"
2556 [(set_attr "type" "veccomplex")
2557 (set_attr "length" "4")])
2558
2559(define_insn "spe_evmwhgssfan"
2560 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2561 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2562 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 718))
2563 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2564 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2565 "TARGET_SPE"
2566 "evmwhgssfan %0,%1,%2"
2567 [(set_attr "type" "veccomplex")
2568 (set_attr "length" "4")])
2569
2570(define_insn "spe_evmwhgsmfan"
2571 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2572 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2573 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 719))
54da776f 2574 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2575 "TARGET_SPE"
2576 "evmwhgsmfan %0,%1,%2"
2577 [(set_attr "type" "veccomplex")
2578 (set_attr "length" "4")])
2579
2580(define_insn "spe_evmwhgsmian"
2581 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2582 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2583 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 720))
54da776f 2584 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2585 "TARGET_SPE"
2586 "evmwhgsmian %0,%1,%2"
2587 [(set_attr "type" "veccomplex")
2588 (set_attr "length" "4")])
2589
2590(define_insn "spe_evmwhgumian"
2591 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2592 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2593 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 721))
54da776f 2594 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2595 "TARGET_SPE"
2596 "evmwhgumian %0,%1,%2"
2597 [(set_attr "type" "veccomplex")
2598 (set_attr "length" "4")])
2599
2600(define_insn "spe_mtspefscr"
2601 [(set (reg:SI SPEFSCR_REGNO)
2602 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2603 722))]
2604 "TARGET_SPE"
2605 "mtspefscr %0"
2606 [(set_attr "type" "vecsimple")])
2607
2608(define_insn "spe_mfspefscr"
2609 [(set (match_operand:SI 0 "register_operand" "=r")
2610 (unspec_volatile:SI [(reg:SI SPEFSCR_REGNO)] 723))]
2611 "TARGET_SPE"
2612 "mfspefscr %0"
2613 [(set_attr "type" "vecsimple")])
2614
423c1189
AH		 2615;; FP comparison stuff.
2616
423c1189 2617;; Flip the GT bit.
6b1fedc3 2618(define_insn "e500_flip_eq_bit"
423c1189
AH		 2619 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2620 (unspec:CCFP
2621 [(match_operand:CCFP 1 "cc_reg_operand" "y")] 999))]
2622 "!TARGET_FPRS && TARGET_HARD_FLOAT"
2623 "*
2624{
6b1fedc3 2625 return output_e500_flip_eq_bit (operands[0], operands[1]);
423c1189
AH		 2626}"
2627 [(set_attr "type" "cr_logical")])
2628
a3170dc6
AH		 2629;; MPC8540 single-precision FP instructions on GPRs.
2630;; We have 2 variants for each. One for IEEE compliant math and one
2631;; for non IEEE compliant math.
2632
2633(define_insn "cmpsfeq_gpr"
2634 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
423c1189
AH		 2635 (unspec:CCFP
2636 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2637 (match_operand:SF 2 "gpc_reg_operand" "r"))]
2638 1000))]
a3170dc6
AH		 2639 "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
2640 "efscmpeq %0,%1,%2"
5e8006fa 2641 [(set_attr "type" "veccmp")])
a3170dc6
AH		 2642
2643(define_insn "tstsfeq_gpr"
2644 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
423c1189
AH		 2645 (unspec:CCFP
2646 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2647 (match_operand:SF 2 "gpc_reg_operand" "r"))]
2648 1001))]
a3170dc6
AH		 2649 "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
2650 "efststeq %0,%1,%2"
5e8006fa 2651 [(set_attr "type" "veccmpsimple")])
a3170dc6
AH		 2652
2653(define_insn "cmpsfgt_gpr"
2654 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
423c1189
AH		 2655 (unspec:CCFP
2656 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2657 (match_operand:SF 2 "gpc_reg_operand" "r"))]
2658 1002))]
a3170dc6
AH		 2659 "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
2660 "efscmpgt %0,%1,%2"
5e8006fa 2661 [(set_attr "type" "veccmp")])
a3170dc6
AH		 2662
2663(define_insn "tstsfgt_gpr"
2664 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
423c1189
AH		 2665 (unspec:CCFP
2666 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2667 (match_operand:SF 2 "gpc_reg_operand" "r"))]
2668 1003))]
a3170dc6
AH		 2669 "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
2670 "efststgt %0,%1,%2"
5e8006fa 2671 [(set_attr "type" "veccmpsimple")])
a3170dc6
AH		 2672
2673(define_insn "cmpsflt_gpr"
2674 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
423c1189
AH		 2675 (unspec:CCFP
2676 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2677 (match_operand:SF 2 "gpc_reg_operand" "r"))]
2678 1004))]
a3170dc6
AH		 2679 "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
2680 "efscmplt %0,%1,%2"
5e8006fa 2681 [(set_attr "type" "veccmp")])
a3170dc6
AH		 2682
2683(define_insn "tstsflt_gpr"
2684 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
423c1189
AH		 2685 (unspec:CCFP
2686 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2687 (match_operand:SF 2 "gpc_reg_operand" "r"))]
f350ff00 2688 1005))]
a3170dc6
AH		 2689 "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
2690 "efststlt %0,%1,%2"
5e8006fa 2691 [(set_attr "type" "veccmpsimple")])
4d4cbc0e
AH		 2692
2693;; Same thing, but for double-precision.
2694
2695(define_insn "cmpdfeq_gpr"
2696 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2697 (unspec:CCFP
2698 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
2699 (match_operand:DF 2 "gpc_reg_operand" "r"))]
2700 CMPDFEQ_GPR))]
2701 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations"
2702 "efdcmpeq %0,%1,%2"
2703 [(set_attr "type" "veccmp")])
2704
2705(define_insn "tstdfeq_gpr"
2706 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2707 (unspec:CCFP
2708 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
2709 (match_operand:DF 2 "gpc_reg_operand" "r"))]
2710 TSTDFEQ_GPR))]
2711 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations"
2712 "efdtsteq %0,%1,%2"
2713 [(set_attr "type" "veccmpsimple")])
2714
2715(define_insn "cmpdfgt_gpr"
2716 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2717 (unspec:CCFP
2718 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
2719 (match_operand:DF 2 "gpc_reg_operand" "r"))]
2720 CMPDFGT_GPR))]
2721 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations"
2722 "efdcmpgt %0,%1,%2"
2723 [(set_attr "type" "veccmp")])
2724
2725(define_insn "tstdfgt_gpr"
2726 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2727 (unspec:CCFP
2728 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
2729 (match_operand:DF 2 "gpc_reg_operand" "r"))]
2730 TSTDFGT_GPR))]
2731 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations"
2732 "efdtstgt %0,%1,%2"
2733 [(set_attr "type" "veccmpsimple")])
2734
2735(define_insn "cmpdflt_gpr"
2736 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2737 (unspec:CCFP
2738 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
2739 (match_operand:DF 2 "gpc_reg_operand" "r"))]
2740 CMPDFLT_GPR))]
2741 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations"
2742 "efdcmplt %0,%1,%2"
2743 [(set_attr "type" "veccmp")])
2744
2745(define_insn "tstdflt_gpr"
2746 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2747 (unspec:CCFP
2748 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
2749 (match_operand:DF 2 "gpc_reg_operand" "r"))]
2750 TSTDFLT_GPR))]
2751 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations"
2752 "efdtstlt %0,%1,%2"
2753 [(set_attr "type" "veccmpsimple")])
Mirror of https://gcc.gnu.org/git/gcc.git