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simd-4.c (main): Make expected value endian-dependent.
[thirdparty/gcc.git] / gcc / config / rs6000 / spe.md
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a3170dc6 1;; e500 SPE description
b6d08ca1 2;; Copyright (C) 2002, 2003 Free Software Foundation, Inc.
a3170dc6
AH		 3;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
4
5de601cf 5;; This file is part of GCC.
a3170dc6 6
5de601cf
NC		 7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
9;; by the Free Software Foundation; either version 2, or (at your
10;; option) any later version.
a3170dc6 11
5de601cf
NC		 12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15;; License for more details.
a3170dc6
AH		 16
17;; You should have received a copy of the GNU General Public License
5de601cf
NC		 18;; along with GCC; see the file COPYING. If not, write to the
19;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
20;; MA 02111-1307, USA.
a3170dc6
AH		 21
22(define_constants
23 [(SPE_ACC_REGNO 111)
24 (SPEFSCR_REGNO 112)])
25
26(define_insn "*negsf2_gpr"
27 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
28 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
29 "TARGET_HARD_FLOAT && !TARGET_FPRS"
30 "efsneg %0,%1"
5e8006fa 31 [(set_attr "type" "fpsimple")])
a3170dc6
AH		 32
33(define_insn "*abssf2_gpr"
34 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
35 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
36 "TARGET_HARD_FLOAT && !TARGET_FPRS"
37 "efsabs %0,%1"
5e8006fa 38 [(set_attr "type" "fpsimple")])
a3170dc6
AH		 39
40(define_insn "*addsf3_gpr"
41 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
42 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
43 (match_operand:SF 2 "gpc_reg_operand" "r")))]
44 "TARGET_HARD_FLOAT && !TARGET_FPRS"
45 "efsadd %0,%1,%2"
46 [(set_attr "type" "fp")])
47
48(define_insn "*subsf3_gpr"
49 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
50 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "r")
51 (match_operand:SF 2 "gpc_reg_operand" "r")))]
52 "TARGET_HARD_FLOAT && !TARGET_FPRS"
53 "efssub %0,%1,%2"
54 [(set_attr "type" "fp")])
55
56(define_insn "*mulsf3_gpr"
57 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
58 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
59 (match_operand:SF 2 "gpc_reg_operand" "r")))]
60 "TARGET_HARD_FLOAT && !TARGET_FPRS"
61 "efsmul %0,%1,%2"
62 [(set_attr "type" "fp")])
63
64(define_insn "*divsf3_gpr"
65 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
66 (div:SF (match_operand:SF 1 "gpc_reg_operand" "r")
67 (match_operand:SF 2 "gpc_reg_operand" "r")))]
68 "TARGET_HARD_FLOAT && !TARGET_FPRS"
69 "efsdiv %0,%1,%2"
5e8006fa 70 [(set_attr "type" "vecfdiv")])
a3170dc6
AH		 71
72(define_insn "spe_efsctuiz"
73 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
74 (unspec:SI [(match_operand:SF 1 "gpc_reg_operand" "r")] 700))]
75 "TARGET_HARD_FLOAT && !TARGET_FPRS"
76 "efsctuiz %0,%1"
77 [(set_attr "type" "fp")])
78
79(define_insn "spe_fixunssfsi2"
80 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
81 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "gpc_reg_operand" "r"))))]
82 "TARGET_HARD_FLOAT && !TARGET_FPRS"
83 "efsctui %0,%1"
84 [(set_attr "type" "fp")])
85
86(define_insn "spe_fix_truncsfsi2"
87 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
88 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
89 "TARGET_HARD_FLOAT && !TARGET_FPRS"
90 "efsctsi %0,%1"
91 [(set_attr "type" "fp")])
92
93(define_insn "spe_floatunssisf2"
94 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
95 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
96 "TARGET_HARD_FLOAT && !TARGET_FPRS"
97 "efscfui %0,%1"
98 [(set_attr "type" "fp")])
99
100(define_insn "spe_floatsisf2"
101 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
102 (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
103 "TARGET_HARD_FLOAT && !TARGET_FPRS"
104 "efscfsi %0,%1"
105 [(set_attr "type" "fp")])
106
107
108;; SPE SIMD instructions
109
110(define_insn "spe_evabs"
111 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
112 (abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
113 "TARGET_SPE"
114 "evabs %0,%1"
115 [(set_attr "type" "vecsimple")
116 (set_attr "length" "4")])
117
118(define_insn "spe_evandc"
119 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
120 (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
121 (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
122 "TARGET_SPE"
123 "evandc %0,%1,%2"
124 [(set_attr "type" "vecsimple")
125 (set_attr "length" "4")])
126
127(define_insn "spe_evand"
128 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
129 (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
130 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
131 "TARGET_SPE"
132 "evand %0,%1,%2"
133 [(set_attr "type" "vecsimple")
134 (set_attr "length" "4")])
135
136;; Vector compare instructions
137
138(define_insn "spe_evcmpeq"
139 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
140 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
141 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 500))]
142 "TARGET_SPE"
143 "evcmpeq %0,%1,%2"
144 [(set_attr "type" "veccmp")
145 (set_attr "length" "4")])
146
147(define_insn "spe_evcmpgts"
148 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
149 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
150 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 501))]
151 "TARGET_SPE"
152 "evcmpgts %0,%1,%2"
153 [(set_attr "type" "veccmp")
154 (set_attr "length" "4")])
155
156(define_insn "spe_evcmpgtu"
157 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
158 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
159 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 502))]
160 "TARGET_SPE"
161 "evcmpgtu %0,%1,%2"
162 [(set_attr "type" "veccmp")
163 (set_attr "length" "4")])
164
165(define_insn "spe_evcmplts"
166 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
167 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
168 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 503))]
169 "TARGET_SPE"
170 "evcmplts %0,%1,%2"
171 [(set_attr "type" "veccmp")
172 (set_attr "length" "4")])
173
174(define_insn "spe_evcmpltu"
175 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
176 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
177 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 504))]
178 "TARGET_SPE"
179 "evcmpltu %0,%1,%2"
180 [(set_attr "type" "veccmp")
181 (set_attr "length" "4")])
182
183;; Floating point vector compare instructions
184
185(define_insn "spe_evfscmpeq"
186 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
187 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
188 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 538))
189 (clobber (reg:SI SPEFSCR_REGNO))]
190 "TARGET_SPE"
191 "evfscmpeq %0,%1,%2"
192 [(set_attr "type" "veccmp")
193 (set_attr "length" "4")])
194
195(define_insn "spe_evfscmpgt"
196 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
197 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
198 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 539))
199 (clobber (reg:SI SPEFSCR_REGNO))]
200 "TARGET_SPE"
201 "evfscmpgt %0,%1,%2"
202 [(set_attr "type" "veccmp")
203 (set_attr "length" "4")])
204
205(define_insn "spe_evfscmplt"
206 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
207 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
208 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 540))
209 (clobber (reg:SI SPEFSCR_REGNO))]
210 "TARGET_SPE"
211 "evfscmplt %0,%1,%2"
212 [(set_attr "type" "veccmp")
213 (set_attr "length" "4")])
214
215(define_insn "spe_evfststeq"
216 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
217 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
218 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 541))]
219 "TARGET_SPE"
220 "evfststeq %0,%1,%2"
221 [(set_attr "type" "veccmp")
222 (set_attr "length" "4")])
223
224(define_insn "spe_evfststgt"
225 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
226 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
227 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 542))]
228 "TARGET_SPE"
229 "evfststgt %0,%1,%2"
230 [(set_attr "type" "veccmp")
231 (set_attr "length" "4")])
232
233(define_insn "spe_evfststlt"
234 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
235 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
236 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 543))]
237 "TARGET_SPE"
238 "evfststlt %0,%1,%2"
239 [(set_attr "type" "veccmp")
240 (set_attr "length" "4")])
241
242;; End of vector compare instructions
243
244(define_insn "spe_evcntlsw"
245 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
246 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 505))]
247 "TARGET_SPE"
248 "evcntlsw %0,%1"
249 [(set_attr "type" "vecsimple")
250 (set_attr "length" "4")])
251
252(define_insn "spe_evcntlzw"
253 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
254 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 506))]
255 "TARGET_SPE"
256 "evcntlzw %0,%1"
257 [(set_attr "type" "vecsimple")
258 (set_attr "length" "4")])
259
260(define_insn "spe_eveqv"
261 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
262 (not:V2SI (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
263 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
264 "TARGET_SPE"
265 "eveqv %0,%1,%2"
266 [(set_attr "type" "vecsimple")
267 (set_attr "length" "4")])
268
269(define_insn "spe_evextsb"
270 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
271 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 507))]
272 "TARGET_SPE"
273 "evextsb %0,%1"
274 [(set_attr "type" "vecsimple")
275 (set_attr "length" "4")])
276
277(define_insn "spe_evextsh"
278 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
279 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 508))]
280 "TARGET_SPE"
281 "evextsh %0,%1"
282 [(set_attr "type" "vecsimple")
283 (set_attr "length" "4")])
284
285(define_insn "spe_evlhhesplat"
626098f9
AH		 286 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
287 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
a3170dc6
AH		 288 (match_operand:QI 2 "immediate_operand" "i"))))
289 (unspec [(const_int 0)] 509)]
626098f9
AH		 290 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
291 "evlhhesplat %0,%2*2(%1)"
a3170dc6
AH		 292 [(set_attr "type" "vecload")
293 (set_attr "length" "4")])
294
295(define_insn "spe_evlhhesplatx"
296 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
297 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
298 (match_operand:SI 2 "gpc_reg_operand" "r"))))
299 (unspec [(const_int 0)] 510)]
300 "TARGET_SPE"
301 "evlhhesplatx %0,%1,%2"
302 [(set_attr "type" "vecload")
303 (set_attr "length" "4")])
304
305(define_insn "spe_evlhhossplat"
306 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
307 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
308 (match_operand:QI 2 "immediate_operand" "i"))))
309 (unspec [(const_int 0)] 511)]
626098f9
AH		 310 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
311 "evlhhossplat %0,%2*2(%1)"
a3170dc6
AH		 312 [(set_attr "type" "vecload")
313 (set_attr "length" "4")])
314
315(define_insn "spe_evlhhossplatx"
316 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
317 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
318 (match_operand:SI 2 "gpc_reg_operand" "r"))))
319 (unspec [(const_int 0)] 512)]
320 "TARGET_SPE"
321 "evlhhossplatx %0,%1,%2"
322 [(set_attr "type" "vecload")
323 (set_attr "length" "4")])
324
325(define_insn "spe_evlhhousplat"
326 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
327 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
328 (match_operand:QI 2 "immediate_operand" "i"))))
329 (unspec [(const_int 0)] 513)]
626098f9
AH		 330 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
331 "evlhhousplat %0,%2*2(%1)"
a3170dc6
AH		 332 [(set_attr "type" "vecload")
333 (set_attr "length" "4")])
334
335(define_insn "spe_evlhhousplatx"
336 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
337 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
338 (match_operand:SI 2 "gpc_reg_operand" "r"))))
339 (unspec [(const_int 0)] 514)]
340 "TARGET_SPE"
341 "evlhhousplatx %0,%1,%2"
342 [(set_attr "type" "vecload")
343 (set_attr "length" "4")])
344
345(define_insn "spe_evlwhsplat"
346 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
347 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
348 (match_operand:QI 2 "immediate_operand" "i"))))
349 (unspec [(const_int 0)] 515)]
626098f9
AH		 350 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
351 "evlwhsplat %0,%2*4(%1)"
a3170dc6
AH		 352 [(set_attr "type" "vecload")
353 (set_attr "length" "4")])
354
355(define_insn "spe_evlwhsplatx"
356 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
357 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
358 (match_operand:SI 2 "gpc_reg_operand" "r"))))
359 (unspec [(const_int 0)] 516)]
360 "TARGET_SPE"
361 "evlwhsplatx %0,%1,%2"
362 [(set_attr "type" "vecload")
363 (set_attr "length" "4")])
364
365(define_insn "spe_evlwwsplat"
366 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
367 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
368 (match_operand:QI 2 "immediate_operand" "i"))))
369 (unspec [(const_int 0)] 517)]
626098f9
AH		 370 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
371 "evlwwsplat %0,%2*4(%1)"
a3170dc6
AH		 372 [(set_attr "type" "vecload")
373 (set_attr "length" "4")])
374
375(define_insn "spe_evlwwsplatx"
376 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
377 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
378 (match_operand:SI 2 "gpc_reg_operand" "r"))))
379 (unspec [(const_int 0)] 518)]
380 "TARGET_SPE"
381 "evlwwsplatx %0,%1,%2"
382 [(set_attr "type" "vecload")
383 (set_attr "length" "4")])
384
385(define_insn "spe_evmergehi"
386 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
387 (vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
388 (vec_select:V2SI
389 (match_operand:V2SI 2 "gpc_reg_operand" "r")
390 (parallel [(const_int 1)
391 (const_int 0)]))
392 (const_int 2)))]
393 "TARGET_SPE"
394 "evmergehi %0,%1,%2"
395 [(set_attr "type" "vecsimple")
396 (set_attr "length" "4")])
397
398(define_insn "spe_evmergehilo"
399 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
400 (vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
401 (match_operand:V2SI 2 "gpc_reg_operand" "r")
402 (const_int 2)))]
403 "TARGET_SPE"
404 "evmergehilo %0,%1,%2"
405 [(set_attr "type" "vecsimple")
406 (set_attr "length" "4")])
407
408(define_insn "spe_evmergelo"
409 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
410 (vec_merge:V2SI (vec_select:V2SI
411 (match_operand:V2SI 1 "gpc_reg_operand" "r")
412 (parallel [(const_int 1)
413 (const_int 0)]))
414 (match_operand:V2SI 2 "gpc_reg_operand" "r")
415 (const_int 2)))]
416 "TARGET_SPE"
417 "evmergelo %0,%1,%2"
418 [(set_attr "type" "vecsimple")
419 (set_attr "length" "4")])
420
421(define_insn "spe_evmergelohi"
422 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
423 (vec_merge:V2SI (vec_select:V2SI
424 (match_operand:V2SI 1 "gpc_reg_operand" "r")
425 (parallel [(const_int 1)
426 (const_int 0)]))
427 (vec_select:V2SI
428 (match_operand:V2SI 2 "gpc_reg_operand" "r")
429 (parallel [(const_int 1)
430 (const_int 0)]))
431 (const_int 2)))]
432 "TARGET_SPE"
433 "evmergelohi %0,%1,%2"
434 [(set_attr "type" "vecsimple")
435 (set_attr "length" "4")])
436
437(define_insn "spe_evnand"
438 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
439 (not:V2SI (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
440 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
441 "TARGET_SPE"
442 "evnand %0,%1,%2"
443 [(set_attr "type" "vecsimple")
444 (set_attr "length" "4")])
445
446(define_insn "spe_evneg"
447 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
448 (neg:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
449 "TARGET_SPE"
450 "evneg %0,%1"
451 [(set_attr "type" "vecsimple")
452 (set_attr "length" "4")])
453
454(define_insn "spe_evnor"
455 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
456 (not:V2SI (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
457 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
458 "TARGET_SPE"
459 "evnor %0,%1,%2"
460 [(set_attr "type" "vecsimple")
461 (set_attr "length" "4")])
462
463(define_insn "spe_evorc"
464 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
465 (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
466 (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
467 "TARGET_SPE"
468 "evorc %0,%1,%2"
469 [(set_attr "type" "vecsimple")
470 (set_attr "length" "4")])
471
472(define_insn "spe_evor"
473 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
474 (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
475 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
476 "TARGET_SPE"
477 "evor %0,%1,%2"
478 [(set_attr "type" "vecsimple")
479 (set_attr "length" "4")])
480
481(define_insn "spe_evrlwi"
482 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
483 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
484 (match_operand:QI 2 "immediate_operand" "i")] 519))]
485 "TARGET_SPE"
78872ad9 486 "evrlwi %0,%1,%2"
a3170dc6
AH		 487 [(set_attr "type" "vecsimple")
488 (set_attr "length" "4")])
489
490(define_insn "spe_evrlw"
491 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
492 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
493 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 520))]
494 "TARGET_SPE"
495 "evrlw %0,%1,%2"
496 [(set_attr "type" "veccomplex")
497 (set_attr "length" "4")])
498
499(define_insn "spe_evrndw"
500 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
501 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 521))]
502 "TARGET_SPE"
503 "evrndw %0,%1"
504 [(set_attr "type" "vecsimple")
505 (set_attr "length" "4")])
506
507(define_insn "spe_evsel"
508 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
509 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
510 (match_operand:V2SI 2 "gpc_reg_operand" "r")
511 (match_operand:CC 3 "cc_reg_operand" "y")] 522))]
512 "TARGET_SPE"
513 "evsel %0,%1,%2,%3"
514 [(set_attr "type" "veccmp")
515 (set_attr "length" "4")])
516
517(define_insn "spe_evsel_fs"
518 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
519 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")
520 (match_operand:V2SF 2 "gpc_reg_operand" "r")
521 (match_operand:CC 3 "cc_reg_operand" "y")] 725))]
522 "TARGET_SPE"
523 "evsel %0,%1,%2,%3"
524 [(set_attr "type" "veccmp")
525 (set_attr "length" "4")])
526
527(define_insn "spe_evslwi"
528 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
529 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
530 (match_operand:QI 2 "immediate_operand" "i")]
531 523))]
532 "TARGET_SPE"
533 "evslwi %0,%1,%2"
534 [(set_attr "type" "vecsimple")
535 (set_attr "length" "4")])
536
537(define_insn "spe_evslw"
538 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
539 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
540 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 524))]
541 "TARGET_SPE"
542 "evslw %0,%1,%2"
543 [(set_attr "type" "vecsimple")
544 (set_attr "length" "4")])
545
546(define_insn "spe_evsrwis"
547 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
548 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
549 (match_operand:QI 2 "immediate_operand" "i")]
550 525))]
551 "TARGET_SPE"
552 "evsrwis %0,%1,%2"
553 [(set_attr "type" "vecsimple")
554 (set_attr "length" "4")])
555
556(define_insn "spe_evsrwiu"
557 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
558 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
559 (match_operand:QI 2 "immediate_operand" "i")]
560 526))]
561 "TARGET_SPE"
562 "evsrwiu %0,%1,%2"
563 [(set_attr "type" "vecsimple")
564 (set_attr "length" "4")])
565
566(define_insn "spe_evsrws"
567 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
568 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
569 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 527))]
570 "TARGET_SPE"
571 "evsrws %0,%1,%2"
572 [(set_attr "type" "vecsimple")
573 (set_attr "length" "4")])
574
575(define_insn "spe_evsrwu"
576 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
577 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
578 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 528))]
579 "TARGET_SPE"
580 "evsrwu %0,%1,%2"
581 [(set_attr "type" "vecsimple")
582 (set_attr "length" "4")])
583
626098f9
AH		 584;; vector xors
585
586(define_insn "xorv2si3"
a3170dc6
AH		 587 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
588 (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
589 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
590 "TARGET_SPE"
591 "evxor %0,%1,%2"
592 [(set_attr "type" "vecsimple")
593 (set_attr "length" "4")])
594
626098f9
AH		 595(define_insn "xorv4hi3"
596 [(set (match_operand:V4HI 0 "gpc_reg_operand" "=r")
597 (xor:V4HI (match_operand:V4HI 1 "gpc_reg_operand" "r")
598 (match_operand:V4HI 2 "gpc_reg_operand" "r")))]
599 "TARGET_SPE"
600 "evxor %0,%1,%2"
601 [(set_attr "type" "vecsimple")
602 (set_attr "length" "4")])
603
604(define_insn "xorv1di3"
605 [(set (match_operand:V1DI 0 "gpc_reg_operand" "=r")
606 (xor:V1DI (match_operand:V1DI 1 "gpc_reg_operand" "r")
607 (match_operand:V1DI 2 "gpc_reg_operand" "r")))]
608 "TARGET_SPE"
609 "evxor %0,%1,%2"
610 [(set_attr "type" "vecsimple")
611 (set_attr "length" "4")])
612
613;; end of vector xors
614
a3170dc6
AH		 615(define_insn "spe_evfsabs"
616 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
617 (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
618 "TARGET_SPE"
619 "evfsabs %0,%1"
5e8006fa 620 [(set_attr "type" "vecsimple")
a3170dc6
AH		 621 (set_attr "length" "4")])
622
623(define_insn "spe_evfsadd"
624 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
625 (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
626 (match_operand:V2SF 2 "gpc_reg_operand" "r")))
627 (clobber (reg:SI SPEFSCR_REGNO))]
628 "TARGET_SPE"
629 "evfsadd %0,%1,%2"
630 [(set_attr "type" "vecfloat")
631 (set_attr "length" "4")])
632
633(define_insn "spe_evfscfsf"
634 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
635 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 529))]
636 "TARGET_SPE"
637 "evfscfsf %0,%1"
638 [(set_attr "type" "vecfloat")
639 (set_attr "length" "4")])
640
641(define_insn "spe_evfscfsi"
642 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
643 (fix:V2SI (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
644 "TARGET_SPE"
645 "evfscfsi %0,%1"
646 [(set_attr "type" "vecfloat")
647 (set_attr "length" "4")])
648
649(define_insn "spe_evfscfuf"
650 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
651 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 530))]
652 "TARGET_SPE"
653 "evfscfuf %0,%1"
654 [(set_attr "type" "vecfloat")
655 (set_attr "length" "4")])
656
657(define_insn "spe_evfscfui"
658 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
659 (unspec:V2SF [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 701))]
660 "TARGET_SPE"
661 "evfscfui %0,%1"
662 [(set_attr "type" "vecfloat")
663 (set_attr "length" "4")])
664
665(define_insn "spe_evfsctsf"
666 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
667 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 531))]
668 "TARGET_SPE"
669 "evfsctsf %0,%1"
670 [(set_attr "type" "vecfloat")
671 (set_attr "length" "4")])
672
673(define_insn "spe_evfsctsi"
674 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
675 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 532))]
676 "TARGET_SPE"
677 "evfsctsi %0,%1"
678 [(set_attr "type" "vecfloat")
679 (set_attr "length" "4")])
680
681(define_insn "spe_evfsctsiz"
682 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
683 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 533))]
684 "TARGET_SPE"
685 "evfsctsiz %0,%1"
686 [(set_attr "type" "vecfloat")
687 (set_attr "length" "4")])
688
689(define_insn "spe_evfsctuf"
690 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
691 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 534))]
692 "TARGET_SPE"
693 "evfsctuf %0,%1"
694 [(set_attr "type" "vecfloat")
695 (set_attr "length" "4")])
696
697(define_insn "spe_evfsctui"
698 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
699 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 535))]
700 "TARGET_SPE"
701 "evfsctui %0,%1"
702 [(set_attr "type" "vecfloat")
703 (set_attr "length" "4")])
704
705(define_insn "spe_evfsctuiz"
706 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
707 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 536))]
708 "TARGET_SPE"
709 "evfsctuiz %0,%1"
710 [(set_attr "type" "vecfloat")
711 (set_attr "length" "4")])
712
713(define_insn "spe_evfsdiv"
714 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
715 (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
716 (match_operand:V2SF 2 "gpc_reg_operand" "r")))
717 (clobber (reg:SI SPEFSCR_REGNO))]
718 "TARGET_SPE"
719 "evfsdiv %0,%1,%2"
5e8006fa 720 [(set_attr "type" "vecfdiv")
a3170dc6
AH		 721 (set_attr "length" "4")])
722
723(define_insn "spe_evfsmul"
724 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
725 (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
726 (match_operand:V2SF 2 "gpc_reg_operand" "r")))
727 (clobber (reg:SI SPEFSCR_REGNO))]
728 "TARGET_SPE"
729 "evfsmul %0,%1,%2"
730 [(set_attr "type" "vecfloat")
731 (set_attr "length" "4")])
732
733(define_insn "spe_evfsnabs"
734 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
735 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 537))]
736 "TARGET_SPE"
737 "evfsnabs %0,%1"
5e8006fa 738 [(set_attr "type" "vecsimple")
a3170dc6
AH		 739 (set_attr "length" "4")])
740
741(define_insn "spe_evfsneg"
742 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
743 (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
744 "TARGET_SPE"
745 "evfsneg %0,%1"
5e8006fa 746 [(set_attr "type" "vecsimple")
a3170dc6
AH		 747 (set_attr "length" "4")])
748
749(define_insn "spe_evfssub"
750 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
751 (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
752 (match_operand:V2SF 2 "gpc_reg_operand" "r")))
753 (clobber (reg:SI SPEFSCR_REGNO))]
754 "TARGET_SPE"
755 "evfssub %0,%1,%2"
756 [(set_attr "type" "vecfloat")
757 (set_attr "length" "4")])
758
759;; SPE SIMD load instructions.
760
b6d08ca1 761;; Only the hardware engineer who designed the SPE understands the
a3170dc6
AH		 762;; plethora of load and store instructions ;-). We have no way of
763;; differentiating between them with RTL so use an unspec of const_int 0
764;; to avoid identical RTL.
765
766(define_insn "spe_evldd"
767 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
768 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
769 (match_operand:QI 2 "immediate_operand" "i"))))
770 (unspec [(const_int 0)] 544)]
771 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
626098f9 772 "evldd %0,%2*8(%1)"
a3170dc6
AH		 773 [(set_attr "type" "vecload")
774 (set_attr "length" "4")])
775
776(define_insn "spe_evlddx"
777 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
778 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
779 (match_operand:SI 2 "gpc_reg_operand" "r"))))
780 (unspec [(const_int 0)] 545)]
781 "TARGET_SPE"
782 "evlddx %0,%1,%2"
783 [(set_attr "type" "vecload")
784 (set_attr "length" "4")])
785
786(define_insn "spe_evldh"
787 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
788 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
789 (match_operand:QI 2 "immediate_operand" "i"))))
790 (unspec [(const_int 0)] 546)]
791 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
626098f9 792 "evldh %0,%2*8(%1)"
a3170dc6
AH		 793 [(set_attr "type" "vecload")
794 (set_attr "length" "4")])
795
796(define_insn "spe_evldhx"
797 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
798 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
799 (match_operand:SI 2 "gpc_reg_operand" "r"))))
800 (unspec [(const_int 0)] 547)]
801 "TARGET_SPE"
802 "evldhx %0,%1,%2"
803 [(set_attr "type" "vecload")
804 (set_attr "length" "4")])
805
806(define_insn "spe_evldw"
807 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
808 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
809 (match_operand:QI 2 "immediate_operand" "i"))))
810 (unspec [(const_int 0)] 548)]
626098f9
AH		 811 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
812 "evldw %0,%2*8(%1)"
a3170dc6
AH		 813 [(set_attr "type" "vecload")
814 (set_attr "length" "4")])
815
816(define_insn "spe_evldwx"
817 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
818 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
819 (match_operand:SI 2 "gpc_reg_operand" "r"))))
820 (unspec [(const_int 0)] 549)]
821 "TARGET_SPE"
822 "evldwx %0,%1,%2"
823 [(set_attr "type" "vecload")
824 (set_attr "length" "4")])
825
826(define_insn "spe_evlwhe"
827 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
828 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
829 (match_operand:QI 2 "immediate_operand" "i"))))
830 (unspec [(const_int 0)] 550)]
626098f9
AH		 831 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
832 "evlwhe %0,%2*4(%1)"
a3170dc6
AH		 833 [(set_attr "type" "vecload")
834 (set_attr "length" "4")])
835
836(define_insn "spe_evlwhex"
837 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
838 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
839 (match_operand:SI 2 "gpc_reg_operand" "r"))))
840 (unspec [(const_int 0)] 551)]
841 "TARGET_SPE"
842 "evlwhex %0,%1,%2"
843 [(set_attr "type" "vecload")
844 (set_attr "length" "4")])
845
846(define_insn "spe_evlwhos"
847 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
848 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
849 (match_operand:QI 2 "immediate_operand" "i"))))
850 (unspec [(const_int 0)] 552)]
626098f9
AH		 851 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
852 "evlwhos %0,%2*4(%1)"
a3170dc6
AH		 853 [(set_attr "type" "vecload")
854 (set_attr "length" "4")])
855
856(define_insn "spe_evlwhosx"
857 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
858 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
859 (match_operand:SI 2 "gpc_reg_operand" "r"))))
860 (unspec [(const_int 0)] 553)]
861 "TARGET_SPE"
862 "evlwhosx %0,%1,%2"
863 [(set_attr "type" "vecload")
864 (set_attr "length" "4")])
865
866(define_insn "spe_evlwhou"
867 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
868 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
869 (match_operand:QI 2 "immediate_operand" "i"))))
870 (unspec [(const_int 0)] 554)]
626098f9
AH		 871 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
872 "evlwhou %0,%2*4(%1)"
a3170dc6
AH		 873 [(set_attr "type" "vecload")
874 (set_attr "length" "4")])
875
876(define_insn "spe_evlwhoux"
877 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
878 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
879 (match_operand:SI 2 "gpc_reg_operand" "r"))))
880 (unspec [(const_int 0)] 555)]
881 "TARGET_SPE"
882 "evlwhoux %0,%1,%2"
883 [(set_attr "type" "vecload")
884 (set_attr "length" "4")])
885
886(define_insn "spe_brinc"
887 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
888 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "r")
889 (match_operand:SI 2 "gpc_reg_operand" "r")] 556))]
890 "TARGET_SPE"
891 "brinc %0,%1,%2"
5e8006fa 892 [(set_attr "type" "brinc")
a3170dc6
AH		 893 (set_attr "length" "4")])
894
895(define_insn "spe_evmhegsmfaa"
896 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
897 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
898 (match_operand:V2SI 2 "gpc_reg_operand" "r")
899 (reg:V2SI SPE_ACC_REGNO)] 557))
54da776f 900 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 901 "TARGET_SPE"
902 "evmhegsmfaa %0,%1,%2"
903 [(set_attr "type" "veccomplex")
904 (set_attr "length" "4")])
905
906(define_insn "spe_evmhegsmfan"
907 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
908 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
909 (match_operand:V2SI 2 "gpc_reg_operand" "r")
910 (reg:V2SI SPE_ACC_REGNO)] 558))
54da776f 911 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 912 "TARGET_SPE"
913 "evmhegsmfan %0,%1,%2"
914 [(set_attr "type" "veccomplex")
915 (set_attr "length" "4")])
916
917(define_insn "spe_evmhegsmiaa"
918 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
919 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
920 (match_operand:V2SI 2 "gpc_reg_operand" "r")
921 (reg:V2SI SPE_ACC_REGNO)] 559))
54da776f 922 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 923 "TARGET_SPE"
924 "evmhegsmiaa %0,%1,%2"
925 [(set_attr "type" "veccomplex")
926 (set_attr "length" "4")])
927
928(define_insn "spe_evmhegsmian"
929 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
930 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
931 (match_operand:V2SI 2 "gpc_reg_operand" "r")
932 (reg:V2SI SPE_ACC_REGNO)] 560))
54da776f 933 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 934 "TARGET_SPE"
935 "evmhegsmian %0,%1,%2"
936 [(set_attr "type" "veccomplex")
937 (set_attr "length" "4")])
938
939(define_insn "spe_evmhegumiaa"
940 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
941 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
942 (match_operand:V2SI 2 "gpc_reg_operand" "r")
943 (reg:V2SI SPE_ACC_REGNO)] 561))
54da776f 944 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 945 "TARGET_SPE"
946 "evmhegumiaa %0,%1,%2"
947 [(set_attr "type" "veccomplex")
948 (set_attr "length" "4")])
949
950(define_insn "spe_evmhegumian"
951 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
952 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
953 (match_operand:V2SI 2 "gpc_reg_operand" "r")
954 (reg:V2SI SPE_ACC_REGNO)] 562))
54da776f 955 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 956 "TARGET_SPE"
957 "evmhegumian %0,%1,%2"
958 [(set_attr "type" "veccomplex")
959 (set_attr "length" "4")])
960
961(define_insn "spe_evmhesmfaaw"
962 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
963 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
964 (match_operand:V2SI 2 "gpc_reg_operand" "r")
965 (reg:V2SI SPE_ACC_REGNO)] 563))
54da776f 966 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 967 "TARGET_SPE"
968 "evmhesmfaaw %0,%1,%2"
969 [(set_attr "type" "veccomplex")
970 (set_attr "length" "4")])
971
972(define_insn "spe_evmhesmfanw"
973 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
974 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
975 (match_operand:V2SI 2 "gpc_reg_operand" "r")
976 (reg:V2SI SPE_ACC_REGNO)] 564))
54da776f 977 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 978 "TARGET_SPE"
979 "evmhesmfanw %0,%1,%2"
980 [(set_attr "type" "veccomplex")
981 (set_attr "length" "4")])
982
983(define_insn "spe_evmhesmfa"
984 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
985 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
986 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 565))
54da776f 987 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 988 "TARGET_SPE"
989 "evmhesmfa %0,%1,%2"
990 [(set_attr "type" "veccomplex")
991 (set_attr "length" "4")])
992
993(define_insn "spe_evmhesmf"
994 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
995 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
996 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 566))]
997 "TARGET_SPE"
998 "evmhesmf %0,%1,%2"
999 [(set_attr "type" "veccomplex")
1000 (set_attr "length" "4")])
1001
1002(define_insn "spe_evmhesmiaaw"
1003 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1004 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1005 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1006 (reg:V2SI SPE_ACC_REGNO)] 567))
54da776f 1007 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1008 "TARGET_SPE"
1009 "evmhesmiaaw %0,%1,%2"
1010 [(set_attr "type" "veccomplex")
1011 (set_attr "length" "4")])
1012
1013(define_insn "spe_evmhesmianw"
1014 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1015 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1016 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1017 (reg:V2SI SPE_ACC_REGNO)] 568))
54da776f 1018 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1019 "TARGET_SPE"
1020 "evmhesmianw %0,%1,%2"
1021 [(set_attr "type" "veccomplex")
1022 (set_attr "length" "4")])
1023
1024(define_insn "spe_evmhesmia"
1025 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1026 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1027 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 569))
54da776f 1028 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1029 "TARGET_SPE"
1030 "evmhesmia %0,%1,%2"
1031 [(set_attr "type" "veccomplex")
1032 (set_attr "length" "4")])
1033
1034(define_insn "spe_evmhesmi"
1035 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1036 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1037 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 570))]
1038 "TARGET_SPE"
1039 "evmhesmi %0,%1,%2"
1040 [(set_attr "type" "veccomplex")
1041 (set_attr "length" "4")])
1042
1043(define_insn "spe_evmhessfaaw"
1044 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1045 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1046 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1047 (reg:V2SI SPE_ACC_REGNO)] 571))
1048 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1049 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1050 "TARGET_SPE"
1051 "evmhessfaaw %0,%1,%2"
1052 [(set_attr "type" "veccomplex")
1053 (set_attr "length" "4")])
1054
1055(define_insn "spe_evmhessfanw"
1056 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1057 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1058 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1059 (reg:V2SI SPE_ACC_REGNO)] 572))
1060 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1061 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1062 "TARGET_SPE"
1063 "evmhessfanw %0,%1,%2"
1064 [(set_attr "type" "veccomplex")
1065 (set_attr "length" "4")])
1066
1067(define_insn "spe_evmhessfa"
1068 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1069 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1070 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 573))
1071 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1072 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1073 "TARGET_SPE"
1074 "evmhessfa %0,%1,%2"
1075 [(set_attr "type" "veccomplex")
1076 (set_attr "length" "4")])
1077
1078(define_insn "spe_evmhessf"
1079 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1080 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1081 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 574))
1082 (clobber (reg:SI SPEFSCR_REGNO))]
1083 "TARGET_SPE"
1084 "evmhessf %0,%1,%2"
1085 [(set_attr "type" "veccomplex")
1086 (set_attr "length" "4")])
1087
1088(define_insn "spe_evmhessiaaw"
1089 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1090 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1091 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1092 (reg:V2SI SPE_ACC_REGNO)] 575))
1093 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1094 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6 1095 "TARGET_SPE"
c9b93e1a 1096 "evmhessiaaw %0,%1,%2"
a3170dc6
AH		 1097 [(set_attr "type" "veccomplex")
1098 (set_attr "length" "4")])
1099
1100(define_insn "spe_evmhessianw"
1101 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1102 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1103 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1104 (reg:V2SI SPE_ACC_REGNO)] 576))
1105 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1106 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1107 "TARGET_SPE"
1108 "evmhessianw %0,%1,%2"
1109 [(set_attr "type" "veccomplex")
1110 (set_attr "length" "4")])
1111
1112(define_insn "spe_evmheumiaaw"
1113 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1114 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1115 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1116 (reg:V2SI SPE_ACC_REGNO)] 577))
54da776f 1117 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1118 "TARGET_SPE"
1119 "evmheumiaaw %0,%1,%2"
1120 [(set_attr "type" "veccomplex")
1121 (set_attr "length" "4")])
1122
1123(define_insn "spe_evmheumianw"
1124 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1125 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1126 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1127 (reg:V2SI SPE_ACC_REGNO)] 578))
54da776f 1128 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1129 "TARGET_SPE"
1130 "evmheumianw %0,%1,%2"
1131 [(set_attr "type" "veccomplex")
1132 (set_attr "length" "4")])
1133
1134(define_insn "spe_evmheumia"
1135 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1136 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1137 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 579))
54da776f 1138 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1139 "TARGET_SPE"
1140 "evmheumia %0,%1,%2"
1141 [(set_attr "type" "veccomplex")
1142 (set_attr "length" "4")])
1143
1144(define_insn "spe_evmheumi"
1145 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1146 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1147 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 580))]
1148 "TARGET_SPE"
1149 "evmheumi %0,%1,%2"
1150 [(set_attr "type" "veccomplex")
1151 (set_attr "length" "4")])
1152
1153(define_insn "spe_evmheusiaaw"
1154 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1155 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1156 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1157 (reg:V2SI SPE_ACC_REGNO)] 581))
1158 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1159 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1160 "TARGET_SPE"
1161 "evmheusiaaw %0,%1,%2"
1162 [(set_attr "type" "veccomplex")
1163 (set_attr "length" "4")])
1164
1165(define_insn "spe_evmheusianw"
1166 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1167 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1168 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1169 (reg:V2SI SPE_ACC_REGNO)] 582))
1170 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1171 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1172 "TARGET_SPE"
1173 "evmheusianw %0,%1,%2"
1174 [(set_attr "type" "veccomplex")
1175 (set_attr "length" "4")])
1176
1177(define_insn "spe_evmhogsmfaa"
1178 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1179 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1180 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1181 (reg:V2SI SPE_ACC_REGNO)] 583))
54da776f 1182 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1183 "TARGET_SPE"
1184 "evmhogsmfaa %0,%1,%2"
1185 [(set_attr "type" "veccomplex")
1186 (set_attr "length" "4")])
1187
1188(define_insn "spe_evmhogsmfan"
1189 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1190 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1191 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1192 (reg:V2SI SPE_ACC_REGNO)] 584))
54da776f 1193 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1194 "TARGET_SPE"
1195 "evmhogsmfan %0,%1,%2"
1196 [(set_attr "type" "veccomplex")
1197 (set_attr "length" "4")])
1198
1199(define_insn "spe_evmhogsmiaa"
1200 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1201 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1202 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1203 (reg:V2SI SPE_ACC_REGNO)] 585))
54da776f 1204 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1205 "TARGET_SPE"
1206 "evmhogsmiaa %0,%1,%2"
1207 [(set_attr "type" "veccomplex")
1208 (set_attr "length" "4")])
1209
1210(define_insn "spe_evmhogsmian"
1211 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1212 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1213 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1214 (reg:V2SI SPE_ACC_REGNO)] 586))
54da776f 1215 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1216 "TARGET_SPE"
1217 "evmhogsmian %0,%1,%2"
1218 [(set_attr "type" "veccomplex")
1219 (set_attr "length" "4")])
1220
1221(define_insn "spe_evmhogumiaa"
1222 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1223 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1224 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1225 (reg:V2SI SPE_ACC_REGNO)] 587))
54da776f 1226 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1227 "TARGET_SPE"
1228 "evmhogumiaa %0,%1,%2"
1229 [(set_attr "type" "veccomplex")
1230 (set_attr "length" "4")])
1231
1232(define_insn "spe_evmhogumian"
1233 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1234 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1235 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1236 (reg:V2SI SPE_ACC_REGNO)] 588))
54da776f 1237 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1238 "TARGET_SPE"
1239 "evmhogumian %0,%1,%2"
1240 [(set_attr "type" "veccomplex")
1241 (set_attr "length" "4")])
1242
1243(define_insn "spe_evmhosmfaaw"
1244 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1245 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1246 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1247 (reg:V2SI SPE_ACC_REGNO)] 589))
54da776f 1248 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1249 "TARGET_SPE"
1250 "evmhosmfaaw %0,%1,%2"
1251 [(set_attr "type" "veccomplex")
1252 (set_attr "length" "4")])
1253
1254(define_insn "spe_evmhosmfanw"
1255 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1256 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1257 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1258 (reg:V2SI SPE_ACC_REGNO)] 590))
54da776f 1259 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1260 "TARGET_SPE"
1261 "evmhosmfanw %0,%1,%2"
1262 [(set_attr "type" "veccomplex")
1263 (set_attr "length" "4")])
1264
1265(define_insn "spe_evmhosmfa"
1266 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1267 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1268 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 591))]
1269 "TARGET_SPE"
1270 "evmhosmfa %0,%1,%2"
1271 [(set_attr "type" "veccomplex")
1272 (set_attr "length" "4")])
1273
1274(define_insn "spe_evmhosmf"
1275 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1276 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1277 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 592))
54da776f 1278 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1279 "TARGET_SPE"
1280 "evmhosmf %0,%1,%2"
1281 [(set_attr "type" "veccomplex")
1282 (set_attr "length" "4")])
1283
1284(define_insn "spe_evmhosmiaaw"
1285 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1286 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1287 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1288 (reg:V2SI SPE_ACC_REGNO)] 593))
54da776f 1289 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1290 "TARGET_SPE"
1291 "evmhosmiaaw %0,%1,%2"
1292 [(set_attr "type" "veccomplex")
1293 (set_attr "length" "4")])
1294
1295(define_insn "spe_evmhosmianw"
1296 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1297 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1298 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1299 (reg:V2SI SPE_ACC_REGNO)] 594))
54da776f 1300 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1301 "TARGET_SPE"
1302 "evmhosmianw %0,%1,%2"
1303 [(set_attr "type" "veccomplex")
1304 (set_attr "length" "4")])
1305
1306(define_insn "spe_evmhosmia"
1307 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1308 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1309 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 595))
54da776f 1310 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1311 "TARGET_SPE"
1312 "evmhosmia %0,%1,%2"
1313 [(set_attr "type" "veccomplex")
1314 (set_attr "length" "4")])
1315
1316(define_insn "spe_evmhosmi"
1317 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1318 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1319 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 596))]
1320 "TARGET_SPE"
1321 "evmhosmi %0,%1,%2"
1322 [(set_attr "type" "veccomplex")
1323 (set_attr "length" "4")])
1324
1325(define_insn "spe_evmhossfaaw"
1326 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1327 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1328 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1329 (reg:V2SI SPE_ACC_REGNO)] 597))
1330 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1331 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1332 "TARGET_SPE"
1333 "evmhossfaaw %0,%1,%2"
1334 [(set_attr "type" "veccomplex")
1335 (set_attr "length" "4")])
1336
1337(define_insn "spe_evmhossfanw"
1338 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1339 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1340 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1341 (reg:V2SI SPE_ACC_REGNO)] 598))
1342 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1343 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1344 "TARGET_SPE"
1345 "evmhossfanw %0,%1,%2"
1346 [(set_attr "type" "veccomplex")
1347 (set_attr "length" "4")])
1348
1349(define_insn "spe_evmhossfa"
1350 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1351 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1352 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1353 (reg:V2SI SPE_ACC_REGNO)] 599))
1354 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1355 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1356 "TARGET_SPE"
1357 "evmhossfa %0,%1,%2"
1358 [(set_attr "type" "veccomplex")
1359 (set_attr "length" "4")])
1360
1361(define_insn "spe_evmhossf"
1362 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1363 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1364 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 600))
1365 (clobber (reg:SI SPEFSCR_REGNO))]
1366 "TARGET_SPE"
1367 "evmhossf %0,%1,%2"
1368 [(set_attr "type" "veccomplex")
1369 (set_attr "length" "4")])
1370
1371(define_insn "spe_evmhossiaaw"
1372 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1373 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1374 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1375 (reg:V2SI SPE_ACC_REGNO)] 601))
1376 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1377 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1378 "TARGET_SPE"
1379 "evmhossiaaw %0,%1,%2"
1380 [(set_attr "type" "veccomplex")
1381 (set_attr "length" "4")])
1382
1383(define_insn "spe_evmhossianw"
1384 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1385 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1386 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1387 (reg:V2SI SPE_ACC_REGNO)] 602))
1388 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1389 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1390 "TARGET_SPE"
1391 "evmhossianw %0,%1,%2"
1392 [(set_attr "type" "veccomplex")
1393 (set_attr "length" "4")])
1394
1395(define_insn "spe_evmhoumiaaw"
1396 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1397 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1398 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1399 (reg:V2SI SPE_ACC_REGNO)] 603))
54da776f 1400 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1401 "TARGET_SPE"
1402 "evmhoumiaaw %0,%1,%2"
1403 [(set_attr "type" "veccomplex")
1404 (set_attr "length" "4")])
1405
1406(define_insn "spe_evmhoumianw"
1407 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1408 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1409 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1410 (reg:V2SI SPE_ACC_REGNO)] 604))
54da776f 1411 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1412 "TARGET_SPE"
1413 "evmhoumianw %0,%1,%2"
1414 [(set_attr "type" "veccomplex")
1415 (set_attr "length" "4")])
1416
1417(define_insn "spe_evmhoumia"
1418 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1419 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1420 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 605))
54da776f 1421 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1422 "TARGET_SPE"
1423 "evmhoumia %0,%1,%2"
1424 [(set_attr "type" "veccomplex")
1425 (set_attr "length" "4")])
1426
1427(define_insn "spe_evmhoumi"
1428 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1429 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1430 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 606))]
1431 "TARGET_SPE"
1432 "evmhoumi %0,%1,%2"
1433 [(set_attr "type" "veccomplex")
1434 (set_attr "length" "4")])
1435
1436(define_insn "spe_evmhousiaaw"
1437 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1438 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1439 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1440 (reg:V2SI SPE_ACC_REGNO)] 607))
1441 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1442 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1443 "TARGET_SPE"
1444 "evmhousiaaw %0,%1,%2"
1445 [(set_attr "type" "veccomplex")
1446 (set_attr "length" "4")])
1447
1448(define_insn "spe_evmhousianw"
1449 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1450 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1451 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1452 (reg:V2SI SPE_ACC_REGNO)] 608))
1453 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1454 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1455 "TARGET_SPE"
1456 "evmhousianw %0,%1,%2"
1457 [(set_attr "type" "veccomplex")
1458 (set_attr "length" "4")])
1459
1460(define_insn "spe_evmmlssfa"
1461 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1462 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1463 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 609))]
1464 "TARGET_SPE"
1465 "evmmlssfa %0,%1,%2"
1466 [(set_attr "type" "veccomplex")
1467 (set_attr "length" "4")])
1468
1469(define_insn "spe_evmmlssf"
1470 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1471 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1472 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 610))]
1473 "TARGET_SPE"
1474 "evmmlssf %0,%1,%2"
1475 [(set_attr "type" "veccomplex")
1476 (set_attr "length" "4")])
1477
1478(define_insn "spe_evmwhsmfa"
1479 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1480 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1481 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 611))
54da776f 1482 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1483 "TARGET_SPE"
1484 "evmwhsmfa %0,%1,%2"
1485 [(set_attr "type" "veccomplex")
1486 (set_attr "length" "4")])
1487
1488(define_insn "spe_evmwhsmf"
1489 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1490 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1491 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 612))]
1492 "TARGET_SPE"
1493 "evmwhsmf %0,%1,%2"
1494 [(set_attr "type" "veccomplex")
1495 (set_attr "length" "4")])
1496
1497(define_insn "spe_evmwhsmia"
1498 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1499 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1500 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 613))
54da776f 1501 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1502 "TARGET_SPE"
1503 "evmwhsmia %0,%1,%2"
1504 [(set_attr "type" "veccomplex")
1505 (set_attr "length" "4")])
1506
1507(define_insn "spe_evmwhsmi"
1508 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1509 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1510 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 614))]
1511 "TARGET_SPE"
1512 "evmwhsmi %0,%1,%2"
1513 [(set_attr "type" "veccomplex")
1514 (set_attr "length" "4")])
1515
1516(define_insn "spe_evmwhssfa"
1517 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1518 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1519 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 615))
1520 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1521 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1522 "TARGET_SPE"
1523 "evmwhssfa %0,%1,%2"
1524 [(set_attr "type" "veccomplex")
1525 (set_attr "length" "4")])
1526
1527(define_insn "spe_evmwhusian"
1528 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1529 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1530 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 626))]
1531 "TARGET_SPE"
1532 "evmwhusian %0,%1,%2"
1533 [(set_attr "type" "veccomplex")
1534 (set_attr "length" "4")])
1535
1536(define_insn "spe_evmwhssf"
1537 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1538 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1539 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 628))
1540 (clobber (reg:SI SPEFSCR_REGNO))]
1541 "TARGET_SPE"
1542 "evmwhssf %0,%1,%2"
1543 [(set_attr "type" "veccomplex")
1544 (set_attr "length" "4")])
1545
1546(define_insn "spe_evmwhumia"
1547 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1548 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1549 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 629))
54da776f 1550 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1551 "TARGET_SPE"
1552 "evmwhumia %0,%1,%2"
1553 [(set_attr "type" "veccomplex")
1554 (set_attr "length" "4")])
1555
1556(define_insn "spe_evmwhumi"
1557 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1558 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1559 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 630))]
1560 "TARGET_SPE"
1561 "evmwhumi %0,%1,%2"
1562 [(set_attr "type" "veccomplex")
1563 (set_attr "length" "4")])
1564
a3170dc6
AH		 1565(define_insn "spe_evmwlsmiaaw"
1566 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1567 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1568 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1569 (reg:V2SI SPE_ACC_REGNO)] 635))
54da776f 1570 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1571 "TARGET_SPE"
1572 "evmwlsmiaaw %0,%1,%2"
1573 [(set_attr "type" "veccomplex")
1574 (set_attr "length" "4")])
1575
1576(define_insn "spe_evmwlsmianw"
1577 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1578 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1579 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1580 (reg:V2SI SPE_ACC_REGNO)] 636))
54da776f 1581 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1582 "TARGET_SPE"
1583 "evmwlsmianw %0,%1,%2"
a3170dc6
AH		 1584 [(set_attr "type" "veccomplex")
1585 (set_attr "length" "4")])
1586
1587(define_insn "spe_evmwlssiaaw"
1588 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1589 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1590 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1591 (reg:V2SI SPE_ACC_REGNO)] 641))
1592 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1593 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1594 "TARGET_SPE"
1595 "evmwlssiaaw %0,%1,%2"
1596 [(set_attr "type" "veccomplex")
1597 (set_attr "length" "4")])
1598
1599(define_insn "spe_evmwlssianw"
1600 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1601 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1602 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1603 (reg:V2SI SPE_ACC_REGNO)] 642))
1604 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1605 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1606 "TARGET_SPE"
1607 "evmwlssianw %0,%1,%2"
1608 [(set_attr "type" "veccomplex")
1609 (set_attr "length" "4")])
1610
1611(define_insn "spe_evmwlumiaaw"
1612 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1613 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1614 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1615 (reg:V2SI SPE_ACC_REGNO)] 643))
54da776f 1616 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1617 "TARGET_SPE"
1618 "evmwlumiaaw %0,%1,%2"
1619 [(set_attr "type" "veccomplex")
1620 (set_attr "length" "4")])
1621
1622(define_insn "spe_evmwlumianw"
1623 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1624 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1625 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1626 (reg:V2SI SPE_ACC_REGNO)] 644))
54da776f 1627 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1628 "TARGET_SPE"
1629 "evmwlumianw %0,%1,%2"
1630 [(set_attr "type" "veccomplex")
1631 (set_attr "length" "4")])
1632
1633(define_insn "spe_evmwlumia"
1634 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1635 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1636 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 645))
54da776f 1637 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1638 "TARGET_SPE"
1639 "evmwlumia %0,%1,%2"
1640 [(set_attr "type" "veccomplex")
1641 (set_attr "length" "4")])
1642
1643(define_insn "spe_evmwlumi"
1644 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1645 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1646 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 646))]
1647 "TARGET_SPE"
1648 "evmwlumi %0,%1,%2"
1649 [(set_attr "type" "veccomplex")
1650 (set_attr "length" "4")])
1651
1652(define_insn "spe_evmwlusiaaw"
1653 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1654 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1655 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1656 (reg:V2SI SPE_ACC_REGNO)] 647))
1657 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1658 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1659 "TARGET_SPE"
1660 "evmwlusiaaw %0,%1,%2"
1661 [(set_attr "type" "veccomplex")
1662 (set_attr "length" "4")])
1663
1664(define_insn "spe_evmwlusianw"
1665 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1666 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1667 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1668 (reg:V2SI SPE_ACC_REGNO)] 648))
1669 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1670 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1671 "TARGET_SPE"
1672 "evmwlusianw %0,%1,%2"
1673 [(set_attr "type" "veccomplex")
1674 (set_attr "length" "4")])
1675
1676(define_insn "spe_evmwsmfaa"
1677 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1678 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1679 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1680 (reg:V2SI SPE_ACC_REGNO)] 649))
54da776f 1681 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1682 "TARGET_SPE"
1683 "evmwsmfaa %0,%1,%2"
1684 [(set_attr "type" "veccomplex")
1685 (set_attr "length" "4")])
1686
1687(define_insn "spe_evmwsmfan"
1688 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1689 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1690 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1691 (reg:V2SI SPE_ACC_REGNO)] 650))
54da776f 1692 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1693 "TARGET_SPE"
1694 "evmwsmfan %0,%1,%2"
1695 [(set_attr "type" "veccomplex")
1696 (set_attr "length" "4")])
1697
1698(define_insn "spe_evmwsmfa"
1699 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1700 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1701 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 651))
54da776f 1702 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1703 "TARGET_SPE"
1704 "evmwsmfa %0,%1,%2"
1705 [(set_attr "type" "veccomplex")
1706 (set_attr "length" "4")])
1707
1708(define_insn "spe_evmwsmf"
1709 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1710 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1711 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 652))]
1712 "TARGET_SPE"
1713 "evmwsmf %0,%1,%2"
1714 [(set_attr "type" "veccomplex")
1715 (set_attr "length" "4")])
1716
1717(define_insn "spe_evmwsmiaa"
1718 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1719 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1720 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1721 (reg:V2SI SPE_ACC_REGNO)] 653))
54da776f 1722 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1723 "TARGET_SPE"
1724 "evmwsmiaa %0,%1,%2"
1725 [(set_attr "type" "veccomplex")
1726 (set_attr "length" "4")])
1727
1728(define_insn "spe_evmwsmian"
1729 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1730 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1731 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1732 (reg:V2SI SPE_ACC_REGNO)] 654))
54da776f 1733 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1734 "TARGET_SPE"
1735 "evmwsmian %0,%1,%2"
1736 [(set_attr "type" "veccomplex")
1737 (set_attr "length" "4")])
1738
1739(define_insn "spe_evmwsmia"
1740 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1741 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1742 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 655))
54da776f 1743 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1744 "TARGET_SPE"
1745 "evmwsmia %0,%1,%2"
1746 [(set_attr "type" "veccomplex")
1747 (set_attr "length" "4")])
1748
1749(define_insn "spe_evmwsmi"
1750 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1751 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1752 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 656))]
1753 "TARGET_SPE"
1754 "evmwsmi %0,%1,%2"
1755 [(set_attr "type" "veccomplex")
1756 (set_attr "length" "4")])
1757
1758(define_insn "spe_evmwssfaa"
1759 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1760 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1761 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1762 (reg:V2SI SPE_ACC_REGNO)] 657))
1763 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1764 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1765 "TARGET_SPE"
1766 "evmwssfaa %0,%1,%2"
1767 [(set_attr "type" "veccomplex")
1768 (set_attr "length" "4")])
1769
1770(define_insn "spe_evmwssfan"
1771 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1772 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1773 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1774 (reg:V2SI SPE_ACC_REGNO)] 658))
1775 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1776 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1777 "TARGET_SPE"
1778 "evmwssfan %0,%1,%2"
1779 [(set_attr "type" "veccomplex")
1780 (set_attr "length" "4")])
1781
1782(define_insn "spe_evmwssfa"
1783 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1784 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1785 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 659))
1786 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1787 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1788 "TARGET_SPE"
1789 "evmwssfa %0,%1,%2"
1790 [(set_attr "type" "veccomplex")
1791 (set_attr "length" "4")])
1792
1793(define_insn "spe_evmwssf"
1794 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1795 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1796 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 660))
1797 (clobber (reg:SI SPEFSCR_REGNO))]
1798 "TARGET_SPE"
1799 "evmwssf %0,%1,%2"
1800 [(set_attr "type" "veccomplex")
1801 (set_attr "length" "4")])
1802
1803(define_insn "spe_evmwumiaa"
1804 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1805 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1806 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1807 (reg:V2SI SPE_ACC_REGNO)] 661))
54da776f 1808 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1809 "TARGET_SPE"
1810 "evmwumiaa %0,%1,%2"
1811 [(set_attr "type" "veccomplex")
1812 (set_attr "length" "4")])
1813
1814(define_insn "spe_evmwumian"
1815 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1816 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1817 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1818 (reg:V2SI SPE_ACC_REGNO)] 662))
54da776f 1819 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1820 "TARGET_SPE"
1821 "evmwumian %0,%1,%2"
1822 [(set_attr "type" "veccomplex")
1823 (set_attr "length" "4")])
1824
1825(define_insn "spe_evmwumia"
1826 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1827 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1828 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 663))
54da776f 1829 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1830 "TARGET_SPE"
1831 "evmwumia %0,%1,%2"
1832 [(set_attr "type" "veccomplex")
1833 (set_attr "length" "4")])
1834
1835(define_insn "spe_evmwumi"
1836 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1837 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1838 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 664))]
1839 "TARGET_SPE"
1840 "evmwumi %0,%1,%2"
1841 [(set_attr "type" "veccomplex")
1842 (set_attr "length" "4")])
1843
1844(define_insn "spe_evaddw"
1845 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1846 (plus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
1847 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
1848 "TARGET_SPE"
1849 "evaddw %0,%1,%2"
5e8006fa 1850 [(set_attr "type" "vecsimple")
a3170dc6
AH		 1851 (set_attr "length" "4")])
1852
1853(define_insn "spe_evaddusiaaw"
1854 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1855 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1856 (reg:V2SI SPE_ACC_REGNO)] 673))
1857 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1858 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1859 "TARGET_SPE"
1860 "evaddusiaaw %0,%1"
1861 [(set_attr "type" "veccomplex")
1862 (set_attr "length" "4")])
1863
1864(define_insn "spe_evaddumiaaw"
1865 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1866 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1867 (reg:V2SI SPE_ACC_REGNO)] 674))
54da776f 1868 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1869 "TARGET_SPE"
1870 "evaddumiaaw %0,%1"
1871 [(set_attr "type" "veccomplex")
1872 (set_attr "length" "4")])
1873
1874(define_insn "spe_evaddssiaaw"
1875 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1876 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1877 (reg:V2SI SPE_ACC_REGNO)] 675))
1878 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1879 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1880 "TARGET_SPE"
1881 "evaddssiaaw %0,%1"
1882 [(set_attr "type" "veccomplex")
1883 (set_attr "length" "4")])
1884
1885(define_insn "spe_evaddsmiaaw"
1886 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1887 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1888 (reg:V2SI SPE_ACC_REGNO)] 676))
54da776f 1889 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1890 "TARGET_SPE"
1891 "evaddsmiaaw %0,%1"
1892 [(set_attr "type" "veccomplex")
1893 (set_attr "length" "4")])
1894
1895(define_insn "spe_evaddiw"
1896 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1897 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1898 (match_operand:QI 2 "immediate_operand" "i")] 677))]
1899 "TARGET_SPE"
1900 "evaddiw %0,%1,%2"
5e8006fa 1901 [(set_attr "type" "vecsimple")
a3170dc6
AH		 1902 (set_attr "length" "4")])
1903
1904(define_insn "spe_evsubifw"
1905 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1906 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1907 (match_operand:QI 2 "immediate_operand" "i")] 678))]
1908 "TARGET_SPE"
1909 "evsubifw %0,%2,%1"
1910 [(set_attr "type" "veccomplex")
1911 (set_attr "length" "4")])
1912
1913(define_insn "spe_evsubfw"
1914 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1915 (minus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
1916 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
1917 "TARGET_SPE"
12850cf2 1918 "evsubfw %0,%2,%1"
a3170dc6
AH		 1919 [(set_attr "type" "veccomplex")
1920 (set_attr "length" "4")])
1921
1922(define_insn "spe_evsubfusiaaw"
1923 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1924 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1925 (reg:V2SI SPE_ACC_REGNO)] 679))
1926 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1927 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1928 "TARGET_SPE"
1929 "evsubfusiaaw %0,%1"
1930 [(set_attr "type" "veccomplex")
1931 (set_attr "length" "4")])
1932
1933(define_insn "spe_evsubfumiaaw"
1934 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1935 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1936 (reg:V2SI SPE_ACC_REGNO)] 680))
54da776f 1937 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1938 "TARGET_SPE"
1939 "evsubfumiaaw %0,%1"
1940 [(set_attr "type" "veccomplex")
1941 (set_attr "length" "4")])
1942
1943(define_insn "spe_evsubfssiaaw"
1944 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1945 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1946 (reg:V2SI SPE_ACC_REGNO)] 681))
1947 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1948 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1949 "TARGET_SPE"
1950 "evsubfssiaaw %0,%1"
1951 [(set_attr "type" "veccomplex")
1952 (set_attr "length" "4")])
1953
1954(define_insn "spe_evsubfsmiaaw"
1955 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1956 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1957 (reg:V2SI SPE_ACC_REGNO)] 682))
54da776f 1958 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1959 "TARGET_SPE"
1960 "evsubfsmiaaw %0,%1"
1961 [(set_attr "type" "veccomplex")
1962 (set_attr "length" "4")])
1963
1964(define_insn "spe_evmra"
1965 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1966 (match_operand:V2SI 1 "gpc_reg_operand" "r"))
c3021e5d
AH		 1967 (set (reg:V2SI SPE_ACC_REGNO)
1968 (unspec:V2SI [(match_dup 1)] 726))]
a3170dc6
AH		 1969 "TARGET_SPE"
1970 "evmra %0,%1"
1971 [(set_attr "type" "veccomplex")
1972 (set_attr "length" "4")])
1973
1974(define_insn "spe_evdivws"
1975 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1976 (div:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
1977 (match_operand:V2SI 2 "gpc_reg_operand" "r")))
1978 (clobber (reg:SI SPEFSCR_REGNO))]
1979 "TARGET_SPE"
1980 "evdivws %0,%1,%2"
5e8006fa 1981 [(set_attr "type" "vecdiv")
a3170dc6
AH		 1982 (set_attr "length" "4")])
1983
1984(define_insn "spe_evdivwu"
1985 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1986 (udiv:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
1987 (match_operand:V2SI 2 "gpc_reg_operand" "r")))
1988 (clobber (reg:SI SPEFSCR_REGNO))]
1989 "TARGET_SPE"
1990 "evdivwu %0,%1,%2"
5e8006fa 1991 [(set_attr "type" "vecdiv")
a3170dc6
AH		 1992 (set_attr "length" "4")])
1993
1994(define_insn "spe_evsplatfi"
1995 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1996 (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 684))]
1997 "TARGET_SPE"
c9b93e1a 1998 "evsplatfi %0,%1"
a3170dc6
AH		 1999 [(set_attr "type" "vecperm")
2000 (set_attr "length" "4")])
2001
2002(define_insn "spe_evsplati"
2003 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2004 (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 685))]
2005 "TARGET_SPE"
c9b93e1a 2006 "evsplati %0,%1"
a3170dc6
AH		 2007 [(set_attr "type" "vecperm")
2008 (set_attr "length" "4")])
2009
2010(define_insn "spe_evstdd"
2011 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2012 (match_operand:QI 1 "immediate_operand" "i")))
2013 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2014 (unspec [(const_int 0)] 686)]
626098f9
AH		 2015 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2016 "evstdd %2,%1*8(%0)"
a3170dc6
AH		 2017 [(set_attr "type" "vecstore")
2018 (set_attr "length" "4")])
2019
2020(define_insn "spe_evstddx"
2021 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2022 (match_operand:SI 1 "gpc_reg_operand" "r")))
2023 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2024 (unspec [(const_int 0)] 687)]
2025 "TARGET_SPE"
2026 "evstddx %2,%0,%1"
2027 [(set_attr "type" "vecstore")
2028 (set_attr "length" "4")])
2029
2030(define_insn "spe_evstdh"
2031 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2032 (match_operand:QI 1 "immediate_operand" "i")))
2033 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2034 (unspec [(const_int 0)] 688)]
626098f9
AH		 2035 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2036 "evstdh %2,%1*8(%0)"
a3170dc6
AH		 2037 [(set_attr "type" "vecstore")
2038 (set_attr "length" "4")])
2039
2040(define_insn "spe_evstdhx"
2041 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2042 (match_operand:SI 1 "gpc_reg_operand" "r")))
2043 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2044 (unspec [(const_int 0)] 689)]
2045 "TARGET_SPE"
2046 "evstdhx %2,%0,%1"
2047 [(set_attr "type" "vecstore")
2048 (set_attr "length" "4")])
2049
2050(define_insn "spe_evstdw"
2051 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2052 (match_operand:QI 1 "immediate_operand" "i")))
2053 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2054 (unspec [(const_int 0)] 690)]
626098f9
AH		 2055 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2056 "evstdw %2,%1*8(%0)"
a3170dc6
AH		 2057 [(set_attr "type" "vecstore")
2058 (set_attr "length" "4")])
2059
2060(define_insn "spe_evstdwx"
2061 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2062 (match_operand:SI 1 "gpc_reg_operand" "r")))
2063 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2064 (unspec [(const_int 0)] 691)]
2065 "TARGET_SPE"
2066 "evstdwx %2,%0,%1"
2067 [(set_attr "type" "vecstore")
2068 (set_attr "length" "4")])
2069
2070(define_insn "spe_evstwhe"
2071 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2072 (match_operand:QI 1 "immediate_operand" "i")))
2073 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2074 (unspec [(const_int 0)] 692)]
626098f9
AH		 2075 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2076 "evstwhe %2,%1*4(%0)"
a3170dc6
AH		 2077 [(set_attr "type" "vecstore")
2078 (set_attr "length" "4")])
2079
2080(define_insn "spe_evstwhex"
2081 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2082 (match_operand:SI 1 "gpc_reg_operand" "r")))
2083 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2084 (unspec [(const_int 0)] 693)]
2085 "TARGET_SPE"
2086 "evstwhex %2,%0,%1"
2087 [(set_attr "type" "vecstore")
2088 (set_attr "length" "4")])
2089
2090(define_insn "spe_evstwho"
2091 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2092 (match_operand:QI 1 "immediate_operand" "i")))
2093 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2094 (unspec [(const_int 0)] 694)]
626098f9
AH		 2095 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2096 "evstwho %2,%1*4(%0)"
a3170dc6
AH		 2097 [(set_attr "type" "vecstore")
2098 (set_attr "length" "4")])
2099
2100(define_insn "spe_evstwhox"
2101 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2102 (match_operand:SI 1 "gpc_reg_operand" "r")))
2103 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2104 (unspec [(const_int 0)] 695)]
2105 "TARGET_SPE"
2106 "evstwhox %2,%0,%1"
2107 [(set_attr "type" "vecstore")
2108 (set_attr "length" "4")])
2109
2110(define_insn "spe_evstwwe"
2111 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2112 (match_operand:QI 1 "immediate_operand" "i")))
2113 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2114 (unspec [(const_int 0)] 696)]
626098f9
AH		 2115 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2116 "evstwwe %2,%1*4(%0)"
a3170dc6
AH		 2117 [(set_attr "type" "vecstore")
2118 (set_attr "length" "4")])
2119
2120(define_insn "spe_evstwwex"
2121 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2122 (match_operand:SI 1 "gpc_reg_operand" "r")))
2123 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2124 (unspec [(const_int 0)] 697)]
2125 "TARGET_SPE"
2126 "evstwwex %2,%0,%1"
2127 [(set_attr "type" "vecstore")
2128 (set_attr "length" "4")])
2129
2130(define_insn "spe_evstwwo"
2131 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2132 (match_operand:QI 1 "immediate_operand" "i")))
2133 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2134 (unspec [(const_int 0)] 698)]
626098f9
AH		 2135 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2136 "evstwwo %2,%1*4(%0)"
a3170dc6
AH		 2137 [(set_attr "type" "vecstore")
2138 (set_attr "length" "4")])
2139
2140(define_insn "spe_evstwwox"
2141 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2142 (match_operand:SI 1 "gpc_reg_operand" "r")))
2143 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2144 (unspec [(const_int 0)] 699)]
2145 "TARGET_SPE"
2146 "evstwwox %2,%0,%1"
2147 [(set_attr "type" "vecstore")
2148 (set_attr "length" "4")])
2149
a3170dc6
AH		 2150;; Vector move instructions.
2151
2152(define_expand "movv2si"
2153 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
2154 (match_operand:V2SI 1 "any_operand" ""))]
2155 "TARGET_SPE"
2156 "{ rs6000_emit_move (operands[0], operands[1], V2SImode); DONE; }")
2157
a3170dc6 2158(define_insn "*movv2si_internal"
d744e06e
AH		 2159 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=m,r,r,r")
2160 (match_operand:V2SI 1 "input_operand" "r,m,r,W"))]
2161 "TARGET_SPE"
2162 "*
2163{
2164 switch (which_alternative)
2165 {
2166 case 0: return \"evstdd%X0 %1,%y0\";
2167 case 1: return \"evldd%X1 %0,%y1\";
2168 case 2: return \"evor %0,%1,%1\";
2169 case 3: return output_vec_const_move (operands);
2170 default: abort ();
2171 }
2172}"
2173 [(set_attr "type" "vecload,vecstore,*,*")
2174 (set_attr "length" "*,*,*,12")])
2175
2176(define_split
2177 [(set (match_operand:V2SI 0 "register_operand" "")
2178 (match_operand:V2SI 1 "zero_constant" ""))]
2179 "TARGET_SPE && reload_completed"
2180 [(set (match_dup 0)
2181 (xor:V2SI (match_dup 0) (match_dup 0)))]
2182 "")
a3170dc6 2183
00a892b8
NC		 2184(define_expand "movv1di"
2185 [(set (match_operand:V1DI 0 "nonimmediate_operand" "")
2186 (match_operand:V1DI 1 "any_operand" ""))]
2187 "TARGET_SPE"
2188 "{ rs6000_emit_move (operands[0], operands[1], V1DImode); DONE; }")
2189
2190(define_insn "*movv1di_internal"
d744e06e
AH		 2191 [(set (match_operand:V1DI 0 "nonimmediate_operand" "=m,r,r,r")
2192 (match_operand:V1DI 1 "input_operand" "r,m,r,W"))]
00a892b8
NC		 2193 "TARGET_SPE"
2194 "@
2195 evstdd%X0 %1,%y0
2196 evldd%X1 %0,%y1
d744e06e
AH		 2197 evor %0,%1,%1
2198 evxor %0,%0,%0"
2199 [(set_attr "type" "vecload,vecstore,*,*")
2200 (set_attr "length" "*,*,*,*")])
00a892b8 2201
a3170dc6
AH		 2202(define_expand "movv4hi"
2203 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
2204 (match_operand:V4HI 1 "any_operand" ""))]
2205 "TARGET_SPE"
2206 "{ rs6000_emit_move (operands[0], operands[1], V4HImode); DONE; }")
2207
2208(define_insn "*movv4hi_internal"
2209 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=m,r,r")
2210 (match_operand:V4HI 1 "input_operand" "r,m,r"))]
2211 "TARGET_SPE"
2212 "@
2213 evstdd%X0 %1,%y0
2214 evldd%X1 %0,%y1
2215 evor %0,%1,%1"
d744e06e 2216 [(set_attr "type" "vecload")])
a3170dc6
AH		 2217
2218(define_expand "movv2sf"
2219 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
2220 (match_operand:V2SF 1 "any_operand" ""))]
2221 "TARGET_SPE"
2222 "{ rs6000_emit_move (operands[0], operands[1], V2SFmode); DONE; }")
2223
2224(define_insn "*movv2sf_internal"
d744e06e
AH		 2225 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,r,r,r")
2226 (match_operand:V2SF 1 "input_operand" "r,m,r,W"))]
a3170dc6
AH		 2227 "TARGET_SPE"
2228 "@
2229 evstdd%X0 %1,%y0
2230 evldd%X1 %0,%y1
d744e06e
AH		 2231 evor %0,%1,%1
2232 evxor %0,%0,%0"
2233 [(set_attr "type" "vecload,vecstore,*,*")
2234 (set_attr "length" "*,*,*,*")])
a3170dc6
AH		 2235
2236(define_insn "spe_evmwhssfaa"
2237 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2238 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2239 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 702))
2240 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2241 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2242 "TARGET_SPE"
2243 "evmwhssfaa %0,%1,%2"
2244 [(set_attr "type" "veccomplex")
2245 (set_attr "length" "4")])
2246
2247(define_insn "spe_evmwhssmaa"
2248 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2249 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2250 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 703))
2251 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2252 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2253 "TARGET_SPE"
2254 "evmwhssmaa %0,%1,%2"
2255 [(set_attr "type" "veccomplex")
2256 (set_attr "length" "4")])
2257
2258(define_insn "spe_evmwhsmfaa"
2259 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2260 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2261 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 704))
54da776f 2262 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2263 "TARGET_SPE"
2264 "evmwhsmfaa %0,%1,%2"
2265 [(set_attr "type" "veccomplex")
2266 (set_attr "length" "4")])
2267
2268(define_insn "spe_evmwhsmiaa"
2269 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2270 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2271 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 705))
54da776f 2272 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2273 "TARGET_SPE"
2274 "evmwhsmiaa %0,%1,%2"
2275 [(set_attr "type" "veccomplex")
2276 (set_attr "length" "4")])
2277
2278(define_insn "spe_evmwhusiaa"
2279 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2280 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2281 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 706))
2282 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2283 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2284 "TARGET_SPE"
2285 "evmwhusiaa %0,%1,%2"
2286 [(set_attr "type" "veccomplex")
2287 (set_attr "length" "4")])
2288
2289(define_insn "spe_evmwhumiaa"
2290 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2291 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2292 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 707))
54da776f 2293 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2294 "TARGET_SPE"
2295 "evmwhumiaa %0,%1,%2"
2296 [(set_attr "type" "veccomplex")
2297 (set_attr "length" "4")])
2298
2299(define_insn "spe_evmwhssfan"
2300 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2301 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2302 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 708))
2303 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2304 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2305 "TARGET_SPE"
2306 "evmwhssfan %0,%1,%2"
2307 [(set_attr "type" "veccomplex")
2308 (set_attr "length" "4")])
2309
2310(define_insn "spe_evmwhssian"
2311 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2312 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2313 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 709))
2314 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2315 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2316 "TARGET_SPE"
2317 "evmwhssian %0,%1,%2"
2318 [(set_attr "type" "veccomplex")
2319 (set_attr "length" "4")])
2320
2321(define_insn "spe_evmwhsmfan"
2322 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2323 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2324 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 710))
54da776f 2325 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2326 "TARGET_SPE"
2327 "evmwhsmfan %0,%1,%2"
2328 [(set_attr "type" "veccomplex")
2329 (set_attr "length" "4")])
2330
2331(define_insn "spe_evmwhsmian"
2332 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2333 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2334 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 711))
54da776f 2335 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2336 "TARGET_SPE"
2337 "evmwhsmian %0,%1,%2"
2338 [(set_attr "type" "veccomplex")
2339 (set_attr "length" "4")])
2340
2341(define_insn "spe_evmwhumian"
2342 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2343 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2344 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 713))
54da776f 2345 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2346 "TARGET_SPE"
2347 "evmwhumian %0,%1,%2"
2348 [(set_attr "type" "veccomplex")
2349 (set_attr "length" "4")])
2350
2351(define_insn "spe_evmwhgssfaa"
2352 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2353 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2354 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 714))
2355 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2356 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2357 "TARGET_SPE"
2358 "evmwhgssfaa %0,%1,%2"
2359 [(set_attr "type" "veccomplex")
2360 (set_attr "length" "4")])
2361
2362(define_insn "spe_evmwhgsmfaa"
2363 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2364 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2365 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 715))
54da776f 2366 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2367 "TARGET_SPE"
2368 "evmwhgsmfaa %0,%1,%2"
2369 [(set_attr "type" "veccomplex")
2370 (set_attr "length" "4")])
2371
2372(define_insn "spe_evmwhgsmiaa"
2373 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2374 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2375 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 716))
54da776f 2376 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2377 "TARGET_SPE"
2378 "evmwhgsmiaa %0,%1,%2"
2379 [(set_attr "type" "veccomplex")
2380 (set_attr "length" "4")])
2381
2382(define_insn "spe_evmwhgumiaa"
2383 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2384 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2385 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 717))
54da776f 2386 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2387 "TARGET_SPE"
2388 "evmwhgumiaa %0,%1,%2"
2389 [(set_attr "type" "veccomplex")
2390 (set_attr "length" "4")])
2391
2392(define_insn "spe_evmwhgssfan"
2393 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2394 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2395 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 718))
2396 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2397 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2398 "TARGET_SPE"
2399 "evmwhgssfan %0,%1,%2"
2400 [(set_attr "type" "veccomplex")
2401 (set_attr "length" "4")])
2402
2403(define_insn "spe_evmwhgsmfan"
2404 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2405 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2406 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 719))
54da776f 2407 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2408 "TARGET_SPE"
2409 "evmwhgsmfan %0,%1,%2"
2410 [(set_attr "type" "veccomplex")
2411 (set_attr "length" "4")])
2412
2413(define_insn "spe_evmwhgsmian"
2414 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2415 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2416 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 720))
54da776f 2417 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2418 "TARGET_SPE"
2419 "evmwhgsmian %0,%1,%2"
2420 [(set_attr "type" "veccomplex")
2421 (set_attr "length" "4")])
2422
2423(define_insn "spe_evmwhgumian"
2424 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2425 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2426 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 721))
54da776f 2427 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2428 "TARGET_SPE"
2429 "evmwhgumian %0,%1,%2"
2430 [(set_attr "type" "veccomplex")
2431 (set_attr "length" "4")])
2432
2433(define_insn "spe_mtspefscr"
2434 [(set (reg:SI SPEFSCR_REGNO)
2435 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2436 722))]
2437 "TARGET_SPE"
2438 "mtspefscr %0"
2439 [(set_attr "type" "vecsimple")])
2440
2441(define_insn "spe_mfspefscr"
2442 [(set (match_operand:SI 0 "register_operand" "=r")
2443 (unspec_volatile:SI [(reg:SI SPEFSCR_REGNO)] 723))]
2444 "TARGET_SPE"
2445 "mfspefscr %0"
2446 [(set_attr "type" "vecsimple")])
2447
2448;; MPC8540 single-precision FP instructions on GPRs.
2449;; We have 2 variants for each. One for IEEE compliant math and one
2450;; for non IEEE compliant math.
2451
2452(define_insn "cmpsfeq_gpr"
2453 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2454 (eq:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2455 (match_operand:SF 2 "gpc_reg_operand" "r")))]
2456 "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
2457 "efscmpeq %0,%1,%2"
5e8006fa 2458 [(set_attr "type" "veccmp")])
a3170dc6
AH		 2459
2460(define_insn "tstsfeq_gpr"
2461 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2462 (eq:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2463 (match_operand:SF 2 "gpc_reg_operand" "r")))]
2464 "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
2465 "efststeq %0,%1,%2"
5e8006fa 2466 [(set_attr "type" "veccmpsimple")])
a3170dc6
AH		 2467
2468(define_insn "cmpsfgt_gpr"
2469 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2470 (gt:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2471 (match_operand:SF 2 "gpc_reg_operand" "r")))]
2472 "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
2473 "efscmpgt %0,%1,%2"
5e8006fa 2474 [(set_attr "type" "veccmp")])
a3170dc6
AH		 2475
2476(define_insn "tstsfgt_gpr"
2477 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2478 (gt:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2479 (match_operand:SF 2 "gpc_reg_operand" "r")))]
2480 "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
2481 "efststgt %0,%1,%2"
5e8006fa 2482 [(set_attr "type" "veccmpsimple")])
a3170dc6
AH		 2483
2484(define_insn "cmpsflt_gpr"
2485 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2486 (lt:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2487 (match_operand:SF 2 "gpc_reg_operand" "r")))]
2488 "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
2489 "efscmplt %0,%1,%2"
5e8006fa 2490 [(set_attr "type" "veccmp")])
a3170dc6
AH		 2491
2492(define_insn "tstsflt_gpr"
2493 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2494 (lt:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2495 (match_operand:SF 2 "gpc_reg_operand" "r")))]
2496 "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
2497 "efststlt %0,%1,%2"
5e8006fa 2498 [(set_attr "type" "veccmpsimple")])
a3170dc6 2499
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