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a3170dc6 1;; e500 SPE description
17caeff2
JM		 2;; Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007
3;; Free Software Foundation, Inc.
a3170dc6
AH		 4;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
5
5de601cf 6;; This file is part of GCC.
a3170dc6 7
5de601cf
NC		 8;; GCC is free software; you can redistribute it and/or modify it
9;; under the terms of the GNU General Public License as published
10;; by the Free Software Foundation; either version 2, or (at your
11;; option) any later version.
a3170dc6 12
5de601cf
NC		 13;; GCC is distributed in the hope that it will be useful, but WITHOUT
14;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16;; License for more details.
a3170dc6
AH		 17
18;; You should have received a copy of the GNU General Public License
5de601cf 19;; along with GCC; see the file COPYING. If not, write to the
39d14dda
KC		 20;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
21;; MA 02110-1301, USA.
a3170dc6
AH		 22
23(define_constants
24 [(SPE_ACC_REGNO 111)
4d4cbc0e
AH		 25 (SPEFSCR_REGNO 112)
26
27 (CMPDFEQ_GPR 1006)
28 (TSTDFEQ_GPR 1007)
29 (CMPDFGT_GPR 1008)
30 (TSTDFGT_GPR 1009)
31 (CMPDFLT_GPR 1010)
32 (TSTDFLT_GPR 1011)
17caeff2
JM		 33 (CMPTFEQ_GPR 1012)
34 (TSTTFEQ_GPR 1013)
35 (CMPTFGT_GPR 1014)
36 (TSTTFGT_GPR 1015)
37 (CMPTFLT_GPR 1016)
38 (TSTTFLT_GPR 1017)
39 (E500_CR_IOR_COMPARE 1018)
4d4cbc0e 40 ])
a3170dc6 41
61c76239
JM		 42;; Modes using a 64-bit register.
43(define_mode_macro SPE64 [DF V4HI V2SF V1DI V2SI])
44
17caeff2
JM		 45;; Likewise, but allow TFmode (two registers) as well.
46(define_mode_macro SPE64TF [DF V4HI V2SF V1DI V2SI TF])
47
48;; DImode and TImode.
49(define_mode_macro DITI [DI TI])
50
a3170dc6
AH		 51(define_insn "*negsf2_gpr"
52 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
53 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
54 "TARGET_HARD_FLOAT && !TARGET_FPRS"
55 "efsneg %0,%1"
5e8006fa 56 [(set_attr "type" "fpsimple")])
a3170dc6
AH		 57
58(define_insn "*abssf2_gpr"
59 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
60 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r")))]
61 "TARGET_HARD_FLOAT && !TARGET_FPRS"
62 "efsabs %0,%1"
5e8006fa 63 [(set_attr "type" "fpsimple")])
a3170dc6 64
fe9c3a97
AH		 65(define_insn "*nabssf2_gpr"
66 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
67 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r"))))]
68 "TARGET_HARD_FLOAT && !TARGET_FPRS"
69 "efsnabs %0,%1"
70 [(set_attr "type" "fpsimple")])
71
a3170dc6
AH		 72(define_insn "*addsf3_gpr"
73 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
74 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
75 (match_operand:SF 2 "gpc_reg_operand" "r")))]
76 "TARGET_HARD_FLOAT && !TARGET_FPRS"
77 "efsadd %0,%1,%2"
78 [(set_attr "type" "fp")])
79
80(define_insn "*subsf3_gpr"
81 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
82 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "r")
83 (match_operand:SF 2 "gpc_reg_operand" "r")))]
84 "TARGET_HARD_FLOAT && !TARGET_FPRS"
85 "efssub %0,%1,%2"
86 [(set_attr "type" "fp")])
87
88(define_insn "*mulsf3_gpr"
89 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
90 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%r")
91 (match_operand:SF 2 "gpc_reg_operand" "r")))]
92 "TARGET_HARD_FLOAT && !TARGET_FPRS"
93 "efsmul %0,%1,%2"
94 [(set_attr "type" "fp")])
95
96(define_insn "*divsf3_gpr"
97 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
98 (div:SF (match_operand:SF 1 "gpc_reg_operand" "r")
99 (match_operand:SF 2 "gpc_reg_operand" "r")))]
100 "TARGET_HARD_FLOAT && !TARGET_FPRS"
101 "efsdiv %0,%1,%2"
5e8006fa 102 [(set_attr "type" "vecfdiv")])
a3170dc6 103
7a2f7870
AH		 104;; Floating point conversion instructions.
105
106(define_insn "fixuns_truncdfsi2"
107 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
108 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
109 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
110 "efdctuiz %0,%1"
111 [(set_attr "type" "fp")])
112
7a2f7870
AH		 113(define_insn "spe_extendsfdf2"
114 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
115 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "r")))]
116 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
117 "efdcfs %0,%1"
118 [(set_attr "type" "fp")])
119
d095928f 120(define_insn "spe_fixuns_truncsfsi2"
a3170dc6 121 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
d095928f 122 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
a3170dc6
AH		 123 "TARGET_HARD_FLOAT && !TARGET_FPRS"
124 "efsctuiz %0,%1"
125 [(set_attr "type" "fp")])
126
d095928f
AH		 127(define_insn "spe_fix_truncsfsi2"
128 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
129 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
130 "TARGET_HARD_FLOAT && !TARGET_FPRS"
131 "efsctsiz %0,%1"
132 [(set_attr "type" "fp")])
a3170dc6 133
7a2f7870
AH		 134(define_insn "spe_fix_truncdfsi2"
135 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
136 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
137 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
138 "efdctsiz %0,%1"
139 [(set_attr "type" "fp")])
140
a3170dc6
AH		 141(define_insn "spe_floatunssisf2"
142 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
143 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
144 "TARGET_HARD_FLOAT && !TARGET_FPRS"
145 "efscfui %0,%1"
146 [(set_attr "type" "fp")])
147
7a2f7870
AH		 148(define_insn "spe_floatunssidf2"
149 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
150 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
151 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
152 "efdcfui %0,%1"
153 [(set_attr "type" "fp")])
154
a3170dc6
AH		 155(define_insn "spe_floatsisf2"
156 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
157 (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
158 "TARGET_HARD_FLOAT && !TARGET_FPRS"
159 "efscfsi %0,%1"
160 [(set_attr "type" "fp")])
161
7a2f7870
AH		 162(define_insn "spe_floatsidf2"
163 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
164 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
165 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
166 "efdcfsi %0,%1"
167 [(set_attr "type" "fp")])
a3170dc6
AH		 168
169;; SPE SIMD instructions
170
171(define_insn "spe_evabs"
172 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
173 (abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
174 "TARGET_SPE"
175 "evabs %0,%1"
176 [(set_attr "type" "vecsimple")
177 (set_attr "length" "4")])
178
179(define_insn "spe_evandc"
180 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
181 (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
182 (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
183 "TARGET_SPE"
184 "evandc %0,%1,%2"
185 [(set_attr "type" "vecsimple")
186 (set_attr "length" "4")])
187
188(define_insn "spe_evand"
189 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
190 (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
191 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
192 "TARGET_SPE"
193 "evand %0,%1,%2"
194 [(set_attr "type" "vecsimple")
195 (set_attr "length" "4")])
196
197;; Vector compare instructions
198
199(define_insn "spe_evcmpeq"
200 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
201 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
202 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 500))]
203 "TARGET_SPE"
204 "evcmpeq %0,%1,%2"
205 [(set_attr "type" "veccmp")
206 (set_attr "length" "4")])
207
208(define_insn "spe_evcmpgts"
209 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
210 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
211 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 501))]
212 "TARGET_SPE"
213 "evcmpgts %0,%1,%2"
214 [(set_attr "type" "veccmp")
215 (set_attr "length" "4")])
216
217(define_insn "spe_evcmpgtu"
218 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
219 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
220 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 502))]
221 "TARGET_SPE"
222 "evcmpgtu %0,%1,%2"
223 [(set_attr "type" "veccmp")
224 (set_attr "length" "4")])
225
226(define_insn "spe_evcmplts"
227 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
228 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
229 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 503))]
230 "TARGET_SPE"
231 "evcmplts %0,%1,%2"
232 [(set_attr "type" "veccmp")
233 (set_attr "length" "4")])
234
235(define_insn "spe_evcmpltu"
236 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
237 (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r")
238 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 504))]
239 "TARGET_SPE"
240 "evcmpltu %0,%1,%2"
241 [(set_attr "type" "veccmp")
242 (set_attr "length" "4")])
243
244;; Floating point vector compare instructions
245
246(define_insn "spe_evfscmpeq"
247 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
248 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
249 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 538))
250 (clobber (reg:SI SPEFSCR_REGNO))]
251 "TARGET_SPE"
252 "evfscmpeq %0,%1,%2"
253 [(set_attr "type" "veccmp")
254 (set_attr "length" "4")])
255
256(define_insn "spe_evfscmpgt"
257 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
258 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
259 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 539))
260 (clobber (reg:SI SPEFSCR_REGNO))]
261 "TARGET_SPE"
262 "evfscmpgt %0,%1,%2"
263 [(set_attr "type" "veccmp")
264 (set_attr "length" "4")])
265
266(define_insn "spe_evfscmplt"
267 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
268 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
269 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 540))
270 (clobber (reg:SI SPEFSCR_REGNO))]
271 "TARGET_SPE"
272 "evfscmplt %0,%1,%2"
273 [(set_attr "type" "veccmp")
274 (set_attr "length" "4")])
275
276(define_insn "spe_evfststeq"
277 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
278 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
279 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 541))]
280 "TARGET_SPE"
281 "evfststeq %0,%1,%2"
282 [(set_attr "type" "veccmp")
283 (set_attr "length" "4")])
284
285(define_insn "spe_evfststgt"
286 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
287 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
288 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 542))]
289 "TARGET_SPE"
290 "evfststgt %0,%1,%2"
291 [(set_attr "type" "veccmp")
292 (set_attr "length" "4")])
293
294(define_insn "spe_evfststlt"
295 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
296 (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r")
297 (match_operand:V2SF 2 "gpc_reg_operand" "r")] 543))]
298 "TARGET_SPE"
299 "evfststlt %0,%1,%2"
300 [(set_attr "type" "veccmp")
301 (set_attr "length" "4")])
302
303;; End of vector compare instructions
304
305(define_insn "spe_evcntlsw"
306 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
307 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 505))]
308 "TARGET_SPE"
309 "evcntlsw %0,%1"
310 [(set_attr "type" "vecsimple")
311 (set_attr "length" "4")])
312
313(define_insn "spe_evcntlzw"
314 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
315 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 506))]
316 "TARGET_SPE"
317 "evcntlzw %0,%1"
318 [(set_attr "type" "vecsimple")
319 (set_attr "length" "4")])
320
321(define_insn "spe_eveqv"
322 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
323 (not:V2SI (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
324 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
325 "TARGET_SPE"
326 "eveqv %0,%1,%2"
327 [(set_attr "type" "vecsimple")
328 (set_attr "length" "4")])
329
330(define_insn "spe_evextsb"
331 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
332 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 507))]
333 "TARGET_SPE"
334 "evextsb %0,%1"
335 [(set_attr "type" "vecsimple")
336 (set_attr "length" "4")])
337
338(define_insn "spe_evextsh"
339 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
340 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 508))]
341 "TARGET_SPE"
342 "evextsh %0,%1"
343 [(set_attr "type" "vecsimple")
344 (set_attr "length" "4")])
345
346(define_insn "spe_evlhhesplat"
626098f9
AH		 347 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
348 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
a3170dc6
AH		 349 (match_operand:QI 2 "immediate_operand" "i"))))
350 (unspec [(const_int 0)] 509)]
626098f9
AH		 351 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
352 "evlhhesplat %0,%2*2(%1)"
a3170dc6
AH		 353 [(set_attr "type" "vecload")
354 (set_attr "length" "4")])
355
356(define_insn "spe_evlhhesplatx"
357 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
358 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
359 (match_operand:SI 2 "gpc_reg_operand" "r"))))
360 (unspec [(const_int 0)] 510)]
361 "TARGET_SPE"
362 "evlhhesplatx %0,%1,%2"
363 [(set_attr "type" "vecload")
364 (set_attr "length" "4")])
365
366(define_insn "spe_evlhhossplat"
367 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
368 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
369 (match_operand:QI 2 "immediate_operand" "i"))))
370 (unspec [(const_int 0)] 511)]
626098f9
AH		 371 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
372 "evlhhossplat %0,%2*2(%1)"
a3170dc6
AH		 373 [(set_attr "type" "vecload")
374 (set_attr "length" "4")])
375
376(define_insn "spe_evlhhossplatx"
377 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
378 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
379 (match_operand:SI 2 "gpc_reg_operand" "r"))))
380 (unspec [(const_int 0)] 512)]
381 "TARGET_SPE"
382 "evlhhossplatx %0,%1,%2"
383 [(set_attr "type" "vecload")
384 (set_attr "length" "4")])
385
386(define_insn "spe_evlhhousplat"
387 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
388 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
389 (match_operand:QI 2 "immediate_operand" "i"))))
390 (unspec [(const_int 0)] 513)]
626098f9
AH		 391 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
392 "evlhhousplat %0,%2*2(%1)"
a3170dc6
AH		 393 [(set_attr "type" "vecload")
394 (set_attr "length" "4")])
395
396(define_insn "spe_evlhhousplatx"
397 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
398 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
399 (match_operand:SI 2 "gpc_reg_operand" "r"))))
400 (unspec [(const_int 0)] 514)]
401 "TARGET_SPE"
402 "evlhhousplatx %0,%1,%2"
403 [(set_attr "type" "vecload")
404 (set_attr "length" "4")])
405
406(define_insn "spe_evlwhsplat"
407 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
408 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
409 (match_operand:QI 2 "immediate_operand" "i"))))
410 (unspec [(const_int 0)] 515)]
626098f9
AH		 411 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
412 "evlwhsplat %0,%2*4(%1)"
a3170dc6
AH		 413 [(set_attr "type" "vecload")
414 (set_attr "length" "4")])
415
416(define_insn "spe_evlwhsplatx"
417 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
418 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
419 (match_operand:SI 2 "gpc_reg_operand" "r"))))
420 (unspec [(const_int 0)] 516)]
421 "TARGET_SPE"
422 "evlwhsplatx %0,%1,%2"
423 [(set_attr "type" "vecload")
424 (set_attr "length" "4")])
425
426(define_insn "spe_evlwwsplat"
427 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
428 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
429 (match_operand:QI 2 "immediate_operand" "i"))))
430 (unspec [(const_int 0)] 517)]
626098f9
AH		 431 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
432 "evlwwsplat %0,%2*4(%1)"
a3170dc6
AH		 433 [(set_attr "type" "vecload")
434 (set_attr "length" "4")])
435
436(define_insn "spe_evlwwsplatx"
437 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
438 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
439 (match_operand:SI 2 "gpc_reg_operand" "r"))))
440 (unspec [(const_int 0)] 518)]
441 "TARGET_SPE"
442 "evlwwsplatx %0,%1,%2"
443 [(set_attr "type" "vecload")
444 (set_attr "length" "4")])
445
446(define_insn "spe_evmergehi"
447 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
448 (vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
449 (vec_select:V2SI
450 (match_operand:V2SI 2 "gpc_reg_operand" "r")
451 (parallel [(const_int 1)
452 (const_int 0)]))
453 (const_int 2)))]
454 "TARGET_SPE"
455 "evmergehi %0,%1,%2"
456 [(set_attr "type" "vecsimple")
457 (set_attr "length" "4")])
458
459(define_insn "spe_evmergehilo"
460 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
461 (vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
462 (match_operand:V2SI 2 "gpc_reg_operand" "r")
463 (const_int 2)))]
464 "TARGET_SPE"
465 "evmergehilo %0,%1,%2"
466 [(set_attr "type" "vecsimple")
467 (set_attr "length" "4")])
468
469(define_insn "spe_evmergelo"
470 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
471 (vec_merge:V2SI (vec_select:V2SI
472 (match_operand:V2SI 1 "gpc_reg_operand" "r")
473 (parallel [(const_int 1)
474 (const_int 0)]))
475 (match_operand:V2SI 2 "gpc_reg_operand" "r")
476 (const_int 2)))]
477 "TARGET_SPE"
478 "evmergelo %0,%1,%2"
479 [(set_attr "type" "vecsimple")
480 (set_attr "length" "4")])
481
482(define_insn "spe_evmergelohi"
483 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
484 (vec_merge:V2SI (vec_select:V2SI
485 (match_operand:V2SI 1 "gpc_reg_operand" "r")
486 (parallel [(const_int 1)
487 (const_int 0)]))
488 (vec_select:V2SI
489 (match_operand:V2SI 2 "gpc_reg_operand" "r")
490 (parallel [(const_int 1)
491 (const_int 0)]))
492 (const_int 2)))]
493 "TARGET_SPE"
494 "evmergelohi %0,%1,%2"
495 [(set_attr "type" "vecsimple")
496 (set_attr "length" "4")])
497
498(define_insn "spe_evnand"
499 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
500 (not:V2SI (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
501 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
502 "TARGET_SPE"
503 "evnand %0,%1,%2"
504 [(set_attr "type" "vecsimple")
505 (set_attr "length" "4")])
506
6a599451 507(define_insn "negv2si2"
a3170dc6
AH		 508 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
509 (neg:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
510 "TARGET_SPE"
511 "evneg %0,%1"
512 [(set_attr "type" "vecsimple")
513 (set_attr "length" "4")])
514
515(define_insn "spe_evnor"
516 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
517 (not:V2SI (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
518 (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
519 "TARGET_SPE"
520 "evnor %0,%1,%2"
521 [(set_attr "type" "vecsimple")
522 (set_attr "length" "4")])
523
524(define_insn "spe_evorc"
525 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
526 (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
527 (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))]
528 "TARGET_SPE"
529 "evorc %0,%1,%2"
530 [(set_attr "type" "vecsimple")
531 (set_attr "length" "4")])
532
533(define_insn "spe_evor"
534 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
535 (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
536 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
537 "TARGET_SPE"
538 "evor %0,%1,%2"
539 [(set_attr "type" "vecsimple")
540 (set_attr "length" "4")])
541
542(define_insn "spe_evrlwi"
543 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
544 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
545 (match_operand:QI 2 "immediate_operand" "i")] 519))]
546 "TARGET_SPE"
78872ad9 547 "evrlwi %0,%1,%2"
a3170dc6
AH		 548 [(set_attr "type" "vecsimple")
549 (set_attr "length" "4")])
550
551(define_insn "spe_evrlw"
552 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
553 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
554 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 520))]
555 "TARGET_SPE"
556 "evrlw %0,%1,%2"
557 [(set_attr "type" "veccomplex")
558 (set_attr "length" "4")])
559
560(define_insn "spe_evrndw"
561 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
562 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 521))]
563 "TARGET_SPE"
564 "evrndw %0,%1"
565 [(set_attr "type" "vecsimple")
566 (set_attr "length" "4")])
567
568(define_insn "spe_evsel"
569 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
570 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
571 (match_operand:V2SI 2 "gpc_reg_operand" "r")
572 (match_operand:CC 3 "cc_reg_operand" "y")] 522))]
573 "TARGET_SPE"
574 "evsel %0,%1,%2,%3"
575 [(set_attr "type" "veccmp")
576 (set_attr "length" "4")])
577
578(define_insn "spe_evsel_fs"
579 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
580 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")
581 (match_operand:V2SF 2 "gpc_reg_operand" "r")
582 (match_operand:CC 3 "cc_reg_operand" "y")] 725))]
583 "TARGET_SPE"
584 "evsel %0,%1,%2,%3"
585 [(set_attr "type" "veccmp")
586 (set_attr "length" "4")])
587
588(define_insn "spe_evslwi"
589 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
590 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
591 (match_operand:QI 2 "immediate_operand" "i")]
592 523))]
593 "TARGET_SPE"
594 "evslwi %0,%1,%2"
595 [(set_attr "type" "vecsimple")
596 (set_attr "length" "4")])
597
598(define_insn "spe_evslw"
599 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
600 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
601 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 524))]
602 "TARGET_SPE"
603 "evslw %0,%1,%2"
604 [(set_attr "type" "vecsimple")
605 (set_attr "length" "4")])
606
607(define_insn "spe_evsrwis"
608 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
609 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
610 (match_operand:QI 2 "immediate_operand" "i")]
611 525))]
612 "TARGET_SPE"
613 "evsrwis %0,%1,%2"
614 [(set_attr "type" "vecsimple")
615 (set_attr "length" "4")])
616
617(define_insn "spe_evsrwiu"
618 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
619 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
620 (match_operand:QI 2 "immediate_operand" "i")]
621 526))]
622 "TARGET_SPE"
623 "evsrwiu %0,%1,%2"
624 [(set_attr "type" "vecsimple")
625 (set_attr "length" "4")])
626
627(define_insn "spe_evsrws"
628 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
629 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
630 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 527))]
631 "TARGET_SPE"
632 "evsrws %0,%1,%2"
633 [(set_attr "type" "vecsimple")
634 (set_attr "length" "4")])
635
636(define_insn "spe_evsrwu"
637 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
638 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
639 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 528))]
640 "TARGET_SPE"
641 "evsrwu %0,%1,%2"
642 [(set_attr "type" "vecsimple")
643 (set_attr "length" "4")])
644
626098f9
AH		 645;; vector xors
646
647(define_insn "xorv2si3"
a3170dc6
AH		 648 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
649 (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
650 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
651 "TARGET_SPE"
652 "evxor %0,%1,%2"
653 [(set_attr "type" "vecsimple")
654 (set_attr "length" "4")])
655
626098f9
AH		 656(define_insn "xorv4hi3"
657 [(set (match_operand:V4HI 0 "gpc_reg_operand" "=r")
658 (xor:V4HI (match_operand:V4HI 1 "gpc_reg_operand" "r")
659 (match_operand:V4HI 2 "gpc_reg_operand" "r")))]
660 "TARGET_SPE"
661 "evxor %0,%1,%2"
662 [(set_attr "type" "vecsimple")
663 (set_attr "length" "4")])
664
665(define_insn "xorv1di3"
666 [(set (match_operand:V1DI 0 "gpc_reg_operand" "=r")
667 (xor:V1DI (match_operand:V1DI 1 "gpc_reg_operand" "r")
668 (match_operand:V1DI 2 "gpc_reg_operand" "r")))]
669 "TARGET_SPE"
670 "evxor %0,%1,%2"
671 [(set_attr "type" "vecsimple")
672 (set_attr "length" "4")])
673
674;; end of vector xors
675
a3170dc6
AH		 676(define_insn "spe_evfsabs"
677 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
678 (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
679 "TARGET_SPE"
680 "evfsabs %0,%1"
5e8006fa 681 [(set_attr "type" "vecsimple")
a3170dc6
AH		 682 (set_attr "length" "4")])
683
684(define_insn "spe_evfsadd"
685 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
686 (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
687 (match_operand:V2SF 2 "gpc_reg_operand" "r")))
688 (clobber (reg:SI SPEFSCR_REGNO))]
689 "TARGET_SPE"
690 "evfsadd %0,%1,%2"
691 [(set_attr "type" "vecfloat")
692 (set_attr "length" "4")])
693
694(define_insn "spe_evfscfsf"
695 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
696 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 529))]
697 "TARGET_SPE"
698 "evfscfsf %0,%1"
699 [(set_attr "type" "vecfloat")
700 (set_attr "length" "4")])
701
702(define_insn "spe_evfscfsi"
e7a9b208
AH		 703 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
704 (float:V2SF (match_operand:V2SI 1 "gpc_reg_operand" "r")))]
a3170dc6
AH		 705 "TARGET_SPE"
706 "evfscfsi %0,%1"
707 [(set_attr "type" "vecfloat")
708 (set_attr "length" "4")])
709
710(define_insn "spe_evfscfuf"
711 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
712 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 530))]
713 "TARGET_SPE"
714 "evfscfuf %0,%1"
715 [(set_attr "type" "vecfloat")
716 (set_attr "length" "4")])
717
718(define_insn "spe_evfscfui"
719 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
720 (unspec:V2SF [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 701))]
721 "TARGET_SPE"
722 "evfscfui %0,%1"
723 [(set_attr "type" "vecfloat")
724 (set_attr "length" "4")])
725
726(define_insn "spe_evfsctsf"
727 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
728 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 531))]
729 "TARGET_SPE"
730 "evfsctsf %0,%1"
731 [(set_attr "type" "vecfloat")
732 (set_attr "length" "4")])
733
734(define_insn "spe_evfsctsi"
735 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
736 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 532))]
737 "TARGET_SPE"
738 "evfsctsi %0,%1"
739 [(set_attr "type" "vecfloat")
740 (set_attr "length" "4")])
741
742(define_insn "spe_evfsctsiz"
743 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
744 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 533))]
745 "TARGET_SPE"
746 "evfsctsiz %0,%1"
747 [(set_attr "type" "vecfloat")
748 (set_attr "length" "4")])
749
750(define_insn "spe_evfsctuf"
751 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
752 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 534))]
753 "TARGET_SPE"
754 "evfsctuf %0,%1"
755 [(set_attr "type" "vecfloat")
756 (set_attr "length" "4")])
757
758(define_insn "spe_evfsctui"
759 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
760 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 535))]
761 "TARGET_SPE"
762 "evfsctui %0,%1"
763 [(set_attr "type" "vecfloat")
764 (set_attr "length" "4")])
765
766(define_insn "spe_evfsctuiz"
767 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
768 (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 536))]
769 "TARGET_SPE"
770 "evfsctuiz %0,%1"
771 [(set_attr "type" "vecfloat")
772 (set_attr "length" "4")])
773
774(define_insn "spe_evfsdiv"
775 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
776 (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
777 (match_operand:V2SF 2 "gpc_reg_operand" "r")))
778 (clobber (reg:SI SPEFSCR_REGNO))]
779 "TARGET_SPE"
780 "evfsdiv %0,%1,%2"
5e8006fa 781 [(set_attr "type" "vecfdiv")
a3170dc6
AH		 782 (set_attr "length" "4")])
783
784(define_insn "spe_evfsmul"
785 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
786 (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
787 (match_operand:V2SF 2 "gpc_reg_operand" "r")))
788 (clobber (reg:SI SPEFSCR_REGNO))]
789 "TARGET_SPE"
790 "evfsmul %0,%1,%2"
791 [(set_attr "type" "vecfloat")
792 (set_attr "length" "4")])
793
794(define_insn "spe_evfsnabs"
795 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
796 (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 537))]
797 "TARGET_SPE"
798 "evfsnabs %0,%1"
5e8006fa 799 [(set_attr "type" "vecsimple")
a3170dc6
AH		 800 (set_attr "length" "4")])
801
802(define_insn "spe_evfsneg"
803 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
804 (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))]
805 "TARGET_SPE"
806 "evfsneg %0,%1"
5e8006fa 807 [(set_attr "type" "vecsimple")
a3170dc6
AH		 808 (set_attr "length" "4")])
809
810(define_insn "spe_evfssub"
811 [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r")
812 (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")
813 (match_operand:V2SF 2 "gpc_reg_operand" "r")))
814 (clobber (reg:SI SPEFSCR_REGNO))]
815 "TARGET_SPE"
816 "evfssub %0,%1,%2"
817 [(set_attr "type" "vecfloat")
818 (set_attr "length" "4")])
819
820;; SPE SIMD load instructions.
821
b6d08ca1 822;; Only the hardware engineer who designed the SPE understands the
a3170dc6
AH		 823;; plethora of load and store instructions ;-). We have no way of
824;; differentiating between them with RTL so use an unspec of const_int 0
825;; to avoid identical RTL.
826
827(define_insn "spe_evldd"
828 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
829 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
830 (match_operand:QI 2 "immediate_operand" "i"))))
831 (unspec [(const_int 0)] 544)]
832 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
626098f9 833 "evldd %0,%2*8(%1)"
a3170dc6
AH		 834 [(set_attr "type" "vecload")
835 (set_attr "length" "4")])
836
837(define_insn "spe_evlddx"
838 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
839 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
840 (match_operand:SI 2 "gpc_reg_operand" "r"))))
841 (unspec [(const_int 0)] 545)]
842 "TARGET_SPE"
843 "evlddx %0,%1,%2"
844 [(set_attr "type" "vecload")
845 (set_attr "length" "4")])
846
847(define_insn "spe_evldh"
848 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
849 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
850 (match_operand:QI 2 "immediate_operand" "i"))))
851 (unspec [(const_int 0)] 546)]
852 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
626098f9 853 "evldh %0,%2*8(%1)"
a3170dc6
AH		 854 [(set_attr "type" "vecload")
855 (set_attr "length" "4")])
856
857(define_insn "spe_evldhx"
858 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
859 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
860 (match_operand:SI 2 "gpc_reg_operand" "r"))))
861 (unspec [(const_int 0)] 547)]
862 "TARGET_SPE"
863 "evldhx %0,%1,%2"
864 [(set_attr "type" "vecload")
865 (set_attr "length" "4")])
866
867(define_insn "spe_evldw"
868 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
869 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
870 (match_operand:QI 2 "immediate_operand" "i"))))
871 (unspec [(const_int 0)] 548)]
626098f9
AH		 872 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
873 "evldw %0,%2*8(%1)"
a3170dc6
AH		 874 [(set_attr "type" "vecload")
875 (set_attr "length" "4")])
876
877(define_insn "spe_evldwx"
878 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
879 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
880 (match_operand:SI 2 "gpc_reg_operand" "r"))))
881 (unspec [(const_int 0)] 549)]
882 "TARGET_SPE"
883 "evldwx %0,%1,%2"
884 [(set_attr "type" "vecload")
885 (set_attr "length" "4")])
886
887(define_insn "spe_evlwhe"
888 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
889 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
890 (match_operand:QI 2 "immediate_operand" "i"))))
891 (unspec [(const_int 0)] 550)]
626098f9
AH		 892 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
893 "evlwhe %0,%2*4(%1)"
a3170dc6
AH		 894 [(set_attr "type" "vecload")
895 (set_attr "length" "4")])
896
897(define_insn "spe_evlwhex"
898 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
899 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
900 (match_operand:SI 2 "gpc_reg_operand" "r"))))
901 (unspec [(const_int 0)] 551)]
902 "TARGET_SPE"
903 "evlwhex %0,%1,%2"
904 [(set_attr "type" "vecload")
905 (set_attr "length" "4")])
906
907(define_insn "spe_evlwhos"
908 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
909 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
910 (match_operand:QI 2 "immediate_operand" "i"))))
911 (unspec [(const_int 0)] 552)]
626098f9
AH		 912 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
913 "evlwhos %0,%2*4(%1)"
a3170dc6
AH		 914 [(set_attr "type" "vecload")
915 (set_attr "length" "4")])
916
917(define_insn "spe_evlwhosx"
918 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
919 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
920 (match_operand:SI 2 "gpc_reg_operand" "r"))))
921 (unspec [(const_int 0)] 553)]
922 "TARGET_SPE"
923 "evlwhosx %0,%1,%2"
924 [(set_attr "type" "vecload")
925 (set_attr "length" "4")])
926
927(define_insn "spe_evlwhou"
928 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
929 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
930 (match_operand:QI 2 "immediate_operand" "i"))))
931 (unspec [(const_int 0)] 554)]
626098f9
AH		 932 "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31"
933 "evlwhou %0,%2*4(%1)"
a3170dc6
AH		 934 [(set_attr "type" "vecload")
935 (set_attr "length" "4")])
936
937(define_insn "spe_evlwhoux"
938 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
939 (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
940 (match_operand:SI 2 "gpc_reg_operand" "r"))))
941 (unspec [(const_int 0)] 555)]
942 "TARGET_SPE"
943 "evlwhoux %0,%1,%2"
944 [(set_attr "type" "vecload")
945 (set_attr "length" "4")])
946
947(define_insn "spe_brinc"
948 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
949 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "r")
950 (match_operand:SI 2 "gpc_reg_operand" "r")] 556))]
951 "TARGET_SPE"
952 "brinc %0,%1,%2"
5e8006fa 953 [(set_attr "type" "brinc")
a3170dc6
AH		 954 (set_attr "length" "4")])
955
956(define_insn "spe_evmhegsmfaa"
957 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
958 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
959 (match_operand:V2SI 2 "gpc_reg_operand" "r")
960 (reg:V2SI SPE_ACC_REGNO)] 557))
54da776f 961 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 962 "TARGET_SPE"
963 "evmhegsmfaa %0,%1,%2"
964 [(set_attr "type" "veccomplex")
965 (set_attr "length" "4")])
966
967(define_insn "spe_evmhegsmfan"
968 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
969 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
970 (match_operand:V2SI 2 "gpc_reg_operand" "r")
971 (reg:V2SI SPE_ACC_REGNO)] 558))
54da776f 972 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 973 "TARGET_SPE"
974 "evmhegsmfan %0,%1,%2"
975 [(set_attr "type" "veccomplex")
976 (set_attr "length" "4")])
977
978(define_insn "spe_evmhegsmiaa"
979 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
980 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
981 (match_operand:V2SI 2 "gpc_reg_operand" "r")
982 (reg:V2SI SPE_ACC_REGNO)] 559))
54da776f 983 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 984 "TARGET_SPE"
985 "evmhegsmiaa %0,%1,%2"
986 [(set_attr "type" "veccomplex")
987 (set_attr "length" "4")])
988
989(define_insn "spe_evmhegsmian"
990 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
991 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
992 (match_operand:V2SI 2 "gpc_reg_operand" "r")
993 (reg:V2SI SPE_ACC_REGNO)] 560))
54da776f 994 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 995 "TARGET_SPE"
996 "evmhegsmian %0,%1,%2"
997 [(set_attr "type" "veccomplex")
998 (set_attr "length" "4")])
999
1000(define_insn "spe_evmhegumiaa"
1001 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1002 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1003 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1004 (reg:V2SI SPE_ACC_REGNO)] 561))
54da776f 1005 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1006 "TARGET_SPE"
1007 "evmhegumiaa %0,%1,%2"
1008 [(set_attr "type" "veccomplex")
1009 (set_attr "length" "4")])
1010
1011(define_insn "spe_evmhegumian"
1012 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1013 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1014 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1015 (reg:V2SI SPE_ACC_REGNO)] 562))
54da776f 1016 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1017 "TARGET_SPE"
1018 "evmhegumian %0,%1,%2"
1019 [(set_attr "type" "veccomplex")
1020 (set_attr "length" "4")])
1021
1022(define_insn "spe_evmhesmfaaw"
1023 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1024 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1025 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1026 (reg:V2SI SPE_ACC_REGNO)] 563))
54da776f 1027 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1028 "TARGET_SPE"
1029 "evmhesmfaaw %0,%1,%2"
1030 [(set_attr "type" "veccomplex")
1031 (set_attr "length" "4")])
1032
1033(define_insn "spe_evmhesmfanw"
1034 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1035 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1036 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1037 (reg:V2SI SPE_ACC_REGNO)] 564))
54da776f 1038 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1039 "TARGET_SPE"
1040 "evmhesmfanw %0,%1,%2"
1041 [(set_attr "type" "veccomplex")
1042 (set_attr "length" "4")])
1043
1044(define_insn "spe_evmhesmfa"
1045 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1046 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1047 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 565))
54da776f 1048 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1049 "TARGET_SPE"
1050 "evmhesmfa %0,%1,%2"
1051 [(set_attr "type" "veccomplex")
1052 (set_attr "length" "4")])
1053
1054(define_insn "spe_evmhesmf"
1055 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1056 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1057 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 566))]
1058 "TARGET_SPE"
1059 "evmhesmf %0,%1,%2"
1060 [(set_attr "type" "veccomplex")
1061 (set_attr "length" "4")])
1062
1063(define_insn "spe_evmhesmiaaw"
1064 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1065 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1066 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1067 (reg:V2SI SPE_ACC_REGNO)] 567))
54da776f 1068 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1069 "TARGET_SPE"
1070 "evmhesmiaaw %0,%1,%2"
1071 [(set_attr "type" "veccomplex")
1072 (set_attr "length" "4")])
1073
1074(define_insn "spe_evmhesmianw"
1075 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1076 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1077 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1078 (reg:V2SI SPE_ACC_REGNO)] 568))
54da776f 1079 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1080 "TARGET_SPE"
1081 "evmhesmianw %0,%1,%2"
1082 [(set_attr "type" "veccomplex")
1083 (set_attr "length" "4")])
1084
1085(define_insn "spe_evmhesmia"
1086 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1087 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1088 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 569))
54da776f 1089 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1090 "TARGET_SPE"
1091 "evmhesmia %0,%1,%2"
1092 [(set_attr "type" "veccomplex")
1093 (set_attr "length" "4")])
1094
1095(define_insn "spe_evmhesmi"
1096 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1097 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1098 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 570))]
1099 "TARGET_SPE"
1100 "evmhesmi %0,%1,%2"
1101 [(set_attr "type" "veccomplex")
1102 (set_attr "length" "4")])
1103
1104(define_insn "spe_evmhessfaaw"
1105 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1106 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1107 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1108 (reg:V2SI SPE_ACC_REGNO)] 571))
1109 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1110 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1111 "TARGET_SPE"
1112 "evmhessfaaw %0,%1,%2"
1113 [(set_attr "type" "veccomplex")
1114 (set_attr "length" "4")])
1115
1116(define_insn "spe_evmhessfanw"
1117 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1118 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1119 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1120 (reg:V2SI SPE_ACC_REGNO)] 572))
1121 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1122 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1123 "TARGET_SPE"
1124 "evmhessfanw %0,%1,%2"
1125 [(set_attr "type" "veccomplex")
1126 (set_attr "length" "4")])
1127
1128(define_insn "spe_evmhessfa"
1129 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1130 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1131 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 573))
1132 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1133 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1134 "TARGET_SPE"
1135 "evmhessfa %0,%1,%2"
1136 [(set_attr "type" "veccomplex")
1137 (set_attr "length" "4")])
1138
1139(define_insn "spe_evmhessf"
1140 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1141 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1142 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 574))
1143 (clobber (reg:SI SPEFSCR_REGNO))]
1144 "TARGET_SPE"
1145 "evmhessf %0,%1,%2"
1146 [(set_attr "type" "veccomplex")
1147 (set_attr "length" "4")])
1148
1149(define_insn "spe_evmhessiaaw"
1150 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1151 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1152 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1153 (reg:V2SI SPE_ACC_REGNO)] 575))
1154 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1155 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6 1156 "TARGET_SPE"
c9b93e1a 1157 "evmhessiaaw %0,%1,%2"
a3170dc6
AH		 1158 [(set_attr "type" "veccomplex")
1159 (set_attr "length" "4")])
1160
1161(define_insn "spe_evmhessianw"
1162 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1163 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1164 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1165 (reg:V2SI SPE_ACC_REGNO)] 576))
1166 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1167 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1168 "TARGET_SPE"
1169 "evmhessianw %0,%1,%2"
1170 [(set_attr "type" "veccomplex")
1171 (set_attr "length" "4")])
1172
1173(define_insn "spe_evmheumiaaw"
1174 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1175 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1176 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1177 (reg:V2SI SPE_ACC_REGNO)] 577))
54da776f 1178 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1179 "TARGET_SPE"
1180 "evmheumiaaw %0,%1,%2"
1181 [(set_attr "type" "veccomplex")
1182 (set_attr "length" "4")])
1183
1184(define_insn "spe_evmheumianw"
1185 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1186 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1187 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1188 (reg:V2SI SPE_ACC_REGNO)] 578))
54da776f 1189 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1190 "TARGET_SPE"
1191 "evmheumianw %0,%1,%2"
1192 [(set_attr "type" "veccomplex")
1193 (set_attr "length" "4")])
1194
1195(define_insn "spe_evmheumia"
1196 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1197 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1198 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 579))
54da776f 1199 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1200 "TARGET_SPE"
1201 "evmheumia %0,%1,%2"
1202 [(set_attr "type" "veccomplex")
1203 (set_attr "length" "4")])
1204
1205(define_insn "spe_evmheumi"
1206 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1207 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1208 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 580))]
1209 "TARGET_SPE"
1210 "evmheumi %0,%1,%2"
1211 [(set_attr "type" "veccomplex")
1212 (set_attr "length" "4")])
1213
1214(define_insn "spe_evmheusiaaw"
1215 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1216 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1217 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1218 (reg:V2SI SPE_ACC_REGNO)] 581))
1219 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1220 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1221 "TARGET_SPE"
1222 "evmheusiaaw %0,%1,%2"
1223 [(set_attr "type" "veccomplex")
1224 (set_attr "length" "4")])
1225
1226(define_insn "spe_evmheusianw"
1227 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1228 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1229 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1230 (reg:V2SI SPE_ACC_REGNO)] 582))
1231 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1232 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1233 "TARGET_SPE"
1234 "evmheusianw %0,%1,%2"
1235 [(set_attr "type" "veccomplex")
1236 (set_attr "length" "4")])
1237
1238(define_insn "spe_evmhogsmfaa"
1239 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1240 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1241 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1242 (reg:V2SI SPE_ACC_REGNO)] 583))
54da776f 1243 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1244 "TARGET_SPE"
1245 "evmhogsmfaa %0,%1,%2"
1246 [(set_attr "type" "veccomplex")
1247 (set_attr "length" "4")])
1248
1249(define_insn "spe_evmhogsmfan"
1250 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1251 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1252 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1253 (reg:V2SI SPE_ACC_REGNO)] 584))
54da776f 1254 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1255 "TARGET_SPE"
1256 "evmhogsmfan %0,%1,%2"
1257 [(set_attr "type" "veccomplex")
1258 (set_attr "length" "4")])
1259
1260(define_insn "spe_evmhogsmiaa"
1261 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1262 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1263 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1264 (reg:V2SI SPE_ACC_REGNO)] 585))
54da776f 1265 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1266 "TARGET_SPE"
1267 "evmhogsmiaa %0,%1,%2"
1268 [(set_attr "type" "veccomplex")
1269 (set_attr "length" "4")])
1270
1271(define_insn "spe_evmhogsmian"
1272 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1273 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1274 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1275 (reg:V2SI SPE_ACC_REGNO)] 586))
54da776f 1276 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1277 "TARGET_SPE"
1278 "evmhogsmian %0,%1,%2"
1279 [(set_attr "type" "veccomplex")
1280 (set_attr "length" "4")])
1281
1282(define_insn "spe_evmhogumiaa"
1283 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1284 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1285 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1286 (reg:V2SI SPE_ACC_REGNO)] 587))
54da776f 1287 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1288 "TARGET_SPE"
1289 "evmhogumiaa %0,%1,%2"
1290 [(set_attr "type" "veccomplex")
1291 (set_attr "length" "4")])
1292
1293(define_insn "spe_evmhogumian"
1294 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1295 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1296 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1297 (reg:V2SI SPE_ACC_REGNO)] 588))
54da776f 1298 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1299 "TARGET_SPE"
1300 "evmhogumian %0,%1,%2"
1301 [(set_attr "type" "veccomplex")
1302 (set_attr "length" "4")])
1303
1304(define_insn "spe_evmhosmfaaw"
1305 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1306 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1307 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1308 (reg:V2SI SPE_ACC_REGNO)] 589))
54da776f 1309 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1310 "TARGET_SPE"
1311 "evmhosmfaaw %0,%1,%2"
1312 [(set_attr "type" "veccomplex")
1313 (set_attr "length" "4")])
1314
1315(define_insn "spe_evmhosmfanw"
1316 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1317 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1318 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1319 (reg:V2SI SPE_ACC_REGNO)] 590))
54da776f 1320 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1321 "TARGET_SPE"
1322 "evmhosmfanw %0,%1,%2"
1323 [(set_attr "type" "veccomplex")
1324 (set_attr "length" "4")])
1325
1326(define_insn "spe_evmhosmfa"
1327 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1328 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1329 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 591))]
1330 "TARGET_SPE"
1331 "evmhosmfa %0,%1,%2"
1332 [(set_attr "type" "veccomplex")
1333 (set_attr "length" "4")])
1334
1335(define_insn "spe_evmhosmf"
1336 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1337 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1338 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 592))
54da776f 1339 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1340 "TARGET_SPE"
1341 "evmhosmf %0,%1,%2"
1342 [(set_attr "type" "veccomplex")
1343 (set_attr "length" "4")])
1344
1345(define_insn "spe_evmhosmiaaw"
1346 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1347 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1348 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1349 (reg:V2SI SPE_ACC_REGNO)] 593))
54da776f 1350 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1351 "TARGET_SPE"
1352 "evmhosmiaaw %0,%1,%2"
1353 [(set_attr "type" "veccomplex")
1354 (set_attr "length" "4")])
1355
1356(define_insn "spe_evmhosmianw"
1357 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1358 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1359 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1360 (reg:V2SI SPE_ACC_REGNO)] 594))
54da776f 1361 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1362 "TARGET_SPE"
1363 "evmhosmianw %0,%1,%2"
1364 [(set_attr "type" "veccomplex")
1365 (set_attr "length" "4")])
1366
1367(define_insn "spe_evmhosmia"
1368 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1369 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1370 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 595))
54da776f 1371 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1372 "TARGET_SPE"
1373 "evmhosmia %0,%1,%2"
1374 [(set_attr "type" "veccomplex")
1375 (set_attr "length" "4")])
1376
1377(define_insn "spe_evmhosmi"
1378 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1379 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1380 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 596))]
1381 "TARGET_SPE"
1382 "evmhosmi %0,%1,%2"
1383 [(set_attr "type" "veccomplex")
1384 (set_attr "length" "4")])
1385
1386(define_insn "spe_evmhossfaaw"
1387 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1388 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1389 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1390 (reg:V2SI SPE_ACC_REGNO)] 597))
1391 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1392 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1393 "TARGET_SPE"
1394 "evmhossfaaw %0,%1,%2"
1395 [(set_attr "type" "veccomplex")
1396 (set_attr "length" "4")])
1397
1398(define_insn "spe_evmhossfanw"
1399 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1400 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1401 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1402 (reg:V2SI SPE_ACC_REGNO)] 598))
1403 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1404 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1405 "TARGET_SPE"
1406 "evmhossfanw %0,%1,%2"
1407 [(set_attr "type" "veccomplex")
1408 (set_attr "length" "4")])
1409
1410(define_insn "spe_evmhossfa"
1411 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1412 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1413 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1414 (reg:V2SI SPE_ACC_REGNO)] 599))
1415 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1416 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1417 "TARGET_SPE"
1418 "evmhossfa %0,%1,%2"
1419 [(set_attr "type" "veccomplex")
1420 (set_attr "length" "4")])
1421
1422(define_insn "spe_evmhossf"
1423 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1424 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1425 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 600))
1426 (clobber (reg:SI SPEFSCR_REGNO))]
1427 "TARGET_SPE"
1428 "evmhossf %0,%1,%2"
1429 [(set_attr "type" "veccomplex")
1430 (set_attr "length" "4")])
1431
1432(define_insn "spe_evmhossiaaw"
1433 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1434 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1435 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1436 (reg:V2SI SPE_ACC_REGNO)] 601))
1437 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1438 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1439 "TARGET_SPE"
1440 "evmhossiaaw %0,%1,%2"
1441 [(set_attr "type" "veccomplex")
1442 (set_attr "length" "4")])
1443
1444(define_insn "spe_evmhossianw"
1445 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1446 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1447 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1448 (reg:V2SI SPE_ACC_REGNO)] 602))
1449 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1450 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1451 "TARGET_SPE"
1452 "evmhossianw %0,%1,%2"
1453 [(set_attr "type" "veccomplex")
1454 (set_attr "length" "4")])
1455
1456(define_insn "spe_evmhoumiaaw"
1457 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1458 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1459 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1460 (reg:V2SI SPE_ACC_REGNO)] 603))
54da776f 1461 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1462 "TARGET_SPE"
1463 "evmhoumiaaw %0,%1,%2"
1464 [(set_attr "type" "veccomplex")
1465 (set_attr "length" "4")])
1466
1467(define_insn "spe_evmhoumianw"
1468 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1469 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1470 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1471 (reg:V2SI SPE_ACC_REGNO)] 604))
54da776f 1472 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1473 "TARGET_SPE"
1474 "evmhoumianw %0,%1,%2"
1475 [(set_attr "type" "veccomplex")
1476 (set_attr "length" "4")])
1477
1478(define_insn "spe_evmhoumia"
1479 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1480 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1481 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 605))
54da776f 1482 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1483 "TARGET_SPE"
1484 "evmhoumia %0,%1,%2"
1485 [(set_attr "type" "veccomplex")
1486 (set_attr "length" "4")])
1487
1488(define_insn "spe_evmhoumi"
1489 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1490 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1491 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 606))]
1492 "TARGET_SPE"
1493 "evmhoumi %0,%1,%2"
1494 [(set_attr "type" "veccomplex")
1495 (set_attr "length" "4")])
1496
1497(define_insn "spe_evmhousiaaw"
1498 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1499 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1500 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1501 (reg:V2SI SPE_ACC_REGNO)] 607))
1502 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1503 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1504 "TARGET_SPE"
1505 "evmhousiaaw %0,%1,%2"
1506 [(set_attr "type" "veccomplex")
1507 (set_attr "length" "4")])
1508
1509(define_insn "spe_evmhousianw"
1510 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1511 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1512 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1513 (reg:V2SI SPE_ACC_REGNO)] 608))
1514 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1515 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1516 "TARGET_SPE"
1517 "evmhousianw %0,%1,%2"
1518 [(set_attr "type" "veccomplex")
1519 (set_attr "length" "4")])
1520
1521(define_insn "spe_evmmlssfa"
1522 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1523 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1524 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 609))]
1525 "TARGET_SPE"
1526 "evmmlssfa %0,%1,%2"
1527 [(set_attr "type" "veccomplex")
1528 (set_attr "length" "4")])
1529
1530(define_insn "spe_evmmlssf"
1531 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1532 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1533 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 610))]
1534 "TARGET_SPE"
1535 "evmmlssf %0,%1,%2"
1536 [(set_attr "type" "veccomplex")
1537 (set_attr "length" "4")])
1538
1539(define_insn "spe_evmwhsmfa"
1540 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1541 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1542 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 611))
54da776f 1543 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1544 "TARGET_SPE"
1545 "evmwhsmfa %0,%1,%2"
1546 [(set_attr "type" "veccomplex")
1547 (set_attr "length" "4")])
1548
1549(define_insn "spe_evmwhsmf"
1550 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1551 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1552 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 612))]
1553 "TARGET_SPE"
1554 "evmwhsmf %0,%1,%2"
1555 [(set_attr "type" "veccomplex")
1556 (set_attr "length" "4")])
1557
1558(define_insn "spe_evmwhsmia"
1559 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1560 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1561 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 613))
54da776f 1562 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1563 "TARGET_SPE"
1564 "evmwhsmia %0,%1,%2"
1565 [(set_attr "type" "veccomplex")
1566 (set_attr "length" "4")])
1567
1568(define_insn "spe_evmwhsmi"
1569 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1570 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1571 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 614))]
1572 "TARGET_SPE"
1573 "evmwhsmi %0,%1,%2"
1574 [(set_attr "type" "veccomplex")
1575 (set_attr "length" "4")])
1576
1577(define_insn "spe_evmwhssfa"
1578 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1579 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1580 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 615))
1581 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1582 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1583 "TARGET_SPE"
1584 "evmwhssfa %0,%1,%2"
1585 [(set_attr "type" "veccomplex")
1586 (set_attr "length" "4")])
1587
1588(define_insn "spe_evmwhusian"
1589 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1590 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1591 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 626))]
1592 "TARGET_SPE"
1593 "evmwhusian %0,%1,%2"
1594 [(set_attr "type" "veccomplex")
1595 (set_attr "length" "4")])
1596
1597(define_insn "spe_evmwhssf"
1598 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1599 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1600 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 628))
1601 (clobber (reg:SI SPEFSCR_REGNO))]
1602 "TARGET_SPE"
1603 "evmwhssf %0,%1,%2"
1604 [(set_attr "type" "veccomplex")
1605 (set_attr "length" "4")])
1606
1607(define_insn "spe_evmwhumia"
1608 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1609 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1610 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 629))
54da776f 1611 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1612 "TARGET_SPE"
1613 "evmwhumia %0,%1,%2"
1614 [(set_attr "type" "veccomplex")
1615 (set_attr "length" "4")])
1616
1617(define_insn "spe_evmwhumi"
1618 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1619 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1620 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 630))]
1621 "TARGET_SPE"
1622 "evmwhumi %0,%1,%2"
1623 [(set_attr "type" "veccomplex")
1624 (set_attr "length" "4")])
1625
a3170dc6
AH		 1626(define_insn "spe_evmwlsmiaaw"
1627 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1628 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1629 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1630 (reg:V2SI SPE_ACC_REGNO)] 635))
54da776f 1631 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1632 "TARGET_SPE"
1633 "evmwlsmiaaw %0,%1,%2"
1634 [(set_attr "type" "veccomplex")
1635 (set_attr "length" "4")])
1636
1637(define_insn "spe_evmwlsmianw"
1638 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1639 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1640 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1641 (reg:V2SI SPE_ACC_REGNO)] 636))
54da776f 1642 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1643 "TARGET_SPE"
1644 "evmwlsmianw %0,%1,%2"
a3170dc6
AH		 1645 [(set_attr "type" "veccomplex")
1646 (set_attr "length" "4")])
1647
1648(define_insn "spe_evmwlssiaaw"
1649 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1650 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1651 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1652 (reg:V2SI SPE_ACC_REGNO)] 641))
1653 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1654 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1655 "TARGET_SPE"
1656 "evmwlssiaaw %0,%1,%2"
1657 [(set_attr "type" "veccomplex")
1658 (set_attr "length" "4")])
1659
1660(define_insn "spe_evmwlssianw"
1661 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1662 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1663 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1664 (reg:V2SI SPE_ACC_REGNO)] 642))
1665 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1666 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1667 "TARGET_SPE"
1668 "evmwlssianw %0,%1,%2"
1669 [(set_attr "type" "veccomplex")
1670 (set_attr "length" "4")])
1671
1672(define_insn "spe_evmwlumiaaw"
1673 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1674 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1675 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1676 (reg:V2SI SPE_ACC_REGNO)] 643))
54da776f 1677 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1678 "TARGET_SPE"
1679 "evmwlumiaaw %0,%1,%2"
1680 [(set_attr "type" "veccomplex")
1681 (set_attr "length" "4")])
1682
1683(define_insn "spe_evmwlumianw"
1684 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1685 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1686 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1687 (reg:V2SI SPE_ACC_REGNO)] 644))
54da776f 1688 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1689 "TARGET_SPE"
1690 "evmwlumianw %0,%1,%2"
1691 [(set_attr "type" "veccomplex")
1692 (set_attr "length" "4")])
1693
1694(define_insn "spe_evmwlumia"
1695 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1696 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1697 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 645))
54da776f 1698 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1699 "TARGET_SPE"
1700 "evmwlumia %0,%1,%2"
1701 [(set_attr "type" "veccomplex")
1702 (set_attr "length" "4")])
1703
1704(define_insn "spe_evmwlumi"
1705 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1706 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1707 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 646))]
1708 "TARGET_SPE"
1709 "evmwlumi %0,%1,%2"
1710 [(set_attr "type" "veccomplex")
1711 (set_attr "length" "4")])
1712
1713(define_insn "spe_evmwlusiaaw"
1714 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1715 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1716 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1717 (reg:V2SI SPE_ACC_REGNO)] 647))
1718 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1719 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1720 "TARGET_SPE"
1721 "evmwlusiaaw %0,%1,%2"
1722 [(set_attr "type" "veccomplex")
1723 (set_attr "length" "4")])
1724
1725(define_insn "spe_evmwlusianw"
1726 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1727 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1728 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1729 (reg:V2SI SPE_ACC_REGNO)] 648))
1730 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1731 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1732 "TARGET_SPE"
1733 "evmwlusianw %0,%1,%2"
1734 [(set_attr "type" "veccomplex")
1735 (set_attr "length" "4")])
1736
1737(define_insn "spe_evmwsmfaa"
1738 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1739 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1740 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1741 (reg:V2SI SPE_ACC_REGNO)] 649))
54da776f 1742 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1743 "TARGET_SPE"
1744 "evmwsmfaa %0,%1,%2"
1745 [(set_attr "type" "veccomplex")
1746 (set_attr "length" "4")])
1747
1748(define_insn "spe_evmwsmfan"
1749 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1750 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1751 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1752 (reg:V2SI SPE_ACC_REGNO)] 650))
54da776f 1753 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1754 "TARGET_SPE"
1755 "evmwsmfan %0,%1,%2"
1756 [(set_attr "type" "veccomplex")
1757 (set_attr "length" "4")])
1758
1759(define_insn "spe_evmwsmfa"
1760 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1761 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1762 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 651))
54da776f 1763 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1764 "TARGET_SPE"
1765 "evmwsmfa %0,%1,%2"
1766 [(set_attr "type" "veccomplex")
1767 (set_attr "length" "4")])
1768
1769(define_insn "spe_evmwsmf"
1770 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1771 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1772 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 652))]
1773 "TARGET_SPE"
1774 "evmwsmf %0,%1,%2"
1775 [(set_attr "type" "veccomplex")
1776 (set_attr "length" "4")])
1777
1778(define_insn "spe_evmwsmiaa"
1779 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1780 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1781 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1782 (reg:V2SI SPE_ACC_REGNO)] 653))
54da776f 1783 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1784 "TARGET_SPE"
1785 "evmwsmiaa %0,%1,%2"
1786 [(set_attr "type" "veccomplex")
1787 (set_attr "length" "4")])
1788
1789(define_insn "spe_evmwsmian"
1790 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1791 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1792 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1793 (reg:V2SI SPE_ACC_REGNO)] 654))
54da776f 1794 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1795 "TARGET_SPE"
1796 "evmwsmian %0,%1,%2"
1797 [(set_attr "type" "veccomplex")
1798 (set_attr "length" "4")])
1799
1800(define_insn "spe_evmwsmia"
1801 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1802 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1803 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 655))
54da776f 1804 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1805 "TARGET_SPE"
1806 "evmwsmia %0,%1,%2"
1807 [(set_attr "type" "veccomplex")
1808 (set_attr "length" "4")])
1809
1810(define_insn "spe_evmwsmi"
1811 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1812 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1813 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 656))]
1814 "TARGET_SPE"
1815 "evmwsmi %0,%1,%2"
1816 [(set_attr "type" "veccomplex")
1817 (set_attr "length" "4")])
1818
1819(define_insn "spe_evmwssfaa"
1820 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1821 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1822 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1823 (reg:V2SI SPE_ACC_REGNO)] 657))
1824 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1825 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1826 "TARGET_SPE"
1827 "evmwssfaa %0,%1,%2"
1828 [(set_attr "type" "veccomplex")
1829 (set_attr "length" "4")])
1830
1831(define_insn "spe_evmwssfan"
1832 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1833 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1834 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1835 (reg:V2SI SPE_ACC_REGNO)] 658))
1836 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1837 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1838 "TARGET_SPE"
1839 "evmwssfan %0,%1,%2"
1840 [(set_attr "type" "veccomplex")
1841 (set_attr "length" "4")])
1842
1843(define_insn "spe_evmwssfa"
1844 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1845 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1846 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 659))
1847 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1848 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1849 "TARGET_SPE"
1850 "evmwssfa %0,%1,%2"
1851 [(set_attr "type" "veccomplex")
1852 (set_attr "length" "4")])
1853
1854(define_insn "spe_evmwssf"
1855 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1856 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1857 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 660))
1858 (clobber (reg:SI SPEFSCR_REGNO))]
1859 "TARGET_SPE"
1860 "evmwssf %0,%1,%2"
1861 [(set_attr "type" "veccomplex")
1862 (set_attr "length" "4")])
1863
1864(define_insn "spe_evmwumiaa"
1865 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1866 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1867 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1868 (reg:V2SI SPE_ACC_REGNO)] 661))
54da776f 1869 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1870 "TARGET_SPE"
1871 "evmwumiaa %0,%1,%2"
1872 [(set_attr "type" "veccomplex")
1873 (set_attr "length" "4")])
1874
1875(define_insn "spe_evmwumian"
1876 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1877 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1878 (match_operand:V2SI 2 "gpc_reg_operand" "r")
1879 (reg:V2SI SPE_ACC_REGNO)] 662))
54da776f 1880 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1881 "TARGET_SPE"
1882 "evmwumian %0,%1,%2"
1883 [(set_attr "type" "veccomplex")
1884 (set_attr "length" "4")])
1885
1886(define_insn "spe_evmwumia"
1887 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1888 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1889 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 663))
54da776f 1890 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1891 "TARGET_SPE"
1892 "evmwumia %0,%1,%2"
1893 [(set_attr "type" "veccomplex")
1894 (set_attr "length" "4")])
1895
1896(define_insn "spe_evmwumi"
1897 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1898 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1899 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 664))]
1900 "TARGET_SPE"
1901 "evmwumi %0,%1,%2"
1902 [(set_attr "type" "veccomplex")
1903 (set_attr "length" "4")])
1904
1905(define_insn "spe_evaddw"
1906 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1907 (plus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
1908 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
1909 "TARGET_SPE"
1910 "evaddw %0,%1,%2"
5e8006fa 1911 [(set_attr "type" "vecsimple")
a3170dc6
AH		 1912 (set_attr "length" "4")])
1913
1914(define_insn "spe_evaddusiaaw"
1915 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1916 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1917 (reg:V2SI SPE_ACC_REGNO)] 673))
1918 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1919 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1920 "TARGET_SPE"
1921 "evaddusiaaw %0,%1"
1922 [(set_attr "type" "veccomplex")
1923 (set_attr "length" "4")])
1924
1925(define_insn "spe_evaddumiaaw"
1926 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1927 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1928 (reg:V2SI SPE_ACC_REGNO)] 674))
54da776f 1929 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1930 "TARGET_SPE"
1931 "evaddumiaaw %0,%1"
1932 [(set_attr "type" "veccomplex")
1933 (set_attr "length" "4")])
1934
1935(define_insn "spe_evaddssiaaw"
1936 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1937 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1938 (reg:V2SI SPE_ACC_REGNO)] 675))
1939 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1940 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1941 "TARGET_SPE"
1942 "evaddssiaaw %0,%1"
1943 [(set_attr "type" "veccomplex")
1944 (set_attr "length" "4")])
1945
1946(define_insn "spe_evaddsmiaaw"
1947 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1948 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1949 (reg:V2SI SPE_ACC_REGNO)] 676))
54da776f 1950 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1951 "TARGET_SPE"
1952 "evaddsmiaaw %0,%1"
1953 [(set_attr "type" "veccomplex")
1954 (set_attr "length" "4")])
1955
1956(define_insn "spe_evaddiw"
1957 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1958 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1959 (match_operand:QI 2 "immediate_operand" "i")] 677))]
1960 "TARGET_SPE"
1961 "evaddiw %0,%1,%2"
5e8006fa 1962 [(set_attr "type" "vecsimple")
a3170dc6
AH		 1963 (set_attr "length" "4")])
1964
1965(define_insn "spe_evsubifw"
1966 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1967 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1968 (match_operand:QI 2 "immediate_operand" "i")] 678))]
1969 "TARGET_SPE"
1970 "evsubifw %0,%2,%1"
1971 [(set_attr "type" "veccomplex")
1972 (set_attr "length" "4")])
1973
1974(define_insn "spe_evsubfw"
1975 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1976 (minus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
1977 (match_operand:V2SI 2 "gpc_reg_operand" "r")))]
1978 "TARGET_SPE"
12850cf2 1979 "evsubfw %0,%2,%1"
a3170dc6
AH		 1980 [(set_attr "type" "veccomplex")
1981 (set_attr "length" "4")])
1982
1983(define_insn "spe_evsubfusiaaw"
1984 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1985 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1986 (reg:V2SI SPE_ACC_REGNO)] 679))
1987 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 1988 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1989 "TARGET_SPE"
1990 "evsubfusiaaw %0,%1"
1991 [(set_attr "type" "veccomplex")
1992 (set_attr "length" "4")])
1993
1994(define_insn "spe_evsubfumiaaw"
1995 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
1996 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
1997 (reg:V2SI SPE_ACC_REGNO)] 680))
54da776f 1998 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 1999 "TARGET_SPE"
2000 "evsubfumiaaw %0,%1"
2001 [(set_attr "type" "veccomplex")
2002 (set_attr "length" "4")])
2003
2004(define_insn "spe_evsubfssiaaw"
2005 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2006 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2007 (reg:V2SI SPE_ACC_REGNO)] 681))
2008 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2009 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2010 "TARGET_SPE"
2011 "evsubfssiaaw %0,%1"
2012 [(set_attr "type" "veccomplex")
2013 (set_attr "length" "4")])
2014
2015(define_insn "spe_evsubfsmiaaw"
2016 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2017 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2018 (reg:V2SI SPE_ACC_REGNO)] 682))
54da776f 2019 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2020 "TARGET_SPE"
2021 "evsubfsmiaaw %0,%1"
2022 [(set_attr "type" "veccomplex")
2023 (set_attr "length" "4")])
2024
2025(define_insn "spe_evmra"
2026 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2027 (match_operand:V2SI 1 "gpc_reg_operand" "r"))
c3021e5d
AH		 2028 (set (reg:V2SI SPE_ACC_REGNO)
2029 (unspec:V2SI [(match_dup 1)] 726))]
a3170dc6
AH		 2030 "TARGET_SPE"
2031 "evmra %0,%1"
2032 [(set_attr "type" "veccomplex")
2033 (set_attr "length" "4")])
2034
2035(define_insn "spe_evdivws"
2036 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2037 (div:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
2038 (match_operand:V2SI 2 "gpc_reg_operand" "r")))
2039 (clobber (reg:SI SPEFSCR_REGNO))]
2040 "TARGET_SPE"
2041 "evdivws %0,%1,%2"
5e8006fa 2042 [(set_attr "type" "vecdiv")
a3170dc6
AH		 2043 (set_attr "length" "4")])
2044
2045(define_insn "spe_evdivwu"
2046 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2047 (udiv:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")
2048 (match_operand:V2SI 2 "gpc_reg_operand" "r")))
2049 (clobber (reg:SI SPEFSCR_REGNO))]
2050 "TARGET_SPE"
2051 "evdivwu %0,%1,%2"
5e8006fa 2052 [(set_attr "type" "vecdiv")
a3170dc6
AH		 2053 (set_attr "length" "4")])
2054
2055(define_insn "spe_evsplatfi"
2056 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2057 (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 684))]
2058 "TARGET_SPE"
c9b93e1a 2059 "evsplatfi %0,%1"
a3170dc6
AH		 2060 [(set_attr "type" "vecperm")
2061 (set_attr "length" "4")])
2062
2063(define_insn "spe_evsplati"
2064 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2065 (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 685))]
2066 "TARGET_SPE"
c9b93e1a 2067 "evsplati %0,%1"
a3170dc6
AH		 2068 [(set_attr "type" "vecperm")
2069 (set_attr "length" "4")])
2070
2071(define_insn "spe_evstdd"
2072 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2073 (match_operand:QI 1 "immediate_operand" "i")))
2074 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2075 (unspec [(const_int 0)] 686)]
626098f9
AH		 2076 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2077 "evstdd %2,%1*8(%0)"
a3170dc6
AH		 2078 [(set_attr "type" "vecstore")
2079 (set_attr "length" "4")])
2080
2081(define_insn "spe_evstddx"
2082 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2083 (match_operand:SI 1 "gpc_reg_operand" "r")))
2084 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2085 (unspec [(const_int 0)] 687)]
2086 "TARGET_SPE"
2087 "evstddx %2,%0,%1"
2088 [(set_attr "type" "vecstore")
2089 (set_attr "length" "4")])
2090
2091(define_insn "spe_evstdh"
2092 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2093 (match_operand:QI 1 "immediate_operand" "i")))
2094 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2095 (unspec [(const_int 0)] 688)]
626098f9
AH		 2096 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2097 "evstdh %2,%1*8(%0)"
a3170dc6
AH		 2098 [(set_attr "type" "vecstore")
2099 (set_attr "length" "4")])
2100
2101(define_insn "spe_evstdhx"
2102 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2103 (match_operand:SI 1 "gpc_reg_operand" "r")))
2104 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2105 (unspec [(const_int 0)] 689)]
2106 "TARGET_SPE"
2107 "evstdhx %2,%0,%1"
2108 [(set_attr "type" "vecstore")
2109 (set_attr "length" "4")])
2110
2111(define_insn "spe_evstdw"
2112 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2113 (match_operand:QI 1 "immediate_operand" "i")))
2114 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2115 (unspec [(const_int 0)] 690)]
626098f9
AH		 2116 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2117 "evstdw %2,%1*8(%0)"
a3170dc6
AH		 2118 [(set_attr "type" "vecstore")
2119 (set_attr "length" "4")])
2120
2121(define_insn "spe_evstdwx"
2122 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2123 (match_operand:SI 1 "gpc_reg_operand" "r")))
2124 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2125 (unspec [(const_int 0)] 691)]
2126 "TARGET_SPE"
2127 "evstdwx %2,%0,%1"
2128 [(set_attr "type" "vecstore")
2129 (set_attr "length" "4")])
2130
2131(define_insn "spe_evstwhe"
2132 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2133 (match_operand:QI 1 "immediate_operand" "i")))
2134 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2135 (unspec [(const_int 0)] 692)]
626098f9
AH		 2136 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2137 "evstwhe %2,%1*4(%0)"
a3170dc6
AH		 2138 [(set_attr "type" "vecstore")
2139 (set_attr "length" "4")])
2140
2141(define_insn "spe_evstwhex"
2142 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2143 (match_operand:SI 1 "gpc_reg_operand" "r")))
2144 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2145 (unspec [(const_int 0)] 693)]
2146 "TARGET_SPE"
2147 "evstwhex %2,%0,%1"
2148 [(set_attr "type" "vecstore")
2149 (set_attr "length" "4")])
2150
2151(define_insn "spe_evstwho"
2152 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2153 (match_operand:QI 1 "immediate_operand" "i")))
2154 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2155 (unspec [(const_int 0)] 694)]
626098f9
AH		 2156 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2157 "evstwho %2,%1*4(%0)"
a3170dc6
AH		 2158 [(set_attr "type" "vecstore")
2159 (set_attr "length" "4")])
2160
2161(define_insn "spe_evstwhox"
2162 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2163 (match_operand:SI 1 "gpc_reg_operand" "r")))
2164 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2165 (unspec [(const_int 0)] 695)]
2166 "TARGET_SPE"
2167 "evstwhox %2,%0,%1"
2168 [(set_attr "type" "vecstore")
2169 (set_attr "length" "4")])
2170
2171(define_insn "spe_evstwwe"
2172 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2173 (match_operand:QI 1 "immediate_operand" "i")))
2174 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2175 (unspec [(const_int 0)] 696)]
626098f9
AH		 2176 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2177 "evstwwe %2,%1*4(%0)"
a3170dc6
AH		 2178 [(set_attr "type" "vecstore")
2179 (set_attr "length" "4")])
2180
2181(define_insn "spe_evstwwex"
2182 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2183 (match_operand:SI 1 "gpc_reg_operand" "r")))
2184 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2185 (unspec [(const_int 0)] 697)]
2186 "TARGET_SPE"
2187 "evstwwex %2,%0,%1"
2188 [(set_attr "type" "vecstore")
2189 (set_attr "length" "4")])
2190
2191(define_insn "spe_evstwwo"
2192 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2193 (match_operand:QI 1 "immediate_operand" "i")))
2194 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2195 (unspec [(const_int 0)] 698)]
626098f9
AH		 2196 "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31"
2197 "evstwwo %2,%1*4(%0)"
a3170dc6
AH		 2198 [(set_attr "type" "vecstore")
2199 (set_attr "length" "4")])
2200
2201(define_insn "spe_evstwwox"
2202 [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b")
2203 (match_operand:SI 1 "gpc_reg_operand" "r")))
2204 (match_operand:V2SI 2 "gpc_reg_operand" "r"))
2205 (unspec [(const_int 0)] 699)]
2206 "TARGET_SPE"
2207 "evstwwox %2,%0,%1"
2208 [(set_attr "type" "vecstore")
2209 (set_attr "length" "4")])
2210
7a2f7870 2211;; Double-precision floating point instructions.
54b695e7
AH		 2212
2213;; FIXME: Add o=r option.
17caeff2
JM		 2214(define_insn "*frob_<SPE64:mode>_<DITI:mode>"
2215 [(set (match_operand:SPE64 0 "nonimmediate_operand" "=r,r")
2216 (subreg:SPE64 (match_operand:DITI 1 "input_operand" "r,m") 0))]
2217 "(TARGET_E500_DOUBLE && <SPE64:MODE>mode == DFmode)
2218 || (TARGET_SPE && <SPE64:MODE>mode != DFmode)"
2219 "@
2220 evmergelo %0,%1,%L1
2221 evldd%X1 %0,%y1")
2222
2223(define_insn "*frob_tf_ti"
2224 [(set (match_operand:TF 0 "gpc_reg_operand" "=r")
2225 (subreg:TF (match_operand:TI 1 "gpc_reg_operand" "r") 0))]
54b695e7 2226 "TARGET_E500_DOUBLE"
b6fda43f
JM		 2227 "evmergelo %0,%1,%L1\;evmergelo %L0,%Y1,%Z1"
2228 [(set_attr "length" "8")])
17caeff2
JM		 2229
2230(define_insn "*frob_<mode>_di_2"
2231 [(set (subreg:DI (match_operand:SPE64TF 0 "nonimmediate_operand" "+&r,r") 0)
2232 (match_operand:DI 1 "input_operand" "r,m"))]
2233 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2234 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
54b695e7 2235 "@
d2952008 2236 evmergelo %0,%1,%L1
54b695e7
AH		 2237 evldd%X1 %0,%y1")
2238
17caeff2
JM		 2239(define_insn "*frob_tf_di_8_2"
2240 [(set (subreg:DI (match_operand:TF 0 "nonimmediate_operand" "+&r,r") 8)
2241 (match_operand:DI 1 "input_operand" "r,m"))]
d2952008 2242 "TARGET_E500_DOUBLE"
17caeff2
JM		 2243 "@
2244 evmergelo %L0,%1,%L1
2245 evldd%X1 %L0,%y1")
2246
2247(define_insn "*frob_di_<mode>"
2248 [(set (match_operand:DI 0 "nonimmediate_operand" "=&r")
2249 (subreg:DI (match_operand:SPE64TF 1 "input_operand" "r") 0))]
2250 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2251 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
d2952008 2252 "evmergehi %0,%1,%1\;mr %L0,%1"
54b695e7
AH		 2253 [(set_attr "length" "8")])
2254
17caeff2
JM		 2255(define_insn "*frob_ti_tf"
2256 [(set (match_operand:TI 0 "nonimmediate_operand" "=&r")
2257 (subreg:TI (match_operand:TF 1 "input_operand" "r") 0))]
54b695e7 2258 "TARGET_E500_DOUBLE"
b6fda43f
JM		 2259 "evmergehi %0,%1,%1\;mr %L0,%1\;evmergehi %Y0,%L1,%L1\;mr %Z0,%L1"
2260 [(set_attr "length" "16")])
17caeff2
JM		 2261
2262(define_insn "*frob_<DITI:mode>_<SPE64:mode>_2"
2263 [(set (subreg:SPE64 (match_operand:DITI 0 "register_operand" "+&r,r") 0)
2264 (match_operand:SPE64 1 "input_operand" "r,m"))]
2265 "(TARGET_E500_DOUBLE && <SPE64:MODE>mode == DFmode)
2266 || (TARGET_SPE && <SPE64:MODE>mode != DFmode)"
d2952008
GR		 2267 "*
2268{
2269 switch (which_alternative)
2270 {
2271 default:
2272 gcc_unreachable ();
2273 case 0:
2274 return \"evmergehi %0,%1,%1\;mr %L0,%1\";
2275 case 1:
198bc787
JM		 2276 /* If the address is not offsettable we need to load the whole
2277 doubleword into a 64-bit register and then copy the high word
2278 to form the correct output layout. */
2279 if (!offsettable_nonstrict_memref_p (operands[1]))
2280 return \"evldd%X1 %L0,%y1\;evmergehi %0,%L0,%L0\";
d2952008
GR		 2281 /* If the low-address word is used in the address, we must load
2282 it last. Otherwise, load it first. Note that we cannot have
2283 auto-increment in that case since the address register is
2284 known to be dead. */
2285 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2286 operands[1], 0))
2287 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
2288 else
2289 return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\";
2290 }
2291}"
2292 [(set_attr "length" "8,8")])
54b695e7 2293
17caeff2
JM		 2294; As the above, but TImode at offset 8.
2295(define_insn "*frob_ti_<mode>_8_2"
2296 [(set (subreg:SPE64 (match_operand:TI 0 "register_operand" "+&r,r") 8)
2297 (match_operand:SPE64 1 "input_operand" "r,m"))]
2298 "(TARGET_E500_DOUBLE && <MODE>mode == DFmode)
2299 || (TARGET_SPE && <MODE>mode != DFmode)"
2300 "*
2301{
2302 switch (which_alternative)
2303 {
2304 default:
2305 gcc_unreachable ();
2306 case 0:
2307 return \"evmergehi %Y0,%1,%1\;mr %Z0,%1\";
2308 case 1:
2309 if (!offsettable_nonstrict_memref_p (operands[1]))
2310 return \"evldd%X1 %Z0,%y1\;evmergehi %Y0,%Z0,%Z0\";
2311 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2312 operands[1], 0))
2313 return \"{l|lwz} %Z0,%L1\;{l|lwz} %Y0,%1\";
2314 else
2315 return \"{l%U1%X1|lwz%U1%X1} %Y0,%1\;{l|lwz} %Z0,%L1\";
2316 }
2317}"
2318 [(set_attr "length" "8,8")])
2319
2320(define_insn "*frob_ti_tf_2"
2321 [(set (subreg:TF (match_operand:TI 0 "gpc_reg_operand" "=&r") 0)
a3f8aaa5 2322 (match_operand:TF 1 "input_operand" "r"))]
17caeff2 2323 "TARGET_E500_DOUBLE"
b6fda43f
JM		 2324 "evmergehi %0,%1,%1\;mr %L0,%1\;evmergehi %Y0,%L1,%L1\;mr %Z0,%L1"
2325 [(set_attr "length" "16")])
17caeff2 2326
61c76239 2327(define_insn "*mov_si<mode>_e500_subreg0"
17caeff2 2328 [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,&r") 0)
61c76239 2329 (match_operand:SI 1 "input_operand" "r,m"))]
17caeff2
JM		 2330 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2331 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
61c76239
JM		 2332 "@
2333 evmergelo %0,%1,%0
b6fda43f
JM		 2334 evmergelohi %0,%0,%0\;{l%U1%X1|lwz%U1%X1} %0,%1\;evmergelohi %0,%0,%0"
2335 [(set_attr "length" "4,12")])
61c76239
JM		 2336
2337;; ??? Could use evstwwe for memory stores in some cases, depending on
2338;; the offset.
2339(define_insn "*mov_si<mode>_e500_subreg0_2"
2340 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
17caeff2
JM		 2341 (subreg:SI (match_operand:SPE64TF 1 "register_operand" "+r,&r") 0))]
2342 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2343 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
61c76239
JM		 2344 "@
2345 evmergehi %0,%0,%1
b6fda43f
JM		 2346 evmergelohi %1,%1,%1\;{st%U0%X0|stw%U0%X0} %1,%0"
2347 [(set_attr "length" "4,8")])
54b695e7 2348
61c76239 2349(define_insn "*mov_si<mode>_e500_subreg4"
17caeff2 2350 [(set (subreg:SI (match_operand:SPE64TF 0 "register_operand" "+r,r") 4)
61c76239 2351 (match_operand:SI 1 "input_operand" "r,m"))]
17caeff2
JM		 2352 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2353 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
61c76239
JM		 2354 "@
2355 mr %0,%1
2356 {l%U1%X1|lwz%U1%X1} %0,%1")
2357
2358(define_insn "*mov_si<mode>_e500_subreg4_2"
2359 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
17caeff2
JM		 2360 (subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 4))]
2361 "(TARGET_E500_DOUBLE && (<MODE>mode == DFmode || <MODE>mode == TFmode))
2362 || (TARGET_SPE && <MODE>mode != DFmode && <MODE>mode != TFmode)"
61c76239
JM		 2363 "@
2364 mr %0,%1
2365 {st%U0%X0|stw%U0%X0} %1,%0")
54b695e7 2366
17caeff2
JM		 2367(define_insn "*mov_sitf_e500_subreg8"
2368 [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,&r") 8)
2369 (match_operand:SI 1 "input_operand" "r,m"))]
2370 "TARGET_E500_DOUBLE"
2371 "@
2372 evmergelo %L0,%1,%L0
b6fda43f
JM		 2373 evmergelohi %L0,%L0,%L0\;{l%U1%X1|lwz%U1%X1} %L0,%1\;evmergelohi %L0,%L0,%L0"
2374 [(set_attr "length" "4,12")])
17caeff2
JM		 2375
2376(define_insn "*mov_sitf_e500_subreg8_2"
2377 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
2378 (subreg:SI (match_operand:TF 1 "register_operand" "+r,&r") 8))]
2379 "TARGET_E500_DOUBLE"
2380 "@
2381 evmergehi %0,%0,%L1
b6fda43f
JM		 2382 evmergelohi %L1,%L1,%L1\;{st%U0%X0|stw%U0%X0} %L1,%0"
2383 [(set_attr "length" "4,8")])
17caeff2
JM		 2384
2385(define_insn "*mov_sitf_e500_subreg12"
2386 [(set (subreg:SI (match_operand:TF 0 "register_operand" "+r,r") 12)
2387 (match_operand:SI 1 "input_operand" "r,m"))]
2388 "TARGET_E500_DOUBLE"
2389 "@
2390 mr %L0,%1
2391 {l%U1%X1|lwz%U1%X1} %L0,%1")
2392
2393(define_insn "*mov_sitf_e500_subreg12_2"
2394 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
2395 (subreg:SI (match_operand:TF 1 "register_operand" "r,r") 12))]
2396 "TARGET_E500_DOUBLE"
2397 "@
2398 mr %0,%L1
2399 {st%U0%X0|stw%U0%X0} %L1,%0")
2400
54b695e7 2401;; FIXME: Allow r=CONST0.
7a2f7870 2402(define_insn "*movdf_e500_double"
165a5bad 2403 [(set (match_operand:DF 0 "rs6000_nonimmediate_operand" "=r,r,m")
7a2f7870
AH		 2404 (match_operand:DF 1 "input_operand" "r,m,r"))]
2405 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE
2406 && (gpc_reg_operand (operands[0], DFmode)
2407 || gpc_reg_operand (operands[1], DFmode))"
2408 "*
2409 {
2410 switch (which_alternative)
2411 {
2412 case 0:
2413 return \"evor %0,%1,%1\";
2414 case 1:
2415 return \"evldd%X1 %0,%y1\";
2416 case 2:
2417 return \"evstdd%X0 %1,%y0\";
2418 default:
37409796 2419 gcc_unreachable ();
7a2f7870
AH		 2420 }
2421 }"
2422 [(set_attr "type" "*,vecload,vecstore")
2423 (set_attr "length" "*,*,*")])
2424
2425(define_insn "spe_truncdfsf2"
2426 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
2427 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "r")))]
2428 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2429 "efscfd %0,%1")
2430
2431(define_insn "spe_absdf2"
2432 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2433 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
2434 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2435 "efdabs %0,%1")
2436
2437(define_insn "spe_nabsdf2"
2438 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2439 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r"))))]
2440 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2441 "efdnabs %0,%1")
2442
2443(define_insn "spe_negdf2"
2444 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2445 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "r")))]
2446 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2447 "efdneg %0,%1")
2448
2449(define_insn "spe_adddf3"
2450 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2451 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2452 (match_operand:DF 2 "gpc_reg_operand" "r")))]
2453 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2454 "efdadd %0,%1,%2")
2455
2456(define_insn "spe_subdf3"
2457 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2458 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2459 (match_operand:DF 2 "gpc_reg_operand" "r")))]
2460 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2461 "efdsub %0,%1,%2")
2462
2463(define_insn "spe_muldf3"
2464 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2465 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2466 (match_operand:DF 2 "gpc_reg_operand" "r")))]
2467 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2468 "efdmul %0,%1,%2")
2469
2470(define_insn "spe_divdf3"
2471 [(set (match_operand:DF 0 "gpc_reg_operand" "=r")
2472 (div:DF (match_operand:DF 1 "gpc_reg_operand" "r")
2473 (match_operand:DF 2 "gpc_reg_operand" "r")))]
2474 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
2475 "efddiv %0,%1,%2")
2476
17caeff2
JM		 2477;; Double-precision floating point instructions for IBM long double.
2478
2479(define_insn_and_split "spe_trunctfdf2_internal1"
2480 [(set (match_operand:DF 0 "gpc_reg_operand" "=r,?r")
2481 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,r")))]
2482 "!TARGET_IEEEQUAD
2483 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2484 "@
2485 #
2486 evor %0,%1,%1"
2487 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
2488 [(const_int 0)]
2489{
2490 emit_note (NOTE_INSN_DELETED);
2491 DONE;
2492})
2493
2494(define_insn_and_split "spe_trunctfsf2"
2495 [(set (match_operand:SF 0 "gpc_reg_operand" "=r")
2496 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "r")))
2497 (clobber (match_scratch:DF 2 "=r"))]
2498 "!TARGET_IEEEQUAD
2499 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2500 "#"
2501 "&& reload_completed"
2502 [(set (match_dup 2)
2503 (float_truncate:DF (match_dup 1)))
2504 (set (match_dup 0)
2505 (float_truncate:SF (match_dup 2)))]
2506 "")
2507
2508(define_insn "spe_extenddftf2"
2509 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,?r,r,o")
2510 (float_extend:TF (match_operand:DF 1 "input_operand" "0,r,m,r")))
2511 (clobber (match_scratch:DF 2 "=X,X,X,&r"))]
2512 "!TARGET_IEEEQUAD
2513 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2514 "@
2515 evxor %L0,%L0,%L0
2516 evor %0,%1,%1\;evxor %L0,%L0,%L0
2517 evldd%X1 %0,%y1\;evxor %L0,%L0,%L0
b6fda43f
JM		 2518 evstdd%X0 %1,%y0\;evxor %2,%2,%2\;evstdd %2,%Y0"
2519 [(set_attr "length" "4,8,8,12")])
17caeff2
JM		 2520
2521(define_expand "spe_fix_trunctfsi2"
2522 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2523 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
2524 (clobber (match_dup 2))
2525 (clobber (match_dup 3))
2526 (clobber (match_dup 4))])]
2527 "!TARGET_IEEEQUAD
2528 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2529{
2530 operands[2] = gen_reg_rtx (DFmode);
2531 operands[3] = gen_reg_rtx (SImode);
2532 operands[4] = gen_reg_rtx (SImode);
2533})
2534
2535; Like fix_trunc_helper, add with rounding towards 0.
2536(define_insn "spe_fix_trunctfsi2_internal"
2537 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2538 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "r")))
2539 (clobber (match_operand:DF 2 "gpc_reg_operand" "=r"))
2540 (clobber (match_operand:SI 3 "gpc_reg_operand" "=&r"))
2541 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))]
2542 "!TARGET_IEEEQUAD
2543 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
b6fda43f
JM		 2544 "mfspefscr %3\;rlwinm %4,%3,0,0,29\;ori %4,%4,1\;efdadd %2,%1,%L1\;mtspefscr %3\;efdctsiz %0, %2"
2545 [(set_attr "length" "24")])
17caeff2
JM		 2546
2547(define_insn "spe_negtf2_internal"
2548 [(set (match_operand:TF 0 "gpc_reg_operand" "=r")
2549 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "r")))]
2550 "!TARGET_IEEEQUAD
2551 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2552 "*
2553{
2554 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
2555 return \"efdneg %L0,%L1\;efdneg %0,%1\";
2556 else
2557 return \"efdneg %0,%1\;efdneg %L0,%L1\";
b6fda43f
JM		 2558}"
2559 [(set_attr "length" "8")])
17caeff2
JM		 2560
2561(define_expand "spe_abstf2_cmp"
2562 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
2563 (match_operand:TF 1 "gpc_reg_operand" "f"))
2564 (set (match_dup 3) (match_dup 5))
2565 (set (match_dup 5) (abs:DF (match_dup 5)))
2566 (set (match_dup 4) (unspec:CCFP [(compare:CCFP (match_dup 3)
2567 (match_dup 5))] CMPDFEQ_GPR))
2568 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
2569 (label_ref (match_operand 2 "" ""))
2570 (pc)))
2571 (set (match_dup 6) (neg:DF (match_dup 6)))]
2572 "!TARGET_IEEEQUAD
2573 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2574 "
2575{
2576 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
2577 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
2578 operands[3] = gen_reg_rtx (DFmode);
2579 operands[4] = gen_reg_rtx (CCFPmode);
2580 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
2581 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
2582}")
2583
2584(define_expand "spe_abstf2_tst"
2585 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
2586 (match_operand:TF 1 "gpc_reg_operand" "f"))
2587 (set (match_dup 3) (match_dup 5))
2588 (set (match_dup 5) (abs:DF (match_dup 5)))
2589 (set (match_dup 4) (unspec:CCFP [(compare:CCFP (match_dup 3)
2590 (match_dup 5))] TSTDFEQ_GPR))
2591 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
2592 (label_ref (match_operand 2 "" ""))
2593 (pc)))
2594 (set (match_dup 6) (neg:DF (match_dup 6)))]
2595 "!TARGET_IEEEQUAD
2596 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128"
2597 "
2598{
2599 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
2600 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
2601 operands[3] = gen_reg_rtx (DFmode);
2602 operands[4] = gen_reg_rtx (CCFPmode);
2603 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
2604 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
2605}")
2606
a3170dc6
AH		 2607;; Vector move instructions.
2608
2609(define_expand "movv2si"
2610 [(set (match_operand:V2SI 0 "nonimmediate_operand" "")
2611 (match_operand:V2SI 1 "any_operand" ""))]
2612 "TARGET_SPE"
2613 "{ rs6000_emit_move (operands[0], operands[1], V2SImode); DONE; }")
2614
a3170dc6 2615(define_insn "*movv2si_internal"
d744e06e
AH		 2616 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=m,r,r,r")
2617 (match_operand:V2SI 1 "input_operand" "r,m,r,W"))]
e66b2fcf
AH		 2618 "TARGET_SPE
2619 && (gpc_reg_operand (operands[0], V2SImode)
2620 || gpc_reg_operand (operands[1], V2SImode))"
d744e06e
AH		 2621 "*
2622{
2623 switch (which_alternative)
2624 {
2625 case 0: return \"evstdd%X0 %1,%y0\";
2626 case 1: return \"evldd%X1 %0,%y1\";
2627 case 2: return \"evor %0,%1,%1\";
2628 case 3: return output_vec_const_move (operands);
37409796 2629 default: gcc_unreachable ();
d744e06e
AH		 2630 }
2631}"
2632 [(set_attr "type" "vecload,vecstore,*,*")
2633 (set_attr "length" "*,*,*,12")])
2634
2635(define_split
2636 [(set (match_operand:V2SI 0 "register_operand" "")
2637 (match_operand:V2SI 1 "zero_constant" ""))]
2638 "TARGET_SPE && reload_completed"
2639 [(set (match_dup 0)
2640 (xor:V2SI (match_dup 0) (match_dup 0)))]
2641 "")
a3170dc6 2642
00a892b8
NC		 2643(define_expand "movv1di"
2644 [(set (match_operand:V1DI 0 "nonimmediate_operand" "")
2645 (match_operand:V1DI 1 "any_operand" ""))]
2646 "TARGET_SPE"
2647 "{ rs6000_emit_move (operands[0], operands[1], V1DImode); DONE; }")
2648
2649(define_insn "*movv1di_internal"
d744e06e
AH		 2650 [(set (match_operand:V1DI 0 "nonimmediate_operand" "=m,r,r,r")
2651 (match_operand:V1DI 1 "input_operand" "r,m,r,W"))]
e66b2fcf
AH		 2652 "TARGET_SPE
2653 && (gpc_reg_operand (operands[0], V1DImode)
2654 || gpc_reg_operand (operands[1], V1DImode))"
00a892b8
NC		 2655 "@
2656 evstdd%X0 %1,%y0
2657 evldd%X1 %0,%y1
d744e06e
AH		 2658 evor %0,%1,%1
2659 evxor %0,%0,%0"
2660 [(set_attr "type" "vecload,vecstore,*,*")
2661 (set_attr "length" "*,*,*,*")])
00a892b8 2662
a3170dc6
AH		 2663(define_expand "movv4hi"
2664 [(set (match_operand:V4HI 0 "nonimmediate_operand" "")
2665 (match_operand:V4HI 1 "any_operand" ""))]
2666 "TARGET_SPE"
2667 "{ rs6000_emit_move (operands[0], operands[1], V4HImode); DONE; }")
2668
2669(define_insn "*movv4hi_internal"
b9bb3235
JM		 2670 [(set (match_operand:V4HI 0 "nonimmediate_operand" "=m,r,r,r")
2671 (match_operand:V4HI 1 "input_operand" "r,m,r,W"))]
e66b2fcf
AH		 2672 "TARGET_SPE
2673 && (gpc_reg_operand (operands[0], V4HImode)
2674 || gpc_reg_operand (operands[1], V4HImode))"
a3170dc6
AH		 2675 "@
2676 evstdd%X0 %1,%y0
2677 evldd%X1 %0,%y1
b9bb3235
JM		 2678 evor %0,%1,%1
2679 evxor %0,%0,%0"
d744e06e 2680 [(set_attr "type" "vecload")])
a3170dc6
AH		 2681
2682(define_expand "movv2sf"
2683 [(set (match_operand:V2SF 0 "nonimmediate_operand" "")
2684 (match_operand:V2SF 1 "any_operand" ""))]
2685 "TARGET_SPE"
2686 "{ rs6000_emit_move (operands[0], operands[1], V2SFmode); DONE; }")
2687
2688(define_insn "*movv2sf_internal"
d744e06e
AH		 2689 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,r,r,r")
2690 (match_operand:V2SF 1 "input_operand" "r,m,r,W"))]
e66b2fcf
AH		 2691 "TARGET_SPE
2692 && (gpc_reg_operand (operands[0], V2SFmode)
2693 || gpc_reg_operand (operands[1], V2SFmode))"
a3170dc6
AH		 2694 "@
2695 evstdd%X0 %1,%y0
2696 evldd%X1 %0,%y1
d744e06e
AH		 2697 evor %0,%1,%1
2698 evxor %0,%0,%0"
2699 [(set_attr "type" "vecload,vecstore,*,*")
2700 (set_attr "length" "*,*,*,*")])
a3170dc6 2701
e66b2fcf
AH		 2702;; End of vector move instructions.
2703
a3170dc6
AH		 2704(define_insn "spe_evmwhssfaa"
2705 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2706 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2707 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 702))
2708 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2709 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2710 "TARGET_SPE"
2711 "evmwhssfaa %0,%1,%2"
2712 [(set_attr "type" "veccomplex")
2713 (set_attr "length" "4")])
2714
2715(define_insn "spe_evmwhssmaa"
2716 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2717 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2718 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 703))
2719 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2720 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2721 "TARGET_SPE"
2722 "evmwhssmaa %0,%1,%2"
2723 [(set_attr "type" "veccomplex")
2724 (set_attr "length" "4")])
2725
2726(define_insn "spe_evmwhsmfaa"
2727 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2728 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2729 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 704))
54da776f 2730 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2731 "TARGET_SPE"
2732 "evmwhsmfaa %0,%1,%2"
2733 [(set_attr "type" "veccomplex")
2734 (set_attr "length" "4")])
2735
2736(define_insn "spe_evmwhsmiaa"
2737 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2738 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2739 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 705))
54da776f 2740 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2741 "TARGET_SPE"
2742 "evmwhsmiaa %0,%1,%2"
2743 [(set_attr "type" "veccomplex")
2744 (set_attr "length" "4")])
2745
2746(define_insn "spe_evmwhusiaa"
2747 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2748 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2749 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 706))
2750 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2751 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2752 "TARGET_SPE"
2753 "evmwhusiaa %0,%1,%2"
2754 [(set_attr "type" "veccomplex")
2755 (set_attr "length" "4")])
2756
2757(define_insn "spe_evmwhumiaa"
2758 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2759 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2760 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 707))
54da776f 2761 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2762 "TARGET_SPE"
2763 "evmwhumiaa %0,%1,%2"
2764 [(set_attr "type" "veccomplex")
2765 (set_attr "length" "4")])
2766
2767(define_insn "spe_evmwhssfan"
2768 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2769 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2770 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 708))
2771 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2772 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2773 "TARGET_SPE"
2774 "evmwhssfan %0,%1,%2"
2775 [(set_attr "type" "veccomplex")
2776 (set_attr "length" "4")])
2777
2778(define_insn "spe_evmwhssian"
2779 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2780 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2781 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 709))
2782 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2783 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2784 "TARGET_SPE"
2785 "evmwhssian %0,%1,%2"
2786 [(set_attr "type" "veccomplex")
2787 (set_attr "length" "4")])
2788
2789(define_insn "spe_evmwhsmfan"
2790 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2791 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2792 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 710))
54da776f 2793 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2794 "TARGET_SPE"
2795 "evmwhsmfan %0,%1,%2"
2796 [(set_attr "type" "veccomplex")
2797 (set_attr "length" "4")])
2798
2799(define_insn "spe_evmwhsmian"
2800 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2801 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2802 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 711))
54da776f 2803 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2804 "TARGET_SPE"
2805 "evmwhsmian %0,%1,%2"
2806 [(set_attr "type" "veccomplex")
2807 (set_attr "length" "4")])
2808
2809(define_insn "spe_evmwhumian"
2810 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2811 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2812 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 713))
54da776f 2813 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2814 "TARGET_SPE"
2815 "evmwhumian %0,%1,%2"
2816 [(set_attr "type" "veccomplex")
2817 (set_attr "length" "4")])
2818
2819(define_insn "spe_evmwhgssfaa"
2820 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2821 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2822 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 714))
2823 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2824 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2825 "TARGET_SPE"
2826 "evmwhgssfaa %0,%1,%2"
2827 [(set_attr "type" "veccomplex")
2828 (set_attr "length" "4")])
2829
2830(define_insn "spe_evmwhgsmfaa"
2831 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2832 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2833 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 715))
54da776f 2834 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2835 "TARGET_SPE"
2836 "evmwhgsmfaa %0,%1,%2"
2837 [(set_attr "type" "veccomplex")
2838 (set_attr "length" "4")])
2839
2840(define_insn "spe_evmwhgsmiaa"
2841 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2842 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2843 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 716))
54da776f 2844 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2845 "TARGET_SPE"
2846 "evmwhgsmiaa %0,%1,%2"
2847 [(set_attr "type" "veccomplex")
2848 (set_attr "length" "4")])
2849
2850(define_insn "spe_evmwhgumiaa"
2851 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2852 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2853 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 717))
54da776f 2854 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2855 "TARGET_SPE"
2856 "evmwhgumiaa %0,%1,%2"
2857 [(set_attr "type" "veccomplex")
2858 (set_attr "length" "4")])
2859
2860(define_insn "spe_evmwhgssfan"
2861 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2862 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2863 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 718))
2864 (clobber (reg:SI SPEFSCR_REGNO))
54da776f 2865 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2866 "TARGET_SPE"
2867 "evmwhgssfan %0,%1,%2"
2868 [(set_attr "type" "veccomplex")
2869 (set_attr "length" "4")])
2870
2871(define_insn "spe_evmwhgsmfan"
2872 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2873 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2874 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 719))
54da776f 2875 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2876 "TARGET_SPE"
2877 "evmwhgsmfan %0,%1,%2"
2878 [(set_attr "type" "veccomplex")
2879 (set_attr "length" "4")])
2880
2881(define_insn "spe_evmwhgsmian"
2882 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2883 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2884 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 720))
54da776f 2885 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2886 "TARGET_SPE"
2887 "evmwhgsmian %0,%1,%2"
2888 [(set_attr "type" "veccomplex")
2889 (set_attr "length" "4")])
2890
2891(define_insn "spe_evmwhgumian"
2892 [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
2893 (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")
2894 (match_operand:V2SI 2 "gpc_reg_operand" "r")] 721))
54da776f 2895 (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))]
a3170dc6
AH		 2896 "TARGET_SPE"
2897 "evmwhgumian %0,%1,%2"
2898 [(set_attr "type" "veccomplex")
2899 (set_attr "length" "4")])
2900
2901(define_insn "spe_mtspefscr"
2902 [(set (reg:SI SPEFSCR_REGNO)
2903 (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")]
2904 722))]
2905 "TARGET_SPE"
2906 "mtspefscr %0"
2907 [(set_attr "type" "vecsimple")])
2908
2909(define_insn "spe_mfspefscr"
2910 [(set (match_operand:SI 0 "register_operand" "=r")
2911 (unspec_volatile:SI [(reg:SI SPEFSCR_REGNO)] 723))]
2912 "TARGET_SPE"
2913 "mfspefscr %0"
2914 [(set_attr "type" "vecsimple")])
2915
423c1189
AH		 2916;; FP comparison stuff.
2917
423c1189 2918;; Flip the GT bit.
64022b5d 2919(define_insn "e500_flip_gt_bit"
423c1189
AH		 2920 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2921 (unspec:CCFP
2922 [(match_operand:CCFP 1 "cc_reg_operand" "y")] 999))]
2923 "!TARGET_FPRS && TARGET_HARD_FLOAT"
2924 "*
2925{
64022b5d 2926 return output_e500_flip_gt_bit (operands[0], operands[1]);
423c1189
AH		 2927}"
2928 [(set_attr "type" "cr_logical")])
2929
a3170dc6
AH		 2930;; MPC8540 single-precision FP instructions on GPRs.
2931;; We have 2 variants for each. One for IEEE compliant math and one
2932;; for non IEEE compliant math.
2933
2934(define_insn "cmpsfeq_gpr"
2935 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
423c1189
AH		 2936 (unspec:CCFP
2937 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2938 (match_operand:SF 2 "gpc_reg_operand" "r"))]
2939 1000))]
a3170dc6
AH		 2940 "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
2941 "efscmpeq %0,%1,%2"
5e8006fa 2942 [(set_attr "type" "veccmp")])
a3170dc6
AH		 2943
2944(define_insn "tstsfeq_gpr"
2945 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
423c1189
AH		 2946 (unspec:CCFP
2947 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2948 (match_operand:SF 2 "gpc_reg_operand" "r"))]
2949 1001))]
a3170dc6
AH		 2950 "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
2951 "efststeq %0,%1,%2"
5e8006fa 2952 [(set_attr "type" "veccmpsimple")])
a3170dc6
AH		 2953
2954(define_insn "cmpsfgt_gpr"
2955 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
423c1189
AH		 2956 (unspec:CCFP
2957 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2958 (match_operand:SF 2 "gpc_reg_operand" "r"))]
2959 1002))]
a3170dc6
AH		 2960 "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
2961 "efscmpgt %0,%1,%2"
5e8006fa 2962 [(set_attr "type" "veccmp")])
a3170dc6
AH		 2963
2964(define_insn "tstsfgt_gpr"
2965 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
423c1189
AH		 2966 (unspec:CCFP
2967 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2968 (match_operand:SF 2 "gpc_reg_operand" "r"))]
2969 1003))]
a3170dc6
AH		 2970 "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
2971 "efststgt %0,%1,%2"
5e8006fa 2972 [(set_attr "type" "veccmpsimple")])
a3170dc6
AH		 2973
2974(define_insn "cmpsflt_gpr"
2975 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
423c1189
AH		 2976 (unspec:CCFP
2977 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2978 (match_operand:SF 2 "gpc_reg_operand" "r"))]
2979 1004))]
a3170dc6
AH		 2980 "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations"
2981 "efscmplt %0,%1,%2"
5e8006fa 2982 [(set_attr "type" "veccmp")])
a3170dc6
AH		 2983
2984(define_insn "tstsflt_gpr"
2985 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
423c1189
AH		 2986 (unspec:CCFP
2987 [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r")
2988 (match_operand:SF 2 "gpc_reg_operand" "r"))]
f350ff00 2989 1005))]
a3170dc6
AH		 2990 "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations"
2991 "efststlt %0,%1,%2"
5e8006fa 2992 [(set_attr "type" "veccmpsimple")])
4d4cbc0e
AH		 2993
2994;; Same thing, but for double-precision.
2995
2996(define_insn "cmpdfeq_gpr"
2997 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
2998 (unspec:CCFP
2999 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3000 (match_operand:DF 2 "gpc_reg_operand" "r"))]
3001 CMPDFEQ_GPR))]
3002 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations"
3003 "efdcmpeq %0,%1,%2"
3004 [(set_attr "type" "veccmp")])
3005
3006(define_insn "tstdfeq_gpr"
3007 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3008 (unspec:CCFP
3009 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3010 (match_operand:DF 2 "gpc_reg_operand" "r"))]
3011 TSTDFEQ_GPR))]
3012 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations"
3013 "efdtsteq %0,%1,%2"
3014 [(set_attr "type" "veccmpsimple")])
3015
3016(define_insn "cmpdfgt_gpr"
3017 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3018 (unspec:CCFP
3019 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3020 (match_operand:DF 2 "gpc_reg_operand" "r"))]
3021 CMPDFGT_GPR))]
3022 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations"
3023 "efdcmpgt %0,%1,%2"
3024 [(set_attr "type" "veccmp")])
3025
3026(define_insn "tstdfgt_gpr"
3027 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3028 (unspec:CCFP
3029 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3030 (match_operand:DF 2 "gpc_reg_operand" "r"))]
3031 TSTDFGT_GPR))]
3032 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations"
3033 "efdtstgt %0,%1,%2"
3034 [(set_attr "type" "veccmpsimple")])
3035
3036(define_insn "cmpdflt_gpr"
3037 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3038 (unspec:CCFP
3039 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3040 (match_operand:DF 2 "gpc_reg_operand" "r"))]
3041 CMPDFLT_GPR))]
3042 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations"
3043 "efdcmplt %0,%1,%2"
3044 [(set_attr "type" "veccmp")])
3045
3046(define_insn "tstdflt_gpr"
3047 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3048 (unspec:CCFP
3049 [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r")
3050 (match_operand:DF 2 "gpc_reg_operand" "r"))]
3051 TSTDFLT_GPR))]
3052 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations"
3053 "efdtstlt %0,%1,%2"
3054 [(set_attr "type" "veccmpsimple")])
64022b5d 3055
17caeff2
JM		 3056;; Same thing, but for IBM long double.
3057
3058(define_insn "cmptfeq_gpr"
3059 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3060 (unspec:CCFP
3061 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3062 (match_operand:TF 2 "gpc_reg_operand" "r"))]
3063 CMPTFEQ_GPR))]
3064 "!TARGET_IEEEQUAD
3065 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3066 && !flag_unsafe_math_optimizations"
3067 "efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmpeq %0,%L1,%L2"
b6fda43f
JM		 3068 [(set_attr "type" "veccmp")
3069 (set_attr "length" "12")])
17caeff2
JM		 3070
3071(define_insn "tsttfeq_gpr"
3072 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3073 (unspec:CCFP
3074 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3075 (match_operand:TF 2 "gpc_reg_operand" "r"))]
3076 TSTTFEQ_GPR))]
3077 "!TARGET_IEEEQUAD
3078 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3079 && flag_unsafe_math_optimizations"
3080 "efdtsteq %0,%1,%2\;bng %0,$+8\;efdtsteq %0,%L1,%L2"
b6fda43f
JM		 3081 [(set_attr "type" "veccmpsimple")
3082 (set_attr "length" "12")])
17caeff2
JM		 3083
3084(define_insn "cmptfgt_gpr"
3085 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3086 (unspec:CCFP
3087 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3088 (match_operand:TF 2 "gpc_reg_operand" "r"))]
3089 CMPTFGT_GPR))]
3090 "!TARGET_IEEEQUAD
3091 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3092 && !flag_unsafe_math_optimizations"
3093 "efdcmpgt %0,%1,%2\;bgt %0,$+16\;efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmpgt %0,%L1,%L2"
b6fda43f
JM		 3094 [(set_attr "type" "veccmp")
3095 (set_attr "length" "20")])
17caeff2
JM		 3096
3097(define_insn "tsttfgt_gpr"
3098 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3099 (unspec:CCFP
3100 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3101 (match_operand:TF 2 "gpc_reg_operand" "r"))]
3102 TSTTFGT_GPR))]
3103 "!TARGET_IEEEQUAD
3104 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3105 && flag_unsafe_math_optimizations"
3106 "efdtstgt %0,%1,%2\;bgt %0,$+16\;efdtsteq %0,%1,%2\;bng %0,$+8\;efdtstgt %0,%L1,%L2"
b6fda43f
JM		 3107 [(set_attr "type" "veccmpsimple")
3108 (set_attr "length" "20")])
17caeff2
JM		 3109
3110(define_insn "cmptflt_gpr"
3111 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3112 (unspec:CCFP
3113 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3114 (match_operand:TF 2 "gpc_reg_operand" "r"))]
3115 CMPTFLT_GPR))]
3116 "!TARGET_IEEEQUAD
3117 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3118 && !flag_unsafe_math_optimizations"
3119 "efdcmplt %0,%1,%2\;bgt %0,$+16\;efdcmpeq %0,%1,%2\;bng %0,$+8\;efdcmplt %0,%L1,%L2"
b6fda43f
JM		 3120 [(set_attr "type" "veccmp")
3121 (set_attr "length" "20")])
17caeff2
JM		 3122
3123(define_insn "tsttflt_gpr"
3124 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3125 (unspec:CCFP
3126 [(compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "r")
3127 (match_operand:TF 2 "gpc_reg_operand" "r"))]
3128 TSTTFLT_GPR))]
3129 "!TARGET_IEEEQUAD
3130 && TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && TARGET_LONG_DOUBLE_128
3131 && flag_unsafe_math_optimizations"
3132 "efdtstlt %0,%1,%2\;bgt %0,$+16\;efdtsteq %0,%1,%2\;bng %0,$+8\;efdtstlt %0,%L1,%L2"
b6fda43f
JM		 3133 [(set_attr "type" "veccmpsimple")
3134 (set_attr "length" "20")])
17caeff2 3135
64022b5d
AH		 3136;; Like cceq_ior_compare, but compare the GT bits.
3137(define_insn "e500_cr_ior_compare"
3138 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3139 (unspec:CCFP [(match_operand 1 "cc_reg_operand" "y")
3140 (match_operand 2 "cc_reg_operand" "y")]
3141 E500_CR_IOR_COMPARE))]
3142 "TARGET_E500"
3143 "cror 4*%0+gt,4*%1+gt,4*%2+gt"
3144 [(set_attr "type" "cr_logical")])
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