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a3170dc6 | 1 | ;; e500 SPE description |
5b86a469 | 2 | ;; Copyright (C) 2002, 2003, 2004, 2005 Free Software Foundation, Inc. |
a3170dc6 AH |
3 | ;; Contributed by Aldy Hernandez (aldy@quesejoda.com) |
4 | ||
5de601cf | 5 | ;; This file is part of GCC. |
a3170dc6 | 6 | |
5de601cf NC |
7 | ;; GCC is free software; you can redistribute it and/or modify it |
8 | ;; under the terms of the GNU General Public License as published | |
9 | ;; by the Free Software Foundation; either version 2, or (at your | |
10 | ;; option) any later version. | |
a3170dc6 | 11 | |
5de601cf NC |
12 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT |
13 | ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | ;; License for more details. | |
a3170dc6 AH |
16 | |
17 | ;; You should have received a copy of the GNU General Public License | |
5de601cf | 18 | ;; along with GCC; see the file COPYING. If not, write to the |
39d14dda KC |
19 | ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, |
20 | ;; MA 02110-1301, USA. | |
a3170dc6 AH |
21 | |
22 | (define_constants | |
23 | [(SPE_ACC_REGNO 111) | |
4d4cbc0e AH |
24 | (SPEFSCR_REGNO 112) |
25 | ||
26 | (CMPDFEQ_GPR 1006) | |
27 | (TSTDFEQ_GPR 1007) | |
28 | (CMPDFGT_GPR 1008) | |
29 | (TSTDFGT_GPR 1009) | |
30 | (CMPDFLT_GPR 1010) | |
31 | (TSTDFLT_GPR 1011) | |
64022b5d | 32 | (E500_CR_IOR_COMPARE 1012) |
4d4cbc0e | 33 | ]) |
a3170dc6 AH |
34 | |
35 | (define_insn "*negsf2_gpr" | |
36 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
37 | (neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))] | |
38 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
39 | "efsneg %0,%1" | |
5e8006fa | 40 | [(set_attr "type" "fpsimple")]) |
a3170dc6 AH |
41 | |
42 | (define_insn "*abssf2_gpr" | |
43 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
44 | (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r")))] | |
45 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
46 | "efsabs %0,%1" | |
5e8006fa | 47 | [(set_attr "type" "fpsimple")]) |
a3170dc6 | 48 | |
fe9c3a97 AH |
49 | (define_insn "*nabssf2_gpr" |
50 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
51 | (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r"))))] | |
52 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
53 | "efsnabs %0,%1" | |
54 | [(set_attr "type" "fpsimple")]) | |
55 | ||
a3170dc6 AH |
56 | (define_insn "*addsf3_gpr" |
57 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
58 | (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%r") | |
59 | (match_operand:SF 2 "gpc_reg_operand" "r")))] | |
60 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
61 | "efsadd %0,%1,%2" | |
62 | [(set_attr "type" "fp")]) | |
63 | ||
64 | (define_insn "*subsf3_gpr" | |
65 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
66 | (minus:SF (match_operand:SF 1 "gpc_reg_operand" "r") | |
67 | (match_operand:SF 2 "gpc_reg_operand" "r")))] | |
68 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
69 | "efssub %0,%1,%2" | |
70 | [(set_attr "type" "fp")]) | |
71 | ||
72 | (define_insn "*mulsf3_gpr" | |
73 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
74 | (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%r") | |
75 | (match_operand:SF 2 "gpc_reg_operand" "r")))] | |
76 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
77 | "efsmul %0,%1,%2" | |
78 | [(set_attr "type" "fp")]) | |
79 | ||
80 | (define_insn "*divsf3_gpr" | |
81 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
82 | (div:SF (match_operand:SF 1 "gpc_reg_operand" "r") | |
83 | (match_operand:SF 2 "gpc_reg_operand" "r")))] | |
84 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
85 | "efsdiv %0,%1,%2" | |
5e8006fa | 86 | [(set_attr "type" "vecfdiv")]) |
a3170dc6 | 87 | |
7a2f7870 AH |
88 | ;; Floating point conversion instructions. |
89 | ||
90 | (define_insn "fixuns_truncdfsi2" | |
91 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
92 | (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))] | |
93 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
94 | "efdctuiz %0,%1" | |
95 | [(set_attr "type" "fp")]) | |
96 | ||
7a2f7870 AH |
97 | (define_insn "spe_extendsfdf2" |
98 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
99 | (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "r")))] | |
100 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
101 | "efdcfs %0,%1" | |
102 | [(set_attr "type" "fp")]) | |
103 | ||
d095928f | 104 | (define_insn "spe_fixuns_truncsfsi2" |
a3170dc6 | 105 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") |
d095928f | 106 | (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))] |
a3170dc6 AH |
107 | "TARGET_HARD_FLOAT && !TARGET_FPRS" |
108 | "efsctuiz %0,%1" | |
109 | [(set_attr "type" "fp")]) | |
110 | ||
d095928f AH |
111 | (define_insn "spe_fix_truncsfsi2" |
112 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
113 | (fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))] | |
114 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
115 | "efsctsiz %0,%1" | |
116 | [(set_attr "type" "fp")]) | |
a3170dc6 | 117 | |
7a2f7870 AH |
118 | (define_insn "spe_fix_truncdfsi2" |
119 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
120 | (fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))] | |
121 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
122 | "efdctsiz %0,%1" | |
123 | [(set_attr "type" "fp")]) | |
124 | ||
a3170dc6 AH |
125 | (define_insn "spe_floatunssisf2" |
126 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
127 | (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
128 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
129 | "efscfui %0,%1" | |
130 | [(set_attr "type" "fp")]) | |
131 | ||
7a2f7870 AH |
132 | (define_insn "spe_floatunssidf2" |
133 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
134 | (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
135 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
136 | "efdcfui %0,%1" | |
137 | [(set_attr "type" "fp")]) | |
138 | ||
a3170dc6 AH |
139 | (define_insn "spe_floatsisf2" |
140 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
141 | (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
142 | "TARGET_HARD_FLOAT && !TARGET_FPRS" | |
143 | "efscfsi %0,%1" | |
144 | [(set_attr "type" "fp")]) | |
145 | ||
7a2f7870 AH |
146 | (define_insn "spe_floatsidf2" |
147 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
148 | (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))] | |
149 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
150 | "efdcfsi %0,%1" | |
151 | [(set_attr "type" "fp")]) | |
a3170dc6 AH |
152 | |
153 | ;; SPE SIMD instructions | |
154 | ||
155 | (define_insn "spe_evabs" | |
156 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
157 | (abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))] | |
158 | "TARGET_SPE" | |
159 | "evabs %0,%1" | |
160 | [(set_attr "type" "vecsimple") | |
161 | (set_attr "length" "4")]) | |
162 | ||
163 | (define_insn "spe_evandc" | |
164 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
165 | (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
166 | (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] | |
167 | "TARGET_SPE" | |
168 | "evandc %0,%1,%2" | |
169 | [(set_attr "type" "vecsimple") | |
170 | (set_attr "length" "4")]) | |
171 | ||
172 | (define_insn "spe_evand" | |
173 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
174 | (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
175 | (match_operand:V2SI 2 "gpc_reg_operand" "r")))] | |
176 | "TARGET_SPE" | |
177 | "evand %0,%1,%2" | |
178 | [(set_attr "type" "vecsimple") | |
179 | (set_attr "length" "4")]) | |
180 | ||
181 | ;; Vector compare instructions | |
182 | ||
183 | (define_insn "spe_evcmpeq" | |
184 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
185 | (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
186 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 500))] | |
187 | "TARGET_SPE" | |
188 | "evcmpeq %0,%1,%2" | |
189 | [(set_attr "type" "veccmp") | |
190 | (set_attr "length" "4")]) | |
191 | ||
192 | (define_insn "spe_evcmpgts" | |
193 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
194 | (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
195 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 501))] | |
196 | "TARGET_SPE" | |
197 | "evcmpgts %0,%1,%2" | |
198 | [(set_attr "type" "veccmp") | |
199 | (set_attr "length" "4")]) | |
200 | ||
201 | (define_insn "spe_evcmpgtu" | |
202 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
203 | (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
204 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 502))] | |
205 | "TARGET_SPE" | |
206 | "evcmpgtu %0,%1,%2" | |
207 | [(set_attr "type" "veccmp") | |
208 | (set_attr "length" "4")]) | |
209 | ||
210 | (define_insn "spe_evcmplts" | |
211 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
212 | (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
213 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 503))] | |
214 | "TARGET_SPE" | |
215 | "evcmplts %0,%1,%2" | |
216 | [(set_attr "type" "veccmp") | |
217 | (set_attr "length" "4")]) | |
218 | ||
219 | (define_insn "spe_evcmpltu" | |
220 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
221 | (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
222 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 504))] | |
223 | "TARGET_SPE" | |
224 | "evcmpltu %0,%1,%2" | |
225 | [(set_attr "type" "veccmp") | |
226 | (set_attr "length" "4")]) | |
227 | ||
228 | ;; Floating point vector compare instructions | |
229 | ||
230 | (define_insn "spe_evfscmpeq" | |
231 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
232 | (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
233 | (match_operand:V2SF 2 "gpc_reg_operand" "r")] 538)) | |
234 | (clobber (reg:SI SPEFSCR_REGNO))] | |
235 | "TARGET_SPE" | |
236 | "evfscmpeq %0,%1,%2" | |
237 | [(set_attr "type" "veccmp") | |
238 | (set_attr "length" "4")]) | |
239 | ||
240 | (define_insn "spe_evfscmpgt" | |
241 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
242 | (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
243 | (match_operand:V2SF 2 "gpc_reg_operand" "r")] 539)) | |
244 | (clobber (reg:SI SPEFSCR_REGNO))] | |
245 | "TARGET_SPE" | |
246 | "evfscmpgt %0,%1,%2" | |
247 | [(set_attr "type" "veccmp") | |
248 | (set_attr "length" "4")]) | |
249 | ||
250 | (define_insn "spe_evfscmplt" | |
251 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
252 | (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
253 | (match_operand:V2SF 2 "gpc_reg_operand" "r")] 540)) | |
254 | (clobber (reg:SI SPEFSCR_REGNO))] | |
255 | "TARGET_SPE" | |
256 | "evfscmplt %0,%1,%2" | |
257 | [(set_attr "type" "veccmp") | |
258 | (set_attr "length" "4")]) | |
259 | ||
260 | (define_insn "spe_evfststeq" | |
261 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
262 | (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
263 | (match_operand:V2SF 2 "gpc_reg_operand" "r")] 541))] | |
264 | "TARGET_SPE" | |
265 | "evfststeq %0,%1,%2" | |
266 | [(set_attr "type" "veccmp") | |
267 | (set_attr "length" "4")]) | |
268 | ||
269 | (define_insn "spe_evfststgt" | |
270 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
271 | (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
272 | (match_operand:V2SF 2 "gpc_reg_operand" "r")] 542))] | |
273 | "TARGET_SPE" | |
274 | "evfststgt %0,%1,%2" | |
275 | [(set_attr "type" "veccmp") | |
276 | (set_attr "length" "4")]) | |
277 | ||
278 | (define_insn "spe_evfststlt" | |
279 | [(set (match_operand:CC 0 "cc_reg_operand" "=y") | |
280 | (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
281 | (match_operand:V2SF 2 "gpc_reg_operand" "r")] 543))] | |
282 | "TARGET_SPE" | |
283 | "evfststlt %0,%1,%2" | |
284 | [(set_attr "type" "veccmp") | |
285 | (set_attr "length" "4")]) | |
286 | ||
287 | ;; End of vector compare instructions | |
288 | ||
289 | (define_insn "spe_evcntlsw" | |
290 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
291 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 505))] | |
292 | "TARGET_SPE" | |
293 | "evcntlsw %0,%1" | |
294 | [(set_attr "type" "vecsimple") | |
295 | (set_attr "length" "4")]) | |
296 | ||
297 | (define_insn "spe_evcntlzw" | |
298 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
299 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 506))] | |
300 | "TARGET_SPE" | |
301 | "evcntlzw %0,%1" | |
302 | [(set_attr "type" "vecsimple") | |
303 | (set_attr "length" "4")]) | |
304 | ||
305 | (define_insn "spe_eveqv" | |
306 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
307 | (not:V2SI (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
308 | (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] | |
309 | "TARGET_SPE" | |
310 | "eveqv %0,%1,%2" | |
311 | [(set_attr "type" "vecsimple") | |
312 | (set_attr "length" "4")]) | |
313 | ||
314 | (define_insn "spe_evextsb" | |
315 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
316 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 507))] | |
317 | "TARGET_SPE" | |
318 | "evextsb %0,%1" | |
319 | [(set_attr "type" "vecsimple") | |
320 | (set_attr "length" "4")]) | |
321 | ||
322 | (define_insn "spe_evextsh" | |
323 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
324 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 508))] | |
325 | "TARGET_SPE" | |
326 | "evextsh %0,%1" | |
327 | [(set_attr "type" "vecsimple") | |
328 | (set_attr "length" "4")]) | |
329 | ||
330 | (define_insn "spe_evlhhesplat" | |
626098f9 AH |
331 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") |
332 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
a3170dc6 AH |
333 | (match_operand:QI 2 "immediate_operand" "i")))) |
334 | (unspec [(const_int 0)] 509)] | |
626098f9 AH |
335 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" |
336 | "evlhhesplat %0,%2*2(%1)" | |
a3170dc6 AH |
337 | [(set_attr "type" "vecload") |
338 | (set_attr "length" "4")]) | |
339 | ||
340 | (define_insn "spe_evlhhesplatx" | |
341 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
342 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
343 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
344 | (unspec [(const_int 0)] 510)] | |
345 | "TARGET_SPE" | |
346 | "evlhhesplatx %0,%1,%2" | |
347 | [(set_attr "type" "vecload") | |
348 | (set_attr "length" "4")]) | |
349 | ||
350 | (define_insn "spe_evlhhossplat" | |
351 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
352 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
353 | (match_operand:QI 2 "immediate_operand" "i")))) | |
354 | (unspec [(const_int 0)] 511)] | |
626098f9 AH |
355 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" |
356 | "evlhhossplat %0,%2*2(%1)" | |
a3170dc6 AH |
357 | [(set_attr "type" "vecload") |
358 | (set_attr "length" "4")]) | |
359 | ||
360 | (define_insn "spe_evlhhossplatx" | |
361 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
362 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
363 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
364 | (unspec [(const_int 0)] 512)] | |
365 | "TARGET_SPE" | |
366 | "evlhhossplatx %0,%1,%2" | |
367 | [(set_attr "type" "vecload") | |
368 | (set_attr "length" "4")]) | |
369 | ||
370 | (define_insn "spe_evlhhousplat" | |
371 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
372 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
373 | (match_operand:QI 2 "immediate_operand" "i")))) | |
374 | (unspec [(const_int 0)] 513)] | |
626098f9 AH |
375 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" |
376 | "evlhhousplat %0,%2*2(%1)" | |
a3170dc6 AH |
377 | [(set_attr "type" "vecload") |
378 | (set_attr "length" "4")]) | |
379 | ||
380 | (define_insn "spe_evlhhousplatx" | |
381 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
382 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
383 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
384 | (unspec [(const_int 0)] 514)] | |
385 | "TARGET_SPE" | |
386 | "evlhhousplatx %0,%1,%2" | |
387 | [(set_attr "type" "vecload") | |
388 | (set_attr "length" "4")]) | |
389 | ||
390 | (define_insn "spe_evlwhsplat" | |
391 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
392 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
393 | (match_operand:QI 2 "immediate_operand" "i")))) | |
394 | (unspec [(const_int 0)] 515)] | |
626098f9 AH |
395 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" |
396 | "evlwhsplat %0,%2*4(%1)" | |
a3170dc6 AH |
397 | [(set_attr "type" "vecload") |
398 | (set_attr "length" "4")]) | |
399 | ||
400 | (define_insn "spe_evlwhsplatx" | |
401 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
402 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
403 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
404 | (unspec [(const_int 0)] 516)] | |
405 | "TARGET_SPE" | |
406 | "evlwhsplatx %0,%1,%2" | |
407 | [(set_attr "type" "vecload") | |
408 | (set_attr "length" "4")]) | |
409 | ||
410 | (define_insn "spe_evlwwsplat" | |
411 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
412 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
413 | (match_operand:QI 2 "immediate_operand" "i")))) | |
414 | (unspec [(const_int 0)] 517)] | |
626098f9 AH |
415 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" |
416 | "evlwwsplat %0,%2*4(%1)" | |
a3170dc6 AH |
417 | [(set_attr "type" "vecload") |
418 | (set_attr "length" "4")]) | |
419 | ||
420 | (define_insn "spe_evlwwsplatx" | |
421 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
422 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
423 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
424 | (unspec [(const_int 0)] 518)] | |
425 | "TARGET_SPE" | |
426 | "evlwwsplatx %0,%1,%2" | |
427 | [(set_attr "type" "vecload") | |
428 | (set_attr "length" "4")]) | |
429 | ||
430 | (define_insn "spe_evmergehi" | |
431 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
432 | (vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
433 | (vec_select:V2SI | |
434 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
435 | (parallel [(const_int 1) | |
436 | (const_int 0)])) | |
437 | (const_int 2)))] | |
438 | "TARGET_SPE" | |
439 | "evmergehi %0,%1,%2" | |
440 | [(set_attr "type" "vecsimple") | |
441 | (set_attr "length" "4")]) | |
442 | ||
443 | (define_insn "spe_evmergehilo" | |
444 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
445 | (vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
446 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
447 | (const_int 2)))] | |
448 | "TARGET_SPE" | |
449 | "evmergehilo %0,%1,%2" | |
450 | [(set_attr "type" "vecsimple") | |
451 | (set_attr "length" "4")]) | |
452 | ||
453 | (define_insn "spe_evmergelo" | |
454 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
455 | (vec_merge:V2SI (vec_select:V2SI | |
456 | (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
457 | (parallel [(const_int 1) | |
458 | (const_int 0)])) | |
459 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
460 | (const_int 2)))] | |
461 | "TARGET_SPE" | |
462 | "evmergelo %0,%1,%2" | |
463 | [(set_attr "type" "vecsimple") | |
464 | (set_attr "length" "4")]) | |
465 | ||
466 | (define_insn "spe_evmergelohi" | |
467 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
468 | (vec_merge:V2SI (vec_select:V2SI | |
469 | (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
470 | (parallel [(const_int 1) | |
471 | (const_int 0)])) | |
472 | (vec_select:V2SI | |
473 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
474 | (parallel [(const_int 1) | |
475 | (const_int 0)])) | |
476 | (const_int 2)))] | |
477 | "TARGET_SPE" | |
478 | "evmergelohi %0,%1,%2" | |
479 | [(set_attr "type" "vecsimple") | |
480 | (set_attr "length" "4")]) | |
481 | ||
482 | (define_insn "spe_evnand" | |
483 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
484 | (not:V2SI (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
485 | (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] | |
486 | "TARGET_SPE" | |
487 | "evnand %0,%1,%2" | |
488 | [(set_attr "type" "vecsimple") | |
489 | (set_attr "length" "4")]) | |
490 | ||
6a599451 | 491 | (define_insn "negv2si2" |
a3170dc6 AH |
492 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") |
493 | (neg:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))] | |
494 | "TARGET_SPE" | |
495 | "evneg %0,%1" | |
496 | [(set_attr "type" "vecsimple") | |
497 | (set_attr "length" "4")]) | |
498 | ||
499 | (define_insn "spe_evnor" | |
500 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
501 | (not:V2SI (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
502 | (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] | |
503 | "TARGET_SPE" | |
504 | "evnor %0,%1,%2" | |
505 | [(set_attr "type" "vecsimple") | |
506 | (set_attr "length" "4")]) | |
507 | ||
508 | (define_insn "spe_evorc" | |
509 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
510 | (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
511 | (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] | |
512 | "TARGET_SPE" | |
513 | "evorc %0,%1,%2" | |
514 | [(set_attr "type" "vecsimple") | |
515 | (set_attr "length" "4")]) | |
516 | ||
517 | (define_insn "spe_evor" | |
518 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
519 | (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
520 | (match_operand:V2SI 2 "gpc_reg_operand" "r")))] | |
521 | "TARGET_SPE" | |
522 | "evor %0,%1,%2" | |
523 | [(set_attr "type" "vecsimple") | |
524 | (set_attr "length" "4")]) | |
525 | ||
526 | (define_insn "spe_evrlwi" | |
527 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
528 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
529 | (match_operand:QI 2 "immediate_operand" "i")] 519))] | |
530 | "TARGET_SPE" | |
78872ad9 | 531 | "evrlwi %0,%1,%2" |
a3170dc6 AH |
532 | [(set_attr "type" "vecsimple") |
533 | (set_attr "length" "4")]) | |
534 | ||
535 | (define_insn "spe_evrlw" | |
536 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
537 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
538 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 520))] | |
539 | "TARGET_SPE" | |
540 | "evrlw %0,%1,%2" | |
541 | [(set_attr "type" "veccomplex") | |
542 | (set_attr "length" "4")]) | |
543 | ||
544 | (define_insn "spe_evrndw" | |
545 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
546 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 521))] | |
547 | "TARGET_SPE" | |
548 | "evrndw %0,%1" | |
549 | [(set_attr "type" "vecsimple") | |
550 | (set_attr "length" "4")]) | |
551 | ||
552 | (define_insn "spe_evsel" | |
553 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
554 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
555 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
556 | (match_operand:CC 3 "cc_reg_operand" "y")] 522))] | |
557 | "TARGET_SPE" | |
558 | "evsel %0,%1,%2,%3" | |
559 | [(set_attr "type" "veccmp") | |
560 | (set_attr "length" "4")]) | |
561 | ||
562 | (define_insn "spe_evsel_fs" | |
563 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
564 | (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r") | |
565 | (match_operand:V2SF 2 "gpc_reg_operand" "r") | |
566 | (match_operand:CC 3 "cc_reg_operand" "y")] 725))] | |
567 | "TARGET_SPE" | |
568 | "evsel %0,%1,%2,%3" | |
569 | [(set_attr "type" "veccmp") | |
570 | (set_attr "length" "4")]) | |
571 | ||
572 | (define_insn "spe_evslwi" | |
573 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
574 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
575 | (match_operand:QI 2 "immediate_operand" "i")] | |
576 | 523))] | |
577 | "TARGET_SPE" | |
578 | "evslwi %0,%1,%2" | |
579 | [(set_attr "type" "vecsimple") | |
580 | (set_attr "length" "4")]) | |
581 | ||
582 | (define_insn "spe_evslw" | |
583 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
584 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
585 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 524))] | |
586 | "TARGET_SPE" | |
587 | "evslw %0,%1,%2" | |
588 | [(set_attr "type" "vecsimple") | |
589 | (set_attr "length" "4")]) | |
590 | ||
591 | (define_insn "spe_evsrwis" | |
592 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
593 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
594 | (match_operand:QI 2 "immediate_operand" "i")] | |
595 | 525))] | |
596 | "TARGET_SPE" | |
597 | "evsrwis %0,%1,%2" | |
598 | [(set_attr "type" "vecsimple") | |
599 | (set_attr "length" "4")]) | |
600 | ||
601 | (define_insn "spe_evsrwiu" | |
602 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
603 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
604 | (match_operand:QI 2 "immediate_operand" "i")] | |
605 | 526))] | |
606 | "TARGET_SPE" | |
607 | "evsrwiu %0,%1,%2" | |
608 | [(set_attr "type" "vecsimple") | |
609 | (set_attr "length" "4")]) | |
610 | ||
611 | (define_insn "spe_evsrws" | |
612 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
613 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
614 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 527))] | |
615 | "TARGET_SPE" | |
616 | "evsrws %0,%1,%2" | |
617 | [(set_attr "type" "vecsimple") | |
618 | (set_attr "length" "4")]) | |
619 | ||
620 | (define_insn "spe_evsrwu" | |
621 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
622 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
623 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 528))] | |
624 | "TARGET_SPE" | |
625 | "evsrwu %0,%1,%2" | |
626 | [(set_attr "type" "vecsimple") | |
627 | (set_attr "length" "4")]) | |
628 | ||
626098f9 AH |
629 | ;; vector xors |
630 | ||
631 | (define_insn "xorv2si3" | |
a3170dc6 AH |
632 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") |
633 | (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
634 | (match_operand:V2SI 2 "gpc_reg_operand" "r")))] | |
635 | "TARGET_SPE" | |
636 | "evxor %0,%1,%2" | |
637 | [(set_attr "type" "vecsimple") | |
638 | (set_attr "length" "4")]) | |
639 | ||
626098f9 AH |
640 | (define_insn "xorv4hi3" |
641 | [(set (match_operand:V4HI 0 "gpc_reg_operand" "=r") | |
642 | (xor:V4HI (match_operand:V4HI 1 "gpc_reg_operand" "r") | |
643 | (match_operand:V4HI 2 "gpc_reg_operand" "r")))] | |
644 | "TARGET_SPE" | |
645 | "evxor %0,%1,%2" | |
646 | [(set_attr "type" "vecsimple") | |
647 | (set_attr "length" "4")]) | |
648 | ||
649 | (define_insn "xorv1di3" | |
650 | [(set (match_operand:V1DI 0 "gpc_reg_operand" "=r") | |
651 | (xor:V1DI (match_operand:V1DI 1 "gpc_reg_operand" "r") | |
652 | (match_operand:V1DI 2 "gpc_reg_operand" "r")))] | |
653 | "TARGET_SPE" | |
654 | "evxor %0,%1,%2" | |
655 | [(set_attr "type" "vecsimple") | |
656 | (set_attr "length" "4")]) | |
657 | ||
658 | ;; end of vector xors | |
659 | ||
a3170dc6 AH |
660 | (define_insn "spe_evfsabs" |
661 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
662 | (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))] | |
663 | "TARGET_SPE" | |
664 | "evfsabs %0,%1" | |
5e8006fa | 665 | [(set_attr "type" "vecsimple") |
a3170dc6 AH |
666 | (set_attr "length" "4")]) |
667 | ||
668 | (define_insn "spe_evfsadd" | |
669 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
670 | (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") | |
671 | (match_operand:V2SF 2 "gpc_reg_operand" "r"))) | |
672 | (clobber (reg:SI SPEFSCR_REGNO))] | |
673 | "TARGET_SPE" | |
674 | "evfsadd %0,%1,%2" | |
675 | [(set_attr "type" "vecfloat") | |
676 | (set_attr "length" "4")]) | |
677 | ||
678 | (define_insn "spe_evfscfsf" | |
679 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
680 | (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 529))] | |
681 | "TARGET_SPE" | |
682 | "evfscfsf %0,%1" | |
683 | [(set_attr "type" "vecfloat") | |
684 | (set_attr "length" "4")]) | |
685 | ||
686 | (define_insn "spe_evfscfsi" | |
e7a9b208 AH |
687 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") |
688 | (float:V2SF (match_operand:V2SI 1 "gpc_reg_operand" "r")))] | |
a3170dc6 AH |
689 | "TARGET_SPE" |
690 | "evfscfsi %0,%1" | |
691 | [(set_attr "type" "vecfloat") | |
692 | (set_attr "length" "4")]) | |
693 | ||
694 | (define_insn "spe_evfscfuf" | |
695 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
696 | (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 530))] | |
697 | "TARGET_SPE" | |
698 | "evfscfuf %0,%1" | |
699 | [(set_attr "type" "vecfloat") | |
700 | (set_attr "length" "4")]) | |
701 | ||
702 | (define_insn "spe_evfscfui" | |
703 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
704 | (unspec:V2SF [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 701))] | |
705 | "TARGET_SPE" | |
706 | "evfscfui %0,%1" | |
707 | [(set_attr "type" "vecfloat") | |
708 | (set_attr "length" "4")]) | |
709 | ||
710 | (define_insn "spe_evfsctsf" | |
711 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
712 | (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 531))] | |
713 | "TARGET_SPE" | |
714 | "evfsctsf %0,%1" | |
715 | [(set_attr "type" "vecfloat") | |
716 | (set_attr "length" "4")]) | |
717 | ||
718 | (define_insn "spe_evfsctsi" | |
719 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
720 | (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 532))] | |
721 | "TARGET_SPE" | |
722 | "evfsctsi %0,%1" | |
723 | [(set_attr "type" "vecfloat") | |
724 | (set_attr "length" "4")]) | |
725 | ||
726 | (define_insn "spe_evfsctsiz" | |
727 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
728 | (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 533))] | |
729 | "TARGET_SPE" | |
730 | "evfsctsiz %0,%1" | |
731 | [(set_attr "type" "vecfloat") | |
732 | (set_attr "length" "4")]) | |
733 | ||
734 | (define_insn "spe_evfsctuf" | |
735 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
736 | (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 534))] | |
737 | "TARGET_SPE" | |
738 | "evfsctuf %0,%1" | |
739 | [(set_attr "type" "vecfloat") | |
740 | (set_attr "length" "4")]) | |
741 | ||
742 | (define_insn "spe_evfsctui" | |
743 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
744 | (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 535))] | |
745 | "TARGET_SPE" | |
746 | "evfsctui %0,%1" | |
747 | [(set_attr "type" "vecfloat") | |
748 | (set_attr "length" "4")]) | |
749 | ||
750 | (define_insn "spe_evfsctuiz" | |
751 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
752 | (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 536))] | |
753 | "TARGET_SPE" | |
754 | "evfsctuiz %0,%1" | |
755 | [(set_attr "type" "vecfloat") | |
756 | (set_attr "length" "4")]) | |
757 | ||
758 | (define_insn "spe_evfsdiv" | |
759 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
760 | (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") | |
761 | (match_operand:V2SF 2 "gpc_reg_operand" "r"))) | |
762 | (clobber (reg:SI SPEFSCR_REGNO))] | |
763 | "TARGET_SPE" | |
764 | "evfsdiv %0,%1,%2" | |
5e8006fa | 765 | [(set_attr "type" "vecfdiv") |
a3170dc6 AH |
766 | (set_attr "length" "4")]) |
767 | ||
768 | (define_insn "spe_evfsmul" | |
769 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
770 | (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") | |
771 | (match_operand:V2SF 2 "gpc_reg_operand" "r"))) | |
772 | (clobber (reg:SI SPEFSCR_REGNO))] | |
773 | "TARGET_SPE" | |
774 | "evfsmul %0,%1,%2" | |
775 | [(set_attr "type" "vecfloat") | |
776 | (set_attr "length" "4")]) | |
777 | ||
778 | (define_insn "spe_evfsnabs" | |
779 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
780 | (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 537))] | |
781 | "TARGET_SPE" | |
782 | "evfsnabs %0,%1" | |
5e8006fa | 783 | [(set_attr "type" "vecsimple") |
a3170dc6 AH |
784 | (set_attr "length" "4")]) |
785 | ||
786 | (define_insn "spe_evfsneg" | |
787 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
788 | (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))] | |
789 | "TARGET_SPE" | |
790 | "evfsneg %0,%1" | |
5e8006fa | 791 | [(set_attr "type" "vecsimple") |
a3170dc6 AH |
792 | (set_attr "length" "4")]) |
793 | ||
794 | (define_insn "spe_evfssub" | |
795 | [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") | |
796 | (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") | |
797 | (match_operand:V2SF 2 "gpc_reg_operand" "r"))) | |
798 | (clobber (reg:SI SPEFSCR_REGNO))] | |
799 | "TARGET_SPE" | |
800 | "evfssub %0,%1,%2" | |
801 | [(set_attr "type" "vecfloat") | |
802 | (set_attr "length" "4")]) | |
803 | ||
804 | ;; SPE SIMD load instructions. | |
805 | ||
b6d08ca1 | 806 | ;; Only the hardware engineer who designed the SPE understands the |
a3170dc6 AH |
807 | ;; plethora of load and store instructions ;-). We have no way of |
808 | ;; differentiating between them with RTL so use an unspec of const_int 0 | |
809 | ;; to avoid identical RTL. | |
810 | ||
811 | (define_insn "spe_evldd" | |
812 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
813 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
814 | (match_operand:QI 2 "immediate_operand" "i")))) | |
815 | (unspec [(const_int 0)] 544)] | |
816 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
626098f9 | 817 | "evldd %0,%2*8(%1)" |
a3170dc6 AH |
818 | [(set_attr "type" "vecload") |
819 | (set_attr "length" "4")]) | |
820 | ||
821 | (define_insn "spe_evlddx" | |
822 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
823 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
824 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
825 | (unspec [(const_int 0)] 545)] | |
826 | "TARGET_SPE" | |
827 | "evlddx %0,%1,%2" | |
828 | [(set_attr "type" "vecload") | |
829 | (set_attr "length" "4")]) | |
830 | ||
831 | (define_insn "spe_evldh" | |
832 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
833 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
834 | (match_operand:QI 2 "immediate_operand" "i")))) | |
835 | (unspec [(const_int 0)] 546)] | |
836 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" | |
626098f9 | 837 | "evldh %0,%2*8(%1)" |
a3170dc6 AH |
838 | [(set_attr "type" "vecload") |
839 | (set_attr "length" "4")]) | |
840 | ||
841 | (define_insn "spe_evldhx" | |
842 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
843 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
844 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
845 | (unspec [(const_int 0)] 547)] | |
846 | "TARGET_SPE" | |
847 | "evldhx %0,%1,%2" | |
848 | [(set_attr "type" "vecload") | |
849 | (set_attr "length" "4")]) | |
850 | ||
851 | (define_insn "spe_evldw" | |
852 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
853 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
854 | (match_operand:QI 2 "immediate_operand" "i")))) | |
855 | (unspec [(const_int 0)] 548)] | |
626098f9 AH |
856 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" |
857 | "evldw %0,%2*8(%1)" | |
a3170dc6 AH |
858 | [(set_attr "type" "vecload") |
859 | (set_attr "length" "4")]) | |
860 | ||
861 | (define_insn "spe_evldwx" | |
862 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
863 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
864 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
865 | (unspec [(const_int 0)] 549)] | |
866 | "TARGET_SPE" | |
867 | "evldwx %0,%1,%2" | |
868 | [(set_attr "type" "vecload") | |
869 | (set_attr "length" "4")]) | |
870 | ||
871 | (define_insn "spe_evlwhe" | |
872 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
873 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
874 | (match_operand:QI 2 "immediate_operand" "i")))) | |
875 | (unspec [(const_int 0)] 550)] | |
626098f9 AH |
876 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" |
877 | "evlwhe %0,%2*4(%1)" | |
a3170dc6 AH |
878 | [(set_attr "type" "vecload") |
879 | (set_attr "length" "4")]) | |
880 | ||
881 | (define_insn "spe_evlwhex" | |
882 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
883 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
884 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
885 | (unspec [(const_int 0)] 551)] | |
886 | "TARGET_SPE" | |
887 | "evlwhex %0,%1,%2" | |
888 | [(set_attr "type" "vecload") | |
889 | (set_attr "length" "4")]) | |
890 | ||
891 | (define_insn "spe_evlwhos" | |
892 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
893 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
894 | (match_operand:QI 2 "immediate_operand" "i")))) | |
895 | (unspec [(const_int 0)] 552)] | |
626098f9 AH |
896 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" |
897 | "evlwhos %0,%2*4(%1)" | |
a3170dc6 AH |
898 | [(set_attr "type" "vecload") |
899 | (set_attr "length" "4")]) | |
900 | ||
901 | (define_insn "spe_evlwhosx" | |
902 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
903 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
904 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
905 | (unspec [(const_int 0)] 553)] | |
906 | "TARGET_SPE" | |
907 | "evlwhosx %0,%1,%2" | |
908 | [(set_attr "type" "vecload") | |
909 | (set_attr "length" "4")]) | |
910 | ||
911 | (define_insn "spe_evlwhou" | |
912 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
913 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
914 | (match_operand:QI 2 "immediate_operand" "i")))) | |
915 | (unspec [(const_int 0)] 554)] | |
626098f9 AH |
916 | "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" |
917 | "evlwhou %0,%2*4(%1)" | |
a3170dc6 AH |
918 | [(set_attr "type" "vecload") |
919 | (set_attr "length" "4")]) | |
920 | ||
921 | (define_insn "spe_evlwhoux" | |
922 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
923 | (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") | |
924 | (match_operand:SI 2 "gpc_reg_operand" "r")))) | |
925 | (unspec [(const_int 0)] 555)] | |
926 | "TARGET_SPE" | |
927 | "evlwhoux %0,%1,%2" | |
928 | [(set_attr "type" "vecload") | |
929 | (set_attr "length" "4")]) | |
930 | ||
931 | (define_insn "spe_brinc" | |
932 | [(set (match_operand:SI 0 "gpc_reg_operand" "=r") | |
933 | (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "r") | |
934 | (match_operand:SI 2 "gpc_reg_operand" "r")] 556))] | |
935 | "TARGET_SPE" | |
936 | "brinc %0,%1,%2" | |
5e8006fa | 937 | [(set_attr "type" "brinc") |
a3170dc6 AH |
938 | (set_attr "length" "4")]) |
939 | ||
940 | (define_insn "spe_evmhegsmfaa" | |
941 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
942 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
943 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
944 | (reg:V2SI SPE_ACC_REGNO)] 557)) | |
54da776f | 945 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
946 | "TARGET_SPE" |
947 | "evmhegsmfaa %0,%1,%2" | |
948 | [(set_attr "type" "veccomplex") | |
949 | (set_attr "length" "4")]) | |
950 | ||
951 | (define_insn "spe_evmhegsmfan" | |
952 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
953 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
954 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
955 | (reg:V2SI SPE_ACC_REGNO)] 558)) | |
54da776f | 956 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
957 | "TARGET_SPE" |
958 | "evmhegsmfan %0,%1,%2" | |
959 | [(set_attr "type" "veccomplex") | |
960 | (set_attr "length" "4")]) | |
961 | ||
962 | (define_insn "spe_evmhegsmiaa" | |
963 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
964 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
965 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
966 | (reg:V2SI SPE_ACC_REGNO)] 559)) | |
54da776f | 967 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
968 | "TARGET_SPE" |
969 | "evmhegsmiaa %0,%1,%2" | |
970 | [(set_attr "type" "veccomplex") | |
971 | (set_attr "length" "4")]) | |
972 | ||
973 | (define_insn "spe_evmhegsmian" | |
974 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
975 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
976 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
977 | (reg:V2SI SPE_ACC_REGNO)] 560)) | |
54da776f | 978 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
979 | "TARGET_SPE" |
980 | "evmhegsmian %0,%1,%2" | |
981 | [(set_attr "type" "veccomplex") | |
982 | (set_attr "length" "4")]) | |
983 | ||
984 | (define_insn "spe_evmhegumiaa" | |
985 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
986 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
987 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
988 | (reg:V2SI SPE_ACC_REGNO)] 561)) | |
54da776f | 989 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
990 | "TARGET_SPE" |
991 | "evmhegumiaa %0,%1,%2" | |
992 | [(set_attr "type" "veccomplex") | |
993 | (set_attr "length" "4")]) | |
994 | ||
995 | (define_insn "spe_evmhegumian" | |
996 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
997 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
998 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
999 | (reg:V2SI SPE_ACC_REGNO)] 562)) | |
54da776f | 1000 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1001 | "TARGET_SPE" |
1002 | "evmhegumian %0,%1,%2" | |
1003 | [(set_attr "type" "veccomplex") | |
1004 | (set_attr "length" "4")]) | |
1005 | ||
1006 | (define_insn "spe_evmhesmfaaw" | |
1007 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1008 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1009 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1010 | (reg:V2SI SPE_ACC_REGNO)] 563)) | |
54da776f | 1011 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1012 | "TARGET_SPE" |
1013 | "evmhesmfaaw %0,%1,%2" | |
1014 | [(set_attr "type" "veccomplex") | |
1015 | (set_attr "length" "4")]) | |
1016 | ||
1017 | (define_insn "spe_evmhesmfanw" | |
1018 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1019 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1020 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1021 | (reg:V2SI SPE_ACC_REGNO)] 564)) | |
54da776f | 1022 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1023 | "TARGET_SPE" |
1024 | "evmhesmfanw %0,%1,%2" | |
1025 | [(set_attr "type" "veccomplex") | |
1026 | (set_attr "length" "4")]) | |
1027 | ||
1028 | (define_insn "spe_evmhesmfa" | |
1029 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1030 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1031 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 565)) | |
54da776f | 1032 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1033 | "TARGET_SPE" |
1034 | "evmhesmfa %0,%1,%2" | |
1035 | [(set_attr "type" "veccomplex") | |
1036 | (set_attr "length" "4")]) | |
1037 | ||
1038 | (define_insn "spe_evmhesmf" | |
1039 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1040 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1041 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 566))] | |
1042 | "TARGET_SPE" | |
1043 | "evmhesmf %0,%1,%2" | |
1044 | [(set_attr "type" "veccomplex") | |
1045 | (set_attr "length" "4")]) | |
1046 | ||
1047 | (define_insn "spe_evmhesmiaaw" | |
1048 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1049 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1050 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1051 | (reg:V2SI SPE_ACC_REGNO)] 567)) | |
54da776f | 1052 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1053 | "TARGET_SPE" |
1054 | "evmhesmiaaw %0,%1,%2" | |
1055 | [(set_attr "type" "veccomplex") | |
1056 | (set_attr "length" "4")]) | |
1057 | ||
1058 | (define_insn "spe_evmhesmianw" | |
1059 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1060 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1061 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1062 | (reg:V2SI SPE_ACC_REGNO)] 568)) | |
54da776f | 1063 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1064 | "TARGET_SPE" |
1065 | "evmhesmianw %0,%1,%2" | |
1066 | [(set_attr "type" "veccomplex") | |
1067 | (set_attr "length" "4")]) | |
1068 | ||
1069 | (define_insn "spe_evmhesmia" | |
1070 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1071 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1072 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 569)) | |
54da776f | 1073 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1074 | "TARGET_SPE" |
1075 | "evmhesmia %0,%1,%2" | |
1076 | [(set_attr "type" "veccomplex") | |
1077 | (set_attr "length" "4")]) | |
1078 | ||
1079 | (define_insn "spe_evmhesmi" | |
1080 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1081 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1082 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 570))] | |
1083 | "TARGET_SPE" | |
1084 | "evmhesmi %0,%1,%2" | |
1085 | [(set_attr "type" "veccomplex") | |
1086 | (set_attr "length" "4")]) | |
1087 | ||
1088 | (define_insn "spe_evmhessfaaw" | |
1089 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1090 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1091 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1092 | (reg:V2SI SPE_ACC_REGNO)] 571)) | |
1093 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1094 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1095 | "TARGET_SPE" |
1096 | "evmhessfaaw %0,%1,%2" | |
1097 | [(set_attr "type" "veccomplex") | |
1098 | (set_attr "length" "4")]) | |
1099 | ||
1100 | (define_insn "spe_evmhessfanw" | |
1101 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1102 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1103 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1104 | (reg:V2SI SPE_ACC_REGNO)] 572)) | |
1105 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1106 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1107 | "TARGET_SPE" |
1108 | "evmhessfanw %0,%1,%2" | |
1109 | [(set_attr "type" "veccomplex") | |
1110 | (set_attr "length" "4")]) | |
1111 | ||
1112 | (define_insn "spe_evmhessfa" | |
1113 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1114 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1115 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 573)) | |
1116 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1117 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1118 | "TARGET_SPE" |
1119 | "evmhessfa %0,%1,%2" | |
1120 | [(set_attr "type" "veccomplex") | |
1121 | (set_attr "length" "4")]) | |
1122 | ||
1123 | (define_insn "spe_evmhessf" | |
1124 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1125 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1126 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 574)) | |
1127 | (clobber (reg:SI SPEFSCR_REGNO))] | |
1128 | "TARGET_SPE" | |
1129 | "evmhessf %0,%1,%2" | |
1130 | [(set_attr "type" "veccomplex") | |
1131 | (set_attr "length" "4")]) | |
1132 | ||
1133 | (define_insn "spe_evmhessiaaw" | |
1134 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1135 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1136 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1137 | (reg:V2SI SPE_ACC_REGNO)] 575)) | |
1138 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1139 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 | 1140 | "TARGET_SPE" |
c9b93e1a | 1141 | "evmhessiaaw %0,%1,%2" |
a3170dc6 AH |
1142 | [(set_attr "type" "veccomplex") |
1143 | (set_attr "length" "4")]) | |
1144 | ||
1145 | (define_insn "spe_evmhessianw" | |
1146 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1147 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1148 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1149 | (reg:V2SI SPE_ACC_REGNO)] 576)) | |
1150 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1151 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1152 | "TARGET_SPE" |
1153 | "evmhessianw %0,%1,%2" | |
1154 | [(set_attr "type" "veccomplex") | |
1155 | (set_attr "length" "4")]) | |
1156 | ||
1157 | (define_insn "spe_evmheumiaaw" | |
1158 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1159 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1160 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1161 | (reg:V2SI SPE_ACC_REGNO)] 577)) | |
54da776f | 1162 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1163 | "TARGET_SPE" |
1164 | "evmheumiaaw %0,%1,%2" | |
1165 | [(set_attr "type" "veccomplex") | |
1166 | (set_attr "length" "4")]) | |
1167 | ||
1168 | (define_insn "spe_evmheumianw" | |
1169 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1170 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1171 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1172 | (reg:V2SI SPE_ACC_REGNO)] 578)) | |
54da776f | 1173 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1174 | "TARGET_SPE" |
1175 | "evmheumianw %0,%1,%2" | |
1176 | [(set_attr "type" "veccomplex") | |
1177 | (set_attr "length" "4")]) | |
1178 | ||
1179 | (define_insn "spe_evmheumia" | |
1180 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1181 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1182 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 579)) | |
54da776f | 1183 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1184 | "TARGET_SPE" |
1185 | "evmheumia %0,%1,%2" | |
1186 | [(set_attr "type" "veccomplex") | |
1187 | (set_attr "length" "4")]) | |
1188 | ||
1189 | (define_insn "spe_evmheumi" | |
1190 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1191 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1192 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 580))] | |
1193 | "TARGET_SPE" | |
1194 | "evmheumi %0,%1,%2" | |
1195 | [(set_attr "type" "veccomplex") | |
1196 | (set_attr "length" "4")]) | |
1197 | ||
1198 | (define_insn "spe_evmheusiaaw" | |
1199 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1200 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1201 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1202 | (reg:V2SI SPE_ACC_REGNO)] 581)) | |
1203 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1204 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1205 | "TARGET_SPE" |
1206 | "evmheusiaaw %0,%1,%2" | |
1207 | [(set_attr "type" "veccomplex") | |
1208 | (set_attr "length" "4")]) | |
1209 | ||
1210 | (define_insn "spe_evmheusianw" | |
1211 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1212 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1213 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1214 | (reg:V2SI SPE_ACC_REGNO)] 582)) | |
1215 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1216 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1217 | "TARGET_SPE" |
1218 | "evmheusianw %0,%1,%2" | |
1219 | [(set_attr "type" "veccomplex") | |
1220 | (set_attr "length" "4")]) | |
1221 | ||
1222 | (define_insn "spe_evmhogsmfaa" | |
1223 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1224 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1225 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1226 | (reg:V2SI SPE_ACC_REGNO)] 583)) | |
54da776f | 1227 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1228 | "TARGET_SPE" |
1229 | "evmhogsmfaa %0,%1,%2" | |
1230 | [(set_attr "type" "veccomplex") | |
1231 | (set_attr "length" "4")]) | |
1232 | ||
1233 | (define_insn "spe_evmhogsmfan" | |
1234 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1235 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1236 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1237 | (reg:V2SI SPE_ACC_REGNO)] 584)) | |
54da776f | 1238 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1239 | "TARGET_SPE" |
1240 | "evmhogsmfan %0,%1,%2" | |
1241 | [(set_attr "type" "veccomplex") | |
1242 | (set_attr "length" "4")]) | |
1243 | ||
1244 | (define_insn "spe_evmhogsmiaa" | |
1245 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1246 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1247 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1248 | (reg:V2SI SPE_ACC_REGNO)] 585)) | |
54da776f | 1249 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1250 | "TARGET_SPE" |
1251 | "evmhogsmiaa %0,%1,%2" | |
1252 | [(set_attr "type" "veccomplex") | |
1253 | (set_attr "length" "4")]) | |
1254 | ||
1255 | (define_insn "spe_evmhogsmian" | |
1256 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1257 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1258 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1259 | (reg:V2SI SPE_ACC_REGNO)] 586)) | |
54da776f | 1260 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1261 | "TARGET_SPE" |
1262 | "evmhogsmian %0,%1,%2" | |
1263 | [(set_attr "type" "veccomplex") | |
1264 | (set_attr "length" "4")]) | |
1265 | ||
1266 | (define_insn "spe_evmhogumiaa" | |
1267 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1268 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1269 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1270 | (reg:V2SI SPE_ACC_REGNO)] 587)) | |
54da776f | 1271 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1272 | "TARGET_SPE" |
1273 | "evmhogumiaa %0,%1,%2" | |
1274 | [(set_attr "type" "veccomplex") | |
1275 | (set_attr "length" "4")]) | |
1276 | ||
1277 | (define_insn "spe_evmhogumian" | |
1278 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1279 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1280 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1281 | (reg:V2SI SPE_ACC_REGNO)] 588)) | |
54da776f | 1282 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1283 | "TARGET_SPE" |
1284 | "evmhogumian %0,%1,%2" | |
1285 | [(set_attr "type" "veccomplex") | |
1286 | (set_attr "length" "4")]) | |
1287 | ||
1288 | (define_insn "spe_evmhosmfaaw" | |
1289 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1290 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1291 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1292 | (reg:V2SI SPE_ACC_REGNO)] 589)) | |
54da776f | 1293 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1294 | "TARGET_SPE" |
1295 | "evmhosmfaaw %0,%1,%2" | |
1296 | [(set_attr "type" "veccomplex") | |
1297 | (set_attr "length" "4")]) | |
1298 | ||
1299 | (define_insn "spe_evmhosmfanw" | |
1300 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1301 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1302 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1303 | (reg:V2SI SPE_ACC_REGNO)] 590)) | |
54da776f | 1304 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1305 | "TARGET_SPE" |
1306 | "evmhosmfanw %0,%1,%2" | |
1307 | [(set_attr "type" "veccomplex") | |
1308 | (set_attr "length" "4")]) | |
1309 | ||
1310 | (define_insn "spe_evmhosmfa" | |
1311 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1312 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1313 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 591))] | |
1314 | "TARGET_SPE" | |
1315 | "evmhosmfa %0,%1,%2" | |
1316 | [(set_attr "type" "veccomplex") | |
1317 | (set_attr "length" "4")]) | |
1318 | ||
1319 | (define_insn "spe_evmhosmf" | |
1320 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1321 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1322 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 592)) | |
54da776f | 1323 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1324 | "TARGET_SPE" |
1325 | "evmhosmf %0,%1,%2" | |
1326 | [(set_attr "type" "veccomplex") | |
1327 | (set_attr "length" "4")]) | |
1328 | ||
1329 | (define_insn "spe_evmhosmiaaw" | |
1330 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1331 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1332 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1333 | (reg:V2SI SPE_ACC_REGNO)] 593)) | |
54da776f | 1334 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1335 | "TARGET_SPE" |
1336 | "evmhosmiaaw %0,%1,%2" | |
1337 | [(set_attr "type" "veccomplex") | |
1338 | (set_attr "length" "4")]) | |
1339 | ||
1340 | (define_insn "spe_evmhosmianw" | |
1341 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1342 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1343 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1344 | (reg:V2SI SPE_ACC_REGNO)] 594)) | |
54da776f | 1345 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1346 | "TARGET_SPE" |
1347 | "evmhosmianw %0,%1,%2" | |
1348 | [(set_attr "type" "veccomplex") | |
1349 | (set_attr "length" "4")]) | |
1350 | ||
1351 | (define_insn "spe_evmhosmia" | |
1352 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1353 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1354 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 595)) | |
54da776f | 1355 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1356 | "TARGET_SPE" |
1357 | "evmhosmia %0,%1,%2" | |
1358 | [(set_attr "type" "veccomplex") | |
1359 | (set_attr "length" "4")]) | |
1360 | ||
1361 | (define_insn "spe_evmhosmi" | |
1362 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1363 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1364 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 596))] | |
1365 | "TARGET_SPE" | |
1366 | "evmhosmi %0,%1,%2" | |
1367 | [(set_attr "type" "veccomplex") | |
1368 | (set_attr "length" "4")]) | |
1369 | ||
1370 | (define_insn "spe_evmhossfaaw" | |
1371 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1372 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1373 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1374 | (reg:V2SI SPE_ACC_REGNO)] 597)) | |
1375 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1376 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1377 | "TARGET_SPE" |
1378 | "evmhossfaaw %0,%1,%2" | |
1379 | [(set_attr "type" "veccomplex") | |
1380 | (set_attr "length" "4")]) | |
1381 | ||
1382 | (define_insn "spe_evmhossfanw" | |
1383 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1384 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1385 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1386 | (reg:V2SI SPE_ACC_REGNO)] 598)) | |
1387 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1388 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1389 | "TARGET_SPE" |
1390 | "evmhossfanw %0,%1,%2" | |
1391 | [(set_attr "type" "veccomplex") | |
1392 | (set_attr "length" "4")]) | |
1393 | ||
1394 | (define_insn "spe_evmhossfa" | |
1395 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1396 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1397 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1398 | (reg:V2SI SPE_ACC_REGNO)] 599)) | |
1399 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1400 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1401 | "TARGET_SPE" |
1402 | "evmhossfa %0,%1,%2" | |
1403 | [(set_attr "type" "veccomplex") | |
1404 | (set_attr "length" "4")]) | |
1405 | ||
1406 | (define_insn "spe_evmhossf" | |
1407 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1408 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1409 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 600)) | |
1410 | (clobber (reg:SI SPEFSCR_REGNO))] | |
1411 | "TARGET_SPE" | |
1412 | "evmhossf %0,%1,%2" | |
1413 | [(set_attr "type" "veccomplex") | |
1414 | (set_attr "length" "4")]) | |
1415 | ||
1416 | (define_insn "spe_evmhossiaaw" | |
1417 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1418 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1419 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1420 | (reg:V2SI SPE_ACC_REGNO)] 601)) | |
1421 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1422 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1423 | "TARGET_SPE" |
1424 | "evmhossiaaw %0,%1,%2" | |
1425 | [(set_attr "type" "veccomplex") | |
1426 | (set_attr "length" "4")]) | |
1427 | ||
1428 | (define_insn "spe_evmhossianw" | |
1429 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1430 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1431 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1432 | (reg:V2SI SPE_ACC_REGNO)] 602)) | |
1433 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1434 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1435 | "TARGET_SPE" |
1436 | "evmhossianw %0,%1,%2" | |
1437 | [(set_attr "type" "veccomplex") | |
1438 | (set_attr "length" "4")]) | |
1439 | ||
1440 | (define_insn "spe_evmhoumiaaw" | |
1441 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1442 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1443 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1444 | (reg:V2SI SPE_ACC_REGNO)] 603)) | |
54da776f | 1445 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1446 | "TARGET_SPE" |
1447 | "evmhoumiaaw %0,%1,%2" | |
1448 | [(set_attr "type" "veccomplex") | |
1449 | (set_attr "length" "4")]) | |
1450 | ||
1451 | (define_insn "spe_evmhoumianw" | |
1452 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1453 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1454 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1455 | (reg:V2SI SPE_ACC_REGNO)] 604)) | |
54da776f | 1456 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1457 | "TARGET_SPE" |
1458 | "evmhoumianw %0,%1,%2" | |
1459 | [(set_attr "type" "veccomplex") | |
1460 | (set_attr "length" "4")]) | |
1461 | ||
1462 | (define_insn "spe_evmhoumia" | |
1463 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1464 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1465 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 605)) | |
54da776f | 1466 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1467 | "TARGET_SPE" |
1468 | "evmhoumia %0,%1,%2" | |
1469 | [(set_attr "type" "veccomplex") | |
1470 | (set_attr "length" "4")]) | |
1471 | ||
1472 | (define_insn "spe_evmhoumi" | |
1473 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1474 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1475 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 606))] | |
1476 | "TARGET_SPE" | |
1477 | "evmhoumi %0,%1,%2" | |
1478 | [(set_attr "type" "veccomplex") | |
1479 | (set_attr "length" "4")]) | |
1480 | ||
1481 | (define_insn "spe_evmhousiaaw" | |
1482 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1483 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1484 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1485 | (reg:V2SI SPE_ACC_REGNO)] 607)) | |
1486 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1487 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1488 | "TARGET_SPE" |
1489 | "evmhousiaaw %0,%1,%2" | |
1490 | [(set_attr "type" "veccomplex") | |
1491 | (set_attr "length" "4")]) | |
1492 | ||
1493 | (define_insn "spe_evmhousianw" | |
1494 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1495 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1496 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1497 | (reg:V2SI SPE_ACC_REGNO)] 608)) | |
1498 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1499 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1500 | "TARGET_SPE" |
1501 | "evmhousianw %0,%1,%2" | |
1502 | [(set_attr "type" "veccomplex") | |
1503 | (set_attr "length" "4")]) | |
1504 | ||
1505 | (define_insn "spe_evmmlssfa" | |
1506 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1507 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1508 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 609))] | |
1509 | "TARGET_SPE" | |
1510 | "evmmlssfa %0,%1,%2" | |
1511 | [(set_attr "type" "veccomplex") | |
1512 | (set_attr "length" "4")]) | |
1513 | ||
1514 | (define_insn "spe_evmmlssf" | |
1515 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1516 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1517 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 610))] | |
1518 | "TARGET_SPE" | |
1519 | "evmmlssf %0,%1,%2" | |
1520 | [(set_attr "type" "veccomplex") | |
1521 | (set_attr "length" "4")]) | |
1522 | ||
1523 | (define_insn "spe_evmwhsmfa" | |
1524 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1525 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1526 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 611)) | |
54da776f | 1527 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1528 | "TARGET_SPE" |
1529 | "evmwhsmfa %0,%1,%2" | |
1530 | [(set_attr "type" "veccomplex") | |
1531 | (set_attr "length" "4")]) | |
1532 | ||
1533 | (define_insn "spe_evmwhsmf" | |
1534 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1535 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1536 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 612))] | |
1537 | "TARGET_SPE" | |
1538 | "evmwhsmf %0,%1,%2" | |
1539 | [(set_attr "type" "veccomplex") | |
1540 | (set_attr "length" "4")]) | |
1541 | ||
1542 | (define_insn "spe_evmwhsmia" | |
1543 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1544 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1545 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 613)) | |
54da776f | 1546 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1547 | "TARGET_SPE" |
1548 | "evmwhsmia %0,%1,%2" | |
1549 | [(set_attr "type" "veccomplex") | |
1550 | (set_attr "length" "4")]) | |
1551 | ||
1552 | (define_insn "spe_evmwhsmi" | |
1553 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1554 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1555 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 614))] | |
1556 | "TARGET_SPE" | |
1557 | "evmwhsmi %0,%1,%2" | |
1558 | [(set_attr "type" "veccomplex") | |
1559 | (set_attr "length" "4")]) | |
1560 | ||
1561 | (define_insn "spe_evmwhssfa" | |
1562 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1563 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1564 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 615)) | |
1565 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1566 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1567 | "TARGET_SPE" |
1568 | "evmwhssfa %0,%1,%2" | |
1569 | [(set_attr "type" "veccomplex") | |
1570 | (set_attr "length" "4")]) | |
1571 | ||
1572 | (define_insn "spe_evmwhusian" | |
1573 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1574 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1575 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 626))] | |
1576 | "TARGET_SPE" | |
1577 | "evmwhusian %0,%1,%2" | |
1578 | [(set_attr "type" "veccomplex") | |
1579 | (set_attr "length" "4")]) | |
1580 | ||
1581 | (define_insn "spe_evmwhssf" | |
1582 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1583 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1584 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 628)) | |
1585 | (clobber (reg:SI SPEFSCR_REGNO))] | |
1586 | "TARGET_SPE" | |
1587 | "evmwhssf %0,%1,%2" | |
1588 | [(set_attr "type" "veccomplex") | |
1589 | (set_attr "length" "4")]) | |
1590 | ||
1591 | (define_insn "spe_evmwhumia" | |
1592 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1593 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1594 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 629)) | |
54da776f | 1595 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1596 | "TARGET_SPE" |
1597 | "evmwhumia %0,%1,%2" | |
1598 | [(set_attr "type" "veccomplex") | |
1599 | (set_attr "length" "4")]) | |
1600 | ||
1601 | (define_insn "spe_evmwhumi" | |
1602 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1603 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1604 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 630))] | |
1605 | "TARGET_SPE" | |
1606 | "evmwhumi %0,%1,%2" | |
1607 | [(set_attr "type" "veccomplex") | |
1608 | (set_attr "length" "4")]) | |
1609 | ||
a3170dc6 AH |
1610 | (define_insn "spe_evmwlsmiaaw" |
1611 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1612 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1613 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1614 | (reg:V2SI SPE_ACC_REGNO)] 635)) | |
54da776f | 1615 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1616 | "TARGET_SPE" |
1617 | "evmwlsmiaaw %0,%1,%2" | |
1618 | [(set_attr "type" "veccomplex") | |
1619 | (set_attr "length" "4")]) | |
1620 | ||
1621 | (define_insn "spe_evmwlsmianw" | |
1622 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1623 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1624 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1625 | (reg:V2SI SPE_ACC_REGNO)] 636)) | |
54da776f | 1626 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1627 | "TARGET_SPE" |
1628 | "evmwlsmianw %0,%1,%2" | |
a3170dc6 AH |
1629 | [(set_attr "type" "veccomplex") |
1630 | (set_attr "length" "4")]) | |
1631 | ||
1632 | (define_insn "spe_evmwlssiaaw" | |
1633 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1634 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1635 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1636 | (reg:V2SI SPE_ACC_REGNO)] 641)) | |
1637 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1638 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1639 | "TARGET_SPE" |
1640 | "evmwlssiaaw %0,%1,%2" | |
1641 | [(set_attr "type" "veccomplex") | |
1642 | (set_attr "length" "4")]) | |
1643 | ||
1644 | (define_insn "spe_evmwlssianw" | |
1645 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1646 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1647 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1648 | (reg:V2SI SPE_ACC_REGNO)] 642)) | |
1649 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1650 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1651 | "TARGET_SPE" |
1652 | "evmwlssianw %0,%1,%2" | |
1653 | [(set_attr "type" "veccomplex") | |
1654 | (set_attr "length" "4")]) | |
1655 | ||
1656 | (define_insn "spe_evmwlumiaaw" | |
1657 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1658 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1659 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1660 | (reg:V2SI SPE_ACC_REGNO)] 643)) | |
54da776f | 1661 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1662 | "TARGET_SPE" |
1663 | "evmwlumiaaw %0,%1,%2" | |
1664 | [(set_attr "type" "veccomplex") | |
1665 | (set_attr "length" "4")]) | |
1666 | ||
1667 | (define_insn "spe_evmwlumianw" | |
1668 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1669 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1670 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1671 | (reg:V2SI SPE_ACC_REGNO)] 644)) | |
54da776f | 1672 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1673 | "TARGET_SPE" |
1674 | "evmwlumianw %0,%1,%2" | |
1675 | [(set_attr "type" "veccomplex") | |
1676 | (set_attr "length" "4")]) | |
1677 | ||
1678 | (define_insn "spe_evmwlumia" | |
1679 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1680 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1681 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 645)) | |
54da776f | 1682 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1683 | "TARGET_SPE" |
1684 | "evmwlumia %0,%1,%2" | |
1685 | [(set_attr "type" "veccomplex") | |
1686 | (set_attr "length" "4")]) | |
1687 | ||
1688 | (define_insn "spe_evmwlumi" | |
1689 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1690 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1691 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 646))] | |
1692 | "TARGET_SPE" | |
1693 | "evmwlumi %0,%1,%2" | |
1694 | [(set_attr "type" "veccomplex") | |
1695 | (set_attr "length" "4")]) | |
1696 | ||
1697 | (define_insn "spe_evmwlusiaaw" | |
1698 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1699 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1700 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1701 | (reg:V2SI SPE_ACC_REGNO)] 647)) | |
1702 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1703 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1704 | "TARGET_SPE" |
1705 | "evmwlusiaaw %0,%1,%2" | |
1706 | [(set_attr "type" "veccomplex") | |
1707 | (set_attr "length" "4")]) | |
1708 | ||
1709 | (define_insn "spe_evmwlusianw" | |
1710 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1711 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1712 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1713 | (reg:V2SI SPE_ACC_REGNO)] 648)) | |
1714 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1715 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1716 | "TARGET_SPE" |
1717 | "evmwlusianw %0,%1,%2" | |
1718 | [(set_attr "type" "veccomplex") | |
1719 | (set_attr "length" "4")]) | |
1720 | ||
1721 | (define_insn "spe_evmwsmfaa" | |
1722 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1723 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1724 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1725 | (reg:V2SI SPE_ACC_REGNO)] 649)) | |
54da776f | 1726 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1727 | "TARGET_SPE" |
1728 | "evmwsmfaa %0,%1,%2" | |
1729 | [(set_attr "type" "veccomplex") | |
1730 | (set_attr "length" "4")]) | |
1731 | ||
1732 | (define_insn "spe_evmwsmfan" | |
1733 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1734 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1735 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1736 | (reg:V2SI SPE_ACC_REGNO)] 650)) | |
54da776f | 1737 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1738 | "TARGET_SPE" |
1739 | "evmwsmfan %0,%1,%2" | |
1740 | [(set_attr "type" "veccomplex") | |
1741 | (set_attr "length" "4")]) | |
1742 | ||
1743 | (define_insn "spe_evmwsmfa" | |
1744 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1745 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1746 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 651)) | |
54da776f | 1747 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1748 | "TARGET_SPE" |
1749 | "evmwsmfa %0,%1,%2" | |
1750 | [(set_attr "type" "veccomplex") | |
1751 | (set_attr "length" "4")]) | |
1752 | ||
1753 | (define_insn "spe_evmwsmf" | |
1754 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1755 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1756 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 652))] | |
1757 | "TARGET_SPE" | |
1758 | "evmwsmf %0,%1,%2" | |
1759 | [(set_attr "type" "veccomplex") | |
1760 | (set_attr "length" "4")]) | |
1761 | ||
1762 | (define_insn "spe_evmwsmiaa" | |
1763 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1764 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1765 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1766 | (reg:V2SI SPE_ACC_REGNO)] 653)) | |
54da776f | 1767 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1768 | "TARGET_SPE" |
1769 | "evmwsmiaa %0,%1,%2" | |
1770 | [(set_attr "type" "veccomplex") | |
1771 | (set_attr "length" "4")]) | |
1772 | ||
1773 | (define_insn "spe_evmwsmian" | |
1774 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1775 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1776 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1777 | (reg:V2SI SPE_ACC_REGNO)] 654)) | |
54da776f | 1778 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1779 | "TARGET_SPE" |
1780 | "evmwsmian %0,%1,%2" | |
1781 | [(set_attr "type" "veccomplex") | |
1782 | (set_attr "length" "4")]) | |
1783 | ||
1784 | (define_insn "spe_evmwsmia" | |
1785 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1786 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1787 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 655)) | |
54da776f | 1788 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1789 | "TARGET_SPE" |
1790 | "evmwsmia %0,%1,%2" | |
1791 | [(set_attr "type" "veccomplex") | |
1792 | (set_attr "length" "4")]) | |
1793 | ||
1794 | (define_insn "spe_evmwsmi" | |
1795 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1796 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1797 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 656))] | |
1798 | "TARGET_SPE" | |
1799 | "evmwsmi %0,%1,%2" | |
1800 | [(set_attr "type" "veccomplex") | |
1801 | (set_attr "length" "4")]) | |
1802 | ||
1803 | (define_insn "spe_evmwssfaa" | |
1804 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1805 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1806 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1807 | (reg:V2SI SPE_ACC_REGNO)] 657)) | |
1808 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1809 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1810 | "TARGET_SPE" |
1811 | "evmwssfaa %0,%1,%2" | |
1812 | [(set_attr "type" "veccomplex") | |
1813 | (set_attr "length" "4")]) | |
1814 | ||
1815 | (define_insn "spe_evmwssfan" | |
1816 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1817 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1818 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1819 | (reg:V2SI SPE_ACC_REGNO)] 658)) | |
1820 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1821 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1822 | "TARGET_SPE" |
1823 | "evmwssfan %0,%1,%2" | |
1824 | [(set_attr "type" "veccomplex") | |
1825 | (set_attr "length" "4")]) | |
1826 | ||
1827 | (define_insn "spe_evmwssfa" | |
1828 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1829 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1830 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 659)) | |
1831 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1832 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1833 | "TARGET_SPE" |
1834 | "evmwssfa %0,%1,%2" | |
1835 | [(set_attr "type" "veccomplex") | |
1836 | (set_attr "length" "4")]) | |
1837 | ||
1838 | (define_insn "spe_evmwssf" | |
1839 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1840 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1841 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 660)) | |
1842 | (clobber (reg:SI SPEFSCR_REGNO))] | |
1843 | "TARGET_SPE" | |
1844 | "evmwssf %0,%1,%2" | |
1845 | [(set_attr "type" "veccomplex") | |
1846 | (set_attr "length" "4")]) | |
1847 | ||
1848 | (define_insn "spe_evmwumiaa" | |
1849 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1850 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1851 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1852 | (reg:V2SI SPE_ACC_REGNO)] 661)) | |
54da776f | 1853 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1854 | "TARGET_SPE" |
1855 | "evmwumiaa %0,%1,%2" | |
1856 | [(set_attr "type" "veccomplex") | |
1857 | (set_attr "length" "4")]) | |
1858 | ||
1859 | (define_insn "spe_evmwumian" | |
1860 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1861 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1862 | (match_operand:V2SI 2 "gpc_reg_operand" "r") | |
1863 | (reg:V2SI SPE_ACC_REGNO)] 662)) | |
54da776f | 1864 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1865 | "TARGET_SPE" |
1866 | "evmwumian %0,%1,%2" | |
1867 | [(set_attr "type" "veccomplex") | |
1868 | (set_attr "length" "4")]) | |
1869 | ||
1870 | (define_insn "spe_evmwumia" | |
1871 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1872 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1873 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 663)) | |
54da776f | 1874 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1875 | "TARGET_SPE" |
1876 | "evmwumia %0,%1,%2" | |
1877 | [(set_attr "type" "veccomplex") | |
1878 | (set_attr "length" "4")]) | |
1879 | ||
1880 | (define_insn "spe_evmwumi" | |
1881 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1882 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1883 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 664))] | |
1884 | "TARGET_SPE" | |
1885 | "evmwumi %0,%1,%2" | |
1886 | [(set_attr "type" "veccomplex") | |
1887 | (set_attr "length" "4")]) | |
1888 | ||
1889 | (define_insn "spe_evaddw" | |
1890 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1891 | (plus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1892 | (match_operand:V2SI 2 "gpc_reg_operand" "r")))] | |
1893 | "TARGET_SPE" | |
1894 | "evaddw %0,%1,%2" | |
5e8006fa | 1895 | [(set_attr "type" "vecsimple") |
a3170dc6 AH |
1896 | (set_attr "length" "4")]) |
1897 | ||
1898 | (define_insn "spe_evaddusiaaw" | |
1899 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1900 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1901 | (reg:V2SI SPE_ACC_REGNO)] 673)) | |
1902 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1903 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1904 | "TARGET_SPE" |
1905 | "evaddusiaaw %0,%1" | |
1906 | [(set_attr "type" "veccomplex") | |
1907 | (set_attr "length" "4")]) | |
1908 | ||
1909 | (define_insn "spe_evaddumiaaw" | |
1910 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1911 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1912 | (reg:V2SI SPE_ACC_REGNO)] 674)) | |
54da776f | 1913 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1914 | "TARGET_SPE" |
1915 | "evaddumiaaw %0,%1" | |
1916 | [(set_attr "type" "veccomplex") | |
1917 | (set_attr "length" "4")]) | |
1918 | ||
1919 | (define_insn "spe_evaddssiaaw" | |
1920 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1921 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1922 | (reg:V2SI SPE_ACC_REGNO)] 675)) | |
1923 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1924 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1925 | "TARGET_SPE" |
1926 | "evaddssiaaw %0,%1" | |
1927 | [(set_attr "type" "veccomplex") | |
1928 | (set_attr "length" "4")]) | |
1929 | ||
1930 | (define_insn "spe_evaddsmiaaw" | |
1931 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1932 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1933 | (reg:V2SI SPE_ACC_REGNO)] 676)) | |
54da776f | 1934 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1935 | "TARGET_SPE" |
1936 | "evaddsmiaaw %0,%1" | |
1937 | [(set_attr "type" "veccomplex") | |
1938 | (set_attr "length" "4")]) | |
1939 | ||
1940 | (define_insn "spe_evaddiw" | |
1941 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1942 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1943 | (match_operand:QI 2 "immediate_operand" "i")] 677))] | |
1944 | "TARGET_SPE" | |
1945 | "evaddiw %0,%1,%2" | |
5e8006fa | 1946 | [(set_attr "type" "vecsimple") |
a3170dc6 AH |
1947 | (set_attr "length" "4")]) |
1948 | ||
1949 | (define_insn "spe_evsubifw" | |
1950 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1951 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1952 | (match_operand:QI 2 "immediate_operand" "i")] 678))] | |
1953 | "TARGET_SPE" | |
1954 | "evsubifw %0,%2,%1" | |
1955 | [(set_attr "type" "veccomplex") | |
1956 | (set_attr "length" "4")]) | |
1957 | ||
1958 | (define_insn "spe_evsubfw" | |
1959 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1960 | (minus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1961 | (match_operand:V2SI 2 "gpc_reg_operand" "r")))] | |
1962 | "TARGET_SPE" | |
12850cf2 | 1963 | "evsubfw %0,%2,%1" |
a3170dc6 AH |
1964 | [(set_attr "type" "veccomplex") |
1965 | (set_attr "length" "4")]) | |
1966 | ||
1967 | (define_insn "spe_evsubfusiaaw" | |
1968 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1969 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1970 | (reg:V2SI SPE_ACC_REGNO)] 679)) | |
1971 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1972 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1973 | "TARGET_SPE" |
1974 | "evsubfusiaaw %0,%1" | |
1975 | [(set_attr "type" "veccomplex") | |
1976 | (set_attr "length" "4")]) | |
1977 | ||
1978 | (define_insn "spe_evsubfumiaaw" | |
1979 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1980 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1981 | (reg:V2SI SPE_ACC_REGNO)] 680)) | |
54da776f | 1982 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1983 | "TARGET_SPE" |
1984 | "evsubfumiaaw %0,%1" | |
1985 | [(set_attr "type" "veccomplex") | |
1986 | (set_attr "length" "4")]) | |
1987 | ||
1988 | (define_insn "spe_evsubfssiaaw" | |
1989 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
1990 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
1991 | (reg:V2SI SPE_ACC_REGNO)] 681)) | |
1992 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 1993 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
1994 | "TARGET_SPE" |
1995 | "evsubfssiaaw %0,%1" | |
1996 | [(set_attr "type" "veccomplex") | |
1997 | (set_attr "length" "4")]) | |
1998 | ||
1999 | (define_insn "spe_evsubfsmiaaw" | |
2000 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2001 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2002 | (reg:V2SI SPE_ACC_REGNO)] 682)) | |
54da776f | 2003 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
2004 | "TARGET_SPE" |
2005 | "evsubfsmiaaw %0,%1" | |
2006 | [(set_attr "type" "veccomplex") | |
2007 | (set_attr "length" "4")]) | |
2008 | ||
2009 | (define_insn "spe_evmra" | |
2010 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2011 | (match_operand:V2SI 1 "gpc_reg_operand" "r")) | |
c3021e5d AH |
2012 | (set (reg:V2SI SPE_ACC_REGNO) |
2013 | (unspec:V2SI [(match_dup 1)] 726))] | |
a3170dc6 AH |
2014 | "TARGET_SPE" |
2015 | "evmra %0,%1" | |
2016 | [(set_attr "type" "veccomplex") | |
2017 | (set_attr "length" "4")]) | |
2018 | ||
2019 | (define_insn "spe_evdivws" | |
2020 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2021 | (div:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2022 | (match_operand:V2SI 2 "gpc_reg_operand" "r"))) | |
2023 | (clobber (reg:SI SPEFSCR_REGNO))] | |
2024 | "TARGET_SPE" | |
2025 | "evdivws %0,%1,%2" | |
5e8006fa | 2026 | [(set_attr "type" "vecdiv") |
a3170dc6 AH |
2027 | (set_attr "length" "4")]) |
2028 | ||
2029 | (define_insn "spe_evdivwu" | |
2030 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2031 | (udiv:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2032 | (match_operand:V2SI 2 "gpc_reg_operand" "r"))) | |
2033 | (clobber (reg:SI SPEFSCR_REGNO))] | |
2034 | "TARGET_SPE" | |
2035 | "evdivwu %0,%1,%2" | |
5e8006fa | 2036 | [(set_attr "type" "vecdiv") |
a3170dc6 AH |
2037 | (set_attr "length" "4")]) |
2038 | ||
2039 | (define_insn "spe_evsplatfi" | |
2040 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2041 | (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 684))] | |
2042 | "TARGET_SPE" | |
c9b93e1a | 2043 | "evsplatfi %0,%1" |
a3170dc6 AH |
2044 | [(set_attr "type" "vecperm") |
2045 | (set_attr "length" "4")]) | |
2046 | ||
2047 | (define_insn "spe_evsplati" | |
2048 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2049 | (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 685))] | |
2050 | "TARGET_SPE" | |
c9b93e1a | 2051 | "evsplati %0,%1" |
a3170dc6 AH |
2052 | [(set_attr "type" "vecperm") |
2053 | (set_attr "length" "4")]) | |
2054 | ||
2055 | (define_insn "spe_evstdd" | |
2056 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2057 | (match_operand:QI 1 "immediate_operand" "i"))) | |
2058 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2059 | (unspec [(const_int 0)] 686)] | |
626098f9 AH |
2060 | "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" |
2061 | "evstdd %2,%1*8(%0)" | |
a3170dc6 AH |
2062 | [(set_attr "type" "vecstore") |
2063 | (set_attr "length" "4")]) | |
2064 | ||
2065 | (define_insn "spe_evstddx" | |
2066 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2067 | (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
2068 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2069 | (unspec [(const_int 0)] 687)] | |
2070 | "TARGET_SPE" | |
2071 | "evstddx %2,%0,%1" | |
2072 | [(set_attr "type" "vecstore") | |
2073 | (set_attr "length" "4")]) | |
2074 | ||
2075 | (define_insn "spe_evstdh" | |
2076 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2077 | (match_operand:QI 1 "immediate_operand" "i"))) | |
2078 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2079 | (unspec [(const_int 0)] 688)] | |
626098f9 AH |
2080 | "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" |
2081 | "evstdh %2,%1*8(%0)" | |
a3170dc6 AH |
2082 | [(set_attr "type" "vecstore") |
2083 | (set_attr "length" "4")]) | |
2084 | ||
2085 | (define_insn "spe_evstdhx" | |
2086 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2087 | (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
2088 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2089 | (unspec [(const_int 0)] 689)] | |
2090 | "TARGET_SPE" | |
2091 | "evstdhx %2,%0,%1" | |
2092 | [(set_attr "type" "vecstore") | |
2093 | (set_attr "length" "4")]) | |
2094 | ||
2095 | (define_insn "spe_evstdw" | |
2096 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2097 | (match_operand:QI 1 "immediate_operand" "i"))) | |
2098 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2099 | (unspec [(const_int 0)] 690)] | |
626098f9 AH |
2100 | "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" |
2101 | "evstdw %2,%1*8(%0)" | |
a3170dc6 AH |
2102 | [(set_attr "type" "vecstore") |
2103 | (set_attr "length" "4")]) | |
2104 | ||
2105 | (define_insn "spe_evstdwx" | |
2106 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2107 | (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
2108 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2109 | (unspec [(const_int 0)] 691)] | |
2110 | "TARGET_SPE" | |
2111 | "evstdwx %2,%0,%1" | |
2112 | [(set_attr "type" "vecstore") | |
2113 | (set_attr "length" "4")]) | |
2114 | ||
2115 | (define_insn "spe_evstwhe" | |
2116 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2117 | (match_operand:QI 1 "immediate_operand" "i"))) | |
2118 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2119 | (unspec [(const_int 0)] 692)] | |
626098f9 AH |
2120 | "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" |
2121 | "evstwhe %2,%1*4(%0)" | |
a3170dc6 AH |
2122 | [(set_attr "type" "vecstore") |
2123 | (set_attr "length" "4")]) | |
2124 | ||
2125 | (define_insn "spe_evstwhex" | |
2126 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2127 | (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
2128 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2129 | (unspec [(const_int 0)] 693)] | |
2130 | "TARGET_SPE" | |
2131 | "evstwhex %2,%0,%1" | |
2132 | [(set_attr "type" "vecstore") | |
2133 | (set_attr "length" "4")]) | |
2134 | ||
2135 | (define_insn "spe_evstwho" | |
2136 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2137 | (match_operand:QI 1 "immediate_operand" "i"))) | |
2138 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2139 | (unspec [(const_int 0)] 694)] | |
626098f9 AH |
2140 | "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" |
2141 | "evstwho %2,%1*4(%0)" | |
a3170dc6 AH |
2142 | [(set_attr "type" "vecstore") |
2143 | (set_attr "length" "4")]) | |
2144 | ||
2145 | (define_insn "spe_evstwhox" | |
2146 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2147 | (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
2148 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2149 | (unspec [(const_int 0)] 695)] | |
2150 | "TARGET_SPE" | |
2151 | "evstwhox %2,%0,%1" | |
2152 | [(set_attr "type" "vecstore") | |
2153 | (set_attr "length" "4")]) | |
2154 | ||
2155 | (define_insn "spe_evstwwe" | |
2156 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2157 | (match_operand:QI 1 "immediate_operand" "i"))) | |
2158 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2159 | (unspec [(const_int 0)] 696)] | |
626098f9 AH |
2160 | "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" |
2161 | "evstwwe %2,%1*4(%0)" | |
a3170dc6 AH |
2162 | [(set_attr "type" "vecstore") |
2163 | (set_attr "length" "4")]) | |
2164 | ||
2165 | (define_insn "spe_evstwwex" | |
2166 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2167 | (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
2168 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2169 | (unspec [(const_int 0)] 697)] | |
2170 | "TARGET_SPE" | |
2171 | "evstwwex %2,%0,%1" | |
2172 | [(set_attr "type" "vecstore") | |
2173 | (set_attr "length" "4")]) | |
2174 | ||
2175 | (define_insn "spe_evstwwo" | |
2176 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2177 | (match_operand:QI 1 "immediate_operand" "i"))) | |
2178 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2179 | (unspec [(const_int 0)] 698)] | |
626098f9 AH |
2180 | "TARGET_SPE && INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) <= 31" |
2181 | "evstwwo %2,%1*4(%0)" | |
a3170dc6 AH |
2182 | [(set_attr "type" "vecstore") |
2183 | (set_attr "length" "4")]) | |
2184 | ||
2185 | (define_insn "spe_evstwwox" | |
2186 | [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") | |
2187 | (match_operand:SI 1 "gpc_reg_operand" "r"))) | |
2188 | (match_operand:V2SI 2 "gpc_reg_operand" "r")) | |
2189 | (unspec [(const_int 0)] 699)] | |
2190 | "TARGET_SPE" | |
2191 | "evstwwox %2,%0,%1" | |
2192 | [(set_attr "type" "vecstore") | |
2193 | (set_attr "length" "4")]) | |
2194 | ||
7a2f7870 | 2195 | ;; Double-precision floating point instructions. |
54b695e7 AH |
2196 | |
2197 | ;; FIXME: Add o=r option. | |
2198 | (define_insn "*frob_df_di" | |
2199 | [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r") | |
2200 | (subreg:DF (match_operand:DI 1 "input_operand" "r,m") 0))] | |
2201 | "TARGET_E500_DOUBLE" | |
2202 | "@ | |
d2952008 | 2203 | evmergelo %0,%1,%L1 |
54b695e7 AH |
2204 | evldd%X1 %0,%y1") |
2205 | ||
2206 | (define_insn "*frob_di_df" | |
2207 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&r") | |
2208 | (subreg:DI (match_operand:DF 1 "input_operand" "r") 0))] | |
d2952008 GR |
2209 | "TARGET_E500_DOUBLE" |
2210 | "evmergehi %0,%1,%1\;mr %L0,%1" | |
54b695e7 AH |
2211 | [(set_attr "length" "8")]) |
2212 | ||
2213 | (define_insn "*frob_di_df_2" | |
27714d43 ED |
2214 | [(set (subreg:DF (match_operand:DI 0 "register_operand" "=&r,r") 0) |
2215 | (match_operand:DF 1 "input_operand" "r,m"))] | |
54b695e7 | 2216 | "TARGET_E500_DOUBLE" |
d2952008 GR |
2217 | "* |
2218 | { | |
2219 | switch (which_alternative) | |
2220 | { | |
2221 | default: | |
2222 | gcc_unreachable (); | |
2223 | case 0: | |
2224 | return \"evmergehi %0,%1,%1\;mr %L0,%1\"; | |
2225 | case 1: | |
198bc787 JM |
2226 | /* If the address is not offsettable we need to load the whole |
2227 | doubleword into a 64-bit register and then copy the high word | |
2228 | to form the correct output layout. */ | |
2229 | if (!offsettable_nonstrict_memref_p (operands[1])) | |
2230 | return \"evldd%X1 %L0,%y1\;evmergehi %0,%L0,%L0\"; | |
d2952008 GR |
2231 | /* If the low-address word is used in the address, we must load |
2232 | it last. Otherwise, load it first. Note that we cannot have | |
2233 | auto-increment in that case since the address register is | |
2234 | known to be dead. */ | |
2235 | if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, | |
2236 | operands[1], 0)) | |
2237 | return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\"; | |
2238 | else | |
2239 | return \"{l%U1%X1|lwz%U1%X1} %0,%1\;{l|lwz} %L0,%L1\"; | |
2240 | } | |
2241 | }" | |
2242 | [(set_attr "length" "8,8")]) | |
54b695e7 AH |
2243 | |
2244 | (define_insn "*mov_sidf_e500_subreg0" | |
2245 | [(set (subreg:SI (match_operand:DF 0 "register_operand" "+r") 0) | |
2246 | (match_operand:SI 1 "register_operand" "r"))] | |
2247 | "TARGET_E500_DOUBLE" | |
2248 | "evmergelo %0,%1,%0") | |
2249 | ||
2250 | (define_insn "*mov_sidf_e500_subreg4" | |
2251 | [(set (subreg:SI (match_operand:DF 0 "register_operand" "+r") 4) | |
2252 | (match_operand:SI 1 "register_operand" "r"))] | |
2253 | "TARGET_E500_DOUBLE" | |
2254 | "mr %0,%1") | |
2255 | ||
2256 | ;; FIXME: Allow r=CONST0. | |
7a2f7870 | 2257 | (define_insn "*movdf_e500_double" |
165a5bad | 2258 | [(set (match_operand:DF 0 "rs6000_nonimmediate_operand" "=r,r,m") |
7a2f7870 AH |
2259 | (match_operand:DF 1 "input_operand" "r,m,r"))] |
2260 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE | |
2261 | && (gpc_reg_operand (operands[0], DFmode) | |
2262 | || gpc_reg_operand (operands[1], DFmode))" | |
2263 | "* | |
2264 | { | |
2265 | switch (which_alternative) | |
2266 | { | |
2267 | case 0: | |
2268 | return \"evor %0,%1,%1\"; | |
2269 | case 1: | |
2270 | return \"evldd%X1 %0,%y1\"; | |
2271 | case 2: | |
2272 | return \"evstdd%X0 %1,%y0\"; | |
2273 | default: | |
37409796 | 2274 | gcc_unreachable (); |
7a2f7870 AH |
2275 | } |
2276 | }" | |
2277 | [(set_attr "type" "*,vecload,vecstore") | |
2278 | (set_attr "length" "*,*,*")]) | |
2279 | ||
2280 | (define_insn "spe_truncdfsf2" | |
2281 | [(set (match_operand:SF 0 "gpc_reg_operand" "=r") | |
2282 | (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "r")))] | |
2283 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
2284 | "efscfd %0,%1") | |
2285 | ||
2286 | (define_insn "spe_absdf2" | |
2287 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
2288 | (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r")))] | |
2289 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
2290 | "efdabs %0,%1") | |
2291 | ||
2292 | (define_insn "spe_nabsdf2" | |
2293 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
2294 | (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "r"))))] | |
2295 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
2296 | "efdnabs %0,%1") | |
2297 | ||
2298 | (define_insn "spe_negdf2" | |
2299 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
2300 | (neg:DF (match_operand:DF 1 "gpc_reg_operand" "r")))] | |
2301 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
2302 | "efdneg %0,%1") | |
2303 | ||
2304 | (define_insn "spe_adddf3" | |
2305 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
2306 | (plus:DF (match_operand:DF 1 "gpc_reg_operand" "r") | |
2307 | (match_operand:DF 2 "gpc_reg_operand" "r")))] | |
2308 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
2309 | "efdadd %0,%1,%2") | |
2310 | ||
2311 | (define_insn "spe_subdf3" | |
2312 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
2313 | (minus:DF (match_operand:DF 1 "gpc_reg_operand" "r") | |
2314 | (match_operand:DF 2 "gpc_reg_operand" "r")))] | |
2315 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
2316 | "efdsub %0,%1,%2") | |
2317 | ||
2318 | (define_insn "spe_muldf3" | |
2319 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
2320 | (mult:DF (match_operand:DF 1 "gpc_reg_operand" "r") | |
2321 | (match_operand:DF 2 "gpc_reg_operand" "r")))] | |
2322 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
2323 | "efdmul %0,%1,%2") | |
2324 | ||
2325 | (define_insn "spe_divdf3" | |
2326 | [(set (match_operand:DF 0 "gpc_reg_operand" "=r") | |
2327 | (div:DF (match_operand:DF 1 "gpc_reg_operand" "r") | |
2328 | (match_operand:DF 2 "gpc_reg_operand" "r")))] | |
2329 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE" | |
2330 | "efddiv %0,%1,%2") | |
2331 | ||
a3170dc6 AH |
2332 | ;; Vector move instructions. |
2333 | ||
2334 | (define_expand "movv2si" | |
2335 | [(set (match_operand:V2SI 0 "nonimmediate_operand" "") | |
2336 | (match_operand:V2SI 1 "any_operand" ""))] | |
2337 | "TARGET_SPE" | |
2338 | "{ rs6000_emit_move (operands[0], operands[1], V2SImode); DONE; }") | |
2339 | ||
a3170dc6 | 2340 | (define_insn "*movv2si_internal" |
d744e06e AH |
2341 | [(set (match_operand:V2SI 0 "nonimmediate_operand" "=m,r,r,r") |
2342 | (match_operand:V2SI 1 "input_operand" "r,m,r,W"))] | |
e66b2fcf AH |
2343 | "TARGET_SPE |
2344 | && (gpc_reg_operand (operands[0], V2SImode) | |
2345 | || gpc_reg_operand (operands[1], V2SImode))" | |
d744e06e AH |
2346 | "* |
2347 | { | |
2348 | switch (which_alternative) | |
2349 | { | |
2350 | case 0: return \"evstdd%X0 %1,%y0\"; | |
2351 | case 1: return \"evldd%X1 %0,%y1\"; | |
2352 | case 2: return \"evor %0,%1,%1\"; | |
2353 | case 3: return output_vec_const_move (operands); | |
37409796 | 2354 | default: gcc_unreachable (); |
d744e06e AH |
2355 | } |
2356 | }" | |
2357 | [(set_attr "type" "vecload,vecstore,*,*") | |
2358 | (set_attr "length" "*,*,*,12")]) | |
2359 | ||
2360 | (define_split | |
2361 | [(set (match_operand:V2SI 0 "register_operand" "") | |
2362 | (match_operand:V2SI 1 "zero_constant" ""))] | |
2363 | "TARGET_SPE && reload_completed" | |
2364 | [(set (match_dup 0) | |
2365 | (xor:V2SI (match_dup 0) (match_dup 0)))] | |
2366 | "") | |
a3170dc6 | 2367 | |
00a892b8 NC |
2368 | (define_expand "movv1di" |
2369 | [(set (match_operand:V1DI 0 "nonimmediate_operand" "") | |
2370 | (match_operand:V1DI 1 "any_operand" ""))] | |
2371 | "TARGET_SPE" | |
2372 | "{ rs6000_emit_move (operands[0], operands[1], V1DImode); DONE; }") | |
2373 | ||
2374 | (define_insn "*movv1di_internal" | |
d744e06e AH |
2375 | [(set (match_operand:V1DI 0 "nonimmediate_operand" "=m,r,r,r") |
2376 | (match_operand:V1DI 1 "input_operand" "r,m,r,W"))] | |
e66b2fcf AH |
2377 | "TARGET_SPE |
2378 | && (gpc_reg_operand (operands[0], V1DImode) | |
2379 | || gpc_reg_operand (operands[1], V1DImode))" | |
00a892b8 NC |
2380 | "@ |
2381 | evstdd%X0 %1,%y0 | |
2382 | evldd%X1 %0,%y1 | |
d744e06e AH |
2383 | evor %0,%1,%1 |
2384 | evxor %0,%0,%0" | |
2385 | [(set_attr "type" "vecload,vecstore,*,*") | |
2386 | (set_attr "length" "*,*,*,*")]) | |
00a892b8 | 2387 | |
a3170dc6 AH |
2388 | (define_expand "movv4hi" |
2389 | [(set (match_operand:V4HI 0 "nonimmediate_operand" "") | |
2390 | (match_operand:V4HI 1 "any_operand" ""))] | |
2391 | "TARGET_SPE" | |
2392 | "{ rs6000_emit_move (operands[0], operands[1], V4HImode); DONE; }") | |
2393 | ||
2394 | (define_insn "*movv4hi_internal" | |
b9bb3235 JM |
2395 | [(set (match_operand:V4HI 0 "nonimmediate_operand" "=m,r,r,r") |
2396 | (match_operand:V4HI 1 "input_operand" "r,m,r,W"))] | |
e66b2fcf AH |
2397 | "TARGET_SPE |
2398 | && (gpc_reg_operand (operands[0], V4HImode) | |
2399 | || gpc_reg_operand (operands[1], V4HImode))" | |
a3170dc6 AH |
2400 | "@ |
2401 | evstdd%X0 %1,%y0 | |
2402 | evldd%X1 %0,%y1 | |
b9bb3235 JM |
2403 | evor %0,%1,%1 |
2404 | evxor %0,%0,%0" | |
d744e06e | 2405 | [(set_attr "type" "vecload")]) |
a3170dc6 AH |
2406 | |
2407 | (define_expand "movv2sf" | |
2408 | [(set (match_operand:V2SF 0 "nonimmediate_operand" "") | |
2409 | (match_operand:V2SF 1 "any_operand" ""))] | |
2410 | "TARGET_SPE" | |
2411 | "{ rs6000_emit_move (operands[0], operands[1], V2SFmode); DONE; }") | |
2412 | ||
2413 | (define_insn "*movv2sf_internal" | |
d744e06e AH |
2414 | [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,r,r,r") |
2415 | (match_operand:V2SF 1 "input_operand" "r,m,r,W"))] | |
e66b2fcf AH |
2416 | "TARGET_SPE |
2417 | && (gpc_reg_operand (operands[0], V2SFmode) | |
2418 | || gpc_reg_operand (operands[1], V2SFmode))" | |
a3170dc6 AH |
2419 | "@ |
2420 | evstdd%X0 %1,%y0 | |
2421 | evldd%X1 %0,%y1 | |
d744e06e AH |
2422 | evor %0,%1,%1 |
2423 | evxor %0,%0,%0" | |
2424 | [(set_attr "type" "vecload,vecstore,*,*") | |
2425 | (set_attr "length" "*,*,*,*")]) | |
a3170dc6 | 2426 | |
e66b2fcf AH |
2427 | ;; End of vector move instructions. |
2428 | ||
a3170dc6 AH |
2429 | (define_insn "spe_evmwhssfaa" |
2430 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2431 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2432 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 702)) | |
2433 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 2434 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
2435 | "TARGET_SPE" |
2436 | "evmwhssfaa %0,%1,%2" | |
2437 | [(set_attr "type" "veccomplex") | |
2438 | (set_attr "length" "4")]) | |
2439 | ||
2440 | (define_insn "spe_evmwhssmaa" | |
2441 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2442 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2443 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 703)) | |
2444 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 2445 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
2446 | "TARGET_SPE" |
2447 | "evmwhssmaa %0,%1,%2" | |
2448 | [(set_attr "type" "veccomplex") | |
2449 | (set_attr "length" "4")]) | |
2450 | ||
2451 | (define_insn "spe_evmwhsmfaa" | |
2452 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2453 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2454 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 704)) | |
54da776f | 2455 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
2456 | "TARGET_SPE" |
2457 | "evmwhsmfaa %0,%1,%2" | |
2458 | [(set_attr "type" "veccomplex") | |
2459 | (set_attr "length" "4")]) | |
2460 | ||
2461 | (define_insn "spe_evmwhsmiaa" | |
2462 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2463 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2464 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 705)) | |
54da776f | 2465 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
2466 | "TARGET_SPE" |
2467 | "evmwhsmiaa %0,%1,%2" | |
2468 | [(set_attr "type" "veccomplex") | |
2469 | (set_attr "length" "4")]) | |
2470 | ||
2471 | (define_insn "spe_evmwhusiaa" | |
2472 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2473 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2474 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 706)) | |
2475 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 2476 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
2477 | "TARGET_SPE" |
2478 | "evmwhusiaa %0,%1,%2" | |
2479 | [(set_attr "type" "veccomplex") | |
2480 | (set_attr "length" "4")]) | |
2481 | ||
2482 | (define_insn "spe_evmwhumiaa" | |
2483 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2484 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2485 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 707)) | |
54da776f | 2486 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
2487 | "TARGET_SPE" |
2488 | "evmwhumiaa %0,%1,%2" | |
2489 | [(set_attr "type" "veccomplex") | |
2490 | (set_attr "length" "4")]) | |
2491 | ||
2492 | (define_insn "spe_evmwhssfan" | |
2493 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2494 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2495 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 708)) | |
2496 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 2497 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
2498 | "TARGET_SPE" |
2499 | "evmwhssfan %0,%1,%2" | |
2500 | [(set_attr "type" "veccomplex") | |
2501 | (set_attr "length" "4")]) | |
2502 | ||
2503 | (define_insn "spe_evmwhssian" | |
2504 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2505 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2506 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 709)) | |
2507 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 2508 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
2509 | "TARGET_SPE" |
2510 | "evmwhssian %0,%1,%2" | |
2511 | [(set_attr "type" "veccomplex") | |
2512 | (set_attr "length" "4")]) | |
2513 | ||
2514 | (define_insn "spe_evmwhsmfan" | |
2515 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2516 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2517 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 710)) | |
54da776f | 2518 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
2519 | "TARGET_SPE" |
2520 | "evmwhsmfan %0,%1,%2" | |
2521 | [(set_attr "type" "veccomplex") | |
2522 | (set_attr "length" "4")]) | |
2523 | ||
2524 | (define_insn "spe_evmwhsmian" | |
2525 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2526 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2527 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 711)) | |
54da776f | 2528 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
2529 | "TARGET_SPE" |
2530 | "evmwhsmian %0,%1,%2" | |
2531 | [(set_attr "type" "veccomplex") | |
2532 | (set_attr "length" "4")]) | |
2533 | ||
2534 | (define_insn "spe_evmwhumian" | |
2535 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2536 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2537 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 713)) | |
54da776f | 2538 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
2539 | "TARGET_SPE" |
2540 | "evmwhumian %0,%1,%2" | |
2541 | [(set_attr "type" "veccomplex") | |
2542 | (set_attr "length" "4")]) | |
2543 | ||
2544 | (define_insn "spe_evmwhgssfaa" | |
2545 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2546 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2547 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 714)) | |
2548 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 2549 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
2550 | "TARGET_SPE" |
2551 | "evmwhgssfaa %0,%1,%2" | |
2552 | [(set_attr "type" "veccomplex") | |
2553 | (set_attr "length" "4")]) | |
2554 | ||
2555 | (define_insn "spe_evmwhgsmfaa" | |
2556 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2557 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2558 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 715)) | |
54da776f | 2559 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
2560 | "TARGET_SPE" |
2561 | "evmwhgsmfaa %0,%1,%2" | |
2562 | [(set_attr "type" "veccomplex") | |
2563 | (set_attr "length" "4")]) | |
2564 | ||
2565 | (define_insn "spe_evmwhgsmiaa" | |
2566 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2567 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2568 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 716)) | |
54da776f | 2569 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
2570 | "TARGET_SPE" |
2571 | "evmwhgsmiaa %0,%1,%2" | |
2572 | [(set_attr "type" "veccomplex") | |
2573 | (set_attr "length" "4")]) | |
2574 | ||
2575 | (define_insn "spe_evmwhgumiaa" | |
2576 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2577 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2578 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 717)) | |
54da776f | 2579 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
2580 | "TARGET_SPE" |
2581 | "evmwhgumiaa %0,%1,%2" | |
2582 | [(set_attr "type" "veccomplex") | |
2583 | (set_attr "length" "4")]) | |
2584 | ||
2585 | (define_insn "spe_evmwhgssfan" | |
2586 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2587 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2588 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 718)) | |
2589 | (clobber (reg:SI SPEFSCR_REGNO)) | |
54da776f | 2590 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
2591 | "TARGET_SPE" |
2592 | "evmwhgssfan %0,%1,%2" | |
2593 | [(set_attr "type" "veccomplex") | |
2594 | (set_attr "length" "4")]) | |
2595 | ||
2596 | (define_insn "spe_evmwhgsmfan" | |
2597 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2598 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2599 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 719)) | |
54da776f | 2600 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
2601 | "TARGET_SPE" |
2602 | "evmwhgsmfan %0,%1,%2" | |
2603 | [(set_attr "type" "veccomplex") | |
2604 | (set_attr "length" "4")]) | |
2605 | ||
2606 | (define_insn "spe_evmwhgsmian" | |
2607 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2608 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2609 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 720)) | |
54da776f | 2610 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
2611 | "TARGET_SPE" |
2612 | "evmwhgsmian %0,%1,%2" | |
2613 | [(set_attr "type" "veccomplex") | |
2614 | (set_attr "length" "4")]) | |
2615 | ||
2616 | (define_insn "spe_evmwhgumian" | |
2617 | [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") | |
2618 | (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") | |
2619 | (match_operand:V2SI 2 "gpc_reg_operand" "r")] 721)) | |
54da776f | 2620 | (set (reg:V2SI SPE_ACC_REGNO) (unspec:V2SI [(const_int 0)] 0))] |
a3170dc6 AH |
2621 | "TARGET_SPE" |
2622 | "evmwhgumian %0,%1,%2" | |
2623 | [(set_attr "type" "veccomplex") | |
2624 | (set_attr "length" "4")]) | |
2625 | ||
2626 | (define_insn "spe_mtspefscr" | |
2627 | [(set (reg:SI SPEFSCR_REGNO) | |
2628 | (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] | |
2629 | 722))] | |
2630 | "TARGET_SPE" | |
2631 | "mtspefscr %0" | |
2632 | [(set_attr "type" "vecsimple")]) | |
2633 | ||
2634 | (define_insn "spe_mfspefscr" | |
2635 | [(set (match_operand:SI 0 "register_operand" "=r") | |
2636 | (unspec_volatile:SI [(reg:SI SPEFSCR_REGNO)] 723))] | |
2637 | "TARGET_SPE" | |
2638 | "mfspefscr %0" | |
2639 | [(set_attr "type" "vecsimple")]) | |
2640 | ||
423c1189 AH |
2641 | ;; FP comparison stuff. |
2642 | ||
423c1189 | 2643 | ;; Flip the GT bit. |
64022b5d | 2644 | (define_insn "e500_flip_gt_bit" |
423c1189 AH |
2645 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") |
2646 | (unspec:CCFP | |
2647 | [(match_operand:CCFP 1 "cc_reg_operand" "y")] 999))] | |
2648 | "!TARGET_FPRS && TARGET_HARD_FLOAT" | |
2649 | "* | |
2650 | { | |
64022b5d | 2651 | return output_e500_flip_gt_bit (operands[0], operands[1]); |
423c1189 AH |
2652 | }" |
2653 | [(set_attr "type" "cr_logical")]) | |
2654 | ||
a3170dc6 AH |
2655 | ;; MPC8540 single-precision FP instructions on GPRs. |
2656 | ;; We have 2 variants for each. One for IEEE compliant math and one | |
2657 | ;; for non IEEE compliant math. | |
2658 | ||
2659 | (define_insn "cmpsfeq_gpr" | |
2660 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
423c1189 AH |
2661 | (unspec:CCFP |
2662 | [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") | |
2663 | (match_operand:SF 2 "gpc_reg_operand" "r"))] | |
2664 | 1000))] | |
a3170dc6 AH |
2665 | "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations" |
2666 | "efscmpeq %0,%1,%2" | |
5e8006fa | 2667 | [(set_attr "type" "veccmp")]) |
a3170dc6 AH |
2668 | |
2669 | (define_insn "tstsfeq_gpr" | |
2670 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
423c1189 AH |
2671 | (unspec:CCFP |
2672 | [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") | |
2673 | (match_operand:SF 2 "gpc_reg_operand" "r"))] | |
2674 | 1001))] | |
a3170dc6 AH |
2675 | "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations" |
2676 | "efststeq %0,%1,%2" | |
5e8006fa | 2677 | [(set_attr "type" "veccmpsimple")]) |
a3170dc6 AH |
2678 | |
2679 | (define_insn "cmpsfgt_gpr" | |
2680 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
423c1189 AH |
2681 | (unspec:CCFP |
2682 | [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") | |
2683 | (match_operand:SF 2 "gpc_reg_operand" "r"))] | |
2684 | 1002))] | |
a3170dc6 AH |
2685 | "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations" |
2686 | "efscmpgt %0,%1,%2" | |
5e8006fa | 2687 | [(set_attr "type" "veccmp")]) |
a3170dc6 AH |
2688 | |
2689 | (define_insn "tstsfgt_gpr" | |
2690 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
423c1189 AH |
2691 | (unspec:CCFP |
2692 | [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") | |
2693 | (match_operand:SF 2 "gpc_reg_operand" "r"))] | |
2694 | 1003))] | |
a3170dc6 AH |
2695 | "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations" |
2696 | "efststgt %0,%1,%2" | |
5e8006fa | 2697 | [(set_attr "type" "veccmpsimple")]) |
a3170dc6 AH |
2698 | |
2699 | (define_insn "cmpsflt_gpr" | |
2700 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
423c1189 AH |
2701 | (unspec:CCFP |
2702 | [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") | |
2703 | (match_operand:SF 2 "gpc_reg_operand" "r"))] | |
2704 | 1004))] | |
a3170dc6 AH |
2705 | "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations" |
2706 | "efscmplt %0,%1,%2" | |
5e8006fa | 2707 | [(set_attr "type" "veccmp")]) |
a3170dc6 AH |
2708 | |
2709 | (define_insn "tstsflt_gpr" | |
2710 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
423c1189 AH |
2711 | (unspec:CCFP |
2712 | [(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") | |
2713 | (match_operand:SF 2 "gpc_reg_operand" "r"))] | |
f350ff00 | 2714 | 1005))] |
a3170dc6 AH |
2715 | "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations" |
2716 | "efststlt %0,%1,%2" | |
5e8006fa | 2717 | [(set_attr "type" "veccmpsimple")]) |
4d4cbc0e AH |
2718 | |
2719 | ;; Same thing, but for double-precision. | |
2720 | ||
2721 | (define_insn "cmpdfeq_gpr" | |
2722 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
2723 | (unspec:CCFP | |
2724 | [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") | |
2725 | (match_operand:DF 2 "gpc_reg_operand" "r"))] | |
2726 | CMPDFEQ_GPR))] | |
2727 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations" | |
2728 | "efdcmpeq %0,%1,%2" | |
2729 | [(set_attr "type" "veccmp")]) | |
2730 | ||
2731 | (define_insn "tstdfeq_gpr" | |
2732 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
2733 | (unspec:CCFP | |
2734 | [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") | |
2735 | (match_operand:DF 2 "gpc_reg_operand" "r"))] | |
2736 | TSTDFEQ_GPR))] | |
2737 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations" | |
2738 | "efdtsteq %0,%1,%2" | |
2739 | [(set_attr "type" "veccmpsimple")]) | |
2740 | ||
2741 | (define_insn "cmpdfgt_gpr" | |
2742 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
2743 | (unspec:CCFP | |
2744 | [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") | |
2745 | (match_operand:DF 2 "gpc_reg_operand" "r"))] | |
2746 | CMPDFGT_GPR))] | |
2747 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations" | |
2748 | "efdcmpgt %0,%1,%2" | |
2749 | [(set_attr "type" "veccmp")]) | |
2750 | ||
2751 | (define_insn "tstdfgt_gpr" | |
2752 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
2753 | (unspec:CCFP | |
2754 | [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") | |
2755 | (match_operand:DF 2 "gpc_reg_operand" "r"))] | |
2756 | TSTDFGT_GPR))] | |
2757 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations" | |
2758 | "efdtstgt %0,%1,%2" | |
2759 | [(set_attr "type" "veccmpsimple")]) | |
2760 | ||
2761 | (define_insn "cmpdflt_gpr" | |
2762 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
2763 | (unspec:CCFP | |
2764 | [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") | |
2765 | (match_operand:DF 2 "gpc_reg_operand" "r"))] | |
2766 | CMPDFLT_GPR))] | |
2767 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && !flag_unsafe_math_optimizations" | |
2768 | "efdcmplt %0,%1,%2" | |
2769 | [(set_attr "type" "veccmp")]) | |
2770 | ||
2771 | (define_insn "tstdflt_gpr" | |
2772 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
2773 | (unspec:CCFP | |
2774 | [(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "r") | |
2775 | (match_operand:DF 2 "gpc_reg_operand" "r"))] | |
2776 | TSTDFLT_GPR))] | |
2777 | "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE && flag_unsafe_math_optimizations" | |
2778 | "efdtstlt %0,%1,%2" | |
2779 | [(set_attr "type" "veccmpsimple")]) | |
64022b5d AH |
2780 | |
2781 | ;; Like cceq_ior_compare, but compare the GT bits. | |
2782 | (define_insn "e500_cr_ior_compare" | |
2783 | [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") | |
2784 | (unspec:CCFP [(match_operand 1 "cc_reg_operand" "y") | |
2785 | (match_operand 2 "cc_reg_operand" "y")] | |
2786 | E500_CR_IOR_COMPARE))] | |
2787 | "TARGET_E500" | |
2788 | "cror 4*%0+gt,4*%1+gt,4*%2+gt" | |
2789 | [(set_attr "type" "cr_logical")]) |