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24833e1a 1/* Subroutines used for code generation on Renesas RX processors.
fbd26352 2 Copyright (C) 2008-2019 Free Software Foundation, Inc.
24833e1a 3 Contributed by Red Hat.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21/* To Do:
22
23 * Re-enable memory-to-memory copies and fix up reload. */
24
785790dc 25#define IN_TARGET_CODE 1
26
24833e1a 27#include "config.h"
28#include "system.h"
29#include "coretypes.h"
9ef16211 30#include "backend.h"
c1eb80de 31#include "target.h"
9ef16211 32#include "rtl.h"
c1eb80de 33#include "tree.h"
30a86690 34#include "stringpool.h"
35#include "attribs.h"
c1eb80de 36#include "cfghooks.h"
9ef16211 37#include "df.h"
ad7b10a2 38#include "memmodel.h"
c1eb80de 39#include "tm_p.h"
40#include "regs.h"
41#include "emit-rtl.h"
42#include "diagnostic-core.h"
9ed99284 43#include "varasm.h"
44#include "stor-layout.h"
45#include "calls.h"
24833e1a 46#include "output.h"
24833e1a 47#include "flags.h"
d53441c8 48#include "explow.h"
24833e1a 49#include "expr.h"
24833e1a 50#include "toplev.h"
24833e1a 51#include "langhooks.h"
fba5dd52 52#include "opts.h"
f7715905 53#include "builtins.h"
6e507301 54
0c71fb4f 55/* This file should be included last. */
4b498588 56#include "target-def.h"
57
6e507301 58static unsigned int rx_gp_base_regnum_val = INVALID_REGNUM;
59static unsigned int rx_pid_base_regnum_val = INVALID_REGNUM;
60static unsigned int rx_num_interrupt_regs;
24833e1a 61\f
6e507301 62static unsigned int
63rx_gp_base_regnum (void)
64{
65 if (rx_gp_base_regnum_val == INVALID_REGNUM)
66 gcc_unreachable ();
67 return rx_gp_base_regnum_val;
68}
69
70static unsigned int
71rx_pid_base_regnum (void)
72{
73 if (rx_pid_base_regnum_val == INVALID_REGNUM)
74 gcc_unreachable ();
75 return rx_pid_base_regnum_val;
76}
77
78/* Find a SYMBOL_REF in a "standard" MEM address and return its decl. */
79
80static tree
81rx_decl_for_addr (rtx op)
82{
83 if (GET_CODE (op) == MEM)
84 op = XEXP (op, 0);
85 if (GET_CODE (op) == CONST)
86 op = XEXP (op, 0);
87 while (GET_CODE (op) == PLUS)
88 op = XEXP (op, 0);
89 if (GET_CODE (op) == SYMBOL_REF)
90 return SYMBOL_REF_DECL (op);
91 return NULL_TREE;
92}
93
6bb30542 94static void rx_print_operand (FILE *, rtx, int);
95
ccfccd66 96#define CC_FLAG_S (1 << 0)
97#define CC_FLAG_Z (1 << 1)
98#define CC_FLAG_O (1 << 2)
99#define CC_FLAG_C (1 << 3)
f7fcec1a 100#define CC_FLAG_FP (1 << 4) /* Fake, to differentiate CC_Fmode. */
ccfccd66 101
3754d046 102static unsigned int flags_from_mode (machine_mode mode);
ccfccd66 103static unsigned int flags_from_code (enum rtx_code code);
67e66e16 104\f
6e507301 105/* Return true if OP is a reference to an object in a PID data area. */
106
107enum pid_type
108{
109 PID_NOT_PID = 0, /* The object is not in the PID data area. */
110 PID_ENCODED, /* The object is in the PID data area. */
111 PID_UNENCODED /* The object will be placed in the PID data area, but it has not been placed there yet. */
112};
113
114static enum pid_type
115rx_pid_data_operand (rtx op)
116{
117 tree op_decl;
118
119 if (!TARGET_PID)
120 return PID_NOT_PID;
121
122 if (GET_CODE (op) == PLUS
123 && GET_CODE (XEXP (op, 0)) == REG
124 && GET_CODE (XEXP (op, 1)) == CONST
125 && GET_CODE (XEXP (XEXP (op, 1), 0)) == UNSPEC)
126 return PID_ENCODED;
127
128 op_decl = rx_decl_for_addr (op);
129
130 if (op_decl)
131 {
132 if (TREE_READONLY (op_decl))
133 return PID_UNENCODED;
134 }
135 else
136 {
137 /* Sigh, some special cases. */
138 if (GET_CODE (op) == SYMBOL_REF
139 || GET_CODE (op) == LABEL_REF)
140 return PID_UNENCODED;
141 }
142
143 return PID_NOT_PID;
144}
145
146static rtx
147rx_legitimize_address (rtx x,
148 rtx oldx ATTRIBUTE_UNUSED,
3754d046 149 machine_mode mode ATTRIBUTE_UNUSED)
6e507301 150{
151 if (rx_pid_data_operand (x) == PID_UNENCODED)
152 {
153 rtx rv = gen_pid_addr (gen_rtx_REG (SImode, rx_pid_base_regnum ()), x);
154 return rv;
155 }
156
157 if (GET_CODE (x) == PLUS
158 && GET_CODE (XEXP (x, 0)) == PLUS
159 && REG_P (XEXP (XEXP (x, 0), 0))
160 && REG_P (XEXP (x, 1)))
161 return force_reg (SImode, x);
162
163 return x;
164}
165
24833e1a 166/* Return true if OP is a reference to an object in a small data area. */
167
168static bool
169rx_small_data_operand (rtx op)
170{
171 if (rx_small_data_limit == 0)
172 return false;
173
174 if (GET_CODE (op) == SYMBOL_REF)
175 return SYMBOL_REF_SMALL_P (op);
176
177 return false;
178}
179
180static bool
3754d046 181rx_is_legitimate_address (machine_mode mode, rtx x,
4bccad5e 182 bool strict ATTRIBUTE_UNUSED)
24833e1a 183{
184 if (RTX_OK_FOR_BASE (x, strict))
185 /* Register Indirect. */
186 return true;
187
f7fcec1a 188 if ((GET_MODE_SIZE (mode) == 4
189 || GET_MODE_SIZE (mode) == 2
190 || GET_MODE_SIZE (mode) == 1)
24833e1a 191 && (GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC))
192 /* Pre-decrement Register Indirect or
193 Post-increment Register Indirect. */
194 return RTX_OK_FOR_BASE (XEXP (x, 0), strict);
195
6e507301 196 switch (rx_pid_data_operand (x))
197 {
198 case PID_UNENCODED:
199 return false;
200 case PID_ENCODED:
201 return true;
202 default:
203 break;
204 }
205
24833e1a 206 if (GET_CODE (x) == PLUS)
207 {
208 rtx arg1 = XEXP (x, 0);
209 rtx arg2 = XEXP (x, 1);
210 rtx index = NULL_RTX;
211
212 if (REG_P (arg1) && RTX_OK_FOR_BASE (arg1, strict))
213 index = arg2;
214 else if (REG_P (arg2) && RTX_OK_FOR_BASE (arg2, strict))
215 index = arg1;
216 else
217 return false;
218
219 switch (GET_CODE (index))
220 {
221 case CONST_INT:
222 {
223 /* Register Relative: REG + INT.
224 Only positive, mode-aligned, mode-sized
225 displacements are allowed. */
226 HOST_WIDE_INT val = INTVAL (index);
227 int factor;
228
229 if (val < 0)
230 return false;
776f1390 231
24833e1a 232 switch (GET_MODE_SIZE (mode))
233 {
234 default:
235 case 4: factor = 4; break;
236 case 2: factor = 2; break;
237 case 1: factor = 1; break;
238 }
239
f7fcec1a 240 if (val > (65535 * factor))
24833e1a 241 return false;
242 return (val % factor) == 0;
243 }
244
245 case REG:
246 /* Unscaled Indexed Register Indirect: REG + REG
247 Size has to be "QI", REG has to be valid. */
248 return GET_MODE_SIZE (mode) == 1 && RTX_OK_FOR_BASE (index, strict);
249
250 case MULT:
251 {
252 /* Scaled Indexed Register Indirect: REG + (REG * FACTOR)
253 Factor has to equal the mode size, REG has to be valid. */
254 rtx factor;
255
256 factor = XEXP (index, 1);
257 index = XEXP (index, 0);
258
259 return REG_P (index)
260 && RTX_OK_FOR_BASE (index, strict)
261 && CONST_INT_P (factor)
262 && GET_MODE_SIZE (mode) == INTVAL (factor);
263 }
264
265 default:
266 return false;
267 }
268 }
269
270 /* Small data area accesses turn into register relative offsets. */
271 return rx_small_data_operand (x);
272}
273
2fbe7a32 274/* Returns TRUE for simple memory addresses, ie ones
24833e1a 275 that do not involve register indirect addressing
276 or pre/post increment/decrement. */
277
278bool
3754d046 279rx_is_restricted_memory_address (rtx mem, machine_mode mode)
24833e1a 280{
24833e1a 281 if (! rx_is_legitimate_address
282 (mode, mem, reload_in_progress || reload_completed))
283 return false;
284
285 switch (GET_CODE (mem))
286 {
287 case REG:
288 /* Simple memory addresses are OK. */
289 return true;
290
14e1e40d 291 case SUBREG:
292 return RX_REG_P (SUBREG_REG (mem));
293
24833e1a 294 case PRE_DEC:
295 case POST_INC:
296 return false;
297
298 case PLUS:
776f1390 299 {
300 rtx base, index;
301
302 /* Only allow REG+INT addressing. */
303 base = XEXP (mem, 0);
304 index = XEXP (mem, 1);
24833e1a 305
776f1390 306 if (! RX_REG_P (base) || ! CONST_INT_P (index))
307 return false;
308
309 return IN_RANGE (INTVAL (index), 0, (0x10000 * GET_MODE_SIZE (mode)) - 1);
310 }
24833e1a 311
312 case SYMBOL_REF:
313 /* Can happen when small data is being supported.
314 Assume that it will be resolved into GP+INT. */
315 return true;
316
317 default:
318 gcc_unreachable ();
319 }
320}
321
5afe50d9 322/* Implement TARGET_MODE_DEPENDENT_ADDRESS_P. */
323
324static bool
4e27ffd0 325rx_mode_dependent_address_p (const_rtx addr, addr_space_t as ATTRIBUTE_UNUSED)
24833e1a 326{
327 if (GET_CODE (addr) == CONST)
328 addr = XEXP (addr, 0);
329
330 switch (GET_CODE (addr))
331 {
332 /* --REG and REG++ only work in SImode. */
333 case PRE_DEC:
334 case POST_INC:
335 return true;
336
337 case MINUS:
338 case PLUS:
339 if (! REG_P (XEXP (addr, 0)))
340 return true;
341
342 addr = XEXP (addr, 1);
343
344 switch (GET_CODE (addr))
345 {
346 case REG:
347 /* REG+REG only works in SImode. */
348 return true;
349
350 case CONST_INT:
351 /* REG+INT is only mode independent if INT is a
b546cdca 352 multiple of 4, positive and will fit into 16-bits. */
24833e1a 353 if (((INTVAL (addr) & 3) == 0)
b546cdca 354 && IN_RANGE (INTVAL (addr), 4, 0xfffc))
24833e1a 355 return false;
356 return true;
357
358 case SYMBOL_REF:
359 case LABEL_REF:
360 return true;
361
362 case MULT:
24833e1a 363 /* REG+REG*SCALE is always mode dependent. */
364 return true;
365
366 default:
367 /* Not recognized, so treat as mode dependent. */
368 return true;
369 }
370
371 case CONST_INT:
372 case SYMBOL_REF:
373 case LABEL_REF:
374 case REG:
375 /* These are all mode independent. */
376 return false;
377
378 default:
379 /* Everything else is unrecognized,
380 so treat as mode dependent. */
381 return true;
382 }
383}
384\f
24833e1a 385/* A C compound statement to output to stdio stream FILE the
386 assembler syntax for an instruction operand that is a memory
387 reference whose address is ADDR. */
388
6bb30542 389static void
3c047fe9 390rx_print_operand_address (FILE * file, machine_mode /*mode*/, rtx addr)
24833e1a 391{
392 switch (GET_CODE (addr))
393 {
394 case REG:
395 fprintf (file, "[");
396 rx_print_operand (file, addr, 0);
397 fprintf (file, "]");
398 break;
399
400 case PRE_DEC:
401 fprintf (file, "[-");
402 rx_print_operand (file, XEXP (addr, 0), 0);
403 fprintf (file, "]");
404 break;
405
406 case POST_INC:
407 fprintf (file, "[");
408 rx_print_operand (file, XEXP (addr, 0), 0);
409 fprintf (file, "+]");
410 break;
411
412 case PLUS:
413 {
414 rtx arg1 = XEXP (addr, 0);
415 rtx arg2 = XEXP (addr, 1);
416 rtx base, index;
417
418 if (REG_P (arg1) && RTX_OK_FOR_BASE (arg1, true))
419 base = arg1, index = arg2;
420 else if (REG_P (arg2) && RTX_OK_FOR_BASE (arg2, true))
421 base = arg2, index = arg1;
422 else
423 {
424 rx_print_operand (file, arg1, 0);
425 fprintf (file, " + ");
426 rx_print_operand (file, arg2, 0);
427 break;
428 }
429
430 if (REG_P (index) || GET_CODE (index) == MULT)
431 {
432 fprintf (file, "[");
433 rx_print_operand (file, index, 'A');
434 fprintf (file, ",");
435 }
436 else /* GET_CODE (index) == CONST_INT */
437 {
438 rx_print_operand (file, index, 'A');
439 fprintf (file, "[");
440 }
441 rx_print_operand (file, base, 0);
442 fprintf (file, "]");
443 break;
444 }
445
95272799 446 case CONST:
447 if (GET_CODE (XEXP (addr, 0)) == UNSPEC)
448 {
449 addr = XEXP (addr, 0);
450 gcc_assert (XINT (addr, 1) == UNSPEC_CONST);
6e507301 451
6e507301 452 addr = XVECEXP (addr, 0, 0);
95272799 453 gcc_assert (CONST_INT_P (addr));
942ca701 454 fprintf (file, "#");
455 output_addr_const (file, addr);
456 break;
95272799 457 }
942ca701 458 fprintf (file, "#");
459 output_addr_const (file, XEXP (addr, 0));
460 break;
461
462 case UNSPEC:
463 addr = XVECEXP (addr, 0, 0);
95272799 464 /* Fall through. */
24833e1a 465 case LABEL_REF:
466 case SYMBOL_REF:
24833e1a 467 fprintf (file, "#");
6e507301 468 /* Fall through. */
24833e1a 469 default:
470 output_addr_const (file, addr);
471 break;
472 }
473}
474
475static void
476rx_print_integer (FILE * file, HOST_WIDE_INT val)
477{
94340817 478 if (val < 64)
24833e1a 479 fprintf (file, HOST_WIDE_INT_PRINT_DEC, val);
480 else
481 fprintf (file,
482 TARGET_AS100_SYNTAX
483 ? "0%" HOST_WIDE_INT_PRINT "xH" : HOST_WIDE_INT_PRINT_HEX,
484 val);
485}
486
487static bool
488rx_assemble_integer (rtx x, unsigned int size, int is_aligned)
489{
490 const char * op = integer_asm_op (size, is_aligned);
491
492 if (! CONST_INT_P (x))
493 return default_assemble_integer (x, size, is_aligned);
494
495 if (op == NULL)
496 return false;
497 fputs (op, asm_out_file);
498
499 rx_print_integer (asm_out_file, INTVAL (x));
500 fputc ('\n', asm_out_file);
501 return true;
502}
503
504
24833e1a 505/* Handles the insertion of a single operand into the assembler output.
506 The %<letter> directives supported are:
507
508 %A Print an operand without a leading # character.
509 %B Print an integer comparison name.
510 %C Print a control register name.
511 %F Print a condition code flag name.
6e507301 512 %G Register used for small-data-area addressing
24833e1a 513 %H Print high part of a DImode register, integer or address.
514 %L Print low part of a DImode register, integer or address.
6bb30542 515 %N Print the negation of the immediate value.
6e507301 516 %P Register used for PID addressing
24833e1a 517 %Q If the operand is a MEM, then correctly generate
776f1390 518 register indirect or register relative addressing.
519 %R Like %Q but for zero-extending loads. */
24833e1a 520
6bb30542 521static void
24833e1a 522rx_print_operand (FILE * file, rtx op, int letter)
523{
776f1390 524 bool unsigned_load = false;
6e507301 525 bool print_hash = true;
526
527 if (letter == 'A'
528 && ((GET_CODE (op) == CONST
529 && GET_CODE (XEXP (op, 0)) == UNSPEC)
530 || GET_CODE (op) == UNSPEC))
531 {
532 print_hash = false;
533 letter = 0;
534 }
776f1390 535
24833e1a 536 switch (letter)
537 {
538 case 'A':
539 /* Print an operand without a leading #. */
540 if (MEM_P (op))
541 op = XEXP (op, 0);
542
543 switch (GET_CODE (op))
544 {
545 case LABEL_REF:
546 case SYMBOL_REF:
547 output_addr_const (file, op);
548 break;
549 case CONST_INT:
550 fprintf (file, "%ld", (long) INTVAL (op));
551 break;
552 default:
553 rx_print_operand (file, op, 0);
554 break;
555 }
556 break;
557
558 case 'B':
ccfccd66 559 {
560 enum rtx_code code = GET_CODE (op);
3754d046 561 machine_mode mode = GET_MODE (XEXP (op, 0));
ccfccd66 562 const char *ret;
563
564 if (mode == CC_Fmode)
565 {
566 /* C flag is undefined, and O flag carries unordered. None of the
567 branch combinations that include O use it helpfully. */
568 switch (code)
569 {
570 case ORDERED:
571 ret = "no";
572 break;
573 case UNORDERED:
574 ret = "o";
575 break;
576 case LT:
577 ret = "n";
578 break;
579 case GE:
580 ret = "pz";
581 break;
582 case EQ:
583 ret = "eq";
584 break;
585 case NE:
586 ret = "ne";
587 break;
588 default:
589 gcc_unreachable ();
590 }
591 }
592 else
593 {
24ad6c43 594 unsigned int flags = flags_from_mode (mode);
776f1390 595
ccfccd66 596 switch (code)
597 {
598 case LT:
24ad6c43 599 ret = (flags & CC_FLAG_O ? "lt" : "n");
ccfccd66 600 break;
601 case GE:
24ad6c43 602 ret = (flags & CC_FLAG_O ? "ge" : "pz");
ccfccd66 603 break;
604 case GT:
605 ret = "gt";
606 break;
607 case LE:
608 ret = "le";
609 break;
610 case GEU:
611 ret = "geu";
612 break;
613 case LTU:
614 ret = "ltu";
615 break;
616 case GTU:
617 ret = "gtu";
618 break;
619 case LEU:
620 ret = "leu";
621 break;
622 case EQ:
623 ret = "eq";
624 break;
625 case NE:
626 ret = "ne";
627 break;
628 default:
629 gcc_unreachable ();
630 }
24ad6c43 631 gcc_checking_assert ((flags_from_code (code) & ~flags) == 0);
ccfccd66 632 }
633 fputs (ret, file);
634 break;
635 }
24833e1a 636
637 case 'C':
638 gcc_assert (CONST_INT_P (op));
639 switch (INTVAL (op))
640 {
140a4ed4 641 case CTRLREG_PSW: fprintf (file, "psw"); break;
642 case CTRLREG_USP: fprintf (file, "usp"); break;
643 case CTRLREG_FPSW: fprintf (file, "fpsw"); break;
644 case CTRLREG_CPEN: fprintf (file, "cpen"); break;
645 case CTRLREG_BPSW: fprintf (file, "bpsw"); break;
646 case CTRLREG_BPC: fprintf (file, "bpc"); break;
647 case CTRLREG_ISP: fprintf (file, "isp"); break;
648 case CTRLREG_FINTV: fprintf (file, "fintv"); break;
649 case CTRLREG_INTB: fprintf (file, "intb"); break;
24833e1a 650 default:
98a5f45d 651 warning (0, "unrecognized control register number: %d - using 'psw'",
6bb30542 652 (int) INTVAL (op));
98cb9b5b 653 fprintf (file, "psw");
654 break;
24833e1a 655 }
656 break;
657
658 case 'F':
659 gcc_assert (CONST_INT_P (op));
660 switch (INTVAL (op))
661 {
662 case 0: case 'c': case 'C': fprintf (file, "C"); break;
663 case 1: case 'z': case 'Z': fprintf (file, "Z"); break;
664 case 2: case 's': case 'S': fprintf (file, "S"); break;
665 case 3: case 'o': case 'O': fprintf (file, "O"); break;
666 case 8: case 'i': case 'I': fprintf (file, "I"); break;
667 case 9: case 'u': case 'U': fprintf (file, "U"); break;
668 default:
669 gcc_unreachable ();
670 }
671 break;
672
6e507301 673 case 'G':
674 fprintf (file, "%s", reg_names [rx_gp_base_regnum ()]);
675 break;
676
24833e1a 677 case 'H':
6bb30542 678 switch (GET_CODE (op))
24833e1a 679 {
6bb30542 680 case REG:
681 fprintf (file, "%s", reg_names [REGNO (op) + (WORDS_BIG_ENDIAN ? 0 : 1)]);
682 break;
683 case CONST_INT:
684 {
685 HOST_WIDE_INT v = INTVAL (op);
67e66e16 686
6bb30542 687 fprintf (file, "#");
688 /* Trickery to avoid problems with shifting 32 bits at a time. */
689 v = v >> 16;
690 v = v >> 16;
691 rx_print_integer (file, v);
692 break;
693 }
694 case CONST_DOUBLE:
24833e1a 695 fprintf (file, "#");
6bb30542 696 rx_print_integer (file, CONST_DOUBLE_HIGH (op));
697 break;
698 case MEM:
24833e1a 699 if (! WORDS_BIG_ENDIAN)
700 op = adjust_address (op, SImode, 4);
3c047fe9 701 output_address (GET_MODE (op), XEXP (op, 0));
6bb30542 702 break;
703 default:
704 gcc_unreachable ();
24833e1a 705 }
706 break;
707
708 case 'L':
6bb30542 709 switch (GET_CODE (op))
24833e1a 710 {
6bb30542 711 case REG:
712 fprintf (file, "%s", reg_names [REGNO (op) + (WORDS_BIG_ENDIAN ? 1 : 0)]);
713 break;
714 case CONST_INT:
24833e1a 715 fprintf (file, "#");
716 rx_print_integer (file, INTVAL (op) & 0xffffffff);
6bb30542 717 break;
718 case CONST_DOUBLE:
719 fprintf (file, "#");
720 rx_print_integer (file, CONST_DOUBLE_LOW (op));
721 break;
722 case MEM:
24833e1a 723 if (WORDS_BIG_ENDIAN)
724 op = adjust_address (op, SImode, 4);
3c047fe9 725 output_address (GET_MODE (op), XEXP (op, 0));
6bb30542 726 break;
727 default:
728 gcc_unreachable ();
24833e1a 729 }
730 break;
731
39349585 732 case 'N':
733 gcc_assert (CONST_INT_P (op));
734 fprintf (file, "#");
735 rx_print_integer (file, - INTVAL (op));
736 break;
737
6e507301 738 case 'P':
739 fprintf (file, "%s", reg_names [rx_pid_base_regnum ()]);
740 break;
741
776f1390 742 case 'R':
5794450f 743 gcc_assert (GET_MODE_SIZE (GET_MODE (op)) <= 4);
776f1390 744 unsigned_load = true;
745 /* Fall through. */
24833e1a 746 case 'Q':
747 if (MEM_P (op))
748 {
749 HOST_WIDE_INT offset;
776f1390 750 rtx mem = op;
24833e1a 751
752 op = XEXP (op, 0);
753
754 if (REG_P (op))
755 offset = 0;
756 else if (GET_CODE (op) == PLUS)
757 {
758 rtx displacement;
759
760 if (REG_P (XEXP (op, 0)))
761 {
762 displacement = XEXP (op, 1);
763 op = XEXP (op, 0);
764 }
765 else
766 {
767 displacement = XEXP (op, 0);
768 op = XEXP (op, 1);
769 gcc_assert (REG_P (op));
770 }
771
772 gcc_assert (CONST_INT_P (displacement));
773 offset = INTVAL (displacement);
774 gcc_assert (offset >= 0);
775
776 fprintf (file, "%ld", offset);
777 }
778 else
779 gcc_unreachable ();
780
781 fprintf (file, "[");
782 rx_print_operand (file, op, 0);
783 fprintf (file, "].");
784
776f1390 785 switch (GET_MODE_SIZE (GET_MODE (mem)))
24833e1a 786 {
787 case 1:
776f1390 788 gcc_assert (offset <= 65535 * 1);
789 fprintf (file, unsigned_load ? "UB" : "B");
24833e1a 790 break;
791 case 2:
792 gcc_assert (offset % 2 == 0);
776f1390 793 gcc_assert (offset <= 65535 * 2);
794 fprintf (file, unsigned_load ? "UW" : "W");
24833e1a 795 break;
776f1390 796 case 4:
24833e1a 797 gcc_assert (offset % 4 == 0);
776f1390 798 gcc_assert (offset <= 65535 * 4);
24833e1a 799 fprintf (file, "L");
800 break;
776f1390 801 default:
802 gcc_unreachable ();
24833e1a 803 }
804 break;
805 }
806
807 /* Fall through. */
808
809 default:
6e507301 810 if (GET_CODE (op) == CONST
811 && GET_CODE (XEXP (op, 0)) == UNSPEC)
812 op = XEXP (op, 0);
813 else if (GET_CODE (op) == CONST
814 && GET_CODE (XEXP (op, 0)) == PLUS
815 && GET_CODE (XEXP (XEXP (op, 0), 0)) == UNSPEC
816 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
817 {
818 if (print_hash)
819 fprintf (file, "#");
820 fprintf (file, "(");
821 rx_print_operand (file, XEXP (XEXP (op, 0), 0), 'A');
822 fprintf (file, " + ");
823 output_addr_const (file, XEXP (XEXP (op, 0), 1));
824 fprintf (file, ")");
825 return;
826 }
827
24833e1a 828 switch (GET_CODE (op))
829 {
830 case MULT:
831 /* Should be the scaled part of an
832 indexed register indirect address. */
833 {
834 rtx base = XEXP (op, 0);
835 rtx index = XEXP (op, 1);
836
837 /* Check for a swaped index register and scaling factor.
838 Not sure if this can happen, but be prepared to handle it. */
839 if (CONST_INT_P (base) && REG_P (index))
840 {
841 rtx tmp = base;
842 base = index;
843 index = tmp;
844 }
845
846 gcc_assert (REG_P (base));
847 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
848 gcc_assert (CONST_INT_P (index));
849 /* Do not try to verify the value of the scalar as it is based
850 on the mode of the MEM not the mode of the MULT. (Which
851 will always be SImode). */
852 fprintf (file, "%s", reg_names [REGNO (base)]);
853 break;
854 }
855
856 case MEM:
3c047fe9 857 output_address (GET_MODE (op), XEXP (op, 0));
24833e1a 858 break;
859
860 case PLUS:
3c047fe9 861 output_address (VOIDmode, op);
24833e1a 862 break;
863
864 case REG:
865 gcc_assert (REGNO (op) < FIRST_PSEUDO_REGISTER);
866 fprintf (file, "%s", reg_names [REGNO (op)]);
867 break;
868
869 case SUBREG:
870 gcc_assert (subreg_regno (op) < FIRST_PSEUDO_REGISTER);
871 fprintf (file, "%s", reg_names [subreg_regno (op)]);
872 break;
873
874 /* This will only be single precision.... */
875 case CONST_DOUBLE:
876 {
877 unsigned long val;
24833e1a 878
945f7b03 879 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), val);
6e507301 880 if (print_hash)
881 fprintf (file, "#");
882 fprintf (file, TARGET_AS100_SYNTAX ? "0%lxH" : "0x%lx", val);
24833e1a 883 break;
884 }
885
886 case CONST_INT:
6e507301 887 if (print_hash)
888 fprintf (file, "#");
24833e1a 889 rx_print_integer (file, INTVAL (op));
890 break;
891
6e507301 892 case UNSPEC:
893 switch (XINT (op, 1))
894 {
895 case UNSPEC_PID_ADDR:
896 {
897 rtx sym, add;
898
899 if (print_hash)
900 fprintf (file, "#");
901 sym = XVECEXP (op, 0, 0);
902 add = NULL_RTX;
903 fprintf (file, "(");
904 if (GET_CODE (sym) == PLUS)
905 {
906 add = XEXP (sym, 1);
907 sym = XEXP (sym, 0);
908 }
909 output_addr_const (file, sym);
910 if (add != NULL_RTX)
911 {
912 fprintf (file, "+");
913 output_addr_const (file, add);
914 }
915 fprintf (file, "-__pid_base");
916 fprintf (file, ")");
917 return;
918 }
919 }
920 /* Fall through */
921
24833e1a 922 case CONST:
6e507301 923 case SYMBOL_REF:
24833e1a 924 case LABEL_REF:
925 case CODE_LABEL:
3c047fe9 926 rx_print_operand_address (file, VOIDmode, op);
24833e1a 927 break;
928
929 default:
930 gcc_unreachable ();
931 }
932 break;
933 }
934}
935
6e507301 936/* Maybe convert an operand into its PID format. */
937
938rtx
939rx_maybe_pidify_operand (rtx op, int copy_to_reg)
940{
941 if (rx_pid_data_operand (op) == PID_UNENCODED)
942 {
943 if (GET_CODE (op) == MEM)
944 {
945 rtx a = gen_pid_addr (gen_rtx_REG (SImode, rx_pid_base_regnum ()), XEXP (op, 0));
946 op = replace_equiv_address (op, a);
947 }
948 else
949 {
950 op = gen_pid_addr (gen_rtx_REG (SImode, rx_pid_base_regnum ()), op);
951 }
952
953 if (copy_to_reg)
954 op = copy_to_mode_reg (GET_MODE (op), op);
955 }
956 return op;
957}
958
24833e1a 959/* Returns an assembler template for a move instruction. */
960
961char *
962rx_gen_move_template (rtx * operands, bool is_movu)
963{
6bb30542 964 static char out_template [64];
24833e1a 965 const char * extension = TARGET_AS100_SYNTAX ? ".L" : "";
966 const char * src_template;
967 const char * dst_template;
968 rtx dest = operands[0];
969 rtx src = operands[1];
970
971 /* Decide which extension, if any, should be given to the move instruction. */
972 switch (CONST_INT_P (src) ? GET_MODE (dest) : GET_MODE (src))
973 {
916ace94 974 case E_QImode:
24833e1a 975 /* The .B extension is not valid when
976 loading an immediate into a register. */
977 if (! REG_P (dest) || ! CONST_INT_P (src))
978 extension = ".B";
979 break;
916ace94 980 case E_HImode:
24833e1a 981 if (! REG_P (dest) || ! CONST_INT_P (src))
982 /* The .W extension is not valid when
983 loading an immediate into a register. */
984 extension = ".W";
985 break;
916ace94 986 case E_DFmode:
987 case E_DImode:
988 case E_SFmode:
989 case E_SImode:
24833e1a 990 extension = ".L";
991 break;
916ace94 992 case E_VOIDmode:
24833e1a 993 /* This mode is used by constants. */
994 break;
995 default:
996 debug_rtx (src);
997 gcc_unreachable ();
998 }
999
6e507301 1000 if (MEM_P (src) && rx_pid_data_operand (XEXP (src, 0)) == PID_UNENCODED)
f0964309 1001 {
1002 gcc_assert (GET_MODE (src) != DImode);
1003 gcc_assert (GET_MODE (src) != DFmode);
1004
1005 src_template = "(%A1 - __pid_base)[%P1]";
1006 }
6e507301 1007 else if (MEM_P (src) && rx_small_data_operand (XEXP (src, 0)))
f0964309 1008 {
1009 gcc_assert (GET_MODE (src) != DImode);
1010 gcc_assert (GET_MODE (src) != DFmode);
1011
1012 src_template = "%%gp(%A1)[%G1]";
1013 }
24833e1a 1014 else
1015 src_template = "%1";
1016
1017 if (MEM_P (dest) && rx_small_data_operand (XEXP (dest, 0)))
f0964309 1018 {
1019 gcc_assert (GET_MODE (dest) != DImode);
1020 gcc_assert (GET_MODE (dest) != DFmode);
1021
1022 dst_template = "%%gp(%A0)[%G0]";
1023 }
24833e1a 1024 else
1025 dst_template = "%0";
1026
f0964309 1027 if (GET_MODE (dest) == DImode || GET_MODE (dest) == DFmode)
1028 {
1029 gcc_assert (! is_movu);
1030
1031 if (REG_P (src) && REG_P (dest) && (REGNO (dest) == REGNO (src) + 1))
734bbdc0 1032 sprintf (out_template, "mov.L\t%%H1, %%H0 ! mov.L\t%%1, %%0");
f0964309 1033 else
734bbdc0 1034 sprintf (out_template, "mov.L\t%%1, %%0 ! mov.L\t%%H1, %%H0");
f0964309 1035 }
1036 else
1037 sprintf (out_template, "%s%s\t%s, %s", is_movu ? "movu" : "mov",
1038 extension, src_template, dst_template);
6bb30542 1039 return out_template;
24833e1a 1040}
24833e1a 1041\f
1042/* Return VALUE rounded up to the next ALIGNMENT boundary. */
1043
1044static inline unsigned int
1045rx_round_up (unsigned int value, unsigned int alignment)
1046{
1047 alignment -= 1;
1048 return (value + alignment) & (~ alignment);
1049}
1050
1051/* Return the number of bytes in the argument registers
1052 occupied by an argument of type TYPE and mode MODE. */
1053
ee4e8428 1054static unsigned int
3754d046 1055rx_function_arg_size (machine_mode mode, const_tree type)
24833e1a 1056{
1057 unsigned int num_bytes;
1058
1059 num_bytes = (mode == BLKmode)
1060 ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
1061 return rx_round_up (num_bytes, UNITS_PER_WORD);
1062}
1063
1064#define NUM_ARG_REGS 4
1065#define MAX_NUM_ARG_BYTES (NUM_ARG_REGS * UNITS_PER_WORD)
1066
1067/* Return an RTL expression describing the register holding a function
1068 parameter of mode MODE and type TYPE or NULL_RTX if the parameter should
1069 be passed on the stack. CUM describes the previous parameters to the
1070 function and NAMED is false if the parameter is part of a variable
1071 parameter list, or the last named parameter before the start of a
1072 variable parameter list. */
1073
ee4e8428 1074static rtx
3754d046 1075rx_function_arg (cumulative_args_t cum, machine_mode mode,
4bccad5e 1076 const_tree type, bool named)
24833e1a 1077{
1078 unsigned int next_reg;
39cba157 1079 unsigned int bytes_so_far = *get_cumulative_args (cum);
24833e1a 1080 unsigned int size;
1081 unsigned int rounded_size;
1082
1083 /* An exploded version of rx_function_arg_size. */
1084 size = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode);
6bb30542 1085 /* If the size is not known it cannot be passed in registers. */
1086 if (size < 1)
1087 return NULL_RTX;
24833e1a 1088
1089 rounded_size = rx_round_up (size, UNITS_PER_WORD);
1090
1091 /* Don't pass this arg via registers if there
1092 are insufficient registers to hold all of it. */
1093 if (rounded_size + bytes_so_far > MAX_NUM_ARG_BYTES)
1094 return NULL_RTX;
1095
1096 /* Unnamed arguments and the last named argument in a
1097 variadic function are always passed on the stack. */
1098 if (!named)
1099 return NULL_RTX;
1100
1101 /* Structures must occupy an exact number of registers,
1102 otherwise they are passed on the stack. */
1103 if ((type == NULL || AGGREGATE_TYPE_P (type))
1104 && (size % UNITS_PER_WORD) != 0)
1105 return NULL_RTX;
1106
1107 next_reg = (bytes_so_far / UNITS_PER_WORD) + 1;
1108
1109 return gen_rtx_REG (mode, next_reg);
1110}
1111
ee4e8428 1112static void
3754d046 1113rx_function_arg_advance (cumulative_args_t cum, machine_mode mode,
4bccad5e 1114 const_tree type, bool named ATTRIBUTE_UNUSED)
ee4e8428 1115{
39cba157 1116 *get_cumulative_args (cum) += rx_function_arg_size (mode, type);
ee4e8428 1117}
1118
bd99ba64 1119static unsigned int
3754d046 1120rx_function_arg_boundary (machine_mode mode ATTRIBUTE_UNUSED,
bd99ba64 1121 const_tree type ATTRIBUTE_UNUSED)
1122{
4246a5c7 1123 /* Older versions of the RX backend aligned all on-stack arguments
ee1401ac 1124 to 32-bits. The RX C ABI however says that they should be
1125 aligned to their natural alignment. (See section 5.2.2 of the ABI). */
1126 if (TARGET_GCC_ABI)
1127 return STACK_BOUNDARY;
1128
1129 if (type)
1130 {
1131 if (DECL_P (type))
1132 return DECL_ALIGN (type);
1133 return TYPE_ALIGN (type);
1134 }
1135
1136 return PARM_BOUNDARY;
bd99ba64 1137}
1138
24833e1a 1139/* Return an RTL describing where a function return value of type RET_TYPE
1140 is held. */
1141
1142static rtx
1143rx_function_value (const_tree ret_type,
1144 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
1145 bool outgoing ATTRIBUTE_UNUSED)
1146{
3754d046 1147 machine_mode mode = TYPE_MODE (ret_type);
bd7d2835 1148
1149 /* RX ABI specifies that small integer types are
1150 promoted to int when returned by a function. */
02f06d23 1151 if (GET_MODE_SIZE (mode) > 0
1152 && GET_MODE_SIZE (mode) < 4
1153 && ! COMPLEX_MODE_P (mode)
942ca701 1154 && ! VECTOR_TYPE_P (ret_type)
1155 && ! VECTOR_MODE_P (mode)
02f06d23 1156 )
bd7d2835 1157 return gen_rtx_REG (SImode, FUNC_RETURN_REGNUM);
1158
1159 return gen_rtx_REG (mode, FUNC_RETURN_REGNUM);
1160}
1161
1162/* TARGET_PROMOTE_FUNCTION_MODE must behave in the same way with
1163 regard to function returns as does TARGET_FUNCTION_VALUE. */
1164
3754d046 1165static machine_mode
bd7d2835 1166rx_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
3754d046 1167 machine_mode mode,
0318c61a 1168 int * punsignedp ATTRIBUTE_UNUSED,
bd7d2835 1169 const_tree funtype ATTRIBUTE_UNUSED,
1170 int for_return)
1171{
1172 if (for_return != 1
1173 || GET_MODE_SIZE (mode) >= 4
02f06d23 1174 || COMPLEX_MODE_P (mode)
942ca701 1175 || VECTOR_MODE_P (mode)
1176 || VECTOR_TYPE_P (type)
bd7d2835 1177 || GET_MODE_SIZE (mode) < 1)
1178 return mode;
1179
1180 return SImode;
24833e1a 1181}
1182
1183static bool
1184rx_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1185{
1186 HOST_WIDE_INT size;
1187
1188 if (TYPE_MODE (type) != BLKmode
1189 && ! AGGREGATE_TYPE_P (type))
1190 return false;
1191
1192 size = int_size_in_bytes (type);
1193 /* Large structs and those whose size is not an
1194 exact multiple of 4 are returned in memory. */
1195 return size < 1
1196 || size > 16
1197 || (size % UNITS_PER_WORD) != 0;
1198}
1199
1200static rtx
1201rx_struct_value_rtx (tree fndecl ATTRIBUTE_UNUSED,
1202 int incoming ATTRIBUTE_UNUSED)
1203{
1204 return gen_rtx_REG (Pmode, STRUCT_VAL_REGNUM);
1205}
1206
1207static bool
1208rx_return_in_msb (const_tree valtype)
1209{
1210 return TARGET_BIG_ENDIAN_DATA
1211 && (AGGREGATE_TYPE_P (valtype) || TREE_CODE (valtype) == COMPLEX_TYPE);
1212}
1213
1214/* Returns true if the provided function has the specified attribute. */
1215
1216static inline bool
1217has_func_attr (const_tree decl, const char * func_attr)
1218{
1219 if (decl == NULL_TREE)
1220 decl = current_function_decl;
1221
1222 return lookup_attribute (func_attr, DECL_ATTRIBUTES (decl)) != NULL_TREE;
1223}
1224
67e66e16 1225/* Returns true if the provided function has the "fast_interrupt" attribute. */
24833e1a 1226
140a4ed4 1227bool
24833e1a 1228is_fast_interrupt_func (const_tree decl)
1229{
67e66e16 1230 return has_func_attr (decl, "fast_interrupt");
24833e1a 1231}
1232
67e66e16 1233/* Returns true if the provided function has the "interrupt" attribute. */
24833e1a 1234
140a4ed4 1235bool
67e66e16 1236is_interrupt_func (const_tree decl)
24833e1a 1237{
67e66e16 1238 return has_func_attr (decl, "interrupt");
24833e1a 1239}
1240
1241/* Returns true if the provided function has the "naked" attribute. */
1242
1243static inline bool
1244is_naked_func (const_tree decl)
1245{
1246 return has_func_attr (decl, "naked");
1247}
1248\f
1249static bool use_fixed_regs = false;
1250
b2d7ede1 1251static void
24833e1a 1252rx_conditional_register_usage (void)
1253{
1254 static bool using_fixed_regs = false;
1255
6e507301 1256 if (TARGET_PID)
1257 {
1258 rx_pid_base_regnum_val = GP_BASE_REGNUM - rx_num_interrupt_regs;
1259 fixed_regs[rx_pid_base_regnum_val] = call_used_regs [rx_pid_base_regnum_val] = 1;
1260 }
1261
24833e1a 1262 if (rx_small_data_limit > 0)
6e507301 1263 {
1264 if (TARGET_PID)
1265 rx_gp_base_regnum_val = rx_pid_base_regnum_val - 1;
1266 else
1267 rx_gp_base_regnum_val = GP_BASE_REGNUM - rx_num_interrupt_regs;
1268
1269 fixed_regs[rx_gp_base_regnum_val] = call_used_regs [rx_gp_base_regnum_val] = 1;
1270 }
24833e1a 1271
1272 if (use_fixed_regs != using_fixed_regs)
1273 {
1274 static char saved_fixed_regs[FIRST_PSEUDO_REGISTER];
1275 static char saved_call_used_regs[FIRST_PSEUDO_REGISTER];
1276
1277 if (use_fixed_regs)
1278 {
24833e1a 1279 unsigned int r;
1280
24833e1a 1281 memcpy (saved_fixed_regs, fixed_regs, sizeof fixed_regs);
1282 memcpy (saved_call_used_regs, call_used_regs, sizeof call_used_regs);
e4d9e8e5 1283
1284 /* This is for fast interrupt handlers. Any register in
1285 the range r10 to r13 (inclusive) that is currently
1286 marked as fixed is now a viable, call-used register. */
24833e1a 1287 for (r = 10; r <= 13; r++)
1288 if (fixed_regs[r])
1289 {
1290 fixed_regs[r] = 0;
1291 call_used_regs[r] = 1;
24833e1a 1292 }
1293
e4d9e8e5 1294 /* Mark r7 as fixed. This is just a hack to avoid
1295 altering the reg_alloc_order array so that the newly
1296 freed r10-r13 registers are the preferred registers. */
1297 fixed_regs[7] = call_used_regs[7] = 1;
24833e1a 1298 }
1299 else
1300 {
1301 /* Restore the normal register masks. */
1302 memcpy (fixed_regs, saved_fixed_regs, sizeof fixed_regs);
1303 memcpy (call_used_regs, saved_call_used_regs, sizeof call_used_regs);
1304 }
1305
1306 using_fixed_regs = use_fixed_regs;
1307 }
1308}
1309
6a47b360 1310struct decl_chain
1311{
1312 tree fndecl;
1313 struct decl_chain * next;
1314};
1315
1316/* Stack of decls for which we have issued warnings. */
1317static struct decl_chain * warned_decls = NULL;
1318
1319static void
1320add_warned_decl (tree fndecl)
1321{
1322 struct decl_chain * warned = (struct decl_chain *) xmalloc (sizeof * warned);
1323
1324 warned->fndecl = fndecl;
1325 warned->next = warned_decls;
1326 warned_decls = warned;
1327}
1328
1329/* Returns TRUE if FNDECL is on our list of warned about decls. */
1330
1331static bool
1332already_warned (tree fndecl)
1333{
1334 struct decl_chain * warned;
1335
1336 for (warned = warned_decls;
1337 warned != NULL;
1338 warned = warned->next)
1339 if (warned->fndecl == fndecl)
1340 return true;
1341
1342 return false;
1343}
1344
24833e1a 1345/* Perform any actions necessary before starting to compile FNDECL.
1346 For the RX we use this to make sure that we have the correct
1347 set of register masks selected. If FNDECL is NULL then we are
1348 compiling top level things. */
1349
1350static void
1351rx_set_current_function (tree fndecl)
1352{
1353 /* Remember the last target of rx_set_current_function. */
1354 static tree rx_previous_fndecl;
67e66e16 1355 bool prev_was_fast_interrupt;
1356 bool current_is_fast_interrupt;
24833e1a 1357
1358 /* Only change the context if the function changes. This hook is called
1359 several times in the course of compiling a function, and we don't want
1360 to slow things down too much or call target_reinit when it isn't safe. */
1361 if (fndecl == rx_previous_fndecl)
1362 return;
1363
67e66e16 1364 prev_was_fast_interrupt
24833e1a 1365 = rx_previous_fndecl
1366 ? is_fast_interrupt_func (rx_previous_fndecl) : false;
67e66e16 1367
1368 current_is_fast_interrupt
24833e1a 1369 = fndecl ? is_fast_interrupt_func (fndecl) : false;
1370
67e66e16 1371 if (prev_was_fast_interrupt != current_is_fast_interrupt)
24833e1a 1372 {
67e66e16 1373 use_fixed_regs = current_is_fast_interrupt;
24833e1a 1374 target_reinit ();
1375 }
67e66e16 1376
6a47b360 1377 if (current_is_fast_interrupt && rx_warn_multiple_fast_interrupts)
1378 {
1379 /* We do not warn about the first fast interrupt routine that
1380 we see. Instead we just push it onto the stack. */
1381 if (warned_decls == NULL)
1382 add_warned_decl (fndecl);
1383
1384 /* Otherwise if this fast interrupt is one for which we have
1385 not already issued a warning, generate one and then push
1386 it onto the stack as well. */
1387 else if (! already_warned (fndecl))
1388 {
1389 warning (0, "multiple fast interrupt routines seen: %qE and %qE",
1390 fndecl, warned_decls->fndecl);
1391 add_warned_decl (fndecl);
1392 }
1393 }
1394
24833e1a 1395 rx_previous_fndecl = fndecl;
1396}
1397\f
1398/* Typical stack layout should looks like this after the function's prologue:
1399
1400 | |
1401 -- ^
1402 | | \ |
1403 | | arguments saved | Increasing
1404 | | on the stack | addresses
1405 PARENT arg pointer -> | | /
1406 -------------------------- ---- -------------------
1407 CHILD |ret | return address
1408 --
1409 | | \
1410 | | call saved
1411 | | registers
1412 | | /
1413 --
1414 | | \
1415 | | local
1416 | | variables
1417 frame pointer -> | | /
1418 --
1419 | | \
1420 | | outgoing | Decreasing
1421 | | arguments | addresses
1422 current stack pointer -> | | / |
1423 -------------------------- ---- ------------------ V
1424 | | */
1425
1426static unsigned int
1427bit_count (unsigned int x)
1428{
1429 const unsigned int m1 = 0x55555555;
1430 const unsigned int m2 = 0x33333333;
1431 const unsigned int m4 = 0x0f0f0f0f;
1432
1433 x -= (x >> 1) & m1;
1434 x = (x & m2) + ((x >> 2) & m2);
1435 x = (x + (x >> 4)) & m4;
1436 x += x >> 8;
1437
1438 return (x + (x >> 16)) & 0x3f;
1439}
1440
e4d9e8e5 1441#define MUST_SAVE_ACC_REGISTER \
1442 (TARGET_SAVE_ACC_REGISTER \
1443 && (is_interrupt_func (NULL_TREE) \
1444 || is_fast_interrupt_func (NULL_TREE)))
1445
24833e1a 1446/* Returns either the lowest numbered and highest numbered registers that
1447 occupy the call-saved area of the stack frame, if the registers are
1448 stored as a contiguous block, or else a bitmask of the individual
1449 registers if they are stored piecemeal.
1450
1451 Also computes the size of the frame and the size of the outgoing
1452 arguments block (in bytes). */
1453
1454static void
1455rx_get_stack_layout (unsigned int * lowest,
1456 unsigned int * highest,
1457 unsigned int * register_mask,
1458 unsigned int * frame_size,
1459 unsigned int * stack_size)
1460{
1461 unsigned int reg;
1462 unsigned int low;
1463 unsigned int high;
1464 unsigned int fixed_reg = 0;
1465 unsigned int save_mask;
1466 unsigned int pushed_mask;
1467 unsigned int unneeded_pushes;
1468
e4d9e8e5 1469 if (is_naked_func (NULL_TREE))
24833e1a 1470 {
1471 /* Naked functions do not create their own stack frame.
e4d9e8e5 1472 Instead the programmer must do that for us. */
24833e1a 1473 * lowest = 0;
1474 * highest = 0;
1475 * register_mask = 0;
1476 * frame_size = 0;
1477 * stack_size = 0;
1478 return;
1479 }
1480
9d2f1b03 1481 for (save_mask = high = low = 0, reg = 1; reg < CC_REGNUM; reg++)
24833e1a 1482 {
21cde6ec 1483 if ((df_regs_ever_live_p (reg)
382ffb70 1484 /* Always save all call clobbered registers inside non-leaf
1485 interrupt handlers, even if they are not live - they may
1486 be used in (non-interrupt aware) routines called from this one. */
1487 || (call_used_regs[reg]
1488 && is_interrupt_func (NULL_TREE)
d5bf7b64 1489 && ! crtl->is_leaf))
24833e1a 1490 && (! call_used_regs[reg]
1491 /* Even call clobbered registered must
67e66e16 1492 be pushed inside interrupt handlers. */
e4d9e8e5 1493 || is_interrupt_func (NULL_TREE)
1494 /* Likewise for fast interrupt handlers, except registers r10 -
1495 r13. These are normally call-saved, but may have been set
1496 to call-used by rx_conditional_register_usage. If so then
1497 they can be used in the fast interrupt handler without
1498 saving them on the stack. */
1499 || (is_fast_interrupt_func (NULL_TREE)
1500 && ! IN_RANGE (reg, 10, 13))))
24833e1a 1501 {
1502 if (low == 0)
1503 low = reg;
1504 high = reg;
1505
1506 save_mask |= 1 << reg;
1507 }
1508
1509 /* Remember if we see a fixed register
1510 after having found the low register. */
1511 if (low != 0 && fixed_reg == 0 && fixed_regs [reg])
1512 fixed_reg = reg;
1513 }
1514
e4d9e8e5 1515 /* If we have to save the accumulator register, make sure
1516 that at least two registers are pushed into the frame. */
1517 if (MUST_SAVE_ACC_REGISTER
1518 && bit_count (save_mask) < 2)
1519 {
1520 save_mask |= (1 << 13) | (1 << 14);
1521 if (low == 0)
1522 low = 13;
bc9bb967 1523 if (high == 0 || low == high)
1524 high = low + 1;
e4d9e8e5 1525 }
1526
24833e1a 1527 /* Decide if it would be faster fill in the call-saved area of the stack
1528 frame using multiple PUSH instructions instead of a single PUSHM
1529 instruction.
1530
1531 SAVE_MASK is a bitmask of the registers that must be stored in the
1532 call-save area. PUSHED_MASK is a bitmask of the registers that would
1533 be pushed into the area if we used a PUSHM instruction. UNNEEDED_PUSHES
1534 is a bitmask of those registers in pushed_mask that are not in
1535 save_mask.
1536
1537 We use a simple heuristic that says that it is better to use
1538 multiple PUSH instructions if the number of unnecessary pushes is
1539 greater than the number of necessary pushes.
1540
1541 We also use multiple PUSH instructions if there are any fixed registers
1542 between LOW and HIGH. The only way that this can happen is if the user
1543 has specified --fixed-<reg-name> on the command line and in such
1544 circumstances we do not want to touch the fixed registers at all.
1545
75759166 1546 Note also that the code in the prologue/epilogue handlers will
1547 automatically merge multiple PUSHes of adjacent registers into a single
1548 PUSHM.
1549
24833e1a 1550 FIXME: Is it worth improving this heuristic ? */
1e9446db 1551 pushed_mask = (HOST_WIDE_INT_M1U << low) & ~(HOST_WIDE_INT_M1U << (high + 1));
24833e1a 1552 unneeded_pushes = (pushed_mask & (~ save_mask)) & pushed_mask;
1553
1554 if ((fixed_reg && fixed_reg <= high)
1555 || (optimize_function_for_speed_p (cfun)
1556 && bit_count (save_mask) < bit_count (unneeded_pushes)))
1557 {
1558 /* Use multiple pushes. */
1559 * lowest = 0;
1560 * highest = 0;
1561 * register_mask = save_mask;
1562 }
1563 else
1564 {
1565 /* Use one push multiple instruction. */
1566 * lowest = low;
1567 * highest = high;
1568 * register_mask = 0;
1569 }
1570
1571 * frame_size = rx_round_up
1572 (get_frame_size (), STACK_BOUNDARY / BITS_PER_UNIT);
1573
1574 if (crtl->args.size > 0)
1575 * frame_size += rx_round_up
1576 (crtl->args.size, STACK_BOUNDARY / BITS_PER_UNIT);
1577
1578 * stack_size = rx_round_up
1579 (crtl->outgoing_args_size, STACK_BOUNDARY / BITS_PER_UNIT);
1580}
1581
1582/* Generate a PUSHM instruction that matches the given operands. */
1583
1584void
1585rx_emit_stack_pushm (rtx * operands)
1586{
1587 HOST_WIDE_INT last_reg;
1588 rtx first_push;
1589
1590 gcc_assert (CONST_INT_P (operands[0]));
1591 last_reg = (INTVAL (operands[0]) / UNITS_PER_WORD) - 1;
1592
1593 gcc_assert (GET_CODE (operands[1]) == PARALLEL);
1594 first_push = XVECEXP (operands[1], 0, 1);
1595 gcc_assert (SET_P (first_push));
1596 first_push = SET_SRC (first_push);
1597 gcc_assert (REG_P (first_push));
1598
1599 asm_fprintf (asm_out_file, "\tpushm\t%s-%s\n",
67e66e16 1600 reg_names [REGNO (first_push) - last_reg],
1601 reg_names [REGNO (first_push)]);
24833e1a 1602}
1603
1604/* Generate a PARALLEL that will pass the rx_store_multiple_vector predicate. */
1605
1606static rtx
1607gen_rx_store_vector (unsigned int low, unsigned int high)
1608{
1609 unsigned int i;
1610 unsigned int count = (high - low) + 2;
1611 rtx vector;
1612
1613 vector = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1614
1615 XVECEXP (vector, 0, 0) =
d1f9b275 1616 gen_rtx_SET (stack_pointer_rtx,
24833e1a 1617 gen_rtx_MINUS (SImode, stack_pointer_rtx,
1618 GEN_INT ((count - 1) * UNITS_PER_WORD)));
1619
1620 for (i = 0; i < count - 1; i++)
1621 XVECEXP (vector, 0, i + 1) =
d1f9b275 1622 gen_rtx_SET (gen_rtx_MEM (SImode,
67e66e16 1623 gen_rtx_MINUS (SImode, stack_pointer_rtx,
1624 GEN_INT ((i + 1) * UNITS_PER_WORD))),
1625 gen_rtx_REG (SImode, high - i));
24833e1a 1626 return vector;
1627}
1628
67e66e16 1629/* Mark INSN as being frame related. If it is a PARALLEL
1630 then mark each element as being frame related as well. */
1631
1632static void
1633mark_frame_related (rtx insn)
1634{
1635 RTX_FRAME_RELATED_P (insn) = 1;
1636 insn = PATTERN (insn);
1637
1638 if (GET_CODE (insn) == PARALLEL)
1639 {
1640 unsigned int i;
1641
61fc50a0 1642 for (i = 0; i < (unsigned) XVECLEN (insn, 0); i++)
67e66e16 1643 RTX_FRAME_RELATED_P (XVECEXP (insn, 0, i)) = 1;
1644 }
1645}
1646
f333f977 1647/* Create CFI notes for register pops. */
1648static void
1649add_pop_cfi_notes (rtx_insn *insn, unsigned int high, unsigned int low)
1650{
1651 rtx t = plus_constant (Pmode, stack_pointer_rtx,
1652 (high - low + 1) * UNITS_PER_WORD);
1653 t = gen_rtx_SET (stack_pointer_rtx, t);
1654 add_reg_note (insn, REG_CFA_ADJUST_CFA, t);
1655 RTX_FRAME_RELATED_P (insn) = 1;
1656 for (unsigned int i = low; i <= high; i++)
1657 add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (word_mode, i));
1658}
1659
1660
95272799 1661static bool
1662ok_for_max_constant (HOST_WIDE_INT val)
1663{
1664 if (rx_max_constant_size == 0 || rx_max_constant_size == 4)
1665 /* If there is no constraint on the size of constants
1666 used as operands, then any value is legitimate. */
1667 return true;
1668
1669 /* rx_max_constant_size specifies the maximum number
1670 of bytes that can be used to hold a signed value. */
1e9446db 1671 return IN_RANGE (val, (HOST_WIDE_INT_M1U << (rx_max_constant_size * 8)),
95272799 1672 ( 1 << (rx_max_constant_size * 8)));
1673}
1674
1675/* Generate an ADD of SRC plus VAL into DEST.
1676 Handles the case where VAL is too big for max_constant_value.
1677 Sets FRAME_RELATED_P on the insn if IS_FRAME_RELATED is true. */
1678
1679static void
1680gen_safe_add (rtx dest, rtx src, rtx val, bool is_frame_related)
1681{
1682 rtx insn;
1683
1684 if (val == NULL_RTX || INTVAL (val) == 0)
1685 {
1686 gcc_assert (dest != src);
1687
1688 insn = emit_move_insn (dest, src);
1689 }
1690 else if (ok_for_max_constant (INTVAL (val)))
1691 insn = emit_insn (gen_addsi3 (dest, src, val));
1692 else
1693 {
f7fcec1a 1694 /* Wrap VAL in an UNSPEC so that rx_is_legitimate_constant
02f06d23 1695 will not reject it. */
1696 val = gen_rtx_CONST (SImode, gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_CONST));
1697 insn = emit_insn (gen_addsi3 (dest, src, val));
95272799 1698
1699 if (is_frame_related)
1700 /* We have to provide our own frame related note here
1701 as the dwarf2out code cannot be expected to grok
1702 our unspec. */
1703 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
d1f9b275 1704 gen_rtx_SET (dest, gen_rtx_PLUS (SImode, src, val)));
95272799 1705 return;
1706 }
1707
1708 if (is_frame_related)
1709 RTX_FRAME_RELATED_P (insn) = 1;
95272799 1710}
1711
75759166 1712static void
1713push_regs (unsigned int high, unsigned int low)
1714{
1715 rtx insn;
1716
1717 if (low == high)
1718 insn = emit_insn (gen_stack_push (gen_rtx_REG (SImode, low)));
1719 else
1720 insn = emit_insn (gen_stack_pushm (GEN_INT (((high - low) + 1) * UNITS_PER_WORD),
1721 gen_rx_store_vector (low, high)));
1722 mark_frame_related (insn);
1723}
1724
24833e1a 1725void
1726rx_expand_prologue (void)
1727{
1728 unsigned int stack_size;
1729 unsigned int frame_size;
1730 unsigned int mask;
1731 unsigned int low;
1732 unsigned int high;
67e66e16 1733 unsigned int reg;
24833e1a 1734
1735 /* Naked functions use their own, programmer provided prologues. */
e4d9e8e5 1736 if (is_naked_func (NULL_TREE))
24833e1a 1737 return;
1738
1739 rx_get_stack_layout (& low, & high, & mask, & frame_size, & stack_size);
1740
ecfbd70a 1741 if (flag_stack_usage_info)
1742 current_function_static_stack_size = frame_size + stack_size;
942ca701 1743
24833e1a 1744 /* If we use any of the callee-saved registers, save them now. */
1745 if (mask)
1746 {
24833e1a 1747 /* Push registers in reverse order. */
9d2f1b03 1748 for (reg = CC_REGNUM; reg --;)
24833e1a 1749 if (mask & (1 << reg))
1750 {
75759166 1751 low = high = reg;
1752
1753 /* Look for a span of registers.
1754 Note - we do not have to worry about -Os and whether
1755 it is better to use a single, longer PUSHM as
1756 rx_get_stack_layout has already done that for us. */
1757 while (reg-- > 0)
1758 if ((mask & (1 << reg)) == 0)
1759 break;
1760 else
1761 --low;
1762
1763 push_regs (high, low);
1764 if (reg == (unsigned) -1)
1765 break;
24833e1a 1766 }
1767 }
1768 else if (low)
75759166 1769 push_regs (high, low);
67e66e16 1770
e4d9e8e5 1771 if (MUST_SAVE_ACC_REGISTER)
67e66e16 1772 {
1773 unsigned int acc_high, acc_low;
1774
1775 /* Interrupt handlers have to preserve the accumulator
1776 register if so requested by the user. Use the first
e4d9e8e5 1777 two pushed registers as intermediaries. */
67e66e16 1778 if (mask)
1779 {
1780 acc_low = acc_high = 0;
1781
9d2f1b03 1782 for (reg = 1; reg < CC_REGNUM; reg ++)
67e66e16 1783 if (mask & (1 << reg))
1784 {
1785 if (acc_low == 0)
1786 acc_low = reg;
1787 else
1788 {
1789 acc_high = reg;
1790 break;
1791 }
1792 }
1793
1794 /* We have assumed that there are at least two registers pushed... */
1795 gcc_assert (acc_high != 0);
1796
1797 /* Note - the bottom 16 bits of the accumulator are inaccessible.
1798 We just assume that they are zero. */
1799 emit_insn (gen_mvfacmi (gen_rtx_REG (SImode, acc_low)));
1800 emit_insn (gen_mvfachi (gen_rtx_REG (SImode, acc_high)));
1801 emit_insn (gen_stack_push (gen_rtx_REG (SImode, acc_low)));
1802 emit_insn (gen_stack_push (gen_rtx_REG (SImode, acc_high)));
1803 }
1804 else
1805 {
1806 acc_low = low;
1807 acc_high = low + 1;
1808
1809 /* We have assumed that there are at least two registers pushed... */
1810 gcc_assert (acc_high <= high);
1811
1812 emit_insn (gen_mvfacmi (gen_rtx_REG (SImode, acc_low)));
1813 emit_insn (gen_mvfachi (gen_rtx_REG (SImode, acc_high)));
1814 emit_insn (gen_stack_pushm (GEN_INT (2 * UNITS_PER_WORD),
1815 gen_rx_store_vector (acc_low, acc_high)));
1816 }
24833e1a 1817 }
1818
1819 /* If needed, set up the frame pointer. */
1820 if (frame_pointer_needed)
95272799 1821 gen_safe_add (frame_pointer_rtx, stack_pointer_rtx,
1822 GEN_INT (- (HOST_WIDE_INT) frame_size), true);
24833e1a 1823
1824 /* Allocate space for the outgoing args.
1825 If the stack frame has not already been set up then handle this as well. */
1826 if (stack_size)
1827 {
1828 if (frame_size)
1829 {
1830 if (frame_pointer_needed)
95272799 1831 gen_safe_add (stack_pointer_rtx, frame_pointer_rtx,
1832 GEN_INT (- (HOST_WIDE_INT) stack_size), true);
24833e1a 1833 else
95272799 1834 gen_safe_add (stack_pointer_rtx, stack_pointer_rtx,
1835 GEN_INT (- (HOST_WIDE_INT) (frame_size + stack_size)),
1836 true);
24833e1a 1837 }
1838 else
95272799 1839 gen_safe_add (stack_pointer_rtx, stack_pointer_rtx,
1840 GEN_INT (- (HOST_WIDE_INT) stack_size), true);
24833e1a 1841 }
1842 else if (frame_size)
1843 {
1844 if (! frame_pointer_needed)
95272799 1845 gen_safe_add (stack_pointer_rtx, stack_pointer_rtx,
1846 GEN_INT (- (HOST_WIDE_INT) frame_size), true);
24833e1a 1847 else
95272799 1848 gen_safe_add (stack_pointer_rtx, frame_pointer_rtx, NULL_RTX,
942ca701 1849 false /* False because the epilogue will use the FP not the SP. */);
24833e1a 1850 }
24833e1a 1851}
1852
7ce85a1f 1853static void
1854add_vector_labels (FILE *file, const char *aname)
1855{
1856 tree vec_attr;
1857 tree val_attr;
1858 const char *vname = "vect";
1859 const char *s;
1860 int vnum;
1861
1862 /* This node is for the vector/interrupt tag itself */
1863 vec_attr = lookup_attribute (aname, DECL_ATTRIBUTES (current_function_decl));
1864 if (!vec_attr)
1865 return;
1866
1867 /* Now point it at the first argument */
1868 vec_attr = TREE_VALUE (vec_attr);
1869
1870 /* Iterate through the arguments. */
1871 while (vec_attr)
1872 {
1873 val_attr = TREE_VALUE (vec_attr);
1874 switch (TREE_CODE (val_attr))
1875 {
1876 case STRING_CST:
1877 s = TREE_STRING_POINTER (val_attr);
1878 goto string_id_common;
1879
1880 case IDENTIFIER_NODE:
1881 s = IDENTIFIER_POINTER (val_attr);
1882
1883 string_id_common:
1884 if (strcmp (s, "$default") == 0)
1885 {
1886 fprintf (file, "\t.global\t$tableentry$default$%s\n", vname);
1887 fprintf (file, "$tableentry$default$%s:\n", vname);
1888 }
1889 else
1890 vname = s;
1891 break;
1892
1893 case INTEGER_CST:
1894 vnum = TREE_INT_CST_LOW (val_attr);
1895
1896 fprintf (file, "\t.global\t$tableentry$%d$%s\n", vnum, vname);
1897 fprintf (file, "$tableentry$%d$%s:\n", vnum, vname);
1898 break;
1899
1900 default:
1901 ;
1902 }
1903
1904 vec_attr = TREE_CHAIN (vec_attr);
1905 }
1906
1907}
1908
24833e1a 1909static void
718e6d56 1910rx_output_function_prologue (FILE * file)
24833e1a 1911{
7ce85a1f 1912 add_vector_labels (file, "interrupt");
1913 add_vector_labels (file, "vector");
1914
24833e1a 1915 if (is_fast_interrupt_func (NULL_TREE))
1916 asm_fprintf (file, "\t; Note: Fast Interrupt Handler\n");
1917
67e66e16 1918 if (is_interrupt_func (NULL_TREE))
1919 asm_fprintf (file, "\t; Note: Interrupt Handler\n");
24833e1a 1920
1921 if (is_naked_func (NULL_TREE))
1922 asm_fprintf (file, "\t; Note: Naked Function\n");
1923
1924 if (cfun->static_chain_decl != NULL)
1925 asm_fprintf (file, "\t; Note: Nested function declared "
1926 "inside another function.\n");
1927
1928 if (crtl->calls_eh_return)
1929 asm_fprintf (file, "\t; Note: Calls __builtin_eh_return.\n");
1930}
1931
1932/* Generate a POPM or RTSD instruction that matches the given operands. */
1933
1934void
1935rx_emit_stack_popm (rtx * operands, bool is_popm)
1936{
1937 HOST_WIDE_INT stack_adjust;
1938 HOST_WIDE_INT last_reg;
1939 rtx first_push;
1940
1941 gcc_assert (CONST_INT_P (operands[0]));
1942 stack_adjust = INTVAL (operands[0]);
1943
1944 gcc_assert (GET_CODE (operands[1]) == PARALLEL);
1945 last_reg = XVECLEN (operands[1], 0) - (is_popm ? 2 : 3);
1946
1947 first_push = XVECEXP (operands[1], 0, 1);
1948 gcc_assert (SET_P (first_push));
1949 first_push = SET_DEST (first_push);
1950 gcc_assert (REG_P (first_push));
1951
1952 if (is_popm)
1953 asm_fprintf (asm_out_file, "\tpopm\t%s-%s\n",
1954 reg_names [REGNO (first_push)],
1955 reg_names [REGNO (first_push) + last_reg]);
1956 else
1957 asm_fprintf (asm_out_file, "\trtsd\t#%d, %s-%s\n",
1958 (int) stack_adjust,
1959 reg_names [REGNO (first_push)],
1960 reg_names [REGNO (first_push) + last_reg]);
1961}
1962
1963/* Generate a PARALLEL which will satisfy the rx_rtsd_vector predicate. */
1964
1965static rtx
1966gen_rx_rtsd_vector (unsigned int adjust, unsigned int low, unsigned int high)
1967{
1968 unsigned int i;
1969 unsigned int bias = 3;
1970 unsigned int count = (high - low) + bias;
1971 rtx vector;
1972
1973 vector = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1974
1975 XVECEXP (vector, 0, 0) =
d1f9b275 1976 gen_rtx_SET (stack_pointer_rtx,
29c05e22 1977 plus_constant (Pmode, stack_pointer_rtx, adjust));
24833e1a 1978
1979 for (i = 0; i < count - 2; i++)
1980 XVECEXP (vector, 0, i + 1) =
d1f9b275 1981 gen_rtx_SET (gen_rtx_REG (SImode, low + i),
24833e1a 1982 gen_rtx_MEM (SImode,
1983 i == 0 ? stack_pointer_rtx
29c05e22 1984 : plus_constant (Pmode, stack_pointer_rtx,
24833e1a 1985 i * UNITS_PER_WORD)));
1986
1a860023 1987 XVECEXP (vector, 0, count - 1) = ret_rtx;
24833e1a 1988
1989 return vector;
1990}
1991
1992/* Generate a PARALLEL which will satisfy the rx_load_multiple_vector predicate. */
1993
1994static rtx
1995gen_rx_popm_vector (unsigned int low, unsigned int high)
1996{
1997 unsigned int i;
1998 unsigned int count = (high - low) + 2;
1999 rtx vector;
2000
2001 vector = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2002
2003 XVECEXP (vector, 0, 0) =
d1f9b275 2004 gen_rtx_SET (stack_pointer_rtx,
29c05e22 2005 plus_constant (Pmode, stack_pointer_rtx,
24833e1a 2006 (count - 1) * UNITS_PER_WORD));
2007
2008 for (i = 0; i < count - 1; i++)
2009 XVECEXP (vector, 0, i + 1) =
d1f9b275 2010 gen_rtx_SET (gen_rtx_REG (SImode, low + i),
24833e1a 2011 gen_rtx_MEM (SImode,
2012 i == 0 ? stack_pointer_rtx
29c05e22 2013 : plus_constant (Pmode, stack_pointer_rtx,
24833e1a 2014 i * UNITS_PER_WORD)));
2015
2016 return vector;
2017}
f35edb6f 2018
2019/* Returns true if a simple return insn can be used. */
2020
2021bool
2022rx_can_use_simple_return (void)
2023{
2024 unsigned int low;
2025 unsigned int high;
2026 unsigned int frame_size;
2027 unsigned int stack_size;
2028 unsigned int register_mask;
2029
2030 if (is_naked_func (NULL_TREE)
2031 || is_fast_interrupt_func (NULL_TREE)
2032 || is_interrupt_func (NULL_TREE))
2033 return false;
2034
2035 rx_get_stack_layout (& low, & high, & register_mask,
2036 & frame_size, & stack_size);
2037
2038 return (register_mask == 0
2039 && (frame_size + stack_size) == 0
2040 && low == 0);
2041}
2042
75759166 2043static void
2044pop_regs (unsigned int high, unsigned int low)
2045{
f333f977 2046 rtx_insn *insn;
75759166 2047 if (high == low)
f333f977 2048 insn = emit_insn (gen_stack_pop (gen_rtx_REG (SImode, low)));
75759166 2049 else
f333f977 2050 insn = emit_insn (gen_stack_popm (GEN_INT (((high - low) + 1)
2051 * UNITS_PER_WORD),
2052 gen_rx_popm_vector (low, high)));
2053 add_pop_cfi_notes (insn, high, low);
75759166 2054}
2055
24833e1a 2056void
2057rx_expand_epilogue (bool is_sibcall)
2058{
2059 unsigned int low;
2060 unsigned int high;
2061 unsigned int frame_size;
2062 unsigned int stack_size;
2063 unsigned int register_mask;
2064 unsigned int regs_size;
67e66e16 2065 unsigned int reg;
24833e1a 2066 unsigned HOST_WIDE_INT total_size;
2067
61fc50a0 2068 /* FIXME: We do not support indirect sibcalls at the moment becaause we
2069 cannot guarantee that the register holding the function address is a
2070 call-used register. If it is a call-saved register then the stack
2071 pop instructions generated in the epilogue will corrupt the address
2072 before it is used.
2073
2074 Creating a new call-used-only register class works but then the
2075 reload pass gets stuck because it cannot always find a call-used
2076 register for spilling sibcalls.
2077
2078 The other possible solution is for this pass to scan forward for the
2079 sibcall instruction (if it has been generated) and work out if it
2080 is an indirect sibcall using a call-saved register. If it is then
2081 the address can copied into a call-used register in this epilogue
2082 code and the sibcall instruction modified to use that register. */
2083
24833e1a 2084 if (is_naked_func (NULL_TREE))
2085 {
61fc50a0 2086 gcc_assert (! is_sibcall);
2087
24833e1a 2088 /* Naked functions use their own, programmer provided epilogues.
2089 But, in order to keep gcc happy we have to generate some kind of
2090 epilogue RTL. */
2091 emit_jump_insn (gen_naked_return ());
2092 return;
2093 }
2094
2095 rx_get_stack_layout (& low, & high, & register_mask,
2096 & frame_size, & stack_size);
2097
2098 total_size = frame_size + stack_size;
2099 regs_size = ((high - low) + 1) * UNITS_PER_WORD;
2100
2101 /* See if we are unable to use the special stack frame deconstruct and
2102 return instructions. In most cases we can use them, but the exceptions
2103 are:
2104
2105 - Sibling calling functions deconstruct the frame but do not return to
2106 their caller. Instead they branch to their sibling and allow their
2107 return instruction to return to this function's parent.
2108
67e66e16 2109 - Fast and normal interrupt handling functions have to use special
24833e1a 2110 return instructions.
2111
2112 - Functions where we have pushed a fragmented set of registers into the
2113 call-save area must have the same set of registers popped. */
2114 if (is_sibcall
2115 || is_fast_interrupt_func (NULL_TREE)
67e66e16 2116 || is_interrupt_func (NULL_TREE)
24833e1a 2117 || register_mask)
2118 {
2119 /* Cannot use the special instructions - deconstruct by hand. */
2120 if (total_size)
95272799 2121 gen_safe_add (stack_pointer_rtx, stack_pointer_rtx,
2122 GEN_INT (total_size), false);
24833e1a 2123
e4d9e8e5 2124 if (MUST_SAVE_ACC_REGISTER)
24833e1a 2125 {
67e66e16 2126 unsigned int acc_low, acc_high;
2127
2128 /* Reverse the saving of the accumulator register onto the stack.
2129 Note we must adjust the saved "low" accumulator value as it
2130 is really the middle 32-bits of the accumulator. */
2131 if (register_mask)
2132 {
2133 acc_low = acc_high = 0;
9d2f1b03 2134
2135 for (reg = 1; reg < CC_REGNUM; reg ++)
67e66e16 2136 if (register_mask & (1 << reg))
2137 {
2138 if (acc_low == 0)
2139 acc_low = reg;
2140 else
2141 {
2142 acc_high = reg;
2143 break;
2144 }
2145 }
2146 emit_insn (gen_stack_pop (gen_rtx_REG (SImode, acc_high)));
2147 emit_insn (gen_stack_pop (gen_rtx_REG (SImode, acc_low)));
2148 }
2149 else
2150 {
2151 acc_low = low;
2152 acc_high = low + 1;
2153 emit_insn (gen_stack_popm (GEN_INT (2 * UNITS_PER_WORD),
2154 gen_rx_popm_vector (acc_low, acc_high)));
2155 }
2156
2157 emit_insn (gen_ashlsi3 (gen_rtx_REG (SImode, acc_low),
2158 gen_rtx_REG (SImode, acc_low),
2159 GEN_INT (16)));
2160 emit_insn (gen_mvtaclo (gen_rtx_REG (SImode, acc_low)));
2161 emit_insn (gen_mvtachi (gen_rtx_REG (SImode, acc_high)));
2162 }
24833e1a 2163
67e66e16 2164 if (register_mask)
2165 {
9d2f1b03 2166 for (reg = 0; reg < CC_REGNUM; reg ++)
24833e1a 2167 if (register_mask & (1 << reg))
75759166 2168 {
2169 low = high = reg;
2170 while (register_mask & (1 << high))
2171 high ++;
2172 pop_regs (high - 1, low);
2173 reg = high;
2174 }
24833e1a 2175 }
2176 else if (low)
75759166 2177 pop_regs (high, low);
24833e1a 2178
2179 if (is_fast_interrupt_func (NULL_TREE))
61fc50a0 2180 {
2181 gcc_assert (! is_sibcall);
2182 emit_jump_insn (gen_fast_interrupt_return ());
2183 }
67e66e16 2184 else if (is_interrupt_func (NULL_TREE))
61fc50a0 2185 {
2186 gcc_assert (! is_sibcall);
2187 emit_jump_insn (gen_exception_return ());
2188 }
24833e1a 2189 else if (! is_sibcall)
2190 emit_jump_insn (gen_simple_return ());
2191
2192 return;
2193 }
2194
2195 /* If we allocated space on the stack, free it now. */
2196 if (total_size)
2197 {
2198 unsigned HOST_WIDE_INT rtsd_size;
2199
2200 /* See if we can use the RTSD instruction. */
2201 rtsd_size = total_size + regs_size;
2202 if (rtsd_size < 1024 && (rtsd_size % 4) == 0)
2203 {
2204 if (low)
2205 emit_jump_insn (gen_pop_and_return
2206 (GEN_INT (rtsd_size),
2207 gen_rx_rtsd_vector (rtsd_size, low, high)));
2208 else
2209 emit_jump_insn (gen_deallocate_and_return (GEN_INT (total_size)));
2210
2211 return;
2212 }
2213
95272799 2214 gen_safe_add (stack_pointer_rtx, stack_pointer_rtx,
2215 GEN_INT (total_size), false);
24833e1a 2216 }
2217
2218 if (low)
2219 emit_jump_insn (gen_pop_and_return (GEN_INT (regs_size),
2220 gen_rx_rtsd_vector (regs_size,
2221 low, high)));
2222 else
2223 emit_jump_insn (gen_simple_return ());
2224}
2225
2226
2227/* Compute the offset (in words) between FROM (arg pointer
2228 or frame pointer) and TO (frame pointer or stack pointer).
2229 See ASCII art comment at the start of rx_expand_prologue
2230 for more information. */
2231
2232int
2233rx_initial_elimination_offset (int from, int to)
2234{
2235 unsigned int low;
2236 unsigned int high;
2237 unsigned int frame_size;
2238 unsigned int stack_size;
2239 unsigned int mask;
2240
2241 rx_get_stack_layout (& low, & high, & mask, & frame_size, & stack_size);
2242
2243 if (from == ARG_POINTER_REGNUM)
2244 {
2245 /* Extend the computed size of the stack frame to
2246 include the registers pushed in the prologue. */
2247 if (low)
2248 frame_size += ((high - low) + 1) * UNITS_PER_WORD;
2249 else
2250 frame_size += bit_count (mask) * UNITS_PER_WORD;
2251
2252 /* Remember to include the return address. */
2253 frame_size += 1 * UNITS_PER_WORD;
2254
2255 if (to == FRAME_POINTER_REGNUM)
2256 return frame_size;
2257
2258 gcc_assert (to == STACK_POINTER_REGNUM);
2259 return frame_size + stack_size;
2260 }
2261
2262 gcc_assert (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM);
2263 return stack_size;
2264}
2265
24833e1a 2266/* Decide if a variable should go into one of the small data sections. */
2267
2268static bool
2269rx_in_small_data (const_tree decl)
2270{
2271 int size;
738a6bda 2272 const char * section;
24833e1a 2273
2274 if (rx_small_data_limit == 0)
2275 return false;
2276
2277 if (TREE_CODE (decl) != VAR_DECL)
2278 return false;
2279
2280 /* We do not put read-only variables into a small data area because
2281 they would be placed with the other read-only sections, far away
2282 from the read-write data sections, and we only have one small
2283 data area pointer.
2284 Similarly commons are placed in the .bss section which might be
2285 far away (and out of alignment with respect to) the .data section. */
2286 if (TREE_READONLY (decl) || DECL_COMMON (decl))
2287 return false;
2288
2289 section = DECL_SECTION_NAME (decl);
2290 if (section)
738a6bda 2291 return (strcmp (section, "D_2") == 0) || (strcmp (section, "B_2") == 0);
24833e1a 2292
2293 size = int_size_in_bytes (TREE_TYPE (decl));
2294
2295 return (size > 0) && (size <= rx_small_data_limit);
2296}
2297
2298/* Return a section for X.
2299 The only special thing we do here is to honor small data. */
2300
2301static section *
3754d046 2302rx_select_rtx_section (machine_mode mode,
24833e1a 2303 rtx x,
2304 unsigned HOST_WIDE_INT align)
2305{
2306 if (rx_small_data_limit > 0
2307 && GET_MODE_SIZE (mode) <= rx_small_data_limit
2308 && align <= (unsigned HOST_WIDE_INT) rx_small_data_limit * BITS_PER_UNIT)
2309 return sdata_section;
2310
2311 return default_elf_select_rtx_section (mode, x, align);
2312}
2313
2314static section *
2315rx_select_section (tree decl,
2316 int reloc,
2317 unsigned HOST_WIDE_INT align)
2318{
2319 if (rx_small_data_limit > 0)
2320 {
2321 switch (categorize_decl_for_section (decl, reloc))
2322 {
2323 case SECCAT_SDATA: return sdata_section;
2324 case SECCAT_SBSS: return sbss_section;
2325 case SECCAT_SRODATA:
2326 /* Fall through. We do not put small, read only
2327 data into the C_2 section because we are not
2328 using the C_2 section. We do not use the C_2
2329 section because it is located with the other
2330 read-only data sections, far away from the read-write
2331 data sections and we only have one small data
2332 pointer (r13). */
2333 default:
2334 break;
2335 }
2336 }
2337
2338 /* If we are supporting the Renesas assembler
2339 we cannot use mergeable sections. */
2340 if (TARGET_AS100_SYNTAX)
2341 switch (categorize_decl_for_section (decl, reloc))
2342 {
2343 case SECCAT_RODATA_MERGE_CONST:
2344 case SECCAT_RODATA_MERGE_STR_INIT:
2345 case SECCAT_RODATA_MERGE_STR:
2346 return readonly_data_section;
2347
2348 default:
2349 break;
2350 }
2351
2352 return default_elf_select_section (decl, reloc, align);
2353}
2354\f
2355enum rx_builtin
2356{
2357 RX_BUILTIN_BRK,
2358 RX_BUILTIN_CLRPSW,
2359 RX_BUILTIN_INT,
2360 RX_BUILTIN_MACHI,
2361 RX_BUILTIN_MACLO,
2362 RX_BUILTIN_MULHI,
2363 RX_BUILTIN_MULLO,
2364 RX_BUILTIN_MVFACHI,
2365 RX_BUILTIN_MVFACMI,
2366 RX_BUILTIN_MVFC,
2367 RX_BUILTIN_MVTACHI,
2368 RX_BUILTIN_MVTACLO,
2369 RX_BUILTIN_MVTC,
67e66e16 2370 RX_BUILTIN_MVTIPL,
24833e1a 2371 RX_BUILTIN_RACW,
2372 RX_BUILTIN_REVW,
2373 RX_BUILTIN_RMPA,
2374 RX_BUILTIN_ROUND,
24833e1a 2375 RX_BUILTIN_SETPSW,
2376 RX_BUILTIN_WAIT,
2377 RX_BUILTIN_max
2378};
2379
103700c7 2380static GTY(()) tree rx_builtins[(int) RX_BUILTIN_max];
2381
24833e1a 2382static void
2383rx_init_builtins (void)
2384{
dbf38144 2385#define ADD_RX_BUILTIN0(UC_NAME, LC_NAME, RET_TYPE) \
2386 rx_builtins[RX_BUILTIN_##UC_NAME] = \
2387 add_builtin_function ("__builtin_rx_" LC_NAME, \
2388 build_function_type_list (RET_TYPE##_type_node, \
2389 NULL_TREE), \
2390 RX_BUILTIN_##UC_NAME, \
2391 BUILT_IN_MD, NULL, NULL_TREE)
2392
24833e1a 2393#define ADD_RX_BUILTIN1(UC_NAME, LC_NAME, RET_TYPE, ARG_TYPE) \
103700c7 2394 rx_builtins[RX_BUILTIN_##UC_NAME] = \
f7fcec1a 2395 add_builtin_function ("__builtin_rx_" LC_NAME, \
24833e1a 2396 build_function_type_list (RET_TYPE##_type_node, \
2397 ARG_TYPE##_type_node, \
2398 NULL_TREE), \
2399 RX_BUILTIN_##UC_NAME, \
2400 BUILT_IN_MD, NULL, NULL_TREE)
2401
2402#define ADD_RX_BUILTIN2(UC_NAME, LC_NAME, RET_TYPE, ARG_TYPE1, ARG_TYPE2) \
103700c7 2403 rx_builtins[RX_BUILTIN_##UC_NAME] = \
24833e1a 2404 add_builtin_function ("__builtin_rx_" LC_NAME, \
2405 build_function_type_list (RET_TYPE##_type_node, \
2406 ARG_TYPE1##_type_node,\
2407 ARG_TYPE2##_type_node,\
2408 NULL_TREE), \
2409 RX_BUILTIN_##UC_NAME, \
2410 BUILT_IN_MD, NULL, NULL_TREE)
2411
2412#define ADD_RX_BUILTIN3(UC_NAME,LC_NAME,RET_TYPE,ARG_TYPE1,ARG_TYPE2,ARG_TYPE3) \
103700c7 2413 rx_builtins[RX_BUILTIN_##UC_NAME] = \
24833e1a 2414 add_builtin_function ("__builtin_rx_" LC_NAME, \
2415 build_function_type_list (RET_TYPE##_type_node, \
2416 ARG_TYPE1##_type_node,\
2417 ARG_TYPE2##_type_node,\
2418 ARG_TYPE3##_type_node,\
2419 NULL_TREE), \
2420 RX_BUILTIN_##UC_NAME, \
2421 BUILT_IN_MD, NULL, NULL_TREE)
2422
dbf38144 2423 ADD_RX_BUILTIN0 (BRK, "brk", void);
24833e1a 2424 ADD_RX_BUILTIN1 (CLRPSW, "clrpsw", void, integer);
2425 ADD_RX_BUILTIN1 (SETPSW, "setpsw", void, integer);
2426 ADD_RX_BUILTIN1 (INT, "int", void, integer);
2427 ADD_RX_BUILTIN2 (MACHI, "machi", void, intSI, intSI);
2428 ADD_RX_BUILTIN2 (MACLO, "maclo", void, intSI, intSI);
2429 ADD_RX_BUILTIN2 (MULHI, "mulhi", void, intSI, intSI);
2430 ADD_RX_BUILTIN2 (MULLO, "mullo", void, intSI, intSI);
dbf38144 2431 ADD_RX_BUILTIN0 (MVFACHI, "mvfachi", intSI);
2432 ADD_RX_BUILTIN0 (MVFACMI, "mvfacmi", intSI);
24833e1a 2433 ADD_RX_BUILTIN1 (MVTACHI, "mvtachi", void, intSI);
2434 ADD_RX_BUILTIN1 (MVTACLO, "mvtaclo", void, intSI);
dbf38144 2435 ADD_RX_BUILTIN0 (RMPA, "rmpa", void);
24833e1a 2436 ADD_RX_BUILTIN1 (MVFC, "mvfc", intSI, integer);
2437 ADD_RX_BUILTIN2 (MVTC, "mvtc", void, integer, integer);
67e66e16 2438 ADD_RX_BUILTIN1 (MVTIPL, "mvtipl", void, integer);
24833e1a 2439 ADD_RX_BUILTIN1 (RACW, "racw", void, integer);
2440 ADD_RX_BUILTIN1 (ROUND, "round", intSI, float);
2441 ADD_RX_BUILTIN1 (REVW, "revw", intSI, intSI);
dbf38144 2442 ADD_RX_BUILTIN0 (WAIT, "wait", void);
24833e1a 2443}
2444
103700c7 2445/* Return the RX builtin for CODE. */
2446
2447static tree
2448rx_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
2449{
2450 if (code >= RX_BUILTIN_max)
2451 return error_mark_node;
2452
2453 return rx_builtins[code];
2454}
2455
24833e1a 2456static rtx
2457rx_expand_void_builtin_1_arg (rtx arg, rtx (* gen_func)(rtx), bool reg)
2458{
2459 if (reg && ! REG_P (arg))
2460 arg = force_reg (SImode, arg);
2461
2462 emit_insn (gen_func (arg));
2463
2464 return NULL_RTX;
2465}
2466
2467static rtx
2468rx_expand_builtin_mvtc (tree exp)
2469{
2470 rtx arg1 = expand_normal (CALL_EXPR_ARG (exp, 0));
2471 rtx arg2 = expand_normal (CALL_EXPR_ARG (exp, 1));
2472
2473 if (! CONST_INT_P (arg1))
2474 return NULL_RTX;
2475
2476 if (! REG_P (arg2))
2477 arg2 = force_reg (SImode, arg2);
2478
2479 emit_insn (gen_mvtc (arg1, arg2));
2480
2481 return NULL_RTX;
2482}
2483
2484static rtx
2485rx_expand_builtin_mvfc (tree t_arg, rtx target)
2486{
2487 rtx arg = expand_normal (t_arg);
2488
2489 if (! CONST_INT_P (arg))
2490 return NULL_RTX;
2491
e4d9e8e5 2492 if (target == NULL_RTX)
2493 return NULL_RTX;
2494
24833e1a 2495 if (! REG_P (target))
2496 target = force_reg (SImode, target);
2497
2498 emit_insn (gen_mvfc (target, arg));
2499
2500 return target;
2501}
2502
67e66e16 2503static rtx
2504rx_expand_builtin_mvtipl (rtx arg)
2505{
2506 /* The RX610 does not support the MVTIPL instruction. */
2507 if (rx_cpu_type == RX610)
2508 return NULL_RTX;
2509
e5743482 2510 if (! CONST_INT_P (arg) || ! IN_RANGE (INTVAL (arg), 0, (1 << 4) - 1))
67e66e16 2511 return NULL_RTX;
2512
2513 emit_insn (gen_mvtipl (arg));
2514
2515 return NULL_RTX;
2516}
2517
24833e1a 2518static rtx
2519rx_expand_builtin_mac (tree exp, rtx (* gen_func)(rtx, rtx))
2520{
2521 rtx arg1 = expand_normal (CALL_EXPR_ARG (exp, 0));
2522 rtx arg2 = expand_normal (CALL_EXPR_ARG (exp, 1));
2523
2524 if (! REG_P (arg1))
2525 arg1 = force_reg (SImode, arg1);
2526
2527 if (! REG_P (arg2))
2528 arg2 = force_reg (SImode, arg2);
2529
2530 emit_insn (gen_func (arg1, arg2));
2531
2532 return NULL_RTX;
2533}
2534
2535static rtx
2536rx_expand_int_builtin_1_arg (rtx arg,
2537 rtx target,
2538 rtx (* gen_func)(rtx, rtx),
2539 bool mem_ok)
2540{
2541 if (! REG_P (arg))
2542 if (!mem_ok || ! MEM_P (arg))
2543 arg = force_reg (SImode, arg);
2544
2545 if (target == NULL_RTX || ! REG_P (target))
2546 target = gen_reg_rtx (SImode);
2547
2548 emit_insn (gen_func (target, arg));
2549
2550 return target;
2551}
2552
2553static rtx
2554rx_expand_int_builtin_0_arg (rtx target, rtx (* gen_func)(rtx))
2555{
2556 if (target == NULL_RTX || ! REG_P (target))
2557 target = gen_reg_rtx (SImode);
2558
2559 emit_insn (gen_func (target));
2560
2561 return target;
2562}
2563
2564static rtx
2565rx_expand_builtin_round (rtx arg, rtx target)
2566{
2567 if ((! REG_P (arg) && ! MEM_P (arg))
2568 || GET_MODE (arg) != SFmode)
2569 arg = force_reg (SFmode, arg);
2570
2571 if (target == NULL_RTX || ! REG_P (target))
2572 target = gen_reg_rtx (SImode);
2573
2574 emit_insn (gen_lrintsf2 (target, arg));
2575
2576 return target;
2577}
2578
e5743482 2579static int
0318c61a 2580valid_psw_flag (rtx op, const char *which)
e5743482 2581{
2582 static int mvtc_inform_done = 0;
2583
2584 if (GET_CODE (op) == CONST_INT)
2585 switch (INTVAL (op))
2586 {
2587 case 0: case 'c': case 'C':
2588 case 1: case 'z': case 'Z':
2589 case 2: case 's': case 'S':
2590 case 3: case 'o': case 'O':
2591 case 8: case 'i': case 'I':
2592 case 9: case 'u': case 'U':
2593 return 1;
2594 }
2595
2f6d557f 2596 error ("%<__builtin_rx_%s%> takes 'C', 'Z', 'S', 'O', 'I', or 'U'", which);
e5743482 2597 if (!mvtc_inform_done)
2f6d557f 2598 error ("use %<__builtin_rx_mvtc%> (0, ... ) to write arbitrary values to PSW");
e5743482 2599 mvtc_inform_done = 1;
2600
2601 return 0;
2602}
2603
24833e1a 2604static rtx
2605rx_expand_builtin (tree exp,
2606 rtx target,
2607 rtx subtarget ATTRIBUTE_UNUSED,
3754d046 2608 machine_mode mode ATTRIBUTE_UNUSED,
24833e1a 2609 int ignore ATTRIBUTE_UNUSED)
2610{
2611 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
432093e5 2612 tree arg = call_expr_nargs (exp) >= 1 ? CALL_EXPR_ARG (exp, 0) : NULL_TREE;
24833e1a 2613 rtx op = arg ? expand_normal (arg) : NULL_RTX;
2614 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
2615
2616 switch (fcode)
2617 {
2618 case RX_BUILTIN_BRK: emit_insn (gen_brk ()); return NULL_RTX;
e5743482 2619 case RX_BUILTIN_CLRPSW:
2620 if (!valid_psw_flag (op, "clrpsw"))
2621 return NULL_RTX;
2622 return rx_expand_void_builtin_1_arg (op, gen_clrpsw, false);
2623 case RX_BUILTIN_SETPSW:
2624 if (!valid_psw_flag (op, "setpsw"))
2625 return NULL_RTX;
2626 return rx_expand_void_builtin_1_arg (op, gen_setpsw, false);
24833e1a 2627 case RX_BUILTIN_INT: return rx_expand_void_builtin_1_arg
2628 (op, gen_int, false);
2629 case RX_BUILTIN_MACHI: return rx_expand_builtin_mac (exp, gen_machi);
2630 case RX_BUILTIN_MACLO: return rx_expand_builtin_mac (exp, gen_maclo);
2631 case RX_BUILTIN_MULHI: return rx_expand_builtin_mac (exp, gen_mulhi);
2632 case RX_BUILTIN_MULLO: return rx_expand_builtin_mac (exp, gen_mullo);
2633 case RX_BUILTIN_MVFACHI: return rx_expand_int_builtin_0_arg
2634 (target, gen_mvfachi);
2635 case RX_BUILTIN_MVFACMI: return rx_expand_int_builtin_0_arg
2636 (target, gen_mvfacmi);
2637 case RX_BUILTIN_MVTACHI: return rx_expand_void_builtin_1_arg
2638 (op, gen_mvtachi, true);
2639 case RX_BUILTIN_MVTACLO: return rx_expand_void_builtin_1_arg
2640 (op, gen_mvtaclo, true);
6202f892 2641 case RX_BUILTIN_RMPA:
2642 if (rx_allow_string_insns)
2643 emit_insn (gen_rmpa ());
2644 else
2f6d557f 2645 error ("%<-mno-allow-string-insns%> forbids the generation "
2646 "of the RMPA instruction");
6202f892 2647 return NULL_RTX;
24833e1a 2648 case RX_BUILTIN_MVFC: return rx_expand_builtin_mvfc (arg, target);
2649 case RX_BUILTIN_MVTC: return rx_expand_builtin_mvtc (exp);
67e66e16 2650 case RX_BUILTIN_MVTIPL: return rx_expand_builtin_mvtipl (op);
24833e1a 2651 case RX_BUILTIN_RACW: return rx_expand_void_builtin_1_arg
2652 (op, gen_racw, false);
2653 case RX_BUILTIN_ROUND: return rx_expand_builtin_round (op, target);
2654 case RX_BUILTIN_REVW: return rx_expand_int_builtin_1_arg
2655 (op, target, gen_revw, false);
24833e1a 2656 case RX_BUILTIN_WAIT: emit_insn (gen_wait ()); return NULL_RTX;
2657
2658 default:
2659 internal_error ("bad builtin code");
2660 break;
2661 }
2662
2663 return NULL_RTX;
2664}
2665\f
2666/* Place an element into a constructor or destructor section.
2667 Like default_ctor_section_asm_out_constructor in varasm.c
2668 except that it uses .init_array (or .fini_array) and it
2669 handles constructor priorities. */
2670
2671static void
2672rx_elf_asm_cdtor (rtx symbol, int priority, bool is_ctor)
2673{
2674 section * s;
2675
2676 if (priority != DEFAULT_INIT_PRIORITY)
2677 {
2678 char buf[18];
2679
2680 sprintf (buf, "%s.%.5u",
2681 is_ctor ? ".init_array" : ".fini_array",
2682 priority);
2683 s = get_section (buf, SECTION_WRITE, NULL_TREE);
2684 }
2685 else if (is_ctor)
2686 s = ctors_section;
2687 else
2688 s = dtors_section;
2689
2690 switch_to_section (s);
2691 assemble_align (POINTER_SIZE);
2692 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
2693}
2694
2695static void
2696rx_elf_asm_constructor (rtx symbol, int priority)
2697{
2698 rx_elf_asm_cdtor (symbol, priority, /* is_ctor= */true);
2699}
2700
2701static void
2702rx_elf_asm_destructor (rtx symbol, int priority)
2703{
2704 rx_elf_asm_cdtor (symbol, priority, /* is_ctor= */false);
2705}
2706\f
67e66e16 2707/* Check "fast_interrupt", "interrupt" and "naked" attributes. */
24833e1a 2708
2709static tree
2710rx_handle_func_attribute (tree * node,
2711 tree name,
277d3719 2712 tree args ATTRIBUTE_UNUSED,
24833e1a 2713 int flags ATTRIBUTE_UNUSED,
2714 bool * no_add_attrs)
2715{
2716 gcc_assert (DECL_P (* node));
24833e1a 2717
2718 if (TREE_CODE (* node) != FUNCTION_DECL)
2719 {
2720 warning (OPT_Wattributes, "%qE attribute only applies to functions",
2721 name);
2722 * no_add_attrs = true;
2723 }
2724
2725 /* FIXME: We ought to check for conflicting attributes. */
2726
2727 /* FIXME: We ought to check that the interrupt and exception
2728 handler attributes have been applied to void functions. */
2729 return NULL_TREE;
2730}
2731
7ce85a1f 2732/* Check "vector" attribute. */
2733
2734static tree
2735rx_handle_vector_attribute (tree * node,
2736 tree name,
2737 tree args,
2738 int flags ATTRIBUTE_UNUSED,
2739 bool * no_add_attrs)
2740{
2741 gcc_assert (DECL_P (* node));
2742 gcc_assert (args != NULL_TREE);
2743
2744 if (TREE_CODE (* node) != FUNCTION_DECL)
2745 {
2746 warning (OPT_Wattributes, "%qE attribute only applies to functions",
2747 name);
2748 * no_add_attrs = true;
2749 }
2750
2751 return NULL_TREE;
2752}
2753
24833e1a 2754/* Table of RX specific attributes. */
2755const struct attribute_spec rx_attribute_table[] =
2756{
672bc44d 2757 /* Name, min_len, max_len, decl_req, type_req, fn_type_req,
2758 affects_type_identity, handler, exclude. */
2759 { "fast_interrupt", 0, 0, true, false, false, false,
2760 rx_handle_func_attribute, NULL },
2761 { "interrupt", 0, -1, true, false, false, false,
2762 rx_handle_func_attribute, NULL },
2763 { "naked", 0, 0, true, false, false, false,
2764 rx_handle_func_attribute, NULL },
2765 { "vector", 1, -1, true, false, false, false,
2766 rx_handle_vector_attribute, NULL },
2767 { NULL, 0, 0, false, false, false, false, NULL, NULL }
24833e1a 2768};
2769
42d89991 2770/* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
02e53c17 2771
2772static void
42d89991 2773rx_override_options_after_change (void)
98cb9b5b 2774{
2775 static bool first_time = TRUE;
98cb9b5b 2776
2777 if (first_time)
2778 {
2779 /* If this is the first time through and the user has not disabled
42d89991 2780 the use of RX FPU hardware then enable -ffinite-math-only,
2781 since the FPU instructions do not support NaNs and infinities. */
98cb9b5b 2782 if (TARGET_USE_FPU)
42d89991 2783 flag_finite_math_only = 1;
98cb9b5b 2784
98cb9b5b 2785 first_time = FALSE;
2786 }
2787 else
2788 {
2789 /* Alert the user if they are changing the optimization options
2790 to use IEEE compliant floating point arithmetic with RX FPU insns. */
2791 if (TARGET_USE_FPU
42d89991 2792 && !flag_finite_math_only)
2793 warning (0, "RX FPU instructions do not support NaNs and infinities");
98cb9b5b 2794 }
2795}
2796
1af17d44 2797static void
2798rx_option_override (void)
2799{
8cb00d70 2800 unsigned int i;
2801 cl_deferred_option *opt;
f1f41a6c 2802 vec<cl_deferred_option> *v = (vec<cl_deferred_option> *) rx_deferred_options;
8cb00d70 2803
f1f41a6c 2804 if (v)
2805 FOR_EACH_VEC_ELT (*v, i, opt)
2806 {
2807 switch (opt->opt_index)
2808 {
2809 case OPT_mint_register_:
2810 switch (opt->value)
2811 {
2812 case 4:
2813 fixed_regs[10] = call_used_regs [10] = 1;
2814 /* Fall through. */
2815 case 3:
2816 fixed_regs[11] = call_used_regs [11] = 1;
2817 /* Fall through. */
2818 case 2:
2819 fixed_regs[12] = call_used_regs [12] = 1;
2820 /* Fall through. */
2821 case 1:
2822 fixed_regs[13] = call_used_regs [13] = 1;
2823 /* Fall through. */
2824 case 0:
2825 rx_num_interrupt_regs = opt->value;
2826 break;
2827 default:
2828 rx_num_interrupt_regs = 0;
2829 /* Error message already given because rx_handle_option
2830 returned false. */
2831 break;
2832 }
2833 break;
8cb00d70 2834
f1f41a6c 2835 default:
2836 gcc_unreachable ();
2837 }
2838 }
8cb00d70 2839
1af17d44 2840 /* This target defaults to strict volatile bitfields. */
941a2396 2841 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
1af17d44 2842 flag_strict_volatile_bitfields = 1;
42d89991 2843
2844 rx_override_options_after_change ();
9f9a3b39 2845
5005fc53 2846 /* These values are bytes, not log. */
6848a0ae 2847 if (! optimize_size)
2848 {
2849 if (flag_align_jumps && !str_align_jumps)
2850 str_align_jumps = ((rx_cpu_type == RX100
2851 || rx_cpu_type == RX200) ? "4" : "8");
2852 if (flag_align_loops && !str_align_loops)
2853 str_align_loops = ((rx_cpu_type == RX100
2854 || rx_cpu_type == RX200) ? "4" : "8");
2855 if (flag_align_labels && !str_align_labels)
2856 str_align_labels = ((rx_cpu_type == RX100
2857 || rx_cpu_type == RX200) ? "4" : "8");
2858 }
1af17d44 2859}
2860
98cb9b5b 2861\f
24833e1a 2862static bool
2863rx_allocate_stack_slots_for_args (void)
2864{
2865 /* Naked functions should not allocate stack slots for arguments. */
2866 return ! is_naked_func (NULL_TREE);
2867}
2868
2869static bool
2870rx_func_attr_inlinable (const_tree decl)
2871{
2872 return ! is_fast_interrupt_func (decl)
67e66e16 2873 && ! is_interrupt_func (decl)
24833e1a 2874 && ! is_naked_func (decl);
2875}
2876
08c6cbd2 2877static bool
2878rx_warn_func_return (tree decl)
2879{
2880 /* Naked functions are implemented entirely in assembly, including the
2881 return sequence, so suppress warnings about this. */
2882 return !is_naked_func (decl);
2883}
2884
61fc50a0 2885/* Return nonzero if it is ok to make a tail-call to DECL,
2886 a function_decl or NULL if this is an indirect call, using EXP */
2887
2888static bool
e4d9e8e5 2889rx_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
61fc50a0 2890{
8b95d2d2 2891 if (TARGET_JSR)
2892 return false;
2893
61fc50a0 2894 /* Do not allow indirect tailcalls. The
2895 sibcall patterns do not support them. */
2896 if (decl == NULL)
2897 return false;
2898
2899 /* Never tailcall from inside interrupt handlers or naked functions. */
2900 if (is_fast_interrupt_func (NULL_TREE)
2901 || is_interrupt_func (NULL_TREE)
2902 || is_naked_func (NULL_TREE))
2903 return false;
2904
2905 return true;
2906}
2907
24833e1a 2908static void
2909rx_file_start (void)
2910{
2911 if (! TARGET_AS100_SYNTAX)
2912 default_file_start ();
2913}
2914
2915static bool
2916rx_is_ms_bitfield_layout (const_tree record_type ATTRIBUTE_UNUSED)
2917{
67cf9b55 2918 /* The packed attribute overrides the MS behavior. */
c6347c7a 2919 return ! TYPE_PACKED (record_type);
24833e1a 2920}
24833e1a 2921\f
2922/* Returns true if X a legitimate constant for an immediate
2923 operand on the RX. X is already known to satisfy CONSTANT_P. */
2924
2925bool
3754d046 2926rx_is_legitimate_constant (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
24833e1a 2927{
24833e1a 2928 switch (GET_CODE (x))
2929 {
2930 case CONST:
2931 x = XEXP (x, 0);
2932
2933 if (GET_CODE (x) == PLUS)
2934 {
2935 if (! CONST_INT_P (XEXP (x, 1)))
2936 return false;
2937
2938 /* GCC would not pass us CONST_INT + CONST_INT so we
2939 know that we have {SYMBOL|LABEL} + CONST_INT. */
2940 x = XEXP (x, 0);
2941 gcc_assert (! CONST_INT_P (x));
2942 }
2943
2944 switch (GET_CODE (x))
2945 {
2946 case LABEL_REF:
2947 case SYMBOL_REF:
2948 return true;
2949
95272799 2950 case UNSPEC:
6e507301 2951 return XINT (x, 1) == UNSPEC_CONST || XINT (x, 1) == UNSPEC_PID_ADDR;
95272799 2952
24833e1a 2953 default:
2954 /* FIXME: Can this ever happen ? */
776f1390 2955 gcc_unreachable ();
24833e1a 2956 }
2957 break;
2958
2959 case LABEL_REF:
2960 case SYMBOL_REF:
2961 return true;
2962 case CONST_DOUBLE:
09bb92cc 2963 return (rx_max_constant_size == 0 || rx_max_constant_size == 4);
24833e1a 2964 case CONST_VECTOR:
2965 return false;
2966 default:
2967 gcc_assert (CONST_INT_P (x));
2968 break;
2969 }
2970
95272799 2971 return ok_for_max_constant (INTVAL (x));
24833e1a 2972}
2973
24833e1a 2974static int
3754d046 2975rx_address_cost (rtx addr, machine_mode mode ATTRIBUTE_UNUSED,
d9c5e5f4 2976 addr_space_t as ATTRIBUTE_UNUSED, bool speed)
24833e1a 2977{
2978 rtx a, b;
2979
2980 if (GET_CODE (addr) != PLUS)
2981 return COSTS_N_INSNS (1);
2982
2983 a = XEXP (addr, 0);
2984 b = XEXP (addr, 1);
2985
2986 if (REG_P (a) && REG_P (b))
2987 /* Try to discourage REG+REG addressing as it keeps two registers live. */
2988 return COSTS_N_INSNS (4);
2989
2990 if (speed)
2991 /* [REG+OFF] is just as fast as [REG]. */
2992 return COSTS_N_INSNS (1);
2993
2994 if (CONST_INT_P (b)
2995 && ((INTVAL (b) > 128) || INTVAL (b) < -127))
2996 /* Try to discourage REG + <large OFF> when optimizing for size. */
2997 return COSTS_N_INSNS (2);
2998
2999 return COSTS_N_INSNS (1);
3000}
3001
e3b0bc49 3002static bool
3003rx_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
3004 int opno ATTRIBUTE_UNUSED, int* total, bool speed)
3005{
3006 if (x == const0_rtx)
3007 {
3008 *total = 0;
3009 return true;
3010 }
3011
3012 switch (GET_CODE (x))
3013 {
3014 case MULT:
3015 if (mode == DImode)
3016 {
3017 *total = COSTS_N_INSNS (2);
3018 return true;
3019 }
3020 /* fall through */
3021
3022 case PLUS:
3023 case MINUS:
3024 case AND:
3025 case COMPARE:
3026 case IOR:
3027 case XOR:
3028 *total = COSTS_N_INSNS (1);
3029 return true;
3030
3031 case DIV:
3032 if (speed)
3033 /* This is the worst case for a division. Pessimize divisions when
3034 not optimizing for size and allow reciprocal optimizations which
3035 produce bigger code. */
3036 *total = COSTS_N_INSNS (20);
3037 else
3038 *total = COSTS_N_INSNS (3);
3039 return true;
3040
3041 case UDIV:
3042 if (speed)
3043 /* This is the worst case for a division. Pessimize divisions when
3044 not optimizing for size and allow reciprocal optimizations which
3045 produce bigger code. */
3046 *total = COSTS_N_INSNS (18);
3047 else
3048 *total = COSTS_N_INSNS (3);
3049 return true;
3050
3051 default:
3052 break;
3053 }
3054
3055 return false;
3056}
3057
24833e1a 3058static bool
3059rx_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
3060{
3061 /* We can always eliminate to the frame pointer.
3062 We can eliminate to the stack pointer unless a frame
3063 pointer is needed. */
3064
3065 return to == FRAME_POINTER_REGNUM
3066 || ( to == STACK_POINTER_REGNUM && ! frame_pointer_needed);
3067}
3068\f
3069
3070static void
3071rx_trampoline_template (FILE * file)
3072{
3073 /* Output assembler code for a block containing the constant
3074 part of a trampoline, leaving space for the variable parts.
3075
3076 On the RX, (where r8 is the static chain regnum) the trampoline
3077 looks like:
3078
3079 mov #<static chain value>, r8
3080 mov #<function's address>, r9
3081 jmp r9
3082
3083 In big-endian-data-mode however instructions are read into the CPU
3084 4 bytes at a time. These bytes are then swapped around before being
3085 passed to the decoder. So...we must partition our trampoline into
3086 4 byte packets and swap these packets around so that the instruction
3087 reader will reverse the process. But, in order to avoid splitting
3088 the 32-bit constants across these packet boundaries, (making inserting
3089 them into the constructed trampoline very difficult) we have to pad the
3090 instruction sequence with NOP insns. ie:
3091
3092 nop
3093 nop
3094 mov.l #<...>, r8
3095 nop
3096 nop
3097 mov.l #<...>, r9
3098 jmp r9
3099 nop
3100 nop */
3101
3102 if (! TARGET_BIG_ENDIAN_DATA)
3103 {
3104 asm_fprintf (file, "\tmov.L\t#0deadbeefH, r%d\n", STATIC_CHAIN_REGNUM);
3105 asm_fprintf (file, "\tmov.L\t#0deadbeefH, r%d\n", TRAMPOLINE_TEMP_REGNUM);
3106 asm_fprintf (file, "\tjmp\tr%d\n", TRAMPOLINE_TEMP_REGNUM);
3107 }
3108 else
3109 {
3110 char r8 = '0' + STATIC_CHAIN_REGNUM;
3111 char r9 = '0' + TRAMPOLINE_TEMP_REGNUM;
3112
3113 if (TARGET_AS100_SYNTAX)
3114 {
3115 asm_fprintf (file, "\t.BYTE 0%c2H, 0fbH, 003H, 003H\n", r8);
3116 asm_fprintf (file, "\t.BYTE 0deH, 0adH, 0beH, 0efH\n");
3117 asm_fprintf (file, "\t.BYTE 0%c2H, 0fbH, 003H, 003H\n", r9);
3118 asm_fprintf (file, "\t.BYTE 0deH, 0adH, 0beH, 0efH\n");
3119 asm_fprintf (file, "\t.BYTE 003H, 003H, 00%cH, 07fH\n", r9);
3120 }
3121 else
3122 {
3123 asm_fprintf (file, "\t.byte 0x%c2, 0xfb, 0x03, 0x03\n", r8);
3124 asm_fprintf (file, "\t.byte 0xde, 0xad, 0xbe, 0xef\n");
3125 asm_fprintf (file, "\t.byte 0x%c2, 0xfb, 0x03, 0x03\n", r9);
3126 asm_fprintf (file, "\t.byte 0xde, 0xad, 0xbe, 0xef\n");
3127 asm_fprintf (file, "\t.byte 0x03, 0x03, 0x0%c, 0x7f\n", r9);
3128 }
3129 }
3130}
3131
3132static void
3133rx_trampoline_init (rtx tramp, tree fndecl, rtx chain)
3134{
3135 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
3136
3137 emit_block_move (tramp, assemble_trampoline_template (),
3138 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
3139
3140 if (TARGET_BIG_ENDIAN_DATA)
3141 {
3142 emit_move_insn (adjust_address (tramp, SImode, 4), chain);
3143 emit_move_insn (adjust_address (tramp, SImode, 12), fnaddr);
3144 }
3145 else
3146 {
3147 emit_move_insn (adjust_address (tramp, SImode, 2), chain);
3148 emit_move_insn (adjust_address (tramp, SImode, 6 + 2), fnaddr);
3149 }
3150}
3151\f
ccfccd66 3152static int
3754d046 3153rx_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
3e8d9684 3154 reg_class_t regclass ATTRIBUTE_UNUSED,
3155 bool in)
9d2f1b03 3156{
6145a46d 3157 return (in ? 2 : 0) + REGISTER_MOVE_COST (mode, regclass, regclass);
9d2f1b03 3158}
3159
ccfccd66 3160/* Convert a CC_MODE to the set of flags that it represents. */
9d2f1b03 3161
3162static unsigned int
3754d046 3163flags_from_mode (machine_mode mode)
9d2f1b03 3164{
ccfccd66 3165 switch (mode)
9d2f1b03 3166 {
916ace94 3167 case E_CC_ZSmode:
ccfccd66 3168 return CC_FLAG_S | CC_FLAG_Z;
916ace94 3169 case E_CC_ZSOmode:
ccfccd66 3170 return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O;
916ace94 3171 case E_CC_ZSCmode:
ccfccd66 3172 return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_C;
916ace94 3173 case E_CCmode:
ccfccd66 3174 return CC_FLAG_S | CC_FLAG_Z | CC_FLAG_O | CC_FLAG_C;
916ace94 3175 case E_CC_Fmode:
ccfccd66 3176 return CC_FLAG_FP;
3177 default:
3178 gcc_unreachable ();
3179 }
3180}
9d2f1b03 3181
ccfccd66 3182/* Convert a set of flags to a CC_MODE that can implement it. */
9d2f1b03 3183
3754d046 3184static machine_mode
ccfccd66 3185mode_from_flags (unsigned int f)
3186{
3187 if (f & CC_FLAG_FP)
3188 return CC_Fmode;
3189 if (f & CC_FLAG_O)
3190 {
3191 if (f & CC_FLAG_C)
3192 return CCmode;
3193 else
3194 return CC_ZSOmode;
9d2f1b03 3195 }
ccfccd66 3196 else if (f & CC_FLAG_C)
3197 return CC_ZSCmode;
3198 else
3199 return CC_ZSmode;
9d2f1b03 3200}
3201
ccfccd66 3202/* Convert an RTX_CODE to the set of flags needed to implement it.
3203 This assumes an integer comparison. */
3204
9d2f1b03 3205static unsigned int
ccfccd66 3206flags_from_code (enum rtx_code code)
9d2f1b03 3207{
ccfccd66 3208 switch (code)
9d2f1b03 3209 {
ccfccd66 3210 case LT:
3211 case GE:
24ad6c43 3212 return CC_FLAG_S;
ccfccd66 3213 case GT:
3214 case LE:
3215 return CC_FLAG_S | CC_FLAG_O | CC_FLAG_Z;
3216 case GEU:
3217 case LTU:
3218 return CC_FLAG_C;
3219 case GTU:
3220 case LEU:
3221 return CC_FLAG_C | CC_FLAG_Z;
3222 case EQ:
3223 case NE:
3224 return CC_FLAG_Z;
3225 default:
3226 gcc_unreachable ();
9d2f1b03 3227 }
3228}
3229
ccfccd66 3230/* Return a CC_MODE of which both M1 and M2 are subsets. */
3231
3754d046 3232static machine_mode
3233rx_cc_modes_compatible (machine_mode m1, machine_mode m2)
9d2f1b03 3234{
ccfccd66 3235 unsigned f;
3236
3237 /* Early out for identical modes. */
3238 if (m1 == m2)
3239 return m1;
3240
3241 /* There's no valid combination for FP vs non-FP. */
3242 f = flags_from_mode (m1) | flags_from_mode (m2);
3243 if (f & CC_FLAG_FP)
3244 return VOIDmode;
3245
3246 /* Otherwise, see what mode can implement all the flags. */
3247 return mode_from_flags (f);
9d2f1b03 3248}
8b8777b9 3249
3250/* Return the minimal CC mode needed to implement (CMP_CODE X Y). */
3251
3754d046 3252machine_mode
24ad6c43 3253rx_select_cc_mode (enum rtx_code cmp_code, rtx x, rtx y)
8b8777b9 3254{
3255 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3256 return CC_Fmode;
3257
24ad6c43 3258 if (y != const0_rtx)
3259 return CCmode;
3260
ccfccd66 3261 return mode_from_flags (flags_from_code (cmp_code));
3262}
3263
ccfccd66 3264/* Split the conditional branch. Emit (COMPARE C1 C2) into CC_REG with
3265 CC_MODE, and use that in branches based on that compare. */
3266
3267void
3754d046 3268rx_split_cbranch (machine_mode cc_mode, enum rtx_code cmp1,
ccfccd66 3269 rtx c1, rtx c2, rtx label)
3270{
3271 rtx flags, x;
3272
3273 flags = gen_rtx_REG (cc_mode, CC_REG);
3274 x = gen_rtx_COMPARE (cc_mode, c1, c2);
d1f9b275 3275 x = gen_rtx_SET (flags, x);
ccfccd66 3276 emit_insn (x);
3277
3278 x = gen_rtx_fmt_ee (cmp1, VOIDmode, flags, const0_rtx);
3279 x = gen_rtx_IF_THEN_ELSE (VOIDmode, x, label, pc_rtx);
d1f9b275 3280 x = gen_rtx_SET (pc_rtx, x);
ccfccd66 3281 emit_jump_insn (x);
8b8777b9 3282}
3283
fc3b02a9 3284/* A helper function for matching parallels that set the flags. */
3285
3286bool
3754d046 3287rx_match_ccmode (rtx insn, machine_mode cc_mode)
fc3b02a9 3288{
3289 rtx op1, flags;
3754d046 3290 machine_mode flags_mode;
fc3b02a9 3291
3292 gcc_checking_assert (XVECLEN (PATTERN (insn), 0) == 2);
3293
e3b93558 3294 op1 = XVECEXP (PATTERN (insn), 0, 0);
fc3b02a9 3295 gcc_checking_assert (GET_CODE (SET_SRC (op1)) == COMPARE);
3296
3297 flags = SET_DEST (op1);
3298 flags_mode = GET_MODE (flags);
3299
3300 if (GET_MODE (SET_SRC (op1)) != flags_mode)
3301 return false;
3302 if (GET_MODE_CLASS (flags_mode) != MODE_CC)
3303 return false;
3304
3305 /* Ensure that the mode of FLAGS is compatible with CC_MODE. */
3306 if (flags_from_mode (flags_mode) & ~flags_from_mode (cc_mode))
3307 return false;
3308
3309 return true;
3310}
9f9a3b39 3311\f
9f9a3b39 3312
3313static int
695d0571 3314rx_max_skip_for_label (rtx_insn *lab)
9f9a3b39 3315{
3316 int opsize;
695d0571 3317 rtx_insn *op;
9f9a3b39 3318
e6cf07b2 3319 if (optimize_size)
3320 return 0;
3321
695d0571 3322 if (lab == NULL)
9f9a3b39 3323 return 0;
fc3b02a9 3324
9f9a3b39 3325 op = lab;
3326 do
3327 {
3328 op = next_nonnote_nondebug_insn (op);
3329 }
3330 while (op && (LABEL_P (op)
3331 || (INSN_P (op) && GET_CODE (PATTERN (op)) == USE)));
3332 if (!op)
3333 return 0;
3334
3335 opsize = get_attr_length (op);
3336 if (opsize >= 0 && opsize < 8)
6fceef7a 3337 return MAX (0, opsize - 1);
9f9a3b39 3338 return 0;
3339}
776f1390 3340
6fceef7a 3341static int
3342rx_align_log_for_label (rtx_insn *lab, int uses_threshold)
3343{
3344 /* This is a simple heuristic to guess when an alignment would not be useful
3345 because the delay due to the inserted NOPs would be greater than the delay
3346 due to the misaligned branch. If uses_threshold is zero then the alignment
3347 is always useful. */
3348 if (LABEL_P (lab) && LABEL_NUSES (lab) < uses_threshold)
3349 return 0;
3350
3351 if (optimize_size)
3352 return 0;
3353
3354 /* Return zero if max_skip not a positive number. */
3355 int max_skip = rx_max_skip_for_label (lab);
3356 if (max_skip <= 0)
3357 return 0;
3358
3359 /* These values are log, not bytes. */
3360 if (rx_cpu_type == RX100 || rx_cpu_type == RX200)
3361 return 2; /* 4 bytes */
3362 return 3; /* 8 bytes */
3363}
3364
3365align_flags
3366rx_align_for_label (rtx_insn *lab, int uses_threshold)
3367{
3368 return align_flags (rx_align_log_for_label (lab, uses_threshold),
3369 rx_max_skip_for_label (lab));
3370}
3371
776f1390 3372/* Compute the real length of the extending load-and-op instructions. */
3373
3374int
fd535fc1 3375rx_adjust_insn_length (rtx_insn *insn, int current_length)
776f1390 3376{
3377 rtx extend, mem, offset;
3378 bool zero;
3379 int factor;
3380
7ce85a1f 3381 if (!INSN_P (insn))
3382 return current_length;
3383
776f1390 3384 switch (INSN_CODE (insn))
3385 {
3386 default:
3387 return current_length;
3388
3389 case CODE_FOR_plussi3_zero_extendhi:
3390 case CODE_FOR_andsi3_zero_extendhi:
3391 case CODE_FOR_iorsi3_zero_extendhi:
3392 case CODE_FOR_xorsi3_zero_extendhi:
3393 case CODE_FOR_divsi3_zero_extendhi:
3394 case CODE_FOR_udivsi3_zero_extendhi:
3395 case CODE_FOR_minussi3_zero_extendhi:
3396 case CODE_FOR_smaxsi3_zero_extendhi:
3397 case CODE_FOR_sminsi3_zero_extendhi:
3398 case CODE_FOR_multsi3_zero_extendhi:
f7fcec1a 3399 case CODE_FOR_comparesi3_zero_extendhi:
776f1390 3400 zero = true;
3401 factor = 2;
3402 break;
3403
3404 case CODE_FOR_plussi3_sign_extendhi:
3405 case CODE_FOR_andsi3_sign_extendhi:
3406 case CODE_FOR_iorsi3_sign_extendhi:
3407 case CODE_FOR_xorsi3_sign_extendhi:
3408 case CODE_FOR_divsi3_sign_extendhi:
3409 case CODE_FOR_udivsi3_sign_extendhi:
3410 case CODE_FOR_minussi3_sign_extendhi:
3411 case CODE_FOR_smaxsi3_sign_extendhi:
3412 case CODE_FOR_sminsi3_sign_extendhi:
3413 case CODE_FOR_multsi3_sign_extendhi:
f7fcec1a 3414 case CODE_FOR_comparesi3_sign_extendhi:
776f1390 3415 zero = false;
3416 factor = 2;
3417 break;
3418
3419 case CODE_FOR_plussi3_zero_extendqi:
3420 case CODE_FOR_andsi3_zero_extendqi:
3421 case CODE_FOR_iorsi3_zero_extendqi:
3422 case CODE_FOR_xorsi3_zero_extendqi:
3423 case CODE_FOR_divsi3_zero_extendqi:
3424 case CODE_FOR_udivsi3_zero_extendqi:
3425 case CODE_FOR_minussi3_zero_extendqi:
3426 case CODE_FOR_smaxsi3_zero_extendqi:
3427 case CODE_FOR_sminsi3_zero_extendqi:
3428 case CODE_FOR_multsi3_zero_extendqi:
f7fcec1a 3429 case CODE_FOR_comparesi3_zero_extendqi:
776f1390 3430 zero = true;
3431 factor = 1;
3432 break;
3433
3434 case CODE_FOR_plussi3_sign_extendqi:
3435 case CODE_FOR_andsi3_sign_extendqi:
3436 case CODE_FOR_iorsi3_sign_extendqi:
3437 case CODE_FOR_xorsi3_sign_extendqi:
3438 case CODE_FOR_divsi3_sign_extendqi:
3439 case CODE_FOR_udivsi3_sign_extendqi:
3440 case CODE_FOR_minussi3_sign_extendqi:
3441 case CODE_FOR_smaxsi3_sign_extendqi:
3442 case CODE_FOR_sminsi3_sign_extendqi:
3443 case CODE_FOR_multsi3_sign_extendqi:
f7fcec1a 3444 case CODE_FOR_comparesi3_sign_extendqi:
776f1390 3445 zero = false;
3446 factor = 1;
3447 break;
3448 }
3449
3450 /* We are expecting: (SET (REG) (<OP> (REG) (<EXTEND> (MEM)))). */
3451 extend = single_set (insn);
3452 gcc_assert (extend != NULL_RTX);
3453
3454 extend = SET_SRC (extend);
3455 if (GET_CODE (XEXP (extend, 0)) == ZERO_EXTEND
3456 || GET_CODE (XEXP (extend, 0)) == SIGN_EXTEND)
3457 extend = XEXP (extend, 0);
3458 else
3459 extend = XEXP (extend, 1);
3460
3461 gcc_assert ((zero && (GET_CODE (extend) == ZERO_EXTEND))
3462 || (! zero && (GET_CODE (extend) == SIGN_EXTEND)));
3463
3464 mem = XEXP (extend, 0);
3465 gcc_checking_assert (MEM_P (mem));
3466 if (REG_P (XEXP (mem, 0)))
3467 return (zero && factor == 1) ? 2 : 3;
3468
3469 /* We are expecting: (MEM (PLUS (REG) (CONST_INT))). */
3470 gcc_checking_assert (GET_CODE (XEXP (mem, 0)) == PLUS);
3471 gcc_checking_assert (REG_P (XEXP (XEXP (mem, 0), 0)));
3472
3473 offset = XEXP (XEXP (mem, 0), 1);
3474 gcc_checking_assert (GET_CODE (offset) == CONST_INT);
3475
3476 if (IN_RANGE (INTVAL (offset), 0, 255 * factor))
3477 return (zero && factor == 1) ? 3 : 4;
3478
3479 return (zero && factor == 1) ? 4 : 5;
3480}
ee1401ac 3481
3482static bool
3483rx_narrow_volatile_bitfield (void)
3484{
3485 return true;
3486}
3487
3488static bool
3489rx_ok_to_inline (tree caller, tree callee)
3490{
3491 /* Do not inline functions with local variables
3492 into a naked CALLER - naked function have no stack frame and
3493 locals need a frame in order to have somewhere to live.
3494
3495 Unfortunately we have no way to determine the presence of
3496 local variables in CALLEE, so we have to be cautious and
3497 assume that there might be some there.
3498
3499 We do allow inlining when CALLEE has the "inline" type
3500 modifier or the "always_inline" or "gnu_inline" attributes. */
3501 return lookup_attribute ("naked", DECL_ATTRIBUTES (caller)) == NULL_TREE
3502 || DECL_DECLARED_INLINE_P (callee)
3503 || lookup_attribute ("always_inline", DECL_ATTRIBUTES (callee)) != NULL_TREE
3504 || lookup_attribute ("gnu_inline", DECL_ATTRIBUTES (callee)) != NULL_TREE;
3505}
3506
f0964309 3507static bool
3508rx_enable_lra (void)
3509{
734bbdc0 3510 return TARGET_ENABLE_LRA;
f0964309 3511}
3512
140a4ed4 3513rx_atomic_sequence::rx_atomic_sequence (const_tree fun_decl)
3514{
3515 if (is_fast_interrupt_func (fun_decl) || is_interrupt_func (fun_decl))
3516 {
3517 /* If we are inside an interrupt handler, assume that interrupts are
3518 off -- which is the default hardware behavior. In this case, there
3519 is no need to disable the interrupts. */
3520 m_prev_psw_reg = NULL;
3521 }
3522 else
3523 {
3524 m_prev_psw_reg = gen_reg_rtx (SImode);
3525 emit_insn (gen_mvfc (m_prev_psw_reg, GEN_INT (CTRLREG_PSW)));
3526 emit_insn (gen_clrpsw (GEN_INT ('I')));
3527 }
3528}
3529
3530rx_atomic_sequence::~rx_atomic_sequence (void)
3531{
3532 if (m_prev_psw_reg != NULL)
3533 emit_insn (gen_mvtc (GEN_INT (CTRLREG_PSW), m_prev_psw_reg));
3534}
3535
504e193c 3536/* Given an insn and a reg number, tell whether the reg dies or is unused
3537 after the insn. */
3538bool
3539rx_reg_dead_or_unused_after_insn (const rtx_insn* i, int regno)
3540{
3541 return find_regno_note (i, REG_DEAD, regno) != NULL
3542 || find_regno_note (i, REG_UNUSED, regno) != NULL;
3543}
3544
3545/* Copy dead and unused notes from SRC to DST for the specified REGNO. */
3546void
3547rx_copy_reg_dead_or_unused_notes (rtx reg, const rtx_insn* src, rtx_insn* dst)
3548{
3549 int regno = REGNO (SUBREG_P (reg) ? SUBREG_REG (reg) : reg);
3550
3551 if (rtx note = find_regno_note (src, REG_DEAD, regno))
3552 add_shallow_copy_of_reg_note (dst, note);
3553
3554 if (rtx note = find_regno_note (src, REG_UNUSED, regno))
3555 add_shallow_copy_of_reg_note (dst, note);
3556}
3557
3558/* Try to fuse the current bit-operation insn with the surrounding memory load
3559 and store. */
3560bool
3561rx_fuse_in_memory_bitop (rtx* operands, rtx_insn* curr_insn,
3562 rtx (*gen_insn)(rtx, rtx))
3563{
3564 rtx op2_reg = SUBREG_P (operands[2]) ? SUBREG_REG (operands[2]) : operands[2];
3565
3566 set_of_reg op2_def = rx_find_set_of_reg (op2_reg, curr_insn,
3567 prev_nonnote_nondebug_insn_bb);
3568 if (op2_def.set_src == NULL_RTX
3569 || !MEM_P (op2_def.set_src)
3570 || GET_MODE (op2_def.set_src) != QImode
3571 || !rx_is_restricted_memory_address (XEXP (op2_def.set_src, 0),
3572 GET_MODE (op2_def.set_src))
3573 || reg_used_between_p (operands[2], op2_def.insn, curr_insn)
3574 || !rx_reg_dead_or_unused_after_insn (curr_insn, REGNO (op2_reg))
3575 )
3576 return false;
3577
3578 /* The register operand originates from a memory load and the memory load
3579 could be fused with the bitop insn.
3580 Look for the following memory store with the same memory operand. */
3581 rtx mem = op2_def.set_src;
3582
3583 /* If the memory is an auto-mod address, it can't be fused. */
3584 if (GET_CODE (XEXP (mem, 0)) == POST_INC
3585 || GET_CODE (XEXP (mem, 0)) == PRE_INC
3586 || GET_CODE (XEXP (mem, 0)) == POST_DEC
3587 || GET_CODE (XEXP (mem, 0)) == PRE_DEC)
3588 return false;
3589
3590 rtx_insn* op0_use = rx_find_use_of_reg (operands[0], curr_insn,
3591 next_nonnote_nondebug_insn_bb);
3592 if (op0_use == NULL
3593 || !(GET_CODE (PATTERN (op0_use)) == SET
3594 && RX_REG_P (XEXP (PATTERN (op0_use), 1))
3595 && reg_overlap_mentioned_p (operands[0], XEXP (PATTERN (op0_use), 1))
3596 && rtx_equal_p (mem, XEXP (PATTERN (op0_use), 0)))
3597 || !rx_reg_dead_or_unused_after_insn (op0_use, REGNO (operands[0]))
3598 || reg_set_between_p (operands[2], curr_insn, op0_use))
3599 return false;
3600
3601 /* If the load-modify-store operation is fused it could potentially modify
3602 load/store ordering if there are other memory accesses between the load
3603 and the store for this insn. If there are volatile mems between the load
3604 and store it's better not to change the ordering. If there is a call
3605 between the load and store, it's also not safe to fuse it. */
3606 for (rtx_insn* i = next_nonnote_nondebug_insn_bb (op2_def.insn);
3607 i != NULL && i != op0_use;
3608 i = next_nonnote_nondebug_insn_bb (i))
3609 if (volatile_insn_p (PATTERN (i)) || CALL_P (i))
3610 return false;
3611
5a73d351 3612 emit_insn (gen_insn (mem, gen_lowpart (QImode, operands[1])));
504e193c 3613 set_insn_deleted (op2_def.insn);
3614 set_insn_deleted (op0_use);
3615 return true;
3616}
3617
74f68e49 3618/* Implement TARGET_HARD_REGNO_NREGS. */
3619
3620static unsigned int
3621rx_hard_regno_nregs (unsigned int, machine_mode mode)
3622{
3623 return CLASS_MAX_NREGS (0, mode);
3624}
3625
b395382f 3626/* Implement TARGET_HARD_REGNO_MODE_OK. */
3627
3628static bool
3629rx_hard_regno_mode_ok (unsigned int regno, machine_mode)
3630{
3631 return REGNO_REG_CLASS (regno) == GR_REGS;
3632}
5f6dcf1a 3633
3634/* Implement TARGET_MODES_TIEABLE_P. */
3635
3636static bool
3637rx_modes_tieable_p (machine_mode mode1, machine_mode mode2)
3638{
3639 return ((GET_MODE_CLASS (mode1) == MODE_FLOAT
3640 || GET_MODE_CLASS (mode1) == MODE_COMPLEX_FLOAT)
3641 == (GET_MODE_CLASS (mode2) == MODE_FLOAT
3642 || GET_MODE_CLASS (mode2) == MODE_COMPLEX_FLOAT));
3643}
9d2f1b03 3644\f
ee1401ac 3645#undef TARGET_NARROW_VOLATILE_BITFIELD
3646#define TARGET_NARROW_VOLATILE_BITFIELD rx_narrow_volatile_bitfield
3647
3648#undef TARGET_CAN_INLINE_P
3649#define TARGET_CAN_INLINE_P rx_ok_to_inline
3650
24833e1a 3651#undef TARGET_FUNCTION_VALUE
3652#define TARGET_FUNCTION_VALUE rx_function_value
3653
3654#undef TARGET_RETURN_IN_MSB
3655#define TARGET_RETURN_IN_MSB rx_return_in_msb
3656
3657#undef TARGET_IN_SMALL_DATA_P
3658#define TARGET_IN_SMALL_DATA_P rx_in_small_data
3659
3660#undef TARGET_RETURN_IN_MEMORY
3661#define TARGET_RETURN_IN_MEMORY rx_return_in_memory
3662
3663#undef TARGET_HAVE_SRODATA_SECTION
3664#define TARGET_HAVE_SRODATA_SECTION true
3665
3666#undef TARGET_ASM_SELECT_RTX_SECTION
3667#define TARGET_ASM_SELECT_RTX_SECTION rx_select_rtx_section
3668
3669#undef TARGET_ASM_SELECT_SECTION
3670#define TARGET_ASM_SELECT_SECTION rx_select_section
3671
3672#undef TARGET_INIT_BUILTINS
3673#define TARGET_INIT_BUILTINS rx_init_builtins
3674
103700c7 3675#undef TARGET_BUILTIN_DECL
3676#define TARGET_BUILTIN_DECL rx_builtin_decl
3677
24833e1a 3678#undef TARGET_EXPAND_BUILTIN
3679#define TARGET_EXPAND_BUILTIN rx_expand_builtin
3680
3681#undef TARGET_ASM_CONSTRUCTOR
3682#define TARGET_ASM_CONSTRUCTOR rx_elf_asm_constructor
3683
3684#undef TARGET_ASM_DESTRUCTOR
3685#define TARGET_ASM_DESTRUCTOR rx_elf_asm_destructor
3686
3687#undef TARGET_STRUCT_VALUE_RTX
3688#define TARGET_STRUCT_VALUE_RTX rx_struct_value_rtx
3689
3690#undef TARGET_ATTRIBUTE_TABLE
3691#define TARGET_ATTRIBUTE_TABLE rx_attribute_table
3692
3693#undef TARGET_ASM_FILE_START
3694#define TARGET_ASM_FILE_START rx_file_start
3695
3696#undef TARGET_MS_BITFIELD_LAYOUT_P
3697#define TARGET_MS_BITFIELD_LAYOUT_P rx_is_ms_bitfield_layout
3698
3699#undef TARGET_LEGITIMATE_ADDRESS_P
3700#define TARGET_LEGITIMATE_ADDRESS_P rx_is_legitimate_address
3701
5afe50d9 3702#undef TARGET_MODE_DEPENDENT_ADDRESS_P
3703#define TARGET_MODE_DEPENDENT_ADDRESS_P rx_mode_dependent_address_p
3704
24833e1a 3705#undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
3706#define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS rx_allocate_stack_slots_for_args
3707
3708#undef TARGET_ASM_FUNCTION_PROLOGUE
3709#define TARGET_ASM_FUNCTION_PROLOGUE rx_output_function_prologue
3710
3711#undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
3712#define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P rx_func_attr_inlinable
3713
61fc50a0 3714#undef TARGET_FUNCTION_OK_FOR_SIBCALL
3715#define TARGET_FUNCTION_OK_FOR_SIBCALL rx_function_ok_for_sibcall
3716
ee4e8428 3717#undef TARGET_FUNCTION_ARG
3718#define TARGET_FUNCTION_ARG rx_function_arg
3719
3720#undef TARGET_FUNCTION_ARG_ADVANCE
3721#define TARGET_FUNCTION_ARG_ADVANCE rx_function_arg_advance
3722
bd99ba64 3723#undef TARGET_FUNCTION_ARG_BOUNDARY
3724#define TARGET_FUNCTION_ARG_BOUNDARY rx_function_arg_boundary
3725
24833e1a 3726#undef TARGET_SET_CURRENT_FUNCTION
3727#define TARGET_SET_CURRENT_FUNCTION rx_set_current_function
3728
24833e1a 3729#undef TARGET_ASM_INTEGER
3730#define TARGET_ASM_INTEGER rx_assemble_integer
3731
3732#undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
3733#define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
3734
3735#undef TARGET_MAX_ANCHOR_OFFSET
3736#define TARGET_MAX_ANCHOR_OFFSET 32
3737
3738#undef TARGET_ADDRESS_COST
3739#define TARGET_ADDRESS_COST rx_address_cost
3740
3741#undef TARGET_CAN_ELIMINATE
3742#define TARGET_CAN_ELIMINATE rx_can_eliminate
3743
b2d7ede1 3744#undef TARGET_CONDITIONAL_REGISTER_USAGE
3745#define TARGET_CONDITIONAL_REGISTER_USAGE rx_conditional_register_usage
3746
24833e1a 3747#undef TARGET_ASM_TRAMPOLINE_TEMPLATE
3748#define TARGET_ASM_TRAMPOLINE_TEMPLATE rx_trampoline_template
3749
3750#undef TARGET_TRAMPOLINE_INIT
3751#define TARGET_TRAMPOLINE_INIT rx_trampoline_init
3752
6bb30542 3753#undef TARGET_PRINT_OPERAND
3754#define TARGET_PRINT_OPERAND rx_print_operand
3755
3756#undef TARGET_PRINT_OPERAND_ADDRESS
3757#define TARGET_PRINT_OPERAND_ADDRESS rx_print_operand_address
3758
9d2f1b03 3759#undef TARGET_CC_MODES_COMPATIBLE
3760#define TARGET_CC_MODES_COMPATIBLE rx_cc_modes_compatible
3761
3762#undef TARGET_MEMORY_MOVE_COST
3763#define TARGET_MEMORY_MOVE_COST rx_memory_move_cost
3764
1af17d44 3765#undef TARGET_OPTION_OVERRIDE
3766#define TARGET_OPTION_OVERRIDE rx_option_override
3767
bd7d2835 3768#undef TARGET_PROMOTE_FUNCTION_MODE
3769#define TARGET_PROMOTE_FUNCTION_MODE rx_promote_function_mode
3770
42d89991 3771#undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
3772#define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE rx_override_options_after_change
02e53c17 3773
77de4b78 3774#undef TARGET_FLAGS_REGNUM
3775#define TARGET_FLAGS_REGNUM CC_REG
3776
ca316360 3777#undef TARGET_LEGITIMATE_CONSTANT_P
f7fcec1a 3778#define TARGET_LEGITIMATE_CONSTANT_P rx_is_legitimate_constant
ca316360 3779
6e507301 3780#undef TARGET_LEGITIMIZE_ADDRESS
3781#define TARGET_LEGITIMIZE_ADDRESS rx_legitimize_address
3782
ee1401ac 3783#undef TARGET_WARN_FUNC_RETURN
3784#define TARGET_WARN_FUNC_RETURN rx_warn_func_return
08c6cbd2 3785
f0964309 3786#undef TARGET_LRA_P
3787#define TARGET_LRA_P rx_enable_lra
3788
74f68e49 3789#undef TARGET_HARD_REGNO_NREGS
3790#define TARGET_HARD_REGNO_NREGS rx_hard_regno_nregs
b395382f 3791#undef TARGET_HARD_REGNO_MODE_OK
3792#define TARGET_HARD_REGNO_MODE_OK rx_hard_regno_mode_ok
3793
5f6dcf1a 3794#undef TARGET_MODES_TIEABLE_P
3795#define TARGET_MODES_TIEABLE_P rx_modes_tieable_p
3796
e3b0bc49 3797#undef TARGET_RTX_COSTS
3798#define TARGET_RTX_COSTS rx_rtx_costs
3799
26771b45 3800#undef TARGET_HAVE_SPECULATION_SAFE_VALUE
3801#define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed
3802
24833e1a 3803struct gcc_target targetm = TARGET_INITIALIZER;
3804
103700c7 3805#include "gt-rx.h"
Mirror of https://gcc.gnu.org/git/gcc.git