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52609473 | 1 | ;; Scheduling description for z990 (cpu 2084). |
aeee4812 | 2 | ;; Copyright (C) 2003-2023 Free Software Foundation, Inc. |
52609473 HP |
3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
4 | ;; Ulrich Weigand (uweigand@de.ibm.com). | |
58add37a UW |
5 | |
6 | ;; This file is part of GCC. | |
7 | ||
8 | ;; GCC is free software; you can redistribute it and/or modify it under | |
9 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 10 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
11 | ;; version. |
12 | ||
13 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
14 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | ;; for more details. | |
17 | ||
52609473 | 18 | ;; You should have received a copy of the GNU General Public License |
2f83c7d6 NC |
19 | ;; along with GCC; see the file COPYING3. If not see |
20 | ;; <http://www.gnu.org/licenses/>. | |
52609473 HP |
21 | |
22 | (define_automaton "x_ipu") | |
23 | ||
24 | (define_cpu_unit "x_e1_r,x_e1_s,x_e1_t" "x_ipu") | |
25 | (define_cpu_unit "x_wr_r,x_wr_s,x_wr_t,x_wr_fp" "x_ipu") | |
26 | (define_cpu_unit "x_s1,x_s2,x_s3,x_s4" "x_ipu") | |
27 | (define_cpu_unit "x_t1,x_t2,x_t3,x_t4" "x_ipu") | |
28 | (define_cpu_unit "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6" "x_ipu") | |
29 | (define_cpu_unit "x_store_tok" "x_ipu") | |
30 | (define_cpu_unit "x_ms,x_mt" "x_ipu") | |
31 | ||
32 | (define_reservation "x-e1-st" "(x_e1_s | x_e1_t)") | |
33 | ||
34 | (define_reservation "x-e1-np" "(x_e1_r + x_e1_s + x_e1_t)") | |
35 | ||
36 | (absence_set "x_e1_r" "x_e1_s,x_e1_t") | |
37 | (absence_set "x_e1_s" "x_e1_t") | |
38 | ||
39 | ;; Try to avoid int <-> fp transitions. | |
40 | ||
41 | (define_reservation "x-x" "x_s1|x_t1,x_s2|x_t2,x_s3|x_t3,x_s4|x_t4") | |
42 | (define_reservation "x-f" "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6") | |
43 | (define_reservation "x-wr-st" "((x_wr_s | x_wr_t),x-x)") | |
44 | (define_reservation "x-wr-np" "((x_wr_r + x_wr_s + x_wr_t),x-x)") | |
45 | (define_reservation "x-wr-fp" "x_wr_fp,x-f") | |
46 | (define_reservation "x-mem" "x_ms|x_mt") | |
47 | ||
48 | (absence_set "x_wr_fp" | |
49 | "x_s1,x_s2,x_s3,x_s4,x_t1,x_t2,x_t3,x_t4,x_wr_s,x_wr_t") | |
50 | ||
51 | (absence_set "x_e1_r,x_wr_r,x_wr_s,x_wr_t" | |
52 | "x_f1,x_f2,x_f3,x_f4,x_f5,x_f6,x_wr_fp") | |
53 | ||
54 | ;; Don't have any load type insn in same group as store | |
55 | ||
56 | (absence_set "x_ms,x_mt" "x_store_tok") | |
57 | ||
58 | ||
59 | ;; | |
60 | ;; Simple insns | |
61 | ;; | |
62 | ||
29a74354 | 63 | (define_insn_reservation "x_int" 1 |
f137aa63 | 64 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
29a74354 UW |
65 | (and (eq_attr "type" "integer") |
66 | (eq_attr "atype" "reg"))) | |
67 | "x-e1-st,x-wr-st") | |
68 | ||
69 | (define_insn_reservation "x_agen" 1 | |
f137aa63 | 70 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
29a74354 UW |
71 | (and (eq_attr "type" "integer") |
72 | (eq_attr "atype" "agen"))) | |
73 | "x-e1-st,x-wr-st") | |
74 | ||
52609473 | 75 | (define_insn_reservation "x_lr" 1 |
f137aa63 | 76 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
52609473 | 77 | (eq_attr "type" "lr")) |
f4aa3848 | 78 | "x-e1-st,x-wr-st") |
52609473 | 79 | |
f4aa3848 | 80 | (define_insn_reservation "x_la" 1 |
f137aa63 | 81 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
52609473 | 82 | (eq_attr "type" "la")) |
f4aa3848 | 83 | "x-e1-st,x-wr-st") |
52609473 | 84 | |
f4aa3848 | 85 | (define_insn_reservation "x_larl" 1 |
f137aa63 | 86 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
52609473 | 87 | (eq_attr "type" "larl")) |
f4aa3848 | 88 | "x-e1-st,x-wr-st") |
52609473 | 89 | |
f4aa3848 | 90 | (define_insn_reservation "x_load" 1 |
f137aa63 | 91 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
52609473 | 92 | (eq_attr "type" "load")) |
f4aa3848 | 93 | "x-e1-st+x-mem,x-wr-st") |
52609473 | 94 | |
f4aa3848 | 95 | (define_insn_reservation "x_store" 1 |
f137aa63 | 96 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
52609473 | 97 | (eq_attr "type" "store")) |
f4aa3848 | 98 | "x-e1-st+x_store_tok,x-wr-st") |
52609473 | 99 | |
f4aa3848 | 100 | (define_insn_reservation "x_branch" 1 |
f137aa63 | 101 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
52609473 | 102 | (eq_attr "type" "branch")) |
f4aa3848 | 103 | "x_e1_r,x_wr_r") |
52609473 | 104 | |
f4aa3848 | 105 | (define_insn_reservation "x_call" 5 |
f137aa63 | 106 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
52609473 | 107 | (eq_attr "type" "jsr")) |
ed0e512a | 108 | "x-e1-np*5,x-wr-np") |
f4aa3848 | 109 | |
ed0e512a | 110 | (define_insn_reservation "x_mul_hi" 2 |
f137aa63 | 111 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
ed0e512a AK |
112 | (eq_attr "type" "imulhi")) |
113 | "x-e1-np*2,x-wr-np") | |
114 | ||
115 | (define_insn_reservation "x_mul_sidi" 4 | |
f137aa63 | 116 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
ed0e512a AK |
117 | (eq_attr "type" "imulsi,imuldi")) |
118 | "x-e1-np*4,x-wr-np") | |
119 | ||
120 | (define_insn_reservation "x_div" 10 | |
f137aa63 | 121 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
ed0e512a AK |
122 | (eq_attr "type" "idiv")) |
123 | "x-e1-np*10,x-wr-np") | |
52609473 | 124 | |
f4aa3848 | 125 | (define_insn_reservation "x_sem" 17 |
f137aa63 | 126 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
e0374221 | 127 | (eq_attr "type" "sem")) |
f4aa3848 | 128 | "x-e1-np+x-mem,x-e1-np*16,x-wr-st") |
e0374221 | 129 | |
52609473 HP |
130 | ;; |
131 | ;; Multicycle insns | |
132 | ;; | |
133 | ||
f4aa3848 | 134 | (define_insn_reservation "x_cs" 1 |
f137aa63 | 135 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
29a74354 | 136 | (eq_attr "type" "cs")) |
f4aa3848 | 137 | "x-e1-np,x-wr-np") |
52609473 | 138 | |
f4aa3848 | 139 | (define_insn_reservation "x_vs" 1 |
f137aa63 | 140 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
29a74354 | 141 | (eq_attr "type" "vs")) |
f4aa3848 | 142 | "x-e1-np*10,x-wr-np") |
29a74354 | 143 | |
f4aa3848 | 144 | (define_insn_reservation "x_stm" 1 |
f137aa63 | 145 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
52609473 | 146 | (eq_attr "type" "stm")) |
f4aa3848 | 147 | "(x-e1-np+x_store_tok)*10,x-wr-np") |
52609473 | 148 | |
f4aa3848 | 149 | (define_insn_reservation "x_lm" 1 |
f137aa63 | 150 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
52609473 | 151 | (eq_attr "type" "lm")) |
f4aa3848 | 152 | "x-e1-np*10,x-wr-np") |
52609473 | 153 | |
f4aa3848 | 154 | (define_insn_reservation "x_other" 1 |
f137aa63 | 155 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
29a74354 | 156 | (eq_attr "type" "other")) |
f4aa3848 | 157 | "x-e1-np,x-wr-np") |
52609473 | 158 | |
52609473 HP |
159 | ;; |
160 | ;; Floating point insns | |
161 | ;; | |
162 | ||
f4aa3848 | 163 | (define_insn_reservation "x_fsimptf" 7 |
f137aa63 | 164 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
2cdece44 | 165 | (eq_attr "type" "fsimptf,fhex")) |
f4aa3848 | 166 | "x_e1_t*2,x-wr-fp") |
f61a2c7d | 167 | |
f4aa3848 | 168 | (define_insn_reservation "x_fsimpdf" 6 |
f137aa63 | 169 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
65b1d8ea | 170 | (eq_attr "type" "fsimpdf,fmuldf,fmadddf,fhex")) |
f4aa3848 | 171 | "x_e1_t,x-wr-fp") |
52609473 | 172 | |
f4aa3848 | 173 | (define_insn_reservation "x_fsimpsf" 6 |
f137aa63 | 174 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
65b1d8ea | 175 | (eq_attr "type" "fsimpsf,fmulsf,fmaddsf,fhex")) |
f4aa3848 | 176 | "x_e1_t,x-wr-fp") |
52609473 | 177 | |
f61a2c7d AK |
178 | |
179 | (define_insn_reservation "x_fmultf" 33 | |
f137aa63 | 180 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
f61a2c7d | 181 | (eq_attr "type" "fmultf")) |
f4aa3848 | 182 | "x_e1_t*27,x-wr-fp") |
f61a2c7d AK |
183 | |
184 | ||
185 | (define_insn_reservation "x_fdivtf" 82 | |
f137aa63 | 186 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
f61a2c7d | 187 | (eq_attr "type" "fdivtf,fsqrttf")) |
f4aa3848 | 188 | "x_e1_t*76,x-wr-fp") |
f61a2c7d | 189 | |
cfdb984b | 190 | (define_insn_reservation "x_fdivdf" 36 |
f137aa63 | 191 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
cfdb984b | 192 | (eq_attr "type" "fdivdf,fsqrtdf")) |
f4aa3848 | 193 | "x_e1_t*30,x-wr-fp") |
52609473 | 194 | |
f4aa3848 | 195 | (define_insn_reservation "x_fdivsf" 36 |
f137aa63 | 196 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
cfdb984b | 197 | (eq_attr "type" "fdivsf,fsqrtsf")) |
f4aa3848 | 198 | "x_e1_t*30,x-wr-fp") |
52609473 | 199 | |
f61a2c7d | 200 | |
f4aa3848 | 201 | (define_insn_reservation "x_floadtf" 6 |
f137aa63 | 202 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
f61a2c7d | 203 | (eq_attr "type" "floadtf")) |
f4aa3848 | 204 | "x_e1_t,x-wr-fp") |
f61a2c7d | 205 | |
f4aa3848 | 206 | (define_insn_reservation "x_floaddf" 6 |
f137aa63 | 207 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
cfdb984b | 208 | (eq_attr "type" "floaddf")) |
f4aa3848 | 209 | "x_e1_t,x-wr-fp") |
52609473 | 210 | |
f4aa3848 | 211 | (define_insn_reservation "x_floadsf" 6 |
f137aa63 | 212 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
cfdb984b | 213 | (eq_attr "type" "floadsf")) |
f4aa3848 | 214 | "x_e1_t,x-wr-fp") |
52609473 | 215 | |
f61a2c7d | 216 | |
f4aa3848 | 217 | (define_insn_reservation "x_fstoredf" 1 |
f137aa63 | 218 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
cfdb984b | 219 | (eq_attr "type" "fstoredf")) |
f4aa3848 | 220 | "x_e1_t,x-wr-fp") |
52609473 | 221 | |
f4aa3848 | 222 | (define_insn_reservation "x_fstoresf" 1 |
f137aa63 | 223 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
cfdb984b | 224 | (eq_attr "type" "fstoresf")) |
f4aa3848 | 225 | "x_e1_t,x-wr-fp") |
52609473 | 226 | |
f61a2c7d AK |
227 | |
228 | (define_insn_reservation "x_ftrunctf" 16 | |
f137aa63 | 229 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
f61a2c7d | 230 | (eq_attr "type" "ftrunctf")) |
f4aa3848 | 231 | "x_e1_t*10,x-wr-fp") |
f61a2c7d AK |
232 | |
233 | (define_insn_reservation "x_ftruncdf" 11 | |
f137aa63 | 234 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
f61a2c7d | 235 | (eq_attr "type" "ftruncdf")) |
f4aa3848 | 236 | "x_e1_t*5,x-wr-fp") |
f61a2c7d AK |
237 | |
238 | ||
f4aa3848 | 239 | (define_insn_reservation "x_ftoi" 1 |
f137aa63 | 240 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
52609473 | 241 | (eq_attr "type" "ftoi")) |
f4aa3848 | 242 | "x_e1_t*3,x-wr-fp") |
52609473 | 243 | |
f4aa3848 | 244 | (define_insn_reservation "x_itof" 7 |
f137aa63 | 245 | (and (eq_attr "cpu" "z990,z9_109,z9_ec") |
9381e3f1 | 246 | (eq_attr "type" "itoftf,itofdf,itofsf")) |
f4aa3848 | 247 | "x_e1_t*3,x-wr-fp") |
52609473 | 248 | |
cfdb984b | 249 | (define_bypass 1 "x_fsimpdf" "x_fstoredf") |
52609473 | 250 | |
cfdb984b | 251 | (define_bypass 1 "x_fsimpsf" "x_fstoresf") |
52609473 | 252 | |
cfdb984b | 253 | (define_bypass 1 "x_floaddf" "x_fsimpdf,x_fstoredf,x_floaddf") |
f4aa3848 | 254 | |
cfdb984b | 255 | (define_bypass 1 "x_floadsf" "x_fsimpsf,x_fstoresf,x_floadsf") |
52609473 | 256 | |
52609473 | 257 | ;; |
f4aa3848 | 258 | ;; s390_agen_dep_p returns 1, if a register is set in the |
fae778eb | 259 | ;; first insn and used in the dependent insn to form a address. |
52609473 HP |
260 | ;; |
261 | ||
262 | ;; | |
fae778eb | 263 | ;; If an instruction uses a register to address memory, it needs |
52609473 | 264 | ;; to be set 5 cycles in advance. |
f4aa3848 | 265 | ;; |
52609473 | 266 | |
f4aa3848 | 267 | (define_bypass 5 "x_int,x_agen,x_lr" |
29a74354 | 268 | "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other" |
52609473 HP |
269 | "s390_agen_dep_p") |
270 | ||
f4aa3848 | 271 | (define_bypass 9 "x_int,x_agen,x_lr" |
f61a2c7d | 272 | "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\ |
cfdb984b | 273 | x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf" |
52609473 HP |
274 | "s390_agen_dep_p") |
275 | ;; | |
f4aa3848 AK |
276 | ;; A load type instruction uses a bypass to feed the result back |
277 | ;; to the address generation pipeline stage. | |
52609473 HP |
278 | ;; |
279 | ||
f4aa3848 | 280 | (define_bypass 4 "x_load" |
29a74354 | 281 | "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other" |
52609473 HP |
282 | "s390_agen_dep_p") |
283 | ||
284 | (define_bypass 5 "x_load" | |
f61a2c7d | 285 | "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\ |
cfdb984b | 286 | x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf" |
52609473 HP |
287 | "s390_agen_dep_p") |
288 | ||
289 | ;; | |
f4aa3848 AK |
290 | ;; A load address type instruction uses a bypass to feed the |
291 | ;; result back to the address generation pipeline stage. | |
52609473 HP |
292 | ;; |
293 | ||
f4aa3848 | 294 | (define_bypass 3 "x_larl,x_la" |
29a74354 | 295 | "x_agen,x_la,x_branch,x_call,x_load,x_store,x_cs,x_stm,x_lm,x_other" |
52609473 HP |
296 | "s390_agen_dep_p") |
297 | ||
298 | (define_bypass 5 "x_larl, x_la" | |
f61a2c7d | 299 | "x_floadtf, x_floaddf, x_floadsf, x_fstoredf, x_fstoresf,\ |
cfdb984b | 300 | x_fsimpdf, x_fsimpsf, x_fdivdf, x_fdivsf" |
52609473 HP |
301 | "s390_agen_dep_p") |
302 | ||
303 | ;; | |
304 | ;; Operand forwarding | |
305 | ;; | |
306 | ||
307 | (define_bypass 0 "x_lr,x_la,x_load" "x_int,x_lr") | |
308 | ||
309 |