]>
Commit | Line | Data |
---|---|---|
9381e3f1 | 1 | ;; Scheduling description for z10 (cpu 2097). |
aeee4812 | 2 | ;; Copyright (C) 2008-2023 Free Software Foundation, Inc. |
9381e3f1 WG |
3 | ;; Contributed by Wolfgang Gellerich (gellerich@de.ibm.com). |
4 | ||
5 | ||
6 | ; General naming conventions used in this file: | |
7 | ; - The two pipelines are called S and T, respectively. | |
8 | ; - A name ending "_S" or "_T" indicates that something happens in | |
9 | ; (or belongs to) this pipeline. | |
10 | ; - A name ending "_ANY" indicates that something happens in (or belongs | |
11 | ; to) either of the two pipelines. | |
12 | ; - A name ending "_BOTH" indicates that something happens in (or belongs | |
13 | ; to) both pipelines. | |
14 | ||
15 | ||
16 | ;; Automaton and components. | |
17 | ||
18 | (define_automaton "z10_cpu") | |
19 | ||
20 | (define_cpu_unit "z10_e1_S, z10_e1_T" "z10_cpu") | |
21 | (define_reservation "z10_e1_ANY" "(z10_e1_S | z10_e1_T)") | |
22 | (define_reservation "z10_e1_BOTH" "(z10_e1_S + z10_e1_T)") | |
23 | ||
24 | ||
25 | ; Both pipelines can execute a branch instruction, and branch | |
26 | ; instructions can be grouped with all other groupable instructions | |
27 | ; but not with a second branch instruction. | |
28 | ||
29 | (define_cpu_unit "z10_branch_ANY" "z10_cpu") | |
30 | ||
31 | (define_insn_reservation "z10_branch" 4 | |
32 | (and (eq_attr "cpu" "z10") | |
33 | (eq_attr "type" "branch")) | |
34 | "z10_branch_ANY + z10_e1_ANY, z10_Gate_ANY") | |
35 | ||
36 | ||
37 | ; Z10 operand and result forwarding. | |
38 | ||
39 | ; Instructions marked with the attributes as z10_fwd or z10_fr can | |
40 | ; forward a value they load from one of their operants into a register | |
41 | ; if the instruction in the second pipeline reads the same register. | |
42 | ; The second operation must be superscalar. Instructions marked as | |
43 | ; z10_rec or z10_fr can receive a value they read from a register is | |
44 | ; this register gets updated by an instruction in the first pipeline. | |
45 | ; The first instruction must be superscalar. | |
46 | ||
47 | ||
48 | ; Forwarding from z10_fwd and z10_fr to z10_super. | |
49 | ||
50 | (define_bypass 0 "z10_la_fwd, z10_la_fwd_A1, z10_larl_fwd, z10_larl_fwd_A3, \ | |
51 | z10_load_fwd, z10_load_fwd_A3, \ | |
52 | z10_other_fwd, z10_other_fwd_A1, z10_other_fwd_A3, \ | |
53 | z10_other_fr, z10_other_fr_A3, z10_other_fr_E1, \ | |
54 | z10_other_fwd_E1, z10_lr_fr, z10_lr_fr_E1, \ | |
55 | z10_int_fwd, z10_int_fwd_A1, z10_int_fwd_A3, \ | |
56 | z10_int_fwd_E1, z10_int_fr, z10_int_fr_E1, \ | |
57 | z10_int_fr_A3" | |
58 | "z10_other_super, z10_other_super_c_E1, z10_other_super_E1, \ | |
59 | z10_int_super, z10_int_super_E1, \ | |
421b1e6b WG |
60 | z10_lr, z10_store_super" |
61 | " ! s390_agen_dep_p") | |
9381e3f1 WG |
62 | |
63 | ||
64 | ; Forwarding from z10_super to frz10_ and z10_rec. | |
65 | ||
66 | (define_bypass 0 "z10_other_super, z10_other_super_E1, z10_other_super_c_E1, \ | |
67 | z10_int_super, z10_int_super_E1, \ | |
68 | z10_larl_super_E1, z10_larl_super, \ | |
69 | z10_store_super" | |
70 | "z10_int_fr, z10_int_fr_E1, z10_int_fr_A3, \ | |
71 | z10_other_fr, z10_other_fr_A3, z10_lr_fr, z10_lr_fr_E1, \ | |
421b1e6b WG |
72 | z10_other_fr_E1, z10_store_rec" |
73 | " ! s390_agen_dep_p") | |
9381e3f1 WG |
74 | |
75 | ||
76 | ; Forwarding from z10_fwd and z10_fr to z10_rec and z10_fr. | |
77 | ||
78 | (define_bypass 0 "z10_la_fwd, z10_la_fwd_A1, z10_larl_fwd, z10_larl_fwd_A3, \ | |
79 | z10_load_fwd, z10_load_fwd_A3, \ | |
80 | z10_other_fwd, z10_other_fwd_A1, z10_other_fwd_A3, \ | |
81 | z10_other_fr, z10_other_fr_A3, z10_other_fr_E1, \ | |
82 | z10_other_fwd_E1, \ | |
83 | z10_lr_fr, z10_lr_fr_E1, \ | |
84 | z10_int_fwd, z10_int_fwd_A1, z10_int_fwd_A3, \ | |
85 | z10_int_fwd_E1, z10_int_fr, z10_int_fr_E1, \ | |
86 | z10_int_fr_A3" | |
87 | "z10_int_fr, z10_int_fr_E1, z10_int_fr_A3, \ | |
88 | z10_other_fr, z10_other_fr_A3, z10_lr_fr, z10_lr_fr_E1, \ | |
421b1e6b WG |
89 | z10_other_fr_E1, z10_store_rec" |
90 | " ! s390_agen_dep_p") | |
9381e3f1 WG |
91 | |
92 | ||
93 | ; | |
94 | ; Simple insns | |
95 | ; | |
96 | ||
97 | ; Here is the cycle diagram for FXU-executed instructions: | |
98 | ; ... A1 A2 A3 E1 P1 P2 P3 R0 ... | |
99 | ; ^ ^ ^ | |
100 | ; | | updated GPR is available | |
101 | ; | write to GPR | |
102 | ; instruction reads GPR during this cycle | |
103 | ||
104 | ||
105 | ; Variants of z10_int follow. | |
106 | ||
107 | (define_insn_reservation "z10_int" 6 | |
108 | (and (and (eq_attr "cpu" "z10") | |
109 | (eq_attr "type" "integer")) | |
110 | (and (eq_attr "atype" "reg") | |
111 | (and (and (eq_attr "z10prop" "!z10_super") | |
112 | (eq_attr "z10prop" "!z10_super_c")) | |
113 | (and (and (and (and (eq_attr "z10prop" "!z10_super_E1") | |
114 | (eq_attr "z10prop" "!z10_super_c_E1")) | |
115 | (eq_attr "z10prop" "!z10_fwd")) | |
116 | (and (eq_attr "z10prop" "!z10_fwd_A1") | |
117 | (eq_attr "z10prop" "!z10_fwd_A3"))) | |
118 | (and (and (eq_attr "z10prop" "!z10_fwd_E1") | |
119 | (eq_attr "z10prop" "!z10_fr")) | |
120 | (and (eq_attr "z10prop" "!z10_fr_E1") | |
121 | (eq_attr "z10prop" "!z10_fr_A3"))))))) | |
122 | "z10_e1_ANY, z10_Gate_ANY") | |
123 | ||
124 | (define_insn_reservation "z10_int_super" 6 | |
125 | (and (eq_attr "cpu" "z10") | |
126 | (and (eq_attr "type" "integer") | |
127 | (and (eq_attr "atype" "reg") | |
128 | (ior (eq_attr "z10prop" "z10_super") | |
129 | (eq_attr "z10prop" "z10_super_c"))))) | |
130 | "z10_e1_ANY, z10_Gate_ANY") | |
131 | ||
132 | (define_insn_reservation "z10_int_super_E1" 6 | |
133 | (and (eq_attr "cpu" "z10") | |
134 | (and (eq_attr "type" "integer") | |
135 | (and (eq_attr "atype" "reg") | |
136 | (ior (eq_attr "z10prop" "z10_super_E1") | |
137 | (eq_attr "z10prop" "z10_super_c_E1"))))) | |
138 | "z10_e1_ANY, z10_Gate_ANY") | |
139 | ||
140 | (define_insn_reservation "z10_int_fwd" 6 | |
141 | (and (eq_attr "cpu" "z10") | |
142 | (and (eq_attr "type" "integer") | |
143 | (and (eq_attr "atype" "reg") | |
144 | (eq_attr "z10prop" "z10_fwd")))) | |
145 | "z10_e1_ANY, z10_Gate_ANY") | |
146 | ||
147 | (define_insn_reservation "z10_int_fwd_A1" 6 | |
148 | (and (eq_attr "cpu" "z10") | |
149 | (and (eq_attr "type" "integer") | |
150 | (and (eq_attr "atype" "reg") | |
151 | (eq_attr "z10prop" "z10_fwd_A1")))) | |
152 | "z10_e1_ANY, z10_Gate_ANY") | |
153 | ||
154 | (define_insn_reservation "z10_int_fwd_A3" 6 | |
155 | (and (eq_attr "cpu" "z10") | |
156 | (and (eq_attr "type" "integer") | |
157 | (and (eq_attr "atype" "reg") | |
158 | (eq_attr "z10prop" "z10_fwd_A3")))) | |
159 | "z10_e1_ANY, z10_Gate_ANY") | |
160 | ||
161 | (define_insn_reservation "z10_int_fwd_E1" 6 | |
162 | (and (eq_attr "cpu" "z10") | |
163 | (and (eq_attr "type" "integer") | |
164 | (and (eq_attr "atype" "reg") | |
165 | (eq_attr "z10prop" "z10_fwd_E1")))) | |
166 | "z10_e1_ANY, z10_Gate_ANY") | |
167 | ||
168 | (define_insn_reservation "z10_int_fr" 6 | |
169 | (and (eq_attr "cpu" "z10") | |
170 | (and (eq_attr "type" "integer") | |
171 | (and (eq_attr "atype" "reg") | |
172 | (eq_attr "z10prop" "z10_fr")))) | |
173 | "z10_e1_ANY, z10_Gate_ANY") | |
174 | ||
175 | (define_insn_reservation "z10_int_fr_E1" 6 | |
176 | (and (eq_attr "cpu" "z10") | |
177 | (and (eq_attr "type" "integer") | |
178 | (and (eq_attr "atype" "reg") | |
179 | (eq_attr "z10prop" "z10_fr_E1")))) | |
180 | "z10_e1_ANY, z10_Gate_ANY") | |
181 | ||
182 | (define_insn_reservation "z10_int_fr_A3" 6 | |
183 | (and (eq_attr "cpu" "z10") | |
184 | (and (eq_attr "type" "integer") | |
185 | (and (eq_attr "atype" "reg") | |
186 | (eq_attr "z10prop" "z10_fr_A3")))) | |
187 | "z10_e1_ANY, z10_Gate_ANY") | |
188 | ||
189 | ; END of z10_int variants | |
190 | ||
191 | ||
192 | (define_insn_reservation "z10_agen" 6 | |
193 | (and (eq_attr "cpu" "z10") | |
194 | (and (eq_attr "type" "integer") | |
195 | (eq_attr "atype" "agen"))) | |
196 | "z10_e1_ANY, z10_Gate_ANY") | |
197 | ||
198 | ||
199 | (define_insn_reservation "z10_lr" 6 | |
200 | (and (eq_attr "cpu" "z10") | |
201 | (and (eq_attr "type" "lr") | |
202 | (and (eq_attr "z10prop" "!z10_fr") | |
203 | (eq_attr "z10prop" "!z10_fr_E1")))) | |
204 | "z10_e1_ANY, z10_Gate_ANY") | |
205 | ||
206 | (define_insn_reservation "z10_lr_fr" 6 | |
207 | (and (eq_attr "cpu" "z10") | |
208 | (and (eq_attr "type" "lr") | |
209 | (eq_attr "z10prop" "z10_fr"))) | |
210 | "z10_e1_ANY, z10_Gate_ANY") | |
9381e3f1 WG |
211 | |
212 | (define_insn_reservation "z10_lr_fr_E1" 6 | |
213 | (and (eq_attr "cpu" "z10") | |
214 | (and (eq_attr "type" "lr") | |
215 | (eq_attr "z10prop" "z10_fr_E1"))) | |
216 | "z10_e1_ANY, z10_Gate_ANY") | |
9381e3f1 WG |
217 | |
218 | (define_insn_reservation "z10_la" 6 | |
219 | (and (eq_attr "cpu" "z10") | |
220 | (and (eq_attr "type" "la") | |
221 | (and (eq_attr "z10prop" "!z10_fwd") | |
222 | (eq_attr "z10prop" "!z10_fwd_A1")))) | |
223 | "z10_e1_ANY, z10_Gate_ANY") | |
224 | ||
225 | (define_insn_reservation "z10_la_fwd" 6 | |
226 | (and (eq_attr "cpu" "z10") | |
227 | (and (eq_attr "type" "la") | |
228 | (eq_attr "z10prop" "z10_fwd"))) | |
229 | "z10_e1_ANY, z10_Gate_ANY") | |
9381e3f1 WG |
230 | |
231 | (define_insn_reservation "z10_la_fwd_A1" 6 | |
232 | (and (eq_attr "cpu" "z10") | |
233 | (and (eq_attr "type" "la") | |
234 | (eq_attr "z10prop" "z10_fwd_A1"))) | |
235 | "z10_e1_ANY, z10_Gate_ANY") | |
9381e3f1 WG |
236 | |
237 | ||
238 | ; larl-type instructions | |
239 | ||
240 | (define_insn_reservation "z10_larl" 6 | |
241 | (and (eq_attr "cpu" "z10") | |
242 | (and (eq_attr "type" "larl") | |
243 | (and (eq_attr "z10prop" "!z10_super_A1") | |
244 | (and (eq_attr "z10prop" "!z10_fwd") | |
245 | (and (eq_attr "z10prop" "!z10_fwd_A3") | |
246 | (and (eq_attr "z10prop" "!z10_super") | |
247 | (eq_attr "z10prop" "!z10_super_c")) | |
248 | (and (eq_attr "z10prop" "!z10_super_E1") | |
249 | (eq_attr "z10prop" "!z10_super_c_E1"))))))) | |
250 | "z10_e1_ANY, z10_Gate_ANY") | |
251 | ||
252 | (define_insn_reservation "z10_larl_super" 6 | |
253 | (and (eq_attr "cpu" "z10") | |
254 | (and (eq_attr "type" "larl") | |
255 | (and (eq_attr "z10prop" "z10_super") | |
256 | (eq_attr "z10prop" "z10_super_c")))) | |
257 | "z10_e1_ANY, z10_Gate_ANY") | |
258 | ||
259 | (define_insn_reservation "z10_larl_fwd" 6 | |
260 | (and (eq_attr "cpu" "z10") | |
261 | (and (eq_attr "type" "larl") | |
262 | (eq_attr "z10prop" "z10_fwd"))) | |
263 | "z10_e1_ANY, z10_Gate_ANY") | |
264 | ||
265 | (define_insn_reservation "z10_larl_fwd_A3" 6 | |
266 | (and (eq_attr "cpu" "z10") | |
267 | (and (eq_attr "type" "larl") | |
268 | (eq_attr "z10prop" "z10_fwd_A3"))) | |
269 | "z10_e1_ANY, z10_Gate_ANY") | |
270 | ||
271 | ||
272 | (define_insn_reservation "z10_larl_A1" 6 | |
273 | (and (eq_attr "cpu" "z10") | |
274 | (and (eq_attr "type" "larl") | |
275 | (eq_attr "z10prop" "z10_super_A1"))) | |
276 | "z10_e1_ANY, z10_Gate_ANY") | |
277 | ; "z10_e1_ANY") | |
278 | ||
279 | (define_insn_reservation "z10_larl_super_E1" 6 | |
280 | (and (eq_attr "cpu" "z10") | |
281 | (and (eq_attr "type" "larl") | |
282 | (ior (eq_attr "z10prop" "z10_super_E1") | |
283 | (eq_attr "z10prop" "z10_super_c_E1")))) | |
284 | "z10_e1_ANY, z10_Gate_ANY") | |
285 | ; "z10_e1_ANY") | |
286 | ||
287 | ||
288 | (define_insn_reservation "z10_load" 6 | |
289 | (and (eq_attr "cpu" "z10") | |
290 | (and (eq_attr "type" "load") | |
291 | (and (eq_attr "z10prop" "!z10_fwd") | |
292 | (eq_attr "z10prop" "!z10_fwd_A3")))) | |
293 | "z10_e1_ANY, z10_Gate_ANY") | |
294 | ||
295 | (define_insn_reservation "z10_load_fwd" 6 | |
296 | (and (eq_attr "cpu" "z10") | |
297 | (and (eq_attr "type" "load") | |
298 | (eq_attr "z10prop" "z10_fwd"))) | |
299 | "z10_e1_ANY, z10_Gate_ANY") | |
300 | ; "z10_e1_ANY") | |
301 | ||
302 | (define_insn_reservation "z10_load_fwd_A3" 6 | |
303 | (and (eq_attr "cpu" "z10") | |
304 | (and (eq_attr "type" "load") | |
305 | (eq_attr "z10prop" "z10_fwd_A3"))) | |
306 | "z10_e1_ANY, z10_Gate_ANY") | |
307 | ; "z10_e1_ANY") | |
308 | ||
309 | (define_insn_reservation "z10_store" 6 | |
310 | (and (eq_attr "cpu" "z10") | |
311 | (and (eq_attr "type" "store") | |
312 | (and (eq_attr "z10prop" "!z10_rec") | |
313 | (and (eq_attr "z10prop" "!z10_super") | |
314 | (eq_attr "z10prop" "!z10_super_c"))))) | |
315 | "z10_e1_ANY, z10_Gate_ANY") | |
316 | ||
317 | (define_insn_reservation "z10_store_super" 6 | |
318 | (and (eq_attr "cpu" "z10") | |
319 | (and (eq_attr "type" "store") | |
320 | (ior (eq_attr "z10prop" "z10_super") | |
321 | (eq_attr "z10prop" "z10_super_c")))) | |
322 | "z10_e1_ANY, z10_Gate_ANY") | |
323 | ||
324 | (define_insn_reservation "z10_store_rec" 6 | |
325 | (and (eq_attr "cpu" "z10") | |
326 | (and (eq_attr "type" "store") | |
327 | (eq_attr "z10prop" "z10_rec"))) | |
328 | "z10_e1_ANY, z10_Gate_ANY") | |
329 | ||
330 | ; The default_latency is chosen to drain off the pipeline. | |
331 | (define_insn_reservation "z10_call" 14 | |
332 | (and (eq_attr "cpu" "z10") | |
333 | (eq_attr "type" "jsr")) | |
334 | "z10_e1_BOTH*4, z10_Gate_BOTH") | |
335 | ||
336 | ; The default latency is for worst case. CS and CSG take one | |
337 | ; cycle only (i.e. latency would be 6). | |
338 | (define_insn_reservation "z10_sem" 9 | |
339 | (and (eq_attr "cpu" "z10") | |
340 | (eq_attr "type" "sem")) | |
341 | "z10_e1_BOTH*5, z10_Gate_ANY") | |
342 | ||
343 | (define_insn_reservation "z10_cs" 6 | |
344 | (and (eq_attr "cpu" "z10") | |
345 | (eq_attr "type" "cs")) | |
346 | "z10_e1_BOTH, z10_Gate_BOTH") | |
347 | ||
348 | (define_insn_reservation "z10_vs" 6 | |
349 | (and (eq_attr "cpu" "z10") | |
350 | (eq_attr "type" "vs")) | |
351 | "z10_e1_BOTH*4, z10_Gate_BOTH") | |
352 | ||
353 | ; Load and store multiple. Actual number of cycles | |
354 | ; in unknown at compile.time. | |
355 | (define_insn_reservation "z10_stm" 10 | |
356 | (and (eq_attr "cpu" "z10") | |
357 | (ior (eq_attr "type" "stm") | |
358 | (eq_attr "type" "lm"))) | |
359 | "z10_e1_BOTH*4, z10_Gate_BOTH") | |
360 | ||
361 | ||
362 | ; Subsets of z10_other follow. | |
363 | ||
364 | (define_insn_reservation "z10_other" 6 | |
365 | (and (and (eq_attr "cpu" "z10") | |
366 | (eq_attr "type" "other")) | |
367 | (and (and (eq_attr "z10prop" "!z10_fwd") | |
368 | (eq_attr "z10prop" "!z10_fwd_A1")) | |
369 | (and (and (and (eq_attr "z10prop" "!z10_fr_A3") | |
370 | (eq_attr "z10prop" "!z10_fwd_A3")) | |
371 | (and (eq_attr "z10prop" "!z10_fr") | |
372 | (eq_attr "z10prop" "!z10_fr_E1"))) | |
373 | (and (and (and (eq_attr "z10prop" "!z10_super") | |
374 | (eq_attr "z10prop" "!z10_super_c")) | |
375 | (eq_attr "z10prop" "!z10_super_c_E1")) | |
376 | (and (eq_attr "z10prop" "!z10_super_E1") | |
377 | (eq_attr "z10prop" "!z10_fwd_E1")))))) | |
378 | "z10_e1_BOTH, z10_Gate_BOTH") | |
379 | ||
380 | (define_insn_reservation "z10_other_fr_E1" 6 | |
381 | (and (eq_attr "cpu" "z10") | |
382 | (and (eq_attr "type" "other") | |
383 | (eq_attr "z10prop" "z10_fr_E1"))) | |
384 | "z10_e1_BOTH, z10_Gate_BOTH") | |
385 | ||
386 | (define_insn_reservation "z10_other_super_c_E1" 6 | |
387 | (and (eq_attr "cpu" "z10") | |
388 | (and (eq_attr "type" "other") | |
389 | (eq_attr "z10prop" "z10_super_c_E1"))) | |
390 | "z10_e1_BOTH, z10_Gate_BOTH") | |
391 | ||
392 | (define_insn_reservation "z10_other_super_E1" 6 | |
393 | (and (eq_attr "cpu" "z10") | |
394 | (and (eq_attr "type" "other") | |
395 | (eq_attr "z10prop" "z10_super_E1"))) | |
396 | "z10_e1_BOTH, z10_Gate_BOTH") | |
397 | ||
398 | (define_insn_reservation "z10_other_fwd_E1" 6 | |
399 | (and (eq_attr "cpu" "z10") | |
400 | (and (eq_attr "type" "other") | |
401 | (eq_attr "z10prop" "z10_fwd_E1"))) | |
402 | "z10_e1_BOTH, z10_Gate_BOTH") | |
403 | ||
404 | (define_insn_reservation "z10_other_fwd" 6 | |
405 | (and (eq_attr "cpu" "z10") | |
406 | (and (eq_attr "type" "other") | |
407 | (eq_attr "z10prop" "z10_fwd"))) | |
408 | "z10_e1_BOTH, z10_Gate_BOTH") | |
409 | ||
410 | (define_insn_reservation "z10_other_fwd_A3" 6 | |
411 | (and (eq_attr "cpu" "z10") | |
412 | (and (eq_attr "type" "other") | |
413 | (eq_attr "z10prop" "z10_fwd_A3"))) | |
414 | "z10_e1_BOTH, z10_Gate_BOTH") | |
415 | ||
416 | (define_insn_reservation "z10_other_fwd_A1" 6 | |
417 | (and (eq_attr "cpu" "z10") | |
418 | (and (eq_attr "type" "other") | |
419 | (eq_attr "z10prop" "z10_fwd_A1"))) | |
420 | "z10_e1_BOTH, z10_Gate_BOTH") | |
421 | ||
422 | (define_insn_reservation "z10_other_fr" 6 | |
423 | (and (eq_attr "cpu" "z10") | |
424 | (and (eq_attr "type" "other") | |
425 | (eq_attr "z10prop" "z10_fr"))) | |
426 | "z10_e1_BOTH, z10_Gate_BOTH") | |
427 | ||
428 | (define_insn_reservation "z10_other_fr_A3" 6 | |
429 | (and (eq_attr "cpu" "z10") | |
430 | (and (eq_attr "type" "other") | |
431 | (eq_attr "z10prop" "z10_fr_A3"))) | |
432 | "z10_e1_BOTH, z10_Gate_BOTH") | |
433 | ||
434 | (define_insn_reservation "z10_other_super" 6 | |
435 | (and (eq_attr "cpu" "z10") | |
436 | (and (eq_attr "type" "other") | |
437 | (ior (eq_attr "z10prop" "z10_super") | |
438 | (eq_attr "z10prop" "z10_super_c")))) | |
439 | "z10_e1_BOTH, z10_Gate_BOTH") | |
440 | ||
441 | ; END of z10_other subsets. | |
442 | ||
443 | ||
444 | ; | |
445 | ; Floating point insns | |
446 | ; | |
447 | ||
448 | ; Z10 executes the following integer operations in the BFU pipeline. | |
449 | ||
450 | (define_insn_reservation "z10_mul_sidi" 12 | |
451 | (and (eq_attr "cpu" "z10") | |
452 | (eq_attr "type" "imulsi,imuldi,imulhi")) | |
453 | "z10_e1_BOTH, z10_Gate_FP") | |
454 | ||
455 | ; Some variants take fewer cycles, but that is not relevant here. | |
456 | (define_insn_reservation "z10_div" 162 | |
457 | (and (eq_attr "cpu" "z10") | |
458 | (eq_attr "type" "idiv")) | |
459 | "z10_e1_BOTH*4, z10_Gate_FP") | |
460 | ||
461 | ||
462 | ; BFP multiplication and general instructions | |
463 | ||
2cdece44 | 464 | (define_insn_reservation "z10_fsimpdf" 6 |
9381e3f1 | 465 | (and (eq_attr "cpu" "z10") |
65b1d8ea | 466 | (eq_attr "type" "fsimpdf,fmuldf,fmadddf")) |
9381e3f1 | 467 | "z10_e1_BOTH, z10_Gate_FP") |
9381e3f1 | 468 | |
2cdece44 | 469 | (define_insn_reservation "z10_fsimpsf" 6 |
9381e3f1 | 470 | (and (eq_attr "cpu" "z10") |
65b1d8ea | 471 | (eq_attr "type" "fsimpsf,fmulsf,fmaddsf")) |
9381e3f1 | 472 | "z10_e1_BOTH, z10_Gate_FP") |
9381e3f1 WG |
473 | |
474 | (define_insn_reservation "z10_fmultf" 52 | |
475 | (and (eq_attr "cpu" "z10") | |
476 | (eq_attr "type" "fmultf")) | |
477 | "z10_e1_BOTH*4, z10_Gate_FP") | |
9381e3f1 WG |
478 | |
479 | (define_insn_reservation "z10_fsimptf" 14 | |
480 | (and (eq_attr "cpu" "z10") | |
481 | (eq_attr "type" "fsimptf")) | |
482 | "z10_e1_BOTH*2, z10_Gate_FP") | |
9381e3f1 WG |
483 | |
484 | ||
485 | ; BFP division | |
486 | ||
487 | (define_insn_reservation "z10_fdivtf" 113 | |
488 | (and (eq_attr "cpu" "z10") | |
489 | (eq_attr "type" "fdivtf")) | |
490 | "z10_e1_T*4, z10_Gate_FP") | |
491 | ||
492 | (define_insn_reservation "z10_fdivdf" 41 | |
493 | (and (eq_attr "cpu" "z10") | |
494 | (eq_attr "type" "fdivdf")) | |
495 | "z10_e1_T*4, z10_Gate_FP") | |
496 | ||
497 | (define_insn_reservation "z10_fdivsf" 34 | |
498 | (and (eq_attr "cpu" "z10") | |
499 | (eq_attr "type" "fdivsf")) | |
500 | "z10_e1_T*4, z10_Gate_FP") | |
501 | ||
502 | ||
503 | ; BFP sqrt | |
504 | ||
505 | (define_insn_reservation "z10_fsqrtsf" 41 | |
506 | (and (eq_attr "cpu" "z10") | |
507 | (eq_attr "type" "fsqrtsf")) | |
508 | "z10_e1_T*4, z10_Gate_FP") | |
509 | ||
510 | (define_insn_reservation "z10_fsqrtdf" 54 | |
511 | (and (eq_attr "cpu" "z10") | |
512 | (eq_attr "type" "fsqrtdf")) | |
513 | "z10_e1_T*4, z10_Gate_FP") | |
514 | ||
515 | (define_insn_reservation "z10_fsqrtf" 122 | |
516 | (and (eq_attr "cpu" "z10") | |
517 | (eq_attr "type" "fsqrttf")) | |
518 | "z10_e1_T*4, z10_Gate_FP") | |
519 | ||
520 | ||
521 | ; BFP load and store | |
522 | ||
523 | (define_insn_reservation "z10_floadtf" 12 | |
524 | (and (eq_attr "cpu" "z10") | |
525 | (eq_attr "type" "floadtf")) | |
526 | "z10_e1_T, z10_Gate_FP") | |
527 | ||
2cdece44 | 528 | (define_insn_reservation "z10_floaddf" 1 |
9381e3f1 WG |
529 | (and (eq_attr "cpu" "z10") |
530 | (eq_attr "type" "floaddf")) | |
531 | "z10_e1_T, z10_Gate_FP") | |
532 | ||
2cdece44 | 533 | (define_insn_reservation "z10_floadsf" 1 |
9381e3f1 WG |
534 | (and (eq_attr "cpu" "z10") |
535 | (eq_attr "type" "floadsf")) | |
536 | "z10_e1_T, z10_Gate_FP") | |
537 | ||
538 | (define_insn_reservation "z10_fstoredf" 12 | |
539 | (and (eq_attr "cpu" "z10") | |
540 | (eq_attr "type" "fstoredf,fstoredd")) | |
541 | "z10_e1_T, z10_Gate_FP") | |
542 | ||
543 | (define_insn_reservation "z10_fstoresf" 12 | |
544 | (and (eq_attr "cpu" "z10") | |
545 | (eq_attr "type" "fstoresf,fstoresd")) | |
546 | "z10_e1_T, z10_Gate_FP") | |
547 | ||
548 | ||
549 | ; BFP truncate | |
2cdece44 | 550 | (define_insn_reservation "z10_ftrunctf" 16 |
9381e3f1 WG |
551 | (and (eq_attr "cpu" "z10") |
552 | (eq_attr "type" "ftrunctf")) | |
553 | "z10_e1_T, z10_Gate_FP") | |
554 | ||
2cdece44 | 555 | (define_insn_reservation "z10_ftruncdf" 12 |
9381e3f1 WG |
556 | (and (eq_attr "cpu" "z10") |
557 | (eq_attr "type" "ftruncdf")) | |
558 | "z10_e1_T, z10_Gate_FP") | |
559 | ||
560 | ||
561 | ; Conversion between BFP and int. | |
562 | (define_insn_reservation "z10_ftoi" 13 | |
563 | (and (eq_attr "cpu" "z10") | |
564 | (eq_attr "type" "ftoi")) | |
565 | "z10_e1_T, z10_Gate_FP") | |
566 | ||
567 | (define_insn_reservation "z10_itoftf" 14 | |
568 | (and (eq_attr "cpu" "z10") | |
569 | (eq_attr "type" "itoftf")) | |
570 | "z10_e1_T*2, z10_Gate_FP") | |
571 | ||
572 | (define_insn_reservation "z10_itofsfdf" 12 | |
573 | (and (eq_attr "cpu" "z10") | |
574 | (eq_attr "type" "itofdf,itofsf")) | |
575 | "z10_e1_T, z10_Gate_FP") | |
576 | ||
577 | ||
578 | ||
579 | ; BFP-related bypasses. There is no bypass for extended mode. | |
580 | (define_bypass 1 "z10_fsimpdf" "z10_fstoredf") | |
581 | (define_bypass 1 "z10_fsimpsf" "z10_fstoresf") | |
2cdece44 WG |
582 | (define_bypass 1 "z10_floaddf" "z10_fsimpdf, z10_fstoredf") |
583 | (define_bypass 1 "z10_floadsf" "z10_fsimpsf, z10_fstoresf") | |
9381e3f1 WG |
584 | |
585 | ||
586 | ; | |
587 | ; insn_reservations for DFP instructions. | |
588 | ; | |
589 | ||
590 | ; Exact number of cycles is not known at compile-time. | |
591 | (define_insn_reservation "z10_fdivddtd" 40 | |
592 | (and (eq_attr "cpu" "z10") | |
593 | (eq_attr "type" "fdivdd,fdivtd")) | |
594 | "z10_e1_BOTH,z10_Gate_DFU") | |
595 | ||
596 | (define_insn_reservation "z10_ftruncsd" 38 | |
597 | (and (eq_attr "cpu" "z10") | |
598 | (eq_attr "type" "ftruncsd")) | |
599 | "z10_e1_BOTH*4,z10_Gate_DFU") | |
600 | ||
601 | (define_insn_reservation "z10_ftruncdd" 340 | |
602 | (and (eq_attr "cpu" "z10") | |
603 | (eq_attr "type" "ftruncsd")) | |
604 | "z10_e1_BOTH*4,z10_Gate_DFU") | |
605 | ||
606 | (define_insn_reservation "z10_floaddd" 12 | |
607 | (and (eq_attr "cpu" "z10") | |
608 | (eq_attr "type" "floaddd")) | |
609 | "z10_e1_BOTH,z10_Gate_DFU") | |
610 | ||
611 | (define_insn_reservation "z10_floadsd" 12 | |
612 | (and (eq_attr "cpu" "z10") | |
613 | (eq_attr "type" "floadsd")) | |
614 | "z10_e1_BOTH,z10_Gate_DFU") | |
615 | ||
616 | ; Exact number of cycles is not known at compile-time. | |
617 | (define_insn_reservation "z10_fmulddtd" 35 | |
618 | (and (eq_attr "cpu" "z10") | |
619 | (eq_attr "type" "fmuldd,fmultd")) | |
620 | "z10_e1_BOTH,z10_Gate_DFU") | |
621 | ||
622 | (define_insn_reservation "z10_fsimpdd" 17 | |
623 | (and (eq_attr "cpu" "z10") | |
624 | (eq_attr "type" "fsimpdd")) | |
625 | "z10_e1_BOTH,z10_Gate_DFU") | |
626 | ||
627 | (define_insn_reservation "z10_fsimpsd" 17 | |
628 | (and (eq_attr "cpu" "z10") | |
629 | (eq_attr "type" "fsimpsd")) | |
630 | "z10_e1_BOTH,z10_Gate_DFU") | |
631 | ||
632 | (define_insn_reservation "z10_fsimptd" 18 | |
633 | (and (eq_attr "cpu" "z10") | |
634 | (eq_attr "type" "fsimptd")) | |
635 | "z10_e1_BOTH,z10_Gate_DFU") | |
636 | ||
637 | (define_insn_reservation "z10_itofdd" 36 | |
638 | (and (eq_attr "cpu" "z10") | |
639 | (eq_attr "type" "itofdd")) | |
640 | "z10_e1_BOTH*3,z10_Gate_DFU") | |
641 | ||
642 | (define_insn_reservation "z10_itoftd" 49 | |
643 | (and (eq_attr "cpu" "z10") | |
644 | (eq_attr "type" "itoftd")) | |
645 | "z10_e1_BOTH*3,z10_Gate_DFU") | |
646 | ||
647 | ; Exact number of cycles is not known at compile-time. | |
648 | (define_insn_reservation "z10_ftoidfp" 30 | |
649 | (and (eq_attr "cpu" "z10") | |
650 | (eq_attr "type" "ftoidfp")) | |
651 | "z10_e1_BOTH*3,z10_Gate_DFU") | |
652 | ||
653 | ||
654 | ; | |
655 | ; Address-related bypasses | |
656 | ; | |
657 | ||
421b1e6b | 658 | ; Here is the cycle diagram for address-related bypasses: |
9381e3f1 | 659 | ; ... G1 G2 G3 A0 A1 A2 A3 E1 P1 P2 P3 R0 ... |
421b1e6b WG |
660 | ; ^ ^ ^ ^ ^ ^ |
661 | ; | | | | | without bypass, its available AFTER this cycle | |
662 | ; | | | | E1-type bypasses provide the new value AFTER this cycle | |
663 | ; | | | A3-type bypasses provide the new value AFTER this cycle | |
664 | ; | | A1-type bypasses provide the new value AFTER this cycle | |
665 | ; | AGI resolution, actual USE of new value is DURING this cycle | |
9381e3f1 WG |
666 | ; AGI detection |
667 | ||
668 | (define_bypass 3 "z10_larl_A1, z10_la_fwd_A1, z10_other_fwd_A1, \ | |
669 | z10_int_fwd_A1" | |
670 | "z10_agen, z10_la, z10_branch, z10_call, z10_load, \ | |
671 | z10_store, \ | |
672 | z10_cs, z10_stm, z10_other" | |
673 | "s390_agen_dep_p") | |
674 | ||
9381e3f1 WG |
675 | (define_bypass 5 "z10_larl_fwd_A3, z10_load_fwd_A3, z10_other_fwd_A3, \ |
676 | z10_other_fr_A3, z10_int_fwd_A3, z10_int_fr_A3" | |
677 | "z10_agen, z10_la, z10_branch, z10_call, z10_load, \ | |
678 | z10_store, \ | |
679 | z10_cs, z10_stm, z10_other" | |
680 | "s390_agen_dep_p") | |
681 | ||
682 | (define_bypass 6 "z10_other_fr_E1, z10_other_super_c_E1, z10_other_super_E1, \ | |
683 | z10_other_fwd_E1, \ | |
684 | z10_lr_fr_E1, z10_larl_super_E1, \ | |
685 | z10_int_super_E1, z10_int_fwd_E1, z10_int_fr_E1" | |
686 | "z10_agen, z10_la, z10_branch, z10_call, z10_load, \ | |
421b1e6b WG |
687 | z10_store, \ |
688 | z10_cs, z10_stm, z10_other" | |
689 | "s390_agen_dep_p") | |
690 | ||
691 | (define_bypass 9 "z10_int_super, z10_int_fwd, z10_int_fr" | |
692 | "z10_agen, z10_la, z10_branch, z10_call, z10_load, \ | |
9381e3f1 WG |
693 | z10_store, \ |
694 | z10_cs, z10_stm, z10_other" | |
695 | "s390_agen_dep_p") | |
696 | ||
697 | ||
698 | ||
699 | ; | |
700 | ; Try to avoid transitions between DFU-, BFU- and FXU-executed instructions as there is a | |
701 | ; dispatch delay required. | |
702 | ; | |
703 | ||
704 | ||
705 | ; Declaration for some pseudo-pipeline stages that reflect the | |
073a8998 | 706 | ; dispatch gap when issuing an INT/FXU/BFU-executed instruction after |
9381e3f1 WG |
707 | ; an instruction executed by a different unit has been executed. The |
708 | ; approach is that we pretend a pipelined execution of BFU operations | |
709 | ; with as many stages as the gap is long and request that none of | |
073a8998 | 710 | ; these stages is busy when issuing a FXU- or DFU-executed |
9381e3f1 WG |
711 | ; instruction. Similar for FXU- and DFU-executed instructions. |
712 | ||
713 | ; Declaration for FPU stages. | |
714 | (define_cpu_unit "z10_f0, z10_f1, z10_f2, z10_f3, z10_f4, z10_f5, z10_f6, \ | |
715 | z10_f7, z10_f8, z10_f9, z10_f10, z10_f11, z10_f12" "z10_cpu") | |
716 | (define_reservation "z10_FP_PP" "z10_f0, z10_f1, z10_f2, z10_f3, z10_f4, \ | |
717 | z10_f5, z10_f6, z10_f7, z10_f8, z10_f9, z10_f10, z10_f11, \ | |
718 | z10_f12") | |
719 | ||
720 | ; Declaration for FXU stages. | |
721 | (define_cpu_unit "z10_S1, z10_S2, z10_S3, z10_S4, z10_S5, z10_S6" "z10_cpu") | |
722 | (define_cpu_unit "z10_T1, z10_T2, z10_T3, z10_T4, z10_T5, z10_T6" "z10_cpu") | |
723 | (define_reservation "z10_INT_PP" "z10_S1 | z10_T1, z10_S2 | z10_T2, z10_S3 \ | |
724 | | z10_T3, z10_S4 | z10_T4, z10_S5 | \ | |
725 | z10_T5, z10_S6 | z10_T6") | |
726 | ||
727 | ; Declaration for DFU stages. | |
728 | (define_cpu_unit "z10_d0, z10_d1, z10_d2, z10_d3, z10_d4, z10_d5, z10_d6" | |
729 | "z10_cpu") | |
730 | (define_reservation "z10_DFU_PP" "z10_d0, z10_d1, z10_d2, z10_d3, z10_d4, \ | |
731 | z10_d5, z10_d6") | |
732 | ||
733 | ||
734 | ; Pseudo-units representing whether the respective unit is available | |
735 | ; in the sense that using it does not cause a dispatch delay. | |
736 | ||
737 | (define_cpu_unit "z10_S_avail, z10_T_avail, z10_FP_avail, z10_DFU_avail" | |
738 | "z10_cpu") | |
739 | ||
740 | (absence_set "z10_FP_avail" | |
741 | "z10_S1, z10_S2, z10_S3, z10_S4, z10_S5, z10_S6, z10_T1, z10_T2, z10_T3, z10_T4, \ | |
742 | z10_T5, z10_T6, \ | |
743 | z10_d0, z10_d1, z10_d2, z10_d3, z10_d4, z10_d5, z10_d6") | |
744 | ||
745 | (absence_set "z10_S_avail,z10_T_avail" | |
746 | "z10_f0, z10_f1, z10_f2, z10_f3, z10_f4, z10_f5, z10_f6, z10_f7, \ | |
747 | z10_f8, z10_f9, z10_f10, z10_f11, z10_f12, \ | |
748 | z10_d0, z10_d1, z10_d2, z10_d3, z10_d4, z10_d5, z10_d6") | |
749 | ||
750 | (absence_set "z10_DFU_avail" | |
751 | "z10_S1, z10_S2, z10_S3, z10_S4, z10_S5, z10_S6, z10_T1, z10_T2, z10_T3, z10_T4, \ | |
752 | z10_T5, z10_T6, \ | |
753 | z10_f0, z10_f1, z10_f2, z10_f3, z10_f4, z10_f5, z10_f6, z10_f7, \ | |
754 | z10_f8, z10_f9, z10_f10, z10_f11, z10_f12") | |
755 | ||
756 | ||
757 | ; Pseudo-units to be used in insn_reservations. | |
758 | ||
759 | (define_reservation "z10_Gate_ANY" "((z10_S_avail | z10_T_avail), z10_INT_PP)") | |
760 | (define_reservation "z10_Gate_BOTH" "((z10_S_avail + z10_T_avail), z10_INT_PP)") | |
761 | ||
762 | (define_reservation "z10_Gate_FP" "z10_FP_avail, z10_FP_PP") | |
763 | ||
764 | (define_reservation "z10_Gate_DFU" "z10_DFU_avail, z10_DFU_PP") |