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59bc01b3 | 1 | ;; Constraints definitions belonging to the gcc backend for IBM S/390. |
fbd26352 | 2 | ;; Copyright (C) 2006-2019 Free Software Foundation, Inc. |
59bc01b3 | 3 | ;; Written by Wolfgang Gellerich, using code and information found in |
4 | ;; files s390.md, s390.h, and s390.c. | |
5 | ;; | |
6 | ;; This file is part of GCC. | |
7 | ;; | |
8 | ;; GCC is free software; you can redistribute it and/or modify it under | |
9 | ;; the terms of the GNU General Public License as published by the Free | |
038d1e19 | 10 | ;; Software Foundation; either version 3, or (at your option) any later |
59bc01b3 | 11 | ;; version. |
12 | ;; | |
13 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
14 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | ;; for more details. | |
17 | ;; | |
18 | ;; You should have received a copy of the GNU General Public License | |
038d1e19 | 19 | ;; along with GCC; see the file COPYING3. If not see |
20 | ;; <http://www.gnu.org/licenses/>. | |
59bc01b3 | 21 | |
22 | ||
23 | ;; | |
24 | ;; Special constraints for s/390 machine description: | |
25 | ;; | |
26 | ;; a -- Any address register from 1 to 15. | |
e68d6a13 | 27 | ;; b -- Memory operand whose address is a symbol reference or a symbol |
28 | ;; reference + constant which can be proven to be naturally aligned. | |
59bc01b3 | 29 | ;; c -- Condition code register 33. |
30 | ;; d -- Any register from 0 to 15. | |
31 | ;; f -- Floating point registers. | |
76a4c804 | 32 | ;; j -- Multiple letter constraint for constant scalar and vector values |
33 | ;; j00: constant zero scalar or vector | |
34 | ;; jm1: constant scalar or vector with all bits set | |
35 | ;; jxx: contiguous bitmask of 0 or 1 in all vector elements | |
36 | ;; jyy: constant consisting of byte chunks being either 0 or 0xff | |
80fc7f56 | 37 | ;; jKK: constant vector with all elements having the same value and |
38 | ;; matching K constraint | |
6191f2a0 | 39 | ;; jm6: An integer operand with the lowest order 6 bits all ones. |
59bc01b3 | 40 | ;; t -- Access registers 36 and 37. |
76a4c804 | 41 | ;; v -- Vector registers v0-v31. |
e68d6a13 | 42 | ;; C -- A signed 8-bit constant (-128..127) |
43 | ;; D -- An unsigned 16-bit constant (0..65535) | |
59bc01b3 | 44 | ;; G -- Const double zero operand |
45 | ;; I -- An 8-bit constant (0..255). | |
46 | ;; J -- A 12-bit constant (0..4095). | |
47 | ;; K -- A 16-bit constant (-32768..32767). | |
48 | ;; L -- Value appropriate as displacement. | |
49 | ;; (0..4095) for short displacement | |
50 | ;; (-524288..524287) for long displacement | |
51 | ;; M -- Constant integer with a value of 0x7fffffff. | |
52 | ;; N -- Multiple letter constraint followed by 4 parameter letters. | |
53 | ;; 0..9,x: number of the part counting from most to least significant | |
9f19cc6b | 54 | ;; S,H,Q: mode of the part |
59bc01b3 | 55 | ;; D,S,H: mode of the containing operand |
56 | ;; 0,F: value of the other parts (F - all bits set) | |
0d46035f | 57 | ;; -- |
e64f5133 | 58 | ;; xxDq satisfies s390_contiguous_bitmask_p for DImode |
59 | ;; (with possible wraparound of the one-bit range) | |
60 | ;; xxSw satisfies s390_contiguous_bitmask_p for SImode | |
61 | ;; (with possible wraparound of the one-bit range) | |
62 | ;; xxSq satisfies s390_contiguous_bitmask_nowrap_p for SImode | |
63 | ;; (without wraparound of the one-bit range) | |
59bc01b3 | 64 | ;; |
65 | ;; The constraint matches if the specified part of a constant | |
66 | ;; has a value different from its other parts. If the letter x | |
67 | ;; is specified instead of a part number, the constraint matches | |
68 | ;; if there is any single part with non-default value. | |
69 | ;; O -- Multiple letter constraint followed by 1 parameter. | |
70 | ;; s: Signed extended immediate value (-2G .. 2G-1). | |
71 | ;; p: Positive extended immediate value (0 .. 4G-1). | |
29847ec4 | 72 | ;; n: Negative extended immediate value (-4G+1 .. -1). |
59bc01b3 | 73 | ;; These constraints do not accept any operand if the machine does |
74 | ;; not provide the extended-immediate facility. | |
75 | ;; P -- Any integer constant that can be loaded without literal pool. | |
76 | ;; Q -- Memory reference without index register and with short displacement. | |
77 | ;; R -- Memory reference with index register and short displacement. | |
78 | ;; S -- Memory reference without index register but with long displacement. | |
79 | ;; T -- Memory reference with index register and long displacement. | |
80 | ;; A -- Multiple letter constraint followed by Q, R, S, or T: | |
81 | ;; Offsettable memory reference of type specified by second letter. | |
82 | ;; B -- Multiple letter constraint followed by Q, R, S, or T: | |
83 | ;; Memory reference of the type specified by second letter that | |
84 | ;; does *not* refer to a literal pool entry. | |
7396c35d | 85 | ;; U -- Pointer with short displacement. (deprecated - use ZR) |
86 | ;; W -- Pointer with long displacement. (deprecated - use ZT) | |
2be7449b | 87 | ;; Y -- Address style operand without index. |
a7b49046 | 88 | ;; ZQ -- Pointer without index register and with short displacement. |
89 | ;; ZR -- Pointer with index register and short displacement. | |
90 | ;; ZS -- Pointer without index register but with long displacement. | |
91 | ;; ZT -- Pointer with index register and long displacement. | |
6dea6aa2 | 92 | ;; ZL -- LARL operand when in 64-bit mode, otherwise nothing. |
a7b49046 | 93 | ;; |
59bc01b3 | 94 | ;; |
95 | ||
96 | ||
97 | ;; | |
98 | ;; Register constraints. | |
99 | ;; | |
100 | ||
ffead1ca | 101 | (define_register_constraint "a" |
59bc01b3 | 102 | "ADDR_REGS" |
103 | "Any address register from 1 to 15.") | |
104 | ||
105 | ||
ffead1ca | 106 | (define_register_constraint "c" |
59bc01b3 | 107 | "CC_REGS" |
108 | "Condition code register 33") | |
109 | ||
110 | ||
ffead1ca | 111 | (define_register_constraint "d" |
59bc01b3 | 112 | "GENERAL_REGS" |
113 | "Any register from 0 to 15") | |
114 | ||
115 | ||
ffead1ca | 116 | (define_register_constraint "f" |
59bc01b3 | 117 | "FP_REGS" |
118 | "Floating point registers") | |
119 | ||
120 | ||
ffead1ca | 121 | (define_register_constraint "t" |
59bc01b3 | 122 | "ACCESS_REGS" |
123 | "@internal | |
124 | Access registers 36 and 37") | |
125 | ||
126 | ||
76a4c804 | 127 | (define_register_constraint "v" |
128 | "VEC_REGS" | |
129 | "Vector registers v0-v31") | |
130 | ||
131 | ||
59bc01b3 | 132 | ;; |
133 | ;; General constraints for constants. | |
134 | ;; | |
135 | ||
e68d6a13 | 136 | (define_constraint "C" |
137 | "@internal | |
138 | An 8-bit signed immediate constant (-128..127)" | |
139 | (and (match_code "const_int") | |
140 | (match_test "ival >= -128 && ival <= 127"))) | |
141 | ||
142 | ||
143 | (define_constraint "D" | |
144 | "An unsigned 16-bit constant (0..65535)" | |
145 | (and (match_code "const_int") | |
146 | (match_test "ival >= 0 && ival <= 65535"))) | |
147 | ||
148 | ||
59bc01b3 | 149 | (define_constraint "G" |
150 | "@internal | |
151 | Const double zero operand" | |
152 | (and (match_code "const_double") | |
153 | (match_test "s390_float_const_zero_p (op)"))) | |
154 | ||
155 | ||
156 | (define_constraint "I" | |
157 | "An 8-bit constant (0..255)" | |
158 | (and (match_code "const_int") | |
99908681 | 159 | (match_test "(unsigned HOST_WIDE_INT) ival <= 255"))) |
59bc01b3 | 160 | |
161 | ||
162 | (define_constraint "J" | |
163 | "A 12-bit constant (0..4095)" | |
164 | (and (match_code "const_int") | |
99908681 | 165 | (match_test "(unsigned HOST_WIDE_INT) ival <= 4095"))) |
59bc01b3 | 166 | |
167 | ||
168 | (define_constraint "K" | |
169 | "A 16-bit constant (-32768..32767)" | |
170 | (and (match_code "const_int") | |
171 | (match_test "ival >= -32768 && ival <= 32767"))) | |
172 | ||
173 | ||
59bc01b3 | 174 | (define_constraint "L" |
175 | "Value appropriate as displacement. | |
176 | (0..4095) for short displacement | |
177 | (-524288..524287) for long displacement" | |
178 | (and (match_code "const_int") | |
179 | (match_test "TARGET_LONG_DISPLACEMENT ? | |
180 | (ival >= -524288 && ival <= 524287) | |
181 | : (ival >= 0 && ival <= 4095)"))) | |
182 | ||
183 | ||
184 | (define_constraint "M" | |
185 | "Constant integer with a value of 0x7fffffff" | |
186 | (and (match_code "const_int") | |
187 | (match_test "ival == 2147483647"))) | |
188 | ||
189 | ||
190 | (define_constraint "P" | |
191 | "@internal | |
192 | Any integer constant that can be loaded without literal pool" | |
193 | (and (match_code "const_int") | |
194 | (match_test "legitimate_reload_constant_p (GEN_INT (ival))"))) | |
195 | ||
196 | ||
197 | (define_address_constraint "Y" | |
2be7449b | 198 | "Address style operand without index register" |
59bc01b3 | 199 | |
2be7449b | 200 | ;; Simply check for base + offset style operands. Reload will take |
201 | ;; care of making sure we have a proper base register. | |
59bc01b3 | 202 | |
2be7449b | 203 | (match_test "s390_decompose_addrstyle_without_index (op, NULL, NULL)" )) |
59bc01b3 | 204 | |
205 | ||
206 | ;; N -- Multiple letter constraint followed by 4 parameter letters. | |
207 | ;; 0..9,x: number of the part counting from most to least significant | |
9f19cc6b | 208 | ;; S,H,Q: mode of the part |
59bc01b3 | 209 | ;; D,S,H: mode of the containing operand |
210 | ;; 0,F: value of the other parts (F = all bits set) | |
211 | ;; | |
212 | ;; The constraint matches if the specified part of a constant | |
213 | ;; has a value different from its other parts. If the letter x | |
214 | ;; is specified instead of a part number, the constraint matches | |
215 | ;; if there is any single part with non-default value. | |
216 | ;; | |
ffead1ca | 217 | ;; The following patterns define only those constraints that are actually |
218 | ;; used in s390.md. If you need an additional one, simply add it in the | |
219 | ;; obvious way. Function s390_N_constraint_str is ready to handle all | |
59bc01b3 | 220 | ;; combinations. |
221 | ;; | |
222 | ||
223 | ||
224 | (define_constraint "NxQS0" | |
225 | "@internal" | |
226 | (and (match_code "const_int") | |
227 | (match_test "s390_N_constraint_str (\"xQS0\", ival)"))) | |
228 | ||
229 | ||
9f19cc6b | 230 | (define_constraint "NxHD0" |
231 | "@internal" | |
232 | (and (match_code "const_int") | |
233 | (match_test "s390_N_constraint_str (\"xHD0\", ival)"))) | |
234 | ||
235 | ||
236 | (define_constraint "NxSD0" | |
237 | "@internal" | |
238 | (and (match_code "const_int") | |
239 | (match_test "s390_N_constraint_str (\"xSD0\", ival)"))) | |
240 | ||
241 | ||
59bc01b3 | 242 | (define_constraint "NxQD0" |
243 | "@internal" | |
244 | (and (match_code "const_int") | |
245 | (match_test "s390_N_constraint_str (\"xQD0\", ival)"))) | |
246 | ||
247 | ||
248 | (define_constraint "N3HD0" | |
249 | "@internal" | |
250 | (and (match_code "const_int") | |
251 | (match_test "s390_N_constraint_str (\"3HD0\", ival)"))) | |
252 | ||
253 | ||
254 | (define_constraint "N2HD0" | |
255 | "@internal" | |
256 | (and (match_code "const_int") | |
257 | (match_test "s390_N_constraint_str (\"2HD0\", ival)"))) | |
258 | ||
259 | ||
260 | (define_constraint "N1SD0" | |
261 | "@internal" | |
262 | (and (match_code "const_int") | |
263 | (match_test "s390_N_constraint_str (\"1SD0\", ival)"))) | |
264 | ||
265 | ||
266 | (define_constraint "N1HS0" | |
267 | "@internal" | |
268 | (and (match_code "const_int") | |
269 | (match_test "s390_N_constraint_str (\"1HS0\", ival)"))) | |
270 | ||
271 | ||
272 | (define_constraint "N1HD0" | |
273 | "@internal" | |
274 | (and (match_code "const_int") | |
275 | (match_test "s390_N_constraint_str (\"1HD0\", ival)"))) | |
276 | ||
277 | ||
278 | (define_constraint "N0SD0" | |
279 | "@internal" | |
280 | (and (match_code "const_int") | |
281 | (match_test "s390_N_constraint_str (\"0SD0\", ival)"))) | |
282 | ||
283 | ||
284 | (define_constraint "N0HS0" | |
285 | "@internal" | |
286 | (and (match_code "const_int") | |
287 | (match_test "s390_N_constraint_str (\"0HS0\", ival)"))) | |
288 | ||
289 | ||
290 | (define_constraint "N0HD0" | |
291 | "@internal" | |
292 | (and (match_code "const_int") | |
293 | (match_test "s390_N_constraint_str (\"0HD0\", ival)"))) | |
294 | ||
295 | ||
296 | (define_constraint "NxQDF" | |
297 | "@internal" | |
298 | (and (match_code "const_int") | |
299 | (match_test "s390_N_constraint_str (\"xQDF\", ival)"))) | |
300 | ||
301 | ||
302 | (define_constraint "N1SDF" | |
303 | "@internal" | |
304 | (and (match_code "const_int") | |
305 | (match_test "s390_N_constraint_str (\"1SDF\", ival)"))) | |
306 | ||
307 | ||
308 | (define_constraint "N0SDF" | |
309 | "@internal" | |
310 | (and (match_code "const_int") | |
311 | (match_test "s390_N_constraint_str (\"0SDF\", ival)"))) | |
312 | ||
313 | ||
314 | (define_constraint "N3HDF" | |
315 | "@internal" | |
316 | (and (match_code "const_int") | |
317 | (match_test "s390_N_constraint_str (\"3HDF\", ival)"))) | |
318 | ||
319 | ||
320 | (define_constraint "N2HDF" | |
321 | "@internal" | |
322 | (and (match_code "const_int") | |
323 | (match_test "s390_N_constraint_str (\"2HDF\", ival)"))) | |
324 | ||
325 | ||
326 | (define_constraint "N1HDF" | |
327 | "@internal" | |
328 | (and (match_code "const_int") | |
329 | (match_test "s390_N_constraint_str (\"1HDF\", ival)"))) | |
330 | ||
331 | ||
332 | (define_constraint "N0HDF" | |
333 | "@internal" | |
334 | (and (match_code "const_int") | |
335 | (match_test "s390_N_constraint_str (\"0HDF\", ival)"))) | |
336 | ||
337 | ||
338 | (define_constraint "N0HSF" | |
339 | "@internal" | |
340 | (and (match_code "const_int") | |
341 | (match_test "s390_N_constraint_str (\"0HSF\", ival)"))) | |
342 | ||
343 | ||
344 | (define_constraint "N1HSF" | |
345 | "@internal" | |
346 | (and (match_code "const_int") | |
347 | (match_test "s390_N_constraint_str (\"1HSF\", ival)"))) | |
348 | ||
349 | ||
350 | (define_constraint "NxQSF" | |
351 | "@internal" | |
352 | (and (match_code "const_int") | |
353 | (match_test "s390_N_constraint_str (\"xQSF\", ival)"))) | |
354 | ||
355 | ||
356 | (define_constraint "NxQHF" | |
357 | "@internal" | |
358 | (and (match_code "const_int") | |
359 | (match_test "s390_N_constraint_str (\"xQHF\", ival)"))) | |
360 | ||
361 | ||
362 | (define_constraint "NxQH0" | |
363 | "@internal" | |
364 | (and (match_code "const_int") | |
365 | (match_test "s390_N_constraint_str (\"xQH0\", ival)"))) | |
366 | ||
e64f5133 | 367 | (define_constraint "NxxDw" |
0d46035f | 368 | "@internal" |
369 | (and (match_code "const_int") | |
e64f5133 | 370 | (match_test "s390_contiguous_bitmask_p (ival, true, 64, NULL, NULL)"))) |
59bc01b3 | 371 | |
0d46035f | 372 | (define_constraint "NxxSq" |
373 | "@internal" | |
374 | (and (match_code "const_int") | |
e64f5133 | 375 | (match_test "s390_contiguous_bitmask_p (ival, false, 32, NULL, NULL)"))) |
376 | ||
377 | (define_constraint "NxxSw" | |
378 | "@internal" | |
379 | (and (match_code "const_int") | |
380 | (match_test "s390_contiguous_bitmask_p (ival, true, 32, NULL, NULL)"))) | |
59bc01b3 | 381 | |
382 | ;; | |
383 | ;; Double-letter constraints starting with O follow. | |
384 | ;; | |
385 | ||
386 | ||
387 | (define_constraint "Os" | |
388 | "@internal | |
389 | Signed extended immediate value (-2G .. 2G-1). | |
390 | This constraint will only match if the machine provides | |
391 | the extended-immediate facility." | |
392 | (and (match_code "const_int") | |
393 | (match_test "s390_O_constraint_str ('s', ival)"))) | |
394 | ||
395 | ||
396 | (define_constraint "Op" | |
397 | "@internal | |
398 | Positive extended immediate value (0 .. 4G-1). | |
399 | This constraint will only match if the machine provides | |
400 | the extended-immediate facility." | |
401 | (and (match_code "const_int") | |
402 | (match_test "s390_O_constraint_str ('p', ival)"))) | |
403 | ||
404 | ||
405 | (define_constraint "On" | |
406 | "@internal | |
29847ec4 | 407 | Negative extended immediate value (-4G+1 .. -1). |
59bc01b3 | 408 | This constraint will only match if the machine provides |
409 | the extended-immediate facility." | |
410 | (and (match_code "const_int") | |
411 | (match_test "s390_O_constraint_str ('n', ival)"))) | |
412 | ||
413 | ||
80fc7f56 | 414 | ;; |
415 | ;; Vector constraints follow. | |
416 | ;; | |
417 | ||
418 | (define_constraint "j00" | |
419 | "Zero scalar or vector constant" | |
420 | (match_test "op == CONST0_RTX (GET_MODE (op))")) | |
421 | ||
422 | (define_constraint "jm1" | |
423 | "All one bit scalar or vector constant" | |
424 | (match_test "op == CONSTM1_RTX (GET_MODE (op))")) | |
425 | ||
4c715561 | 426 | ; vector generate mask operand - support for up to 64 bit elements |
80fc7f56 | 427 | (define_constraint "jxx" |
428 | "@internal" | |
429 | (and (match_code "const_vector") | |
430 | (match_test "s390_contiguous_bitmask_vector_p (op, NULL, NULL)"))) | |
431 | ||
4c715561 | 432 | ; vector generate byte mask operand - this is only supposed to deal |
433 | ; with real vectors 128 bit values of being either 0 or -1 are handled | |
434 | ; with j00 and jm1 | |
80fc7f56 | 435 | (define_constraint "jyy" |
436 | "@internal" | |
437 | (and (match_code "const_vector") | |
438 | (match_test "s390_bytemask_vector_p (op, NULL)"))) | |
439 | ||
4c715561 | 440 | ; vector replicate immediate operand - support for up to 64 bit elements |
80fc7f56 | 441 | (define_constraint "jKK" |
442 | "@internal" | |
4c715561 | 443 | (and (and (and (match_code "const_vector") |
444 | (match_test "const_vec_duplicate_p (op)")) | |
445 | (match_test "GET_MODE_UNIT_SIZE (GET_MODE (op)) <= 8")) | |
80fc7f56 | 446 | (match_test "satisfies_constraint_K (XVECEXP (op, 0, 0))"))) |
59bc01b3 | 447 | |
6191f2a0 | 448 | (define_constraint "jm6" |
449 | "@internal An integer operand with the lowest order 6 bits all ones." | |
450 | (match_operand 0 "const_int_6bitset_operand")) | |
59bc01b3 | 451 | |
452 | ;; | |
453 | ;; Memory constraints follow. | |
454 | ;; | |
455 | ||
456 | (define_memory_constraint "Q" | |
457 | "Memory reference without index register and with short displacement" | |
458 | (match_test "s390_mem_constraint (\"Q\", op)")) | |
459 | ||
460 | ||
59bc01b3 | 461 | (define_memory_constraint "R" |
462 | "Memory reference with index register and short displacement" | |
463 | (match_test "s390_mem_constraint (\"R\", op)")) | |
464 | ||
465 | ||
466 | (define_memory_constraint "S" | |
467 | "Memory reference without index register but with long displacement" | |
468 | (match_test "s390_mem_constraint (\"S\", op)")) | |
469 | ||
470 | ||
471 | (define_memory_constraint "T" | |
472 | "Memory reference with index register and long displacement" | |
473 | (match_test "s390_mem_constraint (\"T\", op)")) | |
474 | ||
475 | ||
e68d6a13 | 476 | (define_memory_constraint "b" |
477 | "Memory reference whose address is a naturally aligned symbol reference." | |
478 | (match_test "MEM_P (op) | |
479 | && s390_check_symref_alignment (XEXP (op, 0), | |
480 | GET_MODE_SIZE (GET_MODE (op)))")) | |
481 | ||
e68d6a13 | 482 | ; This defines 'm' as normal memory constraint. This is only possible |
483 | ; since the standard memory constraint is re-defined in s390.h using | |
484 | ; the TARGET_MEM_CONSTRAINT macro. | |
485 | (define_memory_constraint "m" | |
486 | "Matches the most general memory address for pre-z10 machines." | |
7396c35d | 487 | (match_test "s390_mem_constraint (\"T\", op)")) |
59bc01b3 | 488 | |
489 | (define_memory_constraint "AQ" | |
ffead1ca | 490 | "@internal |
59bc01b3 | 491 | Offsettable memory reference without index register and with short displacement" |
492 | (match_test "s390_mem_constraint (\"AQ\", op)")) | |
493 | ||
494 | ||
495 | (define_memory_constraint "AR" | |
ffead1ca | 496 | "@internal |
59bc01b3 | 497 | Offsettable memory reference with index register and short displacement" |
498 | (match_test "s390_mem_constraint (\"AR\", op)")) | |
499 | ||
500 | ||
501 | (define_memory_constraint "AS" | |
ffead1ca | 502 | "@internal |
59bc01b3 | 503 | Offsettable memory reference without index register but with long displacement" |
504 | (match_test "s390_mem_constraint (\"AS\", op)")) | |
505 | ||
506 | ||
507 | (define_memory_constraint "AT" | |
ffead1ca | 508 | "@internal |
59bc01b3 | 509 | Offsettable memory reference with index register and long displacement" |
510 | (match_test "s390_mem_constraint (\"AT\", op)")) | |
511 | ||
512 | ||
513 | ||
514 | (define_constraint "BQ" | |
ffead1ca | 515 | "@internal |
516 | Memory reference without index register and with short | |
59bc01b3 | 517 | displacement that does *not* refer to a literal pool entry." |
518 | (match_test "s390_mem_constraint (\"BQ\", op)")) | |
519 | ||
520 | ||
521 | (define_constraint "BR" | |
ffead1ca | 522 | "@internal |
59bc01b3 | 523 | Memory reference with index register and short displacement that |
524 | does *not* refer to a literal pool entry. " | |
525 | (match_test "s390_mem_constraint (\"BR\", op)")) | |
526 | ||
527 | ||
528 | (define_constraint "BS" | |
ffead1ca | 529 | "@internal |
59bc01b3 | 530 | Memory reference without index register but with long displacement |
531 | that does *not* refer to a literal pool entry. " | |
532 | (match_test "s390_mem_constraint (\"BS\", op)")) | |
533 | ||
534 | ||
535 | (define_constraint "BT" | |
ffead1ca | 536 | "@internal |
59bc01b3 | 537 | Memory reference with index register and long displacement that |
538 | does *not* refer to a literal pool entry. " | |
539 | (match_test "s390_mem_constraint (\"BT\", op)")) | |
540 | ||
541 | ||
59bc01b3 | 542 | (define_address_constraint "U" |
7396c35d | 543 | "Pointer with short displacement. (deprecated - use ZR)" |
544 | (match_test "s390_mem_constraint (\"ZR\", op)")) | |
59bc01b3 | 545 | |
59bc01b3 | 546 | (define_address_constraint "W" |
7396c35d | 547 | "Pointer with long displacement. (deprecated - use ZT)" |
548 | (match_test "s390_mem_constraint (\"ZT\", op)")) | |
a7b49046 | 549 | |
550 | ||
551 | (define_address_constraint "ZQ" | |
552 | "Pointer without index register and with short displacement." | |
553 | (match_test "s390_mem_constraint (\"ZQ\", op)")) | |
554 | ||
555 | (define_address_constraint "ZR" | |
556 | "Pointer with index register and short displacement." | |
557 | (match_test "s390_mem_constraint (\"ZR\", op)")) | |
558 | ||
559 | (define_address_constraint "ZS" | |
560 | "Pointer without index register but with long displacement." | |
561 | (match_test "s390_mem_constraint (\"ZS\", op)")) | |
562 | ||
563 | (define_address_constraint "ZT" | |
564 | "Pointer with index register and long displacement." | |
565 | (match_test "s390_mem_constraint (\"ZT\", op)")) | |
6dea6aa2 | 566 | |
567 | (define_constraint "ZL" | |
568 | "LARL operand when in 64-bit mode, otherwise nothing." | |
569 | (match_test "TARGET_64BIT && larl_operand (op, VOIDmode)")) |