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2014-11-01 Andrew MacLeod <amacleod@redhat,com>
[thirdparty/gcc.git] / gcc / config / s390 / s390.c
CommitLineData
9db1d521 1/* Subroutines used for code generation on IBM S/390 and zSeries
23a5b65a 2 Copyright (C) 1999-2014 Free Software Foundation, Inc.
9db1d521 3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
963fc8d0
AK		 4 Ulrich Weigand (uweigand@de.ibm.com) and
5 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
9db1d521 6
58add37a 7This file is part of GCC.
9db1d521 8
58add37a
UW		 9GCC is free software; you can redistribute it and/or modify it under
10the terms of the GNU General Public License as published by the Free
2f83c7d6 11Software Foundation; either version 3, or (at your option) any later
58add37a 12version.
9db1d521 13
58add37a
UW		 14GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15WARRANTY; without even the implied warranty of MERCHANTABILITY or
16FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17for more details.
9db1d521
HP		 18
19You should have received a copy of the GNU General Public License
2f83c7d6
NC		 20along with GCC; see the file COPYING3. If not see
21<http://www.gnu.org/licenses/>. */
9db1d521
HP		 22
23#include "config.h"
9db1d521 24#include "system.h"
4977bab6
ZW		 25#include "coretypes.h"
26#include "tm.h"
9db1d521
HP		 27#include "rtl.h"
28#include "tree.h"
d8a2d370
DN		 29#include "print-tree.h"
30#include "stringpool.h"
31#include "stor-layout.h"
32#include "varasm.h"
33#include "calls.h"
9db1d521
HP		 34#include "tm_p.h"
35#include "regs.h"
36#include "hard-reg-set.h"
9db1d521
HP		 37#include "insn-config.h"
38#include "conditions.h"
39#include "output.h"
40#include "insn-attr.h"
41#include "flags.h"
42#include "except.h"
83685514
AM		 43#include "hashtab.h"
44#include "hash-set.h"
45#include "vec.h"
46#include "machmode.h"
47#include "input.h"
9db1d521
HP		 48#include "function.h"
49#include "recog.h"
50#include "expr.h"
7c82a1ed 51#include "reload.h"
718f9c0f 52#include "diagnostic-core.h"
60393bbc
AM		 53#include "predict.h"
54#include "dominance.h"
55#include "cfg.h"
56#include "cfgrtl.h"
57#include "cfganal.h"
58#include "lcm.h"
59#include "cfgbuild.h"
60#include "cfgcleanup.h"
9db1d521
HP		 61#include "basic-block.h"
62#include "ggc.h"
63#include "target.h"
64#include "target-def.h"
0d3c08b6 65#include "debug.h"
f1e639b1 66#include "langhooks.h"
b0710fe1 67#include "insn-codes.h"
a41c6c53 68#include "optabs.h"
2fb9a547 69#include "hash-table.h"
2fb9a547
AM		 70#include "tree-ssa-alias.h"
71#include "internal-fn.h"
72#include "gimple-fold.h"
73#include "tree-eh.h"
74#include "gimple-expr.h"
75#include "is-a.h"
18f429e2 76#include "gimple.h"
45b0be94 77#include "gimplify.h"
6fb5fa3c 78#include "df.h"
ff5b964d 79#include "params.h"
40ac4f73 80#include "cfgloop.h"
96e45421 81#include "opts.h"
4099494d
RS		 82#include "tree-pass.h"
83#include "context.h"
9b2b7279 84#include "builtins.h"
9dc7a9da 85#include "rtl-iter.h"
9db1d521 86
017e0eb9
MD		 87/* Define the specific costs for a given cpu. */
88
f4aa3848 89struct processor_costs
017e0eb9 90{
98fd0d70 91 /* multiplication */
017e0eb9
MD		 92 const int m; /* cost of an M instruction. */
93 const int mghi; /* cost of an MGHI instruction. */
94 const int mh; /* cost of an MH instruction. */
95 const int mhi; /* cost of an MHI instruction. */
2742a1ed 96 const int ml; /* cost of an ML instruction. */
017e0eb9
MD		 97 const int mr; /* cost of an MR instruction. */
98 const int ms; /* cost of an MS instruction. */
99 const int msg; /* cost of an MSG instruction. */
100 const int msgf; /* cost of an MSGF instruction. */
101 const int msgfr; /* cost of an MSGFR instruction. */
102 const int msgr; /* cost of an MSGR instruction. */
103 const int msr; /* cost of an MSR instruction. */
104 const int mult_df; /* cost of multiplication in DFmode. */
f61a2c7d 105 const int mxbr;
98fd0d70 106 /* square root */
f61a2c7d 107 const int sqxbr; /* cost of square root in TFmode. */
2742a1ed
MD		 108 const int sqdbr; /* cost of square root in DFmode. */
109 const int sqebr; /* cost of square root in SFmode. */
98fd0d70 110 /* multiply and add */
b75d6bab
MD		 111 const int madbr; /* cost of multiply and add in DFmode. */
112 const int maebr; /* cost of multiply and add in SFmode. */
98fd0d70 113 /* division */
f61a2c7d 114 const int dxbr;
98fd0d70 115 const int ddbr;
98fd0d70 116 const int debr;
6fa5b390
MD		 117 const int dlgr;
118 const int dlr;
119 const int dr;
120 const int dsgfr;
121 const int dsgr;
017e0eb9
MD		 122};
123
124const struct processor_costs *s390_cost;
125
126static const
f4aa3848 127struct processor_costs z900_cost =
017e0eb9
MD		 128{
129 COSTS_N_INSNS (5), /* M */
130 COSTS_N_INSNS (10), /* MGHI */
131 COSTS_N_INSNS (5), /* MH */
132 COSTS_N_INSNS (4), /* MHI */
2742a1ed 133 COSTS_N_INSNS (5), /* ML */
017e0eb9
MD		 134 COSTS_N_INSNS (5), /* MR */
135 COSTS_N_INSNS (4), /* MS */
136 COSTS_N_INSNS (15), /* MSG */
137 COSTS_N_INSNS (7), /* MSGF */
138 COSTS_N_INSNS (7), /* MSGFR */
139 COSTS_N_INSNS (10), /* MSGR */
140 COSTS_N_INSNS (4), /* MSR */
141 COSTS_N_INSNS (7), /* multiplication in DFmode */
f61a2c7d
AK		 142 COSTS_N_INSNS (13), /* MXBR */
143 COSTS_N_INSNS (136), /* SQXBR */
2742a1ed
MD		 144 COSTS_N_INSNS (44), /* SQDBR */
145 COSTS_N_INSNS (35), /* SQEBR */
b75d6bab
MD		 146 COSTS_N_INSNS (18), /* MADBR */
147 COSTS_N_INSNS (13), /* MAEBR */
f61a2c7d 148 COSTS_N_INSNS (134), /* DXBR */
98fd0d70 149 COSTS_N_INSNS (30), /* DDBR */
98fd0d70 150 COSTS_N_INSNS (27), /* DEBR */
6fa5b390
MD		 151 COSTS_N_INSNS (220), /* DLGR */
152 COSTS_N_INSNS (34), /* DLR */
153 COSTS_N_INSNS (34), /* DR */
154 COSTS_N_INSNS (32), /* DSGFR */
155 COSTS_N_INSNS (32), /* DSGR */
017e0eb9
MD		 156};
157
158static const
f4aa3848 159struct processor_costs z990_cost =
017e0eb9
MD		 160{
161 COSTS_N_INSNS (4), /* M */
162 COSTS_N_INSNS (2), /* MGHI */
163 COSTS_N_INSNS (2), /* MH */
164 COSTS_N_INSNS (2), /* MHI */
2742a1ed 165 COSTS_N_INSNS (4), /* ML */
017e0eb9
MD		 166 COSTS_N_INSNS (4), /* MR */
167 COSTS_N_INSNS (5), /* MS */
168 COSTS_N_INSNS (6), /* MSG */
169 COSTS_N_INSNS (4), /* MSGF */
170 COSTS_N_INSNS (4), /* MSGFR */
171 COSTS_N_INSNS (4), /* MSGR */
172 COSTS_N_INSNS (4), /* MSR */
173 COSTS_N_INSNS (1), /* multiplication in DFmode */
f61a2c7d
AK		 174 COSTS_N_INSNS (28), /* MXBR */
175 COSTS_N_INSNS (130), /* SQXBR */
2742a1ed
MD		 176 COSTS_N_INSNS (66), /* SQDBR */
177 COSTS_N_INSNS (38), /* SQEBR */
b75d6bab
MD		 178 COSTS_N_INSNS (1), /* MADBR */
179 COSTS_N_INSNS (1), /* MAEBR */
f61a2c7d 180 COSTS_N_INSNS (60), /* DXBR */
98fd0d70 181 COSTS_N_INSNS (40), /* DDBR */
142cd70f 182 COSTS_N_INSNS (26), /* DEBR */
6fa5b390
MD		 183 COSTS_N_INSNS (176), /* DLGR */
184 COSTS_N_INSNS (31), /* DLR */
185 COSTS_N_INSNS (31), /* DR */
186 COSTS_N_INSNS (31), /* DSGFR */
187 COSTS_N_INSNS (31), /* DSGR */
017e0eb9
MD		 188};
189
ec24698e 190static const
f4aa3848 191struct processor_costs z9_109_cost =
ec24698e
UW		 192{
193 COSTS_N_INSNS (4), /* M */
194 COSTS_N_INSNS (2), /* MGHI */
195 COSTS_N_INSNS (2), /* MH */
196 COSTS_N_INSNS (2), /* MHI */
197 COSTS_N_INSNS (4), /* ML */
198 COSTS_N_INSNS (4), /* MR */
199 COSTS_N_INSNS (5), /* MS */
200 COSTS_N_INSNS (6), /* MSG */
201 COSTS_N_INSNS (4), /* MSGF */
202 COSTS_N_INSNS (4), /* MSGFR */
203 COSTS_N_INSNS (4), /* MSGR */
204 COSTS_N_INSNS (4), /* MSR */
205 COSTS_N_INSNS (1), /* multiplication in DFmode */
f61a2c7d
AK		 206 COSTS_N_INSNS (28), /* MXBR */
207 COSTS_N_INSNS (130), /* SQXBR */
ec24698e
UW		 208 COSTS_N_INSNS (66), /* SQDBR */
209 COSTS_N_INSNS (38), /* SQEBR */
210 COSTS_N_INSNS (1), /* MADBR */
211 COSTS_N_INSNS (1), /* MAEBR */
f61a2c7d 212 COSTS_N_INSNS (60), /* DXBR */
ec24698e 213 COSTS_N_INSNS (40), /* DDBR */
142cd70f 214 COSTS_N_INSNS (26), /* DEBR */
ec24698e
UW		 215 COSTS_N_INSNS (30), /* DLGR */
216 COSTS_N_INSNS (23), /* DLR */
217 COSTS_N_INSNS (23), /* DR */
218 COSTS_N_INSNS (24), /* DSGFR */
219 COSTS_N_INSNS (24), /* DSGR */
220};
017e0eb9 221
93538e8e
AK		 222static const
223struct processor_costs z10_cost =
224{
9381e3f1
WG		 225 COSTS_N_INSNS (10), /* M */
226 COSTS_N_INSNS (10), /* MGHI */
227 COSTS_N_INSNS (10), /* MH */
228 COSTS_N_INSNS (10), /* MHI */
229 COSTS_N_INSNS (10), /* ML */
230 COSTS_N_INSNS (10), /* MR */
231 COSTS_N_INSNS (10), /* MS */
232 COSTS_N_INSNS (10), /* MSG */
233 COSTS_N_INSNS (10), /* MSGF */
234 COSTS_N_INSNS (10), /* MSGFR */
235 COSTS_N_INSNS (10), /* MSGR */
236 COSTS_N_INSNS (10), /* MSR */
2cdece44 237 COSTS_N_INSNS (1) , /* multiplication in DFmode */
9381e3f1
WG		 238 COSTS_N_INSNS (50), /* MXBR */
239 COSTS_N_INSNS (120), /* SQXBR */
240 COSTS_N_INSNS (52), /* SQDBR */
93538e8e 241 COSTS_N_INSNS (38), /* SQEBR */
2cdece44
WG		 242 COSTS_N_INSNS (1), /* MADBR */
243 COSTS_N_INSNS (1), /* MAEBR */
9381e3f1
WG		 244 COSTS_N_INSNS (111), /* DXBR */
245 COSTS_N_INSNS (39), /* DDBR */
246 COSTS_N_INSNS (32), /* DEBR */
247 COSTS_N_INSNS (160), /* DLGR */
248 COSTS_N_INSNS (71), /* DLR */
249 COSTS_N_INSNS (71), /* DR */
250 COSTS_N_INSNS (71), /* DSGFR */
251 COSTS_N_INSNS (71), /* DSGR */
93538e8e
AK		 252};
253
65b1d8ea
AK		 254static const
255struct processor_costs z196_cost =
256{
257 COSTS_N_INSNS (7), /* M */
258 COSTS_N_INSNS (5), /* MGHI */
259 COSTS_N_INSNS (5), /* MH */
260 COSTS_N_INSNS (5), /* MHI */
261 COSTS_N_INSNS (7), /* ML */
262 COSTS_N_INSNS (7), /* MR */
263 COSTS_N_INSNS (6), /* MS */
264 COSTS_N_INSNS (8), /* MSG */
265 COSTS_N_INSNS (6), /* MSGF */
266 COSTS_N_INSNS (6), /* MSGFR */
267 COSTS_N_INSNS (8), /* MSGR */
268 COSTS_N_INSNS (6), /* MSR */
269 COSTS_N_INSNS (1) , /* multiplication in DFmode */
270 COSTS_N_INSNS (40), /* MXBR B+40 */
271 COSTS_N_INSNS (100), /* SQXBR B+100 */
272 COSTS_N_INSNS (42), /* SQDBR B+42 */
273 COSTS_N_INSNS (28), /* SQEBR B+28 */
274 COSTS_N_INSNS (1), /* MADBR B */
275 COSTS_N_INSNS (1), /* MAEBR B */
276 COSTS_N_INSNS (101), /* DXBR B+101 */
277 COSTS_N_INSNS (29), /* DDBR */
278 COSTS_N_INSNS (22), /* DEBR */
279 COSTS_N_INSNS (160), /* DLGR cracked */
280 COSTS_N_INSNS (160), /* DLR cracked */
281 COSTS_N_INSNS (160), /* DR expanded */
282 COSTS_N_INSNS (160), /* DSGFR cracked */
283 COSTS_N_INSNS (160), /* DSGR cracked */
284};
285
22ac2c2f
AK		 286static const
287struct processor_costs zEC12_cost =
288{
289 COSTS_N_INSNS (7), /* M */
290 COSTS_N_INSNS (5), /* MGHI */
291 COSTS_N_INSNS (5), /* MH */
292 COSTS_N_INSNS (5), /* MHI */
293 COSTS_N_INSNS (7), /* ML */
294 COSTS_N_INSNS (7), /* MR */
295 COSTS_N_INSNS (6), /* MS */
296 COSTS_N_INSNS (8), /* MSG */
297 COSTS_N_INSNS (6), /* MSGF */
298 COSTS_N_INSNS (6), /* MSGFR */
299 COSTS_N_INSNS (8), /* MSGR */
300 COSTS_N_INSNS (6), /* MSR */
301 COSTS_N_INSNS (1) , /* multiplication in DFmode */
302 COSTS_N_INSNS (40), /* MXBR B+40 */
303 COSTS_N_INSNS (100), /* SQXBR B+100 */
304 COSTS_N_INSNS (42), /* SQDBR B+42 */
305 COSTS_N_INSNS (28), /* SQEBR B+28 */
306 COSTS_N_INSNS (1), /* MADBR B */
307 COSTS_N_INSNS (1), /* MAEBR B */
308 COSTS_N_INSNS (131), /* DXBR B+131 */
309 COSTS_N_INSNS (29), /* DDBR */
310 COSTS_N_INSNS (22), /* DEBR */
311 COSTS_N_INSNS (160), /* DLGR cracked */
312 COSTS_N_INSNS (160), /* DLR cracked */
313 COSTS_N_INSNS (160), /* DR expanded */
314 COSTS_N_INSNS (160), /* DSGFR cracked */
315 COSTS_N_INSNS (160), /* DSGR cracked */
316};
317
9db1d521
HP		 318extern int reload_completed;
319
3a892e44 320/* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
775c43d3 321static rtx_insn *last_scheduled_insn;
3a892e44 322
994fe660
UW		 323/* Structure used to hold the components of a S/390 memory
324 address. A legitimate address on S/390 is of the general
325 form
326 base + index + displacement
327 where any of the components is optional.
328
329 base and index are registers of the class ADDR_REGS,
330 displacement is an unsigned 12-bit immediate constant. */
9db1d521
HP		 331
332struct s390_address
333{
334 rtx base;
335 rtx indx;
336 rtx disp;
3ed99cc9 337 bool pointer;
f01cf809 338 bool literal_pool;
9db1d521
HP		 339};
340
f4aa3848 341/* The following structure is embedded in the machine
adf39f8f
AK		 342 specific part of struct function. */
343
d1b38208 344struct GTY (()) s390_frame_layout
adf39f8f
AK		 345{
346 /* Offset within stack frame. */
347 HOST_WIDE_INT gprs_offset;
348 HOST_WIDE_INT f0_offset;
349 HOST_WIDE_INT f4_offset;
350 HOST_WIDE_INT f8_offset;
351 HOST_WIDE_INT backchain_offset;
fb3712f6
AK		 352
353 /* Number of first and last gpr where slots in the register
354 save area are reserved for. */
355 int first_save_gpr_slot;
356 int last_save_gpr_slot;
357
6455a49e
AK		 358 /* Location (FP register number) where GPRs (r0-r15) should
359 be saved to.
360 0 - does not need to be saved at all
361 -1 - stack slot */
362 signed char gpr_save_slots[16];
363
29742ba4 364 /* Number of first and last gpr to be saved, restored. */
4023fb28
UW		 365 int first_save_gpr;
366 int first_restore_gpr;
367 int last_save_gpr;
b767fc11 368 int last_restore_gpr;
4023fb28 369
f4aa3848
AK		 370 /* Bits standing for floating point registers. Set, if the
371 respective register has to be saved. Starting with reg 16 (f0)
adf39f8f 372 at the rightmost bit.
2cf4c39e
AK		 373 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
374 fpr 15 13 11 9 14 12 10 8 7 5 3 1 6 4 2 0
375 reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 */
adf39f8f
AK		 376 unsigned int fpr_bitmap;
377
378 /* Number of floating point registers f8-f15 which must be saved. */
379 int high_fprs;
380
dc4477f5
AK		 381 /* Set if return address needs to be saved.
382 This flag is set by s390_return_addr_rtx if it could not use
383 the initial value of r14 and therefore depends on r14 saved
384 to the stack. */
adf39f8f
AK		 385 bool save_return_addr_p;
386
29742ba4 387 /* Size of stack frame. */
4023fb28 388 HOST_WIDE_INT frame_size;
adf39f8f
AK		 389};
390
391/* Define the structure for the machine field in struct function. */
392
d1b38208 393struct GTY(()) machine_function
adf39f8f
AK		 394{
395 struct s390_frame_layout frame_layout;
fd3cd001 396
585539a1
UW		 397 /* Literal pool base register. */
398 rtx base_reg;
399
91086990
UW		 400 /* True if we may need to perform branch splitting. */
401 bool split_branches_pending_p;
402
7bcebb25 403 bool has_landing_pad_p;
5a3fe9b6
AK		 404
405 /* True if the current function may contain a tbegin clobbering
406 FPRs. */
407 bool tbegin_p;
4023fb28
UW		 408};
409
adf39f8f
AK		 410/* Few accessor macros for struct cfun->machine->s390_frame_layout. */
411
412#define cfun_frame_layout (cfun->machine->frame_layout)
413#define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
6455a49e
AK		 414#define cfun_save_arg_fprs_p (!!(TARGET_64BIT \
415 ? cfun_frame_layout.fpr_bitmap & 0x0f \
416 : cfun_frame_layout.fpr_bitmap & 0x03))
417#define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
9602b6a1 418 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
b89b22fc 419#define cfun_set_fpr_save(REGNO) (cfun->machine->frame_layout.fpr_bitmap |= \
2cf4c39e 420 (1 << (REGNO - FPR0_REGNUM)))
b89b22fc 421#define cfun_fpr_save_p(REGNO) (!!(cfun->machine->frame_layout.fpr_bitmap & \
2cf4c39e 422 (1 << (REGNO - FPR0_REGNUM))))
6455a49e
AK		 423#define cfun_gpr_save_slot(REGNO) \
424 cfun->machine->frame_layout.gpr_save_slots[REGNO]
adf39f8f 425
29a79fcf
UW		 426/* Number of GPRs and FPRs used for argument passing. */
427#define GP_ARG_NUM_REG 5
428#define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
429
b5c67a49
AK		 430/* A couple of shortcuts. */
431#define CONST_OK_FOR_J(x) \
432 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
433#define CONST_OK_FOR_K(x) \
434 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
ec24698e
UW		 435#define CONST_OK_FOR_Os(x) \
436 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
437#define CONST_OK_FOR_Op(x) \
438 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
439#define CONST_OK_FOR_On(x) \
440 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
b5c67a49 441
74aa8b4b
AK		 442#define REGNO_PAIR_OK(REGNO, MODE) \
443 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
444
b0f86a7e 445/* That's the read ahead of the dynamic branch prediction unit in
65b1d8ea
AK		 446 bytes on a z10 (or higher) CPU. */
447#define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
b0f86a7e 448
d0de9e13
DV		 449static const int s390_hotpatch_trampoline_halfwords_default = 12;
450static const int s390_hotpatch_trampoline_halfwords_max = 1000000;
451static int s390_hotpatch_trampoline_halfwords = -1;
452
453/* Return the argument of the given hotpatch attribute or the default value if
454 no argument is present. */
455
456static inline int
457get_hotpatch_attribute (tree hotpatch_attr)
458{
459 const_tree args;
460
461 args = TREE_VALUE (hotpatch_attr);
462
463 return (args) ?
464 TREE_INT_CST_LOW (TREE_VALUE (args)):
465 s390_hotpatch_trampoline_halfwords_default;
466}
467
468/* Check whether the hotpatch attribute is applied to a function and, if it has
469 an argument, the argument is valid. */
470
471static tree
472s390_handle_hotpatch_attribute (tree *node, tree name, tree args,
473 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
474{
475 if (TREE_CODE (*node) != FUNCTION_DECL)
476 {
477 warning (OPT_Wattributes, "%qE attribute only applies to functions",
478 name);
479 *no_add_attrs = true;
480 }
481 else if (args)
482 {
483 tree expr = TREE_VALUE (args);
484
485 if (TREE_CODE (expr) != INTEGER_CST
486 || !INTEGRAL_TYPE_P (TREE_TYPE (expr))
807e902e 487 || wi::gtu_p (expr, s390_hotpatch_trampoline_halfwords_max))
d0de9e13
DV		 488 {
489 error ("requested %qE attribute is not a non-negative integer"
490 " constant or too large (max. %d)", name,
491 s390_hotpatch_trampoline_halfwords_max);
492 *no_add_attrs = true;
493 }
494 }
495
496 return NULL_TREE;
497}
498
499static const struct attribute_spec s390_attribute_table[] = {
500 { "hotpatch", 0, 1, true, false, false, s390_handle_hotpatch_attribute, false
501 },
502 /* End element. */
503 { NULL, 0, 0, false, false, false, NULL, false }
504};
505
5d304e47
AK		 506/* Return the alignment for LABEL. We default to the -falign-labels
507 value except for the literal pool base label. */
508int
509s390_label_align (rtx label)
510{
e8a54173
DM		 511 rtx_insn *prev_insn = prev_active_insn (label);
512 rtx set, src;
5d304e47
AK		 513
514 if (prev_insn == NULL_RTX)
515 goto old;
516
e8a54173 517 set = single_set (prev_insn);
5d304e47 518
e8a54173 519 if (set == NULL_RTX)
5d304e47
AK		 520 goto old;
521
e8a54173 522 src = SET_SRC (set);
5d304e47
AK		 523
524 /* Don't align literal pool base labels. */
e8a54173
DM		 525 if (GET_CODE (src) == UNSPEC
526 && XINT (src, 1) == UNSPEC_MAIN_BASE)
5d304e47
AK		 527 return 0;
528
529 old:
530 return align_labels_log;
531}
532
ef4bddc2 533static machine_mode
c7ff6e7a
AK		 534s390_libgcc_cmp_return_mode (void)
535{
536 return TARGET_64BIT ? DImode : SImode;
537}
538
ef4bddc2 539static machine_mode
c7ff6e7a
AK		 540s390_libgcc_shift_count_mode (void)
541{
542 return TARGET_64BIT ? DImode : SImode;
543}
544
ef4bddc2 545static machine_mode
9602b6a1
AK		 546s390_unwind_word_mode (void)
547{
548 return TARGET_64BIT ? DImode : SImode;
549}
550
4dc19cc0
AK		 551/* Return true if the back end supports mode MODE. */
552static bool
ef4bddc2 553s390_scalar_mode_supported_p (machine_mode mode)
4dc19cc0 554{
9602b6a1
AK		 555 /* In contrast to the default implementation reject TImode constants on 31bit
556 TARGET_ZARCH for ABI compliance. */
557 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
558 return false;
559
4dc19cc0 560 if (DECIMAL_FLOAT_MODE_P (mode))
a9ab39d3 561 return default_decimal_float_supported_p ();
9602b6a1
AK		 562
563 return default_scalar_mode_supported_p (mode);
4dc19cc0
AK		 564}
565
7bcebb25
AK		 566/* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
567
568void
569s390_set_has_landing_pad_p (bool value)
570{
571 cfun->machine->has_landing_pad_p = value;
572}
29a79fcf 573
69950452
AS		 574/* If two condition code modes are compatible, return a condition code
575 mode which is compatible with both. Otherwise, return
576 VOIDmode. */
577
ef4bddc2
RS		 578static machine_mode
579s390_cc_modes_compatible (machine_mode m1, machine_mode m2)
69950452
AS		 580{
581 if (m1 == m2)
582 return m1;
583
584 switch (m1)
585 {
586 case CCZmode:
587 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
588 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
589 return m2;
590 return VOIDmode;
591
592 case CCSmode:
593 case CCUmode:
594 case CCTmode:
595 case CCSRmode:
596 case CCURmode:
597 case CCZ1mode:
598 if (m2 == CCZmode)
599 return m1;
f4aa3848 600
69950452
AS		 601 return VOIDmode;
602
603 default:
604 return VOIDmode;
605 }
606 return VOIDmode;
607}
608
994fe660 609/* Return true if SET either doesn't set the CC register, or else
c7453384 610 the source and destination have matching CC modes and that
994fe660 611 CC mode is at least as constrained as REQ_MODE. */
c7453384 612
3ed99cc9 613static bool
ef4bddc2 614s390_match_ccmode_set (rtx set, machine_mode req_mode)
9db1d521 615{
ef4bddc2 616 machine_mode set_mode;
9db1d521 617
8d933e31 618 gcc_assert (GET_CODE (set) == SET);
9db1d521
HP		 619
620 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
621 return 1;
622
623 set_mode = GET_MODE (SET_DEST (set));
624 switch (set_mode)
625 {
9db1d521 626 case CCSmode:
07893d4f 627 case CCSRmode:
9db1d521 628 case CCUmode:
07893d4f 629 case CCURmode:
ba956982 630 case CCLmode:
07893d4f
UW		 631 case CCL1mode:
632 case CCL2mode:
5d880bd2 633 case CCL3mode:
07893d4f
UW		 634 case CCT1mode:
635 case CCT2mode:
636 case CCT3mode:
637 if (req_mode != set_mode)
ba956982
UW		 638 return 0;
639 break;
07893d4f 640
9db1d521 641 case CCZmode:
07893d4f
UW		 642 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
643 && req_mode != CCSRmode && req_mode != CCURmode)
9db1d521
HP		 644 return 0;
645 break;
0a3bdf9d
UW		 646
647 case CCAPmode:
648 case CCANmode:
649 if (req_mode != CCAmode)
650 return 0;
651 break;
c7453384 652
9db1d521 653 default:
8d933e31 654 gcc_unreachable ();
9db1d521 655 }
c7453384 656
9db1d521
HP		 657 return (GET_MODE (SET_SRC (set)) == set_mode);
658}
659
c7453384
EC		 660/* Return true if every SET in INSN that sets the CC register
661 has source and destination with matching CC modes and that
662 CC mode is at least as constrained as REQ_MODE.
07893d4f 663 If REQ_MODE is VOIDmode, always return false. */
c7453384 664
3ed99cc9 665bool
ef4bddc2 666s390_match_ccmode (rtx_insn *insn, machine_mode req_mode)
9db1d521
HP		 667{
668 int i;
669
07893d4f
UW		 670 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
671 if (req_mode == VOIDmode)
3ed99cc9 672 return false;
07893d4f 673
9db1d521
HP		 674 if (GET_CODE (PATTERN (insn)) == SET)
675 return s390_match_ccmode_set (PATTERN (insn), req_mode);
676
677 if (GET_CODE (PATTERN (insn)) == PARALLEL)
678 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
679 {
680 rtx set = XVECEXP (PATTERN (insn), 0, i);
681 if (GET_CODE (set) == SET)
682 if (!s390_match_ccmode_set (set, req_mode))
3ed99cc9 683 return false;
9db1d521
HP		 684 }
685
3ed99cc9 686 return true;
9db1d521
HP		 687}
688
c7453384 689/* If a test-under-mask instruction can be used to implement
07893d4f 690 (compare (and ... OP1) OP2), return the CC mode required
c7453384 691 to do that. Otherwise, return VOIDmode.
07893d4f
UW		 692 MIXED is true if the instruction can distinguish between
693 CC1 and CC2 for mixed selected bits (TMxx), it is false
694 if the instruction cannot (TM). */
695
ef4bddc2 696machine_mode
3ed99cc9 697s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
07893d4f
UW		 698{
699 int bit0, bit1;
700
701 /* ??? Fixme: should work on CONST_DOUBLE as well. */
702 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
703 return VOIDmode;
704
00bda920
AK		 705 /* Selected bits all zero: CC0.
706 e.g.: int a; if ((a & (16 + 128)) == 0) */
07893d4f
UW		 707 if (INTVAL (op2) == 0)
708 return CCTmode;
709
f4aa3848 710 /* Selected bits all one: CC3.
00bda920 711 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
07893d4f
UW		 712 if (INTVAL (op2) == INTVAL (op1))
713 return CCT3mode;
714
00bda920
AK		 715 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
716 int a;
717 if ((a & (16 + 128)) == 16) -> CCT1
718 if ((a & (16 + 128)) == 128) -> CCT2 */
07893d4f
UW		 719 if (mixed)
720 {
721 bit1 = exact_log2 (INTVAL (op2));
722 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
723 if (bit0 != -1 && bit1 != -1)
724 return bit0 > bit1 ? CCT1mode : CCT2mode;
725 }
726
727 return VOIDmode;
728}
729
c7453384
EC		 730/* Given a comparison code OP (EQ, NE, etc.) and the operands
731 OP0 and OP1 of a COMPARE, return the mode to be used for the
ba956982
UW		 732 comparison. */
733
ef4bddc2 734machine_mode
9c808aad 735s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
ba956982
UW		 736{
737 switch (code)
738 {
739 case EQ:
740 case NE:
26a89301
UW		 741 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
742 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
743 return CCAPmode;
0a3bdf9d 744 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
b5c67a49 745 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
0a3bdf9d 746 return CCAPmode;
3ef093a8
AK		 747 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
748 || GET_CODE (op1) == NEG)
749 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
ba956982
UW		 750 return CCLmode;
751
07893d4f
UW		 752 if (GET_CODE (op0) == AND)
753 {
754 /* Check whether we can potentially do it via TM. */
ef4bddc2 755 machine_mode ccmode;
07893d4f
UW		 756 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
757 if (ccmode != VOIDmode)
758 {
759 /* Relax CCTmode to CCZmode to allow fall-back to AND
760 if that turns out to be beneficial. */
761 return ccmode == CCTmode ? CCZmode : ccmode;
762 }
763 }
764
c7453384 765 if (register_operand (op0, HImode)
07893d4f
UW		 766 && GET_CODE (op1) == CONST_INT
767 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
768 return CCT3mode;
c7453384 769 if (register_operand (op0, QImode)
07893d4f
UW		 770 && GET_CODE (op1) == CONST_INT
771 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
772 return CCT3mode;
773
ba956982
UW		 774 return CCZmode;
775
776 case LE:
777 case LT:
778 case GE:
779 case GT:
00bda920
AK		 780 /* The only overflow condition of NEG and ABS happens when
781 -INT_MAX is used as parameter, which stays negative. So
f4aa3848 782 we have an overflow from a positive value to a negative.
00bda920 783 Using CCAP mode the resulting cc can be used for comparisons. */
26a89301
UW		 784 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
785 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
786 return CCAPmode;
00bda920
AK		 787
788 /* If constants are involved in an add instruction it is possible to use
789 the resulting cc for comparisons with zero. Knowing the sign of the
35fd3193 790 constant the overflow behavior gets predictable. e.g.:
f4aa3848 791 int a, b; if ((b = a + c) > 0)
00bda920 792 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
26a89301 793 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
71ce1a34
AK		 794 && (CONST_OK_FOR_K (INTVAL (XEXP (op0, 1)))
795 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0, 1)), 'O', "Os")
796 /* Avoid INT32_MIN on 32 bit. */
797 && (!TARGET_ZARCH || INTVAL (XEXP (op0, 1)) != -0x7fffffff - 1))))
26a89301
UW		 798 {
799 if (INTVAL (XEXP((op0), 1)) < 0)
800 return CCANmode;
801 else
802 return CCAPmode;
803 }
804 /* Fall through. */
ba956982
UW		 805 case UNORDERED:
806 case ORDERED:
807 case UNEQ:
808 case UNLE:
809 case UNLT:
810 case UNGE:
811 case UNGT:
812 case LTGT:
07893d4f
UW		 813 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
814 && GET_CODE (op1) != CONST_INT)
815 return CCSRmode;
ba956982
UW		 816 return CCSmode;
817
ba956982
UW		 818 case LTU:
819 case GEU:
3ef093a8
AK		 820 if (GET_CODE (op0) == PLUS
821 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
07893d4f
UW		 822 return CCL1mode;
823
824 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
825 && GET_CODE (op1) != CONST_INT)
826 return CCURmode;
827 return CCUmode;
828
829 case LEU:
ba956982 830 case GTU:
3ef093a8
AK		 831 if (GET_CODE (op0) == MINUS
832 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
07893d4f
UW		 833 return CCL2mode;
834
835 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
836 && GET_CODE (op1) != CONST_INT)
837 return CCURmode;
ba956982
UW		 838 return CCUmode;
839
840 default:
8d933e31 841 gcc_unreachable ();
ba956982
UW		 842 }
843}
844
68f9c5e2
UW		 845/* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
846 that we can implement more efficiently. */
847
c354951b
AK		 848static void
849s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
850 bool op0_preserve_value)
68f9c5e2 851{
c354951b
AK		 852 if (op0_preserve_value)
853 return;
854
68f9c5e2
UW		 855 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
856 if ((*code == EQ || *code == NE)
857 && *op1 == const0_rtx
858 && GET_CODE (*op0) == ZERO_EXTRACT
859 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
860 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
861 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
862 {
863 rtx inner = XEXP (*op0, 0);
864 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
865 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
866 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
867
868 if (len > 0 && len < modesize
869 && pos >= 0 && pos + len <= modesize
870 && modesize <= HOST_BITS_PER_WIDE_INT)
871 {
872 unsigned HOST_WIDE_INT block;
873 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
874 block <<= modesize - pos - len;
875
876 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
877 gen_int_mode (block, GET_MODE (inner)));
878 }
879 }
880
881 /* Narrow AND of memory against immediate to enable TM. */
882 if ((*code == EQ || *code == NE)
883 && *op1 == const0_rtx
884 && GET_CODE (*op0) == AND
885 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
886 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
887 {
888 rtx inner = XEXP (*op0, 0);
889 rtx mask = XEXP (*op0, 1);
890
891 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
892 if (GET_CODE (inner) == SUBREG
893 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
894 && (GET_MODE_SIZE (GET_MODE (inner))
895 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
896 && ((INTVAL (mask)
897 & GET_MODE_MASK (GET_MODE (inner))
898 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
899 == 0))
900 inner = SUBREG_REG (inner);
901
902 /* Do not change volatile MEMs. */
903 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
904 {
905 int part = s390_single_part (XEXP (*op0, 1),
906 GET_MODE (inner), QImode, 0);
907 if (part >= 0)
908 {
909 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
910 inner = adjust_address_nv (inner, QImode, part);
911 *op0 = gen_rtx_AND (QImode, inner, mask);
912 }
913 }
914 }
915
916 /* Narrow comparisons against 0xffff to HImode if possible. */
68f9c5e2
UW		 917 if ((*code == EQ || *code == NE)
918 && GET_CODE (*op1) == CONST_INT
919 && INTVAL (*op1) == 0xffff
920 && SCALAR_INT_MODE_P (GET_MODE (*op0))
f4aa3848 921 && (nonzero_bits (*op0, GET_MODE (*op0))
68f9c5e2
UW		 922 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
923 {
924 *op0 = gen_lowpart (HImode, *op0);
925 *op1 = constm1_rtx;
926 }
5b022de5 927
5a3fe9b6 928 /* Remove redundant UNSPEC_STRCMPCC_TO_INT conversions if possible. */
5b022de5 929 if (GET_CODE (*op0) == UNSPEC
5a3fe9b6 930 && XINT (*op0, 1) == UNSPEC_STRCMPCC_TO_INT
5b022de5
UW		 931 && XVECLEN (*op0, 0) == 1
932 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
933 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
934 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
935 && *op1 == const0_rtx)
936 {
937 enum rtx_code new_code = UNKNOWN;
938 switch (*code)
939 {
940 case EQ: new_code = EQ; break;
941 case NE: new_code = NE; break;
02887425
UW		 942 case LT: new_code = GTU; break;
943 case GT: new_code = LTU; break;
944 case LE: new_code = GEU; break;
945 case GE: new_code = LEU; break;
5b022de5
UW		 946 default: break;
947 }
948
949 if (new_code != UNKNOWN)
950 {
951 *op0 = XVECEXP (*op0, 0, 0);
952 *code = new_code;
953 }
954 }
69950452 955
5a3fe9b6 956 /* Remove redundant UNSPEC_CC_TO_INT conversions if possible. */
638e37c2 957 if (GET_CODE (*op0) == UNSPEC
5a3fe9b6 958 && XINT (*op0, 1) == UNSPEC_CC_TO_INT
638e37c2 959 && XVECLEN (*op0, 0) == 1
638e37c2
WG		 960 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
961 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
5a3fe9b6 962 && CONST_INT_P (*op1))
638e37c2
WG		 963 {
964 enum rtx_code new_code = UNKNOWN;
5a3fe9b6 965 switch (GET_MODE (XVECEXP (*op0, 0, 0)))
638e37c2 966 {
5a3fe9b6
AK		 967 case CCZmode:
968 case CCRAWmode:
969 switch (*code)
970 {
971 case EQ: new_code = EQ; break;
972 case NE: new_code = NE; break;
973 default: break;
974 }
975 break;
976 default: break;
638e37c2
WG		 977 }
978
979 if (new_code != UNKNOWN)
980 {
5a3fe9b6
AK		 981 /* For CCRAWmode put the required cc mask into the second
982 operand. */
2561451d
AK		 983 if (GET_MODE (XVECEXP (*op0, 0, 0)) == CCRAWmode
984 && INTVAL (*op1) >= 0 && INTVAL (*op1) <= 3)
5a3fe9b6 985 *op1 = gen_rtx_CONST_INT (VOIDmode, 1 << (3 - INTVAL (*op1)));
638e37c2
WG		 986 *op0 = XVECEXP (*op0, 0, 0);
987 *code = new_code;
988 }
989 }
990
69950452
AS		 991 /* Simplify cascaded EQ, NE with const0_rtx. */
992 if ((*code == NE || *code == EQ)
993 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
994 && GET_MODE (*op0) == SImode
995 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
996 && REG_P (XEXP (*op0, 0))
997 && XEXP (*op0, 1) == const0_rtx
998 && *op1 == const0_rtx)
999 {
1000 if ((*code == EQ && GET_CODE (*op0) == NE)
1001 || (*code == NE && GET_CODE (*op0) == EQ))
1002 *code = EQ;
1003 else
1004 *code = NE;
1005 *op0 = XEXP (*op0, 0);
1006 }
c5b2a111
UW		 1007
1008 /* Prefer register over memory as first operand. */
1009 if (MEM_P (*op0) && REG_P (*op1))
1010 {
1011 rtx tem = *op0; *op0 = *op1; *op1 = tem;
c354951b 1012 *code = (int)swap_condition ((enum rtx_code)*code);
c5b2a111 1013 }
68f9c5e2
UW		 1014}
1015
6590e19a
UW		 1016/* Emit a compare instruction suitable to implement the comparison
1017 OP0 CODE OP1. Return the correct condition RTL to be placed in
1018 the IF_THEN_ELSE of the conditional branch testing the result. */
1019
1020rtx
1021s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
1022{
ef4bddc2 1023 machine_mode mode = s390_select_ccmode (code, op0, op1);
4a77c72b 1024 rtx cc;
6590e19a 1025
e0374221 1026 /* Do not output a redundant compare instruction if a compare_and_swap
69950452 1027 pattern already computed the result and the machine modes are compatible. */
4a77c72b
PB		 1028 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
1029 {
1030 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
1031 == GET_MODE (op0));
1032 cc = op0;
1033 }
e0374221
AS		 1034 else
1035 {
4a77c72b 1036 cc = gen_rtx_REG (mode, CC_REGNUM);
e0374221 1037 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
e0374221 1038 }
4a77c72b 1039
f4aa3848 1040 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
6590e19a
UW		 1041}
1042
0a2aaacc 1043/* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
8bb501bb
AK		 1044 matches CMP.
1045 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
1046 conditional branch testing the result. */
1047
1048static rtx
78ce265b
RH		 1049s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem,
1050 rtx cmp, rtx new_rtx)
8bb501bb 1051{
78ce265b
RH		 1052 emit_insn (gen_atomic_compare_and_swapsi_internal (old, mem, cmp, new_rtx));
1053 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM),
1054 const0_rtx);
8bb501bb
AK		 1055}
1056
5a3fe9b6
AK		 1057/* Emit a jump instruction to TARGET and return it. If COND is
1058 NULL_RTX, emit an unconditional jump, else a conditional jump under
1059 condition COND. */
6590e19a 1060
775c43d3 1061rtx_insn *
6590e19a
UW		 1062s390_emit_jump (rtx target, rtx cond)
1063{
1064 rtx insn;
1065
1066 target = gen_rtx_LABEL_REF (VOIDmode, target);
1067 if (cond)
1068 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
1069
1070 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
5a3fe9b6 1071 return emit_jump_insn (insn);
6590e19a
UW		 1072}
1073
c7453384 1074/* Return branch condition mask to implement a branch
5b022de5 1075 specified by CODE. Return -1 for invalid comparisons. */
ba956982 1076
0bfc3f69 1077int
9c808aad 1078s390_branch_condition_mask (rtx code)
c7453384 1079{
ba956982
UW		 1080 const int CC0 = 1 << 3;
1081 const int CC1 = 1 << 2;
1082 const int CC2 = 1 << 1;
1083 const int CC3 = 1 << 0;
1084
8d933e31
AS		 1085 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
1086 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
5a3fe9b6
AK		 1087 gcc_assert (XEXP (code, 1) == const0_rtx
1088 || (GET_MODE (XEXP (code, 0)) == CCRAWmode
1089 && CONST_INT_P (XEXP (code, 1))));
1090
ba956982
UW		 1091
1092 switch (GET_MODE (XEXP (code, 0)))
1093 {
1094 case CCZmode:
69950452 1095 case CCZ1mode:
ba956982
UW		 1096 switch (GET_CODE (code))
1097 {
1098 case EQ: return CC0;
1099 case NE: return CC1 | CC2 | CC3;
5b022de5 1100 default: return -1;
ba956982
UW		 1101 }
1102 break;
1103
07893d4f
UW		 1104 case CCT1mode:
1105 switch (GET_CODE (code))
1106 {
1107 case EQ: return CC1;
1108 case NE: return CC0 | CC2 | CC3;
5b022de5 1109 default: return -1;
07893d4f
UW		 1110 }
1111 break;
1112
1113 case CCT2mode:
1114 switch (GET_CODE (code))
1115 {
1116 case EQ: return CC2;
1117 case NE: return CC0 | CC1 | CC3;
5b022de5 1118 default: return -1;
07893d4f
UW		 1119 }
1120 break;
1121
1122 case CCT3mode:
1123 switch (GET_CODE (code))
1124 {
1125 case EQ: return CC3;
1126 case NE: return CC0 | CC1 | CC2;
5b022de5 1127 default: return -1;
07893d4f
UW		 1128 }
1129 break;
1130
ba956982
UW		 1131 case CCLmode:
1132 switch (GET_CODE (code))
1133 {
1134 case EQ: return CC0 | CC2;
1135 case NE: return CC1 | CC3;
5b022de5 1136 default: return -1;
07893d4f
UW		 1137 }
1138 break;
1139
1140 case CCL1mode:
1141 switch (GET_CODE (code))
1142 {
1143 case LTU: return CC2 | CC3; /* carry */
1144 case GEU: return CC0 | CC1; /* no carry */
5b022de5 1145 default: return -1;
07893d4f
UW		 1146 }
1147 break;
1148
1149 case CCL2mode:
1150 switch (GET_CODE (code))
1151 {
1152 case GTU: return CC0 | CC1; /* borrow */
1153 case LEU: return CC2 | CC3; /* no borrow */
5b022de5 1154 default: return -1;
ba956982
UW		 1155 }
1156 break;
1157
5d880bd2
UW		 1158 case CCL3mode:
1159 switch (GET_CODE (code))
1160 {
1161 case EQ: return CC0 | CC2;
1162 case NE: return CC1 | CC3;
1163 case LTU: return CC1;
1164 case GTU: return CC3;
1165 case LEU: return CC1 | CC2;
1166 case GEU: return CC2 | CC3;
5b022de5 1167 default: return -1;
5d880bd2
UW		 1168 }
1169
ba956982
UW		 1170 case CCUmode:
1171 switch (GET_CODE (code))
1172 {
1173 case EQ: return CC0;
1174 case NE: return CC1 | CC2 | CC3;
1175 case LTU: return CC1;
1176 case GTU: return CC2;
1177 case LEU: return CC0 | CC1;
1178 case GEU: return CC0 | CC2;
5b022de5 1179 default: return -1;
ba956982
UW		 1180 }
1181 break;
1182
07893d4f
UW		 1183 case CCURmode:
1184 switch (GET_CODE (code))
1185 {
1186 case EQ: return CC0;
1187 case NE: return CC2 | CC1 | CC3;
1188 case LTU: return CC2;
1189 case GTU: return CC1;
1190 case LEU: return CC0 | CC2;
1191 case GEU: return CC0 | CC1;
5b022de5 1192 default: return -1;
07893d4f
UW		 1193 }
1194 break;
1195
0a3bdf9d
UW		 1196 case CCAPmode:
1197 switch (GET_CODE (code))
1198 {
1199 case EQ: return CC0;
1200 case NE: return CC1 | CC2 | CC3;
1201 case LT: return CC1 | CC3;
1202 case GT: return CC2;
1203 case LE: return CC0 | CC1 | CC3;
1204 case GE: return CC0 | CC2;
5b022de5 1205 default: return -1;
0a3bdf9d
UW		 1206 }
1207 break;
1208
1209 case CCANmode:
1210 switch (GET_CODE (code))
1211 {
1212 case EQ: return CC0;
1213 case NE: return CC1 | CC2 | CC3;
1214 case LT: return CC1;
1215 case GT: return CC2 | CC3;
1216 case LE: return CC0 | CC1;
1217 case GE: return CC0 | CC2 | CC3;
5b022de5 1218 default: return -1;
0a3bdf9d
UW		 1219 }
1220 break;
1221
ba956982
UW		 1222 case CCSmode:
1223 switch (GET_CODE (code))
1224 {
1225 case EQ: return CC0;
1226 case NE: return CC1 | CC2 | CC3;
1227 case LT: return CC1;
1228 case GT: return CC2;
1229 case LE: return CC0 | CC1;
1230 case GE: return CC0 | CC2;
1231 case UNORDERED: return CC3;
1232 case ORDERED: return CC0 | CC1 | CC2;
1233 case UNEQ: return CC0 | CC3;
1234 case UNLT: return CC1 | CC3;
1235 case UNGT: return CC2 | CC3;
1236 case UNLE: return CC0 | CC1 | CC3;
1237 case UNGE: return CC0 | CC2 | CC3;
1238 case LTGT: return CC1 | CC2;
5b022de5 1239 default: return -1;
ba956982 1240 }
07893d4f
UW		 1241 break;
1242
1243 case CCSRmode:
1244 switch (GET_CODE (code))
1245 {
1246 case EQ: return CC0;
1247 case NE: return CC2 | CC1 | CC3;
1248 case LT: return CC2;
1249 case GT: return CC1;
1250 case LE: return CC0 | CC2;
1251 case GE: return CC0 | CC1;
1252 case UNORDERED: return CC3;
1253 case ORDERED: return CC0 | CC2 | CC1;
1254 case UNEQ: return CC0 | CC3;
1255 case UNLT: return CC2 | CC3;
1256 case UNGT: return CC1 | CC3;
1257 case UNLE: return CC0 | CC2 | CC3;
1258 case UNGE: return CC0 | CC1 | CC3;
1259 case LTGT: return CC2 | CC1;
5b022de5 1260 default: return -1;
07893d4f
UW		 1261 }
1262 break;
ba956982 1263
5a3fe9b6
AK		 1264 case CCRAWmode:
1265 switch (GET_CODE (code))
1266 {
1267 case EQ:
1268 return INTVAL (XEXP (code, 1));
1269 case NE:
1270 return (INTVAL (XEXP (code, 1))) ^ 0xf;
1271 default:
1272 gcc_unreachable ();
1273 }
1274
ba956982 1275 default:
5b022de5 1276 return -1;
ba956982
UW		 1277 }
1278}
1279
963fc8d0
AK		 1280
1281/* Return branch condition mask to implement a compare and branch
1282 specified by CODE. Return -1 for invalid comparisons. */
1283
1284int
1285s390_compare_and_branch_condition_mask (rtx code)
1286{
1287 const int CC0 = 1 << 3;
1288 const int CC1 = 1 << 2;
1289 const int CC2 = 1 << 1;
1290
1291 switch (GET_CODE (code))
1292 {
1293 case EQ:
1294 return CC0;
1295 case NE:
1296 return CC1 | CC2;
1297 case LT:
1298 case LTU:
1299 return CC1;
1300 case GT:
1301 case GTU:
1302 return CC2;
1303 case LE:
1304 case LEU:
1305 return CC0 | CC1;
1306 case GE:
1307 case GEU:
1308 return CC0 | CC2;
1309 default:
1310 gcc_unreachable ();
1311 }
1312 return -1;
1313}
1314
c7453384
EC		 1315/* If INV is false, return assembler mnemonic string to implement
1316 a branch specified by CODE. If INV is true, return mnemonic
ba956982
UW		 1317 for the corresponding inverted branch. */
1318
1319static const char *
9c808aad 1320s390_branch_condition_mnemonic (rtx code, int inv)
ba956982 1321{
963fc8d0
AK		 1322 int mask;
1323
0139adca 1324 static const char *const mnemonic[16] =
ba956982
UW		 1325 {
1326 NULL, "o", "h", "nle",
1327 "l", "nhe", "lh", "ne",
1328 "e", "nlh", "he", "nl",
1329 "le", "nh", "no", NULL
1330 };
1331
963fc8d0
AK		 1332 if (GET_CODE (XEXP (code, 0)) == REG
1333 && REGNO (XEXP (code, 0)) == CC_REGNUM
5a3fe9b6
AK		 1334 && (XEXP (code, 1) == const0_rtx
1335 || (GET_MODE (XEXP (code, 0)) == CCRAWmode
1336 && CONST_INT_P (XEXP (code, 1)))))
963fc8d0
AK		 1337 mask = s390_branch_condition_mask (code);
1338 else
1339 mask = s390_compare_and_branch_condition_mask (code);
1340
5b022de5 1341 gcc_assert (mask >= 0);
ba956982
UW		 1342
1343 if (inv)
1344 mask ^= 15;
1345
8d933e31 1346 gcc_assert (mask >= 1 && mask <= 14);
ba956982
UW		 1347
1348 return mnemonic[mask];
1349}
1350
f19a9af7
AK		 1351/* Return the part of op which has a value different from def.
1352 The size of the part is determined by mode.
38899e29 1353 Use this function only if you already know that op really
f19a9af7 1354 contains such a part. */
4023fb28 1355
f19a9af7 1356unsigned HOST_WIDE_INT
ef4bddc2 1357s390_extract_part (rtx op, machine_mode mode, int def)
4023fb28 1358{
f19a9af7
AK		 1359 unsigned HOST_WIDE_INT value = 0;
1360 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1361 int part_bits = GET_MODE_BITSIZE (mode);
c4d50129
AK		 1362 unsigned HOST_WIDE_INT part_mask
1363 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
f19a9af7 1364 int i;
38899e29 1365
f19a9af7 1366 for (i = 0; i < max_parts; i++)
4023fb28 1367 {
f19a9af7
AK		 1368 if (i == 0)
1369 value = (unsigned HOST_WIDE_INT) INTVAL (op);
4023fb28 1370 else
f19a9af7 1371 value >>= part_bits;
38899e29 1372
f19a9af7
AK		 1373 if ((value & part_mask) != (def & part_mask))
1374 return value & part_mask;
4023fb28 1375 }
38899e29 1376
8d933e31 1377 gcc_unreachable ();
4023fb28
UW		 1378}
1379
1380/* If OP is an integer constant of mode MODE with exactly one
f19a9af7
AK		 1381 part of mode PART_MODE unequal to DEF, return the number of that
1382 part. Otherwise, return -1. */
4023fb28
UW		 1383
1384int
38899e29 1385s390_single_part (rtx op,
ef4bddc2
RS		 1386 machine_mode mode,
1387 machine_mode part_mode,
f19a9af7
AK		 1388 int def)
1389{
1390 unsigned HOST_WIDE_INT value = 0;
1391 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
c4d50129
AK		 1392 unsigned HOST_WIDE_INT part_mask
1393 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
f19a9af7
AK		 1394 int i, part = -1;
1395
1396 if (GET_CODE (op) != CONST_INT)
1397 return -1;
38899e29 1398
f19a9af7
AK		 1399 for (i = 0; i < n_parts; i++)
1400 {
1401 if (i == 0)
1402 value = (unsigned HOST_WIDE_INT) INTVAL (op);
4023fb28 1403 else
f19a9af7 1404 value >>= GET_MODE_BITSIZE (part_mode);
38899e29 1405
f19a9af7
AK		 1406 if ((value & part_mask) != (def & part_mask))
1407 {
1408 if (part != -1)
1409 return -1;
1410 else
1411 part = i;
1412 }
4023fb28 1413 }
f19a9af7 1414 return part == -1 ? -1 : n_parts - 1 - part;
4023fb28
UW		 1415}
1416
963fc8d0
AK		 1417/* Return true if IN contains a contiguous bitfield in the lower SIZE
1418 bits and no other bits are set in IN. POS and LENGTH can be used
1419 to obtain the start position and the length of the bitfield.
1420
1421 POS gives the position of the first bit of the bitfield counting
1422 from the lowest order bit starting with zero. In order to use this
1423 value for S/390 instructions this has to be converted to "bits big
1424 endian" style. */
1425
1426bool
1427s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1428 int *pos, int *length)
1429{
1430 int tmp_pos = 0;
1431 int tmp_length = 0;
1432 int i;
1433 unsigned HOST_WIDE_INT mask = 1ULL;
1434 bool contiguous = false;
1435
1436 for (i = 0; i < size; mask <<= 1, i++)
1437 {
1438 if (contiguous)
1439 {
1440 if (mask & in)
1441 tmp_length++;
1442 else
1443 break;
1444 }
1445 else
1446 {
1447 if (mask & in)
1448 {
1449 contiguous = true;
1450 tmp_length++;
1451 }
1452 else
1453 tmp_pos++;
1454 }
1455 }
1456
1457 if (!tmp_length)
1458 return false;
1459
1460 /* Calculate a mask for all bits beyond the contiguous bits. */
1461 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1462
1463 if (mask & in)
1464 return false;
1465
1466 if (tmp_length + tmp_pos - 1 > size)
1467 return false;
1468
1469 if (length)
1470 *length = tmp_length;
1471
1472 if (pos)
1473 *pos = tmp_pos;
1474
1475 return true;
1476}
1477
1a2e356e
RH		 1478/* Check whether a rotate of ROTL followed by an AND of CONTIG is
1479 equivalent to a shift followed by the AND. In particular, CONTIG
1480 should not overlap the (rotated) bit 0/bit 63 gap. Negative values
1481 for ROTL indicate a rotate to the right. */
1482
1483bool
1484s390_extzv_shift_ok (int bitsize, int rotl, unsigned HOST_WIDE_INT contig)
1485{
1486 int pos, len;
1487 bool ok;
1488
1489 ok = s390_contiguous_bitmask_p (contig, bitsize, &pos, &len);
1490 gcc_assert (ok);
1491
1492 return ((rotl >= 0 && rotl <= pos)
1493 || (rotl < 0 && -rotl <= bitsize - len - pos));
1494}
1495
c7453384
EC		 1496/* Check whether we can (and want to) split a double-word
1497 move in mode MODE from SRC to DST into two single-word
dc65c307
UW		 1498 moves, moving the subword FIRST_SUBWORD first. */
1499
1500bool
ef4bddc2 1501s390_split_ok_p (rtx dst, rtx src, machine_mode mode, int first_subword)
dc65c307
UW		 1502{
1503 /* Floating point registers cannot be split. */
1504 if (FP_REG_P (src) || FP_REG_P (dst))
1505 return false;
1506
fae778eb 1507 /* We don't need to split if operands are directly accessible. */
dc65c307
UW		 1508 if (s_operand (src, mode) || s_operand (dst, mode))
1509 return false;
1510
1511 /* Non-offsettable memory references cannot be split. */
1512 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1513 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1514 return false;
1515
1516 /* Moving the first subword must not clobber a register
1517 needed to move the second subword. */
1518 if (register_operand (dst, mode))
1519 {
1520 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1521 if (reg_overlap_mentioned_p (subreg, src))
1522 return false;
1523 }
1524
1525 return true;
1526}
1527
bcf8c1cc
AK		 1528/* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1529 and [MEM2, MEM2 + SIZE] do overlap and false
1530 otherwise. */
1531
1532bool
1533s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1534{
1535 rtx addr1, addr2, addr_delta;
1536 HOST_WIDE_INT delta;
1537
1538 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1539 return true;
1540
1541 if (size == 0)
1542 return false;
1543
1544 addr1 = XEXP (mem1, 0);
1545 addr2 = XEXP (mem2, 0);
1546
1547 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1548
1549 /* This overlapping check is used by peepholes merging memory block operations.
1550 Overlapping operations would otherwise be recognized by the S/390 hardware
f4aa3848 1551 and would fall back to a slower implementation. Allowing overlapping
bcf8c1cc 1552 operations would lead to slow code but not to wrong code. Therefore we are
f4aa3848 1553 somewhat optimistic if we cannot prove that the memory blocks are
bcf8c1cc
AK		 1554 overlapping.
1555 That's why we return false here although this may accept operations on
1556 overlapping memory areas. */
1557 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1558 return false;
1559
1560 delta = INTVAL (addr_delta);
1561
1562 if (delta == 0
1563 || (delta > 0 && delta < size)
1564 || (delta < 0 && -delta < size))
1565 return true;
1566
1567 return false;
1568}
1569
19b63d8e
UW		 1570/* Check whether the address of memory reference MEM2 equals exactly
1571 the address of memory reference MEM1 plus DELTA. Return true if
1572 we can prove this to be the case, false otherwise. */
1573
1574bool
1575s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1576{
1577 rtx addr1, addr2, addr_delta;
1578
1579 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1580 return false;
1581
1582 addr1 = XEXP (mem1, 0);
1583 addr2 = XEXP (mem2, 0);
1584
1585 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1586 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1587 return false;
1588
1589 return true;
1590}
1591
8cb66696
UW		 1592/* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1593
1594void
ef4bddc2 1595s390_expand_logical_operator (enum rtx_code code, machine_mode mode,
8cb66696
UW		 1596 rtx *operands)
1597{
ef4bddc2 1598 machine_mode wmode = mode;
8cb66696
UW		 1599 rtx dst = operands[0];
1600 rtx src1 = operands[1];
1601 rtx src2 = operands[2];
1602 rtx op, clob, tem;
1603
1604 /* If we cannot handle the operation directly, use a temp register. */
1605 if (!s390_logical_operator_ok_p (operands))
1606 dst = gen_reg_rtx (mode);
1607
1608 /* QImode and HImode patterns make sense only if we have a destination
1609 in memory. Otherwise perform the operation in SImode. */
1610 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1611 wmode = SImode;
1612
1613 /* Widen operands if required. */
1614 if (mode != wmode)
1615 {
1616 if (GET_CODE (dst) == SUBREG
1617 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1618 dst = tem;
1619 else if (REG_P (dst))
1620 dst = gen_rtx_SUBREG (wmode, dst, 0);
1621 else
1622 dst = gen_reg_rtx (wmode);
1623
1624 if (GET_CODE (src1) == SUBREG
1625 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1626 src1 = tem;
1627 else if (GET_MODE (src1) != VOIDmode)
1628 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1629
1630 if (GET_CODE (src2) == SUBREG
1631 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1632 src2 = tem;
1633 else if (GET_MODE (src2) != VOIDmode)
1634 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1635 }
1636
1637 /* Emit the instruction. */
1638 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1639 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1640 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1641
1642 /* Fix up the destination if needed. */
1643 if (dst != operands[0])
1644 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1645}
1646
1647/* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1648
1649bool
1650s390_logical_operator_ok_p (rtx *operands)
1651{
1652 /* If the destination operand is in memory, it needs to coincide
1653 with one of the source operands. After reload, it has to be
1654 the first source operand. */
1655 if (GET_CODE (operands[0]) == MEM)
1656 return rtx_equal_p (operands[0], operands[1])
1657 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1658
1659 return true;
1660}
1661
0dfa6c5e
UW		 1662/* Narrow logical operation CODE of memory operand MEMOP with immediate
1663 operand IMMOP to switch from SS to SI type instructions. */
1664
1665void
1666s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1667{
1668 int def = code == AND ? -1 : 0;
1669 HOST_WIDE_INT mask;
1670 int part;
1671
1672 gcc_assert (GET_CODE (*memop) == MEM);
1673 gcc_assert (!MEM_VOLATILE_P (*memop));
1674
1675 mask = s390_extract_part (*immop, QImode, def);
1676 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1677 gcc_assert (part >= 0);
1678
1679 *memop = adjust_address (*memop, QImode, part);
1680 *immop = gen_int_mode (mask, QImode);
1681}
1682
ba956982 1683
ab96de7e
AS		 1684/* How to allocate a 'struct machine_function'. */
1685
1686static struct machine_function *
1687s390_init_machine_status (void)
1688{
766090c2 1689 return ggc_cleared_alloc<machine_function> ();
ab96de7e
AS		 1690}
1691
9db1d521
HP		 1692/* Map for smallest class containing reg regno. */
1693
0139adca 1694const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
9db1d521
HP		 1695{ GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1696 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1697 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1698 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1699 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1700 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1701 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1702 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
c5aa1d12
UW		 1703 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1704 ACCESS_REGS, ACCESS_REGS
9db1d521
HP		 1705};
1706
077dab3b
HP		 1707/* Return attribute type of insn. */
1708
1709static enum attr_type
647d790d 1710s390_safe_attr_type (rtx_insn *insn)
077dab3b
HP		 1711{
1712 if (recog_memoized (insn) >= 0)
1713 return get_attr_type (insn);
1714 else
1715 return TYPE_NONE;
1716}
9db1d521 1717
d3632d41
UW		 1718/* Return true if DISP is a valid short displacement. */
1719
3ed99cc9 1720static bool
9c808aad 1721s390_short_displacement (rtx disp)
d3632d41
UW		 1722{
1723 /* No displacement is OK. */
1724 if (!disp)
3ed99cc9 1725 return true;
d3632d41 1726
4fe6dea8
AK		 1727 /* Without the long displacement facility we don't need to
1728 distingiush between long and short displacement. */
1729 if (!TARGET_LONG_DISPLACEMENT)
1730 return true;
1731
d3632d41
UW		 1732 /* Integer displacement in range. */
1733 if (GET_CODE (disp) == CONST_INT)
1734 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1735
1736 /* GOT offset is not OK, the GOT can be large. */
1737 if (GET_CODE (disp) == CONST
1738 && GET_CODE (XEXP (disp, 0)) == UNSPEC
227a39fa
UW		 1739 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1740 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
3ed99cc9 1741 return false;
d3632d41
UW		 1742
1743 /* All other symbolic constants are literal pool references,
1744 which are OK as the literal pool must be small. */
1745 if (GET_CODE (disp) == CONST)
3ed99cc9 1746 return true;
d3632d41 1747
3ed99cc9 1748 return false;
d3632d41
UW		 1749}
1750
ab96de7e
AS		 1751/* Decompose a RTL expression ADDR for a memory address into
1752 its components, returned in OUT.
ccfc6cc8 1753
3ed99cc9 1754 Returns false if ADDR is not a valid memory address, true
ab96de7e
AS		 1755 otherwise. If OUT is NULL, don't return the components,
1756 but check for validity only.
ccfc6cc8 1757
ab96de7e
AS		 1758 Note: Only addresses in canonical form are recognized.
1759 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1760 canonical form so that they will be recognized. */
f19a9af7 1761
ab96de7e 1762static int
5d81b82b 1763s390_decompose_address (rtx addr, struct s390_address *out)
ab96de7e
AS		 1764{
1765 HOST_WIDE_INT offset = 0;
1766 rtx base = NULL_RTX;
1767 rtx indx = NULL_RTX;
1768 rtx disp = NULL_RTX;
1769 rtx orig_disp;
3ed99cc9
AS		 1770 bool pointer = false;
1771 bool base_ptr = false;
1772 bool indx_ptr = false;
f01cf809
UW		 1773 bool literal_pool = false;
1774
1775 /* We may need to substitute the literal pool base register into the address
1776 below. However, at this point we do not know which register is going to
1777 be used as base, so we substitute the arg pointer register. This is going
1778 to be treated as holding a pointer below -- it shouldn't be used for any
1779 other purpose. */
1780 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
0dfa6c5e 1781
ab96de7e 1782 /* Decompose address into base + index + displacement. */
0dfa6c5e 1783
ab96de7e
AS		 1784 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1785 base = addr;
0dfa6c5e 1786
ab96de7e 1787 else if (GET_CODE (addr) == PLUS)
e221ef54 1788 {
ab96de7e
AS		 1789 rtx op0 = XEXP (addr, 0);
1790 rtx op1 = XEXP (addr, 1);
1791 enum rtx_code code0 = GET_CODE (op0);
1792 enum rtx_code code1 = GET_CODE (op1);
e221ef54 1793
ab96de7e
AS		 1794 if (code0 == REG || code0 == UNSPEC)
1795 {
1796 if (code1 == REG || code1 == UNSPEC)
1797 {
1798 indx = op0; /* index + base */
1799 base = op1;
1800 }
e221ef54 1801
ab96de7e
AS		 1802 else
1803 {
1804 base = op0; /* base + displacement */
1805 disp = op1;
1806 }
1807 }
ccfc6cc8 1808
ab96de7e 1809 else if (code0 == PLUS)
d3632d41 1810 {
ab96de7e
AS		 1811 indx = XEXP (op0, 0); /* index + base + disp */
1812 base = XEXP (op0, 1);
1813 disp = op1;
d3632d41 1814 }
d3632d41 1815
ab96de7e 1816 else
d3632d41 1817 {
3ed99cc9 1818 return false;
d3632d41 1819 }
ab96de7e 1820 }
d3632d41 1821
ab96de7e
AS		 1822 else
1823 disp = addr; /* displacement */
d3632d41 1824
ab96de7e
AS		 1825 /* Extract integer part of displacement. */
1826 orig_disp = disp;
1827 if (disp)
1828 {
1829 if (GET_CODE (disp) == CONST_INT)
d3632d41 1830 {
ab96de7e
AS		 1831 offset = INTVAL (disp);
1832 disp = NULL_RTX;
d3632d41 1833 }
ab96de7e
AS		 1834 else if (GET_CODE (disp) == CONST
1835 && GET_CODE (XEXP (disp, 0)) == PLUS
1836 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1837 {
1838 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1839 disp = XEXP (XEXP (disp, 0), 0);
1840 }
1841 }
d3632d41 1842
ab96de7e
AS		 1843 /* Strip off CONST here to avoid special case tests later. */
1844 if (disp && GET_CODE (disp) == CONST)
1845 disp = XEXP (disp, 0);
ac32b25e 1846
ab96de7e
AS		 1847 /* We can convert literal pool addresses to
1848 displacements by basing them off the base register. */
1849 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1850 {
1851 /* Either base or index must be free to hold the base register. */
1852 if (!base)
f01cf809 1853 base = fake_pool_base, literal_pool = true;
ab96de7e 1854 else if (!indx)
f01cf809 1855 indx = fake_pool_base, literal_pool = true;
ab96de7e 1856 else
3ed99cc9 1857 return false;
ab96de7e
AS		 1858
1859 /* Mark up the displacement. */
1860 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1861 UNSPEC_LTREL_OFFSET);
d3632d41 1862 }
ccfc6cc8 1863
ab96de7e
AS		 1864 /* Validate base register. */
1865 if (base)
1866 {
1867 if (GET_CODE (base) == UNSPEC)
1868 switch (XINT (base, 1))
1869 {
1870 case UNSPEC_LTREF:
1871 if (!disp)
f4aa3848 1872 disp = gen_rtx_UNSPEC (Pmode,
ab96de7e
AS		 1873 gen_rtvec (1, XVECEXP (base, 0, 0)),
1874 UNSPEC_LTREL_OFFSET);
1875 else
3ed99cc9 1876 return false;
ccfc6cc8 1877
f01cf809 1878 base = XVECEXP (base, 0, 1);
ab96de7e 1879 break;
f19a9af7 1880
ab96de7e 1881 case UNSPEC_LTREL_BASE:
f01cf809
UW		 1882 if (XVECLEN (base, 0) == 1)
1883 base = fake_pool_base, literal_pool = true;
1884 else
1885 base = XVECEXP (base, 0, 1);
ab96de7e 1886 break;
f19a9af7 1887
ab96de7e 1888 default:
3ed99cc9 1889 return false;
ab96de7e 1890 }
f19a9af7 1891
f4aa3848
AK		 1892 if (!REG_P (base)
1893 || (GET_MODE (base) != SImode
93fa8428 1894 && GET_MODE (base) != Pmode))
3ed99cc9 1895 return false;
ab96de7e 1896
f01cf809 1897 if (REGNO (base) == STACK_POINTER_REGNUM
ab96de7e
AS		 1898 || REGNO (base) == FRAME_POINTER_REGNUM
1899 || ((reload_completed || reload_in_progress)
1900 && frame_pointer_needed
1901 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1902 || REGNO (base) == ARG_POINTER_REGNUM
1903 || (flag_pic
1904 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
3ed99cc9 1905 pointer = base_ptr = true;
f01cf809
UW		 1906
1907 if ((reload_completed || reload_in_progress)
1908 && base == cfun->machine->base_reg)
1909 pointer = base_ptr = literal_pool = true;
ab96de7e
AS		 1910 }
1911
1912 /* Validate index register. */
1913 if (indx)
f19a9af7 1914 {
ab96de7e
AS		 1915 if (GET_CODE (indx) == UNSPEC)
1916 switch (XINT (indx, 1))
1917 {
1918 case UNSPEC_LTREF:
1919 if (!disp)
f4aa3848 1920 disp = gen_rtx_UNSPEC (Pmode,
ab96de7e
AS		 1921 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1922 UNSPEC_LTREL_OFFSET);
1923 else
3ed99cc9 1924 return false;
f19a9af7 1925
f01cf809 1926 indx = XVECEXP (indx, 0, 1);
ab96de7e 1927 break;
f19a9af7 1928
ab96de7e 1929 case UNSPEC_LTREL_BASE:
f01cf809
UW		 1930 if (XVECLEN (indx, 0) == 1)
1931 indx = fake_pool_base, literal_pool = true;
1932 else
1933 indx = XVECEXP (indx, 0, 1);
ab96de7e 1934 break;
f19a9af7 1935
ab96de7e 1936 default:
3ed99cc9 1937 return false;
ab96de7e 1938 }
f19a9af7 1939
f4aa3848 1940 if (!REG_P (indx)
93fa8428
AK		 1941 || (GET_MODE (indx) != SImode
1942 && GET_MODE (indx) != Pmode))
3ed99cc9 1943 return false;
f19a9af7 1944
f01cf809 1945 if (REGNO (indx) == STACK_POINTER_REGNUM
ab96de7e
AS		 1946 || REGNO (indx) == FRAME_POINTER_REGNUM
1947 || ((reload_completed || reload_in_progress)
1948 && frame_pointer_needed
1949 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1950 || REGNO (indx) == ARG_POINTER_REGNUM
1951 || (flag_pic
1952 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
3ed99cc9 1953 pointer = indx_ptr = true;
f01cf809
UW		 1954
1955 if ((reload_completed || reload_in_progress)
1956 && indx == cfun->machine->base_reg)
1957 pointer = indx_ptr = literal_pool = true;
ab96de7e 1958 }
38899e29 1959
ab96de7e
AS		 1960 /* Prefer to use pointer as base, not index. */
1961 if (base && indx && !base_ptr
1962 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1963 {
1964 rtx tmp = base;
1965 base = indx;
1966 indx = tmp;
1967 }
f19a9af7 1968
ab96de7e
AS		 1969 /* Validate displacement. */
1970 if (!disp)
1971 {
f4aa3848
AK		 1972 /* If virtual registers are involved, the displacement will change later
1973 anyway as the virtual registers get eliminated. This could make a
1974 valid displacement invalid, but it is more likely to make an invalid
1975 displacement valid, because we sometimes access the register save area
63296cb1 1976 via negative offsets to one of those registers.
ab96de7e
AS		 1977 Thus we don't check the displacement for validity here. If after
1978 elimination the displacement turns out to be invalid after all,
1979 this is fixed up by reload in any case. */
3597e113
VM		 1980 /* LRA maintains always displacements up to date and we need to
1981 know the displacement is right during all LRA not only at the
1982 final elimination. */
1983 if (lra_in_progress
1984 || (base != arg_pointer_rtx
1985 && indx != arg_pointer_rtx
1986 && base != return_address_pointer_rtx
1987 && indx != return_address_pointer_rtx
1988 && base != frame_pointer_rtx
1989 && indx != frame_pointer_rtx
1990 && base != virtual_stack_vars_rtx
1991 && indx != virtual_stack_vars_rtx))
ab96de7e 1992 if (!DISP_IN_RANGE (offset))
3ed99cc9 1993 return false;
ab96de7e
AS		 1994 }
1995 else
1996 {
1997 /* All the special cases are pointers. */
3ed99cc9 1998 pointer = true;
f19a9af7 1999
ab96de7e
AS		 2000 /* In the small-PIC case, the linker converts @GOT
2001 and @GOTNTPOFF offsets to possible displacements. */
2002 if (GET_CODE (disp) == UNSPEC
2003 && (XINT (disp, 1) == UNSPEC_GOT
2004 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
ab96de7e
AS		 2005 && flag_pic == 1)
2006 {
2007 ;
2008 }
f19a9af7 2009
dc66391d
RS		 2010 /* Accept pool label offsets. */
2011 else if (GET_CODE (disp) == UNSPEC
2012 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
2013 ;
f19a9af7 2014
ab96de7e
AS		 2015 /* Accept literal pool references. */
2016 else if (GET_CODE (disp) == UNSPEC
2017 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
2018 {
bc6ce334
AK		 2019 /* In case CSE pulled a non literal pool reference out of
2020 the pool we have to reject the address. This is
2021 especially important when loading the GOT pointer on non
2022 zarch CPUs. In this case the literal pool contains an lt
2023 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
2024 will most likely exceed the displacement. */
2025 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
2026 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp, 0, 0)))
2027 return false;
2028
ab96de7e
AS		 2029 orig_disp = gen_rtx_CONST (Pmode, disp);
2030 if (offset)
2031 {
2032 /* If we have an offset, make sure it does not
2033 exceed the size of the constant pool entry. */
2034 rtx sym = XVECEXP (disp, 0, 0);
2035 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
3ed99cc9 2036 return false;
f19a9af7 2037
0a81f074 2038 orig_disp = plus_constant (Pmode, orig_disp, offset);
ab96de7e
AS		 2039 }
2040 }
2041
2042 else
3ed99cc9 2043 return false;
f19a9af7
AK		 2044 }
2045
ab96de7e 2046 if (!base && !indx)
3ed99cc9 2047 pointer = true;
ab96de7e
AS		 2048
2049 if (out)
2050 {
2051 out->base = base;
2052 out->indx = indx;
2053 out->disp = orig_disp;
2054 out->pointer = pointer;
f01cf809 2055 out->literal_pool = literal_pool;
ab96de7e
AS		 2056 }
2057
3ed99cc9 2058 return true;
f19a9af7
AK		 2059}
2060
d98ad410
UW		 2061/* Decompose a RTL expression OP for a shift count into its components,
2062 and return the base register in BASE and the offset in OFFSET.
2063
d98ad410
UW		 2064 Return true if OP is a valid shift count, false if not. */
2065
2066bool
4989e88a 2067s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
d98ad410
UW		 2068{
2069 HOST_WIDE_INT off = 0;
2070
d98ad410
UW		 2071 /* We can have an integer constant, an address register,
2072 or a sum of the two. */
2073 if (GET_CODE (op) == CONST_INT)
2074 {
2075 off = INTVAL (op);
2076 op = NULL_RTX;
2077 }
2078 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2079 {
2080 off = INTVAL (XEXP (op, 1));
2081 op = XEXP (op, 0);
2082 }
2083 while (op && GET_CODE (op) == SUBREG)
2084 op = SUBREG_REG (op);
2085
2086 if (op && GET_CODE (op) != REG)
2087 return false;
2088
2089 if (offset)
2090 *offset = off;
2091 if (base)
2092 *base = op;
2093
2094 return true;
2095}
2096
2097
ab96de7e 2098/* Return true if CODE is a valid address without index. */
3c50106f 2099
ab96de7e
AS		 2100bool
2101s390_legitimate_address_without_index_p (rtx op)
2102{
2103 struct s390_address addr;
2104
2105 if (!s390_decompose_address (XEXP (op, 0), &addr))
2106 return false;
2107 if (addr.indx)
2108 return false;
2109
2110 return true;
2111}
2112
cd8dc1f9 2113
0ff4390d
AK		 2114/* Return TRUE if ADDR is an operand valid for a load/store relative
2115 instruction. Be aware that the alignment of the operand needs to
2116 be checked separately.
2117 Valid addresses are single references or a sum of a reference and a
2118 constant integer. Return these parts in SYMREF and ADDEND. You can
2119 pass NULL in REF and/or ADDEND if you are not interested in these
2120 values. Literal pool references are *not* considered symbol
2121 references. */
ab96de7e 2122
4fe6dea8 2123static bool
0ff4390d 2124s390_loadrelative_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
ab96de7e 2125{
4fe6dea8 2126 HOST_WIDE_INT tmpaddend = 0;
ab96de7e 2127
4fe6dea8
AK		 2128 if (GET_CODE (addr) == CONST)
2129 addr = XEXP (addr, 0);
2130
2131 if (GET_CODE (addr) == PLUS)
ab96de7e 2132 {
0ff4390d 2133 if (!CONST_INT_P (XEXP (addr, 1)))
4fe6dea8 2134 return false;
ab96de7e 2135
0ff4390d
AK		 2136 tmpaddend = INTVAL (XEXP (addr, 1));
2137 addr = XEXP (addr, 0);
2138 }
98412b77 2139
0ff4390d
AK		 2140 if ((GET_CODE (addr) == SYMBOL_REF && !CONSTANT_POOL_ADDRESS_P (addr))
2141 || (GET_CODE (addr) == UNSPEC
2142 && (XINT (addr, 1) == UNSPEC_GOTENT
2143 || (TARGET_CPU_ZARCH && XINT (addr, 1) == UNSPEC_PLT))))
2144 {
2145 if (symref)
2146 *symref = addr;
2147 if (addend)
2148 *addend = tmpaddend;
98412b77 2149
0ff4390d
AK		 2150 return true;
2151 }
2152 return false;
98412b77 2153}
4fe6dea8
AK		 2154
2155/* Return true if the address in OP is valid for constraint letter C
2156 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2157 pool MEMs should be accepted. Only the Q, R, S, T constraint
2158 letters are allowed for C. */
ab96de7e 2159
4fe6dea8
AK		 2160static int
2161s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2162{
2163 struct s390_address addr;
2164 bool decomposed = false;
2165
2166 /* This check makes sure that no symbolic address (except literal
2167 pool references) are accepted by the R or T constraints. */
0ff4390d 2168 if (s390_loadrelative_operand_p (op, NULL, NULL))
98635b04
UW		 2169 return 0;
2170
2171 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2172 if (!lit_pool_ok)
ab96de7e 2173 {
4fe6dea8 2174 if (!s390_decompose_address (op, &addr))
ab96de7e 2175 return 0;
98635b04 2176 if (addr.literal_pool)
ab96de7e 2177 return 0;
4fe6dea8 2178 decomposed = true;
ab96de7e
AS		 2179 }
2180
2181 switch (c)
2182 {
4fe6dea8
AK		 2183 case 'Q': /* no index short displacement */
2184 if (!decomposed && !s390_decompose_address (op, &addr))
ab96de7e
AS		 2185 return 0;
2186 if (addr.indx)
2187 return 0;
4fe6dea8 2188 if (!s390_short_displacement (addr.disp))
ab96de7e 2189 return 0;
4fe6dea8 2190 break;
ab96de7e 2191
4fe6dea8 2192 case 'R': /* with index short displacement */
ab96de7e
AS		 2193 if (TARGET_LONG_DISPLACEMENT)
2194 {
4fe6dea8 2195 if (!decomposed && !s390_decompose_address (op, &addr))
ab96de7e
AS		 2196 return 0;
2197 if (!s390_short_displacement (addr.disp))
2198 return 0;
2199 }
4fe6dea8
AK		 2200 /* Any invalid address here will be fixed up by reload,
2201 so accept it for the most generic constraint. */
ab96de7e
AS		 2202 break;
2203
4fe6dea8 2204 case 'S': /* no index long displacement */
ab96de7e
AS		 2205 if (!TARGET_LONG_DISPLACEMENT)
2206 return 0;
4fe6dea8 2207 if (!decomposed && !s390_decompose_address (op, &addr))
ab96de7e
AS		 2208 return 0;
2209 if (addr.indx)
2210 return 0;
2211 if (s390_short_displacement (addr.disp))
2212 return 0;
2213 break;
2214
4fe6dea8 2215 case 'T': /* with index long displacement */
ab96de7e
AS		 2216 if (!TARGET_LONG_DISPLACEMENT)
2217 return 0;
4fe6dea8
AK		 2218 /* Any invalid address here will be fixed up by reload,
2219 so accept it for the most generic constraint. */
2220 if ((decomposed || s390_decompose_address (op, &addr))
2221 && s390_short_displacement (addr.disp))
ab96de7e
AS		 2222 return 0;
2223 break;
4fe6dea8
AK		 2224 default:
2225 return 0;
2226 }
2227 return 1;
2228}
ab96de7e 2229
ab96de7e 2230
4fe6dea8
AK		 2231/* Evaluates constraint strings described by the regular expression
2232 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2233 the constraint given in STR, or 0 else. */
2234
2235int
2236s390_mem_constraint (const char *str, rtx op)
2237{
2238 char c = str[0];
2239
2240 switch (c)
2241 {
2242 case 'A':
2243 /* Check for offsettable variants of memory constraints. */
2244 if (!MEM_P (op) || MEM_VOLATILE_P (op))
ab96de7e 2245 return 0;
4fe6dea8
AK		 2246 if ((reload_completed || reload_in_progress)
2247 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
963fc8d0 2248 return 0;
4fe6dea8
AK		 2249 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2250 case 'B':
2251 /* Check for non-literal-pool variants of memory constraints. */
2252 if (!MEM_P (op))
ab96de7e 2253 return 0;
4fe6dea8
AK		 2254 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2255 case 'Q':
2256 case 'R':
2257 case 'S':
2258 case 'T':
2259 if (GET_CODE (op) != MEM)
2260 return 0;
2261 return s390_check_qrst_address (c, XEXP (op, 0), true);
2262 case 'U':
2263 return (s390_check_qrst_address ('Q', op, true)
2264 || s390_check_qrst_address ('R', op, true));
2265 case 'W':
2266 return (s390_check_qrst_address ('S', op, true)
2267 || s390_check_qrst_address ('T', op, true));
ab96de7e 2268 case 'Y':
d98ad410
UW		 2269 /* Simply check for the basic form of a shift count. Reload will
2270 take care of making sure we have a proper base register. */
4989e88a 2271 if (!s390_decompose_shift_count (op, NULL, NULL))
d98ad410
UW		 2272 return 0;
2273 break;
4fe6dea8
AK		 2274 case 'Z':
2275 return s390_check_qrst_address (str[1], op, true);
ab96de7e
AS		 2276 default:
2277 return 0;
2278 }
ab96de7e
AS		 2279 return 1;
2280}
2281
cd8dc1f9 2282
cd8dc1f9
WG		 2283/* Evaluates constraint strings starting with letter O. Input
2284 parameter C is the second letter following the "O" in the constraint
2285 string. Returns 1 if VALUE meets the respective constraint and 0
2286 otherwise. */
ab96de7e 2287
d096725d 2288int
cd8dc1f9 2289s390_O_constraint_str (const char c, HOST_WIDE_INT value)
d096725d 2290{
cd8dc1f9
WG		 2291 if (!TARGET_EXTIMM)
2292 return 0;
d096725d 2293
cd8dc1f9 2294 switch (c)
d096725d 2295 {
cd8dc1f9
WG		 2296 case 's':
2297 return trunc_int_for_mode (value, SImode) == value;
2298
2299 case 'p':
2300 return value == 0
2301 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2302
2303 case 'n':
ee3f3449 2304 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
cd8dc1f9 2305
d096725d 2306 default:
cd8dc1f9 2307 gcc_unreachable ();
d096725d
AS		 2308 }
2309}
2310
cd8dc1f9
WG		 2311
2312/* Evaluates constraint strings starting with letter N. Parameter STR
2313 contains the letters following letter "N" in the constraint string.
2314 Returns true if VALUE matches the constraint. */
d096725d 2315
ab96de7e 2316int
cd8dc1f9 2317s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
ab96de7e 2318{
ef4bddc2 2319 machine_mode mode, part_mode;
ab96de7e
AS		 2320 int def;
2321 int part, part_goal;
2322
ab96de7e 2323
cd8dc1f9
WG		 2324 if (str[0] == 'x')
2325 part_goal = -1;
2326 else
2327 part_goal = str[0] - '0';
ab96de7e 2328
cd8dc1f9
WG		 2329 switch (str[1])
2330 {
2331 case 'Q':
2332 part_mode = QImode;
ab96de7e 2333 break;
cd8dc1f9
WG		 2334 case 'H':
2335 part_mode = HImode;
ec24698e 2336 break;
cd8dc1f9
WG		 2337 case 'S':
2338 part_mode = SImode;
2339 break;
2340 default:
2341 return 0;
2342 }
ec24698e 2343
cd8dc1f9
WG		 2344 switch (str[2])
2345 {
2346 case 'H':
2347 mode = HImode;
2348 break;
2349 case 'S':
2350 mode = SImode;
2351 break;
2352 case 'D':
2353 mode = DImode;
2354 break;
2355 default:
2356 return 0;
2357 }
11598938 2358
cd8dc1f9
WG		 2359 switch (str[3])
2360 {
2361 case '0':
2362 def = 0;
2363 break;
2364 case 'F':
2365 def = -1;
2366 break;
ab96de7e
AS		 2367 default:
2368 return 0;
2369 }
2370
cd8dc1f9
WG		 2371 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2372 return 0;
2373
2374 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2375 if (part < 0)
2376 return 0;
2377 if (part_goal != -1 && part_goal != part)
2378 return 0;
2379
ab96de7e
AS		 2380 return 1;
2381}
2382
cd8dc1f9
WG		 2383
2384/* Returns true if the input parameter VALUE is a float zero. */
2385
2386int
2387s390_float_const_zero_p (rtx value)
2388{
2389 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2390 && value == CONST0_RTX (GET_MODE (value)));
2391}
2392
ccaed3ba
AS		 2393/* Implement TARGET_REGISTER_MOVE_COST. */
2394
2395static int
ef4bddc2 2396s390_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
ccaed3ba
AS		 2397 reg_class_t from, reg_class_t to)
2398{
1dd03b91
AK		 2399 /* On s390, copy between fprs and gprs is expensive as long as no
2400 ldgr/lgdr can be used. */
2401 if ((!TARGET_Z10 || GET_MODE_SIZE (mode) != 8)
2402 && ((reg_classes_intersect_p (from, GENERAL_REGS)
2403 && reg_classes_intersect_p (to, FP_REGS))
2404 || (reg_classes_intersect_p (from, FP_REGS)
2405 && reg_classes_intersect_p (to, GENERAL_REGS))))
ccaed3ba
AS		 2406 return 10;
2407
2408 return 1;
2409}
2410
2411/* Implement TARGET_MEMORY_MOVE_COST. */
2412
2413static int
ef4bddc2 2414s390_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
ccaed3ba
AS		 2415 reg_class_t rclass ATTRIBUTE_UNUSED,
2416 bool in ATTRIBUTE_UNUSED)
2417{
2418 return 1;
2419}
cd8dc1f9 2420
ab96de7e
AS		 2421/* Compute a (partial) cost for rtx X. Return true if the complete
2422 cost has been computed, and false if subexpressions should be
f4aa3848
AK		 2423 scanned. In either case, *TOTAL contains the cost result.
2424 CODE contains GET_CODE (x), OUTER_CODE contains the code
ab96de7e
AS		 2425 of the superexpression of x. */
2426
2427static bool
68f932c4
RS		 2428s390_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
2429 int *total, bool speed ATTRIBUTE_UNUSED)
3c50106f
RH		 2430{
2431 switch (code)
2432 {
2433 case CONST:
3c50106f 2434 case CONST_INT:
3c50106f
RH		 2435 case LABEL_REF:
2436 case SYMBOL_REF:
2437 case CONST_DOUBLE:
6fa5b390 2438 case MEM:
3c50106f
RH		 2439 *total = 0;
2440 return true;
2441
2442 case ASHIFT:
2443 case ASHIFTRT:
2444 case LSHIFTRT:
017e0eb9
MD		 2445 case ROTATE:
2446 case ROTATERT:
3c50106f
RH		 2447 case AND:
2448 case IOR:
2449 case XOR:
3c50106f
RH		 2450 case NEG:
2451 case NOT:
2452 *total = COSTS_N_INSNS (1);
017e0eb9 2453 return false;
3c50106f 2454
2742a1ed
MD		 2455 case PLUS:
2456 case MINUS:
2742a1ed
MD		 2457 *total = COSTS_N_INSNS (1);
2458 return false;
2459
f4aa3848 2460 case MULT:
017e0eb9
MD		 2461 switch (GET_MODE (x))
2462 {
2463 case SImode:
2742a1ed 2464 {
017e0eb9
MD		 2465 rtx left = XEXP (x, 0);
2466 rtx right = XEXP (x, 1);
2467 if (GET_CODE (right) == CONST_INT
b5c67a49 2468 && CONST_OK_FOR_K (INTVAL (right)))
017e0eb9
MD		 2469 *total = s390_cost->mhi;
2470 else if (GET_CODE (left) == SIGN_EXTEND)
2471 *total = s390_cost->mh;
2472 else
2473 *total = s390_cost->ms; /* msr, ms, msy */
2474 break;
2475 }
2476 case DImode:
2477 {
2478 rtx left = XEXP (x, 0);
2479 rtx right = XEXP (x, 1);
9602b6a1 2480 if (TARGET_ZARCH)
017e0eb9
MD		 2481 {
2482 if (GET_CODE (right) == CONST_INT
b5c67a49 2483 && CONST_OK_FOR_K (INTVAL (right)))
017e0eb9
MD		 2484 *total = s390_cost->mghi;
2485 else if (GET_CODE (left) == SIGN_EXTEND)
2486 *total = s390_cost->msgf;
2487 else
2488 *total = s390_cost->msg; /* msgr, msg */
2489 }
2490 else /* TARGET_31BIT */
2491 {
2492 if (GET_CODE (left) == SIGN_EXTEND
2493 && GET_CODE (right) == SIGN_EXTEND)
2494 /* mulsidi case: mr, m */
2495 *total = s390_cost->m;
2742a1ed
MD		 2496 else if (GET_CODE (left) == ZERO_EXTEND
2497 && GET_CODE (right) == ZERO_EXTEND
2498 && TARGET_CPU_ZARCH)
2499 /* umulsidi case: ml, mlr */
2500 *total = s390_cost->ml;
017e0eb9
MD		 2501 else
2502 /* Complex calculation is required. */
2503 *total = COSTS_N_INSNS (40);
2504 }
2505 break;
2506 }
2507 case SFmode:
2508 case DFmode:
2509 *total = s390_cost->mult_df;
2510 break;
f61a2c7d
AK		 2511 case TFmode:
2512 *total = s390_cost->mxbr;
2513 break;
017e0eb9
MD		 2514 default:
2515 return false;
2516 }
2517 return false;
3c50106f 2518
d7ecb504
RH		 2519 case FMA:
2520 switch (GET_MODE (x))
2521 {
2522 case DFmode:
2523 *total = s390_cost->madbr;
2524 break;
2525 case SFmode:
2526 *total = s390_cost->maebr;
2527 break;
2528 default:
2529 return false;
2530 }
2531 /* Negate in the third argument is free: FMSUB. */
2532 if (GET_CODE (XEXP (x, 2)) == NEG)
2533 {
68f932c4
RS		 2534 *total += (rtx_cost (XEXP (x, 0), FMA, 0, speed)
2535 + rtx_cost (XEXP (x, 1), FMA, 1, speed)
2536 + rtx_cost (XEXP (XEXP (x, 2), 0), FMA, 2, speed));
d7ecb504
RH		 2537 return true;
2538 }
2539 return false;
2540
6fa5b390
MD		 2541 case UDIV:
2542 case UMOD:
2543 if (GET_MODE (x) == TImode) /* 128 bit division */
2544 *total = s390_cost->dlgr;
2545 else if (GET_MODE (x) == DImode)
2546 {
2547 rtx right = XEXP (x, 1);
2548 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2549 *total = s390_cost->dlr;
2550 else /* 64 by 64 bit division */
2551 *total = s390_cost->dlgr;
2552 }
2553 else if (GET_MODE (x) == SImode) /* 32 bit division */
2554 *total = s390_cost->dlr;
2555 return false;
2556
3c50106f 2557 case DIV:
6fa5b390
MD		 2558 case MOD:
2559 if (GET_MODE (x) == DImode)
2560 {
2561 rtx right = XEXP (x, 1);
2562 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
9602b6a1 2563 if (TARGET_ZARCH)
6fa5b390
MD		 2564 *total = s390_cost->dsgfr;
2565 else
2566 *total = s390_cost->dr;
2567 else /* 64 by 64 bit division */
2568 *total = s390_cost->dsgr;
2569 }
2570 else if (GET_MODE (x) == SImode) /* 32 bit division */
2571 *total = s390_cost->dlr;
2572 else if (GET_MODE (x) == SFmode)
98fd0d70 2573 {
142cd70f 2574 *total = s390_cost->debr;
98fd0d70
MD		 2575 }
2576 else if (GET_MODE (x) == DFmode)
2577 {
142cd70f 2578 *total = s390_cost->ddbr;
98fd0d70 2579 }
f61a2c7d
AK		 2580 else if (GET_MODE (x) == TFmode)
2581 {
142cd70f 2582 *total = s390_cost->dxbr;
f61a2c7d 2583 }
017e0eb9
MD		 2584 return false;
2585
2742a1ed
MD		 2586 case SQRT:
2587 if (GET_MODE (x) == SFmode)
2588 *total = s390_cost->sqebr;
f61a2c7d 2589 else if (GET_MODE (x) == DFmode)
2742a1ed 2590 *total = s390_cost->sqdbr;
f61a2c7d
AK		 2591 else /* TFmode */
2592 *total = s390_cost->sqxbr;
2742a1ed
MD		 2593 return false;
2594
017e0eb9 2595 case SIGN_EXTEND:
2742a1ed 2596 case ZERO_EXTEND:
6fa5b390
MD		 2597 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2598 || outer_code == PLUS || outer_code == MINUS
2599 || outer_code == COMPARE)
017e0eb9
MD		 2600 *total = 0;
2601 return false;
3c50106f 2602
6fa5b390
MD		 2603 case COMPARE:
2604 *total = COSTS_N_INSNS (1);
2605 if (GET_CODE (XEXP (x, 0)) == AND
2606 && GET_CODE (XEXP (x, 1)) == CONST_INT
2607 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2608 {
2609 rtx op0 = XEXP (XEXP (x, 0), 0);
2610 rtx op1 = XEXP (XEXP (x, 0), 1);
2611 rtx op2 = XEXP (x, 1);
2612
2613 if (memory_operand (op0, GET_MODE (op0))
2614 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2615 return true;
2616 if (register_operand (op0, GET_MODE (op0))
2617 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2618 return true;
2619 }
2620 return false;
2621
3c50106f
RH		 2622 default:
2623 return false;
2624 }
2625}
2626
dea09b1b
UW		 2627/* Return the cost of an address rtx ADDR. */
2628
dcefdf67 2629static int
ef4bddc2 2630s390_address_cost (rtx addr, machine_mode mode ATTRIBUTE_UNUSED,
b413068c
OE		 2631 addr_space_t as ATTRIBUTE_UNUSED,
2632 bool speed ATTRIBUTE_UNUSED)
dea09b1b
UW		 2633{
2634 struct s390_address ad;
2635 if (!s390_decompose_address (addr, &ad))
2636 return 1000;
2637
2638 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2639}
2640
fd3cd001
UW		 2641/* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2642 otherwise return 0. */
2643
2644int
5d81b82b 2645tls_symbolic_operand (rtx op)
fd3cd001 2646{
fd3cd001
UW		 2647 if (GET_CODE (op) != SYMBOL_REF)
2648 return 0;
114278e7 2649 return SYMBOL_REF_TLS_MODEL (op);
fd3cd001 2650}
9db1d521 2651\f
c5aa1d12
UW		 2652/* Split DImode access register reference REG (on 64-bit) into its constituent
2653 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2654 gen_highpart cannot be used as they assume all registers are word-sized,
2655 while our access registers have only half that size. */
2656
2657void
2658s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2659{
2660 gcc_assert (TARGET_64BIT);
2661 gcc_assert (ACCESS_REG_P (reg));
2662 gcc_assert (GET_MODE (reg) == DImode);
2663 gcc_assert (!(REGNO (reg) & 1));
2664
2665 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2666 *hi = gen_rtx_REG (SImode, REGNO (reg));
2667}
9db1d521 2668
994fe660 2669/* Return true if OP contains a symbol reference */
9db1d521 2670
3ed99cc9 2671bool
9c808aad 2672symbolic_reference_mentioned_p (rtx op)
9db1d521 2673{
5d81b82b
AS		 2674 const char *fmt;
2675 int i;
9db1d521
HP		 2676
2677 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2678 return 1;
2679
2680 fmt = GET_RTX_FORMAT (GET_CODE (op));
2681 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2682 {
2683 if (fmt[i] == 'E')
2684 {
5d81b82b 2685 int j;
9db1d521
HP		 2686
2687 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2688 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2689 return 1;
2690 }
2691
2692 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2693 return 1;
2694 }
2695
2696 return 0;
2697}
2698
fd3cd001
UW		 2699/* Return true if OP contains a reference to a thread-local symbol. */
2700
3ed99cc9 2701bool
9c808aad 2702tls_symbolic_reference_mentioned_p (rtx op)
fd3cd001 2703{
5d81b82b
AS		 2704 const char *fmt;
2705 int i;
fd3cd001
UW		 2706
2707 if (GET_CODE (op) == SYMBOL_REF)
2708 return tls_symbolic_operand (op);
2709
2710 fmt = GET_RTX_FORMAT (GET_CODE (op));
2711 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2712 {
2713 if (fmt[i] == 'E')
2714 {
5d81b82b 2715 int j;
fd3cd001
UW		 2716
2717 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2718 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
3ed99cc9 2719 return true;
fd3cd001
UW		 2720 }
2721
2722 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
3ed99cc9 2723 return true;
fd3cd001
UW		 2724 }
2725
3ed99cc9 2726 return false;
fd3cd001
UW		 2727}
2728
9db1d521 2729
c7453384
EC		 2730/* Return true if OP is a legitimate general operand when
2731 generating PIC code. It is given that flag_pic is on
994fe660
UW		 2732 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2733
9db1d521 2734int
5d81b82b 2735legitimate_pic_operand_p (rtx op)
9db1d521 2736{
4023fb28 2737 /* Accept all non-symbolic constants. */
9db1d521
HP		 2738 if (!SYMBOLIC_CONST (op))
2739 return 1;
2740
c7453384 2741 /* Reject everything else; must be handled
fd3cd001 2742 via emit_symbolic_move. */
9db1d521
HP		 2743 return 0;
2744}
2745
994fe660
UW		 2746/* Returns true if the constant value OP is a legitimate general operand.
2747 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2748
1a627b35 2749static bool
ef4bddc2 2750s390_legitimate_constant_p (machine_mode mode, rtx op)
9db1d521 2751{
4023fb28 2752 /* Accept all non-symbolic constants. */
9db1d521
HP		 2753 if (!SYMBOLIC_CONST (op))
2754 return 1;
2755
fd3cd001 2756 /* Accept immediate LARL operands. */
1a627b35 2757 if (TARGET_CPU_ZARCH && larl_operand (op, mode))
fd3cd001
UW		 2758 return 1;
2759
2760 /* Thread-local symbols are never legal constants. This is
2761 so that emit_call knows that computing such addresses
2762 might require a function call. */
2763 if (TLS_SYMBOLIC_CONST (op))
2764 return 0;
2765
9db1d521
HP		 2766 /* In the PIC case, symbolic constants must *not* be
2767 forced into the literal pool. We accept them here,
fd3cd001 2768 so that they will be handled by emit_symbolic_move. */
9db1d521
HP		 2769 if (flag_pic)
2770 return 1;
2771
9db1d521
HP		 2772 /* All remaining non-PIC symbolic constants are
2773 forced into the literal pool. */
2774 return 0;
2775}
2776
fd3cd001
UW		 2777/* Determine if it's legal to put X into the constant pool. This
2778 is not possible if X contains the address of a symbol that is
2779 not constant (TLS) or not known at final link time (PIC). */
2780
2781static bool
ef4bddc2 2782s390_cannot_force_const_mem (machine_mode mode, rtx x)
fd3cd001
UW		 2783{
2784 switch (GET_CODE (x))
2785 {
2786 case CONST_INT:
2787 case CONST_DOUBLE:
2788 /* Accept all non-symbolic constants. */
2789 return false;
2790
2791 case LABEL_REF:
2792 /* Labels are OK iff we are non-PIC. */
2793 return flag_pic != 0;
2794
2795 case SYMBOL_REF:
2796 /* 'Naked' TLS symbol references are never OK,
2797 non-TLS symbols are OK iff we are non-PIC. */
2798 if (tls_symbolic_operand (x))
2799 return true;
2800 else
2801 return flag_pic != 0;
2802
2803 case CONST:
fbbf66e7 2804 return s390_cannot_force_const_mem (mode, XEXP (x, 0));
fd3cd001
UW		 2805 case PLUS:
2806 case MINUS:
fbbf66e7
RS		 2807 return s390_cannot_force_const_mem (mode, XEXP (x, 0))
2808 || s390_cannot_force_const_mem (mode, XEXP (x, 1));
fd3cd001
UW		 2809
2810 case UNSPEC:
2811 switch (XINT (x, 1))
2812 {
2813 /* Only lt-relative or GOT-relative UNSPECs are OK. */
fd7643fb
UW		 2814 case UNSPEC_LTREL_OFFSET:
2815 case UNSPEC_GOT:
2816 case UNSPEC_GOTOFF:
2817 case UNSPEC_PLTOFF:
fd3cd001
UW		 2818 case UNSPEC_TLSGD:
2819 case UNSPEC_TLSLDM:
2820 case UNSPEC_NTPOFF:
2821 case UNSPEC_DTPOFF:
2822 case UNSPEC_GOTNTPOFF:
2823 case UNSPEC_INDNTPOFF:
2824 return false;
2825
9bb86f41
UW		 2826 /* If the literal pool shares the code section, be put
2827 execute template placeholders into the pool as well. */
2828 case UNSPEC_INSN:
2829 return TARGET_CPU_ZARCH;
2830
fd3cd001
UW		 2831 default:
2832 return true;
2833 }
2834 break;
2835
2836 default:
8d933e31 2837 gcc_unreachable ();
fd3cd001
UW		 2838 }
2839}
2840
4023fb28 2841/* Returns true if the constant value OP is a legitimate general
c7453384 2842 operand during and after reload. The difference to
4023fb28
UW		 2843 legitimate_constant_p is that this function will not accept
2844 a constant that would need to be forced to the literal pool
65b1d8ea
AK		 2845 before it can be used as operand.
2846 This function accepts all constants which can be loaded directly
2847 into a GPR. */
4023fb28 2848
3ed99cc9 2849bool
5d81b82b 2850legitimate_reload_constant_p (rtx op)
4023fb28 2851{
d3632d41 2852 /* Accept la(y) operands. */
c7453384 2853 if (GET_CODE (op) == CONST_INT
d3632d41 2854 && DISP_IN_RANGE (INTVAL (op)))
3ed99cc9 2855 return true;
d3632d41 2856
ec24698e 2857 /* Accept l(g)hi/l(g)fi operands. */
4023fb28 2858 if (GET_CODE (op) == CONST_INT
ec24698e 2859 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
3ed99cc9 2860 return true;
4023fb28
UW		 2861
2862 /* Accept lliXX operands. */
9e8327e3 2863 if (TARGET_ZARCH
11598938
UW		 2864 && GET_CODE (op) == CONST_INT
2865 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2866 && s390_single_part (op, word_mode, HImode, 0) >= 0)
3ed99cc9 2867 return true;
4023fb28 2868
ec24698e
UW		 2869 if (TARGET_EXTIMM
2870 && GET_CODE (op) == CONST_INT
2871 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2872 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2873 return true;
2874
4023fb28 2875 /* Accept larl operands. */
9e8327e3 2876 if (TARGET_CPU_ZARCH
4023fb28 2877 && larl_operand (op, VOIDmode))
3ed99cc9 2878 return true;
4023fb28 2879
45e5214c
UW		 2880 /* Accept floating-point zero operands that fit into a single GPR. */
2881 if (GET_CODE (op) == CONST_DOUBLE
2882 && s390_float_const_zero_p (op)
2883 && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
2884 return true;
2885
11598938
UW		 2886 /* Accept double-word operands that can be split. */
2887 if (GET_CODE (op) == CONST_INT
2888 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2889 {
ef4bddc2 2890 machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
11598938
UW		 2891 rtx hi = operand_subword (op, 0, 0, dword_mode);
2892 rtx lo = operand_subword (op, 1, 0, dword_mode);
2893 return legitimate_reload_constant_p (hi)
2894 && legitimate_reload_constant_p (lo);
2895 }
2896
4023fb28 2897 /* Everything else cannot be handled without reload. */
3ed99cc9 2898 return false;
4023fb28
UW		 2899}
2900
65b1d8ea
AK		 2901/* Returns true if the constant value OP is a legitimate fp operand
2902 during and after reload.
2903 This function accepts all constants which can be loaded directly
2904 into an FPR. */
2905
2906static bool
2907legitimate_reload_fp_constant_p (rtx op)
2908{
2909 /* Accept floating-point zero operands if the load zero instruction
22ac2c2f
AK		 2910 can be used. Prior to z196 the load fp zero instruction caused a
2911 performance penalty if the result is used as BFP number. */
65b1d8ea
AK		 2912 if (TARGET_Z196
2913 && GET_CODE (op) == CONST_DOUBLE
2914 && s390_float_const_zero_p (op))
2915 return true;
2916
2917 return false;
2918}
2919
0a2aaacc 2920/* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
4023fb28
UW		 2921 return the class of reg to actually use. */
2922
5df97412
AS		 2923static reg_class_t
2924s390_preferred_reload_class (rtx op, reg_class_t rclass)
4023fb28 2925{
4023fb28
UW		 2926 switch (GET_CODE (op))
2927 {
45e5214c
UW		 2928 /* Constants we cannot reload into general registers
2929 must be forced into the literal pool. */
4023fb28
UW		 2930 case CONST_DOUBLE:
2931 case CONST_INT:
45e5214c
UW		 2932 if (reg_class_subset_p (GENERAL_REGS, rclass)
2933 && legitimate_reload_constant_p (op))
2934 return GENERAL_REGS;
2935 else if (reg_class_subset_p (ADDR_REGS, rclass)
2936 && legitimate_reload_constant_p (op))
2937 return ADDR_REGS;
65b1d8ea
AK		 2938 else if (reg_class_subset_p (FP_REGS, rclass)
2939 && legitimate_reload_fp_constant_p (op))
2940 return FP_REGS;
2941 return NO_REGS;
4023fb28
UW		 2942
2943 /* If a symbolic constant or a PLUS is reloaded,
14b3e8ef
UW		 2944 it is most likely being used as an address, so
2945 prefer ADDR_REGS. If 'class' is not a superset
2946 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
1abcd5eb 2947 case CONST:
cb4b6d17
AK		 2948 /* Symrefs cannot be pushed into the literal pool with -fPIC
2949 so we *MUST NOT* return NO_REGS for these cases
2950 (s390_cannot_force_const_mem will return true).
2951
2952 On the other hand we MUST return NO_REGS for symrefs with
2953 invalid addend which might have been pushed to the literal
2954 pool (no -fPIC). Usually we would expect them to be
2955 handled via secondary reload but this does not happen if
2956 they are used as literal pool slot replacement in reload
2957 inheritance (see emit_input_reload_insns). */
1abcd5eb
AK		 2958 if (TARGET_CPU_ZARCH
2959 && GET_CODE (XEXP (op, 0)) == PLUS
2960 && GET_CODE (XEXP (XEXP(op, 0), 0)) == SYMBOL_REF
2961 && GET_CODE (XEXP (XEXP(op, 0), 1)) == CONST_INT)
2962 {
cb4b6d17 2963 if (flag_pic && reg_class_subset_p (ADDR_REGS, rclass))
1abcd5eb
AK		 2964 return ADDR_REGS;
2965 else
2966 return NO_REGS;
2967 }
2968 /* fallthrough */
4023fb28
UW		 2969 case LABEL_REF:
2970 case SYMBOL_REF:
212aa74f
AK		 2971 if (!legitimate_reload_constant_p (op))
2972 return NO_REGS;
2973 /* fallthrough */
2974 case PLUS:
2975 /* load address will be used. */
0a2aaacc 2976 if (reg_class_subset_p (ADDR_REGS, rclass))
212aa74f 2977 return ADDR_REGS;
14b3e8ef
UW		 2978 else
2979 return NO_REGS;
4023fb28
UW		 2980
2981 default:
2982 break;
2983 }
2984
0a2aaacc 2985 return rclass;
4023fb28 2986}
9db1d521 2987
963fc8d0
AK		 2988/* Return true if ADDR is SYMBOL_REF + addend with addend being a
2989 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2990 aligned. */
2991
2992bool
2993s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2994{
2995 HOST_WIDE_INT addend;
2996 rtx symref;
2997
0ff4390d
AK		 2998 if (!s390_loadrelative_operand_p (addr, &symref, &addend))
2999 return false;
98412b77 3000
0ff4390d 3001 if (addend & (alignment - 1))
963fc8d0
AK		 3002 return false;
3003
0ff4390d
AK		 3004 if (GET_CODE (symref) == SYMBOL_REF
3005 && !SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref))
3006 return true;
3007
3008 if (GET_CODE (symref) == UNSPEC
3009 && alignment <= UNITS_PER_LONG)
3010 return true;
3011
3012 return false;
963fc8d0
AK		 3013}
3014
3015/* ADDR is moved into REG using larl. If ADDR isn't a valid larl
3016 operand SCRATCH is used to reload the even part of the address and
3017 adding one. */
3018
3019void
3020s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
3021{
3022 HOST_WIDE_INT addend;
3023 rtx symref;
3024
0ff4390d 3025 if (!s390_loadrelative_operand_p (addr, &symref, &addend))
963fc8d0
AK		 3026 gcc_unreachable ();
3027
3028 if (!(addend & 1))
3029 /* Easy case. The addend is even so larl will do fine. */
3030 emit_move_insn (reg, addr);
3031 else
3032 {
3033 /* We can leave the scratch register untouched if the target
3034 register is a valid base register. */
3035 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
3036 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
3037 scratch = reg;
3038
3039 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
3040 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
3041
3042 if (addend != 1)
3043 emit_move_insn (scratch,
3044 gen_rtx_CONST (Pmode,
3045 gen_rtx_PLUS (Pmode, symref,
3046 GEN_INT (addend - 1))));
3047 else
3048 emit_move_insn (scratch, symref);
3049
3050 /* Increment the address using la in order to avoid clobbering cc. */
1abcd5eb 3051 s390_load_address (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
963fc8d0
AK		 3052 }
3053}
3054
3055/* Generate what is necessary to move between REG and MEM using
3056 SCRATCH. The direction is given by TOMEM. */
3057
3058void
3059s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
3060{
3061 /* Reload might have pulled a constant out of the literal pool.
3062 Force it back in. */
3063 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
3064 || GET_CODE (mem) == CONST)
3065 mem = force_const_mem (GET_MODE (reg), mem);
3066
3067 gcc_assert (MEM_P (mem));
3068
3069 /* For a load from memory we can leave the scratch register
3070 untouched if the target register is a valid base register. */
3071 if (!tomem
3072 && REGNO (reg) < FIRST_PSEUDO_REGISTER
3073 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
3074 && GET_MODE (reg) == GET_MODE (scratch))
3075 scratch = reg;
3076
3077 /* Load address into scratch register. Since we can't have a
3078 secondary reload for a secondary reload we have to cover the case
3079 where larl would need a secondary reload here as well. */
3080 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
3081
3082 /* Now we can use a standard load/store to do the move. */
3083 if (tomem)
3084 emit_move_insn (replace_equiv_address (mem, scratch), reg);
3085 else
3086 emit_move_insn (reg, replace_equiv_address (mem, scratch));
3087}
3088
833cd70a 3089/* Inform reload about cases where moving X with a mode MODE to a register in
0a2aaacc 3090 RCLASS requires an extra scratch or immediate register. Return the class
833cd70a 3091 needed for the immediate register. */
f61a2c7d 3092
a87cf97e
JR		 3093static reg_class_t
3094s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
ef4bddc2 3095 machine_mode mode, secondary_reload_info *sri)
833cd70a 3096{
a87cf97e
JR		 3097 enum reg_class rclass = (enum reg_class) rclass_i;
3098
833cd70a 3099 /* Intermediate register needed. */
0a2aaacc 3100 if (reg_classes_intersect_p (CC_REGS, rclass))
9dc62c00
AK		 3101 return GENERAL_REGS;
3102
963fc8d0
AK		 3103 if (TARGET_Z10)
3104 {
212aa74f
AK		 3105 HOST_WIDE_INT offset;
3106 rtx symref;
3107
963fc8d0
AK		 3108 /* On z10 several optimizer steps may generate larl operands with
3109 an odd addend. */
3110 if (in_p
0ff4390d 3111 && s390_loadrelative_operand_p (x, &symref, &offset)
963fc8d0 3112 && mode == Pmode
212aa74f
AK		 3113 && !SYMBOL_REF_ALIGN1_P (symref)
3114 && (offset & 1) == 1)
963fc8d0
AK		 3115 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3116 : CODE_FOR_reloadsi_larl_odd_addend_z10);
3117
3118 /* On z10 we need a scratch register when moving QI, TI or floating
3119 point mode values from or to a memory location with a SYMBOL_REF
3120 or if the symref addend of a SI or DI move is not aligned to the
3121 width of the access. */
3122 if (MEM_P (x)
0ff4390d 3123 && s390_loadrelative_operand_p (XEXP (x, 0), NULL, NULL)
963fc8d0 3124 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
9602b6a1 3125 || (!TARGET_ZARCH && mode == DImode)
963fc8d0
AK		 3126 || ((mode == HImode || mode == SImode || mode == DImode)
3127 && (!s390_check_symref_alignment (XEXP (x, 0),
3128 GET_MODE_SIZE (mode))))))
3129 {
3130#define __SECONDARY_RELOAD_CASE(M,m) \
3131 case M##mode: \
3132 if (TARGET_64BIT) \
3133 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3134 CODE_FOR_reload##m##di_tomem_z10; \
3135 else \
3136 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3137 CODE_FOR_reload##m##si_tomem_z10; \
3138 break;
3139
3140 switch (GET_MODE (x))
3141 {
3142 __SECONDARY_RELOAD_CASE (QI, qi);
3143 __SECONDARY_RELOAD_CASE (HI, hi);
3144 __SECONDARY_RELOAD_CASE (SI, si);
3145 __SECONDARY_RELOAD_CASE (DI, di);
3146 __SECONDARY_RELOAD_CASE (TI, ti);
3147 __SECONDARY_RELOAD_CASE (SF, sf);
3148 __SECONDARY_RELOAD_CASE (DF, df);
3149 __SECONDARY_RELOAD_CASE (TF, tf);
3150 __SECONDARY_RELOAD_CASE (SD, sd);
3151 __SECONDARY_RELOAD_CASE (DD, dd);
3152 __SECONDARY_RELOAD_CASE (TD, td);
3153
3154 default:
3155 gcc_unreachable ();
3156 }
3157#undef __SECONDARY_RELOAD_CASE
3158 }
3159 }
3160
833cd70a
AK		 3161 /* We need a scratch register when loading a PLUS expression which
3162 is not a legitimate operand of the LOAD ADDRESS instruction. */
3597e113
VM		 3163 /* LRA can deal with transformation of plus op very well -- so we
3164 don't need to prompt LRA in this case. */
3165 if (! lra_in_progress && in_p && s390_plus_operand (x, mode))
833cd70a
AK		 3166 sri->icode = (TARGET_64BIT ?
3167 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3168
7fa7289d 3169 /* Performing a multiword move from or to memory we have to make sure the
833cd70a
AK		 3170 second chunk in memory is addressable without causing a displacement
3171 overflow. If that would be the case we calculate the address in
3172 a scratch register. */
3173 if (MEM_P (x)
3174 && GET_CODE (XEXP (x, 0)) == PLUS
3175 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3176 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
0ca89db7 3177 + GET_MODE_SIZE (mode) - 1))
833cd70a 3178 {
7fa7289d 3179 /* For GENERAL_REGS a displacement overflow is no problem if occurring
833cd70a
AK		 3180 in a s_operand address since we may fallback to lm/stm. So we only
3181 have to care about overflows in the b+i+d case. */
0a2aaacc 3182 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
833cd70a
AK		 3183 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3184 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3185 /* For FP_REGS no lm/stm is available so this check is triggered
3186 for displacement overflows in b+i+d and b+d like addresses. */
0a2aaacc 3187 || (reg_classes_intersect_p (FP_REGS, rclass)
833cd70a
AK		 3188 && s390_class_max_nregs (FP_REGS, mode) > 1))
3189 {
3190 if (in_p)
3191 sri->icode = (TARGET_64BIT ?
3192 CODE_FOR_reloaddi_nonoffmem_in :
3193 CODE_FOR_reloadsi_nonoffmem_in);
3194 else
3195 sri->icode = (TARGET_64BIT ?
3196 CODE_FOR_reloaddi_nonoffmem_out :
3197 CODE_FOR_reloadsi_nonoffmem_out);
3198 }
3199 }
9dc62c00 3200
1f9e1fc6
AK		 3201 /* A scratch address register is needed when a symbolic constant is
3202 copied to r0 compiling with -fPIC. In other cases the target
3203 register might be used as temporary (see legitimize_pic_address). */
0a2aaacc 3204 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
1f9e1fc6
AK		 3205 sri->icode = (TARGET_64BIT ?
3206 CODE_FOR_reloaddi_PIC_addr :
3207 CODE_FOR_reloadsi_PIC_addr);
3208
833cd70a 3209 /* Either scratch or no register needed. */
dc65c307
UW		 3210 return NO_REGS;
3211}
3212
f3e9edff
UW		 3213/* Generate code to load SRC, which is PLUS that is not a
3214 legitimate operand for the LA instruction, into TARGET.
3215 SCRATCH may be used as scratch register. */
3216
3217void
5d81b82b
AS		 3218s390_expand_plus_operand (rtx target, rtx src,
3219 rtx scratch)
f3e9edff 3220{
7974fe63 3221 rtx sum1, sum2;
b808c04c 3222 struct s390_address ad;
6a4e49c1 3223
6a4e49c1 3224 /* src must be a PLUS; get its two operands. */
8d933e31
AS		 3225 gcc_assert (GET_CODE (src) == PLUS);
3226 gcc_assert (GET_MODE (src) == Pmode);
f3e9edff 3227
7c82a1ed
UW		 3228 /* Check if any of the two operands is already scheduled
3229 for replacement by reload. This can happen e.g. when
3230 float registers occur in an address. */
3231 sum1 = find_replacement (&XEXP (src, 0));
3232 sum2 = find_replacement (&XEXP (src, 1));
ccfc6cc8 3233 src = gen_rtx_PLUS (Pmode, sum1, sum2);
ccfc6cc8 3234
7974fe63
UW		 3235 /* If the address is already strictly valid, there's nothing to do. */
3236 if (!s390_decompose_address (src, &ad)
93fa8428
AK		 3237 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3238 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
f3e9edff 3239 {
7974fe63
UW		 3240 /* Otherwise, one of the operands cannot be an address register;
3241 we reload its value into the scratch register. */
3242 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3243 {
3244 emit_move_insn (scratch, sum1);
3245 sum1 = scratch;
3246 }
3247 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3248 {
3249 emit_move_insn (scratch, sum2);
3250 sum2 = scratch;
3251 }
f3e9edff 3252
7974fe63
UW		 3253 /* According to the way these invalid addresses are generated
3254 in reload.c, it should never happen (at least on s390) that
3255 *neither* of the PLUS components, after find_replacements
3256 was applied, is an address register. */
3257 if (sum1 == scratch && sum2 == scratch)
3258 {
3259 debug_rtx (src);
8d933e31 3260 gcc_unreachable ();
7974fe63 3261 }
f3e9edff 3262
7974fe63 3263 src = gen_rtx_PLUS (Pmode, sum1, sum2);
f3e9edff
UW		 3264 }
3265
3266 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3267 is only ever performed on addresses, so we can mark the
3268 sum as legitimate for LA in any case. */
a41c6c53 3269 s390_load_address (target, src);
f3e9edff
UW		 3270}
3271
3272
3ed99cc9 3273/* Return true if ADDR is a valid memory address.
ab96de7e 3274 STRICT specifies whether strict register checking applies. */
9db1d521 3275
c6c3dba9 3276static bool
ef4bddc2 3277s390_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
9db1d521 3278{
ab96de7e 3279 struct s390_address ad;
963fc8d0
AK		 3280
3281 if (TARGET_Z10
3282 && larl_operand (addr, VOIDmode)
3283 && (mode == VOIDmode
3284 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3285 return true;
3286
ab96de7e 3287 if (!s390_decompose_address (addr, &ad))
3ed99cc9 3288 return false;
b808c04c
UW		 3289
3290 if (strict)
3291 {
93fa8428 3292 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3ed99cc9 3293 return false;
93fa8428
AK		 3294
3295 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3ed99cc9 3296 return false;
b808c04c
UW		 3297 }
3298 else
3299 {
f4aa3848 3300 if (ad.base
93fa8428
AK		 3301 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3302 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3ed99cc9 3303 return false;
f4aa3848 3304
93fa8428
AK		 3305 if (ad.indx
3306 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3307 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3308 return false;
b808c04c 3309 }
3ed99cc9 3310 return true;
9db1d521
HP		 3311}
3312
3ed99cc9 3313/* Return true if OP is a valid operand for the LA instruction.
ba956982
UW		 3314 In 31-bit, we need to prove that the result is used as an
3315 address, as LA performs only a 31-bit addition. */
3316
3ed99cc9 3317bool
5d81b82b 3318legitimate_la_operand_p (rtx op)
ba956982
UW		 3319{
3320 struct s390_address addr;
b808c04c 3321 if (!s390_decompose_address (op, &addr))
3ed99cc9 3322 return false;
ba956982 3323
3ed99cc9 3324 return (TARGET_64BIT || addr.pointer);
f3e9edff 3325}
ba956982 3326
3ed99cc9 3327/* Return true if it is valid *and* preferable to use LA to
e1d5ee28 3328 compute the sum of OP1 and OP2. */
c7453384 3329
3ed99cc9 3330bool
e1d5ee28 3331preferred_la_operand_p (rtx op1, rtx op2)
100c7420
UW		 3332{
3333 struct s390_address addr;
e1d5ee28
UW		 3334
3335 if (op2 != const0_rtx)
3336 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3337
3338 if (!s390_decompose_address (op1, &addr))
3ed99cc9 3339 return false;
93fa8428 3340 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3ed99cc9 3341 return false;
93fa8428 3342 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3ed99cc9 3343 return false;
100c7420 3344
65b1d8ea 3345 /* Avoid LA instructions with index register on z196; it is
22ac2c2f
AK		 3346 preferable to use regular add instructions when possible.
3347 Starting with zEC12 the la with index register is "uncracked"
3348 again. */
65b1d8ea
AK		 3349 if (addr.indx && s390_tune == PROCESSOR_2817_Z196)
3350 return false;
3351
100c7420 3352 if (!TARGET_64BIT && !addr.pointer)
3ed99cc9 3353 return false;
100c7420
UW		 3354
3355 if (addr.pointer)
3ed99cc9 3356 return true;
100c7420 3357
4888ec5d
UW		 3358 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3359 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3ed99cc9 3360 return true;
100c7420 3361
3ed99cc9 3362 return false;
100c7420
UW		 3363}
3364
a41c6c53
UW		 3365/* Emit a forced load-address operation to load SRC into DST.
3366 This will use the LOAD ADDRESS instruction even in situations
3367 where legitimate_la_operand_p (SRC) returns false. */
ba956982 3368
a41c6c53 3369void
9c808aad 3370s390_load_address (rtx dst, rtx src)
f3e9edff 3371{
a41c6c53
UW		 3372 if (TARGET_64BIT)
3373 emit_move_insn (dst, src);
3374 else
3375 emit_insn (gen_force_la_31 (dst, src));
ba956982
UW		 3376}
3377
9db1d521
HP		 3378/* Return a legitimate reference for ORIG (an address) using the
3379 register REG. If REG is 0, a new pseudo is generated.
3380
3381 There are two types of references that must be handled:
3382
3383 1. Global data references must load the address from the GOT, via
3384 the PIC reg. An insn is emitted to do this load, and the reg is
3385 returned.
3386
3387 2. Static data references, constant pool addresses, and code labels
3388 compute the address as an offset from the GOT, whose base is in
114278e7 3389 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9db1d521
HP		 3390 differentiate them from global data objects. The returned
3391 address is the PIC reg + an unspec constant.
3392
331d9186 3393 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
9db1d521
HP		 3394 reg also appears in the address. */
3395
3396rtx
9c808aad 3397legitimize_pic_address (rtx orig, rtx reg)
9db1d521
HP		 3398{
3399 rtx addr = orig;
0ff4390d 3400 rtx addend = const0_rtx;
0a2aaacc 3401 rtx new_rtx = orig;
9db1d521 3402
cf9d7618
ANM		 3403 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3404
0ff4390d
AK		 3405 if (GET_CODE (addr) == CONST)
3406 addr = XEXP (addr, 0);
3407
3408 if (GET_CODE (addr) == PLUS)
9db1d521 3409 {
0ff4390d
AK		 3410 addend = XEXP (addr, 1);
3411 addr = XEXP (addr, 0);
3412 }
3413
3414 if ((GET_CODE (addr) == LABEL_REF
3415 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr))
3416 || (GET_CODE (addr) == UNSPEC &&
3417 (XINT (addr, 1) == UNSPEC_GOTENT
3418 || (TARGET_CPU_ZARCH && XINT (addr, 1) == UNSPEC_PLT))))
3419 && GET_CODE (addend) == CONST_INT)
3420 {
3421 /* This can be locally addressed. */
3422
3423 /* larl_operand requires UNSPECs to be wrapped in a const rtx. */
3424 rtx const_addr = (GET_CODE (addr) == UNSPEC ?
3425 gen_rtx_CONST (Pmode, addr) : addr);
3426
3427 if (TARGET_CPU_ZARCH
3428 && larl_operand (const_addr, VOIDmode)
3429 && INTVAL (addend) < (HOST_WIDE_INT)1 << 31
3430 && INTVAL (addend) >= -((HOST_WIDE_INT)1 << 31))
3431 {
3432 if (INTVAL (addend) & 1)
3433 {
3434 /* LARL can't handle odd offsets, so emit a pair of LARL
3435 and LA. */
3436 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3437
3438 if (!DISP_IN_RANGE (INTVAL (addend)))
3439 {
3440 HOST_WIDE_INT even = INTVAL (addend) - 1;
3441 addr = gen_rtx_PLUS (Pmode, addr, GEN_INT (even));
3442 addr = gen_rtx_CONST (Pmode, addr);
3443 addend = const1_rtx;
3444 }
3445
3446 emit_move_insn (temp, addr);
3447 new_rtx = gen_rtx_PLUS (Pmode, temp, addend);
3448
3449 if (reg != 0)
3450 {
3451 s390_load_address (reg, new_rtx);
3452 new_rtx = reg;
3453 }
3454 }
3455 else
3456 {
3457 /* If the offset is even, we can just use LARL. This
3458 will happen automatically. */
3459 }
3460 }
9db1d521 3461 else
0ff4390d
AK		 3462 {
3463 /* No larl - Access local symbols relative to the GOT. */
9db1d521 3464
0ff4390d 3465 rtx temp = reg? reg : gen_reg_rtx (Pmode);
9db1d521 3466
fd7643fb 3467 if (reload_in_progress || reload_completed)
6fb5fa3c 3468 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
fd7643fb 3469
0ff4390d
AK		 3470 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3471 if (addend != const0_rtx)
3472 addr = gen_rtx_PLUS (Pmode, addr, addend);
3473 addr = gen_rtx_CONST (Pmode, addr);
3474 addr = force_const_mem (Pmode, addr);
9db1d521
HP		 3475 emit_move_insn (temp, addr);
3476
0ff4390d
AK		 3477 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3478 if (reg != 0)
3479 {
3480 s390_load_address (reg, new_rtx);
3481 new_rtx = reg;
3482 }
3483 }
9db1d521 3484 }
0ff4390d 3485 else if (GET_CODE (addr) == SYMBOL_REF && addend == const0_rtx)
9db1d521 3486 {
0ff4390d
AK		 3487 /* A non-local symbol reference without addend.
3488
3489 The symbol ref is wrapped into an UNSPEC to make sure the
3490 proper operand modifier (@GOT or @GOTENT) will be emitted.
3491 This will tell the linker to put the symbol into the GOT.
3492
3493 Additionally the code dereferencing the GOT slot is emitted here.
3494
3495 An addend to the symref needs to be added afterwards.
3496 legitimize_pic_address calls itself recursively to handle
3497 that case. So no need to do it here. */
3498
9db1d521
HP		 3499 if (reg == 0)
3500 reg = gen_reg_rtx (Pmode);
3501
0ff4390d
AK		 3502 if (TARGET_Z10)
3503 {
3504 /* Use load relative if possible.
3505 lgrl <target>, sym@GOTENT */
3506 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3507 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3508 new_rtx = gen_const_mem (GET_MODE (reg), new_rtx);
3509
3510 emit_move_insn (reg, new_rtx);
3511 new_rtx = reg;
3512 }
3513 else if (flag_pic == 1)
9db1d521 3514 {
0ff4390d
AK		 3515 /* Assume GOT offset is a valid displacement operand (< 4k
3516 or < 512k with z990). This is handled the same way in
3517 both 31- and 64-bit code (@GOT).
3518 lg <target>, sym@GOT(r12) */
9db1d521 3519
c3cc6b78 3520 if (reload_in_progress || reload_completed)
6fb5fa3c 3521 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9db1d521 3522
0a2aaacc
KG		 3523 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3524 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3525 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3526 new_rtx = gen_const_mem (Pmode, new_rtx);
3527 emit_move_insn (reg, new_rtx);
3528 new_rtx = reg;
9db1d521 3529 }
9e8327e3 3530 else if (TARGET_CPU_ZARCH)
9db1d521
HP		 3531 {
3532 /* If the GOT offset might be >= 4k, we determine the position
0ff4390d
AK		 3533 of the GOT entry via a PC-relative LARL (@GOTENT).
3534 larl temp, sym@GOTENT
3535 lg <target>, 0(temp) */
9db1d521 3536
1f9e1fc6
AK		 3537 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3538
3539 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3540 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
9db1d521 3541
0a2aaacc
KG		 3542 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3543 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
0ff4390d 3544 emit_move_insn (temp, new_rtx);
9db1d521 3545
0ff4390d 3546 new_rtx = gen_const_mem (Pmode, temp);
0a2aaacc 3547 emit_move_insn (reg, new_rtx);
0ff4390d 3548
0a2aaacc 3549 new_rtx = reg;
9db1d521
HP		 3550 }
3551 else
3552 {
c7453384 3553 /* If the GOT offset might be >= 4k, we have to load it
0ff4390d
AK		 3554 from the literal pool (@GOT).
3555
3556 lg temp, lit-litbase(r13)
3557 lg <target>, 0(temp)
3558 lit: .long sym@GOT */
9db1d521 3559
1f9e1fc6
AK		 3560 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3561
3562 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3563 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
9db1d521 3564
c3cc6b78 3565 if (reload_in_progress || reload_completed)
6fb5fa3c 3566 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9db1d521 3567
fd7643fb 3568 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
e23795ea
UW		 3569 addr = gen_rtx_CONST (Pmode, addr);
3570 addr = force_const_mem (Pmode, addr);
9db1d521
HP		 3571 emit_move_insn (temp, addr);
3572
0a2aaacc
KG		 3573 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3574 new_rtx = gen_const_mem (Pmode, new_rtx);
3575 emit_move_insn (reg, new_rtx);
3576 new_rtx = reg;
9db1d521 3577 }
c7453384 3578 }
0ff4390d 3579 else if (GET_CODE (addr) == UNSPEC && GET_CODE (addend) == CONST_INT)
9db1d521 3580 {
0ff4390d
AK		 3581 gcc_assert (XVECLEN (addr, 0) == 1);
3582 switch (XINT (addr, 1))
9db1d521 3583 {
0ff4390d
AK		 3584 /* These address symbols (or PLT slots) relative to the GOT
3585 (not GOT slots!). In general this will exceed the
3586 displacement range so these value belong into the literal
3587 pool. */
3588 case UNSPEC_GOTOFF:
3589 case UNSPEC_PLTOFF:
3590 new_rtx = force_const_mem (Pmode, orig);
3591 break;
9db1d521 3592
0ff4390d
AK		 3593 /* For -fPIC the GOT size might exceed the displacement
3594 range so make sure the value is in the literal pool. */
3595 case UNSPEC_GOT:
3596 if (flag_pic == 2)
3597 new_rtx = force_const_mem (Pmode, orig);
3598 break;
9db1d521 3599
0ff4390d
AK		 3600 /* For @GOTENT larl is used. This is handled like local
3601 symbol refs. */
3602 case UNSPEC_GOTENT:
3603 gcc_unreachable ();
3604 break;
9db1d521 3605
0ff4390d
AK		 3606 /* @PLT is OK as is on 64-bit, must be converted to
3607 GOT-relative @PLTOFF on 31-bit. */
3608 case UNSPEC_PLT:
3609 if (!TARGET_CPU_ZARCH)
9db1d521 3610 {
0ff4390d
AK		 3611 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3612
3613 if (reload_in_progress || reload_completed)
3614 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3615
3616 addr = XVECEXP (addr, 0, 0);
3617 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3618 UNSPEC_PLTOFF);
3619 if (addend != const0_rtx)
3620 addr = gen_rtx_PLUS (Pmode, addr, addend);
3621 addr = gen_rtx_CONST (Pmode, addr);
3622 addr = force_const_mem (Pmode, addr);
3623 emit_move_insn (temp, addr);
3624
3625 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3626 if (reg != 0)
9db1d521 3627 {
0ff4390d
AK		 3628 s390_load_address (reg, new_rtx);
3629 new_rtx = reg;
9db1d521 3630 }
0ff4390d
AK		 3631 }
3632 else
3633 /* On 64 bit larl can be used. This case is handled like
3634 local symbol refs. */
3635 gcc_unreachable ();
3636 break;
3637
3638 /* Everything else cannot happen. */
3639 default:
3640 gcc_unreachable ();
3641 }
3642 }
3643 else if (addend != const0_rtx)
3644 {
3645 /* Otherwise, compute the sum. */
9db1d521 3646
0ff4390d
AK		 3647 rtx base = legitimize_pic_address (addr, reg);
3648 new_rtx = legitimize_pic_address (addend,
3649 base == reg ? NULL_RTX : reg);
3650 if (GET_CODE (new_rtx) == CONST_INT)
3651 new_rtx = plus_constant (Pmode, base, INTVAL (new_rtx));
3652 else
3653 {
3654 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3655 {
3656 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3657 new_rtx = XEXP (new_rtx, 1);
9db1d521 3658 }
0ff4390d 3659 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
9db1d521 3660 }
0ff4390d
AK		 3661
3662 if (GET_CODE (new_rtx) == CONST)
3663 new_rtx = XEXP (new_rtx, 0);
3664 new_rtx = force_operand (new_rtx, 0);
9db1d521 3665 }
0ff4390d 3666
0a2aaacc 3667 return new_rtx;
9db1d521
HP		 3668}
3669
fd3cd001
UW		 3670/* Load the thread pointer into a register. */
3671
7b8acc34
AK		 3672rtx
3673s390_get_thread_pointer (void)
fd3cd001 3674{
c5aa1d12 3675 rtx tp = gen_reg_rtx (Pmode);
fd3cd001 3676
c5aa1d12 3677 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
fd3cd001
UW		 3678 mark_reg_pointer (tp, BITS_PER_WORD);
3679
3680 return tp;
3681}
3682
ed9676cf
AK		 3683/* Emit a tls call insn. The call target is the SYMBOL_REF stored
3684 in s390_tls_symbol which always refers to __tls_get_offset.
3685 The returned offset is written to RESULT_REG and an USE rtx is
3686 generated for TLS_CALL. */
fd3cd001
UW		 3687
3688static GTY(()) rtx s390_tls_symbol;
ed9676cf
AK		 3689
3690static void
3691s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
fd3cd001 3692{
ed9676cf 3693 rtx insn;
38899e29 3694
68c0ef75
AK		 3695 if (!flag_pic)
3696 emit_insn (s390_load_got ());
ed9676cf 3697
fd3cd001
UW		 3698 if (!s390_tls_symbol)
3699 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3700
38899e29
EC		 3701 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3702 gen_rtx_REG (Pmode, RETURN_REGNUM));
ed9676cf
AK		 3703
3704 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
becfd6e5 3705 RTL_CONST_CALL_P (insn) = 1;
fd3cd001
UW		 3706}
3707
3708/* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3709 this (thread-local) address. REG may be used as temporary. */
3710
3711static rtx
9c808aad 3712legitimize_tls_address (rtx addr, rtx reg)
fd3cd001 3713{
0a2aaacc 3714 rtx new_rtx, tls_call, temp, base, r2, insn;
fd3cd001
UW		 3715
3716 if (GET_CODE (addr) == SYMBOL_REF)
3717 switch (tls_symbolic_operand (addr))
3718 {
3719 case TLS_MODEL_GLOBAL_DYNAMIC:
3720 start_sequence ();
3721 r2 = gen_rtx_REG (Pmode, 2);
3722 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
0a2aaacc
KG		 3723 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3724 new_rtx = force_const_mem (Pmode, new_rtx);
3725 emit_move_insn (r2, new_rtx);
ed9676cf 3726 s390_emit_tls_call_insn (r2, tls_call);
fd3cd001
UW		 3727 insn = get_insns ();
3728 end_sequence ();
3729
0a2aaacc 3730 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
fd3cd001 3731 temp = gen_reg_rtx (Pmode);
0a2aaacc 3732 emit_libcall_block (insn, temp, r2, new_rtx);
fd3cd001 3733
0a2aaacc 3734 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
fd3cd001
UW		 3735 if (reg != 0)
3736 {
0a2aaacc
KG		 3737 s390_load_address (reg, new_rtx);
3738 new_rtx = reg;
fd3cd001
UW		 3739 }
3740 break;
3741
3742 case TLS_MODEL_LOCAL_DYNAMIC:
3743 start_sequence ();
3744 r2 = gen_rtx_REG (Pmode, 2);
3745 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
0a2aaacc
KG		 3746 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3747 new_rtx = force_const_mem (Pmode, new_rtx);
3748 emit_move_insn (r2, new_rtx);
ed9676cf 3749 s390_emit_tls_call_insn (r2, tls_call);
fd3cd001
UW		 3750 insn = get_insns ();
3751 end_sequence ();
3752
0a2aaacc 3753 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
fd3cd001 3754 temp = gen_reg_rtx (Pmode);
0a2aaacc 3755 emit_libcall_block (insn, temp, r2, new_rtx);
fd3cd001 3756
0a2aaacc 3757 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
fd3cd001 3758 base = gen_reg_rtx (Pmode);
0a2aaacc 3759 s390_load_address (base, new_rtx);
fd3cd001 3760
0a2aaacc
KG		 3761 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3762 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3763 new_rtx = force_const_mem (Pmode, new_rtx);
fd3cd001 3764 temp = gen_reg_rtx (Pmode);
0a2aaacc 3765 emit_move_insn (temp, new_rtx);
fd3cd001 3766
0a2aaacc 3767 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
fd3cd001
UW		 3768 if (reg != 0)
3769 {
0a2aaacc
KG		 3770 s390_load_address (reg, new_rtx);
3771 new_rtx = reg;
fd3cd001
UW		 3772 }
3773 break;
3774
3775 case TLS_MODEL_INITIAL_EXEC:
3776 if (flag_pic == 1)
3777 {
3778 /* Assume GOT offset < 4k. This is handled the same way
3779 in both 31- and 64-bit code. */
3780
3781 if (reload_in_progress || reload_completed)
6fb5fa3c 3782 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
fd3cd001 3783
0a2aaacc
KG		 3784 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3785 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3786 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3787 new_rtx = gen_const_mem (Pmode, new_rtx);
fd3cd001 3788 temp = gen_reg_rtx (Pmode);
0a2aaacc 3789 emit_move_insn (temp, new_rtx);
fd3cd001 3790 }
9e8327e3 3791 else if (TARGET_CPU_ZARCH)
fd3cd001
UW		 3792 {
3793 /* If the GOT offset might be >= 4k, we determine the position
3794 of the GOT entry via a PC-relative LARL. */
3795
0a2aaacc
KG		 3796 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3797 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
fd3cd001 3798 temp = gen_reg_rtx (Pmode);
0a2aaacc 3799 emit_move_insn (temp, new_rtx);
fd3cd001 3800
0a2aaacc 3801 new_rtx = gen_const_mem (Pmode, temp);
fd3cd001 3802 temp = gen_reg_rtx (Pmode);
0a2aaacc 3803 emit_move_insn (temp, new_rtx);
fd3cd001
UW		 3804 }
3805 else if (flag_pic)
3806 {
c7453384 3807 /* If the GOT offset might be >= 4k, we have to load it
fd3cd001
UW		 3808 from the literal pool. */
3809
3810 if (reload_in_progress || reload_completed)
6fb5fa3c 3811 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
fd3cd001 3812
0a2aaacc
KG		 3813 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3814 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3815 new_rtx = force_const_mem (Pmode, new_rtx);
fd3cd001 3816 temp = gen_reg_rtx (Pmode);
0a2aaacc 3817 emit_move_insn (temp, new_rtx);
fd3cd001 3818
0a2aaacc
KG		 3819 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3820 new_rtx = gen_const_mem (Pmode, new_rtx);
fd3cd001 3821
0a2aaacc 3822 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
fd3cd001 3823 temp = gen_reg_rtx (Pmode);
0a2aaacc 3824 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
fd3cd001
UW		 3825 }
3826 else
3827 {
3828 /* In position-dependent code, load the absolute address of
3829 the GOT entry from the literal pool. */
3830
0a2aaacc
KG		 3831 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3832 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3833 new_rtx = force_const_mem (Pmode, new_rtx);
fd3cd001 3834 temp = gen_reg_rtx (Pmode);
0a2aaacc 3835 emit_move_insn (temp, new_rtx);
fd3cd001 3836
0a2aaacc
KG		 3837 new_rtx = temp;
3838 new_rtx = gen_const_mem (Pmode, new_rtx);
3839 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
fd3cd001 3840 temp = gen_reg_rtx (Pmode);
0a2aaacc 3841 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
fd3cd001
UW		 3842 }
3843
0a2aaacc 3844 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
fd3cd001
UW		 3845 if (reg != 0)
3846 {
0a2aaacc
KG		 3847 s390_load_address (reg, new_rtx);
3848 new_rtx = reg;
fd3cd001
UW		 3849 }
3850 break;
3851
3852 case TLS_MODEL_LOCAL_EXEC:
0a2aaacc
KG		 3853 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3854 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3855 new_rtx = force_const_mem (Pmode, new_rtx);
fd3cd001 3856 temp = gen_reg_rtx (Pmode);
0a2aaacc 3857 emit_move_insn (temp, new_rtx);
fd3cd001 3858
0a2aaacc 3859 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
fd3cd001
UW		 3860 if (reg != 0)
3861 {
0a2aaacc
KG		 3862 s390_load_address (reg, new_rtx);
3863 new_rtx = reg;
fd3cd001
UW		 3864 }
3865 break;
3866
3867 default:
8d933e31 3868 gcc_unreachable ();
fd3cd001
UW		 3869 }
3870
3871 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3872 {
3873 switch (XINT (XEXP (addr, 0), 1))
3874 {
3875 case UNSPEC_INDNTPOFF:
8d933e31 3876 gcc_assert (TARGET_CPU_ZARCH);
0a2aaacc 3877 new_rtx = addr;
fd3cd001
UW		 3878 break;
3879
3880 default:
8d933e31 3881 gcc_unreachable ();
fd3cd001
UW		 3882 }
3883 }
3884
578d1468
UW		 3885 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3886 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3887 {
0a2aaacc
KG		 3888 new_rtx = XEXP (XEXP (addr, 0), 0);
3889 if (GET_CODE (new_rtx) != SYMBOL_REF)
3890 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
578d1468 3891
0a2aaacc 3892 new_rtx = legitimize_tls_address (new_rtx, reg);
0a81f074
RS		 3893 new_rtx = plus_constant (Pmode, new_rtx,
3894 INTVAL (XEXP (XEXP (addr, 0), 1)));
0a2aaacc 3895 new_rtx = force_operand (new_rtx, 0);
578d1468
UW		 3896 }
3897
fd3cd001 3898 else
8d933e31 3899 gcc_unreachable (); /* for now ... */
fd3cd001 3900
0a2aaacc 3901 return new_rtx;
fd3cd001
UW		 3902}
3903
1f9e1fc6
AK		 3904/* Emit insns making the address in operands[1] valid for a standard
3905 move to operands[0]. operands[1] is replaced by an address which
3906 should be used instead of the former RTX to emit the move
3907 pattern. */
9db1d521
HP		 3908
3909void
9c808aad 3910emit_symbolic_move (rtx *operands)
9db1d521 3911{
b3a13419 3912 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
9db1d521 3913
fd3cd001 3914 if (GET_CODE (operands[0]) == MEM)
9db1d521 3915 operands[1] = force_reg (Pmode, operands[1]);
fd3cd001
UW		 3916 else if (TLS_SYMBOLIC_CONST (operands[1]))
3917 operands[1] = legitimize_tls_address (operands[1], temp);
3918 else if (flag_pic)
9db1d521
HP		 3919 operands[1] = legitimize_pic_address (operands[1], temp);
3920}
3921
994fe660 3922/* Try machine-dependent ways of modifying an illegitimate address X
9db1d521 3923 to be legitimate. If we find one, return the new, valid address.
9db1d521
HP		 3924
3925 OLDX is the address as it was before break_out_memory_refs was called.
3926 In some cases it is useful to look at this to decide what needs to be done.
3927
994fe660 3928 MODE is the mode of the operand pointed to by X.
9db1d521
HP		 3929
3930 When -fpic is used, special handling is needed for symbolic references.
3931 See comments by legitimize_pic_address for details. */
3932
506d7b68
PB		 3933static rtx
3934s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
ef4bddc2 3935 machine_mode mode ATTRIBUTE_UNUSED)
9db1d521 3936{
ba956982 3937 rtx constant_term = const0_rtx;
9db1d521 3938
fd3cd001
UW		 3939 if (TLS_SYMBOLIC_CONST (x))
3940 {
3941 x = legitimize_tls_address (x, 0);
3942
c6c3dba9 3943 if (s390_legitimate_address_p (mode, x, FALSE))
fd3cd001
UW		 3944 return x;
3945 }
cf9d7618 3946 else if (GET_CODE (x) == PLUS
f4aa3848 3947 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
cf9d7618
ANM		 3948 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3949 {
3950 return x;
3951 }
fd3cd001 3952 else if (flag_pic)
9db1d521 3953 {
ba956982 3954 if (SYMBOLIC_CONST (x)
c7453384
EC		 3955 || (GET_CODE (x) == PLUS
3956 && (SYMBOLIC_CONST (XEXP (x, 0))
ba956982
UW		 3957 || SYMBOLIC_CONST (XEXP (x, 1)))))
3958 x = legitimize_pic_address (x, 0);
3959
c6c3dba9 3960 if (s390_legitimate_address_p (mode, x, FALSE))
ba956982 3961 return x;
9db1d521 3962 }
9db1d521 3963
ba956982 3964 x = eliminate_constant_term (x, &constant_term);
994fe660 3965
61f02ff5
UW		 3966 /* Optimize loading of large displacements by splitting them
3967 into the multiple of 4K and the rest; this allows the
c7453384 3968 former to be CSE'd if possible.
61f02ff5
UW		 3969
3970 Don't do this if the displacement is added to a register
3971 pointing into the stack frame, as the offsets will
3972 change later anyway. */
3973
3974 if (GET_CODE (constant_term) == CONST_INT
d3632d41
UW		 3975 && !TARGET_LONG_DISPLACEMENT
3976 && !DISP_IN_RANGE (INTVAL (constant_term))
61f02ff5
UW		 3977 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3978 {
3979 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3980 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3981
3982 rtx temp = gen_reg_rtx (Pmode);
3983 rtx val = force_operand (GEN_INT (upper), temp);
3984 if (val != temp)
3985 emit_move_insn (temp, val);
3986
3987 x = gen_rtx_PLUS (Pmode, x, temp);
3988 constant_term = GEN_INT (lower);
3989 }
3990
ba956982 3991 if (GET_CODE (x) == PLUS)
9db1d521 3992 {
ba956982
UW		 3993 if (GET_CODE (XEXP (x, 0)) == REG)
3994 {
5d81b82b
AS		 3995 rtx temp = gen_reg_rtx (Pmode);
3996 rtx val = force_operand (XEXP (x, 1), temp);
ba956982
UW		 3997 if (val != temp)
3998 emit_move_insn (temp, val);
3999
4000 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
4001 }
4002
4003 else if (GET_CODE (XEXP (x, 1)) == REG)
4004 {
5d81b82b
AS		 4005 rtx temp = gen_reg_rtx (Pmode);
4006 rtx val = force_operand (XEXP (x, 0), temp);
ba956982
UW		 4007 if (val != temp)
4008 emit_move_insn (temp, val);
4009
4010 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
4011 }
9db1d521 4012 }
ba956982
UW		 4013
4014 if (constant_term != const0_rtx)
4015 x = gen_rtx_PLUS (Pmode, x, constant_term);
4016
4017 return x;
9db1d521
HP		 4018}
4019
0b540f12 4020/* Try a machine-dependent way of reloading an illegitimate address AD
dd5a833e 4021 operand. If we find one, push the reload and return the new address.
0b540f12
UW		 4022
4023 MODE is the mode of the enclosing MEM. OPNUM is the operand number
4024 and TYPE is the reload type of the current reload. */
4025
f4aa3848 4026rtx
ef4bddc2 4027legitimize_reload_address (rtx ad, machine_mode mode ATTRIBUTE_UNUSED,
0b540f12
UW		 4028 int opnum, int type)
4029{
4030 if (!optimize || TARGET_LONG_DISPLACEMENT)
4031 return NULL_RTX;
4032
4033 if (GET_CODE (ad) == PLUS)
4034 {
4035 rtx tem = simplify_binary_operation (PLUS, Pmode,
4036 XEXP (ad, 0), XEXP (ad, 1));
4037 if (tem)
4038 ad = tem;
4039 }
4040
4041 if (GET_CODE (ad) == PLUS
4042 && GET_CODE (XEXP (ad, 0)) == REG
4043 && GET_CODE (XEXP (ad, 1)) == CONST_INT
4044 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
4045 {
4046 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
4047 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
0a2aaacc 4048 rtx cst, tem, new_rtx;
0b540f12
UW		 4049
4050 cst = GEN_INT (upper);
4051 if (!legitimate_reload_constant_p (cst))
4052 cst = force_const_mem (Pmode, cst);
4053
4054 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
0a2aaacc 4055 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
0b540f12
UW		 4056
4057 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
f4aa3848 4058 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
0b540f12 4059 opnum, (enum reload_type) type);
0a2aaacc 4060 return new_rtx;
0b540f12
UW		 4061 }
4062
4063 return NULL_RTX;
4064}
4065
a41c6c53
UW		 4066/* Emit code to move LEN bytes from DST to SRC. */
4067
367d32f3 4068bool
70128ad9 4069s390_expand_movmem (rtx dst, rtx src, rtx len)
a41c6c53 4070{
367d32f3
AK		 4071 /* When tuning for z10 or higher we rely on the Glibc functions to
4072 do the right thing. Only for constant lengths below 64k we will
4073 generate inline code. */
4074 if (s390_tune >= PROCESSOR_2097_Z10
4075 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4076 return false;
4077
a41c6c53
UW		 4078 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4079 {
4080 if (INTVAL (len) > 0)
70128ad9 4081 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
a41c6c53
UW		 4082 }
4083
4084 else if (TARGET_MVCLE)
4085 {
70128ad9 4086 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
a41c6c53
UW		 4087 }
4088
4089 else
4090 {
4091 rtx dst_addr, src_addr, count, blocks, temp;
19f8b229
TS		 4092 rtx_code_label *loop_start_label = gen_label_rtx ();
4093 rtx_code_label *loop_end_label = gen_label_rtx ();
4094 rtx_code_label *end_label = gen_label_rtx ();
ef4bddc2 4095 machine_mode mode;
a41c6c53
UW		 4096
4097 mode = GET_MODE (len);
4098 if (mode == VOIDmode)
b9404c99 4099 mode = Pmode;
a41c6c53 4100
a41c6c53
UW		 4101 dst_addr = gen_reg_rtx (Pmode);
4102 src_addr = gen_reg_rtx (Pmode);
4103 count = gen_reg_rtx (mode);
4104 blocks = gen_reg_rtx (mode);
4105
4106 convert_move (count, len, 1);
c7453384 4107 emit_cmp_and_jump_insns (count, const0_rtx,
a41c6c53
UW		 4108 EQ, NULL_RTX, mode, 1, end_label);
4109
4110 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4111 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
4112 dst = change_address (dst, VOIDmode, dst_addr);
4113 src = change_address (src, VOIDmode, src_addr);
c7453384 4114
bbbbb16a
ILT		 4115 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4116 OPTAB_DIRECT);
a41c6c53
UW		 4117 if (temp != count)
4118 emit_move_insn (count, temp);
4119
bbbbb16a
ILT		 4120 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4121 OPTAB_DIRECT);
a41c6c53
UW		 4122 if (temp != blocks)
4123 emit_move_insn (blocks, temp);
4124
6de9cd9a
DN		 4125 emit_cmp_and_jump_insns (blocks, const0_rtx,
4126 EQ, NULL_RTX, mode, 1, loop_end_label);
70315fcd
SB		 4127
4128 emit_label (loop_start_label);
a41c6c53 4129
adfa3cd3
AK		 4130 if (TARGET_Z10
4131 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
4132 {
4133 rtx prefetch;
4134
4135 /* Issue a read prefetch for the +3 cache line. */
4136 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
4137 const0_rtx, const0_rtx);
4138 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4139 emit_insn (prefetch);
4140
4141 /* Issue a write prefetch for the +3 cache line. */
4142 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
4143 const1_rtx, const0_rtx);
4144 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4145 emit_insn (prefetch);
4146 }
4147
70128ad9 4148 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
c7453384 4149 s390_load_address (dst_addr,
a41c6c53 4150 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
c7453384 4151 s390_load_address (src_addr,
a41c6c53 4152 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
c7453384 4153
bbbbb16a
ILT		 4154 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4155 OPTAB_DIRECT);
a41c6c53
UW		 4156 if (temp != blocks)
4157 emit_move_insn (blocks, temp);
4158
6de9cd9a
DN		 4159 emit_cmp_and_jump_insns (blocks, const0_rtx,
4160 EQ, NULL_RTX, mode, 1, loop_end_label);
70315fcd
SB		 4161
4162 emit_jump (loop_start_label);
6de9cd9a 4163 emit_label (loop_end_label);
a41c6c53 4164
70128ad9 4165 emit_insn (gen_movmem_short (dst, src,
b9404c99 4166 convert_to_mode (Pmode, count, 1)));
a41c6c53
UW		 4167 emit_label (end_label);
4168 }
367d32f3 4169 return true;
a41c6c53
UW		 4170}
4171
6d057022
AS		 4172/* Emit code to set LEN bytes at DST to VAL.
4173 Make use of clrmem if VAL is zero. */
a41c6c53
UW		 4174
4175void
6d057022 4176s390_expand_setmem (rtx dst, rtx len, rtx val)
a41c6c53 4177{
c9f59991
AK		 4178 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4179 return;
4180
6d057022 4181 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
f4aa3848 4182
c9f59991 4183 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
a41c6c53 4184 {
6d057022 4185 if (val == const0_rtx && INTVAL (len) <= 256)
70128ad9 4186 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
6d057022
AS		 4187 else
4188 {
4189 /* Initialize memory by storing the first byte. */
4190 emit_move_insn (adjust_address (dst, QImode, 0), val);
f4aa3848 4191
6d057022
AS		 4192 if (INTVAL (len) > 1)
4193 {
4194 /* Initiate 1 byte overlap move.
4195 The first byte of DST is propagated through DSTP1.
4196 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4197 DST is set to size 1 so the rest of the memory location
4198 does not count as source operand. */
4199 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
f5541398 4200 set_mem_size (dst, 1);
6d057022 4201
f4aa3848 4202 emit_insn (gen_movmem_short (dstp1, dst,
6d057022
AS		 4203 GEN_INT (INTVAL (len) - 2)));
4204 }
4205 }
a41c6c53
UW		 4206 }
4207
4208 else if (TARGET_MVCLE)
4209 {
6d057022
AS		 4210 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4211 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
a41c6c53
UW		 4212 }
4213
4214 else
4215 {
9602b6a1 4216 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
19f8b229
TS		 4217 rtx_code_label *loop_start_label = gen_label_rtx ();
4218 rtx_code_label *loop_end_label = gen_label_rtx ();
4219 rtx_code_label *end_label = gen_label_rtx ();
ef4bddc2 4220 machine_mode mode;
a41c6c53
UW		 4221
4222 mode = GET_MODE (len);
4223 if (mode == VOIDmode)
b9404c99 4224 mode = Pmode;
a41c6c53 4225
a41c6c53 4226 dst_addr = gen_reg_rtx (Pmode);
a41c6c53
UW		 4227 count = gen_reg_rtx (mode);
4228 blocks = gen_reg_rtx (mode);
4229
4230 convert_move (count, len, 1);
c7453384 4231 emit_cmp_and_jump_insns (count, const0_rtx,
a41c6c53
UW		 4232 EQ, NULL_RTX, mode, 1, end_label);
4233
4234 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4235 dst = change_address (dst, VOIDmode, dst_addr);
c7453384 4236
6d057022 4237 if (val == const0_rtx)
bbbbb16a
ILT		 4238 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4239 OPTAB_DIRECT);
6d057022
AS		 4240 else
4241 {
4242 dstp1 = adjust_address (dst, VOIDmode, 1);
f5541398 4243 set_mem_size (dst, 1);
6d057022
AS		 4244
4245 /* Initialize memory by storing the first byte. */
4246 emit_move_insn (adjust_address (dst, QImode, 0), val);
f4aa3848 4247
6d057022
AS		 4248 /* If count is 1 we are done. */
4249 emit_cmp_and_jump_insns (count, const1_rtx,
4250 EQ, NULL_RTX, mode, 1, end_label);
4251
bbbbb16a
ILT		 4252 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4253 OPTAB_DIRECT);
6d057022 4254 }
a41c6c53
UW		 4255 if (temp != count)
4256 emit_move_insn (count, temp);
4257
bbbbb16a
ILT		 4258 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4259 OPTAB_DIRECT);
a41c6c53
UW		 4260 if (temp != blocks)
4261 emit_move_insn (blocks, temp);
4262
6de9cd9a
DN		 4263 emit_cmp_and_jump_insns (blocks, const0_rtx,
4264 EQ, NULL_RTX, mode, 1, loop_end_label);
70315fcd
SB		 4265
4266 emit_label (loop_start_label);
a41c6c53 4267
adfa3cd3
AK		 4268 if (TARGET_Z10
4269 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4270 {
4271 /* Issue a write prefetch for the +4 cache line. */
4272 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4273 GEN_INT (1024)),
4274 const1_rtx, const0_rtx);
4275 emit_insn (prefetch);
4276 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4277 }
4278
6d057022
AS		 4279 if (val == const0_rtx)
4280 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4281 else
4282 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
c7453384 4283 s390_load_address (dst_addr,
a41c6c53 4284 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
c7453384 4285
bbbbb16a
ILT		 4286 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4287 OPTAB_DIRECT);
a41c6c53
UW		 4288 if (temp != blocks)
4289 emit_move_insn (blocks, temp);
4290
6de9cd9a
DN		 4291 emit_cmp_and_jump_insns (blocks, const0_rtx,
4292 EQ, NULL_RTX, mode, 1, loop_end_label);
70315fcd
SB		 4293
4294 emit_jump (loop_start_label);
6de9cd9a 4295 emit_label (loop_end_label);
a41c6c53 4296
6d057022
AS		 4297 if (val == const0_rtx)
4298 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4299 else
4300 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
a41c6c53
UW		 4301 emit_label (end_label);
4302 }
4303}
4304
4305/* Emit code to compare LEN bytes at OP0 with those at OP1,
4306 and return the result in TARGET. */
4307
367d32f3 4308bool
9c808aad 4309s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
a41c6c53 4310{
5b022de5 4311 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
02887425
UW		 4312 rtx tmp;
4313
367d32f3
AK		 4314 /* When tuning for z10 or higher we rely on the Glibc functions to
4315 do the right thing. Only for constant lengths below 64k we will
4316 generate inline code. */
4317 if (s390_tune >= PROCESSOR_2097_Z10
4318 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4319 return false;
4320
02887425
UW		 4321 /* As the result of CMPINT is inverted compared to what we need,
4322 we have to swap the operands. */
4323 tmp = op0; op0 = op1; op1 = tmp;
a41c6c53 4324
a41c6c53
UW		 4325 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4326 {
4327 if (INTVAL (len) > 0)
4328 {
b9404c99 4329 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
02887425 4330 emit_insn (gen_cmpint (target, ccreg));
a41c6c53
UW		 4331 }
4332 else
4333 emit_move_insn (target, const0_rtx);
4334 }
9dc62c00 4335 else if (TARGET_MVCLE)
a41c6c53 4336 {
b9404c99 4337 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
02887425 4338 emit_insn (gen_cmpint (target, ccreg));
a41c6c53 4339 }
a41c6c53
UW		 4340 else
4341 {
4342 rtx addr0, addr1, count, blocks, temp;
19f8b229
TS		 4343 rtx_code_label *loop_start_label = gen_label_rtx ();
4344 rtx_code_label *loop_end_label = gen_label_rtx ();
4345 rtx_code_label *end_label = gen_label_rtx ();
ef4bddc2 4346 machine_mode mode;
a41c6c53
UW		 4347
4348 mode = GET_MODE (len);
4349 if (mode == VOIDmode)
b9404c99 4350 mode = Pmode;
a41c6c53 4351
a41c6c53
UW		 4352 addr0 = gen_reg_rtx (Pmode);
4353 addr1 = gen_reg_rtx (Pmode);
4354 count = gen_reg_rtx (mode);
4355 blocks = gen_reg_rtx (mode);
4356
4357 convert_move (count, len, 1);
c7453384 4358 emit_cmp_and_jump_insns (count, const0_rtx,
a41c6c53
UW		 4359 EQ, NULL_RTX, mode, 1, end_label);
4360
4361 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4362 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4363 op0 = change_address (op0, VOIDmode, addr0);
4364 op1 = change_address (op1, VOIDmode, addr1);
c7453384 4365
bbbbb16a
ILT		 4366 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4367 OPTAB_DIRECT);
a41c6c53
UW		 4368 if (temp != count)
4369 emit_move_insn (count, temp);
4370
bbbbb16a
ILT		 4371 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4372 OPTAB_DIRECT);
a41c6c53
UW		 4373 if (temp != blocks)
4374 emit_move_insn (blocks, temp);
4375
6de9cd9a
DN		 4376 emit_cmp_and_jump_insns (blocks, const0_rtx,
4377 EQ, NULL_RTX, mode, 1, loop_end_label);
70315fcd
SB		 4378
4379 emit_label (loop_start_label);
a41c6c53 4380
adfa3cd3
AK		 4381 if (TARGET_Z10
4382 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4383 {
4384 rtx prefetch;
4385
4386 /* Issue a read prefetch for the +2 cache line of operand 1. */
4387 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4388 const0_rtx, const0_rtx);
4389 emit_insn (prefetch);
4390 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4391
4392 /* Issue a read prefetch for the +2 cache line of operand 2. */
4393 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4394 const0_rtx, const0_rtx);
4395 emit_insn (prefetch);
4396 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4397 }
4398
b9404c99 4399 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
5b022de5 4400 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
c7453384 4401 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
a41c6c53
UW		 4402 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4403 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4404 emit_jump_insn (temp);
4405
c7453384 4406 s390_load_address (addr0,
a41c6c53 4407 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
c7453384 4408 s390_load_address (addr1,
a41c6c53 4409 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
c7453384 4410
bbbbb16a
ILT		 4411 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4412 OPTAB_DIRECT);
a41c6c53
UW		 4413 if (temp != blocks)
4414 emit_move_insn (blocks, temp);
4415
6de9cd9a
DN		 4416 emit_cmp_and_jump_insns (blocks, const0_rtx,
4417 EQ, NULL_RTX, mode, 1, loop_end_label);
70315fcd
SB		 4418
4419 emit_jump (loop_start_label);
6de9cd9a 4420 emit_label (loop_end_label);
a41c6c53 4421
38899e29 4422 emit_insn (gen_cmpmem_short (op0, op1,
b9404c99 4423 convert_to_mode (Pmode, count, 1)));
a41c6c53
UW		 4424 emit_label (end_label);
4425
02887425 4426 emit_insn (gen_cmpint (target, ccreg));
a41c6c53 4427 }
367d32f3 4428 return true;
a41c6c53
UW		 4429}
4430
5d880bd2
UW		 4431
4432/* Expand conditional increment or decrement using alc/slb instructions.
4433 Should generate code setting DST to either SRC or SRC + INCREMENT,
4434 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
00bda920
AK		 4435 Returns true if successful, false otherwise.
4436
4437 That makes it possible to implement some if-constructs without jumps e.g.:
4438 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4439 unsigned int a, b, c;
4440 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4441 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4442 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4443 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4444
4445 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4446 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4447 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4448 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4449 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
5d880bd2
UW		 4450
4451bool
4452s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4453 rtx dst, rtx src, rtx increment)
4454{
ef4bddc2
RS		 4455 machine_mode cmp_mode;
4456 machine_mode cc_mode;
5d880bd2
UW		 4457 rtx op_res;
4458 rtx insn;
4459 rtvec p;
8d933e31 4460 int ret;
5d880bd2
UW		 4461
4462 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4463 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4464 cmp_mode = SImode;
4465 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4466 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4467 cmp_mode = DImode;
4468 else
4469 return false;
4470
4471 /* Try ADD LOGICAL WITH CARRY. */
4472 if (increment == const1_rtx)
4473 {
4474 /* Determine CC mode to use. */
4475 if (cmp_code == EQ || cmp_code == NE)
4476 {
4477 if (cmp_op1 != const0_rtx)
4478 {
4479 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4480 NULL_RTX, 0, OPTAB_WIDEN);
4481 cmp_op1 = const0_rtx;
4482 }
4483
4484 cmp_code = cmp_code == EQ ? LEU : GTU;
4485 }
4486
4487 if (cmp_code == LTU || cmp_code == LEU)
4488 {
4489 rtx tem = cmp_op0;
4490 cmp_op0 = cmp_op1;
4491 cmp_op1 = tem;
4492 cmp_code = swap_condition (cmp_code);
4493 }
4494
4495 switch (cmp_code)
4496 {
4497 case GTU:
4498 cc_mode = CCUmode;
4499 break;
4500
4501 case GEU:
4502 cc_mode = CCL3mode;
4503 break;
4504
4505 default:
4506 return false;
4507 }
4508
4509 /* Emit comparison instruction pattern. */
4510 if (!register_operand (cmp_op0, cmp_mode))
4511 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4512
4513 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4514 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4515 /* We use insn_invalid_p here to add clobbers if required. */
57ac4c34 4516 ret = insn_invalid_p (emit_insn (insn), false);
8d933e31 4517 gcc_assert (!ret);
5d880bd2
UW		 4518
4519 /* Emit ALC instruction pattern. */
4520 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4521 gen_rtx_REG (cc_mode, CC_REGNUM),
4522 const0_rtx);
4523
4524 if (src != const0_rtx)
4525 {
4526 if (!register_operand (src, GET_MODE (dst)))
4527 src = force_reg (GET_MODE (dst), src);
4528
a94a76a7
UW		 4529 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4530 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
5d880bd2
UW		 4531 }
4532
4533 p = rtvec_alloc (2);
f4aa3848 4534 RTVEC_ELT (p, 0) =
5d880bd2 4535 gen_rtx_SET (VOIDmode, dst, op_res);
f4aa3848 4536 RTVEC_ELT (p, 1) =
5d880bd2
UW		 4537 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4538 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4539
4540 return true;
4541 }
4542
4543 /* Try SUBTRACT LOGICAL WITH BORROW. */
4544 if (increment == constm1_rtx)
4545 {
4546 /* Determine CC mode to use. */
4547 if (cmp_code == EQ || cmp_code == NE)
4548 {
4549 if (cmp_op1 != const0_rtx)
4550 {
4551 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4552 NULL_RTX, 0, OPTAB_WIDEN);
4553 cmp_op1 = const0_rtx;
4554 }
4555
4556 cmp_code = cmp_code == EQ ? LEU : GTU;
4557 }
4558
4559 if (cmp_code == GTU || cmp_code == GEU)
4560 {
4561 rtx tem = cmp_op0;
4562 cmp_op0 = cmp_op1;
4563 cmp_op1 = tem;
4564 cmp_code = swap_condition (cmp_code);
4565 }
4566
4567 switch (cmp_code)
4568 {
4569 case LEU:
4570 cc_mode = CCUmode;
4571 break;
4572
4573 case LTU:
4574 cc_mode = CCL3mode;
4575 break;
4576
4577 default:
4578 return false;
4579 }
4580
4581 /* Emit comparison instruction pattern. */
4582 if (!register_operand (cmp_op0, cmp_mode))
4583 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4584
4585 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4586 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4587 /* We use insn_invalid_p here to add clobbers if required. */
57ac4c34 4588 ret = insn_invalid_p (emit_insn (insn), false);
8d933e31 4589 gcc_assert (!ret);
5d880bd2
UW		 4590
4591 /* Emit SLB instruction pattern. */
4592 if (!register_operand (src, GET_MODE (dst)))
4593 src = force_reg (GET_MODE (dst), src);
4594
f4aa3848
AK		 4595 op_res = gen_rtx_MINUS (GET_MODE (dst),
4596 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4597 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4598 gen_rtx_REG (cc_mode, CC_REGNUM),
5d880bd2
UW		 4599 const0_rtx));
4600 p = rtvec_alloc (2);
f4aa3848 4601 RTVEC_ELT (p, 0) =
5d880bd2 4602 gen_rtx_SET (VOIDmode, dst, op_res);
f4aa3848 4603 RTVEC_ELT (p, 1) =
5d880bd2
UW		 4604 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4605 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4606
4607 return true;
4608 }
4609
4610 return false;
4611}
4612
963fc8d0 4613/* Expand code for the insv template. Return true if successful. */
6fa05db6 4614
963fc8d0 4615bool
6fa05db6
AS		 4616s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4617{
4618 int bitsize = INTVAL (op1);
4619 int bitpos = INTVAL (op2);
ef4bddc2
RS		 4620 machine_mode mode = GET_MODE (dest);
4621 machine_mode smode;
78ce265b
RH		 4622 int smode_bsize, mode_bsize;
4623 rtx op, clobber;
6fa05db6 4624
a9d46e32 4625 if (bitsize + bitpos > GET_MODE_BITSIZE (mode))
03ed99a8
AK		 4626 return false;
4627
78ce265b
RH		 4628 /* Generate INSERT IMMEDIATE (IILL et al). */
4629 /* (set (ze (reg)) (const_int)). */
4630 if (TARGET_ZARCH
4631 && register_operand (dest, word_mode)
4632 && (bitpos % 16) == 0
4633 && (bitsize % 16) == 0
4634 && const_int_operand (src, VOIDmode))
963fc8d0 4635 {
78ce265b
RH		 4636 HOST_WIDE_INT val = INTVAL (src);
4637 int regpos = bitpos + bitsize;
963fc8d0 4638
78ce265b
RH		 4639 while (regpos > bitpos)
4640 {
ef4bddc2 4641 machine_mode putmode;
78ce265b
RH		 4642 int putsize;
4643
4644 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4645 putmode = SImode;
4646 else
4647 putmode = HImode;
963fc8d0 4648
78ce265b
RH		 4649 putsize = GET_MODE_BITSIZE (putmode);
4650 regpos -= putsize;
4651 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4652 GEN_INT (putsize),
4653 GEN_INT (regpos)),
4654 gen_int_mode (val, putmode));
4655 val >>= putsize;
4656 }
4657 gcc_assert (regpos == bitpos);
963fc8d0
AK		 4658 return true;
4659 }
4660
78ce265b
RH		 4661 smode = smallest_mode_for_size (bitsize, MODE_INT);
4662 smode_bsize = GET_MODE_BITSIZE (smode);
4663 mode_bsize = GET_MODE_BITSIZE (mode);
6fa05db6 4664
78ce265b 4665 /* Generate STORE CHARACTERS UNDER MASK (STCM et al). */
6fa05db6 4666 if (bitpos == 0
78ce265b
RH		 4667 && (bitsize % BITS_PER_UNIT) == 0
4668 && MEM_P (dest)
6fa05db6
AS		 4669 && (register_operand (src, word_mode)
4670 || const_int_operand (src, VOIDmode)))
4671 {
4672 /* Emit standard pattern if possible. */
78ce265b
RH		 4673 if (smode_bsize == bitsize)
4674 {
4675 emit_move_insn (adjust_address (dest, smode, 0),
4676 gen_lowpart (smode, src));
4677 return true;
4678 }
6fa05db6
AS		 4679
4680 /* (set (ze (mem)) (const_int)). */
4681 else if (const_int_operand (src, VOIDmode))
4682 {
4683 int size = bitsize / BITS_PER_UNIT;
78ce265b
RH		 4684 rtx src_mem = adjust_address (force_const_mem (word_mode, src),
4685 BLKmode,
4686 UNITS_PER_WORD - size);
6fa05db6
AS		 4687
4688 dest = adjust_address (dest, BLKmode, 0);
f5541398 4689 set_mem_size (dest, size);
6fa05db6 4690 s390_expand_movmem (dest, src_mem, GEN_INT (size));
78ce265b 4691 return true;
6fa05db6 4692 }
f4aa3848 4693
6fa05db6
AS		 4694 /* (set (ze (mem)) (reg)). */
4695 else if (register_operand (src, word_mode))
4696 {
78ce265b 4697 if (bitsize <= 32)
6fa05db6
AS		 4698 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4699 const0_rtx), src);
4700 else
4701 {
4702 /* Emit st,stcmh sequence. */
78ce265b 4703 int stcmh_width = bitsize - 32;
6fa05db6
AS		 4704 int size = stcmh_width / BITS_PER_UNIT;
4705
f4aa3848 4706 emit_move_insn (adjust_address (dest, SImode, size),
6fa05db6 4707 gen_lowpart (SImode, src));
f5541398 4708 set_mem_size (dest, size);
78ce265b
RH		 4709 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4710 GEN_INT (stcmh_width),
4711 const0_rtx),
4712 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT (32)));
6fa05db6 4713 }
78ce265b 4714 return true;
6fa05db6 4715 }
78ce265b 4716 }
6fa05db6 4717
78ce265b
RH		 4718 /* Generate INSERT CHARACTERS UNDER MASK (IC, ICM et al). */
4719 if ((bitpos % BITS_PER_UNIT) == 0
4720 && (bitsize % BITS_PER_UNIT) == 0
4721 && (bitpos & 32) == ((bitpos + bitsize - 1) & 32)
4722 && MEM_P (src)
4723 && (mode == DImode || mode == SImode)
4724 && register_operand (dest, mode))
4725 {
4726 /* Emit a strict_low_part pattern if possible. */
4727 if (smode_bsize == bitsize && bitpos == mode_bsize - smode_bsize)
4728 {
4729 op = gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (smode, dest));
4730 op = gen_rtx_SET (VOIDmode, op, gen_lowpart (smode, src));
4731 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4732 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4733 return true;
4734 }
4735
4736 /* ??? There are more powerful versions of ICM that are not
4737 completely represented in the md file. */
6fa05db6
AS		 4738 }
4739
78ce265b
RH		 4740 /* For z10, generate ROTATE THEN INSERT SELECTED BITS (RISBG et al). */
4741 if (TARGET_Z10 && (mode == DImode || mode == SImode))
6fa05db6 4742 {
ef4bddc2 4743 machine_mode mode_s = GET_MODE (src);
6fa05db6 4744
78ce265b 4745 if (mode_s == VOIDmode)
6fa05db6 4746 {
78ce265b
RH		 4747 /* Assume const_int etc already in the proper mode. */
4748 src = force_reg (mode, src);
4749 }
4750 else if (mode_s != mode)
4751 {
4752 gcc_assert (GET_MODE_BITSIZE (mode_s) >= bitsize);
4753 src = force_reg (mode_s, src);
4754 src = gen_lowpart (mode, src);
4755 }
6fa05db6 4756
0d8e4dac
RH		 4757 op = gen_rtx_ZERO_EXTRACT (mode, dest, op1, op2),
4758 op = gen_rtx_SET (VOIDmode, op, src);
22ac2c2f
AK		 4759
4760 if (!TARGET_ZEC12)
4761 {
4762 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4763 op = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber));
4764 }
4765 emit_insn (op);
6fa05db6 4766
6fa05db6
AS		 4767 return true;
4768 }
4769
4770 return false;
4771}
5d880bd2 4772
45d18331
AS		 4773/* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4774 register that holds VAL of mode MODE shifted by COUNT bits. */
3093f076
AS		 4775
4776static inline rtx
ef4bddc2 4777s390_expand_mask_and_shift (rtx val, machine_mode mode, rtx count)
3093f076
AS		 4778{
4779 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4780 NULL_RTX, 1, OPTAB_DIRECT);
f4aa3848 4781 return expand_simple_binop (SImode, ASHIFT, val, count,
3093f076
AS		 4782 NULL_RTX, 1, OPTAB_DIRECT);
4783}
4784
4785/* Structure to hold the initial parameters for a compare_and_swap operation
f4aa3848 4786 in HImode and QImode. */
3093f076
AS		 4787
4788struct alignment_context
4789{
f4aa3848 4790 rtx memsi; /* SI aligned memory location. */
3093f076
AS		 4791 rtx shift; /* Bit offset with regard to lsb. */
4792 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4793 rtx modemaski; /* ~modemask */
6416ae7f 4794 bool aligned; /* True if memory is aligned, false else. */
3093f076
AS		 4795};
4796
45d18331
AS		 4797/* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4798 structure AC for transparent simplifying, if the memory alignment is known
4799 to be at least 32bit. MEM is the memory location for the actual operation
4800 and MODE its mode. */
3093f076
AS		 4801
4802static void
4803init_alignment_context (struct alignment_context *ac, rtx mem,
ef4bddc2 4804 machine_mode mode)
3093f076
AS		 4805{
4806 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4807 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4808
4809 if (ac->aligned)
4810 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4811 else
4812 {
4813 /* Alignment is unknown. */
4814 rtx byteoffset, addr, align;
4815
4816 /* Force the address into a register. */
4817 addr = force_reg (Pmode, XEXP (mem, 0));
4818
4819 /* Align it to SImode. */
4820 align = expand_simple_binop (Pmode, AND, addr,
4821 GEN_INT (-GET_MODE_SIZE (SImode)),
4822 NULL_RTX, 1, OPTAB_DIRECT);
4823 /* Generate MEM. */
4824 ac->memsi = gen_rtx_MEM (SImode, align);
4825 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
44d64274 4826 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
3093f076
AS		 4827 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4828
4829 /* Calculate shiftcount. */
4830 byteoffset = expand_simple_binop (Pmode, AND, addr,
4831 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4832 NULL_RTX, 1, OPTAB_DIRECT);
4833 /* As we already have some offset, evaluate the remaining distance. */
4834 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4835 NULL_RTX, 1, OPTAB_DIRECT);
3093f076 4836 }
78ce265b 4837
3093f076 4838 /* Shift is the byte count, but we need the bitcount. */
78ce265b
RH		 4839 ac->shift = expand_simple_binop (SImode, ASHIFT, ac->shift, GEN_INT (3),
4840 NULL_RTX, 1, OPTAB_DIRECT);
4841
3093f076 4842 /* Calculate masks. */
f4aa3848 4843 ac->modemask = expand_simple_binop (SImode, ASHIFT,
78ce265b
RH		 4844 GEN_INT (GET_MODE_MASK (mode)),
4845 ac->shift, NULL_RTX, 1, OPTAB_DIRECT);
4846 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask,
4847 NULL_RTX, 1);
4848}
4849
4850/* A subroutine of s390_expand_cs_hqi. Insert INS into VAL. If possible,
4851 use a single insv insn into SEQ2. Otherwise, put prep insns in SEQ1 and
4852 perform the merge in SEQ2. */
4853
4854static rtx
4855s390_two_part_insv (struct alignment_context *ac, rtx *seq1, rtx *seq2,
ef4bddc2 4856 machine_mode mode, rtx val, rtx ins)
78ce265b
RH		 4857{
4858 rtx tmp;
4859
4860 if (ac->aligned)
4861 {
4862 start_sequence ();
4863 tmp = copy_to_mode_reg (SImode, val);
4864 if (s390_expand_insv (tmp, GEN_INT (GET_MODE_BITSIZE (mode)),
4865 const0_rtx, ins))
4866 {
4867 *seq1 = NULL;
4868 *seq2 = get_insns ();
4869 end_sequence ();
4870 return tmp;
4871 }
4872 end_sequence ();
4873 }
4874
4875 /* Failed to use insv. Generate a two part shift and mask. */
4876 start_sequence ();
4877 tmp = s390_expand_mask_and_shift (ins, mode, ac->shift);
4878 *seq1 = get_insns ();
4879 end_sequence ();
4880
4881 start_sequence ();
4882 tmp = expand_simple_binop (SImode, IOR, tmp, val, NULL_RTX, 1, OPTAB_DIRECT);
4883 *seq2 = get_insns ();
4884 end_sequence ();
4885
4886 return tmp;
3093f076
AS		 4887}
4888
4889/* Expand an atomic compare and swap operation for HImode and QImode. MEM is
78ce265b
RH		 4890 the memory location, CMP the old value to compare MEM with and NEW_RTX the
4891 value to set if CMP == MEM. */
3093f076
AS		 4892
4893void
ef4bddc2 4894s390_expand_cs_hqi (machine_mode mode, rtx btarget, rtx vtarget, rtx mem,
78ce265b 4895 rtx cmp, rtx new_rtx, bool is_weak)
3093f076
AS		 4896{
4897 struct alignment_context ac;
4e1ffb63 4898 rtx cmpv, newv, val, cc, seq0, seq1, seq2, seq3;
3093f076 4899 rtx res = gen_reg_rtx (SImode);
19f8b229 4900 rtx_code_label *csloop = NULL, *csend = NULL;
3093f076 4901
3093f076
AS		 4902 gcc_assert (MEM_P (mem));
4903
4904 init_alignment_context (&ac, mem, mode);
4905
3093f076
AS		 4906 /* Load full word. Subsequent loads are performed by CS. */
4907 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4908 NULL_RTX, 1, OPTAB_DIRECT);
4909
78ce265b
RH		 4910 /* Prepare insertions of cmp and new_rtx into the loaded value. When
4911 possible, we try to use insv to make this happen efficiently. If
4912 that fails we'll generate code both inside and outside the loop. */
4913 cmpv = s390_two_part_insv (&ac, &seq0, &seq2, mode, val, cmp);
4914 newv = s390_two_part_insv (&ac, &seq1, &seq3, mode, val, new_rtx);
4915
4916 if (seq0)
4917 emit_insn (seq0);
4918 if (seq1)
4919 emit_insn (seq1);
4920
3093f076 4921 /* Start CS loop. */
78ce265b
RH		 4922 if (!is_weak)
4923 {
4924 /* Begin assuming success. */
4925 emit_move_insn (btarget, const1_rtx);
4926
4927 csloop = gen_label_rtx ();
4928 csend = gen_label_rtx ();
4929 emit_label (csloop);
4930 }
4931
f4aa3848 4932 /* val = "<mem>00..0<mem>"
3093f076 4933 * cmp = "00..0<cmp>00..0"
f4aa3848 4934 * new = "00..0<new>00..0"
3093f076
AS		 4935 */
4936
78ce265b
RH		 4937 emit_insn (seq2);
4938 emit_insn (seq3);
4939
4940 cc = s390_emit_compare_and_swap (EQ, res, ac.memsi, cmpv, newv);
4941 if (is_weak)
4942 emit_insn (gen_cstorecc4 (btarget, cc, XEXP (cc, 0), XEXP (cc, 1)));
3093f076 4943 else
3093f076 4944 {
4e1ffb63
RH		 4945 rtx tmp;
4946
78ce265b
RH		 4947 /* Jump to end if we're done (likely?). */
4948 s390_emit_jump (csend, cc);
4949
4e1ffb63
RH		 4950 /* Check for changes outside mode, and loop internal if so.
4951 Arrange the moves so that the compare is adjacent to the
4952 branch so that we can generate CRJ. */
4953 tmp = copy_to_reg (val);
4954 force_expand_binop (SImode, and_optab, res, ac.modemaski, val,
4955 1, OPTAB_DIRECT);
4956 cc = s390_emit_compare (NE, val, tmp);
78ce265b
RH		 4957 s390_emit_jump (csloop, cc);
4958
4959 /* Failed. */
4960 emit_move_insn (btarget, const0_rtx);
4961 emit_label (csend);
3093f076 4962 }
f4aa3848 4963
3093f076 4964 /* Return the correct part of the bitfield. */
78ce265b
RH		 4965 convert_move (vtarget, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4966 NULL_RTX, 1, OPTAB_DIRECT), 1);
3093f076
AS		 4967}
4968
45d18331 4969/* Expand an atomic operation CODE of mode MODE. MEM is the memory location
ea2c620c 4970 and VAL the value to play with. If AFTER is true then store the value
45d18331
AS		 4971 MEM holds after the operation, if AFTER is false then store the value MEM
4972 holds before the operation. If TARGET is zero then discard that value, else
4973 store it to TARGET. */
4974
4975void
ef4bddc2 4976s390_expand_atomic (machine_mode mode, enum rtx_code code,
45d18331
AS		 4977 rtx target, rtx mem, rtx val, bool after)
4978{
4979 struct alignment_context ac;
4980 rtx cmp;
0a2aaacc 4981 rtx new_rtx = gen_reg_rtx (SImode);
45d18331 4982 rtx orig = gen_reg_rtx (SImode);
19f8b229 4983 rtx_code_label *csloop = gen_label_rtx ();
45d18331
AS		 4984
4985 gcc_assert (!target || register_operand (target, VOIDmode));
4986 gcc_assert (MEM_P (mem));
4987
4988 init_alignment_context (&ac, mem, mode);
4989
4990 /* Shift val to the correct bit positions.
4991 Preserve "icm", but prevent "ex icm". */
4992 if (!(ac.aligned && code == SET && MEM_P (val)))
4993 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4994
4995 /* Further preparation insns. */
4996 if (code == PLUS || code == MINUS)
4997 emit_move_insn (orig, val);
4998 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4999 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
5000 NULL_RTX, 1, OPTAB_DIRECT);
5001
5002 /* Load full word. Subsequent loads are performed by CS. */
5003 cmp = force_reg (SImode, ac.memsi);
5004
5005 /* Start CS loop. */
5006 emit_label (csloop);
0a2aaacc 5007 emit_move_insn (new_rtx, cmp);
45d18331
AS		 5008
5009 /* Patch new with val at correct position. */
5010 switch (code)
5011 {
5012 case PLUS:
5013 case MINUS:
0a2aaacc 5014 val = expand_simple_binop (SImode, code, new_rtx, orig,
45d18331
AS		 5015 NULL_RTX, 1, OPTAB_DIRECT);
5016 val = expand_simple_binop (SImode, AND, val, ac.modemask,
5017 NULL_RTX, 1, OPTAB_DIRECT);
5018 /* FALLTHRU */
f4aa3848 5019 case SET:
45d18331 5020 if (ac.aligned && MEM_P (val))
44e95206
AH		 5021 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0,
5022 0, 0, SImode, val);
45d18331
AS		 5023 else
5024 {
0a2aaacc 5025 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
45d18331 5026 NULL_RTX, 1, OPTAB_DIRECT);
0a2aaacc 5027 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
45d18331
AS		 5028 NULL_RTX, 1, OPTAB_DIRECT);
5029 }
5030 break;
5031 case AND:
5032 case IOR:
5033 case XOR:
0a2aaacc 5034 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
45d18331
AS		 5035 NULL_RTX, 1, OPTAB_DIRECT);
5036 break;
5037 case MULT: /* NAND */
0a2aaacc 5038 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
45d18331 5039 NULL_RTX, 1, OPTAB_DIRECT);
6a238c58
AK		 5040 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
5041 NULL_RTX, 1, OPTAB_DIRECT);
45d18331
AS		 5042 break;
5043 default:
5044 gcc_unreachable ();
5045 }
45d18331 5046
8bb501bb 5047 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
0a2aaacc 5048 ac.memsi, cmp, new_rtx));
45d18331
AS		 5049
5050 /* Return the correct part of the bitfield. */
5051 if (target)
5052 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
0a2aaacc 5053 after ? new_rtx : cmp, ac.shift,
45d18331
AS		 5054 NULL_RTX, 1, OPTAB_DIRECT), 1);
5055}
5056
fdbe66f2 5057/* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
6b2300b3
JJ		 5058 We need to emit DTP-relative relocations. */
5059
fdbe66f2
EB		 5060static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
5061
5062static void
9c808aad 5063s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
6b2300b3
JJ		 5064{
5065 switch (size)
5066 {
5067 case 4:
5068 fputs ("\t.long\t", file);
5069 break;
5070 case 8:
5071 fputs ("\t.quad\t", file);
5072 break;
5073 default:
8d933e31 5074 gcc_unreachable ();
6b2300b3
JJ		 5075 }
5076 output_addr_const (file, x);
5077 fputs ("@DTPOFF", file);
5078}
5079
7269aee7 5080#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
608063c3 5081/* Implement TARGET_MANGLE_TYPE. */
7269aee7
AH		 5082
5083static const char *
3101faab 5084s390_mangle_type (const_tree type)
7269aee7
AH		 5085{
5086 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
5087 && TARGET_LONG_DOUBLE_128)
5088 return "g";
5089
5090 /* For all other types, use normal C++ mangling. */
5091 return NULL;
5092}
5093#endif
5094
4c8c0dec 5095/* In the name of slightly smaller debug output, and to cater to
aabcd309 5096 general assembler lossage, recognize various UNSPEC sequences
4c8c0dec
JJ		 5097 and turn them back into a direct symbol reference. */
5098
69bd9368 5099static rtx
9c808aad 5100s390_delegitimize_address (rtx orig_x)
4c8c0dec 5101{
e8d8f497 5102 rtx x, y;
4c8c0dec 5103
e8d8f497
JJ		 5104 orig_x = delegitimize_mem_from_attrs (orig_x);
5105 x = orig_x;
e101e12e
AK		 5106
5107 /* Extract the symbol ref from:
5108 (plus:SI (reg:SI 12 %r12)
5109 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
01841ac0
AK		 5110 UNSPEC_GOTOFF/PLTOFF)))
5111 and
5112 (plus:SI (reg:SI 12 %r12)
5113 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
5114 UNSPEC_GOTOFF/PLTOFF)
5115 (const_int 4 [0x4])))) */
e101e12e
AK		 5116 if (GET_CODE (x) == PLUS
5117 && REG_P (XEXP (x, 0))
5118 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
5119 && GET_CODE (XEXP (x, 1)) == CONST)
5120 {
ab081dd6
AK		 5121 HOST_WIDE_INT offset = 0;
5122
e101e12e
AK		 5123 /* The const operand. */
5124 y = XEXP (XEXP (x, 1), 0);
01841ac0
AK		 5125
5126 if (GET_CODE (y) == PLUS
5127 && GET_CODE (XEXP (y, 1)) == CONST_INT)
ab081dd6
AK		 5128 {
5129 offset = INTVAL (XEXP (y, 1));
5130 y = XEXP (y, 0);
5131 }
01841ac0 5132
e101e12e 5133 if (GET_CODE (y) == UNSPEC
01841ac0
AK		 5134 && (XINT (y, 1) == UNSPEC_GOTOFF
5135 || XINT (y, 1) == UNSPEC_PLTOFF))
0a81f074 5136 return plus_constant (Pmode, XVECEXP (y, 0, 0), offset);
e101e12e
AK		 5137 }
5138
4c8c0dec
JJ		 5139 if (GET_CODE (x) != MEM)
5140 return orig_x;
5141
5142 x = XEXP (x, 0);
5143 if (GET_CODE (x) == PLUS
5144 && GET_CODE (XEXP (x, 1)) == CONST
5145 && GET_CODE (XEXP (x, 0)) == REG
5146 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
5147 {
5148 y = XEXP (XEXP (x, 1), 0);
5149 if (GET_CODE (y) == UNSPEC
fd7643fb 5150 && XINT (y, 1) == UNSPEC_GOT)
67a2f76d
JJ		 5151 y = XVECEXP (y, 0, 0);
5152 else
5153 return orig_x;
4c8c0dec 5154 }
67a2f76d 5155 else if (GET_CODE (x) == CONST)
4c8c0dec 5156 {
01841ac0
AK		 5157 /* Extract the symbol ref from:
5158 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
5159 UNSPEC_PLT/GOTENT))) */
5160
4c8c0dec
JJ		 5161 y = XEXP (x, 0);
5162 if (GET_CODE (y) == UNSPEC
01841ac0
AK		 5163 && (XINT (y, 1) == UNSPEC_GOTENT
5164 || XINT (y, 1) == UNSPEC_PLT))
67a2f76d
JJ		 5165 y = XVECEXP (y, 0, 0);
5166 else
5167 return orig_x;
4c8c0dec 5168 }
67a2f76d
JJ		 5169 else
5170 return orig_x;
4c8c0dec 5171
67a2f76d
JJ		 5172 if (GET_MODE (orig_x) != Pmode)
5173 {
2f36e14b
JJ		 5174 if (GET_MODE (orig_x) == BLKmode)
5175 return orig_x;
67a2f76d
JJ		 5176 y = lowpart_subreg (GET_MODE (orig_x), y, Pmode);
5177 if (y == NULL_RTX)
5178 return orig_x;
5179 }
5180 return y;
4c8c0dec 5181}
ba956982 5182
6d057022
AS		 5183/* Output operand OP to stdio stream FILE.
5184 OP is an address (register + offset) which is not used to address data;
5185 instead the rightmost bits are interpreted as the value. */
ac32b25e
UW		 5186
5187static void
5188print_shift_count_operand (FILE *file, rtx op)
5189{
d98ad410
UW		 5190 HOST_WIDE_INT offset;
5191 rtx base;
f83a336d 5192
d98ad410 5193 /* Extract base register and offset. */
4989e88a 5194 if (!s390_decompose_shift_count (op, &base, &offset))
d98ad410 5195 gcc_unreachable ();
ac32b25e
UW		 5196
5197 /* Sanity check. */
d98ad410 5198 if (base)
8d933e31 5199 {
d98ad410
UW		 5200 gcc_assert (GET_CODE (base) == REG);
5201 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
5202 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
8d933e31 5203 }
ac32b25e 5204
6d057022
AS		 5205 /* Offsets are constricted to twelve bits. */
5206 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
d98ad410
UW		 5207 if (base)
5208 fprintf (file, "(%s)", reg_names[REGNO (base)]);
ac32b25e
UW		 5209}
5210
d0de9e13
DV		 5211/* Returns -1 if the function should not be made hotpatchable. Otherwise it
5212 returns a number >= 0 that is the desired size of the hotpatch trampoline
5213 in halfwords. */
5214
5215static int s390_function_num_hotpatch_trampoline_halfwords (tree decl,
5216 bool do_warn)
5217{
5218 tree attr;
5219
5220 if (DECL_DECLARED_INLINE_P (decl)
5221 || DECL_ARTIFICIAL (decl)
5222 || MAIN_NAME_P (DECL_NAME (decl)))
5223 {
5224 /* - Explicitly inlined functions cannot be hotpatched.
5225 - Artificial functions need not be hotpatched.
5226 - Making the main function hotpatchable is useless. */
5227 return -1;
5228 }
5229 attr = lookup_attribute ("hotpatch", DECL_ATTRIBUTES (decl));
5230 if (attr || s390_hotpatch_trampoline_halfwords >= 0)
5231 {
5232 if (lookup_attribute ("always_inline", DECL_ATTRIBUTES (decl)))
5233 {
5234 if (do_warn)
5235 warning (OPT_Wattributes, "function %qE with the %qs attribute"
5236 " is not hotpatchable", DECL_NAME (decl), "always_inline");
5237 return -1;
5238 }
5239 else
5240 {
5241 return (attr) ?
5242 get_hotpatch_attribute (attr) : s390_hotpatch_trampoline_halfwords;
5243 }
5244 }
5245
5246 return -1;
5247}
5248
5249/* Hook to determine if one function can safely inline another. */
5250
5251static bool
5252s390_can_inline_p (tree caller, tree callee)
5253{
5254 if (s390_function_num_hotpatch_trampoline_halfwords (callee, false) >= 0)
5255 return false;
5256
5257 return default_target_can_inline_p (caller, callee);
5258}
5259
5260/* Write the extra assembler code needed to declare a function properly. */
5261
5262void
5263s390_asm_output_function_label (FILE *asm_out_file, const char *fname,
5264 tree decl)
5265{
5266 int hotpatch_trampoline_halfwords = -1;
5267
5268 if (decl)
5269 {
5270 hotpatch_trampoline_halfwords =
5271 s390_function_num_hotpatch_trampoline_halfwords (decl, true);
5272 if (hotpatch_trampoline_halfwords >= 0
5273 && decl_function_context (decl) != NULL_TREE)
5274 {
e697d119
DV		 5275 warning_at (DECL_SOURCE_LOCATION (decl), OPT_mhotpatch,
5276 "hotpatching is not compatible with nested functions");
d0de9e13
DV		 5277 hotpatch_trampoline_halfwords = -1;
5278 }
5279 }
5280
5281 if (hotpatch_trampoline_halfwords > 0)
5282 {
5283 int i;
5284
5285 /* Add a trampoline code area before the function label and initialize it
5286 with two-byte nop instructions. This area can be overwritten with code
5287 that jumps to a patched version of the function. */
5288 for (i = 0; i < hotpatch_trampoline_halfwords; i++)
5289 asm_fprintf (asm_out_file, "\tnopr\t%%r7\n");
5290 /* Note: The function label must be aligned so that (a) the bytes of the
5291 following nop do not cross a cacheline boundary, and (b) a jump address
5292 (eight bytes for 64 bit targets, 4 bytes for 32 bit targets) can be
5293 stored directly before the label without crossing a cacheline
5294 boundary. All this is necessary to make sure the trampoline code can
5295 be changed atomically. */
5296 }
5297
5298 ASM_OUTPUT_LABEL (asm_out_file, fname);
5299
5300 /* Output a four-byte nop if hotpatching is enabled. This can be overwritten
5301 atomically with a relative backwards jump to the trampoline area. */
5302 if (hotpatch_trampoline_halfwords >= 0)
5303 asm_fprintf (asm_out_file, "\tnop\t0\n");
5304}
5305
38899e29 5306/* Output machine-dependent UNSPECs occurring in address constant X
faeb9bb6
UW		 5307 in assembler syntax to stdio stream FILE. Returns true if the
5308 constant X could be recognized, false otherwise. */
9db1d521 5309
0f8ab434 5310static bool
faeb9bb6 5311s390_output_addr_const_extra (FILE *file, rtx x)
9db1d521 5312{
faeb9bb6
UW		 5313 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
5314 switch (XINT (x, 1))
5315 {
5316 case UNSPEC_GOTENT:
5317 output_addr_const (file, XVECEXP (x, 0, 0));
5318 fprintf (file, "@GOTENT");
5319 return true;
5320 case UNSPEC_GOT:
5321 output_addr_const (file, XVECEXP (x, 0, 0));
5322 fprintf (file, "@GOT");
5323 return true;
5324 case UNSPEC_GOTOFF:
5325 output_addr_const (file, XVECEXP (x, 0, 0));
5326 fprintf (file, "@GOTOFF");
5327 return true;
5328 case UNSPEC_PLT:
5329 output_addr_const (file, XVECEXP (x, 0, 0));
5330 fprintf (file, "@PLT");
5331 return true;
5332 case UNSPEC_PLTOFF:
5333 output_addr_const (file, XVECEXP (x, 0, 0));
5334 fprintf (file, "@PLTOFF");
5335 return true;
5336 case UNSPEC_TLSGD:
5337 output_addr_const (file, XVECEXP (x, 0, 0));
5338 fprintf (file, "@TLSGD");
5339 return true;
5340 case UNSPEC_TLSLDM:
5341 assemble_name (file, get_some_local_dynamic_name ());
5342 fprintf (file, "@TLSLDM");
5343 return true;
5344 case UNSPEC_DTPOFF:
5345 output_addr_const (file, XVECEXP (x, 0, 0));
5346 fprintf (file, "@DTPOFF");
5347 return true;
5348 case UNSPEC_NTPOFF:
5349 output_addr_const (file, XVECEXP (x, 0, 0));
5350 fprintf (file, "@NTPOFF");
5351 return true;
5352 case UNSPEC_GOTNTPOFF:
5353 output_addr_const (file, XVECEXP (x, 0, 0));
5354 fprintf (file, "@GOTNTPOFF");
5355 return true;
5356 case UNSPEC_INDNTPOFF:
5357 output_addr_const (file, XVECEXP (x, 0, 0));
5358 fprintf (file, "@INDNTPOFF");
5359 return true;
5360 }
9db1d521 5361
dc66391d
RS		 5362 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5363 switch (XINT (x, 1))
5364 {
5365 case UNSPEC_POOL_OFFSET:
5366 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5367 output_addr_const (file, x);
5368 return true;
5369 }
faeb9bb6 5370 return false;
9db1d521
HP		 5371}
5372
c7453384 5373/* Output address operand ADDR in assembler syntax to
994fe660 5374 stdio stream FILE. */
9db1d521
HP		 5375
5376void
9c808aad 5377print_operand_address (FILE *file, rtx addr)
9db1d521
HP		 5378{
5379 struct s390_address ad;
5380
0ff4390d 5381 if (s390_loadrelative_operand_p (addr, NULL, NULL))
963fc8d0 5382 {
8395b41e
AK		 5383 if (!TARGET_Z10)
5384 {
3f3c098d
AK		 5385 output_operand_lossage ("symbolic memory references are "
5386 "only supported on z10 or later");
8395b41e
AK		 5387 return;
5388 }
963fc8d0
AK		 5389 output_addr_const (file, addr);
5390 return;
5391 }
5392
b808c04c 5393 if (!s390_decompose_address (addr, &ad)
93fa8428
AK		 5394 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5395 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
c85ce869 5396 output_operand_lossage ("cannot decompose address");
c7453384 5397
9db1d521 5398 if (ad.disp)
faeb9bb6 5399 output_addr_const (file, ad.disp);
9db1d521
HP		 5400 else
5401 fprintf (file, "0");
5402
5403 if (ad.base && ad.indx)
5404 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5405 reg_names[REGNO (ad.base)]);
5406 else if (ad.base)
5407 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5408}
5409
c7453384
EC		 5410/* Output operand X in assembler syntax to stdio stream FILE.
5411 CODE specified the format flag. The following format flags
994fe660
UW		 5412 are recognized:
5413
5414 'C': print opcode suffix for branch condition.
5415 'D': print opcode suffix for inverse branch condition.
f1149235 5416 'E': print opcode suffix for branch on index instruction.
7b8acc34 5417 'G': print the size of the operand in bytes.
75ca1b39
RH		 5418 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5419 'M': print the second word of a TImode operand.
5420 'N': print the second word of a DImode operand.
994fe660
UW		 5421 'O': print only the displacement of a memory reference.
5422 'R': print only the base register of a memory reference.
fc0ea003 5423 'S': print S-type memory reference (base+displacement).
ac32b25e 5424 'Y': print shift count operand.
994fe660 5425
5519a4f9 5426 'b': print integer X as if it's an unsigned byte.
963fc8d0 5427 'c': print integer X as if it's an signed byte.
75ca1b39
RH		 5428 'e': "end" of DImode contiguous bitmask X.
5429 'f': "end" of SImode contiguous bitmask X.
da48f5ec 5430 'h': print integer X as if it's a signed halfword.
f19a9af7 5431 'i': print the first nonzero HImode part of X.
da48f5ec
AK		 5432 'j': print the first HImode part unequal to -1 of X.
5433 'k': print the first nonzero SImode part of X.
5434 'm': print the first SImode part unequal to -1 of X.
75ca1b39
RH		 5435 'o': print integer X as if it's an unsigned 32bit word.
5436 's': "start" of DImode contiguous bitmask X.
5437 't': "start" of SImode contiguous bitmask X.
5438 'x': print integer X as if it's an unsigned halfword.
5439*/
9db1d521
HP		 5440
5441void
9c808aad 5442print_operand (FILE *file, rtx x, int code)
9db1d521 5443{
75ca1b39
RH		 5444 HOST_WIDE_INT ival;
5445
9db1d521
HP		 5446 switch (code)
5447 {
5448 case 'C':
ba956982 5449 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
9db1d521
HP		 5450 return;
5451
5452 case 'D':
ba956982 5453 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
9db1d521
HP		 5454 return;
5455
f1149235
AK		 5456 case 'E':
5457 if (GET_CODE (x) == LE)
5458 fprintf (file, "l");
5459 else if (GET_CODE (x) == GT)
5460 fprintf (file, "h");
5461 else
3f3c098d
AK		 5462 output_operand_lossage ("invalid comparison operator "
5463 "for 'E' output modifier");
f1149235
AK		 5464 return;
5465
fd3cd001
UW		 5466 case 'J':
5467 if (GET_CODE (x) == SYMBOL_REF)
5468 {
5469 fprintf (file, "%s", ":tls_load:");
5470 output_addr_const (file, x);
5471 }
5472 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5473 {
5474 fprintf (file, "%s", ":tls_gdcall:");
5475 output_addr_const (file, XVECEXP (x, 0, 0));
5476 }
5477 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5478 {
5479 fprintf (file, "%s", ":tls_ldcall:");
4fbca4ba
RS		 5480 const char *name = get_some_local_dynamic_name ();
5481 gcc_assert (name);
5482 assemble_name (file, name);
fd3cd001
UW		 5483 }
5484 else
3f3c098d 5485 output_operand_lossage ("invalid reference for 'J' output modifier");
fd3cd001
UW		 5486 return;
5487
7b8acc34
AK		 5488 case 'G':
5489 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5490 return;
5491
9db1d521
HP		 5492 case 'O':
5493 {
5494 struct s390_address ad;
8d933e31 5495 int ret;
9db1d521 5496
8395b41e
AK		 5497 if (!MEM_P (x))
5498 {
3f3c098d
AK		 5499 output_operand_lossage ("memory reference expected for "
5500 "'O' output modifier");
8395b41e
AK		 5501 return;
5502 }
5503
8d933e31 5504 ret = s390_decompose_address (XEXP (x, 0), &ad);
8395b41e
AK		 5505
5506 if (!ret
5507 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5508 || ad.indx)
5509 {
3f3c098d 5510 output_operand_lossage ("invalid address for 'O' output modifier");
8395b41e
AK		 5511 return;
5512 }
9db1d521
HP		 5513
5514 if (ad.disp)
faeb9bb6 5515 output_addr_const (file, ad.disp);
9db1d521
HP		 5516 else
5517 fprintf (file, "0");
5518 }
5519 return;
5520
5521 case 'R':
5522 {
5523 struct s390_address ad;
8d933e31 5524 int ret;
9db1d521 5525
8395b41e
AK		 5526 if (!MEM_P (x))
5527 {
3f3c098d
AK		 5528 output_operand_lossage ("memory reference expected for "
5529 "'R' output modifier");
8395b41e
AK		 5530 return;
5531 }
5532
8d933e31 5533 ret = s390_decompose_address (XEXP (x, 0), &ad);
8395b41e
AK		 5534
5535 if (!ret
5536 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5537 || ad.indx)
5538 {
3f3c098d 5539 output_operand_lossage ("invalid address for 'R' output modifier");
8395b41e
AK		 5540 return;
5541 }
9db1d521
HP		 5542
5543 if (ad.base)
5544 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5545 else
5546 fprintf (file, "0");
5547 }
5548 return;
5549
fc0ea003
UW		 5550 case 'S':
5551 {
5552 struct s390_address ad;
8d933e31 5553 int ret;
fc0ea003 5554
8395b41e
AK		 5555 if (!MEM_P (x))
5556 {
3f3c098d
AK		 5557 output_operand_lossage ("memory reference expected for "
5558 "'S' output modifier");
8395b41e
AK		 5559 return;
5560 }
8d933e31 5561 ret = s390_decompose_address (XEXP (x, 0), &ad);
8395b41e
AK		 5562
5563 if (!ret
5564 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5565 || ad.indx)
5566 {
3f3c098d 5567 output_operand_lossage ("invalid address for 'S' output modifier");
8395b41e
AK		 5568 return;
5569 }
fc0ea003
UW		 5570
5571 if (ad.disp)
5572 output_addr_const (file, ad.disp);
5573 else
5574 fprintf (file, "0");
5575
5576 if (ad.base)
5577 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5578 }
5579 return;
5580
9db1d521
HP		 5581 case 'N':
5582 if (GET_CODE (x) == REG)
5583 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5584 else if (GET_CODE (x) == MEM)
0a81f074
RS		 5585 x = change_address (x, VOIDmode,
5586 plus_constant (Pmode, XEXP (x, 0), 4));
9db1d521 5587 else
3f3c098d
AK		 5588 output_operand_lossage ("register or memory expression expected "
5589 "for 'N' output modifier");
9db1d521
HP		 5590 break;
5591
5592 case 'M':
5593 if (GET_CODE (x) == REG)
5594 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5595 else if (GET_CODE (x) == MEM)
0a81f074
RS		 5596 x = change_address (x, VOIDmode,
5597 plus_constant (Pmode, XEXP (x, 0), 8));
9db1d521 5598 else
3f3c098d
AK		 5599 output_operand_lossage ("register or memory expression expected "
5600 "for 'M' output modifier");
9db1d521 5601 break;
ac32b25e
UW		 5602
5603 case 'Y':
5604 print_shift_count_operand (file, x);
5605 return;
9db1d521
HP		 5606 }
5607
5608 switch (GET_CODE (x))
5609 {
5610 case REG:
5611 fprintf (file, "%s", reg_names[REGNO (x)]);
5612 break;
5613
5614 case MEM:
5615 output_address (XEXP (x, 0));
5616 break;
5617
5618 case CONST:
5619 case CODE_LABEL:
5620 case LABEL_REF:
5621 case SYMBOL_REF:
faeb9bb6 5622 output_addr_const (file, x);
9db1d521
HP		 5623 break;
5624
5625 case CONST_INT:
75ca1b39
RH		 5626 ival = INTVAL (x);
5627 switch (code)
5628 {
5629 case 0:
5630 break;
5631 case 'b':
5632 ival &= 0xff;
5633 break;
5634 case 'c':
5635 ival = ((ival & 0xff) ^ 0x80) - 0x80;
5636 break;
5637 case 'x':
5638 ival &= 0xffff;
5639 break;
5640 case 'h':
5641 ival = ((ival & 0xffff) ^ 0x8000) - 0x8000;
5642 break;
5643 case 'i':
5644 ival = s390_extract_part (x, HImode, 0);
5645 break;
5646 case 'j':
5647 ival = s390_extract_part (x, HImode, -1);
5648 break;
5649 case 'k':
5650 ival = s390_extract_part (x, SImode, 0);
5651 break;
5652 case 'm':
5653 ival = s390_extract_part (x, SImode, -1);
5654 break;
5655 case 'o':
5656 ival &= 0xffffffff;
5657 break;
5658 case 'e': case 'f':
5659 case 's': case 't':
5660 {
5661 int pos, len;
5662 bool ok;
5663
5664 len = (code == 's' || code == 'e' ? 64 : 32);
5665 ok = s390_contiguous_bitmask_p (ival, len, &pos, &len);
5666 gcc_assert (ok);
5667 if (code == 's' || code == 't')
5668 ival = 64 - pos - len;
5669 else
5670 ival = 64 - 1 - pos;
5671 }
5672 break;
5673 default:
5674 output_operand_lossage ("invalid constant for output modifier '%c'", code);
5675 }
5676 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
4023fb28
UW		 5677 break;
5678
5679 case CONST_DOUBLE:
8d933e31 5680 gcc_assert (GET_MODE (x) == VOIDmode);
4023fb28
UW		 5681 if (code == 'b')
5682 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
9db1d521 5683 else if (code == 'x')
4023fb28 5684 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
9db1d521 5685 else if (code == 'h')
3f3c098d
AK		 5686 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5687 ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
9db1d521 5688 else
8395b41e
AK		 5689 {
5690 if (code == 0)
3f3c098d
AK		 5691 output_operand_lossage ("invalid constant - try using "
5692 "an output modifier");
8395b41e 5693 else
3f3c098d
AK		 5694 output_operand_lossage ("invalid constant for output modifier '%c'",
5695 code);
8395b41e 5696 }
9db1d521
HP		 5697 break;
5698
5699 default:
8395b41e 5700 if (code == 0)
3f3c098d
AK		 5701 output_operand_lossage ("invalid expression - try using "
5702 "an output modifier");
8395b41e 5703 else
3f3c098d
AK		 5704 output_operand_lossage ("invalid expression for output "
5705 "modifier '%c'", code);
9db1d521
HP		 5706 break;
5707 }
5708}
5709
301d03af
RS		 5710/* Target hook for assembling integer objects. We need to define it
5711 here to work a round a bug in some versions of GAS, which couldn't
5712 handle values smaller than INT_MIN when printed in decimal. */
5713
5714static bool
9c808aad 5715s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
301d03af
RS		 5716{
5717 if (size == 8 && aligned_p
5718 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5719 {
4a0a75dd
KG		 5720 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5721 INTVAL (x));
301d03af
RS		 5722 return true;
5723 }
5724 return default_assemble_integer (x, size, aligned_p);
5725}
5726
c7453384 5727/* Returns true if register REGNO is used for forming
994fe660 5728 a memory address in expression X. */
9db1d521 5729
3ed99cc9 5730static bool
9c808aad 5731reg_used_in_mem_p (int regno, rtx x)
9db1d521
HP		 5732{
5733 enum rtx_code code = GET_CODE (x);
5734 int i, j;
5735 const char *fmt;
c7453384 5736
9db1d521
HP		 5737 if (code == MEM)
5738 {
5739 if (refers_to_regno_p (regno, regno+1,
5740 XEXP (x, 0), 0))
3ed99cc9 5741 return true;
9db1d521 5742 }
c7453384 5743 else if (code == SET
4023fb28
UW		 5744 && GET_CODE (SET_DEST (x)) == PC)
5745 {
5746 if (refers_to_regno_p (regno, regno+1,
5747 SET_SRC (x), 0))
3ed99cc9 5748 return true;
4023fb28 5749 }
9db1d521
HP		 5750
5751 fmt = GET_RTX_FORMAT (code);
5752 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5753 {
5754 if (fmt[i] == 'e'
5755 && reg_used_in_mem_p (regno, XEXP (x, i)))
3ed99cc9 5756 return true;
c7453384 5757
9db1d521
HP		 5758 else if (fmt[i] == 'E')
5759 for (j = 0; j < XVECLEN (x, i); j++)
5760 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
3ed99cc9 5761 return true;
9db1d521 5762 }
3ed99cc9 5763 return false;
9db1d521
HP		 5764}
5765
d65f7478 5766/* Returns true if expression DEP_RTX sets an address register
994fe660 5767 used by instruction INSN to address memory. */
9db1d521 5768
3ed99cc9 5769static bool
647d790d 5770addr_generation_dependency_p (rtx dep_rtx, rtx_insn *insn)
9db1d521 5771{
4023fb28 5772 rtx target, pat;
9db1d521 5773
b64925dc 5774 if (NONJUMP_INSN_P (dep_rtx))
34f0d87a 5775 dep_rtx = PATTERN (dep_rtx);
077dab3b 5776
9db1d521
HP		 5777 if (GET_CODE (dep_rtx) == SET)
5778 {
5779 target = SET_DEST (dep_rtx);
cc7ab9b7
UW		 5780 if (GET_CODE (target) == STRICT_LOW_PART)
5781 target = XEXP (target, 0);
5782 while (GET_CODE (target) == SUBREG)
5783 target = SUBREG_REG (target);
5784
9db1d521
HP		 5785 if (GET_CODE (target) == REG)
5786 {
5787 int regno = REGNO (target);
5788
077dab3b 5789 if (s390_safe_attr_type (insn) == TYPE_LA)
4023fb28
UW		 5790 {
5791 pat = PATTERN (insn);
5792 if (GET_CODE (pat) == PARALLEL)
5793 {
8d933e31 5794 gcc_assert (XVECLEN (pat, 0) == 2);
4023fb28
UW		 5795 pat = XVECEXP (pat, 0, 0);
5796 }
8d933e31
AS		 5797 gcc_assert (GET_CODE (pat) == SET);
5798 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
4023fb28 5799 }
077dab3b 5800 else if (get_attr_atype (insn) == ATYPE_AGEN)
4023fb28
UW		 5801 return reg_used_in_mem_p (regno, PATTERN (insn));
5802 }
9db1d521 5803 }
3ed99cc9 5804 return false;
9db1d521
HP		 5805}
5806
077dab3b
HP		 5807/* Return 1, if dep_insn sets register used in insn in the agen unit. */
5808
c7453384 5809int
647d790d 5810s390_agen_dep_p (rtx_insn *dep_insn, rtx_insn *insn)
c7453384 5811{
077dab3b
HP		 5812 rtx dep_rtx = PATTERN (dep_insn);
5813 int i;
c7453384
EC		 5814
5815 if (GET_CODE (dep_rtx) == SET
077dab3b
HP		 5816 && addr_generation_dependency_p (dep_rtx, insn))
5817 return 1;
5818 else if (GET_CODE (dep_rtx) == PARALLEL)
5819 {
5820 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5821 {
5822 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5823 return 1;
5824 }
5825 }
5826 return 0;
5827}
5828
9381e3f1 5829
52609473
HP		 5830/* A C statement (sans semicolon) to update the integer scheduling priority
5831 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5832 reduce the priority to execute INSN later. Do not define this macro if
c7453384 5833 you do not need to adjust the scheduling priorities of insns.
52609473 5834
c7453384 5835 A STD instruction should be scheduled earlier,
52609473 5836 in order to use the bypass. */
52609473 5837static int
ac44248e 5838s390_adjust_priority (rtx_insn *insn, int priority)
52609473
HP		 5839{
5840 if (! INSN_P (insn))
5841 return priority;
5842
ec24698e 5843 if (s390_tune != PROCESSOR_2084_Z990
2cdece44 5844 && s390_tune != PROCESSOR_2094_Z9_109
65b1d8ea 5845 && s390_tune != PROCESSOR_2097_Z10
22ac2c2f
AK		 5846 && s390_tune != PROCESSOR_2817_Z196
5847 && s390_tune != PROCESSOR_2827_ZEC12)
52609473
HP		 5848 return priority;
5849
5850 switch (s390_safe_attr_type (insn))
5851 {
cfdb984b
AS		 5852 case TYPE_FSTOREDF:
5853 case TYPE_FSTORESF:
52609473
HP		 5854 priority = priority << 3;
5855 break;
5856 case TYPE_STORE:
ea77e738 5857 case TYPE_STM:
52609473
HP		 5858 priority = priority << 1;
5859 break;
5860 default:
5861 break;
5862 }
5863 return priority;
5864}
f2d3c02a 5865
2cdece44 5866
077dab3b 5867/* The number of instructions that can be issued per cycle. */
f2d3c02a 5868
077dab3b 5869static int
9c808aad 5870s390_issue_rate (void)
077dab3b 5871{
93538e8e
AK		 5872 switch (s390_tune)
5873 {
5874 case PROCESSOR_2084_Z990:
5875 case PROCESSOR_2094_Z9_109:
65b1d8ea 5876 case PROCESSOR_2817_Z196:
93538e8e
AK		 5877 return 3;
5878 case PROCESSOR_2097_Z10:
22ac2c2f 5879 case PROCESSOR_2827_ZEC12:
93538e8e
AK		 5880 return 2;
5881 default:
5882 return 1;
5883 }
077dab3b 5884}
f2d3c02a 5885
52609473 5886static int
9c808aad 5887s390_first_cycle_multipass_dfa_lookahead (void)
52609473 5888{
64e1e4c4 5889 return 4;
52609473
HP		 5890}
5891
585539a1
UW		 5892/* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5893 Fix up MEMs as required. */
5894
5895static void
5896annotate_constant_pool_refs (rtx *x)
5897{
5898 int i, j;
5899 const char *fmt;
5900
8d933e31
AS		 5901 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5902 || !CONSTANT_POOL_ADDRESS_P (*x));
585539a1
UW		 5903
5904 /* Literal pool references can only occur inside a MEM ... */
5905 if (GET_CODE (*x) == MEM)
5906 {
5907 rtx memref = XEXP (*x, 0);
5908
5909 if (GET_CODE (memref) == SYMBOL_REF
5910 && CONSTANT_POOL_ADDRESS_P (memref))
5911 {
5912 rtx base = cfun->machine->base_reg;
5913 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5914 UNSPEC_LTREF);
5915
5916 *x = replace_equiv_address (*x, addr);
5917 return;
5918 }
5919
5920 if (GET_CODE (memref) == CONST
5921 && GET_CODE (XEXP (memref, 0)) == PLUS
5922 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5923 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5924 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5925 {
5926 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5927 rtx sym = XEXP (XEXP (memref, 0), 0);
5928 rtx base = cfun->machine->base_reg;
5929 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5930 UNSPEC_LTREF);
5931
0a81f074 5932 *x = replace_equiv_address (*x, plus_constant (Pmode, addr, off));
585539a1
UW		 5933 return;
5934 }
5935 }
5936
5937 /* ... or a load-address type pattern. */
5938 if (GET_CODE (*x) == SET)
5939 {
5940 rtx addrref = SET_SRC (*x);
5941
5942 if (GET_CODE (addrref) == SYMBOL_REF
5943 && CONSTANT_POOL_ADDRESS_P (addrref))
5944 {
5945 rtx base = cfun->machine->base_reg;
5946 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5947 UNSPEC_LTREF);
5948
5949 SET_SRC (*x) = addr;
5950 return;
5951 }
5952
5953 if (GET_CODE (addrref) == CONST
5954 && GET_CODE (XEXP (addrref, 0)) == PLUS
5955 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5956 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5957 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5958 {
5959 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5960 rtx sym = XEXP (XEXP (addrref, 0), 0);
5961 rtx base = cfun->machine->base_reg;
5962 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5963 UNSPEC_LTREF);
5964
0a81f074 5965 SET_SRC (*x) = plus_constant (Pmode, addr, off);
585539a1
UW		 5966 return;
5967 }
5968 }
5969
5970 /* Annotate LTREL_BASE as well. */
5971 if (GET_CODE (*x) == UNSPEC
5972 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5973 {
5974 rtx base = cfun->machine->base_reg;
5975 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5976 UNSPEC_LTREL_BASE);
5977 return;
5978 }
5979
5980 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5981 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5982 {
5983 if (fmt[i] == 'e')
5984 {
5985 annotate_constant_pool_refs (&XEXP (*x, i));
5986 }
5987 else if (fmt[i] == 'E')
5988 {
5989 for (j = 0; j < XVECLEN (*x, i); j++)
5990 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5991 }
5992 }
5993}
5994
ab96de7e
AS		 5995/* Split all branches that exceed the maximum distance.
5996 Returns true if this created a new literal pool entry. */
5997
5998static int
5999s390_split_branches (void)
6000{
6001 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8d933e31 6002 int new_literal = 0, ret;
775c43d3 6003 rtx_insn *insn;
17f385d8 6004 rtx pat, target;
ab96de7e
AS		 6005 rtx *label;
6006
6007 /* We need correct insn addresses. */
6008
6009 shorten_branches (get_insns ());
6010
6011 /* Find all branches that exceed 64KB, and split them. */
6012
6013 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6014 {
966f97ac 6015 if (! JUMP_P (insn) || tablejump_p (insn, NULL, NULL))
ab96de7e
AS		 6016 continue;
6017
6018 pat = PATTERN (insn);
966f97ac 6019 if (GET_CODE (pat) == PARALLEL)
ab96de7e
AS		 6020 pat = XVECEXP (pat, 0, 0);
6021 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
6022 continue;
6023
6024 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
6025 {
6026 label = &SET_SRC (pat);
6027 }
6028 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
6029 {
6030 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
6031 label = &XEXP (SET_SRC (pat), 1);
6032 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
6033 label = &XEXP (SET_SRC (pat), 2);
6034 else
6035 continue;
6036 }
6037 else
6038 continue;
6039
6040 if (get_attr_length (insn) <= 4)
6041 continue;
6042
e2df5c1d
UW		 6043 /* We are going to use the return register as scratch register,
6044 make sure it will be saved/restored by the prologue/epilogue. */
6045 cfun_frame_layout.save_return_addr_p = 1;
6046
ab96de7e
AS		 6047 if (!flag_pic)
6048 {
6049 new_literal = 1;
17f385d8
DM		 6050 rtx mem = force_const_mem (Pmode, *label);
6051 rtx_insn *set_insn = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, mem), insn);
6052 INSN_ADDRESSES_NEW (set_insn, -1);
6053 annotate_constant_pool_refs (&PATTERN (set_insn));
ab96de7e
AS		 6054
6055 target = temp_reg;
6056 }
6057 else
6058 {
6059 new_literal = 1;
6060 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
6061 UNSPEC_LTREL_OFFSET);
6062 target = gen_rtx_CONST (Pmode, target);
6063 target = force_const_mem (Pmode, target);
17f385d8
DM		 6064 rtx_insn *set_insn = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
6065 INSN_ADDRESSES_NEW (set_insn, -1);
6066 annotate_constant_pool_refs (&PATTERN (set_insn));
ab96de7e
AS		 6067
6068 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
6069 cfun->machine->base_reg),
6070 UNSPEC_LTREL_BASE);
6071 target = gen_rtx_PLUS (Pmode, temp_reg, target);
6072 }
6073
8d933e31
AS		 6074 ret = validate_change (insn, label, target, 0);
6075 gcc_assert (ret);
ab96de7e
AS		 6076 }
6077
6078 return new_literal;
6079}
6080
b2ccb744 6081
f4aa3848
AK		 6082/* Find an annotated literal pool symbol referenced in RTX X,
6083 and store it at REF. Will abort if X contains references to
585539a1
UW		 6084 more than one such pool symbol; multiple references to the same
6085 symbol are allowed, however.
b2ccb744 6086
c7453384 6087 The rtx pointed to by REF must be initialized to NULL_RTX
b2ccb744
UW		 6088 by the caller before calling this routine. */
6089
6090static void
9c808aad 6091find_constant_pool_ref (rtx x, rtx *ref)
b2ccb744
UW		 6092{
6093 int i, j;
6094 const char *fmt;
6095
fd7643fb
UW		 6096 /* Ignore LTREL_BASE references. */
6097 if (GET_CODE (x) == UNSPEC
6098 && XINT (x, 1) == UNSPEC_LTREL_BASE)
6099 return;
5af2f3d3
UW		 6100 /* Likewise POOL_ENTRY insns. */
6101 if (GET_CODE (x) == UNSPEC_VOLATILE
6102 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
6103 return;
fd7643fb 6104
8d933e31
AS		 6105 gcc_assert (GET_CODE (x) != SYMBOL_REF
6106 || !CONSTANT_POOL_ADDRESS_P (x));
585539a1
UW		 6107
6108 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
b2ccb744 6109 {
585539a1 6110 rtx sym = XVECEXP (x, 0, 0);
8d933e31
AS		 6111 gcc_assert (GET_CODE (sym) == SYMBOL_REF
6112 && CONSTANT_POOL_ADDRESS_P (sym));
585539a1 6113
b2ccb744 6114 if (*ref == NULL_RTX)
585539a1 6115 *ref = sym;
f4aa3848 6116 else
8d933e31 6117 gcc_assert (*ref == sym);
585539a1
UW		 6118
6119 return;
b2ccb744
UW		 6120 }
6121
6122 fmt = GET_RTX_FORMAT (GET_CODE (x));
6123 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6124 {
6125 if (fmt[i] == 'e')
6126 {
6127 find_constant_pool_ref (XEXP (x, i), ref);
6128 }
6129 else if (fmt[i] == 'E')
6130 {
6131 for (j = 0; j < XVECLEN (x, i); j++)
6132 find_constant_pool_ref (XVECEXP (x, i, j), ref);
6133 }
6134 }
6135}
6136
f4aa3848 6137/* Replace every reference to the annotated literal pool
585539a1 6138 symbol REF in X by its base plus OFFSET. */
b2ccb744
UW		 6139
6140static void
585539a1 6141replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
b2ccb744
UW		 6142{
6143 int i, j;
6144 const char *fmt;
6145
8d933e31 6146 gcc_assert (*x != ref);
b2ccb744 6147
585539a1
UW		 6148 if (GET_CODE (*x) == UNSPEC
6149 && XINT (*x, 1) == UNSPEC_LTREF
6150 && XVECEXP (*x, 0, 0) == ref)
b2ccb744 6151 {
585539a1
UW		 6152 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
6153 return;
b2ccb744
UW		 6154 }
6155
585539a1
UW		 6156 if (GET_CODE (*x) == PLUS
6157 && GET_CODE (XEXP (*x, 1)) == CONST_INT
6158 && GET_CODE (XEXP (*x, 0)) == UNSPEC
6159 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
6160 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
b2ccb744 6161 {
585539a1 6162 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
0a81f074 6163 *x = plus_constant (Pmode, addr, INTVAL (XEXP (*x, 1)));
585539a1 6164 return;
b2ccb744
UW		 6165 }
6166
6167 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6168 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6169 {
6170 if (fmt[i] == 'e')
6171 {
585539a1 6172 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
b2ccb744
UW		 6173 }
6174 else if (fmt[i] == 'E')
6175 {
6176 for (j = 0; j < XVECLEN (*x, i); j++)
585539a1 6177 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
b2ccb744
UW		 6178 }
6179 }
6180}
6181
c7453384 6182/* Check whether X contains an UNSPEC_LTREL_BASE.
fd7643fb 6183 Return its constant pool symbol if found, NULL_RTX otherwise. */
aee4e0db 6184
fd7643fb 6185static rtx
9c808aad 6186find_ltrel_base (rtx x)
aee4e0db 6187{
aee4e0db
UW		 6188 int i, j;
6189 const char *fmt;
6190
fd7643fb
UW		 6191 if (GET_CODE (x) == UNSPEC
6192 && XINT (x, 1) == UNSPEC_LTREL_BASE)
6193 return XVECEXP (x, 0, 0);
aee4e0db
UW		 6194
6195 fmt = GET_RTX_FORMAT (GET_CODE (x));
6196 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6197 {
6198 if (fmt[i] == 'e')
6199 {
fd7643fb
UW		 6200 rtx fnd = find_ltrel_base (XEXP (x, i));
6201 if (fnd)
6202 return fnd;
aee4e0db
UW		 6203 }
6204 else if (fmt[i] == 'E')
6205 {
6206 for (j = 0; j < XVECLEN (x, i); j++)
fd7643fb
UW		 6207 {
6208 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
6209 if (fnd)
6210 return fnd;
6211 }
aee4e0db
UW		 6212 }
6213 }
6214
fd7643fb 6215 return NULL_RTX;
aee4e0db
UW		 6216}
6217
585539a1 6218/* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
aee4e0db
UW		 6219
6220static void
585539a1 6221replace_ltrel_base (rtx *x)
aee4e0db 6222{
fd7643fb 6223 int i, j;
aee4e0db
UW		 6224 const char *fmt;
6225
fd7643fb
UW		 6226 if (GET_CODE (*x) == UNSPEC
6227 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
aee4e0db 6228 {
585539a1 6229 *x = XVECEXP (*x, 0, 1);
fd7643fb 6230 return;
aee4e0db
UW		 6231 }
6232
6233 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6234 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6235 {
6236 if (fmt[i] == 'e')
6237 {
585539a1 6238 replace_ltrel_base (&XEXP (*x, i));
aee4e0db
UW		 6239 }
6240 else if (fmt[i] == 'E')
6241 {
6242 for (j = 0; j < XVECLEN (*x, i); j++)
585539a1 6243 replace_ltrel_base (&XVECEXP (*x, i, j));
aee4e0db
UW		 6244 }
6245 }
6246}
6247
6248
fd7643fb 6249/* We keep a list of constants which we have to add to internal
b2ccb744
UW		 6250 constant tables in the middle of large functions. */
6251
4dc19cc0 6252#define NR_C_MODES 11
ef4bddc2 6253machine_mode constant_modes[NR_C_MODES] =
b2ccb744 6254{
4dc19cc0
AK		 6255 TFmode, TImode, TDmode,
6256 DFmode, DImode, DDmode,
6257 SFmode, SImode, SDmode,
b2ccb744
UW		 6258 HImode,
6259 QImode
6260};
6261
b2ccb744
UW		 6262struct constant
6263{
6264 struct constant *next;
6265 rtx value;
775c43d3 6266 rtx_code_label *label;
b2ccb744
UW		 6267};
6268
6269struct constant_pool
6270{
6271 struct constant_pool *next;
775c43d3
DM		 6272 rtx_insn *first_insn;
6273 rtx_insn *pool_insn;
aee4e0db 6274 bitmap insns;
775c43d3 6275 rtx_insn *emit_pool_after;
b2ccb744
UW		 6276
6277 struct constant *constants[NR_C_MODES];
9bb86f41 6278 struct constant *execute;
775c43d3 6279 rtx_code_label *label;
b2ccb744
UW		 6280 int size;
6281};
6282
ab96de7e
AS		 6283/* Allocate new constant_pool structure. */
6284
6285static struct constant_pool *
6286s390_alloc_pool (void)
6287{
6288 struct constant_pool *pool;
6289 int i;
6290
6291 pool = (struct constant_pool *) xmalloc (sizeof *pool);
6292 pool->next = NULL;
6293 for (i = 0; i < NR_C_MODES; i++)
6294 pool->constants[i] = NULL;
6295
6296 pool->execute = NULL;
6297 pool->label = gen_label_rtx ();
775c43d3
DM		 6298 pool->first_insn = NULL;
6299 pool->pool_insn = NULL;
ab96de7e
AS		 6300 pool->insns = BITMAP_ALLOC (NULL);
6301 pool->size = 0;
775c43d3 6302 pool->emit_pool_after = NULL;
ab96de7e
AS		 6303
6304 return pool;
6305}
b2ccb744
UW		 6306
6307/* Create new constant pool covering instructions starting at INSN
6308 and chain it to the end of POOL_LIST. */
6309
6310static struct constant_pool *
775c43d3 6311s390_start_pool (struct constant_pool **pool_list, rtx_insn *insn)
b2ccb744
UW		 6312{
6313 struct constant_pool *pool, **prev;
b2ccb744 6314
5af2f3d3 6315 pool = s390_alloc_pool ();
b2ccb744 6316 pool->first_insn = insn;
aee4e0db 6317
b2ccb744
UW		 6318 for (prev = pool_list; *prev; prev = &(*prev)->next)
6319 ;
6320 *prev = pool;
6321
6322 return pool;
6323}
6324
aee4e0db
UW		 6325/* End range of instructions covered by POOL at INSN and emit
6326 placeholder insn representing the pool. */
b2ccb744
UW		 6327
6328static void
775c43d3 6329s390_end_pool (struct constant_pool *pool, rtx_insn *insn)
b2ccb744 6330{
aee4e0db
UW		 6331 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
6332
6333 if (!insn)
6334 insn = get_last_insn ();
6335
6336 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
6337 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6338}
6339
6340/* Add INSN to the list of insns covered by POOL. */
6341
6342static void
9c808aad 6343s390_add_pool_insn (struct constant_pool *pool, rtx insn)
aee4e0db
UW		 6344{
6345 bitmap_set_bit (pool->insns, INSN_UID (insn));
b2ccb744
UW		 6346}
6347
6348/* Return pool out of POOL_LIST that covers INSN. */
6349
6350static struct constant_pool *
9c808aad 6351s390_find_pool (struct constant_pool *pool_list, rtx insn)
b2ccb744 6352{
b2ccb744
UW		 6353 struct constant_pool *pool;
6354
b2ccb744 6355 for (pool = pool_list; pool; pool = pool->next)
aee4e0db 6356 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
b2ccb744
UW		 6357 break;
6358
6359 return pool;
6360}
6361
aee4e0db 6362/* Add constant VAL of mode MODE to the constant pool POOL. */
b2ccb744 6363
aee4e0db 6364static void
ef4bddc2 6365s390_add_constant (struct constant_pool *pool, rtx val, machine_mode mode)
b2ccb744
UW		 6366{
6367 struct constant *c;
b2ccb744
UW		 6368 int i;
6369
6370 for (i = 0; i < NR_C_MODES; i++)
6371 if (constant_modes[i] == mode)
6372 break;
8d933e31 6373 gcc_assert (i != NR_C_MODES);
b2ccb744
UW		 6374
6375 for (c = pool->constants[i]; c != NULL; c = c->next)
6376 if (rtx_equal_p (val, c->value))
6377 break;
6378
6379 if (c == NULL)
6380 {
6381 c = (struct constant *) xmalloc (sizeof *c);
6382 c->value = val;
6383 c->label = gen_label_rtx ();
6384 c->next = pool->constants[i];
6385 pool->constants[i] = c;
6386 pool->size += GET_MODE_SIZE (mode);
6387 }
aee4e0db 6388}
b2ccb744 6389
dc66391d
RS		 6390/* Return an rtx that represents the offset of X from the start of
6391 pool POOL. */
6392
6393static rtx
6394s390_pool_offset (struct constant_pool *pool, rtx x)
6395{
6396 rtx label;
6397
6398 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
6399 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
6400 UNSPEC_POOL_OFFSET);
6401 return gen_rtx_CONST (GET_MODE (x), x);
6402}
6403
aee4e0db
UW		 6404/* Find constant VAL of mode MODE in the constant pool POOL.
6405 Return an RTX describing the distance from the start of
6406 the pool to the location of the new constant. */
c7453384 6407
aee4e0db 6408static rtx
9c808aad 6409s390_find_constant (struct constant_pool *pool, rtx val,
ef4bddc2 6410 machine_mode mode)
aee4e0db
UW		 6411{
6412 struct constant *c;
aee4e0db 6413 int i;
c7453384 6414
aee4e0db
UW		 6415 for (i = 0; i < NR_C_MODES; i++)
6416 if (constant_modes[i] == mode)
6417 break;
8d933e31 6418 gcc_assert (i != NR_C_MODES);
c7453384 6419
aee4e0db
UW		 6420 for (c = pool->constants[i]; c != NULL; c = c->next)
6421 if (rtx_equal_p (val, c->value))
6422 break;
c7453384 6423
8d933e31 6424 gcc_assert (c);
c7453384 6425
dc66391d 6426 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
b2ccb744
UW		 6427}
6428
ab96de7e
AS		 6429/* Check whether INSN is an execute. Return the label_ref to its
6430 execute target template if so, NULL_RTX otherwise. */
6431
6432static rtx
6433s390_execute_label (rtx insn)
6434{
b64925dc 6435 if (NONJUMP_INSN_P (insn)
ab96de7e
AS		 6436 && GET_CODE (PATTERN (insn)) == PARALLEL
6437 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
6438 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
6439 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
6440
6441 return NULL_RTX;
6442}
6443
9bb86f41
UW		 6444/* Add execute target for INSN to the constant pool POOL. */
6445
6446static void
6447s390_add_execute (struct constant_pool *pool, rtx insn)
6448{
6449 struct constant *c;
6450
6451 for (c = pool->execute; c != NULL; c = c->next)
6452 if (INSN_UID (insn) == INSN_UID (c->value))
6453 break;
6454
6455 if (c == NULL)
6456 {
9bb86f41
UW		 6457 c = (struct constant *) xmalloc (sizeof *c);
6458 c->value = insn;
d24959df 6459 c->label = gen_label_rtx ();
9bb86f41
UW		 6460 c->next = pool->execute;
6461 pool->execute = c;
d24959df 6462 pool->size += 6;
9bb86f41
UW		 6463 }
6464}
6465
6466/* Find execute target for INSN in the constant pool POOL.
6467 Return an RTX describing the distance from the start of
6468 the pool to the location of the execute target. */
6469
6470static rtx
6471s390_find_execute (struct constant_pool *pool, rtx insn)
6472{
6473 struct constant *c;
9bb86f41
UW		 6474
6475 for (c = pool->execute; c != NULL; c = c->next)
6476 if (INSN_UID (insn) == INSN_UID (c->value))
6477 break;
6478
8d933e31 6479 gcc_assert (c);
9bb86f41 6480
dc66391d 6481 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
9bb86f41
UW		 6482}
6483
ab96de7e 6484/* For an execute INSN, extract the execute target template. */
9bb86f41
UW		 6485
6486static rtx
ab96de7e 6487s390_execute_target (rtx insn)
9bb86f41 6488{
ab96de7e
AS		 6489 rtx pattern = PATTERN (insn);
6490 gcc_assert (s390_execute_label (insn));
9bb86f41
UW		 6491
6492 if (XVECLEN (pattern, 0) == 2)
6493 {
6494 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6495 }
6496 else
6497 {
6498 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6499 int i;
6500
6501 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6502 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6503
6504 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6505 }
6506
6507 return pattern;
6508}
6509
6510/* Indicate that INSN cannot be duplicated. This is the case for
6511 execute insns that carry a unique label. */
6512
6513static bool
ac44248e 6514s390_cannot_copy_insn_p (rtx_insn *insn)
9bb86f41
UW		 6515{
6516 rtx label = s390_execute_label (insn);
6517 return label && label != const0_rtx;
6518}
6519
5af2f3d3
UW		 6520/* Dump out the constants in POOL. If REMOTE_LABEL is true,
6521 do not emit the pool base label. */
b2ccb744 6522
9bb86f41 6523static void
5af2f3d3 6524s390_dump_pool (struct constant_pool *pool, bool remote_label)
b2ccb744
UW		 6525{
6526 struct constant *c;
775c43d3 6527 rtx_insn *insn = pool->pool_insn;
b2ccb744
UW		 6528 int i;
6529
9bb86f41
UW		 6530 /* Switch to rodata section. */
6531 if (TARGET_CPU_ZARCH)
6532 {
6533 insn = emit_insn_after (gen_pool_section_start (), insn);
6534 INSN_ADDRESSES_NEW (insn, -1);
6535 }
6536
6537 /* Ensure minimum pool alignment. */
9e8327e3 6538 if (TARGET_CPU_ZARCH)
9bb86f41 6539 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
b2ccb744 6540 else
9bb86f41 6541 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
b2ccb744
UW		 6542 INSN_ADDRESSES_NEW (insn, -1);
6543
9bb86f41 6544 /* Emit pool base label. */
5af2f3d3
UW		 6545 if (!remote_label)
6546 {
6547 insn = emit_label_after (pool->label, insn);
6548 INSN_ADDRESSES_NEW (insn, -1);
6549 }
b2ccb744
UW		 6550
6551 /* Dump constants in descending alignment requirement order,
6552 ensuring proper alignment for every constant. */
6553 for (i = 0; i < NR_C_MODES; i++)
6554 for (c = pool->constants[i]; c; c = c->next)
6555 {
fd7643fb 6556 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
77340500 6557 rtx value = copy_rtx (c->value);
aee4e0db
UW		 6558 if (GET_CODE (value) == CONST
6559 && GET_CODE (XEXP (value, 0)) == UNSPEC
fd7643fb 6560 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
aee4e0db 6561 && XVECLEN (XEXP (value, 0), 0) == 1)
dc66391d 6562 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
aee4e0db 6563
b2ccb744
UW		 6564 insn = emit_label_after (c->label, insn);
6565 INSN_ADDRESSES_NEW (insn, -1);
416cf582 6566
38899e29 6567 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
416cf582
UW		 6568 gen_rtvec (1, value),
6569 UNSPECV_POOL_ENTRY);
6570 insn = emit_insn_after (value, insn);
b2ccb744
UW		 6571 INSN_ADDRESSES_NEW (insn, -1);
6572 }
6573
9bb86f41
UW		 6574 /* Ensure minimum alignment for instructions. */
6575 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
b2ccb744
UW		 6576 INSN_ADDRESSES_NEW (insn, -1);
6577
9bb86f41
UW		 6578 /* Output in-pool execute template insns. */
6579 for (c = pool->execute; c; c = c->next)
6580 {
9bb86f41
UW		 6581 insn = emit_label_after (c->label, insn);
6582 INSN_ADDRESSES_NEW (insn, -1);
6583
6584 insn = emit_insn_after (s390_execute_target (c->value), insn);
6585 INSN_ADDRESSES_NEW (insn, -1);
6586 }
6587
6588 /* Switch back to previous section. */
6589 if (TARGET_CPU_ZARCH)
6590 {
6591 insn = emit_insn_after (gen_pool_section_end (), insn);
6592 INSN_ADDRESSES_NEW (insn, -1);
6593 }
6594
b2ccb744
UW		 6595 insn = emit_barrier_after (insn);
6596 INSN_ADDRESSES_NEW (insn, -1);
6597
aee4e0db
UW		 6598 /* Remove placeholder insn. */
6599 remove_insn (pool->pool_insn);
9bb86f41
UW		 6600}
6601
b2ccb744
UW		 6602/* Free all memory used by POOL. */
6603
6604static void
9c808aad 6605s390_free_pool (struct constant_pool *pool)
b2ccb744 6606{
9bb86f41 6607 struct constant *c, *next;
b2ccb744
UW		 6608 int i;
6609
6610 for (i = 0; i < NR_C_MODES; i++)
9bb86f41
UW		 6611 for (c = pool->constants[i]; c; c = next)
6612 {
6613 next = c->next;
6614 free (c);
6615 }
6616
6617 for (c = pool->execute; c; c = next)
b2ccb744 6618 {
9bb86f41
UW		 6619 next = c->next;
6620 free (c);
b2ccb744
UW		 6621 }
6622
7b210806 6623 BITMAP_FREE (pool->insns);
b2ccb744 6624 free (pool);
c7453384 6625}
b2ccb744 6626
b2ccb744 6627
5af2f3d3
UW		 6628/* Collect main literal pool. Return NULL on overflow. */
6629
6630static struct constant_pool *
6631s390_mainpool_start (void)
6632{
6633 struct constant_pool *pool;
775c43d3 6634 rtx_insn *insn;
5af2f3d3
UW		 6635
6636 pool = s390_alloc_pool ();
6637
6638 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6639 {
b64925dc 6640 if (NONJUMP_INSN_P (insn)
585539a1
UW		 6641 && GET_CODE (PATTERN (insn)) == SET
6642 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6643 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
5af2f3d3 6644 {
177bc204
RS		 6645 /* There might be two main_pool instructions if base_reg
6646 is call-clobbered; one for shrink-wrapped code and one
6647 for the rest. We want to keep the first. */
6648 if (pool->pool_insn)
6649 {
6650 insn = PREV_INSN (insn);
6651 delete_insn (NEXT_INSN (insn));
6652 continue;
6653 }
5af2f3d3
UW		 6654 pool->pool_insn = insn;
6655 }
6656
d24959df 6657 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
9bb86f41
UW		 6658 {
6659 s390_add_execute (pool, insn);
6660 }
b64925dc 6661 else if (NONJUMP_INSN_P (insn) || CALL_P (insn))
5af2f3d3
UW		 6662 {
6663 rtx pool_ref = NULL_RTX;
6664 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6665 if (pool_ref)
6666 {
6667 rtx constant = get_pool_constant (pool_ref);
ef4bddc2 6668 machine_mode mode = get_pool_mode (pool_ref);
5af2f3d3
UW		 6669 s390_add_constant (pool, constant, mode);
6670 }
6671 }
03870a04
AK		 6672
6673 /* If hot/cold partitioning is enabled we have to make sure that
6674 the literal pool is emitted in the same section where the
6675 initialization of the literal pool base pointer takes place.
6676 emit_pool_after is only used in the non-overflow case on non
6677 Z cpus where we can emit the literal pool at the end of the
6678 function body within the text section. */
6679 if (NOTE_P (insn)
b49326f1
AK		 6680 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6681 && !pool->emit_pool_after)
6682 pool->emit_pool_after = PREV_INSN (insn);
5af2f3d3
UW		 6683 }
6684
8d933e31 6685 gcc_assert (pool->pool_insn || pool->size == 0);
5af2f3d3
UW		 6686
6687 if (pool->size >= 4096)
6688 {
d76e8439
UW		 6689 /* We're going to chunkify the pool, so remove the main
6690 pool placeholder insn. */
6691 remove_insn (pool->pool_insn);
6692
5af2f3d3
UW		 6693 s390_free_pool (pool);
6694 pool = NULL;
6695 }
6696
03870a04
AK		 6697 /* If the functions ends with the section where the literal pool
6698 should be emitted set the marker to its end. */
b49326f1 6699 if (pool && !pool->emit_pool_after)
03870a04
AK		 6700 pool->emit_pool_after = get_last_insn ();
6701
5af2f3d3
UW		 6702 return pool;
6703}
6704
6705/* POOL holds the main literal pool as collected by s390_mainpool_start.
6706 Modify the current function to output the pool constants as well as
585539a1 6707 the pool register setup instruction. */
5af2f3d3
UW		 6708
6709static void
585539a1 6710s390_mainpool_finish (struct constant_pool *pool)
5af2f3d3 6711{
91086990 6712 rtx base_reg = cfun->machine->base_reg;
5af2f3d3
UW		 6713
6714 /* If the pool is empty, we're done. */
6715 if (pool->size == 0)
6716 {
91086990
UW		 6717 /* We don't actually need a base register after all. */
6718 cfun->machine->base_reg = NULL_RTX;
6719
6720 if (pool->pool_insn)
6721 remove_insn (pool->pool_insn);
5af2f3d3
UW		 6722 s390_free_pool (pool);
6723 return;
6724 }
6725
6726 /* We need correct insn addresses. */
6727 shorten_branches (get_insns ());
6728
9e8327e3 6729 /* On zSeries, we use a LARL to load the pool register. The pool is
5af2f3d3 6730 located in the .rodata section, so we emit it after the function. */
9e8327e3 6731 if (TARGET_CPU_ZARCH)
5af2f3d3 6732 {
17f385d8
DM		 6733 rtx set = gen_main_base_64 (base_reg, pool->label);
6734 rtx_insn *insn = emit_insn_after (set, pool->pool_insn);
5af2f3d3
UW		 6735 INSN_ADDRESSES_NEW (insn, -1);
6736 remove_insn (pool->pool_insn);
38899e29
EC		 6737
6738 insn = get_last_insn ();
5af2f3d3
UW		 6739 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6740 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6741
6742 s390_dump_pool (pool, 0);
6743 }
6744
9e8327e3 6745 /* On S/390, if the total size of the function's code plus literal pool
5af2f3d3
UW		 6746 does not exceed 4096 bytes, we use BASR to set up a function base
6747 pointer, and emit the literal pool at the end of the function. */
03870a04 6748 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
5af2f3d3
UW		 6749 + pool->size + 8 /* alignment slop */ < 4096)
6750 {
17f385d8
DM		 6751 rtx set = gen_main_base_31_small (base_reg, pool->label);
6752 rtx_insn *insn = emit_insn_after (set, pool->pool_insn);
5af2f3d3
UW		 6753 INSN_ADDRESSES_NEW (insn, -1);
6754 remove_insn (pool->pool_insn);
6755
6756 insn = emit_label_after (pool->label, insn);
6757 INSN_ADDRESSES_NEW (insn, -1);
6758
03870a04
AK		 6759 /* emit_pool_after will be set by s390_mainpool_start to the
6760 last insn of the section where the literal pool should be
6761 emitted. */
6762 insn = pool->emit_pool_after;
6763
5af2f3d3
UW		 6764 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6765 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6766
6767 s390_dump_pool (pool, 1);
6768 }
6769
6770 /* Otherwise, we emit an inline literal pool and use BASR to branch
6771 over it, setting up the pool register at the same time. */
6772 else
6773 {
17f385d8 6774 rtx_code_label *pool_end = gen_label_rtx ();
5af2f3d3 6775
17f385d8
DM		 6776 rtx pat = gen_main_base_31_large (base_reg, pool->label, pool_end);
6777 rtx_insn *insn = emit_jump_insn_after (pat, pool->pool_insn);
b0a1ac21 6778 JUMP_LABEL (insn) = pool_end;
5af2f3d3
UW		 6779 INSN_ADDRESSES_NEW (insn, -1);
6780 remove_insn (pool->pool_insn);
6781
6782 insn = emit_label_after (pool->label, insn);
6783 INSN_ADDRESSES_NEW (insn, -1);
6784
6785 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6786 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6787
6788 insn = emit_label_after (pool_end, pool->pool_insn);
6789 INSN_ADDRESSES_NEW (insn, -1);
6790
6791 s390_dump_pool (pool, 1);
6792 }
6793
6794
6795 /* Replace all literal pool references. */
6796
b32d5189 6797 for (rtx_insn *insn = get_insns (); insn; insn = NEXT_INSN (insn))
5af2f3d3
UW		 6798 {
6799 if (INSN_P (insn))
585539a1 6800 replace_ltrel_base (&PATTERN (insn));
5af2f3d3 6801
b64925dc 6802 if (NONJUMP_INSN_P (insn) || CALL_P (insn))
5af2f3d3
UW		 6803 {
6804 rtx addr, pool_ref = NULL_RTX;
6805 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6806 if (pool_ref)
6807 {
9bb86f41
UW		 6808 if (s390_execute_label (insn))
6809 addr = s390_find_execute (pool, insn);
6810 else
6811 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6812 get_pool_mode (pool_ref));
6813
5af2f3d3
UW		 6814 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6815 INSN_CODE (insn) = -1;
6816 }
6817 }
6818 }
6819
6820
6821 /* Free the pool. */
6822 s390_free_pool (pool);
6823}
6824
6825/* POOL holds the main literal pool as collected by s390_mainpool_start.
6826 We have decided we cannot use this pool, so revert all changes
6827 to the current function that were done by s390_mainpool_start. */
6828static void
6829s390_mainpool_cancel (struct constant_pool *pool)
6830{
6831 /* We didn't actually change the instruction stream, so simply
6832 free the pool memory. */
6833 s390_free_pool (pool);
6834}
6835
6836
585539a1 6837/* Chunkify the literal pool. */
9db1d521 6838
b2ccb744
UW		 6839#define S390_POOL_CHUNK_MIN 0xc00
6840#define S390_POOL_CHUNK_MAX 0xe00
6841
c7453384 6842static struct constant_pool *
585539a1 6843s390_chunkify_start (void)
9db1d521 6844{
b2ccb744
UW		 6845 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6846 int extra_size = 0;
6847 bitmap far_labels;
fd7643fb 6848 rtx pending_ltrel = NULL_RTX;
775c43d3 6849 rtx_insn *insn;
9db1d521 6850
9c808aad 6851 rtx (*gen_reload_base) (rtx, rtx) =
9e8327e3 6852 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
aee4e0db
UW		 6853
6854
c3cc6b78
UW		 6855 /* We need correct insn addresses. */
6856
6857 shorten_branches (get_insns ());
6858
fd7643fb 6859 /* Scan all insns and move literals to pool chunks. */
13e58269 6860
13e58269 6861 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9db1d521 6862 {
03870a04
AK		 6863 bool section_switch_p = false;
6864
fd7643fb
UW		 6865 /* Check for pending LTREL_BASE. */
6866 if (INSN_P (insn))
6867 {
6868 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6869 if (ltrel_base)
6870 {
8d933e31
AS		 6871 gcc_assert (ltrel_base == pending_ltrel);
6872 pending_ltrel = NULL_RTX;
fd7643fb
UW		 6873 }
6874 }
6875
d24959df 6876 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
9bb86f41
UW		 6877 {
6878 if (!curr_pool)
6879 curr_pool = s390_start_pool (&pool_list, insn);
6880
6881 s390_add_execute (curr_pool, insn);
6882 s390_add_pool_insn (curr_pool, insn);
6883 }
b64925dc 6884 else if (NONJUMP_INSN_P (insn) || CALL_P (insn))
b2ccb744 6885 {
aee4e0db 6886 rtx pool_ref = NULL_RTX;
b2ccb744
UW		 6887 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6888 if (pool_ref)
6889 {
fd7643fb 6890 rtx constant = get_pool_constant (pool_ref);
ef4bddc2 6891 machine_mode mode = get_pool_mode (pool_ref);
fd7643fb 6892
b2ccb744
UW		 6893 if (!curr_pool)
6894 curr_pool = s390_start_pool (&pool_list, insn);
6895
fd7643fb 6896 s390_add_constant (curr_pool, constant, mode);
aee4e0db 6897 s390_add_pool_insn (curr_pool, insn);
aee4e0db 6898
fd7643fb
UW		 6899 /* Don't split the pool chunk between a LTREL_OFFSET load
6900 and the corresponding LTREL_BASE. */
6901 if (GET_CODE (constant) == CONST
6902 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6903 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6904 {
8d933e31 6905 gcc_assert (!pending_ltrel);
fd7643fb
UW		 6906 pending_ltrel = pool_ref;
6907 }
b2ccb744
UW		 6908 }
6909 }
6910
39718607 6911 if (JUMP_P (insn) || JUMP_TABLE_DATA_P (insn) || LABEL_P (insn))
fd7643fb
UW		 6912 {
6913 if (curr_pool)
6914 s390_add_pool_insn (curr_pool, insn);
6915 /* An LTREL_BASE must follow within the same basic block. */
8d933e31 6916 gcc_assert (!pending_ltrel);
fd7643fb 6917 }
aee4e0db 6918
00fbd5c8
JJ		 6919 if (NOTE_P (insn))
6920 switch (NOTE_KIND (insn))
6921 {
6922 case NOTE_INSN_SWITCH_TEXT_SECTIONS:
6923 section_switch_p = true;
6924 break;
6925 case NOTE_INSN_VAR_LOCATION:
6926 case NOTE_INSN_CALL_ARG_LOCATION:
6927 continue;
6928 default:
6929 break;
6930 }
03870a04 6931
c7453384 6932 if (!curr_pool
b2ccb744
UW		 6933 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6934 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
9db1d521 6935 continue;
13e58269 6936
9e8327e3 6937 if (TARGET_CPU_ZARCH)
9db1d521 6938 {
b2ccb744
UW		 6939 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6940 continue;
13e58269 6941
775c43d3 6942 s390_end_pool (curr_pool, NULL);
b2ccb744
UW		 6943 curr_pool = NULL;
6944 }
6945 else
9db1d521 6946 {
b2ccb744 6947 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
9c808aad 6948 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
b2ccb744
UW		 6949 + extra_size;
6950
6951 /* We will later have to insert base register reload insns.
6952 Those will have an effect on code size, which we need to
6953 consider here. This calculation makes rather pessimistic
6954 worst-case assumptions. */
b64925dc 6955 if (LABEL_P (insn))
b2ccb744 6956 extra_size += 6;
b2ccb744
UW		 6957
6958 if (chunk_size < S390_POOL_CHUNK_MIN
03870a04
AK		 6959 && curr_pool->size < S390_POOL_CHUNK_MIN
6960 && !section_switch_p)
b2ccb744
UW		 6961 continue;
6962
6963 /* Pool chunks can only be inserted after BARRIERs ... */
b64925dc 6964 if (BARRIER_P (insn))
b2ccb744
UW		 6965 {
6966 s390_end_pool (curr_pool, insn);
6967 curr_pool = NULL;
6968 extra_size = 0;
6969 }
6970
6971 /* ... so if we don't find one in time, create one. */
03870a04
AK		 6972 else if (chunk_size > S390_POOL_CHUNK_MAX
6973 || curr_pool->size > S390_POOL_CHUNK_MAX
6974 || section_switch_p)
b2ccb744 6975 {
775c43d3 6976 rtx_insn *label, *jump, *barrier, *next, *prev;
b2ccb744 6977
03870a04
AK		 6978 if (!section_switch_p)
6979 {
6980 /* We can insert the barrier only after a 'real' insn. */
b64925dc 6981 if (! NONJUMP_INSN_P (insn) && ! CALL_P (insn))
03870a04
AK		 6982 continue;
6983 if (get_attr_length (insn) == 0)
6984 continue;
6985 /* Don't separate LTREL_BASE from the corresponding
00fbd5c8 6986 LTREL_OFFSET load. */
03870a04
AK		 6987 if (pending_ltrel)
6988 continue;
00fbd5c8
JJ		 6989 next = insn;
6990 do
6991 {
6992 insn = next;
6993 next = NEXT_INSN (insn);
6994 }
6995 while (next
6996 && NOTE_P (next)
6997 && (NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION
6998 || NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION));
03870a04
AK		 6999 }
7000 else
7001 {
7002 gcc_assert (!pending_ltrel);
7003
7004 /* The old pool has to end before the section switch
7005 note in order to make it part of the current
7006 section. */
7007 insn = PREV_INSN (insn);
7008 }
aee4e0db 7009
9c808aad 7010 label = gen_label_rtx ();
00fbd5c8
JJ		 7011 prev = insn;
7012 if (prev && NOTE_P (prev))
7013 prev = prev_nonnote_insn (prev);
7014 if (prev)
7015 jump = emit_jump_insn_after_setloc (gen_jump (label), insn,
9d12bc68 7016 INSN_LOCATION (prev));
00fbd5c8
JJ		 7017 else
7018 jump = emit_jump_insn_after_noloc (gen_jump (label), insn);
b2ccb744
UW		 7019 barrier = emit_barrier_after (jump);
7020 insn = emit_label_after (label, barrier);
7021 JUMP_LABEL (jump) = label;
7022 LABEL_NUSES (label) = 1;
7023
aee4e0db
UW		 7024 INSN_ADDRESSES_NEW (jump, -1);
7025 INSN_ADDRESSES_NEW (barrier, -1);
b2ccb744
UW		 7026 INSN_ADDRESSES_NEW (insn, -1);
7027
7028 s390_end_pool (curr_pool, barrier);
7029 curr_pool = NULL;
7030 extra_size = 0;
7031 }
13e58269 7032 }
9db1d521 7033 }
ce50cae8 7034
aee4e0db 7035 if (curr_pool)
775c43d3 7036 s390_end_pool (curr_pool, NULL);
8d933e31 7037 gcc_assert (!pending_ltrel);
b2ccb744 7038
c7453384 7039 /* Find all labels that are branched into
13e58269 7040 from an insn belonging to a different chunk. */
ce50cae8 7041
7b210806 7042 far_labels = BITMAP_ALLOC (NULL);
6bc627b3 7043
13e58269 7044 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9db1d521 7045 {
8942ee0f 7046 rtx_jump_table_data *table;
966f97ac 7047
b2ccb744
UW		 7048 /* Labels marked with LABEL_PRESERVE_P can be target
7049 of non-local jumps, so we have to mark them.
7050 The same holds for named labels.
7051
7052 Don't do that, however, if it is the label before
7053 a jump table. */
7054
b64925dc 7055 if (LABEL_P (insn)
b2ccb744
UW		 7056 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
7057 {
775c43d3 7058 rtx_insn *vec_insn = NEXT_INSN (insn);
34f0d87a 7059 if (! vec_insn || ! JUMP_TABLE_DATA_P (vec_insn))
b2ccb744
UW		 7060 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
7061 }
966f97ac
JJ		 7062 /* Check potential targets in a table jump (casesi_jump). */
7063 else if (tablejump_p (insn, NULL, &table))
7064 {
7065 rtx vec_pat = PATTERN (table);
7066 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
7067
7068 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
7069 {
7070 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
b2ccb744 7071
966f97ac
JJ		 7072 if (s390_find_pool (pool_list, label)
7073 != s390_find_pool (pool_list, insn))
7074 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
7075 }
7076 }
7077 /* If we have a direct jump (conditional or unconditional),
7078 check all potential targets. */
b64925dc 7079 else if (JUMP_P (insn))
13e58269 7080 {
966f97ac 7081 rtx pat = PATTERN (insn);
5fdc1e5d 7082
966f97ac 7083 if (GET_CODE (pat) == PARALLEL)
0a3bdf9d
UW		 7084 pat = XVECEXP (pat, 0, 0);
7085
966f97ac
JJ		 7086 if (GET_CODE (pat) == SET)
7087 {
aee4e0db 7088 rtx label = JUMP_LABEL (insn);
177bc204 7089 if (label && !ANY_RETURN_P (label))
13e58269 7090 {
966f97ac 7091 if (s390_find_pool (pool_list, label)
b2ccb744
UW		 7092 != s390_find_pool (pool_list, insn))
7093 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
13e58269 7094 }
b2ccb744 7095 }
966f97ac 7096 }
9db1d521 7097 }
ce50cae8 7098
b2ccb744
UW		 7099 /* Insert base register reload insns before every pool. */
7100
7101 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
aee4e0db 7102 {
f4aa3848 7103 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
585539a1 7104 curr_pool->label);
775c43d3 7105 rtx_insn *insn = curr_pool->first_insn;
aee4e0db
UW		 7106 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
7107 }
b2ccb744
UW		 7108
7109 /* Insert base register reload insns at every far label. */
13e58269 7110
13e58269 7111 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
b64925dc 7112 if (LABEL_P (insn)
b2ccb744
UW		 7113 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
7114 {
7115 struct constant_pool *pool = s390_find_pool (pool_list, insn);
7116 if (pool)
7117 {
f4aa3848 7118 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
585539a1 7119 pool->label);
aee4e0db 7120 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
b2ccb744
UW		 7121 }
7122 }
7123
aee4e0db 7124
7b210806 7125 BITMAP_FREE (far_labels);
13e58269 7126
13e58269
UW		 7127
7128 /* Recompute insn addresses. */
7129
7130 init_insn_lengths ();
7131 shorten_branches (get_insns ());
9db1d521 7132
aee4e0db
UW		 7133 return pool_list;
7134}
9db1d521 7135
aee4e0db 7136/* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
c7453384 7137 After we have decided to use this list, finish implementing
585539a1 7138 all changes to the current function as required. */
c7453384 7139
aee4e0db 7140static void
585539a1 7141s390_chunkify_finish (struct constant_pool *pool_list)
aee4e0db 7142{
aee4e0db 7143 struct constant_pool *curr_pool = NULL;
775c43d3 7144 rtx_insn *insn;
c7453384
EC		 7145
7146
aee4e0db
UW		 7147 /* Replace all literal pool references. */
7148
c7453384 7149 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
aee4e0db 7150 {
fd7643fb 7151 if (INSN_P (insn))
585539a1 7152 replace_ltrel_base (&PATTERN (insn));
fd7643fb 7153
aee4e0db
UW		 7154 curr_pool = s390_find_pool (pool_list, insn);
7155 if (!curr_pool)
7156 continue;
7157
b64925dc 7158 if (NONJUMP_INSN_P (insn) || CALL_P (insn))
aee4e0db
UW		 7159 {
7160 rtx addr, pool_ref = NULL_RTX;
7161 find_constant_pool_ref (PATTERN (insn), &pool_ref);
7162 if (pool_ref)
7163 {
9bb86f41
UW		 7164 if (s390_execute_label (insn))
7165 addr = s390_find_execute (curr_pool, insn);
7166 else
7167 addr = s390_find_constant (curr_pool,
7168 get_pool_constant (pool_ref),
7169 get_pool_mode (pool_ref));
7170
aee4e0db
UW		 7171 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
7172 INSN_CODE (insn) = -1;
7173 }
aee4e0db
UW		 7174 }
7175 }
7176
7177 /* Dump out all literal pools. */
c7453384 7178
aee4e0db 7179 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
5af2f3d3 7180 s390_dump_pool (curr_pool, 0);
c7453384 7181
aee4e0db
UW		 7182 /* Free pool list. */
7183
7184 while (pool_list)
7185 {
7186 struct constant_pool *next = pool_list->next;
7187 s390_free_pool (pool_list);
7188 pool_list = next;
7189 }
7190}
7191
7192/* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7193 We have decided we cannot use this list, so revert all changes
7194 to the current function that were done by s390_chunkify_start. */
c7453384 7195
aee4e0db 7196static void
9c808aad 7197s390_chunkify_cancel (struct constant_pool *pool_list)
aee4e0db
UW		 7198{
7199 struct constant_pool *curr_pool = NULL;
775c43d3 7200 rtx_insn *insn;
aee4e0db
UW		 7201
7202 /* Remove all pool placeholder insns. */
7203
7204 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7205 {
7206 /* Did we insert an extra barrier? Remove it. */
775c43d3
DM		 7207 rtx_insn *barrier = PREV_INSN (curr_pool->pool_insn);
7208 rtx_insn *jump = barrier? PREV_INSN (barrier) : NULL;
7209 rtx_insn *label = NEXT_INSN (curr_pool->pool_insn);
aee4e0db 7210
b64925dc
SB		 7211 if (jump && JUMP_P (jump)
7212 && barrier && BARRIER_P (barrier)
7213 && label && LABEL_P (label)
aee4e0db
UW		 7214 && GET_CODE (PATTERN (jump)) == SET
7215 && SET_DEST (PATTERN (jump)) == pc_rtx
7216 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
7217 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
7218 {
7219 remove_insn (jump);
7220 remove_insn (barrier);
7221 remove_insn (label);
b2ccb744 7222 }
9db1d521 7223
aee4e0db
UW		 7224 remove_insn (curr_pool->pool_insn);
7225 }
7226
fd7643fb 7227 /* Remove all base register reload insns. */
aee4e0db
UW		 7228
7229 for (insn = get_insns (); insn; )
7230 {
775c43d3 7231 rtx_insn *next_insn = NEXT_INSN (insn);
aee4e0db 7232
b64925dc 7233 if (NONJUMP_INSN_P (insn)
aee4e0db
UW		 7234 && GET_CODE (PATTERN (insn)) == SET
7235 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
fd7643fb 7236 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
aee4e0db 7237 remove_insn (insn);
9db1d521 7238
aee4e0db
UW		 7239 insn = next_insn;
7240 }
7241
7242 /* Free pool list. */
9db1d521 7243
b2ccb744 7244 while (pool_list)
9db1d521 7245 {
b2ccb744
UW		 7246 struct constant_pool *next = pool_list->next;
7247 s390_free_pool (pool_list);
7248 pool_list = next;
9db1d521 7249 }
9db1d521
HP		 7250}
7251
faeb9bb6 7252/* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
416cf582
UW		 7253
7254void
ef4bddc2 7255s390_output_pool_entry (rtx exp, machine_mode mode, unsigned int align)
416cf582
UW		 7256{
7257 REAL_VALUE_TYPE r;
7258
7259 switch (GET_MODE_CLASS (mode))
7260 {
7261 case MODE_FLOAT:
4dc19cc0 7262 case MODE_DECIMAL_FLOAT:
8d933e31 7263 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
416cf582
UW		 7264
7265 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
7266 assemble_real (r, mode, align);
7267 break;
7268
7269 case MODE_INT:
faeb9bb6 7270 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
a7fe25b8 7271 mark_symbol_refs_as_used (exp);
416cf582
UW		 7272 break;
7273
7274 default:
8d933e31 7275 gcc_unreachable ();
416cf582
UW		 7276 }
7277}
7278
7279
ab96de7e
AS		 7280/* Return an RTL expression representing the value of the return address
7281 for the frame COUNT steps up from the current frame. FRAME is the
7282 frame pointer of that frame. */
b2ccb744 7283
ab96de7e
AS		 7284rtx
7285s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
b2ccb744 7286{
ab96de7e
AS		 7287 int offset;
7288 rtx addr;
aee4e0db 7289
ab96de7e 7290 /* Without backchain, we fail for all but the current frame. */
c3cc6b78 7291
ab96de7e
AS		 7292 if (!TARGET_BACKCHAIN && count > 0)
7293 return NULL_RTX;
c3cc6b78 7294
ab96de7e
AS		 7295 /* For the current frame, we need to make sure the initial
7296 value of RETURN_REGNUM is actually saved. */
c3cc6b78 7297
ab96de7e 7298 if (count == 0)
c3cc6b78 7299 {
7bcebb25
AK		 7300 /* On non-z architectures branch splitting could overwrite r14. */
7301 if (TARGET_CPU_ZARCH)
7302 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
7303 else
7304 {
7305 cfun_frame_layout.save_return_addr_p = true;
7306 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
7307 }
ab96de7e 7308 }
c3cc6b78 7309
ab96de7e 7310 if (TARGET_PACKED_STACK)
9602b6a1 7311 offset = -2 * UNITS_PER_LONG;
ab96de7e 7312 else
9602b6a1 7313 offset = RETURN_REGNUM * UNITS_PER_LONG;
c3cc6b78 7314
0a81f074 7315 addr = plus_constant (Pmode, frame, offset);
ab96de7e
AS		 7316 addr = memory_address (Pmode, addr);
7317 return gen_rtx_MEM (Pmode, addr);
7318}
c3cc6b78 7319
ab96de7e
AS		 7320/* Return an RTL expression representing the back chain stored in
7321 the current stack frame. */
545d16ff 7322
ab96de7e
AS		 7323rtx
7324s390_back_chain_rtx (void)
7325{
7326 rtx chain;
545d16ff 7327
ab96de7e 7328 gcc_assert (TARGET_BACKCHAIN);
545d16ff 7329
ab96de7e 7330 if (TARGET_PACKED_STACK)
0a81f074 7331 chain = plus_constant (Pmode, stack_pointer_rtx,
9602b6a1 7332 STACK_POINTER_OFFSET - UNITS_PER_LONG);
ab96de7e
AS		 7333 else
7334 chain = stack_pointer_rtx;
545d16ff 7335
ab96de7e
AS		 7336 chain = gen_rtx_MEM (Pmode, chain);
7337 return chain;
7338}
c3cc6b78 7339
ab96de7e
AS		 7340/* Find first call clobbered register unused in a function.
7341 This could be used as base register in a leaf function
7342 or for holding the return address before epilogue. */
c3cc6b78 7343
ab96de7e
AS		 7344static int
7345find_unused_clobbered_reg (void)
7346{
7347 int i;
7348 for (i = 0; i < 6; i++)
6fb5fa3c 7349 if (!df_regs_ever_live_p (i))
ab96de7e
AS		 7350 return i;
7351 return 0;
7352}
c3cc6b78 7353
7bcebb25 7354
f4aa3848 7355/* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7bcebb25
AK		 7356 clobbered hard regs in SETREG. */
7357
7358static void
7bc980e1 7359s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
7bcebb25 7360{
6455a49e 7361 char *regs_ever_clobbered = (char *)data;
7bcebb25 7362 unsigned int i, regno;
ef4bddc2 7363 machine_mode mode = GET_MODE (setreg);
7bcebb25
AK		 7364
7365 if (GET_CODE (setreg) == SUBREG)
7366 {
7367 rtx inner = SUBREG_REG (setreg);
5a3fe9b6 7368 if (!GENERAL_REG_P (inner) && !FP_REG_P (inner))
7bcebb25
AK		 7369 return;
7370 regno = subreg_regno (setreg);
7371 }
5a3fe9b6 7372 else if (GENERAL_REG_P (setreg) || FP_REG_P (setreg))
7bcebb25
AK		 7373 regno = REGNO (setreg);
7374 else
7375 return;
7376
7377 for (i = regno;
7378 i < regno + HARD_REGNO_NREGS (regno, mode);
7379 i++)
7380 regs_ever_clobbered[i] = 1;
7381}
7382
7383/* Walks through all basic blocks of the current function looking
7384 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7385 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7386 each of those regs. */
7387
7388static void
6455a49e 7389s390_regs_ever_clobbered (char regs_ever_clobbered[])
7bcebb25
AK		 7390{
7391 basic_block cur_bb;
775c43d3 7392 rtx_insn *cur_insn;
7bcebb25
AK		 7393 unsigned int i;
7394
6455a49e 7395 memset (regs_ever_clobbered, 0, 32);
7bcebb25
AK		 7396
7397 /* For non-leaf functions we have to consider all call clobbered regs to be
7398 clobbered. */
416ff32e 7399 if (!crtl->is_leaf)
7bcebb25 7400 {
5a3fe9b6 7401 for (i = 0; i < 32; i++)
7bcebb25
AK		 7402 regs_ever_clobbered[i] = call_really_used_regs[i];
7403 }
7404
7405 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7406 this work is done by liveness analysis (mark_regs_live_at_end).
7407 Special care is needed for functions containing landing pads. Landing pads
7408 may use the eh registers, but the code which sets these registers is not
7409 contained in that function. Hence s390_regs_ever_clobbered is not able to
7410 deal with this automatically. */
e3b5732b 7411 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
7bcebb25 7412 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
f4aa3848
AK		 7413 if (crtl->calls_eh_return
7414 || (cfun->machine->has_landing_pad_p
6fb5fa3c 7415 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
297a777d 7416 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
7bcebb25
AK		 7417
7418 /* For nonlocal gotos all call-saved registers have to be saved.
7419 This flag is also set for the unwinding code in libgcc.
7420 See expand_builtin_unwind_init. For regs_ever_live this is done by
7421 reload. */
6455a49e 7422 if (crtl->saves_all_registers)
5a3fe9b6 7423 for (i = 0; i < 32; i++)
7bcebb25
AK		 7424 if (!call_really_used_regs[i])
7425 regs_ever_clobbered[i] = 1;
7426
11cd3bed 7427 FOR_EACH_BB_FN (cur_bb, cfun)
7bcebb25
AK		 7428 {
7429 FOR_BB_INSNS (cur_bb, cur_insn)
7430 {
6455a49e
AK		 7431 rtx pat;
7432
7433 if (!INSN_P (cur_insn))
7434 continue;
7435
7436 pat = PATTERN (cur_insn);
7437
7438 /* Ignore GPR restore insns. */
7439 if (epilogue_completed && RTX_FRAME_RELATED_P (cur_insn))
7440 {
7441 if (GET_CODE (pat) == SET
7442 && GENERAL_REG_P (SET_DEST (pat)))
7443 {
7444 /* lgdr */
7445 if (GET_MODE (SET_SRC (pat)) == DImode
7446 && FP_REG_P (SET_SRC (pat)))
7447 continue;
7448
7449 /* l / lg */
7450 if (GET_CODE (SET_SRC (pat)) == MEM)
7451 continue;
7452 }
7453
7454 /* lm / lmg */
7455 if (GET_CODE (pat) == PARALLEL
7456 && load_multiple_operation (pat, VOIDmode))
7457 continue;
7458 }
7459
7460 note_stores (pat,
7461 s390_reg_clobbered_rtx,
7462 regs_ever_clobbered);
7bcebb25
AK		 7463 }
7464 }
7465}
7466
f4aa3848
AK		 7467/* Determine the frame area which actually has to be accessed
7468 in the function epilogue. The values are stored at the
ab96de7e 7469 given pointers AREA_BOTTOM (address of the lowest used stack
f4aa3848 7470 address) and AREA_TOP (address of the first item which does
ab96de7e 7471 not belong to the stack frame). */
545d16ff 7472
ab96de7e
AS		 7473static void
7474s390_frame_area (int *area_bottom, int *area_top)
7475{
7476 int b, t;
545d16ff 7477
ab96de7e
AS		 7478 b = INT_MAX;
7479 t = INT_MIN;
adf39f8f
AK		 7480
7481 if (cfun_frame_layout.first_restore_gpr != -1)
7482 {
7483 b = (cfun_frame_layout.gprs_offset
9602b6a1 7484 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
adf39f8f 7485 t = b + (cfun_frame_layout.last_restore_gpr
9602b6a1 7486 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
adf39f8f
AK		 7487 }
7488
7489 if (TARGET_64BIT && cfun_save_high_fprs_p)
7490 {
7491 b = MIN (b, cfun_frame_layout.f8_offset);
7492 t = MAX (t, (cfun_frame_layout.f8_offset
7493 + cfun_frame_layout.high_fprs * 8));
7494 }
7495
7496 if (!TARGET_64BIT)
b89b22fc 7497 {
2cf4c39e 7498 if (cfun_fpr_save_p (FPR4_REGNUM))
adf39f8f 7499 {
b89b22fc
AK		 7500 b = MIN (b, cfun_frame_layout.f4_offset);
7501 t = MAX (t, cfun_frame_layout.f4_offset + 8);
adf39f8f 7502 }
2cf4c39e 7503 if (cfun_fpr_save_p (FPR6_REGNUM))
b89b22fc
AK		 7504 {
7505 b = MIN (b, cfun_frame_layout.f4_offset + 8);
7506 t = MAX (t, cfun_frame_layout.f4_offset + 16);
7507 }
7508 }
adf39f8f
AK		 7509 *area_bottom = b;
7510 *area_top = t;
7511}
6455a49e
AK		 7512/* Update gpr_save_slots in the frame layout trying to make use of
7513 FPRs as GPR save slots.
7514 This is a helper routine of s390_register_info. */
4023fb28
UW		 7515
7516static void
6455a49e 7517s390_register_info_gprtofpr ()
4023fb28 7518{
6455a49e 7519 int save_reg_slot = FPR0_REGNUM;
4023fb28 7520 int i, j;
4023fb28 7521
6455a49e
AK		 7522 if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf)
7523 return;
7bcebb25 7524
6455a49e 7525 for (i = 15; i >= 6; i--)
5a3fe9b6 7526 {
6455a49e
AK		 7527 if (cfun_gpr_save_slot (i) == 0)
7528 continue;
36c0bd4f 7529
6455a49e
AK		 7530 /* Advance to the next FP register which can be used as a
7531 GPR save slot. */
7532 while ((!call_really_used_regs[save_reg_slot]
7533 || df_regs_ever_live_p (save_reg_slot)
7534 || cfun_fpr_save_p (save_reg_slot))
7535 && FP_REGNO_P (save_reg_slot))
7536 save_reg_slot++;
7537 if (!FP_REGNO_P (save_reg_slot))
7538 {
7539 /* We only want to use ldgr/lgdr if we can get rid of
7540 stm/lm entirely. So undo the gpr slot allocation in
7541 case we ran out of FPR save slots. */
7542 for (j = 6; j <= 15; j++)
7543 if (FP_REGNO_P (cfun_gpr_save_slot (j)))
7544 cfun_gpr_save_slot (j) = -1;
7545 break;
36c0bd4f 7546 }
6455a49e 7547 cfun_gpr_save_slot (i) = save_reg_slot++;
5a3fe9b6 7548 }
6455a49e 7549}
5a3fe9b6 7550
6455a49e
AK		 7551/* Set the bits in fpr_bitmap for FPRs which need to be saved due to
7552 stdarg.
7553 This is a helper routine for s390_register_info. */
7bcebb25 7554
6455a49e
AK		 7555static void
7556s390_register_info_stdarg_fpr ()
7557{
7558 int i;
7559 int min_fpr;
7560 int max_fpr;
7561
7562 /* Save the FP argument regs for stdarg. f0, f2 for 31 bit and
7563 f0-f4 for 64 bit. */
7564 if (!cfun->stdarg
7565 || !TARGET_HARD_FLOAT
7566 || !cfun->va_list_fpr_size
7567 || crtl->args.info.fprs >= FP_ARG_NUM_REG)
7568 return;
7569
7570 min_fpr = crtl->args.info.fprs;
7571 max_fpr = min_fpr + cfun->va_list_fpr_size;
7572 if (max_fpr > FP_ARG_NUM_REG)
7573 max_fpr = FP_ARG_NUM_REG;
7574
6455a49e
AK		 7575 for (i = min_fpr; i < max_fpr; i++)
7576 cfun_set_fpr_save (i + FPR0_REGNUM);
7577}
7578
7579/* Reserve the GPR save slots for GPRs which need to be saved due to
7580 stdarg.
7581 This is a helper routine for s390_register_info. */
7582
7583static void
7584s390_register_info_stdarg_gpr ()
7585{
7586 int i;
7587 int min_gpr;
7588 int max_gpr;
7589
7590 if (!cfun->stdarg
7591 || !cfun->va_list_gpr_size
7592 || crtl->args.info.gprs >= GP_ARG_NUM_REG)
7593 return;
7594
7595 min_gpr = crtl->args.info.gprs;
7596 max_gpr = min_gpr + cfun->va_list_gpr_size;
7597 if (max_gpr > GP_ARG_NUM_REG)
7598 max_gpr = GP_ARG_NUM_REG;
7599
7600 for (i = min_gpr; i < max_gpr; i++)
7601 cfun_gpr_save_slot (2 + i) = -1;
7602}
7603
7604/* The GPR and FPR save slots in cfun->machine->frame_layout are set
7605 for registers which need to be saved in function prologue.
7606 This function can be used until the insns emitted for save/restore
7607 of the regs are visible in the RTL stream. */
7608
7609static void
7610s390_register_info ()
7611{
7612 int i, j;
7613 char clobbered_regs[32];
7614
7615 gcc_assert (!epilogue_completed);
7616
7617 if (reload_completed)
7618 /* After reload we rely on our own routine to determine which
7619 registers need saving. */
7620 s390_regs_ever_clobbered (clobbered_regs);
7621 else
7622 /* During reload we use regs_ever_live as a base since reload
7623 does changes in there which we otherwise would not be aware
7624 of. */
7625 for (i = 0; i < 32; i++)
7626 clobbered_regs[i] = df_regs_ever_live_p (i);
7627
7628 for (i = 0; i < 32; i++)
7629 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i];
7630
7631 /* Mark the call-saved FPRs which need to be saved.
7632 This needs to be done before checking the special GPRs since the
7633 stack pointer usage depends on whether high FPRs have to be saved
7634 or not. */
7635 cfun_frame_layout.fpr_bitmap = 0;
7636 cfun_frame_layout.high_fprs = 0;
7637 for (i = FPR0_REGNUM; i <= FPR15_REGNUM; i++)
7638 if (clobbered_regs[i] && !call_really_used_regs[i])
7639 {
7640 cfun_set_fpr_save (i);
7641 if (i >= FPR8_REGNUM)
7642 cfun_frame_layout.high_fprs++;
7643 }
c3cc6b78 7644
b767fc11 7645 if (flag_pic)
f4aa3848 7646 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
6455a49e 7647 |= !!df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
91086990 7648
f4aa3848 7649 clobbered_regs[BASE_REGNUM]
e2df5c1d 7650 |= (cfun->machine->base_reg
6455a49e 7651 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
91086990 7652
6455a49e
AK		 7653 clobbered_regs[HARD_FRAME_POINTER_REGNUM]
7654 |= !!frame_pointer_needed;
7655
7656 /* On pre z900 machines this might take until machine dependent
7657 reorg to decide.
7658 save_return_addr_p will only be set on non-zarch machines so
7659 there is no risk that r14 goes into an FPR instead of a stack
7660 slot. */
7bcebb25 7661 clobbered_regs[RETURN_REGNUM]
416ff32e 7662 |= (!crtl->is_leaf
dc4477f5 7663 || TARGET_TPF_PROFILING
e2df5c1d
UW		 7664 || cfun->machine->split_branches_pending_p
7665 || cfun_frame_layout.save_return_addr_p
6455a49e 7666 || crtl->calls_eh_return);
91086990 7667
7bcebb25 7668 clobbered_regs[STACK_POINTER_REGNUM]
416ff32e 7669 |= (!crtl->is_leaf
e2df5c1d
UW		 7670 || TARGET_TPF_PROFILING
7671 || cfun_save_high_fprs_p
7672 || get_frame_size () > 0
36c0bd4f 7673 || (reload_completed && cfun_frame_layout.frame_size > 0)
6455a49e
AK		 7674 || cfun->calls_alloca);
7675
7676 memset (cfun_frame_layout.gpr_save_slots, 0, 16);
7bcebb25 7677
b767fc11 7678 for (i = 6; i < 16; i++)
6455a49e
AK		 7679 if (clobbered_regs[i])
7680 cfun_gpr_save_slot (i) = -1;
c3cc6b78 7681
6455a49e
AK		 7682 s390_register_info_stdarg_fpr ();
7683 s390_register_info_gprtofpr ();
fb3712f6 7684
6455a49e
AK		 7685 /* First find the range of GPRs to be restored. Vararg regs don't
7686 need to be restored so we do it before assigning slots to the
7687 vararg GPRs. */
7688 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7689 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7690 cfun_frame_layout.first_restore_gpr = (i == 16) ? -1 : i;
7691 cfun_frame_layout.last_restore_gpr = (i == 16) ? -1 : j;
fb3712f6 7692
6455a49e
AK		 7693 /* stdarg functions might need to save GPRs 2 to 6. This might
7694 override the GPR->FPR save decision made above for r6 since
7695 vararg regs must go to the stack. */
7696 s390_register_info_stdarg_gpr ();
f4aa3848 7697
6455a49e
AK		 7698 /* Now the range of GPRs which need saving. */
7699 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7700 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7701 cfun_frame_layout.first_save_gpr = (i == 16) ? -1 : i;
7702 cfun_frame_layout.last_save_gpr = (i == 16) ? -1 : j;
7703}
c3cc6b78 7704
6455a49e
AK		 7705/* This function is called by s390_optimize_prologue in order to get
7706 rid of unnecessary GPR save/restore instructions. The register info
7707 for the GPRs is re-computed and the ranges are re-calculated. */
29a79fcf 7708
6455a49e
AK		 7709static void
7710s390_optimize_register_info ()
7711{
7712 char clobbered_regs[32];
7713 int i, j;
29a79fcf 7714
6455a49e
AK		 7715 gcc_assert (epilogue_completed);
7716 gcc_assert (!cfun->machine->split_branches_pending_p);
b767fc11 7717
6455a49e 7718 s390_regs_ever_clobbered (clobbered_regs);
29a79fcf 7719
6455a49e
AK		 7720 for (i = 0; i < 32; i++)
7721 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i];
29a79fcf 7722
6455a49e
AK		 7723 /* There is still special treatment needed for cases invisible to
7724 s390_regs_ever_clobbered. */
7725 clobbered_regs[RETURN_REGNUM]
7726 |= (TARGET_TPF_PROFILING
7727 /* When expanding builtin_return_addr in ESA mode we do not
7728 know whether r14 will later be needed as scratch reg when
7729 doing branch splitting. So the builtin always accesses the
7730 r14 save slot and we need to stick to the save/restore
7731 decision for r14 even if it turns out that it didn't get
7732 clobbered. */
7733 || cfun_frame_layout.save_return_addr_p
7734 || crtl->calls_eh_return);
7735
7736 memset (cfun_frame_layout.gpr_save_slots, 0, 6);
7737
7738 for (i = 6; i < 16; i++)
7739 if (!clobbered_regs[i])
7740 cfun_gpr_save_slot (i) = 0;
7741
7742 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7743 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7744 cfun_frame_layout.first_restore_gpr = (i == 16) ? -1 : i;
7745 cfun_frame_layout.last_restore_gpr = (i == 16) ? -1 : j;
7746
7747 s390_register_info_stdarg_gpr ();
7748
7749 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7750 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7751 cfun_frame_layout.first_save_gpr = (i == 16) ? -1 : i;
7752 cfun_frame_layout.last_save_gpr = (i == 16) ? -1 : j;
adf39f8f
AK		 7753}
7754
91086990 7755/* Fill cfun->machine with info about frame of current function. */
adf39f8f
AK		 7756
7757static void
91086990 7758s390_frame_info (void)
adf39f8f 7759{
74129172 7760 HOST_WIDE_INT lowest_offset;
adf39f8f 7761
6455a49e
AK		 7762 cfun_frame_layout.first_save_gpr_slot = cfun_frame_layout.first_save_gpr;
7763 cfun_frame_layout.last_save_gpr_slot = cfun_frame_layout.last_save_gpr;
7764
7765 /* The va_arg builtin uses a constant distance of 16 *
7766 UNITS_PER_LONG (r0-r15) to reach the FPRs from the reg_save_area
7767 pointer. So even if we are going to save the stack pointer in an
7768 FPR we need the stack space in order to keep the offsets
7769 correct. */
7770 if (cfun->stdarg && cfun_save_arg_fprs_p)
7771 {
7772 cfun_frame_layout.last_save_gpr_slot = STACK_POINTER_REGNUM;
7773
7774 if (cfun_frame_layout.first_save_gpr_slot == -1)
7775 cfun_frame_layout.first_save_gpr_slot = STACK_POINTER_REGNUM;
7776 }
7777
adf39f8f 7778 cfun_frame_layout.frame_size = get_frame_size ();
adf39f8f 7779 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
c85ce869 7780 fatal_error ("total size of local variables exceeds architecture limit");
f4aa3848 7781
b3d31392 7782 if (!TARGET_PACKED_STACK)
adf39f8f 7783 {
74129172 7784 /* Fixed stack layout. */
adf39f8f 7785 cfun_frame_layout.backchain_offset = 0;
9602b6a1 7786 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
adf39f8f
AK		 7787 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7788 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
fb3712f6 7789 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
9602b6a1 7790 * UNITS_PER_LONG);
adf39f8f 7791 }
74129172 7792 else if (TARGET_BACKCHAIN)
adf39f8f 7793 {
74129172
AK		 7794 /* Kernel stack layout - packed stack, backchain, no float */
7795 gcc_assert (TARGET_SOFT_FLOAT);
adf39f8f 7796 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
9602b6a1 7797 - UNITS_PER_LONG);
74129172
AK		 7798
7799 /* The distance between the backchain and the return address
7800 save slot must not change. So we always need a slot for the
7801 stack pointer which resides in between. */
7802 cfun_frame_layout.last_save_gpr_slot = STACK_POINTER_REGNUM;
7803
f4aa3848 7804 cfun_frame_layout.gprs_offset
74129172 7805 = cfun_frame_layout.backchain_offset - cfun_gprs_save_area_size;
f4aa3848 7806
74129172
AK		 7807 /* FPRs will not be saved. Nevertheless pick sane values to
7808 keep area calculations valid. */
7809 cfun_frame_layout.f0_offset =
7810 cfun_frame_layout.f4_offset =
7811 cfun_frame_layout.f8_offset = cfun_frame_layout.gprs_offset;
adf39f8f 7812 }
74129172 7813 else
adf39f8f 7814 {
e179df83
AK		 7815 int num_fprs;
7816
74129172 7817 /* Packed stack layout without backchain. */
f4aa3848 7818
e179df83
AK		 7819 /* With stdarg FPRs need their dedicated slots. */
7820 num_fprs = (TARGET_64BIT && cfun->stdarg ? 2
7821 : (cfun_fpr_save_p (FPR4_REGNUM) +
7822 cfun_fpr_save_p (FPR6_REGNUM)));
7823 cfun_frame_layout.f4_offset = STACK_POINTER_OFFSET - 8 * num_fprs;
7824
7825 num_fprs = (cfun->stdarg ? 2
7826 : (cfun_fpr_save_p (FPR0_REGNUM)
7827 + cfun_fpr_save_p (FPR2_REGNUM)));
7828 cfun_frame_layout.f0_offset = cfun_frame_layout.f4_offset - 8 * num_fprs;
f4aa3848
AK		 7829
7830 cfun_frame_layout.gprs_offset
adf39f8f 7831 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
74129172
AK		 7832
7833 cfun_frame_layout.f8_offset = (cfun_frame_layout.gprs_offset
7834 - cfun_frame_layout.high_fprs * 8);
adf39f8f
AK		 7835 }
7836
74129172
AK		 7837 if (cfun_save_high_fprs_p)
7838 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7839
7840 if (!crtl->is_leaf)
7841 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7842
7843 /* In the following cases we have to allocate a STACK_POINTER_OFFSET
7844 sized area at the bottom of the stack. This is required also for
7845 leaf functions. When GCC generates a local stack reference it
7846 will always add STACK_POINTER_OFFSET to all these references. */
416ff32e 7847 if (crtl->is_leaf
adf39f8f
AK		 7848 && !TARGET_TPF_PROFILING
7849 && cfun_frame_layout.frame_size == 0
6455a49e 7850 && !cfun->calls_alloca)
adf39f8f
AK		 7851 return;
7852
74129172
AK		 7853 /* Calculate the number of bytes we have used in our own register
7854 save area. With the packed stack layout we can re-use the
7855 remaining bytes for normal stack elements. */
adf39f8f 7856
74129172
AK		 7857 if (TARGET_PACKED_STACK)
7858 lowest_offset = MIN (MIN (cfun_frame_layout.f0_offset,
7859 cfun_frame_layout.f4_offset),
7860 cfun_frame_layout.gprs_offset);
7861 else
7862 lowest_offset = 0;
f4aa3848 7863
74129172
AK		 7864 if (TARGET_BACKCHAIN)
7865 lowest_offset = MIN (lowest_offset, cfun_frame_layout.backchain_offset);
f4aa3848 7866
74129172 7867 cfun_frame_layout.frame_size += STACK_POINTER_OFFSET - lowest_offset;
adf39f8f 7868
74129172
AK		 7869 /* If under 31 bit an odd number of gprs has to be saved we have to
7870 adjust the frame size to sustain 8 byte alignment of stack
7871 frames. */
7872 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7873 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7874 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
4023fb28
UW		 7875}
7876
91086990
UW		 7877/* Generate frame layout. Fills in register and frame data for the current
7878 function in cfun->machine. This routine can be called multiple times;
7879 it will re-do the complete frame layout every time. */
4023fb28 7880
91086990
UW		 7881static void
7882s390_init_frame_layout (void)
9db1d521 7883{
91086990
UW		 7884 HOST_WIDE_INT frame_size;
7885 int base_used;
6455a49e
AK		 7886
7887 gcc_assert (!reload_completed);
b767fc11 7888
91086990
UW		 7889 /* On S/390 machines, we may need to perform branch splitting, which
7890 will require both base and return address register. We have no
7891 choice but to assume we're going to need them until right at the
7892 end of the machine dependent reorg phase. */
7893 if (!TARGET_CPU_ZARCH)
7894 cfun->machine->split_branches_pending_p = true;
7895
7896 do
7897 {
7898 frame_size = cfun_frame_layout.frame_size;
7899
7900 /* Try to predict whether we'll need the base register. */
7901 base_used = cfun->machine->split_branches_pending_p
e3b5732b 7902 || crtl->uses_const_pool
20f04e65
AK		 7903 || (!DISP_IN_RANGE (frame_size)
7904 && !CONST_OK_FOR_K (frame_size));
91086990
UW		 7905
7906 /* Decide which register to use as literal pool base. In small
7907 leaf functions, try to use an unused call-clobbered register
7908 as base register to avoid save/restore overhead. */
7909 if (!base_used)
7910 cfun->machine->base_reg = NULL_RTX;
416ff32e 7911 else if (crtl->is_leaf && !df_regs_ever_live_p (5))
91086990
UW		 7912 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7913 else
7914 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
adf39f8f 7915
6455a49e 7916 s390_register_info ();
91086990
UW		 7917 s390_frame_info ();
7918 }
7919 while (frame_size != cfun_frame_layout.frame_size);
9db1d521
HP		 7920}
7921
5a3fe9b6
AK		 7922/* Remove the FPR clobbers from a tbegin insn if it can be proven that
7923 the TX is nonescaping. A transaction is considered escaping if
7924 there is at least one path from tbegin returning CC0 to the
7925 function exit block without an tend.
7926
7927 The check so far has some limitations:
7928 - only single tbegin/tend BBs are supported
7929 - the first cond jump after tbegin must separate the CC0 path from ~CC0
7930 - when CC is copied to a GPR and the CC0 check is done with the GPR
7931 this is not supported
7932*/
7933
7934static void
7935s390_optimize_nonescaping_tx (void)
7936{
7937 const unsigned int CC0 = 1 << 3;
7938 basic_block tbegin_bb = NULL;
7939 basic_block tend_bb = NULL;
7940 basic_block bb;
775c43d3 7941 rtx_insn *insn;
5a3fe9b6
AK		 7942 bool result = true;
7943 int bb_index;
775c43d3 7944 rtx_insn *tbegin_insn = NULL;
5a3fe9b6
AK		 7945
7946 if (!cfun->machine->tbegin_p)
7947 return;
7948
0cae8d31 7949 for (bb_index = 0; bb_index < n_basic_blocks_for_fn (cfun); bb_index++)
5a3fe9b6 7950 {
06e28de2 7951 bb = BASIC_BLOCK_FOR_FN (cfun, bb_index);
5a3fe9b6 7952
2561451d
AK		 7953 if (!bb)
7954 continue;
7955
5a3fe9b6
AK		 7956 FOR_BB_INSNS (bb, insn)
7957 {
7958 rtx ite, cc, pat, target;
7959 unsigned HOST_WIDE_INT mask;
7960
7961 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
7962 continue;
7963
7964 pat = PATTERN (insn);
7965
7966 if (GET_CODE (pat) == PARALLEL)
7967 pat = XVECEXP (pat, 0, 0);
7968
7969 if (GET_CODE (pat) != SET
7970 || GET_CODE (SET_SRC (pat)) != UNSPEC_VOLATILE)
7971 continue;
7972
7973 if (XINT (SET_SRC (pat), 1) == UNSPECV_TBEGIN)
7974 {
b32d5189 7975 rtx_insn *tmp;
5a3fe9b6
AK		 7976
7977 tbegin_insn = insn;
7978
7979 /* Just return if the tbegin doesn't have clobbers. */
7980 if (GET_CODE (PATTERN (insn)) != PARALLEL)
7981 return;
7982
7983 if (tbegin_bb != NULL)
7984 return;
7985
7986 /* Find the next conditional jump. */
7987 for (tmp = NEXT_INSN (insn);
7988 tmp != NULL_RTX;
7989 tmp = NEXT_INSN (tmp))
7990 {
7991 if (reg_set_p (gen_rtx_REG (CCmode, CC_REGNUM), tmp))
7992 return;
7993 if (!JUMP_P (tmp))
7994 continue;
7995
7996 ite = SET_SRC (PATTERN (tmp));
7997 if (GET_CODE (ite) != IF_THEN_ELSE)
7998 continue;
7999
8000 cc = XEXP (XEXP (ite, 0), 0);
8001 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc))
8002 || GET_MODE (cc) != CCRAWmode
8003 || GET_CODE (XEXP (XEXP (ite, 0), 1)) != CONST_INT)
8004 return;
8005
8006 if (bb->succs->length () != 2)
8007 return;
8008
8009 mask = INTVAL (XEXP (XEXP (ite, 0), 1));
8010 if (GET_CODE (XEXP (ite, 0)) == NE)
8011 mask ^= 0xf;
8012
8013 if (mask == CC0)
8014 target = XEXP (ite, 1);
8015 else if (mask == (CC0 ^ 0xf))
8016 target = XEXP (ite, 2);
8017 else
8018 return;
8019
8020 {
8021 edge_iterator ei;
8022 edge e1, e2;
8023
8024 ei = ei_start (bb->succs);
8025 e1 = ei_safe_edge (ei);
8026 ei_next (&ei);
8027 e2 = ei_safe_edge (ei);
8028
8029 if (e2->flags & EDGE_FALLTHRU)
8030 {
8031 e2 = e1;
8032 e1 = ei_safe_edge (ei);
8033 }
8034
8035 if (!(e1->flags & EDGE_FALLTHRU))
8036 return;
8037
8038 tbegin_bb = (target == pc_rtx) ? e1->dest : e2->dest;
8039 }
8040 if (tmp == BB_END (bb))
8041 break;
8042 }
8043 }
8044
8045 if (XINT (SET_SRC (pat), 1) == UNSPECV_TEND)
8046 {
8047 if (tend_bb != NULL)
8048 return;
8049 tend_bb = bb;
8050 }
8051 }
8052 }
8053
8054 /* Either we successfully remove the FPR clobbers here or we are not
8055 able to do anything for this TX. Both cases don't qualify for
8056 another look. */
8057 cfun->machine->tbegin_p = false;
8058
8059 if (tbegin_bb == NULL || tend_bb == NULL)
8060 return;
8061
8062 calculate_dominance_info (CDI_POST_DOMINATORS);
8063 result = dominated_by_p (CDI_POST_DOMINATORS, tbegin_bb, tend_bb);
8064 free_dominance_info (CDI_POST_DOMINATORS);
8065
8066 if (!result)
8067 return;
8068
2561451d
AK		 8069 PATTERN (tbegin_insn) = gen_rtx_PARALLEL (VOIDmode,
8070 gen_rtvec (2,
8071 XVECEXP (PATTERN (tbegin_insn), 0, 0),
8072 XVECEXP (PATTERN (tbegin_insn), 0, 1)));
5a3fe9b6
AK		 8073 INSN_CODE (tbegin_insn) = -1;
8074 df_insn_rescan (tbegin_insn);
8075
8076 return;
8077}
8078
74aa8b4b
AK		 8079/* Return true if it is legal to put a value with MODE into REGNO. */
8080
8081bool
ef4bddc2 8082s390_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
74aa8b4b
AK		 8083{
8084 switch (REGNO_REG_CLASS (regno))
8085 {
8086 case FP_REGS:
8087 if (REGNO_PAIR_OK (regno, mode))
8088 {
8089 if (mode == SImode || mode == DImode)
8090 return true;
8091
8092 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
8093 return true;
8094 }
8095 break;
8096 case ADDR_REGS:
8097 if (FRAME_REGNO_P (regno) && mode == Pmode)
8098 return true;
8099
8100 /* fallthrough */
8101 case GENERAL_REGS:
8102 if (REGNO_PAIR_OK (regno, mode))
8103 {
9602b6a1 8104 if (TARGET_ZARCH
4dc19cc0 8105 || (mode != TFmode && mode != TCmode && mode != TDmode))
74aa8b4b 8106 return true;
f4aa3848 8107 }
74aa8b4b
AK		 8108 break;
8109 case CC_REGS:
8110 if (GET_MODE_CLASS (mode) == MODE_CC)
8111 return true;
8112 break;
8113 case ACCESS_REGS:
8114 if (REGNO_PAIR_OK (regno, mode))
8115 {
8116 if (mode == SImode || mode == Pmode)
8117 return true;
8118 }
8119 break;
8120 default:
8121 return false;
8122 }
f4aa3848 8123
74aa8b4b
AK		 8124 return false;
8125}
8126
7633f08e
UW		 8127/* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
8128
8129bool
8130s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
8131{
8132 /* Once we've decided upon a register to use as base register, it must
8133 no longer be used for any other purpose. */
8134 if (cfun->machine->base_reg)
8135 if (REGNO (cfun->machine->base_reg) == old_reg
8136 || REGNO (cfun->machine->base_reg) == new_reg)
8137 return false;
8138
6455a49e
AK		 8139 /* Prevent regrename from using call-saved regs which haven't
8140 actually been saved. This is necessary since regrename assumes
8141 the backend save/restore decisions are based on
8142 df_regs_ever_live. Since we have our own routine we have to tell
8143 regrename manually about it. */
8144 if (GENERAL_REGNO_P (new_reg)
8145 && !call_really_used_regs[new_reg]
8146 && cfun_gpr_save_slot (new_reg) == 0)
8147 return false;
8148
8149 return true;
8150}
8151
8152/* Return nonzero if register REGNO can be used as a scratch register
8153 in peephole2. */
8154
8155static bool
8156s390_hard_regno_scratch_ok (unsigned int regno)
8157{
8158 /* See s390_hard_regno_rename_ok. */
8159 if (GENERAL_REGNO_P (regno)
8160 && !call_really_used_regs[regno]
8161 && cfun_gpr_save_slot (regno) == 0)
8162 return false;
8163
7633f08e
UW		 8164 return true;
8165}
8166
74aa8b4b 8167/* Maximum number of registers to represent a value of mode MODE
0a2aaacc 8168 in a register of class RCLASS. */
74aa8b4b 8169
c4100a35 8170int
ef4bddc2 8171s390_class_max_nregs (enum reg_class rclass, machine_mode mode)
74aa8b4b 8172{
0a2aaacc 8173 switch (rclass)
74aa8b4b
AK		 8174 {
8175 case FP_REGS:
8176 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
8177 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
8178 else
8179 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
8180 case ACCESS_REGS:
8181 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
8182 default:
8183 break;
8184 }
8185 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8186}
8187
3597e113
VM		 8188/* Return true if we use LRA instead of reload pass. */
8189static bool
8190s390_lra_p (void)
8191{
8192 return s390_lra_flag;
8193}
8194
91086990
UW		 8195/* Return true if register FROM can be eliminated via register TO. */
8196
7b5cbb57
AS		 8197static bool
8198s390_can_eliminate (const int from, const int to)
91086990 8199{
7633f08e
UW		 8200 /* On zSeries machines, we have not marked the base register as fixed.
8201 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
8202 If a function requires the base register, we say here that this
8203 elimination cannot be performed. This will cause reload to free
8204 up the base register (as if it were fixed). On the other hand,
8205 if the current function does *not* require the base register, we
8206 say here the elimination succeeds, which in turn allows reload
8207 to allocate the base register for any other purpose. */
8208 if (from == BASE_REGNUM && to == BASE_REGNUM)
8209 {
8210 if (TARGET_CPU_ZARCH)
8211 {
8212 s390_init_frame_layout ();
8213 return cfun->machine->base_reg == NULL_RTX;
8214 }
8215
8216 return false;
8217 }
8218
8219 /* Everything else must point into the stack frame. */
91086990
UW		 8220 gcc_assert (to == STACK_POINTER_REGNUM
8221 || to == HARD_FRAME_POINTER_REGNUM);
8222
8223 gcc_assert (from == FRAME_POINTER_REGNUM
8224 || from == ARG_POINTER_REGNUM
8225 || from == RETURN_ADDRESS_POINTER_REGNUM);
8226
8227 /* Make sure we actually saved the return address. */
8228 if (from == RETURN_ADDRESS_POINTER_REGNUM)
e3b5732b
JH		 8229 if (!crtl->calls_eh_return
8230 && !cfun->stdarg
91086990
UW		 8231 && !cfun_frame_layout.save_return_addr_p)
8232 return false;
8233
8234 return true;
8235}
8236
8237/* Return offset between register FROM and TO initially after prolog. */
a38e09bc
AK		 8238
8239HOST_WIDE_INT
91086990 8240s390_initial_elimination_offset (int from, int to)
a38e09bc 8241{
91086990 8242 HOST_WIDE_INT offset;
a38e09bc 8243
91086990
UW		 8244 /* ??? Why are we called for non-eliminable pairs? */
8245 if (!s390_can_eliminate (from, to))
8246 return 0;
8247
8248 switch (from)
8249 {
8250 case FRAME_POINTER_REGNUM:
f4aa3848 8251 offset = (get_frame_size()
63296cb1 8252 + STACK_POINTER_OFFSET
38173d38 8253 + crtl->outgoing_args_size);
91086990 8254 break;
adf39f8f 8255
91086990
UW		 8256 case ARG_POINTER_REGNUM:
8257 s390_init_frame_layout ();
8258 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
8259 break;
8260
8261 case RETURN_ADDRESS_POINTER_REGNUM:
8262 s390_init_frame_layout ();
6455a49e
AK		 8263
8264 if (cfun_frame_layout.first_save_gpr_slot == -1)
8265 {
8266 /* If it turns out that for stdarg nothing went into the reg
8267 save area we also do not need the return address
8268 pointer. */
8269 if (cfun->stdarg && !cfun_save_arg_fprs_p)
8270 return 0;
8271
8272 gcc_unreachable ();
8273 }
8274
8275 /* In order to make the following work it is not necessary for
8276 r14 to have a save slot. It is sufficient if one other GPR
8277 got one. Since the GPRs are always stored without gaps we
8278 are able to calculate where the r14 save slot would
8279 reside. */
8280 offset = (cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset +
8281 (RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot) *
8282 UNITS_PER_LONG);
91086990
UW		 8283 break;
8284
7633f08e
UW		 8285 case BASE_REGNUM:
8286 offset = 0;
8287 break;
8288
91086990
UW		 8289 default:
8290 gcc_unreachable ();
8291 }
8292
8293 return offset;
a38e09bc
AK		 8294}
8295
4023fb28 8296/* Emit insn to save fpr REGNUM at offset OFFSET relative
c7453384 8297 to register BASE. Return generated insn. */
994fe660 8298
9db1d521 8299static rtx
9c808aad 8300save_fpr (rtx base, int offset, int regnum)
9db1d521 8301{
4023fb28 8302 rtx addr;
0a81f074 8303 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
dcc9eb26
AK		 8304
8305 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
8306 set_mem_alias_set (addr, get_varargs_alias_set ());
8307 else
8308 set_mem_alias_set (addr, get_frame_alias_set ());
9db1d521 8309
4023fb28
UW		 8310 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
8311}
9db1d521 8312
4023fb28 8313/* Emit insn to restore fpr REGNUM from offset OFFSET relative
c7453384 8314 to register BASE. Return generated insn. */
9db1d521 8315
4023fb28 8316static rtx
9c808aad 8317restore_fpr (rtx base, int offset, int regnum)
4023fb28
UW		 8318{
8319 rtx addr;
0a81f074 8320 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
dcc9eb26 8321 set_mem_alias_set (addr, get_frame_alias_set ());
9db1d521 8322
4023fb28 8323 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
9db1d521
HP		 8324}
8325
75707b28
JJ		 8326/* Return true if REGNO is a global register, but not one
8327 of the special ones that need to be saved/restored in anyway. */
8328
8329static inline bool
8330global_not_special_regno_p (int regno)
8331{
8332 return (global_regs[regno]
8333 /* These registers are special and need to be
8334 restored in any case. */
8335 && !(regno == STACK_POINTER_REGNUM
8336 || regno == RETURN_REGNUM
8337 || regno == BASE_REGNUM
8338 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
8339}
8340
c3cc6b78 8341/* Generate insn to save registers FIRST to LAST into
c7453384 8342 the register save area located at offset OFFSET
c3cc6b78 8343 relative to register BASE. */
9db1d521 8344
c3cc6b78 8345static rtx
9c808aad 8346save_gprs (rtx base, int offset, int first, int last)
9db1d521 8347{
c3cc6b78
UW		 8348 rtx addr, insn, note;
8349 int i;
8350
0a81f074 8351 addr = plus_constant (Pmode, base, offset);
c3cc6b78 8352 addr = gen_rtx_MEM (Pmode, addr);
dcc9eb26
AK		 8353
8354 set_mem_alias_set (addr, get_frame_alias_set ());
c3cc6b78
UW		 8355
8356 /* Special-case single register. */
8357 if (first == last)
8358 {
8359 if (TARGET_64BIT)
8360 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
8361 else
8362 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
8363
75707b28
JJ		 8364 if (!global_not_special_regno_p (first))
8365 RTX_FRAME_RELATED_P (insn) = 1;
c3cc6b78
UW		 8366 return insn;
8367 }
8368
8369
8370 insn = gen_store_multiple (addr,
8371 gen_rtx_REG (Pmode, first),
8372 GEN_INT (last - first + 1));
8373
e3b5732b 8374 if (first <= 6 && cfun->stdarg)
dcc9eb26
AK		 8375 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8376 {
8377 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
f4aa3848 8378
dcc9eb26
AK		 8379 if (first + i <= 6)
8380 set_mem_alias_set (mem, get_varargs_alias_set ());
8381 }
c3cc6b78
UW		 8382
8383 /* We need to set the FRAME_RELATED flag on all SETs
8384 inside the store-multiple pattern.
8385
8386 However, we must not emit DWARF records for registers 2..5
c7453384 8387 if they are stored for use by variable arguments ...
c3cc6b78 8388
a4d05547 8389 ??? Unfortunately, it is not enough to simply not the
c3cc6b78
UW		 8390 FRAME_RELATED flags for those SETs, because the first SET
8391 of the PARALLEL is always treated as if it had the flag
8392 set, even if it does not. Therefore we emit a new pattern
8393 without those registers as REG_FRAME_RELATED_EXPR note. */
8394
75707b28 8395 if (first >= 6 && !global_not_special_regno_p (first))
c3cc6b78
UW		 8396 {
8397 rtx pat = PATTERN (insn);
8398
8399 for (i = 0; i < XVECLEN (pat, 0); i++)
75707b28
JJ		 8400 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
8401 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
8402 0, i)))))
c3cc6b78
UW		 8403 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
8404
8405 RTX_FRAME_RELATED_P (insn) = 1;
8406 }
8407 else if (last >= 6)
8408 {
75707b28
JJ		 8409 int start;
8410
8411 for (start = first >= 6 ? first : 6; start <= last; start++)
8412 if (!global_not_special_regno_p (start))
8413 break;
8414
8415 if (start > last)
8416 return insn;
8417
0a81f074
RS		 8418 addr = plus_constant (Pmode, base,
8419 offset + (start - first) * UNITS_PER_LONG);
6455a49e
AK		 8420
8421 if (start == last)
8422 {
8423 if (TARGET_64BIT)
8424 note = gen_movdi (gen_rtx_MEM (Pmode, addr),
8425 gen_rtx_REG (Pmode, start));
8426 else
8427 note = gen_movsi (gen_rtx_MEM (Pmode, addr),
8428 gen_rtx_REG (Pmode, start));
8429 note = PATTERN (note);
8430
8431 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
8432 RTX_FRAME_RELATED_P (insn) = 1;
8433
8434 return insn;
8435 }
8436
c7453384 8437 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
75707b28
JJ		 8438 gen_rtx_REG (Pmode, start),
8439 GEN_INT (last - start + 1));
c3cc6b78
UW		 8440 note = PATTERN (note);
8441
bbbbb16a 8442 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
c3cc6b78
UW		 8443
8444 for (i = 0; i < XVECLEN (note, 0); i++)
75707b28
JJ		 8445 if (GET_CODE (XVECEXP (note, 0, i)) == SET
8446 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
8447 0, i)))))
c3cc6b78
UW		 8448 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
8449
8450 RTX_FRAME_RELATED_P (insn) = 1;
8451 }
8452
8453 return insn;
4023fb28 8454}
9db1d521 8455
c3cc6b78 8456/* Generate insn to restore registers FIRST to LAST from
c7453384 8457 the register save area located at offset OFFSET
c3cc6b78 8458 relative to register BASE. */
9db1d521 8459
c3cc6b78 8460static rtx
9c808aad 8461restore_gprs (rtx base, int offset, int first, int last)
4023fb28 8462{
c3cc6b78
UW		 8463 rtx addr, insn;
8464
0a81f074 8465 addr = plus_constant (Pmode, base, offset);
c3cc6b78 8466 addr = gen_rtx_MEM (Pmode, addr);
dcc9eb26 8467 set_mem_alias_set (addr, get_frame_alias_set ());
c3cc6b78
UW		 8468
8469 /* Special-case single register. */
8470 if (first == last)
8471 {
8472 if (TARGET_64BIT)
8473 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
8474 else
8475 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
8476
6455a49e 8477 RTX_FRAME_RELATED_P (insn) = 1;
c3cc6b78
UW		 8478 return insn;
8479 }
8480
8481 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
8482 addr,
8483 GEN_INT (last - first + 1));
6455a49e 8484 RTX_FRAME_RELATED_P (insn) = 1;
c3cc6b78 8485 return insn;
4023fb28 8486}
9db1d521 8487
585539a1 8488/* Return insn sequence to load the GOT register. */
fd7643fb
UW		 8489
8490static GTY(()) rtx got_symbol;
775c43d3 8491rtx_insn *
585539a1 8492s390_load_got (void)
fd7643fb 8493{
775c43d3 8494 rtx_insn *insns;
585539a1 8495
68c0ef75
AK		 8496 /* We cannot use pic_offset_table_rtx here since we use this
8497 function also for non-pic if __tls_get_offset is called and in
8498 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
8499 aren't usable. */
8500 rtx got_rtx = gen_rtx_REG (Pmode, 12);
8501
fd7643fb
UW		 8502 if (!got_symbol)
8503 {
8504 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8505 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
8506 }
8507
585539a1
UW		 8508 start_sequence ();
8509
9e8327e3 8510 if (TARGET_CPU_ZARCH)
fd7643fb 8511 {
68c0ef75 8512 emit_move_insn (got_rtx, got_symbol);
fd7643fb
UW		 8513 }
8514 else
8515 {
585539a1 8516 rtx offset;
fd7643fb 8517
c7453384 8518 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
fd7643fb
UW		 8519 UNSPEC_LTREL_OFFSET);
8520 offset = gen_rtx_CONST (Pmode, offset);
8521 offset = force_const_mem (Pmode, offset);
8522
68c0ef75 8523 emit_move_insn (got_rtx, offset);
fd7643fb 8524
c7453384 8525 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
fd7643fb 8526 UNSPEC_LTREL_BASE);
68c0ef75 8527 offset = gen_rtx_PLUS (Pmode, got_rtx, offset);
fd7643fb 8528
68c0ef75 8529 emit_move_insn (got_rtx, offset);
fd7643fb 8530 }
585539a1
UW		 8531
8532 insns = get_insns ();
8533 end_sequence ();
8534 return insns;
fd7643fb
UW		 8535}
8536
12959abe
AK		 8537/* This ties together stack memory (MEM with an alias set of frame_alias_set)
8538 and the change to the stack pointer. */
8539
8540static void
8541s390_emit_stack_tie (void)
8542{
8543 rtx mem = gen_frame_mem (BLKmode,
8544 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
8545
8546 emit_insn (gen_stack_tie (mem));
8547}
8548
6455a49e
AK		 8549/* Copy GPRS into FPR save slots. */
8550
8551static void
8552s390_save_gprs_to_fprs (void)
8553{
8554 int i;
8555
8556 if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf)
8557 return;
8558
8559 for (i = 6; i < 16; i++)
8560 {
8561 if (FP_REGNO_P (cfun_gpr_save_slot (i)))
8562 {
775c43d3 8563 rtx_insn *insn =
6455a49e
AK		 8564 emit_move_insn (gen_rtx_REG (DImode, cfun_gpr_save_slot (i)),
8565 gen_rtx_REG (DImode, i));
8566 RTX_FRAME_RELATED_P (insn) = 1;
8567 }
8568 }
8569}
8570
8571/* Restore GPRs from FPR save slots. */
8572
8573static void
8574s390_restore_gprs_from_fprs (void)
8575{
8576 int i;
8577
8578 if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf)
8579 return;
8580
8581 for (i = 6; i < 16; i++)
8582 {
8583 if (FP_REGNO_P (cfun_gpr_save_slot (i)))
8584 {
775c43d3 8585 rtx_insn *insn =
6455a49e
AK		 8586 emit_move_insn (gen_rtx_REG (DImode, i),
8587 gen_rtx_REG (DImode, cfun_gpr_save_slot (i)));
8588 df_set_regs_ever_live (i, true);
0621cf3c
RS		 8589 add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, i));
8590 if (i == STACK_POINTER_REGNUM)
8591 add_reg_note (insn, REG_CFA_DEF_CFA,
8592 plus_constant (Pmode, stack_pointer_rtx,
8593 STACK_POINTER_OFFSET));
6455a49e
AK		 8594 RTX_FRAME_RELATED_P (insn) = 1;
8595 }
8596 }
8597}
8598
9db1d521 8599
4099494d
RS		 8600/* A pass run immediately before shrink-wrapping and prologue and epilogue
8601 generation. */
8602
4099494d
RS		 8603namespace {
8604
8605const pass_data pass_data_s390_early_mach =
8606{
8607 RTL_PASS, /* type */
8608 "early_mach", /* name */
8609 OPTGROUP_NONE, /* optinfo_flags */
4099494d
RS		 8610 TV_MACH_DEP, /* tv_id */
8611 0, /* properties_required */
8612 0, /* properties_provided */
8613 0, /* properties_destroyed */
8614 0, /* todo_flags_start */
3bea341f 8615 ( TODO_df_verify | TODO_df_finish ), /* todo_flags_finish */
4099494d 8616};
585539a1 8617
4099494d
RS		 8618class pass_s390_early_mach : public rtl_opt_pass
8619{
8620public:
8621 pass_s390_early_mach (gcc::context *ctxt)
8622 : rtl_opt_pass (pass_data_s390_early_mach, ctxt)
8623 {}
8624
8625 /* opt_pass methods: */
be55bfe6 8626 virtual unsigned int execute (function *);
4099494d
RS		 8627
8628}; // class pass_s390_early_mach
8629
be55bfe6
TS		 8630unsigned int
8631pass_s390_early_mach::execute (function *fun)
8632{
775c43d3 8633 rtx_insn *insn;
be55bfe6
TS		 8634
8635 /* Try to get rid of the FPR clobbers. */
8636 s390_optimize_nonescaping_tx ();
8637
8638 /* Re-compute register info. */
8639 s390_register_info ();
8640
8641 /* If we're using a base register, ensure that it is always valid for
8642 the first non-prologue instruction. */
8643 if (fun->machine->base_reg)
8644 emit_insn_at_entry (gen_main_pool (fun->machine->base_reg));
8645
8646 /* Annotate all constant pool references to let the scheduler know
8647 they implicitly use the base register. */
8648 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8649 if (INSN_P (insn))
8650 {
8651 annotate_constant_pool_refs (&PATTERN (insn));
8652 df_insn_rescan (insn);
8653 }
8654 return 0;
8655}
8656
4099494d
RS		 8657} // anon namespace
8658
8659/* Expand the prologue into a bunch of separate insns. */
8660
8661void
8662s390_emit_prologue (void)
8663{
8664 rtx insn, addr;
8665 rtx temp_reg;
8666 int i;
8667 int offset;
8668 int next_fpr = 0;
585539a1 8669
c7453384
EC		 8670 /* Choose best register to use for temp use within prologue.
8671 See below for why TPF must use the register 1. */
8672
f4aa3848 8673 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
416ff32e 8674 && !crtl->is_leaf
7bcebb25 8675 && !TARGET_TPF_PROFILING)
4023fb28 8676 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
9db1d521 8677 else
4023fb28 8678 temp_reg = gen_rtx_REG (Pmode, 1);
9db1d521 8679
6455a49e
AK		 8680 s390_save_gprs_to_fprs ();
8681
4023fb28 8682 /* Save call saved gprs. */
adf39f8f 8683 if (cfun_frame_layout.first_save_gpr != -1)
2790879f 8684 {
f4aa3848
AK		 8685 insn = save_gprs (stack_pointer_rtx,
8686 cfun_frame_layout.gprs_offset +
9602b6a1 8687 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
fb3712f6 8688 - cfun_frame_layout.first_save_gpr_slot),
f4aa3848 8689 cfun_frame_layout.first_save_gpr,
2790879f
AK		 8690 cfun_frame_layout.last_save_gpr);
8691 emit_insn (insn);
8692 }
4023fb28 8693
5af2f3d3 8694 /* Dummy insn to mark literal pool slot. */
c7453384 8695
91086990
UW		 8696 if (cfun->machine->base_reg)
8697 emit_insn (gen_main_pool (cfun->machine->base_reg));
c7453384 8698
adf39f8f 8699 offset = cfun_frame_layout.f0_offset;
4023fb28 8700
adf39f8f 8701 /* Save f0 and f2. */
2cf4c39e 8702 for (i = FPR0_REGNUM; i <= FPR0_REGNUM + 1; i++)
adf39f8f 8703 {
b89b22fc 8704 if (cfun_fpr_save_p (i))
adf39f8f 8705 {
b89b22fc 8706 save_fpr (stack_pointer_rtx, offset, i);
adf39f8f
AK		 8707 offset += 8;
8708 }
e179df83
AK		 8709 else if (!TARGET_PACKED_STACK || cfun->stdarg)
8710 offset += 8;
adf39f8f 8711 }
9db1d521 8712
adf39f8f
AK		 8713 /* Save f4 and f6. */
8714 offset = cfun_frame_layout.f4_offset;
2cf4c39e 8715 for (i = FPR4_REGNUM; i <= FPR4_REGNUM + 1; i++)
adf39f8f 8716 {
b89b22fc 8717 if (cfun_fpr_save_p (i))
4023fb28 8718 {
b89b22fc 8719 insn = save_fpr (stack_pointer_rtx, offset, i);
adf39f8f
AK		 8720 offset += 8;
8721
e179df83
AK		 8722 /* If f4 and f6 are call clobbered they are saved due to
8723 stdargs and therefore are not frame related. */
b89b22fc 8724 if (!call_really_used_regs[i])
adf39f8f 8725 RTX_FRAME_RELATED_P (insn) = 1;
4023fb28 8726 }
e179df83 8727 else if (!TARGET_PACKED_STACK || call_really_used_regs[i])
adf39f8f
AK		 8728 offset += 8;
8729 }
8730
b3d31392 8731 if (TARGET_PACKED_STACK
adf39f8f
AK		 8732 && cfun_save_high_fprs_p
8733 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
8734 {
8735 offset = (cfun_frame_layout.f8_offset
8736 + (cfun_frame_layout.high_fprs - 1) * 8);
8737
2cf4c39e 8738 for (i = FPR15_REGNUM; i >= FPR8_REGNUM && offset >= 0; i--)
b89b22fc 8739 if (cfun_fpr_save_p (i))
adf39f8f 8740 {
b89b22fc 8741 insn = save_fpr (stack_pointer_rtx, offset, i);
f4aa3848 8742
adf39f8f
AK		 8743 RTX_FRAME_RELATED_P (insn) = 1;
8744 offset -= 8;
8745 }
8746 if (offset >= cfun_frame_layout.f8_offset)
b89b22fc 8747 next_fpr = i;
adf39f8f 8748 }
f4aa3848 8749
b3d31392 8750 if (!TARGET_PACKED_STACK)
2cf4c39e 8751 next_fpr = cfun_save_high_fprs_p ? FPR15_REGNUM : 0;
9db1d521 8752
a11e0df4 8753 if (flag_stack_usage_info)
5c779305
AK		 8754 current_function_static_stack_size = cfun_frame_layout.frame_size;
8755
4023fb28 8756 /* Decrement stack pointer. */
9db1d521 8757
adf39f8f 8758 if (cfun_frame_layout.frame_size > 0)
4023fb28 8759 {
adf39f8f 8760 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
bbbbb16a 8761 rtx real_frame_off;
9db1d521 8762
d75f90f1
AK		 8763 if (s390_stack_size)
8764 {
690e7b63 8765 HOST_WIDE_INT stack_guard;
d75f90f1 8766
690e7b63
AK		 8767 if (s390_stack_guard)
8768 stack_guard = s390_stack_guard;
d75f90f1 8769 else
690e7b63
AK		 8770 {
8771 /* If no value for stack guard is provided the smallest power of 2
8772 larger than the current frame size is chosen. */
8773 stack_guard = 1;
8774 while (stack_guard < cfun_frame_layout.frame_size)
8775 stack_guard <<= 1;
8776 }
d75f90f1 8777
690e7b63
AK		 8778 if (cfun_frame_layout.frame_size >= s390_stack_size)
8779 {
cabbe12a 8780 warning (0, "frame size of function %qs is %wd"
690e7b63 8781 " bytes exceeding user provided stack limit of "
cabbe12a 8782 "%d bytes. "
690e7b63
AK		 8783 "An unconditional trap is added.",
8784 current_function_name(), cfun_frame_layout.frame_size,
8785 s390_stack_size);
8786 emit_insn (gen_trap ());
8787 }
8788 else
8789 {
a3e7e012
AK		 8790 /* stack_guard has to be smaller than s390_stack_size.
8791 Otherwise we would emit an AND with zero which would
8792 not match the test under mask pattern. */
8793 if (stack_guard >= s390_stack_size)
8794 {
f137aa63 8795 warning (0, "frame size of function %qs is %wd"
a3e7e012
AK		 8796 " bytes which is more than half the stack size. "
8797 "The dynamic check would not be reliable. "
8798 "No check emitted for this function.",
8799 current_function_name(),
8800 cfun_frame_layout.frame_size);
8801 }
690e7b63 8802 else
a3e7e012
AK		 8803 {
8804 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
8805 & ~(stack_guard - 1));
8806
8807 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
8808 GEN_INT (stack_check_mask));
8809 if (TARGET_64BIT)
8810 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
8811 t, const0_rtx),
8812 t, const0_rtx, const0_rtx));
8813 else
8814 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
8815 t, const0_rtx),
8816 t, const0_rtx, const0_rtx));
8817 }
690e7b63 8818 }
d75f90f1
AK		 8819 }
8820
f4aa3848 8821 if (s390_warn_framesize > 0
d75f90f1 8822 && cfun_frame_layout.frame_size >= s390_warn_framesize)
f137aa63 8823 warning (0, "frame size of %qs is %wd bytes",
d75f90f1
AK		 8824 current_function_name (), cfun_frame_layout.frame_size);
8825
8826 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
d4ee4d25 8827 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
d75f90f1 8828
4023fb28 8829 /* Save incoming stack pointer into temp reg. */
66480e91 8830 if (TARGET_BACKCHAIN || next_fpr)
adf39f8f 8831 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
c7453384 8832
fae778eb 8833 /* Subtract frame size from stack pointer. */
4023fb28 8834
d3632d41
UW		 8835 if (DISP_IN_RANGE (INTVAL (frame_off)))
8836 {
c7453384 8837 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
f4aa3848 8838 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
9c808aad 8839 frame_off));
d3632d41
UW		 8840 insn = emit_insn (insn);
8841 }
8842 else
8843 {
b5c67a49 8844 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
d3632d41
UW		 8845 frame_off = force_const_mem (Pmode, frame_off);
8846
8847 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
585539a1 8848 annotate_constant_pool_refs (&PATTERN (insn));
d3632d41 8849 }
4023fb28 8850
4023fb28 8851 RTX_FRAME_RELATED_P (insn) = 1;
bbbbb16a
ILT		 8852 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8853 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8854 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8855 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8856 real_frame_off)));
4023fb28
UW		 8857
8858 /* Set backchain. */
c7453384 8859
66480e91 8860 if (TARGET_BACKCHAIN)
9db1d521 8861 {
adf39f8f 8862 if (cfun_frame_layout.backchain_offset)
f4aa3848 8863 addr = gen_rtx_MEM (Pmode,
0a81f074 8864 plus_constant (Pmode, stack_pointer_rtx,
adf39f8f
AK		 8865 cfun_frame_layout.backchain_offset));
8866 else
f4aa3848 8867 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
dcc9eb26 8868 set_mem_alias_set (addr, get_frame_alias_set ());
4023fb28 8869 insn = emit_insn (gen_move_insn (addr, temp_reg));
9db1d521 8870 }
7d798969 8871
8f4f502f 8872 /* If we support non-call exceptions (e.g. for Java),
7d798969
UW		 8873 we need to make sure the backchain pointer is set up
8874 before any possibly trapping memory access. */
8f4f502f 8875 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
7d798969
UW		 8876 {
8877 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
c41c1387 8878 emit_clobber (addr);
7d798969 8879 }
4023fb28 8880 }
9db1d521 8881
4023fb28 8882 /* Save fprs 8 - 15 (64 bit ABI). */
c7453384 8883
adf39f8f 8884 if (cfun_save_high_fprs_p && next_fpr)
4023fb28 8885 {
12959abe
AK		 8886 /* If the stack might be accessed through a different register
8887 we have to make sure that the stack pointer decrement is not
8888 moved below the use of the stack slots. */
8889 s390_emit_stack_tie ();
8890
f4aa3848 8891 insn = emit_insn (gen_add2_insn (temp_reg,
adf39f8f
AK		 8892 GEN_INT (cfun_frame_layout.f8_offset)));
8893
8894 offset = 0;
9db1d521 8895
2cf4c39e 8896 for (i = FPR8_REGNUM; i <= next_fpr; i++)
b89b22fc 8897 if (cfun_fpr_save_p (i))
4023fb28 8898 {
0a81f074 8899 rtx addr = plus_constant (Pmode, stack_pointer_rtx,
adf39f8f
AK		 8900 cfun_frame_layout.frame_size
8901 + cfun_frame_layout.f8_offset
8902 + offset);
f4aa3848 8903
adf39f8f
AK		 8904 insn = save_fpr (temp_reg, offset, i);
8905 offset += 8;
4023fb28 8906 RTX_FRAME_RELATED_P (insn) = 1;
bbbbb16a
ILT		 8907 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8908 gen_rtx_SET (VOIDmode,
8909 gen_rtx_MEM (DFmode, addr),
8910 gen_rtx_REG (DFmode, i)));
4023fb28
UW		 8911 }
8912 }
c7453384 8913
4023fb28 8914 /* Set frame pointer, if needed. */
c7453384 8915
29742ba4 8916 if (frame_pointer_needed)
4023fb28
UW		 8917 {
8918 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8919 RTX_FRAME_RELATED_P (insn) = 1;
8920 }
9db1d521 8921
4023fb28 8922 /* Set up got pointer, if needed. */
c7453384 8923
6fb5fa3c 8924 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
585539a1 8925 {
775c43d3 8926 rtx_insn *insns = s390_load_got ();
585539a1 8927
b32d5189 8928 for (rtx_insn *insn = insns; insn; insn = NEXT_INSN (insn))
6fb5fa3c 8929 annotate_constant_pool_refs (&PATTERN (insn));
585539a1
UW		 8930
8931 emit_insn (insns);
8932 }
c7453384 8933
3839e36a 8934 if (TARGET_TPF_PROFILING)
c7453384
EC		 8935 {
8936 /* Generate a BAS instruction to serve as a function
8937 entry intercept to facilitate the use of tracing
2f7e5a0d
EC		 8938 algorithms located at the branch target. */
8939 emit_insn (gen_prologue_tpf ());
c7453384
EC		 8940
8941 /* Emit a blockage here so that all code
8942 lies between the profiling mechanisms. */
8943 emit_insn (gen_blockage ());
8944 }
4023fb28 8945}
9db1d521 8946
b1c9bc51 8947/* Expand the epilogue into a bunch of separate insns. */
9db1d521 8948
4023fb28 8949void
ed9676cf 8950s390_emit_epilogue (bool sibcall)
4023fb28 8951{
75707b28 8952 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
5d4d885c 8953 int area_bottom, area_top, offset = 0;
adf39f8f 8954 int next_offset;
4023fb28 8955 rtvec p;
7333171f 8956 int i;
9db1d521 8957
3839e36a 8958 if (TARGET_TPF_PROFILING)
c7453384
EC		 8959 {
8960
8961 /* Generate a BAS instruction to serve as a function
8962 entry intercept to facilitate the use of tracing
2f7e5a0d 8963 algorithms located at the branch target. */
c7453384 8964
c7453384
EC		 8965 /* Emit a blockage here so that all code
8966 lies between the profiling mechanisms. */
8967 emit_insn (gen_blockage ());
8968
2f7e5a0d 8969 emit_insn (gen_epilogue_tpf ());
c7453384
EC		 8970 }
8971
4023fb28 8972 /* Check whether to use frame or stack pointer for restore. */
9db1d521 8973
f4aa3848 8974 frame_pointer = (frame_pointer_needed
adf39f8f 8975 ? hard_frame_pointer_rtx : stack_pointer_rtx);
9db1d521 8976
adf39f8f 8977 s390_frame_area (&area_bottom, &area_top);
9db1d521 8978
c7453384 8979 /* Check whether we can access the register save area.
4023fb28 8980 If not, increment the frame pointer as required. */
9db1d521 8981
4023fb28
UW		 8982 if (area_top <= area_bottom)
8983 {
8984 /* Nothing to restore. */
8985 }
adf39f8f
AK		 8986 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8987 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
4023fb28
UW		 8988 {
8989 /* Area is in range. */
adf39f8f 8990 offset = cfun_frame_layout.frame_size;
4023fb28
UW		 8991 }
8992 else
8993 {
75707b28 8994 rtx insn, frame_off, cfa;
9db1d521 8995
c7453384 8996 offset = area_bottom < 0 ? -area_bottom : 0;
adf39f8f 8997 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
9db1d521 8998
75707b28
JJ		 8999 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
9000 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
d3632d41
UW		 9001 if (DISP_IN_RANGE (INTVAL (frame_off)))
9002 {
c7453384 9003 insn = gen_rtx_SET (VOIDmode, frame_pointer,
d3632d41
UW		 9004 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
9005 insn = emit_insn (insn);
9006 }
9007 else
9008 {
b5c67a49 9009 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
d3632d41 9010 frame_off = force_const_mem (Pmode, frame_off);
9db1d521 9011
d3632d41 9012 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
585539a1 9013 annotate_constant_pool_refs (&PATTERN (insn));
d3632d41 9014 }
75707b28
JJ		 9015 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
9016 RTX_FRAME_RELATED_P (insn) = 1;
4023fb28 9017 }
9db1d521 9018
4023fb28
UW		 9019 /* Restore call saved fprs. */
9020
9021 if (TARGET_64BIT)
9db1d521 9022 {
adf39f8f
AK		 9023 if (cfun_save_high_fprs_p)
9024 {
9025 next_offset = cfun_frame_layout.f8_offset;
2cf4c39e 9026 for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++)
adf39f8f 9027 {
b89b22fc 9028 if (cfun_fpr_save_p (i))
adf39f8f
AK		 9029 {
9030 restore_fpr (frame_pointer,
9031 offset + next_offset, i);
75707b28
JJ		 9032 cfa_restores
9033 = alloc_reg_note (REG_CFA_RESTORE,
9034 gen_rtx_REG (DFmode, i), cfa_restores);
adf39f8f
AK		 9035 next_offset += 8;
9036 }
9037 }
9038 }
f4aa3848 9039
9db1d521
HP		 9040 }
9041 else
9042 {
adf39f8f 9043 next_offset = cfun_frame_layout.f4_offset;
b89b22fc 9044 /* f4, f6 */
2cf4c39e 9045 for (i = FPR4_REGNUM; i <= FPR4_REGNUM + 1; i++)
adf39f8f 9046 {
b89b22fc 9047 if (cfun_fpr_save_p (i))
adf39f8f
AK		 9048 {
9049 restore_fpr (frame_pointer,
9050 offset + next_offset, i);
75707b28
JJ		 9051 cfa_restores
9052 = alloc_reg_note (REG_CFA_RESTORE,
9053 gen_rtx_REG (DFmode, i), cfa_restores);
adf39f8f
AK		 9054 next_offset += 8;
9055 }
b3d31392 9056 else if (!TARGET_PACKED_STACK)
adf39f8f
AK		 9057 next_offset += 8;
9058 }
f4aa3848 9059
4023fb28 9060 }
9db1d521 9061
4023fb28
UW		 9062 /* Return register. */
9063
c7453384 9064 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
4023fb28
UW		 9065
9066 /* Restore call saved gprs. */
9067
adf39f8f 9068 if (cfun_frame_layout.first_restore_gpr != -1)
4023fb28 9069 {
c3cc6b78 9070 rtx insn, addr;
1447dc69
HP		 9071 int i;
9072
c7453384 9073 /* Check for global register and save them
1447dc69
HP		 9074 to stack location from where they get restored. */
9075
adf39f8f
AK		 9076 for (i = cfun_frame_layout.first_restore_gpr;
9077 i <= cfun_frame_layout.last_restore_gpr;
1447dc69
HP		 9078 i++)
9079 {
75707b28 9080 if (global_not_special_regno_p (i))
1447dc69 9081 {
0a81f074 9082 addr = plus_constant (Pmode, frame_pointer,
f4aa3848 9083 offset + cfun_frame_layout.gprs_offset
fb3712f6 9084 + (i - cfun_frame_layout.first_save_gpr_slot)
9602b6a1 9085 * UNITS_PER_LONG);
1447dc69 9086 addr = gen_rtx_MEM (Pmode, addr);
dcc9eb26 9087 set_mem_alias_set (addr, get_frame_alias_set ());
1447dc69 9088 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
c7453384 9089 }
75707b28
JJ		 9090 else
9091 cfa_restores
9092 = alloc_reg_note (REG_CFA_RESTORE,
9093 gen_rtx_REG (Pmode, i), cfa_restores);
1447dc69 9094 }
4023fb28 9095
ed9676cf 9096 if (! sibcall)
9db1d521 9097 {
ed9676cf 9098 /* Fetch return address from stack before load multiple,
db716bde
AK		 9099 this will do good for scheduling.
9100
9101 Only do this if we already decided that r14 needs to be
9102 saved to a stack slot. (And not just because r14 happens to
9103 be in between two GPRs which need saving.) Otherwise it
9104 would be difficult to take that decision back in
9105 s390_optimize_prologue. */
9106 if (cfun_gpr_save_slot (RETURN_REGNUM) == -1)
ed9676cf
AK		 9107 {
9108 int return_regnum = find_unused_clobbered_reg();
9109 if (!return_regnum)
9110 return_regnum = 4;
9111 return_reg = gen_rtx_REG (Pmode, return_regnum);
38899e29 9112
0a81f074 9113 addr = plus_constant (Pmode, frame_pointer,
adf39f8f 9114 offset + cfun_frame_layout.gprs_offset
f4aa3848 9115 + (RETURN_REGNUM
fb3712f6 9116 - cfun_frame_layout.first_save_gpr_slot)
9602b6a1 9117 * UNITS_PER_LONG);
ed9676cf 9118 addr = gen_rtx_MEM (Pmode, addr);
dcc9eb26 9119 set_mem_alias_set (addr, get_frame_alias_set ());
ed9676cf 9120 emit_move_insn (return_reg, addr);
db716bde
AK		 9121
9122 /* Once we did that optimization we have to make sure
9123 s390_optimize_prologue does not try to remove the
9124 store of r14 since we will not be able to find the
9125 load issued here. */
9126 cfun_frame_layout.save_return_addr_p = true;
ed9676cf 9127 }
9db1d521 9128 }
4023fb28 9129
adf39f8f
AK		 9130 insn = restore_gprs (frame_pointer,
9131 offset + cfun_frame_layout.gprs_offset
f4aa3848 9132 + (cfun_frame_layout.first_restore_gpr
fb3712f6 9133 - cfun_frame_layout.first_save_gpr_slot)
9602b6a1 9134 * UNITS_PER_LONG,
adf39f8f
AK		 9135 cfun_frame_layout.first_restore_gpr,
9136 cfun_frame_layout.last_restore_gpr);
75707b28
JJ		 9137 insn = emit_insn (insn);
9138 REG_NOTES (insn) = cfa_restores;
9139 add_reg_note (insn, REG_CFA_DEF_CFA,
0a81f074
RS		 9140 plus_constant (Pmode, stack_pointer_rtx,
9141 STACK_POINTER_OFFSET));
75707b28 9142 RTX_FRAME_RELATED_P (insn) = 1;
4023fb28 9143 }
9db1d521 9144
6455a49e
AK		 9145 s390_restore_gprs_from_fprs ();
9146
ed9676cf
AK		 9147 if (! sibcall)
9148 {
c7453384 9149
ed9676cf 9150 /* Return to caller. */
38899e29 9151
ed9676cf 9152 p = rtvec_alloc (2);
38899e29 9153
3810076b 9154 RTVEC_ELT (p, 0) = ret_rtx;
ed9676cf
AK		 9155 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
9156 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
9157 }
9db1d521
HP		 9158}
9159
177bc204
RS		 9160/* Implement TARGET_SET_UP_BY_PROLOGUE. */
9161
9162static void
9163s300_set_up_by_prologue (hard_reg_set_container *regs)
9164{
9165 if (cfun->machine->base_reg
9166 && !call_really_used_regs[REGNO (cfun->machine->base_reg)])
9167 SET_HARD_REG_BIT (regs->set, REGNO (cfun->machine->base_reg));
9168}
9169
9170/* Return true if the function can use simple_return to return outside
9171 of a shrink-wrapped region. At present shrink-wrapping is supported
9172 in all cases. */
9173
9174bool
9175s390_can_use_simple_return_insn (void)
9176{
9177 return true;
9178}
9179
9180/* Return true if the epilogue is guaranteed to contain only a return
9181 instruction and if a direct return can therefore be used instead.
9182 One of the main advantages of using direct return instructions
9183 is that we can then use conditional returns. */
9184
9185bool
9186s390_can_use_return_insn (void)
9187{
9188 int i;
9189
9190 if (!reload_completed)
9191 return false;
9192
9193 if (crtl->profile)
9194 return false;
9195
9196 if (TARGET_TPF_PROFILING)
9197 return false;
9198
9199 for (i = 0; i < 16; i++)
9200 if (cfun_gpr_save_slot (i))
9201 return false;
9202
6e77facf
AK		 9203 /* For 31 bit this is not covered by the frame_size check below
9204 since f4, f6 are saved in the register save area without needing
9205 additional stack space. */
9206 if (!TARGET_64BIT
9207 && (cfun_fpr_save_p (FPR4_REGNUM) || cfun_fpr_save_p (FPR6_REGNUM)))
9208 return false;
9209
177bc204
RS		 9210 if (cfun->machine->base_reg
9211 && !call_really_used_regs[REGNO (cfun->machine->base_reg)])
9212 return false;
9213
9214 return cfun_frame_layout.frame_size == 0;
9215}
9db1d521 9216
c7453384 9217/* Return the size in bytes of a function argument of
994fe660
UW		 9218 type TYPE and/or mode MODE. At least one of TYPE or
9219 MODE must be specified. */
9db1d521
HP		 9220
9221static int
ef4bddc2 9222s390_function_arg_size (machine_mode mode, const_tree type)
9db1d521
HP		 9223{
9224 if (type)
9225 return int_size_in_bytes (type);
9226
d65f7478 9227 /* No type info available for some library calls ... */
9db1d521
HP		 9228 if (mode != BLKmode)
9229 return GET_MODE_SIZE (mode);
9230
9231 /* If we have neither type nor mode, abort */
8d933e31 9232 gcc_unreachable ();
9db1d521
HP		 9233}
9234
82b1c974
UW		 9235/* Return true if a function argument of type TYPE and mode MODE
9236 is to be passed in a floating-point register, if available. */
9237
9238static bool
ef4bddc2 9239s390_function_arg_float (machine_mode mode, const_tree type)
82b1c974 9240{
8c17530e
UW		 9241 int size = s390_function_arg_size (mode, type);
9242 if (size > 8)
9243 return false;
9244
82b1c974
UW		 9245 /* Soft-float changes the ABI: no floating-point registers are used. */
9246 if (TARGET_SOFT_FLOAT)
9247 return false;
9248
9249 /* No type info available for some library calls ... */
9250 if (!type)
4dc19cc0 9251 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
82b1c974
UW		 9252
9253 /* The ABI says that record types with a single member are treated
9254 just like that member would be. */
9255 while (TREE_CODE (type) == RECORD_TYPE)
9256 {
9257 tree field, single = NULL_TREE;
9258
910ad8de 9259 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
82b1c974
UW		 9260 {
9261 if (TREE_CODE (field) != FIELD_DECL)
9262 continue;
9263
9264 if (single == NULL_TREE)
9265 single = TREE_TYPE (field);
9266 else
9267 return false;
9268 }
9269
9270 if (single == NULL_TREE)
9271 return false;
9272 else
9273 type = single;
9274 }
9275
9276 return TREE_CODE (type) == REAL_TYPE;
9277}
9278
8c17530e
UW		 9279/* Return true if a function argument of type TYPE and mode MODE
9280 is to be passed in an integer register, or a pair of integer
9281 registers, if available. */
9282
9283static bool
ef4bddc2 9284s390_function_arg_integer (machine_mode mode, const_tree type)
8c17530e
UW		 9285{
9286 int size = s390_function_arg_size (mode, type);
9287 if (size > 8)
9288 return false;
9289
9290 /* No type info available for some library calls ... */
9291 if (!type)
9292 return GET_MODE_CLASS (mode) == MODE_INT
4dc19cc0 9293 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8c17530e
UW		 9294
9295 /* We accept small integral (and similar) types. */
9296 if (INTEGRAL_TYPE_P (type)
38899e29 9297 || POINTER_TYPE_P (type)
0d697034 9298 || TREE_CODE (type) == NULLPTR_TYPE
8c17530e
UW		 9299 || TREE_CODE (type) == OFFSET_TYPE
9300 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
9301 return true;
9302
9303 /* We also accept structs of size 1, 2, 4, 8 that are not
38899e29 9304 passed in floating-point registers. */
8c17530e
UW		 9305 if (AGGREGATE_TYPE_P (type)
9306 && exact_log2 (size) >= 0
9307 && !s390_function_arg_float (mode, type))
9308 return true;
9309
9310 return false;
9311}
9312
994fe660
UW		 9313/* Return 1 if a function argument of type TYPE and mode MODE
9314 is to be passed by reference. The ABI specifies that only
9315 structures of size 1, 2, 4, or 8 bytes are passed by value,
9316 all other structures (and complex numbers) are passed by
9317 reference. */
9318
8cd5a4e0 9319static bool
d5cc9181 9320s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
ef4bddc2 9321 machine_mode mode, const_tree type,
8cd5a4e0 9322 bool named ATTRIBUTE_UNUSED)
9db1d521
HP		 9323{
9324 int size = s390_function_arg_size (mode, type);
8c17530e
UW		 9325 if (size > 8)
9326 return true;
9db1d521
HP		 9327
9328 if (type)
9329 {
8c17530e 9330 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
9db1d521
HP		 9331 return 1;
9332
8c17530e
UW		 9333 if (TREE_CODE (type) == COMPLEX_TYPE
9334 || TREE_CODE (type) == VECTOR_TYPE)
9db1d521
HP		 9335 return 1;
9336 }
c7453384 9337
9db1d521 9338 return 0;
9db1d521
HP		 9339}
9340
9341/* Update the data in CUM to advance over an argument of mode MODE and
9342 data type TYPE. (TYPE is null for libcalls where that information
994fe660
UW		 9343 may not be available.). The boolean NAMED specifies whether the
9344 argument is a named argument (as opposed to an unnamed argument
9345 matching an ellipsis). */
9db1d521 9346
3cb1da52 9347static void
ef4bddc2 9348s390_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
3cb1da52 9349 const_tree type, bool named ATTRIBUTE_UNUSED)
9db1d521 9350{
d5cc9181
JR		 9351 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
9352
8cd5a4e0 9353 if (s390_function_arg_float (mode, type))
9db1d521 9354 {
82b1c974 9355 cum->fprs += 1;
9db1d521 9356 }
8c17530e 9357 else if (s390_function_arg_integer (mode, type))
9db1d521
HP		 9358 {
9359 int size = s390_function_arg_size (mode, type);
9602b6a1 9360 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
9db1d521 9361 }
8c17530e 9362 else
8d933e31 9363 gcc_unreachable ();
9db1d521
HP		 9364}
9365
994fe660
UW		 9366/* Define where to put the arguments to a function.
9367 Value is zero to push the argument on the stack,
9368 or a hard register in which to store the argument.
9369
9370 MODE is the argument's machine mode.
9371 TYPE is the data type of the argument (as a tree).
9372 This is null for libcalls where that information may
9373 not be available.
9374 CUM is a variable of type CUMULATIVE_ARGS which gives info about
9375 the preceding args and about the function being called.
9376 NAMED is nonzero if this argument is a named parameter
c7453384 9377 (otherwise it is an extra parameter matching an ellipsis).
994fe660
UW		 9378
9379 On S/390, we use general purpose registers 2 through 6 to
9380 pass integer, pointer, and certain structure arguments, and
9381 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
9382 to pass floating point arguments. All remaining arguments
9383 are pushed to the stack. */
9db1d521 9384
3cb1da52 9385static rtx
ef4bddc2 9386s390_function_arg (cumulative_args_t cum_v, machine_mode mode,
3cb1da52 9387 const_tree type, bool named ATTRIBUTE_UNUSED)
9db1d521 9388{
d5cc9181
JR		 9389 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
9390
82b1c974 9391 if (s390_function_arg_float (mode, type))
9db1d521 9392 {
29a79fcf 9393 if (cum->fprs + 1 > FP_ARG_NUM_REG)
9db1d521
HP		 9394 return 0;
9395 else
f1c25d3b 9396 return gen_rtx_REG (mode, cum->fprs + 16);
9db1d521 9397 }
8c17530e 9398 else if (s390_function_arg_integer (mode, type))
9db1d521
HP		 9399 {
9400 int size = s390_function_arg_size (mode, type);
9602b6a1 9401 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
9db1d521 9402
29a79fcf 9403 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
9db1d521 9404 return 0;
9602b6a1 9405 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
f1c25d3b 9406 return gen_rtx_REG (mode, cum->gprs + 2);
9602b6a1
AK		 9407 else if (n_gprs == 2)
9408 {
9409 rtvec p = rtvec_alloc (2);
9410
9411 RTVEC_ELT (p, 0)
9412 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
9413 const0_rtx);
9414 RTVEC_ELT (p, 1)
9415 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
9416 GEN_INT (4));
9417
9418 return gen_rtx_PARALLEL (mode, p);
9419 }
9db1d521 9420 }
8c17530e
UW		 9421
9422 /* After the real arguments, expand_call calls us once again
9423 with a void_type_node type. Whatever we return here is
9424 passed as operand 2 to the call expanders.
9425
9426 We don't need this feature ... */
9427 else if (type == void_type_node)
9428 return const0_rtx;
9429
8d933e31 9430 gcc_unreachable ();
8c17530e
UW		 9431}
9432
9433/* Return true if return values of type TYPE should be returned
9434 in a memory buffer whose address is passed by the caller as
9435 hidden first argument. */
9436
9437static bool
586de218 9438s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8c17530e
UW		 9439{
9440 /* We accept small integral (and similar) types. */
9441 if (INTEGRAL_TYPE_P (type)
38899e29 9442 || POINTER_TYPE_P (type)
8c17530e
UW		 9443 || TREE_CODE (type) == OFFSET_TYPE
9444 || TREE_CODE (type) == REAL_TYPE)
9445 return int_size_in_bytes (type) > 8;
9446
9447 /* Aggregates and similar constructs are always returned
9448 in memory. */
9449 if (AGGREGATE_TYPE_P (type)
9450 || TREE_CODE (type) == COMPLEX_TYPE
9451 || TREE_CODE (type) == VECTOR_TYPE)
9452 return true;
9453
9454 /* ??? We get called on all sorts of random stuff from
9455 aggregate_value_p. We can't abort, but it's not clear
9456 what's safe to return. Pretend it's a struct I guess. */
9457 return true;
9458}
9459
cde0f3fd
PB		 9460/* Function arguments and return values are promoted to word size. */
9461
ef4bddc2
RS		 9462static machine_mode
9463s390_promote_function_mode (const_tree type, machine_mode mode,
cde0f3fd
PB		 9464 int *punsignedp,
9465 const_tree fntype ATTRIBUTE_UNUSED,
9466 int for_return ATTRIBUTE_UNUSED)
9467{
9468 if (INTEGRAL_MODE_P (mode)
9602b6a1 9469 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
cde0f3fd 9470 {
5e617be8 9471 if (type != NULL_TREE && POINTER_TYPE_P (type))
cde0f3fd
PB		 9472 *punsignedp = POINTERS_EXTEND_UNSIGNED;
9473 return Pmode;
9474 }
9475
9476 return mode;
9477}
9478
b46616fd
AK		 9479/* Define where to return a (scalar) value of type RET_TYPE.
9480 If RET_TYPE is null, define where to return a (scalar)
8c17530e
UW		 9481 value of mode MODE from a libcall. */
9482
b46616fd 9483static rtx
ef4bddc2 9484s390_function_and_libcall_value (machine_mode mode,
b46616fd
AK		 9485 const_tree ret_type,
9486 const_tree fntype_or_decl,
9487 bool outgoing ATTRIBUTE_UNUSED)
8c17530e 9488{
b46616fd
AK		 9489 /* For normal functions perform the promotion as
9490 promote_function_mode would do. */
9491 if (ret_type)
8c17530e 9492 {
b46616fd
AK		 9493 int unsignedp = TYPE_UNSIGNED (ret_type);
9494 mode = promote_function_mode (ret_type, mode, &unsignedp,
9495 fntype_or_decl, 1);
8c17530e
UW		 9496 }
9497
4dc19cc0 9498 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8d933e31 9499 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8c17530e 9500
4dc19cc0 9501 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8c17530e 9502 return gen_rtx_REG (mode, 16);
9602b6a1
AK		 9503 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
9504 || UNITS_PER_LONG == UNITS_PER_WORD)
8c17530e 9505 return gen_rtx_REG (mode, 2);
9602b6a1
AK		 9506 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
9507 {
b46616fd
AK		 9508 /* This case is triggered when returning a 64 bit value with
9509 -m31 -mzarch. Although the value would fit into a single
9510 register it has to be forced into a 32 bit register pair in
9511 order to match the ABI. */
9602b6a1
AK		 9512 rtvec p = rtvec_alloc (2);
9513
9514 RTVEC_ELT (p, 0)
9515 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
9516 RTVEC_ELT (p, 1)
9517 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
9518
9519 return gen_rtx_PARALLEL (mode, p);
9520 }
9521
9522 gcc_unreachable ();
9db1d521
HP		 9523}
9524
b46616fd
AK		 9525/* Define where to return a scalar return value of type RET_TYPE. */
9526
9527static rtx
9528s390_function_value (const_tree ret_type, const_tree fn_decl_or_type,
9529 bool outgoing)
9530{
9531 return s390_function_and_libcall_value (TYPE_MODE (ret_type), ret_type,
9532 fn_decl_or_type, outgoing);
9533}
9534
9535/* Define where to return a scalar libcall return value of mode
9536 MODE. */
9537
9538static rtx
ef4bddc2 9539s390_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
b46616fd
AK		 9540{
9541 return s390_function_and_libcall_value (mode, NULL_TREE,
9542 NULL_TREE, true);
9543}
9544
9db1d521 9545
994fe660
UW		 9546/* Create and return the va_list datatype.
9547
9548 On S/390, va_list is an array type equivalent to
9549
9550 typedef struct __va_list_tag
9551 {
9552 long __gpr;
9553 long __fpr;
9554 void *__overflow_arg_area;
9555 void *__reg_save_area;
994fe660
UW		 9556 } va_list[1];
9557
9558 where __gpr and __fpr hold the number of general purpose
9559 or floating point arguments used up to now, respectively,
c7453384 9560 __overflow_arg_area points to the stack location of the
994fe660
UW		 9561 next argument passed on the stack, and __reg_save_area
9562 always points to the start of the register area in the
9563 call frame of the current function. The function prologue
9564 saves all registers used for argument passing into this
9565 area if the function uses variable arguments. */
9db1d521 9566
c35d187f
RH		 9567static tree
9568s390_build_builtin_va_list (void)
9db1d521
HP		 9569{
9570 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
9571
47798692 9572 record = lang_hooks.types.make_type (RECORD_TYPE);
9db1d521
HP		 9573
9574 type_decl =
4c4bde29
AH		 9575 build_decl (BUILTINS_LOCATION,
9576 TYPE_DECL, get_identifier ("__va_list_tag"), record);
9db1d521 9577
4c4bde29
AH		 9578 f_gpr = build_decl (BUILTINS_LOCATION,
9579 FIELD_DECL, get_identifier ("__gpr"),
9db1d521 9580 long_integer_type_node);
4c4bde29
AH		 9581 f_fpr = build_decl (BUILTINS_LOCATION,
9582 FIELD_DECL, get_identifier ("__fpr"),
9db1d521 9583 long_integer_type_node);
4c4bde29
AH		 9584 f_ovf = build_decl (BUILTINS_LOCATION,
9585 FIELD_DECL, get_identifier ("__overflow_arg_area"),
9db1d521 9586 ptr_type_node);
4c4bde29
AH		 9587 f_sav = build_decl (BUILTINS_LOCATION,
9588 FIELD_DECL, get_identifier ("__reg_save_area"),
9db1d521
HP		 9589 ptr_type_node);
9590
29a79fcf
UW		 9591 va_list_gpr_counter_field = f_gpr;
9592 va_list_fpr_counter_field = f_fpr;
9593
9db1d521
HP		 9594 DECL_FIELD_CONTEXT (f_gpr) = record;
9595 DECL_FIELD_CONTEXT (f_fpr) = record;
9596 DECL_FIELD_CONTEXT (f_ovf) = record;
9597 DECL_FIELD_CONTEXT (f_sav) = record;
9598
0fd2eac2 9599 TYPE_STUB_DECL (record) = type_decl;
9db1d521
HP		 9600 TYPE_NAME (record) = type_decl;
9601 TYPE_FIELDS (record) = f_gpr;
910ad8de
NF		 9602 DECL_CHAIN (f_gpr) = f_fpr;
9603 DECL_CHAIN (f_fpr) = f_ovf;
9604 DECL_CHAIN (f_ovf) = f_sav;
9db1d521
HP		 9605
9606 layout_type (record);
9607
9608 /* The correct type is an array type of one element. */
9609 return build_array_type (record, build_index_type (size_zero_node));
9610}
9611
994fe660 9612/* Implement va_start by filling the va_list structure VALIST.
6c535c69
ZW		 9613 STDARG_P is always true, and ignored.
9614 NEXTARG points to the first anonymous stack argument.
994fe660 9615
f710504c 9616 The following global variables are used to initialize
994fe660
UW		 9617 the va_list structure:
9618
38173d38 9619 crtl->args.info:
994fe660 9620 holds number of gprs and fprs used for named arguments.
38173d38 9621 crtl->args.arg_offset_rtx:
994fe660
UW		 9622 holds the offset of the first anonymous stack argument
9623 (relative to the virtual arg pointer). */
9db1d521 9624
d7bd8aeb 9625static void
9c808aad 9626s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
9db1d521
HP		 9627{
9628 HOST_WIDE_INT n_gpr, n_fpr;
9629 int off;
9630 tree f_gpr, f_fpr, f_ovf, f_sav;
9631 tree gpr, fpr, ovf, sav, t;
9632
9633 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
910ad8de
NF		 9634 f_fpr = DECL_CHAIN (f_gpr);
9635 f_ovf = DECL_CHAIN (f_fpr);
9636 f_sav = DECL_CHAIN (f_ovf);
9db1d521 9637
86710a8b 9638 valist = build_simple_mem_ref (valist);
47a25a46
RG		 9639 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9640 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
9641 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9642 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
9db1d521
HP		 9643
9644 /* Count number of gp and fp argument registers used. */
9645
38173d38
JH		 9646 n_gpr = crtl->args.info.gprs;
9647 n_fpr = crtl->args.info.fprs;
9db1d521 9648
29a79fcf
UW		 9649 if (cfun->va_list_gpr_size)
9650 {
726a989a
RB		 9651 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
9652 build_int_cst (NULL_TREE, n_gpr));
29a79fcf
UW		 9653 TREE_SIDE_EFFECTS (t) = 1;
9654 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9655 }
9db1d521 9656
29a79fcf
UW		 9657 if (cfun->va_list_fpr_size)
9658 {
726a989a 9659 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
47a25a46 9660 build_int_cst (NULL_TREE, n_fpr));
29a79fcf
UW		 9661 TREE_SIDE_EFFECTS (t) = 1;
9662 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9663 }
9db1d521
HP		 9664
9665 /* Find the overflow area. */
29a79fcf
UW		 9666 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
9667 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
9668 {
9669 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
9db1d521 9670
38173d38 9671 off = INTVAL (crtl->args.arg_offset_rtx);
29a79fcf
UW		 9672 off = off < 0 ? 0 : off;
9673 if (TARGET_DEBUG_ARG)
9674 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
9675 (int)n_gpr, (int)n_fpr, off);
9db1d521 9676
5d49b6a7 9677 t = fold_build_pointer_plus_hwi (t, off);
9db1d521 9678
726a989a 9679 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
29a79fcf
UW		 9680 TREE_SIDE_EFFECTS (t) = 1;
9681 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9682 }
9db1d521
HP		 9683
9684 /* Find the register save area. */
29a79fcf
UW		 9685 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
9686 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
9687 {
9688 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
5d49b6a7 9689 t = fold_build_pointer_plus_hwi (t, -RETURN_REGNUM * UNITS_PER_LONG);
f4aa3848 9690
726a989a 9691 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
29a79fcf
UW		 9692 TREE_SIDE_EFFECTS (t) = 1;
9693 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9694 }
9db1d521
HP		 9695}
9696
c7453384 9697/* Implement va_arg by updating the va_list structure
994fe660 9698 VALIST as required to retrieve an argument of type
c7453384
EC		 9699 TYPE, and returning that argument.
9700
994fe660 9701 Generates code equivalent to:
c7453384 9702
9db1d521
HP		 9703 if (integral value) {
9704 if (size <= 4 && args.gpr < 5 ||
c7453384 9705 size > 4 && args.gpr < 4 )
9db1d521
HP		 9706 ret = args.reg_save_area[args.gpr+8]
9707 else
9708 ret = *args.overflow_arg_area++;
9709 } else if (float value) {
9710 if (args.fgpr < 2)
9711 ret = args.reg_save_area[args.fpr+64]
9712 else
9713 ret = *args.overflow_arg_area++;
9714 } else if (aggregate value) {
9715 if (args.gpr < 5)
9716 ret = *args.reg_save_area[args.gpr]
9717 else
9718 ret = **args.overflow_arg_area++;
9719 } */
9720
ab96de7e 9721static tree
f4aa3848 9722s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
726a989a 9723 gimple_seq *post_p ATTRIBUTE_UNUSED)
9db1d521
HP		 9724{
9725 tree f_gpr, f_fpr, f_ovf, f_sav;
9726 tree gpr, fpr, ovf, sav, reg, t, u;
9727 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
63694b5e 9728 tree lab_false, lab_over, addr;
9db1d521
HP		 9729
9730 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
910ad8de
NF		 9731 f_fpr = DECL_CHAIN (f_gpr);
9732 f_ovf = DECL_CHAIN (f_fpr);
9733 f_sav = DECL_CHAIN (f_ovf);
9db1d521 9734
967af719 9735 valist = build_va_arg_indirect_ref (valist);
47a25a46
RG		 9736 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9737 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
47a25a46 9738 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
9db1d521 9739
726a989a
RB		 9740 /* The tree for args* cannot be shared between gpr/fpr and ovf since
9741 both appear on a lhs. */
9742 valist = unshare_expr (valist);
9743 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9744
9db1d521
HP		 9745 size = int_size_in_bytes (type);
9746
8cd5a4e0 9747 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
9db1d521
HP		 9748 {
9749 if (TARGET_DEBUG_ARG)
9750 {
9751 fprintf (stderr, "va_arg: aggregate type");
9752 debug_tree (type);
9753 }
9754
9755 /* Aggregates are passed by reference. */
9756 indirect_p = 1;
9757 reg = gpr;
9758 n_reg = 1;
ea506297 9759
b3d31392 9760 /* kernel stack layout on 31 bit: It is assumed here that no padding
ea506297
AK		 9761 will be added by s390_frame_info because for va_args always an even
9762 number of gprs has to be saved r15-r2 = 14 regs. */
9602b6a1
AK		 9763 sav_ofs = 2 * UNITS_PER_LONG;
9764 sav_scale = UNITS_PER_LONG;
9765 size = UNITS_PER_LONG;
29a79fcf 9766 max_reg = GP_ARG_NUM_REG - n_reg;
9db1d521 9767 }
82b1c974 9768 else if (s390_function_arg_float (TYPE_MODE (type), type))
9db1d521
HP		 9769 {
9770 if (TARGET_DEBUG_ARG)
9771 {
9772 fprintf (stderr, "va_arg: float type");
9773 debug_tree (type);
9774 }
9775
9776 /* FP args go in FP registers, if present. */
9777 indirect_p = 0;
9778 reg = fpr;
9779 n_reg = 1;
9602b6a1 9780 sav_ofs = 16 * UNITS_PER_LONG;
9db1d521 9781 sav_scale = 8;
29a79fcf 9782 max_reg = FP_ARG_NUM_REG - n_reg;
9db1d521
HP		 9783 }
9784 else
9785 {
9786 if (TARGET_DEBUG_ARG)
9787 {
9788 fprintf (stderr, "va_arg: other type");
9789 debug_tree (type);
9790 }
9791
9792 /* Otherwise into GP registers. */
9793 indirect_p = 0;
9794 reg = gpr;
9602b6a1 9795 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
ea506297 9796
b3d31392
AK		 9797 /* kernel stack layout on 31 bit: It is assumed here that no padding
9798 will be added by s390_frame_info because for va_args always an even
9799 number of gprs has to be saved r15-r2 = 14 regs. */
9602b6a1 9800 sav_ofs = 2 * UNITS_PER_LONG;
c7453384 9801
9602b6a1
AK		 9802 if (size < UNITS_PER_LONG)
9803 sav_ofs += UNITS_PER_LONG - size;
9db1d521 9804
9602b6a1 9805 sav_scale = UNITS_PER_LONG;
29a79fcf 9806 max_reg = GP_ARG_NUM_REG - n_reg;
9db1d521
HP		 9807 }
9808
9809 /* Pull the value out of the saved registers ... */
9810
4c4bde29
AH		 9811 lab_false = create_artificial_label (UNKNOWN_LOCATION);
9812 lab_over = create_artificial_label (UNKNOWN_LOCATION);
63694b5e 9813 addr = create_tmp_var (ptr_type_node, "addr");
9db1d521 9814
6c6dd4bd 9815 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
63694b5e
UW		 9816 t = build2 (GT_EXPR, boolean_type_node, reg, t);
9817 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9818 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9819 gimplify_and_add (t, pre_p);
9db1d521 9820
5d49b6a7 9821 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
f4aa3848 9822 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
6c6dd4bd 9823 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
5d49b6a7 9824 t = fold_build_pointer_plus (t, u);
9db1d521 9825
726a989a 9826 gimplify_assign (addr, t, pre_p);
9db1d521 9827
726a989a 9828 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9db1d521 9829
726a989a 9830 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
9db1d521 9831
9db1d521
HP		 9832
9833 /* ... Otherwise out of the overflow area. */
9834
ab96de7e 9835 t = ovf;
9602b6a1 9836 if (size < UNITS_PER_LONG)
5d49b6a7 9837 t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG - size);
ab96de7e
AS		 9838
9839 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9840
726a989a 9841 gimplify_assign (addr, t, pre_p);
ab96de7e 9842
5d49b6a7 9843 t = fold_build_pointer_plus_hwi (t, size);
726a989a 9844 gimplify_assign (ovf, t, pre_p);
ab96de7e 9845
726a989a 9846 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
ab96de7e
AS		 9847
9848
9849 /* Increment register save count. */
9850
9851 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
9852 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
9853 gimplify_and_add (u, pre_p);
9854
9855 if (indirect_p)
9856 {
5b21f0f3
RG		 9857 t = build_pointer_type_for_mode (build_pointer_type (type),
9858 ptr_mode, true);
ab96de7e
AS		 9859 addr = fold_convert (t, addr);
9860 addr = build_va_arg_indirect_ref (addr);
9861 }
9862 else
9863 {
5b21f0f3 9864 t = build_pointer_type_for_mode (type, ptr_mode, true);
ab96de7e
AS		 9865 addr = fold_convert (t, addr);
9866 }
9867
9868 return build_va_arg_indirect_ref (addr);
9869}
9870
5a3fe9b6
AK		 9871/* Emit rtl for the tbegin or tbegin_retry (RETRY != NULL_RTX)
9872 expanders.
9873 DEST - Register location where CC will be stored.
9874 TDB - Pointer to a 256 byte area where to store the transaction.
9875 diagnostic block. NULL if TDB is not needed.
9876 RETRY - Retry count value. If non-NULL a retry loop for CC2
9877 is emitted
9878 CLOBBER_FPRS_P - If true clobbers for all FPRs are emitted as part
9879 of the tbegin instruction pattern. */
9880
9881void
9882s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p)
9883{
2561451d 9884 rtx retry_plus_two = gen_reg_rtx (SImode);
5a3fe9b6 9885 rtx retry_reg = gen_reg_rtx (SImode);
19f8b229 9886 rtx_code_label *retry_label = NULL;
5a3fe9b6
AK		 9887
9888 if (retry != NULL_RTX)
9889 {
9890 emit_move_insn (retry_reg, retry);
2561451d
AK		 9891 emit_insn (gen_addsi3 (retry_plus_two, retry_reg, const2_rtx));
9892 emit_insn (gen_addsi3 (retry_reg, retry_reg, const1_rtx));
5a3fe9b6
AK		 9893 retry_label = gen_label_rtx ();
9894 emit_label (retry_label);
9895 }
9896
9897 if (clobber_fprs_p)
2561451d 9898 emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), tdb));
5a3fe9b6 9899 else
2561451d
AK		 9900 emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK),
9901 tdb));
5a3fe9b6 9902
2561451d
AK		 9903 emit_move_insn (dest, gen_rtx_UNSPEC (SImode,
9904 gen_rtvec (1, gen_rtx_REG (CCRAWmode,
9905 CC_REGNUM)),
9906 UNSPEC_CC_TO_INT));
5a3fe9b6
AK		 9907 if (retry != NULL_RTX)
9908 {
86464cbd
AK		 9909 const int CC0 = 1 << 3;
9910 const int CC1 = 1 << 2;
9911 const int CC3 = 1 << 0;
9912 rtx jump;
5a3fe9b6 9913 rtx count = gen_reg_rtx (SImode);
775c43d3 9914 rtx_code_label *leave_label = gen_label_rtx ();
86464cbd
AK		 9915
9916 /* Exit for success and permanent failures. */
5a3fe9b6
AK		 9917 jump = s390_emit_jump (leave_label,
9918 gen_rtx_EQ (VOIDmode,
9919 gen_rtx_REG (CCRAWmode, CC_REGNUM),
86464cbd
AK		 9920 gen_rtx_CONST_INT (VOIDmode, CC0 | CC1 | CC3)));
9921 LABEL_NUSES (leave_label) = 1;
5a3fe9b6
AK		 9922
9923 /* CC2 - transient failure. Perform retry with ppa. */
2561451d 9924 emit_move_insn (count, retry_plus_two);
5a3fe9b6
AK		 9925 emit_insn (gen_subsi3 (count, count, retry_reg));
9926 emit_insn (gen_tx_assist (count));
9927 jump = emit_jump_insn (gen_doloop_si64 (retry_label,
9928 retry_reg,
9929 retry_reg));
9930 JUMP_LABEL (jump) = retry_label;
9931 LABEL_NUSES (retry_label) = 1;
86464cbd 9932 emit_label (leave_label);
5a3fe9b6 9933 }
5a3fe9b6
AK		 9934}
9935
9936/* Builtins. */
9937
9938enum s390_builtin
9939{
9940 S390_BUILTIN_TBEGIN,
9941 S390_BUILTIN_TBEGIN_NOFLOAT,
9942 S390_BUILTIN_TBEGIN_RETRY,
9943 S390_BUILTIN_TBEGIN_RETRY_NOFLOAT,
9944 S390_BUILTIN_TBEGINC,
9945 S390_BUILTIN_TEND,
9946 S390_BUILTIN_TABORT,
9947 S390_BUILTIN_NON_TX_STORE,
9948 S390_BUILTIN_TX_NESTING_DEPTH,
9949 S390_BUILTIN_TX_ASSIST,
9950
9951 S390_BUILTIN_max
9952};
9953
9954static enum insn_code const code_for_builtin[S390_BUILTIN_max] = {
9955 CODE_FOR_tbegin,
9956 CODE_FOR_tbegin_nofloat,
9957 CODE_FOR_tbegin_retry,
9958 CODE_FOR_tbegin_retry_nofloat,
9959 CODE_FOR_tbeginc,
9960 CODE_FOR_tend,
9961 CODE_FOR_tabort,
9962 CODE_FOR_ntstg,
9963 CODE_FOR_etnd,
9964 CODE_FOR_tx_assist
9965};
9966
9967static void
9968s390_init_builtins (void)
9969{
9970 tree ftype, uint64_type;
2561451d
AK		 9971 tree returns_twice_attr = tree_cons (get_identifier ("returns_twice"),
9972 NULL, NULL);
9973 tree noreturn_attr = tree_cons (get_identifier ("noreturn"), NULL, NULL);
5a3fe9b6
AK		 9974
9975 /* void foo (void) */
9976 ftype = build_function_type_list (void_type_node, NULL_TREE);
9977 add_builtin_function ("__builtin_tbeginc", ftype, S390_BUILTIN_TBEGINC,
9978 BUILT_IN_MD, NULL, NULL_TREE);
9979
9980 /* void foo (int) */
9981 ftype = build_function_type_list (void_type_node, integer_type_node,
9982 NULL_TREE);
9983 add_builtin_function ("__builtin_tabort", ftype,
2561451d 9984 S390_BUILTIN_TABORT, BUILT_IN_MD, NULL, noreturn_attr);
5a3fe9b6
AK		 9985 add_builtin_function ("__builtin_tx_assist", ftype,
9986 S390_BUILTIN_TX_ASSIST, BUILT_IN_MD, NULL, NULL_TREE);
9987
9988 /* int foo (void *) */
9989 ftype = build_function_type_list (integer_type_node, ptr_type_node, NULL_TREE);
9990 add_builtin_function ("__builtin_tbegin", ftype, S390_BUILTIN_TBEGIN,
2561451d 9991 BUILT_IN_MD, NULL, returns_twice_attr);
5a3fe9b6
AK		 9992 add_builtin_function ("__builtin_tbegin_nofloat", ftype,
9993 S390_BUILTIN_TBEGIN_NOFLOAT,
2561451d 9994 BUILT_IN_MD, NULL, returns_twice_attr);
5a3fe9b6
AK		 9995
9996 /* int foo (void *, int) */
9997 ftype = build_function_type_list (integer_type_node, ptr_type_node,
9998 integer_type_node, NULL_TREE);
9999 add_builtin_function ("__builtin_tbegin_retry", ftype,
10000 S390_BUILTIN_TBEGIN_RETRY,
10001 BUILT_IN_MD,
2561451d 10002 NULL, returns_twice_attr);
5a3fe9b6
AK		 10003 add_builtin_function ("__builtin_tbegin_retry_nofloat", ftype,
10004 S390_BUILTIN_TBEGIN_RETRY_NOFLOAT,
10005 BUILT_IN_MD,
2561451d 10006 NULL, returns_twice_attr);
5a3fe9b6
AK		 10007
10008 /* int foo (void) */
10009 ftype = build_function_type_list (integer_type_node, NULL_TREE);
10010 add_builtin_function ("__builtin_tx_nesting_depth", ftype,
10011 S390_BUILTIN_TX_NESTING_DEPTH,
10012 BUILT_IN_MD, NULL, NULL_TREE);
10013 add_builtin_function ("__builtin_tend", ftype,
10014 S390_BUILTIN_TEND, BUILT_IN_MD, NULL, NULL_TREE);
10015
10016 /* void foo (uint64_t *, uint64_t) */
10017 if (TARGET_64BIT)
10018 uint64_type = long_unsigned_type_node;
10019 else
10020 uint64_type = long_long_unsigned_type_node;
10021
10022 ftype = build_function_type_list (void_type_node,
10023 build_pointer_type (uint64_type),
10024 uint64_type, NULL_TREE);
10025 add_builtin_function ("__builtin_non_tx_store", ftype,
10026 S390_BUILTIN_NON_TX_STORE,
10027 BUILT_IN_MD, NULL, NULL_TREE);
10028}
10029
10030/* Expand an expression EXP that calls a built-in function,
10031 with result going to TARGET if that's convenient
10032 (and in mode MODE if that's convenient).
10033 SUBTARGET may be used as the target for computing one of EXP's operands.
10034 IGNORE is nonzero if the value is to be ignored. */
10035
10036static rtx
10037s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
ef4bddc2 10038 machine_mode mode ATTRIBUTE_UNUSED,
5a3fe9b6
AK		 10039 int ignore ATTRIBUTE_UNUSED)
10040{
10041#define MAX_ARGS 2
10042
10043 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10044 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10045 enum insn_code icode;
10046 rtx op[MAX_ARGS], pat;
10047 int arity;
10048 bool nonvoid;
10049 tree arg;
10050 call_expr_arg_iterator iter;
10051
10052 if (fcode >= S390_BUILTIN_max)
10053 internal_error ("bad builtin fcode");
10054 icode = code_for_builtin[fcode];
10055 if (icode == 0)
10056 internal_error ("bad builtin fcode");
10057
167f68ed
AK		 10058 if (!TARGET_HTM)
10059 error ("Transactional execution builtins not enabled (-mhtm)\n");
5a3fe9b6
AK		 10060
10061 /* Set a flag in the machine specific cfun part in order to support
10062 saving/restoring of FPRs. */
10063 if (fcode == S390_BUILTIN_TBEGIN || fcode == S390_BUILTIN_TBEGIN_RETRY)
10064 cfun->machine->tbegin_p = true;
10065
10066 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
10067
10068 arity = 0;
10069 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
10070 {
10071 const struct insn_operand_data *insn_op;
10072
10073 if (arg == error_mark_node)
10074 return NULL_RTX;
10075 if (arity >= MAX_ARGS)
10076 return NULL_RTX;
10077
10078 insn_op = &insn_data[icode].operand[arity + nonvoid];
10079
10080 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
10081
10082 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
10083 {
10084 if (insn_op->predicate == memory_operand)
10085 {
10086 /* Don't move a NULL pointer into a register. Otherwise
10087 we have to rely on combine being able to move it back
10088 in order to get an immediate 0 in the instruction. */
10089 if (op[arity] != const0_rtx)
10090 op[arity] = copy_to_mode_reg (Pmode, op[arity]);
10091 op[arity] = gen_rtx_MEM (insn_op->mode, op[arity]);
10092 }
10093 else
10094 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
10095 }
10096
10097 arity++;
10098 }
10099
10100 if (nonvoid)
10101 {
ef4bddc2 10102 machine_mode tmode = insn_data[icode].operand[0].mode;
5a3fe9b6
AK		 10103 if (!target
10104 || GET_MODE (target) != tmode
10105 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
10106 target = gen_reg_rtx (tmode);
10107 }
10108
10109 switch (arity)
10110 {
10111 case 0:
10112 pat = GEN_FCN (icode) (target);
10113 break;
10114 case 1:
10115 if (nonvoid)
10116 pat = GEN_FCN (icode) (target, op[0]);
10117 else
10118 pat = GEN_FCN (icode) (op[0]);
10119 break;
10120 case 2:
10121 if (nonvoid)
10122 pat = GEN_FCN (icode) (target, op[0], op[1]);
10123 else
10124 pat = GEN_FCN (icode) (op[0], op[1]);
10125 break;
10126 default:
10127 gcc_unreachable ();
10128 }
10129 if (!pat)
10130 return NULL_RTX;
10131 emit_insn (pat);
10132
10133 if (nonvoid)
10134 return target;
10135 else
10136 return const0_rtx;
10137}
10138
d56a43a0
AK		 10139/* We call mcount before the function prologue. So a profiled leaf
10140 function should stay a leaf function. */
10141
10142static bool
10143s390_keep_leaf_when_profiled ()
10144{
10145 return true;
10146}
5a3fe9b6 10147
ab96de7e
AS		 10148/* Output assembly code for the trampoline template to
10149 stdio stream FILE.
10150
10151 On S/390, we use gpr 1 internally in the trampoline code;
10152 gpr 0 is used to hold the static chain. */
10153
b81ecf6f
RH		 10154static void
10155s390_asm_trampoline_template (FILE *file)
ab96de7e
AS		 10156{
10157 rtx op[2];
10158 op[0] = gen_rtx_REG (Pmode, 0);
10159 op[1] = gen_rtx_REG (Pmode, 1);
10160
10161 if (TARGET_64BIT)
10162 {
cab78b15
AK		 10163 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
10164 output_asm_insn ("lmg\t%0,%1,14(%1)", op); /* 6 byte */
10165 output_asm_insn ("br\t%1", op); /* 2 byte */
ab96de7e
AS		 10166 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
10167 }
10168 else
10169 {
cab78b15
AK		 10170 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
10171 output_asm_insn ("lm\t%0,%1,6(%1)", op); /* 4 byte */
10172 output_asm_insn ("br\t%1", op); /* 2 byte */
ab96de7e
AS		 10173 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
10174 }
10175}
10176
10177/* Emit RTL insns to initialize the variable parts of a trampoline.
10178 FNADDR is an RTX for the address of the function's pure code.
10179 CXT is an RTX for the static chain value for the function. */
10180
b81ecf6f
RH		 10181static void
10182s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
ab96de7e 10183{
b81ecf6f
RH		 10184 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
10185 rtx mem;
3a892e44 10186
b81ecf6f 10187 emit_block_move (m_tramp, assemble_trampoline_template (),
cab78b15 10188 GEN_INT (2 * UNITS_PER_LONG), BLOCK_OP_NORMAL);
b81ecf6f 10189
cab78b15 10190 mem = adjust_address (m_tramp, Pmode, 2 * UNITS_PER_LONG);
b81ecf6f 10191 emit_move_insn (mem, cxt);
cab78b15 10192 mem = adjust_address (m_tramp, Pmode, 3 * UNITS_PER_LONG);
b81ecf6f 10193 emit_move_insn (mem, fnaddr);
ab96de7e
AS		 10194}
10195
ab96de7e
AS		 10196/* Output assembler code to FILE to increment profiler label # LABELNO
10197 for profiling a function entry. */
10198
10199void
10200s390_function_profiler (FILE *file, int labelno)
10201{
10202 rtx op[7];
10203
10204 char label[128];
10205 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
10206
10207 fprintf (file, "# function profiler \n");
10208
10209 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
10210 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
0a81f074 10211 op[1] = gen_rtx_MEM (Pmode, plus_constant (Pmode, op[1], UNITS_PER_LONG));
ab96de7e
AS		 10212
10213 op[2] = gen_rtx_REG (Pmode, 1);
10214 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
10215 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
10216
10217 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
10218 if (flag_pic)
10219 {
10220 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
10221 op[4] = gen_rtx_CONST (Pmode, op[4]);
10222 }
10223
10224 if (TARGET_64BIT)
10225 {
10226 output_asm_insn ("stg\t%0,%1", op);
10227 output_asm_insn ("larl\t%2,%3", op);
10228 output_asm_insn ("brasl\t%0,%4", op);
10229 output_asm_insn ("lg\t%0,%1", op);
10230 }
10231 else if (!flag_pic)
10232 {
10233 op[6] = gen_label_rtx ();
10234
10235 output_asm_insn ("st\t%0,%1", op);
10236 output_asm_insn ("bras\t%2,%l6", op);
10237 output_asm_insn (".long\t%4", op);
10238 output_asm_insn (".long\t%3", op);
10239 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
10240 output_asm_insn ("l\t%0,0(%2)", op);
10241 output_asm_insn ("l\t%2,4(%2)", op);
10242 output_asm_insn ("basr\t%0,%0", op);
10243 output_asm_insn ("l\t%0,%1", op);
10244 }
10245 else
10246 {
10247 op[5] = gen_label_rtx ();
10248 op[6] = gen_label_rtx ();
10249
10250 output_asm_insn ("st\t%0,%1", op);
10251 output_asm_insn ("bras\t%2,%l6", op);
10252 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
10253 output_asm_insn (".long\t%4-%l5", op);
10254 output_asm_insn (".long\t%3-%l5", op);
10255 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
10256 output_asm_insn ("lr\t%0,%2", op);
10257 output_asm_insn ("a\t%0,0(%2)", op);
10258 output_asm_insn ("a\t%2,4(%2)", op);
10259 output_asm_insn ("basr\t%0,%0", op);
10260 output_asm_insn ("l\t%0,%1", op);
10261 }
10262}
10263
10264/* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
10265 into its SYMBOL_REF_FLAGS. */
10266
10267static void
10268s390_encode_section_info (tree decl, rtx rtl, int first)
10269{
10270 default_encode_section_info (decl, rtl, first);
10271
963fc8d0
AK		 10272 if (TREE_CODE (decl) == VAR_DECL)
10273 {
10274 /* If a variable has a forced alignment to < 2 bytes, mark it
10275 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
10276 operand. */
10277 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
10278 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
10279 if (!DECL_SIZE (decl)
10280 || !DECL_ALIGN (decl)
9541ffee 10281 || !tree_fits_shwi_p (DECL_SIZE (decl))
963fc8d0 10282 || (DECL_ALIGN (decl) <= 64
9439e9a1 10283 && DECL_ALIGN (decl) != tree_to_shwi (DECL_SIZE (decl))))
963fc8d0
AK		 10284 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
10285 }
10286
10287 /* Literal pool references don't have a decl so they are handled
10288 differently here. We rely on the information in the MEM_ALIGN
10289 entry to decide upon natural alignment. */
10290 if (MEM_P (rtl)
10291 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
10292 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
10293 && (MEM_ALIGN (rtl) == 0
35fcb6ba 10294 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
963fc8d0
AK		 10295 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
10296 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
ab96de7e
AS		 10297}
10298
10299/* Output thunk to FILE that implements a C++ virtual function call (with
10300 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
10301 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
10302 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
10303 relative to the resulting this pointer. */
10304
10305static void
10306s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
10307 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10308 tree function)
10309{
10310 rtx op[10];
10311 int nonlocal = 0;
10312
81ef7e24
JJ		 10313 /* Make sure unwind info is emitted for the thunk if needed. */
10314 final_start_function (emit_barrier (), file, 1);
10315
ab96de7e
AS		 10316 /* Operand 0 is the target function. */
10317 op[0] = XEXP (DECL_RTL (function), 0);
10318 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
10319 {
10320 nonlocal = 1;
10321 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
10322 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
10323 op[0] = gen_rtx_CONST (Pmode, op[0]);
10324 }
10325
10326 /* Operand 1 is the 'this' pointer. */
10327 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
10328 op[1] = gen_rtx_REG (Pmode, 3);
10329 else
10330 op[1] = gen_rtx_REG (Pmode, 2);
10331
10332 /* Operand 2 is the delta. */
10333 op[2] = GEN_INT (delta);
10334
10335 /* Operand 3 is the vcall_offset. */
10336 op[3] = GEN_INT (vcall_offset);
10337
10338 /* Operand 4 is the temporary register. */
10339 op[4] = gen_rtx_REG (Pmode, 1);
10340
10341 /* Operands 5 to 8 can be used as labels. */
10342 op[5] = NULL_RTX;
10343 op[6] = NULL_RTX;
10344 op[7] = NULL_RTX;
10345 op[8] = NULL_RTX;
10346
10347 /* Operand 9 can be used for temporary register. */
10348 op[9] = NULL_RTX;
10349
10350 /* Generate code. */
10351 if (TARGET_64BIT)
10352 {
10353 /* Setup literal pool pointer if required. */
10354 if ((!DISP_IN_RANGE (delta)
ec24698e
UW		 10355 && !CONST_OK_FOR_K (delta)
10356 && !CONST_OK_FOR_Os (delta))
ab96de7e 10357 || (!DISP_IN_RANGE (vcall_offset)
ec24698e
UW		 10358 && !CONST_OK_FOR_K (vcall_offset)
10359 && !CONST_OK_FOR_Os (vcall_offset)))
ab96de7e
AS		 10360 {
10361 op[5] = gen_label_rtx ();
10362 output_asm_insn ("larl\t%4,%5", op);
10363 }
10364
10365 /* Add DELTA to this pointer. */
10366 if (delta)
10367 {
b5c67a49 10368 if (CONST_OK_FOR_J (delta))
ab96de7e
AS		 10369 output_asm_insn ("la\t%1,%2(%1)", op);
10370 else if (DISP_IN_RANGE (delta))
10371 output_asm_insn ("lay\t%1,%2(%1)", op);
b5c67a49 10372 else if (CONST_OK_FOR_K (delta))
ab96de7e 10373 output_asm_insn ("aghi\t%1,%2", op);
ec24698e
UW		 10374 else if (CONST_OK_FOR_Os (delta))
10375 output_asm_insn ("agfi\t%1,%2", op);
ab96de7e
AS		 10376 else
10377 {
10378 op[6] = gen_label_rtx ();
10379 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
10380 }
10381 }
10382
10383 /* Perform vcall adjustment. */
10384 if (vcall_offset)
10385 {
10386 if (DISP_IN_RANGE (vcall_offset))
10387 {
10388 output_asm_insn ("lg\t%4,0(%1)", op);
10389 output_asm_insn ("ag\t%1,%3(%4)", op);
10390 }
b5c67a49 10391 else if (CONST_OK_FOR_K (vcall_offset))
ab96de7e
AS		 10392 {
10393 output_asm_insn ("lghi\t%4,%3", op);
10394 output_asm_insn ("ag\t%4,0(%1)", op);
10395 output_asm_insn ("ag\t%1,0(%4)", op);
10396 }
ec24698e
UW		 10397 else if (CONST_OK_FOR_Os (vcall_offset))
10398 {
10399 output_asm_insn ("lgfi\t%4,%3", op);
10400 output_asm_insn ("ag\t%4,0(%1)", op);
10401 output_asm_insn ("ag\t%1,0(%4)", op);
10402 }
ab96de7e
AS		 10403 else
10404 {
10405 op[7] = gen_label_rtx ();
10406 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
10407 output_asm_insn ("ag\t%4,0(%1)", op);
10408 output_asm_insn ("ag\t%1,0(%4)", op);
10409 }
10410 }
10411
10412 /* Jump to target. */
10413 output_asm_insn ("jg\t%0", op);
10414
10415 /* Output literal pool if required. */
10416 if (op[5])
10417 {
10418 output_asm_insn (".align\t4", op);
10419 targetm.asm_out.internal_label (file, "L",
10420 CODE_LABEL_NUMBER (op[5]));
10421 }
10422 if (op[6])
10423 {
10424 targetm.asm_out.internal_label (file, "L",
10425 CODE_LABEL_NUMBER (op[6]));
10426 output_asm_insn (".long\t%2", op);
10427 }
10428 if (op[7])
10429 {
10430 targetm.asm_out.internal_label (file, "L",
10431 CODE_LABEL_NUMBER (op[7]));
10432 output_asm_insn (".long\t%3", op);
10433 }
10434 }
10435 else
10436 {
10437 /* Setup base pointer if required. */
10438 if (!vcall_offset
10439 || (!DISP_IN_RANGE (delta)
ec24698e
UW		 10440 && !CONST_OK_FOR_K (delta)
10441 && !CONST_OK_FOR_Os (delta))
ab96de7e 10442 || (!DISP_IN_RANGE (delta)
ec24698e
UW		 10443 && !CONST_OK_FOR_K (vcall_offset)
10444 && !CONST_OK_FOR_Os (vcall_offset)))
ab96de7e
AS		 10445 {
10446 op[5] = gen_label_rtx ();
10447 output_asm_insn ("basr\t%4,0", op);
10448 targetm.asm_out.internal_label (file, "L",
10449 CODE_LABEL_NUMBER (op[5]));
10450 }
10451
10452 /* Add DELTA to this pointer. */
10453 if (delta)
10454 {
b5c67a49 10455 if (CONST_OK_FOR_J (delta))
ab96de7e
AS		 10456 output_asm_insn ("la\t%1,%2(%1)", op);
10457 else if (DISP_IN_RANGE (delta))
10458 output_asm_insn ("lay\t%1,%2(%1)", op);
b5c67a49 10459 else if (CONST_OK_FOR_K (delta))
ab96de7e 10460 output_asm_insn ("ahi\t%1,%2", op);
ec24698e
UW		 10461 else if (CONST_OK_FOR_Os (delta))
10462 output_asm_insn ("afi\t%1,%2", op);
ab96de7e
AS		 10463 else
10464 {
10465 op[6] = gen_label_rtx ();
10466 output_asm_insn ("a\t%1,%6-%5(%4)", op);
10467 }
10468 }
10469
10470 /* Perform vcall adjustment. */
10471 if (vcall_offset)
10472 {
b5c67a49 10473 if (CONST_OK_FOR_J (vcall_offset))
ab96de7e 10474 {
c4d50129 10475 output_asm_insn ("l\t%4,0(%1)", op);
ab96de7e
AS		 10476 output_asm_insn ("a\t%1,%3(%4)", op);
10477 }
10478 else if (DISP_IN_RANGE (vcall_offset))
10479 {
c4d50129 10480 output_asm_insn ("l\t%4,0(%1)", op);
ab96de7e
AS		 10481 output_asm_insn ("ay\t%1,%3(%4)", op);
10482 }
b5c67a49 10483 else if (CONST_OK_FOR_K (vcall_offset))
ab96de7e
AS		 10484 {
10485 output_asm_insn ("lhi\t%4,%3", op);
10486 output_asm_insn ("a\t%4,0(%1)", op);
10487 output_asm_insn ("a\t%1,0(%4)", op);
10488 }
ec24698e
UW		 10489 else if (CONST_OK_FOR_Os (vcall_offset))
10490 {
10491 output_asm_insn ("iilf\t%4,%3", op);
10492 output_asm_insn ("a\t%4,0(%1)", op);
10493 output_asm_insn ("a\t%1,0(%4)", op);
10494 }
ab96de7e
AS		 10495 else
10496 {
10497 op[7] = gen_label_rtx ();
10498 output_asm_insn ("l\t%4,%7-%5(%4)", op);
10499 output_asm_insn ("a\t%4,0(%1)", op);
10500 output_asm_insn ("a\t%1,0(%4)", op);
10501 }
9db1d521 10502
ab96de7e
AS		 10503 /* We had to clobber the base pointer register.
10504 Re-setup the base pointer (with a different base). */
10505 op[5] = gen_label_rtx ();
10506 output_asm_insn ("basr\t%4,0", op);
10507 targetm.asm_out.internal_label (file, "L",
10508 CODE_LABEL_NUMBER (op[5]));
10509 }
9db1d521 10510
ab96de7e
AS		 10511 /* Jump to target. */
10512 op[8] = gen_label_rtx ();
9db1d521 10513
ab96de7e
AS		 10514 if (!flag_pic)
10515 output_asm_insn ("l\t%4,%8-%5(%4)", op);
10516 else if (!nonlocal)
10517 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10518 /* We cannot call through .plt, since .plt requires %r12 loaded. */
10519 else if (flag_pic == 1)
10520 {
10521 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10522 output_asm_insn ("l\t%4,%0(%4)", op);
10523 }
10524 else if (flag_pic == 2)
10525 {
10526 op[9] = gen_rtx_REG (Pmode, 0);
10527 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
10528 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10529 output_asm_insn ("ar\t%4,%9", op);
10530 output_asm_insn ("l\t%4,0(%4)", op);
10531 }
9db1d521 10532
ab96de7e 10533 output_asm_insn ("br\t%4", op);
9db1d521 10534
ab96de7e
AS		 10535 /* Output literal pool. */
10536 output_asm_insn (".align\t4", op);
9db1d521 10537
ab96de7e
AS		 10538 if (nonlocal && flag_pic == 2)
10539 output_asm_insn (".long\t%0", op);
10540 if (nonlocal)
10541 {
10542 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
10543 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
10544 }
63694b5e 10545
ab96de7e
AS		 10546 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
10547 if (!flag_pic)
10548 output_asm_insn (".long\t%0", op);
10549 else
10550 output_asm_insn (".long\t%0-%5", op);
9db1d521 10551
ab96de7e
AS		 10552 if (op[6])
10553 {
10554 targetm.asm_out.internal_label (file, "L",
10555 CODE_LABEL_NUMBER (op[6]));
10556 output_asm_insn (".long\t%2", op);
10557 }
10558 if (op[7])
10559 {
10560 targetm.asm_out.internal_label (file, "L",
10561 CODE_LABEL_NUMBER (op[7]));
10562 output_asm_insn (".long\t%3", op);
10563 }
9db1d521 10564 }
81ef7e24 10565 final_end_function ();
9db1d521
HP		 10566}
10567
ab96de7e 10568static bool
ef4bddc2 10569s390_valid_pointer_mode (machine_mode mode)
ab96de7e
AS		 10570{
10571 return (mode == SImode || (TARGET_64BIT && mode == DImode));
10572}
994fe660 10573
9a6f71b4 10574/* Checks whether the given CALL_EXPR would use a caller
ab96de7e
AS		 10575 saved register. This is used to decide whether sibling call
10576 optimization could be performed on the respective function
10577 call. */
fd3cd001 10578
ab96de7e 10579static bool
9a6f71b4 10580s390_call_saved_register_used (tree call_expr)
fd3cd001 10581{
d5cc9181
JR		 10582 CUMULATIVE_ARGS cum_v;
10583 cumulative_args_t cum;
ab96de7e 10584 tree parameter;
ef4bddc2 10585 machine_mode mode;
ab96de7e
AS		 10586 tree type;
10587 rtx parm_rtx;
9a6f71b4 10588 int reg, i;
fd3cd001 10589
d5cc9181
JR		 10590 INIT_CUMULATIVE_ARGS (cum_v, NULL, NULL, 0, 0);
10591 cum = pack_cumulative_args (&cum_v);
fd3cd001 10592
9a6f71b4 10593 for (i = 0; i < call_expr_nargs (call_expr); i++)
ab96de7e 10594 {
9a6f71b4 10595 parameter = CALL_EXPR_ARG (call_expr, i);
8d933e31 10596 gcc_assert (parameter);
fd3cd001 10597
ab96de7e
AS		 10598 /* For an undeclared variable passed as parameter we will get
10599 an ERROR_MARK node here. */
10600 if (TREE_CODE (parameter) == ERROR_MARK)
10601 return true;
fd3cd001 10602
8d933e31
AS		 10603 type = TREE_TYPE (parameter);
10604 gcc_assert (type);
fd3cd001 10605
8d933e31
AS		 10606 mode = TYPE_MODE (type);
10607 gcc_assert (mode);
fd3cd001 10608
d5cc9181 10609 if (pass_by_reference (&cum_v, mode, type, true))
ab96de7e
AS		 10610 {
10611 mode = Pmode;
10612 type = build_pointer_type (type);
10613 }
fd3cd001 10614
d5cc9181 10615 parm_rtx = s390_function_arg (cum, mode, type, 0);
fd3cd001 10616
d5cc9181 10617 s390_function_arg_advance (cum, mode, type, 0);
fd3cd001 10618
9602b6a1
AK		 10619 if (!parm_rtx)
10620 continue;
10621
10622 if (REG_P (parm_rtx))
10623 {
e8de8fea
AK		 10624 for (reg = 0;
10625 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
10626 reg++)
9602b6a1
AK		 10627 if (!call_used_regs[reg + REGNO (parm_rtx)])
10628 return true;
10629 }
10630
10631 if (GET_CODE (parm_rtx) == PARALLEL)
ab96de7e 10632 {
9602b6a1 10633 int i;
e8de8fea 10634
9602b6a1
AK		 10635 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
10636 {
10637 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
9602b6a1
AK		 10638
10639 gcc_assert (REG_P (r));
10640
e8de8fea
AK		 10641 for (reg = 0;
10642 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
10643 reg++)
9602b6a1
AK		 10644 if (!call_used_regs[reg + REGNO (r)])
10645 return true;
10646 }
ab96de7e 10647 }
9602b6a1 10648
ab96de7e
AS		 10649 }
10650 return false;
10651}
fd3cd001 10652
ab96de7e
AS		 10653/* Return true if the given call expression can be
10654 turned into a sibling call.
10655 DECL holds the declaration of the function to be called whereas
10656 EXP is the call expression itself. */
fd3cd001 10657
ab96de7e
AS		 10658static bool
10659s390_function_ok_for_sibcall (tree decl, tree exp)
10660{
10661 /* The TPF epilogue uses register 1. */
10662 if (TARGET_TPF_PROFILING)
10663 return false;
fd3cd001 10664
ab96de7e
AS		 10665 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
10666 which would have to be restored before the sibcall. */
7691ec4e 10667 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
ab96de7e 10668 return false;
fd3cd001 10669
ab96de7e
AS		 10670 /* Register 6 on s390 is available as an argument register but unfortunately
10671 "caller saved". This makes functions needing this register for arguments
10672 not suitable for sibcalls. */
9a6f71b4 10673 return !s390_call_saved_register_used (exp);
ab96de7e 10674}
fd3cd001 10675
ab96de7e 10676/* Return the fixed registers used for condition codes. */
fd3cd001 10677
ab96de7e
AS		 10678static bool
10679s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
10680{
10681 *p1 = CC_REGNUM;
10682 *p2 = INVALID_REGNUM;
f4aa3848 10683
ab96de7e
AS		 10684 return true;
10685}
fd3cd001 10686
ab96de7e
AS		 10687/* This function is used by the call expanders of the machine description.
10688 It emits the call insn itself together with the necessary operations
10689 to adjust the target address and returns the emitted insn.
10690 ADDR_LOCATION is the target address rtx
10691 TLS_CALL the location of the thread-local symbol
10692 RESULT_REG the register where the result of the call should be stored
10693 RETADDR_REG the register where the return address should be stored
10694 If this parameter is NULL_RTX the call is considered
10695 to be a sibling call. */
fd3cd001 10696
775c43d3 10697rtx_insn *
ab96de7e
AS		 10698s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
10699 rtx retaddr_reg)
9db1d521 10700{
ab96de7e 10701 bool plt_call = false;
775c43d3 10702 rtx_insn *insn;
ab96de7e
AS		 10703 rtx call;
10704 rtx clobber;
10705 rtvec vec;
cadc42db 10706
ab96de7e
AS		 10707 /* Direct function calls need special treatment. */
10708 if (GET_CODE (addr_location) == SYMBOL_REF)
9db1d521 10709 {
ab96de7e
AS		 10710 /* When calling a global routine in PIC mode, we must
10711 replace the symbol itself with the PLT stub. */
10712 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
10713 {
72e2cf16
AK		 10714 if (retaddr_reg != NULL_RTX)
10715 {
10716 addr_location = gen_rtx_UNSPEC (Pmode,
10717 gen_rtvec (1, addr_location),
10718 UNSPEC_PLT);
10719 addr_location = gen_rtx_CONST (Pmode, addr_location);
10720 plt_call = true;
10721 }
10722 else
10723 /* For -fpic code the PLT entries might use r12 which is
10724 call-saved. Therefore we cannot do a sibcall when
10725 calling directly using a symbol ref. When reaching
10726 this point we decided (in s390_function_ok_for_sibcall)
10727 to do a sibcall for a function pointer but one of the
10728 optimizers was able to get rid of the function pointer
10729 by propagating the symbol ref into the call. This
10730 optimization is illegal for S/390 so we turn the direct
10731 call into a indirect call again. */
10732 addr_location = force_reg (Pmode, addr_location);
ab96de7e
AS		 10733 }
10734
10735 /* Unless we can use the bras(l) insn, force the
10736 routine address into a register. */
10737 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
10738 {
10739 if (flag_pic)
10740 addr_location = legitimize_pic_address (addr_location, 0);
10741 else
10742 addr_location = force_reg (Pmode, addr_location);
10743 }
9db1d521 10744 }
ab96de7e
AS		 10745
10746 /* If it is already an indirect call or the code above moved the
10747 SYMBOL_REF to somewhere else make sure the address can be found in
10748 register 1. */
10749 if (retaddr_reg == NULL_RTX
10750 && GET_CODE (addr_location) != SYMBOL_REF
10751 && !plt_call)
9db1d521 10752 {
ab96de7e
AS		 10753 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
10754 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9db1d521 10755 }
9db1d521 10756
ab96de7e
AS		 10757 addr_location = gen_rtx_MEM (QImode, addr_location);
10758 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
4023fb28 10759
ab96de7e
AS		 10760 if (result_reg != NULL_RTX)
10761 call = gen_rtx_SET (VOIDmode, result_reg, call);
4023fb28 10762
ab96de7e
AS		 10763 if (retaddr_reg != NULL_RTX)
10764 {
10765 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
c7453384 10766
ab96de7e
AS		 10767 if (tls_call != NULL_RTX)
10768 vec = gen_rtvec (3, call, clobber,
10769 gen_rtx_USE (VOIDmode, tls_call));
10770 else
10771 vec = gen_rtvec (2, call, clobber);
4023fb28 10772
ab96de7e
AS		 10773 call = gen_rtx_PARALLEL (VOIDmode, vec);
10774 }
4023fb28 10775
ab96de7e 10776 insn = emit_call_insn (call);
4023fb28 10777
ab96de7e
AS		 10778 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
10779 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
10780 {
10781 /* s390_function_ok_for_sibcall should
10782 have denied sibcalls in this case. */
8d933e31 10783 gcc_assert (retaddr_reg != NULL_RTX);
68c0ef75 10784 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, 12));
ab96de7e
AS		 10785 }
10786 return insn;
10787}
4023fb28 10788
5efd84c5 10789/* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
4023fb28 10790
5efd84c5 10791static void
ab96de7e
AS		 10792s390_conditional_register_usage (void)
10793{
10794 int i;
4023fb28 10795
4023fb28
UW		 10796 if (flag_pic)
10797 {
ab96de7e
AS		 10798 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10799 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
4023fb28 10800 }
ab96de7e 10801 if (TARGET_CPU_ZARCH)
4023fb28 10802 {
7633f08e
UW		 10803 fixed_regs[BASE_REGNUM] = 0;
10804 call_used_regs[BASE_REGNUM] = 0;
ab96de7e
AS		 10805 fixed_regs[RETURN_REGNUM] = 0;
10806 call_used_regs[RETURN_REGNUM] = 0;
4023fb28 10807 }
ab96de7e 10808 if (TARGET_64BIT)
4023fb28 10809 {
2cf4c39e 10810 for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++)
ab96de7e 10811 call_used_regs[i] = call_really_used_regs[i] = 0;
4023fb28
UW		 10812 }
10813 else
10814 {
2cf4c39e
AK		 10815 call_used_regs[FPR4_REGNUM] = call_really_used_regs[FPR4_REGNUM] = 0;
10816 call_used_regs[FPR6_REGNUM] = call_really_used_regs[FPR6_REGNUM] = 0;
ab96de7e 10817 }
4023fb28 10818
ab96de7e
AS		 10819 if (TARGET_SOFT_FLOAT)
10820 {
2cf4c39e 10821 for (i = FPR0_REGNUM; i <= FPR15_REGNUM; i++)
ab96de7e 10822 call_used_regs[i] = fixed_regs[i] = 1;
4023fb28
UW		 10823 }
10824}
10825
ab96de7e 10826/* Corresponding function to eh_return expander. */
fb49053f 10827
ab96de7e
AS		 10828static GTY(()) rtx s390_tpf_eh_return_symbol;
10829void
10830s390_emit_tpf_eh_return (rtx target)
fb49053f 10831{
775c43d3
DM		 10832 rtx_insn *insn;
10833 rtx reg, orig_ra;
e23795ea 10834
ab96de7e
AS		 10835 if (!s390_tpf_eh_return_symbol)
10836 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
10837
10838 reg = gen_rtx_REG (Pmode, 2);
87cb0c0c 10839 orig_ra = gen_rtx_REG (Pmode, 3);
ab96de7e
AS		 10840
10841 emit_move_insn (reg, target);
87cb0c0c 10842 emit_move_insn (orig_ra, get_hard_reg_initial_val (Pmode, RETURN_REGNUM));
ab96de7e
AS		 10843 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
10844 gen_rtx_REG (Pmode, RETURN_REGNUM));
10845 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
87cb0c0c 10846 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), orig_ra);
ab96de7e
AS		 10847
10848 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
fd3cd001
UW		 10849}
10850
ab96de7e
AS		 10851/* Rework the prologue/epilogue to avoid saving/restoring
10852 registers unnecessarily. */
3062825f 10853
c590b625 10854static void
ab96de7e 10855s390_optimize_prologue (void)
483ab821 10856{
775c43d3 10857 rtx_insn *insn, *new_insn, *next_insn;
3062825f 10858
ab96de7e 10859 /* Do a final recompute of the frame-related data. */
6455a49e 10860 s390_optimize_register_info ();
3062825f 10861
ab96de7e
AS		 10862 /* If all special registers are in fact used, there's nothing we
10863 can do, so no point in walking the insn list. */
3062825f 10864
f4aa3848 10865 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
ab96de7e 10866 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
f4aa3848
AK		 10867 && (TARGET_CPU_ZARCH
10868 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
ab96de7e
AS		 10869 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
10870 return;
3062825f 10871
ab96de7e 10872 /* Search for prologue/epilogue insns and replace them. */
3062825f 10873
ab96de7e
AS		 10874 for (insn = get_insns (); insn; insn = next_insn)
10875 {
10876 int first, last, off;
10877 rtx set, base, offset;
6455a49e 10878 rtx pat;
3062825f 10879
ab96de7e 10880 next_insn = NEXT_INSN (insn);
89ce1c8f 10881
6455a49e 10882 if (! NONJUMP_INSN_P (insn) || ! RTX_FRAME_RELATED_P (insn))
ab96de7e 10883 continue;
3062825f 10884
6455a49e
AK		 10885 pat = PATTERN (insn);
10886
10887 /* Remove ldgr/lgdr instructions used for saving and restore
10888 GPRs if possible. */
10889 if (TARGET_Z10
10890 && GET_CODE (pat) == SET
10891 && GET_MODE (SET_SRC (pat)) == DImode
10892 && REG_P (SET_SRC (pat))
10893 && REG_P (SET_DEST (pat)))
10894 {
10895 int src_regno = REGNO (SET_SRC (pat));
10896 int dest_regno = REGNO (SET_DEST (pat));
10897 int gpr_regno;
10898 int fpr_regno;
10899
10900 if (!((GENERAL_REGNO_P (src_regno) && FP_REGNO_P (dest_regno))
10901 || (FP_REGNO_P (src_regno) && GENERAL_REGNO_P (dest_regno))))
10902 continue;
10903
10904 gpr_regno = GENERAL_REGNO_P (src_regno) ? src_regno : dest_regno;
10905 fpr_regno = FP_REGNO_P (src_regno) ? src_regno : dest_regno;
10906
10907 /* GPR must be call-saved, FPR must be call-clobbered. */
10908 if (!call_really_used_regs[fpr_regno]
10909 || call_really_used_regs[gpr_regno])
10910 continue;
10911
6455a49e
AK		 10912 /* It must not happen that what we once saved in an FPR now
10913 needs a stack slot. */
10914 gcc_assert (cfun_gpr_save_slot (gpr_regno) != -1);
10915
10916 if (cfun_gpr_save_slot (gpr_regno) == 0)
10917 {
10918 remove_insn (insn);
10919 continue;
10920 }
10921 }
10922
10923 if (GET_CODE (pat) == PARALLEL
10924 && store_multiple_operation (pat, VOIDmode))
3062825f 10925 {
6455a49e 10926 set = XVECEXP (pat, 0, 0);
ab96de7e 10927 first = REGNO (SET_SRC (set));
6455a49e 10928 last = first + XVECLEN (pat, 0) - 1;
ab96de7e
AS		 10929 offset = const0_rtx;
10930 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10931 off = INTVAL (offset);
3062825f 10932
ab96de7e
AS		 10933 if (GET_CODE (base) != REG || off < 0)
10934 continue;
22a707a4
AK		 10935 if (cfun_frame_layout.first_save_gpr != -1
10936 && (cfun_frame_layout.first_save_gpr < first
10937 || cfun_frame_layout.last_save_gpr > last))
10938 continue;
ab96de7e
AS		 10939 if (REGNO (base) != STACK_POINTER_REGNUM
10940 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10941 continue;
10942 if (first > BASE_REGNUM || last < BASE_REGNUM)
10943 continue;
10944
10945 if (cfun_frame_layout.first_save_gpr != -1)
3062825f 10946 {
775c43d3 10947 rtx s_pat = save_gprs (base,
ab96de7e 10948 off + (cfun_frame_layout.first_save_gpr
9602b6a1 10949 - first) * UNITS_PER_LONG,
ab96de7e
AS		 10950 cfun_frame_layout.first_save_gpr,
10951 cfun_frame_layout.last_save_gpr);
775c43d3 10952 new_insn = emit_insn_before (s_pat, insn);
ab96de7e 10953 INSN_ADDRESSES_NEW (new_insn, -1);
3062825f 10954 }
3062825f 10955
ab96de7e
AS		 10956 remove_insn (insn);
10957 continue;
3062825f
UW		 10958 }
10959
22a707a4 10960 if (cfun_frame_layout.first_save_gpr == -1
6455a49e
AK		 10961 && GET_CODE (pat) == SET
10962 && GENERAL_REG_P (SET_SRC (pat))
10963 && GET_CODE (SET_DEST (pat)) == MEM)
3062825f 10964 {
6455a49e 10965 set = pat;
ab96de7e
AS		 10966 first = REGNO (SET_SRC (set));
10967 offset = const0_rtx;
10968 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10969 off = INTVAL (offset);
3062825f 10970
ab96de7e
AS		 10971 if (GET_CODE (base) != REG || off < 0)
10972 continue;
10973 if (REGNO (base) != STACK_POINTER_REGNUM
10974 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10975 continue;
3062825f 10976
ab96de7e
AS		 10977 remove_insn (insn);
10978 continue;
3062825f
UW		 10979 }
10980
6455a49e
AK		 10981 if (GET_CODE (pat) == PARALLEL
10982 && load_multiple_operation (pat, VOIDmode))
89ce1c8f 10983 {
6455a49e 10984 set = XVECEXP (pat, 0, 0);
ab96de7e 10985 first = REGNO (SET_DEST (set));
6455a49e 10986 last = first + XVECLEN (pat, 0) - 1;
ab96de7e
AS		 10987 offset = const0_rtx;
10988 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10989 off = INTVAL (offset);
89ce1c8f 10990
ab96de7e
AS		 10991 if (GET_CODE (base) != REG || off < 0)
10992 continue;
6455a49e 10993
22a707a4
AK		 10994 if (cfun_frame_layout.first_restore_gpr != -1
10995 && (cfun_frame_layout.first_restore_gpr < first
10996 || cfun_frame_layout.last_restore_gpr > last))
10997 continue;
ab96de7e
AS		 10998 if (REGNO (base) != STACK_POINTER_REGNUM
10999 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
11000 continue;
11001 if (first > BASE_REGNUM || last < BASE_REGNUM)
11002 continue;
3062825f 11003
ab96de7e
AS		 11004 if (cfun_frame_layout.first_restore_gpr != -1)
11005 {
775c43d3 11006 rtx rpat = restore_gprs (base,
ab96de7e 11007 off + (cfun_frame_layout.first_restore_gpr
9602b6a1 11008 - first) * UNITS_PER_LONG,
ab96de7e
AS		 11009 cfun_frame_layout.first_restore_gpr,
11010 cfun_frame_layout.last_restore_gpr);
0621cf3c
RS		 11011
11012 /* Remove REG_CFA_RESTOREs for registers that we no
11013 longer need to save. */
775c43d3
DM		 11014 REG_NOTES (rpat) = REG_NOTES (insn);
11015 for (rtx *ptr = &REG_NOTES (rpat); *ptr; )
0621cf3c
RS		 11016 if (REG_NOTE_KIND (*ptr) == REG_CFA_RESTORE
11017 && ((int) REGNO (XEXP (*ptr, 0))
11018 < cfun_frame_layout.first_restore_gpr))
11019 *ptr = XEXP (*ptr, 1);
11020 else
11021 ptr = &XEXP (*ptr, 1);
775c43d3 11022 new_insn = emit_insn_before (rpat, insn);
0621cf3c 11023 RTX_FRAME_RELATED_P (new_insn) = 1;
ab96de7e
AS		 11024 INSN_ADDRESSES_NEW (new_insn, -1);
11025 }
89ce1c8f 11026
ab96de7e
AS		 11027 remove_insn (insn);
11028 continue;
89ce1c8f
JJ		 11029 }
11030
22a707a4 11031 if (cfun_frame_layout.first_restore_gpr == -1
6455a49e
AK		 11032 && GET_CODE (pat) == SET
11033 && GENERAL_REG_P (SET_DEST (pat))
11034 && GET_CODE (SET_SRC (pat)) == MEM)
3062825f 11035 {
6455a49e 11036 set = pat;
ab96de7e
AS		 11037 first = REGNO (SET_DEST (set));
11038 offset = const0_rtx;
11039 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
11040 off = INTVAL (offset);
c7453384 11041
ab96de7e
AS		 11042 if (GET_CODE (base) != REG || off < 0)
11043 continue;
6455a49e 11044
ab96de7e
AS		 11045 if (REGNO (base) != STACK_POINTER_REGNUM
11046 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
11047 continue;
29742ba4 11048
ab96de7e
AS		 11049 remove_insn (insn);
11050 continue;
11051 }
11052 }
29742ba4
HP		 11053}
11054
65b1d8ea
AK		 11055/* On z10 and later the dynamic branch prediction must see the
11056 backward jump within a certain windows. If not it falls back to
11057 the static prediction. This function rearranges the loop backward
11058 branch in a way which makes the static prediction always correct.
11059 The function returns true if it added an instruction. */
b0f86a7e 11060static bool
775c43d3 11061s390_fix_long_loop_prediction (rtx_insn *insn)
b0f86a7e
AK		 11062{
11063 rtx set = single_set (insn);
11064 rtx code_label, label_ref, new_label;
e60365d3 11065 rtx_insn *uncond_jump;
775c43d3 11066 rtx_insn *cur_insn;
b0f86a7e
AK		 11067 rtx tmp;
11068 int distance;
11069
11070 /* This will exclude branch on count and branch on index patterns
11071 since these are correctly statically predicted. */
11072 if (!set
11073 || SET_DEST (set) != pc_rtx
11074 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
11075 return false;
11076
177bc204
RS		 11077 /* Skip conditional returns. */
11078 if (ANY_RETURN_P (XEXP (SET_SRC (set), 1))
11079 && XEXP (SET_SRC (set), 2) == pc_rtx)
11080 return false;
11081
b0f86a7e
AK		 11082 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
11083 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
11084
11085 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
11086
11087 code_label = XEXP (label_ref, 0);
11088
11089 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
11090 || INSN_ADDRESSES (INSN_UID (insn)) == -1
11091 || (INSN_ADDRESSES (INSN_UID (insn))
65b1d8ea 11092 - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE))
b0f86a7e
AK		 11093 return false;
11094
11095 for (distance = 0, cur_insn = PREV_INSN (insn);
65b1d8ea 11096 distance < PREDICT_DISTANCE - 6;
b0f86a7e
AK		 11097 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
11098 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
11099 return false;
11100
11101 new_label = gen_label_rtx ();
11102 uncond_jump = emit_jump_insn_after (
11103 gen_rtx_SET (VOIDmode, pc_rtx,
11104 gen_rtx_LABEL_REF (VOIDmode, code_label)),
11105 insn);
11106 emit_label_after (new_label, uncond_jump);
11107
11108 tmp = XEXP (SET_SRC (set), 1);
11109 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
11110 XEXP (SET_SRC (set), 2) = tmp;
11111 INSN_CODE (insn) = -1;
11112
11113 XEXP (label_ref, 0) = new_label;
11114 JUMP_LABEL (insn) = new_label;
11115 JUMP_LABEL (uncond_jump) = code_label;
11116
11117 return true;
11118}
11119
d277db6b
WG		 11120/* Returns 1 if INSN reads the value of REG for purposes not related
11121 to addressing of memory, and 0 otherwise. */
11122static int
775c43d3 11123s390_non_addr_reg_read_p (rtx reg, rtx_insn *insn)
d277db6b
WG		 11124{
11125 return reg_referenced_p (reg, PATTERN (insn))
11126 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
11127}
11128
e3cba5e5
AK		 11129/* Starting from INSN find_cond_jump looks downwards in the insn
11130 stream for a single jump insn which is the last user of the
11131 condition code set in INSN. */
775c43d3
DM		 11132static rtx_insn *
11133find_cond_jump (rtx_insn *insn)
e3cba5e5
AK		 11134{
11135 for (; insn; insn = NEXT_INSN (insn))
11136 {
11137 rtx ite, cc;
11138
11139 if (LABEL_P (insn))
11140 break;
11141
11142 if (!JUMP_P (insn))
11143 {
11144 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
11145 break;
11146 continue;
11147 }
11148
11149 /* This will be triggered by a return. */
11150 if (GET_CODE (PATTERN (insn)) != SET)
11151 break;
11152
11153 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
11154 ite = SET_SRC (PATTERN (insn));
11155
11156 if (GET_CODE (ite) != IF_THEN_ELSE)
11157 break;
11158
11159 cc = XEXP (XEXP (ite, 0), 0);
11160 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
11161 break;
11162
11163 if (find_reg_note (insn, REG_DEAD, cc))
11164 return insn;
11165 break;
11166 }
11167
775c43d3 11168 return NULL;
e3cba5e5
AK		 11169}
11170
11171/* Swap the condition in COND and the operands in OP0 and OP1 so that
11172 the semantics does not change. If NULL_RTX is passed as COND the
11173 function tries to find the conditional jump starting with INSN. */
11174static void
775c43d3 11175s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx_insn *insn)
e3cba5e5
AK		 11176{
11177 rtx tmp = *op0;
11178
11179 if (cond == NULL_RTX)
11180 {
e8a54173
DM		 11181 rtx_insn *jump = find_cond_jump (NEXT_INSN (insn));
11182 rtx set = jump ? single_set (jump) : NULL_RTX;
e3cba5e5 11183
e8a54173 11184 if (set == NULL_RTX)
e3cba5e5
AK		 11185 return;
11186
e8a54173 11187 cond = XEXP (SET_SRC (set), 0);
e3cba5e5
AK		 11188 }
11189
11190 *op0 = *op1;
11191 *op1 = tmp;
11192 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
11193}
d277db6b
WG		 11194
11195/* On z10, instructions of the compare-and-branch family have the
11196 property to access the register occurring as second operand with
11197 its bits complemented. If such a compare is grouped with a second
11198 instruction that accesses the same register non-complemented, and
11199 if that register's value is delivered via a bypass, then the
11200 pipeline recycles, thereby causing significant performance decline.
11201 This function locates such situations and exchanges the two
b0f86a7e
AK		 11202 operands of the compare. The function return true whenever it
11203 added an insn. */
11204static bool
775c43d3 11205s390_z10_optimize_cmp (rtx_insn *insn)
d277db6b 11206{
775c43d3 11207 rtx_insn *prev_insn, *next_insn;
b0f86a7e
AK		 11208 bool insn_added_p = false;
11209 rtx cond, *op0, *op1;
d277db6b 11210
b0f86a7e 11211 if (GET_CODE (PATTERN (insn)) == PARALLEL)
d277db6b 11212 {
b0f86a7e
AK		 11213 /* Handle compare and branch and branch on count
11214 instructions. */
11215 rtx pattern = single_set (insn);
e3cba5e5 11216
b0f86a7e
AK		 11217 if (!pattern
11218 || SET_DEST (pattern) != pc_rtx
11219 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
11220 return false;
d277db6b 11221
b0f86a7e
AK		 11222 cond = XEXP (SET_SRC (pattern), 0);
11223 op0 = &XEXP (cond, 0);
11224 op1 = &XEXP (cond, 1);
11225 }
11226 else if (GET_CODE (PATTERN (insn)) == SET)
11227 {
11228 rtx src, dest;
d277db6b 11229
b0f86a7e
AK		 11230 /* Handle normal compare instructions. */
11231 src = SET_SRC (PATTERN (insn));
11232 dest = SET_DEST (PATTERN (insn));
e3cba5e5 11233
b0f86a7e
AK		 11234 if (!REG_P (dest)
11235 || !CC_REGNO_P (REGNO (dest))
11236 || GET_CODE (src) != COMPARE)
11237 return false;
e3cba5e5 11238
b0f86a7e
AK		 11239 /* s390_swap_cmp will try to find the conditional
11240 jump when passing NULL_RTX as condition. */
11241 cond = NULL_RTX;
11242 op0 = &XEXP (src, 0);
11243 op1 = &XEXP (src, 1);
11244 }
11245 else
11246 return false;
e3cba5e5 11247
b0f86a7e
AK		 11248 if (!REG_P (*op0) || !REG_P (*op1))
11249 return false;
e3cba5e5 11250
2dfdbf2b
AK		 11251 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
11252 return false;
11253
b0f86a7e
AK		 11254 /* Swap the COMPARE arguments and its mask if there is a
11255 conflicting access in the previous insn. */
33ab2bd4 11256 prev_insn = prev_active_insn (insn);
b0f86a7e
AK		 11257 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
11258 && reg_referenced_p (*op1, PATTERN (prev_insn)))
11259 s390_swap_cmp (cond, op0, op1, insn);
11260
11261 /* Check if there is a conflict with the next insn. If there
11262 was no conflict with the previous insn, then swap the
11263 COMPARE arguments and its mask. If we already swapped
11264 the operands, or if swapping them would cause a conflict
11265 with the previous insn, issue a NOP after the COMPARE in
11266 order to separate the two instuctions. */
33ab2bd4 11267 next_insn = next_active_insn (insn);
b0f86a7e
AK		 11268 if (next_insn != NULL_RTX && INSN_P (next_insn)
11269 && s390_non_addr_reg_read_p (*op1, next_insn))
11270 {
e3cba5e5 11271 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
b0f86a7e 11272 && s390_non_addr_reg_read_p (*op0, prev_insn))
e3cba5e5 11273 {
b0f86a7e
AK		 11274 if (REGNO (*op1) == 0)
11275 emit_insn_after (gen_nop1 (), insn);
e3cba5e5 11276 else
b0f86a7e
AK		 11277 emit_insn_after (gen_nop (), insn);
11278 insn_added_p = true;
d277db6b 11279 }
b0f86a7e
AK		 11280 else
11281 s390_swap_cmp (cond, op0, op1, insn);
d277db6b 11282 }
b0f86a7e 11283 return insn_added_p;
d277db6b
WG		 11284}
11285
ab96de7e 11286/* Perform machine-dependent processing. */
ed9676cf 11287
ab96de7e
AS		 11288static void
11289s390_reorg (void)
ed9676cf 11290{
ab96de7e 11291 bool pool_overflow = false;
ed9676cf 11292
ab96de7e
AS		 11293 /* Make sure all splits have been performed; splits after
11294 machine_dependent_reorg might confuse insn length counts. */
11295 split_all_insns_noflow ();
38899e29 11296
ab96de7e
AS		 11297 /* Install the main literal pool and the associated base
11298 register load insns.
38899e29 11299
ab96de7e
AS		 11300 In addition, there are two problematic situations we need
11301 to correct:
ed9676cf 11302
ab96de7e
AS		 11303 - the literal pool might be > 4096 bytes in size, so that
11304 some of its elements cannot be directly accessed
ed9676cf 11305
ab96de7e
AS		 11306 - a branch target might be > 64K away from the branch, so that
11307 it is not possible to use a PC-relative instruction.
ed9676cf 11308
ab96de7e
AS		 11309 To fix those, we split the single literal pool into multiple
11310 pool chunks, reloading the pool base register at various
11311 points throughout the function to ensure it always points to
11312 the pool chunk the following code expects, and / or replace
11313 PC-relative branches by absolute branches.
ed9676cf 11314
ab96de7e
AS		 11315 However, the two problems are interdependent: splitting the
11316 literal pool can move a branch further away from its target,
11317 causing the 64K limit to overflow, and on the other hand,
11318 replacing a PC-relative branch by an absolute branch means
11319 we need to put the branch target address into the literal
11320 pool, possibly causing it to overflow.
ffdda752 11321
ab96de7e
AS		 11322 So, we loop trying to fix up both problems until we manage
11323 to satisfy both conditions at the same time. Note that the
11324 loop is guaranteed to terminate as every pass of the loop
11325 strictly decreases the total number of PC-relative branches
11326 in the function. (This is not completely true as there
11327 might be branch-over-pool insns introduced by chunkify_start.
11328 Those never need to be split however.) */
ffdda752 11329
ab96de7e
AS		 11330 for (;;)
11331 {
11332 struct constant_pool *pool = NULL;
a628ab6d 11333
ab96de7e
AS		 11334 /* Collect the literal pool. */
11335 if (!pool_overflow)
11336 {
11337 pool = s390_mainpool_start ();
11338 if (!pool)
11339 pool_overflow = true;
11340 }
a628ab6d 11341
ab96de7e
AS		 11342 /* If literal pool overflowed, start to chunkify it. */
11343 if (pool_overflow)
11344 pool = s390_chunkify_start ();
a628ab6d 11345
ab96de7e
AS		 11346 /* Split out-of-range branches. If this has created new
11347 literal pool entries, cancel current chunk list and
11348 recompute it. zSeries machines have large branch
11349 instructions, so we never need to split a branch. */
11350 if (!TARGET_CPU_ZARCH && s390_split_branches ())
11351 {
11352 if (pool_overflow)
11353 s390_chunkify_cancel (pool);
11354 else
11355 s390_mainpool_cancel (pool);
a628ab6d 11356
ab96de7e
AS		 11357 continue;
11358 }
11359
11360 /* If we made it up to here, both conditions are satisfied.
11361 Finish up literal pool related changes. */
11362 if (pool_overflow)
11363 s390_chunkify_finish (pool);
11364 else
11365 s390_mainpool_finish (pool);
11366
11367 /* We're done splitting branches. */
11368 cfun->machine->split_branches_pending_p = false;
11369 break;
a628ab6d 11370 }
a628ab6d 11371
d24959df
UW		 11372 /* Generate out-of-pool execute target insns. */
11373 if (TARGET_CPU_ZARCH)
11374 {
775c43d3
DM		 11375 rtx_insn *insn, *target;
11376 rtx label;
d24959df
UW		 11377
11378 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11379 {
11380 label = s390_execute_label (insn);
11381 if (!label)
11382 continue;
11383
11384 gcc_assert (label != const0_rtx);
11385
11386 target = emit_label (XEXP (label, 0));
11387 INSN_ADDRESSES_NEW (target, -1);
11388
11389 target = emit_insn (s390_execute_target (insn));
11390 INSN_ADDRESSES_NEW (target, -1);
11391 }
11392 }
11393
11394 /* Try to optimize prologue and epilogue further. */
ab96de7e 11395 s390_optimize_prologue ();
d277db6b 11396
65b1d8ea
AK		 11397 /* Walk over the insns and do some >=z10 specific changes. */
11398 if (s390_tune == PROCESSOR_2097_Z10
22ac2c2f
AK		 11399 || s390_tune == PROCESSOR_2817_Z196
11400 || s390_tune == PROCESSOR_2827_ZEC12)
b0f86a7e 11401 {
775c43d3 11402 rtx_insn *insn;
b0f86a7e
AK		 11403 bool insn_added_p = false;
11404
11405 /* The insn lengths and addresses have to be up to date for the
11406 following manipulations. */
11407 shorten_branches (get_insns ());
11408
11409 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11410 {
11411 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
11412 continue;
11413
11414 if (JUMP_P (insn))
65b1d8ea 11415 insn_added_p |= s390_fix_long_loop_prediction (insn);
b0f86a7e 11416
65b1d8ea
AK		 11417 if ((GET_CODE (PATTERN (insn)) == PARALLEL
11418 || GET_CODE (PATTERN (insn)) == SET)
11419 && s390_tune == PROCESSOR_2097_Z10)
b0f86a7e
AK		 11420 insn_added_p |= s390_z10_optimize_cmp (insn);
11421 }
11422
11423 /* Adjust branches if we added new instructions. */
11424 if (insn_added_p)
11425 shorten_branches (get_insns ());
11426 }
ab96de7e 11427}
ed9676cf 11428
3a892e44
AK		 11429/* Return true if INSN is a fp load insn writing register REGNO. */
11430static inline bool
647d790d 11431s390_fpload_toreg (rtx_insn *insn, unsigned int regno)
3a892e44
AK		 11432{
11433 rtx set;
11434 enum attr_type flag = s390_safe_attr_type (insn);
11435
11436 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
11437 return false;
11438
11439 set = single_set (insn);
11440
11441 if (set == NULL_RTX)
11442 return false;
11443
11444 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
11445 return false;
11446
11447 if (REGNO (SET_DEST (set)) != regno)
11448 return false;
11449
11450 return true;
11451}
11452
11453/* This value describes the distance to be avoided between an
11454 aritmetic fp instruction and an fp load writing the same register.
11455 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
11456 fine but the exact value has to be avoided. Otherwise the FP
11457 pipeline will throw an exception causing a major penalty. */
11458#define Z10_EARLYLOAD_DISTANCE 7
11459
11460/* Rearrange the ready list in order to avoid the situation described
11461 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
11462 moved to the very end of the ready list. */
11463static void
ce1ce33a 11464s390_z10_prevent_earlyload_conflicts (rtx_insn **ready, int *nready_p)
3a892e44
AK		 11465{
11466 unsigned int regno;
11467 int nready = *nready_p;
ce1ce33a 11468 rtx_insn *tmp;
3a892e44 11469 int i;
775c43d3 11470 rtx_insn *insn;
3a892e44
AK		 11471 rtx set;
11472 enum attr_type flag;
11473 int distance;
11474
11475 /* Skip DISTANCE - 1 active insns. */
11476 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
11477 distance > 0 && insn != NULL_RTX;
11478 distance--, insn = prev_active_insn (insn))
11479 if (CALL_P (insn) || JUMP_P (insn))
11480 return;
11481
11482 if (insn == NULL_RTX)
11483 return;
11484
11485 set = single_set (insn);
11486
11487 if (set == NULL_RTX || !REG_P (SET_DEST (set))
11488 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
11489 return;
11490
11491 flag = s390_safe_attr_type (insn);
11492
11493 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
11494 return;
11495
11496 regno = REGNO (SET_DEST (set));
11497 i = nready - 1;
11498
11499 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
11500 i--;
11501
11502 if (!i)
11503 return;
11504
11505 tmp = ready[i];
ce1ce33a 11506 memmove (&ready[1], &ready[0], sizeof (rtx_insn *) * i);
3a892e44
AK		 11507 ready[0] = tmp;
11508}
11509
22ac2c2f
AK		 11510
11511/* The s390_sched_state variable tracks the state of the current or
11512 the last instruction group.
11513
11514 0,1,2 number of instructions scheduled in the current group
11515 3 the last group is complete - normal insns
11516 4 the last group was a cracked/expanded insn */
11517
11518static int s390_sched_state;
11519
11520#define S390_OOO_SCHED_STATE_NORMAL 3
11521#define S390_OOO_SCHED_STATE_CRACKED 4
11522
11523#define S390_OOO_SCHED_ATTR_MASK_CRACKED 0x1
11524#define S390_OOO_SCHED_ATTR_MASK_EXPANDED 0x2
11525#define S390_OOO_SCHED_ATTR_MASK_ENDGROUP 0x4
11526#define S390_OOO_SCHED_ATTR_MASK_GROUPALONE 0x8
11527
11528static unsigned int
84034c69 11529s390_get_sched_attrmask (rtx_insn *insn)
22ac2c2f
AK		 11530{
11531 unsigned int mask = 0;
11532
11533 if (get_attr_ooo_cracked (insn))
11534 mask |= S390_OOO_SCHED_ATTR_MASK_CRACKED;
11535 if (get_attr_ooo_expanded (insn))
11536 mask |= S390_OOO_SCHED_ATTR_MASK_EXPANDED;
11537 if (get_attr_ooo_endgroup (insn))
11538 mask |= S390_OOO_SCHED_ATTR_MASK_ENDGROUP;
11539 if (get_attr_ooo_groupalone (insn))
11540 mask |= S390_OOO_SCHED_ATTR_MASK_GROUPALONE;
11541 return mask;
11542}
11543
11544/* Return the scheduling score for INSN. The higher the score the
11545 better. The score is calculated from the OOO scheduling attributes
11546 of INSN and the scheduling state s390_sched_state. */
11547static int
84034c69 11548s390_sched_score (rtx_insn *insn)
22ac2c2f
AK		 11549{
11550 unsigned int mask = s390_get_sched_attrmask (insn);
11551 int score = 0;
11552
11553 switch (s390_sched_state)
11554 {
11555 case 0:
11556 /* Try to put insns into the first slot which would otherwise
11557 break a group. */
11558 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11559 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11560 score += 5;
11561 if ((mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11562 score += 10;
11563 case 1:
11564 /* Prefer not cracked insns while trying to put together a
11565 group. */
11566 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11567 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0
11568 && (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) == 0)
11569 score += 10;
11570 if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) == 0)
11571 score += 5;
11572 break;
11573 case 2:
11574 /* Prefer not cracked insns while trying to put together a
11575 group. */
11576 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11577 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0
11578 && (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) == 0)
11579 score += 10;
11580 /* Prefer endgroup insns in the last slot. */
11581 if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) != 0)
11582 score += 10;
11583 break;
11584 case S390_OOO_SCHED_STATE_NORMAL:
11585 /* Prefer not cracked insns if the last was not cracked. */
11586 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11587 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0)
11588 score += 5;
11589 if ((mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11590 score += 10;
11591 break;
11592 case S390_OOO_SCHED_STATE_CRACKED:
11593 /* Try to keep cracked insns together to prevent them from
11594 interrupting groups. */
11595 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11596 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11597 score += 5;
11598 break;
11599 }
11600 return score;
11601}
11602
3a892e44 11603/* This function is called via hook TARGET_SCHED_REORDER before
631b20a7 11604 issuing one insn from list READY which contains *NREADYP entries.
3a892e44
AK		 11605 For target z10 it reorders load instructions to avoid early load
11606 conflicts in the floating point pipeline */
11607static int
22ac2c2f 11608s390_sched_reorder (FILE *file, int verbose,
ce1ce33a 11609 rtx_insn **ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
3a892e44
AK		 11610{
11611 if (s390_tune == PROCESSOR_2097_Z10)
11612 if (reload_completed && *nreadyp > 1)
11613 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
11614
22ac2c2f
AK		 11615 if (s390_tune == PROCESSOR_2827_ZEC12
11616 && reload_completed
11617 && *nreadyp > 1)
11618 {
11619 int i;
11620 int last_index = *nreadyp - 1;
11621 int max_index = -1;
11622 int max_score = -1;
ce1ce33a 11623 rtx_insn *tmp;
22ac2c2f
AK		 11624
11625 /* Just move the insn with the highest score to the top (the
11626 end) of the list. A full sort is not needed since a conflict
11627 in the hazard recognition cannot happen. So the top insn in
11628 the ready list will always be taken. */
11629 for (i = last_index; i >= 0; i--)
11630 {
11631 int score;
11632
11633 if (recog_memoized (ready[i]) < 0)
11634 continue;
11635
11636 score = s390_sched_score (ready[i]);
11637 if (score > max_score)
11638 {
11639 max_score = score;
11640 max_index = i;
11641 }
11642 }
11643
11644 if (max_index != -1)
11645 {
11646 if (max_index != last_index)
11647 {
11648 tmp = ready[max_index];
11649 ready[max_index] = ready[last_index];
11650 ready[last_index] = tmp;
11651
11652 if (verbose > 5)
11653 fprintf (file,
11654 "move insn %d to the top of list\n",
11655 INSN_UID (ready[last_index]));
11656 }
11657 else if (verbose > 5)
11658 fprintf (file,
11659 "best insn %d already on top\n",
11660 INSN_UID (ready[last_index]));
11661 }
11662
11663 if (verbose > 5)
11664 {
11665 fprintf (file, "ready list ooo attributes - sched state: %d\n",
11666 s390_sched_state);
11667
11668 for (i = last_index; i >= 0; i--)
11669 {
11670 if (recog_memoized (ready[i]) < 0)
11671 continue;
11672 fprintf (file, "insn %d score: %d: ", INSN_UID (ready[i]),
11673 s390_sched_score (ready[i]));
11674#define PRINT_OOO_ATTR(ATTR) fprintf (file, "%s ", get_attr_##ATTR (ready[i]) ? #ATTR : "!" #ATTR);
11675 PRINT_OOO_ATTR (ooo_cracked);
11676 PRINT_OOO_ATTR (ooo_expanded);
11677 PRINT_OOO_ATTR (ooo_endgroup);
11678 PRINT_OOO_ATTR (ooo_groupalone);
11679#undef PRINT_OOO_ATTR
11680 fprintf (file, "\n");
11681 }
11682 }
11683 }
11684
3a892e44
AK		 11685 return s390_issue_rate ();
11686}
11687
22ac2c2f 11688
3a892e44
AK		 11689/* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
11690 the scheduler has issued INSN. It stores the last issued insn into
11691 last_scheduled_insn in order to make it available for
11692 s390_sched_reorder. */
11693static int
ac44248e 11694s390_sched_variable_issue (FILE *file, int verbose, rtx_insn *insn, int more)
3a892e44
AK		 11695{
11696 last_scheduled_insn = insn;
11697
22ac2c2f
AK		 11698 if (s390_tune == PROCESSOR_2827_ZEC12
11699 && reload_completed
11700 && recog_memoized (insn) >= 0)
11701 {
11702 unsigned int mask = s390_get_sched_attrmask (insn);
11703
11704 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11705 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11706 s390_sched_state = S390_OOO_SCHED_STATE_CRACKED;
11707 else if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) != 0
11708 || (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11709 s390_sched_state = S390_OOO_SCHED_STATE_NORMAL;
11710 else
11711 {
11712 /* Only normal insns are left (mask == 0). */
11713 switch (s390_sched_state)
11714 {
11715 case 0:
11716 case 1:
11717 case 2:
11718 case S390_OOO_SCHED_STATE_NORMAL:
11719 if (s390_sched_state == S390_OOO_SCHED_STATE_NORMAL)
11720 s390_sched_state = 1;
11721 else
11722 s390_sched_state++;
11723
11724 break;
11725 case S390_OOO_SCHED_STATE_CRACKED:
11726 s390_sched_state = S390_OOO_SCHED_STATE_NORMAL;
11727 break;
11728 }
11729 }
11730 if (verbose > 5)
11731 {
11732 fprintf (file, "insn %d: ", INSN_UID (insn));
11733#define PRINT_OOO_ATTR(ATTR) \
11734 fprintf (file, "%s ", get_attr_##ATTR (insn) ? #ATTR : "");
11735 PRINT_OOO_ATTR (ooo_cracked);
11736 PRINT_OOO_ATTR (ooo_expanded);
11737 PRINT_OOO_ATTR (ooo_endgroup);
11738 PRINT_OOO_ATTR (ooo_groupalone);
11739#undef PRINT_OOO_ATTR
11740 fprintf (file, "\n");
11741 fprintf (file, "sched state: %d\n", s390_sched_state);
11742 }
11743 }
11744
3a892e44
AK		 11745 if (GET_CODE (PATTERN (insn)) != USE
11746 && GET_CODE (PATTERN (insn)) != CLOBBER)
11747 return more - 1;
11748 else
11749 return more;
11750}
ed9676cf 11751
244e6c5c
AK		 11752static void
11753s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
11754 int verbose ATTRIBUTE_UNUSED,
11755 int max_ready ATTRIBUTE_UNUSED)
11756{
775c43d3 11757 last_scheduled_insn = NULL;
22ac2c2f 11758 s390_sched_state = 0;
244e6c5c
AK		 11759}
11760
40ac4f73 11761/* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
65b1d8ea
AK		 11762 a new number struct loop *loop should be unrolled if tuned for cpus with
11763 a built-in stride prefetcher.
11764 The loop is analyzed for memory accesses by calling check_dpu for
40ac4f73
CB		 11765 each rtx of the loop. Depending on the loop_depth and the amount of
11766 memory accesses a new number <=nunroll is returned to improve the
11767 behaviour of the hardware prefetch unit. */
11768static unsigned
11769s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
11770{
11771 basic_block *bbs;
775c43d3 11772 rtx_insn *insn;
40ac4f73
CB		 11773 unsigned i;
11774 unsigned mem_count = 0;
11775
22ac2c2f
AK		 11776 if (s390_tune != PROCESSOR_2097_Z10
11777 && s390_tune != PROCESSOR_2817_Z196
11778 && s390_tune != PROCESSOR_2827_ZEC12)
40ac4f73
CB		 11779 return nunroll;
11780
11781 /* Count the number of memory references within the loop body. */
11782 bbs = get_loop_body (loop);
9dc7a9da 11783 subrtx_iterator::array_type array;
40ac4f73 11784 for (i = 0; i < loop->num_nodes; i++)
9dc7a9da
RS		 11785 FOR_BB_INSNS (bbs[i], insn)
11786 if (INSN_P (insn) && INSN_CODE (insn) != -1)
11787 FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST)
11788 if (MEM_P (*iter))
11789 mem_count += 1;
40ac4f73
CB		 11790 free (bbs);
11791
11792 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
11793 if (mem_count == 0)
11794 return nunroll;
11795
11796 switch (loop_depth(loop))
11797 {
11798 case 1:
11799 return MIN (nunroll, 28 / mem_count);
11800 case 2:
11801 return MIN (nunroll, 22 / mem_count);
11802 default:
11803 return MIN (nunroll, 16 / mem_count);
11804 }
11805}
11806
4099494d
RS		 11807static void
11808s390_option_override (void)
11809{
11810 unsigned int i;
11811 cl_deferred_option *opt;
11812 vec<cl_deferred_option> *v =
11813 (vec<cl_deferred_option> *) s390_deferred_options;
11814
11815 if (v)
11816 FOR_EACH_VEC_ELT (*v, i, opt)
11817 {
11818 switch (opt->opt_index)
11819 {
11820 case OPT_mhotpatch:
11821 s390_hotpatch_trampoline_halfwords = (opt->value) ?
11822 s390_hotpatch_trampoline_halfwords_default : -1;
11823 break;
11824 case OPT_mhotpatch_:
11825 {
11826 int val;
11827
11828 val = integral_argument (opt->arg);
11829 if (val == -1)
11830 {
11831 /* argument is not a plain number */
11832 error ("argument to %qs should be a non-negative integer",
11833 "-mhotpatch=");
11834 break;
11835 }
11836 else if (val > s390_hotpatch_trampoline_halfwords_max)
11837 {
11838 error ("argument to %qs is too large (max. %d)",
11839 "-mhotpatch=", s390_hotpatch_trampoline_halfwords_max);
11840 break;
11841 }
11842 s390_hotpatch_trampoline_halfwords = val;
11843 break;
11844 }
11845 default:
11846 gcc_unreachable ();
11847 }
11848 }
11849
11850 /* Set up function hooks. */
11851 init_machine_status = s390_init_machine_status;
11852
11853 /* Architecture mode defaults according to ABI. */
11854 if (!(target_flags_explicit & MASK_ZARCH))
11855 {
11856 if (TARGET_64BIT)
11857 target_flags |= MASK_ZARCH;
11858 else
11859 target_flags &= ~MASK_ZARCH;
11860 }
11861
11862 /* Set the march default in case it hasn't been specified on
11863 cmdline. */
11864 if (s390_arch == PROCESSOR_max)
11865 {
11866 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
11867 s390_arch = TARGET_ZARCH ? PROCESSOR_2064_Z900 : PROCESSOR_9672_G5;
11868 s390_arch_flags = processor_flags_table[(int)s390_arch];
11869 }
11870
11871 /* Determine processor to tune for. */
11872 if (s390_tune == PROCESSOR_max)
11873 {
11874 s390_tune = s390_arch;
11875 s390_tune_flags = s390_arch_flags;
11876 }
11877
11878 /* Sanity checks. */
11879 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
11880 error ("z/Architecture mode not supported on %s", s390_arch_string);
11881 if (TARGET_64BIT && !TARGET_ZARCH)
11882 error ("64-bit ABI not supported in ESA/390 mode");
11883
11884 /* Use hardware DFP if available and not explicitly disabled by
11885 user. E.g. with -m31 -march=z10 -mzarch */
11886 if (!(target_flags_explicit & MASK_HARD_DFP) && TARGET_DFP)
11887 target_flags |= MASK_HARD_DFP;
11888
11889 /* Enable hardware transactions if available and not explicitly
11890 disabled by user. E.g. with -m31 -march=zEC12 -mzarch */
11891 if (!(target_flags_explicit & MASK_OPT_HTM) && TARGET_CPU_HTM && TARGET_ZARCH)
11892 target_flags |= MASK_OPT_HTM;
11893
11894 if (TARGET_HARD_DFP && !TARGET_DFP)
11895 {
11896 if (target_flags_explicit & MASK_HARD_DFP)
11897 {
11898 if (!TARGET_CPU_DFP)
11899 error ("hardware decimal floating point instructions"
11900 " not available on %s", s390_arch_string);
11901 if (!TARGET_ZARCH)
11902 error ("hardware decimal floating point instructions"
11903 " not available in ESA/390 mode");
11904 }
11905 else
11906 target_flags &= ~MASK_HARD_DFP;
11907 }
11908
11909 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
11910 {
11911 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
11912 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
11913
11914 target_flags &= ~MASK_HARD_DFP;
11915 }
11916
11917 /* Set processor cost function. */
11918 switch (s390_tune)
11919 {
11920 case PROCESSOR_2084_Z990:
11921 s390_cost = &z990_cost;
11922 break;
11923 case PROCESSOR_2094_Z9_109:
11924 s390_cost = &z9_109_cost;
11925 break;
11926 case PROCESSOR_2097_Z10:
11927 s390_cost = &z10_cost;
11928 break;
11929 case PROCESSOR_2817_Z196:
11930 s390_cost = &z196_cost;
11931 break;
11932 case PROCESSOR_2827_ZEC12:
11933 s390_cost = &zEC12_cost;
11934 break;
11935 default:
11936 s390_cost = &z900_cost;
11937 }
11938
11939 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
11940 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
11941 "in combination");
11942
11943 if (s390_stack_size)
11944 {
11945 if (s390_stack_guard >= s390_stack_size)
11946 error ("stack size must be greater than the stack guard value");
11947 else if (s390_stack_size > 1 << 16)
11948 error ("stack size must not be greater than 64k");
11949 }
11950 else if (s390_stack_guard)
11951 error ("-mstack-guard implies use of -mstack-size");
11952
11953#ifdef TARGET_DEFAULT_LONG_DOUBLE_128
11954 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
11955 target_flags |= MASK_LONG_DOUBLE_128;
11956#endif
11957
11958 if (s390_tune == PROCESSOR_2097_Z10
11959 || s390_tune == PROCESSOR_2817_Z196
11960 || s390_tune == PROCESSOR_2827_ZEC12)
11961 {
11962 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100,
11963 global_options.x_param_values,
11964 global_options_set.x_param_values);
11965 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32,
11966 global_options.x_param_values,
11967 global_options_set.x_param_values);
11968 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000,
11969 global_options.x_param_values,
11970 global_options_set.x_param_values);
11971 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64,
11972 global_options.x_param_values,
11973 global_options_set.x_param_values);
11974 }
11975
11976 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256,
11977 global_options.x_param_values,
11978 global_options_set.x_param_values);
11979 /* values for loop prefetching */
11980 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256,
11981 global_options.x_param_values,
11982 global_options_set.x_param_values);
11983 maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128,
11984 global_options.x_param_values,
11985 global_options_set.x_param_values);
11986 /* s390 has more than 2 levels and the size is much larger. Since
11987 we are always running virtualized assume that we only get a small
11988 part of the caches above l1. */
11989 maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500,
11990 global_options.x_param_values,
11991 global_options_set.x_param_values);
11992 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2,
11993 global_options.x_param_values,
11994 global_options_set.x_param_values);
11995 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6,
11996 global_options.x_param_values,
11997 global_options_set.x_param_values);
11998
11999 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
12000 requires the arch flags to be evaluated already. Since prefetching
12001 is beneficial on s390, we enable it if available. */
12002 if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
12003 flag_prefetch_loop_arrays = 1;
12004
12005 /* Use the alternative scheduling-pressure algorithm by default. */
12006 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, 2,
12007 global_options.x_param_values,
12008 global_options_set.x_param_values);
12009
12010 if (TARGET_TPF)
12011 {
12012 /* Don't emit DWARF3/4 unless specifically selected. The TPF
12013 debuggers do not yet support DWARF 3/4. */
12014 if (!global_options_set.x_dwarf_strict)
12015 dwarf_strict = 1;
12016 if (!global_options_set.x_dwarf_version)
12017 dwarf_version = 2;
12018 }
12019
12020 /* Register a target-specific optimization-and-lowering pass
12021 to run immediately before prologue and epilogue generation.
12022
12023 Registering the pass must be done at start up. It's
12024 convenient to do it here. */
12025 opt_pass *new_pass = new pass_s390_early_mach (g);
12026 struct register_pass_info insert_pass_s390_early_mach =
12027 {
12028 new_pass, /* pass */
12029 "pro_and_epilogue", /* reference_pass_name */
12030 1, /* ref_pass_instance_number */
12031 PASS_POS_INSERT_BEFORE /* po_op */
12032 };
12033 register_pass (&insert_pass_s390_early_mach);
12034}
12035
b5e3200c
JG		 12036/* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */
12037
12038static bool
12039s390_use_by_pieces_infrastructure_p (unsigned int size,
12040 unsigned int align ATTRIBUTE_UNUSED,
12041 enum by_pieces_operation op ATTRIBUTE_UNUSED,
12042 bool speed_p ATTRIBUTE_UNUSED)
12043{
12044 return (size == 1 || size == 2
12045 || size == 4 || (TARGET_ZARCH && size == 8));
12046}
12047
ab96de7e 12048/* Initialize GCC target structure. */
38899e29 12049
ab96de7e
AS		 12050#undef TARGET_ASM_ALIGNED_HI_OP
12051#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
12052#undef TARGET_ASM_ALIGNED_DI_OP
12053#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
12054#undef TARGET_ASM_INTEGER
12055#define TARGET_ASM_INTEGER s390_assemble_integer
ed9676cf 12056
ab96de7e
AS		 12057#undef TARGET_ASM_OPEN_PAREN
12058#define TARGET_ASM_OPEN_PAREN ""
38899e29 12059
ab96de7e
AS		 12060#undef TARGET_ASM_CLOSE_PAREN
12061#define TARGET_ASM_CLOSE_PAREN ""
ed9676cf 12062
c5387660
JM		 12063#undef TARGET_OPTION_OVERRIDE
12064#define TARGET_OPTION_OVERRIDE s390_option_override
12065
ab96de7e
AS		 12066#undef TARGET_ENCODE_SECTION_INFO
12067#define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
ed9676cf 12068
9602b6a1
AK		 12069#undef TARGET_SCALAR_MODE_SUPPORTED_P
12070#define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
12071
ab96de7e
AS		 12072#ifdef HAVE_AS_TLS
12073#undef TARGET_HAVE_TLS
12074#define TARGET_HAVE_TLS true
12075#endif
12076#undef TARGET_CANNOT_FORCE_CONST_MEM
12077#define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
ed9676cf 12078
ab96de7e
AS		 12079#undef TARGET_DELEGITIMIZE_ADDRESS
12080#define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
ed9676cf 12081
506d7b68
PB		 12082#undef TARGET_LEGITIMIZE_ADDRESS
12083#define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
12084
ab96de7e
AS		 12085#undef TARGET_RETURN_IN_MEMORY
12086#define TARGET_RETURN_IN_MEMORY s390_return_in_memory
38899e29 12087
5a3fe9b6
AK		 12088#undef TARGET_INIT_BUILTINS
12089#define TARGET_INIT_BUILTINS s390_init_builtins
12090#undef TARGET_EXPAND_BUILTIN
12091#define TARGET_EXPAND_BUILTIN s390_expand_builtin
12092
0f8ab434
AS		 12093#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
12094#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
12095
ab96de7e
AS		 12096#undef TARGET_ASM_OUTPUT_MI_THUNK
12097#define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
12098#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
3101faab 12099#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
ed9676cf 12100
ab96de7e
AS		 12101#undef TARGET_SCHED_ADJUST_PRIORITY
12102#define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
12103#undef TARGET_SCHED_ISSUE_RATE
12104#define TARGET_SCHED_ISSUE_RATE s390_issue_rate
12105#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
12106#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
38899e29 12107
3a892e44
AK		 12108#undef TARGET_SCHED_VARIABLE_ISSUE
12109#define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
12110#undef TARGET_SCHED_REORDER
12111#define TARGET_SCHED_REORDER s390_sched_reorder
244e6c5c
AK		 12112#undef TARGET_SCHED_INIT
12113#define TARGET_SCHED_INIT s390_sched_init
3a892e44 12114
ab96de7e
AS		 12115#undef TARGET_CANNOT_COPY_INSN_P
12116#define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
12117#undef TARGET_RTX_COSTS
12118#define TARGET_RTX_COSTS s390_rtx_costs
12119#undef TARGET_ADDRESS_COST
12120#define TARGET_ADDRESS_COST s390_address_cost
ccaed3ba
AS		 12121#undef TARGET_REGISTER_MOVE_COST
12122#define TARGET_REGISTER_MOVE_COST s390_register_move_cost
12123#undef TARGET_MEMORY_MOVE_COST
12124#define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
38899e29 12125
ab96de7e
AS		 12126#undef TARGET_MACHINE_DEPENDENT_REORG
12127#define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
8a512b77 12128
ab96de7e
AS		 12129#undef TARGET_VALID_POINTER_MODE
12130#define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
38899e29 12131
ab96de7e
AS		 12132#undef TARGET_BUILD_BUILTIN_VA_LIST
12133#define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
d7bd8aeb
JJ		 12134#undef TARGET_EXPAND_BUILTIN_VA_START
12135#define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
ab96de7e
AS		 12136#undef TARGET_GIMPLIFY_VA_ARG_EXPR
12137#define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
4798630c 12138
cde0f3fd
PB		 12139#undef TARGET_PROMOTE_FUNCTION_MODE
12140#define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
ab96de7e
AS		 12141#undef TARGET_PASS_BY_REFERENCE
12142#define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
4798630c 12143
ab96de7e
AS		 12144#undef TARGET_FUNCTION_OK_FOR_SIBCALL
12145#define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
3cb1da52
NF		 12146#undef TARGET_FUNCTION_ARG
12147#define TARGET_FUNCTION_ARG s390_function_arg
12148#undef TARGET_FUNCTION_ARG_ADVANCE
12149#define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
b46616fd
AK		 12150#undef TARGET_FUNCTION_VALUE
12151#define TARGET_FUNCTION_VALUE s390_function_value
12152#undef TARGET_LIBCALL_VALUE
12153#define TARGET_LIBCALL_VALUE s390_libcall_value
4798630c 12154
d56a43a0
AK		 12155#undef TARGET_KEEP_LEAF_WHEN_PROFILED
12156#define TARGET_KEEP_LEAF_WHEN_PROFILED s390_keep_leaf_when_profiled
12157
ab96de7e
AS		 12158#undef TARGET_FIXED_CONDITION_CODE_REGS
12159#define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
4798630c 12160
ab96de7e
AS		 12161#undef TARGET_CC_MODES_COMPATIBLE
12162#define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
4798630c 12163
e7e64a25 12164#undef TARGET_INVALID_WITHIN_DOLOOP
ac44248e 12165#define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_insn_null
c08b81aa 12166
fdbe66f2
EB		 12167#ifdef HAVE_AS_TLS
12168#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
12169#define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
12170#endif
12171
7269aee7 12172#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
608063c3
JB		 12173#undef TARGET_MANGLE_TYPE
12174#define TARGET_MANGLE_TYPE s390_mangle_type
7269aee7
AH		 12175#endif
12176
4dc19cc0
AK		 12177#undef TARGET_SCALAR_MODE_SUPPORTED_P
12178#define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
12179
5df97412
AS		 12180#undef TARGET_PREFERRED_RELOAD_CLASS
12181#define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
12182
833cd70a
AK		 12183#undef TARGET_SECONDARY_RELOAD
12184#define TARGET_SECONDARY_RELOAD s390_secondary_reload
12185
c7ff6e7a
AK		 12186#undef TARGET_LIBGCC_CMP_RETURN_MODE
12187#define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
12188
12189#undef TARGET_LIBGCC_SHIFT_COUNT_MODE
12190#define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
12191
c6c3dba9
PB		 12192#undef TARGET_LEGITIMATE_ADDRESS_P
12193#define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
12194
1a627b35
RS		 12195#undef TARGET_LEGITIMATE_CONSTANT_P
12196#define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
12197
3597e113
VM		 12198#undef TARGET_LRA_P
12199#define TARGET_LRA_P s390_lra_p
12200
7b5cbb57
AS		 12201#undef TARGET_CAN_ELIMINATE
12202#define TARGET_CAN_ELIMINATE s390_can_eliminate
12203
5efd84c5
NF		 12204#undef TARGET_CONDITIONAL_REGISTER_USAGE
12205#define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
12206
40ac4f73
CB		 12207#undef TARGET_LOOP_UNROLL_ADJUST
12208#define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
12209
b81ecf6f
RH		 12210#undef TARGET_ASM_TRAMPOLINE_TEMPLATE
12211#define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
12212#undef TARGET_TRAMPOLINE_INIT
12213#define TARGET_TRAMPOLINE_INIT s390_trampoline_init
12214
9602b6a1
AK		 12215#undef TARGET_UNWIND_WORD_MODE
12216#define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
12217
c354951b
AK		 12218#undef TARGET_CANONICALIZE_COMPARISON
12219#define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison
12220
6455a49e
AK		 12221#undef TARGET_HARD_REGNO_SCRATCH_OK
12222#define TARGET_HARD_REGNO_SCRATCH_OK s390_hard_regno_scratch_ok
12223
d0de9e13
DV		 12224#undef TARGET_ATTRIBUTE_TABLE
12225#define TARGET_ATTRIBUTE_TABLE s390_attribute_table
12226
12227#undef TARGET_CAN_INLINE_P
12228#define TARGET_CAN_INLINE_P s390_can_inline_p
12229
177bc204
RS		 12230#undef TARGET_SET_UP_BY_PROLOGUE
12231#define TARGET_SET_UP_BY_PROLOGUE s300_set_up_by_prologue
12232
b5e3200c
JG		 12233#undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
12234#define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
12235 s390_use_by_pieces_infrastructure_p
12236
ab96de7e 12237struct gcc_target targetm = TARGET_INITIALIZER;
38899e29 12238
29742ba4 12239#include "gt-s390.h"
Mirror of https://gcc.gnu.org/git/gcc.git