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9db1d521 | 1 | /* Subroutines used for code generation on IBM S/390 and zSeries |
cbe34bb5 | 2 | Copyright (C) 1999-2017 Free Software Foundation, Inc. |
9db1d521 | 3 | Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
4 | Ulrich Weigand (uweigand@de.ibm.com) and |
5 | Andreas Krebbel (Andreas.Krebbel@de.ibm.com). | |
9db1d521 | 6 | |
58add37a | 7 | This file is part of GCC. |
9db1d521 | 8 | |
58add37a UW |
9 | GCC is free software; you can redistribute it and/or modify it under |
10 | the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | Software Foundation; either version 3, or (at your option) any later |
58add37a | 12 | version. |
9db1d521 | 13 | |
58add37a UW |
14 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
15 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | for more details. | |
9db1d521 HP |
18 | |
19 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. */ | |
9db1d521 HP |
22 | |
23 | #include "config.h" | |
9db1d521 | 24 | #include "system.h" |
4977bab6 | 25 | #include "coretypes.h" |
c7131fb2 | 26 | #include "backend.h" |
e11c4407 | 27 | #include "target.h" |
ec47b086 | 28 | #include "target-globals.h" |
e11c4407 | 29 | #include "rtl.h" |
c7131fb2 AM |
30 | #include "tree.h" |
31 | #include "gimple.h" | |
e11c4407 AM |
32 | #include "cfghooks.h" |
33 | #include "cfgloop.h" | |
c7131fb2 | 34 | #include "df.h" |
4d0cdd0c | 35 | #include "memmodel.h" |
e11c4407 AM |
36 | #include "tm_p.h" |
37 | #include "stringpool.h" | |
314e6352 | 38 | #include "attribs.h" |
e11c4407 AM |
39 | #include "expmed.h" |
40 | #include "optabs.h" | |
41 | #include "regs.h" | |
42 | #include "emit-rtl.h" | |
43 | #include "recog.h" | |
44 | #include "cgraph.h" | |
45 | #include "diagnostic-core.h" | |
ec47b086 | 46 | #include "diagnostic.h" |
40e23961 | 47 | #include "alias.h" |
40e23961 | 48 | #include "fold-const.h" |
d8a2d370 | 49 | #include "print-tree.h" |
d8a2d370 DN |
50 | #include "stor-layout.h" |
51 | #include "varasm.h" | |
52 | #include "calls.h" | |
9db1d521 HP |
53 | #include "conditions.h" |
54 | #include "output.h" | |
55 | #include "insn-attr.h" | |
56 | #include "flags.h" | |
57 | #include "except.h" | |
36566b39 PK |
58 | #include "dojump.h" |
59 | #include "explow.h" | |
36566b39 | 60 | #include "stmt.h" |
9db1d521 | 61 | #include "expr.h" |
7c82a1ed | 62 | #include "reload.h" |
60393bbc AM |
63 | #include "cfgrtl.h" |
64 | #include "cfganal.h" | |
65 | #include "lcm.h" | |
66 | #include "cfgbuild.h" | |
67 | #include "cfgcleanup.h" | |
0d3c08b6 | 68 | #include "debug.h" |
f1e639b1 | 69 | #include "langhooks.h" |
2fb9a547 AM |
70 | #include "internal-fn.h" |
71 | #include "gimple-fold.h" | |
72 | #include "tree-eh.h" | |
45b0be94 | 73 | #include "gimplify.h" |
ff5b964d | 74 | #include "params.h" |
96e45421 | 75 | #include "opts.h" |
4099494d RS |
76 | #include "tree-pass.h" |
77 | #include "context.h" | |
9b2b7279 | 78 | #include "builtins.h" |
9dc7a9da | 79 | #include "rtl-iter.h" |
085261c8 | 80 | #include "intl.h" |
b0057efd | 81 | #include "tm-constrs.h" |
db6bb1ec AK |
82 | #include "tree-vrp.h" |
83 | #include "symbol-summary.h" | |
84 | #include "ipa-prop.h" | |
85 | #include "ipa-fnsummary.h" | |
9db1d521 | 86 | |
994c5d85 | 87 | /* This file should be included last. */ |
d58627a0 RS |
88 | #include "target-def.h" |
89 | ||
f939c3e6 RS |
90 | static bool s390_hard_regno_mode_ok (unsigned int, machine_mode); |
91 | ||
ec47b086 DV |
92 | /* Remember the last target of s390_set_current_function. */ |
93 | static GTY(()) tree s390_previous_fndecl; | |
94 | ||
017e0eb9 MD |
95 | /* Define the specific costs for a given cpu. */ |
96 | ||
f4aa3848 | 97 | struct processor_costs |
017e0eb9 | 98 | { |
98fd0d70 | 99 | /* multiplication */ |
017e0eb9 MD |
100 | const int m; /* cost of an M instruction. */ |
101 | const int mghi; /* cost of an MGHI instruction. */ | |
102 | const int mh; /* cost of an MH instruction. */ | |
103 | const int mhi; /* cost of an MHI instruction. */ | |
2742a1ed | 104 | const int ml; /* cost of an ML instruction. */ |
017e0eb9 MD |
105 | const int mr; /* cost of an MR instruction. */ |
106 | const int ms; /* cost of an MS instruction. */ | |
107 | const int msg; /* cost of an MSG instruction. */ | |
108 | const int msgf; /* cost of an MSGF instruction. */ | |
109 | const int msgfr; /* cost of an MSGFR instruction. */ | |
110 | const int msgr; /* cost of an MSGR instruction. */ | |
111 | const int msr; /* cost of an MSR instruction. */ | |
112 | const int mult_df; /* cost of multiplication in DFmode. */ | |
f61a2c7d | 113 | const int mxbr; |
98fd0d70 | 114 | /* square root */ |
f61a2c7d | 115 | const int sqxbr; /* cost of square root in TFmode. */ |
2742a1ed MD |
116 | const int sqdbr; /* cost of square root in DFmode. */ |
117 | const int sqebr; /* cost of square root in SFmode. */ | |
98fd0d70 | 118 | /* multiply and add */ |
b75d6bab MD |
119 | const int madbr; /* cost of multiply and add in DFmode. */ |
120 | const int maebr; /* cost of multiply and add in SFmode. */ | |
98fd0d70 | 121 | /* division */ |
f61a2c7d | 122 | const int dxbr; |
98fd0d70 | 123 | const int ddbr; |
98fd0d70 | 124 | const int debr; |
6fa5b390 MD |
125 | const int dlgr; |
126 | const int dlr; | |
127 | const int dr; | |
128 | const int dsgfr; | |
129 | const int dsgr; | |
017e0eb9 MD |
130 | }; |
131 | ||
ec47b086 | 132 | #define s390_cost ((const struct processor_costs *)(s390_cost_pointer)) |
017e0eb9 MD |
133 | |
134 | static const | |
f4aa3848 | 135 | struct processor_costs z900_cost = |
017e0eb9 MD |
136 | { |
137 | COSTS_N_INSNS (5), /* M */ | |
138 | COSTS_N_INSNS (10), /* MGHI */ | |
139 | COSTS_N_INSNS (5), /* MH */ | |
140 | COSTS_N_INSNS (4), /* MHI */ | |
2742a1ed | 141 | COSTS_N_INSNS (5), /* ML */ |
017e0eb9 MD |
142 | COSTS_N_INSNS (5), /* MR */ |
143 | COSTS_N_INSNS (4), /* MS */ | |
144 | COSTS_N_INSNS (15), /* MSG */ | |
145 | COSTS_N_INSNS (7), /* MSGF */ | |
146 | COSTS_N_INSNS (7), /* MSGFR */ | |
147 | COSTS_N_INSNS (10), /* MSGR */ | |
148 | COSTS_N_INSNS (4), /* MSR */ | |
149 | COSTS_N_INSNS (7), /* multiplication in DFmode */ | |
f61a2c7d AK |
150 | COSTS_N_INSNS (13), /* MXBR */ |
151 | COSTS_N_INSNS (136), /* SQXBR */ | |
2742a1ed MD |
152 | COSTS_N_INSNS (44), /* SQDBR */ |
153 | COSTS_N_INSNS (35), /* SQEBR */ | |
b75d6bab MD |
154 | COSTS_N_INSNS (18), /* MADBR */ |
155 | COSTS_N_INSNS (13), /* MAEBR */ | |
f61a2c7d | 156 | COSTS_N_INSNS (134), /* DXBR */ |
98fd0d70 | 157 | COSTS_N_INSNS (30), /* DDBR */ |
98fd0d70 | 158 | COSTS_N_INSNS (27), /* DEBR */ |
6fa5b390 MD |
159 | COSTS_N_INSNS (220), /* DLGR */ |
160 | COSTS_N_INSNS (34), /* DLR */ | |
161 | COSTS_N_INSNS (34), /* DR */ | |
162 | COSTS_N_INSNS (32), /* DSGFR */ | |
163 | COSTS_N_INSNS (32), /* DSGR */ | |
017e0eb9 MD |
164 | }; |
165 | ||
166 | static const | |
f4aa3848 | 167 | struct processor_costs z990_cost = |
017e0eb9 MD |
168 | { |
169 | COSTS_N_INSNS (4), /* M */ | |
170 | COSTS_N_INSNS (2), /* MGHI */ | |
171 | COSTS_N_INSNS (2), /* MH */ | |
172 | COSTS_N_INSNS (2), /* MHI */ | |
2742a1ed | 173 | COSTS_N_INSNS (4), /* ML */ |
017e0eb9 MD |
174 | COSTS_N_INSNS (4), /* MR */ |
175 | COSTS_N_INSNS (5), /* MS */ | |
176 | COSTS_N_INSNS (6), /* MSG */ | |
177 | COSTS_N_INSNS (4), /* MSGF */ | |
178 | COSTS_N_INSNS (4), /* MSGFR */ | |
179 | COSTS_N_INSNS (4), /* MSGR */ | |
180 | COSTS_N_INSNS (4), /* MSR */ | |
181 | COSTS_N_INSNS (1), /* multiplication in DFmode */ | |
f61a2c7d AK |
182 | COSTS_N_INSNS (28), /* MXBR */ |
183 | COSTS_N_INSNS (130), /* SQXBR */ | |
2742a1ed MD |
184 | COSTS_N_INSNS (66), /* SQDBR */ |
185 | COSTS_N_INSNS (38), /* SQEBR */ | |
b75d6bab MD |
186 | COSTS_N_INSNS (1), /* MADBR */ |
187 | COSTS_N_INSNS (1), /* MAEBR */ | |
f61a2c7d | 188 | COSTS_N_INSNS (60), /* DXBR */ |
98fd0d70 | 189 | COSTS_N_INSNS (40), /* DDBR */ |
142cd70f | 190 | COSTS_N_INSNS (26), /* DEBR */ |
6fa5b390 MD |
191 | COSTS_N_INSNS (176), /* DLGR */ |
192 | COSTS_N_INSNS (31), /* DLR */ | |
193 | COSTS_N_INSNS (31), /* DR */ | |
194 | COSTS_N_INSNS (31), /* DSGFR */ | |
195 | COSTS_N_INSNS (31), /* DSGR */ | |
017e0eb9 MD |
196 | }; |
197 | ||
ec24698e | 198 | static const |
f4aa3848 | 199 | struct processor_costs z9_109_cost = |
ec24698e UW |
200 | { |
201 | COSTS_N_INSNS (4), /* M */ | |
202 | COSTS_N_INSNS (2), /* MGHI */ | |
203 | COSTS_N_INSNS (2), /* MH */ | |
204 | COSTS_N_INSNS (2), /* MHI */ | |
205 | COSTS_N_INSNS (4), /* ML */ | |
206 | COSTS_N_INSNS (4), /* MR */ | |
207 | COSTS_N_INSNS (5), /* MS */ | |
208 | COSTS_N_INSNS (6), /* MSG */ | |
209 | COSTS_N_INSNS (4), /* MSGF */ | |
210 | COSTS_N_INSNS (4), /* MSGFR */ | |
211 | COSTS_N_INSNS (4), /* MSGR */ | |
212 | COSTS_N_INSNS (4), /* MSR */ | |
213 | COSTS_N_INSNS (1), /* multiplication in DFmode */ | |
f61a2c7d AK |
214 | COSTS_N_INSNS (28), /* MXBR */ |
215 | COSTS_N_INSNS (130), /* SQXBR */ | |
ec24698e UW |
216 | COSTS_N_INSNS (66), /* SQDBR */ |
217 | COSTS_N_INSNS (38), /* SQEBR */ | |
218 | COSTS_N_INSNS (1), /* MADBR */ | |
219 | COSTS_N_INSNS (1), /* MAEBR */ | |
f61a2c7d | 220 | COSTS_N_INSNS (60), /* DXBR */ |
ec24698e | 221 | COSTS_N_INSNS (40), /* DDBR */ |
142cd70f | 222 | COSTS_N_INSNS (26), /* DEBR */ |
ec24698e UW |
223 | COSTS_N_INSNS (30), /* DLGR */ |
224 | COSTS_N_INSNS (23), /* DLR */ | |
225 | COSTS_N_INSNS (23), /* DR */ | |
226 | COSTS_N_INSNS (24), /* DSGFR */ | |
227 | COSTS_N_INSNS (24), /* DSGR */ | |
228 | }; | |
017e0eb9 | 229 | |
93538e8e AK |
230 | static const |
231 | struct processor_costs z10_cost = | |
232 | { | |
9381e3f1 WG |
233 | COSTS_N_INSNS (10), /* M */ |
234 | COSTS_N_INSNS (10), /* MGHI */ | |
235 | COSTS_N_INSNS (10), /* MH */ | |
236 | COSTS_N_INSNS (10), /* MHI */ | |
237 | COSTS_N_INSNS (10), /* ML */ | |
238 | COSTS_N_INSNS (10), /* MR */ | |
239 | COSTS_N_INSNS (10), /* MS */ | |
240 | COSTS_N_INSNS (10), /* MSG */ | |
241 | COSTS_N_INSNS (10), /* MSGF */ | |
242 | COSTS_N_INSNS (10), /* MSGFR */ | |
243 | COSTS_N_INSNS (10), /* MSGR */ | |
244 | COSTS_N_INSNS (10), /* MSR */ | |
2cdece44 | 245 | COSTS_N_INSNS (1) , /* multiplication in DFmode */ |
9381e3f1 WG |
246 | COSTS_N_INSNS (50), /* MXBR */ |
247 | COSTS_N_INSNS (120), /* SQXBR */ | |
248 | COSTS_N_INSNS (52), /* SQDBR */ | |
93538e8e | 249 | COSTS_N_INSNS (38), /* SQEBR */ |
2cdece44 WG |
250 | COSTS_N_INSNS (1), /* MADBR */ |
251 | COSTS_N_INSNS (1), /* MAEBR */ | |
9381e3f1 WG |
252 | COSTS_N_INSNS (111), /* DXBR */ |
253 | COSTS_N_INSNS (39), /* DDBR */ | |
254 | COSTS_N_INSNS (32), /* DEBR */ | |
255 | COSTS_N_INSNS (160), /* DLGR */ | |
256 | COSTS_N_INSNS (71), /* DLR */ | |
257 | COSTS_N_INSNS (71), /* DR */ | |
258 | COSTS_N_INSNS (71), /* DSGFR */ | |
259 | COSTS_N_INSNS (71), /* DSGR */ | |
93538e8e AK |
260 | }; |
261 | ||
65b1d8ea AK |
262 | static const |
263 | struct processor_costs z196_cost = | |
264 | { | |
265 | COSTS_N_INSNS (7), /* M */ | |
266 | COSTS_N_INSNS (5), /* MGHI */ | |
267 | COSTS_N_INSNS (5), /* MH */ | |
268 | COSTS_N_INSNS (5), /* MHI */ | |
269 | COSTS_N_INSNS (7), /* ML */ | |
270 | COSTS_N_INSNS (7), /* MR */ | |
271 | COSTS_N_INSNS (6), /* MS */ | |
272 | COSTS_N_INSNS (8), /* MSG */ | |
273 | COSTS_N_INSNS (6), /* MSGF */ | |
274 | COSTS_N_INSNS (6), /* MSGFR */ | |
275 | COSTS_N_INSNS (8), /* MSGR */ | |
276 | COSTS_N_INSNS (6), /* MSR */ | |
277 | COSTS_N_INSNS (1) , /* multiplication in DFmode */ | |
278 | COSTS_N_INSNS (40), /* MXBR B+40 */ | |
279 | COSTS_N_INSNS (100), /* SQXBR B+100 */ | |
280 | COSTS_N_INSNS (42), /* SQDBR B+42 */ | |
281 | COSTS_N_INSNS (28), /* SQEBR B+28 */ | |
282 | COSTS_N_INSNS (1), /* MADBR B */ | |
283 | COSTS_N_INSNS (1), /* MAEBR B */ | |
284 | COSTS_N_INSNS (101), /* DXBR B+101 */ | |
285 | COSTS_N_INSNS (29), /* DDBR */ | |
286 | COSTS_N_INSNS (22), /* DEBR */ | |
287 | COSTS_N_INSNS (160), /* DLGR cracked */ | |
288 | COSTS_N_INSNS (160), /* DLR cracked */ | |
289 | COSTS_N_INSNS (160), /* DR expanded */ | |
290 | COSTS_N_INSNS (160), /* DSGFR cracked */ | |
291 | COSTS_N_INSNS (160), /* DSGR cracked */ | |
292 | }; | |
293 | ||
22ac2c2f AK |
294 | static const |
295 | struct processor_costs zEC12_cost = | |
296 | { | |
297 | COSTS_N_INSNS (7), /* M */ | |
298 | COSTS_N_INSNS (5), /* MGHI */ | |
299 | COSTS_N_INSNS (5), /* MH */ | |
300 | COSTS_N_INSNS (5), /* MHI */ | |
301 | COSTS_N_INSNS (7), /* ML */ | |
302 | COSTS_N_INSNS (7), /* MR */ | |
303 | COSTS_N_INSNS (6), /* MS */ | |
304 | COSTS_N_INSNS (8), /* MSG */ | |
305 | COSTS_N_INSNS (6), /* MSGF */ | |
306 | COSTS_N_INSNS (6), /* MSGFR */ | |
307 | COSTS_N_INSNS (8), /* MSGR */ | |
308 | COSTS_N_INSNS (6), /* MSR */ | |
309 | COSTS_N_INSNS (1) , /* multiplication in DFmode */ | |
310 | COSTS_N_INSNS (40), /* MXBR B+40 */ | |
311 | COSTS_N_INSNS (100), /* SQXBR B+100 */ | |
312 | COSTS_N_INSNS (42), /* SQDBR B+42 */ | |
313 | COSTS_N_INSNS (28), /* SQEBR B+28 */ | |
314 | COSTS_N_INSNS (1), /* MADBR B */ | |
315 | COSTS_N_INSNS (1), /* MAEBR B */ | |
316 | COSTS_N_INSNS (131), /* DXBR B+131 */ | |
317 | COSTS_N_INSNS (29), /* DDBR */ | |
318 | COSTS_N_INSNS (22), /* DEBR */ | |
319 | COSTS_N_INSNS (160), /* DLGR cracked */ | |
320 | COSTS_N_INSNS (160), /* DLR cracked */ | |
321 | COSTS_N_INSNS (160), /* DR expanded */ | |
322 | COSTS_N_INSNS (160), /* DSGFR cracked */ | |
323 | COSTS_N_INSNS (160), /* DSGR cracked */ | |
324 | }; | |
325 | ||
ec47b086 DV |
326 | static struct |
327 | { | |
2731a5b3 | 328 | /* The preferred name to be used in user visible output. */ |
ec47b086 | 329 | const char *const name; |
2731a5b3 AK |
330 | /* CPU name as it should be passed to Binutils via .machine */ |
331 | const char *const binutils_name; | |
ec47b086 DV |
332 | const enum processor_type processor; |
333 | const struct processor_costs *cost; | |
334 | } | |
335 | const processor_table[] = | |
336 | { | |
2731a5b3 AK |
337 | { "g5", "g5", PROCESSOR_9672_G5, &z900_cost }, |
338 | { "g6", "g6", PROCESSOR_9672_G6, &z900_cost }, | |
339 | { "z900", "z900", PROCESSOR_2064_Z900, &z900_cost }, | |
340 | { "z990", "z990", PROCESSOR_2084_Z990, &z990_cost }, | |
341 | { "z9-109", "z9-109", PROCESSOR_2094_Z9_109, &z9_109_cost }, | |
342 | { "z9-ec", "z9-ec", PROCESSOR_2094_Z9_EC, &z9_109_cost }, | |
343 | { "z10", "z10", PROCESSOR_2097_Z10, &z10_cost }, | |
344 | { "z196", "z196", PROCESSOR_2817_Z196, &z196_cost }, | |
345 | { "zEC12", "zEC12", PROCESSOR_2827_ZEC12, &zEC12_cost }, | |
346 | { "z13", "z13", PROCESSOR_2964_Z13, &zEC12_cost }, | |
347 | { "z14", "arch12", PROCESSOR_3906_Z14, &zEC12_cost }, | |
348 | { "native", "", PROCESSOR_NATIVE, NULL } | |
ec47b086 DV |
349 | }; |
350 | ||
9db1d521 HP |
351 | extern int reload_completed; |
352 | ||
3a892e44 | 353 | /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */ |
775c43d3 | 354 | static rtx_insn *last_scheduled_insn; |
23902021 AK |
355 | #define MAX_SCHED_UNITS 3 |
356 | static int last_scheduled_unit_distance[MAX_SCHED_UNITS]; | |
357 | ||
358 | /* The maximum score added for an instruction whose unit hasn't been | |
359 | in use for MAX_SCHED_MIX_DISTANCE steps. Increase this value to | |
360 | give instruction mix scheduling more priority over instruction | |
361 | grouping. */ | |
362 | #define MAX_SCHED_MIX_SCORE 8 | |
363 | ||
364 | /* The maximum distance up to which individual scores will be | |
365 | calculated. Everything beyond this gives MAX_SCHED_MIX_SCORE. | |
366 | Increase this with the OOO windows size of the machine. */ | |
367 | #define MAX_SCHED_MIX_DISTANCE 100 | |
3a892e44 | 368 | |
994fe660 UW |
369 | /* Structure used to hold the components of a S/390 memory |
370 | address. A legitimate address on S/390 is of the general | |
371 | form | |
372 | base + index + displacement | |
373 | where any of the components is optional. | |
374 | ||
375 | base and index are registers of the class ADDR_REGS, | |
376 | displacement is an unsigned 12-bit immediate constant. */ | |
9db1d521 HP |
377 | |
378 | struct s390_address | |
379 | { | |
380 | rtx base; | |
381 | rtx indx; | |
382 | rtx disp; | |
3ed99cc9 | 383 | bool pointer; |
f01cf809 | 384 | bool literal_pool; |
9db1d521 HP |
385 | }; |
386 | ||
f4aa3848 | 387 | /* The following structure is embedded in the machine |
adf39f8f AK |
388 | specific part of struct function. */ |
389 | ||
d1b38208 | 390 | struct GTY (()) s390_frame_layout |
adf39f8f AK |
391 | { |
392 | /* Offset within stack frame. */ | |
393 | HOST_WIDE_INT gprs_offset; | |
394 | HOST_WIDE_INT f0_offset; | |
395 | HOST_WIDE_INT f4_offset; | |
396 | HOST_WIDE_INT f8_offset; | |
397 | HOST_WIDE_INT backchain_offset; | |
fb3712f6 AK |
398 | |
399 | /* Number of first and last gpr where slots in the register | |
400 | save area are reserved for. */ | |
401 | int first_save_gpr_slot; | |
402 | int last_save_gpr_slot; | |
403 | ||
6455a49e AK |
404 | /* Location (FP register number) where GPRs (r0-r15) should |
405 | be saved to. | |
406 | 0 - does not need to be saved at all | |
407 | -1 - stack slot */ | |
82379bdf AK |
408 | #define SAVE_SLOT_NONE 0 |
409 | #define SAVE_SLOT_STACK -1 | |
6455a49e AK |
410 | signed char gpr_save_slots[16]; |
411 | ||
29742ba4 | 412 | /* Number of first and last gpr to be saved, restored. */ |
4023fb28 UW |
413 | int first_save_gpr; |
414 | int first_restore_gpr; | |
415 | int last_save_gpr; | |
b767fc11 | 416 | int last_restore_gpr; |
4023fb28 | 417 | |
f4aa3848 AK |
418 | /* Bits standing for floating point registers. Set, if the |
419 | respective register has to be saved. Starting with reg 16 (f0) | |
adf39f8f | 420 | at the rightmost bit. |
2cf4c39e AK |
421 | Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
422 | fpr 15 13 11 9 14 12 10 8 7 5 3 1 6 4 2 0 | |
423 | reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 */ | |
adf39f8f AK |
424 | unsigned int fpr_bitmap; |
425 | ||
426 | /* Number of floating point registers f8-f15 which must be saved. */ | |
427 | int high_fprs; | |
428 | ||
dc4477f5 AK |
429 | /* Set if return address needs to be saved. |
430 | This flag is set by s390_return_addr_rtx if it could not use | |
431 | the initial value of r14 and therefore depends on r14 saved | |
432 | to the stack. */ | |
adf39f8f AK |
433 | bool save_return_addr_p; |
434 | ||
29742ba4 | 435 | /* Size of stack frame. */ |
4023fb28 | 436 | HOST_WIDE_INT frame_size; |
adf39f8f AK |
437 | }; |
438 | ||
439 | /* Define the structure for the machine field in struct function. */ | |
440 | ||
d1b38208 | 441 | struct GTY(()) machine_function |
adf39f8f AK |
442 | { |
443 | struct s390_frame_layout frame_layout; | |
fd3cd001 | 444 | |
585539a1 UW |
445 | /* Literal pool base register. */ |
446 | rtx base_reg; | |
447 | ||
91086990 UW |
448 | /* True if we may need to perform branch splitting. */ |
449 | bool split_branches_pending_p; | |
450 | ||
7bcebb25 | 451 | bool has_landing_pad_p; |
5a3fe9b6 AK |
452 | |
453 | /* True if the current function may contain a tbegin clobbering | |
454 | FPRs. */ | |
455 | bool tbegin_p; | |
4cb4721f MK |
456 | |
457 | /* For -fsplit-stack support: A stack local which holds a pointer to | |
458 | the stack arguments for a function with a variable number of | |
459 | arguments. This is set at the start of the function and is used | |
460 | to initialize the overflow_arg_area field of the va_list | |
461 | structure. */ | |
462 | rtx split_stack_varargs_pointer; | |
4023fb28 UW |
463 | }; |
464 | ||
adf39f8f AK |
465 | /* Few accessor macros for struct cfun->machine->s390_frame_layout. */ |
466 | ||
467 | #define cfun_frame_layout (cfun->machine->frame_layout) | |
468 | #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs) | |
6455a49e AK |
469 | #define cfun_save_arg_fprs_p (!!(TARGET_64BIT \ |
470 | ? cfun_frame_layout.fpr_bitmap & 0x0f \ | |
471 | : cfun_frame_layout.fpr_bitmap & 0x03)) | |
472 | #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \ | |
9602b6a1 | 473 | cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG) |
b89b22fc | 474 | #define cfun_set_fpr_save(REGNO) (cfun->machine->frame_layout.fpr_bitmap |= \ |
2cf4c39e | 475 | (1 << (REGNO - FPR0_REGNUM))) |
b89b22fc | 476 | #define cfun_fpr_save_p(REGNO) (!!(cfun->machine->frame_layout.fpr_bitmap & \ |
2cf4c39e | 477 | (1 << (REGNO - FPR0_REGNUM)))) |
6455a49e AK |
478 | #define cfun_gpr_save_slot(REGNO) \ |
479 | cfun->machine->frame_layout.gpr_save_slots[REGNO] | |
adf39f8f | 480 | |
29a79fcf UW |
481 | /* Number of GPRs and FPRs used for argument passing. */ |
482 | #define GP_ARG_NUM_REG 5 | |
483 | #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2) | |
085261c8 | 484 | #define VEC_ARG_NUM_REG 8 |
29a79fcf | 485 | |
b5c67a49 AK |
486 | /* A couple of shortcuts. */ |
487 | #define CONST_OK_FOR_J(x) \ | |
488 | CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J") | |
489 | #define CONST_OK_FOR_K(x) \ | |
490 | CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K") | |
ec24698e UW |
491 | #define CONST_OK_FOR_Os(x) \ |
492 | CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os") | |
493 | #define CONST_OK_FOR_Op(x) \ | |
494 | CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op") | |
495 | #define CONST_OK_FOR_On(x) \ | |
496 | CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On") | |
b5c67a49 | 497 | |
74aa8b4b | 498 | #define REGNO_PAIR_OK(REGNO, MODE) \ |
c43f4279 | 499 | (s390_hard_regno_nregs ((REGNO), (MODE)) == 1 || !((REGNO) & 1)) |
74aa8b4b | 500 | |
b0f86a7e | 501 | /* That's the read ahead of the dynamic branch prediction unit in |
65b1d8ea AK |
502 | bytes on a z10 (or higher) CPU. */ |
503 | #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048) | |
b0f86a7e | 504 | |
3af82a61 | 505 | |
45901378 AK |
506 | /* Indicate which ABI has been used for passing vector args. |
507 | 0 - no vector type arguments have been passed where the ABI is relevant | |
508 | 1 - the old ABI has been used | |
509 | 2 - a vector type argument has been passed either in a vector register | |
510 | or on the stack by value */ | |
511 | static int s390_vector_abi = 0; | |
512 | ||
513 | /* Set the vector ABI marker if TYPE is subject to the vector ABI | |
514 | switch. The vector ABI affects only vector data types. There are | |
515 | two aspects of the vector ABI relevant here: | |
516 | ||
517 | 1. vectors >= 16 bytes have an alignment of 8 bytes with the new | |
518 | ABI and natural alignment with the old. | |
519 | ||
520 | 2. vector <= 16 bytes are passed in VRs or by value on the stack | |
521 | with the new ABI but by reference on the stack with the old. | |
522 | ||
523 | If ARG_P is true TYPE is used for a function argument or return | |
524 | value. The ABI marker then is set for all vector data types. If | |
525 | ARG_P is false only type 1 vectors are being checked. */ | |
526 | ||
527 | static void | |
528 | s390_check_type_for_vector_abi (const_tree type, bool arg_p, bool in_struct_p) | |
529 | { | |
530 | static hash_set<const_tree> visited_types_hash; | |
531 | ||
532 | if (s390_vector_abi) | |
533 | return; | |
534 | ||
535 | if (type == NULL_TREE || TREE_CODE (type) == ERROR_MARK) | |
536 | return; | |
537 | ||
538 | if (visited_types_hash.contains (type)) | |
539 | return; | |
540 | ||
541 | visited_types_hash.add (type); | |
542 | ||
543 | if (VECTOR_TYPE_P (type)) | |
544 | { | |
545 | int type_size = int_size_in_bytes (type); | |
546 | ||
547 | /* Outside arguments only the alignment is changing and this | |
548 | only happens for vector types >= 16 bytes. */ | |
549 | if (!arg_p && type_size < 16) | |
550 | return; | |
551 | ||
552 | /* In arguments vector types > 16 are passed as before (GCC | |
553 | never enforced the bigger alignment for arguments which was | |
554 | required by the old vector ABI). However, it might still be | |
555 | ABI relevant due to the changed alignment if it is a struct | |
556 | member. */ | |
557 | if (arg_p && type_size > 16 && !in_struct_p) | |
558 | return; | |
559 | ||
560 | s390_vector_abi = TARGET_VX_ABI ? 2 : 1; | |
561 | } | |
562 | else if (POINTER_TYPE_P (type) || TREE_CODE (type) == ARRAY_TYPE) | |
563 | { | |
564 | /* ARRAY_TYPE: Since with neither of the ABIs we have more than | |
565 | natural alignment there will never be ABI dependent padding | |
566 | in an array type. That's why we do not set in_struct_p to | |
567 | true here. */ | |
568 | s390_check_type_for_vector_abi (TREE_TYPE (type), arg_p, in_struct_p); | |
569 | } | |
570 | else if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE) | |
571 | { | |
572 | tree arg_chain; | |
573 | ||
574 | /* Check the return type. */ | |
575 | s390_check_type_for_vector_abi (TREE_TYPE (type), true, false); | |
576 | ||
577 | for (arg_chain = TYPE_ARG_TYPES (type); | |
578 | arg_chain; | |
579 | arg_chain = TREE_CHAIN (arg_chain)) | |
580 | s390_check_type_for_vector_abi (TREE_VALUE (arg_chain), true, false); | |
581 | } | |
582 | else if (RECORD_OR_UNION_TYPE_P (type)) | |
583 | { | |
584 | tree field; | |
585 | ||
586 | for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) | |
587 | { | |
588 | if (TREE_CODE (field) != FIELD_DECL) | |
589 | continue; | |
590 | ||
591 | s390_check_type_for_vector_abi (TREE_TYPE (field), arg_p, true); | |
592 | } | |
593 | } | |
594 | } | |
595 | ||
596 | ||
3af82a61 AK |
597 | /* System z builtins. */ |
598 | ||
599 | #include "s390-builtins.h" | |
600 | ||
f4d28290 | 601 | const unsigned int bflags_builtin[S390_BUILTIN_MAX + 1] = |
3af82a61 AK |
602 | { |
603 | #undef B_DEF | |
604 | #undef OB_DEF | |
605 | #undef OB_DEF_VAR | |
f4d28290 | 606 | #define B_DEF(NAME, PATTERN, ATTRS, BFLAGS, ...) BFLAGS, |
3af82a61 AK |
607 | #define OB_DEF(...) |
608 | #define OB_DEF_VAR(...) | |
609 | #include "s390-builtins.def" | |
610 | 0 | |
611 | }; | |
612 | ||
f4d28290 AK |
613 | const unsigned int opflags_builtin[S390_BUILTIN_MAX + 1] = |
614 | { | |
615 | #undef B_DEF | |
616 | #undef OB_DEF | |
617 | #undef OB_DEF_VAR | |
618 | #define B_DEF(NAME, PATTERN, ATTRS, BFLAGS, OPFLAGS, ...) OPFLAGS, | |
619 | #define OB_DEF(...) | |
620 | #define OB_DEF_VAR(...) | |
621 | #include "s390-builtins.def" | |
622 | 0 | |
623 | }; | |
624 | ||
625 | const unsigned int bflags_overloaded_builtin[S390_OVERLOADED_BUILTIN_MAX + 1] = | |
626 | { | |
627 | #undef B_DEF | |
628 | #undef OB_DEF | |
629 | #undef OB_DEF_VAR | |
630 | #define B_DEF(...) | |
631 | #define OB_DEF(NAME, FIRST_VAR_NAME, LAST_VAR_NAME, BFLAGS, ...) BFLAGS, | |
632 | #define OB_DEF_VAR(...) | |
633 | #include "s390-builtins.def" | |
634 | 0 | |
635 | }; | |
636 | ||
76794c52 AK |
637 | const unsigned int |
638 | bflags_overloaded_builtin_var[S390_OVERLOADED_BUILTIN_VAR_MAX + 1] = | |
639 | { | |
640 | #undef B_DEF | |
641 | #undef OB_DEF | |
642 | #undef OB_DEF_VAR | |
643 | #define B_DEF(...) | |
644 | #define OB_DEF(...) | |
645 | #define OB_DEF_VAR(NAME, PATTERN, FLAGS, OPFLAGS, FNTYPE) FLAGS, | |
646 | #include "s390-builtins.def" | |
647 | 0 | |
648 | }; | |
649 | ||
f4d28290 AK |
650 | const unsigned int |
651 | opflags_overloaded_builtin_var[S390_OVERLOADED_BUILTIN_VAR_MAX + 1] = | |
3af82a61 AK |
652 | { |
653 | #undef B_DEF | |
654 | #undef OB_DEF | |
655 | #undef OB_DEF_VAR | |
656 | #define B_DEF(...) | |
657 | #define OB_DEF(...) | |
76794c52 | 658 | #define OB_DEF_VAR(NAME, PATTERN, FLAGS, OPFLAGS, FNTYPE) OPFLAGS, |
3af82a61 AK |
659 | #include "s390-builtins.def" |
660 | 0 | |
661 | }; | |
662 | ||
663 | tree s390_builtin_types[BT_MAX]; | |
664 | tree s390_builtin_fn_types[BT_FN_MAX]; | |
665 | tree s390_builtin_decls[S390_BUILTIN_MAX + | |
666 | S390_OVERLOADED_BUILTIN_MAX + | |
667 | S390_OVERLOADED_BUILTIN_VAR_MAX]; | |
668 | ||
669 | static enum insn_code const code_for_builtin[S390_BUILTIN_MAX + 1] = { | |
670 | #undef B_DEF | |
671 | #undef OB_DEF | |
672 | #undef OB_DEF_VAR | |
673 | #define B_DEF(NAME, PATTERN, ...) CODE_FOR_##PATTERN, | |
674 | #define OB_DEF(...) | |
675 | #define OB_DEF_VAR(...) | |
676 | ||
677 | #include "s390-builtins.def" | |
678 | CODE_FOR_nothing | |
679 | }; | |
680 | ||
681 | static void | |
682 | s390_init_builtins (void) | |
683 | { | |
684 | /* These definitions are being used in s390-builtins.def. */ | |
685 | tree returns_twice_attr = tree_cons (get_identifier ("returns_twice"), | |
686 | NULL, NULL); | |
687 | tree noreturn_attr = tree_cons (get_identifier ("noreturn"), NULL, NULL); | |
688 | tree c_uint64_type_node; | |
689 | ||
690 | /* The uint64_type_node from tree.c is not compatible to the C99 | |
691 | uint64_t data type. What we want is c_uint64_type_node from | |
692 | c-common.c. But since backend code is not supposed to interface | |
693 | with the frontend we recreate it here. */ | |
694 | if (TARGET_64BIT) | |
695 | c_uint64_type_node = long_unsigned_type_node; | |
696 | else | |
697 | c_uint64_type_node = long_long_unsigned_type_node; | |
698 | ||
699 | #undef DEF_TYPE | |
c145a510 | 700 | #define DEF_TYPE(INDEX, NODE, CONST_P) \ |
ec47b086 | 701 | if (s390_builtin_types[INDEX] == NULL) \ |
f4d28290 AK |
702 | s390_builtin_types[INDEX] = (!CONST_P) ? \ |
703 | (NODE) : build_type_variant ((NODE), 1, 0); | |
3af82a61 AK |
704 | |
705 | #undef DEF_POINTER_TYPE | |
c145a510 | 706 | #define DEF_POINTER_TYPE(INDEX, INDEX_BASE) \ |
ec47b086 | 707 | if (s390_builtin_types[INDEX] == NULL) \ |
f4d28290 AK |
708 | s390_builtin_types[INDEX] = \ |
709 | build_pointer_type (s390_builtin_types[INDEX_BASE]); | |
3af82a61 AK |
710 | |
711 | #undef DEF_DISTINCT_TYPE | |
c145a510 | 712 | #define DEF_DISTINCT_TYPE(INDEX, INDEX_BASE) \ |
ec47b086 | 713 | if (s390_builtin_types[INDEX] == NULL) \ |
f4d28290 AK |
714 | s390_builtin_types[INDEX] = \ |
715 | build_distinct_type_copy (s390_builtin_types[INDEX_BASE]); | |
3af82a61 AK |
716 | |
717 | #undef DEF_VECTOR_TYPE | |
c145a510 | 718 | #define DEF_VECTOR_TYPE(INDEX, INDEX_BASE, ELEMENTS) \ |
ec47b086 | 719 | if (s390_builtin_types[INDEX] == NULL) \ |
f4d28290 AK |
720 | s390_builtin_types[INDEX] = \ |
721 | build_vector_type (s390_builtin_types[INDEX_BASE], ELEMENTS); | |
3af82a61 AK |
722 | |
723 | #undef DEF_OPAQUE_VECTOR_TYPE | |
c145a510 | 724 | #define DEF_OPAQUE_VECTOR_TYPE(INDEX, INDEX_BASE, ELEMENTS) \ |
ec47b086 | 725 | if (s390_builtin_types[INDEX] == NULL) \ |
f4d28290 AK |
726 | s390_builtin_types[INDEX] = \ |
727 | build_opaque_vector_type (s390_builtin_types[INDEX_BASE], ELEMENTS); | |
3af82a61 AK |
728 | |
729 | #undef DEF_FN_TYPE | |
c145a510 | 730 | #define DEF_FN_TYPE(INDEX, args...) \ |
ec47b086 | 731 | if (s390_builtin_fn_types[INDEX] == NULL) \ |
f4d28290 | 732 | s390_builtin_fn_types[INDEX] = \ |
ec47b086 | 733 | build_function_type_list (args, NULL_TREE); |
3af82a61 AK |
734 | #undef DEF_OV_TYPE |
735 | #define DEF_OV_TYPE(...) | |
736 | #include "s390-builtin-types.def" | |
737 | ||
738 | #undef B_DEF | |
f4d28290 | 739 | #define B_DEF(NAME, PATTERN, ATTRS, BFLAGS, OPFLAGS, FNTYPE) \ |
ec47b086 | 740 | if (s390_builtin_decls[S390_BUILTIN_##NAME] == NULL) \ |
f4d28290 AK |
741 | s390_builtin_decls[S390_BUILTIN_##NAME] = \ |
742 | add_builtin_function ("__builtin_" #NAME, \ | |
743 | s390_builtin_fn_types[FNTYPE], \ | |
744 | S390_BUILTIN_##NAME, \ | |
745 | BUILT_IN_MD, \ | |
746 | NULL, \ | |
747 | ATTRS); | |
3af82a61 | 748 | #undef OB_DEF |
f4d28290 | 749 | #define OB_DEF(NAME, FIRST_VAR_NAME, LAST_VAR_NAME, BFLAGS, FNTYPE) \ |
ec47b086 DV |
750 | if (s390_builtin_decls[S390_OVERLOADED_BUILTIN_##NAME + S390_BUILTIN_MAX] \ |
751 | == NULL) \ | |
f4d28290 AK |
752 | s390_builtin_decls[S390_OVERLOADED_BUILTIN_##NAME + S390_BUILTIN_MAX] = \ |
753 | add_builtin_function ("__builtin_" #NAME, \ | |
754 | s390_builtin_fn_types[FNTYPE], \ | |
755 | S390_OVERLOADED_BUILTIN_##NAME + S390_BUILTIN_MAX, \ | |
756 | BUILT_IN_MD, \ | |
757 | NULL, \ | |
758 | 0); | |
3af82a61 AK |
759 | #undef OB_DEF_VAR |
760 | #define OB_DEF_VAR(...) | |
761 | #include "s390-builtins.def" | |
762 | ||
763 | } | |
764 | ||
765 | /* Return true if ARG is appropriate as argument number ARGNUM of | |
766 | builtin DECL. The operand flags from s390-builtins.def have to | |
767 | passed as OP_FLAGS. */ | |
768 | bool | |
769 | s390_const_operand_ok (tree arg, int argnum, int op_flags, tree decl) | |
770 | { | |
771 | if (O_UIMM_P (op_flags)) | |
772 | { | |
773 | int bitwidths[] = { 1, 2, 3, 4, 5, 8, 12, 16, 32 }; | |
774 | int bitwidth = bitwidths[op_flags - O_U1]; | |
775 | ||
776 | if (!tree_fits_uhwi_p (arg) | |
406fde6e | 777 | || tree_to_uhwi (arg) > (HOST_WIDE_INT_1U << bitwidth) - 1) |
3af82a61 AK |
778 | { |
779 | error("constant argument %d for builtin %qF is out of range (0.." | |
780 | HOST_WIDE_INT_PRINT_UNSIGNED ")", | |
781 | argnum, decl, | |
406fde6e | 782 | (HOST_WIDE_INT_1U << bitwidth) - 1); |
3af82a61 AK |
783 | return false; |
784 | } | |
785 | } | |
786 | ||
787 | if (O_SIMM_P (op_flags)) | |
788 | { | |
789 | int bitwidths[] = { 2, 3, 4, 5, 8, 12, 16, 32 }; | |
790 | int bitwidth = bitwidths[op_flags - O_S2]; | |
791 | ||
792 | if (!tree_fits_shwi_p (arg) | |
406fde6e DV |
793 | || tree_to_shwi (arg) < -(HOST_WIDE_INT_1 << (bitwidth - 1)) |
794 | || tree_to_shwi (arg) > ((HOST_WIDE_INT_1 << (bitwidth - 1)) - 1)) | |
3af82a61 AK |
795 | { |
796 | error("constant argument %d for builtin %qF is out of range (" | |
797 | HOST_WIDE_INT_PRINT_DEC ".." | |
798 | HOST_WIDE_INT_PRINT_DEC ")", | |
799 | argnum, decl, | |
406fde6e DV |
800 | -(HOST_WIDE_INT_1 << (bitwidth - 1)), |
801 | (HOST_WIDE_INT_1 << (bitwidth - 1)) - 1); | |
3af82a61 AK |
802 | return false; |
803 | } | |
804 | } | |
805 | return true; | |
806 | } | |
807 | ||
808 | /* Expand an expression EXP that calls a built-in function, | |
809 | with result going to TARGET if that's convenient | |
810 | (and in mode MODE if that's convenient). | |
811 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
812 | IGNORE is nonzero if the value is to be ignored. */ | |
813 | ||
814 | static rtx | |
815 | s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, | |
816 | machine_mode mode ATTRIBUTE_UNUSED, | |
817 | int ignore ATTRIBUTE_UNUSED) | |
818 | { | |
f90eba2a | 819 | #define MAX_ARGS 6 |
3af82a61 AK |
820 | |
821 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); | |
822 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); | |
823 | enum insn_code icode; | |
824 | rtx op[MAX_ARGS], pat; | |
825 | int arity; | |
826 | bool nonvoid; | |
827 | tree arg; | |
828 | call_expr_arg_iterator iter; | |
f4d28290 | 829 | unsigned int all_op_flags = opflags_for_builtin (fcode); |
3af82a61 AK |
830 | machine_mode last_vec_mode = VOIDmode; |
831 | ||
832 | if (TARGET_DEBUG_ARG) | |
833 | { | |
834 | fprintf (stderr, | |
ec47b086 DV |
835 | "s390_expand_builtin, code = %4d, %s, bflags = 0x%x\n", |
836 | (int)fcode, IDENTIFIER_POINTER (DECL_NAME (fndecl)), | |
837 | bflags_for_builtin (fcode)); | |
3af82a61 AK |
838 | } |
839 | ||
ec47b086 DV |
840 | if (S390_USE_TARGET_ATTRIBUTE) |
841 | { | |
842 | unsigned int bflags; | |
843 | ||
844 | bflags = bflags_for_builtin (fcode); | |
845 | if ((bflags & B_HTM) && !TARGET_HTM) | |
846 | { | |
f3981e7e | 847 | error ("builtin %qF is not supported without -mhtm " |
ec47b086 DV |
848 | "(default with -march=zEC12 and higher).", fndecl); |
849 | return const0_rtx; | |
850 | } | |
6654e96f | 851 | if (((bflags & B_VX) || (bflags & B_VXE)) && !TARGET_VX) |
ec47b086 | 852 | { |
76794c52 | 853 | error ("builtin %qF requires -mvx " |
ec47b086 DV |
854 | "(default with -march=z13 and higher).", fndecl); |
855 | return const0_rtx; | |
856 | } | |
6654e96f AK |
857 | |
858 | if ((bflags & B_VXE) && !TARGET_VXE) | |
859 | { | |
2731a5b3 | 860 | error ("Builtin %qF requires z14 or higher.", fndecl); |
6654e96f AK |
861 | return const0_rtx; |
862 | } | |
ec47b086 | 863 | } |
3af82a61 AK |
864 | if (fcode >= S390_OVERLOADED_BUILTIN_VAR_OFFSET |
865 | && fcode < S390_ALL_BUILTIN_MAX) | |
866 | { | |
867 | gcc_unreachable (); | |
868 | } | |
869 | else if (fcode < S390_OVERLOADED_BUILTIN_OFFSET) | |
870 | { | |
871 | icode = code_for_builtin[fcode]; | |
872 | /* Set a flag in the machine specific cfun part in order to support | |
873 | saving/restoring of FPRs. */ | |
874 | if (fcode == S390_BUILTIN_tbegin || fcode == S390_BUILTIN_tbegin_retry) | |
875 | cfun->machine->tbegin_p = true; | |
876 | } | |
877 | else if (fcode < S390_OVERLOADED_BUILTIN_VAR_OFFSET) | |
878 | { | |
f3981e7e | 879 | error ("unresolved overloaded builtin"); |
3af82a61 AK |
880 | return const0_rtx; |
881 | } | |
882 | else | |
883 | internal_error ("bad builtin fcode"); | |
884 | ||
885 | if (icode == 0) | |
886 | internal_error ("bad builtin icode"); | |
887 | ||
888 | nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node; | |
889 | ||
890 | if (nonvoid) | |
891 | { | |
892 | machine_mode tmode = insn_data[icode].operand[0].mode; | |
893 | if (!target | |
894 | || GET_MODE (target) != tmode | |
895 | || !(*insn_data[icode].operand[0].predicate) (target, tmode)) | |
896 | target = gen_reg_rtx (tmode); | |
897 | ||
898 | /* There are builtins (e.g. vec_promote) with no vector | |
899 | arguments but an element selector. So we have to also look | |
900 | at the vector return type when emitting the modulo | |
901 | operation. */ | |
902 | if (VECTOR_MODE_P (insn_data[icode].operand[0].mode)) | |
903 | last_vec_mode = insn_data[icode].operand[0].mode; | |
904 | } | |
905 | ||
906 | arity = 0; | |
907 | FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) | |
908 | { | |
2d71f118 | 909 | rtx tmp_rtx; |
3af82a61 AK |
910 | const struct insn_operand_data *insn_op; |
911 | unsigned int op_flags = all_op_flags & ((1 << O_SHIFT) - 1); | |
912 | ||
913 | all_op_flags = all_op_flags >> O_SHIFT; | |
914 | ||
915 | if (arg == error_mark_node) | |
916 | return NULL_RTX; | |
917 | if (arity >= MAX_ARGS) | |
918 | return NULL_RTX; | |
919 | ||
920 | if (O_IMM_P (op_flags) | |
921 | && TREE_CODE (arg) != INTEGER_CST) | |
922 | { | |
923 | error ("constant value required for builtin %qF argument %d", | |
924 | fndecl, arity + 1); | |
925 | return const0_rtx; | |
926 | } | |
927 | ||
928 | if (!s390_const_operand_ok (arg, arity + 1, op_flags, fndecl)) | |
929 | return const0_rtx; | |
930 | ||
931 | insn_op = &insn_data[icode].operand[arity + nonvoid]; | |
932 | op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL); | |
933 | ||
dfbe4dfd AK |
934 | /* expand_expr truncates constants to the target mode only if it |
935 | is "convenient". However, our checks below rely on this | |
936 | being done. */ | |
937 | if (CONST_INT_P (op[arity]) | |
938 | && SCALAR_INT_MODE_P (insn_op->mode) | |
939 | && GET_MODE (op[arity]) != insn_op->mode) | |
940 | op[arity] = GEN_INT (trunc_int_for_mode (INTVAL (op[arity]), | |
941 | insn_op->mode)); | |
942 | ||
3af82a61 AK |
943 | /* Wrap the expanded RTX for pointer types into a MEM expr with |
944 | the proper mode. This allows us to use e.g. (match_operand | |
945 | "memory_operand"..) in the insn patterns instead of (mem | |
946 | (match_operand "address_operand)). This is helpful for | |
947 | patterns not just accepting MEMs. */ | |
948 | if (POINTER_TYPE_P (TREE_TYPE (arg)) | |
949 | && insn_op->predicate != address_operand) | |
950 | op[arity] = gen_rtx_MEM (insn_op->mode, op[arity]); | |
951 | ||
952 | /* Expand the module operation required on element selectors. */ | |
953 | if (op_flags == O_ELEM) | |
954 | { | |
955 | gcc_assert (last_vec_mode != VOIDmode); | |
956 | op[arity] = simplify_expand_binop (SImode, code_to_optab (AND), | |
957 | op[arity], | |
958 | GEN_INT (GET_MODE_NUNITS (last_vec_mode) - 1), | |
959 | NULL_RTX, 1, OPTAB_DIRECT); | |
960 | } | |
961 | ||
962 | /* Record the vector mode used for an element selector. This assumes: | |
963 | 1. There is no builtin with two different vector modes and an element selector | |
964 | 2. The element selector comes after the vector type it is referring to. | |
965 | This currently the true for all the builtins but FIXME we | |
966 | should better check for that. */ | |
967 | if (VECTOR_MODE_P (insn_op->mode)) | |
968 | last_vec_mode = insn_op->mode; | |
969 | ||
970 | if (insn_op->predicate (op[arity], insn_op->mode)) | |
971 | { | |
972 | arity++; | |
973 | continue; | |
974 | } | |
975 | ||
976 | if (MEM_P (op[arity]) | |
977 | && insn_op->predicate == memory_operand | |
978 | && (GET_MODE (XEXP (op[arity], 0)) == Pmode | |
979 | || GET_MODE (XEXP (op[arity], 0)) == VOIDmode)) | |
980 | { | |
981 | op[arity] = replace_equiv_address (op[arity], | |
982 | copy_to_mode_reg (Pmode, | |
983 | XEXP (op[arity], 0))); | |
984 | } | |
2d71f118 AK |
985 | /* Some of the builtins require different modes/types than the |
986 | pattern in order to implement a specific API. Instead of | |
987 | adding many expanders which do the mode change we do it here. | |
988 | E.g. s390_vec_add_u128 required to have vector unsigned char | |
989 | arguments is mapped to addti3. */ | |
990 | else if (insn_op->mode != VOIDmode | |
991 | && GET_MODE (op[arity]) != VOIDmode | |
992 | && GET_MODE (op[arity]) != insn_op->mode | |
993 | && ((tmp_rtx = simplify_gen_subreg (insn_op->mode, op[arity], | |
994 | GET_MODE (op[arity]), 0)) | |
995 | != NULL_RTX)) | |
996 | { | |
997 | op[arity] = tmp_rtx; | |
998 | } | |
3af82a61 AK |
999 | else if (GET_MODE (op[arity]) == insn_op->mode |
1000 | || GET_MODE (op[arity]) == VOIDmode | |
1001 | || (insn_op->predicate == address_operand | |
1002 | && GET_MODE (op[arity]) == Pmode)) | |
1003 | { | |
1004 | /* An address_operand usually has VOIDmode in the expander | |
1005 | so we cannot use this. */ | |
1006 | machine_mode target_mode = | |
1007 | (insn_op->predicate == address_operand | |
501623d4 | 1008 | ? (machine_mode) Pmode : insn_op->mode); |
3af82a61 AK |
1009 | op[arity] = copy_to_mode_reg (target_mode, op[arity]); |
1010 | } | |
1011 | ||
1012 | if (!insn_op->predicate (op[arity], insn_op->mode)) | |
1013 | { | |
f3981e7e | 1014 | error ("invalid argument %d for builtin %qF", arity + 1, fndecl); |
3af82a61 AK |
1015 | return const0_rtx; |
1016 | } | |
1017 | arity++; | |
1018 | } | |
1019 | ||
3af82a61 AK |
1020 | switch (arity) |
1021 | { | |
1022 | case 0: | |
1023 | pat = GEN_FCN (icode) (target); | |
1024 | break; | |
1025 | case 1: | |
1026 | if (nonvoid) | |
1027 | pat = GEN_FCN (icode) (target, op[0]); | |
1028 | else | |
1029 | pat = GEN_FCN (icode) (op[0]); | |
1030 | break; | |
1031 | case 2: | |
1032 | if (nonvoid) | |
1033 | pat = GEN_FCN (icode) (target, op[0], op[1]); | |
1034 | else | |
1035 | pat = GEN_FCN (icode) (op[0], op[1]); | |
1036 | break; | |
1037 | case 3: | |
1038 | if (nonvoid) | |
1039 | pat = GEN_FCN (icode) (target, op[0], op[1], op[2]); | |
1040 | else | |
1041 | pat = GEN_FCN (icode) (op[0], op[1], op[2]); | |
1042 | break; | |
1043 | case 4: | |
1044 | if (nonvoid) | |
1045 | pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3]); | |
1046 | else | |
1047 | pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); | |
1048 | break; | |
1049 | case 5: | |
1050 | if (nonvoid) | |
1051 | pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4]); | |
1052 | else | |
1053 | pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4]); | |
1054 | break; | |
1055 | case 6: | |
1056 | if (nonvoid) | |
1057 | pat = GEN_FCN (icode) (target, op[0], op[1], op[2], op[3], op[4], op[5]); | |
1058 | else | |
1059 | pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3], op[4], op[5]); | |
1060 | break; | |
1061 | default: | |
1062 | gcc_unreachable (); | |
1063 | } | |
1064 | if (!pat) | |
1065 | return NULL_RTX; | |
1066 | emit_insn (pat); | |
1067 | ||
1068 | if (nonvoid) | |
1069 | return target; | |
1070 | else | |
1071 | return const0_rtx; | |
1072 | } | |
1073 | ||
1074 | ||
94091f43 DV |
1075 | static const int s390_hotpatch_hw_max = 1000000; |
1076 | static int s390_hotpatch_hw_before_label = 0; | |
1077 | static int s390_hotpatch_hw_after_label = 0; | |
d0de9e13 DV |
1078 | |
1079 | /* Check whether the hotpatch attribute is applied to a function and, if it has | |
1080 | an argument, the argument is valid. */ | |
1081 | ||
1082 | static tree | |
1083 | s390_handle_hotpatch_attribute (tree *node, tree name, tree args, | |
1084 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
1085 | { | |
94091f43 DV |
1086 | tree expr; |
1087 | tree expr2; | |
1088 | int err; | |
1089 | ||
d0de9e13 DV |
1090 | if (TREE_CODE (*node) != FUNCTION_DECL) |
1091 | { | |
1092 | warning (OPT_Wattributes, "%qE attribute only applies to functions", | |
1093 | name); | |
1094 | *no_add_attrs = true; | |
1095 | } | |
94091f43 DV |
1096 | if (args != NULL && TREE_CHAIN (args) != NULL) |
1097 | { | |
1098 | expr = TREE_VALUE (args); | |
1099 | expr2 = TREE_VALUE (TREE_CHAIN (args)); | |
1100 | } | |
1101 | if (args == NULL || TREE_CHAIN (args) == NULL) | |
1102 | err = 1; | |
1103 | else if (TREE_CODE (expr) != INTEGER_CST | |
1104 | || !INTEGRAL_TYPE_P (TREE_TYPE (expr)) | |
1105 | || wi::gtu_p (expr, s390_hotpatch_hw_max)) | |
1106 | err = 1; | |
1107 | else if (TREE_CODE (expr2) != INTEGER_CST | |
1108 | || !INTEGRAL_TYPE_P (TREE_TYPE (expr2)) | |
1109 | || wi::gtu_p (expr2, s390_hotpatch_hw_max)) | |
1110 | err = 1; | |
1111 | else | |
1112 | err = 0; | |
1113 | if (err) | |
d0de9e13 | 1114 | { |
94091f43 DV |
1115 | error ("requested %qE attribute is not a comma separated pair of" |
1116 | " non-negative integer constants or too large (max. %d)", name, | |
1117 | s390_hotpatch_hw_max); | |
1118 | *no_add_attrs = true; | |
d0de9e13 DV |
1119 | } |
1120 | ||
1121 | return NULL_TREE; | |
1122 | } | |
1123 | ||
3af82a61 AK |
1124 | /* Expand the s390_vector_bool type attribute. */ |
1125 | ||
1126 | static tree | |
1127 | s390_handle_vectorbool_attribute (tree *node, tree name ATTRIBUTE_UNUSED, | |
1128 | tree args ATTRIBUTE_UNUSED, | |
1129 | int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) | |
1130 | { | |
1131 | tree type = *node, result = NULL_TREE; | |
1132 | machine_mode mode; | |
1133 | ||
1134 | while (POINTER_TYPE_P (type) | |
1135 | || TREE_CODE (type) == FUNCTION_TYPE | |
1136 | || TREE_CODE (type) == METHOD_TYPE | |
1137 | || TREE_CODE (type) == ARRAY_TYPE) | |
1138 | type = TREE_TYPE (type); | |
1139 | ||
1140 | mode = TYPE_MODE (type); | |
1141 | switch (mode) | |
1142 | { | |
4e10a5a7 RS |
1143 | case E_DImode: case E_V2DImode: |
1144 | result = s390_builtin_types[BT_BV2DI]; | |
1145 | break; | |
1146 | case E_SImode: case E_V4SImode: | |
1147 | result = s390_builtin_types[BT_BV4SI]; | |
1148 | break; | |
1149 | case E_HImode: case E_V8HImode: | |
1150 | result = s390_builtin_types[BT_BV8HI]; | |
1151 | break; | |
1152 | case E_QImode: case E_V16QImode: | |
1153 | result = s390_builtin_types[BT_BV16QI]; | |
1154 | break; | |
1155 | default: | |
1156 | break; | |
3af82a61 AK |
1157 | } |
1158 | ||
1159 | *no_add_attrs = true; /* No need to hang on to the attribute. */ | |
1160 | ||
1161 | if (result) | |
1162 | *node = lang_hooks.types.reconstruct_complex_type (*node, result); | |
1163 | ||
1164 | return NULL_TREE; | |
1165 | } | |
1166 | ||
d0de9e13 | 1167 | static const struct attribute_spec s390_attribute_table[] = { |
3af82a61 AK |
1168 | { "hotpatch", 2, 2, true, false, false, s390_handle_hotpatch_attribute, false }, |
1169 | { "s390_vector_bool", 0, 0, false, true, false, s390_handle_vectorbool_attribute, true }, | |
d0de9e13 DV |
1170 | /* End element. */ |
1171 | { NULL, 0, 0, false, false, false, NULL, false } | |
1172 | }; | |
1173 | ||
5d304e47 AK |
1174 | /* Return the alignment for LABEL. We default to the -falign-labels |
1175 | value except for the literal pool base label. */ | |
1176 | int | |
82082f65 | 1177 | s390_label_align (rtx_insn *label) |
5d304e47 | 1178 | { |
e8a54173 DM |
1179 | rtx_insn *prev_insn = prev_active_insn (label); |
1180 | rtx set, src; | |
5d304e47 AK |
1181 | |
1182 | if (prev_insn == NULL_RTX) | |
1183 | goto old; | |
1184 | ||
e8a54173 | 1185 | set = single_set (prev_insn); |
5d304e47 | 1186 | |
e8a54173 | 1187 | if (set == NULL_RTX) |
5d304e47 AK |
1188 | goto old; |
1189 | ||
e8a54173 | 1190 | src = SET_SRC (set); |
5d304e47 AK |
1191 | |
1192 | /* Don't align literal pool base labels. */ | |
e8a54173 DM |
1193 | if (GET_CODE (src) == UNSPEC |
1194 | && XINT (src, 1) == UNSPEC_MAIN_BASE) | |
5d304e47 AK |
1195 | return 0; |
1196 | ||
1197 | old: | |
1198 | return align_labels_log; | |
1199 | } | |
1200 | ||
935b5226 AK |
1201 | static GTY(()) rtx got_symbol; |
1202 | ||
1203 | /* Return the GOT table symbol. The symbol will be created when the | |
1204 | function is invoked for the first time. */ | |
1205 | ||
1206 | static rtx | |
1207 | s390_got_symbol (void) | |
1208 | { | |
1209 | if (!got_symbol) | |
1210 | { | |
1211 | got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
1212 | SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL; | |
1213 | } | |
1214 | ||
1215 | return got_symbol; | |
1216 | } | |
1217 | ||
095a2d76 | 1218 | static scalar_int_mode |
c7ff6e7a AK |
1219 | s390_libgcc_cmp_return_mode (void) |
1220 | { | |
1221 | return TARGET_64BIT ? DImode : SImode; | |
1222 | } | |
1223 | ||
095a2d76 | 1224 | static scalar_int_mode |
c7ff6e7a AK |
1225 | s390_libgcc_shift_count_mode (void) |
1226 | { | |
1227 | return TARGET_64BIT ? DImode : SImode; | |
1228 | } | |
1229 | ||
095a2d76 | 1230 | static scalar_int_mode |
9602b6a1 AK |
1231 | s390_unwind_word_mode (void) |
1232 | { | |
1233 | return TARGET_64BIT ? DImode : SImode; | |
1234 | } | |
1235 | ||
4dc19cc0 AK |
1236 | /* Return true if the back end supports mode MODE. */ |
1237 | static bool | |
18e2a8b8 | 1238 | s390_scalar_mode_supported_p (scalar_mode mode) |
4dc19cc0 | 1239 | { |
9602b6a1 AK |
1240 | /* In contrast to the default implementation reject TImode constants on 31bit |
1241 | TARGET_ZARCH for ABI compliance. */ | |
1242 | if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode) | |
1243 | return false; | |
1244 | ||
4dc19cc0 | 1245 | if (DECIMAL_FLOAT_MODE_P (mode)) |
a9ab39d3 | 1246 | return default_decimal_float_supported_p (); |
9602b6a1 AK |
1247 | |
1248 | return default_scalar_mode_supported_p (mode); | |
4dc19cc0 AK |
1249 | } |
1250 | ||
085261c8 AK |
1251 | /* Return true if the back end supports vector mode MODE. */ |
1252 | static bool | |
1253 | s390_vector_mode_supported_p (machine_mode mode) | |
1254 | { | |
1255 | machine_mode inner; | |
1256 | ||
1257 | if (!VECTOR_MODE_P (mode) | |
1258 | || !TARGET_VX | |
1259 | || GET_MODE_SIZE (mode) > 16) | |
1260 | return false; | |
1261 | ||
1262 | inner = GET_MODE_INNER (mode); | |
1263 | ||
1264 | switch (inner) | |
1265 | { | |
4e10a5a7 RS |
1266 | case E_QImode: |
1267 | case E_HImode: | |
1268 | case E_SImode: | |
1269 | case E_DImode: | |
1270 | case E_TImode: | |
1271 | case E_SFmode: | |
1272 | case E_DFmode: | |
1273 | case E_TFmode: | |
085261c8 AK |
1274 | return true; |
1275 | default: | |
1276 | return false; | |
1277 | } | |
1278 | } | |
1279 | ||
7bcebb25 AK |
1280 | /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */ |
1281 | ||
1282 | void | |
1283 | s390_set_has_landing_pad_p (bool value) | |
1284 | { | |
1285 | cfun->machine->has_landing_pad_p = value; | |
1286 | } | |
29a79fcf | 1287 | |
69950452 AS |
1288 | /* If two condition code modes are compatible, return a condition code |
1289 | mode which is compatible with both. Otherwise, return | |
1290 | VOIDmode. */ | |
1291 | ||
ef4bddc2 RS |
1292 | static machine_mode |
1293 | s390_cc_modes_compatible (machine_mode m1, machine_mode m2) | |
69950452 AS |
1294 | { |
1295 | if (m1 == m2) | |
1296 | return m1; | |
1297 | ||
1298 | switch (m1) | |
1299 | { | |
4e10a5a7 | 1300 | case E_CCZmode: |
69950452 AS |
1301 | if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode |
1302 | || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode) | |
1303 | return m2; | |
1304 | return VOIDmode; | |
1305 | ||
4e10a5a7 RS |
1306 | case E_CCSmode: |
1307 | case E_CCUmode: | |
1308 | case E_CCTmode: | |
1309 | case E_CCSRmode: | |
1310 | case E_CCURmode: | |
1311 | case E_CCZ1mode: | |
69950452 AS |
1312 | if (m2 == CCZmode) |
1313 | return m1; | |
f4aa3848 | 1314 | |
69950452 AS |
1315 | return VOIDmode; |
1316 | ||
1317 | default: | |
1318 | return VOIDmode; | |
1319 | } | |
1320 | return VOIDmode; | |
1321 | } | |
1322 | ||
994fe660 | 1323 | /* Return true if SET either doesn't set the CC register, or else |
c7453384 | 1324 | the source and destination have matching CC modes and that |
994fe660 | 1325 | CC mode is at least as constrained as REQ_MODE. */ |
c7453384 | 1326 | |
3ed99cc9 | 1327 | static bool |
ef4bddc2 | 1328 | s390_match_ccmode_set (rtx set, machine_mode req_mode) |
9db1d521 | 1329 | { |
ef4bddc2 | 1330 | machine_mode set_mode; |
9db1d521 | 1331 | |
8d933e31 | 1332 | gcc_assert (GET_CODE (set) == SET); |
9db1d521 | 1333 | |
a6a2b532 AK |
1334 | /* These modes are supposed to be used only in CC consumer |
1335 | patterns. */ | |
1336 | gcc_assert (req_mode != CCVIALLmode && req_mode != CCVIANYmode | |
1337 | && req_mode != CCVFALLmode && req_mode != CCVFANYmode); | |
1338 | ||
9db1d521 HP |
1339 | if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set)))) |
1340 | return 1; | |
1341 | ||
1342 | set_mode = GET_MODE (SET_DEST (set)); | |
1343 | switch (set_mode) | |
1344 | { | |
4e10a5a7 RS |
1345 | case E_CCZ1mode: |
1346 | case E_CCSmode: | |
1347 | case E_CCSRmode: | |
1348 | case E_CCUmode: | |
1349 | case E_CCURmode: | |
1350 | case E_CCLmode: | |
1351 | case E_CCL1mode: | |
1352 | case E_CCL2mode: | |
1353 | case E_CCL3mode: | |
1354 | case E_CCT1mode: | |
1355 | case E_CCT2mode: | |
1356 | case E_CCT3mode: | |
1357 | case E_CCVEQmode: | |
1358 | case E_CCVIHmode: | |
1359 | case E_CCVIHUmode: | |
1360 | case E_CCVFHmode: | |
1361 | case E_CCVFHEmode: | |
07893d4f | 1362 | if (req_mode != set_mode) |
ba956982 UW |
1363 | return 0; |
1364 | break; | |
07893d4f | 1365 | |
4e10a5a7 | 1366 | case E_CCZmode: |
07893d4f | 1367 | if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode |
03db9ab5 DV |
1368 | && req_mode != CCSRmode && req_mode != CCURmode |
1369 | && req_mode != CCZ1mode) | |
9db1d521 HP |
1370 | return 0; |
1371 | break; | |
0a3bdf9d | 1372 | |
4e10a5a7 RS |
1373 | case E_CCAPmode: |
1374 | case E_CCANmode: | |
0a3bdf9d UW |
1375 | if (req_mode != CCAmode) |
1376 | return 0; | |
1377 | break; | |
c7453384 | 1378 | |
9db1d521 | 1379 | default: |
8d933e31 | 1380 | gcc_unreachable (); |
9db1d521 | 1381 | } |
c7453384 | 1382 | |
9db1d521 HP |
1383 | return (GET_MODE (SET_SRC (set)) == set_mode); |
1384 | } | |
1385 | ||
c7453384 EC |
1386 | /* Return true if every SET in INSN that sets the CC register |
1387 | has source and destination with matching CC modes and that | |
1388 | CC mode is at least as constrained as REQ_MODE. | |
07893d4f | 1389 | If REQ_MODE is VOIDmode, always return false. */ |
c7453384 | 1390 | |
3ed99cc9 | 1391 | bool |
ef4bddc2 | 1392 | s390_match_ccmode (rtx_insn *insn, machine_mode req_mode) |
9db1d521 HP |
1393 | { |
1394 | int i; | |
1395 | ||
07893d4f UW |
1396 | /* s390_tm_ccmode returns VOIDmode to indicate failure. */ |
1397 | if (req_mode == VOIDmode) | |
3ed99cc9 | 1398 | return false; |
07893d4f | 1399 | |
9db1d521 HP |
1400 | if (GET_CODE (PATTERN (insn)) == SET) |
1401 | return s390_match_ccmode_set (PATTERN (insn), req_mode); | |
1402 | ||
1403 | if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
1404 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) | |
1405 | { | |
1406 | rtx set = XVECEXP (PATTERN (insn), 0, i); | |
1407 | if (GET_CODE (set) == SET) | |
1408 | if (!s390_match_ccmode_set (set, req_mode)) | |
3ed99cc9 | 1409 | return false; |
9db1d521 HP |
1410 | } |
1411 | ||
3ed99cc9 | 1412 | return true; |
9db1d521 HP |
1413 | } |
1414 | ||
c7453384 | 1415 | /* If a test-under-mask instruction can be used to implement |
07893d4f | 1416 | (compare (and ... OP1) OP2), return the CC mode required |
c7453384 | 1417 | to do that. Otherwise, return VOIDmode. |
07893d4f UW |
1418 | MIXED is true if the instruction can distinguish between |
1419 | CC1 and CC2 for mixed selected bits (TMxx), it is false | |
1420 | if the instruction cannot (TM). */ | |
1421 | ||
ef4bddc2 | 1422 | machine_mode |
3ed99cc9 | 1423 | s390_tm_ccmode (rtx op1, rtx op2, bool mixed) |
07893d4f UW |
1424 | { |
1425 | int bit0, bit1; | |
1426 | ||
089b05b1 | 1427 | /* ??? Fixme: should work on CONST_WIDE_INT as well. */ |
07893d4f UW |
1428 | if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT) |
1429 | return VOIDmode; | |
1430 | ||
00bda920 AK |
1431 | /* Selected bits all zero: CC0. |
1432 | e.g.: int a; if ((a & (16 + 128)) == 0) */ | |
07893d4f UW |
1433 | if (INTVAL (op2) == 0) |
1434 | return CCTmode; | |
1435 | ||
f4aa3848 | 1436 | /* Selected bits all one: CC3. |
00bda920 | 1437 | e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */ |
07893d4f UW |
1438 | if (INTVAL (op2) == INTVAL (op1)) |
1439 | return CCT3mode; | |
1440 | ||
00bda920 AK |
1441 | /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.: |
1442 | int a; | |
1443 | if ((a & (16 + 128)) == 16) -> CCT1 | |
1444 | if ((a & (16 + 128)) == 128) -> CCT2 */ | |
07893d4f UW |
1445 | if (mixed) |
1446 | { | |
1447 | bit1 = exact_log2 (INTVAL (op2)); | |
1448 | bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2)); | |
1449 | if (bit0 != -1 && bit1 != -1) | |
1450 | return bit0 > bit1 ? CCT1mode : CCT2mode; | |
1451 | } | |
1452 | ||
1453 | return VOIDmode; | |
1454 | } | |
1455 | ||
c7453384 EC |
1456 | /* Given a comparison code OP (EQ, NE, etc.) and the operands |
1457 | OP0 and OP1 of a COMPARE, return the mode to be used for the | |
ba956982 UW |
1458 | comparison. */ |
1459 | ||
ef4bddc2 | 1460 | machine_mode |
9c808aad | 1461 | s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1) |
ba956982 UW |
1462 | { |
1463 | switch (code) | |
1464 | { | |
1465 | case EQ: | |
1466 | case NE: | |
26a89301 UW |
1467 | if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS) |
1468 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) | |
1469 | return CCAPmode; | |
0a3bdf9d | 1470 | if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT |
b5c67a49 | 1471 | && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1)))) |
0a3bdf9d | 1472 | return CCAPmode; |
3ef093a8 AK |
1473 | if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS |
1474 | || GET_CODE (op1) == NEG) | |
1475 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) | |
ba956982 UW |
1476 | return CCLmode; |
1477 | ||
07893d4f UW |
1478 | if (GET_CODE (op0) == AND) |
1479 | { | |
1480 | /* Check whether we can potentially do it via TM. */ | |
ef4bddc2 | 1481 | machine_mode ccmode; |
07893d4f UW |
1482 | ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1); |
1483 | if (ccmode != VOIDmode) | |
1484 | { | |
1485 | /* Relax CCTmode to CCZmode to allow fall-back to AND | |
1486 | if that turns out to be beneficial. */ | |
1487 | return ccmode == CCTmode ? CCZmode : ccmode; | |
1488 | } | |
1489 | } | |
1490 | ||
c7453384 | 1491 | if (register_operand (op0, HImode) |
07893d4f UW |
1492 | && GET_CODE (op1) == CONST_INT |
1493 | && (INTVAL (op1) == -1 || INTVAL (op1) == 65535)) | |
1494 | return CCT3mode; | |
c7453384 | 1495 | if (register_operand (op0, QImode) |
07893d4f UW |
1496 | && GET_CODE (op1) == CONST_INT |
1497 | && (INTVAL (op1) == -1 || INTVAL (op1) == 255)) | |
1498 | return CCT3mode; | |
1499 | ||
ba956982 UW |
1500 | return CCZmode; |
1501 | ||
1502 | case LE: | |
1503 | case LT: | |
1504 | case GE: | |
1505 | case GT: | |
00bda920 AK |
1506 | /* The only overflow condition of NEG and ABS happens when |
1507 | -INT_MAX is used as parameter, which stays negative. So | |
f4aa3848 | 1508 | we have an overflow from a positive value to a negative. |
00bda920 | 1509 | Using CCAP mode the resulting cc can be used for comparisons. */ |
26a89301 UW |
1510 | if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS) |
1511 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) | |
1512 | return CCAPmode; | |
00bda920 AK |
1513 | |
1514 | /* If constants are involved in an add instruction it is possible to use | |
1515 | the resulting cc for comparisons with zero. Knowing the sign of the | |
35fd3193 | 1516 | constant the overflow behavior gets predictable. e.g.: |
f4aa3848 | 1517 | int a, b; if ((b = a + c) > 0) |
00bda920 | 1518 | with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */ |
26a89301 | 1519 | if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT |
71ce1a34 AK |
1520 | && (CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))) |
1521 | || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0, 1)), 'O', "Os") | |
1522 | /* Avoid INT32_MIN on 32 bit. */ | |
1523 | && (!TARGET_ZARCH || INTVAL (XEXP (op0, 1)) != -0x7fffffff - 1)))) | |
26a89301 UW |
1524 | { |
1525 | if (INTVAL (XEXP((op0), 1)) < 0) | |
1526 | return CCANmode; | |
1527 | else | |
1528 | return CCAPmode; | |
1529 | } | |
1530 | /* Fall through. */ | |
ba956982 UW |
1531 | case UNORDERED: |
1532 | case ORDERED: | |
1533 | case UNEQ: | |
1534 | case UNLE: | |
1535 | case UNLT: | |
1536 | case UNGE: | |
1537 | case UNGT: | |
1538 | case LTGT: | |
07893d4f UW |
1539 | if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND) |
1540 | && GET_CODE (op1) != CONST_INT) | |
1541 | return CCSRmode; | |
ba956982 UW |
1542 | return CCSmode; |
1543 | ||
ba956982 UW |
1544 | case LTU: |
1545 | case GEU: | |
3ef093a8 AK |
1546 | if (GET_CODE (op0) == PLUS |
1547 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) | |
07893d4f UW |
1548 | return CCL1mode; |
1549 | ||
1550 | if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND) | |
1551 | && GET_CODE (op1) != CONST_INT) | |
1552 | return CCURmode; | |
1553 | return CCUmode; | |
1554 | ||
1555 | case LEU: | |
ba956982 | 1556 | case GTU: |
3ef093a8 AK |
1557 | if (GET_CODE (op0) == MINUS |
1558 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) | |
07893d4f UW |
1559 | return CCL2mode; |
1560 | ||
1561 | if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND) | |
1562 | && GET_CODE (op1) != CONST_INT) | |
1563 | return CCURmode; | |
ba956982 UW |
1564 | return CCUmode; |
1565 | ||
1566 | default: | |
8d933e31 | 1567 | gcc_unreachable (); |
ba956982 UW |
1568 | } |
1569 | } | |
1570 | ||
68f9c5e2 UW |
1571 | /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one |
1572 | that we can implement more efficiently. */ | |
1573 | ||
c354951b AK |
1574 | static void |
1575 | s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1, | |
1576 | bool op0_preserve_value) | |
68f9c5e2 | 1577 | { |
c354951b AK |
1578 | if (op0_preserve_value) |
1579 | return; | |
1580 | ||
68f9c5e2 UW |
1581 | /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */ |
1582 | if ((*code == EQ || *code == NE) | |
1583 | && *op1 == const0_rtx | |
1584 | && GET_CODE (*op0) == ZERO_EXTRACT | |
1585 | && GET_CODE (XEXP (*op0, 1)) == CONST_INT | |
1586 | && GET_CODE (XEXP (*op0, 2)) == CONST_INT | |
1587 | && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0)))) | |
1588 | { | |
1589 | rtx inner = XEXP (*op0, 0); | |
1590 | HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner)); | |
1591 | HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1)); | |
1592 | HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2)); | |
1593 | ||
1594 | if (len > 0 && len < modesize | |
1595 | && pos >= 0 && pos + len <= modesize | |
1596 | && modesize <= HOST_BITS_PER_WIDE_INT) | |
1597 | { | |
1598 | unsigned HOST_WIDE_INT block; | |
406fde6e | 1599 | block = (HOST_WIDE_INT_1U << len) - 1; |
68f9c5e2 UW |
1600 | block <<= modesize - pos - len; |
1601 | ||
1602 | *op0 = gen_rtx_AND (GET_MODE (inner), inner, | |
1603 | gen_int_mode (block, GET_MODE (inner))); | |
1604 | } | |
1605 | } | |
1606 | ||
1607 | /* Narrow AND of memory against immediate to enable TM. */ | |
1608 | if ((*code == EQ || *code == NE) | |
1609 | && *op1 == const0_rtx | |
1610 | && GET_CODE (*op0) == AND | |
1611 | && GET_CODE (XEXP (*op0, 1)) == CONST_INT | |
1612 | && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0)))) | |
1613 | { | |
1614 | rtx inner = XEXP (*op0, 0); | |
1615 | rtx mask = XEXP (*op0, 1); | |
1616 | ||
1617 | /* Ignore paradoxical SUBREGs if all extra bits are masked out. */ | |
1618 | if (GET_CODE (inner) == SUBREG | |
1619 | && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner))) | |
1620 | && (GET_MODE_SIZE (GET_MODE (inner)) | |
1621 | >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner)))) | |
1622 | && ((INTVAL (mask) | |
1623 | & GET_MODE_MASK (GET_MODE (inner)) | |
1624 | & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner)))) | |
1625 | == 0)) | |
1626 | inner = SUBREG_REG (inner); | |
1627 | ||
1628 | /* Do not change volatile MEMs. */ | |
1629 | if (MEM_P (inner) && !MEM_VOLATILE_P (inner)) | |
1630 | { | |
1631 | int part = s390_single_part (XEXP (*op0, 1), | |
1632 | GET_MODE (inner), QImode, 0); | |
1633 | if (part >= 0) | |
1634 | { | |
1635 | mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode); | |
1636 | inner = adjust_address_nv (inner, QImode, part); | |
1637 | *op0 = gen_rtx_AND (QImode, inner, mask); | |
1638 | } | |
1639 | } | |
1640 | } | |
1641 | ||
1642 | /* Narrow comparisons against 0xffff to HImode if possible. */ | |
68f9c5e2 UW |
1643 | if ((*code == EQ || *code == NE) |
1644 | && GET_CODE (*op1) == CONST_INT | |
1645 | && INTVAL (*op1) == 0xffff | |
1646 | && SCALAR_INT_MODE_P (GET_MODE (*op0)) | |
f4aa3848 | 1647 | && (nonzero_bits (*op0, GET_MODE (*op0)) |
406fde6e | 1648 | & ~HOST_WIDE_INT_UC (0xffff)) == 0) |
68f9c5e2 UW |
1649 | { |
1650 | *op0 = gen_lowpart (HImode, *op0); | |
1651 | *op1 = constm1_rtx; | |
1652 | } | |
5b022de5 | 1653 | |
5a3fe9b6 | 1654 | /* Remove redundant UNSPEC_STRCMPCC_TO_INT conversions if possible. */ |
5b022de5 | 1655 | if (GET_CODE (*op0) == UNSPEC |
5a3fe9b6 | 1656 | && XINT (*op0, 1) == UNSPEC_STRCMPCC_TO_INT |
5b022de5 UW |
1657 | && XVECLEN (*op0, 0) == 1 |
1658 | && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode | |
1659 | && GET_CODE (XVECEXP (*op0, 0, 0)) == REG | |
1660 | && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM | |
1661 | && *op1 == const0_rtx) | |
1662 | { | |
1663 | enum rtx_code new_code = UNKNOWN; | |
1664 | switch (*code) | |
1665 | { | |
1666 | case EQ: new_code = EQ; break; | |
1667 | case NE: new_code = NE; break; | |
02887425 UW |
1668 | case LT: new_code = GTU; break; |
1669 | case GT: new_code = LTU; break; | |
1670 | case LE: new_code = GEU; break; | |
1671 | case GE: new_code = LEU; break; | |
5b022de5 UW |
1672 | default: break; |
1673 | } | |
1674 | ||
1675 | if (new_code != UNKNOWN) | |
1676 | { | |
1677 | *op0 = XVECEXP (*op0, 0, 0); | |
1678 | *code = new_code; | |
1679 | } | |
1680 | } | |
69950452 | 1681 | |
5a3fe9b6 | 1682 | /* Remove redundant UNSPEC_CC_TO_INT conversions if possible. */ |
638e37c2 | 1683 | if (GET_CODE (*op0) == UNSPEC |
5a3fe9b6 | 1684 | && XINT (*op0, 1) == UNSPEC_CC_TO_INT |
638e37c2 | 1685 | && XVECLEN (*op0, 0) == 1 |
638e37c2 WG |
1686 | && GET_CODE (XVECEXP (*op0, 0, 0)) == REG |
1687 | && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM | |
5a3fe9b6 | 1688 | && CONST_INT_P (*op1)) |
638e37c2 WG |
1689 | { |
1690 | enum rtx_code new_code = UNKNOWN; | |
5a3fe9b6 | 1691 | switch (GET_MODE (XVECEXP (*op0, 0, 0))) |
638e37c2 | 1692 | { |
4e10a5a7 RS |
1693 | case E_CCZmode: |
1694 | case E_CCRAWmode: | |
5a3fe9b6 AK |
1695 | switch (*code) |
1696 | { | |
1697 | case EQ: new_code = EQ; break; | |
1698 | case NE: new_code = NE; break; | |
1699 | default: break; | |
1700 | } | |
1701 | break; | |
1702 | default: break; | |
638e37c2 WG |
1703 | } |
1704 | ||
1705 | if (new_code != UNKNOWN) | |
1706 | { | |
5a3fe9b6 AK |
1707 | /* For CCRAWmode put the required cc mask into the second |
1708 | operand. */ | |
2561451d AK |
1709 | if (GET_MODE (XVECEXP (*op0, 0, 0)) == CCRAWmode |
1710 | && INTVAL (*op1) >= 0 && INTVAL (*op1) <= 3) | |
5a3fe9b6 | 1711 | *op1 = gen_rtx_CONST_INT (VOIDmode, 1 << (3 - INTVAL (*op1))); |
638e37c2 WG |
1712 | *op0 = XVECEXP (*op0, 0, 0); |
1713 | *code = new_code; | |
1714 | } | |
1715 | } | |
1716 | ||
69950452 AS |
1717 | /* Simplify cascaded EQ, NE with const0_rtx. */ |
1718 | if ((*code == NE || *code == EQ) | |
1719 | && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE) | |
1720 | && GET_MODE (*op0) == SImode | |
1721 | && GET_MODE (XEXP (*op0, 0)) == CCZ1mode | |
1722 | && REG_P (XEXP (*op0, 0)) | |
1723 | && XEXP (*op0, 1) == const0_rtx | |
1724 | && *op1 == const0_rtx) | |
1725 | { | |
1726 | if ((*code == EQ && GET_CODE (*op0) == NE) | |
1727 | || (*code == NE && GET_CODE (*op0) == EQ)) | |
1728 | *code = EQ; | |
1729 | else | |
1730 | *code = NE; | |
1731 | *op0 = XEXP (*op0, 0); | |
1732 | } | |
c5b2a111 UW |
1733 | |
1734 | /* Prefer register over memory as first operand. */ | |
1735 | if (MEM_P (*op0) && REG_P (*op1)) | |
1736 | { | |
1737 | rtx tem = *op0; *op0 = *op1; *op1 = tem; | |
c354951b | 1738 | *code = (int)swap_condition ((enum rtx_code)*code); |
c5b2a111 | 1739 | } |
6e5b5de8 | 1740 | |
eca98038 AK |
1741 | /* A comparison result is compared against zero. Replace it with |
1742 | the (perhaps inverted) original comparison. | |
1743 | This probably should be done by simplify_relational_operation. */ | |
1744 | if ((*code == EQ || *code == NE) | |
1745 | && *op1 == const0_rtx | |
1746 | && COMPARISON_P (*op0) | |
1747 | && CC_REG_P (XEXP (*op0, 0))) | |
1748 | { | |
1749 | enum rtx_code new_code; | |
1750 | ||
1751 | if (*code == EQ) | |
1752 | new_code = reversed_comparison_code_parts (GET_CODE (*op0), | |
1753 | XEXP (*op0, 0), | |
1754 | XEXP (*op1, 0), NULL); | |
1755 | else | |
1756 | new_code = GET_CODE (*op0); | |
1757 | ||
1758 | if (new_code != UNKNOWN) | |
1759 | { | |
1760 | *code = new_code; | |
1761 | *op1 = XEXP (*op0, 1); | |
1762 | *op0 = XEXP (*op0, 0); | |
1763 | } | |
1764 | } | |
68f9c5e2 UW |
1765 | } |
1766 | ||
6e5b5de8 | 1767 | |
6590e19a UW |
1768 | /* Emit a compare instruction suitable to implement the comparison |
1769 | OP0 CODE OP1. Return the correct condition RTL to be placed in | |
1770 | the IF_THEN_ELSE of the conditional branch testing the result. */ | |
1771 | ||
1772 | rtx | |
1773 | s390_emit_compare (enum rtx_code code, rtx op0, rtx op1) | |
1774 | { | |
ef4bddc2 | 1775 | machine_mode mode = s390_select_ccmode (code, op0, op1); |
4a77c72b | 1776 | rtx cc; |
6590e19a | 1777 | |
77c585ca | 1778 | if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC) |
4a77c72b | 1779 | { |
6e5b5de8 AK |
1780 | /* Do not output a redundant compare instruction if a |
1781 | compare_and_swap pattern already computed the result and the | |
1782 | machine modes are compatible. */ | |
4a77c72b PB |
1783 | gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode) |
1784 | == GET_MODE (op0)); | |
1785 | cc = op0; | |
1786 | } | |
e0374221 AS |
1787 | else |
1788 | { | |
4a77c72b | 1789 | cc = gen_rtx_REG (mode, CC_REGNUM); |
f7df4a84 | 1790 | emit_insn (gen_rtx_SET (cc, gen_rtx_COMPARE (mode, op0, op1))); |
e0374221 | 1791 | } |
4a77c72b | 1792 | |
f4aa3848 | 1793 | return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx); |
6590e19a UW |
1794 | } |
1795 | ||
0a2aaacc | 1796 | /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD |
8bb501bb AK |
1797 | matches CMP. |
1798 | Return the correct condition RTL to be placed in the IF_THEN_ELSE of the | |
1799 | conditional branch testing the result. */ | |
1800 | ||
1801 | static rtx | |
78ce265b | 1802 | s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, |
03db9ab5 | 1803 | rtx cmp, rtx new_rtx, machine_mode ccmode) |
8bb501bb | 1804 | { |
03db9ab5 DV |
1805 | rtx cc; |
1806 | ||
1807 | cc = gen_rtx_REG (ccmode, CC_REGNUM); | |
1808 | switch (GET_MODE (mem)) | |
1809 | { | |
4e10a5a7 | 1810 | case E_SImode: |
03db9ab5 DV |
1811 | emit_insn (gen_atomic_compare_and_swapsi_internal (old, mem, cmp, |
1812 | new_rtx, cc)); | |
1813 | break; | |
4e10a5a7 | 1814 | case E_DImode: |
03db9ab5 DV |
1815 | emit_insn (gen_atomic_compare_and_swapdi_internal (old, mem, cmp, |
1816 | new_rtx, cc)); | |
1817 | break; | |
4e10a5a7 | 1818 | case E_TImode: |
03db9ab5 DV |
1819 | emit_insn (gen_atomic_compare_and_swapti_internal (old, mem, cmp, |
1820 | new_rtx, cc)); | |
1821 | break; | |
4e10a5a7 RS |
1822 | case E_QImode: |
1823 | case E_HImode: | |
03db9ab5 DV |
1824 | default: |
1825 | gcc_unreachable (); | |
1826 | } | |
1827 | return s390_emit_compare (code, cc, const0_rtx); | |
8bb501bb AK |
1828 | } |
1829 | ||
5a3fe9b6 AK |
1830 | /* Emit a jump instruction to TARGET and return it. If COND is |
1831 | NULL_RTX, emit an unconditional jump, else a conditional jump under | |
1832 | condition COND. */ | |
6590e19a | 1833 | |
775c43d3 | 1834 | rtx_insn * |
6590e19a UW |
1835 | s390_emit_jump (rtx target, rtx cond) |
1836 | { | |
1837 | rtx insn; | |
1838 | ||
1839 | target = gen_rtx_LABEL_REF (VOIDmode, target); | |
1840 | if (cond) | |
1841 | target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx); | |
1842 | ||
f7df4a84 | 1843 | insn = gen_rtx_SET (pc_rtx, target); |
5a3fe9b6 | 1844 | return emit_jump_insn (insn); |
6590e19a UW |
1845 | } |
1846 | ||
c7453384 | 1847 | /* Return branch condition mask to implement a branch |
5b022de5 | 1848 | specified by CODE. Return -1 for invalid comparisons. */ |
ba956982 | 1849 | |
0bfc3f69 | 1850 | int |
9c808aad | 1851 | s390_branch_condition_mask (rtx code) |
c7453384 | 1852 | { |
ba956982 UW |
1853 | const int CC0 = 1 << 3; |
1854 | const int CC1 = 1 << 2; | |
1855 | const int CC2 = 1 << 1; | |
1856 | const int CC3 = 1 << 0; | |
1857 | ||
8d933e31 AS |
1858 | gcc_assert (GET_CODE (XEXP (code, 0)) == REG); |
1859 | gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM); | |
5a3fe9b6 AK |
1860 | gcc_assert (XEXP (code, 1) == const0_rtx |
1861 | || (GET_MODE (XEXP (code, 0)) == CCRAWmode | |
1862 | && CONST_INT_P (XEXP (code, 1)))); | |
1863 | ||
ba956982 UW |
1864 | |
1865 | switch (GET_MODE (XEXP (code, 0))) | |
1866 | { | |
4e10a5a7 RS |
1867 | case E_CCZmode: |
1868 | case E_CCZ1mode: | |
ba956982 UW |
1869 | switch (GET_CODE (code)) |
1870 | { | |
1871 | case EQ: return CC0; | |
1872 | case NE: return CC1 | CC2 | CC3; | |
5b022de5 | 1873 | default: return -1; |
ba956982 UW |
1874 | } |
1875 | break; | |
1876 | ||
4e10a5a7 | 1877 | case E_CCT1mode: |
07893d4f UW |
1878 | switch (GET_CODE (code)) |
1879 | { | |
1880 | case EQ: return CC1; | |
1881 | case NE: return CC0 | CC2 | CC3; | |
5b022de5 | 1882 | default: return -1; |
07893d4f UW |
1883 | } |
1884 | break; | |
1885 | ||
4e10a5a7 | 1886 | case E_CCT2mode: |
07893d4f UW |
1887 | switch (GET_CODE (code)) |
1888 | { | |
1889 | case EQ: return CC2; | |
1890 | case NE: return CC0 | CC1 | CC3; | |
5b022de5 | 1891 | default: return -1; |
07893d4f UW |
1892 | } |
1893 | break; | |
1894 | ||
4e10a5a7 | 1895 | case E_CCT3mode: |
07893d4f UW |
1896 | switch (GET_CODE (code)) |
1897 | { | |
1898 | case EQ: return CC3; | |
1899 | case NE: return CC0 | CC1 | CC2; | |
5b022de5 | 1900 | default: return -1; |
07893d4f UW |
1901 | } |
1902 | break; | |
1903 | ||
4e10a5a7 | 1904 | case E_CCLmode: |
ba956982 UW |
1905 | switch (GET_CODE (code)) |
1906 | { | |
1907 | case EQ: return CC0 | CC2; | |
1908 | case NE: return CC1 | CC3; | |
5b022de5 | 1909 | default: return -1; |
07893d4f UW |
1910 | } |
1911 | break; | |
1912 | ||
4e10a5a7 | 1913 | case E_CCL1mode: |
07893d4f UW |
1914 | switch (GET_CODE (code)) |
1915 | { | |
1916 | case LTU: return CC2 | CC3; /* carry */ | |
1917 | case GEU: return CC0 | CC1; /* no carry */ | |
5b022de5 | 1918 | default: return -1; |
07893d4f UW |
1919 | } |
1920 | break; | |
1921 | ||
4e10a5a7 | 1922 | case E_CCL2mode: |
07893d4f UW |
1923 | switch (GET_CODE (code)) |
1924 | { | |
1925 | case GTU: return CC0 | CC1; /* borrow */ | |
1926 | case LEU: return CC2 | CC3; /* no borrow */ | |
5b022de5 | 1927 | default: return -1; |
ba956982 UW |
1928 | } |
1929 | break; | |
1930 | ||
4e10a5a7 | 1931 | case E_CCL3mode: |
5d880bd2 UW |
1932 | switch (GET_CODE (code)) |
1933 | { | |
1934 | case EQ: return CC0 | CC2; | |
1935 | case NE: return CC1 | CC3; | |
1936 | case LTU: return CC1; | |
1937 | case GTU: return CC3; | |
1938 | case LEU: return CC1 | CC2; | |
1939 | case GEU: return CC2 | CC3; | |
5b022de5 | 1940 | default: return -1; |
5d880bd2 UW |
1941 | } |
1942 | ||
4e10a5a7 | 1943 | case E_CCUmode: |
ba956982 UW |
1944 | switch (GET_CODE (code)) |
1945 | { | |
1946 | case EQ: return CC0; | |
1947 | case NE: return CC1 | CC2 | CC3; | |
1948 | case LTU: return CC1; | |
1949 | case GTU: return CC2; | |
1950 | case LEU: return CC0 | CC1; | |
1951 | case GEU: return CC0 | CC2; | |
5b022de5 | 1952 | default: return -1; |
ba956982 UW |
1953 | } |
1954 | break; | |
1955 | ||
4e10a5a7 | 1956 | case E_CCURmode: |
07893d4f UW |
1957 | switch (GET_CODE (code)) |
1958 | { | |
1959 | case EQ: return CC0; | |
1960 | case NE: return CC2 | CC1 | CC3; | |
1961 | case LTU: return CC2; | |
1962 | case GTU: return CC1; | |
1963 | case LEU: return CC0 | CC2; | |
1964 | case GEU: return CC0 | CC1; | |
5b022de5 | 1965 | default: return -1; |
07893d4f UW |
1966 | } |
1967 | break; | |
1968 | ||
4e10a5a7 | 1969 | case E_CCAPmode: |
0a3bdf9d UW |
1970 | switch (GET_CODE (code)) |
1971 | { | |
1972 | case EQ: return CC0; | |
1973 | case NE: return CC1 | CC2 | CC3; | |
1974 | case LT: return CC1 | CC3; | |
1975 | case GT: return CC2; | |
1976 | case LE: return CC0 | CC1 | CC3; | |
1977 | case GE: return CC0 | CC2; | |
5b022de5 | 1978 | default: return -1; |
0a3bdf9d UW |
1979 | } |
1980 | break; | |
1981 | ||
4e10a5a7 | 1982 | case E_CCANmode: |
0a3bdf9d UW |
1983 | switch (GET_CODE (code)) |
1984 | { | |
1985 | case EQ: return CC0; | |
1986 | case NE: return CC1 | CC2 | CC3; | |
1987 | case LT: return CC1; | |
1988 | case GT: return CC2 | CC3; | |
1989 | case LE: return CC0 | CC1; | |
1990 | case GE: return CC0 | CC2 | CC3; | |
5b022de5 | 1991 | default: return -1; |
0a3bdf9d UW |
1992 | } |
1993 | break; | |
1994 | ||
4e10a5a7 | 1995 | case E_CCSmode: |
ba956982 UW |
1996 | switch (GET_CODE (code)) |
1997 | { | |
1998 | case EQ: return CC0; | |
1999 | case NE: return CC1 | CC2 | CC3; | |
2000 | case LT: return CC1; | |
2001 | case GT: return CC2; | |
2002 | case LE: return CC0 | CC1; | |
2003 | case GE: return CC0 | CC2; | |
2004 | case UNORDERED: return CC3; | |
2005 | case ORDERED: return CC0 | CC1 | CC2; | |
2006 | case UNEQ: return CC0 | CC3; | |
2007 | case UNLT: return CC1 | CC3; | |
2008 | case UNGT: return CC2 | CC3; | |
2009 | case UNLE: return CC0 | CC1 | CC3; | |
2010 | case UNGE: return CC0 | CC2 | CC3; | |
2011 | case LTGT: return CC1 | CC2; | |
5b022de5 | 2012 | default: return -1; |
ba956982 | 2013 | } |
07893d4f UW |
2014 | break; |
2015 | ||
4e10a5a7 | 2016 | case E_CCSRmode: |
07893d4f UW |
2017 | switch (GET_CODE (code)) |
2018 | { | |
2019 | case EQ: return CC0; | |
2020 | case NE: return CC2 | CC1 | CC3; | |
2021 | case LT: return CC2; | |
2022 | case GT: return CC1; | |
2023 | case LE: return CC0 | CC2; | |
2024 | case GE: return CC0 | CC1; | |
2025 | case UNORDERED: return CC3; | |
2026 | case ORDERED: return CC0 | CC2 | CC1; | |
2027 | case UNEQ: return CC0 | CC3; | |
2028 | case UNLT: return CC2 | CC3; | |
2029 | case UNGT: return CC1 | CC3; | |
2030 | case UNLE: return CC0 | CC2 | CC3; | |
2031 | case UNGE: return CC0 | CC1 | CC3; | |
2032 | case LTGT: return CC2 | CC1; | |
5b022de5 | 2033 | default: return -1; |
07893d4f UW |
2034 | } |
2035 | break; | |
ba956982 | 2036 | |
6e5b5de8 | 2037 | /* Vector comparison modes. */ |
a6a2b532 AK |
2038 | /* CC2 will never be set. It however is part of the negated |
2039 | masks. */ | |
4e10a5a7 | 2040 | case E_CCVIALLmode: |
6e5b5de8 AK |
2041 | switch (GET_CODE (code)) |
2042 | { | |
a6a2b532 AK |
2043 | case EQ: |
2044 | case GTU: | |
2045 | case GT: | |
2046 | case GE: return CC0; | |
2047 | /* The inverted modes are in fact *any* modes. */ | |
2048 | case NE: | |
2049 | case LEU: | |
2050 | case LE: | |
2051 | case LT: return CC3 | CC1 | CC2; | |
6e5b5de8 AK |
2052 | default: return -1; |
2053 | } | |
3af82a61 | 2054 | |
4e10a5a7 | 2055 | case E_CCVIANYmode: |
3af82a61 AK |
2056 | switch (GET_CODE (code)) |
2057 | { | |
a6a2b532 AK |
2058 | case EQ: |
2059 | case GTU: | |
2060 | case GT: | |
2061 | case GE: return CC0 | CC1; | |
2062 | /* The inverted modes are in fact *all* modes. */ | |
2063 | case NE: | |
2064 | case LEU: | |
2065 | case LE: | |
2066 | case LT: return CC3 | CC2; | |
3af82a61 AK |
2067 | default: return -1; |
2068 | } | |
4e10a5a7 | 2069 | case E_CCVFALLmode: |
6e5b5de8 AK |
2070 | switch (GET_CODE (code)) |
2071 | { | |
a6a2b532 AK |
2072 | case EQ: |
2073 | case GT: | |
6e5b5de8 | 2074 | case GE: return CC0; |
a6a2b532 AK |
2075 | /* The inverted modes are in fact *any* modes. */ |
2076 | case NE: | |
2077 | case UNLE: | |
2078 | case UNLT: return CC3 | CC1 | CC2; | |
6e5b5de8 AK |
2079 | default: return -1; |
2080 | } | |
3af82a61 | 2081 | |
4e10a5a7 | 2082 | case E_CCVFANYmode: |
3af82a61 AK |
2083 | switch (GET_CODE (code)) |
2084 | { | |
a6a2b532 AK |
2085 | case EQ: |
2086 | case GT: | |
3af82a61 | 2087 | case GE: return CC0 | CC1; |
a6a2b532 AK |
2088 | /* The inverted modes are in fact *all* modes. */ |
2089 | case NE: | |
2090 | case UNLE: | |
2091 | case UNLT: return CC3 | CC2; | |
3af82a61 AK |
2092 | default: return -1; |
2093 | } | |
2094 | ||
4e10a5a7 | 2095 | case E_CCRAWmode: |
5a3fe9b6 AK |
2096 | switch (GET_CODE (code)) |
2097 | { | |
2098 | case EQ: | |
2099 | return INTVAL (XEXP (code, 1)); | |
2100 | case NE: | |
2101 | return (INTVAL (XEXP (code, 1))) ^ 0xf; | |
2102 | default: | |
2103 | gcc_unreachable (); | |
2104 | } | |
2105 | ||
ba956982 | 2106 | default: |
5b022de5 | 2107 | return -1; |
ba956982 UW |
2108 | } |
2109 | } | |
2110 | ||
963fc8d0 AK |
2111 | |
2112 | /* Return branch condition mask to implement a compare and branch | |
2113 | specified by CODE. Return -1 for invalid comparisons. */ | |
2114 | ||
2115 | int | |
2116 | s390_compare_and_branch_condition_mask (rtx code) | |
2117 | { | |
2118 | const int CC0 = 1 << 3; | |
2119 | const int CC1 = 1 << 2; | |
2120 | const int CC2 = 1 << 1; | |
2121 | ||
2122 | switch (GET_CODE (code)) | |
2123 | { | |
2124 | case EQ: | |
2125 | return CC0; | |
2126 | case NE: | |
2127 | return CC1 | CC2; | |
2128 | case LT: | |
2129 | case LTU: | |
2130 | return CC1; | |
2131 | case GT: | |
2132 | case GTU: | |
2133 | return CC2; | |
2134 | case LE: | |
2135 | case LEU: | |
2136 | return CC0 | CC1; | |
2137 | case GE: | |
2138 | case GEU: | |
2139 | return CC0 | CC2; | |
2140 | default: | |
2141 | gcc_unreachable (); | |
2142 | } | |
2143 | return -1; | |
2144 | } | |
2145 | ||
c7453384 EC |
2146 | /* If INV is false, return assembler mnemonic string to implement |
2147 | a branch specified by CODE. If INV is true, return mnemonic | |
ba956982 UW |
2148 | for the corresponding inverted branch. */ |
2149 | ||
2150 | static const char * | |
9c808aad | 2151 | s390_branch_condition_mnemonic (rtx code, int inv) |
ba956982 | 2152 | { |
963fc8d0 AK |
2153 | int mask; |
2154 | ||
0139adca | 2155 | static const char *const mnemonic[16] = |
ba956982 UW |
2156 | { |
2157 | NULL, "o", "h", "nle", | |
2158 | "l", "nhe", "lh", "ne", | |
2159 | "e", "nlh", "he", "nl", | |
2160 | "le", "nh", "no", NULL | |
2161 | }; | |
2162 | ||
963fc8d0 AK |
2163 | if (GET_CODE (XEXP (code, 0)) == REG |
2164 | && REGNO (XEXP (code, 0)) == CC_REGNUM | |
5a3fe9b6 AK |
2165 | && (XEXP (code, 1) == const0_rtx |
2166 | || (GET_MODE (XEXP (code, 0)) == CCRAWmode | |
2167 | && CONST_INT_P (XEXP (code, 1))))) | |
963fc8d0 AK |
2168 | mask = s390_branch_condition_mask (code); |
2169 | else | |
2170 | mask = s390_compare_and_branch_condition_mask (code); | |
2171 | ||
5b022de5 | 2172 | gcc_assert (mask >= 0); |
ba956982 UW |
2173 | |
2174 | if (inv) | |
2175 | mask ^= 15; | |
2176 | ||
8d933e31 | 2177 | gcc_assert (mask >= 1 && mask <= 14); |
ba956982 UW |
2178 | |
2179 | return mnemonic[mask]; | |
2180 | } | |
2181 | ||
f19a9af7 AK |
2182 | /* Return the part of op which has a value different from def. |
2183 | The size of the part is determined by mode. | |
38899e29 | 2184 | Use this function only if you already know that op really |
f19a9af7 | 2185 | contains such a part. */ |
4023fb28 | 2186 | |
f19a9af7 | 2187 | unsigned HOST_WIDE_INT |
ef4bddc2 | 2188 | s390_extract_part (rtx op, machine_mode mode, int def) |
4023fb28 | 2189 | { |
f19a9af7 AK |
2190 | unsigned HOST_WIDE_INT value = 0; |
2191 | int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode); | |
2192 | int part_bits = GET_MODE_BITSIZE (mode); | |
406fde6e | 2193 | unsigned HOST_WIDE_INT part_mask = (HOST_WIDE_INT_1U << part_bits) - 1; |
f19a9af7 | 2194 | int i; |
38899e29 | 2195 | |
f19a9af7 | 2196 | for (i = 0; i < max_parts; i++) |
4023fb28 | 2197 | { |
f19a9af7 | 2198 | if (i == 0) |
406fde6e | 2199 | value = UINTVAL (op); |
4023fb28 | 2200 | else |
f19a9af7 | 2201 | value >>= part_bits; |
38899e29 | 2202 | |
f19a9af7 AK |
2203 | if ((value & part_mask) != (def & part_mask)) |
2204 | return value & part_mask; | |
4023fb28 | 2205 | } |
38899e29 | 2206 | |
8d933e31 | 2207 | gcc_unreachable (); |
4023fb28 UW |
2208 | } |
2209 | ||
2210 | /* If OP is an integer constant of mode MODE with exactly one | |
f19a9af7 AK |
2211 | part of mode PART_MODE unequal to DEF, return the number of that |
2212 | part. Otherwise, return -1. */ | |
4023fb28 UW |
2213 | |
2214 | int | |
38899e29 | 2215 | s390_single_part (rtx op, |
ef4bddc2 RS |
2216 | machine_mode mode, |
2217 | machine_mode part_mode, | |
f19a9af7 AK |
2218 | int def) |
2219 | { | |
2220 | unsigned HOST_WIDE_INT value = 0; | |
2221 | int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode); | |
c4d50129 | 2222 | unsigned HOST_WIDE_INT part_mask |
406fde6e | 2223 | = (HOST_WIDE_INT_1U << GET_MODE_BITSIZE (part_mode)) - 1; |
f19a9af7 AK |
2224 | int i, part = -1; |
2225 | ||
2226 | if (GET_CODE (op) != CONST_INT) | |
2227 | return -1; | |
38899e29 | 2228 | |
f19a9af7 AK |
2229 | for (i = 0; i < n_parts; i++) |
2230 | { | |
2231 | if (i == 0) | |
406fde6e | 2232 | value = UINTVAL (op); |
4023fb28 | 2233 | else |
f19a9af7 | 2234 | value >>= GET_MODE_BITSIZE (part_mode); |
38899e29 | 2235 | |
f19a9af7 AK |
2236 | if ((value & part_mask) != (def & part_mask)) |
2237 | { | |
2238 | if (part != -1) | |
2239 | return -1; | |
2240 | else | |
2241 | part = i; | |
2242 | } | |
4023fb28 | 2243 | } |
f19a9af7 | 2244 | return part == -1 ? -1 : n_parts - 1 - part; |
4023fb28 UW |
2245 | } |
2246 | ||
963fc8d0 | 2247 | /* Return true if IN contains a contiguous bitfield in the lower SIZE |
c2586c82 | 2248 | bits and no other bits are set in (the lower SIZE bits of) IN. |
963fc8d0 | 2249 | |
c2586c82 DV |
2250 | PSTART and PEND can be used to obtain the start and end |
2251 | position (inclusive) of the bitfield relative to 64 | |
2252 | bits. *PSTART / *PEND gives the position of the first/last bit | |
2253 | of the bitfield counting from the highest order bit starting | |
2254 | with zero. */ | |
963fc8d0 AK |
2255 | |
2256 | bool | |
c2586c82 DV |
2257 | s390_contiguous_bitmask_nowrap_p (unsigned HOST_WIDE_INT in, int size, |
2258 | int *pstart, int *pend) | |
963fc8d0 | 2259 | { |
c2586c82 DV |
2260 | int start; |
2261 | int end = -1; | |
406fde6e DV |
2262 | int lowbit = HOST_BITS_PER_WIDE_INT - 1; |
2263 | int highbit = HOST_BITS_PER_WIDE_INT - size; | |
2264 | unsigned HOST_WIDE_INT bitmask = HOST_WIDE_INT_1U; | |
c2586c82 DV |
2265 | |
2266 | gcc_assert (!!pstart == !!pend); | |
2267 | for (start = lowbit; start >= highbit; bitmask <<= 1, start--) | |
2268 | if (end == -1) | |
2269 | { | |
2270 | /* Look for the rightmost bit of a contiguous range of ones. */ | |
2271 | if (bitmask & in) | |
2272 | /* Found it. */ | |
2273 | end = start; | |
2274 | } | |
2275 | else | |
2276 | { | |
2277 | /* Look for the firt zero bit after the range of ones. */ | |
2278 | if (! (bitmask & in)) | |
2279 | /* Found it. */ | |
2280 | break; | |
2281 | } | |
2282 | /* We're one past the last one-bit. */ | |
2283 | start++; | |
963fc8d0 | 2284 | |
c2586c82 DV |
2285 | if (end == -1) |
2286 | /* No one bits found. */ | |
2287 | return false; | |
2288 | ||
2289 | if (start > highbit) | |
963fc8d0 | 2290 | { |
c2586c82 DV |
2291 | unsigned HOST_WIDE_INT mask; |
2292 | ||
2293 | /* Calculate a mask for all bits beyond the contiguous bits. */ | |
406fde6e DV |
2294 | mask = ((~HOST_WIDE_INT_0U >> highbit) |
2295 | & (~HOST_WIDE_INT_0U << (lowbit - start + 1))); | |
c2586c82 DV |
2296 | if (mask & in) |
2297 | /* There are more bits set beyond the first range of one bits. */ | |
2298 | return false; | |
963fc8d0 AK |
2299 | } |
2300 | ||
c2586c82 DV |
2301 | if (pstart) |
2302 | { | |
2303 | *pstart = start; | |
2304 | *pend = end; | |
2305 | } | |
963fc8d0 | 2306 | |
c2586c82 DV |
2307 | return true; |
2308 | } | |
963fc8d0 | 2309 | |
c2586c82 DV |
2310 | /* Same as s390_contiguous_bitmask_nowrap_p but also returns true |
2311 | if ~IN contains a contiguous bitfield. In that case, *END is < | |
2312 | *START. | |
085261c8 | 2313 | |
c2586c82 DV |
2314 | If WRAP_P is true, a bitmask that wraps around is also tested. |
2315 | When a wraparoud occurs *START is greater than *END (in | |
2316 | non-null pointers), and the uppermost (64 - SIZE) bits are thus | |
2317 | part of the range. If WRAP_P is false, no wraparound is | |
2318 | tested. */ | |
963fc8d0 | 2319 | |
c2586c82 DV |
2320 | bool |
2321 | s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, bool wrap_p, | |
2322 | int size, int *start, int *end) | |
2323 | { | |
406fde6e | 2324 | int bs = HOST_BITS_PER_WIDE_INT; |
c2586c82 DV |
2325 | bool b; |
2326 | ||
2327 | gcc_assert (!!start == !!end); | |
406fde6e | 2328 | if ((in & ((~HOST_WIDE_INT_0U) >> (bs - size))) == 0) |
c2586c82 DV |
2329 | /* This cannot be expressed as a contiguous bitmask. Exit early because |
2330 | the second call of s390_contiguous_bitmask_nowrap_p would accept this as | |
2331 | a valid bitmask. */ | |
963fc8d0 | 2332 | return false; |
c2586c82 DV |
2333 | b = s390_contiguous_bitmask_nowrap_p (in, size, start, end); |
2334 | if (b) | |
2335 | return true; | |
2336 | if (! wrap_p) | |
2337 | return false; | |
2338 | b = s390_contiguous_bitmask_nowrap_p (~in, size, start, end); | |
2339 | if (b && start) | |
2340 | { | |
2341 | int s = *start; | |
2342 | int e = *end; | |
963fc8d0 | 2343 | |
c2586c82 DV |
2344 | gcc_assert (s >= 1); |
2345 | *start = ((e + 1) & (bs - 1)); | |
2346 | *end = ((s - 1 + bs) & (bs - 1)); | |
2347 | } | |
963fc8d0 | 2348 | |
c2586c82 | 2349 | return b; |
963fc8d0 AK |
2350 | } |
2351 | ||
085261c8 AK |
2352 | /* Return true if OP contains the same contiguous bitfield in *all* |
2353 | its elements. START and END can be used to obtain the start and | |
2354 | end position of the bitfield. | |
2355 | ||
2356 | START/STOP give the position of the first/last bit of the bitfield | |
2357 | counting from the lowest order bit starting with zero. In order to | |
2358 | use these values for S/390 instructions this has to be converted to | |
2359 | "bits big endian" style. */ | |
2360 | ||
2361 | bool | |
2362 | s390_contiguous_bitmask_vector_p (rtx op, int *start, int *end) | |
2363 | { | |
2364 | unsigned HOST_WIDE_INT mask; | |
c2586c82 | 2365 | int size; |
92695fbb | 2366 | rtx elt; |
c2586c82 | 2367 | bool b; |
085261c8 | 2368 | |
c2586c82 | 2369 | gcc_assert (!!start == !!end); |
92695fbb RS |
2370 | if (!const_vec_duplicate_p (op, &elt) |
2371 | || !CONST_INT_P (elt)) | |
085261c8 AK |
2372 | return false; |
2373 | ||
085261c8 | 2374 | size = GET_MODE_UNIT_BITSIZE (GET_MODE (op)); |
1ce8ee74 AK |
2375 | |
2376 | /* We cannot deal with V1TI/V1TF. This would require a vgmq. */ | |
2377 | if (size > 64) | |
2378 | return false; | |
2379 | ||
92695fbb | 2380 | mask = UINTVAL (elt); |
c2586c82 DV |
2381 | |
2382 | b = s390_contiguous_bitmask_p (mask, true, size, start, end); | |
2383 | if (b) | |
085261c8 | 2384 | { |
c2586c82 DV |
2385 | if (start) |
2386 | { | |
406fde6e DV |
2387 | *start -= (HOST_BITS_PER_WIDE_INT - size); |
2388 | *end -= (HOST_BITS_PER_WIDE_INT - size); | |
c2586c82 | 2389 | } |
085261c8 AK |
2390 | return true; |
2391 | } | |
c2586c82 DV |
2392 | else |
2393 | return false; | |
085261c8 AK |
2394 | } |
2395 | ||
2396 | /* Return true if C consists only of byte chunks being either 0 or | |
2397 | 0xff. If MASK is !=NULL a byte mask is generated which is | |
2398 | appropriate for the vector generate byte mask instruction. */ | |
2399 | ||
2400 | bool | |
2401 | s390_bytemask_vector_p (rtx op, unsigned *mask) | |
2402 | { | |
2403 | int i; | |
2404 | unsigned tmp_mask = 0; | |
2405 | int nunit, unit_size; | |
2406 | ||
2407 | if (!VECTOR_MODE_P (GET_MODE (op)) | |
2408 | || GET_CODE (op) != CONST_VECTOR | |
2409 | || !CONST_INT_P (XVECEXP (op, 0, 0))) | |
2410 | return false; | |
2411 | ||
2412 | nunit = GET_MODE_NUNITS (GET_MODE (op)); | |
2413 | unit_size = GET_MODE_UNIT_SIZE (GET_MODE (op)); | |
2414 | ||
2415 | for (i = 0; i < nunit; i++) | |
2416 | { | |
2417 | unsigned HOST_WIDE_INT c; | |
2418 | int j; | |
2419 | ||
2420 | if (!CONST_INT_P (XVECEXP (op, 0, i))) | |
2421 | return false; | |
2422 | ||
2423 | c = UINTVAL (XVECEXP (op, 0, i)); | |
2424 | for (j = 0; j < unit_size; j++) | |
2425 | { | |
2426 | if ((c & 0xff) != 0 && (c & 0xff) != 0xff) | |
2427 | return false; | |
2428 | tmp_mask |= (c & 1) << ((nunit - 1 - i) * unit_size + j); | |
2429 | c = c >> BITS_PER_UNIT; | |
2430 | } | |
2431 | } | |
2432 | ||
2433 | if (mask != NULL) | |
2434 | *mask = tmp_mask; | |
2435 | ||
2436 | return true; | |
2437 | } | |
2438 | ||
1a2e356e RH |
2439 | /* Check whether a rotate of ROTL followed by an AND of CONTIG is |
2440 | equivalent to a shift followed by the AND. In particular, CONTIG | |
2441 | should not overlap the (rotated) bit 0/bit 63 gap. Negative values | |
2442 | for ROTL indicate a rotate to the right. */ | |
2443 | ||
2444 | bool | |
2445 | s390_extzv_shift_ok (int bitsize, int rotl, unsigned HOST_WIDE_INT contig) | |
2446 | { | |
c2586c82 | 2447 | int start, end; |
1a2e356e RH |
2448 | bool ok; |
2449 | ||
c2586c82 | 2450 | ok = s390_contiguous_bitmask_nowrap_p (contig, bitsize, &start, &end); |
1a2e356e RH |
2451 | gcc_assert (ok); |
2452 | ||
c2586c82 DV |
2453 | if (rotl >= 0) |
2454 | return (64 - end >= rotl); | |
2455 | else | |
2456 | { | |
2457 | /* Translate "- rotate right" in BITSIZE mode to "rotate left" in | |
2458 | DIMode. */ | |
2459 | rotl = -rotl + (64 - bitsize); | |
2460 | return (start >= rotl); | |
2461 | } | |
1a2e356e RH |
2462 | } |
2463 | ||
c7453384 EC |
2464 | /* Check whether we can (and want to) split a double-word |
2465 | move in mode MODE from SRC to DST into two single-word | |
dc65c307 UW |
2466 | moves, moving the subword FIRST_SUBWORD first. */ |
2467 | ||
2468 | bool | |
ef4bddc2 | 2469 | s390_split_ok_p (rtx dst, rtx src, machine_mode mode, int first_subword) |
dc65c307 | 2470 | { |
085261c8 AK |
2471 | /* Floating point and vector registers cannot be split. */ |
2472 | if (FP_REG_P (src) || FP_REG_P (dst) || VECTOR_REG_P (src) || VECTOR_REG_P (dst)) | |
dc65c307 UW |
2473 | return false; |
2474 | ||
dc65c307 UW |
2475 | /* Non-offsettable memory references cannot be split. */ |
2476 | if ((GET_CODE (src) == MEM && !offsettable_memref_p (src)) | |
2477 | || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst))) | |
2478 | return false; | |
2479 | ||
2480 | /* Moving the first subword must not clobber a register | |
2481 | needed to move the second subword. */ | |
2482 | if (register_operand (dst, mode)) | |
2483 | { | |
2484 | rtx subreg = operand_subword (dst, first_subword, 0, mode); | |
2485 | if (reg_overlap_mentioned_p (subreg, src)) | |
2486 | return false; | |
2487 | } | |
2488 | ||
2489 | return true; | |
2490 | } | |
2491 | ||
bcf8c1cc AK |
2492 | /* Return true if it can be proven that [MEM1, MEM1 + SIZE] |
2493 | and [MEM2, MEM2 + SIZE] do overlap and false | |
2494 | otherwise. */ | |
2495 | ||
2496 | bool | |
2497 | s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size) | |
2498 | { | |
2499 | rtx addr1, addr2, addr_delta; | |
2500 | HOST_WIDE_INT delta; | |
2501 | ||
2502 | if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM) | |
2503 | return true; | |
2504 | ||
2505 | if (size == 0) | |
2506 | return false; | |
2507 | ||
2508 | addr1 = XEXP (mem1, 0); | |
2509 | addr2 = XEXP (mem2, 0); | |
2510 | ||
2511 | addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1); | |
2512 | ||
2513 | /* This overlapping check is used by peepholes merging memory block operations. | |
2514 | Overlapping operations would otherwise be recognized by the S/390 hardware | |
f4aa3848 | 2515 | and would fall back to a slower implementation. Allowing overlapping |
bcf8c1cc | 2516 | operations would lead to slow code but not to wrong code. Therefore we are |
f4aa3848 | 2517 | somewhat optimistic if we cannot prove that the memory blocks are |
bcf8c1cc AK |
2518 | overlapping. |
2519 | That's why we return false here although this may accept operations on | |
2520 | overlapping memory areas. */ | |
2521 | if (!addr_delta || GET_CODE (addr_delta) != CONST_INT) | |
2522 | return false; | |
2523 | ||
2524 | delta = INTVAL (addr_delta); | |
2525 | ||
2526 | if (delta == 0 | |
2527 | || (delta > 0 && delta < size) | |
2528 | || (delta < 0 && -delta < size)) | |
2529 | return true; | |
2530 | ||
2531 | return false; | |
2532 | } | |
2533 | ||
19b63d8e UW |
2534 | /* Check whether the address of memory reference MEM2 equals exactly |
2535 | the address of memory reference MEM1 plus DELTA. Return true if | |
2536 | we can prove this to be the case, false otherwise. */ | |
2537 | ||
2538 | bool | |
2539 | s390_offset_p (rtx mem1, rtx mem2, rtx delta) | |
2540 | { | |
2541 | rtx addr1, addr2, addr_delta; | |
2542 | ||
2543 | if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM) | |
2544 | return false; | |
2545 | ||
2546 | addr1 = XEXP (mem1, 0); | |
2547 | addr2 = XEXP (mem2, 0); | |
2548 | ||
2549 | addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1); | |
2550 | if (!addr_delta || !rtx_equal_p (addr_delta, delta)) | |
2551 | return false; | |
2552 | ||
2553 | return true; | |
2554 | } | |
2555 | ||
8cb66696 UW |
2556 | /* Expand logical operator CODE in mode MODE with operands OPERANDS. */ |
2557 | ||
2558 | void | |
ef4bddc2 | 2559 | s390_expand_logical_operator (enum rtx_code code, machine_mode mode, |
8cb66696 UW |
2560 | rtx *operands) |
2561 | { | |
ef4bddc2 | 2562 | machine_mode wmode = mode; |
8cb66696 UW |
2563 | rtx dst = operands[0]; |
2564 | rtx src1 = operands[1]; | |
2565 | rtx src2 = operands[2]; | |
2566 | rtx op, clob, tem; | |
2567 | ||
2568 | /* If we cannot handle the operation directly, use a temp register. */ | |
2569 | if (!s390_logical_operator_ok_p (operands)) | |
2570 | dst = gen_reg_rtx (mode); | |
2571 | ||
2572 | /* QImode and HImode patterns make sense only if we have a destination | |
2573 | in memory. Otherwise perform the operation in SImode. */ | |
2574 | if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM) | |
2575 | wmode = SImode; | |
2576 | ||
2577 | /* Widen operands if required. */ | |
2578 | if (mode != wmode) | |
2579 | { | |
2580 | if (GET_CODE (dst) == SUBREG | |
2581 | && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0) | |
2582 | dst = tem; | |
2583 | else if (REG_P (dst)) | |
2584 | dst = gen_rtx_SUBREG (wmode, dst, 0); | |
2585 | else | |
2586 | dst = gen_reg_rtx (wmode); | |
2587 | ||
2588 | if (GET_CODE (src1) == SUBREG | |
2589 | && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0) | |
2590 | src1 = tem; | |
2591 | else if (GET_MODE (src1) != VOIDmode) | |
2592 | src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0); | |
2593 | ||
2594 | if (GET_CODE (src2) == SUBREG | |
2595 | && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0) | |
2596 | src2 = tem; | |
2597 | else if (GET_MODE (src2) != VOIDmode) | |
2598 | src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0); | |
2599 | } | |
2600 | ||
2601 | /* Emit the instruction. */ | |
f7df4a84 | 2602 | op = gen_rtx_SET (dst, gen_rtx_fmt_ee (code, wmode, src1, src2)); |
8cb66696 UW |
2603 | clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); |
2604 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob))); | |
2605 | ||
2606 | /* Fix up the destination if needed. */ | |
2607 | if (dst != operands[0]) | |
2608 | emit_move_insn (operands[0], gen_lowpart (mode, dst)); | |
2609 | } | |
2610 | ||
2611 | /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */ | |
2612 | ||
2613 | bool | |
2614 | s390_logical_operator_ok_p (rtx *operands) | |
2615 | { | |
2616 | /* If the destination operand is in memory, it needs to coincide | |
2617 | with one of the source operands. After reload, it has to be | |
2618 | the first source operand. */ | |
2619 | if (GET_CODE (operands[0]) == MEM) | |
2620 | return rtx_equal_p (operands[0], operands[1]) | |
2621 | || (!reload_completed && rtx_equal_p (operands[0], operands[2])); | |
2622 | ||
2623 | return true; | |
2624 | } | |
2625 | ||
0dfa6c5e UW |
2626 | /* Narrow logical operation CODE of memory operand MEMOP with immediate |
2627 | operand IMMOP to switch from SS to SI type instructions. */ | |
2628 | ||
2629 | void | |
2630 | s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop) | |
2631 | { | |
2632 | int def = code == AND ? -1 : 0; | |
2633 | HOST_WIDE_INT mask; | |
2634 | int part; | |
2635 | ||
2636 | gcc_assert (GET_CODE (*memop) == MEM); | |
2637 | gcc_assert (!MEM_VOLATILE_P (*memop)); | |
2638 | ||
2639 | mask = s390_extract_part (*immop, QImode, def); | |
2640 | part = s390_single_part (*immop, GET_MODE (*memop), QImode, def); | |
2641 | gcc_assert (part >= 0); | |
2642 | ||
2643 | *memop = adjust_address (*memop, QImode, part); | |
2644 | *immop = gen_int_mode (mask, QImode); | |
2645 | } | |
2646 | ||
ba956982 | 2647 | |
ab96de7e AS |
2648 | /* How to allocate a 'struct machine_function'. */ |
2649 | ||
2650 | static struct machine_function * | |
2651 | s390_init_machine_status (void) | |
2652 | { | |
766090c2 | 2653 | return ggc_cleared_alloc<machine_function> (); |
ab96de7e AS |
2654 | } |
2655 | ||
9db1d521 HP |
2656 | /* Map for smallest class containing reg regno. */ |
2657 | ||
0139adca | 2658 | const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] = |
085261c8 AK |
2659 | { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, /* 0 */ |
2660 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, /* 4 */ | |
2661 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, /* 8 */ | |
2662 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, /* 12 */ | |
2663 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, /* 16 */ | |
2664 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, /* 20 */ | |
2665 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, /* 24 */ | |
2666 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, /* 28 */ | |
2667 | ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS, /* 32 */ | |
2668 | ACCESS_REGS, ACCESS_REGS, VEC_REGS, VEC_REGS, /* 36 */ | |
2669 | VEC_REGS, VEC_REGS, VEC_REGS, VEC_REGS, /* 40 */ | |
2670 | VEC_REGS, VEC_REGS, VEC_REGS, VEC_REGS, /* 44 */ | |
2671 | VEC_REGS, VEC_REGS, VEC_REGS, VEC_REGS, /* 48 */ | |
2672 | VEC_REGS, VEC_REGS /* 52 */ | |
9db1d521 HP |
2673 | }; |
2674 | ||
077dab3b HP |
2675 | /* Return attribute type of insn. */ |
2676 | ||
2677 | static enum attr_type | |
647d790d | 2678 | s390_safe_attr_type (rtx_insn *insn) |
077dab3b HP |
2679 | { |
2680 | if (recog_memoized (insn) >= 0) | |
2681 | return get_attr_type (insn); | |
2682 | else | |
2683 | return TYPE_NONE; | |
2684 | } | |
9db1d521 | 2685 | |
d3632d41 UW |
2686 | /* Return true if DISP is a valid short displacement. */ |
2687 | ||
3ed99cc9 | 2688 | static bool |
9c808aad | 2689 | s390_short_displacement (rtx disp) |
d3632d41 UW |
2690 | { |
2691 | /* No displacement is OK. */ | |
2692 | if (!disp) | |
3ed99cc9 | 2693 | return true; |
d3632d41 | 2694 | |
4fe6dea8 AK |
2695 | /* Without the long displacement facility we don't need to |
2696 | distingiush between long and short displacement. */ | |
2697 | if (!TARGET_LONG_DISPLACEMENT) | |
2698 | return true; | |
2699 | ||
d3632d41 UW |
2700 | /* Integer displacement in range. */ |
2701 | if (GET_CODE (disp) == CONST_INT) | |
2702 | return INTVAL (disp) >= 0 && INTVAL (disp) < 4096; | |
2703 | ||
2704 | /* GOT offset is not OK, the GOT can be large. */ | |
2705 | if (GET_CODE (disp) == CONST | |
2706 | && GET_CODE (XEXP (disp, 0)) == UNSPEC | |
227a39fa UW |
2707 | && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT |
2708 | || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF)) | |
3ed99cc9 | 2709 | return false; |
d3632d41 UW |
2710 | |
2711 | /* All other symbolic constants are literal pool references, | |
2712 | which are OK as the literal pool must be small. */ | |
2713 | if (GET_CODE (disp) == CONST) | |
3ed99cc9 | 2714 | return true; |
d3632d41 | 2715 | |
3ed99cc9 | 2716 | return false; |
d3632d41 UW |
2717 | } |
2718 | ||
ab96de7e AS |
2719 | /* Decompose a RTL expression ADDR for a memory address into |
2720 | its components, returned in OUT. | |
ccfc6cc8 | 2721 | |
3ed99cc9 | 2722 | Returns false if ADDR is not a valid memory address, true |
ab96de7e AS |
2723 | otherwise. If OUT is NULL, don't return the components, |
2724 | but check for validity only. | |
ccfc6cc8 | 2725 | |
ab96de7e AS |
2726 | Note: Only addresses in canonical form are recognized. |
2727 | LEGITIMIZE_ADDRESS should convert non-canonical forms to the | |
2728 | canonical form so that they will be recognized. */ | |
f19a9af7 | 2729 | |
ab96de7e | 2730 | static int |
5d81b82b | 2731 | s390_decompose_address (rtx addr, struct s390_address *out) |
ab96de7e AS |
2732 | { |
2733 | HOST_WIDE_INT offset = 0; | |
2734 | rtx base = NULL_RTX; | |
2735 | rtx indx = NULL_RTX; | |
2736 | rtx disp = NULL_RTX; | |
2737 | rtx orig_disp; | |
3ed99cc9 AS |
2738 | bool pointer = false; |
2739 | bool base_ptr = false; | |
2740 | bool indx_ptr = false; | |
f01cf809 UW |
2741 | bool literal_pool = false; |
2742 | ||
2743 | /* We may need to substitute the literal pool base register into the address | |
2744 | below. However, at this point we do not know which register is going to | |
2745 | be used as base, so we substitute the arg pointer register. This is going | |
2746 | to be treated as holding a pointer below -- it shouldn't be used for any | |
2747 | other purpose. */ | |
2748 | rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM); | |
0dfa6c5e | 2749 | |
ab96de7e | 2750 | /* Decompose address into base + index + displacement. */ |
0dfa6c5e | 2751 | |
ab96de7e AS |
2752 | if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC) |
2753 | base = addr; | |
0dfa6c5e | 2754 | |
ab96de7e | 2755 | else if (GET_CODE (addr) == PLUS) |
e221ef54 | 2756 | { |
ab96de7e AS |
2757 | rtx op0 = XEXP (addr, 0); |
2758 | rtx op1 = XEXP (addr, 1); | |
2759 | enum rtx_code code0 = GET_CODE (op0); | |
2760 | enum rtx_code code1 = GET_CODE (op1); | |
e221ef54 | 2761 | |
ab96de7e AS |
2762 | if (code0 == REG || code0 == UNSPEC) |
2763 | { | |
2764 | if (code1 == REG || code1 == UNSPEC) | |
2765 | { | |
2766 | indx = op0; /* index + base */ | |
2767 | base = op1; | |
2768 | } | |
e221ef54 | 2769 | |
ab96de7e AS |
2770 | else |
2771 | { | |
2772 | base = op0; /* base + displacement */ | |
2773 | disp = op1; | |
2774 | } | |
2775 | } | |
ccfc6cc8 | 2776 | |
ab96de7e | 2777 | else if (code0 == PLUS) |
d3632d41 | 2778 | { |
ab96de7e AS |
2779 | indx = XEXP (op0, 0); /* index + base + disp */ |
2780 | base = XEXP (op0, 1); | |
2781 | disp = op1; | |
d3632d41 | 2782 | } |
d3632d41 | 2783 | |
ab96de7e | 2784 | else |
d3632d41 | 2785 | { |
3ed99cc9 | 2786 | return false; |
d3632d41 | 2787 | } |
ab96de7e | 2788 | } |
d3632d41 | 2789 | |
ab96de7e AS |
2790 | else |
2791 | disp = addr; /* displacement */ | |
d3632d41 | 2792 | |
ab96de7e AS |
2793 | /* Extract integer part of displacement. */ |
2794 | orig_disp = disp; | |
2795 | if (disp) | |
2796 | { | |
2797 | if (GET_CODE (disp) == CONST_INT) | |
d3632d41 | 2798 | { |
ab96de7e AS |
2799 | offset = INTVAL (disp); |
2800 | disp = NULL_RTX; | |
d3632d41 | 2801 | } |
ab96de7e AS |
2802 | else if (GET_CODE (disp) == CONST |
2803 | && GET_CODE (XEXP (disp, 0)) == PLUS | |
2804 | && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT) | |
2805 | { | |
2806 | offset = INTVAL (XEXP (XEXP (disp, 0), 1)); | |
2807 | disp = XEXP (XEXP (disp, 0), 0); | |
2808 | } | |
2809 | } | |
d3632d41 | 2810 | |
ab96de7e AS |
2811 | /* Strip off CONST here to avoid special case tests later. */ |
2812 | if (disp && GET_CODE (disp) == CONST) | |
2813 | disp = XEXP (disp, 0); | |
ac32b25e | 2814 | |
ab96de7e AS |
2815 | /* We can convert literal pool addresses to |
2816 | displacements by basing them off the base register. */ | |
2817 | if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp)) | |
2818 | { | |
085db63d AK |
2819 | if (base || indx) |
2820 | return false; | |
2821 | ||
2822 | base = fake_pool_base, literal_pool = true; | |
ab96de7e AS |
2823 | |
2824 | /* Mark up the displacement. */ | |
2825 | disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp), | |
2826 | UNSPEC_LTREL_OFFSET); | |
d3632d41 | 2827 | } |
ccfc6cc8 | 2828 | |
ab96de7e AS |
2829 | /* Validate base register. */ |
2830 | if (base) | |
2831 | { | |
2832 | if (GET_CODE (base) == UNSPEC) | |
2833 | switch (XINT (base, 1)) | |
2834 | { | |
2835 | case UNSPEC_LTREF: | |
2836 | if (!disp) | |
f4aa3848 | 2837 | disp = gen_rtx_UNSPEC (Pmode, |
ab96de7e AS |
2838 | gen_rtvec (1, XVECEXP (base, 0, 0)), |
2839 | UNSPEC_LTREL_OFFSET); | |
2840 | else | |
3ed99cc9 | 2841 | return false; |
ccfc6cc8 | 2842 | |
f01cf809 | 2843 | base = XVECEXP (base, 0, 1); |
ab96de7e | 2844 | break; |
f19a9af7 | 2845 | |
ab96de7e | 2846 | case UNSPEC_LTREL_BASE: |
f01cf809 UW |
2847 | if (XVECLEN (base, 0) == 1) |
2848 | base = fake_pool_base, literal_pool = true; | |
2849 | else | |
2850 | base = XVECEXP (base, 0, 1); | |
ab96de7e | 2851 | break; |
f19a9af7 | 2852 | |
ab96de7e | 2853 | default: |
3ed99cc9 | 2854 | return false; |
ab96de7e | 2855 | } |
f19a9af7 | 2856 | |
c64181a8 | 2857 | if (!REG_P (base) || GET_MODE (base) != Pmode) |
3ed99cc9 | 2858 | return false; |
ab96de7e | 2859 | |
f01cf809 | 2860 | if (REGNO (base) == STACK_POINTER_REGNUM |
ab96de7e AS |
2861 | || REGNO (base) == FRAME_POINTER_REGNUM |
2862 | || ((reload_completed || reload_in_progress) | |
2863 | && frame_pointer_needed | |
2864 | && REGNO (base) == HARD_FRAME_POINTER_REGNUM) | |
2865 | || REGNO (base) == ARG_POINTER_REGNUM | |
2866 | || (flag_pic | |
2867 | && REGNO (base) == PIC_OFFSET_TABLE_REGNUM)) | |
3ed99cc9 | 2868 | pointer = base_ptr = true; |
f01cf809 UW |
2869 | |
2870 | if ((reload_completed || reload_in_progress) | |
2871 | && base == cfun->machine->base_reg) | |
2872 | pointer = base_ptr = literal_pool = true; | |
ab96de7e AS |
2873 | } |
2874 | ||
2875 | /* Validate index register. */ | |
2876 | if (indx) | |
f19a9af7 | 2877 | { |
ab96de7e AS |
2878 | if (GET_CODE (indx) == UNSPEC) |
2879 | switch (XINT (indx, 1)) | |
2880 | { | |
2881 | case UNSPEC_LTREF: | |
2882 | if (!disp) | |
f4aa3848 | 2883 | disp = gen_rtx_UNSPEC (Pmode, |
ab96de7e AS |
2884 | gen_rtvec (1, XVECEXP (indx, 0, 0)), |
2885 | UNSPEC_LTREL_OFFSET); | |
2886 | else | |
3ed99cc9 | 2887 | return false; |
f19a9af7 | 2888 | |
f01cf809 | 2889 | indx = XVECEXP (indx, 0, 1); |
ab96de7e | 2890 | break; |
f19a9af7 | 2891 | |
ab96de7e | 2892 | case UNSPEC_LTREL_BASE: |
f01cf809 UW |
2893 | if (XVECLEN (indx, 0) == 1) |
2894 | indx = fake_pool_base, literal_pool = true; | |
2895 | else | |
2896 | indx = XVECEXP (indx, 0, 1); | |
ab96de7e | 2897 | break; |
f19a9af7 | 2898 | |
ab96de7e | 2899 | default: |
3ed99cc9 | 2900 | return false; |
ab96de7e | 2901 | } |
f19a9af7 | 2902 | |
c64181a8 | 2903 | if (!REG_P (indx) || GET_MODE (indx) != Pmode) |
3ed99cc9 | 2904 | return false; |
f19a9af7 | 2905 | |
f01cf809 | 2906 | if (REGNO (indx) == STACK_POINTER_REGNUM |
ab96de7e AS |
2907 | || REGNO (indx) == FRAME_POINTER_REGNUM |
2908 | || ((reload_completed || reload_in_progress) | |
2909 | && frame_pointer_needed | |
2910 | && REGNO (indx) == HARD_FRAME_POINTER_REGNUM) | |
2911 | || REGNO (indx) == ARG_POINTER_REGNUM | |
2912 | || (flag_pic | |
2913 | && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM)) | |
3ed99cc9 | 2914 | pointer = indx_ptr = true; |
f01cf809 UW |
2915 | |
2916 | if ((reload_completed || reload_in_progress) | |
2917 | && indx == cfun->machine->base_reg) | |
2918 | pointer = indx_ptr = literal_pool = true; | |
ab96de7e | 2919 | } |
38899e29 | 2920 | |
ab96de7e AS |
2921 | /* Prefer to use pointer as base, not index. */ |
2922 | if (base && indx && !base_ptr | |
2923 | && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx)))) | |
2924 | { | |
2925 | rtx tmp = base; | |
2926 | base = indx; | |
2927 | indx = tmp; | |
2928 | } | |
f19a9af7 | 2929 | |
ab96de7e AS |
2930 | /* Validate displacement. */ |
2931 | if (!disp) | |
2932 | { | |
f4aa3848 AK |
2933 | /* If virtual registers are involved, the displacement will change later |
2934 | anyway as the virtual registers get eliminated. This could make a | |
2935 | valid displacement invalid, but it is more likely to make an invalid | |
2936 | displacement valid, because we sometimes access the register save area | |
63296cb1 | 2937 | via negative offsets to one of those registers. |
ab96de7e AS |
2938 | Thus we don't check the displacement for validity here. If after |
2939 | elimination the displacement turns out to be invalid after all, | |
2940 | this is fixed up by reload in any case. */ | |
3597e113 VM |
2941 | /* LRA maintains always displacements up to date and we need to |
2942 | know the displacement is right during all LRA not only at the | |
2943 | final elimination. */ | |
2944 | if (lra_in_progress | |
2945 | || (base != arg_pointer_rtx | |
2946 | && indx != arg_pointer_rtx | |
2947 | && base != return_address_pointer_rtx | |
2948 | && indx != return_address_pointer_rtx | |
2949 | && base != frame_pointer_rtx | |
2950 | && indx != frame_pointer_rtx | |
2951 | && base != virtual_stack_vars_rtx | |
2952 | && indx != virtual_stack_vars_rtx)) | |
ab96de7e | 2953 | if (!DISP_IN_RANGE (offset)) |
3ed99cc9 | 2954 | return false; |
ab96de7e AS |
2955 | } |
2956 | else | |
2957 | { | |
2958 | /* All the special cases are pointers. */ | |
3ed99cc9 | 2959 | pointer = true; |
f19a9af7 | 2960 | |
ab96de7e AS |
2961 | /* In the small-PIC case, the linker converts @GOT |
2962 | and @GOTNTPOFF offsets to possible displacements. */ | |
2963 | if (GET_CODE (disp) == UNSPEC | |
2964 | && (XINT (disp, 1) == UNSPEC_GOT | |
2965 | || XINT (disp, 1) == UNSPEC_GOTNTPOFF) | |
ab96de7e AS |
2966 | && flag_pic == 1) |
2967 | { | |
2968 | ; | |
2969 | } | |
f19a9af7 | 2970 | |
dc66391d RS |
2971 | /* Accept pool label offsets. */ |
2972 | else if (GET_CODE (disp) == UNSPEC | |
2973 | && XINT (disp, 1) == UNSPEC_POOL_OFFSET) | |
2974 | ; | |
f19a9af7 | 2975 | |
ab96de7e AS |
2976 | /* Accept literal pool references. */ |
2977 | else if (GET_CODE (disp) == UNSPEC | |
2978 | && XINT (disp, 1) == UNSPEC_LTREL_OFFSET) | |
2979 | { | |
bc6ce334 AK |
2980 | /* In case CSE pulled a non literal pool reference out of |
2981 | the pool we have to reject the address. This is | |
2982 | especially important when loading the GOT pointer on non | |
2983 | zarch CPUs. In this case the literal pool contains an lt | |
2984 | relative offset to the _GLOBAL_OFFSET_TABLE_ label which | |
2985 | will most likely exceed the displacement. */ | |
2986 | if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF | |
2987 | || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp, 0, 0))) | |
2988 | return false; | |
2989 | ||
ab96de7e AS |
2990 | orig_disp = gen_rtx_CONST (Pmode, disp); |
2991 | if (offset) | |
2992 | { | |
2993 | /* If we have an offset, make sure it does not | |
2994 | exceed the size of the constant pool entry. */ | |
2995 | rtx sym = XVECEXP (disp, 0, 0); | |
2996 | if (offset >= GET_MODE_SIZE (get_pool_mode (sym))) | |
3ed99cc9 | 2997 | return false; |
f19a9af7 | 2998 | |
0a81f074 | 2999 | orig_disp = plus_constant (Pmode, orig_disp, offset); |
ab96de7e AS |
3000 | } |
3001 | } | |
3002 | ||
3003 | else | |
3ed99cc9 | 3004 | return false; |
f19a9af7 AK |
3005 | } |
3006 | ||
ab96de7e | 3007 | if (!base && !indx) |
3ed99cc9 | 3008 | pointer = true; |
ab96de7e AS |
3009 | |
3010 | if (out) | |
3011 | { | |
3012 | out->base = base; | |
3013 | out->indx = indx; | |
3014 | out->disp = orig_disp; | |
3015 | out->pointer = pointer; | |
f01cf809 | 3016 | out->literal_pool = literal_pool; |
ab96de7e AS |
3017 | } |
3018 | ||
3ed99cc9 | 3019 | return true; |
f19a9af7 AK |
3020 | } |
3021 | ||
dd95128b AK |
3022 | /* Decompose a RTL expression OP for an address style operand into its |
3023 | components, and return the base register in BASE and the offset in | |
3024 | OFFSET. While OP looks like an address it is never supposed to be | |
3025 | used as such. | |
d98ad410 | 3026 | |
dd95128b | 3027 | Return true if OP is a valid address operand, false if not. */ |
d98ad410 UW |
3028 | |
3029 | bool | |
dd95128b AK |
3030 | s390_decompose_addrstyle_without_index (rtx op, rtx *base, |
3031 | HOST_WIDE_INT *offset) | |
d98ad410 | 3032 | { |
191eb16d | 3033 | rtx off = NULL_RTX; |
d98ad410 | 3034 | |
d98ad410 UW |
3035 | /* We can have an integer constant, an address register, |
3036 | or a sum of the two. */ | |
191eb16d | 3037 | if (CONST_SCALAR_INT_P (op)) |
d98ad410 | 3038 | { |
191eb16d | 3039 | off = op; |
d98ad410 UW |
3040 | op = NULL_RTX; |
3041 | } | |
191eb16d | 3042 | if (op && GET_CODE (op) == PLUS && CONST_SCALAR_INT_P (XEXP (op, 1))) |
d98ad410 | 3043 | { |
191eb16d | 3044 | off = XEXP (op, 1); |
d98ad410 UW |
3045 | op = XEXP (op, 0); |
3046 | } | |
3047 | while (op && GET_CODE (op) == SUBREG) | |
3048 | op = SUBREG_REG (op); | |
3049 | ||
3050 | if (op && GET_CODE (op) != REG) | |
3051 | return false; | |
3052 | ||
3053 | if (offset) | |
191eb16d AK |
3054 | { |
3055 | if (off == NULL_RTX) | |
3056 | *offset = 0; | |
3057 | else if (CONST_INT_P (off)) | |
3058 | *offset = INTVAL (off); | |
3059 | else if (CONST_WIDE_INT_P (off)) | |
3060 | /* The offset will anyway be cut down to 12 bits so take just | |
3061 | the lowest order chunk of the wide int. */ | |
3062 | *offset = CONST_WIDE_INT_ELT (off, 0); | |
3063 | else | |
3064 | gcc_unreachable (); | |
3065 | } | |
d98ad410 UW |
3066 | if (base) |
3067 | *base = op; | |
3068 | ||
3069 | return true; | |
3070 | } | |
3071 | ||
3072 | ||
ab96de7e | 3073 | /* Return true if CODE is a valid address without index. */ |
3c50106f | 3074 | |
ab96de7e AS |
3075 | bool |
3076 | s390_legitimate_address_without_index_p (rtx op) | |
3077 | { | |
3078 | struct s390_address addr; | |
3079 | ||
3080 | if (!s390_decompose_address (XEXP (op, 0), &addr)) | |
3081 | return false; | |
3082 | if (addr.indx) | |
3083 | return false; | |
3084 | ||
3085 | return true; | |
3086 | } | |
3087 | ||
cd8dc1f9 | 3088 | |
0ff4390d AK |
3089 | /* Return TRUE if ADDR is an operand valid for a load/store relative |
3090 | instruction. Be aware that the alignment of the operand needs to | |
3091 | be checked separately. | |
3092 | Valid addresses are single references or a sum of a reference and a | |
3093 | constant integer. Return these parts in SYMREF and ADDEND. You can | |
3094 | pass NULL in REF and/or ADDEND if you are not interested in these | |
3095 | values. Literal pool references are *not* considered symbol | |
3096 | references. */ | |
ab96de7e | 3097 | |
4fe6dea8 | 3098 | static bool |
0ff4390d | 3099 | s390_loadrelative_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend) |
ab96de7e | 3100 | { |
4fe6dea8 | 3101 | HOST_WIDE_INT tmpaddend = 0; |
ab96de7e | 3102 | |
4fe6dea8 AK |
3103 | if (GET_CODE (addr) == CONST) |
3104 | addr = XEXP (addr, 0); | |
3105 | ||
3106 | if (GET_CODE (addr) == PLUS) | |
ab96de7e | 3107 | { |
0ff4390d | 3108 | if (!CONST_INT_P (XEXP (addr, 1))) |
4fe6dea8 | 3109 | return false; |
ab96de7e | 3110 | |
0ff4390d AK |
3111 | tmpaddend = INTVAL (XEXP (addr, 1)); |
3112 | addr = XEXP (addr, 0); | |
3113 | } | |
98412b77 | 3114 | |
0ff4390d AK |
3115 | if ((GET_CODE (addr) == SYMBOL_REF && !CONSTANT_POOL_ADDRESS_P (addr)) |
3116 | || (GET_CODE (addr) == UNSPEC | |
3117 | && (XINT (addr, 1) == UNSPEC_GOTENT | |
3118 | || (TARGET_CPU_ZARCH && XINT (addr, 1) == UNSPEC_PLT)))) | |
3119 | { | |
3120 | if (symref) | |
3121 | *symref = addr; | |
3122 | if (addend) | |
3123 | *addend = tmpaddend; | |
98412b77 | 3124 | |
0ff4390d AK |
3125 | return true; |
3126 | } | |
3127 | return false; | |
98412b77 | 3128 | } |
4fe6dea8 AK |
3129 | |
3130 | /* Return true if the address in OP is valid for constraint letter C | |
3131 | if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal | |
3132 | pool MEMs should be accepted. Only the Q, R, S, T constraint | |
3133 | letters are allowed for C. */ | |
ab96de7e | 3134 | |
4fe6dea8 AK |
3135 | static int |
3136 | s390_check_qrst_address (char c, rtx op, bool lit_pool_ok) | |
3137 | { | |
3138 | struct s390_address addr; | |
3139 | bool decomposed = false; | |
3140 | ||
00e0af8d AK |
3141 | if (!address_operand (op, GET_MODE (op))) |
3142 | return 0; | |
3143 | ||
4fe6dea8 AK |
3144 | /* This check makes sure that no symbolic address (except literal |
3145 | pool references) are accepted by the R or T constraints. */ | |
0ff4390d | 3146 | if (s390_loadrelative_operand_p (op, NULL, NULL)) |
98635b04 UW |
3147 | return 0; |
3148 | ||
3149 | /* Ensure literal pool references are only accepted if LIT_POOL_OK. */ | |
3150 | if (!lit_pool_ok) | |
ab96de7e | 3151 | { |
4fe6dea8 | 3152 | if (!s390_decompose_address (op, &addr)) |
ab96de7e | 3153 | return 0; |
98635b04 | 3154 | if (addr.literal_pool) |
ab96de7e | 3155 | return 0; |
4fe6dea8 | 3156 | decomposed = true; |
ab96de7e AS |
3157 | } |
3158 | ||
3e4be43f UW |
3159 | /* With reload, we sometimes get intermediate address forms that are |
3160 | actually invalid as-is, but we need to accept them in the most | |
3161 | generic cases below ('R' or 'T'), since reload will in fact fix | |
3162 | them up. LRA behaves differently here; we never see such forms, | |
3163 | but on the other hand, we need to strictly reject every invalid | |
3164 | address form. Perform this check right up front. */ | |
3165 | if (lra_in_progress) | |
3166 | { | |
3167 | if (!decomposed && !s390_decompose_address (op, &addr)) | |
3168 | return 0; | |
3169 | decomposed = true; | |
3170 | } | |
3171 | ||
ab96de7e AS |
3172 | switch (c) |
3173 | { | |
4fe6dea8 AK |
3174 | case 'Q': /* no index short displacement */ |
3175 | if (!decomposed && !s390_decompose_address (op, &addr)) | |
ab96de7e AS |
3176 | return 0; |
3177 | if (addr.indx) | |
3178 | return 0; | |
4fe6dea8 | 3179 | if (!s390_short_displacement (addr.disp)) |
ab96de7e | 3180 | return 0; |
4fe6dea8 | 3181 | break; |
ab96de7e | 3182 | |
4fe6dea8 | 3183 | case 'R': /* with index short displacement */ |
ab96de7e AS |
3184 | if (TARGET_LONG_DISPLACEMENT) |
3185 | { | |
4fe6dea8 | 3186 | if (!decomposed && !s390_decompose_address (op, &addr)) |
ab96de7e AS |
3187 | return 0; |
3188 | if (!s390_short_displacement (addr.disp)) | |
3189 | return 0; | |
3190 | } | |
4fe6dea8 AK |
3191 | /* Any invalid address here will be fixed up by reload, |
3192 | so accept it for the most generic constraint. */ | |
ab96de7e AS |
3193 | break; |
3194 | ||
4fe6dea8 | 3195 | case 'S': /* no index long displacement */ |
4fe6dea8 | 3196 | if (!decomposed && !s390_decompose_address (op, &addr)) |
ab96de7e AS |
3197 | return 0; |
3198 | if (addr.indx) | |
3199 | return 0; | |
ab96de7e AS |
3200 | break; |
3201 | ||
4fe6dea8 | 3202 | case 'T': /* with index long displacement */ |
4fe6dea8 AK |
3203 | /* Any invalid address here will be fixed up by reload, |
3204 | so accept it for the most generic constraint. */ | |
ab96de7e | 3205 | break; |
3e4be43f | 3206 | |
4fe6dea8 AK |
3207 | default: |
3208 | return 0; | |
3209 | } | |
3210 | return 1; | |
3211 | } | |
ab96de7e | 3212 | |
ab96de7e | 3213 | |
4fe6dea8 | 3214 | /* Evaluates constraint strings described by the regular expression |
3e4be43f | 3215 | ([A|B|Z](Q|R|S|T))|Y and returns 1 if OP is a valid operand for |
4fe6dea8 AK |
3216 | the constraint given in STR, or 0 else. */ |
3217 | ||
3218 | int | |
3219 | s390_mem_constraint (const char *str, rtx op) | |
3220 | { | |
3221 | char c = str[0]; | |
3222 | ||
3223 | switch (c) | |
3224 | { | |
3225 | case 'A': | |
3226 | /* Check for offsettable variants of memory constraints. */ | |
3227 | if (!MEM_P (op) || MEM_VOLATILE_P (op)) | |
ab96de7e | 3228 | return 0; |
4fe6dea8 AK |
3229 | if ((reload_completed || reload_in_progress) |
3230 | ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op)) | |
963fc8d0 | 3231 | return 0; |
4fe6dea8 AK |
3232 | return s390_check_qrst_address (str[1], XEXP (op, 0), true); |
3233 | case 'B': | |
3234 | /* Check for non-literal-pool variants of memory constraints. */ | |
3235 | if (!MEM_P (op)) | |
ab96de7e | 3236 | return 0; |
4fe6dea8 AK |
3237 | return s390_check_qrst_address (str[1], XEXP (op, 0), false); |
3238 | case 'Q': | |
3239 | case 'R': | |
3240 | case 'S': | |
3241 | case 'T': | |
3242 | if (GET_CODE (op) != MEM) | |
3243 | return 0; | |
3244 | return s390_check_qrst_address (c, XEXP (op, 0), true); | |
ab96de7e | 3245 | case 'Y': |
d98ad410 UW |
3246 | /* Simply check for the basic form of a shift count. Reload will |
3247 | take care of making sure we have a proper base register. */ | |
dd95128b | 3248 | if (!s390_decompose_addrstyle_without_index (op, NULL, NULL)) |
d98ad410 UW |
3249 | return 0; |
3250 | break; | |
4fe6dea8 AK |
3251 | case 'Z': |
3252 | return s390_check_qrst_address (str[1], op, true); | |
ab96de7e AS |
3253 | default: |
3254 | return 0; | |
3255 | } | |
ab96de7e AS |
3256 | return 1; |
3257 | } | |
3258 | ||
cd8dc1f9 | 3259 | |
cd8dc1f9 WG |
3260 | /* Evaluates constraint strings starting with letter O. Input |
3261 | parameter C is the second letter following the "O" in the constraint | |
3262 | string. Returns 1 if VALUE meets the respective constraint and 0 | |
3263 | otherwise. */ | |
ab96de7e | 3264 | |
d096725d | 3265 | int |
cd8dc1f9 | 3266 | s390_O_constraint_str (const char c, HOST_WIDE_INT value) |
d096725d | 3267 | { |
cd8dc1f9 WG |
3268 | if (!TARGET_EXTIMM) |
3269 | return 0; | |
d096725d | 3270 | |
cd8dc1f9 | 3271 | switch (c) |
d096725d | 3272 | { |
cd8dc1f9 WG |
3273 | case 's': |
3274 | return trunc_int_for_mode (value, SImode) == value; | |
3275 | ||
3276 | case 'p': | |
3277 | return value == 0 | |
3278 | || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1; | |
3279 | ||
3280 | case 'n': | |
ee3f3449 | 3281 | return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1; |
cd8dc1f9 | 3282 | |
d096725d | 3283 | default: |
cd8dc1f9 | 3284 | gcc_unreachable (); |
d096725d AS |
3285 | } |
3286 | } | |
3287 | ||
cd8dc1f9 WG |
3288 | |
3289 | /* Evaluates constraint strings starting with letter N. Parameter STR | |
3290 | contains the letters following letter "N" in the constraint string. | |
3291 | Returns true if VALUE matches the constraint. */ | |
d096725d | 3292 | |
ab96de7e | 3293 | int |
cd8dc1f9 | 3294 | s390_N_constraint_str (const char *str, HOST_WIDE_INT value) |
ab96de7e | 3295 | { |
ef4bddc2 | 3296 | machine_mode mode, part_mode; |
ab96de7e AS |
3297 | int def; |
3298 | int part, part_goal; | |
3299 | ||
ab96de7e | 3300 | |
cd8dc1f9 WG |
3301 | if (str[0] == 'x') |
3302 | part_goal = -1; | |
3303 | else | |
3304 | part_goal = str[0] - '0'; | |
ab96de7e | 3305 | |
cd8dc1f9 WG |
3306 | switch (str[1]) |
3307 | { | |
3308 | case 'Q': | |
3309 | part_mode = QImode; | |
ab96de7e | 3310 | break; |
cd8dc1f9 WG |
3311 | case 'H': |
3312 | part_mode = HImode; | |
ec24698e | 3313 | break; |
cd8dc1f9 WG |
3314 | case 'S': |
3315 | part_mode = SImode; | |
3316 | break; | |
3317 | default: | |
3318 | return 0; | |
3319 | } | |
ec24698e | 3320 | |
cd8dc1f9 WG |
3321 | switch (str[2]) |
3322 | { | |
3323 | case 'H': | |
3324 | mode = HImode; | |
3325 | break; | |
3326 | case 'S': | |
3327 | mode = SImode; | |
3328 | break; | |
3329 | case 'D': | |
3330 | mode = DImode; | |
3331 | break; | |
3332 | default: | |
3333 | return 0; | |
3334 | } | |
11598938 | 3335 | |
cd8dc1f9 WG |
3336 | switch (str[3]) |
3337 | { | |
3338 | case '0': | |
3339 | def = 0; | |
3340 | break; | |
3341 | case 'F': | |
3342 | def = -1; | |
3343 | break; | |
ab96de7e AS |
3344 | default: |
3345 | return 0; | |
3346 | } | |
3347 | ||
cd8dc1f9 WG |
3348 | if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode)) |
3349 | return 0; | |
3350 | ||
3351 | part = s390_single_part (GEN_INT (value), mode, part_mode, def); | |
3352 | if (part < 0) | |
3353 | return 0; | |
3354 | if (part_goal != -1 && part_goal != part) | |
3355 | return 0; | |
3356 | ||
ab96de7e AS |
3357 | return 1; |
3358 | } | |
3359 | ||
cd8dc1f9 WG |
3360 | |
3361 | /* Returns true if the input parameter VALUE is a float zero. */ | |
3362 | ||
3363 | int | |
3364 | s390_float_const_zero_p (rtx value) | |
3365 | { | |
3366 | return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT | |
3367 | && value == CONST0_RTX (GET_MODE (value))); | |
3368 | } | |
3369 | ||
ccaed3ba AS |
3370 | /* Implement TARGET_REGISTER_MOVE_COST. */ |
3371 | ||
3372 | static int | |
f954fb25 | 3373 | s390_register_move_cost (machine_mode mode, |
ccaed3ba AS |
3374 | reg_class_t from, reg_class_t to) |
3375 | { | |
f954fb25 AK |
3376 | /* On s390, copy between fprs and gprs is expensive. */ |
3377 | ||
3378 | /* It becomes somewhat faster having ldgr/lgdr. */ | |
3379 | if (TARGET_Z10 && GET_MODE_SIZE (mode) == 8) | |
3380 | { | |
3381 | /* ldgr is single cycle. */ | |
3382 | if (reg_classes_intersect_p (from, GENERAL_REGS) | |
3383 | && reg_classes_intersect_p (to, FP_REGS)) | |
3384 | return 1; | |
3385 | /* lgdr needs 3 cycles. */ | |
3386 | if (reg_classes_intersect_p (to, GENERAL_REGS) | |
3387 | && reg_classes_intersect_p (from, FP_REGS)) | |
3388 | return 3; | |
3389 | } | |
3390 | ||
3391 | /* Otherwise copying is done via memory. */ | |
3392 | if ((reg_classes_intersect_p (from, GENERAL_REGS) | |
3393 | && reg_classes_intersect_p (to, FP_REGS)) | |
3394 | || (reg_classes_intersect_p (from, FP_REGS) | |
3395 | && reg_classes_intersect_p (to, GENERAL_REGS))) | |
ccaed3ba AS |
3396 | return 10; |
3397 | ||
3398 | return 1; | |
3399 | } | |
3400 | ||
3401 | /* Implement TARGET_MEMORY_MOVE_COST. */ | |
3402 | ||
3403 | static int | |
ef4bddc2 | 3404 | s390_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED, |
ccaed3ba AS |
3405 | reg_class_t rclass ATTRIBUTE_UNUSED, |
3406 | bool in ATTRIBUTE_UNUSED) | |
3407 | { | |
fb1a3f8f | 3408 | return 2; |
ccaed3ba | 3409 | } |
cd8dc1f9 | 3410 | |
ab96de7e AS |
3411 | /* Compute a (partial) cost for rtx X. Return true if the complete |
3412 | cost has been computed, and false if subexpressions should be | |
2c2156a7 DV |
3413 | scanned. In either case, *TOTAL contains the cost result. The |
3414 | initial value of *TOTAL is the default value computed by | |
3415 | rtx_cost. It may be left unmodified. OUTER_CODE contains the | |
3416 | code of the superexpression of x. */ | |
ab96de7e AS |
3417 | |
3418 | static bool | |
e548c9df AM |
3419 | s390_rtx_costs (rtx x, machine_mode mode, int outer_code, |
3420 | int opno ATTRIBUTE_UNUSED, | |
68f932c4 | 3421 | int *total, bool speed ATTRIBUTE_UNUSED) |
3c50106f | 3422 | { |
e548c9df | 3423 | int code = GET_CODE (x); |
3c50106f RH |
3424 | switch (code) |
3425 | { | |
3426 | case CONST: | |
3c50106f | 3427 | case CONST_INT: |
3c50106f RH |
3428 | case LABEL_REF: |
3429 | case SYMBOL_REF: | |
3430 | case CONST_DOUBLE: | |
089b05b1 | 3431 | case CONST_WIDE_INT: |
6fa5b390 | 3432 | case MEM: |
3c50106f RH |
3433 | *total = 0; |
3434 | return true; | |
3435 | ||
e5309d95 AK |
3436 | case SET: |
3437 | { | |
3438 | /* Without this a conditional move instruction would be | |
3439 | accounted as 3 * COSTS_N_INSNS (set, if_then_else, | |
3440 | comparison operator). That's a bit pessimistic. */ | |
3441 | ||
3442 | if (!TARGET_Z196 || GET_CODE (SET_SRC (x)) != IF_THEN_ELSE) | |
3443 | return false; | |
3444 | ||
3445 | rtx cond = XEXP (SET_SRC (x), 0); | |
3446 | ||
3447 | if (!CC_REG_P (XEXP (cond, 0)) || !CONST_INT_P (XEXP (cond, 1))) | |
3448 | return false; | |
3449 | ||
3450 | /* It is going to be a load/store on condition. Make it | |
3451 | slightly more expensive than a normal load. */ | |
3452 | *total = COSTS_N_INSNS (1) + 1; | |
3453 | ||
3454 | rtx dst = SET_DEST (x); | |
3455 | rtx then = XEXP (SET_SRC (x), 1); | |
3456 | rtx els = XEXP (SET_SRC (x), 2); | |
3457 | ||
3458 | /* It is a real IF-THEN-ELSE. An additional move will be | |
3459 | needed to implement that. */ | |
3460 | if (reload_completed | |
3461 | && !rtx_equal_p (dst, then) | |
3462 | && !rtx_equal_p (dst, els)) | |
3463 | *total += COSTS_N_INSNS (1) / 2; | |
3464 | ||
3465 | /* A minor penalty for constants we cannot directly handle. */ | |
3466 | if ((CONST_INT_P (then) || CONST_INT_P (els)) | |
3467 | && (!TARGET_Z13 || MEM_P (dst) | |
3468 | || (CONST_INT_P (then) && !satisfies_constraint_K (then)) | |
3469 | || (CONST_INT_P (els) && !satisfies_constraint_K (els)))) | |
3470 | *total += COSTS_N_INSNS (1) / 2; | |
3471 | ||
3472 | /* A store on condition can only handle register src operands. */ | |
3473 | if (MEM_P (dst) && (!REG_P (then) || !REG_P (els))) | |
3474 | *total += COSTS_N_INSNS (1) / 2; | |
3475 | ||
3476 | return true; | |
3477 | } | |
3d44ff99 AK |
3478 | case IOR: |
3479 | /* risbg */ | |
3480 | if (GET_CODE (XEXP (x, 0)) == AND | |
3481 | && GET_CODE (XEXP (x, 1)) == ASHIFT | |
3482 | && REG_P (XEXP (XEXP (x, 0), 0)) | |
3483 | && REG_P (XEXP (XEXP (x, 1), 0)) | |
3484 | && CONST_INT_P (XEXP (XEXP (x, 0), 1)) | |
3485 | && CONST_INT_P (XEXP (XEXP (x, 1), 1)) | |
3486 | && (UINTVAL (XEXP (XEXP (x, 0), 1)) == | |
406fde6e | 3487 | (HOST_WIDE_INT_1U << UINTVAL (XEXP (XEXP (x, 1), 1))) - 1)) |
3d44ff99 AK |
3488 | { |
3489 | *total = COSTS_N_INSNS (2); | |
3490 | return true; | |
3491 | } | |
9ec98860 AK |
3492 | |
3493 | /* ~AND on a 128 bit mode. This can be done using a vector | |
3494 | instruction. */ | |
3495 | if (TARGET_VXE | |
3496 | && GET_CODE (XEXP (x, 0)) == NOT | |
3497 | && GET_CODE (XEXP (x, 1)) == NOT | |
3498 | && REG_P (XEXP (XEXP (x, 0), 0)) | |
3499 | && REG_P (XEXP (XEXP (x, 1), 0)) | |
3500 | && GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0), 0))) == 16 | |
3501 | && s390_hard_regno_mode_ok (VR0_REGNUM, | |
3502 | GET_MODE (XEXP (XEXP (x, 0), 0)))) | |
3503 | { | |
3504 | *total = COSTS_N_INSNS (1); | |
3505 | return true; | |
3506 | } | |
1d92cba9 | 3507 | /* fallthrough */ |
3c50106f RH |
3508 | case ASHIFT: |
3509 | case ASHIFTRT: | |
3510 | case LSHIFTRT: | |
017e0eb9 MD |
3511 | case ROTATE: |
3512 | case ROTATERT: | |
3c50106f | 3513 | case AND: |
3c50106f | 3514 | case XOR: |
3c50106f RH |
3515 | case NEG: |
3516 | case NOT: | |
3517 | *total = COSTS_N_INSNS (1); | |
017e0eb9 | 3518 | return false; |
3c50106f | 3519 | |
2742a1ed MD |
3520 | case PLUS: |
3521 | case MINUS: | |
2742a1ed MD |
3522 | *total = COSTS_N_INSNS (1); |
3523 | return false; | |
3524 | ||
f4aa3848 | 3525 | case MULT: |
e548c9df | 3526 | switch (mode) |
017e0eb9 | 3527 | { |
4e10a5a7 | 3528 | case E_SImode: |
2742a1ed | 3529 | { |
017e0eb9 MD |
3530 | rtx left = XEXP (x, 0); |
3531 | rtx right = XEXP (x, 1); | |
3532 | if (GET_CODE (right) == CONST_INT | |
b5c67a49 | 3533 | && CONST_OK_FOR_K (INTVAL (right))) |
017e0eb9 MD |
3534 | *total = s390_cost->mhi; |
3535 | else if (GET_CODE (left) == SIGN_EXTEND) | |
3536 | *total = s390_cost->mh; | |
3537 | else | |
3538 | *total = s390_cost->ms; /* msr, ms, msy */ | |
3539 | break; | |
3540 | } | |
4e10a5a7 | 3541 | case E_DImode: |
017e0eb9 MD |
3542 | { |
3543 | rtx left = XEXP (x, 0); | |
3544 | rtx right = XEXP (x, 1); | |
9602b6a1 | 3545 | if (TARGET_ZARCH) |
017e0eb9 MD |
3546 | { |
3547 | if (GET_CODE (right) == CONST_INT | |
b5c67a49 | 3548 | && CONST_OK_FOR_K (INTVAL (right))) |
017e0eb9 MD |
3549 | *total = s390_cost->mghi; |
3550 | else if (GET_CODE (left) == SIGN_EXTEND) | |
3551 | *total = s390_cost->msgf; | |
3552 | else | |
3553 | *total = s390_cost->msg; /* msgr, msg */ | |
3554 | } | |
3555 | else /* TARGET_31BIT */ | |
3556 | { | |
3557 | if (GET_CODE (left) == SIGN_EXTEND | |
3558 | && GET_CODE (right) == SIGN_EXTEND) | |
3559 | /* mulsidi case: mr, m */ | |
3560 | *total = s390_cost->m; | |
2742a1ed MD |
3561 | else if (GET_CODE (left) == ZERO_EXTEND |
3562 | && GET_CODE (right) == ZERO_EXTEND | |
3563 | && TARGET_CPU_ZARCH) | |
3564 | /* umulsidi case: ml, mlr */ | |
3565 | *total = s390_cost->ml; | |
017e0eb9 MD |
3566 | else |
3567 | /* Complex calculation is required. */ | |
3568 | *total = COSTS_N_INSNS (40); | |
3569 | } | |
3570 | break; | |
3571 | } | |
4e10a5a7 RS |
3572 | case E_SFmode: |
3573 | case E_DFmode: | |
017e0eb9 MD |
3574 | *total = s390_cost->mult_df; |
3575 | break; | |
4e10a5a7 | 3576 | case E_TFmode: |
f61a2c7d AK |
3577 | *total = s390_cost->mxbr; |
3578 | break; | |
017e0eb9 MD |
3579 | default: |
3580 | return false; | |
3581 | } | |
3582 | return false; | |
3c50106f | 3583 | |
d7ecb504 | 3584 | case FMA: |
e548c9df | 3585 | switch (mode) |
d7ecb504 | 3586 | { |
4e10a5a7 | 3587 | case E_DFmode: |
d7ecb504 RH |
3588 | *total = s390_cost->madbr; |
3589 | break; | |
4e10a5a7 | 3590 | case E_SFmode: |
d7ecb504 RH |
3591 | *total = s390_cost->maebr; |
3592 | break; | |
3593 | default: | |
3594 | return false; | |
3595 | } | |
3596 | /* Negate in the third argument is free: FMSUB. */ | |
3597 | if (GET_CODE (XEXP (x, 2)) == NEG) | |
3598 | { | |
e548c9df AM |
3599 | *total += (rtx_cost (XEXP (x, 0), mode, FMA, 0, speed) |
3600 | + rtx_cost (XEXP (x, 1), mode, FMA, 1, speed) | |
3601 | + rtx_cost (XEXP (XEXP (x, 2), 0), mode, FMA, 2, speed)); | |
d7ecb504 RH |
3602 | return true; |
3603 | } | |
3604 | return false; | |
3605 | ||
6fa5b390 MD |
3606 | case UDIV: |
3607 | case UMOD: | |
e548c9df | 3608 | if (mode == TImode) /* 128 bit division */ |
6fa5b390 | 3609 | *total = s390_cost->dlgr; |
e548c9df | 3610 | else if (mode == DImode) |
6fa5b390 MD |
3611 | { |
3612 | rtx right = XEXP (x, 1); | |
3613 | if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */ | |
3614 | *total = s390_cost->dlr; | |
3615 | else /* 64 by 64 bit division */ | |
3616 | *total = s390_cost->dlgr; | |
3617 | } | |
e548c9df | 3618 | else if (mode == SImode) /* 32 bit division */ |
6fa5b390 MD |
3619 | *total = s390_cost->dlr; |
3620 | return false; | |
3621 | ||
3c50106f | 3622 | case DIV: |
6fa5b390 | 3623 | case MOD: |
e548c9df | 3624 | if (mode == DImode) |
6fa5b390 MD |
3625 | { |
3626 | rtx right = XEXP (x, 1); | |
3627 | if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */ | |
9602b6a1 | 3628 | if (TARGET_ZARCH) |
6fa5b390 MD |
3629 | *total = s390_cost->dsgfr; |
3630 | else | |
3631 | *total = s390_cost->dr; | |
3632 | else /* 64 by 64 bit division */ | |
3633 | *total = s390_cost->dsgr; | |
3634 | } | |
e548c9df | 3635 | else if (mode == SImode) /* 32 bit division */ |
6fa5b390 | 3636 | *total = s390_cost->dlr; |
e548c9df | 3637 | else if (mode == SFmode) |
98fd0d70 | 3638 | { |
142cd70f | 3639 | *total = s390_cost->debr; |
98fd0d70 | 3640 | } |
e548c9df | 3641 | else if (mode == DFmode) |
98fd0d70 | 3642 | { |
142cd70f | 3643 | *total = s390_cost->ddbr; |
98fd0d70 | 3644 | } |
e548c9df | 3645 | else if (mode == TFmode) |
f61a2c7d | 3646 | { |
142cd70f | 3647 | *total = s390_cost->dxbr; |
f61a2c7d | 3648 | } |
017e0eb9 MD |
3649 | return false; |
3650 | ||
2742a1ed | 3651 | case SQRT: |
e548c9df | 3652 | if (mode == SFmode) |
2742a1ed | 3653 | *total = s390_cost->sqebr; |
e548c9df | 3654 | else if (mode == DFmode) |
2742a1ed | 3655 | *total = s390_cost->sqdbr; |
f61a2c7d AK |
3656 | else /* TFmode */ |
3657 | *total = s390_cost->sqxbr; | |
2742a1ed MD |
3658 | return false; |
3659 | ||
017e0eb9 | 3660 | case SIGN_EXTEND: |
2742a1ed | 3661 | case ZERO_EXTEND: |
6fa5b390 MD |
3662 | if (outer_code == MULT || outer_code == DIV || outer_code == MOD |
3663 | || outer_code == PLUS || outer_code == MINUS | |
3664 | || outer_code == COMPARE) | |
017e0eb9 MD |
3665 | *total = 0; |
3666 | return false; | |
3c50106f | 3667 | |
6fa5b390 MD |
3668 | case COMPARE: |
3669 | *total = COSTS_N_INSNS (1); | |
3670 | if (GET_CODE (XEXP (x, 0)) == AND | |
3671 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
3672 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) | |
3673 | { | |
3674 | rtx op0 = XEXP (XEXP (x, 0), 0); | |
3675 | rtx op1 = XEXP (XEXP (x, 0), 1); | |
3676 | rtx op2 = XEXP (x, 1); | |
3677 | ||
3678 | if (memory_operand (op0, GET_MODE (op0)) | |
3679 | && s390_tm_ccmode (op1, op2, 0) != VOIDmode) | |
3680 | return true; | |
3681 | if (register_operand (op0, GET_MODE (op0)) | |
3682 | && s390_tm_ccmode (op1, op2, 1) != VOIDmode) | |
3683 | return true; | |
3684 | } | |
3685 | return false; | |
3686 | ||
3c50106f RH |
3687 | default: |
3688 | return false; | |
3689 | } | |
3690 | } | |
3691 | ||
dea09b1b UW |
3692 | /* Return the cost of an address rtx ADDR. */ |
3693 | ||
dcefdf67 | 3694 | static int |
ef4bddc2 | 3695 | s390_address_cost (rtx addr, machine_mode mode ATTRIBUTE_UNUSED, |
b413068c OE |
3696 | addr_space_t as ATTRIBUTE_UNUSED, |
3697 | bool speed ATTRIBUTE_UNUSED) | |
dea09b1b UW |
3698 | { |
3699 | struct s390_address ad; | |
3700 | if (!s390_decompose_address (addr, &ad)) | |
3701 | return 1000; | |
3702 | ||
3703 | return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1); | |
3704 | } | |
3705 | ||
7f5fc633 AK |
3706 | /* Implement targetm.vectorize.builtin_vectorization_cost. */ |
3707 | static int | |
3708 | s390_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost, | |
3709 | tree vectype, | |
3710 | int misalign ATTRIBUTE_UNUSED) | |
3711 | { | |
3712 | switch (type_of_cost) | |
3713 | { | |
3714 | case scalar_stmt: | |
3715 | case scalar_load: | |
3716 | case scalar_store: | |
3717 | case vector_stmt: | |
3718 | case vector_load: | |
3719 | case vector_store: | |
3720 | case vec_to_scalar: | |
3721 | case scalar_to_vec: | |
3722 | case cond_branch_not_taken: | |
3723 | case vec_perm: | |
3724 | case vec_promote_demote: | |
3725 | case unaligned_load: | |
3726 | case unaligned_store: | |
3727 | return 1; | |
3728 | ||
3729 | case cond_branch_taken: | |
3730 | return 3; | |
3731 | ||
3732 | case vec_construct: | |
3733 | return TYPE_VECTOR_SUBPARTS (vectype) - 1; | |
3734 | ||
3735 | default: | |
3736 | gcc_unreachable (); | |
3737 | } | |
3738 | } | |
3739 | ||
fd3cd001 UW |
3740 | /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode, |
3741 | otherwise return 0. */ | |
3742 | ||
3743 | int | |
5d81b82b | 3744 | tls_symbolic_operand (rtx op) |
fd3cd001 | 3745 | { |
fd3cd001 UW |
3746 | if (GET_CODE (op) != SYMBOL_REF) |
3747 | return 0; | |
114278e7 | 3748 | return SYMBOL_REF_TLS_MODEL (op); |
fd3cd001 | 3749 | } |
9db1d521 | 3750 | \f |
c5aa1d12 UW |
3751 | /* Split DImode access register reference REG (on 64-bit) into its constituent |
3752 | low and high parts, and store them into LO and HI. Note that gen_lowpart/ | |
3753 | gen_highpart cannot be used as they assume all registers are word-sized, | |
3754 | while our access registers have only half that size. */ | |
3755 | ||
3756 | void | |
3757 | s390_split_access_reg (rtx reg, rtx *lo, rtx *hi) | |
3758 | { | |
3759 | gcc_assert (TARGET_64BIT); | |
3760 | gcc_assert (ACCESS_REG_P (reg)); | |
3761 | gcc_assert (GET_MODE (reg) == DImode); | |
3762 | gcc_assert (!(REGNO (reg) & 1)); | |
3763 | ||
3764 | *lo = gen_rtx_REG (SImode, REGNO (reg) + 1); | |
3765 | *hi = gen_rtx_REG (SImode, REGNO (reg)); | |
3766 | } | |
9db1d521 | 3767 | |
994fe660 | 3768 | /* Return true if OP contains a symbol reference */ |
9db1d521 | 3769 | |
3ed99cc9 | 3770 | bool |
9c808aad | 3771 | symbolic_reference_mentioned_p (rtx op) |
9db1d521 | 3772 | { |
5d81b82b AS |
3773 | const char *fmt; |
3774 | int i; | |
9db1d521 HP |
3775 | |
3776 | if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF) | |
3777 | return 1; | |
3778 | ||
3779 | fmt = GET_RTX_FORMAT (GET_CODE (op)); | |
3780 | for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--) | |
3781 | { | |
3782 | if (fmt[i] == 'E') | |
3783 | { | |
5d81b82b | 3784 | int j; |
9db1d521 HP |
3785 | |
3786 | for (j = XVECLEN (op, i) - 1; j >= 0; j--) | |
3787 | if (symbolic_reference_mentioned_p (XVECEXP (op, i, j))) | |
3788 | return 1; | |
3789 | } | |
3790 | ||
3791 | else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i))) | |
3792 | return 1; | |
3793 | } | |
3794 | ||
3795 | return 0; | |
3796 | } | |
3797 | ||
fd3cd001 UW |
3798 | /* Return true if OP contains a reference to a thread-local symbol. */ |
3799 | ||
3ed99cc9 | 3800 | bool |
9c808aad | 3801 | tls_symbolic_reference_mentioned_p (rtx op) |
fd3cd001 | 3802 | { |
5d81b82b AS |
3803 | const char *fmt; |
3804 | int i; | |
fd3cd001 UW |
3805 | |
3806 | if (GET_CODE (op) == SYMBOL_REF) | |
3807 | return tls_symbolic_operand (op); | |
3808 | ||
3809 | fmt = GET_RTX_FORMAT (GET_CODE (op)); | |
3810 | for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--) | |
3811 | { | |
3812 | if (fmt[i] == 'E') | |
3813 | { | |
5d81b82b | 3814 | int j; |
fd3cd001 UW |
3815 | |
3816 | for (j = XVECLEN (op, i) - 1; j >= 0; j--) | |
3817 | if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j))) | |
3ed99cc9 | 3818 | return true; |
fd3cd001 UW |
3819 | } |
3820 | ||
3821 | else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i))) | |
3ed99cc9 | 3822 | return true; |
fd3cd001 UW |
3823 | } |
3824 | ||
3ed99cc9 | 3825 | return false; |
fd3cd001 UW |
3826 | } |
3827 | ||
9db1d521 | 3828 | |
c7453384 EC |
3829 | /* Return true if OP is a legitimate general operand when |
3830 | generating PIC code. It is given that flag_pic is on | |
089b05b1 | 3831 | and that OP satisfies CONSTANT_P. */ |
994fe660 | 3832 | |
9db1d521 | 3833 | int |
5d81b82b | 3834 | legitimate_pic_operand_p (rtx op) |
9db1d521 | 3835 | { |
4023fb28 | 3836 | /* Accept all non-symbolic constants. */ |
9db1d521 HP |
3837 | if (!SYMBOLIC_CONST (op)) |
3838 | return 1; | |
3839 | ||
c7453384 | 3840 | /* Reject everything else; must be handled |
fd3cd001 | 3841 | via emit_symbolic_move. */ |
9db1d521 HP |
3842 | return 0; |
3843 | } | |
3844 | ||
994fe660 | 3845 | /* Returns true if the constant value OP is a legitimate general operand. |
089b05b1 | 3846 | It is given that OP satisfies CONSTANT_P. */ |
994fe660 | 3847 | |
1a627b35 | 3848 | static bool |
ef4bddc2 | 3849 | s390_legitimate_constant_p (machine_mode mode, rtx op) |
9db1d521 | 3850 | { |
0600d22c | 3851 | if (TARGET_VX && VECTOR_MODE_P (mode) && GET_CODE (op) == CONST_VECTOR) |
085261c8 AK |
3852 | { |
3853 | if (GET_MODE_SIZE (mode) != 16) | |
3854 | return 0; | |
3855 | ||
b0057efd AK |
3856 | if (!satisfies_constraint_j00 (op) |
3857 | && !satisfies_constraint_jm1 (op) | |
3858 | && !satisfies_constraint_jKK (op) | |
3859 | && !satisfies_constraint_jxx (op) | |
3860 | && !satisfies_constraint_jyy (op)) | |
085261c8 AK |
3861 | return 0; |
3862 | } | |
3863 | ||
4023fb28 | 3864 | /* Accept all non-symbolic constants. */ |
9db1d521 HP |
3865 | if (!SYMBOLIC_CONST (op)) |
3866 | return 1; | |
3867 | ||
fd3cd001 | 3868 | /* Accept immediate LARL operands. */ |
1a627b35 | 3869 | if (TARGET_CPU_ZARCH && larl_operand (op, mode)) |
fd3cd001 UW |
3870 | return 1; |
3871 | ||
3872 | /* Thread-local symbols are never legal constants. This is | |
3873 | so that emit_call knows that computing such addresses | |
3874 | might require a function call. */ | |
3875 | if (TLS_SYMBOLIC_CONST (op)) | |
3876 | return 0; | |
3877 | ||
9db1d521 HP |
3878 | /* In the PIC case, symbolic constants must *not* be |
3879 | forced into the literal pool. We accept them here, | |
fd3cd001 | 3880 | so that they will be handled by emit_symbolic_move. */ |
9db1d521 HP |
3881 | if (flag_pic) |
3882 | return 1; | |
3883 | ||
9db1d521 HP |
3884 | /* All remaining non-PIC symbolic constants are |
3885 | forced into the literal pool. */ | |
3886 | return 0; | |
3887 | } | |
3888 | ||
fd3cd001 UW |
3889 | /* Determine if it's legal to put X into the constant pool. This |
3890 | is not possible if X contains the address of a symbol that is | |
3891 | not constant (TLS) or not known at final link time (PIC). */ | |
3892 | ||
3893 | static bool | |
ef4bddc2 | 3894 | s390_cannot_force_const_mem (machine_mode mode, rtx x) |
fd3cd001 UW |
3895 | { |
3896 | switch (GET_CODE (x)) | |
3897 | { | |
3898 | case CONST_INT: | |
3899 | case CONST_DOUBLE: | |
089b05b1 | 3900 | case CONST_WIDE_INT: |
085261c8 | 3901 | case CONST_VECTOR: |
fd3cd001 UW |
3902 | /* Accept all non-symbolic constants. */ |
3903 | return false; | |
3904 | ||
3905 | case LABEL_REF: | |
3906 | /* Labels are OK iff we are non-PIC. */ | |
3907 | return flag_pic != 0; | |
3908 | ||
3909 | case SYMBOL_REF: | |
3910 | /* 'Naked' TLS symbol references are never OK, | |
3911 | non-TLS symbols are OK iff we are non-PIC. */ | |
3912 | if (tls_symbolic_operand (x)) | |
3913 | return true; | |
3914 | else | |
3915 | return flag_pic != 0; | |
3916 | ||
3917 | case CONST: | |
fbbf66e7 | 3918 | return s390_cannot_force_const_mem (mode, XEXP (x, 0)); |
fd3cd001 UW |
3919 | case PLUS: |
3920 | case MINUS: | |
fbbf66e7 RS |
3921 | return s390_cannot_force_const_mem (mode, XEXP (x, 0)) |
3922 | || s390_cannot_force_const_mem (mode, XEXP (x, 1)); | |
fd3cd001 UW |
3923 | |
3924 | case UNSPEC: | |
3925 | switch (XINT (x, 1)) | |
3926 | { | |
3927 | /* Only lt-relative or GOT-relative UNSPECs are OK. */ | |
fd7643fb UW |
3928 | case UNSPEC_LTREL_OFFSET: |
3929 | case UNSPEC_GOT: | |
3930 | case UNSPEC_GOTOFF: | |
3931 | case UNSPEC_PLTOFF: | |
fd3cd001 UW |
3932 | case UNSPEC_TLSGD: |
3933 | case UNSPEC_TLSLDM: | |
3934 | case UNSPEC_NTPOFF: | |
3935 | case UNSPEC_DTPOFF: | |
3936 | case UNSPEC_GOTNTPOFF: | |
3937 | case UNSPEC_INDNTPOFF: | |
3938 | return false; | |
3939 | ||
9bb86f41 UW |
3940 | /* If the literal pool shares the code section, be put |
3941 | execute template placeholders into the pool as well. */ | |
3942 | case UNSPEC_INSN: | |
3943 | return TARGET_CPU_ZARCH; | |
3944 | ||
fd3cd001 UW |
3945 | default: |
3946 | return true; | |
3947 | } | |
3948 | break; | |
3949 | ||
3950 | default: | |
8d933e31 | 3951 | gcc_unreachable (); |
fd3cd001 UW |
3952 | } |
3953 | } | |
3954 | ||
4023fb28 | 3955 | /* Returns true if the constant value OP is a legitimate general |
c7453384 | 3956 | operand during and after reload. The difference to |
4023fb28 UW |
3957 | legitimate_constant_p is that this function will not accept |
3958 | a constant that would need to be forced to the literal pool | |
65b1d8ea AK |
3959 | before it can be used as operand. |
3960 | This function accepts all constants which can be loaded directly | |
3961 | into a GPR. */ | |
4023fb28 | 3962 | |
3ed99cc9 | 3963 | bool |
5d81b82b | 3964 | legitimate_reload_constant_p (rtx op) |
4023fb28 | 3965 | { |
d3632d41 | 3966 | /* Accept la(y) operands. */ |
c7453384 | 3967 | if (GET_CODE (op) == CONST_INT |
d3632d41 | 3968 | && DISP_IN_RANGE (INTVAL (op))) |
3ed99cc9 | 3969 | return true; |
d3632d41 | 3970 | |
ec24698e | 3971 | /* Accept l(g)hi/l(g)fi operands. */ |
4023fb28 | 3972 | if (GET_CODE (op) == CONST_INT |
ec24698e | 3973 | && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op)))) |
3ed99cc9 | 3974 | return true; |
4023fb28 UW |
3975 | |
3976 | /* Accept lliXX operands. */ | |
9e8327e3 | 3977 | if (TARGET_ZARCH |
11598938 UW |
3978 | && GET_CODE (op) == CONST_INT |
3979 | && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op) | |
3980 | && s390_single_part (op, word_mode, HImode, 0) >= 0) | |
3ed99cc9 | 3981 | return true; |
4023fb28 | 3982 | |
ec24698e UW |
3983 | if (TARGET_EXTIMM |
3984 | && GET_CODE (op) == CONST_INT | |
3985 | && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op) | |
3986 | && s390_single_part (op, word_mode, SImode, 0) >= 0) | |
3987 | return true; | |
3988 | ||
4023fb28 | 3989 | /* Accept larl operands. */ |
9e8327e3 | 3990 | if (TARGET_CPU_ZARCH |
4023fb28 | 3991 | && larl_operand (op, VOIDmode)) |
3ed99cc9 | 3992 | return true; |
4023fb28 | 3993 | |
45e5214c UW |
3994 | /* Accept floating-point zero operands that fit into a single GPR. */ |
3995 | if (GET_CODE (op) == CONST_DOUBLE | |
3996 | && s390_float_const_zero_p (op) | |
3997 | && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD) | |
3998 | return true; | |
3999 | ||
11598938 | 4000 | /* Accept double-word operands that can be split. */ |
089b05b1 DV |
4001 | if (GET_CODE (op) == CONST_WIDE_INT |
4002 | || (GET_CODE (op) == CONST_INT | |
4003 | && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))) | |
11598938 | 4004 | { |
ef4bddc2 | 4005 | machine_mode dword_mode = word_mode == SImode ? DImode : TImode; |
11598938 UW |
4006 | rtx hi = operand_subword (op, 0, 0, dword_mode); |
4007 | rtx lo = operand_subword (op, 1, 0, dword_mode); | |
4008 | return legitimate_reload_constant_p (hi) | |
4009 | && legitimate_reload_constant_p (lo); | |
4010 | } | |
4011 | ||
4023fb28 | 4012 | /* Everything else cannot be handled without reload. */ |
3ed99cc9 | 4013 | return false; |
4023fb28 UW |
4014 | } |
4015 | ||
65b1d8ea AK |
4016 | /* Returns true if the constant value OP is a legitimate fp operand |
4017 | during and after reload. | |
4018 | This function accepts all constants which can be loaded directly | |
4019 | into an FPR. */ | |
4020 | ||
4021 | static bool | |
4022 | legitimate_reload_fp_constant_p (rtx op) | |
4023 | { | |
4024 | /* Accept floating-point zero operands if the load zero instruction | |
22ac2c2f AK |
4025 | can be used. Prior to z196 the load fp zero instruction caused a |
4026 | performance penalty if the result is used as BFP number. */ | |
65b1d8ea AK |
4027 | if (TARGET_Z196 |
4028 | && GET_CODE (op) == CONST_DOUBLE | |
4029 | && s390_float_const_zero_p (op)) | |
4030 | return true; | |
4031 | ||
4032 | return false; | |
4033 | } | |
4034 | ||
085261c8 AK |
4035 | /* Returns true if the constant value OP is a legitimate vector operand |
4036 | during and after reload. | |
4037 | This function accepts all constants which can be loaded directly | |
4038 | into an VR. */ | |
4039 | ||
4040 | static bool | |
4041 | legitimate_reload_vector_constant_p (rtx op) | |
4042 | { | |
085261c8 | 4043 | if (TARGET_VX && GET_MODE_SIZE (GET_MODE (op)) == 16 |
b0057efd AK |
4044 | && (satisfies_constraint_j00 (op) |
4045 | || satisfies_constraint_jm1 (op) | |
4046 | || satisfies_constraint_jKK (op) | |
4047 | || satisfies_constraint_jxx (op) | |
4048 | || satisfies_constraint_jyy (op))) | |
085261c8 AK |
4049 | return true; |
4050 | ||
4051 | return false; | |
4052 | } | |
4053 | ||
0a2aaacc | 4054 | /* Given an rtx OP being reloaded into a reg required to be in class RCLASS, |
4023fb28 UW |
4055 | return the class of reg to actually use. */ |
4056 | ||
5df97412 AS |
4057 | static reg_class_t |
4058 | s390_preferred_reload_class (rtx op, reg_class_t rclass) | |
4023fb28 | 4059 | { |
4023fb28 UW |
4060 | switch (GET_CODE (op)) |
4061 | { | |
45e5214c UW |
4062 | /* Constants we cannot reload into general registers |
4063 | must be forced into the literal pool. */ | |
085261c8 | 4064 | case CONST_VECTOR: |
4023fb28 UW |
4065 | case CONST_DOUBLE: |
4066 | case CONST_INT: | |
089b05b1 | 4067 | case CONST_WIDE_INT: |
45e5214c UW |
4068 | if (reg_class_subset_p (GENERAL_REGS, rclass) |
4069 | && legitimate_reload_constant_p (op)) | |
4070 | return GENERAL_REGS; | |
4071 | else if (reg_class_subset_p (ADDR_REGS, rclass) | |
4072 | && legitimate_reload_constant_p (op)) | |
4073 | return ADDR_REGS; | |
65b1d8ea AK |
4074 | else if (reg_class_subset_p (FP_REGS, rclass) |
4075 | && legitimate_reload_fp_constant_p (op)) | |
4076 | return FP_REGS; | |
085261c8 AK |
4077 | else if (reg_class_subset_p (VEC_REGS, rclass) |
4078 | && legitimate_reload_vector_constant_p (op)) | |
4079 | return VEC_REGS; | |
4080 | ||
65b1d8ea | 4081 | return NO_REGS; |
4023fb28 UW |
4082 | |
4083 | /* If a symbolic constant or a PLUS is reloaded, | |
14b3e8ef UW |
4084 | it is most likely being used as an address, so |
4085 | prefer ADDR_REGS. If 'class' is not a superset | |
4086 | of ADDR_REGS, e.g. FP_REGS, reject this reload. */ | |
1abcd5eb | 4087 | case CONST: |
cb4b6d17 AK |
4088 | /* Symrefs cannot be pushed into the literal pool with -fPIC |
4089 | so we *MUST NOT* return NO_REGS for these cases | |
4090 | (s390_cannot_force_const_mem will return true). | |
4091 | ||
4092 | On the other hand we MUST return NO_REGS for symrefs with | |
4093 | invalid addend which might have been pushed to the literal | |
4094 | pool (no -fPIC). Usually we would expect them to be | |
4095 | handled via secondary reload but this does not happen if | |
4096 | they are used as literal pool slot replacement in reload | |
4097 | inheritance (see emit_input_reload_insns). */ | |
1abcd5eb AK |
4098 | if (TARGET_CPU_ZARCH |
4099 | && GET_CODE (XEXP (op, 0)) == PLUS | |
4100 | && GET_CODE (XEXP (XEXP(op, 0), 0)) == SYMBOL_REF | |
4101 | && GET_CODE (XEXP (XEXP(op, 0), 1)) == CONST_INT) | |
4102 | { | |
cb4b6d17 | 4103 | if (flag_pic && reg_class_subset_p (ADDR_REGS, rclass)) |
1abcd5eb AK |
4104 | return ADDR_REGS; |
4105 | else | |
4106 | return NO_REGS; | |
4107 | } | |
4108 | /* fallthrough */ | |
4023fb28 UW |
4109 | case LABEL_REF: |
4110 | case SYMBOL_REF: | |
212aa74f AK |
4111 | if (!legitimate_reload_constant_p (op)) |
4112 | return NO_REGS; | |
4113 | /* fallthrough */ | |
4114 | case PLUS: | |
4115 | /* load address will be used. */ | |
0a2aaacc | 4116 | if (reg_class_subset_p (ADDR_REGS, rclass)) |
212aa74f | 4117 | return ADDR_REGS; |
14b3e8ef UW |
4118 | else |
4119 | return NO_REGS; | |
4023fb28 UW |
4120 | |
4121 | default: | |
4122 | break; | |
4123 | } | |
4124 | ||
0a2aaacc | 4125 | return rclass; |
4023fb28 | 4126 | } |
9db1d521 | 4127 | |
963fc8d0 AK |
4128 | /* Return true if ADDR is SYMBOL_REF + addend with addend being a |
4129 | multiple of ALIGNMENT and the SYMBOL_REF being naturally | |
4130 | aligned. */ | |
4131 | ||
4132 | bool | |
4133 | s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment) | |
4134 | { | |
4135 | HOST_WIDE_INT addend; | |
4136 | rtx symref; | |
4137 | ||
e63d44c2 RD |
4138 | /* The "required alignment" might be 0 (e.g. for certain structs |
4139 | accessed via BLKmode). Early abort in this case, as well as when | |
4140 | an alignment > 8 is required. */ | |
4141 | if (alignment < 2 || alignment > 8) | |
4142 | return false; | |
4143 | ||
0ff4390d AK |
4144 | if (!s390_loadrelative_operand_p (addr, &symref, &addend)) |
4145 | return false; | |
98412b77 | 4146 | |
0ff4390d | 4147 | if (addend & (alignment - 1)) |
963fc8d0 AK |
4148 | return false; |
4149 | ||
e63d44c2 RD |
4150 | if (GET_CODE (symref) == SYMBOL_REF) |
4151 | { | |
4152 | /* We have load-relative instructions for 2-byte, 4-byte, and | |
4153 | 8-byte alignment so allow only these. */ | |
4154 | switch (alignment) | |
4155 | { | |
4156 | case 8: return !SYMBOL_FLAG_NOTALIGN8_P (symref); | |
4157 | case 4: return !SYMBOL_FLAG_NOTALIGN4_P (symref); | |
4158 | case 2: return !SYMBOL_FLAG_NOTALIGN2_P (symref); | |
4159 | default: return false; | |
4160 | } | |
4161 | } | |
0ff4390d AK |
4162 | |
4163 | if (GET_CODE (symref) == UNSPEC | |
4164 | && alignment <= UNITS_PER_LONG) | |
4165 | return true; | |
4166 | ||
4167 | return false; | |
963fc8d0 AK |
4168 | } |
4169 | ||
4170 | /* ADDR is moved into REG using larl. If ADDR isn't a valid larl | |
4171 | operand SCRATCH is used to reload the even part of the address and | |
4172 | adding one. */ | |
4173 | ||
4174 | void | |
4175 | s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch) | |
4176 | { | |
4177 | HOST_WIDE_INT addend; | |
4178 | rtx symref; | |
4179 | ||
0ff4390d | 4180 | if (!s390_loadrelative_operand_p (addr, &symref, &addend)) |
963fc8d0 AK |
4181 | gcc_unreachable (); |
4182 | ||
4183 | if (!(addend & 1)) | |
4184 | /* Easy case. The addend is even so larl will do fine. */ | |
4185 | emit_move_insn (reg, addr); | |
4186 | else | |
4187 | { | |
4188 | /* We can leave the scratch register untouched if the target | |
4189 | register is a valid base register. */ | |
4190 | if (REGNO (reg) < FIRST_PSEUDO_REGISTER | |
4191 | && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS) | |
4192 | scratch = reg; | |
4193 | ||
4194 | gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER); | |
4195 | gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS); | |
4196 | ||
4197 | if (addend != 1) | |
4198 | emit_move_insn (scratch, | |
4199 | gen_rtx_CONST (Pmode, | |
4200 | gen_rtx_PLUS (Pmode, symref, | |
4201 | GEN_INT (addend - 1)))); | |
4202 | else | |
4203 | emit_move_insn (scratch, symref); | |
4204 | ||
4205 | /* Increment the address using la in order to avoid clobbering cc. */ | |
1abcd5eb | 4206 | s390_load_address (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx)); |
963fc8d0 AK |
4207 | } |
4208 | } | |
4209 | ||
4210 | /* Generate what is necessary to move between REG and MEM using | |
4211 | SCRATCH. The direction is given by TOMEM. */ | |
4212 | ||
4213 | void | |
4214 | s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem) | |
4215 | { | |
4216 | /* Reload might have pulled a constant out of the literal pool. | |
4217 | Force it back in. */ | |
4218 | if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE | |
089b05b1 | 4219 | || GET_CODE (mem) == CONST_WIDE_INT |
085261c8 | 4220 | || GET_CODE (mem) == CONST_VECTOR |
963fc8d0 AK |
4221 | || GET_CODE (mem) == CONST) |
4222 | mem = force_const_mem (GET_MODE (reg), mem); | |
4223 | ||
4224 | gcc_assert (MEM_P (mem)); | |
4225 | ||
4226 | /* For a load from memory we can leave the scratch register | |
4227 | untouched if the target register is a valid base register. */ | |
4228 | if (!tomem | |
4229 | && REGNO (reg) < FIRST_PSEUDO_REGISTER | |
4230 | && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS | |
4231 | && GET_MODE (reg) == GET_MODE (scratch)) | |
4232 | scratch = reg; | |
4233 | ||
4234 | /* Load address into scratch register. Since we can't have a | |
4235 | secondary reload for a secondary reload we have to cover the case | |
4236 | where larl would need a secondary reload here as well. */ | |
4237 | s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch); | |
4238 | ||
4239 | /* Now we can use a standard load/store to do the move. */ | |
4240 | if (tomem) | |
4241 | emit_move_insn (replace_equiv_address (mem, scratch), reg); | |
4242 | else | |
4243 | emit_move_insn (reg, replace_equiv_address (mem, scratch)); | |
4244 | } | |
4245 | ||
833cd70a | 4246 | /* Inform reload about cases where moving X with a mode MODE to a register in |
0a2aaacc | 4247 | RCLASS requires an extra scratch or immediate register. Return the class |
833cd70a | 4248 | needed for the immediate register. */ |
f61a2c7d | 4249 | |
a87cf97e JR |
4250 | static reg_class_t |
4251 | s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, | |
ef4bddc2 | 4252 | machine_mode mode, secondary_reload_info *sri) |
833cd70a | 4253 | { |
a87cf97e JR |
4254 | enum reg_class rclass = (enum reg_class) rclass_i; |
4255 | ||
833cd70a | 4256 | /* Intermediate register needed. */ |
0a2aaacc | 4257 | if (reg_classes_intersect_p (CC_REGS, rclass)) |
9dc62c00 AK |
4258 | return GENERAL_REGS; |
4259 | ||
085261c8 AK |
4260 | if (TARGET_VX) |
4261 | { | |
4262 | /* The vst/vl vector move instructions allow only for short | |
4263 | displacements. */ | |
4264 | if (MEM_P (x) | |
4265 | && GET_CODE (XEXP (x, 0)) == PLUS | |
4266 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
4267 | && !SHORT_DISP_IN_RANGE(INTVAL (XEXP (XEXP (x, 0), 1))) | |
4268 | && reg_class_subset_p (rclass, VEC_REGS) | |
4269 | && (!reg_class_subset_p (rclass, FP_REGS) | |
4270 | || (GET_MODE_SIZE (mode) > 8 | |
4271 | && s390_class_max_nregs (FP_REGS, mode) == 1))) | |
4272 | { | |
4273 | if (in_p) | |
4274 | sri->icode = (TARGET_64BIT ? | |
4275 | CODE_FOR_reloaddi_la_in : | |
4276 | CODE_FOR_reloadsi_la_in); | |
4277 | else | |
4278 | sri->icode = (TARGET_64BIT ? | |
4279 | CODE_FOR_reloaddi_la_out : | |
4280 | CODE_FOR_reloadsi_la_out); | |
4281 | } | |
4282 | } | |
4283 | ||
963fc8d0 AK |
4284 | if (TARGET_Z10) |
4285 | { | |
212aa74f AK |
4286 | HOST_WIDE_INT offset; |
4287 | rtx symref; | |
4288 | ||
963fc8d0 AK |
4289 | /* On z10 several optimizer steps may generate larl operands with |
4290 | an odd addend. */ | |
4291 | if (in_p | |
0ff4390d | 4292 | && s390_loadrelative_operand_p (x, &symref, &offset) |
963fc8d0 | 4293 | && mode == Pmode |
e63d44c2 | 4294 | && !SYMBOL_FLAG_NOTALIGN2_P (symref) |
212aa74f | 4295 | && (offset & 1) == 1) |
963fc8d0 AK |
4296 | sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10 |
4297 | : CODE_FOR_reloadsi_larl_odd_addend_z10); | |
4298 | ||
05702110 AK |
4299 | /* Handle all the (mem (symref)) accesses we cannot use the z10 |
4300 | instructions for. */ | |
963fc8d0 | 4301 | if (MEM_P (x) |
0ff4390d | 4302 | && s390_loadrelative_operand_p (XEXP (x, 0), NULL, NULL) |
05702110 | 4303 | && (mode == QImode |
996fcca1 | 4304 | || !reg_class_subset_p (rclass, GENERAL_REGS) |
05702110 AK |
4305 | || GET_MODE_SIZE (mode) > UNITS_PER_WORD |
4306 | || !s390_check_symref_alignment (XEXP (x, 0), | |
4307 | GET_MODE_SIZE (mode)))) | |
963fc8d0 AK |
4308 | { |
4309 | #define __SECONDARY_RELOAD_CASE(M,m) \ | |
4e10a5a7 | 4310 | case E_##M##mode: \ |
963fc8d0 AK |
4311 | if (TARGET_64BIT) \ |
4312 | sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \ | |
4313 | CODE_FOR_reload##m##di_tomem_z10; \ | |
4314 | else \ | |
4315 | sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \ | |
4316 | CODE_FOR_reload##m##si_tomem_z10; \ | |
4317 | break; | |
4318 | ||
4319 | switch (GET_MODE (x)) | |
4320 | { | |
4321 | __SECONDARY_RELOAD_CASE (QI, qi); | |
4322 | __SECONDARY_RELOAD_CASE (HI, hi); | |
4323 | __SECONDARY_RELOAD_CASE (SI, si); | |
4324 | __SECONDARY_RELOAD_CASE (DI, di); | |
4325 | __SECONDARY_RELOAD_CASE (TI, ti); | |
4326 | __SECONDARY_RELOAD_CASE (SF, sf); | |
4327 | __SECONDARY_RELOAD_CASE (DF, df); | |
4328 | __SECONDARY_RELOAD_CASE (TF, tf); | |
4329 | __SECONDARY_RELOAD_CASE (SD, sd); | |
4330 | __SECONDARY_RELOAD_CASE (DD, dd); | |
4331 | __SECONDARY_RELOAD_CASE (TD, td); | |
085261c8 AK |
4332 | __SECONDARY_RELOAD_CASE (V1QI, v1qi); |
4333 | __SECONDARY_RELOAD_CASE (V2QI, v2qi); | |
4334 | __SECONDARY_RELOAD_CASE (V4QI, v4qi); | |
4335 | __SECONDARY_RELOAD_CASE (V8QI, v8qi); | |
4336 | __SECONDARY_RELOAD_CASE (V16QI, v16qi); | |
4337 | __SECONDARY_RELOAD_CASE (V1HI, v1hi); | |
4338 | __SECONDARY_RELOAD_CASE (V2HI, v2hi); | |
4339 | __SECONDARY_RELOAD_CASE (V4HI, v4hi); | |
4340 | __SECONDARY_RELOAD_CASE (V8HI, v8hi); | |
4341 | __SECONDARY_RELOAD_CASE (V1SI, v1si); | |
4342 | __SECONDARY_RELOAD_CASE (V2SI, v2si); | |
4343 | __SECONDARY_RELOAD_CASE (V4SI, v4si); | |
4344 | __SECONDARY_RELOAD_CASE (V1DI, v1di); | |
4345 | __SECONDARY_RELOAD_CASE (V2DI, v2di); | |
4346 | __SECONDARY_RELOAD_CASE (V1TI, v1ti); | |
4347 | __SECONDARY_RELOAD_CASE (V1SF, v1sf); | |
4348 | __SECONDARY_RELOAD_CASE (V2SF, v2sf); | |
4349 | __SECONDARY_RELOAD_CASE (V4SF, v4sf); | |
4350 | __SECONDARY_RELOAD_CASE (V1DF, v1df); | |
4351 | __SECONDARY_RELOAD_CASE (V2DF, v2df); | |
4352 | __SECONDARY_RELOAD_CASE (V1TF, v1tf); | |
963fc8d0 AK |
4353 | default: |
4354 | gcc_unreachable (); | |
4355 | } | |
4356 | #undef __SECONDARY_RELOAD_CASE | |
4357 | } | |
4358 | } | |
4359 | ||
833cd70a AK |
4360 | /* We need a scratch register when loading a PLUS expression which |
4361 | is not a legitimate operand of the LOAD ADDRESS instruction. */ | |
3597e113 VM |
4362 | /* LRA can deal with transformation of plus op very well -- so we |
4363 | don't need to prompt LRA in this case. */ | |
4364 | if (! lra_in_progress && in_p && s390_plus_operand (x, mode)) | |
833cd70a AK |
4365 | sri->icode = (TARGET_64BIT ? |
4366 | CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus); | |
4367 | ||
7fa7289d | 4368 | /* Performing a multiword move from or to memory we have to make sure the |
833cd70a AK |
4369 | second chunk in memory is addressable without causing a displacement |
4370 | overflow. If that would be the case we calculate the address in | |
4371 | a scratch register. */ | |
4372 | if (MEM_P (x) | |
4373 | && GET_CODE (XEXP (x, 0)) == PLUS | |
4374 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
4375 | && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1)) | |
0ca89db7 | 4376 | + GET_MODE_SIZE (mode) - 1)) |
833cd70a | 4377 | { |
7fa7289d | 4378 | /* For GENERAL_REGS a displacement overflow is no problem if occurring |
833cd70a AK |
4379 | in a s_operand address since we may fallback to lm/stm. So we only |
4380 | have to care about overflows in the b+i+d case. */ | |
0a2aaacc | 4381 | if ((reg_classes_intersect_p (GENERAL_REGS, rclass) |
833cd70a AK |
4382 | && s390_class_max_nregs (GENERAL_REGS, mode) > 1 |
4383 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS) | |
4384 | /* For FP_REGS no lm/stm is available so this check is triggered | |
4385 | for displacement overflows in b+i+d and b+d like addresses. */ | |
0a2aaacc | 4386 | || (reg_classes_intersect_p (FP_REGS, rclass) |
833cd70a AK |
4387 | && s390_class_max_nregs (FP_REGS, mode) > 1)) |
4388 | { | |
4389 | if (in_p) | |
4390 | sri->icode = (TARGET_64BIT ? | |
085261c8 AK |
4391 | CODE_FOR_reloaddi_la_in : |
4392 | CODE_FOR_reloadsi_la_in); | |
833cd70a AK |
4393 | else |
4394 | sri->icode = (TARGET_64BIT ? | |
085261c8 AK |
4395 | CODE_FOR_reloaddi_la_out : |
4396 | CODE_FOR_reloadsi_la_out); | |
833cd70a AK |
4397 | } |
4398 | } | |
9dc62c00 | 4399 | |
1f9e1fc6 AK |
4400 | /* A scratch address register is needed when a symbolic constant is |
4401 | copied to r0 compiling with -fPIC. In other cases the target | |
4402 | register might be used as temporary (see legitimize_pic_address). */ | |
0a2aaacc | 4403 | if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS) |
1f9e1fc6 AK |
4404 | sri->icode = (TARGET_64BIT ? |
4405 | CODE_FOR_reloaddi_PIC_addr : | |
4406 | CODE_FOR_reloadsi_PIC_addr); | |
4407 | ||
833cd70a | 4408 | /* Either scratch or no register needed. */ |
dc65c307 UW |
4409 | return NO_REGS; |
4410 | } | |
4411 | ||
f3e9edff UW |
4412 | /* Generate code to load SRC, which is PLUS that is not a |
4413 | legitimate operand for the LA instruction, into TARGET. | |
4414 | SCRATCH may be used as scratch register. */ | |
4415 | ||
4416 | void | |
5d81b82b AS |
4417 | s390_expand_plus_operand (rtx target, rtx src, |
4418 | rtx scratch) | |
f3e9edff | 4419 | { |
7974fe63 | 4420 | rtx sum1, sum2; |
b808c04c | 4421 | struct s390_address ad; |
6a4e49c1 | 4422 | |
6a4e49c1 | 4423 | /* src must be a PLUS; get its two operands. */ |
8d933e31 AS |
4424 | gcc_assert (GET_CODE (src) == PLUS); |
4425 | gcc_assert (GET_MODE (src) == Pmode); | |
f3e9edff | 4426 | |
7c82a1ed UW |
4427 | /* Check if any of the two operands is already scheduled |
4428 | for replacement by reload. This can happen e.g. when | |
4429 | float registers occur in an address. */ | |
4430 | sum1 = find_replacement (&XEXP (src, 0)); | |
4431 | sum2 = find_replacement (&XEXP (src, 1)); | |
ccfc6cc8 | 4432 | src = gen_rtx_PLUS (Pmode, sum1, sum2); |
ccfc6cc8 | 4433 | |
7974fe63 UW |
4434 | /* If the address is already strictly valid, there's nothing to do. */ |
4435 | if (!s390_decompose_address (src, &ad) | |
93fa8428 AK |
4436 | || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base))) |
4437 | || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))) | |
f3e9edff | 4438 | { |
7974fe63 UW |
4439 | /* Otherwise, one of the operands cannot be an address register; |
4440 | we reload its value into the scratch register. */ | |
4441 | if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15) | |
4442 | { | |
4443 | emit_move_insn (scratch, sum1); | |
4444 | sum1 = scratch; | |
4445 | } | |
4446 | if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15) | |
4447 | { | |
4448 | emit_move_insn (scratch, sum2); | |
4449 | sum2 = scratch; | |
4450 | } | |
f3e9edff | 4451 | |
7974fe63 UW |
4452 | /* According to the way these invalid addresses are generated |
4453 | in reload.c, it should never happen (at least on s390) that | |
4454 | *neither* of the PLUS components, after find_replacements | |
4455 | was applied, is an address register. */ | |
4456 | if (sum1 == scratch && sum2 == scratch) | |
4457 | { | |
4458 | debug_rtx (src); | |
8d933e31 | 4459 | gcc_unreachable (); |
7974fe63 | 4460 | } |
f3e9edff | 4461 | |
7974fe63 | 4462 | src = gen_rtx_PLUS (Pmode, sum1, sum2); |
f3e9edff UW |
4463 | } |
4464 | ||
4465 | /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS | |
4466 | is only ever performed on addresses, so we can mark the | |
4467 | sum as legitimate for LA in any case. */ | |
a41c6c53 | 4468 | s390_load_address (target, src); |
f3e9edff UW |
4469 | } |
4470 | ||
4471 | ||
3ed99cc9 | 4472 | /* Return true if ADDR is a valid memory address. |
ab96de7e | 4473 | STRICT specifies whether strict register checking applies. */ |
9db1d521 | 4474 | |
c6c3dba9 | 4475 | static bool |
ef4bddc2 | 4476 | s390_legitimate_address_p (machine_mode mode, rtx addr, bool strict) |
9db1d521 | 4477 | { |
ab96de7e | 4478 | struct s390_address ad; |
963fc8d0 AK |
4479 | |
4480 | if (TARGET_Z10 | |
4481 | && larl_operand (addr, VOIDmode) | |
4482 | && (mode == VOIDmode | |
4483 | || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode)))) | |
4484 | return true; | |
4485 | ||
ab96de7e | 4486 | if (!s390_decompose_address (addr, &ad)) |
3ed99cc9 | 4487 | return false; |
b808c04c UW |
4488 | |
4489 | if (strict) | |
4490 | { | |
93fa8428 | 4491 | if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base))) |
3ed99cc9 | 4492 | return false; |
93fa8428 AK |
4493 | |
4494 | if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))) | |
3ed99cc9 | 4495 | return false; |
b808c04c UW |
4496 | } |
4497 | else | |
4498 | { | |
f4aa3848 | 4499 | if (ad.base |
93fa8428 AK |
4500 | && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER |
4501 | || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS)) | |
3ed99cc9 | 4502 | return false; |
f4aa3848 | 4503 | |
93fa8428 AK |
4504 | if (ad.indx |
4505 | && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER | |
4506 | || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS)) | |
4507 | return false; | |
b808c04c | 4508 | } |
3ed99cc9 | 4509 | return true; |
9db1d521 HP |
4510 | } |
4511 | ||
3ed99cc9 | 4512 | /* Return true if OP is a valid operand for the LA instruction. |
ba956982 UW |
4513 | In 31-bit, we need to prove that the result is used as an |
4514 | address, as LA performs only a 31-bit addition. */ | |
4515 | ||
3ed99cc9 | 4516 | bool |
5d81b82b | 4517 | legitimate_la_operand_p (rtx op) |
ba956982 UW |
4518 | { |
4519 | struct s390_address addr; | |
b808c04c | 4520 | if (!s390_decompose_address (op, &addr)) |
3ed99cc9 | 4521 | return false; |
ba956982 | 4522 | |
3ed99cc9 | 4523 | return (TARGET_64BIT || addr.pointer); |
f3e9edff | 4524 | } |
ba956982 | 4525 | |
3ed99cc9 | 4526 | /* Return true if it is valid *and* preferable to use LA to |
e1d5ee28 | 4527 | compute the sum of OP1 and OP2. */ |
c7453384 | 4528 | |
3ed99cc9 | 4529 | bool |
e1d5ee28 | 4530 | preferred_la_operand_p (rtx op1, rtx op2) |
100c7420 UW |
4531 | { |
4532 | struct s390_address addr; | |
e1d5ee28 UW |
4533 | |
4534 | if (op2 != const0_rtx) | |
4535 | op1 = gen_rtx_PLUS (Pmode, op1, op2); | |
4536 | ||
4537 | if (!s390_decompose_address (op1, &addr)) | |
3ed99cc9 | 4538 | return false; |
93fa8428 | 4539 | if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base))) |
3ed99cc9 | 4540 | return false; |
93fa8428 | 4541 | if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx))) |
3ed99cc9 | 4542 | return false; |
100c7420 | 4543 | |
65b1d8ea | 4544 | /* Avoid LA instructions with index register on z196; it is |
22ac2c2f AK |
4545 | preferable to use regular add instructions when possible. |
4546 | Starting with zEC12 the la with index register is "uncracked" | |
4547 | again. */ | |
65b1d8ea AK |
4548 | if (addr.indx && s390_tune == PROCESSOR_2817_Z196) |
4549 | return false; | |
4550 | ||
100c7420 | 4551 | if (!TARGET_64BIT && !addr.pointer) |
3ed99cc9 | 4552 | return false; |
100c7420 UW |
4553 | |
4554 | if (addr.pointer) | |
3ed99cc9 | 4555 | return true; |
100c7420 | 4556 | |
4888ec5d UW |
4557 | if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base)) |
4558 | || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx))) | |
3ed99cc9 | 4559 | return true; |
100c7420 | 4560 | |
3ed99cc9 | 4561 | return false; |
100c7420 UW |
4562 | } |
4563 | ||
a41c6c53 UW |
4564 | /* Emit a forced load-address operation to load SRC into DST. |
4565 | This will use the LOAD ADDRESS instruction even in situations | |
4566 | where legitimate_la_operand_p (SRC) returns false. */ | |
ba956982 | 4567 | |
a41c6c53 | 4568 | void |
9c808aad | 4569 | s390_load_address (rtx dst, rtx src) |
f3e9edff | 4570 | { |
a41c6c53 UW |
4571 | if (TARGET_64BIT) |
4572 | emit_move_insn (dst, src); | |
4573 | else | |
4574 | emit_insn (gen_force_la_31 (dst, src)); | |
ba956982 UW |
4575 | } |
4576 | ||
935b5226 AK |
4577 | /* Return true if it ok to use SYMBOL_REF in a relative address. */ |
4578 | ||
4579 | bool | |
4580 | s390_rel_address_ok_p (rtx symbol_ref) | |
4581 | { | |
4582 | tree decl; | |
4583 | ||
4584 | if (symbol_ref == s390_got_symbol () || CONSTANT_POOL_ADDRESS_P (symbol_ref)) | |
4585 | return true; | |
4586 | ||
4587 | decl = SYMBOL_REF_DECL (symbol_ref); | |
4588 | ||
4589 | if (!flag_pic || SYMBOL_REF_LOCAL_P (symbol_ref)) | |
4590 | return (s390_pic_data_is_text_relative | |
4591 | || (decl | |
4592 | && TREE_CODE (decl) == FUNCTION_DECL)); | |
4593 | ||
4594 | return false; | |
4595 | } | |
4596 | ||
9db1d521 HP |
4597 | /* Return a legitimate reference for ORIG (an address) using the |
4598 | register REG. If REG is 0, a new pseudo is generated. | |
4599 | ||
4600 | There are two types of references that must be handled: | |
4601 | ||
4602 | 1. Global data references must load the address from the GOT, via | |
4603 | the PIC reg. An insn is emitted to do this load, and the reg is | |
4604 | returned. | |
4605 | ||
4606 | 2. Static data references, constant pool addresses, and code labels | |
4607 | compute the address as an offset from the GOT, whose base is in | |
114278e7 | 4608 | the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to |
9db1d521 HP |
4609 | differentiate them from global data objects. The returned |
4610 | address is the PIC reg + an unspec constant. | |
4611 | ||
331d9186 | 4612 | TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC |
9db1d521 HP |
4613 | reg also appears in the address. */ |
4614 | ||
4615 | rtx | |
9c808aad | 4616 | legitimize_pic_address (rtx orig, rtx reg) |
9db1d521 HP |
4617 | { |
4618 | rtx addr = orig; | |
0ff4390d | 4619 | rtx addend = const0_rtx; |
0a2aaacc | 4620 | rtx new_rtx = orig; |
9db1d521 | 4621 | |
cf9d7618 ANM |
4622 | gcc_assert (!TLS_SYMBOLIC_CONST (addr)); |
4623 | ||
0ff4390d AK |
4624 | if (GET_CODE (addr) == CONST) |
4625 | addr = XEXP (addr, 0); | |
4626 | ||
4627 | if (GET_CODE (addr) == PLUS) | |
9db1d521 | 4628 | { |
0ff4390d AK |
4629 | addend = XEXP (addr, 1); |
4630 | addr = XEXP (addr, 0); | |
4631 | } | |
4632 | ||
4633 | if ((GET_CODE (addr) == LABEL_REF | |
935b5226 | 4634 | || (SYMBOL_REF_P (addr) && s390_rel_address_ok_p (addr)) |
0ff4390d AK |
4635 | || (GET_CODE (addr) == UNSPEC && |
4636 | (XINT (addr, 1) == UNSPEC_GOTENT | |
4637 | || (TARGET_CPU_ZARCH && XINT (addr, 1) == UNSPEC_PLT)))) | |
4638 | && GET_CODE (addend) == CONST_INT) | |
4639 | { | |
4640 | /* This can be locally addressed. */ | |
4641 | ||
4642 | /* larl_operand requires UNSPECs to be wrapped in a const rtx. */ | |
4643 | rtx const_addr = (GET_CODE (addr) == UNSPEC ? | |
4644 | gen_rtx_CONST (Pmode, addr) : addr); | |
4645 | ||
4646 | if (TARGET_CPU_ZARCH | |
4647 | && larl_operand (const_addr, VOIDmode) | |
406fde6e DV |
4648 | && INTVAL (addend) < HOST_WIDE_INT_1 << 31 |
4649 | && INTVAL (addend) >= -(HOST_WIDE_INT_1 << 31)) | |
0ff4390d AK |
4650 | { |
4651 | if (INTVAL (addend) & 1) | |
4652 | { | |
4653 | /* LARL can't handle odd offsets, so emit a pair of LARL | |
4654 | and LA. */ | |
4655 | rtx temp = reg? reg : gen_reg_rtx (Pmode); | |
4656 | ||
4657 | if (!DISP_IN_RANGE (INTVAL (addend))) | |
4658 | { | |
4659 | HOST_WIDE_INT even = INTVAL (addend) - 1; | |
4660 | addr = gen_rtx_PLUS (Pmode, addr, GEN_INT (even)); | |
4661 | addr = gen_rtx_CONST (Pmode, addr); | |
4662 | addend = const1_rtx; | |
4663 | } | |
4664 | ||
4665 | emit_move_insn (temp, addr); | |
4666 | new_rtx = gen_rtx_PLUS (Pmode, temp, addend); | |
4667 | ||
4668 | if (reg != 0) | |
4669 | { | |
4670 | s390_load_address (reg, new_rtx); | |
4671 | new_rtx = reg; | |
4672 | } | |
4673 | } | |
4674 | else | |
4675 | { | |
4676 | /* If the offset is even, we can just use LARL. This | |
4677 | will happen automatically. */ | |
4678 | } | |
4679 | } | |
9db1d521 | 4680 | else |
0ff4390d AK |
4681 | { |
4682 | /* No larl - Access local symbols relative to the GOT. */ | |
9db1d521 | 4683 | |
0ff4390d | 4684 | rtx temp = reg? reg : gen_reg_rtx (Pmode); |
9db1d521 | 4685 | |
fd7643fb | 4686 | if (reload_in_progress || reload_completed) |
6fb5fa3c | 4687 | df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); |
fd7643fb | 4688 | |
0ff4390d AK |
4689 | addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF); |
4690 | if (addend != const0_rtx) | |
4691 | addr = gen_rtx_PLUS (Pmode, addr, addend); | |
4692 | addr = gen_rtx_CONST (Pmode, addr); | |
4693 | addr = force_const_mem (Pmode, addr); | |
9db1d521 HP |
4694 | emit_move_insn (temp, addr); |
4695 | ||
0ff4390d AK |
4696 | new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp); |
4697 | if (reg != 0) | |
4698 | { | |
4699 | s390_load_address (reg, new_rtx); | |
4700 | new_rtx = reg; | |
4701 | } | |
4702 | } | |
9db1d521 | 4703 | } |
0ff4390d | 4704 | else if (GET_CODE (addr) == SYMBOL_REF && addend == const0_rtx) |
9db1d521 | 4705 | { |
0ff4390d AK |
4706 | /* A non-local symbol reference without addend. |
4707 | ||
4708 | The symbol ref is wrapped into an UNSPEC to make sure the | |
4709 | proper operand modifier (@GOT or @GOTENT) will be emitted. | |
4710 | This will tell the linker to put the symbol into the GOT. | |
4711 | ||
4712 | Additionally the code dereferencing the GOT slot is emitted here. | |
4713 | ||
4714 | An addend to the symref needs to be added afterwards. | |
4715 | legitimize_pic_address calls itself recursively to handle | |
4716 | that case. So no need to do it here. */ | |
4717 | ||
9db1d521 HP |
4718 | if (reg == 0) |
4719 | reg = gen_reg_rtx (Pmode); | |
4720 | ||
0ff4390d AK |
4721 | if (TARGET_Z10) |
4722 | { | |
4723 | /* Use load relative if possible. | |
4724 | lgrl <target>, sym@GOTENT */ | |
4725 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT); | |
4726 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
4727 | new_rtx = gen_const_mem (GET_MODE (reg), new_rtx); | |
4728 | ||
4729 | emit_move_insn (reg, new_rtx); | |
4730 | new_rtx = reg; | |
4731 | } | |
4732 | else if (flag_pic == 1) | |
9db1d521 | 4733 | { |
0ff4390d AK |
4734 | /* Assume GOT offset is a valid displacement operand (< 4k |
4735 | or < 512k with z990). This is handled the same way in | |
4736 | both 31- and 64-bit code (@GOT). | |
4737 | lg <target>, sym@GOT(r12) */ | |
9db1d521 | 4738 | |
c3cc6b78 | 4739 | if (reload_in_progress || reload_completed) |
6fb5fa3c | 4740 | df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); |
9db1d521 | 4741 | |
0a2aaacc KG |
4742 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT); |
4743 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
4744 | new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx); | |
4745 | new_rtx = gen_const_mem (Pmode, new_rtx); | |
4746 | emit_move_insn (reg, new_rtx); | |
4747 | new_rtx = reg; | |
9db1d521 | 4748 | } |
9e8327e3 | 4749 | else if (TARGET_CPU_ZARCH) |
9db1d521 HP |
4750 | { |
4751 | /* If the GOT offset might be >= 4k, we determine the position | |
0ff4390d AK |
4752 | of the GOT entry via a PC-relative LARL (@GOTENT). |
4753 | larl temp, sym@GOTENT | |
4754 | lg <target>, 0(temp) */ | |
9db1d521 | 4755 | |
1f9e1fc6 AK |
4756 | rtx temp = reg ? reg : gen_reg_rtx (Pmode); |
4757 | ||
4758 | gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER | |
4759 | || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS); | |
9db1d521 | 4760 | |
0a2aaacc KG |
4761 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT); |
4762 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
0ff4390d | 4763 | emit_move_insn (temp, new_rtx); |
9db1d521 | 4764 | |
0ff4390d | 4765 | new_rtx = gen_const_mem (Pmode, temp); |
0a2aaacc | 4766 | emit_move_insn (reg, new_rtx); |
0ff4390d | 4767 | |
0a2aaacc | 4768 | new_rtx = reg; |
9db1d521 HP |
4769 | } |
4770 | else | |
4771 | { | |
c7453384 | 4772 | /* If the GOT offset might be >= 4k, we have to load it |
0ff4390d AK |
4773 | from the literal pool (@GOT). |
4774 | ||
4775 | lg temp, lit-litbase(r13) | |
4776 | lg <target>, 0(temp) | |
4777 | lit: .long sym@GOT */ | |
9db1d521 | 4778 | |
1f9e1fc6 AK |
4779 | rtx temp = reg ? reg : gen_reg_rtx (Pmode); |
4780 | ||
4781 | gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER | |
4782 | || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS); | |
9db1d521 | 4783 | |
c3cc6b78 | 4784 | if (reload_in_progress || reload_completed) |
6fb5fa3c | 4785 | df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); |
9db1d521 | 4786 | |
fd7643fb | 4787 | addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT); |
e23795ea UW |
4788 | addr = gen_rtx_CONST (Pmode, addr); |
4789 | addr = force_const_mem (Pmode, addr); | |
9db1d521 HP |
4790 | emit_move_insn (temp, addr); |
4791 | ||
0a2aaacc KG |
4792 | new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp); |
4793 | new_rtx = gen_const_mem (Pmode, new_rtx); | |
4794 | emit_move_insn (reg, new_rtx); | |
4795 | new_rtx = reg; | |
9db1d521 | 4796 | } |
c7453384 | 4797 | } |
0ff4390d | 4798 | else if (GET_CODE (addr) == UNSPEC && GET_CODE (addend) == CONST_INT) |
9db1d521 | 4799 | { |
0ff4390d AK |
4800 | gcc_assert (XVECLEN (addr, 0) == 1); |
4801 | switch (XINT (addr, 1)) | |
9db1d521 | 4802 | { |
0ff4390d AK |
4803 | /* These address symbols (or PLT slots) relative to the GOT |
4804 | (not GOT slots!). In general this will exceed the | |
4805 | displacement range so these value belong into the literal | |
4806 | pool. */ | |
4807 | case UNSPEC_GOTOFF: | |
4808 | case UNSPEC_PLTOFF: | |
4809 | new_rtx = force_const_mem (Pmode, orig); | |
4810 | break; | |
9db1d521 | 4811 | |
0ff4390d AK |
4812 | /* For -fPIC the GOT size might exceed the displacement |
4813 | range so make sure the value is in the literal pool. */ | |
4814 | case UNSPEC_GOT: | |
4815 | if (flag_pic == 2) | |
4816 | new_rtx = force_const_mem (Pmode, orig); | |
4817 | break; | |
9db1d521 | 4818 | |
0ff4390d AK |
4819 | /* For @GOTENT larl is used. This is handled like local |
4820 | symbol refs. */ | |
4821 | case UNSPEC_GOTENT: | |
4822 | gcc_unreachable (); | |
4823 | break; | |
9db1d521 | 4824 | |
0ff4390d AK |
4825 | /* @PLT is OK as is on 64-bit, must be converted to |
4826 | GOT-relative @PLTOFF on 31-bit. */ | |
4827 | case UNSPEC_PLT: | |
4828 | if (!TARGET_CPU_ZARCH) | |
9db1d521 | 4829 | { |
0ff4390d AK |
4830 | rtx temp = reg? reg : gen_reg_rtx (Pmode); |
4831 | ||
4832 | if (reload_in_progress || reload_completed) | |
4833 | df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); | |
4834 | ||
4835 | addr = XVECEXP (addr, 0, 0); | |
4836 | addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), | |
4837 | UNSPEC_PLTOFF); | |
4838 | if (addend != const0_rtx) | |
4839 | addr = gen_rtx_PLUS (Pmode, addr, addend); | |
4840 | addr = gen_rtx_CONST (Pmode, addr); | |
4841 | addr = force_const_mem (Pmode, addr); | |
4842 | emit_move_insn (temp, addr); | |
4843 | ||
4844 | new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp); | |
4845 | if (reg != 0) | |
9db1d521 | 4846 | { |
0ff4390d AK |
4847 | s390_load_address (reg, new_rtx); |
4848 | new_rtx = reg; | |
9db1d521 | 4849 | } |
0ff4390d AK |
4850 | } |
4851 | else | |
4852 | /* On 64 bit larl can be used. This case is handled like | |
4853 | local symbol refs. */ | |
4854 | gcc_unreachable (); | |
4855 | break; | |
4856 | ||
4857 | /* Everything else cannot happen. */ | |
4858 | default: | |
4859 | gcc_unreachable (); | |
4860 | } | |
4861 | } | |
4862 | else if (addend != const0_rtx) | |
4863 | { | |
4864 | /* Otherwise, compute the sum. */ | |
9db1d521 | 4865 | |
0ff4390d AK |
4866 | rtx base = legitimize_pic_address (addr, reg); |
4867 | new_rtx = legitimize_pic_address (addend, | |
4868 | base == reg ? NULL_RTX : reg); | |
4869 | if (GET_CODE (new_rtx) == CONST_INT) | |
4870 | new_rtx = plus_constant (Pmode, base, INTVAL (new_rtx)); | |
4871 | else | |
4872 | { | |
4873 | if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1))) | |
4874 | { | |
4875 | base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0)); | |
4876 | new_rtx = XEXP (new_rtx, 1); | |
9db1d521 | 4877 | } |
0ff4390d | 4878 | new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx); |
9db1d521 | 4879 | } |
0ff4390d AK |
4880 | |
4881 | if (GET_CODE (new_rtx) == CONST) | |
4882 | new_rtx = XEXP (new_rtx, 0); | |
4883 | new_rtx = force_operand (new_rtx, 0); | |
9db1d521 | 4884 | } |
0ff4390d | 4885 | |
0a2aaacc | 4886 | return new_rtx; |
9db1d521 HP |
4887 | } |
4888 | ||
fd3cd001 UW |
4889 | /* Load the thread pointer into a register. */ |
4890 | ||
7b8acc34 AK |
4891 | rtx |
4892 | s390_get_thread_pointer (void) | |
fd3cd001 | 4893 | { |
c5aa1d12 | 4894 | rtx tp = gen_reg_rtx (Pmode); |
fd3cd001 | 4895 | |
c5aa1d12 | 4896 | emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM)); |
fd3cd001 UW |
4897 | mark_reg_pointer (tp, BITS_PER_WORD); |
4898 | ||
4899 | return tp; | |
4900 | } | |
4901 | ||
ed9676cf AK |
4902 | /* Emit a tls call insn. The call target is the SYMBOL_REF stored |
4903 | in s390_tls_symbol which always refers to __tls_get_offset. | |
4904 | The returned offset is written to RESULT_REG and an USE rtx is | |
4905 | generated for TLS_CALL. */ | |
fd3cd001 UW |
4906 | |
4907 | static GTY(()) rtx s390_tls_symbol; | |
ed9676cf AK |
4908 | |
4909 | static void | |
4910 | s390_emit_tls_call_insn (rtx result_reg, rtx tls_call) | |
fd3cd001 | 4911 | { |
ed9676cf | 4912 | rtx insn; |
38899e29 | 4913 | |
68c0ef75 AK |
4914 | if (!flag_pic) |
4915 | emit_insn (s390_load_got ()); | |
ed9676cf | 4916 | |
fd3cd001 UW |
4917 | if (!s390_tls_symbol) |
4918 | s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset"); | |
4919 | ||
38899e29 EC |
4920 | insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg, |
4921 | gen_rtx_REG (Pmode, RETURN_REGNUM)); | |
ed9676cf AK |
4922 | |
4923 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg); | |
becfd6e5 | 4924 | RTL_CONST_CALL_P (insn) = 1; |
fd3cd001 UW |
4925 | } |
4926 | ||
4927 | /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute | |
4928 | this (thread-local) address. REG may be used as temporary. */ | |
4929 | ||
4930 | static rtx | |
9c808aad | 4931 | legitimize_tls_address (rtx addr, rtx reg) |
fd3cd001 | 4932 | { |
9b2ea071 TS |
4933 | rtx new_rtx, tls_call, temp, base, r2; |
4934 | rtx_insn *insn; | |
fd3cd001 UW |
4935 | |
4936 | if (GET_CODE (addr) == SYMBOL_REF) | |
4937 | switch (tls_symbolic_operand (addr)) | |
4938 | { | |
4939 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
4940 | start_sequence (); | |
4941 | r2 = gen_rtx_REG (Pmode, 2); | |
4942 | tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD); | |
0a2aaacc KG |
4943 | new_rtx = gen_rtx_CONST (Pmode, tls_call); |
4944 | new_rtx = force_const_mem (Pmode, new_rtx); | |
4945 | emit_move_insn (r2, new_rtx); | |
ed9676cf | 4946 | s390_emit_tls_call_insn (r2, tls_call); |
fd3cd001 UW |
4947 | insn = get_insns (); |
4948 | end_sequence (); | |
4949 | ||
0a2aaacc | 4950 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF); |
fd3cd001 | 4951 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 4952 | emit_libcall_block (insn, temp, r2, new_rtx); |
fd3cd001 | 4953 | |
0a2aaacc | 4954 | new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp); |
fd3cd001 UW |
4955 | if (reg != 0) |
4956 | { | |
0a2aaacc KG |
4957 | s390_load_address (reg, new_rtx); |
4958 | new_rtx = reg; | |
fd3cd001 UW |
4959 | } |
4960 | break; | |
4961 | ||
4962 | case TLS_MODEL_LOCAL_DYNAMIC: | |
4963 | start_sequence (); | |
4964 | r2 = gen_rtx_REG (Pmode, 2); | |
4965 | tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM); | |
0a2aaacc KG |
4966 | new_rtx = gen_rtx_CONST (Pmode, tls_call); |
4967 | new_rtx = force_const_mem (Pmode, new_rtx); | |
4968 | emit_move_insn (r2, new_rtx); | |
ed9676cf | 4969 | s390_emit_tls_call_insn (r2, tls_call); |
fd3cd001 UW |
4970 | insn = get_insns (); |
4971 | end_sequence (); | |
4972 | ||
0a2aaacc | 4973 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF); |
fd3cd001 | 4974 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 4975 | emit_libcall_block (insn, temp, r2, new_rtx); |
fd3cd001 | 4976 | |
0a2aaacc | 4977 | new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp); |
fd3cd001 | 4978 | base = gen_reg_rtx (Pmode); |
0a2aaacc | 4979 | s390_load_address (base, new_rtx); |
fd3cd001 | 4980 | |
0a2aaacc KG |
4981 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF); |
4982 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
4983 | new_rtx = force_const_mem (Pmode, new_rtx); | |
fd3cd001 | 4984 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 4985 | emit_move_insn (temp, new_rtx); |
fd3cd001 | 4986 | |
0a2aaacc | 4987 | new_rtx = gen_rtx_PLUS (Pmode, base, temp); |
fd3cd001 UW |
4988 | if (reg != 0) |
4989 | { | |
0a2aaacc KG |
4990 | s390_load_address (reg, new_rtx); |
4991 | new_rtx = reg; | |
fd3cd001 UW |
4992 | } |
4993 | break; | |
4994 | ||
4995 | case TLS_MODEL_INITIAL_EXEC: | |
4996 | if (flag_pic == 1) | |
4997 | { | |
4998 | /* Assume GOT offset < 4k. This is handled the same way | |
4999 | in both 31- and 64-bit code. */ | |
5000 | ||
5001 | if (reload_in_progress || reload_completed) | |
6fb5fa3c | 5002 | df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); |
fd3cd001 | 5003 | |
0a2aaacc KG |
5004 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF); |
5005 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
5006 | new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx); | |
5007 | new_rtx = gen_const_mem (Pmode, new_rtx); | |
fd3cd001 | 5008 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 5009 | emit_move_insn (temp, new_rtx); |
fd3cd001 | 5010 | } |
9e8327e3 | 5011 | else if (TARGET_CPU_ZARCH) |
fd3cd001 UW |
5012 | { |
5013 | /* If the GOT offset might be >= 4k, we determine the position | |
5014 | of the GOT entry via a PC-relative LARL. */ | |
5015 | ||
0a2aaacc KG |
5016 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF); |
5017 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
fd3cd001 | 5018 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 5019 | emit_move_insn (temp, new_rtx); |
fd3cd001 | 5020 | |
0a2aaacc | 5021 | new_rtx = gen_const_mem (Pmode, temp); |
fd3cd001 | 5022 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 5023 | emit_move_insn (temp, new_rtx); |
fd3cd001 UW |
5024 | } |
5025 | else if (flag_pic) | |
5026 | { | |
c7453384 | 5027 | /* If the GOT offset might be >= 4k, we have to load it |
fd3cd001 UW |
5028 | from the literal pool. */ |
5029 | ||
5030 | if (reload_in_progress || reload_completed) | |
6fb5fa3c | 5031 | df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); |
fd3cd001 | 5032 | |
0a2aaacc KG |
5033 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF); |
5034 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
5035 | new_rtx = force_const_mem (Pmode, new_rtx); | |
fd3cd001 | 5036 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 5037 | emit_move_insn (temp, new_rtx); |
fd3cd001 | 5038 | |
0a2aaacc KG |
5039 | new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp); |
5040 | new_rtx = gen_const_mem (Pmode, new_rtx); | |
fd3cd001 | 5041 | |
0a2aaacc | 5042 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD); |
fd3cd001 | 5043 | temp = gen_reg_rtx (Pmode); |
f7df4a84 | 5044 | emit_insn (gen_rtx_SET (temp, new_rtx)); |
fd3cd001 UW |
5045 | } |
5046 | else | |
5047 | { | |
5048 | /* In position-dependent code, load the absolute address of | |
5049 | the GOT entry from the literal pool. */ | |
5050 | ||
0a2aaacc KG |
5051 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF); |
5052 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
5053 | new_rtx = force_const_mem (Pmode, new_rtx); | |
fd3cd001 | 5054 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 5055 | emit_move_insn (temp, new_rtx); |
fd3cd001 | 5056 | |
0a2aaacc KG |
5057 | new_rtx = temp; |
5058 | new_rtx = gen_const_mem (Pmode, new_rtx); | |
5059 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD); | |
fd3cd001 | 5060 | temp = gen_reg_rtx (Pmode); |
f7df4a84 | 5061 | emit_insn (gen_rtx_SET (temp, new_rtx)); |
fd3cd001 UW |
5062 | } |
5063 | ||
0a2aaacc | 5064 | new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp); |
fd3cd001 UW |
5065 | if (reg != 0) |
5066 | { | |
0a2aaacc KG |
5067 | s390_load_address (reg, new_rtx); |
5068 | new_rtx = reg; | |
fd3cd001 UW |
5069 | } |
5070 | break; | |
5071 | ||
5072 | case TLS_MODEL_LOCAL_EXEC: | |
0a2aaacc KG |
5073 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF); |
5074 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
5075 | new_rtx = force_const_mem (Pmode, new_rtx); | |
fd3cd001 | 5076 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 5077 | emit_move_insn (temp, new_rtx); |
fd3cd001 | 5078 | |
0a2aaacc | 5079 | new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp); |
fd3cd001 UW |
5080 | if (reg != 0) |
5081 | { | |
0a2aaacc KG |
5082 | s390_load_address (reg, new_rtx); |
5083 | new_rtx = reg; | |
fd3cd001 UW |
5084 | } |
5085 | break; | |
5086 | ||
5087 | default: | |
8d933e31 | 5088 | gcc_unreachable (); |
fd3cd001 UW |
5089 | } |
5090 | ||
5091 | else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC) | |
5092 | { | |
5093 | switch (XINT (XEXP (addr, 0), 1)) | |
5094 | { | |
5095 | case UNSPEC_INDNTPOFF: | |
8d933e31 | 5096 | gcc_assert (TARGET_CPU_ZARCH); |
0a2aaacc | 5097 | new_rtx = addr; |
fd3cd001 UW |
5098 | break; |
5099 | ||
5100 | default: | |
8d933e31 | 5101 | gcc_unreachable (); |
fd3cd001 UW |
5102 | } |
5103 | } | |
5104 | ||
578d1468 UW |
5105 | else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS |
5106 | && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT) | |
5107 | { | |
0a2aaacc KG |
5108 | new_rtx = XEXP (XEXP (addr, 0), 0); |
5109 | if (GET_CODE (new_rtx) != SYMBOL_REF) | |
5110 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
578d1468 | 5111 | |
0a2aaacc | 5112 | new_rtx = legitimize_tls_address (new_rtx, reg); |
0a81f074 RS |
5113 | new_rtx = plus_constant (Pmode, new_rtx, |
5114 | INTVAL (XEXP (XEXP (addr, 0), 1))); | |
0a2aaacc | 5115 | new_rtx = force_operand (new_rtx, 0); |
578d1468 UW |
5116 | } |
5117 | ||
fd3cd001 | 5118 | else |
8d933e31 | 5119 | gcc_unreachable (); /* for now ... */ |
fd3cd001 | 5120 | |
0a2aaacc | 5121 | return new_rtx; |
fd3cd001 UW |
5122 | } |
5123 | ||
1f9e1fc6 AK |
5124 | /* Emit insns making the address in operands[1] valid for a standard |
5125 | move to operands[0]. operands[1] is replaced by an address which | |
5126 | should be used instead of the former RTX to emit the move | |
5127 | pattern. */ | |
9db1d521 HP |
5128 | |
5129 | void | |
9c808aad | 5130 | emit_symbolic_move (rtx *operands) |
9db1d521 | 5131 | { |
b3a13419 | 5132 | rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); |
9db1d521 | 5133 | |
fd3cd001 | 5134 | if (GET_CODE (operands[0]) == MEM) |
9db1d521 | 5135 | operands[1] = force_reg (Pmode, operands[1]); |
fd3cd001 UW |
5136 | else if (TLS_SYMBOLIC_CONST (operands[1])) |
5137 | operands[1] = legitimize_tls_address (operands[1], temp); | |
5138 | else if (flag_pic) | |
9db1d521 HP |
5139 | operands[1] = legitimize_pic_address (operands[1], temp); |
5140 | } | |
5141 | ||
994fe660 | 5142 | /* Try machine-dependent ways of modifying an illegitimate address X |
9db1d521 | 5143 | to be legitimate. If we find one, return the new, valid address. |
9db1d521 HP |
5144 | |
5145 | OLDX is the address as it was before break_out_memory_refs was called. | |
5146 | In some cases it is useful to look at this to decide what needs to be done. | |
5147 | ||
994fe660 | 5148 | MODE is the mode of the operand pointed to by X. |
9db1d521 HP |
5149 | |
5150 | When -fpic is used, special handling is needed for symbolic references. | |
5151 | See comments by legitimize_pic_address for details. */ | |
5152 | ||
506d7b68 PB |
5153 | static rtx |
5154 | s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, | |
ef4bddc2 | 5155 | machine_mode mode ATTRIBUTE_UNUSED) |
9db1d521 | 5156 | { |
ba956982 | 5157 | rtx constant_term = const0_rtx; |
9db1d521 | 5158 | |
fd3cd001 UW |
5159 | if (TLS_SYMBOLIC_CONST (x)) |
5160 | { | |
5161 | x = legitimize_tls_address (x, 0); | |
5162 | ||
c6c3dba9 | 5163 | if (s390_legitimate_address_p (mode, x, FALSE)) |
fd3cd001 UW |
5164 | return x; |
5165 | } | |
cf9d7618 | 5166 | else if (GET_CODE (x) == PLUS |
f4aa3848 | 5167 | && (TLS_SYMBOLIC_CONST (XEXP (x, 0)) |
cf9d7618 ANM |
5168 | || TLS_SYMBOLIC_CONST (XEXP (x, 1)))) |
5169 | { | |
5170 | return x; | |
5171 | } | |
fd3cd001 | 5172 | else if (flag_pic) |
9db1d521 | 5173 | { |
ba956982 | 5174 | if (SYMBOLIC_CONST (x) |
c7453384 EC |
5175 | || (GET_CODE (x) == PLUS |
5176 | && (SYMBOLIC_CONST (XEXP (x, 0)) | |
ba956982 UW |
5177 | || SYMBOLIC_CONST (XEXP (x, 1))))) |
5178 | x = legitimize_pic_address (x, 0); | |
5179 | ||
c6c3dba9 | 5180 | if (s390_legitimate_address_p (mode, x, FALSE)) |
ba956982 | 5181 | return x; |
9db1d521 | 5182 | } |
9db1d521 | 5183 | |
ba956982 | 5184 | x = eliminate_constant_term (x, &constant_term); |
994fe660 | 5185 | |
61f02ff5 UW |
5186 | /* Optimize loading of large displacements by splitting them |
5187 | into the multiple of 4K and the rest; this allows the | |
c7453384 | 5188 | former to be CSE'd if possible. |
61f02ff5 UW |
5189 | |
5190 | Don't do this if the displacement is added to a register | |
5191 | pointing into the stack frame, as the offsets will | |
5192 | change later anyway. */ | |
5193 | ||
5194 | if (GET_CODE (constant_term) == CONST_INT | |
d3632d41 UW |
5195 | && !TARGET_LONG_DISPLACEMENT |
5196 | && !DISP_IN_RANGE (INTVAL (constant_term)) | |
61f02ff5 UW |
5197 | && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x)))) |
5198 | { | |
5199 | HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff; | |
5200 | HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower; | |
5201 | ||
5202 | rtx temp = gen_reg_rtx (Pmode); | |
5203 | rtx val = force_operand (GEN_INT (upper), temp); | |
5204 | if (val != temp) | |
5205 | emit_move_insn (temp, val); | |
5206 | ||
5207 | x = gen_rtx_PLUS (Pmode, x, temp); | |
5208 | constant_term = GEN_INT (lower); | |
5209 | } | |
5210 | ||
ba956982 | 5211 | if (GET_CODE (x) == PLUS) |
9db1d521 | 5212 | { |
ba956982 UW |
5213 | if (GET_CODE (XEXP (x, 0)) == REG) |
5214 | { | |
5d81b82b AS |
5215 | rtx temp = gen_reg_rtx (Pmode); |
5216 | rtx val = force_operand (XEXP (x, 1), temp); | |
ba956982 UW |
5217 | if (val != temp) |
5218 | emit_move_insn (temp, val); | |
5219 | ||
5220 | x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp); | |
5221 | } | |
5222 | ||
5223 | else if (GET_CODE (XEXP (x, 1)) == REG) | |
5224 | { | |
5d81b82b AS |
5225 | rtx temp = gen_reg_rtx (Pmode); |
5226 | rtx val = force_operand (XEXP (x, 0), temp); | |
ba956982 UW |
5227 | if (val != temp) |
5228 | emit_move_insn (temp, val); | |
5229 | ||
5230 | x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1)); | |
5231 | } | |
9db1d521 | 5232 | } |
ba956982 UW |
5233 | |
5234 | if (constant_term != const0_rtx) | |
5235 | x = gen_rtx_PLUS (Pmode, x, constant_term); | |
5236 | ||
5237 | return x; | |
9db1d521 HP |
5238 | } |
5239 | ||
0b540f12 | 5240 | /* Try a machine-dependent way of reloading an illegitimate address AD |
dd5a833e | 5241 | operand. If we find one, push the reload and return the new address. |
0b540f12 UW |
5242 | |
5243 | MODE is the mode of the enclosing MEM. OPNUM is the operand number | |
5244 | and TYPE is the reload type of the current reload. */ | |
5245 | ||
f4aa3848 | 5246 | rtx |
ef4bddc2 | 5247 | legitimize_reload_address (rtx ad, machine_mode mode ATTRIBUTE_UNUSED, |
0b540f12 UW |
5248 | int opnum, int type) |
5249 | { | |
5250 | if (!optimize || TARGET_LONG_DISPLACEMENT) | |
5251 | return NULL_RTX; | |
5252 | ||
5253 | if (GET_CODE (ad) == PLUS) | |
5254 | { | |
5255 | rtx tem = simplify_binary_operation (PLUS, Pmode, | |
5256 | XEXP (ad, 0), XEXP (ad, 1)); | |
5257 | if (tem) | |
5258 | ad = tem; | |
5259 | } | |
5260 | ||
5261 | if (GET_CODE (ad) == PLUS | |
5262 | && GET_CODE (XEXP (ad, 0)) == REG | |
5263 | && GET_CODE (XEXP (ad, 1)) == CONST_INT | |
5264 | && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1)))) | |
5265 | { | |
5266 | HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff; | |
5267 | HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower; | |
0a2aaacc | 5268 | rtx cst, tem, new_rtx; |
0b540f12 UW |
5269 | |
5270 | cst = GEN_INT (upper); | |
5271 | if (!legitimate_reload_constant_p (cst)) | |
5272 | cst = force_const_mem (Pmode, cst); | |
5273 | ||
5274 | tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst); | |
0a2aaacc | 5275 | new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower)); |
0b540f12 UW |
5276 | |
5277 | push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0, | |
f4aa3848 | 5278 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, |
0b540f12 | 5279 | opnum, (enum reload_type) type); |
0a2aaacc | 5280 | return new_rtx; |
0b540f12 UW |
5281 | } |
5282 | ||
5283 | return NULL_RTX; | |
5284 | } | |
5285 | ||
a41c6c53 UW |
5286 | /* Emit code to move LEN bytes from DST to SRC. */ |
5287 | ||
367d32f3 | 5288 | bool |
70128ad9 | 5289 | s390_expand_movmem (rtx dst, rtx src, rtx len) |
a41c6c53 | 5290 | { |
367d32f3 AK |
5291 | /* When tuning for z10 or higher we rely on the Glibc functions to |
5292 | do the right thing. Only for constant lengths below 64k we will | |
5293 | generate inline code. */ | |
5294 | if (s390_tune >= PROCESSOR_2097_Z10 | |
5295 | && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16))) | |
5296 | return false; | |
5297 | ||
f5a537e3 AK |
5298 | /* Expand memcpy for constant length operands without a loop if it |
5299 | is shorter that way. | |
5300 | ||
5301 | With a constant length argument a | |
5302 | memcpy loop (without pfd) is 36 bytes -> 6 * mvc */ | |
5303 | if (GET_CODE (len) == CONST_INT | |
5304 | && INTVAL (len) >= 0 | |
5305 | && INTVAL (len) <= 256 * 6 | |
5306 | && (!TARGET_MVCLE || INTVAL (len) <= 256)) | |
a41c6c53 | 5307 | { |
f5a537e3 AK |
5308 | HOST_WIDE_INT o, l; |
5309 | ||
5310 | for (l = INTVAL (len), o = 0; l > 0; l -= 256, o += 256) | |
5311 | { | |
5312 | rtx newdst = adjust_address (dst, BLKmode, o); | |
5313 | rtx newsrc = adjust_address (src, BLKmode, o); | |
5314 | emit_insn (gen_movmem_short (newdst, newsrc, | |
5315 | GEN_INT (l > 256 ? 255 : l - 1))); | |
5316 | } | |
a41c6c53 UW |
5317 | } |
5318 | ||
5319 | else if (TARGET_MVCLE) | |
5320 | { | |
70128ad9 | 5321 | emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1))); |
a41c6c53 UW |
5322 | } |
5323 | ||
5324 | else | |
5325 | { | |
5326 | rtx dst_addr, src_addr, count, blocks, temp; | |
19f8b229 TS |
5327 | rtx_code_label *loop_start_label = gen_label_rtx (); |
5328 | rtx_code_label *loop_end_label = gen_label_rtx (); | |
5329 | rtx_code_label *end_label = gen_label_rtx (); | |
ef4bddc2 | 5330 | machine_mode mode; |
a41c6c53 UW |
5331 | |
5332 | mode = GET_MODE (len); | |
5333 | if (mode == VOIDmode) | |
b9404c99 | 5334 | mode = Pmode; |
a41c6c53 | 5335 | |
a41c6c53 UW |
5336 | dst_addr = gen_reg_rtx (Pmode); |
5337 | src_addr = gen_reg_rtx (Pmode); | |
5338 | count = gen_reg_rtx (mode); | |
5339 | blocks = gen_reg_rtx (mode); | |
5340 | ||
5341 | convert_move (count, len, 1); | |
c7453384 | 5342 | emit_cmp_and_jump_insns (count, const0_rtx, |
a41c6c53 UW |
5343 | EQ, NULL_RTX, mode, 1, end_label); |
5344 | ||
5345 | emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX)); | |
5346 | emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX)); | |
5347 | dst = change_address (dst, VOIDmode, dst_addr); | |
5348 | src = change_address (src, VOIDmode, src_addr); | |
c7453384 | 5349 | |
bbbbb16a ILT |
5350 | temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, |
5351 | OPTAB_DIRECT); | |
a41c6c53 UW |
5352 | if (temp != count) |
5353 | emit_move_insn (count, temp); | |
5354 | ||
bbbbb16a ILT |
5355 | temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1, |
5356 | OPTAB_DIRECT); | |
a41c6c53 UW |
5357 | if (temp != blocks) |
5358 | emit_move_insn (blocks, temp); | |
5359 | ||
6de9cd9a DN |
5360 | emit_cmp_and_jump_insns (blocks, const0_rtx, |
5361 | EQ, NULL_RTX, mode, 1, loop_end_label); | |
70315fcd SB |
5362 | |
5363 | emit_label (loop_start_label); | |
a41c6c53 | 5364 | |
adfa3cd3 AK |
5365 | if (TARGET_Z10 |
5366 | && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768)) | |
5367 | { | |
5368 | rtx prefetch; | |
5369 | ||
5370 | /* Issue a read prefetch for the +3 cache line. */ | |
5371 | prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)), | |
5372 | const0_rtx, const0_rtx); | |
5373 | PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true; | |
5374 | emit_insn (prefetch); | |
5375 | ||
5376 | /* Issue a write prefetch for the +3 cache line. */ | |
5377 | prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)), | |
5378 | const1_rtx, const0_rtx); | |
5379 | PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true; | |
5380 | emit_insn (prefetch); | |
5381 | } | |
5382 | ||
70128ad9 | 5383 | emit_insn (gen_movmem_short (dst, src, GEN_INT (255))); |
c7453384 | 5384 | s390_load_address (dst_addr, |
a41c6c53 | 5385 | gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256))); |
c7453384 | 5386 | s390_load_address (src_addr, |
a41c6c53 | 5387 | gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256))); |
c7453384 | 5388 | |
bbbbb16a ILT |
5389 | temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, |
5390 | OPTAB_DIRECT); | |
a41c6c53 UW |
5391 | if (temp != blocks) |
5392 | emit_move_insn (blocks, temp); | |
5393 | ||
6de9cd9a DN |
5394 | emit_cmp_and_jump_insns (blocks, const0_rtx, |
5395 | EQ, NULL_RTX, mode, 1, loop_end_label); | |
70315fcd SB |
5396 | |
5397 | emit_jump (loop_start_label); | |
6de9cd9a | 5398 | emit_label (loop_end_label); |
a41c6c53 | 5399 | |
70128ad9 | 5400 | emit_insn (gen_movmem_short (dst, src, |
b9404c99 | 5401 | convert_to_mode (Pmode, count, 1))); |
a41c6c53 UW |
5402 | emit_label (end_label); |
5403 | } | |
367d32f3 | 5404 | return true; |
a41c6c53 UW |
5405 | } |
5406 | ||
6d057022 AS |
5407 | /* Emit code to set LEN bytes at DST to VAL. |
5408 | Make use of clrmem if VAL is zero. */ | |
a41c6c53 UW |
5409 | |
5410 | void | |
6d057022 | 5411 | s390_expand_setmem (rtx dst, rtx len, rtx val) |
a41c6c53 | 5412 | { |
8597cd33 | 5413 | if (GET_CODE (len) == CONST_INT && INTVAL (len) <= 0) |
c9f59991 AK |
5414 | return; |
5415 | ||
6d057022 | 5416 | gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode); |
f4aa3848 | 5417 | |
8597cd33 AK |
5418 | /* Expand setmem/clrmem for a constant length operand without a |
5419 | loop if it will be shorter that way. | |
5420 | With a constant length and without pfd argument a | |
5421 | clrmem loop is 32 bytes -> 5.3 * xc | |
5422 | setmem loop is 36 bytes -> 3.6 * (mvi/stc + mvc) */ | |
5423 | if (GET_CODE (len) == CONST_INT | |
5424 | && ((INTVAL (len) <= 256 * 5 && val == const0_rtx) | |
5425 | || INTVAL (len) <= 257 * 3) | |
5426 | && (!TARGET_MVCLE || INTVAL (len) <= 256)) | |
a41c6c53 | 5427 | { |
8597cd33 | 5428 | HOST_WIDE_INT o, l; |
f4aa3848 | 5429 | |
8597cd33 AK |
5430 | if (val == const0_rtx) |
5431 | /* clrmem: emit 256 byte blockwise XCs. */ | |
5432 | for (l = INTVAL (len), o = 0; l > 0; l -= 256, o += 256) | |
5433 | { | |
5434 | rtx newdst = adjust_address (dst, BLKmode, o); | |
5435 | emit_insn (gen_clrmem_short (newdst, | |
5436 | GEN_INT (l > 256 ? 255 : l - 1))); | |
5437 | } | |
5438 | else | |
5439 | /* setmem: emit 1(mvi) + 256(mvc) byte blockwise memsets by | |
5440 | setting first byte to val and using a 256 byte mvc with one | |
5441 | byte overlap to propagate the byte. */ | |
5442 | for (l = INTVAL (len), o = 0; l > 0; l -= 257, o += 257) | |
5443 | { | |
5444 | rtx newdst = adjust_address (dst, BLKmode, o); | |
5445 | emit_move_insn (adjust_address (dst, QImode, o), val); | |
5446 | if (l > 1) | |
5447 | { | |
5448 | rtx newdstp1 = adjust_address (dst, BLKmode, o + 1); | |
5449 | emit_insn (gen_movmem_short (newdstp1, newdst, | |
5450 | GEN_INT (l > 257 ? 255 : l - 2))); | |
5451 | } | |
5452 | } | |
a41c6c53 UW |
5453 | } |
5454 | ||
5455 | else if (TARGET_MVCLE) | |
5456 | { | |
6d057022 | 5457 | val = force_not_mem (convert_modes (Pmode, QImode, val, 1)); |
da0dcab1 DV |
5458 | if (TARGET_64BIT) |
5459 | emit_insn (gen_setmem_long_di (dst, convert_to_mode (Pmode, len, 1), | |
5460 | val)); | |
5461 | else | |
5462 | emit_insn (gen_setmem_long_si (dst, convert_to_mode (Pmode, len, 1), | |
5463 | val)); | |
a41c6c53 UW |
5464 | } |
5465 | ||
5466 | else | |
5467 | { | |
9602b6a1 | 5468 | rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX; |
19f8b229 | 5469 | rtx_code_label *loop_start_label = gen_label_rtx (); |
587790e6 AK |
5470 | rtx_code_label *onebyte_end_label = gen_label_rtx (); |
5471 | rtx_code_label *zerobyte_end_label = gen_label_rtx (); | |
5472 | rtx_code_label *restbyte_end_label = gen_label_rtx (); | |
ef4bddc2 | 5473 | machine_mode mode; |
a41c6c53 UW |
5474 | |
5475 | mode = GET_MODE (len); | |
5476 | if (mode == VOIDmode) | |
587790e6 | 5477 | mode = Pmode; |
a41c6c53 | 5478 | |
a41c6c53 | 5479 | dst_addr = gen_reg_rtx (Pmode); |
a41c6c53 UW |
5480 | count = gen_reg_rtx (mode); |
5481 | blocks = gen_reg_rtx (mode); | |
5482 | ||
5483 | convert_move (count, len, 1); | |
c7453384 | 5484 | emit_cmp_and_jump_insns (count, const0_rtx, |
587790e6 | 5485 | EQ, NULL_RTX, mode, 1, zerobyte_end_label, |
8f746f8c | 5486 | profile_probability::very_unlikely ()); |
a41c6c53 | 5487 | |
587790e6 AK |
5488 | /* We need to make a copy of the target address since memset is |
5489 | supposed to return it unmodified. We have to make it here | |
5490 | already since the new reg is used at onebyte_end_label. */ | |
a41c6c53 UW |
5491 | emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX)); |
5492 | dst = change_address (dst, VOIDmode, dst_addr); | |
c7453384 | 5493 | |
587790e6 | 5494 | if (val != const0_rtx) |
6d057022 | 5495 | { |
587790e6 AK |
5496 | /* When using the overlapping mvc the original target |
5497 | address is only accessed as single byte entity (even by | |
5498 | the mvc reading this value). */ | |
f5541398 | 5499 | set_mem_size (dst, 1); |
587790e6 AK |
5500 | dstp1 = adjust_address (dst, VOIDmode, 1); |
5501 | emit_cmp_and_jump_insns (count, | |
5502 | const1_rtx, EQ, NULL_RTX, mode, 1, | |
8f746f8c AK |
5503 | onebyte_end_label, |
5504 | profile_probability::very_unlikely ()); | |
6d057022 | 5505 | } |
587790e6 AK |
5506 | |
5507 | /* There is one unconditional (mvi+mvc)/xc after the loop | |
5508 | dealing with the rest of the bytes, subtracting two (mvi+mvc) | |
5509 | or one (xc) here leaves this number of bytes to be handled by | |
5510 | it. */ | |
5511 | temp = expand_binop (mode, add_optab, count, | |
5512 | val == const0_rtx ? constm1_rtx : GEN_INT (-2), | |
5513 | count, 1, OPTAB_DIRECT); | |
a41c6c53 | 5514 | if (temp != count) |
587790e6 | 5515 | emit_move_insn (count, temp); |
a41c6c53 | 5516 | |
bbbbb16a ILT |
5517 | temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1, |
5518 | OPTAB_DIRECT); | |
a41c6c53 | 5519 | if (temp != blocks) |
587790e6 | 5520 | emit_move_insn (blocks, temp); |
a41c6c53 | 5521 | |
6de9cd9a | 5522 | emit_cmp_and_jump_insns (blocks, const0_rtx, |
587790e6 AK |
5523 | EQ, NULL_RTX, mode, 1, restbyte_end_label); |
5524 | ||
5525 | emit_jump (loop_start_label); | |
5526 | ||
5527 | if (val != const0_rtx) | |
5528 | { | |
5529 | /* The 1 byte != 0 special case. Not handled efficiently | |
5530 | since we require two jumps for that. However, this | |
5531 | should be very rare. */ | |
5532 | emit_label (onebyte_end_label); | |
5533 | emit_move_insn (adjust_address (dst, QImode, 0), val); | |
5534 | emit_jump (zerobyte_end_label); | |
5535 | } | |
70315fcd SB |
5536 | |
5537 | emit_label (loop_start_label); | |
a41c6c53 | 5538 | |
adfa3cd3 AK |
5539 | if (TARGET_Z10 |
5540 | && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024)) | |
5541 | { | |
5542 | /* Issue a write prefetch for the +4 cache line. */ | |
5543 | rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, | |
5544 | GEN_INT (1024)), | |
5545 | const1_rtx, const0_rtx); | |
5546 | emit_insn (prefetch); | |
5547 | PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true; | |
5548 | } | |
5549 | ||
6d057022 AS |
5550 | if (val == const0_rtx) |
5551 | emit_insn (gen_clrmem_short (dst, GEN_INT (255))); | |
5552 | else | |
587790e6 AK |
5553 | { |
5554 | /* Set the first byte in the block to the value and use an | |
5555 | overlapping mvc for the block. */ | |
5556 | emit_move_insn (adjust_address (dst, QImode, 0), val); | |
5557 | emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (254))); | |
5558 | } | |
c7453384 | 5559 | s390_load_address (dst_addr, |
a41c6c53 | 5560 | gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256))); |
c7453384 | 5561 | |
bbbbb16a ILT |
5562 | temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, |
5563 | OPTAB_DIRECT); | |
a41c6c53 | 5564 | if (temp != blocks) |
587790e6 | 5565 | emit_move_insn (blocks, temp); |
a41c6c53 | 5566 | |
6de9cd9a | 5567 | emit_cmp_and_jump_insns (blocks, const0_rtx, |
587790e6 | 5568 | NE, NULL_RTX, mode, 1, loop_start_label); |
70315fcd | 5569 | |
587790e6 | 5570 | emit_label (restbyte_end_label); |
a41c6c53 | 5571 | |
6d057022 | 5572 | if (val == const0_rtx) |
587790e6 | 5573 | emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1))); |
6d057022 | 5574 | else |
587790e6 AK |
5575 | { |
5576 | /* Set the first byte in the block to the value and use an | |
5577 | overlapping mvc for the block. */ | |
5578 | emit_move_insn (adjust_address (dst, QImode, 0), val); | |
5579 | /* execute only uses the lowest 8 bits of count that's | |
5580 | exactly what we need here. */ | |
5581 | emit_insn (gen_movmem_short (dstp1, dst, | |
5582 | convert_to_mode (Pmode, count, 1))); | |
5583 | } | |
5584 | ||
5585 | emit_label (zerobyte_end_label); | |
a41c6c53 UW |
5586 | } |
5587 | } | |
5588 | ||
5589 | /* Emit code to compare LEN bytes at OP0 with those at OP1, | |
5590 | and return the result in TARGET. */ | |
5591 | ||
367d32f3 | 5592 | bool |
9c808aad | 5593 | s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len) |
a41c6c53 | 5594 | { |
5b022de5 | 5595 | rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM); |
02887425 UW |
5596 | rtx tmp; |
5597 | ||
367d32f3 AK |
5598 | /* When tuning for z10 or higher we rely on the Glibc functions to |
5599 | do the right thing. Only for constant lengths below 64k we will | |
5600 | generate inline code. */ | |
5601 | if (s390_tune >= PROCESSOR_2097_Z10 | |
5602 | && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16))) | |
5603 | return false; | |
5604 | ||
02887425 UW |
5605 | /* As the result of CMPINT is inverted compared to what we need, |
5606 | we have to swap the operands. */ | |
5607 | tmp = op0; op0 = op1; op1 = tmp; | |
a41c6c53 | 5608 | |
a41c6c53 UW |
5609 | if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256) |
5610 | { | |
5611 | if (INTVAL (len) > 0) | |
5612 | { | |
b9404c99 | 5613 | emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1))); |
02887425 | 5614 | emit_insn (gen_cmpint (target, ccreg)); |
a41c6c53 UW |
5615 | } |
5616 | else | |
5617 | emit_move_insn (target, const0_rtx); | |
5618 | } | |
9dc62c00 | 5619 | else if (TARGET_MVCLE) |
a41c6c53 | 5620 | { |
b9404c99 | 5621 | emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1))); |
02887425 | 5622 | emit_insn (gen_cmpint (target, ccreg)); |
a41c6c53 | 5623 | } |
a41c6c53 UW |
5624 | else |
5625 | { | |
5626 | rtx addr0, addr1, count, blocks, temp; | |
19f8b229 TS |
5627 | rtx_code_label *loop_start_label = gen_label_rtx (); |
5628 | rtx_code_label *loop_end_label = gen_label_rtx (); | |
5629 | rtx_code_label *end_label = gen_label_rtx (); | |
ef4bddc2 | 5630 | machine_mode mode; |
a41c6c53 UW |
5631 | |
5632 | mode = GET_MODE (len); | |
5633 | if (mode == VOIDmode) | |
b9404c99 | 5634 | mode = Pmode; |
a41c6c53 | 5635 | |
a41c6c53 UW |
5636 | addr0 = gen_reg_rtx (Pmode); |
5637 | addr1 = gen_reg_rtx (Pmode); | |
5638 | count = gen_reg_rtx (mode); | |
5639 | blocks = gen_reg_rtx (mode); | |
5640 | ||
5641 | convert_move (count, len, 1); | |
c7453384 | 5642 | emit_cmp_and_jump_insns (count, const0_rtx, |
a41c6c53 UW |
5643 | EQ, NULL_RTX, mode, 1, end_label); |
5644 | ||
5645 | emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX)); | |
5646 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
5647 | op0 = change_address (op0, VOIDmode, addr0); | |
5648 | op1 = change_address (op1, VOIDmode, addr1); | |
c7453384 | 5649 | |
bbbbb16a ILT |
5650 | temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, |
5651 | OPTAB_DIRECT); | |
a41c6c53 UW |
5652 | if (temp != count) |
5653 | emit_move_insn (count, temp); | |
5654 | ||
bbbbb16a ILT |
5655 | temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1, |
5656 | OPTAB_DIRECT); | |
a41c6c53 UW |
5657 | if (temp != blocks) |
5658 | emit_move_insn (blocks, temp); | |
5659 | ||
6de9cd9a DN |
5660 | emit_cmp_and_jump_insns (blocks, const0_rtx, |
5661 | EQ, NULL_RTX, mode, 1, loop_end_label); | |
70315fcd SB |
5662 | |
5663 | emit_label (loop_start_label); | |
a41c6c53 | 5664 | |
adfa3cd3 AK |
5665 | if (TARGET_Z10 |
5666 | && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512)) | |
5667 | { | |
5668 | rtx prefetch; | |
5669 | ||
5670 | /* Issue a read prefetch for the +2 cache line of operand 1. */ | |
5671 | prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)), | |
5672 | const0_rtx, const0_rtx); | |
5673 | emit_insn (prefetch); | |
5674 | PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true; | |
5675 | ||
5676 | /* Issue a read prefetch for the +2 cache line of operand 2. */ | |
5677 | prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)), | |
5678 | const0_rtx, const0_rtx); | |
5679 | emit_insn (prefetch); | |
5680 | PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true; | |
5681 | } | |
5682 | ||
b9404c99 | 5683 | emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255))); |
5b022de5 | 5684 | temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx); |
c7453384 | 5685 | temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp, |
a41c6c53 | 5686 | gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx); |
f7df4a84 | 5687 | temp = gen_rtx_SET (pc_rtx, temp); |
a41c6c53 UW |
5688 | emit_jump_insn (temp); |
5689 | ||
c7453384 | 5690 | s390_load_address (addr0, |
a41c6c53 | 5691 | gen_rtx_PLUS (Pmode, addr0, GEN_INT (256))); |
c7453384 | 5692 | s390_load_address (addr1, |
a41c6c53 | 5693 | gen_rtx_PLUS (Pmode, addr1, GEN_INT (256))); |
c7453384 | 5694 | |
bbbbb16a ILT |
5695 | temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, |
5696 | OPTAB_DIRECT); | |
a41c6c53 UW |
5697 | if (temp != blocks) |
5698 | emit_move_insn (blocks, temp); | |
5699 | ||
6de9cd9a DN |
5700 | emit_cmp_and_jump_insns (blocks, const0_rtx, |
5701 | EQ, NULL_RTX, mode, 1, loop_end_label); | |
70315fcd SB |
5702 | |
5703 | emit_jump (loop_start_label); | |
6de9cd9a | 5704 | emit_label (loop_end_label); |
a41c6c53 | 5705 | |
38899e29 | 5706 | emit_insn (gen_cmpmem_short (op0, op1, |
b9404c99 | 5707 | convert_to_mode (Pmode, count, 1))); |
a41c6c53 UW |
5708 | emit_label (end_label); |
5709 | ||
02887425 | 5710 | emit_insn (gen_cmpint (target, ccreg)); |
a41c6c53 | 5711 | } |
367d32f3 | 5712 | return true; |
a41c6c53 UW |
5713 | } |
5714 | ||
085261c8 AK |
5715 | /* Emit a conditional jump to LABEL for condition code mask MASK using |
5716 | comparsion operator COMPARISON. Return the emitted jump insn. */ | |
5717 | ||
d8485bdb | 5718 | static rtx_insn * |
085261c8 AK |
5719 | s390_emit_ccraw_jump (HOST_WIDE_INT mask, enum rtx_code comparison, rtx label) |
5720 | { | |
5721 | rtx temp; | |
5722 | ||
5723 | gcc_assert (comparison == EQ || comparison == NE); | |
5724 | gcc_assert (mask > 0 && mask < 15); | |
5725 | ||
5726 | temp = gen_rtx_fmt_ee (comparison, VOIDmode, | |
5727 | gen_rtx_REG (CCRAWmode, CC_REGNUM), GEN_INT (mask)); | |
5728 | temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp, | |
5729 | gen_rtx_LABEL_REF (VOIDmode, label), pc_rtx); | |
5730 | temp = gen_rtx_SET (pc_rtx, temp); | |
5731 | return emit_jump_insn (temp); | |
5732 | } | |
5733 | ||
5734 | /* Emit the instructions to implement strlen of STRING and store the | |
5735 | result in TARGET. The string has the known ALIGNMENT. This | |
5736 | version uses vector instructions and is therefore not appropriate | |
5737 | for targets prior to z13. */ | |
5738 | ||
5739 | void | |
5740 | s390_expand_vec_strlen (rtx target, rtx string, rtx alignment) | |
5741 | { | |
085261c8 AK |
5742 | rtx highest_index_to_load_reg = gen_reg_rtx (Pmode); |
5743 | rtx str_reg = gen_reg_rtx (V16QImode); | |
5744 | rtx str_addr_base_reg = gen_reg_rtx (Pmode); | |
5745 | rtx str_idx_reg = gen_reg_rtx (Pmode); | |
5746 | rtx result_reg = gen_reg_rtx (V16QImode); | |
5747 | rtx is_aligned_label = gen_label_rtx (); | |
5748 | rtx into_loop_label = NULL_RTX; | |
5749 | rtx loop_start_label = gen_label_rtx (); | |
5750 | rtx temp; | |
5751 | rtx len = gen_reg_rtx (QImode); | |
5752 | rtx cond; | |
5753 | ||
5754 | s390_load_address (str_addr_base_reg, XEXP (string, 0)); | |
5755 | emit_move_insn (str_idx_reg, const0_rtx); | |
5756 | ||
5757 | if (INTVAL (alignment) < 16) | |
5758 | { | |
5759 | /* Check whether the address happens to be aligned properly so | |
5760 | jump directly to the aligned loop. */ | |
5761 | emit_cmp_and_jump_insns (gen_rtx_AND (Pmode, | |
5762 | str_addr_base_reg, GEN_INT (15)), | |
5763 | const0_rtx, EQ, NULL_RTX, | |
5764 | Pmode, 1, is_aligned_label); | |
5765 | ||
5766 | temp = gen_reg_rtx (Pmode); | |
5767 | temp = expand_binop (Pmode, and_optab, str_addr_base_reg, | |
5768 | GEN_INT (15), temp, 1, OPTAB_DIRECT); | |
5769 | gcc_assert (REG_P (temp)); | |
5770 | highest_index_to_load_reg = | |
5771 | expand_binop (Pmode, sub_optab, GEN_INT (15), temp, | |
5772 | highest_index_to_load_reg, 1, OPTAB_DIRECT); | |
5773 | gcc_assert (REG_P (highest_index_to_load_reg)); | |
5774 | emit_insn (gen_vllv16qi (str_reg, | |
5775 | convert_to_mode (SImode, highest_index_to_load_reg, 1), | |
5776 | gen_rtx_MEM (BLKmode, str_addr_base_reg))); | |
5777 | ||
5778 | into_loop_label = gen_label_rtx (); | |
5779 | s390_emit_jump (into_loop_label, NULL_RTX); | |
5780 | emit_barrier (); | |
5781 | } | |
5782 | ||
5783 | emit_label (is_aligned_label); | |
5784 | LABEL_NUSES (is_aligned_label) = INTVAL (alignment) < 16 ? 2 : 1; | |
5785 | ||
5786 | /* Reaching this point we are only performing 16 bytes aligned | |
5787 | loads. */ | |
5788 | emit_move_insn (highest_index_to_load_reg, GEN_INT (15)); | |
5789 | ||
5790 | emit_label (loop_start_label); | |
5791 | LABEL_NUSES (loop_start_label) = 1; | |
5792 | ||
5793 | /* Load 16 bytes of the string into VR. */ | |
5794 | emit_move_insn (str_reg, | |
5795 | gen_rtx_MEM (V16QImode, | |
5796 | gen_rtx_PLUS (Pmode, str_idx_reg, | |
5797 | str_addr_base_reg))); | |
5798 | if (into_loop_label != NULL_RTX) | |
5799 | { | |
5800 | emit_label (into_loop_label); | |
5801 | LABEL_NUSES (into_loop_label) = 1; | |
5802 | } | |
5803 | ||
5804 | /* Increment string index by 16 bytes. */ | |
5805 | expand_binop (Pmode, add_optab, str_idx_reg, GEN_INT (16), | |
5806 | str_idx_reg, 1, OPTAB_DIRECT); | |
5807 | ||
5808 | emit_insn (gen_vec_vfenesv16qi (result_reg, str_reg, str_reg, | |
5809 | GEN_INT (VSTRING_FLAG_ZS | VSTRING_FLAG_CS))); | |
5810 | ||
5811 | add_int_reg_note (s390_emit_ccraw_jump (8, NE, loop_start_label), | |
5fa396ad JH |
5812 | REG_BR_PROB, |
5813 | profile_probability::very_likely ().to_reg_br_prob_note ()); | |
ff03930a | 5814 | emit_insn (gen_vec_extractv16qiqi (len, result_reg, GEN_INT (7))); |
085261c8 AK |
5815 | |
5816 | /* If the string pointer wasn't aligned we have loaded less then 16 | |
5817 | bytes and the remaining bytes got filled with zeros (by vll). | |
5818 | Now we have to check whether the resulting index lies within the | |
5819 | bytes actually part of the string. */ | |
5820 | ||
5821 | cond = s390_emit_compare (GT, convert_to_mode (Pmode, len, 1), | |
5822 | highest_index_to_load_reg); | |
5823 | s390_load_address (highest_index_to_load_reg, | |
5824 | gen_rtx_PLUS (Pmode, highest_index_to_load_reg, | |
5825 | const1_rtx)); | |
5826 | if (TARGET_64BIT) | |
5827 | emit_insn (gen_movdicc (str_idx_reg, cond, | |
5828 | highest_index_to_load_reg, str_idx_reg)); | |
5829 | else | |
5830 | emit_insn (gen_movsicc (str_idx_reg, cond, | |
5831 | highest_index_to_load_reg, str_idx_reg)); | |
5832 | ||
5fa396ad JH |
5833 | add_reg_br_prob_note (s390_emit_jump (is_aligned_label, cond), |
5834 | profile_probability::very_unlikely ()); | |
085261c8 AK |
5835 | |
5836 | expand_binop (Pmode, add_optab, str_idx_reg, | |
5837 | GEN_INT (-16), str_idx_reg, 1, OPTAB_DIRECT); | |
5838 | /* FIXME: len is already zero extended - so avoid the llgcr emitted | |
5839 | here. */ | |
5840 | temp = expand_binop (Pmode, add_optab, str_idx_reg, | |
5841 | convert_to_mode (Pmode, len, 1), | |
5842 | target, 1, OPTAB_DIRECT); | |
5843 | if (temp != target) | |
5844 | emit_move_insn (target, temp); | |
5845 | } | |
5d880bd2 | 5846 | |
859a4c0e AK |
5847 | void |
5848 | s390_expand_vec_movstr (rtx result, rtx dst, rtx src) | |
5849 | { | |
859a4c0e AK |
5850 | rtx temp = gen_reg_rtx (Pmode); |
5851 | rtx src_addr = XEXP (src, 0); | |
5852 | rtx dst_addr = XEXP (dst, 0); | |
5853 | rtx src_addr_reg = gen_reg_rtx (Pmode); | |
5854 | rtx dst_addr_reg = gen_reg_rtx (Pmode); | |
5855 | rtx offset = gen_reg_rtx (Pmode); | |
5856 | rtx vsrc = gen_reg_rtx (V16QImode); | |
5857 | rtx vpos = gen_reg_rtx (V16QImode); | |
5858 | rtx loadlen = gen_reg_rtx (SImode); | |
5859 | rtx gpos_qi = gen_reg_rtx(QImode); | |
5860 | rtx gpos = gen_reg_rtx (SImode); | |
5861 | rtx done_label = gen_label_rtx (); | |
5862 | rtx loop_label = gen_label_rtx (); | |
5863 | rtx exit_label = gen_label_rtx (); | |
5864 | rtx full_label = gen_label_rtx (); | |
5865 | ||
5866 | /* Perform a quick check for string ending on the first up to 16 | |
5867 | bytes and exit early if successful. */ | |
5868 | ||
5869 | emit_insn (gen_vlbb (vsrc, src, GEN_INT (6))); | |
5870 | emit_insn (gen_lcbb (loadlen, src_addr, GEN_INT (6))); | |
5871 | emit_insn (gen_vfenezv16qi (vpos, vsrc, vsrc)); | |
ff03930a | 5872 | emit_insn (gen_vec_extractv16qiqi (gpos_qi, vpos, GEN_INT (7))); |
859a4c0e AK |
5873 | emit_move_insn (gpos, gen_rtx_SUBREG (SImode, gpos_qi, 0)); |
5874 | /* gpos is the byte index if a zero was found and 16 otherwise. | |
5875 | So if it is lower than the loaded bytes we have a hit. */ | |
5876 | emit_cmp_and_jump_insns (gpos, loadlen, GE, NULL_RTX, SImode, 1, | |
5877 | full_label); | |
5878 | emit_insn (gen_vstlv16qi (vsrc, gpos, dst)); | |
5879 | ||
5880 | force_expand_binop (Pmode, add_optab, dst_addr, gpos, result, | |
5881 | 1, OPTAB_DIRECT); | |
5882 | emit_jump (exit_label); | |
5883 | emit_barrier (); | |
5884 | ||
5885 | emit_label (full_label); | |
5886 | LABEL_NUSES (full_label) = 1; | |
5887 | ||
5888 | /* Calculate `offset' so that src + offset points to the last byte | |
5889 | before 16 byte alignment. */ | |
5890 | ||
5891 | /* temp = src_addr & 0xf */ | |
5892 | force_expand_binop (Pmode, and_optab, src_addr, GEN_INT (15), temp, | |
5893 | 1, OPTAB_DIRECT); | |
5894 | ||
5895 | /* offset = 0xf - temp */ | |
5896 | emit_move_insn (offset, GEN_INT (15)); | |
5897 | force_expand_binop (Pmode, sub_optab, offset, temp, offset, | |
5898 | 1, OPTAB_DIRECT); | |
5899 | ||
5900 | /* Store `offset' bytes in the dstination string. The quick check | |
5901 | has loaded at least `offset' bytes into vsrc. */ | |
5902 | ||
5903 | emit_insn (gen_vstlv16qi (vsrc, gen_lowpart (SImode, offset), dst)); | |
5904 | ||
5905 | /* Advance to the next byte to be loaded. */ | |
5906 | force_expand_binop (Pmode, add_optab, offset, const1_rtx, offset, | |
5907 | 1, OPTAB_DIRECT); | |
5908 | ||
5909 | /* Make sure the addresses are single regs which can be used as a | |
5910 | base. */ | |
5911 | emit_move_insn (src_addr_reg, src_addr); | |
5912 | emit_move_insn (dst_addr_reg, dst_addr); | |
5913 | ||
5914 | /* MAIN LOOP */ | |
5915 | ||
5916 | emit_label (loop_label); | |
5917 | LABEL_NUSES (loop_label) = 1; | |
5918 | ||
5919 | emit_move_insn (vsrc, | |
5920 | gen_rtx_MEM (V16QImode, | |
5921 | gen_rtx_PLUS (Pmode, src_addr_reg, offset))); | |
5922 | ||
5923 | emit_insn (gen_vec_vfenesv16qi (vpos, vsrc, vsrc, | |
5924 | GEN_INT (VSTRING_FLAG_ZS | VSTRING_FLAG_CS))); | |
5925 | add_int_reg_note (s390_emit_ccraw_jump (8, EQ, done_label), | |
5fa396ad JH |
5926 | REG_BR_PROB, profile_probability::very_unlikely () |
5927 | .to_reg_br_prob_note ()); | |
859a4c0e AK |
5928 | |
5929 | emit_move_insn (gen_rtx_MEM (V16QImode, | |
5930 | gen_rtx_PLUS (Pmode, dst_addr_reg, offset)), | |
5931 | vsrc); | |
5932 | /* offset += 16 */ | |
5933 | force_expand_binop (Pmode, add_optab, offset, GEN_INT (16), | |
5934 | offset, 1, OPTAB_DIRECT); | |
5935 | ||
5936 | emit_jump (loop_label); | |
5937 | emit_barrier (); | |
5938 | ||
5939 | /* REGULAR EXIT */ | |
5940 | ||
5941 | /* We are done. Add the offset of the zero character to the dst_addr | |
5942 | pointer to get the result. */ | |
5943 | ||
5944 | emit_label (done_label); | |
5945 | LABEL_NUSES (done_label) = 1; | |
5946 | ||
5947 | force_expand_binop (Pmode, add_optab, dst_addr_reg, offset, dst_addr_reg, | |
5948 | 1, OPTAB_DIRECT); | |
5949 | ||
ff03930a | 5950 | emit_insn (gen_vec_extractv16qiqi (gpos_qi, vpos, GEN_INT (7))); |
859a4c0e AK |
5951 | emit_move_insn (gpos, gen_rtx_SUBREG (SImode, gpos_qi, 0)); |
5952 | ||
5953 | emit_insn (gen_vstlv16qi (vsrc, gpos, gen_rtx_MEM (BLKmode, dst_addr_reg))); | |
5954 | ||
5955 | force_expand_binop (Pmode, add_optab, dst_addr_reg, gpos, result, | |
5956 | 1, OPTAB_DIRECT); | |
5957 | ||
5958 | /* EARLY EXIT */ | |
5959 | ||
5960 | emit_label (exit_label); | |
5961 | LABEL_NUSES (exit_label) = 1; | |
5962 | } | |
5963 | ||
5964 | ||
5d880bd2 UW |
5965 | /* Expand conditional increment or decrement using alc/slb instructions. |
5966 | Should generate code setting DST to either SRC or SRC + INCREMENT, | |
5967 | depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1. | |
00bda920 AK |
5968 | Returns true if successful, false otherwise. |
5969 | ||
5970 | That makes it possible to implement some if-constructs without jumps e.g.: | |
5971 | (borrow = CC0 | CC1 and carry = CC2 | CC3) | |
5972 | unsigned int a, b, c; | |
5973 | if (a < b) c++; -> CCU b > a -> CC2; c += carry; | |
5974 | if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow; | |
5975 | if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry; | |
5976 | if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow; | |
5977 | ||
5978 | Checks for EQ and NE with a nonzero value need an additional xor e.g.: | |
5979 | if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry; | |
5980 | if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow; | |
5981 | if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry; | |
5982 | if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */ | |
5d880bd2 UW |
5983 | |
5984 | bool | |
5985 | s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1, | |
5986 | rtx dst, rtx src, rtx increment) | |
5987 | { | |
ef4bddc2 RS |
5988 | machine_mode cmp_mode; |
5989 | machine_mode cc_mode; | |
5d880bd2 UW |
5990 | rtx op_res; |
5991 | rtx insn; | |
5992 | rtvec p; | |
8d933e31 | 5993 | int ret; |
5d880bd2 UW |
5994 | |
5995 | if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode) | |
5996 | && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode)) | |
5997 | cmp_mode = SImode; | |
5998 | else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode) | |
5999 | && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode)) | |
6000 | cmp_mode = DImode; | |
6001 | else | |
6002 | return false; | |
6003 | ||
6004 | /* Try ADD LOGICAL WITH CARRY. */ | |
6005 | if (increment == const1_rtx) | |
6006 | { | |
6007 | /* Determine CC mode to use. */ | |
6008 | if (cmp_code == EQ || cmp_code == NE) | |
6009 | { | |
6010 | if (cmp_op1 != const0_rtx) | |
6011 | { | |
6012 | cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1, | |
6013 | NULL_RTX, 0, OPTAB_WIDEN); | |
6014 | cmp_op1 = const0_rtx; | |
6015 | } | |
6016 | ||
6017 | cmp_code = cmp_code == EQ ? LEU : GTU; | |
6018 | } | |
6019 | ||
6020 | if (cmp_code == LTU || cmp_code == LEU) | |
6021 | { | |
6022 | rtx tem = cmp_op0; | |
6023 | cmp_op0 = cmp_op1; | |
6024 | cmp_op1 = tem; | |
6025 | cmp_code = swap_condition (cmp_code); | |
6026 | } | |
6027 | ||
6028 | switch (cmp_code) | |
6029 | { | |
6030 | case GTU: | |
6031 | cc_mode = CCUmode; | |
6032 | break; | |
6033 | ||
6034 | case GEU: | |
6035 | cc_mode = CCL3mode; | |
6036 | break; | |
6037 | ||
6038 | default: | |
6039 | return false; | |
6040 | } | |
6041 | ||
6042 | /* Emit comparison instruction pattern. */ | |
6043 | if (!register_operand (cmp_op0, cmp_mode)) | |
6044 | cmp_op0 = force_reg (cmp_mode, cmp_op0); | |
6045 | ||
f7df4a84 | 6046 | insn = gen_rtx_SET (gen_rtx_REG (cc_mode, CC_REGNUM), |
5d880bd2 UW |
6047 | gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1)); |
6048 | /* We use insn_invalid_p here to add clobbers if required. */ | |
57ac4c34 | 6049 | ret = insn_invalid_p (emit_insn (insn), false); |
8d933e31 | 6050 | gcc_assert (!ret); |
5d880bd2 UW |
6051 | |
6052 | /* Emit ALC instruction pattern. */ | |
6053 | op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst), | |
6054 | gen_rtx_REG (cc_mode, CC_REGNUM), | |
6055 | const0_rtx); | |
6056 | ||
6057 | if (src != const0_rtx) | |
6058 | { | |
6059 | if (!register_operand (src, GET_MODE (dst))) | |
6060 | src = force_reg (GET_MODE (dst), src); | |
6061 | ||
a94a76a7 UW |
6062 | op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src); |
6063 | op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx); | |
5d880bd2 UW |
6064 | } |
6065 | ||
6066 | p = rtvec_alloc (2); | |
f4aa3848 | 6067 | RTVEC_ELT (p, 0) = |
f7df4a84 | 6068 | gen_rtx_SET (dst, op_res); |
f4aa3848 | 6069 | RTVEC_ELT (p, 1) = |
5d880bd2 UW |
6070 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); |
6071 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
6072 | ||
6073 | return true; | |
6074 | } | |
6075 | ||
6076 | /* Try SUBTRACT LOGICAL WITH BORROW. */ | |
6077 | if (increment == constm1_rtx) | |
6078 | { | |
6079 | /* Determine CC mode to use. */ | |
6080 | if (cmp_code == EQ || cmp_code == NE) | |
6081 | { | |
6082 | if (cmp_op1 != const0_rtx) | |
6083 | { | |
6084 | cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1, | |
6085 | NULL_RTX, 0, OPTAB_WIDEN); | |
6086 | cmp_op1 = const0_rtx; | |
6087 | } | |
6088 | ||
6089 | cmp_code = cmp_code == EQ ? LEU : GTU; | |
6090 | } | |
6091 | ||
6092 | if (cmp_code == GTU || cmp_code == GEU) | |
6093 | { | |
6094 | rtx tem = cmp_op0; | |
6095 | cmp_op0 = cmp_op1; | |
6096 | cmp_op1 = tem; | |
6097 | cmp_code = swap_condition (cmp_code); | |
6098 | } | |
6099 | ||
6100 | switch (cmp_code) | |
6101 | { | |
6102 | case LEU: | |
6103 | cc_mode = CCUmode; | |
6104 | break; | |
6105 | ||
6106 | case LTU: | |
6107 | cc_mode = CCL3mode; | |
6108 | break; | |
6109 | ||
6110 | default: | |
6111 | return false; | |
6112 | } | |
6113 | ||
6114 | /* Emit comparison instruction pattern. */ | |
6115 | if (!register_operand (cmp_op0, cmp_mode)) | |
6116 | cmp_op0 = force_reg (cmp_mode, cmp_op0); | |
6117 | ||
f7df4a84 | 6118 | insn = gen_rtx_SET (gen_rtx_REG (cc_mode, CC_REGNUM), |
5d880bd2 UW |
6119 | gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1)); |
6120 | /* We use insn_invalid_p here to add clobbers if required. */ | |
57ac4c34 | 6121 | ret = insn_invalid_p (emit_insn (insn), false); |
8d933e31 | 6122 | gcc_assert (!ret); |
5d880bd2 UW |
6123 | |
6124 | /* Emit SLB instruction pattern. */ | |
6125 | if (!register_operand (src, GET_MODE (dst))) | |
6126 | src = force_reg (GET_MODE (dst), src); | |
6127 | ||
f4aa3848 AK |
6128 | op_res = gen_rtx_MINUS (GET_MODE (dst), |
6129 | gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx), | |
6130 | gen_rtx_fmt_ee (cmp_code, GET_MODE (dst), | |
6131 | gen_rtx_REG (cc_mode, CC_REGNUM), | |
5d880bd2 UW |
6132 | const0_rtx)); |
6133 | p = rtvec_alloc (2); | |
f4aa3848 | 6134 | RTVEC_ELT (p, 0) = |
f7df4a84 | 6135 | gen_rtx_SET (dst, op_res); |
f4aa3848 | 6136 | RTVEC_ELT (p, 1) = |
5d880bd2 UW |
6137 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); |
6138 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
6139 | ||
6140 | return true; | |
6141 | } | |
6142 | ||
6143 | return false; | |
6144 | } | |
6145 | ||
963fc8d0 | 6146 | /* Expand code for the insv template. Return true if successful. */ |
6fa05db6 | 6147 | |
963fc8d0 | 6148 | bool |
6fa05db6 AS |
6149 | s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src) |
6150 | { | |
6151 | int bitsize = INTVAL (op1); | |
6152 | int bitpos = INTVAL (op2); | |
ef4bddc2 RS |
6153 | machine_mode mode = GET_MODE (dest); |
6154 | machine_mode smode; | |
78ce265b RH |
6155 | int smode_bsize, mode_bsize; |
6156 | rtx op, clobber; | |
6fa05db6 | 6157 | |
a9d46e32 | 6158 | if (bitsize + bitpos > GET_MODE_BITSIZE (mode)) |
03ed99a8 AK |
6159 | return false; |
6160 | ||
78ce265b RH |
6161 | /* Generate INSERT IMMEDIATE (IILL et al). */ |
6162 | /* (set (ze (reg)) (const_int)). */ | |
6163 | if (TARGET_ZARCH | |
6164 | && register_operand (dest, word_mode) | |
6165 | && (bitpos % 16) == 0 | |
6166 | && (bitsize % 16) == 0 | |
6167 | && const_int_operand (src, VOIDmode)) | |
963fc8d0 | 6168 | { |
78ce265b RH |
6169 | HOST_WIDE_INT val = INTVAL (src); |
6170 | int regpos = bitpos + bitsize; | |
963fc8d0 | 6171 | |
78ce265b RH |
6172 | while (regpos > bitpos) |
6173 | { | |
ef4bddc2 | 6174 | machine_mode putmode; |
78ce265b RH |
6175 | int putsize; |
6176 | ||
6177 | if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32)) | |
6178 | putmode = SImode; | |
6179 | else | |
6180 | putmode = HImode; | |
963fc8d0 | 6181 | |
78ce265b RH |
6182 | putsize = GET_MODE_BITSIZE (putmode); |
6183 | regpos -= putsize; | |
6184 | emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, | |
6185 | GEN_INT (putsize), | |
6186 | GEN_INT (regpos)), | |
6187 | gen_int_mode (val, putmode)); | |
6188 | val >>= putsize; | |
6189 | } | |
6190 | gcc_assert (regpos == bitpos); | |
963fc8d0 AK |
6191 | return true; |
6192 | } | |
6193 | ||
f67f4dff | 6194 | smode = smallest_int_mode_for_size (bitsize); |
78ce265b RH |
6195 | smode_bsize = GET_MODE_BITSIZE (smode); |
6196 | mode_bsize = GET_MODE_BITSIZE (mode); | |
6fa05db6 | 6197 | |
78ce265b | 6198 | /* Generate STORE CHARACTERS UNDER MASK (STCM et al). */ |
6fa05db6 | 6199 | if (bitpos == 0 |
78ce265b RH |
6200 | && (bitsize % BITS_PER_UNIT) == 0 |
6201 | && MEM_P (dest) | |
6fa05db6 AS |
6202 | && (register_operand (src, word_mode) |
6203 | || const_int_operand (src, VOIDmode))) | |
6204 | { | |
6205 | /* Emit standard pattern if possible. */ | |
78ce265b RH |
6206 | if (smode_bsize == bitsize) |
6207 | { | |
6208 | emit_move_insn (adjust_address (dest, smode, 0), | |
6209 | gen_lowpart (smode, src)); | |
6210 | return true; | |
6211 | } | |
6fa05db6 AS |
6212 | |
6213 | /* (set (ze (mem)) (const_int)). */ | |
6214 | else if (const_int_operand (src, VOIDmode)) | |
6215 | { | |
6216 | int size = bitsize / BITS_PER_UNIT; | |
78ce265b RH |
6217 | rtx src_mem = adjust_address (force_const_mem (word_mode, src), |
6218 | BLKmode, | |
6219 | UNITS_PER_WORD - size); | |
6fa05db6 AS |
6220 | |
6221 | dest = adjust_address (dest, BLKmode, 0); | |
f5541398 | 6222 | set_mem_size (dest, size); |
6fa05db6 | 6223 | s390_expand_movmem (dest, src_mem, GEN_INT (size)); |
78ce265b | 6224 | return true; |
6fa05db6 | 6225 | } |
f4aa3848 | 6226 | |
6fa05db6 AS |
6227 | /* (set (ze (mem)) (reg)). */ |
6228 | else if (register_operand (src, word_mode)) | |
6229 | { | |
78ce265b | 6230 | if (bitsize <= 32) |
6fa05db6 AS |
6231 | emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1, |
6232 | const0_rtx), src); | |
6233 | else | |
6234 | { | |
6235 | /* Emit st,stcmh sequence. */ | |
78ce265b | 6236 | int stcmh_width = bitsize - 32; |
6fa05db6 AS |
6237 | int size = stcmh_width / BITS_PER_UNIT; |
6238 | ||
f4aa3848 | 6239 | emit_move_insn (adjust_address (dest, SImode, size), |
6fa05db6 | 6240 | gen_lowpart (SImode, src)); |
f5541398 | 6241 | set_mem_size (dest, size); |
78ce265b RH |
6242 | emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, |
6243 | GEN_INT (stcmh_width), | |
6244 | const0_rtx), | |
6245 | gen_rtx_LSHIFTRT (word_mode, src, GEN_INT (32))); | |
6fa05db6 | 6246 | } |
78ce265b | 6247 | return true; |
6fa05db6 | 6248 | } |
78ce265b | 6249 | } |
6fa05db6 | 6250 | |
78ce265b RH |
6251 | /* Generate INSERT CHARACTERS UNDER MASK (IC, ICM et al). */ |
6252 | if ((bitpos % BITS_PER_UNIT) == 0 | |
6253 | && (bitsize % BITS_PER_UNIT) == 0 | |
6254 | && (bitpos & 32) == ((bitpos + bitsize - 1) & 32) | |
6255 | && MEM_P (src) | |
6256 | && (mode == DImode || mode == SImode) | |
6257 | && register_operand (dest, mode)) | |
6258 | { | |
6259 | /* Emit a strict_low_part pattern if possible. */ | |
6260 | if (smode_bsize == bitsize && bitpos == mode_bsize - smode_bsize) | |
6261 | { | |
6262 | op = gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (smode, dest)); | |
f7df4a84 | 6263 | op = gen_rtx_SET (op, gen_lowpart (smode, src)); |
78ce265b RH |
6264 | clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); |
6265 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber))); | |
6266 | return true; | |
6267 | } | |
6268 | ||
6269 | /* ??? There are more powerful versions of ICM that are not | |
6270 | completely represented in the md file. */ | |
6fa05db6 AS |
6271 | } |
6272 | ||
78ce265b RH |
6273 | /* For z10, generate ROTATE THEN INSERT SELECTED BITS (RISBG et al). */ |
6274 | if (TARGET_Z10 && (mode == DImode || mode == SImode)) | |
6fa05db6 | 6275 | { |
ef4bddc2 | 6276 | machine_mode mode_s = GET_MODE (src); |
6fa05db6 | 6277 | |
e7067fcd | 6278 | if (CONSTANT_P (src)) |
6fa05db6 | 6279 | { |
3d44ff99 AK |
6280 | /* For constant zero values the representation with AND |
6281 | appears to be folded in more situations than the (set | |
6282 | (zero_extract) ...). | |
6283 | We only do this when the start and end of the bitfield | |
6284 | remain in the same SImode chunk. That way nihf or nilf | |
6285 | can be used. | |
6286 | The AND patterns might still generate a risbg for this. */ | |
6287 | if (src == const0_rtx && bitpos / 32 == (bitpos + bitsize - 1) / 32) | |
6288 | return false; | |
6289 | else | |
6290 | src = force_reg (mode, src); | |
78ce265b RH |
6291 | } |
6292 | else if (mode_s != mode) | |
6293 | { | |
6294 | gcc_assert (GET_MODE_BITSIZE (mode_s) >= bitsize); | |
6295 | src = force_reg (mode_s, src); | |
6296 | src = gen_lowpart (mode, src); | |
6297 | } | |
6fa05db6 | 6298 | |
0d8e4dac | 6299 | op = gen_rtx_ZERO_EXTRACT (mode, dest, op1, op2), |
f7df4a84 | 6300 | op = gen_rtx_SET (op, src); |
22ac2c2f AK |
6301 | |
6302 | if (!TARGET_ZEC12) | |
6303 | { | |
6304 | clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); | |
6305 | op = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)); | |
6306 | } | |
6307 | emit_insn (op); | |
6fa05db6 | 6308 | |
6fa05db6 AS |
6309 | return true; |
6310 | } | |
6311 | ||
6312 | return false; | |
6313 | } | |
5d880bd2 | 6314 | |
45d18331 AS |
6315 | /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a |
6316 | register that holds VAL of mode MODE shifted by COUNT bits. */ | |
3093f076 AS |
6317 | |
6318 | static inline rtx | |
ef4bddc2 | 6319 | s390_expand_mask_and_shift (rtx val, machine_mode mode, rtx count) |
3093f076 AS |
6320 | { |
6321 | val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)), | |
6322 | NULL_RTX, 1, OPTAB_DIRECT); | |
f4aa3848 | 6323 | return expand_simple_binop (SImode, ASHIFT, val, count, |
3093f076 AS |
6324 | NULL_RTX, 1, OPTAB_DIRECT); |
6325 | } | |
6326 | ||
085261c8 AK |
6327 | /* Generate a vector comparison COND of CMP_OP1 and CMP_OP2 and store |
6328 | the result in TARGET. */ | |
6329 | ||
6330 | void | |
6331 | s390_expand_vec_compare (rtx target, enum rtx_code cond, | |
6332 | rtx cmp_op1, rtx cmp_op2) | |
6333 | { | |
6334 | machine_mode mode = GET_MODE (target); | |
6335 | bool neg_p = false, swap_p = false; | |
6336 | rtx tmp; | |
6337 | ||
2de2b3f9 | 6338 | if (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_VECTOR_FLOAT) |
085261c8 AK |
6339 | { |
6340 | switch (cond) | |
6341 | { | |
6342 | /* NE a != b -> !(a == b) */ | |
6343 | case NE: cond = EQ; neg_p = true; break; | |
6344 | /* UNGT a u> b -> !(b >= a) */ | |
6345 | case UNGT: cond = GE; neg_p = true; swap_p = true; break; | |
6346 | /* UNGE a u>= b -> !(b > a) */ | |
6347 | case UNGE: cond = GT; neg_p = true; swap_p = true; break; | |
6348 | /* LE: a <= b -> b >= a */ | |
6349 | case LE: cond = GE; swap_p = true; break; | |
6350 | /* UNLE: a u<= b -> !(a > b) */ | |
6351 | case UNLE: cond = GT; neg_p = true; break; | |
6352 | /* LT: a < b -> b > a */ | |
6353 | case LT: cond = GT; swap_p = true; break; | |
6354 | /* UNLT: a u< b -> !(a >= b) */ | |
6355 | case UNLT: cond = GE; neg_p = true; break; | |
6356 | case UNEQ: | |
6357 | emit_insn (gen_vec_cmpuneqv2df (target, cmp_op1, cmp_op2)); | |
6358 | return; | |
6359 | case LTGT: | |
6360 | emit_insn (gen_vec_cmpltgtv2df (target, cmp_op1, cmp_op2)); | |
6361 | return; | |
6362 | case ORDERED: | |
6363 | emit_insn (gen_vec_orderedv2df (target, cmp_op1, cmp_op2)); | |
6364 | return; | |
6365 | case UNORDERED: | |
6366 | emit_insn (gen_vec_unorderedv2df (target, cmp_op1, cmp_op2)); | |
6367 | return; | |
6368 | default: break; | |
6369 | } | |
6370 | } | |
6371 | else | |
6372 | { | |
6373 | switch (cond) | |
6374 | { | |
6375 | /* NE: a != b -> !(a == b) */ | |
6376 | case NE: cond = EQ; neg_p = true; break; | |
6377 | /* GE: a >= b -> !(b > a) */ | |
6378 | case GE: cond = GT; neg_p = true; swap_p = true; break; | |
6379 | /* GEU: a >= b -> !(b > a) */ | |
6380 | case GEU: cond = GTU; neg_p = true; swap_p = true; break; | |
6381 | /* LE: a <= b -> !(a > b) */ | |
6382 | case LE: cond = GT; neg_p = true; break; | |
6383 | /* LEU: a <= b -> !(a > b) */ | |
6384 | case LEU: cond = GTU; neg_p = true; break; | |
6385 | /* LT: a < b -> b > a */ | |
6386 | case LT: cond = GT; swap_p = true; break; | |
6387 | /* LTU: a < b -> b > a */ | |
6388 | case LTU: cond = GTU; swap_p = true; break; | |
6389 | default: break; | |
6390 | } | |
6391 | } | |
6392 | ||
6393 | if (swap_p) | |
6394 | { | |
6395 | tmp = cmp_op1; cmp_op1 = cmp_op2; cmp_op2 = tmp; | |
6396 | } | |
6397 | ||
6398 | emit_insn (gen_rtx_SET (target, gen_rtx_fmt_ee (cond, | |
6399 | mode, | |
6400 | cmp_op1, cmp_op2))); | |
6401 | if (neg_p) | |
6402 | emit_insn (gen_rtx_SET (target, gen_rtx_NOT (mode, target))); | |
6403 | } | |
6404 | ||
3af82a61 AK |
6405 | /* Expand the comparison CODE of CMP1 and CMP2 and copy 1 or 0 into |
6406 | TARGET if either all (ALL_P is true) or any (ALL_P is false) of the | |
a6a2b532 AK |
6407 | elements in CMP1 and CMP2 fulfill the comparison. |
6408 | This function is only used to emit patterns for the vx builtins and | |
6409 | therefore only handles comparison codes required by the | |
6410 | builtins. */ | |
3af82a61 AK |
6411 | void |
6412 | s390_expand_vec_compare_cc (rtx target, enum rtx_code code, | |
6413 | rtx cmp1, rtx cmp2, bool all_p) | |
6414 | { | |
a6a2b532 | 6415 | machine_mode cc_producer_mode, cc_consumer_mode, scratch_mode; |
3af82a61 AK |
6416 | rtx tmp_reg = gen_reg_rtx (SImode); |
6417 | bool swap_p = false; | |
6418 | ||
6419 | if (GET_MODE_CLASS (GET_MODE (cmp1)) == MODE_VECTOR_INT) | |
6420 | { | |
6421 | switch (code) | |
6422 | { | |
a6a2b532 AK |
6423 | case EQ: |
6424 | case NE: | |
6425 | cc_producer_mode = CCVEQmode; | |
6426 | break; | |
6427 | case GE: | |
6428 | case LT: | |
6429 | code = swap_condition (code); | |
6430 | swap_p = true; | |
6431 | /* fallthrough */ | |
6432 | case GT: | |
6433 | case LE: | |
6434 | cc_producer_mode = CCVIHmode; | |
6435 | break; | |
6436 | case GEU: | |
6437 | case LTU: | |
6438 | code = swap_condition (code); | |
6439 | swap_p = true; | |
6440 | /* fallthrough */ | |
6441 | case GTU: | |
6442 | case LEU: | |
6443 | cc_producer_mode = CCVIHUmode; | |
6444 | break; | |
6445 | default: | |
6446 | gcc_unreachable (); | |
3af82a61 | 6447 | } |
a6a2b532 | 6448 | |
3af82a61 | 6449 | scratch_mode = GET_MODE (cmp1); |
a6a2b532 AK |
6450 | /* These codes represent inverted CC interpretations. Inverting |
6451 | an ALL CC mode results in an ANY CC mode and the other way | |
6452 | around. Invert the all_p flag here to compensate for | |
6453 | that. */ | |
6454 | if (code == NE || code == LE || code == LEU) | |
6455 | all_p = !all_p; | |
6456 | ||
6457 | cc_consumer_mode = all_p ? CCVIALLmode : CCVIANYmode; | |
3af82a61 | 6458 | } |
a6a2b532 | 6459 | else if (GET_MODE_CLASS (GET_MODE (cmp1)) == MODE_VECTOR_FLOAT) |
3af82a61 | 6460 | { |
a6a2b532 AK |
6461 | bool inv_p = false; |
6462 | ||
3af82a61 AK |
6463 | switch (code) |
6464 | { | |
a6a2b532 AK |
6465 | case EQ: cc_producer_mode = CCVEQmode; break; |
6466 | case NE: cc_producer_mode = CCVEQmode; inv_p = true; break; | |
6467 | case GT: cc_producer_mode = CCVFHmode; break; | |
6468 | case GE: cc_producer_mode = CCVFHEmode; break; | |
6469 | case UNLE: cc_producer_mode = CCVFHmode; inv_p = true; break; | |
6470 | case UNLT: cc_producer_mode = CCVFHEmode; inv_p = true; break; | |
6471 | case LT: cc_producer_mode = CCVFHmode; code = GT; swap_p = true; break; | |
6472 | case LE: cc_producer_mode = CCVFHEmode; code = GE; swap_p = true; break; | |
3af82a61 AK |
6473 | default: gcc_unreachable (); |
6474 | } | |
ddc203a7 | 6475 | scratch_mode = mode_for_int_vector (GET_MODE (cmp1)).require (); |
a6a2b532 AK |
6476 | |
6477 | if (inv_p) | |
6478 | all_p = !all_p; | |
6479 | ||
6480 | cc_consumer_mode = all_p ? CCVFALLmode : CCVFANYmode; | |
3af82a61 AK |
6481 | } |
6482 | else | |
6483 | gcc_unreachable (); | |
6484 | ||
3af82a61 AK |
6485 | if (swap_p) |
6486 | { | |
6487 | rtx tmp = cmp2; | |
6488 | cmp2 = cmp1; | |
6489 | cmp1 = tmp; | |
6490 | } | |
6491 | ||
6492 | emit_insn (gen_rtx_PARALLEL (VOIDmode, | |
6493 | gen_rtvec (2, gen_rtx_SET ( | |
a6a2b532 AK |
6494 | gen_rtx_REG (cc_producer_mode, CC_REGNUM), |
6495 | gen_rtx_COMPARE (cc_producer_mode, cmp1, cmp2)), | |
3af82a61 AK |
6496 | gen_rtx_CLOBBER (VOIDmode, |
6497 | gen_rtx_SCRATCH (scratch_mode))))); | |
6498 | emit_move_insn (target, const0_rtx); | |
6499 | emit_move_insn (tmp_reg, const1_rtx); | |
6500 | ||
6501 | emit_move_insn (target, | |
6502 | gen_rtx_IF_THEN_ELSE (SImode, | |
a6a2b532 AK |
6503 | gen_rtx_fmt_ee (code, VOIDmode, |
6504 | gen_rtx_REG (cc_consumer_mode, CC_REGNUM), | |
3af82a61 | 6505 | const0_rtx), |
a6a2b532 | 6506 | tmp_reg, target)); |
3af82a61 AK |
6507 | } |
6508 | ||
eca98038 AK |
6509 | /* Invert the comparison CODE applied to a CC mode. This is only safe |
6510 | if we know whether there result was created by a floating point | |
6511 | compare or not. For the CCV modes this is encoded as part of the | |
6512 | mode. */ | |
6513 | enum rtx_code | |
6514 | s390_reverse_condition (machine_mode mode, enum rtx_code code) | |
6515 | { | |
6516 | /* Reversal of FP compares takes care -- an ordered compare | |
6517 | becomes an unordered compare and vice versa. */ | |
6518 | if (mode == CCVFALLmode || mode == CCVFANYmode) | |
6519 | return reverse_condition_maybe_unordered (code); | |
6520 | else if (mode == CCVIALLmode || mode == CCVIANYmode) | |
6521 | return reverse_condition (code); | |
6522 | else | |
6523 | gcc_unreachable (); | |
6524 | } | |
6525 | ||
085261c8 AK |
6526 | /* Generate a vector comparison expression loading either elements of |
6527 | THEN or ELS into TARGET depending on the comparison COND of CMP_OP1 | |
6528 | and CMP_OP2. */ | |
6529 | ||
6530 | void | |
6531 | s390_expand_vcond (rtx target, rtx then, rtx els, | |
6532 | enum rtx_code cond, rtx cmp_op1, rtx cmp_op2) | |
6533 | { | |
6534 | rtx tmp; | |
6535 | machine_mode result_mode; | |
6536 | rtx result_target; | |
6537 | ||
d958ae79 RD |
6538 | machine_mode target_mode = GET_MODE (target); |
6539 | machine_mode cmp_mode = GET_MODE (cmp_op1); | |
6540 | rtx op = (cond == LT) ? els : then; | |
6541 | ||
6542 | /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31 | |
6543 | and x < 0 ? 1 : 0 into (unsigned) x >> 31. Likewise | |
6544 | for short and byte (x >> 15 and x >> 7 respectively). */ | |
6545 | if ((cond == LT || cond == GE) | |
6546 | && target_mode == cmp_mode | |
6547 | && cmp_op2 == CONST0_RTX (cmp_mode) | |
6548 | && op == CONST0_RTX (target_mode) | |
6549 | && s390_vector_mode_supported_p (target_mode) | |
6550 | && GET_MODE_CLASS (target_mode) == MODE_VECTOR_INT) | |
6551 | { | |
6552 | rtx negop = (cond == LT) ? then : els; | |
6553 | ||
6554 | int shift = GET_MODE_BITSIZE (GET_MODE_INNER (target_mode)) - 1; | |
6555 | ||
6556 | /* if x < 0 ? 1 : 0 or if x >= 0 ? 0 : 1 */ | |
6557 | if (negop == CONST1_RTX (target_mode)) | |
6558 | { | |
6559 | rtx res = expand_simple_binop (cmp_mode, LSHIFTRT, cmp_op1, | |
6560 | GEN_INT (shift), target, | |
6561 | 1, OPTAB_DIRECT); | |
6562 | if (res != target) | |
6563 | emit_move_insn (target, res); | |
6564 | return; | |
6565 | } | |
6566 | ||
6567 | /* if x < 0 ? -1 : 0 or if x >= 0 ? 0 : -1 */ | |
916c0f6a | 6568 | else if (all_ones_operand (negop, target_mode)) |
d958ae79 RD |
6569 | { |
6570 | rtx res = expand_simple_binop (cmp_mode, ASHIFTRT, cmp_op1, | |
6571 | GEN_INT (shift), target, | |
6572 | 0, OPTAB_DIRECT); | |
6573 | if (res != target) | |
6574 | emit_move_insn (target, res); | |
6575 | return; | |
6576 | } | |
6577 | } | |
6578 | ||
085261c8 AK |
6579 | /* We always use an integral type vector to hold the comparison |
6580 | result. */ | |
ddc203a7 | 6581 | result_mode = mode_for_int_vector (cmp_mode).require (); |
085261c8 AK |
6582 | result_target = gen_reg_rtx (result_mode); |
6583 | ||
d958ae79 RD |
6584 | /* We allow vector immediates as comparison operands that |
6585 | can be handled by the optimization above but not by the | |
6586 | following code. Hence, force them into registers here. */ | |
085261c8 | 6587 | if (!REG_P (cmp_op1)) |
d0a859e6 | 6588 | cmp_op1 = force_reg (GET_MODE (cmp_op1), cmp_op1); |
085261c8 AK |
6589 | |
6590 | if (!REG_P (cmp_op2)) | |
d0a859e6 | 6591 | cmp_op2 = force_reg (GET_MODE (cmp_op2), cmp_op2); |
085261c8 AK |
6592 | |
6593 | s390_expand_vec_compare (result_target, cond, | |
6594 | cmp_op1, cmp_op2); | |
6595 | ||
6596 | /* If the results are supposed to be either -1 or 0 we are done | |
6597 | since this is what our compare instructions generate anyway. */ | |
916c0f6a | 6598 | if (all_ones_operand (then, GET_MODE (then)) |
085261c8 AK |
6599 | && const0_operand (els, GET_MODE (els))) |
6600 | { | |
d958ae79 | 6601 | emit_move_insn (target, gen_rtx_SUBREG (target_mode, |
085261c8 AK |
6602 | result_target, 0)); |
6603 | return; | |
6604 | } | |
6605 | ||
6606 | /* Otherwise we will do a vsel afterwards. */ | |
6607 | /* This gets triggered e.g. | |
6608 | with gcc.c-torture/compile/pr53410-1.c */ | |
6609 | if (!REG_P (then)) | |
d958ae79 | 6610 | then = force_reg (target_mode, then); |
085261c8 AK |
6611 | |
6612 | if (!REG_P (els)) | |
d958ae79 | 6613 | els = force_reg (target_mode, els); |
085261c8 AK |
6614 | |
6615 | tmp = gen_rtx_fmt_ee (EQ, VOIDmode, | |
6616 | result_target, | |
6617 | CONST0_RTX (result_mode)); | |
6618 | ||
6619 | /* We compared the result against zero above so we have to swap then | |
6620 | and els here. */ | |
d958ae79 | 6621 | tmp = gen_rtx_IF_THEN_ELSE (target_mode, tmp, els, then); |
085261c8 | 6622 | |
d958ae79 | 6623 | gcc_assert (target_mode == GET_MODE (then)); |
085261c8 AK |
6624 | emit_insn (gen_rtx_SET (target, tmp)); |
6625 | } | |
6626 | ||
6627 | /* Emit the RTX necessary to initialize the vector TARGET with values | |
6628 | in VALS. */ | |
6629 | void | |
6630 | s390_expand_vec_init (rtx target, rtx vals) | |
6631 | { | |
6632 | machine_mode mode = GET_MODE (target); | |
6633 | machine_mode inner_mode = GET_MODE_INNER (mode); | |
6634 | int n_elts = GET_MODE_NUNITS (mode); | |
6635 | bool all_same = true, all_regs = true, all_const_int = true; | |
6636 | rtx x; | |
6637 | int i; | |
6638 | ||
6639 | for (i = 0; i < n_elts; ++i) | |
6640 | { | |
6641 | x = XVECEXP (vals, 0, i); | |
6642 | ||
6643 | if (!CONST_INT_P (x)) | |
6644 | all_const_int = false; | |
6645 | ||
6646 | if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0))) | |
6647 | all_same = false; | |
6648 | ||
6649 | if (!REG_P (x)) | |
6650 | all_regs = false; | |
6651 | } | |
6652 | ||
6653 | /* Use vector gen mask or vector gen byte mask if possible. */ | |
6654 | if (all_same && all_const_int | |
6655 | && (XVECEXP (vals, 0, 0) == const0_rtx | |
6656 | || s390_contiguous_bitmask_vector_p (XVECEXP (vals, 0, 0), | |
6657 | NULL, NULL) | |
6658 | || s390_bytemask_vector_p (XVECEXP (vals, 0, 0), NULL))) | |
6659 | { | |
6660 | emit_insn (gen_rtx_SET (target, | |
6661 | gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)))); | |
6662 | return; | |
6663 | } | |
6664 | ||
6665 | if (all_same) | |
6666 | { | |
6667 | emit_insn (gen_rtx_SET (target, | |
6668 | gen_rtx_VEC_DUPLICATE (mode, | |
6669 | XVECEXP (vals, 0, 0)))); | |
6670 | return; | |
6671 | } | |
6672 | ||
a602f985 AK |
6673 | if (all_regs |
6674 | && REG_P (target) | |
6675 | && n_elts == 2 | |
6676 | && GET_MODE_SIZE (inner_mode) == 8) | |
085261c8 AK |
6677 | { |
6678 | /* Use vector load pair. */ | |
6679 | emit_insn (gen_rtx_SET (target, | |
6680 | gen_rtx_VEC_CONCAT (mode, | |
6681 | XVECEXP (vals, 0, 0), | |
6682 | XVECEXP (vals, 0, 1)))); | |
6683 | return; | |
6684 | } | |
72612e4e AK |
6685 | |
6686 | /* Use vector load logical element and zero. */ | |
6687 | if (TARGET_VXE && (mode == V4SImode || mode == V4SFmode)) | |
6688 | { | |
6689 | bool found = true; | |
6690 | ||
6691 | x = XVECEXP (vals, 0, 0); | |
6692 | if (memory_operand (x, inner_mode)) | |
6693 | { | |
6694 | for (i = 1; i < n_elts; ++i) | |
6695 | found = found && XVECEXP (vals, 0, i) == const0_rtx; | |
6696 | ||
6697 | if (found) | |
6698 | { | |
6699 | machine_mode half_mode = (inner_mode == SFmode | |
6700 | ? V2SFmode : V2SImode); | |
6701 | emit_insn (gen_rtx_SET (target, | |
6702 | gen_rtx_VEC_CONCAT (mode, | |
6703 | gen_rtx_VEC_CONCAT (half_mode, | |
6704 | x, | |
6705 | const0_rtx), | |
6706 | gen_rtx_VEC_CONCAT (half_mode, | |
6707 | const0_rtx, | |
6708 | const0_rtx)))); | |
6709 | return; | |
6710 | } | |
6711 | } | |
6712 | } | |
085261c8 AK |
6713 | |
6714 | /* We are about to set the vector elements one by one. Zero out the | |
6715 | full register first in order to help the data flow framework to | |
6716 | detect it as full VR set. */ | |
6717 | emit_insn (gen_rtx_SET (target, CONST0_RTX (mode))); | |
6718 | ||
6719 | /* Unfortunately the vec_init expander is not allowed to fail. So | |
6720 | we have to implement the fallback ourselves. */ | |
6721 | for (i = 0; i < n_elts; i++) | |
a07189f4 AK |
6722 | { |
6723 | rtx elem = XVECEXP (vals, 0, i); | |
6724 | if (!general_operand (elem, GET_MODE (elem))) | |
6725 | elem = force_reg (inner_mode, elem); | |
6726 | ||
6727 | emit_insn (gen_rtx_SET (target, | |
6728 | gen_rtx_UNSPEC (mode, | |
6729 | gen_rtvec (3, elem, | |
6730 | GEN_INT (i), target), | |
6731 | UNSPEC_VEC_SET))); | |
6732 | } | |
085261c8 AK |
6733 | } |
6734 | ||
3093f076 | 6735 | /* Structure to hold the initial parameters for a compare_and_swap operation |
f4aa3848 | 6736 | in HImode and QImode. */ |
3093f076 AS |
6737 | |
6738 | struct alignment_context | |
6739 | { | |
f4aa3848 | 6740 | rtx memsi; /* SI aligned memory location. */ |
3093f076 AS |
6741 | rtx shift; /* Bit offset with regard to lsb. */ |
6742 | rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */ | |
6743 | rtx modemaski; /* ~modemask */ | |
6416ae7f | 6744 | bool aligned; /* True if memory is aligned, false else. */ |
3093f076 AS |
6745 | }; |
6746 | ||
45d18331 AS |
6747 | /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize |
6748 | structure AC for transparent simplifying, if the memory alignment is known | |
6749 | to be at least 32bit. MEM is the memory location for the actual operation | |
6750 | and MODE its mode. */ | |
3093f076 AS |
6751 | |
6752 | static void | |
6753 | init_alignment_context (struct alignment_context *ac, rtx mem, | |
ef4bddc2 | 6754 | machine_mode mode) |
3093f076 AS |
6755 | { |
6756 | ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode)); | |
6757 | ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode)); | |
6758 | ||
6759 | if (ac->aligned) | |
6760 | ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */ | |
6761 | else | |
6762 | { | |
6763 | /* Alignment is unknown. */ | |
6764 | rtx byteoffset, addr, align; | |
6765 | ||
6766 | /* Force the address into a register. */ | |
6767 | addr = force_reg (Pmode, XEXP (mem, 0)); | |
6768 | ||
6769 | /* Align it to SImode. */ | |
6770 | align = expand_simple_binop (Pmode, AND, addr, | |
6771 | GEN_INT (-GET_MODE_SIZE (SImode)), | |
6772 | NULL_RTX, 1, OPTAB_DIRECT); | |
6773 | /* Generate MEM. */ | |
6774 | ac->memsi = gen_rtx_MEM (SImode, align); | |
6775 | MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem); | |
44d64274 | 6776 | set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER); |
3093f076 AS |
6777 | set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode)); |
6778 | ||
6779 | /* Calculate shiftcount. */ | |
6780 | byteoffset = expand_simple_binop (Pmode, AND, addr, | |
6781 | GEN_INT (GET_MODE_SIZE (SImode) - 1), | |
6782 | NULL_RTX, 1, OPTAB_DIRECT); | |
6783 | /* As we already have some offset, evaluate the remaining distance. */ | |
6784 | ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset, | |
6785 | NULL_RTX, 1, OPTAB_DIRECT); | |
3093f076 | 6786 | } |
78ce265b | 6787 | |
3093f076 | 6788 | /* Shift is the byte count, but we need the bitcount. */ |
78ce265b RH |
6789 | ac->shift = expand_simple_binop (SImode, ASHIFT, ac->shift, GEN_INT (3), |
6790 | NULL_RTX, 1, OPTAB_DIRECT); | |
6791 | ||
3093f076 | 6792 | /* Calculate masks. */ |
f4aa3848 | 6793 | ac->modemask = expand_simple_binop (SImode, ASHIFT, |
78ce265b RH |
6794 | GEN_INT (GET_MODE_MASK (mode)), |
6795 | ac->shift, NULL_RTX, 1, OPTAB_DIRECT); | |
6796 | ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, | |
6797 | NULL_RTX, 1); | |
6798 | } | |
6799 | ||
6800 | /* A subroutine of s390_expand_cs_hqi. Insert INS into VAL. If possible, | |
6801 | use a single insv insn into SEQ2. Otherwise, put prep insns in SEQ1 and | |
6802 | perform the merge in SEQ2. */ | |
6803 | ||
6804 | static rtx | |
6805 | s390_two_part_insv (struct alignment_context *ac, rtx *seq1, rtx *seq2, | |
ef4bddc2 | 6806 | machine_mode mode, rtx val, rtx ins) |
78ce265b RH |
6807 | { |
6808 | rtx tmp; | |
6809 | ||
6810 | if (ac->aligned) | |
6811 | { | |
6812 | start_sequence (); | |
6813 | tmp = copy_to_mode_reg (SImode, val); | |
6814 | if (s390_expand_insv (tmp, GEN_INT (GET_MODE_BITSIZE (mode)), | |
6815 | const0_rtx, ins)) | |
6816 | { | |
6817 | *seq1 = NULL; | |
6818 | *seq2 = get_insns (); | |
6819 | end_sequence (); | |
6820 | return tmp; | |
6821 | } | |
6822 | end_sequence (); | |
6823 | } | |
6824 | ||
6825 | /* Failed to use insv. Generate a two part shift and mask. */ | |
6826 | start_sequence (); | |
6827 | tmp = s390_expand_mask_and_shift (ins, mode, ac->shift); | |
6828 | *seq1 = get_insns (); | |
6829 | end_sequence (); | |
6830 | ||
6831 | start_sequence (); | |
6832 | tmp = expand_simple_binop (SImode, IOR, tmp, val, NULL_RTX, 1, OPTAB_DIRECT); | |
6833 | *seq2 = get_insns (); | |
6834 | end_sequence (); | |
6835 | ||
6836 | return tmp; | |
3093f076 AS |
6837 | } |
6838 | ||
6839 | /* Expand an atomic compare and swap operation for HImode and QImode. MEM is | |
78ce265b RH |
6840 | the memory location, CMP the old value to compare MEM with and NEW_RTX the |
6841 | value to set if CMP == MEM. */ | |
3093f076 | 6842 | |
03db9ab5 | 6843 | static void |
ef4bddc2 | 6844 | s390_expand_cs_hqi (machine_mode mode, rtx btarget, rtx vtarget, rtx mem, |
78ce265b | 6845 | rtx cmp, rtx new_rtx, bool is_weak) |
3093f076 AS |
6846 | { |
6847 | struct alignment_context ac; | |
4e1ffb63 | 6848 | rtx cmpv, newv, val, cc, seq0, seq1, seq2, seq3; |
3093f076 | 6849 | rtx res = gen_reg_rtx (SImode); |
19f8b229 | 6850 | rtx_code_label *csloop = NULL, *csend = NULL; |
3093f076 | 6851 | |
3093f076 AS |
6852 | gcc_assert (MEM_P (mem)); |
6853 | ||
6854 | init_alignment_context (&ac, mem, mode); | |
6855 | ||
3093f076 AS |
6856 | /* Load full word. Subsequent loads are performed by CS. */ |
6857 | val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski, | |
6858 | NULL_RTX, 1, OPTAB_DIRECT); | |
6859 | ||
78ce265b RH |
6860 | /* Prepare insertions of cmp and new_rtx into the loaded value. When |
6861 | possible, we try to use insv to make this happen efficiently. If | |
6862 | that fails we'll generate code both inside and outside the loop. */ | |
6863 | cmpv = s390_two_part_insv (&ac, &seq0, &seq2, mode, val, cmp); | |
6864 | newv = s390_two_part_insv (&ac, &seq1, &seq3, mode, val, new_rtx); | |
6865 | ||
6866 | if (seq0) | |
6867 | emit_insn (seq0); | |
6868 | if (seq1) | |
6869 | emit_insn (seq1); | |
6870 | ||
3093f076 | 6871 | /* Start CS loop. */ |
78ce265b RH |
6872 | if (!is_weak) |
6873 | { | |
6874 | /* Begin assuming success. */ | |
6875 | emit_move_insn (btarget, const1_rtx); | |
6876 | ||
6877 | csloop = gen_label_rtx (); | |
6878 | csend = gen_label_rtx (); | |
6879 | emit_label (csloop); | |
6880 | } | |
6881 | ||
f4aa3848 | 6882 | /* val = "<mem>00..0<mem>" |
3093f076 | 6883 | * cmp = "00..0<cmp>00..0" |
f4aa3848 | 6884 | * new = "00..0<new>00..0" |
3093f076 AS |
6885 | */ |
6886 | ||
78ce265b RH |
6887 | emit_insn (seq2); |
6888 | emit_insn (seq3); | |
6889 | ||
03db9ab5 | 6890 | cc = s390_emit_compare_and_swap (EQ, res, ac.memsi, cmpv, newv, CCZ1mode); |
78ce265b RH |
6891 | if (is_weak) |
6892 | emit_insn (gen_cstorecc4 (btarget, cc, XEXP (cc, 0), XEXP (cc, 1))); | |
3093f076 | 6893 | else |
3093f076 | 6894 | { |
4e1ffb63 RH |
6895 | rtx tmp; |
6896 | ||
78ce265b RH |
6897 | /* Jump to end if we're done (likely?). */ |
6898 | s390_emit_jump (csend, cc); | |
6899 | ||
4e1ffb63 RH |
6900 | /* Check for changes outside mode, and loop internal if so. |
6901 | Arrange the moves so that the compare is adjacent to the | |
6902 | branch so that we can generate CRJ. */ | |
6903 | tmp = copy_to_reg (val); | |
6904 | force_expand_binop (SImode, and_optab, res, ac.modemaski, val, | |
6905 | 1, OPTAB_DIRECT); | |
6906 | cc = s390_emit_compare (NE, val, tmp); | |
78ce265b RH |
6907 | s390_emit_jump (csloop, cc); |
6908 | ||
6909 | /* Failed. */ | |
6910 | emit_move_insn (btarget, const0_rtx); | |
6911 | emit_label (csend); | |
3093f076 | 6912 | } |
f4aa3848 | 6913 | |
3093f076 | 6914 | /* Return the correct part of the bitfield. */ |
78ce265b RH |
6915 | convert_move (vtarget, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift, |
6916 | NULL_RTX, 1, OPTAB_DIRECT), 1); | |
3093f076 AS |
6917 | } |
6918 | ||
03db9ab5 DV |
6919 | /* Variant of s390_expand_cs for SI, DI and TI modes. */ |
6920 | static void | |
6921 | s390_expand_cs_tdsi (machine_mode mode, rtx btarget, rtx vtarget, rtx mem, | |
6922 | rtx cmp, rtx new_rtx, bool is_weak) | |
6923 | { | |
6924 | rtx output = vtarget; | |
6925 | rtx_code_label *skip_cs_label = NULL; | |
6926 | bool do_const_opt = false; | |
6927 | ||
6928 | if (!register_operand (output, mode)) | |
6929 | output = gen_reg_rtx (mode); | |
6930 | ||
6931 | /* If IS_WEAK is true and the INPUT value is a constant, compare the memory | |
6932 | with the constant first and skip the compare_and_swap because its very | |
6933 | expensive and likely to fail anyway. | |
6934 | Note 1: This is done only for IS_WEAK. C11 allows optimizations that may | |
6935 | cause spurious in that case. | |
6936 | Note 2: It may be useful to do this also for non-constant INPUT. | |
6937 | Note 3: Currently only targets with "load on condition" are supported | |
6938 | (z196 and newer). */ | |
6939 | ||
6940 | if (TARGET_Z196 | |
6941 | && (mode == SImode || mode == DImode)) | |
6942 | do_const_opt = (is_weak && CONST_INT_P (cmp)); | |
6943 | ||
6944 | if (do_const_opt) | |
6945 | { | |
03db9ab5 DV |
6946 | rtx cc = gen_rtx_REG (CCZmode, CC_REGNUM); |
6947 | ||
6948 | skip_cs_label = gen_label_rtx (); | |
6949 | emit_move_insn (btarget, const0_rtx); | |
6950 | if (CONST_INT_P (cmp) && INTVAL (cmp) == 0) | |
6951 | { | |
6952 | rtvec lt = rtvec_alloc (2); | |
6953 | ||
6954 | /* Load-and-test + conditional jump. */ | |
6955 | RTVEC_ELT (lt, 0) | |
6956 | = gen_rtx_SET (cc, gen_rtx_COMPARE (CCZmode, mem, cmp)); | |
6957 | RTVEC_ELT (lt, 1) = gen_rtx_SET (output, mem); | |
6958 | emit_insn (gen_rtx_PARALLEL (VOIDmode, lt)); | |
6959 | } | |
6960 | else | |
6961 | { | |
6962 | emit_move_insn (output, mem); | |
6963 | emit_insn (gen_rtx_SET (cc, gen_rtx_COMPARE (CCZmode, output, cmp))); | |
6964 | } | |
6965 | s390_emit_jump (skip_cs_label, gen_rtx_NE (VOIDmode, cc, const0_rtx)); | |
5fa396ad JH |
6966 | add_reg_br_prob_note (get_last_insn (), |
6967 | profile_probability::very_unlikely ()); | |
03db9ab5 DV |
6968 | /* If the jump is not taken, OUTPUT is the expected value. */ |
6969 | cmp = output; | |
6970 | /* Reload newval to a register manually, *after* the compare and jump | |
6971 | above. Otherwise Reload might place it before the jump. */ | |
6972 | } | |
6973 | else | |
6974 | cmp = force_reg (mode, cmp); | |
6975 | new_rtx = force_reg (mode, new_rtx); | |
6976 | s390_emit_compare_and_swap (EQ, output, mem, cmp, new_rtx, | |
6977 | (do_const_opt) ? CCZmode : CCZ1mode); | |
6978 | if (skip_cs_label != NULL) | |
6979 | emit_label (skip_cs_label); | |
6980 | ||
6981 | /* We deliberately accept non-register operands in the predicate | |
6982 | to ensure the write back to the output operand happens *before* | |
6983 | the store-flags code below. This makes it easier for combine | |
6984 | to merge the store-flags code with a potential test-and-branch | |
6985 | pattern following (immediately!) afterwards. */ | |
6986 | if (output != vtarget) | |
6987 | emit_move_insn (vtarget, output); | |
6988 | ||
6989 | if (do_const_opt) | |
6990 | { | |
6991 | rtx cc, cond, ite; | |
6992 | ||
6993 | /* Do not use gen_cstorecc4 here because it writes either 1 or 0, but | |
6994 | btarget has already been initialized with 0 above. */ | |
6995 | cc = gen_rtx_REG (CCZmode, CC_REGNUM); | |
6996 | cond = gen_rtx_EQ (VOIDmode, cc, const0_rtx); | |
6997 | ite = gen_rtx_IF_THEN_ELSE (SImode, cond, const1_rtx, btarget); | |
6998 | emit_insn (gen_rtx_SET (btarget, ite)); | |
6999 | } | |
7000 | else | |
7001 | { | |
7002 | rtx cc, cond; | |
7003 | ||
7004 | cc = gen_rtx_REG (CCZ1mode, CC_REGNUM); | |
7005 | cond = gen_rtx_EQ (SImode, cc, const0_rtx); | |
7006 | emit_insn (gen_cstorecc4 (btarget, cond, cc, const0_rtx)); | |
7007 | } | |
7008 | } | |
7009 | ||
7010 | /* Expand an atomic compare and swap operation. MEM is the memory location, | |
7011 | CMP the old value to compare MEM with and NEW_RTX the value to set if | |
7012 | CMP == MEM. */ | |
7013 | ||
7014 | void | |
7015 | s390_expand_cs (machine_mode mode, rtx btarget, rtx vtarget, rtx mem, | |
7016 | rtx cmp, rtx new_rtx, bool is_weak) | |
7017 | { | |
7018 | switch (mode) | |
7019 | { | |
4e10a5a7 RS |
7020 | case E_TImode: |
7021 | case E_DImode: | |
7022 | case E_SImode: | |
03db9ab5 DV |
7023 | s390_expand_cs_tdsi (mode, btarget, vtarget, mem, cmp, new_rtx, is_weak); |
7024 | break; | |
4e10a5a7 RS |
7025 | case E_HImode: |
7026 | case E_QImode: | |
03db9ab5 DV |
7027 | s390_expand_cs_hqi (mode, btarget, vtarget, mem, cmp, new_rtx, is_weak); |
7028 | break; | |
7029 | default: | |
7030 | gcc_unreachable (); | |
7031 | } | |
7032 | } | |
7033 | ||
7034 | /* Expand an atomic_exchange operation simulated with a compare-and-swap loop. | |
7035 | The memory location MEM is set to INPUT. OUTPUT is set to the previous value | |
7036 | of MEM. */ | |
7037 | ||
7038 | void | |
7039 | s390_expand_atomic_exchange_tdsi (rtx output, rtx mem, rtx input) | |
7040 | { | |
7041 | machine_mode mode = GET_MODE (mem); | |
7042 | rtx_code_label *csloop; | |
7043 | ||
7044 | if (TARGET_Z196 | |
7045 | && (mode == DImode || mode == SImode) | |
7046 | && CONST_INT_P (input) && INTVAL (input) == 0) | |
7047 | { | |
7048 | emit_move_insn (output, const0_rtx); | |
7049 | if (mode == DImode) | |
7050 | emit_insn (gen_atomic_fetch_anddi (output, mem, const0_rtx, input)); | |
7051 | else | |
7052 | emit_insn (gen_atomic_fetch_andsi (output, mem, const0_rtx, input)); | |
7053 | return; | |
7054 | } | |
7055 | ||
7056 | input = force_reg (mode, input); | |
7057 | emit_move_insn (output, mem); | |
7058 | csloop = gen_label_rtx (); | |
7059 | emit_label (csloop); | |
7060 | s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, output, mem, output, | |
7061 | input, CCZ1mode)); | |
7062 | } | |
7063 | ||
45d18331 | 7064 | /* Expand an atomic operation CODE of mode MODE. MEM is the memory location |
ea2c620c | 7065 | and VAL the value to play with. If AFTER is true then store the value |
45d18331 AS |
7066 | MEM holds after the operation, if AFTER is false then store the value MEM |
7067 | holds before the operation. If TARGET is zero then discard that value, else | |
7068 | store it to TARGET. */ | |
7069 | ||
7070 | void | |
ef4bddc2 | 7071 | s390_expand_atomic (machine_mode mode, enum rtx_code code, |
45d18331 AS |
7072 | rtx target, rtx mem, rtx val, bool after) |
7073 | { | |
7074 | struct alignment_context ac; | |
7075 | rtx cmp; | |
0a2aaacc | 7076 | rtx new_rtx = gen_reg_rtx (SImode); |
45d18331 | 7077 | rtx orig = gen_reg_rtx (SImode); |
19f8b229 | 7078 | rtx_code_label *csloop = gen_label_rtx (); |
45d18331 AS |
7079 | |
7080 | gcc_assert (!target || register_operand (target, VOIDmode)); | |
7081 | gcc_assert (MEM_P (mem)); | |
7082 | ||
7083 | init_alignment_context (&ac, mem, mode); | |
7084 | ||
7085 | /* Shift val to the correct bit positions. | |
7086 | Preserve "icm", but prevent "ex icm". */ | |
7087 | if (!(ac.aligned && code == SET && MEM_P (val))) | |
7088 | val = s390_expand_mask_and_shift (val, mode, ac.shift); | |
7089 | ||
7090 | /* Further preparation insns. */ | |
7091 | if (code == PLUS || code == MINUS) | |
7092 | emit_move_insn (orig, val); | |
7093 | else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */ | |
7094 | val = expand_simple_binop (SImode, XOR, val, ac.modemaski, | |
7095 | NULL_RTX, 1, OPTAB_DIRECT); | |
7096 | ||
7097 | /* Load full word. Subsequent loads are performed by CS. */ | |
7098 | cmp = force_reg (SImode, ac.memsi); | |
7099 | ||
7100 | /* Start CS loop. */ | |
7101 | emit_label (csloop); | |
0a2aaacc | 7102 | emit_move_insn (new_rtx, cmp); |
45d18331 AS |
7103 | |
7104 | /* Patch new with val at correct position. */ | |
7105 | switch (code) | |
7106 | { | |
7107 | case PLUS: | |
7108 | case MINUS: | |
0a2aaacc | 7109 | val = expand_simple_binop (SImode, code, new_rtx, orig, |
45d18331 AS |
7110 | NULL_RTX, 1, OPTAB_DIRECT); |
7111 | val = expand_simple_binop (SImode, AND, val, ac.modemask, | |
7112 | NULL_RTX, 1, OPTAB_DIRECT); | |
7113 | /* FALLTHRU */ | |
f4aa3848 | 7114 | case SET: |
45d18331 | 7115 | if (ac.aligned && MEM_P (val)) |
44e95206 | 7116 | store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0, |
ee45a32d | 7117 | 0, 0, SImode, val, false); |
45d18331 AS |
7118 | else |
7119 | { | |
0a2aaacc | 7120 | new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski, |
45d18331 | 7121 | NULL_RTX, 1, OPTAB_DIRECT); |
0a2aaacc | 7122 | new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val, |
45d18331 AS |
7123 | NULL_RTX, 1, OPTAB_DIRECT); |
7124 | } | |
7125 | break; | |
7126 | case AND: | |
7127 | case IOR: | |
7128 | case XOR: | |
0a2aaacc | 7129 | new_rtx = expand_simple_binop (SImode, code, new_rtx, val, |
45d18331 AS |
7130 | NULL_RTX, 1, OPTAB_DIRECT); |
7131 | break; | |
7132 | case MULT: /* NAND */ | |
0a2aaacc | 7133 | new_rtx = expand_simple_binop (SImode, AND, new_rtx, val, |
45d18331 | 7134 | NULL_RTX, 1, OPTAB_DIRECT); |
6a238c58 AK |
7135 | new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask, |
7136 | NULL_RTX, 1, OPTAB_DIRECT); | |
45d18331 AS |
7137 | break; |
7138 | default: | |
7139 | gcc_unreachable (); | |
7140 | } | |
45d18331 | 7141 | |
8bb501bb | 7142 | s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp, |
03db9ab5 DV |
7143 | ac.memsi, cmp, new_rtx, |
7144 | CCZ1mode)); | |
45d18331 AS |
7145 | |
7146 | /* Return the correct part of the bitfield. */ | |
7147 | if (target) | |
7148 | convert_move (target, expand_simple_binop (SImode, LSHIFTRT, | |
0a2aaacc | 7149 | after ? new_rtx : cmp, ac.shift, |
45d18331 AS |
7150 | NULL_RTX, 1, OPTAB_DIRECT), 1); |
7151 | } | |
7152 | ||
fdbe66f2 | 7153 | /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. |
6b2300b3 JJ |
7154 | We need to emit DTP-relative relocations. */ |
7155 | ||
fdbe66f2 EB |
7156 | static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; |
7157 | ||
7158 | static void | |
9c808aad | 7159 | s390_output_dwarf_dtprel (FILE *file, int size, rtx x) |
6b2300b3 JJ |
7160 | { |
7161 | switch (size) | |
7162 | { | |
7163 | case 4: | |
7164 | fputs ("\t.long\t", file); | |
7165 | break; | |
7166 | case 8: | |
7167 | fputs ("\t.quad\t", file); | |
7168 | break; | |
7169 | default: | |
8d933e31 | 7170 | gcc_unreachable (); |
6b2300b3 JJ |
7171 | } |
7172 | output_addr_const (file, x); | |
7173 | fputs ("@DTPOFF", file); | |
7174 | } | |
7175 | ||
085261c8 AK |
7176 | /* Return the proper mode for REGNO being represented in the dwarf |
7177 | unwind table. */ | |
7178 | machine_mode | |
7179 | s390_dwarf_frame_reg_mode (int regno) | |
7180 | { | |
7181 | machine_mode save_mode = default_dwarf_frame_reg_mode (regno); | |
7182 | ||
7e5c3746 AK |
7183 | /* Make sure not to return DImode for any GPR with -m31 -mzarch. */ |
7184 | if (GENERAL_REGNO_P (regno)) | |
7185 | save_mode = Pmode; | |
7186 | ||
085261c8 AK |
7187 | /* The rightmost 64 bits of vector registers are call-clobbered. */ |
7188 | if (GET_MODE_SIZE (save_mode) > 8) | |
7189 | save_mode = DImode; | |
7190 | ||
7191 | return save_mode; | |
7192 | } | |
7193 | ||
7269aee7 | 7194 | #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING |
608063c3 | 7195 | /* Implement TARGET_MANGLE_TYPE. */ |
7269aee7 AH |
7196 | |
7197 | static const char * | |
3101faab | 7198 | s390_mangle_type (const_tree type) |
7269aee7 | 7199 | { |
3af82a61 AK |
7200 | type = TYPE_MAIN_VARIANT (type); |
7201 | ||
7202 | if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE | |
7203 | && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE) | |
7204 | return NULL; | |
7205 | ||
7206 | if (type == s390_builtin_types[BT_BV16QI]) return "U6__boolc"; | |
7207 | if (type == s390_builtin_types[BT_BV8HI]) return "U6__bools"; | |
7208 | if (type == s390_builtin_types[BT_BV4SI]) return "U6__booli"; | |
7209 | if (type == s390_builtin_types[BT_BV2DI]) return "U6__booll"; | |
7210 | ||
7269aee7 AH |
7211 | if (TYPE_MAIN_VARIANT (type) == long_double_type_node |
7212 | && TARGET_LONG_DOUBLE_128) | |
7213 | return "g"; | |
7214 | ||
7215 | /* For all other types, use normal C++ mangling. */ | |
7216 | return NULL; | |
7217 | } | |
7218 | #endif | |
7219 | ||
4c8c0dec | 7220 | /* In the name of slightly smaller debug output, and to cater to |
aabcd309 | 7221 | general assembler lossage, recognize various UNSPEC sequences |
4c8c0dec JJ |
7222 | and turn them back into a direct symbol reference. */ |
7223 | ||
69bd9368 | 7224 | static rtx |
9c808aad | 7225 | s390_delegitimize_address (rtx orig_x) |
4c8c0dec | 7226 | { |
e8d8f497 | 7227 | rtx x, y; |
4c8c0dec | 7228 | |
e8d8f497 JJ |
7229 | orig_x = delegitimize_mem_from_attrs (orig_x); |
7230 | x = orig_x; | |
e101e12e AK |
7231 | |
7232 | /* Extract the symbol ref from: | |
7233 | (plus:SI (reg:SI 12 %r12) | |
7234 | (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))] | |
01841ac0 AK |
7235 | UNSPEC_GOTOFF/PLTOFF))) |
7236 | and | |
7237 | (plus:SI (reg:SI 12 %r12) | |
7238 | (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))] | |
7239 | UNSPEC_GOTOFF/PLTOFF) | |
7240 | (const_int 4 [0x4])))) */ | |
e101e12e AK |
7241 | if (GET_CODE (x) == PLUS |
7242 | && REG_P (XEXP (x, 0)) | |
7243 | && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM | |
7244 | && GET_CODE (XEXP (x, 1)) == CONST) | |
7245 | { | |
ab081dd6 AK |
7246 | HOST_WIDE_INT offset = 0; |
7247 | ||
e101e12e AK |
7248 | /* The const operand. */ |
7249 | y = XEXP (XEXP (x, 1), 0); | |
01841ac0 AK |
7250 | |
7251 | if (GET_CODE (y) == PLUS | |
7252 | && GET_CODE (XEXP (y, 1)) == CONST_INT) | |
ab081dd6 AK |
7253 | { |
7254 | offset = INTVAL (XEXP (y, 1)); | |
7255 | y = XEXP (y, 0); | |
7256 | } | |
01841ac0 | 7257 | |
e101e12e | 7258 | if (GET_CODE (y) == UNSPEC |
01841ac0 AK |
7259 | && (XINT (y, 1) == UNSPEC_GOTOFF |
7260 | || XINT (y, 1) == UNSPEC_PLTOFF)) | |
0a81f074 | 7261 | return plus_constant (Pmode, XVECEXP (y, 0, 0), offset); |
e101e12e AK |
7262 | } |
7263 | ||
4c8c0dec JJ |
7264 | if (GET_CODE (x) != MEM) |
7265 | return orig_x; | |
7266 | ||
7267 | x = XEXP (x, 0); | |
7268 | if (GET_CODE (x) == PLUS | |
7269 | && GET_CODE (XEXP (x, 1)) == CONST | |
7270 | && GET_CODE (XEXP (x, 0)) == REG | |
7271 | && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM) | |
7272 | { | |
7273 | y = XEXP (XEXP (x, 1), 0); | |
7274 | if (GET_CODE (y) == UNSPEC | |
fd7643fb | 7275 | && XINT (y, 1) == UNSPEC_GOT) |
67a2f76d JJ |
7276 | y = XVECEXP (y, 0, 0); |
7277 | else | |
7278 | return orig_x; | |
4c8c0dec | 7279 | } |
67a2f76d | 7280 | else if (GET_CODE (x) == CONST) |
4c8c0dec | 7281 | { |
01841ac0 AK |
7282 | /* Extract the symbol ref from: |
7283 | (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))] | |
7284 | UNSPEC_PLT/GOTENT))) */ | |
7285 | ||
4c8c0dec JJ |
7286 | y = XEXP (x, 0); |
7287 | if (GET_CODE (y) == UNSPEC | |
01841ac0 AK |
7288 | && (XINT (y, 1) == UNSPEC_GOTENT |
7289 | || XINT (y, 1) == UNSPEC_PLT)) | |
67a2f76d JJ |
7290 | y = XVECEXP (y, 0, 0); |
7291 | else | |
7292 | return orig_x; | |
4c8c0dec | 7293 | } |
67a2f76d JJ |
7294 | else |
7295 | return orig_x; | |
4c8c0dec | 7296 | |
67a2f76d JJ |
7297 | if (GET_MODE (orig_x) != Pmode) |
7298 | { | |
2f36e14b JJ |
7299 | if (GET_MODE (orig_x) == BLKmode) |
7300 | return orig_x; | |
67a2f76d JJ |
7301 | y = lowpart_subreg (GET_MODE (orig_x), y, Pmode); |
7302 | if (y == NULL_RTX) | |
7303 | return orig_x; | |
7304 | } | |
7305 | return y; | |
4c8c0dec | 7306 | } |
ba956982 | 7307 | |
6d057022 AS |
7308 | /* Output operand OP to stdio stream FILE. |
7309 | OP is an address (register + offset) which is not used to address data; | |
7310 | instead the rightmost bits are interpreted as the value. */ | |
ac32b25e UW |
7311 | |
7312 | static void | |
dd95128b | 7313 | print_addrstyle_operand (FILE *file, rtx op) |
ac32b25e | 7314 | { |
d98ad410 UW |
7315 | HOST_WIDE_INT offset; |
7316 | rtx base; | |
f83a336d | 7317 | |
d98ad410 | 7318 | /* Extract base register and offset. */ |
dd95128b | 7319 | if (!s390_decompose_addrstyle_without_index (op, &base, &offset)) |
d98ad410 | 7320 | gcc_unreachable (); |
ac32b25e UW |
7321 | |
7322 | /* Sanity check. */ | |
d98ad410 | 7323 | if (base) |
8d933e31 | 7324 | { |
d98ad410 UW |
7325 | gcc_assert (GET_CODE (base) == REG); |
7326 | gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER); | |
7327 | gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS); | |
8d933e31 | 7328 | } |
ac32b25e | 7329 | |
6d057022 AS |
7330 | /* Offsets are constricted to twelve bits. */ |
7331 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1)); | |
d98ad410 UW |
7332 | if (base) |
7333 | fprintf (file, "(%s)", reg_names[REGNO (base)]); | |
ac32b25e UW |
7334 | } |
7335 | ||
2d38d809 DV |
7336 | /* Assigns the number of NOP halfwords to be emitted before and after the |
7337 | function label to *HW_BEFORE and *HW_AFTER. Both pointers must not be NULL. | |
7338 | If hotpatching is disabled for the function, the values are set to zero. | |
7339 | */ | |
d0de9e13 | 7340 | |
2d38d809 | 7341 | static void |
94091f43 DV |
7342 | s390_function_num_hotpatch_hw (tree decl, |
7343 | int *hw_before, | |
7344 | int *hw_after) | |
d0de9e13 DV |
7345 | { |
7346 | tree attr; | |
7347 | ||
94091f43 DV |
7348 | attr = lookup_attribute ("hotpatch", DECL_ATTRIBUTES (decl)); |
7349 | ||
7350 | /* Handle the arguments of the hotpatch attribute. The values | |
7351 | specified via attribute might override the cmdline argument | |
7352 | values. */ | |
7353 | if (attr) | |
d0de9e13 | 7354 | { |
94091f43 DV |
7355 | tree args = TREE_VALUE (attr); |
7356 | ||
7357 | *hw_before = TREE_INT_CST_LOW (TREE_VALUE (args)); | |
7358 | *hw_after = TREE_INT_CST_LOW (TREE_VALUE (TREE_CHAIN (args))); | |
d0de9e13 | 7359 | } |
94091f43 | 7360 | else |
d0de9e13 | 7361 | { |
94091f43 DV |
7362 | /* Use the values specified by the cmdline arguments. */ |
7363 | *hw_before = s390_hotpatch_hw_before_label; | |
7364 | *hw_after = s390_hotpatch_hw_after_label; | |
d0de9e13 | 7365 | } |
d0de9e13 DV |
7366 | } |
7367 | ||
ec47b086 DV |
7368 | /* Write the current .machine and .machinemode specification to the assembler |
7369 | file. */ | |
7370 | ||
7763d972 | 7371 | #ifdef HAVE_AS_MACHINE_MACHINEMODE |
ec47b086 DV |
7372 | static void |
7373 | s390_asm_output_machine_for_arch (FILE *asm_out_file) | |
7374 | { | |
7375 | fprintf (asm_out_file, "\t.machinemode %s\n", | |
7376 | (TARGET_ZARCH) ? "zarch" : "esa"); | |
2731a5b3 AK |
7377 | fprintf (asm_out_file, "\t.machine \"%s", |
7378 | processor_table[s390_arch].binutils_name); | |
ec47b086 DV |
7379 | if (S390_USE_ARCHITECTURE_MODIFIERS) |
7380 | { | |
7381 | int cpu_flags; | |
7382 | ||
7383 | cpu_flags = processor_flags_table[(int) s390_arch]; | |
7384 | if (TARGET_HTM && !(cpu_flags & PF_TX)) | |
7385 | fprintf (asm_out_file, "+htm"); | |
7386 | else if (!TARGET_HTM && (cpu_flags & PF_TX)) | |
7387 | fprintf (asm_out_file, "+nohtm"); | |
7388 | if (TARGET_VX && !(cpu_flags & PF_VX)) | |
7389 | fprintf (asm_out_file, "+vx"); | |
7390 | else if (!TARGET_VX && (cpu_flags & PF_VX)) | |
7391 | fprintf (asm_out_file, "+novx"); | |
7392 | } | |
7393 | fprintf (asm_out_file, "\"\n"); | |
7394 | } | |
7395 | ||
7396 | /* Write an extra function header before the very start of the function. */ | |
7397 | ||
7398 | void | |
7399 | s390_asm_output_function_prefix (FILE *asm_out_file, | |
7400 | const char *fnname ATTRIBUTE_UNUSED) | |
7401 | { | |
7402 | if (DECL_FUNCTION_SPECIFIC_TARGET (current_function_decl) == NULL) | |
7403 | return; | |
7404 | /* Since only the function specific options are saved but not the indications | |
7405 | which options are set, it's too much work here to figure out which options | |
7406 | have actually changed. Thus, generate .machine and .machinemode whenever a | |
7407 | function has the target attribute or pragma. */ | |
7408 | fprintf (asm_out_file, "\t.machinemode push\n"); | |
7409 | fprintf (asm_out_file, "\t.machine push\n"); | |
7410 | s390_asm_output_machine_for_arch (asm_out_file); | |
7411 | } | |
7412 | ||
7413 | /* Write an extra function footer after the very end of the function. */ | |
7414 | ||
7415 | void | |
7416 | s390_asm_declare_function_size (FILE *asm_out_file, | |
d45ef29e | 7417 | const char *fnname, tree decl) |
ec47b086 | 7418 | { |
d45ef29e MK |
7419 | if (!flag_inhibit_size_directive) |
7420 | ASM_OUTPUT_MEASURED_SIZE (asm_out_file, fnname); | |
ec47b086 DV |
7421 | if (DECL_FUNCTION_SPECIFIC_TARGET (decl) == NULL) |
7422 | return; | |
7423 | fprintf (asm_out_file, "\t.machine pop\n"); | |
7424 | fprintf (asm_out_file, "\t.machinemode pop\n"); | |
7425 | } | |
7426 | #endif | |
7427 | ||
d0de9e13 DV |
7428 | /* Write the extra assembler code needed to declare a function properly. */ |
7429 | ||
7430 | void | |
7431 | s390_asm_output_function_label (FILE *asm_out_file, const char *fname, | |
7432 | tree decl) | |
7433 | { | |
94091f43 | 7434 | int hw_before, hw_after; |
d0de9e13 | 7435 | |
2d38d809 DV |
7436 | s390_function_num_hotpatch_hw (decl, &hw_before, &hw_after); |
7437 | if (hw_before > 0) | |
d0de9e13 | 7438 | { |
f8af0e30 | 7439 | unsigned int function_alignment; |
d0de9e13 DV |
7440 | int i; |
7441 | ||
7442 | /* Add a trampoline code area before the function label and initialize it | |
7443 | with two-byte nop instructions. This area can be overwritten with code | |
7444 | that jumps to a patched version of the function. */ | |
4bbc8970 | 7445 | asm_fprintf (asm_out_file, "\tnopr\t%%r0" |
2d38d809 DV |
7446 | "\t# pre-label NOPs for hotpatch (%d halfwords)\n", |
7447 | hw_before); | |
7448 | for (i = 1; i < hw_before; i++) | |
4bbc8970 | 7449 | fputs ("\tnopr\t%r0\n", asm_out_file); |
2d38d809 | 7450 | |
d0de9e13 DV |
7451 | /* Note: The function label must be aligned so that (a) the bytes of the |
7452 | following nop do not cross a cacheline boundary, and (b) a jump address | |
7453 | (eight bytes for 64 bit targets, 4 bytes for 32 bit targets) can be | |
7454 | stored directly before the label without crossing a cacheline | |
7455 | boundary. All this is necessary to make sure the trampoline code can | |
2d38d809 DV |
7456 | be changed atomically. |
7457 | This alignment is done automatically using the FOUNCTION_BOUNDARY, but | |
7458 | if there are NOPs before the function label, the alignment is placed | |
7459 | before them. So it is necessary to duplicate the alignment after the | |
7460 | NOPs. */ | |
f8af0e30 DV |
7461 | function_alignment = MAX (8, DECL_ALIGN (decl) / BITS_PER_UNIT); |
7462 | if (! DECL_USER_ALIGN (decl)) | |
7463 | function_alignment = MAX (function_alignment, | |
7464 | (unsigned int) align_functions); | |
2d38d809 | 7465 | fputs ("\t# alignment for hotpatch\n", asm_out_file); |
f8af0e30 | 7466 | ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (function_alignment)); |
d0de9e13 DV |
7467 | } |
7468 | ||
ec47b086 DV |
7469 | if (S390_USE_TARGET_ATTRIBUTE && TARGET_DEBUG_ARG) |
7470 | { | |
7471 | asm_fprintf (asm_out_file, "\t# fn:%s ar%d\n", fname, s390_arch); | |
7472 | asm_fprintf (asm_out_file, "\t# fn:%s tu%d\n", fname, s390_tune); | |
7473 | asm_fprintf (asm_out_file, "\t# fn:%s sg%d\n", fname, s390_stack_guard); | |
7474 | asm_fprintf (asm_out_file, "\t# fn:%s ss%d\n", fname, s390_stack_size); | |
7475 | asm_fprintf (asm_out_file, "\t# fn:%s bc%d\n", fname, s390_branch_cost); | |
7476 | asm_fprintf (asm_out_file, "\t# fn:%s wf%d\n", fname, | |
7477 | s390_warn_framesize); | |
7478 | asm_fprintf (asm_out_file, "\t# fn:%s ba%d\n", fname, TARGET_BACKCHAIN); | |
7479 | asm_fprintf (asm_out_file, "\t# fn:%s hd%d\n", fname, TARGET_HARD_DFP); | |
7480 | asm_fprintf (asm_out_file, "\t# fn:%s hf%d\n", fname, !TARGET_SOFT_FLOAT); | |
7481 | asm_fprintf (asm_out_file, "\t# fn:%s ht%d\n", fname, TARGET_OPT_HTM); | |
7482 | asm_fprintf (asm_out_file, "\t# fn:%s vx%d\n", fname, TARGET_OPT_VX); | |
7483 | asm_fprintf (asm_out_file, "\t# fn:%s ps%d\n", fname, | |
7484 | TARGET_PACKED_STACK); | |
7485 | asm_fprintf (asm_out_file, "\t# fn:%s se%d\n", fname, TARGET_SMALL_EXEC); | |
7486 | asm_fprintf (asm_out_file, "\t# fn:%s mv%d\n", fname, TARGET_MVCLE); | |
7487 | asm_fprintf (asm_out_file, "\t# fn:%s zv%d\n", fname, TARGET_ZVECTOR); | |
7488 | asm_fprintf (asm_out_file, "\t# fn:%s wd%d\n", fname, | |
7489 | s390_warn_dynamicstack_p); | |
7490 | } | |
d0de9e13 | 7491 | ASM_OUTPUT_LABEL (asm_out_file, fname); |
2d38d809 DV |
7492 | if (hw_after > 0) |
7493 | asm_fprintf (asm_out_file, | |
7494 | "\t# post-label NOPs for hotpatch (%d halfwords)\n", | |
7495 | hw_after); | |
d0de9e13 DV |
7496 | } |
7497 | ||
38899e29 | 7498 | /* Output machine-dependent UNSPECs occurring in address constant X |
faeb9bb6 UW |
7499 | in assembler syntax to stdio stream FILE. Returns true if the |
7500 | constant X could be recognized, false otherwise. */ | |
9db1d521 | 7501 | |
0f8ab434 | 7502 | static bool |
faeb9bb6 | 7503 | s390_output_addr_const_extra (FILE *file, rtx x) |
9db1d521 | 7504 | { |
faeb9bb6 UW |
7505 | if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1) |
7506 | switch (XINT (x, 1)) | |
7507 | { | |
7508 | case UNSPEC_GOTENT: | |
7509 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
7510 | fprintf (file, "@GOTENT"); | |
7511 | return true; | |
7512 | case UNSPEC_GOT: | |
7513 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
7514 | fprintf (file, "@GOT"); | |
7515 | return true; | |
7516 | case UNSPEC_GOTOFF: | |
7517 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
7518 | fprintf (file, "@GOTOFF"); | |
7519 | return true; | |
7520 | case UNSPEC_PLT: | |
7521 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
7522 | fprintf (file, "@PLT"); | |
7523 | return true; | |
7524 | case UNSPEC_PLTOFF: | |
7525 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
7526 | fprintf (file, "@PLTOFF"); | |
7527 | return true; | |
7528 | case UNSPEC_TLSGD: | |
7529 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
7530 | fprintf (file, "@TLSGD"); | |
7531 | return true; | |
7532 | case UNSPEC_TLSLDM: | |
7533 | assemble_name (file, get_some_local_dynamic_name ()); | |
7534 | fprintf (file, "@TLSLDM"); | |
7535 | return true; | |
7536 | case UNSPEC_DTPOFF: | |
7537 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
7538 | fprintf (file, "@DTPOFF"); | |
7539 | return true; | |
7540 | case UNSPEC_NTPOFF: | |
7541 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
7542 | fprintf (file, "@NTPOFF"); | |
7543 | return true; | |
7544 | case UNSPEC_GOTNTPOFF: | |
7545 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
7546 | fprintf (file, "@GOTNTPOFF"); | |
7547 | return true; | |
7548 | case UNSPEC_INDNTPOFF: | |
7549 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
7550 | fprintf (file, "@INDNTPOFF"); | |
7551 | return true; | |
7552 | } | |
9db1d521 | 7553 | |
dc66391d RS |
7554 | if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2) |
7555 | switch (XINT (x, 1)) | |
7556 | { | |
7557 | case UNSPEC_POOL_OFFSET: | |
7558 | x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1)); | |
7559 | output_addr_const (file, x); | |
7560 | return true; | |
7561 | } | |
faeb9bb6 | 7562 | return false; |
9db1d521 HP |
7563 | } |
7564 | ||
c7453384 | 7565 | /* Output address operand ADDR in assembler syntax to |
994fe660 | 7566 | stdio stream FILE. */ |
9db1d521 HP |
7567 | |
7568 | void | |
9c808aad | 7569 | print_operand_address (FILE *file, rtx addr) |
9db1d521 HP |
7570 | { |
7571 | struct s390_address ad; | |
e6b07173 | 7572 | memset (&ad, 0, sizeof (s390_address)); |
9db1d521 | 7573 | |
0ff4390d | 7574 | if (s390_loadrelative_operand_p (addr, NULL, NULL)) |
963fc8d0 | 7575 | { |
8395b41e AK |
7576 | if (!TARGET_Z10) |
7577 | { | |
3f3c098d AK |
7578 | output_operand_lossage ("symbolic memory references are " |
7579 | "only supported on z10 or later"); | |
8395b41e AK |
7580 | return; |
7581 | } | |
963fc8d0 AK |
7582 | output_addr_const (file, addr); |
7583 | return; | |
7584 | } | |
7585 | ||
b808c04c | 7586 | if (!s390_decompose_address (addr, &ad) |
93fa8428 AK |
7587 | || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base))) |
7588 | || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))) | |
c85ce869 | 7589 | output_operand_lossage ("cannot decompose address"); |
c7453384 | 7590 | |
9db1d521 | 7591 | if (ad.disp) |
faeb9bb6 | 7592 | output_addr_const (file, ad.disp); |
9db1d521 HP |
7593 | else |
7594 | fprintf (file, "0"); | |
7595 | ||
7596 | if (ad.base && ad.indx) | |
7597 | fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)], | |
7598 | reg_names[REGNO (ad.base)]); | |
7599 | else if (ad.base) | |
7600 | fprintf (file, "(%s)", reg_names[REGNO (ad.base)]); | |
7601 | } | |
7602 | ||
c7453384 EC |
7603 | /* Output operand X in assembler syntax to stdio stream FILE. |
7604 | CODE specified the format flag. The following format flags | |
994fe660 UW |
7605 | are recognized: |
7606 | ||
7607 | 'C': print opcode suffix for branch condition. | |
7608 | 'D': print opcode suffix for inverse branch condition. | |
f1149235 | 7609 | 'E': print opcode suffix for branch on index instruction. |
7b8acc34 | 7610 | 'G': print the size of the operand in bytes. |
75ca1b39 RH |
7611 | 'J': print tls_load/tls_gdcall/tls_ldcall suffix |
7612 | 'M': print the second word of a TImode operand. | |
7613 | 'N': print the second word of a DImode operand. | |
085261c8 AK |
7614 | 'O': print only the displacement of a memory reference or address. |
7615 | 'R': print only the base register of a memory reference or address. | |
fc0ea003 | 7616 | 'S': print S-type memory reference (base+displacement). |
dd95128b AK |
7617 | 'Y': print address style operand without index (e.g. shift count or setmem |
7618 | operand). | |
994fe660 | 7619 | |
5519a4f9 | 7620 | 'b': print integer X as if it's an unsigned byte. |
963fc8d0 | 7621 | 'c': print integer X as if it's an signed byte. |
085261c8 AK |
7622 | 'e': "end" contiguous bitmask X in either DImode or vector inner mode. |
7623 | 'f': "end" contiguous bitmask X in SImode. | |
da48f5ec | 7624 | 'h': print integer X as if it's a signed halfword. |
f19a9af7 | 7625 | 'i': print the first nonzero HImode part of X. |
da48f5ec AK |
7626 | 'j': print the first HImode part unequal to -1 of X. |
7627 | 'k': print the first nonzero SImode part of X. | |
7628 | 'm': print the first SImode part unequal to -1 of X. | |
75ca1b39 | 7629 | 'o': print integer X as if it's an unsigned 32bit word. |
085261c8 AK |
7630 | 's': "start" of contiguous bitmask X in either DImode or vector inner mode. |
7631 | 't': CONST_INT: "start" of contiguous bitmask X in SImode. | |
7632 | CONST_VECTOR: Generate a bitmask for vgbm instruction. | |
75ca1b39 | 7633 | 'x': print integer X as if it's an unsigned halfword. |
085261c8 | 7634 | 'v': print register number as vector register (v1 instead of f1). |
75ca1b39 | 7635 | */ |
9db1d521 HP |
7636 | |
7637 | void | |
9c808aad | 7638 | print_operand (FILE *file, rtx x, int code) |
9db1d521 | 7639 | { |
75ca1b39 RH |
7640 | HOST_WIDE_INT ival; |
7641 | ||
9db1d521 HP |
7642 | switch (code) |
7643 | { | |
7644 | case 'C': | |
ba956982 | 7645 | fprintf (file, s390_branch_condition_mnemonic (x, FALSE)); |
9db1d521 HP |
7646 | return; |
7647 | ||
7648 | case 'D': | |
ba956982 | 7649 | fprintf (file, s390_branch_condition_mnemonic (x, TRUE)); |
9db1d521 HP |
7650 | return; |
7651 | ||
f1149235 AK |
7652 | case 'E': |
7653 | if (GET_CODE (x) == LE) | |
7654 | fprintf (file, "l"); | |
7655 | else if (GET_CODE (x) == GT) | |
7656 | fprintf (file, "h"); | |
7657 | else | |
3f3c098d AK |
7658 | output_operand_lossage ("invalid comparison operator " |
7659 | "for 'E' output modifier"); | |
f1149235 AK |
7660 | return; |
7661 | ||
fd3cd001 UW |
7662 | case 'J': |
7663 | if (GET_CODE (x) == SYMBOL_REF) | |
7664 | { | |
7665 | fprintf (file, "%s", ":tls_load:"); | |
7666 | output_addr_const (file, x); | |
7667 | } | |
7668 | else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD) | |
7669 | { | |
7670 | fprintf (file, "%s", ":tls_gdcall:"); | |
7671 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
7672 | } | |
7673 | else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM) | |
7674 | { | |
7675 | fprintf (file, "%s", ":tls_ldcall:"); | |
4fbca4ba RS |
7676 | const char *name = get_some_local_dynamic_name (); |
7677 | gcc_assert (name); | |
7678 | assemble_name (file, name); | |
fd3cd001 UW |
7679 | } |
7680 | else | |
3f3c098d | 7681 | output_operand_lossage ("invalid reference for 'J' output modifier"); |
fd3cd001 UW |
7682 | return; |
7683 | ||
7b8acc34 AK |
7684 | case 'G': |
7685 | fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x))); | |
7686 | return; | |
7687 | ||
9db1d521 HP |
7688 | case 'O': |
7689 | { | |
7690 | struct s390_address ad; | |
8d933e31 | 7691 | int ret; |
9db1d521 | 7692 | |
085261c8 | 7693 | ret = s390_decompose_address (MEM_P (x) ? XEXP (x, 0) : x, &ad); |
8395b41e AK |
7694 | |
7695 | if (!ret | |
7696 | || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base))) | |
7697 | || ad.indx) | |
7698 | { | |
3f3c098d | 7699 | output_operand_lossage ("invalid address for 'O' output modifier"); |
8395b41e AK |
7700 | return; |
7701 | } | |
9db1d521 HP |
7702 | |
7703 | if (ad.disp) | |
faeb9bb6 | 7704 | output_addr_const (file, ad.disp); |
9db1d521 HP |
7705 | else |
7706 | fprintf (file, "0"); | |
7707 | } | |
7708 | return; | |
7709 | ||
7710 | case 'R': | |
7711 | { | |
7712 | struct s390_address ad; | |
8d933e31 | 7713 | int ret; |
9db1d521 | 7714 | |
085261c8 | 7715 | ret = s390_decompose_address (MEM_P (x) ? XEXP (x, 0) : x, &ad); |
8395b41e AK |
7716 | |
7717 | if (!ret | |
7718 | || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base))) | |
7719 | || ad.indx) | |
7720 | { | |
3f3c098d | 7721 | output_operand_lossage ("invalid address for 'R' output modifier"); |
8395b41e AK |
7722 | return; |
7723 | } | |
9db1d521 HP |
7724 | |
7725 | if (ad.base) | |
7726 | fprintf (file, "%s", reg_names[REGNO (ad.base)]); | |
7727 | else | |
7728 | fprintf (file, "0"); | |
7729 | } | |
7730 | return; | |
7731 | ||
fc0ea003 UW |
7732 | case 'S': |
7733 | { | |
7734 | struct s390_address ad; | |
8d933e31 | 7735 | int ret; |
fc0ea003 | 7736 | |
8395b41e AK |
7737 | if (!MEM_P (x)) |
7738 | { | |
3f3c098d AK |
7739 | output_operand_lossage ("memory reference expected for " |
7740 | "'S' output modifier"); | |
8395b41e AK |
7741 | return; |
7742 | } | |
8d933e31 | 7743 | ret = s390_decompose_address (XEXP (x, 0), &ad); |
8395b41e AK |
7744 | |
7745 | if (!ret | |
7746 | || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base))) | |
7747 | || ad.indx) | |
7748 | { | |
3f3c098d | 7749 | output_operand_lossage ("invalid address for 'S' output modifier"); |
8395b41e AK |
7750 | return; |
7751 | } | |
fc0ea003 UW |
7752 | |
7753 | if (ad.disp) | |
7754 | output_addr_const (file, ad.disp); | |
7755 | else | |
7756 | fprintf (file, "0"); | |
7757 | ||
7758 | if (ad.base) | |
7759 | fprintf (file, "(%s)", reg_names[REGNO (ad.base)]); | |
7760 | } | |
7761 | return; | |
7762 | ||
9db1d521 HP |
7763 | case 'N': |
7764 | if (GET_CODE (x) == REG) | |
7765 | x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1); | |
7766 | else if (GET_CODE (x) == MEM) | |
0a81f074 RS |
7767 | x = change_address (x, VOIDmode, |
7768 | plus_constant (Pmode, XEXP (x, 0), 4)); | |
9db1d521 | 7769 | else |
3f3c098d AK |
7770 | output_operand_lossage ("register or memory expression expected " |
7771 | "for 'N' output modifier"); | |
9db1d521 HP |
7772 | break; |
7773 | ||
7774 | case 'M': | |
7775 | if (GET_CODE (x) == REG) | |
7776 | x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1); | |
7777 | else if (GET_CODE (x) == MEM) | |
0a81f074 RS |
7778 | x = change_address (x, VOIDmode, |
7779 | plus_constant (Pmode, XEXP (x, 0), 8)); | |
9db1d521 | 7780 | else |
3f3c098d AK |
7781 | output_operand_lossage ("register or memory expression expected " |
7782 | "for 'M' output modifier"); | |
9db1d521 | 7783 | break; |
ac32b25e UW |
7784 | |
7785 | case 'Y': | |
dd95128b | 7786 | print_addrstyle_operand (file, x); |
ac32b25e | 7787 | return; |
9db1d521 HP |
7788 | } |
7789 | ||
7790 | switch (GET_CODE (x)) | |
7791 | { | |
7792 | case REG: | |
085261c8 AK |
7793 | /* Print FP regs as fx instead of vx when they are accessed |
7794 | through non-vector mode. */ | |
7795 | if (code == 'v' | |
7796 | || VECTOR_NOFP_REG_P (x) | |
7797 | || (FP_REG_P (x) && VECTOR_MODE_P (GET_MODE (x))) | |
7798 | || (VECTOR_REG_P (x) | |
7799 | && (GET_MODE_SIZE (GET_MODE (x)) / | |
7800 | s390_class_max_nregs (FP_REGS, GET_MODE (x))) > 8)) | |
7801 | fprintf (file, "%%v%s", reg_names[REGNO (x)] + 2); | |
7802 | else | |
7803 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
9db1d521 HP |
7804 | break; |
7805 | ||
7806 | case MEM: | |
cc8ca59e | 7807 | output_address (GET_MODE (x), XEXP (x, 0)); |
9db1d521 HP |
7808 | break; |
7809 | ||
7810 | case CONST: | |
7811 | case CODE_LABEL: | |
7812 | case LABEL_REF: | |
7813 | case SYMBOL_REF: | |
faeb9bb6 | 7814 | output_addr_const (file, x); |
9db1d521 HP |
7815 | break; |
7816 | ||
7817 | case CONST_INT: | |
75ca1b39 RH |
7818 | ival = INTVAL (x); |
7819 | switch (code) | |
7820 | { | |
7821 | case 0: | |
7822 | break; | |
7823 | case 'b': | |
7824 | ival &= 0xff; | |
7825 | break; | |
7826 | case 'c': | |
7827 | ival = ((ival & 0xff) ^ 0x80) - 0x80; | |
7828 | break; | |
7829 | case 'x': | |
7830 | ival &= 0xffff; | |
7831 | break; | |
7832 | case 'h': | |
7833 | ival = ((ival & 0xffff) ^ 0x8000) - 0x8000; | |
7834 | break; | |
7835 | case 'i': | |
7836 | ival = s390_extract_part (x, HImode, 0); | |
7837 | break; | |
7838 | case 'j': | |
7839 | ival = s390_extract_part (x, HImode, -1); | |
7840 | break; | |
7841 | case 'k': | |
7842 | ival = s390_extract_part (x, SImode, 0); | |
7843 | break; | |
7844 | case 'm': | |
7845 | ival = s390_extract_part (x, SImode, -1); | |
7846 | break; | |
7847 | case 'o': | |
7848 | ival &= 0xffffffff; | |
7849 | break; | |
7850 | case 'e': case 'f': | |
7851 | case 's': case 't': | |
7852 | { | |
c2586c82 DV |
7853 | int start, end; |
7854 | int len; | |
75ca1b39 RH |
7855 | bool ok; |
7856 | ||
7857 | len = (code == 's' || code == 'e' ? 64 : 32); | |
c2586c82 | 7858 | ok = s390_contiguous_bitmask_p (ival, true, len, &start, &end); |
75ca1b39 RH |
7859 | gcc_assert (ok); |
7860 | if (code == 's' || code == 't') | |
c2586c82 | 7861 | ival = start; |
75ca1b39 | 7862 | else |
c2586c82 | 7863 | ival = end; |
75ca1b39 RH |
7864 | } |
7865 | break; | |
7866 | default: | |
7867 | output_operand_lossage ("invalid constant for output modifier '%c'", code); | |
7868 | } | |
7869 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival); | |
4023fb28 UW |
7870 | break; |
7871 | ||
089b05b1 | 7872 | case CONST_WIDE_INT: |
4023fb28 | 7873 | if (code == 'b') |
089b05b1 DV |
7874 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
7875 | CONST_WIDE_INT_ELT (x, 0) & 0xff); | |
9db1d521 | 7876 | else if (code == 'x') |
089b05b1 DV |
7877 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
7878 | CONST_WIDE_INT_ELT (x, 0) & 0xffff); | |
9db1d521 | 7879 | else if (code == 'h') |
3f3c098d | 7880 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
089b05b1 | 7881 | ((CONST_WIDE_INT_ELT (x, 0) & 0xffff) ^ 0x8000) - 0x8000); |
9db1d521 | 7882 | else |
8395b41e AK |
7883 | { |
7884 | if (code == 0) | |
3f3c098d AK |
7885 | output_operand_lossage ("invalid constant - try using " |
7886 | "an output modifier"); | |
8395b41e | 7887 | else |
3f3c098d AK |
7888 | output_operand_lossage ("invalid constant for output modifier '%c'", |
7889 | code); | |
8395b41e | 7890 | } |
9db1d521 | 7891 | break; |
085261c8 AK |
7892 | case CONST_VECTOR: |
7893 | switch (code) | |
7894 | { | |
b0057efd AK |
7895 | case 'h': |
7896 | gcc_assert (const_vec_duplicate_p (x)); | |
7897 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, | |
7898 | ((INTVAL (XVECEXP (x, 0, 0)) & 0xffff) ^ 0x8000) - 0x8000); | |
7899 | break; | |
085261c8 AK |
7900 | case 'e': |
7901 | case 's': | |
7902 | { | |
c2586c82 | 7903 | int start, end; |
085261c8 AK |
7904 | bool ok; |
7905 | ||
c2586c82 | 7906 | ok = s390_contiguous_bitmask_vector_p (x, &start, &end); |
085261c8 | 7907 | gcc_assert (ok); |
c2586c82 | 7908 | ival = (code == 's') ? start : end; |
085261c8 AK |
7909 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival); |
7910 | } | |
7911 | break; | |
7912 | case 't': | |
7913 | { | |
7914 | unsigned mask; | |
7915 | bool ok = s390_bytemask_vector_p (x, &mask); | |
7916 | gcc_assert (ok); | |
7917 | fprintf (file, "%u", mask); | |
7918 | } | |
7919 | break; | |
7920 | ||
7921 | default: | |
7922 | output_operand_lossage ("invalid constant vector for output " | |
7923 | "modifier '%c'", code); | |
7924 | } | |
7925 | break; | |
9db1d521 HP |
7926 | |
7927 | default: | |
8395b41e | 7928 | if (code == 0) |
3f3c098d AK |
7929 | output_operand_lossage ("invalid expression - try using " |
7930 | "an output modifier"); | |
8395b41e | 7931 | else |
3f3c098d AK |
7932 | output_operand_lossage ("invalid expression for output " |
7933 | "modifier '%c'", code); | |
9db1d521 HP |
7934 | break; |
7935 | } | |
7936 | } | |
7937 | ||
301d03af RS |
7938 | /* Target hook for assembling integer objects. We need to define it |
7939 | here to work a round a bug in some versions of GAS, which couldn't | |
7940 | handle values smaller than INT_MIN when printed in decimal. */ | |
7941 | ||
7942 | static bool | |
9c808aad | 7943 | s390_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af RS |
7944 | { |
7945 | if (size == 8 && aligned_p | |
7946 | && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN) | |
7947 | { | |
4a0a75dd KG |
7948 | fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n", |
7949 | INTVAL (x)); | |
301d03af RS |
7950 | return true; |
7951 | } | |
7952 | return default_assemble_integer (x, size, aligned_p); | |
7953 | } | |
7954 | ||
c7453384 | 7955 | /* Returns true if register REGNO is used for forming |
994fe660 | 7956 | a memory address in expression X. */ |
9db1d521 | 7957 | |
3ed99cc9 | 7958 | static bool |
9c808aad | 7959 | reg_used_in_mem_p (int regno, rtx x) |
9db1d521 HP |
7960 | { |
7961 | enum rtx_code code = GET_CODE (x); | |
7962 | int i, j; | |
7963 | const char *fmt; | |
c7453384 | 7964 | |
9db1d521 HP |
7965 | if (code == MEM) |
7966 | { | |
c9bd6bcd | 7967 | if (refers_to_regno_p (regno, XEXP (x, 0))) |
3ed99cc9 | 7968 | return true; |
9db1d521 | 7969 | } |
c7453384 | 7970 | else if (code == SET |
4023fb28 UW |
7971 | && GET_CODE (SET_DEST (x)) == PC) |
7972 | { | |
c9bd6bcd | 7973 | if (refers_to_regno_p (regno, SET_SRC (x))) |
3ed99cc9 | 7974 | return true; |
4023fb28 | 7975 | } |
9db1d521 HP |
7976 | |
7977 | fmt = GET_RTX_FORMAT (code); | |
7978 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
7979 | { | |
7980 | if (fmt[i] == 'e' | |
7981 | && reg_used_in_mem_p (regno, XEXP (x, i))) | |
3ed99cc9 | 7982 | return true; |
c7453384 | 7983 | |
9db1d521 HP |
7984 | else if (fmt[i] == 'E') |
7985 | for (j = 0; j < XVECLEN (x, i); j++) | |
7986 | if (reg_used_in_mem_p (regno, XVECEXP (x, i, j))) | |
3ed99cc9 | 7987 | return true; |
9db1d521 | 7988 | } |
3ed99cc9 | 7989 | return false; |
9db1d521 HP |
7990 | } |
7991 | ||
d65f7478 | 7992 | /* Returns true if expression DEP_RTX sets an address register |
994fe660 | 7993 | used by instruction INSN to address memory. */ |
9db1d521 | 7994 | |
3ed99cc9 | 7995 | static bool |
647d790d | 7996 | addr_generation_dependency_p (rtx dep_rtx, rtx_insn *insn) |
9db1d521 | 7997 | { |
4023fb28 | 7998 | rtx target, pat; |
9db1d521 | 7999 | |
b64925dc | 8000 | if (NONJUMP_INSN_P (dep_rtx)) |
34f0d87a | 8001 | dep_rtx = PATTERN (dep_rtx); |
077dab3b | 8002 | |
9db1d521 HP |
8003 | if (GET_CODE (dep_rtx) == SET) |
8004 | { | |
8005 | target = SET_DEST (dep_rtx); | |
cc7ab9b7 UW |
8006 | if (GET_CODE (target) == STRICT_LOW_PART) |
8007 | target = XEXP (target, 0); | |
8008 | while (GET_CODE (target) == SUBREG) | |
8009 | target = SUBREG_REG (target); | |
8010 | ||
9db1d521 HP |
8011 | if (GET_CODE (target) == REG) |
8012 | { | |
8013 | int regno = REGNO (target); | |
8014 | ||
077dab3b | 8015 | if (s390_safe_attr_type (insn) == TYPE_LA) |
4023fb28 UW |
8016 | { |
8017 | pat = PATTERN (insn); | |
8018 | if (GET_CODE (pat) == PARALLEL) | |
8019 | { | |
8d933e31 | 8020 | gcc_assert (XVECLEN (pat, 0) == 2); |
4023fb28 UW |
8021 | pat = XVECEXP (pat, 0, 0); |
8022 | } | |
8d933e31 | 8023 | gcc_assert (GET_CODE (pat) == SET); |
c9bd6bcd | 8024 | return refers_to_regno_p (regno, SET_SRC (pat)); |
4023fb28 | 8025 | } |
077dab3b | 8026 | else if (get_attr_atype (insn) == ATYPE_AGEN) |
4023fb28 UW |
8027 | return reg_used_in_mem_p (regno, PATTERN (insn)); |
8028 | } | |
9db1d521 | 8029 | } |
3ed99cc9 | 8030 | return false; |
9db1d521 HP |
8031 | } |
8032 | ||
077dab3b HP |
8033 | /* Return 1, if dep_insn sets register used in insn in the agen unit. */ |
8034 | ||
c7453384 | 8035 | int |
647d790d | 8036 | s390_agen_dep_p (rtx_insn *dep_insn, rtx_insn *insn) |
c7453384 | 8037 | { |
077dab3b HP |
8038 | rtx dep_rtx = PATTERN (dep_insn); |
8039 | int i; | |
c7453384 EC |
8040 | |
8041 | if (GET_CODE (dep_rtx) == SET | |
077dab3b HP |
8042 | && addr_generation_dependency_p (dep_rtx, insn)) |
8043 | return 1; | |
8044 | else if (GET_CODE (dep_rtx) == PARALLEL) | |
8045 | { | |
8046 | for (i = 0; i < XVECLEN (dep_rtx, 0); i++) | |
8047 | { | |
8048 | if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn)) | |
8049 | return 1; | |
8050 | } | |
8051 | } | |
8052 | return 0; | |
8053 | } | |
8054 | ||
9381e3f1 | 8055 | |
52609473 HP |
8056 | /* A C statement (sans semicolon) to update the integer scheduling priority |
8057 | INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier, | |
8058 | reduce the priority to execute INSN later. Do not define this macro if | |
c7453384 | 8059 | you do not need to adjust the scheduling priorities of insns. |
52609473 | 8060 | |
c7453384 | 8061 | A STD instruction should be scheduled earlier, |
52609473 | 8062 | in order to use the bypass. */ |
52609473 | 8063 | static int |
ac44248e | 8064 | s390_adjust_priority (rtx_insn *insn, int priority) |
52609473 HP |
8065 | { |
8066 | if (! INSN_P (insn)) | |
8067 | return priority; | |
8068 | ||
fd9c86e0 | 8069 | if (s390_tune <= PROCESSOR_2064_Z900) |
52609473 HP |
8070 | return priority; |
8071 | ||
8072 | switch (s390_safe_attr_type (insn)) | |
8073 | { | |
cfdb984b AS |
8074 | case TYPE_FSTOREDF: |
8075 | case TYPE_FSTORESF: | |
52609473 HP |
8076 | priority = priority << 3; |
8077 | break; | |
8078 | case TYPE_STORE: | |
ea77e738 | 8079 | case TYPE_STM: |
52609473 HP |
8080 | priority = priority << 1; |
8081 | break; | |
8082 | default: | |
8083 | break; | |
8084 | } | |
8085 | return priority; | |
8086 | } | |
f2d3c02a | 8087 | |
2cdece44 | 8088 | |
077dab3b | 8089 | /* The number of instructions that can be issued per cycle. */ |
f2d3c02a | 8090 | |
077dab3b | 8091 | static int |
9c808aad | 8092 | s390_issue_rate (void) |
077dab3b | 8093 | { |
93538e8e AK |
8094 | switch (s390_tune) |
8095 | { | |
8096 | case PROCESSOR_2084_Z990: | |
8097 | case PROCESSOR_2094_Z9_109: | |
fd9c86e0 | 8098 | case PROCESSOR_2094_Z9_EC: |
65b1d8ea | 8099 | case PROCESSOR_2817_Z196: |
93538e8e AK |
8100 | return 3; |
8101 | case PROCESSOR_2097_Z10: | |
8102 | return 2; | |
bacf8ec3 DV |
8103 | case PROCESSOR_9672_G5: |
8104 | case PROCESSOR_9672_G6: | |
8105 | case PROCESSOR_2064_Z900: | |
ff39d72a AK |
8106 | /* Starting with EC12 we use the sched_reorder hook to take care |
8107 | of instruction dispatch constraints. The algorithm only | |
8108 | picks the best instruction and assumes only a single | |
8109 | instruction gets issued per cycle. */ | |
8110 | case PROCESSOR_2827_ZEC12: | |
bacf8ec3 | 8111 | case PROCESSOR_2964_Z13: |
2731a5b3 | 8112 | case PROCESSOR_3906_Z14: |
93538e8e AK |
8113 | default: |
8114 | return 1; | |
8115 | } | |
077dab3b | 8116 | } |
f2d3c02a | 8117 | |
52609473 | 8118 | static int |
9c808aad | 8119 | s390_first_cycle_multipass_dfa_lookahead (void) |
52609473 | 8120 | { |
64e1e4c4 | 8121 | return 4; |
52609473 HP |
8122 | } |
8123 | ||
585539a1 UW |
8124 | /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression. |
8125 | Fix up MEMs as required. */ | |
8126 | ||
8127 | static void | |
8128 | annotate_constant_pool_refs (rtx *x) | |
8129 | { | |
8130 | int i, j; | |
8131 | const char *fmt; | |
8132 | ||
8d933e31 AS |
8133 | gcc_assert (GET_CODE (*x) != SYMBOL_REF |
8134 | || !CONSTANT_POOL_ADDRESS_P (*x)); | |
585539a1 UW |
8135 | |
8136 | /* Literal pool references can only occur inside a MEM ... */ | |
8137 | if (GET_CODE (*x) == MEM) | |
8138 | { | |
8139 | rtx memref = XEXP (*x, 0); | |
8140 | ||
8141 | if (GET_CODE (memref) == SYMBOL_REF | |
8142 | && CONSTANT_POOL_ADDRESS_P (memref)) | |
8143 | { | |
8144 | rtx base = cfun->machine->base_reg; | |
8145 | rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base), | |
8146 | UNSPEC_LTREF); | |
8147 | ||
8148 | *x = replace_equiv_address (*x, addr); | |
8149 | return; | |
8150 | } | |
8151 | ||
8152 | if (GET_CODE (memref) == CONST | |
8153 | && GET_CODE (XEXP (memref, 0)) == PLUS | |
8154 | && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT | |
8155 | && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF | |
8156 | && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0))) | |
8157 | { | |
8158 | HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1)); | |
8159 | rtx sym = XEXP (XEXP (memref, 0), 0); | |
8160 | rtx base = cfun->machine->base_reg; | |
8161 | rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base), | |
8162 | UNSPEC_LTREF); | |
8163 | ||
0a81f074 | 8164 | *x = replace_equiv_address (*x, plus_constant (Pmode, addr, off)); |
585539a1 UW |
8165 | return; |
8166 | } | |
8167 | } | |
8168 | ||
8169 | /* ... or a load-address type pattern. */ | |
8170 | if (GET_CODE (*x) == SET) | |
8171 | { | |
8172 | rtx addrref = SET_SRC (*x); | |
8173 | ||
8174 | if (GET_CODE (addrref) == SYMBOL_REF | |
8175 | && CONSTANT_POOL_ADDRESS_P (addrref)) | |
8176 | { | |
8177 | rtx base = cfun->machine->base_reg; | |
8178 | rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base), | |
8179 | UNSPEC_LTREF); | |
8180 | ||
8181 | SET_SRC (*x) = addr; | |
8182 | return; | |
8183 | } | |
8184 | ||
8185 | if (GET_CODE (addrref) == CONST | |
8186 | && GET_CODE (XEXP (addrref, 0)) == PLUS | |
8187 | && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT | |
8188 | && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF | |
8189 | && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0))) | |
8190 | { | |
8191 | HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1)); | |
8192 | rtx sym = XEXP (XEXP (addrref, 0), 0); | |
8193 | rtx base = cfun->machine->base_reg; | |
8194 | rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base), | |
8195 | UNSPEC_LTREF); | |
8196 | ||
0a81f074 | 8197 | SET_SRC (*x) = plus_constant (Pmode, addr, off); |
585539a1 UW |
8198 | return; |
8199 | } | |
8200 | } | |
8201 | ||
8202 | /* Annotate LTREL_BASE as well. */ | |
8203 | if (GET_CODE (*x) == UNSPEC | |
8204 | && XINT (*x, 1) == UNSPEC_LTREL_BASE) | |
8205 | { | |
8206 | rtx base = cfun->machine->base_reg; | |
8207 | *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base), | |
8208 | UNSPEC_LTREL_BASE); | |
8209 | return; | |
8210 | } | |
8211 | ||
8212 | fmt = GET_RTX_FORMAT (GET_CODE (*x)); | |
8213 | for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--) | |
8214 | { | |
8215 | if (fmt[i] == 'e') | |
8216 | { | |
8217 | annotate_constant_pool_refs (&XEXP (*x, i)); | |
8218 | } | |
8219 | else if (fmt[i] == 'E') | |
8220 | { | |
8221 | for (j = 0; j < XVECLEN (*x, i); j++) | |
8222 | annotate_constant_pool_refs (&XVECEXP (*x, i, j)); | |
8223 | } | |
8224 | } | |
8225 | } | |
8226 | ||
ab96de7e AS |
8227 | /* Split all branches that exceed the maximum distance. |
8228 | Returns true if this created a new literal pool entry. */ | |
8229 | ||
8230 | static int | |
8231 | s390_split_branches (void) | |
8232 | { | |
8233 | rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM); | |
8d933e31 | 8234 | int new_literal = 0, ret; |
775c43d3 | 8235 | rtx_insn *insn; |
17f385d8 | 8236 | rtx pat, target; |
ab96de7e AS |
8237 | rtx *label; |
8238 | ||
8239 | /* We need correct insn addresses. */ | |
8240 | ||
8241 | shorten_branches (get_insns ()); | |
8242 | ||
8243 | /* Find all branches that exceed 64KB, and split them. */ | |
8244 | ||
8245 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
8246 | { | |
966f97ac | 8247 | if (! JUMP_P (insn) || tablejump_p (insn, NULL, NULL)) |
ab96de7e AS |
8248 | continue; |
8249 | ||
8250 | pat = PATTERN (insn); | |
966f97ac | 8251 | if (GET_CODE (pat) == PARALLEL) |
ab96de7e AS |
8252 | pat = XVECEXP (pat, 0, 0); |
8253 | if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx) | |
8254 | continue; | |
8255 | ||
8256 | if (GET_CODE (SET_SRC (pat)) == LABEL_REF) | |
8257 | { | |
8258 | label = &SET_SRC (pat); | |
8259 | } | |
8260 | else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE) | |
8261 | { | |
8262 | if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF) | |
8263 | label = &XEXP (SET_SRC (pat), 1); | |
8264 | else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF) | |
8265 | label = &XEXP (SET_SRC (pat), 2); | |
8266 | else | |
8267 | continue; | |
8268 | } | |
8269 | else | |
8270 | continue; | |
8271 | ||
8272 | if (get_attr_length (insn) <= 4) | |
8273 | continue; | |
8274 | ||
e2df5c1d UW |
8275 | /* We are going to use the return register as scratch register, |
8276 | make sure it will be saved/restored by the prologue/epilogue. */ | |
8277 | cfun_frame_layout.save_return_addr_p = 1; | |
8278 | ||
ab96de7e AS |
8279 | if (!flag_pic) |
8280 | { | |
8281 | new_literal = 1; | |
17f385d8 | 8282 | rtx mem = force_const_mem (Pmode, *label); |
f7df4a84 RS |
8283 | rtx_insn *set_insn = emit_insn_before (gen_rtx_SET (temp_reg, mem), |
8284 | insn); | |
17f385d8 DM |
8285 | INSN_ADDRESSES_NEW (set_insn, -1); |
8286 | annotate_constant_pool_refs (&PATTERN (set_insn)); | |
ab96de7e AS |
8287 | |
8288 | target = temp_reg; | |
8289 | } | |
8290 | else | |
8291 | { | |
8292 | new_literal = 1; | |
8293 | target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label), | |
8294 | UNSPEC_LTREL_OFFSET); | |
8295 | target = gen_rtx_CONST (Pmode, target); | |
8296 | target = force_const_mem (Pmode, target); | |
f7df4a84 RS |
8297 | rtx_insn *set_insn = emit_insn_before (gen_rtx_SET (temp_reg, target), |
8298 | insn); | |
17f385d8 DM |
8299 | INSN_ADDRESSES_NEW (set_insn, -1); |
8300 | annotate_constant_pool_refs (&PATTERN (set_insn)); | |
ab96de7e AS |
8301 | |
8302 | target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0), | |
8303 | cfun->machine->base_reg), | |
8304 | UNSPEC_LTREL_BASE); | |
8305 | target = gen_rtx_PLUS (Pmode, temp_reg, target); | |
8306 | } | |
8307 | ||
8d933e31 AS |
8308 | ret = validate_change (insn, label, target, 0); |
8309 | gcc_assert (ret); | |
ab96de7e AS |
8310 | } |
8311 | ||
8312 | return new_literal; | |
8313 | } | |
8314 | ||
b2ccb744 | 8315 | |
f4aa3848 AK |
8316 | /* Find an annotated literal pool symbol referenced in RTX X, |
8317 | and store it at REF. Will abort if X contains references to | |
585539a1 UW |
8318 | more than one such pool symbol; multiple references to the same |
8319 | symbol are allowed, however. | |
b2ccb744 | 8320 | |
c7453384 | 8321 | The rtx pointed to by REF must be initialized to NULL_RTX |
b2ccb744 UW |
8322 | by the caller before calling this routine. */ |
8323 | ||
8324 | static void | |
9c808aad | 8325 | find_constant_pool_ref (rtx x, rtx *ref) |
b2ccb744 UW |
8326 | { |
8327 | int i, j; | |
8328 | const char *fmt; | |
8329 | ||
fd7643fb UW |
8330 | /* Ignore LTREL_BASE references. */ |
8331 | if (GET_CODE (x) == UNSPEC | |
8332 | && XINT (x, 1) == UNSPEC_LTREL_BASE) | |
8333 | return; | |
5af2f3d3 UW |
8334 | /* Likewise POOL_ENTRY insns. */ |
8335 | if (GET_CODE (x) == UNSPEC_VOLATILE | |
8336 | && XINT (x, 1) == UNSPECV_POOL_ENTRY) | |
8337 | return; | |
fd7643fb | 8338 | |
8d933e31 AS |
8339 | gcc_assert (GET_CODE (x) != SYMBOL_REF |
8340 | || !CONSTANT_POOL_ADDRESS_P (x)); | |
585539a1 UW |
8341 | |
8342 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF) | |
b2ccb744 | 8343 | { |
585539a1 | 8344 | rtx sym = XVECEXP (x, 0, 0); |
8d933e31 AS |
8345 | gcc_assert (GET_CODE (sym) == SYMBOL_REF |
8346 | && CONSTANT_POOL_ADDRESS_P (sym)); | |
585539a1 | 8347 | |
b2ccb744 | 8348 | if (*ref == NULL_RTX) |
585539a1 | 8349 | *ref = sym; |
f4aa3848 | 8350 | else |
8d933e31 | 8351 | gcc_assert (*ref == sym); |
585539a1 UW |
8352 | |
8353 | return; | |
b2ccb744 UW |
8354 | } |
8355 | ||
8356 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
8357 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
8358 | { | |
8359 | if (fmt[i] == 'e') | |
8360 | { | |
8361 | find_constant_pool_ref (XEXP (x, i), ref); | |
8362 | } | |
8363 | else if (fmt[i] == 'E') | |
8364 | { | |
8365 | for (j = 0; j < XVECLEN (x, i); j++) | |
8366 | find_constant_pool_ref (XVECEXP (x, i, j), ref); | |
8367 | } | |
8368 | } | |
8369 | } | |
8370 | ||
f4aa3848 | 8371 | /* Replace every reference to the annotated literal pool |
585539a1 | 8372 | symbol REF in X by its base plus OFFSET. */ |
b2ccb744 UW |
8373 | |
8374 | static void | |
585539a1 | 8375 | replace_constant_pool_ref (rtx *x, rtx ref, rtx offset) |
b2ccb744 UW |
8376 | { |
8377 | int i, j; | |
8378 | const char *fmt; | |
8379 | ||
8d933e31 | 8380 | gcc_assert (*x != ref); |
b2ccb744 | 8381 | |
585539a1 UW |
8382 | if (GET_CODE (*x) == UNSPEC |
8383 | && XINT (*x, 1) == UNSPEC_LTREF | |
8384 | && XVECEXP (*x, 0, 0) == ref) | |
b2ccb744 | 8385 | { |
585539a1 UW |
8386 | *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset); |
8387 | return; | |
b2ccb744 UW |
8388 | } |
8389 | ||
585539a1 UW |
8390 | if (GET_CODE (*x) == PLUS |
8391 | && GET_CODE (XEXP (*x, 1)) == CONST_INT | |
8392 | && GET_CODE (XEXP (*x, 0)) == UNSPEC | |
8393 | && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF | |
8394 | && XVECEXP (XEXP (*x, 0), 0, 0) == ref) | |
b2ccb744 | 8395 | { |
585539a1 | 8396 | rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset); |
0a81f074 | 8397 | *x = plus_constant (Pmode, addr, INTVAL (XEXP (*x, 1))); |
585539a1 | 8398 | return; |
b2ccb744 UW |
8399 | } |
8400 | ||
8401 | fmt = GET_RTX_FORMAT (GET_CODE (*x)); | |
8402 | for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--) | |
8403 | { | |
8404 | if (fmt[i] == 'e') | |
8405 | { | |
585539a1 | 8406 | replace_constant_pool_ref (&XEXP (*x, i), ref, offset); |
b2ccb744 UW |
8407 | } |
8408 | else if (fmt[i] == 'E') | |
8409 | { | |
8410 | for (j = 0; j < XVECLEN (*x, i); j++) | |
585539a1 | 8411 | replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset); |
b2ccb744 UW |
8412 | } |
8413 | } | |
8414 | } | |
8415 | ||
c7453384 | 8416 | /* Check whether X contains an UNSPEC_LTREL_BASE. |
fd7643fb | 8417 | Return its constant pool symbol if found, NULL_RTX otherwise. */ |
aee4e0db | 8418 | |
fd7643fb | 8419 | static rtx |
9c808aad | 8420 | find_ltrel_base (rtx x) |
aee4e0db | 8421 | { |
aee4e0db UW |
8422 | int i, j; |
8423 | const char *fmt; | |
8424 | ||
fd7643fb UW |
8425 | if (GET_CODE (x) == UNSPEC |
8426 | && XINT (x, 1) == UNSPEC_LTREL_BASE) | |
8427 | return XVECEXP (x, 0, 0); | |
aee4e0db UW |
8428 | |
8429 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
8430 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
8431 | { | |
8432 | if (fmt[i] == 'e') | |
8433 | { | |
fd7643fb UW |
8434 | rtx fnd = find_ltrel_base (XEXP (x, i)); |
8435 | if (fnd) | |
8436 | return fnd; | |
aee4e0db UW |
8437 | } |
8438 | else if (fmt[i] == 'E') | |
8439 | { | |
8440 | for (j = 0; j < XVECLEN (x, i); j++) | |
fd7643fb UW |
8441 | { |
8442 | rtx fnd = find_ltrel_base (XVECEXP (x, i, j)); | |
8443 | if (fnd) | |
8444 | return fnd; | |
8445 | } | |
aee4e0db UW |
8446 | } |
8447 | } | |
8448 | ||
fd7643fb | 8449 | return NULL_RTX; |
aee4e0db UW |
8450 | } |
8451 | ||
585539a1 | 8452 | /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */ |
aee4e0db UW |
8453 | |
8454 | static void | |
585539a1 | 8455 | replace_ltrel_base (rtx *x) |
aee4e0db | 8456 | { |
fd7643fb | 8457 | int i, j; |
aee4e0db UW |
8458 | const char *fmt; |
8459 | ||
fd7643fb UW |
8460 | if (GET_CODE (*x) == UNSPEC |
8461 | && XINT (*x, 1) == UNSPEC_LTREL_BASE) | |
aee4e0db | 8462 | { |
585539a1 | 8463 | *x = XVECEXP (*x, 0, 1); |
fd7643fb | 8464 | return; |
aee4e0db UW |
8465 | } |
8466 | ||
8467 | fmt = GET_RTX_FORMAT (GET_CODE (*x)); | |
8468 | for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--) | |
8469 | { | |
8470 | if (fmt[i] == 'e') | |
8471 | { | |
585539a1 | 8472 | replace_ltrel_base (&XEXP (*x, i)); |
aee4e0db UW |
8473 | } |
8474 | else if (fmt[i] == 'E') | |
8475 | { | |
8476 | for (j = 0; j < XVECLEN (*x, i); j++) | |
585539a1 | 8477 | replace_ltrel_base (&XVECEXP (*x, i, j)); |
aee4e0db UW |
8478 | } |
8479 | } | |
8480 | } | |
8481 | ||
8482 | ||
fd7643fb | 8483 | /* We keep a list of constants which we have to add to internal |
b2ccb744 UW |
8484 | constant tables in the middle of large functions. */ |
8485 | ||
e0654cf2 | 8486 | #define NR_C_MODES 32 |
ef4bddc2 | 8487 | machine_mode constant_modes[NR_C_MODES] = |
b2ccb744 | 8488 | { |
4dc19cc0 | 8489 | TFmode, TImode, TDmode, |
e0654cf2 AK |
8490 | V16QImode, V8HImode, V4SImode, V2DImode, V1TImode, |
8491 | V4SFmode, V2DFmode, V1TFmode, | |
4dc19cc0 | 8492 | DFmode, DImode, DDmode, |
085261c8 | 8493 | V8QImode, V4HImode, V2SImode, V1DImode, V2SFmode, V1DFmode, |
4dc19cc0 | 8494 | SFmode, SImode, SDmode, |
085261c8 | 8495 | V4QImode, V2HImode, V1SImode, V1SFmode, |
b2ccb744 | 8496 | HImode, |
085261c8 AK |
8497 | V2QImode, V1HImode, |
8498 | QImode, | |
8499 | V1QImode | |
b2ccb744 UW |
8500 | }; |
8501 | ||
b2ccb744 UW |
8502 | struct constant |
8503 | { | |
8504 | struct constant *next; | |
8505 | rtx value; | |
775c43d3 | 8506 | rtx_code_label *label; |
b2ccb744 UW |
8507 | }; |
8508 | ||
8509 | struct constant_pool | |
8510 | { | |
8511 | struct constant_pool *next; | |
775c43d3 DM |
8512 | rtx_insn *first_insn; |
8513 | rtx_insn *pool_insn; | |
aee4e0db | 8514 | bitmap insns; |
775c43d3 | 8515 | rtx_insn *emit_pool_after; |
b2ccb744 UW |
8516 | |
8517 | struct constant *constants[NR_C_MODES]; | |
9bb86f41 | 8518 | struct constant *execute; |
775c43d3 | 8519 | rtx_code_label *label; |
b2ccb744 UW |
8520 | int size; |
8521 | }; | |
8522 | ||
ab96de7e AS |
8523 | /* Allocate new constant_pool structure. */ |
8524 | ||
8525 | static struct constant_pool * | |
8526 | s390_alloc_pool (void) | |
8527 | { | |
8528 | struct constant_pool *pool; | |
8529 | int i; | |
8530 | ||
8531 | pool = (struct constant_pool *) xmalloc (sizeof *pool); | |
8532 | pool->next = NULL; | |
8533 | for (i = 0; i < NR_C_MODES; i++) | |
8534 | pool->constants[i] = NULL; | |
8535 | ||
8536 | pool->execute = NULL; | |
8537 | pool->label = gen_label_rtx (); | |
775c43d3 DM |
8538 | pool->first_insn = NULL; |
8539 | pool->pool_insn = NULL; | |
ab96de7e AS |
8540 | pool->insns = BITMAP_ALLOC (NULL); |
8541 | pool->size = 0; | |
775c43d3 | 8542 | pool->emit_pool_after = NULL; |
ab96de7e AS |
8543 | |
8544 | return pool; | |
8545 | } | |
b2ccb744 UW |
8546 | |
8547 | /* Create new constant pool covering instructions starting at INSN | |
8548 | and chain it to the end of POOL_LIST. */ | |
8549 | ||
8550 | static struct constant_pool * | |
775c43d3 | 8551 | s390_start_pool (struct constant_pool **pool_list, rtx_insn *insn) |
b2ccb744 UW |
8552 | { |
8553 | struct constant_pool *pool, **prev; | |
b2ccb744 | 8554 | |
5af2f3d3 | 8555 | pool = s390_alloc_pool (); |
b2ccb744 | 8556 | pool->first_insn = insn; |
aee4e0db | 8557 | |
b2ccb744 UW |
8558 | for (prev = pool_list; *prev; prev = &(*prev)->next) |
8559 | ; | |
8560 | *prev = pool; | |
8561 | ||
8562 | return pool; | |
8563 | } | |
8564 | ||
aee4e0db UW |
8565 | /* End range of instructions covered by POOL at INSN and emit |
8566 | placeholder insn representing the pool. */ | |
b2ccb744 UW |
8567 | |
8568 | static void | |
775c43d3 | 8569 | s390_end_pool (struct constant_pool *pool, rtx_insn *insn) |
b2ccb744 | 8570 | { |
aee4e0db UW |
8571 | rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */); |
8572 | ||
8573 | if (!insn) | |
8574 | insn = get_last_insn (); | |
8575 | ||
8576 | pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn); | |
8577 | INSN_ADDRESSES_NEW (pool->pool_insn, -1); | |
8578 | } | |
8579 | ||
8580 | /* Add INSN to the list of insns covered by POOL. */ | |
8581 | ||
8582 | static void | |
9c808aad | 8583 | s390_add_pool_insn (struct constant_pool *pool, rtx insn) |
aee4e0db UW |
8584 | { |
8585 | bitmap_set_bit (pool->insns, INSN_UID (insn)); | |
b2ccb744 UW |
8586 | } |
8587 | ||
8588 | /* Return pool out of POOL_LIST that covers INSN. */ | |
8589 | ||
8590 | static struct constant_pool * | |
9c808aad | 8591 | s390_find_pool (struct constant_pool *pool_list, rtx insn) |
b2ccb744 | 8592 | { |
b2ccb744 UW |
8593 | struct constant_pool *pool; |
8594 | ||
b2ccb744 | 8595 | for (pool = pool_list; pool; pool = pool->next) |
aee4e0db | 8596 | if (bitmap_bit_p (pool->insns, INSN_UID (insn))) |
b2ccb744 UW |
8597 | break; |
8598 | ||
8599 | return pool; | |
8600 | } | |
8601 | ||
aee4e0db | 8602 | /* Add constant VAL of mode MODE to the constant pool POOL. */ |
b2ccb744 | 8603 | |
aee4e0db | 8604 | static void |
ef4bddc2 | 8605 | s390_add_constant (struct constant_pool *pool, rtx val, machine_mode mode) |
b2ccb744 UW |
8606 | { |
8607 | struct constant *c; | |
b2ccb744 UW |
8608 | int i; |
8609 | ||
8610 | for (i = 0; i < NR_C_MODES; i++) | |
8611 | if (constant_modes[i] == mode) | |
8612 | break; | |
8d933e31 | 8613 | gcc_assert (i != NR_C_MODES); |
b2ccb744 UW |
8614 | |
8615 | for (c = pool->constants[i]; c != NULL; c = c->next) | |
8616 | if (rtx_equal_p (val, c->value)) | |
8617 | break; | |
8618 | ||
8619 | if (c == NULL) | |
8620 | { | |
8621 | c = (struct constant *) xmalloc (sizeof *c); | |
8622 | c->value = val; | |
8623 | c->label = gen_label_rtx (); | |
8624 | c->next = pool->constants[i]; | |
8625 | pool->constants[i] = c; | |
8626 | pool->size += GET_MODE_SIZE (mode); | |
8627 | } | |
aee4e0db | 8628 | } |
b2ccb744 | 8629 | |
dc66391d RS |
8630 | /* Return an rtx that represents the offset of X from the start of |
8631 | pool POOL. */ | |
8632 | ||
8633 | static rtx | |
8634 | s390_pool_offset (struct constant_pool *pool, rtx x) | |
8635 | { | |
8636 | rtx label; | |
8637 | ||
8638 | label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label); | |
8639 | x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label), | |
8640 | UNSPEC_POOL_OFFSET); | |
8641 | return gen_rtx_CONST (GET_MODE (x), x); | |
8642 | } | |
8643 | ||
aee4e0db UW |
8644 | /* Find constant VAL of mode MODE in the constant pool POOL. |
8645 | Return an RTX describing the distance from the start of | |
8646 | the pool to the location of the new constant. */ | |
c7453384 | 8647 | |
aee4e0db | 8648 | static rtx |
9c808aad | 8649 | s390_find_constant (struct constant_pool *pool, rtx val, |
ef4bddc2 | 8650 | machine_mode mode) |
aee4e0db UW |
8651 | { |
8652 | struct constant *c; | |
aee4e0db | 8653 | int i; |
c7453384 | 8654 | |
aee4e0db UW |
8655 | for (i = 0; i < NR_C_MODES; i++) |
8656 | if (constant_modes[i] == mode) | |
8657 | break; | |
8d933e31 | 8658 | gcc_assert (i != NR_C_MODES); |
c7453384 | 8659 | |
aee4e0db UW |
8660 | for (c = pool->constants[i]; c != NULL; c = c->next) |
8661 | if (rtx_equal_p (val, c->value)) | |
8662 | break; | |
c7453384 | 8663 | |
8d933e31 | 8664 | gcc_assert (c); |
c7453384 | 8665 | |
dc66391d | 8666 | return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label)); |
b2ccb744 UW |
8667 | } |
8668 | ||
ab96de7e AS |
8669 | /* Check whether INSN is an execute. Return the label_ref to its |
8670 | execute target template if so, NULL_RTX otherwise. */ | |
8671 | ||
8672 | static rtx | |
8673 | s390_execute_label (rtx insn) | |
8674 | { | |
b64925dc | 8675 | if (NONJUMP_INSN_P (insn) |
ab96de7e AS |
8676 | && GET_CODE (PATTERN (insn)) == PARALLEL |
8677 | && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC | |
8678 | && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE) | |
8679 | return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2); | |
8680 | ||
8681 | return NULL_RTX; | |
8682 | } | |
8683 | ||
9bb86f41 UW |
8684 | /* Add execute target for INSN to the constant pool POOL. */ |
8685 | ||
8686 | static void | |
8687 | s390_add_execute (struct constant_pool *pool, rtx insn) | |
8688 | { | |
8689 | struct constant *c; | |
8690 | ||
8691 | for (c = pool->execute; c != NULL; c = c->next) | |
8692 | if (INSN_UID (insn) == INSN_UID (c->value)) | |
8693 | break; | |
8694 | ||
8695 | if (c == NULL) | |
8696 | { | |
9bb86f41 UW |
8697 | c = (struct constant *) xmalloc (sizeof *c); |
8698 | c->value = insn; | |
d24959df | 8699 | c->label = gen_label_rtx (); |
9bb86f41 UW |
8700 | c->next = pool->execute; |
8701 | pool->execute = c; | |
d24959df | 8702 | pool->size += 6; |
9bb86f41 UW |
8703 | } |
8704 | } | |
8705 | ||
8706 | /* Find execute target for INSN in the constant pool POOL. | |
8707 | Return an RTX describing the distance from the start of | |
8708 | the pool to the location of the execute target. */ | |
8709 | ||
8710 | static rtx | |
8711 | s390_find_execute (struct constant_pool *pool, rtx insn) | |
8712 | { | |
8713 | struct constant *c; | |
9bb86f41 UW |
8714 | |
8715 | for (c = pool->execute; c != NULL; c = c->next) | |
8716 | if (INSN_UID (insn) == INSN_UID (c->value)) | |
8717 | break; | |
8718 | ||
8d933e31 | 8719 | gcc_assert (c); |
9bb86f41 | 8720 | |
dc66391d | 8721 | return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label)); |
9bb86f41 UW |
8722 | } |
8723 | ||
ab96de7e | 8724 | /* For an execute INSN, extract the execute target template. */ |
9bb86f41 UW |
8725 | |
8726 | static rtx | |
ab96de7e | 8727 | s390_execute_target (rtx insn) |
9bb86f41 | 8728 | { |
ab96de7e AS |
8729 | rtx pattern = PATTERN (insn); |
8730 | gcc_assert (s390_execute_label (insn)); | |
9bb86f41 UW |
8731 | |
8732 | if (XVECLEN (pattern, 0) == 2) | |
8733 | { | |
8734 | pattern = copy_rtx (XVECEXP (pattern, 0, 1)); | |
8735 | } | |
8736 | else | |
8737 | { | |
8738 | rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1); | |
8739 | int i; | |
8740 | ||
8741 | for (i = 0; i < XVECLEN (pattern, 0) - 1; i++) | |
8742 | RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1)); | |
8743 | ||
8744 | pattern = gen_rtx_PARALLEL (VOIDmode, vec); | |
8745 | } | |
8746 | ||
8747 | return pattern; | |
8748 | } | |
8749 | ||
8750 | /* Indicate that INSN cannot be duplicated. This is the case for | |
8751 | execute insns that carry a unique label. */ | |
8752 | ||
8753 | static bool | |
ac44248e | 8754 | s390_cannot_copy_insn_p (rtx_insn *insn) |
9bb86f41 UW |
8755 | { |
8756 | rtx label = s390_execute_label (insn); | |
8757 | return label && label != const0_rtx; | |
8758 | } | |
8759 | ||
5af2f3d3 UW |
8760 | /* Dump out the constants in POOL. If REMOTE_LABEL is true, |
8761 | do not emit the pool base label. */ | |
b2ccb744 | 8762 | |
9bb86f41 | 8763 | static void |
5af2f3d3 | 8764 | s390_dump_pool (struct constant_pool *pool, bool remote_label) |
b2ccb744 UW |
8765 | { |
8766 | struct constant *c; | |
775c43d3 | 8767 | rtx_insn *insn = pool->pool_insn; |
b2ccb744 UW |
8768 | int i; |
8769 | ||
9bb86f41 UW |
8770 | /* Switch to rodata section. */ |
8771 | if (TARGET_CPU_ZARCH) | |
8772 | { | |
8773 | insn = emit_insn_after (gen_pool_section_start (), insn); | |
8774 | INSN_ADDRESSES_NEW (insn, -1); | |
8775 | } | |
8776 | ||
8777 | /* Ensure minimum pool alignment. */ | |
9e8327e3 | 8778 | if (TARGET_CPU_ZARCH) |
9bb86f41 | 8779 | insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn); |
b2ccb744 | 8780 | else |
9bb86f41 | 8781 | insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn); |
b2ccb744 UW |
8782 | INSN_ADDRESSES_NEW (insn, -1); |
8783 | ||
9bb86f41 | 8784 | /* Emit pool base label. */ |
5af2f3d3 UW |
8785 | if (!remote_label) |
8786 | { | |
8787 | insn = emit_label_after (pool->label, insn); | |
8788 | INSN_ADDRESSES_NEW (insn, -1); | |
8789 | } | |
b2ccb744 UW |
8790 | |
8791 | /* Dump constants in descending alignment requirement order, | |
8792 | ensuring proper alignment for every constant. */ | |
8793 | for (i = 0; i < NR_C_MODES; i++) | |
8794 | for (c = pool->constants[i]; c; c = c->next) | |
8795 | { | |
fd7643fb | 8796 | /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */ |
77340500 | 8797 | rtx value = copy_rtx (c->value); |
aee4e0db UW |
8798 | if (GET_CODE (value) == CONST |
8799 | && GET_CODE (XEXP (value, 0)) == UNSPEC | |
fd7643fb | 8800 | && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET |
aee4e0db | 8801 | && XVECLEN (XEXP (value, 0), 0) == 1) |
dc66391d | 8802 | value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0)); |
aee4e0db | 8803 | |
b2ccb744 UW |
8804 | insn = emit_label_after (c->label, insn); |
8805 | INSN_ADDRESSES_NEW (insn, -1); | |
416cf582 | 8806 | |
38899e29 | 8807 | value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i], |
416cf582 UW |
8808 | gen_rtvec (1, value), |
8809 | UNSPECV_POOL_ENTRY); | |
8810 | insn = emit_insn_after (value, insn); | |
b2ccb744 UW |
8811 | INSN_ADDRESSES_NEW (insn, -1); |
8812 | } | |
8813 | ||
9bb86f41 UW |
8814 | /* Ensure minimum alignment for instructions. */ |
8815 | insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn); | |
b2ccb744 UW |
8816 | INSN_ADDRESSES_NEW (insn, -1); |
8817 | ||
9bb86f41 UW |
8818 | /* Output in-pool execute template insns. */ |
8819 | for (c = pool->execute; c; c = c->next) | |
8820 | { | |
9bb86f41 UW |
8821 | insn = emit_label_after (c->label, insn); |
8822 | INSN_ADDRESSES_NEW (insn, -1); | |
8823 | ||
8824 | insn = emit_insn_after (s390_execute_target (c->value), insn); | |
8825 | INSN_ADDRESSES_NEW (insn, -1); | |
8826 | } | |
8827 | ||
8828 | /* Switch back to previous section. */ | |
8829 | if (TARGET_CPU_ZARCH) | |
8830 | { | |
8831 | insn = emit_insn_after (gen_pool_section_end (), insn); | |
8832 | INSN_ADDRESSES_NEW (insn, -1); | |
8833 | } | |
8834 | ||
b2ccb744 UW |
8835 | insn = emit_barrier_after (insn); |
8836 | INSN_ADDRESSES_NEW (insn, -1); | |
8837 | ||
aee4e0db UW |
8838 | /* Remove placeholder insn. */ |
8839 | remove_insn (pool->pool_insn); | |
9bb86f41 UW |
8840 | } |
8841 | ||
b2ccb744 UW |
8842 | /* Free all memory used by POOL. */ |
8843 | ||
8844 | static void | |
9c808aad | 8845 | s390_free_pool (struct constant_pool *pool) |
b2ccb744 | 8846 | { |
9bb86f41 | 8847 | struct constant *c, *next; |
b2ccb744 UW |
8848 | int i; |
8849 | ||
8850 | for (i = 0; i < NR_C_MODES; i++) | |
9bb86f41 UW |
8851 | for (c = pool->constants[i]; c; c = next) |
8852 | { | |
8853 | next = c->next; | |
8854 | free (c); | |
8855 | } | |
8856 | ||
8857 | for (c = pool->execute; c; c = next) | |
b2ccb744 | 8858 | { |
9bb86f41 UW |
8859 | next = c->next; |
8860 | free (c); | |
b2ccb744 UW |
8861 | } |
8862 | ||
7b210806 | 8863 | BITMAP_FREE (pool->insns); |
b2ccb744 | 8864 | free (pool); |
c7453384 | 8865 | } |
b2ccb744 | 8866 | |
b2ccb744 | 8867 | |
5af2f3d3 UW |
8868 | /* Collect main literal pool. Return NULL on overflow. */ |
8869 | ||
8870 | static struct constant_pool * | |
8871 | s390_mainpool_start (void) | |
8872 | { | |
8873 | struct constant_pool *pool; | |
775c43d3 | 8874 | rtx_insn *insn; |
5af2f3d3 UW |
8875 | |
8876 | pool = s390_alloc_pool (); | |
8877 | ||
8878 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
8879 | { | |
b64925dc | 8880 | if (NONJUMP_INSN_P (insn) |
585539a1 UW |
8881 | && GET_CODE (PATTERN (insn)) == SET |
8882 | && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE | |
8883 | && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL) | |
5af2f3d3 | 8884 | { |
177bc204 RS |
8885 | /* There might be two main_pool instructions if base_reg |
8886 | is call-clobbered; one for shrink-wrapped code and one | |
8887 | for the rest. We want to keep the first. */ | |
8888 | if (pool->pool_insn) | |
8889 | { | |
8890 | insn = PREV_INSN (insn); | |
8891 | delete_insn (NEXT_INSN (insn)); | |
8892 | continue; | |
8893 | } | |
5af2f3d3 UW |
8894 | pool->pool_insn = insn; |
8895 | } | |
8896 | ||
d24959df | 8897 | if (!TARGET_CPU_ZARCH && s390_execute_label (insn)) |
9bb86f41 UW |
8898 | { |
8899 | s390_add_execute (pool, insn); | |
8900 | } | |
b64925dc | 8901 | else if (NONJUMP_INSN_P (insn) || CALL_P (insn)) |
5af2f3d3 UW |
8902 | { |
8903 | rtx pool_ref = NULL_RTX; | |
8904 | find_constant_pool_ref (PATTERN (insn), &pool_ref); | |
8905 | if (pool_ref) | |
8906 | { | |
8907 | rtx constant = get_pool_constant (pool_ref); | |
ef4bddc2 | 8908 | machine_mode mode = get_pool_mode (pool_ref); |
5af2f3d3 UW |
8909 | s390_add_constant (pool, constant, mode); |
8910 | } | |
8911 | } | |
03870a04 AK |
8912 | |
8913 | /* If hot/cold partitioning is enabled we have to make sure that | |
8914 | the literal pool is emitted in the same section where the | |
8915 | initialization of the literal pool base pointer takes place. | |
8916 | emit_pool_after is only used in the non-overflow case on non | |
8917 | Z cpus where we can emit the literal pool at the end of the | |
8918 | function body within the text section. */ | |
8919 | if (NOTE_P (insn) | |
b49326f1 AK |
8920 | && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS |
8921 | && !pool->emit_pool_after) | |
8922 | pool->emit_pool_after = PREV_INSN (insn); | |
5af2f3d3 UW |
8923 | } |
8924 | ||
8d933e31 | 8925 | gcc_assert (pool->pool_insn || pool->size == 0); |
5af2f3d3 UW |
8926 | |
8927 | if (pool->size >= 4096) | |
8928 | { | |
d76e8439 UW |
8929 | /* We're going to chunkify the pool, so remove the main |
8930 | pool placeholder insn. */ | |
8931 | remove_insn (pool->pool_insn); | |
8932 | ||
5af2f3d3 UW |
8933 | s390_free_pool (pool); |
8934 | pool = NULL; | |
8935 | } | |
8936 | ||
03870a04 AK |
8937 | /* If the functions ends with the section where the literal pool |
8938 | should be emitted set the marker to its end. */ | |
b49326f1 | 8939 | if (pool && !pool->emit_pool_after) |
03870a04 AK |
8940 | pool->emit_pool_after = get_last_insn (); |
8941 | ||
5af2f3d3 UW |
8942 | return pool; |
8943 | } | |
8944 | ||
8945 | /* POOL holds the main literal pool as collected by s390_mainpool_start. | |
8946 | Modify the current function to output the pool constants as well as | |
585539a1 | 8947 | the pool register setup instruction. */ |
5af2f3d3 UW |
8948 | |
8949 | static void | |
585539a1 | 8950 | s390_mainpool_finish (struct constant_pool *pool) |
5af2f3d3 | 8951 | { |
91086990 | 8952 | rtx base_reg = cfun->machine->base_reg; |
5af2f3d3 UW |
8953 | |
8954 | /* If the pool is empty, we're done. */ | |
8955 | if (pool->size == 0) | |
8956 | { | |
91086990 UW |
8957 | /* We don't actually need a base register after all. */ |
8958 | cfun->machine->base_reg = NULL_RTX; | |
8959 | ||
8960 | if (pool->pool_insn) | |
8961 | remove_insn (pool->pool_insn); | |
5af2f3d3 UW |
8962 | s390_free_pool (pool); |
8963 | return; | |
8964 | } | |
8965 | ||
8966 | /* We need correct insn addresses. */ | |
8967 | shorten_branches (get_insns ()); | |
8968 | ||
9e8327e3 | 8969 | /* On zSeries, we use a LARL to load the pool register. The pool is |
5af2f3d3 | 8970 | located in the .rodata section, so we emit it after the function. */ |
9e8327e3 | 8971 | if (TARGET_CPU_ZARCH) |
5af2f3d3 | 8972 | { |
17f385d8 DM |
8973 | rtx set = gen_main_base_64 (base_reg, pool->label); |
8974 | rtx_insn *insn = emit_insn_after (set, pool->pool_insn); | |
5af2f3d3 UW |
8975 | INSN_ADDRESSES_NEW (insn, -1); |
8976 | remove_insn (pool->pool_insn); | |
38899e29 EC |
8977 | |
8978 | insn = get_last_insn (); | |
5af2f3d3 UW |
8979 | pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn); |
8980 | INSN_ADDRESSES_NEW (pool->pool_insn, -1); | |
8981 | ||
8982 | s390_dump_pool (pool, 0); | |
8983 | } | |
8984 | ||
9e8327e3 | 8985 | /* On S/390, if the total size of the function's code plus literal pool |
5af2f3d3 UW |
8986 | does not exceed 4096 bytes, we use BASR to set up a function base |
8987 | pointer, and emit the literal pool at the end of the function. */ | |
03870a04 | 8988 | else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after)) |
5af2f3d3 UW |
8989 | + pool->size + 8 /* alignment slop */ < 4096) |
8990 | { | |
17f385d8 DM |
8991 | rtx set = gen_main_base_31_small (base_reg, pool->label); |
8992 | rtx_insn *insn = emit_insn_after (set, pool->pool_insn); | |
5af2f3d3 UW |
8993 | INSN_ADDRESSES_NEW (insn, -1); |
8994 | remove_insn (pool->pool_insn); | |
8995 | ||
8996 | insn = emit_label_after (pool->label, insn); | |
8997 | INSN_ADDRESSES_NEW (insn, -1); | |
8998 | ||
03870a04 AK |
8999 | /* emit_pool_after will be set by s390_mainpool_start to the |
9000 | last insn of the section where the literal pool should be | |
9001 | emitted. */ | |
9002 | insn = pool->emit_pool_after; | |
9003 | ||
5af2f3d3 UW |
9004 | pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn); |
9005 | INSN_ADDRESSES_NEW (pool->pool_insn, -1); | |
9006 | ||
9007 | s390_dump_pool (pool, 1); | |
9008 | } | |
9009 | ||
9010 | /* Otherwise, we emit an inline literal pool and use BASR to branch | |
9011 | over it, setting up the pool register at the same time. */ | |
9012 | else | |
9013 | { | |
17f385d8 | 9014 | rtx_code_label *pool_end = gen_label_rtx (); |
5af2f3d3 | 9015 | |
17f385d8 DM |
9016 | rtx pat = gen_main_base_31_large (base_reg, pool->label, pool_end); |
9017 | rtx_insn *insn = emit_jump_insn_after (pat, pool->pool_insn); | |
b0a1ac21 | 9018 | JUMP_LABEL (insn) = pool_end; |
5af2f3d3 UW |
9019 | INSN_ADDRESSES_NEW (insn, -1); |
9020 | remove_insn (pool->pool_insn); | |
9021 | ||
9022 | insn = emit_label_after (pool->label, insn); | |
9023 | INSN_ADDRESSES_NEW (insn, -1); | |
9024 | ||
9025 | pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn); | |
9026 | INSN_ADDRESSES_NEW (pool->pool_insn, -1); | |
9027 | ||
9028 | insn = emit_label_after (pool_end, pool->pool_insn); | |
9029 | INSN_ADDRESSES_NEW (insn, -1); | |
9030 | ||
9031 | s390_dump_pool (pool, 1); | |
9032 | } | |
9033 | ||
9034 | ||
9035 | /* Replace all literal pool references. */ | |
9036 | ||
b32d5189 | 9037 | for (rtx_insn *insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
5af2f3d3 UW |
9038 | { |
9039 | if (INSN_P (insn)) | |
585539a1 | 9040 | replace_ltrel_base (&PATTERN (insn)); |
5af2f3d3 | 9041 | |
b64925dc | 9042 | if (NONJUMP_INSN_P (insn) || CALL_P (insn)) |
5af2f3d3 UW |
9043 | { |
9044 | rtx addr, pool_ref = NULL_RTX; | |
9045 | find_constant_pool_ref (PATTERN (insn), &pool_ref); | |
9046 | if (pool_ref) | |
9047 | { | |
9bb86f41 UW |
9048 | if (s390_execute_label (insn)) |
9049 | addr = s390_find_execute (pool, insn); | |
9050 | else | |
9051 | addr = s390_find_constant (pool, get_pool_constant (pool_ref), | |
9052 | get_pool_mode (pool_ref)); | |
9053 | ||
5af2f3d3 UW |
9054 | replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr); |
9055 | INSN_CODE (insn) = -1; | |
9056 | } | |
9057 | } | |
9058 | } | |
9059 | ||
9060 | ||
9061 | /* Free the pool. */ | |
9062 | s390_free_pool (pool); | |
9063 | } | |
9064 | ||
9065 | /* POOL holds the main literal pool as collected by s390_mainpool_start. | |
9066 | We have decided we cannot use this pool, so revert all changes | |
9067 | to the current function that were done by s390_mainpool_start. */ | |
9068 | static void | |
9069 | s390_mainpool_cancel (struct constant_pool *pool) | |
9070 | { | |
9071 | /* We didn't actually change the instruction stream, so simply | |
9072 | free the pool memory. */ | |
9073 | s390_free_pool (pool); | |
9074 | } | |
9075 | ||
9076 | ||
585539a1 | 9077 | /* Chunkify the literal pool. */ |
9db1d521 | 9078 | |
b2ccb744 UW |
9079 | #define S390_POOL_CHUNK_MIN 0xc00 |
9080 | #define S390_POOL_CHUNK_MAX 0xe00 | |
9081 | ||
c7453384 | 9082 | static struct constant_pool * |
585539a1 | 9083 | s390_chunkify_start (void) |
9db1d521 | 9084 | { |
b2ccb744 UW |
9085 | struct constant_pool *curr_pool = NULL, *pool_list = NULL; |
9086 | int extra_size = 0; | |
9087 | bitmap far_labels; | |
fd7643fb | 9088 | rtx pending_ltrel = NULL_RTX; |
775c43d3 | 9089 | rtx_insn *insn; |
9db1d521 | 9090 | |
9c808aad | 9091 | rtx (*gen_reload_base) (rtx, rtx) = |
9e8327e3 | 9092 | TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31; |
aee4e0db UW |
9093 | |
9094 | ||
c3cc6b78 UW |
9095 | /* We need correct insn addresses. */ |
9096 | ||
9097 | shorten_branches (get_insns ()); | |
9098 | ||
fd7643fb | 9099 | /* Scan all insns and move literals to pool chunks. */ |
13e58269 | 9100 | |
13e58269 | 9101 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
9db1d521 | 9102 | { |
03870a04 AK |
9103 | bool section_switch_p = false; |
9104 | ||
fd7643fb UW |
9105 | /* Check for pending LTREL_BASE. */ |
9106 | if (INSN_P (insn)) | |
9107 | { | |
9108 | rtx ltrel_base = find_ltrel_base (PATTERN (insn)); | |
9109 | if (ltrel_base) | |
9110 | { | |
8d933e31 AS |
9111 | gcc_assert (ltrel_base == pending_ltrel); |
9112 | pending_ltrel = NULL_RTX; | |
fd7643fb UW |
9113 | } |
9114 | } | |
9115 | ||
d24959df | 9116 | if (!TARGET_CPU_ZARCH && s390_execute_label (insn)) |
9bb86f41 UW |
9117 | { |
9118 | if (!curr_pool) | |
9119 | curr_pool = s390_start_pool (&pool_list, insn); | |
9120 | ||
9121 | s390_add_execute (curr_pool, insn); | |
9122 | s390_add_pool_insn (curr_pool, insn); | |
9123 | } | |
b64925dc | 9124 | else if (NONJUMP_INSN_P (insn) || CALL_P (insn)) |
b2ccb744 | 9125 | { |
aee4e0db | 9126 | rtx pool_ref = NULL_RTX; |
b2ccb744 UW |
9127 | find_constant_pool_ref (PATTERN (insn), &pool_ref); |
9128 | if (pool_ref) | |
9129 | { | |
fd7643fb | 9130 | rtx constant = get_pool_constant (pool_ref); |
ef4bddc2 | 9131 | machine_mode mode = get_pool_mode (pool_ref); |
fd7643fb | 9132 | |
b2ccb744 UW |
9133 | if (!curr_pool) |
9134 | curr_pool = s390_start_pool (&pool_list, insn); | |
9135 | ||
fd7643fb | 9136 | s390_add_constant (curr_pool, constant, mode); |
aee4e0db | 9137 | s390_add_pool_insn (curr_pool, insn); |
aee4e0db | 9138 | |
fd7643fb UW |
9139 | /* Don't split the pool chunk between a LTREL_OFFSET load |
9140 | and the corresponding LTREL_BASE. */ | |
9141 | if (GET_CODE (constant) == CONST | |
9142 | && GET_CODE (XEXP (constant, 0)) == UNSPEC | |
9143 | && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET) | |
9144 | { | |
8d933e31 | 9145 | gcc_assert (!pending_ltrel); |
fd7643fb UW |
9146 | pending_ltrel = pool_ref; |
9147 | } | |
b2ccb744 UW |
9148 | } |
9149 | } | |
9150 | ||
39718607 | 9151 | if (JUMP_P (insn) || JUMP_TABLE_DATA_P (insn) || LABEL_P (insn)) |
fd7643fb UW |
9152 | { |
9153 | if (curr_pool) | |
9154 | s390_add_pool_insn (curr_pool, insn); | |
9155 | /* An LTREL_BASE must follow within the same basic block. */ | |
8d933e31 | 9156 | gcc_assert (!pending_ltrel); |
fd7643fb | 9157 | } |
aee4e0db | 9158 | |
00fbd5c8 JJ |
9159 | if (NOTE_P (insn)) |
9160 | switch (NOTE_KIND (insn)) | |
9161 | { | |
9162 | case NOTE_INSN_SWITCH_TEXT_SECTIONS: | |
9163 | section_switch_p = true; | |
9164 | break; | |
9165 | case NOTE_INSN_VAR_LOCATION: | |
9166 | case NOTE_INSN_CALL_ARG_LOCATION: | |
9167 | continue; | |
9168 | default: | |
9169 | break; | |
9170 | } | |
03870a04 | 9171 | |
c7453384 | 9172 | if (!curr_pool |
b2ccb744 UW |
9173 | || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn) |
9174 | || INSN_ADDRESSES (INSN_UID (insn)) == -1) | |
9db1d521 | 9175 | continue; |
13e58269 | 9176 | |
9e8327e3 | 9177 | if (TARGET_CPU_ZARCH) |
9db1d521 | 9178 | { |
b2ccb744 UW |
9179 | if (curr_pool->size < S390_POOL_CHUNK_MAX) |
9180 | continue; | |
13e58269 | 9181 | |
775c43d3 | 9182 | s390_end_pool (curr_pool, NULL); |
b2ccb744 UW |
9183 | curr_pool = NULL; |
9184 | } | |
9185 | else | |
9db1d521 | 9186 | { |
b2ccb744 | 9187 | int chunk_size = INSN_ADDRESSES (INSN_UID (insn)) |
9c808aad | 9188 | - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn)) |
b2ccb744 UW |
9189 | + extra_size; |
9190 | ||
9191 | /* We will later have to insert base register reload insns. | |
9192 | Those will have an effect on code size, which we need to | |
9193 | consider here. This calculation makes rather pessimistic | |
9194 | worst-case assumptions. */ | |
b64925dc | 9195 | if (LABEL_P (insn)) |
b2ccb744 | 9196 | extra_size += 6; |
b2ccb744 UW |
9197 | |
9198 | if (chunk_size < S390_POOL_CHUNK_MIN | |
03870a04 AK |
9199 | && curr_pool->size < S390_POOL_CHUNK_MIN |
9200 | && !section_switch_p) | |
b2ccb744 UW |
9201 | continue; |
9202 | ||
9203 | /* Pool chunks can only be inserted after BARRIERs ... */ | |
b64925dc | 9204 | if (BARRIER_P (insn)) |
b2ccb744 UW |
9205 | { |
9206 | s390_end_pool (curr_pool, insn); | |
9207 | curr_pool = NULL; | |
9208 | extra_size = 0; | |
9209 | } | |
9210 | ||
9211 | /* ... so if we don't find one in time, create one. */ | |
03870a04 AK |
9212 | else if (chunk_size > S390_POOL_CHUNK_MAX |
9213 | || curr_pool->size > S390_POOL_CHUNK_MAX | |
9214 | || section_switch_p) | |
b2ccb744 | 9215 | { |
775c43d3 | 9216 | rtx_insn *label, *jump, *barrier, *next, *prev; |
b2ccb744 | 9217 | |
03870a04 AK |
9218 | if (!section_switch_p) |
9219 | { | |
9220 | /* We can insert the barrier only after a 'real' insn. */ | |
b64925dc | 9221 | if (! NONJUMP_INSN_P (insn) && ! CALL_P (insn)) |
03870a04 AK |
9222 | continue; |
9223 | if (get_attr_length (insn) == 0) | |
9224 | continue; | |
9225 | /* Don't separate LTREL_BASE from the corresponding | |
00fbd5c8 | 9226 | LTREL_OFFSET load. */ |
03870a04 AK |
9227 | if (pending_ltrel) |
9228 | continue; | |
00fbd5c8 JJ |
9229 | next = insn; |
9230 | do | |
9231 | { | |
9232 | insn = next; | |
9233 | next = NEXT_INSN (insn); | |
9234 | } | |
9235 | while (next | |
9236 | && NOTE_P (next) | |
9237 | && (NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION | |
9238 | || NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION)); | |
03870a04 AK |
9239 | } |
9240 | else | |
9241 | { | |
9242 | gcc_assert (!pending_ltrel); | |
9243 | ||
9244 | /* The old pool has to end before the section switch | |
9245 | note in order to make it part of the current | |
9246 | section. */ | |
9247 | insn = PREV_INSN (insn); | |
9248 | } | |
aee4e0db | 9249 | |
9c808aad | 9250 | label = gen_label_rtx (); |
00fbd5c8 JJ |
9251 | prev = insn; |
9252 | if (prev && NOTE_P (prev)) | |
9253 | prev = prev_nonnote_insn (prev); | |
9254 | if (prev) | |
9255 | jump = emit_jump_insn_after_setloc (gen_jump (label), insn, | |
9d12bc68 | 9256 | INSN_LOCATION (prev)); |
00fbd5c8 JJ |
9257 | else |
9258 | jump = emit_jump_insn_after_noloc (gen_jump (label), insn); | |
b2ccb744 UW |
9259 | barrier = emit_barrier_after (jump); |
9260 | insn = emit_label_after (label, barrier); | |
9261 | JUMP_LABEL (jump) = label; | |
9262 | LABEL_NUSES (label) = 1; | |
9263 | ||
aee4e0db UW |
9264 | INSN_ADDRESSES_NEW (jump, -1); |
9265 | INSN_ADDRESSES_NEW (barrier, -1); | |
b2ccb744 UW |
9266 | INSN_ADDRESSES_NEW (insn, -1); |
9267 | ||
9268 | s390_end_pool (curr_pool, barrier); | |
9269 | curr_pool = NULL; | |
9270 | extra_size = 0; | |
9271 | } | |
13e58269 | 9272 | } |
9db1d521 | 9273 | } |
ce50cae8 | 9274 | |
aee4e0db | 9275 | if (curr_pool) |
775c43d3 | 9276 | s390_end_pool (curr_pool, NULL); |
8d933e31 | 9277 | gcc_assert (!pending_ltrel); |
b2ccb744 | 9278 | |
c7453384 | 9279 | /* Find all labels that are branched into |
13e58269 | 9280 | from an insn belonging to a different chunk. */ |
ce50cae8 | 9281 | |
7b210806 | 9282 | far_labels = BITMAP_ALLOC (NULL); |
6bc627b3 | 9283 | |
13e58269 | 9284 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
9db1d521 | 9285 | { |
8942ee0f | 9286 | rtx_jump_table_data *table; |
966f97ac | 9287 | |
b2ccb744 UW |
9288 | /* Labels marked with LABEL_PRESERVE_P can be target |
9289 | of non-local jumps, so we have to mark them. | |
9290 | The same holds for named labels. | |
9291 | ||
9292 | Don't do that, however, if it is the label before | |
9293 | a jump table. */ | |
9294 | ||
b64925dc | 9295 | if (LABEL_P (insn) |
b2ccb744 UW |
9296 | && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn))) |
9297 | { | |
775c43d3 | 9298 | rtx_insn *vec_insn = NEXT_INSN (insn); |
34f0d87a | 9299 | if (! vec_insn || ! JUMP_TABLE_DATA_P (vec_insn)) |
b2ccb744 UW |
9300 | bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn)); |
9301 | } | |
966f97ac JJ |
9302 | /* Check potential targets in a table jump (casesi_jump). */ |
9303 | else if (tablejump_p (insn, NULL, &table)) | |
9304 | { | |
9305 | rtx vec_pat = PATTERN (table); | |
9306 | int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC; | |
9307 | ||
9308 | for (i = 0; i < XVECLEN (vec_pat, diff_p); i++) | |
9309 | { | |
9310 | rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0); | |
b2ccb744 | 9311 | |
966f97ac JJ |
9312 | if (s390_find_pool (pool_list, label) |
9313 | != s390_find_pool (pool_list, insn)) | |
9314 | bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label)); | |
9315 | } | |
9316 | } | |
9317 | /* If we have a direct jump (conditional or unconditional), | |
9318 | check all potential targets. */ | |
b64925dc | 9319 | else if (JUMP_P (insn)) |
13e58269 | 9320 | { |
966f97ac | 9321 | rtx pat = PATTERN (insn); |
5fdc1e5d | 9322 | |
966f97ac | 9323 | if (GET_CODE (pat) == PARALLEL) |
0a3bdf9d UW |
9324 | pat = XVECEXP (pat, 0, 0); |
9325 | ||
966f97ac JJ |
9326 | if (GET_CODE (pat) == SET) |
9327 | { | |
aee4e0db | 9328 | rtx label = JUMP_LABEL (insn); |
177bc204 | 9329 | if (label && !ANY_RETURN_P (label)) |
13e58269 | 9330 | { |
966f97ac | 9331 | if (s390_find_pool (pool_list, label) |
b2ccb744 UW |
9332 | != s390_find_pool (pool_list, insn)) |
9333 | bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label)); | |
13e58269 | 9334 | } |
b2ccb744 | 9335 | } |
966f97ac | 9336 | } |
9db1d521 | 9337 | } |
ce50cae8 | 9338 | |
b2ccb744 UW |
9339 | /* Insert base register reload insns before every pool. */ |
9340 | ||
9341 | for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next) | |
aee4e0db | 9342 | { |
f4aa3848 | 9343 | rtx new_insn = gen_reload_base (cfun->machine->base_reg, |
585539a1 | 9344 | curr_pool->label); |
775c43d3 | 9345 | rtx_insn *insn = curr_pool->first_insn; |
aee4e0db UW |
9346 | INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1); |
9347 | } | |
b2ccb744 UW |
9348 | |
9349 | /* Insert base register reload insns at every far label. */ | |
13e58269 | 9350 | |
13e58269 | 9351 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
b64925dc | 9352 | if (LABEL_P (insn) |
b2ccb744 UW |
9353 | && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn))) |
9354 | { | |
9355 | struct constant_pool *pool = s390_find_pool (pool_list, insn); | |
9356 | if (pool) | |
9357 | { | |
f4aa3848 | 9358 | rtx new_insn = gen_reload_base (cfun->machine->base_reg, |
585539a1 | 9359 | pool->label); |
aee4e0db | 9360 | INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1); |
b2ccb744 UW |
9361 | } |
9362 | } | |
9363 | ||
aee4e0db | 9364 | |
7b210806 | 9365 | BITMAP_FREE (far_labels); |
13e58269 | 9366 | |
13e58269 UW |
9367 | |
9368 | /* Recompute insn addresses. */ | |
9369 | ||
9370 | init_insn_lengths (); | |
9371 | shorten_branches (get_insns ()); | |
9db1d521 | 9372 | |
aee4e0db UW |
9373 | return pool_list; |
9374 | } | |
9db1d521 | 9375 | |
aee4e0db | 9376 | /* POOL_LIST is a chunk list as prepared by s390_chunkify_start. |
c7453384 | 9377 | After we have decided to use this list, finish implementing |
585539a1 | 9378 | all changes to the current function as required. */ |
c7453384 | 9379 | |
aee4e0db | 9380 | static void |
585539a1 | 9381 | s390_chunkify_finish (struct constant_pool *pool_list) |
aee4e0db | 9382 | { |
aee4e0db | 9383 | struct constant_pool *curr_pool = NULL; |
775c43d3 | 9384 | rtx_insn *insn; |
c7453384 EC |
9385 | |
9386 | ||
aee4e0db UW |
9387 | /* Replace all literal pool references. */ |
9388 | ||
c7453384 | 9389 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
aee4e0db | 9390 | { |
fd7643fb | 9391 | if (INSN_P (insn)) |
585539a1 | 9392 | replace_ltrel_base (&PATTERN (insn)); |
fd7643fb | 9393 | |
aee4e0db UW |
9394 | curr_pool = s390_find_pool (pool_list, insn); |
9395 | if (!curr_pool) | |
9396 | continue; | |
9397 | ||
b64925dc | 9398 | if (NONJUMP_INSN_P (insn) || CALL_P (insn)) |
aee4e0db UW |
9399 | { |
9400 | rtx addr, pool_ref = NULL_RTX; | |
9401 | find_constant_pool_ref (PATTERN (insn), &pool_ref); | |
9402 | if (pool_ref) | |
9403 | { | |
9bb86f41 UW |
9404 | if (s390_execute_label (insn)) |
9405 | addr = s390_find_execute (curr_pool, insn); | |
9406 | else | |
9407 | addr = s390_find_constant (curr_pool, | |
9408 | get_pool_constant (pool_ref), | |
9409 | get_pool_mode (pool_ref)); | |
9410 | ||
aee4e0db UW |
9411 | replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr); |
9412 | INSN_CODE (insn) = -1; | |
9413 | } | |
aee4e0db UW |
9414 | } |
9415 | } | |
9416 | ||
9417 | /* Dump out all literal pools. */ | |
c7453384 | 9418 | |
aee4e0db | 9419 | for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next) |
5af2f3d3 | 9420 | s390_dump_pool (curr_pool, 0); |
c7453384 | 9421 | |
aee4e0db UW |
9422 | /* Free pool list. */ |
9423 | ||
9424 | while (pool_list) | |
9425 | { | |
9426 | struct constant_pool *next = pool_list->next; | |
9427 | s390_free_pool (pool_list); | |
9428 | pool_list = next; | |
9429 | } | |
9430 | } | |
9431 | ||
9432 | /* POOL_LIST is a chunk list as prepared by s390_chunkify_start. | |
9433 | We have decided we cannot use this list, so revert all changes | |
9434 | to the current function that were done by s390_chunkify_start. */ | |
c7453384 | 9435 | |
aee4e0db | 9436 | static void |
9c808aad | 9437 | s390_chunkify_cancel (struct constant_pool *pool_list) |
aee4e0db UW |
9438 | { |
9439 | struct constant_pool *curr_pool = NULL; | |
775c43d3 | 9440 | rtx_insn *insn; |
aee4e0db UW |
9441 | |
9442 | /* Remove all pool placeholder insns. */ | |
9443 | ||
9444 | for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next) | |
9445 | { | |
9446 | /* Did we insert an extra barrier? Remove it. */ | |
775c43d3 DM |
9447 | rtx_insn *barrier = PREV_INSN (curr_pool->pool_insn); |
9448 | rtx_insn *jump = barrier? PREV_INSN (barrier) : NULL; | |
9449 | rtx_insn *label = NEXT_INSN (curr_pool->pool_insn); | |
aee4e0db | 9450 | |
b64925dc SB |
9451 | if (jump && JUMP_P (jump) |
9452 | && barrier && BARRIER_P (barrier) | |
9453 | && label && LABEL_P (label) | |
aee4e0db UW |
9454 | && GET_CODE (PATTERN (jump)) == SET |
9455 | && SET_DEST (PATTERN (jump)) == pc_rtx | |
9456 | && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF | |
9457 | && XEXP (SET_SRC (PATTERN (jump)), 0) == label) | |
9458 | { | |
9459 | remove_insn (jump); | |
9460 | remove_insn (barrier); | |
9461 | remove_insn (label); | |
b2ccb744 | 9462 | } |
9db1d521 | 9463 | |
aee4e0db UW |
9464 | remove_insn (curr_pool->pool_insn); |
9465 | } | |
9466 | ||
fd7643fb | 9467 | /* Remove all base register reload insns. */ |
aee4e0db UW |
9468 | |
9469 | for (insn = get_insns (); insn; ) | |
9470 | { | |
775c43d3 | 9471 | rtx_insn *next_insn = NEXT_INSN (insn); |
aee4e0db | 9472 | |
b64925dc | 9473 | if (NONJUMP_INSN_P (insn) |
aee4e0db UW |
9474 | && GET_CODE (PATTERN (insn)) == SET |
9475 | && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC | |
fd7643fb | 9476 | && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE) |
aee4e0db | 9477 | remove_insn (insn); |
9db1d521 | 9478 | |
aee4e0db UW |
9479 | insn = next_insn; |
9480 | } | |
9481 | ||
9482 | /* Free pool list. */ | |
9db1d521 | 9483 | |
b2ccb744 | 9484 | while (pool_list) |
9db1d521 | 9485 | { |
b2ccb744 UW |
9486 | struct constant_pool *next = pool_list->next; |
9487 | s390_free_pool (pool_list); | |
9488 | pool_list = next; | |
9db1d521 | 9489 | } |
9db1d521 HP |
9490 | } |
9491 | ||
faeb9bb6 | 9492 | /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */ |
416cf582 UW |
9493 | |
9494 | void | |
ef4bddc2 | 9495 | s390_output_pool_entry (rtx exp, machine_mode mode, unsigned int align) |
416cf582 | 9496 | { |
416cf582 UW |
9497 | switch (GET_MODE_CLASS (mode)) |
9498 | { | |
9499 | case MODE_FLOAT: | |
4dc19cc0 | 9500 | case MODE_DECIMAL_FLOAT: |
8d933e31 | 9501 | gcc_assert (GET_CODE (exp) == CONST_DOUBLE); |
416cf582 | 9502 | |
fc0461ae RS |
9503 | assemble_real (*CONST_DOUBLE_REAL_VALUE (exp), |
9504 | as_a <scalar_float_mode> (mode), align); | |
416cf582 UW |
9505 | break; |
9506 | ||
9507 | case MODE_INT: | |
faeb9bb6 | 9508 | assemble_integer (exp, GET_MODE_SIZE (mode), align, 1); |
a7fe25b8 | 9509 | mark_symbol_refs_as_used (exp); |
416cf582 UW |
9510 | break; |
9511 | ||
085261c8 AK |
9512 | case MODE_VECTOR_INT: |
9513 | case MODE_VECTOR_FLOAT: | |
9514 | { | |
9515 | int i; | |
9516 | machine_mode inner_mode; | |
9517 | gcc_assert (GET_CODE (exp) == CONST_VECTOR); | |
9518 | ||
9519 | inner_mode = GET_MODE_INNER (GET_MODE (exp)); | |
9520 | for (i = 0; i < XVECLEN (exp, 0); i++) | |
9521 | s390_output_pool_entry (XVECEXP (exp, 0, i), | |
9522 | inner_mode, | |
9523 | i == 0 | |
9524 | ? align | |
9525 | : GET_MODE_BITSIZE (inner_mode)); | |
9526 | } | |
9527 | break; | |
9528 | ||
416cf582 | 9529 | default: |
8d933e31 | 9530 | gcc_unreachable (); |
416cf582 UW |
9531 | } |
9532 | } | |
9533 | ||
9534 | ||
ab96de7e AS |
9535 | /* Return an RTL expression representing the value of the return address |
9536 | for the frame COUNT steps up from the current frame. FRAME is the | |
9537 | frame pointer of that frame. */ | |
b2ccb744 | 9538 | |
ab96de7e AS |
9539 | rtx |
9540 | s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED) | |
b2ccb744 | 9541 | { |
ab96de7e AS |
9542 | int offset; |
9543 | rtx addr; | |
aee4e0db | 9544 | |
ab96de7e | 9545 | /* Without backchain, we fail for all but the current frame. */ |
c3cc6b78 | 9546 | |
ab96de7e AS |
9547 | if (!TARGET_BACKCHAIN && count > 0) |
9548 | return NULL_RTX; | |
c3cc6b78 | 9549 | |
ab96de7e AS |
9550 | /* For the current frame, we need to make sure the initial |
9551 | value of RETURN_REGNUM is actually saved. */ | |
c3cc6b78 | 9552 | |
ab96de7e | 9553 | if (count == 0) |
c3cc6b78 | 9554 | { |
7bcebb25 AK |
9555 | /* On non-z architectures branch splitting could overwrite r14. */ |
9556 | if (TARGET_CPU_ZARCH) | |
9557 | return get_hard_reg_initial_val (Pmode, RETURN_REGNUM); | |
9558 | else | |
9559 | { | |
9560 | cfun_frame_layout.save_return_addr_p = true; | |
9561 | return gen_rtx_MEM (Pmode, return_address_pointer_rtx); | |
9562 | } | |
ab96de7e | 9563 | } |
c3cc6b78 | 9564 | |
ab96de7e | 9565 | if (TARGET_PACKED_STACK) |
9602b6a1 | 9566 | offset = -2 * UNITS_PER_LONG; |
ab96de7e | 9567 | else |
9602b6a1 | 9568 | offset = RETURN_REGNUM * UNITS_PER_LONG; |
c3cc6b78 | 9569 | |
0a81f074 | 9570 | addr = plus_constant (Pmode, frame, offset); |
ab96de7e AS |
9571 | addr = memory_address (Pmode, addr); |
9572 | return gen_rtx_MEM (Pmode, addr); | |
9573 | } | |
c3cc6b78 | 9574 | |
ab96de7e AS |
9575 | /* Return an RTL expression representing the back chain stored in |
9576 | the current stack frame. */ | |
545d16ff | 9577 | |
ab96de7e AS |
9578 | rtx |
9579 | s390_back_chain_rtx (void) | |
9580 | { | |
9581 | rtx chain; | |
545d16ff | 9582 | |
ab96de7e | 9583 | gcc_assert (TARGET_BACKCHAIN); |
545d16ff | 9584 | |
ab96de7e | 9585 | if (TARGET_PACKED_STACK) |
0a81f074 | 9586 | chain = plus_constant (Pmode, stack_pointer_rtx, |
9602b6a1 | 9587 | STACK_POINTER_OFFSET - UNITS_PER_LONG); |
ab96de7e AS |
9588 | else |
9589 | chain = stack_pointer_rtx; | |
545d16ff | 9590 | |
ab96de7e AS |
9591 | chain = gen_rtx_MEM (Pmode, chain); |
9592 | return chain; | |
9593 | } | |
c3cc6b78 | 9594 | |
ab96de7e AS |
9595 | /* Find first call clobbered register unused in a function. |
9596 | This could be used as base register in a leaf function | |
9597 | or for holding the return address before epilogue. */ | |
c3cc6b78 | 9598 | |
ab96de7e AS |
9599 | static int |
9600 | find_unused_clobbered_reg (void) | |
9601 | { | |
9602 | int i; | |
9603 | for (i = 0; i < 6; i++) | |
6fb5fa3c | 9604 | if (!df_regs_ever_live_p (i)) |
ab96de7e AS |
9605 | return i; |
9606 | return 0; | |
9607 | } | |
c3cc6b78 | 9608 | |
7bcebb25 | 9609 | |
f4aa3848 | 9610 | /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all |
7bcebb25 AK |
9611 | clobbered hard regs in SETREG. */ |
9612 | ||
9613 | static void | |
7bc980e1 | 9614 | s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data) |
7bcebb25 | 9615 | { |
6455a49e | 9616 | char *regs_ever_clobbered = (char *)data; |
7bcebb25 | 9617 | unsigned int i, regno; |
ef4bddc2 | 9618 | machine_mode mode = GET_MODE (setreg); |
7bcebb25 AK |
9619 | |
9620 | if (GET_CODE (setreg) == SUBREG) | |
9621 | { | |
9622 | rtx inner = SUBREG_REG (setreg); | |
5a3fe9b6 | 9623 | if (!GENERAL_REG_P (inner) && !FP_REG_P (inner)) |
7bcebb25 AK |
9624 | return; |
9625 | regno = subreg_regno (setreg); | |
9626 | } | |
5a3fe9b6 | 9627 | else if (GENERAL_REG_P (setreg) || FP_REG_P (setreg)) |
7bcebb25 AK |
9628 | regno = REGNO (setreg); |
9629 | else | |
9630 | return; | |
9631 | ||
9632 | for (i = regno; | |
4edd6298 | 9633 | i < end_hard_regno (mode, regno); |
7bcebb25 AK |
9634 | i++) |
9635 | regs_ever_clobbered[i] = 1; | |
9636 | } | |
9637 | ||
9638 | /* Walks through all basic blocks of the current function looking | |
9639 | for clobbered hard regs using s390_reg_clobbered_rtx. The fields | |
9640 | of the passed integer array REGS_EVER_CLOBBERED are set to one for | |
9641 | each of those regs. */ | |
9642 | ||
9643 | static void | |
6455a49e | 9644 | s390_regs_ever_clobbered (char regs_ever_clobbered[]) |
7bcebb25 AK |
9645 | { |
9646 | basic_block cur_bb; | |
775c43d3 | 9647 | rtx_insn *cur_insn; |
7bcebb25 AK |
9648 | unsigned int i; |
9649 | ||
6455a49e | 9650 | memset (regs_ever_clobbered, 0, 32); |
7bcebb25 AK |
9651 | |
9652 | /* For non-leaf functions we have to consider all call clobbered regs to be | |
9653 | clobbered. */ | |
416ff32e | 9654 | if (!crtl->is_leaf) |
7bcebb25 | 9655 | { |
5a3fe9b6 | 9656 | for (i = 0; i < 32; i++) |
7bcebb25 AK |
9657 | regs_ever_clobbered[i] = call_really_used_regs[i]; |
9658 | } | |
9659 | ||
9660 | /* Make the "magic" eh_return registers live if necessary. For regs_ever_live | |
9661 | this work is done by liveness analysis (mark_regs_live_at_end). | |
9662 | Special care is needed for functions containing landing pads. Landing pads | |
9663 | may use the eh registers, but the code which sets these registers is not | |
9664 | contained in that function. Hence s390_regs_ever_clobbered is not able to | |
9665 | deal with this automatically. */ | |
e3b5732b | 9666 | if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p) |
7bcebb25 | 9667 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++) |
f4aa3848 AK |
9668 | if (crtl->calls_eh_return |
9669 | || (cfun->machine->has_landing_pad_p | |
6fb5fa3c | 9670 | && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i)))) |
297a777d | 9671 | regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1; |
7bcebb25 AK |
9672 | |
9673 | /* For nonlocal gotos all call-saved registers have to be saved. | |
9674 | This flag is also set for the unwinding code in libgcc. | |
9675 | See expand_builtin_unwind_init. For regs_ever_live this is done by | |
9676 | reload. */ | |
6455a49e | 9677 | if (crtl->saves_all_registers) |
5a3fe9b6 | 9678 | for (i = 0; i < 32; i++) |
7bcebb25 AK |
9679 | if (!call_really_used_regs[i]) |
9680 | regs_ever_clobbered[i] = 1; | |
9681 | ||
11cd3bed | 9682 | FOR_EACH_BB_FN (cur_bb, cfun) |
7bcebb25 AK |
9683 | { |
9684 | FOR_BB_INSNS (cur_bb, cur_insn) | |
9685 | { | |
6455a49e AK |
9686 | rtx pat; |
9687 | ||
9688 | if (!INSN_P (cur_insn)) | |
9689 | continue; | |
9690 | ||
9691 | pat = PATTERN (cur_insn); | |
9692 | ||
9693 | /* Ignore GPR restore insns. */ | |
9694 | if (epilogue_completed && RTX_FRAME_RELATED_P (cur_insn)) | |
9695 | { | |
9696 | if (GET_CODE (pat) == SET | |
9697 | && GENERAL_REG_P (SET_DEST (pat))) | |
9698 | { | |
9699 | /* lgdr */ | |
9700 | if (GET_MODE (SET_SRC (pat)) == DImode | |
9701 | && FP_REG_P (SET_SRC (pat))) | |
9702 | continue; | |
9703 | ||
9704 | /* l / lg */ | |
9705 | if (GET_CODE (SET_SRC (pat)) == MEM) | |
9706 | continue; | |
9707 | } | |
9708 | ||
9709 | /* lm / lmg */ | |
9710 | if (GET_CODE (pat) == PARALLEL | |
9711 | && load_multiple_operation (pat, VOIDmode)) | |
9712 | continue; | |
9713 | } | |
9714 | ||
9715 | note_stores (pat, | |
9716 | s390_reg_clobbered_rtx, | |
9717 | regs_ever_clobbered); | |
7bcebb25 AK |
9718 | } |
9719 | } | |
9720 | } | |
9721 | ||
f4aa3848 AK |
9722 | /* Determine the frame area which actually has to be accessed |
9723 | in the function epilogue. The values are stored at the | |
ab96de7e | 9724 | given pointers AREA_BOTTOM (address of the lowest used stack |
f4aa3848 | 9725 | address) and AREA_TOP (address of the first item which does |
ab96de7e | 9726 | not belong to the stack frame). */ |
545d16ff | 9727 | |
ab96de7e AS |
9728 | static void |
9729 | s390_frame_area (int *area_bottom, int *area_top) | |
9730 | { | |
9731 | int b, t; | |
545d16ff | 9732 | |
ab96de7e AS |
9733 | b = INT_MAX; |
9734 | t = INT_MIN; | |
adf39f8f AK |
9735 | |
9736 | if (cfun_frame_layout.first_restore_gpr != -1) | |
9737 | { | |
9738 | b = (cfun_frame_layout.gprs_offset | |
9602b6a1 | 9739 | + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG); |
adf39f8f | 9740 | t = b + (cfun_frame_layout.last_restore_gpr |
9602b6a1 | 9741 | - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG; |
adf39f8f AK |
9742 | } |
9743 | ||
9744 | if (TARGET_64BIT && cfun_save_high_fprs_p) | |
9745 | { | |
9746 | b = MIN (b, cfun_frame_layout.f8_offset); | |
9747 | t = MAX (t, (cfun_frame_layout.f8_offset | |
9748 | + cfun_frame_layout.high_fprs * 8)); | |
9749 | } | |
9750 | ||
9751 | if (!TARGET_64BIT) | |
b89b22fc | 9752 | { |
2cf4c39e | 9753 | if (cfun_fpr_save_p (FPR4_REGNUM)) |
adf39f8f | 9754 | { |
b89b22fc AK |
9755 | b = MIN (b, cfun_frame_layout.f4_offset); |
9756 | t = MAX (t, cfun_frame_layout.f4_offset + 8); | |
adf39f8f | 9757 | } |
2cf4c39e | 9758 | if (cfun_fpr_save_p (FPR6_REGNUM)) |
b89b22fc AK |
9759 | { |
9760 | b = MIN (b, cfun_frame_layout.f4_offset + 8); | |
9761 | t = MAX (t, cfun_frame_layout.f4_offset + 16); | |
9762 | } | |
9763 | } | |
adf39f8f AK |
9764 | *area_bottom = b; |
9765 | *area_top = t; | |
9766 | } | |
6455a49e AK |
9767 | /* Update gpr_save_slots in the frame layout trying to make use of |
9768 | FPRs as GPR save slots. | |
9769 | This is a helper routine of s390_register_info. */ | |
4023fb28 UW |
9770 | |
9771 | static void | |
6455a49e | 9772 | s390_register_info_gprtofpr () |
4023fb28 | 9773 | { |
6455a49e | 9774 | int save_reg_slot = FPR0_REGNUM; |
4023fb28 | 9775 | int i, j; |
4023fb28 | 9776 | |
6455a49e AK |
9777 | if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf) |
9778 | return; | |
7bcebb25 | 9779 | |
d0ee17a5 DV |
9780 | /* builtin_eh_return needs to be able to modify the return address |
9781 | on the stack. It could also adjust the FPR save slot instead but | |
9782 | is it worth the trouble?! */ | |
9783 | if (crtl->calls_eh_return) | |
9784 | return; | |
9785 | ||
6455a49e | 9786 | for (i = 15; i >= 6; i--) |
5a3fe9b6 | 9787 | { |
82379bdf | 9788 | if (cfun_gpr_save_slot (i) == SAVE_SLOT_NONE) |
6455a49e | 9789 | continue; |
36c0bd4f | 9790 | |
6455a49e AK |
9791 | /* Advance to the next FP register which can be used as a |
9792 | GPR save slot. */ | |
9793 | while ((!call_really_used_regs[save_reg_slot] | |
9794 | || df_regs_ever_live_p (save_reg_slot) | |
9795 | || cfun_fpr_save_p (save_reg_slot)) | |
9796 | && FP_REGNO_P (save_reg_slot)) | |
9797 | save_reg_slot++; | |
9798 | if (!FP_REGNO_P (save_reg_slot)) | |
9799 | { | |
9800 | /* We only want to use ldgr/lgdr if we can get rid of | |
9801 | stm/lm entirely. So undo the gpr slot allocation in | |
9802 | case we ran out of FPR save slots. */ | |
9803 | for (j = 6; j <= 15; j++) | |
9804 | if (FP_REGNO_P (cfun_gpr_save_slot (j))) | |
82379bdf | 9805 | cfun_gpr_save_slot (j) = SAVE_SLOT_STACK; |
6455a49e | 9806 | break; |
36c0bd4f | 9807 | } |
6455a49e | 9808 | cfun_gpr_save_slot (i) = save_reg_slot++; |
5a3fe9b6 | 9809 | } |
6455a49e | 9810 | } |
5a3fe9b6 | 9811 | |
6455a49e AK |
9812 | /* Set the bits in fpr_bitmap for FPRs which need to be saved due to |
9813 | stdarg. | |
9814 | This is a helper routine for s390_register_info. */ | |
7bcebb25 | 9815 | |
6455a49e AK |
9816 | static void |
9817 | s390_register_info_stdarg_fpr () | |
9818 | { | |
9819 | int i; | |
9820 | int min_fpr; | |
9821 | int max_fpr; | |
9822 | ||
9823 | /* Save the FP argument regs for stdarg. f0, f2 for 31 bit and | |
9824 | f0-f4 for 64 bit. */ | |
9825 | if (!cfun->stdarg | |
9826 | || !TARGET_HARD_FLOAT | |
9827 | || !cfun->va_list_fpr_size | |
9828 | || crtl->args.info.fprs >= FP_ARG_NUM_REG) | |
9829 | return; | |
9830 | ||
9831 | min_fpr = crtl->args.info.fprs; | |
82379bdf AK |
9832 | max_fpr = min_fpr + cfun->va_list_fpr_size - 1; |
9833 | if (max_fpr >= FP_ARG_NUM_REG) | |
9834 | max_fpr = FP_ARG_NUM_REG - 1; | |
6455a49e | 9835 | |
82379bdf AK |
9836 | /* FPR argument regs start at f0. */ |
9837 | min_fpr += FPR0_REGNUM; | |
9838 | max_fpr += FPR0_REGNUM; | |
9839 | ||
9840 | for (i = min_fpr; i <= max_fpr; i++) | |
9841 | cfun_set_fpr_save (i); | |
6455a49e AK |
9842 | } |
9843 | ||
9844 | /* Reserve the GPR save slots for GPRs which need to be saved due to | |
9845 | stdarg. | |
9846 | This is a helper routine for s390_register_info. */ | |
9847 | ||
9848 | static void | |
9849 | s390_register_info_stdarg_gpr () | |
9850 | { | |
9851 | int i; | |
9852 | int min_gpr; | |
9853 | int max_gpr; | |
9854 | ||
9855 | if (!cfun->stdarg | |
9856 | || !cfun->va_list_gpr_size | |
9857 | || crtl->args.info.gprs >= GP_ARG_NUM_REG) | |
9858 | return; | |
9859 | ||
9860 | min_gpr = crtl->args.info.gprs; | |
82379bdf AK |
9861 | max_gpr = min_gpr + cfun->va_list_gpr_size - 1; |
9862 | if (max_gpr >= GP_ARG_NUM_REG) | |
9863 | max_gpr = GP_ARG_NUM_REG - 1; | |
9864 | ||
9865 | /* GPR argument regs start at r2. */ | |
9866 | min_gpr += GPR2_REGNUM; | |
9867 | max_gpr += GPR2_REGNUM; | |
9868 | ||
9869 | /* If r6 was supposed to be saved into an FPR and now needs to go to | |
9870 | the stack for vararg we have to adjust the restore range to make | |
9871 | sure that the restore is done from stack as well. */ | |
9872 | if (FP_REGNO_P (cfun_gpr_save_slot (GPR6_REGNUM)) | |
9873 | && min_gpr <= GPR6_REGNUM | |
9874 | && max_gpr >= GPR6_REGNUM) | |
9875 | { | |
9876 | if (cfun_frame_layout.first_restore_gpr == -1 | |
9877 | || cfun_frame_layout.first_restore_gpr > GPR6_REGNUM) | |
9878 | cfun_frame_layout.first_restore_gpr = GPR6_REGNUM; | |
9879 | if (cfun_frame_layout.last_restore_gpr == -1 | |
9880 | || cfun_frame_layout.last_restore_gpr < GPR6_REGNUM) | |
9881 | cfun_frame_layout.last_restore_gpr = GPR6_REGNUM; | |
9882 | } | |
9883 | ||
9884 | if (cfun_frame_layout.first_save_gpr == -1 | |
9885 | || cfun_frame_layout.first_save_gpr > min_gpr) | |
9886 | cfun_frame_layout.first_save_gpr = min_gpr; | |
9887 | ||
9888 | if (cfun_frame_layout.last_save_gpr == -1 | |
9889 | || cfun_frame_layout.last_save_gpr < max_gpr) | |
9890 | cfun_frame_layout.last_save_gpr = max_gpr; | |
9891 | ||
9892 | for (i = min_gpr; i <= max_gpr; i++) | |
9893 | cfun_gpr_save_slot (i) = SAVE_SLOT_STACK; | |
9894 | } | |
9895 | ||
9896 | /* Calculate the save and restore ranges for stm(g) and lm(g) in the | |
9897 | prologue and epilogue. */ | |
6455a49e | 9898 | |
82379bdf AK |
9899 | static void |
9900 | s390_register_info_set_ranges () | |
9901 | { | |
9902 | int i, j; | |
9903 | ||
9904 | /* Find the first and the last save slot supposed to use the stack | |
9905 | to set the restore range. | |
9906 | Vararg regs might be marked as save to stack but only the | |
9907 | call-saved regs really need restoring (i.e. r6). This code | |
9908 | assumes that the vararg regs have not yet been recorded in | |
9909 | cfun_gpr_save_slot. */ | |
9910 | for (i = 0; i < 16 && cfun_gpr_save_slot (i) != SAVE_SLOT_STACK; i++); | |
9911 | for (j = 15; j > i && cfun_gpr_save_slot (j) != SAVE_SLOT_STACK; j--); | |
9912 | cfun_frame_layout.first_restore_gpr = (i == 16) ? -1 : i; | |
9913 | cfun_frame_layout.last_restore_gpr = (i == 16) ? -1 : j; | |
82379bdf AK |
9914 | cfun_frame_layout.first_save_gpr = (i == 16) ? -1 : i; |
9915 | cfun_frame_layout.last_save_gpr = (i == 16) ? -1 : j; | |
6455a49e AK |
9916 | } |
9917 | ||
9918 | /* The GPR and FPR save slots in cfun->machine->frame_layout are set | |
9919 | for registers which need to be saved in function prologue. | |
9920 | This function can be used until the insns emitted for save/restore | |
9921 | of the regs are visible in the RTL stream. */ | |
9922 | ||
9923 | static void | |
9924 | s390_register_info () | |
9925 | { | |
82379bdf | 9926 | int i; |
6455a49e AK |
9927 | char clobbered_regs[32]; |
9928 | ||
9929 | gcc_assert (!epilogue_completed); | |
9930 | ||
9931 | if (reload_completed) | |
9932 | /* After reload we rely on our own routine to determine which | |
9933 | registers need saving. */ | |
9934 | s390_regs_ever_clobbered (clobbered_regs); | |
9935 | else | |
9936 | /* During reload we use regs_ever_live as a base since reload | |
9937 | does changes in there which we otherwise would not be aware | |
9938 | of. */ | |
9939 | for (i = 0; i < 32; i++) | |
9940 | clobbered_regs[i] = df_regs_ever_live_p (i); | |
9941 | ||
9942 | for (i = 0; i < 32; i++) | |
9943 | clobbered_regs[i] = clobbered_regs[i] && !global_regs[i]; | |
9944 | ||
9945 | /* Mark the call-saved FPRs which need to be saved. | |
9946 | This needs to be done before checking the special GPRs since the | |
9947 | stack pointer usage depends on whether high FPRs have to be saved | |
9948 | or not. */ | |
9949 | cfun_frame_layout.fpr_bitmap = 0; | |
9950 | cfun_frame_layout.high_fprs = 0; | |
9951 | for (i = FPR0_REGNUM; i <= FPR15_REGNUM; i++) | |
9952 | if (clobbered_regs[i] && !call_really_used_regs[i]) | |
9953 | { | |
9954 | cfun_set_fpr_save (i); | |
9955 | if (i >= FPR8_REGNUM) | |
9956 | cfun_frame_layout.high_fprs++; | |
9957 | } | |
c3cc6b78 | 9958 | |
4cb4721f MK |
9959 | /* Register 12 is used for GOT address, but also as temp in prologue |
9960 | for split-stack stdarg functions (unless r14 is available). */ | |
9961 | clobbered_regs[12] | |
9962 | |= ((flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) | |
9963 | || (flag_split_stack && cfun->stdarg | |
9964 | && (crtl->is_leaf || TARGET_TPF_PROFILING | |
9965 | || has_hard_reg_initial_val (Pmode, RETURN_REGNUM)))); | |
91086990 | 9966 | |
f4aa3848 | 9967 | clobbered_regs[BASE_REGNUM] |
e2df5c1d | 9968 | |= (cfun->machine->base_reg |
6455a49e | 9969 | && REGNO (cfun->machine->base_reg) == BASE_REGNUM); |
91086990 | 9970 | |
6455a49e AK |
9971 | clobbered_regs[HARD_FRAME_POINTER_REGNUM] |
9972 | |= !!frame_pointer_needed; | |
9973 | ||
9974 | /* On pre z900 machines this might take until machine dependent | |
9975 | reorg to decide. | |
9976 | save_return_addr_p will only be set on non-zarch machines so | |
9977 | there is no risk that r14 goes into an FPR instead of a stack | |
9978 | slot. */ | |
7bcebb25 | 9979 | clobbered_regs[RETURN_REGNUM] |
416ff32e | 9980 | |= (!crtl->is_leaf |
dc4477f5 | 9981 | || TARGET_TPF_PROFILING |
e2df5c1d UW |
9982 | || cfun->machine->split_branches_pending_p |
9983 | || cfun_frame_layout.save_return_addr_p | |
6455a49e | 9984 | || crtl->calls_eh_return); |
91086990 | 9985 | |
7bcebb25 | 9986 | clobbered_regs[STACK_POINTER_REGNUM] |
416ff32e | 9987 | |= (!crtl->is_leaf |
e2df5c1d UW |
9988 | || TARGET_TPF_PROFILING |
9989 | || cfun_save_high_fprs_p | |
9990 | || get_frame_size () > 0 | |
36c0bd4f | 9991 | || (reload_completed && cfun_frame_layout.frame_size > 0) |
6455a49e AK |
9992 | || cfun->calls_alloca); |
9993 | ||
82379bdf | 9994 | memset (cfun_frame_layout.gpr_save_slots, SAVE_SLOT_NONE, 16); |
7bcebb25 | 9995 | |
b767fc11 | 9996 | for (i = 6; i < 16; i++) |
6455a49e | 9997 | if (clobbered_regs[i]) |
82379bdf | 9998 | cfun_gpr_save_slot (i) = SAVE_SLOT_STACK; |
c3cc6b78 | 9999 | |
6455a49e AK |
10000 | s390_register_info_stdarg_fpr (); |
10001 | s390_register_info_gprtofpr (); | |
82379bdf | 10002 | s390_register_info_set_ranges (); |
6455a49e | 10003 | /* stdarg functions might need to save GPRs 2 to 6. This might |
82379bdf AK |
10004 | override the GPR->FPR save decision made by |
10005 | s390_register_info_gprtofpr for r6 since vararg regs must go to | |
10006 | the stack. */ | |
6455a49e | 10007 | s390_register_info_stdarg_gpr (); |
6455a49e | 10008 | } |
c3cc6b78 | 10009 | |
6455a49e AK |
10010 | /* This function is called by s390_optimize_prologue in order to get |
10011 | rid of unnecessary GPR save/restore instructions. The register info | |
10012 | for the GPRs is re-computed and the ranges are re-calculated. */ | |
29a79fcf | 10013 | |
6455a49e AK |
10014 | static void |
10015 | s390_optimize_register_info () | |
10016 | { | |
10017 | char clobbered_regs[32]; | |
82379bdf | 10018 | int i; |
29a79fcf | 10019 | |
6455a49e AK |
10020 | gcc_assert (epilogue_completed); |
10021 | gcc_assert (!cfun->machine->split_branches_pending_p); | |
b767fc11 | 10022 | |
6455a49e | 10023 | s390_regs_ever_clobbered (clobbered_regs); |
29a79fcf | 10024 | |
6455a49e AK |
10025 | for (i = 0; i < 32; i++) |
10026 | clobbered_regs[i] = clobbered_regs[i] && !global_regs[i]; | |
29a79fcf | 10027 | |
6455a49e AK |
10028 | /* There is still special treatment needed for cases invisible to |
10029 | s390_regs_ever_clobbered. */ | |
10030 | clobbered_regs[RETURN_REGNUM] | |
10031 | |= (TARGET_TPF_PROFILING | |
10032 | /* When expanding builtin_return_addr in ESA mode we do not | |
10033 | know whether r14 will later be needed as scratch reg when | |
10034 | doing branch splitting. So the builtin always accesses the | |
10035 | r14 save slot and we need to stick to the save/restore | |
10036 | decision for r14 even if it turns out that it didn't get | |
10037 | clobbered. */ | |
10038 | || cfun_frame_layout.save_return_addr_p | |
10039 | || crtl->calls_eh_return); | |
10040 | ||
82379bdf | 10041 | memset (cfun_frame_layout.gpr_save_slots, SAVE_SLOT_NONE, 6); |
6455a49e AK |
10042 | |
10043 | for (i = 6; i < 16; i++) | |
10044 | if (!clobbered_regs[i]) | |
82379bdf | 10045 | cfun_gpr_save_slot (i) = SAVE_SLOT_NONE; |
6455a49e | 10046 | |
82379bdf | 10047 | s390_register_info_set_ranges (); |
6455a49e | 10048 | s390_register_info_stdarg_gpr (); |
adf39f8f AK |
10049 | } |
10050 | ||
91086990 | 10051 | /* Fill cfun->machine with info about frame of current function. */ |
adf39f8f AK |
10052 | |
10053 | static void | |
91086990 | 10054 | s390_frame_info (void) |
adf39f8f | 10055 | { |
74129172 | 10056 | HOST_WIDE_INT lowest_offset; |
adf39f8f | 10057 | |
6455a49e AK |
10058 | cfun_frame_layout.first_save_gpr_slot = cfun_frame_layout.first_save_gpr; |
10059 | cfun_frame_layout.last_save_gpr_slot = cfun_frame_layout.last_save_gpr; | |
10060 | ||
10061 | /* The va_arg builtin uses a constant distance of 16 * | |
10062 | UNITS_PER_LONG (r0-r15) to reach the FPRs from the reg_save_area | |
10063 | pointer. So even if we are going to save the stack pointer in an | |
10064 | FPR we need the stack space in order to keep the offsets | |
10065 | correct. */ | |
10066 | if (cfun->stdarg && cfun_save_arg_fprs_p) | |
10067 | { | |
10068 | cfun_frame_layout.last_save_gpr_slot = STACK_POINTER_REGNUM; | |
10069 | ||
10070 | if (cfun_frame_layout.first_save_gpr_slot == -1) | |
10071 | cfun_frame_layout.first_save_gpr_slot = STACK_POINTER_REGNUM; | |
10072 | } | |
10073 | ||
adf39f8f | 10074 | cfun_frame_layout.frame_size = get_frame_size (); |
adf39f8f | 10075 | if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000) |
40fecdd6 JM |
10076 | fatal_error (input_location, |
10077 | "total size of local variables exceeds architecture limit"); | |
f4aa3848 | 10078 | |
b3d31392 | 10079 | if (!TARGET_PACKED_STACK) |
adf39f8f | 10080 | { |
74129172 | 10081 | /* Fixed stack layout. */ |
adf39f8f | 10082 | cfun_frame_layout.backchain_offset = 0; |
9602b6a1 | 10083 | cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG; |
adf39f8f AK |
10084 | cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8; |
10085 | cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8; | |
fb3712f6 | 10086 | cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot |
9602b6a1 | 10087 | * UNITS_PER_LONG); |
adf39f8f | 10088 | } |
74129172 | 10089 | else if (TARGET_BACKCHAIN) |
adf39f8f | 10090 | { |
74129172 AK |
10091 | /* Kernel stack layout - packed stack, backchain, no float */ |
10092 | gcc_assert (TARGET_SOFT_FLOAT); | |
adf39f8f | 10093 | cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET |
9602b6a1 | 10094 | - UNITS_PER_LONG); |
74129172 AK |
10095 | |
10096 | /* The distance between the backchain and the return address | |
10097 | save slot must not change. So we always need a slot for the | |
10098 | stack pointer which resides in between. */ | |
10099 | cfun_frame_layout.last_save_gpr_slot = STACK_POINTER_REGNUM; | |
10100 | ||
f4aa3848 | 10101 | cfun_frame_layout.gprs_offset |
74129172 | 10102 | = cfun_frame_layout.backchain_offset - cfun_gprs_save_area_size; |
f4aa3848 | 10103 | |
74129172 AK |
10104 | /* FPRs will not be saved. Nevertheless pick sane values to |
10105 | keep area calculations valid. */ | |
10106 | cfun_frame_layout.f0_offset = | |
10107 | cfun_frame_layout.f4_offset = | |
10108 | cfun_frame_layout.f8_offset = cfun_frame_layout.gprs_offset; | |
adf39f8f | 10109 | } |
74129172 | 10110 | else |
adf39f8f | 10111 | { |
e179df83 AK |
10112 | int num_fprs; |
10113 | ||
74129172 | 10114 | /* Packed stack layout without backchain. */ |
f4aa3848 | 10115 | |
e179df83 AK |
10116 | /* With stdarg FPRs need their dedicated slots. */ |
10117 | num_fprs = (TARGET_64BIT && cfun->stdarg ? 2 | |
10118 | : (cfun_fpr_save_p (FPR4_REGNUM) + | |
10119 | cfun_fpr_save_p (FPR6_REGNUM))); | |
10120 | cfun_frame_layout.f4_offset = STACK_POINTER_OFFSET - 8 * num_fprs; | |
10121 | ||
10122 | num_fprs = (cfun->stdarg ? 2 | |
10123 | : (cfun_fpr_save_p (FPR0_REGNUM) | |
10124 | + cfun_fpr_save_p (FPR2_REGNUM))); | |
10125 | cfun_frame_layout.f0_offset = cfun_frame_layout.f4_offset - 8 * num_fprs; | |
f4aa3848 AK |
10126 | |
10127 | cfun_frame_layout.gprs_offset | |
adf39f8f | 10128 | = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size; |
74129172 AK |
10129 | |
10130 | cfun_frame_layout.f8_offset = (cfun_frame_layout.gprs_offset | |
10131 | - cfun_frame_layout.high_fprs * 8); | |
adf39f8f AK |
10132 | } |
10133 | ||
74129172 AK |
10134 | if (cfun_save_high_fprs_p) |
10135 | cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8; | |
10136 | ||
10137 | if (!crtl->is_leaf) | |
10138 | cfun_frame_layout.frame_size += crtl->outgoing_args_size; | |
10139 | ||
10140 | /* In the following cases we have to allocate a STACK_POINTER_OFFSET | |
10141 | sized area at the bottom of the stack. This is required also for | |
10142 | leaf functions. When GCC generates a local stack reference it | |
10143 | will always add STACK_POINTER_OFFSET to all these references. */ | |
416ff32e | 10144 | if (crtl->is_leaf |
adf39f8f AK |
10145 | && !TARGET_TPF_PROFILING |
10146 | && cfun_frame_layout.frame_size == 0 | |
6455a49e | 10147 | && !cfun->calls_alloca) |
adf39f8f AK |
10148 | return; |
10149 | ||
74129172 AK |
10150 | /* Calculate the number of bytes we have used in our own register |
10151 | save area. With the packed stack layout we can re-use the | |
10152 | remaining bytes for normal stack elements. */ | |
adf39f8f | 10153 | |
74129172 AK |
10154 | if (TARGET_PACKED_STACK) |
10155 | lowest_offset = MIN (MIN (cfun_frame_layout.f0_offset, | |
10156 | cfun_frame_layout.f4_offset), | |
10157 | cfun_frame_layout.gprs_offset); | |
10158 | else | |
10159 | lowest_offset = 0; | |
f4aa3848 | 10160 | |
74129172 AK |
10161 | if (TARGET_BACKCHAIN) |
10162 | lowest_offset = MIN (lowest_offset, cfun_frame_layout.backchain_offset); | |
f4aa3848 | 10163 | |
74129172 | 10164 | cfun_frame_layout.frame_size += STACK_POINTER_OFFSET - lowest_offset; |
adf39f8f | 10165 | |
74129172 AK |
10166 | /* If under 31 bit an odd number of gprs has to be saved we have to |
10167 | adjust the frame size to sustain 8 byte alignment of stack | |
10168 | frames. */ | |
10169 | cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size + | |
10170 | STACK_BOUNDARY / BITS_PER_UNIT - 1) | |
10171 | & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1)); | |
4023fb28 UW |
10172 | } |
10173 | ||
91086990 UW |
10174 | /* Generate frame layout. Fills in register and frame data for the current |
10175 | function in cfun->machine. This routine can be called multiple times; | |
10176 | it will re-do the complete frame layout every time. */ | |
4023fb28 | 10177 | |
91086990 UW |
10178 | static void |
10179 | s390_init_frame_layout (void) | |
9db1d521 | 10180 | { |
91086990 UW |
10181 | HOST_WIDE_INT frame_size; |
10182 | int base_used; | |
6455a49e | 10183 | |
9158295f AK |
10184 | /* After LRA the frame layout is supposed to be read-only and should |
10185 | not be re-computed. */ | |
10186 | if (reload_completed) | |
10187 | return; | |
b767fc11 | 10188 | |
91086990 UW |
10189 | /* On S/390 machines, we may need to perform branch splitting, which |
10190 | will require both base and return address register. We have no | |
10191 | choice but to assume we're going to need them until right at the | |
10192 | end of the machine dependent reorg phase. */ | |
10193 | if (!TARGET_CPU_ZARCH) | |
10194 | cfun->machine->split_branches_pending_p = true; | |
10195 | ||
10196 | do | |
10197 | { | |
10198 | frame_size = cfun_frame_layout.frame_size; | |
10199 | ||
10200 | /* Try to predict whether we'll need the base register. */ | |
10201 | base_used = cfun->machine->split_branches_pending_p | |
e3b5732b | 10202 | || crtl->uses_const_pool |
20f04e65 AK |
10203 | || (!DISP_IN_RANGE (frame_size) |
10204 | && !CONST_OK_FOR_K (frame_size)); | |
91086990 UW |
10205 | |
10206 | /* Decide which register to use as literal pool base. In small | |
10207 | leaf functions, try to use an unused call-clobbered register | |
10208 | as base register to avoid save/restore overhead. */ | |
10209 | if (!base_used) | |
10210 | cfun->machine->base_reg = NULL_RTX; | |
91086990 | 10211 | else |
10148d74 DV |
10212 | { |
10213 | int br = 0; | |
10214 | ||
10215 | if (crtl->is_leaf) | |
10216 | /* Prefer r5 (most likely to be free). */ | |
10217 | for (br = 5; br >= 2 && df_regs_ever_live_p (br); br--) | |
10218 | ; | |
10219 | cfun->machine->base_reg = | |
0b729f58 | 10220 | gen_rtx_REG (Pmode, (br >= 2) ? br : BASE_REGNUM); |
10148d74 | 10221 | } |
adf39f8f | 10222 | |
6455a49e | 10223 | s390_register_info (); |
91086990 UW |
10224 | s390_frame_info (); |
10225 | } | |
10226 | while (frame_size != cfun_frame_layout.frame_size); | |
9db1d521 HP |
10227 | } |
10228 | ||
5a3fe9b6 AK |
10229 | /* Remove the FPR clobbers from a tbegin insn if it can be proven that |
10230 | the TX is nonescaping. A transaction is considered escaping if | |
10231 | there is at least one path from tbegin returning CC0 to the | |
10232 | function exit block without an tend. | |
10233 | ||
10234 | The check so far has some limitations: | |
10235 | - only single tbegin/tend BBs are supported | |
10236 | - the first cond jump after tbegin must separate the CC0 path from ~CC0 | |
10237 | - when CC is copied to a GPR and the CC0 check is done with the GPR | |
10238 | this is not supported | |
10239 | */ | |
10240 | ||
10241 | static void | |
10242 | s390_optimize_nonescaping_tx (void) | |
10243 | { | |
10244 | const unsigned int CC0 = 1 << 3; | |
10245 | basic_block tbegin_bb = NULL; | |
10246 | basic_block tend_bb = NULL; | |
10247 | basic_block bb; | |
775c43d3 | 10248 | rtx_insn *insn; |
5a3fe9b6 AK |
10249 | bool result = true; |
10250 | int bb_index; | |
775c43d3 | 10251 | rtx_insn *tbegin_insn = NULL; |
5a3fe9b6 AK |
10252 | |
10253 | if (!cfun->machine->tbegin_p) | |
10254 | return; | |
10255 | ||
0cae8d31 | 10256 | for (bb_index = 0; bb_index < n_basic_blocks_for_fn (cfun); bb_index++) |
5a3fe9b6 | 10257 | { |
06e28de2 | 10258 | bb = BASIC_BLOCK_FOR_FN (cfun, bb_index); |
5a3fe9b6 | 10259 | |
2561451d AK |
10260 | if (!bb) |
10261 | continue; | |
10262 | ||
5a3fe9b6 AK |
10263 | FOR_BB_INSNS (bb, insn) |
10264 | { | |
10265 | rtx ite, cc, pat, target; | |
10266 | unsigned HOST_WIDE_INT mask; | |
10267 | ||
10268 | if (!INSN_P (insn) || INSN_CODE (insn) <= 0) | |
10269 | continue; | |
10270 | ||
10271 | pat = PATTERN (insn); | |
10272 | ||
10273 | if (GET_CODE (pat) == PARALLEL) | |
10274 | pat = XVECEXP (pat, 0, 0); | |
10275 | ||
10276 | if (GET_CODE (pat) != SET | |
10277 | || GET_CODE (SET_SRC (pat)) != UNSPEC_VOLATILE) | |
10278 | continue; | |
10279 | ||
10280 | if (XINT (SET_SRC (pat), 1) == UNSPECV_TBEGIN) | |
10281 | { | |
b32d5189 | 10282 | rtx_insn *tmp; |
5a3fe9b6 AK |
10283 | |
10284 | tbegin_insn = insn; | |
10285 | ||
10286 | /* Just return if the tbegin doesn't have clobbers. */ | |
10287 | if (GET_CODE (PATTERN (insn)) != PARALLEL) | |
10288 | return; | |
10289 | ||
10290 | if (tbegin_bb != NULL) | |
10291 | return; | |
10292 | ||
10293 | /* Find the next conditional jump. */ | |
10294 | for (tmp = NEXT_INSN (insn); | |
10295 | tmp != NULL_RTX; | |
10296 | tmp = NEXT_INSN (tmp)) | |
10297 | { | |
10298 | if (reg_set_p (gen_rtx_REG (CCmode, CC_REGNUM), tmp)) | |
10299 | return; | |
10300 | if (!JUMP_P (tmp)) | |
10301 | continue; | |
10302 | ||
10303 | ite = SET_SRC (PATTERN (tmp)); | |
10304 | if (GET_CODE (ite) != IF_THEN_ELSE) | |
10305 | continue; | |
10306 | ||
10307 | cc = XEXP (XEXP (ite, 0), 0); | |
10308 | if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)) | |
10309 | || GET_MODE (cc) != CCRAWmode | |
10310 | || GET_CODE (XEXP (XEXP (ite, 0), 1)) != CONST_INT) | |
10311 | return; | |
10312 | ||
10313 | if (bb->succs->length () != 2) | |
10314 | return; | |
10315 | ||
10316 | mask = INTVAL (XEXP (XEXP (ite, 0), 1)); | |
10317 | if (GET_CODE (XEXP (ite, 0)) == NE) | |
10318 | mask ^= 0xf; | |
10319 | ||
10320 | if (mask == CC0) | |
10321 | target = XEXP (ite, 1); | |
10322 | else if (mask == (CC0 ^ 0xf)) | |
10323 | target = XEXP (ite, 2); | |
10324 | else | |
10325 | return; | |
10326 | ||
10327 | { | |
10328 | edge_iterator ei; | |
10329 | edge e1, e2; | |
10330 | ||
10331 | ei = ei_start (bb->succs); | |
10332 | e1 = ei_safe_edge (ei); | |
10333 | ei_next (&ei); | |
10334 | e2 = ei_safe_edge (ei); | |
10335 | ||
10336 | if (e2->flags & EDGE_FALLTHRU) | |
10337 | { | |
10338 | e2 = e1; | |
10339 | e1 = ei_safe_edge (ei); | |
10340 | } | |
10341 | ||
10342 | if (!(e1->flags & EDGE_FALLTHRU)) | |
10343 | return; | |
10344 | ||
10345 | tbegin_bb = (target == pc_rtx) ? e1->dest : e2->dest; | |
10346 | } | |
10347 | if (tmp == BB_END (bb)) | |
10348 | break; | |
10349 | } | |
10350 | } | |
10351 | ||
10352 | if (XINT (SET_SRC (pat), 1) == UNSPECV_TEND) | |
10353 | { | |
10354 | if (tend_bb != NULL) | |
10355 | return; | |
10356 | tend_bb = bb; | |
10357 | } | |
10358 | } | |
10359 | } | |
10360 | ||
10361 | /* Either we successfully remove the FPR clobbers here or we are not | |
10362 | able to do anything for this TX. Both cases don't qualify for | |
10363 | another look. */ | |
10364 | cfun->machine->tbegin_p = false; | |
10365 | ||
10366 | if (tbegin_bb == NULL || tend_bb == NULL) | |
10367 | return; | |
10368 | ||
10369 | calculate_dominance_info (CDI_POST_DOMINATORS); | |
10370 | result = dominated_by_p (CDI_POST_DOMINATORS, tbegin_bb, tend_bb); | |
10371 | free_dominance_info (CDI_POST_DOMINATORS); | |
10372 | ||
10373 | if (!result) | |
10374 | return; | |
10375 | ||
2561451d AK |
10376 | PATTERN (tbegin_insn) = gen_rtx_PARALLEL (VOIDmode, |
10377 | gen_rtvec (2, | |
10378 | XVECEXP (PATTERN (tbegin_insn), 0, 0), | |
10379 | XVECEXP (PATTERN (tbegin_insn), 0, 1))); | |
5a3fe9b6 AK |
10380 | INSN_CODE (tbegin_insn) = -1; |
10381 | df_insn_rescan (tbegin_insn); | |
10382 | ||
10383 | return; | |
10384 | } | |
10385 | ||
c43f4279 RS |
10386 | /* Implement TARGET_HARD_REGNO_NREGS. Because all registers in a class |
10387 | have the same size, this is equivalent to CLASS_MAX_NREGS. */ | |
10388 | ||
10389 | static unsigned int | |
10390 | s390_hard_regno_nregs (unsigned int regno, machine_mode mode) | |
10391 | { | |
10392 | return s390_class_max_nregs (REGNO_REG_CLASS (regno), mode); | |
10393 | } | |
10394 | ||
10395 | /* Implement TARGET_HARD_REGNO_MODE_OK. | |
10396 | ||
10397 | Integer modes <= word size fit into any GPR. | |
10398 | Integer modes > word size fit into successive GPRs, starting with | |
10399 | an even-numbered register. | |
10400 | SImode and DImode fit into FPRs as well. | |
10401 | ||
10402 | Floating point modes <= word size fit into any FPR or GPR. | |
10403 | Floating point modes > word size (i.e. DFmode on 32-bit) fit | |
10404 | into any FPR, or an even-odd GPR pair. | |
10405 | TFmode fits only into an even-odd FPR pair. | |
10406 | ||
10407 | Complex floating point modes fit either into two FPRs, or into | |
10408 | successive GPRs (again starting with an even number). | |
10409 | TCmode fits only into two successive even-odd FPR pairs. | |
10410 | ||
10411 | Condition code modes fit only into the CC register. */ | |
74aa8b4b | 10412 | |
f939c3e6 | 10413 | static bool |
ef4bddc2 | 10414 | s390_hard_regno_mode_ok (unsigned int regno, machine_mode mode) |
74aa8b4b | 10415 | { |
085261c8 AK |
10416 | if (!TARGET_VX && VECTOR_NOFP_REGNO_P (regno)) |
10417 | return false; | |
10418 | ||
74aa8b4b AK |
10419 | switch (REGNO_REG_CLASS (regno)) |
10420 | { | |
085261c8 AK |
10421 | case VEC_REGS: |
10422 | return ((GET_MODE_CLASS (mode) == MODE_INT | |
10423 | && s390_class_max_nregs (VEC_REGS, mode) == 1) | |
10424 | || mode == DFmode | |
2de2b3f9 | 10425 | || (TARGET_VXE && mode == SFmode) |
085261c8 AK |
10426 | || s390_vector_mode_supported_p (mode)); |
10427 | break; | |
74aa8b4b | 10428 | case FP_REGS: |
085261c8 AK |
10429 | if (TARGET_VX |
10430 | && ((GET_MODE_CLASS (mode) == MODE_INT | |
10431 | && s390_class_max_nregs (FP_REGS, mode) == 1) | |
10432 | || mode == DFmode | |
10433 | || s390_vector_mode_supported_p (mode))) | |
10434 | return true; | |
10435 | ||
74aa8b4b AK |
10436 | if (REGNO_PAIR_OK (regno, mode)) |
10437 | { | |
10438 | if (mode == SImode || mode == DImode) | |
10439 | return true; | |
10440 | ||
10441 | if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT) | |
10442 | return true; | |
10443 | } | |
10444 | break; | |
10445 | case ADDR_REGS: | |
10446 | if (FRAME_REGNO_P (regno) && mode == Pmode) | |
10447 | return true; | |
10448 | ||
10449 | /* fallthrough */ | |
10450 | case GENERAL_REGS: | |
10451 | if (REGNO_PAIR_OK (regno, mode)) | |
10452 | { | |
9602b6a1 | 10453 | if (TARGET_ZARCH |
4dc19cc0 | 10454 | || (mode != TFmode && mode != TCmode && mode != TDmode)) |
74aa8b4b | 10455 | return true; |
f4aa3848 | 10456 | } |
74aa8b4b AK |
10457 | break; |
10458 | case CC_REGS: | |
10459 | if (GET_MODE_CLASS (mode) == MODE_CC) | |
10460 | return true; | |
10461 | break; | |
10462 | case ACCESS_REGS: | |
10463 | if (REGNO_PAIR_OK (regno, mode)) | |
10464 | { | |
10465 | if (mode == SImode || mode == Pmode) | |
10466 | return true; | |
10467 | } | |
10468 | break; | |
10469 | default: | |
10470 | return false; | |
10471 | } | |
f4aa3848 | 10472 | |
74aa8b4b AK |
10473 | return false; |
10474 | } | |
10475 | ||
99e1629f RS |
10476 | /* Implement TARGET_MODES_TIEABLE_P. */ |
10477 | ||
10478 | static bool | |
10479 | s390_modes_tieable_p (machine_mode mode1, machine_mode mode2) | |
10480 | { | |
10481 | return ((mode1 == SFmode || mode1 == DFmode) | |
10482 | == (mode2 == SFmode || mode2 == DFmode)); | |
10483 | } | |
10484 | ||
7633f08e UW |
10485 | /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */ |
10486 | ||
10487 | bool | |
10488 | s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg) | |
10489 | { | |
10490 | /* Once we've decided upon a register to use as base register, it must | |
10491 | no longer be used for any other purpose. */ | |
10492 | if (cfun->machine->base_reg) | |
10493 | if (REGNO (cfun->machine->base_reg) == old_reg | |
10494 | || REGNO (cfun->machine->base_reg) == new_reg) | |
10495 | return false; | |
10496 | ||
6455a49e AK |
10497 | /* Prevent regrename from using call-saved regs which haven't |
10498 | actually been saved. This is necessary since regrename assumes | |
10499 | the backend save/restore decisions are based on | |
10500 | df_regs_ever_live. Since we have our own routine we have to tell | |
10501 | regrename manually about it. */ | |
10502 | if (GENERAL_REGNO_P (new_reg) | |
10503 | && !call_really_used_regs[new_reg] | |
82379bdf | 10504 | && cfun_gpr_save_slot (new_reg) == SAVE_SLOT_NONE) |
6455a49e AK |
10505 | return false; |
10506 | ||
10507 | return true; | |
10508 | } | |
10509 | ||
10510 | /* Return nonzero if register REGNO can be used as a scratch register | |
10511 | in peephole2. */ | |
10512 | ||
10513 | static bool | |
10514 | s390_hard_regno_scratch_ok (unsigned int regno) | |
10515 | { | |
10516 | /* See s390_hard_regno_rename_ok. */ | |
10517 | if (GENERAL_REGNO_P (regno) | |
10518 | && !call_really_used_regs[regno] | |
82379bdf | 10519 | && cfun_gpr_save_slot (regno) == SAVE_SLOT_NONE) |
6455a49e AK |
10520 | return false; |
10521 | ||
7633f08e UW |
10522 | return true; |
10523 | } | |
10524 | ||
80ec73f4 RS |
10525 | /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. When generating |
10526 | code that runs in z/Architecture mode, but conforms to the 31-bit | |
10527 | ABI, GPRs can hold 8 bytes; the ABI guarantees only that the lower 4 | |
10528 | bytes are saved across calls, however. */ | |
10529 | ||
10530 | static bool | |
10531 | s390_hard_regno_call_part_clobbered (unsigned int regno, machine_mode mode) | |
10532 | { | |
10533 | if (!TARGET_64BIT | |
10534 | && TARGET_ZARCH | |
10535 | && GET_MODE_SIZE (mode) > 4 | |
10536 | && ((regno >= 6 && regno <= 15) || regno == 32)) | |
10537 | return true; | |
10538 | ||
10539 | if (TARGET_VX | |
10540 | && GET_MODE_SIZE (mode) > 8 | |
10541 | && (((TARGET_64BIT && regno >= 24 && regno <= 31)) | |
10542 | || (!TARGET_64BIT && (regno == 18 || regno == 19)))) | |
10543 | return true; | |
10544 | ||
10545 | return false; | |
10546 | } | |
10547 | ||
74aa8b4b | 10548 | /* Maximum number of registers to represent a value of mode MODE |
0a2aaacc | 10549 | in a register of class RCLASS. */ |
74aa8b4b | 10550 | |
c4100a35 | 10551 | int |
ef4bddc2 | 10552 | s390_class_max_nregs (enum reg_class rclass, machine_mode mode) |
74aa8b4b | 10553 | { |
085261c8 AK |
10554 | int reg_size; |
10555 | bool reg_pair_required_p = false; | |
10556 | ||
0a2aaacc | 10557 | switch (rclass) |
74aa8b4b AK |
10558 | { |
10559 | case FP_REGS: | |
085261c8 AK |
10560 | case VEC_REGS: |
10561 | reg_size = TARGET_VX ? 16 : 8; | |
10562 | ||
10563 | /* TF and TD modes would fit into a VR but we put them into a | |
10564 | register pair since we do not have 128bit FP instructions on | |
10565 | full VRs. */ | |
10566 | if (TARGET_VX | |
10567 | && SCALAR_FLOAT_MODE_P (mode) | |
10568 | && GET_MODE_SIZE (mode) >= 16) | |
10569 | reg_pair_required_p = true; | |
10570 | ||
10571 | /* Even if complex types would fit into a single FPR/VR we force | |
10572 | them into a register pair to deal with the parts more easily. | |
10573 | (FIXME: What about complex ints?) */ | |
74aa8b4b | 10574 | if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) |
085261c8 AK |
10575 | reg_pair_required_p = true; |
10576 | break; | |
74aa8b4b | 10577 | case ACCESS_REGS: |
085261c8 AK |
10578 | reg_size = 4; |
10579 | break; | |
74aa8b4b | 10580 | default: |
085261c8 | 10581 | reg_size = UNITS_PER_WORD; |
74aa8b4b AK |
10582 | break; |
10583 | } | |
085261c8 AK |
10584 | |
10585 | if (reg_pair_required_p) | |
10586 | return 2 * ((GET_MODE_SIZE (mode) / 2 + reg_size - 1) / reg_size); | |
10587 | ||
10588 | return (GET_MODE_SIZE (mode) + reg_size - 1) / reg_size; | |
10589 | } | |
10590 | ||
10591 | /* Return TRUE if changing mode from FROM to TO should not be allowed | |
10592 | for register class CLASS. */ | |
10593 | ||
10594 | int | |
10595 | s390_cannot_change_mode_class (machine_mode from_mode, | |
10596 | machine_mode to_mode, | |
10597 | enum reg_class rclass) | |
10598 | { | |
10599 | machine_mode small_mode; | |
10600 | machine_mode big_mode; | |
10601 | ||
2de2b3f9 AK |
10602 | /* V1TF and TF have different representations in vector |
10603 | registers. */ | |
10604 | if (reg_classes_intersect_p (VEC_REGS, rclass) | |
10605 | && ((from_mode == V1TFmode && to_mode == TFmode) | |
10606 | || (from_mode == TFmode && to_mode == V1TFmode))) | |
10607 | return 1; | |
10608 | ||
085261c8 AK |
10609 | if (GET_MODE_SIZE (from_mode) == GET_MODE_SIZE (to_mode)) |
10610 | return 0; | |
10611 | ||
10612 | if (GET_MODE_SIZE (from_mode) < GET_MODE_SIZE (to_mode)) | |
10613 | { | |
10614 | small_mode = from_mode; | |
10615 | big_mode = to_mode; | |
10616 | } | |
10617 | else | |
10618 | { | |
10619 | small_mode = to_mode; | |
10620 | big_mode = from_mode; | |
10621 | } | |
10622 | ||
10623 | /* Values residing in VRs are little-endian style. All modes are | |
10624 | placed left-aligned in an VR. This means that we cannot allow | |
10625 | switching between modes with differing sizes. Also if the vector | |
10626 | facility is available we still place TFmode values in VR register | |
10627 | pairs, since the only instructions we have operating on TFmodes | |
10628 | only deal with register pairs. Therefore we have to allow DFmode | |
10629 | subregs of TFmodes to enable the TFmode splitters. */ | |
10630 | if (reg_classes_intersect_p (VEC_REGS, rclass) | |
10631 | && (GET_MODE_SIZE (small_mode) < 8 | |
10632 | || s390_class_max_nregs (VEC_REGS, big_mode) == 1)) | |
10633 | return 1; | |
10634 | ||
10635 | /* Likewise for access registers, since they have only half the | |
10636 | word size on 64-bit. */ | |
10637 | if (reg_classes_intersect_p (ACCESS_REGS, rclass)) | |
10638 | return 1; | |
10639 | ||
10640 | return 0; | |
74aa8b4b AK |
10641 | } |
10642 | ||
3597e113 VM |
10643 | /* Return true if we use LRA instead of reload pass. */ |
10644 | static bool | |
10645 | s390_lra_p (void) | |
10646 | { | |
10647 | return s390_lra_flag; | |
10648 | } | |
10649 | ||
91086990 UW |
10650 | /* Return true if register FROM can be eliminated via register TO. */ |
10651 | ||
7b5cbb57 AS |
10652 | static bool |
10653 | s390_can_eliminate (const int from, const int to) | |
91086990 | 10654 | { |
7633f08e UW |
10655 | /* On zSeries machines, we have not marked the base register as fixed. |
10656 | Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM. | |
10657 | If a function requires the base register, we say here that this | |
10658 | elimination cannot be performed. This will cause reload to free | |
10659 | up the base register (as if it were fixed). On the other hand, | |
10660 | if the current function does *not* require the base register, we | |
10661 | say here the elimination succeeds, which in turn allows reload | |
10662 | to allocate the base register for any other purpose. */ | |
10663 | if (from == BASE_REGNUM && to == BASE_REGNUM) | |
10664 | { | |
10665 | if (TARGET_CPU_ZARCH) | |
10666 | { | |
10667 | s390_init_frame_layout (); | |
10668 | return cfun->machine->base_reg == NULL_RTX; | |
10669 | } | |
10670 | ||
10671 | return false; | |
10672 | } | |
10673 | ||
10674 | /* Everything else must point into the stack frame. */ | |
91086990 UW |
10675 | gcc_assert (to == STACK_POINTER_REGNUM |
10676 | || to == HARD_FRAME_POINTER_REGNUM); | |
10677 | ||
10678 | gcc_assert (from == FRAME_POINTER_REGNUM | |
10679 | || from == ARG_POINTER_REGNUM | |
10680 | || from == RETURN_ADDRESS_POINTER_REGNUM); | |
10681 | ||
10682 | /* Make sure we actually saved the return address. */ | |
10683 | if (from == RETURN_ADDRESS_POINTER_REGNUM) | |
e3b5732b JH |
10684 | if (!crtl->calls_eh_return |
10685 | && !cfun->stdarg | |
91086990 UW |
10686 | && !cfun_frame_layout.save_return_addr_p) |
10687 | return false; | |
10688 | ||
10689 | return true; | |
10690 | } | |
10691 | ||
10692 | /* Return offset between register FROM and TO initially after prolog. */ | |
a38e09bc AK |
10693 | |
10694 | HOST_WIDE_INT | |
91086990 | 10695 | s390_initial_elimination_offset (int from, int to) |
a38e09bc | 10696 | { |
91086990 | 10697 | HOST_WIDE_INT offset; |
a38e09bc | 10698 | |
91086990 UW |
10699 | /* ??? Why are we called for non-eliminable pairs? */ |
10700 | if (!s390_can_eliminate (from, to)) | |
10701 | return 0; | |
10702 | ||
10703 | switch (from) | |
10704 | { | |
10705 | case FRAME_POINTER_REGNUM: | |
f4aa3848 | 10706 | offset = (get_frame_size() |
63296cb1 | 10707 | + STACK_POINTER_OFFSET |
38173d38 | 10708 | + crtl->outgoing_args_size); |
91086990 | 10709 | break; |
adf39f8f | 10710 | |
91086990 UW |
10711 | case ARG_POINTER_REGNUM: |
10712 | s390_init_frame_layout (); | |
10713 | offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET; | |
10714 | break; | |
10715 | ||
10716 | case RETURN_ADDRESS_POINTER_REGNUM: | |
10717 | s390_init_frame_layout (); | |
6455a49e AK |
10718 | |
10719 | if (cfun_frame_layout.first_save_gpr_slot == -1) | |
10720 | { | |
10721 | /* If it turns out that for stdarg nothing went into the reg | |
10722 | save area we also do not need the return address | |
10723 | pointer. */ | |
10724 | if (cfun->stdarg && !cfun_save_arg_fprs_p) | |
10725 | return 0; | |
10726 | ||
10727 | gcc_unreachable (); | |
10728 | } | |
10729 | ||
10730 | /* In order to make the following work it is not necessary for | |
10731 | r14 to have a save slot. It is sufficient if one other GPR | |
10732 | got one. Since the GPRs are always stored without gaps we | |
10733 | are able to calculate where the r14 save slot would | |
10734 | reside. */ | |
10735 | offset = (cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset + | |
10736 | (RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot) * | |
10737 | UNITS_PER_LONG); | |
91086990 UW |
10738 | break; |
10739 | ||
7633f08e UW |
10740 | case BASE_REGNUM: |
10741 | offset = 0; | |
10742 | break; | |
10743 | ||
91086990 UW |
10744 | default: |
10745 | gcc_unreachable (); | |
10746 | } | |
10747 | ||
10748 | return offset; | |
a38e09bc AK |
10749 | } |
10750 | ||
4023fb28 | 10751 | /* Emit insn to save fpr REGNUM at offset OFFSET relative |
c7453384 | 10752 | to register BASE. Return generated insn. */ |
994fe660 | 10753 | |
9db1d521 | 10754 | static rtx |
9c808aad | 10755 | save_fpr (rtx base, int offset, int regnum) |
9db1d521 | 10756 | { |
4023fb28 | 10757 | rtx addr; |
0a81f074 | 10758 | addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset)); |
dcc9eb26 AK |
10759 | |
10760 | if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG)) | |
10761 | set_mem_alias_set (addr, get_varargs_alias_set ()); | |
10762 | else | |
10763 | set_mem_alias_set (addr, get_frame_alias_set ()); | |
9db1d521 | 10764 | |
4023fb28 UW |
10765 | return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum)); |
10766 | } | |
9db1d521 | 10767 | |
4023fb28 | 10768 | /* Emit insn to restore fpr REGNUM from offset OFFSET relative |
c7453384 | 10769 | to register BASE. Return generated insn. */ |
9db1d521 | 10770 | |
4023fb28 | 10771 | static rtx |
9c808aad | 10772 | restore_fpr (rtx base, int offset, int regnum) |
4023fb28 UW |
10773 | { |
10774 | rtx addr; | |
0a81f074 | 10775 | addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset)); |
dcc9eb26 | 10776 | set_mem_alias_set (addr, get_frame_alias_set ()); |
9db1d521 | 10777 | |
4023fb28 | 10778 | return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr); |
9db1d521 HP |
10779 | } |
10780 | ||
75707b28 JJ |
10781 | /* Return true if REGNO is a global register, but not one |
10782 | of the special ones that need to be saved/restored in anyway. */ | |
10783 | ||
10784 | static inline bool | |
10785 | global_not_special_regno_p (int regno) | |
10786 | { | |
10787 | return (global_regs[regno] | |
10788 | /* These registers are special and need to be | |
10789 | restored in any case. */ | |
10790 | && !(regno == STACK_POINTER_REGNUM | |
10791 | || regno == RETURN_REGNUM | |
10792 | || regno == BASE_REGNUM | |
10793 | || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM))); | |
10794 | } | |
10795 | ||
c3cc6b78 | 10796 | /* Generate insn to save registers FIRST to LAST into |
c7453384 | 10797 | the register save area located at offset OFFSET |
c3cc6b78 | 10798 | relative to register BASE. */ |
9db1d521 | 10799 | |
c3cc6b78 | 10800 | static rtx |
9c808aad | 10801 | save_gprs (rtx base, int offset, int first, int last) |
9db1d521 | 10802 | { |
c3cc6b78 UW |
10803 | rtx addr, insn, note; |
10804 | int i; | |
10805 | ||
0a81f074 | 10806 | addr = plus_constant (Pmode, base, offset); |
c3cc6b78 | 10807 | addr = gen_rtx_MEM (Pmode, addr); |
dcc9eb26 AK |
10808 | |
10809 | set_mem_alias_set (addr, get_frame_alias_set ()); | |
c3cc6b78 UW |
10810 | |
10811 | /* Special-case single register. */ | |
10812 | if (first == last) | |
10813 | { | |
10814 | if (TARGET_64BIT) | |
10815 | insn = gen_movdi (addr, gen_rtx_REG (Pmode, first)); | |
10816 | else | |
10817 | insn = gen_movsi (addr, gen_rtx_REG (Pmode, first)); | |
10818 | ||
75707b28 JJ |
10819 | if (!global_not_special_regno_p (first)) |
10820 | RTX_FRAME_RELATED_P (insn) = 1; | |
c3cc6b78 UW |
10821 | return insn; |
10822 | } | |
10823 | ||
10824 | ||
10825 | insn = gen_store_multiple (addr, | |
10826 | gen_rtx_REG (Pmode, first), | |
10827 | GEN_INT (last - first + 1)); | |
10828 | ||
e3b5732b | 10829 | if (first <= 6 && cfun->stdarg) |
dcc9eb26 AK |
10830 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) |
10831 | { | |
10832 | rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0); | |
f4aa3848 | 10833 | |
dcc9eb26 AK |
10834 | if (first + i <= 6) |
10835 | set_mem_alias_set (mem, get_varargs_alias_set ()); | |
10836 | } | |
c3cc6b78 UW |
10837 | |
10838 | /* We need to set the FRAME_RELATED flag on all SETs | |
10839 | inside the store-multiple pattern. | |
10840 | ||
10841 | However, we must not emit DWARF records for registers 2..5 | |
c7453384 | 10842 | if they are stored for use by variable arguments ... |
c3cc6b78 | 10843 | |
a4d05547 | 10844 | ??? Unfortunately, it is not enough to simply not the |
c3cc6b78 UW |
10845 | FRAME_RELATED flags for those SETs, because the first SET |
10846 | of the PARALLEL is always treated as if it had the flag | |
10847 | set, even if it does not. Therefore we emit a new pattern | |
10848 | without those registers as REG_FRAME_RELATED_EXPR note. */ | |
10849 | ||
75707b28 | 10850 | if (first >= 6 && !global_not_special_regno_p (first)) |
c3cc6b78 UW |
10851 | { |
10852 | rtx pat = PATTERN (insn); | |
10853 | ||
10854 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
75707b28 JJ |
10855 | if (GET_CODE (XVECEXP (pat, 0, i)) == SET |
10856 | && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat, | |
10857 | 0, i))))) | |
c3cc6b78 UW |
10858 | RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1; |
10859 | ||
10860 | RTX_FRAME_RELATED_P (insn) = 1; | |
10861 | } | |
10862 | else if (last >= 6) | |
10863 | { | |
75707b28 JJ |
10864 | int start; |
10865 | ||
10866 | for (start = first >= 6 ? first : 6; start <= last; start++) | |
10867 | if (!global_not_special_regno_p (start)) | |
10868 | break; | |
10869 | ||
10870 | if (start > last) | |
10871 | return insn; | |
10872 | ||
0a81f074 RS |
10873 | addr = plus_constant (Pmode, base, |
10874 | offset + (start - first) * UNITS_PER_LONG); | |
6455a49e AK |
10875 | |
10876 | if (start == last) | |
10877 | { | |
10878 | if (TARGET_64BIT) | |
10879 | note = gen_movdi (gen_rtx_MEM (Pmode, addr), | |
10880 | gen_rtx_REG (Pmode, start)); | |
10881 | else | |
10882 | note = gen_movsi (gen_rtx_MEM (Pmode, addr), | |
10883 | gen_rtx_REG (Pmode, start)); | |
10884 | note = PATTERN (note); | |
10885 | ||
10886 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, note); | |
10887 | RTX_FRAME_RELATED_P (insn) = 1; | |
10888 | ||
10889 | return insn; | |
10890 | } | |
10891 | ||
c7453384 | 10892 | note = gen_store_multiple (gen_rtx_MEM (Pmode, addr), |
75707b28 JJ |
10893 | gen_rtx_REG (Pmode, start), |
10894 | GEN_INT (last - start + 1)); | |
c3cc6b78 UW |
10895 | note = PATTERN (note); |
10896 | ||
bbbbb16a | 10897 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, note); |
c3cc6b78 UW |
10898 | |
10899 | for (i = 0; i < XVECLEN (note, 0); i++) | |
75707b28 JJ |
10900 | if (GET_CODE (XVECEXP (note, 0, i)) == SET |
10901 | && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note, | |
10902 | 0, i))))) | |
c3cc6b78 UW |
10903 | RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1; |
10904 | ||
10905 | RTX_FRAME_RELATED_P (insn) = 1; | |
10906 | } | |
10907 | ||
10908 | return insn; | |
4023fb28 | 10909 | } |
9db1d521 | 10910 | |
c3cc6b78 | 10911 | /* Generate insn to restore registers FIRST to LAST from |
c7453384 | 10912 | the register save area located at offset OFFSET |
c3cc6b78 | 10913 | relative to register BASE. */ |
9db1d521 | 10914 | |
c3cc6b78 | 10915 | static rtx |
9c808aad | 10916 | restore_gprs (rtx base, int offset, int first, int last) |
4023fb28 | 10917 | { |
c3cc6b78 UW |
10918 | rtx addr, insn; |
10919 | ||
0a81f074 | 10920 | addr = plus_constant (Pmode, base, offset); |
c3cc6b78 | 10921 | addr = gen_rtx_MEM (Pmode, addr); |
dcc9eb26 | 10922 | set_mem_alias_set (addr, get_frame_alias_set ()); |
c3cc6b78 UW |
10923 | |
10924 | /* Special-case single register. */ | |
10925 | if (first == last) | |
10926 | { | |
10927 | if (TARGET_64BIT) | |
10928 | insn = gen_movdi (gen_rtx_REG (Pmode, first), addr); | |
10929 | else | |
10930 | insn = gen_movsi (gen_rtx_REG (Pmode, first), addr); | |
10931 | ||
6455a49e | 10932 | RTX_FRAME_RELATED_P (insn) = 1; |
c3cc6b78 UW |
10933 | return insn; |
10934 | } | |
10935 | ||
10936 | insn = gen_load_multiple (gen_rtx_REG (Pmode, first), | |
10937 | addr, | |
10938 | GEN_INT (last - first + 1)); | |
6455a49e | 10939 | RTX_FRAME_RELATED_P (insn) = 1; |
c3cc6b78 | 10940 | return insn; |
4023fb28 | 10941 | } |
9db1d521 | 10942 | |
585539a1 | 10943 | /* Return insn sequence to load the GOT register. */ |
fd7643fb | 10944 | |
775c43d3 | 10945 | rtx_insn * |
585539a1 | 10946 | s390_load_got (void) |
fd7643fb | 10947 | { |
775c43d3 | 10948 | rtx_insn *insns; |
585539a1 | 10949 | |
68c0ef75 AK |
10950 | /* We cannot use pic_offset_table_rtx here since we use this |
10951 | function also for non-pic if __tls_get_offset is called and in | |
10952 | that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx | |
10953 | aren't usable. */ | |
10954 | rtx got_rtx = gen_rtx_REG (Pmode, 12); | |
10955 | ||
585539a1 UW |
10956 | start_sequence (); |
10957 | ||
9e8327e3 | 10958 | if (TARGET_CPU_ZARCH) |
fd7643fb | 10959 | { |
935b5226 | 10960 | emit_move_insn (got_rtx, s390_got_symbol ()); |
fd7643fb UW |
10961 | } |
10962 | else | |
10963 | { | |
585539a1 | 10964 | rtx offset; |
fd7643fb | 10965 | |
935b5226 | 10966 | offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, s390_got_symbol ()), |
fd7643fb UW |
10967 | UNSPEC_LTREL_OFFSET); |
10968 | offset = gen_rtx_CONST (Pmode, offset); | |
10969 | offset = force_const_mem (Pmode, offset); | |
10970 | ||
68c0ef75 | 10971 | emit_move_insn (got_rtx, offset); |
fd7643fb | 10972 | |
c7453384 | 10973 | offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)), |
fd7643fb | 10974 | UNSPEC_LTREL_BASE); |
68c0ef75 | 10975 | offset = gen_rtx_PLUS (Pmode, got_rtx, offset); |
fd7643fb | 10976 | |
68c0ef75 | 10977 | emit_move_insn (got_rtx, offset); |
fd7643fb | 10978 | } |
585539a1 UW |
10979 | |
10980 | insns = get_insns (); | |
10981 | end_sequence (); | |
10982 | return insns; | |
fd7643fb UW |
10983 | } |
10984 | ||
12959abe AK |
10985 | /* This ties together stack memory (MEM with an alias set of frame_alias_set) |
10986 | and the change to the stack pointer. */ | |
10987 | ||
10988 | static void | |
10989 | s390_emit_stack_tie (void) | |
10990 | { | |
10991 | rtx mem = gen_frame_mem (BLKmode, | |
10992 | gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); | |
10993 | ||
10994 | emit_insn (gen_stack_tie (mem)); | |
10995 | } | |
10996 | ||
6455a49e AK |
10997 | /* Copy GPRS into FPR save slots. */ |
10998 | ||
10999 | static void | |
11000 | s390_save_gprs_to_fprs (void) | |
11001 | { | |
11002 | int i; | |
11003 | ||
11004 | if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf) | |
11005 | return; | |
11006 | ||
11007 | for (i = 6; i < 16; i++) | |
11008 | { | |
11009 | if (FP_REGNO_P (cfun_gpr_save_slot (i))) | |
11010 | { | |
775c43d3 | 11011 | rtx_insn *insn = |
6455a49e AK |
11012 | emit_move_insn (gen_rtx_REG (DImode, cfun_gpr_save_slot (i)), |
11013 | gen_rtx_REG (DImode, i)); | |
11014 | RTX_FRAME_RELATED_P (insn) = 1; | |
b8fedf99 AK |
11015 | /* This prevents dwarf2cfi from interpreting the set. Doing |
11016 | so it might emit def_cfa_register infos setting an FPR as | |
11017 | new CFA. */ | |
efa68ffc | 11018 | add_reg_note (insn, REG_CFA_REGISTER, copy_rtx (PATTERN (insn))); |
6455a49e AK |
11019 | } |
11020 | } | |
11021 | } | |
11022 | ||
11023 | /* Restore GPRs from FPR save slots. */ | |
11024 | ||
11025 | static void | |
11026 | s390_restore_gprs_from_fprs (void) | |
11027 | { | |
11028 | int i; | |
11029 | ||
11030 | if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf) | |
11031 | return; | |
11032 | ||
11033 | for (i = 6; i < 16; i++) | |
11034 | { | |
82c6f58a AK |
11035 | rtx_insn *insn; |
11036 | ||
11037 | if (!FP_REGNO_P (cfun_gpr_save_slot (i))) | |
11038 | continue; | |
11039 | ||
11040 | rtx fpr = gen_rtx_REG (DImode, cfun_gpr_save_slot (i)); | |
11041 | ||
11042 | if (i == STACK_POINTER_REGNUM) | |
11043 | insn = emit_insn (gen_stack_restore_from_fpr (fpr)); | |
11044 | else | |
11045 | insn = emit_move_insn (gen_rtx_REG (DImode, i), fpr); | |
11046 | ||
11047 | df_set_regs_ever_live (i, true); | |
11048 | add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, i)); | |
11049 | if (i == STACK_POINTER_REGNUM) | |
11050 | add_reg_note (insn, REG_CFA_DEF_CFA, | |
11051 | plus_constant (Pmode, stack_pointer_rtx, | |
11052 | STACK_POINTER_OFFSET)); | |
11053 | RTX_FRAME_RELATED_P (insn) = 1; | |
6455a49e AK |
11054 | } |
11055 | } | |
11056 | ||
9db1d521 | 11057 | |
4099494d RS |
11058 | /* A pass run immediately before shrink-wrapping and prologue and epilogue |
11059 | generation. */ | |
11060 | ||
4099494d RS |
11061 | namespace { |
11062 | ||
11063 | const pass_data pass_data_s390_early_mach = | |
11064 | { | |
11065 | RTL_PASS, /* type */ | |
11066 | "early_mach", /* name */ | |
11067 | OPTGROUP_NONE, /* optinfo_flags */ | |
4099494d RS |
11068 | TV_MACH_DEP, /* tv_id */ |
11069 | 0, /* properties_required */ | |
11070 | 0, /* properties_provided */ | |
11071 | 0, /* properties_destroyed */ | |
11072 | 0, /* todo_flags_start */ | |
3bea341f | 11073 | ( TODO_df_verify | TODO_df_finish ), /* todo_flags_finish */ |
4099494d | 11074 | }; |
585539a1 | 11075 | |
4099494d RS |
11076 | class pass_s390_early_mach : public rtl_opt_pass |
11077 | { | |
11078 | public: | |
11079 | pass_s390_early_mach (gcc::context *ctxt) | |
11080 | : rtl_opt_pass (pass_data_s390_early_mach, ctxt) | |
11081 | {} | |
11082 | ||
11083 | /* opt_pass methods: */ | |
be55bfe6 | 11084 | virtual unsigned int execute (function *); |
4099494d RS |
11085 | |
11086 | }; // class pass_s390_early_mach | |
11087 | ||
be55bfe6 TS |
11088 | unsigned int |
11089 | pass_s390_early_mach::execute (function *fun) | |
11090 | { | |
775c43d3 | 11091 | rtx_insn *insn; |
be55bfe6 TS |
11092 | |
11093 | /* Try to get rid of the FPR clobbers. */ | |
11094 | s390_optimize_nonescaping_tx (); | |
11095 | ||
11096 | /* Re-compute register info. */ | |
11097 | s390_register_info (); | |
11098 | ||
11099 | /* If we're using a base register, ensure that it is always valid for | |
11100 | the first non-prologue instruction. */ | |
11101 | if (fun->machine->base_reg) | |
11102 | emit_insn_at_entry (gen_main_pool (fun->machine->base_reg)); | |
11103 | ||
11104 | /* Annotate all constant pool references to let the scheduler know | |
11105 | they implicitly use the base register. */ | |
11106 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
11107 | if (INSN_P (insn)) | |
11108 | { | |
11109 | annotate_constant_pool_refs (&PATTERN (insn)); | |
11110 | df_insn_rescan (insn); | |
11111 | } | |
11112 | return 0; | |
11113 | } | |
11114 | ||
4099494d RS |
11115 | } // anon namespace |
11116 | ||
11117 | /* Expand the prologue into a bunch of separate insns. */ | |
11118 | ||
11119 | void | |
11120 | s390_emit_prologue (void) | |
11121 | { | |
11122 | rtx insn, addr; | |
11123 | rtx temp_reg; | |
11124 | int i; | |
11125 | int offset; | |
11126 | int next_fpr = 0; | |
585539a1 | 11127 | |
c7453384 | 11128 | /* Choose best register to use for temp use within prologue. |
4cb4721f MK |
11129 | TPF with profiling must avoid the register 14 - the tracing function |
11130 | needs the original contents of r14 to be preserved. */ | |
c7453384 | 11131 | |
f4aa3848 | 11132 | if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM) |
416ff32e | 11133 | && !crtl->is_leaf |
7bcebb25 | 11134 | && !TARGET_TPF_PROFILING) |
4023fb28 | 11135 | temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM); |
4cb4721f MK |
11136 | else if (flag_split_stack && cfun->stdarg) |
11137 | temp_reg = gen_rtx_REG (Pmode, 12); | |
9db1d521 | 11138 | else |
4023fb28 | 11139 | temp_reg = gen_rtx_REG (Pmode, 1); |
9db1d521 | 11140 | |
6455a49e AK |
11141 | s390_save_gprs_to_fprs (); |
11142 | ||
4023fb28 | 11143 | /* Save call saved gprs. */ |
adf39f8f | 11144 | if (cfun_frame_layout.first_save_gpr != -1) |
2790879f | 11145 | { |
f4aa3848 AK |
11146 | insn = save_gprs (stack_pointer_rtx, |
11147 | cfun_frame_layout.gprs_offset + | |
9602b6a1 | 11148 | UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr |
fb3712f6 | 11149 | - cfun_frame_layout.first_save_gpr_slot), |
f4aa3848 | 11150 | cfun_frame_layout.first_save_gpr, |
2790879f AK |
11151 | cfun_frame_layout.last_save_gpr); |
11152 | emit_insn (insn); | |
11153 | } | |
4023fb28 | 11154 | |
5af2f3d3 | 11155 | /* Dummy insn to mark literal pool slot. */ |
c7453384 | 11156 | |
91086990 UW |
11157 | if (cfun->machine->base_reg) |
11158 | emit_insn (gen_main_pool (cfun->machine->base_reg)); | |
c7453384 | 11159 | |
adf39f8f | 11160 | offset = cfun_frame_layout.f0_offset; |
4023fb28 | 11161 | |
adf39f8f | 11162 | /* Save f0 and f2. */ |
2cf4c39e | 11163 | for (i = FPR0_REGNUM; i <= FPR0_REGNUM + 1; i++) |
adf39f8f | 11164 | { |
b89b22fc | 11165 | if (cfun_fpr_save_p (i)) |
adf39f8f | 11166 | { |
b89b22fc | 11167 | save_fpr (stack_pointer_rtx, offset, i); |
adf39f8f AK |
11168 | offset += 8; |
11169 | } | |
e179df83 AK |
11170 | else if (!TARGET_PACKED_STACK || cfun->stdarg) |
11171 | offset += 8; | |
adf39f8f | 11172 | } |
9db1d521 | 11173 | |
adf39f8f AK |
11174 | /* Save f4 and f6. */ |
11175 | offset = cfun_frame_layout.f4_offset; | |
2cf4c39e | 11176 | for (i = FPR4_REGNUM; i <= FPR4_REGNUM + 1; i++) |
adf39f8f | 11177 | { |
b89b22fc | 11178 | if (cfun_fpr_save_p (i)) |
4023fb28 | 11179 | { |
b89b22fc | 11180 | insn = save_fpr (stack_pointer_rtx, offset, i); |
adf39f8f AK |
11181 | offset += 8; |
11182 | ||
e179df83 AK |
11183 | /* If f4 and f6 are call clobbered they are saved due to |
11184 | stdargs and therefore are not frame related. */ | |
b89b22fc | 11185 | if (!call_really_used_regs[i]) |
adf39f8f | 11186 | RTX_FRAME_RELATED_P (insn) = 1; |
4023fb28 | 11187 | } |
e179df83 | 11188 | else if (!TARGET_PACKED_STACK || call_really_used_regs[i]) |
adf39f8f AK |
11189 | offset += 8; |
11190 | } | |
11191 | ||
b3d31392 | 11192 | if (TARGET_PACKED_STACK |
adf39f8f AK |
11193 | && cfun_save_high_fprs_p |
11194 | && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0) | |
11195 | { | |
11196 | offset = (cfun_frame_layout.f8_offset | |
11197 | + (cfun_frame_layout.high_fprs - 1) * 8); | |
11198 | ||
2cf4c39e | 11199 | for (i = FPR15_REGNUM; i >= FPR8_REGNUM && offset >= 0; i--) |
b89b22fc | 11200 | if (cfun_fpr_save_p (i)) |
adf39f8f | 11201 | { |
b89b22fc | 11202 | insn = save_fpr (stack_pointer_rtx, offset, i); |
f4aa3848 | 11203 | |
adf39f8f AK |
11204 | RTX_FRAME_RELATED_P (insn) = 1; |
11205 | offset -= 8; | |
11206 | } | |
11207 | if (offset >= cfun_frame_layout.f8_offset) | |
b89b22fc | 11208 | next_fpr = i; |
adf39f8f | 11209 | } |
f4aa3848 | 11210 | |
b3d31392 | 11211 | if (!TARGET_PACKED_STACK) |
2cf4c39e | 11212 | next_fpr = cfun_save_high_fprs_p ? FPR15_REGNUM : 0; |
9db1d521 | 11213 | |
a11e0df4 | 11214 | if (flag_stack_usage_info) |
5c779305 AK |
11215 | current_function_static_stack_size = cfun_frame_layout.frame_size; |
11216 | ||
4023fb28 | 11217 | /* Decrement stack pointer. */ |
9db1d521 | 11218 | |
adf39f8f | 11219 | if (cfun_frame_layout.frame_size > 0) |
4023fb28 | 11220 | { |
adf39f8f | 11221 | rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size); |
bbbbb16a | 11222 | rtx real_frame_off; |
9db1d521 | 11223 | |
d75f90f1 AK |
11224 | if (s390_stack_size) |
11225 | { | |
690e7b63 | 11226 | HOST_WIDE_INT stack_guard; |
d75f90f1 | 11227 | |
690e7b63 AK |
11228 | if (s390_stack_guard) |
11229 | stack_guard = s390_stack_guard; | |
d75f90f1 | 11230 | else |
690e7b63 AK |
11231 | { |
11232 | /* If no value for stack guard is provided the smallest power of 2 | |
11233 | larger than the current frame size is chosen. */ | |
11234 | stack_guard = 1; | |
11235 | while (stack_guard < cfun_frame_layout.frame_size) | |
11236 | stack_guard <<= 1; | |
11237 | } | |
d75f90f1 | 11238 | |
690e7b63 AK |
11239 | if (cfun_frame_layout.frame_size >= s390_stack_size) |
11240 | { | |
cabbe12a | 11241 | warning (0, "frame size of function %qs is %wd" |
690e7b63 | 11242 | " bytes exceeding user provided stack limit of " |
cabbe12a | 11243 | "%d bytes. " |
690e7b63 AK |
11244 | "An unconditional trap is added.", |
11245 | current_function_name(), cfun_frame_layout.frame_size, | |
11246 | s390_stack_size); | |
11247 | emit_insn (gen_trap ()); | |
d26d508a | 11248 | emit_barrier (); |
690e7b63 AK |
11249 | } |
11250 | else | |
11251 | { | |
a3e7e012 AK |
11252 | /* stack_guard has to be smaller than s390_stack_size. |
11253 | Otherwise we would emit an AND with zero which would | |
11254 | not match the test under mask pattern. */ | |
11255 | if (stack_guard >= s390_stack_size) | |
11256 | { | |
f137aa63 | 11257 | warning (0, "frame size of function %qs is %wd" |
a3e7e012 AK |
11258 | " bytes which is more than half the stack size. " |
11259 | "The dynamic check would not be reliable. " | |
11260 | "No check emitted for this function.", | |
11261 | current_function_name(), | |
11262 | cfun_frame_layout.frame_size); | |
11263 | } | |
690e7b63 | 11264 | else |
a3e7e012 AK |
11265 | { |
11266 | HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1) | |
11267 | & ~(stack_guard - 1)); | |
11268 | ||
11269 | rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx, | |
11270 | GEN_INT (stack_check_mask)); | |
11271 | if (TARGET_64BIT) | |
11272 | emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode, | |
11273 | t, const0_rtx), | |
11274 | t, const0_rtx, const0_rtx)); | |
11275 | else | |
11276 | emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode, | |
11277 | t, const0_rtx), | |
11278 | t, const0_rtx, const0_rtx)); | |
11279 | } | |
690e7b63 | 11280 | } |
d75f90f1 AK |
11281 | } |
11282 | ||
f4aa3848 | 11283 | if (s390_warn_framesize > 0 |
d75f90f1 | 11284 | && cfun_frame_layout.frame_size >= s390_warn_framesize) |
f137aa63 | 11285 | warning (0, "frame size of %qs is %wd bytes", |
d75f90f1 AK |
11286 | current_function_name (), cfun_frame_layout.frame_size); |
11287 | ||
11288 | if (s390_warn_dynamicstack_p && cfun->calls_alloca) | |
d4ee4d25 | 11289 | warning (0, "%qs uses dynamic stack allocation", current_function_name ()); |
d75f90f1 | 11290 | |
4023fb28 | 11291 | /* Save incoming stack pointer into temp reg. */ |
66480e91 | 11292 | if (TARGET_BACKCHAIN || next_fpr) |
adf39f8f | 11293 | insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx)); |
c7453384 | 11294 | |
fae778eb | 11295 | /* Subtract frame size from stack pointer. */ |
4023fb28 | 11296 | |
d3632d41 UW |
11297 | if (DISP_IN_RANGE (INTVAL (frame_off))) |
11298 | { | |
f7df4a84 | 11299 | insn = gen_rtx_SET (stack_pointer_rtx, |
f4aa3848 | 11300 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, |
9c808aad | 11301 | frame_off)); |
d3632d41 UW |
11302 | insn = emit_insn (insn); |
11303 | } | |
11304 | else | |
11305 | { | |
b5c67a49 | 11306 | if (!CONST_OK_FOR_K (INTVAL (frame_off))) |
d3632d41 UW |
11307 | frame_off = force_const_mem (Pmode, frame_off); |
11308 | ||
11309 | insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off)); | |
585539a1 | 11310 | annotate_constant_pool_refs (&PATTERN (insn)); |
d3632d41 | 11311 | } |
4023fb28 | 11312 | |
4023fb28 | 11313 | RTX_FRAME_RELATED_P (insn) = 1; |
bbbbb16a ILT |
11314 | real_frame_off = GEN_INT (-cfun_frame_layout.frame_size); |
11315 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, | |
f7df4a84 | 11316 | gen_rtx_SET (stack_pointer_rtx, |
bbbbb16a ILT |
11317 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, |
11318 | real_frame_off))); | |
4023fb28 UW |
11319 | |
11320 | /* Set backchain. */ | |
c7453384 | 11321 | |
66480e91 | 11322 | if (TARGET_BACKCHAIN) |
9db1d521 | 11323 | { |
adf39f8f | 11324 | if (cfun_frame_layout.backchain_offset) |
f4aa3848 | 11325 | addr = gen_rtx_MEM (Pmode, |
0a81f074 | 11326 | plus_constant (Pmode, stack_pointer_rtx, |
adf39f8f AK |
11327 | cfun_frame_layout.backchain_offset)); |
11328 | else | |
f4aa3848 | 11329 | addr = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
dcc9eb26 | 11330 | set_mem_alias_set (addr, get_frame_alias_set ()); |
4023fb28 | 11331 | insn = emit_insn (gen_move_insn (addr, temp_reg)); |
9db1d521 | 11332 | } |
7d798969 | 11333 | |
8f4f502f | 11334 | /* If we support non-call exceptions (e.g. for Java), |
7d798969 UW |
11335 | we need to make sure the backchain pointer is set up |
11336 | before any possibly trapping memory access. */ | |
8f4f502f | 11337 | if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions) |
7d798969 UW |
11338 | { |
11339 | addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)); | |
c41c1387 | 11340 | emit_clobber (addr); |
7d798969 | 11341 | } |
4023fb28 | 11342 | } |
9db1d521 | 11343 | |
4023fb28 | 11344 | /* Save fprs 8 - 15 (64 bit ABI). */ |
c7453384 | 11345 | |
adf39f8f | 11346 | if (cfun_save_high_fprs_p && next_fpr) |
4023fb28 | 11347 | { |
12959abe AK |
11348 | /* If the stack might be accessed through a different register |
11349 | we have to make sure that the stack pointer decrement is not | |
11350 | moved below the use of the stack slots. */ | |
11351 | s390_emit_stack_tie (); | |
11352 | ||
f4aa3848 | 11353 | insn = emit_insn (gen_add2_insn (temp_reg, |
adf39f8f AK |
11354 | GEN_INT (cfun_frame_layout.f8_offset))); |
11355 | ||
11356 | offset = 0; | |
9db1d521 | 11357 | |
2cf4c39e | 11358 | for (i = FPR8_REGNUM; i <= next_fpr; i++) |
b89b22fc | 11359 | if (cfun_fpr_save_p (i)) |
4023fb28 | 11360 | { |
0a81f074 | 11361 | rtx addr = plus_constant (Pmode, stack_pointer_rtx, |
adf39f8f AK |
11362 | cfun_frame_layout.frame_size |
11363 | + cfun_frame_layout.f8_offset | |
11364 | + offset); | |
f4aa3848 | 11365 | |
adf39f8f AK |
11366 | insn = save_fpr (temp_reg, offset, i); |
11367 | offset += 8; | |
4023fb28 | 11368 | RTX_FRAME_RELATED_P (insn) = 1; |
bbbbb16a | 11369 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
f7df4a84 | 11370 | gen_rtx_SET (gen_rtx_MEM (DFmode, addr), |
bbbbb16a | 11371 | gen_rtx_REG (DFmode, i))); |
4023fb28 UW |
11372 | } |
11373 | } | |
c7453384 | 11374 | |
4023fb28 | 11375 | /* Set frame pointer, if needed. */ |
c7453384 | 11376 | |
29742ba4 | 11377 | if (frame_pointer_needed) |
4023fb28 UW |
11378 | { |
11379 | insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); | |
11380 | RTX_FRAME_RELATED_P (insn) = 1; | |
11381 | } | |
9db1d521 | 11382 | |
4023fb28 | 11383 | /* Set up got pointer, if needed. */ |
c7453384 | 11384 | |
6fb5fa3c | 11385 | if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) |
585539a1 | 11386 | { |
775c43d3 | 11387 | rtx_insn *insns = s390_load_got (); |
585539a1 | 11388 | |
b32d5189 | 11389 | for (rtx_insn *insn = insns; insn; insn = NEXT_INSN (insn)) |
6fb5fa3c | 11390 | annotate_constant_pool_refs (&PATTERN (insn)); |
585539a1 UW |
11391 | |
11392 | emit_insn (insns); | |
11393 | } | |
c7453384 | 11394 | |
3839e36a | 11395 | if (TARGET_TPF_PROFILING) |
c7453384 EC |
11396 | { |
11397 | /* Generate a BAS instruction to serve as a function | |
11398 | entry intercept to facilitate the use of tracing | |
2f7e5a0d EC |
11399 | algorithms located at the branch target. */ |
11400 | emit_insn (gen_prologue_tpf ()); | |
c7453384 EC |
11401 | |
11402 | /* Emit a blockage here so that all code | |
11403 | lies between the profiling mechanisms. */ | |
11404 | emit_insn (gen_blockage ()); | |
11405 | } | |
4023fb28 | 11406 | } |
9db1d521 | 11407 | |
b1c9bc51 | 11408 | /* Expand the epilogue into a bunch of separate insns. */ |
9db1d521 | 11409 | |
4023fb28 | 11410 | void |
ed9676cf | 11411 | s390_emit_epilogue (bool sibcall) |
4023fb28 | 11412 | { |
75707b28 | 11413 | rtx frame_pointer, return_reg, cfa_restores = NULL_RTX; |
5d4d885c | 11414 | int area_bottom, area_top, offset = 0; |
adf39f8f | 11415 | int next_offset; |
4023fb28 | 11416 | rtvec p; |
7333171f | 11417 | int i; |
9db1d521 | 11418 | |
3839e36a | 11419 | if (TARGET_TPF_PROFILING) |
c7453384 EC |
11420 | { |
11421 | ||
11422 | /* Generate a BAS instruction to serve as a function | |
11423 | entry intercept to facilitate the use of tracing | |
2f7e5a0d | 11424 | algorithms located at the branch target. */ |
c7453384 | 11425 | |
c7453384 EC |
11426 | /* Emit a blockage here so that all code |
11427 | lies between the profiling mechanisms. */ | |
11428 | emit_insn (gen_blockage ()); | |
11429 | ||
2f7e5a0d | 11430 | emit_insn (gen_epilogue_tpf ()); |
c7453384 EC |
11431 | } |
11432 | ||
4023fb28 | 11433 | /* Check whether to use frame or stack pointer for restore. */ |
9db1d521 | 11434 | |
f4aa3848 | 11435 | frame_pointer = (frame_pointer_needed |
adf39f8f | 11436 | ? hard_frame_pointer_rtx : stack_pointer_rtx); |
9db1d521 | 11437 | |
adf39f8f | 11438 | s390_frame_area (&area_bottom, &area_top); |
9db1d521 | 11439 | |
c7453384 | 11440 | /* Check whether we can access the register save area. |
4023fb28 | 11441 | If not, increment the frame pointer as required. */ |
9db1d521 | 11442 | |
4023fb28 UW |
11443 | if (area_top <= area_bottom) |
11444 | { | |
11445 | /* Nothing to restore. */ | |
11446 | } | |
adf39f8f AK |
11447 | else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom) |
11448 | && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1)) | |
4023fb28 UW |
11449 | { |
11450 | /* Area is in range. */ | |
adf39f8f | 11451 | offset = cfun_frame_layout.frame_size; |
4023fb28 UW |
11452 | } |
11453 | else | |
11454 | { | |
75707b28 | 11455 | rtx insn, frame_off, cfa; |
9db1d521 | 11456 | |
c7453384 | 11457 | offset = area_bottom < 0 ? -area_bottom : 0; |
adf39f8f | 11458 | frame_off = GEN_INT (cfun_frame_layout.frame_size - offset); |
9db1d521 | 11459 | |
f7df4a84 | 11460 | cfa = gen_rtx_SET (frame_pointer, |
75707b28 | 11461 | gen_rtx_PLUS (Pmode, frame_pointer, frame_off)); |
d3632d41 UW |
11462 | if (DISP_IN_RANGE (INTVAL (frame_off))) |
11463 | { | |
f7df4a84 | 11464 | insn = gen_rtx_SET (frame_pointer, |
d3632d41 UW |
11465 | gen_rtx_PLUS (Pmode, frame_pointer, frame_off)); |
11466 | insn = emit_insn (insn); | |
11467 | } | |
11468 | else | |
11469 | { | |
b5c67a49 | 11470 | if (!CONST_OK_FOR_K (INTVAL (frame_off))) |
d3632d41 | 11471 | frame_off = force_const_mem (Pmode, frame_off); |
9db1d521 | 11472 | |
d3632d41 | 11473 | insn = emit_insn (gen_add2_insn (frame_pointer, frame_off)); |
585539a1 | 11474 | annotate_constant_pool_refs (&PATTERN (insn)); |
d3632d41 | 11475 | } |
75707b28 JJ |
11476 | add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa); |
11477 | RTX_FRAME_RELATED_P (insn) = 1; | |
4023fb28 | 11478 | } |
9db1d521 | 11479 | |
4023fb28 UW |
11480 | /* Restore call saved fprs. */ |
11481 | ||
11482 | if (TARGET_64BIT) | |
9db1d521 | 11483 | { |
adf39f8f AK |
11484 | if (cfun_save_high_fprs_p) |
11485 | { | |
11486 | next_offset = cfun_frame_layout.f8_offset; | |
2cf4c39e | 11487 | for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++) |
adf39f8f | 11488 | { |
b89b22fc | 11489 | if (cfun_fpr_save_p (i)) |
adf39f8f AK |
11490 | { |
11491 | restore_fpr (frame_pointer, | |
11492 | offset + next_offset, i); | |
75707b28 JJ |
11493 | cfa_restores |
11494 | = alloc_reg_note (REG_CFA_RESTORE, | |
11495 | gen_rtx_REG (DFmode, i), cfa_restores); | |
adf39f8f AK |
11496 | next_offset += 8; |
11497 | } | |
11498 | } | |
11499 | } | |
f4aa3848 | 11500 | |
9db1d521 HP |
11501 | } |
11502 | else | |
11503 | { | |
adf39f8f | 11504 | next_offset = cfun_frame_layout.f4_offset; |
b89b22fc | 11505 | /* f4, f6 */ |
2cf4c39e | 11506 | for (i = FPR4_REGNUM; i <= FPR4_REGNUM + 1; i++) |
adf39f8f | 11507 | { |
b89b22fc | 11508 | if (cfun_fpr_save_p (i)) |
adf39f8f AK |
11509 | { |
11510 | restore_fpr (frame_pointer, | |
11511 | offset + next_offset, i); | |
75707b28 JJ |
11512 | cfa_restores |
11513 | = alloc_reg_note (REG_CFA_RESTORE, | |
11514 | gen_rtx_REG (DFmode, i), cfa_restores); | |
adf39f8f AK |
11515 | next_offset += 8; |
11516 | } | |
b3d31392 | 11517 | else if (!TARGET_PACKED_STACK) |
adf39f8f AK |
11518 | next_offset += 8; |
11519 | } | |
f4aa3848 | 11520 | |
4023fb28 | 11521 | } |
9db1d521 | 11522 | |
4023fb28 UW |
11523 | /* Return register. */ |
11524 | ||
c7453384 | 11525 | return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM); |
4023fb28 UW |
11526 | |
11527 | /* Restore call saved gprs. */ | |
11528 | ||
adf39f8f | 11529 | if (cfun_frame_layout.first_restore_gpr != -1) |
4023fb28 | 11530 | { |
c3cc6b78 | 11531 | rtx insn, addr; |
1447dc69 HP |
11532 | int i; |
11533 | ||
c7453384 | 11534 | /* Check for global register and save them |
1447dc69 HP |
11535 | to stack location from where they get restored. */ |
11536 | ||
adf39f8f AK |
11537 | for (i = cfun_frame_layout.first_restore_gpr; |
11538 | i <= cfun_frame_layout.last_restore_gpr; | |
1447dc69 HP |
11539 | i++) |
11540 | { | |
75707b28 | 11541 | if (global_not_special_regno_p (i)) |
1447dc69 | 11542 | { |
0a81f074 | 11543 | addr = plus_constant (Pmode, frame_pointer, |
f4aa3848 | 11544 | offset + cfun_frame_layout.gprs_offset |
fb3712f6 | 11545 | + (i - cfun_frame_layout.first_save_gpr_slot) |
9602b6a1 | 11546 | * UNITS_PER_LONG); |
1447dc69 | 11547 | addr = gen_rtx_MEM (Pmode, addr); |
dcc9eb26 | 11548 | set_mem_alias_set (addr, get_frame_alias_set ()); |
1447dc69 | 11549 | emit_move_insn (addr, gen_rtx_REG (Pmode, i)); |
c7453384 | 11550 | } |
75707b28 JJ |
11551 | else |
11552 | cfa_restores | |
11553 | = alloc_reg_note (REG_CFA_RESTORE, | |
11554 | gen_rtx_REG (Pmode, i), cfa_restores); | |
1447dc69 | 11555 | } |
4023fb28 | 11556 | |
4ba66aee AK |
11557 | /* Fetch return address from stack before load multiple, |
11558 | this will do good for scheduling. | |
11559 | ||
11560 | Only do this if we already decided that r14 needs to be | |
11561 | saved to a stack slot. (And not just because r14 happens to | |
11562 | be in between two GPRs which need saving.) Otherwise it | |
11563 | would be difficult to take that decision back in | |
11564 | s390_optimize_prologue. | |
11565 | ||
11566 | This optimization is only helpful on in-order machines. */ | |
11567 | if (! sibcall | |
11568 | && cfun_gpr_save_slot (RETURN_REGNUM) == SAVE_SLOT_STACK | |
11569 | && s390_tune <= PROCESSOR_2097_Z10) | |
11570 | { | |
11571 | int return_regnum = find_unused_clobbered_reg(); | |
11572 | if (!return_regnum) | |
11573 | return_regnum = 4; | |
11574 | return_reg = gen_rtx_REG (Pmode, return_regnum); | |
11575 | ||
11576 | addr = plus_constant (Pmode, frame_pointer, | |
11577 | offset + cfun_frame_layout.gprs_offset | |
11578 | + (RETURN_REGNUM | |
11579 | - cfun_frame_layout.first_save_gpr_slot) | |
11580 | * UNITS_PER_LONG); | |
11581 | addr = gen_rtx_MEM (Pmode, addr); | |
11582 | set_mem_alias_set (addr, get_frame_alias_set ()); | |
11583 | emit_move_insn (return_reg, addr); | |
db716bde | 11584 | |
4ba66aee AK |
11585 | /* Once we did that optimization we have to make sure |
11586 | s390_optimize_prologue does not try to remove the store | |
11587 | of r14 since we will not be able to find the load issued | |
11588 | here. */ | |
11589 | cfun_frame_layout.save_return_addr_p = true; | |
9db1d521 | 11590 | } |
4023fb28 | 11591 | |
adf39f8f AK |
11592 | insn = restore_gprs (frame_pointer, |
11593 | offset + cfun_frame_layout.gprs_offset | |
f4aa3848 | 11594 | + (cfun_frame_layout.first_restore_gpr |
fb3712f6 | 11595 | - cfun_frame_layout.first_save_gpr_slot) |
9602b6a1 | 11596 | * UNITS_PER_LONG, |
adf39f8f AK |
11597 | cfun_frame_layout.first_restore_gpr, |
11598 | cfun_frame_layout.last_restore_gpr); | |
75707b28 JJ |
11599 | insn = emit_insn (insn); |
11600 | REG_NOTES (insn) = cfa_restores; | |
11601 | add_reg_note (insn, REG_CFA_DEF_CFA, | |
0a81f074 RS |
11602 | plus_constant (Pmode, stack_pointer_rtx, |
11603 | STACK_POINTER_OFFSET)); | |
75707b28 | 11604 | RTX_FRAME_RELATED_P (insn) = 1; |
4023fb28 | 11605 | } |
9db1d521 | 11606 | |
6455a49e AK |
11607 | s390_restore_gprs_from_fprs (); |
11608 | ||
ed9676cf AK |
11609 | if (! sibcall) |
11610 | { | |
c7453384 | 11611 | |
ed9676cf | 11612 | /* Return to caller. */ |
38899e29 | 11613 | |
ed9676cf | 11614 | p = rtvec_alloc (2); |
38899e29 | 11615 | |
3810076b | 11616 | RTVEC_ELT (p, 0) = ret_rtx; |
ed9676cf AK |
11617 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg); |
11618 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
11619 | } | |
9db1d521 HP |
11620 | } |
11621 | ||
177bc204 RS |
11622 | /* Implement TARGET_SET_UP_BY_PROLOGUE. */ |
11623 | ||
11624 | static void | |
11625 | s300_set_up_by_prologue (hard_reg_set_container *regs) | |
11626 | { | |
11627 | if (cfun->machine->base_reg | |
11628 | && !call_really_used_regs[REGNO (cfun->machine->base_reg)]) | |
11629 | SET_HARD_REG_BIT (regs->set, REGNO (cfun->machine->base_reg)); | |
11630 | } | |
11631 | ||
4cb4721f MK |
11632 | /* -fsplit-stack support. */ |
11633 | ||
11634 | /* A SYMBOL_REF for __morestack. */ | |
11635 | static GTY(()) rtx morestack_ref; | |
11636 | ||
11637 | /* When using -fsplit-stack, the allocation routines set a field in | |
11638 | the TCB to the bottom of the stack plus this much space, measured | |
11639 | in bytes. */ | |
11640 | ||
11641 | #define SPLIT_STACK_AVAILABLE 1024 | |
11642 | ||
11643 | /* Emit -fsplit-stack prologue, which goes before the regular function | |
11644 | prologue. */ | |
11645 | ||
11646 | void | |
11647 | s390_expand_split_stack_prologue (void) | |
11648 | { | |
11649 | rtx r1, guard, cc = NULL; | |
11650 | rtx_insn *insn; | |
11651 | /* Offset from thread pointer to __private_ss. */ | |
11652 | int psso = TARGET_64BIT ? 0x38 : 0x20; | |
11653 | /* Pointer size in bytes. */ | |
11654 | /* Frame size and argument size - the two parameters to __morestack. */ | |
11655 | HOST_WIDE_INT frame_size = cfun_frame_layout.frame_size; | |
11656 | /* Align argument size to 8 bytes - simplifies __morestack code. */ | |
11657 | HOST_WIDE_INT args_size = crtl->args.size >= 0 | |
11658 | ? ((crtl->args.size + 7) & ~7) | |
11659 | : 0; | |
11660 | /* Label to be called by __morestack. */ | |
11661 | rtx_code_label *call_done = NULL; | |
11662 | rtx_code_label *parm_base = NULL; | |
11663 | rtx tmp; | |
11664 | ||
11665 | gcc_assert (flag_split_stack && reload_completed); | |
11666 | if (!TARGET_CPU_ZARCH) | |
11667 | { | |
11668 | sorry ("CPUs older than z900 are not supported for -fsplit-stack"); | |
11669 | return; | |
11670 | } | |
11671 | ||
11672 | r1 = gen_rtx_REG (Pmode, 1); | |
11673 | ||
11674 | /* If no stack frame will be allocated, don't do anything. */ | |
11675 | if (!frame_size) | |
11676 | { | |
11677 | if (cfun->machine->split_stack_varargs_pointer != NULL_RTX) | |
11678 | { | |
11679 | /* If va_start is used, just use r15. */ | |
11680 | emit_move_insn (r1, | |
11681 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, | |
11682 | GEN_INT (STACK_POINTER_OFFSET))); | |
11683 | ||
11684 | } | |
11685 | return; | |
11686 | } | |
11687 | ||
11688 | if (morestack_ref == NULL_RTX) | |
11689 | { | |
11690 | morestack_ref = gen_rtx_SYMBOL_REF (Pmode, "__morestack"); | |
11691 | SYMBOL_REF_FLAGS (morestack_ref) |= (SYMBOL_FLAG_LOCAL | |
11692 | | SYMBOL_FLAG_FUNCTION); | |
11693 | } | |
11694 | ||
11695 | if (CONST_OK_FOR_K (frame_size) || CONST_OK_FOR_Op (frame_size)) | |
11696 | { | |
11697 | /* If frame_size will fit in an add instruction, do a stack space | |
11698 | check, and only call __morestack if there's not enough space. */ | |
11699 | ||
11700 | /* Get thread pointer. r1 is the only register we can always destroy - r0 | |
11701 | could contain a static chain (and cannot be used to address memory | |
11702 | anyway), r2-r6 can contain parameters, and r6-r15 are callee-saved. */ | |
11703 | emit_move_insn (r1, gen_rtx_REG (Pmode, TP_REGNUM)); | |
11704 | /* Aim at __private_ss. */ | |
11705 | guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, r1, psso)); | |
11706 | ||
11707 | /* If less that 1kiB used, skip addition and compare directly with | |
11708 | __private_ss. */ | |
11709 | if (frame_size > SPLIT_STACK_AVAILABLE) | |
11710 | { | |
11711 | emit_move_insn (r1, guard); | |
11712 | if (TARGET_64BIT) | |
11713 | emit_insn (gen_adddi3 (r1, r1, GEN_INT (frame_size))); | |
11714 | else | |
11715 | emit_insn (gen_addsi3 (r1, r1, GEN_INT (frame_size))); | |
11716 | guard = r1; | |
11717 | } | |
11718 | ||
11719 | /* Compare the (maybe adjusted) guard with the stack pointer. */ | |
11720 | cc = s390_emit_compare (LT, stack_pointer_rtx, guard); | |
11721 | } | |
11722 | ||
11723 | call_done = gen_label_rtx (); | |
11724 | parm_base = gen_label_rtx (); | |
11725 | ||
11726 | /* Emit the parameter block. */ | |
11727 | tmp = gen_split_stack_data (parm_base, call_done, | |
11728 | GEN_INT (frame_size), | |
11729 | GEN_INT (args_size)); | |
11730 | insn = emit_insn (tmp); | |
11731 | add_reg_note (insn, REG_LABEL_OPERAND, call_done); | |
11732 | LABEL_NUSES (call_done)++; | |
11733 | add_reg_note (insn, REG_LABEL_OPERAND, parm_base); | |
11734 | LABEL_NUSES (parm_base)++; | |
11735 | ||
11736 | /* %r1 = litbase. */ | |
11737 | insn = emit_move_insn (r1, gen_rtx_LABEL_REF (VOIDmode, parm_base)); | |
11738 | add_reg_note (insn, REG_LABEL_OPERAND, parm_base); | |
11739 | LABEL_NUSES (parm_base)++; | |
11740 | ||
11741 | /* Now, we need to call __morestack. It has very special calling | |
11742 | conventions: it preserves param/return/static chain registers for | |
11743 | calling main function body, and looks for its own parameters at %r1. */ | |
11744 | ||
11745 | if (cc != NULL) | |
11746 | { | |
11747 | tmp = gen_split_stack_cond_call (morestack_ref, cc, call_done); | |
11748 | ||
11749 | insn = emit_jump_insn (tmp); | |
11750 | JUMP_LABEL (insn) = call_done; | |
11751 | LABEL_NUSES (call_done)++; | |
11752 | ||
11753 | /* Mark the jump as very unlikely to be taken. */ | |
5fa396ad JH |
11754 | add_reg_br_prob_note (insn, |
11755 | profile_probability::very_unlikely ()); | |
4cb4721f MK |
11756 | |
11757 | if (cfun->machine->split_stack_varargs_pointer != NULL_RTX) | |
11758 | { | |
11759 | /* If va_start is used, and __morestack was not called, just use | |
11760 | r15. */ | |
11761 | emit_move_insn (r1, | |
11762 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, | |
11763 | GEN_INT (STACK_POINTER_OFFSET))); | |
11764 | } | |
11765 | } | |
11766 | else | |
11767 | { | |
11768 | tmp = gen_split_stack_call (morestack_ref, call_done); | |
11769 | insn = emit_jump_insn (tmp); | |
11770 | JUMP_LABEL (insn) = call_done; | |
11771 | LABEL_NUSES (call_done)++; | |
11772 | emit_barrier (); | |
11773 | } | |
11774 | ||
11775 | /* __morestack will call us here. */ | |
11776 | ||
11777 | emit_label (call_done); | |
11778 | } | |
11779 | ||
11780 | /* We may have to tell the dataflow pass that the split stack prologue | |
11781 | is initializing a register. */ | |
11782 | ||
11783 | static void | |
11784 | s390_live_on_entry (bitmap regs) | |
11785 | { | |
11786 | if (cfun->machine->split_stack_varargs_pointer != NULL_RTX) | |
11787 | { | |
11788 | gcc_assert (flag_split_stack); | |
11789 | bitmap_set_bit (regs, 1); | |
11790 | } | |
11791 | } | |
11792 | ||
177bc204 RS |
11793 | /* Return true if the function can use simple_return to return outside |
11794 | of a shrink-wrapped region. At present shrink-wrapping is supported | |
11795 | in all cases. */ | |
11796 | ||
11797 | bool | |
11798 | s390_can_use_simple_return_insn (void) | |
11799 | { | |
11800 | return true; | |
11801 | } | |
11802 | ||
11803 | /* Return true if the epilogue is guaranteed to contain only a return | |
11804 | instruction and if a direct return can therefore be used instead. | |
11805 | One of the main advantages of using direct return instructions | |
11806 | is that we can then use conditional returns. */ | |
11807 | ||
11808 | bool | |
11809 | s390_can_use_return_insn (void) | |
11810 | { | |
11811 | int i; | |
11812 | ||
11813 | if (!reload_completed) | |
11814 | return false; | |
11815 | ||
11816 | if (crtl->profile) | |
11817 | return false; | |
11818 | ||
11819 | if (TARGET_TPF_PROFILING) | |
11820 | return false; | |
11821 | ||
11822 | for (i = 0; i < 16; i++) | |
82379bdf | 11823 | if (cfun_gpr_save_slot (i) != SAVE_SLOT_NONE) |
177bc204 RS |
11824 | return false; |
11825 | ||
6e77facf AK |
11826 | /* For 31 bit this is not covered by the frame_size check below |
11827 | since f4, f6 are saved in the register save area without needing | |
11828 | additional stack space. */ | |
11829 | if (!TARGET_64BIT | |
11830 | && (cfun_fpr_save_p (FPR4_REGNUM) || cfun_fpr_save_p (FPR6_REGNUM))) | |
11831 | return false; | |
11832 | ||
177bc204 RS |
11833 | if (cfun->machine->base_reg |
11834 | && !call_really_used_regs[REGNO (cfun->machine->base_reg)]) | |
11835 | return false; | |
11836 | ||
11837 | return cfun_frame_layout.frame_size == 0; | |
11838 | } | |
9db1d521 | 11839 | |
085261c8 AK |
11840 | /* The VX ABI differs for vararg functions. Therefore we need the |
11841 | prototype of the callee to be available when passing vector type | |
11842 | values. */ | |
11843 | static const char * | |
11844 | s390_invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val) | |
11845 | { | |
11846 | return ((TARGET_VX_ABI | |
11847 | && typelist == 0 | |
11848 | && VECTOR_TYPE_P (TREE_TYPE (val)) | |
11849 | && (funcdecl == NULL_TREE | |
11850 | || (TREE_CODE (funcdecl) == FUNCTION_DECL | |
11851 | && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD))) | |
f3981e7e | 11852 | ? N_("vector argument passed to unprototyped function") |
085261c8 AK |
11853 | : NULL); |
11854 | } | |
11855 | ||
11856 | ||
c7453384 | 11857 | /* Return the size in bytes of a function argument of |
994fe660 UW |
11858 | type TYPE and/or mode MODE. At least one of TYPE or |
11859 | MODE must be specified. */ | |
9db1d521 HP |
11860 | |
11861 | static int | |
ef4bddc2 | 11862 | s390_function_arg_size (machine_mode mode, const_tree type) |
9db1d521 HP |
11863 | { |
11864 | if (type) | |
11865 | return int_size_in_bytes (type); | |
11866 | ||
d65f7478 | 11867 | /* No type info available for some library calls ... */ |
9db1d521 HP |
11868 | if (mode != BLKmode) |
11869 | return GET_MODE_SIZE (mode); | |
11870 | ||
11871 | /* If we have neither type nor mode, abort */ | |
8d933e31 | 11872 | gcc_unreachable (); |
9db1d521 HP |
11873 | } |
11874 | ||
085261c8 AK |
11875 | /* Return true if a function argument of type TYPE and mode MODE |
11876 | is to be passed in a vector register, if available. */ | |
11877 | ||
11878 | bool | |
11879 | s390_function_arg_vector (machine_mode mode, const_tree type) | |
11880 | { | |
11881 | if (!TARGET_VX_ABI) | |
11882 | return false; | |
11883 | ||
11884 | if (s390_function_arg_size (mode, type) > 16) | |
11885 | return false; | |
11886 | ||
11887 | /* No type info available for some library calls ... */ | |
11888 | if (!type) | |
11889 | return VECTOR_MODE_P (mode); | |
11890 | ||
11891 | /* The ABI says that record types with a single member are treated | |
11892 | just like that member would be. */ | |
11893 | while (TREE_CODE (type) == RECORD_TYPE) | |
11894 | { | |
11895 | tree field, single = NULL_TREE; | |
11896 | ||
11897 | for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) | |
11898 | { | |
11899 | if (TREE_CODE (field) != FIELD_DECL) | |
11900 | continue; | |
11901 | ||
11902 | if (single == NULL_TREE) | |
11903 | single = TREE_TYPE (field); | |
11904 | else | |
11905 | return false; | |
11906 | } | |
11907 | ||
11908 | if (single == NULL_TREE) | |
11909 | return false; | |
11910 | else | |
11911 | { | |
11912 | /* If the field declaration adds extra byte due to | |
11913 | e.g. padding this is not accepted as vector type. */ | |
11914 | if (int_size_in_bytes (single) <= 0 | |
11915 | || int_size_in_bytes (single) != int_size_in_bytes (type)) | |
11916 | return false; | |
11917 | type = single; | |
11918 | } | |
11919 | } | |
11920 | ||
11921 | return VECTOR_TYPE_P (type); | |
11922 | } | |
11923 | ||
82b1c974 UW |
11924 | /* Return true if a function argument of type TYPE and mode MODE |
11925 | is to be passed in a floating-point register, if available. */ | |
11926 | ||
11927 | static bool | |
ef4bddc2 | 11928 | s390_function_arg_float (machine_mode mode, const_tree type) |
82b1c974 | 11929 | { |
085261c8 | 11930 | if (s390_function_arg_size (mode, type) > 8) |
8c17530e UW |
11931 | return false; |
11932 | ||
82b1c974 UW |
11933 | /* Soft-float changes the ABI: no floating-point registers are used. */ |
11934 | if (TARGET_SOFT_FLOAT) | |
11935 | return false; | |
11936 | ||
11937 | /* No type info available for some library calls ... */ | |
11938 | if (!type) | |
4dc19cc0 | 11939 | return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode; |
82b1c974 UW |
11940 | |
11941 | /* The ABI says that record types with a single member are treated | |
11942 | just like that member would be. */ | |
11943 | while (TREE_CODE (type) == RECORD_TYPE) | |
11944 | { | |
11945 | tree field, single = NULL_TREE; | |
11946 | ||
910ad8de | 11947 | for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) |
82b1c974 UW |
11948 | { |
11949 | if (TREE_CODE (field) != FIELD_DECL) | |
11950 | continue; | |
11951 | ||
11952 | if (single == NULL_TREE) | |
11953 | single = TREE_TYPE (field); | |
11954 | else | |
11955 | return false; | |
11956 | } | |
11957 | ||
11958 | if (single == NULL_TREE) | |
11959 | return false; | |
11960 | else | |
11961 | type = single; | |
11962 | } | |
11963 | ||
11964 | return TREE_CODE (type) == REAL_TYPE; | |
11965 | } | |
11966 | ||
8c17530e UW |
11967 | /* Return true if a function argument of type TYPE and mode MODE |
11968 | is to be passed in an integer register, or a pair of integer | |
11969 | registers, if available. */ | |
11970 | ||
11971 | static bool | |
ef4bddc2 | 11972 | s390_function_arg_integer (machine_mode mode, const_tree type) |
8c17530e UW |
11973 | { |
11974 | int size = s390_function_arg_size (mode, type); | |
11975 | if (size > 8) | |
11976 | return false; | |
11977 | ||
11978 | /* No type info available for some library calls ... */ | |
11979 | if (!type) | |
11980 | return GET_MODE_CLASS (mode) == MODE_INT | |
4dc19cc0 | 11981 | || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode)); |
8c17530e UW |
11982 | |
11983 | /* We accept small integral (and similar) types. */ | |
11984 | if (INTEGRAL_TYPE_P (type) | |
38899e29 | 11985 | || POINTER_TYPE_P (type) |
0d697034 | 11986 | || TREE_CODE (type) == NULLPTR_TYPE |
8c17530e UW |
11987 | || TREE_CODE (type) == OFFSET_TYPE |
11988 | || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE)) | |
11989 | return true; | |
11990 | ||
11991 | /* We also accept structs of size 1, 2, 4, 8 that are not | |
38899e29 | 11992 | passed in floating-point registers. */ |
8c17530e UW |
11993 | if (AGGREGATE_TYPE_P (type) |
11994 | && exact_log2 (size) >= 0 | |
11995 | && !s390_function_arg_float (mode, type)) | |
11996 | return true; | |
11997 | ||
11998 | return false; | |
11999 | } | |
12000 | ||
994fe660 UW |
12001 | /* Return 1 if a function argument of type TYPE and mode MODE |
12002 | is to be passed by reference. The ABI specifies that only | |
12003 | structures of size 1, 2, 4, or 8 bytes are passed by value, | |
12004 | all other structures (and complex numbers) are passed by | |
12005 | reference. */ | |
12006 | ||
8cd5a4e0 | 12007 | static bool |
d5cc9181 | 12008 | s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED, |
ef4bddc2 | 12009 | machine_mode mode, const_tree type, |
8cd5a4e0 | 12010 | bool named ATTRIBUTE_UNUSED) |
9db1d521 HP |
12011 | { |
12012 | int size = s390_function_arg_size (mode, type); | |
085261c8 AK |
12013 | |
12014 | if (s390_function_arg_vector (mode, type)) | |
12015 | return false; | |
12016 | ||
8c17530e UW |
12017 | if (size > 8) |
12018 | return true; | |
9db1d521 HP |
12019 | |
12020 | if (type) | |
12021 | { | |
8c17530e | 12022 | if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0) |
085261c8 | 12023 | return true; |
9db1d521 | 12024 | |
8c17530e UW |
12025 | if (TREE_CODE (type) == COMPLEX_TYPE |
12026 | || TREE_CODE (type) == VECTOR_TYPE) | |
085261c8 | 12027 | return true; |
9db1d521 | 12028 | } |
c7453384 | 12029 | |
085261c8 | 12030 | return false; |
9db1d521 HP |
12031 | } |
12032 | ||
12033 | /* Update the data in CUM to advance over an argument of mode MODE and | |
12034 | data type TYPE. (TYPE is null for libcalls where that information | |
994fe660 UW |
12035 | may not be available.). The boolean NAMED specifies whether the |
12036 | argument is a named argument (as opposed to an unnamed argument | |
12037 | matching an ellipsis). */ | |
9db1d521 | 12038 | |
3cb1da52 | 12039 | static void |
ef4bddc2 | 12040 | s390_function_arg_advance (cumulative_args_t cum_v, machine_mode mode, |
085261c8 | 12041 | const_tree type, bool named) |
9db1d521 | 12042 | { |
d5cc9181 JR |
12043 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
12044 | ||
085261c8 AK |
12045 | if (s390_function_arg_vector (mode, type)) |
12046 | { | |
12047 | /* We are called for unnamed vector stdarg arguments which are | |
12048 | passed on the stack. In this case this hook does not have to | |
12049 | do anything since stack arguments are tracked by common | |
12050 | code. */ | |
12051 | if (!named) | |
12052 | return; | |
12053 | cum->vrs += 1; | |
12054 | } | |
12055 | else if (s390_function_arg_float (mode, type)) | |
9db1d521 | 12056 | { |
82b1c974 | 12057 | cum->fprs += 1; |
9db1d521 | 12058 | } |
8c17530e | 12059 | else if (s390_function_arg_integer (mode, type)) |
9db1d521 HP |
12060 | { |
12061 | int size = s390_function_arg_size (mode, type); | |
9602b6a1 | 12062 | cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG); |
9db1d521 | 12063 | } |
8c17530e | 12064 | else |
8d933e31 | 12065 | gcc_unreachable (); |
9db1d521 HP |
12066 | } |
12067 | ||
994fe660 UW |
12068 | /* Define where to put the arguments to a function. |
12069 | Value is zero to push the argument on the stack, | |
12070 | or a hard register in which to store the argument. | |
12071 | ||
12072 | MODE is the argument's machine mode. | |
12073 | TYPE is the data type of the argument (as a tree). | |
12074 | This is null for libcalls where that information may | |
12075 | not be available. | |
12076 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
12077 | the preceding args and about the function being called. | |
12078 | NAMED is nonzero if this argument is a named parameter | |
c7453384 | 12079 | (otherwise it is an extra parameter matching an ellipsis). |
994fe660 UW |
12080 | |
12081 | On S/390, we use general purpose registers 2 through 6 to | |
12082 | pass integer, pointer, and certain structure arguments, and | |
12083 | floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit) | |
12084 | to pass floating point arguments. All remaining arguments | |
12085 | are pushed to the stack. */ | |
9db1d521 | 12086 | |
3cb1da52 | 12087 | static rtx |
ef4bddc2 | 12088 | s390_function_arg (cumulative_args_t cum_v, machine_mode mode, |
085261c8 | 12089 | const_tree type, bool named) |
9db1d521 | 12090 | { |
d5cc9181 JR |
12091 | CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); |
12092 | ||
45901378 AK |
12093 | if (!named) |
12094 | s390_check_type_for_vector_abi (type, true, false); | |
085261c8 AK |
12095 | |
12096 | if (s390_function_arg_vector (mode, type)) | |
12097 | { | |
12098 | /* Vector arguments being part of the ellipsis are passed on the | |
12099 | stack. */ | |
12100 | if (!named || (cum->vrs + 1 > VEC_ARG_NUM_REG)) | |
12101 | return NULL_RTX; | |
12102 | ||
12103 | return gen_rtx_REG (mode, cum->vrs + FIRST_VEC_ARG_REGNO); | |
12104 | } | |
12105 | else if (s390_function_arg_float (mode, type)) | |
9db1d521 | 12106 | { |
29a79fcf | 12107 | if (cum->fprs + 1 > FP_ARG_NUM_REG) |
085261c8 | 12108 | return NULL_RTX; |
9db1d521 | 12109 | else |
f1c25d3b | 12110 | return gen_rtx_REG (mode, cum->fprs + 16); |
9db1d521 | 12111 | } |
8c17530e | 12112 | else if (s390_function_arg_integer (mode, type)) |
9db1d521 HP |
12113 | { |
12114 | int size = s390_function_arg_size (mode, type); | |
9602b6a1 | 12115 | int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG; |
9db1d521 | 12116 | |
29a79fcf | 12117 | if (cum->gprs + n_gprs > GP_ARG_NUM_REG) |
085261c8 | 12118 | return NULL_RTX; |
9602b6a1 | 12119 | else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG) |
f1c25d3b | 12120 | return gen_rtx_REG (mode, cum->gprs + 2); |
9602b6a1 AK |
12121 | else if (n_gprs == 2) |
12122 | { | |
12123 | rtvec p = rtvec_alloc (2); | |
12124 | ||
12125 | RTVEC_ELT (p, 0) | |
12126 | = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2), | |
12127 | const0_rtx); | |
12128 | RTVEC_ELT (p, 1) | |
12129 | = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3), | |
12130 | GEN_INT (4)); | |
12131 | ||
12132 | return gen_rtx_PARALLEL (mode, p); | |
12133 | } | |
9db1d521 | 12134 | } |
8c17530e UW |
12135 | |
12136 | /* After the real arguments, expand_call calls us once again | |
12137 | with a void_type_node type. Whatever we return here is | |
12138 | passed as operand 2 to the call expanders. | |
12139 | ||
12140 | We don't need this feature ... */ | |
12141 | else if (type == void_type_node) | |
12142 | return const0_rtx; | |
12143 | ||
8d933e31 | 12144 | gcc_unreachable (); |
8c17530e UW |
12145 | } |
12146 | ||
76b0cbf8 RS |
12147 | /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Vector arguments are |
12148 | left-justified when placed on the stack during parameter passing. */ | |
12149 | ||
12150 | static pad_direction | |
12151 | s390_function_arg_padding (machine_mode mode, const_tree type) | |
12152 | { | |
12153 | if (s390_function_arg_vector (mode, type)) | |
12154 | return PAD_UPWARD; | |
12155 | ||
12156 | return default_function_arg_padding (mode, type); | |
12157 | } | |
12158 | ||
8c17530e UW |
12159 | /* Return true if return values of type TYPE should be returned |
12160 | in a memory buffer whose address is passed by the caller as | |
12161 | hidden first argument. */ | |
12162 | ||
12163 | static bool | |
586de218 | 12164 | s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED) |
8c17530e UW |
12165 | { |
12166 | /* We accept small integral (and similar) types. */ | |
12167 | if (INTEGRAL_TYPE_P (type) | |
38899e29 | 12168 | || POINTER_TYPE_P (type) |
8c17530e UW |
12169 | || TREE_CODE (type) == OFFSET_TYPE |
12170 | || TREE_CODE (type) == REAL_TYPE) | |
12171 | return int_size_in_bytes (type) > 8; | |
12172 | ||
085261c8 AK |
12173 | /* vector types which fit into a VR. */ |
12174 | if (TARGET_VX_ABI | |
12175 | && VECTOR_TYPE_P (type) | |
12176 | && int_size_in_bytes (type) <= 16) | |
12177 | return false; | |
12178 | ||
8c17530e UW |
12179 | /* Aggregates and similar constructs are always returned |
12180 | in memory. */ | |
12181 | if (AGGREGATE_TYPE_P (type) | |
12182 | || TREE_CODE (type) == COMPLEX_TYPE | |
085261c8 | 12183 | || VECTOR_TYPE_P (type)) |
8c17530e UW |
12184 | return true; |
12185 | ||
12186 | /* ??? We get called on all sorts of random stuff from | |
12187 | aggregate_value_p. We can't abort, but it's not clear | |
12188 | what's safe to return. Pretend it's a struct I guess. */ | |
12189 | return true; | |
12190 | } | |
12191 | ||
cde0f3fd PB |
12192 | /* Function arguments and return values are promoted to word size. */ |
12193 | ||
ef4bddc2 RS |
12194 | static machine_mode |
12195 | s390_promote_function_mode (const_tree type, machine_mode mode, | |
cde0f3fd PB |
12196 | int *punsignedp, |
12197 | const_tree fntype ATTRIBUTE_UNUSED, | |
12198 | int for_return ATTRIBUTE_UNUSED) | |
12199 | { | |
12200 | if (INTEGRAL_MODE_P (mode) | |
9602b6a1 | 12201 | && GET_MODE_SIZE (mode) < UNITS_PER_LONG) |
cde0f3fd | 12202 | { |
5e617be8 | 12203 | if (type != NULL_TREE && POINTER_TYPE_P (type)) |
cde0f3fd PB |
12204 | *punsignedp = POINTERS_EXTEND_UNSIGNED; |
12205 | return Pmode; | |
12206 | } | |
12207 | ||
12208 | return mode; | |
12209 | } | |
12210 | ||
b46616fd AK |
12211 | /* Define where to return a (scalar) value of type RET_TYPE. |
12212 | If RET_TYPE is null, define where to return a (scalar) | |
8c17530e UW |
12213 | value of mode MODE from a libcall. */ |
12214 | ||
b46616fd | 12215 | static rtx |
ef4bddc2 | 12216 | s390_function_and_libcall_value (machine_mode mode, |
b46616fd AK |
12217 | const_tree ret_type, |
12218 | const_tree fntype_or_decl, | |
12219 | bool outgoing ATTRIBUTE_UNUSED) | |
8c17530e | 12220 | { |
085261c8 AK |
12221 | /* For vector return types it is important to use the RET_TYPE |
12222 | argument whenever available since the middle-end might have | |
12223 | changed the mode to a scalar mode. */ | |
12224 | bool vector_ret_type_p = ((ret_type && VECTOR_TYPE_P (ret_type)) | |
12225 | || (!ret_type && VECTOR_MODE_P (mode))); | |
12226 | ||
b46616fd AK |
12227 | /* For normal functions perform the promotion as |
12228 | promote_function_mode would do. */ | |
12229 | if (ret_type) | |
8c17530e | 12230 | { |
b46616fd AK |
12231 | int unsignedp = TYPE_UNSIGNED (ret_type); |
12232 | mode = promote_function_mode (ret_type, mode, &unsignedp, | |
12233 | fntype_or_decl, 1); | |
8c17530e UW |
12234 | } |
12235 | ||
085261c8 AK |
12236 | gcc_assert (GET_MODE_CLASS (mode) == MODE_INT |
12237 | || SCALAR_FLOAT_MODE_P (mode) | |
12238 | || (TARGET_VX_ABI && vector_ret_type_p)); | |
12239 | gcc_assert (GET_MODE_SIZE (mode) <= (TARGET_VX_ABI ? 16 : 8)); | |
8c17530e | 12240 | |
085261c8 AK |
12241 | if (TARGET_VX_ABI && vector_ret_type_p) |
12242 | return gen_rtx_REG (mode, FIRST_VEC_ARG_REGNO); | |
12243 | else if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode)) | |
8c17530e | 12244 | return gen_rtx_REG (mode, 16); |
9602b6a1 AK |
12245 | else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG |
12246 | || UNITS_PER_LONG == UNITS_PER_WORD) | |
8c17530e | 12247 | return gen_rtx_REG (mode, 2); |
9602b6a1 AK |
12248 | else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG) |
12249 | { | |
b46616fd AK |
12250 | /* This case is triggered when returning a 64 bit value with |
12251 | -m31 -mzarch. Although the value would fit into a single | |
12252 | register it has to be forced into a 32 bit register pair in | |
12253 | order to match the ABI. */ | |
9602b6a1 AK |
12254 | rtvec p = rtvec_alloc (2); |
12255 | ||
12256 | RTVEC_ELT (p, 0) | |
12257 | = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx); | |
12258 | RTVEC_ELT (p, 1) | |
12259 | = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4)); | |
12260 | ||
12261 | return gen_rtx_PARALLEL (mode, p); | |
12262 | } | |
12263 | ||
12264 | gcc_unreachable (); | |
9db1d521 HP |
12265 | } |
12266 | ||
b46616fd AK |
12267 | /* Define where to return a scalar return value of type RET_TYPE. */ |
12268 | ||
12269 | static rtx | |
12270 | s390_function_value (const_tree ret_type, const_tree fn_decl_or_type, | |
12271 | bool outgoing) | |
12272 | { | |
12273 | return s390_function_and_libcall_value (TYPE_MODE (ret_type), ret_type, | |
12274 | fn_decl_or_type, outgoing); | |
12275 | } | |
12276 | ||
12277 | /* Define where to return a scalar libcall return value of mode | |
12278 | MODE. */ | |
12279 | ||
12280 | static rtx | |
ef4bddc2 | 12281 | s390_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) |
b46616fd AK |
12282 | { |
12283 | return s390_function_and_libcall_value (mode, NULL_TREE, | |
12284 | NULL_TREE, true); | |
12285 | } | |
12286 | ||
9db1d521 | 12287 | |
994fe660 UW |
12288 | /* Create and return the va_list datatype. |
12289 | ||
12290 | On S/390, va_list is an array type equivalent to | |
12291 | ||
12292 | typedef struct __va_list_tag | |
12293 | { | |
12294 | long __gpr; | |
12295 | long __fpr; | |
12296 | void *__overflow_arg_area; | |
12297 | void *__reg_save_area; | |
994fe660 UW |
12298 | } va_list[1]; |
12299 | ||
12300 | where __gpr and __fpr hold the number of general purpose | |
12301 | or floating point arguments used up to now, respectively, | |
c7453384 | 12302 | __overflow_arg_area points to the stack location of the |
994fe660 UW |
12303 | next argument passed on the stack, and __reg_save_area |
12304 | always points to the start of the register area in the | |
12305 | call frame of the current function. The function prologue | |
12306 | saves all registers used for argument passing into this | |
12307 | area if the function uses variable arguments. */ | |
9db1d521 | 12308 | |
c35d187f RH |
12309 | static tree |
12310 | s390_build_builtin_va_list (void) | |
9db1d521 HP |
12311 | { |
12312 | tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl; | |
12313 | ||
47798692 | 12314 | record = lang_hooks.types.make_type (RECORD_TYPE); |
9db1d521 HP |
12315 | |
12316 | type_decl = | |
4c4bde29 AH |
12317 | build_decl (BUILTINS_LOCATION, |
12318 | TYPE_DECL, get_identifier ("__va_list_tag"), record); | |
9db1d521 | 12319 | |
4c4bde29 AH |
12320 | f_gpr = build_decl (BUILTINS_LOCATION, |
12321 | FIELD_DECL, get_identifier ("__gpr"), | |
9db1d521 | 12322 | long_integer_type_node); |
4c4bde29 AH |
12323 | f_fpr = build_decl (BUILTINS_LOCATION, |
12324 | FIELD_DECL, get_identifier ("__fpr"), | |
9db1d521 | 12325 | long_integer_type_node); |
4c4bde29 AH |
12326 | f_ovf = build_decl (BUILTINS_LOCATION, |
12327 | FIELD_DECL, get_identifier ("__overflow_arg_area"), | |
9db1d521 | 12328 | ptr_type_node); |
4c4bde29 AH |
12329 | f_sav = build_decl (BUILTINS_LOCATION, |
12330 | FIELD_DECL, get_identifier ("__reg_save_area"), | |
9db1d521 HP |
12331 | ptr_type_node); |
12332 | ||
29a79fcf UW |
12333 | va_list_gpr_counter_field = f_gpr; |
12334 | va_list_fpr_counter_field = f_fpr; | |
12335 | ||
9db1d521 HP |
12336 | DECL_FIELD_CONTEXT (f_gpr) = record; |
12337 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
12338 | DECL_FIELD_CONTEXT (f_ovf) = record; | |
12339 | DECL_FIELD_CONTEXT (f_sav) = record; | |
12340 | ||
0fd2eac2 | 12341 | TYPE_STUB_DECL (record) = type_decl; |
9db1d521 HP |
12342 | TYPE_NAME (record) = type_decl; |
12343 | TYPE_FIELDS (record) = f_gpr; | |
910ad8de NF |
12344 | DECL_CHAIN (f_gpr) = f_fpr; |
12345 | DECL_CHAIN (f_fpr) = f_ovf; | |
12346 | DECL_CHAIN (f_ovf) = f_sav; | |
9db1d521 HP |
12347 | |
12348 | layout_type (record); | |
12349 | ||
12350 | /* The correct type is an array type of one element. */ | |
12351 | return build_array_type (record, build_index_type (size_zero_node)); | |
12352 | } | |
12353 | ||
994fe660 | 12354 | /* Implement va_start by filling the va_list structure VALIST. |
6c535c69 ZW |
12355 | STDARG_P is always true, and ignored. |
12356 | NEXTARG points to the first anonymous stack argument. | |
994fe660 | 12357 | |
f710504c | 12358 | The following global variables are used to initialize |
994fe660 UW |
12359 | the va_list structure: |
12360 | ||
38173d38 | 12361 | crtl->args.info: |
994fe660 | 12362 | holds number of gprs and fprs used for named arguments. |
38173d38 | 12363 | crtl->args.arg_offset_rtx: |
994fe660 UW |
12364 | holds the offset of the first anonymous stack argument |
12365 | (relative to the virtual arg pointer). */ | |
9db1d521 | 12366 | |
d7bd8aeb | 12367 | static void |
9c808aad | 12368 | s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED) |
9db1d521 HP |
12369 | { |
12370 | HOST_WIDE_INT n_gpr, n_fpr; | |
12371 | int off; | |
12372 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
12373 | tree gpr, fpr, ovf, sav, t; | |
12374 | ||
12375 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); | |
910ad8de NF |
12376 | f_fpr = DECL_CHAIN (f_gpr); |
12377 | f_ovf = DECL_CHAIN (f_fpr); | |
12378 | f_sav = DECL_CHAIN (f_ovf); | |
9db1d521 | 12379 | |
86710a8b | 12380 | valist = build_simple_mem_ref (valist); |
47a25a46 RG |
12381 | gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
12382 | fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
12383 | ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
12384 | sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); | |
9db1d521 HP |
12385 | |
12386 | /* Count number of gp and fp argument registers used. */ | |
12387 | ||
38173d38 JH |
12388 | n_gpr = crtl->args.info.gprs; |
12389 | n_fpr = crtl->args.info.fprs; | |
9db1d521 | 12390 | |
29a79fcf UW |
12391 | if (cfun->va_list_gpr_size) |
12392 | { | |
726a989a RB |
12393 | t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr, |
12394 | build_int_cst (NULL_TREE, n_gpr)); | |
29a79fcf UW |
12395 | TREE_SIDE_EFFECTS (t) = 1; |
12396 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
12397 | } | |
9db1d521 | 12398 | |
29a79fcf UW |
12399 | if (cfun->va_list_fpr_size) |
12400 | { | |
726a989a | 12401 | t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr, |
47a25a46 | 12402 | build_int_cst (NULL_TREE, n_fpr)); |
29a79fcf UW |
12403 | TREE_SIDE_EFFECTS (t) = 1; |
12404 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
12405 | } | |
9db1d521 | 12406 | |
4cb4721f MK |
12407 | if (flag_split_stack |
12408 | && (lookup_attribute ("no_split_stack", DECL_ATTRIBUTES (cfun->decl)) | |
12409 | == NULL) | |
12410 | && cfun->machine->split_stack_varargs_pointer == NULL_RTX) | |
12411 | { | |
12412 | rtx reg; | |
12413 | rtx_insn *seq; | |
12414 | ||
12415 | reg = gen_reg_rtx (Pmode); | |
12416 | cfun->machine->split_stack_varargs_pointer = reg; | |
12417 | ||
12418 | start_sequence (); | |
12419 | emit_move_insn (reg, gen_rtx_REG (Pmode, 1)); | |
12420 | seq = get_insns (); | |
12421 | end_sequence (); | |
12422 | ||
12423 | push_topmost_sequence (); | |
12424 | emit_insn_after (seq, entry_of_function ()); | |
12425 | pop_topmost_sequence (); | |
12426 | } | |
12427 | ||
085261c8 AK |
12428 | /* Find the overflow area. |
12429 | FIXME: This currently is too pessimistic when the vector ABI is | |
12430 | enabled. In that case we *always* set up the overflow area | |
12431 | pointer. */ | |
29a79fcf | 12432 | if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG |
085261c8 AK |
12433 | || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG |
12434 | || TARGET_VX_ABI) | |
29a79fcf | 12435 | { |
4cb4721f MK |
12436 | if (cfun->machine->split_stack_varargs_pointer == NULL_RTX) |
12437 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
12438 | else | |
12439 | t = make_tree (TREE_TYPE (ovf), cfun->machine->split_stack_varargs_pointer); | |
9db1d521 | 12440 | |
38173d38 | 12441 | off = INTVAL (crtl->args.arg_offset_rtx); |
29a79fcf UW |
12442 | off = off < 0 ? 0 : off; |
12443 | if (TARGET_DEBUG_ARG) | |
12444 | fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n", | |
12445 | (int)n_gpr, (int)n_fpr, off); | |
9db1d521 | 12446 | |
5d49b6a7 | 12447 | t = fold_build_pointer_plus_hwi (t, off); |
9db1d521 | 12448 | |
726a989a | 12449 | t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); |
29a79fcf UW |
12450 | TREE_SIDE_EFFECTS (t) = 1; |
12451 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
12452 | } | |
9db1d521 HP |
12453 | |
12454 | /* Find the register save area. */ | |
29a79fcf UW |
12455 | if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG) |
12456 | || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG)) | |
12457 | { | |
12458 | t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx); | |
5d49b6a7 | 12459 | t = fold_build_pointer_plus_hwi (t, -RETURN_REGNUM * UNITS_PER_LONG); |
f4aa3848 | 12460 | |
726a989a | 12461 | t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t); |
29a79fcf UW |
12462 | TREE_SIDE_EFFECTS (t) = 1; |
12463 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
12464 | } | |
9db1d521 HP |
12465 | } |
12466 | ||
c7453384 | 12467 | /* Implement va_arg by updating the va_list structure |
994fe660 | 12468 | VALIST as required to retrieve an argument of type |
c7453384 EC |
12469 | TYPE, and returning that argument. |
12470 | ||
994fe660 | 12471 | Generates code equivalent to: |
c7453384 | 12472 | |
9db1d521 HP |
12473 | if (integral value) { |
12474 | if (size <= 4 && args.gpr < 5 || | |
c7453384 | 12475 | size > 4 && args.gpr < 4 ) |
9db1d521 HP |
12476 | ret = args.reg_save_area[args.gpr+8] |
12477 | else | |
12478 | ret = *args.overflow_arg_area++; | |
085261c8 AK |
12479 | } else if (vector value) { |
12480 | ret = *args.overflow_arg_area; | |
12481 | args.overflow_arg_area += size / 8; | |
9db1d521 HP |
12482 | } else if (float value) { |
12483 | if (args.fgpr < 2) | |
12484 | ret = args.reg_save_area[args.fpr+64] | |
12485 | else | |
12486 | ret = *args.overflow_arg_area++; | |
12487 | } else if (aggregate value) { | |
12488 | if (args.gpr < 5) | |
12489 | ret = *args.reg_save_area[args.gpr] | |
12490 | else | |
12491 | ret = **args.overflow_arg_area++; | |
12492 | } */ | |
12493 | ||
ab96de7e | 12494 | static tree |
f4aa3848 | 12495 | s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, |
726a989a | 12496 | gimple_seq *post_p ATTRIBUTE_UNUSED) |
9db1d521 HP |
12497 | { |
12498 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
12499 | tree gpr, fpr, ovf, sav, reg, t, u; | |
12500 | int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg; | |
e6b07173 | 12501 | tree lab_false, lab_over = NULL_TREE; |
085261c8 AK |
12502 | tree addr = create_tmp_var (ptr_type_node, "addr"); |
12503 | bool left_align_p; /* How a value < UNITS_PER_LONG is aligned within | |
12504 | a stack slot. */ | |
9db1d521 HP |
12505 | |
12506 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); | |
910ad8de NF |
12507 | f_fpr = DECL_CHAIN (f_gpr); |
12508 | f_ovf = DECL_CHAIN (f_fpr); | |
12509 | f_sav = DECL_CHAIN (f_ovf); | |
9db1d521 | 12510 | |
47a25a46 RG |
12511 | gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
12512 | fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
47a25a46 | 12513 | sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); |
9db1d521 | 12514 | |
726a989a RB |
12515 | /* The tree for args* cannot be shared between gpr/fpr and ovf since |
12516 | both appear on a lhs. */ | |
12517 | valist = unshare_expr (valist); | |
12518 | ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
12519 | ||
9db1d521 HP |
12520 | size = int_size_in_bytes (type); |
12521 | ||
45901378 AK |
12522 | s390_check_type_for_vector_abi (type, true, false); |
12523 | ||
8cd5a4e0 | 12524 | if (pass_by_reference (NULL, TYPE_MODE (type), type, false)) |
9db1d521 HP |
12525 | { |
12526 | if (TARGET_DEBUG_ARG) | |
12527 | { | |
12528 | fprintf (stderr, "va_arg: aggregate type"); | |
12529 | debug_tree (type); | |
12530 | } | |
12531 | ||
12532 | /* Aggregates are passed by reference. */ | |
12533 | indirect_p = 1; | |
12534 | reg = gpr; | |
12535 | n_reg = 1; | |
ea506297 | 12536 | |
b3d31392 | 12537 | /* kernel stack layout on 31 bit: It is assumed here that no padding |
ea506297 AK |
12538 | will be added by s390_frame_info because for va_args always an even |
12539 | number of gprs has to be saved r15-r2 = 14 regs. */ | |
9602b6a1 AK |
12540 | sav_ofs = 2 * UNITS_PER_LONG; |
12541 | sav_scale = UNITS_PER_LONG; | |
12542 | size = UNITS_PER_LONG; | |
29a79fcf | 12543 | max_reg = GP_ARG_NUM_REG - n_reg; |
085261c8 AK |
12544 | left_align_p = false; |
12545 | } | |
12546 | else if (s390_function_arg_vector (TYPE_MODE (type), type)) | |
12547 | { | |
12548 | if (TARGET_DEBUG_ARG) | |
12549 | { | |
12550 | fprintf (stderr, "va_arg: vector type"); | |
12551 | debug_tree (type); | |
12552 | } | |
12553 | ||
12554 | indirect_p = 0; | |
12555 | reg = NULL_TREE; | |
12556 | n_reg = 0; | |
12557 | sav_ofs = 0; | |
12558 | sav_scale = 8; | |
12559 | max_reg = 0; | |
12560 | left_align_p = true; | |
9db1d521 | 12561 | } |
82b1c974 | 12562 | else if (s390_function_arg_float (TYPE_MODE (type), type)) |
9db1d521 HP |
12563 | { |
12564 | if (TARGET_DEBUG_ARG) | |
12565 | { | |
12566 | fprintf (stderr, "va_arg: float type"); | |
12567 | debug_tree (type); | |
12568 | } | |
12569 | ||
12570 | /* FP args go in FP registers, if present. */ | |
12571 | indirect_p = 0; | |
12572 | reg = fpr; | |
12573 | n_reg = 1; | |
9602b6a1 | 12574 | sav_ofs = 16 * UNITS_PER_LONG; |
9db1d521 | 12575 | sav_scale = 8; |
29a79fcf | 12576 | max_reg = FP_ARG_NUM_REG - n_reg; |
085261c8 | 12577 | left_align_p = false; |
9db1d521 HP |
12578 | } |
12579 | else | |
12580 | { | |
12581 | if (TARGET_DEBUG_ARG) | |
12582 | { | |
12583 | fprintf (stderr, "va_arg: other type"); | |
12584 | debug_tree (type); | |
12585 | } | |
12586 | ||
12587 | /* Otherwise into GP registers. */ | |
12588 | indirect_p = 0; | |
12589 | reg = gpr; | |
9602b6a1 | 12590 | n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG; |
ea506297 | 12591 | |
b3d31392 AK |
12592 | /* kernel stack layout on 31 bit: It is assumed here that no padding |
12593 | will be added by s390_frame_info because for va_args always an even | |
12594 | number of gprs has to be saved r15-r2 = 14 regs. */ | |
9602b6a1 | 12595 | sav_ofs = 2 * UNITS_PER_LONG; |
c7453384 | 12596 | |
9602b6a1 AK |
12597 | if (size < UNITS_PER_LONG) |
12598 | sav_ofs += UNITS_PER_LONG - size; | |
9db1d521 | 12599 | |
9602b6a1 | 12600 | sav_scale = UNITS_PER_LONG; |
29a79fcf | 12601 | max_reg = GP_ARG_NUM_REG - n_reg; |
085261c8 | 12602 | left_align_p = false; |
9db1d521 HP |
12603 | } |
12604 | ||
12605 | /* Pull the value out of the saved registers ... */ | |
12606 | ||
085261c8 AK |
12607 | if (reg != NULL_TREE) |
12608 | { | |
12609 | /* | |
12610 | if (reg > ((typeof (reg))max_reg)) | |
12611 | goto lab_false; | |
9db1d521 | 12612 | |
085261c8 | 12613 | addr = sav + sav_ofs + reg * save_scale; |
9db1d521 | 12614 | |
085261c8 | 12615 | goto lab_over; |
9db1d521 | 12616 | |
085261c8 AK |
12617 | lab_false: |
12618 | */ | |
12619 | ||
12620 | lab_false = create_artificial_label (UNKNOWN_LOCATION); | |
12621 | lab_over = create_artificial_label (UNKNOWN_LOCATION); | |
12622 | ||
12623 | t = fold_convert (TREE_TYPE (reg), size_int (max_reg)); | |
12624 | t = build2 (GT_EXPR, boolean_type_node, reg, t); | |
12625 | u = build1 (GOTO_EXPR, void_type_node, lab_false); | |
12626 | t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE); | |
12627 | gimplify_and_add (t, pre_p); | |
9db1d521 | 12628 | |
085261c8 AK |
12629 | t = fold_build_pointer_plus_hwi (sav, sav_ofs); |
12630 | u = build2 (MULT_EXPR, TREE_TYPE (reg), reg, | |
12631 | fold_convert (TREE_TYPE (reg), size_int (sav_scale))); | |
12632 | t = fold_build_pointer_plus (t, u); | |
9db1d521 | 12633 | |
085261c8 | 12634 | gimplify_assign (addr, t, pre_p); |
9db1d521 | 12635 | |
085261c8 AK |
12636 | gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over)); |
12637 | ||
12638 | gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false)); | |
12639 | } | |
9db1d521 HP |
12640 | |
12641 | /* ... Otherwise out of the overflow area. */ | |
12642 | ||
ab96de7e | 12643 | t = ovf; |
085261c8 | 12644 | if (size < UNITS_PER_LONG && !left_align_p) |
5d49b6a7 | 12645 | t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG - size); |
ab96de7e AS |
12646 | |
12647 | gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue); | |
12648 | ||
726a989a | 12649 | gimplify_assign (addr, t, pre_p); |
ab96de7e | 12650 | |
085261c8 AK |
12651 | if (size < UNITS_PER_LONG && left_align_p) |
12652 | t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG); | |
12653 | else | |
12654 | t = fold_build_pointer_plus_hwi (t, size); | |
12655 | ||
726a989a | 12656 | gimplify_assign (ovf, t, pre_p); |
ab96de7e | 12657 | |
085261c8 AK |
12658 | if (reg != NULL_TREE) |
12659 | gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over)); | |
ab96de7e AS |
12660 | |
12661 | ||
12662 | /* Increment register save count. */ | |
12663 | ||
085261c8 AK |
12664 | if (n_reg > 0) |
12665 | { | |
12666 | u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg, | |
12667 | fold_convert (TREE_TYPE (reg), size_int (n_reg))); | |
12668 | gimplify_and_add (u, pre_p); | |
12669 | } | |
ab96de7e AS |
12670 | |
12671 | if (indirect_p) | |
12672 | { | |
5b21f0f3 RG |
12673 | t = build_pointer_type_for_mode (build_pointer_type (type), |
12674 | ptr_mode, true); | |
ab96de7e AS |
12675 | addr = fold_convert (t, addr); |
12676 | addr = build_va_arg_indirect_ref (addr); | |
12677 | } | |
12678 | else | |
12679 | { | |
5b21f0f3 | 12680 | t = build_pointer_type_for_mode (type, ptr_mode, true); |
ab96de7e AS |
12681 | addr = fold_convert (t, addr); |
12682 | } | |
12683 | ||
12684 | return build_va_arg_indirect_ref (addr); | |
12685 | } | |
12686 | ||
5a3fe9b6 AK |
12687 | /* Emit rtl for the tbegin or tbegin_retry (RETRY != NULL_RTX) |
12688 | expanders. | |
12689 | DEST - Register location where CC will be stored. | |
12690 | TDB - Pointer to a 256 byte area where to store the transaction. | |
12691 | diagnostic block. NULL if TDB is not needed. | |
12692 | RETRY - Retry count value. If non-NULL a retry loop for CC2 | |
12693 | is emitted | |
12694 | CLOBBER_FPRS_P - If true clobbers for all FPRs are emitted as part | |
12695 | of the tbegin instruction pattern. */ | |
12696 | ||
12697 | void | |
12698 | s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p) | |
12699 | { | |
2561451d | 12700 | rtx retry_plus_two = gen_reg_rtx (SImode); |
5a3fe9b6 | 12701 | rtx retry_reg = gen_reg_rtx (SImode); |
19f8b229 | 12702 | rtx_code_label *retry_label = NULL; |
5a3fe9b6 AK |
12703 | |
12704 | if (retry != NULL_RTX) | |
12705 | { | |
12706 | emit_move_insn (retry_reg, retry); | |
2561451d AK |
12707 | emit_insn (gen_addsi3 (retry_plus_two, retry_reg, const2_rtx)); |
12708 | emit_insn (gen_addsi3 (retry_reg, retry_reg, const1_rtx)); | |
5a3fe9b6 AK |
12709 | retry_label = gen_label_rtx (); |
12710 | emit_label (retry_label); | |
12711 | } | |
12712 | ||
12713 | if (clobber_fprs_p) | |
c914ac45 AK |
12714 | { |
12715 | if (TARGET_VX) | |
12716 | emit_insn (gen_tbegin_1_z13 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), | |
12717 | tdb)); | |
12718 | else | |
12719 | emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), | |
12720 | tdb)); | |
12721 | } | |
5a3fe9b6 | 12722 | else |
2561451d AK |
12723 | emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), |
12724 | tdb)); | |
5a3fe9b6 | 12725 | |
2561451d AK |
12726 | emit_move_insn (dest, gen_rtx_UNSPEC (SImode, |
12727 | gen_rtvec (1, gen_rtx_REG (CCRAWmode, | |
12728 | CC_REGNUM)), | |
12729 | UNSPEC_CC_TO_INT)); | |
5a3fe9b6 AK |
12730 | if (retry != NULL_RTX) |
12731 | { | |
86464cbd AK |
12732 | const int CC0 = 1 << 3; |
12733 | const int CC1 = 1 << 2; | |
12734 | const int CC3 = 1 << 0; | |
12735 | rtx jump; | |
5a3fe9b6 | 12736 | rtx count = gen_reg_rtx (SImode); |
775c43d3 | 12737 | rtx_code_label *leave_label = gen_label_rtx (); |
86464cbd AK |
12738 | |
12739 | /* Exit for success and permanent failures. */ | |
5a3fe9b6 AK |
12740 | jump = s390_emit_jump (leave_label, |
12741 | gen_rtx_EQ (VOIDmode, | |
12742 | gen_rtx_REG (CCRAWmode, CC_REGNUM), | |
86464cbd AK |
12743 | gen_rtx_CONST_INT (VOIDmode, CC0 | CC1 | CC3))); |
12744 | LABEL_NUSES (leave_label) = 1; | |
5a3fe9b6 AK |
12745 | |
12746 | /* CC2 - transient failure. Perform retry with ppa. */ | |
2561451d | 12747 | emit_move_insn (count, retry_plus_two); |
5a3fe9b6 AK |
12748 | emit_insn (gen_subsi3 (count, count, retry_reg)); |
12749 | emit_insn (gen_tx_assist (count)); | |
12750 | jump = emit_jump_insn (gen_doloop_si64 (retry_label, | |
12751 | retry_reg, | |
12752 | retry_reg)); | |
12753 | JUMP_LABEL (jump) = retry_label; | |
12754 | LABEL_NUSES (retry_label) = 1; | |
86464cbd | 12755 | emit_label (leave_label); |
5a3fe9b6 | 12756 | } |
5a3fe9b6 AK |
12757 | } |
12758 | ||
5a3fe9b6 | 12759 | |
9b80b7bc AK |
12760 | /* Return the decl for the target specific builtin with the function |
12761 | code FCODE. */ | |
12762 | ||
12763 | static tree | |
12764 | s390_builtin_decl (unsigned fcode, bool initialized_p ATTRIBUTE_UNUSED) | |
12765 | { | |
12766 | if (fcode >= S390_BUILTIN_MAX) | |
12767 | return error_mark_node; | |
12768 | ||
12769 | return s390_builtin_decls[fcode]; | |
12770 | } | |
12771 | ||
d56a43a0 AK |
12772 | /* We call mcount before the function prologue. So a profiled leaf |
12773 | function should stay a leaf function. */ | |
12774 | ||
12775 | static bool | |
12776 | s390_keep_leaf_when_profiled () | |
12777 | { | |
12778 | return true; | |
12779 | } | |
5a3fe9b6 | 12780 | |
ab96de7e AS |
12781 | /* Output assembly code for the trampoline template to |
12782 | stdio stream FILE. | |
12783 | ||
12784 | On S/390, we use gpr 1 internally in the trampoline code; | |
12785 | gpr 0 is used to hold the static chain. */ | |
12786 | ||
b81ecf6f RH |
12787 | static void |
12788 | s390_asm_trampoline_template (FILE *file) | |
ab96de7e AS |
12789 | { |
12790 | rtx op[2]; | |
12791 | op[0] = gen_rtx_REG (Pmode, 0); | |
12792 | op[1] = gen_rtx_REG (Pmode, 1); | |
12793 | ||
12794 | if (TARGET_64BIT) | |
12795 | { | |
cab78b15 AK |
12796 | output_asm_insn ("basr\t%1,0", op); /* 2 byte */ |
12797 | output_asm_insn ("lmg\t%0,%1,14(%1)", op); /* 6 byte */ | |
12798 | output_asm_insn ("br\t%1", op); /* 2 byte */ | |
ab96de7e AS |
12799 | ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10)); |
12800 | } | |
12801 | else | |
12802 | { | |
cab78b15 AK |
12803 | output_asm_insn ("basr\t%1,0", op); /* 2 byte */ |
12804 | output_asm_insn ("lm\t%0,%1,6(%1)", op); /* 4 byte */ | |
12805 | output_asm_insn ("br\t%1", op); /* 2 byte */ | |
ab96de7e AS |
12806 | ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8)); |
12807 | } | |
12808 | } | |
12809 | ||
12810 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
12811 | FNADDR is an RTX for the address of the function's pure code. | |
12812 | CXT is an RTX for the static chain value for the function. */ | |
12813 | ||
b81ecf6f RH |
12814 | static void |
12815 | s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt) | |
ab96de7e | 12816 | { |
b81ecf6f RH |
12817 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); |
12818 | rtx mem; | |
3a892e44 | 12819 | |
b81ecf6f | 12820 | emit_block_move (m_tramp, assemble_trampoline_template (), |
cab78b15 | 12821 | GEN_INT (2 * UNITS_PER_LONG), BLOCK_OP_NORMAL); |
b81ecf6f | 12822 | |
cab78b15 | 12823 | mem = adjust_address (m_tramp, Pmode, 2 * UNITS_PER_LONG); |
b81ecf6f | 12824 | emit_move_insn (mem, cxt); |
cab78b15 | 12825 | mem = adjust_address (m_tramp, Pmode, 3 * UNITS_PER_LONG); |
b81ecf6f | 12826 | emit_move_insn (mem, fnaddr); |
ab96de7e AS |
12827 | } |
12828 | ||
ab96de7e AS |
12829 | /* Output assembler code to FILE to increment profiler label # LABELNO |
12830 | for profiling a function entry. */ | |
12831 | ||
12832 | void | |
12833 | s390_function_profiler (FILE *file, int labelno) | |
12834 | { | |
12835 | rtx op[7]; | |
12836 | ||
12837 | char label[128]; | |
12838 | ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno); | |
12839 | ||
12840 | fprintf (file, "# function profiler \n"); | |
12841 | ||
12842 | op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM); | |
12843 | op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
0a81f074 | 12844 | op[1] = gen_rtx_MEM (Pmode, plus_constant (Pmode, op[1], UNITS_PER_LONG)); |
ab96de7e AS |
12845 | |
12846 | op[2] = gen_rtx_REG (Pmode, 1); | |
12847 | op[3] = gen_rtx_SYMBOL_REF (Pmode, label); | |
12848 | SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL; | |
12849 | ||
12850 | op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount"); | |
12851 | if (flag_pic) | |
12852 | { | |
12853 | op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT); | |
12854 | op[4] = gen_rtx_CONST (Pmode, op[4]); | |
12855 | } | |
12856 | ||
12857 | if (TARGET_64BIT) | |
12858 | { | |
12859 | output_asm_insn ("stg\t%0,%1", op); | |
12860 | output_asm_insn ("larl\t%2,%3", op); | |
12861 | output_asm_insn ("brasl\t%0,%4", op); | |
12862 | output_asm_insn ("lg\t%0,%1", op); | |
12863 | } | |
7e2507a5 MK |
12864 | else if (TARGET_CPU_ZARCH) |
12865 | { | |
12866 | output_asm_insn ("st\t%0,%1", op); | |
12867 | output_asm_insn ("larl\t%2,%3", op); | |
12868 | output_asm_insn ("brasl\t%0,%4", op); | |
12869 | output_asm_insn ("l\t%0,%1", op); | |
12870 | } | |
ab96de7e AS |
12871 | else if (!flag_pic) |
12872 | { | |
12873 | op[6] = gen_label_rtx (); | |
12874 | ||
12875 | output_asm_insn ("st\t%0,%1", op); | |
12876 | output_asm_insn ("bras\t%2,%l6", op); | |
12877 | output_asm_insn (".long\t%4", op); | |
12878 | output_asm_insn (".long\t%3", op); | |
12879 | targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6])); | |
12880 | output_asm_insn ("l\t%0,0(%2)", op); | |
12881 | output_asm_insn ("l\t%2,4(%2)", op); | |
12882 | output_asm_insn ("basr\t%0,%0", op); | |
12883 | output_asm_insn ("l\t%0,%1", op); | |
12884 | } | |
12885 | else | |
12886 | { | |
12887 | op[5] = gen_label_rtx (); | |
12888 | op[6] = gen_label_rtx (); | |
12889 | ||
12890 | output_asm_insn ("st\t%0,%1", op); | |
12891 | output_asm_insn ("bras\t%2,%l6", op); | |
12892 | targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5])); | |
12893 | output_asm_insn (".long\t%4-%l5", op); | |
12894 | output_asm_insn (".long\t%3-%l5", op); | |
12895 | targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6])); | |
12896 | output_asm_insn ("lr\t%0,%2", op); | |
12897 | output_asm_insn ("a\t%0,0(%2)", op); | |
12898 | output_asm_insn ("a\t%2,4(%2)", op); | |
12899 | output_asm_insn ("basr\t%0,%0", op); | |
12900 | output_asm_insn ("l\t%0,%1", op); | |
12901 | } | |
12902 | } | |
12903 | ||
12904 | /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF | |
12905 | into its SYMBOL_REF_FLAGS. */ | |
12906 | ||
12907 | static void | |
12908 | s390_encode_section_info (tree decl, rtx rtl, int first) | |
12909 | { | |
12910 | default_encode_section_info (decl, rtl, first); | |
12911 | ||
963fc8d0 AK |
12912 | if (TREE_CODE (decl) == VAR_DECL) |
12913 | { | |
e63d44c2 RD |
12914 | /* Store the alignment to be able to check if we can use |
12915 | a larl/load-relative instruction. We only handle the cases | |
54158a1a | 12916 | that can go wrong (i.e. no FUNC_DECLs). */ |
1397e163 | 12917 | if (DECL_ALIGN (decl) == 0 || DECL_ALIGN (decl) % 16) |
e63d44c2 | 12918 | SYMBOL_FLAG_SET_NOTALIGN2 (XEXP (rtl, 0)); |
54158a1a AK |
12919 | else if (DECL_ALIGN (decl) % 32) |
12920 | SYMBOL_FLAG_SET_NOTALIGN4 (XEXP (rtl, 0)); | |
12921 | else if (DECL_ALIGN (decl) % 64) | |
12922 | SYMBOL_FLAG_SET_NOTALIGN8 (XEXP (rtl, 0)); | |
963fc8d0 AK |
12923 | } |
12924 | ||
12925 | /* Literal pool references don't have a decl so they are handled | |
12926 | differently here. We rely on the information in the MEM_ALIGN | |
e63d44c2 | 12927 | entry to decide upon the alignment. */ |
963fc8d0 AK |
12928 | if (MEM_P (rtl) |
12929 | && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF | |
54158a1a | 12930 | && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))) |
e63d44c2 | 12931 | { |
1397e163 | 12932 | if (MEM_ALIGN (rtl) == 0 || MEM_ALIGN (rtl) % 16) |
e63d44c2 | 12933 | SYMBOL_FLAG_SET_NOTALIGN2 (XEXP (rtl, 0)); |
54158a1a AK |
12934 | else if (MEM_ALIGN (rtl) % 32) |
12935 | SYMBOL_FLAG_SET_NOTALIGN4 (XEXP (rtl, 0)); | |
12936 | else if (MEM_ALIGN (rtl) % 64) | |
12937 | SYMBOL_FLAG_SET_NOTALIGN8 (XEXP (rtl, 0)); | |
e63d44c2 | 12938 | } |
ab96de7e AS |
12939 | } |
12940 | ||
12941 | /* Output thunk to FILE that implements a C++ virtual function call (with | |
12942 | multiple inheritance) to FUNCTION. The thunk adjusts the this pointer | |
12943 | by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment | |
12944 | stored at VCALL_OFFSET in the vtable whose address is located at offset 0 | |
12945 | relative to the resulting this pointer. */ | |
12946 | ||
12947 | static void | |
12948 | s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, | |
12949 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
12950 | tree function) | |
12951 | { | |
12952 | rtx op[10]; | |
12953 | int nonlocal = 0; | |
12954 | ||
81ef7e24 JJ |
12955 | /* Make sure unwind info is emitted for the thunk if needed. */ |
12956 | final_start_function (emit_barrier (), file, 1); | |
12957 | ||
ab96de7e AS |
12958 | /* Operand 0 is the target function. */ |
12959 | op[0] = XEXP (DECL_RTL (function), 0); | |
12960 | if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0])) | |
12961 | { | |
12962 | nonlocal = 1; | |
12963 | op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]), | |
12964 | TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT); | |
12965 | op[0] = gen_rtx_CONST (Pmode, op[0]); | |
12966 | } | |
12967 | ||
12968 | /* Operand 1 is the 'this' pointer. */ | |
12969 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) | |
12970 | op[1] = gen_rtx_REG (Pmode, 3); | |
12971 | else | |
12972 | op[1] = gen_rtx_REG (Pmode, 2); | |
12973 | ||
12974 | /* Operand 2 is the delta. */ | |
12975 | op[2] = GEN_INT (delta); | |
12976 | ||
12977 | /* Operand 3 is the vcall_offset. */ | |
12978 | op[3] = GEN_INT (vcall_offset); | |
12979 | ||
12980 | /* Operand 4 is the temporary register. */ | |
12981 | op[4] = gen_rtx_REG (Pmode, 1); | |
12982 | ||
12983 | /* Operands 5 to 8 can be used as labels. */ | |
12984 | op[5] = NULL_RTX; | |
12985 | op[6] = NULL_RTX; | |
12986 | op[7] = NULL_RTX; | |
12987 | op[8] = NULL_RTX; | |
12988 | ||
12989 | /* Operand 9 can be used for temporary register. */ | |
12990 | op[9] = NULL_RTX; | |
12991 | ||
12992 | /* Generate code. */ | |
12993 | if (TARGET_64BIT) | |
12994 | { | |
12995 | /* Setup literal pool pointer if required. */ | |
12996 | if ((!DISP_IN_RANGE (delta) | |
ec24698e UW |
12997 | && !CONST_OK_FOR_K (delta) |
12998 | && !CONST_OK_FOR_Os (delta)) | |
ab96de7e | 12999 | || (!DISP_IN_RANGE (vcall_offset) |
ec24698e UW |
13000 | && !CONST_OK_FOR_K (vcall_offset) |
13001 | && !CONST_OK_FOR_Os (vcall_offset))) | |
ab96de7e AS |
13002 | { |
13003 | op[5] = gen_label_rtx (); | |
13004 | output_asm_insn ("larl\t%4,%5", op); | |
13005 | } | |
13006 | ||
13007 | /* Add DELTA to this pointer. */ | |
13008 | if (delta) | |
13009 | { | |
b5c67a49 | 13010 | if (CONST_OK_FOR_J (delta)) |
ab96de7e AS |
13011 | output_asm_insn ("la\t%1,%2(%1)", op); |
13012 | else if (DISP_IN_RANGE (delta)) | |
13013 | output_asm_insn ("lay\t%1,%2(%1)", op); | |
b5c67a49 | 13014 | else if (CONST_OK_FOR_K (delta)) |
ab96de7e | 13015 | output_asm_insn ("aghi\t%1,%2", op); |
ec24698e UW |
13016 | else if (CONST_OK_FOR_Os (delta)) |
13017 | output_asm_insn ("agfi\t%1,%2", op); | |
ab96de7e AS |
13018 | else |
13019 | { | |
13020 | op[6] = gen_label_rtx (); | |
13021 | output_asm_insn ("agf\t%1,%6-%5(%4)", op); | |
13022 | } | |
13023 | } | |
13024 | ||
13025 | /* Perform vcall adjustment. */ | |
13026 | if (vcall_offset) | |
13027 | { | |
13028 | if (DISP_IN_RANGE (vcall_offset)) | |
13029 | { | |
13030 | output_asm_insn ("lg\t%4,0(%1)", op); | |
13031 | output_asm_insn ("ag\t%1,%3(%4)", op); | |
13032 | } | |
b5c67a49 | 13033 | else if (CONST_OK_FOR_K (vcall_offset)) |
ab96de7e AS |
13034 | { |
13035 | output_asm_insn ("lghi\t%4,%3", op); | |
13036 | output_asm_insn ("ag\t%4,0(%1)", op); | |
13037 | output_asm_insn ("ag\t%1,0(%4)", op); | |
13038 | } | |
ec24698e UW |
13039 | else if (CONST_OK_FOR_Os (vcall_offset)) |
13040 | { | |
13041 | output_asm_insn ("lgfi\t%4,%3", op); | |
13042 | output_asm_insn ("ag\t%4,0(%1)", op); | |
13043 | output_asm_insn ("ag\t%1,0(%4)", op); | |
13044 | } | |
ab96de7e AS |
13045 | else |
13046 | { | |
13047 | op[7] = gen_label_rtx (); | |
13048 | output_asm_insn ("llgf\t%4,%7-%5(%4)", op); | |
13049 | output_asm_insn ("ag\t%4,0(%1)", op); | |
13050 | output_asm_insn ("ag\t%1,0(%4)", op); | |
13051 | } | |
13052 | } | |
13053 | ||
13054 | /* Jump to target. */ | |
13055 | output_asm_insn ("jg\t%0", op); | |
13056 | ||
13057 | /* Output literal pool if required. */ | |
13058 | if (op[5]) | |
13059 | { | |
13060 | output_asm_insn (".align\t4", op); | |
13061 | targetm.asm_out.internal_label (file, "L", | |
13062 | CODE_LABEL_NUMBER (op[5])); | |
13063 | } | |
13064 | if (op[6]) | |
13065 | { | |
13066 | targetm.asm_out.internal_label (file, "L", | |
13067 | CODE_LABEL_NUMBER (op[6])); | |
13068 | output_asm_insn (".long\t%2", op); | |
13069 | } | |
13070 | if (op[7]) | |
13071 | { | |
13072 | targetm.asm_out.internal_label (file, "L", | |
13073 | CODE_LABEL_NUMBER (op[7])); | |
13074 | output_asm_insn (".long\t%3", op); | |
13075 | } | |
13076 | } | |
13077 | else | |
13078 | { | |
13079 | /* Setup base pointer if required. */ | |
13080 | if (!vcall_offset | |
13081 | || (!DISP_IN_RANGE (delta) | |
ec24698e UW |
13082 | && !CONST_OK_FOR_K (delta) |
13083 | && !CONST_OK_FOR_Os (delta)) | |
ab96de7e | 13084 | || (!DISP_IN_RANGE (delta) |
ec24698e UW |
13085 | && !CONST_OK_FOR_K (vcall_offset) |
13086 | && !CONST_OK_FOR_Os (vcall_offset))) | |
ab96de7e AS |
13087 | { |
13088 | op[5] = gen_label_rtx (); | |
13089 | output_asm_insn ("basr\t%4,0", op); | |
13090 | targetm.asm_out.internal_label (file, "L", | |
13091 | CODE_LABEL_NUMBER (op[5])); | |
13092 | } | |
13093 | ||
13094 | /* Add DELTA to this pointer. */ | |
13095 | if (delta) | |
13096 | { | |
b5c67a49 | 13097 | if (CONST_OK_FOR_J (delta)) |
ab96de7e AS |
13098 | output_asm_insn ("la\t%1,%2(%1)", op); |
13099 | else if (DISP_IN_RANGE (delta)) | |
13100 | output_asm_insn ("lay\t%1,%2(%1)", op); | |
b5c67a49 | 13101 | else if (CONST_OK_FOR_K (delta)) |
ab96de7e | 13102 | output_asm_insn ("ahi\t%1,%2", op); |
ec24698e UW |
13103 | else if (CONST_OK_FOR_Os (delta)) |
13104 | output_asm_insn ("afi\t%1,%2", op); | |
ab96de7e AS |
13105 | else |
13106 | { | |
13107 | op[6] = gen_label_rtx (); | |
13108 | output_asm_insn ("a\t%1,%6-%5(%4)", op); | |
13109 | } | |
13110 | } | |
13111 | ||
13112 | /* Perform vcall adjustment. */ | |
13113 | if (vcall_offset) | |
13114 | { | |
b5c67a49 | 13115 | if (CONST_OK_FOR_J (vcall_offset)) |
ab96de7e | 13116 | { |
c4d50129 | 13117 | output_asm_insn ("l\t%4,0(%1)", op); |
ab96de7e AS |
13118 | output_asm_insn ("a\t%1,%3(%4)", op); |
13119 | } | |
13120 | else if (DISP_IN_RANGE (vcall_offset)) | |
13121 | { | |
c4d50129 | 13122 | output_asm_insn ("l\t%4,0(%1)", op); |
ab96de7e AS |
13123 | output_asm_insn ("ay\t%1,%3(%4)", op); |
13124 | } | |
b5c67a49 | 13125 | else if (CONST_OK_FOR_K (vcall_offset)) |
ab96de7e AS |
13126 | { |
13127 | output_asm_insn ("lhi\t%4,%3", op); | |
13128 | output_asm_insn ("a\t%4,0(%1)", op); | |
13129 | output_asm_insn ("a\t%1,0(%4)", op); | |
13130 | } | |
ec24698e UW |
13131 | else if (CONST_OK_FOR_Os (vcall_offset)) |
13132 | { | |
13133 | output_asm_insn ("iilf\t%4,%3", op); | |
13134 | output_asm_insn ("a\t%4,0(%1)", op); | |
13135 | output_asm_insn ("a\t%1,0(%4)", op); | |
13136 | } | |
ab96de7e AS |
13137 | else |
13138 | { | |
13139 | op[7] = gen_label_rtx (); | |
13140 | output_asm_insn ("l\t%4,%7-%5(%4)", op); | |
13141 | output_asm_insn ("a\t%4,0(%1)", op); | |
13142 | output_asm_insn ("a\t%1,0(%4)", op); | |
13143 | } | |
9db1d521 | 13144 | |
ab96de7e AS |
13145 | /* We had to clobber the base pointer register. |
13146 | Re-setup the base pointer (with a different base). */ | |
13147 | op[5] = gen_label_rtx (); | |
13148 | output_asm_insn ("basr\t%4,0", op); | |
13149 | targetm.asm_out.internal_label (file, "L", | |
13150 | CODE_LABEL_NUMBER (op[5])); | |
13151 | } | |
9db1d521 | 13152 | |
ab96de7e AS |
13153 | /* Jump to target. */ |
13154 | op[8] = gen_label_rtx (); | |
9db1d521 | 13155 | |
ab96de7e AS |
13156 | if (!flag_pic) |
13157 | output_asm_insn ("l\t%4,%8-%5(%4)", op); | |
13158 | else if (!nonlocal) | |
13159 | output_asm_insn ("a\t%4,%8-%5(%4)", op); | |
13160 | /* We cannot call through .plt, since .plt requires %r12 loaded. */ | |
13161 | else if (flag_pic == 1) | |
13162 | { | |
13163 | output_asm_insn ("a\t%4,%8-%5(%4)", op); | |
13164 | output_asm_insn ("l\t%4,%0(%4)", op); | |
13165 | } | |
13166 | else if (flag_pic == 2) | |
13167 | { | |
13168 | op[9] = gen_rtx_REG (Pmode, 0); | |
13169 | output_asm_insn ("l\t%9,%8-4-%5(%4)", op); | |
13170 | output_asm_insn ("a\t%4,%8-%5(%4)", op); | |
13171 | output_asm_insn ("ar\t%4,%9", op); | |
13172 | output_asm_insn ("l\t%4,0(%4)", op); | |
13173 | } | |
9db1d521 | 13174 | |
ab96de7e | 13175 | output_asm_insn ("br\t%4", op); |
9db1d521 | 13176 | |
ab96de7e AS |
13177 | /* Output literal pool. */ |
13178 | output_asm_insn (".align\t4", op); | |
9db1d521 | 13179 | |
ab96de7e AS |
13180 | if (nonlocal && flag_pic == 2) |
13181 | output_asm_insn (".long\t%0", op); | |
13182 | if (nonlocal) | |
13183 | { | |
13184 | op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
13185 | SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL; | |
13186 | } | |
63694b5e | 13187 | |
ab96de7e AS |
13188 | targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8])); |
13189 | if (!flag_pic) | |
13190 | output_asm_insn (".long\t%0", op); | |
13191 | else | |
13192 | output_asm_insn (".long\t%0-%5", op); | |
9db1d521 | 13193 | |
ab96de7e AS |
13194 | if (op[6]) |
13195 | { | |
13196 | targetm.asm_out.internal_label (file, "L", | |
13197 | CODE_LABEL_NUMBER (op[6])); | |
13198 | output_asm_insn (".long\t%2", op); | |
13199 | } | |
13200 | if (op[7]) | |
13201 | { | |
13202 | targetm.asm_out.internal_label (file, "L", | |
13203 | CODE_LABEL_NUMBER (op[7])); | |
13204 | output_asm_insn (".long\t%3", op); | |
13205 | } | |
9db1d521 | 13206 | } |
81ef7e24 | 13207 | final_end_function (); |
9db1d521 HP |
13208 | } |
13209 | ||
ab96de7e | 13210 | static bool |
095a2d76 | 13211 | s390_valid_pointer_mode (scalar_int_mode mode) |
ab96de7e AS |
13212 | { |
13213 | return (mode == SImode || (TARGET_64BIT && mode == DImode)); | |
13214 | } | |
994fe660 | 13215 | |
9a6f71b4 | 13216 | /* Checks whether the given CALL_EXPR would use a caller |
ab96de7e AS |
13217 | saved register. This is used to decide whether sibling call |
13218 | optimization could be performed on the respective function | |
13219 | call. */ | |
fd3cd001 | 13220 | |
ab96de7e | 13221 | static bool |
9a6f71b4 | 13222 | s390_call_saved_register_used (tree call_expr) |
fd3cd001 | 13223 | { |
d5cc9181 JR |
13224 | CUMULATIVE_ARGS cum_v; |
13225 | cumulative_args_t cum; | |
ab96de7e | 13226 | tree parameter; |
ef4bddc2 | 13227 | machine_mode mode; |
ab96de7e AS |
13228 | tree type; |
13229 | rtx parm_rtx; | |
9a6f71b4 | 13230 | int reg, i; |
fd3cd001 | 13231 | |
d5cc9181 JR |
13232 | INIT_CUMULATIVE_ARGS (cum_v, NULL, NULL, 0, 0); |
13233 | cum = pack_cumulative_args (&cum_v); | |
fd3cd001 | 13234 | |
9a6f71b4 | 13235 | for (i = 0; i < call_expr_nargs (call_expr); i++) |
ab96de7e | 13236 | { |
9a6f71b4 | 13237 | parameter = CALL_EXPR_ARG (call_expr, i); |
8d933e31 | 13238 | gcc_assert (parameter); |
fd3cd001 | 13239 | |
ab96de7e AS |
13240 | /* For an undeclared variable passed as parameter we will get |
13241 | an ERROR_MARK node here. */ | |
13242 | if (TREE_CODE (parameter) == ERROR_MARK) | |
13243 | return true; | |
fd3cd001 | 13244 | |
8d933e31 AS |
13245 | type = TREE_TYPE (parameter); |
13246 | gcc_assert (type); | |
fd3cd001 | 13247 | |
8d933e31 AS |
13248 | mode = TYPE_MODE (type); |
13249 | gcc_assert (mode); | |
fd3cd001 | 13250 | |
085261c8 AK |
13251 | /* We assume that in the target function all parameters are |
13252 | named. This only has an impact on vector argument register | |
13253 | usage none of which is call-saved. */ | |
d5cc9181 | 13254 | if (pass_by_reference (&cum_v, mode, type, true)) |
ab96de7e AS |
13255 | { |
13256 | mode = Pmode; | |
13257 | type = build_pointer_type (type); | |
13258 | } | |
fd3cd001 | 13259 | |
085261c8 | 13260 | parm_rtx = s390_function_arg (cum, mode, type, true); |
fd3cd001 | 13261 | |
085261c8 | 13262 | s390_function_arg_advance (cum, mode, type, true); |
fd3cd001 | 13263 | |
9602b6a1 AK |
13264 | if (!parm_rtx) |
13265 | continue; | |
13266 | ||
13267 | if (REG_P (parm_rtx)) | |
13268 | { | |
462a99aa | 13269 | for (reg = 0; reg < REG_NREGS (parm_rtx); reg++) |
9602b6a1 AK |
13270 | if (!call_used_regs[reg + REGNO (parm_rtx)]) |
13271 | return true; | |
13272 | } | |
13273 | ||
13274 | if (GET_CODE (parm_rtx) == PARALLEL) | |
ab96de7e | 13275 | { |
9602b6a1 | 13276 | int i; |
e8de8fea | 13277 | |
9602b6a1 AK |
13278 | for (i = 0; i < XVECLEN (parm_rtx, 0); i++) |
13279 | { | |
13280 | rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0); | |
9602b6a1 AK |
13281 | |
13282 | gcc_assert (REG_P (r)); | |
13283 | ||
462a99aa | 13284 | for (reg = 0; reg < REG_NREGS (r); reg++) |
9602b6a1 AK |
13285 | if (!call_used_regs[reg + REGNO (r)]) |
13286 | return true; | |
13287 | } | |
ab96de7e | 13288 | } |
9602b6a1 | 13289 | |
ab96de7e AS |
13290 | } |
13291 | return false; | |
13292 | } | |
fd3cd001 | 13293 | |
ab96de7e AS |
13294 | /* Return true if the given call expression can be |
13295 | turned into a sibling call. | |
13296 | DECL holds the declaration of the function to be called whereas | |
13297 | EXP is the call expression itself. */ | |
fd3cd001 | 13298 | |
ab96de7e AS |
13299 | static bool |
13300 | s390_function_ok_for_sibcall (tree decl, tree exp) | |
13301 | { | |
13302 | /* The TPF epilogue uses register 1. */ | |
13303 | if (TARGET_TPF_PROFILING) | |
13304 | return false; | |
fd3cd001 | 13305 | |
ab96de7e AS |
13306 | /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved) |
13307 | which would have to be restored before the sibcall. */ | |
7691ec4e | 13308 | if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl)) |
ab96de7e | 13309 | return false; |
fd3cd001 | 13310 | |
ab96de7e AS |
13311 | /* Register 6 on s390 is available as an argument register but unfortunately |
13312 | "caller saved". This makes functions needing this register for arguments | |
13313 | not suitable for sibcalls. */ | |
9a6f71b4 | 13314 | return !s390_call_saved_register_used (exp); |
ab96de7e | 13315 | } |
fd3cd001 | 13316 | |
ab96de7e | 13317 | /* Return the fixed registers used for condition codes. */ |
fd3cd001 | 13318 | |
ab96de7e AS |
13319 | static bool |
13320 | s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) | |
13321 | { | |
13322 | *p1 = CC_REGNUM; | |
13323 | *p2 = INVALID_REGNUM; | |
f4aa3848 | 13324 | |
ab96de7e AS |
13325 | return true; |
13326 | } | |
fd3cd001 | 13327 | |
ab96de7e AS |
13328 | /* This function is used by the call expanders of the machine description. |
13329 | It emits the call insn itself together with the necessary operations | |
13330 | to adjust the target address and returns the emitted insn. | |
13331 | ADDR_LOCATION is the target address rtx | |
13332 | TLS_CALL the location of the thread-local symbol | |
13333 | RESULT_REG the register where the result of the call should be stored | |
13334 | RETADDR_REG the register where the return address should be stored | |
13335 | If this parameter is NULL_RTX the call is considered | |
13336 | to be a sibling call. */ | |
fd3cd001 | 13337 | |
775c43d3 | 13338 | rtx_insn * |
ab96de7e AS |
13339 | s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg, |
13340 | rtx retaddr_reg) | |
9db1d521 | 13341 | { |
ab96de7e | 13342 | bool plt_call = false; |
775c43d3 | 13343 | rtx_insn *insn; |
ab96de7e AS |
13344 | rtx call; |
13345 | rtx clobber; | |
13346 | rtvec vec; | |
cadc42db | 13347 | |
ab96de7e AS |
13348 | /* Direct function calls need special treatment. */ |
13349 | if (GET_CODE (addr_location) == SYMBOL_REF) | |
9db1d521 | 13350 | { |
ab96de7e AS |
13351 | /* When calling a global routine in PIC mode, we must |
13352 | replace the symbol itself with the PLT stub. */ | |
13353 | if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location)) | |
13354 | { | |
15288e9a | 13355 | if (TARGET_64BIT || retaddr_reg != NULL_RTX) |
72e2cf16 AK |
13356 | { |
13357 | addr_location = gen_rtx_UNSPEC (Pmode, | |
13358 | gen_rtvec (1, addr_location), | |
13359 | UNSPEC_PLT); | |
13360 | addr_location = gen_rtx_CONST (Pmode, addr_location); | |
13361 | plt_call = true; | |
13362 | } | |
13363 | else | |
13364 | /* For -fpic code the PLT entries might use r12 which is | |
13365 | call-saved. Therefore we cannot do a sibcall when | |
13366 | calling directly using a symbol ref. When reaching | |
13367 | this point we decided (in s390_function_ok_for_sibcall) | |
13368 | to do a sibcall for a function pointer but one of the | |
13369 | optimizers was able to get rid of the function pointer | |
13370 | by propagating the symbol ref into the call. This | |
13371 | optimization is illegal for S/390 so we turn the direct | |
13372 | call into a indirect call again. */ | |
13373 | addr_location = force_reg (Pmode, addr_location); | |
ab96de7e AS |
13374 | } |
13375 | ||
13376 | /* Unless we can use the bras(l) insn, force the | |
13377 | routine address into a register. */ | |
13378 | if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH) | |
13379 | { | |
13380 | if (flag_pic) | |
13381 | addr_location = legitimize_pic_address (addr_location, 0); | |
13382 | else | |
13383 | addr_location = force_reg (Pmode, addr_location); | |
13384 | } | |
9db1d521 | 13385 | } |
ab96de7e AS |
13386 | |
13387 | /* If it is already an indirect call or the code above moved the | |
13388 | SYMBOL_REF to somewhere else make sure the address can be found in | |
13389 | register 1. */ | |
13390 | if (retaddr_reg == NULL_RTX | |
13391 | && GET_CODE (addr_location) != SYMBOL_REF | |
13392 | && !plt_call) | |
9db1d521 | 13393 | { |
ab96de7e AS |
13394 | emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location); |
13395 | addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM); | |
9db1d521 | 13396 | } |
9db1d521 | 13397 | |
ab96de7e AS |
13398 | addr_location = gen_rtx_MEM (QImode, addr_location); |
13399 | call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx); | |
4023fb28 | 13400 | |
ab96de7e | 13401 | if (result_reg != NULL_RTX) |
f7df4a84 | 13402 | call = gen_rtx_SET (result_reg, call); |
4023fb28 | 13403 | |
ab96de7e AS |
13404 | if (retaddr_reg != NULL_RTX) |
13405 | { | |
13406 | clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg); | |
c7453384 | 13407 | |
ab96de7e AS |
13408 | if (tls_call != NULL_RTX) |
13409 | vec = gen_rtvec (3, call, clobber, | |
13410 | gen_rtx_USE (VOIDmode, tls_call)); | |
13411 | else | |
13412 | vec = gen_rtvec (2, call, clobber); | |
4023fb28 | 13413 | |
ab96de7e AS |
13414 | call = gen_rtx_PARALLEL (VOIDmode, vec); |
13415 | } | |
4023fb28 | 13416 | |
ab96de7e | 13417 | insn = emit_call_insn (call); |
4023fb28 | 13418 | |
ab96de7e AS |
13419 | /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */ |
13420 | if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX) | |
13421 | { | |
13422 | /* s390_function_ok_for_sibcall should | |
13423 | have denied sibcalls in this case. */ | |
8d933e31 | 13424 | gcc_assert (retaddr_reg != NULL_RTX); |
68c0ef75 | 13425 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, 12)); |
ab96de7e AS |
13426 | } |
13427 | return insn; | |
13428 | } | |
4023fb28 | 13429 | |
5efd84c5 | 13430 | /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */ |
4023fb28 | 13431 | |
5efd84c5 | 13432 | static void |
ab96de7e AS |
13433 | s390_conditional_register_usage (void) |
13434 | { | |
13435 | int i; | |
4023fb28 | 13436 | |
4023fb28 UW |
13437 | if (flag_pic) |
13438 | { | |
ab96de7e AS |
13439 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; |
13440 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
4023fb28 | 13441 | } |
ab96de7e | 13442 | if (TARGET_CPU_ZARCH) |
4023fb28 | 13443 | { |
7633f08e UW |
13444 | fixed_regs[BASE_REGNUM] = 0; |
13445 | call_used_regs[BASE_REGNUM] = 0; | |
ab96de7e AS |
13446 | fixed_regs[RETURN_REGNUM] = 0; |
13447 | call_used_regs[RETURN_REGNUM] = 0; | |
4023fb28 | 13448 | } |
ab96de7e | 13449 | if (TARGET_64BIT) |
4023fb28 | 13450 | { |
2cf4c39e | 13451 | for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++) |
ab96de7e | 13452 | call_used_regs[i] = call_really_used_regs[i] = 0; |
4023fb28 UW |
13453 | } |
13454 | else | |
13455 | { | |
2cf4c39e AK |
13456 | call_used_regs[FPR4_REGNUM] = call_really_used_regs[FPR4_REGNUM] = 0; |
13457 | call_used_regs[FPR6_REGNUM] = call_really_used_regs[FPR6_REGNUM] = 0; | |
ab96de7e | 13458 | } |
4023fb28 | 13459 | |
ab96de7e AS |
13460 | if (TARGET_SOFT_FLOAT) |
13461 | { | |
2cf4c39e | 13462 | for (i = FPR0_REGNUM; i <= FPR15_REGNUM; i++) |
ab96de7e | 13463 | call_used_regs[i] = fixed_regs[i] = 1; |
4023fb28 | 13464 | } |
085261c8 AK |
13465 | |
13466 | /* Disable v16 - v31 for non-vector target. */ | |
13467 | if (!TARGET_VX) | |
13468 | { | |
13469 | for (i = VR16_REGNUM; i <= VR31_REGNUM; i++) | |
13470 | fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1; | |
13471 | } | |
4023fb28 UW |
13472 | } |
13473 | ||
ab96de7e | 13474 | /* Corresponding function to eh_return expander. */ |
fb49053f | 13475 | |
ab96de7e AS |
13476 | static GTY(()) rtx s390_tpf_eh_return_symbol; |
13477 | void | |
13478 | s390_emit_tpf_eh_return (rtx target) | |
fb49053f | 13479 | { |
775c43d3 DM |
13480 | rtx_insn *insn; |
13481 | rtx reg, orig_ra; | |
e23795ea | 13482 | |
ab96de7e AS |
13483 | if (!s390_tpf_eh_return_symbol) |
13484 | s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return"); | |
13485 | ||
13486 | reg = gen_rtx_REG (Pmode, 2); | |
87cb0c0c | 13487 | orig_ra = gen_rtx_REG (Pmode, 3); |
ab96de7e AS |
13488 | |
13489 | emit_move_insn (reg, target); | |
87cb0c0c | 13490 | emit_move_insn (orig_ra, get_hard_reg_initial_val (Pmode, RETURN_REGNUM)); |
ab96de7e AS |
13491 | insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg, |
13492 | gen_rtx_REG (Pmode, RETURN_REGNUM)); | |
13493 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg); | |
87cb0c0c | 13494 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), orig_ra); |
ab96de7e AS |
13495 | |
13496 | emit_move_insn (EH_RETURN_HANDLER_RTX, reg); | |
fd3cd001 UW |
13497 | } |
13498 | ||
ab96de7e AS |
13499 | /* Rework the prologue/epilogue to avoid saving/restoring |
13500 | registers unnecessarily. */ | |
3062825f | 13501 | |
c590b625 | 13502 | static void |
ab96de7e | 13503 | s390_optimize_prologue (void) |
483ab821 | 13504 | { |
775c43d3 | 13505 | rtx_insn *insn, *new_insn, *next_insn; |
3062825f | 13506 | |
ab96de7e | 13507 | /* Do a final recompute of the frame-related data. */ |
6455a49e | 13508 | s390_optimize_register_info (); |
3062825f | 13509 | |
ab96de7e AS |
13510 | /* If all special registers are in fact used, there's nothing we |
13511 | can do, so no point in walking the insn list. */ | |
3062825f | 13512 | |
f4aa3848 | 13513 | if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM |
ab96de7e | 13514 | && cfun_frame_layout.last_save_gpr >= BASE_REGNUM |
f4aa3848 AK |
13515 | && (TARGET_CPU_ZARCH |
13516 | || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM | |
ab96de7e AS |
13517 | && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM))) |
13518 | return; | |
3062825f | 13519 | |
ab96de7e | 13520 | /* Search for prologue/epilogue insns and replace them. */ |
3062825f | 13521 | |
ab96de7e AS |
13522 | for (insn = get_insns (); insn; insn = next_insn) |
13523 | { | |
13524 | int first, last, off; | |
13525 | rtx set, base, offset; | |
6455a49e | 13526 | rtx pat; |
3062825f | 13527 | |
ab96de7e | 13528 | next_insn = NEXT_INSN (insn); |
89ce1c8f | 13529 | |
6455a49e | 13530 | if (! NONJUMP_INSN_P (insn) || ! RTX_FRAME_RELATED_P (insn)) |
ab96de7e | 13531 | continue; |
3062825f | 13532 | |
6455a49e AK |
13533 | pat = PATTERN (insn); |
13534 | ||
13535 | /* Remove ldgr/lgdr instructions used for saving and restore | |
13536 | GPRs if possible. */ | |
82c6f58a AK |
13537 | if (TARGET_Z10) |
13538 | { | |
13539 | rtx tmp_pat = pat; | |
6455a49e | 13540 | |
82c6f58a AK |
13541 | if (INSN_CODE (insn) == CODE_FOR_stack_restore_from_fpr) |
13542 | tmp_pat = XVECEXP (pat, 0, 0); | |
6455a49e | 13543 | |
82c6f58a AK |
13544 | if (GET_CODE (tmp_pat) == SET |
13545 | && GET_MODE (SET_SRC (tmp_pat)) == DImode | |
13546 | && REG_P (SET_SRC (tmp_pat)) | |
13547 | && REG_P (SET_DEST (tmp_pat))) | |
13548 | { | |
13549 | int src_regno = REGNO (SET_SRC (tmp_pat)); | |
13550 | int dest_regno = REGNO (SET_DEST (tmp_pat)); | |
13551 | int gpr_regno; | |
13552 | int fpr_regno; | |
13553 | ||
13554 | if (!((GENERAL_REGNO_P (src_regno) | |
13555 | && FP_REGNO_P (dest_regno)) | |
13556 | || (FP_REGNO_P (src_regno) | |
13557 | && GENERAL_REGNO_P (dest_regno)))) | |
13558 | continue; | |
6455a49e | 13559 | |
82c6f58a AK |
13560 | gpr_regno = GENERAL_REGNO_P (src_regno) ? src_regno : dest_regno; |
13561 | fpr_regno = FP_REGNO_P (src_regno) ? src_regno : dest_regno; | |
6455a49e | 13562 | |
82c6f58a AK |
13563 | /* GPR must be call-saved, FPR must be call-clobbered. */ |
13564 | if (!call_really_used_regs[fpr_regno] | |
13565 | || call_really_used_regs[gpr_regno]) | |
13566 | continue; | |
13567 | ||
13568 | /* It must not happen that what we once saved in an FPR now | |
13569 | needs a stack slot. */ | |
13570 | gcc_assert (cfun_gpr_save_slot (gpr_regno) != SAVE_SLOT_STACK); | |
13571 | ||
13572 | if (cfun_gpr_save_slot (gpr_regno) == SAVE_SLOT_NONE) | |
13573 | { | |
13574 | remove_insn (insn); | |
13575 | continue; | |
13576 | } | |
6455a49e AK |
13577 | } |
13578 | } | |
13579 | ||
13580 | if (GET_CODE (pat) == PARALLEL | |
13581 | && store_multiple_operation (pat, VOIDmode)) | |
3062825f | 13582 | { |
6455a49e | 13583 | set = XVECEXP (pat, 0, 0); |
ab96de7e | 13584 | first = REGNO (SET_SRC (set)); |
6455a49e | 13585 | last = first + XVECLEN (pat, 0) - 1; |
ab96de7e AS |
13586 | offset = const0_rtx; |
13587 | base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset); | |
13588 | off = INTVAL (offset); | |
3062825f | 13589 | |
ab96de7e AS |
13590 | if (GET_CODE (base) != REG || off < 0) |
13591 | continue; | |
22a707a4 AK |
13592 | if (cfun_frame_layout.first_save_gpr != -1 |
13593 | && (cfun_frame_layout.first_save_gpr < first | |
13594 | || cfun_frame_layout.last_save_gpr > last)) | |
13595 | continue; | |
ab96de7e AS |
13596 | if (REGNO (base) != STACK_POINTER_REGNUM |
13597 | && REGNO (base) != HARD_FRAME_POINTER_REGNUM) | |
13598 | continue; | |
13599 | if (first > BASE_REGNUM || last < BASE_REGNUM) | |
13600 | continue; | |
13601 | ||
13602 | if (cfun_frame_layout.first_save_gpr != -1) | |
3062825f | 13603 | { |
775c43d3 | 13604 | rtx s_pat = save_gprs (base, |
ab96de7e | 13605 | off + (cfun_frame_layout.first_save_gpr |
9602b6a1 | 13606 | - first) * UNITS_PER_LONG, |
ab96de7e AS |
13607 | cfun_frame_layout.first_save_gpr, |
13608 | cfun_frame_layout.last_save_gpr); | |
775c43d3 | 13609 | new_insn = emit_insn_before (s_pat, insn); |
ab96de7e | 13610 | INSN_ADDRESSES_NEW (new_insn, -1); |
3062825f | 13611 | } |
3062825f | 13612 | |
ab96de7e AS |
13613 | remove_insn (insn); |
13614 | continue; | |
3062825f UW |
13615 | } |
13616 | ||
22a707a4 | 13617 | if (cfun_frame_layout.first_save_gpr == -1 |
6455a49e AK |
13618 | && GET_CODE (pat) == SET |
13619 | && GENERAL_REG_P (SET_SRC (pat)) | |
13620 | && GET_CODE (SET_DEST (pat)) == MEM) | |
3062825f | 13621 | { |
6455a49e | 13622 | set = pat; |
ab96de7e AS |
13623 | first = REGNO (SET_SRC (set)); |
13624 | offset = const0_rtx; | |
13625 | base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset); | |
13626 | off = INTVAL (offset); | |
3062825f | 13627 | |
ab96de7e AS |
13628 | if (GET_CODE (base) != REG || off < 0) |
13629 | continue; | |
13630 | if (REGNO (base) != STACK_POINTER_REGNUM | |
13631 | && REGNO (base) != HARD_FRAME_POINTER_REGNUM) | |
13632 | continue; | |
3062825f | 13633 | |
ab96de7e AS |
13634 | remove_insn (insn); |
13635 | continue; | |
3062825f UW |
13636 | } |
13637 | ||
6455a49e AK |
13638 | if (GET_CODE (pat) == PARALLEL |
13639 | && load_multiple_operation (pat, VOIDmode)) | |
89ce1c8f | 13640 | { |
6455a49e | 13641 | set = XVECEXP (pat, 0, 0); |
ab96de7e | 13642 | first = REGNO (SET_DEST (set)); |
6455a49e | 13643 | last = first + XVECLEN (pat, 0) - 1; |
ab96de7e AS |
13644 | offset = const0_rtx; |
13645 | base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset); | |
13646 | off = INTVAL (offset); | |
89ce1c8f | 13647 | |
ab96de7e AS |
13648 | if (GET_CODE (base) != REG || off < 0) |
13649 | continue; | |
6455a49e | 13650 | |
22a707a4 AK |
13651 | if (cfun_frame_layout.first_restore_gpr != -1 |
13652 | && (cfun_frame_layout.first_restore_gpr < first | |
13653 | || cfun_frame_layout.last_restore_gpr > last)) | |
13654 | continue; | |
ab96de7e AS |
13655 | if (REGNO (base) != STACK_POINTER_REGNUM |
13656 | && REGNO (base) != HARD_FRAME_POINTER_REGNUM) | |
13657 | continue; | |
13658 | if (first > BASE_REGNUM || last < BASE_REGNUM) | |
13659 | continue; | |
3062825f | 13660 | |
ab96de7e AS |
13661 | if (cfun_frame_layout.first_restore_gpr != -1) |
13662 | { | |
775c43d3 | 13663 | rtx rpat = restore_gprs (base, |
ab96de7e | 13664 | off + (cfun_frame_layout.first_restore_gpr |
9602b6a1 | 13665 | - first) * UNITS_PER_LONG, |
ab96de7e AS |
13666 | cfun_frame_layout.first_restore_gpr, |
13667 | cfun_frame_layout.last_restore_gpr); | |
0621cf3c RS |
13668 | |
13669 | /* Remove REG_CFA_RESTOREs for registers that we no | |
13670 | longer need to save. */ | |
775c43d3 DM |
13671 | REG_NOTES (rpat) = REG_NOTES (insn); |
13672 | for (rtx *ptr = ®_NOTES (rpat); *ptr; ) | |
0621cf3c RS |
13673 | if (REG_NOTE_KIND (*ptr) == REG_CFA_RESTORE |
13674 | && ((int) REGNO (XEXP (*ptr, 0)) | |
13675 | < cfun_frame_layout.first_restore_gpr)) | |
13676 | *ptr = XEXP (*ptr, 1); | |
13677 | else | |
13678 | ptr = &XEXP (*ptr, 1); | |
775c43d3 | 13679 | new_insn = emit_insn_before (rpat, insn); |
0621cf3c | 13680 | RTX_FRAME_RELATED_P (new_insn) = 1; |
ab96de7e AS |
13681 | INSN_ADDRESSES_NEW (new_insn, -1); |
13682 | } | |
89ce1c8f | 13683 | |
ab96de7e AS |
13684 | remove_insn (insn); |
13685 | continue; | |
89ce1c8f JJ |
13686 | } |
13687 | ||
22a707a4 | 13688 | if (cfun_frame_layout.first_restore_gpr == -1 |
6455a49e AK |
13689 | && GET_CODE (pat) == SET |
13690 | && GENERAL_REG_P (SET_DEST (pat)) | |
13691 | && GET_CODE (SET_SRC (pat)) == MEM) | |
3062825f | 13692 | { |
6455a49e | 13693 | set = pat; |
ab96de7e AS |
13694 | first = REGNO (SET_DEST (set)); |
13695 | offset = const0_rtx; | |
13696 | base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset); | |
13697 | off = INTVAL (offset); | |
c7453384 | 13698 | |
ab96de7e AS |
13699 | if (GET_CODE (base) != REG || off < 0) |
13700 | continue; | |
6455a49e | 13701 | |
ab96de7e AS |
13702 | if (REGNO (base) != STACK_POINTER_REGNUM |
13703 | && REGNO (base) != HARD_FRAME_POINTER_REGNUM) | |
13704 | continue; | |
29742ba4 | 13705 | |
ab96de7e AS |
13706 | remove_insn (insn); |
13707 | continue; | |
13708 | } | |
13709 | } | |
29742ba4 HP |
13710 | } |
13711 | ||
65b1d8ea AK |
13712 | /* On z10 and later the dynamic branch prediction must see the |
13713 | backward jump within a certain windows. If not it falls back to | |
13714 | the static prediction. This function rearranges the loop backward | |
13715 | branch in a way which makes the static prediction always correct. | |
13716 | The function returns true if it added an instruction. */ | |
b0f86a7e | 13717 | static bool |
775c43d3 | 13718 | s390_fix_long_loop_prediction (rtx_insn *insn) |
b0f86a7e AK |
13719 | { |
13720 | rtx set = single_set (insn); | |
9b2ea071 | 13721 | rtx code_label, label_ref; |
e60365d3 | 13722 | rtx_insn *uncond_jump; |
775c43d3 | 13723 | rtx_insn *cur_insn; |
b0f86a7e AK |
13724 | rtx tmp; |
13725 | int distance; | |
13726 | ||
13727 | /* This will exclude branch on count and branch on index patterns | |
13728 | since these are correctly statically predicted. */ | |
13729 | if (!set | |
13730 | || SET_DEST (set) != pc_rtx | |
13731 | || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE) | |
13732 | return false; | |
13733 | ||
177bc204 RS |
13734 | /* Skip conditional returns. */ |
13735 | if (ANY_RETURN_P (XEXP (SET_SRC (set), 1)) | |
13736 | && XEXP (SET_SRC (set), 2) == pc_rtx) | |
13737 | return false; | |
13738 | ||
b0f86a7e AK |
13739 | label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ? |
13740 | XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2)); | |
13741 | ||
13742 | gcc_assert (GET_CODE (label_ref) == LABEL_REF); | |
13743 | ||
13744 | code_label = XEXP (label_ref, 0); | |
13745 | ||
13746 | if (INSN_ADDRESSES (INSN_UID (code_label)) == -1 | |
13747 | || INSN_ADDRESSES (INSN_UID (insn)) == -1 | |
13748 | || (INSN_ADDRESSES (INSN_UID (insn)) | |
65b1d8ea | 13749 | - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE)) |
b0f86a7e AK |
13750 | return false; |
13751 | ||
13752 | for (distance = 0, cur_insn = PREV_INSN (insn); | |
65b1d8ea | 13753 | distance < PREDICT_DISTANCE - 6; |
b0f86a7e AK |
13754 | distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn)) |
13755 | if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn)) | |
13756 | return false; | |
13757 | ||
9b2ea071 | 13758 | rtx_code_label *new_label = gen_label_rtx (); |
b0f86a7e | 13759 | uncond_jump = emit_jump_insn_after ( |
f7df4a84 | 13760 | gen_rtx_SET (pc_rtx, |
b0f86a7e AK |
13761 | gen_rtx_LABEL_REF (VOIDmode, code_label)), |
13762 | insn); | |
13763 | emit_label_after (new_label, uncond_jump); | |
13764 | ||
13765 | tmp = XEXP (SET_SRC (set), 1); | |
13766 | XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2); | |
13767 | XEXP (SET_SRC (set), 2) = tmp; | |
13768 | INSN_CODE (insn) = -1; | |
13769 | ||
13770 | XEXP (label_ref, 0) = new_label; | |
13771 | JUMP_LABEL (insn) = new_label; | |
13772 | JUMP_LABEL (uncond_jump) = code_label; | |
13773 | ||
13774 | return true; | |
13775 | } | |
13776 | ||
d277db6b WG |
13777 | /* Returns 1 if INSN reads the value of REG for purposes not related |
13778 | to addressing of memory, and 0 otherwise. */ | |
13779 | static int | |
775c43d3 | 13780 | s390_non_addr_reg_read_p (rtx reg, rtx_insn *insn) |
d277db6b WG |
13781 | { |
13782 | return reg_referenced_p (reg, PATTERN (insn)) | |
13783 | && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn)); | |
13784 | } | |
13785 | ||
e3cba5e5 AK |
13786 | /* Starting from INSN find_cond_jump looks downwards in the insn |
13787 | stream for a single jump insn which is the last user of the | |
13788 | condition code set in INSN. */ | |
775c43d3 DM |
13789 | static rtx_insn * |
13790 | find_cond_jump (rtx_insn *insn) | |
e3cba5e5 AK |
13791 | { |
13792 | for (; insn; insn = NEXT_INSN (insn)) | |
13793 | { | |
13794 | rtx ite, cc; | |
13795 | ||
13796 | if (LABEL_P (insn)) | |
13797 | break; | |
13798 | ||
13799 | if (!JUMP_P (insn)) | |
13800 | { | |
13801 | if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn)) | |
13802 | break; | |
13803 | continue; | |
13804 | } | |
13805 | ||
13806 | /* This will be triggered by a return. */ | |
13807 | if (GET_CODE (PATTERN (insn)) != SET) | |
13808 | break; | |
13809 | ||
13810 | gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx); | |
13811 | ite = SET_SRC (PATTERN (insn)); | |
13812 | ||
13813 | if (GET_CODE (ite) != IF_THEN_ELSE) | |
13814 | break; | |
13815 | ||
13816 | cc = XEXP (XEXP (ite, 0), 0); | |
13817 | if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc))) | |
13818 | break; | |
13819 | ||
13820 | if (find_reg_note (insn, REG_DEAD, cc)) | |
13821 | return insn; | |
13822 | break; | |
13823 | } | |
13824 | ||
775c43d3 | 13825 | return NULL; |
e3cba5e5 AK |
13826 | } |
13827 | ||
13828 | /* Swap the condition in COND and the operands in OP0 and OP1 so that | |
13829 | the semantics does not change. If NULL_RTX is passed as COND the | |
13830 | function tries to find the conditional jump starting with INSN. */ | |
13831 | static void | |
775c43d3 | 13832 | s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx_insn *insn) |
e3cba5e5 AK |
13833 | { |
13834 | rtx tmp = *op0; | |
13835 | ||
13836 | if (cond == NULL_RTX) | |
13837 | { | |
e8a54173 DM |
13838 | rtx_insn *jump = find_cond_jump (NEXT_INSN (insn)); |
13839 | rtx set = jump ? single_set (jump) : NULL_RTX; | |
e3cba5e5 | 13840 | |
e8a54173 | 13841 | if (set == NULL_RTX) |
e3cba5e5 AK |
13842 | return; |
13843 | ||
e8a54173 | 13844 | cond = XEXP (SET_SRC (set), 0); |
e3cba5e5 AK |
13845 | } |
13846 | ||
13847 | *op0 = *op1; | |
13848 | *op1 = tmp; | |
13849 | PUT_CODE (cond, swap_condition (GET_CODE (cond))); | |
13850 | } | |
d277db6b WG |
13851 | |
13852 | /* On z10, instructions of the compare-and-branch family have the | |
13853 | property to access the register occurring as second operand with | |
13854 | its bits complemented. If such a compare is grouped with a second | |
13855 | instruction that accesses the same register non-complemented, and | |
13856 | if that register's value is delivered via a bypass, then the | |
13857 | pipeline recycles, thereby causing significant performance decline. | |
13858 | This function locates such situations and exchanges the two | |
b0f86a7e AK |
13859 | operands of the compare. The function return true whenever it |
13860 | added an insn. */ | |
13861 | static bool | |
775c43d3 | 13862 | s390_z10_optimize_cmp (rtx_insn *insn) |
d277db6b | 13863 | { |
775c43d3 | 13864 | rtx_insn *prev_insn, *next_insn; |
b0f86a7e AK |
13865 | bool insn_added_p = false; |
13866 | rtx cond, *op0, *op1; | |
d277db6b | 13867 | |
b0f86a7e | 13868 | if (GET_CODE (PATTERN (insn)) == PARALLEL) |
d277db6b | 13869 | { |
b0f86a7e AK |
13870 | /* Handle compare and branch and branch on count |
13871 | instructions. */ | |
13872 | rtx pattern = single_set (insn); | |
e3cba5e5 | 13873 | |
b0f86a7e AK |
13874 | if (!pattern |
13875 | || SET_DEST (pattern) != pc_rtx | |
13876 | || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE) | |
13877 | return false; | |
d277db6b | 13878 | |
b0f86a7e AK |
13879 | cond = XEXP (SET_SRC (pattern), 0); |
13880 | op0 = &XEXP (cond, 0); | |
13881 | op1 = &XEXP (cond, 1); | |
13882 | } | |
13883 | else if (GET_CODE (PATTERN (insn)) == SET) | |
13884 | { | |
13885 | rtx src, dest; | |
d277db6b | 13886 | |
b0f86a7e AK |
13887 | /* Handle normal compare instructions. */ |
13888 | src = SET_SRC (PATTERN (insn)); | |
13889 | dest = SET_DEST (PATTERN (insn)); | |
e3cba5e5 | 13890 | |
b0f86a7e AK |
13891 | if (!REG_P (dest) |
13892 | || !CC_REGNO_P (REGNO (dest)) | |
13893 | || GET_CODE (src) != COMPARE) | |
13894 | return false; | |
e3cba5e5 | 13895 | |
b0f86a7e AK |
13896 | /* s390_swap_cmp will try to find the conditional |
13897 | jump when passing NULL_RTX as condition. */ | |
13898 | cond = NULL_RTX; | |
13899 | op0 = &XEXP (src, 0); | |
13900 | op1 = &XEXP (src, 1); | |
13901 | } | |
13902 | else | |
13903 | return false; | |
e3cba5e5 | 13904 | |
b0f86a7e AK |
13905 | if (!REG_P (*op0) || !REG_P (*op1)) |
13906 | return false; | |
e3cba5e5 | 13907 | |
2dfdbf2b AK |
13908 | if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT) |
13909 | return false; | |
13910 | ||
b0f86a7e AK |
13911 | /* Swap the COMPARE arguments and its mask if there is a |
13912 | conflicting access in the previous insn. */ | |
33ab2bd4 | 13913 | prev_insn = prev_active_insn (insn); |
b0f86a7e AK |
13914 | if (prev_insn != NULL_RTX && INSN_P (prev_insn) |
13915 | && reg_referenced_p (*op1, PATTERN (prev_insn))) | |
13916 | s390_swap_cmp (cond, op0, op1, insn); | |
13917 | ||
13918 | /* Check if there is a conflict with the next insn. If there | |
13919 | was no conflict with the previous insn, then swap the | |
13920 | COMPARE arguments and its mask. If we already swapped | |
13921 | the operands, or if swapping them would cause a conflict | |
13922 | with the previous insn, issue a NOP after the COMPARE in | |
13923 | order to separate the two instuctions. */ | |
33ab2bd4 | 13924 | next_insn = next_active_insn (insn); |
b0f86a7e AK |
13925 | if (next_insn != NULL_RTX && INSN_P (next_insn) |
13926 | && s390_non_addr_reg_read_p (*op1, next_insn)) | |
13927 | { | |
e3cba5e5 | 13928 | if (prev_insn != NULL_RTX && INSN_P (prev_insn) |
b0f86a7e | 13929 | && s390_non_addr_reg_read_p (*op0, prev_insn)) |
e3cba5e5 | 13930 | { |
b0f86a7e AK |
13931 | if (REGNO (*op1) == 0) |
13932 | emit_insn_after (gen_nop1 (), insn); | |
e3cba5e5 | 13933 | else |
b0f86a7e AK |
13934 | emit_insn_after (gen_nop (), insn); |
13935 | insn_added_p = true; | |
d277db6b | 13936 | } |
b0f86a7e AK |
13937 | else |
13938 | s390_swap_cmp (cond, op0, op1, insn); | |
d277db6b | 13939 | } |
b0f86a7e | 13940 | return insn_added_p; |
d277db6b WG |
13941 | } |
13942 | ||
539405d5 AK |
13943 | /* Number of INSNs to be scanned backward in the last BB of the loop |
13944 | and forward in the first BB of the loop. This usually should be a | |
13945 | bit more than the number of INSNs which could go into one | |
13946 | group. */ | |
13947 | #define S390_OSC_SCAN_INSN_NUM 5 | |
13948 | ||
13949 | /* Scan LOOP for static OSC collisions and return true if a osc_break | |
13950 | should be issued for this loop. */ | |
13951 | static bool | |
13952 | s390_adjust_loop_scan_osc (struct loop* loop) | |
13953 | ||
13954 | { | |
13955 | HARD_REG_SET modregs, newregs; | |
13956 | rtx_insn *insn, *store_insn = NULL; | |
13957 | rtx set; | |
13958 | struct s390_address addr_store, addr_load; | |
13959 | subrtx_iterator::array_type array; | |
13960 | int insn_count; | |
13961 | ||
13962 | CLEAR_HARD_REG_SET (modregs); | |
13963 | ||
13964 | insn_count = 0; | |
13965 | FOR_BB_INSNS_REVERSE (loop->latch, insn) | |
13966 | { | |
13967 | if (!INSN_P (insn) || INSN_CODE (insn) <= 0) | |
13968 | continue; | |
13969 | ||
13970 | insn_count++; | |
13971 | if (insn_count > S390_OSC_SCAN_INSN_NUM) | |
13972 | return false; | |
13973 | ||
13974 | find_all_hard_reg_sets (insn, &newregs, true); | |
13975 | IOR_HARD_REG_SET (modregs, newregs); | |
13976 | ||
13977 | set = single_set (insn); | |
13978 | if (!set) | |
13979 | continue; | |
13980 | ||
13981 | if (MEM_P (SET_DEST (set)) | |
13982 | && s390_decompose_address (XEXP (SET_DEST (set), 0), &addr_store)) | |
13983 | { | |
13984 | store_insn = insn; | |
13985 | break; | |
13986 | } | |
13987 | } | |
13988 | ||
13989 | if (store_insn == NULL_RTX) | |
13990 | return false; | |
13991 | ||
13992 | insn_count = 0; | |
13993 | FOR_BB_INSNS (loop->header, insn) | |
13994 | { | |
13995 | if (!INSN_P (insn) || INSN_CODE (insn) <= 0) | |
13996 | continue; | |
13997 | ||
13998 | if (insn == store_insn) | |
13999 | return false; | |
14000 | ||
14001 | insn_count++; | |
14002 | if (insn_count > S390_OSC_SCAN_INSN_NUM) | |
14003 | return false; | |
14004 | ||
14005 | find_all_hard_reg_sets (insn, &newregs, true); | |
14006 | IOR_HARD_REG_SET (modregs, newregs); | |
14007 | ||
14008 | set = single_set (insn); | |
14009 | if (!set) | |
14010 | continue; | |
14011 | ||
14012 | /* An intermediate store disrupts static OSC checking | |
14013 | anyway. */ | |
14014 | if (MEM_P (SET_DEST (set)) | |
14015 | && s390_decompose_address (XEXP (SET_DEST (set), 0), NULL)) | |
14016 | return false; | |
14017 | ||
14018 | FOR_EACH_SUBRTX (iter, array, SET_SRC (set), NONCONST) | |
14019 | if (MEM_P (*iter) | |
14020 | && s390_decompose_address (XEXP (*iter, 0), &addr_load) | |
14021 | && rtx_equal_p (addr_load.base, addr_store.base) | |
14022 | && rtx_equal_p (addr_load.indx, addr_store.indx) | |
14023 | && rtx_equal_p (addr_load.disp, addr_store.disp)) | |
14024 | { | |
14025 | if ((addr_load.base != NULL_RTX | |
14026 | && TEST_HARD_REG_BIT (modregs, REGNO (addr_load.base))) | |
14027 | || (addr_load.indx != NULL_RTX | |
14028 | && TEST_HARD_REG_BIT (modregs, REGNO (addr_load.indx)))) | |
14029 | return true; | |
14030 | } | |
14031 | } | |
14032 | return false; | |
14033 | } | |
14034 | ||
14035 | /* Look for adjustments which can be done on simple innermost | |
14036 | loops. */ | |
14037 | static void | |
14038 | s390_adjust_loops () | |
14039 | { | |
14040 | struct loop *loop = NULL; | |
14041 | ||
14042 | df_analyze (); | |
14043 | compute_bb_for_insn (); | |
14044 | ||
14045 | /* Find the loops. */ | |
14046 | loop_optimizer_init (AVOID_CFG_MODIFICATIONS); | |
14047 | ||
14048 | FOR_EACH_LOOP (loop, LI_ONLY_INNERMOST) | |
14049 | { | |
14050 | if (dump_file) | |
14051 | { | |
14052 | flow_loop_dump (loop, dump_file, NULL, 0); | |
14053 | fprintf (dump_file, ";; OSC loop scan Loop: "); | |
14054 | } | |
14055 | if (loop->latch == NULL | |
14056 | || pc_set (BB_END (loop->latch)) == NULL_RTX | |
14057 | || !s390_adjust_loop_scan_osc (loop)) | |
14058 | { | |
14059 | if (dump_file) | |
14060 | { | |
14061 | if (loop->latch == NULL) | |
14062 | fprintf (dump_file, " muliple backward jumps\n"); | |
14063 | else | |
14064 | { | |
14065 | fprintf (dump_file, " header insn: %d latch insn: %d ", | |
14066 | INSN_UID (BB_HEAD (loop->header)), | |
14067 | INSN_UID (BB_END (loop->latch))); | |
14068 | if (pc_set (BB_END (loop->latch)) == NULL_RTX) | |
14069 | fprintf (dump_file, " loop does not end with jump\n"); | |
14070 | else | |
14071 | fprintf (dump_file, " not instrumented\n"); | |
14072 | } | |
14073 | } | |
14074 | } | |
14075 | else | |
14076 | { | |
14077 | rtx_insn *new_insn; | |
14078 | ||
14079 | if (dump_file) | |
14080 | fprintf (dump_file, " adding OSC break insn: "); | |
14081 | new_insn = emit_insn_before (gen_osc_break (), | |
14082 | BB_END (loop->latch)); | |
14083 | INSN_ADDRESSES_NEW (new_insn, -1); | |
14084 | } | |
14085 | } | |
14086 | ||
14087 | loop_optimizer_finalize (); | |
14088 | ||
14089 | df_finish_pass (false); | |
14090 | } | |
14091 | ||
ab96de7e | 14092 | /* Perform machine-dependent processing. */ |
ed9676cf | 14093 | |
ab96de7e AS |
14094 | static void |
14095 | s390_reorg (void) | |
ed9676cf | 14096 | { |
ab96de7e | 14097 | bool pool_overflow = false; |
f8af0e30 | 14098 | int hw_before, hw_after; |
ed9676cf | 14099 | |
539405d5 AK |
14100 | if (s390_tune == PROCESSOR_2964_Z13) |
14101 | s390_adjust_loops (); | |
14102 | ||
ab96de7e AS |
14103 | /* Make sure all splits have been performed; splits after |
14104 | machine_dependent_reorg might confuse insn length counts. */ | |
14105 | split_all_insns_noflow (); | |
38899e29 | 14106 | |
ab96de7e AS |
14107 | /* Install the main literal pool and the associated base |
14108 | register load insns. | |
38899e29 | 14109 | |
ab96de7e AS |
14110 | In addition, there are two problematic situations we need |
14111 | to correct: | |
ed9676cf | 14112 | |
ab96de7e AS |
14113 | - the literal pool might be > 4096 bytes in size, so that |
14114 | some of its elements cannot be directly accessed | |
ed9676cf | 14115 | |
ab96de7e AS |
14116 | - a branch target might be > 64K away from the branch, so that |
14117 | it is not possible to use a PC-relative instruction. | |
ed9676cf | 14118 | |
ab96de7e AS |
14119 | To fix those, we split the single literal pool into multiple |
14120 | pool chunks, reloading the pool base register at various | |
14121 | points throughout the function to ensure it always points to | |
14122 | the pool chunk the following code expects, and / or replace | |
14123 | PC-relative branches by absolute branches. | |
ed9676cf | 14124 | |
ab96de7e AS |
14125 | However, the two problems are interdependent: splitting the |
14126 | literal pool can move a branch further away from its target, | |
14127 | causing the 64K limit to overflow, and on the other hand, | |
14128 | replacing a PC-relative branch by an absolute branch means | |
14129 | we need to put the branch target address into the literal | |
14130 | pool, possibly causing it to overflow. | |
ffdda752 | 14131 | |
ab96de7e AS |
14132 | So, we loop trying to fix up both problems until we manage |
14133 | to satisfy both conditions at the same time. Note that the | |
14134 | loop is guaranteed to terminate as every pass of the loop | |
14135 | strictly decreases the total number of PC-relative branches | |
14136 | in the function. (This is not completely true as there | |
14137 | might be branch-over-pool insns introduced by chunkify_start. | |
14138 | Those never need to be split however.) */ | |
ffdda752 | 14139 | |
ab96de7e AS |
14140 | for (;;) |
14141 | { | |
14142 | struct constant_pool *pool = NULL; | |
a628ab6d | 14143 | |
ab96de7e AS |
14144 | /* Collect the literal pool. */ |
14145 | if (!pool_overflow) | |
14146 | { | |
14147 | pool = s390_mainpool_start (); | |
14148 | if (!pool) | |
14149 | pool_overflow = true; | |
14150 | } | |
a628ab6d | 14151 | |
ab96de7e AS |
14152 | /* If literal pool overflowed, start to chunkify it. */ |
14153 | if (pool_overflow) | |
14154 | pool = s390_chunkify_start (); | |
a628ab6d | 14155 | |
ab96de7e AS |
14156 | /* Split out-of-range branches. If this has created new |
14157 | literal pool entries, cancel current chunk list and | |
14158 | recompute it. zSeries machines have large branch | |
14159 | instructions, so we never need to split a branch. */ | |
14160 | if (!TARGET_CPU_ZARCH && s390_split_branches ()) | |
14161 | { | |
14162 | if (pool_overflow) | |
14163 | s390_chunkify_cancel (pool); | |
14164 | else | |
14165 | s390_mainpool_cancel (pool); | |
a628ab6d | 14166 | |
ab96de7e AS |
14167 | continue; |
14168 | } | |
14169 | ||
14170 | /* If we made it up to here, both conditions are satisfied. | |
14171 | Finish up literal pool related changes. */ | |
14172 | if (pool_overflow) | |
14173 | s390_chunkify_finish (pool); | |
14174 | else | |
14175 | s390_mainpool_finish (pool); | |
14176 | ||
14177 | /* We're done splitting branches. */ | |
14178 | cfun->machine->split_branches_pending_p = false; | |
14179 | break; | |
a628ab6d | 14180 | } |
a628ab6d | 14181 | |
d24959df UW |
14182 | /* Generate out-of-pool execute target insns. */ |
14183 | if (TARGET_CPU_ZARCH) | |
14184 | { | |
775c43d3 DM |
14185 | rtx_insn *insn, *target; |
14186 | rtx label; | |
d24959df UW |
14187 | |
14188 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
14189 | { | |
14190 | label = s390_execute_label (insn); | |
14191 | if (!label) | |
14192 | continue; | |
14193 | ||
14194 | gcc_assert (label != const0_rtx); | |
14195 | ||
14196 | target = emit_label (XEXP (label, 0)); | |
14197 | INSN_ADDRESSES_NEW (target, -1); | |
14198 | ||
14199 | target = emit_insn (s390_execute_target (insn)); | |
14200 | INSN_ADDRESSES_NEW (target, -1); | |
14201 | } | |
14202 | } | |
14203 | ||
14204 | /* Try to optimize prologue and epilogue further. */ | |
ab96de7e | 14205 | s390_optimize_prologue (); |
d277db6b | 14206 | |
65b1d8ea | 14207 | /* Walk over the insns and do some >=z10 specific changes. */ |
bacf8ec3 | 14208 | if (s390_tune >= PROCESSOR_2097_Z10) |
b0f86a7e | 14209 | { |
775c43d3 | 14210 | rtx_insn *insn; |
b0f86a7e AK |
14211 | bool insn_added_p = false; |
14212 | ||
14213 | /* The insn lengths and addresses have to be up to date for the | |
14214 | following manipulations. */ | |
14215 | shorten_branches (get_insns ()); | |
14216 | ||
14217 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
14218 | { | |
14219 | if (!INSN_P (insn) || INSN_CODE (insn) <= 0) | |
14220 | continue; | |
14221 | ||
14222 | if (JUMP_P (insn)) | |
65b1d8ea | 14223 | insn_added_p |= s390_fix_long_loop_prediction (insn); |
b0f86a7e | 14224 | |
65b1d8ea AK |
14225 | if ((GET_CODE (PATTERN (insn)) == PARALLEL |
14226 | || GET_CODE (PATTERN (insn)) == SET) | |
14227 | && s390_tune == PROCESSOR_2097_Z10) | |
b0f86a7e AK |
14228 | insn_added_p |= s390_z10_optimize_cmp (insn); |
14229 | } | |
14230 | ||
14231 | /* Adjust branches if we added new instructions. */ | |
14232 | if (insn_added_p) | |
14233 | shorten_branches (get_insns ()); | |
14234 | } | |
f8af0e30 DV |
14235 | |
14236 | s390_function_num_hotpatch_hw (current_function_decl, &hw_before, &hw_after); | |
14237 | if (hw_after > 0) | |
14238 | { | |
14239 | rtx_insn *insn; | |
14240 | ||
2d38d809 | 14241 | /* Insert NOPs for hotpatching. */ |
f8af0e30 | 14242 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
1f8d3e42 DV |
14243 | /* Emit NOPs |
14244 | 1. inside the area covered by debug information to allow setting | |
14245 | breakpoints at the NOPs, | |
14246 | 2. before any insn which results in an asm instruction, | |
14247 | 3. before in-function labels to avoid jumping to the NOPs, for | |
14248 | example as part of a loop, | |
14249 | 4. before any barrier in case the function is completely empty | |
14250 | (__builtin_unreachable ()) and has neither internal labels nor | |
14251 | active insns. | |
14252 | */ | |
14253 | if (active_insn_p (insn) || BARRIER_P (insn) || LABEL_P (insn)) | |
14254 | break; | |
14255 | /* Output a series of NOPs before the first active insn. */ | |
14256 | while (insn && hw_after > 0) | |
f8af0e30 DV |
14257 | { |
14258 | if (hw_after >= 3 && TARGET_CPU_ZARCH) | |
14259 | { | |
1f8d3e42 | 14260 | emit_insn_before (gen_nop_6_byte (), insn); |
f8af0e30 DV |
14261 | hw_after -= 3; |
14262 | } | |
14263 | else if (hw_after >= 2) | |
14264 | { | |
1f8d3e42 | 14265 | emit_insn_before (gen_nop_4_byte (), insn); |
f8af0e30 DV |
14266 | hw_after -= 2; |
14267 | } | |
14268 | else | |
14269 | { | |
1f8d3e42 | 14270 | emit_insn_before (gen_nop_2_byte (), insn); |
f8af0e30 DV |
14271 | hw_after -= 1; |
14272 | } | |
14273 | } | |
f8af0e30 | 14274 | } |
ab96de7e | 14275 | } |
ed9676cf | 14276 | |
3a892e44 AK |
14277 | /* Return true if INSN is a fp load insn writing register REGNO. */ |
14278 | static inline bool | |
647d790d | 14279 | s390_fpload_toreg (rtx_insn *insn, unsigned int regno) |
3a892e44 AK |
14280 | { |
14281 | rtx set; | |
14282 | enum attr_type flag = s390_safe_attr_type (insn); | |
14283 | ||
14284 | if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF) | |
14285 | return false; | |
14286 | ||
14287 | set = single_set (insn); | |
14288 | ||
14289 | if (set == NULL_RTX) | |
14290 | return false; | |
14291 | ||
14292 | if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set))) | |
14293 | return false; | |
14294 | ||
14295 | if (REGNO (SET_DEST (set)) != regno) | |
14296 | return false; | |
14297 | ||
14298 | return true; | |
14299 | } | |
14300 | ||
14301 | /* This value describes the distance to be avoided between an | |
5764ee3c | 14302 | arithmetic fp instruction and an fp load writing the same register. |
3a892e44 AK |
14303 | Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is |
14304 | fine but the exact value has to be avoided. Otherwise the FP | |
14305 | pipeline will throw an exception causing a major penalty. */ | |
14306 | #define Z10_EARLYLOAD_DISTANCE 7 | |
14307 | ||
14308 | /* Rearrange the ready list in order to avoid the situation described | |
14309 | for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is | |
14310 | moved to the very end of the ready list. */ | |
14311 | static void | |
ce1ce33a | 14312 | s390_z10_prevent_earlyload_conflicts (rtx_insn **ready, int *nready_p) |
3a892e44 AK |
14313 | { |
14314 | unsigned int regno; | |
14315 | int nready = *nready_p; | |
ce1ce33a | 14316 | rtx_insn *tmp; |
3a892e44 | 14317 | int i; |
775c43d3 | 14318 | rtx_insn *insn; |
3a892e44 AK |
14319 | rtx set; |
14320 | enum attr_type flag; | |
14321 | int distance; | |
14322 | ||
14323 | /* Skip DISTANCE - 1 active insns. */ | |
14324 | for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1; | |
14325 | distance > 0 && insn != NULL_RTX; | |
14326 | distance--, insn = prev_active_insn (insn)) | |
14327 | if (CALL_P (insn) || JUMP_P (insn)) | |
14328 | return; | |
14329 | ||
14330 | if (insn == NULL_RTX) | |
14331 | return; | |
14332 | ||
14333 | set = single_set (insn); | |
14334 | ||
14335 | if (set == NULL_RTX || !REG_P (SET_DEST (set)) | |
14336 | || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT) | |
14337 | return; | |
14338 | ||
14339 | flag = s390_safe_attr_type (insn); | |
14340 | ||
14341 | if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF) | |
14342 | return; | |
14343 | ||
14344 | regno = REGNO (SET_DEST (set)); | |
14345 | i = nready - 1; | |
14346 | ||
14347 | while (!s390_fpload_toreg (ready[i], regno) && i > 0) | |
14348 | i--; | |
14349 | ||
14350 | if (!i) | |
14351 | return; | |
14352 | ||
14353 | tmp = ready[i]; | |
ce1ce33a | 14354 | memmove (&ready[1], &ready[0], sizeof (rtx_insn *) * i); |
3a892e44 AK |
14355 | ready[0] = tmp; |
14356 | } | |
14357 | ||
22ac2c2f AK |
14358 | |
14359 | /* The s390_sched_state variable tracks the state of the current or | |
14360 | the last instruction group. | |
14361 | ||
14362 | 0,1,2 number of instructions scheduled in the current group | |
14363 | 3 the last group is complete - normal insns | |
14364 | 4 the last group was a cracked/expanded insn */ | |
14365 | ||
14366 | static int s390_sched_state; | |
14367 | ||
23902021 AK |
14368 | #define S390_SCHED_STATE_NORMAL 3 |
14369 | #define S390_SCHED_STATE_CRACKED 4 | |
22ac2c2f | 14370 | |
23902021 AK |
14371 | #define S390_SCHED_ATTR_MASK_CRACKED 0x1 |
14372 | #define S390_SCHED_ATTR_MASK_EXPANDED 0x2 | |
14373 | #define S390_SCHED_ATTR_MASK_ENDGROUP 0x4 | |
14374 | #define S390_SCHED_ATTR_MASK_GROUPALONE 0x8 | |
22ac2c2f AK |
14375 | |
14376 | static unsigned int | |
84034c69 | 14377 | s390_get_sched_attrmask (rtx_insn *insn) |
22ac2c2f AK |
14378 | { |
14379 | unsigned int mask = 0; | |
14380 | ||
23902021 AK |
14381 | switch (s390_tune) |
14382 | { | |
14383 | case PROCESSOR_2827_ZEC12: | |
14384 | if (get_attr_zEC12_cracked (insn)) | |
14385 | mask |= S390_SCHED_ATTR_MASK_CRACKED; | |
14386 | if (get_attr_zEC12_expanded (insn)) | |
14387 | mask |= S390_SCHED_ATTR_MASK_EXPANDED; | |
14388 | if (get_attr_zEC12_endgroup (insn)) | |
14389 | mask |= S390_SCHED_ATTR_MASK_ENDGROUP; | |
14390 | if (get_attr_zEC12_groupalone (insn)) | |
14391 | mask |= S390_SCHED_ATTR_MASK_GROUPALONE; | |
14392 | break; | |
14393 | case PROCESSOR_2964_Z13: | |
2731a5b3 | 14394 | case PROCESSOR_3906_Z14: |
23902021 AK |
14395 | if (get_attr_z13_cracked (insn)) |
14396 | mask |= S390_SCHED_ATTR_MASK_CRACKED; | |
14397 | if (get_attr_z13_expanded (insn)) | |
14398 | mask |= S390_SCHED_ATTR_MASK_EXPANDED; | |
14399 | if (get_attr_z13_endgroup (insn)) | |
14400 | mask |= S390_SCHED_ATTR_MASK_ENDGROUP; | |
14401 | if (get_attr_z13_groupalone (insn)) | |
14402 | mask |= S390_SCHED_ATTR_MASK_GROUPALONE; | |
14403 | break; | |
14404 | default: | |
14405 | gcc_unreachable (); | |
14406 | } | |
14407 | return mask; | |
14408 | } | |
14409 | ||
14410 | static unsigned int | |
14411 | s390_get_unit_mask (rtx_insn *insn, int *units) | |
14412 | { | |
14413 | unsigned int mask = 0; | |
14414 | ||
14415 | switch (s390_tune) | |
14416 | { | |
14417 | case PROCESSOR_2964_Z13: | |
2731a5b3 | 14418 | case PROCESSOR_3906_Z14: |
23902021 AK |
14419 | *units = 3; |
14420 | if (get_attr_z13_unit_lsu (insn)) | |
14421 | mask |= 1 << 0; | |
14422 | if (get_attr_z13_unit_fxu (insn)) | |
14423 | mask |= 1 << 1; | |
14424 | if (get_attr_z13_unit_vfu (insn)) | |
14425 | mask |= 1 << 2; | |
14426 | break; | |
14427 | default: | |
14428 | gcc_unreachable (); | |
14429 | } | |
22ac2c2f AK |
14430 | return mask; |
14431 | } | |
14432 | ||
14433 | /* Return the scheduling score for INSN. The higher the score the | |
14434 | better. The score is calculated from the OOO scheduling attributes | |
14435 | of INSN and the scheduling state s390_sched_state. */ | |
14436 | static int | |
84034c69 | 14437 | s390_sched_score (rtx_insn *insn) |
22ac2c2f AK |
14438 | { |
14439 | unsigned int mask = s390_get_sched_attrmask (insn); | |
14440 | int score = 0; | |
14441 | ||
14442 | switch (s390_sched_state) | |
14443 | { | |
14444 | case 0: | |
14445 | /* Try to put insns into the first slot which would otherwise | |
14446 | break a group. */ | |
23902021 AK |
14447 | if ((mask & S390_SCHED_ATTR_MASK_CRACKED) != 0 |
14448 | || (mask & S390_SCHED_ATTR_MASK_EXPANDED) != 0) | |
22ac2c2f | 14449 | score += 5; |
23902021 | 14450 | if ((mask & S390_SCHED_ATTR_MASK_GROUPALONE) != 0) |
22ac2c2f | 14451 | score += 10; |
1d92cba9 | 14452 | /* fallthrough */ |
22ac2c2f AK |
14453 | case 1: |
14454 | /* Prefer not cracked insns while trying to put together a | |
14455 | group. */ | |
23902021 AK |
14456 | if ((mask & S390_SCHED_ATTR_MASK_CRACKED) == 0 |
14457 | && (mask & S390_SCHED_ATTR_MASK_EXPANDED) == 0 | |
14458 | && (mask & S390_SCHED_ATTR_MASK_GROUPALONE) == 0) | |
22ac2c2f | 14459 | score += 10; |
23902021 | 14460 | if ((mask & S390_SCHED_ATTR_MASK_ENDGROUP) == 0) |
22ac2c2f AK |
14461 | score += 5; |
14462 | break; | |
14463 | case 2: | |
14464 | /* Prefer not cracked insns while trying to put together a | |
14465 | group. */ | |
23902021 AK |
14466 | if ((mask & S390_SCHED_ATTR_MASK_CRACKED) == 0 |
14467 | && (mask & S390_SCHED_ATTR_MASK_EXPANDED) == 0 | |
14468 | && (mask & S390_SCHED_ATTR_MASK_GROUPALONE) == 0) | |
22ac2c2f AK |
14469 | score += 10; |
14470 | /* Prefer endgroup insns in the last slot. */ | |
23902021 | 14471 | if ((mask & S390_SCHED_ATTR_MASK_ENDGROUP) != 0) |
22ac2c2f AK |
14472 | score += 10; |
14473 | break; | |
23902021 | 14474 | case S390_SCHED_STATE_NORMAL: |
22ac2c2f | 14475 | /* Prefer not cracked insns if the last was not cracked. */ |
23902021 AK |
14476 | if ((mask & S390_SCHED_ATTR_MASK_CRACKED) == 0 |
14477 | && (mask & S390_SCHED_ATTR_MASK_EXPANDED) == 0) | |
22ac2c2f | 14478 | score += 5; |
23902021 | 14479 | if ((mask & S390_SCHED_ATTR_MASK_GROUPALONE) != 0) |
22ac2c2f AK |
14480 | score += 10; |
14481 | break; | |
23902021 | 14482 | case S390_SCHED_STATE_CRACKED: |
22ac2c2f AK |
14483 | /* Try to keep cracked insns together to prevent them from |
14484 | interrupting groups. */ | |
23902021 AK |
14485 | if ((mask & S390_SCHED_ATTR_MASK_CRACKED) != 0 |
14486 | || (mask & S390_SCHED_ATTR_MASK_EXPANDED) != 0) | |
22ac2c2f AK |
14487 | score += 5; |
14488 | break; | |
14489 | } | |
23902021 | 14490 | |
6654e96f | 14491 | if (s390_tune >= PROCESSOR_2964_Z13) |
23902021 AK |
14492 | { |
14493 | int units, i; | |
14494 | unsigned unit_mask, m = 1; | |
14495 | ||
14496 | unit_mask = s390_get_unit_mask (insn, &units); | |
14497 | gcc_assert (units <= MAX_SCHED_UNITS); | |
14498 | ||
14499 | /* Add a score in range 0..MAX_SCHED_MIX_SCORE depending on how long | |
14500 | ago the last insn of this unit type got scheduled. This is | |
14501 | supposed to help providing a proper instruction mix to the | |
14502 | CPU. */ | |
14503 | for (i = 0; i < units; i++, m <<= 1) | |
14504 | if (m & unit_mask) | |
14505 | score += (last_scheduled_unit_distance[i] * MAX_SCHED_MIX_SCORE / | |
14506 | MAX_SCHED_MIX_DISTANCE); | |
14507 | } | |
22ac2c2f AK |
14508 | return score; |
14509 | } | |
14510 | ||
3a892e44 | 14511 | /* This function is called via hook TARGET_SCHED_REORDER before |
631b20a7 | 14512 | issuing one insn from list READY which contains *NREADYP entries. |
3a892e44 AK |
14513 | For target z10 it reorders load instructions to avoid early load |
14514 | conflicts in the floating point pipeline */ | |
14515 | static int | |
22ac2c2f | 14516 | s390_sched_reorder (FILE *file, int verbose, |
ce1ce33a | 14517 | rtx_insn **ready, int *nreadyp, int clock ATTRIBUTE_UNUSED) |
3a892e44 | 14518 | { |
bacf8ec3 DV |
14519 | if (s390_tune == PROCESSOR_2097_Z10 |
14520 | && reload_completed | |
14521 | && *nreadyp > 1) | |
14522 | s390_z10_prevent_earlyload_conflicts (ready, nreadyp); | |
3a892e44 | 14523 | |
bacf8ec3 | 14524 | if (s390_tune >= PROCESSOR_2827_ZEC12 |
22ac2c2f AK |
14525 | && reload_completed |
14526 | && *nreadyp > 1) | |
14527 | { | |
14528 | int i; | |
14529 | int last_index = *nreadyp - 1; | |
14530 | int max_index = -1; | |
14531 | int max_score = -1; | |
ce1ce33a | 14532 | rtx_insn *tmp; |
22ac2c2f AK |
14533 | |
14534 | /* Just move the insn with the highest score to the top (the | |
14535 | end) of the list. A full sort is not needed since a conflict | |
14536 | in the hazard recognition cannot happen. So the top insn in | |
14537 | the ready list will always be taken. */ | |
14538 | for (i = last_index; i >= 0; i--) | |
14539 | { | |
14540 | int score; | |
14541 | ||
14542 | if (recog_memoized (ready[i]) < 0) | |
14543 | continue; | |
14544 | ||
14545 | score = s390_sched_score (ready[i]); | |
14546 | if (score > max_score) | |
14547 | { | |
14548 | max_score = score; | |
14549 | max_index = i; | |
14550 | } | |
14551 | } | |
14552 | ||
14553 | if (max_index != -1) | |
14554 | { | |
14555 | if (max_index != last_index) | |
14556 | { | |
14557 | tmp = ready[max_index]; | |
14558 | ready[max_index] = ready[last_index]; | |
14559 | ready[last_index] = tmp; | |
14560 | ||
14561 | if (verbose > 5) | |
14562 | fprintf (file, | |
23902021 | 14563 | ";;\t\tBACKEND: move insn %d to the top of list\n", |
22ac2c2f AK |
14564 | INSN_UID (ready[last_index])); |
14565 | } | |
14566 | else if (verbose > 5) | |
14567 | fprintf (file, | |
23902021 | 14568 | ";;\t\tBACKEND: best insn %d already on top\n", |
22ac2c2f AK |
14569 | INSN_UID (ready[last_index])); |
14570 | } | |
14571 | ||
14572 | if (verbose > 5) | |
14573 | { | |
14574 | fprintf (file, "ready list ooo attributes - sched state: %d\n", | |
14575 | s390_sched_state); | |
14576 | ||
14577 | for (i = last_index; i >= 0; i--) | |
14578 | { | |
23902021 AK |
14579 | unsigned int sched_mask; |
14580 | rtx_insn *insn = ready[i]; | |
14581 | ||
14582 | if (recog_memoized (insn) < 0) | |
22ac2c2f | 14583 | continue; |
23902021 AK |
14584 | |
14585 | sched_mask = s390_get_sched_attrmask (insn); | |
14586 | fprintf (file, ";;\t\tBACKEND: insn %d score: %d: ", | |
14587 | INSN_UID (insn), | |
14588 | s390_sched_score (insn)); | |
14589 | #define PRINT_SCHED_ATTR(M, ATTR) fprintf (file, "%s ",\ | |
14590 | ((M) & sched_mask) ? #ATTR : ""); | |
14591 | PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_CRACKED, cracked); | |
14592 | PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_EXPANDED, expanded); | |
14593 | PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_ENDGROUP, endgroup); | |
14594 | PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_GROUPALONE, groupalone); | |
14595 | #undef PRINT_SCHED_ATTR | |
6654e96f | 14596 | if (s390_tune >= PROCESSOR_2964_Z13) |
23902021 AK |
14597 | { |
14598 | unsigned int unit_mask, m = 1; | |
14599 | int units, j; | |
14600 | ||
14601 | unit_mask = s390_get_unit_mask (insn, &units); | |
14602 | fprintf (file, "(units:"); | |
14603 | for (j = 0; j < units; j++, m <<= 1) | |
14604 | if (m & unit_mask) | |
14605 | fprintf (file, " u%d", j); | |
14606 | fprintf (file, ")"); | |
14607 | } | |
22ac2c2f AK |
14608 | fprintf (file, "\n"); |
14609 | } | |
14610 | } | |
14611 | } | |
14612 | ||
3a892e44 AK |
14613 | return s390_issue_rate (); |
14614 | } | |
14615 | ||
22ac2c2f | 14616 | |
3a892e44 AK |
14617 | /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after |
14618 | the scheduler has issued INSN. It stores the last issued insn into | |
14619 | last_scheduled_insn in order to make it available for | |
14620 | s390_sched_reorder. */ | |
14621 | static int | |
ac44248e | 14622 | s390_sched_variable_issue (FILE *file, int verbose, rtx_insn *insn, int more) |
3a892e44 AK |
14623 | { |
14624 | last_scheduled_insn = insn; | |
14625 | ||
bacf8ec3 | 14626 | if (s390_tune >= PROCESSOR_2827_ZEC12 |
22ac2c2f AK |
14627 | && reload_completed |
14628 | && recog_memoized (insn) >= 0) | |
14629 | { | |
14630 | unsigned int mask = s390_get_sched_attrmask (insn); | |
14631 | ||
23902021 AK |
14632 | if ((mask & S390_SCHED_ATTR_MASK_CRACKED) != 0 |
14633 | || (mask & S390_SCHED_ATTR_MASK_EXPANDED) != 0) | |
14634 | s390_sched_state = S390_SCHED_STATE_CRACKED; | |
14635 | else if ((mask & S390_SCHED_ATTR_MASK_ENDGROUP) != 0 | |
14636 | || (mask & S390_SCHED_ATTR_MASK_GROUPALONE) != 0) | |
14637 | s390_sched_state = S390_SCHED_STATE_NORMAL; | |
22ac2c2f AK |
14638 | else |
14639 | { | |
14640 | /* Only normal insns are left (mask == 0). */ | |
14641 | switch (s390_sched_state) | |
14642 | { | |
14643 | case 0: | |
14644 | case 1: | |
14645 | case 2: | |
23902021 AK |
14646 | case S390_SCHED_STATE_NORMAL: |
14647 | if (s390_sched_state == S390_SCHED_STATE_NORMAL) | |
22ac2c2f AK |
14648 | s390_sched_state = 1; |
14649 | else | |
14650 | s390_sched_state++; | |
14651 | ||
14652 | break; | |
23902021 AK |
14653 | case S390_SCHED_STATE_CRACKED: |
14654 | s390_sched_state = S390_SCHED_STATE_NORMAL; | |
22ac2c2f AK |
14655 | break; |
14656 | } | |
14657 | } | |
23902021 | 14658 | |
6654e96f | 14659 | if (s390_tune >= PROCESSOR_2964_Z13) |
23902021 AK |
14660 | { |
14661 | int units, i; | |
14662 | unsigned unit_mask, m = 1; | |
14663 | ||
14664 | unit_mask = s390_get_unit_mask (insn, &units); | |
14665 | gcc_assert (units <= MAX_SCHED_UNITS); | |
14666 | ||
14667 | for (i = 0; i < units; i++, m <<= 1) | |
14668 | if (m & unit_mask) | |
14669 | last_scheduled_unit_distance[i] = 0; | |
14670 | else if (last_scheduled_unit_distance[i] < MAX_SCHED_MIX_DISTANCE) | |
14671 | last_scheduled_unit_distance[i]++; | |
14672 | } | |
14673 | ||
22ac2c2f AK |
14674 | if (verbose > 5) |
14675 | { | |
23902021 AK |
14676 | unsigned int sched_mask; |
14677 | ||
14678 | sched_mask = s390_get_sched_attrmask (insn); | |
14679 | ||
14680 | fprintf (file, ";;\t\tBACKEND: insn %d: ", INSN_UID (insn)); | |
14681 | #define PRINT_SCHED_ATTR(M, ATTR) fprintf (file, "%s ", ((M) & sched_mask) ? #ATTR : ""); | |
14682 | PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_CRACKED, cracked); | |
14683 | PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_EXPANDED, expanded); | |
14684 | PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_ENDGROUP, endgroup); | |
14685 | PRINT_SCHED_ATTR (S390_SCHED_ATTR_MASK_GROUPALONE, groupalone); | |
14686 | #undef PRINT_SCHED_ATTR | |
14687 | ||
6654e96f | 14688 | if (s390_tune >= PROCESSOR_2964_Z13) |
23902021 AK |
14689 | { |
14690 | unsigned int unit_mask, m = 1; | |
14691 | int units, j; | |
14692 | ||
14693 | unit_mask = s390_get_unit_mask (insn, &units); | |
14694 | fprintf (file, "(units:"); | |
14695 | for (j = 0; j < units; j++, m <<= 1) | |
14696 | if (m & unit_mask) | |
14697 | fprintf (file, " %d", j); | |
14698 | fprintf (file, ")"); | |
14699 | } | |
14700 | fprintf (file, " sched state: %d\n", s390_sched_state); | |
14701 | ||
6654e96f | 14702 | if (s390_tune >= PROCESSOR_2964_Z13) |
23902021 AK |
14703 | { |
14704 | int units, j; | |
14705 | ||
14706 | s390_get_unit_mask (insn, &units); | |
14707 | ||
14708 | fprintf (file, ";;\t\tBACKEND: units unused for: "); | |
14709 | for (j = 0; j < units; j++) | |
14710 | fprintf (file, "%d:%d ", j, last_scheduled_unit_distance[j]); | |
14711 | fprintf (file, "\n"); | |
14712 | } | |
22ac2c2f AK |
14713 | } |
14714 | } | |
14715 | ||
3a892e44 AK |
14716 | if (GET_CODE (PATTERN (insn)) != USE |
14717 | && GET_CODE (PATTERN (insn)) != CLOBBER) | |
14718 | return more - 1; | |
14719 | else | |
14720 | return more; | |
14721 | } | |
ed9676cf | 14722 | |
244e6c5c AK |
14723 | static void |
14724 | s390_sched_init (FILE *file ATTRIBUTE_UNUSED, | |
14725 | int verbose ATTRIBUTE_UNUSED, | |
14726 | int max_ready ATTRIBUTE_UNUSED) | |
14727 | { | |
775c43d3 | 14728 | last_scheduled_insn = NULL; |
23902021 | 14729 | memset (last_scheduled_unit_distance, 0, MAX_SCHED_UNITS * sizeof (int)); |
22ac2c2f | 14730 | s390_sched_state = 0; |
244e6c5c AK |
14731 | } |
14732 | ||
40ac4f73 | 14733 | /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates |
65b1d8ea AK |
14734 | a new number struct loop *loop should be unrolled if tuned for cpus with |
14735 | a built-in stride prefetcher. | |
14736 | The loop is analyzed for memory accesses by calling check_dpu for | |
40ac4f73 CB |
14737 | each rtx of the loop. Depending on the loop_depth and the amount of |
14738 | memory accesses a new number <=nunroll is returned to improve the | |
9c582551 | 14739 | behavior of the hardware prefetch unit. */ |
40ac4f73 CB |
14740 | static unsigned |
14741 | s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop) | |
14742 | { | |
14743 | basic_block *bbs; | |
775c43d3 | 14744 | rtx_insn *insn; |
40ac4f73 CB |
14745 | unsigned i; |
14746 | unsigned mem_count = 0; | |
14747 | ||
bacf8ec3 | 14748 | if (s390_tune < PROCESSOR_2097_Z10) |
40ac4f73 CB |
14749 | return nunroll; |
14750 | ||
14751 | /* Count the number of memory references within the loop body. */ | |
14752 | bbs = get_loop_body (loop); | |
9dc7a9da | 14753 | subrtx_iterator::array_type array; |
40ac4f73 | 14754 | for (i = 0; i < loop->num_nodes; i++) |
9dc7a9da RS |
14755 | FOR_BB_INSNS (bbs[i], insn) |
14756 | if (INSN_P (insn) && INSN_CODE (insn) != -1) | |
14757 | FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST) | |
14758 | if (MEM_P (*iter)) | |
14759 | mem_count += 1; | |
40ac4f73 CB |
14760 | free (bbs); |
14761 | ||
14762 | /* Prevent division by zero, and we do not need to adjust nunroll in this case. */ | |
14763 | if (mem_count == 0) | |
14764 | return nunroll; | |
14765 | ||
14766 | switch (loop_depth(loop)) | |
14767 | { | |
14768 | case 1: | |
14769 | return MIN (nunroll, 28 / mem_count); | |
14770 | case 2: | |
14771 | return MIN (nunroll, 22 / mem_count); | |
14772 | default: | |
14773 | return MIN (nunroll, 16 / mem_count); | |
14774 | } | |
14775 | } | |
14776 | ||
ec47b086 DV |
14777 | /* Restore the current options. This is a hook function and also called |
14778 | internally. */ | |
14779 | ||
4099494d | 14780 | static void |
ec47b086 DV |
14781 | s390_function_specific_restore (struct gcc_options *opts, |
14782 | struct cl_target_option *ptr ATTRIBUTE_UNUSED) | |
4099494d | 14783 | { |
ec47b086 DV |
14784 | opts->x_s390_cost_pointer = (long)processor_table[opts->x_s390_tune].cost; |
14785 | } | |
4099494d | 14786 | |
ec47b086 | 14787 | static void |
6638efce AK |
14788 | s390_option_override_internal (bool main_args_p, |
14789 | struct gcc_options *opts, | |
ec47b086 DV |
14790 | const struct gcc_options *opts_set) |
14791 | { | |
6638efce AK |
14792 | const char *prefix; |
14793 | const char *suffix; | |
14794 | ||
14795 | /* Set up prefix/suffix so the error messages refer to either the command | |
14796 | line argument, or the attribute(target). */ | |
14797 | if (main_args_p) | |
14798 | { | |
14799 | prefix = "-m"; | |
14800 | suffix = ""; | |
14801 | } | |
14802 | else | |
14803 | { | |
14804 | prefix = "option(\""; | |
14805 | suffix = "\")"; | |
14806 | } | |
14807 | ||
14808 | ||
4099494d | 14809 | /* Architecture mode defaults according to ABI. */ |
ec47b086 | 14810 | if (!(opts_set->x_target_flags & MASK_ZARCH)) |
4099494d RS |
14811 | { |
14812 | if (TARGET_64BIT) | |
ec47b086 | 14813 | opts->x_target_flags |= MASK_ZARCH; |
4099494d | 14814 | else |
ec47b086 | 14815 | opts->x_target_flags &= ~MASK_ZARCH; |
4099494d RS |
14816 | } |
14817 | ||
ec47b086 DV |
14818 | /* Set the march default in case it hasn't been specified on cmdline. */ |
14819 | if (!opts_set->x_s390_arch) | |
6638efce AK |
14820 | opts->x_s390_arch = PROCESSOR_2064_Z900; |
14821 | else if (opts->x_s390_arch == PROCESSOR_9672_G5 | |
14822 | || opts->x_s390_arch == PROCESSOR_9672_G6) | |
14823 | warning (OPT_Wdeprecated, "%sarch=%s%s is deprecated and will be removed " | |
14824 | "in future releases; use at least %sarch=z900%s", | |
14825 | prefix, opts->x_s390_arch == PROCESSOR_9672_G5 ? "g5" : "g6", | |
14826 | suffix, prefix, suffix); | |
14827 | ||
ec47b086 | 14828 | opts->x_s390_arch_flags = processor_flags_table[(int) opts->x_s390_arch]; |
4099494d RS |
14829 | |
14830 | /* Determine processor to tune for. */ | |
ec47b086 DV |
14831 | if (!opts_set->x_s390_tune) |
14832 | opts->x_s390_tune = opts->x_s390_arch; | |
6638efce AK |
14833 | else if (opts->x_s390_tune == PROCESSOR_9672_G5 |
14834 | || opts->x_s390_tune == PROCESSOR_9672_G6) | |
14835 | warning (OPT_Wdeprecated, "%stune=%s%s is deprecated and will be removed " | |
14836 | "in future releases; use at least %stune=z900%s", | |
14837 | prefix, opts->x_s390_tune == PROCESSOR_9672_G5 ? "g5" : "g6", | |
14838 | suffix, prefix, suffix); | |
14839 | ||
ec47b086 | 14840 | opts->x_s390_tune_flags = processor_flags_table[opts->x_s390_tune]; |
4099494d RS |
14841 | |
14842 | /* Sanity checks. */ | |
ec47b086 DV |
14843 | if (opts->x_s390_arch == PROCESSOR_NATIVE |
14844 | || opts->x_s390_tune == PROCESSOR_NATIVE) | |
cb0edc39 | 14845 | gcc_unreachable (); |
ec47b086 DV |
14846 | if (TARGET_ZARCH_P (opts->x_target_flags) && !TARGET_CPU_ZARCH_P (opts)) |
14847 | error ("z/Architecture mode not supported on %s", | |
14848 | processor_table[(int)opts->x_s390_arch].name); | |
14849 | if (TARGET_64BIT && !TARGET_ZARCH_P (opts->x_target_flags)) | |
4099494d RS |
14850 | error ("64-bit ABI not supported in ESA/390 mode"); |
14851 | ||
4099494d RS |
14852 | /* Enable hardware transactions if available and not explicitly |
14853 | disabled by user. E.g. with -m31 -march=zEC12 -mzarch */ | |
ec47b086 DV |
14854 | if (!TARGET_OPT_HTM_P (opts_set->x_target_flags)) |
14855 | { | |
14856 | if (TARGET_CPU_HTM_P (opts) && TARGET_ZARCH_P (opts->x_target_flags)) | |
14857 | opts->x_target_flags |= MASK_OPT_HTM; | |
14858 | else | |
14859 | opts->x_target_flags &= ~MASK_OPT_HTM; | |
14860 | } | |
4099494d | 14861 | |
ec47b086 | 14862 | if (TARGET_OPT_VX_P (opts_set->x_target_flags)) |
55ac540c | 14863 | { |
ec47b086 | 14864 | if (TARGET_OPT_VX_P (opts->x_target_flags)) |
55ac540c | 14865 | { |
ec47b086 | 14866 | if (!TARGET_CPU_VX_P (opts)) |
55ac540c | 14867 | error ("hardware vector support not available on %s", |
ec47b086 DV |
14868 | processor_table[(int)opts->x_s390_arch].name); |
14869 | if (TARGET_SOFT_FLOAT_P (opts->x_target_flags)) | |
55ac540c AK |
14870 | error ("hardware vector support not available with -msoft-float"); |
14871 | } | |
14872 | } | |
ec47b086 DV |
14873 | else |
14874 | { | |
14875 | if (TARGET_CPU_VX_P (opts)) | |
14876 | /* Enable vector support if available and not explicitly disabled | |
14877 | by user. E.g. with -m31 -march=z13 -mzarch */ | |
14878 | opts->x_target_flags |= MASK_OPT_VX; | |
14879 | else | |
14880 | opts->x_target_flags &= ~MASK_OPT_VX; | |
14881 | } | |
55ac540c | 14882 | |
ec47b086 DV |
14883 | /* Use hardware DFP if available and not explicitly disabled by |
14884 | user. E.g. with -m31 -march=z10 -mzarch */ | |
14885 | if (!TARGET_HARD_DFP_P (opts_set->x_target_flags)) | |
14886 | { | |
14887 | if (TARGET_DFP_P (opts)) | |
14888 | opts->x_target_flags |= MASK_HARD_DFP; | |
14889 | else | |
14890 | opts->x_target_flags &= ~MASK_HARD_DFP; | |
14891 | } | |
14892 | ||
14893 | if (TARGET_HARD_DFP_P (opts->x_target_flags) && !TARGET_DFP_P (opts)) | |
4099494d | 14894 | { |
ec47b086 | 14895 | if (TARGET_HARD_DFP_P (opts_set->x_target_flags)) |
4099494d | 14896 | { |
ec47b086 | 14897 | if (!TARGET_CPU_DFP_P (opts)) |
4099494d | 14898 | error ("hardware decimal floating point instructions" |
ec47b086 DV |
14899 | " not available on %s", |
14900 | processor_table[(int)opts->x_s390_arch].name); | |
14901 | if (!TARGET_ZARCH_P (opts->x_target_flags)) | |
4099494d RS |
14902 | error ("hardware decimal floating point instructions" |
14903 | " not available in ESA/390 mode"); | |
14904 | } | |
14905 | else | |
ec47b086 | 14906 | opts->x_target_flags &= ~MASK_HARD_DFP; |
4099494d RS |
14907 | } |
14908 | ||
ec47b086 DV |
14909 | if (TARGET_SOFT_FLOAT_P (opts_set->x_target_flags) |
14910 | && TARGET_SOFT_FLOAT_P (opts->x_target_flags)) | |
4099494d | 14911 | { |
ec47b086 DV |
14912 | if (TARGET_HARD_DFP_P (opts_set->x_target_flags) |
14913 | && TARGET_HARD_DFP_P (opts->x_target_flags)) | |
4099494d RS |
14914 | error ("-mhard-dfp can%'t be used in conjunction with -msoft-float"); |
14915 | ||
ec47b086 | 14916 | opts->x_target_flags &= ~MASK_HARD_DFP; |
4099494d RS |
14917 | } |
14918 | ||
ec47b086 DV |
14919 | if (TARGET_BACKCHAIN_P (opts->x_target_flags) |
14920 | && TARGET_PACKED_STACK_P (opts->x_target_flags) | |
14921 | && TARGET_HARD_FLOAT_P (opts->x_target_flags)) | |
4099494d RS |
14922 | error ("-mbackchain -mpacked-stack -mhard-float are not supported " |
14923 | "in combination"); | |
14924 | ||
ec47b086 | 14925 | if (opts->x_s390_stack_size) |
4099494d | 14926 | { |
ec47b086 | 14927 | if (opts->x_s390_stack_guard >= opts->x_s390_stack_size) |
4099494d | 14928 | error ("stack size must be greater than the stack guard value"); |
ec47b086 | 14929 | else if (opts->x_s390_stack_size > 1 << 16) |
4099494d RS |
14930 | error ("stack size must not be greater than 64k"); |
14931 | } | |
ec47b086 | 14932 | else if (opts->x_s390_stack_guard) |
4099494d RS |
14933 | error ("-mstack-guard implies use of -mstack-size"); |
14934 | ||
14935 | #ifdef TARGET_DEFAULT_LONG_DOUBLE_128 | |
ec47b086 DV |
14936 | if (!TARGET_LONG_DOUBLE_128_P (opts_set->x_target_flags)) |
14937 | opts->x_target_flags |= MASK_LONG_DOUBLE_128; | |
4099494d RS |
14938 | #endif |
14939 | ||
ec47b086 | 14940 | if (opts->x_s390_tune >= PROCESSOR_2097_Z10) |
4099494d RS |
14941 | { |
14942 | maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100, | |
ec47b086 DV |
14943 | opts->x_param_values, |
14944 | opts_set->x_param_values); | |
4099494d | 14945 | maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32, |
ec47b086 DV |
14946 | opts->x_param_values, |
14947 | opts_set->x_param_values); | |
4099494d | 14948 | maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000, |
ec47b086 DV |
14949 | opts->x_param_values, |
14950 | opts_set->x_param_values); | |
4099494d | 14951 | maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64, |
ec47b086 DV |
14952 | opts->x_param_values, |
14953 | opts_set->x_param_values); | |
4099494d RS |
14954 | } |
14955 | ||
14956 | maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256, | |
ec47b086 DV |
14957 | opts->x_param_values, |
14958 | opts_set->x_param_values); | |
4099494d RS |
14959 | /* values for loop prefetching */ |
14960 | maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256, | |
ec47b086 DV |
14961 | opts->x_param_values, |
14962 | opts_set->x_param_values); | |
4099494d | 14963 | maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128, |
ec47b086 DV |
14964 | opts->x_param_values, |
14965 | opts_set->x_param_values); | |
4099494d RS |
14966 | /* s390 has more than 2 levels and the size is much larger. Since |
14967 | we are always running virtualized assume that we only get a small | |
14968 | part of the caches above l1. */ | |
14969 | maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500, | |
ec47b086 DV |
14970 | opts->x_param_values, |
14971 | opts_set->x_param_values); | |
4099494d | 14972 | maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2, |
ec47b086 DV |
14973 | opts->x_param_values, |
14974 | opts_set->x_param_values); | |
4099494d | 14975 | maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6, |
ec47b086 DV |
14976 | opts->x_param_values, |
14977 | opts_set->x_param_values); | |
14978 | ||
14979 | /* Use the alternative scheduling-pressure algorithm by default. */ | |
14980 | maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, 2, | |
14981 | opts->x_param_values, | |
14982 | opts_set->x_param_values); | |
14983 | ||
6cc61b5a RD |
14984 | maybe_set_param_value (PARAM_MIN_VECT_LOOP_BOUND, 2, |
14985 | opts->x_param_values, | |
14986 | opts_set->x_param_values); | |
14987 | ||
ec47b086 DV |
14988 | /* Call target specific restore function to do post-init work. At the moment, |
14989 | this just sets opts->x_s390_cost_pointer. */ | |
14990 | s390_function_specific_restore (opts, NULL); | |
14991 | } | |
14992 | ||
14993 | static void | |
14994 | s390_option_override (void) | |
14995 | { | |
14996 | unsigned int i; | |
14997 | cl_deferred_option *opt; | |
14998 | vec<cl_deferred_option> *v = | |
14999 | (vec<cl_deferred_option> *) s390_deferred_options; | |
15000 | ||
15001 | if (v) | |
15002 | FOR_EACH_VEC_ELT (*v, i, opt) | |
15003 | { | |
15004 | switch (opt->opt_index) | |
15005 | { | |
15006 | case OPT_mhotpatch_: | |
15007 | { | |
15008 | int val1; | |
15009 | int val2; | |
15010 | char s[256]; | |
15011 | char *t; | |
15012 | ||
15013 | strncpy (s, opt->arg, 256); | |
15014 | s[255] = 0; | |
15015 | t = strchr (s, ','); | |
15016 | if (t != NULL) | |
15017 | { | |
15018 | *t = 0; | |
15019 | t++; | |
15020 | val1 = integral_argument (s); | |
15021 | val2 = integral_argument (t); | |
15022 | } | |
15023 | else | |
15024 | { | |
15025 | val1 = -1; | |
15026 | val2 = -1; | |
15027 | } | |
15028 | if (val1 == -1 || val2 == -1) | |
15029 | { | |
15030 | /* argument is not a plain number */ | |
15031 | error ("arguments to %qs should be non-negative integers", | |
15032 | "-mhotpatch=n,m"); | |
15033 | break; | |
15034 | } | |
15035 | else if (val1 > s390_hotpatch_hw_max | |
15036 | || val2 > s390_hotpatch_hw_max) | |
15037 | { | |
15038 | error ("argument to %qs is too large (max. %d)", | |
15039 | "-mhotpatch=n,m", s390_hotpatch_hw_max); | |
15040 | break; | |
15041 | } | |
15042 | s390_hotpatch_hw_before_label = val1; | |
15043 | s390_hotpatch_hw_after_label = val2; | |
15044 | break; | |
15045 | } | |
15046 | default: | |
15047 | gcc_unreachable (); | |
15048 | } | |
15049 | } | |
15050 | ||
15051 | /* Set up function hooks. */ | |
15052 | init_machine_status = s390_init_machine_status; | |
15053 | ||
6638efce | 15054 | s390_option_override_internal (true, &global_options, &global_options_set); |
ec47b086 DV |
15055 | |
15056 | /* Save the initial options in case the user does function specific | |
15057 | options. */ | |
15058 | target_option_default_node = build_target_option_node (&global_options); | |
15059 | target_option_current_node = target_option_default_node; | |
4099494d RS |
15060 | |
15061 | /* This cannot reside in s390_option_optimization_table since HAVE_prefetch | |
15062 | requires the arch flags to be evaluated already. Since prefetching | |
15063 | is beneficial on s390, we enable it if available. */ | |
15064 | if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3) | |
15065 | flag_prefetch_loop_arrays = 1; | |
15066 | ||
935b5226 AK |
15067 | if (!s390_pic_data_is_text_relative && !flag_pic) |
15068 | error ("-mno-pic-data-is-text-relative cannot be used without -fpic/-fPIC"); | |
15069 | ||
4099494d RS |
15070 | if (TARGET_TPF) |
15071 | { | |
15072 | /* Don't emit DWARF3/4 unless specifically selected. The TPF | |
15073 | debuggers do not yet support DWARF 3/4. */ | |
15074 | if (!global_options_set.x_dwarf_strict) | |
15075 | dwarf_strict = 1; | |
15076 | if (!global_options_set.x_dwarf_version) | |
15077 | dwarf_version = 2; | |
15078 | } | |
15079 | ||
15080 | /* Register a target-specific optimization-and-lowering pass | |
15081 | to run immediately before prologue and epilogue generation. | |
15082 | ||
15083 | Registering the pass must be done at start up. It's | |
15084 | convenient to do it here. */ | |
15085 | opt_pass *new_pass = new pass_s390_early_mach (g); | |
15086 | struct register_pass_info insert_pass_s390_early_mach = | |
15087 | { | |
15088 | new_pass, /* pass */ | |
15089 | "pro_and_epilogue", /* reference_pass_name */ | |
15090 | 1, /* ref_pass_instance_number */ | |
15091 | PASS_POS_INSERT_BEFORE /* po_op */ | |
15092 | }; | |
15093 | register_pass (&insert_pass_s390_early_mach); | |
15094 | } | |
15095 | ||
ec47b086 DV |
15096 | #if S390_USE_TARGET_ATTRIBUTE |
15097 | /* Inner function to process the attribute((target(...))), take an argument and | |
15098 | set the current options from the argument. If we have a list, recursively go | |
15099 | over the list. */ | |
15100 | ||
15101 | static bool | |
15102 | s390_valid_target_attribute_inner_p (tree args, | |
15103 | struct gcc_options *opts, | |
15104 | struct gcc_options *new_opts_set, | |
15105 | bool force_pragma) | |
15106 | { | |
15107 | char *next_optstr; | |
15108 | bool ret = true; | |
15109 | ||
15110 | #define S390_ATTRIB(S,O,A) { S, sizeof (S)-1, O, A, 0 } | |
15111 | #define S390_PRAGMA(S,O,A) { S, sizeof (S)-1, O, A, 1 } | |
15112 | static const struct | |
15113 | { | |
15114 | const char *string; | |
15115 | size_t len; | |
15116 | int opt; | |
15117 | int has_arg; | |
15118 | int only_as_pragma; | |
15119 | } attrs[] = { | |
15120 | /* enum options */ | |
15121 | S390_ATTRIB ("arch=", OPT_march_, 1), | |
15122 | S390_ATTRIB ("tune=", OPT_mtune_, 1), | |
15123 | /* uinteger options */ | |
15124 | S390_ATTRIB ("stack-guard=", OPT_mstack_guard_, 1), | |
15125 | S390_ATTRIB ("stack-size=", OPT_mstack_size_, 1), | |
15126 | S390_ATTRIB ("branch-cost=", OPT_mbranch_cost_, 1), | |
15127 | S390_ATTRIB ("warn-framesize=", OPT_mwarn_framesize_, 1), | |
15128 | /* flag options */ | |
15129 | S390_ATTRIB ("backchain", OPT_mbackchain, 0), | |
15130 | S390_ATTRIB ("hard-dfp", OPT_mhard_dfp, 0), | |
15131 | S390_ATTRIB ("hard-float", OPT_mhard_float, 0), | |
15132 | S390_ATTRIB ("htm", OPT_mhtm, 0), | |
15133 | S390_ATTRIB ("vx", OPT_mvx, 0), | |
15134 | S390_ATTRIB ("packed-stack", OPT_mpacked_stack, 0), | |
15135 | S390_ATTRIB ("small-exec", OPT_msmall_exec, 0), | |
15136 | S390_ATTRIB ("soft-float", OPT_msoft_float, 0), | |
15137 | S390_ATTRIB ("mvcle", OPT_mmvcle, 0), | |
15138 | S390_PRAGMA ("zvector", OPT_mzvector, 0), | |
15139 | /* boolean options */ | |
15140 | S390_ATTRIB ("warn-dynamicstack", OPT_mwarn_dynamicstack, 0), | |
15141 | }; | |
15142 | #undef S390_ATTRIB | |
15143 | #undef S390_PRAGMA | |
15144 | ||
15145 | /* If this is a list, recurse to get the options. */ | |
15146 | if (TREE_CODE (args) == TREE_LIST) | |
15147 | { | |
15148 | bool ret = true; | |
15149 | int num_pragma_values; | |
15150 | int i; | |
15151 | ||
15152 | /* Note: attribs.c:decl_attributes prepends the values from | |
15153 | current_target_pragma to the list of target attributes. To determine | |
15154 | whether we're looking at a value of the attribute or the pragma we | |
15155 | assume that the first [list_length (current_target_pragma)] values in | |
15156 | the list are the values from the pragma. */ | |
15157 | num_pragma_values = (!force_pragma && current_target_pragma != NULL) | |
15158 | ? list_length (current_target_pragma) : 0; | |
15159 | for (i = 0; args; args = TREE_CHAIN (args), i++) | |
15160 | { | |
15161 | bool is_pragma; | |
15162 | ||
15163 | is_pragma = (force_pragma || i < num_pragma_values); | |
15164 | if (TREE_VALUE (args) | |
15165 | && !s390_valid_target_attribute_inner_p (TREE_VALUE (args), | |
15166 | opts, new_opts_set, | |
15167 | is_pragma)) | |
15168 | { | |
15169 | ret = false; | |
15170 | } | |
15171 | } | |
15172 | return ret; | |
15173 | } | |
15174 | ||
15175 | else if (TREE_CODE (args) != STRING_CST) | |
15176 | { | |
15177 | error ("attribute %<target%> argument not a string"); | |
15178 | return false; | |
15179 | } | |
15180 | ||
15181 | /* Handle multiple arguments separated by commas. */ | |
15182 | next_optstr = ASTRDUP (TREE_STRING_POINTER (args)); | |
15183 | ||
15184 | while (next_optstr && *next_optstr != '\0') | |
15185 | { | |
15186 | char *p = next_optstr; | |
15187 | char *orig_p = p; | |
15188 | char *comma = strchr (next_optstr, ','); | |
15189 | size_t len, opt_len; | |
15190 | int opt; | |
15191 | bool opt_set_p; | |
15192 | char ch; | |
15193 | unsigned i; | |
15194 | int mask = 0; | |
15195 | enum cl_var_type var_type; | |
15196 | bool found; | |
15197 | ||
15198 | if (comma) | |
15199 | { | |
15200 | *comma = '\0'; | |
15201 | len = comma - next_optstr; | |
15202 | next_optstr = comma + 1; | |
15203 | } | |
15204 | else | |
15205 | { | |
15206 | len = strlen (p); | |
15207 | next_optstr = NULL; | |
15208 | } | |
15209 | ||
15210 | /* Recognize no-xxx. */ | |
15211 | if (len > 3 && p[0] == 'n' && p[1] == 'o' && p[2] == '-') | |
15212 | { | |
15213 | opt_set_p = false; | |
15214 | p += 3; | |
15215 | len -= 3; | |
15216 | } | |
15217 | else | |
15218 | opt_set_p = true; | |
15219 | ||
15220 | /* Find the option. */ | |
15221 | ch = *p; | |
15222 | found = false; | |
15223 | for (i = 0; i < ARRAY_SIZE (attrs); i++) | |
15224 | { | |
15225 | opt_len = attrs[i].len; | |
15226 | if (ch == attrs[i].string[0] | |
15227 | && ((attrs[i].has_arg) ? len > opt_len : len == opt_len) | |
15228 | && memcmp (p, attrs[i].string, opt_len) == 0) | |
15229 | { | |
15230 | opt = attrs[i].opt; | |
15231 | if (!opt_set_p && cl_options[opt].cl_reject_negative) | |
15232 | continue; | |
15233 | mask = cl_options[opt].var_value; | |
15234 | var_type = cl_options[opt].var_type; | |
15235 | found = true; | |
15236 | break; | |
15237 | } | |
15238 | } | |
15239 | ||
15240 | /* Process the option. */ | |
15241 | if (!found) | |
15242 | { | |
15243 | error ("attribute(target(\"%s\")) is unknown", orig_p); | |
15244 | return false; | |
15245 | } | |
15246 | else if (attrs[i].only_as_pragma && !force_pragma) | |
15247 | { | |
15248 | /* Value is not allowed for the target attribute. */ | |
f3981e7e | 15249 | error ("value %qs is not supported by attribute %<target%>", |
ec47b086 DV |
15250 | attrs[i].string); |
15251 | return false; | |
15252 | } | |
15253 | ||
15254 | else if (var_type == CLVC_BIT_SET || var_type == CLVC_BIT_CLEAR) | |
15255 | { | |
15256 | if (var_type == CLVC_BIT_CLEAR) | |
15257 | opt_set_p = !opt_set_p; | |
15258 | ||
15259 | if (opt_set_p) | |
15260 | opts->x_target_flags |= mask; | |
15261 | else | |
15262 | opts->x_target_flags &= ~mask; | |
15263 | new_opts_set->x_target_flags |= mask; | |
15264 | } | |
15265 | ||
15266 | else if (cl_options[opt].var_type == CLVC_BOOLEAN) | |
15267 | { | |
15268 | int value; | |
15269 | ||
15270 | if (cl_options[opt].cl_uinteger) | |
15271 | { | |
15272 | /* Unsigned integer argument. Code based on the function | |
15273 | decode_cmdline_option () in opts-common.c. */ | |
15274 | value = integral_argument (p + opt_len); | |
15275 | } | |
15276 | else | |
15277 | value = (opt_set_p) ? 1 : 0; | |
15278 | ||
15279 | if (value != -1) | |
15280 | { | |
15281 | struct cl_decoded_option decoded; | |
15282 | ||
15283 | /* Value range check; only implemented for numeric and boolean | |
15284 | options at the moment. */ | |
15285 | generate_option (opt, NULL, value, CL_TARGET, &decoded); | |
15286 | s390_handle_option (opts, new_opts_set, &decoded, input_location); | |
15287 | set_option (opts, new_opts_set, opt, value, | |
15288 | p + opt_len, DK_UNSPECIFIED, input_location, | |
15289 | global_dc); | |
15290 | } | |
15291 | else | |
15292 | { | |
15293 | error ("attribute(target(\"%s\")) is unknown", orig_p); | |
15294 | ret = false; | |
15295 | } | |
15296 | } | |
15297 | ||
15298 | else if (cl_options[opt].var_type == CLVC_ENUM) | |
15299 | { | |
15300 | bool arg_ok; | |
15301 | int value; | |
15302 | ||
15303 | arg_ok = opt_enum_arg_to_value (opt, p + opt_len, &value, CL_TARGET); | |
15304 | if (arg_ok) | |
15305 | set_option (opts, new_opts_set, opt, value, | |
15306 | p + opt_len, DK_UNSPECIFIED, input_location, | |
15307 | global_dc); | |
15308 | else | |
15309 | { | |
15310 | error ("attribute(target(\"%s\")) is unknown", orig_p); | |
15311 | ret = false; | |
15312 | } | |
15313 | } | |
15314 | ||
15315 | else | |
15316 | gcc_unreachable (); | |
15317 | } | |
15318 | return ret; | |
15319 | } | |
15320 | ||
15321 | /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */ | |
15322 | ||
15323 | tree | |
15324 | s390_valid_target_attribute_tree (tree args, | |
15325 | struct gcc_options *opts, | |
15326 | const struct gcc_options *opts_set, | |
15327 | bool force_pragma) | |
15328 | { | |
15329 | tree t = NULL_TREE; | |
15330 | struct gcc_options new_opts_set; | |
15331 | ||
15332 | memset (&new_opts_set, 0, sizeof (new_opts_set)); | |
15333 | ||
15334 | /* Process each of the options on the chain. */ | |
15335 | if (! s390_valid_target_attribute_inner_p (args, opts, &new_opts_set, | |
15336 | force_pragma)) | |
15337 | return error_mark_node; | |
15338 | ||
15339 | /* If some option was set (even if it has not changed), rerun | |
15340 | s390_option_override_internal, and then save the options away. */ | |
15341 | if (new_opts_set.x_target_flags | |
15342 | || new_opts_set.x_s390_arch | |
15343 | || new_opts_set.x_s390_tune | |
15344 | || new_opts_set.x_s390_stack_guard | |
15345 | || new_opts_set.x_s390_stack_size | |
15346 | || new_opts_set.x_s390_branch_cost | |
15347 | || new_opts_set.x_s390_warn_framesize | |
15348 | || new_opts_set.x_s390_warn_dynamicstack_p) | |
15349 | { | |
15350 | const unsigned char *src = (const unsigned char *)opts_set; | |
15351 | unsigned char *dest = (unsigned char *)&new_opts_set; | |
15352 | unsigned int i; | |
15353 | ||
15354 | /* Merge the original option flags into the new ones. */ | |
15355 | for (i = 0; i < sizeof(*opts_set); i++) | |
15356 | dest[i] |= src[i]; | |
15357 | ||
15358 | /* Do any overrides, such as arch=xxx, or tune=xxx support. */ | |
6638efce | 15359 | s390_option_override_internal (false, opts, &new_opts_set); |
ec47b086 DV |
15360 | /* Save the current options unless we are validating options for |
15361 | #pragma. */ | |
15362 | t = build_target_option_node (opts); | |
15363 | } | |
15364 | return t; | |
15365 | } | |
15366 | ||
15367 | /* Hook to validate attribute((target("string"))). */ | |
15368 | ||
15369 | static bool | |
15370 | s390_valid_target_attribute_p (tree fndecl, | |
15371 | tree ARG_UNUSED (name), | |
15372 | tree args, | |
15373 | int ARG_UNUSED (flags)) | |
15374 | { | |
15375 | struct gcc_options func_options; | |
15376 | tree new_target, new_optimize; | |
15377 | bool ret = true; | |
15378 | ||
15379 | /* attribute((target("default"))) does nothing, beyond | |
15380 | affecting multi-versioning. */ | |
15381 | if (TREE_VALUE (args) | |
15382 | && TREE_CODE (TREE_VALUE (args)) == STRING_CST | |
15383 | && TREE_CHAIN (args) == NULL_TREE | |
15384 | && strcmp (TREE_STRING_POINTER (TREE_VALUE (args)), "default") == 0) | |
15385 | return true; | |
15386 | ||
15387 | tree old_optimize = build_optimization_node (&global_options); | |
15388 | ||
15389 | /* Get the optimization options of the current function. */ | |
15390 | tree func_optimize = DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl); | |
15391 | ||
15392 | if (!func_optimize) | |
15393 | func_optimize = old_optimize; | |
15394 | ||
15395 | /* Init func_options. */ | |
15396 | memset (&func_options, 0, sizeof (func_options)); | |
15397 | init_options_struct (&func_options, NULL); | |
15398 | lang_hooks.init_options_struct (&func_options); | |
15399 | ||
15400 | cl_optimization_restore (&func_options, TREE_OPTIMIZATION (func_optimize)); | |
15401 | ||
15402 | /* Initialize func_options to the default before its target options can | |
15403 | be set. */ | |
15404 | cl_target_option_restore (&func_options, | |
15405 | TREE_TARGET_OPTION (target_option_default_node)); | |
15406 | ||
15407 | new_target = s390_valid_target_attribute_tree (args, &func_options, | |
15408 | &global_options_set, | |
15409 | (args == | |
15410 | current_target_pragma)); | |
15411 | new_optimize = build_optimization_node (&func_options); | |
15412 | if (new_target == error_mark_node) | |
15413 | ret = false; | |
15414 | else if (fndecl && new_target) | |
15415 | { | |
15416 | DECL_FUNCTION_SPECIFIC_TARGET (fndecl) = new_target; | |
15417 | if (old_optimize != new_optimize) | |
15418 | DECL_FUNCTION_SPECIFIC_OPTIMIZATION (fndecl) = new_optimize; | |
15419 | } | |
15420 | return ret; | |
15421 | } | |
15422 | ||
db6bb1ec AK |
15423 | /* Hook to determine if one function can safely inline another. */ |
15424 | ||
15425 | static bool | |
15426 | s390_can_inline_p (tree caller, tree callee) | |
15427 | { | |
15428 | tree caller_tree = DECL_FUNCTION_SPECIFIC_TARGET (caller); | |
15429 | tree callee_tree = DECL_FUNCTION_SPECIFIC_TARGET (callee); | |
15430 | ||
15431 | if (!callee_tree) | |
15432 | callee_tree = target_option_default_node; | |
15433 | if (!caller_tree) | |
15434 | caller_tree = target_option_default_node; | |
15435 | if (callee_tree == caller_tree) | |
15436 | return true; | |
15437 | ||
15438 | struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree); | |
15439 | struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree); | |
15440 | bool ret = true; | |
15441 | ||
15442 | if ((caller_opts->x_target_flags & ~(MASK_SOFT_FLOAT | MASK_HARD_DFP)) | |
15443 | != (callee_opts->x_target_flags & ~(MASK_SOFT_FLOAT | MASK_HARD_DFP))) | |
15444 | ret = false; | |
15445 | ||
15446 | /* Don't inline functions to be compiled for a more recent arch into a | |
15447 | function for an older arch. */ | |
15448 | else if (caller_opts->x_s390_arch < callee_opts->x_s390_arch) | |
15449 | ret = false; | |
15450 | ||
15451 | /* Inlining a hard float function into a soft float function is only | |
15452 | allowed if the hard float function doesn't actually make use of | |
15453 | floating point. | |
15454 | ||
15455 | We are called from FEs for multi-versioning call optimization, so | |
15456 | beware of ipa_fn_summaries not available. */ | |
15457 | else if (((TARGET_SOFT_FLOAT_P (caller_opts->x_target_flags) | |
15458 | && !TARGET_SOFT_FLOAT_P (callee_opts->x_target_flags)) | |
15459 | || (!TARGET_HARD_DFP_P (caller_opts->x_target_flags) | |
15460 | && TARGET_HARD_DFP_P (callee_opts->x_target_flags))) | |
15461 | && (! ipa_fn_summaries | |
15462 | || ipa_fn_summaries->get | |
15463 | (cgraph_node::get (callee))->fp_expressions)) | |
15464 | ret = false; | |
15465 | ||
15466 | return ret; | |
15467 | } | |
15468 | ||
ec47b086 DV |
15469 | /* Restore targets globals from NEW_TREE and invalidate s390_previous_fndecl |
15470 | cache. */ | |
15471 | ||
15472 | void | |
15473 | s390_activate_target_options (tree new_tree) | |
15474 | { | |
15475 | cl_target_option_restore (&global_options, TREE_TARGET_OPTION (new_tree)); | |
15476 | if (TREE_TARGET_GLOBALS (new_tree)) | |
15477 | restore_target_globals (TREE_TARGET_GLOBALS (new_tree)); | |
15478 | else if (new_tree == target_option_default_node) | |
15479 | restore_target_globals (&default_target_globals); | |
15480 | else | |
15481 | TREE_TARGET_GLOBALS (new_tree) = save_target_globals_default_opts (); | |
15482 | s390_previous_fndecl = NULL_TREE; | |
15483 | } | |
15484 | ||
15485 | /* Establish appropriate back-end context for processing the function | |
15486 | FNDECL. The argument might be NULL to indicate processing at top | |
15487 | level, outside of any function scope. */ | |
15488 | static void | |
15489 | s390_set_current_function (tree fndecl) | |
15490 | { | |
15491 | /* Only change the context if the function changes. This hook is called | |
15492 | several times in the course of compiling a function, and we don't want to | |
15493 | slow things down too much or call target_reinit when it isn't safe. */ | |
15494 | if (fndecl == s390_previous_fndecl) | |
15495 | return; | |
15496 | ||
15497 | tree old_tree; | |
15498 | if (s390_previous_fndecl == NULL_TREE) | |
15499 | old_tree = target_option_current_node; | |
15500 | else if (DECL_FUNCTION_SPECIFIC_TARGET (s390_previous_fndecl)) | |
15501 | old_tree = DECL_FUNCTION_SPECIFIC_TARGET (s390_previous_fndecl); | |
15502 | else | |
15503 | old_tree = target_option_default_node; | |
15504 | ||
15505 | if (fndecl == NULL_TREE) | |
15506 | { | |
15507 | if (old_tree != target_option_current_node) | |
15508 | s390_activate_target_options (target_option_current_node); | |
15509 | return; | |
15510 | } | |
15511 | ||
15512 | tree new_tree = DECL_FUNCTION_SPECIFIC_TARGET (fndecl); | |
15513 | if (new_tree == NULL_TREE) | |
15514 | new_tree = target_option_default_node; | |
15515 | ||
15516 | if (old_tree != new_tree) | |
15517 | s390_activate_target_options (new_tree); | |
15518 | s390_previous_fndecl = fndecl; | |
15519 | } | |
15520 | #endif | |
15521 | ||
b5e3200c JG |
15522 | /* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */ |
15523 | ||
15524 | static bool | |
445d7826 | 15525 | s390_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size, |
b5e3200c JG |
15526 | unsigned int align ATTRIBUTE_UNUSED, |
15527 | enum by_pieces_operation op ATTRIBUTE_UNUSED, | |
15528 | bool speed_p ATTRIBUTE_UNUSED) | |
15529 | { | |
15530 | return (size == 1 || size == 2 | |
15531 | || size == 4 || (TARGET_ZARCH && size == 8)); | |
15532 | } | |
15533 | ||
35bc11c3 AK |
15534 | /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */ |
15535 | ||
15536 | static void | |
15537 | s390_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) | |
15538 | { | |
3af82a61 AK |
15539 | tree sfpc = s390_builtin_decls[S390_BUILTIN_s390_sfpc]; |
15540 | tree efpc = s390_builtin_decls[S390_BUILTIN_s390_efpc]; | |
35bc11c3 | 15541 | tree call_efpc = build_call_expr (efpc, 0); |
f2c0c243 | 15542 | tree fenv_var = create_tmp_var_raw (unsigned_type_node); |
35bc11c3 AK |
15543 | |
15544 | #define FPC_EXCEPTION_MASK HOST_WIDE_INT_UC (0xf8000000) | |
15545 | #define FPC_FLAGS_MASK HOST_WIDE_INT_UC (0x00f80000) | |
15546 | #define FPC_DXC_MASK HOST_WIDE_INT_UC (0x0000ff00) | |
15547 | #define FPC_EXCEPTION_MASK_SHIFT HOST_WIDE_INT_UC (24) | |
15548 | #define FPC_FLAGS_SHIFT HOST_WIDE_INT_UC (16) | |
15549 | #define FPC_DXC_SHIFT HOST_WIDE_INT_UC (8) | |
15550 | ||
15551 | /* Generates the equivalent of feholdexcept (&fenv_var) | |
15552 | ||
15553 | fenv_var = __builtin_s390_efpc (); | |
15554 | __builtin_s390_sfpc (fenv_var & mask) */ | |
15555 | tree old_fpc = build2 (MODIFY_EXPR, unsigned_type_node, fenv_var, call_efpc); | |
15556 | tree new_fpc = | |
15557 | build2 (BIT_AND_EXPR, unsigned_type_node, fenv_var, | |
15558 | build_int_cst (unsigned_type_node, | |
15559 | ~(FPC_DXC_MASK | FPC_FLAGS_MASK | | |
15560 | FPC_EXCEPTION_MASK))); | |
15561 | tree set_new_fpc = build_call_expr (sfpc, 1, new_fpc); | |
15562 | *hold = build2 (COMPOUND_EXPR, void_type_node, old_fpc, set_new_fpc); | |
15563 | ||
15564 | /* Generates the equivalent of feclearexcept (FE_ALL_EXCEPT) | |
15565 | ||
15566 | __builtin_s390_sfpc (__builtin_s390_efpc () & mask) */ | |
15567 | new_fpc = build2 (BIT_AND_EXPR, unsigned_type_node, call_efpc, | |
15568 | build_int_cst (unsigned_type_node, | |
15569 | ~(FPC_DXC_MASK | FPC_FLAGS_MASK))); | |
15570 | *clear = build_call_expr (sfpc, 1, new_fpc); | |
15571 | ||
15572 | /* Generates the equivalent of feupdateenv (fenv_var) | |
15573 | ||
15574 | old_fpc = __builtin_s390_efpc (); | |
15575 | __builtin_s390_sfpc (fenv_var); | |
15576 | __atomic_feraiseexcept ((old_fpc & FPC_FLAGS_MASK) >> FPC_FLAGS_SHIFT); */ | |
15577 | ||
f2c0c243 | 15578 | old_fpc = create_tmp_var_raw (unsigned_type_node); |
35bc11c3 AK |
15579 | tree store_old_fpc = build2 (MODIFY_EXPR, void_type_node, |
15580 | old_fpc, call_efpc); | |
15581 | ||
15582 | set_new_fpc = build_call_expr (sfpc, 1, fenv_var); | |
15583 | ||
15584 | tree raise_old_except = build2 (BIT_AND_EXPR, unsigned_type_node, old_fpc, | |
15585 | build_int_cst (unsigned_type_node, | |
15586 | FPC_FLAGS_MASK)); | |
15587 | raise_old_except = build2 (RSHIFT_EXPR, unsigned_type_node, raise_old_except, | |
15588 | build_int_cst (unsigned_type_node, | |
15589 | FPC_FLAGS_SHIFT)); | |
15590 | tree atomic_feraiseexcept | |
15591 | = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT); | |
15592 | raise_old_except = build_call_expr (atomic_feraiseexcept, | |
15593 | 1, raise_old_except); | |
15594 | ||
15595 | *update = build2 (COMPOUND_EXPR, void_type_node, | |
15596 | build2 (COMPOUND_EXPR, void_type_node, | |
15597 | store_old_fpc, set_new_fpc), | |
15598 | raise_old_except); | |
15599 | ||
15600 | #undef FPC_EXCEPTION_MASK | |
15601 | #undef FPC_FLAGS_MASK | |
15602 | #undef FPC_DXC_MASK | |
15603 | #undef FPC_EXCEPTION_MASK_SHIFT | |
15604 | #undef FPC_FLAGS_SHIFT | |
15605 | #undef FPC_DXC_SHIFT | |
15606 | } | |
15607 | ||
085261c8 AK |
15608 | /* Return the vector mode to be used for inner mode MODE when doing |
15609 | vectorization. */ | |
15610 | static machine_mode | |
005ba29c | 15611 | s390_preferred_simd_mode (scalar_mode mode) |
085261c8 AK |
15612 | { |
15613 | if (TARGET_VX) | |
15614 | switch (mode) | |
15615 | { | |
4e10a5a7 | 15616 | case E_DFmode: |
085261c8 | 15617 | return V2DFmode; |
4e10a5a7 | 15618 | case E_DImode: |
085261c8 | 15619 | return V2DImode; |
4e10a5a7 | 15620 | case E_SImode: |
085261c8 | 15621 | return V4SImode; |
4e10a5a7 | 15622 | case E_HImode: |
085261c8 | 15623 | return V8HImode; |
4e10a5a7 | 15624 | case E_QImode: |
085261c8 AK |
15625 | return V16QImode; |
15626 | default:; | |
15627 | } | |
15628 | return word_mode; | |
15629 | } | |
15630 | ||
15631 | /* Our hardware does not require vectors to be strictly aligned. */ | |
15632 | static bool | |
15633 | s390_support_vector_misalignment (machine_mode mode ATTRIBUTE_UNUSED, | |
15634 | const_tree type ATTRIBUTE_UNUSED, | |
15635 | int misalignment ATTRIBUTE_UNUSED, | |
15636 | bool is_packed ATTRIBUTE_UNUSED) | |
15637 | { | |
920cc696 AK |
15638 | if (TARGET_VX) |
15639 | return true; | |
15640 | ||
15641 | return default_builtin_support_vector_misalignment (mode, type, misalignment, | |
15642 | is_packed); | |
085261c8 AK |
15643 | } |
15644 | ||
15645 | /* The vector ABI requires vector types to be aligned on an 8 byte | |
15646 | boundary (our stack alignment). However, we allow this to be | |
15647 | overriden by the user, while this definitely breaks the ABI. */ | |
15648 | static HOST_WIDE_INT | |
15649 | s390_vector_alignment (const_tree type) | |
15650 | { | |
15651 | if (!TARGET_VX_ABI) | |
15652 | return default_vector_alignment (type); | |
15653 | ||
15654 | if (TYPE_USER_ALIGN (type)) | |
15655 | return TYPE_ALIGN (type); | |
15656 | ||
15657 | return MIN (64, tree_to_shwi (TYPE_SIZE (type))); | |
15658 | } | |
15659 | ||
7763d972 DV |
15660 | #ifdef HAVE_AS_MACHINE_MACHINEMODE |
15661 | /* Implement TARGET_ASM_FILE_START. */ | |
15662 | static void | |
15663 | s390_asm_file_start (void) | |
15664 | { | |
587b7f7a | 15665 | default_file_start (); |
7763d972 DV |
15666 | s390_asm_output_machine_for_arch (asm_out_file); |
15667 | } | |
15668 | #endif | |
15669 | ||
45901378 AK |
15670 | /* Implement TARGET_ASM_FILE_END. */ |
15671 | static void | |
15672 | s390_asm_file_end (void) | |
15673 | { | |
15674 | #ifdef HAVE_AS_GNU_ATTRIBUTE | |
15675 | varpool_node *vnode; | |
15676 | cgraph_node *cnode; | |
15677 | ||
15678 | FOR_EACH_VARIABLE (vnode) | |
15679 | if (TREE_PUBLIC (vnode->decl)) | |
15680 | s390_check_type_for_vector_abi (TREE_TYPE (vnode->decl), false, false); | |
15681 | ||
15682 | FOR_EACH_FUNCTION (cnode) | |
15683 | if (TREE_PUBLIC (cnode->decl)) | |
15684 | s390_check_type_for_vector_abi (TREE_TYPE (cnode->decl), false, false); | |
15685 | ||
15686 | ||
15687 | if (s390_vector_abi != 0) | |
15688 | fprintf (asm_out_file, "\t.gnu_attribute 8, %d\n", | |
15689 | s390_vector_abi); | |
15690 | #endif | |
15691 | file_end_indicate_exec_stack (); | |
4cb4721f MK |
15692 | |
15693 | if (flag_split_stack) | |
15694 | file_end_indicate_split_stack (); | |
45901378 | 15695 | } |
085261c8 | 15696 | |
cb4c41dd AK |
15697 | /* Return true if TYPE is a vector bool type. */ |
15698 | static inline bool | |
15699 | s390_vector_bool_type_p (const_tree type) | |
15700 | { | |
15701 | return TYPE_VECTOR_OPAQUE (type); | |
15702 | } | |
15703 | ||
15704 | /* Return the diagnostic message string if the binary operation OP is | |
15705 | not permitted on TYPE1 and TYPE2, NULL otherwise. */ | |
15706 | static const char* | |
15707 | s390_invalid_binary_op (int op ATTRIBUTE_UNUSED, const_tree type1, const_tree type2) | |
15708 | { | |
15709 | bool bool1_p, bool2_p; | |
15710 | bool plusminus_p; | |
15711 | bool muldiv_p; | |
15712 | bool compare_p; | |
15713 | machine_mode mode1, mode2; | |
15714 | ||
15715 | if (!TARGET_ZVECTOR) | |
15716 | return NULL; | |
15717 | ||
15718 | if (!VECTOR_TYPE_P (type1) || !VECTOR_TYPE_P (type2)) | |
15719 | return NULL; | |
15720 | ||
15721 | bool1_p = s390_vector_bool_type_p (type1); | |
15722 | bool2_p = s390_vector_bool_type_p (type2); | |
15723 | ||
15724 | /* Mixing signed and unsigned types is forbidden for all | |
15725 | operators. */ | |
15726 | if (!bool1_p && !bool2_p | |
15727 | && TYPE_UNSIGNED (type1) != TYPE_UNSIGNED (type2)) | |
bd2c6270 | 15728 | return N_("types differ in signedness"); |
cb4c41dd AK |
15729 | |
15730 | plusminus_p = (op == PLUS_EXPR || op == MINUS_EXPR); | |
15731 | muldiv_p = (op == MULT_EXPR || op == RDIV_EXPR || op == TRUNC_DIV_EXPR | |
15732 | || op == CEIL_DIV_EXPR || op == FLOOR_DIV_EXPR | |
15733 | || op == ROUND_DIV_EXPR); | |
15734 | compare_p = (op == LT_EXPR || op == LE_EXPR || op == GT_EXPR || op == GE_EXPR | |
15735 | || op == EQ_EXPR || op == NE_EXPR); | |
15736 | ||
15737 | if (bool1_p && bool2_p && (plusminus_p || muldiv_p)) | |
15738 | return N_("binary operator does not support two vector bool operands"); | |
15739 | ||
15740 | if (bool1_p != bool2_p && (muldiv_p || compare_p)) | |
15741 | return N_("binary operator does not support vector bool operand"); | |
15742 | ||
15743 | mode1 = TYPE_MODE (type1); | |
15744 | mode2 = TYPE_MODE (type2); | |
15745 | ||
15746 | if (bool1_p != bool2_p && plusminus_p | |
15747 | && (GET_MODE_CLASS (mode1) == MODE_VECTOR_FLOAT | |
15748 | || GET_MODE_CLASS (mode2) == MODE_VECTOR_FLOAT)) | |
15749 | return N_("binary operator does not support mixing vector " | |
15750 | "bool with floating point vector operands"); | |
15751 | ||
15752 | return NULL; | |
15753 | } | |
15754 | ||
638108bd JG |
15755 | /* Implement TARGET_C_EXCESS_PRECISION. |
15756 | ||
15757 | FIXME: For historical reasons, float_t and double_t are typedef'ed to | |
15758 | double on s390, causing operations on float_t to operate in a higher | |
15759 | precision than is necessary. However, it is not the case that SFmode | |
15760 | operations have implicit excess precision, and we generate more optimal | |
15761 | code if we let the compiler know no implicit extra precision is added. | |
15762 | ||
15763 | That means when we are compiling with -fexcess-precision=fast, the value | |
15764 | we set for FLT_EVAL_METHOD will be out of line with the actual precision of | |
15765 | float_t (though they would be correct for -fexcess-precision=standard). | |
15766 | ||
15767 | A complete fix would modify glibc to remove the unnecessary typedef | |
15768 | of float_t to double. */ | |
15769 | ||
15770 | static enum flt_eval_method | |
15771 | s390_excess_precision (enum excess_precision_type type) | |
15772 | { | |
15773 | switch (type) | |
15774 | { | |
15775 | case EXCESS_PRECISION_TYPE_IMPLICIT: | |
15776 | case EXCESS_PRECISION_TYPE_FAST: | |
15777 | /* The fastest type to promote to will always be the native type, | |
15778 | whether that occurs with implicit excess precision or | |
15779 | otherwise. */ | |
15780 | return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT; | |
15781 | case EXCESS_PRECISION_TYPE_STANDARD: | |
15782 | /* Otherwise, when we are in a standards compliant mode, to | |
15783 | ensure consistency with the implementation in glibc, report that | |
15784 | float is evaluated to the range and precision of double. */ | |
15785 | return FLT_EVAL_METHOD_PROMOTE_TO_DOUBLE; | |
15786 | default: | |
15787 | gcc_unreachable (); | |
15788 | } | |
15789 | return FLT_EVAL_METHOD_UNPREDICTABLE; | |
15790 | } | |
15791 | ||
4997a71d JJ |
15792 | /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */ |
15793 | ||
15794 | static unsigned HOST_WIDE_INT | |
15795 | s390_asan_shadow_offset (void) | |
15796 | { | |
15797 | return TARGET_64BIT ? HOST_WIDE_INT_1U << 52 : HOST_WIDE_INT_UC (0x20000000); | |
15798 | } | |
15799 | ||
ab96de7e | 15800 | /* Initialize GCC target structure. */ |
38899e29 | 15801 | |
ab96de7e AS |
15802 | #undef TARGET_ASM_ALIGNED_HI_OP |
15803 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
15804 | #undef TARGET_ASM_ALIGNED_DI_OP | |
15805 | #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" | |
15806 | #undef TARGET_ASM_INTEGER | |
15807 | #define TARGET_ASM_INTEGER s390_assemble_integer | |
ed9676cf | 15808 | |
ab96de7e AS |
15809 | #undef TARGET_ASM_OPEN_PAREN |
15810 | #define TARGET_ASM_OPEN_PAREN "" | |
38899e29 | 15811 | |
ab96de7e AS |
15812 | #undef TARGET_ASM_CLOSE_PAREN |
15813 | #define TARGET_ASM_CLOSE_PAREN "" | |
ed9676cf | 15814 | |
c5387660 JM |
15815 | #undef TARGET_OPTION_OVERRIDE |
15816 | #define TARGET_OPTION_OVERRIDE s390_option_override | |
15817 | ||
1202f33e JJ |
15818 | #ifdef TARGET_THREAD_SSP_OFFSET |
15819 | #undef TARGET_STACK_PROTECT_GUARD | |
15820 | #define TARGET_STACK_PROTECT_GUARD hook_tree_void_null | |
15821 | #endif | |
15822 | ||
ab96de7e AS |
15823 | #undef TARGET_ENCODE_SECTION_INFO |
15824 | #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info | |
ed9676cf | 15825 | |
9602b6a1 AK |
15826 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
15827 | #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p | |
15828 | ||
ab96de7e AS |
15829 | #ifdef HAVE_AS_TLS |
15830 | #undef TARGET_HAVE_TLS | |
15831 | #define TARGET_HAVE_TLS true | |
15832 | #endif | |
15833 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
15834 | #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem | |
ed9676cf | 15835 | |
ab96de7e AS |
15836 | #undef TARGET_DELEGITIMIZE_ADDRESS |
15837 | #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address | |
ed9676cf | 15838 | |
506d7b68 PB |
15839 | #undef TARGET_LEGITIMIZE_ADDRESS |
15840 | #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address | |
15841 | ||
ab96de7e AS |
15842 | #undef TARGET_RETURN_IN_MEMORY |
15843 | #define TARGET_RETURN_IN_MEMORY s390_return_in_memory | |
38899e29 | 15844 | |
5a3fe9b6 AK |
15845 | #undef TARGET_INIT_BUILTINS |
15846 | #define TARGET_INIT_BUILTINS s390_init_builtins | |
15847 | #undef TARGET_EXPAND_BUILTIN | |
15848 | #define TARGET_EXPAND_BUILTIN s390_expand_builtin | |
9b80b7bc AK |
15849 | #undef TARGET_BUILTIN_DECL |
15850 | #define TARGET_BUILTIN_DECL s390_builtin_decl | |
5a3fe9b6 | 15851 | |
0f8ab434 AS |
15852 | #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA |
15853 | #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra | |
15854 | ||
ab96de7e AS |
15855 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
15856 | #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk | |
15857 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
3101faab | 15858 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true |
ed9676cf | 15859 | |
638108bd JG |
15860 | #undef TARGET_C_EXCESS_PRECISION |
15861 | #define TARGET_C_EXCESS_PRECISION s390_excess_precision | |
15862 | ||
ab96de7e AS |
15863 | #undef TARGET_SCHED_ADJUST_PRIORITY |
15864 | #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority | |
15865 | #undef TARGET_SCHED_ISSUE_RATE | |
15866 | #define TARGET_SCHED_ISSUE_RATE s390_issue_rate | |
15867 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD | |
15868 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead | |
38899e29 | 15869 | |
3a892e44 AK |
15870 | #undef TARGET_SCHED_VARIABLE_ISSUE |
15871 | #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue | |
15872 | #undef TARGET_SCHED_REORDER | |
15873 | #define TARGET_SCHED_REORDER s390_sched_reorder | |
244e6c5c AK |
15874 | #undef TARGET_SCHED_INIT |
15875 | #define TARGET_SCHED_INIT s390_sched_init | |
3a892e44 | 15876 | |
ab96de7e AS |
15877 | #undef TARGET_CANNOT_COPY_INSN_P |
15878 | #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p | |
15879 | #undef TARGET_RTX_COSTS | |
15880 | #define TARGET_RTX_COSTS s390_rtx_costs | |
15881 | #undef TARGET_ADDRESS_COST | |
15882 | #define TARGET_ADDRESS_COST s390_address_cost | |
ccaed3ba AS |
15883 | #undef TARGET_REGISTER_MOVE_COST |
15884 | #define TARGET_REGISTER_MOVE_COST s390_register_move_cost | |
15885 | #undef TARGET_MEMORY_MOVE_COST | |
15886 | #define TARGET_MEMORY_MOVE_COST s390_memory_move_cost | |
7f5fc633 AK |
15887 | #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST |
15888 | #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \ | |
15889 | s390_builtin_vectorization_cost | |
38899e29 | 15890 | |
ab96de7e AS |
15891 | #undef TARGET_MACHINE_DEPENDENT_REORG |
15892 | #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg | |
8a512b77 | 15893 | |
ab96de7e AS |
15894 | #undef TARGET_VALID_POINTER_MODE |
15895 | #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode | |
38899e29 | 15896 | |
ab96de7e AS |
15897 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
15898 | #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list | |
d7bd8aeb JJ |
15899 | #undef TARGET_EXPAND_BUILTIN_VA_START |
15900 | #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start | |
4997a71d JJ |
15901 | #undef TARGET_ASAN_SHADOW_OFFSET |
15902 | #define TARGET_ASAN_SHADOW_OFFSET s390_asan_shadow_offset | |
ab96de7e AS |
15903 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
15904 | #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg | |
4798630c | 15905 | |
cde0f3fd PB |
15906 | #undef TARGET_PROMOTE_FUNCTION_MODE |
15907 | #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode | |
ab96de7e AS |
15908 | #undef TARGET_PASS_BY_REFERENCE |
15909 | #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference | |
4798630c | 15910 | |
ab96de7e AS |
15911 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
15912 | #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall | |
3cb1da52 NF |
15913 | #undef TARGET_FUNCTION_ARG |
15914 | #define TARGET_FUNCTION_ARG s390_function_arg | |
15915 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
15916 | #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance | |
76b0cbf8 RS |
15917 | #undef TARGET_FUNCTION_ARG_PADDING |
15918 | #define TARGET_FUNCTION_ARG_PADDING s390_function_arg_padding | |
b46616fd AK |
15919 | #undef TARGET_FUNCTION_VALUE |
15920 | #define TARGET_FUNCTION_VALUE s390_function_value | |
15921 | #undef TARGET_LIBCALL_VALUE | |
15922 | #define TARGET_LIBCALL_VALUE s390_libcall_value | |
085261c8 AK |
15923 | #undef TARGET_STRICT_ARGUMENT_NAMING |
15924 | #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true | |
4798630c | 15925 | |
d56a43a0 AK |
15926 | #undef TARGET_KEEP_LEAF_WHEN_PROFILED |
15927 | #define TARGET_KEEP_LEAF_WHEN_PROFILED s390_keep_leaf_when_profiled | |
15928 | ||
ab96de7e AS |
15929 | #undef TARGET_FIXED_CONDITION_CODE_REGS |
15930 | #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs | |
4798630c | 15931 | |
ab96de7e AS |
15932 | #undef TARGET_CC_MODES_COMPATIBLE |
15933 | #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible | |
4798630c | 15934 | |
e7e64a25 | 15935 | #undef TARGET_INVALID_WITHIN_DOLOOP |
ac44248e | 15936 | #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_insn_null |
c08b81aa | 15937 | |
fdbe66f2 EB |
15938 | #ifdef HAVE_AS_TLS |
15939 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
15940 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel | |
15941 | #endif | |
15942 | ||
085261c8 AK |
15943 | #undef TARGET_DWARF_FRAME_REG_MODE |
15944 | #define TARGET_DWARF_FRAME_REG_MODE s390_dwarf_frame_reg_mode | |
15945 | ||
7269aee7 | 15946 | #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING |
608063c3 JB |
15947 | #undef TARGET_MANGLE_TYPE |
15948 | #define TARGET_MANGLE_TYPE s390_mangle_type | |
7269aee7 AH |
15949 | #endif |
15950 | ||
4dc19cc0 AK |
15951 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
15952 | #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p | |
15953 | ||
085261c8 AK |
15954 | #undef TARGET_VECTOR_MODE_SUPPORTED_P |
15955 | #define TARGET_VECTOR_MODE_SUPPORTED_P s390_vector_mode_supported_p | |
15956 | ||
5df97412 AS |
15957 | #undef TARGET_PREFERRED_RELOAD_CLASS |
15958 | #define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class | |
15959 | ||
833cd70a AK |
15960 | #undef TARGET_SECONDARY_RELOAD |
15961 | #define TARGET_SECONDARY_RELOAD s390_secondary_reload | |
15962 | ||
c7ff6e7a AK |
15963 | #undef TARGET_LIBGCC_CMP_RETURN_MODE |
15964 | #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode | |
15965 | ||
15966 | #undef TARGET_LIBGCC_SHIFT_COUNT_MODE | |
15967 | #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode | |
15968 | ||
c6c3dba9 PB |
15969 | #undef TARGET_LEGITIMATE_ADDRESS_P |
15970 | #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p | |
15971 | ||
1a627b35 RS |
15972 | #undef TARGET_LEGITIMATE_CONSTANT_P |
15973 | #define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p | |
15974 | ||
3597e113 VM |
15975 | #undef TARGET_LRA_P |
15976 | #define TARGET_LRA_P s390_lra_p | |
15977 | ||
7b5cbb57 AS |
15978 | #undef TARGET_CAN_ELIMINATE |
15979 | #define TARGET_CAN_ELIMINATE s390_can_eliminate | |
15980 | ||
5efd84c5 NF |
15981 | #undef TARGET_CONDITIONAL_REGISTER_USAGE |
15982 | #define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage | |
15983 | ||
40ac4f73 CB |
15984 | #undef TARGET_LOOP_UNROLL_ADJUST |
15985 | #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust | |
15986 | ||
b81ecf6f RH |
15987 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE |
15988 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template | |
15989 | #undef TARGET_TRAMPOLINE_INIT | |
15990 | #define TARGET_TRAMPOLINE_INIT s390_trampoline_init | |
15991 | ||
a0003c78 DV |
15992 | /* PR 79421 */ |
15993 | #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS | |
15994 | #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1 | |
15995 | ||
9602b6a1 AK |
15996 | #undef TARGET_UNWIND_WORD_MODE |
15997 | #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode | |
15998 | ||
c354951b AK |
15999 | #undef TARGET_CANONICALIZE_COMPARISON |
16000 | #define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison | |
16001 | ||
6455a49e AK |
16002 | #undef TARGET_HARD_REGNO_SCRATCH_OK |
16003 | #define TARGET_HARD_REGNO_SCRATCH_OK s390_hard_regno_scratch_ok | |
16004 | ||
c43f4279 RS |
16005 | #undef TARGET_HARD_REGNO_NREGS |
16006 | #define TARGET_HARD_REGNO_NREGS s390_hard_regno_nregs | |
f939c3e6 RS |
16007 | #undef TARGET_HARD_REGNO_MODE_OK |
16008 | #define TARGET_HARD_REGNO_MODE_OK s390_hard_regno_mode_ok | |
99e1629f RS |
16009 | #undef TARGET_MODES_TIEABLE_P |
16010 | #define TARGET_MODES_TIEABLE_P s390_modes_tieable_p | |
f939c3e6 | 16011 | |
80ec73f4 RS |
16012 | #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED |
16013 | #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \ | |
16014 | s390_hard_regno_call_part_clobbered | |
16015 | ||
d0de9e13 DV |
16016 | #undef TARGET_ATTRIBUTE_TABLE |
16017 | #define TARGET_ATTRIBUTE_TABLE s390_attribute_table | |
16018 | ||
94091f43 DV |
16019 | #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P |
16020 | #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true | |
d0de9e13 | 16021 | |
177bc204 RS |
16022 | #undef TARGET_SET_UP_BY_PROLOGUE |
16023 | #define TARGET_SET_UP_BY_PROLOGUE s300_set_up_by_prologue | |
16024 | ||
4cb4721f MK |
16025 | #undef TARGET_EXTRA_LIVE_ON_ENTRY |
16026 | #define TARGET_EXTRA_LIVE_ON_ENTRY s390_live_on_entry | |
16027 | ||
b5e3200c JG |
16028 | #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P |
16029 | #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \ | |
16030 | s390_use_by_pieces_infrastructure_p | |
16031 | ||
35bc11c3 AK |
16032 | #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV |
16033 | #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV s390_atomic_assign_expand_fenv | |
16034 | ||
085261c8 AK |
16035 | #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN |
16036 | #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN s390_invalid_arg_for_unprototyped_fn | |
16037 | ||
16038 | #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE | |
16039 | #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE s390_preferred_simd_mode | |
16040 | ||
16041 | #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT | |
16042 | #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT s390_support_vector_misalignment | |
16043 | ||
16044 | #undef TARGET_VECTOR_ALIGNMENT | |
16045 | #define TARGET_VECTOR_ALIGNMENT s390_vector_alignment | |
16046 | ||
cb4c41dd AK |
16047 | #undef TARGET_INVALID_BINARY_OP |
16048 | #define TARGET_INVALID_BINARY_OP s390_invalid_binary_op | |
16049 | ||
7763d972 DV |
16050 | #ifdef HAVE_AS_MACHINE_MACHINEMODE |
16051 | #undef TARGET_ASM_FILE_START | |
16052 | #define TARGET_ASM_FILE_START s390_asm_file_start | |
16053 | #endif | |
16054 | ||
45901378 AK |
16055 | #undef TARGET_ASM_FILE_END |
16056 | #define TARGET_ASM_FILE_END s390_asm_file_end | |
16057 | ||
ec47b086 DV |
16058 | #if S390_USE_TARGET_ATTRIBUTE |
16059 | #undef TARGET_SET_CURRENT_FUNCTION | |
16060 | #define TARGET_SET_CURRENT_FUNCTION s390_set_current_function | |
16061 | ||
16062 | #undef TARGET_OPTION_VALID_ATTRIBUTE_P | |
16063 | #define TARGET_OPTION_VALID_ATTRIBUTE_P s390_valid_target_attribute_p | |
db6bb1ec AK |
16064 | |
16065 | #undef TARGET_CAN_INLINE_P | |
16066 | #define TARGET_CAN_INLINE_P s390_can_inline_p | |
ec47b086 DV |
16067 | #endif |
16068 | ||
16069 | #undef TARGET_OPTION_RESTORE | |
16070 | #define TARGET_OPTION_RESTORE s390_function_specific_restore | |
16071 | ||
ab96de7e | 16072 | struct gcc_target targetm = TARGET_INITIALIZER; |
38899e29 | 16073 | |
29742ba4 | 16074 | #include "gt-s390.h" |