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9db1d521 | 1 | /* Subroutines used for code generation on IBM S/390 and zSeries |
6fb5fa3c | 2 | Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, |
81ef7e24 | 3 | 2007, 2008, 2009, 2010 Free Software Foundation, Inc. |
9db1d521 | 4 | Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
5 | Ulrich Weigand (uweigand@de.ibm.com) and |
6 | Andreas Krebbel (Andreas.Krebbel@de.ibm.com). | |
9db1d521 | 7 | |
58add37a | 8 | This file is part of GCC. |
9db1d521 | 9 | |
58add37a UW |
10 | GCC is free software; you can redistribute it and/or modify it under |
11 | the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 12 | Software Foundation; either version 3, or (at your option) any later |
58add37a | 13 | version. |
9db1d521 | 14 | |
58add37a UW |
15 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
16 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
18 | for more details. | |
9db1d521 HP |
19 | |
20 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
21 | along with GCC; see the file COPYING3. If not see |
22 | <http://www.gnu.org/licenses/>. */ | |
9db1d521 HP |
23 | |
24 | #include "config.h" | |
9db1d521 | 25 | #include "system.h" |
4977bab6 ZW |
26 | #include "coretypes.h" |
27 | #include "tm.h" | |
9db1d521 HP |
28 | #include "rtl.h" |
29 | #include "tree.h" | |
30 | #include "tm_p.h" | |
31 | #include "regs.h" | |
32 | #include "hard-reg-set.h" | |
9db1d521 HP |
33 | #include "insn-config.h" |
34 | #include "conditions.h" | |
35 | #include "output.h" | |
36 | #include "insn-attr.h" | |
37 | #include "flags.h" | |
38 | #include "except.h" | |
39 | #include "function.h" | |
40 | #include "recog.h" | |
41 | #include "expr.h" | |
7c82a1ed | 42 | #include "reload.h" |
718f9c0f | 43 | #include "diagnostic-core.h" |
9db1d521 HP |
44 | #include "toplev.h" |
45 | #include "basic-block.h" | |
4023fb28 | 46 | #include "integrate.h" |
9db1d521 HP |
47 | #include "ggc.h" |
48 | #include "target.h" | |
49 | #include "target-def.h" | |
0d3c08b6 | 50 | #include "debug.h" |
f1e639b1 | 51 | #include "langhooks.h" |
a41c6c53 | 52 | #include "optabs.h" |
726a989a | 53 | #include "gimple.h" |
6fb5fa3c | 54 | #include "df.h" |
ff5b964d | 55 | #include "params.h" |
40ac4f73 | 56 | #include "cfgloop.h" |
9db1d521 | 57 | |
114278e7 | 58 | |
017e0eb9 MD |
59 | /* Define the specific costs for a given cpu. */ |
60 | ||
f4aa3848 | 61 | struct processor_costs |
017e0eb9 | 62 | { |
98fd0d70 | 63 | /* multiplication */ |
017e0eb9 MD |
64 | const int m; /* cost of an M instruction. */ |
65 | const int mghi; /* cost of an MGHI instruction. */ | |
66 | const int mh; /* cost of an MH instruction. */ | |
67 | const int mhi; /* cost of an MHI instruction. */ | |
2742a1ed | 68 | const int ml; /* cost of an ML instruction. */ |
017e0eb9 MD |
69 | const int mr; /* cost of an MR instruction. */ |
70 | const int ms; /* cost of an MS instruction. */ | |
71 | const int msg; /* cost of an MSG instruction. */ | |
72 | const int msgf; /* cost of an MSGF instruction. */ | |
73 | const int msgfr; /* cost of an MSGFR instruction. */ | |
74 | const int msgr; /* cost of an MSGR instruction. */ | |
75 | const int msr; /* cost of an MSR instruction. */ | |
76 | const int mult_df; /* cost of multiplication in DFmode. */ | |
f61a2c7d | 77 | const int mxbr; |
98fd0d70 | 78 | /* square root */ |
f61a2c7d | 79 | const int sqxbr; /* cost of square root in TFmode. */ |
2742a1ed MD |
80 | const int sqdbr; /* cost of square root in DFmode. */ |
81 | const int sqebr; /* cost of square root in SFmode. */ | |
98fd0d70 | 82 | /* multiply and add */ |
b75d6bab MD |
83 | const int madbr; /* cost of multiply and add in DFmode. */ |
84 | const int maebr; /* cost of multiply and add in SFmode. */ | |
98fd0d70 | 85 | /* division */ |
f61a2c7d | 86 | const int dxbr; |
98fd0d70 | 87 | const int ddbr; |
98fd0d70 | 88 | const int debr; |
6fa5b390 MD |
89 | const int dlgr; |
90 | const int dlr; | |
91 | const int dr; | |
92 | const int dsgfr; | |
93 | const int dsgr; | |
017e0eb9 MD |
94 | }; |
95 | ||
96 | const struct processor_costs *s390_cost; | |
97 | ||
98 | static const | |
f4aa3848 | 99 | struct processor_costs z900_cost = |
017e0eb9 MD |
100 | { |
101 | COSTS_N_INSNS (5), /* M */ | |
102 | COSTS_N_INSNS (10), /* MGHI */ | |
103 | COSTS_N_INSNS (5), /* MH */ | |
104 | COSTS_N_INSNS (4), /* MHI */ | |
2742a1ed | 105 | COSTS_N_INSNS (5), /* ML */ |
017e0eb9 MD |
106 | COSTS_N_INSNS (5), /* MR */ |
107 | COSTS_N_INSNS (4), /* MS */ | |
108 | COSTS_N_INSNS (15), /* MSG */ | |
109 | COSTS_N_INSNS (7), /* MSGF */ | |
110 | COSTS_N_INSNS (7), /* MSGFR */ | |
111 | COSTS_N_INSNS (10), /* MSGR */ | |
112 | COSTS_N_INSNS (4), /* MSR */ | |
113 | COSTS_N_INSNS (7), /* multiplication in DFmode */ | |
f61a2c7d AK |
114 | COSTS_N_INSNS (13), /* MXBR */ |
115 | COSTS_N_INSNS (136), /* SQXBR */ | |
2742a1ed MD |
116 | COSTS_N_INSNS (44), /* SQDBR */ |
117 | COSTS_N_INSNS (35), /* SQEBR */ | |
b75d6bab MD |
118 | COSTS_N_INSNS (18), /* MADBR */ |
119 | COSTS_N_INSNS (13), /* MAEBR */ | |
f61a2c7d | 120 | COSTS_N_INSNS (134), /* DXBR */ |
98fd0d70 | 121 | COSTS_N_INSNS (30), /* DDBR */ |
98fd0d70 | 122 | COSTS_N_INSNS (27), /* DEBR */ |
6fa5b390 MD |
123 | COSTS_N_INSNS (220), /* DLGR */ |
124 | COSTS_N_INSNS (34), /* DLR */ | |
125 | COSTS_N_INSNS (34), /* DR */ | |
126 | COSTS_N_INSNS (32), /* DSGFR */ | |
127 | COSTS_N_INSNS (32), /* DSGR */ | |
017e0eb9 MD |
128 | }; |
129 | ||
130 | static const | |
f4aa3848 | 131 | struct processor_costs z990_cost = |
017e0eb9 MD |
132 | { |
133 | COSTS_N_INSNS (4), /* M */ | |
134 | COSTS_N_INSNS (2), /* MGHI */ | |
135 | COSTS_N_INSNS (2), /* MH */ | |
136 | COSTS_N_INSNS (2), /* MHI */ | |
2742a1ed | 137 | COSTS_N_INSNS (4), /* ML */ |
017e0eb9 MD |
138 | COSTS_N_INSNS (4), /* MR */ |
139 | COSTS_N_INSNS (5), /* MS */ | |
140 | COSTS_N_INSNS (6), /* MSG */ | |
141 | COSTS_N_INSNS (4), /* MSGF */ | |
142 | COSTS_N_INSNS (4), /* MSGFR */ | |
143 | COSTS_N_INSNS (4), /* MSGR */ | |
144 | COSTS_N_INSNS (4), /* MSR */ | |
145 | COSTS_N_INSNS (1), /* multiplication in DFmode */ | |
f61a2c7d AK |
146 | COSTS_N_INSNS (28), /* MXBR */ |
147 | COSTS_N_INSNS (130), /* SQXBR */ | |
2742a1ed MD |
148 | COSTS_N_INSNS (66), /* SQDBR */ |
149 | COSTS_N_INSNS (38), /* SQEBR */ | |
b75d6bab MD |
150 | COSTS_N_INSNS (1), /* MADBR */ |
151 | COSTS_N_INSNS (1), /* MAEBR */ | |
f61a2c7d | 152 | COSTS_N_INSNS (60), /* DXBR */ |
98fd0d70 | 153 | COSTS_N_INSNS (40), /* DDBR */ |
142cd70f | 154 | COSTS_N_INSNS (26), /* DEBR */ |
6fa5b390 MD |
155 | COSTS_N_INSNS (176), /* DLGR */ |
156 | COSTS_N_INSNS (31), /* DLR */ | |
157 | COSTS_N_INSNS (31), /* DR */ | |
158 | COSTS_N_INSNS (31), /* DSGFR */ | |
159 | COSTS_N_INSNS (31), /* DSGR */ | |
017e0eb9 MD |
160 | }; |
161 | ||
ec24698e | 162 | static const |
f4aa3848 | 163 | struct processor_costs z9_109_cost = |
ec24698e UW |
164 | { |
165 | COSTS_N_INSNS (4), /* M */ | |
166 | COSTS_N_INSNS (2), /* MGHI */ | |
167 | COSTS_N_INSNS (2), /* MH */ | |
168 | COSTS_N_INSNS (2), /* MHI */ | |
169 | COSTS_N_INSNS (4), /* ML */ | |
170 | COSTS_N_INSNS (4), /* MR */ | |
171 | COSTS_N_INSNS (5), /* MS */ | |
172 | COSTS_N_INSNS (6), /* MSG */ | |
173 | COSTS_N_INSNS (4), /* MSGF */ | |
174 | COSTS_N_INSNS (4), /* MSGFR */ | |
175 | COSTS_N_INSNS (4), /* MSGR */ | |
176 | COSTS_N_INSNS (4), /* MSR */ | |
177 | COSTS_N_INSNS (1), /* multiplication in DFmode */ | |
f61a2c7d AK |
178 | COSTS_N_INSNS (28), /* MXBR */ |
179 | COSTS_N_INSNS (130), /* SQXBR */ | |
ec24698e UW |
180 | COSTS_N_INSNS (66), /* SQDBR */ |
181 | COSTS_N_INSNS (38), /* SQEBR */ | |
182 | COSTS_N_INSNS (1), /* MADBR */ | |
183 | COSTS_N_INSNS (1), /* MAEBR */ | |
f61a2c7d | 184 | COSTS_N_INSNS (60), /* DXBR */ |
ec24698e | 185 | COSTS_N_INSNS (40), /* DDBR */ |
142cd70f | 186 | COSTS_N_INSNS (26), /* DEBR */ |
ec24698e UW |
187 | COSTS_N_INSNS (30), /* DLGR */ |
188 | COSTS_N_INSNS (23), /* DLR */ | |
189 | COSTS_N_INSNS (23), /* DR */ | |
190 | COSTS_N_INSNS (24), /* DSGFR */ | |
191 | COSTS_N_INSNS (24), /* DSGR */ | |
192 | }; | |
017e0eb9 | 193 | |
93538e8e AK |
194 | static const |
195 | struct processor_costs z10_cost = | |
196 | { | |
9381e3f1 WG |
197 | COSTS_N_INSNS (10), /* M */ |
198 | COSTS_N_INSNS (10), /* MGHI */ | |
199 | COSTS_N_INSNS (10), /* MH */ | |
200 | COSTS_N_INSNS (10), /* MHI */ | |
201 | COSTS_N_INSNS (10), /* ML */ | |
202 | COSTS_N_INSNS (10), /* MR */ | |
203 | COSTS_N_INSNS (10), /* MS */ | |
204 | COSTS_N_INSNS (10), /* MSG */ | |
205 | COSTS_N_INSNS (10), /* MSGF */ | |
206 | COSTS_N_INSNS (10), /* MSGFR */ | |
207 | COSTS_N_INSNS (10), /* MSGR */ | |
208 | COSTS_N_INSNS (10), /* MSR */ | |
2cdece44 | 209 | COSTS_N_INSNS (1) , /* multiplication in DFmode */ |
9381e3f1 WG |
210 | COSTS_N_INSNS (50), /* MXBR */ |
211 | COSTS_N_INSNS (120), /* SQXBR */ | |
212 | COSTS_N_INSNS (52), /* SQDBR */ | |
93538e8e | 213 | COSTS_N_INSNS (38), /* SQEBR */ |
2cdece44 WG |
214 | COSTS_N_INSNS (1), /* MADBR */ |
215 | COSTS_N_INSNS (1), /* MAEBR */ | |
9381e3f1 WG |
216 | COSTS_N_INSNS (111), /* DXBR */ |
217 | COSTS_N_INSNS (39), /* DDBR */ | |
218 | COSTS_N_INSNS (32), /* DEBR */ | |
219 | COSTS_N_INSNS (160), /* DLGR */ | |
220 | COSTS_N_INSNS (71), /* DLR */ | |
221 | COSTS_N_INSNS (71), /* DR */ | |
222 | COSTS_N_INSNS (71), /* DSGFR */ | |
223 | COSTS_N_INSNS (71), /* DSGR */ | |
93538e8e AK |
224 | }; |
225 | ||
65b1d8ea AK |
226 | static const |
227 | struct processor_costs z196_cost = | |
228 | { | |
229 | COSTS_N_INSNS (7), /* M */ | |
230 | COSTS_N_INSNS (5), /* MGHI */ | |
231 | COSTS_N_INSNS (5), /* MH */ | |
232 | COSTS_N_INSNS (5), /* MHI */ | |
233 | COSTS_N_INSNS (7), /* ML */ | |
234 | COSTS_N_INSNS (7), /* MR */ | |
235 | COSTS_N_INSNS (6), /* MS */ | |
236 | COSTS_N_INSNS (8), /* MSG */ | |
237 | COSTS_N_INSNS (6), /* MSGF */ | |
238 | COSTS_N_INSNS (6), /* MSGFR */ | |
239 | COSTS_N_INSNS (8), /* MSGR */ | |
240 | COSTS_N_INSNS (6), /* MSR */ | |
241 | COSTS_N_INSNS (1) , /* multiplication in DFmode */ | |
242 | COSTS_N_INSNS (40), /* MXBR B+40 */ | |
243 | COSTS_N_INSNS (100), /* SQXBR B+100 */ | |
244 | COSTS_N_INSNS (42), /* SQDBR B+42 */ | |
245 | COSTS_N_INSNS (28), /* SQEBR B+28 */ | |
246 | COSTS_N_INSNS (1), /* MADBR B */ | |
247 | COSTS_N_INSNS (1), /* MAEBR B */ | |
248 | COSTS_N_INSNS (101), /* DXBR B+101 */ | |
249 | COSTS_N_INSNS (29), /* DDBR */ | |
250 | COSTS_N_INSNS (22), /* DEBR */ | |
251 | COSTS_N_INSNS (160), /* DLGR cracked */ | |
252 | COSTS_N_INSNS (160), /* DLR cracked */ | |
253 | COSTS_N_INSNS (160), /* DR expanded */ | |
254 | COSTS_N_INSNS (160), /* DSGFR cracked */ | |
255 | COSTS_N_INSNS (160), /* DSGR cracked */ | |
256 | }; | |
257 | ||
9db1d521 HP |
258 | extern int reload_completed; |
259 | ||
3a892e44 AK |
260 | /* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */ |
261 | static rtx last_scheduled_insn; | |
262 | ||
994fe660 UW |
263 | /* Structure used to hold the components of a S/390 memory |
264 | address. A legitimate address on S/390 is of the general | |
265 | form | |
266 | base + index + displacement | |
267 | where any of the components is optional. | |
268 | ||
269 | base and index are registers of the class ADDR_REGS, | |
270 | displacement is an unsigned 12-bit immediate constant. */ | |
9db1d521 HP |
271 | |
272 | struct s390_address | |
273 | { | |
274 | rtx base; | |
275 | rtx indx; | |
276 | rtx disp; | |
3ed99cc9 | 277 | bool pointer; |
f01cf809 | 278 | bool literal_pool; |
9db1d521 HP |
279 | }; |
280 | ||
be2c2a4b | 281 | /* Which cpu are we tuning for. */ |
f5db779b | 282 | enum processor_type s390_tune = PROCESSOR_max; |
81f40b79 | 283 | int s390_tune_flags; |
1fec52be HP |
284 | /* Which instruction set architecture to use. */ |
285 | enum processor_type s390_arch; | |
81f40b79 | 286 | int s390_arch_flags; |
d75f90f1 AK |
287 | |
288 | HOST_WIDE_INT s390_warn_framesize = 0; | |
d75f90f1 AK |
289 | HOST_WIDE_INT s390_stack_size = 0; |
290 | HOST_WIDE_INT s390_stack_guard = 0; | |
291 | ||
f4aa3848 | 292 | /* The following structure is embedded in the machine |
adf39f8f AK |
293 | specific part of struct function. */ |
294 | ||
d1b38208 | 295 | struct GTY (()) s390_frame_layout |
adf39f8f AK |
296 | { |
297 | /* Offset within stack frame. */ | |
298 | HOST_WIDE_INT gprs_offset; | |
299 | HOST_WIDE_INT f0_offset; | |
300 | HOST_WIDE_INT f4_offset; | |
301 | HOST_WIDE_INT f8_offset; | |
302 | HOST_WIDE_INT backchain_offset; | |
fb3712f6 AK |
303 | |
304 | /* Number of first and last gpr where slots in the register | |
305 | save area are reserved for. */ | |
306 | int first_save_gpr_slot; | |
307 | int last_save_gpr_slot; | |
308 | ||
29742ba4 | 309 | /* Number of first and last gpr to be saved, restored. */ |
4023fb28 UW |
310 | int first_save_gpr; |
311 | int first_restore_gpr; | |
312 | int last_save_gpr; | |
b767fc11 | 313 | int last_restore_gpr; |
4023fb28 | 314 | |
f4aa3848 AK |
315 | /* Bits standing for floating point registers. Set, if the |
316 | respective register has to be saved. Starting with reg 16 (f0) | |
adf39f8f AK |
317 | at the rightmost bit. |
318 | Bit 15 - 8 7 6 5 4 3 2 1 0 | |
319 | fpr 15 - 8 7 5 3 1 6 4 2 0 | |
320 | reg 31 - 24 23 22 21 20 19 18 17 16 */ | |
321 | unsigned int fpr_bitmap; | |
322 | ||
323 | /* Number of floating point registers f8-f15 which must be saved. */ | |
324 | int high_fprs; | |
325 | ||
dc4477f5 AK |
326 | /* Set if return address needs to be saved. |
327 | This flag is set by s390_return_addr_rtx if it could not use | |
328 | the initial value of r14 and therefore depends on r14 saved | |
329 | to the stack. */ | |
adf39f8f AK |
330 | bool save_return_addr_p; |
331 | ||
29742ba4 | 332 | /* Size of stack frame. */ |
4023fb28 | 333 | HOST_WIDE_INT frame_size; |
adf39f8f AK |
334 | }; |
335 | ||
336 | /* Define the structure for the machine field in struct function. */ | |
337 | ||
d1b38208 | 338 | struct GTY(()) machine_function |
adf39f8f AK |
339 | { |
340 | struct s390_frame_layout frame_layout; | |
fd3cd001 | 341 | |
585539a1 UW |
342 | /* Literal pool base register. */ |
343 | rtx base_reg; | |
344 | ||
91086990 UW |
345 | /* True if we may need to perform branch splitting. */ |
346 | bool split_branches_pending_p; | |
347 | ||
fd3cd001 UW |
348 | /* Some local-dynamic TLS symbol name. */ |
349 | const char *some_ld_name; | |
7bcebb25 AK |
350 | |
351 | bool has_landing_pad_p; | |
4023fb28 UW |
352 | }; |
353 | ||
adf39f8f AK |
354 | /* Few accessor macros for struct cfun->machine->s390_frame_layout. */ |
355 | ||
356 | #define cfun_frame_layout (cfun->machine->frame_layout) | |
357 | #define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs) | |
fb3712f6 | 358 | #define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \ |
9602b6a1 | 359 | cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG) |
adf39f8f AK |
360 | #define cfun_set_fpr_bit(BITNUM) (cfun->machine->frame_layout.fpr_bitmap |= \ |
361 | (1 << (BITNUM))) | |
362 | #define cfun_fpr_bit_p(BITNUM) (!!(cfun->machine->frame_layout.fpr_bitmap & \ | |
363 | (1 << (BITNUM)))) | |
364 | ||
29a79fcf UW |
365 | /* Number of GPRs and FPRs used for argument passing. */ |
366 | #define GP_ARG_NUM_REG 5 | |
367 | #define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2) | |
368 | ||
b5c67a49 AK |
369 | /* A couple of shortcuts. */ |
370 | #define CONST_OK_FOR_J(x) \ | |
371 | CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J") | |
372 | #define CONST_OK_FOR_K(x) \ | |
373 | CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K") | |
ec24698e UW |
374 | #define CONST_OK_FOR_Os(x) \ |
375 | CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os") | |
376 | #define CONST_OK_FOR_Op(x) \ | |
377 | CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op") | |
378 | #define CONST_OK_FOR_On(x) \ | |
379 | CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On") | |
b5c67a49 | 380 | |
74aa8b4b AK |
381 | #define REGNO_PAIR_OK(REGNO, MODE) \ |
382 | (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1)) | |
383 | ||
b0f86a7e | 384 | /* That's the read ahead of the dynamic branch prediction unit in |
65b1d8ea AK |
385 | bytes on a z10 (or higher) CPU. */ |
386 | #define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048) | |
b0f86a7e | 387 | |
c7ff6e7a AK |
388 | static enum machine_mode |
389 | s390_libgcc_cmp_return_mode (void) | |
390 | { | |
391 | return TARGET_64BIT ? DImode : SImode; | |
392 | } | |
393 | ||
394 | static enum machine_mode | |
395 | s390_libgcc_shift_count_mode (void) | |
396 | { | |
397 | return TARGET_64BIT ? DImode : SImode; | |
398 | } | |
399 | ||
9602b6a1 AK |
400 | static enum machine_mode |
401 | s390_unwind_word_mode (void) | |
402 | { | |
403 | return TARGET_64BIT ? DImode : SImode; | |
404 | } | |
405 | ||
4dc19cc0 AK |
406 | /* Return true if the back end supports mode MODE. */ |
407 | static bool | |
408 | s390_scalar_mode_supported_p (enum machine_mode mode) | |
409 | { | |
9602b6a1 AK |
410 | /* In contrast to the default implementation reject TImode constants on 31bit |
411 | TARGET_ZARCH for ABI compliance. */ | |
412 | if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode) | |
413 | return false; | |
414 | ||
4dc19cc0 | 415 | if (DECIMAL_FLOAT_MODE_P (mode)) |
a9ab39d3 | 416 | return default_decimal_float_supported_p (); |
9602b6a1 AK |
417 | |
418 | return default_scalar_mode_supported_p (mode); | |
4dc19cc0 AK |
419 | } |
420 | ||
7bcebb25 AK |
421 | /* Set the has_landing_pad_p flag in struct machine_function to VALUE. */ |
422 | ||
423 | void | |
424 | s390_set_has_landing_pad_p (bool value) | |
425 | { | |
426 | cfun->machine->has_landing_pad_p = value; | |
427 | } | |
29a79fcf | 428 | |
69950452 AS |
429 | /* If two condition code modes are compatible, return a condition code |
430 | mode which is compatible with both. Otherwise, return | |
431 | VOIDmode. */ | |
432 | ||
433 | static enum machine_mode | |
434 | s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2) | |
435 | { | |
436 | if (m1 == m2) | |
437 | return m1; | |
438 | ||
439 | switch (m1) | |
440 | { | |
441 | case CCZmode: | |
442 | if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode | |
443 | || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode) | |
444 | return m2; | |
445 | return VOIDmode; | |
446 | ||
447 | case CCSmode: | |
448 | case CCUmode: | |
449 | case CCTmode: | |
450 | case CCSRmode: | |
451 | case CCURmode: | |
452 | case CCZ1mode: | |
453 | if (m2 == CCZmode) | |
454 | return m1; | |
f4aa3848 | 455 | |
69950452 AS |
456 | return VOIDmode; |
457 | ||
458 | default: | |
459 | return VOIDmode; | |
460 | } | |
461 | return VOIDmode; | |
462 | } | |
463 | ||
994fe660 | 464 | /* Return true if SET either doesn't set the CC register, or else |
c7453384 | 465 | the source and destination have matching CC modes and that |
994fe660 | 466 | CC mode is at least as constrained as REQ_MODE. */ |
c7453384 | 467 | |
3ed99cc9 | 468 | static bool |
9c808aad | 469 | s390_match_ccmode_set (rtx set, enum machine_mode req_mode) |
9db1d521 | 470 | { |
994fe660 | 471 | enum machine_mode set_mode; |
9db1d521 | 472 | |
8d933e31 | 473 | gcc_assert (GET_CODE (set) == SET); |
9db1d521 HP |
474 | |
475 | if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set)))) | |
476 | return 1; | |
477 | ||
478 | set_mode = GET_MODE (SET_DEST (set)); | |
479 | switch (set_mode) | |
480 | { | |
9db1d521 | 481 | case CCSmode: |
07893d4f | 482 | case CCSRmode: |
9db1d521 | 483 | case CCUmode: |
07893d4f | 484 | case CCURmode: |
ba956982 | 485 | case CCLmode: |
07893d4f UW |
486 | case CCL1mode: |
487 | case CCL2mode: | |
5d880bd2 | 488 | case CCL3mode: |
07893d4f UW |
489 | case CCT1mode: |
490 | case CCT2mode: | |
491 | case CCT3mode: | |
492 | if (req_mode != set_mode) | |
ba956982 UW |
493 | return 0; |
494 | break; | |
07893d4f | 495 | |
9db1d521 | 496 | case CCZmode: |
07893d4f UW |
497 | if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode |
498 | && req_mode != CCSRmode && req_mode != CCURmode) | |
9db1d521 HP |
499 | return 0; |
500 | break; | |
0a3bdf9d UW |
501 | |
502 | case CCAPmode: | |
503 | case CCANmode: | |
504 | if (req_mode != CCAmode) | |
505 | return 0; | |
506 | break; | |
c7453384 | 507 | |
9db1d521 | 508 | default: |
8d933e31 | 509 | gcc_unreachable (); |
9db1d521 | 510 | } |
c7453384 | 511 | |
9db1d521 HP |
512 | return (GET_MODE (SET_SRC (set)) == set_mode); |
513 | } | |
514 | ||
c7453384 EC |
515 | /* Return true if every SET in INSN that sets the CC register |
516 | has source and destination with matching CC modes and that | |
517 | CC mode is at least as constrained as REQ_MODE. | |
07893d4f | 518 | If REQ_MODE is VOIDmode, always return false. */ |
c7453384 | 519 | |
3ed99cc9 | 520 | bool |
9c808aad | 521 | s390_match_ccmode (rtx insn, enum machine_mode req_mode) |
9db1d521 HP |
522 | { |
523 | int i; | |
524 | ||
07893d4f UW |
525 | /* s390_tm_ccmode returns VOIDmode to indicate failure. */ |
526 | if (req_mode == VOIDmode) | |
3ed99cc9 | 527 | return false; |
07893d4f | 528 | |
9db1d521 HP |
529 | if (GET_CODE (PATTERN (insn)) == SET) |
530 | return s390_match_ccmode_set (PATTERN (insn), req_mode); | |
531 | ||
532 | if (GET_CODE (PATTERN (insn)) == PARALLEL) | |
533 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) | |
534 | { | |
535 | rtx set = XVECEXP (PATTERN (insn), 0, i); | |
536 | if (GET_CODE (set) == SET) | |
537 | if (!s390_match_ccmode_set (set, req_mode)) | |
3ed99cc9 | 538 | return false; |
9db1d521 HP |
539 | } |
540 | ||
3ed99cc9 | 541 | return true; |
9db1d521 HP |
542 | } |
543 | ||
c7453384 | 544 | /* If a test-under-mask instruction can be used to implement |
07893d4f | 545 | (compare (and ... OP1) OP2), return the CC mode required |
c7453384 | 546 | to do that. Otherwise, return VOIDmode. |
07893d4f UW |
547 | MIXED is true if the instruction can distinguish between |
548 | CC1 and CC2 for mixed selected bits (TMxx), it is false | |
549 | if the instruction cannot (TM). */ | |
550 | ||
551 | enum machine_mode | |
3ed99cc9 | 552 | s390_tm_ccmode (rtx op1, rtx op2, bool mixed) |
07893d4f UW |
553 | { |
554 | int bit0, bit1; | |
555 | ||
556 | /* ??? Fixme: should work on CONST_DOUBLE as well. */ | |
557 | if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT) | |
558 | return VOIDmode; | |
559 | ||
00bda920 AK |
560 | /* Selected bits all zero: CC0. |
561 | e.g.: int a; if ((a & (16 + 128)) == 0) */ | |
07893d4f UW |
562 | if (INTVAL (op2) == 0) |
563 | return CCTmode; | |
564 | ||
f4aa3848 | 565 | /* Selected bits all one: CC3. |
00bda920 | 566 | e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */ |
07893d4f UW |
567 | if (INTVAL (op2) == INTVAL (op1)) |
568 | return CCT3mode; | |
569 | ||
00bda920 AK |
570 | /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.: |
571 | int a; | |
572 | if ((a & (16 + 128)) == 16) -> CCT1 | |
573 | if ((a & (16 + 128)) == 128) -> CCT2 */ | |
07893d4f UW |
574 | if (mixed) |
575 | { | |
576 | bit1 = exact_log2 (INTVAL (op2)); | |
577 | bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2)); | |
578 | if (bit0 != -1 && bit1 != -1) | |
579 | return bit0 > bit1 ? CCT1mode : CCT2mode; | |
580 | } | |
581 | ||
582 | return VOIDmode; | |
583 | } | |
584 | ||
c7453384 EC |
585 | /* Given a comparison code OP (EQ, NE, etc.) and the operands |
586 | OP0 and OP1 of a COMPARE, return the mode to be used for the | |
ba956982 UW |
587 | comparison. */ |
588 | ||
589 | enum machine_mode | |
9c808aad | 590 | s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1) |
ba956982 UW |
591 | { |
592 | switch (code) | |
593 | { | |
594 | case EQ: | |
595 | case NE: | |
26a89301 UW |
596 | if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS) |
597 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) | |
598 | return CCAPmode; | |
0a3bdf9d | 599 | if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT |
b5c67a49 | 600 | && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1)))) |
0a3bdf9d | 601 | return CCAPmode; |
3ef093a8 AK |
602 | if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS |
603 | || GET_CODE (op1) == NEG) | |
604 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) | |
ba956982 UW |
605 | return CCLmode; |
606 | ||
07893d4f UW |
607 | if (GET_CODE (op0) == AND) |
608 | { | |
609 | /* Check whether we can potentially do it via TM. */ | |
610 | enum machine_mode ccmode; | |
611 | ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1); | |
612 | if (ccmode != VOIDmode) | |
613 | { | |
614 | /* Relax CCTmode to CCZmode to allow fall-back to AND | |
615 | if that turns out to be beneficial. */ | |
616 | return ccmode == CCTmode ? CCZmode : ccmode; | |
617 | } | |
618 | } | |
619 | ||
c7453384 | 620 | if (register_operand (op0, HImode) |
07893d4f UW |
621 | && GET_CODE (op1) == CONST_INT |
622 | && (INTVAL (op1) == -1 || INTVAL (op1) == 65535)) | |
623 | return CCT3mode; | |
c7453384 | 624 | if (register_operand (op0, QImode) |
07893d4f UW |
625 | && GET_CODE (op1) == CONST_INT |
626 | && (INTVAL (op1) == -1 || INTVAL (op1) == 255)) | |
627 | return CCT3mode; | |
628 | ||
ba956982 UW |
629 | return CCZmode; |
630 | ||
631 | case LE: | |
632 | case LT: | |
633 | case GE: | |
634 | case GT: | |
00bda920 AK |
635 | /* The only overflow condition of NEG and ABS happens when |
636 | -INT_MAX is used as parameter, which stays negative. So | |
f4aa3848 | 637 | we have an overflow from a positive value to a negative. |
00bda920 | 638 | Using CCAP mode the resulting cc can be used for comparisons. */ |
26a89301 UW |
639 | if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS) |
640 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) | |
641 | return CCAPmode; | |
00bda920 AK |
642 | |
643 | /* If constants are involved in an add instruction it is possible to use | |
644 | the resulting cc for comparisons with zero. Knowing the sign of the | |
35fd3193 | 645 | constant the overflow behavior gets predictable. e.g.: |
f4aa3848 | 646 | int a, b; if ((b = a + c) > 0) |
00bda920 | 647 | with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */ |
26a89301 | 648 | if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT |
b5c67a49 | 649 | && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1)))) |
26a89301 UW |
650 | { |
651 | if (INTVAL (XEXP((op0), 1)) < 0) | |
652 | return CCANmode; | |
653 | else | |
654 | return CCAPmode; | |
655 | } | |
656 | /* Fall through. */ | |
ba956982 UW |
657 | case UNORDERED: |
658 | case ORDERED: | |
659 | case UNEQ: | |
660 | case UNLE: | |
661 | case UNLT: | |
662 | case UNGE: | |
663 | case UNGT: | |
664 | case LTGT: | |
07893d4f UW |
665 | if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND) |
666 | && GET_CODE (op1) != CONST_INT) | |
667 | return CCSRmode; | |
ba956982 UW |
668 | return CCSmode; |
669 | ||
ba956982 UW |
670 | case LTU: |
671 | case GEU: | |
3ef093a8 AK |
672 | if (GET_CODE (op0) == PLUS |
673 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) | |
07893d4f UW |
674 | return CCL1mode; |
675 | ||
676 | if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND) | |
677 | && GET_CODE (op1) != CONST_INT) | |
678 | return CCURmode; | |
679 | return CCUmode; | |
680 | ||
681 | case LEU: | |
ba956982 | 682 | case GTU: |
3ef093a8 AK |
683 | if (GET_CODE (op0) == MINUS |
684 | && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT) | |
07893d4f UW |
685 | return CCL2mode; |
686 | ||
687 | if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND) | |
688 | && GET_CODE (op1) != CONST_INT) | |
689 | return CCURmode; | |
ba956982 UW |
690 | return CCUmode; |
691 | ||
692 | default: | |
8d933e31 | 693 | gcc_unreachable (); |
ba956982 UW |
694 | } |
695 | } | |
696 | ||
68f9c5e2 UW |
697 | /* Replace the comparison OP0 CODE OP1 by a semantically equivalent one |
698 | that we can implement more efficiently. */ | |
699 | ||
700 | void | |
701 | s390_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1) | |
702 | { | |
703 | /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */ | |
704 | if ((*code == EQ || *code == NE) | |
705 | && *op1 == const0_rtx | |
706 | && GET_CODE (*op0) == ZERO_EXTRACT | |
707 | && GET_CODE (XEXP (*op0, 1)) == CONST_INT | |
708 | && GET_CODE (XEXP (*op0, 2)) == CONST_INT | |
709 | && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0)))) | |
710 | { | |
711 | rtx inner = XEXP (*op0, 0); | |
712 | HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner)); | |
713 | HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1)); | |
714 | HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2)); | |
715 | ||
716 | if (len > 0 && len < modesize | |
717 | && pos >= 0 && pos + len <= modesize | |
718 | && modesize <= HOST_BITS_PER_WIDE_INT) | |
719 | { | |
720 | unsigned HOST_WIDE_INT block; | |
721 | block = ((unsigned HOST_WIDE_INT) 1 << len) - 1; | |
722 | block <<= modesize - pos - len; | |
723 | ||
724 | *op0 = gen_rtx_AND (GET_MODE (inner), inner, | |
725 | gen_int_mode (block, GET_MODE (inner))); | |
726 | } | |
727 | } | |
728 | ||
729 | /* Narrow AND of memory against immediate to enable TM. */ | |
730 | if ((*code == EQ || *code == NE) | |
731 | && *op1 == const0_rtx | |
732 | && GET_CODE (*op0) == AND | |
733 | && GET_CODE (XEXP (*op0, 1)) == CONST_INT | |
734 | && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0)))) | |
735 | { | |
736 | rtx inner = XEXP (*op0, 0); | |
737 | rtx mask = XEXP (*op0, 1); | |
738 | ||
739 | /* Ignore paradoxical SUBREGs if all extra bits are masked out. */ | |
740 | if (GET_CODE (inner) == SUBREG | |
741 | && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner))) | |
742 | && (GET_MODE_SIZE (GET_MODE (inner)) | |
743 | >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner)))) | |
744 | && ((INTVAL (mask) | |
745 | & GET_MODE_MASK (GET_MODE (inner)) | |
746 | & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner)))) | |
747 | == 0)) | |
748 | inner = SUBREG_REG (inner); | |
749 | ||
750 | /* Do not change volatile MEMs. */ | |
751 | if (MEM_P (inner) && !MEM_VOLATILE_P (inner)) | |
752 | { | |
753 | int part = s390_single_part (XEXP (*op0, 1), | |
754 | GET_MODE (inner), QImode, 0); | |
755 | if (part >= 0) | |
756 | { | |
757 | mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode); | |
758 | inner = adjust_address_nv (inner, QImode, part); | |
759 | *op0 = gen_rtx_AND (QImode, inner, mask); | |
760 | } | |
761 | } | |
762 | } | |
763 | ||
764 | /* Narrow comparisons against 0xffff to HImode if possible. */ | |
68f9c5e2 UW |
765 | if ((*code == EQ || *code == NE) |
766 | && GET_CODE (*op1) == CONST_INT | |
767 | && INTVAL (*op1) == 0xffff | |
768 | && SCALAR_INT_MODE_P (GET_MODE (*op0)) | |
f4aa3848 | 769 | && (nonzero_bits (*op0, GET_MODE (*op0)) |
68f9c5e2 UW |
770 | & ~(unsigned HOST_WIDE_INT) 0xffff) == 0) |
771 | { | |
772 | *op0 = gen_lowpart (HImode, *op0); | |
773 | *op1 = constm1_rtx; | |
774 | } | |
5b022de5 | 775 | |
638e37c2 | 776 | /* Remove redundant UNSPEC_CCU_TO_INT conversions if possible. */ |
5b022de5 | 777 | if (GET_CODE (*op0) == UNSPEC |
638e37c2 | 778 | && XINT (*op0, 1) == UNSPEC_CCU_TO_INT |
5b022de5 UW |
779 | && XVECLEN (*op0, 0) == 1 |
780 | && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode | |
781 | && GET_CODE (XVECEXP (*op0, 0, 0)) == REG | |
782 | && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM | |
783 | && *op1 == const0_rtx) | |
784 | { | |
785 | enum rtx_code new_code = UNKNOWN; | |
786 | switch (*code) | |
787 | { | |
788 | case EQ: new_code = EQ; break; | |
789 | case NE: new_code = NE; break; | |
02887425 UW |
790 | case LT: new_code = GTU; break; |
791 | case GT: new_code = LTU; break; | |
792 | case LE: new_code = GEU; break; | |
793 | case GE: new_code = LEU; break; | |
5b022de5 UW |
794 | default: break; |
795 | } | |
796 | ||
797 | if (new_code != UNKNOWN) | |
798 | { | |
799 | *op0 = XVECEXP (*op0, 0, 0); | |
800 | *code = new_code; | |
801 | } | |
802 | } | |
69950452 | 803 | |
638e37c2 WG |
804 | /* Remove redundant UNSPEC_CCZ_TO_INT conversions if possible. */ |
805 | if (GET_CODE (*op0) == UNSPEC | |
806 | && XINT (*op0, 1) == UNSPEC_CCZ_TO_INT | |
807 | && XVECLEN (*op0, 0) == 1 | |
808 | && GET_MODE (XVECEXP (*op0, 0, 0)) == CCZmode | |
809 | && GET_CODE (XVECEXP (*op0, 0, 0)) == REG | |
810 | && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM | |
811 | && *op1 == const0_rtx) | |
812 | { | |
813 | enum rtx_code new_code = UNKNOWN; | |
814 | switch (*code) | |
815 | { | |
816 | case EQ: new_code = EQ; break; | |
817 | case NE: new_code = NE; break; | |
818 | default: break; | |
819 | } | |
820 | ||
821 | if (new_code != UNKNOWN) | |
822 | { | |
823 | *op0 = XVECEXP (*op0, 0, 0); | |
824 | *code = new_code; | |
825 | } | |
826 | } | |
827 | ||
69950452 AS |
828 | /* Simplify cascaded EQ, NE with const0_rtx. */ |
829 | if ((*code == NE || *code == EQ) | |
830 | && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE) | |
831 | && GET_MODE (*op0) == SImode | |
832 | && GET_MODE (XEXP (*op0, 0)) == CCZ1mode | |
833 | && REG_P (XEXP (*op0, 0)) | |
834 | && XEXP (*op0, 1) == const0_rtx | |
835 | && *op1 == const0_rtx) | |
836 | { | |
837 | if ((*code == EQ && GET_CODE (*op0) == NE) | |
838 | || (*code == NE && GET_CODE (*op0) == EQ)) | |
839 | *code = EQ; | |
840 | else | |
841 | *code = NE; | |
842 | *op0 = XEXP (*op0, 0); | |
843 | } | |
c5b2a111 UW |
844 | |
845 | /* Prefer register over memory as first operand. */ | |
846 | if (MEM_P (*op0) && REG_P (*op1)) | |
847 | { | |
848 | rtx tem = *op0; *op0 = *op1; *op1 = tem; | |
849 | *code = swap_condition (*code); | |
850 | } | |
68f9c5e2 UW |
851 | } |
852 | ||
6590e19a UW |
853 | /* Emit a compare instruction suitable to implement the comparison |
854 | OP0 CODE OP1. Return the correct condition RTL to be placed in | |
855 | the IF_THEN_ELSE of the conditional branch testing the result. */ | |
856 | ||
857 | rtx | |
858 | s390_emit_compare (enum rtx_code code, rtx op0, rtx op1) | |
859 | { | |
860 | enum machine_mode mode = s390_select_ccmode (code, op0, op1); | |
4a77c72b | 861 | rtx cc; |
6590e19a | 862 | |
e0374221 | 863 | /* Do not output a redundant compare instruction if a compare_and_swap |
69950452 | 864 | pattern already computed the result and the machine modes are compatible. */ |
4a77c72b PB |
865 | if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC) |
866 | { | |
867 | gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode) | |
868 | == GET_MODE (op0)); | |
869 | cc = op0; | |
870 | } | |
e0374221 AS |
871 | else |
872 | { | |
4a77c72b | 873 | cc = gen_rtx_REG (mode, CC_REGNUM); |
e0374221 | 874 | emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1))); |
e0374221 | 875 | } |
4a77c72b | 876 | |
f4aa3848 | 877 | return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx); |
6590e19a UW |
878 | } |
879 | ||
0a2aaacc | 880 | /* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD |
8bb501bb AK |
881 | matches CMP. |
882 | Return the correct condition RTL to be placed in the IF_THEN_ELSE of the | |
883 | conditional branch testing the result. */ | |
884 | ||
885 | static rtx | |
0a2aaacc | 886 | s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem, rtx cmp, rtx new_rtx) |
8bb501bb | 887 | { |
4a77c72b PB |
888 | emit_insn (gen_sync_compare_and_swapsi (old, mem, cmp, new_rtx)); |
889 | return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM), const0_rtx); | |
8bb501bb AK |
890 | } |
891 | ||
6590e19a UW |
892 | /* Emit a jump instruction to TARGET. If COND is NULL_RTX, emit an |
893 | unconditional jump, else a conditional jump under condition COND. */ | |
894 | ||
895 | void | |
896 | s390_emit_jump (rtx target, rtx cond) | |
897 | { | |
898 | rtx insn; | |
899 | ||
900 | target = gen_rtx_LABEL_REF (VOIDmode, target); | |
901 | if (cond) | |
902 | target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx); | |
903 | ||
904 | insn = gen_rtx_SET (VOIDmode, pc_rtx, target); | |
905 | emit_jump_insn (insn); | |
906 | } | |
907 | ||
c7453384 | 908 | /* Return branch condition mask to implement a branch |
5b022de5 | 909 | specified by CODE. Return -1 for invalid comparisons. */ |
ba956982 | 910 | |
0bfc3f69 | 911 | int |
9c808aad | 912 | s390_branch_condition_mask (rtx code) |
c7453384 | 913 | { |
ba956982 UW |
914 | const int CC0 = 1 << 3; |
915 | const int CC1 = 1 << 2; | |
916 | const int CC2 = 1 << 1; | |
917 | const int CC3 = 1 << 0; | |
918 | ||
8d933e31 AS |
919 | gcc_assert (GET_CODE (XEXP (code, 0)) == REG); |
920 | gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM); | |
921 | gcc_assert (XEXP (code, 1) == const0_rtx); | |
ba956982 UW |
922 | |
923 | switch (GET_MODE (XEXP (code, 0))) | |
924 | { | |
925 | case CCZmode: | |
69950452 | 926 | case CCZ1mode: |
ba956982 UW |
927 | switch (GET_CODE (code)) |
928 | { | |
929 | case EQ: return CC0; | |
930 | case NE: return CC1 | CC2 | CC3; | |
5b022de5 | 931 | default: return -1; |
ba956982 UW |
932 | } |
933 | break; | |
934 | ||
07893d4f UW |
935 | case CCT1mode: |
936 | switch (GET_CODE (code)) | |
937 | { | |
938 | case EQ: return CC1; | |
939 | case NE: return CC0 | CC2 | CC3; | |
5b022de5 | 940 | default: return -1; |
07893d4f UW |
941 | } |
942 | break; | |
943 | ||
944 | case CCT2mode: | |
945 | switch (GET_CODE (code)) | |
946 | { | |
947 | case EQ: return CC2; | |
948 | case NE: return CC0 | CC1 | CC3; | |
5b022de5 | 949 | default: return -1; |
07893d4f UW |
950 | } |
951 | break; | |
952 | ||
953 | case CCT3mode: | |
954 | switch (GET_CODE (code)) | |
955 | { | |
956 | case EQ: return CC3; | |
957 | case NE: return CC0 | CC1 | CC2; | |
5b022de5 | 958 | default: return -1; |
07893d4f UW |
959 | } |
960 | break; | |
961 | ||
ba956982 UW |
962 | case CCLmode: |
963 | switch (GET_CODE (code)) | |
964 | { | |
965 | case EQ: return CC0 | CC2; | |
966 | case NE: return CC1 | CC3; | |
5b022de5 | 967 | default: return -1; |
07893d4f UW |
968 | } |
969 | break; | |
970 | ||
971 | case CCL1mode: | |
972 | switch (GET_CODE (code)) | |
973 | { | |
974 | case LTU: return CC2 | CC3; /* carry */ | |
975 | case GEU: return CC0 | CC1; /* no carry */ | |
5b022de5 | 976 | default: return -1; |
07893d4f UW |
977 | } |
978 | break; | |
979 | ||
980 | case CCL2mode: | |
981 | switch (GET_CODE (code)) | |
982 | { | |
983 | case GTU: return CC0 | CC1; /* borrow */ | |
984 | case LEU: return CC2 | CC3; /* no borrow */ | |
5b022de5 | 985 | default: return -1; |
ba956982 UW |
986 | } |
987 | break; | |
988 | ||
5d880bd2 UW |
989 | case CCL3mode: |
990 | switch (GET_CODE (code)) | |
991 | { | |
992 | case EQ: return CC0 | CC2; | |
993 | case NE: return CC1 | CC3; | |
994 | case LTU: return CC1; | |
995 | case GTU: return CC3; | |
996 | case LEU: return CC1 | CC2; | |
997 | case GEU: return CC2 | CC3; | |
5b022de5 | 998 | default: return -1; |
5d880bd2 UW |
999 | } |
1000 | ||
ba956982 UW |
1001 | case CCUmode: |
1002 | switch (GET_CODE (code)) | |
1003 | { | |
1004 | case EQ: return CC0; | |
1005 | case NE: return CC1 | CC2 | CC3; | |
1006 | case LTU: return CC1; | |
1007 | case GTU: return CC2; | |
1008 | case LEU: return CC0 | CC1; | |
1009 | case GEU: return CC0 | CC2; | |
5b022de5 | 1010 | default: return -1; |
ba956982 UW |
1011 | } |
1012 | break; | |
1013 | ||
07893d4f UW |
1014 | case CCURmode: |
1015 | switch (GET_CODE (code)) | |
1016 | { | |
1017 | case EQ: return CC0; | |
1018 | case NE: return CC2 | CC1 | CC3; | |
1019 | case LTU: return CC2; | |
1020 | case GTU: return CC1; | |
1021 | case LEU: return CC0 | CC2; | |
1022 | case GEU: return CC0 | CC1; | |
5b022de5 | 1023 | default: return -1; |
07893d4f UW |
1024 | } |
1025 | break; | |
1026 | ||
0a3bdf9d UW |
1027 | case CCAPmode: |
1028 | switch (GET_CODE (code)) | |
1029 | { | |
1030 | case EQ: return CC0; | |
1031 | case NE: return CC1 | CC2 | CC3; | |
1032 | case LT: return CC1 | CC3; | |
1033 | case GT: return CC2; | |
1034 | case LE: return CC0 | CC1 | CC3; | |
1035 | case GE: return CC0 | CC2; | |
5b022de5 | 1036 | default: return -1; |
0a3bdf9d UW |
1037 | } |
1038 | break; | |
1039 | ||
1040 | case CCANmode: | |
1041 | switch (GET_CODE (code)) | |
1042 | { | |
1043 | case EQ: return CC0; | |
1044 | case NE: return CC1 | CC2 | CC3; | |
1045 | case LT: return CC1; | |
1046 | case GT: return CC2 | CC3; | |
1047 | case LE: return CC0 | CC1; | |
1048 | case GE: return CC0 | CC2 | CC3; | |
5b022de5 | 1049 | default: return -1; |
0a3bdf9d UW |
1050 | } |
1051 | break; | |
1052 | ||
ba956982 UW |
1053 | case CCSmode: |
1054 | switch (GET_CODE (code)) | |
1055 | { | |
1056 | case EQ: return CC0; | |
1057 | case NE: return CC1 | CC2 | CC3; | |
1058 | case LT: return CC1; | |
1059 | case GT: return CC2; | |
1060 | case LE: return CC0 | CC1; | |
1061 | case GE: return CC0 | CC2; | |
1062 | case UNORDERED: return CC3; | |
1063 | case ORDERED: return CC0 | CC1 | CC2; | |
1064 | case UNEQ: return CC0 | CC3; | |
1065 | case UNLT: return CC1 | CC3; | |
1066 | case UNGT: return CC2 | CC3; | |
1067 | case UNLE: return CC0 | CC1 | CC3; | |
1068 | case UNGE: return CC0 | CC2 | CC3; | |
1069 | case LTGT: return CC1 | CC2; | |
5b022de5 | 1070 | default: return -1; |
ba956982 | 1071 | } |
07893d4f UW |
1072 | break; |
1073 | ||
1074 | case CCSRmode: | |
1075 | switch (GET_CODE (code)) | |
1076 | { | |
1077 | case EQ: return CC0; | |
1078 | case NE: return CC2 | CC1 | CC3; | |
1079 | case LT: return CC2; | |
1080 | case GT: return CC1; | |
1081 | case LE: return CC0 | CC2; | |
1082 | case GE: return CC0 | CC1; | |
1083 | case UNORDERED: return CC3; | |
1084 | case ORDERED: return CC0 | CC2 | CC1; | |
1085 | case UNEQ: return CC0 | CC3; | |
1086 | case UNLT: return CC2 | CC3; | |
1087 | case UNGT: return CC1 | CC3; | |
1088 | case UNLE: return CC0 | CC2 | CC3; | |
1089 | case UNGE: return CC0 | CC1 | CC3; | |
1090 | case LTGT: return CC2 | CC1; | |
5b022de5 | 1091 | default: return -1; |
07893d4f UW |
1092 | } |
1093 | break; | |
ba956982 UW |
1094 | |
1095 | default: | |
5b022de5 | 1096 | return -1; |
ba956982 UW |
1097 | } |
1098 | } | |
1099 | ||
963fc8d0 AK |
1100 | |
1101 | /* Return branch condition mask to implement a compare and branch | |
1102 | specified by CODE. Return -1 for invalid comparisons. */ | |
1103 | ||
1104 | int | |
1105 | s390_compare_and_branch_condition_mask (rtx code) | |
1106 | { | |
1107 | const int CC0 = 1 << 3; | |
1108 | const int CC1 = 1 << 2; | |
1109 | const int CC2 = 1 << 1; | |
1110 | ||
1111 | switch (GET_CODE (code)) | |
1112 | { | |
1113 | case EQ: | |
1114 | return CC0; | |
1115 | case NE: | |
1116 | return CC1 | CC2; | |
1117 | case LT: | |
1118 | case LTU: | |
1119 | return CC1; | |
1120 | case GT: | |
1121 | case GTU: | |
1122 | return CC2; | |
1123 | case LE: | |
1124 | case LEU: | |
1125 | return CC0 | CC1; | |
1126 | case GE: | |
1127 | case GEU: | |
1128 | return CC0 | CC2; | |
1129 | default: | |
1130 | gcc_unreachable (); | |
1131 | } | |
1132 | return -1; | |
1133 | } | |
1134 | ||
c7453384 EC |
1135 | /* If INV is false, return assembler mnemonic string to implement |
1136 | a branch specified by CODE. If INV is true, return mnemonic | |
ba956982 UW |
1137 | for the corresponding inverted branch. */ |
1138 | ||
1139 | static const char * | |
9c808aad | 1140 | s390_branch_condition_mnemonic (rtx code, int inv) |
ba956982 | 1141 | { |
963fc8d0 AK |
1142 | int mask; |
1143 | ||
0139adca | 1144 | static const char *const mnemonic[16] = |
ba956982 UW |
1145 | { |
1146 | NULL, "o", "h", "nle", | |
1147 | "l", "nhe", "lh", "ne", | |
1148 | "e", "nlh", "he", "nl", | |
1149 | "le", "nh", "no", NULL | |
1150 | }; | |
1151 | ||
963fc8d0 AK |
1152 | if (GET_CODE (XEXP (code, 0)) == REG |
1153 | && REGNO (XEXP (code, 0)) == CC_REGNUM | |
1154 | && XEXP (code, 1) == const0_rtx) | |
1155 | mask = s390_branch_condition_mask (code); | |
1156 | else | |
1157 | mask = s390_compare_and_branch_condition_mask (code); | |
1158 | ||
5b022de5 | 1159 | gcc_assert (mask >= 0); |
ba956982 UW |
1160 | |
1161 | if (inv) | |
1162 | mask ^= 15; | |
1163 | ||
8d933e31 | 1164 | gcc_assert (mask >= 1 && mask <= 14); |
ba956982 UW |
1165 | |
1166 | return mnemonic[mask]; | |
1167 | } | |
1168 | ||
f19a9af7 AK |
1169 | /* Return the part of op which has a value different from def. |
1170 | The size of the part is determined by mode. | |
38899e29 | 1171 | Use this function only if you already know that op really |
f19a9af7 | 1172 | contains such a part. */ |
4023fb28 | 1173 | |
f19a9af7 AK |
1174 | unsigned HOST_WIDE_INT |
1175 | s390_extract_part (rtx op, enum machine_mode mode, int def) | |
4023fb28 | 1176 | { |
f19a9af7 AK |
1177 | unsigned HOST_WIDE_INT value = 0; |
1178 | int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode); | |
1179 | int part_bits = GET_MODE_BITSIZE (mode); | |
c4d50129 AK |
1180 | unsigned HOST_WIDE_INT part_mask |
1181 | = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1; | |
f19a9af7 | 1182 | int i; |
38899e29 | 1183 | |
f19a9af7 | 1184 | for (i = 0; i < max_parts; i++) |
4023fb28 | 1185 | { |
f19a9af7 AK |
1186 | if (i == 0) |
1187 | value = (unsigned HOST_WIDE_INT) INTVAL (op); | |
4023fb28 | 1188 | else |
f19a9af7 | 1189 | value >>= part_bits; |
38899e29 | 1190 | |
f19a9af7 AK |
1191 | if ((value & part_mask) != (def & part_mask)) |
1192 | return value & part_mask; | |
4023fb28 | 1193 | } |
38899e29 | 1194 | |
8d933e31 | 1195 | gcc_unreachable (); |
4023fb28 UW |
1196 | } |
1197 | ||
1198 | /* If OP is an integer constant of mode MODE with exactly one | |
f19a9af7 AK |
1199 | part of mode PART_MODE unequal to DEF, return the number of that |
1200 | part. Otherwise, return -1. */ | |
4023fb28 UW |
1201 | |
1202 | int | |
38899e29 EC |
1203 | s390_single_part (rtx op, |
1204 | enum machine_mode mode, | |
f19a9af7 AK |
1205 | enum machine_mode part_mode, |
1206 | int def) | |
1207 | { | |
1208 | unsigned HOST_WIDE_INT value = 0; | |
1209 | int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode); | |
c4d50129 AK |
1210 | unsigned HOST_WIDE_INT part_mask |
1211 | = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1; | |
f19a9af7 AK |
1212 | int i, part = -1; |
1213 | ||
1214 | if (GET_CODE (op) != CONST_INT) | |
1215 | return -1; | |
38899e29 | 1216 | |
f19a9af7 AK |
1217 | for (i = 0; i < n_parts; i++) |
1218 | { | |
1219 | if (i == 0) | |
1220 | value = (unsigned HOST_WIDE_INT) INTVAL (op); | |
4023fb28 | 1221 | else |
f19a9af7 | 1222 | value >>= GET_MODE_BITSIZE (part_mode); |
38899e29 | 1223 | |
f19a9af7 AK |
1224 | if ((value & part_mask) != (def & part_mask)) |
1225 | { | |
1226 | if (part != -1) | |
1227 | return -1; | |
1228 | else | |
1229 | part = i; | |
1230 | } | |
4023fb28 | 1231 | } |
f19a9af7 | 1232 | return part == -1 ? -1 : n_parts - 1 - part; |
4023fb28 UW |
1233 | } |
1234 | ||
963fc8d0 AK |
1235 | /* Return true if IN contains a contiguous bitfield in the lower SIZE |
1236 | bits and no other bits are set in IN. POS and LENGTH can be used | |
1237 | to obtain the start position and the length of the bitfield. | |
1238 | ||
1239 | POS gives the position of the first bit of the bitfield counting | |
1240 | from the lowest order bit starting with zero. In order to use this | |
1241 | value for S/390 instructions this has to be converted to "bits big | |
1242 | endian" style. */ | |
1243 | ||
1244 | bool | |
1245 | s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size, | |
1246 | int *pos, int *length) | |
1247 | { | |
1248 | int tmp_pos = 0; | |
1249 | int tmp_length = 0; | |
1250 | int i; | |
1251 | unsigned HOST_WIDE_INT mask = 1ULL; | |
1252 | bool contiguous = false; | |
1253 | ||
1254 | for (i = 0; i < size; mask <<= 1, i++) | |
1255 | { | |
1256 | if (contiguous) | |
1257 | { | |
1258 | if (mask & in) | |
1259 | tmp_length++; | |
1260 | else | |
1261 | break; | |
1262 | } | |
1263 | else | |
1264 | { | |
1265 | if (mask & in) | |
1266 | { | |
1267 | contiguous = true; | |
1268 | tmp_length++; | |
1269 | } | |
1270 | else | |
1271 | tmp_pos++; | |
1272 | } | |
1273 | } | |
1274 | ||
1275 | if (!tmp_length) | |
1276 | return false; | |
1277 | ||
1278 | /* Calculate a mask for all bits beyond the contiguous bits. */ | |
1279 | mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1)); | |
1280 | ||
1281 | if (mask & in) | |
1282 | return false; | |
1283 | ||
1284 | if (tmp_length + tmp_pos - 1 > size) | |
1285 | return false; | |
1286 | ||
1287 | if (length) | |
1288 | *length = tmp_length; | |
1289 | ||
1290 | if (pos) | |
1291 | *pos = tmp_pos; | |
1292 | ||
1293 | return true; | |
1294 | } | |
1295 | ||
c7453384 EC |
1296 | /* Check whether we can (and want to) split a double-word |
1297 | move in mode MODE from SRC to DST into two single-word | |
dc65c307 UW |
1298 | moves, moving the subword FIRST_SUBWORD first. */ |
1299 | ||
1300 | bool | |
9c808aad | 1301 | s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword) |
dc65c307 UW |
1302 | { |
1303 | /* Floating point registers cannot be split. */ | |
1304 | if (FP_REG_P (src) || FP_REG_P (dst)) | |
1305 | return false; | |
1306 | ||
fae778eb | 1307 | /* We don't need to split if operands are directly accessible. */ |
dc65c307 UW |
1308 | if (s_operand (src, mode) || s_operand (dst, mode)) |
1309 | return false; | |
1310 | ||
1311 | /* Non-offsettable memory references cannot be split. */ | |
1312 | if ((GET_CODE (src) == MEM && !offsettable_memref_p (src)) | |
1313 | || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst))) | |
1314 | return false; | |
1315 | ||
1316 | /* Moving the first subword must not clobber a register | |
1317 | needed to move the second subword. */ | |
1318 | if (register_operand (dst, mode)) | |
1319 | { | |
1320 | rtx subreg = operand_subword (dst, first_subword, 0, mode); | |
1321 | if (reg_overlap_mentioned_p (subreg, src)) | |
1322 | return false; | |
1323 | } | |
1324 | ||
1325 | return true; | |
1326 | } | |
1327 | ||
bcf8c1cc AK |
1328 | /* Return true if it can be proven that [MEM1, MEM1 + SIZE] |
1329 | and [MEM2, MEM2 + SIZE] do overlap and false | |
1330 | otherwise. */ | |
1331 | ||
1332 | bool | |
1333 | s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size) | |
1334 | { | |
1335 | rtx addr1, addr2, addr_delta; | |
1336 | HOST_WIDE_INT delta; | |
1337 | ||
1338 | if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM) | |
1339 | return true; | |
1340 | ||
1341 | if (size == 0) | |
1342 | return false; | |
1343 | ||
1344 | addr1 = XEXP (mem1, 0); | |
1345 | addr2 = XEXP (mem2, 0); | |
1346 | ||
1347 | addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1); | |
1348 | ||
1349 | /* This overlapping check is used by peepholes merging memory block operations. | |
1350 | Overlapping operations would otherwise be recognized by the S/390 hardware | |
f4aa3848 | 1351 | and would fall back to a slower implementation. Allowing overlapping |
bcf8c1cc | 1352 | operations would lead to slow code but not to wrong code. Therefore we are |
f4aa3848 | 1353 | somewhat optimistic if we cannot prove that the memory blocks are |
bcf8c1cc AK |
1354 | overlapping. |
1355 | That's why we return false here although this may accept operations on | |
1356 | overlapping memory areas. */ | |
1357 | if (!addr_delta || GET_CODE (addr_delta) != CONST_INT) | |
1358 | return false; | |
1359 | ||
1360 | delta = INTVAL (addr_delta); | |
1361 | ||
1362 | if (delta == 0 | |
1363 | || (delta > 0 && delta < size) | |
1364 | || (delta < 0 && -delta < size)) | |
1365 | return true; | |
1366 | ||
1367 | return false; | |
1368 | } | |
1369 | ||
19b63d8e UW |
1370 | /* Check whether the address of memory reference MEM2 equals exactly |
1371 | the address of memory reference MEM1 plus DELTA. Return true if | |
1372 | we can prove this to be the case, false otherwise. */ | |
1373 | ||
1374 | bool | |
1375 | s390_offset_p (rtx mem1, rtx mem2, rtx delta) | |
1376 | { | |
1377 | rtx addr1, addr2, addr_delta; | |
1378 | ||
1379 | if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM) | |
1380 | return false; | |
1381 | ||
1382 | addr1 = XEXP (mem1, 0); | |
1383 | addr2 = XEXP (mem2, 0); | |
1384 | ||
1385 | addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1); | |
1386 | if (!addr_delta || !rtx_equal_p (addr_delta, delta)) | |
1387 | return false; | |
1388 | ||
1389 | return true; | |
1390 | } | |
1391 | ||
8cb66696 UW |
1392 | /* Expand logical operator CODE in mode MODE with operands OPERANDS. */ |
1393 | ||
1394 | void | |
1395 | s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode, | |
1396 | rtx *operands) | |
1397 | { | |
1398 | enum machine_mode wmode = mode; | |
1399 | rtx dst = operands[0]; | |
1400 | rtx src1 = operands[1]; | |
1401 | rtx src2 = operands[2]; | |
1402 | rtx op, clob, tem; | |
1403 | ||
1404 | /* If we cannot handle the operation directly, use a temp register. */ | |
1405 | if (!s390_logical_operator_ok_p (operands)) | |
1406 | dst = gen_reg_rtx (mode); | |
1407 | ||
1408 | /* QImode and HImode patterns make sense only if we have a destination | |
1409 | in memory. Otherwise perform the operation in SImode. */ | |
1410 | if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM) | |
1411 | wmode = SImode; | |
1412 | ||
1413 | /* Widen operands if required. */ | |
1414 | if (mode != wmode) | |
1415 | { | |
1416 | if (GET_CODE (dst) == SUBREG | |
1417 | && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0) | |
1418 | dst = tem; | |
1419 | else if (REG_P (dst)) | |
1420 | dst = gen_rtx_SUBREG (wmode, dst, 0); | |
1421 | else | |
1422 | dst = gen_reg_rtx (wmode); | |
1423 | ||
1424 | if (GET_CODE (src1) == SUBREG | |
1425 | && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0) | |
1426 | src1 = tem; | |
1427 | else if (GET_MODE (src1) != VOIDmode) | |
1428 | src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0); | |
1429 | ||
1430 | if (GET_CODE (src2) == SUBREG | |
1431 | && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0) | |
1432 | src2 = tem; | |
1433 | else if (GET_MODE (src2) != VOIDmode) | |
1434 | src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0); | |
1435 | } | |
1436 | ||
1437 | /* Emit the instruction. */ | |
1438 | op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2)); | |
1439 | clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); | |
1440 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob))); | |
1441 | ||
1442 | /* Fix up the destination if needed. */ | |
1443 | if (dst != operands[0]) | |
1444 | emit_move_insn (operands[0], gen_lowpart (mode, dst)); | |
1445 | } | |
1446 | ||
1447 | /* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */ | |
1448 | ||
1449 | bool | |
1450 | s390_logical_operator_ok_p (rtx *operands) | |
1451 | { | |
1452 | /* If the destination operand is in memory, it needs to coincide | |
1453 | with one of the source operands. After reload, it has to be | |
1454 | the first source operand. */ | |
1455 | if (GET_CODE (operands[0]) == MEM) | |
1456 | return rtx_equal_p (operands[0], operands[1]) | |
1457 | || (!reload_completed && rtx_equal_p (operands[0], operands[2])); | |
1458 | ||
1459 | return true; | |
1460 | } | |
1461 | ||
0dfa6c5e UW |
1462 | /* Narrow logical operation CODE of memory operand MEMOP with immediate |
1463 | operand IMMOP to switch from SS to SI type instructions. */ | |
1464 | ||
1465 | void | |
1466 | s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop) | |
1467 | { | |
1468 | int def = code == AND ? -1 : 0; | |
1469 | HOST_WIDE_INT mask; | |
1470 | int part; | |
1471 | ||
1472 | gcc_assert (GET_CODE (*memop) == MEM); | |
1473 | gcc_assert (!MEM_VOLATILE_P (*memop)); | |
1474 | ||
1475 | mask = s390_extract_part (*immop, QImode, def); | |
1476 | part = s390_single_part (*immop, GET_MODE (*memop), QImode, def); | |
1477 | gcc_assert (part >= 0); | |
1478 | ||
1479 | *memop = adjust_address (*memop, QImode, part); | |
1480 | *immop = gen_int_mode (mask, QImode); | |
1481 | } | |
1482 | ||
ba956982 | 1483 | |
ab96de7e AS |
1484 | /* How to allocate a 'struct machine_function'. */ |
1485 | ||
1486 | static struct machine_function * | |
1487 | s390_init_machine_status (void) | |
1488 | { | |
a9429e29 | 1489 | return ggc_alloc_cleared_machine_function (); |
ab96de7e AS |
1490 | } |
1491 | ||
c7453384 | 1492 | /* Change optimizations to be performed, depending on the |
3020190e | 1493 | optimization level. */ |
994fe660 | 1494 | |
3020190e JM |
1495 | static const struct default_options s390_option_optimization_table[] = |
1496 | { | |
1497 | { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 }, | |
994fe660 | 1498 | |
3020190e JM |
1499 | /* ??? There are apparently still problems with -fcaller-saves. */ |
1500 | { OPT_LEVELS_ALL, OPT_fcaller_saves, NULL, 0 }, | |
9db1d521 | 1501 | |
3020190e JM |
1502 | /* Use MVCLE instructions to decrease code size if requested. */ |
1503 | { OPT_LEVELS_SIZE, OPT_mmvcle, NULL, 1 }, | |
2120e3cd | 1504 | |
3020190e JM |
1505 | { OPT_LEVELS_NONE, 0, NULL, 0 } |
1506 | }; | |
9db1d521 | 1507 | |
7e4aae92 JM |
1508 | /* Implement TARGET_OPTION_INIT_STRUCT. */ |
1509 | ||
1510 | static void | |
1511 | s390_option_init_struct (struct gcc_options *opts) | |
1512 | { | |
1513 | /* By default, always emit DWARF-2 unwind info. This allows debugging | |
1514 | without maintaining a stack frame back-chain. */ | |
1515 | opts->x_flag_asynchronous_unwind_tables = 1; | |
1516 | } | |
1517 | ||
f5db779b RS |
1518 | /* Return true if ARG is the name of a processor. Set *TYPE and *FLAGS |
1519 | to the associated processor_type and processor_flags if so. */ | |
1520 | ||
1521 | static bool | |
1522 | s390_handle_arch_option (const char *arg, | |
1523 | enum processor_type *type, | |
81f40b79 | 1524 | int *flags) |
4023fb28 | 1525 | { |
1fec52be HP |
1526 | static struct pta |
1527 | { | |
1528 | const char *const name; /* processor name or nickname. */ | |
1529 | const enum processor_type processor; | |
81f40b79 | 1530 | const int flags; /* From enum processor_flags. */ |
1fec52be HP |
1531 | } |
1532 | const processor_alias_table[] = | |
1533 | { | |
f13e0d4e UW |
1534 | {"g5", PROCESSOR_9672_G5, PF_IEEE_FLOAT}, |
1535 | {"g6", PROCESSOR_9672_G6, PF_IEEE_FLOAT}, | |
1536 | {"z900", PROCESSOR_2064_Z900, PF_IEEE_FLOAT | PF_ZARCH}, | |
c7453384 | 1537 | {"z990", PROCESSOR_2084_Z990, PF_IEEE_FLOAT | PF_ZARCH |
f13e0d4e | 1538 | | PF_LONG_DISPLACEMENT}, |
ec24698e UW |
1539 | {"z9-109", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH |
1540 | | PF_LONG_DISPLACEMENT | PF_EXTIMM}, | |
3443392a AK |
1541 | {"z9-ec", PROCESSOR_2094_Z9_109, PF_IEEE_FLOAT | PF_ZARCH |
1542 | | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP }, | |
93538e8e | 1543 | {"z10", PROCESSOR_2097_Z10, PF_IEEE_FLOAT | PF_ZARCH |
65b1d8ea AK |
1544 | | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10}, |
1545 | {"z196", PROCESSOR_2817_Z196, PF_IEEE_FLOAT | PF_ZARCH | |
1546 | | PF_LONG_DISPLACEMENT | PF_EXTIMM | PF_DFP | PF_Z10 | PF_Z196 }, | |
1fec52be | 1547 | }; |
f5db779b RS |
1548 | size_t i; |
1549 | ||
1550 | for (i = 0; i < ARRAY_SIZE (processor_alias_table); i++) | |
1551 | if (strcmp (arg, processor_alias_table[i].name) == 0) | |
1552 | { | |
1553 | *type = processor_alias_table[i].processor; | |
1554 | *flags = processor_alias_table[i].flags; | |
1555 | return true; | |
1556 | } | |
7876e2b5 AK |
1557 | |
1558 | *type = PROCESSOR_max; | |
1559 | *flags = 0; | |
f5db779b RS |
1560 | return false; |
1561 | } | |
1562 | ||
1563 | /* Implement TARGET_HANDLE_OPTION. */ | |
1fec52be | 1564 | |
f5db779b RS |
1565 | static bool |
1566 | s390_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) | |
1567 | { | |
1568 | switch (code) | |
1569 | { | |
1570 | case OPT_march_: | |
f5db779b RS |
1571 | return s390_handle_arch_option (arg, &s390_arch, &s390_arch_flags); |
1572 | ||
1573 | case OPT_mstack_guard_: | |
1574 | if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_guard) != 1) | |
1575 | return false; | |
1576 | if (exact_log2 (s390_stack_guard) == -1) | |
1577 | error ("stack guard value must be an exact power of 2"); | |
1578 | return true; | |
1579 | ||
1580 | case OPT_mstack_size_: | |
1581 | if (sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_stack_size) != 1) | |
1582 | return false; | |
1583 | if (exact_log2 (s390_stack_size) == -1) | |
1584 | error ("stack size must be an exact power of 2"); | |
1585 | return true; | |
1586 | ||
1587 | case OPT_mtune_: | |
1588 | return s390_handle_arch_option (arg, &s390_tune, &s390_tune_flags); | |
1589 | ||
1590 | case OPT_mwarn_framesize_: | |
1591 | return sscanf (arg, HOST_WIDE_INT_PRINT_DEC, &s390_warn_framesize) == 1; | |
1592 | ||
1593 | default: | |
1594 | return true; | |
1595 | } | |
1596 | } | |
1fec52be | 1597 | |
c5387660 JM |
1598 | static void |
1599 | s390_option_override (void) | |
f5db779b | 1600 | { |
29742ba4 HP |
1601 | /* Set up function hooks. */ |
1602 | init_machine_status = s390_init_machine_status; | |
f13e0d4e UW |
1603 | |
1604 | /* Architecture mode defaults according to ABI. */ | |
1605 | if (!(target_flags_explicit & MASK_ZARCH)) | |
1606 | { | |
1607 | if (TARGET_64BIT) | |
1608 | target_flags |= MASK_ZARCH; | |
1609 | else | |
1610 | target_flags &= ~MASK_ZARCH; | |
1611 | } | |
1612 | ||
1613 | /* Determine processor architectural level. */ | |
1fec52be | 1614 | if (!s390_arch_string) |
f5db779b RS |
1615 | { |
1616 | s390_arch_string = TARGET_ZARCH? "z900" : "g5"; | |
1617 | s390_handle_arch_option (s390_arch_string, &s390_arch, &s390_arch_flags); | |
1618 | } | |
1fec52be | 1619 | |
7876e2b5 AK |
1620 | /* This check is triggered when the user specified a wrong -march= |
1621 | string and prevents subsequent error messages from being | |
1622 | issued. */ | |
1623 | if (s390_arch == PROCESSOR_max) | |
1624 | return; | |
1625 | ||
f13e0d4e | 1626 | /* Determine processor to tune for. */ |
f5db779b | 1627 | if (s390_tune == PROCESSOR_max) |
1fec52be | 1628 | { |
f13e0d4e UW |
1629 | s390_tune = s390_arch; |
1630 | s390_tune_flags = s390_arch_flags; | |
1fec52be HP |
1631 | } |
1632 | ||
f13e0d4e | 1633 | /* Sanity checks. */ |
3443392a | 1634 | if (TARGET_ZARCH && !TARGET_CPU_ZARCH) |
c85ce869 | 1635 | error ("z/Architecture mode not supported on %s", s390_arch_string); |
f13e0d4e | 1636 | if (TARGET_64BIT && !TARGET_ZARCH) |
c85ce869 | 1637 | error ("64-bit ABI not supported in ESA/390 mode"); |
d75f90f1 | 1638 | |
47d94c1a | 1639 | if (TARGET_HARD_DFP && !TARGET_DFP) |
3443392a | 1640 | { |
47d94c1a | 1641 | if (target_flags_explicit & MASK_HARD_DFP) |
3443392a AK |
1642 | { |
1643 | if (!TARGET_CPU_DFP) | |
d8a07487 | 1644 | error ("hardware decimal floating point instructions" |
3443392a AK |
1645 | " not available on %s", s390_arch_string); |
1646 | if (!TARGET_ZARCH) | |
d8a07487 | 1647 | error ("hardware decimal floating point instructions" |
3443392a AK |
1648 | " not available in ESA/390 mode"); |
1649 | } | |
1650 | else | |
47d94c1a | 1651 | target_flags &= ~MASK_HARD_DFP; |
3443392a AK |
1652 | } |
1653 | ||
1654 | if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT) | |
1655 | { | |
47d94c1a | 1656 | if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP) |
d8a07487 | 1657 | error ("-mhard-dfp can%'t be used in conjunction with -msoft-float"); |
3443392a | 1658 | |
47d94c1a | 1659 | target_flags &= ~MASK_HARD_DFP; |
3443392a AK |
1660 | } |
1661 | ||
017e0eb9 | 1662 | /* Set processor cost function. */ |
93538e8e AK |
1663 | switch (s390_tune) |
1664 | { | |
1665 | case PROCESSOR_2084_Z990: | |
1666 | s390_cost = &z990_cost; | |
1667 | break; | |
1668 | case PROCESSOR_2094_Z9_109: | |
1669 | s390_cost = &z9_109_cost; | |
1670 | break; | |
1671 | case PROCESSOR_2097_Z10: | |
1672 | s390_cost = &z10_cost; | |
65b1d8ea AK |
1673 | case PROCESSOR_2817_Z196: |
1674 | s390_cost = &z196_cost; | |
93538e8e AK |
1675 | break; |
1676 | default: | |
1677 | s390_cost = &z900_cost; | |
1678 | } | |
1679 | ||
6b78f6be AK |
1680 | if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT) |
1681 | error ("-mbackchain -mpacked-stack -mhard-float are not supported " | |
c85ce869 | 1682 | "in combination"); |
6b78f6be | 1683 | |
f5db779b | 1684 | if (s390_stack_size) |
d75f90f1 | 1685 | { |
690e7b63 | 1686 | if (s390_stack_guard >= s390_stack_size) |
f5db779b | 1687 | error ("stack size must be greater than the stack guard value"); |
f695eccf AK |
1688 | else if (s390_stack_size > 1 << 16) |
1689 | error ("stack size must not be greater than 64k"); | |
d75f90f1 | 1690 | } |
f5db779b | 1691 | else if (s390_stack_guard) |
f4aa3848 | 1692 | error ("-mstack-guard implies use of -mstack-size"); |
ed965309 JJ |
1693 | |
1694 | #ifdef TARGET_DEFAULT_LONG_DOUBLE_128 | |
1695 | if (!(target_flags_explicit & MASK_LONG_DOUBLE_128)) | |
1696 | target_flags |= MASK_LONG_DOUBLE_128; | |
1697 | #endif | |
ff5b964d | 1698 | |
65b1d8ea AK |
1699 | if (s390_tune == PROCESSOR_2097_Z10 |
1700 | || s390_tune == PROCESSOR_2817_Z196) | |
cc6ae6a1 | 1701 | { |
48476d13 JM |
1702 | maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100, |
1703 | global_options.x_param_values, | |
1704 | global_options_set.x_param_values); | |
1705 | maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32, | |
1706 | global_options.x_param_values, | |
1707 | global_options_set.x_param_values); | |
1708 | maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000, | |
1709 | global_options.x_param_values, | |
1710 | global_options_set.x_param_values); | |
1711 | maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64, | |
1712 | global_options.x_param_values, | |
1713 | global_options_set.x_param_values); | |
cc6ae6a1 | 1714 | } |
dc2f28c5 | 1715 | |
48476d13 JM |
1716 | maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256, |
1717 | global_options.x_param_values, | |
1718 | global_options_set.x_param_values); | |
24a235c8 | 1719 | /* values for loop prefetching */ |
48476d13 JM |
1720 | maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256, |
1721 | global_options.x_param_values, | |
1722 | global_options_set.x_param_values); | |
1723 | maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128, | |
1724 | global_options.x_param_values, | |
1725 | global_options_set.x_param_values); | |
24a235c8 CB |
1726 | /* s390 has more than 2 levels and the size is much larger. Since |
1727 | we are always running virtualized assume that we only get a small | |
1728 | part of the caches above l1. */ | |
48476d13 JM |
1729 | maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500, |
1730 | global_options.x_param_values, | |
1731 | global_options_set.x_param_values); | |
1732 | maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2, | |
1733 | global_options.x_param_values, | |
1734 | global_options_set.x_param_values); | |
1735 | maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6, | |
1736 | global_options.x_param_values, | |
1737 | global_options_set.x_param_values); | |
ca1930ce | 1738 | |
3020190e | 1739 | /* This cannot reside in s390_option_optimization_table since HAVE_prefetch |
c3ac3ddf CB |
1740 | requires the arch flags to be evaluated already. Since prefetching |
1741 | is beneficial on s390, we enable it if available. */ | |
1742 | if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3) | |
ca1930ce | 1743 | flag_prefetch_loop_arrays = 1; |
29742ba4 | 1744 | } |
9db1d521 HP |
1745 | |
1746 | /* Map for smallest class containing reg regno. */ | |
1747 | ||
0139adca | 1748 | const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] = |
9db1d521 HP |
1749 | { GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, |
1750 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
1751 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
1752 | ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, | |
1753 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
1754 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
1755 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
1756 | FP_REGS, FP_REGS, FP_REGS, FP_REGS, | |
c5aa1d12 UW |
1757 | ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS, |
1758 | ACCESS_REGS, ACCESS_REGS | |
9db1d521 HP |
1759 | }; |
1760 | ||
077dab3b HP |
1761 | /* Return attribute type of insn. */ |
1762 | ||
1763 | static enum attr_type | |
9c808aad | 1764 | s390_safe_attr_type (rtx insn) |
077dab3b HP |
1765 | { |
1766 | if (recog_memoized (insn) >= 0) | |
1767 | return get_attr_type (insn); | |
1768 | else | |
1769 | return TYPE_NONE; | |
1770 | } | |
9db1d521 | 1771 | |
d3632d41 UW |
1772 | /* Return true if DISP is a valid short displacement. */ |
1773 | ||
3ed99cc9 | 1774 | static bool |
9c808aad | 1775 | s390_short_displacement (rtx disp) |
d3632d41 UW |
1776 | { |
1777 | /* No displacement is OK. */ | |
1778 | if (!disp) | |
3ed99cc9 | 1779 | return true; |
d3632d41 | 1780 | |
4fe6dea8 AK |
1781 | /* Without the long displacement facility we don't need to |
1782 | distingiush between long and short displacement. */ | |
1783 | if (!TARGET_LONG_DISPLACEMENT) | |
1784 | return true; | |
1785 | ||
d3632d41 UW |
1786 | /* Integer displacement in range. */ |
1787 | if (GET_CODE (disp) == CONST_INT) | |
1788 | return INTVAL (disp) >= 0 && INTVAL (disp) < 4096; | |
1789 | ||
1790 | /* GOT offset is not OK, the GOT can be large. */ | |
1791 | if (GET_CODE (disp) == CONST | |
1792 | && GET_CODE (XEXP (disp, 0)) == UNSPEC | |
227a39fa UW |
1793 | && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT |
1794 | || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF)) | |
3ed99cc9 | 1795 | return false; |
d3632d41 UW |
1796 | |
1797 | /* All other symbolic constants are literal pool references, | |
1798 | which are OK as the literal pool must be small. */ | |
1799 | if (GET_CODE (disp) == CONST) | |
3ed99cc9 | 1800 | return true; |
d3632d41 | 1801 | |
3ed99cc9 | 1802 | return false; |
d3632d41 UW |
1803 | } |
1804 | ||
ab96de7e AS |
1805 | /* Decompose a RTL expression ADDR for a memory address into |
1806 | its components, returned in OUT. | |
ccfc6cc8 | 1807 | |
3ed99cc9 | 1808 | Returns false if ADDR is not a valid memory address, true |
ab96de7e AS |
1809 | otherwise. If OUT is NULL, don't return the components, |
1810 | but check for validity only. | |
ccfc6cc8 | 1811 | |
ab96de7e AS |
1812 | Note: Only addresses in canonical form are recognized. |
1813 | LEGITIMIZE_ADDRESS should convert non-canonical forms to the | |
1814 | canonical form so that they will be recognized. */ | |
f19a9af7 | 1815 | |
ab96de7e | 1816 | static int |
5d81b82b | 1817 | s390_decompose_address (rtx addr, struct s390_address *out) |
ab96de7e AS |
1818 | { |
1819 | HOST_WIDE_INT offset = 0; | |
1820 | rtx base = NULL_RTX; | |
1821 | rtx indx = NULL_RTX; | |
1822 | rtx disp = NULL_RTX; | |
1823 | rtx orig_disp; | |
3ed99cc9 AS |
1824 | bool pointer = false; |
1825 | bool base_ptr = false; | |
1826 | bool indx_ptr = false; | |
f01cf809 UW |
1827 | bool literal_pool = false; |
1828 | ||
1829 | /* We may need to substitute the literal pool base register into the address | |
1830 | below. However, at this point we do not know which register is going to | |
1831 | be used as base, so we substitute the arg pointer register. This is going | |
1832 | to be treated as holding a pointer below -- it shouldn't be used for any | |
1833 | other purpose. */ | |
1834 | rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM); | |
0dfa6c5e | 1835 | |
ab96de7e | 1836 | /* Decompose address into base + index + displacement. */ |
0dfa6c5e | 1837 | |
ab96de7e AS |
1838 | if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC) |
1839 | base = addr; | |
0dfa6c5e | 1840 | |
ab96de7e | 1841 | else if (GET_CODE (addr) == PLUS) |
e221ef54 | 1842 | { |
ab96de7e AS |
1843 | rtx op0 = XEXP (addr, 0); |
1844 | rtx op1 = XEXP (addr, 1); | |
1845 | enum rtx_code code0 = GET_CODE (op0); | |
1846 | enum rtx_code code1 = GET_CODE (op1); | |
e221ef54 | 1847 | |
ab96de7e AS |
1848 | if (code0 == REG || code0 == UNSPEC) |
1849 | { | |
1850 | if (code1 == REG || code1 == UNSPEC) | |
1851 | { | |
1852 | indx = op0; /* index + base */ | |
1853 | base = op1; | |
1854 | } | |
e221ef54 | 1855 | |
ab96de7e AS |
1856 | else |
1857 | { | |
1858 | base = op0; /* base + displacement */ | |
1859 | disp = op1; | |
1860 | } | |
1861 | } | |
ccfc6cc8 | 1862 | |
ab96de7e | 1863 | else if (code0 == PLUS) |
d3632d41 | 1864 | { |
ab96de7e AS |
1865 | indx = XEXP (op0, 0); /* index + base + disp */ |
1866 | base = XEXP (op0, 1); | |
1867 | disp = op1; | |
d3632d41 | 1868 | } |
d3632d41 | 1869 | |
ab96de7e | 1870 | else |
d3632d41 | 1871 | { |
3ed99cc9 | 1872 | return false; |
d3632d41 | 1873 | } |
ab96de7e | 1874 | } |
d3632d41 | 1875 | |
ab96de7e AS |
1876 | else |
1877 | disp = addr; /* displacement */ | |
d3632d41 | 1878 | |
ab96de7e AS |
1879 | /* Extract integer part of displacement. */ |
1880 | orig_disp = disp; | |
1881 | if (disp) | |
1882 | { | |
1883 | if (GET_CODE (disp) == CONST_INT) | |
d3632d41 | 1884 | { |
ab96de7e AS |
1885 | offset = INTVAL (disp); |
1886 | disp = NULL_RTX; | |
d3632d41 | 1887 | } |
ab96de7e AS |
1888 | else if (GET_CODE (disp) == CONST |
1889 | && GET_CODE (XEXP (disp, 0)) == PLUS | |
1890 | && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT) | |
1891 | { | |
1892 | offset = INTVAL (XEXP (XEXP (disp, 0), 1)); | |
1893 | disp = XEXP (XEXP (disp, 0), 0); | |
1894 | } | |
1895 | } | |
d3632d41 | 1896 | |
ab96de7e AS |
1897 | /* Strip off CONST here to avoid special case tests later. */ |
1898 | if (disp && GET_CODE (disp) == CONST) | |
1899 | disp = XEXP (disp, 0); | |
ac32b25e | 1900 | |
ab96de7e AS |
1901 | /* We can convert literal pool addresses to |
1902 | displacements by basing them off the base register. */ | |
1903 | if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp)) | |
1904 | { | |
1905 | /* Either base or index must be free to hold the base register. */ | |
1906 | if (!base) | |
f01cf809 | 1907 | base = fake_pool_base, literal_pool = true; |
ab96de7e | 1908 | else if (!indx) |
f01cf809 | 1909 | indx = fake_pool_base, literal_pool = true; |
ab96de7e | 1910 | else |
3ed99cc9 | 1911 | return false; |
ab96de7e AS |
1912 | |
1913 | /* Mark up the displacement. */ | |
1914 | disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp), | |
1915 | UNSPEC_LTREL_OFFSET); | |
d3632d41 | 1916 | } |
ccfc6cc8 | 1917 | |
ab96de7e AS |
1918 | /* Validate base register. */ |
1919 | if (base) | |
1920 | { | |
1921 | if (GET_CODE (base) == UNSPEC) | |
1922 | switch (XINT (base, 1)) | |
1923 | { | |
1924 | case UNSPEC_LTREF: | |
1925 | if (!disp) | |
f4aa3848 | 1926 | disp = gen_rtx_UNSPEC (Pmode, |
ab96de7e AS |
1927 | gen_rtvec (1, XVECEXP (base, 0, 0)), |
1928 | UNSPEC_LTREL_OFFSET); | |
1929 | else | |
3ed99cc9 | 1930 | return false; |
ccfc6cc8 | 1931 | |
f01cf809 | 1932 | base = XVECEXP (base, 0, 1); |
ab96de7e | 1933 | break; |
f19a9af7 | 1934 | |
ab96de7e | 1935 | case UNSPEC_LTREL_BASE: |
f01cf809 UW |
1936 | if (XVECLEN (base, 0) == 1) |
1937 | base = fake_pool_base, literal_pool = true; | |
1938 | else | |
1939 | base = XVECEXP (base, 0, 1); | |
ab96de7e | 1940 | break; |
f19a9af7 | 1941 | |
ab96de7e | 1942 | default: |
3ed99cc9 | 1943 | return false; |
ab96de7e | 1944 | } |
f19a9af7 | 1945 | |
f4aa3848 AK |
1946 | if (!REG_P (base) |
1947 | || (GET_MODE (base) != SImode | |
93fa8428 | 1948 | && GET_MODE (base) != Pmode)) |
3ed99cc9 | 1949 | return false; |
ab96de7e | 1950 | |
f01cf809 | 1951 | if (REGNO (base) == STACK_POINTER_REGNUM |
ab96de7e AS |
1952 | || REGNO (base) == FRAME_POINTER_REGNUM |
1953 | || ((reload_completed || reload_in_progress) | |
1954 | && frame_pointer_needed | |
1955 | && REGNO (base) == HARD_FRAME_POINTER_REGNUM) | |
1956 | || REGNO (base) == ARG_POINTER_REGNUM | |
1957 | || (flag_pic | |
1958 | && REGNO (base) == PIC_OFFSET_TABLE_REGNUM)) | |
3ed99cc9 | 1959 | pointer = base_ptr = true; |
f01cf809 UW |
1960 | |
1961 | if ((reload_completed || reload_in_progress) | |
1962 | && base == cfun->machine->base_reg) | |
1963 | pointer = base_ptr = literal_pool = true; | |
ab96de7e AS |
1964 | } |
1965 | ||
1966 | /* Validate index register. */ | |
1967 | if (indx) | |
f19a9af7 | 1968 | { |
ab96de7e AS |
1969 | if (GET_CODE (indx) == UNSPEC) |
1970 | switch (XINT (indx, 1)) | |
1971 | { | |
1972 | case UNSPEC_LTREF: | |
1973 | if (!disp) | |
f4aa3848 | 1974 | disp = gen_rtx_UNSPEC (Pmode, |
ab96de7e AS |
1975 | gen_rtvec (1, XVECEXP (indx, 0, 0)), |
1976 | UNSPEC_LTREL_OFFSET); | |
1977 | else | |
3ed99cc9 | 1978 | return false; |
f19a9af7 | 1979 | |
f01cf809 | 1980 | indx = XVECEXP (indx, 0, 1); |
ab96de7e | 1981 | break; |
f19a9af7 | 1982 | |
ab96de7e | 1983 | case UNSPEC_LTREL_BASE: |
f01cf809 UW |
1984 | if (XVECLEN (indx, 0) == 1) |
1985 | indx = fake_pool_base, literal_pool = true; | |
1986 | else | |
1987 | indx = XVECEXP (indx, 0, 1); | |
ab96de7e | 1988 | break; |
f19a9af7 | 1989 | |
ab96de7e | 1990 | default: |
3ed99cc9 | 1991 | return false; |
ab96de7e | 1992 | } |
f19a9af7 | 1993 | |
f4aa3848 | 1994 | if (!REG_P (indx) |
93fa8428 AK |
1995 | || (GET_MODE (indx) != SImode |
1996 | && GET_MODE (indx) != Pmode)) | |
3ed99cc9 | 1997 | return false; |
f19a9af7 | 1998 | |
f01cf809 | 1999 | if (REGNO (indx) == STACK_POINTER_REGNUM |
ab96de7e AS |
2000 | || REGNO (indx) == FRAME_POINTER_REGNUM |
2001 | || ((reload_completed || reload_in_progress) | |
2002 | && frame_pointer_needed | |
2003 | && REGNO (indx) == HARD_FRAME_POINTER_REGNUM) | |
2004 | || REGNO (indx) == ARG_POINTER_REGNUM | |
2005 | || (flag_pic | |
2006 | && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM)) | |
3ed99cc9 | 2007 | pointer = indx_ptr = true; |
f01cf809 UW |
2008 | |
2009 | if ((reload_completed || reload_in_progress) | |
2010 | && indx == cfun->machine->base_reg) | |
2011 | pointer = indx_ptr = literal_pool = true; | |
ab96de7e | 2012 | } |
38899e29 | 2013 | |
ab96de7e AS |
2014 | /* Prefer to use pointer as base, not index. */ |
2015 | if (base && indx && !base_ptr | |
2016 | && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx)))) | |
2017 | { | |
2018 | rtx tmp = base; | |
2019 | base = indx; | |
2020 | indx = tmp; | |
2021 | } | |
f19a9af7 | 2022 | |
ab96de7e AS |
2023 | /* Validate displacement. */ |
2024 | if (!disp) | |
2025 | { | |
f4aa3848 AK |
2026 | /* If virtual registers are involved, the displacement will change later |
2027 | anyway as the virtual registers get eliminated. This could make a | |
2028 | valid displacement invalid, but it is more likely to make an invalid | |
2029 | displacement valid, because we sometimes access the register save area | |
63296cb1 | 2030 | via negative offsets to one of those registers. |
ab96de7e AS |
2031 | Thus we don't check the displacement for validity here. If after |
2032 | elimination the displacement turns out to be invalid after all, | |
2033 | this is fixed up by reload in any case. */ | |
f4aa3848 AK |
2034 | if (base != arg_pointer_rtx |
2035 | && indx != arg_pointer_rtx | |
2036 | && base != return_address_pointer_rtx | |
63296cb1 | 2037 | && indx != return_address_pointer_rtx |
f4aa3848 | 2038 | && base != frame_pointer_rtx |
63296cb1 | 2039 | && indx != frame_pointer_rtx |
f4aa3848 | 2040 | && base != virtual_stack_vars_rtx |
63296cb1 | 2041 | && indx != virtual_stack_vars_rtx) |
ab96de7e | 2042 | if (!DISP_IN_RANGE (offset)) |
3ed99cc9 | 2043 | return false; |
ab96de7e AS |
2044 | } |
2045 | else | |
2046 | { | |
2047 | /* All the special cases are pointers. */ | |
3ed99cc9 | 2048 | pointer = true; |
f19a9af7 | 2049 | |
ab96de7e AS |
2050 | /* In the small-PIC case, the linker converts @GOT |
2051 | and @GOTNTPOFF offsets to possible displacements. */ | |
2052 | if (GET_CODE (disp) == UNSPEC | |
2053 | && (XINT (disp, 1) == UNSPEC_GOT | |
2054 | || XINT (disp, 1) == UNSPEC_GOTNTPOFF) | |
ab96de7e AS |
2055 | && flag_pic == 1) |
2056 | { | |
2057 | ; | |
2058 | } | |
f19a9af7 | 2059 | |
dc66391d RS |
2060 | /* Accept pool label offsets. */ |
2061 | else if (GET_CODE (disp) == UNSPEC | |
2062 | && XINT (disp, 1) == UNSPEC_POOL_OFFSET) | |
2063 | ; | |
f19a9af7 | 2064 | |
ab96de7e AS |
2065 | /* Accept literal pool references. */ |
2066 | else if (GET_CODE (disp) == UNSPEC | |
2067 | && XINT (disp, 1) == UNSPEC_LTREL_OFFSET) | |
2068 | { | |
2069 | orig_disp = gen_rtx_CONST (Pmode, disp); | |
2070 | if (offset) | |
2071 | { | |
2072 | /* If we have an offset, make sure it does not | |
2073 | exceed the size of the constant pool entry. */ | |
2074 | rtx sym = XVECEXP (disp, 0, 0); | |
2075 | if (offset >= GET_MODE_SIZE (get_pool_mode (sym))) | |
3ed99cc9 | 2076 | return false; |
f19a9af7 | 2077 | |
ab96de7e AS |
2078 | orig_disp = plus_constant (orig_disp, offset); |
2079 | } | |
2080 | } | |
2081 | ||
2082 | else | |
3ed99cc9 | 2083 | return false; |
f19a9af7 AK |
2084 | } |
2085 | ||
ab96de7e | 2086 | if (!base && !indx) |
3ed99cc9 | 2087 | pointer = true; |
ab96de7e AS |
2088 | |
2089 | if (out) | |
2090 | { | |
2091 | out->base = base; | |
2092 | out->indx = indx; | |
2093 | out->disp = orig_disp; | |
2094 | out->pointer = pointer; | |
f01cf809 | 2095 | out->literal_pool = literal_pool; |
ab96de7e AS |
2096 | } |
2097 | ||
3ed99cc9 | 2098 | return true; |
f19a9af7 AK |
2099 | } |
2100 | ||
d98ad410 UW |
2101 | /* Decompose a RTL expression OP for a shift count into its components, |
2102 | and return the base register in BASE and the offset in OFFSET. | |
2103 | ||
d98ad410 UW |
2104 | Return true if OP is a valid shift count, false if not. */ |
2105 | ||
2106 | bool | |
4989e88a | 2107 | s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset) |
d98ad410 UW |
2108 | { |
2109 | HOST_WIDE_INT off = 0; | |
2110 | ||
d98ad410 UW |
2111 | /* We can have an integer constant, an address register, |
2112 | or a sum of the two. */ | |
2113 | if (GET_CODE (op) == CONST_INT) | |
2114 | { | |
2115 | off = INTVAL (op); | |
2116 | op = NULL_RTX; | |
2117 | } | |
2118 | if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT) | |
2119 | { | |
2120 | off = INTVAL (XEXP (op, 1)); | |
2121 | op = XEXP (op, 0); | |
2122 | } | |
2123 | while (op && GET_CODE (op) == SUBREG) | |
2124 | op = SUBREG_REG (op); | |
2125 | ||
2126 | if (op && GET_CODE (op) != REG) | |
2127 | return false; | |
2128 | ||
2129 | if (offset) | |
2130 | *offset = off; | |
2131 | if (base) | |
2132 | *base = op; | |
2133 | ||
2134 | return true; | |
2135 | } | |
2136 | ||
2137 | ||
ab96de7e | 2138 | /* Return true if CODE is a valid address without index. */ |
3c50106f | 2139 | |
ab96de7e AS |
2140 | bool |
2141 | s390_legitimate_address_without_index_p (rtx op) | |
2142 | { | |
2143 | struct s390_address addr; | |
2144 | ||
2145 | if (!s390_decompose_address (XEXP (op, 0), &addr)) | |
2146 | return false; | |
2147 | if (addr.indx) | |
2148 | return false; | |
2149 | ||
2150 | return true; | |
2151 | } | |
2152 | ||
cd8dc1f9 | 2153 | |
4fe6dea8 AK |
2154 | /* Return true if ADDR is of kind symbol_ref or symbol_ref + const_int |
2155 | and return these parts in SYMREF and ADDEND. You can pass NULL in | |
98635b04 UW |
2156 | SYMREF and/or ADDEND if you are not interested in these values. |
2157 | Literal pool references are *not* considered symbol references. */ | |
ab96de7e | 2158 | |
4fe6dea8 AK |
2159 | static bool |
2160 | s390_symref_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend) | |
ab96de7e | 2161 | { |
4fe6dea8 | 2162 | HOST_WIDE_INT tmpaddend = 0; |
ab96de7e | 2163 | |
4fe6dea8 AK |
2164 | if (GET_CODE (addr) == CONST) |
2165 | addr = XEXP (addr, 0); | |
2166 | ||
2167 | if (GET_CODE (addr) == PLUS) | |
ab96de7e | 2168 | { |
4fe6dea8 | 2169 | if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF |
98635b04 | 2170 | && !CONSTANT_POOL_ADDRESS_P (XEXP (addr, 0)) |
4fe6dea8 AK |
2171 | && CONST_INT_P (XEXP (addr, 1))) |
2172 | { | |
2173 | tmpaddend = INTVAL (XEXP (addr, 1)); | |
2174 | addr = XEXP (addr, 0); | |
2175 | } | |
2176 | else | |
2177 | return false; | |
2178 | } | |
2179 | else | |
98635b04 | 2180 | if (GET_CODE (addr) != SYMBOL_REF || CONSTANT_POOL_ADDRESS_P (addr)) |
4fe6dea8 | 2181 | return false; |
ab96de7e | 2182 | |
4fe6dea8 AK |
2183 | if (symref) |
2184 | *symref = addr; | |
2185 | if (addend) | |
2186 | *addend = tmpaddend; | |
ab96de7e | 2187 | |
4fe6dea8 AK |
2188 | return true; |
2189 | } | |
2190 | ||
2191 | ||
2192 | /* Return true if the address in OP is valid for constraint letter C | |
2193 | if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal | |
2194 | pool MEMs should be accepted. Only the Q, R, S, T constraint | |
2195 | letters are allowed for C. */ | |
ab96de7e | 2196 | |
4fe6dea8 AK |
2197 | static int |
2198 | s390_check_qrst_address (char c, rtx op, bool lit_pool_ok) | |
2199 | { | |
2200 | struct s390_address addr; | |
2201 | bool decomposed = false; | |
2202 | ||
2203 | /* This check makes sure that no symbolic address (except literal | |
2204 | pool references) are accepted by the R or T constraints. */ | |
2205 | if (s390_symref_operand_p (op, NULL, NULL)) | |
98635b04 UW |
2206 | return 0; |
2207 | ||
2208 | /* Ensure literal pool references are only accepted if LIT_POOL_OK. */ | |
2209 | if (!lit_pool_ok) | |
ab96de7e | 2210 | { |
4fe6dea8 | 2211 | if (!s390_decompose_address (op, &addr)) |
ab96de7e | 2212 | return 0; |
98635b04 | 2213 | if (addr.literal_pool) |
ab96de7e | 2214 | return 0; |
4fe6dea8 | 2215 | decomposed = true; |
ab96de7e AS |
2216 | } |
2217 | ||
2218 | switch (c) | |
2219 | { | |
4fe6dea8 AK |
2220 | case 'Q': /* no index short displacement */ |
2221 | if (!decomposed && !s390_decompose_address (op, &addr)) | |
ab96de7e AS |
2222 | return 0; |
2223 | if (addr.indx) | |
2224 | return 0; | |
4fe6dea8 | 2225 | if (!s390_short_displacement (addr.disp)) |
ab96de7e | 2226 | return 0; |
4fe6dea8 | 2227 | break; |
ab96de7e | 2228 | |
4fe6dea8 | 2229 | case 'R': /* with index short displacement */ |
ab96de7e AS |
2230 | if (TARGET_LONG_DISPLACEMENT) |
2231 | { | |
4fe6dea8 | 2232 | if (!decomposed && !s390_decompose_address (op, &addr)) |
ab96de7e AS |
2233 | return 0; |
2234 | if (!s390_short_displacement (addr.disp)) | |
2235 | return 0; | |
2236 | } | |
4fe6dea8 AK |
2237 | /* Any invalid address here will be fixed up by reload, |
2238 | so accept it for the most generic constraint. */ | |
ab96de7e AS |
2239 | break; |
2240 | ||
4fe6dea8 | 2241 | case 'S': /* no index long displacement */ |
ab96de7e AS |
2242 | if (!TARGET_LONG_DISPLACEMENT) |
2243 | return 0; | |
4fe6dea8 | 2244 | if (!decomposed && !s390_decompose_address (op, &addr)) |
ab96de7e AS |
2245 | return 0; |
2246 | if (addr.indx) | |
2247 | return 0; | |
2248 | if (s390_short_displacement (addr.disp)) | |
2249 | return 0; | |
2250 | break; | |
2251 | ||
4fe6dea8 | 2252 | case 'T': /* with index long displacement */ |
ab96de7e AS |
2253 | if (!TARGET_LONG_DISPLACEMENT) |
2254 | return 0; | |
4fe6dea8 AK |
2255 | /* Any invalid address here will be fixed up by reload, |
2256 | so accept it for the most generic constraint. */ | |
2257 | if ((decomposed || s390_decompose_address (op, &addr)) | |
2258 | && s390_short_displacement (addr.disp)) | |
ab96de7e AS |
2259 | return 0; |
2260 | break; | |
4fe6dea8 AK |
2261 | default: |
2262 | return 0; | |
2263 | } | |
2264 | return 1; | |
2265 | } | |
ab96de7e | 2266 | |
ab96de7e | 2267 | |
4fe6dea8 AK |
2268 | /* Evaluates constraint strings described by the regular expression |
2269 | ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for | |
2270 | the constraint given in STR, or 0 else. */ | |
2271 | ||
2272 | int | |
2273 | s390_mem_constraint (const char *str, rtx op) | |
2274 | { | |
2275 | char c = str[0]; | |
2276 | ||
2277 | switch (c) | |
2278 | { | |
2279 | case 'A': | |
2280 | /* Check for offsettable variants of memory constraints. */ | |
2281 | if (!MEM_P (op) || MEM_VOLATILE_P (op)) | |
ab96de7e | 2282 | return 0; |
4fe6dea8 AK |
2283 | if ((reload_completed || reload_in_progress) |
2284 | ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op)) | |
963fc8d0 | 2285 | return 0; |
4fe6dea8 AK |
2286 | return s390_check_qrst_address (str[1], XEXP (op, 0), true); |
2287 | case 'B': | |
2288 | /* Check for non-literal-pool variants of memory constraints. */ | |
2289 | if (!MEM_P (op)) | |
ab96de7e | 2290 | return 0; |
4fe6dea8 AK |
2291 | return s390_check_qrst_address (str[1], XEXP (op, 0), false); |
2292 | case 'Q': | |
2293 | case 'R': | |
2294 | case 'S': | |
2295 | case 'T': | |
2296 | if (GET_CODE (op) != MEM) | |
2297 | return 0; | |
2298 | return s390_check_qrst_address (c, XEXP (op, 0), true); | |
2299 | case 'U': | |
2300 | return (s390_check_qrst_address ('Q', op, true) | |
2301 | || s390_check_qrst_address ('R', op, true)); | |
2302 | case 'W': | |
2303 | return (s390_check_qrst_address ('S', op, true) | |
2304 | || s390_check_qrst_address ('T', op, true)); | |
ab96de7e | 2305 | case 'Y': |
d98ad410 UW |
2306 | /* Simply check for the basic form of a shift count. Reload will |
2307 | take care of making sure we have a proper base register. */ | |
4989e88a | 2308 | if (!s390_decompose_shift_count (op, NULL, NULL)) |
d98ad410 UW |
2309 | return 0; |
2310 | break; | |
4fe6dea8 AK |
2311 | case 'Z': |
2312 | return s390_check_qrst_address (str[1], op, true); | |
ab96de7e AS |
2313 | default: |
2314 | return 0; | |
2315 | } | |
ab96de7e AS |
2316 | return 1; |
2317 | } | |
2318 | ||
cd8dc1f9 | 2319 | |
cd8dc1f9 WG |
2320 | /* Evaluates constraint strings starting with letter O. Input |
2321 | parameter C is the second letter following the "O" in the constraint | |
2322 | string. Returns 1 if VALUE meets the respective constraint and 0 | |
2323 | otherwise. */ | |
ab96de7e | 2324 | |
d096725d | 2325 | int |
cd8dc1f9 | 2326 | s390_O_constraint_str (const char c, HOST_WIDE_INT value) |
d096725d | 2327 | { |
cd8dc1f9 WG |
2328 | if (!TARGET_EXTIMM) |
2329 | return 0; | |
d096725d | 2330 | |
cd8dc1f9 | 2331 | switch (c) |
d096725d | 2332 | { |
cd8dc1f9 WG |
2333 | case 's': |
2334 | return trunc_int_for_mode (value, SImode) == value; | |
2335 | ||
2336 | case 'p': | |
2337 | return value == 0 | |
2338 | || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1; | |
2339 | ||
2340 | case 'n': | |
ee3f3449 | 2341 | return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1; |
cd8dc1f9 | 2342 | |
d096725d | 2343 | default: |
cd8dc1f9 | 2344 | gcc_unreachable (); |
d096725d AS |
2345 | } |
2346 | } | |
2347 | ||
cd8dc1f9 WG |
2348 | |
2349 | /* Evaluates constraint strings starting with letter N. Parameter STR | |
2350 | contains the letters following letter "N" in the constraint string. | |
2351 | Returns true if VALUE matches the constraint. */ | |
d096725d | 2352 | |
ab96de7e | 2353 | int |
cd8dc1f9 | 2354 | s390_N_constraint_str (const char *str, HOST_WIDE_INT value) |
ab96de7e AS |
2355 | { |
2356 | enum machine_mode mode, part_mode; | |
2357 | int def; | |
2358 | int part, part_goal; | |
2359 | ||
ab96de7e | 2360 | |
cd8dc1f9 WG |
2361 | if (str[0] == 'x') |
2362 | part_goal = -1; | |
2363 | else | |
2364 | part_goal = str[0] - '0'; | |
ab96de7e | 2365 | |
cd8dc1f9 WG |
2366 | switch (str[1]) |
2367 | { | |
2368 | case 'Q': | |
2369 | part_mode = QImode; | |
ab96de7e | 2370 | break; |
cd8dc1f9 WG |
2371 | case 'H': |
2372 | part_mode = HImode; | |
ec24698e | 2373 | break; |
cd8dc1f9 WG |
2374 | case 'S': |
2375 | part_mode = SImode; | |
2376 | break; | |
2377 | default: | |
2378 | return 0; | |
2379 | } | |
ec24698e | 2380 | |
cd8dc1f9 WG |
2381 | switch (str[2]) |
2382 | { | |
2383 | case 'H': | |
2384 | mode = HImode; | |
2385 | break; | |
2386 | case 'S': | |
2387 | mode = SImode; | |
2388 | break; | |
2389 | case 'D': | |
2390 | mode = DImode; | |
2391 | break; | |
2392 | default: | |
2393 | return 0; | |
2394 | } | |
11598938 | 2395 | |
cd8dc1f9 WG |
2396 | switch (str[3]) |
2397 | { | |
2398 | case '0': | |
2399 | def = 0; | |
2400 | break; | |
2401 | case 'F': | |
2402 | def = -1; | |
2403 | break; | |
ab96de7e AS |
2404 | default: |
2405 | return 0; | |
2406 | } | |
2407 | ||
cd8dc1f9 WG |
2408 | if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode)) |
2409 | return 0; | |
2410 | ||
2411 | part = s390_single_part (GEN_INT (value), mode, part_mode, def); | |
2412 | if (part < 0) | |
2413 | return 0; | |
2414 | if (part_goal != -1 && part_goal != part) | |
2415 | return 0; | |
2416 | ||
ab96de7e AS |
2417 | return 1; |
2418 | } | |
2419 | ||
cd8dc1f9 WG |
2420 | |
2421 | /* Returns true if the input parameter VALUE is a float zero. */ | |
2422 | ||
2423 | int | |
2424 | s390_float_const_zero_p (rtx value) | |
2425 | { | |
2426 | return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT | |
2427 | && value == CONST0_RTX (GET_MODE (value))); | |
2428 | } | |
2429 | ||
2430 | ||
ab96de7e AS |
2431 | /* Compute a (partial) cost for rtx X. Return true if the complete |
2432 | cost has been computed, and false if subexpressions should be | |
f4aa3848 AK |
2433 | scanned. In either case, *TOTAL contains the cost result. |
2434 | CODE contains GET_CODE (x), OUTER_CODE contains the code | |
ab96de7e AS |
2435 | of the superexpression of x. */ |
2436 | ||
2437 | static bool | |
f40751dd JH |
2438 | s390_rtx_costs (rtx x, int code, int outer_code, int *total, |
2439 | bool speed ATTRIBUTE_UNUSED) | |
3c50106f RH |
2440 | { |
2441 | switch (code) | |
2442 | { | |
2443 | case CONST: | |
3c50106f | 2444 | case CONST_INT: |
3c50106f RH |
2445 | case LABEL_REF: |
2446 | case SYMBOL_REF: | |
2447 | case CONST_DOUBLE: | |
6fa5b390 | 2448 | case MEM: |
3c50106f RH |
2449 | *total = 0; |
2450 | return true; | |
2451 | ||
2452 | case ASHIFT: | |
2453 | case ASHIFTRT: | |
2454 | case LSHIFTRT: | |
017e0eb9 MD |
2455 | case ROTATE: |
2456 | case ROTATERT: | |
3c50106f RH |
2457 | case AND: |
2458 | case IOR: | |
2459 | case XOR: | |
3c50106f RH |
2460 | case NEG: |
2461 | case NOT: | |
2462 | *total = COSTS_N_INSNS (1); | |
017e0eb9 | 2463 | return false; |
3c50106f | 2464 | |
2742a1ed MD |
2465 | case PLUS: |
2466 | case MINUS: | |
2467 | /* Check for multiply and add. */ | |
b75d6bab | 2468 | if ((GET_MODE (x) == DFmode || GET_MODE (x) == SFmode) |
2742a1ed | 2469 | && GET_CODE (XEXP (x, 0)) == MULT |
142cd70f | 2470 | && TARGET_HARD_FLOAT && TARGET_FUSED_MADD) |
2742a1ed MD |
2471 | { |
2472 | /* This is the multiply and add case. */ | |
b75d6bab MD |
2473 | if (GET_MODE (x) == DFmode) |
2474 | *total = s390_cost->madbr; | |
2475 | else | |
2476 | *total = s390_cost->maebr; | |
bbbbb16a ILT |
2477 | *total += (rtx_cost (XEXP (XEXP (x, 0), 0), MULT, speed) |
2478 | + rtx_cost (XEXP (XEXP (x, 0), 1), MULT, speed) | |
2479 | + rtx_cost (XEXP (x, 1), (enum rtx_code) code, speed)); | |
2742a1ed MD |
2480 | return true; /* Do not do an additional recursive descent. */ |
2481 | } | |
2482 | *total = COSTS_N_INSNS (1); | |
2483 | return false; | |
2484 | ||
f4aa3848 | 2485 | case MULT: |
017e0eb9 MD |
2486 | switch (GET_MODE (x)) |
2487 | { | |
2488 | case SImode: | |
2742a1ed | 2489 | { |
017e0eb9 MD |
2490 | rtx left = XEXP (x, 0); |
2491 | rtx right = XEXP (x, 1); | |
2492 | if (GET_CODE (right) == CONST_INT | |
b5c67a49 | 2493 | && CONST_OK_FOR_K (INTVAL (right))) |
017e0eb9 MD |
2494 | *total = s390_cost->mhi; |
2495 | else if (GET_CODE (left) == SIGN_EXTEND) | |
2496 | *total = s390_cost->mh; | |
2497 | else | |
2498 | *total = s390_cost->ms; /* msr, ms, msy */ | |
2499 | break; | |
2500 | } | |
2501 | case DImode: | |
2502 | { | |
2503 | rtx left = XEXP (x, 0); | |
2504 | rtx right = XEXP (x, 1); | |
9602b6a1 | 2505 | if (TARGET_ZARCH) |
017e0eb9 MD |
2506 | { |
2507 | if (GET_CODE (right) == CONST_INT | |
b5c67a49 | 2508 | && CONST_OK_FOR_K (INTVAL (right))) |
017e0eb9 MD |
2509 | *total = s390_cost->mghi; |
2510 | else if (GET_CODE (left) == SIGN_EXTEND) | |
2511 | *total = s390_cost->msgf; | |
2512 | else | |
2513 | *total = s390_cost->msg; /* msgr, msg */ | |
2514 | } | |
2515 | else /* TARGET_31BIT */ | |
2516 | { | |
2517 | if (GET_CODE (left) == SIGN_EXTEND | |
2518 | && GET_CODE (right) == SIGN_EXTEND) | |
2519 | /* mulsidi case: mr, m */ | |
2520 | *total = s390_cost->m; | |
2742a1ed MD |
2521 | else if (GET_CODE (left) == ZERO_EXTEND |
2522 | && GET_CODE (right) == ZERO_EXTEND | |
2523 | && TARGET_CPU_ZARCH) | |
2524 | /* umulsidi case: ml, mlr */ | |
2525 | *total = s390_cost->ml; | |
017e0eb9 MD |
2526 | else |
2527 | /* Complex calculation is required. */ | |
2528 | *total = COSTS_N_INSNS (40); | |
2529 | } | |
2530 | break; | |
2531 | } | |
2532 | case SFmode: | |
2533 | case DFmode: | |
2534 | *total = s390_cost->mult_df; | |
2535 | break; | |
f61a2c7d AK |
2536 | case TFmode: |
2537 | *total = s390_cost->mxbr; | |
2538 | break; | |
017e0eb9 MD |
2539 | default: |
2540 | return false; | |
2541 | } | |
2542 | return false; | |
3c50106f | 2543 | |
6fa5b390 MD |
2544 | case UDIV: |
2545 | case UMOD: | |
2546 | if (GET_MODE (x) == TImode) /* 128 bit division */ | |
2547 | *total = s390_cost->dlgr; | |
2548 | else if (GET_MODE (x) == DImode) | |
2549 | { | |
2550 | rtx right = XEXP (x, 1); | |
2551 | if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */ | |
2552 | *total = s390_cost->dlr; | |
2553 | else /* 64 by 64 bit division */ | |
2554 | *total = s390_cost->dlgr; | |
2555 | } | |
2556 | else if (GET_MODE (x) == SImode) /* 32 bit division */ | |
2557 | *total = s390_cost->dlr; | |
2558 | return false; | |
2559 | ||
3c50106f | 2560 | case DIV: |
6fa5b390 MD |
2561 | case MOD: |
2562 | if (GET_MODE (x) == DImode) | |
2563 | { | |
2564 | rtx right = XEXP (x, 1); | |
2565 | if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */ | |
9602b6a1 | 2566 | if (TARGET_ZARCH) |
6fa5b390 MD |
2567 | *total = s390_cost->dsgfr; |
2568 | else | |
2569 | *total = s390_cost->dr; | |
2570 | else /* 64 by 64 bit division */ | |
2571 | *total = s390_cost->dsgr; | |
2572 | } | |
2573 | else if (GET_MODE (x) == SImode) /* 32 bit division */ | |
2574 | *total = s390_cost->dlr; | |
2575 | else if (GET_MODE (x) == SFmode) | |
98fd0d70 | 2576 | { |
142cd70f | 2577 | *total = s390_cost->debr; |
98fd0d70 MD |
2578 | } |
2579 | else if (GET_MODE (x) == DFmode) | |
2580 | { | |
142cd70f | 2581 | *total = s390_cost->ddbr; |
98fd0d70 | 2582 | } |
f61a2c7d AK |
2583 | else if (GET_MODE (x) == TFmode) |
2584 | { | |
142cd70f | 2585 | *total = s390_cost->dxbr; |
f61a2c7d | 2586 | } |
017e0eb9 MD |
2587 | return false; |
2588 | ||
2742a1ed MD |
2589 | case SQRT: |
2590 | if (GET_MODE (x) == SFmode) | |
2591 | *total = s390_cost->sqebr; | |
f61a2c7d | 2592 | else if (GET_MODE (x) == DFmode) |
2742a1ed | 2593 | *total = s390_cost->sqdbr; |
f61a2c7d AK |
2594 | else /* TFmode */ |
2595 | *total = s390_cost->sqxbr; | |
2742a1ed MD |
2596 | return false; |
2597 | ||
017e0eb9 | 2598 | case SIGN_EXTEND: |
2742a1ed | 2599 | case ZERO_EXTEND: |
6fa5b390 MD |
2600 | if (outer_code == MULT || outer_code == DIV || outer_code == MOD |
2601 | || outer_code == PLUS || outer_code == MINUS | |
2602 | || outer_code == COMPARE) | |
017e0eb9 MD |
2603 | *total = 0; |
2604 | return false; | |
3c50106f | 2605 | |
6fa5b390 MD |
2606 | case COMPARE: |
2607 | *total = COSTS_N_INSNS (1); | |
2608 | if (GET_CODE (XEXP (x, 0)) == AND | |
2609 | && GET_CODE (XEXP (x, 1)) == CONST_INT | |
2610 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT) | |
2611 | { | |
2612 | rtx op0 = XEXP (XEXP (x, 0), 0); | |
2613 | rtx op1 = XEXP (XEXP (x, 0), 1); | |
2614 | rtx op2 = XEXP (x, 1); | |
2615 | ||
2616 | if (memory_operand (op0, GET_MODE (op0)) | |
2617 | && s390_tm_ccmode (op1, op2, 0) != VOIDmode) | |
2618 | return true; | |
2619 | if (register_operand (op0, GET_MODE (op0)) | |
2620 | && s390_tm_ccmode (op1, op2, 1) != VOIDmode) | |
2621 | return true; | |
2622 | } | |
2623 | return false; | |
2624 | ||
3c50106f RH |
2625 | default: |
2626 | return false; | |
2627 | } | |
2628 | } | |
2629 | ||
dea09b1b UW |
2630 | /* Return the cost of an address rtx ADDR. */ |
2631 | ||
dcefdf67 | 2632 | static int |
f40751dd | 2633 | s390_address_cost (rtx addr, bool speed ATTRIBUTE_UNUSED) |
dea09b1b UW |
2634 | { |
2635 | struct s390_address ad; | |
2636 | if (!s390_decompose_address (addr, &ad)) | |
2637 | return 1000; | |
2638 | ||
2639 | return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1); | |
2640 | } | |
2641 | ||
fd3cd001 UW |
2642 | /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode, |
2643 | otherwise return 0. */ | |
2644 | ||
2645 | int | |
5d81b82b | 2646 | tls_symbolic_operand (rtx op) |
fd3cd001 | 2647 | { |
fd3cd001 UW |
2648 | if (GET_CODE (op) != SYMBOL_REF) |
2649 | return 0; | |
114278e7 | 2650 | return SYMBOL_REF_TLS_MODEL (op); |
fd3cd001 | 2651 | } |
9db1d521 | 2652 | \f |
c5aa1d12 UW |
2653 | /* Split DImode access register reference REG (on 64-bit) into its constituent |
2654 | low and high parts, and store them into LO and HI. Note that gen_lowpart/ | |
2655 | gen_highpart cannot be used as they assume all registers are word-sized, | |
2656 | while our access registers have only half that size. */ | |
2657 | ||
2658 | void | |
2659 | s390_split_access_reg (rtx reg, rtx *lo, rtx *hi) | |
2660 | { | |
2661 | gcc_assert (TARGET_64BIT); | |
2662 | gcc_assert (ACCESS_REG_P (reg)); | |
2663 | gcc_assert (GET_MODE (reg) == DImode); | |
2664 | gcc_assert (!(REGNO (reg) & 1)); | |
2665 | ||
2666 | *lo = gen_rtx_REG (SImode, REGNO (reg) + 1); | |
2667 | *hi = gen_rtx_REG (SImode, REGNO (reg)); | |
2668 | } | |
9db1d521 | 2669 | |
994fe660 | 2670 | /* Return true if OP contains a symbol reference */ |
9db1d521 | 2671 | |
3ed99cc9 | 2672 | bool |
9c808aad | 2673 | symbolic_reference_mentioned_p (rtx op) |
9db1d521 | 2674 | { |
5d81b82b AS |
2675 | const char *fmt; |
2676 | int i; | |
9db1d521 HP |
2677 | |
2678 | if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF) | |
2679 | return 1; | |
2680 | ||
2681 | fmt = GET_RTX_FORMAT (GET_CODE (op)); | |
2682 | for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--) | |
2683 | { | |
2684 | if (fmt[i] == 'E') | |
2685 | { | |
5d81b82b | 2686 | int j; |
9db1d521 HP |
2687 | |
2688 | for (j = XVECLEN (op, i) - 1; j >= 0; j--) | |
2689 | if (symbolic_reference_mentioned_p (XVECEXP (op, i, j))) | |
2690 | return 1; | |
2691 | } | |
2692 | ||
2693 | else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i))) | |
2694 | return 1; | |
2695 | } | |
2696 | ||
2697 | return 0; | |
2698 | } | |
2699 | ||
fd3cd001 UW |
2700 | /* Return true if OP contains a reference to a thread-local symbol. */ |
2701 | ||
3ed99cc9 | 2702 | bool |
9c808aad | 2703 | tls_symbolic_reference_mentioned_p (rtx op) |
fd3cd001 | 2704 | { |
5d81b82b AS |
2705 | const char *fmt; |
2706 | int i; | |
fd3cd001 UW |
2707 | |
2708 | if (GET_CODE (op) == SYMBOL_REF) | |
2709 | return tls_symbolic_operand (op); | |
2710 | ||
2711 | fmt = GET_RTX_FORMAT (GET_CODE (op)); | |
2712 | for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--) | |
2713 | { | |
2714 | if (fmt[i] == 'E') | |
2715 | { | |
5d81b82b | 2716 | int j; |
fd3cd001 UW |
2717 | |
2718 | for (j = XVECLEN (op, i) - 1; j >= 0; j--) | |
2719 | if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j))) | |
3ed99cc9 | 2720 | return true; |
fd3cd001 UW |
2721 | } |
2722 | ||
2723 | else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i))) | |
3ed99cc9 | 2724 | return true; |
fd3cd001 UW |
2725 | } |
2726 | ||
3ed99cc9 | 2727 | return false; |
fd3cd001 UW |
2728 | } |
2729 | ||
9db1d521 | 2730 | |
c7453384 EC |
2731 | /* Return true if OP is a legitimate general operand when |
2732 | generating PIC code. It is given that flag_pic is on | |
994fe660 UW |
2733 | and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */ |
2734 | ||
9db1d521 | 2735 | int |
5d81b82b | 2736 | legitimate_pic_operand_p (rtx op) |
9db1d521 | 2737 | { |
4023fb28 | 2738 | /* Accept all non-symbolic constants. */ |
9db1d521 HP |
2739 | if (!SYMBOLIC_CONST (op)) |
2740 | return 1; | |
2741 | ||
c7453384 | 2742 | /* Reject everything else; must be handled |
fd3cd001 | 2743 | via emit_symbolic_move. */ |
9db1d521 HP |
2744 | return 0; |
2745 | } | |
2746 | ||
994fe660 UW |
2747 | /* Returns true if the constant value OP is a legitimate general operand. |
2748 | It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
2749 | ||
9db1d521 | 2750 | int |
5d81b82b | 2751 | legitimate_constant_p (rtx op) |
9db1d521 | 2752 | { |
4023fb28 | 2753 | /* Accept all non-symbolic constants. */ |
9db1d521 HP |
2754 | if (!SYMBOLIC_CONST (op)) |
2755 | return 1; | |
2756 | ||
fd3cd001 | 2757 | /* Accept immediate LARL operands. */ |
9e8327e3 | 2758 | if (TARGET_CPU_ZARCH && larl_operand (op, VOIDmode)) |
fd3cd001 UW |
2759 | return 1; |
2760 | ||
2761 | /* Thread-local symbols are never legal constants. This is | |
2762 | so that emit_call knows that computing such addresses | |
2763 | might require a function call. */ | |
2764 | if (TLS_SYMBOLIC_CONST (op)) | |
2765 | return 0; | |
2766 | ||
9db1d521 HP |
2767 | /* In the PIC case, symbolic constants must *not* be |
2768 | forced into the literal pool. We accept them here, | |
fd3cd001 | 2769 | so that they will be handled by emit_symbolic_move. */ |
9db1d521 HP |
2770 | if (flag_pic) |
2771 | return 1; | |
2772 | ||
9db1d521 HP |
2773 | /* All remaining non-PIC symbolic constants are |
2774 | forced into the literal pool. */ | |
2775 | return 0; | |
2776 | } | |
2777 | ||
fd3cd001 UW |
2778 | /* Determine if it's legal to put X into the constant pool. This |
2779 | is not possible if X contains the address of a symbol that is | |
2780 | not constant (TLS) or not known at final link time (PIC). */ | |
2781 | ||
2782 | static bool | |
9c808aad | 2783 | s390_cannot_force_const_mem (rtx x) |
fd3cd001 UW |
2784 | { |
2785 | switch (GET_CODE (x)) | |
2786 | { | |
2787 | case CONST_INT: | |
2788 | case CONST_DOUBLE: | |
2789 | /* Accept all non-symbolic constants. */ | |
2790 | return false; | |
2791 | ||
2792 | case LABEL_REF: | |
2793 | /* Labels are OK iff we are non-PIC. */ | |
2794 | return flag_pic != 0; | |
2795 | ||
2796 | case SYMBOL_REF: | |
2797 | /* 'Naked' TLS symbol references are never OK, | |
2798 | non-TLS symbols are OK iff we are non-PIC. */ | |
2799 | if (tls_symbolic_operand (x)) | |
2800 | return true; | |
2801 | else | |
2802 | return flag_pic != 0; | |
2803 | ||
2804 | case CONST: | |
2805 | return s390_cannot_force_const_mem (XEXP (x, 0)); | |
2806 | case PLUS: | |
2807 | case MINUS: | |
2808 | return s390_cannot_force_const_mem (XEXP (x, 0)) | |
2809 | || s390_cannot_force_const_mem (XEXP (x, 1)); | |
2810 | ||
2811 | case UNSPEC: | |
2812 | switch (XINT (x, 1)) | |
2813 | { | |
2814 | /* Only lt-relative or GOT-relative UNSPECs are OK. */ | |
fd7643fb UW |
2815 | case UNSPEC_LTREL_OFFSET: |
2816 | case UNSPEC_GOT: | |
2817 | case UNSPEC_GOTOFF: | |
2818 | case UNSPEC_PLTOFF: | |
fd3cd001 UW |
2819 | case UNSPEC_TLSGD: |
2820 | case UNSPEC_TLSLDM: | |
2821 | case UNSPEC_NTPOFF: | |
2822 | case UNSPEC_DTPOFF: | |
2823 | case UNSPEC_GOTNTPOFF: | |
2824 | case UNSPEC_INDNTPOFF: | |
2825 | return false; | |
2826 | ||
9bb86f41 UW |
2827 | /* If the literal pool shares the code section, be put |
2828 | execute template placeholders into the pool as well. */ | |
2829 | case UNSPEC_INSN: | |
2830 | return TARGET_CPU_ZARCH; | |
2831 | ||
fd3cd001 UW |
2832 | default: |
2833 | return true; | |
2834 | } | |
2835 | break; | |
2836 | ||
2837 | default: | |
8d933e31 | 2838 | gcc_unreachable (); |
fd3cd001 UW |
2839 | } |
2840 | } | |
2841 | ||
4023fb28 | 2842 | /* Returns true if the constant value OP is a legitimate general |
c7453384 | 2843 | operand during and after reload. The difference to |
4023fb28 UW |
2844 | legitimate_constant_p is that this function will not accept |
2845 | a constant that would need to be forced to the literal pool | |
65b1d8ea AK |
2846 | before it can be used as operand. |
2847 | This function accepts all constants which can be loaded directly | |
2848 | into a GPR. */ | |
4023fb28 | 2849 | |
3ed99cc9 | 2850 | bool |
5d81b82b | 2851 | legitimate_reload_constant_p (rtx op) |
4023fb28 | 2852 | { |
d3632d41 | 2853 | /* Accept la(y) operands. */ |
c7453384 | 2854 | if (GET_CODE (op) == CONST_INT |
d3632d41 | 2855 | && DISP_IN_RANGE (INTVAL (op))) |
3ed99cc9 | 2856 | return true; |
d3632d41 | 2857 | |
ec24698e | 2858 | /* Accept l(g)hi/l(g)fi operands. */ |
4023fb28 | 2859 | if (GET_CODE (op) == CONST_INT |
ec24698e | 2860 | && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op)))) |
3ed99cc9 | 2861 | return true; |
4023fb28 UW |
2862 | |
2863 | /* Accept lliXX operands. */ | |
9e8327e3 | 2864 | if (TARGET_ZARCH |
11598938 UW |
2865 | && GET_CODE (op) == CONST_INT |
2866 | && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op) | |
2867 | && s390_single_part (op, word_mode, HImode, 0) >= 0) | |
3ed99cc9 | 2868 | return true; |
4023fb28 | 2869 | |
ec24698e UW |
2870 | if (TARGET_EXTIMM |
2871 | && GET_CODE (op) == CONST_INT | |
2872 | && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op) | |
2873 | && s390_single_part (op, word_mode, SImode, 0) >= 0) | |
2874 | return true; | |
2875 | ||
4023fb28 | 2876 | /* Accept larl operands. */ |
9e8327e3 | 2877 | if (TARGET_CPU_ZARCH |
4023fb28 | 2878 | && larl_operand (op, VOIDmode)) |
3ed99cc9 | 2879 | return true; |
4023fb28 | 2880 | |
45e5214c UW |
2881 | /* Accept floating-point zero operands that fit into a single GPR. */ |
2882 | if (GET_CODE (op) == CONST_DOUBLE | |
2883 | && s390_float_const_zero_p (op) | |
2884 | && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD) | |
2885 | return true; | |
2886 | ||
11598938 UW |
2887 | /* Accept double-word operands that can be split. */ |
2888 | if (GET_CODE (op) == CONST_INT | |
2889 | && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op)) | |
2890 | { | |
2891 | enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode; | |
2892 | rtx hi = operand_subword (op, 0, 0, dword_mode); | |
2893 | rtx lo = operand_subword (op, 1, 0, dword_mode); | |
2894 | return legitimate_reload_constant_p (hi) | |
2895 | && legitimate_reload_constant_p (lo); | |
2896 | } | |
2897 | ||
4023fb28 | 2898 | /* Everything else cannot be handled without reload. */ |
3ed99cc9 | 2899 | return false; |
4023fb28 UW |
2900 | } |
2901 | ||
65b1d8ea AK |
2902 | /* Returns true if the constant value OP is a legitimate fp operand |
2903 | during and after reload. | |
2904 | This function accepts all constants which can be loaded directly | |
2905 | into an FPR. */ | |
2906 | ||
2907 | static bool | |
2908 | legitimate_reload_fp_constant_p (rtx op) | |
2909 | { | |
2910 | /* Accept floating-point zero operands if the load zero instruction | |
2911 | can be used. */ | |
2912 | if (TARGET_Z196 | |
2913 | && GET_CODE (op) == CONST_DOUBLE | |
2914 | && s390_float_const_zero_p (op)) | |
2915 | return true; | |
2916 | ||
2917 | return false; | |
2918 | } | |
2919 | ||
0a2aaacc | 2920 | /* Given an rtx OP being reloaded into a reg required to be in class RCLASS, |
4023fb28 UW |
2921 | return the class of reg to actually use. */ |
2922 | ||
2923 | enum reg_class | |
0a2aaacc | 2924 | s390_preferred_reload_class (rtx op, enum reg_class rclass) |
4023fb28 | 2925 | { |
4023fb28 UW |
2926 | switch (GET_CODE (op)) |
2927 | { | |
45e5214c UW |
2928 | /* Constants we cannot reload into general registers |
2929 | must be forced into the literal pool. */ | |
4023fb28 UW |
2930 | case CONST_DOUBLE: |
2931 | case CONST_INT: | |
45e5214c UW |
2932 | if (reg_class_subset_p (GENERAL_REGS, rclass) |
2933 | && legitimate_reload_constant_p (op)) | |
2934 | return GENERAL_REGS; | |
2935 | else if (reg_class_subset_p (ADDR_REGS, rclass) | |
2936 | && legitimate_reload_constant_p (op)) | |
2937 | return ADDR_REGS; | |
65b1d8ea AK |
2938 | else if (reg_class_subset_p (FP_REGS, rclass) |
2939 | && legitimate_reload_fp_constant_p (op)) | |
2940 | return FP_REGS; | |
2941 | return NO_REGS; | |
4023fb28 UW |
2942 | |
2943 | /* If a symbolic constant or a PLUS is reloaded, | |
14b3e8ef UW |
2944 | it is most likely being used as an address, so |
2945 | prefer ADDR_REGS. If 'class' is not a superset | |
2946 | of ADDR_REGS, e.g. FP_REGS, reject this reload. */ | |
4023fb28 UW |
2947 | case PLUS: |
2948 | case LABEL_REF: | |
2949 | case SYMBOL_REF: | |
2950 | case CONST: | |
0a2aaacc | 2951 | if (reg_class_subset_p (ADDR_REGS, rclass)) |
14b3e8ef UW |
2952 | return ADDR_REGS; |
2953 | else | |
2954 | return NO_REGS; | |
4023fb28 UW |
2955 | |
2956 | default: | |
2957 | break; | |
2958 | } | |
2959 | ||
0a2aaacc | 2960 | return rclass; |
4023fb28 | 2961 | } |
9db1d521 | 2962 | |
963fc8d0 AK |
2963 | /* Return true if ADDR is SYMBOL_REF + addend with addend being a |
2964 | multiple of ALIGNMENT and the SYMBOL_REF being naturally | |
2965 | aligned. */ | |
2966 | ||
2967 | bool | |
2968 | s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment) | |
2969 | { | |
2970 | HOST_WIDE_INT addend; | |
2971 | rtx symref; | |
2972 | ||
2973 | if (!s390_symref_operand_p (addr, &symref, &addend)) | |
2974 | return false; | |
2975 | ||
2976 | return (!SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref) | |
2977 | && !(addend & (alignment - 1))); | |
2978 | } | |
2979 | ||
2980 | /* ADDR is moved into REG using larl. If ADDR isn't a valid larl | |
2981 | operand SCRATCH is used to reload the even part of the address and | |
2982 | adding one. */ | |
2983 | ||
2984 | void | |
2985 | s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch) | |
2986 | { | |
2987 | HOST_WIDE_INT addend; | |
2988 | rtx symref; | |
2989 | ||
2990 | if (!s390_symref_operand_p (addr, &symref, &addend)) | |
2991 | gcc_unreachable (); | |
2992 | ||
2993 | if (!(addend & 1)) | |
2994 | /* Easy case. The addend is even so larl will do fine. */ | |
2995 | emit_move_insn (reg, addr); | |
2996 | else | |
2997 | { | |
2998 | /* We can leave the scratch register untouched if the target | |
2999 | register is a valid base register. */ | |
3000 | if (REGNO (reg) < FIRST_PSEUDO_REGISTER | |
3001 | && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS) | |
3002 | scratch = reg; | |
3003 | ||
3004 | gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER); | |
3005 | gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS); | |
3006 | ||
3007 | if (addend != 1) | |
3008 | emit_move_insn (scratch, | |
3009 | gen_rtx_CONST (Pmode, | |
3010 | gen_rtx_PLUS (Pmode, symref, | |
3011 | GEN_INT (addend - 1)))); | |
3012 | else | |
3013 | emit_move_insn (scratch, symref); | |
3014 | ||
3015 | /* Increment the address using la in order to avoid clobbering cc. */ | |
3016 | emit_move_insn (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx)); | |
3017 | } | |
3018 | } | |
3019 | ||
3020 | /* Generate what is necessary to move between REG and MEM using | |
3021 | SCRATCH. The direction is given by TOMEM. */ | |
3022 | ||
3023 | void | |
3024 | s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem) | |
3025 | { | |
3026 | /* Reload might have pulled a constant out of the literal pool. | |
3027 | Force it back in. */ | |
3028 | if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE | |
3029 | || GET_CODE (mem) == CONST) | |
3030 | mem = force_const_mem (GET_MODE (reg), mem); | |
3031 | ||
3032 | gcc_assert (MEM_P (mem)); | |
3033 | ||
3034 | /* For a load from memory we can leave the scratch register | |
3035 | untouched if the target register is a valid base register. */ | |
3036 | if (!tomem | |
3037 | && REGNO (reg) < FIRST_PSEUDO_REGISTER | |
3038 | && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS | |
3039 | && GET_MODE (reg) == GET_MODE (scratch)) | |
3040 | scratch = reg; | |
3041 | ||
3042 | /* Load address into scratch register. Since we can't have a | |
3043 | secondary reload for a secondary reload we have to cover the case | |
3044 | where larl would need a secondary reload here as well. */ | |
3045 | s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch); | |
3046 | ||
3047 | /* Now we can use a standard load/store to do the move. */ | |
3048 | if (tomem) | |
3049 | emit_move_insn (replace_equiv_address (mem, scratch), reg); | |
3050 | else | |
3051 | emit_move_insn (reg, replace_equiv_address (mem, scratch)); | |
3052 | } | |
3053 | ||
833cd70a | 3054 | /* Inform reload about cases where moving X with a mode MODE to a register in |
0a2aaacc | 3055 | RCLASS requires an extra scratch or immediate register. Return the class |
833cd70a | 3056 | needed for the immediate register. */ |
f61a2c7d | 3057 | |
a87cf97e JR |
3058 | static reg_class_t |
3059 | s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, | |
833cd70a AK |
3060 | enum machine_mode mode, secondary_reload_info *sri) |
3061 | { | |
a87cf97e JR |
3062 | enum reg_class rclass = (enum reg_class) rclass_i; |
3063 | ||
833cd70a | 3064 | /* Intermediate register needed. */ |
0a2aaacc | 3065 | if (reg_classes_intersect_p (CC_REGS, rclass)) |
9dc62c00 AK |
3066 | return GENERAL_REGS; |
3067 | ||
963fc8d0 AK |
3068 | if (TARGET_Z10) |
3069 | { | |
3070 | /* On z10 several optimizer steps may generate larl operands with | |
3071 | an odd addend. */ | |
3072 | if (in_p | |
3073 | && s390_symref_operand_p (x, NULL, NULL) | |
3074 | && mode == Pmode | |
3075 | && !s390_check_symref_alignment (x, 2)) | |
3076 | sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10 | |
3077 | : CODE_FOR_reloadsi_larl_odd_addend_z10); | |
3078 | ||
3079 | /* On z10 we need a scratch register when moving QI, TI or floating | |
3080 | point mode values from or to a memory location with a SYMBOL_REF | |
3081 | or if the symref addend of a SI or DI move is not aligned to the | |
3082 | width of the access. */ | |
3083 | if (MEM_P (x) | |
3084 | && s390_symref_operand_p (XEXP (x, 0), NULL, NULL) | |
3085 | && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode) | |
9602b6a1 | 3086 | || (!TARGET_ZARCH && mode == DImode) |
963fc8d0 AK |
3087 | || ((mode == HImode || mode == SImode || mode == DImode) |
3088 | && (!s390_check_symref_alignment (XEXP (x, 0), | |
3089 | GET_MODE_SIZE (mode)))))) | |
3090 | { | |
3091 | #define __SECONDARY_RELOAD_CASE(M,m) \ | |
3092 | case M##mode: \ | |
3093 | if (TARGET_64BIT) \ | |
3094 | sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \ | |
3095 | CODE_FOR_reload##m##di_tomem_z10; \ | |
3096 | else \ | |
3097 | sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \ | |
3098 | CODE_FOR_reload##m##si_tomem_z10; \ | |
3099 | break; | |
3100 | ||
3101 | switch (GET_MODE (x)) | |
3102 | { | |
3103 | __SECONDARY_RELOAD_CASE (QI, qi); | |
3104 | __SECONDARY_RELOAD_CASE (HI, hi); | |
3105 | __SECONDARY_RELOAD_CASE (SI, si); | |
3106 | __SECONDARY_RELOAD_CASE (DI, di); | |
3107 | __SECONDARY_RELOAD_CASE (TI, ti); | |
3108 | __SECONDARY_RELOAD_CASE (SF, sf); | |
3109 | __SECONDARY_RELOAD_CASE (DF, df); | |
3110 | __SECONDARY_RELOAD_CASE (TF, tf); | |
3111 | __SECONDARY_RELOAD_CASE (SD, sd); | |
3112 | __SECONDARY_RELOAD_CASE (DD, dd); | |
3113 | __SECONDARY_RELOAD_CASE (TD, td); | |
3114 | ||
3115 | default: | |
3116 | gcc_unreachable (); | |
3117 | } | |
3118 | #undef __SECONDARY_RELOAD_CASE | |
3119 | } | |
3120 | } | |
3121 | ||
833cd70a AK |
3122 | /* We need a scratch register when loading a PLUS expression which |
3123 | is not a legitimate operand of the LOAD ADDRESS instruction. */ | |
3124 | if (in_p && s390_plus_operand (x, mode)) | |
3125 | sri->icode = (TARGET_64BIT ? | |
3126 | CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus); | |
3127 | ||
7fa7289d | 3128 | /* Performing a multiword move from or to memory we have to make sure the |
833cd70a AK |
3129 | second chunk in memory is addressable without causing a displacement |
3130 | overflow. If that would be the case we calculate the address in | |
3131 | a scratch register. */ | |
3132 | if (MEM_P (x) | |
3133 | && GET_CODE (XEXP (x, 0)) == PLUS | |
3134 | && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT | |
3135 | && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1)) | |
0ca89db7 | 3136 | + GET_MODE_SIZE (mode) - 1)) |
833cd70a | 3137 | { |
7fa7289d | 3138 | /* For GENERAL_REGS a displacement overflow is no problem if occurring |
833cd70a AK |
3139 | in a s_operand address since we may fallback to lm/stm. So we only |
3140 | have to care about overflows in the b+i+d case. */ | |
0a2aaacc | 3141 | if ((reg_classes_intersect_p (GENERAL_REGS, rclass) |
833cd70a AK |
3142 | && s390_class_max_nregs (GENERAL_REGS, mode) > 1 |
3143 | && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS) | |
3144 | /* For FP_REGS no lm/stm is available so this check is triggered | |
3145 | for displacement overflows in b+i+d and b+d like addresses. */ | |
0a2aaacc | 3146 | || (reg_classes_intersect_p (FP_REGS, rclass) |
833cd70a AK |
3147 | && s390_class_max_nregs (FP_REGS, mode) > 1)) |
3148 | { | |
3149 | if (in_p) | |
3150 | sri->icode = (TARGET_64BIT ? | |
3151 | CODE_FOR_reloaddi_nonoffmem_in : | |
3152 | CODE_FOR_reloadsi_nonoffmem_in); | |
3153 | else | |
3154 | sri->icode = (TARGET_64BIT ? | |
3155 | CODE_FOR_reloaddi_nonoffmem_out : | |
3156 | CODE_FOR_reloadsi_nonoffmem_out); | |
3157 | } | |
3158 | } | |
9dc62c00 | 3159 | |
1f9e1fc6 AK |
3160 | /* A scratch address register is needed when a symbolic constant is |
3161 | copied to r0 compiling with -fPIC. In other cases the target | |
3162 | register might be used as temporary (see legitimize_pic_address). */ | |
0a2aaacc | 3163 | if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS) |
1f9e1fc6 AK |
3164 | sri->icode = (TARGET_64BIT ? |
3165 | CODE_FOR_reloaddi_PIC_addr : | |
3166 | CODE_FOR_reloadsi_PIC_addr); | |
3167 | ||
833cd70a | 3168 | /* Either scratch or no register needed. */ |
dc65c307 UW |
3169 | return NO_REGS; |
3170 | } | |
3171 | ||
f3e9edff UW |
3172 | /* Generate code to load SRC, which is PLUS that is not a |
3173 | legitimate operand for the LA instruction, into TARGET. | |
3174 | SCRATCH may be used as scratch register. */ | |
3175 | ||
3176 | void | |
5d81b82b AS |
3177 | s390_expand_plus_operand (rtx target, rtx src, |
3178 | rtx scratch) | |
f3e9edff | 3179 | { |
7974fe63 | 3180 | rtx sum1, sum2; |
b808c04c | 3181 | struct s390_address ad; |
6a4e49c1 | 3182 | |
6a4e49c1 | 3183 | /* src must be a PLUS; get its two operands. */ |
8d933e31 AS |
3184 | gcc_assert (GET_CODE (src) == PLUS); |
3185 | gcc_assert (GET_MODE (src) == Pmode); | |
f3e9edff | 3186 | |
7c82a1ed UW |
3187 | /* Check if any of the two operands is already scheduled |
3188 | for replacement by reload. This can happen e.g. when | |
3189 | float registers occur in an address. */ | |
3190 | sum1 = find_replacement (&XEXP (src, 0)); | |
3191 | sum2 = find_replacement (&XEXP (src, 1)); | |
ccfc6cc8 | 3192 | src = gen_rtx_PLUS (Pmode, sum1, sum2); |
ccfc6cc8 | 3193 | |
7974fe63 UW |
3194 | /* If the address is already strictly valid, there's nothing to do. */ |
3195 | if (!s390_decompose_address (src, &ad) | |
93fa8428 AK |
3196 | || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base))) |
3197 | || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))) | |
f3e9edff | 3198 | { |
7974fe63 UW |
3199 | /* Otherwise, one of the operands cannot be an address register; |
3200 | we reload its value into the scratch register. */ | |
3201 | if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15) | |
3202 | { | |
3203 | emit_move_insn (scratch, sum1); | |
3204 | sum1 = scratch; | |
3205 | } | |
3206 | if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15) | |
3207 | { | |
3208 | emit_move_insn (scratch, sum2); | |
3209 | sum2 = scratch; | |
3210 | } | |
f3e9edff | 3211 | |
7974fe63 UW |
3212 | /* According to the way these invalid addresses are generated |
3213 | in reload.c, it should never happen (at least on s390) that | |
3214 | *neither* of the PLUS components, after find_replacements | |
3215 | was applied, is an address register. */ | |
3216 | if (sum1 == scratch && sum2 == scratch) | |
3217 | { | |
3218 | debug_rtx (src); | |
8d933e31 | 3219 | gcc_unreachable (); |
7974fe63 | 3220 | } |
f3e9edff | 3221 | |
7974fe63 | 3222 | src = gen_rtx_PLUS (Pmode, sum1, sum2); |
f3e9edff UW |
3223 | } |
3224 | ||
3225 | /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS | |
3226 | is only ever performed on addresses, so we can mark the | |
3227 | sum as legitimate for LA in any case. */ | |
a41c6c53 | 3228 | s390_load_address (target, src); |
f3e9edff UW |
3229 | } |
3230 | ||
3231 | ||
3ed99cc9 | 3232 | /* Return true if ADDR is a valid memory address. |
ab96de7e | 3233 | STRICT specifies whether strict register checking applies. */ |
9db1d521 | 3234 | |
c6c3dba9 PB |
3235 | static bool |
3236 | s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict) | |
9db1d521 | 3237 | { |
ab96de7e | 3238 | struct s390_address ad; |
963fc8d0 AK |
3239 | |
3240 | if (TARGET_Z10 | |
3241 | && larl_operand (addr, VOIDmode) | |
3242 | && (mode == VOIDmode | |
3243 | || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode)))) | |
3244 | return true; | |
3245 | ||
ab96de7e | 3246 | if (!s390_decompose_address (addr, &ad)) |
3ed99cc9 | 3247 | return false; |
b808c04c UW |
3248 | |
3249 | if (strict) | |
3250 | { | |
93fa8428 | 3251 | if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base))) |
3ed99cc9 | 3252 | return false; |
93fa8428 AK |
3253 | |
3254 | if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))) | |
3ed99cc9 | 3255 | return false; |
b808c04c UW |
3256 | } |
3257 | else | |
3258 | { | |
f4aa3848 | 3259 | if (ad.base |
93fa8428 AK |
3260 | && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER |
3261 | || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS)) | |
3ed99cc9 | 3262 | return false; |
f4aa3848 | 3263 | |
93fa8428 AK |
3264 | if (ad.indx |
3265 | && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER | |
3266 | || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS)) | |
3267 | return false; | |
b808c04c | 3268 | } |
3ed99cc9 | 3269 | return true; |
9db1d521 HP |
3270 | } |
3271 | ||
3ed99cc9 | 3272 | /* Return true if OP is a valid operand for the LA instruction. |
ba956982 UW |
3273 | In 31-bit, we need to prove that the result is used as an |
3274 | address, as LA performs only a 31-bit addition. */ | |
3275 | ||
3ed99cc9 | 3276 | bool |
5d81b82b | 3277 | legitimate_la_operand_p (rtx op) |
ba956982 UW |
3278 | { |
3279 | struct s390_address addr; | |
b808c04c | 3280 | if (!s390_decompose_address (op, &addr)) |
3ed99cc9 | 3281 | return false; |
ba956982 | 3282 | |
3ed99cc9 | 3283 | return (TARGET_64BIT || addr.pointer); |
f3e9edff | 3284 | } |
ba956982 | 3285 | |
3ed99cc9 | 3286 | /* Return true if it is valid *and* preferable to use LA to |
e1d5ee28 | 3287 | compute the sum of OP1 and OP2. */ |
c7453384 | 3288 | |
3ed99cc9 | 3289 | bool |
e1d5ee28 | 3290 | preferred_la_operand_p (rtx op1, rtx op2) |
100c7420 UW |
3291 | { |
3292 | struct s390_address addr; | |
e1d5ee28 UW |
3293 | |
3294 | if (op2 != const0_rtx) | |
3295 | op1 = gen_rtx_PLUS (Pmode, op1, op2); | |
3296 | ||
3297 | if (!s390_decompose_address (op1, &addr)) | |
3ed99cc9 | 3298 | return false; |
93fa8428 | 3299 | if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base))) |
3ed99cc9 | 3300 | return false; |
93fa8428 | 3301 | if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx))) |
3ed99cc9 | 3302 | return false; |
100c7420 | 3303 | |
65b1d8ea AK |
3304 | /* Avoid LA instructions with index register on z196; it is |
3305 | preferable to use regular add instructions when possible. */ | |
3306 | if (addr.indx && s390_tune == PROCESSOR_2817_Z196) | |
3307 | return false; | |
3308 | ||
100c7420 | 3309 | if (!TARGET_64BIT && !addr.pointer) |
3ed99cc9 | 3310 | return false; |
100c7420 UW |
3311 | |
3312 | if (addr.pointer) | |
3ed99cc9 | 3313 | return true; |
100c7420 | 3314 | |
4888ec5d UW |
3315 | if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base)) |
3316 | || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx))) | |
3ed99cc9 | 3317 | return true; |
100c7420 | 3318 | |
3ed99cc9 | 3319 | return false; |
100c7420 UW |
3320 | } |
3321 | ||
a41c6c53 UW |
3322 | /* Emit a forced load-address operation to load SRC into DST. |
3323 | This will use the LOAD ADDRESS instruction even in situations | |
3324 | where legitimate_la_operand_p (SRC) returns false. */ | |
ba956982 | 3325 | |
a41c6c53 | 3326 | void |
9c808aad | 3327 | s390_load_address (rtx dst, rtx src) |
f3e9edff | 3328 | { |
a41c6c53 UW |
3329 | if (TARGET_64BIT) |
3330 | emit_move_insn (dst, src); | |
3331 | else | |
3332 | emit_insn (gen_force_la_31 (dst, src)); | |
ba956982 UW |
3333 | } |
3334 | ||
9db1d521 HP |
3335 | /* Return a legitimate reference for ORIG (an address) using the |
3336 | register REG. If REG is 0, a new pseudo is generated. | |
3337 | ||
3338 | There are two types of references that must be handled: | |
3339 | ||
3340 | 1. Global data references must load the address from the GOT, via | |
3341 | the PIC reg. An insn is emitted to do this load, and the reg is | |
3342 | returned. | |
3343 | ||
3344 | 2. Static data references, constant pool addresses, and code labels | |
3345 | compute the address as an offset from the GOT, whose base is in | |
114278e7 | 3346 | the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to |
9db1d521 HP |
3347 | differentiate them from global data objects. The returned |
3348 | address is the PIC reg + an unspec constant. | |
3349 | ||
331d9186 | 3350 | TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC |
9db1d521 HP |
3351 | reg also appears in the address. */ |
3352 | ||
3353 | rtx | |
9c808aad | 3354 | legitimize_pic_address (rtx orig, rtx reg) |
9db1d521 HP |
3355 | { |
3356 | rtx addr = orig; | |
0a2aaacc | 3357 | rtx new_rtx = orig; |
9db1d521 HP |
3358 | rtx base; |
3359 | ||
cf9d7618 ANM |
3360 | gcc_assert (!TLS_SYMBOLIC_CONST (addr)); |
3361 | ||
9db1d521 | 3362 | if (GET_CODE (addr) == LABEL_REF |
114278e7 | 3363 | || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr))) |
9db1d521 HP |
3364 | { |
3365 | /* This is a local symbol. */ | |
9e8327e3 | 3366 | if (TARGET_CPU_ZARCH && larl_operand (addr, VOIDmode)) |
9db1d521 | 3367 | { |
c7453384 EC |
3368 | /* Access local symbols PC-relative via LARL. |
3369 | This is the same as in the non-PIC case, so it is | |
d65f7478 | 3370 | handled automatically ... */ |
9db1d521 HP |
3371 | } |
3372 | else | |
3373 | { | |
fd7643fb | 3374 | /* Access local symbols relative to the GOT. */ |
9db1d521 HP |
3375 | |
3376 | rtx temp = reg? reg : gen_reg_rtx (Pmode); | |
3377 | ||
fd7643fb | 3378 | if (reload_in_progress || reload_completed) |
6fb5fa3c | 3379 | df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); |
fd7643fb UW |
3380 | |
3381 | addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF); | |
e23795ea UW |
3382 | addr = gen_rtx_CONST (Pmode, addr); |
3383 | addr = force_const_mem (Pmode, addr); | |
9db1d521 HP |
3384 | emit_move_insn (temp, addr); |
3385 | ||
0a2aaacc | 3386 | new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp); |
9db1d521 HP |
3387 | if (reg != 0) |
3388 | { | |
0a2aaacc KG |
3389 | s390_load_address (reg, new_rtx); |
3390 | new_rtx = reg; | |
9db1d521 HP |
3391 | } |
3392 | } | |
3393 | } | |
3394 | else if (GET_CODE (addr) == SYMBOL_REF) | |
3395 | { | |
3396 | if (reg == 0) | |
3397 | reg = gen_reg_rtx (Pmode); | |
3398 | ||
3399 | if (flag_pic == 1) | |
3400 | { | |
3401 | /* Assume GOT offset < 4k. This is handled the same way | |
fd7643fb | 3402 | in both 31- and 64-bit code (@GOT). */ |
9db1d521 | 3403 | |
c3cc6b78 | 3404 | if (reload_in_progress || reload_completed) |
6fb5fa3c | 3405 | df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); |
9db1d521 | 3406 | |
0a2aaacc KG |
3407 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT); |
3408 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
3409 | new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx); | |
3410 | new_rtx = gen_const_mem (Pmode, new_rtx); | |
3411 | emit_move_insn (reg, new_rtx); | |
3412 | new_rtx = reg; | |
9db1d521 | 3413 | } |
9e8327e3 | 3414 | else if (TARGET_CPU_ZARCH) |
9db1d521 HP |
3415 | { |
3416 | /* If the GOT offset might be >= 4k, we determine the position | |
3417 | of the GOT entry via a PC-relative LARL (@GOTENT). */ | |
3418 | ||
1f9e1fc6 AK |
3419 | rtx temp = reg ? reg : gen_reg_rtx (Pmode); |
3420 | ||
3421 | gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER | |
3422 | || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS); | |
9db1d521 | 3423 | |
0a2aaacc KG |
3424 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT); |
3425 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
3426 | emit_move_insn (temp, new_rtx); | |
9db1d521 | 3427 | |
0a2aaacc KG |
3428 | new_rtx = gen_const_mem (Pmode, temp); |
3429 | emit_move_insn (reg, new_rtx); | |
3430 | new_rtx = reg; | |
9db1d521 HP |
3431 | } |
3432 | else | |
3433 | { | |
c7453384 | 3434 | /* If the GOT offset might be >= 4k, we have to load it |
9db1d521 HP |
3435 | from the literal pool (@GOT). */ |
3436 | ||
1f9e1fc6 AK |
3437 | rtx temp = reg ? reg : gen_reg_rtx (Pmode); |
3438 | ||
3439 | gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER | |
3440 | || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS); | |
9db1d521 | 3441 | |
c3cc6b78 | 3442 | if (reload_in_progress || reload_completed) |
6fb5fa3c | 3443 | df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); |
9db1d521 | 3444 | |
fd7643fb | 3445 | addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT); |
e23795ea UW |
3446 | addr = gen_rtx_CONST (Pmode, addr); |
3447 | addr = force_const_mem (Pmode, addr); | |
9db1d521 HP |
3448 | emit_move_insn (temp, addr); |
3449 | ||
0a2aaacc KG |
3450 | new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp); |
3451 | new_rtx = gen_const_mem (Pmode, new_rtx); | |
3452 | emit_move_insn (reg, new_rtx); | |
3453 | new_rtx = reg; | |
9db1d521 | 3454 | } |
c7453384 | 3455 | } |
9db1d521 HP |
3456 | else |
3457 | { | |
3458 | if (GET_CODE (addr) == CONST) | |
3459 | { | |
3460 | addr = XEXP (addr, 0); | |
3461 | if (GET_CODE (addr) == UNSPEC) | |
3462 | { | |
8d933e31 | 3463 | gcc_assert (XVECLEN (addr, 0) == 1); |
9db1d521 HP |
3464 | switch (XINT (addr, 1)) |
3465 | { | |
fd7643fb | 3466 | /* If someone moved a GOT-relative UNSPEC |
9db1d521 | 3467 | out of the literal pool, force them back in. */ |
fd7643fb UW |
3468 | case UNSPEC_GOTOFF: |
3469 | case UNSPEC_PLTOFF: | |
0a2aaacc | 3470 | new_rtx = force_const_mem (Pmode, orig); |
9db1d521 HP |
3471 | break; |
3472 | ||
fd7643fb UW |
3473 | /* @GOT is OK as is if small. */ |
3474 | case UNSPEC_GOT: | |
3475 | if (flag_pic == 2) | |
0a2aaacc | 3476 | new_rtx = force_const_mem (Pmode, orig); |
fd7643fb UW |
3477 | break; |
3478 | ||
9db1d521 | 3479 | /* @GOTENT is OK as is. */ |
fd7643fb | 3480 | case UNSPEC_GOTENT: |
9db1d521 HP |
3481 | break; |
3482 | ||
3483 | /* @PLT is OK as is on 64-bit, must be converted to | |
fd7643fb UW |
3484 | GOT-relative @PLTOFF on 31-bit. */ |
3485 | case UNSPEC_PLT: | |
9e8327e3 | 3486 | if (!TARGET_CPU_ZARCH) |
9db1d521 HP |
3487 | { |
3488 | rtx temp = reg? reg : gen_reg_rtx (Pmode); | |
3489 | ||
fd7643fb | 3490 | if (reload_in_progress || reload_completed) |
6fb5fa3c | 3491 | df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); |
fd7643fb | 3492 | |
9db1d521 | 3493 | addr = XVECEXP (addr, 0, 0); |
c7453384 | 3494 | addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), |
fd7643fb | 3495 | UNSPEC_PLTOFF); |
e23795ea UW |
3496 | addr = gen_rtx_CONST (Pmode, addr); |
3497 | addr = force_const_mem (Pmode, addr); | |
9db1d521 HP |
3498 | emit_move_insn (temp, addr); |
3499 | ||
0a2aaacc | 3500 | new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp); |
9db1d521 HP |
3501 | if (reg != 0) |
3502 | { | |
0a2aaacc KG |
3503 | s390_load_address (reg, new_rtx); |
3504 | new_rtx = reg; | |
9db1d521 HP |
3505 | } |
3506 | } | |
3507 | break; | |
3508 | ||
3509 | /* Everything else cannot happen. */ | |
3510 | default: | |
8d933e31 | 3511 | gcc_unreachable (); |
9db1d521 HP |
3512 | } |
3513 | } | |
f4aa3848 | 3514 | else |
8d933e31 | 3515 | gcc_assert (GET_CODE (addr) == PLUS); |
9db1d521 HP |
3516 | } |
3517 | if (GET_CODE (addr) == PLUS) | |
3518 | { | |
3519 | rtx op0 = XEXP (addr, 0), op1 = XEXP (addr, 1); | |
cf9d7618 ANM |
3520 | |
3521 | gcc_assert (!TLS_SYMBOLIC_CONST (op0)); | |
3522 | gcc_assert (!TLS_SYMBOLIC_CONST (op1)); | |
3523 | ||
c7453384 | 3524 | /* Check first to see if this is a constant offset |
9db1d521 HP |
3525 | from a local symbol reference. */ |
3526 | if ((GET_CODE (op0) == LABEL_REF | |
114278e7 | 3527 | || (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op0))) |
9db1d521 HP |
3528 | && GET_CODE (op1) == CONST_INT) |
3529 | { | |
e064939e MM |
3530 | if (TARGET_CPU_ZARCH |
3531 | && larl_operand (op0, VOIDmode) | |
3532 | && INTVAL (op1) < (HOST_WIDE_INT)1 << 31 | |
3533 | && INTVAL (op1) >= -((HOST_WIDE_INT)1 << 31)) | |
9db1d521 HP |
3534 | { |
3535 | if (INTVAL (op1) & 1) | |
3536 | { | |
c7453384 | 3537 | /* LARL can't handle odd offsets, so emit a |
9db1d521 HP |
3538 | pair of LARL and LA. */ |
3539 | rtx temp = reg? reg : gen_reg_rtx (Pmode); | |
3540 | ||
d3632d41 | 3541 | if (!DISP_IN_RANGE (INTVAL (op1))) |
9db1d521 | 3542 | { |
e064939e | 3543 | HOST_WIDE_INT even = INTVAL (op1) - 1; |
9db1d521 | 3544 | op0 = gen_rtx_PLUS (Pmode, op0, GEN_INT (even)); |
b30d2115 | 3545 | op0 = gen_rtx_CONST (Pmode, op0); |
a556fd39 | 3546 | op1 = const1_rtx; |
9db1d521 HP |
3547 | } |
3548 | ||
3549 | emit_move_insn (temp, op0); | |
0a2aaacc | 3550 | new_rtx = gen_rtx_PLUS (Pmode, temp, op1); |
9db1d521 HP |
3551 | |
3552 | if (reg != 0) | |
3553 | { | |
0a2aaacc KG |
3554 | s390_load_address (reg, new_rtx); |
3555 | new_rtx = reg; | |
9db1d521 HP |
3556 | } |
3557 | } | |
3558 | else | |
3559 | { | |
3560 | /* If the offset is even, we can just use LARL. | |
3561 | This will happen automatically. */ | |
3562 | } | |
3563 | } | |
3564 | else | |
3565 | { | |
fd7643fb | 3566 | /* Access local symbols relative to the GOT. */ |
9db1d521 HP |
3567 | |
3568 | rtx temp = reg? reg : gen_reg_rtx (Pmode); | |
3569 | ||
fd7643fb | 3570 | if (reload_in_progress || reload_completed) |
6fb5fa3c | 3571 | df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); |
fd7643fb | 3572 | |
c7453384 | 3573 | addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0), |
fd7643fb | 3574 | UNSPEC_GOTOFF); |
e23795ea UW |
3575 | addr = gen_rtx_PLUS (Pmode, addr, op1); |
3576 | addr = gen_rtx_CONST (Pmode, addr); | |
3577 | addr = force_const_mem (Pmode, addr); | |
cfbab41c | 3578 | emit_move_insn (temp, addr); |
9db1d521 | 3579 | |
0a2aaacc | 3580 | new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp); |
9db1d521 HP |
3581 | if (reg != 0) |
3582 | { | |
0a2aaacc KG |
3583 | s390_load_address (reg, new_rtx); |
3584 | new_rtx = reg; | |
9db1d521 HP |
3585 | } |
3586 | } | |
3587 | } | |
3588 | ||
fd7643fb | 3589 | /* Now, check whether it is a GOT relative symbol plus offset |
9db1d521 HP |
3590 | that was pulled out of the literal pool. Force it back in. */ |
3591 | ||
3592 | else if (GET_CODE (op0) == UNSPEC | |
cfbab41c JJ |
3593 | && GET_CODE (op1) == CONST_INT |
3594 | && XINT (op0, 1) == UNSPEC_GOTOFF) | |
9db1d521 | 3595 | { |
8d933e31 | 3596 | gcc_assert (XVECLEN (op0, 0) == 1); |
9db1d521 | 3597 | |
0a2aaacc | 3598 | new_rtx = force_const_mem (Pmode, orig); |
9db1d521 HP |
3599 | } |
3600 | ||
3601 | /* Otherwise, compute the sum. */ | |
3602 | else | |
3603 | { | |
3604 | base = legitimize_pic_address (XEXP (addr, 0), reg); | |
0a2aaacc | 3605 | new_rtx = legitimize_pic_address (XEXP (addr, 1), |
9db1d521 | 3606 | base == reg ? NULL_RTX : reg); |
0a2aaacc KG |
3607 | if (GET_CODE (new_rtx) == CONST_INT) |
3608 | new_rtx = plus_constant (base, INTVAL (new_rtx)); | |
9db1d521 HP |
3609 | else |
3610 | { | |
0a2aaacc | 3611 | if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1))) |
9db1d521 | 3612 | { |
0a2aaacc KG |
3613 | base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0)); |
3614 | new_rtx = XEXP (new_rtx, 1); | |
9db1d521 | 3615 | } |
0a2aaacc | 3616 | new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx); |
9db1d521 HP |
3617 | } |
3618 | ||
0a2aaacc KG |
3619 | if (GET_CODE (new_rtx) == CONST) |
3620 | new_rtx = XEXP (new_rtx, 0); | |
3621 | new_rtx = force_operand (new_rtx, 0); | |
9db1d521 HP |
3622 | } |
3623 | } | |
3624 | } | |
0a2aaacc | 3625 | return new_rtx; |
9db1d521 HP |
3626 | } |
3627 | ||
fd3cd001 UW |
3628 | /* Load the thread pointer into a register. */ |
3629 | ||
7b8acc34 AK |
3630 | rtx |
3631 | s390_get_thread_pointer (void) | |
fd3cd001 | 3632 | { |
c5aa1d12 | 3633 | rtx tp = gen_reg_rtx (Pmode); |
fd3cd001 | 3634 | |
c5aa1d12 | 3635 | emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM)); |
fd3cd001 UW |
3636 | mark_reg_pointer (tp, BITS_PER_WORD); |
3637 | ||
3638 | return tp; | |
3639 | } | |
3640 | ||
ed9676cf AK |
3641 | /* Emit a tls call insn. The call target is the SYMBOL_REF stored |
3642 | in s390_tls_symbol which always refers to __tls_get_offset. | |
3643 | The returned offset is written to RESULT_REG and an USE rtx is | |
3644 | generated for TLS_CALL. */ | |
fd3cd001 UW |
3645 | |
3646 | static GTY(()) rtx s390_tls_symbol; | |
ed9676cf AK |
3647 | |
3648 | static void | |
3649 | s390_emit_tls_call_insn (rtx result_reg, rtx tls_call) | |
fd3cd001 | 3650 | { |
ed9676cf | 3651 | rtx insn; |
38899e29 | 3652 | |
8d933e31 | 3653 | gcc_assert (flag_pic); |
ed9676cf | 3654 | |
fd3cd001 UW |
3655 | if (!s390_tls_symbol) |
3656 | s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset"); | |
3657 | ||
38899e29 EC |
3658 | insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg, |
3659 | gen_rtx_REG (Pmode, RETURN_REGNUM)); | |
ed9676cf AK |
3660 | |
3661 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg); | |
becfd6e5 | 3662 | RTL_CONST_CALL_P (insn) = 1; |
fd3cd001 UW |
3663 | } |
3664 | ||
3665 | /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute | |
3666 | this (thread-local) address. REG may be used as temporary. */ | |
3667 | ||
3668 | static rtx | |
9c808aad | 3669 | legitimize_tls_address (rtx addr, rtx reg) |
fd3cd001 | 3670 | { |
0a2aaacc | 3671 | rtx new_rtx, tls_call, temp, base, r2, insn; |
fd3cd001 UW |
3672 | |
3673 | if (GET_CODE (addr) == SYMBOL_REF) | |
3674 | switch (tls_symbolic_operand (addr)) | |
3675 | { | |
3676 | case TLS_MODEL_GLOBAL_DYNAMIC: | |
3677 | start_sequence (); | |
3678 | r2 = gen_rtx_REG (Pmode, 2); | |
3679 | tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD); | |
0a2aaacc KG |
3680 | new_rtx = gen_rtx_CONST (Pmode, tls_call); |
3681 | new_rtx = force_const_mem (Pmode, new_rtx); | |
3682 | emit_move_insn (r2, new_rtx); | |
ed9676cf | 3683 | s390_emit_tls_call_insn (r2, tls_call); |
fd3cd001 UW |
3684 | insn = get_insns (); |
3685 | end_sequence (); | |
3686 | ||
0a2aaacc | 3687 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF); |
fd3cd001 | 3688 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 3689 | emit_libcall_block (insn, temp, r2, new_rtx); |
fd3cd001 | 3690 | |
0a2aaacc | 3691 | new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp); |
fd3cd001 UW |
3692 | if (reg != 0) |
3693 | { | |
0a2aaacc KG |
3694 | s390_load_address (reg, new_rtx); |
3695 | new_rtx = reg; | |
fd3cd001 UW |
3696 | } |
3697 | break; | |
3698 | ||
3699 | case TLS_MODEL_LOCAL_DYNAMIC: | |
3700 | start_sequence (); | |
3701 | r2 = gen_rtx_REG (Pmode, 2); | |
3702 | tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM); | |
0a2aaacc KG |
3703 | new_rtx = gen_rtx_CONST (Pmode, tls_call); |
3704 | new_rtx = force_const_mem (Pmode, new_rtx); | |
3705 | emit_move_insn (r2, new_rtx); | |
ed9676cf | 3706 | s390_emit_tls_call_insn (r2, tls_call); |
fd3cd001 UW |
3707 | insn = get_insns (); |
3708 | end_sequence (); | |
3709 | ||
0a2aaacc | 3710 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF); |
fd3cd001 | 3711 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 3712 | emit_libcall_block (insn, temp, r2, new_rtx); |
fd3cd001 | 3713 | |
0a2aaacc | 3714 | new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp); |
fd3cd001 | 3715 | base = gen_reg_rtx (Pmode); |
0a2aaacc | 3716 | s390_load_address (base, new_rtx); |
fd3cd001 | 3717 | |
0a2aaacc KG |
3718 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF); |
3719 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
3720 | new_rtx = force_const_mem (Pmode, new_rtx); | |
fd3cd001 | 3721 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 3722 | emit_move_insn (temp, new_rtx); |
fd3cd001 | 3723 | |
0a2aaacc | 3724 | new_rtx = gen_rtx_PLUS (Pmode, base, temp); |
fd3cd001 UW |
3725 | if (reg != 0) |
3726 | { | |
0a2aaacc KG |
3727 | s390_load_address (reg, new_rtx); |
3728 | new_rtx = reg; | |
fd3cd001 UW |
3729 | } |
3730 | break; | |
3731 | ||
3732 | case TLS_MODEL_INITIAL_EXEC: | |
3733 | if (flag_pic == 1) | |
3734 | { | |
3735 | /* Assume GOT offset < 4k. This is handled the same way | |
3736 | in both 31- and 64-bit code. */ | |
3737 | ||
3738 | if (reload_in_progress || reload_completed) | |
6fb5fa3c | 3739 | df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); |
fd3cd001 | 3740 | |
0a2aaacc KG |
3741 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF); |
3742 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
3743 | new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx); | |
3744 | new_rtx = gen_const_mem (Pmode, new_rtx); | |
fd3cd001 | 3745 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 3746 | emit_move_insn (temp, new_rtx); |
fd3cd001 | 3747 | } |
9e8327e3 | 3748 | else if (TARGET_CPU_ZARCH) |
fd3cd001 UW |
3749 | { |
3750 | /* If the GOT offset might be >= 4k, we determine the position | |
3751 | of the GOT entry via a PC-relative LARL. */ | |
3752 | ||
0a2aaacc KG |
3753 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF); |
3754 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
fd3cd001 | 3755 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 3756 | emit_move_insn (temp, new_rtx); |
fd3cd001 | 3757 | |
0a2aaacc | 3758 | new_rtx = gen_const_mem (Pmode, temp); |
fd3cd001 | 3759 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 3760 | emit_move_insn (temp, new_rtx); |
fd3cd001 UW |
3761 | } |
3762 | else if (flag_pic) | |
3763 | { | |
c7453384 | 3764 | /* If the GOT offset might be >= 4k, we have to load it |
fd3cd001 UW |
3765 | from the literal pool. */ |
3766 | ||
3767 | if (reload_in_progress || reload_completed) | |
6fb5fa3c | 3768 | df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true); |
fd3cd001 | 3769 | |
0a2aaacc KG |
3770 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF); |
3771 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
3772 | new_rtx = force_const_mem (Pmode, new_rtx); | |
fd3cd001 | 3773 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 3774 | emit_move_insn (temp, new_rtx); |
fd3cd001 | 3775 | |
0a2aaacc KG |
3776 | new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp); |
3777 | new_rtx = gen_const_mem (Pmode, new_rtx); | |
fd3cd001 | 3778 | |
0a2aaacc | 3779 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD); |
fd3cd001 | 3780 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 3781 | emit_insn (gen_rtx_SET (Pmode, temp, new_rtx)); |
fd3cd001 UW |
3782 | } |
3783 | else | |
3784 | { | |
3785 | /* In position-dependent code, load the absolute address of | |
3786 | the GOT entry from the literal pool. */ | |
3787 | ||
0a2aaacc KG |
3788 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF); |
3789 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
3790 | new_rtx = force_const_mem (Pmode, new_rtx); | |
fd3cd001 | 3791 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 3792 | emit_move_insn (temp, new_rtx); |
fd3cd001 | 3793 | |
0a2aaacc KG |
3794 | new_rtx = temp; |
3795 | new_rtx = gen_const_mem (Pmode, new_rtx); | |
3796 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD); | |
fd3cd001 | 3797 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 3798 | emit_insn (gen_rtx_SET (Pmode, temp, new_rtx)); |
fd3cd001 UW |
3799 | } |
3800 | ||
0a2aaacc | 3801 | new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp); |
fd3cd001 UW |
3802 | if (reg != 0) |
3803 | { | |
0a2aaacc KG |
3804 | s390_load_address (reg, new_rtx); |
3805 | new_rtx = reg; | |
fd3cd001 UW |
3806 | } |
3807 | break; | |
3808 | ||
3809 | case TLS_MODEL_LOCAL_EXEC: | |
0a2aaacc KG |
3810 | new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF); |
3811 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
3812 | new_rtx = force_const_mem (Pmode, new_rtx); | |
fd3cd001 | 3813 | temp = gen_reg_rtx (Pmode); |
0a2aaacc | 3814 | emit_move_insn (temp, new_rtx); |
fd3cd001 | 3815 | |
0a2aaacc | 3816 | new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp); |
fd3cd001 UW |
3817 | if (reg != 0) |
3818 | { | |
0a2aaacc KG |
3819 | s390_load_address (reg, new_rtx); |
3820 | new_rtx = reg; | |
fd3cd001 UW |
3821 | } |
3822 | break; | |
3823 | ||
3824 | default: | |
8d933e31 | 3825 | gcc_unreachable (); |
fd3cd001 UW |
3826 | } |
3827 | ||
3828 | else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC) | |
3829 | { | |
3830 | switch (XINT (XEXP (addr, 0), 1)) | |
3831 | { | |
3832 | case UNSPEC_INDNTPOFF: | |
8d933e31 | 3833 | gcc_assert (TARGET_CPU_ZARCH); |
0a2aaacc | 3834 | new_rtx = addr; |
fd3cd001 UW |
3835 | break; |
3836 | ||
3837 | default: | |
8d933e31 | 3838 | gcc_unreachable (); |
fd3cd001 UW |
3839 | } |
3840 | } | |
3841 | ||
578d1468 UW |
3842 | else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS |
3843 | && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT) | |
3844 | { | |
0a2aaacc KG |
3845 | new_rtx = XEXP (XEXP (addr, 0), 0); |
3846 | if (GET_CODE (new_rtx) != SYMBOL_REF) | |
3847 | new_rtx = gen_rtx_CONST (Pmode, new_rtx); | |
578d1468 | 3848 | |
0a2aaacc KG |
3849 | new_rtx = legitimize_tls_address (new_rtx, reg); |
3850 | new_rtx = plus_constant (new_rtx, INTVAL (XEXP (XEXP (addr, 0), 1))); | |
3851 | new_rtx = force_operand (new_rtx, 0); | |
578d1468 UW |
3852 | } |
3853 | ||
fd3cd001 | 3854 | else |
8d933e31 | 3855 | gcc_unreachable (); /* for now ... */ |
fd3cd001 | 3856 | |
0a2aaacc | 3857 | return new_rtx; |
fd3cd001 UW |
3858 | } |
3859 | ||
1f9e1fc6 AK |
3860 | /* Emit insns making the address in operands[1] valid for a standard |
3861 | move to operands[0]. operands[1] is replaced by an address which | |
3862 | should be used instead of the former RTX to emit the move | |
3863 | pattern. */ | |
9db1d521 HP |
3864 | |
3865 | void | |
9c808aad | 3866 | emit_symbolic_move (rtx *operands) |
9db1d521 | 3867 | { |
b3a13419 | 3868 | rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); |
9db1d521 | 3869 | |
fd3cd001 | 3870 | if (GET_CODE (operands[0]) == MEM) |
9db1d521 | 3871 | operands[1] = force_reg (Pmode, operands[1]); |
fd3cd001 UW |
3872 | else if (TLS_SYMBOLIC_CONST (operands[1])) |
3873 | operands[1] = legitimize_tls_address (operands[1], temp); | |
3874 | else if (flag_pic) | |
9db1d521 HP |
3875 | operands[1] = legitimize_pic_address (operands[1], temp); |
3876 | } | |
3877 | ||
994fe660 | 3878 | /* Try machine-dependent ways of modifying an illegitimate address X |
9db1d521 | 3879 | to be legitimate. If we find one, return the new, valid address. |
9db1d521 HP |
3880 | |
3881 | OLDX is the address as it was before break_out_memory_refs was called. | |
3882 | In some cases it is useful to look at this to decide what needs to be done. | |
3883 | ||
994fe660 | 3884 | MODE is the mode of the operand pointed to by X. |
9db1d521 HP |
3885 | |
3886 | When -fpic is used, special handling is needed for symbolic references. | |
3887 | See comments by legitimize_pic_address for details. */ | |
3888 | ||
506d7b68 PB |
3889 | static rtx |
3890 | s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, | |
3891 | enum machine_mode mode ATTRIBUTE_UNUSED) | |
9db1d521 | 3892 | { |
ba956982 | 3893 | rtx constant_term = const0_rtx; |
9db1d521 | 3894 | |
fd3cd001 UW |
3895 | if (TLS_SYMBOLIC_CONST (x)) |
3896 | { | |
3897 | x = legitimize_tls_address (x, 0); | |
3898 | ||
c6c3dba9 | 3899 | if (s390_legitimate_address_p (mode, x, FALSE)) |
fd3cd001 UW |
3900 | return x; |
3901 | } | |
cf9d7618 | 3902 | else if (GET_CODE (x) == PLUS |
f4aa3848 | 3903 | && (TLS_SYMBOLIC_CONST (XEXP (x, 0)) |
cf9d7618 ANM |
3904 | || TLS_SYMBOLIC_CONST (XEXP (x, 1)))) |
3905 | { | |
3906 | return x; | |
3907 | } | |
fd3cd001 | 3908 | else if (flag_pic) |
9db1d521 | 3909 | { |
ba956982 | 3910 | if (SYMBOLIC_CONST (x) |
c7453384 EC |
3911 | || (GET_CODE (x) == PLUS |
3912 | && (SYMBOLIC_CONST (XEXP (x, 0)) | |
ba956982 UW |
3913 | || SYMBOLIC_CONST (XEXP (x, 1))))) |
3914 | x = legitimize_pic_address (x, 0); | |
3915 | ||
c6c3dba9 | 3916 | if (s390_legitimate_address_p (mode, x, FALSE)) |
ba956982 | 3917 | return x; |
9db1d521 | 3918 | } |
9db1d521 | 3919 | |
ba956982 | 3920 | x = eliminate_constant_term (x, &constant_term); |
994fe660 | 3921 | |
61f02ff5 UW |
3922 | /* Optimize loading of large displacements by splitting them |
3923 | into the multiple of 4K and the rest; this allows the | |
c7453384 | 3924 | former to be CSE'd if possible. |
61f02ff5 UW |
3925 | |
3926 | Don't do this if the displacement is added to a register | |
3927 | pointing into the stack frame, as the offsets will | |
3928 | change later anyway. */ | |
3929 | ||
3930 | if (GET_CODE (constant_term) == CONST_INT | |
d3632d41 UW |
3931 | && !TARGET_LONG_DISPLACEMENT |
3932 | && !DISP_IN_RANGE (INTVAL (constant_term)) | |
61f02ff5 UW |
3933 | && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x)))) |
3934 | { | |
3935 | HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff; | |
3936 | HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower; | |
3937 | ||
3938 | rtx temp = gen_reg_rtx (Pmode); | |
3939 | rtx val = force_operand (GEN_INT (upper), temp); | |
3940 | if (val != temp) | |
3941 | emit_move_insn (temp, val); | |
3942 | ||
3943 | x = gen_rtx_PLUS (Pmode, x, temp); | |
3944 | constant_term = GEN_INT (lower); | |
3945 | } | |
3946 | ||
ba956982 | 3947 | if (GET_CODE (x) == PLUS) |
9db1d521 | 3948 | { |
ba956982 UW |
3949 | if (GET_CODE (XEXP (x, 0)) == REG) |
3950 | { | |
5d81b82b AS |
3951 | rtx temp = gen_reg_rtx (Pmode); |
3952 | rtx val = force_operand (XEXP (x, 1), temp); | |
ba956982 UW |
3953 | if (val != temp) |
3954 | emit_move_insn (temp, val); | |
3955 | ||
3956 | x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp); | |
3957 | } | |
3958 | ||
3959 | else if (GET_CODE (XEXP (x, 1)) == REG) | |
3960 | { | |
5d81b82b AS |
3961 | rtx temp = gen_reg_rtx (Pmode); |
3962 | rtx val = force_operand (XEXP (x, 0), temp); | |
ba956982 UW |
3963 | if (val != temp) |
3964 | emit_move_insn (temp, val); | |
3965 | ||
3966 | x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1)); | |
3967 | } | |
9db1d521 | 3968 | } |
ba956982 UW |
3969 | |
3970 | if (constant_term != const0_rtx) | |
3971 | x = gen_rtx_PLUS (Pmode, x, constant_term); | |
3972 | ||
3973 | return x; | |
9db1d521 HP |
3974 | } |
3975 | ||
0b540f12 UW |
3976 | /* Try a machine-dependent way of reloading an illegitimate address AD |
3977 | operand. If we find one, push the reload and and return the new address. | |
3978 | ||
3979 | MODE is the mode of the enclosing MEM. OPNUM is the operand number | |
3980 | and TYPE is the reload type of the current reload. */ | |
3981 | ||
f4aa3848 | 3982 | rtx |
0b540f12 UW |
3983 | legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED, |
3984 | int opnum, int type) | |
3985 | { | |
3986 | if (!optimize || TARGET_LONG_DISPLACEMENT) | |
3987 | return NULL_RTX; | |
3988 | ||
3989 | if (GET_CODE (ad) == PLUS) | |
3990 | { | |
3991 | rtx tem = simplify_binary_operation (PLUS, Pmode, | |
3992 | XEXP (ad, 0), XEXP (ad, 1)); | |
3993 | if (tem) | |
3994 | ad = tem; | |
3995 | } | |
3996 | ||
3997 | if (GET_CODE (ad) == PLUS | |
3998 | && GET_CODE (XEXP (ad, 0)) == REG | |
3999 | && GET_CODE (XEXP (ad, 1)) == CONST_INT | |
4000 | && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1)))) | |
4001 | { | |
4002 | HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff; | |
4003 | HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower; | |
0a2aaacc | 4004 | rtx cst, tem, new_rtx; |
0b540f12 UW |
4005 | |
4006 | cst = GEN_INT (upper); | |
4007 | if (!legitimate_reload_constant_p (cst)) | |
4008 | cst = force_const_mem (Pmode, cst); | |
4009 | ||
4010 | tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst); | |
0a2aaacc | 4011 | new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower)); |
0b540f12 UW |
4012 | |
4013 | push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0, | |
f4aa3848 | 4014 | BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, |
0b540f12 | 4015 | opnum, (enum reload_type) type); |
0a2aaacc | 4016 | return new_rtx; |
0b540f12 UW |
4017 | } |
4018 | ||
4019 | return NULL_RTX; | |
4020 | } | |
4021 | ||
a41c6c53 UW |
4022 | /* Emit code to move LEN bytes from DST to SRC. */ |
4023 | ||
4024 | void | |
70128ad9 | 4025 | s390_expand_movmem (rtx dst, rtx src, rtx len) |
a41c6c53 | 4026 | { |
a41c6c53 UW |
4027 | if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256) |
4028 | { | |
4029 | if (INTVAL (len) > 0) | |
70128ad9 | 4030 | emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1))); |
a41c6c53 UW |
4031 | } |
4032 | ||
4033 | else if (TARGET_MVCLE) | |
4034 | { | |
70128ad9 | 4035 | emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1))); |
a41c6c53 UW |
4036 | } |
4037 | ||
4038 | else | |
4039 | { | |
4040 | rtx dst_addr, src_addr, count, blocks, temp; | |
70315fcd | 4041 | rtx loop_start_label = gen_label_rtx (); |
6de9cd9a | 4042 | rtx loop_end_label = gen_label_rtx (); |
a41c6c53 UW |
4043 | rtx end_label = gen_label_rtx (); |
4044 | enum machine_mode mode; | |
a41c6c53 UW |
4045 | |
4046 | mode = GET_MODE (len); | |
4047 | if (mode == VOIDmode) | |
b9404c99 | 4048 | mode = Pmode; |
a41c6c53 | 4049 | |
a41c6c53 UW |
4050 | dst_addr = gen_reg_rtx (Pmode); |
4051 | src_addr = gen_reg_rtx (Pmode); | |
4052 | count = gen_reg_rtx (mode); | |
4053 | blocks = gen_reg_rtx (mode); | |
4054 | ||
4055 | convert_move (count, len, 1); | |
c7453384 | 4056 | emit_cmp_and_jump_insns (count, const0_rtx, |
a41c6c53 UW |
4057 | EQ, NULL_RTX, mode, 1, end_label); |
4058 | ||
4059 | emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX)); | |
4060 | emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX)); | |
4061 | dst = change_address (dst, VOIDmode, dst_addr); | |
4062 | src = change_address (src, VOIDmode, src_addr); | |
c7453384 | 4063 | |
bbbbb16a ILT |
4064 | temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, |
4065 | OPTAB_DIRECT); | |
a41c6c53 UW |
4066 | if (temp != count) |
4067 | emit_move_insn (count, temp); | |
4068 | ||
bbbbb16a ILT |
4069 | temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1, |
4070 | OPTAB_DIRECT); | |
a41c6c53 UW |
4071 | if (temp != blocks) |
4072 | emit_move_insn (blocks, temp); | |
4073 | ||
6de9cd9a DN |
4074 | emit_cmp_and_jump_insns (blocks, const0_rtx, |
4075 | EQ, NULL_RTX, mode, 1, loop_end_label); | |
70315fcd SB |
4076 | |
4077 | emit_label (loop_start_label); | |
a41c6c53 | 4078 | |
adfa3cd3 AK |
4079 | if (TARGET_Z10 |
4080 | && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768)) | |
4081 | { | |
4082 | rtx prefetch; | |
4083 | ||
4084 | /* Issue a read prefetch for the +3 cache line. */ | |
4085 | prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)), | |
4086 | const0_rtx, const0_rtx); | |
4087 | PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true; | |
4088 | emit_insn (prefetch); | |
4089 | ||
4090 | /* Issue a write prefetch for the +3 cache line. */ | |
4091 | prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)), | |
4092 | const1_rtx, const0_rtx); | |
4093 | PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true; | |
4094 | emit_insn (prefetch); | |
4095 | } | |
4096 | ||
70128ad9 | 4097 | emit_insn (gen_movmem_short (dst, src, GEN_INT (255))); |
c7453384 | 4098 | s390_load_address (dst_addr, |
a41c6c53 | 4099 | gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256))); |
c7453384 | 4100 | s390_load_address (src_addr, |
a41c6c53 | 4101 | gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256))); |
c7453384 | 4102 | |
bbbbb16a ILT |
4103 | temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, |
4104 | OPTAB_DIRECT); | |
a41c6c53 UW |
4105 | if (temp != blocks) |
4106 | emit_move_insn (blocks, temp); | |
4107 | ||
6de9cd9a DN |
4108 | emit_cmp_and_jump_insns (blocks, const0_rtx, |
4109 | EQ, NULL_RTX, mode, 1, loop_end_label); | |
70315fcd SB |
4110 | |
4111 | emit_jump (loop_start_label); | |
6de9cd9a | 4112 | emit_label (loop_end_label); |
a41c6c53 | 4113 | |
70128ad9 | 4114 | emit_insn (gen_movmem_short (dst, src, |
b9404c99 | 4115 | convert_to_mode (Pmode, count, 1))); |
a41c6c53 UW |
4116 | emit_label (end_label); |
4117 | } | |
4118 | } | |
4119 | ||
6d057022 AS |
4120 | /* Emit code to set LEN bytes at DST to VAL. |
4121 | Make use of clrmem if VAL is zero. */ | |
a41c6c53 UW |
4122 | |
4123 | void | |
6d057022 | 4124 | s390_expand_setmem (rtx dst, rtx len, rtx val) |
a41c6c53 | 4125 | { |
c9f59991 AK |
4126 | if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0) |
4127 | return; | |
4128 | ||
6d057022 | 4129 | gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode); |
f4aa3848 | 4130 | |
c9f59991 | 4131 | if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257) |
a41c6c53 | 4132 | { |
6d057022 | 4133 | if (val == const0_rtx && INTVAL (len) <= 256) |
70128ad9 | 4134 | emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1))); |
6d057022 AS |
4135 | else |
4136 | { | |
4137 | /* Initialize memory by storing the first byte. */ | |
4138 | emit_move_insn (adjust_address (dst, QImode, 0), val); | |
f4aa3848 | 4139 | |
6d057022 AS |
4140 | if (INTVAL (len) > 1) |
4141 | { | |
4142 | /* Initiate 1 byte overlap move. | |
4143 | The first byte of DST is propagated through DSTP1. | |
4144 | Prepare a movmem for: DST+1 = DST (length = LEN - 1). | |
4145 | DST is set to size 1 so the rest of the memory location | |
4146 | does not count as source operand. */ | |
4147 | rtx dstp1 = adjust_address (dst, VOIDmode, 1); | |
4148 | set_mem_size (dst, const1_rtx); | |
4149 | ||
f4aa3848 | 4150 | emit_insn (gen_movmem_short (dstp1, dst, |
6d057022 AS |
4151 | GEN_INT (INTVAL (len) - 2))); |
4152 | } | |
4153 | } | |
a41c6c53 UW |
4154 | } |
4155 | ||
4156 | else if (TARGET_MVCLE) | |
4157 | { | |
6d057022 AS |
4158 | val = force_not_mem (convert_modes (Pmode, QImode, val, 1)); |
4159 | emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val)); | |
a41c6c53 UW |
4160 | } |
4161 | ||
4162 | else | |
4163 | { | |
9602b6a1 | 4164 | rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX; |
70315fcd | 4165 | rtx loop_start_label = gen_label_rtx (); |
6de9cd9a | 4166 | rtx loop_end_label = gen_label_rtx (); |
a41c6c53 UW |
4167 | rtx end_label = gen_label_rtx (); |
4168 | enum machine_mode mode; | |
a41c6c53 UW |
4169 | |
4170 | mode = GET_MODE (len); | |
4171 | if (mode == VOIDmode) | |
b9404c99 | 4172 | mode = Pmode; |
a41c6c53 | 4173 | |
a41c6c53 | 4174 | dst_addr = gen_reg_rtx (Pmode); |
a41c6c53 UW |
4175 | count = gen_reg_rtx (mode); |
4176 | blocks = gen_reg_rtx (mode); | |
4177 | ||
4178 | convert_move (count, len, 1); | |
c7453384 | 4179 | emit_cmp_and_jump_insns (count, const0_rtx, |
a41c6c53 UW |
4180 | EQ, NULL_RTX, mode, 1, end_label); |
4181 | ||
4182 | emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX)); | |
4183 | dst = change_address (dst, VOIDmode, dst_addr); | |
c7453384 | 4184 | |
6d057022 | 4185 | if (val == const0_rtx) |
bbbbb16a ILT |
4186 | temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, |
4187 | OPTAB_DIRECT); | |
6d057022 AS |
4188 | else |
4189 | { | |
4190 | dstp1 = adjust_address (dst, VOIDmode, 1); | |
4191 | set_mem_size (dst, const1_rtx); | |
4192 | ||
4193 | /* Initialize memory by storing the first byte. */ | |
4194 | emit_move_insn (adjust_address (dst, QImode, 0), val); | |
f4aa3848 | 4195 | |
6d057022 AS |
4196 | /* If count is 1 we are done. */ |
4197 | emit_cmp_and_jump_insns (count, const1_rtx, | |
4198 | EQ, NULL_RTX, mode, 1, end_label); | |
4199 | ||
bbbbb16a ILT |
4200 | temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1, |
4201 | OPTAB_DIRECT); | |
6d057022 | 4202 | } |
a41c6c53 UW |
4203 | if (temp != count) |
4204 | emit_move_insn (count, temp); | |
4205 | ||
bbbbb16a ILT |
4206 | temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1, |
4207 | OPTAB_DIRECT); | |
a41c6c53 UW |
4208 | if (temp != blocks) |
4209 | emit_move_insn (blocks, temp); | |
4210 | ||
6de9cd9a DN |
4211 | emit_cmp_and_jump_insns (blocks, const0_rtx, |
4212 | EQ, NULL_RTX, mode, 1, loop_end_label); | |
70315fcd SB |
4213 | |
4214 | emit_label (loop_start_label); | |
a41c6c53 | 4215 | |
adfa3cd3 AK |
4216 | if (TARGET_Z10 |
4217 | && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024)) | |
4218 | { | |
4219 | /* Issue a write prefetch for the +4 cache line. */ | |
4220 | rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, | |
4221 | GEN_INT (1024)), | |
4222 | const1_rtx, const0_rtx); | |
4223 | emit_insn (prefetch); | |
4224 | PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true; | |
4225 | } | |
4226 | ||
6d057022 AS |
4227 | if (val == const0_rtx) |
4228 | emit_insn (gen_clrmem_short (dst, GEN_INT (255))); | |
4229 | else | |
4230 | emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255))); | |
c7453384 | 4231 | s390_load_address (dst_addr, |
a41c6c53 | 4232 | gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256))); |
c7453384 | 4233 | |
bbbbb16a ILT |
4234 | temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, |
4235 | OPTAB_DIRECT); | |
a41c6c53 UW |
4236 | if (temp != blocks) |
4237 | emit_move_insn (blocks, temp); | |
4238 | ||
6de9cd9a DN |
4239 | emit_cmp_and_jump_insns (blocks, const0_rtx, |
4240 | EQ, NULL_RTX, mode, 1, loop_end_label); | |
70315fcd SB |
4241 | |
4242 | emit_jump (loop_start_label); | |
6de9cd9a | 4243 | emit_label (loop_end_label); |
a41c6c53 | 4244 | |
6d057022 AS |
4245 | if (val == const0_rtx) |
4246 | emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1))); | |
4247 | else | |
4248 | emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1))); | |
a41c6c53 UW |
4249 | emit_label (end_label); |
4250 | } | |
4251 | } | |
4252 | ||
4253 | /* Emit code to compare LEN bytes at OP0 with those at OP1, | |
4254 | and return the result in TARGET. */ | |
4255 | ||
4256 | void | |
9c808aad | 4257 | s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len) |
a41c6c53 | 4258 | { |
5b022de5 | 4259 | rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM); |
02887425 UW |
4260 | rtx tmp; |
4261 | ||
4262 | /* As the result of CMPINT is inverted compared to what we need, | |
4263 | we have to swap the operands. */ | |
4264 | tmp = op0; op0 = op1; op1 = tmp; | |
a41c6c53 | 4265 | |
a41c6c53 UW |
4266 | if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256) |
4267 | { | |
4268 | if (INTVAL (len) > 0) | |
4269 | { | |
b9404c99 | 4270 | emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1))); |
02887425 | 4271 | emit_insn (gen_cmpint (target, ccreg)); |
a41c6c53 UW |
4272 | } |
4273 | else | |
4274 | emit_move_insn (target, const0_rtx); | |
4275 | } | |
9dc62c00 | 4276 | else if (TARGET_MVCLE) |
a41c6c53 | 4277 | { |
b9404c99 | 4278 | emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1))); |
02887425 | 4279 | emit_insn (gen_cmpint (target, ccreg)); |
a41c6c53 | 4280 | } |
a41c6c53 UW |
4281 | else |
4282 | { | |
4283 | rtx addr0, addr1, count, blocks, temp; | |
70315fcd | 4284 | rtx loop_start_label = gen_label_rtx (); |
6de9cd9a | 4285 | rtx loop_end_label = gen_label_rtx (); |
a41c6c53 UW |
4286 | rtx end_label = gen_label_rtx (); |
4287 | enum machine_mode mode; | |
a41c6c53 UW |
4288 | |
4289 | mode = GET_MODE (len); | |
4290 | if (mode == VOIDmode) | |
b9404c99 | 4291 | mode = Pmode; |
a41c6c53 | 4292 | |
a41c6c53 UW |
4293 | addr0 = gen_reg_rtx (Pmode); |
4294 | addr1 = gen_reg_rtx (Pmode); | |
4295 | count = gen_reg_rtx (mode); | |
4296 | blocks = gen_reg_rtx (mode); | |
4297 | ||
4298 | convert_move (count, len, 1); | |
c7453384 | 4299 | emit_cmp_and_jump_insns (count, const0_rtx, |
a41c6c53 UW |
4300 | EQ, NULL_RTX, mode, 1, end_label); |
4301 | ||
4302 | emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX)); | |
4303 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
4304 | op0 = change_address (op0, VOIDmode, addr0); | |
4305 | op1 = change_address (op1, VOIDmode, addr1); | |
c7453384 | 4306 | |
bbbbb16a ILT |
4307 | temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1, |
4308 | OPTAB_DIRECT); | |
a41c6c53 UW |
4309 | if (temp != count) |
4310 | emit_move_insn (count, temp); | |
4311 | ||
bbbbb16a ILT |
4312 | temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1, |
4313 | OPTAB_DIRECT); | |
a41c6c53 UW |
4314 | if (temp != blocks) |
4315 | emit_move_insn (blocks, temp); | |
4316 | ||
6de9cd9a DN |
4317 | emit_cmp_and_jump_insns (blocks, const0_rtx, |
4318 | EQ, NULL_RTX, mode, 1, loop_end_label); | |
70315fcd SB |
4319 | |
4320 | emit_label (loop_start_label); | |
a41c6c53 | 4321 | |
adfa3cd3 AK |
4322 | if (TARGET_Z10 |
4323 | && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512)) | |
4324 | { | |
4325 | rtx prefetch; | |
4326 | ||
4327 | /* Issue a read prefetch for the +2 cache line of operand 1. */ | |
4328 | prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)), | |
4329 | const0_rtx, const0_rtx); | |
4330 | emit_insn (prefetch); | |
4331 | PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true; | |
4332 | ||
4333 | /* Issue a read prefetch for the +2 cache line of operand 2. */ | |
4334 | prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)), | |
4335 | const0_rtx, const0_rtx); | |
4336 | emit_insn (prefetch); | |
4337 | PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true; | |
4338 | } | |
4339 | ||
b9404c99 | 4340 | emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255))); |
5b022de5 | 4341 | temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx); |
c7453384 | 4342 | temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp, |
a41c6c53 UW |
4343 | gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx); |
4344 | temp = gen_rtx_SET (VOIDmode, pc_rtx, temp); | |
4345 | emit_jump_insn (temp); | |
4346 | ||
c7453384 | 4347 | s390_load_address (addr0, |
a41c6c53 | 4348 | gen_rtx_PLUS (Pmode, addr0, GEN_INT (256))); |
c7453384 | 4349 | s390_load_address (addr1, |
a41c6c53 | 4350 | gen_rtx_PLUS (Pmode, addr1, GEN_INT (256))); |
c7453384 | 4351 | |
bbbbb16a ILT |
4352 | temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1, |
4353 | OPTAB_DIRECT); | |
a41c6c53 UW |
4354 | if (temp != blocks) |
4355 | emit_move_insn (blocks, temp); | |
4356 | ||
6de9cd9a DN |
4357 | emit_cmp_and_jump_insns (blocks, const0_rtx, |
4358 | EQ, NULL_RTX, mode, 1, loop_end_label); | |
70315fcd SB |
4359 | |
4360 | emit_jump (loop_start_label); | |
6de9cd9a | 4361 | emit_label (loop_end_label); |
a41c6c53 | 4362 | |
38899e29 | 4363 | emit_insn (gen_cmpmem_short (op0, op1, |
b9404c99 | 4364 | convert_to_mode (Pmode, count, 1))); |
a41c6c53 UW |
4365 | emit_label (end_label); |
4366 | ||
02887425 | 4367 | emit_insn (gen_cmpint (target, ccreg)); |
a41c6c53 UW |
4368 | } |
4369 | } | |
4370 | ||
5d880bd2 UW |
4371 | |
4372 | /* Expand conditional increment or decrement using alc/slb instructions. | |
4373 | Should generate code setting DST to either SRC or SRC + INCREMENT, | |
4374 | depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1. | |
00bda920 AK |
4375 | Returns true if successful, false otherwise. |
4376 | ||
4377 | That makes it possible to implement some if-constructs without jumps e.g.: | |
4378 | (borrow = CC0 | CC1 and carry = CC2 | CC3) | |
4379 | unsigned int a, b, c; | |
4380 | if (a < b) c++; -> CCU b > a -> CC2; c += carry; | |
4381 | if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow; | |
4382 | if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry; | |
4383 | if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow; | |
4384 | ||
4385 | Checks for EQ and NE with a nonzero value need an additional xor e.g.: | |
4386 | if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry; | |
4387 | if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow; | |
4388 | if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry; | |
4389 | if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */ | |
5d880bd2 UW |
4390 | |
4391 | bool | |
4392 | s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1, | |
4393 | rtx dst, rtx src, rtx increment) | |
4394 | { | |
4395 | enum machine_mode cmp_mode; | |
4396 | enum machine_mode cc_mode; | |
4397 | rtx op_res; | |
4398 | rtx insn; | |
4399 | rtvec p; | |
8d933e31 | 4400 | int ret; |
5d880bd2 UW |
4401 | |
4402 | if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode) | |
4403 | && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode)) | |
4404 | cmp_mode = SImode; | |
4405 | else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode) | |
4406 | && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode)) | |
4407 | cmp_mode = DImode; | |
4408 | else | |
4409 | return false; | |
4410 | ||
4411 | /* Try ADD LOGICAL WITH CARRY. */ | |
4412 | if (increment == const1_rtx) | |
4413 | { | |
4414 | /* Determine CC mode to use. */ | |
4415 | if (cmp_code == EQ || cmp_code == NE) | |
4416 | { | |
4417 | if (cmp_op1 != const0_rtx) | |
4418 | { | |
4419 | cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1, | |
4420 | NULL_RTX, 0, OPTAB_WIDEN); | |
4421 | cmp_op1 = const0_rtx; | |
4422 | } | |
4423 | ||
4424 | cmp_code = cmp_code == EQ ? LEU : GTU; | |
4425 | } | |
4426 | ||
4427 | if (cmp_code == LTU || cmp_code == LEU) | |
4428 | { | |
4429 | rtx tem = cmp_op0; | |
4430 | cmp_op0 = cmp_op1; | |
4431 | cmp_op1 = tem; | |
4432 | cmp_code = swap_condition (cmp_code); | |
4433 | } | |
4434 | ||
4435 | switch (cmp_code) | |
4436 | { | |
4437 | case GTU: | |
4438 | cc_mode = CCUmode; | |
4439 | break; | |
4440 | ||
4441 | case GEU: | |
4442 | cc_mode = CCL3mode; | |
4443 | break; | |
4444 | ||
4445 | default: | |
4446 | return false; | |
4447 | } | |
4448 | ||
4449 | /* Emit comparison instruction pattern. */ | |
4450 | if (!register_operand (cmp_op0, cmp_mode)) | |
4451 | cmp_op0 = force_reg (cmp_mode, cmp_op0); | |
4452 | ||
4453 | insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM), | |
4454 | gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1)); | |
4455 | /* We use insn_invalid_p here to add clobbers if required. */ | |
8d933e31 AS |
4456 | ret = insn_invalid_p (emit_insn (insn)); |
4457 | gcc_assert (!ret); | |
5d880bd2 UW |
4458 | |
4459 | /* Emit ALC instruction pattern. */ | |
4460 | op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst), | |
4461 | gen_rtx_REG (cc_mode, CC_REGNUM), | |
4462 | const0_rtx); | |
4463 | ||
4464 | if (src != const0_rtx) | |
4465 | { | |
4466 | if (!register_operand (src, GET_MODE (dst))) | |
4467 | src = force_reg (GET_MODE (dst), src); | |
4468 | ||
a94a76a7 UW |
4469 | op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src); |
4470 | op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx); | |
5d880bd2 UW |
4471 | } |
4472 | ||
4473 | p = rtvec_alloc (2); | |
f4aa3848 | 4474 | RTVEC_ELT (p, 0) = |
5d880bd2 | 4475 | gen_rtx_SET (VOIDmode, dst, op_res); |
f4aa3848 | 4476 | RTVEC_ELT (p, 1) = |
5d880bd2 UW |
4477 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); |
4478 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
4479 | ||
4480 | return true; | |
4481 | } | |
4482 | ||
4483 | /* Try SUBTRACT LOGICAL WITH BORROW. */ | |
4484 | if (increment == constm1_rtx) | |
4485 | { | |
4486 | /* Determine CC mode to use. */ | |
4487 | if (cmp_code == EQ || cmp_code == NE) | |
4488 | { | |
4489 | if (cmp_op1 != const0_rtx) | |
4490 | { | |
4491 | cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1, | |
4492 | NULL_RTX, 0, OPTAB_WIDEN); | |
4493 | cmp_op1 = const0_rtx; | |
4494 | } | |
4495 | ||
4496 | cmp_code = cmp_code == EQ ? LEU : GTU; | |
4497 | } | |
4498 | ||
4499 | if (cmp_code == GTU || cmp_code == GEU) | |
4500 | { | |
4501 | rtx tem = cmp_op0; | |
4502 | cmp_op0 = cmp_op1; | |
4503 | cmp_op1 = tem; | |
4504 | cmp_code = swap_condition (cmp_code); | |
4505 | } | |
4506 | ||
4507 | switch (cmp_code) | |
4508 | { | |
4509 | case LEU: | |
4510 | cc_mode = CCUmode; | |
4511 | break; | |
4512 | ||
4513 | case LTU: | |
4514 | cc_mode = CCL3mode; | |
4515 | break; | |
4516 | ||
4517 | default: | |
4518 | return false; | |
4519 | } | |
4520 | ||
4521 | /* Emit comparison instruction pattern. */ | |
4522 | if (!register_operand (cmp_op0, cmp_mode)) | |
4523 | cmp_op0 = force_reg (cmp_mode, cmp_op0); | |
4524 | ||
4525 | insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM), | |
4526 | gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1)); | |
4527 | /* We use insn_invalid_p here to add clobbers if required. */ | |
8d933e31 AS |
4528 | ret = insn_invalid_p (emit_insn (insn)); |
4529 | gcc_assert (!ret); | |
5d880bd2 UW |
4530 | |
4531 | /* Emit SLB instruction pattern. */ | |
4532 | if (!register_operand (src, GET_MODE (dst))) | |
4533 | src = force_reg (GET_MODE (dst), src); | |
4534 | ||
f4aa3848 AK |
4535 | op_res = gen_rtx_MINUS (GET_MODE (dst), |
4536 | gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx), | |
4537 | gen_rtx_fmt_ee (cmp_code, GET_MODE (dst), | |
4538 | gen_rtx_REG (cc_mode, CC_REGNUM), | |
5d880bd2 UW |
4539 | const0_rtx)); |
4540 | p = rtvec_alloc (2); | |
f4aa3848 | 4541 | RTVEC_ELT (p, 0) = |
5d880bd2 | 4542 | gen_rtx_SET (VOIDmode, dst, op_res); |
f4aa3848 | 4543 | RTVEC_ELT (p, 1) = |
5d880bd2 UW |
4544 | gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); |
4545 | emit_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
4546 | ||
4547 | return true; | |
4548 | } | |
4549 | ||
4550 | return false; | |
4551 | } | |
4552 | ||
963fc8d0 | 4553 | /* Expand code for the insv template. Return true if successful. */ |
6fa05db6 | 4554 | |
963fc8d0 | 4555 | bool |
6fa05db6 AS |
4556 | s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src) |
4557 | { | |
4558 | int bitsize = INTVAL (op1); | |
4559 | int bitpos = INTVAL (op2); | |
4560 | ||
963fc8d0 AK |
4561 | /* On z10 we can use the risbg instruction to implement insv. */ |
4562 | if (TARGET_Z10 | |
4563 | && ((GET_MODE (dest) == DImode && GET_MODE (src) == DImode) | |
4564 | || (GET_MODE (dest) == SImode && GET_MODE (src) == SImode))) | |
4565 | { | |
4566 | rtx op; | |
4567 | rtx clobber; | |
4568 | ||
4569 | op = gen_rtx_SET (GET_MODE(src), | |
4570 | gen_rtx_ZERO_EXTRACT (GET_MODE (dest), dest, op1, op2), | |
4571 | src); | |
4572 | clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM)); | |
4573 | emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber))); | |
4574 | ||
4575 | return true; | |
4576 | } | |
4577 | ||
c83eecad | 4578 | /* We need byte alignment. */ |
6fa05db6 AS |
4579 | if (bitsize % BITS_PER_UNIT) |
4580 | return false; | |
4581 | ||
4582 | if (bitpos == 0 | |
4583 | && memory_operand (dest, VOIDmode) | |
4584 | && (register_operand (src, word_mode) | |
4585 | || const_int_operand (src, VOIDmode))) | |
4586 | { | |
4587 | /* Emit standard pattern if possible. */ | |
4588 | enum machine_mode mode = smallest_mode_for_size (bitsize, MODE_INT); | |
4589 | if (GET_MODE_BITSIZE (mode) == bitsize) | |
4590 | emit_move_insn (adjust_address (dest, mode, 0), gen_lowpart (mode, src)); | |
4591 | ||
4592 | /* (set (ze (mem)) (const_int)). */ | |
4593 | else if (const_int_operand (src, VOIDmode)) | |
4594 | { | |
4595 | int size = bitsize / BITS_PER_UNIT; | |
4596 | rtx src_mem = adjust_address (force_const_mem (word_mode, src), BLKmode, | |
4597 | GET_MODE_SIZE (word_mode) - size); | |
4598 | ||
4599 | dest = adjust_address (dest, BLKmode, 0); | |
4600 | set_mem_size (dest, GEN_INT (size)); | |
4601 | s390_expand_movmem (dest, src_mem, GEN_INT (size)); | |
4602 | } | |
f4aa3848 | 4603 | |
6fa05db6 AS |
4604 | /* (set (ze (mem)) (reg)). */ |
4605 | else if (register_operand (src, word_mode)) | |
4606 | { | |
4607 | if (bitsize <= GET_MODE_BITSIZE (SImode)) | |
4608 | emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1, | |
4609 | const0_rtx), src); | |
4610 | else | |
4611 | { | |
4612 | /* Emit st,stcmh sequence. */ | |
4613 | int stcmh_width = bitsize - GET_MODE_BITSIZE (SImode); | |
4614 | int size = stcmh_width / BITS_PER_UNIT; | |
4615 | ||
f4aa3848 | 4616 | emit_move_insn (adjust_address (dest, SImode, size), |
6fa05db6 AS |
4617 | gen_lowpart (SImode, src)); |
4618 | set_mem_size (dest, GEN_INT (size)); | |
4619 | emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, GEN_INT | |
4620 | (stcmh_width), const0_rtx), | |
4621 | gen_rtx_LSHIFTRT (word_mode, src, GEN_INT | |
4622 | (GET_MODE_BITSIZE (SImode)))); | |
4623 | } | |
4624 | } | |
4625 | else | |
4626 | return false; | |
4627 | ||
4628 | return true; | |
4629 | } | |
4630 | ||
4631 | /* (set (ze (reg)) (const_int)). */ | |
4632 | if (TARGET_ZARCH | |
f4aa3848 | 4633 | && register_operand (dest, word_mode) |
6fa05db6 AS |
4634 | && (bitpos % 16) == 0 |
4635 | && (bitsize % 16) == 0 | |
4636 | && const_int_operand (src, VOIDmode)) | |
4637 | { | |
4638 | HOST_WIDE_INT val = INTVAL (src); | |
4639 | int regpos = bitpos + bitsize; | |
4640 | ||
4641 | while (regpos > bitpos) | |
4642 | { | |
4643 | enum machine_mode putmode; | |
4644 | int putsize; | |
4645 | ||
4646 | if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32)) | |
4647 | putmode = SImode; | |
4648 | else | |
4649 | putmode = HImode; | |
4650 | ||
4651 | putsize = GET_MODE_BITSIZE (putmode); | |
4652 | regpos -= putsize; | |
f4aa3848 | 4653 | emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, |
6fa05db6 | 4654 | GEN_INT (putsize), |
f4aa3848 | 4655 | GEN_INT (regpos)), |
6fa05db6 AS |
4656 | gen_int_mode (val, putmode)); |
4657 | val >>= putsize; | |
4658 | } | |
4659 | gcc_assert (regpos == bitpos); | |
4660 | return true; | |
4661 | } | |
4662 | ||
4663 | return false; | |
4664 | } | |
5d880bd2 | 4665 | |
45d18331 AS |
4666 | /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a |
4667 | register that holds VAL of mode MODE shifted by COUNT bits. */ | |
3093f076 AS |
4668 | |
4669 | static inline rtx | |
4670 | s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count) | |
4671 | { | |
4672 | val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)), | |
4673 | NULL_RTX, 1, OPTAB_DIRECT); | |
f4aa3848 | 4674 | return expand_simple_binop (SImode, ASHIFT, val, count, |
3093f076 AS |
4675 | NULL_RTX, 1, OPTAB_DIRECT); |
4676 | } | |
4677 | ||
4678 | /* Structure to hold the initial parameters for a compare_and_swap operation | |
f4aa3848 | 4679 | in HImode and QImode. */ |
3093f076 AS |
4680 | |
4681 | struct alignment_context | |
4682 | { | |
f4aa3848 | 4683 | rtx memsi; /* SI aligned memory location. */ |
3093f076 AS |
4684 | rtx shift; /* Bit offset with regard to lsb. */ |
4685 | rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */ | |
4686 | rtx modemaski; /* ~modemask */ | |
6416ae7f | 4687 | bool aligned; /* True if memory is aligned, false else. */ |
3093f076 AS |
4688 | }; |
4689 | ||
45d18331 AS |
4690 | /* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize |
4691 | structure AC for transparent simplifying, if the memory alignment is known | |
4692 | to be at least 32bit. MEM is the memory location for the actual operation | |
4693 | and MODE its mode. */ | |
3093f076 AS |
4694 | |
4695 | static void | |
4696 | init_alignment_context (struct alignment_context *ac, rtx mem, | |
4697 | enum machine_mode mode) | |
4698 | { | |
4699 | ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode)); | |
4700 | ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode)); | |
4701 | ||
4702 | if (ac->aligned) | |
4703 | ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */ | |
4704 | else | |
4705 | { | |
4706 | /* Alignment is unknown. */ | |
4707 | rtx byteoffset, addr, align; | |
4708 | ||
4709 | /* Force the address into a register. */ | |
4710 | addr = force_reg (Pmode, XEXP (mem, 0)); | |
4711 | ||
4712 | /* Align it to SImode. */ | |
4713 | align = expand_simple_binop (Pmode, AND, addr, | |
4714 | GEN_INT (-GET_MODE_SIZE (SImode)), | |
4715 | NULL_RTX, 1, OPTAB_DIRECT); | |
4716 | /* Generate MEM. */ | |
4717 | ac->memsi = gen_rtx_MEM (SImode, align); | |
4718 | MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem); | |
44d64274 | 4719 | set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER); |
3093f076 AS |
4720 | set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode)); |
4721 | ||
4722 | /* Calculate shiftcount. */ | |
4723 | byteoffset = expand_simple_binop (Pmode, AND, addr, | |
4724 | GEN_INT (GET_MODE_SIZE (SImode) - 1), | |
4725 | NULL_RTX, 1, OPTAB_DIRECT); | |
4726 | /* As we already have some offset, evaluate the remaining distance. */ | |
4727 | ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset, | |
4728 | NULL_RTX, 1, OPTAB_DIRECT); | |
4729 | ||
4730 | } | |
4731 | /* Shift is the byte count, but we need the bitcount. */ | |
4732 | ac->shift = expand_simple_binop (SImode, MULT, ac->shift, GEN_INT (BITS_PER_UNIT), | |
4733 | NULL_RTX, 1, OPTAB_DIRECT); | |
4734 | /* Calculate masks. */ | |
f4aa3848 | 4735 | ac->modemask = expand_simple_binop (SImode, ASHIFT, |
3093f076 AS |
4736 | GEN_INT (GET_MODE_MASK (mode)), ac->shift, |
4737 | NULL_RTX, 1, OPTAB_DIRECT); | |
4738 | ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1); | |
4739 | } | |
4740 | ||
4741 | /* Expand an atomic compare and swap operation for HImode and QImode. MEM is | |
0a2aaacc | 4742 | the memory location, CMP the old value to compare MEM with and NEW_RTX the value |
3093f076 AS |
4743 | to set if CMP == MEM. |
4744 | CMP is never in memory for compare_and_swap_cc because | |
4745 | expand_bool_compare_and_swap puts it into a register for later compare. */ | |
4746 | ||
4747 | void | |
0a2aaacc | 4748 | s390_expand_cs_hqi (enum machine_mode mode, rtx target, rtx mem, rtx cmp, rtx new_rtx) |
3093f076 AS |
4749 | { |
4750 | struct alignment_context ac; | |
4751 | rtx cmpv, newv, val, resv, cc; | |
4752 | rtx res = gen_reg_rtx (SImode); | |
4753 | rtx csloop = gen_label_rtx (); | |
4754 | rtx csend = gen_label_rtx (); | |
4755 | ||
4756 | gcc_assert (register_operand (target, VOIDmode)); | |
4757 | gcc_assert (MEM_P (mem)); | |
4758 | ||
4759 | init_alignment_context (&ac, mem, mode); | |
4760 | ||
4761 | /* Shift the values to the correct bit positions. */ | |
4762 | if (!(ac.aligned && MEM_P (cmp))) | |
4763 | cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift); | |
0a2aaacc KG |
4764 | if (!(ac.aligned && MEM_P (new_rtx))) |
4765 | new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift); | |
3093f076 AS |
4766 | |
4767 | /* Load full word. Subsequent loads are performed by CS. */ | |
4768 | val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski, | |
4769 | NULL_RTX, 1, OPTAB_DIRECT); | |
4770 | ||
4771 | /* Start CS loop. */ | |
4772 | emit_label (csloop); | |
f4aa3848 | 4773 | /* val = "<mem>00..0<mem>" |
3093f076 | 4774 | * cmp = "00..0<cmp>00..0" |
f4aa3848 | 4775 | * new = "00..0<new>00..0" |
3093f076 AS |
4776 | */ |
4777 | ||
4778 | /* Patch cmp and new with val at correct position. */ | |
4779 | if (ac.aligned && MEM_P (cmp)) | |
4780 | { | |
4781 | cmpv = force_reg (SImode, val); | |
4782 | store_bit_field (cmpv, GET_MODE_BITSIZE (mode), 0, SImode, cmp); | |
4783 | } | |
4784 | else | |
4785 | cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val, | |
4786 | NULL_RTX, 1, OPTAB_DIRECT)); | |
0a2aaacc | 4787 | if (ac.aligned && MEM_P (new_rtx)) |
3093f076 AS |
4788 | { |
4789 | newv = force_reg (SImode, val); | |
0a2aaacc | 4790 | store_bit_field (newv, GET_MODE_BITSIZE (mode), 0, SImode, new_rtx); |
3093f076 AS |
4791 | } |
4792 | else | |
0a2aaacc | 4793 | newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val, |
3093f076 AS |
4794 | NULL_RTX, 1, OPTAB_DIRECT)); |
4795 | ||
3093f076 | 4796 | /* Jump to end if we're done (likely?). */ |
8bb501bb AK |
4797 | s390_emit_jump (csend, s390_emit_compare_and_swap (EQ, res, ac.memsi, |
4798 | cmpv, newv)); | |
3093f076 AS |
4799 | |
4800 | /* Check for changes outside mode. */ | |
f4aa3848 | 4801 | resv = expand_simple_binop (SImode, AND, res, ac.modemaski, |
3093f076 | 4802 | NULL_RTX, 1, OPTAB_DIRECT); |
f4aa3848 | 4803 | cc = s390_emit_compare (NE, resv, val); |
3093f076 AS |
4804 | emit_move_insn (val, resv); |
4805 | /* Loop internal if so. */ | |
4806 | s390_emit_jump (csloop, cc); | |
4807 | ||
4808 | emit_label (csend); | |
f4aa3848 | 4809 | |
3093f076 | 4810 | /* Return the correct part of the bitfield. */ |
f4aa3848 | 4811 | convert_move (target, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift, |
3093f076 AS |
4812 | NULL_RTX, 1, OPTAB_DIRECT), 1); |
4813 | } | |
4814 | ||
45d18331 | 4815 | /* Expand an atomic operation CODE of mode MODE. MEM is the memory location |
ea2c620c | 4816 | and VAL the value to play with. If AFTER is true then store the value |
45d18331 AS |
4817 | MEM holds after the operation, if AFTER is false then store the value MEM |
4818 | holds before the operation. If TARGET is zero then discard that value, else | |
4819 | store it to TARGET. */ | |
4820 | ||
4821 | void | |
4822 | s390_expand_atomic (enum machine_mode mode, enum rtx_code code, | |
4823 | rtx target, rtx mem, rtx val, bool after) | |
4824 | { | |
4825 | struct alignment_context ac; | |
4826 | rtx cmp; | |
0a2aaacc | 4827 | rtx new_rtx = gen_reg_rtx (SImode); |
45d18331 AS |
4828 | rtx orig = gen_reg_rtx (SImode); |
4829 | rtx csloop = gen_label_rtx (); | |
4830 | ||
4831 | gcc_assert (!target || register_operand (target, VOIDmode)); | |
4832 | gcc_assert (MEM_P (mem)); | |
4833 | ||
4834 | init_alignment_context (&ac, mem, mode); | |
4835 | ||
4836 | /* Shift val to the correct bit positions. | |
4837 | Preserve "icm", but prevent "ex icm". */ | |
4838 | if (!(ac.aligned && code == SET && MEM_P (val))) | |
4839 | val = s390_expand_mask_and_shift (val, mode, ac.shift); | |
4840 | ||
4841 | /* Further preparation insns. */ | |
4842 | if (code == PLUS || code == MINUS) | |
4843 | emit_move_insn (orig, val); | |
4844 | else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */ | |
4845 | val = expand_simple_binop (SImode, XOR, val, ac.modemaski, | |
4846 | NULL_RTX, 1, OPTAB_DIRECT); | |
4847 | ||
4848 | /* Load full word. Subsequent loads are performed by CS. */ | |
4849 | cmp = force_reg (SImode, ac.memsi); | |
4850 | ||
4851 | /* Start CS loop. */ | |
4852 | emit_label (csloop); | |
0a2aaacc | 4853 | emit_move_insn (new_rtx, cmp); |
45d18331 AS |
4854 | |
4855 | /* Patch new with val at correct position. */ | |
4856 | switch (code) | |
4857 | { | |
4858 | case PLUS: | |
4859 | case MINUS: | |
0a2aaacc | 4860 | val = expand_simple_binop (SImode, code, new_rtx, orig, |
45d18331 AS |
4861 | NULL_RTX, 1, OPTAB_DIRECT); |
4862 | val = expand_simple_binop (SImode, AND, val, ac.modemask, | |
4863 | NULL_RTX, 1, OPTAB_DIRECT); | |
4864 | /* FALLTHRU */ | |
f4aa3848 | 4865 | case SET: |
45d18331 | 4866 | if (ac.aligned && MEM_P (val)) |
0a2aaacc | 4867 | store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0, SImode, val); |
45d18331 AS |
4868 | else |
4869 | { | |
0a2aaacc | 4870 | new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski, |
45d18331 | 4871 | NULL_RTX, 1, OPTAB_DIRECT); |
0a2aaacc | 4872 | new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val, |
45d18331 AS |
4873 | NULL_RTX, 1, OPTAB_DIRECT); |
4874 | } | |
4875 | break; | |
4876 | case AND: | |
4877 | case IOR: | |
4878 | case XOR: | |
0a2aaacc | 4879 | new_rtx = expand_simple_binop (SImode, code, new_rtx, val, |
45d18331 AS |
4880 | NULL_RTX, 1, OPTAB_DIRECT); |
4881 | break; | |
4882 | case MULT: /* NAND */ | |
0a2aaacc | 4883 | new_rtx = expand_simple_binop (SImode, AND, new_rtx, val, |
45d18331 | 4884 | NULL_RTX, 1, OPTAB_DIRECT); |
6a238c58 AK |
4885 | new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask, |
4886 | NULL_RTX, 1, OPTAB_DIRECT); | |
45d18331 AS |
4887 | break; |
4888 | default: | |
4889 | gcc_unreachable (); | |
4890 | } | |
45d18331 | 4891 | |
8bb501bb | 4892 | s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp, |
0a2aaacc | 4893 | ac.memsi, cmp, new_rtx)); |
45d18331 AS |
4894 | |
4895 | /* Return the correct part of the bitfield. */ | |
4896 | if (target) | |
4897 | convert_move (target, expand_simple_binop (SImode, LSHIFTRT, | |
0a2aaacc | 4898 | after ? new_rtx : cmp, ac.shift, |
45d18331 AS |
4899 | NULL_RTX, 1, OPTAB_DIRECT), 1); |
4900 | } | |
4901 | ||
fdbe66f2 | 4902 | /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. |
6b2300b3 JJ |
4903 | We need to emit DTP-relative relocations. */ |
4904 | ||
fdbe66f2 EB |
4905 | static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; |
4906 | ||
4907 | static void | |
9c808aad | 4908 | s390_output_dwarf_dtprel (FILE *file, int size, rtx x) |
6b2300b3 JJ |
4909 | { |
4910 | switch (size) | |
4911 | { | |
4912 | case 4: | |
4913 | fputs ("\t.long\t", file); | |
4914 | break; | |
4915 | case 8: | |
4916 | fputs ("\t.quad\t", file); | |
4917 | break; | |
4918 | default: | |
8d933e31 | 4919 | gcc_unreachable (); |
6b2300b3 JJ |
4920 | } |
4921 | output_addr_const (file, x); | |
4922 | fputs ("@DTPOFF", file); | |
4923 | } | |
4924 | ||
7269aee7 | 4925 | #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING |
608063c3 | 4926 | /* Implement TARGET_MANGLE_TYPE. */ |
7269aee7 AH |
4927 | |
4928 | static const char * | |
3101faab | 4929 | s390_mangle_type (const_tree type) |
7269aee7 AH |
4930 | { |
4931 | if (TYPE_MAIN_VARIANT (type) == long_double_type_node | |
4932 | && TARGET_LONG_DOUBLE_128) | |
4933 | return "g"; | |
4934 | ||
4935 | /* For all other types, use normal C++ mangling. */ | |
4936 | return NULL; | |
4937 | } | |
4938 | #endif | |
4939 | ||
4c8c0dec | 4940 | /* In the name of slightly smaller debug output, and to cater to |
aabcd309 | 4941 | general assembler lossage, recognize various UNSPEC sequences |
4c8c0dec JJ |
4942 | and turn them back into a direct symbol reference. */ |
4943 | ||
69bd9368 | 4944 | static rtx |
9c808aad | 4945 | s390_delegitimize_address (rtx orig_x) |
4c8c0dec | 4946 | { |
e8d8f497 | 4947 | rtx x, y; |
4c8c0dec | 4948 | |
e8d8f497 JJ |
4949 | orig_x = delegitimize_mem_from_attrs (orig_x); |
4950 | x = orig_x; | |
4c8c0dec JJ |
4951 | if (GET_CODE (x) != MEM) |
4952 | return orig_x; | |
4953 | ||
4954 | x = XEXP (x, 0); | |
4955 | if (GET_CODE (x) == PLUS | |
4956 | && GET_CODE (XEXP (x, 1)) == CONST | |
4957 | && GET_CODE (XEXP (x, 0)) == REG | |
4958 | && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM) | |
4959 | { | |
4960 | y = XEXP (XEXP (x, 1), 0); | |
4961 | if (GET_CODE (y) == UNSPEC | |
fd7643fb | 4962 | && XINT (y, 1) == UNSPEC_GOT) |
4c8c0dec JJ |
4963 | return XVECEXP (y, 0, 0); |
4964 | return orig_x; | |
4965 | } | |
4966 | ||
4967 | if (GET_CODE (x) == CONST) | |
4968 | { | |
4969 | y = XEXP (x, 0); | |
4970 | if (GET_CODE (y) == UNSPEC | |
fd7643fb | 4971 | && XINT (y, 1) == UNSPEC_GOTENT) |
4c8c0dec JJ |
4972 | return XVECEXP (y, 0, 0); |
4973 | return orig_x; | |
4974 | } | |
4975 | ||
c7453384 | 4976 | return orig_x; |
4c8c0dec | 4977 | } |
ba956982 | 4978 | |
6d057022 AS |
4979 | /* Output operand OP to stdio stream FILE. |
4980 | OP is an address (register + offset) which is not used to address data; | |
4981 | instead the rightmost bits are interpreted as the value. */ | |
ac32b25e UW |
4982 | |
4983 | static void | |
4984 | print_shift_count_operand (FILE *file, rtx op) | |
4985 | { | |
d98ad410 UW |
4986 | HOST_WIDE_INT offset; |
4987 | rtx base; | |
f83a336d | 4988 | |
d98ad410 | 4989 | /* Extract base register and offset. */ |
4989e88a | 4990 | if (!s390_decompose_shift_count (op, &base, &offset)) |
d98ad410 | 4991 | gcc_unreachable (); |
ac32b25e UW |
4992 | |
4993 | /* Sanity check. */ | |
d98ad410 | 4994 | if (base) |
8d933e31 | 4995 | { |
d98ad410 UW |
4996 | gcc_assert (GET_CODE (base) == REG); |
4997 | gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER); | |
4998 | gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS); | |
8d933e31 | 4999 | } |
ac32b25e | 5000 | |
6d057022 AS |
5001 | /* Offsets are constricted to twelve bits. */ |
5002 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1)); | |
d98ad410 UW |
5003 | if (base) |
5004 | fprintf (file, "(%s)", reg_names[REGNO (base)]); | |
ac32b25e UW |
5005 | } |
5006 | ||
ab96de7e | 5007 | /* See 'get_some_local_dynamic_name'. */ |
fd3cd001 UW |
5008 | |
5009 | static int | |
9c808aad | 5010 | get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) |
fd3cd001 UW |
5011 | { |
5012 | rtx x = *px; | |
5013 | ||
5014 | if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) | |
5015 | { | |
5016 | x = get_pool_constant (x); | |
5017 | return for_each_rtx (&x, get_some_local_dynamic_name_1, 0); | |
5018 | } | |
5019 | ||
5020 | if (GET_CODE (x) == SYMBOL_REF | |
5021 | && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC) | |
5022 | { | |
5023 | cfun->machine->some_ld_name = XSTR (x, 0); | |
5024 | return 1; | |
5025 | } | |
5026 | ||
5027 | return 0; | |
5028 | } | |
5029 | ||
ab96de7e AS |
5030 | /* Locate some local-dynamic symbol still in use by this function |
5031 | so that we can print its name in local-dynamic base patterns. */ | |
5032 | ||
5033 | static const char * | |
5034 | get_some_local_dynamic_name (void) | |
5035 | { | |
5036 | rtx insn; | |
5037 | ||
5038 | if (cfun->machine->some_ld_name) | |
5039 | return cfun->machine->some_ld_name; | |
5040 | ||
5041 | for (insn = get_insns (); insn ; insn = NEXT_INSN (insn)) | |
5042 | if (INSN_P (insn) | |
5043 | && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0)) | |
5044 | return cfun->machine->some_ld_name; | |
5045 | ||
8d933e31 | 5046 | gcc_unreachable (); |
ab96de7e AS |
5047 | } |
5048 | ||
38899e29 | 5049 | /* Output machine-dependent UNSPECs occurring in address constant X |
faeb9bb6 UW |
5050 | in assembler syntax to stdio stream FILE. Returns true if the |
5051 | constant X could be recognized, false otherwise. */ | |
9db1d521 | 5052 | |
faeb9bb6 UW |
5053 | bool |
5054 | s390_output_addr_const_extra (FILE *file, rtx x) | |
9db1d521 | 5055 | { |
faeb9bb6 UW |
5056 | if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1) |
5057 | switch (XINT (x, 1)) | |
5058 | { | |
5059 | case UNSPEC_GOTENT: | |
5060 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5061 | fprintf (file, "@GOTENT"); | |
5062 | return true; | |
5063 | case UNSPEC_GOT: | |
5064 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5065 | fprintf (file, "@GOT"); | |
5066 | return true; | |
5067 | case UNSPEC_GOTOFF: | |
5068 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5069 | fprintf (file, "@GOTOFF"); | |
5070 | return true; | |
5071 | case UNSPEC_PLT: | |
5072 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5073 | fprintf (file, "@PLT"); | |
5074 | return true; | |
5075 | case UNSPEC_PLTOFF: | |
5076 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5077 | fprintf (file, "@PLTOFF"); | |
5078 | return true; | |
5079 | case UNSPEC_TLSGD: | |
5080 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5081 | fprintf (file, "@TLSGD"); | |
5082 | return true; | |
5083 | case UNSPEC_TLSLDM: | |
5084 | assemble_name (file, get_some_local_dynamic_name ()); | |
5085 | fprintf (file, "@TLSLDM"); | |
5086 | return true; | |
5087 | case UNSPEC_DTPOFF: | |
5088 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5089 | fprintf (file, "@DTPOFF"); | |
5090 | return true; | |
5091 | case UNSPEC_NTPOFF: | |
5092 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5093 | fprintf (file, "@NTPOFF"); | |
5094 | return true; | |
5095 | case UNSPEC_GOTNTPOFF: | |
5096 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5097 | fprintf (file, "@GOTNTPOFF"); | |
5098 | return true; | |
5099 | case UNSPEC_INDNTPOFF: | |
5100 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5101 | fprintf (file, "@INDNTPOFF"); | |
5102 | return true; | |
5103 | } | |
9db1d521 | 5104 | |
dc66391d RS |
5105 | if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2) |
5106 | switch (XINT (x, 1)) | |
5107 | { | |
5108 | case UNSPEC_POOL_OFFSET: | |
5109 | x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1)); | |
5110 | output_addr_const (file, x); | |
5111 | return true; | |
5112 | } | |
faeb9bb6 | 5113 | return false; |
9db1d521 HP |
5114 | } |
5115 | ||
c7453384 | 5116 | /* Output address operand ADDR in assembler syntax to |
994fe660 | 5117 | stdio stream FILE. */ |
9db1d521 HP |
5118 | |
5119 | void | |
9c808aad | 5120 | print_operand_address (FILE *file, rtx addr) |
9db1d521 HP |
5121 | { |
5122 | struct s390_address ad; | |
5123 | ||
963fc8d0 AK |
5124 | if (s390_symref_operand_p (addr, NULL, NULL)) |
5125 | { | |
5126 | gcc_assert (TARGET_Z10); | |
5127 | output_addr_const (file, addr); | |
5128 | return; | |
5129 | } | |
5130 | ||
b808c04c | 5131 | if (!s390_decompose_address (addr, &ad) |
93fa8428 AK |
5132 | || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base))) |
5133 | || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))) | |
c85ce869 | 5134 | output_operand_lossage ("cannot decompose address"); |
c7453384 | 5135 | |
9db1d521 | 5136 | if (ad.disp) |
faeb9bb6 | 5137 | output_addr_const (file, ad.disp); |
9db1d521 HP |
5138 | else |
5139 | fprintf (file, "0"); | |
5140 | ||
5141 | if (ad.base && ad.indx) | |
5142 | fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)], | |
5143 | reg_names[REGNO (ad.base)]); | |
5144 | else if (ad.base) | |
5145 | fprintf (file, "(%s)", reg_names[REGNO (ad.base)]); | |
5146 | } | |
5147 | ||
c7453384 EC |
5148 | /* Output operand X in assembler syntax to stdio stream FILE. |
5149 | CODE specified the format flag. The following format flags | |
994fe660 UW |
5150 | are recognized: |
5151 | ||
5152 | 'C': print opcode suffix for branch condition. | |
5153 | 'D': print opcode suffix for inverse branch condition. | |
f1149235 | 5154 | 'E': print opcode suffix for branch on index instruction. |
fd3cd001 | 5155 | 'J': print tls_load/tls_gdcall/tls_ldcall suffix |
7b8acc34 | 5156 | 'G': print the size of the operand in bytes. |
994fe660 UW |
5157 | 'O': print only the displacement of a memory reference. |
5158 | 'R': print only the base register of a memory reference. | |
fc0ea003 | 5159 | 'S': print S-type memory reference (base+displacement). |
994fe660 UW |
5160 | 'N': print the second word of a DImode operand. |
5161 | 'M': print the second word of a TImode operand. | |
ac32b25e | 5162 | 'Y': print shift count operand. |
994fe660 | 5163 | |
5519a4f9 | 5164 | 'b': print integer X as if it's an unsigned byte. |
963fc8d0 | 5165 | 'c': print integer X as if it's an signed byte. |
da48f5ec AK |
5166 | 'x': print integer X as if it's an unsigned halfword. |
5167 | 'h': print integer X as if it's a signed halfword. | |
f19a9af7 | 5168 | 'i': print the first nonzero HImode part of X. |
da48f5ec AK |
5169 | 'j': print the first HImode part unequal to -1 of X. |
5170 | 'k': print the first nonzero SImode part of X. | |
5171 | 'm': print the first SImode part unequal to -1 of X. | |
5172 | 'o': print integer X as if it's an unsigned 32bit word. */ | |
9db1d521 HP |
5173 | |
5174 | void | |
9c808aad | 5175 | print_operand (FILE *file, rtx x, int code) |
9db1d521 HP |
5176 | { |
5177 | switch (code) | |
5178 | { | |
5179 | case 'C': | |
ba956982 | 5180 | fprintf (file, s390_branch_condition_mnemonic (x, FALSE)); |
9db1d521 HP |
5181 | return; |
5182 | ||
5183 | case 'D': | |
ba956982 | 5184 | fprintf (file, s390_branch_condition_mnemonic (x, TRUE)); |
9db1d521 HP |
5185 | return; |
5186 | ||
f1149235 AK |
5187 | case 'E': |
5188 | if (GET_CODE (x) == LE) | |
5189 | fprintf (file, "l"); | |
5190 | else if (GET_CODE (x) == GT) | |
5191 | fprintf (file, "h"); | |
5192 | else | |
5193 | gcc_unreachable (); | |
5194 | return; | |
5195 | ||
fd3cd001 UW |
5196 | case 'J': |
5197 | if (GET_CODE (x) == SYMBOL_REF) | |
5198 | { | |
5199 | fprintf (file, "%s", ":tls_load:"); | |
5200 | output_addr_const (file, x); | |
5201 | } | |
5202 | else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD) | |
5203 | { | |
5204 | fprintf (file, "%s", ":tls_gdcall:"); | |
5205 | output_addr_const (file, XVECEXP (x, 0, 0)); | |
5206 | } | |
5207 | else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM) | |
5208 | { | |
5209 | fprintf (file, "%s", ":tls_ldcall:"); | |
5210 | assemble_name (file, get_some_local_dynamic_name ()); | |
5211 | } | |
5212 | else | |
8d933e31 | 5213 | gcc_unreachable (); |
fd3cd001 UW |
5214 | return; |
5215 | ||
7b8acc34 AK |
5216 | case 'G': |
5217 | fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x))); | |
5218 | return; | |
5219 | ||
9db1d521 HP |
5220 | case 'O': |
5221 | { | |
5222 | struct s390_address ad; | |
8d933e31 | 5223 | int ret; |
9db1d521 | 5224 | |
8d933e31 AS |
5225 | gcc_assert (GET_CODE (x) == MEM); |
5226 | ret = s390_decompose_address (XEXP (x, 0), &ad); | |
5227 | gcc_assert (ret); | |
93fa8428 | 5228 | gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base))); |
8d933e31 | 5229 | gcc_assert (!ad.indx); |
9db1d521 HP |
5230 | |
5231 | if (ad.disp) | |
faeb9bb6 | 5232 | output_addr_const (file, ad.disp); |
9db1d521 HP |
5233 | else |
5234 | fprintf (file, "0"); | |
5235 | } | |
5236 | return; | |
5237 | ||
5238 | case 'R': | |
5239 | { | |
5240 | struct s390_address ad; | |
8d933e31 | 5241 | int ret; |
9db1d521 | 5242 | |
8d933e31 AS |
5243 | gcc_assert (GET_CODE (x) == MEM); |
5244 | ret = s390_decompose_address (XEXP (x, 0), &ad); | |
5245 | gcc_assert (ret); | |
93fa8428 | 5246 | gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base))); |
8d933e31 | 5247 | gcc_assert (!ad.indx); |
9db1d521 HP |
5248 | |
5249 | if (ad.base) | |
5250 | fprintf (file, "%s", reg_names[REGNO (ad.base)]); | |
5251 | else | |
5252 | fprintf (file, "0"); | |
5253 | } | |
5254 | return; | |
5255 | ||
fc0ea003 UW |
5256 | case 'S': |
5257 | { | |
5258 | struct s390_address ad; | |
8d933e31 | 5259 | int ret; |
fc0ea003 | 5260 | |
8d933e31 AS |
5261 | gcc_assert (GET_CODE (x) == MEM); |
5262 | ret = s390_decompose_address (XEXP (x, 0), &ad); | |
5263 | gcc_assert (ret); | |
93fa8428 | 5264 | gcc_assert (!ad.base || REGNO_OK_FOR_BASE_P (REGNO (ad.base))); |
8d933e31 | 5265 | gcc_assert (!ad.indx); |
fc0ea003 UW |
5266 | |
5267 | if (ad.disp) | |
5268 | output_addr_const (file, ad.disp); | |
5269 | else | |
5270 | fprintf (file, "0"); | |
5271 | ||
5272 | if (ad.base) | |
5273 | fprintf (file, "(%s)", reg_names[REGNO (ad.base)]); | |
5274 | } | |
5275 | return; | |
5276 | ||
9db1d521 HP |
5277 | case 'N': |
5278 | if (GET_CODE (x) == REG) | |
5279 | x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1); | |
5280 | else if (GET_CODE (x) == MEM) | |
5281 | x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 4)); | |
5282 | else | |
8d933e31 | 5283 | gcc_unreachable (); |
9db1d521 HP |
5284 | break; |
5285 | ||
5286 | case 'M': | |
5287 | if (GET_CODE (x) == REG) | |
5288 | x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1); | |
5289 | else if (GET_CODE (x) == MEM) | |
5290 | x = change_address (x, VOIDmode, plus_constant (XEXP (x, 0), 8)); | |
5291 | else | |
8d933e31 | 5292 | gcc_unreachable (); |
9db1d521 | 5293 | break; |
ac32b25e UW |
5294 | |
5295 | case 'Y': | |
5296 | print_shift_count_operand (file, x); | |
5297 | return; | |
9db1d521 HP |
5298 | } |
5299 | ||
5300 | switch (GET_CODE (x)) | |
5301 | { | |
5302 | case REG: | |
5303 | fprintf (file, "%s", reg_names[REGNO (x)]); | |
5304 | break; | |
5305 | ||
5306 | case MEM: | |
5307 | output_address (XEXP (x, 0)); | |
5308 | break; | |
5309 | ||
5310 | case CONST: | |
5311 | case CODE_LABEL: | |
5312 | case LABEL_REF: | |
5313 | case SYMBOL_REF: | |
faeb9bb6 | 5314 | output_addr_const (file, x); |
9db1d521 HP |
5315 | break; |
5316 | ||
5317 | case CONST_INT: | |
5318 | if (code == 'b') | |
4023fb28 | 5319 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xff); |
963fc8d0 AK |
5320 | else if (code == 'c') |
5321 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xff) ^ 0x80) - 0x80); | |
4023fb28 UW |
5322 | else if (code == 'x') |
5323 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffff); | |
5324 | else if (code == 'h') | |
5325 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000); | |
f19a9af7 | 5326 | else if (code == 'i') |
38899e29 | 5327 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
f19a9af7 AK |
5328 | s390_extract_part (x, HImode, 0)); |
5329 | else if (code == 'j') | |
38899e29 EC |
5330 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, |
5331 | s390_extract_part (x, HImode, -1)); | |
ec24698e UW |
5332 | else if (code == 'k') |
5333 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, | |
5334 | s390_extract_part (x, SImode, 0)); | |
5335 | else if (code == 'm') | |
5336 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, | |
5337 | s390_extract_part (x, SImode, -1)); | |
5338 | else if (code == 'o') | |
5339 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0xffffffff); | |
4023fb28 UW |
5340 | else |
5341 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); | |
5342 | break; | |
5343 | ||
5344 | case CONST_DOUBLE: | |
8d933e31 | 5345 | gcc_assert (GET_MODE (x) == VOIDmode); |
4023fb28 UW |
5346 | if (code == 'b') |
5347 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff); | |
9db1d521 | 5348 | else if (code == 'x') |
4023fb28 | 5349 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff); |
9db1d521 | 5350 | else if (code == 'h') |
4023fb28 | 5351 | fprintf (file, HOST_WIDE_INT_PRINT_DEC, ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000); |
9db1d521 | 5352 | else |
8d933e31 | 5353 | gcc_unreachable (); |
9db1d521 HP |
5354 | break; |
5355 | ||
5356 | default: | |
5357 | fatal_insn ("UNKNOWN in print_operand !?", x); | |
5358 | break; | |
5359 | } | |
5360 | } | |
5361 | ||
301d03af RS |
5362 | /* Target hook for assembling integer objects. We need to define it |
5363 | here to work a round a bug in some versions of GAS, which couldn't | |
5364 | handle values smaller than INT_MIN when printed in decimal. */ | |
5365 | ||
5366 | static bool | |
9c808aad | 5367 | s390_assemble_integer (rtx x, unsigned int size, int aligned_p) |
301d03af RS |
5368 | { |
5369 | if (size == 8 && aligned_p | |
5370 | && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN) | |
5371 | { | |
4a0a75dd KG |
5372 | fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n", |
5373 | INTVAL (x)); | |
301d03af RS |
5374 | return true; |
5375 | } | |
5376 | return default_assemble_integer (x, size, aligned_p); | |
5377 | } | |
5378 | ||
c7453384 | 5379 | /* Returns true if register REGNO is used for forming |
994fe660 | 5380 | a memory address in expression X. */ |
9db1d521 | 5381 | |
3ed99cc9 | 5382 | static bool |
9c808aad | 5383 | reg_used_in_mem_p (int regno, rtx x) |
9db1d521 HP |
5384 | { |
5385 | enum rtx_code code = GET_CODE (x); | |
5386 | int i, j; | |
5387 | const char *fmt; | |
c7453384 | 5388 | |
9db1d521 HP |
5389 | if (code == MEM) |
5390 | { | |
5391 | if (refers_to_regno_p (regno, regno+1, | |
5392 | XEXP (x, 0), 0)) | |
3ed99cc9 | 5393 | return true; |
9db1d521 | 5394 | } |
c7453384 | 5395 | else if (code == SET |
4023fb28 UW |
5396 | && GET_CODE (SET_DEST (x)) == PC) |
5397 | { | |
5398 | if (refers_to_regno_p (regno, regno+1, | |
5399 | SET_SRC (x), 0)) | |
3ed99cc9 | 5400 | return true; |
4023fb28 | 5401 | } |
9db1d521 HP |
5402 | |
5403 | fmt = GET_RTX_FORMAT (code); | |
5404 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
5405 | { | |
5406 | if (fmt[i] == 'e' | |
5407 | && reg_used_in_mem_p (regno, XEXP (x, i))) | |
3ed99cc9 | 5408 | return true; |
c7453384 | 5409 | |
9db1d521 HP |
5410 | else if (fmt[i] == 'E') |
5411 | for (j = 0; j < XVECLEN (x, i); j++) | |
5412 | if (reg_used_in_mem_p (regno, XVECEXP (x, i, j))) | |
3ed99cc9 | 5413 | return true; |
9db1d521 | 5414 | } |
3ed99cc9 | 5415 | return false; |
9db1d521 HP |
5416 | } |
5417 | ||
d65f7478 | 5418 | /* Returns true if expression DEP_RTX sets an address register |
994fe660 | 5419 | used by instruction INSN to address memory. */ |
9db1d521 | 5420 | |
3ed99cc9 | 5421 | static bool |
9c808aad | 5422 | addr_generation_dependency_p (rtx dep_rtx, rtx insn) |
9db1d521 | 5423 | { |
4023fb28 | 5424 | rtx target, pat; |
9db1d521 | 5425 | |
077dab3b HP |
5426 | if (GET_CODE (dep_rtx) == INSN) |
5427 | dep_rtx = PATTERN (dep_rtx); | |
5428 | ||
9db1d521 HP |
5429 | if (GET_CODE (dep_rtx) == SET) |
5430 | { | |
5431 | target = SET_DEST (dep_rtx); | |
cc7ab9b7 UW |
5432 | if (GET_CODE (target) == STRICT_LOW_PART) |
5433 | target = XEXP (target, 0); | |
5434 | while (GET_CODE (target) == SUBREG) | |
5435 | target = SUBREG_REG (target); | |
5436 | ||
9db1d521 HP |
5437 | if (GET_CODE (target) == REG) |
5438 | { | |
5439 | int regno = REGNO (target); | |
5440 | ||
077dab3b | 5441 | if (s390_safe_attr_type (insn) == TYPE_LA) |
4023fb28 UW |
5442 | { |
5443 | pat = PATTERN (insn); | |
5444 | if (GET_CODE (pat) == PARALLEL) | |
5445 | { | |
8d933e31 | 5446 | gcc_assert (XVECLEN (pat, 0) == 2); |
4023fb28 UW |
5447 | pat = XVECEXP (pat, 0, 0); |
5448 | } | |
8d933e31 AS |
5449 | gcc_assert (GET_CODE (pat) == SET); |
5450 | return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0); | |
4023fb28 | 5451 | } |
077dab3b | 5452 | else if (get_attr_atype (insn) == ATYPE_AGEN) |
4023fb28 UW |
5453 | return reg_used_in_mem_p (regno, PATTERN (insn)); |
5454 | } | |
9db1d521 | 5455 | } |
3ed99cc9 | 5456 | return false; |
9db1d521 HP |
5457 | } |
5458 | ||
077dab3b HP |
5459 | /* Return 1, if dep_insn sets register used in insn in the agen unit. */ |
5460 | ||
c7453384 | 5461 | int |
9c808aad | 5462 | s390_agen_dep_p (rtx dep_insn, rtx insn) |
c7453384 | 5463 | { |
077dab3b HP |
5464 | rtx dep_rtx = PATTERN (dep_insn); |
5465 | int i; | |
c7453384 EC |
5466 | |
5467 | if (GET_CODE (dep_rtx) == SET | |
077dab3b HP |
5468 | && addr_generation_dependency_p (dep_rtx, insn)) |
5469 | return 1; | |
5470 | else if (GET_CODE (dep_rtx) == PARALLEL) | |
5471 | { | |
5472 | for (i = 0; i < XVECLEN (dep_rtx, 0); i++) | |
5473 | { | |
5474 | if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn)) | |
5475 | return 1; | |
5476 | } | |
5477 | } | |
5478 | return 0; | |
5479 | } | |
5480 | ||
9381e3f1 | 5481 | |
52609473 HP |
5482 | /* A C statement (sans semicolon) to update the integer scheduling priority |
5483 | INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier, | |
5484 | reduce the priority to execute INSN later. Do not define this macro if | |
c7453384 | 5485 | you do not need to adjust the scheduling priorities of insns. |
52609473 | 5486 | |
c7453384 | 5487 | A STD instruction should be scheduled earlier, |
52609473 | 5488 | in order to use the bypass. */ |
52609473 | 5489 | static int |
9c808aad | 5490 | s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority) |
52609473 HP |
5491 | { |
5492 | if (! INSN_P (insn)) | |
5493 | return priority; | |
5494 | ||
ec24698e | 5495 | if (s390_tune != PROCESSOR_2084_Z990 |
2cdece44 | 5496 | && s390_tune != PROCESSOR_2094_Z9_109 |
65b1d8ea AK |
5497 | && s390_tune != PROCESSOR_2097_Z10 |
5498 | && s390_tune != PROCESSOR_2817_Z196) | |
52609473 HP |
5499 | return priority; |
5500 | ||
5501 | switch (s390_safe_attr_type (insn)) | |
5502 | { | |
cfdb984b AS |
5503 | case TYPE_FSTOREDF: |
5504 | case TYPE_FSTORESF: | |
52609473 HP |
5505 | priority = priority << 3; |
5506 | break; | |
5507 | case TYPE_STORE: | |
ea77e738 | 5508 | case TYPE_STM: |
52609473 HP |
5509 | priority = priority << 1; |
5510 | break; | |
5511 | default: | |
5512 | break; | |
5513 | } | |
5514 | return priority; | |
5515 | } | |
f2d3c02a | 5516 | |
2cdece44 | 5517 | |
077dab3b | 5518 | /* The number of instructions that can be issued per cycle. */ |
f2d3c02a | 5519 | |
077dab3b | 5520 | static int |
9c808aad | 5521 | s390_issue_rate (void) |
077dab3b | 5522 | { |
93538e8e AK |
5523 | switch (s390_tune) |
5524 | { | |
5525 | case PROCESSOR_2084_Z990: | |
5526 | case PROCESSOR_2094_Z9_109: | |
65b1d8ea | 5527 | case PROCESSOR_2817_Z196: |
93538e8e AK |
5528 | return 3; |
5529 | case PROCESSOR_2097_Z10: | |
5530 | return 2; | |
5531 | default: | |
5532 | return 1; | |
5533 | } | |
077dab3b | 5534 | } |
f2d3c02a | 5535 | |
52609473 | 5536 | static int |
9c808aad | 5537 | s390_first_cycle_multipass_dfa_lookahead (void) |
52609473 | 5538 | { |
64e1e4c4 | 5539 | return 4; |
52609473 HP |
5540 | } |
5541 | ||
585539a1 UW |
5542 | /* Annotate every literal pool reference in X by an UNSPEC_LTREF expression. |
5543 | Fix up MEMs as required. */ | |
5544 | ||
5545 | static void | |
5546 | annotate_constant_pool_refs (rtx *x) | |
5547 | { | |
5548 | int i, j; | |
5549 | const char *fmt; | |
5550 | ||
8d933e31 AS |
5551 | gcc_assert (GET_CODE (*x) != SYMBOL_REF |
5552 | || !CONSTANT_POOL_ADDRESS_P (*x)); | |
585539a1 UW |
5553 | |
5554 | /* Literal pool references can only occur inside a MEM ... */ | |
5555 | if (GET_CODE (*x) == MEM) | |
5556 | { | |
5557 | rtx memref = XEXP (*x, 0); | |
5558 | ||
5559 | if (GET_CODE (memref) == SYMBOL_REF | |
5560 | && CONSTANT_POOL_ADDRESS_P (memref)) | |
5561 | { | |
5562 | rtx base = cfun->machine->base_reg; | |
5563 | rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base), | |
5564 | UNSPEC_LTREF); | |
5565 | ||
5566 | *x = replace_equiv_address (*x, addr); | |
5567 | return; | |
5568 | } | |
5569 | ||
5570 | if (GET_CODE (memref) == CONST | |
5571 | && GET_CODE (XEXP (memref, 0)) == PLUS | |
5572 | && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT | |
5573 | && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF | |
5574 | && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0))) | |
5575 | { | |
5576 | HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1)); | |
5577 | rtx sym = XEXP (XEXP (memref, 0), 0); | |
5578 | rtx base = cfun->machine->base_reg; | |
5579 | rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base), | |
5580 | UNSPEC_LTREF); | |
5581 | ||
5582 | *x = replace_equiv_address (*x, plus_constant (addr, off)); | |
5583 | return; | |
5584 | } | |
5585 | } | |
5586 | ||
5587 | /* ... or a load-address type pattern. */ | |
5588 | if (GET_CODE (*x) == SET) | |
5589 | { | |
5590 | rtx addrref = SET_SRC (*x); | |
5591 | ||
5592 | if (GET_CODE (addrref) == SYMBOL_REF | |
5593 | && CONSTANT_POOL_ADDRESS_P (addrref)) | |
5594 | { | |
5595 | rtx base = cfun->machine->base_reg; | |
5596 | rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base), | |
5597 | UNSPEC_LTREF); | |
5598 | ||
5599 | SET_SRC (*x) = addr; | |
5600 | return; | |
5601 | } | |
5602 | ||
5603 | if (GET_CODE (addrref) == CONST | |
5604 | && GET_CODE (XEXP (addrref, 0)) == PLUS | |
5605 | && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT | |
5606 | && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF | |
5607 | && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0))) | |
5608 | { | |
5609 | HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1)); | |
5610 | rtx sym = XEXP (XEXP (addrref, 0), 0); | |
5611 | rtx base = cfun->machine->base_reg; | |
5612 | rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base), | |
5613 | UNSPEC_LTREF); | |
5614 | ||
5615 | SET_SRC (*x) = plus_constant (addr, off); | |
5616 | return; | |
5617 | } | |
5618 | } | |
5619 | ||
5620 | /* Annotate LTREL_BASE as well. */ | |
5621 | if (GET_CODE (*x) == UNSPEC | |
5622 | && XINT (*x, 1) == UNSPEC_LTREL_BASE) | |
5623 | { | |
5624 | rtx base = cfun->machine->base_reg; | |
5625 | *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base), | |
5626 | UNSPEC_LTREL_BASE); | |
5627 | return; | |
5628 | } | |
5629 | ||
5630 | fmt = GET_RTX_FORMAT (GET_CODE (*x)); | |
5631 | for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--) | |
5632 | { | |
5633 | if (fmt[i] == 'e') | |
5634 | { | |
5635 | annotate_constant_pool_refs (&XEXP (*x, i)); | |
5636 | } | |
5637 | else if (fmt[i] == 'E') | |
5638 | { | |
5639 | for (j = 0; j < XVECLEN (*x, i); j++) | |
5640 | annotate_constant_pool_refs (&XVECEXP (*x, i, j)); | |
5641 | } | |
5642 | } | |
5643 | } | |
5644 | ||
ab96de7e AS |
5645 | /* Split all branches that exceed the maximum distance. |
5646 | Returns true if this created a new literal pool entry. */ | |
5647 | ||
5648 | static int | |
5649 | s390_split_branches (void) | |
5650 | { | |
5651 | rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM); | |
8d933e31 | 5652 | int new_literal = 0, ret; |
ab96de7e AS |
5653 | rtx insn, pat, tmp, target; |
5654 | rtx *label; | |
5655 | ||
5656 | /* We need correct insn addresses. */ | |
5657 | ||
5658 | shorten_branches (get_insns ()); | |
5659 | ||
5660 | /* Find all branches that exceed 64KB, and split them. */ | |
5661 | ||
5662 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
5663 | { | |
5664 | if (GET_CODE (insn) != JUMP_INSN) | |
5665 | continue; | |
5666 | ||
5667 | pat = PATTERN (insn); | |
5668 | if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2) | |
5669 | pat = XVECEXP (pat, 0, 0); | |
5670 | if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx) | |
5671 | continue; | |
5672 | ||
5673 | if (GET_CODE (SET_SRC (pat)) == LABEL_REF) | |
5674 | { | |
5675 | label = &SET_SRC (pat); | |
5676 | } | |
5677 | else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE) | |
5678 | { | |
5679 | if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF) | |
5680 | label = &XEXP (SET_SRC (pat), 1); | |
5681 | else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF) | |
5682 | label = &XEXP (SET_SRC (pat), 2); | |
5683 | else | |
5684 | continue; | |
5685 | } | |
5686 | else | |
5687 | continue; | |
5688 | ||
5689 | if (get_attr_length (insn) <= 4) | |
5690 | continue; | |
5691 | ||
e2df5c1d UW |
5692 | /* We are going to use the return register as scratch register, |
5693 | make sure it will be saved/restored by the prologue/epilogue. */ | |
5694 | cfun_frame_layout.save_return_addr_p = 1; | |
5695 | ||
ab96de7e AS |
5696 | if (!flag_pic) |
5697 | { | |
5698 | new_literal = 1; | |
5699 | tmp = force_const_mem (Pmode, *label); | |
5700 | tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn); | |
5701 | INSN_ADDRESSES_NEW (tmp, -1); | |
5702 | annotate_constant_pool_refs (&PATTERN (tmp)); | |
5703 | ||
5704 | target = temp_reg; | |
5705 | } | |
5706 | else | |
5707 | { | |
5708 | new_literal = 1; | |
5709 | target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label), | |
5710 | UNSPEC_LTREL_OFFSET); | |
5711 | target = gen_rtx_CONST (Pmode, target); | |
5712 | target = force_const_mem (Pmode, target); | |
5713 | tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn); | |
5714 | INSN_ADDRESSES_NEW (tmp, -1); | |
5715 | annotate_constant_pool_refs (&PATTERN (tmp)); | |
5716 | ||
5717 | target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0), | |
5718 | cfun->machine->base_reg), | |
5719 | UNSPEC_LTREL_BASE); | |
5720 | target = gen_rtx_PLUS (Pmode, temp_reg, target); | |
5721 | } | |
5722 | ||
8d933e31 AS |
5723 | ret = validate_change (insn, label, target, 0); |
5724 | gcc_assert (ret); | |
ab96de7e AS |
5725 | } |
5726 | ||
5727 | return new_literal; | |
5728 | } | |
5729 | ||
b2ccb744 | 5730 | |
f4aa3848 AK |
5731 | /* Find an annotated literal pool symbol referenced in RTX X, |
5732 | and store it at REF. Will abort if X contains references to | |
585539a1 UW |
5733 | more than one such pool symbol; multiple references to the same |
5734 | symbol are allowed, however. | |
b2ccb744 | 5735 | |
c7453384 | 5736 | The rtx pointed to by REF must be initialized to NULL_RTX |
b2ccb744 UW |
5737 | by the caller before calling this routine. */ |
5738 | ||
5739 | static void | |
9c808aad | 5740 | find_constant_pool_ref (rtx x, rtx *ref) |
b2ccb744 UW |
5741 | { |
5742 | int i, j; | |
5743 | const char *fmt; | |
5744 | ||
fd7643fb UW |
5745 | /* Ignore LTREL_BASE references. */ |
5746 | if (GET_CODE (x) == UNSPEC | |
5747 | && XINT (x, 1) == UNSPEC_LTREL_BASE) | |
5748 | return; | |
5af2f3d3 UW |
5749 | /* Likewise POOL_ENTRY insns. */ |
5750 | if (GET_CODE (x) == UNSPEC_VOLATILE | |
5751 | && XINT (x, 1) == UNSPECV_POOL_ENTRY) | |
5752 | return; | |
fd7643fb | 5753 | |
8d933e31 AS |
5754 | gcc_assert (GET_CODE (x) != SYMBOL_REF |
5755 | || !CONSTANT_POOL_ADDRESS_P (x)); | |
585539a1 UW |
5756 | |
5757 | if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF) | |
b2ccb744 | 5758 | { |
585539a1 | 5759 | rtx sym = XVECEXP (x, 0, 0); |
8d933e31 AS |
5760 | gcc_assert (GET_CODE (sym) == SYMBOL_REF |
5761 | && CONSTANT_POOL_ADDRESS_P (sym)); | |
585539a1 | 5762 | |
b2ccb744 | 5763 | if (*ref == NULL_RTX) |
585539a1 | 5764 | *ref = sym; |
f4aa3848 | 5765 | else |
8d933e31 | 5766 | gcc_assert (*ref == sym); |
585539a1 UW |
5767 | |
5768 | return; | |
b2ccb744 UW |
5769 | } |
5770 | ||
5771 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
5772 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
5773 | { | |
5774 | if (fmt[i] == 'e') | |
5775 | { | |
5776 | find_constant_pool_ref (XEXP (x, i), ref); | |
5777 | } | |
5778 | else if (fmt[i] == 'E') | |
5779 | { | |
5780 | for (j = 0; j < XVECLEN (x, i); j++) | |
5781 | find_constant_pool_ref (XVECEXP (x, i, j), ref); | |
5782 | } | |
5783 | } | |
5784 | } | |
5785 | ||
f4aa3848 | 5786 | /* Replace every reference to the annotated literal pool |
585539a1 | 5787 | symbol REF in X by its base plus OFFSET. */ |
b2ccb744 UW |
5788 | |
5789 | static void | |
585539a1 | 5790 | replace_constant_pool_ref (rtx *x, rtx ref, rtx offset) |
b2ccb744 UW |
5791 | { |
5792 | int i, j; | |
5793 | const char *fmt; | |
5794 | ||
8d933e31 | 5795 | gcc_assert (*x != ref); |
b2ccb744 | 5796 | |
585539a1 UW |
5797 | if (GET_CODE (*x) == UNSPEC |
5798 | && XINT (*x, 1) == UNSPEC_LTREF | |
5799 | && XVECEXP (*x, 0, 0) == ref) | |
b2ccb744 | 5800 | { |
585539a1 UW |
5801 | *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset); |
5802 | return; | |
b2ccb744 UW |
5803 | } |
5804 | ||
585539a1 UW |
5805 | if (GET_CODE (*x) == PLUS |
5806 | && GET_CODE (XEXP (*x, 1)) == CONST_INT | |
5807 | && GET_CODE (XEXP (*x, 0)) == UNSPEC | |
5808 | && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF | |
5809 | && XVECEXP (XEXP (*x, 0), 0, 0) == ref) | |
b2ccb744 | 5810 | { |
585539a1 UW |
5811 | rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset); |
5812 | *x = plus_constant (addr, INTVAL (XEXP (*x, 1))); | |
5813 | return; | |
b2ccb744 UW |
5814 | } |
5815 | ||
5816 | fmt = GET_RTX_FORMAT (GET_CODE (*x)); | |
5817 | for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--) | |
5818 | { | |
5819 | if (fmt[i] == 'e') | |
5820 | { | |
585539a1 | 5821 | replace_constant_pool_ref (&XEXP (*x, i), ref, offset); |
b2ccb744 UW |
5822 | } |
5823 | else if (fmt[i] == 'E') | |
5824 | { | |
5825 | for (j = 0; j < XVECLEN (*x, i); j++) | |
585539a1 | 5826 | replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset); |
b2ccb744 UW |
5827 | } |
5828 | } | |
5829 | } | |
5830 | ||
c7453384 | 5831 | /* Check whether X contains an UNSPEC_LTREL_BASE. |
fd7643fb | 5832 | Return its constant pool symbol if found, NULL_RTX otherwise. */ |
aee4e0db | 5833 | |
fd7643fb | 5834 | static rtx |
9c808aad | 5835 | find_ltrel_base (rtx x) |
aee4e0db | 5836 | { |
aee4e0db UW |
5837 | int i, j; |
5838 | const char *fmt; | |
5839 | ||
fd7643fb UW |
5840 | if (GET_CODE (x) == UNSPEC |
5841 | && XINT (x, 1) == UNSPEC_LTREL_BASE) | |
5842 | return XVECEXP (x, 0, 0); | |
aee4e0db UW |
5843 | |
5844 | fmt = GET_RTX_FORMAT (GET_CODE (x)); | |
5845 | for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) | |
5846 | { | |
5847 | if (fmt[i] == 'e') | |
5848 | { | |
fd7643fb UW |
5849 | rtx fnd = find_ltrel_base (XEXP (x, i)); |
5850 | if (fnd) | |
5851 | return fnd; | |
aee4e0db UW |
5852 | } |
5853 | else if (fmt[i] == 'E') | |
5854 | { | |
5855 | for (j = 0; j < XVECLEN (x, i); j++) | |
fd7643fb UW |
5856 | { |
5857 | rtx fnd = find_ltrel_base (XVECEXP (x, i, j)); | |
5858 | if (fnd) | |
5859 | return fnd; | |
5860 | } | |
aee4e0db UW |
5861 | } |
5862 | } | |
5863 | ||
fd7643fb | 5864 | return NULL_RTX; |
aee4e0db UW |
5865 | } |
5866 | ||
585539a1 | 5867 | /* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */ |
aee4e0db UW |
5868 | |
5869 | static void | |
585539a1 | 5870 | replace_ltrel_base (rtx *x) |
aee4e0db | 5871 | { |
fd7643fb | 5872 | int i, j; |
aee4e0db UW |
5873 | const char *fmt; |
5874 | ||
fd7643fb UW |
5875 | if (GET_CODE (*x) == UNSPEC |
5876 | && XINT (*x, 1) == UNSPEC_LTREL_BASE) | |
aee4e0db | 5877 | { |
585539a1 | 5878 | *x = XVECEXP (*x, 0, 1); |
fd7643fb | 5879 | return; |
aee4e0db UW |
5880 | } |
5881 | ||
5882 | fmt = GET_RTX_FORMAT (GET_CODE (*x)); | |
5883 | for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--) | |
5884 | { | |
5885 | if (fmt[i] == 'e') | |
5886 | { | |
585539a1 | 5887 | replace_ltrel_base (&XEXP (*x, i)); |
aee4e0db UW |
5888 | } |
5889 | else if (fmt[i] == 'E') | |
5890 | { | |
5891 | for (j = 0; j < XVECLEN (*x, i); j++) | |
585539a1 | 5892 | replace_ltrel_base (&XVECEXP (*x, i, j)); |
aee4e0db UW |
5893 | } |
5894 | } | |
5895 | } | |
5896 | ||
5897 | ||
fd7643fb | 5898 | /* We keep a list of constants which we have to add to internal |
b2ccb744 UW |
5899 | constant tables in the middle of large functions. */ |
5900 | ||
4dc19cc0 | 5901 | #define NR_C_MODES 11 |
c7453384 | 5902 | enum machine_mode constant_modes[NR_C_MODES] = |
b2ccb744 | 5903 | { |
4dc19cc0 AK |
5904 | TFmode, TImode, TDmode, |
5905 | DFmode, DImode, DDmode, | |
5906 | SFmode, SImode, SDmode, | |
b2ccb744 UW |
5907 | HImode, |
5908 | QImode | |
5909 | }; | |
5910 | ||
b2ccb744 UW |
5911 | struct constant |
5912 | { | |
5913 | struct constant *next; | |
5914 | rtx value; | |
5915 | rtx label; | |
5916 | }; | |
5917 | ||
5918 | struct constant_pool | |
5919 | { | |
5920 | struct constant_pool *next; | |
5921 | rtx first_insn; | |
aee4e0db UW |
5922 | rtx pool_insn; |
5923 | bitmap insns; | |
03870a04 | 5924 | rtx emit_pool_after; |
b2ccb744 UW |
5925 | |
5926 | struct constant *constants[NR_C_MODES]; | |
9bb86f41 | 5927 | struct constant *execute; |
b2ccb744 UW |
5928 | rtx label; |
5929 | int size; | |
5930 | }; | |
5931 | ||
ab96de7e AS |
5932 | /* Allocate new constant_pool structure. */ |
5933 | ||
5934 | static struct constant_pool * | |
5935 | s390_alloc_pool (void) | |
5936 | { | |
5937 | struct constant_pool *pool; | |
5938 | int i; | |
5939 | ||
5940 | pool = (struct constant_pool *) xmalloc (sizeof *pool); | |
5941 | pool->next = NULL; | |
5942 | for (i = 0; i < NR_C_MODES; i++) | |
5943 | pool->constants[i] = NULL; | |
5944 | ||
5945 | pool->execute = NULL; | |
5946 | pool->label = gen_label_rtx (); | |
5947 | pool->first_insn = NULL_RTX; | |
5948 | pool->pool_insn = NULL_RTX; | |
5949 | pool->insns = BITMAP_ALLOC (NULL); | |
5950 | pool->size = 0; | |
03870a04 | 5951 | pool->emit_pool_after = NULL_RTX; |
ab96de7e AS |
5952 | |
5953 | return pool; | |
5954 | } | |
b2ccb744 UW |
5955 | |
5956 | /* Create new constant pool covering instructions starting at INSN | |
5957 | and chain it to the end of POOL_LIST. */ | |
5958 | ||
5959 | static struct constant_pool * | |
9c808aad | 5960 | s390_start_pool (struct constant_pool **pool_list, rtx insn) |
b2ccb744 UW |
5961 | { |
5962 | struct constant_pool *pool, **prev; | |
b2ccb744 | 5963 | |
5af2f3d3 | 5964 | pool = s390_alloc_pool (); |
b2ccb744 | 5965 | pool->first_insn = insn; |
aee4e0db | 5966 | |
b2ccb744 UW |
5967 | for (prev = pool_list; *prev; prev = &(*prev)->next) |
5968 | ; | |
5969 | *prev = pool; | |
5970 | ||
5971 | return pool; | |
5972 | } | |
5973 | ||
aee4e0db UW |
5974 | /* End range of instructions covered by POOL at INSN and emit |
5975 | placeholder insn representing the pool. */ | |
b2ccb744 UW |
5976 | |
5977 | static void | |
9c808aad | 5978 | s390_end_pool (struct constant_pool *pool, rtx insn) |
b2ccb744 | 5979 | { |
aee4e0db UW |
5980 | rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */); |
5981 | ||
5982 | if (!insn) | |
5983 | insn = get_last_insn (); | |
5984 | ||
5985 | pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn); | |
5986 | INSN_ADDRESSES_NEW (pool->pool_insn, -1); | |
5987 | } | |
5988 | ||
5989 | /* Add INSN to the list of insns covered by POOL. */ | |
5990 | ||
5991 | static void | |
9c808aad | 5992 | s390_add_pool_insn (struct constant_pool *pool, rtx insn) |
aee4e0db UW |
5993 | { |
5994 | bitmap_set_bit (pool->insns, INSN_UID (insn)); | |
b2ccb744 UW |
5995 | } |
5996 | ||
5997 | /* Return pool out of POOL_LIST that covers INSN. */ | |
5998 | ||
5999 | static struct constant_pool * | |
9c808aad | 6000 | s390_find_pool (struct constant_pool *pool_list, rtx insn) |
b2ccb744 | 6001 | { |
b2ccb744 UW |
6002 | struct constant_pool *pool; |
6003 | ||
b2ccb744 | 6004 | for (pool = pool_list; pool; pool = pool->next) |
aee4e0db | 6005 | if (bitmap_bit_p (pool->insns, INSN_UID (insn))) |
b2ccb744 UW |
6006 | break; |
6007 | ||
6008 | return pool; | |
6009 | } | |
6010 | ||
aee4e0db | 6011 | /* Add constant VAL of mode MODE to the constant pool POOL. */ |
b2ccb744 | 6012 | |
aee4e0db | 6013 | static void |
9c808aad | 6014 | s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode) |
b2ccb744 UW |
6015 | { |
6016 | struct constant *c; | |
b2ccb744 UW |
6017 | int i; |
6018 | ||
6019 | for (i = 0; i < NR_C_MODES; i++) | |
6020 | if (constant_modes[i] == mode) | |
6021 | break; | |
8d933e31 | 6022 | gcc_assert (i != NR_C_MODES); |
b2ccb744 UW |
6023 | |
6024 | for (c = pool->constants[i]; c != NULL; c = c->next) | |
6025 | if (rtx_equal_p (val, c->value)) | |
6026 | break; | |
6027 | ||
6028 | if (c == NULL) | |
6029 | { | |
6030 | c = (struct constant *) xmalloc (sizeof *c); | |
6031 | c->value = val; | |
6032 | c->label = gen_label_rtx (); | |
6033 | c->next = pool->constants[i]; | |
6034 | pool->constants[i] = c; | |
6035 | pool->size += GET_MODE_SIZE (mode); | |
6036 | } | |
aee4e0db | 6037 | } |
b2ccb744 | 6038 | |
dc66391d RS |
6039 | /* Return an rtx that represents the offset of X from the start of |
6040 | pool POOL. */ | |
6041 | ||
6042 | static rtx | |
6043 | s390_pool_offset (struct constant_pool *pool, rtx x) | |
6044 | { | |
6045 | rtx label; | |
6046 | ||
6047 | label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label); | |
6048 | x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label), | |
6049 | UNSPEC_POOL_OFFSET); | |
6050 | return gen_rtx_CONST (GET_MODE (x), x); | |
6051 | } | |
6052 | ||
aee4e0db UW |
6053 | /* Find constant VAL of mode MODE in the constant pool POOL. |
6054 | Return an RTX describing the distance from the start of | |
6055 | the pool to the location of the new constant. */ | |
c7453384 | 6056 | |
aee4e0db | 6057 | static rtx |
9c808aad AJ |
6058 | s390_find_constant (struct constant_pool *pool, rtx val, |
6059 | enum machine_mode mode) | |
aee4e0db UW |
6060 | { |
6061 | struct constant *c; | |
aee4e0db | 6062 | int i; |
c7453384 | 6063 | |
aee4e0db UW |
6064 | for (i = 0; i < NR_C_MODES; i++) |
6065 | if (constant_modes[i] == mode) | |
6066 | break; | |
8d933e31 | 6067 | gcc_assert (i != NR_C_MODES); |
c7453384 | 6068 | |
aee4e0db UW |
6069 | for (c = pool->constants[i]; c != NULL; c = c->next) |
6070 | if (rtx_equal_p (val, c->value)) | |
6071 | break; | |
c7453384 | 6072 | |
8d933e31 | 6073 | gcc_assert (c); |
c7453384 | 6074 | |
dc66391d | 6075 | return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label)); |
b2ccb744 UW |
6076 | } |
6077 | ||
ab96de7e AS |
6078 | /* Check whether INSN is an execute. Return the label_ref to its |
6079 | execute target template if so, NULL_RTX otherwise. */ | |
6080 | ||
6081 | static rtx | |
6082 | s390_execute_label (rtx insn) | |
6083 | { | |
6084 | if (GET_CODE (insn) == INSN | |
6085 | && GET_CODE (PATTERN (insn)) == PARALLEL | |
6086 | && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC | |
6087 | && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE) | |
6088 | return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2); | |
6089 | ||
6090 | return NULL_RTX; | |
6091 | } | |
6092 | ||
9bb86f41 UW |
6093 | /* Add execute target for INSN to the constant pool POOL. */ |
6094 | ||
6095 | static void | |
6096 | s390_add_execute (struct constant_pool *pool, rtx insn) | |
6097 | { | |
6098 | struct constant *c; | |
6099 | ||
6100 | for (c = pool->execute; c != NULL; c = c->next) | |
6101 | if (INSN_UID (insn) == INSN_UID (c->value)) | |
6102 | break; | |
6103 | ||
6104 | if (c == NULL) | |
6105 | { | |
9bb86f41 UW |
6106 | c = (struct constant *) xmalloc (sizeof *c); |
6107 | c->value = insn; | |
d24959df | 6108 | c->label = gen_label_rtx (); |
9bb86f41 UW |
6109 | c->next = pool->execute; |
6110 | pool->execute = c; | |
d24959df | 6111 | pool->size += 6; |
9bb86f41 UW |
6112 | } |
6113 | } | |
6114 | ||
6115 | /* Find execute target for INSN in the constant pool POOL. | |
6116 | Return an RTX describing the distance from the start of | |
6117 | the pool to the location of the execute target. */ | |
6118 | ||
6119 | static rtx | |
6120 | s390_find_execute (struct constant_pool *pool, rtx insn) | |
6121 | { | |
6122 | struct constant *c; | |
9bb86f41 UW |
6123 | |
6124 | for (c = pool->execute; c != NULL; c = c->next) | |
6125 | if (INSN_UID (insn) == INSN_UID (c->value)) | |
6126 | break; | |
6127 | ||
8d933e31 | 6128 | gcc_assert (c); |
9bb86f41 | 6129 | |
dc66391d | 6130 | return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label)); |
9bb86f41 UW |
6131 | } |
6132 | ||
ab96de7e | 6133 | /* For an execute INSN, extract the execute target template. */ |
9bb86f41 UW |
6134 | |
6135 | static rtx | |
ab96de7e | 6136 | s390_execute_target (rtx insn) |
9bb86f41 | 6137 | { |
ab96de7e AS |
6138 | rtx pattern = PATTERN (insn); |
6139 | gcc_assert (s390_execute_label (insn)); | |
9bb86f41 UW |
6140 | |
6141 | if (XVECLEN (pattern, 0) == 2) | |
6142 | { | |
6143 | pattern = copy_rtx (XVECEXP (pattern, 0, 1)); | |
6144 | } | |
6145 | else | |
6146 | { | |
6147 | rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1); | |
6148 | int i; | |
6149 | ||
6150 | for (i = 0; i < XVECLEN (pattern, 0) - 1; i++) | |
6151 | RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1)); | |
6152 | ||
6153 | pattern = gen_rtx_PARALLEL (VOIDmode, vec); | |
6154 | } | |
6155 | ||
6156 | return pattern; | |
6157 | } | |
6158 | ||
6159 | /* Indicate that INSN cannot be duplicated. This is the case for | |
6160 | execute insns that carry a unique label. */ | |
6161 | ||
6162 | static bool | |
6163 | s390_cannot_copy_insn_p (rtx insn) | |
6164 | { | |
6165 | rtx label = s390_execute_label (insn); | |
6166 | return label && label != const0_rtx; | |
6167 | } | |
6168 | ||
5af2f3d3 UW |
6169 | /* Dump out the constants in POOL. If REMOTE_LABEL is true, |
6170 | do not emit the pool base label. */ | |
b2ccb744 | 6171 | |
9bb86f41 | 6172 | static void |
5af2f3d3 | 6173 | s390_dump_pool (struct constant_pool *pool, bool remote_label) |
b2ccb744 UW |
6174 | { |
6175 | struct constant *c; | |
9bb86f41 | 6176 | rtx insn = pool->pool_insn; |
b2ccb744 UW |
6177 | int i; |
6178 | ||
9bb86f41 UW |
6179 | /* Switch to rodata section. */ |
6180 | if (TARGET_CPU_ZARCH) | |
6181 | { | |
6182 | insn = emit_insn_after (gen_pool_section_start (), insn); | |
6183 | INSN_ADDRESSES_NEW (insn, -1); | |
6184 | } | |
6185 | ||
6186 | /* Ensure minimum pool alignment. */ | |
9e8327e3 | 6187 | if (TARGET_CPU_ZARCH) |
9bb86f41 | 6188 | insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn); |
b2ccb744 | 6189 | else |
9bb86f41 | 6190 | insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn); |
b2ccb744 UW |
6191 | INSN_ADDRESSES_NEW (insn, -1); |
6192 | ||
9bb86f41 | 6193 | /* Emit pool base label. */ |
5af2f3d3 UW |
6194 | if (!remote_label) |
6195 | { | |
6196 | insn = emit_label_after (pool->label, insn); | |
6197 | INSN_ADDRESSES_NEW (insn, -1); | |
6198 | } | |
b2ccb744 UW |
6199 | |
6200 | /* Dump constants in descending alignment requirement order, | |
6201 | ensuring proper alignment for every constant. */ | |
6202 | for (i = 0; i < NR_C_MODES; i++) | |
6203 | for (c = pool->constants[i]; c; c = c->next) | |
6204 | { | |
fd7643fb | 6205 | /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */ |
77340500 | 6206 | rtx value = copy_rtx (c->value); |
aee4e0db UW |
6207 | if (GET_CODE (value) == CONST |
6208 | && GET_CODE (XEXP (value, 0)) == UNSPEC | |
fd7643fb | 6209 | && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET |
aee4e0db | 6210 | && XVECLEN (XEXP (value, 0), 0) == 1) |
dc66391d | 6211 | value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0)); |
aee4e0db | 6212 | |
b2ccb744 UW |
6213 | insn = emit_label_after (c->label, insn); |
6214 | INSN_ADDRESSES_NEW (insn, -1); | |
416cf582 | 6215 | |
38899e29 | 6216 | value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i], |
416cf582 UW |
6217 | gen_rtvec (1, value), |
6218 | UNSPECV_POOL_ENTRY); | |
6219 | insn = emit_insn_after (value, insn); | |
b2ccb744 UW |
6220 | INSN_ADDRESSES_NEW (insn, -1); |
6221 | } | |
6222 | ||
9bb86f41 UW |
6223 | /* Ensure minimum alignment for instructions. */ |
6224 | insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn); | |
b2ccb744 UW |
6225 | INSN_ADDRESSES_NEW (insn, -1); |
6226 | ||
9bb86f41 UW |
6227 | /* Output in-pool execute template insns. */ |
6228 | for (c = pool->execute; c; c = c->next) | |
6229 | { | |
9bb86f41 UW |
6230 | insn = emit_label_after (c->label, insn); |
6231 | INSN_ADDRESSES_NEW (insn, -1); | |
6232 | ||
6233 | insn = emit_insn_after (s390_execute_target (c->value), insn); | |
6234 | INSN_ADDRESSES_NEW (insn, -1); | |
6235 | } | |
6236 | ||
6237 | /* Switch back to previous section. */ | |
6238 | if (TARGET_CPU_ZARCH) | |
6239 | { | |
6240 | insn = emit_insn_after (gen_pool_section_end (), insn); | |
6241 | INSN_ADDRESSES_NEW (insn, -1); | |
6242 | } | |
6243 | ||
b2ccb744 UW |
6244 | insn = emit_barrier_after (insn); |
6245 | INSN_ADDRESSES_NEW (insn, -1); | |
6246 | ||
aee4e0db UW |
6247 | /* Remove placeholder insn. */ |
6248 | remove_insn (pool->pool_insn); | |
9bb86f41 UW |
6249 | } |
6250 | ||
b2ccb744 UW |
6251 | /* Free all memory used by POOL. */ |
6252 | ||
6253 | static void | |
9c808aad | 6254 | s390_free_pool (struct constant_pool *pool) |
b2ccb744 | 6255 | { |
9bb86f41 | 6256 | struct constant *c, *next; |
b2ccb744 UW |
6257 | int i; |
6258 | ||
6259 | for (i = 0; i < NR_C_MODES; i++) | |
9bb86f41 UW |
6260 | for (c = pool->constants[i]; c; c = next) |
6261 | { | |
6262 | next = c->next; | |
6263 | free (c); | |
6264 | } | |
6265 | ||
6266 | for (c = pool->execute; c; c = next) | |
b2ccb744 | 6267 | { |
9bb86f41 UW |
6268 | next = c->next; |
6269 | free (c); | |
b2ccb744 UW |
6270 | } |
6271 | ||
7b210806 | 6272 | BITMAP_FREE (pool->insns); |
b2ccb744 | 6273 | free (pool); |
c7453384 | 6274 | } |
b2ccb744 | 6275 | |
b2ccb744 | 6276 | |
5af2f3d3 UW |
6277 | /* Collect main literal pool. Return NULL on overflow. */ |
6278 | ||
6279 | static struct constant_pool * | |
6280 | s390_mainpool_start (void) | |
6281 | { | |
6282 | struct constant_pool *pool; | |
6283 | rtx insn; | |
6284 | ||
6285 | pool = s390_alloc_pool (); | |
6286 | ||
6287 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
6288 | { | |
6289 | if (GET_CODE (insn) == INSN | |
585539a1 UW |
6290 | && GET_CODE (PATTERN (insn)) == SET |
6291 | && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE | |
6292 | && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL) | |
5af2f3d3 | 6293 | { |
8d933e31 | 6294 | gcc_assert (!pool->pool_insn); |
5af2f3d3 UW |
6295 | pool->pool_insn = insn; |
6296 | } | |
6297 | ||
d24959df | 6298 | if (!TARGET_CPU_ZARCH && s390_execute_label (insn)) |
9bb86f41 UW |
6299 | { |
6300 | s390_add_execute (pool, insn); | |
6301 | } | |
6302 | else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN) | |
5af2f3d3 UW |
6303 | { |
6304 | rtx pool_ref = NULL_RTX; | |
6305 | find_constant_pool_ref (PATTERN (insn), &pool_ref); | |
6306 | if (pool_ref) | |
6307 | { | |
6308 | rtx constant = get_pool_constant (pool_ref); | |
6309 | enum machine_mode mode = get_pool_mode (pool_ref); | |
6310 | s390_add_constant (pool, constant, mode); | |
6311 | } | |
6312 | } | |
03870a04 AK |
6313 | |
6314 | /* If hot/cold partitioning is enabled we have to make sure that | |
6315 | the literal pool is emitted in the same section where the | |
6316 | initialization of the literal pool base pointer takes place. | |
6317 | emit_pool_after is only used in the non-overflow case on non | |
6318 | Z cpus where we can emit the literal pool at the end of the | |
6319 | function body within the text section. */ | |
6320 | if (NOTE_P (insn) | |
b49326f1 AK |
6321 | && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS |
6322 | && !pool->emit_pool_after) | |
6323 | pool->emit_pool_after = PREV_INSN (insn); | |
5af2f3d3 UW |
6324 | } |
6325 | ||
8d933e31 | 6326 | gcc_assert (pool->pool_insn || pool->size == 0); |
5af2f3d3 UW |
6327 | |
6328 | if (pool->size >= 4096) | |
6329 | { | |
d76e8439 UW |
6330 | /* We're going to chunkify the pool, so remove the main |
6331 | pool placeholder insn. */ | |
6332 | remove_insn (pool->pool_insn); | |
6333 | ||
5af2f3d3 UW |
6334 | s390_free_pool (pool); |
6335 | pool = NULL; | |
6336 | } | |
6337 | ||
03870a04 AK |
6338 | /* If the functions ends with the section where the literal pool |
6339 | should be emitted set the marker to its end. */ | |
b49326f1 | 6340 | if (pool && !pool->emit_pool_after) |
03870a04 AK |
6341 | pool->emit_pool_after = get_last_insn (); |
6342 | ||
5af2f3d3 UW |
6343 | return pool; |
6344 | } | |
6345 | ||
6346 | /* POOL holds the main literal pool as collected by s390_mainpool_start. | |
6347 | Modify the current function to output the pool constants as well as | |
585539a1 | 6348 | the pool register setup instruction. */ |
5af2f3d3 UW |
6349 | |
6350 | static void | |
585539a1 | 6351 | s390_mainpool_finish (struct constant_pool *pool) |
5af2f3d3 | 6352 | { |
91086990 | 6353 | rtx base_reg = cfun->machine->base_reg; |
5af2f3d3 UW |
6354 | rtx insn; |
6355 | ||
6356 | /* If the pool is empty, we're done. */ | |
6357 | if (pool->size == 0) | |
6358 | { | |
91086990 UW |
6359 | /* We don't actually need a base register after all. */ |
6360 | cfun->machine->base_reg = NULL_RTX; | |
6361 | ||
6362 | if (pool->pool_insn) | |
6363 | remove_insn (pool->pool_insn); | |
5af2f3d3 UW |
6364 | s390_free_pool (pool); |
6365 | return; | |
6366 | } | |
6367 | ||
6368 | /* We need correct insn addresses. */ | |
6369 | shorten_branches (get_insns ()); | |
6370 | ||
9e8327e3 | 6371 | /* On zSeries, we use a LARL to load the pool register. The pool is |
5af2f3d3 | 6372 | located in the .rodata section, so we emit it after the function. */ |
9e8327e3 | 6373 | if (TARGET_CPU_ZARCH) |
5af2f3d3 UW |
6374 | { |
6375 | insn = gen_main_base_64 (base_reg, pool->label); | |
6376 | insn = emit_insn_after (insn, pool->pool_insn); | |
6377 | INSN_ADDRESSES_NEW (insn, -1); | |
6378 | remove_insn (pool->pool_insn); | |
38899e29 EC |
6379 | |
6380 | insn = get_last_insn (); | |
5af2f3d3 UW |
6381 | pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn); |
6382 | INSN_ADDRESSES_NEW (pool->pool_insn, -1); | |
6383 | ||
6384 | s390_dump_pool (pool, 0); | |
6385 | } | |
6386 | ||
9e8327e3 | 6387 | /* On S/390, if the total size of the function's code plus literal pool |
5af2f3d3 UW |
6388 | does not exceed 4096 bytes, we use BASR to set up a function base |
6389 | pointer, and emit the literal pool at the end of the function. */ | |
03870a04 | 6390 | else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after)) |
5af2f3d3 UW |
6391 | + pool->size + 8 /* alignment slop */ < 4096) |
6392 | { | |
6393 | insn = gen_main_base_31_small (base_reg, pool->label); | |
6394 | insn = emit_insn_after (insn, pool->pool_insn); | |
6395 | INSN_ADDRESSES_NEW (insn, -1); | |
6396 | remove_insn (pool->pool_insn); | |
6397 | ||
6398 | insn = emit_label_after (pool->label, insn); | |
6399 | INSN_ADDRESSES_NEW (insn, -1); | |
6400 | ||
03870a04 AK |
6401 | /* emit_pool_after will be set by s390_mainpool_start to the |
6402 | last insn of the section where the literal pool should be | |
6403 | emitted. */ | |
6404 | insn = pool->emit_pool_after; | |
6405 | ||
5af2f3d3 UW |
6406 | pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn); |
6407 | INSN_ADDRESSES_NEW (pool->pool_insn, -1); | |
6408 | ||
6409 | s390_dump_pool (pool, 1); | |
6410 | } | |
6411 | ||
6412 | /* Otherwise, we emit an inline literal pool and use BASR to branch | |
6413 | over it, setting up the pool register at the same time. */ | |
6414 | else | |
6415 | { | |
6416 | rtx pool_end = gen_label_rtx (); | |
6417 | ||
6418 | insn = gen_main_base_31_large (base_reg, pool->label, pool_end); | |
6419 | insn = emit_insn_after (insn, pool->pool_insn); | |
6420 | INSN_ADDRESSES_NEW (insn, -1); | |
6421 | remove_insn (pool->pool_insn); | |
6422 | ||
6423 | insn = emit_label_after (pool->label, insn); | |
6424 | INSN_ADDRESSES_NEW (insn, -1); | |
6425 | ||
6426 | pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn); | |
6427 | INSN_ADDRESSES_NEW (pool->pool_insn, -1); | |
6428 | ||
6429 | insn = emit_label_after (pool_end, pool->pool_insn); | |
6430 | INSN_ADDRESSES_NEW (insn, -1); | |
6431 | ||
6432 | s390_dump_pool (pool, 1); | |
6433 | } | |
6434 | ||
6435 | ||
6436 | /* Replace all literal pool references. */ | |
6437 | ||
6438 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
6439 | { | |
6440 | if (INSN_P (insn)) | |
585539a1 | 6441 | replace_ltrel_base (&PATTERN (insn)); |
5af2f3d3 UW |
6442 | |
6443 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN) | |
6444 | { | |
6445 | rtx addr, pool_ref = NULL_RTX; | |
6446 | find_constant_pool_ref (PATTERN (insn), &pool_ref); | |
6447 | if (pool_ref) | |
6448 | { | |
9bb86f41 UW |
6449 | if (s390_execute_label (insn)) |
6450 | addr = s390_find_execute (pool, insn); | |
6451 | else | |
6452 | addr = s390_find_constant (pool, get_pool_constant (pool_ref), | |
6453 | get_pool_mode (pool_ref)); | |
6454 | ||
5af2f3d3 UW |
6455 | replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr); |
6456 | INSN_CODE (insn) = -1; | |
6457 | } | |
6458 | } | |
6459 | } | |
6460 | ||
6461 | ||
6462 | /* Free the pool. */ | |
6463 | s390_free_pool (pool); | |
6464 | } | |
6465 | ||
6466 | /* POOL holds the main literal pool as collected by s390_mainpool_start. | |
6467 | We have decided we cannot use this pool, so revert all changes | |
6468 | to the current function that were done by s390_mainpool_start. */ | |
6469 | static void | |
6470 | s390_mainpool_cancel (struct constant_pool *pool) | |
6471 | { | |
6472 | /* We didn't actually change the instruction stream, so simply | |
6473 | free the pool memory. */ | |
6474 | s390_free_pool (pool); | |
6475 | } | |
6476 | ||
6477 | ||
585539a1 | 6478 | /* Chunkify the literal pool. */ |
9db1d521 | 6479 | |
b2ccb744 UW |
6480 | #define S390_POOL_CHUNK_MIN 0xc00 |
6481 | #define S390_POOL_CHUNK_MAX 0xe00 | |
6482 | ||
c7453384 | 6483 | static struct constant_pool * |
585539a1 | 6484 | s390_chunkify_start (void) |
9db1d521 | 6485 | { |
b2ccb744 UW |
6486 | struct constant_pool *curr_pool = NULL, *pool_list = NULL; |
6487 | int extra_size = 0; | |
6488 | bitmap far_labels; | |
fd7643fb | 6489 | rtx pending_ltrel = NULL_RTX; |
13e58269 | 6490 | rtx insn; |
9db1d521 | 6491 | |
9c808aad | 6492 | rtx (*gen_reload_base) (rtx, rtx) = |
9e8327e3 | 6493 | TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31; |
aee4e0db UW |
6494 | |
6495 | ||
c3cc6b78 UW |
6496 | /* We need correct insn addresses. */ |
6497 | ||
6498 | shorten_branches (get_insns ()); | |
6499 | ||
fd7643fb | 6500 | /* Scan all insns and move literals to pool chunks. */ |
13e58269 | 6501 | |
13e58269 | 6502 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
9db1d521 | 6503 | { |
03870a04 AK |
6504 | bool section_switch_p = false; |
6505 | ||
fd7643fb UW |
6506 | /* Check for pending LTREL_BASE. */ |
6507 | if (INSN_P (insn)) | |
6508 | { | |
6509 | rtx ltrel_base = find_ltrel_base (PATTERN (insn)); | |
6510 | if (ltrel_base) | |
6511 | { | |
8d933e31 AS |
6512 | gcc_assert (ltrel_base == pending_ltrel); |
6513 | pending_ltrel = NULL_RTX; | |
fd7643fb UW |
6514 | } |
6515 | } | |
6516 | ||
d24959df | 6517 | if (!TARGET_CPU_ZARCH && s390_execute_label (insn)) |
9bb86f41 UW |
6518 | { |
6519 | if (!curr_pool) | |
6520 | curr_pool = s390_start_pool (&pool_list, insn); | |
6521 | ||
6522 | s390_add_execute (curr_pool, insn); | |
6523 | s390_add_pool_insn (curr_pool, insn); | |
6524 | } | |
6525 | else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN) | |
b2ccb744 | 6526 | { |
aee4e0db | 6527 | rtx pool_ref = NULL_RTX; |
b2ccb744 UW |
6528 | find_constant_pool_ref (PATTERN (insn), &pool_ref); |
6529 | if (pool_ref) | |
6530 | { | |
fd7643fb UW |
6531 | rtx constant = get_pool_constant (pool_ref); |
6532 | enum machine_mode mode = get_pool_mode (pool_ref); | |
6533 | ||
b2ccb744 UW |
6534 | if (!curr_pool) |
6535 | curr_pool = s390_start_pool (&pool_list, insn); | |
6536 | ||
fd7643fb | 6537 | s390_add_constant (curr_pool, constant, mode); |
aee4e0db | 6538 | s390_add_pool_insn (curr_pool, insn); |
aee4e0db | 6539 | |
fd7643fb UW |
6540 | /* Don't split the pool chunk between a LTREL_OFFSET load |
6541 | and the corresponding LTREL_BASE. */ | |
6542 | if (GET_CODE (constant) == CONST | |
6543 | && GET_CODE (XEXP (constant, 0)) == UNSPEC | |
6544 | && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET) | |
6545 | { | |
8d933e31 | 6546 | gcc_assert (!pending_ltrel); |
fd7643fb UW |
6547 | pending_ltrel = pool_ref; |
6548 | } | |
b2ccb744 UW |
6549 | } |
6550 | } | |
6551 | ||
aee4e0db | 6552 | if (GET_CODE (insn) == JUMP_INSN || GET_CODE (insn) == CODE_LABEL) |
fd7643fb UW |
6553 | { |
6554 | if (curr_pool) | |
6555 | s390_add_pool_insn (curr_pool, insn); | |
6556 | /* An LTREL_BASE must follow within the same basic block. */ | |
8d933e31 | 6557 | gcc_assert (!pending_ltrel); |
fd7643fb | 6558 | } |
aee4e0db | 6559 | |
03870a04 AK |
6560 | if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS) |
6561 | section_switch_p = true; | |
6562 | ||
c7453384 | 6563 | if (!curr_pool |
b2ccb744 UW |
6564 | || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn) |
6565 | || INSN_ADDRESSES (INSN_UID (insn)) == -1) | |
9db1d521 | 6566 | continue; |
13e58269 | 6567 | |
9e8327e3 | 6568 | if (TARGET_CPU_ZARCH) |
9db1d521 | 6569 | { |
b2ccb744 UW |
6570 | if (curr_pool->size < S390_POOL_CHUNK_MAX) |
6571 | continue; | |
13e58269 | 6572 | |
aee4e0db | 6573 | s390_end_pool (curr_pool, NULL_RTX); |
b2ccb744 UW |
6574 | curr_pool = NULL; |
6575 | } | |
6576 | else | |
9db1d521 | 6577 | { |
b2ccb744 | 6578 | int chunk_size = INSN_ADDRESSES (INSN_UID (insn)) |
9c808aad | 6579 | - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn)) |
b2ccb744 UW |
6580 | + extra_size; |
6581 | ||
6582 | /* We will later have to insert base register reload insns. | |
6583 | Those will have an effect on code size, which we need to | |
6584 | consider here. This calculation makes rather pessimistic | |
6585 | worst-case assumptions. */ | |
aee4e0db | 6586 | if (GET_CODE (insn) == CODE_LABEL) |
b2ccb744 | 6587 | extra_size += 6; |
b2ccb744 UW |
6588 | |
6589 | if (chunk_size < S390_POOL_CHUNK_MIN | |
03870a04 AK |
6590 | && curr_pool->size < S390_POOL_CHUNK_MIN |
6591 | && !section_switch_p) | |
b2ccb744 UW |
6592 | continue; |
6593 | ||
6594 | /* Pool chunks can only be inserted after BARRIERs ... */ | |
6595 | if (GET_CODE (insn) == BARRIER) | |
6596 | { | |
6597 | s390_end_pool (curr_pool, insn); | |
6598 | curr_pool = NULL; | |
6599 | extra_size = 0; | |
6600 | } | |
6601 | ||
6602 | /* ... so if we don't find one in time, create one. */ | |
03870a04 AK |
6603 | else if (chunk_size > S390_POOL_CHUNK_MAX |
6604 | || curr_pool->size > S390_POOL_CHUNK_MAX | |
6605 | || section_switch_p) | |
b2ccb744 | 6606 | { |
b2ccb744 UW |
6607 | rtx label, jump, barrier; |
6608 | ||
03870a04 AK |
6609 | if (!section_switch_p) |
6610 | { | |
6611 | /* We can insert the barrier only after a 'real' insn. */ | |
6612 | if (GET_CODE (insn) != INSN && GET_CODE (insn) != CALL_INSN) | |
6613 | continue; | |
6614 | if (get_attr_length (insn) == 0) | |
6615 | continue; | |
6616 | /* Don't separate LTREL_BASE from the corresponding | |
fd7643fb | 6617 | LTREL_OFFSET load. */ |
03870a04 AK |
6618 | if (pending_ltrel) |
6619 | continue; | |
6620 | } | |
6621 | else | |
6622 | { | |
6623 | gcc_assert (!pending_ltrel); | |
6624 | ||
6625 | /* The old pool has to end before the section switch | |
6626 | note in order to make it part of the current | |
6627 | section. */ | |
6628 | insn = PREV_INSN (insn); | |
6629 | } | |
aee4e0db | 6630 | |
9c808aad | 6631 | label = gen_label_rtx (); |
b2ccb744 UW |
6632 | jump = emit_jump_insn_after (gen_jump (label), insn); |
6633 | barrier = emit_barrier_after (jump); | |
6634 | insn = emit_label_after (label, barrier); | |
6635 | JUMP_LABEL (jump) = label; | |
6636 | LABEL_NUSES (label) = 1; | |
6637 | ||
aee4e0db UW |
6638 | INSN_ADDRESSES_NEW (jump, -1); |
6639 | INSN_ADDRESSES_NEW (barrier, -1); | |
b2ccb744 UW |
6640 | INSN_ADDRESSES_NEW (insn, -1); |
6641 | ||
6642 | s390_end_pool (curr_pool, barrier); | |
6643 | curr_pool = NULL; | |
6644 | extra_size = 0; | |
6645 | } | |
13e58269 | 6646 | } |
9db1d521 | 6647 | } |
ce50cae8 | 6648 | |
aee4e0db UW |
6649 | if (curr_pool) |
6650 | s390_end_pool (curr_pool, NULL_RTX); | |
8d933e31 | 6651 | gcc_assert (!pending_ltrel); |
b2ccb744 | 6652 | |
c7453384 | 6653 | /* Find all labels that are branched into |
13e58269 | 6654 | from an insn belonging to a different chunk. */ |
ce50cae8 | 6655 | |
7b210806 | 6656 | far_labels = BITMAP_ALLOC (NULL); |
6bc627b3 | 6657 | |
13e58269 | 6658 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
9db1d521 | 6659 | { |
b2ccb744 UW |
6660 | /* Labels marked with LABEL_PRESERVE_P can be target |
6661 | of non-local jumps, so we have to mark them. | |
6662 | The same holds for named labels. | |
6663 | ||
6664 | Don't do that, however, if it is the label before | |
6665 | a jump table. */ | |
6666 | ||
c7453384 | 6667 | if (GET_CODE (insn) == CODE_LABEL |
b2ccb744 UW |
6668 | && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn))) |
6669 | { | |
6670 | rtx vec_insn = next_real_insn (insn); | |
c7453384 | 6671 | rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ? |
b2ccb744 UW |
6672 | PATTERN (vec_insn) : NULL_RTX; |
6673 | if (!vec_pat | |
6674 | || !(GET_CODE (vec_pat) == ADDR_VEC | |
6675 | || GET_CODE (vec_pat) == ADDR_DIFF_VEC)) | |
6676 | bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn)); | |
6677 | } | |
6678 | ||
6679 | /* If we have a direct jump (conditional or unconditional) | |
6680 | or a casesi jump, check all potential targets. */ | |
c7453384 | 6681 | else if (GET_CODE (insn) == JUMP_INSN) |
13e58269 UW |
6682 | { |
6683 | rtx pat = PATTERN (insn); | |
0a3bdf9d UW |
6684 | if (GET_CODE (pat) == PARALLEL && XVECLEN (pat, 0) > 2) |
6685 | pat = XVECEXP (pat, 0, 0); | |
6686 | ||
c7453384 | 6687 | if (GET_CODE (pat) == SET) |
13e58269 | 6688 | { |
aee4e0db | 6689 | rtx label = JUMP_LABEL (insn); |
13e58269 UW |
6690 | if (label) |
6691 | { | |
c7453384 | 6692 | if (s390_find_pool (pool_list, label) |
b2ccb744 UW |
6693 | != s390_find_pool (pool_list, insn)) |
6694 | bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label)); | |
13e58269 | 6695 | } |
c7453384 | 6696 | } |
b2ccb744 UW |
6697 | else if (GET_CODE (pat) == PARALLEL |
6698 | && XVECLEN (pat, 0) == 2 | |
6699 | && GET_CODE (XVECEXP (pat, 0, 0)) == SET | |
6700 | && GET_CODE (XVECEXP (pat, 0, 1)) == USE | |
6701 | && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == LABEL_REF) | |
6702 | { | |
6703 | /* Find the jump table used by this casesi jump. */ | |
6704 | rtx vec_label = XEXP (XEXP (XVECEXP (pat, 0, 1), 0), 0); | |
6705 | rtx vec_insn = next_real_insn (vec_label); | |
c7453384 | 6706 | rtx vec_pat = vec_insn && GET_CODE (vec_insn) == JUMP_INSN ? |
b2ccb744 UW |
6707 | PATTERN (vec_insn) : NULL_RTX; |
6708 | if (vec_pat | |
6709 | && (GET_CODE (vec_pat) == ADDR_VEC | |
6710 | || GET_CODE (vec_pat) == ADDR_DIFF_VEC)) | |
6711 | { | |
6712 | int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC; | |
13e58269 | 6713 | |
b2ccb744 UW |
6714 | for (i = 0; i < XVECLEN (vec_pat, diff_p); i++) |
6715 | { | |
6716 | rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0); | |
13e58269 | 6717 | |
c7453384 | 6718 | if (s390_find_pool (pool_list, label) |
b2ccb744 UW |
6719 | != s390_find_pool (pool_list, insn)) |
6720 | bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label)); | |
6721 | } | |
6722 | } | |
6723 | } | |
13e58269 | 6724 | } |
9db1d521 | 6725 | } |
ce50cae8 | 6726 | |
b2ccb744 UW |
6727 | /* Insert base register reload insns before every pool. */ |
6728 | ||
6729 | for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next) | |
aee4e0db | 6730 | { |
f4aa3848 | 6731 | rtx new_insn = gen_reload_base (cfun->machine->base_reg, |
585539a1 | 6732 | curr_pool->label); |
aee4e0db UW |
6733 | rtx insn = curr_pool->first_insn; |
6734 | INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1); | |
6735 | } | |
b2ccb744 UW |
6736 | |
6737 | /* Insert base register reload insns at every far label. */ | |
13e58269 | 6738 | |
13e58269 | 6739 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
c7453384 | 6740 | if (GET_CODE (insn) == CODE_LABEL |
b2ccb744 UW |
6741 | && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn))) |
6742 | { | |
6743 | struct constant_pool *pool = s390_find_pool (pool_list, insn); | |
6744 | if (pool) | |
6745 | { | |
f4aa3848 | 6746 | rtx new_insn = gen_reload_base (cfun->machine->base_reg, |
585539a1 | 6747 | pool->label); |
aee4e0db | 6748 | INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1); |
b2ccb744 UW |
6749 | } |
6750 | } | |
6751 | ||
aee4e0db | 6752 | |
7b210806 | 6753 | BITMAP_FREE (far_labels); |
13e58269 | 6754 | |
13e58269 UW |
6755 | |
6756 | /* Recompute insn addresses. */ | |
6757 | ||
6758 | init_insn_lengths (); | |
6759 | shorten_branches (get_insns ()); | |
9db1d521 | 6760 | |
aee4e0db UW |
6761 | return pool_list; |
6762 | } | |
9db1d521 | 6763 | |
aee4e0db | 6764 | /* POOL_LIST is a chunk list as prepared by s390_chunkify_start. |
c7453384 | 6765 | After we have decided to use this list, finish implementing |
585539a1 | 6766 | all changes to the current function as required. */ |
c7453384 | 6767 | |
aee4e0db | 6768 | static void |
585539a1 | 6769 | s390_chunkify_finish (struct constant_pool *pool_list) |
aee4e0db | 6770 | { |
aee4e0db UW |
6771 | struct constant_pool *curr_pool = NULL; |
6772 | rtx insn; | |
c7453384 EC |
6773 | |
6774 | ||
aee4e0db UW |
6775 | /* Replace all literal pool references. */ |
6776 | ||
c7453384 | 6777 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) |
aee4e0db | 6778 | { |
fd7643fb | 6779 | if (INSN_P (insn)) |
585539a1 | 6780 | replace_ltrel_base (&PATTERN (insn)); |
fd7643fb | 6781 | |
aee4e0db UW |
6782 | curr_pool = s390_find_pool (pool_list, insn); |
6783 | if (!curr_pool) | |
6784 | continue; | |
6785 | ||
6786 | if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN) | |
6787 | { | |
6788 | rtx addr, pool_ref = NULL_RTX; | |
6789 | find_constant_pool_ref (PATTERN (insn), &pool_ref); | |
6790 | if (pool_ref) | |
6791 | { | |
9bb86f41 UW |
6792 | if (s390_execute_label (insn)) |
6793 | addr = s390_find_execute (curr_pool, insn); | |
6794 | else | |
6795 | addr = s390_find_constant (curr_pool, | |
6796 | get_pool_constant (pool_ref), | |
6797 | get_pool_mode (pool_ref)); | |
6798 | ||
aee4e0db UW |
6799 | replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr); |
6800 | INSN_CODE (insn) = -1; | |
6801 | } | |
aee4e0db UW |
6802 | } |
6803 | } | |
6804 | ||
6805 | /* Dump out all literal pools. */ | |
c7453384 | 6806 | |
aee4e0db | 6807 | for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next) |
5af2f3d3 | 6808 | s390_dump_pool (curr_pool, 0); |
c7453384 | 6809 | |
aee4e0db UW |
6810 | /* Free pool list. */ |
6811 | ||
6812 | while (pool_list) | |
6813 | { | |
6814 | struct constant_pool *next = pool_list->next; | |
6815 | s390_free_pool (pool_list); | |
6816 | pool_list = next; | |
6817 | } | |
6818 | } | |
6819 | ||
6820 | /* POOL_LIST is a chunk list as prepared by s390_chunkify_start. | |
6821 | We have decided we cannot use this list, so revert all changes | |
6822 | to the current function that were done by s390_chunkify_start. */ | |
c7453384 | 6823 | |
aee4e0db | 6824 | static void |
9c808aad | 6825 | s390_chunkify_cancel (struct constant_pool *pool_list) |
aee4e0db UW |
6826 | { |
6827 | struct constant_pool *curr_pool = NULL; | |
6828 | rtx insn; | |
6829 | ||
6830 | /* Remove all pool placeholder insns. */ | |
6831 | ||
6832 | for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next) | |
6833 | { | |
6834 | /* Did we insert an extra barrier? Remove it. */ | |
6835 | rtx barrier = PREV_INSN (curr_pool->pool_insn); | |
6836 | rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX; | |
6837 | rtx label = NEXT_INSN (curr_pool->pool_insn); | |
6838 | ||
6839 | if (jump && GET_CODE (jump) == JUMP_INSN | |
6840 | && barrier && GET_CODE (barrier) == BARRIER | |
6841 | && label && GET_CODE (label) == CODE_LABEL | |
6842 | && GET_CODE (PATTERN (jump)) == SET | |
6843 | && SET_DEST (PATTERN (jump)) == pc_rtx | |
6844 | && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF | |
6845 | && XEXP (SET_SRC (PATTERN (jump)), 0) == label) | |
6846 | { | |
6847 | remove_insn (jump); | |
6848 | remove_insn (barrier); | |
6849 | remove_insn (label); | |
b2ccb744 | 6850 | } |
9db1d521 | 6851 | |
aee4e0db UW |
6852 | remove_insn (curr_pool->pool_insn); |
6853 | } | |
6854 | ||
fd7643fb | 6855 | /* Remove all base register reload insns. */ |
aee4e0db UW |
6856 | |
6857 | for (insn = get_insns (); insn; ) | |
6858 | { | |
6859 | rtx next_insn = NEXT_INSN (insn); | |
6860 | ||
6861 | if (GET_CODE (insn) == INSN | |
6862 | && GET_CODE (PATTERN (insn)) == SET | |
6863 | && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC | |
fd7643fb | 6864 | && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE) |
aee4e0db | 6865 | remove_insn (insn); |
9db1d521 | 6866 | |
aee4e0db UW |
6867 | insn = next_insn; |
6868 | } | |
6869 | ||
6870 | /* Free pool list. */ | |
9db1d521 | 6871 | |
b2ccb744 | 6872 | while (pool_list) |
9db1d521 | 6873 | { |
b2ccb744 UW |
6874 | struct constant_pool *next = pool_list->next; |
6875 | s390_free_pool (pool_list); | |
6876 | pool_list = next; | |
9db1d521 | 6877 | } |
9db1d521 HP |
6878 | } |
6879 | ||
faeb9bb6 | 6880 | /* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */ |
416cf582 UW |
6881 | |
6882 | void | |
faeb9bb6 | 6883 | s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align) |
416cf582 UW |
6884 | { |
6885 | REAL_VALUE_TYPE r; | |
6886 | ||
6887 | switch (GET_MODE_CLASS (mode)) | |
6888 | { | |
6889 | case MODE_FLOAT: | |
4dc19cc0 | 6890 | case MODE_DECIMAL_FLOAT: |
8d933e31 | 6891 | gcc_assert (GET_CODE (exp) == CONST_DOUBLE); |
416cf582 UW |
6892 | |
6893 | REAL_VALUE_FROM_CONST_DOUBLE (r, exp); | |
6894 | assemble_real (r, mode, align); | |
6895 | break; | |
6896 | ||
6897 | case MODE_INT: | |
faeb9bb6 | 6898 | assemble_integer (exp, GET_MODE_SIZE (mode), align, 1); |
a7fe25b8 | 6899 | mark_symbol_refs_as_used (exp); |
416cf582 UW |
6900 | break; |
6901 | ||
6902 | default: | |
8d933e31 | 6903 | gcc_unreachable (); |
416cf582 UW |
6904 | } |
6905 | } | |
6906 | ||
6907 | ||
ab96de7e AS |
6908 | /* Return an RTL expression representing the value of the return address |
6909 | for the frame COUNT steps up from the current frame. FRAME is the | |
6910 | frame pointer of that frame. */ | |
b2ccb744 | 6911 | |
ab96de7e AS |
6912 | rtx |
6913 | s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED) | |
b2ccb744 | 6914 | { |
ab96de7e AS |
6915 | int offset; |
6916 | rtx addr; | |
aee4e0db | 6917 | |
ab96de7e | 6918 | /* Without backchain, we fail for all but the current frame. */ |
c3cc6b78 | 6919 | |
ab96de7e AS |
6920 | if (!TARGET_BACKCHAIN && count > 0) |
6921 | return NULL_RTX; | |
c3cc6b78 | 6922 | |
ab96de7e AS |
6923 | /* For the current frame, we need to make sure the initial |
6924 | value of RETURN_REGNUM is actually saved. */ | |
c3cc6b78 | 6925 | |
ab96de7e | 6926 | if (count == 0) |
c3cc6b78 | 6927 | { |
7bcebb25 AK |
6928 | /* On non-z architectures branch splitting could overwrite r14. */ |
6929 | if (TARGET_CPU_ZARCH) | |
6930 | return get_hard_reg_initial_val (Pmode, RETURN_REGNUM); | |
6931 | else | |
6932 | { | |
6933 | cfun_frame_layout.save_return_addr_p = true; | |
6934 | return gen_rtx_MEM (Pmode, return_address_pointer_rtx); | |
6935 | } | |
ab96de7e | 6936 | } |
c3cc6b78 | 6937 | |
ab96de7e | 6938 | if (TARGET_PACKED_STACK) |
9602b6a1 | 6939 | offset = -2 * UNITS_PER_LONG; |
ab96de7e | 6940 | else |
9602b6a1 | 6941 | offset = RETURN_REGNUM * UNITS_PER_LONG; |
c3cc6b78 | 6942 | |
ab96de7e AS |
6943 | addr = plus_constant (frame, offset); |
6944 | addr = memory_address (Pmode, addr); | |
6945 | return gen_rtx_MEM (Pmode, addr); | |
6946 | } | |
c3cc6b78 | 6947 | |
ab96de7e AS |
6948 | /* Return an RTL expression representing the back chain stored in |
6949 | the current stack frame. */ | |
545d16ff | 6950 | |
ab96de7e AS |
6951 | rtx |
6952 | s390_back_chain_rtx (void) | |
6953 | { | |
6954 | rtx chain; | |
545d16ff | 6955 | |
ab96de7e | 6956 | gcc_assert (TARGET_BACKCHAIN); |
545d16ff | 6957 | |
ab96de7e AS |
6958 | if (TARGET_PACKED_STACK) |
6959 | chain = plus_constant (stack_pointer_rtx, | |
9602b6a1 | 6960 | STACK_POINTER_OFFSET - UNITS_PER_LONG); |
ab96de7e AS |
6961 | else |
6962 | chain = stack_pointer_rtx; | |
545d16ff | 6963 | |
ab96de7e AS |
6964 | chain = gen_rtx_MEM (Pmode, chain); |
6965 | return chain; | |
6966 | } | |
c3cc6b78 | 6967 | |
ab96de7e AS |
6968 | /* Find first call clobbered register unused in a function. |
6969 | This could be used as base register in a leaf function | |
6970 | or for holding the return address before epilogue. */ | |
c3cc6b78 | 6971 | |
ab96de7e AS |
6972 | static int |
6973 | find_unused_clobbered_reg (void) | |
6974 | { | |
6975 | int i; | |
6976 | for (i = 0; i < 6; i++) | |
6fb5fa3c | 6977 | if (!df_regs_ever_live_p (i)) |
ab96de7e AS |
6978 | return i; |
6979 | return 0; | |
6980 | } | |
c3cc6b78 | 6981 | |
7bcebb25 | 6982 | |
f4aa3848 | 6983 | /* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all |
7bcebb25 AK |
6984 | clobbered hard regs in SETREG. */ |
6985 | ||
6986 | static void | |
7bc980e1 | 6987 | s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data) |
7bcebb25 AK |
6988 | { |
6989 | int *regs_ever_clobbered = (int *)data; | |
6990 | unsigned int i, regno; | |
6991 | enum machine_mode mode = GET_MODE (setreg); | |
6992 | ||
6993 | if (GET_CODE (setreg) == SUBREG) | |
6994 | { | |
6995 | rtx inner = SUBREG_REG (setreg); | |
6996 | if (!GENERAL_REG_P (inner)) | |
6997 | return; | |
6998 | regno = subreg_regno (setreg); | |
6999 | } | |
7000 | else if (GENERAL_REG_P (setreg)) | |
7001 | regno = REGNO (setreg); | |
7002 | else | |
7003 | return; | |
7004 | ||
7005 | for (i = regno; | |
7006 | i < regno + HARD_REGNO_NREGS (regno, mode); | |
7007 | i++) | |
7008 | regs_ever_clobbered[i] = 1; | |
7009 | } | |
7010 | ||
7011 | /* Walks through all basic blocks of the current function looking | |
7012 | for clobbered hard regs using s390_reg_clobbered_rtx. The fields | |
7013 | of the passed integer array REGS_EVER_CLOBBERED are set to one for | |
7014 | each of those regs. */ | |
7015 | ||
7016 | static void | |
7017 | s390_regs_ever_clobbered (int *regs_ever_clobbered) | |
7018 | { | |
7019 | basic_block cur_bb; | |
7020 | rtx cur_insn; | |
7021 | unsigned int i; | |
7022 | ||
7023 | memset (regs_ever_clobbered, 0, 16 * sizeof (int)); | |
7024 | ||
7025 | /* For non-leaf functions we have to consider all call clobbered regs to be | |
7026 | clobbered. */ | |
7027 | if (!current_function_is_leaf) | |
7028 | { | |
7029 | for (i = 0; i < 16; i++) | |
7030 | regs_ever_clobbered[i] = call_really_used_regs[i]; | |
7031 | } | |
7032 | ||
7033 | /* Make the "magic" eh_return registers live if necessary. For regs_ever_live | |
7034 | this work is done by liveness analysis (mark_regs_live_at_end). | |
7035 | Special care is needed for functions containing landing pads. Landing pads | |
7036 | may use the eh registers, but the code which sets these registers is not | |
7037 | contained in that function. Hence s390_regs_ever_clobbered is not able to | |
7038 | deal with this automatically. */ | |
e3b5732b | 7039 | if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p) |
7bcebb25 | 7040 | for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++) |
f4aa3848 AK |
7041 | if (crtl->calls_eh_return |
7042 | || (cfun->machine->has_landing_pad_p | |
6fb5fa3c | 7043 | && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i)))) |
297a777d | 7044 | regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1; |
7bcebb25 AK |
7045 | |
7046 | /* For nonlocal gotos all call-saved registers have to be saved. | |
7047 | This flag is also set for the unwinding code in libgcc. | |
7048 | See expand_builtin_unwind_init. For regs_ever_live this is done by | |
7049 | reload. */ | |
e3b5732b | 7050 | if (cfun->has_nonlocal_label) |
7bcebb25 AK |
7051 | for (i = 0; i < 16; i++) |
7052 | if (!call_really_used_regs[i]) | |
7053 | regs_ever_clobbered[i] = 1; | |
7054 | ||
7055 | FOR_EACH_BB (cur_bb) | |
7056 | { | |
7057 | FOR_BB_INSNS (cur_bb, cur_insn) | |
7058 | { | |
7059 | if (INSN_P (cur_insn)) | |
7060 | note_stores (PATTERN (cur_insn), | |
f4aa3848 | 7061 | s390_reg_clobbered_rtx, |
7bcebb25 AK |
7062 | regs_ever_clobbered); |
7063 | } | |
7064 | } | |
7065 | } | |
7066 | ||
f4aa3848 AK |
7067 | /* Determine the frame area which actually has to be accessed |
7068 | in the function epilogue. The values are stored at the | |
ab96de7e | 7069 | given pointers AREA_BOTTOM (address of the lowest used stack |
f4aa3848 | 7070 | address) and AREA_TOP (address of the first item which does |
ab96de7e | 7071 | not belong to the stack frame). */ |
545d16ff | 7072 | |
ab96de7e AS |
7073 | static void |
7074 | s390_frame_area (int *area_bottom, int *area_top) | |
7075 | { | |
7076 | int b, t; | |
7077 | int i; | |
545d16ff | 7078 | |
ab96de7e AS |
7079 | b = INT_MAX; |
7080 | t = INT_MIN; | |
adf39f8f AK |
7081 | |
7082 | if (cfun_frame_layout.first_restore_gpr != -1) | |
7083 | { | |
7084 | b = (cfun_frame_layout.gprs_offset | |
9602b6a1 | 7085 | + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG); |
adf39f8f | 7086 | t = b + (cfun_frame_layout.last_restore_gpr |
9602b6a1 | 7087 | - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG; |
adf39f8f AK |
7088 | } |
7089 | ||
7090 | if (TARGET_64BIT && cfun_save_high_fprs_p) | |
7091 | { | |
7092 | b = MIN (b, cfun_frame_layout.f8_offset); | |
7093 | t = MAX (t, (cfun_frame_layout.f8_offset | |
7094 | + cfun_frame_layout.high_fprs * 8)); | |
7095 | } | |
7096 | ||
7097 | if (!TARGET_64BIT) | |
7098 | for (i = 2; i < 4; i++) | |
7099 | if (cfun_fpr_bit_p (i)) | |
7100 | { | |
7101 | b = MIN (b, cfun_frame_layout.f4_offset + (i - 2) * 8); | |
7102 | t = MAX (t, cfun_frame_layout.f4_offset + (i - 1) * 8); | |
7103 | } | |
f4aa3848 | 7104 | |
adf39f8f AK |
7105 | *area_bottom = b; |
7106 | *area_top = t; | |
7107 | } | |
7108 | ||
91086990 | 7109 | /* Fill cfun->machine with info about register usage of current function. |
7bcebb25 | 7110 | Return in CLOBBERED_REGS which GPRs are currently considered set. */ |
4023fb28 UW |
7111 | |
7112 | static void | |
7bcebb25 | 7113 | s390_register_info (int clobbered_regs[]) |
4023fb28 UW |
7114 | { |
7115 | int i, j; | |
4023fb28 | 7116 | |
adf39f8f AK |
7117 | /* fprs 8 - 15 are call saved for 64 Bit ABI. */ |
7118 | cfun_frame_layout.fpr_bitmap = 0; | |
7119 | cfun_frame_layout.high_fprs = 0; | |
c3cc6b78 | 7120 | if (TARGET_64BIT) |
c7453384 | 7121 | for (i = 24; i < 32; i++) |
6fb5fa3c | 7122 | if (df_regs_ever_live_p (i) && !global_regs[i]) |
c3cc6b78 | 7123 | { |
adf39f8f AK |
7124 | cfun_set_fpr_bit (i - 16); |
7125 | cfun_frame_layout.high_fprs++; | |
c3cc6b78 | 7126 | } |
4023fb28 | 7127 | |
b767fc11 UW |
7128 | /* Find first and last gpr to be saved. We trust regs_ever_live |
7129 | data, except that we don't save and restore global registers. | |
545d16ff | 7130 | |
b767fc11 UW |
7131 | Also, all registers with special meaning to the compiler need |
7132 | to be handled extra. */ | |
545d16ff | 7133 | |
7bcebb25 AK |
7134 | s390_regs_ever_clobbered (clobbered_regs); |
7135 | ||
b767fc11 | 7136 | for (i = 0; i < 16; i++) |
e2df5c1d | 7137 | clobbered_regs[i] = clobbered_regs[i] && !global_regs[i] && !fixed_regs[i]; |
7bcebb25 AK |
7138 | |
7139 | if (frame_pointer_needed) | |
7140 | clobbered_regs[HARD_FRAME_POINTER_REGNUM] = 1; | |
c3cc6b78 | 7141 | |
b767fc11 | 7142 | if (flag_pic) |
f4aa3848 | 7143 | clobbered_regs[PIC_OFFSET_TABLE_REGNUM] |
6fb5fa3c | 7144 | |= df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM); |
91086990 | 7145 | |
f4aa3848 | 7146 | clobbered_regs[BASE_REGNUM] |
e2df5c1d UW |
7147 | |= (cfun->machine->base_reg |
7148 | && REGNO (cfun->machine->base_reg) == BASE_REGNUM); | |
91086990 | 7149 | |
7bcebb25 | 7150 | clobbered_regs[RETURN_REGNUM] |
e2df5c1d | 7151 | |= (!current_function_is_leaf |
dc4477f5 | 7152 | || TARGET_TPF_PROFILING |
e2df5c1d UW |
7153 | || cfun->machine->split_branches_pending_p |
7154 | || cfun_frame_layout.save_return_addr_p | |
e3b5732b JH |
7155 | || crtl->calls_eh_return |
7156 | || cfun->stdarg); | |
91086990 | 7157 | |
7bcebb25 | 7158 | clobbered_regs[STACK_POINTER_REGNUM] |
e2df5c1d UW |
7159 | |= (!current_function_is_leaf |
7160 | || TARGET_TPF_PROFILING | |
7161 | || cfun_save_high_fprs_p | |
7162 | || get_frame_size () > 0 | |
e3b5732b JH |
7163 | || cfun->calls_alloca |
7164 | || cfun->stdarg); | |
7bcebb25 | 7165 | |
b767fc11 | 7166 | for (i = 6; i < 16; i++) |
6fb5fa3c | 7167 | if (df_regs_ever_live_p (i) || clobbered_regs[i]) |
b767fc11 | 7168 | break; |
4023fb28 | 7169 | for (j = 15; j > i; j--) |
6fb5fa3c | 7170 | if (df_regs_ever_live_p (j) || clobbered_regs[j]) |
b767fc11 | 7171 | break; |
c3cc6b78 | 7172 | |
b767fc11 UW |
7173 | if (i == 16) |
7174 | { | |
7175 | /* Nothing to save/restore. */ | |
fb3712f6 AK |
7176 | cfun_frame_layout.first_save_gpr_slot = -1; |
7177 | cfun_frame_layout.last_save_gpr_slot = -1; | |
adf39f8f AK |
7178 | cfun_frame_layout.first_save_gpr = -1; |
7179 | cfun_frame_layout.first_restore_gpr = -1; | |
7180 | cfun_frame_layout.last_save_gpr = -1; | |
7181 | cfun_frame_layout.last_restore_gpr = -1; | |
b767fc11 UW |
7182 | } |
7183 | else | |
7184 | { | |
fb3712f6 AK |
7185 | /* Save slots for gprs from i to j. */ |
7186 | cfun_frame_layout.first_save_gpr_slot = i; | |
7187 | cfun_frame_layout.last_save_gpr_slot = j; | |
7188 | ||
f4aa3848 AK |
7189 | for (i = cfun_frame_layout.first_save_gpr_slot; |
7190 | i < cfun_frame_layout.last_save_gpr_slot + 1; | |
fb3712f6 AK |
7191 | i++) |
7192 | if (clobbered_regs[i]) | |
7193 | break; | |
7194 | ||
7195 | for (j = cfun_frame_layout.last_save_gpr_slot; j > i; j--) | |
7196 | if (clobbered_regs[j]) | |
7197 | break; | |
f4aa3848 | 7198 | |
fb3712f6 AK |
7199 | if (i == cfun_frame_layout.last_save_gpr_slot + 1) |
7200 | { | |
7201 | /* Nothing to save/restore. */ | |
7202 | cfun_frame_layout.first_save_gpr = -1; | |
7203 | cfun_frame_layout.first_restore_gpr = -1; | |
7204 | cfun_frame_layout.last_save_gpr = -1; | |
7205 | cfun_frame_layout.last_restore_gpr = -1; | |
7206 | } | |
7207 | else | |
7208 | { | |
7209 | /* Save / Restore from gpr i to j. */ | |
7210 | cfun_frame_layout.first_save_gpr = i; | |
7211 | cfun_frame_layout.first_restore_gpr = i; | |
7212 | cfun_frame_layout.last_save_gpr = j; | |
7213 | cfun_frame_layout.last_restore_gpr = j; | |
7214 | } | |
b767fc11 | 7215 | } |
c3cc6b78 | 7216 | |
e3b5732b | 7217 | if (cfun->stdarg) |
b767fc11 | 7218 | { |
adf39f8f | 7219 | /* Varargs functions need to save gprs 2 to 6. */ |
29a79fcf | 7220 | if (cfun->va_list_gpr_size |
38173d38 | 7221 | && crtl->args.info.gprs < GP_ARG_NUM_REG) |
29a79fcf | 7222 | { |
38173d38 | 7223 | int min_gpr = crtl->args.info.gprs; |
29a79fcf UW |
7224 | int max_gpr = min_gpr + cfun->va_list_gpr_size; |
7225 | if (max_gpr > GP_ARG_NUM_REG) | |
7226 | max_gpr = GP_ARG_NUM_REG; | |
7227 | ||
7228 | if (cfun_frame_layout.first_save_gpr == -1 | |
7229 | || cfun_frame_layout.first_save_gpr > 2 + min_gpr) | |
fb3712f6 AK |
7230 | { |
7231 | cfun_frame_layout.first_save_gpr = 2 + min_gpr; | |
7232 | cfun_frame_layout.first_save_gpr_slot = 2 + min_gpr; | |
7233 | } | |
29a79fcf UW |
7234 | |
7235 | if (cfun_frame_layout.last_save_gpr == -1 | |
7236 | || cfun_frame_layout.last_save_gpr < 2 + max_gpr - 1) | |
fb3712f6 AK |
7237 | { |
7238 | cfun_frame_layout.last_save_gpr = 2 + max_gpr - 1; | |
7239 | cfun_frame_layout.last_save_gpr_slot = 2 + max_gpr - 1; | |
7240 | } | |
29a79fcf | 7241 | } |
b767fc11 | 7242 | |
adf39f8f | 7243 | /* Mark f0, f2 for 31 bit and f0-f4 for 64 bit to be saved. */ |
29a79fcf | 7244 | if (TARGET_HARD_FLOAT && cfun->va_list_fpr_size |
38173d38 | 7245 | && crtl->args.info.fprs < FP_ARG_NUM_REG) |
29a79fcf | 7246 | { |
38173d38 | 7247 | int min_fpr = crtl->args.info.fprs; |
29a79fcf UW |
7248 | int max_fpr = min_fpr + cfun->va_list_fpr_size; |
7249 | if (max_fpr > FP_ARG_NUM_REG) | |
7250 | max_fpr = FP_ARG_NUM_REG; | |
7251 | ||
7252 | /* ??? This is currently required to ensure proper location | |
7253 | of the fpr save slots within the va_list save area. */ | |
7254 | if (TARGET_PACKED_STACK) | |
7255 | min_fpr = 0; | |
7256 | ||
7257 | for (i = min_fpr; i < max_fpr; i++) | |
7258 | cfun_set_fpr_bit (i); | |
7259 | } | |
adf39f8f AK |
7260 | } |
7261 | ||
7262 | if (!TARGET_64BIT) | |
7263 | for (i = 2; i < 4; i++) | |
6fb5fa3c | 7264 | if (df_regs_ever_live_p (i + 16) && !global_regs[i + 16]) |
adf39f8f AK |
7265 | cfun_set_fpr_bit (i); |
7266 | } | |
7267 | ||
91086990 | 7268 | /* Fill cfun->machine with info about frame of current function. */ |
adf39f8f AK |
7269 | |
7270 | static void | |
91086990 | 7271 | s390_frame_info (void) |
adf39f8f AK |
7272 | { |
7273 | int i; | |
7274 | ||
7275 | cfun_frame_layout.frame_size = get_frame_size (); | |
adf39f8f | 7276 | if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000) |
c85ce869 | 7277 | fatal_error ("total size of local variables exceeds architecture limit"); |
f4aa3848 | 7278 | |
b3d31392 | 7279 | if (!TARGET_PACKED_STACK) |
adf39f8f AK |
7280 | { |
7281 | cfun_frame_layout.backchain_offset = 0; | |
9602b6a1 | 7282 | cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG; |
adf39f8f AK |
7283 | cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8; |
7284 | cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8; | |
fb3712f6 | 7285 | cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot |
9602b6a1 | 7286 | * UNITS_PER_LONG); |
adf39f8f | 7287 | } |
b3d31392 | 7288 | else if (TARGET_BACKCHAIN) /* kernel stack layout */ |
adf39f8f AK |
7289 | { |
7290 | cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET | |
9602b6a1 | 7291 | - UNITS_PER_LONG); |
f4aa3848 AK |
7292 | cfun_frame_layout.gprs_offset |
7293 | = (cfun_frame_layout.backchain_offset | |
fb3712f6 | 7294 | - (STACK_POINTER_REGNUM - cfun_frame_layout.first_save_gpr_slot + 1) |
9602b6a1 | 7295 | * UNITS_PER_LONG); |
f4aa3848 | 7296 | |
adf39f8f AK |
7297 | if (TARGET_64BIT) |
7298 | { | |
f4aa3848 | 7299 | cfun_frame_layout.f4_offset |
adf39f8f AK |
7300 | = (cfun_frame_layout.gprs_offset |
7301 | - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3))); | |
f4aa3848 AK |
7302 | |
7303 | cfun_frame_layout.f0_offset | |
7304 | = (cfun_frame_layout.f4_offset | |
adf39f8f AK |
7305 | - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1))); |
7306 | } | |
7307 | else | |
7308 | { | |
ea506297 AK |
7309 | /* On 31 bit we have to care about alignment of the |
7310 | floating point regs to provide fastest access. */ | |
f4aa3848 AK |
7311 | cfun_frame_layout.f0_offset |
7312 | = ((cfun_frame_layout.gprs_offset | |
ea506297 | 7313 | & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1)) |
adf39f8f | 7314 | - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1))); |
f4aa3848 AK |
7315 | |
7316 | cfun_frame_layout.f4_offset | |
adf39f8f AK |
7317 | = (cfun_frame_layout.f0_offset |
7318 | - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3))); | |
7319 | } | |
7320 | } | |
7321 | else /* no backchain */ | |
7322 | { | |
f4aa3848 | 7323 | cfun_frame_layout.f4_offset |
adf39f8f AK |
7324 | = (STACK_POINTER_OFFSET |
7325 | - 8 * (cfun_fpr_bit_p (2) + cfun_fpr_bit_p (3))); | |
f4aa3848 AK |
7326 | |
7327 | cfun_frame_layout.f0_offset | |
adf39f8f AK |
7328 | = (cfun_frame_layout.f4_offset |
7329 | - 8 * (cfun_fpr_bit_p (0) + cfun_fpr_bit_p (1))); | |
f4aa3848 AK |
7330 | |
7331 | cfun_frame_layout.gprs_offset | |
adf39f8f AK |
7332 | = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size; |
7333 | } | |
7334 | ||
7335 | if (current_function_is_leaf | |
7336 | && !TARGET_TPF_PROFILING | |
7337 | && cfun_frame_layout.frame_size == 0 | |
7338 | && !cfun_save_high_fprs_p | |
e3b5732b JH |
7339 | && !cfun->calls_alloca |
7340 | && !cfun->stdarg) | |
adf39f8f AK |
7341 | return; |
7342 | ||
b3d31392 | 7343 | if (!TARGET_PACKED_STACK) |
63296cb1 | 7344 | cfun_frame_layout.frame_size += (STACK_POINTER_OFFSET |
38173d38 | 7345 | + crtl->outgoing_args_size |
adf39f8f AK |
7346 | + cfun_frame_layout.high_fprs * 8); |
7347 | else | |
7348 | { | |
66480e91 | 7349 | if (TARGET_BACKCHAIN) |
9602b6a1 | 7350 | cfun_frame_layout.frame_size += UNITS_PER_LONG; |
ea506297 | 7351 | |
f4aa3848 | 7352 | /* No alignment trouble here because f8-f15 are only saved under |
ea506297 | 7353 | 64 bit. */ |
adf39f8f AK |
7354 | cfun_frame_layout.f8_offset = (MIN (MIN (cfun_frame_layout.f0_offset, |
7355 | cfun_frame_layout.f4_offset), | |
7356 | cfun_frame_layout.gprs_offset) | |
7357 | - cfun_frame_layout.high_fprs * 8); | |
7358 | ||
7359 | cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8; | |
7360 | ||
7361 | for (i = 0; i < 8; i++) | |
7362 | if (cfun_fpr_bit_p (i)) | |
7363 | cfun_frame_layout.frame_size += 8; | |
f4aa3848 | 7364 | |
adf39f8f | 7365 | cfun_frame_layout.frame_size += cfun_gprs_save_area_size; |
f4aa3848 | 7366 | |
ea506297 AK |
7367 | /* If under 31 bit an odd number of gprs has to be saved we have to adjust |
7368 | the frame size to sustain 8 byte alignment of stack frames. */ | |
adf39f8f AK |
7369 | cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size + |
7370 | STACK_BOUNDARY / BITS_PER_UNIT - 1) | |
7371 | & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1)); | |
7372 | ||
38173d38 | 7373 | cfun_frame_layout.frame_size += crtl->outgoing_args_size; |
b767fc11 | 7374 | } |
4023fb28 UW |
7375 | } |
7376 | ||
91086990 UW |
7377 | /* Generate frame layout. Fills in register and frame data for the current |
7378 | function in cfun->machine. This routine can be called multiple times; | |
7379 | it will re-do the complete frame layout every time. */ | |
4023fb28 | 7380 | |
91086990 UW |
7381 | static void |
7382 | s390_init_frame_layout (void) | |
9db1d521 | 7383 | { |
91086990 UW |
7384 | HOST_WIDE_INT frame_size; |
7385 | int base_used; | |
7bcebb25 | 7386 | int clobbered_regs[16]; |
b767fc11 | 7387 | |
91086990 UW |
7388 | /* On S/390 machines, we may need to perform branch splitting, which |
7389 | will require both base and return address register. We have no | |
7390 | choice but to assume we're going to need them until right at the | |
7391 | end of the machine dependent reorg phase. */ | |
7392 | if (!TARGET_CPU_ZARCH) | |
7393 | cfun->machine->split_branches_pending_p = true; | |
7394 | ||
7395 | do | |
7396 | { | |
7397 | frame_size = cfun_frame_layout.frame_size; | |
7398 | ||
7399 | /* Try to predict whether we'll need the base register. */ | |
7400 | base_used = cfun->machine->split_branches_pending_p | |
e3b5732b | 7401 | || crtl->uses_const_pool |
20f04e65 AK |
7402 | || (!DISP_IN_RANGE (frame_size) |
7403 | && !CONST_OK_FOR_K (frame_size)); | |
91086990 UW |
7404 | |
7405 | /* Decide which register to use as literal pool base. In small | |
7406 | leaf functions, try to use an unused call-clobbered register | |
7407 | as base register to avoid save/restore overhead. */ | |
7408 | if (!base_used) | |
7409 | cfun->machine->base_reg = NULL_RTX; | |
6fb5fa3c | 7410 | else if (current_function_is_leaf && !df_regs_ever_live_p (5)) |
91086990 UW |
7411 | cfun->machine->base_reg = gen_rtx_REG (Pmode, 5); |
7412 | else | |
7413 | cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM); | |
adf39f8f | 7414 | |
7bcebb25 | 7415 | s390_register_info (clobbered_regs); |
91086990 UW |
7416 | s390_frame_info (); |
7417 | } | |
7418 | while (frame_size != cfun_frame_layout.frame_size); | |
9db1d521 HP |
7419 | } |
7420 | ||
91086990 UW |
7421 | /* Update frame layout. Recompute actual register save data based on |
7422 | current info and update regs_ever_live for the special registers. | |
7423 | May be called multiple times, but may never cause *more* registers | |
7424 | to be saved than s390_init_frame_layout allocated room for. */ | |
7425 | ||
7426 | static void | |
7427 | s390_update_frame_layout (void) | |
7428 | { | |
7bcebb25 | 7429 | int clobbered_regs[16]; |
91086990 | 7430 | |
7bcebb25 | 7431 | s390_register_info (clobbered_regs); |
91086990 | 7432 | |
f4aa3848 | 7433 | df_set_regs_ever_live (BASE_REGNUM, |
6fb5fa3c | 7434 | clobbered_regs[BASE_REGNUM] ? true : false); |
f4aa3848 | 7435 | df_set_regs_ever_live (RETURN_REGNUM, |
6fb5fa3c | 7436 | clobbered_regs[RETURN_REGNUM] ? true : false); |
f4aa3848 | 7437 | df_set_regs_ever_live (STACK_POINTER_REGNUM, |
6fb5fa3c | 7438 | clobbered_regs[STACK_POINTER_REGNUM] ? true : false); |
91086990 UW |
7439 | |
7440 | if (cfun->machine->base_reg) | |
6fb5fa3c | 7441 | df_set_regs_ever_live (REGNO (cfun->machine->base_reg), true); |
91086990 UW |
7442 | } |
7443 | ||
74aa8b4b AK |
7444 | /* Return true if it is legal to put a value with MODE into REGNO. */ |
7445 | ||
7446 | bool | |
7447 | s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) | |
7448 | { | |
7449 | switch (REGNO_REG_CLASS (regno)) | |
7450 | { | |
7451 | case FP_REGS: | |
7452 | if (REGNO_PAIR_OK (regno, mode)) | |
7453 | { | |
7454 | if (mode == SImode || mode == DImode) | |
7455 | return true; | |
7456 | ||
7457 | if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT) | |
7458 | return true; | |
7459 | } | |
7460 | break; | |
7461 | case ADDR_REGS: | |
7462 | if (FRAME_REGNO_P (regno) && mode == Pmode) | |
7463 | return true; | |
7464 | ||
7465 | /* fallthrough */ | |
7466 | case GENERAL_REGS: | |
7467 | if (REGNO_PAIR_OK (regno, mode)) | |
7468 | { | |
9602b6a1 | 7469 | if (TARGET_ZARCH |
4dc19cc0 | 7470 | || (mode != TFmode && mode != TCmode && mode != TDmode)) |
74aa8b4b | 7471 | return true; |
f4aa3848 | 7472 | } |
74aa8b4b AK |
7473 | break; |
7474 | case CC_REGS: | |
7475 | if (GET_MODE_CLASS (mode) == MODE_CC) | |
7476 | return true; | |
7477 | break; | |
7478 | case ACCESS_REGS: | |
7479 | if (REGNO_PAIR_OK (regno, mode)) | |
7480 | { | |
7481 | if (mode == SImode || mode == Pmode) | |
7482 | return true; | |
7483 | } | |
7484 | break; | |
7485 | default: | |
7486 | return false; | |
7487 | } | |
f4aa3848 | 7488 | |
74aa8b4b AK |
7489 | return false; |
7490 | } | |
7491 | ||
7633f08e UW |
7492 | /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */ |
7493 | ||
7494 | bool | |
7495 | s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg) | |
7496 | { | |
7497 | /* Once we've decided upon a register to use as base register, it must | |
7498 | no longer be used for any other purpose. */ | |
7499 | if (cfun->machine->base_reg) | |
7500 | if (REGNO (cfun->machine->base_reg) == old_reg | |
7501 | || REGNO (cfun->machine->base_reg) == new_reg) | |
7502 | return false; | |
7503 | ||
7504 | return true; | |
7505 | } | |
7506 | ||
74aa8b4b | 7507 | /* Maximum number of registers to represent a value of mode MODE |
0a2aaacc | 7508 | in a register of class RCLASS. */ |
74aa8b4b AK |
7509 | |
7510 | bool | |
0a2aaacc | 7511 | s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode) |
74aa8b4b | 7512 | { |
0a2aaacc | 7513 | switch (rclass) |
74aa8b4b AK |
7514 | { |
7515 | case FP_REGS: | |
7516 | if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) | |
7517 | return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8); | |
7518 | else | |
7519 | return (GET_MODE_SIZE (mode) + 8 - 1) / 8; | |
7520 | case ACCESS_REGS: | |
7521 | return (GET_MODE_SIZE (mode) + 4 - 1) / 4; | |
7522 | default: | |
7523 | break; | |
7524 | } | |
7525 | return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; | |
7526 | } | |
7527 | ||
91086990 UW |
7528 | /* Return true if register FROM can be eliminated via register TO. */ |
7529 | ||
7b5cbb57 AS |
7530 | static bool |
7531 | s390_can_eliminate (const int from, const int to) | |
91086990 | 7532 | { |
7633f08e UW |
7533 | /* On zSeries machines, we have not marked the base register as fixed. |
7534 | Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM. | |
7535 | If a function requires the base register, we say here that this | |
7536 | elimination cannot be performed. This will cause reload to free | |
7537 | up the base register (as if it were fixed). On the other hand, | |
7538 | if the current function does *not* require the base register, we | |
7539 | say here the elimination succeeds, which in turn allows reload | |
7540 | to allocate the base register for any other purpose. */ | |
7541 | if (from == BASE_REGNUM && to == BASE_REGNUM) | |
7542 | { | |
7543 | if (TARGET_CPU_ZARCH) | |
7544 | { | |
7545 | s390_init_frame_layout (); | |
7546 | return cfun->machine->base_reg == NULL_RTX; | |
7547 | } | |
7548 | ||
7549 | return false; | |
7550 | } | |
7551 | ||
7552 | /* Everything else must point into the stack frame. */ | |
91086990 UW |
7553 | gcc_assert (to == STACK_POINTER_REGNUM |
7554 | || to == HARD_FRAME_POINTER_REGNUM); | |
7555 | ||
7556 | gcc_assert (from == FRAME_POINTER_REGNUM | |
7557 | || from == ARG_POINTER_REGNUM | |
7558 | || from == RETURN_ADDRESS_POINTER_REGNUM); | |
7559 | ||
7560 | /* Make sure we actually saved the return address. */ | |
7561 | if (from == RETURN_ADDRESS_POINTER_REGNUM) | |
e3b5732b JH |
7562 | if (!crtl->calls_eh_return |
7563 | && !cfun->stdarg | |
91086990 UW |
7564 | && !cfun_frame_layout.save_return_addr_p) |
7565 | return false; | |
7566 | ||
7567 | return true; | |
7568 | } | |
7569 | ||
7570 | /* Return offset between register FROM and TO initially after prolog. */ | |
a38e09bc AK |
7571 | |
7572 | HOST_WIDE_INT | |
91086990 | 7573 | s390_initial_elimination_offset (int from, int to) |
a38e09bc | 7574 | { |
91086990 UW |
7575 | HOST_WIDE_INT offset; |
7576 | int index; | |
a38e09bc | 7577 | |
91086990 UW |
7578 | /* ??? Why are we called for non-eliminable pairs? */ |
7579 | if (!s390_can_eliminate (from, to)) | |
7580 | return 0; | |
7581 | ||
7582 | switch (from) | |
7583 | { | |
7584 | case FRAME_POINTER_REGNUM: | |
f4aa3848 | 7585 | offset = (get_frame_size() |
63296cb1 | 7586 | + STACK_POINTER_OFFSET |
38173d38 | 7587 | + crtl->outgoing_args_size); |
91086990 | 7588 | break; |
adf39f8f | 7589 | |
91086990 UW |
7590 | case ARG_POINTER_REGNUM: |
7591 | s390_init_frame_layout (); | |
7592 | offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET; | |
7593 | break; | |
7594 | ||
7595 | case RETURN_ADDRESS_POINTER_REGNUM: | |
7596 | s390_init_frame_layout (); | |
fb3712f6 | 7597 | index = RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot; |
91086990 UW |
7598 | gcc_assert (index >= 0); |
7599 | offset = cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset; | |
9602b6a1 | 7600 | offset += index * UNITS_PER_LONG; |
91086990 UW |
7601 | break; |
7602 | ||
7633f08e UW |
7603 | case BASE_REGNUM: |
7604 | offset = 0; | |
7605 | break; | |
7606 | ||
91086990 UW |
7607 | default: |
7608 | gcc_unreachable (); | |
7609 | } | |
7610 | ||
7611 | return offset; | |
a38e09bc AK |
7612 | } |
7613 | ||
4023fb28 | 7614 | /* Emit insn to save fpr REGNUM at offset OFFSET relative |
c7453384 | 7615 | to register BASE. Return generated insn. */ |
994fe660 | 7616 | |
9db1d521 | 7617 | static rtx |
9c808aad | 7618 | save_fpr (rtx base, int offset, int regnum) |
9db1d521 | 7619 | { |
4023fb28 UW |
7620 | rtx addr; |
7621 | addr = gen_rtx_MEM (DFmode, plus_constant (base, offset)); | |
dcc9eb26 AK |
7622 | |
7623 | if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG)) | |
7624 | set_mem_alias_set (addr, get_varargs_alias_set ()); | |
7625 | else | |
7626 | set_mem_alias_set (addr, get_frame_alias_set ()); | |
9db1d521 | 7627 | |
4023fb28 UW |
7628 | return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum)); |
7629 | } | |
9db1d521 | 7630 | |
4023fb28 | 7631 | /* Emit insn to restore fpr REGNUM from offset OFFSET relative |
c7453384 | 7632 | to register BASE. Return generated insn. */ |
9db1d521 | 7633 | |
4023fb28 | 7634 | static rtx |
9c808aad | 7635 | restore_fpr (rtx base, int offset, int regnum) |
4023fb28 UW |
7636 | { |
7637 | rtx addr; | |
7638 | addr = gen_rtx_MEM (DFmode, plus_constant (base, offset)); | |
dcc9eb26 | 7639 | set_mem_alias_set (addr, get_frame_alias_set ()); |
9db1d521 | 7640 | |
4023fb28 | 7641 | return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr); |
9db1d521 HP |
7642 | } |
7643 | ||
75707b28 JJ |
7644 | /* Return true if REGNO is a global register, but not one |
7645 | of the special ones that need to be saved/restored in anyway. */ | |
7646 | ||
7647 | static inline bool | |
7648 | global_not_special_regno_p (int regno) | |
7649 | { | |
7650 | return (global_regs[regno] | |
7651 | /* These registers are special and need to be | |
7652 | restored in any case. */ | |
7653 | && !(regno == STACK_POINTER_REGNUM | |
7654 | || regno == RETURN_REGNUM | |
7655 | || regno == BASE_REGNUM | |
7656 | || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM))); | |
7657 | } | |
7658 | ||
c3cc6b78 | 7659 | /* Generate insn to save registers FIRST to LAST into |
c7453384 | 7660 | the register save area located at offset OFFSET |
c3cc6b78 | 7661 | relative to register BASE. */ |
9db1d521 | 7662 | |
c3cc6b78 | 7663 | static rtx |
9c808aad | 7664 | save_gprs (rtx base, int offset, int first, int last) |
9db1d521 | 7665 | { |
c3cc6b78 UW |
7666 | rtx addr, insn, note; |
7667 | int i; | |
7668 | ||
adf39f8f | 7669 | addr = plus_constant (base, offset); |
c3cc6b78 | 7670 | addr = gen_rtx_MEM (Pmode, addr); |
dcc9eb26 AK |
7671 | |
7672 | set_mem_alias_set (addr, get_frame_alias_set ()); | |
c3cc6b78 UW |
7673 | |
7674 | /* Special-case single register. */ | |
7675 | if (first == last) | |
7676 | { | |
7677 | if (TARGET_64BIT) | |
7678 | insn = gen_movdi (addr, gen_rtx_REG (Pmode, first)); | |
7679 | else | |
7680 | insn = gen_movsi (addr, gen_rtx_REG (Pmode, first)); | |
7681 | ||
75707b28 JJ |
7682 | if (!global_not_special_regno_p (first)) |
7683 | RTX_FRAME_RELATED_P (insn) = 1; | |
c3cc6b78 UW |
7684 | return insn; |
7685 | } | |
7686 | ||
7687 | ||
7688 | insn = gen_store_multiple (addr, | |
7689 | gen_rtx_REG (Pmode, first), | |
7690 | GEN_INT (last - first + 1)); | |
7691 | ||
e3b5732b | 7692 | if (first <= 6 && cfun->stdarg) |
dcc9eb26 AK |
7693 | for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++) |
7694 | { | |
7695 | rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0); | |
f4aa3848 | 7696 | |
dcc9eb26 AK |
7697 | if (first + i <= 6) |
7698 | set_mem_alias_set (mem, get_varargs_alias_set ()); | |
7699 | } | |
c3cc6b78 UW |
7700 | |
7701 | /* We need to set the FRAME_RELATED flag on all SETs | |
7702 | inside the store-multiple pattern. | |
7703 | ||
7704 | However, we must not emit DWARF records for registers 2..5 | |
c7453384 | 7705 | if they are stored for use by variable arguments ... |
c3cc6b78 | 7706 | |
a4d05547 | 7707 | ??? Unfortunately, it is not enough to simply not the |
c3cc6b78 UW |
7708 | FRAME_RELATED flags for those SETs, because the first SET |
7709 | of the PARALLEL is always treated as if it had the flag | |
7710 | set, even if it does not. Therefore we emit a new pattern | |
7711 | without those registers as REG_FRAME_RELATED_EXPR note. */ | |
7712 | ||
75707b28 | 7713 | if (first >= 6 && !global_not_special_regno_p (first)) |
c3cc6b78 UW |
7714 | { |
7715 | rtx pat = PATTERN (insn); | |
7716 | ||
7717 | for (i = 0; i < XVECLEN (pat, 0); i++) | |
75707b28 JJ |
7718 | if (GET_CODE (XVECEXP (pat, 0, i)) == SET |
7719 | && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat, | |
7720 | 0, i))))) | |
c3cc6b78 UW |
7721 | RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1; |
7722 | ||
7723 | RTX_FRAME_RELATED_P (insn) = 1; | |
7724 | } | |
7725 | else if (last >= 6) | |
7726 | { | |
75707b28 JJ |
7727 | int start; |
7728 | ||
7729 | for (start = first >= 6 ? first : 6; start <= last; start++) | |
7730 | if (!global_not_special_regno_p (start)) | |
7731 | break; | |
7732 | ||
7733 | if (start > last) | |
7734 | return insn; | |
7735 | ||
9602b6a1 | 7736 | addr = plus_constant (base, offset + (start - first) * UNITS_PER_LONG); |
c7453384 | 7737 | note = gen_store_multiple (gen_rtx_MEM (Pmode, addr), |
75707b28 JJ |
7738 | gen_rtx_REG (Pmode, start), |
7739 | GEN_INT (last - start + 1)); | |
c3cc6b78 UW |
7740 | note = PATTERN (note); |
7741 | ||
bbbbb16a | 7742 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, note); |
c3cc6b78 UW |
7743 | |
7744 | for (i = 0; i < XVECLEN (note, 0); i++) | |
75707b28 JJ |
7745 | if (GET_CODE (XVECEXP (note, 0, i)) == SET |
7746 | && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note, | |
7747 | 0, i))))) | |
c3cc6b78 UW |
7748 | RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1; |
7749 | ||
7750 | RTX_FRAME_RELATED_P (insn) = 1; | |
7751 | } | |
7752 | ||
7753 | return insn; | |
4023fb28 | 7754 | } |
9db1d521 | 7755 | |
c3cc6b78 | 7756 | /* Generate insn to restore registers FIRST to LAST from |
c7453384 | 7757 | the register save area located at offset OFFSET |
c3cc6b78 | 7758 | relative to register BASE. */ |
9db1d521 | 7759 | |
c3cc6b78 | 7760 | static rtx |
9c808aad | 7761 | restore_gprs (rtx base, int offset, int first, int last) |
4023fb28 | 7762 | { |
c3cc6b78 UW |
7763 | rtx addr, insn; |
7764 | ||
adf39f8f | 7765 | addr = plus_constant (base, offset); |
c3cc6b78 | 7766 | addr = gen_rtx_MEM (Pmode, addr); |
dcc9eb26 | 7767 | set_mem_alias_set (addr, get_frame_alias_set ()); |
c3cc6b78 UW |
7768 | |
7769 | /* Special-case single register. */ | |
7770 | if (first == last) | |
7771 | { | |
7772 | if (TARGET_64BIT) | |
7773 | insn = gen_movdi (gen_rtx_REG (Pmode, first), addr); | |
7774 | else | |
7775 | insn = gen_movsi (gen_rtx_REG (Pmode, first), addr); | |
7776 | ||
7777 | return insn; | |
7778 | } | |
7779 | ||
7780 | insn = gen_load_multiple (gen_rtx_REG (Pmode, first), | |
7781 | addr, | |
7782 | GEN_INT (last - first + 1)); | |
7783 | return insn; | |
4023fb28 | 7784 | } |
9db1d521 | 7785 | |
585539a1 | 7786 | /* Return insn sequence to load the GOT register. */ |
fd7643fb UW |
7787 | |
7788 | static GTY(()) rtx got_symbol; | |
585539a1 UW |
7789 | rtx |
7790 | s390_load_got (void) | |
fd7643fb | 7791 | { |
585539a1 UW |
7792 | rtx insns; |
7793 | ||
fd7643fb UW |
7794 | if (!got_symbol) |
7795 | { | |
7796 | got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
7797 | SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL; | |
7798 | } | |
7799 | ||
585539a1 UW |
7800 | start_sequence (); |
7801 | ||
9e8327e3 | 7802 | if (TARGET_CPU_ZARCH) |
fd7643fb | 7803 | { |
585539a1 | 7804 | emit_move_insn (pic_offset_table_rtx, got_symbol); |
fd7643fb UW |
7805 | } |
7806 | else | |
7807 | { | |
585539a1 | 7808 | rtx offset; |
fd7643fb | 7809 | |
c7453384 | 7810 | offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol), |
fd7643fb UW |
7811 | UNSPEC_LTREL_OFFSET); |
7812 | offset = gen_rtx_CONST (Pmode, offset); | |
7813 | offset = force_const_mem (Pmode, offset); | |
7814 | ||
585539a1 | 7815 | emit_move_insn (pic_offset_table_rtx, offset); |
fd7643fb | 7816 | |
c7453384 | 7817 | offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)), |
fd7643fb UW |
7818 | UNSPEC_LTREL_BASE); |
7819 | offset = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, offset); | |
7820 | ||
585539a1 | 7821 | emit_move_insn (pic_offset_table_rtx, offset); |
fd7643fb | 7822 | } |
585539a1 UW |
7823 | |
7824 | insns = get_insns (); | |
7825 | end_sequence (); | |
7826 | return insns; | |
fd7643fb UW |
7827 | } |
7828 | ||
12959abe AK |
7829 | /* This ties together stack memory (MEM with an alias set of frame_alias_set) |
7830 | and the change to the stack pointer. */ | |
7831 | ||
7832 | static void | |
7833 | s390_emit_stack_tie (void) | |
7834 | { | |
7835 | rtx mem = gen_frame_mem (BLKmode, | |
7836 | gen_rtx_REG (Pmode, STACK_POINTER_REGNUM)); | |
7837 | ||
7838 | emit_insn (gen_stack_tie (mem)); | |
7839 | } | |
7840 | ||
4023fb28 | 7841 | /* Expand the prologue into a bunch of separate insns. */ |
9db1d521 | 7842 | |
4023fb28 | 7843 | void |
9c808aad | 7844 | s390_emit_prologue (void) |
4023fb28 | 7845 | { |
4023fb28 UW |
7846 | rtx insn, addr; |
7847 | rtx temp_reg; | |
2c153108 | 7848 | int i; |
adf39f8f AK |
7849 | int offset; |
7850 | int next_fpr = 0; | |
9db1d521 | 7851 | |
91086990 | 7852 | /* Complete frame layout. */ |
b767fc11 | 7853 | |
91086990 | 7854 | s390_update_frame_layout (); |
4023fb28 | 7855 | |
585539a1 UW |
7856 | /* Annotate all constant pool references to let the scheduler know |
7857 | they implicitly use the base register. */ | |
7858 | ||
7859 | push_topmost_sequence (); | |
7860 | ||
7861 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
7862 | if (INSN_P (insn)) | |
6fb5fa3c DB |
7863 | { |
7864 | annotate_constant_pool_refs (&PATTERN (insn)); | |
7865 | df_insn_rescan (insn); | |
7866 | } | |
585539a1 UW |
7867 | |
7868 | pop_topmost_sequence (); | |
7869 | ||
c7453384 EC |
7870 | /* Choose best register to use for temp use within prologue. |
7871 | See below for why TPF must use the register 1. */ | |
7872 | ||
f4aa3848 AK |
7873 | if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM) |
7874 | && !current_function_is_leaf | |
7bcebb25 | 7875 | && !TARGET_TPF_PROFILING) |
4023fb28 | 7876 | temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM); |
9db1d521 | 7877 | else |
4023fb28 | 7878 | temp_reg = gen_rtx_REG (Pmode, 1); |
9db1d521 | 7879 | |
4023fb28 | 7880 | /* Save call saved gprs. */ |
adf39f8f | 7881 | if (cfun_frame_layout.first_save_gpr != -1) |
2790879f | 7882 | { |
f4aa3848 AK |
7883 | insn = save_gprs (stack_pointer_rtx, |
7884 | cfun_frame_layout.gprs_offset + | |
9602b6a1 | 7885 | UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr |
fb3712f6 | 7886 | - cfun_frame_layout.first_save_gpr_slot), |
f4aa3848 | 7887 | cfun_frame_layout.first_save_gpr, |
2790879f AK |
7888 | cfun_frame_layout.last_save_gpr); |
7889 | emit_insn (insn); | |
7890 | } | |
4023fb28 | 7891 | |
5af2f3d3 | 7892 | /* Dummy insn to mark literal pool slot. */ |
c7453384 | 7893 | |
91086990 UW |
7894 | if (cfun->machine->base_reg) |
7895 | emit_insn (gen_main_pool (cfun->machine->base_reg)); | |
c7453384 | 7896 | |
adf39f8f | 7897 | offset = cfun_frame_layout.f0_offset; |
4023fb28 | 7898 | |
adf39f8f AK |
7899 | /* Save f0 and f2. */ |
7900 | for (i = 0; i < 2; i++) | |
7901 | { | |
7902 | if (cfun_fpr_bit_p (i)) | |
7903 | { | |
7904 | save_fpr (stack_pointer_rtx, offset, i + 16); | |
7905 | offset += 8; | |
7906 | } | |
b3d31392 | 7907 | else if (!TARGET_PACKED_STACK) |
adf39f8f AK |
7908 | offset += 8; |
7909 | } | |
9db1d521 | 7910 | |
adf39f8f AK |
7911 | /* Save f4 and f6. */ |
7912 | offset = cfun_frame_layout.f4_offset; | |
7913 | for (i = 2; i < 4; i++) | |
7914 | { | |
7915 | if (cfun_fpr_bit_p (i)) | |
4023fb28 | 7916 | { |
adf39f8f AK |
7917 | insn = save_fpr (stack_pointer_rtx, offset, i + 16); |
7918 | offset += 8; | |
7919 | ||
7920 | /* If f4 and f6 are call clobbered they are saved due to stdargs and | |
7921 | therefore are not frame related. */ | |
7922 | if (!call_really_used_regs[i + 16]) | |
7923 | RTX_FRAME_RELATED_P (insn) = 1; | |
4023fb28 | 7924 | } |
b3d31392 | 7925 | else if (!TARGET_PACKED_STACK) |
adf39f8f AK |
7926 | offset += 8; |
7927 | } | |
7928 | ||
b3d31392 | 7929 | if (TARGET_PACKED_STACK |
adf39f8f AK |
7930 | && cfun_save_high_fprs_p |
7931 | && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0) | |
7932 | { | |
7933 | offset = (cfun_frame_layout.f8_offset | |
7934 | + (cfun_frame_layout.high_fprs - 1) * 8); | |
7935 | ||
7936 | for (i = 15; i > 7 && offset >= 0; i--) | |
7937 | if (cfun_fpr_bit_p (i)) | |
7938 | { | |
7939 | insn = save_fpr (stack_pointer_rtx, offset, i + 16); | |
f4aa3848 | 7940 | |
adf39f8f AK |
7941 | RTX_FRAME_RELATED_P (insn) = 1; |
7942 | offset -= 8; | |
7943 | } | |
7944 | if (offset >= cfun_frame_layout.f8_offset) | |
7945 | next_fpr = i + 16; | |
7946 | } | |
f4aa3848 | 7947 | |
b3d31392 | 7948 | if (!TARGET_PACKED_STACK) |
adf39f8f | 7949 | next_fpr = cfun_save_high_fprs_p ? 31 : 0; |
9db1d521 | 7950 | |
5c779305 AK |
7951 | if (flag_stack_usage) |
7952 | current_function_static_stack_size = cfun_frame_layout.frame_size; | |
7953 | ||
4023fb28 | 7954 | /* Decrement stack pointer. */ |
9db1d521 | 7955 | |
adf39f8f | 7956 | if (cfun_frame_layout.frame_size > 0) |
4023fb28 | 7957 | { |
adf39f8f | 7958 | rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size); |
bbbbb16a | 7959 | rtx real_frame_off; |
9db1d521 | 7960 | |
d75f90f1 AK |
7961 | if (s390_stack_size) |
7962 | { | |
690e7b63 | 7963 | HOST_WIDE_INT stack_guard; |
d75f90f1 | 7964 | |
690e7b63 AK |
7965 | if (s390_stack_guard) |
7966 | stack_guard = s390_stack_guard; | |
d75f90f1 | 7967 | else |
690e7b63 AK |
7968 | { |
7969 | /* If no value for stack guard is provided the smallest power of 2 | |
7970 | larger than the current frame size is chosen. */ | |
7971 | stack_guard = 1; | |
7972 | while (stack_guard < cfun_frame_layout.frame_size) | |
7973 | stack_guard <<= 1; | |
7974 | } | |
d75f90f1 | 7975 | |
690e7b63 AK |
7976 | if (cfun_frame_layout.frame_size >= s390_stack_size) |
7977 | { | |
7978 | warning (0, "frame size of function %qs is " | |
7979 | HOST_WIDE_INT_PRINT_DEC | |
7980 | " bytes exceeding user provided stack limit of " | |
7981 | HOST_WIDE_INT_PRINT_DEC " bytes. " | |
7982 | "An unconditional trap is added.", | |
7983 | current_function_name(), cfun_frame_layout.frame_size, | |
7984 | s390_stack_size); | |
7985 | emit_insn (gen_trap ()); | |
7986 | } | |
7987 | else | |
7988 | { | |
a3e7e012 AK |
7989 | /* stack_guard has to be smaller than s390_stack_size. |
7990 | Otherwise we would emit an AND with zero which would | |
7991 | not match the test under mask pattern. */ | |
7992 | if (stack_guard >= s390_stack_size) | |
7993 | { | |
7994 | warning (0, "frame size of function %qs is " | |
7995 | HOST_WIDE_INT_PRINT_DEC | |
7996 | " bytes which is more than half the stack size. " | |
7997 | "The dynamic check would not be reliable. " | |
7998 | "No check emitted for this function.", | |
7999 | current_function_name(), | |
8000 | cfun_frame_layout.frame_size); | |
8001 | } | |
690e7b63 | 8002 | else |
a3e7e012 AK |
8003 | { |
8004 | HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1) | |
8005 | & ~(stack_guard - 1)); | |
8006 | ||
8007 | rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx, | |
8008 | GEN_INT (stack_check_mask)); | |
8009 | if (TARGET_64BIT) | |
8010 | emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode, | |
8011 | t, const0_rtx), | |
8012 | t, const0_rtx, const0_rtx)); | |
8013 | else | |
8014 | emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode, | |
8015 | t, const0_rtx), | |
8016 | t, const0_rtx, const0_rtx)); | |
8017 | } | |
690e7b63 | 8018 | } |
d75f90f1 AK |
8019 | } |
8020 | ||
f4aa3848 | 8021 | if (s390_warn_framesize > 0 |
d75f90f1 | 8022 | && cfun_frame_layout.frame_size >= s390_warn_framesize) |
f4aa3848 | 8023 | warning (0, "frame size of %qs is " HOST_WIDE_INT_PRINT_DEC " bytes", |
d75f90f1 AK |
8024 | current_function_name (), cfun_frame_layout.frame_size); |
8025 | ||
8026 | if (s390_warn_dynamicstack_p && cfun->calls_alloca) | |
d4ee4d25 | 8027 | warning (0, "%qs uses dynamic stack allocation", current_function_name ()); |
d75f90f1 | 8028 | |
4023fb28 | 8029 | /* Save incoming stack pointer into temp reg. */ |
66480e91 | 8030 | if (TARGET_BACKCHAIN || next_fpr) |
adf39f8f | 8031 | insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx)); |
c7453384 | 8032 | |
fae778eb | 8033 | /* Subtract frame size from stack pointer. */ |
4023fb28 | 8034 | |
d3632d41 UW |
8035 | if (DISP_IN_RANGE (INTVAL (frame_off))) |
8036 | { | |
c7453384 | 8037 | insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx, |
f4aa3848 | 8038 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, |
9c808aad | 8039 | frame_off)); |
d3632d41 UW |
8040 | insn = emit_insn (insn); |
8041 | } | |
8042 | else | |
8043 | { | |
b5c67a49 | 8044 | if (!CONST_OK_FOR_K (INTVAL (frame_off))) |
d3632d41 UW |
8045 | frame_off = force_const_mem (Pmode, frame_off); |
8046 | ||
8047 | insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off)); | |
585539a1 | 8048 | annotate_constant_pool_refs (&PATTERN (insn)); |
d3632d41 | 8049 | } |
4023fb28 | 8050 | |
4023fb28 | 8051 | RTX_FRAME_RELATED_P (insn) = 1; |
bbbbb16a ILT |
8052 | real_frame_off = GEN_INT (-cfun_frame_layout.frame_size); |
8053 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, | |
8054 | gen_rtx_SET (VOIDmode, stack_pointer_rtx, | |
8055 | gen_rtx_PLUS (Pmode, stack_pointer_rtx, | |
8056 | real_frame_off))); | |
4023fb28 UW |
8057 | |
8058 | /* Set backchain. */ | |
c7453384 | 8059 | |
66480e91 | 8060 | if (TARGET_BACKCHAIN) |
9db1d521 | 8061 | { |
adf39f8f | 8062 | if (cfun_frame_layout.backchain_offset) |
f4aa3848 AK |
8063 | addr = gen_rtx_MEM (Pmode, |
8064 | plus_constant (stack_pointer_rtx, | |
adf39f8f AK |
8065 | cfun_frame_layout.backchain_offset)); |
8066 | else | |
f4aa3848 | 8067 | addr = gen_rtx_MEM (Pmode, stack_pointer_rtx); |
dcc9eb26 | 8068 | set_mem_alias_set (addr, get_frame_alias_set ()); |
4023fb28 | 8069 | insn = emit_insn (gen_move_insn (addr, temp_reg)); |
9db1d521 | 8070 | } |
7d798969 | 8071 | |
8f4f502f | 8072 | /* If we support non-call exceptions (e.g. for Java), |
7d798969 UW |
8073 | we need to make sure the backchain pointer is set up |
8074 | before any possibly trapping memory access. */ | |
8f4f502f | 8075 | if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions) |
7d798969 UW |
8076 | { |
8077 | addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode)); | |
c41c1387 | 8078 | emit_clobber (addr); |
7d798969 | 8079 | } |
4023fb28 | 8080 | } |
9db1d521 | 8081 | |
4023fb28 | 8082 | /* Save fprs 8 - 15 (64 bit ABI). */ |
c7453384 | 8083 | |
adf39f8f | 8084 | if (cfun_save_high_fprs_p && next_fpr) |
4023fb28 | 8085 | { |
12959abe AK |
8086 | /* If the stack might be accessed through a different register |
8087 | we have to make sure that the stack pointer decrement is not | |
8088 | moved below the use of the stack slots. */ | |
8089 | s390_emit_stack_tie (); | |
8090 | ||
f4aa3848 | 8091 | insn = emit_insn (gen_add2_insn (temp_reg, |
adf39f8f AK |
8092 | GEN_INT (cfun_frame_layout.f8_offset))); |
8093 | ||
8094 | offset = 0; | |
9db1d521 | 8095 | |
adf39f8f AK |
8096 | for (i = 24; i <= next_fpr; i++) |
8097 | if (cfun_fpr_bit_p (i - 16)) | |
4023fb28 | 8098 | { |
c7453384 | 8099 | rtx addr = plus_constant (stack_pointer_rtx, |
adf39f8f AK |
8100 | cfun_frame_layout.frame_size |
8101 | + cfun_frame_layout.f8_offset | |
8102 | + offset); | |
f4aa3848 | 8103 | |
adf39f8f AK |
8104 | insn = save_fpr (temp_reg, offset, i); |
8105 | offset += 8; | |
4023fb28 | 8106 | RTX_FRAME_RELATED_P (insn) = 1; |
bbbbb16a ILT |
8107 | add_reg_note (insn, REG_FRAME_RELATED_EXPR, |
8108 | gen_rtx_SET (VOIDmode, | |
8109 | gen_rtx_MEM (DFmode, addr), | |
8110 | gen_rtx_REG (DFmode, i))); | |
4023fb28 UW |
8111 | } |
8112 | } | |
c7453384 | 8113 | |
4023fb28 | 8114 | /* Set frame pointer, if needed. */ |
c7453384 | 8115 | |
29742ba4 | 8116 | if (frame_pointer_needed) |
4023fb28 UW |
8117 | { |
8118 | insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); | |
8119 | RTX_FRAME_RELATED_P (insn) = 1; | |
8120 | } | |
9db1d521 | 8121 | |
4023fb28 | 8122 | /* Set up got pointer, if needed. */ |
c7453384 | 8123 | |
6fb5fa3c | 8124 | if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) |
585539a1 UW |
8125 | { |
8126 | rtx insns = s390_load_got (); | |
8127 | ||
8128 | for (insn = insns; insn; insn = NEXT_INSN (insn)) | |
6fb5fa3c | 8129 | annotate_constant_pool_refs (&PATTERN (insn)); |
585539a1 UW |
8130 | |
8131 | emit_insn (insns); | |
8132 | } | |
c7453384 | 8133 | |
3839e36a | 8134 | if (TARGET_TPF_PROFILING) |
c7453384 EC |
8135 | { |
8136 | /* Generate a BAS instruction to serve as a function | |
8137 | entry intercept to facilitate the use of tracing | |
2f7e5a0d EC |
8138 | algorithms located at the branch target. */ |
8139 | emit_insn (gen_prologue_tpf ()); | |
c7453384 EC |
8140 | |
8141 | /* Emit a blockage here so that all code | |
8142 | lies between the profiling mechanisms. */ | |
8143 | emit_insn (gen_blockage ()); | |
8144 | } | |
4023fb28 | 8145 | } |
9db1d521 | 8146 | |
b1c9bc51 | 8147 | /* Expand the epilogue into a bunch of separate insns. */ |
9db1d521 | 8148 | |
4023fb28 | 8149 | void |
ed9676cf | 8150 | s390_emit_epilogue (bool sibcall) |
4023fb28 | 8151 | { |
75707b28 | 8152 | rtx frame_pointer, return_reg, cfa_restores = NULL_RTX; |
5d4d885c | 8153 | int area_bottom, area_top, offset = 0; |
adf39f8f | 8154 | int next_offset; |
4023fb28 | 8155 | rtvec p; |
7333171f | 8156 | int i; |
9db1d521 | 8157 | |
3839e36a | 8158 | if (TARGET_TPF_PROFILING) |
c7453384 EC |
8159 | { |
8160 | ||
8161 | /* Generate a BAS instruction to serve as a function | |
8162 | entry intercept to facilitate the use of tracing | |
2f7e5a0d | 8163 | algorithms located at the branch target. */ |
c7453384 | 8164 | |
c7453384 EC |
8165 | /* Emit a blockage here so that all code |
8166 | lies between the profiling mechanisms. */ | |
8167 | emit_insn (gen_blockage ()); | |
8168 | ||
2f7e5a0d | 8169 | emit_insn (gen_epilogue_tpf ()); |
c7453384 EC |
8170 | } |
8171 | ||
4023fb28 | 8172 | /* Check whether to use frame or stack pointer for restore. */ |
9db1d521 | 8173 | |
f4aa3848 | 8174 | frame_pointer = (frame_pointer_needed |
adf39f8f | 8175 | ? hard_frame_pointer_rtx : stack_pointer_rtx); |
9db1d521 | 8176 | |
adf39f8f | 8177 | s390_frame_area (&area_bottom, &area_top); |
9db1d521 | 8178 | |
c7453384 | 8179 | /* Check whether we can access the register save area. |
4023fb28 | 8180 | If not, increment the frame pointer as required. */ |
9db1d521 | 8181 | |
4023fb28 UW |
8182 | if (area_top <= area_bottom) |
8183 | { | |
8184 | /* Nothing to restore. */ | |
8185 | } | |
adf39f8f AK |
8186 | else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom) |
8187 | && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1)) | |
4023fb28 UW |
8188 | { |
8189 | /* Area is in range. */ | |
adf39f8f | 8190 | offset = cfun_frame_layout.frame_size; |
4023fb28 UW |
8191 | } |
8192 | else | |
8193 | { | |
75707b28 | 8194 | rtx insn, frame_off, cfa; |
9db1d521 | 8195 | |
c7453384 | 8196 | offset = area_bottom < 0 ? -area_bottom : 0; |
adf39f8f | 8197 | frame_off = GEN_INT (cfun_frame_layout.frame_size - offset); |
9db1d521 | 8198 | |
75707b28 JJ |
8199 | cfa = gen_rtx_SET (VOIDmode, frame_pointer, |
8200 | gen_rtx_PLUS (Pmode, frame_pointer, frame_off)); | |
d3632d41 UW |
8201 | if (DISP_IN_RANGE (INTVAL (frame_off))) |
8202 | { | |
c7453384 | 8203 | insn = gen_rtx_SET (VOIDmode, frame_pointer, |
d3632d41 UW |
8204 | gen_rtx_PLUS (Pmode, frame_pointer, frame_off)); |
8205 | insn = emit_insn (insn); | |
8206 | } | |
8207 | else | |
8208 | { | |
b5c67a49 | 8209 | if (!CONST_OK_FOR_K (INTVAL (frame_off))) |
d3632d41 | 8210 | frame_off = force_const_mem (Pmode, frame_off); |
9db1d521 | 8211 | |
d3632d41 | 8212 | insn = emit_insn (gen_add2_insn (frame_pointer, frame_off)); |
585539a1 | 8213 | annotate_constant_pool_refs (&PATTERN (insn)); |
d3632d41 | 8214 | } |
75707b28 JJ |
8215 | add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa); |
8216 | RTX_FRAME_RELATED_P (insn) = 1; | |
4023fb28 | 8217 | } |
9db1d521 | 8218 | |
4023fb28 UW |
8219 | /* Restore call saved fprs. */ |
8220 | ||
8221 | if (TARGET_64BIT) | |
9db1d521 | 8222 | { |
adf39f8f AK |
8223 | if (cfun_save_high_fprs_p) |
8224 | { | |
8225 | next_offset = cfun_frame_layout.f8_offset; | |
8226 | for (i = 24; i < 32; i++) | |
8227 | { | |
8228 | if (cfun_fpr_bit_p (i - 16)) | |
8229 | { | |
8230 | restore_fpr (frame_pointer, | |
8231 | offset + next_offset, i); | |
75707b28 JJ |
8232 | cfa_restores |
8233 | = alloc_reg_note (REG_CFA_RESTORE, | |
8234 | gen_rtx_REG (DFmode, i), cfa_restores); | |
adf39f8f AK |
8235 | next_offset += 8; |
8236 | } | |
8237 | } | |
8238 | } | |
f4aa3848 | 8239 | |
9db1d521 HP |
8240 | } |
8241 | else | |
8242 | { | |
adf39f8f | 8243 | next_offset = cfun_frame_layout.f4_offset; |
7333171f | 8244 | for (i = 18; i < 20; i++) |
adf39f8f AK |
8245 | { |
8246 | if (cfun_fpr_bit_p (i - 16)) | |
8247 | { | |
8248 | restore_fpr (frame_pointer, | |
8249 | offset + next_offset, i); | |
75707b28 JJ |
8250 | cfa_restores |
8251 | = alloc_reg_note (REG_CFA_RESTORE, | |
8252 | gen_rtx_REG (DFmode, i), cfa_restores); | |
adf39f8f AK |
8253 | next_offset += 8; |
8254 | } | |
b3d31392 | 8255 | else if (!TARGET_PACKED_STACK) |
adf39f8f AK |
8256 | next_offset += 8; |
8257 | } | |
f4aa3848 | 8258 | |
4023fb28 | 8259 | } |
9db1d521 | 8260 | |
4023fb28 UW |
8261 | /* Return register. */ |
8262 | ||
c7453384 | 8263 | return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM); |
4023fb28 UW |
8264 | |
8265 | /* Restore call saved gprs. */ | |
8266 | ||
adf39f8f | 8267 | if (cfun_frame_layout.first_restore_gpr != -1) |
4023fb28 | 8268 | { |
c3cc6b78 | 8269 | rtx insn, addr; |
1447dc69 HP |
8270 | int i; |
8271 | ||
c7453384 | 8272 | /* Check for global register and save them |
1447dc69 HP |
8273 | to stack location from where they get restored. */ |
8274 | ||
adf39f8f AK |
8275 | for (i = cfun_frame_layout.first_restore_gpr; |
8276 | i <= cfun_frame_layout.last_restore_gpr; | |
1447dc69 HP |
8277 | i++) |
8278 | { | |
75707b28 | 8279 | if (global_not_special_regno_p (i)) |
1447dc69 | 8280 | { |
c7453384 | 8281 | addr = plus_constant (frame_pointer, |
f4aa3848 | 8282 | offset + cfun_frame_layout.gprs_offset |
fb3712f6 | 8283 | + (i - cfun_frame_layout.first_save_gpr_slot) |
9602b6a1 | 8284 | * UNITS_PER_LONG); |
1447dc69 | 8285 | addr = gen_rtx_MEM (Pmode, addr); |
dcc9eb26 | 8286 | set_mem_alias_set (addr, get_frame_alias_set ()); |
1447dc69 | 8287 | emit_move_insn (addr, gen_rtx_REG (Pmode, i)); |
c7453384 | 8288 | } |
75707b28 JJ |
8289 | else |
8290 | cfa_restores | |
8291 | = alloc_reg_note (REG_CFA_RESTORE, | |
8292 | gen_rtx_REG (Pmode, i), cfa_restores); | |
1447dc69 | 8293 | } |
4023fb28 | 8294 | |
ed9676cf | 8295 | if (! sibcall) |
9db1d521 | 8296 | { |
ed9676cf AK |
8297 | /* Fetch return address from stack before load multiple, |
8298 | this will do good for scheduling. */ | |
38899e29 | 8299 | |
adf39f8f AK |
8300 | if (cfun_frame_layout.save_return_addr_p |
8301 | || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM | |
8302 | && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM)) | |
ed9676cf AK |
8303 | { |
8304 | int return_regnum = find_unused_clobbered_reg(); | |
8305 | if (!return_regnum) | |
8306 | return_regnum = 4; | |
8307 | return_reg = gen_rtx_REG (Pmode, return_regnum); | |
38899e29 | 8308 | |
ed9676cf | 8309 | addr = plus_constant (frame_pointer, |
adf39f8f | 8310 | offset + cfun_frame_layout.gprs_offset |
f4aa3848 | 8311 | + (RETURN_REGNUM |
fb3712f6 | 8312 | - cfun_frame_layout.first_save_gpr_slot) |
9602b6a1 | 8313 | * UNITS_PER_LONG); |
ed9676cf | 8314 | addr = gen_rtx_MEM (Pmode, addr); |
dcc9eb26 | 8315 | set_mem_alias_set (addr, get_frame_alias_set ()); |
ed9676cf AK |
8316 | emit_move_insn (return_reg, addr); |
8317 | } | |
9db1d521 | 8318 | } |
4023fb28 | 8319 | |
adf39f8f AK |
8320 | insn = restore_gprs (frame_pointer, |
8321 | offset + cfun_frame_layout.gprs_offset | |
f4aa3848 | 8322 | + (cfun_frame_layout.first_restore_gpr |
fb3712f6 | 8323 | - cfun_frame_layout.first_save_gpr_slot) |
9602b6a1 | 8324 | * UNITS_PER_LONG, |
adf39f8f AK |
8325 | cfun_frame_layout.first_restore_gpr, |
8326 | cfun_frame_layout.last_restore_gpr); | |
75707b28 JJ |
8327 | insn = emit_insn (insn); |
8328 | REG_NOTES (insn) = cfa_restores; | |
8329 | add_reg_note (insn, REG_CFA_DEF_CFA, | |
8330 | plus_constant (stack_pointer_rtx, STACK_POINTER_OFFSET)); | |
8331 | RTX_FRAME_RELATED_P (insn) = 1; | |
4023fb28 | 8332 | } |
9db1d521 | 8333 | |
ed9676cf AK |
8334 | if (! sibcall) |
8335 | { | |
c7453384 | 8336 | |
ed9676cf | 8337 | /* Return to caller. */ |
38899e29 | 8338 | |
ed9676cf | 8339 | p = rtvec_alloc (2); |
38899e29 | 8340 | |
ed9676cf AK |
8341 | RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode); |
8342 | RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg); | |
8343 | emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p)); | |
8344 | } | |
9db1d521 HP |
8345 | } |
8346 | ||
9db1d521 | 8347 | |
c7453384 | 8348 | /* Return the size in bytes of a function argument of |
994fe660 UW |
8349 | type TYPE and/or mode MODE. At least one of TYPE or |
8350 | MODE must be specified. */ | |
9db1d521 HP |
8351 | |
8352 | static int | |
586de218 | 8353 | s390_function_arg_size (enum machine_mode mode, const_tree type) |
9db1d521 HP |
8354 | { |
8355 | if (type) | |
8356 | return int_size_in_bytes (type); | |
8357 | ||
d65f7478 | 8358 | /* No type info available for some library calls ... */ |
9db1d521 HP |
8359 | if (mode != BLKmode) |
8360 | return GET_MODE_SIZE (mode); | |
8361 | ||
8362 | /* If we have neither type nor mode, abort */ | |
8d933e31 | 8363 | gcc_unreachable (); |
9db1d521 HP |
8364 | } |
8365 | ||
82b1c974 UW |
8366 | /* Return true if a function argument of type TYPE and mode MODE |
8367 | is to be passed in a floating-point register, if available. */ | |
8368 | ||
8369 | static bool | |
3cb1da52 | 8370 | s390_function_arg_float (enum machine_mode mode, const_tree type) |
82b1c974 | 8371 | { |
8c17530e UW |
8372 | int size = s390_function_arg_size (mode, type); |
8373 | if (size > 8) | |
8374 | return false; | |
8375 | ||
82b1c974 UW |
8376 | /* Soft-float changes the ABI: no floating-point registers are used. */ |
8377 | if (TARGET_SOFT_FLOAT) | |
8378 | return false; | |
8379 | ||
8380 | /* No type info available for some library calls ... */ | |
8381 | if (!type) | |
4dc19cc0 | 8382 | return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode; |
82b1c974 UW |
8383 | |
8384 | /* The ABI says that record types with a single member are treated | |
8385 | just like that member would be. */ | |
8386 | while (TREE_CODE (type) == RECORD_TYPE) | |
8387 | { | |
8388 | tree field, single = NULL_TREE; | |
8389 | ||
910ad8de | 8390 | for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) |
82b1c974 UW |
8391 | { |
8392 | if (TREE_CODE (field) != FIELD_DECL) | |
8393 | continue; | |
8394 | ||
8395 | if (single == NULL_TREE) | |
8396 | single = TREE_TYPE (field); | |
8397 | else | |
8398 | return false; | |
8399 | } | |
8400 | ||
8401 | if (single == NULL_TREE) | |
8402 | return false; | |
8403 | else | |
8404 | type = single; | |
8405 | } | |
8406 | ||
8407 | return TREE_CODE (type) == REAL_TYPE; | |
8408 | } | |
8409 | ||
8c17530e UW |
8410 | /* Return true if a function argument of type TYPE and mode MODE |
8411 | is to be passed in an integer register, or a pair of integer | |
8412 | registers, if available. */ | |
8413 | ||
8414 | static bool | |
3cb1da52 | 8415 | s390_function_arg_integer (enum machine_mode mode, const_tree type) |
8c17530e UW |
8416 | { |
8417 | int size = s390_function_arg_size (mode, type); | |
8418 | if (size > 8) | |
8419 | return false; | |
8420 | ||
8421 | /* No type info available for some library calls ... */ | |
8422 | if (!type) | |
8423 | return GET_MODE_CLASS (mode) == MODE_INT | |
4dc19cc0 | 8424 | || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode)); |
8c17530e UW |
8425 | |
8426 | /* We accept small integral (and similar) types. */ | |
8427 | if (INTEGRAL_TYPE_P (type) | |
38899e29 | 8428 | || POINTER_TYPE_P (type) |
8c17530e UW |
8429 | || TREE_CODE (type) == OFFSET_TYPE |
8430 | || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE)) | |
8431 | return true; | |
8432 | ||
8433 | /* We also accept structs of size 1, 2, 4, 8 that are not | |
38899e29 | 8434 | passed in floating-point registers. */ |
8c17530e UW |
8435 | if (AGGREGATE_TYPE_P (type) |
8436 | && exact_log2 (size) >= 0 | |
8437 | && !s390_function_arg_float (mode, type)) | |
8438 | return true; | |
8439 | ||
8440 | return false; | |
8441 | } | |
8442 | ||
994fe660 UW |
8443 | /* Return 1 if a function argument of type TYPE and mode MODE |
8444 | is to be passed by reference. The ABI specifies that only | |
8445 | structures of size 1, 2, 4, or 8 bytes are passed by value, | |
8446 | all other structures (and complex numbers) are passed by | |
8447 | reference. */ | |
8448 | ||
8cd5a4e0 RH |
8449 | static bool |
8450 | s390_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED, | |
586de218 | 8451 | enum machine_mode mode, const_tree type, |
8cd5a4e0 | 8452 | bool named ATTRIBUTE_UNUSED) |
9db1d521 HP |
8453 | { |
8454 | int size = s390_function_arg_size (mode, type); | |
8c17530e UW |
8455 | if (size > 8) |
8456 | return true; | |
9db1d521 HP |
8457 | |
8458 | if (type) | |
8459 | { | |
8c17530e | 8460 | if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0) |
9db1d521 HP |
8461 | return 1; |
8462 | ||
8c17530e UW |
8463 | if (TREE_CODE (type) == COMPLEX_TYPE |
8464 | || TREE_CODE (type) == VECTOR_TYPE) | |
9db1d521 HP |
8465 | return 1; |
8466 | } | |
c7453384 | 8467 | |
9db1d521 | 8468 | return 0; |
9db1d521 HP |
8469 | } |
8470 | ||
8471 | /* Update the data in CUM to advance over an argument of mode MODE and | |
8472 | data type TYPE. (TYPE is null for libcalls where that information | |
994fe660 UW |
8473 | may not be available.). The boolean NAMED specifies whether the |
8474 | argument is a named argument (as opposed to an unnamed argument | |
8475 | matching an ellipsis). */ | |
9db1d521 | 8476 | |
3cb1da52 | 8477 | static void |
9c808aad | 8478 | s390_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, |
3cb1da52 | 8479 | const_tree type, bool named ATTRIBUTE_UNUSED) |
9db1d521 | 8480 | { |
8cd5a4e0 | 8481 | if (s390_function_arg_float (mode, type)) |
9db1d521 | 8482 | { |
82b1c974 | 8483 | cum->fprs += 1; |
9db1d521 | 8484 | } |
8c17530e | 8485 | else if (s390_function_arg_integer (mode, type)) |
9db1d521 HP |
8486 | { |
8487 | int size = s390_function_arg_size (mode, type); | |
9602b6a1 | 8488 | cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG); |
9db1d521 | 8489 | } |
8c17530e | 8490 | else |
8d933e31 | 8491 | gcc_unreachable (); |
9db1d521 HP |
8492 | } |
8493 | ||
994fe660 UW |
8494 | /* Define where to put the arguments to a function. |
8495 | Value is zero to push the argument on the stack, | |
8496 | or a hard register in which to store the argument. | |
8497 | ||
8498 | MODE is the argument's machine mode. | |
8499 | TYPE is the data type of the argument (as a tree). | |
8500 | This is null for libcalls where that information may | |
8501 | not be available. | |
8502 | CUM is a variable of type CUMULATIVE_ARGS which gives info about | |
8503 | the preceding args and about the function being called. | |
8504 | NAMED is nonzero if this argument is a named parameter | |
c7453384 | 8505 | (otherwise it is an extra parameter matching an ellipsis). |
994fe660 UW |
8506 | |
8507 | On S/390, we use general purpose registers 2 through 6 to | |
8508 | pass integer, pointer, and certain structure arguments, and | |
8509 | floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit) | |
8510 | to pass floating point arguments. All remaining arguments | |
8511 | are pushed to the stack. */ | |
9db1d521 | 8512 | |
3cb1da52 NF |
8513 | static rtx |
8514 | s390_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, | |
8515 | const_tree type, bool named ATTRIBUTE_UNUSED) | |
9db1d521 | 8516 | { |
82b1c974 | 8517 | if (s390_function_arg_float (mode, type)) |
9db1d521 | 8518 | { |
29a79fcf | 8519 | if (cum->fprs + 1 > FP_ARG_NUM_REG) |
9db1d521 HP |
8520 | return 0; |
8521 | else | |
f1c25d3b | 8522 | return gen_rtx_REG (mode, cum->fprs + 16); |
9db1d521 | 8523 | } |
8c17530e | 8524 | else if (s390_function_arg_integer (mode, type)) |
9db1d521 HP |
8525 | { |
8526 | int size = s390_function_arg_size (mode, type); | |
9602b6a1 | 8527 | int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG; |
9db1d521 | 8528 | |
29a79fcf | 8529 | if (cum->gprs + n_gprs > GP_ARG_NUM_REG) |
9db1d521 | 8530 | return 0; |
9602b6a1 | 8531 | else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG) |
f1c25d3b | 8532 | return gen_rtx_REG (mode, cum->gprs + 2); |
9602b6a1 AK |
8533 | else if (n_gprs == 2) |
8534 | { | |
8535 | rtvec p = rtvec_alloc (2); | |
8536 | ||
8537 | RTVEC_ELT (p, 0) | |
8538 | = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2), | |
8539 | const0_rtx); | |
8540 | RTVEC_ELT (p, 1) | |
8541 | = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3), | |
8542 | GEN_INT (4)); | |
8543 | ||
8544 | return gen_rtx_PARALLEL (mode, p); | |
8545 | } | |
9db1d521 | 8546 | } |
8c17530e UW |
8547 | |
8548 | /* After the real arguments, expand_call calls us once again | |
8549 | with a void_type_node type. Whatever we return here is | |
8550 | passed as operand 2 to the call expanders. | |
8551 | ||
8552 | We don't need this feature ... */ | |
8553 | else if (type == void_type_node) | |
8554 | return const0_rtx; | |
8555 | ||
8d933e31 | 8556 | gcc_unreachable (); |
8c17530e UW |
8557 | } |
8558 | ||
8559 | /* Return true if return values of type TYPE should be returned | |
8560 | in a memory buffer whose address is passed by the caller as | |
8561 | hidden first argument. */ | |
8562 | ||
8563 | static bool | |
586de218 | 8564 | s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED) |
8c17530e UW |
8565 | { |
8566 | /* We accept small integral (and similar) types. */ | |
8567 | if (INTEGRAL_TYPE_P (type) | |
38899e29 | 8568 | || POINTER_TYPE_P (type) |
8c17530e UW |
8569 | || TREE_CODE (type) == OFFSET_TYPE |
8570 | || TREE_CODE (type) == REAL_TYPE) | |
8571 | return int_size_in_bytes (type) > 8; | |
8572 | ||
8573 | /* Aggregates and similar constructs are always returned | |
8574 | in memory. */ | |
8575 | if (AGGREGATE_TYPE_P (type) | |
8576 | || TREE_CODE (type) == COMPLEX_TYPE | |
8577 | || TREE_CODE (type) == VECTOR_TYPE) | |
8578 | return true; | |
8579 | ||
8580 | /* ??? We get called on all sorts of random stuff from | |
8581 | aggregate_value_p. We can't abort, but it's not clear | |
8582 | what's safe to return. Pretend it's a struct I guess. */ | |
8583 | return true; | |
8584 | } | |
8585 | ||
cde0f3fd PB |
8586 | /* Function arguments and return values are promoted to word size. */ |
8587 | ||
8588 | static enum machine_mode | |
8589 | s390_promote_function_mode (const_tree type, enum machine_mode mode, | |
8590 | int *punsignedp, | |
8591 | const_tree fntype ATTRIBUTE_UNUSED, | |
8592 | int for_return ATTRIBUTE_UNUSED) | |
8593 | { | |
8594 | if (INTEGRAL_MODE_P (mode) | |
9602b6a1 | 8595 | && GET_MODE_SIZE (mode) < UNITS_PER_LONG) |
cde0f3fd PB |
8596 | { |
8597 | if (POINTER_TYPE_P (type)) | |
8598 | *punsignedp = POINTERS_EXTEND_UNSIGNED; | |
8599 | return Pmode; | |
8600 | } | |
8601 | ||
8602 | return mode; | |
8603 | } | |
8604 | ||
8c17530e UW |
8605 | /* Define where to return a (scalar) value of type TYPE. |
8606 | If TYPE is null, define where to return a (scalar) | |
8607 | value of mode MODE from a libcall. */ | |
8608 | ||
8609 | rtx | |
cde0f3fd | 8610 | s390_function_value (const_tree type, const_tree fn, enum machine_mode mode) |
8c17530e UW |
8611 | { |
8612 | if (type) | |
8613 | { | |
8df83eae | 8614 | int unsignedp = TYPE_UNSIGNED (type); |
cde0f3fd | 8615 | mode = promote_function_mode (type, TYPE_MODE (type), &unsignedp, fn, 1); |
8c17530e UW |
8616 | } |
8617 | ||
4dc19cc0 | 8618 | gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode)); |
8d933e31 | 8619 | gcc_assert (GET_MODE_SIZE (mode) <= 8); |
8c17530e | 8620 | |
4dc19cc0 | 8621 | if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode)) |
8c17530e | 8622 | return gen_rtx_REG (mode, 16); |
9602b6a1 AK |
8623 | else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG |
8624 | || UNITS_PER_LONG == UNITS_PER_WORD) | |
8c17530e | 8625 | return gen_rtx_REG (mode, 2); |
9602b6a1 AK |
8626 | else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG) |
8627 | { | |
8628 | rtvec p = rtvec_alloc (2); | |
8629 | ||
8630 | RTVEC_ELT (p, 0) | |
8631 | = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx); | |
8632 | RTVEC_ELT (p, 1) | |
8633 | = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4)); | |
8634 | ||
8635 | return gen_rtx_PARALLEL (mode, p); | |
8636 | } | |
8637 | ||
8638 | gcc_unreachable (); | |
9db1d521 HP |
8639 | } |
8640 | ||
8641 | ||
994fe660 UW |
8642 | /* Create and return the va_list datatype. |
8643 | ||
8644 | On S/390, va_list is an array type equivalent to | |
8645 | ||
8646 | typedef struct __va_list_tag | |
8647 | { | |
8648 | long __gpr; | |
8649 | long __fpr; | |
8650 | void *__overflow_arg_area; | |
8651 | void *__reg_save_area; | |
994fe660 UW |
8652 | } va_list[1]; |
8653 | ||
8654 | where __gpr and __fpr hold the number of general purpose | |
8655 | or floating point arguments used up to now, respectively, | |
c7453384 | 8656 | __overflow_arg_area points to the stack location of the |
994fe660 UW |
8657 | next argument passed on the stack, and __reg_save_area |
8658 | always points to the start of the register area in the | |
8659 | call frame of the current function. The function prologue | |
8660 | saves all registers used for argument passing into this | |
8661 | area if the function uses variable arguments. */ | |
9db1d521 | 8662 | |
c35d187f RH |
8663 | static tree |
8664 | s390_build_builtin_va_list (void) | |
9db1d521 HP |
8665 | { |
8666 | tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl; | |
8667 | ||
47798692 | 8668 | record = lang_hooks.types.make_type (RECORD_TYPE); |
9db1d521 HP |
8669 | |
8670 | type_decl = | |
4c4bde29 AH |
8671 | build_decl (BUILTINS_LOCATION, |
8672 | TYPE_DECL, get_identifier ("__va_list_tag"), record); | |
9db1d521 | 8673 | |
4c4bde29 AH |
8674 | f_gpr = build_decl (BUILTINS_LOCATION, |
8675 | FIELD_DECL, get_identifier ("__gpr"), | |
9db1d521 | 8676 | long_integer_type_node); |
4c4bde29 AH |
8677 | f_fpr = build_decl (BUILTINS_LOCATION, |
8678 | FIELD_DECL, get_identifier ("__fpr"), | |
9db1d521 | 8679 | long_integer_type_node); |
4c4bde29 AH |
8680 | f_ovf = build_decl (BUILTINS_LOCATION, |
8681 | FIELD_DECL, get_identifier ("__overflow_arg_area"), | |
9db1d521 | 8682 | ptr_type_node); |
4c4bde29 AH |
8683 | f_sav = build_decl (BUILTINS_LOCATION, |
8684 | FIELD_DECL, get_identifier ("__reg_save_area"), | |
9db1d521 HP |
8685 | ptr_type_node); |
8686 | ||
29a79fcf UW |
8687 | va_list_gpr_counter_field = f_gpr; |
8688 | va_list_fpr_counter_field = f_fpr; | |
8689 | ||
9db1d521 HP |
8690 | DECL_FIELD_CONTEXT (f_gpr) = record; |
8691 | DECL_FIELD_CONTEXT (f_fpr) = record; | |
8692 | DECL_FIELD_CONTEXT (f_ovf) = record; | |
8693 | DECL_FIELD_CONTEXT (f_sav) = record; | |
8694 | ||
0fd2eac2 | 8695 | TYPE_STUB_DECL (record) = type_decl; |
9db1d521 HP |
8696 | TYPE_NAME (record) = type_decl; |
8697 | TYPE_FIELDS (record) = f_gpr; | |
910ad8de NF |
8698 | DECL_CHAIN (f_gpr) = f_fpr; |
8699 | DECL_CHAIN (f_fpr) = f_ovf; | |
8700 | DECL_CHAIN (f_ovf) = f_sav; | |
9db1d521 HP |
8701 | |
8702 | layout_type (record); | |
8703 | ||
8704 | /* The correct type is an array type of one element. */ | |
8705 | return build_array_type (record, build_index_type (size_zero_node)); | |
8706 | } | |
8707 | ||
994fe660 | 8708 | /* Implement va_start by filling the va_list structure VALIST. |
6c535c69 ZW |
8709 | STDARG_P is always true, and ignored. |
8710 | NEXTARG points to the first anonymous stack argument. | |
994fe660 | 8711 | |
f710504c | 8712 | The following global variables are used to initialize |
994fe660 UW |
8713 | the va_list structure: |
8714 | ||
38173d38 | 8715 | crtl->args.info: |
994fe660 | 8716 | holds number of gprs and fprs used for named arguments. |
38173d38 | 8717 | crtl->args.arg_offset_rtx: |
994fe660 UW |
8718 | holds the offset of the first anonymous stack argument |
8719 | (relative to the virtual arg pointer). */ | |
9db1d521 | 8720 | |
d7bd8aeb | 8721 | static void |
9c808aad | 8722 | s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED) |
9db1d521 HP |
8723 | { |
8724 | HOST_WIDE_INT n_gpr, n_fpr; | |
8725 | int off; | |
8726 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
8727 | tree gpr, fpr, ovf, sav, t; | |
8728 | ||
8729 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); | |
910ad8de NF |
8730 | f_fpr = DECL_CHAIN (f_gpr); |
8731 | f_ovf = DECL_CHAIN (f_fpr); | |
8732 | f_sav = DECL_CHAIN (f_ovf); | |
9db1d521 | 8733 | |
86710a8b | 8734 | valist = build_simple_mem_ref (valist); |
47a25a46 RG |
8735 | gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
8736 | fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
8737 | ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
8738 | sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); | |
9db1d521 HP |
8739 | |
8740 | /* Count number of gp and fp argument registers used. */ | |
8741 | ||
38173d38 JH |
8742 | n_gpr = crtl->args.info.gprs; |
8743 | n_fpr = crtl->args.info.fprs; | |
9db1d521 | 8744 | |
29a79fcf UW |
8745 | if (cfun->va_list_gpr_size) |
8746 | { | |
726a989a RB |
8747 | t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr, |
8748 | build_int_cst (NULL_TREE, n_gpr)); | |
29a79fcf UW |
8749 | TREE_SIDE_EFFECTS (t) = 1; |
8750 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
8751 | } | |
9db1d521 | 8752 | |
29a79fcf UW |
8753 | if (cfun->va_list_fpr_size) |
8754 | { | |
726a989a | 8755 | t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr, |
47a25a46 | 8756 | build_int_cst (NULL_TREE, n_fpr)); |
29a79fcf UW |
8757 | TREE_SIDE_EFFECTS (t) = 1; |
8758 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
8759 | } | |
9db1d521 HP |
8760 | |
8761 | /* Find the overflow area. */ | |
29a79fcf UW |
8762 | if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG |
8763 | || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG) | |
8764 | { | |
8765 | t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); | |
9db1d521 | 8766 | |
38173d38 | 8767 | off = INTVAL (crtl->args.arg_offset_rtx); |
29a79fcf UW |
8768 | off = off < 0 ? 0 : off; |
8769 | if (TARGET_DEBUG_ARG) | |
8770 | fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n", | |
8771 | (int)n_gpr, (int)n_fpr, off); | |
9db1d521 | 8772 | |
5be014d5 | 8773 | t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t, size_int (off)); |
9db1d521 | 8774 | |
726a989a | 8775 | t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); |
29a79fcf UW |
8776 | TREE_SIDE_EFFECTS (t) = 1; |
8777 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
8778 | } | |
9db1d521 HP |
8779 | |
8780 | /* Find the register save area. */ | |
29a79fcf UW |
8781 | if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG) |
8782 | || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG)) | |
8783 | { | |
8784 | t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx); | |
5be014d5 | 8785 | t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t, |
9602b6a1 | 8786 | size_int (-RETURN_REGNUM * UNITS_PER_LONG)); |
f4aa3848 | 8787 | |
726a989a | 8788 | t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t); |
29a79fcf UW |
8789 | TREE_SIDE_EFFECTS (t) = 1; |
8790 | expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); | |
8791 | } | |
9db1d521 HP |
8792 | } |
8793 | ||
c7453384 | 8794 | /* Implement va_arg by updating the va_list structure |
994fe660 | 8795 | VALIST as required to retrieve an argument of type |
c7453384 EC |
8796 | TYPE, and returning that argument. |
8797 | ||
994fe660 | 8798 | Generates code equivalent to: |
c7453384 | 8799 | |
9db1d521 HP |
8800 | if (integral value) { |
8801 | if (size <= 4 && args.gpr < 5 || | |
c7453384 | 8802 | size > 4 && args.gpr < 4 ) |
9db1d521 HP |
8803 | ret = args.reg_save_area[args.gpr+8] |
8804 | else | |
8805 | ret = *args.overflow_arg_area++; | |
8806 | } else if (float value) { | |
8807 | if (args.fgpr < 2) | |
8808 | ret = args.reg_save_area[args.fpr+64] | |
8809 | else | |
8810 | ret = *args.overflow_arg_area++; | |
8811 | } else if (aggregate value) { | |
8812 | if (args.gpr < 5) | |
8813 | ret = *args.reg_save_area[args.gpr] | |
8814 | else | |
8815 | ret = **args.overflow_arg_area++; | |
8816 | } */ | |
8817 | ||
ab96de7e | 8818 | static tree |
f4aa3848 | 8819 | s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, |
726a989a | 8820 | gimple_seq *post_p ATTRIBUTE_UNUSED) |
9db1d521 HP |
8821 | { |
8822 | tree f_gpr, f_fpr, f_ovf, f_sav; | |
8823 | tree gpr, fpr, ovf, sav, reg, t, u; | |
8824 | int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg; | |
63694b5e | 8825 | tree lab_false, lab_over, addr; |
9db1d521 HP |
8826 | |
8827 | f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); | |
910ad8de NF |
8828 | f_fpr = DECL_CHAIN (f_gpr); |
8829 | f_ovf = DECL_CHAIN (f_fpr); | |
8830 | f_sav = DECL_CHAIN (f_ovf); | |
9db1d521 | 8831 | |
967af719 | 8832 | valist = build_va_arg_indirect_ref (valist); |
47a25a46 RG |
8833 | gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); |
8834 | fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); | |
47a25a46 | 8835 | sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); |
9db1d521 | 8836 | |
726a989a RB |
8837 | /* The tree for args* cannot be shared between gpr/fpr and ovf since |
8838 | both appear on a lhs. */ | |
8839 | valist = unshare_expr (valist); | |
8840 | ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); | |
8841 | ||
9db1d521 HP |
8842 | size = int_size_in_bytes (type); |
8843 | ||
8cd5a4e0 | 8844 | if (pass_by_reference (NULL, TYPE_MODE (type), type, false)) |
9db1d521 HP |
8845 | { |
8846 | if (TARGET_DEBUG_ARG) | |
8847 | { | |
8848 | fprintf (stderr, "va_arg: aggregate type"); | |
8849 | debug_tree (type); | |
8850 | } | |
8851 | ||
8852 | /* Aggregates are passed by reference. */ | |
8853 | indirect_p = 1; | |
8854 | reg = gpr; | |
8855 | n_reg = 1; | |
ea506297 | 8856 | |
b3d31392 | 8857 | /* kernel stack layout on 31 bit: It is assumed here that no padding |
ea506297 AK |
8858 | will be added by s390_frame_info because for va_args always an even |
8859 | number of gprs has to be saved r15-r2 = 14 regs. */ | |
9602b6a1 AK |
8860 | sav_ofs = 2 * UNITS_PER_LONG; |
8861 | sav_scale = UNITS_PER_LONG; | |
8862 | size = UNITS_PER_LONG; | |
29a79fcf | 8863 | max_reg = GP_ARG_NUM_REG - n_reg; |
9db1d521 | 8864 | } |
82b1c974 | 8865 | else if (s390_function_arg_float (TYPE_MODE (type), type)) |
9db1d521 HP |
8866 | { |
8867 | if (TARGET_DEBUG_ARG) | |
8868 | { | |
8869 | fprintf (stderr, "va_arg: float type"); | |
8870 | debug_tree (type); | |
8871 | } | |
8872 | ||
8873 | /* FP args go in FP registers, if present. */ | |
8874 | indirect_p = 0; | |
8875 | reg = fpr; | |
8876 | n_reg = 1; | |
9602b6a1 | 8877 | sav_ofs = 16 * UNITS_PER_LONG; |
9db1d521 | 8878 | sav_scale = 8; |
29a79fcf | 8879 | max_reg = FP_ARG_NUM_REG - n_reg; |
9db1d521 HP |
8880 | } |
8881 | else | |
8882 | { | |
8883 | if (TARGET_DEBUG_ARG) | |
8884 | { | |
8885 | fprintf (stderr, "va_arg: other type"); | |
8886 | debug_tree (type); | |
8887 | } | |
8888 | ||
8889 | /* Otherwise into GP registers. */ | |
8890 | indirect_p = 0; | |
8891 | reg = gpr; | |
9602b6a1 | 8892 | n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG; |
ea506297 | 8893 | |
b3d31392 AK |
8894 | /* kernel stack layout on 31 bit: It is assumed here that no padding |
8895 | will be added by s390_frame_info because for va_args always an even | |
8896 | number of gprs has to be saved r15-r2 = 14 regs. */ | |
9602b6a1 | 8897 | sav_ofs = 2 * UNITS_PER_LONG; |
c7453384 | 8898 | |
9602b6a1 AK |
8899 | if (size < UNITS_PER_LONG) |
8900 | sav_ofs += UNITS_PER_LONG - size; | |
9db1d521 | 8901 | |
9602b6a1 | 8902 | sav_scale = UNITS_PER_LONG; |
29a79fcf | 8903 | max_reg = GP_ARG_NUM_REG - n_reg; |
9db1d521 HP |
8904 | } |
8905 | ||
8906 | /* Pull the value out of the saved registers ... */ | |
8907 | ||
4c4bde29 AH |
8908 | lab_false = create_artificial_label (UNKNOWN_LOCATION); |
8909 | lab_over = create_artificial_label (UNKNOWN_LOCATION); | |
63694b5e | 8910 | addr = create_tmp_var (ptr_type_node, "addr"); |
9db1d521 | 8911 | |
6c6dd4bd | 8912 | t = fold_convert (TREE_TYPE (reg), size_int (max_reg)); |
63694b5e UW |
8913 | t = build2 (GT_EXPR, boolean_type_node, reg, t); |
8914 | u = build1 (GOTO_EXPR, void_type_node, lab_false); | |
8915 | t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE); | |
8916 | gimplify_and_add (t, pre_p); | |
9db1d521 | 8917 | |
f4aa3848 | 8918 | t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, |
5be014d5 | 8919 | size_int (sav_ofs)); |
f4aa3848 | 8920 | u = build2 (MULT_EXPR, TREE_TYPE (reg), reg, |
6c6dd4bd | 8921 | fold_convert (TREE_TYPE (reg), size_int (sav_scale))); |
5be014d5 | 8922 | t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, fold_convert (sizetype, u)); |
9db1d521 | 8923 | |
726a989a | 8924 | gimplify_assign (addr, t, pre_p); |
9db1d521 | 8925 | |
726a989a | 8926 | gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over)); |
9db1d521 | 8927 | |
726a989a | 8928 | gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false)); |
9db1d521 | 8929 | |
9db1d521 HP |
8930 | |
8931 | /* ... Otherwise out of the overflow area. */ | |
8932 | ||
ab96de7e | 8933 | t = ovf; |
9602b6a1 | 8934 | if (size < UNITS_PER_LONG) |
f4aa3848 | 8935 | t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, |
9602b6a1 | 8936 | size_int (UNITS_PER_LONG - size)); |
ab96de7e AS |
8937 | |
8938 | gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue); | |
8939 | ||
726a989a | 8940 | gimplify_assign (addr, t, pre_p); |
ab96de7e | 8941 | |
f4aa3848 | 8942 | t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, |
5be014d5 | 8943 | size_int (size)); |
726a989a | 8944 | gimplify_assign (ovf, t, pre_p); |
ab96de7e | 8945 | |
726a989a | 8946 | gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over)); |
ab96de7e AS |
8947 | |
8948 | ||
8949 | /* Increment register save count. */ | |
8950 | ||
8951 | u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg, | |
8952 | fold_convert (TREE_TYPE (reg), size_int (n_reg))); | |
8953 | gimplify_and_add (u, pre_p); | |
8954 | ||
8955 | if (indirect_p) | |
8956 | { | |
5b21f0f3 RG |
8957 | t = build_pointer_type_for_mode (build_pointer_type (type), |
8958 | ptr_mode, true); | |
ab96de7e AS |
8959 | addr = fold_convert (t, addr); |
8960 | addr = build_va_arg_indirect_ref (addr); | |
8961 | } | |
8962 | else | |
8963 | { | |
5b21f0f3 | 8964 | t = build_pointer_type_for_mode (type, ptr_mode, true); |
ab96de7e AS |
8965 | addr = fold_convert (t, addr); |
8966 | } | |
8967 | ||
8968 | return build_va_arg_indirect_ref (addr); | |
8969 | } | |
8970 | ||
8971 | ||
8972 | /* Builtins. */ | |
8973 | ||
8974 | enum s390_builtin | |
8975 | { | |
8976 | S390_BUILTIN_THREAD_POINTER, | |
8977 | S390_BUILTIN_SET_THREAD_POINTER, | |
8978 | ||
8979 | S390_BUILTIN_max | |
8980 | }; | |
8981 | ||
32e8bb8e | 8982 | static enum insn_code const code_for_builtin_64[S390_BUILTIN_max] = { |
ab96de7e AS |
8983 | CODE_FOR_get_tp_64, |
8984 | CODE_FOR_set_tp_64 | |
8985 | }; | |
8986 | ||
32e8bb8e | 8987 | static enum insn_code const code_for_builtin_31[S390_BUILTIN_max] = { |
ab96de7e AS |
8988 | CODE_FOR_get_tp_31, |
8989 | CODE_FOR_set_tp_31 | |
8990 | }; | |
8991 | ||
8992 | static void | |
8993 | s390_init_builtins (void) | |
8994 | { | |
8995 | tree ftype; | |
8996 | ||
8997 | ftype = build_function_type (ptr_type_node, void_list_node); | |
c79efc4d RÁE |
8998 | add_builtin_function ("__builtin_thread_pointer", ftype, |
8999 | S390_BUILTIN_THREAD_POINTER, BUILT_IN_MD, | |
9000 | NULL, NULL_TREE); | |
ab96de7e AS |
9001 | |
9002 | ftype = build_function_type_list (void_type_node, ptr_type_node, NULL_TREE); | |
c79efc4d RÁE |
9003 | add_builtin_function ("__builtin_set_thread_pointer", ftype, |
9004 | S390_BUILTIN_SET_THREAD_POINTER, BUILT_IN_MD, | |
9005 | NULL, NULL_TREE); | |
ab96de7e AS |
9006 | } |
9007 | ||
9008 | /* Expand an expression EXP that calls a built-in function, | |
9009 | with result going to TARGET if that's convenient | |
9010 | (and in mode MODE if that's convenient). | |
9011 | SUBTARGET may be used as the target for computing one of EXP's operands. | |
9012 | IGNORE is nonzero if the value is to be ignored. */ | |
9013 | ||
9014 | static rtx | |
9015 | s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, | |
9016 | enum machine_mode mode ATTRIBUTE_UNUSED, | |
9017 | int ignore ATTRIBUTE_UNUSED) | |
9018 | { | |
9019 | #define MAX_ARGS 2 | |
9020 | ||
32e8bb8e | 9021 | enum insn_code const *code_for_builtin = |
ab96de7e AS |
9022 | TARGET_64BIT ? code_for_builtin_64 : code_for_builtin_31; |
9023 | ||
5039610b | 9024 | tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); |
ab96de7e | 9025 | unsigned int fcode = DECL_FUNCTION_CODE (fndecl); |
ab96de7e AS |
9026 | enum insn_code icode; |
9027 | rtx op[MAX_ARGS], pat; | |
9028 | int arity; | |
9029 | bool nonvoid; | |
5039610b SL |
9030 | tree arg; |
9031 | call_expr_arg_iterator iter; | |
ab96de7e AS |
9032 | |
9033 | if (fcode >= S390_BUILTIN_max) | |
9034 | internal_error ("bad builtin fcode"); | |
9035 | icode = code_for_builtin[fcode]; | |
9036 | if (icode == 0) | |
9037 | internal_error ("bad builtin fcode"); | |
9038 | ||
9039 | nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node; | |
9040 | ||
5039610b SL |
9041 | arity = 0; |
9042 | FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) | |
ab96de7e AS |
9043 | { |
9044 | const struct insn_operand_data *insn_op; | |
9045 | ||
ab96de7e AS |
9046 | if (arg == error_mark_node) |
9047 | return NULL_RTX; | |
9048 | if (arity > MAX_ARGS) | |
9049 | return NULL_RTX; | |
9050 | ||
9051 | insn_op = &insn_data[icode].operand[arity + nonvoid]; | |
9052 | ||
bbbbb16a | 9053 | op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL); |
ab96de7e AS |
9054 | |
9055 | if (!(*insn_op->predicate) (op[arity], insn_op->mode)) | |
9056 | op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]); | |
5039610b | 9057 | arity++; |
ab96de7e AS |
9058 | } |
9059 | ||
9060 | if (nonvoid) | |
9061 | { | |
9062 | enum machine_mode tmode = insn_data[icode].operand[0].mode; | |
9063 | if (!target | |
9064 | || GET_MODE (target) != tmode | |
9065 | || !(*insn_data[icode].operand[0].predicate) (target, tmode)) | |
9066 | target = gen_reg_rtx (tmode); | |
9067 | } | |
9068 | ||
9069 | switch (arity) | |
9070 | { | |
9071 | case 0: | |
9072 | pat = GEN_FCN (icode) (target); | |
9073 | break; | |
9074 | case 1: | |
9075 | if (nonvoid) | |
9076 | pat = GEN_FCN (icode) (target, op[0]); | |
9077 | else | |
9078 | pat = GEN_FCN (icode) (op[0]); | |
9079 | break; | |
9080 | case 2: | |
9081 | pat = GEN_FCN (icode) (target, op[0], op[1]); | |
9082 | break; | |
9083 | default: | |
8d933e31 | 9084 | gcc_unreachable (); |
ab96de7e AS |
9085 | } |
9086 | if (!pat) | |
9087 | return NULL_RTX; | |
9088 | emit_insn (pat); | |
9089 | ||
9090 | if (nonvoid) | |
9091 | return target; | |
9092 | else | |
9093 | return const0_rtx; | |
9094 | } | |
9095 | ||
9096 | ||
9097 | /* Output assembly code for the trampoline template to | |
9098 | stdio stream FILE. | |
9099 | ||
9100 | On S/390, we use gpr 1 internally in the trampoline code; | |
9101 | gpr 0 is used to hold the static chain. */ | |
9102 | ||
b81ecf6f RH |
9103 | static void |
9104 | s390_asm_trampoline_template (FILE *file) | |
ab96de7e AS |
9105 | { |
9106 | rtx op[2]; | |
9107 | op[0] = gen_rtx_REG (Pmode, 0); | |
9108 | op[1] = gen_rtx_REG (Pmode, 1); | |
9109 | ||
9110 | if (TARGET_64BIT) | |
9111 | { | |
9112 | output_asm_insn ("basr\t%1,0", op); | |
9113 | output_asm_insn ("lmg\t%0,%1,14(%1)", op); | |
9114 | output_asm_insn ("br\t%1", op); | |
9115 | ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10)); | |
9116 | } | |
9117 | else | |
9118 | { | |
9119 | output_asm_insn ("basr\t%1,0", op); | |
9120 | output_asm_insn ("lm\t%0,%1,6(%1)", op); | |
9121 | output_asm_insn ("br\t%1", op); | |
9122 | ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8)); | |
9123 | } | |
9124 | } | |
9125 | ||
9126 | /* Emit RTL insns to initialize the variable parts of a trampoline. | |
9127 | FNADDR is an RTX for the address of the function's pure code. | |
9128 | CXT is an RTX for the static chain value for the function. */ | |
9129 | ||
b81ecf6f RH |
9130 | static void |
9131 | s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt) | |
ab96de7e | 9132 | { |
b81ecf6f RH |
9133 | rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); |
9134 | rtx mem; | |
3a892e44 | 9135 | |
b81ecf6f RH |
9136 | emit_block_move (m_tramp, assemble_trampoline_template (), |
9137 | GEN_INT (2*UNITS_PER_WORD), BLOCK_OP_NORMAL); | |
9138 | ||
9139 | mem = adjust_address (m_tramp, Pmode, 2*UNITS_PER_WORD); | |
9140 | emit_move_insn (mem, cxt); | |
9141 | mem = adjust_address (m_tramp, Pmode, 3*UNITS_PER_WORD); | |
9142 | emit_move_insn (mem, fnaddr); | |
ab96de7e AS |
9143 | } |
9144 | ||
ab96de7e AS |
9145 | /* Output assembler code to FILE to increment profiler label # LABELNO |
9146 | for profiling a function entry. */ | |
9147 | ||
9148 | void | |
9149 | s390_function_profiler (FILE *file, int labelno) | |
9150 | { | |
9151 | rtx op[7]; | |
9152 | ||
9153 | char label[128]; | |
9154 | ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno); | |
9155 | ||
9156 | fprintf (file, "# function profiler \n"); | |
9157 | ||
9158 | op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM); | |
9159 | op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); | |
9602b6a1 | 9160 | op[1] = gen_rtx_MEM (Pmode, plus_constant (op[1], UNITS_PER_LONG)); |
ab96de7e AS |
9161 | |
9162 | op[2] = gen_rtx_REG (Pmode, 1); | |
9163 | op[3] = gen_rtx_SYMBOL_REF (Pmode, label); | |
9164 | SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL; | |
9165 | ||
9166 | op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount"); | |
9167 | if (flag_pic) | |
9168 | { | |
9169 | op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT); | |
9170 | op[4] = gen_rtx_CONST (Pmode, op[4]); | |
9171 | } | |
9172 | ||
9173 | if (TARGET_64BIT) | |
9174 | { | |
9175 | output_asm_insn ("stg\t%0,%1", op); | |
9176 | output_asm_insn ("larl\t%2,%3", op); | |
9177 | output_asm_insn ("brasl\t%0,%4", op); | |
9178 | output_asm_insn ("lg\t%0,%1", op); | |
9179 | } | |
9180 | else if (!flag_pic) | |
9181 | { | |
9182 | op[6] = gen_label_rtx (); | |
9183 | ||
9184 | output_asm_insn ("st\t%0,%1", op); | |
9185 | output_asm_insn ("bras\t%2,%l6", op); | |
9186 | output_asm_insn (".long\t%4", op); | |
9187 | output_asm_insn (".long\t%3", op); | |
9188 | targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6])); | |
9189 | output_asm_insn ("l\t%0,0(%2)", op); | |
9190 | output_asm_insn ("l\t%2,4(%2)", op); | |
9191 | output_asm_insn ("basr\t%0,%0", op); | |
9192 | output_asm_insn ("l\t%0,%1", op); | |
9193 | } | |
9194 | else | |
9195 | { | |
9196 | op[5] = gen_label_rtx (); | |
9197 | op[6] = gen_label_rtx (); | |
9198 | ||
9199 | output_asm_insn ("st\t%0,%1", op); | |
9200 | output_asm_insn ("bras\t%2,%l6", op); | |
9201 | targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5])); | |
9202 | output_asm_insn (".long\t%4-%l5", op); | |
9203 | output_asm_insn (".long\t%3-%l5", op); | |
9204 | targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6])); | |
9205 | output_asm_insn ("lr\t%0,%2", op); | |
9206 | output_asm_insn ("a\t%0,0(%2)", op); | |
9207 | output_asm_insn ("a\t%2,4(%2)", op); | |
9208 | output_asm_insn ("basr\t%0,%0", op); | |
9209 | output_asm_insn ("l\t%0,%1", op); | |
9210 | } | |
9211 | } | |
9212 | ||
9213 | /* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF | |
9214 | into its SYMBOL_REF_FLAGS. */ | |
9215 | ||
9216 | static void | |
9217 | s390_encode_section_info (tree decl, rtx rtl, int first) | |
9218 | { | |
9219 | default_encode_section_info (decl, rtl, first); | |
9220 | ||
963fc8d0 AK |
9221 | if (TREE_CODE (decl) == VAR_DECL) |
9222 | { | |
9223 | /* If a variable has a forced alignment to < 2 bytes, mark it | |
9224 | with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL | |
9225 | operand. */ | |
9226 | if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16) | |
9227 | SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1; | |
9228 | if (!DECL_SIZE (decl) | |
9229 | || !DECL_ALIGN (decl) | |
9230 | || !host_integerp (DECL_SIZE (decl), 0) | |
9231 | || (DECL_ALIGN (decl) <= 64 | |
9232 | && DECL_ALIGN (decl) != tree_low_cst (DECL_SIZE (decl), 0))) | |
9233 | SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED; | |
9234 | } | |
9235 | ||
9236 | /* Literal pool references don't have a decl so they are handled | |
9237 | differently here. We rely on the information in the MEM_ALIGN | |
9238 | entry to decide upon natural alignment. */ | |
9239 | if (MEM_P (rtl) | |
9240 | && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF | |
9241 | && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0)) | |
9242 | && (MEM_ALIGN (rtl) == 0 | |
35fcb6ba | 9243 | || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0 |
963fc8d0 AK |
9244 | || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl)))) |
9245 | SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED; | |
ab96de7e AS |
9246 | } |
9247 | ||
9248 | /* Output thunk to FILE that implements a C++ virtual function call (with | |
9249 | multiple inheritance) to FUNCTION. The thunk adjusts the this pointer | |
9250 | by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment | |
9251 | stored at VCALL_OFFSET in the vtable whose address is located at offset 0 | |
9252 | relative to the resulting this pointer. */ | |
9253 | ||
9254 | static void | |
9255 | s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, | |
9256 | HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, | |
9257 | tree function) | |
9258 | { | |
9259 | rtx op[10]; | |
9260 | int nonlocal = 0; | |
9261 | ||
81ef7e24 JJ |
9262 | /* Make sure unwind info is emitted for the thunk if needed. */ |
9263 | final_start_function (emit_barrier (), file, 1); | |
9264 | ||
ab96de7e AS |
9265 | /* Operand 0 is the target function. */ |
9266 | op[0] = XEXP (DECL_RTL (function), 0); | |
9267 | if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0])) | |
9268 | { | |
9269 | nonlocal = 1; | |
9270 | op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]), | |
9271 | TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT); | |
9272 | op[0] = gen_rtx_CONST (Pmode, op[0]); | |
9273 | } | |
9274 | ||
9275 | /* Operand 1 is the 'this' pointer. */ | |
9276 | if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) | |
9277 | op[1] = gen_rtx_REG (Pmode, 3); | |
9278 | else | |
9279 | op[1] = gen_rtx_REG (Pmode, 2); | |
9280 | ||
9281 | /* Operand 2 is the delta. */ | |
9282 | op[2] = GEN_INT (delta); | |
9283 | ||
9284 | /* Operand 3 is the vcall_offset. */ | |
9285 | op[3] = GEN_INT (vcall_offset); | |
9286 | ||
9287 | /* Operand 4 is the temporary register. */ | |
9288 | op[4] = gen_rtx_REG (Pmode, 1); | |
9289 | ||
9290 | /* Operands 5 to 8 can be used as labels. */ | |
9291 | op[5] = NULL_RTX; | |
9292 | op[6] = NULL_RTX; | |
9293 | op[7] = NULL_RTX; | |
9294 | op[8] = NULL_RTX; | |
9295 | ||
9296 | /* Operand 9 can be used for temporary register. */ | |
9297 | op[9] = NULL_RTX; | |
9298 | ||
9299 | /* Generate code. */ | |
9300 | if (TARGET_64BIT) | |
9301 | { | |
9302 | /* Setup literal pool pointer if required. */ | |
9303 | if ((!DISP_IN_RANGE (delta) | |
ec24698e UW |
9304 | && !CONST_OK_FOR_K (delta) |
9305 | && !CONST_OK_FOR_Os (delta)) | |
ab96de7e | 9306 | || (!DISP_IN_RANGE (vcall_offset) |
ec24698e UW |
9307 | && !CONST_OK_FOR_K (vcall_offset) |
9308 | && !CONST_OK_FOR_Os (vcall_offset))) | |
ab96de7e AS |
9309 | { |
9310 | op[5] = gen_label_rtx (); | |
9311 | output_asm_insn ("larl\t%4,%5", op); | |
9312 | } | |
9313 | ||
9314 | /* Add DELTA to this pointer. */ | |
9315 | if (delta) | |
9316 | { | |
b5c67a49 | 9317 | if (CONST_OK_FOR_J (delta)) |
ab96de7e AS |
9318 | output_asm_insn ("la\t%1,%2(%1)", op); |
9319 | else if (DISP_IN_RANGE (delta)) | |
9320 | output_asm_insn ("lay\t%1,%2(%1)", op); | |
b5c67a49 | 9321 | else if (CONST_OK_FOR_K (delta)) |
ab96de7e | 9322 | output_asm_insn ("aghi\t%1,%2", op); |
ec24698e UW |
9323 | else if (CONST_OK_FOR_Os (delta)) |
9324 | output_asm_insn ("agfi\t%1,%2", op); | |
ab96de7e AS |
9325 | else |
9326 | { | |
9327 | op[6] = gen_label_rtx (); | |
9328 | output_asm_insn ("agf\t%1,%6-%5(%4)", op); | |
9329 | } | |
9330 | } | |
9331 | ||
9332 | /* Perform vcall adjustment. */ | |
9333 | if (vcall_offset) | |
9334 | { | |
9335 | if (DISP_IN_RANGE (vcall_offset)) | |
9336 | { | |
9337 | output_asm_insn ("lg\t%4,0(%1)", op); | |
9338 | output_asm_insn ("ag\t%1,%3(%4)", op); | |
9339 | } | |
b5c67a49 | 9340 | else if (CONST_OK_FOR_K (vcall_offset)) |
ab96de7e AS |
9341 | { |
9342 | output_asm_insn ("lghi\t%4,%3", op); | |
9343 | output_asm_insn ("ag\t%4,0(%1)", op); | |
9344 | output_asm_insn ("ag\t%1,0(%4)", op); | |
9345 | } | |
ec24698e UW |
9346 | else if (CONST_OK_FOR_Os (vcall_offset)) |
9347 | { | |
9348 | output_asm_insn ("lgfi\t%4,%3", op); | |
9349 | output_asm_insn ("ag\t%4,0(%1)", op); | |
9350 | output_asm_insn ("ag\t%1,0(%4)", op); | |
9351 | } | |
ab96de7e AS |
9352 | else |
9353 | { | |
9354 | op[7] = gen_label_rtx (); | |
9355 | output_asm_insn ("llgf\t%4,%7-%5(%4)", op); | |
9356 | output_asm_insn ("ag\t%4,0(%1)", op); | |
9357 | output_asm_insn ("ag\t%1,0(%4)", op); | |
9358 | } | |
9359 | } | |
9360 | ||
9361 | /* Jump to target. */ | |
9362 | output_asm_insn ("jg\t%0", op); | |
9363 | ||
9364 | /* Output literal pool if required. */ | |
9365 | if (op[5]) | |
9366 | { | |
9367 | output_asm_insn (".align\t4", op); | |
9368 | targetm.asm_out.internal_label (file, "L", | |
9369 | CODE_LABEL_NUMBER (op[5])); | |
9370 | } | |
9371 | if (op[6]) | |
9372 | { | |
9373 | targetm.asm_out.internal_label (file, "L", | |
9374 | CODE_LABEL_NUMBER (op[6])); | |
9375 | output_asm_insn (".long\t%2", op); | |
9376 | } | |
9377 | if (op[7]) | |
9378 | { | |
9379 | targetm.asm_out.internal_label (file, "L", | |
9380 | CODE_LABEL_NUMBER (op[7])); | |
9381 | output_asm_insn (".long\t%3", op); | |
9382 | } | |
9383 | } | |
9384 | else | |
9385 | { | |
9386 | /* Setup base pointer if required. */ | |
9387 | if (!vcall_offset | |
9388 | || (!DISP_IN_RANGE (delta) | |
ec24698e UW |
9389 | && !CONST_OK_FOR_K (delta) |
9390 | && !CONST_OK_FOR_Os (delta)) | |
ab96de7e | 9391 | || (!DISP_IN_RANGE (delta) |
ec24698e UW |
9392 | && !CONST_OK_FOR_K (vcall_offset) |
9393 | && !CONST_OK_FOR_Os (vcall_offset))) | |
ab96de7e AS |
9394 | { |
9395 | op[5] = gen_label_rtx (); | |
9396 | output_asm_insn ("basr\t%4,0", op); | |
9397 | targetm.asm_out.internal_label (file, "L", | |
9398 | CODE_LABEL_NUMBER (op[5])); | |
9399 | } | |
9400 | ||
9401 | /* Add DELTA to this pointer. */ | |
9402 | if (delta) | |
9403 | { | |
b5c67a49 | 9404 | if (CONST_OK_FOR_J (delta)) |
ab96de7e AS |
9405 | output_asm_insn ("la\t%1,%2(%1)", op); |
9406 | else if (DISP_IN_RANGE (delta)) | |
9407 | output_asm_insn ("lay\t%1,%2(%1)", op); | |
b5c67a49 | 9408 | else if (CONST_OK_FOR_K (delta)) |
ab96de7e | 9409 | output_asm_insn ("ahi\t%1,%2", op); |
ec24698e UW |
9410 | else if (CONST_OK_FOR_Os (delta)) |
9411 | output_asm_insn ("afi\t%1,%2", op); | |
ab96de7e AS |
9412 | else |
9413 | { | |
9414 | op[6] = gen_label_rtx (); | |
9415 | output_asm_insn ("a\t%1,%6-%5(%4)", op); | |
9416 | } | |
9417 | } | |
9418 | ||
9419 | /* Perform vcall adjustment. */ | |
9420 | if (vcall_offset) | |
9421 | { | |
b5c67a49 | 9422 | if (CONST_OK_FOR_J (vcall_offset)) |
ab96de7e | 9423 | { |
c4d50129 | 9424 | output_asm_insn ("l\t%4,0(%1)", op); |
ab96de7e AS |
9425 | output_asm_insn ("a\t%1,%3(%4)", op); |
9426 | } | |
9427 | else if (DISP_IN_RANGE (vcall_offset)) | |
9428 | { | |
c4d50129 | 9429 | output_asm_insn ("l\t%4,0(%1)", op); |
ab96de7e AS |
9430 | output_asm_insn ("ay\t%1,%3(%4)", op); |
9431 | } | |
b5c67a49 | 9432 | else if (CONST_OK_FOR_K (vcall_offset)) |
ab96de7e AS |
9433 | { |
9434 | output_asm_insn ("lhi\t%4,%3", op); | |
9435 | output_asm_insn ("a\t%4,0(%1)", op); | |
9436 | output_asm_insn ("a\t%1,0(%4)", op); | |
9437 | } | |
ec24698e UW |
9438 | else if (CONST_OK_FOR_Os (vcall_offset)) |
9439 | { | |
9440 | output_asm_insn ("iilf\t%4,%3", op); | |
9441 | output_asm_insn ("a\t%4,0(%1)", op); | |
9442 | output_asm_insn ("a\t%1,0(%4)", op); | |
9443 | } | |
ab96de7e AS |
9444 | else |
9445 | { | |
9446 | op[7] = gen_label_rtx (); | |
9447 | output_asm_insn ("l\t%4,%7-%5(%4)", op); | |
9448 | output_asm_insn ("a\t%4,0(%1)", op); | |
9449 | output_asm_insn ("a\t%1,0(%4)", op); | |
9450 | } | |
9db1d521 | 9451 | |
ab96de7e AS |
9452 | /* We had to clobber the base pointer register. |
9453 | Re-setup the base pointer (with a different base). */ | |
9454 | op[5] = gen_label_rtx (); | |
9455 | output_asm_insn ("basr\t%4,0", op); | |
9456 | targetm.asm_out.internal_label (file, "L", | |
9457 | CODE_LABEL_NUMBER (op[5])); | |
9458 | } | |
9db1d521 | 9459 | |
ab96de7e AS |
9460 | /* Jump to target. */ |
9461 | op[8] = gen_label_rtx (); | |
9db1d521 | 9462 | |
ab96de7e AS |
9463 | if (!flag_pic) |
9464 | output_asm_insn ("l\t%4,%8-%5(%4)", op); | |
9465 | else if (!nonlocal) | |
9466 | output_asm_insn ("a\t%4,%8-%5(%4)", op); | |
9467 | /* We cannot call through .plt, since .plt requires %r12 loaded. */ | |
9468 | else if (flag_pic == 1) | |
9469 | { | |
9470 | output_asm_insn ("a\t%4,%8-%5(%4)", op); | |
9471 | output_asm_insn ("l\t%4,%0(%4)", op); | |
9472 | } | |
9473 | else if (flag_pic == 2) | |
9474 | { | |
9475 | op[9] = gen_rtx_REG (Pmode, 0); | |
9476 | output_asm_insn ("l\t%9,%8-4-%5(%4)", op); | |
9477 | output_asm_insn ("a\t%4,%8-%5(%4)", op); | |
9478 | output_asm_insn ("ar\t%4,%9", op); | |
9479 | output_asm_insn ("l\t%4,0(%4)", op); | |
9480 | } | |
9db1d521 | 9481 | |
ab96de7e | 9482 | output_asm_insn ("br\t%4", op); |
9db1d521 | 9483 | |
ab96de7e AS |
9484 | /* Output literal pool. */ |
9485 | output_asm_insn (".align\t4", op); | |
9db1d521 | 9486 | |
ab96de7e AS |
9487 | if (nonlocal && flag_pic == 2) |
9488 | output_asm_insn (".long\t%0", op); | |
9489 | if (nonlocal) | |
9490 | { | |
9491 | op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); | |
9492 | SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL; | |
9493 | } | |
63694b5e | 9494 | |
ab96de7e AS |
9495 | targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8])); |
9496 | if (!flag_pic) | |
9497 | output_asm_insn (".long\t%0", op); | |
9498 | else | |
9499 | output_asm_insn (".long\t%0-%5", op); | |
9db1d521 | 9500 | |
ab96de7e AS |
9501 | if (op[6]) |
9502 | { | |
9503 | targetm.asm_out.internal_label (file, "L", | |
9504 | CODE_LABEL_NUMBER (op[6])); | |
9505 | output_asm_insn (".long\t%2", op); | |
9506 | } | |
9507 | if (op[7]) | |
9508 | { | |
9509 | targetm.asm_out.internal_label (file, "L", | |
9510 | CODE_LABEL_NUMBER (op[7])); | |
9511 | output_asm_insn (".long\t%3", op); | |
9512 | } | |
9db1d521 | 9513 | } |
81ef7e24 | 9514 | final_end_function (); |
9db1d521 HP |
9515 | } |
9516 | ||
ab96de7e AS |
9517 | static bool |
9518 | s390_valid_pointer_mode (enum machine_mode mode) | |
9519 | { | |
9520 | return (mode == SImode || (TARGET_64BIT && mode == DImode)); | |
9521 | } | |
994fe660 | 9522 | |
9a6f71b4 | 9523 | /* Checks whether the given CALL_EXPR would use a caller |
ab96de7e AS |
9524 | saved register. This is used to decide whether sibling call |
9525 | optimization could be performed on the respective function | |
9526 | call. */ | |
fd3cd001 | 9527 | |
ab96de7e | 9528 | static bool |
9a6f71b4 | 9529 | s390_call_saved_register_used (tree call_expr) |
fd3cd001 | 9530 | { |
ab96de7e AS |
9531 | CUMULATIVE_ARGS cum; |
9532 | tree parameter; | |
9533 | enum machine_mode mode; | |
9534 | tree type; | |
9535 | rtx parm_rtx; | |
9a6f71b4 | 9536 | int reg, i; |
fd3cd001 | 9537 | |
ab96de7e | 9538 | INIT_CUMULATIVE_ARGS (cum, NULL, NULL, 0, 0); |
fd3cd001 | 9539 | |
9a6f71b4 | 9540 | for (i = 0; i < call_expr_nargs (call_expr); i++) |
ab96de7e | 9541 | { |
9a6f71b4 | 9542 | parameter = CALL_EXPR_ARG (call_expr, i); |
8d933e31 | 9543 | gcc_assert (parameter); |
fd3cd001 | 9544 | |
ab96de7e AS |
9545 | /* For an undeclared variable passed as parameter we will get |
9546 | an ERROR_MARK node here. */ | |
9547 | if (TREE_CODE (parameter) == ERROR_MARK) | |
9548 | return true; | |
fd3cd001 | 9549 | |
8d933e31 AS |
9550 | type = TREE_TYPE (parameter); |
9551 | gcc_assert (type); | |
fd3cd001 | 9552 | |
8d933e31 AS |
9553 | mode = TYPE_MODE (type); |
9554 | gcc_assert (mode); | |
fd3cd001 | 9555 | |
ab96de7e AS |
9556 | if (pass_by_reference (&cum, mode, type, true)) |
9557 | { | |
9558 | mode = Pmode; | |
9559 | type = build_pointer_type (type); | |
9560 | } | |
fd3cd001 | 9561 | |
ab96de7e | 9562 | parm_rtx = s390_function_arg (&cum, mode, type, 0); |
fd3cd001 | 9563 | |
ab96de7e | 9564 | s390_function_arg_advance (&cum, mode, type, 0); |
fd3cd001 | 9565 | |
9602b6a1 AK |
9566 | if (!parm_rtx) |
9567 | continue; | |
9568 | ||
9569 | if (REG_P (parm_rtx)) | |
9570 | { | |
e8de8fea AK |
9571 | for (reg = 0; |
9572 | reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx)); | |
9573 | reg++) | |
9602b6a1 AK |
9574 | if (!call_used_regs[reg + REGNO (parm_rtx)]) |
9575 | return true; | |
9576 | } | |
9577 | ||
9578 | if (GET_CODE (parm_rtx) == PARALLEL) | |
ab96de7e | 9579 | { |
9602b6a1 | 9580 | int i; |
e8de8fea | 9581 | |
9602b6a1 AK |
9582 | for (i = 0; i < XVECLEN (parm_rtx, 0); i++) |
9583 | { | |
9584 | rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0); | |
9602b6a1 AK |
9585 | |
9586 | gcc_assert (REG_P (r)); | |
9587 | ||
e8de8fea AK |
9588 | for (reg = 0; |
9589 | reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r)); | |
9590 | reg++) | |
9602b6a1 AK |
9591 | if (!call_used_regs[reg + REGNO (r)]) |
9592 | return true; | |
9593 | } | |
ab96de7e | 9594 | } |
9602b6a1 | 9595 | |
ab96de7e AS |
9596 | } |
9597 | return false; | |
9598 | } | |
fd3cd001 | 9599 | |
ab96de7e AS |
9600 | /* Return true if the given call expression can be |
9601 | turned into a sibling call. | |
9602 | DECL holds the declaration of the function to be called whereas | |
9603 | EXP is the call expression itself. */ | |
fd3cd001 | 9604 | |
ab96de7e AS |
9605 | static bool |
9606 | s390_function_ok_for_sibcall (tree decl, tree exp) | |
9607 | { | |
9608 | /* The TPF epilogue uses register 1. */ | |
9609 | if (TARGET_TPF_PROFILING) | |
9610 | return false; | |
fd3cd001 | 9611 | |
ab96de7e AS |
9612 | /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved) |
9613 | which would have to be restored before the sibcall. */ | |
7691ec4e | 9614 | if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl)) |
ab96de7e | 9615 | return false; |
fd3cd001 | 9616 | |
ab96de7e AS |
9617 | /* Register 6 on s390 is available as an argument register but unfortunately |
9618 | "caller saved". This makes functions needing this register for arguments | |
9619 | not suitable for sibcalls. */ | |
9a6f71b4 | 9620 | return !s390_call_saved_register_used (exp); |
ab96de7e | 9621 | } |
fd3cd001 | 9622 | |
ab96de7e | 9623 | /* Return the fixed registers used for condition codes. */ |
fd3cd001 | 9624 | |
ab96de7e AS |
9625 | static bool |
9626 | s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) | |
9627 | { | |
9628 | *p1 = CC_REGNUM; | |
9629 | *p2 = INVALID_REGNUM; | |
f4aa3848 | 9630 | |
ab96de7e AS |
9631 | return true; |
9632 | } | |
fd3cd001 | 9633 | |
ab96de7e AS |
9634 | /* This function is used by the call expanders of the machine description. |
9635 | It emits the call insn itself together with the necessary operations | |
9636 | to adjust the target address and returns the emitted insn. | |
9637 | ADDR_LOCATION is the target address rtx | |
9638 | TLS_CALL the location of the thread-local symbol | |
9639 | RESULT_REG the register where the result of the call should be stored | |
9640 | RETADDR_REG the register where the return address should be stored | |
9641 | If this parameter is NULL_RTX the call is considered | |
9642 | to be a sibling call. */ | |
fd3cd001 | 9643 | |
ab96de7e AS |
9644 | rtx |
9645 | s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg, | |
9646 | rtx retaddr_reg) | |
9db1d521 | 9647 | { |
ab96de7e AS |
9648 | bool plt_call = false; |
9649 | rtx insn; | |
9650 | rtx call; | |
9651 | rtx clobber; | |
9652 | rtvec vec; | |
cadc42db | 9653 | |
ab96de7e AS |
9654 | /* Direct function calls need special treatment. */ |
9655 | if (GET_CODE (addr_location) == SYMBOL_REF) | |
9db1d521 | 9656 | { |
ab96de7e AS |
9657 | /* When calling a global routine in PIC mode, we must |
9658 | replace the symbol itself with the PLT stub. */ | |
9659 | if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location)) | |
9660 | { | |
72e2cf16 AK |
9661 | if (retaddr_reg != NULL_RTX) |
9662 | { | |
9663 | addr_location = gen_rtx_UNSPEC (Pmode, | |
9664 | gen_rtvec (1, addr_location), | |
9665 | UNSPEC_PLT); | |
9666 | addr_location = gen_rtx_CONST (Pmode, addr_location); | |
9667 | plt_call = true; | |
9668 | } | |
9669 | else | |
9670 | /* For -fpic code the PLT entries might use r12 which is | |
9671 | call-saved. Therefore we cannot do a sibcall when | |
9672 | calling directly using a symbol ref. When reaching | |
9673 | this point we decided (in s390_function_ok_for_sibcall) | |
9674 | to do a sibcall for a function pointer but one of the | |
9675 | optimizers was able to get rid of the function pointer | |
9676 | by propagating the symbol ref into the call. This | |
9677 | optimization is illegal for S/390 so we turn the direct | |
9678 | call into a indirect call again. */ | |
9679 | addr_location = force_reg (Pmode, addr_location); | |
ab96de7e AS |
9680 | } |
9681 | ||
9682 | /* Unless we can use the bras(l) insn, force the | |
9683 | routine address into a register. */ | |
9684 | if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH) | |
9685 | { | |
9686 | if (flag_pic) | |
9687 | addr_location = legitimize_pic_address (addr_location, 0); | |
9688 | else | |
9689 | addr_location = force_reg (Pmode, addr_location); | |
9690 | } | |
9db1d521 | 9691 | } |
ab96de7e AS |
9692 | |
9693 | /* If it is already an indirect call or the code above moved the | |
9694 | SYMBOL_REF to somewhere else make sure the address can be found in | |
9695 | register 1. */ | |
9696 | if (retaddr_reg == NULL_RTX | |
9697 | && GET_CODE (addr_location) != SYMBOL_REF | |
9698 | && !plt_call) | |
9db1d521 | 9699 | { |
ab96de7e AS |
9700 | emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location); |
9701 | addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM); | |
9db1d521 | 9702 | } |
9db1d521 | 9703 | |
ab96de7e AS |
9704 | addr_location = gen_rtx_MEM (QImode, addr_location); |
9705 | call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx); | |
4023fb28 | 9706 | |
ab96de7e AS |
9707 | if (result_reg != NULL_RTX) |
9708 | call = gen_rtx_SET (VOIDmode, result_reg, call); | |
4023fb28 | 9709 | |
ab96de7e AS |
9710 | if (retaddr_reg != NULL_RTX) |
9711 | { | |
9712 | clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg); | |
c7453384 | 9713 | |
ab96de7e AS |
9714 | if (tls_call != NULL_RTX) |
9715 | vec = gen_rtvec (3, call, clobber, | |
9716 | gen_rtx_USE (VOIDmode, tls_call)); | |
9717 | else | |
9718 | vec = gen_rtvec (2, call, clobber); | |
4023fb28 | 9719 | |
ab96de7e AS |
9720 | call = gen_rtx_PARALLEL (VOIDmode, vec); |
9721 | } | |
4023fb28 | 9722 | |
ab96de7e | 9723 | insn = emit_call_insn (call); |
4023fb28 | 9724 | |
ab96de7e AS |
9725 | /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */ |
9726 | if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX) | |
9727 | { | |
9728 | /* s390_function_ok_for_sibcall should | |
9729 | have denied sibcalls in this case. */ | |
8d933e31 | 9730 | gcc_assert (retaddr_reg != NULL_RTX); |
4023fb28 | 9731 | |
ab96de7e AS |
9732 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); |
9733 | } | |
9734 | return insn; | |
9735 | } | |
4023fb28 | 9736 | |
ab96de7e | 9737 | /* Implement CONDITIONAL_REGISTER_USAGE. */ |
4023fb28 | 9738 | |
ab96de7e AS |
9739 | void |
9740 | s390_conditional_register_usage (void) | |
9741 | { | |
9742 | int i; | |
4023fb28 | 9743 | |
4023fb28 UW |
9744 | if (flag_pic) |
9745 | { | |
ab96de7e AS |
9746 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; |
9747 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; | |
4023fb28 | 9748 | } |
ab96de7e | 9749 | if (TARGET_CPU_ZARCH) |
4023fb28 | 9750 | { |
7633f08e UW |
9751 | fixed_regs[BASE_REGNUM] = 0; |
9752 | call_used_regs[BASE_REGNUM] = 0; | |
ab96de7e AS |
9753 | fixed_regs[RETURN_REGNUM] = 0; |
9754 | call_used_regs[RETURN_REGNUM] = 0; | |
4023fb28 | 9755 | } |
ab96de7e | 9756 | if (TARGET_64BIT) |
4023fb28 | 9757 | { |
ab96de7e AS |
9758 | for (i = 24; i < 32; i++) |
9759 | call_used_regs[i] = call_really_used_regs[i] = 0; | |
4023fb28 UW |
9760 | } |
9761 | else | |
9762 | { | |
ab96de7e AS |
9763 | for (i = 18; i < 20; i++) |
9764 | call_used_regs[i] = call_really_used_regs[i] = 0; | |
9765 | } | |
4023fb28 | 9766 | |
ab96de7e AS |
9767 | if (TARGET_SOFT_FLOAT) |
9768 | { | |
9769 | for (i = 16; i < 32; i++) | |
9770 | call_used_regs[i] = fixed_regs[i] = 1; | |
4023fb28 UW |
9771 | } |
9772 | } | |
9773 | ||
ab96de7e | 9774 | /* Corresponding function to eh_return expander. */ |
fb49053f | 9775 | |
ab96de7e AS |
9776 | static GTY(()) rtx s390_tpf_eh_return_symbol; |
9777 | void | |
9778 | s390_emit_tpf_eh_return (rtx target) | |
fb49053f | 9779 | { |
ab96de7e | 9780 | rtx insn, reg; |
e23795ea | 9781 | |
ab96de7e AS |
9782 | if (!s390_tpf_eh_return_symbol) |
9783 | s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return"); | |
9784 | ||
9785 | reg = gen_rtx_REG (Pmode, 2); | |
9786 | ||
9787 | emit_move_insn (reg, target); | |
9788 | insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg, | |
9789 | gen_rtx_REG (Pmode, RETURN_REGNUM)); | |
9790 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg); | |
9791 | ||
9792 | emit_move_insn (EH_RETURN_HANDLER_RTX, reg); | |
fd3cd001 UW |
9793 | } |
9794 | ||
ab96de7e AS |
9795 | /* Rework the prologue/epilogue to avoid saving/restoring |
9796 | registers unnecessarily. */ | |
3062825f | 9797 | |
c590b625 | 9798 | static void |
ab96de7e | 9799 | s390_optimize_prologue (void) |
483ab821 | 9800 | { |
ab96de7e | 9801 | rtx insn, new_insn, next_insn; |
3062825f | 9802 | |
ab96de7e | 9803 | /* Do a final recompute of the frame-related data. */ |
3062825f | 9804 | |
ab96de7e | 9805 | s390_update_frame_layout (); |
3062825f | 9806 | |
ab96de7e AS |
9807 | /* If all special registers are in fact used, there's nothing we |
9808 | can do, so no point in walking the insn list. */ | |
3062825f | 9809 | |
f4aa3848 | 9810 | if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM |
ab96de7e | 9811 | && cfun_frame_layout.last_save_gpr >= BASE_REGNUM |
f4aa3848 AK |
9812 | && (TARGET_CPU_ZARCH |
9813 | || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM | |
ab96de7e AS |
9814 | && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM))) |
9815 | return; | |
3062825f | 9816 | |
ab96de7e | 9817 | /* Search for prologue/epilogue insns and replace them. */ |
3062825f | 9818 | |
ab96de7e AS |
9819 | for (insn = get_insns (); insn; insn = next_insn) |
9820 | { | |
9821 | int first, last, off; | |
9822 | rtx set, base, offset; | |
3062825f | 9823 | |
ab96de7e | 9824 | next_insn = NEXT_INSN (insn); |
89ce1c8f | 9825 | |
ab96de7e AS |
9826 | if (GET_CODE (insn) != INSN) |
9827 | continue; | |
3062825f | 9828 | |
ab96de7e AS |
9829 | if (GET_CODE (PATTERN (insn)) == PARALLEL |
9830 | && store_multiple_operation (PATTERN (insn), VOIDmode)) | |
3062825f | 9831 | { |
ab96de7e AS |
9832 | set = XVECEXP (PATTERN (insn), 0, 0); |
9833 | first = REGNO (SET_SRC (set)); | |
9834 | last = first + XVECLEN (PATTERN (insn), 0) - 1; | |
9835 | offset = const0_rtx; | |
9836 | base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset); | |
9837 | off = INTVAL (offset); | |
3062825f | 9838 | |
ab96de7e AS |
9839 | if (GET_CODE (base) != REG || off < 0) |
9840 | continue; | |
22a707a4 AK |
9841 | if (cfun_frame_layout.first_save_gpr != -1 |
9842 | && (cfun_frame_layout.first_save_gpr < first | |
9843 | || cfun_frame_layout.last_save_gpr > last)) | |
9844 | continue; | |
ab96de7e AS |
9845 | if (REGNO (base) != STACK_POINTER_REGNUM |
9846 | && REGNO (base) != HARD_FRAME_POINTER_REGNUM) | |
9847 | continue; | |
9848 | if (first > BASE_REGNUM || last < BASE_REGNUM) | |
9849 | continue; | |
9850 | ||
9851 | if (cfun_frame_layout.first_save_gpr != -1) | |
3062825f | 9852 | { |
f4aa3848 | 9853 | new_insn = save_gprs (base, |
ab96de7e | 9854 | off + (cfun_frame_layout.first_save_gpr |
9602b6a1 | 9855 | - first) * UNITS_PER_LONG, |
ab96de7e AS |
9856 | cfun_frame_layout.first_save_gpr, |
9857 | cfun_frame_layout.last_save_gpr); | |
9858 | new_insn = emit_insn_before (new_insn, insn); | |
9859 | INSN_ADDRESSES_NEW (new_insn, -1); | |
3062825f | 9860 | } |
3062825f | 9861 | |
ab96de7e AS |
9862 | remove_insn (insn); |
9863 | continue; | |
3062825f UW |
9864 | } |
9865 | ||
22a707a4 AK |
9866 | if (cfun_frame_layout.first_save_gpr == -1 |
9867 | && GET_CODE (PATTERN (insn)) == SET | |
ab96de7e AS |
9868 | && GET_CODE (SET_SRC (PATTERN (insn))) == REG |
9869 | && (REGNO (SET_SRC (PATTERN (insn))) == BASE_REGNUM | |
9870 | || (!TARGET_CPU_ZARCH | |
9871 | && REGNO (SET_SRC (PATTERN (insn))) == RETURN_REGNUM)) | |
9872 | && GET_CODE (SET_DEST (PATTERN (insn))) == MEM) | |
3062825f | 9873 | { |
ab96de7e AS |
9874 | set = PATTERN (insn); |
9875 | first = REGNO (SET_SRC (set)); | |
9876 | offset = const0_rtx; | |
9877 | base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset); | |
9878 | off = INTVAL (offset); | |
3062825f | 9879 | |
ab96de7e AS |
9880 | if (GET_CODE (base) != REG || off < 0) |
9881 | continue; | |
9882 | if (REGNO (base) != STACK_POINTER_REGNUM | |
9883 | && REGNO (base) != HARD_FRAME_POINTER_REGNUM) | |
9884 | continue; | |
3062825f | 9885 | |
ab96de7e AS |
9886 | remove_insn (insn); |
9887 | continue; | |
3062825f UW |
9888 | } |
9889 | ||
ab96de7e AS |
9890 | if (GET_CODE (PATTERN (insn)) == PARALLEL |
9891 | && load_multiple_operation (PATTERN (insn), VOIDmode)) | |
89ce1c8f | 9892 | { |
ab96de7e AS |
9893 | set = XVECEXP (PATTERN (insn), 0, 0); |
9894 | first = REGNO (SET_DEST (set)); | |
9895 | last = first + XVECLEN (PATTERN (insn), 0) - 1; | |
9896 | offset = const0_rtx; | |
9897 | base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset); | |
9898 | off = INTVAL (offset); | |
89ce1c8f | 9899 | |
ab96de7e AS |
9900 | if (GET_CODE (base) != REG || off < 0) |
9901 | continue; | |
22a707a4 AK |
9902 | if (cfun_frame_layout.first_restore_gpr != -1 |
9903 | && (cfun_frame_layout.first_restore_gpr < first | |
9904 | || cfun_frame_layout.last_restore_gpr > last)) | |
9905 | continue; | |
ab96de7e AS |
9906 | if (REGNO (base) != STACK_POINTER_REGNUM |
9907 | && REGNO (base) != HARD_FRAME_POINTER_REGNUM) | |
9908 | continue; | |
9909 | if (first > BASE_REGNUM || last < BASE_REGNUM) | |
9910 | continue; | |
3062825f | 9911 | |
ab96de7e AS |
9912 | if (cfun_frame_layout.first_restore_gpr != -1) |
9913 | { | |
f4aa3848 | 9914 | new_insn = restore_gprs (base, |
ab96de7e | 9915 | off + (cfun_frame_layout.first_restore_gpr |
9602b6a1 | 9916 | - first) * UNITS_PER_LONG, |
ab96de7e AS |
9917 | cfun_frame_layout.first_restore_gpr, |
9918 | cfun_frame_layout.last_restore_gpr); | |
9919 | new_insn = emit_insn_before (new_insn, insn); | |
9920 | INSN_ADDRESSES_NEW (new_insn, -1); | |
9921 | } | |
89ce1c8f | 9922 | |
ab96de7e AS |
9923 | remove_insn (insn); |
9924 | continue; | |
89ce1c8f JJ |
9925 | } |
9926 | ||
22a707a4 AK |
9927 | if (cfun_frame_layout.first_restore_gpr == -1 |
9928 | && GET_CODE (PATTERN (insn)) == SET | |
ab96de7e AS |
9929 | && GET_CODE (SET_DEST (PATTERN (insn))) == REG |
9930 | && (REGNO (SET_DEST (PATTERN (insn))) == BASE_REGNUM | |
9931 | || (!TARGET_CPU_ZARCH | |
9932 | && REGNO (SET_DEST (PATTERN (insn))) == RETURN_REGNUM)) | |
9933 | && GET_CODE (SET_SRC (PATTERN (insn))) == MEM) | |
3062825f | 9934 | { |
ab96de7e AS |
9935 | set = PATTERN (insn); |
9936 | first = REGNO (SET_DEST (set)); | |
9937 | offset = const0_rtx; | |
9938 | base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset); | |
9939 | off = INTVAL (offset); | |
c7453384 | 9940 | |
ab96de7e AS |
9941 | if (GET_CODE (base) != REG || off < 0) |
9942 | continue; | |
9943 | if (REGNO (base) != STACK_POINTER_REGNUM | |
9944 | && REGNO (base) != HARD_FRAME_POINTER_REGNUM) | |
9945 | continue; | |
29742ba4 | 9946 | |
ab96de7e AS |
9947 | remove_insn (insn); |
9948 | continue; | |
9949 | } | |
9950 | } | |
29742ba4 HP |
9951 | } |
9952 | ||
65b1d8ea AK |
9953 | /* On z10 and later the dynamic branch prediction must see the |
9954 | backward jump within a certain windows. If not it falls back to | |
9955 | the static prediction. This function rearranges the loop backward | |
9956 | branch in a way which makes the static prediction always correct. | |
9957 | The function returns true if it added an instruction. */ | |
b0f86a7e | 9958 | static bool |
65b1d8ea | 9959 | s390_fix_long_loop_prediction (rtx insn) |
b0f86a7e AK |
9960 | { |
9961 | rtx set = single_set (insn); | |
9962 | rtx code_label, label_ref, new_label; | |
9963 | rtx uncond_jump; | |
9964 | rtx cur_insn; | |
9965 | rtx tmp; | |
9966 | int distance; | |
9967 | ||
9968 | /* This will exclude branch on count and branch on index patterns | |
9969 | since these are correctly statically predicted. */ | |
9970 | if (!set | |
9971 | || SET_DEST (set) != pc_rtx | |
9972 | || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE) | |
9973 | return false; | |
9974 | ||
9975 | label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ? | |
9976 | XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2)); | |
9977 | ||
9978 | gcc_assert (GET_CODE (label_ref) == LABEL_REF); | |
9979 | ||
9980 | code_label = XEXP (label_ref, 0); | |
9981 | ||
9982 | if (INSN_ADDRESSES (INSN_UID (code_label)) == -1 | |
9983 | || INSN_ADDRESSES (INSN_UID (insn)) == -1 | |
9984 | || (INSN_ADDRESSES (INSN_UID (insn)) | |
65b1d8ea | 9985 | - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE)) |
b0f86a7e AK |
9986 | return false; |
9987 | ||
9988 | for (distance = 0, cur_insn = PREV_INSN (insn); | |
65b1d8ea | 9989 | distance < PREDICT_DISTANCE - 6; |
b0f86a7e AK |
9990 | distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn)) |
9991 | if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn)) | |
9992 | return false; | |
9993 | ||
9994 | new_label = gen_label_rtx (); | |
9995 | uncond_jump = emit_jump_insn_after ( | |
9996 | gen_rtx_SET (VOIDmode, pc_rtx, | |
9997 | gen_rtx_LABEL_REF (VOIDmode, code_label)), | |
9998 | insn); | |
9999 | emit_label_after (new_label, uncond_jump); | |
10000 | ||
10001 | tmp = XEXP (SET_SRC (set), 1); | |
10002 | XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2); | |
10003 | XEXP (SET_SRC (set), 2) = tmp; | |
10004 | INSN_CODE (insn) = -1; | |
10005 | ||
10006 | XEXP (label_ref, 0) = new_label; | |
10007 | JUMP_LABEL (insn) = new_label; | |
10008 | JUMP_LABEL (uncond_jump) = code_label; | |
10009 | ||
10010 | return true; | |
10011 | } | |
10012 | ||
d277db6b WG |
10013 | /* Returns 1 if INSN reads the value of REG for purposes not related |
10014 | to addressing of memory, and 0 otherwise. */ | |
10015 | static int | |
10016 | s390_non_addr_reg_read_p (rtx reg, rtx insn) | |
10017 | { | |
10018 | return reg_referenced_p (reg, PATTERN (insn)) | |
10019 | && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn)); | |
10020 | } | |
10021 | ||
e3cba5e5 AK |
10022 | /* Starting from INSN find_cond_jump looks downwards in the insn |
10023 | stream for a single jump insn which is the last user of the | |
10024 | condition code set in INSN. */ | |
10025 | static rtx | |
10026 | find_cond_jump (rtx insn) | |
10027 | { | |
10028 | for (; insn; insn = NEXT_INSN (insn)) | |
10029 | { | |
10030 | rtx ite, cc; | |
10031 | ||
10032 | if (LABEL_P (insn)) | |
10033 | break; | |
10034 | ||
10035 | if (!JUMP_P (insn)) | |
10036 | { | |
10037 | if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn)) | |
10038 | break; | |
10039 | continue; | |
10040 | } | |
10041 | ||
10042 | /* This will be triggered by a return. */ | |
10043 | if (GET_CODE (PATTERN (insn)) != SET) | |
10044 | break; | |
10045 | ||
10046 | gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx); | |
10047 | ite = SET_SRC (PATTERN (insn)); | |
10048 | ||
10049 | if (GET_CODE (ite) != IF_THEN_ELSE) | |
10050 | break; | |
10051 | ||
10052 | cc = XEXP (XEXP (ite, 0), 0); | |
10053 | if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc))) | |
10054 | break; | |
10055 | ||
10056 | if (find_reg_note (insn, REG_DEAD, cc)) | |
10057 | return insn; | |
10058 | break; | |
10059 | } | |
10060 | ||
10061 | return NULL_RTX; | |
10062 | } | |
10063 | ||
10064 | /* Swap the condition in COND and the operands in OP0 and OP1 so that | |
10065 | the semantics does not change. If NULL_RTX is passed as COND the | |
10066 | function tries to find the conditional jump starting with INSN. */ | |
10067 | static void | |
10068 | s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn) | |
10069 | { | |
10070 | rtx tmp = *op0; | |
10071 | ||
10072 | if (cond == NULL_RTX) | |
10073 | { | |
10074 | rtx jump = find_cond_jump (NEXT_INSN (insn)); | |
10075 | jump = jump ? single_set (jump) : NULL_RTX; | |
10076 | ||
10077 | if (jump == NULL_RTX) | |
10078 | return; | |
10079 | ||
10080 | cond = XEXP (XEXP (jump, 1), 0); | |
10081 | } | |
10082 | ||
10083 | *op0 = *op1; | |
10084 | *op1 = tmp; | |
10085 | PUT_CODE (cond, swap_condition (GET_CODE (cond))); | |
10086 | } | |
d277db6b WG |
10087 | |
10088 | /* On z10, instructions of the compare-and-branch family have the | |
10089 | property to access the register occurring as second operand with | |
10090 | its bits complemented. If such a compare is grouped with a second | |
10091 | instruction that accesses the same register non-complemented, and | |
10092 | if that register's value is delivered via a bypass, then the | |
10093 | pipeline recycles, thereby causing significant performance decline. | |
10094 | This function locates such situations and exchanges the two | |
b0f86a7e AK |
10095 | operands of the compare. The function return true whenever it |
10096 | added an insn. */ | |
10097 | static bool | |
10098 | s390_z10_optimize_cmp (rtx insn) | |
d277db6b | 10099 | { |
b0f86a7e AK |
10100 | rtx prev_insn, next_insn; |
10101 | bool insn_added_p = false; | |
10102 | rtx cond, *op0, *op1; | |
d277db6b | 10103 | |
b0f86a7e | 10104 | if (GET_CODE (PATTERN (insn)) == PARALLEL) |
d277db6b | 10105 | { |
b0f86a7e AK |
10106 | /* Handle compare and branch and branch on count |
10107 | instructions. */ | |
10108 | rtx pattern = single_set (insn); | |
e3cba5e5 | 10109 | |
b0f86a7e AK |
10110 | if (!pattern |
10111 | || SET_DEST (pattern) != pc_rtx | |
10112 | || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE) | |
10113 | return false; | |
d277db6b | 10114 | |
b0f86a7e AK |
10115 | cond = XEXP (SET_SRC (pattern), 0); |
10116 | op0 = &XEXP (cond, 0); | |
10117 | op1 = &XEXP (cond, 1); | |
10118 | } | |
10119 | else if (GET_CODE (PATTERN (insn)) == SET) | |
10120 | { | |
10121 | rtx src, dest; | |
d277db6b | 10122 | |
b0f86a7e AK |
10123 | /* Handle normal compare instructions. */ |
10124 | src = SET_SRC (PATTERN (insn)); | |
10125 | dest = SET_DEST (PATTERN (insn)); | |
e3cba5e5 | 10126 | |
b0f86a7e AK |
10127 | if (!REG_P (dest) |
10128 | || !CC_REGNO_P (REGNO (dest)) | |
10129 | || GET_CODE (src) != COMPARE) | |
10130 | return false; | |
e3cba5e5 | 10131 | |
b0f86a7e AK |
10132 | /* s390_swap_cmp will try to find the conditional |
10133 | jump when passing NULL_RTX as condition. */ | |
10134 | cond = NULL_RTX; | |
10135 | op0 = &XEXP (src, 0); | |
10136 | op1 = &XEXP (src, 1); | |
10137 | } | |
10138 | else | |
10139 | return false; | |
e3cba5e5 | 10140 | |
b0f86a7e AK |
10141 | if (!REG_P (*op0) || !REG_P (*op1)) |
10142 | return false; | |
e3cba5e5 | 10143 | |
2dfdbf2b AK |
10144 | if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT) |
10145 | return false; | |
10146 | ||
b0f86a7e AK |
10147 | /* Swap the COMPARE arguments and its mask if there is a |
10148 | conflicting access in the previous insn. */ | |
33ab2bd4 | 10149 | prev_insn = prev_active_insn (insn); |
b0f86a7e AK |
10150 | if (prev_insn != NULL_RTX && INSN_P (prev_insn) |
10151 | && reg_referenced_p (*op1, PATTERN (prev_insn))) | |
10152 | s390_swap_cmp (cond, op0, op1, insn); | |
10153 | ||
10154 | /* Check if there is a conflict with the next insn. If there | |
10155 | was no conflict with the previous insn, then swap the | |
10156 | COMPARE arguments and its mask. If we already swapped | |
10157 | the operands, or if swapping them would cause a conflict | |
10158 | with the previous insn, issue a NOP after the COMPARE in | |
10159 | order to separate the two instuctions. */ | |
33ab2bd4 | 10160 | next_insn = next_active_insn (insn); |
b0f86a7e AK |
10161 | if (next_insn != NULL_RTX && INSN_P (next_insn) |
10162 | && s390_non_addr_reg_read_p (*op1, next_insn)) | |
10163 | { | |
e3cba5e5 | 10164 | if (prev_insn != NULL_RTX && INSN_P (prev_insn) |
b0f86a7e | 10165 | && s390_non_addr_reg_read_p (*op0, prev_insn)) |
e3cba5e5 | 10166 | { |
b0f86a7e AK |
10167 | if (REGNO (*op1) == 0) |
10168 | emit_insn_after (gen_nop1 (), insn); | |
e3cba5e5 | 10169 | else |
b0f86a7e AK |
10170 | emit_insn_after (gen_nop (), insn); |
10171 | insn_added_p = true; | |
d277db6b | 10172 | } |
b0f86a7e AK |
10173 | else |
10174 | s390_swap_cmp (cond, op0, op1, insn); | |
d277db6b | 10175 | } |
b0f86a7e | 10176 | return insn_added_p; |
d277db6b WG |
10177 | } |
10178 | ||
ab96de7e | 10179 | /* Perform machine-dependent processing. */ |
ed9676cf | 10180 | |
ab96de7e AS |
10181 | static void |
10182 | s390_reorg (void) | |
ed9676cf | 10183 | { |
ab96de7e | 10184 | bool pool_overflow = false; |
ed9676cf | 10185 | |
ab96de7e AS |
10186 | /* Make sure all splits have been performed; splits after |
10187 | machine_dependent_reorg might confuse insn length counts. */ | |
10188 | split_all_insns_noflow (); | |
38899e29 | 10189 | |
ab96de7e AS |
10190 | /* Install the main literal pool and the associated base |
10191 | register load insns. | |
38899e29 | 10192 | |
ab96de7e AS |
10193 | In addition, there are two problematic situations we need |
10194 | to correct: | |
ed9676cf | 10195 | |
ab96de7e AS |
10196 | - the literal pool might be > 4096 bytes in size, so that |
10197 | some of its elements cannot be directly accessed | |
ed9676cf | 10198 | |
ab96de7e AS |
10199 | - a branch target might be > 64K away from the branch, so that |
10200 | it is not possible to use a PC-relative instruction. | |
ed9676cf | 10201 | |
ab96de7e AS |
10202 | To fix those, we split the single literal pool into multiple |
10203 | pool chunks, reloading the pool base register at various | |
10204 | points throughout the function to ensure it always points to | |
10205 | the pool chunk the following code expects, and / or replace | |
10206 | PC-relative branches by absolute branches. | |
ed9676cf | 10207 | |
ab96de7e AS |
10208 | However, the two problems are interdependent: splitting the |
10209 | literal pool can move a branch further away from its target, | |
10210 | causing the 64K limit to overflow, and on the other hand, | |
10211 | replacing a PC-relative branch by an absolute branch means | |
10212 | we need to put the branch target address into the literal | |
10213 | pool, possibly causing it to overflow. | |
ffdda752 | 10214 | |
ab96de7e AS |
10215 | So, we loop trying to fix up both problems until we manage |
10216 | to satisfy both conditions at the same time. Note that the | |
10217 | loop is guaranteed to terminate as every pass of the loop | |
10218 | strictly decreases the total number of PC-relative branches | |
10219 | in the function. (This is not completely true as there | |
10220 | might be branch-over-pool insns introduced by chunkify_start. | |
10221 | Those never need to be split however.) */ | |
ffdda752 | 10222 | |
ab96de7e AS |
10223 | for (;;) |
10224 | { | |
10225 | struct constant_pool *pool = NULL; | |
a628ab6d | 10226 | |
ab96de7e AS |
10227 | /* Collect the literal pool. */ |
10228 | if (!pool_overflow) | |
10229 | { | |
10230 | pool = s390_mainpool_start (); | |
10231 | if (!pool) | |
10232 | pool_overflow = true; | |
10233 | } | |
a628ab6d | 10234 | |
ab96de7e AS |
10235 | /* If literal pool overflowed, start to chunkify it. */ |
10236 | if (pool_overflow) | |
10237 | pool = s390_chunkify_start (); | |
a628ab6d | 10238 | |
ab96de7e AS |
10239 | /* Split out-of-range branches. If this has created new |
10240 | literal pool entries, cancel current chunk list and | |
10241 | recompute it. zSeries machines have large branch | |
10242 | instructions, so we never need to split a branch. */ | |
10243 | if (!TARGET_CPU_ZARCH && s390_split_branches ()) | |
10244 | { | |
10245 | if (pool_overflow) | |
10246 | s390_chunkify_cancel (pool); | |
10247 | else | |
10248 | s390_mainpool_cancel (pool); | |
a628ab6d | 10249 | |
ab96de7e AS |
10250 | continue; |
10251 | } | |
10252 | ||
10253 | /* If we made it up to here, both conditions are satisfied. | |
10254 | Finish up literal pool related changes. */ | |
10255 | if (pool_overflow) | |
10256 | s390_chunkify_finish (pool); | |
10257 | else | |
10258 | s390_mainpool_finish (pool); | |
10259 | ||
10260 | /* We're done splitting branches. */ | |
10261 | cfun->machine->split_branches_pending_p = false; | |
10262 | break; | |
a628ab6d | 10263 | } |
a628ab6d | 10264 | |
d24959df UW |
10265 | /* Generate out-of-pool execute target insns. */ |
10266 | if (TARGET_CPU_ZARCH) | |
10267 | { | |
10268 | rtx insn, label, target; | |
10269 | ||
10270 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
10271 | { | |
10272 | label = s390_execute_label (insn); | |
10273 | if (!label) | |
10274 | continue; | |
10275 | ||
10276 | gcc_assert (label != const0_rtx); | |
10277 | ||
10278 | target = emit_label (XEXP (label, 0)); | |
10279 | INSN_ADDRESSES_NEW (target, -1); | |
10280 | ||
10281 | target = emit_insn (s390_execute_target (insn)); | |
10282 | INSN_ADDRESSES_NEW (target, -1); | |
10283 | } | |
10284 | } | |
10285 | ||
10286 | /* Try to optimize prologue and epilogue further. */ | |
ab96de7e | 10287 | s390_optimize_prologue (); |
d277db6b | 10288 | |
65b1d8ea AK |
10289 | /* Walk over the insns and do some >=z10 specific changes. */ |
10290 | if (s390_tune == PROCESSOR_2097_Z10 | |
10291 | || s390_tune == PROCESSOR_2817_Z196) | |
b0f86a7e AK |
10292 | { |
10293 | rtx insn; | |
10294 | bool insn_added_p = false; | |
10295 | ||
10296 | /* The insn lengths and addresses have to be up to date for the | |
10297 | following manipulations. */ | |
10298 | shorten_branches (get_insns ()); | |
10299 | ||
10300 | for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) | |
10301 | { | |
10302 | if (!INSN_P (insn) || INSN_CODE (insn) <= 0) | |
10303 | continue; | |
10304 | ||
10305 | if (JUMP_P (insn)) | |
65b1d8ea | 10306 | insn_added_p |= s390_fix_long_loop_prediction (insn); |
b0f86a7e | 10307 | |
65b1d8ea AK |
10308 | if ((GET_CODE (PATTERN (insn)) == PARALLEL |
10309 | || GET_CODE (PATTERN (insn)) == SET) | |
10310 | && s390_tune == PROCESSOR_2097_Z10) | |
b0f86a7e AK |
10311 | insn_added_p |= s390_z10_optimize_cmp (insn); |
10312 | } | |
10313 | ||
10314 | /* Adjust branches if we added new instructions. */ | |
10315 | if (insn_added_p) | |
10316 | shorten_branches (get_insns ()); | |
10317 | } | |
ab96de7e | 10318 | } |
ed9676cf | 10319 | |
3a892e44 AK |
10320 | /* Return true if INSN is a fp load insn writing register REGNO. */ |
10321 | static inline bool | |
10322 | s390_fpload_toreg (rtx insn, unsigned int regno) | |
10323 | { | |
10324 | rtx set; | |
10325 | enum attr_type flag = s390_safe_attr_type (insn); | |
10326 | ||
10327 | if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF) | |
10328 | return false; | |
10329 | ||
10330 | set = single_set (insn); | |
10331 | ||
10332 | if (set == NULL_RTX) | |
10333 | return false; | |
10334 | ||
10335 | if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set))) | |
10336 | return false; | |
10337 | ||
10338 | if (REGNO (SET_DEST (set)) != regno) | |
10339 | return false; | |
10340 | ||
10341 | return true; | |
10342 | } | |
10343 | ||
10344 | /* This value describes the distance to be avoided between an | |
10345 | aritmetic fp instruction and an fp load writing the same register. | |
10346 | Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is | |
10347 | fine but the exact value has to be avoided. Otherwise the FP | |
10348 | pipeline will throw an exception causing a major penalty. */ | |
10349 | #define Z10_EARLYLOAD_DISTANCE 7 | |
10350 | ||
10351 | /* Rearrange the ready list in order to avoid the situation described | |
10352 | for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is | |
10353 | moved to the very end of the ready list. */ | |
10354 | static void | |
10355 | s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p) | |
10356 | { | |
10357 | unsigned int regno; | |
10358 | int nready = *nready_p; | |
10359 | rtx tmp; | |
10360 | int i; | |
10361 | rtx insn; | |
10362 | rtx set; | |
10363 | enum attr_type flag; | |
10364 | int distance; | |
10365 | ||
10366 | /* Skip DISTANCE - 1 active insns. */ | |
10367 | for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1; | |
10368 | distance > 0 && insn != NULL_RTX; | |
10369 | distance--, insn = prev_active_insn (insn)) | |
10370 | if (CALL_P (insn) || JUMP_P (insn)) | |
10371 | return; | |
10372 | ||
10373 | if (insn == NULL_RTX) | |
10374 | return; | |
10375 | ||
10376 | set = single_set (insn); | |
10377 | ||
10378 | if (set == NULL_RTX || !REG_P (SET_DEST (set)) | |
10379 | || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT) | |
10380 | return; | |
10381 | ||
10382 | flag = s390_safe_attr_type (insn); | |
10383 | ||
10384 | if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF) | |
10385 | return; | |
10386 | ||
10387 | regno = REGNO (SET_DEST (set)); | |
10388 | i = nready - 1; | |
10389 | ||
10390 | while (!s390_fpload_toreg (ready[i], regno) && i > 0) | |
10391 | i--; | |
10392 | ||
10393 | if (!i) | |
10394 | return; | |
10395 | ||
10396 | tmp = ready[i]; | |
10397 | memmove (&ready[1], &ready[0], sizeof (rtx) * i); | |
10398 | ready[0] = tmp; | |
10399 | } | |
10400 | ||
10401 | /* This function is called via hook TARGET_SCHED_REORDER before | |
10402 | issueing one insn from list READY which contains *NREADYP entries. | |
10403 | For target z10 it reorders load instructions to avoid early load | |
10404 | conflicts in the floating point pipeline */ | |
10405 | static int | |
10406 | s390_sched_reorder (FILE *file ATTRIBUTE_UNUSED, int verbose ATTRIBUTE_UNUSED, | |
10407 | rtx *ready, int *nreadyp, int clock ATTRIBUTE_UNUSED) | |
10408 | { | |
10409 | if (s390_tune == PROCESSOR_2097_Z10) | |
10410 | if (reload_completed && *nreadyp > 1) | |
10411 | s390_z10_prevent_earlyload_conflicts (ready, nreadyp); | |
10412 | ||
10413 | return s390_issue_rate (); | |
10414 | } | |
10415 | ||
10416 | /* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after | |
10417 | the scheduler has issued INSN. It stores the last issued insn into | |
10418 | last_scheduled_insn in order to make it available for | |
10419 | s390_sched_reorder. */ | |
10420 | static int | |
10421 | s390_sched_variable_issue (FILE *file ATTRIBUTE_UNUSED, | |
10422 | int verbose ATTRIBUTE_UNUSED, | |
10423 | rtx insn, int more) | |
10424 | { | |
10425 | last_scheduled_insn = insn; | |
10426 | ||
10427 | if (GET_CODE (PATTERN (insn)) != USE | |
10428 | && GET_CODE (PATTERN (insn)) != CLOBBER) | |
10429 | return more - 1; | |
10430 | else | |
10431 | return more; | |
10432 | } | |
ed9676cf | 10433 | |
244e6c5c AK |
10434 | static void |
10435 | s390_sched_init (FILE *file ATTRIBUTE_UNUSED, | |
10436 | int verbose ATTRIBUTE_UNUSED, | |
10437 | int max_ready ATTRIBUTE_UNUSED) | |
10438 | { | |
10439 | last_scheduled_insn = NULL_RTX; | |
10440 | } | |
10441 | ||
40ac4f73 CB |
10442 | /* This function checks the whole of insn X for memory references. The |
10443 | function always returns zero because the framework it is called | |
10444 | from would stop recursively analyzing the insn upon a return value | |
10445 | other than zero. The real result of this function is updating | |
10446 | counter variable MEM_COUNT. */ | |
10447 | static int | |
10448 | check_dpu (rtx *x, unsigned *mem_count) | |
10449 | { | |
10450 | if (*x != NULL_RTX && MEM_P (*x)) | |
10451 | (*mem_count)++; | |
10452 | return 0; | |
10453 | } | |
10454 | ||
10455 | /* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates | |
65b1d8ea AK |
10456 | a new number struct loop *loop should be unrolled if tuned for cpus with |
10457 | a built-in stride prefetcher. | |
10458 | The loop is analyzed for memory accesses by calling check_dpu for | |
40ac4f73 CB |
10459 | each rtx of the loop. Depending on the loop_depth and the amount of |
10460 | memory accesses a new number <=nunroll is returned to improve the | |
10461 | behaviour of the hardware prefetch unit. */ | |
10462 | static unsigned | |
10463 | s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop) | |
10464 | { | |
10465 | basic_block *bbs; | |
10466 | rtx insn; | |
10467 | unsigned i; | |
10468 | unsigned mem_count = 0; | |
10469 | ||
65b1d8ea | 10470 | if (s390_tune != PROCESSOR_2097_Z10 && s390_tune != PROCESSOR_2817_Z196) |
40ac4f73 CB |
10471 | return nunroll; |
10472 | ||
10473 | /* Count the number of memory references within the loop body. */ | |
10474 | bbs = get_loop_body (loop); | |
10475 | for (i = 0; i < loop->num_nodes; i++) | |
10476 | { | |
10477 | for (insn = BB_HEAD (bbs[i]); insn != BB_END (bbs[i]); insn = NEXT_INSN (insn)) | |
10478 | if (INSN_P (insn) && INSN_CODE (insn) != -1) | |
10479 | for_each_rtx (&insn, (rtx_function) check_dpu, &mem_count); | |
10480 | } | |
10481 | free (bbs); | |
10482 | ||
10483 | /* Prevent division by zero, and we do not need to adjust nunroll in this case. */ | |
10484 | if (mem_count == 0) | |
10485 | return nunroll; | |
10486 | ||
10487 | switch (loop_depth(loop)) | |
10488 | { | |
10489 | case 1: | |
10490 | return MIN (nunroll, 28 / mem_count); | |
10491 | case 2: | |
10492 | return MIN (nunroll, 22 / mem_count); | |
10493 | default: | |
10494 | return MIN (nunroll, 16 / mem_count); | |
10495 | } | |
10496 | } | |
10497 | ||
ab96de7e | 10498 | /* Initialize GCC target structure. */ |
38899e29 | 10499 | |
ab96de7e AS |
10500 | #undef TARGET_ASM_ALIGNED_HI_OP |
10501 | #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" | |
10502 | #undef TARGET_ASM_ALIGNED_DI_OP | |
10503 | #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t" | |
10504 | #undef TARGET_ASM_INTEGER | |
10505 | #define TARGET_ASM_INTEGER s390_assemble_integer | |
ed9676cf | 10506 | |
ab96de7e AS |
10507 | #undef TARGET_ASM_OPEN_PAREN |
10508 | #define TARGET_ASM_OPEN_PAREN "" | |
38899e29 | 10509 | |
ab96de7e AS |
10510 | #undef TARGET_ASM_CLOSE_PAREN |
10511 | #define TARGET_ASM_CLOSE_PAREN "" | |
ed9676cf | 10512 | |
ab96de7e AS |
10513 | #undef TARGET_DEFAULT_TARGET_FLAGS |
10514 | #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_FUSED_MADD) | |
9602b6a1 | 10515 | |
ab96de7e AS |
10516 | #undef TARGET_HANDLE_OPTION |
10517 | #define TARGET_HANDLE_OPTION s390_handle_option | |
38899e29 | 10518 | |
c5387660 JM |
10519 | #undef TARGET_OPTION_OVERRIDE |
10520 | #define TARGET_OPTION_OVERRIDE s390_option_override | |
10521 | ||
3020190e JM |
10522 | #undef TARGET_OPTION_OPTIMIZATION_TABLE |
10523 | #define TARGET_OPTION_OPTIMIZATION_TABLE s390_option_optimization_table | |
fac0f722 | 10524 | |
7e4aae92 JM |
10525 | #undef TARGET_OPTION_INIT_STRUCT |
10526 | #define TARGET_OPTION_INIT_STRUCT s390_option_init_struct | |
10527 | ||
ab96de7e AS |
10528 | #undef TARGET_ENCODE_SECTION_INFO |
10529 | #define TARGET_ENCODE_SECTION_INFO s390_encode_section_info | |
ed9676cf | 10530 | |
9602b6a1 AK |
10531 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
10532 | #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p | |
10533 | ||
ab96de7e AS |
10534 | #ifdef HAVE_AS_TLS |
10535 | #undef TARGET_HAVE_TLS | |
10536 | #define TARGET_HAVE_TLS true | |
10537 | #endif | |
10538 | #undef TARGET_CANNOT_FORCE_CONST_MEM | |
10539 | #define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem | |
ed9676cf | 10540 | |
ab96de7e AS |
10541 | #undef TARGET_DELEGITIMIZE_ADDRESS |
10542 | #define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address | |
ed9676cf | 10543 | |
506d7b68 PB |
10544 | #undef TARGET_LEGITIMIZE_ADDRESS |
10545 | #define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address | |
10546 | ||
ab96de7e AS |
10547 | #undef TARGET_RETURN_IN_MEMORY |
10548 | #define TARGET_RETURN_IN_MEMORY s390_return_in_memory | |
38899e29 | 10549 | |
ab96de7e AS |
10550 | #undef TARGET_INIT_BUILTINS |
10551 | #define TARGET_INIT_BUILTINS s390_init_builtins | |
10552 | #undef TARGET_EXPAND_BUILTIN | |
10553 | #define TARGET_EXPAND_BUILTIN s390_expand_builtin | |
38899e29 | 10554 | |
ab96de7e AS |
10555 | #undef TARGET_ASM_OUTPUT_MI_THUNK |
10556 | #define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk | |
10557 | #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK | |
3101faab | 10558 | #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true |
ed9676cf | 10559 | |
ab96de7e AS |
10560 | #undef TARGET_SCHED_ADJUST_PRIORITY |
10561 | #define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority | |
10562 | #undef TARGET_SCHED_ISSUE_RATE | |
10563 | #define TARGET_SCHED_ISSUE_RATE s390_issue_rate | |
10564 | #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD | |
10565 | #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead | |
38899e29 | 10566 | |
3a892e44 AK |
10567 | #undef TARGET_SCHED_VARIABLE_ISSUE |
10568 | #define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue | |
10569 | #undef TARGET_SCHED_REORDER | |
10570 | #define TARGET_SCHED_REORDER s390_sched_reorder | |
244e6c5c AK |
10571 | #undef TARGET_SCHED_INIT |
10572 | #define TARGET_SCHED_INIT s390_sched_init | |
3a892e44 | 10573 | |
ab96de7e AS |
10574 | #undef TARGET_CANNOT_COPY_INSN_P |
10575 | #define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p | |
10576 | #undef TARGET_RTX_COSTS | |
10577 | #define TARGET_RTX_COSTS s390_rtx_costs | |
10578 | #undef TARGET_ADDRESS_COST | |
10579 | #define TARGET_ADDRESS_COST s390_address_cost | |
38899e29 | 10580 | |
ab96de7e AS |
10581 | #undef TARGET_MACHINE_DEPENDENT_REORG |
10582 | #define TARGET_MACHINE_DEPENDENT_REORG s390_reorg | |
8a512b77 | 10583 | |
ab96de7e AS |
10584 | #undef TARGET_VALID_POINTER_MODE |
10585 | #define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode | |
38899e29 | 10586 | |
ab96de7e AS |
10587 | #undef TARGET_BUILD_BUILTIN_VA_LIST |
10588 | #define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list | |
d7bd8aeb JJ |
10589 | #undef TARGET_EXPAND_BUILTIN_VA_START |
10590 | #define TARGET_EXPAND_BUILTIN_VA_START s390_va_start | |
ab96de7e AS |
10591 | #undef TARGET_GIMPLIFY_VA_ARG_EXPR |
10592 | #define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg | |
4798630c | 10593 | |
cde0f3fd PB |
10594 | #undef TARGET_PROMOTE_FUNCTION_MODE |
10595 | #define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode | |
ab96de7e AS |
10596 | #undef TARGET_PASS_BY_REFERENCE |
10597 | #define TARGET_PASS_BY_REFERENCE s390_pass_by_reference | |
4798630c | 10598 | |
ab96de7e AS |
10599 | #undef TARGET_FUNCTION_OK_FOR_SIBCALL |
10600 | #define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall | |
3cb1da52 NF |
10601 | #undef TARGET_FUNCTION_ARG |
10602 | #define TARGET_FUNCTION_ARG s390_function_arg | |
10603 | #undef TARGET_FUNCTION_ARG_ADVANCE | |
10604 | #define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance | |
4798630c | 10605 | |
ab96de7e AS |
10606 | #undef TARGET_FIXED_CONDITION_CODE_REGS |
10607 | #define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs | |
4798630c | 10608 | |
ab96de7e AS |
10609 | #undef TARGET_CC_MODES_COMPATIBLE |
10610 | #define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible | |
4798630c | 10611 | |
e7e64a25 | 10612 | #undef TARGET_INVALID_WITHIN_DOLOOP |
3101faab | 10613 | #define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null |
c08b81aa | 10614 | |
fdbe66f2 EB |
10615 | #ifdef HAVE_AS_TLS |
10616 | #undef TARGET_ASM_OUTPUT_DWARF_DTPREL | |
10617 | #define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel | |
10618 | #endif | |
10619 | ||
7269aee7 | 10620 | #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING |
608063c3 JB |
10621 | #undef TARGET_MANGLE_TYPE |
10622 | #define TARGET_MANGLE_TYPE s390_mangle_type | |
7269aee7 AH |
10623 | #endif |
10624 | ||
4dc19cc0 AK |
10625 | #undef TARGET_SCALAR_MODE_SUPPORTED_P |
10626 | #define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p | |
10627 | ||
833cd70a AK |
10628 | #undef TARGET_SECONDARY_RELOAD |
10629 | #define TARGET_SECONDARY_RELOAD s390_secondary_reload | |
10630 | ||
c7ff6e7a AK |
10631 | #undef TARGET_LIBGCC_CMP_RETURN_MODE |
10632 | #define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode | |
10633 | ||
10634 | #undef TARGET_LIBGCC_SHIFT_COUNT_MODE | |
10635 | #define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode | |
10636 | ||
c6c3dba9 PB |
10637 | #undef TARGET_LEGITIMATE_ADDRESS_P |
10638 | #define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p | |
10639 | ||
7b5cbb57 AS |
10640 | #undef TARGET_CAN_ELIMINATE |
10641 | #define TARGET_CAN_ELIMINATE s390_can_eliminate | |
10642 | ||
40ac4f73 CB |
10643 | #undef TARGET_LOOP_UNROLL_ADJUST |
10644 | #define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust | |
10645 | ||
b81ecf6f RH |
10646 | #undef TARGET_ASM_TRAMPOLINE_TEMPLATE |
10647 | #define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template | |
10648 | #undef TARGET_TRAMPOLINE_INIT | |
10649 | #define TARGET_TRAMPOLINE_INIT s390_trampoline_init | |
10650 | ||
9602b6a1 AK |
10651 | #undef TARGET_UNWIND_WORD_MODE |
10652 | #define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode | |
10653 | ||
ab96de7e | 10654 | struct gcc_target targetm = TARGET_INITIALIZER; |
38899e29 | 10655 | |
29742ba4 | 10656 | #include "gt-s390.h" |