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decl.c, [...]: Remove redundant enum from machine_mode.
[thirdparty/gcc.git] / gcc / config / s390 / s390.c
CommitLineData
9db1d521 1/* Subroutines used for code generation on IBM S/390 and zSeries
23a5b65a 2 Copyright (C) 1999-2014 Free Software Foundation, Inc.
9db1d521 3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
963fc8d0
AK		 4 Ulrich Weigand (uweigand@de.ibm.com) and
5 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
9db1d521 6
58add37a 7This file is part of GCC.
9db1d521 8
58add37a
UW		 9GCC is free software; you can redistribute it and/or modify it under
10the terms of the GNU General Public License as published by the Free
2f83c7d6 11Software Foundation; either version 3, or (at your option) any later
58add37a 12version.
9db1d521 13
58add37a
UW		 14GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15WARRANTY; without even the implied warranty of MERCHANTABILITY or
16FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17for more details.
9db1d521
HP		 18
19You should have received a copy of the GNU General Public License
2f83c7d6
NC		 20along with GCC; see the file COPYING3. If not see
21<http://www.gnu.org/licenses/>. */
9db1d521
HP		 22
23#include "config.h"
9db1d521 24#include "system.h"
4977bab6
ZW		 25#include "coretypes.h"
26#include "tm.h"
9db1d521
HP		 27#include "rtl.h"
28#include "tree.h"
d8a2d370
DN		 29#include "print-tree.h"
30#include "stringpool.h"
31#include "stor-layout.h"
32#include "varasm.h"
33#include "calls.h"
9db1d521
HP		 34#include "tm_p.h"
35#include "regs.h"
36#include "hard-reg-set.h"
9db1d521
HP		 37#include "insn-config.h"
38#include "conditions.h"
39#include "output.h"
40#include "insn-attr.h"
41#include "flags.h"
42#include "except.h"
83685514
AM		 43#include "hashtab.h"
44#include "hash-set.h"
45#include "vec.h"
46#include "machmode.h"
47#include "input.h"
9db1d521
HP		 48#include "function.h"
49#include "recog.h"
50#include "expr.h"
7c82a1ed 51#include "reload.h"
718f9c0f 52#include "diagnostic-core.h"
60393bbc
AM		 53#include "predict.h"
54#include "dominance.h"
55#include "cfg.h"
56#include "cfgrtl.h"
57#include "cfganal.h"
58#include "lcm.h"
59#include "cfgbuild.h"
60#include "cfgcleanup.h"
9db1d521
HP		 61#include "basic-block.h"
62#include "ggc.h"
63#include "target.h"
64#include "target-def.h"
0d3c08b6 65#include "debug.h"
f1e639b1 66#include "langhooks.h"
a41c6c53 67#include "optabs.h"
2fb9a547 68#include "hash-table.h"
2fb9a547
AM		 69#include "tree-ssa-alias.h"
70#include "internal-fn.h"
71#include "gimple-fold.h"
72#include "tree-eh.h"
73#include "gimple-expr.h"
74#include "is-a.h"
18f429e2 75#include "gimple.h"
45b0be94 76#include "gimplify.h"
6fb5fa3c 77#include "df.h"
ff5b964d 78#include "params.h"
40ac4f73 79#include "cfgloop.h"
96e45421 80#include "opts.h"
4099494d
RS		 81#include "tree-pass.h"
82#include "context.h"
9b2b7279 83#include "builtins.h"
9dc7a9da 84#include "rtl-iter.h"
9db1d521 85
017e0eb9
MD		 86/* Define the specific costs for a given cpu. */
87
f4aa3848 88struct processor_costs
017e0eb9 89{
98fd0d70 90 /* multiplication */
017e0eb9
MD		 91 const int m; /* cost of an M instruction. */
92 const int mghi; /* cost of an MGHI instruction. */
93 const int mh; /* cost of an MH instruction. */
94 const int mhi; /* cost of an MHI instruction. */
2742a1ed 95 const int ml; /* cost of an ML instruction. */
017e0eb9
MD		 96 const int mr; /* cost of an MR instruction. */
97 const int ms; /* cost of an MS instruction. */
98 const int msg; /* cost of an MSG instruction. */
99 const int msgf; /* cost of an MSGF instruction. */
100 const int msgfr; /* cost of an MSGFR instruction. */
101 const int msgr; /* cost of an MSGR instruction. */
102 const int msr; /* cost of an MSR instruction. */
103 const int mult_df; /* cost of multiplication in DFmode. */
f61a2c7d 104 const int mxbr;
98fd0d70 105 /* square root */
f61a2c7d 106 const int sqxbr; /* cost of square root in TFmode. */
2742a1ed
MD		 107 const int sqdbr; /* cost of square root in DFmode. */
108 const int sqebr; /* cost of square root in SFmode. */
98fd0d70 109 /* multiply and add */
b75d6bab
MD		 110 const int madbr; /* cost of multiply and add in DFmode. */
111 const int maebr; /* cost of multiply and add in SFmode. */
98fd0d70 112 /* division */
f61a2c7d 113 const int dxbr;
98fd0d70 114 const int ddbr;
98fd0d70 115 const int debr;
6fa5b390
MD		 116 const int dlgr;
117 const int dlr;
118 const int dr;
119 const int dsgfr;
120 const int dsgr;
017e0eb9
MD		 121};
122
123const struct processor_costs *s390_cost;
124
125static const
f4aa3848 126struct processor_costs z900_cost =
017e0eb9
MD		 127{
128 COSTS_N_INSNS (5), /* M */
129 COSTS_N_INSNS (10), /* MGHI */
130 COSTS_N_INSNS (5), /* MH */
131 COSTS_N_INSNS (4), /* MHI */
2742a1ed 132 COSTS_N_INSNS (5), /* ML */
017e0eb9
MD		 133 COSTS_N_INSNS (5), /* MR */
134 COSTS_N_INSNS (4), /* MS */
135 COSTS_N_INSNS (15), /* MSG */
136 COSTS_N_INSNS (7), /* MSGF */
137 COSTS_N_INSNS (7), /* MSGFR */
138 COSTS_N_INSNS (10), /* MSGR */
139 COSTS_N_INSNS (4), /* MSR */
140 COSTS_N_INSNS (7), /* multiplication in DFmode */
f61a2c7d
AK		 141 COSTS_N_INSNS (13), /* MXBR */
142 COSTS_N_INSNS (136), /* SQXBR */
2742a1ed
MD		 143 COSTS_N_INSNS (44), /* SQDBR */
144 COSTS_N_INSNS (35), /* SQEBR */
b75d6bab
MD		 145 COSTS_N_INSNS (18), /* MADBR */
146 COSTS_N_INSNS (13), /* MAEBR */
f61a2c7d 147 COSTS_N_INSNS (134), /* DXBR */
98fd0d70 148 COSTS_N_INSNS (30), /* DDBR */
98fd0d70 149 COSTS_N_INSNS (27), /* DEBR */
6fa5b390
MD		 150 COSTS_N_INSNS (220), /* DLGR */
151 COSTS_N_INSNS (34), /* DLR */
152 COSTS_N_INSNS (34), /* DR */
153 COSTS_N_INSNS (32), /* DSGFR */
154 COSTS_N_INSNS (32), /* DSGR */
017e0eb9
MD		 155};
156
157static const
f4aa3848 158struct processor_costs z990_cost =
017e0eb9
MD		 159{
160 COSTS_N_INSNS (4), /* M */
161 COSTS_N_INSNS (2), /* MGHI */
162 COSTS_N_INSNS (2), /* MH */
163 COSTS_N_INSNS (2), /* MHI */
2742a1ed 164 COSTS_N_INSNS (4), /* ML */
017e0eb9
MD		 165 COSTS_N_INSNS (4), /* MR */
166 COSTS_N_INSNS (5), /* MS */
167 COSTS_N_INSNS (6), /* MSG */
168 COSTS_N_INSNS (4), /* MSGF */
169 COSTS_N_INSNS (4), /* MSGFR */
170 COSTS_N_INSNS (4), /* MSGR */
171 COSTS_N_INSNS (4), /* MSR */
172 COSTS_N_INSNS (1), /* multiplication in DFmode */
f61a2c7d
AK		 173 COSTS_N_INSNS (28), /* MXBR */
174 COSTS_N_INSNS (130), /* SQXBR */
2742a1ed
MD		 175 COSTS_N_INSNS (66), /* SQDBR */
176 COSTS_N_INSNS (38), /* SQEBR */
b75d6bab
MD		 177 COSTS_N_INSNS (1), /* MADBR */
178 COSTS_N_INSNS (1), /* MAEBR */
f61a2c7d 179 COSTS_N_INSNS (60), /* DXBR */
98fd0d70 180 COSTS_N_INSNS (40), /* DDBR */
142cd70f 181 COSTS_N_INSNS (26), /* DEBR */
6fa5b390
MD		 182 COSTS_N_INSNS (176), /* DLGR */
183 COSTS_N_INSNS (31), /* DLR */
184 COSTS_N_INSNS (31), /* DR */
185 COSTS_N_INSNS (31), /* DSGFR */
186 COSTS_N_INSNS (31), /* DSGR */
017e0eb9
MD		 187};
188
ec24698e 189static const
f4aa3848 190struct processor_costs z9_109_cost =
ec24698e
UW		 191{
192 COSTS_N_INSNS (4), /* M */
193 COSTS_N_INSNS (2), /* MGHI */
194 COSTS_N_INSNS (2), /* MH */
195 COSTS_N_INSNS (2), /* MHI */
196 COSTS_N_INSNS (4), /* ML */
197 COSTS_N_INSNS (4), /* MR */
198 COSTS_N_INSNS (5), /* MS */
199 COSTS_N_INSNS (6), /* MSG */
200 COSTS_N_INSNS (4), /* MSGF */
201 COSTS_N_INSNS (4), /* MSGFR */
202 COSTS_N_INSNS (4), /* MSGR */
203 COSTS_N_INSNS (4), /* MSR */
204 COSTS_N_INSNS (1), /* multiplication in DFmode */
f61a2c7d
AK		 205 COSTS_N_INSNS (28), /* MXBR */
206 COSTS_N_INSNS (130), /* SQXBR */
ec24698e
UW		 207 COSTS_N_INSNS (66), /* SQDBR */
208 COSTS_N_INSNS (38), /* SQEBR */
209 COSTS_N_INSNS (1), /* MADBR */
210 COSTS_N_INSNS (1), /* MAEBR */
f61a2c7d 211 COSTS_N_INSNS (60), /* DXBR */
ec24698e 212 COSTS_N_INSNS (40), /* DDBR */
142cd70f 213 COSTS_N_INSNS (26), /* DEBR */
ec24698e
UW		 214 COSTS_N_INSNS (30), /* DLGR */
215 COSTS_N_INSNS (23), /* DLR */
216 COSTS_N_INSNS (23), /* DR */
217 COSTS_N_INSNS (24), /* DSGFR */
218 COSTS_N_INSNS (24), /* DSGR */
219};
017e0eb9 220
93538e8e
AK		 221static const
222struct processor_costs z10_cost =
223{
9381e3f1
WG		 224 COSTS_N_INSNS (10), /* M */
225 COSTS_N_INSNS (10), /* MGHI */
226 COSTS_N_INSNS (10), /* MH */
227 COSTS_N_INSNS (10), /* MHI */
228 COSTS_N_INSNS (10), /* ML */
229 COSTS_N_INSNS (10), /* MR */
230 COSTS_N_INSNS (10), /* MS */
231 COSTS_N_INSNS (10), /* MSG */
232 COSTS_N_INSNS (10), /* MSGF */
233 COSTS_N_INSNS (10), /* MSGFR */
234 COSTS_N_INSNS (10), /* MSGR */
235 COSTS_N_INSNS (10), /* MSR */
2cdece44 236 COSTS_N_INSNS (1) , /* multiplication in DFmode */
9381e3f1
WG		 237 COSTS_N_INSNS (50), /* MXBR */
238 COSTS_N_INSNS (120), /* SQXBR */
239 COSTS_N_INSNS (52), /* SQDBR */
93538e8e 240 COSTS_N_INSNS (38), /* SQEBR */
2cdece44
WG		 241 COSTS_N_INSNS (1), /* MADBR */
242 COSTS_N_INSNS (1), /* MAEBR */
9381e3f1
WG		 243 COSTS_N_INSNS (111), /* DXBR */
244 COSTS_N_INSNS (39), /* DDBR */
245 COSTS_N_INSNS (32), /* DEBR */
246 COSTS_N_INSNS (160), /* DLGR */
247 COSTS_N_INSNS (71), /* DLR */
248 COSTS_N_INSNS (71), /* DR */
249 COSTS_N_INSNS (71), /* DSGFR */
250 COSTS_N_INSNS (71), /* DSGR */
93538e8e
AK		 251};
252
65b1d8ea
AK		 253static const
254struct processor_costs z196_cost =
255{
256 COSTS_N_INSNS (7), /* M */
257 COSTS_N_INSNS (5), /* MGHI */
258 COSTS_N_INSNS (5), /* MH */
259 COSTS_N_INSNS (5), /* MHI */
260 COSTS_N_INSNS (7), /* ML */
261 COSTS_N_INSNS (7), /* MR */
262 COSTS_N_INSNS (6), /* MS */
263 COSTS_N_INSNS (8), /* MSG */
264 COSTS_N_INSNS (6), /* MSGF */
265 COSTS_N_INSNS (6), /* MSGFR */
266 COSTS_N_INSNS (8), /* MSGR */
267 COSTS_N_INSNS (6), /* MSR */
268 COSTS_N_INSNS (1) , /* multiplication in DFmode */
269 COSTS_N_INSNS (40), /* MXBR B+40 */
270 COSTS_N_INSNS (100), /* SQXBR B+100 */
271 COSTS_N_INSNS (42), /* SQDBR B+42 */
272 COSTS_N_INSNS (28), /* SQEBR B+28 */
273 COSTS_N_INSNS (1), /* MADBR B */
274 COSTS_N_INSNS (1), /* MAEBR B */
275 COSTS_N_INSNS (101), /* DXBR B+101 */
276 COSTS_N_INSNS (29), /* DDBR */
277 COSTS_N_INSNS (22), /* DEBR */
278 COSTS_N_INSNS (160), /* DLGR cracked */
279 COSTS_N_INSNS (160), /* DLR cracked */
280 COSTS_N_INSNS (160), /* DR expanded */
281 COSTS_N_INSNS (160), /* DSGFR cracked */
282 COSTS_N_INSNS (160), /* DSGR cracked */
283};
284
22ac2c2f
AK		 285static const
286struct processor_costs zEC12_cost =
287{
288 COSTS_N_INSNS (7), /* M */
289 COSTS_N_INSNS (5), /* MGHI */
290 COSTS_N_INSNS (5), /* MH */
291 COSTS_N_INSNS (5), /* MHI */
292 COSTS_N_INSNS (7), /* ML */
293 COSTS_N_INSNS (7), /* MR */
294 COSTS_N_INSNS (6), /* MS */
295 COSTS_N_INSNS (8), /* MSG */
296 COSTS_N_INSNS (6), /* MSGF */
297 COSTS_N_INSNS (6), /* MSGFR */
298 COSTS_N_INSNS (8), /* MSGR */
299 COSTS_N_INSNS (6), /* MSR */
300 COSTS_N_INSNS (1) , /* multiplication in DFmode */
301 COSTS_N_INSNS (40), /* MXBR B+40 */
302 COSTS_N_INSNS (100), /* SQXBR B+100 */
303 COSTS_N_INSNS (42), /* SQDBR B+42 */
304 COSTS_N_INSNS (28), /* SQEBR B+28 */
305 COSTS_N_INSNS (1), /* MADBR B */
306 COSTS_N_INSNS (1), /* MAEBR B */
307 COSTS_N_INSNS (131), /* DXBR B+131 */
308 COSTS_N_INSNS (29), /* DDBR */
309 COSTS_N_INSNS (22), /* DEBR */
310 COSTS_N_INSNS (160), /* DLGR cracked */
311 COSTS_N_INSNS (160), /* DLR cracked */
312 COSTS_N_INSNS (160), /* DR expanded */
313 COSTS_N_INSNS (160), /* DSGFR cracked */
314 COSTS_N_INSNS (160), /* DSGR cracked */
315};
316
9db1d521
HP		 317extern int reload_completed;
318
3a892e44 319/* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
775c43d3 320static rtx_insn *last_scheduled_insn;
3a892e44 321
994fe660
UW		 322/* Structure used to hold the components of a S/390 memory
323 address. A legitimate address on S/390 is of the general
324 form
325 base + index + displacement
326 where any of the components is optional.
327
328 base and index are registers of the class ADDR_REGS,
329 displacement is an unsigned 12-bit immediate constant. */
9db1d521
HP		 330
331struct s390_address
332{
333 rtx base;
334 rtx indx;
335 rtx disp;
3ed99cc9 336 bool pointer;
f01cf809 337 bool literal_pool;
9db1d521
HP		 338};
339
f4aa3848 340/* The following structure is embedded in the machine
adf39f8f
AK		 341 specific part of struct function. */
342
d1b38208 343struct GTY (()) s390_frame_layout
adf39f8f
AK		 344{
345 /* Offset within stack frame. */
346 HOST_WIDE_INT gprs_offset;
347 HOST_WIDE_INT f0_offset;
348 HOST_WIDE_INT f4_offset;
349 HOST_WIDE_INT f8_offset;
350 HOST_WIDE_INT backchain_offset;
fb3712f6
AK		 351
352 /* Number of first and last gpr where slots in the register
353 save area are reserved for. */
354 int first_save_gpr_slot;
355 int last_save_gpr_slot;
356
6455a49e
AK		 357 /* Location (FP register number) where GPRs (r0-r15) should
358 be saved to.
359 0 - does not need to be saved at all
360 -1 - stack slot */
361 signed char gpr_save_slots[16];
362
29742ba4 363 /* Number of first and last gpr to be saved, restored. */
4023fb28
UW		 364 int first_save_gpr;
365 int first_restore_gpr;
366 int last_save_gpr;
b767fc11 367 int last_restore_gpr;
4023fb28 368
f4aa3848
AK		 369 /* Bits standing for floating point registers. Set, if the
370 respective register has to be saved. Starting with reg 16 (f0)
adf39f8f 371 at the rightmost bit.
2cf4c39e
AK		 372 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
373 fpr 15 13 11 9 14 12 10 8 7 5 3 1 6 4 2 0
374 reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 */
adf39f8f
AK		 375 unsigned int fpr_bitmap;
376
377 /* Number of floating point registers f8-f15 which must be saved. */
378 int high_fprs;
379
dc4477f5
AK		 380 /* Set if return address needs to be saved.
381 This flag is set by s390_return_addr_rtx if it could not use
382 the initial value of r14 and therefore depends on r14 saved
383 to the stack. */
adf39f8f
AK		 384 bool save_return_addr_p;
385
29742ba4 386 /* Size of stack frame. */
4023fb28 387 HOST_WIDE_INT frame_size;
adf39f8f
AK		 388};
389
390/* Define the structure for the machine field in struct function. */
391
d1b38208 392struct GTY(()) machine_function
adf39f8f
AK		 393{
394 struct s390_frame_layout frame_layout;
fd3cd001 395
585539a1
UW		 396 /* Literal pool base register. */
397 rtx base_reg;
398
91086990
UW		 399 /* True if we may need to perform branch splitting. */
400 bool split_branches_pending_p;
401
7bcebb25 402 bool has_landing_pad_p;
5a3fe9b6
AK		 403
404 /* True if the current function may contain a tbegin clobbering
405 FPRs. */
406 bool tbegin_p;
4023fb28
UW		 407};
408
adf39f8f
AK		 409/* Few accessor macros for struct cfun->machine->s390_frame_layout. */
410
411#define cfun_frame_layout (cfun->machine->frame_layout)
412#define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
6455a49e
AK		 413#define cfun_save_arg_fprs_p (!!(TARGET_64BIT \
414 ? cfun_frame_layout.fpr_bitmap & 0x0f \
415 : cfun_frame_layout.fpr_bitmap & 0x03))
416#define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
9602b6a1 417 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
b89b22fc 418#define cfun_set_fpr_save(REGNO) (cfun->machine->frame_layout.fpr_bitmap |= \
2cf4c39e 419 (1 << (REGNO - FPR0_REGNUM)))
b89b22fc 420#define cfun_fpr_save_p(REGNO) (!!(cfun->machine->frame_layout.fpr_bitmap & \
2cf4c39e 421 (1 << (REGNO - FPR0_REGNUM))))
6455a49e
AK		 422#define cfun_gpr_save_slot(REGNO) \
423 cfun->machine->frame_layout.gpr_save_slots[REGNO]
adf39f8f 424
29a79fcf
UW		 425/* Number of GPRs and FPRs used for argument passing. */
426#define GP_ARG_NUM_REG 5
427#define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
428
b5c67a49
AK		 429/* A couple of shortcuts. */
430#define CONST_OK_FOR_J(x) \
431 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
432#define CONST_OK_FOR_K(x) \
433 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
ec24698e
UW		 434#define CONST_OK_FOR_Os(x) \
435 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
436#define CONST_OK_FOR_Op(x) \
437 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
438#define CONST_OK_FOR_On(x) \
439 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
b5c67a49 440
74aa8b4b
AK		 441#define REGNO_PAIR_OK(REGNO, MODE) \
442 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
443
b0f86a7e 444/* That's the read ahead of the dynamic branch prediction unit in
65b1d8ea
AK		 445 bytes on a z10 (or higher) CPU. */
446#define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
b0f86a7e 447
d0de9e13
DV		 448static const int s390_hotpatch_trampoline_halfwords_default = 12;
449static const int s390_hotpatch_trampoline_halfwords_max = 1000000;
450static int s390_hotpatch_trampoline_halfwords = -1;
451
452/* Return the argument of the given hotpatch attribute or the default value if
453 no argument is present. */
454
455static inline int
456get_hotpatch_attribute (tree hotpatch_attr)
457{
458 const_tree args;
459
460 args = TREE_VALUE (hotpatch_attr);
461
462 return (args) ?
463 TREE_INT_CST_LOW (TREE_VALUE (args)):
464 s390_hotpatch_trampoline_halfwords_default;
465}
466
467/* Check whether the hotpatch attribute is applied to a function and, if it has
468 an argument, the argument is valid. */
469
470static tree
471s390_handle_hotpatch_attribute (tree *node, tree name, tree args,
472 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
473{
474 if (TREE_CODE (*node) != FUNCTION_DECL)
475 {
476 warning (OPT_Wattributes, "%qE attribute only applies to functions",
477 name);
478 *no_add_attrs = true;
479 }
480 else if (args)
481 {
482 tree expr = TREE_VALUE (args);
483
484 if (TREE_CODE (expr) != INTEGER_CST
485 || !INTEGRAL_TYPE_P (TREE_TYPE (expr))
807e902e 486 || wi::gtu_p (expr, s390_hotpatch_trampoline_halfwords_max))
d0de9e13
DV		 487 {
488 error ("requested %qE attribute is not a non-negative integer"
489 " constant or too large (max. %d)", name,
490 s390_hotpatch_trampoline_halfwords_max);
491 *no_add_attrs = true;
492 }
493 }
494
495 return NULL_TREE;
496}
497
498static const struct attribute_spec s390_attribute_table[] = {
499 { "hotpatch", 0, 1, true, false, false, s390_handle_hotpatch_attribute, false
500 },
501 /* End element. */
502 { NULL, 0, 0, false, false, false, NULL, false }
503};
504
5d304e47
AK		 505/* Return the alignment for LABEL. We default to the -falign-labels
506 value except for the literal pool base label. */
507int
508s390_label_align (rtx label)
509{
e8a54173
DM		 510 rtx_insn *prev_insn = prev_active_insn (label);
511 rtx set, src;
5d304e47
AK		 512
513 if (prev_insn == NULL_RTX)
514 goto old;
515
e8a54173 516 set = single_set (prev_insn);
5d304e47 517
e8a54173 518 if (set == NULL_RTX)
5d304e47
AK		 519 goto old;
520
e8a54173 521 src = SET_SRC (set);
5d304e47
AK		 522
523 /* Don't align literal pool base labels. */
e8a54173
DM		 524 if (GET_CODE (src) == UNSPEC
525 && XINT (src, 1) == UNSPEC_MAIN_BASE)
5d304e47
AK		 526 return 0;
527
528 old:
529 return align_labels_log;
530}
531
ef4bddc2 532static machine_mode
c7ff6e7a
AK		 533s390_libgcc_cmp_return_mode (void)
534{
535 return TARGET_64BIT ? DImode : SImode;
536}
537
ef4bddc2 538static machine_mode
c7ff6e7a
AK		 539s390_libgcc_shift_count_mode (void)
540{
541 return TARGET_64BIT ? DImode : SImode;
542}
543
ef4bddc2 544static machine_mode
9602b6a1
AK		 545s390_unwind_word_mode (void)
546{
547 return TARGET_64BIT ? DImode : SImode;
548}
549
4dc19cc0
AK		 550/* Return true if the back end supports mode MODE. */
551static bool
ef4bddc2 552s390_scalar_mode_supported_p (machine_mode mode)
4dc19cc0 553{
9602b6a1
AK		 554 /* In contrast to the default implementation reject TImode constants on 31bit
555 TARGET_ZARCH for ABI compliance. */
556 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
557 return false;
558
4dc19cc0 559 if (DECIMAL_FLOAT_MODE_P (mode))
a9ab39d3 560 return default_decimal_float_supported_p ();
9602b6a1
AK		 561
562 return default_scalar_mode_supported_p (mode);
4dc19cc0
AK		 563}
564
7bcebb25
AK		 565/* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
566
567void
568s390_set_has_landing_pad_p (bool value)
569{
570 cfun->machine->has_landing_pad_p = value;
571}
29a79fcf 572
69950452
AS		 573/* If two condition code modes are compatible, return a condition code
574 mode which is compatible with both. Otherwise, return
575 VOIDmode. */
576
ef4bddc2
RS		 577static machine_mode
578s390_cc_modes_compatible (machine_mode m1, machine_mode m2)
69950452
AS		 579{
580 if (m1 == m2)
581 return m1;
582
583 switch (m1)
584 {
585 case CCZmode:
586 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
587 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
588 return m2;
589 return VOIDmode;
590
591 case CCSmode:
592 case CCUmode:
593 case CCTmode:
594 case CCSRmode:
595 case CCURmode:
596 case CCZ1mode:
597 if (m2 == CCZmode)
598 return m1;
f4aa3848 599
69950452
AS		 600 return VOIDmode;
601
602 default:
603 return VOIDmode;
604 }
605 return VOIDmode;
606}
607
994fe660 608/* Return true if SET either doesn't set the CC register, or else
c7453384 609 the source and destination have matching CC modes and that
994fe660 610 CC mode is at least as constrained as REQ_MODE. */
c7453384 611
3ed99cc9 612static bool
ef4bddc2 613s390_match_ccmode_set (rtx set, machine_mode req_mode)
9db1d521 614{
ef4bddc2 615 machine_mode set_mode;
9db1d521 616
8d933e31 617 gcc_assert (GET_CODE (set) == SET);
9db1d521
HP		 618
619 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
620 return 1;
621
622 set_mode = GET_MODE (SET_DEST (set));
623 switch (set_mode)
624 {
9db1d521 625 case CCSmode:
07893d4f 626 case CCSRmode:
9db1d521 627 case CCUmode:
07893d4f 628 case CCURmode:
ba956982 629 case CCLmode:
07893d4f
UW		 630 case CCL1mode:
631 case CCL2mode:
5d880bd2 632 case CCL3mode:
07893d4f
UW		 633 case CCT1mode:
634 case CCT2mode:
635 case CCT3mode:
636 if (req_mode != set_mode)
ba956982
UW		 637 return 0;
638 break;
07893d4f 639
9db1d521 640 case CCZmode:
07893d4f
UW		 641 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
642 && req_mode != CCSRmode && req_mode != CCURmode)
9db1d521
HP		 643 return 0;
644 break;
0a3bdf9d
UW		 645
646 case CCAPmode:
647 case CCANmode:
648 if (req_mode != CCAmode)
649 return 0;
650 break;
c7453384 651
9db1d521 652 default:
8d933e31 653 gcc_unreachable ();
9db1d521 654 }
c7453384 655
9db1d521
HP		 656 return (GET_MODE (SET_SRC (set)) == set_mode);
657}
658
c7453384
EC		 659/* Return true if every SET in INSN that sets the CC register
660 has source and destination with matching CC modes and that
661 CC mode is at least as constrained as REQ_MODE.
07893d4f 662 If REQ_MODE is VOIDmode, always return false. */
c7453384 663
3ed99cc9 664bool
ef4bddc2 665s390_match_ccmode (rtx_insn *insn, machine_mode req_mode)
9db1d521
HP		 666{
667 int i;
668
07893d4f
UW		 669 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
670 if (req_mode == VOIDmode)
3ed99cc9 671 return false;
07893d4f 672
9db1d521
HP		 673 if (GET_CODE (PATTERN (insn)) == SET)
674 return s390_match_ccmode_set (PATTERN (insn), req_mode);
675
676 if (GET_CODE (PATTERN (insn)) == PARALLEL)
677 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
678 {
679 rtx set = XVECEXP (PATTERN (insn), 0, i);
680 if (GET_CODE (set) == SET)
681 if (!s390_match_ccmode_set (set, req_mode))
3ed99cc9 682 return false;
9db1d521
HP		 683 }
684
3ed99cc9 685 return true;
9db1d521
HP		 686}
687
c7453384 688/* If a test-under-mask instruction can be used to implement
07893d4f 689 (compare (and ... OP1) OP2), return the CC mode required
c7453384 690 to do that. Otherwise, return VOIDmode.
07893d4f
UW		 691 MIXED is true if the instruction can distinguish between
692 CC1 and CC2 for mixed selected bits (TMxx), it is false
693 if the instruction cannot (TM). */
694
ef4bddc2 695machine_mode
3ed99cc9 696s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
07893d4f
UW		 697{
698 int bit0, bit1;
699
700 /* ??? Fixme: should work on CONST_DOUBLE as well. */
701 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
702 return VOIDmode;
703
00bda920
AK		 704 /* Selected bits all zero: CC0.
705 e.g.: int a; if ((a & (16 + 128)) == 0) */
07893d4f
UW		 706 if (INTVAL (op2) == 0)
707 return CCTmode;
708
f4aa3848 709 /* Selected bits all one: CC3.
00bda920 710 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
07893d4f
UW		 711 if (INTVAL (op2) == INTVAL (op1))
712 return CCT3mode;
713
00bda920
AK		 714 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
715 int a;
716 if ((a & (16 + 128)) == 16) -> CCT1
717 if ((a & (16 + 128)) == 128) -> CCT2 */
07893d4f
UW		 718 if (mixed)
719 {
720 bit1 = exact_log2 (INTVAL (op2));
721 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
722 if (bit0 != -1 && bit1 != -1)
723 return bit0 > bit1 ? CCT1mode : CCT2mode;
724 }
725
726 return VOIDmode;
727}
728
c7453384
EC		 729/* Given a comparison code OP (EQ, NE, etc.) and the operands
730 OP0 and OP1 of a COMPARE, return the mode to be used for the
ba956982
UW		 731 comparison. */
732
ef4bddc2 733machine_mode
9c808aad 734s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
ba956982
UW		 735{
736 switch (code)
737 {
738 case EQ:
739 case NE:
26a89301
UW		 740 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
741 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
742 return CCAPmode;
0a3bdf9d 743 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
b5c67a49 744 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
0a3bdf9d 745 return CCAPmode;
3ef093a8
AK		 746 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
747 || GET_CODE (op1) == NEG)
748 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
ba956982
UW		 749 return CCLmode;
750
07893d4f
UW		 751 if (GET_CODE (op0) == AND)
752 {
753 /* Check whether we can potentially do it via TM. */
ef4bddc2 754 machine_mode ccmode;
07893d4f
UW		 755 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
756 if (ccmode != VOIDmode)
757 {
758 /* Relax CCTmode to CCZmode to allow fall-back to AND
759 if that turns out to be beneficial. */
760 return ccmode == CCTmode ? CCZmode : ccmode;
761 }
762 }
763
c7453384 764 if (register_operand (op0, HImode)
07893d4f
UW		 765 && GET_CODE (op1) == CONST_INT
766 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
767 return CCT3mode;
c7453384 768 if (register_operand (op0, QImode)
07893d4f
UW		 769 && GET_CODE (op1) == CONST_INT
770 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
771 return CCT3mode;
772
ba956982
UW		 773 return CCZmode;
774
775 case LE:
776 case LT:
777 case GE:
778 case GT:
00bda920
AK		 779 /* The only overflow condition of NEG and ABS happens when
780 -INT_MAX is used as parameter, which stays negative. So
f4aa3848 781 we have an overflow from a positive value to a negative.
00bda920 782 Using CCAP mode the resulting cc can be used for comparisons. */
26a89301
UW		 783 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
784 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
785 return CCAPmode;
00bda920
AK		 786
787 /* If constants are involved in an add instruction it is possible to use
788 the resulting cc for comparisons with zero. Knowing the sign of the
35fd3193 789 constant the overflow behavior gets predictable. e.g.:
f4aa3848 790 int a, b; if ((b = a + c) > 0)
00bda920 791 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
26a89301 792 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
71ce1a34
AK		 793 && (CONST_OK_FOR_K (INTVAL (XEXP (op0, 1)))
794 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0, 1)), 'O', "Os")
795 /* Avoid INT32_MIN on 32 bit. */
796 && (!TARGET_ZARCH || INTVAL (XEXP (op0, 1)) != -0x7fffffff - 1))))
26a89301
UW		 797 {
798 if (INTVAL (XEXP((op0), 1)) < 0)
799 return CCANmode;
800 else
801 return CCAPmode;
802 }
803 /* Fall through. */
ba956982
UW		 804 case UNORDERED:
805 case ORDERED:
806 case UNEQ:
807 case UNLE:
808 case UNLT:
809 case UNGE:
810 case UNGT:
811 case LTGT:
07893d4f
UW		 812 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
813 && GET_CODE (op1) != CONST_INT)
814 return CCSRmode;
ba956982
UW		 815 return CCSmode;
816
ba956982
UW		 817 case LTU:
818 case GEU:
3ef093a8
AK		 819 if (GET_CODE (op0) == PLUS
820 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
07893d4f
UW		 821 return CCL1mode;
822
823 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
824 && GET_CODE (op1) != CONST_INT)
825 return CCURmode;
826 return CCUmode;
827
828 case LEU:
ba956982 829 case GTU:
3ef093a8
AK		 830 if (GET_CODE (op0) == MINUS
831 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
07893d4f
UW		 832 return CCL2mode;
833
834 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
835 && GET_CODE (op1) != CONST_INT)
836 return CCURmode;
ba956982
UW		 837 return CCUmode;
838
839 default:
8d933e31 840 gcc_unreachable ();
ba956982
UW		 841 }
842}
843
68f9c5e2
UW		 844/* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
845 that we can implement more efficiently. */
846
c354951b
AK		 847static void
848s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
849 bool op0_preserve_value)
68f9c5e2 850{
c354951b
AK		 851 if (op0_preserve_value)
852 return;
853
68f9c5e2
UW		 854 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
855 if ((*code == EQ || *code == NE)
856 && *op1 == const0_rtx
857 && GET_CODE (*op0) == ZERO_EXTRACT
858 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
859 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
860 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
861 {
862 rtx inner = XEXP (*op0, 0);
863 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
864 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
865 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
866
867 if (len > 0 && len < modesize
868 && pos >= 0 && pos + len <= modesize
869 && modesize <= HOST_BITS_PER_WIDE_INT)
870 {
871 unsigned HOST_WIDE_INT block;
872 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
873 block <<= modesize - pos - len;
874
875 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
876 gen_int_mode (block, GET_MODE (inner)));
877 }
878 }
879
880 /* Narrow AND of memory against immediate to enable TM. */
881 if ((*code == EQ || *code == NE)
882 && *op1 == const0_rtx
883 && GET_CODE (*op0) == AND
884 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
885 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
886 {
887 rtx inner = XEXP (*op0, 0);
888 rtx mask = XEXP (*op0, 1);
889
890 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
891 if (GET_CODE (inner) == SUBREG
892 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
893 && (GET_MODE_SIZE (GET_MODE (inner))
894 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
895 && ((INTVAL (mask)
896 & GET_MODE_MASK (GET_MODE (inner))
897 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
898 == 0))
899 inner = SUBREG_REG (inner);
900
901 /* Do not change volatile MEMs. */
902 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
903 {
904 int part = s390_single_part (XEXP (*op0, 1),
905 GET_MODE (inner), QImode, 0);
906 if (part >= 0)
907 {
908 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
909 inner = adjust_address_nv (inner, QImode, part);
910 *op0 = gen_rtx_AND (QImode, inner, mask);
911 }
912 }
913 }
914
915 /* Narrow comparisons against 0xffff to HImode if possible. */
68f9c5e2
UW		 916 if ((*code == EQ || *code == NE)
917 && GET_CODE (*op1) == CONST_INT
918 && INTVAL (*op1) == 0xffff
919 && SCALAR_INT_MODE_P (GET_MODE (*op0))
f4aa3848 920 && (nonzero_bits (*op0, GET_MODE (*op0))
68f9c5e2
UW		 921 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
922 {
923 *op0 = gen_lowpart (HImode, *op0);
924 *op1 = constm1_rtx;
925 }
5b022de5 926
5a3fe9b6 927 /* Remove redundant UNSPEC_STRCMPCC_TO_INT conversions if possible. */
5b022de5 928 if (GET_CODE (*op0) == UNSPEC
5a3fe9b6 929 && XINT (*op0, 1) == UNSPEC_STRCMPCC_TO_INT
5b022de5
UW		 930 && XVECLEN (*op0, 0) == 1
931 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
932 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
933 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
934 && *op1 == const0_rtx)
935 {
936 enum rtx_code new_code = UNKNOWN;
937 switch (*code)
938 {
939 case EQ: new_code = EQ; break;
940 case NE: new_code = NE; break;
02887425
UW		 941 case LT: new_code = GTU; break;
942 case GT: new_code = LTU; break;
943 case LE: new_code = GEU; break;
944 case GE: new_code = LEU; break;
5b022de5
UW		 945 default: break;
946 }
947
948 if (new_code != UNKNOWN)
949 {
950 *op0 = XVECEXP (*op0, 0, 0);
951 *code = new_code;
952 }
953 }
69950452 954
5a3fe9b6 955 /* Remove redundant UNSPEC_CC_TO_INT conversions if possible. */
638e37c2 956 if (GET_CODE (*op0) == UNSPEC
5a3fe9b6 957 && XINT (*op0, 1) == UNSPEC_CC_TO_INT
638e37c2 958 && XVECLEN (*op0, 0) == 1
638e37c2
WG		 959 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
960 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
5a3fe9b6 961 && CONST_INT_P (*op1))
638e37c2
WG		 962 {
963 enum rtx_code new_code = UNKNOWN;
5a3fe9b6 964 switch (GET_MODE (XVECEXP (*op0, 0, 0)))
638e37c2 965 {
5a3fe9b6
AK		 966 case CCZmode:
967 case CCRAWmode:
968 switch (*code)
969 {
970 case EQ: new_code = EQ; break;
971 case NE: new_code = NE; break;
972 default: break;
973 }
974 break;
975 default: break;
638e37c2
WG		 976 }
977
978 if (new_code != UNKNOWN)
979 {
5a3fe9b6
AK		 980 /* For CCRAWmode put the required cc mask into the second
981 operand. */
2561451d
AK		 982 if (GET_MODE (XVECEXP (*op0, 0, 0)) == CCRAWmode
983 && INTVAL (*op1) >= 0 && INTVAL (*op1) <= 3)
5a3fe9b6 984 *op1 = gen_rtx_CONST_INT (VOIDmode, 1 << (3 - INTVAL (*op1)));
638e37c2
WG		 985 *op0 = XVECEXP (*op0, 0, 0);
986 *code = new_code;
987 }
988 }
989
69950452
AS		 990 /* Simplify cascaded EQ, NE with const0_rtx. */
991 if ((*code == NE || *code == EQ)
992 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
993 && GET_MODE (*op0) == SImode
994 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
995 && REG_P (XEXP (*op0, 0))
996 && XEXP (*op0, 1) == const0_rtx
997 && *op1 == const0_rtx)
998 {
999 if ((*code == EQ && GET_CODE (*op0) == NE)
1000 || (*code == NE && GET_CODE (*op0) == EQ))
1001 *code = EQ;
1002 else
1003 *code = NE;
1004 *op0 = XEXP (*op0, 0);
1005 }
c5b2a111
UW		 1006
1007 /* Prefer register over memory as first operand. */
1008 if (MEM_P (*op0) && REG_P (*op1))
1009 {
1010 rtx tem = *op0; *op0 = *op1; *op1 = tem;
c354951b 1011 *code = (int)swap_condition ((enum rtx_code)*code);
c5b2a111 1012 }
68f9c5e2
UW		 1013}
1014
6590e19a
UW		 1015/* Emit a compare instruction suitable to implement the comparison
1016 OP0 CODE OP1. Return the correct condition RTL to be placed in
1017 the IF_THEN_ELSE of the conditional branch testing the result. */
1018
1019rtx
1020s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
1021{
ef4bddc2 1022 machine_mode mode = s390_select_ccmode (code, op0, op1);
4a77c72b 1023 rtx cc;
6590e19a 1024
e0374221 1025 /* Do not output a redundant compare instruction if a compare_and_swap
69950452 1026 pattern already computed the result and the machine modes are compatible. */
4a77c72b
PB		 1027 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
1028 {
1029 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
1030 == GET_MODE (op0));
1031 cc = op0;
1032 }
e0374221
AS		 1033 else
1034 {
4a77c72b 1035 cc = gen_rtx_REG (mode, CC_REGNUM);
e0374221 1036 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
e0374221 1037 }
4a77c72b 1038
f4aa3848 1039 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
6590e19a
UW		 1040}
1041
0a2aaacc 1042/* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
8bb501bb
AK		 1043 matches CMP.
1044 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
1045 conditional branch testing the result. */
1046
1047static rtx
78ce265b
RH		 1048s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem,
1049 rtx cmp, rtx new_rtx)
8bb501bb 1050{
78ce265b
RH		 1051 emit_insn (gen_atomic_compare_and_swapsi_internal (old, mem, cmp, new_rtx));
1052 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM),
1053 const0_rtx);
8bb501bb
AK		 1054}
1055
5a3fe9b6
AK		 1056/* Emit a jump instruction to TARGET and return it. If COND is
1057 NULL_RTX, emit an unconditional jump, else a conditional jump under
1058 condition COND. */
6590e19a 1059
775c43d3 1060rtx_insn *
6590e19a
UW		 1061s390_emit_jump (rtx target, rtx cond)
1062{
1063 rtx insn;
1064
1065 target = gen_rtx_LABEL_REF (VOIDmode, target);
1066 if (cond)
1067 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
1068
1069 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
5a3fe9b6 1070 return emit_jump_insn (insn);
6590e19a
UW		 1071}
1072
c7453384 1073/* Return branch condition mask to implement a branch
5b022de5 1074 specified by CODE. Return -1 for invalid comparisons. */
ba956982 1075
0bfc3f69 1076int
9c808aad 1077s390_branch_condition_mask (rtx code)
c7453384 1078{
ba956982
UW		 1079 const int CC0 = 1 << 3;
1080 const int CC1 = 1 << 2;
1081 const int CC2 = 1 << 1;
1082 const int CC3 = 1 << 0;
1083
8d933e31
AS		 1084 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
1085 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
5a3fe9b6
AK		 1086 gcc_assert (XEXP (code, 1) == const0_rtx
1087 || (GET_MODE (XEXP (code, 0)) == CCRAWmode
1088 && CONST_INT_P (XEXP (code, 1))));
1089
ba956982
UW		 1090
1091 switch (GET_MODE (XEXP (code, 0)))
1092 {
1093 case CCZmode:
69950452 1094 case CCZ1mode:
ba956982
UW		 1095 switch (GET_CODE (code))
1096 {
1097 case EQ: return CC0;
1098 case NE: return CC1 | CC2 | CC3;
5b022de5 1099 default: return -1;
ba956982
UW		 1100 }
1101 break;
1102
07893d4f
UW		 1103 case CCT1mode:
1104 switch (GET_CODE (code))
1105 {
1106 case EQ: return CC1;
1107 case NE: return CC0 | CC2 | CC3;
5b022de5 1108 default: return -1;
07893d4f
UW		 1109 }
1110 break;
1111
1112 case CCT2mode:
1113 switch (GET_CODE (code))
1114 {
1115 case EQ: return CC2;
1116 case NE: return CC0 | CC1 | CC3;
5b022de5 1117 default: return -1;
07893d4f
UW		 1118 }
1119 break;
1120
1121 case CCT3mode:
1122 switch (GET_CODE (code))
1123 {
1124 case EQ: return CC3;
1125 case NE: return CC0 | CC1 | CC2;
5b022de5 1126 default: return -1;
07893d4f
UW		 1127 }
1128 break;
1129
ba956982
UW		 1130 case CCLmode:
1131 switch (GET_CODE (code))
1132 {
1133 case EQ: return CC0 | CC2;
1134 case NE: return CC1 | CC3;
5b022de5 1135 default: return -1;
07893d4f
UW		 1136 }
1137 break;
1138
1139 case CCL1mode:
1140 switch (GET_CODE (code))
1141 {
1142 case LTU: return CC2 | CC3; /* carry */
1143 case GEU: return CC0 | CC1; /* no carry */
5b022de5 1144 default: return -1;
07893d4f
UW		 1145 }
1146 break;
1147
1148 case CCL2mode:
1149 switch (GET_CODE (code))
1150 {
1151 case GTU: return CC0 | CC1; /* borrow */
1152 case LEU: return CC2 | CC3; /* no borrow */
5b022de5 1153 default: return -1;
ba956982
UW		 1154 }
1155 break;
1156
5d880bd2
UW		 1157 case CCL3mode:
1158 switch (GET_CODE (code))
1159 {
1160 case EQ: return CC0 | CC2;
1161 case NE: return CC1 | CC3;
1162 case LTU: return CC1;
1163 case GTU: return CC3;
1164 case LEU: return CC1 | CC2;
1165 case GEU: return CC2 | CC3;
5b022de5 1166 default: return -1;
5d880bd2
UW		 1167 }
1168
ba956982
UW		 1169 case CCUmode:
1170 switch (GET_CODE (code))
1171 {
1172 case EQ: return CC0;
1173 case NE: return CC1 | CC2 | CC3;
1174 case LTU: return CC1;
1175 case GTU: return CC2;
1176 case LEU: return CC0 | CC1;
1177 case GEU: return CC0 | CC2;
5b022de5 1178 default: return -1;
ba956982
UW		 1179 }
1180 break;
1181
07893d4f
UW		 1182 case CCURmode:
1183 switch (GET_CODE (code))
1184 {
1185 case EQ: return CC0;
1186 case NE: return CC2 | CC1 | CC3;
1187 case LTU: return CC2;
1188 case GTU: return CC1;
1189 case LEU: return CC0 | CC2;
1190 case GEU: return CC0 | CC1;
5b022de5 1191 default: return -1;
07893d4f
UW		 1192 }
1193 break;
1194
0a3bdf9d
UW		 1195 case CCAPmode:
1196 switch (GET_CODE (code))
1197 {
1198 case EQ: return CC0;
1199 case NE: return CC1 | CC2 | CC3;
1200 case LT: return CC1 | CC3;
1201 case GT: return CC2;
1202 case LE: return CC0 | CC1 | CC3;
1203 case GE: return CC0 | CC2;
5b022de5 1204 default: return -1;
0a3bdf9d
UW		 1205 }
1206 break;
1207
1208 case CCANmode:
1209 switch (GET_CODE (code))
1210 {
1211 case EQ: return CC0;
1212 case NE: return CC1 | CC2 | CC3;
1213 case LT: return CC1;
1214 case GT: return CC2 | CC3;
1215 case LE: return CC0 | CC1;
1216 case GE: return CC0 | CC2 | CC3;
5b022de5 1217 default: return -1;
0a3bdf9d
UW		 1218 }
1219 break;
1220
ba956982
UW		 1221 case CCSmode:
1222 switch (GET_CODE (code))
1223 {
1224 case EQ: return CC0;
1225 case NE: return CC1 | CC2 | CC3;
1226 case LT: return CC1;
1227 case GT: return CC2;
1228 case LE: return CC0 | CC1;
1229 case GE: return CC0 | CC2;
1230 case UNORDERED: return CC3;
1231 case ORDERED: return CC0 | CC1 | CC2;
1232 case UNEQ: return CC0 | CC3;
1233 case UNLT: return CC1 | CC3;
1234 case UNGT: return CC2 | CC3;
1235 case UNLE: return CC0 | CC1 | CC3;
1236 case UNGE: return CC0 | CC2 | CC3;
1237 case LTGT: return CC1 | CC2;
5b022de5 1238 default: return -1;
ba956982 1239 }
07893d4f
UW		 1240 break;
1241
1242 case CCSRmode:
1243 switch (GET_CODE (code))
1244 {
1245 case EQ: return CC0;
1246 case NE: return CC2 | CC1 | CC3;
1247 case LT: return CC2;
1248 case GT: return CC1;
1249 case LE: return CC0 | CC2;
1250 case GE: return CC0 | CC1;
1251 case UNORDERED: return CC3;
1252 case ORDERED: return CC0 | CC2 | CC1;
1253 case UNEQ: return CC0 | CC3;
1254 case UNLT: return CC2 | CC3;
1255 case UNGT: return CC1 | CC3;
1256 case UNLE: return CC0 | CC2 | CC3;
1257 case UNGE: return CC0 | CC1 | CC3;
1258 case LTGT: return CC2 | CC1;
5b022de5 1259 default: return -1;
07893d4f
UW		 1260 }
1261 break;
ba956982 1262
5a3fe9b6
AK		 1263 case CCRAWmode:
1264 switch (GET_CODE (code))
1265 {
1266 case EQ:
1267 return INTVAL (XEXP (code, 1));
1268 case NE:
1269 return (INTVAL (XEXP (code, 1))) ^ 0xf;
1270 default:
1271 gcc_unreachable ();
1272 }
1273
ba956982 1274 default:
5b022de5 1275 return -1;
ba956982
UW		 1276 }
1277}
1278
963fc8d0
AK		 1279
1280/* Return branch condition mask to implement a compare and branch
1281 specified by CODE. Return -1 for invalid comparisons. */
1282
1283int
1284s390_compare_and_branch_condition_mask (rtx code)
1285{
1286 const int CC0 = 1 << 3;
1287 const int CC1 = 1 << 2;
1288 const int CC2 = 1 << 1;
1289
1290 switch (GET_CODE (code))
1291 {
1292 case EQ:
1293 return CC0;
1294 case NE:
1295 return CC1 | CC2;
1296 case LT:
1297 case LTU:
1298 return CC1;
1299 case GT:
1300 case GTU:
1301 return CC2;
1302 case LE:
1303 case LEU:
1304 return CC0 | CC1;
1305 case GE:
1306 case GEU:
1307 return CC0 | CC2;
1308 default:
1309 gcc_unreachable ();
1310 }
1311 return -1;
1312}
1313
c7453384
EC		 1314/* If INV is false, return assembler mnemonic string to implement
1315 a branch specified by CODE. If INV is true, return mnemonic
ba956982
UW		 1316 for the corresponding inverted branch. */
1317
1318static const char *
9c808aad 1319s390_branch_condition_mnemonic (rtx code, int inv)
ba956982 1320{
963fc8d0
AK		 1321 int mask;
1322
0139adca 1323 static const char *const mnemonic[16] =
ba956982
UW		 1324 {
1325 NULL, "o", "h", "nle",
1326 "l", "nhe", "lh", "ne",
1327 "e", "nlh", "he", "nl",
1328 "le", "nh", "no", NULL
1329 };
1330
963fc8d0
AK		 1331 if (GET_CODE (XEXP (code, 0)) == REG
1332 && REGNO (XEXP (code, 0)) == CC_REGNUM
5a3fe9b6
AK		 1333 && (XEXP (code, 1) == const0_rtx
1334 || (GET_MODE (XEXP (code, 0)) == CCRAWmode
1335 && CONST_INT_P (XEXP (code, 1)))))
963fc8d0
AK		 1336 mask = s390_branch_condition_mask (code);
1337 else
1338 mask = s390_compare_and_branch_condition_mask (code);
1339
5b022de5 1340 gcc_assert (mask >= 0);
ba956982
UW		 1341
1342 if (inv)
1343 mask ^= 15;
1344
8d933e31 1345 gcc_assert (mask >= 1 && mask <= 14);
ba956982
UW		 1346
1347 return mnemonic[mask];
1348}
1349
f19a9af7
AK		 1350/* Return the part of op which has a value different from def.
1351 The size of the part is determined by mode.
38899e29 1352 Use this function only if you already know that op really
f19a9af7 1353 contains such a part. */
4023fb28 1354
f19a9af7 1355unsigned HOST_WIDE_INT
ef4bddc2 1356s390_extract_part (rtx op, machine_mode mode, int def)
4023fb28 1357{
f19a9af7
AK		 1358 unsigned HOST_WIDE_INT value = 0;
1359 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1360 int part_bits = GET_MODE_BITSIZE (mode);
c4d50129
AK		 1361 unsigned HOST_WIDE_INT part_mask
1362 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
f19a9af7 1363 int i;
38899e29 1364
f19a9af7 1365 for (i = 0; i < max_parts; i++)
4023fb28 1366 {
f19a9af7
AK		 1367 if (i == 0)
1368 value = (unsigned HOST_WIDE_INT) INTVAL (op);
4023fb28 1369 else
f19a9af7 1370 value >>= part_bits;
38899e29 1371
f19a9af7
AK		 1372 if ((value & part_mask) != (def & part_mask))
1373 return value & part_mask;
4023fb28 1374 }
38899e29 1375
8d933e31 1376 gcc_unreachable ();
4023fb28
UW		 1377}
1378
1379/* If OP is an integer constant of mode MODE with exactly one
f19a9af7
AK		 1380 part of mode PART_MODE unequal to DEF, return the number of that
1381 part. Otherwise, return -1. */
4023fb28
UW		 1382
1383int
38899e29 1384s390_single_part (rtx op,
ef4bddc2
RS		 1385 machine_mode mode,
1386 machine_mode part_mode,
f19a9af7
AK		 1387 int def)
1388{
1389 unsigned HOST_WIDE_INT value = 0;
1390 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
c4d50129
AK		 1391 unsigned HOST_WIDE_INT part_mask
1392 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
f19a9af7
AK		 1393 int i, part = -1;
1394
1395 if (GET_CODE (op) != CONST_INT)
1396 return -1;
38899e29 1397
f19a9af7
AK		 1398 for (i = 0; i < n_parts; i++)
1399 {
1400 if (i == 0)
1401 value = (unsigned HOST_WIDE_INT) INTVAL (op);
4023fb28 1402 else
f19a9af7 1403 value >>= GET_MODE_BITSIZE (part_mode);
38899e29 1404
f19a9af7
AK		 1405 if ((value & part_mask) != (def & part_mask))
1406 {
1407 if (part != -1)
1408 return -1;
1409 else
1410 part = i;
1411 }
4023fb28 1412 }
f19a9af7 1413 return part == -1 ? -1 : n_parts - 1 - part;
4023fb28
UW		 1414}
1415
963fc8d0
AK		 1416/* Return true if IN contains a contiguous bitfield in the lower SIZE
1417 bits and no other bits are set in IN. POS and LENGTH can be used
1418 to obtain the start position and the length of the bitfield.
1419
1420 POS gives the position of the first bit of the bitfield counting
1421 from the lowest order bit starting with zero. In order to use this
1422 value for S/390 instructions this has to be converted to "bits big
1423 endian" style. */
1424
1425bool
1426s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1427 int *pos, int *length)
1428{
1429 int tmp_pos = 0;
1430 int tmp_length = 0;
1431 int i;
1432 unsigned HOST_WIDE_INT mask = 1ULL;
1433 bool contiguous = false;
1434
1435 for (i = 0; i < size; mask <<= 1, i++)
1436 {
1437 if (contiguous)
1438 {
1439 if (mask & in)
1440 tmp_length++;
1441 else
1442 break;
1443 }
1444 else
1445 {
1446 if (mask & in)
1447 {
1448 contiguous = true;
1449 tmp_length++;
1450 }
1451 else
1452 tmp_pos++;
1453 }
1454 }
1455
1456 if (!tmp_length)
1457 return false;
1458
1459 /* Calculate a mask for all bits beyond the contiguous bits. */
1460 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1461
1462 if (mask & in)
1463 return false;
1464
1465 if (tmp_length + tmp_pos - 1 > size)
1466 return false;
1467
1468 if (length)
1469 *length = tmp_length;
1470
1471 if (pos)
1472 *pos = tmp_pos;
1473
1474 return true;
1475}
1476
1a2e356e
RH		 1477/* Check whether a rotate of ROTL followed by an AND of CONTIG is
1478 equivalent to a shift followed by the AND. In particular, CONTIG
1479 should not overlap the (rotated) bit 0/bit 63 gap. Negative values
1480 for ROTL indicate a rotate to the right. */
1481
1482bool
1483s390_extzv_shift_ok (int bitsize, int rotl, unsigned HOST_WIDE_INT contig)
1484{
1485 int pos, len;
1486 bool ok;
1487
1488 ok = s390_contiguous_bitmask_p (contig, bitsize, &pos, &len);
1489 gcc_assert (ok);
1490
1491 return ((rotl >= 0 && rotl <= pos)
1492 || (rotl < 0 && -rotl <= bitsize - len - pos));
1493}
1494
c7453384
EC		 1495/* Check whether we can (and want to) split a double-word
1496 move in mode MODE from SRC to DST into two single-word
dc65c307
UW		 1497 moves, moving the subword FIRST_SUBWORD first. */
1498
1499bool
ef4bddc2 1500s390_split_ok_p (rtx dst, rtx src, machine_mode mode, int first_subword)
dc65c307
UW		 1501{
1502 /* Floating point registers cannot be split. */
1503 if (FP_REG_P (src) || FP_REG_P (dst))
1504 return false;
1505
fae778eb 1506 /* We don't need to split if operands are directly accessible. */
dc65c307
UW		 1507 if (s_operand (src, mode) || s_operand (dst, mode))
1508 return false;
1509
1510 /* Non-offsettable memory references cannot be split. */
1511 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1512 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1513 return false;
1514
1515 /* Moving the first subword must not clobber a register
1516 needed to move the second subword. */
1517 if (register_operand (dst, mode))
1518 {
1519 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1520 if (reg_overlap_mentioned_p (subreg, src))
1521 return false;
1522 }
1523
1524 return true;
1525}
1526
bcf8c1cc
AK		 1527/* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1528 and [MEM2, MEM2 + SIZE] do overlap and false
1529 otherwise. */
1530
1531bool
1532s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1533{
1534 rtx addr1, addr2, addr_delta;
1535 HOST_WIDE_INT delta;
1536
1537 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1538 return true;
1539
1540 if (size == 0)
1541 return false;
1542
1543 addr1 = XEXP (mem1, 0);
1544 addr2 = XEXP (mem2, 0);
1545
1546 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1547
1548 /* This overlapping check is used by peepholes merging memory block operations.
1549 Overlapping operations would otherwise be recognized by the S/390 hardware
f4aa3848 1550 and would fall back to a slower implementation. Allowing overlapping
bcf8c1cc 1551 operations would lead to slow code but not to wrong code. Therefore we are
f4aa3848 1552 somewhat optimistic if we cannot prove that the memory blocks are
bcf8c1cc
AK		 1553 overlapping.
1554 That's why we return false here although this may accept operations on
1555 overlapping memory areas. */
1556 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1557 return false;
1558
1559 delta = INTVAL (addr_delta);
1560
1561 if (delta == 0
1562 || (delta > 0 && delta < size)
1563 || (delta < 0 && -delta < size))
1564 return true;
1565
1566 return false;
1567}
1568
19b63d8e
UW		 1569/* Check whether the address of memory reference MEM2 equals exactly
1570 the address of memory reference MEM1 plus DELTA. Return true if
1571 we can prove this to be the case, false otherwise. */
1572
1573bool
1574s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1575{
1576 rtx addr1, addr2, addr_delta;
1577
1578 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1579 return false;
1580
1581 addr1 = XEXP (mem1, 0);
1582 addr2 = XEXP (mem2, 0);
1583
1584 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1585 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1586 return false;
1587
1588 return true;
1589}
1590
8cb66696
UW		 1591/* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1592
1593void
ef4bddc2 1594s390_expand_logical_operator (enum rtx_code code, machine_mode mode,
8cb66696
UW		 1595 rtx *operands)
1596{
ef4bddc2 1597 machine_mode wmode = mode;
8cb66696
UW		 1598 rtx dst = operands[0];
1599 rtx src1 = operands[1];
1600 rtx src2 = operands[2];
1601 rtx op, clob, tem;
1602
1603 /* If we cannot handle the operation directly, use a temp register. */
1604 if (!s390_logical_operator_ok_p (operands))
1605 dst = gen_reg_rtx (mode);
1606
1607 /* QImode and HImode patterns make sense only if we have a destination
1608 in memory. Otherwise perform the operation in SImode. */
1609 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1610 wmode = SImode;
1611
1612 /* Widen operands if required. */
1613 if (mode != wmode)
1614 {
1615 if (GET_CODE (dst) == SUBREG
1616 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1617 dst = tem;
1618 else if (REG_P (dst))
1619 dst = gen_rtx_SUBREG (wmode, dst, 0);
1620 else
1621 dst = gen_reg_rtx (wmode);
1622
1623 if (GET_CODE (src1) == SUBREG
1624 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1625 src1 = tem;
1626 else if (GET_MODE (src1) != VOIDmode)
1627 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1628
1629 if (GET_CODE (src2) == SUBREG
1630 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1631 src2 = tem;
1632 else if (GET_MODE (src2) != VOIDmode)
1633 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1634 }
1635
1636 /* Emit the instruction. */
1637 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1638 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1639 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1640
1641 /* Fix up the destination if needed. */
1642 if (dst != operands[0])
1643 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1644}
1645
1646/* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1647
1648bool
1649s390_logical_operator_ok_p (rtx *operands)
1650{
1651 /* If the destination operand is in memory, it needs to coincide
1652 with one of the source operands. After reload, it has to be
1653 the first source operand. */
1654 if (GET_CODE (operands[0]) == MEM)
1655 return rtx_equal_p (operands[0], operands[1])
1656 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1657
1658 return true;
1659}
1660
0dfa6c5e
UW		 1661/* Narrow logical operation CODE of memory operand MEMOP with immediate
1662 operand IMMOP to switch from SS to SI type instructions. */
1663
1664void
1665s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1666{
1667 int def = code == AND ? -1 : 0;
1668 HOST_WIDE_INT mask;
1669 int part;
1670
1671 gcc_assert (GET_CODE (*memop) == MEM);
1672 gcc_assert (!MEM_VOLATILE_P (*memop));
1673
1674 mask = s390_extract_part (*immop, QImode, def);
1675 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1676 gcc_assert (part >= 0);
1677
1678 *memop = adjust_address (*memop, QImode, part);
1679 *immop = gen_int_mode (mask, QImode);
1680}
1681
ba956982 1682
ab96de7e
AS		 1683/* How to allocate a 'struct machine_function'. */
1684
1685static struct machine_function *
1686s390_init_machine_status (void)
1687{
766090c2 1688 return ggc_cleared_alloc<machine_function> ();
ab96de7e
AS		 1689}
1690
9db1d521
HP		 1691/* Map for smallest class containing reg regno. */
1692
0139adca 1693const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
9db1d521
HP		 1694{ GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1695 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1696 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1697 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1698 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1699 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1700 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1701 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
c5aa1d12
UW		 1702 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1703 ACCESS_REGS, ACCESS_REGS
9db1d521
HP		 1704};
1705
077dab3b
HP		 1706/* Return attribute type of insn. */
1707
1708static enum attr_type
647d790d 1709s390_safe_attr_type (rtx_insn *insn)
077dab3b
HP		 1710{
1711 if (recog_memoized (insn) >= 0)
1712 return get_attr_type (insn);
1713 else
1714 return TYPE_NONE;
1715}
9db1d521 1716
d3632d41
UW		 1717/* Return true if DISP is a valid short displacement. */
1718
3ed99cc9 1719static bool
9c808aad 1720s390_short_displacement (rtx disp)
d3632d41
UW		 1721{
1722 /* No displacement is OK. */
1723 if (!disp)
3ed99cc9 1724 return true;
d3632d41 1725
4fe6dea8
AK		 1726 /* Without the long displacement facility we don't need to
1727 distingiush between long and short displacement. */
1728 if (!TARGET_LONG_DISPLACEMENT)
1729 return true;
1730
d3632d41
UW		 1731 /* Integer displacement in range. */
1732 if (GET_CODE (disp) == CONST_INT)
1733 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1734
1735 /* GOT offset is not OK, the GOT can be large. */
1736 if (GET_CODE (disp) == CONST
1737 && GET_CODE (XEXP (disp, 0)) == UNSPEC
227a39fa
UW		 1738 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1739 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
3ed99cc9 1740 return false;
d3632d41
UW		 1741
1742 /* All other symbolic constants are literal pool references,
1743 which are OK as the literal pool must be small. */
1744 if (GET_CODE (disp) == CONST)
3ed99cc9 1745 return true;
d3632d41 1746
3ed99cc9 1747 return false;
d3632d41
UW		 1748}
1749
ab96de7e
AS		 1750/* Decompose a RTL expression ADDR for a memory address into
1751 its components, returned in OUT.
ccfc6cc8 1752
3ed99cc9 1753 Returns false if ADDR is not a valid memory address, true
ab96de7e
AS		 1754 otherwise. If OUT is NULL, don't return the components,
1755 but check for validity only.
ccfc6cc8 1756
ab96de7e
AS		 1757 Note: Only addresses in canonical form are recognized.
1758 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1759 canonical form so that they will be recognized. */
f19a9af7 1760
ab96de7e 1761static int
5d81b82b 1762s390_decompose_address (rtx addr, struct s390_address *out)
ab96de7e
AS		 1763{
1764 HOST_WIDE_INT offset = 0;
1765 rtx base = NULL_RTX;
1766 rtx indx = NULL_RTX;
1767 rtx disp = NULL_RTX;
1768 rtx orig_disp;
3ed99cc9
AS		 1769 bool pointer = false;
1770 bool base_ptr = false;
1771 bool indx_ptr = false;
f01cf809
UW		 1772 bool literal_pool = false;
1773
1774 /* We may need to substitute the literal pool base register into the address
1775 below. However, at this point we do not know which register is going to
1776 be used as base, so we substitute the arg pointer register. This is going
1777 to be treated as holding a pointer below -- it shouldn't be used for any
1778 other purpose. */
1779 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
0dfa6c5e 1780
ab96de7e 1781 /* Decompose address into base + index + displacement. */
0dfa6c5e 1782
ab96de7e
AS		 1783 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1784 base = addr;
0dfa6c5e 1785
ab96de7e 1786 else if (GET_CODE (addr) == PLUS)
e221ef54 1787 {
ab96de7e
AS		 1788 rtx op0 = XEXP (addr, 0);
1789 rtx op1 = XEXP (addr, 1);
1790 enum rtx_code code0 = GET_CODE (op0);
1791 enum rtx_code code1 = GET_CODE (op1);
e221ef54 1792
ab96de7e
AS		 1793 if (code0 == REG || code0 == UNSPEC)
1794 {
1795 if (code1 == REG || code1 == UNSPEC)
1796 {
1797 indx = op0; /* index + base */
1798 base = op1;
1799 }
e221ef54 1800
ab96de7e
AS		 1801 else
1802 {
1803 base = op0; /* base + displacement */
1804 disp = op1;
1805 }
1806 }
ccfc6cc8 1807
ab96de7e 1808 else if (code0 == PLUS)
d3632d41 1809 {
ab96de7e
AS		 1810 indx = XEXP (op0, 0); /* index + base + disp */
1811 base = XEXP (op0, 1);
1812 disp = op1;
d3632d41 1813 }
d3632d41 1814
ab96de7e 1815 else
d3632d41 1816 {
3ed99cc9 1817 return false;
d3632d41 1818 }
ab96de7e 1819 }
d3632d41 1820
ab96de7e
AS		 1821 else
1822 disp = addr; /* displacement */
d3632d41 1823
ab96de7e
AS		 1824 /* Extract integer part of displacement. */
1825 orig_disp = disp;
1826 if (disp)
1827 {
1828 if (GET_CODE (disp) == CONST_INT)
d3632d41 1829 {
ab96de7e
AS		 1830 offset = INTVAL (disp);
1831 disp = NULL_RTX;
d3632d41 1832 }
ab96de7e
AS		 1833 else if (GET_CODE (disp) == CONST
1834 && GET_CODE (XEXP (disp, 0)) == PLUS
1835 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1836 {
1837 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1838 disp = XEXP (XEXP (disp, 0), 0);
1839 }
1840 }
d3632d41 1841
ab96de7e
AS		 1842 /* Strip off CONST here to avoid special case tests later. */
1843 if (disp && GET_CODE (disp) == CONST)
1844 disp = XEXP (disp, 0);
ac32b25e 1845
ab96de7e
AS		 1846 /* We can convert literal pool addresses to
1847 displacements by basing them off the base register. */
1848 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1849 {
1850 /* Either base or index must be free to hold the base register. */
1851 if (!base)
f01cf809 1852 base = fake_pool_base, literal_pool = true;
ab96de7e 1853 else if (!indx)
f01cf809 1854 indx = fake_pool_base, literal_pool = true;
ab96de7e 1855 else
3ed99cc9 1856 return false;
ab96de7e
AS		 1857
1858 /* Mark up the displacement. */
1859 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1860 UNSPEC_LTREL_OFFSET);
d3632d41 1861 }
ccfc6cc8 1862
ab96de7e
AS		 1863 /* Validate base register. */
1864 if (base)
1865 {
1866 if (GET_CODE (base) == UNSPEC)
1867 switch (XINT (base, 1))
1868 {
1869 case UNSPEC_LTREF:
1870 if (!disp)
f4aa3848 1871 disp = gen_rtx_UNSPEC (Pmode,
ab96de7e
AS		 1872 gen_rtvec (1, XVECEXP (base, 0, 0)),
1873 UNSPEC_LTREL_OFFSET);
1874 else
3ed99cc9 1875 return false;
ccfc6cc8 1876
f01cf809 1877 base = XVECEXP (base, 0, 1);
ab96de7e 1878 break;
f19a9af7 1879
ab96de7e 1880 case UNSPEC_LTREL_BASE:
f01cf809
UW		 1881 if (XVECLEN (base, 0) == 1)
1882 base = fake_pool_base, literal_pool = true;
1883 else
1884 base = XVECEXP (base, 0, 1);
ab96de7e 1885 break;
f19a9af7 1886
ab96de7e 1887 default:
3ed99cc9 1888 return false;
ab96de7e 1889 }
f19a9af7 1890
f4aa3848
AK		 1891 if (!REG_P (base)
1892 || (GET_MODE (base) != SImode
93fa8428 1893 && GET_MODE (base) != Pmode))
3ed99cc9 1894 return false;
ab96de7e 1895
f01cf809 1896 if (REGNO (base) == STACK_POINTER_REGNUM
ab96de7e
AS		 1897 || REGNO (base) == FRAME_POINTER_REGNUM
1898 || ((reload_completed || reload_in_progress)
1899 && frame_pointer_needed
1900 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
1901 || REGNO (base) == ARG_POINTER_REGNUM
1902 || (flag_pic
1903 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
3ed99cc9 1904 pointer = base_ptr = true;
f01cf809
UW		 1905
1906 if ((reload_completed || reload_in_progress)
1907 && base == cfun->machine->base_reg)
1908 pointer = base_ptr = literal_pool = true;
ab96de7e
AS		 1909 }
1910
1911 /* Validate index register. */
1912 if (indx)
f19a9af7 1913 {
ab96de7e
AS		 1914 if (GET_CODE (indx) == UNSPEC)
1915 switch (XINT (indx, 1))
1916 {
1917 case UNSPEC_LTREF:
1918 if (!disp)
f4aa3848 1919 disp = gen_rtx_UNSPEC (Pmode,
ab96de7e
AS		 1920 gen_rtvec (1, XVECEXP (indx, 0, 0)),
1921 UNSPEC_LTREL_OFFSET);
1922 else
3ed99cc9 1923 return false;
f19a9af7 1924
f01cf809 1925 indx = XVECEXP (indx, 0, 1);
ab96de7e 1926 break;
f19a9af7 1927
ab96de7e 1928 case UNSPEC_LTREL_BASE:
f01cf809
UW		 1929 if (XVECLEN (indx, 0) == 1)
1930 indx = fake_pool_base, literal_pool = true;
1931 else
1932 indx = XVECEXP (indx, 0, 1);
ab96de7e 1933 break;
f19a9af7 1934
ab96de7e 1935 default:
3ed99cc9 1936 return false;
ab96de7e 1937 }
f19a9af7 1938
f4aa3848 1939 if (!REG_P (indx)
93fa8428
AK		 1940 || (GET_MODE (indx) != SImode
1941 && GET_MODE (indx) != Pmode))
3ed99cc9 1942 return false;
f19a9af7 1943
f01cf809 1944 if (REGNO (indx) == STACK_POINTER_REGNUM
ab96de7e
AS		 1945 || REGNO (indx) == FRAME_POINTER_REGNUM
1946 || ((reload_completed || reload_in_progress)
1947 && frame_pointer_needed
1948 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
1949 || REGNO (indx) == ARG_POINTER_REGNUM
1950 || (flag_pic
1951 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
3ed99cc9 1952 pointer = indx_ptr = true;
f01cf809
UW		 1953
1954 if ((reload_completed || reload_in_progress)
1955 && indx == cfun->machine->base_reg)
1956 pointer = indx_ptr = literal_pool = true;
ab96de7e 1957 }
38899e29 1958
ab96de7e
AS		 1959 /* Prefer to use pointer as base, not index. */
1960 if (base && indx && !base_ptr
1961 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
1962 {
1963 rtx tmp = base;
1964 base = indx;
1965 indx = tmp;
1966 }
f19a9af7 1967
ab96de7e
AS		 1968 /* Validate displacement. */
1969 if (!disp)
1970 {
f4aa3848
AK		 1971 /* If virtual registers are involved, the displacement will change later
1972 anyway as the virtual registers get eliminated. This could make a
1973 valid displacement invalid, but it is more likely to make an invalid
1974 displacement valid, because we sometimes access the register save area
63296cb1 1975 via negative offsets to one of those registers.
ab96de7e
AS		 1976 Thus we don't check the displacement for validity here. If after
1977 elimination the displacement turns out to be invalid after all,
1978 this is fixed up by reload in any case. */
3597e113
VM		 1979 /* LRA maintains always displacements up to date and we need to
1980 know the displacement is right during all LRA not only at the
1981 final elimination. */
1982 if (lra_in_progress
1983 || (base != arg_pointer_rtx
1984 && indx != arg_pointer_rtx
1985 && base != return_address_pointer_rtx
1986 && indx != return_address_pointer_rtx
1987 && base != frame_pointer_rtx
1988 && indx != frame_pointer_rtx
1989 && base != virtual_stack_vars_rtx
1990 && indx != virtual_stack_vars_rtx))
ab96de7e 1991 if (!DISP_IN_RANGE (offset))
3ed99cc9 1992 return false;
ab96de7e
AS		 1993 }
1994 else
1995 {
1996 /* All the special cases are pointers. */
3ed99cc9 1997 pointer = true;
f19a9af7 1998
ab96de7e
AS		 1999 /* In the small-PIC case, the linker converts @GOT
2000 and @GOTNTPOFF offsets to possible displacements. */
2001 if (GET_CODE (disp) == UNSPEC
2002 && (XINT (disp, 1) == UNSPEC_GOT
2003 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
ab96de7e
AS		 2004 && flag_pic == 1)
2005 {
2006 ;
2007 }
f19a9af7 2008
dc66391d
RS		 2009 /* Accept pool label offsets. */
2010 else if (GET_CODE (disp) == UNSPEC
2011 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
2012 ;
f19a9af7 2013
ab96de7e
AS		 2014 /* Accept literal pool references. */
2015 else if (GET_CODE (disp) == UNSPEC
2016 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
2017 {
bc6ce334
AK		 2018 /* In case CSE pulled a non literal pool reference out of
2019 the pool we have to reject the address. This is
2020 especially important when loading the GOT pointer on non
2021 zarch CPUs. In this case the literal pool contains an lt
2022 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
2023 will most likely exceed the displacement. */
2024 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
2025 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp, 0, 0)))
2026 return false;
2027
ab96de7e
AS		 2028 orig_disp = gen_rtx_CONST (Pmode, disp);
2029 if (offset)
2030 {
2031 /* If we have an offset, make sure it does not
2032 exceed the size of the constant pool entry. */
2033 rtx sym = XVECEXP (disp, 0, 0);
2034 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
3ed99cc9 2035 return false;
f19a9af7 2036
0a81f074 2037 orig_disp = plus_constant (Pmode, orig_disp, offset);
ab96de7e
AS		 2038 }
2039 }
2040
2041 else
3ed99cc9 2042 return false;
f19a9af7
AK		 2043 }
2044
ab96de7e 2045 if (!base && !indx)
3ed99cc9 2046 pointer = true;
ab96de7e
AS		 2047
2048 if (out)
2049 {
2050 out->base = base;
2051 out->indx = indx;
2052 out->disp = orig_disp;
2053 out->pointer = pointer;
f01cf809 2054 out->literal_pool = literal_pool;
ab96de7e
AS		 2055 }
2056
3ed99cc9 2057 return true;
f19a9af7
AK		 2058}
2059
d98ad410
UW		 2060/* Decompose a RTL expression OP for a shift count into its components,
2061 and return the base register in BASE and the offset in OFFSET.
2062
d98ad410
UW		 2063 Return true if OP is a valid shift count, false if not. */
2064
2065bool
4989e88a 2066s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
d98ad410
UW		 2067{
2068 HOST_WIDE_INT off = 0;
2069
d98ad410
UW		 2070 /* We can have an integer constant, an address register,
2071 or a sum of the two. */
2072 if (GET_CODE (op) == CONST_INT)
2073 {
2074 off = INTVAL (op);
2075 op = NULL_RTX;
2076 }
2077 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2078 {
2079 off = INTVAL (XEXP (op, 1));
2080 op = XEXP (op, 0);
2081 }
2082 while (op && GET_CODE (op) == SUBREG)
2083 op = SUBREG_REG (op);
2084
2085 if (op && GET_CODE (op) != REG)
2086 return false;
2087
2088 if (offset)
2089 *offset = off;
2090 if (base)
2091 *base = op;
2092
2093 return true;
2094}
2095
2096
ab96de7e 2097/* Return true if CODE is a valid address without index. */
3c50106f 2098
ab96de7e
AS		 2099bool
2100s390_legitimate_address_without_index_p (rtx op)
2101{
2102 struct s390_address addr;
2103
2104 if (!s390_decompose_address (XEXP (op, 0), &addr))
2105 return false;
2106 if (addr.indx)
2107 return false;
2108
2109 return true;
2110}
2111
cd8dc1f9 2112
0ff4390d
AK		 2113/* Return TRUE if ADDR is an operand valid for a load/store relative
2114 instruction. Be aware that the alignment of the operand needs to
2115 be checked separately.
2116 Valid addresses are single references or a sum of a reference and a
2117 constant integer. Return these parts in SYMREF and ADDEND. You can
2118 pass NULL in REF and/or ADDEND if you are not interested in these
2119 values. Literal pool references are *not* considered symbol
2120 references. */
ab96de7e 2121
4fe6dea8 2122static bool
0ff4390d 2123s390_loadrelative_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
ab96de7e 2124{
4fe6dea8 2125 HOST_WIDE_INT tmpaddend = 0;
ab96de7e 2126
4fe6dea8
AK		 2127 if (GET_CODE (addr) == CONST)
2128 addr = XEXP (addr, 0);
2129
2130 if (GET_CODE (addr) == PLUS)
ab96de7e 2131 {
0ff4390d 2132 if (!CONST_INT_P (XEXP (addr, 1)))
4fe6dea8 2133 return false;
ab96de7e 2134
0ff4390d
AK		 2135 tmpaddend = INTVAL (XEXP (addr, 1));
2136 addr = XEXP (addr, 0);
2137 }
98412b77 2138
0ff4390d
AK		 2139 if ((GET_CODE (addr) == SYMBOL_REF && !CONSTANT_POOL_ADDRESS_P (addr))
2140 || (GET_CODE (addr) == UNSPEC
2141 && (XINT (addr, 1) == UNSPEC_GOTENT
2142 || (TARGET_CPU_ZARCH && XINT (addr, 1) == UNSPEC_PLT))))
2143 {
2144 if (symref)
2145 *symref = addr;
2146 if (addend)
2147 *addend = tmpaddend;
98412b77 2148
0ff4390d
AK		 2149 return true;
2150 }
2151 return false;
98412b77 2152}
4fe6dea8
AK		 2153
2154/* Return true if the address in OP is valid for constraint letter C
2155 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2156 pool MEMs should be accepted. Only the Q, R, S, T constraint
2157 letters are allowed for C. */
ab96de7e 2158
4fe6dea8
AK		 2159static int
2160s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2161{
2162 struct s390_address addr;
2163 bool decomposed = false;
2164
2165 /* This check makes sure that no symbolic address (except literal
2166 pool references) are accepted by the R or T constraints. */
0ff4390d 2167 if (s390_loadrelative_operand_p (op, NULL, NULL))
98635b04
UW		 2168 return 0;
2169
2170 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2171 if (!lit_pool_ok)
ab96de7e 2172 {
4fe6dea8 2173 if (!s390_decompose_address (op, &addr))
ab96de7e 2174 return 0;
98635b04 2175 if (addr.literal_pool)
ab96de7e 2176 return 0;
4fe6dea8 2177 decomposed = true;
ab96de7e
AS		 2178 }
2179
2180 switch (c)
2181 {
4fe6dea8
AK		 2182 case 'Q': /* no index short displacement */
2183 if (!decomposed && !s390_decompose_address (op, &addr))
ab96de7e
AS		 2184 return 0;
2185 if (addr.indx)
2186 return 0;
4fe6dea8 2187 if (!s390_short_displacement (addr.disp))
ab96de7e 2188 return 0;
4fe6dea8 2189 break;
ab96de7e 2190
4fe6dea8 2191 case 'R': /* with index short displacement */
ab96de7e
AS		 2192 if (TARGET_LONG_DISPLACEMENT)
2193 {
4fe6dea8 2194 if (!decomposed && !s390_decompose_address (op, &addr))
ab96de7e
AS		 2195 return 0;
2196 if (!s390_short_displacement (addr.disp))
2197 return 0;
2198 }
4fe6dea8
AK		 2199 /* Any invalid address here will be fixed up by reload,
2200 so accept it for the most generic constraint. */
ab96de7e
AS		 2201 break;
2202
4fe6dea8 2203 case 'S': /* no index long displacement */
ab96de7e
AS		 2204 if (!TARGET_LONG_DISPLACEMENT)
2205 return 0;
4fe6dea8 2206 if (!decomposed && !s390_decompose_address (op, &addr))
ab96de7e
AS		 2207 return 0;
2208 if (addr.indx)
2209 return 0;
2210 if (s390_short_displacement (addr.disp))
2211 return 0;
2212 break;
2213
4fe6dea8 2214 case 'T': /* with index long displacement */
ab96de7e
AS		 2215 if (!TARGET_LONG_DISPLACEMENT)
2216 return 0;
4fe6dea8
AK		 2217 /* Any invalid address here will be fixed up by reload,
2218 so accept it for the most generic constraint. */
2219 if ((decomposed || s390_decompose_address (op, &addr))
2220 && s390_short_displacement (addr.disp))
ab96de7e
AS		 2221 return 0;
2222 break;
4fe6dea8
AK		 2223 default:
2224 return 0;
2225 }
2226 return 1;
2227}
ab96de7e 2228
ab96de7e 2229
4fe6dea8
AK		 2230/* Evaluates constraint strings described by the regular expression
2231 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2232 the constraint given in STR, or 0 else. */
2233
2234int
2235s390_mem_constraint (const char *str, rtx op)
2236{
2237 char c = str[0];
2238
2239 switch (c)
2240 {
2241 case 'A':
2242 /* Check for offsettable variants of memory constraints. */
2243 if (!MEM_P (op) || MEM_VOLATILE_P (op))
ab96de7e 2244 return 0;
4fe6dea8
AK		 2245 if ((reload_completed || reload_in_progress)
2246 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
963fc8d0 2247 return 0;
4fe6dea8
AK		 2248 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2249 case 'B':
2250 /* Check for non-literal-pool variants of memory constraints. */
2251 if (!MEM_P (op))
ab96de7e 2252 return 0;
4fe6dea8
AK		 2253 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2254 case 'Q':
2255 case 'R':
2256 case 'S':
2257 case 'T':
2258 if (GET_CODE (op) != MEM)
2259 return 0;
2260 return s390_check_qrst_address (c, XEXP (op, 0), true);
2261 case 'U':
2262 return (s390_check_qrst_address ('Q', op, true)
2263 || s390_check_qrst_address ('R', op, true));
2264 case 'W':
2265 return (s390_check_qrst_address ('S', op, true)
2266 || s390_check_qrst_address ('T', op, true));
ab96de7e 2267 case 'Y':
d98ad410
UW		 2268 /* Simply check for the basic form of a shift count. Reload will
2269 take care of making sure we have a proper base register. */
4989e88a 2270 if (!s390_decompose_shift_count (op, NULL, NULL))
d98ad410
UW		 2271 return 0;
2272 break;
4fe6dea8
AK		 2273 case 'Z':
2274 return s390_check_qrst_address (str[1], op, true);
ab96de7e
AS		 2275 default:
2276 return 0;
2277 }
ab96de7e
AS		 2278 return 1;
2279}
2280
cd8dc1f9 2281
cd8dc1f9
WG		 2282/* Evaluates constraint strings starting with letter O. Input
2283 parameter C is the second letter following the "O" in the constraint
2284 string. Returns 1 if VALUE meets the respective constraint and 0
2285 otherwise. */
ab96de7e 2286
d096725d 2287int
cd8dc1f9 2288s390_O_constraint_str (const char c, HOST_WIDE_INT value)
d096725d 2289{
cd8dc1f9
WG		 2290 if (!TARGET_EXTIMM)
2291 return 0;
d096725d 2292
cd8dc1f9 2293 switch (c)
d096725d 2294 {
cd8dc1f9
WG		 2295 case 's':
2296 return trunc_int_for_mode (value, SImode) == value;
2297
2298 case 'p':
2299 return value == 0
2300 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2301
2302 case 'n':
ee3f3449 2303 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
cd8dc1f9 2304
d096725d 2305 default:
cd8dc1f9 2306 gcc_unreachable ();
d096725d
AS		 2307 }
2308}
2309
cd8dc1f9
WG		 2310
2311/* Evaluates constraint strings starting with letter N. Parameter STR
2312 contains the letters following letter "N" in the constraint string.
2313 Returns true if VALUE matches the constraint. */
d096725d 2314
ab96de7e 2315int
cd8dc1f9 2316s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
ab96de7e 2317{
ef4bddc2 2318 machine_mode mode, part_mode;
ab96de7e
AS		 2319 int def;
2320 int part, part_goal;
2321
ab96de7e 2322
cd8dc1f9
WG		 2323 if (str[0] == 'x')
2324 part_goal = -1;
2325 else
2326 part_goal = str[0] - '0';
ab96de7e 2327
cd8dc1f9
WG		 2328 switch (str[1])
2329 {
2330 case 'Q':
2331 part_mode = QImode;
ab96de7e 2332 break;
cd8dc1f9
WG		 2333 case 'H':
2334 part_mode = HImode;
ec24698e 2335 break;
cd8dc1f9
WG		 2336 case 'S':
2337 part_mode = SImode;
2338 break;
2339 default:
2340 return 0;
2341 }
ec24698e 2342
cd8dc1f9
WG		 2343 switch (str[2])
2344 {
2345 case 'H':
2346 mode = HImode;
2347 break;
2348 case 'S':
2349 mode = SImode;
2350 break;
2351 case 'D':
2352 mode = DImode;
2353 break;
2354 default:
2355 return 0;
2356 }
11598938 2357
cd8dc1f9
WG		 2358 switch (str[3])
2359 {
2360 case '0':
2361 def = 0;
2362 break;
2363 case 'F':
2364 def = -1;
2365 break;
ab96de7e
AS		 2366 default:
2367 return 0;
2368 }
2369
cd8dc1f9
WG		 2370 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2371 return 0;
2372
2373 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2374 if (part < 0)
2375 return 0;
2376 if (part_goal != -1 && part_goal != part)
2377 return 0;
2378
ab96de7e
AS		 2379 return 1;
2380}
2381
cd8dc1f9
WG		 2382
2383/* Returns true if the input parameter VALUE is a float zero. */
2384
2385int
2386s390_float_const_zero_p (rtx value)
2387{
2388 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2389 && value == CONST0_RTX (GET_MODE (value)));
2390}
2391
ccaed3ba
AS		 2392/* Implement TARGET_REGISTER_MOVE_COST. */
2393
2394static int
ef4bddc2 2395s390_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
ccaed3ba
AS		 2396 reg_class_t from, reg_class_t to)
2397{
1dd03b91
AK		 2398 /* On s390, copy between fprs and gprs is expensive as long as no
2399 ldgr/lgdr can be used. */
2400 if ((!TARGET_Z10 || GET_MODE_SIZE (mode) != 8)
2401 && ((reg_classes_intersect_p (from, GENERAL_REGS)
2402 && reg_classes_intersect_p (to, FP_REGS))
2403 || (reg_classes_intersect_p (from, FP_REGS)
2404 && reg_classes_intersect_p (to, GENERAL_REGS))))
ccaed3ba
AS		 2405 return 10;
2406
2407 return 1;
2408}
2409
2410/* Implement TARGET_MEMORY_MOVE_COST. */
2411
2412static int
ef4bddc2 2413s390_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
ccaed3ba
AS		 2414 reg_class_t rclass ATTRIBUTE_UNUSED,
2415 bool in ATTRIBUTE_UNUSED)
2416{
2417 return 1;
2418}
cd8dc1f9 2419
ab96de7e
AS		 2420/* Compute a (partial) cost for rtx X. Return true if the complete
2421 cost has been computed, and false if subexpressions should be
f4aa3848
AK		 2422 scanned. In either case, *TOTAL contains the cost result.
2423 CODE contains GET_CODE (x), OUTER_CODE contains the code
ab96de7e
AS		 2424 of the superexpression of x. */
2425
2426static bool
68f932c4
RS		 2427s390_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
2428 int *total, bool speed ATTRIBUTE_UNUSED)
3c50106f
RH		 2429{
2430 switch (code)
2431 {
2432 case CONST:
3c50106f 2433 case CONST_INT:
3c50106f
RH		 2434 case LABEL_REF:
2435 case SYMBOL_REF:
2436 case CONST_DOUBLE:
6fa5b390 2437 case MEM:
3c50106f
RH		 2438 *total = 0;
2439 return true;
2440
2441 case ASHIFT:
2442 case ASHIFTRT:
2443 case LSHIFTRT:
017e0eb9
MD		 2444 case ROTATE:
2445 case ROTATERT:
3c50106f
RH		 2446 case AND:
2447 case IOR:
2448 case XOR:
3c50106f
RH		 2449 case NEG:
2450 case NOT:
2451 *total = COSTS_N_INSNS (1);
017e0eb9 2452 return false;
3c50106f 2453
2742a1ed
MD		 2454 case PLUS:
2455 case MINUS:
2742a1ed
MD		 2456 *total = COSTS_N_INSNS (1);
2457 return false;
2458
f4aa3848 2459 case MULT:
017e0eb9
MD		 2460 switch (GET_MODE (x))
2461 {
2462 case SImode:
2742a1ed 2463 {
017e0eb9
MD		 2464 rtx left = XEXP (x, 0);
2465 rtx right = XEXP (x, 1);
2466 if (GET_CODE (right) == CONST_INT
b5c67a49 2467 && CONST_OK_FOR_K (INTVAL (right)))
017e0eb9
MD		 2468 *total = s390_cost->mhi;
2469 else if (GET_CODE (left) == SIGN_EXTEND)
2470 *total = s390_cost->mh;
2471 else
2472 *total = s390_cost->ms; /* msr, ms, msy */
2473 break;
2474 }
2475 case DImode:
2476 {
2477 rtx left = XEXP (x, 0);
2478 rtx right = XEXP (x, 1);
9602b6a1 2479 if (TARGET_ZARCH)
017e0eb9
MD		 2480 {
2481 if (GET_CODE (right) == CONST_INT
b5c67a49 2482 && CONST_OK_FOR_K (INTVAL (right)))
017e0eb9
MD		 2483 *total = s390_cost->mghi;
2484 else if (GET_CODE (left) == SIGN_EXTEND)
2485 *total = s390_cost->msgf;
2486 else
2487 *total = s390_cost->msg; /* msgr, msg */
2488 }
2489 else /* TARGET_31BIT */
2490 {
2491 if (GET_CODE (left) == SIGN_EXTEND
2492 && GET_CODE (right) == SIGN_EXTEND)
2493 /* mulsidi case: mr, m */
2494 *total = s390_cost->m;
2742a1ed
MD		 2495 else if (GET_CODE (left) == ZERO_EXTEND
2496 && GET_CODE (right) == ZERO_EXTEND
2497 && TARGET_CPU_ZARCH)
2498 /* umulsidi case: ml, mlr */
2499 *total = s390_cost->ml;
017e0eb9
MD		 2500 else
2501 /* Complex calculation is required. */
2502 *total = COSTS_N_INSNS (40);
2503 }
2504 break;
2505 }
2506 case SFmode:
2507 case DFmode:
2508 *total = s390_cost->mult_df;
2509 break;
f61a2c7d
AK		 2510 case TFmode:
2511 *total = s390_cost->mxbr;
2512 break;
017e0eb9
MD		 2513 default:
2514 return false;
2515 }
2516 return false;
3c50106f 2517
d7ecb504
RH		 2518 case FMA:
2519 switch (GET_MODE (x))
2520 {
2521 case DFmode:
2522 *total = s390_cost->madbr;
2523 break;
2524 case SFmode:
2525 *total = s390_cost->maebr;
2526 break;
2527 default:
2528 return false;
2529 }
2530 /* Negate in the third argument is free: FMSUB. */
2531 if (GET_CODE (XEXP (x, 2)) == NEG)
2532 {
68f932c4
RS		 2533 *total += (rtx_cost (XEXP (x, 0), FMA, 0, speed)
2534 + rtx_cost (XEXP (x, 1), FMA, 1, speed)
2535 + rtx_cost (XEXP (XEXP (x, 2), 0), FMA, 2, speed));
d7ecb504
RH		 2536 return true;
2537 }
2538 return false;
2539
6fa5b390
MD		 2540 case UDIV:
2541 case UMOD:
2542 if (GET_MODE (x) == TImode) /* 128 bit division */
2543 *total = s390_cost->dlgr;
2544 else if (GET_MODE (x) == DImode)
2545 {
2546 rtx right = XEXP (x, 1);
2547 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2548 *total = s390_cost->dlr;
2549 else /* 64 by 64 bit division */
2550 *total = s390_cost->dlgr;
2551 }
2552 else if (GET_MODE (x) == SImode) /* 32 bit division */
2553 *total = s390_cost->dlr;
2554 return false;
2555
3c50106f 2556 case DIV:
6fa5b390
MD		 2557 case MOD:
2558 if (GET_MODE (x) == DImode)
2559 {
2560 rtx right = XEXP (x, 1);
2561 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
9602b6a1 2562 if (TARGET_ZARCH)
6fa5b390
MD		 2563 *total = s390_cost->dsgfr;
2564 else
2565 *total = s390_cost->dr;
2566 else /* 64 by 64 bit division */
2567 *total = s390_cost->dsgr;
2568 }
2569 else if (GET_MODE (x) == SImode) /* 32 bit division */
2570 *total = s390_cost->dlr;
2571 else if (GET_MODE (x) == SFmode)
98fd0d70 2572 {
142cd70f 2573 *total = s390_cost->debr;
98fd0d70
MD		 2574 }
2575 else if (GET_MODE (x) == DFmode)
2576 {
142cd70f 2577 *total = s390_cost->ddbr;
98fd0d70 2578 }
f61a2c7d
AK		 2579 else if (GET_MODE (x) == TFmode)
2580 {
142cd70f 2581 *total = s390_cost->dxbr;
f61a2c7d 2582 }
017e0eb9
MD		 2583 return false;
2584
2742a1ed
MD		 2585 case SQRT:
2586 if (GET_MODE (x) == SFmode)
2587 *total = s390_cost->sqebr;
f61a2c7d 2588 else if (GET_MODE (x) == DFmode)
2742a1ed 2589 *total = s390_cost->sqdbr;
f61a2c7d
AK		 2590 else /* TFmode */
2591 *total = s390_cost->sqxbr;
2742a1ed
MD		 2592 return false;
2593
017e0eb9 2594 case SIGN_EXTEND:
2742a1ed 2595 case ZERO_EXTEND:
6fa5b390
MD		 2596 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2597 || outer_code == PLUS || outer_code == MINUS
2598 || outer_code == COMPARE)
017e0eb9
MD		 2599 *total = 0;
2600 return false;
3c50106f 2601
6fa5b390
MD		 2602 case COMPARE:
2603 *total = COSTS_N_INSNS (1);
2604 if (GET_CODE (XEXP (x, 0)) == AND
2605 && GET_CODE (XEXP (x, 1)) == CONST_INT
2606 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2607 {
2608 rtx op0 = XEXP (XEXP (x, 0), 0);
2609 rtx op1 = XEXP (XEXP (x, 0), 1);
2610 rtx op2 = XEXP (x, 1);
2611
2612 if (memory_operand (op0, GET_MODE (op0))
2613 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2614 return true;
2615 if (register_operand (op0, GET_MODE (op0))
2616 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2617 return true;
2618 }
2619 return false;
2620
3c50106f
RH		 2621 default:
2622 return false;
2623 }
2624}
2625
dea09b1b
UW		 2626/* Return the cost of an address rtx ADDR. */
2627
dcefdf67 2628static int
ef4bddc2 2629s390_address_cost (rtx addr, machine_mode mode ATTRIBUTE_UNUSED,
b413068c
OE		 2630 addr_space_t as ATTRIBUTE_UNUSED,
2631 bool speed ATTRIBUTE_UNUSED)
dea09b1b
UW		 2632{
2633 struct s390_address ad;
2634 if (!s390_decompose_address (addr, &ad))
2635 return 1000;
2636
2637 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2638}
2639
fd3cd001
UW		 2640/* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2641 otherwise return 0. */
2642
2643int
5d81b82b 2644tls_symbolic_operand (rtx op)
fd3cd001 2645{
fd3cd001
UW		 2646 if (GET_CODE (op) != SYMBOL_REF)
2647 return 0;
114278e7 2648 return SYMBOL_REF_TLS_MODEL (op);
fd3cd001 2649}
9db1d521 2650\f
c5aa1d12
UW		 2651/* Split DImode access register reference REG (on 64-bit) into its constituent
2652 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2653 gen_highpart cannot be used as they assume all registers are word-sized,
2654 while our access registers have only half that size. */
2655
2656void
2657s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2658{
2659 gcc_assert (TARGET_64BIT);
2660 gcc_assert (ACCESS_REG_P (reg));
2661 gcc_assert (GET_MODE (reg) == DImode);
2662 gcc_assert (!(REGNO (reg) & 1));
2663
2664 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2665 *hi = gen_rtx_REG (SImode, REGNO (reg));
2666}
9db1d521 2667
994fe660 2668/* Return true if OP contains a symbol reference */
9db1d521 2669
3ed99cc9 2670bool
9c808aad 2671symbolic_reference_mentioned_p (rtx op)
9db1d521 2672{
5d81b82b
AS		 2673 const char *fmt;
2674 int i;
9db1d521
HP		 2675
2676 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2677 return 1;
2678
2679 fmt = GET_RTX_FORMAT (GET_CODE (op));
2680 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2681 {
2682 if (fmt[i] == 'E')
2683 {
5d81b82b 2684 int j;
9db1d521
HP		 2685
2686 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2687 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2688 return 1;
2689 }
2690
2691 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2692 return 1;
2693 }
2694
2695 return 0;
2696}
2697
fd3cd001
UW		 2698/* Return true if OP contains a reference to a thread-local symbol. */
2699
3ed99cc9 2700bool
9c808aad 2701tls_symbolic_reference_mentioned_p (rtx op)
fd3cd001 2702{
5d81b82b
AS		 2703 const char *fmt;
2704 int i;
fd3cd001
UW		 2705
2706 if (GET_CODE (op) == SYMBOL_REF)
2707 return tls_symbolic_operand (op);
2708
2709 fmt = GET_RTX_FORMAT (GET_CODE (op));
2710 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2711 {
2712 if (fmt[i] == 'E')
2713 {
5d81b82b 2714 int j;
fd3cd001
UW		 2715
2716 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2717 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
3ed99cc9 2718 return true;
fd3cd001
UW		 2719 }
2720
2721 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
3ed99cc9 2722 return true;
fd3cd001
UW		 2723 }
2724
3ed99cc9 2725 return false;
fd3cd001
UW		 2726}
2727
9db1d521 2728
c7453384
EC		 2729/* Return true if OP is a legitimate general operand when
2730 generating PIC code. It is given that flag_pic is on
994fe660
UW		 2731 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2732
9db1d521 2733int
5d81b82b 2734legitimate_pic_operand_p (rtx op)
9db1d521 2735{
4023fb28 2736 /* Accept all non-symbolic constants. */
9db1d521
HP		 2737 if (!SYMBOLIC_CONST (op))
2738 return 1;
2739
c7453384 2740 /* Reject everything else; must be handled
fd3cd001 2741 via emit_symbolic_move. */
9db1d521
HP		 2742 return 0;
2743}
2744
994fe660
UW		 2745/* Returns true if the constant value OP is a legitimate general operand.
2746 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2747
1a627b35 2748static bool
ef4bddc2 2749s390_legitimate_constant_p (machine_mode mode, rtx op)
9db1d521 2750{
4023fb28 2751 /* Accept all non-symbolic constants. */
9db1d521
HP		 2752 if (!SYMBOLIC_CONST (op))
2753 return 1;
2754
fd3cd001 2755 /* Accept immediate LARL operands. */
1a627b35 2756 if (TARGET_CPU_ZARCH && larl_operand (op, mode))
fd3cd001
UW		 2757 return 1;
2758
2759 /* Thread-local symbols are never legal constants. This is
2760 so that emit_call knows that computing such addresses
2761 might require a function call. */
2762 if (TLS_SYMBOLIC_CONST (op))
2763 return 0;
2764
9db1d521
HP		 2765 /* In the PIC case, symbolic constants must *not* be
2766 forced into the literal pool. We accept them here,
fd3cd001 2767 so that they will be handled by emit_symbolic_move. */
9db1d521
HP		 2768 if (flag_pic)
2769 return 1;
2770
9db1d521
HP		 2771 /* All remaining non-PIC symbolic constants are
2772 forced into the literal pool. */
2773 return 0;
2774}
2775
fd3cd001
UW		 2776/* Determine if it's legal to put X into the constant pool. This
2777 is not possible if X contains the address of a symbol that is
2778 not constant (TLS) or not known at final link time (PIC). */
2779
2780static bool
ef4bddc2 2781s390_cannot_force_const_mem (machine_mode mode, rtx x)
fd3cd001
UW		 2782{
2783 switch (GET_CODE (x))
2784 {
2785 case CONST_INT:
2786 case CONST_DOUBLE:
2787 /* Accept all non-symbolic constants. */
2788 return false;
2789
2790 case LABEL_REF:
2791 /* Labels are OK iff we are non-PIC. */
2792 return flag_pic != 0;
2793
2794 case SYMBOL_REF:
2795 /* 'Naked' TLS symbol references are never OK,
2796 non-TLS symbols are OK iff we are non-PIC. */
2797 if (tls_symbolic_operand (x))
2798 return true;
2799 else
2800 return flag_pic != 0;
2801
2802 case CONST:
fbbf66e7 2803 return s390_cannot_force_const_mem (mode, XEXP (x, 0));
fd3cd001
UW		 2804 case PLUS:
2805 case MINUS:
fbbf66e7
RS		 2806 return s390_cannot_force_const_mem (mode, XEXP (x, 0))
2807 || s390_cannot_force_const_mem (mode, XEXP (x, 1));
fd3cd001
UW		 2808
2809 case UNSPEC:
2810 switch (XINT (x, 1))
2811 {
2812 /* Only lt-relative or GOT-relative UNSPECs are OK. */
fd7643fb
UW		 2813 case UNSPEC_LTREL_OFFSET:
2814 case UNSPEC_GOT:
2815 case UNSPEC_GOTOFF:
2816 case UNSPEC_PLTOFF:
fd3cd001
UW		 2817 case UNSPEC_TLSGD:
2818 case UNSPEC_TLSLDM:
2819 case UNSPEC_NTPOFF:
2820 case UNSPEC_DTPOFF:
2821 case UNSPEC_GOTNTPOFF:
2822 case UNSPEC_INDNTPOFF:
2823 return false;
2824
9bb86f41
UW		 2825 /* If the literal pool shares the code section, be put
2826 execute template placeholders into the pool as well. */
2827 case UNSPEC_INSN:
2828 return TARGET_CPU_ZARCH;
2829
fd3cd001
UW		 2830 default:
2831 return true;
2832 }
2833 break;
2834
2835 default:
8d933e31 2836 gcc_unreachable ();
fd3cd001
UW		 2837 }
2838}
2839
4023fb28 2840/* Returns true if the constant value OP is a legitimate general
c7453384 2841 operand during and after reload. The difference to
4023fb28
UW		 2842 legitimate_constant_p is that this function will not accept
2843 a constant that would need to be forced to the literal pool
65b1d8ea
AK		 2844 before it can be used as operand.
2845 This function accepts all constants which can be loaded directly
2846 into a GPR. */
4023fb28 2847
3ed99cc9 2848bool
5d81b82b 2849legitimate_reload_constant_p (rtx op)
4023fb28 2850{
d3632d41 2851 /* Accept la(y) operands. */
c7453384 2852 if (GET_CODE (op) == CONST_INT
d3632d41 2853 && DISP_IN_RANGE (INTVAL (op)))
3ed99cc9 2854 return true;
d3632d41 2855
ec24698e 2856 /* Accept l(g)hi/l(g)fi operands. */
4023fb28 2857 if (GET_CODE (op) == CONST_INT
ec24698e 2858 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
3ed99cc9 2859 return true;
4023fb28
UW		 2860
2861 /* Accept lliXX operands. */
9e8327e3 2862 if (TARGET_ZARCH
11598938
UW		 2863 && GET_CODE (op) == CONST_INT
2864 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2865 && s390_single_part (op, word_mode, HImode, 0) >= 0)
3ed99cc9 2866 return true;
4023fb28 2867
ec24698e
UW		 2868 if (TARGET_EXTIMM
2869 && GET_CODE (op) == CONST_INT
2870 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2871 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2872 return true;
2873
4023fb28 2874 /* Accept larl operands. */
9e8327e3 2875 if (TARGET_CPU_ZARCH
4023fb28 2876 && larl_operand (op, VOIDmode))
3ed99cc9 2877 return true;
4023fb28 2878
45e5214c
UW		 2879 /* Accept floating-point zero operands that fit into a single GPR. */
2880 if (GET_CODE (op) == CONST_DOUBLE
2881 && s390_float_const_zero_p (op)
2882 && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
2883 return true;
2884
11598938
UW		 2885 /* Accept double-word operands that can be split. */
2886 if (GET_CODE (op) == CONST_INT
2887 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2888 {
ef4bddc2 2889 machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
11598938
UW		 2890 rtx hi = operand_subword (op, 0, 0, dword_mode);
2891 rtx lo = operand_subword (op, 1, 0, dword_mode);
2892 return legitimate_reload_constant_p (hi)
2893 && legitimate_reload_constant_p (lo);
2894 }
2895
4023fb28 2896 /* Everything else cannot be handled without reload. */
3ed99cc9 2897 return false;
4023fb28
UW		 2898}
2899
65b1d8ea
AK		 2900/* Returns true if the constant value OP is a legitimate fp operand
2901 during and after reload.
2902 This function accepts all constants which can be loaded directly
2903 into an FPR. */
2904
2905static bool
2906legitimate_reload_fp_constant_p (rtx op)
2907{
2908 /* Accept floating-point zero operands if the load zero instruction
22ac2c2f
AK		 2909 can be used. Prior to z196 the load fp zero instruction caused a
2910 performance penalty if the result is used as BFP number. */
65b1d8ea
AK		 2911 if (TARGET_Z196
2912 && GET_CODE (op) == CONST_DOUBLE
2913 && s390_float_const_zero_p (op))
2914 return true;
2915
2916 return false;
2917}
2918
0a2aaacc 2919/* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
4023fb28
UW		 2920 return the class of reg to actually use. */
2921
5df97412
AS		 2922static reg_class_t
2923s390_preferred_reload_class (rtx op, reg_class_t rclass)
4023fb28 2924{
4023fb28
UW		 2925 switch (GET_CODE (op))
2926 {
45e5214c
UW		 2927 /* Constants we cannot reload into general registers
2928 must be forced into the literal pool. */
4023fb28
UW		 2929 case CONST_DOUBLE:
2930 case CONST_INT:
45e5214c
UW		 2931 if (reg_class_subset_p (GENERAL_REGS, rclass)
2932 && legitimate_reload_constant_p (op))
2933 return GENERAL_REGS;
2934 else if (reg_class_subset_p (ADDR_REGS, rclass)
2935 && legitimate_reload_constant_p (op))
2936 return ADDR_REGS;
65b1d8ea
AK		 2937 else if (reg_class_subset_p (FP_REGS, rclass)
2938 && legitimate_reload_fp_constant_p (op))
2939 return FP_REGS;
2940 return NO_REGS;
4023fb28
UW		 2941
2942 /* If a symbolic constant or a PLUS is reloaded,
14b3e8ef
UW		 2943 it is most likely being used as an address, so
2944 prefer ADDR_REGS. If 'class' is not a superset
2945 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
1abcd5eb 2946 case CONST:
cb4b6d17
AK		 2947 /* Symrefs cannot be pushed into the literal pool with -fPIC
2948 so we *MUST NOT* return NO_REGS for these cases
2949 (s390_cannot_force_const_mem will return true).
2950
2951 On the other hand we MUST return NO_REGS for symrefs with
2952 invalid addend which might have been pushed to the literal
2953 pool (no -fPIC). Usually we would expect them to be
2954 handled via secondary reload but this does not happen if
2955 they are used as literal pool slot replacement in reload
2956 inheritance (see emit_input_reload_insns). */
1abcd5eb
AK		 2957 if (TARGET_CPU_ZARCH
2958 && GET_CODE (XEXP (op, 0)) == PLUS
2959 && GET_CODE (XEXP (XEXP(op, 0), 0)) == SYMBOL_REF
2960 && GET_CODE (XEXP (XEXP(op, 0), 1)) == CONST_INT)
2961 {
cb4b6d17 2962 if (flag_pic && reg_class_subset_p (ADDR_REGS, rclass))
1abcd5eb
AK		 2963 return ADDR_REGS;
2964 else
2965 return NO_REGS;
2966 }
2967 /* fallthrough */
4023fb28
UW		 2968 case LABEL_REF:
2969 case SYMBOL_REF:
212aa74f
AK		 2970 if (!legitimate_reload_constant_p (op))
2971 return NO_REGS;
2972 /* fallthrough */
2973 case PLUS:
2974 /* load address will be used. */
0a2aaacc 2975 if (reg_class_subset_p (ADDR_REGS, rclass))
212aa74f 2976 return ADDR_REGS;
14b3e8ef
UW		 2977 else
2978 return NO_REGS;
4023fb28
UW		 2979
2980 default:
2981 break;
2982 }
2983
0a2aaacc 2984 return rclass;
4023fb28 2985}
9db1d521 2986
963fc8d0
AK		 2987/* Return true if ADDR is SYMBOL_REF + addend with addend being a
2988 multiple of ALIGNMENT and the SYMBOL_REF being naturally
2989 aligned. */
2990
2991bool
2992s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
2993{
2994 HOST_WIDE_INT addend;
2995 rtx symref;
2996
0ff4390d
AK		 2997 if (!s390_loadrelative_operand_p (addr, &symref, &addend))
2998 return false;
98412b77 2999
0ff4390d 3000 if (addend & (alignment - 1))
963fc8d0
AK		 3001 return false;
3002
0ff4390d
AK		 3003 if (GET_CODE (symref) == SYMBOL_REF
3004 && !SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref))
3005 return true;
3006
3007 if (GET_CODE (symref) == UNSPEC
3008 && alignment <= UNITS_PER_LONG)
3009 return true;
3010
3011 return false;
963fc8d0
AK		 3012}
3013
3014/* ADDR is moved into REG using larl. If ADDR isn't a valid larl
3015 operand SCRATCH is used to reload the even part of the address and
3016 adding one. */
3017
3018void
3019s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
3020{
3021 HOST_WIDE_INT addend;
3022 rtx symref;
3023
0ff4390d 3024 if (!s390_loadrelative_operand_p (addr, &symref, &addend))
963fc8d0
AK		 3025 gcc_unreachable ();
3026
3027 if (!(addend & 1))
3028 /* Easy case. The addend is even so larl will do fine. */
3029 emit_move_insn (reg, addr);
3030 else
3031 {
3032 /* We can leave the scratch register untouched if the target
3033 register is a valid base register. */
3034 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
3035 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
3036 scratch = reg;
3037
3038 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
3039 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
3040
3041 if (addend != 1)
3042 emit_move_insn (scratch,
3043 gen_rtx_CONST (Pmode,
3044 gen_rtx_PLUS (Pmode, symref,
3045 GEN_INT (addend - 1))));
3046 else
3047 emit_move_insn (scratch, symref);
3048
3049 /* Increment the address using la in order to avoid clobbering cc. */
1abcd5eb 3050 s390_load_address (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
963fc8d0
AK		 3051 }
3052}
3053
3054/* Generate what is necessary to move between REG and MEM using
3055 SCRATCH. The direction is given by TOMEM. */
3056
3057void
3058s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
3059{
3060 /* Reload might have pulled a constant out of the literal pool.
3061 Force it back in. */
3062 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
3063 || GET_CODE (mem) == CONST)
3064 mem = force_const_mem (GET_MODE (reg), mem);
3065
3066 gcc_assert (MEM_P (mem));
3067
3068 /* For a load from memory we can leave the scratch register
3069 untouched if the target register is a valid base register. */
3070 if (!tomem
3071 && REGNO (reg) < FIRST_PSEUDO_REGISTER
3072 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
3073 && GET_MODE (reg) == GET_MODE (scratch))
3074 scratch = reg;
3075
3076 /* Load address into scratch register. Since we can't have a
3077 secondary reload for a secondary reload we have to cover the case
3078 where larl would need a secondary reload here as well. */
3079 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
3080
3081 /* Now we can use a standard load/store to do the move. */
3082 if (tomem)
3083 emit_move_insn (replace_equiv_address (mem, scratch), reg);
3084 else
3085 emit_move_insn (reg, replace_equiv_address (mem, scratch));
3086}
3087
833cd70a 3088/* Inform reload about cases where moving X with a mode MODE to a register in
0a2aaacc 3089 RCLASS requires an extra scratch or immediate register. Return the class
833cd70a 3090 needed for the immediate register. */
f61a2c7d 3091
a87cf97e
JR		 3092static reg_class_t
3093s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
ef4bddc2 3094 machine_mode mode, secondary_reload_info *sri)
833cd70a 3095{
a87cf97e
JR		 3096 enum reg_class rclass = (enum reg_class) rclass_i;
3097
833cd70a 3098 /* Intermediate register needed. */
0a2aaacc 3099 if (reg_classes_intersect_p (CC_REGS, rclass))
9dc62c00
AK		 3100 return GENERAL_REGS;
3101
963fc8d0
AK		 3102 if (TARGET_Z10)
3103 {
212aa74f
AK		 3104 HOST_WIDE_INT offset;
3105 rtx symref;
3106
963fc8d0
AK		 3107 /* On z10 several optimizer steps may generate larl operands with
3108 an odd addend. */
3109 if (in_p
0ff4390d 3110 && s390_loadrelative_operand_p (x, &symref, &offset)
963fc8d0 3111 && mode == Pmode
212aa74f
AK		 3112 && !SYMBOL_REF_ALIGN1_P (symref)
3113 && (offset & 1) == 1)
963fc8d0
AK		 3114 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3115 : CODE_FOR_reloadsi_larl_odd_addend_z10);
3116
3117 /* On z10 we need a scratch register when moving QI, TI or floating
3118 point mode values from or to a memory location with a SYMBOL_REF
3119 or if the symref addend of a SI or DI move is not aligned to the
3120 width of the access. */
3121 if (MEM_P (x)
0ff4390d 3122 && s390_loadrelative_operand_p (XEXP (x, 0), NULL, NULL)
963fc8d0 3123 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
9602b6a1 3124 || (!TARGET_ZARCH && mode == DImode)
963fc8d0
AK		 3125 || ((mode == HImode || mode == SImode || mode == DImode)
3126 && (!s390_check_symref_alignment (XEXP (x, 0),
3127 GET_MODE_SIZE (mode))))))
3128 {
3129#define __SECONDARY_RELOAD_CASE(M,m) \
3130 case M##mode: \
3131 if (TARGET_64BIT) \
3132 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3133 CODE_FOR_reload##m##di_tomem_z10; \
3134 else \
3135 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3136 CODE_FOR_reload##m##si_tomem_z10; \
3137 break;
3138
3139 switch (GET_MODE (x))
3140 {
3141 __SECONDARY_RELOAD_CASE (QI, qi);
3142 __SECONDARY_RELOAD_CASE (HI, hi);
3143 __SECONDARY_RELOAD_CASE (SI, si);
3144 __SECONDARY_RELOAD_CASE (DI, di);
3145 __SECONDARY_RELOAD_CASE (TI, ti);
3146 __SECONDARY_RELOAD_CASE (SF, sf);
3147 __SECONDARY_RELOAD_CASE (DF, df);
3148 __SECONDARY_RELOAD_CASE (TF, tf);
3149 __SECONDARY_RELOAD_CASE (SD, sd);
3150 __SECONDARY_RELOAD_CASE (DD, dd);
3151 __SECONDARY_RELOAD_CASE (TD, td);
3152
3153 default:
3154 gcc_unreachable ();
3155 }
3156#undef __SECONDARY_RELOAD_CASE
3157 }
3158 }
3159
833cd70a
AK		 3160 /* We need a scratch register when loading a PLUS expression which
3161 is not a legitimate operand of the LOAD ADDRESS instruction. */
3597e113
VM		 3162 /* LRA can deal with transformation of plus op very well -- so we
3163 don't need to prompt LRA in this case. */
3164 if (! lra_in_progress && in_p && s390_plus_operand (x, mode))
833cd70a
AK		 3165 sri->icode = (TARGET_64BIT ?
3166 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3167
7fa7289d 3168 /* Performing a multiword move from or to memory we have to make sure the
833cd70a
AK		 3169 second chunk in memory is addressable without causing a displacement
3170 overflow. If that would be the case we calculate the address in
3171 a scratch register. */
3172 if (MEM_P (x)
3173 && GET_CODE (XEXP (x, 0)) == PLUS
3174 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3175 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
0ca89db7 3176 + GET_MODE_SIZE (mode) - 1))
833cd70a 3177 {
7fa7289d 3178 /* For GENERAL_REGS a displacement overflow is no problem if occurring
833cd70a
AK		 3179 in a s_operand address since we may fallback to lm/stm. So we only
3180 have to care about overflows in the b+i+d case. */
0a2aaacc 3181 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
833cd70a
AK		 3182 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3183 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3184 /* For FP_REGS no lm/stm is available so this check is triggered
3185 for displacement overflows in b+i+d and b+d like addresses. */
0a2aaacc 3186 || (reg_classes_intersect_p (FP_REGS, rclass)
833cd70a
AK		 3187 && s390_class_max_nregs (FP_REGS, mode) > 1))
3188 {
3189 if (in_p)
3190 sri->icode = (TARGET_64BIT ?
3191 CODE_FOR_reloaddi_nonoffmem_in :
3192 CODE_FOR_reloadsi_nonoffmem_in);
3193 else
3194 sri->icode = (TARGET_64BIT ?
3195 CODE_FOR_reloaddi_nonoffmem_out :
3196 CODE_FOR_reloadsi_nonoffmem_out);
3197 }
3198 }
9dc62c00 3199
1f9e1fc6
AK		 3200 /* A scratch address register is needed when a symbolic constant is
3201 copied to r0 compiling with -fPIC. In other cases the target
3202 register might be used as temporary (see legitimize_pic_address). */
0a2aaacc 3203 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
1f9e1fc6
AK		 3204 sri->icode = (TARGET_64BIT ?
3205 CODE_FOR_reloaddi_PIC_addr :
3206 CODE_FOR_reloadsi_PIC_addr);
3207
833cd70a 3208 /* Either scratch or no register needed. */
dc65c307
UW		 3209 return NO_REGS;
3210}
3211
f3e9edff
UW		 3212/* Generate code to load SRC, which is PLUS that is not a
3213 legitimate operand for the LA instruction, into TARGET.
3214 SCRATCH may be used as scratch register. */
3215
3216void
5d81b82b
AS		 3217s390_expand_plus_operand (rtx target, rtx src,
3218 rtx scratch)
f3e9edff 3219{
7974fe63 3220 rtx sum1, sum2;
b808c04c 3221 struct s390_address ad;
6a4e49c1 3222
6a4e49c1 3223 /* src must be a PLUS; get its two operands. */
8d933e31
AS		 3224 gcc_assert (GET_CODE (src) == PLUS);
3225 gcc_assert (GET_MODE (src) == Pmode);
f3e9edff 3226
7c82a1ed
UW		 3227 /* Check if any of the two operands is already scheduled
3228 for replacement by reload. This can happen e.g. when
3229 float registers occur in an address. */
3230 sum1 = find_replacement (&XEXP (src, 0));
3231 sum2 = find_replacement (&XEXP (src, 1));
ccfc6cc8 3232 src = gen_rtx_PLUS (Pmode, sum1, sum2);
ccfc6cc8 3233
7974fe63
UW		 3234 /* If the address is already strictly valid, there's nothing to do. */
3235 if (!s390_decompose_address (src, &ad)
93fa8428
AK		 3236 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3237 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
f3e9edff 3238 {
7974fe63
UW		 3239 /* Otherwise, one of the operands cannot be an address register;
3240 we reload its value into the scratch register. */
3241 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3242 {
3243 emit_move_insn (scratch, sum1);
3244 sum1 = scratch;
3245 }
3246 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3247 {
3248 emit_move_insn (scratch, sum2);
3249 sum2 = scratch;
3250 }
f3e9edff 3251
7974fe63
UW		 3252 /* According to the way these invalid addresses are generated
3253 in reload.c, it should never happen (at least on s390) that
3254 *neither* of the PLUS components, after find_replacements
3255 was applied, is an address register. */
3256 if (sum1 == scratch && sum2 == scratch)
3257 {
3258 debug_rtx (src);
8d933e31 3259 gcc_unreachable ();
7974fe63 3260 }
f3e9edff 3261
7974fe63 3262 src = gen_rtx_PLUS (Pmode, sum1, sum2);
f3e9edff
UW		 3263 }
3264
3265 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3266 is only ever performed on addresses, so we can mark the
3267 sum as legitimate for LA in any case. */
a41c6c53 3268 s390_load_address (target, src);
f3e9edff
UW		 3269}
3270
3271
3ed99cc9 3272/* Return true if ADDR is a valid memory address.
ab96de7e 3273 STRICT specifies whether strict register checking applies. */
9db1d521 3274
c6c3dba9 3275static bool
ef4bddc2 3276s390_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
9db1d521 3277{
ab96de7e 3278 struct s390_address ad;
963fc8d0
AK		 3279
3280 if (TARGET_Z10
3281 && larl_operand (addr, VOIDmode)
3282 && (mode == VOIDmode
3283 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3284 return true;
3285
ab96de7e 3286 if (!s390_decompose_address (addr, &ad))
3ed99cc9 3287 return false;
b808c04c
UW		 3288
3289 if (strict)
3290 {
93fa8428 3291 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3ed99cc9 3292 return false;
93fa8428
AK		 3293
3294 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
3ed99cc9 3295 return false;
b808c04c
UW		 3296 }
3297 else
3298 {
f4aa3848 3299 if (ad.base
93fa8428
AK		 3300 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3301 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
3ed99cc9 3302 return false;
f4aa3848 3303
93fa8428
AK		 3304 if (ad.indx
3305 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3306 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3307 return false;
b808c04c 3308 }
3ed99cc9 3309 return true;
9db1d521
HP		 3310}
3311
3ed99cc9 3312/* Return true if OP is a valid operand for the LA instruction.
ba956982
UW		 3313 In 31-bit, we need to prove that the result is used as an
3314 address, as LA performs only a 31-bit addition. */
3315
3ed99cc9 3316bool
5d81b82b 3317legitimate_la_operand_p (rtx op)
ba956982
UW		 3318{
3319 struct s390_address addr;
b808c04c 3320 if (!s390_decompose_address (op, &addr))
3ed99cc9 3321 return false;
ba956982 3322
3ed99cc9 3323 return (TARGET_64BIT || addr.pointer);
f3e9edff 3324}
ba956982 3325
3ed99cc9 3326/* Return true if it is valid *and* preferable to use LA to
e1d5ee28 3327 compute the sum of OP1 and OP2. */
c7453384 3328
3ed99cc9 3329bool
e1d5ee28 3330preferred_la_operand_p (rtx op1, rtx op2)
100c7420
UW		 3331{
3332 struct s390_address addr;
e1d5ee28
UW		 3333
3334 if (op2 != const0_rtx)
3335 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3336
3337 if (!s390_decompose_address (op1, &addr))
3ed99cc9 3338 return false;
93fa8428 3339 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
3ed99cc9 3340 return false;
93fa8428 3341 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
3ed99cc9 3342 return false;
100c7420 3343
65b1d8ea 3344 /* Avoid LA instructions with index register on z196; it is
22ac2c2f
AK		 3345 preferable to use regular add instructions when possible.
3346 Starting with zEC12 the la with index register is "uncracked"
3347 again. */
65b1d8ea
AK		 3348 if (addr.indx && s390_tune == PROCESSOR_2817_Z196)
3349 return false;
3350
100c7420 3351 if (!TARGET_64BIT && !addr.pointer)
3ed99cc9 3352 return false;
100c7420
UW		 3353
3354 if (addr.pointer)
3ed99cc9 3355 return true;
100c7420 3356
4888ec5d
UW		 3357 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3358 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
3ed99cc9 3359 return true;
100c7420 3360
3ed99cc9 3361 return false;
100c7420
UW		 3362}
3363
a41c6c53
UW		 3364/* Emit a forced load-address operation to load SRC into DST.
3365 This will use the LOAD ADDRESS instruction even in situations
3366 where legitimate_la_operand_p (SRC) returns false. */
ba956982 3367
a41c6c53 3368void
9c808aad 3369s390_load_address (rtx dst, rtx src)
f3e9edff 3370{
a41c6c53
UW		 3371 if (TARGET_64BIT)
3372 emit_move_insn (dst, src);
3373 else
3374 emit_insn (gen_force_la_31 (dst, src));
ba956982
UW		 3375}
3376
9db1d521
HP		 3377/* Return a legitimate reference for ORIG (an address) using the
3378 register REG. If REG is 0, a new pseudo is generated.
3379
3380 There are two types of references that must be handled:
3381
3382 1. Global data references must load the address from the GOT, via
3383 the PIC reg. An insn is emitted to do this load, and the reg is
3384 returned.
3385
3386 2. Static data references, constant pool addresses, and code labels
3387 compute the address as an offset from the GOT, whose base is in
114278e7 3388 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
9db1d521
HP		 3389 differentiate them from global data objects. The returned
3390 address is the PIC reg + an unspec constant.
3391
331d9186 3392 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
9db1d521
HP		 3393 reg also appears in the address. */
3394
3395rtx
9c808aad 3396legitimize_pic_address (rtx orig, rtx reg)
9db1d521
HP		 3397{
3398 rtx addr = orig;
0ff4390d 3399 rtx addend = const0_rtx;
0a2aaacc 3400 rtx new_rtx = orig;
9db1d521 3401
cf9d7618
ANM		 3402 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3403
0ff4390d
AK		 3404 if (GET_CODE (addr) == CONST)
3405 addr = XEXP (addr, 0);
3406
3407 if (GET_CODE (addr) == PLUS)
9db1d521 3408 {
0ff4390d
AK		 3409 addend = XEXP (addr, 1);
3410 addr = XEXP (addr, 0);
3411 }
3412
3413 if ((GET_CODE (addr) == LABEL_REF
3414 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr))
3415 || (GET_CODE (addr) == UNSPEC &&
3416 (XINT (addr, 1) == UNSPEC_GOTENT
3417 || (TARGET_CPU_ZARCH && XINT (addr, 1) == UNSPEC_PLT))))
3418 && GET_CODE (addend) == CONST_INT)
3419 {
3420 /* This can be locally addressed. */
3421
3422 /* larl_operand requires UNSPECs to be wrapped in a const rtx. */
3423 rtx const_addr = (GET_CODE (addr) == UNSPEC ?
3424 gen_rtx_CONST (Pmode, addr) : addr);
3425
3426 if (TARGET_CPU_ZARCH
3427 && larl_operand (const_addr, VOIDmode)
3428 && INTVAL (addend) < (HOST_WIDE_INT)1 << 31
3429 && INTVAL (addend) >= -((HOST_WIDE_INT)1 << 31))
3430 {
3431 if (INTVAL (addend) & 1)
3432 {
3433 /* LARL can't handle odd offsets, so emit a pair of LARL
3434 and LA. */
3435 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3436
3437 if (!DISP_IN_RANGE (INTVAL (addend)))
3438 {
3439 HOST_WIDE_INT even = INTVAL (addend) - 1;
3440 addr = gen_rtx_PLUS (Pmode, addr, GEN_INT (even));
3441 addr = gen_rtx_CONST (Pmode, addr);
3442 addend = const1_rtx;
3443 }
3444
3445 emit_move_insn (temp, addr);
3446 new_rtx = gen_rtx_PLUS (Pmode, temp, addend);
3447
3448 if (reg != 0)
3449 {
3450 s390_load_address (reg, new_rtx);
3451 new_rtx = reg;
3452 }
3453 }
3454 else
3455 {
3456 /* If the offset is even, we can just use LARL. This
3457 will happen automatically. */
3458 }
3459 }
9db1d521 3460 else
0ff4390d
AK		 3461 {
3462 /* No larl - Access local symbols relative to the GOT. */
9db1d521 3463
0ff4390d 3464 rtx temp = reg? reg : gen_reg_rtx (Pmode);
9db1d521 3465
fd7643fb 3466 if (reload_in_progress || reload_completed)
6fb5fa3c 3467 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
fd7643fb 3468
0ff4390d
AK		 3469 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3470 if (addend != const0_rtx)
3471 addr = gen_rtx_PLUS (Pmode, addr, addend);
3472 addr = gen_rtx_CONST (Pmode, addr);
3473 addr = force_const_mem (Pmode, addr);
9db1d521
HP		 3474 emit_move_insn (temp, addr);
3475
0ff4390d
AK		 3476 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3477 if (reg != 0)
3478 {
3479 s390_load_address (reg, new_rtx);
3480 new_rtx = reg;
3481 }
3482 }
9db1d521 3483 }
0ff4390d 3484 else if (GET_CODE (addr) == SYMBOL_REF && addend == const0_rtx)
9db1d521 3485 {
0ff4390d
AK		 3486 /* A non-local symbol reference without addend.
3487
3488 The symbol ref is wrapped into an UNSPEC to make sure the
3489 proper operand modifier (@GOT or @GOTENT) will be emitted.
3490 This will tell the linker to put the symbol into the GOT.
3491
3492 Additionally the code dereferencing the GOT slot is emitted here.
3493
3494 An addend to the symref needs to be added afterwards.
3495 legitimize_pic_address calls itself recursively to handle
3496 that case. So no need to do it here. */
3497
9db1d521
HP		 3498 if (reg == 0)
3499 reg = gen_reg_rtx (Pmode);
3500
0ff4390d
AK		 3501 if (TARGET_Z10)
3502 {
3503 /* Use load relative if possible.
3504 lgrl <target>, sym@GOTENT */
3505 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3506 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3507 new_rtx = gen_const_mem (GET_MODE (reg), new_rtx);
3508
3509 emit_move_insn (reg, new_rtx);
3510 new_rtx = reg;
3511 }
3512 else if (flag_pic == 1)
9db1d521 3513 {
0ff4390d
AK		 3514 /* Assume GOT offset is a valid displacement operand (< 4k
3515 or < 512k with z990). This is handled the same way in
3516 both 31- and 64-bit code (@GOT).
3517 lg <target>, sym@GOT(r12) */
9db1d521 3518
c3cc6b78 3519 if (reload_in_progress || reload_completed)
6fb5fa3c 3520 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9db1d521 3521
0a2aaacc
KG		 3522 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3523 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3524 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3525 new_rtx = gen_const_mem (Pmode, new_rtx);
3526 emit_move_insn (reg, new_rtx);
3527 new_rtx = reg;
9db1d521 3528 }
9e8327e3 3529 else if (TARGET_CPU_ZARCH)
9db1d521
HP		 3530 {
3531 /* If the GOT offset might be >= 4k, we determine the position
0ff4390d
AK		 3532 of the GOT entry via a PC-relative LARL (@GOTENT).
3533 larl temp, sym@GOTENT
3534 lg <target>, 0(temp) */
9db1d521 3535
1f9e1fc6
AK		 3536 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3537
3538 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3539 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
9db1d521 3540
0a2aaacc
KG		 3541 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3542 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
0ff4390d 3543 emit_move_insn (temp, new_rtx);
9db1d521 3544
0ff4390d 3545 new_rtx = gen_const_mem (Pmode, temp);
0a2aaacc 3546 emit_move_insn (reg, new_rtx);
0ff4390d 3547
0a2aaacc 3548 new_rtx = reg;
9db1d521
HP		 3549 }
3550 else
3551 {
c7453384 3552 /* If the GOT offset might be >= 4k, we have to load it
0ff4390d
AK		 3553 from the literal pool (@GOT).
3554
3555 lg temp, lit-litbase(r13)
3556 lg <target>, 0(temp)
3557 lit: .long sym@GOT */
9db1d521 3558
1f9e1fc6
AK		 3559 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3560
3561 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3562 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
9db1d521 3563
c3cc6b78 3564 if (reload_in_progress || reload_completed)
6fb5fa3c 3565 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
9db1d521 3566
fd7643fb 3567 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
e23795ea
UW		 3568 addr = gen_rtx_CONST (Pmode, addr);
3569 addr = force_const_mem (Pmode, addr);
9db1d521
HP		 3570 emit_move_insn (temp, addr);
3571
0a2aaacc
KG		 3572 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3573 new_rtx = gen_const_mem (Pmode, new_rtx);
3574 emit_move_insn (reg, new_rtx);
3575 new_rtx = reg;
9db1d521 3576 }
c7453384 3577 }
0ff4390d 3578 else if (GET_CODE (addr) == UNSPEC && GET_CODE (addend) == CONST_INT)
9db1d521 3579 {
0ff4390d
AK		 3580 gcc_assert (XVECLEN (addr, 0) == 1);
3581 switch (XINT (addr, 1))
9db1d521 3582 {
0ff4390d
AK		 3583 /* These address symbols (or PLT slots) relative to the GOT
3584 (not GOT slots!). In general this will exceed the
3585 displacement range so these value belong into the literal
3586 pool. */
3587 case UNSPEC_GOTOFF:
3588 case UNSPEC_PLTOFF:
3589 new_rtx = force_const_mem (Pmode, orig);
3590 break;
9db1d521 3591
0ff4390d
AK		 3592 /* For -fPIC the GOT size might exceed the displacement
3593 range so make sure the value is in the literal pool. */
3594 case UNSPEC_GOT:
3595 if (flag_pic == 2)
3596 new_rtx = force_const_mem (Pmode, orig);
3597 break;
9db1d521 3598
0ff4390d
AK		 3599 /* For @GOTENT larl is used. This is handled like local
3600 symbol refs. */
3601 case UNSPEC_GOTENT:
3602 gcc_unreachable ();
3603 break;
9db1d521 3604
0ff4390d
AK		 3605 /* @PLT is OK as is on 64-bit, must be converted to
3606 GOT-relative @PLTOFF on 31-bit. */
3607 case UNSPEC_PLT:
3608 if (!TARGET_CPU_ZARCH)
9db1d521 3609 {
0ff4390d
AK		 3610 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3611
3612 if (reload_in_progress || reload_completed)
3613 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3614
3615 addr = XVECEXP (addr, 0, 0);
3616 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3617 UNSPEC_PLTOFF);
3618 if (addend != const0_rtx)
3619 addr = gen_rtx_PLUS (Pmode, addr, addend);
3620 addr = gen_rtx_CONST (Pmode, addr);
3621 addr = force_const_mem (Pmode, addr);
3622 emit_move_insn (temp, addr);
3623
3624 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3625 if (reg != 0)
9db1d521 3626 {
0ff4390d
AK		 3627 s390_load_address (reg, new_rtx);
3628 new_rtx = reg;
9db1d521 3629 }
0ff4390d
AK		 3630 }
3631 else
3632 /* On 64 bit larl can be used. This case is handled like
3633 local symbol refs. */
3634 gcc_unreachable ();
3635 break;
3636
3637 /* Everything else cannot happen. */
3638 default:
3639 gcc_unreachable ();
3640 }
3641 }
3642 else if (addend != const0_rtx)
3643 {
3644 /* Otherwise, compute the sum. */
9db1d521 3645
0ff4390d
AK		 3646 rtx base = legitimize_pic_address (addr, reg);
3647 new_rtx = legitimize_pic_address (addend,
3648 base == reg ? NULL_RTX : reg);
3649 if (GET_CODE (new_rtx) == CONST_INT)
3650 new_rtx = plus_constant (Pmode, base, INTVAL (new_rtx));
3651 else
3652 {
3653 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3654 {
3655 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3656 new_rtx = XEXP (new_rtx, 1);
9db1d521 3657 }
0ff4390d 3658 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
9db1d521 3659 }
0ff4390d
AK		 3660
3661 if (GET_CODE (new_rtx) == CONST)
3662 new_rtx = XEXP (new_rtx, 0);
3663 new_rtx = force_operand (new_rtx, 0);
9db1d521 3664 }
0ff4390d 3665
0a2aaacc 3666 return new_rtx;
9db1d521
HP		 3667}
3668
fd3cd001
UW		 3669/* Load the thread pointer into a register. */
3670
7b8acc34
AK		 3671rtx
3672s390_get_thread_pointer (void)
fd3cd001 3673{
c5aa1d12 3674 rtx tp = gen_reg_rtx (Pmode);
fd3cd001 3675
c5aa1d12 3676 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
fd3cd001
UW		 3677 mark_reg_pointer (tp, BITS_PER_WORD);
3678
3679 return tp;
3680}
3681
ed9676cf
AK		 3682/* Emit a tls call insn. The call target is the SYMBOL_REF stored
3683 in s390_tls_symbol which always refers to __tls_get_offset.
3684 The returned offset is written to RESULT_REG and an USE rtx is
3685 generated for TLS_CALL. */
fd3cd001
UW		 3686
3687static GTY(()) rtx s390_tls_symbol;
ed9676cf
AK		 3688
3689static void
3690s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
fd3cd001 3691{
ed9676cf 3692 rtx insn;
38899e29 3693
68c0ef75
AK		 3694 if (!flag_pic)
3695 emit_insn (s390_load_got ());
ed9676cf 3696
fd3cd001
UW		 3697 if (!s390_tls_symbol)
3698 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3699
38899e29
EC		 3700 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3701 gen_rtx_REG (Pmode, RETURN_REGNUM));
ed9676cf
AK		 3702
3703 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
becfd6e5 3704 RTL_CONST_CALL_P (insn) = 1;
fd3cd001
UW		 3705}
3706
3707/* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3708 this (thread-local) address. REG may be used as temporary. */
3709
3710static rtx
9c808aad 3711legitimize_tls_address (rtx addr, rtx reg)
fd3cd001 3712{
0a2aaacc 3713 rtx new_rtx, tls_call, temp, base, r2, insn;
fd3cd001
UW		 3714
3715 if (GET_CODE (addr) == SYMBOL_REF)
3716 switch (tls_symbolic_operand (addr))
3717 {
3718 case TLS_MODEL_GLOBAL_DYNAMIC:
3719 start_sequence ();
3720 r2 = gen_rtx_REG (Pmode, 2);
3721 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
0a2aaacc
KG		 3722 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3723 new_rtx = force_const_mem (Pmode, new_rtx);
3724 emit_move_insn (r2, new_rtx);
ed9676cf 3725 s390_emit_tls_call_insn (r2, tls_call);
fd3cd001
UW		 3726 insn = get_insns ();
3727 end_sequence ();
3728
0a2aaacc 3729 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
fd3cd001 3730 temp = gen_reg_rtx (Pmode);
0a2aaacc 3731 emit_libcall_block (insn, temp, r2, new_rtx);
fd3cd001 3732
0a2aaacc 3733 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
fd3cd001
UW		 3734 if (reg != 0)
3735 {
0a2aaacc
KG		 3736 s390_load_address (reg, new_rtx);
3737 new_rtx = reg;
fd3cd001
UW		 3738 }
3739 break;
3740
3741 case TLS_MODEL_LOCAL_DYNAMIC:
3742 start_sequence ();
3743 r2 = gen_rtx_REG (Pmode, 2);
3744 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
0a2aaacc
KG		 3745 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3746 new_rtx = force_const_mem (Pmode, new_rtx);
3747 emit_move_insn (r2, new_rtx);
ed9676cf 3748 s390_emit_tls_call_insn (r2, tls_call);
fd3cd001
UW		 3749 insn = get_insns ();
3750 end_sequence ();
3751
0a2aaacc 3752 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
fd3cd001 3753 temp = gen_reg_rtx (Pmode);
0a2aaacc 3754 emit_libcall_block (insn, temp, r2, new_rtx);
fd3cd001 3755
0a2aaacc 3756 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
fd3cd001 3757 base = gen_reg_rtx (Pmode);
0a2aaacc 3758 s390_load_address (base, new_rtx);
fd3cd001 3759
0a2aaacc
KG		 3760 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3761 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3762 new_rtx = force_const_mem (Pmode, new_rtx);
fd3cd001 3763 temp = gen_reg_rtx (Pmode);
0a2aaacc 3764 emit_move_insn (temp, new_rtx);
fd3cd001 3765
0a2aaacc 3766 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
fd3cd001
UW		 3767 if (reg != 0)
3768 {
0a2aaacc
KG		 3769 s390_load_address (reg, new_rtx);
3770 new_rtx = reg;
fd3cd001
UW		 3771 }
3772 break;
3773
3774 case TLS_MODEL_INITIAL_EXEC:
3775 if (flag_pic == 1)
3776 {
3777 /* Assume GOT offset < 4k. This is handled the same way
3778 in both 31- and 64-bit code. */
3779
3780 if (reload_in_progress || reload_completed)
6fb5fa3c 3781 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
fd3cd001 3782
0a2aaacc
KG		 3783 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3784 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3785 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3786 new_rtx = gen_const_mem (Pmode, new_rtx);
fd3cd001 3787 temp = gen_reg_rtx (Pmode);
0a2aaacc 3788 emit_move_insn (temp, new_rtx);
fd3cd001 3789 }
9e8327e3 3790 else if (TARGET_CPU_ZARCH)
fd3cd001
UW		 3791 {
3792 /* If the GOT offset might be >= 4k, we determine the position
3793 of the GOT entry via a PC-relative LARL. */
3794
0a2aaacc
KG		 3795 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3796 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
fd3cd001 3797 temp = gen_reg_rtx (Pmode);
0a2aaacc 3798 emit_move_insn (temp, new_rtx);
fd3cd001 3799
0a2aaacc 3800 new_rtx = gen_const_mem (Pmode, temp);
fd3cd001 3801 temp = gen_reg_rtx (Pmode);
0a2aaacc 3802 emit_move_insn (temp, new_rtx);
fd3cd001
UW		 3803 }
3804 else if (flag_pic)
3805 {
c7453384 3806 /* If the GOT offset might be >= 4k, we have to load it
fd3cd001
UW		 3807 from the literal pool. */
3808
3809 if (reload_in_progress || reload_completed)
6fb5fa3c 3810 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
fd3cd001 3811
0a2aaacc
KG		 3812 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3813 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3814 new_rtx = force_const_mem (Pmode, new_rtx);
fd3cd001 3815 temp = gen_reg_rtx (Pmode);
0a2aaacc 3816 emit_move_insn (temp, new_rtx);
fd3cd001 3817
0a2aaacc
KG		 3818 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3819 new_rtx = gen_const_mem (Pmode, new_rtx);
fd3cd001 3820
0a2aaacc 3821 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
fd3cd001 3822 temp = gen_reg_rtx (Pmode);
0a2aaacc 3823 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
fd3cd001
UW		 3824 }
3825 else
3826 {
3827 /* In position-dependent code, load the absolute address of
3828 the GOT entry from the literal pool. */
3829
0a2aaacc
KG		 3830 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3831 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3832 new_rtx = force_const_mem (Pmode, new_rtx);
fd3cd001 3833 temp = gen_reg_rtx (Pmode);
0a2aaacc 3834 emit_move_insn (temp, new_rtx);
fd3cd001 3835
0a2aaacc
KG		 3836 new_rtx = temp;
3837 new_rtx = gen_const_mem (Pmode, new_rtx);
3838 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
fd3cd001 3839 temp = gen_reg_rtx (Pmode);
0a2aaacc 3840 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
fd3cd001
UW		 3841 }
3842
0a2aaacc 3843 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
fd3cd001
UW		 3844 if (reg != 0)
3845 {
0a2aaacc
KG		 3846 s390_load_address (reg, new_rtx);
3847 new_rtx = reg;
fd3cd001
UW		 3848 }
3849 break;
3850
3851 case TLS_MODEL_LOCAL_EXEC:
0a2aaacc
KG		 3852 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3853 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3854 new_rtx = force_const_mem (Pmode, new_rtx);
fd3cd001 3855 temp = gen_reg_rtx (Pmode);
0a2aaacc 3856 emit_move_insn (temp, new_rtx);
fd3cd001 3857
0a2aaacc 3858 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
fd3cd001
UW		 3859 if (reg != 0)
3860 {
0a2aaacc
KG		 3861 s390_load_address (reg, new_rtx);
3862 new_rtx = reg;
fd3cd001
UW		 3863 }
3864 break;
3865
3866 default:
8d933e31 3867 gcc_unreachable ();
fd3cd001
UW		 3868 }
3869
3870 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3871 {
3872 switch (XINT (XEXP (addr, 0), 1))
3873 {
3874 case UNSPEC_INDNTPOFF:
8d933e31 3875 gcc_assert (TARGET_CPU_ZARCH);
0a2aaacc 3876 new_rtx = addr;
fd3cd001
UW		 3877 break;
3878
3879 default:
8d933e31 3880 gcc_unreachable ();
fd3cd001
UW		 3881 }
3882 }
3883
578d1468
UW		 3884 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3885 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3886 {
0a2aaacc
KG		 3887 new_rtx = XEXP (XEXP (addr, 0), 0);
3888 if (GET_CODE (new_rtx) != SYMBOL_REF)
3889 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
578d1468 3890
0a2aaacc 3891 new_rtx = legitimize_tls_address (new_rtx, reg);
0a81f074
RS		 3892 new_rtx = plus_constant (Pmode, new_rtx,
3893 INTVAL (XEXP (XEXP (addr, 0), 1)));
0a2aaacc 3894 new_rtx = force_operand (new_rtx, 0);
578d1468
UW		 3895 }
3896
fd3cd001 3897 else
8d933e31 3898 gcc_unreachable (); /* for now ... */
fd3cd001 3899
0a2aaacc 3900 return new_rtx;
fd3cd001
UW		 3901}
3902
1f9e1fc6
AK		 3903/* Emit insns making the address in operands[1] valid for a standard
3904 move to operands[0]. operands[1] is replaced by an address which
3905 should be used instead of the former RTX to emit the move
3906 pattern. */
9db1d521
HP		 3907
3908void
9c808aad 3909emit_symbolic_move (rtx *operands)
9db1d521 3910{
b3a13419 3911 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
9db1d521 3912
fd3cd001 3913 if (GET_CODE (operands[0]) == MEM)
9db1d521 3914 operands[1] = force_reg (Pmode, operands[1]);
fd3cd001
UW		 3915 else if (TLS_SYMBOLIC_CONST (operands[1]))
3916 operands[1] = legitimize_tls_address (operands[1], temp);
3917 else if (flag_pic)
9db1d521
HP		 3918 operands[1] = legitimize_pic_address (operands[1], temp);
3919}
3920
994fe660 3921/* Try machine-dependent ways of modifying an illegitimate address X
9db1d521 3922 to be legitimate. If we find one, return the new, valid address.
9db1d521
HP		 3923
3924 OLDX is the address as it was before break_out_memory_refs was called.
3925 In some cases it is useful to look at this to decide what needs to be done.
3926
994fe660 3927 MODE is the mode of the operand pointed to by X.
9db1d521
HP		 3928
3929 When -fpic is used, special handling is needed for symbolic references.
3930 See comments by legitimize_pic_address for details. */
3931
506d7b68
PB		 3932static rtx
3933s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
ef4bddc2 3934 machine_mode mode ATTRIBUTE_UNUSED)
9db1d521 3935{
ba956982 3936 rtx constant_term = const0_rtx;
9db1d521 3937
fd3cd001
UW		 3938 if (TLS_SYMBOLIC_CONST (x))
3939 {
3940 x = legitimize_tls_address (x, 0);
3941
c6c3dba9 3942 if (s390_legitimate_address_p (mode, x, FALSE))
fd3cd001
UW		 3943 return x;
3944 }
cf9d7618 3945 else if (GET_CODE (x) == PLUS
f4aa3848 3946 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
cf9d7618
ANM		 3947 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
3948 {
3949 return x;
3950 }
fd3cd001 3951 else if (flag_pic)
9db1d521 3952 {
ba956982 3953 if (SYMBOLIC_CONST (x)
c7453384
EC		 3954 || (GET_CODE (x) == PLUS
3955 && (SYMBOLIC_CONST (XEXP (x, 0))
ba956982
UW		 3956 || SYMBOLIC_CONST (XEXP (x, 1)))))
3957 x = legitimize_pic_address (x, 0);
3958
c6c3dba9 3959 if (s390_legitimate_address_p (mode, x, FALSE))
ba956982 3960 return x;
9db1d521 3961 }
9db1d521 3962
ba956982 3963 x = eliminate_constant_term (x, &constant_term);
994fe660 3964
61f02ff5
UW		 3965 /* Optimize loading of large displacements by splitting them
3966 into the multiple of 4K and the rest; this allows the
c7453384 3967 former to be CSE'd if possible.
61f02ff5
UW		 3968
3969 Don't do this if the displacement is added to a register
3970 pointing into the stack frame, as the offsets will
3971 change later anyway. */
3972
3973 if (GET_CODE (constant_term) == CONST_INT
d3632d41
UW		 3974 && !TARGET_LONG_DISPLACEMENT
3975 && !DISP_IN_RANGE (INTVAL (constant_term))
61f02ff5
UW		 3976 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
3977 {
3978 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
3979 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
3980
3981 rtx temp = gen_reg_rtx (Pmode);
3982 rtx val = force_operand (GEN_INT (upper), temp);
3983 if (val != temp)
3984 emit_move_insn (temp, val);
3985
3986 x = gen_rtx_PLUS (Pmode, x, temp);
3987 constant_term = GEN_INT (lower);
3988 }
3989
ba956982 3990 if (GET_CODE (x) == PLUS)
9db1d521 3991 {
ba956982
UW		 3992 if (GET_CODE (XEXP (x, 0)) == REG)
3993 {
5d81b82b
AS		 3994 rtx temp = gen_reg_rtx (Pmode);
3995 rtx val = force_operand (XEXP (x, 1), temp);
ba956982
UW		 3996 if (val != temp)
3997 emit_move_insn (temp, val);
3998
3999 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
4000 }
4001
4002 else if (GET_CODE (XEXP (x, 1)) == REG)
4003 {
5d81b82b
AS		 4004 rtx temp = gen_reg_rtx (Pmode);
4005 rtx val = force_operand (XEXP (x, 0), temp);
ba956982
UW		 4006 if (val != temp)
4007 emit_move_insn (temp, val);
4008
4009 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
4010 }
9db1d521 4011 }
ba956982
UW		 4012
4013 if (constant_term != const0_rtx)
4014 x = gen_rtx_PLUS (Pmode, x, constant_term);
4015
4016 return x;
9db1d521
HP		 4017}
4018
0b540f12 4019/* Try a machine-dependent way of reloading an illegitimate address AD
dd5a833e 4020 operand. If we find one, push the reload and return the new address.
0b540f12
UW		 4021
4022 MODE is the mode of the enclosing MEM. OPNUM is the operand number
4023 and TYPE is the reload type of the current reload. */
4024
f4aa3848 4025rtx
ef4bddc2 4026legitimize_reload_address (rtx ad, machine_mode mode ATTRIBUTE_UNUSED,
0b540f12
UW		 4027 int opnum, int type)
4028{
4029 if (!optimize || TARGET_LONG_DISPLACEMENT)
4030 return NULL_RTX;
4031
4032 if (GET_CODE (ad) == PLUS)
4033 {
4034 rtx tem = simplify_binary_operation (PLUS, Pmode,
4035 XEXP (ad, 0), XEXP (ad, 1));
4036 if (tem)
4037 ad = tem;
4038 }
4039
4040 if (GET_CODE (ad) == PLUS
4041 && GET_CODE (XEXP (ad, 0)) == REG
4042 && GET_CODE (XEXP (ad, 1)) == CONST_INT
4043 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
4044 {
4045 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
4046 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
0a2aaacc 4047 rtx cst, tem, new_rtx;
0b540f12
UW		 4048
4049 cst = GEN_INT (upper);
4050 if (!legitimate_reload_constant_p (cst))
4051 cst = force_const_mem (Pmode, cst);
4052
4053 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
0a2aaacc 4054 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
0b540f12
UW		 4055
4056 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
f4aa3848 4057 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
0b540f12 4058 opnum, (enum reload_type) type);
0a2aaacc 4059 return new_rtx;
0b540f12
UW		 4060 }
4061
4062 return NULL_RTX;
4063}
4064
a41c6c53
UW		 4065/* Emit code to move LEN bytes from DST to SRC. */
4066
367d32f3 4067bool
70128ad9 4068s390_expand_movmem (rtx dst, rtx src, rtx len)
a41c6c53 4069{
367d32f3
AK		 4070 /* When tuning for z10 or higher we rely on the Glibc functions to
4071 do the right thing. Only for constant lengths below 64k we will
4072 generate inline code. */
4073 if (s390_tune >= PROCESSOR_2097_Z10
4074 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4075 return false;
4076
a41c6c53
UW		 4077 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4078 {
4079 if (INTVAL (len) > 0)
70128ad9 4080 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
a41c6c53
UW		 4081 }
4082
4083 else if (TARGET_MVCLE)
4084 {
70128ad9 4085 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
a41c6c53
UW		 4086 }
4087
4088 else
4089 {
4090 rtx dst_addr, src_addr, count, blocks, temp;
19f8b229
TS		 4091 rtx_code_label *loop_start_label = gen_label_rtx ();
4092 rtx_code_label *loop_end_label = gen_label_rtx ();
4093 rtx_code_label *end_label = gen_label_rtx ();
ef4bddc2 4094 machine_mode mode;
a41c6c53
UW		 4095
4096 mode = GET_MODE (len);
4097 if (mode == VOIDmode)
b9404c99 4098 mode = Pmode;
a41c6c53 4099
a41c6c53
UW		 4100 dst_addr = gen_reg_rtx (Pmode);
4101 src_addr = gen_reg_rtx (Pmode);
4102 count = gen_reg_rtx (mode);
4103 blocks = gen_reg_rtx (mode);
4104
4105 convert_move (count, len, 1);
c7453384 4106 emit_cmp_and_jump_insns (count, const0_rtx,
a41c6c53
UW		 4107 EQ, NULL_RTX, mode, 1, end_label);
4108
4109 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4110 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
4111 dst = change_address (dst, VOIDmode, dst_addr);
4112 src = change_address (src, VOIDmode, src_addr);
c7453384 4113
bbbbb16a
ILT		 4114 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4115 OPTAB_DIRECT);
a41c6c53
UW		 4116 if (temp != count)
4117 emit_move_insn (count, temp);
4118
bbbbb16a
ILT		 4119 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4120 OPTAB_DIRECT);
a41c6c53
UW		 4121 if (temp != blocks)
4122 emit_move_insn (blocks, temp);
4123
6de9cd9a
DN		 4124 emit_cmp_and_jump_insns (blocks, const0_rtx,
4125 EQ, NULL_RTX, mode, 1, loop_end_label);
70315fcd
SB		 4126
4127 emit_label (loop_start_label);
a41c6c53 4128
adfa3cd3
AK		 4129 if (TARGET_Z10
4130 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
4131 {
4132 rtx prefetch;
4133
4134 /* Issue a read prefetch for the +3 cache line. */
4135 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
4136 const0_rtx, const0_rtx);
4137 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4138 emit_insn (prefetch);
4139
4140 /* Issue a write prefetch for the +3 cache line. */
4141 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
4142 const1_rtx, const0_rtx);
4143 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4144 emit_insn (prefetch);
4145 }
4146
70128ad9 4147 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
c7453384 4148 s390_load_address (dst_addr,
a41c6c53 4149 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
c7453384 4150 s390_load_address (src_addr,
a41c6c53 4151 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
c7453384 4152
bbbbb16a
ILT		 4153 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4154 OPTAB_DIRECT);
a41c6c53
UW		 4155 if (temp != blocks)
4156 emit_move_insn (blocks, temp);
4157
6de9cd9a
DN		 4158 emit_cmp_and_jump_insns (blocks, const0_rtx,
4159 EQ, NULL_RTX, mode, 1, loop_end_label);
70315fcd
SB		 4160
4161 emit_jump (loop_start_label);
6de9cd9a 4162 emit_label (loop_end_label);
a41c6c53 4163
70128ad9 4164 emit_insn (gen_movmem_short (dst, src,
b9404c99 4165 convert_to_mode (Pmode, count, 1)));
a41c6c53
UW		 4166 emit_label (end_label);
4167 }
367d32f3 4168 return true;
a41c6c53
UW		 4169}
4170
6d057022
AS		 4171/* Emit code to set LEN bytes at DST to VAL.
4172 Make use of clrmem if VAL is zero. */
a41c6c53
UW		 4173
4174void
6d057022 4175s390_expand_setmem (rtx dst, rtx len, rtx val)
a41c6c53 4176{
c9f59991
AK		 4177 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4178 return;
4179
6d057022 4180 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
f4aa3848 4181
c9f59991 4182 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
a41c6c53 4183 {
6d057022 4184 if (val == const0_rtx && INTVAL (len) <= 256)
70128ad9 4185 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
6d057022
AS		 4186 else
4187 {
4188 /* Initialize memory by storing the first byte. */
4189 emit_move_insn (adjust_address (dst, QImode, 0), val);
f4aa3848 4190
6d057022
AS		 4191 if (INTVAL (len) > 1)
4192 {
4193 /* Initiate 1 byte overlap move.
4194 The first byte of DST is propagated through DSTP1.
4195 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4196 DST is set to size 1 so the rest of the memory location
4197 does not count as source operand. */
4198 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
f5541398 4199 set_mem_size (dst, 1);
6d057022 4200
f4aa3848 4201 emit_insn (gen_movmem_short (dstp1, dst,
6d057022
AS		 4202 GEN_INT (INTVAL (len) - 2)));
4203 }
4204 }
a41c6c53
UW		 4205 }
4206
4207 else if (TARGET_MVCLE)
4208 {
6d057022
AS		 4209 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4210 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
a41c6c53
UW		 4211 }
4212
4213 else
4214 {
9602b6a1 4215 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
19f8b229
TS		 4216 rtx_code_label *loop_start_label = gen_label_rtx ();
4217 rtx_code_label *loop_end_label = gen_label_rtx ();
4218 rtx_code_label *end_label = gen_label_rtx ();
ef4bddc2 4219 machine_mode mode;
a41c6c53
UW		 4220
4221 mode = GET_MODE (len);
4222 if (mode == VOIDmode)
b9404c99 4223 mode = Pmode;
a41c6c53 4224
a41c6c53 4225 dst_addr = gen_reg_rtx (Pmode);
a41c6c53
UW		 4226 count = gen_reg_rtx (mode);
4227 blocks = gen_reg_rtx (mode);
4228
4229 convert_move (count, len, 1);
c7453384 4230 emit_cmp_and_jump_insns (count, const0_rtx,
a41c6c53
UW		 4231 EQ, NULL_RTX, mode, 1, end_label);
4232
4233 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4234 dst = change_address (dst, VOIDmode, dst_addr);
c7453384 4235
6d057022 4236 if (val == const0_rtx)
bbbbb16a
ILT		 4237 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4238 OPTAB_DIRECT);
6d057022
AS		 4239 else
4240 {
4241 dstp1 = adjust_address (dst, VOIDmode, 1);
f5541398 4242 set_mem_size (dst, 1);
6d057022
AS		 4243
4244 /* Initialize memory by storing the first byte. */
4245 emit_move_insn (adjust_address (dst, QImode, 0), val);
f4aa3848 4246
6d057022
AS		 4247 /* If count is 1 we are done. */
4248 emit_cmp_and_jump_insns (count, const1_rtx,
4249 EQ, NULL_RTX, mode, 1, end_label);
4250
bbbbb16a
ILT		 4251 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4252 OPTAB_DIRECT);
6d057022 4253 }
a41c6c53
UW		 4254 if (temp != count)
4255 emit_move_insn (count, temp);
4256
bbbbb16a
ILT		 4257 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4258 OPTAB_DIRECT);
a41c6c53
UW		 4259 if (temp != blocks)
4260 emit_move_insn (blocks, temp);
4261
6de9cd9a
DN		 4262 emit_cmp_and_jump_insns (blocks, const0_rtx,
4263 EQ, NULL_RTX, mode, 1, loop_end_label);
70315fcd
SB		 4264
4265 emit_label (loop_start_label);
a41c6c53 4266
adfa3cd3
AK		 4267 if (TARGET_Z10
4268 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4269 {
4270 /* Issue a write prefetch for the +4 cache line. */
4271 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4272 GEN_INT (1024)),
4273 const1_rtx, const0_rtx);
4274 emit_insn (prefetch);
4275 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4276 }
4277
6d057022
AS		 4278 if (val == const0_rtx)
4279 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4280 else
4281 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
c7453384 4282 s390_load_address (dst_addr,
a41c6c53 4283 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
c7453384 4284
bbbbb16a
ILT		 4285 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4286 OPTAB_DIRECT);
a41c6c53
UW		 4287 if (temp != blocks)
4288 emit_move_insn (blocks, temp);
4289
6de9cd9a
DN		 4290 emit_cmp_and_jump_insns (blocks, const0_rtx,
4291 EQ, NULL_RTX, mode, 1, loop_end_label);
70315fcd
SB		 4292
4293 emit_jump (loop_start_label);
6de9cd9a 4294 emit_label (loop_end_label);
a41c6c53 4295
6d057022
AS		 4296 if (val == const0_rtx)
4297 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4298 else
4299 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
a41c6c53
UW		 4300 emit_label (end_label);
4301 }
4302}
4303
4304/* Emit code to compare LEN bytes at OP0 with those at OP1,
4305 and return the result in TARGET. */
4306
367d32f3 4307bool
9c808aad 4308s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
a41c6c53 4309{
5b022de5 4310 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
02887425
UW		 4311 rtx tmp;
4312
367d32f3
AK		 4313 /* When tuning for z10 or higher we rely on the Glibc functions to
4314 do the right thing. Only for constant lengths below 64k we will
4315 generate inline code. */
4316 if (s390_tune >= PROCESSOR_2097_Z10
4317 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4318 return false;
4319
02887425
UW		 4320 /* As the result of CMPINT is inverted compared to what we need,
4321 we have to swap the operands. */
4322 tmp = op0; op0 = op1; op1 = tmp;
a41c6c53 4323
a41c6c53
UW		 4324 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4325 {
4326 if (INTVAL (len) > 0)
4327 {
b9404c99 4328 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
02887425 4329 emit_insn (gen_cmpint (target, ccreg));
a41c6c53
UW		 4330 }
4331 else
4332 emit_move_insn (target, const0_rtx);
4333 }
9dc62c00 4334 else if (TARGET_MVCLE)
a41c6c53 4335 {
b9404c99 4336 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
02887425 4337 emit_insn (gen_cmpint (target, ccreg));
a41c6c53 4338 }
a41c6c53
UW		 4339 else
4340 {
4341 rtx addr0, addr1, count, blocks, temp;
19f8b229
TS		 4342 rtx_code_label *loop_start_label = gen_label_rtx ();
4343 rtx_code_label *loop_end_label = gen_label_rtx ();
4344 rtx_code_label *end_label = gen_label_rtx ();
ef4bddc2 4345 machine_mode mode;
a41c6c53
UW		 4346
4347 mode = GET_MODE (len);
4348 if (mode == VOIDmode)
b9404c99 4349 mode = Pmode;
a41c6c53 4350
a41c6c53
UW		 4351 addr0 = gen_reg_rtx (Pmode);
4352 addr1 = gen_reg_rtx (Pmode);
4353 count = gen_reg_rtx (mode);
4354 blocks = gen_reg_rtx (mode);
4355
4356 convert_move (count, len, 1);
c7453384 4357 emit_cmp_and_jump_insns (count, const0_rtx,
a41c6c53
UW		 4358 EQ, NULL_RTX, mode, 1, end_label);
4359
4360 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4361 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4362 op0 = change_address (op0, VOIDmode, addr0);
4363 op1 = change_address (op1, VOIDmode, addr1);
c7453384 4364
bbbbb16a
ILT		 4365 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4366 OPTAB_DIRECT);
a41c6c53
UW		 4367 if (temp != count)
4368 emit_move_insn (count, temp);
4369
bbbbb16a
ILT		 4370 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4371 OPTAB_DIRECT);
a41c6c53
UW		 4372 if (temp != blocks)
4373 emit_move_insn (blocks, temp);
4374
6de9cd9a
DN		 4375 emit_cmp_and_jump_insns (blocks, const0_rtx,
4376 EQ, NULL_RTX, mode, 1, loop_end_label);
70315fcd
SB		 4377
4378 emit_label (loop_start_label);
a41c6c53 4379
adfa3cd3
AK		 4380 if (TARGET_Z10
4381 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4382 {
4383 rtx prefetch;
4384
4385 /* Issue a read prefetch for the +2 cache line of operand 1. */
4386 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4387 const0_rtx, const0_rtx);
4388 emit_insn (prefetch);
4389 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4390
4391 /* Issue a read prefetch for the +2 cache line of operand 2. */
4392 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4393 const0_rtx, const0_rtx);
4394 emit_insn (prefetch);
4395 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4396 }
4397
b9404c99 4398 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
5b022de5 4399 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
c7453384 4400 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
a41c6c53
UW		 4401 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4402 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4403 emit_jump_insn (temp);
4404
c7453384 4405 s390_load_address (addr0,
a41c6c53 4406 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
c7453384 4407 s390_load_address (addr1,
a41c6c53 4408 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
c7453384 4409
bbbbb16a
ILT		 4410 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4411 OPTAB_DIRECT);
a41c6c53
UW		 4412 if (temp != blocks)
4413 emit_move_insn (blocks, temp);
4414
6de9cd9a
DN		 4415 emit_cmp_and_jump_insns (blocks, const0_rtx,
4416 EQ, NULL_RTX, mode, 1, loop_end_label);
70315fcd
SB		 4417
4418 emit_jump (loop_start_label);
6de9cd9a 4419 emit_label (loop_end_label);
a41c6c53 4420
38899e29 4421 emit_insn (gen_cmpmem_short (op0, op1,
b9404c99 4422 convert_to_mode (Pmode, count, 1)));
a41c6c53
UW		 4423 emit_label (end_label);
4424
02887425 4425 emit_insn (gen_cmpint (target, ccreg));
a41c6c53 4426 }
367d32f3 4427 return true;
a41c6c53
UW		 4428}
4429
5d880bd2
UW		 4430
4431/* Expand conditional increment or decrement using alc/slb instructions.
4432 Should generate code setting DST to either SRC or SRC + INCREMENT,
4433 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
00bda920
AK		 4434 Returns true if successful, false otherwise.
4435
4436 That makes it possible to implement some if-constructs without jumps e.g.:
4437 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4438 unsigned int a, b, c;
4439 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4440 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4441 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4442 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4443
4444 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4445 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4446 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4447 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4448 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
5d880bd2
UW		 4449
4450bool
4451s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4452 rtx dst, rtx src, rtx increment)
4453{
ef4bddc2
RS		 4454 machine_mode cmp_mode;
4455 machine_mode cc_mode;
5d880bd2
UW		 4456 rtx op_res;
4457 rtx insn;
4458 rtvec p;
8d933e31 4459 int ret;
5d880bd2
UW		 4460
4461 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4462 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4463 cmp_mode = SImode;
4464 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4465 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4466 cmp_mode = DImode;
4467 else
4468 return false;
4469
4470 /* Try ADD LOGICAL WITH CARRY. */
4471 if (increment == const1_rtx)
4472 {
4473 /* Determine CC mode to use. */
4474 if (cmp_code == EQ || cmp_code == NE)
4475 {
4476 if (cmp_op1 != const0_rtx)
4477 {
4478 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4479 NULL_RTX, 0, OPTAB_WIDEN);
4480 cmp_op1 = const0_rtx;
4481 }
4482
4483 cmp_code = cmp_code == EQ ? LEU : GTU;
4484 }
4485
4486 if (cmp_code == LTU || cmp_code == LEU)
4487 {
4488 rtx tem = cmp_op0;
4489 cmp_op0 = cmp_op1;
4490 cmp_op1 = tem;
4491 cmp_code = swap_condition (cmp_code);
4492 }
4493
4494 switch (cmp_code)
4495 {
4496 case GTU:
4497 cc_mode = CCUmode;
4498 break;
4499
4500 case GEU:
4501 cc_mode = CCL3mode;
4502 break;
4503
4504 default:
4505 return false;
4506 }
4507
4508 /* Emit comparison instruction pattern. */
4509 if (!register_operand (cmp_op0, cmp_mode))
4510 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4511
4512 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4513 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4514 /* We use insn_invalid_p here to add clobbers if required. */
57ac4c34 4515 ret = insn_invalid_p (emit_insn (insn), false);
8d933e31 4516 gcc_assert (!ret);
5d880bd2
UW		 4517
4518 /* Emit ALC instruction pattern. */
4519 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4520 gen_rtx_REG (cc_mode, CC_REGNUM),
4521 const0_rtx);
4522
4523 if (src != const0_rtx)
4524 {
4525 if (!register_operand (src, GET_MODE (dst)))
4526 src = force_reg (GET_MODE (dst), src);
4527
a94a76a7
UW		 4528 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4529 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
5d880bd2
UW		 4530 }
4531
4532 p = rtvec_alloc (2);
f4aa3848 4533 RTVEC_ELT (p, 0) =
5d880bd2 4534 gen_rtx_SET (VOIDmode, dst, op_res);
f4aa3848 4535 RTVEC_ELT (p, 1) =
5d880bd2
UW		 4536 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4537 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4538
4539 return true;
4540 }
4541
4542 /* Try SUBTRACT LOGICAL WITH BORROW. */
4543 if (increment == constm1_rtx)
4544 {
4545 /* Determine CC mode to use. */
4546 if (cmp_code == EQ || cmp_code == NE)
4547 {
4548 if (cmp_op1 != const0_rtx)
4549 {
4550 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4551 NULL_RTX, 0, OPTAB_WIDEN);
4552 cmp_op1 = const0_rtx;
4553 }
4554
4555 cmp_code = cmp_code == EQ ? LEU : GTU;
4556 }
4557
4558 if (cmp_code == GTU || cmp_code == GEU)
4559 {
4560 rtx tem = cmp_op0;
4561 cmp_op0 = cmp_op1;
4562 cmp_op1 = tem;
4563 cmp_code = swap_condition (cmp_code);
4564 }
4565
4566 switch (cmp_code)
4567 {
4568 case LEU:
4569 cc_mode = CCUmode;
4570 break;
4571
4572 case LTU:
4573 cc_mode = CCL3mode;
4574 break;
4575
4576 default:
4577 return false;
4578 }
4579
4580 /* Emit comparison instruction pattern. */
4581 if (!register_operand (cmp_op0, cmp_mode))
4582 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4583
4584 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4585 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4586 /* We use insn_invalid_p here to add clobbers if required. */
57ac4c34 4587 ret = insn_invalid_p (emit_insn (insn), false);
8d933e31 4588 gcc_assert (!ret);
5d880bd2
UW		 4589
4590 /* Emit SLB instruction pattern. */
4591 if (!register_operand (src, GET_MODE (dst)))
4592 src = force_reg (GET_MODE (dst), src);
4593
f4aa3848
AK		 4594 op_res = gen_rtx_MINUS (GET_MODE (dst),
4595 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4596 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4597 gen_rtx_REG (cc_mode, CC_REGNUM),
5d880bd2
UW		 4598 const0_rtx));
4599 p = rtvec_alloc (2);
f4aa3848 4600 RTVEC_ELT (p, 0) =
5d880bd2 4601 gen_rtx_SET (VOIDmode, dst, op_res);
f4aa3848 4602 RTVEC_ELT (p, 1) =
5d880bd2
UW		 4603 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4604 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4605
4606 return true;
4607 }
4608
4609 return false;
4610}
4611
963fc8d0 4612/* Expand code for the insv template. Return true if successful. */
6fa05db6 4613
963fc8d0 4614bool
6fa05db6
AS		 4615s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4616{
4617 int bitsize = INTVAL (op1);
4618 int bitpos = INTVAL (op2);
ef4bddc2
RS		 4619 machine_mode mode = GET_MODE (dest);
4620 machine_mode smode;
78ce265b
RH		 4621 int smode_bsize, mode_bsize;
4622 rtx op, clobber;
6fa05db6 4623
a9d46e32 4624 if (bitsize + bitpos > GET_MODE_BITSIZE (mode))
03ed99a8
AK		 4625 return false;
4626
78ce265b
RH		 4627 /* Generate INSERT IMMEDIATE (IILL et al). */
4628 /* (set (ze (reg)) (const_int)). */
4629 if (TARGET_ZARCH
4630 && register_operand (dest, word_mode)
4631 && (bitpos % 16) == 0
4632 && (bitsize % 16) == 0
4633 && const_int_operand (src, VOIDmode))
963fc8d0 4634 {
78ce265b
RH		 4635 HOST_WIDE_INT val = INTVAL (src);
4636 int regpos = bitpos + bitsize;
963fc8d0 4637
78ce265b
RH		 4638 while (regpos > bitpos)
4639 {
ef4bddc2 4640 machine_mode putmode;
78ce265b
RH		 4641 int putsize;
4642
4643 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4644 putmode = SImode;
4645 else
4646 putmode = HImode;
963fc8d0 4647
78ce265b
RH		 4648 putsize = GET_MODE_BITSIZE (putmode);
4649 regpos -= putsize;
4650 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4651 GEN_INT (putsize),
4652 GEN_INT (regpos)),
4653 gen_int_mode (val, putmode));
4654 val >>= putsize;
4655 }
4656 gcc_assert (regpos == bitpos);
963fc8d0
AK		 4657 return true;
4658 }
4659
78ce265b
RH		 4660 smode = smallest_mode_for_size (bitsize, MODE_INT);
4661 smode_bsize = GET_MODE_BITSIZE (smode);
4662 mode_bsize = GET_MODE_BITSIZE (mode);
6fa05db6 4663
78ce265b 4664 /* Generate STORE CHARACTERS UNDER MASK (STCM et al). */
6fa05db6 4665 if (bitpos == 0
78ce265b
RH		 4666 && (bitsize % BITS_PER_UNIT) == 0
4667 && MEM_P (dest)
6fa05db6
AS		 4668 && (register_operand (src, word_mode)
4669 || const_int_operand (src, VOIDmode)))
4670 {
4671 /* Emit standard pattern if possible. */
78ce265b
RH		 4672 if (smode_bsize == bitsize)
4673 {
4674 emit_move_insn (adjust_address (dest, smode, 0),
4675 gen_lowpart (smode, src));
4676 return true;
4677 }
6fa05db6
AS		 4678
4679 /* (set (ze (mem)) (const_int)). */
4680 else if (const_int_operand (src, VOIDmode))
4681 {
4682 int size = bitsize / BITS_PER_UNIT;
78ce265b
RH		 4683 rtx src_mem = adjust_address (force_const_mem (word_mode, src),
4684 BLKmode,
4685 UNITS_PER_WORD - size);
6fa05db6
AS		 4686
4687 dest = adjust_address (dest, BLKmode, 0);
f5541398 4688 set_mem_size (dest, size);
6fa05db6 4689 s390_expand_movmem (dest, src_mem, GEN_INT (size));
78ce265b 4690 return true;
6fa05db6 4691 }
f4aa3848 4692
6fa05db6
AS		 4693 /* (set (ze (mem)) (reg)). */
4694 else if (register_operand (src, word_mode))
4695 {
78ce265b 4696 if (bitsize <= 32)
6fa05db6
AS		 4697 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4698 const0_rtx), src);
4699 else
4700 {
4701 /* Emit st,stcmh sequence. */
78ce265b 4702 int stcmh_width = bitsize - 32;
6fa05db6
AS		 4703 int size = stcmh_width / BITS_PER_UNIT;
4704
f4aa3848 4705 emit_move_insn (adjust_address (dest, SImode, size),
6fa05db6 4706 gen_lowpart (SImode, src));
f5541398 4707 set_mem_size (dest, size);
78ce265b
RH		 4708 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4709 GEN_INT (stcmh_width),
4710 const0_rtx),
4711 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT (32)));
6fa05db6 4712 }
78ce265b 4713 return true;
6fa05db6 4714 }
78ce265b 4715 }
6fa05db6 4716
78ce265b
RH		 4717 /* Generate INSERT CHARACTERS UNDER MASK (IC, ICM et al). */
4718 if ((bitpos % BITS_PER_UNIT) == 0
4719 && (bitsize % BITS_PER_UNIT) == 0
4720 && (bitpos & 32) == ((bitpos + bitsize - 1) & 32)
4721 && MEM_P (src)
4722 && (mode == DImode || mode == SImode)
4723 && register_operand (dest, mode))
4724 {
4725 /* Emit a strict_low_part pattern if possible. */
4726 if (smode_bsize == bitsize && bitpos == mode_bsize - smode_bsize)
4727 {
4728 op = gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (smode, dest));
4729 op = gen_rtx_SET (VOIDmode, op, gen_lowpart (smode, src));
4730 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4731 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4732 return true;
4733 }
4734
4735 /* ??? There are more powerful versions of ICM that are not
4736 completely represented in the md file. */
6fa05db6
AS		 4737 }
4738
78ce265b
RH		 4739 /* For z10, generate ROTATE THEN INSERT SELECTED BITS (RISBG et al). */
4740 if (TARGET_Z10 && (mode == DImode || mode == SImode))
6fa05db6 4741 {
ef4bddc2 4742 machine_mode mode_s = GET_MODE (src);
6fa05db6 4743
78ce265b 4744 if (mode_s == VOIDmode)
6fa05db6 4745 {
78ce265b
RH		 4746 /* Assume const_int etc already in the proper mode. */
4747 src = force_reg (mode, src);
4748 }
4749 else if (mode_s != mode)
4750 {
4751 gcc_assert (GET_MODE_BITSIZE (mode_s) >= bitsize);
4752 src = force_reg (mode_s, src);
4753 src = gen_lowpart (mode, src);
4754 }
6fa05db6 4755
0d8e4dac
RH		 4756 op = gen_rtx_ZERO_EXTRACT (mode, dest, op1, op2),
4757 op = gen_rtx_SET (VOIDmode, op, src);
22ac2c2f
AK		 4758
4759 if (!TARGET_ZEC12)
4760 {
4761 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4762 op = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber));
4763 }
4764 emit_insn (op);
6fa05db6 4765
6fa05db6
AS		 4766 return true;
4767 }
4768
4769 return false;
4770}
5d880bd2 4771
45d18331
AS		 4772/* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4773 register that holds VAL of mode MODE shifted by COUNT bits. */
3093f076
AS		 4774
4775static inline rtx
ef4bddc2 4776s390_expand_mask_and_shift (rtx val, machine_mode mode, rtx count)
3093f076
AS		 4777{
4778 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4779 NULL_RTX, 1, OPTAB_DIRECT);
f4aa3848 4780 return expand_simple_binop (SImode, ASHIFT, val, count,
3093f076
AS		 4781 NULL_RTX, 1, OPTAB_DIRECT);
4782}
4783
4784/* Structure to hold the initial parameters for a compare_and_swap operation
f4aa3848 4785 in HImode and QImode. */
3093f076
AS		 4786
4787struct alignment_context
4788{
f4aa3848 4789 rtx memsi; /* SI aligned memory location. */
3093f076
AS		 4790 rtx shift; /* Bit offset with regard to lsb. */
4791 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4792 rtx modemaski; /* ~modemask */
6416ae7f 4793 bool aligned; /* True if memory is aligned, false else. */
3093f076
AS		 4794};
4795
45d18331
AS		 4796/* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4797 structure AC for transparent simplifying, if the memory alignment is known
4798 to be at least 32bit. MEM is the memory location for the actual operation
4799 and MODE its mode. */
3093f076
AS		 4800
4801static void
4802init_alignment_context (struct alignment_context *ac, rtx mem,
ef4bddc2 4803 machine_mode mode)
3093f076
AS		 4804{
4805 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4806 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4807
4808 if (ac->aligned)
4809 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4810 else
4811 {
4812 /* Alignment is unknown. */
4813 rtx byteoffset, addr, align;
4814
4815 /* Force the address into a register. */
4816 addr = force_reg (Pmode, XEXP (mem, 0));
4817
4818 /* Align it to SImode. */
4819 align = expand_simple_binop (Pmode, AND, addr,
4820 GEN_INT (-GET_MODE_SIZE (SImode)),
4821 NULL_RTX, 1, OPTAB_DIRECT);
4822 /* Generate MEM. */
4823 ac->memsi = gen_rtx_MEM (SImode, align);
4824 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
44d64274 4825 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
3093f076
AS		 4826 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4827
4828 /* Calculate shiftcount. */
4829 byteoffset = expand_simple_binop (Pmode, AND, addr,
4830 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4831 NULL_RTX, 1, OPTAB_DIRECT);
4832 /* As we already have some offset, evaluate the remaining distance. */
4833 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4834 NULL_RTX, 1, OPTAB_DIRECT);
3093f076 4835 }
78ce265b 4836
3093f076 4837 /* Shift is the byte count, but we need the bitcount. */
78ce265b
RH		 4838 ac->shift = expand_simple_binop (SImode, ASHIFT, ac->shift, GEN_INT (3),
4839 NULL_RTX, 1, OPTAB_DIRECT);
4840
3093f076 4841 /* Calculate masks. */
f4aa3848 4842 ac->modemask = expand_simple_binop (SImode, ASHIFT,
78ce265b
RH		 4843 GEN_INT (GET_MODE_MASK (mode)),
4844 ac->shift, NULL_RTX, 1, OPTAB_DIRECT);
4845 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask,
4846 NULL_RTX, 1);
4847}
4848
4849/* A subroutine of s390_expand_cs_hqi. Insert INS into VAL. If possible,
4850 use a single insv insn into SEQ2. Otherwise, put prep insns in SEQ1 and
4851 perform the merge in SEQ2. */
4852
4853static rtx
4854s390_two_part_insv (struct alignment_context *ac, rtx *seq1, rtx *seq2,
ef4bddc2 4855 machine_mode mode, rtx val, rtx ins)
78ce265b
RH		 4856{
4857 rtx tmp;
4858
4859 if (ac->aligned)
4860 {
4861 start_sequence ();
4862 tmp = copy_to_mode_reg (SImode, val);
4863 if (s390_expand_insv (tmp, GEN_INT (GET_MODE_BITSIZE (mode)),
4864 const0_rtx, ins))
4865 {
4866 *seq1 = NULL;
4867 *seq2 = get_insns ();
4868 end_sequence ();
4869 return tmp;
4870 }
4871 end_sequence ();
4872 }
4873
4874 /* Failed to use insv. Generate a two part shift and mask. */
4875 start_sequence ();
4876 tmp = s390_expand_mask_and_shift (ins, mode, ac->shift);
4877 *seq1 = get_insns ();
4878 end_sequence ();
4879
4880 start_sequence ();
4881 tmp = expand_simple_binop (SImode, IOR, tmp, val, NULL_RTX, 1, OPTAB_DIRECT);
4882 *seq2 = get_insns ();
4883 end_sequence ();
4884
4885 return tmp;
3093f076
AS		 4886}
4887
4888/* Expand an atomic compare and swap operation for HImode and QImode. MEM is
78ce265b
RH		 4889 the memory location, CMP the old value to compare MEM with and NEW_RTX the
4890 value to set if CMP == MEM. */
3093f076
AS		 4891
4892void
ef4bddc2 4893s390_expand_cs_hqi (machine_mode mode, rtx btarget, rtx vtarget, rtx mem,
78ce265b 4894 rtx cmp, rtx new_rtx, bool is_weak)
3093f076
AS		 4895{
4896 struct alignment_context ac;
4e1ffb63 4897 rtx cmpv, newv, val, cc, seq0, seq1, seq2, seq3;
3093f076 4898 rtx res = gen_reg_rtx (SImode);
19f8b229 4899 rtx_code_label *csloop = NULL, *csend = NULL;
3093f076 4900
3093f076
AS		 4901 gcc_assert (MEM_P (mem));
4902
4903 init_alignment_context (&ac, mem, mode);
4904
3093f076
AS		 4905 /* Load full word. Subsequent loads are performed by CS. */
4906 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
4907 NULL_RTX, 1, OPTAB_DIRECT);
4908
78ce265b
RH		 4909 /* Prepare insertions of cmp and new_rtx into the loaded value. When
4910 possible, we try to use insv to make this happen efficiently. If
4911 that fails we'll generate code both inside and outside the loop. */
4912 cmpv = s390_two_part_insv (&ac, &seq0, &seq2, mode, val, cmp);
4913 newv = s390_two_part_insv (&ac, &seq1, &seq3, mode, val, new_rtx);
4914
4915 if (seq0)
4916 emit_insn (seq0);
4917 if (seq1)
4918 emit_insn (seq1);
4919
3093f076 4920 /* Start CS loop. */
78ce265b
RH		 4921 if (!is_weak)
4922 {
4923 /* Begin assuming success. */
4924 emit_move_insn (btarget, const1_rtx);
4925
4926 csloop = gen_label_rtx ();
4927 csend = gen_label_rtx ();
4928 emit_label (csloop);
4929 }
4930
f4aa3848 4931 /* val = "<mem>00..0<mem>"
3093f076 4932 * cmp = "00..0<cmp>00..0"
f4aa3848 4933 * new = "00..0<new>00..0"
3093f076
AS		 4934 */
4935
78ce265b
RH		 4936 emit_insn (seq2);
4937 emit_insn (seq3);
4938
4939 cc = s390_emit_compare_and_swap (EQ, res, ac.memsi, cmpv, newv);
4940 if (is_weak)
4941 emit_insn (gen_cstorecc4 (btarget, cc, XEXP (cc, 0), XEXP (cc, 1)));
3093f076 4942 else
3093f076 4943 {
4e1ffb63
RH		 4944 rtx tmp;
4945
78ce265b
RH		 4946 /* Jump to end if we're done (likely?). */
4947 s390_emit_jump (csend, cc);
4948
4e1ffb63
RH		 4949 /* Check for changes outside mode, and loop internal if so.
4950 Arrange the moves so that the compare is adjacent to the
4951 branch so that we can generate CRJ. */
4952 tmp = copy_to_reg (val);
4953 force_expand_binop (SImode, and_optab, res, ac.modemaski, val,
4954 1, OPTAB_DIRECT);
4955 cc = s390_emit_compare (NE, val, tmp);
78ce265b
RH		 4956 s390_emit_jump (csloop, cc);
4957
4958 /* Failed. */
4959 emit_move_insn (btarget, const0_rtx);
4960 emit_label (csend);
3093f076 4961 }
f4aa3848 4962
3093f076 4963 /* Return the correct part of the bitfield. */
78ce265b
RH		 4964 convert_move (vtarget, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
4965 NULL_RTX, 1, OPTAB_DIRECT), 1);
3093f076
AS		 4966}
4967
45d18331 4968/* Expand an atomic operation CODE of mode MODE. MEM is the memory location
ea2c620c 4969 and VAL the value to play with. If AFTER is true then store the value
45d18331
AS		 4970 MEM holds after the operation, if AFTER is false then store the value MEM
4971 holds before the operation. If TARGET is zero then discard that value, else
4972 store it to TARGET. */
4973
4974void
ef4bddc2 4975s390_expand_atomic (machine_mode mode, enum rtx_code code,
45d18331
AS		 4976 rtx target, rtx mem, rtx val, bool after)
4977{
4978 struct alignment_context ac;
4979 rtx cmp;
0a2aaacc 4980 rtx new_rtx = gen_reg_rtx (SImode);
45d18331 4981 rtx orig = gen_reg_rtx (SImode);
19f8b229 4982 rtx_code_label *csloop = gen_label_rtx ();
45d18331
AS		 4983
4984 gcc_assert (!target || register_operand (target, VOIDmode));
4985 gcc_assert (MEM_P (mem));
4986
4987 init_alignment_context (&ac, mem, mode);
4988
4989 /* Shift val to the correct bit positions.
4990 Preserve "icm", but prevent "ex icm". */
4991 if (!(ac.aligned && code == SET && MEM_P (val)))
4992 val = s390_expand_mask_and_shift (val, mode, ac.shift);
4993
4994 /* Further preparation insns. */
4995 if (code == PLUS || code == MINUS)
4996 emit_move_insn (orig, val);
4997 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
4998 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
4999 NULL_RTX, 1, OPTAB_DIRECT);
5000
5001 /* Load full word. Subsequent loads are performed by CS. */
5002 cmp = force_reg (SImode, ac.memsi);
5003
5004 /* Start CS loop. */
5005 emit_label (csloop);
0a2aaacc 5006 emit_move_insn (new_rtx, cmp);
45d18331
AS		 5007
5008 /* Patch new with val at correct position. */
5009 switch (code)
5010 {
5011 case PLUS:
5012 case MINUS:
0a2aaacc 5013 val = expand_simple_binop (SImode, code, new_rtx, orig,
45d18331
AS		 5014 NULL_RTX, 1, OPTAB_DIRECT);
5015 val = expand_simple_binop (SImode, AND, val, ac.modemask,
5016 NULL_RTX, 1, OPTAB_DIRECT);
5017 /* FALLTHRU */
f4aa3848 5018 case SET:
45d18331 5019 if (ac.aligned && MEM_P (val))
44e95206
AH		 5020 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0,
5021 0, 0, SImode, val);
45d18331
AS		 5022 else
5023 {
0a2aaacc 5024 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
45d18331 5025 NULL_RTX, 1, OPTAB_DIRECT);
0a2aaacc 5026 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
45d18331
AS		 5027 NULL_RTX, 1, OPTAB_DIRECT);
5028 }
5029 break;
5030 case AND:
5031 case IOR:
5032 case XOR:
0a2aaacc 5033 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
45d18331
AS		 5034 NULL_RTX, 1, OPTAB_DIRECT);
5035 break;
5036 case MULT: /* NAND */
0a2aaacc 5037 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
45d18331 5038 NULL_RTX, 1, OPTAB_DIRECT);
6a238c58
AK		 5039 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
5040 NULL_RTX, 1, OPTAB_DIRECT);
45d18331
AS		 5041 break;
5042 default:
5043 gcc_unreachable ();
5044 }
45d18331 5045
8bb501bb 5046 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
0a2aaacc 5047 ac.memsi, cmp, new_rtx));
45d18331
AS		 5048
5049 /* Return the correct part of the bitfield. */
5050 if (target)
5051 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
0a2aaacc 5052 after ? new_rtx : cmp, ac.shift,
45d18331
AS		 5053 NULL_RTX, 1, OPTAB_DIRECT), 1);
5054}
5055
fdbe66f2 5056/* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
6b2300b3
JJ		 5057 We need to emit DTP-relative relocations. */
5058
fdbe66f2
EB		 5059static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
5060
5061static void
9c808aad 5062s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
6b2300b3
JJ		 5063{
5064 switch (size)
5065 {
5066 case 4:
5067 fputs ("\t.long\t", file);
5068 break;
5069 case 8:
5070 fputs ("\t.quad\t", file);
5071 break;
5072 default:
8d933e31 5073 gcc_unreachable ();
6b2300b3
JJ		 5074 }
5075 output_addr_const (file, x);
5076 fputs ("@DTPOFF", file);
5077}
5078
7269aee7 5079#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
608063c3 5080/* Implement TARGET_MANGLE_TYPE. */
7269aee7
AH		 5081
5082static const char *
3101faab 5083s390_mangle_type (const_tree type)
7269aee7
AH		 5084{
5085 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
5086 && TARGET_LONG_DOUBLE_128)
5087 return "g";
5088
5089 /* For all other types, use normal C++ mangling. */
5090 return NULL;
5091}
5092#endif
5093
4c8c0dec 5094/* In the name of slightly smaller debug output, and to cater to
aabcd309 5095 general assembler lossage, recognize various UNSPEC sequences
4c8c0dec
JJ		 5096 and turn them back into a direct symbol reference. */
5097
69bd9368 5098static rtx
9c808aad 5099s390_delegitimize_address (rtx orig_x)
4c8c0dec 5100{
e8d8f497 5101 rtx x, y;
4c8c0dec 5102
e8d8f497
JJ		 5103 orig_x = delegitimize_mem_from_attrs (orig_x);
5104 x = orig_x;
e101e12e
AK		 5105
5106 /* Extract the symbol ref from:
5107 (plus:SI (reg:SI 12 %r12)
5108 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
01841ac0
AK		 5109 UNSPEC_GOTOFF/PLTOFF)))
5110 and
5111 (plus:SI (reg:SI 12 %r12)
5112 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
5113 UNSPEC_GOTOFF/PLTOFF)
5114 (const_int 4 [0x4])))) */
e101e12e
AK		 5115 if (GET_CODE (x) == PLUS
5116 && REG_P (XEXP (x, 0))
5117 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
5118 && GET_CODE (XEXP (x, 1)) == CONST)
5119 {
ab081dd6
AK		 5120 HOST_WIDE_INT offset = 0;
5121
e101e12e
AK		 5122 /* The const operand. */
5123 y = XEXP (XEXP (x, 1), 0);
01841ac0
AK		 5124
5125 if (GET_CODE (y) == PLUS
5126 && GET_CODE (XEXP (y, 1)) == CONST_INT)
ab081dd6
AK		 5127 {
5128 offset = INTVAL (XEXP (y, 1));
5129 y = XEXP (y, 0);
5130 }
01841ac0 5131
e101e12e 5132 if (GET_CODE (y) == UNSPEC
01841ac0
AK		 5133 && (XINT (y, 1) == UNSPEC_GOTOFF
5134 || XINT (y, 1) == UNSPEC_PLTOFF))
0a81f074 5135 return plus_constant (Pmode, XVECEXP (y, 0, 0), offset);
e101e12e
AK		 5136 }
5137
4c8c0dec
JJ		 5138 if (GET_CODE (x) != MEM)
5139 return orig_x;
5140
5141 x = XEXP (x, 0);
5142 if (GET_CODE (x) == PLUS
5143 && GET_CODE (XEXP (x, 1)) == CONST
5144 && GET_CODE (XEXP (x, 0)) == REG
5145 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
5146 {
5147 y = XEXP (XEXP (x, 1), 0);
5148 if (GET_CODE (y) == UNSPEC
fd7643fb 5149 && XINT (y, 1) == UNSPEC_GOT)
67a2f76d
JJ		 5150 y = XVECEXP (y, 0, 0);
5151 else
5152 return orig_x;
4c8c0dec 5153 }
67a2f76d 5154 else if (GET_CODE (x) == CONST)
4c8c0dec 5155 {
01841ac0
AK		 5156 /* Extract the symbol ref from:
5157 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
5158 UNSPEC_PLT/GOTENT))) */
5159
4c8c0dec
JJ		 5160 y = XEXP (x, 0);
5161 if (GET_CODE (y) == UNSPEC
01841ac0
AK		 5162 && (XINT (y, 1) == UNSPEC_GOTENT
5163 || XINT (y, 1) == UNSPEC_PLT))
67a2f76d
JJ		 5164 y = XVECEXP (y, 0, 0);
5165 else
5166 return orig_x;
4c8c0dec 5167 }
67a2f76d
JJ		 5168 else
5169 return orig_x;
4c8c0dec 5170
67a2f76d
JJ		 5171 if (GET_MODE (orig_x) != Pmode)
5172 {
2f36e14b
JJ		 5173 if (GET_MODE (orig_x) == BLKmode)
5174 return orig_x;
67a2f76d
JJ		 5175 y = lowpart_subreg (GET_MODE (orig_x), y, Pmode);
5176 if (y == NULL_RTX)
5177 return orig_x;
5178 }
5179 return y;
4c8c0dec 5180}
ba956982 5181
6d057022
AS		 5182/* Output operand OP to stdio stream FILE.
5183 OP is an address (register + offset) which is not used to address data;
5184 instead the rightmost bits are interpreted as the value. */
ac32b25e
UW		 5185
5186static void
5187print_shift_count_operand (FILE *file, rtx op)
5188{
d98ad410
UW		 5189 HOST_WIDE_INT offset;
5190 rtx base;
f83a336d 5191
d98ad410 5192 /* Extract base register and offset. */
4989e88a 5193 if (!s390_decompose_shift_count (op, &base, &offset))
d98ad410 5194 gcc_unreachable ();
ac32b25e
UW		 5195
5196 /* Sanity check. */
d98ad410 5197 if (base)
8d933e31 5198 {
d98ad410
UW		 5199 gcc_assert (GET_CODE (base) == REG);
5200 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
5201 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
8d933e31 5202 }
ac32b25e 5203
6d057022
AS		 5204 /* Offsets are constricted to twelve bits. */
5205 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
d98ad410
UW		 5206 if (base)
5207 fprintf (file, "(%s)", reg_names[REGNO (base)]);
ac32b25e
UW		 5208}
5209
d0de9e13
DV		 5210/* Returns -1 if the function should not be made hotpatchable. Otherwise it
5211 returns a number >= 0 that is the desired size of the hotpatch trampoline
5212 in halfwords. */
5213
5214static int s390_function_num_hotpatch_trampoline_halfwords (tree decl,
5215 bool do_warn)
5216{
5217 tree attr;
5218
5219 if (DECL_DECLARED_INLINE_P (decl)
5220 || DECL_ARTIFICIAL (decl)
5221 || MAIN_NAME_P (DECL_NAME (decl)))
5222 {
5223 /* - Explicitly inlined functions cannot be hotpatched.
5224 - Artificial functions need not be hotpatched.
5225 - Making the main function hotpatchable is useless. */
5226 return -1;
5227 }
5228 attr = lookup_attribute ("hotpatch", DECL_ATTRIBUTES (decl));
5229 if (attr || s390_hotpatch_trampoline_halfwords >= 0)
5230 {
5231 if (lookup_attribute ("always_inline", DECL_ATTRIBUTES (decl)))
5232 {
5233 if (do_warn)
5234 warning (OPT_Wattributes, "function %qE with the %qs attribute"
5235 " is not hotpatchable", DECL_NAME (decl), "always_inline");
5236 return -1;
5237 }
5238 else
5239 {
5240 return (attr) ?
5241 get_hotpatch_attribute (attr) : s390_hotpatch_trampoline_halfwords;
5242 }
5243 }
5244
5245 return -1;
5246}
5247
5248/* Hook to determine if one function can safely inline another. */
5249
5250static bool
5251s390_can_inline_p (tree caller, tree callee)
5252{
5253 if (s390_function_num_hotpatch_trampoline_halfwords (callee, false) >= 0)
5254 return false;
5255
5256 return default_target_can_inline_p (caller, callee);
5257}
5258
5259/* Write the extra assembler code needed to declare a function properly. */
5260
5261void
5262s390_asm_output_function_label (FILE *asm_out_file, const char *fname,
5263 tree decl)
5264{
5265 int hotpatch_trampoline_halfwords = -1;
5266
5267 if (decl)
5268 {
5269 hotpatch_trampoline_halfwords =
5270 s390_function_num_hotpatch_trampoline_halfwords (decl, true);
5271 if (hotpatch_trampoline_halfwords >= 0
5272 && decl_function_context (decl) != NULL_TREE)
5273 {
e697d119
DV		 5274 warning_at (DECL_SOURCE_LOCATION (decl), OPT_mhotpatch,
5275 "hotpatching is not compatible with nested functions");
d0de9e13
DV		 5276 hotpatch_trampoline_halfwords = -1;
5277 }
5278 }
5279
5280 if (hotpatch_trampoline_halfwords > 0)
5281 {
5282 int i;
5283
5284 /* Add a trampoline code area before the function label and initialize it
5285 with two-byte nop instructions. This area can be overwritten with code
5286 that jumps to a patched version of the function. */
5287 for (i = 0; i < hotpatch_trampoline_halfwords; i++)
5288 asm_fprintf (asm_out_file, "\tnopr\t%%r7\n");
5289 /* Note: The function label must be aligned so that (a) the bytes of the
5290 following nop do not cross a cacheline boundary, and (b) a jump address
5291 (eight bytes for 64 bit targets, 4 bytes for 32 bit targets) can be
5292 stored directly before the label without crossing a cacheline
5293 boundary. All this is necessary to make sure the trampoline code can
5294 be changed atomically. */
5295 }
5296
5297 ASM_OUTPUT_LABEL (asm_out_file, fname);
5298
5299 /* Output a four-byte nop if hotpatching is enabled. This can be overwritten
5300 atomically with a relative backwards jump to the trampoline area. */
5301 if (hotpatch_trampoline_halfwords >= 0)
5302 asm_fprintf (asm_out_file, "\tnop\t0\n");
5303}
5304
38899e29 5305/* Output machine-dependent UNSPECs occurring in address constant X
faeb9bb6
UW		 5306 in assembler syntax to stdio stream FILE. Returns true if the
5307 constant X could be recognized, false otherwise. */
9db1d521 5308
0f8ab434 5309static bool
faeb9bb6 5310s390_output_addr_const_extra (FILE *file, rtx x)
9db1d521 5311{
faeb9bb6
UW		 5312 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
5313 switch (XINT (x, 1))
5314 {
5315 case UNSPEC_GOTENT:
5316 output_addr_const (file, XVECEXP (x, 0, 0));
5317 fprintf (file, "@GOTENT");
5318 return true;
5319 case UNSPEC_GOT:
5320 output_addr_const (file, XVECEXP (x, 0, 0));
5321 fprintf (file, "@GOT");
5322 return true;
5323 case UNSPEC_GOTOFF:
5324 output_addr_const (file, XVECEXP (x, 0, 0));
5325 fprintf (file, "@GOTOFF");
5326 return true;
5327 case UNSPEC_PLT:
5328 output_addr_const (file, XVECEXP (x, 0, 0));
5329 fprintf (file, "@PLT");
5330 return true;
5331 case UNSPEC_PLTOFF:
5332 output_addr_const (file, XVECEXP (x, 0, 0));
5333 fprintf (file, "@PLTOFF");
5334 return true;
5335 case UNSPEC_TLSGD:
5336 output_addr_const (file, XVECEXP (x, 0, 0));
5337 fprintf (file, "@TLSGD");
5338 return true;
5339 case UNSPEC_TLSLDM:
5340 assemble_name (file, get_some_local_dynamic_name ());
5341 fprintf (file, "@TLSLDM");
5342 return true;
5343 case UNSPEC_DTPOFF:
5344 output_addr_const (file, XVECEXP (x, 0, 0));
5345 fprintf (file, "@DTPOFF");
5346 return true;
5347 case UNSPEC_NTPOFF:
5348 output_addr_const (file, XVECEXP (x, 0, 0));
5349 fprintf (file, "@NTPOFF");
5350 return true;
5351 case UNSPEC_GOTNTPOFF:
5352 output_addr_const (file, XVECEXP (x, 0, 0));
5353 fprintf (file, "@GOTNTPOFF");
5354 return true;
5355 case UNSPEC_INDNTPOFF:
5356 output_addr_const (file, XVECEXP (x, 0, 0));
5357 fprintf (file, "@INDNTPOFF");
5358 return true;
5359 }
9db1d521 5360
dc66391d
RS		 5361 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5362 switch (XINT (x, 1))
5363 {
5364 case UNSPEC_POOL_OFFSET:
5365 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5366 output_addr_const (file, x);
5367 return true;
5368 }
faeb9bb6 5369 return false;
9db1d521
HP		 5370}
5371
c7453384 5372/* Output address operand ADDR in assembler syntax to
994fe660 5373 stdio stream FILE. */
9db1d521
HP		 5374
5375void
9c808aad 5376print_operand_address (FILE *file, rtx addr)
9db1d521
HP		 5377{
5378 struct s390_address ad;
5379
0ff4390d 5380 if (s390_loadrelative_operand_p (addr, NULL, NULL))
963fc8d0 5381 {
8395b41e
AK		 5382 if (!TARGET_Z10)
5383 {
3f3c098d
AK		 5384 output_operand_lossage ("symbolic memory references are "
5385 "only supported on z10 or later");
8395b41e
AK		 5386 return;
5387 }
963fc8d0
AK		 5388 output_addr_const (file, addr);
5389 return;
5390 }
5391
b808c04c 5392 if (!s390_decompose_address (addr, &ad)
93fa8428
AK		 5393 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5394 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
c85ce869 5395 output_operand_lossage ("cannot decompose address");
c7453384 5396
9db1d521 5397 if (ad.disp)
faeb9bb6 5398 output_addr_const (file, ad.disp);
9db1d521
HP		 5399 else
5400 fprintf (file, "0");
5401
5402 if (ad.base && ad.indx)
5403 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5404 reg_names[REGNO (ad.base)]);
5405 else if (ad.base)
5406 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5407}
5408
c7453384
EC		 5409/* Output operand X in assembler syntax to stdio stream FILE.
5410 CODE specified the format flag. The following format flags
994fe660
UW		 5411 are recognized:
5412
5413 'C': print opcode suffix for branch condition.
5414 'D': print opcode suffix for inverse branch condition.
f1149235 5415 'E': print opcode suffix for branch on index instruction.
7b8acc34 5416 'G': print the size of the operand in bytes.
75ca1b39
RH		 5417 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5418 'M': print the second word of a TImode operand.
5419 'N': print the second word of a DImode operand.
994fe660
UW		 5420 'O': print only the displacement of a memory reference.
5421 'R': print only the base register of a memory reference.
fc0ea003 5422 'S': print S-type memory reference (base+displacement).
ac32b25e 5423 'Y': print shift count operand.
994fe660 5424
5519a4f9 5425 'b': print integer X as if it's an unsigned byte.
963fc8d0 5426 'c': print integer X as if it's an signed byte.
75ca1b39
RH		 5427 'e': "end" of DImode contiguous bitmask X.
5428 'f': "end" of SImode contiguous bitmask X.
da48f5ec 5429 'h': print integer X as if it's a signed halfword.
f19a9af7 5430 'i': print the first nonzero HImode part of X.
da48f5ec
AK		 5431 'j': print the first HImode part unequal to -1 of X.
5432 'k': print the first nonzero SImode part of X.
5433 'm': print the first SImode part unequal to -1 of X.
75ca1b39
RH		 5434 'o': print integer X as if it's an unsigned 32bit word.
5435 's': "start" of DImode contiguous bitmask X.
5436 't': "start" of SImode contiguous bitmask X.
5437 'x': print integer X as if it's an unsigned halfword.
5438*/
9db1d521
HP		 5439
5440void
9c808aad 5441print_operand (FILE *file, rtx x, int code)
9db1d521 5442{
75ca1b39
RH		 5443 HOST_WIDE_INT ival;
5444
9db1d521
HP		 5445 switch (code)
5446 {
5447 case 'C':
ba956982 5448 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
9db1d521
HP		 5449 return;
5450
5451 case 'D':
ba956982 5452 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
9db1d521
HP		 5453 return;
5454
f1149235
AK		 5455 case 'E':
5456 if (GET_CODE (x) == LE)
5457 fprintf (file, "l");
5458 else if (GET_CODE (x) == GT)
5459 fprintf (file, "h");
5460 else
3f3c098d
AK		 5461 output_operand_lossage ("invalid comparison operator "
5462 "for 'E' output modifier");
f1149235
AK		 5463 return;
5464
fd3cd001
UW		 5465 case 'J':
5466 if (GET_CODE (x) == SYMBOL_REF)
5467 {
5468 fprintf (file, "%s", ":tls_load:");
5469 output_addr_const (file, x);
5470 }
5471 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5472 {
5473 fprintf (file, "%s", ":tls_gdcall:");
5474 output_addr_const (file, XVECEXP (x, 0, 0));
5475 }
5476 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5477 {
5478 fprintf (file, "%s", ":tls_ldcall:");
4fbca4ba
RS		 5479 const char *name = get_some_local_dynamic_name ();
5480 gcc_assert (name);
5481 assemble_name (file, name);
fd3cd001
UW		 5482 }
5483 else
3f3c098d 5484 output_operand_lossage ("invalid reference for 'J' output modifier");
fd3cd001
UW		 5485 return;
5486
7b8acc34
AK		 5487 case 'G':
5488 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5489 return;
5490
9db1d521
HP		 5491 case 'O':
5492 {
5493 struct s390_address ad;
8d933e31 5494 int ret;
9db1d521 5495
8395b41e
AK		 5496 if (!MEM_P (x))
5497 {
3f3c098d
AK		 5498 output_operand_lossage ("memory reference expected for "
5499 "'O' output modifier");
8395b41e
AK		 5500 return;
5501 }
5502
8d933e31 5503 ret = s390_decompose_address (XEXP (x, 0), &ad);
8395b41e
AK		 5504
5505 if (!ret
5506 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5507 || ad.indx)
5508 {
3f3c098d 5509 output_operand_lossage ("invalid address for 'O' output modifier");
8395b41e
AK		 5510 return;
5511 }
9db1d521
HP		 5512
5513 if (ad.disp)
faeb9bb6 5514 output_addr_const (file, ad.disp);
9db1d521
HP		 5515 else
5516 fprintf (file, "0");
5517 }
5518 return;
5519
5520 case 'R':
5521 {
5522 struct s390_address ad;
8d933e31 5523 int ret;
9db1d521 5524
8395b41e
AK		 5525 if (!MEM_P (x))
5526 {
3f3c098d
AK		 5527 output_operand_lossage ("memory reference expected for "
5528 "'R' output modifier");
8395b41e
AK		 5529 return;
5530 }
5531
8d933e31 5532 ret = s390_decompose_address (XEXP (x, 0), &ad);
8395b41e
AK		 5533
5534 if (!ret
5535 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5536 || ad.indx)
5537 {
3f3c098d 5538 output_operand_lossage ("invalid address for 'R' output modifier");
8395b41e
AK		 5539 return;
5540 }
9db1d521
HP		 5541
5542 if (ad.base)
5543 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5544 else
5545 fprintf (file, "0");
5546 }
5547 return;
5548
fc0ea003
UW		 5549 case 'S':
5550 {
5551 struct s390_address ad;
8d933e31 5552 int ret;
fc0ea003 5553
8395b41e
AK		 5554 if (!MEM_P (x))
5555 {
3f3c098d
AK		 5556 output_operand_lossage ("memory reference expected for "
5557 "'S' output modifier");
8395b41e
AK		 5558 return;
5559 }
8d933e31 5560 ret = s390_decompose_address (XEXP (x, 0), &ad);
8395b41e
AK		 5561
5562 if (!ret
5563 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5564 || ad.indx)
5565 {
3f3c098d 5566 output_operand_lossage ("invalid address for 'S' output modifier");
8395b41e
AK		 5567 return;
5568 }
fc0ea003
UW		 5569
5570 if (ad.disp)
5571 output_addr_const (file, ad.disp);
5572 else
5573 fprintf (file, "0");
5574
5575 if (ad.base)
5576 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5577 }
5578 return;
5579
9db1d521
HP		 5580 case 'N':
5581 if (GET_CODE (x) == REG)
5582 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5583 else if (GET_CODE (x) == MEM)
0a81f074
RS		 5584 x = change_address (x, VOIDmode,
5585 plus_constant (Pmode, XEXP (x, 0), 4));
9db1d521 5586 else
3f3c098d
AK		 5587 output_operand_lossage ("register or memory expression expected "
5588 "for 'N' output modifier");
9db1d521
HP		 5589 break;
5590
5591 case 'M':
5592 if (GET_CODE (x) == REG)
5593 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5594 else if (GET_CODE (x) == MEM)
0a81f074
RS		 5595 x = change_address (x, VOIDmode,
5596 plus_constant (Pmode, XEXP (x, 0), 8));
9db1d521 5597 else
3f3c098d
AK		 5598 output_operand_lossage ("register or memory expression expected "
5599 "for 'M' output modifier");
9db1d521 5600 break;
ac32b25e
UW		 5601
5602 case 'Y':
5603 print_shift_count_operand (file, x);
5604 return;
9db1d521
HP		 5605 }
5606
5607 switch (GET_CODE (x))
5608 {
5609 case REG:
5610 fprintf (file, "%s", reg_names[REGNO (x)]);
5611 break;
5612
5613 case MEM:
5614 output_address (XEXP (x, 0));
5615 break;
5616
5617 case CONST:
5618 case CODE_LABEL:
5619 case LABEL_REF:
5620 case SYMBOL_REF:
faeb9bb6 5621 output_addr_const (file, x);
9db1d521
HP		 5622 break;
5623
5624 case CONST_INT:
75ca1b39
RH		 5625 ival = INTVAL (x);
5626 switch (code)
5627 {
5628 case 0:
5629 break;
5630 case 'b':
5631 ival &= 0xff;
5632 break;
5633 case 'c':
5634 ival = ((ival & 0xff) ^ 0x80) - 0x80;
5635 break;
5636 case 'x':
5637 ival &= 0xffff;
5638 break;
5639 case 'h':
5640 ival = ((ival & 0xffff) ^ 0x8000) - 0x8000;
5641 break;
5642 case 'i':
5643 ival = s390_extract_part (x, HImode, 0);
5644 break;
5645 case 'j':
5646 ival = s390_extract_part (x, HImode, -1);
5647 break;
5648 case 'k':
5649 ival = s390_extract_part (x, SImode, 0);
5650 break;
5651 case 'm':
5652 ival = s390_extract_part (x, SImode, -1);
5653 break;
5654 case 'o':
5655 ival &= 0xffffffff;
5656 break;
5657 case 'e': case 'f':
5658 case 's': case 't':
5659 {
5660 int pos, len;
5661 bool ok;
5662
5663 len = (code == 's' || code == 'e' ? 64 : 32);
5664 ok = s390_contiguous_bitmask_p (ival, len, &pos, &len);
5665 gcc_assert (ok);
5666 if (code == 's' || code == 't')
5667 ival = 64 - pos - len;
5668 else
5669 ival = 64 - 1 - pos;
5670 }
5671 break;
5672 default:
5673 output_operand_lossage ("invalid constant for output modifier '%c'", code);
5674 }
5675 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
4023fb28
UW		 5676 break;
5677
5678 case CONST_DOUBLE:
8d933e31 5679 gcc_assert (GET_MODE (x) == VOIDmode);
4023fb28
UW		 5680 if (code == 'b')
5681 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
9db1d521 5682 else if (code == 'x')
4023fb28 5683 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
9db1d521 5684 else if (code == 'h')
3f3c098d
AK		 5685 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5686 ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
9db1d521 5687 else
8395b41e
AK		 5688 {
5689 if (code == 0)
3f3c098d
AK		 5690 output_operand_lossage ("invalid constant - try using "
5691 "an output modifier");
8395b41e 5692 else
3f3c098d
AK		 5693 output_operand_lossage ("invalid constant for output modifier '%c'",
5694 code);
8395b41e 5695 }
9db1d521
HP		 5696 break;
5697
5698 default:
8395b41e 5699 if (code == 0)
3f3c098d
AK		 5700 output_operand_lossage ("invalid expression - try using "
5701 "an output modifier");
8395b41e 5702 else
3f3c098d
AK		 5703 output_operand_lossage ("invalid expression for output "
5704 "modifier '%c'", code);
9db1d521
HP		 5705 break;
5706 }
5707}
5708
301d03af
RS		 5709/* Target hook for assembling integer objects. We need to define it
5710 here to work a round a bug in some versions of GAS, which couldn't
5711 handle values smaller than INT_MIN when printed in decimal. */
5712
5713static bool
9c808aad 5714s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
301d03af
RS		 5715{
5716 if (size == 8 && aligned_p
5717 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5718 {
4a0a75dd
KG		 5719 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5720 INTVAL (x));
301d03af
RS		 5721 return true;
5722 }
5723 return default_assemble_integer (x, size, aligned_p);
5724}
5725
c7453384 5726/* Returns true if register REGNO is used for forming
994fe660 5727 a memory address in expression X. */
9db1d521 5728
3ed99cc9 5729static bool
9c808aad 5730reg_used_in_mem_p (int regno, rtx x)
9db1d521
HP		 5731{
5732 enum rtx_code code = GET_CODE (x);
5733 int i, j;
5734 const char *fmt;
c7453384 5735
9db1d521
HP		 5736 if (code == MEM)
5737 {
5738 if (refers_to_regno_p (regno, regno+1,
5739 XEXP (x, 0), 0))
3ed99cc9 5740 return true;
9db1d521 5741 }
c7453384 5742 else if (code == SET
4023fb28
UW		 5743 && GET_CODE (SET_DEST (x)) == PC)
5744 {
5745 if (refers_to_regno_p (regno, regno+1,
5746 SET_SRC (x), 0))
3ed99cc9 5747 return true;
4023fb28 5748 }
9db1d521
HP		 5749
5750 fmt = GET_RTX_FORMAT (code);
5751 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5752 {
5753 if (fmt[i] == 'e'
5754 && reg_used_in_mem_p (regno, XEXP (x, i)))
3ed99cc9 5755 return true;
c7453384 5756
9db1d521
HP		 5757 else if (fmt[i] == 'E')
5758 for (j = 0; j < XVECLEN (x, i); j++)
5759 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
3ed99cc9 5760 return true;
9db1d521 5761 }
3ed99cc9 5762 return false;
9db1d521
HP		 5763}
5764
d65f7478 5765/* Returns true if expression DEP_RTX sets an address register
994fe660 5766 used by instruction INSN to address memory. */
9db1d521 5767
3ed99cc9 5768static bool
647d790d 5769addr_generation_dependency_p (rtx dep_rtx, rtx_insn *insn)
9db1d521 5770{
4023fb28 5771 rtx target, pat;
9db1d521 5772
b64925dc 5773 if (NONJUMP_INSN_P (dep_rtx))
34f0d87a 5774 dep_rtx = PATTERN (dep_rtx);
077dab3b 5775
9db1d521
HP		 5776 if (GET_CODE (dep_rtx) == SET)
5777 {
5778 target = SET_DEST (dep_rtx);
cc7ab9b7
UW		 5779 if (GET_CODE (target) == STRICT_LOW_PART)
5780 target = XEXP (target, 0);
5781 while (GET_CODE (target) == SUBREG)
5782 target = SUBREG_REG (target);
5783
9db1d521
HP		 5784 if (GET_CODE (target) == REG)
5785 {
5786 int regno = REGNO (target);
5787
077dab3b 5788 if (s390_safe_attr_type (insn) == TYPE_LA)
4023fb28
UW		 5789 {
5790 pat = PATTERN (insn);
5791 if (GET_CODE (pat) == PARALLEL)
5792 {
8d933e31 5793 gcc_assert (XVECLEN (pat, 0) == 2);
4023fb28
UW		 5794 pat = XVECEXP (pat, 0, 0);
5795 }
8d933e31
AS		 5796 gcc_assert (GET_CODE (pat) == SET);
5797 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
4023fb28 5798 }
077dab3b 5799 else if (get_attr_atype (insn) == ATYPE_AGEN)
4023fb28
UW		 5800 return reg_used_in_mem_p (regno, PATTERN (insn));
5801 }
9db1d521 5802 }
3ed99cc9 5803 return false;
9db1d521
HP		 5804}
5805
077dab3b
HP		 5806/* Return 1, if dep_insn sets register used in insn in the agen unit. */
5807
c7453384 5808int
647d790d 5809s390_agen_dep_p (rtx_insn *dep_insn, rtx_insn *insn)
c7453384 5810{
077dab3b
HP		 5811 rtx dep_rtx = PATTERN (dep_insn);
5812 int i;
c7453384
EC		 5813
5814 if (GET_CODE (dep_rtx) == SET
077dab3b
HP		 5815 && addr_generation_dependency_p (dep_rtx, insn))
5816 return 1;
5817 else if (GET_CODE (dep_rtx) == PARALLEL)
5818 {
5819 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5820 {
5821 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5822 return 1;
5823 }
5824 }
5825 return 0;
5826}
5827
9381e3f1 5828
52609473
HP		 5829/* A C statement (sans semicolon) to update the integer scheduling priority
5830 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5831 reduce the priority to execute INSN later. Do not define this macro if
c7453384 5832 you do not need to adjust the scheduling priorities of insns.
52609473 5833
c7453384 5834 A STD instruction should be scheduled earlier,
52609473 5835 in order to use the bypass. */
52609473 5836static int
ac44248e 5837s390_adjust_priority (rtx_insn *insn, int priority)
52609473
HP		 5838{
5839 if (! INSN_P (insn))
5840 return priority;
5841
ec24698e 5842 if (s390_tune != PROCESSOR_2084_Z990
2cdece44 5843 && s390_tune != PROCESSOR_2094_Z9_109
65b1d8ea 5844 && s390_tune != PROCESSOR_2097_Z10
22ac2c2f
AK		 5845 && s390_tune != PROCESSOR_2817_Z196
5846 && s390_tune != PROCESSOR_2827_ZEC12)
52609473
HP		 5847 return priority;
5848
5849 switch (s390_safe_attr_type (insn))
5850 {
cfdb984b
AS		 5851 case TYPE_FSTOREDF:
5852 case TYPE_FSTORESF:
52609473
HP		 5853 priority = priority << 3;
5854 break;
5855 case TYPE_STORE:
ea77e738 5856 case TYPE_STM:
52609473
HP		 5857 priority = priority << 1;
5858 break;
5859 default:
5860 break;
5861 }
5862 return priority;
5863}
f2d3c02a 5864
2cdece44 5865
077dab3b 5866/* The number of instructions that can be issued per cycle. */
f2d3c02a 5867
077dab3b 5868static int
9c808aad 5869s390_issue_rate (void)
077dab3b 5870{
93538e8e
AK		 5871 switch (s390_tune)
5872 {
5873 case PROCESSOR_2084_Z990:
5874 case PROCESSOR_2094_Z9_109:
65b1d8ea 5875 case PROCESSOR_2817_Z196:
93538e8e
AK		 5876 return 3;
5877 case PROCESSOR_2097_Z10:
22ac2c2f 5878 case PROCESSOR_2827_ZEC12:
93538e8e
AK		 5879 return 2;
5880 default:
5881 return 1;
5882 }
077dab3b 5883}
f2d3c02a 5884
52609473 5885static int
9c808aad 5886s390_first_cycle_multipass_dfa_lookahead (void)
52609473 5887{
64e1e4c4 5888 return 4;
52609473
HP		 5889}
5890
585539a1
UW		 5891/* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5892 Fix up MEMs as required. */
5893
5894static void
5895annotate_constant_pool_refs (rtx *x)
5896{
5897 int i, j;
5898 const char *fmt;
5899
8d933e31
AS		 5900 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5901 || !CONSTANT_POOL_ADDRESS_P (*x));
585539a1
UW		 5902
5903 /* Literal pool references can only occur inside a MEM ... */
5904 if (GET_CODE (*x) == MEM)
5905 {
5906 rtx memref = XEXP (*x, 0);
5907
5908 if (GET_CODE (memref) == SYMBOL_REF
5909 && CONSTANT_POOL_ADDRESS_P (memref))
5910 {
5911 rtx base = cfun->machine->base_reg;
5912 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5913 UNSPEC_LTREF);
5914
5915 *x = replace_equiv_address (*x, addr);
5916 return;
5917 }
5918
5919 if (GET_CODE (memref) == CONST
5920 && GET_CODE (XEXP (memref, 0)) == PLUS
5921 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5922 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5923 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5924 {
5925 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5926 rtx sym = XEXP (XEXP (memref, 0), 0);
5927 rtx base = cfun->machine->base_reg;
5928 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5929 UNSPEC_LTREF);
5930
0a81f074 5931 *x = replace_equiv_address (*x, plus_constant (Pmode, addr, off));
585539a1
UW		 5932 return;
5933 }
5934 }
5935
5936 /* ... or a load-address type pattern. */
5937 if (GET_CODE (*x) == SET)
5938 {
5939 rtx addrref = SET_SRC (*x);
5940
5941 if (GET_CODE (addrref) == SYMBOL_REF
5942 && CONSTANT_POOL_ADDRESS_P (addrref))
5943 {
5944 rtx base = cfun->machine->base_reg;
5945 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5946 UNSPEC_LTREF);
5947
5948 SET_SRC (*x) = addr;
5949 return;
5950 }
5951
5952 if (GET_CODE (addrref) == CONST
5953 && GET_CODE (XEXP (addrref, 0)) == PLUS
5954 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5955 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5956 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
5957 {
5958 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
5959 rtx sym = XEXP (XEXP (addrref, 0), 0);
5960 rtx base = cfun->machine->base_reg;
5961 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5962 UNSPEC_LTREF);
5963
0a81f074 5964 SET_SRC (*x) = plus_constant (Pmode, addr, off);
585539a1
UW		 5965 return;
5966 }
5967 }
5968
5969 /* Annotate LTREL_BASE as well. */
5970 if (GET_CODE (*x) == UNSPEC
5971 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
5972 {
5973 rtx base = cfun->machine->base_reg;
5974 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
5975 UNSPEC_LTREL_BASE);
5976 return;
5977 }
5978
5979 fmt = GET_RTX_FORMAT (GET_CODE (*x));
5980 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
5981 {
5982 if (fmt[i] == 'e')
5983 {
5984 annotate_constant_pool_refs (&XEXP (*x, i));
5985 }
5986 else if (fmt[i] == 'E')
5987 {
5988 for (j = 0; j < XVECLEN (*x, i); j++)
5989 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
5990 }
5991 }
5992}
5993
ab96de7e
AS		 5994/* Split all branches that exceed the maximum distance.
5995 Returns true if this created a new literal pool entry. */
5996
5997static int
5998s390_split_branches (void)
5999{
6000 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8d933e31 6001 int new_literal = 0, ret;
775c43d3 6002 rtx_insn *insn;
17f385d8 6003 rtx pat, target;
ab96de7e
AS		 6004 rtx *label;
6005
6006 /* We need correct insn addresses. */
6007
6008 shorten_branches (get_insns ());
6009
6010 /* Find all branches that exceed 64KB, and split them. */
6011
6012 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6013 {
966f97ac 6014 if (! JUMP_P (insn) || tablejump_p (insn, NULL, NULL))
ab96de7e
AS		 6015 continue;
6016
6017 pat = PATTERN (insn);
966f97ac 6018 if (GET_CODE (pat) == PARALLEL)
ab96de7e
AS		 6019 pat = XVECEXP (pat, 0, 0);
6020 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
6021 continue;
6022
6023 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
6024 {
6025 label = &SET_SRC (pat);
6026 }
6027 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
6028 {
6029 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
6030 label = &XEXP (SET_SRC (pat), 1);
6031 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
6032 label = &XEXP (SET_SRC (pat), 2);
6033 else
6034 continue;
6035 }
6036 else
6037 continue;
6038
6039 if (get_attr_length (insn) <= 4)
6040 continue;
6041
e2df5c1d
UW		 6042 /* We are going to use the return register as scratch register,
6043 make sure it will be saved/restored by the prologue/epilogue. */
6044 cfun_frame_layout.save_return_addr_p = 1;
6045
ab96de7e
AS		 6046 if (!flag_pic)
6047 {
6048 new_literal = 1;
17f385d8
DM		 6049 rtx mem = force_const_mem (Pmode, *label);
6050 rtx_insn *set_insn = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, mem), insn);
6051 INSN_ADDRESSES_NEW (set_insn, -1);
6052 annotate_constant_pool_refs (&PATTERN (set_insn));
ab96de7e
AS		 6053
6054 target = temp_reg;
6055 }
6056 else
6057 {
6058 new_literal = 1;
6059 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
6060 UNSPEC_LTREL_OFFSET);
6061 target = gen_rtx_CONST (Pmode, target);
6062 target = force_const_mem (Pmode, target);
17f385d8
DM		 6063 rtx_insn *set_insn = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
6064 INSN_ADDRESSES_NEW (set_insn, -1);
6065 annotate_constant_pool_refs (&PATTERN (set_insn));
ab96de7e
AS		 6066
6067 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
6068 cfun->machine->base_reg),
6069 UNSPEC_LTREL_BASE);
6070 target = gen_rtx_PLUS (Pmode, temp_reg, target);
6071 }
6072
8d933e31
AS		 6073 ret = validate_change (insn, label, target, 0);
6074 gcc_assert (ret);
ab96de7e
AS		 6075 }
6076
6077 return new_literal;
6078}
6079
b2ccb744 6080
f4aa3848
AK		 6081/* Find an annotated literal pool symbol referenced in RTX X,
6082 and store it at REF. Will abort if X contains references to
585539a1
UW		 6083 more than one such pool symbol; multiple references to the same
6084 symbol are allowed, however.
b2ccb744 6085
c7453384 6086 The rtx pointed to by REF must be initialized to NULL_RTX
b2ccb744
UW		 6087 by the caller before calling this routine. */
6088
6089static void
9c808aad 6090find_constant_pool_ref (rtx x, rtx *ref)
b2ccb744
UW		 6091{
6092 int i, j;
6093 const char *fmt;
6094
fd7643fb
UW		 6095 /* Ignore LTREL_BASE references. */
6096 if (GET_CODE (x) == UNSPEC
6097 && XINT (x, 1) == UNSPEC_LTREL_BASE)
6098 return;
5af2f3d3
UW		 6099 /* Likewise POOL_ENTRY insns. */
6100 if (GET_CODE (x) == UNSPEC_VOLATILE
6101 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
6102 return;
fd7643fb 6103
8d933e31
AS		 6104 gcc_assert (GET_CODE (x) != SYMBOL_REF
6105 || !CONSTANT_POOL_ADDRESS_P (x));
585539a1
UW		 6106
6107 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
b2ccb744 6108 {
585539a1 6109 rtx sym = XVECEXP (x, 0, 0);
8d933e31
AS		 6110 gcc_assert (GET_CODE (sym) == SYMBOL_REF
6111 && CONSTANT_POOL_ADDRESS_P (sym));
585539a1 6112
b2ccb744 6113 if (*ref == NULL_RTX)
585539a1 6114 *ref = sym;
f4aa3848 6115 else
8d933e31 6116 gcc_assert (*ref == sym);
585539a1
UW		 6117
6118 return;
b2ccb744
UW		 6119 }
6120
6121 fmt = GET_RTX_FORMAT (GET_CODE (x));
6122 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6123 {
6124 if (fmt[i] == 'e')
6125 {
6126 find_constant_pool_ref (XEXP (x, i), ref);
6127 }
6128 else if (fmt[i] == 'E')
6129 {
6130 for (j = 0; j < XVECLEN (x, i); j++)
6131 find_constant_pool_ref (XVECEXP (x, i, j), ref);
6132 }
6133 }
6134}
6135
f4aa3848 6136/* Replace every reference to the annotated literal pool
585539a1 6137 symbol REF in X by its base plus OFFSET. */
b2ccb744
UW		 6138
6139static void
585539a1 6140replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
b2ccb744
UW		 6141{
6142 int i, j;
6143 const char *fmt;
6144
8d933e31 6145 gcc_assert (*x != ref);
b2ccb744 6146
585539a1
UW		 6147 if (GET_CODE (*x) == UNSPEC
6148 && XINT (*x, 1) == UNSPEC_LTREF
6149 && XVECEXP (*x, 0, 0) == ref)
b2ccb744 6150 {
585539a1
UW		 6151 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
6152 return;
b2ccb744
UW		 6153 }
6154
585539a1
UW		 6155 if (GET_CODE (*x) == PLUS
6156 && GET_CODE (XEXP (*x, 1)) == CONST_INT
6157 && GET_CODE (XEXP (*x, 0)) == UNSPEC
6158 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
6159 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
b2ccb744 6160 {
585539a1 6161 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
0a81f074 6162 *x = plus_constant (Pmode, addr, INTVAL (XEXP (*x, 1)));
585539a1 6163 return;
b2ccb744
UW		 6164 }
6165
6166 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6167 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6168 {
6169 if (fmt[i] == 'e')
6170 {
585539a1 6171 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
b2ccb744
UW		 6172 }
6173 else if (fmt[i] == 'E')
6174 {
6175 for (j = 0; j < XVECLEN (*x, i); j++)
585539a1 6176 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
b2ccb744
UW		 6177 }
6178 }
6179}
6180
c7453384 6181/* Check whether X contains an UNSPEC_LTREL_BASE.
fd7643fb 6182 Return its constant pool symbol if found, NULL_RTX otherwise. */
aee4e0db 6183
fd7643fb 6184static rtx
9c808aad 6185find_ltrel_base (rtx x)
aee4e0db 6186{
aee4e0db
UW		 6187 int i, j;
6188 const char *fmt;
6189
fd7643fb
UW		 6190 if (GET_CODE (x) == UNSPEC
6191 && XINT (x, 1) == UNSPEC_LTREL_BASE)
6192 return XVECEXP (x, 0, 0);
aee4e0db
UW		 6193
6194 fmt = GET_RTX_FORMAT (GET_CODE (x));
6195 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6196 {
6197 if (fmt[i] == 'e')
6198 {
fd7643fb
UW		 6199 rtx fnd = find_ltrel_base (XEXP (x, i));
6200 if (fnd)
6201 return fnd;
aee4e0db
UW		 6202 }
6203 else if (fmt[i] == 'E')
6204 {
6205 for (j = 0; j < XVECLEN (x, i); j++)
fd7643fb
UW		 6206 {
6207 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
6208 if (fnd)
6209 return fnd;
6210 }
aee4e0db
UW		 6211 }
6212 }
6213
fd7643fb 6214 return NULL_RTX;
aee4e0db
UW		 6215}
6216
585539a1 6217/* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
aee4e0db
UW		 6218
6219static void
585539a1 6220replace_ltrel_base (rtx *x)
aee4e0db 6221{
fd7643fb 6222 int i, j;
aee4e0db
UW		 6223 const char *fmt;
6224
fd7643fb
UW		 6225 if (GET_CODE (*x) == UNSPEC
6226 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
aee4e0db 6227 {
585539a1 6228 *x = XVECEXP (*x, 0, 1);
fd7643fb 6229 return;
aee4e0db
UW		 6230 }
6231
6232 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6233 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6234 {
6235 if (fmt[i] == 'e')
6236 {
585539a1 6237 replace_ltrel_base (&XEXP (*x, i));
aee4e0db
UW		 6238 }
6239 else if (fmt[i] == 'E')
6240 {
6241 for (j = 0; j < XVECLEN (*x, i); j++)
585539a1 6242 replace_ltrel_base (&XVECEXP (*x, i, j));
aee4e0db
UW		 6243 }
6244 }
6245}
6246
6247
fd7643fb 6248/* We keep a list of constants which we have to add to internal
b2ccb744
UW		 6249 constant tables in the middle of large functions. */
6250
4dc19cc0 6251#define NR_C_MODES 11
ef4bddc2 6252machine_mode constant_modes[NR_C_MODES] =
b2ccb744 6253{
4dc19cc0
AK		 6254 TFmode, TImode, TDmode,
6255 DFmode, DImode, DDmode,
6256 SFmode, SImode, SDmode,
b2ccb744
UW		 6257 HImode,
6258 QImode
6259};
6260
b2ccb744
UW		 6261struct constant
6262{
6263 struct constant *next;
6264 rtx value;
775c43d3 6265 rtx_code_label *label;
b2ccb744
UW		 6266};
6267
6268struct constant_pool
6269{
6270 struct constant_pool *next;
775c43d3
DM		 6271 rtx_insn *first_insn;
6272 rtx_insn *pool_insn;
aee4e0db 6273 bitmap insns;
775c43d3 6274 rtx_insn *emit_pool_after;
b2ccb744
UW		 6275
6276 struct constant *constants[NR_C_MODES];
9bb86f41 6277 struct constant *execute;
775c43d3 6278 rtx_code_label *label;
b2ccb744
UW		 6279 int size;
6280};
6281
ab96de7e
AS		 6282/* Allocate new constant_pool structure. */
6283
6284static struct constant_pool *
6285s390_alloc_pool (void)
6286{
6287 struct constant_pool *pool;
6288 int i;
6289
6290 pool = (struct constant_pool *) xmalloc (sizeof *pool);
6291 pool->next = NULL;
6292 for (i = 0; i < NR_C_MODES; i++)
6293 pool->constants[i] = NULL;
6294
6295 pool->execute = NULL;
6296 pool->label = gen_label_rtx ();
775c43d3
DM		 6297 pool->first_insn = NULL;
6298 pool->pool_insn = NULL;
ab96de7e
AS		 6299 pool->insns = BITMAP_ALLOC (NULL);
6300 pool->size = 0;
775c43d3 6301 pool->emit_pool_after = NULL;
ab96de7e
AS		 6302
6303 return pool;
6304}
b2ccb744
UW		 6305
6306/* Create new constant pool covering instructions starting at INSN
6307 and chain it to the end of POOL_LIST. */
6308
6309static struct constant_pool *
775c43d3 6310s390_start_pool (struct constant_pool **pool_list, rtx_insn *insn)
b2ccb744
UW		 6311{
6312 struct constant_pool *pool, **prev;
b2ccb744 6313
5af2f3d3 6314 pool = s390_alloc_pool ();
b2ccb744 6315 pool->first_insn = insn;
aee4e0db 6316
b2ccb744
UW		 6317 for (prev = pool_list; *prev; prev = &(*prev)->next)
6318 ;
6319 *prev = pool;
6320
6321 return pool;
6322}
6323
aee4e0db
UW		 6324/* End range of instructions covered by POOL at INSN and emit
6325 placeholder insn representing the pool. */
b2ccb744
UW		 6326
6327static void
775c43d3 6328s390_end_pool (struct constant_pool *pool, rtx_insn *insn)
b2ccb744 6329{
aee4e0db
UW		 6330 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
6331
6332 if (!insn)
6333 insn = get_last_insn ();
6334
6335 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
6336 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6337}
6338
6339/* Add INSN to the list of insns covered by POOL. */
6340
6341static void
9c808aad 6342s390_add_pool_insn (struct constant_pool *pool, rtx insn)
aee4e0db
UW		 6343{
6344 bitmap_set_bit (pool->insns, INSN_UID (insn));
b2ccb744
UW		 6345}
6346
6347/* Return pool out of POOL_LIST that covers INSN. */
6348
6349static struct constant_pool *
9c808aad 6350s390_find_pool (struct constant_pool *pool_list, rtx insn)
b2ccb744 6351{
b2ccb744
UW		 6352 struct constant_pool *pool;
6353
b2ccb744 6354 for (pool = pool_list; pool; pool = pool->next)
aee4e0db 6355 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
b2ccb744
UW		 6356 break;
6357
6358 return pool;
6359}
6360
aee4e0db 6361/* Add constant VAL of mode MODE to the constant pool POOL. */
b2ccb744 6362
aee4e0db 6363static void
ef4bddc2 6364s390_add_constant (struct constant_pool *pool, rtx val, machine_mode mode)
b2ccb744
UW		 6365{
6366 struct constant *c;
b2ccb744
UW		 6367 int i;
6368
6369 for (i = 0; i < NR_C_MODES; i++)
6370 if (constant_modes[i] == mode)
6371 break;
8d933e31 6372 gcc_assert (i != NR_C_MODES);
b2ccb744
UW		 6373
6374 for (c = pool->constants[i]; c != NULL; c = c->next)
6375 if (rtx_equal_p (val, c->value))
6376 break;
6377
6378 if (c == NULL)
6379 {
6380 c = (struct constant *) xmalloc (sizeof *c);
6381 c->value = val;
6382 c->label = gen_label_rtx ();
6383 c->next = pool->constants[i];
6384 pool->constants[i] = c;
6385 pool->size += GET_MODE_SIZE (mode);
6386 }
aee4e0db 6387}
b2ccb744 6388
dc66391d
RS		 6389/* Return an rtx that represents the offset of X from the start of
6390 pool POOL. */
6391
6392static rtx
6393s390_pool_offset (struct constant_pool *pool, rtx x)
6394{
6395 rtx label;
6396
6397 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
6398 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
6399 UNSPEC_POOL_OFFSET);
6400 return gen_rtx_CONST (GET_MODE (x), x);
6401}
6402
aee4e0db
UW		 6403/* Find constant VAL of mode MODE in the constant pool POOL.
6404 Return an RTX describing the distance from the start of
6405 the pool to the location of the new constant. */
c7453384 6406
aee4e0db 6407static rtx
9c808aad 6408s390_find_constant (struct constant_pool *pool, rtx val,
ef4bddc2 6409 machine_mode mode)
aee4e0db
UW		 6410{
6411 struct constant *c;
aee4e0db 6412 int i;
c7453384 6413
aee4e0db
UW		 6414 for (i = 0; i < NR_C_MODES; i++)
6415 if (constant_modes[i] == mode)
6416 break;
8d933e31 6417 gcc_assert (i != NR_C_MODES);
c7453384 6418
aee4e0db
UW		 6419 for (c = pool->constants[i]; c != NULL; c = c->next)
6420 if (rtx_equal_p (val, c->value))
6421 break;
c7453384 6422
8d933e31 6423 gcc_assert (c);
c7453384 6424
dc66391d 6425 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
b2ccb744
UW		 6426}
6427
ab96de7e
AS		 6428/* Check whether INSN is an execute. Return the label_ref to its
6429 execute target template if so, NULL_RTX otherwise. */
6430
6431static rtx
6432s390_execute_label (rtx insn)
6433{
b64925dc 6434 if (NONJUMP_INSN_P (insn)
ab96de7e
AS		 6435 && GET_CODE (PATTERN (insn)) == PARALLEL
6436 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
6437 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
6438 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
6439
6440 return NULL_RTX;
6441}
6442
9bb86f41
UW		 6443/* Add execute target for INSN to the constant pool POOL. */
6444
6445static void
6446s390_add_execute (struct constant_pool *pool, rtx insn)
6447{
6448 struct constant *c;
6449
6450 for (c = pool->execute; c != NULL; c = c->next)
6451 if (INSN_UID (insn) == INSN_UID (c->value))
6452 break;
6453
6454 if (c == NULL)
6455 {
9bb86f41
UW		 6456 c = (struct constant *) xmalloc (sizeof *c);
6457 c->value = insn;
d24959df 6458 c->label = gen_label_rtx ();
9bb86f41
UW		 6459 c->next = pool->execute;
6460 pool->execute = c;
d24959df 6461 pool->size += 6;
9bb86f41
UW		 6462 }
6463}
6464
6465/* Find execute target for INSN in the constant pool POOL.
6466 Return an RTX describing the distance from the start of
6467 the pool to the location of the execute target. */
6468
6469static rtx
6470s390_find_execute (struct constant_pool *pool, rtx insn)
6471{
6472 struct constant *c;
9bb86f41
UW		 6473
6474 for (c = pool->execute; c != NULL; c = c->next)
6475 if (INSN_UID (insn) == INSN_UID (c->value))
6476 break;
6477
8d933e31 6478 gcc_assert (c);
9bb86f41 6479
dc66391d 6480 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
9bb86f41
UW		 6481}
6482
ab96de7e 6483/* For an execute INSN, extract the execute target template. */
9bb86f41
UW		 6484
6485static rtx
ab96de7e 6486s390_execute_target (rtx insn)
9bb86f41 6487{
ab96de7e
AS		 6488 rtx pattern = PATTERN (insn);
6489 gcc_assert (s390_execute_label (insn));
9bb86f41
UW		 6490
6491 if (XVECLEN (pattern, 0) == 2)
6492 {
6493 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6494 }
6495 else
6496 {
6497 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6498 int i;
6499
6500 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6501 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6502
6503 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6504 }
6505
6506 return pattern;
6507}
6508
6509/* Indicate that INSN cannot be duplicated. This is the case for
6510 execute insns that carry a unique label. */
6511
6512static bool
ac44248e 6513s390_cannot_copy_insn_p (rtx_insn *insn)
9bb86f41
UW		 6514{
6515 rtx label = s390_execute_label (insn);
6516 return label && label != const0_rtx;
6517}
6518
5af2f3d3
UW		 6519/* Dump out the constants in POOL. If REMOTE_LABEL is true,
6520 do not emit the pool base label. */
b2ccb744 6521
9bb86f41 6522static void
5af2f3d3 6523s390_dump_pool (struct constant_pool *pool, bool remote_label)
b2ccb744
UW		 6524{
6525 struct constant *c;
775c43d3 6526 rtx_insn *insn = pool->pool_insn;
b2ccb744
UW		 6527 int i;
6528
9bb86f41
UW		 6529 /* Switch to rodata section. */
6530 if (TARGET_CPU_ZARCH)
6531 {
6532 insn = emit_insn_after (gen_pool_section_start (), insn);
6533 INSN_ADDRESSES_NEW (insn, -1);
6534 }
6535
6536 /* Ensure minimum pool alignment. */
9e8327e3 6537 if (TARGET_CPU_ZARCH)
9bb86f41 6538 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
b2ccb744 6539 else
9bb86f41 6540 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
b2ccb744
UW		 6541 INSN_ADDRESSES_NEW (insn, -1);
6542
9bb86f41 6543 /* Emit pool base label. */
5af2f3d3
UW		 6544 if (!remote_label)
6545 {
6546 insn = emit_label_after (pool->label, insn);
6547 INSN_ADDRESSES_NEW (insn, -1);
6548 }
b2ccb744
UW		 6549
6550 /* Dump constants in descending alignment requirement order,
6551 ensuring proper alignment for every constant. */
6552 for (i = 0; i < NR_C_MODES; i++)
6553 for (c = pool->constants[i]; c; c = c->next)
6554 {
fd7643fb 6555 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
77340500 6556 rtx value = copy_rtx (c->value);
aee4e0db
UW		 6557 if (GET_CODE (value) == CONST
6558 && GET_CODE (XEXP (value, 0)) == UNSPEC
fd7643fb 6559 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
aee4e0db 6560 && XVECLEN (XEXP (value, 0), 0) == 1)
dc66391d 6561 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
aee4e0db 6562
b2ccb744
UW		 6563 insn = emit_label_after (c->label, insn);
6564 INSN_ADDRESSES_NEW (insn, -1);
416cf582 6565
38899e29 6566 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
416cf582
UW		 6567 gen_rtvec (1, value),
6568 UNSPECV_POOL_ENTRY);
6569 insn = emit_insn_after (value, insn);
b2ccb744
UW		 6570 INSN_ADDRESSES_NEW (insn, -1);
6571 }
6572
9bb86f41
UW		 6573 /* Ensure minimum alignment for instructions. */
6574 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
b2ccb744
UW		 6575 INSN_ADDRESSES_NEW (insn, -1);
6576
9bb86f41
UW		 6577 /* Output in-pool execute template insns. */
6578 for (c = pool->execute; c; c = c->next)
6579 {
9bb86f41
UW		 6580 insn = emit_label_after (c->label, insn);
6581 INSN_ADDRESSES_NEW (insn, -1);
6582
6583 insn = emit_insn_after (s390_execute_target (c->value), insn);
6584 INSN_ADDRESSES_NEW (insn, -1);
6585 }
6586
6587 /* Switch back to previous section. */
6588 if (TARGET_CPU_ZARCH)
6589 {
6590 insn = emit_insn_after (gen_pool_section_end (), insn);
6591 INSN_ADDRESSES_NEW (insn, -1);
6592 }
6593
b2ccb744
UW		 6594 insn = emit_barrier_after (insn);
6595 INSN_ADDRESSES_NEW (insn, -1);
6596
aee4e0db
UW		 6597 /* Remove placeholder insn. */
6598 remove_insn (pool->pool_insn);
9bb86f41
UW		 6599}
6600
b2ccb744
UW		 6601/* Free all memory used by POOL. */
6602
6603static void
9c808aad 6604s390_free_pool (struct constant_pool *pool)
b2ccb744 6605{
9bb86f41 6606 struct constant *c, *next;
b2ccb744
UW		 6607 int i;
6608
6609 for (i = 0; i < NR_C_MODES; i++)
9bb86f41
UW		 6610 for (c = pool->constants[i]; c; c = next)
6611 {
6612 next = c->next;
6613 free (c);
6614 }
6615
6616 for (c = pool->execute; c; c = next)
b2ccb744 6617 {
9bb86f41
UW		 6618 next = c->next;
6619 free (c);
b2ccb744
UW		 6620 }
6621
7b210806 6622 BITMAP_FREE (pool->insns);
b2ccb744 6623 free (pool);
c7453384 6624}
b2ccb744 6625
b2ccb744 6626
5af2f3d3
UW		 6627/* Collect main literal pool. Return NULL on overflow. */
6628
6629static struct constant_pool *
6630s390_mainpool_start (void)
6631{
6632 struct constant_pool *pool;
775c43d3 6633 rtx_insn *insn;
5af2f3d3
UW		 6634
6635 pool = s390_alloc_pool ();
6636
6637 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6638 {
b64925dc 6639 if (NONJUMP_INSN_P (insn)
585539a1
UW		 6640 && GET_CODE (PATTERN (insn)) == SET
6641 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6642 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
5af2f3d3 6643 {
177bc204
RS		 6644 /* There might be two main_pool instructions if base_reg
6645 is call-clobbered; one for shrink-wrapped code and one
6646 for the rest. We want to keep the first. */
6647 if (pool->pool_insn)
6648 {
6649 insn = PREV_INSN (insn);
6650 delete_insn (NEXT_INSN (insn));
6651 continue;
6652 }
5af2f3d3
UW		 6653 pool->pool_insn = insn;
6654 }
6655
d24959df 6656 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
9bb86f41
UW		 6657 {
6658 s390_add_execute (pool, insn);
6659 }
b64925dc 6660 else if (NONJUMP_INSN_P (insn) || CALL_P (insn))
5af2f3d3
UW		 6661 {
6662 rtx pool_ref = NULL_RTX;
6663 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6664 if (pool_ref)
6665 {
6666 rtx constant = get_pool_constant (pool_ref);
ef4bddc2 6667 machine_mode mode = get_pool_mode (pool_ref);
5af2f3d3
UW		 6668 s390_add_constant (pool, constant, mode);
6669 }
6670 }
03870a04
AK		 6671
6672 /* If hot/cold partitioning is enabled we have to make sure that
6673 the literal pool is emitted in the same section where the
6674 initialization of the literal pool base pointer takes place.
6675 emit_pool_after is only used in the non-overflow case on non
6676 Z cpus where we can emit the literal pool at the end of the
6677 function body within the text section. */
6678 if (NOTE_P (insn)
b49326f1
AK		 6679 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6680 && !pool->emit_pool_after)
6681 pool->emit_pool_after = PREV_INSN (insn);
5af2f3d3
UW		 6682 }
6683
8d933e31 6684 gcc_assert (pool->pool_insn || pool->size == 0);
5af2f3d3
UW		 6685
6686 if (pool->size >= 4096)
6687 {
d76e8439
UW		 6688 /* We're going to chunkify the pool, so remove the main
6689 pool placeholder insn. */
6690 remove_insn (pool->pool_insn);
6691
5af2f3d3
UW		 6692 s390_free_pool (pool);
6693 pool = NULL;
6694 }
6695
03870a04
AK		 6696 /* If the functions ends with the section where the literal pool
6697 should be emitted set the marker to its end. */
b49326f1 6698 if (pool && !pool->emit_pool_after)
03870a04
AK		 6699 pool->emit_pool_after = get_last_insn ();
6700
5af2f3d3
UW		 6701 return pool;
6702}
6703
6704/* POOL holds the main literal pool as collected by s390_mainpool_start.
6705 Modify the current function to output the pool constants as well as
585539a1 6706 the pool register setup instruction. */
5af2f3d3
UW		 6707
6708static void
585539a1 6709s390_mainpool_finish (struct constant_pool *pool)
5af2f3d3 6710{
91086990 6711 rtx base_reg = cfun->machine->base_reg;
5af2f3d3
UW		 6712
6713 /* If the pool is empty, we're done. */
6714 if (pool->size == 0)
6715 {
91086990
UW		 6716 /* We don't actually need a base register after all. */
6717 cfun->machine->base_reg = NULL_RTX;
6718
6719 if (pool->pool_insn)
6720 remove_insn (pool->pool_insn);
5af2f3d3
UW		 6721 s390_free_pool (pool);
6722 return;
6723 }
6724
6725 /* We need correct insn addresses. */
6726 shorten_branches (get_insns ());
6727
9e8327e3 6728 /* On zSeries, we use a LARL to load the pool register. The pool is
5af2f3d3 6729 located in the .rodata section, so we emit it after the function. */
9e8327e3 6730 if (TARGET_CPU_ZARCH)
5af2f3d3 6731 {
17f385d8
DM		 6732 rtx set = gen_main_base_64 (base_reg, pool->label);
6733 rtx_insn *insn = emit_insn_after (set, pool->pool_insn);
5af2f3d3
UW		 6734 INSN_ADDRESSES_NEW (insn, -1);
6735 remove_insn (pool->pool_insn);
38899e29
EC		 6736
6737 insn = get_last_insn ();
5af2f3d3
UW		 6738 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6739 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6740
6741 s390_dump_pool (pool, 0);
6742 }
6743
9e8327e3 6744 /* On S/390, if the total size of the function's code plus literal pool
5af2f3d3
UW		 6745 does not exceed 4096 bytes, we use BASR to set up a function base
6746 pointer, and emit the literal pool at the end of the function. */
03870a04 6747 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
5af2f3d3
UW		 6748 + pool->size + 8 /* alignment slop */ < 4096)
6749 {
17f385d8
DM		 6750 rtx set = gen_main_base_31_small (base_reg, pool->label);
6751 rtx_insn *insn = emit_insn_after (set, pool->pool_insn);
5af2f3d3
UW		 6752 INSN_ADDRESSES_NEW (insn, -1);
6753 remove_insn (pool->pool_insn);
6754
6755 insn = emit_label_after (pool->label, insn);
6756 INSN_ADDRESSES_NEW (insn, -1);
6757
03870a04
AK		 6758 /* emit_pool_after will be set by s390_mainpool_start to the
6759 last insn of the section where the literal pool should be
6760 emitted. */
6761 insn = pool->emit_pool_after;
6762
5af2f3d3
UW		 6763 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6764 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6765
6766 s390_dump_pool (pool, 1);
6767 }
6768
6769 /* Otherwise, we emit an inline literal pool and use BASR to branch
6770 over it, setting up the pool register at the same time. */
6771 else
6772 {
17f385d8 6773 rtx_code_label *pool_end = gen_label_rtx ();
5af2f3d3 6774
17f385d8
DM		 6775 rtx pat = gen_main_base_31_large (base_reg, pool->label, pool_end);
6776 rtx_insn *insn = emit_jump_insn_after (pat, pool->pool_insn);
b0a1ac21 6777 JUMP_LABEL (insn) = pool_end;
5af2f3d3
UW		 6778 INSN_ADDRESSES_NEW (insn, -1);
6779 remove_insn (pool->pool_insn);
6780
6781 insn = emit_label_after (pool->label, insn);
6782 INSN_ADDRESSES_NEW (insn, -1);
6783
6784 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6785 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6786
6787 insn = emit_label_after (pool_end, pool->pool_insn);
6788 INSN_ADDRESSES_NEW (insn, -1);
6789
6790 s390_dump_pool (pool, 1);
6791 }
6792
6793
6794 /* Replace all literal pool references. */
6795
b32d5189 6796 for (rtx_insn *insn = get_insns (); insn; insn = NEXT_INSN (insn))
5af2f3d3
UW		 6797 {
6798 if (INSN_P (insn))
585539a1 6799 replace_ltrel_base (&PATTERN (insn));
5af2f3d3 6800
b64925dc 6801 if (NONJUMP_INSN_P (insn) || CALL_P (insn))
5af2f3d3
UW		 6802 {
6803 rtx addr, pool_ref = NULL_RTX;
6804 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6805 if (pool_ref)
6806 {
9bb86f41
UW		 6807 if (s390_execute_label (insn))
6808 addr = s390_find_execute (pool, insn);
6809 else
6810 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6811 get_pool_mode (pool_ref));
6812
5af2f3d3
UW		 6813 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6814 INSN_CODE (insn) = -1;
6815 }
6816 }
6817 }
6818
6819
6820 /* Free the pool. */
6821 s390_free_pool (pool);
6822}
6823
6824/* POOL holds the main literal pool as collected by s390_mainpool_start.
6825 We have decided we cannot use this pool, so revert all changes
6826 to the current function that were done by s390_mainpool_start. */
6827static void
6828s390_mainpool_cancel (struct constant_pool *pool)
6829{
6830 /* We didn't actually change the instruction stream, so simply
6831 free the pool memory. */
6832 s390_free_pool (pool);
6833}
6834
6835
585539a1 6836/* Chunkify the literal pool. */
9db1d521 6837
b2ccb744
UW		 6838#define S390_POOL_CHUNK_MIN 0xc00
6839#define S390_POOL_CHUNK_MAX 0xe00
6840
c7453384 6841static struct constant_pool *
585539a1 6842s390_chunkify_start (void)
9db1d521 6843{
b2ccb744
UW		 6844 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6845 int extra_size = 0;
6846 bitmap far_labels;
fd7643fb 6847 rtx pending_ltrel = NULL_RTX;
775c43d3 6848 rtx_insn *insn;
9db1d521 6849
9c808aad 6850 rtx (*gen_reload_base) (rtx, rtx) =
9e8327e3 6851 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
aee4e0db
UW		 6852
6853
c3cc6b78
UW		 6854 /* We need correct insn addresses. */
6855
6856 shorten_branches (get_insns ());
6857
fd7643fb 6858 /* Scan all insns and move literals to pool chunks. */
13e58269 6859
13e58269 6860 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9db1d521 6861 {
03870a04
AK		 6862 bool section_switch_p = false;
6863
fd7643fb
UW		 6864 /* Check for pending LTREL_BASE. */
6865 if (INSN_P (insn))
6866 {
6867 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6868 if (ltrel_base)
6869 {
8d933e31
AS		 6870 gcc_assert (ltrel_base == pending_ltrel);
6871 pending_ltrel = NULL_RTX;
fd7643fb
UW		 6872 }
6873 }
6874
d24959df 6875 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
9bb86f41
UW		 6876 {
6877 if (!curr_pool)
6878 curr_pool = s390_start_pool (&pool_list, insn);
6879
6880 s390_add_execute (curr_pool, insn);
6881 s390_add_pool_insn (curr_pool, insn);
6882 }
b64925dc 6883 else if (NONJUMP_INSN_P (insn) || CALL_P (insn))
b2ccb744 6884 {
aee4e0db 6885 rtx pool_ref = NULL_RTX;
b2ccb744
UW		 6886 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6887 if (pool_ref)
6888 {
fd7643fb 6889 rtx constant = get_pool_constant (pool_ref);
ef4bddc2 6890 machine_mode mode = get_pool_mode (pool_ref);
fd7643fb 6891
b2ccb744
UW		 6892 if (!curr_pool)
6893 curr_pool = s390_start_pool (&pool_list, insn);
6894
fd7643fb 6895 s390_add_constant (curr_pool, constant, mode);
aee4e0db 6896 s390_add_pool_insn (curr_pool, insn);
aee4e0db 6897
fd7643fb
UW		 6898 /* Don't split the pool chunk between a LTREL_OFFSET load
6899 and the corresponding LTREL_BASE. */
6900 if (GET_CODE (constant) == CONST
6901 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6902 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6903 {
8d933e31 6904 gcc_assert (!pending_ltrel);
fd7643fb
UW		 6905 pending_ltrel = pool_ref;
6906 }
b2ccb744
UW		 6907 }
6908 }
6909
39718607 6910 if (JUMP_P (insn) || JUMP_TABLE_DATA_P (insn) || LABEL_P (insn))
fd7643fb
UW		 6911 {
6912 if (curr_pool)
6913 s390_add_pool_insn (curr_pool, insn);
6914 /* An LTREL_BASE must follow within the same basic block. */
8d933e31 6915 gcc_assert (!pending_ltrel);
fd7643fb 6916 }
aee4e0db 6917
00fbd5c8
JJ		 6918 if (NOTE_P (insn))
6919 switch (NOTE_KIND (insn))
6920 {
6921 case NOTE_INSN_SWITCH_TEXT_SECTIONS:
6922 section_switch_p = true;
6923 break;
6924 case NOTE_INSN_VAR_LOCATION:
6925 case NOTE_INSN_CALL_ARG_LOCATION:
6926 continue;
6927 default:
6928 break;
6929 }
03870a04 6930
c7453384 6931 if (!curr_pool
b2ccb744
UW		 6932 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6933 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
9db1d521 6934 continue;
13e58269 6935
9e8327e3 6936 if (TARGET_CPU_ZARCH)
9db1d521 6937 {
b2ccb744
UW		 6938 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6939 continue;
13e58269 6940
775c43d3 6941 s390_end_pool (curr_pool, NULL);
b2ccb744
UW		 6942 curr_pool = NULL;
6943 }
6944 else
9db1d521 6945 {
b2ccb744 6946 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
9c808aad 6947 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
b2ccb744
UW		 6948 + extra_size;
6949
6950 /* We will later have to insert base register reload insns.
6951 Those will have an effect on code size, which we need to
6952 consider here. This calculation makes rather pessimistic
6953 worst-case assumptions. */
b64925dc 6954 if (LABEL_P (insn))
b2ccb744 6955 extra_size += 6;
b2ccb744
UW		 6956
6957 if (chunk_size < S390_POOL_CHUNK_MIN
03870a04
AK		 6958 && curr_pool->size < S390_POOL_CHUNK_MIN
6959 && !section_switch_p)
b2ccb744
UW		 6960 continue;
6961
6962 /* Pool chunks can only be inserted after BARRIERs ... */
b64925dc 6963 if (BARRIER_P (insn))
b2ccb744
UW		 6964 {
6965 s390_end_pool (curr_pool, insn);
6966 curr_pool = NULL;
6967 extra_size = 0;
6968 }
6969
6970 /* ... so if we don't find one in time, create one. */
03870a04
AK		 6971 else if (chunk_size > S390_POOL_CHUNK_MAX
6972 || curr_pool->size > S390_POOL_CHUNK_MAX
6973 || section_switch_p)
b2ccb744 6974 {
775c43d3 6975 rtx_insn *label, *jump, *barrier, *next, *prev;
b2ccb744 6976
03870a04
AK		 6977 if (!section_switch_p)
6978 {
6979 /* We can insert the barrier only after a 'real' insn. */
b64925dc 6980 if (! NONJUMP_INSN_P (insn) && ! CALL_P (insn))
03870a04
AK		 6981 continue;
6982 if (get_attr_length (insn) == 0)
6983 continue;
6984 /* Don't separate LTREL_BASE from the corresponding
00fbd5c8 6985 LTREL_OFFSET load. */
03870a04
AK		 6986 if (pending_ltrel)
6987 continue;
00fbd5c8
JJ		 6988 next = insn;
6989 do
6990 {
6991 insn = next;
6992 next = NEXT_INSN (insn);
6993 }
6994 while (next
6995 && NOTE_P (next)
6996 && (NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION
6997 || NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION));
03870a04
AK		 6998 }
6999 else
7000 {
7001 gcc_assert (!pending_ltrel);
7002
7003 /* The old pool has to end before the section switch
7004 note in order to make it part of the current
7005 section. */
7006 insn = PREV_INSN (insn);
7007 }
aee4e0db 7008
9c808aad 7009 label = gen_label_rtx ();
00fbd5c8
JJ		 7010 prev = insn;
7011 if (prev && NOTE_P (prev))
7012 prev = prev_nonnote_insn (prev);
7013 if (prev)
7014 jump = emit_jump_insn_after_setloc (gen_jump (label), insn,
9d12bc68 7015 INSN_LOCATION (prev));
00fbd5c8
JJ		 7016 else
7017 jump = emit_jump_insn_after_noloc (gen_jump (label), insn);
b2ccb744
UW		 7018 barrier = emit_barrier_after (jump);
7019 insn = emit_label_after (label, barrier);
7020 JUMP_LABEL (jump) = label;
7021 LABEL_NUSES (label) = 1;
7022
aee4e0db
UW		 7023 INSN_ADDRESSES_NEW (jump, -1);
7024 INSN_ADDRESSES_NEW (barrier, -1);
b2ccb744
UW		 7025 INSN_ADDRESSES_NEW (insn, -1);
7026
7027 s390_end_pool (curr_pool, barrier);
7028 curr_pool = NULL;
7029 extra_size = 0;
7030 }
13e58269 7031 }
9db1d521 7032 }
ce50cae8 7033
aee4e0db 7034 if (curr_pool)
775c43d3 7035 s390_end_pool (curr_pool, NULL);
8d933e31 7036 gcc_assert (!pending_ltrel);
b2ccb744 7037
c7453384 7038 /* Find all labels that are branched into
13e58269 7039 from an insn belonging to a different chunk. */
ce50cae8 7040
7b210806 7041 far_labels = BITMAP_ALLOC (NULL);
6bc627b3 7042
13e58269 7043 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
9db1d521 7044 {
8942ee0f 7045 rtx_jump_table_data *table;
966f97ac 7046
b2ccb744
UW		 7047 /* Labels marked with LABEL_PRESERVE_P can be target
7048 of non-local jumps, so we have to mark them.
7049 The same holds for named labels.
7050
7051 Don't do that, however, if it is the label before
7052 a jump table. */
7053
b64925dc 7054 if (LABEL_P (insn)
b2ccb744
UW		 7055 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
7056 {
775c43d3 7057 rtx_insn *vec_insn = NEXT_INSN (insn);
34f0d87a 7058 if (! vec_insn || ! JUMP_TABLE_DATA_P (vec_insn))
b2ccb744
UW		 7059 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
7060 }
966f97ac
JJ		 7061 /* Check potential targets in a table jump (casesi_jump). */
7062 else if (tablejump_p (insn, NULL, &table))
7063 {
7064 rtx vec_pat = PATTERN (table);
7065 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
7066
7067 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
7068 {
7069 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
b2ccb744 7070
966f97ac
JJ		 7071 if (s390_find_pool (pool_list, label)
7072 != s390_find_pool (pool_list, insn))
7073 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
7074 }
7075 }
7076 /* If we have a direct jump (conditional or unconditional),
7077 check all potential targets. */
b64925dc 7078 else if (JUMP_P (insn))
13e58269 7079 {
966f97ac 7080 rtx pat = PATTERN (insn);
5fdc1e5d 7081
966f97ac 7082 if (GET_CODE (pat) == PARALLEL)
0a3bdf9d
UW		 7083 pat = XVECEXP (pat, 0, 0);
7084
966f97ac
JJ		 7085 if (GET_CODE (pat) == SET)
7086 {
aee4e0db 7087 rtx label = JUMP_LABEL (insn);
177bc204 7088 if (label && !ANY_RETURN_P (label))
13e58269 7089 {
966f97ac 7090 if (s390_find_pool (pool_list, label)
b2ccb744
UW		 7091 != s390_find_pool (pool_list, insn))
7092 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
13e58269 7093 }
b2ccb744 7094 }
966f97ac 7095 }
9db1d521 7096 }
ce50cae8 7097
b2ccb744
UW		 7098 /* Insert base register reload insns before every pool. */
7099
7100 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
aee4e0db 7101 {
f4aa3848 7102 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
585539a1 7103 curr_pool->label);
775c43d3 7104 rtx_insn *insn = curr_pool->first_insn;
aee4e0db
UW		 7105 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
7106 }
b2ccb744
UW		 7107
7108 /* Insert base register reload insns at every far label. */
13e58269 7109
13e58269 7110 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
b64925dc 7111 if (LABEL_P (insn)
b2ccb744
UW		 7112 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
7113 {
7114 struct constant_pool *pool = s390_find_pool (pool_list, insn);
7115 if (pool)
7116 {
f4aa3848 7117 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
585539a1 7118 pool->label);
aee4e0db 7119 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
b2ccb744
UW		 7120 }
7121 }
7122
aee4e0db 7123
7b210806 7124 BITMAP_FREE (far_labels);
13e58269 7125
13e58269
UW		 7126
7127 /* Recompute insn addresses. */
7128
7129 init_insn_lengths ();
7130 shorten_branches (get_insns ());
9db1d521 7131
aee4e0db
UW		 7132 return pool_list;
7133}
9db1d521 7134
aee4e0db 7135/* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
c7453384 7136 After we have decided to use this list, finish implementing
585539a1 7137 all changes to the current function as required. */
c7453384 7138
aee4e0db 7139static void
585539a1 7140s390_chunkify_finish (struct constant_pool *pool_list)
aee4e0db 7141{
aee4e0db 7142 struct constant_pool *curr_pool = NULL;
775c43d3 7143 rtx_insn *insn;
c7453384
EC		 7144
7145
aee4e0db
UW		 7146 /* Replace all literal pool references. */
7147
c7453384 7148 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
aee4e0db 7149 {
fd7643fb 7150 if (INSN_P (insn))
585539a1 7151 replace_ltrel_base (&PATTERN (insn));
fd7643fb 7152
aee4e0db
UW		 7153 curr_pool = s390_find_pool (pool_list, insn);
7154 if (!curr_pool)
7155 continue;
7156
b64925dc 7157 if (NONJUMP_INSN_P (insn) || CALL_P (insn))
aee4e0db
UW		 7158 {
7159 rtx addr, pool_ref = NULL_RTX;
7160 find_constant_pool_ref (PATTERN (insn), &pool_ref);
7161 if (pool_ref)
7162 {
9bb86f41
UW		 7163 if (s390_execute_label (insn))
7164 addr = s390_find_execute (curr_pool, insn);
7165 else
7166 addr = s390_find_constant (curr_pool,
7167 get_pool_constant (pool_ref),
7168 get_pool_mode (pool_ref));
7169
aee4e0db
UW		 7170 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
7171 INSN_CODE (insn) = -1;
7172 }
aee4e0db
UW		 7173 }
7174 }
7175
7176 /* Dump out all literal pools. */
c7453384 7177
aee4e0db 7178 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
5af2f3d3 7179 s390_dump_pool (curr_pool, 0);
c7453384 7180
aee4e0db
UW		 7181 /* Free pool list. */
7182
7183 while (pool_list)
7184 {
7185 struct constant_pool *next = pool_list->next;
7186 s390_free_pool (pool_list);
7187 pool_list = next;
7188 }
7189}
7190
7191/* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7192 We have decided we cannot use this list, so revert all changes
7193 to the current function that were done by s390_chunkify_start. */
c7453384 7194
aee4e0db 7195static void
9c808aad 7196s390_chunkify_cancel (struct constant_pool *pool_list)
aee4e0db
UW		 7197{
7198 struct constant_pool *curr_pool = NULL;
775c43d3 7199 rtx_insn *insn;
aee4e0db
UW		 7200
7201 /* Remove all pool placeholder insns. */
7202
7203 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7204 {
7205 /* Did we insert an extra barrier? Remove it. */
775c43d3
DM		 7206 rtx_insn *barrier = PREV_INSN (curr_pool->pool_insn);
7207 rtx_insn *jump = barrier? PREV_INSN (barrier) : NULL;
7208 rtx_insn *label = NEXT_INSN (curr_pool->pool_insn);
aee4e0db 7209
b64925dc
SB		 7210 if (jump && JUMP_P (jump)
7211 && barrier && BARRIER_P (barrier)
7212 && label && LABEL_P (label)
aee4e0db
UW		 7213 && GET_CODE (PATTERN (jump)) == SET
7214 && SET_DEST (PATTERN (jump)) == pc_rtx
7215 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
7216 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
7217 {
7218 remove_insn (jump);
7219 remove_insn (barrier);
7220 remove_insn (label);
b2ccb744 7221 }
9db1d521 7222
aee4e0db
UW		 7223 remove_insn (curr_pool->pool_insn);
7224 }
7225
fd7643fb 7226 /* Remove all base register reload insns. */
aee4e0db
UW		 7227
7228 for (insn = get_insns (); insn; )
7229 {
775c43d3 7230 rtx_insn *next_insn = NEXT_INSN (insn);
aee4e0db 7231
b64925dc 7232 if (NONJUMP_INSN_P (insn)
aee4e0db
UW		 7233 && GET_CODE (PATTERN (insn)) == SET
7234 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
fd7643fb 7235 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
aee4e0db 7236 remove_insn (insn);
9db1d521 7237
aee4e0db
UW		 7238 insn = next_insn;
7239 }
7240
7241 /* Free pool list. */
9db1d521 7242
b2ccb744 7243 while (pool_list)
9db1d521 7244 {
b2ccb744
UW		 7245 struct constant_pool *next = pool_list->next;
7246 s390_free_pool (pool_list);
7247 pool_list = next;
9db1d521 7248 }
9db1d521
HP		 7249}
7250
faeb9bb6 7251/* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
416cf582
UW		 7252
7253void
ef4bddc2 7254s390_output_pool_entry (rtx exp, machine_mode mode, unsigned int align)
416cf582
UW		 7255{
7256 REAL_VALUE_TYPE r;
7257
7258 switch (GET_MODE_CLASS (mode))
7259 {
7260 case MODE_FLOAT:
4dc19cc0 7261 case MODE_DECIMAL_FLOAT:
8d933e31 7262 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
416cf582
UW		 7263
7264 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
7265 assemble_real (r, mode, align);
7266 break;
7267
7268 case MODE_INT:
faeb9bb6 7269 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
a7fe25b8 7270 mark_symbol_refs_as_used (exp);
416cf582
UW		 7271 break;
7272
7273 default:
8d933e31 7274 gcc_unreachable ();
416cf582
UW		 7275 }
7276}
7277
7278
ab96de7e
AS		 7279/* Return an RTL expression representing the value of the return address
7280 for the frame COUNT steps up from the current frame. FRAME is the
7281 frame pointer of that frame. */
b2ccb744 7282
ab96de7e
AS		 7283rtx
7284s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
b2ccb744 7285{
ab96de7e
AS		 7286 int offset;
7287 rtx addr;
aee4e0db 7288
ab96de7e 7289 /* Without backchain, we fail for all but the current frame. */
c3cc6b78 7290
ab96de7e
AS		 7291 if (!TARGET_BACKCHAIN && count > 0)
7292 return NULL_RTX;
c3cc6b78 7293
ab96de7e
AS		 7294 /* For the current frame, we need to make sure the initial
7295 value of RETURN_REGNUM is actually saved. */
c3cc6b78 7296
ab96de7e 7297 if (count == 0)
c3cc6b78 7298 {
7bcebb25
AK		 7299 /* On non-z architectures branch splitting could overwrite r14. */
7300 if (TARGET_CPU_ZARCH)
7301 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
7302 else
7303 {
7304 cfun_frame_layout.save_return_addr_p = true;
7305 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
7306 }
ab96de7e 7307 }
c3cc6b78 7308
ab96de7e 7309 if (TARGET_PACKED_STACK)
9602b6a1 7310 offset = -2 * UNITS_PER_LONG;
ab96de7e 7311 else
9602b6a1 7312 offset = RETURN_REGNUM * UNITS_PER_LONG;
c3cc6b78 7313
0a81f074 7314 addr = plus_constant (Pmode, frame, offset);
ab96de7e
AS		 7315 addr = memory_address (Pmode, addr);
7316 return gen_rtx_MEM (Pmode, addr);
7317}
c3cc6b78 7318
ab96de7e
AS		 7319/* Return an RTL expression representing the back chain stored in
7320 the current stack frame. */
545d16ff 7321
ab96de7e
AS		 7322rtx
7323s390_back_chain_rtx (void)
7324{
7325 rtx chain;
545d16ff 7326
ab96de7e 7327 gcc_assert (TARGET_BACKCHAIN);
545d16ff 7328
ab96de7e 7329 if (TARGET_PACKED_STACK)
0a81f074 7330 chain = plus_constant (Pmode, stack_pointer_rtx,
9602b6a1 7331 STACK_POINTER_OFFSET - UNITS_PER_LONG);
ab96de7e
AS		 7332 else
7333 chain = stack_pointer_rtx;
545d16ff 7334
ab96de7e
AS		 7335 chain = gen_rtx_MEM (Pmode, chain);
7336 return chain;
7337}
c3cc6b78 7338
ab96de7e
AS		 7339/* Find first call clobbered register unused in a function.
7340 This could be used as base register in a leaf function
7341 or for holding the return address before epilogue. */
c3cc6b78 7342
ab96de7e
AS		 7343static int
7344find_unused_clobbered_reg (void)
7345{
7346 int i;
7347 for (i = 0; i < 6; i++)
6fb5fa3c 7348 if (!df_regs_ever_live_p (i))
ab96de7e
AS		 7349 return i;
7350 return 0;
7351}
c3cc6b78 7352
7bcebb25 7353
f4aa3848 7354/* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
7bcebb25
AK		 7355 clobbered hard regs in SETREG. */
7356
7357static void
7bc980e1 7358s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
7bcebb25 7359{
6455a49e 7360 char *regs_ever_clobbered = (char *)data;
7bcebb25 7361 unsigned int i, regno;
ef4bddc2 7362 machine_mode mode = GET_MODE (setreg);
7bcebb25
AK		 7363
7364 if (GET_CODE (setreg) == SUBREG)
7365 {
7366 rtx inner = SUBREG_REG (setreg);
5a3fe9b6 7367 if (!GENERAL_REG_P (inner) && !FP_REG_P (inner))
7bcebb25
AK		 7368 return;
7369 regno = subreg_regno (setreg);
7370 }
5a3fe9b6 7371 else if (GENERAL_REG_P (setreg) || FP_REG_P (setreg))
7bcebb25
AK		 7372 regno = REGNO (setreg);
7373 else
7374 return;
7375
7376 for (i = regno;
7377 i < regno + HARD_REGNO_NREGS (regno, mode);
7378 i++)
7379 regs_ever_clobbered[i] = 1;
7380}
7381
7382/* Walks through all basic blocks of the current function looking
7383 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7384 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7385 each of those regs. */
7386
7387static void
6455a49e 7388s390_regs_ever_clobbered (char regs_ever_clobbered[])
7bcebb25
AK		 7389{
7390 basic_block cur_bb;
775c43d3 7391 rtx_insn *cur_insn;
7bcebb25
AK		 7392 unsigned int i;
7393
6455a49e 7394 memset (regs_ever_clobbered, 0, 32);
7bcebb25
AK		 7395
7396 /* For non-leaf functions we have to consider all call clobbered regs to be
7397 clobbered. */
416ff32e 7398 if (!crtl->is_leaf)
7bcebb25 7399 {
5a3fe9b6 7400 for (i = 0; i < 32; i++)
7bcebb25
AK		 7401 regs_ever_clobbered[i] = call_really_used_regs[i];
7402 }
7403
7404 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7405 this work is done by liveness analysis (mark_regs_live_at_end).
7406 Special care is needed for functions containing landing pads. Landing pads
7407 may use the eh registers, but the code which sets these registers is not
7408 contained in that function. Hence s390_regs_ever_clobbered is not able to
7409 deal with this automatically. */
e3b5732b 7410 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
7bcebb25 7411 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
f4aa3848
AK		 7412 if (crtl->calls_eh_return
7413 || (cfun->machine->has_landing_pad_p
6fb5fa3c 7414 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
297a777d 7415 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
7bcebb25
AK		 7416
7417 /* For nonlocal gotos all call-saved registers have to be saved.
7418 This flag is also set for the unwinding code in libgcc.
7419 See expand_builtin_unwind_init. For regs_ever_live this is done by
7420 reload. */
6455a49e 7421 if (crtl->saves_all_registers)
5a3fe9b6 7422 for (i = 0; i < 32; i++)
7bcebb25
AK		 7423 if (!call_really_used_regs[i])
7424 regs_ever_clobbered[i] = 1;
7425
11cd3bed 7426 FOR_EACH_BB_FN (cur_bb, cfun)
7bcebb25
AK		 7427 {
7428 FOR_BB_INSNS (cur_bb, cur_insn)
7429 {
6455a49e
AK		 7430 rtx pat;
7431
7432 if (!INSN_P (cur_insn))
7433 continue;
7434
7435 pat = PATTERN (cur_insn);
7436
7437 /* Ignore GPR restore insns. */
7438 if (epilogue_completed && RTX_FRAME_RELATED_P (cur_insn))
7439 {
7440 if (GET_CODE (pat) == SET
7441 && GENERAL_REG_P (SET_DEST (pat)))
7442 {
7443 /* lgdr */
7444 if (GET_MODE (SET_SRC (pat)) == DImode
7445 && FP_REG_P (SET_SRC (pat)))
7446 continue;
7447
7448 /* l / lg */
7449 if (GET_CODE (SET_SRC (pat)) == MEM)
7450 continue;
7451 }
7452
7453 /* lm / lmg */
7454 if (GET_CODE (pat) == PARALLEL
7455 && load_multiple_operation (pat, VOIDmode))
7456 continue;
7457 }
7458
7459 note_stores (pat,
7460 s390_reg_clobbered_rtx,
7461 regs_ever_clobbered);
7bcebb25
AK		 7462 }
7463 }
7464}
7465
f4aa3848
AK		 7466/* Determine the frame area which actually has to be accessed
7467 in the function epilogue. The values are stored at the
ab96de7e 7468 given pointers AREA_BOTTOM (address of the lowest used stack
f4aa3848 7469 address) and AREA_TOP (address of the first item which does
ab96de7e 7470 not belong to the stack frame). */
545d16ff 7471
ab96de7e
AS		 7472static void
7473s390_frame_area (int *area_bottom, int *area_top)
7474{
7475 int b, t;
545d16ff 7476
ab96de7e
AS		 7477 b = INT_MAX;
7478 t = INT_MIN;
adf39f8f
AK		 7479
7480 if (cfun_frame_layout.first_restore_gpr != -1)
7481 {
7482 b = (cfun_frame_layout.gprs_offset
9602b6a1 7483 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
adf39f8f 7484 t = b + (cfun_frame_layout.last_restore_gpr
9602b6a1 7485 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
adf39f8f
AK		 7486 }
7487
7488 if (TARGET_64BIT && cfun_save_high_fprs_p)
7489 {
7490 b = MIN (b, cfun_frame_layout.f8_offset);
7491 t = MAX (t, (cfun_frame_layout.f8_offset
7492 + cfun_frame_layout.high_fprs * 8));
7493 }
7494
7495 if (!TARGET_64BIT)
b89b22fc 7496 {
2cf4c39e 7497 if (cfun_fpr_save_p (FPR4_REGNUM))
adf39f8f 7498 {
b89b22fc
AK		 7499 b = MIN (b, cfun_frame_layout.f4_offset);
7500 t = MAX (t, cfun_frame_layout.f4_offset + 8);
adf39f8f 7501 }
2cf4c39e 7502 if (cfun_fpr_save_p (FPR6_REGNUM))
b89b22fc
AK		 7503 {
7504 b = MIN (b, cfun_frame_layout.f4_offset + 8);
7505 t = MAX (t, cfun_frame_layout.f4_offset + 16);
7506 }
7507 }
adf39f8f
AK		 7508 *area_bottom = b;
7509 *area_top = t;
7510}
6455a49e
AK		 7511/* Update gpr_save_slots in the frame layout trying to make use of
7512 FPRs as GPR save slots.
7513 This is a helper routine of s390_register_info. */
4023fb28
UW		 7514
7515static void
6455a49e 7516s390_register_info_gprtofpr ()
4023fb28 7517{
6455a49e 7518 int save_reg_slot = FPR0_REGNUM;
4023fb28 7519 int i, j;
4023fb28 7520
6455a49e
AK		 7521 if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf)
7522 return;
7bcebb25 7523
6455a49e 7524 for (i = 15; i >= 6; i--)
5a3fe9b6 7525 {
6455a49e
AK		 7526 if (cfun_gpr_save_slot (i) == 0)
7527 continue;
36c0bd4f 7528
6455a49e
AK		 7529 /* Advance to the next FP register which can be used as a
7530 GPR save slot. */
7531 while ((!call_really_used_regs[save_reg_slot]
7532 || df_regs_ever_live_p (save_reg_slot)
7533 || cfun_fpr_save_p (save_reg_slot))
7534 && FP_REGNO_P (save_reg_slot))
7535 save_reg_slot++;
7536 if (!FP_REGNO_P (save_reg_slot))
7537 {
7538 /* We only want to use ldgr/lgdr if we can get rid of
7539 stm/lm entirely. So undo the gpr slot allocation in
7540 case we ran out of FPR save slots. */
7541 for (j = 6; j <= 15; j++)
7542 if (FP_REGNO_P (cfun_gpr_save_slot (j)))
7543 cfun_gpr_save_slot (j) = -1;
7544 break;
36c0bd4f 7545 }
6455a49e 7546 cfun_gpr_save_slot (i) = save_reg_slot++;
5a3fe9b6 7547 }
6455a49e 7548}
5a3fe9b6 7549
6455a49e
AK		 7550/* Set the bits in fpr_bitmap for FPRs which need to be saved due to
7551 stdarg.
7552 This is a helper routine for s390_register_info. */
7bcebb25 7553
6455a49e
AK		 7554static void
7555s390_register_info_stdarg_fpr ()
7556{
7557 int i;
7558 int min_fpr;
7559 int max_fpr;
7560
7561 /* Save the FP argument regs for stdarg. f0, f2 for 31 bit and
7562 f0-f4 for 64 bit. */
7563 if (!cfun->stdarg
7564 || !TARGET_HARD_FLOAT
7565 || !cfun->va_list_fpr_size
7566 || crtl->args.info.fprs >= FP_ARG_NUM_REG)
7567 return;
7568
7569 min_fpr = crtl->args.info.fprs;
7570 max_fpr = min_fpr + cfun->va_list_fpr_size;
7571 if (max_fpr > FP_ARG_NUM_REG)
7572 max_fpr = FP_ARG_NUM_REG;
7573
6455a49e
AK		 7574 for (i = min_fpr; i < max_fpr; i++)
7575 cfun_set_fpr_save (i + FPR0_REGNUM);
7576}
7577
7578/* Reserve the GPR save slots for GPRs which need to be saved due to
7579 stdarg.
7580 This is a helper routine for s390_register_info. */
7581
7582static void
7583s390_register_info_stdarg_gpr ()
7584{
7585 int i;
7586 int min_gpr;
7587 int max_gpr;
7588
7589 if (!cfun->stdarg
7590 || !cfun->va_list_gpr_size
7591 || crtl->args.info.gprs >= GP_ARG_NUM_REG)
7592 return;
7593
7594 min_gpr = crtl->args.info.gprs;
7595 max_gpr = min_gpr + cfun->va_list_gpr_size;
7596 if (max_gpr > GP_ARG_NUM_REG)
7597 max_gpr = GP_ARG_NUM_REG;
7598
7599 for (i = min_gpr; i < max_gpr; i++)
7600 cfun_gpr_save_slot (2 + i) = -1;
7601}
7602
7603/* The GPR and FPR save slots in cfun->machine->frame_layout are set
7604 for registers which need to be saved in function prologue.
7605 This function can be used until the insns emitted for save/restore
7606 of the regs are visible in the RTL stream. */
7607
7608static void
7609s390_register_info ()
7610{
7611 int i, j;
7612 char clobbered_regs[32];
7613
7614 gcc_assert (!epilogue_completed);
7615
7616 if (reload_completed)
7617 /* After reload we rely on our own routine to determine which
7618 registers need saving. */
7619 s390_regs_ever_clobbered (clobbered_regs);
7620 else
7621 /* During reload we use regs_ever_live as a base since reload
7622 does changes in there which we otherwise would not be aware
7623 of. */
7624 for (i = 0; i < 32; i++)
7625 clobbered_regs[i] = df_regs_ever_live_p (i);
7626
7627 for (i = 0; i < 32; i++)
7628 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i];
7629
7630 /* Mark the call-saved FPRs which need to be saved.
7631 This needs to be done before checking the special GPRs since the
7632 stack pointer usage depends on whether high FPRs have to be saved
7633 or not. */
7634 cfun_frame_layout.fpr_bitmap = 0;
7635 cfun_frame_layout.high_fprs = 0;
7636 for (i = FPR0_REGNUM; i <= FPR15_REGNUM; i++)
7637 if (clobbered_regs[i] && !call_really_used_regs[i])
7638 {
7639 cfun_set_fpr_save (i);
7640 if (i >= FPR8_REGNUM)
7641 cfun_frame_layout.high_fprs++;
7642 }
c3cc6b78 7643
b767fc11 7644 if (flag_pic)
f4aa3848 7645 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
6455a49e 7646 |= !!df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
91086990 7647
f4aa3848 7648 clobbered_regs[BASE_REGNUM]
e2df5c1d 7649 |= (cfun->machine->base_reg
6455a49e 7650 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
91086990 7651
6455a49e
AK		 7652 clobbered_regs[HARD_FRAME_POINTER_REGNUM]
7653 |= !!frame_pointer_needed;
7654
7655 /* On pre z900 machines this might take until machine dependent
7656 reorg to decide.
7657 save_return_addr_p will only be set on non-zarch machines so
7658 there is no risk that r14 goes into an FPR instead of a stack
7659 slot. */
7bcebb25 7660 clobbered_regs[RETURN_REGNUM]
416ff32e 7661 |= (!crtl->is_leaf
dc4477f5 7662 || TARGET_TPF_PROFILING
e2df5c1d
UW		 7663 || cfun->machine->split_branches_pending_p
7664 || cfun_frame_layout.save_return_addr_p
6455a49e 7665 || crtl->calls_eh_return);
91086990 7666
7bcebb25 7667 clobbered_regs[STACK_POINTER_REGNUM]
416ff32e 7668 |= (!crtl->is_leaf
e2df5c1d
UW		 7669 || TARGET_TPF_PROFILING
7670 || cfun_save_high_fprs_p
7671 || get_frame_size () > 0
36c0bd4f 7672 || (reload_completed && cfun_frame_layout.frame_size > 0)
6455a49e
AK		 7673 || cfun->calls_alloca);
7674
7675 memset (cfun_frame_layout.gpr_save_slots, 0, 16);
7bcebb25 7676
b767fc11 7677 for (i = 6; i < 16; i++)
6455a49e
AK		 7678 if (clobbered_regs[i])
7679 cfun_gpr_save_slot (i) = -1;
c3cc6b78 7680
6455a49e
AK		 7681 s390_register_info_stdarg_fpr ();
7682 s390_register_info_gprtofpr ();
fb3712f6 7683
6455a49e
AK		 7684 /* First find the range of GPRs to be restored. Vararg regs don't
7685 need to be restored so we do it before assigning slots to the
7686 vararg GPRs. */
7687 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7688 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7689 cfun_frame_layout.first_restore_gpr = (i == 16) ? -1 : i;
7690 cfun_frame_layout.last_restore_gpr = (i == 16) ? -1 : j;
fb3712f6 7691
6455a49e
AK		 7692 /* stdarg functions might need to save GPRs 2 to 6. This might
7693 override the GPR->FPR save decision made above for r6 since
7694 vararg regs must go to the stack. */
7695 s390_register_info_stdarg_gpr ();
f4aa3848 7696
6455a49e
AK		 7697 /* Now the range of GPRs which need saving. */
7698 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7699 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7700 cfun_frame_layout.first_save_gpr = (i == 16) ? -1 : i;
7701 cfun_frame_layout.last_save_gpr = (i == 16) ? -1 : j;
7702}
c3cc6b78 7703
6455a49e
AK		 7704/* This function is called by s390_optimize_prologue in order to get
7705 rid of unnecessary GPR save/restore instructions. The register info
7706 for the GPRs is re-computed and the ranges are re-calculated. */
29a79fcf 7707
6455a49e
AK		 7708static void
7709s390_optimize_register_info ()
7710{
7711 char clobbered_regs[32];
7712 int i, j;
29a79fcf 7713
6455a49e
AK		 7714 gcc_assert (epilogue_completed);
7715 gcc_assert (!cfun->machine->split_branches_pending_p);
b767fc11 7716
6455a49e 7717 s390_regs_ever_clobbered (clobbered_regs);
29a79fcf 7718
6455a49e
AK		 7719 for (i = 0; i < 32; i++)
7720 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i];
29a79fcf 7721
6455a49e
AK		 7722 /* There is still special treatment needed for cases invisible to
7723 s390_regs_ever_clobbered. */
7724 clobbered_regs[RETURN_REGNUM]
7725 |= (TARGET_TPF_PROFILING
7726 /* When expanding builtin_return_addr in ESA mode we do not
7727 know whether r14 will later be needed as scratch reg when
7728 doing branch splitting. So the builtin always accesses the
7729 r14 save slot and we need to stick to the save/restore
7730 decision for r14 even if it turns out that it didn't get
7731 clobbered. */
7732 || cfun_frame_layout.save_return_addr_p
7733 || crtl->calls_eh_return);
7734
7735 memset (cfun_frame_layout.gpr_save_slots, 0, 6);
7736
7737 for (i = 6; i < 16; i++)
7738 if (!clobbered_regs[i])
7739 cfun_gpr_save_slot (i) = 0;
7740
7741 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7742 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7743 cfun_frame_layout.first_restore_gpr = (i == 16) ? -1 : i;
7744 cfun_frame_layout.last_restore_gpr = (i == 16) ? -1 : j;
7745
7746 s390_register_info_stdarg_gpr ();
7747
7748 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7749 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7750 cfun_frame_layout.first_save_gpr = (i == 16) ? -1 : i;
7751 cfun_frame_layout.last_save_gpr = (i == 16) ? -1 : j;
adf39f8f
AK		 7752}
7753
91086990 7754/* Fill cfun->machine with info about frame of current function. */
adf39f8f
AK		 7755
7756static void
91086990 7757s390_frame_info (void)
adf39f8f 7758{
74129172 7759 HOST_WIDE_INT lowest_offset;
adf39f8f 7760
6455a49e
AK		 7761 cfun_frame_layout.first_save_gpr_slot = cfun_frame_layout.first_save_gpr;
7762 cfun_frame_layout.last_save_gpr_slot = cfun_frame_layout.last_save_gpr;
7763
7764 /* The va_arg builtin uses a constant distance of 16 *
7765 UNITS_PER_LONG (r0-r15) to reach the FPRs from the reg_save_area
7766 pointer. So even if we are going to save the stack pointer in an
7767 FPR we need the stack space in order to keep the offsets
7768 correct. */
7769 if (cfun->stdarg && cfun_save_arg_fprs_p)
7770 {
7771 cfun_frame_layout.last_save_gpr_slot = STACK_POINTER_REGNUM;
7772
7773 if (cfun_frame_layout.first_save_gpr_slot == -1)
7774 cfun_frame_layout.first_save_gpr_slot = STACK_POINTER_REGNUM;
7775 }
7776
adf39f8f 7777 cfun_frame_layout.frame_size = get_frame_size ();
adf39f8f 7778 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
c85ce869 7779 fatal_error ("total size of local variables exceeds architecture limit");
f4aa3848 7780
b3d31392 7781 if (!TARGET_PACKED_STACK)
adf39f8f 7782 {
74129172 7783 /* Fixed stack layout. */
adf39f8f 7784 cfun_frame_layout.backchain_offset = 0;
9602b6a1 7785 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
adf39f8f
AK		 7786 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7787 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
fb3712f6 7788 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
9602b6a1 7789 * UNITS_PER_LONG);
adf39f8f 7790 }
74129172 7791 else if (TARGET_BACKCHAIN)
adf39f8f 7792 {
74129172
AK		 7793 /* Kernel stack layout - packed stack, backchain, no float */
7794 gcc_assert (TARGET_SOFT_FLOAT);
adf39f8f 7795 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
9602b6a1 7796 - UNITS_PER_LONG);
74129172
AK		 7797
7798 /* The distance between the backchain and the return address
7799 save slot must not change. So we always need a slot for the
7800 stack pointer which resides in between. */
7801 cfun_frame_layout.last_save_gpr_slot = STACK_POINTER_REGNUM;
7802
f4aa3848 7803 cfun_frame_layout.gprs_offset
74129172 7804 = cfun_frame_layout.backchain_offset - cfun_gprs_save_area_size;
f4aa3848 7805
74129172
AK		 7806 /* FPRs will not be saved. Nevertheless pick sane values to
7807 keep area calculations valid. */
7808 cfun_frame_layout.f0_offset =
7809 cfun_frame_layout.f4_offset =
7810 cfun_frame_layout.f8_offset = cfun_frame_layout.gprs_offset;
adf39f8f 7811 }
74129172 7812 else
adf39f8f 7813 {
e179df83
AK		 7814 int num_fprs;
7815
74129172 7816 /* Packed stack layout without backchain. */
f4aa3848 7817
e179df83
AK		 7818 /* With stdarg FPRs need their dedicated slots. */
7819 num_fprs = (TARGET_64BIT && cfun->stdarg ? 2
7820 : (cfun_fpr_save_p (FPR4_REGNUM) +
7821 cfun_fpr_save_p (FPR6_REGNUM)));
7822 cfun_frame_layout.f4_offset = STACK_POINTER_OFFSET - 8 * num_fprs;
7823
7824 num_fprs = (cfun->stdarg ? 2
7825 : (cfun_fpr_save_p (FPR0_REGNUM)
7826 + cfun_fpr_save_p (FPR2_REGNUM)));
7827 cfun_frame_layout.f0_offset = cfun_frame_layout.f4_offset - 8 * num_fprs;
f4aa3848
AK		 7828
7829 cfun_frame_layout.gprs_offset
adf39f8f 7830 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
74129172
AK		 7831
7832 cfun_frame_layout.f8_offset = (cfun_frame_layout.gprs_offset
7833 - cfun_frame_layout.high_fprs * 8);
adf39f8f
AK		 7834 }
7835
74129172
AK		 7836 if (cfun_save_high_fprs_p)
7837 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7838
7839 if (!crtl->is_leaf)
7840 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7841
7842 /* In the following cases we have to allocate a STACK_POINTER_OFFSET
7843 sized area at the bottom of the stack. This is required also for
7844 leaf functions. When GCC generates a local stack reference it
7845 will always add STACK_POINTER_OFFSET to all these references. */
416ff32e 7846 if (crtl->is_leaf
adf39f8f
AK		 7847 && !TARGET_TPF_PROFILING
7848 && cfun_frame_layout.frame_size == 0
6455a49e 7849 && !cfun->calls_alloca)
adf39f8f
AK		 7850 return;
7851
74129172
AK		 7852 /* Calculate the number of bytes we have used in our own register
7853 save area. With the packed stack layout we can re-use the
7854 remaining bytes for normal stack elements. */
adf39f8f 7855
74129172
AK		 7856 if (TARGET_PACKED_STACK)
7857 lowest_offset = MIN (MIN (cfun_frame_layout.f0_offset,
7858 cfun_frame_layout.f4_offset),
7859 cfun_frame_layout.gprs_offset);
7860 else
7861 lowest_offset = 0;
f4aa3848 7862
74129172
AK		 7863 if (TARGET_BACKCHAIN)
7864 lowest_offset = MIN (lowest_offset, cfun_frame_layout.backchain_offset);
f4aa3848 7865
74129172 7866 cfun_frame_layout.frame_size += STACK_POINTER_OFFSET - lowest_offset;
adf39f8f 7867
74129172
AK		 7868 /* If under 31 bit an odd number of gprs has to be saved we have to
7869 adjust the frame size to sustain 8 byte alignment of stack
7870 frames. */
7871 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7872 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7873 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
4023fb28
UW		 7874}
7875
91086990
UW		 7876/* Generate frame layout. Fills in register and frame data for the current
7877 function in cfun->machine. This routine can be called multiple times;
7878 it will re-do the complete frame layout every time. */
4023fb28 7879
91086990
UW		 7880static void
7881s390_init_frame_layout (void)
9db1d521 7882{
91086990
UW		 7883 HOST_WIDE_INT frame_size;
7884 int base_used;
6455a49e
AK		 7885
7886 gcc_assert (!reload_completed);
b767fc11 7887
91086990
UW		 7888 /* On S/390 machines, we may need to perform branch splitting, which
7889 will require both base and return address register. We have no
7890 choice but to assume we're going to need them until right at the
7891 end of the machine dependent reorg phase. */
7892 if (!TARGET_CPU_ZARCH)
7893 cfun->machine->split_branches_pending_p = true;
7894
7895 do
7896 {
7897 frame_size = cfun_frame_layout.frame_size;
7898
7899 /* Try to predict whether we'll need the base register. */
7900 base_used = cfun->machine->split_branches_pending_p
e3b5732b 7901 || crtl->uses_const_pool
20f04e65
AK		 7902 || (!DISP_IN_RANGE (frame_size)
7903 && !CONST_OK_FOR_K (frame_size));
91086990
UW		 7904
7905 /* Decide which register to use as literal pool base. In small
7906 leaf functions, try to use an unused call-clobbered register
7907 as base register to avoid save/restore overhead. */
7908 if (!base_used)
7909 cfun->machine->base_reg = NULL_RTX;
416ff32e 7910 else if (crtl->is_leaf && !df_regs_ever_live_p (5))
91086990
UW		 7911 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7912 else
7913 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
adf39f8f 7914
6455a49e 7915 s390_register_info ();
91086990
UW		 7916 s390_frame_info ();
7917 }
7918 while (frame_size != cfun_frame_layout.frame_size);
9db1d521
HP		 7919}
7920
5a3fe9b6
AK		 7921/* Remove the FPR clobbers from a tbegin insn if it can be proven that
7922 the TX is nonescaping. A transaction is considered escaping if
7923 there is at least one path from tbegin returning CC0 to the
7924 function exit block without an tend.
7925
7926 The check so far has some limitations:
7927 - only single tbegin/tend BBs are supported
7928 - the first cond jump after tbegin must separate the CC0 path from ~CC0
7929 - when CC is copied to a GPR and the CC0 check is done with the GPR
7930 this is not supported
7931*/
7932
7933static void
7934s390_optimize_nonescaping_tx (void)
7935{
7936 const unsigned int CC0 = 1 << 3;
7937 basic_block tbegin_bb = NULL;
7938 basic_block tend_bb = NULL;
7939 basic_block bb;
775c43d3 7940 rtx_insn *insn;
5a3fe9b6
AK		 7941 bool result = true;
7942 int bb_index;
775c43d3 7943 rtx_insn *tbegin_insn = NULL;
5a3fe9b6
AK		 7944
7945 if (!cfun->machine->tbegin_p)
7946 return;
7947
0cae8d31 7948 for (bb_index = 0; bb_index < n_basic_blocks_for_fn (cfun); bb_index++)
5a3fe9b6 7949 {
06e28de2 7950 bb = BASIC_BLOCK_FOR_FN (cfun, bb_index);
5a3fe9b6 7951
2561451d
AK		 7952 if (!bb)
7953 continue;
7954
5a3fe9b6
AK		 7955 FOR_BB_INSNS (bb, insn)
7956 {
7957 rtx ite, cc, pat, target;
7958 unsigned HOST_WIDE_INT mask;
7959
7960 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
7961 continue;
7962
7963 pat = PATTERN (insn);
7964
7965 if (GET_CODE (pat) == PARALLEL)
7966 pat = XVECEXP (pat, 0, 0);
7967
7968 if (GET_CODE (pat) != SET
7969 || GET_CODE (SET_SRC (pat)) != UNSPEC_VOLATILE)
7970 continue;
7971
7972 if (XINT (SET_SRC (pat), 1) == UNSPECV_TBEGIN)
7973 {
b32d5189 7974 rtx_insn *tmp;
5a3fe9b6
AK		 7975
7976 tbegin_insn = insn;
7977
7978 /* Just return if the tbegin doesn't have clobbers. */
7979 if (GET_CODE (PATTERN (insn)) != PARALLEL)
7980 return;
7981
7982 if (tbegin_bb != NULL)
7983 return;
7984
7985 /* Find the next conditional jump. */
7986 for (tmp = NEXT_INSN (insn);
7987 tmp != NULL_RTX;
7988 tmp = NEXT_INSN (tmp))
7989 {
7990 if (reg_set_p (gen_rtx_REG (CCmode, CC_REGNUM), tmp))
7991 return;
7992 if (!JUMP_P (tmp))
7993 continue;
7994
7995 ite = SET_SRC (PATTERN (tmp));
7996 if (GET_CODE (ite) != IF_THEN_ELSE)
7997 continue;
7998
7999 cc = XEXP (XEXP (ite, 0), 0);
8000 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc))
8001 || GET_MODE (cc) != CCRAWmode
8002 || GET_CODE (XEXP (XEXP (ite, 0), 1)) != CONST_INT)
8003 return;
8004
8005 if (bb->succs->length () != 2)
8006 return;
8007
8008 mask = INTVAL (XEXP (XEXP (ite, 0), 1));
8009 if (GET_CODE (XEXP (ite, 0)) == NE)
8010 mask ^= 0xf;
8011
8012 if (mask == CC0)
8013 target = XEXP (ite, 1);
8014 else if (mask == (CC0 ^ 0xf))
8015 target = XEXP (ite, 2);
8016 else
8017 return;
8018
8019 {
8020 edge_iterator ei;
8021 edge e1, e2;
8022
8023 ei = ei_start (bb->succs);
8024 e1 = ei_safe_edge (ei);
8025 ei_next (&ei);
8026 e2 = ei_safe_edge (ei);
8027
8028 if (e2->flags & EDGE_FALLTHRU)
8029 {
8030 e2 = e1;
8031 e1 = ei_safe_edge (ei);
8032 }
8033
8034 if (!(e1->flags & EDGE_FALLTHRU))
8035 return;
8036
8037 tbegin_bb = (target == pc_rtx) ? e1->dest : e2->dest;
8038 }
8039 if (tmp == BB_END (bb))
8040 break;
8041 }
8042 }
8043
8044 if (XINT (SET_SRC (pat), 1) == UNSPECV_TEND)
8045 {
8046 if (tend_bb != NULL)
8047 return;
8048 tend_bb = bb;
8049 }
8050 }
8051 }
8052
8053 /* Either we successfully remove the FPR clobbers here or we are not
8054 able to do anything for this TX. Both cases don't qualify for
8055 another look. */
8056 cfun->machine->tbegin_p = false;
8057
8058 if (tbegin_bb == NULL || tend_bb == NULL)
8059 return;
8060
8061 calculate_dominance_info (CDI_POST_DOMINATORS);
8062 result = dominated_by_p (CDI_POST_DOMINATORS, tbegin_bb, tend_bb);
8063 free_dominance_info (CDI_POST_DOMINATORS);
8064
8065 if (!result)
8066 return;
8067
2561451d
AK		 8068 PATTERN (tbegin_insn) = gen_rtx_PARALLEL (VOIDmode,
8069 gen_rtvec (2,
8070 XVECEXP (PATTERN (tbegin_insn), 0, 0),
8071 XVECEXP (PATTERN (tbegin_insn), 0, 1)));
5a3fe9b6
AK		 8072 INSN_CODE (tbegin_insn) = -1;
8073 df_insn_rescan (tbegin_insn);
8074
8075 return;
8076}
8077
74aa8b4b
AK		 8078/* Return true if it is legal to put a value with MODE into REGNO. */
8079
8080bool
ef4bddc2 8081s390_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
74aa8b4b
AK		 8082{
8083 switch (REGNO_REG_CLASS (regno))
8084 {
8085 case FP_REGS:
8086 if (REGNO_PAIR_OK (regno, mode))
8087 {
8088 if (mode == SImode || mode == DImode)
8089 return true;
8090
8091 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
8092 return true;
8093 }
8094 break;
8095 case ADDR_REGS:
8096 if (FRAME_REGNO_P (regno) && mode == Pmode)
8097 return true;
8098
8099 /* fallthrough */
8100 case GENERAL_REGS:
8101 if (REGNO_PAIR_OK (regno, mode))
8102 {
9602b6a1 8103 if (TARGET_ZARCH
4dc19cc0 8104 || (mode != TFmode && mode != TCmode && mode != TDmode))
74aa8b4b 8105 return true;
f4aa3848 8106 }
74aa8b4b
AK		 8107 break;
8108 case CC_REGS:
8109 if (GET_MODE_CLASS (mode) == MODE_CC)
8110 return true;
8111 break;
8112 case ACCESS_REGS:
8113 if (REGNO_PAIR_OK (regno, mode))
8114 {
8115 if (mode == SImode || mode == Pmode)
8116 return true;
8117 }
8118 break;
8119 default:
8120 return false;
8121 }
f4aa3848 8122
74aa8b4b
AK		 8123 return false;
8124}
8125
7633f08e
UW		 8126/* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
8127
8128bool
8129s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
8130{
8131 /* Once we've decided upon a register to use as base register, it must
8132 no longer be used for any other purpose. */
8133 if (cfun->machine->base_reg)
8134 if (REGNO (cfun->machine->base_reg) == old_reg
8135 || REGNO (cfun->machine->base_reg) == new_reg)
8136 return false;
8137
6455a49e
AK		 8138 /* Prevent regrename from using call-saved regs which haven't
8139 actually been saved. This is necessary since regrename assumes
8140 the backend save/restore decisions are based on
8141 df_regs_ever_live. Since we have our own routine we have to tell
8142 regrename manually about it. */
8143 if (GENERAL_REGNO_P (new_reg)
8144 && !call_really_used_regs[new_reg]
8145 && cfun_gpr_save_slot (new_reg) == 0)
8146 return false;
8147
8148 return true;
8149}
8150
8151/* Return nonzero if register REGNO can be used as a scratch register
8152 in peephole2. */
8153
8154static bool
8155s390_hard_regno_scratch_ok (unsigned int regno)
8156{
8157 /* See s390_hard_regno_rename_ok. */
8158 if (GENERAL_REGNO_P (regno)
8159 && !call_really_used_regs[regno]
8160 && cfun_gpr_save_slot (regno) == 0)
8161 return false;
8162
7633f08e
UW		 8163 return true;
8164}
8165
74aa8b4b 8166/* Maximum number of registers to represent a value of mode MODE
0a2aaacc 8167 in a register of class RCLASS. */
74aa8b4b 8168
c4100a35 8169int
ef4bddc2 8170s390_class_max_nregs (enum reg_class rclass, machine_mode mode)
74aa8b4b 8171{
0a2aaacc 8172 switch (rclass)
74aa8b4b
AK		 8173 {
8174 case FP_REGS:
8175 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
8176 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
8177 else
8178 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
8179 case ACCESS_REGS:
8180 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
8181 default:
8182 break;
8183 }
8184 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8185}
8186
3597e113
VM		 8187/* Return true if we use LRA instead of reload pass. */
8188static bool
8189s390_lra_p (void)
8190{
8191 return s390_lra_flag;
8192}
8193
91086990
UW		 8194/* Return true if register FROM can be eliminated via register TO. */
8195
7b5cbb57
AS		 8196static bool
8197s390_can_eliminate (const int from, const int to)
91086990 8198{
7633f08e
UW		 8199 /* On zSeries machines, we have not marked the base register as fixed.
8200 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
8201 If a function requires the base register, we say here that this
8202 elimination cannot be performed. This will cause reload to free
8203 up the base register (as if it were fixed). On the other hand,
8204 if the current function does *not* require the base register, we
8205 say here the elimination succeeds, which in turn allows reload
8206 to allocate the base register for any other purpose. */
8207 if (from == BASE_REGNUM && to == BASE_REGNUM)
8208 {
8209 if (TARGET_CPU_ZARCH)
8210 {
8211 s390_init_frame_layout ();
8212 return cfun->machine->base_reg == NULL_RTX;
8213 }
8214
8215 return false;
8216 }
8217
8218 /* Everything else must point into the stack frame. */
91086990
UW		 8219 gcc_assert (to == STACK_POINTER_REGNUM
8220 || to == HARD_FRAME_POINTER_REGNUM);
8221
8222 gcc_assert (from == FRAME_POINTER_REGNUM
8223 || from == ARG_POINTER_REGNUM
8224 || from == RETURN_ADDRESS_POINTER_REGNUM);
8225
8226 /* Make sure we actually saved the return address. */
8227 if (from == RETURN_ADDRESS_POINTER_REGNUM)
e3b5732b
JH		 8228 if (!crtl->calls_eh_return
8229 && !cfun->stdarg
91086990
UW		 8230 && !cfun_frame_layout.save_return_addr_p)
8231 return false;
8232
8233 return true;
8234}
8235
8236/* Return offset between register FROM and TO initially after prolog. */
a38e09bc
AK		 8237
8238HOST_WIDE_INT
91086990 8239s390_initial_elimination_offset (int from, int to)
a38e09bc 8240{
91086990 8241 HOST_WIDE_INT offset;
a38e09bc 8242
91086990
UW		 8243 /* ??? Why are we called for non-eliminable pairs? */
8244 if (!s390_can_eliminate (from, to))
8245 return 0;
8246
8247 switch (from)
8248 {
8249 case FRAME_POINTER_REGNUM:
f4aa3848 8250 offset = (get_frame_size()
63296cb1 8251 + STACK_POINTER_OFFSET
38173d38 8252 + crtl->outgoing_args_size);
91086990 8253 break;
adf39f8f 8254
91086990
UW		 8255 case ARG_POINTER_REGNUM:
8256 s390_init_frame_layout ();
8257 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
8258 break;
8259
8260 case RETURN_ADDRESS_POINTER_REGNUM:
8261 s390_init_frame_layout ();
6455a49e
AK		 8262
8263 if (cfun_frame_layout.first_save_gpr_slot == -1)
8264 {
8265 /* If it turns out that for stdarg nothing went into the reg
8266 save area we also do not need the return address
8267 pointer. */
8268 if (cfun->stdarg && !cfun_save_arg_fprs_p)
8269 return 0;
8270
8271 gcc_unreachable ();
8272 }
8273
8274 /* In order to make the following work it is not necessary for
8275 r14 to have a save slot. It is sufficient if one other GPR
8276 got one. Since the GPRs are always stored without gaps we
8277 are able to calculate where the r14 save slot would
8278 reside. */
8279 offset = (cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset +
8280 (RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot) *
8281 UNITS_PER_LONG);
91086990
UW		 8282 break;
8283
7633f08e
UW		 8284 case BASE_REGNUM:
8285 offset = 0;
8286 break;
8287
91086990
UW		 8288 default:
8289 gcc_unreachable ();
8290 }
8291
8292 return offset;
a38e09bc
AK		 8293}
8294
4023fb28 8295/* Emit insn to save fpr REGNUM at offset OFFSET relative
c7453384 8296 to register BASE. Return generated insn. */
994fe660 8297
9db1d521 8298static rtx
9c808aad 8299save_fpr (rtx base, int offset, int regnum)
9db1d521 8300{
4023fb28 8301 rtx addr;
0a81f074 8302 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
dcc9eb26
AK		 8303
8304 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
8305 set_mem_alias_set (addr, get_varargs_alias_set ());
8306 else
8307 set_mem_alias_set (addr, get_frame_alias_set ());
9db1d521 8308
4023fb28
UW		 8309 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
8310}
9db1d521 8311
4023fb28 8312/* Emit insn to restore fpr REGNUM from offset OFFSET relative
c7453384 8313 to register BASE. Return generated insn. */
9db1d521 8314
4023fb28 8315static rtx
9c808aad 8316restore_fpr (rtx base, int offset, int regnum)
4023fb28
UW		 8317{
8318 rtx addr;
0a81f074 8319 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
dcc9eb26 8320 set_mem_alias_set (addr, get_frame_alias_set ());
9db1d521 8321
4023fb28 8322 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
9db1d521
HP		 8323}
8324
75707b28
JJ		 8325/* Return true if REGNO is a global register, but not one
8326 of the special ones that need to be saved/restored in anyway. */
8327
8328static inline bool
8329global_not_special_regno_p (int regno)
8330{
8331 return (global_regs[regno]
8332 /* These registers are special and need to be
8333 restored in any case. */
8334 && !(regno == STACK_POINTER_REGNUM
8335 || regno == RETURN_REGNUM
8336 || regno == BASE_REGNUM
8337 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
8338}
8339
c3cc6b78 8340/* Generate insn to save registers FIRST to LAST into
c7453384 8341 the register save area located at offset OFFSET
c3cc6b78 8342 relative to register BASE. */
9db1d521 8343
c3cc6b78 8344static rtx
9c808aad 8345save_gprs (rtx base, int offset, int first, int last)
9db1d521 8346{
c3cc6b78
UW		 8347 rtx addr, insn, note;
8348 int i;
8349
0a81f074 8350 addr = plus_constant (Pmode, base, offset);
c3cc6b78 8351 addr = gen_rtx_MEM (Pmode, addr);
dcc9eb26
AK		 8352
8353 set_mem_alias_set (addr, get_frame_alias_set ());
c3cc6b78
UW		 8354
8355 /* Special-case single register. */
8356 if (first == last)
8357 {
8358 if (TARGET_64BIT)
8359 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
8360 else
8361 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
8362
75707b28
JJ		 8363 if (!global_not_special_regno_p (first))
8364 RTX_FRAME_RELATED_P (insn) = 1;
c3cc6b78
UW		 8365 return insn;
8366 }
8367
8368
8369 insn = gen_store_multiple (addr,
8370 gen_rtx_REG (Pmode, first),
8371 GEN_INT (last - first + 1));
8372
e3b5732b 8373 if (first <= 6 && cfun->stdarg)
dcc9eb26
AK		 8374 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8375 {
8376 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
f4aa3848 8377
dcc9eb26
AK		 8378 if (first + i <= 6)
8379 set_mem_alias_set (mem, get_varargs_alias_set ());
8380 }
c3cc6b78
UW		 8381
8382 /* We need to set the FRAME_RELATED flag on all SETs
8383 inside the store-multiple pattern.
8384
8385 However, we must not emit DWARF records for registers 2..5
c7453384 8386 if they are stored for use by variable arguments ...
c3cc6b78 8387
a4d05547 8388 ??? Unfortunately, it is not enough to simply not the
c3cc6b78
UW		 8389 FRAME_RELATED flags for those SETs, because the first SET
8390 of the PARALLEL is always treated as if it had the flag
8391 set, even if it does not. Therefore we emit a new pattern
8392 without those registers as REG_FRAME_RELATED_EXPR note. */
8393
75707b28 8394 if (first >= 6 && !global_not_special_regno_p (first))
c3cc6b78
UW		 8395 {
8396 rtx pat = PATTERN (insn);
8397
8398 for (i = 0; i < XVECLEN (pat, 0); i++)
75707b28
JJ		 8399 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
8400 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
8401 0, i)))))
c3cc6b78
UW		 8402 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
8403
8404 RTX_FRAME_RELATED_P (insn) = 1;
8405 }
8406 else if (last >= 6)
8407 {
75707b28
JJ		 8408 int start;
8409
8410 for (start = first >= 6 ? first : 6; start <= last; start++)
8411 if (!global_not_special_regno_p (start))
8412 break;
8413
8414 if (start > last)
8415 return insn;
8416
0a81f074
RS		 8417 addr = plus_constant (Pmode, base,
8418 offset + (start - first) * UNITS_PER_LONG);
6455a49e
AK		 8419
8420 if (start == last)
8421 {
8422 if (TARGET_64BIT)
8423 note = gen_movdi (gen_rtx_MEM (Pmode, addr),
8424 gen_rtx_REG (Pmode, start));
8425 else
8426 note = gen_movsi (gen_rtx_MEM (Pmode, addr),
8427 gen_rtx_REG (Pmode, start));
8428 note = PATTERN (note);
8429
8430 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
8431 RTX_FRAME_RELATED_P (insn) = 1;
8432
8433 return insn;
8434 }
8435
c7453384 8436 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
75707b28
JJ		 8437 gen_rtx_REG (Pmode, start),
8438 GEN_INT (last - start + 1));
c3cc6b78
UW		 8439 note = PATTERN (note);
8440
bbbbb16a 8441 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
c3cc6b78
UW		 8442
8443 for (i = 0; i < XVECLEN (note, 0); i++)
75707b28
JJ		 8444 if (GET_CODE (XVECEXP (note, 0, i)) == SET
8445 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
8446 0, i)))))
c3cc6b78
UW		 8447 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
8448
8449 RTX_FRAME_RELATED_P (insn) = 1;
8450 }
8451
8452 return insn;
4023fb28 8453}
9db1d521 8454
c3cc6b78 8455/* Generate insn to restore registers FIRST to LAST from
c7453384 8456 the register save area located at offset OFFSET
c3cc6b78 8457 relative to register BASE. */
9db1d521 8458
c3cc6b78 8459static rtx
9c808aad 8460restore_gprs (rtx base, int offset, int first, int last)
4023fb28 8461{
c3cc6b78
UW		 8462 rtx addr, insn;
8463
0a81f074 8464 addr = plus_constant (Pmode, base, offset);
c3cc6b78 8465 addr = gen_rtx_MEM (Pmode, addr);
dcc9eb26 8466 set_mem_alias_set (addr, get_frame_alias_set ());
c3cc6b78
UW		 8467
8468 /* Special-case single register. */
8469 if (first == last)
8470 {
8471 if (TARGET_64BIT)
8472 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
8473 else
8474 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
8475
6455a49e 8476 RTX_FRAME_RELATED_P (insn) = 1;
c3cc6b78
UW		 8477 return insn;
8478 }
8479
8480 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
8481 addr,
8482 GEN_INT (last - first + 1));
6455a49e 8483 RTX_FRAME_RELATED_P (insn) = 1;
c3cc6b78 8484 return insn;
4023fb28 8485}
9db1d521 8486
585539a1 8487/* Return insn sequence to load the GOT register. */
fd7643fb
UW		 8488
8489static GTY(()) rtx got_symbol;
775c43d3 8490rtx_insn *
585539a1 8491s390_load_got (void)
fd7643fb 8492{
775c43d3 8493 rtx_insn *insns;
585539a1 8494
68c0ef75
AK		 8495 /* We cannot use pic_offset_table_rtx here since we use this
8496 function also for non-pic if __tls_get_offset is called and in
8497 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
8498 aren't usable. */
8499 rtx got_rtx = gen_rtx_REG (Pmode, 12);
8500
fd7643fb
UW		 8501 if (!got_symbol)
8502 {
8503 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8504 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
8505 }
8506
585539a1
UW		 8507 start_sequence ();
8508
9e8327e3 8509 if (TARGET_CPU_ZARCH)
fd7643fb 8510 {
68c0ef75 8511 emit_move_insn (got_rtx, got_symbol);
fd7643fb
UW		 8512 }
8513 else
8514 {
585539a1 8515 rtx offset;
fd7643fb 8516
c7453384 8517 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
fd7643fb
UW		 8518 UNSPEC_LTREL_OFFSET);
8519 offset = gen_rtx_CONST (Pmode, offset);
8520 offset = force_const_mem (Pmode, offset);
8521
68c0ef75 8522 emit_move_insn (got_rtx, offset);
fd7643fb 8523
c7453384 8524 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
fd7643fb 8525 UNSPEC_LTREL_BASE);
68c0ef75 8526 offset = gen_rtx_PLUS (Pmode, got_rtx, offset);
fd7643fb 8527
68c0ef75 8528 emit_move_insn (got_rtx, offset);
fd7643fb 8529 }
585539a1
UW		 8530
8531 insns = get_insns ();
8532 end_sequence ();
8533 return insns;
fd7643fb
UW		 8534}
8535
12959abe
AK		 8536/* This ties together stack memory (MEM with an alias set of frame_alias_set)
8537 and the change to the stack pointer. */
8538
8539static void
8540s390_emit_stack_tie (void)
8541{
8542 rtx mem = gen_frame_mem (BLKmode,
8543 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
8544
8545 emit_insn (gen_stack_tie (mem));
8546}
8547
6455a49e
AK		 8548/* Copy GPRS into FPR save slots. */
8549
8550static void
8551s390_save_gprs_to_fprs (void)
8552{
8553 int i;
8554
8555 if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf)
8556 return;
8557
8558 for (i = 6; i < 16; i++)
8559 {
8560 if (FP_REGNO_P (cfun_gpr_save_slot (i)))
8561 {
775c43d3 8562 rtx_insn *insn =
6455a49e
AK		 8563 emit_move_insn (gen_rtx_REG (DImode, cfun_gpr_save_slot (i)),
8564 gen_rtx_REG (DImode, i));
8565 RTX_FRAME_RELATED_P (insn) = 1;
8566 }
8567 }
8568}
8569
8570/* Restore GPRs from FPR save slots. */
8571
8572static void
8573s390_restore_gprs_from_fprs (void)
8574{
8575 int i;
8576
8577 if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf)
8578 return;
8579
8580 for (i = 6; i < 16; i++)
8581 {
8582 if (FP_REGNO_P (cfun_gpr_save_slot (i)))
8583 {
775c43d3 8584 rtx_insn *insn =
6455a49e
AK		 8585 emit_move_insn (gen_rtx_REG (DImode, i),
8586 gen_rtx_REG (DImode, cfun_gpr_save_slot (i)));
8587 df_set_regs_ever_live (i, true);
0621cf3c
RS		 8588 add_reg_note (insn, REG_CFA_RESTORE, gen_rtx_REG (DImode, i));
8589 if (i == STACK_POINTER_REGNUM)
8590 add_reg_note (insn, REG_CFA_DEF_CFA,
8591 plus_constant (Pmode, stack_pointer_rtx,
8592 STACK_POINTER_OFFSET));
6455a49e
AK		 8593 RTX_FRAME_RELATED_P (insn) = 1;
8594 }
8595 }
8596}
8597
9db1d521 8598
4099494d
RS		 8599/* A pass run immediately before shrink-wrapping and prologue and epilogue
8600 generation. */
8601
4099494d
RS		 8602namespace {
8603
8604const pass_data pass_data_s390_early_mach =
8605{
8606 RTL_PASS, /* type */
8607 "early_mach", /* name */
8608 OPTGROUP_NONE, /* optinfo_flags */
4099494d
RS		 8609 TV_MACH_DEP, /* tv_id */
8610 0, /* properties_required */
8611 0, /* properties_provided */
8612 0, /* properties_destroyed */
8613 0, /* todo_flags_start */
3bea341f 8614 ( TODO_df_verify | TODO_df_finish ), /* todo_flags_finish */
4099494d 8615};
585539a1 8616
4099494d
RS		 8617class pass_s390_early_mach : public rtl_opt_pass
8618{
8619public:
8620 pass_s390_early_mach (gcc::context *ctxt)
8621 : rtl_opt_pass (pass_data_s390_early_mach, ctxt)
8622 {}
8623
8624 /* opt_pass methods: */
be55bfe6 8625 virtual unsigned int execute (function *);
4099494d
RS		 8626
8627}; // class pass_s390_early_mach
8628
be55bfe6
TS		 8629unsigned int
8630pass_s390_early_mach::execute (function *fun)
8631{
775c43d3 8632 rtx_insn *insn;
be55bfe6
TS		 8633
8634 /* Try to get rid of the FPR clobbers. */
8635 s390_optimize_nonescaping_tx ();
8636
8637 /* Re-compute register info. */
8638 s390_register_info ();
8639
8640 /* If we're using a base register, ensure that it is always valid for
8641 the first non-prologue instruction. */
8642 if (fun->machine->base_reg)
8643 emit_insn_at_entry (gen_main_pool (fun->machine->base_reg));
8644
8645 /* Annotate all constant pool references to let the scheduler know
8646 they implicitly use the base register. */
8647 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8648 if (INSN_P (insn))
8649 {
8650 annotate_constant_pool_refs (&PATTERN (insn));
8651 df_insn_rescan (insn);
8652 }
8653 return 0;
8654}
8655
4099494d
RS		 8656} // anon namespace
8657
8658/* Expand the prologue into a bunch of separate insns. */
8659
8660void
8661s390_emit_prologue (void)
8662{
8663 rtx insn, addr;
8664 rtx temp_reg;
8665 int i;
8666 int offset;
8667 int next_fpr = 0;
585539a1 8668
c7453384
EC		 8669 /* Choose best register to use for temp use within prologue.
8670 See below for why TPF must use the register 1. */
8671
f4aa3848 8672 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
416ff32e 8673 && !crtl->is_leaf
7bcebb25 8674 && !TARGET_TPF_PROFILING)
4023fb28 8675 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
9db1d521 8676 else
4023fb28 8677 temp_reg = gen_rtx_REG (Pmode, 1);
9db1d521 8678
6455a49e
AK		 8679 s390_save_gprs_to_fprs ();
8680
4023fb28 8681 /* Save call saved gprs. */
adf39f8f 8682 if (cfun_frame_layout.first_save_gpr != -1)
2790879f 8683 {
f4aa3848
AK		 8684 insn = save_gprs (stack_pointer_rtx,
8685 cfun_frame_layout.gprs_offset +
9602b6a1 8686 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
fb3712f6 8687 - cfun_frame_layout.first_save_gpr_slot),
f4aa3848 8688 cfun_frame_layout.first_save_gpr,
2790879f
AK		 8689 cfun_frame_layout.last_save_gpr);
8690 emit_insn (insn);
8691 }
4023fb28 8692
5af2f3d3 8693 /* Dummy insn to mark literal pool slot. */
c7453384 8694
91086990
UW		 8695 if (cfun->machine->base_reg)
8696 emit_insn (gen_main_pool (cfun->machine->base_reg));
c7453384 8697
adf39f8f 8698 offset = cfun_frame_layout.f0_offset;
4023fb28 8699
adf39f8f 8700 /* Save f0 and f2. */
2cf4c39e 8701 for (i = FPR0_REGNUM; i <= FPR0_REGNUM + 1; i++)
adf39f8f 8702 {
b89b22fc 8703 if (cfun_fpr_save_p (i))
adf39f8f 8704 {
b89b22fc 8705 save_fpr (stack_pointer_rtx, offset, i);
adf39f8f
AK		 8706 offset += 8;
8707 }
e179df83
AK		 8708 else if (!TARGET_PACKED_STACK || cfun->stdarg)
8709 offset += 8;
adf39f8f 8710 }
9db1d521 8711
adf39f8f
AK		 8712 /* Save f4 and f6. */
8713 offset = cfun_frame_layout.f4_offset;
2cf4c39e 8714 for (i = FPR4_REGNUM; i <= FPR4_REGNUM + 1; i++)
adf39f8f 8715 {
b89b22fc 8716 if (cfun_fpr_save_p (i))
4023fb28 8717 {
b89b22fc 8718 insn = save_fpr (stack_pointer_rtx, offset, i);
adf39f8f
AK		 8719 offset += 8;
8720
e179df83
AK		 8721 /* If f4 and f6 are call clobbered they are saved due to
8722 stdargs and therefore are not frame related. */
b89b22fc 8723 if (!call_really_used_regs[i])
adf39f8f 8724 RTX_FRAME_RELATED_P (insn) = 1;
4023fb28 8725 }
e179df83 8726 else if (!TARGET_PACKED_STACK || call_really_used_regs[i])
adf39f8f
AK		 8727 offset += 8;
8728 }
8729
b3d31392 8730 if (TARGET_PACKED_STACK
adf39f8f
AK		 8731 && cfun_save_high_fprs_p
8732 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
8733 {
8734 offset = (cfun_frame_layout.f8_offset
8735 + (cfun_frame_layout.high_fprs - 1) * 8);
8736
2cf4c39e 8737 for (i = FPR15_REGNUM; i >= FPR8_REGNUM && offset >= 0; i--)
b89b22fc 8738 if (cfun_fpr_save_p (i))
adf39f8f 8739 {
b89b22fc 8740 insn = save_fpr (stack_pointer_rtx, offset, i);
f4aa3848 8741
adf39f8f
AK		 8742 RTX_FRAME_RELATED_P (insn) = 1;
8743 offset -= 8;
8744 }
8745 if (offset >= cfun_frame_layout.f8_offset)
b89b22fc 8746 next_fpr = i;
adf39f8f 8747 }
f4aa3848 8748
b3d31392 8749 if (!TARGET_PACKED_STACK)
2cf4c39e 8750 next_fpr = cfun_save_high_fprs_p ? FPR15_REGNUM : 0;
9db1d521 8751
a11e0df4 8752 if (flag_stack_usage_info)
5c779305
AK		 8753 current_function_static_stack_size = cfun_frame_layout.frame_size;
8754
4023fb28 8755 /* Decrement stack pointer. */
9db1d521 8756
adf39f8f 8757 if (cfun_frame_layout.frame_size > 0)
4023fb28 8758 {
adf39f8f 8759 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
bbbbb16a 8760 rtx real_frame_off;
9db1d521 8761
d75f90f1
AK		 8762 if (s390_stack_size)
8763 {
690e7b63 8764 HOST_WIDE_INT stack_guard;
d75f90f1 8765
690e7b63
AK		 8766 if (s390_stack_guard)
8767 stack_guard = s390_stack_guard;
d75f90f1 8768 else
690e7b63
AK		 8769 {
8770 /* If no value for stack guard is provided the smallest power of 2
8771 larger than the current frame size is chosen. */
8772 stack_guard = 1;
8773 while (stack_guard < cfun_frame_layout.frame_size)
8774 stack_guard <<= 1;
8775 }
d75f90f1 8776
690e7b63
AK		 8777 if (cfun_frame_layout.frame_size >= s390_stack_size)
8778 {
cabbe12a 8779 warning (0, "frame size of function %qs is %wd"
690e7b63 8780 " bytes exceeding user provided stack limit of "
cabbe12a 8781 "%d bytes. "
690e7b63
AK		 8782 "An unconditional trap is added.",
8783 current_function_name(), cfun_frame_layout.frame_size,
8784 s390_stack_size);
8785 emit_insn (gen_trap ());
8786 }
8787 else
8788 {
a3e7e012
AK		 8789 /* stack_guard has to be smaller than s390_stack_size.
8790 Otherwise we would emit an AND with zero which would
8791 not match the test under mask pattern. */
8792 if (stack_guard >= s390_stack_size)
8793 {
f137aa63 8794 warning (0, "frame size of function %qs is %wd"
a3e7e012
AK		 8795 " bytes which is more than half the stack size. "
8796 "The dynamic check would not be reliable. "
8797 "No check emitted for this function.",
8798 current_function_name(),
8799 cfun_frame_layout.frame_size);
8800 }
690e7b63 8801 else
a3e7e012
AK		 8802 {
8803 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
8804 & ~(stack_guard - 1));
8805
8806 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
8807 GEN_INT (stack_check_mask));
8808 if (TARGET_64BIT)
8809 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
8810 t, const0_rtx),
8811 t, const0_rtx, const0_rtx));
8812 else
8813 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
8814 t, const0_rtx),
8815 t, const0_rtx, const0_rtx));
8816 }
690e7b63 8817 }
d75f90f1
AK		 8818 }
8819
f4aa3848 8820 if (s390_warn_framesize > 0
d75f90f1 8821 && cfun_frame_layout.frame_size >= s390_warn_framesize)
f137aa63 8822 warning (0, "frame size of %qs is %wd bytes",
d75f90f1
AK		 8823 current_function_name (), cfun_frame_layout.frame_size);
8824
8825 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
d4ee4d25 8826 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
d75f90f1 8827
4023fb28 8828 /* Save incoming stack pointer into temp reg. */
66480e91 8829 if (TARGET_BACKCHAIN || next_fpr)
adf39f8f 8830 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
c7453384 8831
fae778eb 8832 /* Subtract frame size from stack pointer. */
4023fb28 8833
d3632d41
UW		 8834 if (DISP_IN_RANGE (INTVAL (frame_off)))
8835 {
c7453384 8836 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
f4aa3848 8837 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
9c808aad 8838 frame_off));
d3632d41
UW		 8839 insn = emit_insn (insn);
8840 }
8841 else
8842 {
b5c67a49 8843 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
d3632d41
UW		 8844 frame_off = force_const_mem (Pmode, frame_off);
8845
8846 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
585539a1 8847 annotate_constant_pool_refs (&PATTERN (insn));
d3632d41 8848 }
4023fb28 8849
4023fb28 8850 RTX_FRAME_RELATED_P (insn) = 1;
bbbbb16a
ILT		 8851 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8852 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8853 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8854 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8855 real_frame_off)));
4023fb28
UW		 8856
8857 /* Set backchain. */
c7453384 8858
66480e91 8859 if (TARGET_BACKCHAIN)
9db1d521 8860 {
adf39f8f 8861 if (cfun_frame_layout.backchain_offset)
f4aa3848 8862 addr = gen_rtx_MEM (Pmode,
0a81f074 8863 plus_constant (Pmode, stack_pointer_rtx,
adf39f8f
AK		 8864 cfun_frame_layout.backchain_offset));
8865 else
f4aa3848 8866 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
dcc9eb26 8867 set_mem_alias_set (addr, get_frame_alias_set ());
4023fb28 8868 insn = emit_insn (gen_move_insn (addr, temp_reg));
9db1d521 8869 }
7d798969 8870
8f4f502f 8871 /* If we support non-call exceptions (e.g. for Java),
7d798969
UW		 8872 we need to make sure the backchain pointer is set up
8873 before any possibly trapping memory access. */
8f4f502f 8874 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
7d798969
UW		 8875 {
8876 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
c41c1387 8877 emit_clobber (addr);
7d798969 8878 }
4023fb28 8879 }
9db1d521 8880
4023fb28 8881 /* Save fprs 8 - 15 (64 bit ABI). */
c7453384 8882
adf39f8f 8883 if (cfun_save_high_fprs_p && next_fpr)
4023fb28 8884 {
12959abe
AK		 8885 /* If the stack might be accessed through a different register
8886 we have to make sure that the stack pointer decrement is not
8887 moved below the use of the stack slots. */
8888 s390_emit_stack_tie ();
8889
f4aa3848 8890 insn = emit_insn (gen_add2_insn (temp_reg,
adf39f8f
AK		 8891 GEN_INT (cfun_frame_layout.f8_offset)));
8892
8893 offset = 0;
9db1d521 8894
2cf4c39e 8895 for (i = FPR8_REGNUM; i <= next_fpr; i++)
b89b22fc 8896 if (cfun_fpr_save_p (i))
4023fb28 8897 {
0a81f074 8898 rtx addr = plus_constant (Pmode, stack_pointer_rtx,
adf39f8f
AK		 8899 cfun_frame_layout.frame_size
8900 + cfun_frame_layout.f8_offset
8901 + offset);
f4aa3848 8902
adf39f8f
AK		 8903 insn = save_fpr (temp_reg, offset, i);
8904 offset += 8;
4023fb28 8905 RTX_FRAME_RELATED_P (insn) = 1;
bbbbb16a
ILT		 8906 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8907 gen_rtx_SET (VOIDmode,
8908 gen_rtx_MEM (DFmode, addr),
8909 gen_rtx_REG (DFmode, i)));
4023fb28
UW		 8910 }
8911 }
c7453384 8912
4023fb28 8913 /* Set frame pointer, if needed. */
c7453384 8914
29742ba4 8915 if (frame_pointer_needed)
4023fb28
UW		 8916 {
8917 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8918 RTX_FRAME_RELATED_P (insn) = 1;
8919 }
9db1d521 8920
4023fb28 8921 /* Set up got pointer, if needed. */
c7453384 8922
6fb5fa3c 8923 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
585539a1 8924 {
775c43d3 8925 rtx_insn *insns = s390_load_got ();
585539a1 8926
b32d5189 8927 for (rtx_insn *insn = insns; insn; insn = NEXT_INSN (insn))
6fb5fa3c 8928 annotate_constant_pool_refs (&PATTERN (insn));
585539a1
UW		 8929
8930 emit_insn (insns);
8931 }
c7453384 8932
3839e36a 8933 if (TARGET_TPF_PROFILING)
c7453384
EC		 8934 {
8935 /* Generate a BAS instruction to serve as a function
8936 entry intercept to facilitate the use of tracing
2f7e5a0d
EC		 8937 algorithms located at the branch target. */
8938 emit_insn (gen_prologue_tpf ());
c7453384
EC		 8939
8940 /* Emit a blockage here so that all code
8941 lies between the profiling mechanisms. */
8942 emit_insn (gen_blockage ());
8943 }
4023fb28 8944}
9db1d521 8945
b1c9bc51 8946/* Expand the epilogue into a bunch of separate insns. */
9db1d521 8947
4023fb28 8948void
ed9676cf 8949s390_emit_epilogue (bool sibcall)
4023fb28 8950{
75707b28 8951 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
5d4d885c 8952 int area_bottom, area_top, offset = 0;
adf39f8f 8953 int next_offset;
4023fb28 8954 rtvec p;
7333171f 8955 int i;
9db1d521 8956
3839e36a 8957 if (TARGET_TPF_PROFILING)
c7453384
EC		 8958 {
8959
8960 /* Generate a BAS instruction to serve as a function
8961 entry intercept to facilitate the use of tracing
2f7e5a0d 8962 algorithms located at the branch target. */
c7453384 8963
c7453384
EC		 8964 /* Emit a blockage here so that all code
8965 lies between the profiling mechanisms. */
8966 emit_insn (gen_blockage ());
8967
2f7e5a0d 8968 emit_insn (gen_epilogue_tpf ());
c7453384
EC		 8969 }
8970
4023fb28 8971 /* Check whether to use frame or stack pointer for restore. */
9db1d521 8972
f4aa3848 8973 frame_pointer = (frame_pointer_needed
adf39f8f 8974 ? hard_frame_pointer_rtx : stack_pointer_rtx);
9db1d521 8975
adf39f8f 8976 s390_frame_area (&area_bottom, &area_top);
9db1d521 8977
c7453384 8978 /* Check whether we can access the register save area.
4023fb28 8979 If not, increment the frame pointer as required. */
9db1d521 8980
4023fb28
UW		 8981 if (area_top <= area_bottom)
8982 {
8983 /* Nothing to restore. */
8984 }
adf39f8f
AK		 8985 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8986 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
4023fb28
UW		 8987 {
8988 /* Area is in range. */
adf39f8f 8989 offset = cfun_frame_layout.frame_size;
4023fb28
UW		 8990 }
8991 else
8992 {
75707b28 8993 rtx insn, frame_off, cfa;
9db1d521 8994
c7453384 8995 offset = area_bottom < 0 ? -area_bottom : 0;
adf39f8f 8996 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
9db1d521 8997
75707b28
JJ		 8998 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8999 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
d3632d41
UW		 9000 if (DISP_IN_RANGE (INTVAL (frame_off)))
9001 {
c7453384 9002 insn = gen_rtx_SET (VOIDmode, frame_pointer,
d3632d41
UW		 9003 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
9004 insn = emit_insn (insn);
9005 }
9006 else
9007 {
b5c67a49 9008 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
d3632d41 9009 frame_off = force_const_mem (Pmode, frame_off);
9db1d521 9010
d3632d41 9011 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
585539a1 9012 annotate_constant_pool_refs (&PATTERN (insn));
d3632d41 9013 }
75707b28
JJ		 9014 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
9015 RTX_FRAME_RELATED_P (insn) = 1;
4023fb28 9016 }
9db1d521 9017
4023fb28
UW		 9018 /* Restore call saved fprs. */
9019
9020 if (TARGET_64BIT)
9db1d521 9021 {
adf39f8f
AK		 9022 if (cfun_save_high_fprs_p)
9023 {
9024 next_offset = cfun_frame_layout.f8_offset;
2cf4c39e 9025 for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++)
adf39f8f 9026 {
b89b22fc 9027 if (cfun_fpr_save_p (i))
adf39f8f
AK		 9028 {
9029 restore_fpr (frame_pointer,
9030 offset + next_offset, i);
75707b28
JJ		 9031 cfa_restores
9032 = alloc_reg_note (REG_CFA_RESTORE,
9033 gen_rtx_REG (DFmode, i), cfa_restores);
adf39f8f
AK		 9034 next_offset += 8;
9035 }
9036 }
9037 }
f4aa3848 9038
9db1d521
HP		 9039 }
9040 else
9041 {
adf39f8f 9042 next_offset = cfun_frame_layout.f4_offset;
b89b22fc 9043 /* f4, f6 */
2cf4c39e 9044 for (i = FPR4_REGNUM; i <= FPR4_REGNUM + 1; i++)
adf39f8f 9045 {
b89b22fc 9046 if (cfun_fpr_save_p (i))
adf39f8f
AK		 9047 {
9048 restore_fpr (frame_pointer,
9049 offset + next_offset, i);
75707b28
JJ		 9050 cfa_restores
9051 = alloc_reg_note (REG_CFA_RESTORE,
9052 gen_rtx_REG (DFmode, i), cfa_restores);
adf39f8f
AK		 9053 next_offset += 8;
9054 }
b3d31392 9055 else if (!TARGET_PACKED_STACK)
adf39f8f
AK		 9056 next_offset += 8;
9057 }
f4aa3848 9058
4023fb28 9059 }
9db1d521 9060
4023fb28
UW		 9061 /* Return register. */
9062
c7453384 9063 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
4023fb28
UW		 9064
9065 /* Restore call saved gprs. */
9066
adf39f8f 9067 if (cfun_frame_layout.first_restore_gpr != -1)
4023fb28 9068 {
c3cc6b78 9069 rtx insn, addr;
1447dc69
HP		 9070 int i;
9071
c7453384 9072 /* Check for global register and save them
1447dc69
HP		 9073 to stack location from where they get restored. */
9074
adf39f8f
AK		 9075 for (i = cfun_frame_layout.first_restore_gpr;
9076 i <= cfun_frame_layout.last_restore_gpr;
1447dc69
HP		 9077 i++)
9078 {
75707b28 9079 if (global_not_special_regno_p (i))
1447dc69 9080 {
0a81f074 9081 addr = plus_constant (Pmode, frame_pointer,
f4aa3848 9082 offset + cfun_frame_layout.gprs_offset
fb3712f6 9083 + (i - cfun_frame_layout.first_save_gpr_slot)
9602b6a1 9084 * UNITS_PER_LONG);
1447dc69 9085 addr = gen_rtx_MEM (Pmode, addr);
dcc9eb26 9086 set_mem_alias_set (addr, get_frame_alias_set ());
1447dc69 9087 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
c7453384 9088 }
75707b28
JJ		 9089 else
9090 cfa_restores
9091 = alloc_reg_note (REG_CFA_RESTORE,
9092 gen_rtx_REG (Pmode, i), cfa_restores);
1447dc69 9093 }
4023fb28 9094
ed9676cf 9095 if (! sibcall)
9db1d521 9096 {
ed9676cf 9097 /* Fetch return address from stack before load multiple,
db716bde
AK		 9098 this will do good for scheduling.
9099
9100 Only do this if we already decided that r14 needs to be
9101 saved to a stack slot. (And not just because r14 happens to
9102 be in between two GPRs which need saving.) Otherwise it
9103 would be difficult to take that decision back in
9104 s390_optimize_prologue. */
9105 if (cfun_gpr_save_slot (RETURN_REGNUM) == -1)
ed9676cf
AK		 9106 {
9107 int return_regnum = find_unused_clobbered_reg();
9108 if (!return_regnum)
9109 return_regnum = 4;
9110 return_reg = gen_rtx_REG (Pmode, return_regnum);
38899e29 9111
0a81f074 9112 addr = plus_constant (Pmode, frame_pointer,
adf39f8f 9113 offset + cfun_frame_layout.gprs_offset
f4aa3848 9114 + (RETURN_REGNUM
fb3712f6 9115 - cfun_frame_layout.first_save_gpr_slot)
9602b6a1 9116 * UNITS_PER_LONG);
ed9676cf 9117 addr = gen_rtx_MEM (Pmode, addr);
dcc9eb26 9118 set_mem_alias_set (addr, get_frame_alias_set ());
ed9676cf 9119 emit_move_insn (return_reg, addr);
db716bde
AK		 9120
9121 /* Once we did that optimization we have to make sure
9122 s390_optimize_prologue does not try to remove the
9123 store of r14 since we will not be able to find the
9124 load issued here. */
9125 cfun_frame_layout.save_return_addr_p = true;
ed9676cf 9126 }
9db1d521 9127 }
4023fb28 9128
adf39f8f
AK		 9129 insn = restore_gprs (frame_pointer,
9130 offset + cfun_frame_layout.gprs_offset
f4aa3848 9131 + (cfun_frame_layout.first_restore_gpr
fb3712f6 9132 - cfun_frame_layout.first_save_gpr_slot)
9602b6a1 9133 * UNITS_PER_LONG,
adf39f8f
AK		 9134 cfun_frame_layout.first_restore_gpr,
9135 cfun_frame_layout.last_restore_gpr);
75707b28
JJ		 9136 insn = emit_insn (insn);
9137 REG_NOTES (insn) = cfa_restores;
9138 add_reg_note (insn, REG_CFA_DEF_CFA,
0a81f074
RS		 9139 plus_constant (Pmode, stack_pointer_rtx,
9140 STACK_POINTER_OFFSET));
75707b28 9141 RTX_FRAME_RELATED_P (insn) = 1;
4023fb28 9142 }
9db1d521 9143
6455a49e
AK		 9144 s390_restore_gprs_from_fprs ();
9145
ed9676cf
AK		 9146 if (! sibcall)
9147 {
c7453384 9148
ed9676cf 9149 /* Return to caller. */
38899e29 9150
ed9676cf 9151 p = rtvec_alloc (2);
38899e29 9152
3810076b 9153 RTVEC_ELT (p, 0) = ret_rtx;
ed9676cf
AK		 9154 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
9155 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
9156 }
9db1d521
HP		 9157}
9158
177bc204
RS		 9159/* Implement TARGET_SET_UP_BY_PROLOGUE. */
9160
9161static void
9162s300_set_up_by_prologue (hard_reg_set_container *regs)
9163{
9164 if (cfun->machine->base_reg
9165 && !call_really_used_regs[REGNO (cfun->machine->base_reg)])
9166 SET_HARD_REG_BIT (regs->set, REGNO (cfun->machine->base_reg));
9167}
9168
9169/* Return true if the function can use simple_return to return outside
9170 of a shrink-wrapped region. At present shrink-wrapping is supported
9171 in all cases. */
9172
9173bool
9174s390_can_use_simple_return_insn (void)
9175{
9176 return true;
9177}
9178
9179/* Return true if the epilogue is guaranteed to contain only a return
9180 instruction and if a direct return can therefore be used instead.
9181 One of the main advantages of using direct return instructions
9182 is that we can then use conditional returns. */
9183
9184bool
9185s390_can_use_return_insn (void)
9186{
9187 int i;
9188
9189 if (!reload_completed)
9190 return false;
9191
9192 if (crtl->profile)
9193 return false;
9194
9195 if (TARGET_TPF_PROFILING)
9196 return false;
9197
9198 for (i = 0; i < 16; i++)
9199 if (cfun_gpr_save_slot (i))
9200 return false;
9201
6e77facf
AK		 9202 /* For 31 bit this is not covered by the frame_size check below
9203 since f4, f6 are saved in the register save area without needing
9204 additional stack space. */
9205 if (!TARGET_64BIT
9206 && (cfun_fpr_save_p (FPR4_REGNUM) || cfun_fpr_save_p (FPR6_REGNUM)))
9207 return false;
9208
177bc204
RS		 9209 if (cfun->machine->base_reg
9210 && !call_really_used_regs[REGNO (cfun->machine->base_reg)])
9211 return false;
9212
9213 return cfun_frame_layout.frame_size == 0;
9214}
9db1d521 9215
c7453384 9216/* Return the size in bytes of a function argument of
994fe660
UW		 9217 type TYPE and/or mode MODE. At least one of TYPE or
9218 MODE must be specified. */
9db1d521
HP		 9219
9220static int
ef4bddc2 9221s390_function_arg_size (machine_mode mode, const_tree type)
9db1d521
HP		 9222{
9223 if (type)
9224 return int_size_in_bytes (type);
9225
d65f7478 9226 /* No type info available for some library calls ... */
9db1d521
HP		 9227 if (mode != BLKmode)
9228 return GET_MODE_SIZE (mode);
9229
9230 /* If we have neither type nor mode, abort */
8d933e31 9231 gcc_unreachable ();
9db1d521
HP		 9232}
9233
82b1c974
UW		 9234/* Return true if a function argument of type TYPE and mode MODE
9235 is to be passed in a floating-point register, if available. */
9236
9237static bool
ef4bddc2 9238s390_function_arg_float (machine_mode mode, const_tree type)
82b1c974 9239{
8c17530e
UW		 9240 int size = s390_function_arg_size (mode, type);
9241 if (size > 8)
9242 return false;
9243
82b1c974
UW		 9244 /* Soft-float changes the ABI: no floating-point registers are used. */
9245 if (TARGET_SOFT_FLOAT)
9246 return false;
9247
9248 /* No type info available for some library calls ... */
9249 if (!type)
4dc19cc0 9250 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
82b1c974
UW		 9251
9252 /* The ABI says that record types with a single member are treated
9253 just like that member would be. */
9254 while (TREE_CODE (type) == RECORD_TYPE)
9255 {
9256 tree field, single = NULL_TREE;
9257
910ad8de 9258 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
82b1c974
UW		 9259 {
9260 if (TREE_CODE (field) != FIELD_DECL)
9261 continue;
9262
9263 if (single == NULL_TREE)
9264 single = TREE_TYPE (field);
9265 else
9266 return false;
9267 }
9268
9269 if (single == NULL_TREE)
9270 return false;
9271 else
9272 type = single;
9273 }
9274
9275 return TREE_CODE (type) == REAL_TYPE;
9276}
9277
8c17530e
UW		 9278/* Return true if a function argument of type TYPE and mode MODE
9279 is to be passed in an integer register, or a pair of integer
9280 registers, if available. */
9281
9282static bool
ef4bddc2 9283s390_function_arg_integer (machine_mode mode, const_tree type)
8c17530e
UW		 9284{
9285 int size = s390_function_arg_size (mode, type);
9286 if (size > 8)
9287 return false;
9288
9289 /* No type info available for some library calls ... */
9290 if (!type)
9291 return GET_MODE_CLASS (mode) == MODE_INT
4dc19cc0 9292 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
8c17530e
UW		 9293
9294 /* We accept small integral (and similar) types. */
9295 if (INTEGRAL_TYPE_P (type)
38899e29 9296 || POINTER_TYPE_P (type)
0d697034 9297 || TREE_CODE (type) == NULLPTR_TYPE
8c17530e
UW		 9298 || TREE_CODE (type) == OFFSET_TYPE
9299 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
9300 return true;
9301
9302 /* We also accept structs of size 1, 2, 4, 8 that are not
38899e29 9303 passed in floating-point registers. */
8c17530e
UW		 9304 if (AGGREGATE_TYPE_P (type)
9305 && exact_log2 (size) >= 0
9306 && !s390_function_arg_float (mode, type))
9307 return true;
9308
9309 return false;
9310}
9311
994fe660
UW		 9312/* Return 1 if a function argument of type TYPE and mode MODE
9313 is to be passed by reference. The ABI specifies that only
9314 structures of size 1, 2, 4, or 8 bytes are passed by value,
9315 all other structures (and complex numbers) are passed by
9316 reference. */
9317
8cd5a4e0 9318static bool
d5cc9181 9319s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
ef4bddc2 9320 machine_mode mode, const_tree type,
8cd5a4e0 9321 bool named ATTRIBUTE_UNUSED)
9db1d521
HP		 9322{
9323 int size = s390_function_arg_size (mode, type);
8c17530e
UW		 9324 if (size > 8)
9325 return true;
9db1d521
HP		 9326
9327 if (type)
9328 {
8c17530e 9329 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
9db1d521
HP		 9330 return 1;
9331
8c17530e
UW		 9332 if (TREE_CODE (type) == COMPLEX_TYPE
9333 || TREE_CODE (type) == VECTOR_TYPE)
9db1d521
HP		 9334 return 1;
9335 }
c7453384 9336
9db1d521 9337 return 0;
9db1d521
HP		 9338}
9339
9340/* Update the data in CUM to advance over an argument of mode MODE and
9341 data type TYPE. (TYPE is null for libcalls where that information
994fe660
UW		 9342 may not be available.). The boolean NAMED specifies whether the
9343 argument is a named argument (as opposed to an unnamed argument
9344 matching an ellipsis). */
9db1d521 9345
3cb1da52 9346static void
ef4bddc2 9347s390_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
3cb1da52 9348 const_tree type, bool named ATTRIBUTE_UNUSED)
9db1d521 9349{
d5cc9181
JR		 9350 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
9351
8cd5a4e0 9352 if (s390_function_arg_float (mode, type))
9db1d521 9353 {
82b1c974 9354 cum->fprs += 1;
9db1d521 9355 }
8c17530e 9356 else if (s390_function_arg_integer (mode, type))
9db1d521
HP		 9357 {
9358 int size = s390_function_arg_size (mode, type);
9602b6a1 9359 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
9db1d521 9360 }
8c17530e 9361 else
8d933e31 9362 gcc_unreachable ();
9db1d521
HP		 9363}
9364
994fe660
UW		 9365/* Define where to put the arguments to a function.
9366 Value is zero to push the argument on the stack,
9367 or a hard register in which to store the argument.
9368
9369 MODE is the argument's machine mode.
9370 TYPE is the data type of the argument (as a tree).
9371 This is null for libcalls where that information may
9372 not be available.
9373 CUM is a variable of type CUMULATIVE_ARGS which gives info about
9374 the preceding args and about the function being called.
9375 NAMED is nonzero if this argument is a named parameter
c7453384 9376 (otherwise it is an extra parameter matching an ellipsis).
994fe660
UW		 9377
9378 On S/390, we use general purpose registers 2 through 6 to
9379 pass integer, pointer, and certain structure arguments, and
9380 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
9381 to pass floating point arguments. All remaining arguments
9382 are pushed to the stack. */
9db1d521 9383
3cb1da52 9384static rtx
ef4bddc2 9385s390_function_arg (cumulative_args_t cum_v, machine_mode mode,
3cb1da52 9386 const_tree type, bool named ATTRIBUTE_UNUSED)
9db1d521 9387{
d5cc9181
JR		 9388 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
9389
82b1c974 9390 if (s390_function_arg_float (mode, type))
9db1d521 9391 {
29a79fcf 9392 if (cum->fprs + 1 > FP_ARG_NUM_REG)
9db1d521
HP		 9393 return 0;
9394 else
f1c25d3b 9395 return gen_rtx_REG (mode, cum->fprs + 16);
9db1d521 9396 }
8c17530e 9397 else if (s390_function_arg_integer (mode, type))
9db1d521
HP		 9398 {
9399 int size = s390_function_arg_size (mode, type);
9602b6a1 9400 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
9db1d521 9401
29a79fcf 9402 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
9db1d521 9403 return 0;
9602b6a1 9404 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
f1c25d3b 9405 return gen_rtx_REG (mode, cum->gprs + 2);
9602b6a1
AK		 9406 else if (n_gprs == 2)
9407 {
9408 rtvec p = rtvec_alloc (2);
9409
9410 RTVEC_ELT (p, 0)
9411 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
9412 const0_rtx);
9413 RTVEC_ELT (p, 1)
9414 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
9415 GEN_INT (4));
9416
9417 return gen_rtx_PARALLEL (mode, p);
9418 }
9db1d521 9419 }
8c17530e
UW		 9420
9421 /* After the real arguments, expand_call calls us once again
9422 with a void_type_node type. Whatever we return here is
9423 passed as operand 2 to the call expanders.
9424
9425 We don't need this feature ... */
9426 else if (type == void_type_node)
9427 return const0_rtx;
9428
8d933e31 9429 gcc_unreachable ();
8c17530e
UW		 9430}
9431
9432/* Return true if return values of type TYPE should be returned
9433 in a memory buffer whose address is passed by the caller as
9434 hidden first argument. */
9435
9436static bool
586de218 9437s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
8c17530e
UW		 9438{
9439 /* We accept small integral (and similar) types. */
9440 if (INTEGRAL_TYPE_P (type)
38899e29 9441 || POINTER_TYPE_P (type)
8c17530e
UW		 9442 || TREE_CODE (type) == OFFSET_TYPE
9443 || TREE_CODE (type) == REAL_TYPE)
9444 return int_size_in_bytes (type) > 8;
9445
9446 /* Aggregates and similar constructs are always returned
9447 in memory. */
9448 if (AGGREGATE_TYPE_P (type)
9449 || TREE_CODE (type) == COMPLEX_TYPE
9450 || TREE_CODE (type) == VECTOR_TYPE)
9451 return true;
9452
9453 /* ??? We get called on all sorts of random stuff from
9454 aggregate_value_p. We can't abort, but it's not clear
9455 what's safe to return. Pretend it's a struct I guess. */
9456 return true;
9457}
9458
cde0f3fd
PB		 9459/* Function arguments and return values are promoted to word size. */
9460
ef4bddc2
RS		 9461static machine_mode
9462s390_promote_function_mode (const_tree type, machine_mode mode,
cde0f3fd
PB		 9463 int *punsignedp,
9464 const_tree fntype ATTRIBUTE_UNUSED,
9465 int for_return ATTRIBUTE_UNUSED)
9466{
9467 if (INTEGRAL_MODE_P (mode)
9602b6a1 9468 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
cde0f3fd 9469 {
5e617be8 9470 if (type != NULL_TREE && POINTER_TYPE_P (type))
cde0f3fd
PB		 9471 *punsignedp = POINTERS_EXTEND_UNSIGNED;
9472 return Pmode;
9473 }
9474
9475 return mode;
9476}
9477
b46616fd
AK		 9478/* Define where to return a (scalar) value of type RET_TYPE.
9479 If RET_TYPE is null, define where to return a (scalar)
8c17530e
UW		 9480 value of mode MODE from a libcall. */
9481
b46616fd 9482static rtx
ef4bddc2 9483s390_function_and_libcall_value (machine_mode mode,
b46616fd
AK		 9484 const_tree ret_type,
9485 const_tree fntype_or_decl,
9486 bool outgoing ATTRIBUTE_UNUSED)
8c17530e 9487{
b46616fd
AK		 9488 /* For normal functions perform the promotion as
9489 promote_function_mode would do. */
9490 if (ret_type)
8c17530e 9491 {
b46616fd
AK		 9492 int unsignedp = TYPE_UNSIGNED (ret_type);
9493 mode = promote_function_mode (ret_type, mode, &unsignedp,
9494 fntype_or_decl, 1);
8c17530e
UW		 9495 }
9496
4dc19cc0 9497 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
8d933e31 9498 gcc_assert (GET_MODE_SIZE (mode) <= 8);
8c17530e 9499
4dc19cc0 9500 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
8c17530e 9501 return gen_rtx_REG (mode, 16);
9602b6a1
AK		 9502 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
9503 || UNITS_PER_LONG == UNITS_PER_WORD)
8c17530e 9504 return gen_rtx_REG (mode, 2);
9602b6a1
AK		 9505 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
9506 {
b46616fd
AK		 9507 /* This case is triggered when returning a 64 bit value with
9508 -m31 -mzarch. Although the value would fit into a single
9509 register it has to be forced into a 32 bit register pair in
9510 order to match the ABI. */
9602b6a1
AK		 9511 rtvec p = rtvec_alloc (2);
9512
9513 RTVEC_ELT (p, 0)
9514 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
9515 RTVEC_ELT (p, 1)
9516 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
9517
9518 return gen_rtx_PARALLEL (mode, p);
9519 }
9520
9521 gcc_unreachable ();
9db1d521
HP		 9522}
9523
b46616fd
AK		 9524/* Define where to return a scalar return value of type RET_TYPE. */
9525
9526static rtx
9527s390_function_value (const_tree ret_type, const_tree fn_decl_or_type,
9528 bool outgoing)
9529{
9530 return s390_function_and_libcall_value (TYPE_MODE (ret_type), ret_type,
9531 fn_decl_or_type, outgoing);
9532}
9533
9534/* Define where to return a scalar libcall return value of mode
9535 MODE. */
9536
9537static rtx
ef4bddc2 9538s390_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
b46616fd
AK		 9539{
9540 return s390_function_and_libcall_value (mode, NULL_TREE,
9541 NULL_TREE, true);
9542}
9543
9db1d521 9544
994fe660
UW		 9545/* Create and return the va_list datatype.
9546
9547 On S/390, va_list is an array type equivalent to
9548
9549 typedef struct __va_list_tag
9550 {
9551 long __gpr;
9552 long __fpr;
9553 void *__overflow_arg_area;
9554 void *__reg_save_area;
994fe660
UW		 9555 } va_list[1];
9556
9557 where __gpr and __fpr hold the number of general purpose
9558 or floating point arguments used up to now, respectively,
c7453384 9559 __overflow_arg_area points to the stack location of the
994fe660
UW		 9560 next argument passed on the stack, and __reg_save_area
9561 always points to the start of the register area in the
9562 call frame of the current function. The function prologue
9563 saves all registers used for argument passing into this
9564 area if the function uses variable arguments. */
9db1d521 9565
c35d187f
RH		 9566static tree
9567s390_build_builtin_va_list (void)
9db1d521
HP		 9568{
9569 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
9570
47798692 9571 record = lang_hooks.types.make_type (RECORD_TYPE);
9db1d521
HP		 9572
9573 type_decl =
4c4bde29
AH		 9574 build_decl (BUILTINS_LOCATION,
9575 TYPE_DECL, get_identifier ("__va_list_tag"), record);
9db1d521 9576
4c4bde29
AH		 9577 f_gpr = build_decl (BUILTINS_LOCATION,
9578 FIELD_DECL, get_identifier ("__gpr"),
9db1d521 9579 long_integer_type_node);
4c4bde29
AH		 9580 f_fpr = build_decl (BUILTINS_LOCATION,
9581 FIELD_DECL, get_identifier ("__fpr"),
9db1d521 9582 long_integer_type_node);
4c4bde29
AH		 9583 f_ovf = build_decl (BUILTINS_LOCATION,
9584 FIELD_DECL, get_identifier ("__overflow_arg_area"),
9db1d521 9585 ptr_type_node);
4c4bde29
AH		 9586 f_sav = build_decl (BUILTINS_LOCATION,
9587 FIELD_DECL, get_identifier ("__reg_save_area"),
9db1d521
HP		 9588 ptr_type_node);
9589
29a79fcf
UW		 9590 va_list_gpr_counter_field = f_gpr;
9591 va_list_fpr_counter_field = f_fpr;
9592
9db1d521
HP		 9593 DECL_FIELD_CONTEXT (f_gpr) = record;
9594 DECL_FIELD_CONTEXT (f_fpr) = record;
9595 DECL_FIELD_CONTEXT (f_ovf) = record;
9596 DECL_FIELD_CONTEXT (f_sav) = record;
9597
0fd2eac2 9598 TYPE_STUB_DECL (record) = type_decl;
9db1d521
HP		 9599 TYPE_NAME (record) = type_decl;
9600 TYPE_FIELDS (record) = f_gpr;
910ad8de
NF		 9601 DECL_CHAIN (f_gpr) = f_fpr;
9602 DECL_CHAIN (f_fpr) = f_ovf;
9603 DECL_CHAIN (f_ovf) = f_sav;
9db1d521
HP		 9604
9605 layout_type (record);
9606
9607 /* The correct type is an array type of one element. */
9608 return build_array_type (record, build_index_type (size_zero_node));
9609}
9610
994fe660 9611/* Implement va_start by filling the va_list structure VALIST.
6c535c69
ZW		 9612 STDARG_P is always true, and ignored.
9613 NEXTARG points to the first anonymous stack argument.
994fe660 9614
f710504c 9615 The following global variables are used to initialize
994fe660
UW		 9616 the va_list structure:
9617
38173d38 9618 crtl->args.info:
994fe660 9619 holds number of gprs and fprs used for named arguments.
38173d38 9620 crtl->args.arg_offset_rtx:
994fe660
UW		 9621 holds the offset of the first anonymous stack argument
9622 (relative to the virtual arg pointer). */
9db1d521 9623
d7bd8aeb 9624static void
9c808aad 9625s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
9db1d521
HP		 9626{
9627 HOST_WIDE_INT n_gpr, n_fpr;
9628 int off;
9629 tree f_gpr, f_fpr, f_ovf, f_sav;
9630 tree gpr, fpr, ovf, sav, t;
9631
9632 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
910ad8de
NF		 9633 f_fpr = DECL_CHAIN (f_gpr);
9634 f_ovf = DECL_CHAIN (f_fpr);
9635 f_sav = DECL_CHAIN (f_ovf);
9db1d521 9636
86710a8b 9637 valist = build_simple_mem_ref (valist);
47a25a46
RG		 9638 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9639 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
9640 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9641 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
9db1d521
HP		 9642
9643 /* Count number of gp and fp argument registers used. */
9644
38173d38
JH		 9645 n_gpr = crtl->args.info.gprs;
9646 n_fpr = crtl->args.info.fprs;
9db1d521 9647
29a79fcf
UW		 9648 if (cfun->va_list_gpr_size)
9649 {
726a989a
RB		 9650 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
9651 build_int_cst (NULL_TREE, n_gpr));
29a79fcf
UW		 9652 TREE_SIDE_EFFECTS (t) = 1;
9653 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9654 }
9db1d521 9655
29a79fcf
UW		 9656 if (cfun->va_list_fpr_size)
9657 {
726a989a 9658 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
47a25a46 9659 build_int_cst (NULL_TREE, n_fpr));
29a79fcf
UW		 9660 TREE_SIDE_EFFECTS (t) = 1;
9661 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9662 }
9db1d521
HP		 9663
9664 /* Find the overflow area. */
29a79fcf
UW		 9665 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
9666 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
9667 {
9668 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
9db1d521 9669
38173d38 9670 off = INTVAL (crtl->args.arg_offset_rtx);
29a79fcf
UW		 9671 off = off < 0 ? 0 : off;
9672 if (TARGET_DEBUG_ARG)
9673 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
9674 (int)n_gpr, (int)n_fpr, off);
9db1d521 9675
5d49b6a7 9676 t = fold_build_pointer_plus_hwi (t, off);
9db1d521 9677
726a989a 9678 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
29a79fcf
UW		 9679 TREE_SIDE_EFFECTS (t) = 1;
9680 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9681 }
9db1d521
HP		 9682
9683 /* Find the register save area. */
29a79fcf
UW		 9684 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
9685 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
9686 {
9687 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
5d49b6a7 9688 t = fold_build_pointer_plus_hwi (t, -RETURN_REGNUM * UNITS_PER_LONG);
f4aa3848 9689
726a989a 9690 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
29a79fcf
UW		 9691 TREE_SIDE_EFFECTS (t) = 1;
9692 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9693 }
9db1d521
HP		 9694}
9695
c7453384 9696/* Implement va_arg by updating the va_list structure
994fe660 9697 VALIST as required to retrieve an argument of type
c7453384
EC		 9698 TYPE, and returning that argument.
9699
994fe660 9700 Generates code equivalent to:
c7453384 9701
9db1d521
HP		 9702 if (integral value) {
9703 if (size <= 4 && args.gpr < 5 ||
c7453384 9704 size > 4 && args.gpr < 4 )
9db1d521
HP		 9705 ret = args.reg_save_area[args.gpr+8]
9706 else
9707 ret = *args.overflow_arg_area++;
9708 } else if (float value) {
9709 if (args.fgpr < 2)
9710 ret = args.reg_save_area[args.fpr+64]
9711 else
9712 ret = *args.overflow_arg_area++;
9713 } else if (aggregate value) {
9714 if (args.gpr < 5)
9715 ret = *args.reg_save_area[args.gpr]
9716 else
9717 ret = **args.overflow_arg_area++;
9718 } */
9719
ab96de7e 9720static tree
f4aa3848 9721s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
726a989a 9722 gimple_seq *post_p ATTRIBUTE_UNUSED)
9db1d521
HP		 9723{
9724 tree f_gpr, f_fpr, f_ovf, f_sav;
9725 tree gpr, fpr, ovf, sav, reg, t, u;
9726 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
63694b5e 9727 tree lab_false, lab_over, addr;
9db1d521
HP		 9728
9729 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
910ad8de
NF		 9730 f_fpr = DECL_CHAIN (f_gpr);
9731 f_ovf = DECL_CHAIN (f_fpr);
9732 f_sav = DECL_CHAIN (f_ovf);
9db1d521 9733
967af719 9734 valist = build_va_arg_indirect_ref (valist);
47a25a46
RG		 9735 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9736 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
47a25a46 9737 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
9db1d521 9738
726a989a
RB		 9739 /* The tree for args* cannot be shared between gpr/fpr and ovf since
9740 both appear on a lhs. */
9741 valist = unshare_expr (valist);
9742 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9743
9db1d521
HP		 9744 size = int_size_in_bytes (type);
9745
8cd5a4e0 9746 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
9db1d521
HP		 9747 {
9748 if (TARGET_DEBUG_ARG)
9749 {
9750 fprintf (stderr, "va_arg: aggregate type");
9751 debug_tree (type);
9752 }
9753
9754 /* Aggregates are passed by reference. */
9755 indirect_p = 1;
9756 reg = gpr;
9757 n_reg = 1;
ea506297 9758
b3d31392 9759 /* kernel stack layout on 31 bit: It is assumed here that no padding
ea506297
AK		 9760 will be added by s390_frame_info because for va_args always an even
9761 number of gprs has to be saved r15-r2 = 14 regs. */
9602b6a1
AK		 9762 sav_ofs = 2 * UNITS_PER_LONG;
9763 sav_scale = UNITS_PER_LONG;
9764 size = UNITS_PER_LONG;
29a79fcf 9765 max_reg = GP_ARG_NUM_REG - n_reg;
9db1d521 9766 }
82b1c974 9767 else if (s390_function_arg_float (TYPE_MODE (type), type))
9db1d521
HP		 9768 {
9769 if (TARGET_DEBUG_ARG)
9770 {
9771 fprintf (stderr, "va_arg: float type");
9772 debug_tree (type);
9773 }
9774
9775 /* FP args go in FP registers, if present. */
9776 indirect_p = 0;
9777 reg = fpr;
9778 n_reg = 1;
9602b6a1 9779 sav_ofs = 16 * UNITS_PER_LONG;
9db1d521 9780 sav_scale = 8;
29a79fcf 9781 max_reg = FP_ARG_NUM_REG - n_reg;
9db1d521
HP		 9782 }
9783 else
9784 {
9785 if (TARGET_DEBUG_ARG)
9786 {
9787 fprintf (stderr, "va_arg: other type");
9788 debug_tree (type);
9789 }
9790
9791 /* Otherwise into GP registers. */
9792 indirect_p = 0;
9793 reg = gpr;
9602b6a1 9794 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
ea506297 9795
b3d31392
AK		 9796 /* kernel stack layout on 31 bit: It is assumed here that no padding
9797 will be added by s390_frame_info because for va_args always an even
9798 number of gprs has to be saved r15-r2 = 14 regs. */
9602b6a1 9799 sav_ofs = 2 * UNITS_PER_LONG;
c7453384 9800
9602b6a1
AK		 9801 if (size < UNITS_PER_LONG)
9802 sav_ofs += UNITS_PER_LONG - size;
9db1d521 9803
9602b6a1 9804 sav_scale = UNITS_PER_LONG;
29a79fcf 9805 max_reg = GP_ARG_NUM_REG - n_reg;
9db1d521
HP		 9806 }
9807
9808 /* Pull the value out of the saved registers ... */
9809
4c4bde29
AH		 9810 lab_false = create_artificial_label (UNKNOWN_LOCATION);
9811 lab_over = create_artificial_label (UNKNOWN_LOCATION);
63694b5e 9812 addr = create_tmp_var (ptr_type_node, "addr");
9db1d521 9813
6c6dd4bd 9814 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
63694b5e
UW		 9815 t = build2 (GT_EXPR, boolean_type_node, reg, t);
9816 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9817 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9818 gimplify_and_add (t, pre_p);
9db1d521 9819
5d49b6a7 9820 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
f4aa3848 9821 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
6c6dd4bd 9822 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
5d49b6a7 9823 t = fold_build_pointer_plus (t, u);
9db1d521 9824
726a989a 9825 gimplify_assign (addr, t, pre_p);
9db1d521 9826
726a989a 9827 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
9db1d521 9828
726a989a 9829 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
9db1d521 9830
9db1d521
HP		 9831
9832 /* ... Otherwise out of the overflow area. */
9833
ab96de7e 9834 t = ovf;
9602b6a1 9835 if (size < UNITS_PER_LONG)
5d49b6a7 9836 t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG - size);
ab96de7e
AS		 9837
9838 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9839
726a989a 9840 gimplify_assign (addr, t, pre_p);
ab96de7e 9841
5d49b6a7 9842 t = fold_build_pointer_plus_hwi (t, size);
726a989a 9843 gimplify_assign (ovf, t, pre_p);
ab96de7e 9844
726a989a 9845 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
ab96de7e
AS		 9846
9847
9848 /* Increment register save count. */
9849
9850 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
9851 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
9852 gimplify_and_add (u, pre_p);
9853
9854 if (indirect_p)
9855 {
5b21f0f3
RG		 9856 t = build_pointer_type_for_mode (build_pointer_type (type),
9857 ptr_mode, true);
ab96de7e
AS		 9858 addr = fold_convert (t, addr);
9859 addr = build_va_arg_indirect_ref (addr);
9860 }
9861 else
9862 {
5b21f0f3 9863 t = build_pointer_type_for_mode (type, ptr_mode, true);
ab96de7e
AS		 9864 addr = fold_convert (t, addr);
9865 }
9866
9867 return build_va_arg_indirect_ref (addr);
9868}
9869
5a3fe9b6
AK		 9870/* Emit rtl for the tbegin or tbegin_retry (RETRY != NULL_RTX)
9871 expanders.
9872 DEST - Register location where CC will be stored.
9873 TDB - Pointer to a 256 byte area where to store the transaction.
9874 diagnostic block. NULL if TDB is not needed.
9875 RETRY - Retry count value. If non-NULL a retry loop for CC2
9876 is emitted
9877 CLOBBER_FPRS_P - If true clobbers for all FPRs are emitted as part
9878 of the tbegin instruction pattern. */
9879
9880void
9881s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p)
9882{
2561451d 9883 rtx retry_plus_two = gen_reg_rtx (SImode);
5a3fe9b6 9884 rtx retry_reg = gen_reg_rtx (SImode);
19f8b229 9885 rtx_code_label *retry_label = NULL;
5a3fe9b6
AK		 9886
9887 if (retry != NULL_RTX)
9888 {
9889 emit_move_insn (retry_reg, retry);
2561451d
AK		 9890 emit_insn (gen_addsi3 (retry_plus_two, retry_reg, const2_rtx));
9891 emit_insn (gen_addsi3 (retry_reg, retry_reg, const1_rtx));
5a3fe9b6
AK		 9892 retry_label = gen_label_rtx ();
9893 emit_label (retry_label);
9894 }
9895
9896 if (clobber_fprs_p)
2561451d 9897 emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), tdb));
5a3fe9b6 9898 else
2561451d
AK		 9899 emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK),
9900 tdb));
5a3fe9b6 9901
2561451d
AK		 9902 emit_move_insn (dest, gen_rtx_UNSPEC (SImode,
9903 gen_rtvec (1, gen_rtx_REG (CCRAWmode,
9904 CC_REGNUM)),
9905 UNSPEC_CC_TO_INT));
5a3fe9b6
AK		 9906 if (retry != NULL_RTX)
9907 {
86464cbd
AK		 9908 const int CC0 = 1 << 3;
9909 const int CC1 = 1 << 2;
9910 const int CC3 = 1 << 0;
9911 rtx jump;
5a3fe9b6 9912 rtx count = gen_reg_rtx (SImode);
775c43d3 9913 rtx_code_label *leave_label = gen_label_rtx ();
86464cbd
AK		 9914
9915 /* Exit for success and permanent failures. */
5a3fe9b6
AK		 9916 jump = s390_emit_jump (leave_label,
9917 gen_rtx_EQ (VOIDmode,
9918 gen_rtx_REG (CCRAWmode, CC_REGNUM),
86464cbd
AK		 9919 gen_rtx_CONST_INT (VOIDmode, CC0 | CC1 | CC3)));
9920 LABEL_NUSES (leave_label) = 1;
5a3fe9b6
AK		 9921
9922 /* CC2 - transient failure. Perform retry with ppa. */
2561451d 9923 emit_move_insn (count, retry_plus_two);
5a3fe9b6
AK		 9924 emit_insn (gen_subsi3 (count, count, retry_reg));
9925 emit_insn (gen_tx_assist (count));
9926 jump = emit_jump_insn (gen_doloop_si64 (retry_label,
9927 retry_reg,
9928 retry_reg));
9929 JUMP_LABEL (jump) = retry_label;
9930 LABEL_NUSES (retry_label) = 1;
86464cbd 9931 emit_label (leave_label);
5a3fe9b6 9932 }
5a3fe9b6
AK		 9933}
9934
9935/* Builtins. */
9936
9937enum s390_builtin
9938{
9939 S390_BUILTIN_TBEGIN,
9940 S390_BUILTIN_TBEGIN_NOFLOAT,
9941 S390_BUILTIN_TBEGIN_RETRY,
9942 S390_BUILTIN_TBEGIN_RETRY_NOFLOAT,
9943 S390_BUILTIN_TBEGINC,
9944 S390_BUILTIN_TEND,
9945 S390_BUILTIN_TABORT,
9946 S390_BUILTIN_NON_TX_STORE,
9947 S390_BUILTIN_TX_NESTING_DEPTH,
9948 S390_BUILTIN_TX_ASSIST,
9949
9950 S390_BUILTIN_max
9951};
9952
9953static enum insn_code const code_for_builtin[S390_BUILTIN_max] = {
9954 CODE_FOR_tbegin,
9955 CODE_FOR_tbegin_nofloat,
9956 CODE_FOR_tbegin_retry,
9957 CODE_FOR_tbegin_retry_nofloat,
9958 CODE_FOR_tbeginc,
9959 CODE_FOR_tend,
9960 CODE_FOR_tabort,
9961 CODE_FOR_ntstg,
9962 CODE_FOR_etnd,
9963 CODE_FOR_tx_assist
9964};
9965
9966static void
9967s390_init_builtins (void)
9968{
9969 tree ftype, uint64_type;
2561451d
AK		 9970 tree returns_twice_attr = tree_cons (get_identifier ("returns_twice"),
9971 NULL, NULL);
9972 tree noreturn_attr = tree_cons (get_identifier ("noreturn"), NULL, NULL);
5a3fe9b6
AK		 9973
9974 /* void foo (void) */
9975 ftype = build_function_type_list (void_type_node, NULL_TREE);
9976 add_builtin_function ("__builtin_tbeginc", ftype, S390_BUILTIN_TBEGINC,
9977 BUILT_IN_MD, NULL, NULL_TREE);
9978
9979 /* void foo (int) */
9980 ftype = build_function_type_list (void_type_node, integer_type_node,
9981 NULL_TREE);
9982 add_builtin_function ("__builtin_tabort", ftype,
2561451d 9983 S390_BUILTIN_TABORT, BUILT_IN_MD, NULL, noreturn_attr);
5a3fe9b6
AK		 9984 add_builtin_function ("__builtin_tx_assist", ftype,
9985 S390_BUILTIN_TX_ASSIST, BUILT_IN_MD, NULL, NULL_TREE);
9986
9987 /* int foo (void *) */
9988 ftype = build_function_type_list (integer_type_node, ptr_type_node, NULL_TREE);
9989 add_builtin_function ("__builtin_tbegin", ftype, S390_BUILTIN_TBEGIN,
2561451d 9990 BUILT_IN_MD, NULL, returns_twice_attr);
5a3fe9b6
AK		 9991 add_builtin_function ("__builtin_tbegin_nofloat", ftype,
9992 S390_BUILTIN_TBEGIN_NOFLOAT,
2561451d 9993 BUILT_IN_MD, NULL, returns_twice_attr);
5a3fe9b6
AK		 9994
9995 /* int foo (void *, int) */
9996 ftype = build_function_type_list (integer_type_node, ptr_type_node,
9997 integer_type_node, NULL_TREE);
9998 add_builtin_function ("__builtin_tbegin_retry", ftype,
9999 S390_BUILTIN_TBEGIN_RETRY,
10000 BUILT_IN_MD,
2561451d 10001 NULL, returns_twice_attr);
5a3fe9b6
AK		 10002 add_builtin_function ("__builtin_tbegin_retry_nofloat", ftype,
10003 S390_BUILTIN_TBEGIN_RETRY_NOFLOAT,
10004 BUILT_IN_MD,
2561451d 10005 NULL, returns_twice_attr);
5a3fe9b6
AK		 10006
10007 /* int foo (void) */
10008 ftype = build_function_type_list (integer_type_node, NULL_TREE);
10009 add_builtin_function ("__builtin_tx_nesting_depth", ftype,
10010 S390_BUILTIN_TX_NESTING_DEPTH,
10011 BUILT_IN_MD, NULL, NULL_TREE);
10012 add_builtin_function ("__builtin_tend", ftype,
10013 S390_BUILTIN_TEND, BUILT_IN_MD, NULL, NULL_TREE);
10014
10015 /* void foo (uint64_t *, uint64_t) */
10016 if (TARGET_64BIT)
10017 uint64_type = long_unsigned_type_node;
10018 else
10019 uint64_type = long_long_unsigned_type_node;
10020
10021 ftype = build_function_type_list (void_type_node,
10022 build_pointer_type (uint64_type),
10023 uint64_type, NULL_TREE);
10024 add_builtin_function ("__builtin_non_tx_store", ftype,
10025 S390_BUILTIN_NON_TX_STORE,
10026 BUILT_IN_MD, NULL, NULL_TREE);
10027}
10028
10029/* Expand an expression EXP that calls a built-in function,
10030 with result going to TARGET if that's convenient
10031 (and in mode MODE if that's convenient).
10032 SUBTARGET may be used as the target for computing one of EXP's operands.
10033 IGNORE is nonzero if the value is to be ignored. */
10034
10035static rtx
10036s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
ef4bddc2 10037 machine_mode mode ATTRIBUTE_UNUSED,
5a3fe9b6
AK		 10038 int ignore ATTRIBUTE_UNUSED)
10039{
10040#define MAX_ARGS 2
10041
10042 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10043 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10044 enum insn_code icode;
10045 rtx op[MAX_ARGS], pat;
10046 int arity;
10047 bool nonvoid;
10048 tree arg;
10049 call_expr_arg_iterator iter;
10050
10051 if (fcode >= S390_BUILTIN_max)
10052 internal_error ("bad builtin fcode");
10053 icode = code_for_builtin[fcode];
10054 if (icode == 0)
10055 internal_error ("bad builtin fcode");
10056
167f68ed
AK		 10057 if (!TARGET_HTM)
10058 error ("Transactional execution builtins not enabled (-mhtm)\n");
5a3fe9b6
AK		 10059
10060 /* Set a flag in the machine specific cfun part in order to support
10061 saving/restoring of FPRs. */
10062 if (fcode == S390_BUILTIN_TBEGIN || fcode == S390_BUILTIN_TBEGIN_RETRY)
10063 cfun->machine->tbegin_p = true;
10064
10065 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
10066
10067 arity = 0;
10068 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
10069 {
10070 const struct insn_operand_data *insn_op;
10071
10072 if (arg == error_mark_node)
10073 return NULL_RTX;
10074 if (arity >= MAX_ARGS)
10075 return NULL_RTX;
10076
10077 insn_op = &insn_data[icode].operand[arity + nonvoid];
10078
10079 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
10080
10081 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
10082 {
10083 if (insn_op->predicate == memory_operand)
10084 {
10085 /* Don't move a NULL pointer into a register. Otherwise
10086 we have to rely on combine being able to move it back
10087 in order to get an immediate 0 in the instruction. */
10088 if (op[arity] != const0_rtx)
10089 op[arity] = copy_to_mode_reg (Pmode, op[arity]);
10090 op[arity] = gen_rtx_MEM (insn_op->mode, op[arity]);
10091 }
10092 else
10093 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
10094 }
10095
10096 arity++;
10097 }
10098
10099 if (nonvoid)
10100 {
ef4bddc2 10101 machine_mode tmode = insn_data[icode].operand[0].mode;
5a3fe9b6
AK		 10102 if (!target
10103 || GET_MODE (target) != tmode
10104 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
10105 target = gen_reg_rtx (tmode);
10106 }
10107
10108 switch (arity)
10109 {
10110 case 0:
10111 pat = GEN_FCN (icode) (target);
10112 break;
10113 case 1:
10114 if (nonvoid)
10115 pat = GEN_FCN (icode) (target, op[0]);
10116 else
10117 pat = GEN_FCN (icode) (op[0]);
10118 break;
10119 case 2:
10120 if (nonvoid)
10121 pat = GEN_FCN (icode) (target, op[0], op[1]);
10122 else
10123 pat = GEN_FCN (icode) (op[0], op[1]);
10124 break;
10125 default:
10126 gcc_unreachable ();
10127 }
10128 if (!pat)
10129 return NULL_RTX;
10130 emit_insn (pat);
10131
10132 if (nonvoid)
10133 return target;
10134 else
10135 return const0_rtx;
10136}
10137
d56a43a0
AK		 10138/* We call mcount before the function prologue. So a profiled leaf
10139 function should stay a leaf function. */
10140
10141static bool
10142s390_keep_leaf_when_profiled ()
10143{
10144 return true;
10145}
5a3fe9b6 10146
ab96de7e
AS		 10147/* Output assembly code for the trampoline template to
10148 stdio stream FILE.
10149
10150 On S/390, we use gpr 1 internally in the trampoline code;
10151 gpr 0 is used to hold the static chain. */
10152
b81ecf6f
RH		 10153static void
10154s390_asm_trampoline_template (FILE *file)
ab96de7e
AS		 10155{
10156 rtx op[2];
10157 op[0] = gen_rtx_REG (Pmode, 0);
10158 op[1] = gen_rtx_REG (Pmode, 1);
10159
10160 if (TARGET_64BIT)
10161 {
cab78b15
AK		 10162 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
10163 output_asm_insn ("lmg\t%0,%1,14(%1)", op); /* 6 byte */
10164 output_asm_insn ("br\t%1", op); /* 2 byte */
ab96de7e
AS		 10165 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
10166 }
10167 else
10168 {
cab78b15
AK		 10169 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
10170 output_asm_insn ("lm\t%0,%1,6(%1)", op); /* 4 byte */
10171 output_asm_insn ("br\t%1", op); /* 2 byte */
ab96de7e
AS		 10172 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
10173 }
10174}
10175
10176/* Emit RTL insns to initialize the variable parts of a trampoline.
10177 FNADDR is an RTX for the address of the function's pure code.
10178 CXT is an RTX for the static chain value for the function. */
10179
b81ecf6f
RH		 10180static void
10181s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
ab96de7e 10182{
b81ecf6f
RH		 10183 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
10184 rtx mem;
3a892e44 10185
b81ecf6f 10186 emit_block_move (m_tramp, assemble_trampoline_template (),
cab78b15 10187 GEN_INT (2 * UNITS_PER_LONG), BLOCK_OP_NORMAL);
b81ecf6f 10188
cab78b15 10189 mem = adjust_address (m_tramp, Pmode, 2 * UNITS_PER_LONG);
b81ecf6f 10190 emit_move_insn (mem, cxt);
cab78b15 10191 mem = adjust_address (m_tramp, Pmode, 3 * UNITS_PER_LONG);
b81ecf6f 10192 emit_move_insn (mem, fnaddr);
ab96de7e
AS		 10193}
10194
ab96de7e
AS		 10195/* Output assembler code to FILE to increment profiler label # LABELNO
10196 for profiling a function entry. */
10197
10198void
10199s390_function_profiler (FILE *file, int labelno)
10200{
10201 rtx op[7];
10202
10203 char label[128];
10204 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
10205
10206 fprintf (file, "# function profiler \n");
10207
10208 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
10209 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
0a81f074 10210 op[1] = gen_rtx_MEM (Pmode, plus_constant (Pmode, op[1], UNITS_PER_LONG));
ab96de7e
AS		 10211
10212 op[2] = gen_rtx_REG (Pmode, 1);
10213 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
10214 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
10215
10216 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
10217 if (flag_pic)
10218 {
10219 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
10220 op[4] = gen_rtx_CONST (Pmode, op[4]);
10221 }
10222
10223 if (TARGET_64BIT)
10224 {
10225 output_asm_insn ("stg\t%0,%1", op);
10226 output_asm_insn ("larl\t%2,%3", op);
10227 output_asm_insn ("brasl\t%0,%4", op);
10228 output_asm_insn ("lg\t%0,%1", op);
10229 }
10230 else if (!flag_pic)
10231 {
10232 op[6] = gen_label_rtx ();
10233
10234 output_asm_insn ("st\t%0,%1", op);
10235 output_asm_insn ("bras\t%2,%l6", op);
10236 output_asm_insn (".long\t%4", op);
10237 output_asm_insn (".long\t%3", op);
10238 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
10239 output_asm_insn ("l\t%0,0(%2)", op);
10240 output_asm_insn ("l\t%2,4(%2)", op);
10241 output_asm_insn ("basr\t%0,%0", op);
10242 output_asm_insn ("l\t%0,%1", op);
10243 }
10244 else
10245 {
10246 op[5] = gen_label_rtx ();
10247 op[6] = gen_label_rtx ();
10248
10249 output_asm_insn ("st\t%0,%1", op);
10250 output_asm_insn ("bras\t%2,%l6", op);
10251 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
10252 output_asm_insn (".long\t%4-%l5", op);
10253 output_asm_insn (".long\t%3-%l5", op);
10254 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
10255 output_asm_insn ("lr\t%0,%2", op);
10256 output_asm_insn ("a\t%0,0(%2)", op);
10257 output_asm_insn ("a\t%2,4(%2)", op);
10258 output_asm_insn ("basr\t%0,%0", op);
10259 output_asm_insn ("l\t%0,%1", op);
10260 }
10261}
10262
10263/* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
10264 into its SYMBOL_REF_FLAGS. */
10265
10266static void
10267s390_encode_section_info (tree decl, rtx rtl, int first)
10268{
10269 default_encode_section_info (decl, rtl, first);
10270
963fc8d0
AK		 10271 if (TREE_CODE (decl) == VAR_DECL)
10272 {
10273 /* If a variable has a forced alignment to < 2 bytes, mark it
10274 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
10275 operand. */
10276 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
10277 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
10278 if (!DECL_SIZE (decl)
10279 || !DECL_ALIGN (decl)
9541ffee 10280 || !tree_fits_shwi_p (DECL_SIZE (decl))
963fc8d0 10281 || (DECL_ALIGN (decl) <= 64
9439e9a1 10282 && DECL_ALIGN (decl) != tree_to_shwi (DECL_SIZE (decl))))
963fc8d0
AK		 10283 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
10284 }
10285
10286 /* Literal pool references don't have a decl so they are handled
10287 differently here. We rely on the information in the MEM_ALIGN
10288 entry to decide upon natural alignment. */
10289 if (MEM_P (rtl)
10290 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
10291 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
10292 && (MEM_ALIGN (rtl) == 0
35fcb6ba 10293 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
963fc8d0
AK		 10294 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
10295 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
ab96de7e
AS		 10296}
10297
10298/* Output thunk to FILE that implements a C++ virtual function call (with
10299 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
10300 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
10301 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
10302 relative to the resulting this pointer. */
10303
10304static void
10305s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
10306 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10307 tree function)
10308{
10309 rtx op[10];
10310 int nonlocal = 0;
10311
81ef7e24
JJ		 10312 /* Make sure unwind info is emitted for the thunk if needed. */
10313 final_start_function (emit_barrier (), file, 1);
10314
ab96de7e
AS		 10315 /* Operand 0 is the target function. */
10316 op[0] = XEXP (DECL_RTL (function), 0);
10317 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
10318 {
10319 nonlocal = 1;
10320 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
10321 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
10322 op[0] = gen_rtx_CONST (Pmode, op[0]);
10323 }
10324
10325 /* Operand 1 is the 'this' pointer. */
10326 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
10327 op[1] = gen_rtx_REG (Pmode, 3);
10328 else
10329 op[1] = gen_rtx_REG (Pmode, 2);
10330
10331 /* Operand 2 is the delta. */
10332 op[2] = GEN_INT (delta);
10333
10334 /* Operand 3 is the vcall_offset. */
10335 op[3] = GEN_INT (vcall_offset);
10336
10337 /* Operand 4 is the temporary register. */
10338 op[4] = gen_rtx_REG (Pmode, 1);
10339
10340 /* Operands 5 to 8 can be used as labels. */
10341 op[5] = NULL_RTX;
10342 op[6] = NULL_RTX;
10343 op[7] = NULL_RTX;
10344 op[8] = NULL_RTX;
10345
10346 /* Operand 9 can be used for temporary register. */
10347 op[9] = NULL_RTX;
10348
10349 /* Generate code. */
10350 if (TARGET_64BIT)
10351 {
10352 /* Setup literal pool pointer if required. */
10353 if ((!DISP_IN_RANGE (delta)
ec24698e
UW		 10354 && !CONST_OK_FOR_K (delta)
10355 && !CONST_OK_FOR_Os (delta))
ab96de7e 10356 || (!DISP_IN_RANGE (vcall_offset)
ec24698e
UW		 10357 && !CONST_OK_FOR_K (vcall_offset)
10358 && !CONST_OK_FOR_Os (vcall_offset)))
ab96de7e
AS		 10359 {
10360 op[5] = gen_label_rtx ();
10361 output_asm_insn ("larl\t%4,%5", op);
10362 }
10363
10364 /* Add DELTA to this pointer. */
10365 if (delta)
10366 {
b5c67a49 10367 if (CONST_OK_FOR_J (delta))
ab96de7e
AS		 10368 output_asm_insn ("la\t%1,%2(%1)", op);
10369 else if (DISP_IN_RANGE (delta))
10370 output_asm_insn ("lay\t%1,%2(%1)", op);
b5c67a49 10371 else if (CONST_OK_FOR_K (delta))
ab96de7e 10372 output_asm_insn ("aghi\t%1,%2", op);
ec24698e
UW		 10373 else if (CONST_OK_FOR_Os (delta))
10374 output_asm_insn ("agfi\t%1,%2", op);
ab96de7e
AS		 10375 else
10376 {
10377 op[6] = gen_label_rtx ();
10378 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
10379 }
10380 }
10381
10382 /* Perform vcall adjustment. */
10383 if (vcall_offset)
10384 {
10385 if (DISP_IN_RANGE (vcall_offset))
10386 {
10387 output_asm_insn ("lg\t%4,0(%1)", op);
10388 output_asm_insn ("ag\t%1,%3(%4)", op);
10389 }
b5c67a49 10390 else if (CONST_OK_FOR_K (vcall_offset))
ab96de7e
AS		 10391 {
10392 output_asm_insn ("lghi\t%4,%3", op);
10393 output_asm_insn ("ag\t%4,0(%1)", op);
10394 output_asm_insn ("ag\t%1,0(%4)", op);
10395 }
ec24698e
UW		 10396 else if (CONST_OK_FOR_Os (vcall_offset))
10397 {
10398 output_asm_insn ("lgfi\t%4,%3", op);
10399 output_asm_insn ("ag\t%4,0(%1)", op);
10400 output_asm_insn ("ag\t%1,0(%4)", op);
10401 }
ab96de7e
AS		 10402 else
10403 {
10404 op[7] = gen_label_rtx ();
10405 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
10406 output_asm_insn ("ag\t%4,0(%1)", op);
10407 output_asm_insn ("ag\t%1,0(%4)", op);
10408 }
10409 }
10410
10411 /* Jump to target. */
10412 output_asm_insn ("jg\t%0", op);
10413
10414 /* Output literal pool if required. */
10415 if (op[5])
10416 {
10417 output_asm_insn (".align\t4", op);
10418 targetm.asm_out.internal_label (file, "L",
10419 CODE_LABEL_NUMBER (op[5]));
10420 }
10421 if (op[6])
10422 {
10423 targetm.asm_out.internal_label (file, "L",
10424 CODE_LABEL_NUMBER (op[6]));
10425 output_asm_insn (".long\t%2", op);
10426 }
10427 if (op[7])
10428 {
10429 targetm.asm_out.internal_label (file, "L",
10430 CODE_LABEL_NUMBER (op[7]));
10431 output_asm_insn (".long\t%3", op);
10432 }
10433 }
10434 else
10435 {
10436 /* Setup base pointer if required. */
10437 if (!vcall_offset
10438 || (!DISP_IN_RANGE (delta)
ec24698e
UW		 10439 && !CONST_OK_FOR_K (delta)
10440 && !CONST_OK_FOR_Os (delta))
ab96de7e 10441 || (!DISP_IN_RANGE (delta)
ec24698e
UW		 10442 && !CONST_OK_FOR_K (vcall_offset)
10443 && !CONST_OK_FOR_Os (vcall_offset)))
ab96de7e
AS		 10444 {
10445 op[5] = gen_label_rtx ();
10446 output_asm_insn ("basr\t%4,0", op);
10447 targetm.asm_out.internal_label (file, "L",
10448 CODE_LABEL_NUMBER (op[5]));
10449 }
10450
10451 /* Add DELTA to this pointer. */
10452 if (delta)
10453 {
b5c67a49 10454 if (CONST_OK_FOR_J (delta))
ab96de7e
AS		 10455 output_asm_insn ("la\t%1,%2(%1)", op);
10456 else if (DISP_IN_RANGE (delta))
10457 output_asm_insn ("lay\t%1,%2(%1)", op);
b5c67a49 10458 else if (CONST_OK_FOR_K (delta))
ab96de7e 10459 output_asm_insn ("ahi\t%1,%2", op);
ec24698e
UW		 10460 else if (CONST_OK_FOR_Os (delta))
10461 output_asm_insn ("afi\t%1,%2", op);
ab96de7e
AS		 10462 else
10463 {
10464 op[6] = gen_label_rtx ();
10465 output_asm_insn ("a\t%1,%6-%5(%4)", op);
10466 }
10467 }
10468
10469 /* Perform vcall adjustment. */
10470 if (vcall_offset)
10471 {
b5c67a49 10472 if (CONST_OK_FOR_J (vcall_offset))
ab96de7e 10473 {
c4d50129 10474 output_asm_insn ("l\t%4,0(%1)", op);
ab96de7e
AS		 10475 output_asm_insn ("a\t%1,%3(%4)", op);
10476 }
10477 else if (DISP_IN_RANGE (vcall_offset))
10478 {
c4d50129 10479 output_asm_insn ("l\t%4,0(%1)", op);
ab96de7e
AS		 10480 output_asm_insn ("ay\t%1,%3(%4)", op);
10481 }
b5c67a49 10482 else if (CONST_OK_FOR_K (vcall_offset))
ab96de7e
AS		 10483 {
10484 output_asm_insn ("lhi\t%4,%3", op);
10485 output_asm_insn ("a\t%4,0(%1)", op);
10486 output_asm_insn ("a\t%1,0(%4)", op);
10487 }
ec24698e
UW		 10488 else if (CONST_OK_FOR_Os (vcall_offset))
10489 {
10490 output_asm_insn ("iilf\t%4,%3", op);
10491 output_asm_insn ("a\t%4,0(%1)", op);
10492 output_asm_insn ("a\t%1,0(%4)", op);
10493 }
ab96de7e
AS		 10494 else
10495 {
10496 op[7] = gen_label_rtx ();
10497 output_asm_insn ("l\t%4,%7-%5(%4)", op);
10498 output_asm_insn ("a\t%4,0(%1)", op);
10499 output_asm_insn ("a\t%1,0(%4)", op);
10500 }
9db1d521 10501
ab96de7e
AS		 10502 /* We had to clobber the base pointer register.
10503 Re-setup the base pointer (with a different base). */
10504 op[5] = gen_label_rtx ();
10505 output_asm_insn ("basr\t%4,0", op);
10506 targetm.asm_out.internal_label (file, "L",
10507 CODE_LABEL_NUMBER (op[5]));
10508 }
9db1d521 10509
ab96de7e
AS		 10510 /* Jump to target. */
10511 op[8] = gen_label_rtx ();
9db1d521 10512
ab96de7e
AS		 10513 if (!flag_pic)
10514 output_asm_insn ("l\t%4,%8-%5(%4)", op);
10515 else if (!nonlocal)
10516 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10517 /* We cannot call through .plt, since .plt requires %r12 loaded. */
10518 else if (flag_pic == 1)
10519 {
10520 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10521 output_asm_insn ("l\t%4,%0(%4)", op);
10522 }
10523 else if (flag_pic == 2)
10524 {
10525 op[9] = gen_rtx_REG (Pmode, 0);
10526 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
10527 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10528 output_asm_insn ("ar\t%4,%9", op);
10529 output_asm_insn ("l\t%4,0(%4)", op);
10530 }
9db1d521 10531
ab96de7e 10532 output_asm_insn ("br\t%4", op);
9db1d521 10533
ab96de7e
AS		 10534 /* Output literal pool. */
10535 output_asm_insn (".align\t4", op);
9db1d521 10536
ab96de7e
AS		 10537 if (nonlocal && flag_pic == 2)
10538 output_asm_insn (".long\t%0", op);
10539 if (nonlocal)
10540 {
10541 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
10542 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
10543 }
63694b5e 10544
ab96de7e
AS		 10545 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
10546 if (!flag_pic)
10547 output_asm_insn (".long\t%0", op);
10548 else
10549 output_asm_insn (".long\t%0-%5", op);
9db1d521 10550
ab96de7e
AS		 10551 if (op[6])
10552 {
10553 targetm.asm_out.internal_label (file, "L",
10554 CODE_LABEL_NUMBER (op[6]));
10555 output_asm_insn (".long\t%2", op);
10556 }
10557 if (op[7])
10558 {
10559 targetm.asm_out.internal_label (file, "L",
10560 CODE_LABEL_NUMBER (op[7]));
10561 output_asm_insn (".long\t%3", op);
10562 }
9db1d521 10563 }
81ef7e24 10564 final_end_function ();
9db1d521
HP		 10565}
10566
ab96de7e 10567static bool
ef4bddc2 10568s390_valid_pointer_mode (machine_mode mode)
ab96de7e
AS		 10569{
10570 return (mode == SImode || (TARGET_64BIT && mode == DImode));
10571}
994fe660 10572
9a6f71b4 10573/* Checks whether the given CALL_EXPR would use a caller
ab96de7e
AS		 10574 saved register. This is used to decide whether sibling call
10575 optimization could be performed on the respective function
10576 call. */
fd3cd001 10577
ab96de7e 10578static bool
9a6f71b4 10579s390_call_saved_register_used (tree call_expr)
fd3cd001 10580{
d5cc9181
JR		 10581 CUMULATIVE_ARGS cum_v;
10582 cumulative_args_t cum;
ab96de7e 10583 tree parameter;
ef4bddc2 10584 machine_mode mode;
ab96de7e
AS		 10585 tree type;
10586 rtx parm_rtx;
9a6f71b4 10587 int reg, i;
fd3cd001 10588
d5cc9181
JR		 10589 INIT_CUMULATIVE_ARGS (cum_v, NULL, NULL, 0, 0);
10590 cum = pack_cumulative_args (&cum_v);
fd3cd001 10591
9a6f71b4 10592 for (i = 0; i < call_expr_nargs (call_expr); i++)
ab96de7e 10593 {
9a6f71b4 10594 parameter = CALL_EXPR_ARG (call_expr, i);
8d933e31 10595 gcc_assert (parameter);
fd3cd001 10596
ab96de7e
AS		 10597 /* For an undeclared variable passed as parameter we will get
10598 an ERROR_MARK node here. */
10599 if (TREE_CODE (parameter) == ERROR_MARK)
10600 return true;
fd3cd001 10601
8d933e31
AS		 10602 type = TREE_TYPE (parameter);
10603 gcc_assert (type);
fd3cd001 10604
8d933e31
AS		 10605 mode = TYPE_MODE (type);
10606 gcc_assert (mode);
fd3cd001 10607
d5cc9181 10608 if (pass_by_reference (&cum_v, mode, type, true))
ab96de7e
AS		 10609 {
10610 mode = Pmode;
10611 type = build_pointer_type (type);
10612 }
fd3cd001 10613
d5cc9181 10614 parm_rtx = s390_function_arg (cum, mode, type, 0);
fd3cd001 10615
d5cc9181 10616 s390_function_arg_advance (cum, mode, type, 0);
fd3cd001 10617
9602b6a1
AK		 10618 if (!parm_rtx)
10619 continue;
10620
10621 if (REG_P (parm_rtx))
10622 {
e8de8fea
AK		 10623 for (reg = 0;
10624 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
10625 reg++)
9602b6a1
AK		 10626 if (!call_used_regs[reg + REGNO (parm_rtx)])
10627 return true;
10628 }
10629
10630 if (GET_CODE (parm_rtx) == PARALLEL)
ab96de7e 10631 {
9602b6a1 10632 int i;
e8de8fea 10633
9602b6a1
AK		 10634 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
10635 {
10636 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
9602b6a1
AK		 10637
10638 gcc_assert (REG_P (r));
10639
e8de8fea
AK		 10640 for (reg = 0;
10641 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
10642 reg++)
9602b6a1
AK		 10643 if (!call_used_regs[reg + REGNO (r)])
10644 return true;
10645 }
ab96de7e 10646 }
9602b6a1 10647
ab96de7e
AS		 10648 }
10649 return false;
10650}
fd3cd001 10651
ab96de7e
AS		 10652/* Return true if the given call expression can be
10653 turned into a sibling call.
10654 DECL holds the declaration of the function to be called whereas
10655 EXP is the call expression itself. */
fd3cd001 10656
ab96de7e
AS		 10657static bool
10658s390_function_ok_for_sibcall (tree decl, tree exp)
10659{
10660 /* The TPF epilogue uses register 1. */
10661 if (TARGET_TPF_PROFILING)
10662 return false;
fd3cd001 10663
ab96de7e
AS		 10664 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
10665 which would have to be restored before the sibcall. */
7691ec4e 10666 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
ab96de7e 10667 return false;
fd3cd001 10668
ab96de7e
AS		 10669 /* Register 6 on s390 is available as an argument register but unfortunately
10670 "caller saved". This makes functions needing this register for arguments
10671 not suitable for sibcalls. */
9a6f71b4 10672 return !s390_call_saved_register_used (exp);
ab96de7e 10673}
fd3cd001 10674
ab96de7e 10675/* Return the fixed registers used for condition codes. */
fd3cd001 10676
ab96de7e
AS		 10677static bool
10678s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
10679{
10680 *p1 = CC_REGNUM;
10681 *p2 = INVALID_REGNUM;
f4aa3848 10682
ab96de7e
AS		 10683 return true;
10684}
fd3cd001 10685
ab96de7e
AS		 10686/* This function is used by the call expanders of the machine description.
10687 It emits the call insn itself together with the necessary operations
10688 to adjust the target address and returns the emitted insn.
10689 ADDR_LOCATION is the target address rtx
10690 TLS_CALL the location of the thread-local symbol
10691 RESULT_REG the register where the result of the call should be stored
10692 RETADDR_REG the register where the return address should be stored
10693 If this parameter is NULL_RTX the call is considered
10694 to be a sibling call. */
fd3cd001 10695
775c43d3 10696rtx_insn *
ab96de7e
AS		 10697s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
10698 rtx retaddr_reg)
9db1d521 10699{
ab96de7e 10700 bool plt_call = false;
775c43d3 10701 rtx_insn *insn;
ab96de7e
AS		 10702 rtx call;
10703 rtx clobber;
10704 rtvec vec;
cadc42db 10705
ab96de7e
AS		 10706 /* Direct function calls need special treatment. */
10707 if (GET_CODE (addr_location) == SYMBOL_REF)
9db1d521 10708 {
ab96de7e
AS		 10709 /* When calling a global routine in PIC mode, we must
10710 replace the symbol itself with the PLT stub. */
10711 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
10712 {
72e2cf16
AK		 10713 if (retaddr_reg != NULL_RTX)
10714 {
10715 addr_location = gen_rtx_UNSPEC (Pmode,
10716 gen_rtvec (1, addr_location),
10717 UNSPEC_PLT);
10718 addr_location = gen_rtx_CONST (Pmode, addr_location);
10719 plt_call = true;
10720 }
10721 else
10722 /* For -fpic code the PLT entries might use r12 which is
10723 call-saved. Therefore we cannot do a sibcall when
10724 calling directly using a symbol ref. When reaching
10725 this point we decided (in s390_function_ok_for_sibcall)
10726 to do a sibcall for a function pointer but one of the
10727 optimizers was able to get rid of the function pointer
10728 by propagating the symbol ref into the call. This
10729 optimization is illegal for S/390 so we turn the direct
10730 call into a indirect call again. */
10731 addr_location = force_reg (Pmode, addr_location);
ab96de7e
AS		 10732 }
10733
10734 /* Unless we can use the bras(l) insn, force the
10735 routine address into a register. */
10736 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
10737 {
10738 if (flag_pic)
10739 addr_location = legitimize_pic_address (addr_location, 0);
10740 else
10741 addr_location = force_reg (Pmode, addr_location);
10742 }
9db1d521 10743 }
ab96de7e
AS		 10744
10745 /* If it is already an indirect call or the code above moved the
10746 SYMBOL_REF to somewhere else make sure the address can be found in
10747 register 1. */
10748 if (retaddr_reg == NULL_RTX
10749 && GET_CODE (addr_location) != SYMBOL_REF
10750 && !plt_call)
9db1d521 10751 {
ab96de7e
AS		 10752 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
10753 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
9db1d521 10754 }
9db1d521 10755
ab96de7e
AS		 10756 addr_location = gen_rtx_MEM (QImode, addr_location);
10757 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
4023fb28 10758
ab96de7e
AS		 10759 if (result_reg != NULL_RTX)
10760 call = gen_rtx_SET (VOIDmode, result_reg, call);
4023fb28 10761
ab96de7e
AS		 10762 if (retaddr_reg != NULL_RTX)
10763 {
10764 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
c7453384 10765
ab96de7e
AS		 10766 if (tls_call != NULL_RTX)
10767 vec = gen_rtvec (3, call, clobber,
10768 gen_rtx_USE (VOIDmode, tls_call));
10769 else
10770 vec = gen_rtvec (2, call, clobber);
4023fb28 10771
ab96de7e
AS		 10772 call = gen_rtx_PARALLEL (VOIDmode, vec);
10773 }
4023fb28 10774
ab96de7e 10775 insn = emit_call_insn (call);
4023fb28 10776
ab96de7e
AS		 10777 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
10778 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
10779 {
10780 /* s390_function_ok_for_sibcall should
10781 have denied sibcalls in this case. */
8d933e31 10782 gcc_assert (retaddr_reg != NULL_RTX);
68c0ef75 10783 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, 12));
ab96de7e
AS		 10784 }
10785 return insn;
10786}
4023fb28 10787
5efd84c5 10788/* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
4023fb28 10789
5efd84c5 10790static void
ab96de7e
AS		 10791s390_conditional_register_usage (void)
10792{
10793 int i;
4023fb28 10794
4023fb28
UW		 10795 if (flag_pic)
10796 {
ab96de7e
AS		 10797 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10798 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
4023fb28 10799 }
ab96de7e 10800 if (TARGET_CPU_ZARCH)
4023fb28 10801 {
7633f08e
UW		 10802 fixed_regs[BASE_REGNUM] = 0;
10803 call_used_regs[BASE_REGNUM] = 0;
ab96de7e
AS		 10804 fixed_regs[RETURN_REGNUM] = 0;
10805 call_used_regs[RETURN_REGNUM] = 0;
4023fb28 10806 }
ab96de7e 10807 if (TARGET_64BIT)
4023fb28 10808 {
2cf4c39e 10809 for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++)
ab96de7e 10810 call_used_regs[i] = call_really_used_regs[i] = 0;
4023fb28
UW		 10811 }
10812 else
10813 {
2cf4c39e
AK		 10814 call_used_regs[FPR4_REGNUM] = call_really_used_regs[FPR4_REGNUM] = 0;
10815 call_used_regs[FPR6_REGNUM] = call_really_used_regs[FPR6_REGNUM] = 0;
ab96de7e 10816 }
4023fb28 10817
ab96de7e
AS		 10818 if (TARGET_SOFT_FLOAT)
10819 {
2cf4c39e 10820 for (i = FPR0_REGNUM; i <= FPR15_REGNUM; i++)
ab96de7e 10821 call_used_regs[i] = fixed_regs[i] = 1;
4023fb28
UW		 10822 }
10823}
10824
ab96de7e 10825/* Corresponding function to eh_return expander. */
fb49053f 10826
ab96de7e
AS		 10827static GTY(()) rtx s390_tpf_eh_return_symbol;
10828void
10829s390_emit_tpf_eh_return (rtx target)
fb49053f 10830{
775c43d3
DM		 10831 rtx_insn *insn;
10832 rtx reg, orig_ra;
e23795ea 10833
ab96de7e
AS		 10834 if (!s390_tpf_eh_return_symbol)
10835 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
10836
10837 reg = gen_rtx_REG (Pmode, 2);
87cb0c0c 10838 orig_ra = gen_rtx_REG (Pmode, 3);
ab96de7e
AS		 10839
10840 emit_move_insn (reg, target);
87cb0c0c 10841 emit_move_insn (orig_ra, get_hard_reg_initial_val (Pmode, RETURN_REGNUM));
ab96de7e
AS		 10842 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
10843 gen_rtx_REG (Pmode, RETURN_REGNUM));
10844 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
87cb0c0c 10845 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), orig_ra);
ab96de7e
AS		 10846
10847 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
fd3cd001
UW		 10848}
10849
ab96de7e
AS		 10850/* Rework the prologue/epilogue to avoid saving/restoring
10851 registers unnecessarily. */
3062825f 10852
c590b625 10853static void
ab96de7e 10854s390_optimize_prologue (void)
483ab821 10855{
775c43d3 10856 rtx_insn *insn, *new_insn, *next_insn;
3062825f 10857
ab96de7e 10858 /* Do a final recompute of the frame-related data. */
6455a49e 10859 s390_optimize_register_info ();
3062825f 10860
ab96de7e
AS		 10861 /* If all special registers are in fact used, there's nothing we
10862 can do, so no point in walking the insn list. */
3062825f 10863
f4aa3848 10864 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
ab96de7e 10865 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
f4aa3848
AK		 10866 && (TARGET_CPU_ZARCH
10867 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
ab96de7e
AS		 10868 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
10869 return;
3062825f 10870
ab96de7e 10871 /* Search for prologue/epilogue insns and replace them. */
3062825f 10872
ab96de7e
AS		 10873 for (insn = get_insns (); insn; insn = next_insn)
10874 {
10875 int first, last, off;
10876 rtx set, base, offset;
6455a49e 10877 rtx pat;
3062825f 10878
ab96de7e 10879 next_insn = NEXT_INSN (insn);
89ce1c8f 10880
6455a49e 10881 if (! NONJUMP_INSN_P (insn) || ! RTX_FRAME_RELATED_P (insn))
ab96de7e 10882 continue;
3062825f 10883
6455a49e
AK		 10884 pat = PATTERN (insn);
10885
10886 /* Remove ldgr/lgdr instructions used for saving and restore
10887 GPRs if possible. */
10888 if (TARGET_Z10
10889 && GET_CODE (pat) == SET
10890 && GET_MODE (SET_SRC (pat)) == DImode
10891 && REG_P (SET_SRC (pat))
10892 && REG_P (SET_DEST (pat)))
10893 {
10894 int src_regno = REGNO (SET_SRC (pat));
10895 int dest_regno = REGNO (SET_DEST (pat));
10896 int gpr_regno;
10897 int fpr_regno;
10898
10899 if (!((GENERAL_REGNO_P (src_regno) && FP_REGNO_P (dest_regno))
10900 || (FP_REGNO_P (src_regno) && GENERAL_REGNO_P (dest_regno))))
10901 continue;
10902
10903 gpr_regno = GENERAL_REGNO_P (src_regno) ? src_regno : dest_regno;
10904 fpr_regno = FP_REGNO_P (src_regno) ? src_regno : dest_regno;
10905
10906 /* GPR must be call-saved, FPR must be call-clobbered. */
10907 if (!call_really_used_regs[fpr_regno]
10908 || call_really_used_regs[gpr_regno])
10909 continue;
10910
6455a49e
AK		 10911 /* It must not happen that what we once saved in an FPR now
10912 needs a stack slot. */
10913 gcc_assert (cfun_gpr_save_slot (gpr_regno) != -1);
10914
10915 if (cfun_gpr_save_slot (gpr_regno) == 0)
10916 {
10917 remove_insn (insn);
10918 continue;
10919 }
10920 }
10921
10922 if (GET_CODE (pat) == PARALLEL
10923 && store_multiple_operation (pat, VOIDmode))
3062825f 10924 {
6455a49e 10925 set = XVECEXP (pat, 0, 0);
ab96de7e 10926 first = REGNO (SET_SRC (set));
6455a49e 10927 last = first + XVECLEN (pat, 0) - 1;
ab96de7e
AS		 10928 offset = const0_rtx;
10929 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10930 off = INTVAL (offset);
3062825f 10931
ab96de7e
AS		 10932 if (GET_CODE (base) != REG || off < 0)
10933 continue;
22a707a4
AK		 10934 if (cfun_frame_layout.first_save_gpr != -1
10935 && (cfun_frame_layout.first_save_gpr < first
10936 || cfun_frame_layout.last_save_gpr > last))
10937 continue;
ab96de7e
AS		 10938 if (REGNO (base) != STACK_POINTER_REGNUM
10939 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10940 continue;
10941 if (first > BASE_REGNUM || last < BASE_REGNUM)
10942 continue;
10943
10944 if (cfun_frame_layout.first_save_gpr != -1)
3062825f 10945 {
775c43d3 10946 rtx s_pat = save_gprs (base,
ab96de7e 10947 off + (cfun_frame_layout.first_save_gpr
9602b6a1 10948 - first) * UNITS_PER_LONG,
ab96de7e
AS		 10949 cfun_frame_layout.first_save_gpr,
10950 cfun_frame_layout.last_save_gpr);
775c43d3 10951 new_insn = emit_insn_before (s_pat, insn);
ab96de7e 10952 INSN_ADDRESSES_NEW (new_insn, -1);
3062825f 10953 }
3062825f 10954
ab96de7e
AS		 10955 remove_insn (insn);
10956 continue;
3062825f
UW		 10957 }
10958
22a707a4 10959 if (cfun_frame_layout.first_save_gpr == -1
6455a49e
AK		 10960 && GET_CODE (pat) == SET
10961 && GENERAL_REG_P (SET_SRC (pat))
10962 && GET_CODE (SET_DEST (pat)) == MEM)
3062825f 10963 {
6455a49e 10964 set = pat;
ab96de7e
AS		 10965 first = REGNO (SET_SRC (set));
10966 offset = const0_rtx;
10967 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10968 off = INTVAL (offset);
3062825f 10969
ab96de7e
AS		 10970 if (GET_CODE (base) != REG || off < 0)
10971 continue;
10972 if (REGNO (base) != STACK_POINTER_REGNUM
10973 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10974 continue;
3062825f 10975
ab96de7e
AS		 10976 remove_insn (insn);
10977 continue;
3062825f
UW		 10978 }
10979
6455a49e
AK		 10980 if (GET_CODE (pat) == PARALLEL
10981 && load_multiple_operation (pat, VOIDmode))
89ce1c8f 10982 {
6455a49e 10983 set = XVECEXP (pat, 0, 0);
ab96de7e 10984 first = REGNO (SET_DEST (set));
6455a49e 10985 last = first + XVECLEN (pat, 0) - 1;
ab96de7e
AS		 10986 offset = const0_rtx;
10987 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10988 off = INTVAL (offset);
89ce1c8f 10989
ab96de7e
AS		 10990 if (GET_CODE (base) != REG || off < 0)
10991 continue;
6455a49e 10992
22a707a4
AK		 10993 if (cfun_frame_layout.first_restore_gpr != -1
10994 && (cfun_frame_layout.first_restore_gpr < first
10995 || cfun_frame_layout.last_restore_gpr > last))
10996 continue;
ab96de7e
AS		 10997 if (REGNO (base) != STACK_POINTER_REGNUM
10998 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10999 continue;
11000 if (first > BASE_REGNUM || last < BASE_REGNUM)
11001 continue;
3062825f 11002
ab96de7e
AS		 11003 if (cfun_frame_layout.first_restore_gpr != -1)
11004 {
775c43d3 11005 rtx rpat = restore_gprs (base,
ab96de7e 11006 off + (cfun_frame_layout.first_restore_gpr
9602b6a1 11007 - first) * UNITS_PER_LONG,
ab96de7e
AS		 11008 cfun_frame_layout.first_restore_gpr,
11009 cfun_frame_layout.last_restore_gpr);
0621cf3c
RS		 11010
11011 /* Remove REG_CFA_RESTOREs for registers that we no
11012 longer need to save. */
775c43d3
DM		 11013 REG_NOTES (rpat) = REG_NOTES (insn);
11014 for (rtx *ptr = &REG_NOTES (rpat); *ptr; )
0621cf3c
RS		 11015 if (REG_NOTE_KIND (*ptr) == REG_CFA_RESTORE
11016 && ((int) REGNO (XEXP (*ptr, 0))
11017 < cfun_frame_layout.first_restore_gpr))
11018 *ptr = XEXP (*ptr, 1);
11019 else
11020 ptr = &XEXP (*ptr, 1);
775c43d3 11021 new_insn = emit_insn_before (rpat, insn);
0621cf3c 11022 RTX_FRAME_RELATED_P (new_insn) = 1;
ab96de7e
AS		 11023 INSN_ADDRESSES_NEW (new_insn, -1);
11024 }
89ce1c8f 11025
ab96de7e
AS		 11026 remove_insn (insn);
11027 continue;
89ce1c8f
JJ		 11028 }
11029
22a707a4 11030 if (cfun_frame_layout.first_restore_gpr == -1
6455a49e
AK		 11031 && GET_CODE (pat) == SET
11032 && GENERAL_REG_P (SET_DEST (pat))
11033 && GET_CODE (SET_SRC (pat)) == MEM)
3062825f 11034 {
6455a49e 11035 set = pat;
ab96de7e
AS		 11036 first = REGNO (SET_DEST (set));
11037 offset = const0_rtx;
11038 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
11039 off = INTVAL (offset);
c7453384 11040
ab96de7e
AS		 11041 if (GET_CODE (base) != REG || off < 0)
11042 continue;
6455a49e 11043
ab96de7e
AS		 11044 if (REGNO (base) != STACK_POINTER_REGNUM
11045 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
11046 continue;
29742ba4 11047
ab96de7e
AS		 11048 remove_insn (insn);
11049 continue;
11050 }
11051 }
29742ba4
HP		 11052}
11053
65b1d8ea
AK		 11054/* On z10 and later the dynamic branch prediction must see the
11055 backward jump within a certain windows. If not it falls back to
11056 the static prediction. This function rearranges the loop backward
11057 branch in a way which makes the static prediction always correct.
11058 The function returns true if it added an instruction. */
b0f86a7e 11059static bool
775c43d3 11060s390_fix_long_loop_prediction (rtx_insn *insn)
b0f86a7e
AK		 11061{
11062 rtx set = single_set (insn);
11063 rtx code_label, label_ref, new_label;
e60365d3 11064 rtx_insn *uncond_jump;
775c43d3 11065 rtx_insn *cur_insn;
b0f86a7e
AK		 11066 rtx tmp;
11067 int distance;
11068
11069 /* This will exclude branch on count and branch on index patterns
11070 since these are correctly statically predicted. */
11071 if (!set
11072 || SET_DEST (set) != pc_rtx
11073 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
11074 return false;
11075
177bc204
RS		 11076 /* Skip conditional returns. */
11077 if (ANY_RETURN_P (XEXP (SET_SRC (set), 1))
11078 && XEXP (SET_SRC (set), 2) == pc_rtx)
11079 return false;
11080
b0f86a7e
AK		 11081 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
11082 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
11083
11084 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
11085
11086 code_label = XEXP (label_ref, 0);
11087
11088 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
11089 || INSN_ADDRESSES (INSN_UID (insn)) == -1
11090 || (INSN_ADDRESSES (INSN_UID (insn))
65b1d8ea 11091 - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE))
b0f86a7e
AK		 11092 return false;
11093
11094 for (distance = 0, cur_insn = PREV_INSN (insn);
65b1d8ea 11095 distance < PREDICT_DISTANCE - 6;
b0f86a7e
AK		 11096 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
11097 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
11098 return false;
11099
11100 new_label = gen_label_rtx ();
11101 uncond_jump = emit_jump_insn_after (
11102 gen_rtx_SET (VOIDmode, pc_rtx,
11103 gen_rtx_LABEL_REF (VOIDmode, code_label)),
11104 insn);
11105 emit_label_after (new_label, uncond_jump);
11106
11107 tmp = XEXP (SET_SRC (set), 1);
11108 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
11109 XEXP (SET_SRC (set), 2) = tmp;
11110 INSN_CODE (insn) = -1;
11111
11112 XEXP (label_ref, 0) = new_label;
11113 JUMP_LABEL (insn) = new_label;
11114 JUMP_LABEL (uncond_jump) = code_label;
11115
11116 return true;
11117}
11118
d277db6b
WG		 11119/* Returns 1 if INSN reads the value of REG for purposes not related
11120 to addressing of memory, and 0 otherwise. */
11121static int
775c43d3 11122s390_non_addr_reg_read_p (rtx reg, rtx_insn *insn)
d277db6b
WG		 11123{
11124 return reg_referenced_p (reg, PATTERN (insn))
11125 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
11126}
11127
e3cba5e5
AK		 11128/* Starting from INSN find_cond_jump looks downwards in the insn
11129 stream for a single jump insn which is the last user of the
11130 condition code set in INSN. */
775c43d3
DM		 11131static rtx_insn *
11132find_cond_jump (rtx_insn *insn)
e3cba5e5
AK		 11133{
11134 for (; insn; insn = NEXT_INSN (insn))
11135 {
11136 rtx ite, cc;
11137
11138 if (LABEL_P (insn))
11139 break;
11140
11141 if (!JUMP_P (insn))
11142 {
11143 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
11144 break;
11145 continue;
11146 }
11147
11148 /* This will be triggered by a return. */
11149 if (GET_CODE (PATTERN (insn)) != SET)
11150 break;
11151
11152 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
11153 ite = SET_SRC (PATTERN (insn));
11154
11155 if (GET_CODE (ite) != IF_THEN_ELSE)
11156 break;
11157
11158 cc = XEXP (XEXP (ite, 0), 0);
11159 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
11160 break;
11161
11162 if (find_reg_note (insn, REG_DEAD, cc))
11163 return insn;
11164 break;
11165 }
11166
775c43d3 11167 return NULL;
e3cba5e5
AK		 11168}
11169
11170/* Swap the condition in COND and the operands in OP0 and OP1 so that
11171 the semantics does not change. If NULL_RTX is passed as COND the
11172 function tries to find the conditional jump starting with INSN. */
11173static void
775c43d3 11174s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx_insn *insn)
e3cba5e5
AK		 11175{
11176 rtx tmp = *op0;
11177
11178 if (cond == NULL_RTX)
11179 {
e8a54173
DM		 11180 rtx_insn *jump = find_cond_jump (NEXT_INSN (insn));
11181 rtx set = jump ? single_set (jump) : NULL_RTX;
e3cba5e5 11182
e8a54173 11183 if (set == NULL_RTX)
e3cba5e5
AK		 11184 return;
11185
e8a54173 11186 cond = XEXP (SET_SRC (set), 0);
e3cba5e5
AK		 11187 }
11188
11189 *op0 = *op1;
11190 *op1 = tmp;
11191 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
11192}
d277db6b
WG		 11193
11194/* On z10, instructions of the compare-and-branch family have the
11195 property to access the register occurring as second operand with
11196 its bits complemented. If such a compare is grouped with a second
11197 instruction that accesses the same register non-complemented, and
11198 if that register's value is delivered via a bypass, then the
11199 pipeline recycles, thereby causing significant performance decline.
11200 This function locates such situations and exchanges the two
b0f86a7e
AK		 11201 operands of the compare. The function return true whenever it
11202 added an insn. */
11203static bool
775c43d3 11204s390_z10_optimize_cmp (rtx_insn *insn)
d277db6b 11205{
775c43d3 11206 rtx_insn *prev_insn, *next_insn;
b0f86a7e
AK		 11207 bool insn_added_p = false;
11208 rtx cond, *op0, *op1;
d277db6b 11209
b0f86a7e 11210 if (GET_CODE (PATTERN (insn)) == PARALLEL)
d277db6b 11211 {
b0f86a7e
AK		 11212 /* Handle compare and branch and branch on count
11213 instructions. */
11214 rtx pattern = single_set (insn);
e3cba5e5 11215
b0f86a7e
AK		 11216 if (!pattern
11217 || SET_DEST (pattern) != pc_rtx
11218 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
11219 return false;
d277db6b 11220
b0f86a7e
AK		 11221 cond = XEXP (SET_SRC (pattern), 0);
11222 op0 = &XEXP (cond, 0);
11223 op1 = &XEXP (cond, 1);
11224 }
11225 else if (GET_CODE (PATTERN (insn)) == SET)
11226 {
11227 rtx src, dest;
d277db6b 11228
b0f86a7e
AK		 11229 /* Handle normal compare instructions. */
11230 src = SET_SRC (PATTERN (insn));
11231 dest = SET_DEST (PATTERN (insn));
e3cba5e5 11232
b0f86a7e
AK		 11233 if (!REG_P (dest)
11234 || !CC_REGNO_P (REGNO (dest))
11235 || GET_CODE (src) != COMPARE)
11236 return false;
e3cba5e5 11237
b0f86a7e
AK		 11238 /* s390_swap_cmp will try to find the conditional
11239 jump when passing NULL_RTX as condition. */
11240 cond = NULL_RTX;
11241 op0 = &XEXP (src, 0);
11242 op1 = &XEXP (src, 1);
11243 }
11244 else
11245 return false;
e3cba5e5 11246
b0f86a7e
AK		 11247 if (!REG_P (*op0) || !REG_P (*op1))
11248 return false;
e3cba5e5 11249
2dfdbf2b
AK		 11250 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
11251 return false;
11252
b0f86a7e
AK		 11253 /* Swap the COMPARE arguments and its mask if there is a
11254 conflicting access in the previous insn. */
33ab2bd4 11255 prev_insn = prev_active_insn (insn);
b0f86a7e
AK		 11256 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
11257 && reg_referenced_p (*op1, PATTERN (prev_insn)))
11258 s390_swap_cmp (cond, op0, op1, insn);
11259
11260 /* Check if there is a conflict with the next insn. If there
11261 was no conflict with the previous insn, then swap the
11262 COMPARE arguments and its mask. If we already swapped
11263 the operands, or if swapping them would cause a conflict
11264 with the previous insn, issue a NOP after the COMPARE in
11265 order to separate the two instuctions. */
33ab2bd4 11266 next_insn = next_active_insn (insn);
b0f86a7e
AK		 11267 if (next_insn != NULL_RTX && INSN_P (next_insn)
11268 && s390_non_addr_reg_read_p (*op1, next_insn))
11269 {
e3cba5e5 11270 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
b0f86a7e 11271 && s390_non_addr_reg_read_p (*op0, prev_insn))
e3cba5e5 11272 {
b0f86a7e
AK		 11273 if (REGNO (*op1) == 0)
11274 emit_insn_after (gen_nop1 (), insn);
e3cba5e5 11275 else
b0f86a7e
AK		 11276 emit_insn_after (gen_nop (), insn);
11277 insn_added_p = true;
d277db6b 11278 }
b0f86a7e
AK		 11279 else
11280 s390_swap_cmp (cond, op0, op1, insn);
d277db6b 11281 }
b0f86a7e 11282 return insn_added_p;
d277db6b
WG		 11283}
11284
ab96de7e 11285/* Perform machine-dependent processing. */
ed9676cf 11286
ab96de7e
AS		 11287static void
11288s390_reorg (void)
ed9676cf 11289{
ab96de7e 11290 bool pool_overflow = false;
ed9676cf 11291
ab96de7e
AS		 11292 /* Make sure all splits have been performed; splits after
11293 machine_dependent_reorg might confuse insn length counts. */
11294 split_all_insns_noflow ();
38899e29 11295
ab96de7e
AS		 11296 /* Install the main literal pool and the associated base
11297 register load insns.
38899e29 11298
ab96de7e
AS		 11299 In addition, there are two problematic situations we need
11300 to correct:
ed9676cf 11301
ab96de7e
AS		 11302 - the literal pool might be > 4096 bytes in size, so that
11303 some of its elements cannot be directly accessed
ed9676cf 11304
ab96de7e
AS		 11305 - a branch target might be > 64K away from the branch, so that
11306 it is not possible to use a PC-relative instruction.
ed9676cf 11307
ab96de7e
AS		 11308 To fix those, we split the single literal pool into multiple
11309 pool chunks, reloading the pool base register at various
11310 points throughout the function to ensure it always points to
11311 the pool chunk the following code expects, and / or replace
11312 PC-relative branches by absolute branches.
ed9676cf 11313
ab96de7e
AS		 11314 However, the two problems are interdependent: splitting the
11315 literal pool can move a branch further away from its target,
11316 causing the 64K limit to overflow, and on the other hand,
11317 replacing a PC-relative branch by an absolute branch means
11318 we need to put the branch target address into the literal
11319 pool, possibly causing it to overflow.
ffdda752 11320
ab96de7e
AS		 11321 So, we loop trying to fix up both problems until we manage
11322 to satisfy both conditions at the same time. Note that the
11323 loop is guaranteed to terminate as every pass of the loop
11324 strictly decreases the total number of PC-relative branches
11325 in the function. (This is not completely true as there
11326 might be branch-over-pool insns introduced by chunkify_start.
11327 Those never need to be split however.) */
ffdda752 11328
ab96de7e
AS		 11329 for (;;)
11330 {
11331 struct constant_pool *pool = NULL;
a628ab6d 11332
ab96de7e
AS		 11333 /* Collect the literal pool. */
11334 if (!pool_overflow)
11335 {
11336 pool = s390_mainpool_start ();
11337 if (!pool)
11338 pool_overflow = true;
11339 }
a628ab6d 11340
ab96de7e
AS		 11341 /* If literal pool overflowed, start to chunkify it. */
11342 if (pool_overflow)
11343 pool = s390_chunkify_start ();
a628ab6d 11344
ab96de7e
AS		 11345 /* Split out-of-range branches. If this has created new
11346 literal pool entries, cancel current chunk list and
11347 recompute it. zSeries machines have large branch
11348 instructions, so we never need to split a branch. */
11349 if (!TARGET_CPU_ZARCH && s390_split_branches ())
11350 {
11351 if (pool_overflow)
11352 s390_chunkify_cancel (pool);
11353 else
11354 s390_mainpool_cancel (pool);
a628ab6d 11355
ab96de7e
AS		 11356 continue;
11357 }
11358
11359 /* If we made it up to here, both conditions are satisfied.
11360 Finish up literal pool related changes. */
11361 if (pool_overflow)
11362 s390_chunkify_finish (pool);
11363 else
11364 s390_mainpool_finish (pool);
11365
11366 /* We're done splitting branches. */
11367 cfun->machine->split_branches_pending_p = false;
11368 break;
a628ab6d 11369 }
a628ab6d 11370
d24959df
UW		 11371 /* Generate out-of-pool execute target insns. */
11372 if (TARGET_CPU_ZARCH)
11373 {
775c43d3
DM		 11374 rtx_insn *insn, *target;
11375 rtx label;
d24959df
UW		 11376
11377 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11378 {
11379 label = s390_execute_label (insn);
11380 if (!label)
11381 continue;
11382
11383 gcc_assert (label != const0_rtx);
11384
11385 target = emit_label (XEXP (label, 0));
11386 INSN_ADDRESSES_NEW (target, -1);
11387
11388 target = emit_insn (s390_execute_target (insn));
11389 INSN_ADDRESSES_NEW (target, -1);
11390 }
11391 }
11392
11393 /* Try to optimize prologue and epilogue further. */
ab96de7e 11394 s390_optimize_prologue ();
d277db6b 11395
65b1d8ea
AK		 11396 /* Walk over the insns and do some >=z10 specific changes. */
11397 if (s390_tune == PROCESSOR_2097_Z10
22ac2c2f
AK		 11398 || s390_tune == PROCESSOR_2817_Z196
11399 || s390_tune == PROCESSOR_2827_ZEC12)
b0f86a7e 11400 {
775c43d3 11401 rtx_insn *insn;
b0f86a7e
AK		 11402 bool insn_added_p = false;
11403
11404 /* The insn lengths and addresses have to be up to date for the
11405 following manipulations. */
11406 shorten_branches (get_insns ());
11407
11408 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11409 {
11410 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
11411 continue;
11412
11413 if (JUMP_P (insn))
65b1d8ea 11414 insn_added_p |= s390_fix_long_loop_prediction (insn);
b0f86a7e 11415
65b1d8ea
AK		 11416 if ((GET_CODE (PATTERN (insn)) == PARALLEL
11417 || GET_CODE (PATTERN (insn)) == SET)
11418 && s390_tune == PROCESSOR_2097_Z10)
b0f86a7e
AK		 11419 insn_added_p |= s390_z10_optimize_cmp (insn);
11420 }
11421
11422 /* Adjust branches if we added new instructions. */
11423 if (insn_added_p)
11424 shorten_branches (get_insns ());
11425 }
ab96de7e 11426}
ed9676cf 11427
3a892e44
AK		 11428/* Return true if INSN is a fp load insn writing register REGNO. */
11429static inline bool
647d790d 11430s390_fpload_toreg (rtx_insn *insn, unsigned int regno)
3a892e44
AK		 11431{
11432 rtx set;
11433 enum attr_type flag = s390_safe_attr_type (insn);
11434
11435 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
11436 return false;
11437
11438 set = single_set (insn);
11439
11440 if (set == NULL_RTX)
11441 return false;
11442
11443 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
11444 return false;
11445
11446 if (REGNO (SET_DEST (set)) != regno)
11447 return false;
11448
11449 return true;
11450}
11451
11452/* This value describes the distance to be avoided between an
11453 aritmetic fp instruction and an fp load writing the same register.
11454 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
11455 fine but the exact value has to be avoided. Otherwise the FP
11456 pipeline will throw an exception causing a major penalty. */
11457#define Z10_EARLYLOAD_DISTANCE 7
11458
11459/* Rearrange the ready list in order to avoid the situation described
11460 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
11461 moved to the very end of the ready list. */
11462static void
ce1ce33a 11463s390_z10_prevent_earlyload_conflicts (rtx_insn **ready, int *nready_p)
3a892e44
AK		 11464{
11465 unsigned int regno;
11466 int nready = *nready_p;
ce1ce33a 11467 rtx_insn *tmp;
3a892e44 11468 int i;
775c43d3 11469 rtx_insn *insn;
3a892e44
AK		 11470 rtx set;
11471 enum attr_type flag;
11472 int distance;
11473
11474 /* Skip DISTANCE - 1 active insns. */
11475 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
11476 distance > 0 && insn != NULL_RTX;
11477 distance--, insn = prev_active_insn (insn))
11478 if (CALL_P (insn) || JUMP_P (insn))
11479 return;
11480
11481 if (insn == NULL_RTX)
11482 return;
11483
11484 set = single_set (insn);
11485
11486 if (set == NULL_RTX || !REG_P (SET_DEST (set))
11487 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
11488 return;
11489
11490 flag = s390_safe_attr_type (insn);
11491
11492 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
11493 return;
11494
11495 regno = REGNO (SET_DEST (set));
11496 i = nready - 1;
11497
11498 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
11499 i--;
11500
11501 if (!i)
11502 return;
11503
11504 tmp = ready[i];
ce1ce33a 11505 memmove (&ready[1], &ready[0], sizeof (rtx_insn *) * i);
3a892e44
AK		 11506 ready[0] = tmp;
11507}
11508
22ac2c2f
AK		 11509
11510/* The s390_sched_state variable tracks the state of the current or
11511 the last instruction group.
11512
11513 0,1,2 number of instructions scheduled in the current group
11514 3 the last group is complete - normal insns
11515 4 the last group was a cracked/expanded insn */
11516
11517static int s390_sched_state;
11518
11519#define S390_OOO_SCHED_STATE_NORMAL 3
11520#define S390_OOO_SCHED_STATE_CRACKED 4
11521
11522#define S390_OOO_SCHED_ATTR_MASK_CRACKED 0x1
11523#define S390_OOO_SCHED_ATTR_MASK_EXPANDED 0x2
11524#define S390_OOO_SCHED_ATTR_MASK_ENDGROUP 0x4
11525#define S390_OOO_SCHED_ATTR_MASK_GROUPALONE 0x8
11526
11527static unsigned int
84034c69 11528s390_get_sched_attrmask (rtx_insn *insn)
22ac2c2f
AK		 11529{
11530 unsigned int mask = 0;
11531
11532 if (get_attr_ooo_cracked (insn))
11533 mask |= S390_OOO_SCHED_ATTR_MASK_CRACKED;
11534 if (get_attr_ooo_expanded (insn))
11535 mask |= S390_OOO_SCHED_ATTR_MASK_EXPANDED;
11536 if (get_attr_ooo_endgroup (insn))
11537 mask |= S390_OOO_SCHED_ATTR_MASK_ENDGROUP;
11538 if (get_attr_ooo_groupalone (insn))
11539 mask |= S390_OOO_SCHED_ATTR_MASK_GROUPALONE;
11540 return mask;
11541}
11542
11543/* Return the scheduling score for INSN. The higher the score the
11544 better. The score is calculated from the OOO scheduling attributes
11545 of INSN and the scheduling state s390_sched_state. */
11546static int
84034c69 11547s390_sched_score (rtx_insn *insn)
22ac2c2f
AK		 11548{
11549 unsigned int mask = s390_get_sched_attrmask (insn);
11550 int score = 0;
11551
11552 switch (s390_sched_state)
11553 {
11554 case 0:
11555 /* Try to put insns into the first slot which would otherwise
11556 break a group. */
11557 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11558 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11559 score += 5;
11560 if ((mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11561 score += 10;
11562 case 1:
11563 /* Prefer not cracked insns while trying to put together a
11564 group. */
11565 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11566 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0
11567 && (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) == 0)
11568 score += 10;
11569 if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) == 0)
11570 score += 5;
11571 break;
11572 case 2:
11573 /* Prefer not cracked insns while trying to put together a
11574 group. */
11575 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11576 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0
11577 && (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) == 0)
11578 score += 10;
11579 /* Prefer endgroup insns in the last slot. */
11580 if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) != 0)
11581 score += 10;
11582 break;
11583 case S390_OOO_SCHED_STATE_NORMAL:
11584 /* Prefer not cracked insns if the last was not cracked. */
11585 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11586 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0)
11587 score += 5;
11588 if ((mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11589 score += 10;
11590 break;
11591 case S390_OOO_SCHED_STATE_CRACKED:
11592 /* Try to keep cracked insns together to prevent them from
11593 interrupting groups. */
11594 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11595 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11596 score += 5;
11597 break;
11598 }
11599 return score;
11600}
11601
3a892e44 11602/* This function is called via hook TARGET_SCHED_REORDER before
631b20a7 11603 issuing one insn from list READY which contains *NREADYP entries.
3a892e44
AK		 11604 For target z10 it reorders load instructions to avoid early load
11605 conflicts in the floating point pipeline */
11606static int
22ac2c2f 11607s390_sched_reorder (FILE *file, int verbose,
ce1ce33a 11608 rtx_insn **ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
3a892e44
AK		 11609{
11610 if (s390_tune == PROCESSOR_2097_Z10)
11611 if (reload_completed && *nreadyp > 1)
11612 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
11613
22ac2c2f
AK		 11614 if (s390_tune == PROCESSOR_2827_ZEC12
11615 && reload_completed
11616 && *nreadyp > 1)
11617 {
11618 int i;
11619 int last_index = *nreadyp - 1;
11620 int max_index = -1;
11621 int max_score = -1;
ce1ce33a 11622 rtx_insn *tmp;
22ac2c2f
AK		 11623
11624 /* Just move the insn with the highest score to the top (the
11625 end) of the list. A full sort is not needed since a conflict
11626 in the hazard recognition cannot happen. So the top insn in
11627 the ready list will always be taken. */
11628 for (i = last_index; i >= 0; i--)
11629 {
11630 int score;
11631
11632 if (recog_memoized (ready[i]) < 0)
11633 continue;
11634
11635 score = s390_sched_score (ready[i]);
11636 if (score > max_score)
11637 {
11638 max_score = score;
11639 max_index = i;
11640 }
11641 }
11642
11643 if (max_index != -1)
11644 {
11645 if (max_index != last_index)
11646 {
11647 tmp = ready[max_index];
11648 ready[max_index] = ready[last_index];
11649 ready[last_index] = tmp;
11650
11651 if (verbose > 5)
11652 fprintf (file,
11653 "move insn %d to the top of list\n",
11654 INSN_UID (ready[last_index]));
11655 }
11656 else if (verbose > 5)
11657 fprintf (file,
11658 "best insn %d already on top\n",
11659 INSN_UID (ready[last_index]));
11660 }
11661
11662 if (verbose > 5)
11663 {
11664 fprintf (file, "ready list ooo attributes - sched state: %d\n",
11665 s390_sched_state);
11666
11667 for (i = last_index; i >= 0; i--)
11668 {
11669 if (recog_memoized (ready[i]) < 0)
11670 continue;
11671 fprintf (file, "insn %d score: %d: ", INSN_UID (ready[i]),
11672 s390_sched_score (ready[i]));
11673#define PRINT_OOO_ATTR(ATTR) fprintf (file, "%s ", get_attr_##ATTR (ready[i]) ? #ATTR : "!" #ATTR);
11674 PRINT_OOO_ATTR (ooo_cracked);
11675 PRINT_OOO_ATTR (ooo_expanded);
11676 PRINT_OOO_ATTR (ooo_endgroup);
11677 PRINT_OOO_ATTR (ooo_groupalone);
11678#undef PRINT_OOO_ATTR
11679 fprintf (file, "\n");
11680 }
11681 }
11682 }
11683
3a892e44
AK		 11684 return s390_issue_rate ();
11685}
11686
22ac2c2f 11687
3a892e44
AK		 11688/* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
11689 the scheduler has issued INSN. It stores the last issued insn into
11690 last_scheduled_insn in order to make it available for
11691 s390_sched_reorder. */
11692static int
ac44248e 11693s390_sched_variable_issue (FILE *file, int verbose, rtx_insn *insn, int more)
3a892e44
AK		 11694{
11695 last_scheduled_insn = insn;
11696
22ac2c2f
AK		 11697 if (s390_tune == PROCESSOR_2827_ZEC12
11698 && reload_completed
11699 && recog_memoized (insn) >= 0)
11700 {
11701 unsigned int mask = s390_get_sched_attrmask (insn);
11702
11703 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11704 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11705 s390_sched_state = S390_OOO_SCHED_STATE_CRACKED;
11706 else if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) != 0
11707 || (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11708 s390_sched_state = S390_OOO_SCHED_STATE_NORMAL;
11709 else
11710 {
11711 /* Only normal insns are left (mask == 0). */
11712 switch (s390_sched_state)
11713 {
11714 case 0:
11715 case 1:
11716 case 2:
11717 case S390_OOO_SCHED_STATE_NORMAL:
11718 if (s390_sched_state == S390_OOO_SCHED_STATE_NORMAL)
11719 s390_sched_state = 1;
11720 else
11721 s390_sched_state++;
11722
11723 break;
11724 case S390_OOO_SCHED_STATE_CRACKED:
11725 s390_sched_state = S390_OOO_SCHED_STATE_NORMAL;
11726 break;
11727 }
11728 }
11729 if (verbose > 5)
11730 {
11731 fprintf (file, "insn %d: ", INSN_UID (insn));
11732#define PRINT_OOO_ATTR(ATTR) \
11733 fprintf (file, "%s ", get_attr_##ATTR (insn) ? #ATTR : "");
11734 PRINT_OOO_ATTR (ooo_cracked);
11735 PRINT_OOO_ATTR (ooo_expanded);
11736 PRINT_OOO_ATTR (ooo_endgroup);
11737 PRINT_OOO_ATTR (ooo_groupalone);
11738#undef PRINT_OOO_ATTR
11739 fprintf (file, "\n");
11740 fprintf (file, "sched state: %d\n", s390_sched_state);
11741 }
11742 }
11743
3a892e44
AK		 11744 if (GET_CODE (PATTERN (insn)) != USE
11745 && GET_CODE (PATTERN (insn)) != CLOBBER)
11746 return more - 1;
11747 else
11748 return more;
11749}
ed9676cf 11750
244e6c5c
AK		 11751static void
11752s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
11753 int verbose ATTRIBUTE_UNUSED,
11754 int max_ready ATTRIBUTE_UNUSED)
11755{
775c43d3 11756 last_scheduled_insn = NULL;
22ac2c2f 11757 s390_sched_state = 0;
244e6c5c
AK		 11758}
11759
40ac4f73 11760/* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
65b1d8ea
AK		 11761 a new number struct loop *loop should be unrolled if tuned for cpus with
11762 a built-in stride prefetcher.
11763 The loop is analyzed for memory accesses by calling check_dpu for
40ac4f73
CB		 11764 each rtx of the loop. Depending on the loop_depth and the amount of
11765 memory accesses a new number <=nunroll is returned to improve the
11766 behaviour of the hardware prefetch unit. */
11767static unsigned
11768s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
11769{
11770 basic_block *bbs;
775c43d3 11771 rtx_insn *insn;
40ac4f73
CB		 11772 unsigned i;
11773 unsigned mem_count = 0;
11774
22ac2c2f
AK		 11775 if (s390_tune != PROCESSOR_2097_Z10
11776 && s390_tune != PROCESSOR_2817_Z196
11777 && s390_tune != PROCESSOR_2827_ZEC12)
40ac4f73
CB		 11778 return nunroll;
11779
11780 /* Count the number of memory references within the loop body. */
11781 bbs = get_loop_body (loop);
9dc7a9da 11782 subrtx_iterator::array_type array;
40ac4f73 11783 for (i = 0; i < loop->num_nodes; i++)
9dc7a9da
RS		 11784 FOR_BB_INSNS (bbs[i], insn)
11785 if (INSN_P (insn) && INSN_CODE (insn) != -1)
11786 FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST)
11787 if (MEM_P (*iter))
11788 mem_count += 1;
40ac4f73
CB		 11789 free (bbs);
11790
11791 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
11792 if (mem_count == 0)
11793 return nunroll;
11794
11795 switch (loop_depth(loop))
11796 {
11797 case 1:
11798 return MIN (nunroll, 28 / mem_count);
11799 case 2:
11800 return MIN (nunroll, 22 / mem_count);
11801 default:
11802 return MIN (nunroll, 16 / mem_count);
11803 }
11804}
11805
4099494d
RS		 11806static void
11807s390_option_override (void)
11808{
11809 unsigned int i;
11810 cl_deferred_option *opt;
11811 vec<cl_deferred_option> *v =
11812 (vec<cl_deferred_option> *) s390_deferred_options;
11813
11814 if (v)
11815 FOR_EACH_VEC_ELT (*v, i, opt)
11816 {
11817 switch (opt->opt_index)
11818 {
11819 case OPT_mhotpatch:
11820 s390_hotpatch_trampoline_halfwords = (opt->value) ?
11821 s390_hotpatch_trampoline_halfwords_default : -1;
11822 break;
11823 case OPT_mhotpatch_:
11824 {
11825 int val;
11826
11827 val = integral_argument (opt->arg);
11828 if (val == -1)
11829 {
11830 /* argument is not a plain number */
11831 error ("argument to %qs should be a non-negative integer",
11832 "-mhotpatch=");
11833 break;
11834 }
11835 else if (val > s390_hotpatch_trampoline_halfwords_max)
11836 {
11837 error ("argument to %qs is too large (max. %d)",
11838 "-mhotpatch=", s390_hotpatch_trampoline_halfwords_max);
11839 break;
11840 }
11841 s390_hotpatch_trampoline_halfwords = val;
11842 break;
11843 }
11844 default:
11845 gcc_unreachable ();
11846 }
11847 }
11848
11849 /* Set up function hooks. */
11850 init_machine_status = s390_init_machine_status;
11851
11852 /* Architecture mode defaults according to ABI. */
11853 if (!(target_flags_explicit & MASK_ZARCH))
11854 {
11855 if (TARGET_64BIT)
11856 target_flags |= MASK_ZARCH;
11857 else
11858 target_flags &= ~MASK_ZARCH;
11859 }
11860
11861 /* Set the march default in case it hasn't been specified on
11862 cmdline. */
11863 if (s390_arch == PROCESSOR_max)
11864 {
11865 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
11866 s390_arch = TARGET_ZARCH ? PROCESSOR_2064_Z900 : PROCESSOR_9672_G5;
11867 s390_arch_flags = processor_flags_table[(int)s390_arch];
11868 }
11869
11870 /* Determine processor to tune for. */
11871 if (s390_tune == PROCESSOR_max)
11872 {
11873 s390_tune = s390_arch;
11874 s390_tune_flags = s390_arch_flags;
11875 }
11876
11877 /* Sanity checks. */
11878 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
11879 error ("z/Architecture mode not supported on %s", s390_arch_string);
11880 if (TARGET_64BIT && !TARGET_ZARCH)
11881 error ("64-bit ABI not supported in ESA/390 mode");
11882
11883 /* Use hardware DFP if available and not explicitly disabled by
11884 user. E.g. with -m31 -march=z10 -mzarch */
11885 if (!(target_flags_explicit & MASK_HARD_DFP) && TARGET_DFP)
11886 target_flags |= MASK_HARD_DFP;
11887
11888 /* Enable hardware transactions if available and not explicitly
11889 disabled by user. E.g. with -m31 -march=zEC12 -mzarch */
11890 if (!(target_flags_explicit & MASK_OPT_HTM) && TARGET_CPU_HTM && TARGET_ZARCH)
11891 target_flags |= MASK_OPT_HTM;
11892
11893 if (TARGET_HARD_DFP && !TARGET_DFP)
11894 {
11895 if (target_flags_explicit & MASK_HARD_DFP)
11896 {
11897 if (!TARGET_CPU_DFP)
11898 error ("hardware decimal floating point instructions"
11899 " not available on %s", s390_arch_string);
11900 if (!TARGET_ZARCH)
11901 error ("hardware decimal floating point instructions"
11902 " not available in ESA/390 mode");
11903 }
11904 else
11905 target_flags &= ~MASK_HARD_DFP;
11906 }
11907
11908 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
11909 {
11910 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
11911 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
11912
11913 target_flags &= ~MASK_HARD_DFP;
11914 }
11915
11916 /* Set processor cost function. */
11917 switch (s390_tune)
11918 {
11919 case PROCESSOR_2084_Z990:
11920 s390_cost = &z990_cost;
11921 break;
11922 case PROCESSOR_2094_Z9_109:
11923 s390_cost = &z9_109_cost;
11924 break;
11925 case PROCESSOR_2097_Z10:
11926 s390_cost = &z10_cost;
11927 break;
11928 case PROCESSOR_2817_Z196:
11929 s390_cost = &z196_cost;
11930 break;
11931 case PROCESSOR_2827_ZEC12:
11932 s390_cost = &zEC12_cost;
11933 break;
11934 default:
11935 s390_cost = &z900_cost;
11936 }
11937
11938 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
11939 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
11940 "in combination");
11941
11942 if (s390_stack_size)
11943 {
11944 if (s390_stack_guard >= s390_stack_size)
11945 error ("stack size must be greater than the stack guard value");
11946 else if (s390_stack_size > 1 << 16)
11947 error ("stack size must not be greater than 64k");
11948 }
11949 else if (s390_stack_guard)
11950 error ("-mstack-guard implies use of -mstack-size");
11951
11952#ifdef TARGET_DEFAULT_LONG_DOUBLE_128
11953 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
11954 target_flags |= MASK_LONG_DOUBLE_128;
11955#endif
11956
11957 if (s390_tune == PROCESSOR_2097_Z10
11958 || s390_tune == PROCESSOR_2817_Z196
11959 || s390_tune == PROCESSOR_2827_ZEC12)
11960 {
11961 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100,
11962 global_options.x_param_values,
11963 global_options_set.x_param_values);
11964 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32,
11965 global_options.x_param_values,
11966 global_options_set.x_param_values);
11967 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000,
11968 global_options.x_param_values,
11969 global_options_set.x_param_values);
11970 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64,
11971 global_options.x_param_values,
11972 global_options_set.x_param_values);
11973 }
11974
11975 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256,
11976 global_options.x_param_values,
11977 global_options_set.x_param_values);
11978 /* values for loop prefetching */
11979 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256,
11980 global_options.x_param_values,
11981 global_options_set.x_param_values);
11982 maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128,
11983 global_options.x_param_values,
11984 global_options_set.x_param_values);
11985 /* s390 has more than 2 levels and the size is much larger. Since
11986 we are always running virtualized assume that we only get a small
11987 part of the caches above l1. */
11988 maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500,
11989 global_options.x_param_values,
11990 global_options_set.x_param_values);
11991 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2,
11992 global_options.x_param_values,
11993 global_options_set.x_param_values);
11994 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6,
11995 global_options.x_param_values,
11996 global_options_set.x_param_values);
11997
11998 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
11999 requires the arch flags to be evaluated already. Since prefetching
12000 is beneficial on s390, we enable it if available. */
12001 if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
12002 flag_prefetch_loop_arrays = 1;
12003
12004 /* Use the alternative scheduling-pressure algorithm by default. */
12005 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, 2,
12006 global_options.x_param_values,
12007 global_options_set.x_param_values);
12008
12009 if (TARGET_TPF)
12010 {
12011 /* Don't emit DWARF3/4 unless specifically selected. The TPF
12012 debuggers do not yet support DWARF 3/4. */
12013 if (!global_options_set.x_dwarf_strict)
12014 dwarf_strict = 1;
12015 if (!global_options_set.x_dwarf_version)
12016 dwarf_version = 2;
12017 }
12018
12019 /* Register a target-specific optimization-and-lowering pass
12020 to run immediately before prologue and epilogue generation.
12021
12022 Registering the pass must be done at start up. It's
12023 convenient to do it here. */
12024 opt_pass *new_pass = new pass_s390_early_mach (g);
12025 struct register_pass_info insert_pass_s390_early_mach =
12026 {
12027 new_pass, /* pass */
12028 "pro_and_epilogue", /* reference_pass_name */
12029 1, /* ref_pass_instance_number */
12030 PASS_POS_INSERT_BEFORE /* po_op */
12031 };
12032 register_pass (&insert_pass_s390_early_mach);
12033}
12034
ab96de7e 12035/* Initialize GCC target structure. */
38899e29 12036
ab96de7e
AS		 12037#undef TARGET_ASM_ALIGNED_HI_OP
12038#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
12039#undef TARGET_ASM_ALIGNED_DI_OP
12040#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
12041#undef TARGET_ASM_INTEGER
12042#define TARGET_ASM_INTEGER s390_assemble_integer
ed9676cf 12043
ab96de7e
AS		 12044#undef TARGET_ASM_OPEN_PAREN
12045#define TARGET_ASM_OPEN_PAREN ""
38899e29 12046
ab96de7e
AS		 12047#undef TARGET_ASM_CLOSE_PAREN
12048#define TARGET_ASM_CLOSE_PAREN ""
ed9676cf 12049
c5387660
JM		 12050#undef TARGET_OPTION_OVERRIDE
12051#define TARGET_OPTION_OVERRIDE s390_option_override
12052
ab96de7e
AS		 12053#undef TARGET_ENCODE_SECTION_INFO
12054#define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
ed9676cf 12055
9602b6a1
AK		 12056#undef TARGET_SCALAR_MODE_SUPPORTED_P
12057#define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
12058
ab96de7e
AS		 12059#ifdef HAVE_AS_TLS
12060#undef TARGET_HAVE_TLS
12061#define TARGET_HAVE_TLS true
12062#endif
12063#undef TARGET_CANNOT_FORCE_CONST_MEM
12064#define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
ed9676cf 12065
ab96de7e
AS		 12066#undef TARGET_DELEGITIMIZE_ADDRESS
12067#define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
ed9676cf 12068
506d7b68
PB		 12069#undef TARGET_LEGITIMIZE_ADDRESS
12070#define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
12071
ab96de7e
AS		 12072#undef TARGET_RETURN_IN_MEMORY
12073#define TARGET_RETURN_IN_MEMORY s390_return_in_memory
38899e29 12074
5a3fe9b6
AK		 12075#undef TARGET_INIT_BUILTINS
12076#define TARGET_INIT_BUILTINS s390_init_builtins
12077#undef TARGET_EXPAND_BUILTIN
12078#define TARGET_EXPAND_BUILTIN s390_expand_builtin
12079
0f8ab434
AS		 12080#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
12081#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
12082
ab96de7e
AS		 12083#undef TARGET_ASM_OUTPUT_MI_THUNK
12084#define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
12085#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
3101faab 12086#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
ed9676cf 12087
ab96de7e
AS		 12088#undef TARGET_SCHED_ADJUST_PRIORITY
12089#define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
12090#undef TARGET_SCHED_ISSUE_RATE
12091#define TARGET_SCHED_ISSUE_RATE s390_issue_rate
12092#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
12093#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
38899e29 12094
3a892e44
AK		 12095#undef TARGET_SCHED_VARIABLE_ISSUE
12096#define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
12097#undef TARGET_SCHED_REORDER
12098#define TARGET_SCHED_REORDER s390_sched_reorder
244e6c5c
AK		 12099#undef TARGET_SCHED_INIT
12100#define TARGET_SCHED_INIT s390_sched_init
3a892e44 12101
ab96de7e
AS		 12102#undef TARGET_CANNOT_COPY_INSN_P
12103#define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
12104#undef TARGET_RTX_COSTS
12105#define TARGET_RTX_COSTS s390_rtx_costs
12106#undef TARGET_ADDRESS_COST
12107#define TARGET_ADDRESS_COST s390_address_cost
ccaed3ba
AS		 12108#undef TARGET_REGISTER_MOVE_COST
12109#define TARGET_REGISTER_MOVE_COST s390_register_move_cost
12110#undef TARGET_MEMORY_MOVE_COST
12111#define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
38899e29 12112
ab96de7e
AS		 12113#undef TARGET_MACHINE_DEPENDENT_REORG
12114#define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
8a512b77 12115
ab96de7e
AS		 12116#undef TARGET_VALID_POINTER_MODE
12117#define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
38899e29 12118
ab96de7e
AS		 12119#undef TARGET_BUILD_BUILTIN_VA_LIST
12120#define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
d7bd8aeb
JJ		 12121#undef TARGET_EXPAND_BUILTIN_VA_START
12122#define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
ab96de7e
AS		 12123#undef TARGET_GIMPLIFY_VA_ARG_EXPR
12124#define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
4798630c 12125
cde0f3fd
PB		 12126#undef TARGET_PROMOTE_FUNCTION_MODE
12127#define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
ab96de7e
AS		 12128#undef TARGET_PASS_BY_REFERENCE
12129#define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
4798630c 12130
ab96de7e
AS		 12131#undef TARGET_FUNCTION_OK_FOR_SIBCALL
12132#define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
3cb1da52
NF		 12133#undef TARGET_FUNCTION_ARG
12134#define TARGET_FUNCTION_ARG s390_function_arg
12135#undef TARGET_FUNCTION_ARG_ADVANCE
12136#define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
b46616fd
AK		 12137#undef TARGET_FUNCTION_VALUE
12138#define TARGET_FUNCTION_VALUE s390_function_value
12139#undef TARGET_LIBCALL_VALUE
12140#define TARGET_LIBCALL_VALUE s390_libcall_value
4798630c 12141
d56a43a0
AK		 12142#undef TARGET_KEEP_LEAF_WHEN_PROFILED
12143#define TARGET_KEEP_LEAF_WHEN_PROFILED s390_keep_leaf_when_profiled
12144
ab96de7e
AS		 12145#undef TARGET_FIXED_CONDITION_CODE_REGS
12146#define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
4798630c 12147
ab96de7e
AS		 12148#undef TARGET_CC_MODES_COMPATIBLE
12149#define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
4798630c 12150
e7e64a25 12151#undef TARGET_INVALID_WITHIN_DOLOOP
ac44248e 12152#define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_insn_null
c08b81aa 12153
fdbe66f2
EB		 12154#ifdef HAVE_AS_TLS
12155#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
12156#define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
12157#endif
12158
7269aee7 12159#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
608063c3
JB		 12160#undef TARGET_MANGLE_TYPE
12161#define TARGET_MANGLE_TYPE s390_mangle_type
7269aee7
AH		 12162#endif
12163
4dc19cc0
AK		 12164#undef TARGET_SCALAR_MODE_SUPPORTED_P
12165#define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
12166
5df97412
AS		 12167#undef TARGET_PREFERRED_RELOAD_CLASS
12168#define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
12169
833cd70a
AK		 12170#undef TARGET_SECONDARY_RELOAD
12171#define TARGET_SECONDARY_RELOAD s390_secondary_reload
12172
c7ff6e7a
AK		 12173#undef TARGET_LIBGCC_CMP_RETURN_MODE
12174#define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
12175
12176#undef TARGET_LIBGCC_SHIFT_COUNT_MODE
12177#define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
12178
c6c3dba9
PB		 12179#undef TARGET_LEGITIMATE_ADDRESS_P
12180#define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
12181
1a627b35
RS		 12182#undef TARGET_LEGITIMATE_CONSTANT_P
12183#define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
12184
3597e113
VM		 12185#undef TARGET_LRA_P
12186#define TARGET_LRA_P s390_lra_p
12187
7b5cbb57
AS		 12188#undef TARGET_CAN_ELIMINATE
12189#define TARGET_CAN_ELIMINATE s390_can_eliminate
12190
5efd84c5
NF		 12191#undef TARGET_CONDITIONAL_REGISTER_USAGE
12192#define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
12193
40ac4f73
CB		 12194#undef TARGET_LOOP_UNROLL_ADJUST
12195#define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
12196
b81ecf6f
RH		 12197#undef TARGET_ASM_TRAMPOLINE_TEMPLATE
12198#define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
12199#undef TARGET_TRAMPOLINE_INIT
12200#define TARGET_TRAMPOLINE_INIT s390_trampoline_init
12201
9602b6a1
AK		 12202#undef TARGET_UNWIND_WORD_MODE
12203#define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
12204
c354951b
AK		 12205#undef TARGET_CANONICALIZE_COMPARISON
12206#define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison
12207
6455a49e
AK		 12208#undef TARGET_HARD_REGNO_SCRATCH_OK
12209#define TARGET_HARD_REGNO_SCRATCH_OK s390_hard_regno_scratch_ok
12210
d0de9e13
DV		 12211#undef TARGET_ATTRIBUTE_TABLE
12212#define TARGET_ATTRIBUTE_TABLE s390_attribute_table
12213
12214#undef TARGET_CAN_INLINE_P
12215#define TARGET_CAN_INLINE_P s390_can_inline_p
12216
177bc204
RS		 12217#undef TARGET_SET_UP_BY_PROLOGUE
12218#define TARGET_SET_UP_BY_PROLOGUE s300_set_up_by_prologue
12219
ab96de7e 12220struct gcc_target targetm = TARGET_INITIALIZER;
38899e29 12221
29742ba4 12222#include "gt-s390.h"
Mirror of https://gcc.gnu.org/git/gcc.git