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Eliminate FOR_EACH_BB macro.
[thirdparty/gcc.git] / gcc / config / s390 / s390.c
CommitLineData
4673c1a0 1/* Subroutines used for code generation on IBM S/390 and zSeries
711789cc 2 Copyright (C) 1999-2013 Free Software Foundation, Inc.
4673c1a0 3 Contributed by Hartmut Penner (hpenner@de.ibm.com) and
e68d6a13 4 Ulrich Weigand (uweigand@de.ibm.com) and
5 Andreas Krebbel (Andreas.Krebbel@de.ibm.com).
4673c1a0 6
1e98c8f3 7This file is part of GCC.
4673c1a0 8
1e98c8f3 9GCC is free software; you can redistribute it and/or modify it under
10the terms of the GNU General Public License as published by the Free
038d1e19 11Software Foundation; either version 3, or (at your option) any later
1e98c8f3 12version.
4673c1a0 13
1e98c8f3 14GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15WARRANTY; without even the implied warranty of MERCHANTABILITY or
16FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17for more details.
4673c1a0 18
19You should have received a copy of the GNU General Public License
038d1e19 20along with GCC; see the file COPYING3. If not see
21<http://www.gnu.org/licenses/>. */
4673c1a0 22
23#include "config.h"
4673c1a0 24#include "system.h"
805e22b2 25#include "coretypes.h"
26#include "tm.h"
4673c1a0 27#include "rtl.h"
28#include "tree.h"
9ed99284 29#include "print-tree.h"
30#include "stringpool.h"
31#include "stor-layout.h"
32#include "varasm.h"
33#include "calls.h"
4673c1a0 34#include "tm_p.h"
35#include "regs.h"
36#include "hard-reg-set.h"
4673c1a0 37#include "insn-config.h"
38#include "conditions.h"
39#include "output.h"
40#include "insn-attr.h"
41#include "flags.h"
42#include "except.h"
43#include "function.h"
44#include "recog.h"
45#include "expr.h"
c10847b9 46#include "reload.h"
0b205f4c 47#include "diagnostic-core.h"
4673c1a0 48#include "basic-block.h"
49#include "ggc.h"
50#include "target.h"
51#include "target-def.h"
7baa5366 52#include "debug.h"
a1f71e15 53#include "langhooks.h"
4fbc4db5 54#include "optabs.h"
bc61cadb 55#include "pointer-set.h"
56#include "hash-table.h"
57#include "vec.h"
58#include "basic-block.h"
59#include "tree-ssa-alias.h"
60#include "internal-fn.h"
61#include "gimple-fold.h"
62#include "tree-eh.h"
63#include "gimple-expr.h"
64#include "is-a.h"
e795d6e1 65#include "gimple.h"
a8783bee 66#include "gimplify.h"
3072d30e 67#include "df.h"
c0717306 68#include "params.h"
9ccaa774 69#include "cfgloop.h"
fba5dd52 70#include "opts.h"
4673c1a0 71
18925d38 72/* Define the specific costs for a given cpu. */
73
ffead1ca 74struct processor_costs
18925d38 75{
260075cc 76 /* multiplication */
18925d38 77 const int m; /* cost of an M instruction. */
78 const int mghi; /* cost of an MGHI instruction. */
79 const int mh; /* cost of an MH instruction. */
80 const int mhi; /* cost of an MHI instruction. */
9cd3f3e6 81 const int ml; /* cost of an ML instruction. */
18925d38 82 const int mr; /* cost of an MR instruction. */
83 const int ms; /* cost of an MS instruction. */
84 const int msg; /* cost of an MSG instruction. */
85 const int msgf; /* cost of an MSGF instruction. */
86 const int msgfr; /* cost of an MSGFR instruction. */
87 const int msgr; /* cost of an MSGR instruction. */
88 const int msr; /* cost of an MSR instruction. */
89 const int mult_df; /* cost of multiplication in DFmode. */
429f9fdb 90 const int mxbr;
260075cc 91 /* square root */
429f9fdb 92 const int sqxbr; /* cost of square root in TFmode. */
9cd3f3e6 93 const int sqdbr; /* cost of square root in DFmode. */
94 const int sqebr; /* cost of square root in SFmode. */
260075cc 95 /* multiply and add */
d95e38cf 96 const int madbr; /* cost of multiply and add in DFmode. */
97 const int maebr; /* cost of multiply and add in SFmode. */
260075cc 98 /* division */
429f9fdb 99 const int dxbr;
260075cc 100 const int ddbr;
260075cc 101 const int debr;
3f074425 102 const int dlgr;
103 const int dlr;
104 const int dr;
105 const int dsgfr;
106 const int dsgr;
18925d38 107};
108
109const struct processor_costs *s390_cost;
110
111static const
ffead1ca 112struct processor_costs z900_cost =
18925d38 113{
114 COSTS_N_INSNS (5), /* M */
115 COSTS_N_INSNS (10), /* MGHI */
116 COSTS_N_INSNS (5), /* MH */
117 COSTS_N_INSNS (4), /* MHI */
9cd3f3e6 118 COSTS_N_INSNS (5), /* ML */
18925d38 119 COSTS_N_INSNS (5), /* MR */
120 COSTS_N_INSNS (4), /* MS */
121 COSTS_N_INSNS (15), /* MSG */
122 COSTS_N_INSNS (7), /* MSGF */
123 COSTS_N_INSNS (7), /* MSGFR */
124 COSTS_N_INSNS (10), /* MSGR */
125 COSTS_N_INSNS (4), /* MSR */
126 COSTS_N_INSNS (7), /* multiplication in DFmode */
429f9fdb 127 COSTS_N_INSNS (13), /* MXBR */
128 COSTS_N_INSNS (136), /* SQXBR */
9cd3f3e6 129 COSTS_N_INSNS (44), /* SQDBR */
130 COSTS_N_INSNS (35), /* SQEBR */
d95e38cf 131 COSTS_N_INSNS (18), /* MADBR */
132 COSTS_N_INSNS (13), /* MAEBR */
429f9fdb 133 COSTS_N_INSNS (134), /* DXBR */
260075cc 134 COSTS_N_INSNS (30), /* DDBR */
260075cc 135 COSTS_N_INSNS (27), /* DEBR */
3f074425 136 COSTS_N_INSNS (220), /* DLGR */
137 COSTS_N_INSNS (34), /* DLR */
138 COSTS_N_INSNS (34), /* DR */
139 COSTS_N_INSNS (32), /* DSGFR */
140 COSTS_N_INSNS (32), /* DSGR */
18925d38 141};
142
143static const
ffead1ca 144struct processor_costs z990_cost =
18925d38 145{
146 COSTS_N_INSNS (4), /* M */
147 COSTS_N_INSNS (2), /* MGHI */
148 COSTS_N_INSNS (2), /* MH */
149 COSTS_N_INSNS (2), /* MHI */
9cd3f3e6 150 COSTS_N_INSNS (4), /* ML */
18925d38 151 COSTS_N_INSNS (4), /* MR */
152 COSTS_N_INSNS (5), /* MS */
153 COSTS_N_INSNS (6), /* MSG */
154 COSTS_N_INSNS (4), /* MSGF */
155 COSTS_N_INSNS (4), /* MSGFR */
156 COSTS_N_INSNS (4), /* MSGR */
157 COSTS_N_INSNS (4), /* MSR */
158 COSTS_N_INSNS (1), /* multiplication in DFmode */
429f9fdb 159 COSTS_N_INSNS (28), /* MXBR */
160 COSTS_N_INSNS (130), /* SQXBR */
9cd3f3e6 161 COSTS_N_INSNS (66), /* SQDBR */
162 COSTS_N_INSNS (38), /* SQEBR */
d95e38cf 163 COSTS_N_INSNS (1), /* MADBR */
164 COSTS_N_INSNS (1), /* MAEBR */
429f9fdb 165 COSTS_N_INSNS (60), /* DXBR */
260075cc 166 COSTS_N_INSNS (40), /* DDBR */
095798e3 167 COSTS_N_INSNS (26), /* DEBR */
3f074425 168 COSTS_N_INSNS (176), /* DLGR */
169 COSTS_N_INSNS (31), /* DLR */
170 COSTS_N_INSNS (31), /* DR */
171 COSTS_N_INSNS (31), /* DSGFR */
172 COSTS_N_INSNS (31), /* DSGR */
18925d38 173};
174
163277cf 175static const
ffead1ca 176struct processor_costs z9_109_cost =
163277cf 177{
178 COSTS_N_INSNS (4), /* M */
179 COSTS_N_INSNS (2), /* MGHI */
180 COSTS_N_INSNS (2), /* MH */
181 COSTS_N_INSNS (2), /* MHI */
182 COSTS_N_INSNS (4), /* ML */
183 COSTS_N_INSNS (4), /* MR */
184 COSTS_N_INSNS (5), /* MS */
185 COSTS_N_INSNS (6), /* MSG */
186 COSTS_N_INSNS (4), /* MSGF */
187 COSTS_N_INSNS (4), /* MSGFR */
188 COSTS_N_INSNS (4), /* MSGR */
189 COSTS_N_INSNS (4), /* MSR */
190 COSTS_N_INSNS (1), /* multiplication in DFmode */
429f9fdb 191 COSTS_N_INSNS (28), /* MXBR */
192 COSTS_N_INSNS (130), /* SQXBR */
163277cf 193 COSTS_N_INSNS (66), /* SQDBR */
194 COSTS_N_INSNS (38), /* SQEBR */
195 COSTS_N_INSNS (1), /* MADBR */
196 COSTS_N_INSNS (1), /* MAEBR */
429f9fdb 197 COSTS_N_INSNS (60), /* DXBR */
163277cf 198 COSTS_N_INSNS (40), /* DDBR */
095798e3 199 COSTS_N_INSNS (26), /* DEBR */
163277cf 200 COSTS_N_INSNS (30), /* DLGR */
201 COSTS_N_INSNS (23), /* DLR */
202 COSTS_N_INSNS (23), /* DR */
203 COSTS_N_INSNS (24), /* DSGFR */
204 COSTS_N_INSNS (24), /* DSGR */
205};
18925d38 206
a850370e 207static const
208struct processor_costs z10_cost =
209{
510c2327 210 COSTS_N_INSNS (10), /* M */
211 COSTS_N_INSNS (10), /* MGHI */
212 COSTS_N_INSNS (10), /* MH */
213 COSTS_N_INSNS (10), /* MHI */
214 COSTS_N_INSNS (10), /* ML */
215 COSTS_N_INSNS (10), /* MR */
216 COSTS_N_INSNS (10), /* MS */
217 COSTS_N_INSNS (10), /* MSG */
218 COSTS_N_INSNS (10), /* MSGF */
219 COSTS_N_INSNS (10), /* MSGFR */
220 COSTS_N_INSNS (10), /* MSGR */
221 COSTS_N_INSNS (10), /* MSR */
b0eacf26 222 COSTS_N_INSNS (1) , /* multiplication in DFmode */
510c2327 223 COSTS_N_INSNS (50), /* MXBR */
224 COSTS_N_INSNS (120), /* SQXBR */
225 COSTS_N_INSNS (52), /* SQDBR */
a850370e 226 COSTS_N_INSNS (38), /* SQEBR */
b0eacf26 227 COSTS_N_INSNS (1), /* MADBR */
228 COSTS_N_INSNS (1), /* MAEBR */
510c2327 229 COSTS_N_INSNS (111), /* DXBR */
230 COSTS_N_INSNS (39), /* DDBR */
231 COSTS_N_INSNS (32), /* DEBR */
232 COSTS_N_INSNS (160), /* DLGR */
233 COSTS_N_INSNS (71), /* DLR */
234 COSTS_N_INSNS (71), /* DR */
235 COSTS_N_INSNS (71), /* DSGFR */
236 COSTS_N_INSNS (71), /* DSGR */
a850370e 237};
238
33d033da 239static const
240struct processor_costs z196_cost =
241{
242 COSTS_N_INSNS (7), /* M */
243 COSTS_N_INSNS (5), /* MGHI */
244 COSTS_N_INSNS (5), /* MH */
245 COSTS_N_INSNS (5), /* MHI */
246 COSTS_N_INSNS (7), /* ML */
247 COSTS_N_INSNS (7), /* MR */
248 COSTS_N_INSNS (6), /* MS */
249 COSTS_N_INSNS (8), /* MSG */
250 COSTS_N_INSNS (6), /* MSGF */
251 COSTS_N_INSNS (6), /* MSGFR */
252 COSTS_N_INSNS (8), /* MSGR */
253 COSTS_N_INSNS (6), /* MSR */
254 COSTS_N_INSNS (1) , /* multiplication in DFmode */
255 COSTS_N_INSNS (40), /* MXBR B+40 */
256 COSTS_N_INSNS (100), /* SQXBR B+100 */
257 COSTS_N_INSNS (42), /* SQDBR B+42 */
258 COSTS_N_INSNS (28), /* SQEBR B+28 */
259 COSTS_N_INSNS (1), /* MADBR B */
260 COSTS_N_INSNS (1), /* MAEBR B */
261 COSTS_N_INSNS (101), /* DXBR B+101 */
262 COSTS_N_INSNS (29), /* DDBR */
263 COSTS_N_INSNS (22), /* DEBR */
264 COSTS_N_INSNS (160), /* DLGR cracked */
265 COSTS_N_INSNS (160), /* DLR cracked */
266 COSTS_N_INSNS (160), /* DR expanded */
267 COSTS_N_INSNS (160), /* DSGFR cracked */
268 COSTS_N_INSNS (160), /* DSGR cracked */
269};
270
81769881 271static const
272struct processor_costs zEC12_cost =
273{
274 COSTS_N_INSNS (7), /* M */
275 COSTS_N_INSNS (5), /* MGHI */
276 COSTS_N_INSNS (5), /* MH */
277 COSTS_N_INSNS (5), /* MHI */
278 COSTS_N_INSNS (7), /* ML */
279 COSTS_N_INSNS (7), /* MR */
280 COSTS_N_INSNS (6), /* MS */
281 COSTS_N_INSNS (8), /* MSG */
282 COSTS_N_INSNS (6), /* MSGF */
283 COSTS_N_INSNS (6), /* MSGFR */
284 COSTS_N_INSNS (8), /* MSGR */
285 COSTS_N_INSNS (6), /* MSR */
286 COSTS_N_INSNS (1) , /* multiplication in DFmode */
287 COSTS_N_INSNS (40), /* MXBR B+40 */
288 COSTS_N_INSNS (100), /* SQXBR B+100 */
289 COSTS_N_INSNS (42), /* SQDBR B+42 */
290 COSTS_N_INSNS (28), /* SQEBR B+28 */
291 COSTS_N_INSNS (1), /* MADBR B */
292 COSTS_N_INSNS (1), /* MAEBR B */
293 COSTS_N_INSNS (131), /* DXBR B+131 */
294 COSTS_N_INSNS (29), /* DDBR */
295 COSTS_N_INSNS (22), /* DEBR */
296 COSTS_N_INSNS (160), /* DLGR cracked */
297 COSTS_N_INSNS (160), /* DLR cracked */
298 COSTS_N_INSNS (160), /* DR expanded */
299 COSTS_N_INSNS (160), /* DSGFR cracked */
300 COSTS_N_INSNS (160), /* DSGR cracked */
301};
302
4673c1a0 303extern int reload_completed;
304
8a2a84e3 305/* Kept up to date using the SCHED_VARIABLE_ISSUE hook. */
306static rtx last_scheduled_insn;
307
56769981 308/* Structure used to hold the components of a S/390 memory
309 address. A legitimate address on S/390 is of the general
310 form
311 base + index + displacement
312 where any of the components is optional.
313
314 base and index are registers of the class ADDR_REGS,
315 displacement is an unsigned 12-bit immediate constant. */
4673c1a0 316
317struct s390_address
318{
319 rtx base;
320 rtx indx;
321 rtx disp;
e5537457 322 bool pointer;
05b58257 323 bool literal_pool;
4673c1a0 324};
325
ffead1ca 326/* The following structure is embedded in the machine
67928721 327 specific part of struct function. */
328
fb1e4f4a 329struct GTY (()) s390_frame_layout
67928721 330{
331 /* Offset within stack frame. */
332 HOST_WIDE_INT gprs_offset;
333 HOST_WIDE_INT f0_offset;
334 HOST_WIDE_INT f4_offset;
335 HOST_WIDE_INT f8_offset;
336 HOST_WIDE_INT backchain_offset;
5214e6ae 337
338 /* Number of first and last gpr where slots in the register
339 save area are reserved for. */
340 int first_save_gpr_slot;
341 int last_save_gpr_slot;
342
ff4ce128 343 /* Location (FP register number) where GPRs (r0-r15) should
344 be saved to.
345 0 - does not need to be saved at all
346 -1 - stack slot */
347 signed char gpr_save_slots[16];
348
5a5e802f 349 /* Number of first and last gpr to be saved, restored. */
8b4a4127 350 int first_save_gpr;
351 int first_restore_gpr;
352 int last_save_gpr;
beee1f75 353 int last_restore_gpr;
8b4a4127 354
ffead1ca 355 /* Bits standing for floating point registers. Set, if the
356 respective register has to be saved. Starting with reg 16 (f0)
67928721 357 at the rightmost bit.
6a2469fe 358 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
359 fpr 15 13 11 9 14 12 10 8 7 5 3 1 6 4 2 0
360 reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 */
67928721 361 unsigned int fpr_bitmap;
362
363 /* Number of floating point registers f8-f15 which must be saved. */
364 int high_fprs;
365
9bee2845 366 /* Set if return address needs to be saved.
367 This flag is set by s390_return_addr_rtx if it could not use
368 the initial value of r14 and therefore depends on r14 saved
369 to the stack. */
67928721 370 bool save_return_addr_p;
371
5a5e802f 372 /* Size of stack frame. */
8b4a4127 373 HOST_WIDE_INT frame_size;
67928721 374};
375
376/* Define the structure for the machine field in struct function. */
377
fb1e4f4a 378struct GTY(()) machine_function
67928721 379{
380 struct s390_frame_layout frame_layout;
be00aaa8 381
20074f87 382 /* Literal pool base register. */
383 rtx base_reg;
384
4fed3f99 385 /* True if we may need to perform branch splitting. */
386 bool split_branches_pending_p;
387
be00aaa8 388 /* Some local-dynamic TLS symbol name. */
389 const char *some_ld_name;
1e639cb0 390
391 bool has_landing_pad_p;
5ada7a14 392
393 /* True if the current function may contain a tbegin clobbering
394 FPRs. */
395 bool tbegin_p;
8b4a4127 396};
397
67928721 398/* Few accessor macros for struct cfun->machine->s390_frame_layout. */
399
400#define cfun_frame_layout (cfun->machine->frame_layout)
401#define cfun_save_high_fprs_p (!!cfun_frame_layout.high_fprs)
ff4ce128 402#define cfun_save_arg_fprs_p (!!(TARGET_64BIT \
403 ? cfun_frame_layout.fpr_bitmap & 0x0f \
404 : cfun_frame_layout.fpr_bitmap & 0x03))
405#define cfun_gprs_save_area_size ((cfun_frame_layout.last_save_gpr_slot - \
b5fdc416 406 cfun_frame_layout.first_save_gpr_slot + 1) * UNITS_PER_LONG)
29439367 407#define cfun_set_fpr_save(REGNO) (cfun->machine->frame_layout.fpr_bitmap |= \
6a2469fe 408 (1 << (REGNO - FPR0_REGNUM)))
29439367 409#define cfun_fpr_save_p(REGNO) (!!(cfun->machine->frame_layout.fpr_bitmap & \
6a2469fe 410 (1 << (REGNO - FPR0_REGNUM))))
ff4ce128 411#define cfun_gpr_save_slot(REGNO) \
412 cfun->machine->frame_layout.gpr_save_slots[REGNO]
67928721 413
6902d973 414/* Number of GPRs and FPRs used for argument passing. */
415#define GP_ARG_NUM_REG 5
416#define FP_ARG_NUM_REG (TARGET_64BIT? 4 : 2)
417
cb888f33 418/* A couple of shortcuts. */
419#define CONST_OK_FOR_J(x) \
420 CONST_OK_FOR_CONSTRAINT_P((x), 'J', "J")
421#define CONST_OK_FOR_K(x) \
422 CONST_OK_FOR_CONSTRAINT_P((x), 'K', "K")
163277cf 423#define CONST_OK_FOR_Os(x) \
424 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Os")
425#define CONST_OK_FOR_Op(x) \
426 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "Op")
427#define CONST_OK_FOR_On(x) \
428 CONST_OK_FOR_CONSTRAINT_P((x), 'O', "On")
cb888f33 429
8f1128bb 430#define REGNO_PAIR_OK(REGNO, MODE) \
431 (HARD_REGNO_NREGS ((REGNO), (MODE)) == 1 || !((REGNO) & 1))
432
73df8a45 433/* That's the read ahead of the dynamic branch prediction unit in
33d033da 434 bytes on a z10 (or higher) CPU. */
435#define PREDICT_DISTANCE (TARGET_Z10 ? 384 : 2048)
73df8a45 436
6d0afa28 437/* Return the alignment for LABEL. We default to the -falign-labels
438 value except for the literal pool base label. */
439int
440s390_label_align (rtx label)
441{
442 rtx prev_insn = prev_active_insn (label);
443
444 if (prev_insn == NULL_RTX)
445 goto old;
446
447 prev_insn = single_set (prev_insn);
448
449 if (prev_insn == NULL_RTX)
450 goto old;
451
452 prev_insn = SET_SRC (prev_insn);
453
454 /* Don't align literal pool base labels. */
455 if (GET_CODE (prev_insn) == UNSPEC
456 && XINT (prev_insn, 1) == UNSPEC_MAIN_BASE)
457 return 0;
458
459 old:
460 return align_labels_log;
461}
462
0ef89dfd 463static enum machine_mode
464s390_libgcc_cmp_return_mode (void)
465{
466 return TARGET_64BIT ? DImode : SImode;
467}
468
469static enum machine_mode
470s390_libgcc_shift_count_mode (void)
471{
472 return TARGET_64BIT ? DImode : SImode;
473}
474
b5fdc416 475static enum machine_mode
476s390_unwind_word_mode (void)
477{
478 return TARGET_64BIT ? DImode : SImode;
479}
480
36868490 481/* Return true if the back end supports mode MODE. */
482static bool
483s390_scalar_mode_supported_p (enum machine_mode mode)
484{
b5fdc416 485 /* In contrast to the default implementation reject TImode constants on 31bit
486 TARGET_ZARCH for ABI compliance. */
487 if (!TARGET_64BIT && TARGET_ZARCH && mode == TImode)
488 return false;
489
36868490 490 if (DECIMAL_FLOAT_MODE_P (mode))
8e72d11d 491 return default_decimal_float_supported_p ();
b5fdc416 492
493 return default_scalar_mode_supported_p (mode);
36868490 494}
495
1e639cb0 496/* Set the has_landing_pad_p flag in struct machine_function to VALUE. */
497
498void
499s390_set_has_landing_pad_p (bool value)
500{
501 cfun->machine->has_landing_pad_p = value;
502}
6902d973 503
9c93d843 504/* If two condition code modes are compatible, return a condition code
505 mode which is compatible with both. Otherwise, return
506 VOIDmode. */
507
508static enum machine_mode
509s390_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2)
510{
511 if (m1 == m2)
512 return m1;
513
514 switch (m1)
515 {
516 case CCZmode:
517 if (m2 == CCUmode || m2 == CCTmode || m2 == CCZ1mode
518 || m2 == CCSmode || m2 == CCSRmode || m2 == CCURmode)
519 return m2;
520 return VOIDmode;
521
522 case CCSmode:
523 case CCUmode:
524 case CCTmode:
525 case CCSRmode:
526 case CCURmode:
527 case CCZ1mode:
528 if (m2 == CCZmode)
529 return m1;
ffead1ca 530
9c93d843 531 return VOIDmode;
532
533 default:
534 return VOIDmode;
535 }
536 return VOIDmode;
537}
538
56769981 539/* Return true if SET either doesn't set the CC register, or else
f81e845f 540 the source and destination have matching CC modes and that
56769981 541 CC mode is at least as constrained as REQ_MODE. */
f81e845f 542
e5537457 543static bool
b40da9a7 544s390_match_ccmode_set (rtx set, enum machine_mode req_mode)
4673c1a0 545{
56769981 546 enum machine_mode set_mode;
4673c1a0 547
32eda510 548 gcc_assert (GET_CODE (set) == SET);
4673c1a0 549
550 if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
551 return 1;
552
553 set_mode = GET_MODE (SET_DEST (set));
554 switch (set_mode)
555 {
4673c1a0 556 case CCSmode:
c6821d1c 557 case CCSRmode:
4673c1a0 558 case CCUmode:
c6821d1c 559 case CCURmode:
2eb8fe23 560 case CCLmode:
c6821d1c 561 case CCL1mode:
562 case CCL2mode:
3b699fc7 563 case CCL3mode:
c6821d1c 564 case CCT1mode:
565 case CCT2mode:
566 case CCT3mode:
567 if (req_mode != set_mode)
2eb8fe23 568 return 0;
569 break;
c6821d1c 570
4673c1a0 571 case CCZmode:
c6821d1c 572 if (req_mode != CCSmode && req_mode != CCUmode && req_mode != CCTmode
573 && req_mode != CCSRmode && req_mode != CCURmode)
4673c1a0 574 return 0;
575 break;
3c482144 576
577 case CCAPmode:
578 case CCANmode:
579 if (req_mode != CCAmode)
580 return 0;
581 break;
f81e845f 582
4673c1a0 583 default:
32eda510 584 gcc_unreachable ();
4673c1a0 585 }
f81e845f 586
4673c1a0 587 return (GET_MODE (SET_SRC (set)) == set_mode);
588}
589
f81e845f 590/* Return true if every SET in INSN that sets the CC register
591 has source and destination with matching CC modes and that
592 CC mode is at least as constrained as REQ_MODE.
c6821d1c 593 If REQ_MODE is VOIDmode, always return false. */
f81e845f 594
e5537457 595bool
b40da9a7 596s390_match_ccmode (rtx insn, enum machine_mode req_mode)
4673c1a0 597{
598 int i;
599
c6821d1c 600 /* s390_tm_ccmode returns VOIDmode to indicate failure. */
601 if (req_mode == VOIDmode)
e5537457 602 return false;
c6821d1c 603
4673c1a0 604 if (GET_CODE (PATTERN (insn)) == SET)
605 return s390_match_ccmode_set (PATTERN (insn), req_mode);
606
607 if (GET_CODE (PATTERN (insn)) == PARALLEL)
608 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
609 {
610 rtx set = XVECEXP (PATTERN (insn), 0, i);
611 if (GET_CODE (set) == SET)
612 if (!s390_match_ccmode_set (set, req_mode))
e5537457 613 return false;
4673c1a0 614 }
615
e5537457 616 return true;
4673c1a0 617}
618
f81e845f 619/* If a test-under-mask instruction can be used to implement
c6821d1c 620 (compare (and ... OP1) OP2), return the CC mode required
f81e845f 621 to do that. Otherwise, return VOIDmode.
c6821d1c 622 MIXED is true if the instruction can distinguish between
623 CC1 and CC2 for mixed selected bits (TMxx), it is false
624 if the instruction cannot (TM). */
625
626enum machine_mode
e5537457 627s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
c6821d1c 628{
629 int bit0, bit1;
630
631 /* ??? Fixme: should work on CONST_DOUBLE as well. */
632 if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
633 return VOIDmode;
634
eeba5f25 635 /* Selected bits all zero: CC0.
636 e.g.: int a; if ((a & (16 + 128)) == 0) */
c6821d1c 637 if (INTVAL (op2) == 0)
638 return CCTmode;
639
ffead1ca 640 /* Selected bits all one: CC3.
eeba5f25 641 e.g.: int a; if ((a & (16 + 128)) == 16 + 128) */
c6821d1c 642 if (INTVAL (op2) == INTVAL (op1))
643 return CCT3mode;
644
eeba5f25 645 /* Exactly two bits selected, mixed zeroes and ones: CC1 or CC2. e.g.:
646 int a;
647 if ((a & (16 + 128)) == 16) -> CCT1
648 if ((a & (16 + 128)) == 128) -> CCT2 */
c6821d1c 649 if (mixed)
650 {
651 bit1 = exact_log2 (INTVAL (op2));
652 bit0 = exact_log2 (INTVAL (op1) ^ INTVAL (op2));
653 if (bit0 != -1 && bit1 != -1)
654 return bit0 > bit1 ? CCT1mode : CCT2mode;
655 }
656
657 return VOIDmode;
658}
659
f81e845f 660/* Given a comparison code OP (EQ, NE, etc.) and the operands
661 OP0 and OP1 of a COMPARE, return the mode to be used for the
2eb8fe23 662 comparison. */
663
664enum machine_mode
b40da9a7 665s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
2eb8fe23 666{
667 switch (code)
668 {
669 case EQ:
670 case NE:
9be33ca2 671 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
672 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
673 return CCAPmode;
3c482144 674 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
cb888f33 675 && CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
3c482144 676 return CCAPmode;
e9fd5349 677 if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
678 || GET_CODE (op1) == NEG)
679 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
2eb8fe23 680 return CCLmode;
681
c6821d1c 682 if (GET_CODE (op0) == AND)
683 {
684 /* Check whether we can potentially do it via TM. */
685 enum machine_mode ccmode;
686 ccmode = s390_tm_ccmode (XEXP (op0, 1), op1, 1);
687 if (ccmode != VOIDmode)
688 {
689 /* Relax CCTmode to CCZmode to allow fall-back to AND
690 if that turns out to be beneficial. */
691 return ccmode == CCTmode ? CCZmode : ccmode;
692 }
693 }
694
f81e845f 695 if (register_operand (op0, HImode)
c6821d1c 696 && GET_CODE (op1) == CONST_INT
697 && (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
698 return CCT3mode;
f81e845f 699 if (register_operand (op0, QImode)
c6821d1c 700 && GET_CODE (op1) == CONST_INT
701 && (INTVAL (op1) == -1 || INTVAL (op1) == 255))
702 return CCT3mode;
703
2eb8fe23 704 return CCZmode;
705
706 case LE:
707 case LT:
708 case GE:
709 case GT:
eeba5f25 710 /* The only overflow condition of NEG and ABS happens when
711 -INT_MAX is used as parameter, which stays negative. So
ffead1ca 712 we have an overflow from a positive value to a negative.
eeba5f25 713 Using CCAP mode the resulting cc can be used for comparisons. */
9be33ca2 714 if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
715 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
716 return CCAPmode;
eeba5f25 717
718 /* If constants are involved in an add instruction it is possible to use
719 the resulting cc for comparisons with zero. Knowing the sign of the
0975351b 720 constant the overflow behavior gets predictable. e.g.:
ffead1ca 721 int a, b; if ((b = a + c) > 0)
eeba5f25 722 with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
9be33ca2 723 if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
ea14438e 724 && (CONST_OK_FOR_K (INTVAL (XEXP (op0, 1)))
725 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0, 1)), 'O', "Os")
726 /* Avoid INT32_MIN on 32 bit. */
727 && (!TARGET_ZARCH || INTVAL (XEXP (op0, 1)) != -0x7fffffff - 1))))
9be33ca2 728 {
729 if (INTVAL (XEXP((op0), 1)) < 0)
730 return CCANmode;
731 else
732 return CCAPmode;
733 }
734 /* Fall through. */
2eb8fe23 735 case UNORDERED:
736 case ORDERED:
737 case UNEQ:
738 case UNLE:
739 case UNLT:
740 case UNGE:
741 case UNGT:
742 case LTGT:
c6821d1c 743 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
744 && GET_CODE (op1) != CONST_INT)
745 return CCSRmode;
2eb8fe23 746 return CCSmode;
747
2eb8fe23 748 case LTU:
749 case GEU:
e9fd5349 750 if (GET_CODE (op0) == PLUS
751 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
c6821d1c 752 return CCL1mode;
753
754 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
755 && GET_CODE (op1) != CONST_INT)
756 return CCURmode;
757 return CCUmode;
758
759 case LEU:
2eb8fe23 760 case GTU:
e9fd5349 761 if (GET_CODE (op0) == MINUS
762 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
c6821d1c 763 return CCL2mode;
764
765 if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
766 && GET_CODE (op1) != CONST_INT)
767 return CCURmode;
2eb8fe23 768 return CCUmode;
769
770 default:
32eda510 771 gcc_unreachable ();
2eb8fe23 772 }
773}
774
ebe32bb0 775/* Replace the comparison OP0 CODE OP1 by a semantically equivalent one
776 that we can implement more efficiently. */
777
d5065e6e 778static void
779s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
780 bool op0_preserve_value)
ebe32bb0 781{
d5065e6e 782 if (op0_preserve_value)
783 return;
784
ebe32bb0 785 /* Convert ZERO_EXTRACT back to AND to enable TM patterns. */
786 if ((*code == EQ || *code == NE)
787 && *op1 == const0_rtx
788 && GET_CODE (*op0) == ZERO_EXTRACT
789 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
790 && GET_CODE (XEXP (*op0, 2)) == CONST_INT
791 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
792 {
793 rtx inner = XEXP (*op0, 0);
794 HOST_WIDE_INT modesize = GET_MODE_BITSIZE (GET_MODE (inner));
795 HOST_WIDE_INT len = INTVAL (XEXP (*op0, 1));
796 HOST_WIDE_INT pos = INTVAL (XEXP (*op0, 2));
797
798 if (len > 0 && len < modesize
799 && pos >= 0 && pos + len <= modesize
800 && modesize <= HOST_BITS_PER_WIDE_INT)
801 {
802 unsigned HOST_WIDE_INT block;
803 block = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
804 block <<= modesize - pos - len;
805
806 *op0 = gen_rtx_AND (GET_MODE (inner), inner,
807 gen_int_mode (block, GET_MODE (inner)));
808 }
809 }
810
811 /* Narrow AND of memory against immediate to enable TM. */
812 if ((*code == EQ || *code == NE)
813 && *op1 == const0_rtx
814 && GET_CODE (*op0) == AND
815 && GET_CODE (XEXP (*op0, 1)) == CONST_INT
816 && SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
817 {
818 rtx inner = XEXP (*op0, 0);
819 rtx mask = XEXP (*op0, 1);
820
821 /* Ignore paradoxical SUBREGs if all extra bits are masked out. */
822 if (GET_CODE (inner) == SUBREG
823 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
824 && (GET_MODE_SIZE (GET_MODE (inner))
825 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
826 && ((INTVAL (mask)
827 & GET_MODE_MASK (GET_MODE (inner))
828 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (inner))))
829 == 0))
830 inner = SUBREG_REG (inner);
831
832 /* Do not change volatile MEMs. */
833 if (MEM_P (inner) && !MEM_VOLATILE_P (inner))
834 {
835 int part = s390_single_part (XEXP (*op0, 1),
836 GET_MODE (inner), QImode, 0);
837 if (part >= 0)
838 {
839 mask = gen_int_mode (s390_extract_part (mask, QImode, 0), QImode);
840 inner = adjust_address_nv (inner, QImode, part);
841 *op0 = gen_rtx_AND (QImode, inner, mask);
842 }
843 }
844 }
845
846 /* Narrow comparisons against 0xffff to HImode if possible. */
ebe32bb0 847 if ((*code == EQ || *code == NE)
848 && GET_CODE (*op1) == CONST_INT
849 && INTVAL (*op1) == 0xffff
850 && SCALAR_INT_MODE_P (GET_MODE (*op0))
ffead1ca 851 && (nonzero_bits (*op0, GET_MODE (*op0))
ebe32bb0 852 & ~(unsigned HOST_WIDE_INT) 0xffff) == 0)
853 {
854 *op0 = gen_lowpart (HImode, *op0);
855 *op1 = constm1_rtx;
856 }
80b53886 857
5ada7a14 858 /* Remove redundant UNSPEC_STRCMPCC_TO_INT conversions if possible. */
80b53886 859 if (GET_CODE (*op0) == UNSPEC
5ada7a14 860 && XINT (*op0, 1) == UNSPEC_STRCMPCC_TO_INT
80b53886 861 && XVECLEN (*op0, 0) == 1
862 && GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
863 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
864 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
865 && *op1 == const0_rtx)
866 {
867 enum rtx_code new_code = UNKNOWN;
868 switch (*code)
869 {
870 case EQ: new_code = EQ; break;
871 case NE: new_code = NE; break;
dd16a4bd 872 case LT: new_code = GTU; break;
873 case GT: new_code = LTU; break;
874 case LE: new_code = GEU; break;
875 case GE: new_code = LEU; break;
80b53886 876 default: break;
877 }
878
879 if (new_code != UNKNOWN)
880 {
881 *op0 = XVECEXP (*op0, 0, 0);
882 *code = new_code;
883 }
884 }
9c93d843 885
5ada7a14 886 /* Remove redundant UNSPEC_CC_TO_INT conversions if possible. */
27784c70 887 if (GET_CODE (*op0) == UNSPEC
5ada7a14 888 && XINT (*op0, 1) == UNSPEC_CC_TO_INT
27784c70 889 && XVECLEN (*op0, 0) == 1
27784c70 890 && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
891 && REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
5ada7a14 892 && CONST_INT_P (*op1))
27784c70 893 {
894 enum rtx_code new_code = UNKNOWN;
5ada7a14 895 switch (GET_MODE (XVECEXP (*op0, 0, 0)))
27784c70 896 {
5ada7a14 897 case CCZmode:
898 case CCRAWmode:
899 switch (*code)
900 {
901 case EQ: new_code = EQ; break;
902 case NE: new_code = NE; break;
903 default: break;
904 }
905 break;
906 default: break;
27784c70 907 }
908
909 if (new_code != UNKNOWN)
910 {
5ada7a14 911 /* For CCRAWmode put the required cc mask into the second
912 operand. */
91dfd73e 913 if (GET_MODE (XVECEXP (*op0, 0, 0)) == CCRAWmode
914 && INTVAL (*op1) >= 0 && INTVAL (*op1) <= 3)
5ada7a14 915 *op1 = gen_rtx_CONST_INT (VOIDmode, 1 << (3 - INTVAL (*op1)));
27784c70 916 *op0 = XVECEXP (*op0, 0, 0);
917 *code = new_code;
918 }
919 }
920
9c93d843 921 /* Simplify cascaded EQ, NE with const0_rtx. */
922 if ((*code == NE || *code == EQ)
923 && (GET_CODE (*op0) == EQ || GET_CODE (*op0) == NE)
924 && GET_MODE (*op0) == SImode
925 && GET_MODE (XEXP (*op0, 0)) == CCZ1mode
926 && REG_P (XEXP (*op0, 0))
927 && XEXP (*op0, 1) == const0_rtx
928 && *op1 == const0_rtx)
929 {
930 if ((*code == EQ && GET_CODE (*op0) == NE)
931 || (*code == NE && GET_CODE (*op0) == EQ))
932 *code = EQ;
933 else
934 *code = NE;
935 *op0 = XEXP (*op0, 0);
936 }
a0631a8a 937
938 /* Prefer register over memory as first operand. */
939 if (MEM_P (*op0) && REG_P (*op1))
940 {
941 rtx tem = *op0; *op0 = *op1; *op1 = tem;
d5065e6e 942 *code = (int)swap_condition ((enum rtx_code)*code);
a0631a8a 943 }
ebe32bb0 944}
945
0d656e8b 946/* Emit a compare instruction suitable to implement the comparison
947 OP0 CODE OP1. Return the correct condition RTL to be placed in
948 the IF_THEN_ELSE of the conditional branch testing the result. */
949
950rtx
951s390_emit_compare (enum rtx_code code, rtx op0, rtx op1)
952{
953 enum machine_mode mode = s390_select_ccmode (code, op0, op1);
8e58aded 954 rtx cc;
0d656e8b 955
891e3096 956 /* Do not output a redundant compare instruction if a compare_and_swap
9c93d843 957 pattern already computed the result and the machine modes are compatible. */
8e58aded 958 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
959 {
960 gcc_assert (s390_cc_modes_compatible (GET_MODE (op0), mode)
961 == GET_MODE (op0));
962 cc = op0;
963 }
891e3096 964 else
965 {
8e58aded 966 cc = gen_rtx_REG (mode, CC_REGNUM);
891e3096 967 emit_insn (gen_rtx_SET (VOIDmode, cc, gen_rtx_COMPARE (mode, op0, op1)));
891e3096 968 }
8e58aded 969
ffead1ca 970 return gen_rtx_fmt_ee (code, VOIDmode, cc, const0_rtx);
0d656e8b 971}
972
8deb3959 973/* Emit a SImode compare and swap instruction setting MEM to NEW_RTX if OLD
db1f11e3 974 matches CMP.
975 Return the correct condition RTL to be placed in the IF_THEN_ELSE of the
976 conditional branch testing the result. */
977
978static rtx
8c753480 979s390_emit_compare_and_swap (enum rtx_code code, rtx old, rtx mem,
980 rtx cmp, rtx new_rtx)
db1f11e3 981{
8c753480 982 emit_insn (gen_atomic_compare_and_swapsi_internal (old, mem, cmp, new_rtx));
983 return s390_emit_compare (code, gen_rtx_REG (CCZ1mode, CC_REGNUM),
984 const0_rtx);
db1f11e3 985}
986
5ada7a14 987/* Emit a jump instruction to TARGET and return it. If COND is
988 NULL_RTX, emit an unconditional jump, else a conditional jump under
989 condition COND. */
0d656e8b 990
5ada7a14 991rtx
0d656e8b 992s390_emit_jump (rtx target, rtx cond)
993{
994 rtx insn;
995
996 target = gen_rtx_LABEL_REF (VOIDmode, target);
997 if (cond)
998 target = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, target, pc_rtx);
999
1000 insn = gen_rtx_SET (VOIDmode, pc_rtx, target);
5ada7a14 1001 return emit_jump_insn (insn);
0d656e8b 1002}
1003
f81e845f 1004/* Return branch condition mask to implement a branch
80b53886 1005 specified by CODE. Return -1 for invalid comparisons. */
2eb8fe23 1006
8cc5de33 1007int
b40da9a7 1008s390_branch_condition_mask (rtx code)
f81e845f 1009{
2eb8fe23 1010 const int CC0 = 1 << 3;
1011 const int CC1 = 1 << 2;
1012 const int CC2 = 1 << 1;
1013 const int CC3 = 1 << 0;
1014
32eda510 1015 gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
1016 gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
5ada7a14 1017 gcc_assert (XEXP (code, 1) == const0_rtx
1018 || (GET_MODE (XEXP (code, 0)) == CCRAWmode
1019 && CONST_INT_P (XEXP (code, 1))));
1020
2eb8fe23 1021
1022 switch (GET_MODE (XEXP (code, 0)))
1023 {
1024 case CCZmode:
9c93d843 1025 case CCZ1mode:
2eb8fe23 1026 switch (GET_CODE (code))
1027 {
1028 case EQ: return CC0;
1029 case NE: return CC1 | CC2 | CC3;
80b53886 1030 default: return -1;
2eb8fe23 1031 }
1032 break;
1033
c6821d1c 1034 case CCT1mode:
1035 switch (GET_CODE (code))
1036 {
1037 case EQ: return CC1;
1038 case NE: return CC0 | CC2 | CC3;
80b53886 1039 default: return -1;
c6821d1c 1040 }
1041 break;
1042
1043 case CCT2mode:
1044 switch (GET_CODE (code))
1045 {
1046 case EQ: return CC2;
1047 case NE: return CC0 | CC1 | CC3;
80b53886 1048 default: return -1;
c6821d1c 1049 }
1050 break;
1051
1052 case CCT3mode:
1053 switch (GET_CODE (code))
1054 {
1055 case EQ: return CC3;
1056 case NE: return CC0 | CC1 | CC2;
80b53886 1057 default: return -1;
c6821d1c 1058 }
1059 break;
1060
2eb8fe23 1061 case CCLmode:
1062 switch (GET_CODE (code))
1063 {
1064 case EQ: return CC0 | CC2;
1065 case NE: return CC1 | CC3;
80b53886 1066 default: return -1;
c6821d1c 1067 }
1068 break;
1069
1070 case CCL1mode:
1071 switch (GET_CODE (code))
1072 {
1073 case LTU: return CC2 | CC3; /* carry */
1074 case GEU: return CC0 | CC1; /* no carry */
80b53886 1075 default: return -1;
c6821d1c 1076 }
1077 break;
1078
1079 case CCL2mode:
1080 switch (GET_CODE (code))
1081 {
1082 case GTU: return CC0 | CC1; /* borrow */
1083 case LEU: return CC2 | CC3; /* no borrow */
80b53886 1084 default: return -1;
2eb8fe23 1085 }
1086 break;
1087
3b699fc7 1088 case CCL3mode:
1089 switch (GET_CODE (code))
1090 {
1091 case EQ: return CC0 | CC2;
1092 case NE: return CC1 | CC3;
1093 case LTU: return CC1;
1094 case GTU: return CC3;
1095 case LEU: return CC1 | CC2;
1096 case GEU: return CC2 | CC3;
80b53886 1097 default: return -1;
3b699fc7 1098 }
1099
2eb8fe23 1100 case CCUmode:
1101 switch (GET_CODE (code))
1102 {
1103 case EQ: return CC0;
1104 case NE: return CC1 | CC2 | CC3;
1105 case LTU: return CC1;
1106 case GTU: return CC2;
1107 case LEU: return CC0 | CC1;
1108 case GEU: return CC0 | CC2;
80b53886 1109 default: return -1;
2eb8fe23 1110 }
1111 break;
1112
c6821d1c 1113 case CCURmode:
1114 switch (GET_CODE (code))
1115 {
1116 case EQ: return CC0;
1117 case NE: return CC2 | CC1 | CC3;
1118 case LTU: return CC2;
1119 case GTU: return CC1;
1120 case LEU: return CC0 | CC2;
1121 case GEU: return CC0 | CC1;
80b53886 1122 default: return -1;
c6821d1c 1123 }
1124 break;
1125
3c482144 1126 case CCAPmode:
1127 switch (GET_CODE (code))
1128 {
1129 case EQ: return CC0;
1130 case NE: return CC1 | CC2 | CC3;
1131 case LT: return CC1 | CC3;
1132 case GT: return CC2;
1133 case LE: return CC0 | CC1 | CC3;
1134 case GE: return CC0 | CC2;
80b53886 1135 default: return -1;
3c482144 1136 }
1137 break;
1138
1139 case CCANmode:
1140 switch (GET_CODE (code))
1141 {
1142 case EQ: return CC0;
1143 case NE: return CC1 | CC2 | CC3;
1144 case LT: return CC1;
1145 case GT: return CC2 | CC3;
1146 case LE: return CC0 | CC1;
1147 case GE: return CC0 | CC2 | CC3;
80b53886 1148 default: return -1;
3c482144 1149 }
1150 break;
1151
2eb8fe23 1152 case CCSmode:
1153 switch (GET_CODE (code))
1154 {
1155 case EQ: return CC0;
1156 case NE: return CC1 | CC2 | CC3;
1157 case LT: return CC1;
1158 case GT: return CC2;
1159 case LE: return CC0 | CC1;
1160 case GE: return CC0 | CC2;
1161 case UNORDERED: return CC3;
1162 case ORDERED: return CC0 | CC1 | CC2;
1163 case UNEQ: return CC0 | CC3;
1164 case UNLT: return CC1 | CC3;
1165 case UNGT: return CC2 | CC3;
1166 case UNLE: return CC0 | CC1 | CC3;
1167 case UNGE: return CC0 | CC2 | CC3;
1168 case LTGT: return CC1 | CC2;
80b53886 1169 default: return -1;
2eb8fe23 1170 }
c6821d1c 1171 break;
1172
1173 case CCSRmode:
1174 switch (GET_CODE (code))
1175 {
1176 case EQ: return CC0;
1177 case NE: return CC2 | CC1 | CC3;
1178 case LT: return CC2;
1179 case GT: return CC1;
1180 case LE: return CC0 | CC2;
1181 case GE: return CC0 | CC1;
1182 case UNORDERED: return CC3;
1183 case ORDERED: return CC0 | CC2 | CC1;
1184 case UNEQ: return CC0 | CC3;
1185 case UNLT: return CC2 | CC3;
1186 case UNGT: return CC1 | CC3;
1187 case UNLE: return CC0 | CC2 | CC3;
1188 case UNGE: return CC0 | CC1 | CC3;
1189 case LTGT: return CC2 | CC1;
80b53886 1190 default: return -1;
c6821d1c 1191 }
1192 break;
2eb8fe23 1193
5ada7a14 1194 case CCRAWmode:
1195 switch (GET_CODE (code))
1196 {
1197 case EQ:
1198 return INTVAL (XEXP (code, 1));
1199 case NE:
1200 return (INTVAL (XEXP (code, 1))) ^ 0xf;
1201 default:
1202 gcc_unreachable ();
1203 }
1204
2eb8fe23 1205 default:
80b53886 1206 return -1;
2eb8fe23 1207 }
1208}
1209
e68d6a13 1210
1211/* Return branch condition mask to implement a compare and branch
1212 specified by CODE. Return -1 for invalid comparisons. */
1213
1214int
1215s390_compare_and_branch_condition_mask (rtx code)
1216{
1217 const int CC0 = 1 << 3;
1218 const int CC1 = 1 << 2;
1219 const int CC2 = 1 << 1;
1220
1221 switch (GET_CODE (code))
1222 {
1223 case EQ:
1224 return CC0;
1225 case NE:
1226 return CC1 | CC2;
1227 case LT:
1228 case LTU:
1229 return CC1;
1230 case GT:
1231 case GTU:
1232 return CC2;
1233 case LE:
1234 case LEU:
1235 return CC0 | CC1;
1236 case GE:
1237 case GEU:
1238 return CC0 | CC2;
1239 default:
1240 gcc_unreachable ();
1241 }
1242 return -1;
1243}
1244
f81e845f 1245/* If INV is false, return assembler mnemonic string to implement
1246 a branch specified by CODE. If INV is true, return mnemonic
2eb8fe23 1247 for the corresponding inverted branch. */
1248
1249static const char *
b40da9a7 1250s390_branch_condition_mnemonic (rtx code, int inv)
2eb8fe23 1251{
e68d6a13 1252 int mask;
1253
c8834c5f 1254 static const char *const mnemonic[16] =
2eb8fe23 1255 {
1256 NULL, "o", "h", "nle",
1257 "l", "nhe", "lh", "ne",
1258 "e", "nlh", "he", "nl",
1259 "le", "nh", "no", NULL
1260 };
1261
e68d6a13 1262 if (GET_CODE (XEXP (code, 0)) == REG
1263 && REGNO (XEXP (code, 0)) == CC_REGNUM
5ada7a14 1264 && (XEXP (code, 1) == const0_rtx
1265 || (GET_MODE (XEXP (code, 0)) == CCRAWmode
1266 && CONST_INT_P (XEXP (code, 1)))))
e68d6a13 1267 mask = s390_branch_condition_mask (code);
1268 else
1269 mask = s390_compare_and_branch_condition_mask (code);
1270
80b53886 1271 gcc_assert (mask >= 0);
2eb8fe23 1272
1273 if (inv)
1274 mask ^= 15;
1275
32eda510 1276 gcc_assert (mask >= 1 && mask <= 14);
2eb8fe23 1277
1278 return mnemonic[mask];
1279}
1280
64a1078f 1281/* Return the part of op which has a value different from def.
1282 The size of the part is determined by mode.
f588eb9f 1283 Use this function only if you already know that op really
64a1078f 1284 contains such a part. */
8b4a4127 1285
64a1078f 1286unsigned HOST_WIDE_INT
1287s390_extract_part (rtx op, enum machine_mode mode, int def)
8b4a4127 1288{
64a1078f 1289 unsigned HOST_WIDE_INT value = 0;
1290 int max_parts = HOST_BITS_PER_WIDE_INT / GET_MODE_BITSIZE (mode);
1291 int part_bits = GET_MODE_BITSIZE (mode);
0451e449 1292 unsigned HOST_WIDE_INT part_mask
1293 = ((unsigned HOST_WIDE_INT)1 << part_bits) - 1;
64a1078f 1294 int i;
f588eb9f 1295
64a1078f 1296 for (i = 0; i < max_parts; i++)
8b4a4127 1297 {
64a1078f 1298 if (i == 0)
1299 value = (unsigned HOST_WIDE_INT) INTVAL (op);
8b4a4127 1300 else
64a1078f 1301 value >>= part_bits;
f588eb9f 1302
64a1078f 1303 if ((value & part_mask) != (def & part_mask))
1304 return value & part_mask;
8b4a4127 1305 }
f588eb9f 1306
32eda510 1307 gcc_unreachable ();
8b4a4127 1308}
1309
1310/* If OP is an integer constant of mode MODE with exactly one
64a1078f 1311 part of mode PART_MODE unequal to DEF, return the number of that
1312 part. Otherwise, return -1. */
8b4a4127 1313
1314int
f588eb9f 1315s390_single_part (rtx op,
1316 enum machine_mode mode,
64a1078f 1317 enum machine_mode part_mode,
1318 int def)
1319{
1320 unsigned HOST_WIDE_INT value = 0;
1321 int n_parts = GET_MODE_SIZE (mode) / GET_MODE_SIZE (part_mode);
0451e449 1322 unsigned HOST_WIDE_INT part_mask
1323 = ((unsigned HOST_WIDE_INT)1 << GET_MODE_BITSIZE (part_mode)) - 1;
64a1078f 1324 int i, part = -1;
1325
1326 if (GET_CODE (op) != CONST_INT)
1327 return -1;
f588eb9f 1328
64a1078f 1329 for (i = 0; i < n_parts; i++)
1330 {
1331 if (i == 0)
1332 value = (unsigned HOST_WIDE_INT) INTVAL (op);
8b4a4127 1333 else
64a1078f 1334 value >>= GET_MODE_BITSIZE (part_mode);
f588eb9f 1335
64a1078f 1336 if ((value & part_mask) != (def & part_mask))
1337 {
1338 if (part != -1)
1339 return -1;
1340 else
1341 part = i;
1342 }
8b4a4127 1343 }
64a1078f 1344 return part == -1 ? -1 : n_parts - 1 - part;
8b4a4127 1345}
1346
e68d6a13 1347/* Return true if IN contains a contiguous bitfield in the lower SIZE
1348 bits and no other bits are set in IN. POS and LENGTH can be used
1349 to obtain the start position and the length of the bitfield.
1350
1351 POS gives the position of the first bit of the bitfield counting
1352 from the lowest order bit starting with zero. In order to use this
1353 value for S/390 instructions this has to be converted to "bits big
1354 endian" style. */
1355
1356bool
1357s390_contiguous_bitmask_p (unsigned HOST_WIDE_INT in, int size,
1358 int *pos, int *length)
1359{
1360 int tmp_pos = 0;
1361 int tmp_length = 0;
1362 int i;
1363 unsigned HOST_WIDE_INT mask = 1ULL;
1364 bool contiguous = false;
1365
1366 for (i = 0; i < size; mask <<= 1, i++)
1367 {
1368 if (contiguous)
1369 {
1370 if (mask & in)
1371 tmp_length++;
1372 else
1373 break;
1374 }
1375 else
1376 {
1377 if (mask & in)
1378 {
1379 contiguous = true;
1380 tmp_length++;
1381 }
1382 else
1383 tmp_pos++;
1384 }
1385 }
1386
1387 if (!tmp_length)
1388 return false;
1389
1390 /* Calculate a mask for all bits beyond the contiguous bits. */
1391 mask = (-1LL & ~(((1ULL << (tmp_length + tmp_pos - 1)) << 1) - 1));
1392
1393 if (mask & in)
1394 return false;
1395
1396 if (tmp_length + tmp_pos - 1 > size)
1397 return false;
1398
1399 if (length)
1400 *length = tmp_length;
1401
1402 if (pos)
1403 *pos = tmp_pos;
1404
1405 return true;
1406}
1407
6bc28655 1408/* Check whether a rotate of ROTL followed by an AND of CONTIG is
1409 equivalent to a shift followed by the AND. In particular, CONTIG
1410 should not overlap the (rotated) bit 0/bit 63 gap. Negative values
1411 for ROTL indicate a rotate to the right. */
1412
1413bool
1414s390_extzv_shift_ok (int bitsize, int rotl, unsigned HOST_WIDE_INT contig)
1415{
1416 int pos, len;
1417 bool ok;
1418
1419 ok = s390_contiguous_bitmask_p (contig, bitsize, &pos, &len);
1420 gcc_assert (ok);
1421
1422 return ((rotl >= 0 && rotl <= pos)
1423 || (rotl < 0 && -rotl <= bitsize - len - pos));
1424}
1425
f81e845f 1426/* Check whether we can (and want to) split a double-word
1427 move in mode MODE from SRC to DST into two single-word
66795431 1428 moves, moving the subword FIRST_SUBWORD first. */
1429
1430bool
b40da9a7 1431s390_split_ok_p (rtx dst, rtx src, enum machine_mode mode, int first_subword)
66795431 1432{
1433 /* Floating point registers cannot be split. */
1434 if (FP_REG_P (src) || FP_REG_P (dst))
1435 return false;
1436
1fc184ee 1437 /* We don't need to split if operands are directly accessible. */
66795431 1438 if (s_operand (src, mode) || s_operand (dst, mode))
1439 return false;
1440
1441 /* Non-offsettable memory references cannot be split. */
1442 if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
1443 || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
1444 return false;
1445
1446 /* Moving the first subword must not clobber a register
1447 needed to move the second subword. */
1448 if (register_operand (dst, mode))
1449 {
1450 rtx subreg = operand_subword (dst, first_subword, 0, mode);
1451 if (reg_overlap_mentioned_p (subreg, src))
1452 return false;
1453 }
1454
1455 return true;
1456}
1457
74bdf297 1458/* Return true if it can be proven that [MEM1, MEM1 + SIZE]
1459 and [MEM2, MEM2 + SIZE] do overlap and false
1460 otherwise. */
1461
1462bool
1463s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
1464{
1465 rtx addr1, addr2, addr_delta;
1466 HOST_WIDE_INT delta;
1467
1468 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1469 return true;
1470
1471 if (size == 0)
1472 return false;
1473
1474 addr1 = XEXP (mem1, 0);
1475 addr2 = XEXP (mem2, 0);
1476
1477 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1478
1479 /* This overlapping check is used by peepholes merging memory block operations.
1480 Overlapping operations would otherwise be recognized by the S/390 hardware
ffead1ca 1481 and would fall back to a slower implementation. Allowing overlapping
74bdf297 1482 operations would lead to slow code but not to wrong code. Therefore we are
ffead1ca 1483 somewhat optimistic if we cannot prove that the memory blocks are
74bdf297 1484 overlapping.
1485 That's why we return false here although this may accept operations on
1486 overlapping memory areas. */
1487 if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
1488 return false;
1489
1490 delta = INTVAL (addr_delta);
1491
1492 if (delta == 0
1493 || (delta > 0 && delta < size)
1494 || (delta < 0 && -delta < size))
1495 return true;
1496
1497 return false;
1498}
1499
9dffd3ff 1500/* Check whether the address of memory reference MEM2 equals exactly
1501 the address of memory reference MEM1 plus DELTA. Return true if
1502 we can prove this to be the case, false otherwise. */
1503
1504bool
1505s390_offset_p (rtx mem1, rtx mem2, rtx delta)
1506{
1507 rtx addr1, addr2, addr_delta;
1508
1509 if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
1510 return false;
1511
1512 addr1 = XEXP (mem1, 0);
1513 addr2 = XEXP (mem2, 0);
1514
1515 addr_delta = simplify_binary_operation (MINUS, Pmode, addr2, addr1);
1516 if (!addr_delta || !rtx_equal_p (addr_delta, delta))
1517 return false;
1518
1519 return true;
1520}
1521
3e247a31 1522/* Expand logical operator CODE in mode MODE with operands OPERANDS. */
1523
1524void
1525s390_expand_logical_operator (enum rtx_code code, enum machine_mode mode,
1526 rtx *operands)
1527{
1528 enum machine_mode wmode = mode;
1529 rtx dst = operands[0];
1530 rtx src1 = operands[1];
1531 rtx src2 = operands[2];
1532 rtx op, clob, tem;
1533
1534 /* If we cannot handle the operation directly, use a temp register. */
1535 if (!s390_logical_operator_ok_p (operands))
1536 dst = gen_reg_rtx (mode);
1537
1538 /* QImode and HImode patterns make sense only if we have a destination
1539 in memory. Otherwise perform the operation in SImode. */
1540 if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
1541 wmode = SImode;
1542
1543 /* Widen operands if required. */
1544 if (mode != wmode)
1545 {
1546 if (GET_CODE (dst) == SUBREG
1547 && (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
1548 dst = tem;
1549 else if (REG_P (dst))
1550 dst = gen_rtx_SUBREG (wmode, dst, 0);
1551 else
1552 dst = gen_reg_rtx (wmode);
1553
1554 if (GET_CODE (src1) == SUBREG
1555 && (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
1556 src1 = tem;
1557 else if (GET_MODE (src1) != VOIDmode)
1558 src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
1559
1560 if (GET_CODE (src2) == SUBREG
1561 && (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
1562 src2 = tem;
1563 else if (GET_MODE (src2) != VOIDmode)
1564 src2 = gen_rtx_SUBREG (wmode, force_reg (mode, src2), 0);
1565 }
1566
1567 /* Emit the instruction. */
1568 op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, wmode, src1, src2));
1569 clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
1570 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clob)));
1571
1572 /* Fix up the destination if needed. */
1573 if (dst != operands[0])
1574 emit_move_insn (operands[0], gen_lowpart (mode, dst));
1575}
1576
1577/* Check whether OPERANDS are OK for a logical operation (AND, IOR, XOR). */
1578
1579bool
1580s390_logical_operator_ok_p (rtx *operands)
1581{
1582 /* If the destination operand is in memory, it needs to coincide
1583 with one of the source operands. After reload, it has to be
1584 the first source operand. */
1585 if (GET_CODE (operands[0]) == MEM)
1586 return rtx_equal_p (operands[0], operands[1])
1587 || (!reload_completed && rtx_equal_p (operands[0], operands[2]));
1588
1589 return true;
1590}
1591
3f56e755 1592/* Narrow logical operation CODE of memory operand MEMOP with immediate
1593 operand IMMOP to switch from SS to SI type instructions. */
1594
1595void
1596s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
1597{
1598 int def = code == AND ? -1 : 0;
1599 HOST_WIDE_INT mask;
1600 int part;
1601
1602 gcc_assert (GET_CODE (*memop) == MEM);
1603 gcc_assert (!MEM_VOLATILE_P (*memop));
1604
1605 mask = s390_extract_part (*immop, QImode, def);
1606 part = s390_single_part (*immop, GET_MODE (*memop), QImode, def);
1607 gcc_assert (part >= 0);
1608
1609 *memop = adjust_address (*memop, QImode, part);
1610 *immop = gen_int_mode (mask, QImode);
1611}
1612
2eb8fe23 1613
875862bf 1614/* How to allocate a 'struct machine_function'. */
1615
1616static struct machine_function *
1617s390_init_machine_status (void)
1618{
ba72912a 1619 return ggc_alloc_cleared_machine_function ();
875862bf 1620}
1621
4c834714 1622static void
1623s390_option_override (void)
28ee8079 1624{
5a5e802f 1625 /* Set up function hooks. */
1626 init_machine_status = s390_init_machine_status;
b8c0043c 1627
1628 /* Architecture mode defaults according to ABI. */
1629 if (!(target_flags_explicit & MASK_ZARCH))
1630 {
1631 if (TARGET_64BIT)
1632 target_flags |= MASK_ZARCH;
1633 else
1634 target_flags &= ~MASK_ZARCH;
1635 }
1636
7fe62d25 1637 /* Set the march default in case it hasn't been specified on
1638 cmdline. */
1639 if (s390_arch == PROCESSOR_max)
28ee8079 1640 {
1641 s390_arch_string = TARGET_ZARCH? "z900" : "g5";
7fe62d25 1642 s390_arch = TARGET_ZARCH ? PROCESSOR_2064_Z900 : PROCESSOR_9672_G5;
1643 s390_arch_flags = processor_flags_table[(int)s390_arch];
28ee8079 1644 }
95ae2fd6 1645
b8c0043c 1646 /* Determine processor to tune for. */
28ee8079 1647 if (s390_tune == PROCESSOR_max)
95ae2fd6 1648 {
b8c0043c 1649 s390_tune = s390_arch;
1650 s390_tune_flags = s390_arch_flags;
95ae2fd6 1651 }
1652
b8c0043c 1653 /* Sanity checks. */
7818a08e 1654 if (TARGET_ZARCH && !TARGET_CPU_ZARCH)
3284a242 1655 error ("z/Architecture mode not supported on %s", s390_arch_string);
b8c0043c 1656 if (TARGET_64BIT && !TARGET_ZARCH)
3284a242 1657 error ("64-bit ABI not supported in ESA/390 mode");
cbb300e8 1658
dcba5e45 1659 /* Use hardware DFP if available and not explicitly disabled by
1660 user. E.g. with -m31 -march=z10 -mzarch */
1661 if (!(target_flags_explicit & MASK_HARD_DFP) && TARGET_DFP)
1662 target_flags |= MASK_HARD_DFP;
1663
5ada7a14 1664 /* Enable hardware transactions if available and not explicitly
1665 disabled by user. E.g. with -m31 -march=zEC12 -mzarch */
1666 if (!(target_flags_explicit & MASK_OPT_HTM) && TARGET_CPU_HTM && TARGET_ZARCH)
1667 target_flags |= MASK_OPT_HTM;
1668
b44d7d37 1669 if (TARGET_HARD_DFP && !TARGET_DFP)
7818a08e 1670 {
b44d7d37 1671 if (target_flags_explicit & MASK_HARD_DFP)
7818a08e 1672 {
1673 if (!TARGET_CPU_DFP)
bf776685 1674 error ("hardware decimal floating point instructions"
7818a08e 1675 " not available on %s", s390_arch_string);
1676 if (!TARGET_ZARCH)
bf776685 1677 error ("hardware decimal floating point instructions"
7818a08e 1678 " not available in ESA/390 mode");
1679 }
1680 else
b44d7d37 1681 target_flags &= ~MASK_HARD_DFP;
7818a08e 1682 }
1683
1684 if ((target_flags_explicit & MASK_SOFT_FLOAT) && TARGET_SOFT_FLOAT)
1685 {
b44d7d37 1686 if ((target_flags_explicit & MASK_HARD_DFP) && TARGET_HARD_DFP)
bf776685 1687 error ("-mhard-dfp can%'t be used in conjunction with -msoft-float");
7818a08e 1688
b44d7d37 1689 target_flags &= ~MASK_HARD_DFP;
7818a08e 1690 }
1691
18925d38 1692 /* Set processor cost function. */
a850370e 1693 switch (s390_tune)
1694 {
1695 case PROCESSOR_2084_Z990:
1696 s390_cost = &z990_cost;
1697 break;
1698 case PROCESSOR_2094_Z9_109:
1699 s390_cost = &z9_109_cost;
1700 break;
1701 case PROCESSOR_2097_Z10:
1702 s390_cost = &z10_cost;
c22c2d09 1703 break;
33d033da 1704 case PROCESSOR_2817_Z196:
1705 s390_cost = &z196_cost;
a850370e 1706 break;
81769881 1707 case PROCESSOR_2827_ZEC12:
1708 s390_cost = &zEC12_cost;
1709 break;
a850370e 1710 default:
1711 s390_cost = &z900_cost;
1712 }
1713
5724df29 1714 if (TARGET_BACKCHAIN && TARGET_PACKED_STACK && TARGET_HARD_FLOAT)
1715 error ("-mbackchain -mpacked-stack -mhard-float are not supported "
3284a242 1716 "in combination");
5724df29 1717
28ee8079 1718 if (s390_stack_size)
cbb300e8 1719 {
00d233e6 1720 if (s390_stack_guard >= s390_stack_size)
28ee8079 1721 error ("stack size must be greater than the stack guard value");
a4e6ef04 1722 else if (s390_stack_size > 1 << 16)
1723 error ("stack size must not be greater than 64k");
cbb300e8 1724 }
28ee8079 1725 else if (s390_stack_guard)
ffead1ca 1726 error ("-mstack-guard implies use of -mstack-size");
2dde0cc6 1727
1728#ifdef TARGET_DEFAULT_LONG_DOUBLE_128
1729 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128))
1730 target_flags |= MASK_LONG_DOUBLE_128;
1731#endif
c0717306 1732
33d033da 1733 if (s390_tune == PROCESSOR_2097_Z10
81769881 1734 || s390_tune == PROCESSOR_2817_Z196
1735 || s390_tune == PROCESSOR_2827_ZEC12)
a52ee362 1736 {
56f280c4 1737 maybe_set_param_value (PARAM_MAX_UNROLLED_INSNS, 100,
1738 global_options.x_param_values,
1739 global_options_set.x_param_values);
1740 maybe_set_param_value (PARAM_MAX_UNROLL_TIMES, 32,
1741 global_options.x_param_values,
1742 global_options_set.x_param_values);
1743 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEELED_INSNS, 2000,
1744 global_options.x_param_values,
1745 global_options_set.x_param_values);
1746 maybe_set_param_value (PARAM_MAX_COMPLETELY_PEEL_TIMES, 64,
1747 global_options.x_param_values,
1748 global_options_set.x_param_values);
a52ee362 1749 }
8aca5068 1750
56f280c4 1751 maybe_set_param_value (PARAM_MAX_PENDING_LIST_LENGTH, 256,
1752 global_options.x_param_values,
1753 global_options_set.x_param_values);
d80deb0a 1754 /* values for loop prefetching */
56f280c4 1755 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 256,
1756 global_options.x_param_values,
1757 global_options_set.x_param_values);
1758 maybe_set_param_value (PARAM_L1_CACHE_SIZE, 128,
1759 global_options.x_param_values,
1760 global_options_set.x_param_values);
d80deb0a 1761 /* s390 has more than 2 levels and the size is much larger. Since
1762 we are always running virtualized assume that we only get a small
1763 part of the caches above l1. */
56f280c4 1764 maybe_set_param_value (PARAM_L2_CACHE_SIZE, 1500,
1765 global_options.x_param_values,
1766 global_options_set.x_param_values);
1767 maybe_set_param_value (PARAM_PREFETCH_MIN_INSN_TO_MEM_RATIO, 2,
1768 global_options.x_param_values,
1769 global_options_set.x_param_values);
1770 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 6,
1771 global_options.x_param_values,
1772 global_options_set.x_param_values);
f0b78aef 1773
c17f64cc 1774 /* This cannot reside in s390_option_optimization_table since HAVE_prefetch
7b132fab 1775 requires the arch flags to be evaluated already. Since prefetching
1776 is beneficial on s390, we enable it if available. */
1777 if (flag_prefetch_loop_arrays < 0 && HAVE_prefetch && optimize >= 3)
f0b78aef 1778 flag_prefetch_loop_arrays = 1;
d86dbf92 1779
1780 /* Use the alternative scheduling-pressure algorithm by default. */
1781 maybe_set_param_value (PARAM_SCHED_PRESSURE_ALGORITHM, 2,
1782 global_options.x_param_values,
1783 global_options_set.x_param_values);
fd1df2e7 1784
1785 if (TARGET_TPF)
1786 {
1787 /* Don't emit DWARF3/4 unless specifically selected. The TPF
1788 debuggers do not yet support DWARF 3/4. */
1789 if (!global_options_set.x_dwarf_strict)
1790 dwarf_strict = 1;
1791 if (!global_options_set.x_dwarf_version)
1792 dwarf_version = 2;
1793 }
5a5e802f 1794}
4673c1a0 1795
1796/* Map for smallest class containing reg regno. */
1797
c8834c5f 1798const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] =
4673c1a0 1799{ GENERAL_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1800 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1801 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1802 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
1803 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1804 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1805 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
1806 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
923cf36d 1807 ADDR_REGS, CC_REGS, ADDR_REGS, ADDR_REGS,
1808 ACCESS_REGS, ACCESS_REGS
4673c1a0 1809};
1810
71343e6b 1811/* Return attribute type of insn. */
1812
1813static enum attr_type
b40da9a7 1814s390_safe_attr_type (rtx insn)
71343e6b 1815{
1816 if (recog_memoized (insn) >= 0)
1817 return get_attr_type (insn);
1818 else
1819 return TYPE_NONE;
1820}
4673c1a0 1821
51aa1e9c 1822/* Return true if DISP is a valid short displacement. */
1823
e5537457 1824static bool
b40da9a7 1825s390_short_displacement (rtx disp)
51aa1e9c 1826{
1827 /* No displacement is OK. */
1828 if (!disp)
e5537457 1829 return true;
51aa1e9c 1830
a7b49046 1831 /* Without the long displacement facility we don't need to
1832 distingiush between long and short displacement. */
1833 if (!TARGET_LONG_DISPLACEMENT)
1834 return true;
1835
51aa1e9c 1836 /* Integer displacement in range. */
1837 if (GET_CODE (disp) == CONST_INT)
1838 return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
1839
1840 /* GOT offset is not OK, the GOT can be large. */
1841 if (GET_CODE (disp) == CONST
1842 && GET_CODE (XEXP (disp, 0)) == UNSPEC
a6e4e903 1843 && (XINT (XEXP (disp, 0), 1) == UNSPEC_GOT
1844 || XINT (XEXP (disp, 0), 1) == UNSPEC_GOTNTPOFF))
e5537457 1845 return false;
51aa1e9c 1846
1847 /* All other symbolic constants are literal pool references,
1848 which are OK as the literal pool must be small. */
1849 if (GET_CODE (disp) == CONST)
e5537457 1850 return true;
51aa1e9c 1851
e5537457 1852 return false;
51aa1e9c 1853}
1854
875862bf 1855/* Decompose a RTL expression ADDR for a memory address into
1856 its components, returned in OUT.
a5004c3d 1857
e5537457 1858 Returns false if ADDR is not a valid memory address, true
875862bf 1859 otherwise. If OUT is NULL, don't return the components,
1860 but check for validity only.
a5004c3d 1861
875862bf 1862 Note: Only addresses in canonical form are recognized.
1863 LEGITIMIZE_ADDRESS should convert non-canonical forms to the
1864 canonical form so that they will be recognized. */
64a1078f 1865
875862bf 1866static int
edd89d66 1867s390_decompose_address (rtx addr, struct s390_address *out)
875862bf 1868{
1869 HOST_WIDE_INT offset = 0;
1870 rtx base = NULL_RTX;
1871 rtx indx = NULL_RTX;
1872 rtx disp = NULL_RTX;
1873 rtx orig_disp;
e5537457 1874 bool pointer = false;
1875 bool base_ptr = false;
1876 bool indx_ptr = false;
05b58257 1877 bool literal_pool = false;
1878
1879 /* We may need to substitute the literal pool base register into the address
1880 below. However, at this point we do not know which register is going to
1881 be used as base, so we substitute the arg pointer register. This is going
1882 to be treated as holding a pointer below -- it shouldn't be used for any
1883 other purpose. */
1884 rtx fake_pool_base = gen_rtx_REG (Pmode, ARG_POINTER_REGNUM);
3f56e755 1885
875862bf 1886 /* Decompose address into base + index + displacement. */
3f56e755 1887
875862bf 1888 if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
1889 base = addr;
3f56e755 1890
875862bf 1891 else if (GET_CODE (addr) == PLUS)
6b1c8423 1892 {
875862bf 1893 rtx op0 = XEXP (addr, 0);
1894 rtx op1 = XEXP (addr, 1);
1895 enum rtx_code code0 = GET_CODE (op0);
1896 enum rtx_code code1 = GET_CODE (op1);
6b1c8423 1897
875862bf 1898 if (code0 == REG || code0 == UNSPEC)
1899 {
1900 if (code1 == REG || code1 == UNSPEC)
1901 {
1902 indx = op0; /* index + base */
1903 base = op1;
1904 }
6b1c8423 1905
875862bf 1906 else
1907 {
1908 base = op0; /* base + displacement */
1909 disp = op1;
1910 }
1911 }
a5004c3d 1912
875862bf 1913 else if (code0 == PLUS)
51aa1e9c 1914 {
875862bf 1915 indx = XEXP (op0, 0); /* index + base + disp */
1916 base = XEXP (op0, 1);
1917 disp = op1;
51aa1e9c 1918 }
51aa1e9c 1919
875862bf 1920 else
51aa1e9c 1921 {
e5537457 1922 return false;
51aa1e9c 1923 }
875862bf 1924 }
51aa1e9c 1925
875862bf 1926 else
1927 disp = addr; /* displacement */
51aa1e9c 1928
875862bf 1929 /* Extract integer part of displacement. */
1930 orig_disp = disp;
1931 if (disp)
1932 {
1933 if (GET_CODE (disp) == CONST_INT)
51aa1e9c 1934 {
875862bf 1935 offset = INTVAL (disp);
1936 disp = NULL_RTX;
51aa1e9c 1937 }
875862bf 1938 else if (GET_CODE (disp) == CONST
1939 && GET_CODE (XEXP (disp, 0)) == PLUS
1940 && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
1941 {
1942 offset = INTVAL (XEXP (XEXP (disp, 0), 1));
1943 disp = XEXP (XEXP (disp, 0), 0);
1944 }
1945 }
51aa1e9c 1946
875862bf 1947 /* Strip off CONST here to avoid special case tests later. */
1948 if (disp && GET_CODE (disp) == CONST)
1949 disp = XEXP (disp, 0);
63ebd742 1950
875862bf 1951 /* We can convert literal pool addresses to
1952 displacements by basing them off the base register. */
1953 if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
1954 {
1955 /* Either base or index must be free to hold the base register. */
1956 if (!base)
05b58257 1957 base = fake_pool_base, literal_pool = true;
875862bf 1958 else if (!indx)
05b58257 1959 indx = fake_pool_base, literal_pool = true;
875862bf 1960 else
e5537457 1961 return false;
875862bf 1962
1963 /* Mark up the displacement. */
1964 disp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, disp),
1965 UNSPEC_LTREL_OFFSET);
51aa1e9c 1966 }
a5004c3d 1967
875862bf 1968 /* Validate base register. */
1969 if (base)
1970 {
1971 if (GET_CODE (base) == UNSPEC)
1972 switch (XINT (base, 1))
1973 {
1974 case UNSPEC_LTREF:
1975 if (!disp)
ffead1ca 1976 disp = gen_rtx_UNSPEC (Pmode,
875862bf 1977 gen_rtvec (1, XVECEXP (base, 0, 0)),
1978 UNSPEC_LTREL_OFFSET);
1979 else
e5537457 1980 return false;
a5004c3d 1981
05b58257 1982 base = XVECEXP (base, 0, 1);
875862bf 1983 break;
64a1078f 1984
875862bf 1985 case UNSPEC_LTREL_BASE:
05b58257 1986 if (XVECLEN (base, 0) == 1)
1987 base = fake_pool_base, literal_pool = true;
1988 else
1989 base = XVECEXP (base, 0, 1);
875862bf 1990 break;
64a1078f 1991
875862bf 1992 default:
e5537457 1993 return false;
875862bf 1994 }
64a1078f 1995
ffead1ca 1996 if (!REG_P (base)
1997 || (GET_MODE (base) != SImode
1e280623 1998 && GET_MODE (base) != Pmode))
e5537457 1999 return false;
875862bf 2000
05b58257 2001 if (REGNO (base) == STACK_POINTER_REGNUM
875862bf 2002 || REGNO (base) == FRAME_POINTER_REGNUM
2003 || ((reload_completed || reload_in_progress)
2004 && frame_pointer_needed
2005 && REGNO (base) == HARD_FRAME_POINTER_REGNUM)
2006 || REGNO (base) == ARG_POINTER_REGNUM
2007 || (flag_pic
2008 && REGNO (base) == PIC_OFFSET_TABLE_REGNUM))
e5537457 2009 pointer = base_ptr = true;
05b58257 2010
2011 if ((reload_completed || reload_in_progress)
2012 && base == cfun->machine->base_reg)
2013 pointer = base_ptr = literal_pool = true;
875862bf 2014 }
2015
2016 /* Validate index register. */
2017 if (indx)
64a1078f 2018 {
875862bf 2019 if (GET_CODE (indx) == UNSPEC)
2020 switch (XINT (indx, 1))
2021 {
2022 case UNSPEC_LTREF:
2023 if (!disp)
ffead1ca 2024 disp = gen_rtx_UNSPEC (Pmode,
875862bf 2025 gen_rtvec (1, XVECEXP (indx, 0, 0)),
2026 UNSPEC_LTREL_OFFSET);
2027 else
e5537457 2028 return false;
64a1078f 2029
05b58257 2030 indx = XVECEXP (indx, 0, 1);
875862bf 2031 break;
64a1078f 2032
875862bf 2033 case UNSPEC_LTREL_BASE:
05b58257 2034 if (XVECLEN (indx, 0) == 1)
2035 indx = fake_pool_base, literal_pool = true;
2036 else
2037 indx = XVECEXP (indx, 0, 1);
875862bf 2038 break;
64a1078f 2039
875862bf 2040 default:
e5537457 2041 return false;
875862bf 2042 }
64a1078f 2043
ffead1ca 2044 if (!REG_P (indx)
1e280623 2045 || (GET_MODE (indx) != SImode
2046 && GET_MODE (indx) != Pmode))
e5537457 2047 return false;
64a1078f 2048
05b58257 2049 if (REGNO (indx) == STACK_POINTER_REGNUM
875862bf 2050 || REGNO (indx) == FRAME_POINTER_REGNUM
2051 || ((reload_completed || reload_in_progress)
2052 && frame_pointer_needed
2053 && REGNO (indx) == HARD_FRAME_POINTER_REGNUM)
2054 || REGNO (indx) == ARG_POINTER_REGNUM
2055 || (flag_pic
2056 && REGNO (indx) == PIC_OFFSET_TABLE_REGNUM))
e5537457 2057 pointer = indx_ptr = true;
05b58257 2058
2059 if ((reload_completed || reload_in_progress)
2060 && indx == cfun->machine->base_reg)
2061 pointer = indx_ptr = literal_pool = true;
875862bf 2062 }
f588eb9f 2063
875862bf 2064 /* Prefer to use pointer as base, not index. */
2065 if (base && indx && !base_ptr
2066 && (indx_ptr || (!REG_POINTER (base) && REG_POINTER (indx))))
2067 {
2068 rtx tmp = base;
2069 base = indx;
2070 indx = tmp;
2071 }
64a1078f 2072
875862bf 2073 /* Validate displacement. */
2074 if (!disp)
2075 {
ffead1ca 2076 /* If virtual registers are involved, the displacement will change later
2077 anyway as the virtual registers get eliminated. This could make a
2078 valid displacement invalid, but it is more likely to make an invalid
2079 displacement valid, because we sometimes access the register save area
119114cb 2080 via negative offsets to one of those registers.
875862bf 2081 Thus we don't check the displacement for validity here. If after
2082 elimination the displacement turns out to be invalid after all,
2083 this is fixed up by reload in any case. */
7b1bda1c 2084 /* LRA maintains always displacements up to date and we need to
2085 know the displacement is right during all LRA not only at the
2086 final elimination. */
2087 if (lra_in_progress
2088 || (base != arg_pointer_rtx
2089 && indx != arg_pointer_rtx
2090 && base != return_address_pointer_rtx
2091 && indx != return_address_pointer_rtx
2092 && base != frame_pointer_rtx
2093 && indx != frame_pointer_rtx
2094 && base != virtual_stack_vars_rtx
2095 && indx != virtual_stack_vars_rtx))
875862bf 2096 if (!DISP_IN_RANGE (offset))
e5537457 2097 return false;
875862bf 2098 }
2099 else
2100 {
2101 /* All the special cases are pointers. */
e5537457 2102 pointer = true;
64a1078f 2103
875862bf 2104 /* In the small-PIC case, the linker converts @GOT
2105 and @GOTNTPOFF offsets to possible displacements. */
2106 if (GET_CODE (disp) == UNSPEC
2107 && (XINT (disp, 1) == UNSPEC_GOT
2108 || XINT (disp, 1) == UNSPEC_GOTNTPOFF)
875862bf 2109 && flag_pic == 1)
2110 {
2111 ;
2112 }
64a1078f 2113
1ed7a160 2114 /* Accept pool label offsets. */
2115 else if (GET_CODE (disp) == UNSPEC
2116 && XINT (disp, 1) == UNSPEC_POOL_OFFSET)
2117 ;
64a1078f 2118
875862bf 2119 /* Accept literal pool references. */
2120 else if (GET_CODE (disp) == UNSPEC
2121 && XINT (disp, 1) == UNSPEC_LTREL_OFFSET)
2122 {
cf8ffe7d 2123 /* In case CSE pulled a non literal pool reference out of
2124 the pool we have to reject the address. This is
2125 especially important when loading the GOT pointer on non
2126 zarch CPUs. In this case the literal pool contains an lt
2127 relative offset to the _GLOBAL_OFFSET_TABLE_ label which
2128 will most likely exceed the displacement. */
2129 if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
2130 || !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp, 0, 0)))
2131 return false;
2132
875862bf 2133 orig_disp = gen_rtx_CONST (Pmode, disp);
2134 if (offset)
2135 {
2136 /* If we have an offset, make sure it does not
2137 exceed the size of the constant pool entry. */
2138 rtx sym = XVECEXP (disp, 0, 0);
2139 if (offset >= GET_MODE_SIZE (get_pool_mode (sym)))
e5537457 2140 return false;
64a1078f 2141
29c05e22 2142 orig_disp = plus_constant (Pmode, orig_disp, offset);
875862bf 2143 }
2144 }
2145
2146 else
e5537457 2147 return false;
64a1078f 2148 }
2149
875862bf 2150 if (!base && !indx)
e5537457 2151 pointer = true;
875862bf 2152
2153 if (out)
2154 {
2155 out->base = base;
2156 out->indx = indx;
2157 out->disp = orig_disp;
2158 out->pointer = pointer;
05b58257 2159 out->literal_pool = literal_pool;
875862bf 2160 }
2161
e5537457 2162 return true;
64a1078f 2163}
2164
6d6be381 2165/* Decompose a RTL expression OP for a shift count into its components,
2166 and return the base register in BASE and the offset in OFFSET.
2167
6d6be381 2168 Return true if OP is a valid shift count, false if not. */
2169
2170bool
417cba42 2171s390_decompose_shift_count (rtx op, rtx *base, HOST_WIDE_INT *offset)
6d6be381 2172{
2173 HOST_WIDE_INT off = 0;
2174
6d6be381 2175 /* We can have an integer constant, an address register,
2176 or a sum of the two. */
2177 if (GET_CODE (op) == CONST_INT)
2178 {
2179 off = INTVAL (op);
2180 op = NULL_RTX;
2181 }
2182 if (op && GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
2183 {
2184 off = INTVAL (XEXP (op, 1));
2185 op = XEXP (op, 0);
2186 }
2187 while (op && GET_CODE (op) == SUBREG)
2188 op = SUBREG_REG (op);
2189
2190 if (op && GET_CODE (op) != REG)
2191 return false;
2192
2193 if (offset)
2194 *offset = off;
2195 if (base)
2196 *base = op;
2197
2198 return true;
2199}
2200
2201
875862bf 2202/* Return true if CODE is a valid address without index. */
fab7adbf 2203
875862bf 2204bool
2205s390_legitimate_address_without_index_p (rtx op)
2206{
2207 struct s390_address addr;
2208
2209 if (!s390_decompose_address (XEXP (op, 0), &addr))
2210 return false;
2211 if (addr.indx)
2212 return false;
2213
2214 return true;
2215}
2216
59bc01b3 2217
2a672556 2218/* Return TRUE if ADDR is an operand valid for a load/store relative
2219 instruction. Be aware that the alignment of the operand needs to
2220 be checked separately.
2221 Valid addresses are single references or a sum of a reference and a
2222 constant integer. Return these parts in SYMREF and ADDEND. You can
2223 pass NULL in REF and/or ADDEND if you are not interested in these
2224 values. Literal pool references are *not* considered symbol
2225 references. */
875862bf 2226
a7b49046 2227static bool
2a672556 2228s390_loadrelative_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
875862bf 2229{
a7b49046 2230 HOST_WIDE_INT tmpaddend = 0;
875862bf 2231
a7b49046 2232 if (GET_CODE (addr) == CONST)
2233 addr = XEXP (addr, 0);
2234
2235 if (GET_CODE (addr) == PLUS)
875862bf 2236 {
2a672556 2237 if (!CONST_INT_P (XEXP (addr, 1)))
a7b49046 2238 return false;
875862bf 2239
2a672556 2240 tmpaddend = INTVAL (XEXP (addr, 1));
2241 addr = XEXP (addr, 0);
2242 }
62cb5855 2243
2a672556 2244 if ((GET_CODE (addr) == SYMBOL_REF && !CONSTANT_POOL_ADDRESS_P (addr))
2245 || (GET_CODE (addr) == UNSPEC
2246 && (XINT (addr, 1) == UNSPEC_GOTENT
2247 || (TARGET_CPU_ZARCH && XINT (addr, 1) == UNSPEC_PLT))))
2248 {
2249 if (symref)
2250 *symref = addr;
2251 if (addend)
2252 *addend = tmpaddend;
62cb5855 2253
2a672556 2254 return true;
2255 }
2256 return false;
62cb5855 2257}
a7b49046 2258
2259/* Return true if the address in OP is valid for constraint letter C
2260 if wrapped in a MEM rtx. Set LIT_POOL_OK to true if it literal
2261 pool MEMs should be accepted. Only the Q, R, S, T constraint
2262 letters are allowed for C. */
875862bf 2263
a7b49046 2264static int
2265s390_check_qrst_address (char c, rtx op, bool lit_pool_ok)
2266{
2267 struct s390_address addr;
2268 bool decomposed = false;
2269
2270 /* This check makes sure that no symbolic address (except literal
2271 pool references) are accepted by the R or T constraints. */
2a672556 2272 if (s390_loadrelative_operand_p (op, NULL, NULL))
f3959569 2273 return 0;
2274
2275 /* Ensure literal pool references are only accepted if LIT_POOL_OK. */
2276 if (!lit_pool_ok)
875862bf 2277 {
a7b49046 2278 if (!s390_decompose_address (op, &addr))
875862bf 2279 return 0;
f3959569 2280 if (addr.literal_pool)
875862bf 2281 return 0;
a7b49046 2282 decomposed = true;
875862bf 2283 }
2284
2285 switch (c)
2286 {
a7b49046 2287 case 'Q': /* no index short displacement */
2288 if (!decomposed && !s390_decompose_address (op, &addr))
875862bf 2289 return 0;
2290 if (addr.indx)
2291 return 0;
a7b49046 2292 if (!s390_short_displacement (addr.disp))
875862bf 2293 return 0;
a7b49046 2294 break;
875862bf 2295
a7b49046 2296 case 'R': /* with index short displacement */
875862bf 2297 if (TARGET_LONG_DISPLACEMENT)
2298 {
a7b49046 2299 if (!decomposed && !s390_decompose_address (op, &addr))
875862bf 2300 return 0;
2301 if (!s390_short_displacement (addr.disp))
2302 return 0;
2303 }
a7b49046 2304 /* Any invalid address here will be fixed up by reload,
2305 so accept it for the most generic constraint. */
875862bf 2306 break;
2307
a7b49046 2308 case 'S': /* no index long displacement */
875862bf 2309 if (!TARGET_LONG_DISPLACEMENT)
2310 return 0;
a7b49046 2311 if (!decomposed && !s390_decompose_address (op, &addr))
875862bf 2312 return 0;
2313 if (addr.indx)
2314 return 0;
2315 if (s390_short_displacement (addr.disp))
2316 return 0;
2317 break;
2318
a7b49046 2319 case 'T': /* with index long displacement */
875862bf 2320 if (!TARGET_LONG_DISPLACEMENT)
2321 return 0;
a7b49046 2322 /* Any invalid address here will be fixed up by reload,
2323 so accept it for the most generic constraint. */
2324 if ((decomposed || s390_decompose_address (op, &addr))
2325 && s390_short_displacement (addr.disp))
875862bf 2326 return 0;
2327 break;
a7b49046 2328 default:
2329 return 0;
2330 }
2331 return 1;
2332}
875862bf 2333
875862bf 2334
a7b49046 2335/* Evaluates constraint strings described by the regular expression
2336 ([A|B|Z](Q|R|S|T))|U|W|Y and returns 1 if OP is a valid operand for
2337 the constraint given in STR, or 0 else. */
2338
2339int
2340s390_mem_constraint (const char *str, rtx op)
2341{
2342 char c = str[0];
2343
2344 switch (c)
2345 {
2346 case 'A':
2347 /* Check for offsettable variants of memory constraints. */
2348 if (!MEM_P (op) || MEM_VOLATILE_P (op))
875862bf 2349 return 0;
a7b49046 2350 if ((reload_completed || reload_in_progress)
2351 ? !offsettable_memref_p (op) : !offsettable_nonstrict_memref_p (op))
e68d6a13 2352 return 0;
a7b49046 2353 return s390_check_qrst_address (str[1], XEXP (op, 0), true);
2354 case 'B':
2355 /* Check for non-literal-pool variants of memory constraints. */
2356 if (!MEM_P (op))
875862bf 2357 return 0;
a7b49046 2358 return s390_check_qrst_address (str[1], XEXP (op, 0), false);
2359 case 'Q':
2360 case 'R':
2361 case 'S':
2362 case 'T':
2363 if (GET_CODE (op) != MEM)
2364 return 0;
2365 return s390_check_qrst_address (c, XEXP (op, 0), true);
2366 case 'U':
2367 return (s390_check_qrst_address ('Q', op, true)
2368 || s390_check_qrst_address ('R', op, true));
2369 case 'W':
2370 return (s390_check_qrst_address ('S', op, true)
2371 || s390_check_qrst_address ('T', op, true));
875862bf 2372 case 'Y':
6d6be381 2373 /* Simply check for the basic form of a shift count. Reload will
2374 take care of making sure we have a proper base register. */
417cba42 2375 if (!s390_decompose_shift_count (op, NULL, NULL))
6d6be381 2376 return 0;
2377 break;
a7b49046 2378 case 'Z':
2379 return s390_check_qrst_address (str[1], op, true);
875862bf 2380 default:
2381 return 0;
2382 }
875862bf 2383 return 1;
2384}
2385
59bc01b3 2386
59bc01b3 2387/* Evaluates constraint strings starting with letter O. Input
2388 parameter C is the second letter following the "O" in the constraint
2389 string. Returns 1 if VALUE meets the respective constraint and 0
2390 otherwise. */
875862bf 2391
e863b008 2392int
59bc01b3 2393s390_O_constraint_str (const char c, HOST_WIDE_INT value)
e863b008 2394{
59bc01b3 2395 if (!TARGET_EXTIMM)
2396 return 0;
e863b008 2397
59bc01b3 2398 switch (c)
e863b008 2399 {
59bc01b3 2400 case 's':
2401 return trunc_int_for_mode (value, SImode) == value;
2402
2403 case 'p':
2404 return value == 0
2405 || s390_single_part (GEN_INT (value), DImode, SImode, 0) == 1;
2406
2407 case 'n':
29847ec4 2408 return s390_single_part (GEN_INT (value - 1), DImode, SImode, -1) == 1;
59bc01b3 2409
e863b008 2410 default:
59bc01b3 2411 gcc_unreachable ();
e863b008 2412 }
2413}
2414
59bc01b3 2415
2416/* Evaluates constraint strings starting with letter N. Parameter STR
2417 contains the letters following letter "N" in the constraint string.
2418 Returns true if VALUE matches the constraint. */
e863b008 2419
875862bf 2420int
59bc01b3 2421s390_N_constraint_str (const char *str, HOST_WIDE_INT value)
875862bf 2422{
2423 enum machine_mode mode, part_mode;
2424 int def;
2425 int part, part_goal;
2426
875862bf 2427
59bc01b3 2428 if (str[0] == 'x')
2429 part_goal = -1;
2430 else
2431 part_goal = str[0] - '0';
875862bf 2432
59bc01b3 2433 switch (str[1])
2434 {
2435 case 'Q':
2436 part_mode = QImode;
875862bf 2437 break;
59bc01b3 2438 case 'H':
2439 part_mode = HImode;
163277cf 2440 break;
59bc01b3 2441 case 'S':
2442 part_mode = SImode;
2443 break;
2444 default:
2445 return 0;
2446 }
163277cf 2447
59bc01b3 2448 switch (str[2])
2449 {
2450 case 'H':
2451 mode = HImode;
2452 break;
2453 case 'S':
2454 mode = SImode;
2455 break;
2456 case 'D':
2457 mode = DImode;
2458 break;
2459 default:
2460 return 0;
2461 }
53239c89 2462
59bc01b3 2463 switch (str[3])
2464 {
2465 case '0':
2466 def = 0;
2467 break;
2468 case 'F':
2469 def = -1;
2470 break;
875862bf 2471 default:
2472 return 0;
2473 }
2474
59bc01b3 2475 if (GET_MODE_SIZE (mode) <= GET_MODE_SIZE (part_mode))
2476 return 0;
2477
2478 part = s390_single_part (GEN_INT (value), mode, part_mode, def);
2479 if (part < 0)
2480 return 0;
2481 if (part_goal != -1 && part_goal != part)
2482 return 0;
2483
875862bf 2484 return 1;
2485}
2486
59bc01b3 2487
2488/* Returns true if the input parameter VALUE is a float zero. */
2489
2490int
2491s390_float_const_zero_p (rtx value)
2492{
2493 return (GET_MODE_CLASS (GET_MODE (value)) == MODE_FLOAT
2494 && value == CONST0_RTX (GET_MODE (value)));
2495}
2496
fa7a995b 2497/* Implement TARGET_REGISTER_MOVE_COST. */
2498
2499static int
2500s390_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2501 reg_class_t from, reg_class_t to)
2502{
7af74943 2503 /* On s390, copy between fprs and gprs is expensive as long as no
2504 ldgr/lgdr can be used. */
2505 if ((!TARGET_Z10 || GET_MODE_SIZE (mode) != 8)
2506 && ((reg_classes_intersect_p (from, GENERAL_REGS)
2507 && reg_classes_intersect_p (to, FP_REGS))
2508 || (reg_classes_intersect_p (from, FP_REGS)
2509 && reg_classes_intersect_p (to, GENERAL_REGS))))
fa7a995b 2510 return 10;
2511
2512 return 1;
2513}
2514
2515/* Implement TARGET_MEMORY_MOVE_COST. */
2516
2517static int
2518s390_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
2519 reg_class_t rclass ATTRIBUTE_UNUSED,
2520 bool in ATTRIBUTE_UNUSED)
2521{
2522 return 1;
2523}
59bc01b3 2524
875862bf 2525/* Compute a (partial) cost for rtx X. Return true if the complete
2526 cost has been computed, and false if subexpressions should be
ffead1ca 2527 scanned. In either case, *TOTAL contains the cost result.
2528 CODE contains GET_CODE (x), OUTER_CODE contains the code
875862bf 2529 of the superexpression of x. */
2530
2531static bool
20d892d1 2532s390_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
2533 int *total, bool speed ATTRIBUTE_UNUSED)
fab7adbf 2534{
2535 switch (code)
2536 {
2537 case CONST:
fab7adbf 2538 case CONST_INT:
fab7adbf 2539 case LABEL_REF:
2540 case SYMBOL_REF:
2541 case CONST_DOUBLE:
3f074425 2542 case MEM:
fab7adbf 2543 *total = 0;
2544 return true;
2545
2546 case ASHIFT:
2547 case ASHIFTRT:
2548 case LSHIFTRT:
18925d38 2549 case ROTATE:
2550 case ROTATERT:
fab7adbf 2551 case AND:
2552 case IOR:
2553 case XOR:
fab7adbf 2554 case NEG:
2555 case NOT:
2556 *total = COSTS_N_INSNS (1);
18925d38 2557 return false;
fab7adbf 2558
9cd3f3e6 2559 case PLUS:
2560 case MINUS:
9cd3f3e6 2561 *total = COSTS_N_INSNS (1);
2562 return false;
2563
ffead1ca 2564 case MULT:
18925d38 2565 switch (GET_MODE (x))
2566 {
2567 case SImode:
9cd3f3e6 2568 {
18925d38 2569 rtx left = XEXP (x, 0);
2570 rtx right = XEXP (x, 1);
2571 if (GET_CODE (right) == CONST_INT
cb888f33 2572 && CONST_OK_FOR_K (INTVAL (right)))
18925d38 2573 *total = s390_cost->mhi;
2574 else if (GET_CODE (left) == SIGN_EXTEND)
2575 *total = s390_cost->mh;
2576 else
2577 *total = s390_cost->ms; /* msr, ms, msy */
2578 break;
2579 }
2580 case DImode:
2581 {
2582 rtx left = XEXP (x, 0);
2583 rtx right = XEXP (x, 1);
b5fdc416 2584 if (TARGET_ZARCH)
18925d38 2585 {
2586 if (GET_CODE (right) == CONST_INT
cb888f33 2587 && CONST_OK_FOR_K (INTVAL (right)))
18925d38 2588 *total = s390_cost->mghi;
2589 else if (GET_CODE (left) == SIGN_EXTEND)
2590 *total = s390_cost->msgf;
2591 else
2592 *total = s390_cost->msg; /* msgr, msg */
2593 }
2594 else /* TARGET_31BIT */
2595 {
2596 if (GET_CODE (left) == SIGN_EXTEND
2597 && GET_CODE (right) == SIGN_EXTEND)
2598 /* mulsidi case: mr, m */
2599 *total = s390_cost->m;
9cd3f3e6 2600 else if (GET_CODE (left) == ZERO_EXTEND
2601 && GET_CODE (right) == ZERO_EXTEND
2602 && TARGET_CPU_ZARCH)
2603 /* umulsidi case: ml, mlr */
2604 *total = s390_cost->ml;
18925d38 2605 else
2606 /* Complex calculation is required. */
2607 *total = COSTS_N_INSNS (40);
2608 }
2609 break;
2610 }
2611 case SFmode:
2612 case DFmode:
2613 *total = s390_cost->mult_df;
2614 break;
429f9fdb 2615 case TFmode:
2616 *total = s390_cost->mxbr;
2617 break;
18925d38 2618 default:
2619 return false;
2620 }
2621 return false;
fab7adbf 2622
81470015 2623 case FMA:
2624 switch (GET_MODE (x))
2625 {
2626 case DFmode:
2627 *total = s390_cost->madbr;
2628 break;
2629 case SFmode:
2630 *total = s390_cost->maebr;
2631 break;
2632 default:
2633 return false;
2634 }
2635 /* Negate in the third argument is free: FMSUB. */
2636 if (GET_CODE (XEXP (x, 2)) == NEG)
2637 {
20d892d1 2638 *total += (rtx_cost (XEXP (x, 0), FMA, 0, speed)
2639 + rtx_cost (XEXP (x, 1), FMA, 1, speed)
2640 + rtx_cost (XEXP (XEXP (x, 2), 0), FMA, 2, speed));
81470015 2641 return true;
2642 }
2643 return false;
2644
3f074425 2645 case UDIV:
2646 case UMOD:
2647 if (GET_MODE (x) == TImode) /* 128 bit division */
2648 *total = s390_cost->dlgr;
2649 else if (GET_MODE (x) == DImode)
2650 {
2651 rtx right = XEXP (x, 1);
2652 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
2653 *total = s390_cost->dlr;
2654 else /* 64 by 64 bit division */
2655 *total = s390_cost->dlgr;
2656 }
2657 else if (GET_MODE (x) == SImode) /* 32 bit division */
2658 *total = s390_cost->dlr;
2659 return false;
2660
fab7adbf 2661 case DIV:
3f074425 2662 case MOD:
2663 if (GET_MODE (x) == DImode)
2664 {
2665 rtx right = XEXP (x, 1);
2666 if (GET_CODE (right) == ZERO_EXTEND) /* 64 by 32 bit division */
b5fdc416 2667 if (TARGET_ZARCH)
3f074425 2668 *total = s390_cost->dsgfr;
2669 else
2670 *total = s390_cost->dr;
2671 else /* 64 by 64 bit division */
2672 *total = s390_cost->dsgr;
2673 }
2674 else if (GET_MODE (x) == SImode) /* 32 bit division */
2675 *total = s390_cost->dlr;
2676 else if (GET_MODE (x) == SFmode)
260075cc 2677 {
095798e3 2678 *total = s390_cost->debr;
260075cc 2679 }
2680 else if (GET_MODE (x) == DFmode)
2681 {
095798e3 2682 *total = s390_cost->ddbr;
260075cc 2683 }
429f9fdb 2684 else if (GET_MODE (x) == TFmode)
2685 {
095798e3 2686 *total = s390_cost->dxbr;
429f9fdb 2687 }
18925d38 2688 return false;
2689
9cd3f3e6 2690 case SQRT:
2691 if (GET_MODE (x) == SFmode)
2692 *total = s390_cost->sqebr;
429f9fdb 2693 else if (GET_MODE (x) == DFmode)
9cd3f3e6 2694 *total = s390_cost->sqdbr;
429f9fdb 2695 else /* TFmode */
2696 *total = s390_cost->sqxbr;
9cd3f3e6 2697 return false;
2698
18925d38 2699 case SIGN_EXTEND:
9cd3f3e6 2700 case ZERO_EXTEND:
3f074425 2701 if (outer_code == MULT || outer_code == DIV || outer_code == MOD
2702 || outer_code == PLUS || outer_code == MINUS
2703 || outer_code == COMPARE)
18925d38 2704 *total = 0;
2705 return false;
fab7adbf 2706
3f074425 2707 case COMPARE:
2708 *total = COSTS_N_INSNS (1);
2709 if (GET_CODE (XEXP (x, 0)) == AND
2710 && GET_CODE (XEXP (x, 1)) == CONST_INT
2711 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
2712 {
2713 rtx op0 = XEXP (XEXP (x, 0), 0);
2714 rtx op1 = XEXP (XEXP (x, 0), 1);
2715 rtx op2 = XEXP (x, 1);
2716
2717 if (memory_operand (op0, GET_MODE (op0))
2718 && s390_tm_ccmode (op1, op2, 0) != VOIDmode)
2719 return true;
2720 if (register_operand (op0, GET_MODE (op0))
2721 && s390_tm_ccmode (op1, op2, 1) != VOIDmode)
2722 return true;
2723 }
2724 return false;
2725
fab7adbf 2726 default:
2727 return false;
2728 }
2729}
2730
ee9c19ee 2731/* Return the cost of an address rtx ADDR. */
2732
ec0457a8 2733static int
d9c5e5f4 2734s390_address_cost (rtx addr, enum machine_mode mode ATTRIBUTE_UNUSED,
2735 addr_space_t as ATTRIBUTE_UNUSED,
2736 bool speed ATTRIBUTE_UNUSED)
ee9c19ee 2737{
2738 struct s390_address ad;
2739 if (!s390_decompose_address (addr, &ad))
2740 return 1000;
2741
2742 return ad.indx? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (1);
2743}
2744
be00aaa8 2745/* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
2746 otherwise return 0. */
2747
2748int
edd89d66 2749tls_symbolic_operand (rtx op)
be00aaa8 2750{
be00aaa8 2751 if (GET_CODE (op) != SYMBOL_REF)
2752 return 0;
a3e33162 2753 return SYMBOL_REF_TLS_MODEL (op);
be00aaa8 2754}
4673c1a0 2755\f
923cf36d 2756/* Split DImode access register reference REG (on 64-bit) into its constituent
2757 low and high parts, and store them into LO and HI. Note that gen_lowpart/
2758 gen_highpart cannot be used as they assume all registers are word-sized,
2759 while our access registers have only half that size. */
2760
2761void
2762s390_split_access_reg (rtx reg, rtx *lo, rtx *hi)
2763{
2764 gcc_assert (TARGET_64BIT);
2765 gcc_assert (ACCESS_REG_P (reg));
2766 gcc_assert (GET_MODE (reg) == DImode);
2767 gcc_assert (!(REGNO (reg) & 1));
2768
2769 *lo = gen_rtx_REG (SImode, REGNO (reg) + 1);
2770 *hi = gen_rtx_REG (SImode, REGNO (reg));
2771}
4673c1a0 2772
56769981 2773/* Return true if OP contains a symbol reference */
4673c1a0 2774
e5537457 2775bool
b40da9a7 2776symbolic_reference_mentioned_p (rtx op)
4673c1a0 2777{
edd89d66 2778 const char *fmt;
2779 int i;
4673c1a0 2780
2781 if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
2782 return 1;
2783
2784 fmt = GET_RTX_FORMAT (GET_CODE (op));
2785 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2786 {
2787 if (fmt[i] == 'E')
2788 {
edd89d66 2789 int j;
4673c1a0 2790
2791 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2792 if (symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
2793 return 1;
2794 }
2795
2796 else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i)))
2797 return 1;
2798 }
2799
2800 return 0;
2801}
2802
be00aaa8 2803/* Return true if OP contains a reference to a thread-local symbol. */
2804
e5537457 2805bool
b40da9a7 2806tls_symbolic_reference_mentioned_p (rtx op)
be00aaa8 2807{
edd89d66 2808 const char *fmt;
2809 int i;
be00aaa8 2810
2811 if (GET_CODE (op) == SYMBOL_REF)
2812 return tls_symbolic_operand (op);
2813
2814 fmt = GET_RTX_FORMAT (GET_CODE (op));
2815 for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--)
2816 {
2817 if (fmt[i] == 'E')
2818 {
edd89d66 2819 int j;
be00aaa8 2820
2821 for (j = XVECLEN (op, i) - 1; j >= 0; j--)
2822 if (tls_symbolic_reference_mentioned_p (XVECEXP (op, i, j)))
e5537457 2823 return true;
be00aaa8 2824 }
2825
2826 else if (fmt[i] == 'e' && tls_symbolic_reference_mentioned_p (XEXP (op, i)))
e5537457 2827 return true;
be00aaa8 2828 }
2829
e5537457 2830 return false;
be00aaa8 2831}
2832
4673c1a0 2833
f81e845f 2834/* Return true if OP is a legitimate general operand when
2835 generating PIC code. It is given that flag_pic is on
56769981 2836 and that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2837
4673c1a0 2838int
edd89d66 2839legitimate_pic_operand_p (rtx op)
4673c1a0 2840{
8b4a4127 2841 /* Accept all non-symbolic constants. */
4673c1a0 2842 if (!SYMBOLIC_CONST (op))
2843 return 1;
2844
f81e845f 2845 /* Reject everything else; must be handled
be00aaa8 2846 via emit_symbolic_move. */
4673c1a0 2847 return 0;
2848}
2849
56769981 2850/* Returns true if the constant value OP is a legitimate general operand.
2851 It is given that OP satisfies CONSTANT_P or is a CONST_DOUBLE. */
2852
ca316360 2853static bool
2854s390_legitimate_constant_p (enum machine_mode mode, rtx op)
4673c1a0 2855{
8b4a4127 2856 /* Accept all non-symbolic constants. */
4673c1a0 2857 if (!SYMBOLIC_CONST (op))
2858 return 1;
2859
be00aaa8 2860 /* Accept immediate LARL operands. */
ca316360 2861 if (TARGET_CPU_ZARCH && larl_operand (op, mode))
be00aaa8 2862 return 1;
2863
2864 /* Thread-local symbols are never legal constants. This is
2865 so that emit_call knows that computing such addresses
2866 might require a function call. */
2867 if (TLS_SYMBOLIC_CONST (op))
2868 return 0;
2869
4673c1a0 2870 /* In the PIC case, symbolic constants must *not* be
2871 forced into the literal pool. We accept them here,
be00aaa8 2872 so that they will be handled by emit_symbolic_move. */
4673c1a0 2873 if (flag_pic)
2874 return 1;
2875
4673c1a0 2876 /* All remaining non-PIC symbolic constants are
2877 forced into the literal pool. */
2878 return 0;
2879}
2880
be00aaa8 2881/* Determine if it's legal to put X into the constant pool. This
2882 is not possible if X contains the address of a symbol that is
2883 not constant (TLS) or not known at final link time (PIC). */
2884
2885static bool
7d7d7bd2 2886s390_cannot_force_const_mem (enum machine_mode mode, rtx x)
be00aaa8 2887{
2888 switch (GET_CODE (x))
2889 {
2890 case CONST_INT:
2891 case CONST_DOUBLE:
2892 /* Accept all non-symbolic constants. */
2893 return false;
2894
2895 case LABEL_REF:
2896 /* Labels are OK iff we are non-PIC. */
2897 return flag_pic != 0;
2898
2899 case SYMBOL_REF:
2900 /* 'Naked' TLS symbol references are never OK,
2901 non-TLS symbols are OK iff we are non-PIC. */
2902 if (tls_symbolic_operand (x))
2903 return true;
2904 else
2905 return flag_pic != 0;
2906
2907 case CONST:
7d7d7bd2 2908 return s390_cannot_force_const_mem (mode, XEXP (x, 0));
be00aaa8 2909 case PLUS:
2910 case MINUS:
7d7d7bd2 2911 return s390_cannot_force_const_mem (mode, XEXP (x, 0))
2912 || s390_cannot_force_const_mem (mode, XEXP (x, 1));
be00aaa8 2913
2914 case UNSPEC:
2915 switch (XINT (x, 1))
2916 {
2917 /* Only lt-relative or GOT-relative UNSPECs are OK. */
12ef3745 2918 case UNSPEC_LTREL_OFFSET:
2919 case UNSPEC_GOT:
2920 case UNSPEC_GOTOFF:
2921 case UNSPEC_PLTOFF:
be00aaa8 2922 case UNSPEC_TLSGD:
2923 case UNSPEC_TLSLDM:
2924 case UNSPEC_NTPOFF:
2925 case UNSPEC_DTPOFF:
2926 case UNSPEC_GOTNTPOFF:
2927 case UNSPEC_INDNTPOFF:
2928 return false;
2929
d345b493 2930 /* If the literal pool shares the code section, be put
2931 execute template placeholders into the pool as well. */
2932 case UNSPEC_INSN:
2933 return TARGET_CPU_ZARCH;
2934
be00aaa8 2935 default:
2936 return true;
2937 }
2938 break;
2939
2940 default:
32eda510 2941 gcc_unreachable ();
be00aaa8 2942 }
2943}
2944
8b4a4127 2945/* Returns true if the constant value OP is a legitimate general
f81e845f 2946 operand during and after reload. The difference to
8b4a4127 2947 legitimate_constant_p is that this function will not accept
2948 a constant that would need to be forced to the literal pool
33d033da 2949 before it can be used as operand.
2950 This function accepts all constants which can be loaded directly
2951 into a GPR. */
8b4a4127 2952
e5537457 2953bool
edd89d66 2954legitimate_reload_constant_p (rtx op)
8b4a4127 2955{
51aa1e9c 2956 /* Accept la(y) operands. */
f81e845f 2957 if (GET_CODE (op) == CONST_INT
51aa1e9c 2958 && DISP_IN_RANGE (INTVAL (op)))
e5537457 2959 return true;
51aa1e9c 2960
163277cf 2961 /* Accept l(g)hi/l(g)fi operands. */
8b4a4127 2962 if (GET_CODE (op) == CONST_INT
163277cf 2963 && (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
e5537457 2964 return true;
8b4a4127 2965
2966 /* Accept lliXX operands. */
dafc8d45 2967 if (TARGET_ZARCH
53239c89 2968 && GET_CODE (op) == CONST_INT
2969 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2970 && s390_single_part (op, word_mode, HImode, 0) >= 0)
e5537457 2971 return true;
8b4a4127 2972
163277cf 2973 if (TARGET_EXTIMM
2974 && GET_CODE (op) == CONST_INT
2975 && trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
2976 && s390_single_part (op, word_mode, SImode, 0) >= 0)
2977 return true;
2978
8b4a4127 2979 /* Accept larl operands. */
dafc8d45 2980 if (TARGET_CPU_ZARCH
8b4a4127 2981 && larl_operand (op, VOIDmode))
e5537457 2982 return true;
8b4a4127 2983
70037005 2984 /* Accept floating-point zero operands that fit into a single GPR. */
2985 if (GET_CODE (op) == CONST_DOUBLE
2986 && s390_float_const_zero_p (op)
2987 && GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
2988 return true;
2989
53239c89 2990 /* Accept double-word operands that can be split. */
2991 if (GET_CODE (op) == CONST_INT
2992 && trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op))
2993 {
2994 enum machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
2995 rtx hi = operand_subword (op, 0, 0, dword_mode);
2996 rtx lo = operand_subword (op, 1, 0, dword_mode);
2997 return legitimate_reload_constant_p (hi)
2998 && legitimate_reload_constant_p (lo);
2999 }
3000
8b4a4127 3001 /* Everything else cannot be handled without reload. */
e5537457 3002 return false;
8b4a4127 3003}
3004
33d033da 3005/* Returns true if the constant value OP is a legitimate fp operand
3006 during and after reload.
3007 This function accepts all constants which can be loaded directly
3008 into an FPR. */
3009
3010static bool
3011legitimate_reload_fp_constant_p (rtx op)
3012{
3013 /* Accept floating-point zero operands if the load zero instruction
81769881 3014 can be used. Prior to z196 the load fp zero instruction caused a
3015 performance penalty if the result is used as BFP number. */
33d033da 3016 if (TARGET_Z196
3017 && GET_CODE (op) == CONST_DOUBLE
3018 && s390_float_const_zero_p (op))
3019 return true;
3020
3021 return false;
3022}
3023
8deb3959 3024/* Given an rtx OP being reloaded into a reg required to be in class RCLASS,
8b4a4127 3025 return the class of reg to actually use. */
3026
3359ccfd 3027static reg_class_t
3028s390_preferred_reload_class (rtx op, reg_class_t rclass)
8b4a4127 3029{
8b4a4127 3030 switch (GET_CODE (op))
3031 {
70037005 3032 /* Constants we cannot reload into general registers
3033 must be forced into the literal pool. */
8b4a4127 3034 case CONST_DOUBLE:
3035 case CONST_INT:
70037005 3036 if (reg_class_subset_p (GENERAL_REGS, rclass)
3037 && legitimate_reload_constant_p (op))
3038 return GENERAL_REGS;
3039 else if (reg_class_subset_p (ADDR_REGS, rclass)
3040 && legitimate_reload_constant_p (op))
3041 return ADDR_REGS;
33d033da 3042 else if (reg_class_subset_p (FP_REGS, rclass)
3043 && legitimate_reload_fp_constant_p (op))
3044 return FP_REGS;
3045 return NO_REGS;
8b4a4127 3046
3047 /* If a symbolic constant or a PLUS is reloaded,
0b300c86 3048 it is most likely being used as an address, so
3049 prefer ADDR_REGS. If 'class' is not a superset
3050 of ADDR_REGS, e.g. FP_REGS, reject this reload. */
de47476b 3051 case CONST:
3052 /* A larl operand with odd addend will get fixed via secondary
3053 reload. So don't request it to be pushed into literal
3054 pool. */
3055 if (TARGET_CPU_ZARCH
3056 && GET_CODE (XEXP (op, 0)) == PLUS
3057 && GET_CODE (XEXP (XEXP(op, 0), 0)) == SYMBOL_REF
3058 && GET_CODE (XEXP (XEXP(op, 0), 1)) == CONST_INT)
3059 {
3060 if (reg_class_subset_p (ADDR_REGS, rclass))
3061 return ADDR_REGS;
3062 else
3063 return NO_REGS;
3064 }
3065 /* fallthrough */
8b4a4127 3066 case LABEL_REF:
3067 case SYMBOL_REF:
08d88e72 3068 if (!legitimate_reload_constant_p (op))
3069 return NO_REGS;
3070 /* fallthrough */
3071 case PLUS:
3072 /* load address will be used. */
8deb3959 3073 if (reg_class_subset_p (ADDR_REGS, rclass))
08d88e72 3074 return ADDR_REGS;
0b300c86 3075 else
3076 return NO_REGS;
8b4a4127 3077
3078 default:
3079 break;
3080 }
3081
8deb3959 3082 return rclass;
8b4a4127 3083}
4673c1a0 3084
e68d6a13 3085/* Return true if ADDR is SYMBOL_REF + addend with addend being a
3086 multiple of ALIGNMENT and the SYMBOL_REF being naturally
3087 aligned. */
3088
3089bool
3090s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
3091{
3092 HOST_WIDE_INT addend;
3093 rtx symref;
3094
2a672556 3095 if (!s390_loadrelative_operand_p (addr, &symref, &addend))
3096 return false;
62cb5855 3097
2a672556 3098 if (addend & (alignment - 1))
e68d6a13 3099 return false;
3100
2a672556 3101 if (GET_CODE (symref) == SYMBOL_REF
3102 && !SYMBOL_REF_NOT_NATURALLY_ALIGNED_P (symref))
3103 return true;
3104
3105 if (GET_CODE (symref) == UNSPEC
3106 && alignment <= UNITS_PER_LONG)
3107 return true;
3108
3109 return false;
e68d6a13 3110}
3111
3112/* ADDR is moved into REG using larl. If ADDR isn't a valid larl
3113 operand SCRATCH is used to reload the even part of the address and
3114 adding one. */
3115
3116void
3117s390_reload_larl_operand (rtx reg, rtx addr, rtx scratch)
3118{
3119 HOST_WIDE_INT addend;
3120 rtx symref;
3121
2a672556 3122 if (!s390_loadrelative_operand_p (addr, &symref, &addend))
e68d6a13 3123 gcc_unreachable ();
3124
3125 if (!(addend & 1))
3126 /* Easy case. The addend is even so larl will do fine. */
3127 emit_move_insn (reg, addr);
3128 else
3129 {
3130 /* We can leave the scratch register untouched if the target
3131 register is a valid base register. */
3132 if (REGNO (reg) < FIRST_PSEUDO_REGISTER
3133 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS)
3134 scratch = reg;
3135
3136 gcc_assert (REGNO (scratch) < FIRST_PSEUDO_REGISTER);
3137 gcc_assert (REGNO_REG_CLASS (REGNO (scratch)) == ADDR_REGS);
3138
3139 if (addend != 1)
3140 emit_move_insn (scratch,
3141 gen_rtx_CONST (Pmode,
3142 gen_rtx_PLUS (Pmode, symref,
3143 GEN_INT (addend - 1))));
3144 else
3145 emit_move_insn (scratch, symref);
3146
3147 /* Increment the address using la in order to avoid clobbering cc. */
de47476b 3148 s390_load_address (reg, gen_rtx_PLUS (Pmode, scratch, const1_rtx));
e68d6a13 3149 }
3150}
3151
3152/* Generate what is necessary to move between REG and MEM using
3153 SCRATCH. The direction is given by TOMEM. */
3154
3155void
3156s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
3157{
3158 /* Reload might have pulled a constant out of the literal pool.
3159 Force it back in. */
3160 if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
3161 || GET_CODE (mem) == CONST)
3162 mem = force_const_mem (GET_MODE (reg), mem);
3163
3164 gcc_assert (MEM_P (mem));
3165
3166 /* For a load from memory we can leave the scratch register
3167 untouched if the target register is a valid base register. */
3168 if (!tomem
3169 && REGNO (reg) < FIRST_PSEUDO_REGISTER
3170 && REGNO_REG_CLASS (REGNO (reg)) == ADDR_REGS
3171 && GET_MODE (reg) == GET_MODE (scratch))
3172 scratch = reg;
3173
3174 /* Load address into scratch register. Since we can't have a
3175 secondary reload for a secondary reload we have to cover the case
3176 where larl would need a secondary reload here as well. */
3177 s390_reload_larl_operand (scratch, XEXP (mem, 0), scratch);
3178
3179 /* Now we can use a standard load/store to do the move. */
3180 if (tomem)
3181 emit_move_insn (replace_equiv_address (mem, scratch), reg);
3182 else
3183 emit_move_insn (reg, replace_equiv_address (mem, scratch));
3184}
3185
328d5423 3186/* Inform reload about cases where moving X with a mode MODE to a register in
8deb3959 3187 RCLASS requires an extra scratch or immediate register. Return the class
328d5423 3188 needed for the immediate register. */
429f9fdb 3189
964229b7 3190static reg_class_t
3191s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
328d5423 3192 enum machine_mode mode, secondary_reload_info *sri)
3193{
964229b7 3194 enum reg_class rclass = (enum reg_class) rclass_i;
3195
328d5423 3196 /* Intermediate register needed. */
8deb3959 3197 if (reg_classes_intersect_p (CC_REGS, rclass))
bcbf02a5 3198 return GENERAL_REGS;
3199
e68d6a13 3200 if (TARGET_Z10)
3201 {
08d88e72 3202 HOST_WIDE_INT offset;
3203 rtx symref;
3204
e68d6a13 3205 /* On z10 several optimizer steps may generate larl operands with
3206 an odd addend. */
3207 if (in_p
2a672556 3208 && s390_loadrelative_operand_p (x, &symref, &offset)
e68d6a13 3209 && mode == Pmode
08d88e72 3210 && !SYMBOL_REF_ALIGN1_P (symref)
3211 && (offset & 1) == 1)
e68d6a13 3212 sri->icode = ((mode == DImode) ? CODE_FOR_reloaddi_larl_odd_addend_z10
3213 : CODE_FOR_reloadsi_larl_odd_addend_z10);
3214
3215 /* On z10 we need a scratch register when moving QI, TI or floating
3216 point mode values from or to a memory location with a SYMBOL_REF
3217 or if the symref addend of a SI or DI move is not aligned to the
3218 width of the access. */
3219 if (MEM_P (x)
2a672556 3220 && s390_loadrelative_operand_p (XEXP (x, 0), NULL, NULL)
e68d6a13 3221 && (mode == QImode || mode == TImode || FLOAT_MODE_P (mode)
b5fdc416 3222 || (!TARGET_ZARCH && mode == DImode)
e68d6a13 3223 || ((mode == HImode || mode == SImode || mode == DImode)
3224 && (!s390_check_symref_alignment (XEXP (x, 0),
3225 GET_MODE_SIZE (mode))))))
3226 {
3227#define __SECONDARY_RELOAD_CASE(M,m) \
3228 case M##mode: \
3229 if (TARGET_64BIT) \
3230 sri->icode = in_p ? CODE_FOR_reload##m##di_toreg_z10 : \
3231 CODE_FOR_reload##m##di_tomem_z10; \
3232 else \
3233 sri->icode = in_p ? CODE_FOR_reload##m##si_toreg_z10 : \
3234 CODE_FOR_reload##m##si_tomem_z10; \
3235 break;
3236
3237 switch (GET_MODE (x))
3238 {
3239 __SECONDARY_RELOAD_CASE (QI, qi);
3240 __SECONDARY_RELOAD_CASE (HI, hi);
3241 __SECONDARY_RELOAD_CASE (SI, si);
3242 __SECONDARY_RELOAD_CASE (DI, di);
3243 __SECONDARY_RELOAD_CASE (TI, ti);
3244 __SECONDARY_RELOAD_CASE (SF, sf);
3245 __SECONDARY_RELOAD_CASE (DF, df);
3246 __SECONDARY_RELOAD_CASE (TF, tf);
3247 __SECONDARY_RELOAD_CASE (SD, sd);
3248 __SECONDARY_RELOAD_CASE (DD, dd);
3249 __SECONDARY_RELOAD_CASE (TD, td);
3250
3251 default:
3252 gcc_unreachable ();
3253 }
3254#undef __SECONDARY_RELOAD_CASE
3255 }
3256 }
3257
328d5423 3258 /* We need a scratch register when loading a PLUS expression which
3259 is not a legitimate operand of the LOAD ADDRESS instruction. */
7b1bda1c 3260 /* LRA can deal with transformation of plus op very well -- so we
3261 don't need to prompt LRA in this case. */
3262 if (! lra_in_progress && in_p && s390_plus_operand (x, mode))
328d5423 3263 sri->icode = (TARGET_64BIT ?
3264 CODE_FOR_reloaddi_plus : CODE_FOR_reloadsi_plus);
3265
efec32e0 3266 /* Performing a multiword move from or to memory we have to make sure the
328d5423 3267 second chunk in memory is addressable without causing a displacement
3268 overflow. If that would be the case we calculate the address in
3269 a scratch register. */
3270 if (MEM_P (x)
3271 && GET_CODE (XEXP (x, 0)) == PLUS
3272 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3273 && !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
6938bdf8 3274 + GET_MODE_SIZE (mode) - 1))
328d5423 3275 {
efec32e0 3276 /* For GENERAL_REGS a displacement overflow is no problem if occurring
328d5423 3277 in a s_operand address since we may fallback to lm/stm. So we only
3278 have to care about overflows in the b+i+d case. */
8deb3959 3279 if ((reg_classes_intersect_p (GENERAL_REGS, rclass)
328d5423 3280 && s390_class_max_nregs (GENERAL_REGS, mode) > 1
3281 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
3282 /* For FP_REGS no lm/stm is available so this check is triggered
3283 for displacement overflows in b+i+d and b+d like addresses. */
8deb3959 3284 || (reg_classes_intersect_p (FP_REGS, rclass)
328d5423 3285 && s390_class_max_nregs (FP_REGS, mode) > 1))
3286 {
3287 if (in_p)
3288 sri->icode = (TARGET_64BIT ?
3289 CODE_FOR_reloaddi_nonoffmem_in :
3290 CODE_FOR_reloadsi_nonoffmem_in);
3291 else
3292 sri->icode = (TARGET_64BIT ?
3293 CODE_FOR_reloaddi_nonoffmem_out :
3294 CODE_FOR_reloadsi_nonoffmem_out);
3295 }
3296 }
bcbf02a5 3297
08b5e262 3298 /* A scratch address register is needed when a symbolic constant is
3299 copied to r0 compiling with -fPIC. In other cases the target
3300 register might be used as temporary (see legitimize_pic_address). */
8deb3959 3301 if (in_p && SYMBOLIC_CONST (x) && flag_pic == 2 && rclass != ADDR_REGS)
08b5e262 3302 sri->icode = (TARGET_64BIT ?
3303 CODE_FOR_reloaddi_PIC_addr :
3304 CODE_FOR_reloadsi_PIC_addr);
3305
328d5423 3306 /* Either scratch or no register needed. */
66795431 3307 return NO_REGS;
3308}
3309
64f977d6 3310/* Generate code to load SRC, which is PLUS that is not a
3311 legitimate operand for the LA instruction, into TARGET.
3312 SCRATCH may be used as scratch register. */
3313
3314void
edd89d66 3315s390_expand_plus_operand (rtx target, rtx src,
3316 rtx scratch)
64f977d6 3317{
e7f0624a 3318 rtx sum1, sum2;
8ba34dcd 3319 struct s390_address ad;
dc4951d9 3320
dc4951d9 3321 /* src must be a PLUS; get its two operands. */
32eda510 3322 gcc_assert (GET_CODE (src) == PLUS);
3323 gcc_assert (GET_MODE (src) == Pmode);
64f977d6 3324
c10847b9 3325 /* Check if any of the two operands is already scheduled
3326 for replacement by reload. This can happen e.g. when
3327 float registers occur in an address. */
3328 sum1 = find_replacement (&XEXP (src, 0));
3329 sum2 = find_replacement (&XEXP (src, 1));
a5004c3d 3330 src = gen_rtx_PLUS (Pmode, sum1, sum2);
a5004c3d 3331
e7f0624a 3332 /* If the address is already strictly valid, there's nothing to do. */
3333 if (!s390_decompose_address (src, &ad)
1e280623 3334 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
3335 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
64f977d6 3336 {
e7f0624a 3337 /* Otherwise, one of the operands cannot be an address register;
3338 we reload its value into the scratch register. */
3339 if (true_regnum (sum1) < 1 || true_regnum (sum1) > 15)
3340 {
3341 emit_move_insn (scratch, sum1);
3342 sum1 = scratch;
3343 }
3344 if (true_regnum (sum2) < 1 || true_regnum (sum2) > 15)
3345 {
3346 emit_move_insn (scratch, sum2);
3347 sum2 = scratch;
3348 }
64f977d6 3349
e7f0624a 3350 /* According to the way these invalid addresses are generated
3351 in reload.c, it should never happen (at least on s390) that
3352 *neither* of the PLUS components, after find_replacements
3353 was applied, is an address register. */
3354 if (sum1 == scratch && sum2 == scratch)
3355 {
3356 debug_rtx (src);
32eda510 3357 gcc_unreachable ();
e7f0624a 3358 }
64f977d6 3359
e7f0624a 3360 src = gen_rtx_PLUS (Pmode, sum1, sum2);
64f977d6 3361 }
3362
3363 /* Emit the LOAD ADDRESS pattern. Note that reload of PLUS
3364 is only ever performed on addresses, so we can mark the
3365 sum as legitimate for LA in any case. */
4fbc4db5 3366 s390_load_address (target, src);
64f977d6 3367}
3368
3369
e5537457 3370/* Return true if ADDR is a valid memory address.
875862bf 3371 STRICT specifies whether strict register checking applies. */
4673c1a0 3372
fd50b071 3373static bool
3374s390_legitimate_address_p (enum machine_mode mode, rtx addr, bool strict)
4673c1a0 3375{
875862bf 3376 struct s390_address ad;
e68d6a13 3377
3378 if (TARGET_Z10
3379 && larl_operand (addr, VOIDmode)
3380 && (mode == VOIDmode
3381 || s390_check_symref_alignment (addr, GET_MODE_SIZE (mode))))
3382 return true;
3383
875862bf 3384 if (!s390_decompose_address (addr, &ad))
e5537457 3385 return false;
8ba34dcd 3386
3387 if (strict)
3388 {
1e280623 3389 if (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
e5537457 3390 return false;
1e280623 3391
3392 if (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx)))
e5537457 3393 return false;
8ba34dcd 3394 }
3395 else
3396 {
ffead1ca 3397 if (ad.base
1e280623 3398 && !(REGNO (ad.base) >= FIRST_PSEUDO_REGISTER
3399 || REGNO_REG_CLASS (REGNO (ad.base)) == ADDR_REGS))
e5537457 3400 return false;
ffead1ca 3401
1e280623 3402 if (ad.indx
3403 && !(REGNO (ad.indx) >= FIRST_PSEUDO_REGISTER
3404 || REGNO_REG_CLASS (REGNO (ad.indx)) == ADDR_REGS))
3405 return false;
8ba34dcd 3406 }
e5537457 3407 return true;
4673c1a0 3408}
3409
e5537457 3410/* Return true if OP is a valid operand for the LA instruction.
2eb8fe23 3411 In 31-bit, we need to prove that the result is used as an
3412 address, as LA performs only a 31-bit addition. */
3413
e5537457 3414bool
edd89d66 3415legitimate_la_operand_p (rtx op)
2eb8fe23 3416{
3417 struct s390_address addr;
8ba34dcd 3418 if (!s390_decompose_address (op, &addr))
e5537457 3419 return false;
2eb8fe23 3420
e5537457 3421 return (TARGET_64BIT || addr.pointer);
64f977d6 3422}
2eb8fe23 3423
e5537457 3424/* Return true if it is valid *and* preferable to use LA to
c6061690 3425 compute the sum of OP1 and OP2. */
f81e845f 3426
e5537457 3427bool
c6061690 3428preferred_la_operand_p (rtx op1, rtx op2)
a40b2054 3429{
3430 struct s390_address addr;
c6061690 3431
3432 if (op2 != const0_rtx)
3433 op1 = gen_rtx_PLUS (Pmode, op1, op2);
3434
3435 if (!s390_decompose_address (op1, &addr))
e5537457 3436 return false;
1e280623 3437 if (addr.base && !REGNO_OK_FOR_BASE_P (REGNO (addr.base)))
e5537457 3438 return false;
1e280623 3439 if (addr.indx && !REGNO_OK_FOR_INDEX_P (REGNO (addr.indx)))
e5537457 3440 return false;
a40b2054 3441
33d033da 3442 /* Avoid LA instructions with index register on z196; it is
81769881 3443 preferable to use regular add instructions when possible.
3444 Starting with zEC12 the la with index register is "uncracked"
3445 again. */
33d033da 3446 if (addr.indx && s390_tune == PROCESSOR_2817_Z196)
3447 return false;
3448
a40b2054 3449 if (!TARGET_64BIT && !addr.pointer)
e5537457 3450 return false;
a40b2054 3451
3452 if (addr.pointer)
e5537457 3453 return true;
a40b2054 3454
ec3b9583 3455 if ((addr.base && REG_P (addr.base) && REG_POINTER (addr.base))
3456 || (addr.indx && REG_P (addr.indx) && REG_POINTER (addr.indx)))
e5537457 3457 return true;
a40b2054 3458
e5537457 3459 return false;
a40b2054 3460}
3461
4fbc4db5 3462/* Emit a forced load-address operation to load SRC into DST.
3463 This will use the LOAD ADDRESS instruction even in situations
3464 where legitimate_la_operand_p (SRC) returns false. */
2eb8fe23 3465
4fbc4db5 3466void
b40da9a7 3467s390_load_address (rtx dst, rtx src)
64f977d6 3468{
4fbc4db5 3469 if (TARGET_64BIT)
3470 emit_move_insn (dst, src);
3471 else
3472 emit_insn (gen_force_la_31 (dst, src));
2eb8fe23 3473}
3474
4673c1a0 3475/* Return a legitimate reference for ORIG (an address) using the
3476 register REG. If REG is 0, a new pseudo is generated.
3477
3478 There are two types of references that must be handled:
3479
3480 1. Global data references must load the address from the GOT, via
3481 the PIC reg. An insn is emitted to do this load, and the reg is
3482 returned.
3483
3484 2. Static data references, constant pool addresses, and code labels
3485 compute the address as an offset from the GOT, whose base is in
a3e33162 3486 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
4673c1a0 3487 differentiate them from global data objects. The returned
3488 address is the PIC reg + an unspec constant.
3489
bc409cb4 3490 TARGET_LEGITIMIZE_ADDRESS_P rejects symbolic references unless the PIC
4673c1a0 3491 reg also appears in the address. */
3492
3493rtx
b40da9a7 3494legitimize_pic_address (rtx orig, rtx reg)
4673c1a0 3495{
3496 rtx addr = orig;
2a672556 3497 rtx addend = const0_rtx;
8deb3959 3498 rtx new_rtx = orig;
4673c1a0 3499
1ed004b7 3500 gcc_assert (!TLS_SYMBOLIC_CONST (addr));
3501
2a672556 3502 if (GET_CODE (addr) == CONST)
3503 addr = XEXP (addr, 0);
3504
3505 if (GET_CODE (addr) == PLUS)
4673c1a0 3506 {
2a672556 3507 addend = XEXP (addr, 1);
3508 addr = XEXP (addr, 0);
3509 }
3510
3511 if ((GET_CODE (addr) == LABEL_REF
3512 || (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (addr))
3513 || (GET_CODE (addr) == UNSPEC &&
3514 (XINT (addr, 1) == UNSPEC_GOTENT
3515 || (TARGET_CPU_ZARCH && XINT (addr, 1) == UNSPEC_PLT))))
3516 && GET_CODE (addend) == CONST_INT)
3517 {
3518 /* This can be locally addressed. */
3519
3520 /* larl_operand requires UNSPECs to be wrapped in a const rtx. */
3521 rtx const_addr = (GET_CODE (addr) == UNSPEC ?
3522 gen_rtx_CONST (Pmode, addr) : addr);
3523
3524 if (TARGET_CPU_ZARCH
3525 && larl_operand (const_addr, VOIDmode)
3526 && INTVAL (addend) < (HOST_WIDE_INT)1 << 31
3527 && INTVAL (addend) >= -((HOST_WIDE_INT)1 << 31))
3528 {
3529 if (INTVAL (addend) & 1)
3530 {
3531 /* LARL can't handle odd offsets, so emit a pair of LARL
3532 and LA. */
3533 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3534
3535 if (!DISP_IN_RANGE (INTVAL (addend)))
3536 {
3537 HOST_WIDE_INT even = INTVAL (addend) - 1;
3538 addr = gen_rtx_PLUS (Pmode, addr, GEN_INT (even));
3539 addr = gen_rtx_CONST (Pmode, addr);
3540 addend = const1_rtx;
3541 }
3542
3543 emit_move_insn (temp, addr);
3544 new_rtx = gen_rtx_PLUS (Pmode, temp, addend);
3545
3546 if (reg != 0)
3547 {
3548 s390_load_address (reg, new_rtx);
3549 new_rtx = reg;
3550 }
3551 }
3552 else
3553 {
3554 /* If the offset is even, we can just use LARL. This
3555 will happen automatically. */
3556 }
3557 }
4673c1a0 3558 else
2a672556 3559 {
3560 /* No larl - Access local symbols relative to the GOT. */
4673c1a0 3561
2a672556 3562 rtx temp = reg? reg : gen_reg_rtx (Pmode);
4673c1a0 3563
12ef3745 3564 if (reload_in_progress || reload_completed)
3072d30e 3565 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
12ef3745 3566
2a672556 3567 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF);
3568 if (addend != const0_rtx)
3569 addr = gen_rtx_PLUS (Pmode, addr, addend);
3570 addr = gen_rtx_CONST (Pmode, addr);
3571 addr = force_const_mem (Pmode, addr);
4673c1a0 3572 emit_move_insn (temp, addr);
3573
2a672556 3574 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3575 if (reg != 0)
3576 {
3577 s390_load_address (reg, new_rtx);
3578 new_rtx = reg;
3579 }
3580 }
4673c1a0 3581 }
2a672556 3582 else if (GET_CODE (addr) == SYMBOL_REF && addend == const0_rtx)
4673c1a0 3583 {
2a672556 3584 /* A non-local symbol reference without addend.
3585
3586 The symbol ref is wrapped into an UNSPEC to make sure the
3587 proper operand modifier (@GOT or @GOTENT) will be emitted.
3588 This will tell the linker to put the symbol into the GOT.
3589
3590 Additionally the code dereferencing the GOT slot is emitted here.
3591
3592 An addend to the symref needs to be added afterwards.
3593 legitimize_pic_address calls itself recursively to handle
3594 that case. So no need to do it here. */
3595
4673c1a0 3596 if (reg == 0)
3597 reg = gen_reg_rtx (Pmode);
3598
2a672556 3599 if (TARGET_Z10)
3600 {
3601 /* Use load relative if possible.
3602 lgrl <target>, sym@GOTENT */
3603 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3604 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3605 new_rtx = gen_const_mem (GET_MODE (reg), new_rtx);
3606
3607 emit_move_insn (reg, new_rtx);
3608 new_rtx = reg;
3609 }
3610 else if (flag_pic == 1)
4673c1a0 3611 {
2a672556 3612 /* Assume GOT offset is a valid displacement operand (< 4k
3613 or < 512k with z990). This is handled the same way in
3614 both 31- and 64-bit code (@GOT).
3615 lg <target>, sym@GOT(r12) */
4673c1a0 3616
9a2a66ae 3617 if (reload_in_progress || reload_completed)
3072d30e 3618 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
4673c1a0 3619
8deb3959 3620 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
3621 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3622 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3623 new_rtx = gen_const_mem (Pmode, new_rtx);
3624 emit_move_insn (reg, new_rtx);
3625 new_rtx = reg;
4673c1a0 3626 }
dafc8d45 3627 else if (TARGET_CPU_ZARCH)
4673c1a0 3628 {
3629 /* If the GOT offset might be >= 4k, we determine the position
2a672556 3630 of the GOT entry via a PC-relative LARL (@GOTENT).
3631 larl temp, sym@GOTENT
3632 lg <target>, 0(temp) */
4673c1a0 3633
08b5e262 3634 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3635
3636 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3637 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
4673c1a0 3638
8deb3959 3639 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTENT);
3640 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
2a672556 3641 emit_move_insn (temp, new_rtx);
4673c1a0 3642
2a672556 3643 new_rtx = gen_const_mem (Pmode, temp);
8deb3959 3644 emit_move_insn (reg, new_rtx);
2a672556 3645
8deb3959 3646 new_rtx = reg;
4673c1a0 3647 }
3648 else
3649 {
f81e845f 3650 /* If the GOT offset might be >= 4k, we have to load it
2a672556 3651 from the literal pool (@GOT).
3652
3653 lg temp, lit-litbase(r13)
3654 lg <target>, 0(temp)
3655 lit: .long sym@GOT */
4673c1a0 3656
08b5e262 3657 rtx temp = reg ? reg : gen_reg_rtx (Pmode);
3658
3659 gcc_assert (REGNO (temp) >= FIRST_PSEUDO_REGISTER
3660 || REGNO_REG_CLASS (REGNO (temp)) == ADDR_REGS);
4673c1a0 3661
9a2a66ae 3662 if (reload_in_progress || reload_completed)
3072d30e 3663 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
4673c1a0 3664
12ef3745 3665 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT);
525d1294 3666 addr = gen_rtx_CONST (Pmode, addr);
3667 addr = force_const_mem (Pmode, addr);
4673c1a0 3668 emit_move_insn (temp, addr);
3669
8deb3959 3670 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3671 new_rtx = gen_const_mem (Pmode, new_rtx);
3672 emit_move_insn (reg, new_rtx);
3673 new_rtx = reg;
4673c1a0 3674 }
f81e845f 3675 }
2a672556 3676 else if (GET_CODE (addr) == UNSPEC && GET_CODE (addend) == CONST_INT)
4673c1a0 3677 {
2a672556 3678 gcc_assert (XVECLEN (addr, 0) == 1);
3679 switch (XINT (addr, 1))
4673c1a0 3680 {
2a672556 3681 /* These address symbols (or PLT slots) relative to the GOT
3682 (not GOT slots!). In general this will exceed the
3683 displacement range so these value belong into the literal
3684 pool. */
3685 case UNSPEC_GOTOFF:
3686 case UNSPEC_PLTOFF:
3687 new_rtx = force_const_mem (Pmode, orig);
3688 break;
4673c1a0 3689
2a672556 3690 /* For -fPIC the GOT size might exceed the displacement
3691 range so make sure the value is in the literal pool. */
3692 case UNSPEC_GOT:
3693 if (flag_pic == 2)
3694 new_rtx = force_const_mem (Pmode, orig);
3695 break;
4673c1a0 3696
2a672556 3697 /* For @GOTENT larl is used. This is handled like local
3698 symbol refs. */
3699 case UNSPEC_GOTENT:
3700 gcc_unreachable ();
3701 break;
4673c1a0 3702
2a672556 3703 /* @PLT is OK as is on 64-bit, must be converted to
3704 GOT-relative @PLTOFF on 31-bit. */
3705 case UNSPEC_PLT:
3706 if (!TARGET_CPU_ZARCH)
4673c1a0 3707 {
2a672556 3708 rtx temp = reg? reg : gen_reg_rtx (Pmode);
3709
3710 if (reload_in_progress || reload_completed)
3711 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
3712
3713 addr = XVECEXP (addr, 0, 0);
3714 addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr),
3715 UNSPEC_PLTOFF);
3716 if (addend != const0_rtx)
3717 addr = gen_rtx_PLUS (Pmode, addr, addend);
3718 addr = gen_rtx_CONST (Pmode, addr);
3719 addr = force_const_mem (Pmode, addr);
3720 emit_move_insn (temp, addr);
3721
3722 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3723 if (reg != 0)
4673c1a0 3724 {
2a672556 3725 s390_load_address (reg, new_rtx);
3726 new_rtx = reg;
4673c1a0 3727 }
2a672556 3728 }
3729 else
3730 /* On 64 bit larl can be used. This case is handled like
3731 local symbol refs. */
3732 gcc_unreachable ();
3733 break;
3734
3735 /* Everything else cannot happen. */
3736 default:
3737 gcc_unreachable ();
3738 }
3739 }
3740 else if (addend != const0_rtx)
3741 {
3742 /* Otherwise, compute the sum. */
4673c1a0 3743
2a672556 3744 rtx base = legitimize_pic_address (addr, reg);
3745 new_rtx = legitimize_pic_address (addend,
3746 base == reg ? NULL_RTX : reg);
3747 if (GET_CODE (new_rtx) == CONST_INT)
3748 new_rtx = plus_constant (Pmode, base, INTVAL (new_rtx));
3749 else
3750 {
3751 if (GET_CODE (new_rtx) == PLUS && CONSTANT_P (XEXP (new_rtx, 1)))
3752 {
3753 base = gen_rtx_PLUS (Pmode, base, XEXP (new_rtx, 0));
3754 new_rtx = XEXP (new_rtx, 1);
4673c1a0 3755 }
2a672556 3756 new_rtx = gen_rtx_PLUS (Pmode, base, new_rtx);
4673c1a0 3757 }
2a672556 3758
3759 if (GET_CODE (new_rtx) == CONST)
3760 new_rtx = XEXP (new_rtx, 0);
3761 new_rtx = force_operand (new_rtx, 0);
4673c1a0 3762 }
2a672556 3763
8deb3959 3764 return new_rtx;
4673c1a0 3765}
3766
be00aaa8 3767/* Load the thread pointer into a register. */
3768
cc87d0c5 3769rtx
3770s390_get_thread_pointer (void)
be00aaa8 3771{
923cf36d 3772 rtx tp = gen_reg_rtx (Pmode);
be00aaa8 3773
923cf36d 3774 emit_move_insn (tp, gen_rtx_REG (Pmode, TP_REGNUM));
be00aaa8 3775 mark_reg_pointer (tp, BITS_PER_WORD);
3776
3777 return tp;
3778}
3779
7346ca58 3780/* Emit a tls call insn. The call target is the SYMBOL_REF stored
3781 in s390_tls_symbol which always refers to __tls_get_offset.
3782 The returned offset is written to RESULT_REG and an USE rtx is
3783 generated for TLS_CALL. */
be00aaa8 3784
3785static GTY(()) rtx s390_tls_symbol;
7346ca58 3786
3787static void
3788s390_emit_tls_call_insn (rtx result_reg, rtx tls_call)
be00aaa8 3789{
7346ca58 3790 rtx insn;
f588eb9f 3791
c60a7572 3792 if (!flag_pic)
3793 emit_insn (s390_load_got ());
7346ca58 3794
be00aaa8 3795 if (!s390_tls_symbol)
3796 s390_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_offset");
3797
f588eb9f 3798 insn = s390_emit_call (s390_tls_symbol, tls_call, result_reg,
3799 gen_rtx_REG (Pmode, RETURN_REGNUM));
7346ca58 3800
3801 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), result_reg);
9c2a0c05 3802 RTL_CONST_CALL_P (insn) = 1;
be00aaa8 3803}
3804
3805/* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3806 this (thread-local) address. REG may be used as temporary. */
3807
3808static rtx
b40da9a7 3809legitimize_tls_address (rtx addr, rtx reg)
be00aaa8 3810{
8deb3959 3811 rtx new_rtx, tls_call, temp, base, r2, insn;
be00aaa8 3812
3813 if (GET_CODE (addr) == SYMBOL_REF)
3814 switch (tls_symbolic_operand (addr))
3815 {
3816 case TLS_MODEL_GLOBAL_DYNAMIC:
3817 start_sequence ();
3818 r2 = gen_rtx_REG (Pmode, 2);
3819 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_TLSGD);
8deb3959 3820 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3821 new_rtx = force_const_mem (Pmode, new_rtx);
3822 emit_move_insn (r2, new_rtx);
7346ca58 3823 s390_emit_tls_call_insn (r2, tls_call);
be00aaa8 3824 insn = get_insns ();
3825 end_sequence ();
3826
8deb3959 3827 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
be00aaa8 3828 temp = gen_reg_rtx (Pmode);
8deb3959 3829 emit_libcall_block (insn, temp, r2, new_rtx);
be00aaa8 3830
8deb3959 3831 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
be00aaa8 3832 if (reg != 0)
3833 {
8deb3959 3834 s390_load_address (reg, new_rtx);
3835 new_rtx = reg;
be00aaa8 3836 }
3837 break;
3838
3839 case TLS_MODEL_LOCAL_DYNAMIC:
3840 start_sequence ();
3841 r2 = gen_rtx_REG (Pmode, 2);
3842 tls_call = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM);
8deb3959 3843 new_rtx = gen_rtx_CONST (Pmode, tls_call);
3844 new_rtx = force_const_mem (Pmode, new_rtx);
3845 emit_move_insn (r2, new_rtx);
7346ca58 3846 s390_emit_tls_call_insn (r2, tls_call);
be00aaa8 3847 insn = get_insns ();
3848 end_sequence ();
3849
8deb3959 3850 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), UNSPEC_TLSLDM_NTPOFF);
be00aaa8 3851 temp = gen_reg_rtx (Pmode);
8deb3959 3852 emit_libcall_block (insn, temp, r2, new_rtx);
be00aaa8 3853
8deb3959 3854 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
be00aaa8 3855 base = gen_reg_rtx (Pmode);
8deb3959 3856 s390_load_address (base, new_rtx);
be00aaa8 3857
8deb3959 3858 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_DTPOFF);
3859 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3860 new_rtx = force_const_mem (Pmode, new_rtx);
be00aaa8 3861 temp = gen_reg_rtx (Pmode);
8deb3959 3862 emit_move_insn (temp, new_rtx);
be00aaa8 3863
8deb3959 3864 new_rtx = gen_rtx_PLUS (Pmode, base, temp);
be00aaa8 3865 if (reg != 0)
3866 {
8deb3959 3867 s390_load_address (reg, new_rtx);
3868 new_rtx = reg;
be00aaa8 3869 }
3870 break;
3871
3872 case TLS_MODEL_INITIAL_EXEC:
3873 if (flag_pic == 1)
3874 {
3875 /* Assume GOT offset < 4k. This is handled the same way
3876 in both 31- and 64-bit code. */
3877
3878 if (reload_in_progress || reload_completed)
3072d30e 3879 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
be00aaa8 3880
8deb3959 3881 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3882 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3883 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
3884 new_rtx = gen_const_mem (Pmode, new_rtx);
be00aaa8 3885 temp = gen_reg_rtx (Pmode);
8deb3959 3886 emit_move_insn (temp, new_rtx);
be00aaa8 3887 }
dafc8d45 3888 else if (TARGET_CPU_ZARCH)
be00aaa8 3889 {
3890 /* If the GOT offset might be >= 4k, we determine the position
3891 of the GOT entry via a PC-relative LARL. */
3892
8deb3959 3893 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3894 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
be00aaa8 3895 temp = gen_reg_rtx (Pmode);
8deb3959 3896 emit_move_insn (temp, new_rtx);
be00aaa8 3897
8deb3959 3898 new_rtx = gen_const_mem (Pmode, temp);
be00aaa8 3899 temp = gen_reg_rtx (Pmode);
8deb3959 3900 emit_move_insn (temp, new_rtx);
be00aaa8 3901 }
3902 else if (flag_pic)
3903 {
f81e845f 3904 /* If the GOT offset might be >= 4k, we have to load it
be00aaa8 3905 from the literal pool. */
3906
3907 if (reload_in_progress || reload_completed)
3072d30e 3908 df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
be00aaa8 3909
8deb3959 3910 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTNTPOFF);
3911 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3912 new_rtx = force_const_mem (Pmode, new_rtx);
be00aaa8 3913 temp = gen_reg_rtx (Pmode);
8deb3959 3914 emit_move_insn (temp, new_rtx);
be00aaa8 3915
8deb3959 3916 new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, temp);
3917 new_rtx = gen_const_mem (Pmode, new_rtx);
be00aaa8 3918
8deb3959 3919 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
be00aaa8 3920 temp = gen_reg_rtx (Pmode);
8deb3959 3921 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
be00aaa8 3922 }
3923 else
3924 {
3925 /* In position-dependent code, load the absolute address of
3926 the GOT entry from the literal pool. */
3927
8deb3959 3928 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_INDNTPOFF);
3929 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3930 new_rtx = force_const_mem (Pmode, new_rtx);
be00aaa8 3931 temp = gen_reg_rtx (Pmode);
8deb3959 3932 emit_move_insn (temp, new_rtx);
be00aaa8 3933
8deb3959 3934 new_rtx = temp;
3935 new_rtx = gen_const_mem (Pmode, new_rtx);
3936 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, new_rtx, addr), UNSPEC_TLS_LOAD);
be00aaa8 3937 temp = gen_reg_rtx (Pmode);
8deb3959 3938 emit_insn (gen_rtx_SET (Pmode, temp, new_rtx));
be00aaa8 3939 }
3940
8deb3959 3941 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
be00aaa8 3942 if (reg != 0)
3943 {
8deb3959 3944 s390_load_address (reg, new_rtx);
3945 new_rtx = reg;
be00aaa8 3946 }
3947 break;
3948
3949 case TLS_MODEL_LOCAL_EXEC:
8deb3959 3950 new_rtx = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_NTPOFF);
3951 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
3952 new_rtx = force_const_mem (Pmode, new_rtx);
be00aaa8 3953 temp = gen_reg_rtx (Pmode);
8deb3959 3954 emit_move_insn (temp, new_rtx);
be00aaa8 3955
8deb3959 3956 new_rtx = gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), temp);
be00aaa8 3957 if (reg != 0)
3958 {
8deb3959 3959 s390_load_address (reg, new_rtx);
3960 new_rtx = reg;
be00aaa8 3961 }
3962 break;
3963
3964 default:
32eda510 3965 gcc_unreachable ();
be00aaa8 3966 }
3967
3968 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == UNSPEC)
3969 {
3970 switch (XINT (XEXP (addr, 0), 1))
3971 {
3972 case UNSPEC_INDNTPOFF:
32eda510 3973 gcc_assert (TARGET_CPU_ZARCH);
8deb3959 3974 new_rtx = addr;
be00aaa8 3975 break;
3976
3977 default:
32eda510 3978 gcc_unreachable ();
be00aaa8 3979 }
3980 }
3981
b7ace65c 3982 else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
3983 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
3984 {
8deb3959 3985 new_rtx = XEXP (XEXP (addr, 0), 0);
3986 if (GET_CODE (new_rtx) != SYMBOL_REF)
3987 new_rtx = gen_rtx_CONST (Pmode, new_rtx);
b7ace65c 3988
8deb3959 3989 new_rtx = legitimize_tls_address (new_rtx, reg);
29c05e22 3990 new_rtx = plus_constant (Pmode, new_rtx,
3991 INTVAL (XEXP (XEXP (addr, 0), 1)));
8deb3959 3992 new_rtx = force_operand (new_rtx, 0);
b7ace65c 3993 }
3994
be00aaa8 3995 else
32eda510 3996 gcc_unreachable (); /* for now ... */
be00aaa8 3997
8deb3959 3998 return new_rtx;
be00aaa8 3999}
4000
08b5e262 4001/* Emit insns making the address in operands[1] valid for a standard
4002 move to operands[0]. operands[1] is replaced by an address which
4003 should be used instead of the former RTX to emit the move
4004 pattern. */
4673c1a0 4005
4006void
b40da9a7 4007emit_symbolic_move (rtx *operands)
4673c1a0 4008{
e1ba4a27 4009 rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
4673c1a0 4010
be00aaa8 4011 if (GET_CODE (operands[0]) == MEM)
4673c1a0 4012 operands[1] = force_reg (Pmode, operands[1]);
be00aaa8 4013 else if (TLS_SYMBOLIC_CONST (operands[1]))
4014 operands[1] = legitimize_tls_address (operands[1], temp);
4015 else if (flag_pic)
4673c1a0 4016 operands[1] = legitimize_pic_address (operands[1], temp);
4017}
4018
56769981 4019/* Try machine-dependent ways of modifying an illegitimate address X
4673c1a0 4020 to be legitimate. If we find one, return the new, valid address.
4673c1a0 4021
4022 OLDX is the address as it was before break_out_memory_refs was called.
4023 In some cases it is useful to look at this to decide what needs to be done.
4024
56769981 4025 MODE is the mode of the operand pointed to by X.
4673c1a0 4026
4027 When -fpic is used, special handling is needed for symbolic references.
4028 See comments by legitimize_pic_address for details. */
4029
41e3a0c7 4030static rtx
4031s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
4032 enum machine_mode mode ATTRIBUTE_UNUSED)
4673c1a0 4033{
2eb8fe23 4034 rtx constant_term = const0_rtx;
4673c1a0 4035
be00aaa8 4036 if (TLS_SYMBOLIC_CONST (x))
4037 {
4038 x = legitimize_tls_address (x, 0);
4039
fd50b071 4040 if (s390_legitimate_address_p (mode, x, FALSE))
be00aaa8 4041 return x;
4042 }
1ed004b7 4043 else if (GET_CODE (x) == PLUS
ffead1ca 4044 && (TLS_SYMBOLIC_CONST (XEXP (x, 0))
1ed004b7 4045 || TLS_SYMBOLIC_CONST (XEXP (x, 1))))
4046 {
4047 return x;
4048 }
be00aaa8 4049 else if (flag_pic)
4673c1a0 4050 {
2eb8fe23 4051 if (SYMBOLIC_CONST (x)
f81e845f 4052 || (GET_CODE (x) == PLUS
4053 && (SYMBOLIC_CONST (XEXP (x, 0))
2eb8fe23 4054 || SYMBOLIC_CONST (XEXP (x, 1)))))
4055 x = legitimize_pic_address (x, 0);
4056
fd50b071 4057 if (s390_legitimate_address_p (mode, x, FALSE))
2eb8fe23 4058 return x;
4673c1a0 4059 }
4673c1a0 4060
2eb8fe23 4061 x = eliminate_constant_term (x, &constant_term);
56769981 4062
de84f805 4063 /* Optimize loading of large displacements by splitting them
4064 into the multiple of 4K and the rest; this allows the
f81e845f 4065 former to be CSE'd if possible.
de84f805 4066
4067 Don't do this if the displacement is added to a register
4068 pointing into the stack frame, as the offsets will
4069 change later anyway. */
4070
4071 if (GET_CODE (constant_term) == CONST_INT
51aa1e9c 4072 && !TARGET_LONG_DISPLACEMENT
4073 && !DISP_IN_RANGE (INTVAL (constant_term))
de84f805 4074 && !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
4075 {
4076 HOST_WIDE_INT lower = INTVAL (constant_term) & 0xfff;
4077 HOST_WIDE_INT upper = INTVAL (constant_term) ^ lower;
4078
4079 rtx temp = gen_reg_rtx (Pmode);
4080 rtx val = force_operand (GEN_INT (upper), temp);
4081 if (val != temp)
4082 emit_move_insn (temp, val);
4083
4084 x = gen_rtx_PLUS (Pmode, x, temp);
4085 constant_term = GEN_INT (lower);
4086 }
4087
2eb8fe23 4088 if (GET_CODE (x) == PLUS)
4673c1a0 4089 {
2eb8fe23 4090 if (GET_CODE (XEXP (x, 0)) == REG)
4091 {
edd89d66 4092 rtx temp = gen_reg_rtx (Pmode);
4093 rtx val = force_operand (XEXP (x, 1), temp);
2eb8fe23 4094 if (val != temp)
4095 emit_move_insn (temp, val);
4096
4097 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
4098 }
4099
4100 else if (GET_CODE (XEXP (x, 1)) == REG)
4101 {
edd89d66 4102 rtx temp = gen_reg_rtx (Pmode);
4103 rtx val = force_operand (XEXP (x, 0), temp);
2eb8fe23 4104 if (val != temp)
4105 emit_move_insn (temp, val);
4106
4107 x = gen_rtx_PLUS (Pmode, temp, XEXP (x, 1));
4108 }
4673c1a0 4109 }
2eb8fe23 4110
4111 if (constant_term != const0_rtx)
4112 x = gen_rtx_PLUS (Pmode, x, constant_term);
4113
4114 return x;
4673c1a0 4115}
4116
e4542435 4117/* Try a machine-dependent way of reloading an illegitimate address AD
851d9296 4118 operand. If we find one, push the reload and return the new address.
e4542435 4119
4120 MODE is the mode of the enclosing MEM. OPNUM is the operand number
4121 and TYPE is the reload type of the current reload. */
4122
ffead1ca 4123rtx
e4542435 4124legitimize_reload_address (rtx ad, enum machine_mode mode ATTRIBUTE_UNUSED,
4125 int opnum, int type)
4126{
4127 if (!optimize || TARGET_LONG_DISPLACEMENT)
4128 return NULL_RTX;
4129
4130 if (GET_CODE (ad) == PLUS)
4131 {
4132 rtx tem = simplify_binary_operation (PLUS, Pmode,
4133 XEXP (ad, 0), XEXP (ad, 1));
4134 if (tem)
4135 ad = tem;
4136 }
4137
4138 if (GET_CODE (ad) == PLUS
4139 && GET_CODE (XEXP (ad, 0)) == REG
4140 && GET_CODE (XEXP (ad, 1)) == CONST_INT
4141 && !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
4142 {
4143 HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
4144 HOST_WIDE_INT upper = INTVAL (XEXP (ad, 1)) ^ lower;
8deb3959 4145 rtx cst, tem, new_rtx;
e4542435 4146
4147 cst = GEN_INT (upper);
4148 if (!legitimate_reload_constant_p (cst))
4149 cst = force_const_mem (Pmode, cst);
4150
4151 tem = gen_rtx_PLUS (Pmode, XEXP (ad, 0), cst);
8deb3959 4152 new_rtx = gen_rtx_PLUS (Pmode, tem, GEN_INT (lower));
e4542435 4153
4154 push_reload (XEXP (tem, 1), 0, &XEXP (tem, 1), 0,
ffead1ca 4155 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
e4542435 4156 opnum, (enum reload_type) type);
8deb3959 4157 return new_rtx;
e4542435 4158 }
4159
4160 return NULL_RTX;
4161}
4162
4fbc4db5 4163/* Emit code to move LEN bytes from DST to SRC. */
4164
daa87e5a 4165bool
008c057d 4166s390_expand_movmem (rtx dst, rtx src, rtx len)
4fbc4db5 4167{
daa87e5a 4168 /* When tuning for z10 or higher we rely on the Glibc functions to
4169 do the right thing. Only for constant lengths below 64k we will
4170 generate inline code. */
4171 if (s390_tune >= PROCESSOR_2097_Z10
4172 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4173 return false;
4174
4fbc4db5 4175 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4176 {
4177 if (INTVAL (len) > 0)
008c057d 4178 emit_insn (gen_movmem_short (dst, src, GEN_INT (INTVAL (len) - 1)));
4fbc4db5 4179 }
4180
4181 else if (TARGET_MVCLE)
4182 {
008c057d 4183 emit_insn (gen_movmem_long (dst, src, convert_to_mode (Pmode, len, 1)));
4fbc4db5 4184 }
4185
4186 else
4187 {
4188 rtx dst_addr, src_addr, count, blocks, temp;
7746964e 4189 rtx loop_start_label = gen_label_rtx ();
4ee9c684 4190 rtx loop_end_label = gen_label_rtx ();
4fbc4db5 4191 rtx end_label = gen_label_rtx ();
4192 enum machine_mode mode;
4fbc4db5 4193
4194 mode = GET_MODE (len);
4195 if (mode == VOIDmode)
31838f66 4196 mode = Pmode;
4fbc4db5 4197
4fbc4db5 4198 dst_addr = gen_reg_rtx (Pmode);
4199 src_addr = gen_reg_rtx (Pmode);
4200 count = gen_reg_rtx (mode);
4201 blocks = gen_reg_rtx (mode);
4202
4203 convert_move (count, len, 1);
f81e845f 4204 emit_cmp_and_jump_insns (count, const0_rtx,
4fbc4db5 4205 EQ, NULL_RTX, mode, 1, end_label);
4206
4207 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4208 emit_move_insn (src_addr, force_operand (XEXP (src, 0), NULL_RTX));
4209 dst = change_address (dst, VOIDmode, dst_addr);
4210 src = change_address (src, VOIDmode, src_addr);
f81e845f 4211
b9c74b4d 4212 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4213 OPTAB_DIRECT);
4fbc4db5 4214 if (temp != count)
4215 emit_move_insn (count, temp);
4216
b9c74b4d 4217 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4218 OPTAB_DIRECT);
4fbc4db5 4219 if (temp != blocks)
4220 emit_move_insn (blocks, temp);
4221
4ee9c684 4222 emit_cmp_and_jump_insns (blocks, const0_rtx,
4223 EQ, NULL_RTX, mode, 1, loop_end_label);
7746964e 4224
4225 emit_label (loop_start_label);
4fbc4db5 4226
d5de7805 4227 if (TARGET_Z10
4228 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
4229 {
4230 rtx prefetch;
4231
4232 /* Issue a read prefetch for the +3 cache line. */
4233 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, src_addr, GEN_INT (768)),
4234 const0_rtx, const0_rtx);
4235 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4236 emit_insn (prefetch);
4237
4238 /* Issue a write prefetch for the +3 cache line. */
4239 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (768)),
4240 const1_rtx, const0_rtx);
4241 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4242 emit_insn (prefetch);
4243 }
4244
008c057d 4245 emit_insn (gen_movmem_short (dst, src, GEN_INT (255)));
f81e845f 4246 s390_load_address (dst_addr,
4fbc4db5 4247 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
f81e845f 4248 s390_load_address (src_addr,
4fbc4db5 4249 gen_rtx_PLUS (Pmode, src_addr, GEN_INT (256)));
f81e845f 4250
b9c74b4d 4251 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4252 OPTAB_DIRECT);
4fbc4db5 4253 if (temp != blocks)
4254 emit_move_insn (blocks, temp);
4255
4ee9c684 4256 emit_cmp_and_jump_insns (blocks, const0_rtx,
4257 EQ, NULL_RTX, mode, 1, loop_end_label);
7746964e 4258
4259 emit_jump (loop_start_label);
4ee9c684 4260 emit_label (loop_end_label);
4fbc4db5 4261
008c057d 4262 emit_insn (gen_movmem_short (dst, src,
31838f66 4263 convert_to_mode (Pmode, count, 1)));
4fbc4db5 4264 emit_label (end_label);
4265 }
daa87e5a 4266 return true;
4fbc4db5 4267}
4268
805a133b 4269/* Emit code to set LEN bytes at DST to VAL.
4270 Make use of clrmem if VAL is zero. */
4fbc4db5 4271
4272void
805a133b 4273s390_expand_setmem (rtx dst, rtx len, rtx val)
4fbc4db5 4274{
1ed6fd08 4275 if (GET_CODE (len) == CONST_INT && INTVAL (len) == 0)
4276 return;
4277
805a133b 4278 gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
ffead1ca 4279
1ed6fd08 4280 if (GET_CODE (len) == CONST_INT && INTVAL (len) > 0 && INTVAL (len) <= 257)
4fbc4db5 4281 {
805a133b 4282 if (val == const0_rtx && INTVAL (len) <= 256)
008c057d 4283 emit_insn (gen_clrmem_short (dst, GEN_INT (INTVAL (len) - 1)));
805a133b 4284 else
4285 {
4286 /* Initialize memory by storing the first byte. */
4287 emit_move_insn (adjust_address (dst, QImode, 0), val);
ffead1ca 4288
805a133b 4289 if (INTVAL (len) > 1)
4290 {
4291 /* Initiate 1 byte overlap move.
4292 The first byte of DST is propagated through DSTP1.
4293 Prepare a movmem for: DST+1 = DST (length = LEN - 1).
4294 DST is set to size 1 so the rest of the memory location
4295 does not count as source operand. */
4296 rtx dstp1 = adjust_address (dst, VOIDmode, 1);
5b2a69fa 4297 set_mem_size (dst, 1);
805a133b 4298
ffead1ca 4299 emit_insn (gen_movmem_short (dstp1, dst,
805a133b 4300 GEN_INT (INTVAL (len) - 2)));
4301 }
4302 }
4fbc4db5 4303 }
4304
4305 else if (TARGET_MVCLE)
4306 {
805a133b 4307 val = force_not_mem (convert_modes (Pmode, QImode, val, 1));
4308 emit_insn (gen_setmem_long (dst, convert_to_mode (Pmode, len, 1), val));
4fbc4db5 4309 }
4310
4311 else
4312 {
b5fdc416 4313 rtx dst_addr, count, blocks, temp, dstp1 = NULL_RTX;
7746964e 4314 rtx loop_start_label = gen_label_rtx ();
4ee9c684 4315 rtx loop_end_label = gen_label_rtx ();
4fbc4db5 4316 rtx end_label = gen_label_rtx ();
4317 enum machine_mode mode;
4fbc4db5 4318
4319 mode = GET_MODE (len);
4320 if (mode == VOIDmode)
31838f66 4321 mode = Pmode;
4fbc4db5 4322
4fbc4db5 4323 dst_addr = gen_reg_rtx (Pmode);
4fbc4db5 4324 count = gen_reg_rtx (mode);
4325 blocks = gen_reg_rtx (mode);
4326
4327 convert_move (count, len, 1);
f81e845f 4328 emit_cmp_and_jump_insns (count, const0_rtx,
4fbc4db5 4329 EQ, NULL_RTX, mode, 1, end_label);
4330
4331 emit_move_insn (dst_addr, force_operand (XEXP (dst, 0), NULL_RTX));
4332 dst = change_address (dst, VOIDmode, dst_addr);
f81e845f 4333
805a133b 4334 if (val == const0_rtx)
b9c74b4d 4335 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4336 OPTAB_DIRECT);
805a133b 4337 else
4338 {
4339 dstp1 = adjust_address (dst, VOIDmode, 1);
5b2a69fa 4340 set_mem_size (dst, 1);
805a133b 4341
4342 /* Initialize memory by storing the first byte. */
4343 emit_move_insn (adjust_address (dst, QImode, 0), val);
ffead1ca 4344
805a133b 4345 /* If count is 1 we are done. */
4346 emit_cmp_and_jump_insns (count, const1_rtx,
4347 EQ, NULL_RTX, mode, 1, end_label);
4348
b9c74b4d 4349 temp = expand_binop (mode, add_optab, count, GEN_INT (-2), count, 1,
4350 OPTAB_DIRECT);
805a133b 4351 }
4fbc4db5 4352 if (temp != count)
4353 emit_move_insn (count, temp);
4354
b9c74b4d 4355 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4356 OPTAB_DIRECT);
4fbc4db5 4357 if (temp != blocks)
4358 emit_move_insn (blocks, temp);
4359
4ee9c684 4360 emit_cmp_and_jump_insns (blocks, const0_rtx,
4361 EQ, NULL_RTX, mode, 1, loop_end_label);
7746964e 4362
4363 emit_label (loop_start_label);
4fbc4db5 4364
d5de7805 4365 if (TARGET_Z10
4366 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 1024))
4367 {
4368 /* Issue a write prefetch for the +4 cache line. */
4369 rtx prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, dst_addr,
4370 GEN_INT (1024)),
4371 const1_rtx, const0_rtx);
4372 emit_insn (prefetch);
4373 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4374 }
4375
805a133b 4376 if (val == const0_rtx)
4377 emit_insn (gen_clrmem_short (dst, GEN_INT (255)));
4378 else
4379 emit_insn (gen_movmem_short (dstp1, dst, GEN_INT (255)));
f81e845f 4380 s390_load_address (dst_addr,
4fbc4db5 4381 gen_rtx_PLUS (Pmode, dst_addr, GEN_INT (256)));
f81e845f 4382
b9c74b4d 4383 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4384 OPTAB_DIRECT);
4fbc4db5 4385 if (temp != blocks)
4386 emit_move_insn (blocks, temp);
4387
4ee9c684 4388 emit_cmp_and_jump_insns (blocks, const0_rtx,
4389 EQ, NULL_RTX, mode, 1, loop_end_label);
7746964e 4390
4391 emit_jump (loop_start_label);
4ee9c684 4392 emit_label (loop_end_label);
4fbc4db5 4393
805a133b 4394 if (val == const0_rtx)
4395 emit_insn (gen_clrmem_short (dst, convert_to_mode (Pmode, count, 1)));
4396 else
4397 emit_insn (gen_movmem_short (dstp1, dst, convert_to_mode (Pmode, count, 1)));
4fbc4db5 4398 emit_label (end_label);
4399 }
4400}
4401
4402/* Emit code to compare LEN bytes at OP0 with those at OP1,
4403 and return the result in TARGET. */
4404
daa87e5a 4405bool
b40da9a7 4406s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
4fbc4db5 4407{
80b53886 4408 rtx ccreg = gen_rtx_REG (CCUmode, CC_REGNUM);
dd16a4bd 4409 rtx tmp;
4410
daa87e5a 4411 /* When tuning for z10 or higher we rely on the Glibc functions to
4412 do the right thing. Only for constant lengths below 64k we will
4413 generate inline code. */
4414 if (s390_tune >= PROCESSOR_2097_Z10
4415 && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
4416 return false;
4417
dd16a4bd 4418 /* As the result of CMPINT is inverted compared to what we need,
4419 we have to swap the operands. */
4420 tmp = op0; op0 = op1; op1 = tmp;
4fbc4db5 4421
4fbc4db5 4422 if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
4423 {
4424 if (INTVAL (len) > 0)
4425 {
31838f66 4426 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (INTVAL (len) - 1)));
dd16a4bd 4427 emit_insn (gen_cmpint (target, ccreg));
4fbc4db5 4428 }
4429 else
4430 emit_move_insn (target, const0_rtx);
4431 }
bcbf02a5 4432 else if (TARGET_MVCLE)
4fbc4db5 4433 {
31838f66 4434 emit_insn (gen_cmpmem_long (op0, op1, convert_to_mode (Pmode, len, 1)));
dd16a4bd 4435 emit_insn (gen_cmpint (target, ccreg));
4fbc4db5 4436 }
4fbc4db5 4437 else
4438 {
4439 rtx addr0, addr1, count, blocks, temp;
7746964e 4440 rtx loop_start_label = gen_label_rtx ();
4ee9c684 4441 rtx loop_end_label = gen_label_rtx ();
4fbc4db5 4442 rtx end_label = gen_label_rtx ();
4443 enum machine_mode mode;
4fbc4db5 4444
4445 mode = GET_MODE (len);
4446 if (mode == VOIDmode)
31838f66 4447 mode = Pmode;
4fbc4db5 4448
4fbc4db5 4449 addr0 = gen_reg_rtx (Pmode);
4450 addr1 = gen_reg_rtx (Pmode);
4451 count = gen_reg_rtx (mode);
4452 blocks = gen_reg_rtx (mode);
4453
4454 convert_move (count, len, 1);
f81e845f 4455 emit_cmp_and_jump_insns (count, const0_rtx,
4fbc4db5 4456 EQ, NULL_RTX, mode, 1, end_label);
4457
4458 emit_move_insn (addr0, force_operand (XEXP (op0, 0), NULL_RTX));
4459 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX));
4460 op0 = change_address (op0, VOIDmode, addr0);
4461 op1 = change_address (op1, VOIDmode, addr1);
f81e845f 4462
b9c74b4d 4463 temp = expand_binop (mode, add_optab, count, constm1_rtx, count, 1,
4464 OPTAB_DIRECT);
4fbc4db5 4465 if (temp != count)
4466 emit_move_insn (count, temp);
4467
b9c74b4d 4468 temp = expand_binop (mode, lshr_optab, count, GEN_INT (8), blocks, 1,
4469 OPTAB_DIRECT);
4fbc4db5 4470 if (temp != blocks)
4471 emit_move_insn (blocks, temp);
4472
4ee9c684 4473 emit_cmp_and_jump_insns (blocks, const0_rtx,
4474 EQ, NULL_RTX, mode, 1, loop_end_label);
7746964e 4475
4476 emit_label (loop_start_label);
4fbc4db5 4477
d5de7805 4478 if (TARGET_Z10
4479 && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
4480 {
4481 rtx prefetch;
4482
4483 /* Issue a read prefetch for the +2 cache line of operand 1. */
4484 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr0, GEN_INT (512)),
4485 const0_rtx, const0_rtx);
4486 emit_insn (prefetch);
4487 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4488
4489 /* Issue a read prefetch for the +2 cache line of operand 2. */
4490 prefetch = gen_prefetch (gen_rtx_PLUS (Pmode, addr1, GEN_INT (512)),
4491 const0_rtx, const0_rtx);
4492 emit_insn (prefetch);
4493 PREFETCH_SCHEDULE_BARRIER_P (prefetch) = true;
4494 }
4495
31838f66 4496 emit_insn (gen_cmpmem_short (op0, op1, GEN_INT (255)));
80b53886 4497 temp = gen_rtx_NE (VOIDmode, ccreg, const0_rtx);
f81e845f 4498 temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp,
4fbc4db5 4499 gen_rtx_LABEL_REF (VOIDmode, end_label), pc_rtx);
4500 temp = gen_rtx_SET (VOIDmode, pc_rtx, temp);
4501 emit_jump_insn (temp);
4502
f81e845f 4503 s390_load_address (addr0,
4fbc4db5 4504 gen_rtx_PLUS (Pmode, addr0, GEN_INT (256)));
f81e845f 4505 s390_load_address (addr1,
4fbc4db5 4506 gen_rtx_PLUS (Pmode, addr1, GEN_INT (256)));
f81e845f 4507
b9c74b4d 4508 temp = expand_binop (mode, add_optab, blocks, constm1_rtx, blocks, 1,
4509 OPTAB_DIRECT);
4fbc4db5 4510 if (temp != blocks)
4511 emit_move_insn (blocks, temp);
4512
4ee9c684 4513 emit_cmp_and_jump_insns (blocks, const0_rtx,
4514 EQ, NULL_RTX, mode, 1, loop_end_label);
7746964e 4515
4516 emit_jump (loop_start_label);
4ee9c684 4517 emit_label (loop_end_label);
4fbc4db5 4518
f588eb9f 4519 emit_insn (gen_cmpmem_short (op0, op1,
31838f66 4520 convert_to_mode (Pmode, count, 1)));
4fbc4db5 4521 emit_label (end_label);
4522
dd16a4bd 4523 emit_insn (gen_cmpint (target, ccreg));
4fbc4db5 4524 }
daa87e5a 4525 return true;
4fbc4db5 4526}
4527
3b699fc7 4528
4529/* Expand conditional increment or decrement using alc/slb instructions.
4530 Should generate code setting DST to either SRC or SRC + INCREMENT,
4531 depending on the result of the comparison CMP_OP0 CMP_CODE CMP_OP1.
eeba5f25 4532 Returns true if successful, false otherwise.
4533
4534 That makes it possible to implement some if-constructs without jumps e.g.:
4535 (borrow = CC0 | CC1 and carry = CC2 | CC3)
4536 unsigned int a, b, c;
4537 if (a < b) c++; -> CCU b > a -> CC2; c += carry;
4538 if (a < b) c--; -> CCL3 a - b -> borrow; c -= borrow;
4539 if (a <= b) c++; -> CCL3 b - a -> borrow; c += carry;
4540 if (a <= b) c--; -> CCU a <= b -> borrow; c -= borrow;
4541
4542 Checks for EQ and NE with a nonzero value need an additional xor e.g.:
4543 if (a == b) c++; -> CCL3 a ^= b; 0 - a -> borrow; c += carry;
4544 if (a == b) c--; -> CCU a ^= b; a <= 0 -> CC0 | CC1; c -= borrow;
4545 if (a != b) c++; -> CCU a ^= b; a > 0 -> CC2; c += carry;
4546 if (a != b) c--; -> CCL3 a ^= b; 0 - a -> borrow; c -= borrow; */
3b699fc7 4547
4548bool
4549s390_expand_addcc (enum rtx_code cmp_code, rtx cmp_op0, rtx cmp_op1,
4550 rtx dst, rtx src, rtx increment)
4551{
4552 enum machine_mode cmp_mode;
4553 enum machine_mode cc_mode;
4554 rtx op_res;
4555 rtx insn;
4556 rtvec p;
32eda510 4557 int ret;
3b699fc7 4558
4559 if ((GET_MODE (cmp_op0) == SImode || GET_MODE (cmp_op0) == VOIDmode)
4560 && (GET_MODE (cmp_op1) == SImode || GET_MODE (cmp_op1) == VOIDmode))
4561 cmp_mode = SImode;
4562 else if ((GET_MODE (cmp_op0) == DImode || GET_MODE (cmp_op0) == VOIDmode)
4563 && (GET_MODE (cmp_op1) == DImode || GET_MODE (cmp_op1) == VOIDmode))
4564 cmp_mode = DImode;
4565 else
4566 return false;
4567
4568 /* Try ADD LOGICAL WITH CARRY. */
4569 if (increment == const1_rtx)
4570 {
4571 /* Determine CC mode to use. */
4572 if (cmp_code == EQ || cmp_code == NE)
4573 {
4574 if (cmp_op1 != const0_rtx)
4575 {
4576 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4577 NULL_RTX, 0, OPTAB_WIDEN);
4578 cmp_op1 = const0_rtx;
4579 }
4580
4581 cmp_code = cmp_code == EQ ? LEU : GTU;
4582 }
4583
4584 if (cmp_code == LTU || cmp_code == LEU)
4585 {
4586 rtx tem = cmp_op0;
4587 cmp_op0 = cmp_op1;
4588 cmp_op1 = tem;
4589 cmp_code = swap_condition (cmp_code);
4590 }
4591
4592 switch (cmp_code)
4593 {
4594 case GTU:
4595 cc_mode = CCUmode;
4596 break;
4597
4598 case GEU:
4599 cc_mode = CCL3mode;
4600 break;
4601
4602 default:
4603 return false;
4604 }
4605
4606 /* Emit comparison instruction pattern. */
4607 if (!register_operand (cmp_op0, cmp_mode))
4608 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4609
4610 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4611 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4612 /* We use insn_invalid_p here to add clobbers if required. */
dae9d0e7 4613 ret = insn_invalid_p (emit_insn (insn), false);
32eda510 4614 gcc_assert (!ret);
3b699fc7 4615
4616 /* Emit ALC instruction pattern. */
4617 op_res = gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4618 gen_rtx_REG (cc_mode, CC_REGNUM),
4619 const0_rtx);
4620
4621 if (src != const0_rtx)
4622 {
4623 if (!register_operand (src, GET_MODE (dst)))
4624 src = force_reg (GET_MODE (dst), src);
4625
6f4afa7e 4626 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, src);
4627 op_res = gen_rtx_PLUS (GET_MODE (dst), op_res, const0_rtx);
3b699fc7 4628 }
4629
4630 p = rtvec_alloc (2);
ffead1ca 4631 RTVEC_ELT (p, 0) =
3b699fc7 4632 gen_rtx_SET (VOIDmode, dst, op_res);
ffead1ca 4633 RTVEC_ELT (p, 1) =
3b699fc7 4634 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4635 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4636
4637 return true;
4638 }
4639
4640 /* Try SUBTRACT LOGICAL WITH BORROW. */
4641 if (increment == constm1_rtx)
4642 {
4643 /* Determine CC mode to use. */
4644 if (cmp_code == EQ || cmp_code == NE)
4645 {
4646 if (cmp_op1 != const0_rtx)
4647 {
4648 cmp_op0 = expand_simple_binop (cmp_mode, XOR, cmp_op0, cmp_op1,
4649 NULL_RTX, 0, OPTAB_WIDEN);
4650 cmp_op1 = const0_rtx;
4651 }
4652
4653 cmp_code = cmp_code == EQ ? LEU : GTU;
4654 }
4655
4656 if (cmp_code == GTU || cmp_code == GEU)
4657 {
4658 rtx tem = cmp_op0;
4659 cmp_op0 = cmp_op1;
4660 cmp_op1 = tem;
4661 cmp_code = swap_condition (cmp_code);
4662 }
4663
4664 switch (cmp_code)
4665 {
4666 case LEU:
4667 cc_mode = CCUmode;
4668 break;
4669
4670 case LTU:
4671 cc_mode = CCL3mode;
4672 break;
4673
4674 default:
4675 return false;
4676 }
4677
4678 /* Emit comparison instruction pattern. */
4679 if (!register_operand (cmp_op0, cmp_mode))
4680 cmp_op0 = force_reg (cmp_mode, cmp_op0);
4681
4682 insn = gen_rtx_SET (VOIDmode, gen_rtx_REG (cc_mode, CC_REGNUM),
4683 gen_rtx_COMPARE (cc_mode, cmp_op0, cmp_op1));
4684 /* We use insn_invalid_p here to add clobbers if required. */
dae9d0e7 4685 ret = insn_invalid_p (emit_insn (insn), false);
32eda510 4686 gcc_assert (!ret);
3b699fc7 4687
4688 /* Emit SLB instruction pattern. */
4689 if (!register_operand (src, GET_MODE (dst)))
4690 src = force_reg (GET_MODE (dst), src);
4691
ffead1ca 4692 op_res = gen_rtx_MINUS (GET_MODE (dst),
4693 gen_rtx_MINUS (GET_MODE (dst), src, const0_rtx),
4694 gen_rtx_fmt_ee (cmp_code, GET_MODE (dst),
4695 gen_rtx_REG (cc_mode, CC_REGNUM),
3b699fc7 4696 const0_rtx));
4697 p = rtvec_alloc (2);
ffead1ca 4698 RTVEC_ELT (p, 0) =
3b699fc7 4699 gen_rtx_SET (VOIDmode, dst, op_res);
ffead1ca 4700 RTVEC_ELT (p, 1) =
3b699fc7 4701 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4702 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
4703
4704 return true;
4705 }
4706
4707 return false;
4708}
4709
e68d6a13 4710/* Expand code for the insv template. Return true if successful. */
0349cc73 4711
e68d6a13 4712bool
0349cc73 4713s390_expand_insv (rtx dest, rtx op1, rtx op2, rtx src)
4714{
4715 int bitsize = INTVAL (op1);
4716 int bitpos = INTVAL (op2);
8c753480 4717 enum machine_mode mode = GET_MODE (dest);
4718 enum machine_mode smode;
4719 int smode_bsize, mode_bsize;
4720 rtx op, clobber;
0349cc73 4721
31efd1ec 4722 if (bitsize + bitpos > GET_MODE_SIZE (mode))
4723 return false;
4724
8c753480 4725 /* Generate INSERT IMMEDIATE (IILL et al). */
4726 /* (set (ze (reg)) (const_int)). */
4727 if (TARGET_ZARCH
4728 && register_operand (dest, word_mode)
4729 && (bitpos % 16) == 0
4730 && (bitsize % 16) == 0
4731 && const_int_operand (src, VOIDmode))
e68d6a13 4732 {
8c753480 4733 HOST_WIDE_INT val = INTVAL (src);
4734 int regpos = bitpos + bitsize;
e68d6a13 4735
8c753480 4736 while (regpos > bitpos)
4737 {
4738 enum machine_mode putmode;
4739 int putsize;
4740
4741 if (TARGET_EXTIMM && (regpos % 32 == 0) && (regpos >= bitpos + 32))
4742 putmode = SImode;
4743 else
4744 putmode = HImode;
e68d6a13 4745
8c753480 4746 putsize = GET_MODE_BITSIZE (putmode);
4747 regpos -= putsize;
4748 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4749 GEN_INT (putsize),
4750 GEN_INT (regpos)),
4751 gen_int_mode (val, putmode));
4752 val >>= putsize;
4753 }
4754 gcc_assert (regpos == bitpos);
e68d6a13 4755 return true;
4756 }
4757
8c753480 4758 smode = smallest_mode_for_size (bitsize, MODE_INT);
4759 smode_bsize = GET_MODE_BITSIZE (smode);
4760 mode_bsize = GET_MODE_BITSIZE (mode);
0349cc73 4761
8c753480 4762 /* Generate STORE CHARACTERS UNDER MASK (STCM et al). */
0349cc73 4763 if (bitpos == 0
8c753480 4764 && (bitsize % BITS_PER_UNIT) == 0
4765 && MEM_P (dest)
0349cc73 4766 && (register_operand (src, word_mode)
4767 || const_int_operand (src, VOIDmode)))
4768 {
4769 /* Emit standard pattern if possible. */
8c753480 4770 if (smode_bsize == bitsize)
4771 {
4772 emit_move_insn (adjust_address (dest, smode, 0),
4773 gen_lowpart (smode, src));
4774 return true;
4775 }
0349cc73 4776
4777 /* (set (ze (mem)) (const_int)). */
4778 else if (const_int_operand (src, VOIDmode))
4779 {
4780 int size = bitsize / BITS_PER_UNIT;
8c753480 4781 rtx src_mem = adjust_address (force_const_mem (word_mode, src),
4782 BLKmode,
4783 UNITS_PER_WORD - size);
0349cc73 4784
4785 dest = adjust_address (dest, BLKmode, 0);
5b2a69fa 4786 set_mem_size (dest, size);
0349cc73 4787 s390_expand_movmem (dest, src_mem, GEN_INT (size));
8c753480 4788 return true;
0349cc73 4789 }
ffead1ca 4790
0349cc73 4791 /* (set (ze (mem)) (reg)). */
4792 else if (register_operand (src, word_mode))
4793 {
8c753480 4794 if (bitsize <= 32)
0349cc73 4795 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest, op1,
4796 const0_rtx), src);
4797 else
4798 {
4799 /* Emit st,stcmh sequence. */
8c753480 4800 int stcmh_width = bitsize - 32;
0349cc73 4801 int size = stcmh_width / BITS_PER_UNIT;
4802
ffead1ca 4803 emit_move_insn (adjust_address (dest, SImode, size),
0349cc73 4804 gen_lowpart (SImode, src));
5b2a69fa 4805 set_mem_size (dest, size);
8c753480 4806 emit_move_insn (gen_rtx_ZERO_EXTRACT (word_mode, dest,
4807 GEN_INT (stcmh_width),
4808 const0_rtx),
4809 gen_rtx_LSHIFTRT (word_mode, src, GEN_INT (32)));
0349cc73 4810 }
8c753480 4811 return true;
0349cc73 4812 }
8c753480 4813 }
0349cc73 4814
8c753480 4815 /* Generate INSERT CHARACTERS UNDER MASK (IC, ICM et al). */
4816 if ((bitpos % BITS_PER_UNIT) == 0
4817 && (bitsize % BITS_PER_UNIT) == 0
4818 && (bitpos & 32) == ((bitpos + bitsize - 1) & 32)
4819 && MEM_P (src)
4820 && (mode == DImode || mode == SImode)
4821 && register_operand (dest, mode))
4822 {
4823 /* Emit a strict_low_part pattern if possible. */
4824 if (smode_bsize == bitsize && bitpos == mode_bsize - smode_bsize)
4825 {
4826 op = gen_rtx_STRICT_LOW_PART (VOIDmode, gen_lowpart (smode, dest));
4827 op = gen_rtx_SET (VOIDmode, op, gen_lowpart (smode, src));
4828 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4829 emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber)));
4830 return true;
4831 }
4832
4833 /* ??? There are more powerful versions of ICM that are not
4834 completely represented in the md file. */
0349cc73 4835 }
4836
8c753480 4837 /* For z10, generate ROTATE THEN INSERT SELECTED BITS (RISBG et al). */
4838 if (TARGET_Z10 && (mode == DImode || mode == SImode))
0349cc73 4839 {
8c753480 4840 enum machine_mode mode_s = GET_MODE (src);
0349cc73 4841
8c753480 4842 if (mode_s == VOIDmode)
0349cc73 4843 {
8c753480 4844 /* Assume const_int etc already in the proper mode. */
4845 src = force_reg (mode, src);
4846 }
4847 else if (mode_s != mode)
4848 {
4849 gcc_assert (GET_MODE_BITSIZE (mode_s) >= bitsize);
4850 src = force_reg (mode_s, src);
4851 src = gen_lowpart (mode, src);
4852 }
0349cc73 4853
99274008 4854 op = gen_rtx_ZERO_EXTRACT (mode, dest, op1, op2),
4855 op = gen_rtx_SET (VOIDmode, op, src);
81769881 4856
4857 if (!TARGET_ZEC12)
4858 {
4859 clobber = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM));
4860 op = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, op, clobber));
4861 }
4862 emit_insn (op);
0349cc73 4863
0349cc73 4864 return true;
4865 }
4866
4867 return false;
4868}
3b699fc7 4869
7cc66daf 4870/* A subroutine of s390_expand_cs_hqi and s390_expand_atomic which returns a
4871 register that holds VAL of mode MODE shifted by COUNT bits. */
182f815e 4872
4873static inline rtx
4874s390_expand_mask_and_shift (rtx val, enum machine_mode mode, rtx count)
4875{
4876 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)),
4877 NULL_RTX, 1, OPTAB_DIRECT);
ffead1ca 4878 return expand_simple_binop (SImode, ASHIFT, val, count,
182f815e 4879 NULL_RTX, 1, OPTAB_DIRECT);
4880}
4881
4882/* Structure to hold the initial parameters for a compare_and_swap operation
ffead1ca 4883 in HImode and QImode. */
182f815e 4884
4885struct alignment_context
4886{
ffead1ca 4887 rtx memsi; /* SI aligned memory location. */
182f815e 4888 rtx shift; /* Bit offset with regard to lsb. */
4889 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */
4890 rtx modemaski; /* ~modemask */
191ec5a2 4891 bool aligned; /* True if memory is aligned, false else. */
182f815e 4892};
4893
7cc66daf 4894/* A subroutine of s390_expand_cs_hqi and s390_expand_atomic to initialize
4895 structure AC for transparent simplifying, if the memory alignment is known
4896 to be at least 32bit. MEM is the memory location for the actual operation
4897 and MODE its mode. */
182f815e 4898
4899static void
4900init_alignment_context (struct alignment_context *ac, rtx mem,
4901 enum machine_mode mode)
4902{
4903 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode));
4904 ac->aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode));
4905
4906 if (ac->aligned)
4907 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */
4908 else
4909 {
4910 /* Alignment is unknown. */
4911 rtx byteoffset, addr, align;
4912
4913 /* Force the address into a register. */
4914 addr = force_reg (Pmode, XEXP (mem, 0));
4915
4916 /* Align it to SImode. */
4917 align = expand_simple_binop (Pmode, AND, addr,
4918 GEN_INT (-GET_MODE_SIZE (SImode)),
4919 NULL_RTX, 1, OPTAB_DIRECT);
4920 /* Generate MEM. */
4921 ac->memsi = gen_rtx_MEM (SImode, align);
4922 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem);
bd1da572 4923 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER);
182f815e 4924 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode));
4925
4926 /* Calculate shiftcount. */
4927 byteoffset = expand_simple_binop (Pmode, AND, addr,
4928 GEN_INT (GET_MODE_SIZE (SImode) - 1),
4929 NULL_RTX, 1, OPTAB_DIRECT);
4930 /* As we already have some offset, evaluate the remaining distance. */
4931 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset,
4932 NULL_RTX, 1, OPTAB_DIRECT);
182f815e 4933 }
8c753480 4934
182f815e 4935 /* Shift is the byte count, but we need the bitcount. */
8c753480 4936 ac->shift = expand_simple_binop (SImode, ASHIFT, ac->shift, GEN_INT (3),
4937 NULL_RTX, 1, OPTAB_DIRECT);
4938
182f815e 4939 /* Calculate masks. */
ffead1ca 4940 ac->modemask = expand_simple_binop (SImode, ASHIFT,
8c753480 4941 GEN_INT (GET_MODE_MASK (mode)),
4942 ac->shift, NULL_RTX, 1, OPTAB_DIRECT);
4943 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask,
4944 NULL_RTX, 1);
4945}
4946
4947/* A subroutine of s390_expand_cs_hqi. Insert INS into VAL. If possible,
4948 use a single insv insn into SEQ2. Otherwise, put prep insns in SEQ1 and
4949 perform the merge in SEQ2. */
4950
4951static rtx
4952s390_two_part_insv (struct alignment_context *ac, rtx *seq1, rtx *seq2,
4953 enum machine_mode mode, rtx val, rtx ins)
4954{
4955 rtx tmp;
4956
4957 if (ac->aligned)
4958 {
4959 start_sequence ();
4960 tmp = copy_to_mode_reg (SImode, val);
4961 if (s390_expand_insv (tmp, GEN_INT (GET_MODE_BITSIZE (mode)),
4962 const0_rtx, ins))
4963 {
4964 *seq1 = NULL;
4965 *seq2 = get_insns ();
4966 end_sequence ();
4967 return tmp;
4968 }
4969 end_sequence ();
4970 }
4971
4972 /* Failed to use insv. Generate a two part shift and mask. */
4973 start_sequence ();
4974 tmp = s390_expand_mask_and_shift (ins, mode, ac->shift);
4975 *seq1 = get_insns ();
4976 end_sequence ();
4977
4978 start_sequence ();
4979 tmp = expand_simple_binop (SImode, IOR, tmp, val, NULL_RTX, 1, OPTAB_DIRECT);
4980 *seq2 = get_insns ();
4981 end_sequence ();
4982
4983 return tmp;
182f815e 4984}
4985
4986/* Expand an atomic compare and swap operation for HImode and QImode. MEM is
8c753480 4987 the memory location, CMP the old value to compare MEM with and NEW_RTX the
4988 value to set if CMP == MEM. */
182f815e 4989
4990void
8c753480 4991s390_expand_cs_hqi (enum machine_mode mode, rtx btarget, rtx vtarget, rtx mem,
4992 rtx cmp, rtx new_rtx, bool is_weak)
182f815e 4993{
4994 struct alignment_context ac;
77e58889 4995 rtx cmpv, newv, val, cc, seq0, seq1, seq2, seq3;
182f815e 4996 rtx res = gen_reg_rtx (SImode);
8c753480 4997 rtx csloop = NULL, csend = NULL;
182f815e 4998
182f815e 4999 gcc_assert (MEM_P (mem));
5000
5001 init_alignment_context (&ac, mem, mode);
5002
182f815e 5003 /* Load full word. Subsequent loads are performed by CS. */
5004 val = expand_simple_binop (SImode, AND, ac.memsi, ac.modemaski,
5005 NULL_RTX, 1, OPTAB_DIRECT);
5006
8c753480 5007 /* Prepare insertions of cmp and new_rtx into the loaded value. When
5008 possible, we try to use insv to make this happen efficiently. If
5009 that fails we'll generate code both inside and outside the loop. */
5010 cmpv = s390_two_part_insv (&ac, &seq0, &seq2, mode, val, cmp);
5011 newv = s390_two_part_insv (&ac, &seq1, &seq3, mode, val, new_rtx);
5012
5013 if (seq0)
5014 emit_insn (seq0);
5015 if (seq1)
5016 emit_insn (seq1);
5017
182f815e 5018 /* Start CS loop. */
8c753480 5019 if (!is_weak)
5020 {
5021 /* Begin assuming success. */
5022 emit_move_insn (btarget, const1_rtx);
5023
5024 csloop = gen_label_rtx ();
5025 csend = gen_label_rtx ();
5026 emit_label (csloop);
5027 }
5028
ffead1ca 5029 /* val = "<mem>00..0<mem>"
182f815e 5030 * cmp = "00..0<cmp>00..0"
ffead1ca 5031 * new = "00..0<new>00..0"
182f815e 5032 */
5033
8c753480 5034 emit_insn (seq2);
5035 emit_insn (seq3);
5036
5037 cc = s390_emit_compare_and_swap (EQ, res, ac.memsi, cmpv, newv);
5038 if (is_weak)
5039 emit_insn (gen_cstorecc4 (btarget, cc, XEXP (cc, 0), XEXP (cc, 1)));
182f815e 5040 else
182f815e 5041 {
77e58889 5042 rtx tmp;
5043
8c753480 5044 /* Jump to end if we're done (likely?). */
5045 s390_emit_jump (csend, cc);
5046
77e58889 5047 /* Check for changes outside mode, and loop internal if so.
5048 Arrange the moves so that the compare is adjacent to the
5049 branch so that we can generate CRJ. */
5050 tmp = copy_to_reg (val);
5051 force_expand_binop (SImode, and_optab, res, ac.modemaski, val,
5052 1, OPTAB_DIRECT);
5053 cc = s390_emit_compare (NE, val, tmp);
8c753480 5054 s390_emit_jump (csloop, cc);
5055
5056 /* Failed. */
5057 emit_move_insn (btarget, const0_rtx);
5058 emit_label (csend);
182f815e 5059 }
ffead1ca 5060
182f815e 5061 /* Return the correct part of the bitfield. */
8c753480 5062 convert_move (vtarget, expand_simple_binop (SImode, LSHIFTRT, res, ac.shift,
5063 NULL_RTX, 1, OPTAB_DIRECT), 1);
182f815e 5064}
5065
7cc66daf 5066/* Expand an atomic operation CODE of mode MODE. MEM is the memory location
85694bac 5067 and VAL the value to play with. If AFTER is true then store the value
7cc66daf 5068 MEM holds after the operation, if AFTER is false then store the value MEM
5069 holds before the operation. If TARGET is zero then discard that value, else
5070 store it to TARGET. */
5071
5072void
5073s390_expand_atomic (enum machine_mode mode, enum rtx_code code,
5074 rtx target, rtx mem, rtx val, bool after)
5075{
5076 struct alignment_context ac;
5077 rtx cmp;
8deb3959 5078 rtx new_rtx = gen_reg_rtx (SImode);
7cc66daf 5079 rtx orig = gen_reg_rtx (SImode);
5080 rtx csloop = gen_label_rtx ();
5081
5082 gcc_assert (!target || register_operand (target, VOIDmode));
5083 gcc_assert (MEM_P (mem));
5084
5085 init_alignment_context (&ac, mem, mode);
5086
5087 /* Shift val to the correct bit positions.
5088 Preserve "icm", but prevent "ex icm". */
5089 if (!(ac.aligned && code == SET && MEM_P (val)))
5090 val = s390_expand_mask_and_shift (val, mode, ac.shift);
5091
5092 /* Further preparation insns. */
5093 if (code == PLUS || code == MINUS)
5094 emit_move_insn (orig, val);
5095 else if (code == MULT || code == AND) /* val = "11..1<val>11..1" */
5096 val = expand_simple_binop (SImode, XOR, val, ac.modemaski,
5097 NULL_RTX, 1, OPTAB_DIRECT);
5098
5099 /* Load full word. Subsequent loads are performed by CS. */
5100 cmp = force_reg (SImode, ac.memsi);
5101
5102 /* Start CS loop. */
5103 emit_label (csloop);
8deb3959 5104 emit_move_insn (new_rtx, cmp);
7cc66daf 5105
5106 /* Patch new with val at correct position. */
5107 switch (code)
5108 {
5109 case PLUS:
5110 case MINUS:
8deb3959 5111 val = expand_simple_binop (SImode, code, new_rtx, orig,
7cc66daf 5112 NULL_RTX, 1, OPTAB_DIRECT);
5113 val = expand_simple_binop (SImode, AND, val, ac.modemask,
5114 NULL_RTX, 1, OPTAB_DIRECT);
5115 /* FALLTHRU */
ffead1ca 5116 case SET:
7cc66daf 5117 if (ac.aligned && MEM_P (val))
b634c730 5118 store_bit_field (new_rtx, GET_MODE_BITSIZE (mode), 0,
5119 0, 0, SImode, val);
7cc66daf 5120 else
5121 {
8deb3959 5122 new_rtx = expand_simple_binop (SImode, AND, new_rtx, ac.modemaski,
7cc66daf 5123 NULL_RTX, 1, OPTAB_DIRECT);
8deb3959 5124 new_rtx = expand_simple_binop (SImode, IOR, new_rtx, val,
7cc66daf 5125 NULL_RTX, 1, OPTAB_DIRECT);
5126 }
5127 break;
5128 case AND:
5129 case IOR:
5130 case XOR:
8deb3959 5131 new_rtx = expand_simple_binop (SImode, code, new_rtx, val,
7cc66daf 5132 NULL_RTX, 1, OPTAB_DIRECT);
5133 break;
5134 case MULT: /* NAND */
8deb3959 5135 new_rtx = expand_simple_binop (SImode, AND, new_rtx, val,
7cc66daf 5136 NULL_RTX, 1, OPTAB_DIRECT);
636c17b8 5137 new_rtx = expand_simple_binop (SImode, XOR, new_rtx, ac.modemask,
5138 NULL_RTX, 1, OPTAB_DIRECT);
7cc66daf 5139 break;
5140 default:
5141 gcc_unreachable ();
5142 }
7cc66daf 5143
db1f11e3 5144 s390_emit_jump (csloop, s390_emit_compare_and_swap (NE, cmp,
8deb3959 5145 ac.memsi, cmp, new_rtx));
7cc66daf 5146
5147 /* Return the correct part of the bitfield. */
5148 if (target)
5149 convert_move (target, expand_simple_binop (SImode, LSHIFTRT,
8deb3959 5150 after ? new_rtx : cmp, ac.shift,
7cc66daf 5151 NULL_RTX, 1, OPTAB_DIRECT), 1);
5152}
5153
40af64cc 5154/* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
03c118d5 5155 We need to emit DTP-relative relocations. */
5156
40af64cc 5157static void s390_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
5158
5159static void
b40da9a7 5160s390_output_dwarf_dtprel (FILE *file, int size, rtx x)
03c118d5 5161{
5162 switch (size)
5163 {
5164 case 4:
5165 fputs ("\t.long\t", file);
5166 break;
5167 case 8:
5168 fputs ("\t.quad\t", file);
5169 break;
5170 default:
32eda510 5171 gcc_unreachable ();
03c118d5 5172 }
5173 output_addr_const (file, x);
5174 fputs ("@DTPOFF", file);
5175}
5176
4257b08a 5177#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
eddcdde1 5178/* Implement TARGET_MANGLE_TYPE. */
4257b08a 5179
5180static const char *
a9f1838b 5181s390_mangle_type (const_tree type)
4257b08a 5182{
5183 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
5184 && TARGET_LONG_DOUBLE_128)
5185 return "g";
5186
5187 /* For all other types, use normal C++ mangling. */
5188 return NULL;
5189}
5190#endif
5191
e93986bb 5192/* In the name of slightly smaller debug output, and to cater to
06b27565 5193 general assembler lossage, recognize various UNSPEC sequences
e93986bb 5194 and turn them back into a direct symbol reference. */
5195
07576557 5196static rtx
b40da9a7 5197s390_delegitimize_address (rtx orig_x)
e93986bb 5198{
3b6b647c 5199 rtx x, y;
e93986bb 5200
3b6b647c 5201 orig_x = delegitimize_mem_from_attrs (orig_x);
5202 x = orig_x;
4796d433 5203
5204 /* Extract the symbol ref from:
5205 (plus:SI (reg:SI 12 %r12)
5206 (const:SI (unspec:SI [(symbol_ref/f:SI ("*.LC0"))]
2b2b857a 5207 UNSPEC_GOTOFF/PLTOFF)))
5208 and
5209 (plus:SI (reg:SI 12 %r12)
5210 (const:SI (plus:SI (unspec:SI [(symbol_ref:SI ("L"))]
5211 UNSPEC_GOTOFF/PLTOFF)
5212 (const_int 4 [0x4])))) */
4796d433 5213 if (GET_CODE (x) == PLUS
5214 && REG_P (XEXP (x, 0))
5215 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM
5216 && GET_CODE (XEXP (x, 1)) == CONST)
5217 {
b6382e93 5218 HOST_WIDE_INT offset = 0;
5219
4796d433 5220 /* The const operand. */
5221 y = XEXP (XEXP (x, 1), 0);
2b2b857a 5222
5223 if (GET_CODE (y) == PLUS
5224 && GET_CODE (XEXP (y, 1)) == CONST_INT)
b6382e93 5225 {
5226 offset = INTVAL (XEXP (y, 1));
5227 y = XEXP (y, 0);
5228 }
2b2b857a 5229
4796d433 5230 if (GET_CODE (y) == UNSPEC
2b2b857a 5231 && (XINT (y, 1) == UNSPEC_GOTOFF
5232 || XINT (y, 1) == UNSPEC_PLTOFF))
29c05e22 5233 return plus_constant (Pmode, XVECEXP (y, 0, 0), offset);
4796d433 5234 }
5235
e93986bb 5236 if (GET_CODE (x) != MEM)
5237 return orig_x;
5238
5239 x = XEXP (x, 0);
5240 if (GET_CODE (x) == PLUS
5241 && GET_CODE (XEXP (x, 1)) == CONST
5242 && GET_CODE (XEXP (x, 0)) == REG
5243 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
5244 {
5245 y = XEXP (XEXP (x, 1), 0);
5246 if (GET_CODE (y) == UNSPEC
12ef3745 5247 && XINT (y, 1) == UNSPEC_GOT)
54cb44a3 5248 y = XVECEXP (y, 0, 0);
5249 else
5250 return orig_x;
e93986bb 5251 }
54cb44a3 5252 else if (GET_CODE (x) == CONST)
e93986bb 5253 {
2b2b857a 5254 /* Extract the symbol ref from:
5255 (mem:QI (const:DI (unspec:DI [(symbol_ref:DI ("foo"))]
5256 UNSPEC_PLT/GOTENT))) */
5257
e93986bb 5258 y = XEXP (x, 0);
5259 if (GET_CODE (y) == UNSPEC
2b2b857a 5260 && (XINT (y, 1) == UNSPEC_GOTENT
5261 || XINT (y, 1) == UNSPEC_PLT))
54cb44a3 5262 y = XVECEXP (y, 0, 0);
5263 else
5264 return orig_x;
e93986bb 5265 }
54cb44a3 5266 else
5267 return orig_x;
e93986bb 5268
54cb44a3 5269 if (GET_MODE (orig_x) != Pmode)
5270 {
2b03de53 5271 if (GET_MODE (orig_x) == BLKmode)
5272 return orig_x;
54cb44a3 5273 y = lowpart_subreg (GET_MODE (orig_x), y, Pmode);
5274 if (y == NULL_RTX)
5275 return orig_x;
5276 }
5277 return y;
e93986bb 5278}
2eb8fe23 5279
805a133b 5280/* Output operand OP to stdio stream FILE.
5281 OP is an address (register + offset) which is not used to address data;
5282 instead the rightmost bits are interpreted as the value. */
63ebd742 5283
5284static void
5285print_shift_count_operand (FILE *file, rtx op)
5286{
6d6be381 5287 HOST_WIDE_INT offset;
5288 rtx base;
9a09ba70 5289
6d6be381 5290 /* Extract base register and offset. */
417cba42 5291 if (!s390_decompose_shift_count (op, &base, &offset))
6d6be381 5292 gcc_unreachable ();
63ebd742 5293
5294 /* Sanity check. */
6d6be381 5295 if (base)
32eda510 5296 {
6d6be381 5297 gcc_assert (GET_CODE (base) == REG);
5298 gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
5299 gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
32eda510 5300 }
63ebd742 5301
805a133b 5302 /* Offsets are constricted to twelve bits. */
5303 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset & ((1 << 12) - 1));
6d6be381 5304 if (base)
5305 fprintf (file, "(%s)", reg_names[REGNO (base)]);
63ebd742 5306}
5307
875862bf 5308/* See 'get_some_local_dynamic_name'. */
be00aaa8 5309
5310static int
b40da9a7 5311get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
be00aaa8 5312{
5313 rtx x = *px;
5314
5315 if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
5316 {
5317 x = get_pool_constant (x);
5318 return for_each_rtx (&x, get_some_local_dynamic_name_1, 0);
5319 }
5320
5321 if (GET_CODE (x) == SYMBOL_REF
5322 && tls_symbolic_operand (x) == TLS_MODEL_LOCAL_DYNAMIC)
5323 {
5324 cfun->machine->some_ld_name = XSTR (x, 0);
5325 return 1;
5326 }
5327
5328 return 0;
5329}
5330
875862bf 5331/* Locate some local-dynamic symbol still in use by this function
5332 so that we can print its name in local-dynamic base patterns. */
5333
5334static const char *
5335get_some_local_dynamic_name (void)
5336{
5337 rtx insn;
5338
5339 if (cfun->machine->some_ld_name)
5340 return cfun->machine->some_ld_name;
5341
5342 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
5343 if (INSN_P (insn)
5344 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
5345 return cfun->machine->some_ld_name;
5346
32eda510 5347 gcc_unreachable ();
875862bf 5348}
5349
f588eb9f 5350/* Output machine-dependent UNSPECs occurring in address constant X
74d2529d 5351 in assembler syntax to stdio stream FILE. Returns true if the
5352 constant X could be recognized, false otherwise. */
4673c1a0 5353
1a561788 5354static bool
74d2529d 5355s390_output_addr_const_extra (FILE *file, rtx x)
4673c1a0 5356{
74d2529d 5357 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1)
5358 switch (XINT (x, 1))
5359 {
5360 case UNSPEC_GOTENT:
5361 output_addr_const (file, XVECEXP (x, 0, 0));
5362 fprintf (file, "@GOTENT");
5363 return true;
5364 case UNSPEC_GOT:
5365 output_addr_const (file, XVECEXP (x, 0, 0));
5366 fprintf (file, "@GOT");
5367 return true;
5368 case UNSPEC_GOTOFF:
5369 output_addr_const (file, XVECEXP (x, 0, 0));
5370 fprintf (file, "@GOTOFF");
5371 return true;
5372 case UNSPEC_PLT:
5373 output_addr_const (file, XVECEXP (x, 0, 0));
5374 fprintf (file, "@PLT");
5375 return true;
5376 case UNSPEC_PLTOFF:
5377 output_addr_const (file, XVECEXP (x, 0, 0));
5378 fprintf (file, "@PLTOFF");
5379 return true;
5380 case UNSPEC_TLSGD:
5381 output_addr_const (file, XVECEXP (x, 0, 0));
5382 fprintf (file, "@TLSGD");
5383 return true;
5384 case UNSPEC_TLSLDM:
5385 assemble_name (file, get_some_local_dynamic_name ());
5386 fprintf (file, "@TLSLDM");
5387 return true;
5388 case UNSPEC_DTPOFF:
5389 output_addr_const (file, XVECEXP (x, 0, 0));
5390 fprintf (file, "@DTPOFF");
5391 return true;
5392 case UNSPEC_NTPOFF:
5393 output_addr_const (file, XVECEXP (x, 0, 0));
5394 fprintf (file, "@NTPOFF");
5395 return true;
5396 case UNSPEC_GOTNTPOFF:
5397 output_addr_const (file, XVECEXP (x, 0, 0));
5398 fprintf (file, "@GOTNTPOFF");
5399 return true;
5400 case UNSPEC_INDNTPOFF:
5401 output_addr_const (file, XVECEXP (x, 0, 0));
5402 fprintf (file, "@INDNTPOFF");
5403 return true;
5404 }
4673c1a0 5405
1ed7a160 5406 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 2)
5407 switch (XINT (x, 1))
5408 {
5409 case UNSPEC_POOL_OFFSET:
5410 x = gen_rtx_MINUS (GET_MODE (x), XVECEXP (x, 0, 0), XVECEXP (x, 0, 1));
5411 output_addr_const (file, x);
5412 return true;
5413 }
74d2529d 5414 return false;
4673c1a0 5415}
5416
f81e845f 5417/* Output address operand ADDR in assembler syntax to
56769981 5418 stdio stream FILE. */
4673c1a0 5419
5420void
b40da9a7 5421print_operand_address (FILE *file, rtx addr)
4673c1a0 5422{
5423 struct s390_address ad;
5424
2a672556 5425 if (s390_loadrelative_operand_p (addr, NULL, NULL))
e68d6a13 5426 {
53b9033c 5427 if (!TARGET_Z10)
5428 {
902602ef 5429 output_operand_lossage ("symbolic memory references are "
5430 "only supported on z10 or later");
53b9033c 5431 return;
5432 }
e68d6a13 5433 output_addr_const (file, addr);
5434 return;
5435 }
5436
8ba34dcd 5437 if (!s390_decompose_address (addr, &ad)
1e280623 5438 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5439 || (ad.indx && !REGNO_OK_FOR_INDEX_P (REGNO (ad.indx))))
3284a242 5440 output_operand_lossage ("cannot decompose address");
f81e845f 5441
4673c1a0 5442 if (ad.disp)
74d2529d 5443 output_addr_const (file, ad.disp);
4673c1a0 5444 else
5445 fprintf (file, "0");
5446
5447 if (ad.base && ad.indx)
5448 fprintf (file, "(%s,%s)", reg_names[REGNO (ad.indx)],
5449 reg_names[REGNO (ad.base)]);
5450 else if (ad.base)
5451 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5452}
5453
f81e845f 5454/* Output operand X in assembler syntax to stdio stream FILE.
5455 CODE specified the format flag. The following format flags
56769981 5456 are recognized:
5457
5458 'C': print opcode suffix for branch condition.
5459 'D': print opcode suffix for inverse branch condition.
f1443d23 5460 'E': print opcode suffix for branch on index instruction.
cc87d0c5 5461 'G': print the size of the operand in bytes.
0d46035f 5462 'J': print tls_load/tls_gdcall/tls_ldcall suffix
5463 'M': print the second word of a TImode operand.
5464 'N': print the second word of a DImode operand.
56769981 5465 'O': print only the displacement of a memory reference.
5466 'R': print only the base register of a memory reference.
0574acbe 5467 'S': print S-type memory reference (base+displacement).
63ebd742 5468 'Y': print shift count operand.
56769981 5469
45981c0a 5470 'b': print integer X as if it's an unsigned byte.
e68d6a13 5471 'c': print integer X as if it's an signed byte.
0d46035f 5472 'e': "end" of DImode contiguous bitmask X.
5473 'f': "end" of SImode contiguous bitmask X.
b9059d39 5474 'h': print integer X as if it's a signed halfword.
64a1078f 5475 'i': print the first nonzero HImode part of X.
b9059d39 5476 'j': print the first HImode part unequal to -1 of X.
5477 'k': print the first nonzero SImode part of X.
5478 'm': print the first SImode part unequal to -1 of X.
0d46035f 5479 'o': print integer X as if it's an unsigned 32bit word.
5480 's': "start" of DImode contiguous bitmask X.
5481 't': "start" of SImode contiguous bitmask X.
5482 'x': print integer X as if it's an unsigned halfword.
5483*/
4673c1a0 5484
5485void
b40da9a7 5486print_operand (FILE *file, rtx x, int code)
4673c1a0 5487{
0d46035f 5488 HOST_WIDE_INT ival;
5489
4673c1a0 5490 switch (code)
5491 {
5492 case 'C':
2eb8fe23 5493 fprintf (file, s390_branch_condition_mnemonic (x, FALSE));
4673c1a0 5494 return;
5495
5496 case 'D':
2eb8fe23 5497 fprintf (file, s390_branch_condition_mnemonic (x, TRUE));
4673c1a0 5498 return;
5499
f1443d23 5500 case 'E':
5501 if (GET_CODE (x) == LE)
5502 fprintf (file, "l");
5503 else if (GET_CODE (x) == GT)
5504 fprintf (file, "h");
5505 else
902602ef 5506 output_operand_lossage ("invalid comparison operator "
5507 "for 'E' output modifier");
f1443d23 5508 return;
5509
be00aaa8 5510 case 'J':
5511 if (GET_CODE (x) == SYMBOL_REF)
5512 {
5513 fprintf (file, "%s", ":tls_load:");
5514 output_addr_const (file, x);
5515 }
5516 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSGD)
5517 {
5518 fprintf (file, "%s", ":tls_gdcall:");
5519 output_addr_const (file, XVECEXP (x, 0, 0));
5520 }
5521 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLSLDM)
5522 {
5523 fprintf (file, "%s", ":tls_ldcall:");
5524 assemble_name (file, get_some_local_dynamic_name ());
5525 }
5526 else
902602ef 5527 output_operand_lossage ("invalid reference for 'J' output modifier");
be00aaa8 5528 return;
5529
cc87d0c5 5530 case 'G':
5531 fprintf (file, "%u", GET_MODE_SIZE (GET_MODE (x)));
5532 return;
5533
4673c1a0 5534 case 'O':
5535 {
5536 struct s390_address ad;
32eda510 5537 int ret;
4673c1a0 5538
53b9033c 5539 if (!MEM_P (x))
5540 {
902602ef 5541 output_operand_lossage ("memory reference expected for "
5542 "'O' output modifier");
53b9033c 5543 return;
5544 }
5545
32eda510 5546 ret = s390_decompose_address (XEXP (x, 0), &ad);
53b9033c 5547
5548 if (!ret
5549 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5550 || ad.indx)
5551 {
902602ef 5552 output_operand_lossage ("invalid address for 'O' output modifier");
53b9033c 5553 return;
5554 }
4673c1a0 5555
5556 if (ad.disp)
74d2529d 5557 output_addr_const (file, ad.disp);
4673c1a0 5558 else
5559 fprintf (file, "0");
5560 }
5561 return;
5562
5563 case 'R':
5564 {
5565 struct s390_address ad;
32eda510 5566 int ret;
4673c1a0 5567
53b9033c 5568 if (!MEM_P (x))
5569 {
902602ef 5570 output_operand_lossage ("memory reference expected for "
5571 "'R' output modifier");
53b9033c 5572 return;
5573 }
5574
32eda510 5575 ret = s390_decompose_address (XEXP (x, 0), &ad);
53b9033c 5576
5577 if (!ret
5578 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5579 || ad.indx)
5580 {
902602ef 5581 output_operand_lossage ("invalid address for 'R' output modifier");
53b9033c 5582 return;
5583 }
4673c1a0 5584
5585 if (ad.base)
5586 fprintf (file, "%s", reg_names[REGNO (ad.base)]);
5587 else
5588 fprintf (file, "0");
5589 }
5590 return;
5591
0574acbe 5592 case 'S':
5593 {
5594 struct s390_address ad;
32eda510 5595 int ret;
0574acbe 5596
53b9033c 5597 if (!MEM_P (x))
5598 {
902602ef 5599 output_operand_lossage ("memory reference expected for "
5600 "'S' output modifier");
53b9033c 5601 return;
5602 }
32eda510 5603 ret = s390_decompose_address (XEXP (x, 0), &ad);
53b9033c 5604
5605 if (!ret
5606 || (ad.base && !REGNO_OK_FOR_BASE_P (REGNO (ad.base)))
5607 || ad.indx)
5608 {
902602ef 5609 output_operand_lossage ("invalid address for 'S' output modifier");
53b9033c 5610 return;
5611 }
0574acbe 5612
5613 if (ad.disp)
5614 output_addr_const (file, ad.disp);
5615 else
5616 fprintf (file, "0");
5617
5618 if (ad.base)
5619 fprintf (file, "(%s)", reg_names[REGNO (ad.base)]);
5620 }
5621 return;
5622
4673c1a0 5623 case 'N':
5624 if (GET_CODE (x) == REG)
5625 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5626 else if (GET_CODE (x) == MEM)
29c05e22 5627 x = change_address (x, VOIDmode,
5628 plus_constant (Pmode, XEXP (x, 0), 4));
4673c1a0 5629 else
902602ef 5630 output_operand_lossage ("register or memory expression expected "
5631 "for 'N' output modifier");
4673c1a0 5632 break;
5633
5634 case 'M':
5635 if (GET_CODE (x) == REG)
5636 x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
5637 else if (GET_CODE (x) == MEM)
29c05e22 5638 x = change_address (x, VOIDmode,
5639 plus_constant (Pmode, XEXP (x, 0), 8));
4673c1a0 5640 else
902602ef 5641 output_operand_lossage ("register or memory expression expected "
5642 "for 'M' output modifier");
4673c1a0 5643 break;
63ebd742 5644
5645 case 'Y':
5646 print_shift_count_operand (file, x);
5647 return;
4673c1a0 5648 }
5649
5650 switch (GET_CODE (x))
5651 {
5652 case REG:
5653 fprintf (file, "%s", reg_names[REGNO (x)]);
5654 break;
5655
5656 case MEM:
5657 output_address (XEXP (x, 0));
5658 break;
5659
5660 case CONST:
5661 case CODE_LABEL:
5662 case LABEL_REF:
5663 case SYMBOL_REF:
74d2529d 5664 output_addr_const (file, x);
4673c1a0 5665 break;
5666
5667 case CONST_INT:
0d46035f 5668 ival = INTVAL (x);
5669 switch (code)
5670 {
5671 case 0:
5672 break;
5673 case 'b':
5674 ival &= 0xff;
5675 break;
5676 case 'c':
5677 ival = ((ival & 0xff) ^ 0x80) - 0x80;
5678 break;
5679 case 'x':
5680 ival &= 0xffff;
5681 break;
5682 case 'h':
5683 ival = ((ival & 0xffff) ^ 0x8000) - 0x8000;
5684 break;
5685 case 'i':
5686 ival = s390_extract_part (x, HImode, 0);
5687 break;
5688 case 'j':
5689 ival = s390_extract_part (x, HImode, -1);
5690 break;
5691 case 'k':
5692 ival = s390_extract_part (x, SImode, 0);
5693 break;
5694 case 'm':
5695 ival = s390_extract_part (x, SImode, -1);
5696 break;
5697 case 'o':
5698 ival &= 0xffffffff;
5699 break;
5700 case 'e': case 'f':
5701 case 's': case 't':
5702 {
5703 int pos, len;
5704 bool ok;
5705
5706 len = (code == 's' || code == 'e' ? 64 : 32);
5707 ok = s390_contiguous_bitmask_p (ival, len, &pos, &len);
5708 gcc_assert (ok);
5709 if (code == 's' || code == 't')
5710 ival = 64 - pos - len;
5711 else
5712 ival = 64 - 1 - pos;
5713 }
5714 break;
5715 default:
5716 output_operand_lossage ("invalid constant for output modifier '%c'", code);
5717 }
5718 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ival);
8b4a4127 5719 break;
5720
5721 case CONST_DOUBLE:
32eda510 5722 gcc_assert (GET_MODE (x) == VOIDmode);
8b4a4127 5723 if (code == 'b')
5724 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xff);
4673c1a0 5725 else if (code == 'x')
8b4a4127 5726 fprintf (file, HOST_WIDE_INT_PRINT_DEC, CONST_DOUBLE_LOW (x) & 0xffff);
4673c1a0 5727 else if (code == 'h')
902602ef 5728 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
5729 ((CONST_DOUBLE_LOW (x) & 0xffff) ^ 0x8000) - 0x8000);
4673c1a0 5730 else
53b9033c 5731 {
5732 if (code == 0)
902602ef 5733 output_operand_lossage ("invalid constant - try using "
5734 "an output modifier");
53b9033c 5735 else
902602ef 5736 output_operand_lossage ("invalid constant for output modifier '%c'",
5737 code);
53b9033c 5738 }
4673c1a0 5739 break;
5740
5741 default:
53b9033c 5742 if (code == 0)
902602ef 5743 output_operand_lossage ("invalid expression - try using "
5744 "an output modifier");
53b9033c 5745 else
902602ef 5746 output_operand_lossage ("invalid expression for output "
5747 "modifier '%c'", code);
4673c1a0 5748 break;
5749 }
5750}
5751
58356836 5752/* Target hook for assembling integer objects. We need to define it
5753 here to work a round a bug in some versions of GAS, which couldn't
5754 handle values smaller than INT_MIN when printed in decimal. */
5755
5756static bool
b40da9a7 5757s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
58356836 5758{
5759 if (size == 8 && aligned_p
5760 && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
5761 {
4840a03a 5762 fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
5763 INTVAL (x));
58356836 5764 return true;
5765 }
5766 return default_assemble_integer (x, size, aligned_p);
5767}
5768
f81e845f 5769/* Returns true if register REGNO is used for forming
56769981 5770 a memory address in expression X. */
4673c1a0 5771
e5537457 5772static bool
b40da9a7 5773reg_used_in_mem_p (int regno, rtx x)
4673c1a0 5774{
5775 enum rtx_code code = GET_CODE (x);
5776 int i, j;
5777 const char *fmt;
f81e845f 5778
4673c1a0 5779 if (code == MEM)
5780 {
5781 if (refers_to_regno_p (regno, regno+1,
5782 XEXP (x, 0), 0))
e5537457 5783 return true;
4673c1a0 5784 }
f81e845f 5785 else if (code == SET
8b4a4127 5786 && GET_CODE (SET_DEST (x)) == PC)
5787 {
5788 if (refers_to_regno_p (regno, regno+1,
5789 SET_SRC (x), 0))
e5537457 5790 return true;
8b4a4127 5791 }
4673c1a0 5792
5793 fmt = GET_RTX_FORMAT (code);
5794 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5795 {
5796 if (fmt[i] == 'e'
5797 && reg_used_in_mem_p (regno, XEXP (x, i)))
e5537457 5798 return true;
f81e845f 5799
4673c1a0 5800 else if (fmt[i] == 'E')
5801 for (j = 0; j < XVECLEN (x, i); j++)
5802 if (reg_used_in_mem_p (regno, XVECEXP (x, i, j)))
e5537457 5803 return true;
4673c1a0 5804 }
e5537457 5805 return false;
4673c1a0 5806}
5807
0c034860 5808/* Returns true if expression DEP_RTX sets an address register
56769981 5809 used by instruction INSN to address memory. */
4673c1a0 5810
e5537457 5811static bool
b40da9a7 5812addr_generation_dependency_p (rtx dep_rtx, rtx insn)
4673c1a0 5813{
8b4a4127 5814 rtx target, pat;
4673c1a0 5815
aa90bb35 5816 if (NONJUMP_INSN_P (dep_rtx))
77985f1a 5817 dep_rtx = PATTERN (dep_rtx);
71343e6b 5818
4673c1a0 5819 if (GET_CODE (dep_rtx) == SET)
5820 {
5821 target = SET_DEST (dep_rtx);
147b6a2d 5822 if (GET_CODE (target) == STRICT_LOW_PART)
5823 target = XEXP (target, 0);
5824 while (GET_CODE (target) == SUBREG)
5825 target = SUBREG_REG (target);
5826
4673c1a0 5827 if (GET_CODE (target) == REG)
5828 {
5829 int regno = REGNO (target);
5830
71343e6b 5831 if (s390_safe_attr_type (insn) == TYPE_LA)
8b4a4127 5832 {
5833 pat = PATTERN (insn);
5834 if (GET_CODE (pat) == PARALLEL)
5835 {
32eda510 5836 gcc_assert (XVECLEN (pat, 0) == 2);
8b4a4127 5837 pat = XVECEXP (pat, 0, 0);
5838 }
32eda510 5839 gcc_assert (GET_CODE (pat) == SET);
5840 return refers_to_regno_p (regno, regno+1, SET_SRC (pat), 0);
8b4a4127 5841 }
71343e6b 5842 else if (get_attr_atype (insn) == ATYPE_AGEN)
8b4a4127 5843 return reg_used_in_mem_p (regno, PATTERN (insn));
5844 }
4673c1a0 5845 }
e5537457 5846 return false;
4673c1a0 5847}
5848
71343e6b 5849/* Return 1, if dep_insn sets register used in insn in the agen unit. */
5850
f81e845f 5851int
b40da9a7 5852s390_agen_dep_p (rtx dep_insn, rtx insn)
f81e845f 5853{
71343e6b 5854 rtx dep_rtx = PATTERN (dep_insn);
5855 int i;
f81e845f 5856
5857 if (GET_CODE (dep_rtx) == SET
71343e6b 5858 && addr_generation_dependency_p (dep_rtx, insn))
5859 return 1;
5860 else if (GET_CODE (dep_rtx) == PARALLEL)
5861 {
5862 for (i = 0; i < XVECLEN (dep_rtx, 0); i++)
5863 {
5864 if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn))
5865 return 1;
5866 }
5867 }
5868 return 0;
5869}
5870
510c2327 5871
e51ae8ff 5872/* A C statement (sans semicolon) to update the integer scheduling priority
5873 INSN_PRIORITY (INSN). Increase the priority to execute the INSN earlier,
5874 reduce the priority to execute INSN later. Do not define this macro if
f81e845f 5875 you do not need to adjust the scheduling priorities of insns.
e51ae8ff 5876
f81e845f 5877 A STD instruction should be scheduled earlier,
e51ae8ff 5878 in order to use the bypass. */
e51ae8ff 5879static int
b40da9a7 5880s390_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
e51ae8ff 5881{
5882 if (! INSN_P (insn))
5883 return priority;
5884
163277cf 5885 if (s390_tune != PROCESSOR_2084_Z990
b0eacf26 5886 && s390_tune != PROCESSOR_2094_Z9_109
33d033da 5887 && s390_tune != PROCESSOR_2097_Z10
81769881 5888 && s390_tune != PROCESSOR_2817_Z196
5889 && s390_tune != PROCESSOR_2827_ZEC12)
e51ae8ff 5890 return priority;
5891
5892 switch (s390_safe_attr_type (insn))
5893 {
11f88fec 5894 case TYPE_FSTOREDF:
5895 case TYPE_FSTORESF:
e51ae8ff 5896 priority = priority << 3;
5897 break;
5898 case TYPE_STORE:
76dbb8df 5899 case TYPE_STM:
e51ae8ff 5900 priority = priority << 1;
5901 break;
5902 default:
5903 break;
5904 }
5905 return priority;
5906}
369293ed 5907
b0eacf26 5908
71343e6b 5909/* The number of instructions that can be issued per cycle. */
369293ed 5910
71343e6b 5911static int
b40da9a7 5912s390_issue_rate (void)
71343e6b 5913{
a850370e 5914 switch (s390_tune)
5915 {
5916 case PROCESSOR_2084_Z990:
5917 case PROCESSOR_2094_Z9_109:
33d033da 5918 case PROCESSOR_2817_Z196:
a850370e 5919 return 3;
5920 case PROCESSOR_2097_Z10:
81769881 5921 case PROCESSOR_2827_ZEC12:
a850370e 5922 return 2;
5923 default:
5924 return 1;
5925 }
71343e6b 5926}
369293ed 5927
e51ae8ff 5928static int
b40da9a7 5929s390_first_cycle_multipass_dfa_lookahead (void)
e51ae8ff 5930{
a65ea517 5931 return 4;
e51ae8ff 5932}
5933
20074f87 5934/* Annotate every literal pool reference in X by an UNSPEC_LTREF expression.
5935 Fix up MEMs as required. */
5936
5937static void
5938annotate_constant_pool_refs (rtx *x)
5939{
5940 int i, j;
5941 const char *fmt;
5942
32eda510 5943 gcc_assert (GET_CODE (*x) != SYMBOL_REF
5944 || !CONSTANT_POOL_ADDRESS_P (*x));
20074f87 5945
5946 /* Literal pool references can only occur inside a MEM ... */
5947 if (GET_CODE (*x) == MEM)
5948 {
5949 rtx memref = XEXP (*x, 0);
5950
5951 if (GET_CODE (memref) == SYMBOL_REF
5952 && CONSTANT_POOL_ADDRESS_P (memref))
5953 {
5954 rtx base = cfun->machine->base_reg;
5955 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, memref, base),
5956 UNSPEC_LTREF);
5957
5958 *x = replace_equiv_address (*x, addr);
5959 return;
5960 }
5961
5962 if (GET_CODE (memref) == CONST
5963 && GET_CODE (XEXP (memref, 0)) == PLUS
5964 && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
5965 && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
5966 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
5967 {
5968 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
5969 rtx sym = XEXP (XEXP (memref, 0), 0);
5970 rtx base = cfun->machine->base_reg;
5971 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
5972 UNSPEC_LTREF);
5973
29c05e22 5974 *x = replace_equiv_address (*x, plus_constant (Pmode, addr, off));
20074f87 5975 return;
5976 }
5977 }
5978
5979 /* ... or a load-address type pattern. */
5980 if (GET_CODE (*x) == SET)
5981 {
5982 rtx addrref = SET_SRC (*x);
5983
5984 if (GET_CODE (addrref) == SYMBOL_REF
5985 && CONSTANT_POOL_ADDRESS_P (addrref))
5986 {
5987 rtx base = cfun->machine->base_reg;
5988 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, addrref, base),
5989 UNSPEC_LTREF);
5990
5991 SET_SRC (*x) = addr;
5992 return;
5993 }
5994
5995 if (GET_CODE (addrref) == CONST
5996 && GET_CODE (XEXP (addrref, 0)) == PLUS
5997 && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
5998 && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
5999 && CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
6000 {
6001 HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
6002 rtx sym = XEXP (XEXP (addrref, 0), 0);
6003 rtx base = cfun->machine->base_reg;
6004 rtx addr = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, sym, base),
6005 UNSPEC_LTREF);
6006
29c05e22 6007 SET_SRC (*x) = plus_constant (Pmode, addr, off);
20074f87 6008 return;
6009 }
6010 }
6011
6012 /* Annotate LTREL_BASE as well. */
6013 if (GET_CODE (*x) == UNSPEC
6014 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
6015 {
6016 rtx base = cfun->machine->base_reg;
6017 *x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XVECEXP (*x, 0, 0), base),
6018 UNSPEC_LTREL_BASE);
6019 return;
6020 }
6021
6022 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6023 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6024 {
6025 if (fmt[i] == 'e')
6026 {
6027 annotate_constant_pool_refs (&XEXP (*x, i));
6028 }
6029 else if (fmt[i] == 'E')
6030 {
6031 for (j = 0; j < XVECLEN (*x, i); j++)
6032 annotate_constant_pool_refs (&XVECEXP (*x, i, j));
6033 }
6034 }
6035}
6036
875862bf 6037/* Split all branches that exceed the maximum distance.
6038 Returns true if this created a new literal pool entry. */
6039
6040static int
6041s390_split_branches (void)
6042{
6043 rtx temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
32eda510 6044 int new_literal = 0, ret;
875862bf 6045 rtx insn, pat, tmp, target;
6046 rtx *label;
6047
6048 /* We need correct insn addresses. */
6049
6050 shorten_branches (get_insns ());
6051
6052 /* Find all branches that exceed 64KB, and split them. */
6053
6054 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6055 {
245402e7 6056 if (! JUMP_P (insn) || tablejump_p (insn, NULL, NULL))
875862bf 6057 continue;
6058
6059 pat = PATTERN (insn);
245402e7 6060 if (GET_CODE (pat) == PARALLEL)
875862bf 6061 pat = XVECEXP (pat, 0, 0);
6062 if (GET_CODE (pat) != SET || SET_DEST (pat) != pc_rtx)
6063 continue;
6064
6065 if (GET_CODE (SET_SRC (pat)) == LABEL_REF)
6066 {
6067 label = &SET_SRC (pat);
6068 }
6069 else if (GET_CODE (SET_SRC (pat)) == IF_THEN_ELSE)
6070 {
6071 if (GET_CODE (XEXP (SET_SRC (pat), 1)) == LABEL_REF)
6072 label = &XEXP (SET_SRC (pat), 1);
6073 else if (GET_CODE (XEXP (SET_SRC (pat), 2)) == LABEL_REF)
6074 label = &XEXP (SET_SRC (pat), 2);
6075 else
6076 continue;
6077 }
6078 else
6079 continue;
6080
6081 if (get_attr_length (insn) <= 4)
6082 continue;
6083
77beec48 6084 /* We are going to use the return register as scratch register,
6085 make sure it will be saved/restored by the prologue/epilogue. */
6086 cfun_frame_layout.save_return_addr_p = 1;
6087
875862bf 6088 if (!flag_pic)
6089 {
6090 new_literal = 1;
6091 tmp = force_const_mem (Pmode, *label);
6092 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, tmp), insn);
6093 INSN_ADDRESSES_NEW (tmp, -1);
6094 annotate_constant_pool_refs (&PATTERN (tmp));
6095
6096 target = temp_reg;
6097 }
6098 else
6099 {
6100 new_literal = 1;
6101 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, *label),
6102 UNSPEC_LTREL_OFFSET);
6103 target = gen_rtx_CONST (Pmode, target);
6104 target = force_const_mem (Pmode, target);
6105 tmp = emit_insn_before (gen_rtx_SET (Pmode, temp_reg, target), insn);
6106 INSN_ADDRESSES_NEW (tmp, -1);
6107 annotate_constant_pool_refs (&PATTERN (tmp));
6108
6109 target = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, XEXP (target, 0),
6110 cfun->machine->base_reg),
6111 UNSPEC_LTREL_BASE);
6112 target = gen_rtx_PLUS (Pmode, temp_reg, target);
6113 }
6114
32eda510 6115 ret = validate_change (insn, label, target, 0);
6116 gcc_assert (ret);
875862bf 6117 }
6118
6119 return new_literal;
6120}
6121
0756cebb 6122
ffead1ca 6123/* Find an annotated literal pool symbol referenced in RTX X,
6124 and store it at REF. Will abort if X contains references to
20074f87 6125 more than one such pool symbol; multiple references to the same
6126 symbol are allowed, however.
0756cebb 6127
f81e845f 6128 The rtx pointed to by REF must be initialized to NULL_RTX
0756cebb 6129 by the caller before calling this routine. */
6130
6131static void
b40da9a7 6132find_constant_pool_ref (rtx x, rtx *ref)
0756cebb 6133{
6134 int i, j;
6135 const char *fmt;
6136
12ef3745 6137 /* Ignore LTREL_BASE references. */
6138 if (GET_CODE (x) == UNSPEC
6139 && XINT (x, 1) == UNSPEC_LTREL_BASE)
6140 return;
c2c1332a 6141 /* Likewise POOL_ENTRY insns. */
6142 if (GET_CODE (x) == UNSPEC_VOLATILE
6143 && XINT (x, 1) == UNSPECV_POOL_ENTRY)
6144 return;
12ef3745 6145
32eda510 6146 gcc_assert (GET_CODE (x) != SYMBOL_REF
6147 || !CONSTANT_POOL_ADDRESS_P (x));
20074f87 6148
6149 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
0756cebb 6150 {
20074f87 6151 rtx sym = XVECEXP (x, 0, 0);
32eda510 6152 gcc_assert (GET_CODE (sym) == SYMBOL_REF
6153 && CONSTANT_POOL_ADDRESS_P (sym));
20074f87 6154
0756cebb 6155 if (*ref == NULL_RTX)
20074f87 6156 *ref = sym;
ffead1ca 6157 else
32eda510 6158 gcc_assert (*ref == sym);
20074f87 6159
6160 return;
0756cebb 6161 }
6162
6163 fmt = GET_RTX_FORMAT (GET_CODE (x));
6164 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6165 {
6166 if (fmt[i] == 'e')
6167 {
6168 find_constant_pool_ref (XEXP (x, i), ref);
6169 }
6170 else if (fmt[i] == 'E')
6171 {
6172 for (j = 0; j < XVECLEN (x, i); j++)
6173 find_constant_pool_ref (XVECEXP (x, i, j), ref);
6174 }
6175 }
6176}
6177
ffead1ca 6178/* Replace every reference to the annotated literal pool
20074f87 6179 symbol REF in X by its base plus OFFSET. */
0756cebb 6180
6181static void
20074f87 6182replace_constant_pool_ref (rtx *x, rtx ref, rtx offset)
0756cebb 6183{
6184 int i, j;
6185 const char *fmt;
6186
32eda510 6187 gcc_assert (*x != ref);
0756cebb 6188
20074f87 6189 if (GET_CODE (*x) == UNSPEC
6190 && XINT (*x, 1) == UNSPEC_LTREF
6191 && XVECEXP (*x, 0, 0) == ref)
0756cebb 6192 {
20074f87 6193 *x = gen_rtx_PLUS (Pmode, XVECEXP (*x, 0, 1), offset);
6194 return;
0756cebb 6195 }
6196
20074f87 6197 if (GET_CODE (*x) == PLUS
6198 && GET_CODE (XEXP (*x, 1)) == CONST_INT
6199 && GET_CODE (XEXP (*x, 0)) == UNSPEC
6200 && XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
6201 && XVECEXP (XEXP (*x, 0), 0, 0) == ref)
0756cebb 6202 {
20074f87 6203 rtx addr = gen_rtx_PLUS (Pmode, XVECEXP (XEXP (*x, 0), 0, 1), offset);
29c05e22 6204 *x = plus_constant (Pmode, addr, INTVAL (XEXP (*x, 1)));
20074f87 6205 return;
0756cebb 6206 }
6207
6208 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6209 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6210 {
6211 if (fmt[i] == 'e')
6212 {
20074f87 6213 replace_constant_pool_ref (&XEXP (*x, i), ref, offset);
0756cebb 6214 }
6215 else if (fmt[i] == 'E')
6216 {
6217 for (j = 0; j < XVECLEN (*x, i); j++)
20074f87 6218 replace_constant_pool_ref (&XVECEXP (*x, i, j), ref, offset);
0756cebb 6219 }
6220 }
6221}
6222
f81e845f 6223/* Check whether X contains an UNSPEC_LTREL_BASE.
12ef3745 6224 Return its constant pool symbol if found, NULL_RTX otherwise. */
96be3ab6 6225
12ef3745 6226static rtx
b40da9a7 6227find_ltrel_base (rtx x)
96be3ab6 6228{
96be3ab6 6229 int i, j;
6230 const char *fmt;
6231
12ef3745 6232 if (GET_CODE (x) == UNSPEC
6233 && XINT (x, 1) == UNSPEC_LTREL_BASE)
6234 return XVECEXP (x, 0, 0);
96be3ab6 6235
6236 fmt = GET_RTX_FORMAT (GET_CODE (x));
6237 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6238 {
6239 if (fmt[i] == 'e')
6240 {
12ef3745 6241 rtx fnd = find_ltrel_base (XEXP (x, i));
6242 if (fnd)
6243 return fnd;
96be3ab6 6244 }
6245 else if (fmt[i] == 'E')
6246 {
6247 for (j = 0; j < XVECLEN (x, i); j++)
12ef3745 6248 {
6249 rtx fnd = find_ltrel_base (XVECEXP (x, i, j));
6250 if (fnd)
6251 return fnd;
6252 }
96be3ab6 6253 }
6254 }
6255
12ef3745 6256 return NULL_RTX;
96be3ab6 6257}
6258
20074f87 6259/* Replace any occurrence of UNSPEC_LTREL_BASE in X with its base. */
96be3ab6 6260
6261static void
20074f87 6262replace_ltrel_base (rtx *x)
96be3ab6 6263{
12ef3745 6264 int i, j;
96be3ab6 6265 const char *fmt;
6266
12ef3745 6267 if (GET_CODE (*x) == UNSPEC
6268 && XINT (*x, 1) == UNSPEC_LTREL_BASE)
96be3ab6 6269 {
20074f87 6270 *x = XVECEXP (*x, 0, 1);
12ef3745 6271 return;
96be3ab6 6272 }
6273
6274 fmt = GET_RTX_FORMAT (GET_CODE (*x));
6275 for (i = GET_RTX_LENGTH (GET_CODE (*x)) - 1; i >= 0; i--)
6276 {
6277 if (fmt[i] == 'e')
6278 {
20074f87 6279 replace_ltrel_base (&XEXP (*x, i));
96be3ab6 6280 }
6281 else if (fmt[i] == 'E')
6282 {
6283 for (j = 0; j < XVECLEN (*x, i); j++)
20074f87 6284 replace_ltrel_base (&XVECEXP (*x, i, j));
96be3ab6 6285 }
6286 }
6287}
6288
6289
12ef3745 6290/* We keep a list of constants which we have to add to internal
0756cebb 6291 constant tables in the middle of large functions. */
6292
36868490 6293#define NR_C_MODES 11
f81e845f 6294enum machine_mode constant_modes[NR_C_MODES] =
0756cebb 6295{
36868490 6296 TFmode, TImode, TDmode,
6297 DFmode, DImode, DDmode,
6298 SFmode, SImode, SDmode,
0756cebb 6299 HImode,
6300 QImode
6301};
6302
0756cebb 6303struct constant
6304{
6305 struct constant *next;
6306 rtx value;
6307 rtx label;
6308};
6309
6310struct constant_pool
6311{
6312 struct constant_pool *next;
6313 rtx first_insn;
96be3ab6 6314 rtx pool_insn;
6315 bitmap insns;
86428198 6316 rtx emit_pool_after;
0756cebb 6317
6318 struct constant *constants[NR_C_MODES];
d345b493 6319 struct constant *execute;
0756cebb 6320 rtx label;
6321 int size;
6322};
6323
875862bf 6324/* Allocate new constant_pool structure. */
6325
6326static struct constant_pool *
6327s390_alloc_pool (void)
6328{
6329 struct constant_pool *pool;
6330 int i;
6331
6332 pool = (struct constant_pool *) xmalloc (sizeof *pool);
6333 pool->next = NULL;
6334 for (i = 0; i < NR_C_MODES; i++)
6335 pool->constants[i] = NULL;
6336
6337 pool->execute = NULL;
6338 pool->label = gen_label_rtx ();
6339 pool->first_insn = NULL_RTX;
6340 pool->pool_insn = NULL_RTX;
6341 pool->insns = BITMAP_ALLOC (NULL);
6342 pool->size = 0;
86428198 6343 pool->emit_pool_after = NULL_RTX;
875862bf 6344
6345 return pool;
6346}
0756cebb 6347
6348/* Create new constant pool covering instructions starting at INSN
6349 and chain it to the end of POOL_LIST. */
6350
6351static struct constant_pool *
b40da9a7 6352s390_start_pool (struct constant_pool **pool_list, rtx insn)
0756cebb 6353{
6354 struct constant_pool *pool, **prev;
0756cebb 6355
c2c1332a 6356 pool = s390_alloc_pool ();
0756cebb 6357 pool->first_insn = insn;
96be3ab6 6358
0756cebb 6359 for (prev = pool_list; *prev; prev = &(*prev)->next)
6360 ;
6361 *prev = pool;
6362
6363 return pool;
6364}
6365
96be3ab6 6366/* End range of instructions covered by POOL at INSN and emit
6367 placeholder insn representing the pool. */
0756cebb 6368
6369static void
b40da9a7 6370s390_end_pool (struct constant_pool *pool, rtx insn)
0756cebb 6371{
96be3ab6 6372 rtx pool_size = GEN_INT (pool->size + 8 /* alignment slop */);
6373
6374 if (!insn)
6375 insn = get_last_insn ();
6376
6377 pool->pool_insn = emit_insn_after (gen_pool (pool_size), insn);
6378 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6379}
6380
6381/* Add INSN to the list of insns covered by POOL. */
6382
6383static void
b40da9a7 6384s390_add_pool_insn (struct constant_pool *pool, rtx insn)
96be3ab6 6385{
6386 bitmap_set_bit (pool->insns, INSN_UID (insn));
0756cebb 6387}
6388
6389/* Return pool out of POOL_LIST that covers INSN. */
6390
6391static struct constant_pool *
b40da9a7 6392s390_find_pool (struct constant_pool *pool_list, rtx insn)
0756cebb 6393{
0756cebb 6394 struct constant_pool *pool;
6395
0756cebb 6396 for (pool = pool_list; pool; pool = pool->next)
96be3ab6 6397 if (bitmap_bit_p (pool->insns, INSN_UID (insn)))
0756cebb 6398 break;
6399
6400 return pool;
6401}
6402
96be3ab6 6403/* Add constant VAL of mode MODE to the constant pool POOL. */
0756cebb 6404
96be3ab6 6405static void
b40da9a7 6406s390_add_constant (struct constant_pool *pool, rtx val, enum machine_mode mode)
0756cebb 6407{
6408 struct constant *c;
0756cebb 6409 int i;
6410
6411 for (i = 0; i < NR_C_MODES; i++)
6412 if (constant_modes[i] == mode)
6413 break;
32eda510 6414 gcc_assert (i != NR_C_MODES);
0756cebb 6415
6416 for (c = pool->constants[i]; c != NULL; c = c->next)
6417 if (rtx_equal_p (val, c->value))
6418 break;
6419
6420 if (c == NULL)
6421 {
6422 c = (struct constant *) xmalloc (sizeof *c);
6423 c->value = val;
6424 c->label = gen_label_rtx ();
6425 c->next = pool->constants[i];
6426 pool->constants[i] = c;
6427 pool->size += GET_MODE_SIZE (mode);
6428 }
96be3ab6 6429}
0756cebb 6430
1ed7a160 6431/* Return an rtx that represents the offset of X from the start of
6432 pool POOL. */
6433
6434static rtx
6435s390_pool_offset (struct constant_pool *pool, rtx x)
6436{
6437 rtx label;
6438
6439 label = gen_rtx_LABEL_REF (GET_MODE (x), pool->label);
6440 x = gen_rtx_UNSPEC (GET_MODE (x), gen_rtvec (2, x, label),
6441 UNSPEC_POOL_OFFSET);
6442 return gen_rtx_CONST (GET_MODE (x), x);
6443}
6444
96be3ab6 6445/* Find constant VAL of mode MODE in the constant pool POOL.
6446 Return an RTX describing the distance from the start of
6447 the pool to the location of the new constant. */
f81e845f 6448
96be3ab6 6449static rtx
b40da9a7 6450s390_find_constant (struct constant_pool *pool, rtx val,
6451 enum machine_mode mode)
96be3ab6 6452{
6453 struct constant *c;
96be3ab6 6454 int i;
f81e845f 6455
96be3ab6 6456 for (i = 0; i < NR_C_MODES; i++)
6457 if (constant_modes[i] == mode)
6458 break;
32eda510 6459 gcc_assert (i != NR_C_MODES);
f81e845f 6460
96be3ab6 6461 for (c = pool->constants[i]; c != NULL; c = c->next)
6462 if (rtx_equal_p (val, c->value))
6463 break;
f81e845f 6464
32eda510 6465 gcc_assert (c);
f81e845f 6466
1ed7a160 6467 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
0756cebb 6468}
6469
875862bf 6470/* Check whether INSN is an execute. Return the label_ref to its
6471 execute target template if so, NULL_RTX otherwise. */
6472
6473static rtx
6474s390_execute_label (rtx insn)
6475{
aa90bb35 6476 if (NONJUMP_INSN_P (insn)
875862bf 6477 && GET_CODE (PATTERN (insn)) == PARALLEL
6478 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == UNSPEC
6479 && XINT (XVECEXP (PATTERN (insn), 0, 0), 1) == UNSPEC_EXECUTE)
6480 return XVECEXP (XVECEXP (PATTERN (insn), 0, 0), 0, 2);
6481
6482 return NULL_RTX;
6483}
6484
d345b493 6485/* Add execute target for INSN to the constant pool POOL. */
6486
6487static void
6488s390_add_execute (struct constant_pool *pool, rtx insn)
6489{
6490 struct constant *c;
6491
6492 for (c = pool->execute; c != NULL; c = c->next)
6493 if (INSN_UID (insn) == INSN_UID (c->value))
6494 break;
6495
6496 if (c == NULL)
6497 {
d345b493 6498 c = (struct constant *) xmalloc (sizeof *c);
6499 c->value = insn;
babfdedf 6500 c->label = gen_label_rtx ();
d345b493 6501 c->next = pool->execute;
6502 pool->execute = c;
babfdedf 6503 pool->size += 6;
d345b493 6504 }
6505}
6506
6507/* Find execute target for INSN in the constant pool POOL.
6508 Return an RTX describing the distance from the start of
6509 the pool to the location of the execute target. */
6510
6511static rtx
6512s390_find_execute (struct constant_pool *pool, rtx insn)
6513{
6514 struct constant *c;
d345b493 6515
6516 for (c = pool->execute; c != NULL; c = c->next)
6517 if (INSN_UID (insn) == INSN_UID (c->value))
6518 break;
6519
32eda510 6520 gcc_assert (c);
d345b493 6521
1ed7a160 6522 return s390_pool_offset (pool, gen_rtx_LABEL_REF (Pmode, c->label));
d345b493 6523}
6524
875862bf 6525/* For an execute INSN, extract the execute target template. */
d345b493 6526
6527static rtx
875862bf 6528s390_execute_target (rtx insn)
d345b493 6529{
875862bf 6530 rtx pattern = PATTERN (insn);
6531 gcc_assert (s390_execute_label (insn));
d345b493 6532
6533 if (XVECLEN (pattern, 0) == 2)
6534 {
6535 pattern = copy_rtx (XVECEXP (pattern, 0, 1));
6536 }
6537 else
6538 {
6539 rtvec vec = rtvec_alloc (XVECLEN (pattern, 0) - 1);
6540 int i;
6541
6542 for (i = 0; i < XVECLEN (pattern, 0) - 1; i++)
6543 RTVEC_ELT (vec, i) = copy_rtx (XVECEXP (pattern, 0, i + 1));
6544
6545 pattern = gen_rtx_PARALLEL (VOIDmode, vec);
6546 }
6547
6548 return pattern;
6549}
6550
6551/* Indicate that INSN cannot be duplicated. This is the case for
6552 execute insns that carry a unique label. */
6553
6554static bool
6555s390_cannot_copy_insn_p (rtx insn)
6556{
6557 rtx label = s390_execute_label (insn);
6558 return label && label != const0_rtx;
6559}
6560
c2c1332a 6561/* Dump out the constants in POOL. If REMOTE_LABEL is true,
6562 do not emit the pool base label. */
0756cebb 6563
d345b493 6564static void
c2c1332a 6565s390_dump_pool (struct constant_pool *pool, bool remote_label)
0756cebb 6566{
6567 struct constant *c;
d345b493 6568 rtx insn = pool->pool_insn;
0756cebb 6569 int i;
6570
d345b493 6571 /* Switch to rodata section. */
6572 if (TARGET_CPU_ZARCH)
6573 {
6574 insn = emit_insn_after (gen_pool_section_start (), insn);
6575 INSN_ADDRESSES_NEW (insn, -1);
6576 }
6577
6578 /* Ensure minimum pool alignment. */
dafc8d45 6579 if (TARGET_CPU_ZARCH)
d345b493 6580 insn = emit_insn_after (gen_pool_align (GEN_INT (8)), insn);
0756cebb 6581 else
d345b493 6582 insn = emit_insn_after (gen_pool_align (GEN_INT (4)), insn);
0756cebb 6583 INSN_ADDRESSES_NEW (insn, -1);
6584
d345b493 6585 /* Emit pool base label. */
c2c1332a 6586 if (!remote_label)
6587 {
6588 insn = emit_label_after (pool->label, insn);
6589 INSN_ADDRESSES_NEW (insn, -1);
6590 }
0756cebb 6591
6592 /* Dump constants in descending alignment requirement order,
6593 ensuring proper alignment for every constant. */
6594 for (i = 0; i < NR_C_MODES; i++)
6595 for (c = pool->constants[i]; c; c = c->next)
6596 {
12ef3745 6597 /* Convert UNSPEC_LTREL_OFFSET unspecs to pool-relative references. */
b2ed6df1 6598 rtx value = copy_rtx (c->value);
96be3ab6 6599 if (GET_CODE (value) == CONST
6600 && GET_CODE (XEXP (value, 0)) == UNSPEC
12ef3745 6601 && XINT (XEXP (value, 0), 1) == UNSPEC_LTREL_OFFSET
96be3ab6 6602 && XVECLEN (XEXP (value, 0), 0) == 1)
1ed7a160 6603 value = s390_pool_offset (pool, XVECEXP (XEXP (value, 0), 0, 0));
96be3ab6 6604
0756cebb 6605 insn = emit_label_after (c->label, insn);
6606 INSN_ADDRESSES_NEW (insn, -1);
df82fb76 6607
f588eb9f 6608 value = gen_rtx_UNSPEC_VOLATILE (constant_modes[i],
df82fb76 6609 gen_rtvec (1, value),
6610 UNSPECV_POOL_ENTRY);
6611 insn = emit_insn_after (value, insn);
0756cebb 6612 INSN_ADDRESSES_NEW (insn, -1);
6613 }
6614
d345b493 6615 /* Ensure minimum alignment for instructions. */
6616 insn = emit_insn_after (gen_pool_align (GEN_INT (2)), insn);
0756cebb 6617 INSN_ADDRESSES_NEW (insn, -1);
6618
d345b493 6619 /* Output in-pool execute template insns. */
6620 for (c = pool->execute; c; c = c->next)
6621 {
d345b493 6622 insn = emit_label_after (c->label, insn);
6623 INSN_ADDRESSES_NEW (insn, -1);
6624
6625 insn = emit_insn_after (s390_execute_target (c->value), insn);
6626 INSN_ADDRESSES_NEW (insn, -1);
6627 }
6628
6629 /* Switch back to previous section. */
6630 if (TARGET_CPU_ZARCH)
6631 {
6632 insn = emit_insn_after (gen_pool_section_end (), insn);
6633 INSN_ADDRESSES_NEW (insn, -1);
6634 }
6635
0756cebb 6636 insn = emit_barrier_after (insn);
6637 INSN_ADDRESSES_NEW (insn, -1);
6638
96be3ab6 6639 /* Remove placeholder insn. */
6640 remove_insn (pool->pool_insn);
d345b493 6641}
6642
0756cebb 6643/* Free all memory used by POOL. */
6644
6645static void
b40da9a7 6646s390_free_pool (struct constant_pool *pool)
0756cebb 6647{
d345b493 6648 struct constant *c, *next;
0756cebb 6649 int i;
6650
6651 for (i = 0; i < NR_C_MODES; i++)
d345b493 6652 for (c = pool->constants[i]; c; c = next)
6653 {
6654 next = c->next;
6655 free (c);
6656 }
6657
6658 for (c = pool->execute; c; c = next)
0756cebb 6659 {
d345b493 6660 next = c->next;
6661 free (c);
0756cebb 6662 }
6663
4d6e8511 6664 BITMAP_FREE (pool->insns);
0756cebb 6665 free (pool);
f81e845f 6666}
0756cebb 6667
0756cebb 6668
c2c1332a 6669/* Collect main literal pool. Return NULL on overflow. */
6670
6671static struct constant_pool *
6672s390_mainpool_start (void)
6673{
6674 struct constant_pool *pool;
6675 rtx insn;
6676
6677 pool = s390_alloc_pool ();
6678
6679 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6680 {
aa90bb35 6681 if (NONJUMP_INSN_P (insn)
20074f87 6682 && GET_CODE (PATTERN (insn)) == SET
6683 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC_VOLATILE
6684 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPECV_MAIN_POOL)
c2c1332a 6685 {
32eda510 6686 gcc_assert (!pool->pool_insn);
c2c1332a 6687 pool->pool_insn = insn;
6688 }
6689
babfdedf 6690 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
d345b493 6691 {
6692 s390_add_execute (pool, insn);
6693 }
aa90bb35 6694 else if (NONJUMP_INSN_P (insn) || CALL_P (insn))
c2c1332a 6695 {
6696 rtx pool_ref = NULL_RTX;
6697 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6698 if (pool_ref)
6699 {
6700 rtx constant = get_pool_constant (pool_ref);
6701 enum machine_mode mode = get_pool_mode (pool_ref);
6702 s390_add_constant (pool, constant, mode);
6703 }
6704 }
86428198 6705
6706 /* If hot/cold partitioning is enabled we have to make sure that
6707 the literal pool is emitted in the same section where the
6708 initialization of the literal pool base pointer takes place.
6709 emit_pool_after is only used in the non-overflow case on non
6710 Z cpus where we can emit the literal pool at the end of the
6711 function body within the text section. */
6712 if (NOTE_P (insn)
7338c728 6713 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS
6714 && !pool->emit_pool_after)
6715 pool->emit_pool_after = PREV_INSN (insn);
c2c1332a 6716 }
6717
32eda510 6718 gcc_assert (pool->pool_insn || pool->size == 0);
c2c1332a 6719
6720 if (pool->size >= 4096)
6721 {
7de9f7aa 6722 /* We're going to chunkify the pool, so remove the main
6723 pool placeholder insn. */
6724 remove_insn (pool->pool_insn);
6725
c2c1332a 6726 s390_free_pool (pool);
6727 pool = NULL;
6728 }
6729
86428198 6730 /* If the functions ends with the section where the literal pool
6731 should be emitted set the marker to its end. */
7338c728 6732 if (pool && !pool->emit_pool_after)
86428198 6733 pool->emit_pool_after = get_last_insn ();
6734
c2c1332a 6735 return pool;
6736}
6737
6738/* POOL holds the main literal pool as collected by s390_mainpool_start.
6739 Modify the current function to output the pool constants as well as
20074f87 6740 the pool register setup instruction. */
c2c1332a 6741
6742static void
20074f87 6743s390_mainpool_finish (struct constant_pool *pool)
c2c1332a 6744{
4fed3f99 6745 rtx base_reg = cfun->machine->base_reg;
c2c1332a 6746 rtx insn;
6747
6748 /* If the pool is empty, we're done. */
6749 if (pool->size == 0)
6750 {
4fed3f99 6751 /* We don't actually need a base register after all. */
6752 cfun->machine->base_reg = NULL_RTX;
6753
6754 if (pool->pool_insn)
6755 remove_insn (pool->pool_insn);
c2c1332a 6756 s390_free_pool (pool);
6757 return;
6758 }
6759
6760 /* We need correct insn addresses. */
6761 shorten_branches (get_insns ());
6762
dafc8d45 6763 /* On zSeries, we use a LARL to load the pool register. The pool is
c2c1332a 6764 located in the .rodata section, so we emit it after the function. */
dafc8d45 6765 if (TARGET_CPU_ZARCH)
c2c1332a 6766 {
6767 insn = gen_main_base_64 (base_reg, pool->label);
6768 insn = emit_insn_after (insn, pool->pool_insn);
6769 INSN_ADDRESSES_NEW (insn, -1);
6770 remove_insn (pool->pool_insn);
f588eb9f 6771
6772 insn = get_last_insn ();
c2c1332a 6773 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6774 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6775
6776 s390_dump_pool (pool, 0);
6777 }
6778
dafc8d45 6779 /* On S/390, if the total size of the function's code plus literal pool
c2c1332a 6780 does not exceed 4096 bytes, we use BASR to set up a function base
6781 pointer, and emit the literal pool at the end of the function. */
86428198 6782 else if (INSN_ADDRESSES (INSN_UID (pool->emit_pool_after))
c2c1332a 6783 + pool->size + 8 /* alignment slop */ < 4096)
6784 {
6785 insn = gen_main_base_31_small (base_reg, pool->label);
6786 insn = emit_insn_after (insn, pool->pool_insn);
6787 INSN_ADDRESSES_NEW (insn, -1);
6788 remove_insn (pool->pool_insn);
6789
6790 insn = emit_label_after (pool->label, insn);
6791 INSN_ADDRESSES_NEW (insn, -1);
6792
86428198 6793 /* emit_pool_after will be set by s390_mainpool_start to the
6794 last insn of the section where the literal pool should be
6795 emitted. */
6796 insn = pool->emit_pool_after;
6797
c2c1332a 6798 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6799 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6800
6801 s390_dump_pool (pool, 1);
6802 }
6803
6804 /* Otherwise, we emit an inline literal pool and use BASR to branch
6805 over it, setting up the pool register at the same time. */
6806 else
6807 {
6808 rtx pool_end = gen_label_rtx ();
6809
6810 insn = gen_main_base_31_large (base_reg, pool->label, pool_end);
12f0f6d7 6811 insn = emit_jump_insn_after (insn, pool->pool_insn);
6812 JUMP_LABEL (insn) = pool_end;
c2c1332a 6813 INSN_ADDRESSES_NEW (insn, -1);
6814 remove_insn (pool->pool_insn);
6815
6816 insn = emit_label_after (pool->label, insn);
6817 INSN_ADDRESSES_NEW (insn, -1);
6818
6819 pool->pool_insn = emit_insn_after (gen_pool (const0_rtx), insn);
6820 INSN_ADDRESSES_NEW (pool->pool_insn, -1);
6821
6822 insn = emit_label_after (pool_end, pool->pool_insn);
6823 INSN_ADDRESSES_NEW (insn, -1);
6824
6825 s390_dump_pool (pool, 1);
6826 }
6827
6828
6829 /* Replace all literal pool references. */
6830
6831 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
6832 {
6833 if (INSN_P (insn))
20074f87 6834 replace_ltrel_base (&PATTERN (insn));
c2c1332a 6835
aa90bb35 6836 if (NONJUMP_INSN_P (insn) || CALL_P (insn))
c2c1332a 6837 {
6838 rtx addr, pool_ref = NULL_RTX;
6839 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6840 if (pool_ref)
6841 {
d345b493 6842 if (s390_execute_label (insn))
6843 addr = s390_find_execute (pool, insn);
6844 else
6845 addr = s390_find_constant (pool, get_pool_constant (pool_ref),
6846 get_pool_mode (pool_ref));
6847
c2c1332a 6848 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
6849 INSN_CODE (insn) = -1;
6850 }
6851 }
6852 }
6853
6854
6855 /* Free the pool. */
6856 s390_free_pool (pool);
6857}
6858
6859/* POOL holds the main literal pool as collected by s390_mainpool_start.
6860 We have decided we cannot use this pool, so revert all changes
6861 to the current function that were done by s390_mainpool_start. */
6862static void
6863s390_mainpool_cancel (struct constant_pool *pool)
6864{
6865 /* We didn't actually change the instruction stream, so simply
6866 free the pool memory. */
6867 s390_free_pool (pool);
6868}
6869
6870
20074f87 6871/* Chunkify the literal pool. */
4673c1a0 6872
0756cebb 6873#define S390_POOL_CHUNK_MIN 0xc00
6874#define S390_POOL_CHUNK_MAX 0xe00
6875
f81e845f 6876static struct constant_pool *
20074f87 6877s390_chunkify_start (void)
4673c1a0 6878{
0756cebb 6879 struct constant_pool *curr_pool = NULL, *pool_list = NULL;
6880 int extra_size = 0;
6881 bitmap far_labels;
12ef3745 6882 rtx pending_ltrel = NULL_RTX;
479ca6e8 6883 rtx insn;
4673c1a0 6884
b40da9a7 6885 rtx (*gen_reload_base) (rtx, rtx) =
dafc8d45 6886 TARGET_CPU_ZARCH? gen_reload_base_64 : gen_reload_base_31;
96be3ab6 6887
6888
9a2a66ae 6889 /* We need correct insn addresses. */
6890
6891 shorten_branches (get_insns ());
6892
12ef3745 6893 /* Scan all insns and move literals to pool chunks. */
479ca6e8 6894
479ca6e8 6895 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
4673c1a0 6896 {
86428198 6897 bool section_switch_p = false;
6898
12ef3745 6899 /* Check for pending LTREL_BASE. */
6900 if (INSN_P (insn))
6901 {
6902 rtx ltrel_base = find_ltrel_base (PATTERN (insn));
6903 if (ltrel_base)
6904 {
32eda510 6905 gcc_assert (ltrel_base == pending_ltrel);
6906 pending_ltrel = NULL_RTX;
12ef3745 6907 }
6908 }
6909
babfdedf 6910 if (!TARGET_CPU_ZARCH && s390_execute_label (insn))
d345b493 6911 {
6912 if (!curr_pool)
6913 curr_pool = s390_start_pool (&pool_list, insn);
6914
6915 s390_add_execute (curr_pool, insn);
6916 s390_add_pool_insn (curr_pool, insn);
6917 }
aa90bb35 6918 else if (NONJUMP_INSN_P (insn) || CALL_P (insn))
0756cebb 6919 {
96be3ab6 6920 rtx pool_ref = NULL_RTX;
0756cebb 6921 find_constant_pool_ref (PATTERN (insn), &pool_ref);
6922 if (pool_ref)
6923 {
12ef3745 6924 rtx constant = get_pool_constant (pool_ref);
6925 enum machine_mode mode = get_pool_mode (pool_ref);
6926
0756cebb 6927 if (!curr_pool)
6928 curr_pool = s390_start_pool (&pool_list, insn);
6929
12ef3745 6930 s390_add_constant (curr_pool, constant, mode);
96be3ab6 6931 s390_add_pool_insn (curr_pool, insn);
96be3ab6 6932
12ef3745 6933 /* Don't split the pool chunk between a LTREL_OFFSET load
6934 and the corresponding LTREL_BASE. */
6935 if (GET_CODE (constant) == CONST
6936 && GET_CODE (XEXP (constant, 0)) == UNSPEC
6937 && XINT (XEXP (constant, 0), 1) == UNSPEC_LTREL_OFFSET)
6938 {
32eda510 6939 gcc_assert (!pending_ltrel);
12ef3745 6940 pending_ltrel = pool_ref;
6941 }
0756cebb 6942 }
6943 }
6944
91f71fa3 6945 if (JUMP_P (insn) || JUMP_TABLE_DATA_P (insn) || LABEL_P (insn))
12ef3745 6946 {
6947 if (curr_pool)
6948 s390_add_pool_insn (curr_pool, insn);
6949 /* An LTREL_BASE must follow within the same basic block. */
32eda510 6950 gcc_assert (!pending_ltrel);
12ef3745 6951 }
96be3ab6 6952
414bc417 6953 if (NOTE_P (insn))
6954 switch (NOTE_KIND (insn))
6955 {
6956 case NOTE_INSN_SWITCH_TEXT_SECTIONS:
6957 section_switch_p = true;
6958 break;
6959 case NOTE_INSN_VAR_LOCATION:
6960 case NOTE_INSN_CALL_ARG_LOCATION:
6961 continue;
6962 default:
6963 break;
6964 }
86428198 6965
f81e845f 6966 if (!curr_pool
0756cebb 6967 || INSN_ADDRESSES_SIZE () <= (size_t) INSN_UID (insn)
6968 || INSN_ADDRESSES (INSN_UID (insn)) == -1)
4673c1a0 6969 continue;
479ca6e8 6970
dafc8d45 6971 if (TARGET_CPU_ZARCH)
4673c1a0 6972 {
0756cebb 6973 if (curr_pool->size < S390_POOL_CHUNK_MAX)
6974 continue;
479ca6e8 6975
96be3ab6 6976 s390_end_pool (curr_pool, NULL_RTX);
0756cebb 6977 curr_pool = NULL;
6978 }
6979 else
4673c1a0 6980 {
0756cebb 6981 int chunk_size = INSN_ADDRESSES (INSN_UID (insn))
b40da9a7 6982 - INSN_ADDRESSES (INSN_UID (curr_pool->first_insn))
0756cebb 6983 + extra_size;
6984
6985 /* We will later have to insert base register reload insns.
6986 Those will have an effect on code size, which we need to
6987 consider here. This calculation makes rather pessimistic
6988 worst-case assumptions. */
aa90bb35 6989 if (LABEL_P (insn))
0756cebb 6990 extra_size += 6;
0756cebb 6991
6992 if (chunk_size < S390_POOL_CHUNK_MIN
86428198 6993 && curr_pool->size < S390_POOL_CHUNK_MIN
6994 && !section_switch_p)
0756cebb 6995 continue;
6996
6997 /* Pool chunks can only be inserted after BARRIERs ... */
aa90bb35 6998 if (BARRIER_P (insn))
0756cebb 6999 {
7000 s390_end_pool (curr_pool, insn);
7001 curr_pool = NULL;
7002 extra_size = 0;
7003 }
7004
7005 /* ... so if we don't find one in time, create one. */
86428198 7006 else if (chunk_size > S390_POOL_CHUNK_MAX
7007 || curr_pool->size > S390_POOL_CHUNK_MAX
7008 || section_switch_p)
0756cebb 7009 {
414bc417 7010 rtx label, jump, barrier, next, prev;
0756cebb 7011
86428198 7012 if (!section_switch_p)
7013 {
7014 /* We can insert the barrier only after a 'real' insn. */
aa90bb35 7015 if (! NONJUMP_INSN_P (insn) && ! CALL_P (insn))
86428198 7016 continue;
7017 if (get_attr_length (insn) == 0)
7018 continue;
7019 /* Don't separate LTREL_BASE from the corresponding
414bc417 7020 LTREL_OFFSET load. */
86428198 7021 if (pending_ltrel)
7022 continue;
414bc417 7023 next = insn;
7024 do
7025 {
7026 insn = next;
7027 next = NEXT_INSN (insn);
7028 }
7029 while (next
7030 && NOTE_P (next)
7031 && (NOTE_KIND (next) == NOTE_INSN_VAR_LOCATION
7032 || NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION));
86428198 7033 }
7034 else
7035 {
7036 gcc_assert (!pending_ltrel);
7037
7038 /* The old pool has to end before the section switch
7039 note in order to make it part of the current
7040 section. */
7041 insn = PREV_INSN (insn);
7042 }
96be3ab6 7043
b40da9a7 7044 label = gen_label_rtx ();
414bc417 7045 prev = insn;
7046 if (prev && NOTE_P (prev))
7047 prev = prev_nonnote_insn (prev);
7048 if (prev)
7049 jump = emit_jump_insn_after_setloc (gen_jump (label), insn,
d53c050c 7050 INSN_LOCATION (prev));
414bc417 7051 else
7052 jump = emit_jump_insn_after_noloc (gen_jump (label), insn);
0756cebb 7053 barrier = emit_barrier_after (jump);
7054 insn = emit_label_after (label, barrier);
7055 JUMP_LABEL (jump) = label;
7056 LABEL_NUSES (label) = 1;
7057
96be3ab6 7058 INSN_ADDRESSES_NEW (jump, -1);
7059 INSN_ADDRESSES_NEW (barrier, -1);
0756cebb 7060 INSN_ADDRESSES_NEW (insn, -1);
7061
7062 s390_end_pool (curr_pool, barrier);
7063 curr_pool = NULL;
7064 extra_size = 0;
7065 }
479ca6e8 7066 }
4673c1a0 7067 }
9fa6d5d9 7068
96be3ab6 7069 if (curr_pool)
7070 s390_end_pool (curr_pool, NULL_RTX);
32eda510 7071 gcc_assert (!pending_ltrel);
0756cebb 7072
f81e845f 7073 /* Find all labels that are branched into
479ca6e8 7074 from an insn belonging to a different chunk. */
9fa6d5d9 7075
4d6e8511 7076 far_labels = BITMAP_ALLOC (NULL);
a8ef833a 7077
479ca6e8 7078 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
4673c1a0 7079 {
245402e7 7080 rtx table;
7081
0756cebb 7082 /* Labels marked with LABEL_PRESERVE_P can be target
7083 of non-local jumps, so we have to mark them.
7084 The same holds for named labels.
7085
7086 Don't do that, however, if it is the label before
7087 a jump table. */
7088
aa90bb35 7089 if (LABEL_P (insn)
0756cebb 7090 && (LABEL_PRESERVE_P (insn) || LABEL_NAME (insn)))
7091 {
0cd9a9a9 7092 rtx vec_insn = NEXT_INSN (insn);
77985f1a 7093 if (! vec_insn || ! JUMP_TABLE_DATA_P (vec_insn))
0756cebb 7094 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (insn));
7095 }
245402e7 7096 /* Check potential targets in a table jump (casesi_jump). */
7097 else if (tablejump_p (insn, NULL, &table))
7098 {
7099 rtx vec_pat = PATTERN (table);
7100 int i, diff_p = GET_CODE (vec_pat) == ADDR_DIFF_VEC;
7101
7102 for (i = 0; i < XVECLEN (vec_pat, diff_p); i++)
7103 {
7104 rtx label = XEXP (XVECEXP (vec_pat, diff_p, i), 0);
0756cebb 7105
245402e7 7106 if (s390_find_pool (pool_list, label)
7107 != s390_find_pool (pool_list, insn))
7108 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
7109 }
7110 }
7111 /* If we have a direct jump (conditional or unconditional),
7112 check all potential targets. */
aa90bb35 7113 else if (JUMP_P (insn))
479ca6e8 7114 {
245402e7 7115 rtx pat = PATTERN (insn);
0cd9a9a9 7116
245402e7 7117 if (GET_CODE (pat) == PARALLEL)
3c482144 7118 pat = XVECEXP (pat, 0, 0);
7119
245402e7 7120 if (GET_CODE (pat) == SET)
7121 {
96be3ab6 7122 rtx label = JUMP_LABEL (insn);
479ca6e8 7123 if (label)
7124 {
245402e7 7125 if (s390_find_pool (pool_list, label)
0756cebb 7126 != s390_find_pool (pool_list, insn))
7127 bitmap_set_bit (far_labels, CODE_LABEL_NUMBER (label));
479ca6e8 7128 }
0756cebb 7129 }
245402e7 7130 }
4673c1a0 7131 }
9fa6d5d9 7132
0756cebb 7133 /* Insert base register reload insns before every pool. */
7134
7135 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
96be3ab6 7136 {
ffead1ca 7137 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
20074f87 7138 curr_pool->label);
96be3ab6 7139 rtx insn = curr_pool->first_insn;
7140 INSN_ADDRESSES_NEW (emit_insn_before (new_insn, insn), -1);
7141 }
0756cebb 7142
7143 /* Insert base register reload insns at every far label. */
479ca6e8 7144
479ca6e8 7145 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
aa90bb35 7146 if (LABEL_P (insn)
0756cebb 7147 && bitmap_bit_p (far_labels, CODE_LABEL_NUMBER (insn)))
7148 {
7149 struct constant_pool *pool = s390_find_pool (pool_list, insn);
7150 if (pool)
7151 {
ffead1ca 7152 rtx new_insn = gen_reload_base (cfun->machine->base_reg,
20074f87 7153 pool->label);
96be3ab6 7154 INSN_ADDRESSES_NEW (emit_insn_after (new_insn, insn), -1);
0756cebb 7155 }
7156 }
7157
96be3ab6 7158
4d6e8511 7159 BITMAP_FREE (far_labels);
479ca6e8 7160
479ca6e8 7161
7162 /* Recompute insn addresses. */
7163
7164 init_insn_lengths ();
7165 shorten_branches (get_insns ());
4673c1a0 7166
96be3ab6 7167 return pool_list;
7168}
4673c1a0 7169
96be3ab6 7170/* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
f81e845f 7171 After we have decided to use this list, finish implementing
20074f87 7172 all changes to the current function as required. */
f81e845f 7173
96be3ab6 7174static void
20074f87 7175s390_chunkify_finish (struct constant_pool *pool_list)
96be3ab6 7176{
96be3ab6 7177 struct constant_pool *curr_pool = NULL;
7178 rtx insn;
f81e845f 7179
7180
96be3ab6 7181 /* Replace all literal pool references. */
7182
f81e845f 7183 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
96be3ab6 7184 {
12ef3745 7185 if (INSN_P (insn))
20074f87 7186 replace_ltrel_base (&PATTERN (insn));
12ef3745 7187
96be3ab6 7188 curr_pool = s390_find_pool (pool_list, insn);
7189 if (!curr_pool)
7190 continue;
7191
aa90bb35 7192 if (NONJUMP_INSN_P (insn) || CALL_P (insn))
96be3ab6 7193 {
7194 rtx addr, pool_ref = NULL_RTX;
7195 find_constant_pool_ref (PATTERN (insn), &pool_ref);
7196 if (pool_ref)
7197 {
d345b493 7198 if (s390_execute_label (insn))
7199 addr = s390_find_execute (curr_pool, insn);
7200 else
7201 addr = s390_find_constant (curr_pool,
7202 get_pool_constant (pool_ref),
7203 get_pool_mode (pool_ref));
7204
96be3ab6 7205 replace_constant_pool_ref (&PATTERN (insn), pool_ref, addr);
7206 INSN_CODE (insn) = -1;
7207 }
96be3ab6 7208 }
7209 }
7210
7211 /* Dump out all literal pools. */
f81e845f 7212
96be3ab6 7213 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
c2c1332a 7214 s390_dump_pool (curr_pool, 0);
f81e845f 7215
96be3ab6 7216 /* Free pool list. */
7217
7218 while (pool_list)
7219 {
7220 struct constant_pool *next = pool_list->next;
7221 s390_free_pool (pool_list);
7222 pool_list = next;
7223 }
7224}
7225
7226/* POOL_LIST is a chunk list as prepared by s390_chunkify_start.
7227 We have decided we cannot use this list, so revert all changes
7228 to the current function that were done by s390_chunkify_start. */
f81e845f 7229
96be3ab6 7230static void
b40da9a7 7231s390_chunkify_cancel (struct constant_pool *pool_list)
96be3ab6 7232{
7233 struct constant_pool *curr_pool = NULL;
7234 rtx insn;
7235
7236 /* Remove all pool placeholder insns. */
7237
7238 for (curr_pool = pool_list; curr_pool; curr_pool = curr_pool->next)
7239 {
7240 /* Did we insert an extra barrier? Remove it. */
7241 rtx barrier = PREV_INSN (curr_pool->pool_insn);
7242 rtx jump = barrier? PREV_INSN (barrier) : NULL_RTX;
7243 rtx label = NEXT_INSN (curr_pool->pool_insn);
7244
aa90bb35 7245 if (jump && JUMP_P (jump)
7246 && barrier && BARRIER_P (barrier)
7247 && label && LABEL_P (label)
96be3ab6 7248 && GET_CODE (PATTERN (jump)) == SET
7249 && SET_DEST (PATTERN (jump)) == pc_rtx
7250 && GET_CODE (SET_SRC (PATTERN (jump))) == LABEL_REF
7251 && XEXP (SET_SRC (PATTERN (jump)), 0) == label)
7252 {
7253 remove_insn (jump);
7254 remove_insn (barrier);
7255 remove_insn (label);
0756cebb 7256 }
4673c1a0 7257
96be3ab6 7258 remove_insn (curr_pool->pool_insn);
7259 }
7260
12ef3745 7261 /* Remove all base register reload insns. */
96be3ab6 7262
7263 for (insn = get_insns (); insn; )
7264 {
7265 rtx next_insn = NEXT_INSN (insn);
7266
aa90bb35 7267 if (NONJUMP_INSN_P (insn)
96be3ab6 7268 && GET_CODE (PATTERN (insn)) == SET
7269 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
12ef3745 7270 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_RELOAD_BASE)
96be3ab6 7271 remove_insn (insn);
4673c1a0 7272
96be3ab6 7273 insn = next_insn;
7274 }
7275
7276 /* Free pool list. */
4673c1a0 7277
0756cebb 7278 while (pool_list)
4673c1a0 7279 {
0756cebb 7280 struct constant_pool *next = pool_list->next;
7281 s390_free_pool (pool_list);
7282 pool_list = next;
4673c1a0 7283 }
4673c1a0 7284}
7285
74d2529d 7286/* Output the constant pool entry EXP in mode MODE with alignment ALIGN. */
df82fb76 7287
7288void
74d2529d 7289s390_output_pool_entry (rtx exp, enum machine_mode mode, unsigned int align)
df82fb76 7290{
7291 REAL_VALUE_TYPE r;
7292
7293 switch (GET_MODE_CLASS (mode))
7294 {
7295 case MODE_FLOAT:
36868490 7296 case MODE_DECIMAL_FLOAT:
32eda510 7297 gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
df82fb76 7298
7299 REAL_VALUE_FROM_CONST_DOUBLE (r, exp);
7300 assemble_real (r, mode, align);
7301 break;
7302
7303 case MODE_INT:
74d2529d 7304 assemble_integer (exp, GET_MODE_SIZE (mode), align, 1);
af2a449c 7305 mark_symbol_refs_as_used (exp);
df82fb76 7306 break;
7307
7308 default:
32eda510 7309 gcc_unreachable ();
df82fb76 7310 }
7311}
7312
7313
875862bf 7314/* Return an RTL expression representing the value of the return address
7315 for the frame COUNT steps up from the current frame. FRAME is the
7316 frame pointer of that frame. */
0756cebb 7317
875862bf 7318rtx
7319s390_return_addr_rtx (int count, rtx frame ATTRIBUTE_UNUSED)
0756cebb 7320{
875862bf 7321 int offset;
7322 rtx addr;
96be3ab6 7323
875862bf 7324 /* Without backchain, we fail for all but the current frame. */
9a2a66ae 7325
875862bf 7326 if (!TARGET_BACKCHAIN && count > 0)
7327 return NULL_RTX;
9a2a66ae 7328
875862bf 7329 /* For the current frame, we need to make sure the initial
7330 value of RETURN_REGNUM is actually saved. */
9a2a66ae 7331
875862bf 7332 if (count == 0)
9a2a66ae 7333 {
1e639cb0 7334 /* On non-z architectures branch splitting could overwrite r14. */
7335 if (TARGET_CPU_ZARCH)
7336 return get_hard_reg_initial_val (Pmode, RETURN_REGNUM);
7337 else
7338 {
7339 cfun_frame_layout.save_return_addr_p = true;
7340 return gen_rtx_MEM (Pmode, return_address_pointer_rtx);
7341 }
875862bf 7342 }
9a2a66ae 7343
875862bf 7344 if (TARGET_PACKED_STACK)
b5fdc416 7345 offset = -2 * UNITS_PER_LONG;
875862bf 7346 else
b5fdc416 7347 offset = RETURN_REGNUM * UNITS_PER_LONG;
9a2a66ae 7348
29c05e22 7349 addr = plus_constant (Pmode, frame, offset);
875862bf 7350 addr = memory_address (Pmode, addr);
7351 return gen_rtx_MEM (Pmode, addr);
7352}
9a2a66ae 7353
875862bf 7354/* Return an RTL expression representing the back chain stored in
7355 the current stack frame. */
5fe74ca1 7356
875862bf 7357rtx
7358s390_back_chain_rtx (void)
7359{
7360 rtx chain;
5fe74ca1 7361
875862bf 7362 gcc_assert (TARGET_BACKCHAIN);
5fe74ca1 7363
875862bf 7364 if (TARGET_PACKED_STACK)
29c05e22 7365 chain = plus_constant (Pmode, stack_pointer_rtx,
b5fdc416 7366 STACK_POINTER_OFFSET - UNITS_PER_LONG);
875862bf 7367 else
7368 chain = stack_pointer_rtx;
5fe74ca1 7369
875862bf 7370 chain = gen_rtx_MEM (Pmode, chain);
7371 return chain;
7372}
9a2a66ae 7373
875862bf 7374/* Find first call clobbered register unused in a function.
7375 This could be used as base register in a leaf function
7376 or for holding the return address before epilogue. */
9a2a66ae 7377
875862bf 7378static int
7379find_unused_clobbered_reg (void)
7380{
7381 int i;
7382 for (i = 0; i < 6; i++)
3072d30e 7383 if (!df_regs_ever_live_p (i))
875862bf 7384 return i;
7385 return 0;
7386}
9a2a66ae 7387
1e639cb0 7388
ffead1ca 7389/* Helper function for s390_regs_ever_clobbered. Sets the fields in DATA for all
1e639cb0 7390 clobbered hard regs in SETREG. */
7391
7392static void
81a410b1 7393s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *data)
1e639cb0 7394{
ff4ce128 7395 char *regs_ever_clobbered = (char *)data;
1e639cb0 7396 unsigned int i, regno;
7397 enum machine_mode mode = GET_MODE (setreg);
7398
7399 if (GET_CODE (setreg) == SUBREG)
7400 {
7401 rtx inner = SUBREG_REG (setreg);
5ada7a14 7402 if (!GENERAL_REG_P (inner) && !FP_REG_P (inner))
1e639cb0 7403 return;
7404 regno = subreg_regno (setreg);
7405 }
5ada7a14 7406 else if (GENERAL_REG_P (setreg) || FP_REG_P (setreg))
1e639cb0 7407 regno = REGNO (setreg);
7408 else
7409 return;
7410
7411 for (i = regno;
7412 i < regno + HARD_REGNO_NREGS (regno, mode);
7413 i++)
7414 regs_ever_clobbered[i] = 1;
7415}
7416
7417/* Walks through all basic blocks of the current function looking
7418 for clobbered hard regs using s390_reg_clobbered_rtx. The fields
7419 of the passed integer array REGS_EVER_CLOBBERED are set to one for
7420 each of those regs. */
7421
7422static void
ff4ce128 7423s390_regs_ever_clobbered (char regs_ever_clobbered[])
1e639cb0 7424{
7425 basic_block cur_bb;
7426 rtx cur_insn;
7427 unsigned int i;
7428
ff4ce128 7429 memset (regs_ever_clobbered, 0, 32);
1e639cb0 7430
7431 /* For non-leaf functions we have to consider all call clobbered regs to be
7432 clobbered. */
d5bf7b64 7433 if (!crtl->is_leaf)
1e639cb0 7434 {
5ada7a14 7435 for (i = 0; i < 32; i++)
1e639cb0 7436 regs_ever_clobbered[i] = call_really_used_regs[i];
7437 }
7438
7439 /* Make the "magic" eh_return registers live if necessary. For regs_ever_live
7440 this work is done by liveness analysis (mark_regs_live_at_end).
7441 Special care is needed for functions containing landing pads. Landing pads
7442 may use the eh registers, but the code which sets these registers is not
7443 contained in that function. Hence s390_regs_ever_clobbered is not able to
7444 deal with this automatically. */
18d50ae6 7445 if (crtl->calls_eh_return || cfun->machine->has_landing_pad_p)
1e639cb0 7446 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM ; i++)
ffead1ca 7447 if (crtl->calls_eh_return
7448 || (cfun->machine->has_landing_pad_p
3072d30e 7449 && df_regs_ever_live_p (EH_RETURN_DATA_REGNO (i))))
220be973 7450 regs_ever_clobbered[EH_RETURN_DATA_REGNO (i)] = 1;
1e639cb0 7451
7452 /* For nonlocal gotos all call-saved registers have to be saved.
7453 This flag is also set for the unwinding code in libgcc.
7454 See expand_builtin_unwind_init. For regs_ever_live this is done by
7455 reload. */
ff4ce128 7456 if (crtl->saves_all_registers)
5ada7a14 7457 for (i = 0; i < 32; i++)
1e639cb0 7458 if (!call_really_used_regs[i])
7459 regs_ever_clobbered[i] = 1;
7460
fc00614f 7461 FOR_EACH_BB_FN (cur_bb, cfun)
1e639cb0 7462 {
7463 FOR_BB_INSNS (cur_bb, cur_insn)
7464 {
ff4ce128 7465 rtx pat;
7466
7467 if (!INSN_P (cur_insn))
7468 continue;
7469
7470 pat = PATTERN (cur_insn);
7471
7472 /* Ignore GPR restore insns. */
7473 if (epilogue_completed && RTX_FRAME_RELATED_P (cur_insn))
7474 {
7475 if (GET_CODE (pat) == SET
7476 && GENERAL_REG_P (SET_DEST (pat)))
7477 {
7478 /* lgdr */
7479 if (GET_MODE (SET_SRC (pat)) == DImode
7480 && FP_REG_P (SET_SRC (pat)))
7481 continue;
7482
7483 /* l / lg */
7484 if (GET_CODE (SET_SRC (pat)) == MEM)
7485 continue;
7486 }
7487
7488 /* lm / lmg */
7489 if (GET_CODE (pat) == PARALLEL
7490 && load_multiple_operation (pat, VOIDmode))
7491 continue;
7492 }
7493
7494 note_stores (pat,
7495 s390_reg_clobbered_rtx,
7496 regs_ever_clobbered);
1e639cb0 7497 }
7498 }
7499}
7500
ffead1ca 7501/* Determine the frame area which actually has to be accessed
7502 in the function epilogue. The values are stored at the
875862bf 7503 given pointers AREA_BOTTOM (address of the lowest used stack
ffead1ca 7504 address) and AREA_TOP (address of the first item which does
875862bf 7505 not belong to the stack frame). */
5fe74ca1 7506
875862bf 7507static void
7508s390_frame_area (int *area_bottom, int *area_top)
7509{
7510 int b, t;
5fe74ca1 7511
875862bf 7512 b = INT_MAX;
7513 t = INT_MIN;
67928721 7514
7515 if (cfun_frame_layout.first_restore_gpr != -1)
7516 {
7517 b = (cfun_frame_layout.gprs_offset
b5fdc416 7518 + cfun_frame_layout.first_restore_gpr * UNITS_PER_LONG);
67928721 7519 t = b + (cfun_frame_layout.last_restore_gpr
b5fdc416 7520 - cfun_frame_layout.first_restore_gpr + 1) * UNITS_PER_LONG;
67928721 7521 }
7522
7523 if (TARGET_64BIT && cfun_save_high_fprs_p)
7524 {
7525 b = MIN (b, cfun_frame_layout.f8_offset);
7526 t = MAX (t, (cfun_frame_layout.f8_offset
7527 + cfun_frame_layout.high_fprs * 8));
7528 }
7529
7530 if (!TARGET_64BIT)
29439367 7531 {
6a2469fe 7532 if (cfun_fpr_save_p (FPR4_REGNUM))
67928721 7533 {
29439367 7534 b = MIN (b, cfun_frame_layout.f4_offset);
7535 t = MAX (t, cfun_frame_layout.f4_offset + 8);
67928721 7536 }
6a2469fe 7537 if (cfun_fpr_save_p (FPR6_REGNUM))
29439367 7538 {
7539 b = MIN (b, cfun_frame_layout.f4_offset + 8);
7540 t = MAX (t, cfun_frame_layout.f4_offset + 16);
7541 }
7542 }
67928721 7543 *area_bottom = b;
7544 *area_top = t;
7545}
ff4ce128 7546/* Update gpr_save_slots in the frame layout trying to make use of
7547 FPRs as GPR save slots.
7548 This is a helper routine of s390_register_info. */
8b4a4127 7549
7550static void
ff4ce128 7551s390_register_info_gprtofpr ()
8b4a4127 7552{
ff4ce128 7553 int save_reg_slot = FPR0_REGNUM;
8b4a4127 7554 int i, j;
8b4a4127 7555
ff4ce128 7556 if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf)
7557 return;
1e639cb0 7558
ff4ce128 7559 for (i = 15; i >= 6; i--)
5ada7a14 7560 {
ff4ce128 7561 if (cfun_gpr_save_slot (i) == 0)
7562 continue;
68bc0408 7563
ff4ce128 7564 /* Advance to the next FP register which can be used as a
7565 GPR save slot. */
7566 while ((!call_really_used_regs[save_reg_slot]
7567 || df_regs_ever_live_p (save_reg_slot)
7568 || cfun_fpr_save_p (save_reg_slot))
7569 && FP_REGNO_P (save_reg_slot))
7570 save_reg_slot++;
7571 if (!FP_REGNO_P (save_reg_slot))
7572 {
7573 /* We only want to use ldgr/lgdr if we can get rid of
7574 stm/lm entirely. So undo the gpr slot allocation in
7575 case we ran out of FPR save slots. */
7576 for (j = 6; j <= 15; j++)
7577 if (FP_REGNO_P (cfun_gpr_save_slot (j)))
7578 cfun_gpr_save_slot (j) = -1;
7579 break;
68bc0408 7580 }
ff4ce128 7581 cfun_gpr_save_slot (i) = save_reg_slot++;
5ada7a14 7582 }
ff4ce128 7583}
5ada7a14 7584
ff4ce128 7585/* Set the bits in fpr_bitmap for FPRs which need to be saved due to
7586 stdarg.
7587 This is a helper routine for s390_register_info. */
1e639cb0 7588
ff4ce128 7589static void
7590s390_register_info_stdarg_fpr ()
7591{
7592 int i;
7593 int min_fpr;
7594 int max_fpr;
7595
7596 /* Save the FP argument regs for stdarg. f0, f2 for 31 bit and
7597 f0-f4 for 64 bit. */
7598 if (!cfun->stdarg
7599 || !TARGET_HARD_FLOAT
7600 || !cfun->va_list_fpr_size
7601 || crtl->args.info.fprs >= FP_ARG_NUM_REG)
7602 return;
7603
7604 min_fpr = crtl->args.info.fprs;
7605 max_fpr = min_fpr + cfun->va_list_fpr_size;
7606 if (max_fpr > FP_ARG_NUM_REG)
7607 max_fpr = FP_ARG_NUM_REG;
7608
ff4ce128 7609 for (i = min_fpr; i < max_fpr; i++)
7610 cfun_set_fpr_save (i + FPR0_REGNUM);
7611}
7612
7613/* Reserve the GPR save slots for GPRs which need to be saved due to
7614 stdarg.
7615 This is a helper routine for s390_register_info. */
7616
7617static void
7618s390_register_info_stdarg_gpr ()
7619{
7620 int i;
7621 int min_gpr;
7622 int max_gpr;
7623
7624 if (!cfun->stdarg
7625 || !cfun->va_list_gpr_size
7626 || crtl->args.info.gprs >= GP_ARG_NUM_REG)
7627 return;
7628
7629 min_gpr = crtl->args.info.gprs;
7630 max_gpr = min_gpr + cfun->va_list_gpr_size;
7631 if (max_gpr > GP_ARG_NUM_REG)
7632 max_gpr = GP_ARG_NUM_REG;
7633
7634 for (i = min_gpr; i < max_gpr; i++)
7635 cfun_gpr_save_slot (2 + i) = -1;
7636}
7637
7638/* The GPR and FPR save slots in cfun->machine->frame_layout are set
7639 for registers which need to be saved in function prologue.
7640 This function can be used until the insns emitted for save/restore
7641 of the regs are visible in the RTL stream. */
7642
7643static void
7644s390_register_info ()
7645{
7646 int i, j;
7647 char clobbered_regs[32];
7648
7649 gcc_assert (!epilogue_completed);
7650
7651 if (reload_completed)
7652 /* After reload we rely on our own routine to determine which
7653 registers need saving. */
7654 s390_regs_ever_clobbered (clobbered_regs);
7655 else
7656 /* During reload we use regs_ever_live as a base since reload
7657 does changes in there which we otherwise would not be aware
7658 of. */
7659 for (i = 0; i < 32; i++)
7660 clobbered_regs[i] = df_regs_ever_live_p (i);
7661
7662 for (i = 0; i < 32; i++)
7663 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i];
7664
7665 /* Mark the call-saved FPRs which need to be saved.
7666 This needs to be done before checking the special GPRs since the
7667 stack pointer usage depends on whether high FPRs have to be saved
7668 or not. */
7669 cfun_frame_layout.fpr_bitmap = 0;
7670 cfun_frame_layout.high_fprs = 0;
7671 for (i = FPR0_REGNUM; i <= FPR15_REGNUM; i++)
7672 if (clobbered_regs[i] && !call_really_used_regs[i])
7673 {
7674 cfun_set_fpr_save (i);
7675 if (i >= FPR8_REGNUM)
7676 cfun_frame_layout.high_fprs++;
7677 }
9a2a66ae 7678
beee1f75 7679 if (flag_pic)
ffead1ca 7680 clobbered_regs[PIC_OFFSET_TABLE_REGNUM]
ff4ce128 7681 |= !!df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM);
4fed3f99 7682
ffead1ca 7683 clobbered_regs[BASE_REGNUM]
77beec48 7684 |= (cfun->machine->base_reg
ff4ce128 7685 && REGNO (cfun->machine->base_reg) == BASE_REGNUM);
4fed3f99 7686
ff4ce128 7687 clobbered_regs[HARD_FRAME_POINTER_REGNUM]
7688 |= !!frame_pointer_needed;
7689
7690 /* On pre z900 machines this might take until machine dependent
7691 reorg to decide.
7692 save_return_addr_p will only be set on non-zarch machines so
7693 there is no risk that r14 goes into an FPR instead of a stack
7694 slot. */
1e639cb0 7695 clobbered_regs[RETURN_REGNUM]
d5bf7b64 7696 |= (!crtl->is_leaf
9bee2845 7697 || TARGET_TPF_PROFILING
77beec48 7698 || cfun->machine->split_branches_pending_p
7699 || cfun_frame_layout.save_return_addr_p
ff4ce128 7700 || crtl->calls_eh_return);
4fed3f99 7701
1e639cb0 7702 clobbered_regs[STACK_POINTER_REGNUM]
d5bf7b64 7703 |= (!crtl->is_leaf
77beec48 7704 || TARGET_TPF_PROFILING
7705 || cfun_save_high_fprs_p
7706 || get_frame_size () > 0
68bc0408 7707 || (reload_completed && cfun_frame_layout.frame_size > 0)
ff4ce128 7708 || cfun->calls_alloca);
7709
7710 memset (cfun_frame_layout.gpr_save_slots, 0, 16);
1e639cb0 7711
beee1f75 7712 for (i = 6; i < 16; i++)
ff4ce128 7713 if (clobbered_regs[i])
7714 cfun_gpr_save_slot (i) = -1;
9a2a66ae 7715
ff4ce128 7716 s390_register_info_stdarg_fpr ();
7717 s390_register_info_gprtofpr ();
5214e6ae 7718
ff4ce128 7719 /* First find the range of GPRs to be restored. Vararg regs don't
7720 need to be restored so we do it before assigning slots to the
7721 vararg GPRs. */
7722 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7723 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7724 cfun_frame_layout.first_restore_gpr = (i == 16) ? -1 : i;
7725 cfun_frame_layout.last_restore_gpr = (i == 16) ? -1 : j;
5214e6ae 7726
ff4ce128 7727 /* stdarg functions might need to save GPRs 2 to 6. This might
7728 override the GPR->FPR save decision made above for r6 since
7729 vararg regs must go to the stack. */
7730 s390_register_info_stdarg_gpr ();
ffead1ca 7731
ff4ce128 7732 /* Now the range of GPRs which need saving. */
7733 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7734 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7735 cfun_frame_layout.first_save_gpr = (i == 16) ? -1 : i;
7736 cfun_frame_layout.last_save_gpr = (i == 16) ? -1 : j;
7737}
9a2a66ae 7738
ff4ce128 7739/* This function is called by s390_optimize_prologue in order to get
7740 rid of unnecessary GPR save/restore instructions. The register info
7741 for the GPRs is re-computed and the ranges are re-calculated. */
6902d973 7742
ff4ce128 7743static void
7744s390_optimize_register_info ()
7745{
7746 char clobbered_regs[32];
7747 int i, j;
6902d973 7748
ff4ce128 7749 gcc_assert (epilogue_completed);
7750 gcc_assert (!cfun->machine->split_branches_pending_p);
beee1f75 7751
ff4ce128 7752 s390_regs_ever_clobbered (clobbered_regs);
6902d973 7753
ff4ce128 7754 for (i = 0; i < 32; i++)
7755 clobbered_regs[i] = clobbered_regs[i] && !global_regs[i];
6902d973 7756
ff4ce128 7757 /* There is still special treatment needed for cases invisible to
7758 s390_regs_ever_clobbered. */
7759 clobbered_regs[RETURN_REGNUM]
7760 |= (TARGET_TPF_PROFILING
7761 /* When expanding builtin_return_addr in ESA mode we do not
7762 know whether r14 will later be needed as scratch reg when
7763 doing branch splitting. So the builtin always accesses the
7764 r14 save slot and we need to stick to the save/restore
7765 decision for r14 even if it turns out that it didn't get
7766 clobbered. */
7767 || cfun_frame_layout.save_return_addr_p
7768 || crtl->calls_eh_return);
7769
7770 memset (cfun_frame_layout.gpr_save_slots, 0, 6);
7771
7772 for (i = 6; i < 16; i++)
7773 if (!clobbered_regs[i])
7774 cfun_gpr_save_slot (i) = 0;
7775
7776 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7777 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7778 cfun_frame_layout.first_restore_gpr = (i == 16) ? -1 : i;
7779 cfun_frame_layout.last_restore_gpr = (i == 16) ? -1 : j;
7780
7781 s390_register_info_stdarg_gpr ();
7782
7783 for (i = 0; i < 16 && cfun_gpr_save_slot (i) != -1; i++);
7784 for (j = 15; j > i && cfun_gpr_save_slot (j) != -1; j--);
7785 cfun_frame_layout.first_save_gpr = (i == 16) ? -1 : i;
7786 cfun_frame_layout.last_save_gpr = (i == 16) ? -1 : j;
67928721 7787}
7788
4fed3f99 7789/* Fill cfun->machine with info about frame of current function. */
67928721 7790
7791static void
4fed3f99 7792s390_frame_info (void)
67928721 7793{
62eb9236 7794 HOST_WIDE_INT lowest_offset;
67928721 7795
ff4ce128 7796 cfun_frame_layout.first_save_gpr_slot = cfun_frame_layout.first_save_gpr;
7797 cfun_frame_layout.last_save_gpr_slot = cfun_frame_layout.last_save_gpr;
7798
7799 /* The va_arg builtin uses a constant distance of 16 *
7800 UNITS_PER_LONG (r0-r15) to reach the FPRs from the reg_save_area
7801 pointer. So even if we are going to save the stack pointer in an
7802 FPR we need the stack space in order to keep the offsets
7803 correct. */
7804 if (cfun->stdarg && cfun_save_arg_fprs_p)
7805 {
7806 cfun_frame_layout.last_save_gpr_slot = STACK_POINTER_REGNUM;
7807
7808 if (cfun_frame_layout.first_save_gpr_slot == -1)
7809 cfun_frame_layout.first_save_gpr_slot = STACK_POINTER_REGNUM;
7810 }
7811
67928721 7812 cfun_frame_layout.frame_size = get_frame_size ();
67928721 7813 if (!TARGET_64BIT && cfun_frame_layout.frame_size > 0x7fff0000)
3284a242 7814 fatal_error ("total size of local variables exceeds architecture limit");
ffead1ca 7815
646a946e 7816 if (!TARGET_PACKED_STACK)
67928721 7817 {
62eb9236 7818 /* Fixed stack layout. */
67928721 7819 cfun_frame_layout.backchain_offset = 0;
b5fdc416 7820 cfun_frame_layout.f0_offset = 16 * UNITS_PER_LONG;
67928721 7821 cfun_frame_layout.f4_offset = cfun_frame_layout.f0_offset + 2 * 8;
7822 cfun_frame_layout.f8_offset = -cfun_frame_layout.high_fprs * 8;
5214e6ae 7823 cfun_frame_layout.gprs_offset = (cfun_frame_layout.first_save_gpr_slot
b5fdc416 7824 * UNITS_PER_LONG);
67928721 7825 }
62eb9236 7826 else if (TARGET_BACKCHAIN)
67928721 7827 {
62eb9236 7828 /* Kernel stack layout - packed stack, backchain, no float */
7829 gcc_assert (TARGET_SOFT_FLOAT);
67928721 7830 cfun_frame_layout.backchain_offset = (STACK_POINTER_OFFSET
b5fdc416 7831 - UNITS_PER_LONG);
62eb9236 7832
7833 /* The distance between the backchain and the return address
7834 save slot must not change. So we always need a slot for the
7835 stack pointer which resides in between. */
7836 cfun_frame_layout.last_save_gpr_slot = STACK_POINTER_REGNUM;
7837
ffead1ca 7838 cfun_frame_layout.gprs_offset
62eb9236 7839 = cfun_frame_layout.backchain_offset - cfun_gprs_save_area_size;
ffead1ca 7840
62eb9236 7841 /* FPRs will not be saved. Nevertheless pick sane values to
7842 keep area calculations valid. */
7843 cfun_frame_layout.f0_offset =
7844 cfun_frame_layout.f4_offset =
7845 cfun_frame_layout.f8_offset = cfun_frame_layout.gprs_offset;
67928721 7846 }
62eb9236 7847 else
67928721 7848 {
031bdf83 7849 int num_fprs;
7850
62eb9236 7851 /* Packed stack layout without backchain. */
ffead1ca 7852
031bdf83 7853 /* With stdarg FPRs need their dedicated slots. */
7854 num_fprs = (TARGET_64BIT && cfun->stdarg ? 2
7855 : (cfun_fpr_save_p (FPR4_REGNUM) +
7856 cfun_fpr_save_p (FPR6_REGNUM)));
7857 cfun_frame_layout.f4_offset = STACK_POINTER_OFFSET - 8 * num_fprs;
7858
7859 num_fprs = (cfun->stdarg ? 2
7860 : (cfun_fpr_save_p (FPR0_REGNUM)
7861 + cfun_fpr_save_p (FPR2_REGNUM)));
7862 cfun_frame_layout.f0_offset = cfun_frame_layout.f4_offset - 8 * num_fprs;
ffead1ca 7863
7864 cfun_frame_layout.gprs_offset
67928721 7865 = cfun_frame_layout.f0_offset - cfun_gprs_save_area_size;
62eb9236 7866
7867 cfun_frame_layout.f8_offset = (cfun_frame_layout.gprs_offset
7868 - cfun_frame_layout.high_fprs * 8);
67928721 7869 }
7870
62eb9236 7871 if (cfun_save_high_fprs_p)
7872 cfun_frame_layout.frame_size += cfun_frame_layout.high_fprs * 8;
7873
7874 if (!crtl->is_leaf)
7875 cfun_frame_layout.frame_size += crtl->outgoing_args_size;
7876
7877 /* In the following cases we have to allocate a STACK_POINTER_OFFSET
7878 sized area at the bottom of the stack. This is required also for
7879 leaf functions. When GCC generates a local stack reference it
7880 will always add STACK_POINTER_OFFSET to all these references. */
d5bf7b64 7881 if (crtl->is_leaf
67928721 7882 && !TARGET_TPF_PROFILING
7883 && cfun_frame_layout.frame_size == 0
ff4ce128 7884 && !cfun->calls_alloca)
67928721 7885 return;
7886
62eb9236 7887 /* Calculate the number of bytes we have used in our own register
7888 save area. With the packed stack layout we can re-use the
7889 remaining bytes for normal stack elements. */
67928721 7890
62eb9236 7891 if (TARGET_PACKED_STACK)
7892 lowest_offset = MIN (MIN (cfun_frame_layout.f0_offset,
7893 cfun_frame_layout.f4_offset),
7894 cfun_frame_layout.gprs_offset);
7895 else
7896 lowest_offset = 0;
ffead1ca 7897
62eb9236 7898 if (TARGET_BACKCHAIN)
7899 lowest_offset = MIN (lowest_offset, cfun_frame_layout.backchain_offset);
ffead1ca 7900
62eb9236 7901 cfun_frame_layout.frame_size += STACK_POINTER_OFFSET - lowest_offset;
67928721 7902
62eb9236 7903 /* If under 31 bit an odd number of gprs has to be saved we have to
7904 adjust the frame size to sustain 8 byte alignment of stack
7905 frames. */
7906 cfun_frame_layout.frame_size = ((cfun_frame_layout.frame_size +
7907 STACK_BOUNDARY / BITS_PER_UNIT - 1)
7908 & ~(STACK_BOUNDARY / BITS_PER_UNIT - 1));
8b4a4127 7909}
7910
4fed3f99 7911/* Generate frame layout. Fills in register and frame data for the current
7912 function in cfun->machine. This routine can be called multiple times;
7913 it will re-do the complete frame layout every time. */
8b4a4127 7914
4fed3f99 7915static void
7916s390_init_frame_layout (void)
4673c1a0 7917{
4fed3f99 7918 HOST_WIDE_INT frame_size;
7919 int base_used;
ff4ce128 7920
7921 gcc_assert (!reload_completed);
beee1f75 7922
4fed3f99 7923 /* On S/390 machines, we may need to perform branch splitting, which
7924 will require both base and return address register. We have no
7925 choice but to assume we're going to need them until right at the
7926 end of the machine dependent reorg phase. */
7927 if (!TARGET_CPU_ZARCH)
7928 cfun->machine->split_branches_pending_p = true;
7929
7930 do
7931 {
7932 frame_size = cfun_frame_layout.frame_size;
7933
7934 /* Try to predict whether we'll need the base register. */
7935 base_used = cfun->machine->split_branches_pending_p
18d50ae6 7936 || crtl->uses_const_pool
3ea2a559 7937 || (!DISP_IN_RANGE (frame_size)
7938 && !CONST_OK_FOR_K (frame_size));
4fed3f99 7939
7940 /* Decide which register to use as literal pool base. In small
7941 leaf functions, try to use an unused call-clobbered register
7942 as base register to avoid save/restore overhead. */
7943 if (!base_used)
7944 cfun->machine->base_reg = NULL_RTX;
d5bf7b64 7945 else if (crtl->is_leaf && !df_regs_ever_live_p (5))
4fed3f99 7946 cfun->machine->base_reg = gen_rtx_REG (Pmode, 5);
7947 else
7948 cfun->machine->base_reg = gen_rtx_REG (Pmode, BASE_REGNUM);
67928721 7949
ff4ce128 7950 s390_register_info ();
4fed3f99 7951 s390_frame_info ();
7952 }
7953 while (frame_size != cfun_frame_layout.frame_size);
4673c1a0 7954}
7955
5ada7a14 7956/* Remove the FPR clobbers from a tbegin insn if it can be proven that
7957 the TX is nonescaping. A transaction is considered escaping if
7958 there is at least one path from tbegin returning CC0 to the
7959 function exit block without an tend.
7960
7961 The check so far has some limitations:
7962 - only single tbegin/tend BBs are supported
7963 - the first cond jump after tbegin must separate the CC0 path from ~CC0
7964 - when CC is copied to a GPR and the CC0 check is done with the GPR
7965 this is not supported
7966*/
7967
7968static void
7969s390_optimize_nonescaping_tx (void)
7970{
7971 const unsigned int CC0 = 1 << 3;
7972 basic_block tbegin_bb = NULL;
7973 basic_block tend_bb = NULL;
7974 basic_block bb;
7975 rtx insn;
7976 bool result = true;
7977 int bb_index;
7978 rtx tbegin_insn = NULL_RTX;
7979
7980 if (!cfun->machine->tbegin_p)
7981 return;
7982
a28770e1 7983 for (bb_index = 0; bb_index < n_basic_blocks_for_fn (cfun); bb_index++)
5ada7a14 7984 {
f5a6b05f 7985 bb = BASIC_BLOCK_FOR_FN (cfun, bb_index);
5ada7a14 7986
91dfd73e 7987 if (!bb)
7988 continue;
7989
5ada7a14 7990 FOR_BB_INSNS (bb, insn)
7991 {
7992 rtx ite, cc, pat, target;
7993 unsigned HOST_WIDE_INT mask;
7994
7995 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
7996 continue;
7997
7998 pat = PATTERN (insn);
7999
8000 if (GET_CODE (pat) == PARALLEL)
8001 pat = XVECEXP (pat, 0, 0);
8002
8003 if (GET_CODE (pat) != SET
8004 || GET_CODE (SET_SRC (pat)) != UNSPEC_VOLATILE)
8005 continue;
8006
8007 if (XINT (SET_SRC (pat), 1) == UNSPECV_TBEGIN)
8008 {
8009 rtx tmp;
8010
8011 tbegin_insn = insn;
8012
8013 /* Just return if the tbegin doesn't have clobbers. */
8014 if (GET_CODE (PATTERN (insn)) != PARALLEL)
8015 return;
8016
8017 if (tbegin_bb != NULL)
8018 return;
8019
8020 /* Find the next conditional jump. */
8021 for (tmp = NEXT_INSN (insn);
8022 tmp != NULL_RTX;
8023 tmp = NEXT_INSN (tmp))
8024 {
8025 if (reg_set_p (gen_rtx_REG (CCmode, CC_REGNUM), tmp))
8026 return;
8027 if (!JUMP_P (tmp))
8028 continue;
8029
8030 ite = SET_SRC (PATTERN (tmp));
8031 if (GET_CODE (ite) != IF_THEN_ELSE)
8032 continue;
8033
8034 cc = XEXP (XEXP (ite, 0), 0);
8035 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc))
8036 || GET_MODE (cc) != CCRAWmode
8037 || GET_CODE (XEXP (XEXP (ite, 0), 1)) != CONST_INT)
8038 return;
8039
8040 if (bb->succs->length () != 2)
8041 return;
8042
8043 mask = INTVAL (XEXP (XEXP (ite, 0), 1));
8044 if (GET_CODE (XEXP (ite, 0)) == NE)
8045 mask ^= 0xf;
8046
8047 if (mask == CC0)
8048 target = XEXP (ite, 1);
8049 else if (mask == (CC0 ^ 0xf))
8050 target = XEXP (ite, 2);
8051 else
8052 return;
8053
8054 {
8055 edge_iterator ei;
8056 edge e1, e2;
8057
8058 ei = ei_start (bb->succs);
8059 e1 = ei_safe_edge (ei);
8060 ei_next (&ei);
8061 e2 = ei_safe_edge (ei);
8062
8063 if (e2->flags & EDGE_FALLTHRU)
8064 {
8065 e2 = e1;
8066 e1 = ei_safe_edge (ei);
8067 }
8068
8069 if (!(e1->flags & EDGE_FALLTHRU))
8070 return;
8071
8072 tbegin_bb = (target == pc_rtx) ? e1->dest : e2->dest;
8073 }
8074 if (tmp == BB_END (bb))
8075 break;
8076 }
8077 }
8078
8079 if (XINT (SET_SRC (pat), 1) == UNSPECV_TEND)
8080 {
8081 if (tend_bb != NULL)
8082 return;
8083 tend_bb = bb;
8084 }
8085 }
8086 }
8087
8088 /* Either we successfully remove the FPR clobbers here or we are not
8089 able to do anything for this TX. Both cases don't qualify for
8090 another look. */
8091 cfun->machine->tbegin_p = false;
8092
8093 if (tbegin_bb == NULL || tend_bb == NULL)
8094 return;
8095
8096 calculate_dominance_info (CDI_POST_DOMINATORS);
8097 result = dominated_by_p (CDI_POST_DOMINATORS, tbegin_bb, tend_bb);
8098 free_dominance_info (CDI_POST_DOMINATORS);
8099
8100 if (!result)
8101 return;
8102
91dfd73e 8103 PATTERN (tbegin_insn) = gen_rtx_PARALLEL (VOIDmode,
8104 gen_rtvec (2,
8105 XVECEXP (PATTERN (tbegin_insn), 0, 0),
8106 XVECEXP (PATTERN (tbegin_insn), 0, 1)));
5ada7a14 8107 INSN_CODE (tbegin_insn) = -1;
8108 df_insn_rescan (tbegin_insn);
8109
8110 return;
8111}
8112
8f1128bb 8113/* Return true if it is legal to put a value with MODE into REGNO. */
8114
8115bool
8116s390_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
8117{
8118 switch (REGNO_REG_CLASS (regno))
8119 {
8120 case FP_REGS:
8121 if (REGNO_PAIR_OK (regno, mode))
8122 {
8123 if (mode == SImode || mode == DImode)
8124 return true;
8125
8126 if (FLOAT_MODE_P (mode) && GET_MODE_CLASS (mode) != MODE_VECTOR_FLOAT)
8127 return true;
8128 }
8129 break;
8130 case ADDR_REGS:
8131 if (FRAME_REGNO_P (regno) && mode == Pmode)
8132 return true;
8133
8134 /* fallthrough */
8135 case GENERAL_REGS:
8136 if (REGNO_PAIR_OK (regno, mode))
8137 {
b5fdc416 8138 if (TARGET_ZARCH
36868490 8139 || (mode != TFmode && mode != TCmode && mode != TDmode))
8f1128bb 8140 return true;
ffead1ca 8141 }
8f1128bb 8142 break;
8143 case CC_REGS:
8144 if (GET_MODE_CLASS (mode) == MODE_CC)
8145 return true;
8146 break;
8147 case ACCESS_REGS:
8148 if (REGNO_PAIR_OK (regno, mode))
8149 {
8150 if (mode == SImode || mode == Pmode)
8151 return true;
8152 }
8153 break;
8154 default:
8155 return false;
8156 }
ffead1ca 8157
8f1128bb 8158 return false;
8159}
8160
d1a5573e 8161/* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */
8162
8163bool
8164s390_hard_regno_rename_ok (unsigned int old_reg, unsigned int new_reg)
8165{
8166 /* Once we've decided upon a register to use as base register, it must
8167 no longer be used for any other purpose. */
8168 if (cfun->machine->base_reg)
8169 if (REGNO (cfun->machine->base_reg) == old_reg
8170 || REGNO (cfun->machine->base_reg) == new_reg)
8171 return false;
8172
ff4ce128 8173 /* Prevent regrename from using call-saved regs which haven't
8174 actually been saved. This is necessary since regrename assumes
8175 the backend save/restore decisions are based on
8176 df_regs_ever_live. Since we have our own routine we have to tell
8177 regrename manually about it. */
8178 if (GENERAL_REGNO_P (new_reg)
8179 && !call_really_used_regs[new_reg]
8180 && cfun_gpr_save_slot (new_reg) == 0)
8181 return false;
8182
8183 return true;
8184}
8185
8186/* Return nonzero if register REGNO can be used as a scratch register
8187 in peephole2. */
8188
8189static bool
8190s390_hard_regno_scratch_ok (unsigned int regno)
8191{
8192 /* See s390_hard_regno_rename_ok. */
8193 if (GENERAL_REGNO_P (regno)
8194 && !call_really_used_regs[regno]
8195 && cfun_gpr_save_slot (regno) == 0)
8196 return false;
8197
d1a5573e 8198 return true;
8199}
8200
8f1128bb 8201/* Maximum number of registers to represent a value of mode MODE
8deb3959 8202 in a register of class RCLASS. */
8f1128bb 8203
6c2d82ab 8204int
8deb3959 8205s390_class_max_nregs (enum reg_class rclass, enum machine_mode mode)
8f1128bb 8206{
8deb3959 8207 switch (rclass)
8f1128bb 8208 {
8209 case FP_REGS:
8210 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
8211 return 2 * ((GET_MODE_SIZE (mode) / 2 + 8 - 1) / 8);
8212 else
8213 return (GET_MODE_SIZE (mode) + 8 - 1) / 8;
8214 case ACCESS_REGS:
8215 return (GET_MODE_SIZE (mode) + 4 - 1) / 4;
8216 default:
8217 break;
8218 }
8219 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
8220}
8221
7b1bda1c 8222/* Return true if we use LRA instead of reload pass. */
8223static bool
8224s390_lra_p (void)
8225{
8226 return s390_lra_flag;
8227}
8228
4fed3f99 8229/* Return true if register FROM can be eliminated via register TO. */
8230
cd90919d 8231static bool
8232s390_can_eliminate (const int from, const int to)
4fed3f99 8233{
d1a5573e 8234 /* On zSeries machines, we have not marked the base register as fixed.
8235 Instead, we have an elimination rule BASE_REGNUM -> BASE_REGNUM.
8236 If a function requires the base register, we say here that this
8237 elimination cannot be performed. This will cause reload to free
8238 up the base register (as if it were fixed). On the other hand,
8239 if the current function does *not* require the base register, we
8240 say here the elimination succeeds, which in turn allows reload
8241 to allocate the base register for any other purpose. */
8242 if (from == BASE_REGNUM && to == BASE_REGNUM)
8243 {
8244 if (TARGET_CPU_ZARCH)
8245 {
8246 s390_init_frame_layout ();
8247 return cfun->machine->base_reg == NULL_RTX;
8248 }
8249
8250 return false;
8251 }
8252
8253 /* Everything else must point into the stack frame. */
4fed3f99 8254 gcc_assert (to == STACK_POINTER_REGNUM
8255 || to == HARD_FRAME_POINTER_REGNUM);
8256
8257 gcc_assert (from == FRAME_POINTER_REGNUM
8258 || from == ARG_POINTER_REGNUM
8259 || from == RETURN_ADDRESS_POINTER_REGNUM);
8260
8261 /* Make sure we actually saved the return address. */
8262 if (from == RETURN_ADDRESS_POINTER_REGNUM)
18d50ae6 8263 if (!crtl->calls_eh_return
8264 && !cfun->stdarg
4fed3f99 8265 && !cfun_frame_layout.save_return_addr_p)
8266 return false;
8267
8268 return true;
8269}
8270
8271/* Return offset between register FROM and TO initially after prolog. */
7cbfc974 8272
8273HOST_WIDE_INT
4fed3f99 8274s390_initial_elimination_offset (int from, int to)
7cbfc974 8275{
4fed3f99 8276 HOST_WIDE_INT offset;
7cbfc974 8277
4fed3f99 8278 /* ??? Why are we called for non-eliminable pairs? */
8279 if (!s390_can_eliminate (from, to))
8280 return 0;
8281
8282 switch (from)
8283 {
8284 case FRAME_POINTER_REGNUM:
ffead1ca 8285 offset = (get_frame_size()
119114cb 8286 + STACK_POINTER_OFFSET
abe32cce 8287 + crtl->outgoing_args_size);
4fed3f99 8288 break;
67928721 8289
4fed3f99 8290 case ARG_POINTER_REGNUM:
8291 s390_init_frame_layout ();
8292 offset = cfun_frame_layout.frame_size + STACK_POINTER_OFFSET;
8293 break;
8294
8295 case RETURN_ADDRESS_POINTER_REGNUM:
8296 s390_init_frame_layout ();
ff4ce128 8297
8298 if (cfun_frame_layout.first_save_gpr_slot == -1)
8299 {
8300 /* If it turns out that for stdarg nothing went into the reg
8301 save area we also do not need the return address
8302 pointer. */
8303 if (cfun->stdarg && !cfun_save_arg_fprs_p)
8304 return 0;
8305
8306 gcc_unreachable ();
8307 }
8308
8309 /* In order to make the following work it is not necessary for
8310 r14 to have a save slot. It is sufficient if one other GPR
8311 got one. Since the GPRs are always stored without gaps we
8312 are able to calculate where the r14 save slot would
8313 reside. */
8314 offset = (cfun_frame_layout.frame_size + cfun_frame_layout.gprs_offset +
8315 (RETURN_REGNUM - cfun_frame_layout.first_save_gpr_slot) *
8316 UNITS_PER_LONG);
4fed3f99 8317 break;
8318
d1a5573e 8319 case BASE_REGNUM:
8320 offset = 0;
8321 break;
8322
4fed3f99 8323 default:
8324 gcc_unreachable ();
8325 }
8326
8327 return offset;
7cbfc974 8328}
8329
8b4a4127 8330/* Emit insn to save fpr REGNUM at offset OFFSET relative
f81e845f 8331 to register BASE. Return generated insn. */
56769981 8332
4673c1a0 8333static rtx
b40da9a7 8334save_fpr (rtx base, int offset, int regnum)
4673c1a0 8335{
8b4a4127 8336 rtx addr;
29c05e22 8337 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
ce1d5a67 8338
8339 if (regnum >= 16 && regnum <= (16 + FP_ARG_NUM_REG))
8340 set_mem_alias_set (addr, get_varargs_alias_set ());
8341 else
8342 set_mem_alias_set (addr, get_frame_alias_set ());
4673c1a0 8343
8b4a4127 8344 return emit_move_insn (addr, gen_rtx_REG (DFmode, regnum));
8345}
4673c1a0 8346
8b4a4127 8347/* Emit insn to restore fpr REGNUM from offset OFFSET relative
f81e845f 8348 to register BASE. Return generated insn. */
4673c1a0 8349
8b4a4127 8350static rtx
b40da9a7 8351restore_fpr (rtx base, int offset, int regnum)
8b4a4127 8352{
8353 rtx addr;
29c05e22 8354 addr = gen_rtx_MEM (DFmode, plus_constant (Pmode, base, offset));
ce1d5a67 8355 set_mem_alias_set (addr, get_frame_alias_set ());
4673c1a0 8356
8b4a4127 8357 return emit_move_insn (gen_rtx_REG (DFmode, regnum), addr);
4673c1a0 8358}
8359
a3cd0f6a 8360/* Return true if REGNO is a global register, but not one
8361 of the special ones that need to be saved/restored in anyway. */
8362
8363static inline bool
8364global_not_special_regno_p (int regno)
8365{
8366 return (global_regs[regno]
8367 /* These registers are special and need to be
8368 restored in any case. */
8369 && !(regno == STACK_POINTER_REGNUM
8370 || regno == RETURN_REGNUM
8371 || regno == BASE_REGNUM
8372 || (flag_pic && regno == (int)PIC_OFFSET_TABLE_REGNUM)));
8373}
8374
9a2a66ae 8375/* Generate insn to save registers FIRST to LAST into
f81e845f 8376 the register save area located at offset OFFSET
9a2a66ae 8377 relative to register BASE. */
4673c1a0 8378
9a2a66ae 8379static rtx
b40da9a7 8380save_gprs (rtx base, int offset, int first, int last)
4673c1a0 8381{
9a2a66ae 8382 rtx addr, insn, note;
8383 int i;
8384
29c05e22 8385 addr = plus_constant (Pmode, base, offset);
9a2a66ae 8386 addr = gen_rtx_MEM (Pmode, addr);
ce1d5a67 8387
8388 set_mem_alias_set (addr, get_frame_alias_set ());
9a2a66ae 8389
8390 /* Special-case single register. */
8391 if (first == last)
8392 {
8393 if (TARGET_64BIT)
8394 insn = gen_movdi (addr, gen_rtx_REG (Pmode, first));
8395 else
8396 insn = gen_movsi (addr, gen_rtx_REG (Pmode, first));
8397
a3cd0f6a 8398 if (!global_not_special_regno_p (first))
8399 RTX_FRAME_RELATED_P (insn) = 1;
9a2a66ae 8400 return insn;
8401 }
8402
8403
8404 insn = gen_store_multiple (addr,
8405 gen_rtx_REG (Pmode, first),
8406 GEN_INT (last - first + 1));
8407
18d50ae6 8408 if (first <= 6 && cfun->stdarg)
ce1d5a67 8409 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
8410 {
8411 rtx mem = XEXP (XVECEXP (PATTERN (insn), 0, i), 0);
ffead1ca 8412
ce1d5a67 8413 if (first + i <= 6)
8414 set_mem_alias_set (mem, get_varargs_alias_set ());
8415 }
9a2a66ae 8416
8417 /* We need to set the FRAME_RELATED flag on all SETs
8418 inside the store-multiple pattern.
8419
8420 However, we must not emit DWARF records for registers 2..5
f81e845f 8421 if they are stored for use by variable arguments ...
9a2a66ae 8422
3ce7ff97 8423 ??? Unfortunately, it is not enough to simply not the
9a2a66ae 8424 FRAME_RELATED flags for those SETs, because the first SET
8425 of the PARALLEL is always treated as if it had the flag
8426 set, even if it does not. Therefore we emit a new pattern
8427 without those registers as REG_FRAME_RELATED_EXPR note. */
8428
a3cd0f6a 8429 if (first >= 6 && !global_not_special_regno_p (first))
9a2a66ae 8430 {
8431 rtx pat = PATTERN (insn);
8432
8433 for (i = 0; i < XVECLEN (pat, 0); i++)
a3cd0f6a 8434 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
8435 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (pat,
8436 0, i)))))
9a2a66ae 8437 RTX_FRAME_RELATED_P (XVECEXP (pat, 0, i)) = 1;
8438
8439 RTX_FRAME_RELATED_P (insn) = 1;
8440 }
8441 else if (last >= 6)
8442 {
a3cd0f6a 8443 int start;
8444
8445 for (start = first >= 6 ? first : 6; start <= last; start++)
8446 if (!global_not_special_regno_p (start))
8447 break;
8448
8449 if (start > last)
8450 return insn;
8451
29c05e22 8452 addr = plus_constant (Pmode, base,
8453 offset + (start - first) * UNITS_PER_LONG);
ff4ce128 8454
8455 if (start == last)
8456 {
8457 if (TARGET_64BIT)
8458 note = gen_movdi (gen_rtx_MEM (Pmode, addr),
8459 gen_rtx_REG (Pmode, start));
8460 else
8461 note = gen_movsi (gen_rtx_MEM (Pmode, addr),
8462 gen_rtx_REG (Pmode, start));
8463 note = PATTERN (note);
8464
8465 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
8466 RTX_FRAME_RELATED_P (insn) = 1;
8467
8468 return insn;
8469 }
8470
f81e845f 8471 note = gen_store_multiple (gen_rtx_MEM (Pmode, addr),
a3cd0f6a 8472 gen_rtx_REG (Pmode, start),
8473 GEN_INT (last - start + 1));
9a2a66ae 8474 note = PATTERN (note);
8475
b9c74b4d 8476 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note);
9a2a66ae 8477
8478 for (i = 0; i < XVECLEN (note, 0); i++)
a3cd0f6a 8479 if (GET_CODE (XVECEXP (note, 0, i)) == SET
8480 && !global_not_special_regno_p (REGNO (SET_SRC (XVECEXP (note,
8481 0, i)))))
9a2a66ae 8482 RTX_FRAME_RELATED_P (XVECEXP (note, 0, i)) = 1;
8483
8484 RTX_FRAME_RELATED_P (insn) = 1;
8485 }
8486
8487 return insn;
8b4a4127 8488}
4673c1a0 8489
9a2a66ae 8490/* Generate insn to restore registers FIRST to LAST from
f81e845f 8491 the register save area located at offset OFFSET
9a2a66ae 8492 relative to register BASE. */
4673c1a0 8493
9a2a66ae 8494static rtx
b40da9a7 8495restore_gprs (rtx base, int offset, int first, int last)
8b4a4127 8496{
9a2a66ae 8497 rtx addr, insn;
8498
29c05e22 8499 addr = plus_constant (Pmode, base, offset);
9a2a66ae 8500 addr = gen_rtx_MEM (Pmode, addr);
ce1d5a67 8501 set_mem_alias_set (addr, get_frame_alias_set ());
9a2a66ae 8502
8503 /* Special-case single register. */
8504 if (first == last)
8505 {
8506 if (TARGET_64BIT)
8507 insn = gen_movdi (gen_rtx_REG (Pmode, first), addr);
8508 else
8509 insn = gen_movsi (gen_rtx_REG (Pmode, first), addr);
8510
ff4ce128 8511 RTX_FRAME_RELATED_P (insn) = 1;
9a2a66ae 8512 return insn;
8513 }
8514
8515 insn = gen_load_multiple (gen_rtx_REG (Pmode, first),
8516 addr,
8517 GEN_INT (last - first + 1));
ff4ce128 8518 RTX_FRAME_RELATED_P (insn) = 1;
9a2a66ae 8519 return insn;
8b4a4127 8520}
4673c1a0 8521
20074f87 8522/* Return insn sequence to load the GOT register. */
12ef3745 8523
8524static GTY(()) rtx got_symbol;
20074f87 8525rtx
8526s390_load_got (void)
12ef3745 8527{
20074f87 8528 rtx insns;
8529
c60a7572 8530 /* We cannot use pic_offset_table_rtx here since we use this
8531 function also for non-pic if __tls_get_offset is called and in
8532 that case PIC_OFFSET_TABLE_REGNUM as well as pic_offset_table_rtx
8533 aren't usable. */
8534 rtx got_rtx = gen_rtx_REG (Pmode, 12);
8535
12ef3745 8536 if (!got_symbol)
8537 {
8538 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
8539 SYMBOL_REF_FLAGS (got_symbol) = SYMBOL_FLAG_LOCAL;
8540 }
8541
20074f87 8542 start_sequence ();
8543
dafc8d45 8544 if (TARGET_CPU_ZARCH)
12ef3745 8545 {
c60a7572 8546 emit_move_insn (got_rtx, got_symbol);
12ef3745 8547 }
8548 else
8549 {
20074f87 8550 rtx offset;
12ef3745 8551
f81e845f 8552 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, got_symbol),
12ef3745 8553 UNSPEC_LTREL_OFFSET);
8554 offset = gen_rtx_CONST (Pmode, offset);
8555 offset = force_const_mem (Pmode, offset);
8556
c60a7572 8557 emit_move_insn (got_rtx, offset);
12ef3745 8558
f81e845f 8559 offset = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (offset, 0)),
12ef3745 8560 UNSPEC_LTREL_BASE);
c60a7572 8561 offset = gen_rtx_PLUS (Pmode, got_rtx, offset);
12ef3745 8562
c60a7572 8563 emit_move_insn (got_rtx, offset);
12ef3745 8564 }
20074f87 8565
8566 insns = get_insns ();
8567 end_sequence ();
8568 return insns;
12ef3745 8569}
8570
062c49fd 8571/* This ties together stack memory (MEM with an alias set of frame_alias_set)
8572 and the change to the stack pointer. */
8573
8574static void
8575s390_emit_stack_tie (void)
8576{
8577 rtx mem = gen_frame_mem (BLKmode,
8578 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
8579
8580 emit_insn (gen_stack_tie (mem));
8581}
8582
ff4ce128 8583/* Copy GPRS into FPR save slots. */
8584
8585static void
8586s390_save_gprs_to_fprs (void)
8587{
8588 int i;
8589
8590 if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf)
8591 return;
8592
8593 for (i = 6; i < 16; i++)
8594 {
8595 if (FP_REGNO_P (cfun_gpr_save_slot (i)))
8596 {
8597 rtx insn =
8598 emit_move_insn (gen_rtx_REG (DImode, cfun_gpr_save_slot (i)),
8599 gen_rtx_REG (DImode, i));
8600 RTX_FRAME_RELATED_P (insn) = 1;
8601 }
8602 }
8603}
8604
8605/* Restore GPRs from FPR save slots. */
8606
8607static void
8608s390_restore_gprs_from_fprs (void)
8609{
8610 int i;
8611
8612 if (!TARGET_Z10 || !TARGET_HARD_FLOAT || !crtl->is_leaf)
8613 return;
8614
8615 for (i = 6; i < 16; i++)
8616 {
8617 if (FP_REGNO_P (cfun_gpr_save_slot (i)))
8618 {
8619 rtx insn =
8620 emit_move_insn (gen_rtx_REG (DImode, i),
8621 gen_rtx_REG (DImode, cfun_gpr_save_slot (i)));
8622 df_set_regs_ever_live (i, true);
8623 /* The frame related flag is only required on the save
8624 operations. We nevertheless set it also for the restore
8625 in order to recognize these instructions in
8626 s390_optimize_prologue. The flag will then be
8627 deleted. */
8628 RTX_FRAME_RELATED_P (insn) = 1;
8629 }
8630 }
8631}
8632
8b4a4127 8633/* Expand the prologue into a bunch of separate insns. */
4673c1a0 8634
8b4a4127 8635void
b40da9a7 8636s390_emit_prologue (void)
8b4a4127 8637{
8b4a4127 8638 rtx insn, addr;
8639 rtx temp_reg;
7bbebc45 8640 int i;
67928721 8641 int offset;
8642 int next_fpr = 0;
4673c1a0 8643
5ada7a14 8644 /* Try to get rid of the FPR clobbers. */
8645 s390_optimize_nonescaping_tx ();
beee1f75 8646
ff4ce128 8647 /* Re-compute register info. */
8648 s390_register_info ();
8b4a4127 8649
20074f87 8650 /* Annotate all constant pool references to let the scheduler know
8651 they implicitly use the base register. */
8652
8653 push_topmost_sequence ();
8654
8655 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8656 if (INSN_P (insn))
3072d30e 8657 {
8658 annotate_constant_pool_refs (&PATTERN (insn));
8659 df_insn_rescan (insn);
8660 }
20074f87 8661
8662 pop_topmost_sequence ();
8663
f81e845f 8664 /* Choose best register to use for temp use within prologue.
8665 See below for why TPF must use the register 1. */
8666
ffead1ca 8667 if (!has_hard_reg_initial_val (Pmode, RETURN_REGNUM)
d5bf7b64 8668 && !crtl->is_leaf
1e639cb0 8669 && !TARGET_TPF_PROFILING)
8b4a4127 8670 temp_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
4673c1a0 8671 else
8b4a4127 8672 temp_reg = gen_rtx_REG (Pmode, 1);
4673c1a0 8673
ff4ce128 8674 s390_save_gprs_to_fprs ();
8675
8b4a4127 8676 /* Save call saved gprs. */
67928721 8677 if (cfun_frame_layout.first_save_gpr != -1)
4ac7fd98 8678 {
ffead1ca 8679 insn = save_gprs (stack_pointer_rtx,
8680 cfun_frame_layout.gprs_offset +
b5fdc416 8681 UNITS_PER_LONG * (cfun_frame_layout.first_save_gpr
5214e6ae 8682 - cfun_frame_layout.first_save_gpr_slot),
ffead1ca 8683 cfun_frame_layout.first_save_gpr,
4ac7fd98 8684 cfun_frame_layout.last_save_gpr);
8685 emit_insn (insn);
8686 }
8b4a4127 8687
c2c1332a 8688 /* Dummy insn to mark literal pool slot. */
f81e845f 8689
4fed3f99 8690 if (cfun->machine->base_reg)
8691 emit_insn (gen_main_pool (cfun->machine->base_reg));
f81e845f 8692
67928721 8693 offset = cfun_frame_layout.f0_offset;
8b4a4127 8694
67928721 8695 /* Save f0 and f2. */
6a2469fe 8696 for (i = FPR0_REGNUM; i <= FPR0_REGNUM + 1; i++)
67928721 8697 {
29439367 8698 if (cfun_fpr_save_p (i))
67928721 8699 {
29439367 8700 save_fpr (stack_pointer_rtx, offset, i);
67928721 8701 offset += 8;
8702 }
031bdf83 8703 else if (!TARGET_PACKED_STACK || cfun->stdarg)
8704 offset += 8;
67928721 8705 }
4673c1a0 8706
67928721 8707 /* Save f4 and f6. */
8708 offset = cfun_frame_layout.f4_offset;
6a2469fe 8709 for (i = FPR4_REGNUM; i <= FPR4_REGNUM + 1; i++)
67928721 8710 {
29439367 8711 if (cfun_fpr_save_p (i))
8b4a4127 8712 {
29439367 8713 insn = save_fpr (stack_pointer_rtx, offset, i);
67928721 8714 offset += 8;
8715
031bdf83 8716 /* If f4 and f6 are call clobbered they are saved due to
8717 stdargs and therefore are not frame related. */
29439367 8718 if (!call_really_used_regs[i])
67928721 8719 RTX_FRAME_RELATED_P (insn) = 1;
8b4a4127 8720 }
031bdf83 8721 else if (!TARGET_PACKED_STACK || call_really_used_regs[i])
67928721 8722 offset += 8;
8723 }
8724
646a946e 8725 if (TARGET_PACKED_STACK
67928721 8726 && cfun_save_high_fprs_p
8727 && cfun_frame_layout.f8_offset + cfun_frame_layout.high_fprs * 8 > 0)
8728 {
8729 offset = (cfun_frame_layout.f8_offset
8730 + (cfun_frame_layout.high_fprs - 1) * 8);
8731
6a2469fe 8732 for (i = FPR15_REGNUM; i >= FPR8_REGNUM && offset >= 0; i--)
29439367 8733 if (cfun_fpr_save_p (i))
67928721 8734 {
29439367 8735 insn = save_fpr (stack_pointer_rtx, offset, i);
ffead1ca 8736
67928721 8737 RTX_FRAME_RELATED_P (insn) = 1;
8738 offset -= 8;
8739 }
8740 if (offset >= cfun_frame_layout.f8_offset)
29439367 8741 next_fpr = i;
67928721 8742 }
ffead1ca 8743
646a946e 8744 if (!TARGET_PACKED_STACK)
6a2469fe 8745 next_fpr = cfun_save_high_fprs_p ? FPR15_REGNUM : 0;
4673c1a0 8746
8c0dd614 8747 if (flag_stack_usage_info)
7810b579 8748 current_function_static_stack_size = cfun_frame_layout.frame_size;
8749
8b4a4127 8750 /* Decrement stack pointer. */
4673c1a0 8751
67928721 8752 if (cfun_frame_layout.frame_size > 0)
8b4a4127 8753 {
67928721 8754 rtx frame_off = GEN_INT (-cfun_frame_layout.frame_size);
b9c74b4d 8755 rtx real_frame_off;
4673c1a0 8756
cbb300e8 8757 if (s390_stack_size)
8758 {
00d233e6 8759 HOST_WIDE_INT stack_guard;
cbb300e8 8760
00d233e6 8761 if (s390_stack_guard)
8762 stack_guard = s390_stack_guard;
cbb300e8 8763 else
00d233e6 8764 {
8765 /* If no value for stack guard is provided the smallest power of 2
8766 larger than the current frame size is chosen. */
8767 stack_guard = 1;
8768 while (stack_guard < cfun_frame_layout.frame_size)
8769 stack_guard <<= 1;
8770 }
cbb300e8 8771
00d233e6 8772 if (cfun_frame_layout.frame_size >= s390_stack_size)
8773 {
8ad6fff9 8774 warning (0, "frame size of function %qs is %wd"
00d233e6 8775 " bytes exceeding user provided stack limit of "
8ad6fff9 8776 "%d bytes. "
00d233e6 8777 "An unconditional trap is added.",
8778 current_function_name(), cfun_frame_layout.frame_size,
8779 s390_stack_size);
8780 emit_insn (gen_trap ());
8781 }
8782 else
8783 {
b437383e 8784 /* stack_guard has to be smaller than s390_stack_size.
8785 Otherwise we would emit an AND with zero which would
8786 not match the test under mask pattern. */
8787 if (stack_guard >= s390_stack_size)
8788 {
7fe62d25 8789 warning (0, "frame size of function %qs is %wd"
b437383e 8790 " bytes which is more than half the stack size. "
8791 "The dynamic check would not be reliable. "
8792 "No check emitted for this function.",
8793 current_function_name(),
8794 cfun_frame_layout.frame_size);
8795 }
00d233e6 8796 else
b437383e 8797 {
8798 HOST_WIDE_INT stack_check_mask = ((s390_stack_size - 1)
8799 & ~(stack_guard - 1));
8800
8801 rtx t = gen_rtx_AND (Pmode, stack_pointer_rtx,
8802 GEN_INT (stack_check_mask));
8803 if (TARGET_64BIT)
8804 emit_insn (gen_ctrapdi4 (gen_rtx_EQ (VOIDmode,
8805 t, const0_rtx),
8806 t, const0_rtx, const0_rtx));
8807 else
8808 emit_insn (gen_ctrapsi4 (gen_rtx_EQ (VOIDmode,
8809 t, const0_rtx),
8810 t, const0_rtx, const0_rtx));
8811 }
00d233e6 8812 }
cbb300e8 8813 }
8814
ffead1ca 8815 if (s390_warn_framesize > 0
cbb300e8 8816 && cfun_frame_layout.frame_size >= s390_warn_framesize)
7fe62d25 8817 warning (0, "frame size of %qs is %wd bytes",
cbb300e8 8818 current_function_name (), cfun_frame_layout.frame_size);
8819
8820 if (s390_warn_dynamicstack_p && cfun->calls_alloca)
c3ceba8e 8821 warning (0, "%qs uses dynamic stack allocation", current_function_name ());
cbb300e8 8822
8b4a4127 8823 /* Save incoming stack pointer into temp reg. */
e5c64bfc 8824 if (TARGET_BACKCHAIN || next_fpr)
67928721 8825 insn = emit_insn (gen_move_insn (temp_reg, stack_pointer_rtx));
f81e845f 8826
1fc184ee 8827 /* Subtract frame size from stack pointer. */
8b4a4127 8828
51aa1e9c 8829 if (DISP_IN_RANGE (INTVAL (frame_off)))
8830 {
f81e845f 8831 insn = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
ffead1ca 8832 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
b40da9a7 8833 frame_off));
51aa1e9c 8834 insn = emit_insn (insn);
8835 }
8836 else
8837 {
cb888f33 8838 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
51aa1e9c 8839 frame_off = force_const_mem (Pmode, frame_off);
8840
8841 insn = emit_insn (gen_add2_insn (stack_pointer_rtx, frame_off));
20074f87 8842 annotate_constant_pool_refs (&PATTERN (insn));
51aa1e9c 8843 }
8b4a4127 8844
8b4a4127 8845 RTX_FRAME_RELATED_P (insn) = 1;
b9c74b4d 8846 real_frame_off = GEN_INT (-cfun_frame_layout.frame_size);
8847 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8848 gen_rtx_SET (VOIDmode, stack_pointer_rtx,
8849 gen_rtx_PLUS (Pmode, stack_pointer_rtx,
8850 real_frame_off)));
8b4a4127 8851
8852 /* Set backchain. */
f81e845f 8853
e5c64bfc 8854 if (TARGET_BACKCHAIN)
4673c1a0 8855 {
67928721 8856 if (cfun_frame_layout.backchain_offset)
ffead1ca 8857 addr = gen_rtx_MEM (Pmode,
29c05e22 8858 plus_constant (Pmode, stack_pointer_rtx,
67928721 8859 cfun_frame_layout.backchain_offset));
8860 else
ffead1ca 8861 addr = gen_rtx_MEM (Pmode, stack_pointer_rtx);
ce1d5a67 8862 set_mem_alias_set (addr, get_frame_alias_set ());
8b4a4127 8863 insn = emit_insn (gen_move_insn (addr, temp_reg));
4673c1a0 8864 }
90524d70 8865
cbeb677e 8866 /* If we support non-call exceptions (e.g. for Java),
90524d70 8867 we need to make sure the backchain pointer is set up
8868 before any possibly trapping memory access. */
cbeb677e 8869 if (TARGET_BACKCHAIN && cfun->can_throw_non_call_exceptions)
90524d70 8870 {
8871 addr = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode));
18b42941 8872 emit_clobber (addr);
90524d70 8873 }
8b4a4127 8874 }
4673c1a0 8875
8b4a4127 8876 /* Save fprs 8 - 15 (64 bit ABI). */
f81e845f 8877
67928721 8878 if (cfun_save_high_fprs_p && next_fpr)
8b4a4127 8879 {
062c49fd 8880 /* If the stack might be accessed through a different register
8881 we have to make sure that the stack pointer decrement is not
8882 moved below the use of the stack slots. */
8883 s390_emit_stack_tie ();
8884
ffead1ca 8885 insn = emit_insn (gen_add2_insn (temp_reg,
67928721 8886 GEN_INT (cfun_frame_layout.f8_offset)));
8887
8888 offset = 0;
4673c1a0 8889
6a2469fe 8890 for (i = FPR8_REGNUM; i <= next_fpr; i++)
29439367 8891 if (cfun_fpr_save_p (i))
8b4a4127 8892 {
29c05e22 8893 rtx addr = plus_constant (Pmode, stack_pointer_rtx,
67928721 8894 cfun_frame_layout.frame_size
8895 + cfun_frame_layout.f8_offset
8896 + offset);
ffead1ca 8897
67928721 8898 insn = save_fpr (temp_reg, offset, i);
8899 offset += 8;
8b4a4127 8900 RTX_FRAME_RELATED_P (insn) = 1;
b9c74b4d 8901 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
8902 gen_rtx_SET (VOIDmode,
8903 gen_rtx_MEM (DFmode, addr),
8904 gen_rtx_REG (DFmode, i)));
8b4a4127 8905 }
8906 }
f81e845f 8907
8b4a4127 8908 /* Set frame pointer, if needed. */
f81e845f 8909
5a5e802f 8910 if (frame_pointer_needed)
8b4a4127 8911 {
8912 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
8913 RTX_FRAME_RELATED_P (insn) = 1;
8914 }
4673c1a0 8915
8b4a4127 8916 /* Set up got pointer, if needed. */
f81e845f 8917
3072d30e 8918 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
20074f87 8919 {
8920 rtx insns = s390_load_got ();
8921
8922 for (insn = insns; insn; insn = NEXT_INSN (insn))
3072d30e 8923 annotate_constant_pool_refs (&PATTERN (insn));
20074f87 8924
8925 emit_insn (insns);
8926 }
f81e845f 8927
de253666 8928 if (TARGET_TPF_PROFILING)
f81e845f 8929 {
8930 /* Generate a BAS instruction to serve as a function
8931 entry intercept to facilitate the use of tracing
346fecd5 8932 algorithms located at the branch target. */
8933 emit_insn (gen_prologue_tpf ());
f81e845f 8934
8935 /* Emit a blockage here so that all code
8936 lies between the profiling mechanisms. */
8937 emit_insn (gen_blockage ());
8938 }
8b4a4127 8939}
4673c1a0 8940
d2833c15 8941/* Expand the epilogue into a bunch of separate insns. */
4673c1a0 8942
8b4a4127 8943void
7346ca58 8944s390_emit_epilogue (bool sibcall)
8b4a4127 8945{
a3cd0f6a 8946 rtx frame_pointer, return_reg, cfa_restores = NULL_RTX;
abd8f04d 8947 int area_bottom, area_top, offset = 0;
67928721 8948 int next_offset;
8b4a4127 8949 rtvec p;
78c2b526 8950 int i;
4673c1a0 8951
de253666 8952 if (TARGET_TPF_PROFILING)
f81e845f 8953 {
8954
8955 /* Generate a BAS instruction to serve as a function
8956 entry intercept to facilitate the use of tracing
346fecd5 8957 algorithms located at the branch target. */
f81e845f 8958
f81e845f 8959 /* Emit a blockage here so that all code
8960 lies between the profiling mechanisms. */
8961 emit_insn (gen_blockage ());
8962
346fecd5 8963 emit_insn (gen_epilogue_tpf ());
f81e845f 8964 }
8965
8b4a4127 8966 /* Check whether to use frame or stack pointer for restore. */
4673c1a0 8967
ffead1ca 8968 frame_pointer = (frame_pointer_needed
67928721 8969 ? hard_frame_pointer_rtx : stack_pointer_rtx);
4673c1a0 8970
67928721 8971 s390_frame_area (&area_bottom, &area_top);
4673c1a0 8972
f81e845f 8973 /* Check whether we can access the register save area.
8b4a4127 8974 If not, increment the frame pointer as required. */
4673c1a0 8975
8b4a4127 8976 if (area_top <= area_bottom)
8977 {
8978 /* Nothing to restore. */
8979 }
67928721 8980 else if (DISP_IN_RANGE (cfun_frame_layout.frame_size + area_bottom)
8981 && DISP_IN_RANGE (cfun_frame_layout.frame_size + area_top - 1))
8b4a4127 8982 {
8983 /* Area is in range. */
67928721 8984 offset = cfun_frame_layout.frame_size;
8b4a4127 8985 }
8986 else
8987 {
a3cd0f6a 8988 rtx insn, frame_off, cfa;
4673c1a0 8989
f81e845f 8990 offset = area_bottom < 0 ? -area_bottom : 0;
67928721 8991 frame_off = GEN_INT (cfun_frame_layout.frame_size - offset);
4673c1a0 8992
a3cd0f6a 8993 cfa = gen_rtx_SET (VOIDmode, frame_pointer,
8994 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
51aa1e9c 8995 if (DISP_IN_RANGE (INTVAL (frame_off)))
8996 {
f81e845f 8997 insn = gen_rtx_SET (VOIDmode, frame_pointer,
51aa1e9c 8998 gen_rtx_PLUS (Pmode, frame_pointer, frame_off));
8999 insn = emit_insn (insn);
9000 }
9001 else
9002 {
cb888f33 9003 if (!CONST_OK_FOR_K (INTVAL (frame_off)))
51aa1e9c 9004 frame_off = force_const_mem (Pmode, frame_off);
4673c1a0 9005
51aa1e9c 9006 insn = emit_insn (gen_add2_insn (frame_pointer, frame_off));
20074f87 9007 annotate_constant_pool_refs (&PATTERN (insn));
51aa1e9c 9008 }
a3cd0f6a 9009 add_reg_note (insn, REG_CFA_ADJUST_CFA, cfa);
9010 RTX_FRAME_RELATED_P (insn) = 1;
8b4a4127 9011 }
4673c1a0 9012
8b4a4127 9013 /* Restore call saved fprs. */
9014
9015 if (TARGET_64BIT)
4673c1a0 9016 {
67928721 9017 if (cfun_save_high_fprs_p)
9018 {
9019 next_offset = cfun_frame_layout.f8_offset;
6a2469fe 9020 for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++)
67928721 9021 {
29439367 9022 if (cfun_fpr_save_p (i))
67928721 9023 {
9024 restore_fpr (frame_pointer,
9025 offset + next_offset, i);
a3cd0f6a 9026 cfa_restores
9027 = alloc_reg_note (REG_CFA_RESTORE,
9028 gen_rtx_REG (DFmode, i), cfa_restores);
67928721 9029 next_offset += 8;
9030 }
9031 }
9032 }
ffead1ca 9033
4673c1a0 9034 }
9035 else
9036 {
67928721 9037 next_offset = cfun_frame_layout.f4_offset;
29439367 9038 /* f4, f6 */
6a2469fe 9039 for (i = FPR4_REGNUM; i <= FPR4_REGNUM + 1; i++)
67928721 9040 {
29439367 9041 if (cfun_fpr_save_p (i))
67928721 9042 {
9043 restore_fpr (frame_pointer,
9044 offset + next_offset, i);
a3cd0f6a 9045 cfa_restores
9046 = alloc_reg_note (REG_CFA_RESTORE,
9047 gen_rtx_REG (DFmode, i), cfa_restores);
67928721 9048 next_offset += 8;
9049 }
646a946e 9050 else if (!TARGET_PACKED_STACK)
67928721 9051 next_offset += 8;
9052 }
ffead1ca 9053
8b4a4127 9054 }
4673c1a0 9055
8b4a4127 9056 /* Return register. */
9057
f81e845f 9058 return_reg = gen_rtx_REG (Pmode, RETURN_REGNUM);
8b4a4127 9059
9060 /* Restore call saved gprs. */
9061
67928721 9062 if (cfun_frame_layout.first_restore_gpr != -1)
8b4a4127 9063 {
9a2a66ae 9064 rtx insn, addr;
43935856 9065 int i;
9066
f81e845f 9067 /* Check for global register and save them
43935856 9068 to stack location from where they get restored. */
9069
67928721 9070 for (i = cfun_frame_layout.first_restore_gpr;
9071 i <= cfun_frame_layout.last_restore_gpr;
43935856 9072 i++)
9073 {
a3cd0f6a 9074 if (global_not_special_regno_p (i))
43935856 9075 {
29c05e22 9076 addr = plus_constant (Pmode, frame_pointer,
ffead1ca 9077 offset + cfun_frame_layout.gprs_offset
5214e6ae 9078 + (i - cfun_frame_layout.first_save_gpr_slot)
b5fdc416 9079 * UNITS_PER_LONG);
43935856 9080 addr = gen_rtx_MEM (Pmode, addr);
ce1d5a67 9081 set_mem_alias_set (addr, get_frame_alias_set ());
43935856 9082 emit_move_insn (addr, gen_rtx_REG (Pmode, i));
f81e845f 9083 }
a3cd0f6a 9084 else
9085 cfa_restores
9086 = alloc_reg_note (REG_CFA_RESTORE,
9087 gen_rtx_REG (Pmode, i), cfa_restores);
43935856 9088 }
8b4a4127 9089
7346ca58 9090 if (! sibcall)
4673c1a0 9091 {
7346ca58 9092 /* Fetch return address from stack before load multiple,
9093 this will do good for scheduling. */
f588eb9f 9094
67928721 9095 if (cfun_frame_layout.save_return_addr_p
9096 || (cfun_frame_layout.first_restore_gpr < BASE_REGNUM
9097 && cfun_frame_layout.last_restore_gpr > RETURN_REGNUM))
7346ca58 9098 {
9099 int return_regnum = find_unused_clobbered_reg();
9100 if (!return_regnum)
9101 return_regnum = 4;
9102 return_reg = gen_rtx_REG (Pmode, return_regnum);
f588eb9f 9103
29c05e22 9104 addr = plus_constant (Pmode, frame_pointer,
67928721 9105 offset + cfun_frame_layout.gprs_offset
ffead1ca 9106 + (RETURN_REGNUM
5214e6ae 9107 - cfun_frame_layout.first_save_gpr_slot)
b5fdc416 9108 * UNITS_PER_LONG);
7346ca58 9109 addr = gen_rtx_MEM (Pmode, addr);
ce1d5a67 9110 set_mem_alias_set (addr, get_frame_alias_set ());
7346ca58 9111 emit_move_insn (return_reg, addr);
9112 }
4673c1a0 9113 }
8b4a4127 9114
67928721 9115 insn = restore_gprs (frame_pointer,
9116 offset + cfun_frame_layout.gprs_offset
ffead1ca 9117 + (cfun_frame_layout.first_restore_gpr
5214e6ae 9118 - cfun_frame_layout.first_save_gpr_slot)
b5fdc416 9119 * UNITS_PER_LONG,
67928721 9120 cfun_frame_layout.first_restore_gpr,
9121 cfun_frame_layout.last_restore_gpr);
a3cd0f6a 9122 insn = emit_insn (insn);
9123 REG_NOTES (insn) = cfa_restores;
9124 add_reg_note (insn, REG_CFA_DEF_CFA,
29c05e22 9125 plus_constant (Pmode, stack_pointer_rtx,
9126 STACK_POINTER_OFFSET));
a3cd0f6a 9127 RTX_FRAME_RELATED_P (insn) = 1;
8b4a4127 9128 }
4673c1a0 9129
ff4ce128 9130 s390_restore_gprs_from_fprs ();
9131
7346ca58 9132 if (! sibcall)
9133 {
f81e845f 9134
7346ca58 9135 /* Return to caller. */
f588eb9f 9136
7346ca58 9137 p = rtvec_alloc (2);
f588eb9f 9138
1a860023 9139 RTVEC_ELT (p, 0) = ret_rtx;
7346ca58 9140 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode, return_reg);
9141 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
9142 }
4673c1a0 9143}
9144
4673c1a0 9145
f81e845f 9146/* Return the size in bytes of a function argument of
56769981 9147 type TYPE and/or mode MODE. At least one of TYPE or
9148 MODE must be specified. */
4673c1a0 9149
9150static int
fb80456a 9151s390_function_arg_size (enum machine_mode mode, const_tree type)
4673c1a0 9152{
9153 if (type)
9154 return int_size_in_bytes (type);
9155
0c034860 9156 /* No type info available for some library calls ... */
4673c1a0 9157 if (mode != BLKmode)
9158 return GET_MODE_SIZE (mode);
9159
9160 /* If we have neither type nor mode, abort */
32eda510 9161 gcc_unreachable ();
4673c1a0 9162}
9163
59652f3f 9164/* Return true if a function argument of type TYPE and mode MODE
9165 is to be passed in a floating-point register, if available. */
9166
9167static bool
12bc26aa 9168s390_function_arg_float (enum machine_mode mode, const_tree type)
59652f3f 9169{
201e502c 9170 int size = s390_function_arg_size (mode, type);
9171 if (size > 8)
9172 return false;
9173
59652f3f 9174 /* Soft-float changes the ABI: no floating-point registers are used. */
9175 if (TARGET_SOFT_FLOAT)
9176 return false;
9177
9178 /* No type info available for some library calls ... */
9179 if (!type)
36868490 9180 return mode == SFmode || mode == DFmode || mode == SDmode || mode == DDmode;
59652f3f 9181
9182 /* The ABI says that record types with a single member are treated
9183 just like that member would be. */
9184 while (TREE_CODE (type) == RECORD_TYPE)
9185 {
9186 tree field, single = NULL_TREE;
9187
1767a056 9188 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
59652f3f 9189 {
9190 if (TREE_CODE (field) != FIELD_DECL)
9191 continue;
9192
9193 if (single == NULL_TREE)
9194 single = TREE_TYPE (field);
9195 else
9196 return false;
9197 }
9198
9199 if (single == NULL_TREE)
9200 return false;
9201 else
9202 type = single;
9203 }
9204
9205 return TREE_CODE (type) == REAL_TYPE;
9206}
9207
201e502c 9208/* Return true if a function argument of type TYPE and mode MODE
9209 is to be passed in an integer register, or a pair of integer
9210 registers, if available. */
9211
9212static bool
12bc26aa 9213s390_function_arg_integer (enum machine_mode mode, const_tree type)
201e502c 9214{
9215 int size = s390_function_arg_size (mode, type);
9216 if (size > 8)
9217 return false;
9218
9219 /* No type info available for some library calls ... */
9220 if (!type)
9221 return GET_MODE_CLASS (mode) == MODE_INT
36868490 9222 || (TARGET_SOFT_FLOAT && SCALAR_FLOAT_MODE_P (mode));
201e502c 9223
9224 /* We accept small integral (and similar) types. */
9225 if (INTEGRAL_TYPE_P (type)
f588eb9f 9226 || POINTER_TYPE_P (type)
bd3e12e5 9227 || TREE_CODE (type) == NULLPTR_TYPE
201e502c 9228 || TREE_CODE (type) == OFFSET_TYPE
9229 || (TARGET_SOFT_FLOAT && TREE_CODE (type) == REAL_TYPE))
9230 return true;
9231
9232 /* We also accept structs of size 1, 2, 4, 8 that are not
f588eb9f 9233 passed in floating-point registers. */
201e502c 9234 if (AGGREGATE_TYPE_P (type)
9235 && exact_log2 (size) >= 0
9236 && !s390_function_arg_float (mode, type))
9237 return true;
9238
9239 return false;
9240}
9241
56769981 9242/* Return 1 if a function argument of type TYPE and mode MODE
9243 is to be passed by reference. The ABI specifies that only
9244 structures of size 1, 2, 4, or 8 bytes are passed by value,
9245 all other structures (and complex numbers) are passed by
9246 reference. */
9247
b981d932 9248static bool
39cba157 9249s390_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
fb80456a 9250 enum machine_mode mode, const_tree type,
b981d932 9251 bool named ATTRIBUTE_UNUSED)
4673c1a0 9252{
9253 int size = s390_function_arg_size (mode, type);
201e502c 9254 if (size > 8)
9255 return true;
4673c1a0 9256
9257 if (type)
9258 {
201e502c 9259 if (AGGREGATE_TYPE_P (type) && exact_log2 (size) < 0)
4673c1a0 9260 return 1;
9261
201e502c 9262 if (TREE_CODE (type) == COMPLEX_TYPE
9263 || TREE_CODE (type) == VECTOR_TYPE)
4673c1a0 9264 return 1;
9265 }
f81e845f 9266
4673c1a0 9267 return 0;
4673c1a0 9268}
9269
9270/* Update the data in CUM to advance over an argument of mode MODE and
9271 data type TYPE. (TYPE is null for libcalls where that information
56769981 9272 may not be available.). The boolean NAMED specifies whether the
9273 argument is a named argument (as opposed to an unnamed argument
9274 matching an ellipsis). */
4673c1a0 9275
12bc26aa 9276static void
39cba157 9277s390_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
12bc26aa 9278 const_tree type, bool named ATTRIBUTE_UNUSED)
4673c1a0 9279{
39cba157 9280 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
9281
b981d932 9282 if (s390_function_arg_float (mode, type))
4673c1a0 9283 {
59652f3f 9284 cum->fprs += 1;
4673c1a0 9285 }
201e502c 9286 else if (s390_function_arg_integer (mode, type))
4673c1a0 9287 {
9288 int size = s390_function_arg_size (mode, type);
b5fdc416 9289 cum->gprs += ((size + UNITS_PER_LONG - 1) / UNITS_PER_LONG);
4673c1a0 9290 }
201e502c 9291 else
32eda510 9292 gcc_unreachable ();
4673c1a0 9293}
9294
56769981 9295/* Define where to put the arguments to a function.
9296 Value is zero to push the argument on the stack,
9297 or a hard register in which to store the argument.
9298
9299 MODE is the argument's machine mode.
9300 TYPE is the data type of the argument (as a tree).
9301 This is null for libcalls where that information may
9302 not be available.
9303 CUM is a variable of type CUMULATIVE_ARGS which gives info about
9304 the preceding args and about the function being called.
9305 NAMED is nonzero if this argument is a named parameter
f81e845f 9306 (otherwise it is an extra parameter matching an ellipsis).
56769981 9307
9308 On S/390, we use general purpose registers 2 through 6 to
9309 pass integer, pointer, and certain structure arguments, and
9310 floating point registers 0 and 2 (0, 2, 4, and 6 on 64-bit)
9311 to pass floating point arguments. All remaining arguments
9312 are pushed to the stack. */
4673c1a0 9313
12bc26aa 9314static rtx
39cba157 9315s390_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
12bc26aa 9316 const_tree type, bool named ATTRIBUTE_UNUSED)
4673c1a0 9317{
39cba157 9318 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
9319
59652f3f 9320 if (s390_function_arg_float (mode, type))
4673c1a0 9321 {
6902d973 9322 if (cum->fprs + 1 > FP_ARG_NUM_REG)
4673c1a0 9323 return 0;
9324 else
1a83b3ff 9325 return gen_rtx_REG (mode, cum->fprs + 16);
4673c1a0 9326 }
201e502c 9327 else if (s390_function_arg_integer (mode, type))
4673c1a0 9328 {
9329 int size = s390_function_arg_size (mode, type);
b5fdc416 9330 int n_gprs = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
4673c1a0 9331
6902d973 9332 if (cum->gprs + n_gprs > GP_ARG_NUM_REG)
4673c1a0 9333 return 0;
b5fdc416 9334 else if (n_gprs == 1 || UNITS_PER_WORD == UNITS_PER_LONG)
1a83b3ff 9335 return gen_rtx_REG (mode, cum->gprs + 2);
b5fdc416 9336 else if (n_gprs == 2)
9337 {
9338 rtvec p = rtvec_alloc (2);
9339
9340 RTVEC_ELT (p, 0)
9341 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 2),
9342 const0_rtx);
9343 RTVEC_ELT (p, 1)
9344 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, cum->gprs + 3),
9345 GEN_INT (4));
9346
9347 return gen_rtx_PARALLEL (mode, p);
9348 }
4673c1a0 9349 }
201e502c 9350
9351 /* After the real arguments, expand_call calls us once again
9352 with a void_type_node type. Whatever we return here is
9353 passed as operand 2 to the call expanders.
9354
9355 We don't need this feature ... */
9356 else if (type == void_type_node)
9357 return const0_rtx;
9358
32eda510 9359 gcc_unreachable ();
201e502c 9360}
9361
9362/* Return true if return values of type TYPE should be returned
9363 in a memory buffer whose address is passed by the caller as
9364 hidden first argument. */
9365
9366static bool
fb80456a 9367s390_return_in_memory (const_tree type, const_tree fundecl ATTRIBUTE_UNUSED)
201e502c 9368{
9369 /* We accept small integral (and similar) types. */
9370 if (INTEGRAL_TYPE_P (type)
f588eb9f 9371 || POINTER_TYPE_P (type)
201e502c 9372 || TREE_CODE (type) == OFFSET_TYPE
9373 || TREE_CODE (type) == REAL_TYPE)
9374 return int_size_in_bytes (type) > 8;
9375
9376 /* Aggregates and similar constructs are always returned
9377 in memory. */
9378 if (AGGREGATE_TYPE_P (type)
9379 || TREE_CODE (type) == COMPLEX_TYPE
9380 || TREE_CODE (type) == VECTOR_TYPE)
9381 return true;
9382
9383 /* ??? We get called on all sorts of random stuff from
9384 aggregate_value_p. We can't abort, but it's not clear
9385 what's safe to return. Pretend it's a struct I guess. */
9386 return true;
9387}
9388
3b2411a8 9389/* Function arguments and return values are promoted to word size. */
9390
9391static enum machine_mode
9392s390_promote_function_mode (const_tree type, enum machine_mode mode,
9393 int *punsignedp,
9394 const_tree fntype ATTRIBUTE_UNUSED,
9395 int for_return ATTRIBUTE_UNUSED)
9396{
9397 if (INTEGRAL_MODE_P (mode)
b5fdc416 9398 && GET_MODE_SIZE (mode) < UNITS_PER_LONG)
3b2411a8 9399 {
adaf4ef0 9400 if (type != NULL_TREE && POINTER_TYPE_P (type))
3b2411a8 9401 *punsignedp = POINTERS_EXTEND_UNSIGNED;
9402 return Pmode;
9403 }
9404
9405 return mode;
9406}
9407
dc3b3062 9408/* Define where to return a (scalar) value of type RET_TYPE.
9409 If RET_TYPE is null, define where to return a (scalar)
201e502c 9410 value of mode MODE from a libcall. */
9411
dc3b3062 9412static rtx
9413s390_function_and_libcall_value (enum machine_mode mode,
9414 const_tree ret_type,
9415 const_tree fntype_or_decl,
9416 bool outgoing ATTRIBUTE_UNUSED)
201e502c 9417{
dc3b3062 9418 /* For normal functions perform the promotion as
9419 promote_function_mode would do. */
9420 if (ret_type)
201e502c 9421 {
dc3b3062 9422 int unsignedp = TYPE_UNSIGNED (ret_type);
9423 mode = promote_function_mode (ret_type, mode, &unsignedp,
9424 fntype_or_decl, 1);
201e502c 9425 }
9426
36868490 9427 gcc_assert (GET_MODE_CLASS (mode) == MODE_INT || SCALAR_FLOAT_MODE_P (mode));
32eda510 9428 gcc_assert (GET_MODE_SIZE (mode) <= 8);
201e502c 9429
36868490 9430 if (TARGET_HARD_FLOAT && SCALAR_FLOAT_MODE_P (mode))
201e502c 9431 return gen_rtx_REG (mode, 16);
b5fdc416 9432 else if (GET_MODE_SIZE (mode) <= UNITS_PER_LONG
9433 || UNITS_PER_LONG == UNITS_PER_WORD)
201e502c 9434 return gen_rtx_REG (mode, 2);
b5fdc416 9435 else if (GET_MODE_SIZE (mode) == 2 * UNITS_PER_LONG)
9436 {
dc3b3062 9437 /* This case is triggered when returning a 64 bit value with
9438 -m31 -mzarch. Although the value would fit into a single
9439 register it has to be forced into a 32 bit register pair in
9440 order to match the ABI. */
b5fdc416 9441 rtvec p = rtvec_alloc (2);
9442
9443 RTVEC_ELT (p, 0)
9444 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 2), const0_rtx);
9445 RTVEC_ELT (p, 1)
9446 = gen_rtx_EXPR_LIST (SImode, gen_rtx_REG (SImode, 3), GEN_INT (4));
9447
9448 return gen_rtx_PARALLEL (mode, p);
9449 }
9450
9451 gcc_unreachable ();
4673c1a0 9452}
9453
dc3b3062 9454/* Define where to return a scalar return value of type RET_TYPE. */
9455
9456static rtx
9457s390_function_value (const_tree ret_type, const_tree fn_decl_or_type,
9458 bool outgoing)
9459{
9460 return s390_function_and_libcall_value (TYPE_MODE (ret_type), ret_type,
9461 fn_decl_or_type, outgoing);
9462}
9463
9464/* Define where to return a scalar libcall return value of mode
9465 MODE. */
9466
9467static rtx
9468s390_libcall_value (enum machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
9469{
9470 return s390_function_and_libcall_value (mode, NULL_TREE,
9471 NULL_TREE, true);
9472}
9473
4673c1a0 9474
56769981 9475/* Create and return the va_list datatype.
9476
9477 On S/390, va_list is an array type equivalent to
9478
9479 typedef struct __va_list_tag
9480 {
9481 long __gpr;
9482 long __fpr;
9483 void *__overflow_arg_area;
9484 void *__reg_save_area;
56769981 9485 } va_list[1];
9486
9487 where __gpr and __fpr hold the number of general purpose
9488 or floating point arguments used up to now, respectively,
f81e845f 9489 __overflow_arg_area points to the stack location of the
56769981 9490 next argument passed on the stack, and __reg_save_area
9491 always points to the start of the register area in the
9492 call frame of the current function. The function prologue
9493 saves all registers used for argument passing into this
9494 area if the function uses variable arguments. */
4673c1a0 9495
2e15d750 9496static tree
9497s390_build_builtin_va_list (void)
4673c1a0 9498{
9499 tree f_gpr, f_fpr, f_ovf, f_sav, record, type_decl;
9500
5ebb663d 9501 record = lang_hooks.types.make_type (RECORD_TYPE);
4673c1a0 9502
9503 type_decl =
54e46243 9504 build_decl (BUILTINS_LOCATION,
9505 TYPE_DECL, get_identifier ("__va_list_tag"), record);
4673c1a0 9506
54e46243 9507 f_gpr = build_decl (BUILTINS_LOCATION,
9508 FIELD_DECL, get_identifier ("__gpr"),
4673c1a0 9509 long_integer_type_node);
54e46243 9510 f_fpr = build_decl (BUILTINS_LOCATION,
9511 FIELD_DECL, get_identifier ("__fpr"),
4673c1a0 9512 long_integer_type_node);
54e46243 9513 f_ovf = build_decl (BUILTINS_LOCATION,
9514 FIELD_DECL, get_identifier ("__overflow_arg_area"),
4673c1a0 9515 ptr_type_node);
54e46243 9516 f_sav = build_decl (BUILTINS_LOCATION,
9517 FIELD_DECL, get_identifier ("__reg_save_area"),
4673c1a0 9518 ptr_type_node);
9519
6902d973 9520 va_list_gpr_counter_field = f_gpr;
9521 va_list_fpr_counter_field = f_fpr;
9522
4673c1a0 9523 DECL_FIELD_CONTEXT (f_gpr) = record;
9524 DECL_FIELD_CONTEXT (f_fpr) = record;
9525 DECL_FIELD_CONTEXT (f_ovf) = record;
9526 DECL_FIELD_CONTEXT (f_sav) = record;
9527
bc907808 9528 TYPE_STUB_DECL (record) = type_decl;
4673c1a0 9529 TYPE_NAME (record) = type_decl;
9530 TYPE_FIELDS (record) = f_gpr;
1767a056 9531 DECL_CHAIN (f_gpr) = f_fpr;
9532 DECL_CHAIN (f_fpr) = f_ovf;
9533 DECL_CHAIN (f_ovf) = f_sav;
4673c1a0 9534
9535 layout_type (record);
9536
9537 /* The correct type is an array type of one element. */
9538 return build_array_type (record, build_index_type (size_zero_node));
9539}
9540
56769981 9541/* Implement va_start by filling the va_list structure VALIST.
7ccc713a 9542 STDARG_P is always true, and ignored.
9543 NEXTARG points to the first anonymous stack argument.
56769981 9544
8ef587dc 9545 The following global variables are used to initialize
56769981 9546 the va_list structure:
9547
abe32cce 9548 crtl->args.info:
56769981 9549 holds number of gprs and fprs used for named arguments.
abe32cce 9550 crtl->args.arg_offset_rtx:
56769981 9551 holds the offset of the first anonymous stack argument
9552 (relative to the virtual arg pointer). */
4673c1a0 9553
8a58ed0a 9554static void
b40da9a7 9555s390_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED)
4673c1a0 9556{
9557 HOST_WIDE_INT n_gpr, n_fpr;
9558 int off;
9559 tree f_gpr, f_fpr, f_ovf, f_sav;
9560 tree gpr, fpr, ovf, sav, t;
9561
9562 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
1767a056 9563 f_fpr = DECL_CHAIN (f_gpr);
9564 f_ovf = DECL_CHAIN (f_fpr);
9565 f_sav = DECL_CHAIN (f_ovf);
4673c1a0 9566
170efcd4 9567 valist = build_simple_mem_ref (valist);
ed03eadb 9568 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9569 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
9570 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9571 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
4673c1a0 9572
9573 /* Count number of gp and fp argument registers used. */
9574
abe32cce 9575 n_gpr = crtl->args.info.gprs;
9576 n_fpr = crtl->args.info.fprs;
4673c1a0 9577
6902d973 9578 if (cfun->va_list_gpr_size)
9579 {
75a70cf9 9580 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
9581 build_int_cst (NULL_TREE, n_gpr));
6902d973 9582 TREE_SIDE_EFFECTS (t) = 1;
9583 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9584 }
4673c1a0 9585
6902d973 9586 if (cfun->va_list_fpr_size)
9587 {
75a70cf9 9588 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
ed03eadb 9589 build_int_cst (NULL_TREE, n_fpr));
6902d973 9590 TREE_SIDE_EFFECTS (t) = 1;
9591 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9592 }
4673c1a0 9593
9594 /* Find the overflow area. */
6902d973 9595 if (n_gpr + cfun->va_list_gpr_size > GP_ARG_NUM_REG
9596 || n_fpr + cfun->va_list_fpr_size > FP_ARG_NUM_REG)
9597 {
9598 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
4673c1a0 9599
abe32cce 9600 off = INTVAL (crtl->args.arg_offset_rtx);
6902d973 9601 off = off < 0 ? 0 : off;
9602 if (TARGET_DEBUG_ARG)
9603 fprintf (stderr, "va_start: n_gpr = %d, n_fpr = %d off %d\n",
9604 (int)n_gpr, (int)n_fpr, off);
4673c1a0 9605
2cc66f2a 9606 t = fold_build_pointer_plus_hwi (t, off);
4673c1a0 9607
75a70cf9 9608 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
6902d973 9609 TREE_SIDE_EFFECTS (t) = 1;
9610 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9611 }
4673c1a0 9612
9613 /* Find the register save area. */
6902d973 9614 if ((cfun->va_list_gpr_size && n_gpr < GP_ARG_NUM_REG)
9615 || (cfun->va_list_fpr_size && n_fpr < FP_ARG_NUM_REG))
9616 {
9617 t = make_tree (TREE_TYPE (sav), return_address_pointer_rtx);
2cc66f2a 9618 t = fold_build_pointer_plus_hwi (t, -RETURN_REGNUM * UNITS_PER_LONG);
ffead1ca 9619
75a70cf9 9620 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
6902d973 9621 TREE_SIDE_EFFECTS (t) = 1;
9622 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
9623 }
4673c1a0 9624}
9625
f81e845f 9626/* Implement va_arg by updating the va_list structure
56769981 9627 VALIST as required to retrieve an argument of type
f81e845f 9628 TYPE, and returning that argument.
9629
56769981 9630 Generates code equivalent to:
f81e845f 9631
4673c1a0 9632 if (integral value) {
9633 if (size <= 4 && args.gpr < 5 ||
f81e845f 9634 size > 4 && args.gpr < 4 )
4673c1a0 9635 ret = args.reg_save_area[args.gpr+8]
9636 else
9637 ret = *args.overflow_arg_area++;
9638 } else if (float value) {
9639 if (args.fgpr < 2)
9640 ret = args.reg_save_area[args.fpr+64]
9641 else
9642 ret = *args.overflow_arg_area++;
9643 } else if (aggregate value) {
9644 if (args.gpr < 5)
9645 ret = *args.reg_save_area[args.gpr]
9646 else
9647 ret = **args.overflow_arg_area++;
9648 } */
9649
875862bf 9650static tree
ffead1ca 9651s390_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p,
75a70cf9 9652 gimple_seq *post_p ATTRIBUTE_UNUSED)
4673c1a0 9653{
9654 tree f_gpr, f_fpr, f_ovf, f_sav;
9655 tree gpr, fpr, ovf, sav, reg, t, u;
9656 int indirect_p, size, n_reg, sav_ofs, sav_scale, max_reg;
d93e0d9f 9657 tree lab_false, lab_over, addr;
4673c1a0 9658
9659 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
1767a056 9660 f_fpr = DECL_CHAIN (f_gpr);
9661 f_ovf = DECL_CHAIN (f_fpr);
9662 f_sav = DECL_CHAIN (f_ovf);
4673c1a0 9663
bfe827ee 9664 valist = build_va_arg_indirect_ref (valist);
ed03eadb 9665 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
9666 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
ed03eadb 9667 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
4673c1a0 9668
75a70cf9 9669 /* The tree for args* cannot be shared between gpr/fpr and ovf since
9670 both appear on a lhs. */
9671 valist = unshare_expr (valist);
9672 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
9673
4673c1a0 9674 size = int_size_in_bytes (type);
9675
b981d932 9676 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
4673c1a0 9677 {
9678 if (TARGET_DEBUG_ARG)
9679 {
9680 fprintf (stderr, "va_arg: aggregate type");
9681 debug_tree (type);
9682 }
9683
9684 /* Aggregates are passed by reference. */
9685 indirect_p = 1;
9686 reg = gpr;
9687 n_reg = 1;
99e8a714 9688
646a946e 9689 /* kernel stack layout on 31 bit: It is assumed here that no padding
99e8a714 9690 will be added by s390_frame_info because for va_args always an even
9691 number of gprs has to be saved r15-r2 = 14 regs. */
b5fdc416 9692 sav_ofs = 2 * UNITS_PER_LONG;
9693 sav_scale = UNITS_PER_LONG;
9694 size = UNITS_PER_LONG;
6902d973 9695 max_reg = GP_ARG_NUM_REG - n_reg;
4673c1a0 9696 }
59652f3f 9697 else if (s390_function_arg_float (TYPE_MODE (type), type))
4673c1a0 9698 {
9699 if (TARGET_DEBUG_ARG)
9700 {
9701 fprintf (stderr, "va_arg: float type");
9702 debug_tree (type);
9703 }
9704
9705 /* FP args go in FP registers, if present. */
9706 indirect_p = 0;
9707 reg = fpr;
9708 n_reg = 1;
b5fdc416 9709 sav_ofs = 16 * UNITS_PER_LONG;
4673c1a0 9710 sav_scale = 8;
6902d973 9711 max_reg = FP_ARG_NUM_REG - n_reg;
4673c1a0 9712 }
9713 else
9714 {
9715 if (TARGET_DEBUG_ARG)
9716 {
9717 fprintf (stderr, "va_arg: other type");
9718 debug_tree (type);
9719 }
9720
9721 /* Otherwise into GP registers. */
9722 indirect_p = 0;
9723 reg = gpr;
b5fdc416 9724 n_reg = (size + UNITS_PER_LONG - 1) / UNITS_PER_LONG;
99e8a714 9725
646a946e 9726 /* kernel stack layout on 31 bit: It is assumed here that no padding
9727 will be added by s390_frame_info because for va_args always an even
9728 number of gprs has to be saved r15-r2 = 14 regs. */
b5fdc416 9729 sav_ofs = 2 * UNITS_PER_LONG;
f81e845f 9730
b5fdc416 9731 if (size < UNITS_PER_LONG)
9732 sav_ofs += UNITS_PER_LONG - size;
4673c1a0 9733
b5fdc416 9734 sav_scale = UNITS_PER_LONG;
6902d973 9735 max_reg = GP_ARG_NUM_REG - n_reg;
4673c1a0 9736 }
9737
9738 /* Pull the value out of the saved registers ... */
9739
54e46243 9740 lab_false = create_artificial_label (UNKNOWN_LOCATION);
9741 lab_over = create_artificial_label (UNKNOWN_LOCATION);
d93e0d9f 9742 addr = create_tmp_var (ptr_type_node, "addr");
4673c1a0 9743
3c2ee2c9 9744 t = fold_convert (TREE_TYPE (reg), size_int (max_reg));
d93e0d9f 9745 t = build2 (GT_EXPR, boolean_type_node, reg, t);
9746 u = build1 (GOTO_EXPR, void_type_node, lab_false);
9747 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
9748 gimplify_and_add (t, pre_p);
4673c1a0 9749
2cc66f2a 9750 t = fold_build_pointer_plus_hwi (sav, sav_ofs);
ffead1ca 9751 u = build2 (MULT_EXPR, TREE_TYPE (reg), reg,
3c2ee2c9 9752 fold_convert (TREE_TYPE (reg), size_int (sav_scale)));
2cc66f2a 9753 t = fold_build_pointer_plus (t, u);
4673c1a0 9754
75a70cf9 9755 gimplify_assign (addr, t, pre_p);
4673c1a0 9756
75a70cf9 9757 gimple_seq_add_stmt (pre_p, gimple_build_goto (lab_over));
4673c1a0 9758
75a70cf9 9759 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_false));
4673c1a0 9760
4673c1a0 9761
9762 /* ... Otherwise out of the overflow area. */
9763
875862bf 9764 t = ovf;
b5fdc416 9765 if (size < UNITS_PER_LONG)
2cc66f2a 9766 t = fold_build_pointer_plus_hwi (t, UNITS_PER_LONG - size);
875862bf 9767
9768 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
9769
75a70cf9 9770 gimplify_assign (addr, t, pre_p);
875862bf 9771
2cc66f2a 9772 t = fold_build_pointer_plus_hwi (t, size);
75a70cf9 9773 gimplify_assign (ovf, t, pre_p);
875862bf 9774
75a70cf9 9775 gimple_seq_add_stmt (pre_p, gimple_build_label (lab_over));
875862bf 9776
9777
9778 /* Increment register save count. */
9779
9780 u = build2 (PREINCREMENT_EXPR, TREE_TYPE (reg), reg,
9781 fold_convert (TREE_TYPE (reg), size_int (n_reg)));
9782 gimplify_and_add (u, pre_p);
9783
9784 if (indirect_p)
9785 {
8115f0af 9786 t = build_pointer_type_for_mode (build_pointer_type (type),
9787 ptr_mode, true);
875862bf 9788 addr = fold_convert (t, addr);
9789 addr = build_va_arg_indirect_ref (addr);
9790 }
9791 else
9792 {
8115f0af 9793 t = build_pointer_type_for_mode (type, ptr_mode, true);
875862bf 9794 addr = fold_convert (t, addr);
9795 }
9796
9797 return build_va_arg_indirect_ref (addr);
9798}
9799
5ada7a14 9800/* Emit rtl for the tbegin or tbegin_retry (RETRY != NULL_RTX)
9801 expanders.
9802 DEST - Register location where CC will be stored.
9803 TDB - Pointer to a 256 byte area where to store the transaction.
9804 diagnostic block. NULL if TDB is not needed.
9805 RETRY - Retry count value. If non-NULL a retry loop for CC2
9806 is emitted
9807 CLOBBER_FPRS_P - If true clobbers for all FPRs are emitted as part
9808 of the tbegin instruction pattern. */
9809
9810void
9811s390_expand_tbegin (rtx dest, rtx tdb, rtx retry, bool clobber_fprs_p)
9812{
9813 const int CC0 = 1 << 3;
9814 const int CC1 = 1 << 2;
9815 const int CC3 = 1 << 0;
9816 rtx abort_label = gen_label_rtx ();
9817 rtx leave_label = gen_label_rtx ();
91dfd73e 9818 rtx retry_plus_two = gen_reg_rtx (SImode);
5ada7a14 9819 rtx retry_reg = gen_reg_rtx (SImode);
9820 rtx retry_label = NULL_RTX;
9821 rtx jump;
9eb946de 9822 int very_unlikely = REG_BR_PROB_BASE / 100 - 1;
5ada7a14 9823
9824 if (retry != NULL_RTX)
9825 {
9826 emit_move_insn (retry_reg, retry);
91dfd73e 9827 emit_insn (gen_addsi3 (retry_plus_two, retry_reg, const2_rtx));
9828 emit_insn (gen_addsi3 (retry_reg, retry_reg, const1_rtx));
5ada7a14 9829 retry_label = gen_label_rtx ();
9830 emit_label (retry_label);
9831 }
9832
9833 if (clobber_fprs_p)
91dfd73e 9834 emit_insn (gen_tbegin_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK), tdb));
5ada7a14 9835 else
91dfd73e 9836 emit_insn (gen_tbegin_nofloat_1 (gen_rtx_CONST_INT (VOIDmode, TBEGIN_MASK),
9837 tdb));
5ada7a14 9838
9839 jump = s390_emit_jump (abort_label,
9840 gen_rtx_NE (VOIDmode,
9841 gen_rtx_REG (CCRAWmode, CC_REGNUM),
9842 gen_rtx_CONST_INT (VOIDmode, CC0)));
9843
9844 JUMP_LABEL (jump) = abort_label;
9845 LABEL_NUSES (abort_label) = 1;
9eb946de 9846 add_int_reg_note (jump, REG_BR_PROB, very_unlikely);
5ada7a14 9847
9848 /* Initialize CC return value. */
9849 emit_move_insn (dest, const0_rtx);
9850
9851 s390_emit_jump (leave_label, NULL_RTX);
9852 LABEL_NUSES (leave_label) = 1;
9853 emit_barrier ();
9854
9855 /* Abort handler code. */
9856
9857 emit_label (abort_label);
91dfd73e 9858 emit_move_insn (dest, gen_rtx_UNSPEC (SImode,
9859 gen_rtvec (1, gen_rtx_REG (CCRAWmode,
9860 CC_REGNUM)),
9861 UNSPEC_CC_TO_INT));
5ada7a14 9862 if (retry != NULL_RTX)
9863 {
9864 rtx count = gen_reg_rtx (SImode);
9865 jump = s390_emit_jump (leave_label,
9866 gen_rtx_EQ (VOIDmode,
9867 gen_rtx_REG (CCRAWmode, CC_REGNUM),
9868 gen_rtx_CONST_INT (VOIDmode, CC1 | CC3)));
9869 LABEL_NUSES (leave_label) = 2;
9eb946de 9870 add_int_reg_note (jump, REG_BR_PROB, very_unlikely);
5ada7a14 9871
9872 /* CC2 - transient failure. Perform retry with ppa. */
91dfd73e 9873 emit_move_insn (count, retry_plus_two);
5ada7a14 9874 emit_insn (gen_subsi3 (count, count, retry_reg));
9875 emit_insn (gen_tx_assist (count));
9876 jump = emit_jump_insn (gen_doloop_si64 (retry_label,
9877 retry_reg,
9878 retry_reg));
9879 JUMP_LABEL (jump) = retry_label;
9880 LABEL_NUSES (retry_label) = 1;
9881 }
9882
5ada7a14 9883 emit_label (leave_label);
9884}
9885
9886/* Builtins. */
9887
9888enum s390_builtin
9889{
9890 S390_BUILTIN_TBEGIN,
9891 S390_BUILTIN_TBEGIN_NOFLOAT,
9892 S390_BUILTIN_TBEGIN_RETRY,
9893 S390_BUILTIN_TBEGIN_RETRY_NOFLOAT,
9894 S390_BUILTIN_TBEGINC,
9895 S390_BUILTIN_TEND,
9896 S390_BUILTIN_TABORT,
9897 S390_BUILTIN_NON_TX_STORE,
9898 S390_BUILTIN_TX_NESTING_DEPTH,
9899 S390_BUILTIN_TX_ASSIST,
9900
9901 S390_BUILTIN_max
9902};
9903
9904static enum insn_code const code_for_builtin[S390_BUILTIN_max] = {
9905 CODE_FOR_tbegin,
9906 CODE_FOR_tbegin_nofloat,
9907 CODE_FOR_tbegin_retry,
9908 CODE_FOR_tbegin_retry_nofloat,
9909 CODE_FOR_tbeginc,
9910 CODE_FOR_tend,
9911 CODE_FOR_tabort,
9912 CODE_FOR_ntstg,
9913 CODE_FOR_etnd,
9914 CODE_FOR_tx_assist
9915};
9916
9917static void
9918s390_init_builtins (void)
9919{
9920 tree ftype, uint64_type;
91dfd73e 9921 tree returns_twice_attr = tree_cons (get_identifier ("returns_twice"),
9922 NULL, NULL);
9923 tree noreturn_attr = tree_cons (get_identifier ("noreturn"), NULL, NULL);
5ada7a14 9924
9925 /* void foo (void) */
9926 ftype = build_function_type_list (void_type_node, NULL_TREE);
9927 add_builtin_function ("__builtin_tbeginc", ftype, S390_BUILTIN_TBEGINC,
9928 BUILT_IN_MD, NULL, NULL_TREE);
9929
9930 /* void foo (int) */
9931 ftype = build_function_type_list (void_type_node, integer_type_node,
9932 NULL_TREE);
9933 add_builtin_function ("__builtin_tabort", ftype,
91dfd73e 9934 S390_BUILTIN_TABORT, BUILT_IN_MD, NULL, noreturn_attr);
5ada7a14 9935 add_builtin_function ("__builtin_tx_assist", ftype,
9936 S390_BUILTIN_TX_ASSIST, BUILT_IN_MD, NULL, NULL_TREE);
9937
9938 /* int foo (void *) */
9939 ftype = build_function_type_list (integer_type_node, ptr_type_node, NULL_TREE);
9940 add_builtin_function ("__builtin_tbegin", ftype, S390_BUILTIN_TBEGIN,
91dfd73e 9941 BUILT_IN_MD, NULL, returns_twice_attr);
5ada7a14 9942 add_builtin_function ("__builtin_tbegin_nofloat", ftype,
9943 S390_BUILTIN_TBEGIN_NOFLOAT,
91dfd73e 9944 BUILT_IN_MD, NULL, returns_twice_attr);
5ada7a14 9945
9946 /* int foo (void *, int) */
9947 ftype = build_function_type_list (integer_type_node, ptr_type_node,
9948 integer_type_node, NULL_TREE);
9949 add_builtin_function ("__builtin_tbegin_retry", ftype,
9950 S390_BUILTIN_TBEGIN_RETRY,
9951 BUILT_IN_MD,
91dfd73e 9952 NULL, returns_twice_attr);
5ada7a14 9953 add_builtin_function ("__builtin_tbegin_retry_nofloat", ftype,
9954 S390_BUILTIN_TBEGIN_RETRY_NOFLOAT,
9955 BUILT_IN_MD,
91dfd73e 9956 NULL, returns_twice_attr);
5ada7a14 9957
9958 /* int foo (void) */
9959 ftype = build_function_type_list (integer_type_node, NULL_TREE);
9960 add_builtin_function ("__builtin_tx_nesting_depth", ftype,
9961 S390_BUILTIN_TX_NESTING_DEPTH,
9962 BUILT_IN_MD, NULL, NULL_TREE);
9963 add_builtin_function ("__builtin_tend", ftype,
9964 S390_BUILTIN_TEND, BUILT_IN_MD, NULL, NULL_TREE);
9965
9966 /* void foo (uint64_t *, uint64_t) */
9967 if (TARGET_64BIT)
9968 uint64_type = long_unsigned_type_node;
9969 else
9970 uint64_type = long_long_unsigned_type_node;
9971
9972 ftype = build_function_type_list (void_type_node,
9973 build_pointer_type (uint64_type),
9974 uint64_type, NULL_TREE);
9975 add_builtin_function ("__builtin_non_tx_store", ftype,
9976 S390_BUILTIN_NON_TX_STORE,
9977 BUILT_IN_MD, NULL, NULL_TREE);
9978}
9979
9980/* Expand an expression EXP that calls a built-in function,
9981 with result going to TARGET if that's convenient
9982 (and in mode MODE if that's convenient).
9983 SUBTARGET may be used as the target for computing one of EXP's operands.
9984 IGNORE is nonzero if the value is to be ignored. */
9985
9986static rtx
9987s390_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
9988 enum machine_mode mode ATTRIBUTE_UNUSED,
9989 int ignore ATTRIBUTE_UNUSED)
9990{
9991#define MAX_ARGS 2
9992
9993 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
9994 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
9995 enum insn_code icode;
9996 rtx op[MAX_ARGS], pat;
9997 int arity;
9998 bool nonvoid;
9999 tree arg;
10000 call_expr_arg_iterator iter;
10001
10002 if (fcode >= S390_BUILTIN_max)
10003 internal_error ("bad builtin fcode");
10004 icode = code_for_builtin[fcode];
10005 if (icode == 0)
10006 internal_error ("bad builtin fcode");
10007
ee2dbc39 10008 if (!TARGET_HTM)
10009 error ("Transactional execution builtins not enabled (-mhtm)\n");
5ada7a14 10010
10011 /* Set a flag in the machine specific cfun part in order to support
10012 saving/restoring of FPRs. */
10013 if (fcode == S390_BUILTIN_TBEGIN || fcode == S390_BUILTIN_TBEGIN_RETRY)
10014 cfun->machine->tbegin_p = true;
10015
10016 nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node;
10017
10018 arity = 0;
10019 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp)
10020 {
10021 const struct insn_operand_data *insn_op;
10022
10023 if (arg == error_mark_node)
10024 return NULL_RTX;
10025 if (arity >= MAX_ARGS)
10026 return NULL_RTX;
10027
10028 insn_op = &insn_data[icode].operand[arity + nonvoid];
10029
10030 op[arity] = expand_expr (arg, NULL_RTX, insn_op->mode, EXPAND_NORMAL);
10031
10032 if (!(*insn_op->predicate) (op[arity], insn_op->mode))
10033 {
10034 if (insn_op->predicate == memory_operand)
10035 {
10036 /* Don't move a NULL pointer into a register. Otherwise
10037 we have to rely on combine being able to move it back
10038 in order to get an immediate 0 in the instruction. */
10039 if (op[arity] != const0_rtx)
10040 op[arity] = copy_to_mode_reg (Pmode, op[arity]);
10041 op[arity] = gen_rtx_MEM (insn_op->mode, op[arity]);
10042 }
10043 else
10044 op[arity] = copy_to_mode_reg (insn_op->mode, op[arity]);
10045 }
10046
10047 arity++;
10048 }
10049
10050 if (nonvoid)
10051 {
10052 enum machine_mode tmode = insn_data[icode].operand[0].mode;
10053 if (!target
10054 || GET_MODE (target) != tmode
10055 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
10056 target = gen_reg_rtx (tmode);
10057 }
10058
10059 switch (arity)
10060 {
10061 case 0:
10062 pat = GEN_FCN (icode) (target);
10063 break;
10064 case 1:
10065 if (nonvoid)
10066 pat = GEN_FCN (icode) (target, op[0]);
10067 else
10068 pat = GEN_FCN (icode) (op[0]);
10069 break;
10070 case 2:
10071 if (nonvoid)
10072 pat = GEN_FCN (icode) (target, op[0], op[1]);
10073 else
10074 pat = GEN_FCN (icode) (op[0], op[1]);
10075 break;
10076 default:
10077 gcc_unreachable ();
10078 }
10079 if (!pat)
10080 return NULL_RTX;
10081 emit_insn (pat);
10082
10083 if (nonvoid)
10084 return target;
10085 else
10086 return const0_rtx;
10087}
10088
10089
875862bf 10090/* Output assembly code for the trampoline template to
10091 stdio stream FILE.
10092
10093 On S/390, we use gpr 1 internally in the trampoline code;
10094 gpr 0 is used to hold the static chain. */
10095
4d946732 10096static void
10097s390_asm_trampoline_template (FILE *file)
875862bf 10098{
10099 rtx op[2];
10100 op[0] = gen_rtx_REG (Pmode, 0);
10101 op[1] = gen_rtx_REG (Pmode, 1);
10102
10103 if (TARGET_64BIT)
10104 {
29335855 10105 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
10106 output_asm_insn ("lmg\t%0,%1,14(%1)", op); /* 6 byte */
10107 output_asm_insn ("br\t%1", op); /* 2 byte */
875862bf 10108 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 10));
10109 }
10110 else
10111 {
29335855 10112 output_asm_insn ("basr\t%1,0", op); /* 2 byte */
10113 output_asm_insn ("lm\t%0,%1,6(%1)", op); /* 4 byte */
10114 output_asm_insn ("br\t%1", op); /* 2 byte */
875862bf 10115 ASM_OUTPUT_SKIP (file, (HOST_WIDE_INT)(TRAMPOLINE_SIZE - 8));
10116 }
10117}
10118
10119/* Emit RTL insns to initialize the variable parts of a trampoline.
10120 FNADDR is an RTX for the address of the function's pure code.
10121 CXT is an RTX for the static chain value for the function. */
10122
4d946732 10123static void
10124s390_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt)
875862bf 10125{
4d946732 10126 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
10127 rtx mem;
8a2a84e3 10128
4d946732 10129 emit_block_move (m_tramp, assemble_trampoline_template (),
29335855 10130 GEN_INT (2 * UNITS_PER_LONG), BLOCK_OP_NORMAL);
4d946732 10131
29335855 10132 mem = adjust_address (m_tramp, Pmode, 2 * UNITS_PER_LONG);
4d946732 10133 emit_move_insn (mem, cxt);
29335855 10134 mem = adjust_address (m_tramp, Pmode, 3 * UNITS_PER_LONG);
4d946732 10135 emit_move_insn (mem, fnaddr);
875862bf 10136}
10137
875862bf 10138/* Output assembler code to FILE to increment profiler label # LABELNO
10139 for profiling a function entry. */
10140
10141void
10142s390_function_profiler (FILE *file, int labelno)
10143{
10144 rtx op[7];
10145
10146 char label[128];
10147 ASM_GENERATE_INTERNAL_LABEL (label, "LP", labelno);
10148
10149 fprintf (file, "# function profiler \n");
10150
10151 op[0] = gen_rtx_REG (Pmode, RETURN_REGNUM);
10152 op[1] = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
29c05e22 10153 op[1] = gen_rtx_MEM (Pmode, plus_constant (Pmode, op[1], UNITS_PER_LONG));
875862bf 10154
10155 op[2] = gen_rtx_REG (Pmode, 1);
10156 op[3] = gen_rtx_SYMBOL_REF (Pmode, label);
10157 SYMBOL_REF_FLAGS (op[3]) = SYMBOL_FLAG_LOCAL;
10158
10159 op[4] = gen_rtx_SYMBOL_REF (Pmode, "_mcount");
10160 if (flag_pic)
10161 {
10162 op[4] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[4]), UNSPEC_PLT);
10163 op[4] = gen_rtx_CONST (Pmode, op[4]);
10164 }
10165
10166 if (TARGET_64BIT)
10167 {
10168 output_asm_insn ("stg\t%0,%1", op);
10169 output_asm_insn ("larl\t%2,%3", op);
10170 output_asm_insn ("brasl\t%0,%4", op);
10171 output_asm_insn ("lg\t%0,%1", op);
10172 }
10173 else if (!flag_pic)
10174 {
10175 op[6] = gen_label_rtx ();
10176
10177 output_asm_insn ("st\t%0,%1", op);
10178 output_asm_insn ("bras\t%2,%l6", op);
10179 output_asm_insn (".long\t%4", op);
10180 output_asm_insn (".long\t%3", op);
10181 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
10182 output_asm_insn ("l\t%0,0(%2)", op);
10183 output_asm_insn ("l\t%2,4(%2)", op);
10184 output_asm_insn ("basr\t%0,%0", op);
10185 output_asm_insn ("l\t%0,%1", op);
10186 }
10187 else
10188 {
10189 op[5] = gen_label_rtx ();
10190 op[6] = gen_label_rtx ();
10191
10192 output_asm_insn ("st\t%0,%1", op);
10193 output_asm_insn ("bras\t%2,%l6", op);
10194 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[5]));
10195 output_asm_insn (".long\t%4-%l5", op);
10196 output_asm_insn (".long\t%3-%l5", op);
10197 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[6]));
10198 output_asm_insn ("lr\t%0,%2", op);
10199 output_asm_insn ("a\t%0,0(%2)", op);
10200 output_asm_insn ("a\t%2,4(%2)", op);
10201 output_asm_insn ("basr\t%0,%0", op);
10202 output_asm_insn ("l\t%0,%1", op);
10203 }
10204}
10205
10206/* Encode symbol attributes (local vs. global, tls model) of a SYMBOL_REF
10207 into its SYMBOL_REF_FLAGS. */
10208
10209static void
10210s390_encode_section_info (tree decl, rtx rtl, int first)
10211{
10212 default_encode_section_info (decl, rtl, first);
10213
e68d6a13 10214 if (TREE_CODE (decl) == VAR_DECL)
10215 {
10216 /* If a variable has a forced alignment to < 2 bytes, mark it
10217 with SYMBOL_FLAG_ALIGN1 to prevent it from being used as LARL
10218 operand. */
10219 if (DECL_USER_ALIGN (decl) && DECL_ALIGN (decl) < 16)
10220 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_ALIGN1;
10221 if (!DECL_SIZE (decl)
10222 || !DECL_ALIGN (decl)
35ec552a 10223 || !tree_fits_shwi_p (DECL_SIZE (decl))
e68d6a13 10224 || (DECL_ALIGN (decl) <= 64
fcb97e84 10225 && DECL_ALIGN (decl) != tree_to_shwi (DECL_SIZE (decl))))
e68d6a13 10226 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
10227 }
10228
10229 /* Literal pool references don't have a decl so they are handled
10230 differently here. We rely on the information in the MEM_ALIGN
10231 entry to decide upon natural alignment. */
10232 if (MEM_P (rtl)
10233 && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
10234 && TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0))
10235 && (MEM_ALIGN (rtl) == 0
e632c1c2 10236 || GET_MODE_BITSIZE (GET_MODE (rtl)) == 0
e68d6a13 10237 || MEM_ALIGN (rtl) < GET_MODE_BITSIZE (GET_MODE (rtl))))
10238 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_NOT_NATURALLY_ALIGNED;
875862bf 10239}
10240
10241/* Output thunk to FILE that implements a C++ virtual function call (with
10242 multiple inheritance) to FUNCTION. The thunk adjusts the this pointer
10243 by DELTA, and unless VCALL_OFFSET is zero, applies an additional adjustment
10244 stored at VCALL_OFFSET in the vtable whose address is located at offset 0
10245 relative to the resulting this pointer. */
10246
10247static void
10248s390_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
10249 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10250 tree function)
10251{
10252 rtx op[10];
10253 int nonlocal = 0;
10254
21a38800 10255 /* Make sure unwind info is emitted for the thunk if needed. */
10256 final_start_function (emit_barrier (), file, 1);
10257
875862bf 10258 /* Operand 0 is the target function. */
10259 op[0] = XEXP (DECL_RTL (function), 0);
10260 if (flag_pic && !SYMBOL_REF_LOCAL_P (op[0]))
10261 {
10262 nonlocal = 1;
10263 op[0] = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op[0]),
10264 TARGET_64BIT ? UNSPEC_PLT : UNSPEC_GOT);
10265 op[0] = gen_rtx_CONST (Pmode, op[0]);
10266 }
10267
10268 /* Operand 1 is the 'this' pointer. */
10269 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
10270 op[1] = gen_rtx_REG (Pmode, 3);
10271 else
10272 op[1] = gen_rtx_REG (Pmode, 2);
10273
10274 /* Operand 2 is the delta. */
10275 op[2] = GEN_INT (delta);
10276
10277 /* Operand 3 is the vcall_offset. */
10278 op[3] = GEN_INT (vcall_offset);
10279
10280 /* Operand 4 is the temporary register. */
10281 op[4] = gen_rtx_REG (Pmode, 1);
10282
10283 /* Operands 5 to 8 can be used as labels. */
10284 op[5] = NULL_RTX;
10285 op[6] = NULL_RTX;
10286 op[7] = NULL_RTX;
10287 op[8] = NULL_RTX;
10288
10289 /* Operand 9 can be used for temporary register. */
10290 op[9] = NULL_RTX;
10291
10292 /* Generate code. */
10293 if (TARGET_64BIT)
10294 {
10295 /* Setup literal pool pointer if required. */
10296 if ((!DISP_IN_RANGE (delta)
163277cf 10297 && !CONST_OK_FOR_K (delta)
10298 && !CONST_OK_FOR_Os (delta))
875862bf 10299 || (!DISP_IN_RANGE (vcall_offset)
163277cf 10300 && !CONST_OK_FOR_K (vcall_offset)
10301 && !CONST_OK_FOR_Os (vcall_offset)))
875862bf 10302 {
10303 op[5] = gen_label_rtx ();
10304 output_asm_insn ("larl\t%4,%5", op);
10305 }
10306
10307 /* Add DELTA to this pointer. */
10308 if (delta)
10309 {
cb888f33 10310 if (CONST_OK_FOR_J (delta))
875862bf 10311 output_asm_insn ("la\t%1,%2(%1)", op);
10312 else if (DISP_IN_RANGE (delta))
10313 output_asm_insn ("lay\t%1,%2(%1)", op);
cb888f33 10314 else if (CONST_OK_FOR_K (delta))
875862bf 10315 output_asm_insn ("aghi\t%1,%2", op);
163277cf 10316 else if (CONST_OK_FOR_Os (delta))
10317 output_asm_insn ("agfi\t%1,%2", op);
875862bf 10318 else
10319 {
10320 op[6] = gen_label_rtx ();
10321 output_asm_insn ("agf\t%1,%6-%5(%4)", op);
10322 }
10323 }
10324
10325 /* Perform vcall adjustment. */
10326 if (vcall_offset)
10327 {
10328 if (DISP_IN_RANGE (vcall_offset))
10329 {
10330 output_asm_insn ("lg\t%4,0(%1)", op);
10331 output_asm_insn ("ag\t%1,%3(%4)", op);
10332 }
cb888f33 10333 else if (CONST_OK_FOR_K (vcall_offset))
875862bf 10334 {
10335 output_asm_insn ("lghi\t%4,%3", op);
10336 output_asm_insn ("ag\t%4,0(%1)", op);
10337 output_asm_insn ("ag\t%1,0(%4)", op);
10338 }
163277cf 10339 else if (CONST_OK_FOR_Os (vcall_offset))
10340 {
10341 output_asm_insn ("lgfi\t%4,%3", op);
10342 output_asm_insn ("ag\t%4,0(%1)", op);
10343 output_asm_insn ("ag\t%1,0(%4)", op);
10344 }
875862bf 10345 else
10346 {
10347 op[7] = gen_label_rtx ();
10348 output_asm_insn ("llgf\t%4,%7-%5(%4)", op);
10349 output_asm_insn ("ag\t%4,0(%1)", op);
10350 output_asm_insn ("ag\t%1,0(%4)", op);
10351 }
10352 }
10353
10354 /* Jump to target. */
10355 output_asm_insn ("jg\t%0", op);
10356
10357 /* Output literal pool if required. */
10358 if (op[5])
10359 {
10360 output_asm_insn (".align\t4", op);
10361 targetm.asm_out.internal_label (file, "L",
10362 CODE_LABEL_NUMBER (op[5]));
10363 }
10364 if (op[6])
10365 {
10366 targetm.asm_out.internal_label (file, "L",
10367 CODE_LABEL_NUMBER (op[6]));
10368 output_asm_insn (".long\t%2", op);
10369 }
10370 if (op[7])
10371 {
10372 targetm.asm_out.internal_label (file, "L",
10373 CODE_LABEL_NUMBER (op[7]));
10374 output_asm_insn (".long\t%3", op);
10375 }
10376 }
10377 else
10378 {
10379 /* Setup base pointer if required. */
10380 if (!vcall_offset
10381 || (!DISP_IN_RANGE (delta)
163277cf 10382 && !CONST_OK_FOR_K (delta)
10383 && !CONST_OK_FOR_Os (delta))
875862bf 10384 || (!DISP_IN_RANGE (delta)
163277cf 10385 && !CONST_OK_FOR_K (vcall_offset)
10386 && !CONST_OK_FOR_Os (vcall_offset)))
875862bf 10387 {
10388 op[5] = gen_label_rtx ();
10389 output_asm_insn ("basr\t%4,0", op);
10390 targetm.asm_out.internal_label (file, "L",
10391 CODE_LABEL_NUMBER (op[5]));
10392 }
10393
10394 /* Add DELTA to this pointer. */
10395 if (delta)
10396 {
cb888f33 10397 if (CONST_OK_FOR_J (delta))
875862bf 10398 output_asm_insn ("la\t%1,%2(%1)", op);
10399 else if (DISP_IN_RANGE (delta))
10400 output_asm_insn ("lay\t%1,%2(%1)", op);
cb888f33 10401 else if (CONST_OK_FOR_K (delta))
875862bf 10402 output_asm_insn ("ahi\t%1,%2", op);
163277cf 10403 else if (CONST_OK_FOR_Os (delta))
10404 output_asm_insn ("afi\t%1,%2", op);
875862bf 10405 else
10406 {
10407 op[6] = gen_label_rtx ();
10408 output_asm_insn ("a\t%1,%6-%5(%4)", op);
10409 }
10410 }
10411
10412 /* Perform vcall adjustment. */
10413 if (vcall_offset)
10414 {
cb888f33 10415 if (CONST_OK_FOR_J (vcall_offset))
875862bf 10416 {
0451e449 10417 output_asm_insn ("l\t%4,0(%1)", op);
875862bf 10418 output_asm_insn ("a\t%1,%3(%4)", op);
10419 }
10420 else if (DISP_IN_RANGE (vcall_offset))
10421 {
0451e449 10422 output_asm_insn ("l\t%4,0(%1)", op);
875862bf 10423 output_asm_insn ("ay\t%1,%3(%4)", op);
10424 }
cb888f33 10425 else if (CONST_OK_FOR_K (vcall_offset))
875862bf 10426 {
10427 output_asm_insn ("lhi\t%4,%3", op);
10428 output_asm_insn ("a\t%4,0(%1)", op);
10429 output_asm_insn ("a\t%1,0(%4)", op);
10430 }
163277cf 10431 else if (CONST_OK_FOR_Os (vcall_offset))
10432 {
10433 output_asm_insn ("iilf\t%4,%3", op);
10434 output_asm_insn ("a\t%4,0(%1)", op);
10435 output_asm_insn ("a\t%1,0(%4)", op);
10436 }
875862bf 10437 else
10438 {
10439 op[7] = gen_label_rtx ();
10440 output_asm_insn ("l\t%4,%7-%5(%4)", op);
10441 output_asm_insn ("a\t%4,0(%1)", op);
10442 output_asm_insn ("a\t%1,0(%4)", op);
10443 }
4673c1a0 10444
875862bf 10445 /* We had to clobber the base pointer register.
10446 Re-setup the base pointer (with a different base). */
10447 op[5] = gen_label_rtx ();
10448 output_asm_insn ("basr\t%4,0", op);
10449 targetm.asm_out.internal_label (file, "L",
10450 CODE_LABEL_NUMBER (op[5]));
10451 }
4673c1a0 10452
875862bf 10453 /* Jump to target. */
10454 op[8] = gen_label_rtx ();
4673c1a0 10455
875862bf 10456 if (!flag_pic)
10457 output_asm_insn ("l\t%4,%8-%5(%4)", op);
10458 else if (!nonlocal)
10459 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10460 /* We cannot call through .plt, since .plt requires %r12 loaded. */
10461 else if (flag_pic == 1)
10462 {
10463 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10464 output_asm_insn ("l\t%4,%0(%4)", op);
10465 }
10466 else if (flag_pic == 2)
10467 {
10468 op[9] = gen_rtx_REG (Pmode, 0);
10469 output_asm_insn ("l\t%9,%8-4-%5(%4)", op);
10470 output_asm_insn ("a\t%4,%8-%5(%4)", op);
10471 output_asm_insn ("ar\t%4,%9", op);
10472 output_asm_insn ("l\t%4,0(%4)", op);
10473 }
4673c1a0 10474
875862bf 10475 output_asm_insn ("br\t%4", op);
4673c1a0 10476
875862bf 10477 /* Output literal pool. */
10478 output_asm_insn (".align\t4", op);
4673c1a0 10479
875862bf 10480 if (nonlocal && flag_pic == 2)
10481 output_asm_insn (".long\t%0", op);
10482 if (nonlocal)
10483 {
10484 op[0] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
10485 SYMBOL_REF_FLAGS (op[0]) = SYMBOL_FLAG_LOCAL;
10486 }
d93e0d9f 10487
875862bf 10488 targetm.asm_out.internal_label (file, "L", CODE_LABEL_NUMBER (op[8]));
10489 if (!flag_pic)
10490 output_asm_insn (".long\t%0", op);
10491 else
10492 output_asm_insn (".long\t%0-%5", op);
4673c1a0 10493
875862bf 10494 if (op[6])
10495 {
10496 targetm.asm_out.internal_label (file, "L",
10497 CODE_LABEL_NUMBER (op[6]));
10498 output_asm_insn (".long\t%2", op);
10499 }
10500 if (op[7])
10501 {
10502 targetm.asm_out.internal_label (file, "L",
10503 CODE_LABEL_NUMBER (op[7]));
10504 output_asm_insn (".long\t%3", op);
10505 }
4673c1a0 10506 }
21a38800 10507 final_end_function ();
4673c1a0 10508}
10509
875862bf 10510static bool
10511s390_valid_pointer_mode (enum machine_mode mode)
10512{
10513 return (mode == SImode || (TARGET_64BIT && mode == DImode));
10514}
56769981 10515
347301d6 10516/* Checks whether the given CALL_EXPR would use a caller
875862bf 10517 saved register. This is used to decide whether sibling call
10518 optimization could be performed on the respective function
10519 call. */
be00aaa8 10520
875862bf 10521static bool
347301d6 10522s390_call_saved_register_used (tree call_expr)
be00aaa8 10523{
39cba157 10524 CUMULATIVE_ARGS cum_v;
10525 cumulative_args_t cum;
875862bf 10526 tree parameter;
10527 enum machine_mode mode;
10528 tree type;
10529 rtx parm_rtx;
347301d6 10530 int reg, i;
be00aaa8 10531
39cba157 10532 INIT_CUMULATIVE_ARGS (cum_v, NULL, NULL, 0, 0);
10533 cum = pack_cumulative_args (&cum_v);
be00aaa8 10534
347301d6 10535 for (i = 0; i < call_expr_nargs (call_expr); i++)
875862bf 10536 {
347301d6 10537 parameter = CALL_EXPR_ARG (call_expr, i);
32eda510 10538 gcc_assert (parameter);
be00aaa8 10539
875862bf 10540 /* For an undeclared variable passed as parameter we will get
10541 an ERROR_MARK node here. */
10542 if (TREE_CODE (parameter) == ERROR_MARK)
10543 return true;
be00aaa8 10544
32eda510 10545 type = TREE_TYPE (parameter);
10546 gcc_assert (type);
be00aaa8 10547
32eda510 10548 mode = TYPE_MODE (type);
10549 gcc_assert (mode);
be00aaa8 10550
39cba157 10551 if (pass_by_reference (&cum_v, mode, type, true))
875862bf 10552 {
10553 mode = Pmode;
10554 type = build_pointer_type (type);
10555 }
be00aaa8 10556
39cba157 10557 parm_rtx = s390_function_arg (cum, mode, type, 0);
be00aaa8 10558
39cba157 10559 s390_function_arg_advance (cum, mode, type, 0);
be00aaa8 10560
b5fdc416 10561 if (!parm_rtx)
10562 continue;
10563
10564 if (REG_P (parm_rtx))
10565 {
cc6a115b 10566 for (reg = 0;
10567 reg < HARD_REGNO_NREGS (REGNO (parm_rtx), GET_MODE (parm_rtx));
10568 reg++)
b5fdc416 10569 if (!call_used_regs[reg + REGNO (parm_rtx)])
10570 return true;
10571 }
10572
10573 if (GET_CODE (parm_rtx) == PARALLEL)
875862bf 10574 {
b5fdc416 10575 int i;
cc6a115b 10576
b5fdc416 10577 for (i = 0; i < XVECLEN (parm_rtx, 0); i++)
10578 {
10579 rtx r = XEXP (XVECEXP (parm_rtx, 0, i), 0);
b5fdc416 10580
10581 gcc_assert (REG_P (r));
10582
cc6a115b 10583 for (reg = 0;
10584 reg < HARD_REGNO_NREGS (REGNO (r), GET_MODE (r));
10585 reg++)
b5fdc416 10586 if (!call_used_regs[reg + REGNO (r)])
10587 return true;
10588 }
875862bf 10589 }
b5fdc416 10590
875862bf 10591 }
10592 return false;
10593}
be00aaa8 10594
875862bf 10595/* Return true if the given call expression can be
10596 turned into a sibling call.
10597 DECL holds the declaration of the function to be called whereas
10598 EXP is the call expression itself. */
be00aaa8 10599
875862bf 10600static bool
10601s390_function_ok_for_sibcall (tree decl, tree exp)
10602{
10603 /* The TPF epilogue uses register 1. */
10604 if (TARGET_TPF_PROFILING)
10605 return false;
be00aaa8 10606
875862bf 10607 /* The 31 bit PLT code uses register 12 (GOT pointer - caller saved)
10608 which would have to be restored before the sibcall. */
a47b0dc3 10609 if (!TARGET_64BIT && flag_pic && decl && !targetm.binds_local_p (decl))
875862bf 10610 return false;
be00aaa8 10611
875862bf 10612 /* Register 6 on s390 is available as an argument register but unfortunately
10613 "caller saved". This makes functions needing this register for arguments
10614 not suitable for sibcalls. */
347301d6 10615 return !s390_call_saved_register_used (exp);
875862bf 10616}
be00aaa8 10617
875862bf 10618/* Return the fixed registers used for condition codes. */
be00aaa8 10619
875862bf 10620static bool
10621s390_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2)
10622{
10623 *p1 = CC_REGNUM;
10624 *p2 = INVALID_REGNUM;
ffead1ca 10625
875862bf 10626 return true;
10627}
be00aaa8 10628
875862bf 10629/* This function is used by the call expanders of the machine description.
10630 It emits the call insn itself together with the necessary operations
10631 to adjust the target address and returns the emitted insn.
10632 ADDR_LOCATION is the target address rtx
10633 TLS_CALL the location of the thread-local symbol
10634 RESULT_REG the register where the result of the call should be stored
10635 RETADDR_REG the register where the return address should be stored
10636 If this parameter is NULL_RTX the call is considered
10637 to be a sibling call. */
be00aaa8 10638
875862bf 10639rtx
10640s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
10641 rtx retaddr_reg)
4673c1a0 10642{
875862bf 10643 bool plt_call = false;
10644 rtx insn;
10645 rtx call;
10646 rtx clobber;
10647 rtvec vec;
4a1c604e 10648
875862bf 10649 /* Direct function calls need special treatment. */
10650 if (GET_CODE (addr_location) == SYMBOL_REF)
4673c1a0 10651 {
875862bf 10652 /* When calling a global routine in PIC mode, we must
10653 replace the symbol itself with the PLT stub. */
10654 if (flag_pic && !SYMBOL_REF_LOCAL_P (addr_location))
10655 {
9c7185f7 10656 if (retaddr_reg != NULL_RTX)
10657 {
10658 addr_location = gen_rtx_UNSPEC (Pmode,
10659 gen_rtvec (1, addr_location),
10660 UNSPEC_PLT);
10661 addr_location = gen_rtx_CONST (Pmode, addr_location);
10662 plt_call = true;
10663 }
10664 else
10665 /* For -fpic code the PLT entries might use r12 which is
10666 call-saved. Therefore we cannot do a sibcall when
10667 calling directly using a symbol ref. When reaching
10668 this point we decided (in s390_function_ok_for_sibcall)
10669 to do a sibcall for a function pointer but one of the
10670 optimizers was able to get rid of the function pointer
10671 by propagating the symbol ref into the call. This
10672 optimization is illegal for S/390 so we turn the direct
10673 call into a indirect call again. */
10674 addr_location = force_reg (Pmode, addr_location);
875862bf 10675 }
10676
10677 /* Unless we can use the bras(l) insn, force the
10678 routine address into a register. */
10679 if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH)
10680 {
10681 if (flag_pic)
10682 addr_location = legitimize_pic_address (addr_location, 0);
10683 else
10684 addr_location = force_reg (Pmode, addr_location);
10685 }
4673c1a0 10686 }
875862bf 10687
10688 /* If it is already an indirect call or the code above moved the
10689 SYMBOL_REF to somewhere else make sure the address can be found in
10690 register 1. */
10691 if (retaddr_reg == NULL_RTX
10692 && GET_CODE (addr_location) != SYMBOL_REF
10693 && !plt_call)
4673c1a0 10694 {
875862bf 10695 emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
10696 addr_location = gen_rtx_REG (Pmode, SIBCALL_REGNUM);
4673c1a0 10697 }
4673c1a0 10698
875862bf 10699 addr_location = gen_rtx_MEM (QImode, addr_location);
10700 call = gen_rtx_CALL (VOIDmode, addr_location, const0_rtx);
8b4a4127 10701
875862bf 10702 if (result_reg != NULL_RTX)
10703 call = gen_rtx_SET (VOIDmode, result_reg, call);
8b4a4127 10704
875862bf 10705 if (retaddr_reg != NULL_RTX)
10706 {
10707 clobber = gen_rtx_CLOBBER (VOIDmode, retaddr_reg);
f81e845f 10708
875862bf 10709 if (tls_call != NULL_RTX)
10710 vec = gen_rtvec (3, call, clobber,
10711 gen_rtx_USE (VOIDmode, tls_call));
10712 else
10713 vec = gen_rtvec (2, call, clobber);
8b4a4127 10714
875862bf 10715 call = gen_rtx_PARALLEL (VOIDmode, vec);
10716 }
8b4a4127 10717
875862bf 10718 insn = emit_call_insn (call);
8b4a4127 10719
875862bf 10720 /* 31-bit PLT stubs and tls calls use the GOT register implicitly. */
10721 if ((!TARGET_64BIT && plt_call) || tls_call != NULL_RTX)
10722 {
10723 /* s390_function_ok_for_sibcall should
10724 have denied sibcalls in this case. */
32eda510 10725 gcc_assert (retaddr_reg != NULL_RTX);
c60a7572 10726 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), gen_rtx_REG (Pmode, 12));
875862bf 10727 }
10728 return insn;
10729}
8b4a4127 10730
b2d7ede1 10731/* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
8b4a4127 10732
b2d7ede1 10733static void
875862bf 10734s390_conditional_register_usage (void)
10735{
10736 int i;
8b4a4127 10737
8b4a4127 10738 if (flag_pic)
10739 {
875862bf 10740 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10741 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
8b4a4127 10742 }
875862bf 10743 if (TARGET_CPU_ZARCH)
8b4a4127 10744 {
d1a5573e 10745 fixed_regs[BASE_REGNUM] = 0;
10746 call_used_regs[BASE_REGNUM] = 0;
875862bf 10747 fixed_regs[RETURN_REGNUM] = 0;
10748 call_used_regs[RETURN_REGNUM] = 0;
8b4a4127 10749 }
875862bf 10750 if (TARGET_64BIT)
8b4a4127 10751 {
6a2469fe 10752 for (i = FPR8_REGNUM; i <= FPR15_REGNUM; i++)
875862bf 10753 call_used_regs[i] = call_really_used_regs[i] = 0;
8b4a4127 10754 }
10755 else
10756 {
6a2469fe 10757 call_used_regs[FPR4_REGNUM] = call_really_used_regs[FPR4_REGNUM] = 0;
10758 call_used_regs[FPR6_REGNUM] = call_really_used_regs[FPR6_REGNUM] = 0;
875862bf 10759 }
8b4a4127 10760
875862bf 10761 if (TARGET_SOFT_FLOAT)
10762 {
6a2469fe 10763 for (i = FPR0_REGNUM; i <= FPR15_REGNUM; i++)
875862bf 10764 call_used_regs[i] = fixed_regs[i] = 1;
8b4a4127 10765 }
10766}
10767
875862bf 10768/* Corresponding function to eh_return expander. */
7811991d 10769
875862bf 10770static GTY(()) rtx s390_tpf_eh_return_symbol;
10771void
10772s390_emit_tpf_eh_return (rtx target)
7811991d 10773{
875862bf 10774 rtx insn, reg;
525d1294 10775
875862bf 10776 if (!s390_tpf_eh_return_symbol)
10777 s390_tpf_eh_return_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tpf_eh_return");
10778
10779 reg = gen_rtx_REG (Pmode, 2);
10780
10781 emit_move_insn (reg, target);
10782 insn = s390_emit_call (s390_tpf_eh_return_symbol, NULL_RTX, reg,
10783 gen_rtx_REG (Pmode, RETURN_REGNUM));
10784 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), reg);
10785
10786 emit_move_insn (EH_RETURN_HANDLER_RTX, reg);
be00aaa8 10787}
10788
875862bf 10789/* Rework the prologue/epilogue to avoid saving/restoring
10790 registers unnecessarily. */
c20f8a1d 10791
6988553d 10792static void
875862bf 10793s390_optimize_prologue (void)
c6933ba6 10794{
875862bf 10795 rtx insn, new_insn, next_insn;
c20f8a1d 10796
875862bf 10797 /* Do a final recompute of the frame-related data. */
ff4ce128 10798 s390_optimize_register_info ();
c20f8a1d 10799
875862bf 10800 /* If all special registers are in fact used, there's nothing we
10801 can do, so no point in walking the insn list. */
c20f8a1d 10802
ffead1ca 10803 if (cfun_frame_layout.first_save_gpr <= BASE_REGNUM
875862bf 10804 && cfun_frame_layout.last_save_gpr >= BASE_REGNUM
ffead1ca 10805 && (TARGET_CPU_ZARCH
10806 || (cfun_frame_layout.first_save_gpr <= RETURN_REGNUM
875862bf 10807 && cfun_frame_layout.last_save_gpr >= RETURN_REGNUM)))
10808 return;
c20f8a1d 10809
875862bf 10810 /* Search for prologue/epilogue insns and replace them. */
c20f8a1d 10811
875862bf 10812 for (insn = get_insns (); insn; insn = next_insn)
10813 {
10814 int first, last, off;
10815 rtx set, base, offset;
ff4ce128 10816 rtx pat;
c20f8a1d 10817
875862bf 10818 next_insn = NEXT_INSN (insn);
d7bec695 10819
ff4ce128 10820 if (! NONJUMP_INSN_P (insn) || ! RTX_FRAME_RELATED_P (insn))
875862bf 10821 continue;
c20f8a1d 10822
ff4ce128 10823 pat = PATTERN (insn);
10824
10825 /* Remove ldgr/lgdr instructions used for saving and restore
10826 GPRs if possible. */
10827 if (TARGET_Z10
10828 && GET_CODE (pat) == SET
10829 && GET_MODE (SET_SRC (pat)) == DImode
10830 && REG_P (SET_SRC (pat))
10831 && REG_P (SET_DEST (pat)))
10832 {
10833 int src_regno = REGNO (SET_SRC (pat));
10834 int dest_regno = REGNO (SET_DEST (pat));
10835 int gpr_regno;
10836 int fpr_regno;
10837
10838 if (!((GENERAL_REGNO_P (src_regno) && FP_REGNO_P (dest_regno))
10839 || (FP_REGNO_P (src_regno) && GENERAL_REGNO_P (dest_regno))))
10840 continue;
10841
10842 gpr_regno = GENERAL_REGNO_P (src_regno) ? src_regno : dest_regno;
10843 fpr_regno = FP_REGNO_P (src_regno) ? src_regno : dest_regno;
10844
10845 /* GPR must be call-saved, FPR must be call-clobbered. */
10846 if (!call_really_used_regs[fpr_regno]
10847 || call_really_used_regs[gpr_regno])
10848 continue;
10849
10850 /* For restores we have to revert the frame related flag
10851 since no debug info is supposed to be generated for
10852 these. */
10853 if (dest_regno == gpr_regno)
10854 RTX_FRAME_RELATED_P (insn) = 0;
10855
10856 /* It must not happen that what we once saved in an FPR now
10857 needs a stack slot. */
10858 gcc_assert (cfun_gpr_save_slot (gpr_regno) != -1);
10859
10860 if (cfun_gpr_save_slot (gpr_regno) == 0)
10861 {
10862 remove_insn (insn);
10863 continue;
10864 }
10865 }
10866
10867 if (GET_CODE (pat) == PARALLEL
10868 && store_multiple_operation (pat, VOIDmode))
c20f8a1d 10869 {
ff4ce128 10870 set = XVECEXP (pat, 0, 0);
875862bf 10871 first = REGNO (SET_SRC (set));
ff4ce128 10872 last = first + XVECLEN (pat, 0) - 1;
875862bf 10873 offset = const0_rtx;
10874 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10875 off = INTVAL (offset);
c20f8a1d 10876
875862bf 10877 if (GET_CODE (base) != REG || off < 0)
10878 continue;
43944aa4 10879 if (cfun_frame_layout.first_save_gpr != -1
10880 && (cfun_frame_layout.first_save_gpr < first
10881 || cfun_frame_layout.last_save_gpr > last))
10882 continue;
875862bf 10883 if (REGNO (base) != STACK_POINTER_REGNUM
10884 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10885 continue;
10886 if (first > BASE_REGNUM || last < BASE_REGNUM)
10887 continue;
10888
10889 if (cfun_frame_layout.first_save_gpr != -1)
c20f8a1d 10890 {
ffead1ca 10891 new_insn = save_gprs (base,
875862bf 10892 off + (cfun_frame_layout.first_save_gpr
b5fdc416 10893 - first) * UNITS_PER_LONG,
875862bf 10894 cfun_frame_layout.first_save_gpr,
10895 cfun_frame_layout.last_save_gpr);
10896 new_insn = emit_insn_before (new_insn, insn);
10897 INSN_ADDRESSES_NEW (new_insn, -1);
c20f8a1d 10898 }
c20f8a1d 10899
875862bf 10900 remove_insn (insn);
10901 continue;
c20f8a1d 10902 }
10903
43944aa4 10904 if (cfun_frame_layout.first_save_gpr == -1
ff4ce128 10905 && GET_CODE (pat) == SET
10906 && GENERAL_REG_P (SET_SRC (pat))
10907 && GET_CODE (SET_DEST (pat)) == MEM)
c20f8a1d 10908 {
ff4ce128 10909 set = pat;
875862bf 10910 first = REGNO (SET_SRC (set));
10911 offset = const0_rtx;
10912 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
10913 off = INTVAL (offset);
c20f8a1d 10914
875862bf 10915 if (GET_CODE (base) != REG || off < 0)
10916 continue;
10917 if (REGNO (base) != STACK_POINTER_REGNUM
10918 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10919 continue;
c20f8a1d 10920
875862bf 10921 remove_insn (insn);
10922 continue;
c20f8a1d 10923 }
10924
ff4ce128 10925 if (GET_CODE (pat) == PARALLEL
10926 && load_multiple_operation (pat, VOIDmode))
d7bec695 10927 {
ff4ce128 10928 set = XVECEXP (pat, 0, 0);
875862bf 10929 first = REGNO (SET_DEST (set));
ff4ce128 10930 last = first + XVECLEN (pat, 0) - 1;
875862bf 10931 offset = const0_rtx;
10932 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10933 off = INTVAL (offset);
d7bec695 10934
875862bf 10935 if (GET_CODE (base) != REG || off < 0)
10936 continue;
ff4ce128 10937
10938 RTX_FRAME_RELATED_P (insn) = 0;
10939
43944aa4 10940 if (cfun_frame_layout.first_restore_gpr != -1
10941 && (cfun_frame_layout.first_restore_gpr < first
10942 || cfun_frame_layout.last_restore_gpr > last))
10943 continue;
875862bf 10944 if (REGNO (base) != STACK_POINTER_REGNUM
10945 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10946 continue;
10947 if (first > BASE_REGNUM || last < BASE_REGNUM)
10948 continue;
c20f8a1d 10949
875862bf 10950 if (cfun_frame_layout.first_restore_gpr != -1)
10951 {
ffead1ca 10952 new_insn = restore_gprs (base,
875862bf 10953 off + (cfun_frame_layout.first_restore_gpr
b5fdc416 10954 - first) * UNITS_PER_LONG,
875862bf 10955 cfun_frame_layout.first_restore_gpr,
10956 cfun_frame_layout.last_restore_gpr);
ff4ce128 10957 RTX_FRAME_RELATED_P (new_insn) = 0;
875862bf 10958 new_insn = emit_insn_before (new_insn, insn);
10959 INSN_ADDRESSES_NEW (new_insn, -1);
10960 }
d7bec695 10961
875862bf 10962 remove_insn (insn);
10963 continue;
d7bec695 10964 }
10965
43944aa4 10966 if (cfun_frame_layout.first_restore_gpr == -1
ff4ce128 10967 && GET_CODE (pat) == SET
10968 && GENERAL_REG_P (SET_DEST (pat))
10969 && GET_CODE (SET_SRC (pat)) == MEM)
c20f8a1d 10970 {
ff4ce128 10971 set = pat;
875862bf 10972 first = REGNO (SET_DEST (set));
10973 offset = const0_rtx;
10974 base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
10975 off = INTVAL (offset);
f81e845f 10976
875862bf 10977 if (GET_CODE (base) != REG || off < 0)
10978 continue;
ff4ce128 10979
10980 RTX_FRAME_RELATED_P (insn) = 0;
10981
875862bf 10982 if (REGNO (base) != STACK_POINTER_REGNUM
10983 && REGNO (base) != HARD_FRAME_POINTER_REGNUM)
10984 continue;
5a5e802f 10985
875862bf 10986 remove_insn (insn);
10987 continue;
10988 }
10989 }
5a5e802f 10990}
10991
33d033da 10992/* On z10 and later the dynamic branch prediction must see the
10993 backward jump within a certain windows. If not it falls back to
10994 the static prediction. This function rearranges the loop backward
10995 branch in a way which makes the static prediction always correct.
10996 The function returns true if it added an instruction. */
73df8a45 10997static bool
33d033da 10998s390_fix_long_loop_prediction (rtx insn)
73df8a45 10999{
11000 rtx set = single_set (insn);
11001 rtx code_label, label_ref, new_label;
11002 rtx uncond_jump;
11003 rtx cur_insn;
11004 rtx tmp;
11005 int distance;
11006
11007 /* This will exclude branch on count and branch on index patterns
11008 since these are correctly statically predicted. */
11009 if (!set
11010 || SET_DEST (set) != pc_rtx
11011 || GET_CODE (SET_SRC(set)) != IF_THEN_ELSE)
11012 return false;
11013
11014 label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
11015 XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
11016
11017 gcc_assert (GET_CODE (label_ref) == LABEL_REF);
11018
11019 code_label = XEXP (label_ref, 0);
11020
11021 if (INSN_ADDRESSES (INSN_UID (code_label)) == -1
11022 || INSN_ADDRESSES (INSN_UID (insn)) == -1
11023 || (INSN_ADDRESSES (INSN_UID (insn))
33d033da 11024 - INSN_ADDRESSES (INSN_UID (code_label)) < PREDICT_DISTANCE))
73df8a45 11025 return false;
11026
11027 for (distance = 0, cur_insn = PREV_INSN (insn);
33d033da 11028 distance < PREDICT_DISTANCE - 6;
73df8a45 11029 distance += get_attr_length (cur_insn), cur_insn = PREV_INSN (cur_insn))
11030 if (!cur_insn || JUMP_P (cur_insn) || LABEL_P (cur_insn))
11031 return false;
11032
11033 new_label = gen_label_rtx ();
11034 uncond_jump = emit_jump_insn_after (
11035 gen_rtx_SET (VOIDmode, pc_rtx,
11036 gen_rtx_LABEL_REF (VOIDmode, code_label)),
11037 insn);
11038 emit_label_after (new_label, uncond_jump);
11039
11040 tmp = XEXP (SET_SRC (set), 1);
11041 XEXP (SET_SRC (set), 1) = XEXP (SET_SRC (set), 2);
11042 XEXP (SET_SRC (set), 2) = tmp;
11043 INSN_CODE (insn) = -1;
11044
11045 XEXP (label_ref, 0) = new_label;
11046 JUMP_LABEL (insn) = new_label;
11047 JUMP_LABEL (uncond_jump) = code_label;
11048
11049 return true;
11050}
11051
3b14a2e6 11052/* Returns 1 if INSN reads the value of REG for purposes not related
11053 to addressing of memory, and 0 otherwise. */
11054static int
11055s390_non_addr_reg_read_p (rtx reg, rtx insn)
11056{
11057 return reg_referenced_p (reg, PATTERN (insn))
11058 && !reg_used_in_mem_p (REGNO (reg), PATTERN (insn));
11059}
11060
512d9edf 11061/* Starting from INSN find_cond_jump looks downwards in the insn
11062 stream for a single jump insn which is the last user of the
11063 condition code set in INSN. */
11064static rtx
11065find_cond_jump (rtx insn)
11066{
11067 for (; insn; insn = NEXT_INSN (insn))
11068 {
11069 rtx ite, cc;
11070
11071 if (LABEL_P (insn))
11072 break;
11073
11074 if (!JUMP_P (insn))
11075 {
11076 if (reg_mentioned_p (gen_rtx_REG (CCmode, CC_REGNUM), insn))
11077 break;
11078 continue;
11079 }
11080
11081 /* This will be triggered by a return. */
11082 if (GET_CODE (PATTERN (insn)) != SET)
11083 break;
11084
11085 gcc_assert (SET_DEST (PATTERN (insn)) == pc_rtx);
11086 ite = SET_SRC (PATTERN (insn));
11087
11088 if (GET_CODE (ite) != IF_THEN_ELSE)
11089 break;
11090
11091 cc = XEXP (XEXP (ite, 0), 0);
11092 if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc)))
11093 break;
11094
11095 if (find_reg_note (insn, REG_DEAD, cc))
11096 return insn;
11097 break;
11098 }
11099
11100 return NULL_RTX;
11101}
11102
11103/* Swap the condition in COND and the operands in OP0 and OP1 so that
11104 the semantics does not change. If NULL_RTX is passed as COND the
11105 function tries to find the conditional jump starting with INSN. */
11106static void
11107s390_swap_cmp (rtx cond, rtx *op0, rtx *op1, rtx insn)
11108{
11109 rtx tmp = *op0;
11110
11111 if (cond == NULL_RTX)
11112 {
11113 rtx jump = find_cond_jump (NEXT_INSN (insn));
11114 jump = jump ? single_set (jump) : NULL_RTX;
11115
11116 if (jump == NULL_RTX)
11117 return;
11118
11119 cond = XEXP (XEXP (jump, 1), 0);
11120 }
11121
11122 *op0 = *op1;
11123 *op1 = tmp;
11124 PUT_CODE (cond, swap_condition (GET_CODE (cond)));
11125}
3b14a2e6 11126
11127/* On z10, instructions of the compare-and-branch family have the
11128 property to access the register occurring as second operand with
11129 its bits complemented. If such a compare is grouped with a second
11130 instruction that accesses the same register non-complemented, and
11131 if that register's value is delivered via a bypass, then the
11132 pipeline recycles, thereby causing significant performance decline.
11133 This function locates such situations and exchanges the two
73df8a45 11134 operands of the compare. The function return true whenever it
11135 added an insn. */
11136static bool
11137s390_z10_optimize_cmp (rtx insn)
3b14a2e6 11138{
73df8a45 11139 rtx prev_insn, next_insn;
11140 bool insn_added_p = false;
11141 rtx cond, *op0, *op1;
3b14a2e6 11142
73df8a45 11143 if (GET_CODE (PATTERN (insn)) == PARALLEL)
3b14a2e6 11144 {
73df8a45 11145 /* Handle compare and branch and branch on count
11146 instructions. */
11147 rtx pattern = single_set (insn);
512d9edf 11148
73df8a45 11149 if (!pattern
11150 || SET_DEST (pattern) != pc_rtx
11151 || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE)
11152 return false;
3b14a2e6 11153
73df8a45 11154 cond = XEXP (SET_SRC (pattern), 0);
11155 op0 = &XEXP (cond, 0);
11156 op1 = &XEXP (cond, 1);
11157 }
11158 else if (GET_CODE (PATTERN (insn)) == SET)
11159 {
11160 rtx src, dest;
3b14a2e6 11161
73df8a45 11162 /* Handle normal compare instructions. */
11163 src = SET_SRC (PATTERN (insn));
11164 dest = SET_DEST (PATTERN (insn));
512d9edf 11165
73df8a45 11166 if (!REG_P (dest)
11167 || !CC_REGNO_P (REGNO (dest))
11168 || GET_CODE (src) != COMPARE)
11169 return false;
512d9edf 11170
73df8a45 11171 /* s390_swap_cmp will try to find the conditional
11172 jump when passing NULL_RTX as condition. */
11173 cond = NULL_RTX;
11174 op0 = &XEXP (src, 0);
11175 op1 = &XEXP (src, 1);
11176 }
11177 else
11178 return false;
512d9edf 11179
73df8a45 11180 if (!REG_P (*op0) || !REG_P (*op1))
11181 return false;
512d9edf 11182
cc6056e1 11183 if (GET_MODE_CLASS (GET_MODE (*op0)) != MODE_INT)
11184 return false;
11185
73df8a45 11186 /* Swap the COMPARE arguments and its mask if there is a
11187 conflicting access in the previous insn. */
bc1c8bc5 11188 prev_insn = prev_active_insn (insn);
73df8a45 11189 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
11190 && reg_referenced_p (*op1, PATTERN (prev_insn)))
11191 s390_swap_cmp (cond, op0, op1, insn);
11192
11193 /* Check if there is a conflict with the next insn. If there
11194 was no conflict with the previous insn, then swap the
11195 COMPARE arguments and its mask. If we already swapped
11196 the operands, or if swapping them would cause a conflict
11197 with the previous insn, issue a NOP after the COMPARE in
11198 order to separate the two instuctions. */
bc1c8bc5 11199 next_insn = next_active_insn (insn);
73df8a45 11200 if (next_insn != NULL_RTX && INSN_P (next_insn)
11201 && s390_non_addr_reg_read_p (*op1, next_insn))
11202 {
512d9edf 11203 if (prev_insn != NULL_RTX && INSN_P (prev_insn)
73df8a45 11204 && s390_non_addr_reg_read_p (*op0, prev_insn))
512d9edf 11205 {
73df8a45 11206 if (REGNO (*op1) == 0)
11207 emit_insn_after (gen_nop1 (), insn);
512d9edf 11208 else
73df8a45 11209 emit_insn_after (gen_nop (), insn);
11210 insn_added_p = true;
3b14a2e6 11211 }
73df8a45 11212 else
11213 s390_swap_cmp (cond, op0, op1, insn);
3b14a2e6 11214 }
73df8a45 11215 return insn_added_p;
3b14a2e6 11216}
11217
875862bf 11218/* Perform machine-dependent processing. */
7346ca58 11219
875862bf 11220static void
11221s390_reorg (void)
7346ca58 11222{
875862bf 11223 bool pool_overflow = false;
7346ca58 11224
875862bf 11225 /* Make sure all splits have been performed; splits after
11226 machine_dependent_reorg might confuse insn length counts. */
11227 split_all_insns_noflow ();
f588eb9f 11228
875862bf 11229 /* Install the main literal pool and the associated base
11230 register load insns.
f588eb9f 11231
875862bf 11232 In addition, there are two problematic situations we need
11233 to correct:
7346ca58 11234
875862bf 11235 - the literal pool might be > 4096 bytes in size, so that
11236 some of its elements cannot be directly accessed
7346ca58 11237
875862bf 11238 - a branch target might be > 64K away from the branch, so that
11239 it is not possible to use a PC-relative instruction.
7346ca58 11240
875862bf 11241 To fix those, we split the single literal pool into multiple
11242 pool chunks, reloading the pool base register at various
11243 points throughout the function to ensure it always points to
11244 the pool chunk the following code expects, and / or replace
11245 PC-relative branches by absolute branches.
7346ca58 11246
875862bf 11247 However, the two problems are interdependent: splitting the
11248 literal pool can move a branch further away from its target,
11249 causing the 64K limit to overflow, and on the other hand,
11250 replacing a PC-relative branch by an absolute branch means
11251 we need to put the branch target address into the literal
11252 pool, possibly causing it to overflow.
44a61e21 11253
875862bf 11254 So, we loop trying to fix up both problems until we manage
11255 to satisfy both conditions at the same time. Note that the
11256 loop is guaranteed to terminate as every pass of the loop
11257 strictly decreases the total number of PC-relative branches
11258 in the function. (This is not completely true as there
11259 might be branch-over-pool insns introduced by chunkify_start.
11260 Those never need to be split however.) */
44a61e21 11261
875862bf 11262 for (;;)
11263 {
11264 struct constant_pool *pool = NULL;
80aaaa56 11265
875862bf 11266 /* Collect the literal pool. */
11267 if (!pool_overflow)
11268 {
11269 pool = s390_mainpool_start ();
11270 if (!pool)
11271 pool_overflow = true;
11272 }
80aaaa56 11273
875862bf 11274 /* If literal pool overflowed, start to chunkify it. */
11275 if (pool_overflow)
11276 pool = s390_chunkify_start ();
80aaaa56 11277
875862bf 11278 /* Split out-of-range branches. If this has created new
11279 literal pool entries, cancel current chunk list and
11280 recompute it. zSeries machines have large branch
11281 instructions, so we never need to split a branch. */
11282 if (!TARGET_CPU_ZARCH && s390_split_branches ())
11283 {
11284 if (pool_overflow)
11285 s390_chunkify_cancel (pool);
11286 else
11287 s390_mainpool_cancel (pool);
80aaaa56 11288
875862bf 11289 continue;
11290 }
11291
11292 /* If we made it up to here, both conditions are satisfied.
11293 Finish up literal pool related changes. */
11294 if (pool_overflow)
11295 s390_chunkify_finish (pool);
11296 else
11297 s390_mainpool_finish (pool);
11298
11299 /* We're done splitting branches. */
11300 cfun->machine->split_branches_pending_p = false;
11301 break;
80aaaa56 11302 }
80aaaa56 11303
babfdedf 11304 /* Generate out-of-pool execute target insns. */
11305 if (TARGET_CPU_ZARCH)
11306 {
11307 rtx insn, label, target;
11308
11309 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11310 {
11311 label = s390_execute_label (insn);
11312 if (!label)
11313 continue;
11314
11315 gcc_assert (label != const0_rtx);
11316
11317 target = emit_label (XEXP (label, 0));
11318 INSN_ADDRESSES_NEW (target, -1);
11319
11320 target = emit_insn (s390_execute_target (insn));
11321 INSN_ADDRESSES_NEW (target, -1);
11322 }
11323 }
11324
11325 /* Try to optimize prologue and epilogue further. */
875862bf 11326 s390_optimize_prologue ();
3b14a2e6 11327
33d033da 11328 /* Walk over the insns and do some >=z10 specific changes. */
11329 if (s390_tune == PROCESSOR_2097_Z10
81769881 11330 || s390_tune == PROCESSOR_2817_Z196
11331 || s390_tune == PROCESSOR_2827_ZEC12)
73df8a45 11332 {
11333 rtx insn;
11334 bool insn_added_p = false;
11335
11336 /* The insn lengths and addresses have to be up to date for the
11337 following manipulations. */
11338 shorten_branches (get_insns ());
11339
11340 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
11341 {
11342 if (!INSN_P (insn) || INSN_CODE (insn) <= 0)
11343 continue;
11344
11345 if (JUMP_P (insn))
33d033da 11346 insn_added_p |= s390_fix_long_loop_prediction (insn);
73df8a45 11347
33d033da 11348 if ((GET_CODE (PATTERN (insn)) == PARALLEL
11349 || GET_CODE (PATTERN (insn)) == SET)
11350 && s390_tune == PROCESSOR_2097_Z10)
73df8a45 11351 insn_added_p |= s390_z10_optimize_cmp (insn);
11352 }
11353
11354 /* Adjust branches if we added new instructions. */
11355 if (insn_added_p)
11356 shorten_branches (get_insns ());
11357 }
875862bf 11358}
7346ca58 11359
8a2a84e3 11360/* Return true if INSN is a fp load insn writing register REGNO. */
11361static inline bool
11362s390_fpload_toreg (rtx insn, unsigned int regno)
11363{
11364 rtx set;
11365 enum attr_type flag = s390_safe_attr_type (insn);
11366
11367 if (flag != TYPE_FLOADSF && flag != TYPE_FLOADDF)
11368 return false;
11369
11370 set = single_set (insn);
11371
11372 if (set == NULL_RTX)
11373 return false;
11374
11375 if (!REG_P (SET_DEST (set)) || !MEM_P (SET_SRC (set)))
11376 return false;
11377
11378 if (REGNO (SET_DEST (set)) != regno)
11379 return false;
11380
11381 return true;
11382}
11383
11384/* This value describes the distance to be avoided between an
11385 aritmetic fp instruction and an fp load writing the same register.
11386 Z10_EARLYLOAD_DISTANCE - 1 as well as Z10_EARLYLOAD_DISTANCE + 1 is
11387 fine but the exact value has to be avoided. Otherwise the FP
11388 pipeline will throw an exception causing a major penalty. */
11389#define Z10_EARLYLOAD_DISTANCE 7
11390
11391/* Rearrange the ready list in order to avoid the situation described
11392 for Z10_EARLYLOAD_DISTANCE. A problematic load instruction is
11393 moved to the very end of the ready list. */
11394static void
11395s390_z10_prevent_earlyload_conflicts (rtx *ready, int *nready_p)
11396{
11397 unsigned int regno;
11398 int nready = *nready_p;
11399 rtx tmp;
11400 int i;
11401 rtx insn;
11402 rtx set;
11403 enum attr_type flag;
11404 int distance;
11405
11406 /* Skip DISTANCE - 1 active insns. */
11407 for (insn = last_scheduled_insn, distance = Z10_EARLYLOAD_DISTANCE - 1;
11408 distance > 0 && insn != NULL_RTX;
11409 distance--, insn = prev_active_insn (insn))
11410 if (CALL_P (insn) || JUMP_P (insn))
11411 return;
11412
11413 if (insn == NULL_RTX)
11414 return;
11415
11416 set = single_set (insn);
11417
11418 if (set == NULL_RTX || !REG_P (SET_DEST (set))
11419 || GET_MODE_CLASS (GET_MODE (SET_DEST (set))) != MODE_FLOAT)
11420 return;
11421
11422 flag = s390_safe_attr_type (insn);
11423
11424 if (flag == TYPE_FLOADSF || flag == TYPE_FLOADDF)
11425 return;
11426
11427 regno = REGNO (SET_DEST (set));
11428 i = nready - 1;
11429
11430 while (!s390_fpload_toreg (ready[i], regno) && i > 0)
11431 i--;
11432
11433 if (!i)
11434 return;
11435
11436 tmp = ready[i];
11437 memmove (&ready[1], &ready[0], sizeof (rtx) * i);
11438 ready[0] = tmp;
11439}
11440
81769881 11441
11442/* The s390_sched_state variable tracks the state of the current or
11443 the last instruction group.
11444
11445 0,1,2 number of instructions scheduled in the current group
11446 3 the last group is complete - normal insns
11447 4 the last group was a cracked/expanded insn */
11448
11449static int s390_sched_state;
11450
11451#define S390_OOO_SCHED_STATE_NORMAL 3
11452#define S390_OOO_SCHED_STATE_CRACKED 4
11453
11454#define S390_OOO_SCHED_ATTR_MASK_CRACKED 0x1
11455#define S390_OOO_SCHED_ATTR_MASK_EXPANDED 0x2
11456#define S390_OOO_SCHED_ATTR_MASK_ENDGROUP 0x4
11457#define S390_OOO_SCHED_ATTR_MASK_GROUPALONE 0x8
11458
11459static unsigned int
11460s390_get_sched_attrmask (rtx insn)
11461{
11462 unsigned int mask = 0;
11463
11464 if (get_attr_ooo_cracked (insn))
11465 mask |= S390_OOO_SCHED_ATTR_MASK_CRACKED;
11466 if (get_attr_ooo_expanded (insn))
11467 mask |= S390_OOO_SCHED_ATTR_MASK_EXPANDED;
11468 if (get_attr_ooo_endgroup (insn))
11469 mask |= S390_OOO_SCHED_ATTR_MASK_ENDGROUP;
11470 if (get_attr_ooo_groupalone (insn))
11471 mask |= S390_OOO_SCHED_ATTR_MASK_GROUPALONE;
11472 return mask;
11473}
11474
11475/* Return the scheduling score for INSN. The higher the score the
11476 better. The score is calculated from the OOO scheduling attributes
11477 of INSN and the scheduling state s390_sched_state. */
11478static int
11479s390_sched_score (rtx insn)
11480{
11481 unsigned int mask = s390_get_sched_attrmask (insn);
11482 int score = 0;
11483
11484 switch (s390_sched_state)
11485 {
11486 case 0:
11487 /* Try to put insns into the first slot which would otherwise
11488 break a group. */
11489 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11490 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11491 score += 5;
11492 if ((mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11493 score += 10;
11494 case 1:
11495 /* Prefer not cracked insns while trying to put together a
11496 group. */
11497 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11498 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0
11499 && (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) == 0)
11500 score += 10;
11501 if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) == 0)
11502 score += 5;
11503 break;
11504 case 2:
11505 /* Prefer not cracked insns while trying to put together a
11506 group. */
11507 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11508 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0
11509 && (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) == 0)
11510 score += 10;
11511 /* Prefer endgroup insns in the last slot. */
11512 if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) != 0)
11513 score += 10;
11514 break;
11515 case S390_OOO_SCHED_STATE_NORMAL:
11516 /* Prefer not cracked insns if the last was not cracked. */
11517 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) == 0
11518 && (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) == 0)
11519 score += 5;
11520 if ((mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11521 score += 10;
11522 break;
11523 case S390_OOO_SCHED_STATE_CRACKED:
11524 /* Try to keep cracked insns together to prevent them from
11525 interrupting groups. */
11526 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11527 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11528 score += 5;
11529 break;
11530 }
11531 return score;
11532}
11533
8a2a84e3 11534/* This function is called via hook TARGET_SCHED_REORDER before
4246a5c7 11535 issuing one insn from list READY which contains *NREADYP entries.
8a2a84e3 11536 For target z10 it reorders load instructions to avoid early load
11537 conflicts in the floating point pipeline */
11538static int
81769881 11539s390_sched_reorder (FILE *file, int verbose,
8a2a84e3 11540 rtx *ready, int *nreadyp, int clock ATTRIBUTE_UNUSED)
11541{
11542 if (s390_tune == PROCESSOR_2097_Z10)
11543 if (reload_completed && *nreadyp > 1)
11544 s390_z10_prevent_earlyload_conflicts (ready, nreadyp);
11545
81769881 11546 if (s390_tune == PROCESSOR_2827_ZEC12
11547 && reload_completed
11548 && *nreadyp > 1)
11549 {
11550 int i;
11551 int last_index = *nreadyp - 1;
11552 int max_index = -1;
11553 int max_score = -1;
11554 rtx tmp;
11555
11556 /* Just move the insn with the highest score to the top (the
11557 end) of the list. A full sort is not needed since a conflict
11558 in the hazard recognition cannot happen. So the top insn in
11559 the ready list will always be taken. */
11560 for (i = last_index; i >= 0; i--)
11561 {
11562 int score;
11563
11564 if (recog_memoized (ready[i]) < 0)
11565 continue;
11566
11567 score = s390_sched_score (ready[i]);
11568 if (score > max_score)
11569 {
11570 max_score = score;
11571 max_index = i;
11572 }
11573 }
11574
11575 if (max_index != -1)
11576 {
11577 if (max_index != last_index)
11578 {
11579 tmp = ready[max_index];
11580 ready[max_index] = ready[last_index];
11581 ready[last_index] = tmp;
11582
11583 if (verbose > 5)
11584 fprintf (file,
11585 "move insn %d to the top of list\n",
11586 INSN_UID (ready[last_index]));
11587 }
11588 else if (verbose > 5)
11589 fprintf (file,
11590 "best insn %d already on top\n",
11591 INSN_UID (ready[last_index]));
11592 }
11593
11594 if (verbose > 5)
11595 {
11596 fprintf (file, "ready list ooo attributes - sched state: %d\n",
11597 s390_sched_state);
11598
11599 for (i = last_index; i >= 0; i--)
11600 {
11601 if (recog_memoized (ready[i]) < 0)
11602 continue;
11603 fprintf (file, "insn %d score: %d: ", INSN_UID (ready[i]),
11604 s390_sched_score (ready[i]));
11605#define PRINT_OOO_ATTR(ATTR) fprintf (file, "%s ", get_attr_##ATTR (ready[i]) ? #ATTR : "!" #ATTR);
11606 PRINT_OOO_ATTR (ooo_cracked);
11607 PRINT_OOO_ATTR (ooo_expanded);
11608 PRINT_OOO_ATTR (ooo_endgroup);
11609 PRINT_OOO_ATTR (ooo_groupalone);
11610#undef PRINT_OOO_ATTR
11611 fprintf (file, "\n");
11612 }
11613 }
11614 }
11615
8a2a84e3 11616 return s390_issue_rate ();
11617}
11618
81769881 11619
8a2a84e3 11620/* This function is called via hook TARGET_SCHED_VARIABLE_ISSUE after
11621 the scheduler has issued INSN. It stores the last issued insn into
11622 last_scheduled_insn in order to make it available for
11623 s390_sched_reorder. */
11624static int
81769881 11625s390_sched_variable_issue (FILE *file, int verbose, rtx insn, int more)
8a2a84e3 11626{
11627 last_scheduled_insn = insn;
11628
81769881 11629 if (s390_tune == PROCESSOR_2827_ZEC12
11630 && reload_completed
11631 && recog_memoized (insn) >= 0)
11632 {
11633 unsigned int mask = s390_get_sched_attrmask (insn);
11634
11635 if ((mask & S390_OOO_SCHED_ATTR_MASK_CRACKED) != 0
11636 || (mask & S390_OOO_SCHED_ATTR_MASK_EXPANDED) != 0)
11637 s390_sched_state = S390_OOO_SCHED_STATE_CRACKED;
11638 else if ((mask & S390_OOO_SCHED_ATTR_MASK_ENDGROUP) != 0
11639 || (mask & S390_OOO_SCHED_ATTR_MASK_GROUPALONE) != 0)
11640 s390_sched_state = S390_OOO_SCHED_STATE_NORMAL;
11641 else
11642 {
11643 /* Only normal insns are left (mask == 0). */
11644 switch (s390_sched_state)
11645 {
11646 case 0:
11647 case 1:
11648 case 2:
11649 case S390_OOO_SCHED_STATE_NORMAL:
11650 if (s390_sched_state == S390_OOO_SCHED_STATE_NORMAL)
11651 s390_sched_state = 1;
11652 else
11653 s390_sched_state++;
11654
11655 break;
11656 case S390_OOO_SCHED_STATE_CRACKED:
11657 s390_sched_state = S390_OOO_SCHED_STATE_NORMAL;
11658 break;
11659 }
11660 }
11661 if (verbose > 5)
11662 {
11663 fprintf (file, "insn %d: ", INSN_UID (insn));
11664#define PRINT_OOO_ATTR(ATTR) \
11665 fprintf (file, "%s ", get_attr_##ATTR (insn) ? #ATTR : "");
11666 PRINT_OOO_ATTR (ooo_cracked);
11667 PRINT_OOO_ATTR (ooo_expanded);
11668 PRINT_OOO_ATTR (ooo_endgroup);
11669 PRINT_OOO_ATTR (ooo_groupalone);
11670#undef PRINT_OOO_ATTR
11671 fprintf (file, "\n");
11672 fprintf (file, "sched state: %d\n", s390_sched_state);
11673 }
11674 }
11675
8a2a84e3 11676 if (GET_CODE (PATTERN (insn)) != USE
11677 && GET_CODE (PATTERN (insn)) != CLOBBER)
11678 return more - 1;
11679 else
11680 return more;
11681}
7346ca58 11682
494d0169 11683static void
11684s390_sched_init (FILE *file ATTRIBUTE_UNUSED,
11685 int verbose ATTRIBUTE_UNUSED,
11686 int max_ready ATTRIBUTE_UNUSED)
11687{
11688 last_scheduled_insn = NULL_RTX;
81769881 11689 s390_sched_state = 0;
494d0169 11690}
11691
9ccaa774 11692/* This function checks the whole of insn X for memory references. The
11693 function always returns zero because the framework it is called
11694 from would stop recursively analyzing the insn upon a return value
11695 other than zero. The real result of this function is updating
11696 counter variable MEM_COUNT. */
11697static int
11698check_dpu (rtx *x, unsigned *mem_count)
11699{
11700 if (*x != NULL_RTX && MEM_P (*x))
11701 (*mem_count)++;
11702 return 0;
11703}
11704
11705/* This target hook implementation for TARGET_LOOP_UNROLL_ADJUST calculates
33d033da 11706 a new number struct loop *loop should be unrolled if tuned for cpus with
11707 a built-in stride prefetcher.
11708 The loop is analyzed for memory accesses by calling check_dpu for
9ccaa774 11709 each rtx of the loop. Depending on the loop_depth and the amount of
11710 memory accesses a new number <=nunroll is returned to improve the
11711 behaviour of the hardware prefetch unit. */
11712static unsigned
11713s390_loop_unroll_adjust (unsigned nunroll, struct loop *loop)
11714{
11715 basic_block *bbs;
11716 rtx insn;
11717 unsigned i;
11718 unsigned mem_count = 0;
11719
81769881 11720 if (s390_tune != PROCESSOR_2097_Z10
11721 && s390_tune != PROCESSOR_2817_Z196
11722 && s390_tune != PROCESSOR_2827_ZEC12)
9ccaa774 11723 return nunroll;
11724
11725 /* Count the number of memory references within the loop body. */
11726 bbs = get_loop_body (loop);
11727 for (i = 0; i < loop->num_nodes; i++)
11728 {
11729 for (insn = BB_HEAD (bbs[i]); insn != BB_END (bbs[i]); insn = NEXT_INSN (insn))
11730 if (INSN_P (insn) && INSN_CODE (insn) != -1)
11731 for_each_rtx (&insn, (rtx_function) check_dpu, &mem_count);
11732 }
11733 free (bbs);
11734
11735 /* Prevent division by zero, and we do not need to adjust nunroll in this case. */
11736 if (mem_count == 0)
11737 return nunroll;
11738
11739 switch (loop_depth(loop))
11740 {
11741 case 1:
11742 return MIN (nunroll, 28 / mem_count);
11743 case 2:
11744 return MIN (nunroll, 22 / mem_count);
11745 default:
11746 return MIN (nunroll, 16 / mem_count);
11747 }
11748}
11749
875862bf 11750/* Initialize GCC target structure. */
f588eb9f 11751
875862bf 11752#undef TARGET_ASM_ALIGNED_HI_OP
11753#define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
11754#undef TARGET_ASM_ALIGNED_DI_OP
11755#define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
11756#undef TARGET_ASM_INTEGER
11757#define TARGET_ASM_INTEGER s390_assemble_integer
7346ca58 11758
875862bf 11759#undef TARGET_ASM_OPEN_PAREN
11760#define TARGET_ASM_OPEN_PAREN ""
f588eb9f 11761
875862bf 11762#undef TARGET_ASM_CLOSE_PAREN
11763#define TARGET_ASM_CLOSE_PAREN ""
7346ca58 11764
4c834714 11765#undef TARGET_OPTION_OVERRIDE
11766#define TARGET_OPTION_OVERRIDE s390_option_override
11767
875862bf 11768#undef TARGET_ENCODE_SECTION_INFO
11769#define TARGET_ENCODE_SECTION_INFO s390_encode_section_info
7346ca58 11770
b5fdc416 11771#undef TARGET_SCALAR_MODE_SUPPORTED_P
11772#define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
11773
875862bf 11774#ifdef HAVE_AS_TLS
11775#undef TARGET_HAVE_TLS
11776#define TARGET_HAVE_TLS true
11777#endif
11778#undef TARGET_CANNOT_FORCE_CONST_MEM
11779#define TARGET_CANNOT_FORCE_CONST_MEM s390_cannot_force_const_mem
7346ca58 11780
875862bf 11781#undef TARGET_DELEGITIMIZE_ADDRESS
11782#define TARGET_DELEGITIMIZE_ADDRESS s390_delegitimize_address
7346ca58 11783
41e3a0c7 11784#undef TARGET_LEGITIMIZE_ADDRESS
11785#define TARGET_LEGITIMIZE_ADDRESS s390_legitimize_address
11786
875862bf 11787#undef TARGET_RETURN_IN_MEMORY
11788#define TARGET_RETURN_IN_MEMORY s390_return_in_memory
f588eb9f 11789
5ada7a14 11790#undef TARGET_INIT_BUILTINS
11791#define TARGET_INIT_BUILTINS s390_init_builtins
11792#undef TARGET_EXPAND_BUILTIN
11793#define TARGET_EXPAND_BUILTIN s390_expand_builtin
11794
1a561788 11795#undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
11796#define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA s390_output_addr_const_extra
11797
875862bf 11798#undef TARGET_ASM_OUTPUT_MI_THUNK
11799#define TARGET_ASM_OUTPUT_MI_THUNK s390_output_mi_thunk
11800#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
a9f1838b 11801#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
7346ca58 11802
875862bf 11803#undef TARGET_SCHED_ADJUST_PRIORITY
11804#define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority
11805#undef TARGET_SCHED_ISSUE_RATE
11806#define TARGET_SCHED_ISSUE_RATE s390_issue_rate
11807#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
11808#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD s390_first_cycle_multipass_dfa_lookahead
f588eb9f 11809
8a2a84e3 11810#undef TARGET_SCHED_VARIABLE_ISSUE
11811#define TARGET_SCHED_VARIABLE_ISSUE s390_sched_variable_issue
11812#undef TARGET_SCHED_REORDER
11813#define TARGET_SCHED_REORDER s390_sched_reorder
494d0169 11814#undef TARGET_SCHED_INIT
11815#define TARGET_SCHED_INIT s390_sched_init
8a2a84e3 11816
875862bf 11817#undef TARGET_CANNOT_COPY_INSN_P
11818#define TARGET_CANNOT_COPY_INSN_P s390_cannot_copy_insn_p
11819#undef TARGET_RTX_COSTS
11820#define TARGET_RTX_COSTS s390_rtx_costs
11821#undef TARGET_ADDRESS_COST
11822#define TARGET_ADDRESS_COST s390_address_cost
fa7a995b 11823#undef TARGET_REGISTER_MOVE_COST
11824#define TARGET_REGISTER_MOVE_COST s390_register_move_cost
11825#undef TARGET_MEMORY_MOVE_COST
11826#define TARGET_MEMORY_MOVE_COST s390_memory_move_cost
f588eb9f 11827
875862bf 11828#undef TARGET_MACHINE_DEPENDENT_REORG
11829#define TARGET_MACHINE_DEPENDENT_REORG s390_reorg
71597dac 11830
875862bf 11831#undef TARGET_VALID_POINTER_MODE
11832#define TARGET_VALID_POINTER_MODE s390_valid_pointer_mode
f588eb9f 11833
875862bf 11834#undef TARGET_BUILD_BUILTIN_VA_LIST
11835#define TARGET_BUILD_BUILTIN_VA_LIST s390_build_builtin_va_list
8a58ed0a 11836#undef TARGET_EXPAND_BUILTIN_VA_START
11837#define TARGET_EXPAND_BUILTIN_VA_START s390_va_start
875862bf 11838#undef TARGET_GIMPLIFY_VA_ARG_EXPR
11839#define TARGET_GIMPLIFY_VA_ARG_EXPR s390_gimplify_va_arg
b33c41a1 11840
3b2411a8 11841#undef TARGET_PROMOTE_FUNCTION_MODE
11842#define TARGET_PROMOTE_FUNCTION_MODE s390_promote_function_mode
875862bf 11843#undef TARGET_PASS_BY_REFERENCE
11844#define TARGET_PASS_BY_REFERENCE s390_pass_by_reference
b33c41a1 11845
875862bf 11846#undef TARGET_FUNCTION_OK_FOR_SIBCALL
11847#define TARGET_FUNCTION_OK_FOR_SIBCALL s390_function_ok_for_sibcall
12bc26aa 11848#undef TARGET_FUNCTION_ARG
11849#define TARGET_FUNCTION_ARG s390_function_arg
11850#undef TARGET_FUNCTION_ARG_ADVANCE
11851#define TARGET_FUNCTION_ARG_ADVANCE s390_function_arg_advance
dc3b3062 11852#undef TARGET_FUNCTION_VALUE
11853#define TARGET_FUNCTION_VALUE s390_function_value
11854#undef TARGET_LIBCALL_VALUE
11855#define TARGET_LIBCALL_VALUE s390_libcall_value
b33c41a1 11856
875862bf 11857#undef TARGET_FIXED_CONDITION_CODE_REGS
11858#define TARGET_FIXED_CONDITION_CODE_REGS s390_fixed_condition_code_regs
b33c41a1 11859
875862bf 11860#undef TARGET_CC_MODES_COMPATIBLE
11861#define TARGET_CC_MODES_COMPATIBLE s390_cc_modes_compatible
b33c41a1 11862
1606e68a 11863#undef TARGET_INVALID_WITHIN_DOLOOP
a9f1838b 11864#define TARGET_INVALID_WITHIN_DOLOOP hook_constcharptr_const_rtx_null
e75dabf7 11865
40af64cc 11866#ifdef HAVE_AS_TLS
11867#undef TARGET_ASM_OUTPUT_DWARF_DTPREL
11868#define TARGET_ASM_OUTPUT_DWARF_DTPREL s390_output_dwarf_dtprel
11869#endif
11870
4257b08a 11871#ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING
eddcdde1 11872#undef TARGET_MANGLE_TYPE
11873#define TARGET_MANGLE_TYPE s390_mangle_type
4257b08a 11874#endif
11875
36868490 11876#undef TARGET_SCALAR_MODE_SUPPORTED_P
11877#define TARGET_SCALAR_MODE_SUPPORTED_P s390_scalar_mode_supported_p
11878
3359ccfd 11879#undef TARGET_PREFERRED_RELOAD_CLASS
11880#define TARGET_PREFERRED_RELOAD_CLASS s390_preferred_reload_class
11881
328d5423 11882#undef TARGET_SECONDARY_RELOAD
11883#define TARGET_SECONDARY_RELOAD s390_secondary_reload
11884
0ef89dfd 11885#undef TARGET_LIBGCC_CMP_RETURN_MODE
11886#define TARGET_LIBGCC_CMP_RETURN_MODE s390_libgcc_cmp_return_mode
11887
11888#undef TARGET_LIBGCC_SHIFT_COUNT_MODE
11889#define TARGET_LIBGCC_SHIFT_COUNT_MODE s390_libgcc_shift_count_mode
11890
fd50b071 11891#undef TARGET_LEGITIMATE_ADDRESS_P
11892#define TARGET_LEGITIMATE_ADDRESS_P s390_legitimate_address_p
11893
ca316360 11894#undef TARGET_LEGITIMATE_CONSTANT_P
11895#define TARGET_LEGITIMATE_CONSTANT_P s390_legitimate_constant_p
11896
7b1bda1c 11897#undef TARGET_LRA_P
11898#define TARGET_LRA_P s390_lra_p
11899
cd90919d 11900#undef TARGET_CAN_ELIMINATE
11901#define TARGET_CAN_ELIMINATE s390_can_eliminate
11902
b2d7ede1 11903#undef TARGET_CONDITIONAL_REGISTER_USAGE
11904#define TARGET_CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage
11905
9ccaa774 11906#undef TARGET_LOOP_UNROLL_ADJUST
11907#define TARGET_LOOP_UNROLL_ADJUST s390_loop_unroll_adjust
11908
4d946732 11909#undef TARGET_ASM_TRAMPOLINE_TEMPLATE
11910#define TARGET_ASM_TRAMPOLINE_TEMPLATE s390_asm_trampoline_template
11911#undef TARGET_TRAMPOLINE_INIT
11912#define TARGET_TRAMPOLINE_INIT s390_trampoline_init
11913
b5fdc416 11914#undef TARGET_UNWIND_WORD_MODE
11915#define TARGET_UNWIND_WORD_MODE s390_unwind_word_mode
11916
d5065e6e 11917#undef TARGET_CANONICALIZE_COMPARISON
11918#define TARGET_CANONICALIZE_COMPARISON s390_canonicalize_comparison
11919
ff4ce128 11920#undef TARGET_HARD_REGNO_SCRATCH_OK
11921#define TARGET_HARD_REGNO_SCRATCH_OK s390_hard_regno_scratch_ok
11922
875862bf 11923struct gcc_target targetm = TARGET_INITIALIZER;
f588eb9f 11924
5a5e802f 11925#include "gt-s390.h"
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