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9db1d521 | 1 | /* Definitions of target machine for GNU compiler, for IBM S/390 |
2f83c7d6 | 2 | Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, |
81f40b79 | 3 | 2007, 2008, 2009 Free Software Foundation, Inc. |
9db1d521 | 4 | Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
f314b9b1 | 5 | Ulrich Weigand (uweigand@de.ibm.com). |
963fc8d0 | 6 | Andreas Krebbel (Andreas.Krebbel@de.ibm.com) |
9db1d521 | 7 | |
58add37a | 8 | This file is part of GCC. |
9db1d521 | 9 | |
58add37a UW |
10 | GCC is free software; you can redistribute it and/or modify it under |
11 | the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 12 | Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
13 | version. |
14 | ||
15 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
16 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
18 | for more details. | |
9db1d521 HP |
19 | |
20 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
21 | along with GCC; see the file COPYING3. If not see |
22 | <http://www.gnu.org/licenses/>. */ | |
9db1d521 HP |
23 | |
24 | #ifndef _S390_H | |
25 | #define _S390_H | |
26 | ||
c7453384 | 27 | /* Which processor to generate code or schedule for. The cpu attribute |
1fec52be HP |
28 | defines a list that mirrors this list, so changes to s390.md must be |
29 | made at the same time. */ | |
30 | ||
31 | enum processor_type | |
32 | { | |
c7453384 EC |
33 | PROCESSOR_9672_G5, |
34 | PROCESSOR_9672_G6, | |
35 | PROCESSOR_2064_Z900, | |
f13e0d4e | 36 | PROCESSOR_2084_Z990, |
ec24698e | 37 | PROCESSOR_2094_Z9_109, |
93538e8e | 38 | PROCESSOR_2097_Z10, |
1fec52be HP |
39 | PROCESSOR_max |
40 | }; | |
41 | ||
f13e0d4e UW |
42 | /* Optional architectural facilities supported by the processor. */ |
43 | ||
44 | enum processor_flags | |
45 | { | |
46 | PF_IEEE_FLOAT = 1, | |
47 | PF_ZARCH = 2, | |
ec24698e | 48 | PF_LONG_DISPLACEMENT = 4, |
85dae55a | 49 | PF_EXTIMM = 8, |
93538e8e AK |
50 | PF_DFP = 16, |
51 | PF_Z10 = 32 | |
f13e0d4e UW |
52 | }; |
53 | ||
54 | extern enum processor_type s390_tune; | |
81f40b79 | 55 | extern int s390_tune_flags; |
1fec52be | 56 | |
90c6fd8a AK |
57 | /* This is necessary to avoid a warning about comparing different enum |
58 | types. */ | |
59 | #define s390_tune_attr ((enum attr_cpu)s390_tune) | |
60 | ||
1fec52be | 61 | extern enum processor_type s390_arch; |
81f40b79 | 62 | extern int s390_arch_flags; |
d75f90f1 | 63 | |
963fc8d0 AK |
64 | /* These flags indicate that the generated code should run on a cpu |
65 | providing the respective hardware facility regardless of the | |
66 | current cpu mode (ESA or z/Architecture). */ | |
67 | ||
f13e0d4e UW |
68 | #define TARGET_CPU_IEEE_FLOAT \ |
69 | (s390_arch_flags & PF_IEEE_FLOAT) | |
70 | #define TARGET_CPU_ZARCH \ | |
71 | (s390_arch_flags & PF_ZARCH) | |
72 | #define TARGET_CPU_LONG_DISPLACEMENT \ | |
73 | (s390_arch_flags & PF_LONG_DISPLACEMENT) | |
ec24698e UW |
74 | #define TARGET_CPU_EXTIMM \ |
75 | (s390_arch_flags & PF_EXTIMM) | |
85dae55a AK |
76 | #define TARGET_CPU_DFP \ |
77 | (s390_arch_flags & PF_DFP) | |
93538e8e AK |
78 | #define TARGET_CPU_Z10 \ |
79 | (s390_arch_flags & PF_Z10) | |
f13e0d4e | 80 | |
963fc8d0 AK |
81 | /* These flags indicate that the generated code should run on a cpu |
82 | providing the respective hardware facility when run in | |
83 | z/Architecture mode. */ | |
84 | ||
f13e0d4e UW |
85 | #define TARGET_LONG_DISPLACEMENT \ |
86 | (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT) | |
ec24698e UW |
87 | #define TARGET_EXTIMM \ |
88 | (TARGET_ZARCH && TARGET_CPU_EXTIMM) | |
85dae55a | 89 | #define TARGET_DFP \ |
fb068247 | 90 | (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT) |
93538e8e AK |
91 | #define TARGET_Z10 \ |
92 | (TARGET_ZARCH && TARGET_CPU_Z10) | |
42c78618 | 93 | |
862a2d83 | 94 | /* Run-time target specification. */ |
9db1d521 | 95 | |
a771c4b3 UW |
96 | /* Defaults for option flags defined only on some subtargets. */ |
97 | #ifndef TARGET_TPF_PROFILING | |
98 | #define TARGET_TPF_PROFILING 0 | |
99 | #endif | |
100 | ||
4798630c D |
101 | /* This will be overridden by OS headers. */ |
102 | #define TARGET_TPF 0 | |
103 | ||
862a2d83 UW |
104 | /* Target CPU builtins. */ |
105 | #define TARGET_CPU_CPP_BUILTINS() \ | |
106 | do \ | |
107 | { \ | |
108 | builtin_assert ("cpu=s390"); \ | |
109 | builtin_assert ("machine=s390"); \ | |
110 | builtin_define ("__s390__"); \ | |
9602b6a1 AK |
111 | if (TARGET_ZARCH) \ |
112 | builtin_define ("__zarch__"); \ | |
862a2d83 UW |
113 | if (TARGET_64BIT) \ |
114 | builtin_define ("__s390x__"); \ | |
f61a2c7d AK |
115 | if (TARGET_LONG_DOUBLE_128) \ |
116 | builtin_define ("__LONG_DOUBLE_128__"); \ | |
862a2d83 UW |
117 | } \ |
118 | while (0) | |
9db1d521 | 119 | |
58d10f89 | 120 | #ifdef DEFAULT_TARGET_64BIT |
47d94c1a | 121 | #define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP) |
58d10f89 | 122 | #else |
85dae55a | 123 | #define TARGET_DEFAULT 0 |
58d10f89 UW |
124 | #endif |
125 | ||
f13e0d4e UW |
126 | /* Support for configure-time defaults. */ |
127 | #define OPTION_DEFAULT_SPECS \ | |
128 | { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" }, \ | |
129 | { "arch", "%{!march=*:-march=%(VALUE)}" }, \ | |
130 | { "tune", "%{!mtune=*:-mtune=%(VALUE)}" } | |
131 | ||
132 | /* Defaulting rules. */ | |
133 | #ifdef DEFAULT_TARGET_64BIT | |
134 | #define DRIVER_SELF_SPECS \ | |
135 | "%{!m31:%{!m64:-m64}}", \ | |
136 | "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ | |
137 | "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}" | |
138 | #else | |
139 | #define DRIVER_SELF_SPECS \ | |
140 | "%{!m31:%{!m64:-m31}}", \ | |
141 | "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ | |
142 | "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}" | |
143 | #endif | |
144 | ||
862a2d83 UW |
145 | /* Target version string. Overridden by the OS header. */ |
146 | #ifdef DEFAULT_TARGET_64BIT | |
147 | #define TARGET_VERSION fprintf (stderr, " (zSeries)"); | |
148 | #else | |
149 | #define TARGET_VERSION fprintf (stderr, " (S/390)"); | |
150 | #endif | |
9db1d521 | 151 | |
862a2d83 UW |
152 | /* Hooks to override options. */ |
153 | #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) optimization_options(LEVEL, SIZE) | |
4023fb28 UW |
154 | #define OVERRIDE_OPTIONS override_options () |
155 | ||
862a2d83 UW |
156 | /* Frame pointer is not used for debugging. */ |
157 | #define CAN_DEBUG_WITHOUT_FP | |
9db1d521 | 158 | |
638e37c2 | 159 | /* Constants needed to control the TEST DATA CLASS (TDC) instruction. */ |
0387c142 WG |
160 | #define S390_TDC_POSITIVE_ZERO (1 << 11) |
161 | #define S390_TDC_NEGATIVE_ZERO (1 << 10) | |
162 | #define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER (1 << 9) | |
163 | #define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER (1 << 8) | |
164 | #define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER (1 << 7) | |
165 | #define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER (1 << 6) | |
166 | #define S390_TDC_POSITIVE_INFINITY (1 << 5) | |
167 | #define S390_TDC_NEGATIVE_INFINITY (1 << 4) | |
168 | #define S390_TDC_POSITIVE_QUIET_NAN (1 << 3) | |
169 | #define S390_TDC_NEGATIVE_QUIET_NAN (1 << 2) | |
170 | #define S390_TDC_POSITIVE_SIGNALING_NAN (1 << 1) | |
171 | #define S390_TDC_NEGATIVE_SIGNALING_NAN (1 << 0) | |
172 | ||
173 | /* The following values are different for DFP. */ | |
174 | #define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9) | |
175 | #define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8) | |
176 | #define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER (1 << 7) | |
177 | #define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER (1 << 6) | |
178 | ||
f4aa3848 | 179 | /* For signbit, the BFP-DFP-difference makes no difference. */ |
0f67fa83 | 180 | #define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \ |
0387c142 WG |
181 | | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \ |
182 | | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\ | |
0f67fa83 WG |
183 | | S390_TDC_NEGATIVE_INFINITY \ |
184 | | S390_TDC_NEGATIVE_QUIET_NAN \ | |
185 | | S390_TDC_NEGATIVE_SIGNALING_NAN ) | |
186 | ||
638e37c2 WG |
187 | #define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \ |
188 | | S390_TDC_NEGATIVE_INFINITY ) | |
9db1d521 HP |
189 | |
190 | /* Target machine storage layout. */ | |
191 | ||
862a2d83 | 192 | /* Everything is big-endian. */ |
9db1d521 | 193 | #define BITS_BIG_ENDIAN 1 |
9db1d521 | 194 | #define BYTES_BIG_ENDIAN 1 |
9db1d521 HP |
195 | #define WORDS_BIG_ENDIAN 1 |
196 | ||
9602b6a1 AK |
197 | #define STACK_SIZE_MODE (Pmode) |
198 | ||
fe86047c | 199 | #ifndef IN_LIBGCC2 |
9602b6a1 AK |
200 | |
201 | /* Width of a word, in units (bytes). */ | |
202 | #define UNITS_PER_WORD (TARGET_ZARCH ? 8 : 4) | |
203 | ||
204 | /* Width of a pointer. To be used instead of UNITS_PER_WORD in | |
205 | ABI-relevant contexts. This always matches | |
206 | GET_MODE_SIZE (Pmode). */ | |
207 | #define UNITS_PER_LONG (TARGET_64BIT ? 8 : 4) | |
208 | #define MIN_UNITS_PER_WORD 4 | |
209 | #define MAX_BITS_PER_WORD 64 | |
210 | #else | |
211 | ||
212 | /* In libgcc, UNITS_PER_WORD has ABI-relevant effects, e.g. whether | |
213 | the library should export TImode functions or not. Thus, we have | |
214 | to redefine UNITS_PER_WORD depending on __s390x__ for libgcc. */ | |
215 | #ifdef __s390x__ | |
216 | #define UNITS_PER_WORD 8 | |
217 | #else | |
218 | #define UNITS_PER_WORD 4 | |
219 | #endif | |
fe86047c | 220 | #endif |
9602b6a1 AK |
221 | |
222 | /* Width of a pointer, in bits. */ | |
223 | #define POINTER_SIZE (TARGET_64BIT ? 64 : 32) | |
9db1d521 | 224 | |
9db1d521 | 225 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
9db1d521 HP |
226 | #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32) |
227 | ||
228 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
9db1d521 HP |
229 | #define STACK_BOUNDARY 64 |
230 | ||
231 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
9db1d521 HP |
232 | #define FUNCTION_BOUNDARY 32 |
233 | ||
234 | /* There is no point aligning anything to a rounder boundary than this. */ | |
9db1d521 HP |
235 | #define BIGGEST_ALIGNMENT 64 |
236 | ||
237 | /* Alignment of field after `int : 0' in a structure. */ | |
9db1d521 HP |
238 | #define EMPTY_FIELD_BOUNDARY 32 |
239 | ||
f710504c | 240 | /* Alignment on even addresses for LARL instruction. */ |
9db1d521 | 241 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) |
9db1d521 HP |
242 | #define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) |
243 | ||
862a2d83 | 244 | /* Alignment is not required by the hardware. */ |
9db1d521 HP |
245 | #define STRICT_ALIGNMENT 0 |
246 | ||
862a2d83 UW |
247 | /* Mode of stack savearea. |
248 | FUNCTION is VOIDmode because calling convention maintains SP. | |
249 | BLOCK needs Pmode for SP. | |
250 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ | |
251 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
252 | (LEVEL == SAVE_FUNCTION ? VOIDmode \ | |
43ab026f | 253 | : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode) |
862a2d83 | 254 | |
9db1d521 | 255 | |
862a2d83 | 256 | /* Type layout. */ |
9db1d521 | 257 | |
862a2d83 UW |
258 | /* Sizes in bits of the source language data types. */ |
259 | #define SHORT_TYPE_SIZE 16 | |
260 | #define INT_TYPE_SIZE 32 | |
261 | #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) | |
862a2d83 UW |
262 | #define LONG_LONG_TYPE_SIZE 64 |
263 | #define FLOAT_TYPE_SIZE 32 | |
264 | #define DOUBLE_TYPE_SIZE 64 | |
f61a2c7d AK |
265 | #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) |
266 | ||
267 | /* Define this to set long double type size to use in libgcc2.c, which can | |
268 | not depend on target_flags. */ | |
269 | #ifdef __LONG_DOUBLE_128__ | |
270 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 | |
271 | #else | |
272 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 | |
273 | #endif | |
274 | ||
275 | /* Work around target_flags dependency in ada/targtyps.c. */ | |
276 | #define WIDEST_HARDWARE_FP_SIZE 64 | |
862a2d83 UW |
277 | |
278 | /* We use "unsigned char" as default. */ | |
279 | #define DEFAULT_SIGNED_CHAR 0 | |
280 | ||
281 | ||
282 | /* Register usage. */ | |
283 | ||
284 | /* We have 16 general purpose registers (registers 0-15), | |
285 | and 16 floating point registers (registers 16-31). | |
286 | (On non-IEEE machines, we have only 4 fp registers.) | |
c7453384 | 287 | |
862a2d83 UW |
288 | Amongst the general purpose registers, some are used |
289 | for specific purposes: | |
290 | GPR 11: Hard frame pointer (if needed) | |
291 | GPR 12: Global offset table pointer (if needed) | |
292 | GPR 13: Literal pool base register | |
293 | GPR 14: Return address register | |
294 | GPR 15: Stack pointer | |
c7453384 | 295 | |
c5aa1d12 | 296 | Registers 32-35 are 'fake' hard registers that do not |
862a2d83 UW |
297 | correspond to actual hardware: |
298 | Reg 32: Argument pointer | |
299 | Reg 33: Condition code | |
f4aa3848 | 300 | Reg 34: Frame pointer |
c5aa1d12 | 301 | Reg 35: Return address pointer |
862a2d83 | 302 | |
f4aa3848 | 303 | Registers 36 and 37 are mapped to access registers |
c5aa1d12 UW |
304 | 0 and 1, used to implement thread-local storage. */ |
305 | ||
306 | #define FIRST_PSEUDO_REGISTER 38 | |
862a2d83 UW |
307 | |
308 | /* Standard register usage. */ | |
8e509cf9 UW |
309 | #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16) |
310 | #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16) | |
142cd70f | 311 | #define FP_REGNO_P(N) ((N) >= 16 && (N) < 32) |
8e509cf9 | 312 | #define CC_REGNO_P(N) ((N) == 33) |
a38e09bc | 313 | #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34 || (N) == 35) |
c5aa1d12 | 314 | #define ACCESS_REGNO_P(N) ((N) == 36 || (N) == 37) |
8e509cf9 UW |
315 | |
316 | #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) | |
317 | #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X))) | |
318 | #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) | |
319 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) | |
4888ec5d | 320 | #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X))) |
c5aa1d12 | 321 | #define ACCESS_REG_P(X) (REG_P (X) && ACCESS_REGNO_P (REGNO (X))) |
9db1d521 | 322 | |
862a2d83 | 323 | /* Set up fixed registers and calling convention: |
9db1d521 | 324 | |
862a2d83 UW |
325 | GPRs 0-5 are always call-clobbered, |
326 | GPRs 6-15 are always call-saved. | |
327 | GPR 12 is fixed if used as GOT pointer. | |
328 | GPR 13 is always fixed (as literal pool pointer). | |
545d16ff | 329 | GPR 14 is always fixed on S/390 machines (as return address). |
862a2d83 UW |
330 | GPR 15 is always fixed (as stack pointer). |
331 | The 'fake' hard registers are call-clobbered and fixed. | |
c5aa1d12 | 332 | The access registers are call-saved and fixed. |
9db1d521 | 333 | |
862a2d83 UW |
334 | On 31-bit, FPRs 18-19 are call-clobbered; |
335 | on 64-bit, FPRs 24-31 are call-clobbered. | |
336 | The remaining FPRs are call-saved. */ | |
9db1d521 HP |
337 | |
338 | #define FIXED_REGISTERS \ | |
339 | { 0, 0, 0, 0, \ | |
340 | 0, 0, 0, 0, \ | |
341 | 0, 0, 0, 0, \ | |
342 | 0, 1, 1, 1, \ | |
343 | 0, 0, 0, 0, \ | |
344 | 0, 0, 0, 0, \ | |
345 | 0, 0, 0, 0, \ | |
346 | 0, 0, 0, 0, \ | |
c5aa1d12 UW |
347 | 1, 1, 1, 1, \ |
348 | 1, 1 } | |
9db1d521 | 349 | |
9db1d521 HP |
350 | #define CALL_USED_REGISTERS \ |
351 | { 1, 1, 1, 1, \ | |
352 | 1, 1, 0, 0, \ | |
353 | 0, 0, 0, 0, \ | |
354 | 0, 1, 1, 1, \ | |
4023fb28 UW |
355 | 1, 1, 1, 1, \ |
356 | 1, 1, 1, 1, \ | |
357 | 1, 1, 1, 1, \ | |
358 | 1, 1, 1, 1, \ | |
c5aa1d12 UW |
359 | 1, 1, 1, 1, \ |
360 | 1, 1 } | |
4023fb28 | 361 | |
4023fb28 UW |
362 | #define CALL_REALLY_USED_REGISTERS \ |
363 | { 1, 1, 1, 1, \ | |
9db1d521 | 364 | 1, 1, 0, 0, \ |
4023fb28 UW |
365 | 0, 0, 0, 0, \ |
366 | 0, 0, 0, 0, \ | |
9db1d521 HP |
367 | 1, 1, 1, 1, \ |
368 | 1, 1, 1, 1, \ | |
369 | 1, 1, 1, 1, \ | |
4023fb28 | 370 | 1, 1, 1, 1, \ |
c5aa1d12 UW |
371 | 1, 1, 1, 1, \ |
372 | 0, 0 } | |
9db1d521 | 373 | |
38899e29 | 374 | #define CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage () |
9db1d521 | 375 | |
862a2d83 UW |
376 | /* Preferred register allocation order. */ |
377 | #define REG_ALLOC_ORDER \ | |
7633f08e | 378 | { 1, 2, 3, 4, 5, 0, 12, 11, 10, 9, 8, 7, 6, 14, 13, \ |
862a2d83 UW |
379 | 16, 17, 18, 19, 20, 21, 22, 23, \ |
380 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
c5aa1d12 | 381 | 15, 32, 33, 34, 35, 36, 37 } |
9db1d521 | 382 | |
9db1d521 | 383 | |
862a2d83 | 384 | /* Fitting values into registers. */ |
c7453384 | 385 | |
862a2d83 UW |
386 | /* Integer modes <= word size fit into any GPR. |
387 | Integer modes > word size fit into successive GPRs, starting with | |
388 | an even-numbered register. | |
389 | SImode and DImode fit into FPRs as well. | |
c7453384 | 390 | |
862a2d83 UW |
391 | Floating point modes <= word size fit into any FPR or GPR. |
392 | Floating point modes > word size (i.e. DFmode on 32-bit) fit | |
393 | into any FPR, or an even-odd GPR pair. | |
f61a2c7d | 394 | TFmode fits only into an even-odd FPR pair. |
c7453384 | 395 | |
862a2d83 UW |
396 | Complex floating point modes fit either into two FPRs, or into |
397 | successive GPRs (again starting with an even number). | |
f61a2c7d | 398 | TCmode fits only into two successive even-odd FPR pairs. |
c7453384 | 399 | |
862a2d83 | 400 | Condition code modes fit only into the CC register. */ |
9db1d521 | 401 | |
74aa8b4b AK |
402 | /* Because all registers in a class have the same size HARD_REGNO_NREGS |
403 | is equivalent to CLASS_MAX_NREGS. */ | |
9db1d521 | 404 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
74aa8b4b AK |
405 | s390_class_max_nregs (REGNO_REG_CLASS (REGNO), (MODE)) |
406 | ||
407 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
408 | s390_hard_regno_mode_ok ((REGNO), (MODE)) | |
409 | ||
410 | #define HARD_REGNO_RENAME_OK(FROM, TO) \ | |
7633f08e UW |
411 | s390_hard_regno_rename_ok (FROM, TO) |
412 | ||
9db1d521 HP |
413 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
414 | (((MODE1) == SFmode || (MODE1) == DFmode) \ | |
415 | == ((MODE2) == SFmode || (MODE2) == DFmode)) | |
416 | ||
9602b6a1 AK |
417 | /* When generating code that runs in z/Architecture mode, |
418 | but conforms to the 31-bit ABI, GPRs can hold 8 bytes; | |
419 | the ABI guarantees only that the lower 4 bytes are | |
420 | saved across calls, however. */ | |
421 | #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ | |
422 | (!TARGET_64BIT && TARGET_ZARCH \ | |
423 | && GET_MODE_SIZE (MODE) > 4 \ | |
424 | && (((REGNO) >= 6 && (REGNO) <= 15) || (REGNO) == 32)) | |
425 | ||
862a2d83 UW |
426 | /* Maximum number of registers to represent a value of mode MODE |
427 | in a register of class CLASS. */ | |
428 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
74aa8b4b | 429 | s390_class_max_nregs ((CLASS), (MODE)) |
4023fb28 | 430 | |
862a2d83 UW |
431 | /* If a 4-byte value is loaded into a FPR, it is placed into the |
432 | *upper* half of the register, not the lower. Therefore, we | |
c5aa1d12 UW |
433 | cannot use SUBREGs to switch between modes in FP registers. |
434 | Likewise for access registers, since they have only half the | |
435 | word size on 64-bit. */ | |
f61a2c7d AK |
436 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ |
437 | (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ | |
438 | ? ((reg_classes_intersect_p (FP_REGS, CLASS) \ | |
439 | && (GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8)) \ | |
440 | || reg_classes_intersect_p (ACCESS_REGS, CLASS)) : 0) | |
9db1d521 | 441 | |
862a2d83 | 442 | /* Register classes. */ |
c7453384 | 443 | |
862a2d83 UW |
444 | /* We use the following register classes: |
445 | GENERAL_REGS All general purpose registers | |
446 | ADDR_REGS All general purpose registers except %r0 | |
447 | (These registers can be used in address generation) | |
448 | FP_REGS All floating point registers | |
c5aa1d12 UW |
449 | CC_REGS The condition code register |
450 | ACCESS_REGS The access registers | |
c7453384 | 451 | |
862a2d83 UW |
452 | GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS |
453 | ADDR_FP_REGS Union of ADDR_REGS and FP_REGS | |
c5aa1d12 UW |
454 | GENERAL_CC_REGS Union of GENERAL_REGS and CC_REGS |
455 | ADDR_CC_REGS Union of ADDR_REGS and CC_REGS | |
c7453384 | 456 | |
862a2d83 UW |
457 | NO_REGS No registers |
458 | ALL_REGS All registers | |
c7453384 | 459 | |
862a2d83 | 460 | Note that the 'fake' frame pointer and argument pointer registers |
c5aa1d12 | 461 | are included amongst the address registers here. */ |
9db1d521 HP |
462 | |
463 | enum reg_class | |
464 | { | |
c5aa1d12 | 465 | NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS, |
f4aa3848 | 466 | ADDR_CC_REGS, GENERAL_CC_REGS, |
4023fb28 UW |
467 | FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, |
468 | ALL_REGS, LIM_REG_CLASSES | |
9db1d521 | 469 | }; |
9db1d521 HP |
470 | #define N_REG_CLASSES (int) LIM_REG_CLASSES |
471 | ||
c5aa1d12 UW |
472 | #define REG_CLASS_NAMES \ |
473 | { "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS", \ | |
474 | "ADDR_CC_REGS", "GENERAL_CC_REGS", \ | |
475 | "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" } | |
9db1d521 | 476 | |
862a2d83 | 477 | /* Class -> register mapping. */ |
9db1d521 HP |
478 | #define REG_CLASS_CONTENTS \ |
479 | { \ | |
480 | { 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
9dc62c00 | 481 | { 0x00000000, 0x00000002 }, /* CC_REGS */ \ |
a38e09bc AK |
482 | { 0x0000fffe, 0x0000000d }, /* ADDR_REGS */ \ |
483 | { 0x0000ffff, 0x0000000d }, /* GENERAL_REGS */ \ | |
c5aa1d12 | 484 | { 0x00000000, 0x00000030 }, /* ACCESS_REGS */ \ |
9dc62c00 AK |
485 | { 0x0000fffe, 0x0000000f }, /* ADDR_CC_REGS */ \ |
486 | { 0x0000ffff, 0x0000000f }, /* GENERAL_CC_REGS */ \ | |
9db1d521 | 487 | { 0xffff0000, 0x00000000 }, /* FP_REGS */ \ |
a38e09bc AK |
488 | { 0xfffffffe, 0x0000000d }, /* ADDR_FP_REGS */ \ |
489 | { 0xffffffff, 0x0000000d }, /* GENERAL_FP_REGS */ \ | |
c5aa1d12 | 490 | { 0xffffffff, 0x0000003f }, /* ALL_REGS */ \ |
9db1d521 HP |
491 | } |
492 | ||
058e97ec VM |
493 | /* The following macro defines cover classes for Integrated Register |
494 | Allocator. Cover classes is a set of non-intersected register | |
495 | classes covering all hard registers used for register allocation | |
496 | purpose. Any move between two registers of a cover class should be | |
497 | cheaper than load or store of the registers. The macro value is | |
498 | array of register classes with LIM_REG_CLASSES used as the end | |
499 | marker. */ | |
500 | ||
501 | #define IRA_COVER_CLASSES \ | |
502 | { \ | |
503 | GENERAL_REGS, FP_REGS, CC_REGS, ACCESS_REGS, LIM_REG_CLASSES \ | |
504 | } | |
505 | ||
506 | /* In some case register allocation order is not enough for IRA to | |
507 | generate a good code. The following macro (if defined) increases | |
508 | cost of REGNO for a pseudo approximately by pseudo usage frequency | |
509 | multiplied by the macro value. | |
510 | ||
511 | We avoid usage of BASE_REGNUM by nonzero macro value because the | |
512 | reload can decide not to use the hard register because some | |
513 | constant was forced to be in memory. */ | |
514 | #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) \ | |
515 | (regno == BASE_REGNUM ? 0.0 : 0.5) | |
516 | ||
862a2d83 UW |
517 | /* Register -> class mapping. */ |
518 | extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; | |
519 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) | |
9db1d521 | 520 | |
862a2d83 UW |
521 | /* ADDR_REGS can be used as base or index register. */ |
522 | #define INDEX_REG_CLASS ADDR_REGS | |
523 | #define BASE_REG_CLASS ADDR_REGS | |
9db1d521 | 524 | |
862a2d83 UW |
525 | /* Check whether REGNO is a hard register of the suitable class |
526 | or a pseudo register currently allocated to one such. */ | |
527 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
528 | (((REGNO) < FIRST_PSEUDO_REGISTER \ | |
93fa8428 AK |
529 | && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \ |
530 | || ADDR_REGNO_P (reg_renumber[REGNO])) | |
862a2d83 | 531 | #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) |
9db1d521 | 532 | |
9db1d521 | 533 | |
862a2d83 UW |
534 | /* Given an rtx X being reloaded into a reg required to be in class CLASS, |
535 | return the class of reg to actually use. */ | |
536 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
537 | s390_preferred_reload_class ((X), (CLASS)) | |
9db1d521 | 538 | |
963fc8d0 AK |
539 | /* We need secondary memory to move data between GPRs and FPRs. With |
540 | DFP the ldgr lgdr instructions are available. But these | |
541 | instructions do not handle GPR pairs so it is not possible for 31 | |
542 | bit. */ | |
862a2d83 | 543 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ |
85dae55a AK |
544 | ((CLASS1) != (CLASS2) \ |
545 | && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS) \ | |
963fc8d0 | 546 | && (!TARGET_DFP || !TARGET_64BIT || GET_MODE_SIZE (MODE) != 8)) |
862a2d83 UW |
547 | |
548 | /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit | |
549 | because the movsi and movsf patterns don't handle r/f moves. */ | |
550 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
551 | (GET_MODE_BITSIZE (MODE) < 32 \ | |
552 | ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
553 | : MODE) | |
554 | ||
555 | ||
862a2d83 | 556 | /* Stack layout and calling conventions. */ |
c7453384 | 557 | |
862a2d83 UW |
558 | /* Our stack grows from higher to lower addresses. However, local variables |
559 | are accessed by positive offsets, and function arguments are stored at | |
560 | increasing addresses. */ | |
561 | #define STACK_GROWS_DOWNWARD | |
63296cb1 | 562 | #define FRAME_GROWS_DOWNWARD 1 |
862a2d83 | 563 | /* #undef ARGS_GROW_DOWNWARD */ |
9db1d521 | 564 | |
862a2d83 UW |
565 | /* The basic stack layout looks like this: the stack pointer points |
566 | to the register save area for called functions. Above that area | |
567 | is the location to place outgoing arguments. Above those follow | |
568 | dynamic allocations (alloca), and finally the local variables. */ | |
9db1d521 | 569 | |
862a2d83 UW |
570 | /* Offset from stack-pointer to first location of outgoing args. */ |
571 | #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96) | |
9db1d521 | 572 | |
862a2d83 | 573 | /* Offset within stack frame to start allocating local variables at. */ |
63296cb1 | 574 | #define STARTING_FRAME_OFFSET 0 |
9db1d521 | 575 | |
862a2d83 UW |
576 | /* Offset from the stack pointer register to an item dynamically |
577 | allocated on the stack, e.g., by `alloca'. */ | |
63296cb1 | 578 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ |
38173d38 | 579 | (STACK_POINTER_OFFSET + crtl->outgoing_args_size) |
9db1d521 | 580 | |
862a2d83 UW |
581 | /* Offset of first parameter from the argument pointer register value. |
582 | We have a fake argument pointer register that points directly to | |
583 | the argument area. */ | |
584 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
9db1d521 | 585 | |
f4aa3848 | 586 | /* Defining this macro makes __builtin_frame_address(0) and |
c6d01079 AK |
587 | __builtin_return_address(0) work with -fomit-frame-pointer. */ |
588 | #define INITIAL_FRAME_ADDRESS_RTX \ | |
78791a80 | 589 | (plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET)) |
c6d01079 | 590 | |
c7453384 | 591 | /* The return address of the current frame is retrieved |
4023fb28 UW |
592 | from the initial value of register RETURN_REGNUM. |
593 | For frames farther back, we use the stack slot where | |
594 | the corresponding RETURN_REGNUM register was saved. */ | |
c6d01079 AK |
595 | #define DYNAMIC_CHAIN_ADDRESS(FRAME) \ |
596 | (TARGET_PACKED_STACK ? \ | |
9602b6a1 | 597 | plus_constant ((FRAME), STACK_POINTER_OFFSET - UNITS_PER_LONG) : (FRAME)) |
4023fb28 | 598 | |
78791a80 AK |
599 | /* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of |
600 | builtin_frame_address. Otherwise arg pointer - | |
601 | STACK_POINTER_OFFSET would be returned for | |
602 | __builtin_frame_address(0) what might result in an address pointing | |
603 | somewhere into the middle of the local variables since the packed | |
604 | stack layout generally does not need all the bytes in the register | |
605 | save area. */ | |
606 | #define FRAME_ADDR_RTX(FRAME) \ | |
607 | DYNAMIC_CHAIN_ADDRESS ((FRAME)) | |
608 | ||
c6d01079 | 609 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
5d4d885c | 610 | s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME))) |
9db1d521 | 611 | |
862a2d83 | 612 | /* In 31-bit mode, we need to mask off the high bit of return addresses. */ |
a556fd39 | 613 | #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff)) |
9db1d521 | 614 | |
4023fb28 | 615 | |
862a2d83 | 616 | /* Exception handling. */ |
c7453384 | 617 | |
862a2d83 UW |
618 | /* Describe calling conventions for DWARF-2 exception handling. */ |
619 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM) | |
4023fb28 | 620 | #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET |
9db1d521 HP |
621 | #define DWARF_FRAME_RETURN_COLUMN 14 |
622 | ||
623 | /* Describe how we implement __builtin_eh_return. */ | |
624 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM) | |
a38e09bc | 625 | #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx) |
f4aa3848 | 626 | |
18789f4e UW |
627 | /* Select a format to encode pointers in exception handling data. */ |
628 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
629 | (flag_pic \ | |
630 | ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ | |
631 | : DW_EH_PE_absptr) | |
632 | ||
9602b6a1 AK |
633 | /* Register save slot alignment. */ |
634 | #define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_LONG) | |
635 | ||
9db1d521 | 636 | |
862a2d83 | 637 | /* Frame registers. */ |
9db1d521 | 638 | |
862a2d83 UW |
639 | #define STACK_POINTER_REGNUM 15 |
640 | #define FRAME_POINTER_REGNUM 34 | |
641 | #define HARD_FRAME_POINTER_REGNUM 11 | |
642 | #define ARG_POINTER_REGNUM 32 | |
a38e09bc | 643 | #define RETURN_ADDRESS_POINTER_REGNUM 35 |
9db1d521 | 644 | |
c7453384 EC |
645 | /* The static chain must be call-clobbered, but not used for |
646 | function argument passing. As register 1 is clobbered by | |
862a2d83 UW |
647 | the trampoline code, we only have one option. */ |
648 | #define STATIC_CHAIN_REGNUM 0 | |
9db1d521 | 649 | |
862a2d83 UW |
650 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
651 | To avoid ABI incompatibility, this number must not change even as | |
652 | 'fake' hard registers are added or removed. */ | |
653 | #define DWARF_FRAME_REGISTERS 34 | |
9db1d521 | 654 | |
9db1d521 | 655 | |
862a2d83 | 656 | /* Frame pointer and argument pointer elimination. */ |
9db1d521 | 657 | |
7633f08e UW |
658 | #define ELIMINABLE_REGS \ |
659 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
660 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
661 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
662 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
663 | { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
664 | { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
665 | { BASE_REGNUM, BASE_REGNUM }} | |
9db1d521 | 666 | |
91086990 UW |
667 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
668 | (OFFSET) = s390_initial_elimination_offset ((FROM), (TO)) | |
9db1d521 | 669 | |
9db1d521 | 670 | |
862a2d83 | 671 | /* Stack arguments. */ |
c7453384 | 672 | |
862a2d83 UW |
673 | /* We need current_function_outgoing_args to be valid. */ |
674 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
9db1d521 | 675 | |
862a2d83 UW |
676 | /* Return doesn't modify the stack. */ |
677 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 | |
9db1d521 | 678 | |
9db1d521 | 679 | |
862a2d83 | 680 | /* Register arguments. */ |
c7453384 | 681 | |
9db1d521 HP |
682 | typedef struct s390_arg_structure |
683 | { | |
684 | int gprs; /* gpr so far */ | |
685 | int fprs; /* fpr so far */ | |
686 | } | |
687 | CUMULATIVE_ARGS; | |
688 | ||
07711f53 | 689 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \ |
9db1d521 HP |
690 | ((CUM).gprs=0, (CUM).fprs=0) |
691 | ||
9db1d521 | 692 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
994fe660 | 693 | s390_function_arg_advance (&CUM, MODE, TYPE, NAMED) |
9db1d521 | 694 | |
9db1d521 | 695 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
994fe660 | 696 | s390_function_arg (&CUM, MODE, TYPE, NAMED) |
9db1d521 | 697 | |
96e2afa8 AK |
698 | /* Arguments can be placed in general registers 2 to 6, or in floating |
699 | point registers 0 and 2 for 31 bit and fprs 0, 2, 4 and 6 for 64 | |
700 | bit. */ | |
862a2d83 | 701 | #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \ |
96e2afa8 | 702 | (N) == 16 || (N) == 17 || (TARGET_64BIT && ((N) == 18 || (N) == 19))) |
9db1d521 | 703 | |
9db1d521 | 704 | |
862a2d83 | 705 | /* Scalar return values. */ |
c7453384 | 706 | |
8c17530e | 707 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
cde0f3fd | 708 | s390_function_value ((VALTYPE), (FUNC), VOIDmode) |
8c17530e UW |
709 | |
710 | #define LIBCALL_VALUE(MODE) \ | |
cde0f3fd | 711 | s390_function_value (NULL, NULL, (MODE)) |
9db1d521 | 712 | |
862a2d83 | 713 | /* Only gpr 2 and fpr 0 are ever used as return registers. */ |
9db1d521 HP |
714 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16) |
715 | ||
9db1d521 | 716 | |
862a2d83 | 717 | /* Function entry and exit. */ |
c7453384 | 718 | |
862a2d83 UW |
719 | /* When returning from a function, the stack pointer does not matter. */ |
720 | #define EXIT_IGNORE_STACK 1 | |
9db1d521 | 721 | |
9db1d521 | 722 | |
862a2d83 | 723 | /* Profiling. */ |
9db1d521 HP |
724 | |
725 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
862a2d83 | 726 | s390_function_profiler ((FILE), ((LABELNO))) |
9db1d521 | 727 | |
c52a375d | 728 | #define PROFILE_BEFORE_PROLOGUE 1 |
9db1d521 | 729 | |
9db1d521 | 730 | |
862a2d83 | 731 | /* Trampolines for nested functions. */ |
9db1d521 | 732 | |
b81ecf6f RH |
733 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 32 : 16) |
734 | #define TRAMPOLINE_ALIGNMENT BITS_PER_WORD | |
9db1d521 | 735 | |
862a2d83 | 736 | /* Addressing modes, and classification of registers for them. */ |
9db1d521 | 737 | |
862a2d83 UW |
738 | /* Recognize any constant value that is a valid address. */ |
739 | #define CONSTANT_ADDRESS_P(X) 0 | |
9db1d521 | 740 | |
862a2d83 UW |
741 | /* Maximum number of registers that can appear in a valid memory address. */ |
742 | #define MAX_REGS_PER_ADDRESS 2 | |
9db1d521 | 743 | |
963fc8d0 | 744 | /* This definition replaces the formerly used 'm' constraint with a |
c6c3dba9 PB |
745 | different constraint letter in order to avoid changing semantics of |
746 | the 'm' constraint when accepting new address formats in | |
747 | TARGET_LEGITIMATE_ADDRESS_P. The constraint letter defined here | |
748 | must not be used in insn definitions or inline assemblies. */ | |
963fc8d0 AK |
749 | #define TARGET_MEM_CONSTRAINT 'e' |
750 | ||
0b540f12 UW |
751 | /* Try a machine-dependent way of reloading an illegitimate address |
752 | operand. If we find one, push the reload and jump to WIN. This | |
753 | macro is used in only one place: `find_reloads_address' in reload.c. */ | |
754 | #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ | |
755 | do { \ | |
0a2aaacc KG |
756 | rtx new_rtx = legitimize_reload_address (AD, MODE, OPNUM, (int)(TYPE)); \ |
757 | if (new_rtx) \ | |
0b540f12 | 758 | { \ |
0a2aaacc | 759 | (AD) = new_rtx; \ |
0b540f12 UW |
760 | goto WIN; \ |
761 | } \ | |
762 | } while (0) | |
763 | ||
862a2d83 UW |
764 | /* Nonzero if the constant value X is a legitimate general operand. |
765 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
766 | #define LEGITIMATE_CONSTANT_P(X) \ | |
767 | legitimate_constant_p (X) | |
9db1d521 | 768 | |
862a2d83 UW |
769 | /* Helper macro for s390.c and s390.md to check for symbolic constants. */ |
770 | #define SYMBOLIC_CONST(X) \ | |
771 | (GET_CODE (X) == SYMBOL_REF \ | |
772 | || GET_CODE (X) == LABEL_REF \ | |
773 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
9db1d521 | 774 | |
fd3cd001 UW |
775 | #define TLS_SYMBOLIC_CONST(X) \ |
776 | ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \ | |
777 | || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X))) | |
778 | ||
9db1d521 | 779 | |
862a2d83 | 780 | /* Condition codes. */ |
9db1d521 | 781 | |
862a2d83 UW |
782 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
783 | return the mode to be used for the comparison. */ | |
784 | #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y)) | |
c7453384 | 785 | |
68f9c5e2 UW |
786 | /* Canonicalize a comparison from one we don't have to one we do have. */ |
787 | #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ | |
788 | s390_canonicalize_comparison (&(CODE), &(OP0), &(OP1)) | |
789 | ||
862a2d83 | 790 | /* Relative costs of operations. */ |
9db1d521 | 791 | |
9db1d521 | 792 | /* On s390, copy between fprs and gprs is expensive. */ |
9db1d521 | 793 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
14b3e8ef UW |
794 | (( ( reg_classes_intersect_p ((CLASS1), GENERAL_REGS) \ |
795 | && reg_classes_intersect_p ((CLASS2), FP_REGS)) \ | |
796 | || ( reg_classes_intersect_p ((CLASS1), FP_REGS) \ | |
797 | && reg_classes_intersect_p ((CLASS2), GENERAL_REGS))) ? 10 : 1) | |
9db1d521 | 798 | |
9db1d521 HP |
799 | /* A C expression for the cost of moving data of mode M between a |
800 | register and memory. A value of 2 is the default; this cost is | |
862a2d83 | 801 | relative to those in `REGISTER_MOVE_COST'. */ |
9db1d521 HP |
802 | #define MEMORY_MOVE_COST(M, C, I) 1 |
803 | ||
804 | /* A C expression for the cost of a branch instruction. A value of 1 | |
805 | is the default; other values are interpreted relative to that. */ | |
3a4fd356 | 806 | #define BRANCH_COST(speed_p, predictable_p) 1 |
9db1d521 | 807 | |
862a2d83 UW |
808 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
809 | #define SLOW_BYTE_ACCESS 1 | |
810 | ||
c5443745 | 811 | /* An integer expression for the size in bits of the largest integer machine |
f4aa3848 | 812 | mode that should actually be used. We allow pairs of registers. */ |
c5443745 UW |
813 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) |
814 | ||
862a2d83 | 815 | /* The maximum number of bytes that a single instruction can move quickly |
ff482c8d | 816 | between memory and registers or between two memory locations. */ |
9602b6a1 AK |
817 | #define MOVE_MAX (TARGET_ZARCH ? 16 : 8) |
818 | #define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4) | |
862a2d83 | 819 | #define MAX_MOVE_MAX 16 |
9db1d521 | 820 | |
862a2d83 UW |
821 | /* Determine whether to use move_by_pieces or block move insn. */ |
822 | #define MOVE_BY_PIECES_P(SIZE, ALIGN) \ | |
823 | ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ | |
9602b6a1 | 824 | || (TARGET_ZARCH && (SIZE) == 8) ) |
862a2d83 UW |
825 | |
826 | /* Determine whether to use clear_by_pieces or block clear insn. */ | |
827 | #define CLEAR_BY_PIECES_P(SIZE, ALIGN) \ | |
828 | ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ | |
9602b6a1 | 829 | || (TARGET_ZARCH && (SIZE) == 8) ) |
862a2d83 | 830 | |
45d78e7f | 831 | /* This macro is used to determine whether store_by_pieces should be |
cfa31150 | 832 | called to "memcpy" storage when the source is a constant string. */ |
45d78e7f JJ |
833 | #define STORE_BY_PIECES_P(SIZE, ALIGN) MOVE_BY_PIECES_P (SIZE, ALIGN) |
834 | ||
cfa31150 SL |
835 | /* Likewise to decide whether to "memset" storage with byte values |
836 | other than zero. */ | |
837 | #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P (SIZE, ALIGN) | |
838 | ||
862a2d83 UW |
839 | /* Don't perform CSE on function addresses. */ |
840 | #define NO_FUNCTION_CSE | |
841 | ||
5f1b2ee6 AK |
842 | /* This value is used in tree-sra to decide whether it might benefical |
843 | to split a struct move into several word-size moves. For S/390 | |
844 | only small values make sense here since struct moves are relatively | |
845 | cheap thanks to mvc so the small default value choosen for archs | |
846 | with memmove patterns should be ok. But this value is multiplied | |
847 | in tree-sra with UNITS_PER_WORD to make a decision so we adjust it | |
848 | here to compensate for that factor since mvc costs exactly the same | |
849 | on 31 and 64 bit. */ | |
e04ad03d | 850 | #define MOVE_RATIO(speed) (TARGET_64BIT? 2 : 4) |
5f1b2ee6 | 851 | |
862a2d83 UW |
852 | |
853 | /* Sections. */ | |
854 | ||
855 | /* Output before read-only data. */ | |
856 | #define TEXT_SECTION_ASM_OP ".text" | |
857 | ||
858 | /* Output before writable (initialized) data. */ | |
859 | #define DATA_SECTION_ASM_OP ".data" | |
860 | ||
861 | /* Output before writable (uninitialized) data. */ | |
862 | #define BSS_SECTION_ASM_OP ".bss" | |
863 | ||
864 | /* S/390 constant pool breaks the devices in crtstuff.c to control section | |
865 | in where code resides. We have to write it as asm code. */ | |
866 | #ifndef __s390x__ | |
867 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
868 | asm (SECTION_OP "\n\ | |
869 | bras\t%r2,1f\n\ | |
870 | 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\ | |
871 | 1: l\t%r3,0(%r2)\n\ | |
872 | bas\t%r14,0(%r3,%r2)\n\ | |
873 | .previous"); | |
874 | #endif | |
63a1ff86 | 875 | |
862a2d83 UW |
876 | |
877 | /* Position independent code. */ | |
878 | ||
c7453384 | 879 | extern int flag_pic; |
862a2d83 UW |
880 | |
881 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM) | |
882 | ||
883 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) | |
63a1ff86 UW |
884 | |
885 | ||
886 | /* Assembler file format. */ | |
887 | ||
888 | /* Character to start a comment. */ | |
889 | #define ASM_COMMENT_START "#" | |
890 | ||
891 | /* Declare an uninitialized external linkage data object. */ | |
892 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
893 | asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) | |
894 | ||
895 | /* Globalizing directive for a label. */ | |
896 | #define GLOBAL_ASM_OP ".globl " | |
897 | ||
898 | /* Advance the location counter to a multiple of 2**LOG bytes. */ | |
899 | #define ASM_OUTPUT_ALIGN(FILE, LOG) \ | |
900 | if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG)) | |
901 | ||
902 | /* Advance the location counter by SIZE bytes. */ | |
903 | #define ASM_OUTPUT_SKIP(FILE, SIZE) \ | |
58e15542 | 904 | fprintf ((FILE), "\t.set\t.,.+"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) |
63a1ff86 | 905 | |
63a1ff86 UW |
906 | /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */ |
907 | #define LOCAL_LABEL_PREFIX "." | |
9db1d521 HP |
908 | |
909 | /* How to refer to registers in assembler output. This sequence is | |
910 | indexed by compiler's hard-register-number (see above). */ | |
9db1d521 HP |
911 | #define REGISTER_NAMES \ |
912 | { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ | |
a38e09bc | 913 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ |
9db1d521 | 914 | "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \ |
a38e09bc | 915 | "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \ |
c5aa1d12 | 916 | "%ap", "%cc", "%fp", "%rp", "%a0", "%a1" \ |
9db1d521 HP |
917 | } |
918 | ||
63a1ff86 | 919 | /* Print operand X (an rtx) in assembler syntax to file FILE. */ |
9db1d521 | 920 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) |
9db1d521 HP |
921 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) |
922 | ||
faeb9bb6 UW |
923 | /* Output machine-dependent UNSPECs in address constants. */ |
924 | #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ | |
925 | do { \ | |
926 | if (!s390_output_addr_const_extra (FILE, (X))) \ | |
927 | goto FAIL; \ | |
928 | } while (0); | |
929 | ||
63a1ff86 UW |
930 | /* Output an element of a case-vector that is absolute. */ |
931 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
932 | do { \ | |
933 | char buf[32]; \ | |
9602b6a1 | 934 | fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ |
63a1ff86 UW |
935 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ |
936 | assemble_name ((FILE), buf); \ | |
937 | fputc ('\n', (FILE)); \ | |
938 | } while (0) | |
939 | ||
940 | /* Output an element of a case-vector that is relative. */ | |
941 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
942 | do { \ | |
943 | char buf[32]; \ | |
9602b6a1 | 944 | fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ |
63a1ff86 UW |
945 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ |
946 | assemble_name ((FILE), buf); \ | |
947 | fputc ('-', (FILE)); \ | |
948 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \ | |
949 | assemble_name ((FILE), buf); \ | |
950 | fputc ('\n', (FILE)); \ | |
951 | } while (0) | |
952 | ||
9db1d521 | 953 | |
862a2d83 UW |
954 | /* Miscellaneous parameters. */ |
955 | ||
862a2d83 UW |
956 | /* Specify the machine mode that this machine uses for the index in the |
957 | tablejump instruction. */ | |
958 | #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) | |
959 | ||
862a2d83 UW |
960 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
961 | is done just by pretending it is already truncated. */ | |
962 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
963 | ||
964 | /* Specify the machine mode that pointers have. | |
965 | After generation of rtl, the compiler makes no further distinction | |
966 | between pointers and any other objects of this machine mode. */ | |
967 | #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode)) | |
968 | ||
c7453384 EC |
969 | /* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */ |
970 | #define POINTERS_EXTEND_UNSIGNED -1 | |
971 | ||
862a2d83 UW |
972 | /* A function address in a call instruction is a byte address (for |
973 | indexing purposes) so give the MEM rtx a byte's mode. */ | |
974 | #define FUNCTION_MODE QImode | |
975 | ||
ec24698e UW |
976 | /* Specify the value which is used when clz operand is zero. */ |
977 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1) | |
978 | ||
0bfc3f69 | 979 | /* Machine-specific symbol_ref flags. */ |
963fc8d0 AK |
980 | #define SYMBOL_FLAG_ALIGN1 (SYMBOL_FLAG_MACH_DEP << 0) |
981 | #define SYMBOL_REF_ALIGN1_P(X) \ | |
982 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN1)) | |
983 | #define SYMBOL_FLAG_NOT_NATURALLY_ALIGNED (SYMBOL_FLAG_MACH_DEP << 1) | |
984 | #define SYMBOL_REF_NOT_NATURALLY_ALIGNED_P(X) \ | |
985 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_NOT_NATURALLY_ALIGNED)) | |
0bfc3f69 AS |
986 | |
987 | /* Check whether integer displacement is in range. */ | |
988 | #define DISP_IN_RANGE(d) \ | |
989 | (TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \ | |
990 | : ((d) >= 0 && (d) <= 4095)) | |
991 | ||
c7453384 | 992 | #endif |