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9db1d521 | 1 | /* Definitions of target machine for GNU compiler, for IBM S/390 |
2f83c7d6 | 2 | Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, |
963fc8d0 | 3 | 2007, 2008 Free Software Foundation, Inc. |
9db1d521 | 4 | Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
f314b9b1 | 5 | Ulrich Weigand (uweigand@de.ibm.com). |
963fc8d0 | 6 | Andreas Krebbel (Andreas.Krebbel@de.ibm.com) |
9db1d521 | 7 | |
58add37a | 8 | This file is part of GCC. |
9db1d521 | 9 | |
58add37a UW |
10 | GCC is free software; you can redistribute it and/or modify it under |
11 | the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 12 | Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
13 | version. |
14 | ||
15 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
16 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
18 | for more details. | |
9db1d521 HP |
19 | |
20 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
21 | along with GCC; see the file COPYING3. If not see |
22 | <http://www.gnu.org/licenses/>. */ | |
9db1d521 HP |
23 | |
24 | #ifndef _S390_H | |
25 | #define _S390_H | |
26 | ||
42c78618 UW |
27 | /* Override the __fixdfdi etc. routines when building libgcc2. |
28 | ??? This should be done in a cleaner way ... */ | |
fe86047c | 29 | #if defined (IN_LIBGCC2) && !defined (__s390x__) |
ca11c37c | 30 | #include <config/s390/fixdfdi.h> |
42c78618 UW |
31 | #endif |
32 | ||
c7453384 | 33 | /* Which processor to generate code or schedule for. The cpu attribute |
1fec52be HP |
34 | defines a list that mirrors this list, so changes to s390.md must be |
35 | made at the same time. */ | |
36 | ||
37 | enum processor_type | |
38 | { | |
c7453384 EC |
39 | PROCESSOR_9672_G5, |
40 | PROCESSOR_9672_G6, | |
41 | PROCESSOR_2064_Z900, | |
f13e0d4e | 42 | PROCESSOR_2084_Z990, |
ec24698e | 43 | PROCESSOR_2094_Z9_109, |
93538e8e | 44 | PROCESSOR_2097_Z10, |
1fec52be HP |
45 | PROCESSOR_max |
46 | }; | |
47 | ||
f13e0d4e UW |
48 | /* Optional architectural facilities supported by the processor. */ |
49 | ||
50 | enum processor_flags | |
51 | { | |
52 | PF_IEEE_FLOAT = 1, | |
53 | PF_ZARCH = 2, | |
ec24698e | 54 | PF_LONG_DISPLACEMENT = 4, |
85dae55a | 55 | PF_EXTIMM = 8, |
93538e8e AK |
56 | PF_DFP = 16, |
57 | PF_Z10 = 32 | |
f13e0d4e UW |
58 | }; |
59 | ||
60 | extern enum processor_type s390_tune; | |
61 | extern enum processor_flags s390_tune_flags; | |
1fec52be HP |
62 | |
63 | extern enum processor_type s390_arch; | |
f13e0d4e | 64 | extern enum processor_flags s390_arch_flags; |
d75f90f1 | 65 | |
963fc8d0 AK |
66 | /* These flags indicate that the generated code should run on a cpu |
67 | providing the respective hardware facility regardless of the | |
68 | current cpu mode (ESA or z/Architecture). */ | |
69 | ||
f13e0d4e UW |
70 | #define TARGET_CPU_IEEE_FLOAT \ |
71 | (s390_arch_flags & PF_IEEE_FLOAT) | |
72 | #define TARGET_CPU_ZARCH \ | |
73 | (s390_arch_flags & PF_ZARCH) | |
74 | #define TARGET_CPU_LONG_DISPLACEMENT \ | |
75 | (s390_arch_flags & PF_LONG_DISPLACEMENT) | |
ec24698e UW |
76 | #define TARGET_CPU_EXTIMM \ |
77 | (s390_arch_flags & PF_EXTIMM) | |
85dae55a AK |
78 | #define TARGET_CPU_DFP \ |
79 | (s390_arch_flags & PF_DFP) | |
93538e8e AK |
80 | #define TARGET_CPU_Z10 \ |
81 | (s390_arch_flags & PF_Z10) | |
f13e0d4e | 82 | |
963fc8d0 AK |
83 | /* These flags indicate that the generated code should run on a cpu |
84 | providing the respective hardware facility when run in | |
85 | z/Architecture mode. */ | |
86 | ||
f13e0d4e UW |
87 | #define TARGET_LONG_DISPLACEMENT \ |
88 | (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT) | |
ec24698e UW |
89 | #define TARGET_EXTIMM \ |
90 | (TARGET_ZARCH && TARGET_CPU_EXTIMM) | |
85dae55a | 91 | #define TARGET_DFP \ |
fb068247 | 92 | (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT) |
93538e8e AK |
93 | #define TARGET_Z10 \ |
94 | (TARGET_ZARCH && TARGET_CPU_Z10) | |
42c78618 | 95 | |
862a2d83 | 96 | /* Run-time target specification. */ |
9db1d521 | 97 | |
a771c4b3 UW |
98 | /* Defaults for option flags defined only on some subtargets. */ |
99 | #ifndef TARGET_TPF_PROFILING | |
100 | #define TARGET_TPF_PROFILING 0 | |
101 | #endif | |
102 | ||
4798630c D |
103 | /* This will be overridden by OS headers. */ |
104 | #define TARGET_TPF 0 | |
105 | ||
862a2d83 UW |
106 | /* Target CPU builtins. */ |
107 | #define TARGET_CPU_CPP_BUILTINS() \ | |
108 | do \ | |
109 | { \ | |
110 | builtin_assert ("cpu=s390"); \ | |
111 | builtin_assert ("machine=s390"); \ | |
112 | builtin_define ("__s390__"); \ | |
113 | if (TARGET_64BIT) \ | |
114 | builtin_define ("__s390x__"); \ | |
f61a2c7d AK |
115 | if (TARGET_LONG_DOUBLE_128) \ |
116 | builtin_define ("__LONG_DOUBLE_128__"); \ | |
862a2d83 UW |
117 | } \ |
118 | while (0) | |
9db1d521 | 119 | |
58d10f89 | 120 | #ifdef DEFAULT_TARGET_64BIT |
47d94c1a | 121 | #define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP) |
58d10f89 | 122 | #else |
85dae55a | 123 | #define TARGET_DEFAULT 0 |
58d10f89 UW |
124 | #endif |
125 | ||
f13e0d4e UW |
126 | /* Support for configure-time defaults. */ |
127 | #define OPTION_DEFAULT_SPECS \ | |
128 | { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" }, \ | |
129 | { "arch", "%{!march=*:-march=%(VALUE)}" }, \ | |
130 | { "tune", "%{!mtune=*:-mtune=%(VALUE)}" } | |
131 | ||
132 | /* Defaulting rules. */ | |
133 | #ifdef DEFAULT_TARGET_64BIT | |
134 | #define DRIVER_SELF_SPECS \ | |
135 | "%{!m31:%{!m64:-m64}}", \ | |
136 | "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ | |
137 | "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}" | |
138 | #else | |
139 | #define DRIVER_SELF_SPECS \ | |
140 | "%{!m31:%{!m64:-m31}}", \ | |
141 | "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ | |
142 | "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}" | |
143 | #endif | |
144 | ||
862a2d83 UW |
145 | /* Target version string. Overridden by the OS header. */ |
146 | #ifdef DEFAULT_TARGET_64BIT | |
147 | #define TARGET_VERSION fprintf (stderr, " (zSeries)"); | |
148 | #else | |
149 | #define TARGET_VERSION fprintf (stderr, " (S/390)"); | |
150 | #endif | |
9db1d521 | 151 | |
862a2d83 UW |
152 | /* Hooks to override options. */ |
153 | #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) optimization_options(LEVEL, SIZE) | |
4023fb28 UW |
154 | #define OVERRIDE_OPTIONS override_options () |
155 | ||
862a2d83 UW |
156 | /* Frame pointer is not used for debugging. */ |
157 | #define CAN_DEBUG_WITHOUT_FP | |
9db1d521 | 158 | |
638e37c2 | 159 | /* Constants needed to control the TEST DATA CLASS (TDC) instruction. */ |
0387c142 WG |
160 | #define S390_TDC_POSITIVE_ZERO (1 << 11) |
161 | #define S390_TDC_NEGATIVE_ZERO (1 << 10) | |
162 | #define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER (1 << 9) | |
163 | #define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER (1 << 8) | |
164 | #define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER (1 << 7) | |
165 | #define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER (1 << 6) | |
166 | #define S390_TDC_POSITIVE_INFINITY (1 << 5) | |
167 | #define S390_TDC_NEGATIVE_INFINITY (1 << 4) | |
168 | #define S390_TDC_POSITIVE_QUIET_NAN (1 << 3) | |
169 | #define S390_TDC_NEGATIVE_QUIET_NAN (1 << 2) | |
170 | #define S390_TDC_POSITIVE_SIGNALING_NAN (1 << 1) | |
171 | #define S390_TDC_NEGATIVE_SIGNALING_NAN (1 << 0) | |
172 | ||
173 | /* The following values are different for DFP. */ | |
174 | #define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9) | |
175 | #define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8) | |
176 | #define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER (1 << 7) | |
177 | #define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER (1 << 6) | |
178 | ||
179 | /* For signbit, the BFP-DFP-difference makes no difference. */ | |
0f67fa83 | 180 | #define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \ |
0387c142 WG |
181 | | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \ |
182 | | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\ | |
0f67fa83 WG |
183 | | S390_TDC_NEGATIVE_INFINITY \ |
184 | | S390_TDC_NEGATIVE_QUIET_NAN \ | |
185 | | S390_TDC_NEGATIVE_SIGNALING_NAN ) | |
186 | ||
638e37c2 WG |
187 | #define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \ |
188 | | S390_TDC_NEGATIVE_INFINITY ) | |
9db1d521 | 189 | |
fe86047c UW |
190 | /* In libgcc2, determine target settings as compile-time constants. */ |
191 | #ifdef IN_LIBGCC2 | |
192 | #undef TARGET_64BIT | |
193 | #ifdef __s390x__ | |
194 | #define TARGET_64BIT 1 | |
195 | #else | |
196 | #define TARGET_64BIT 0 | |
197 | #endif | |
198 | #endif | |
199 | ||
200 | ||
9db1d521 HP |
201 | /* Target machine storage layout. */ |
202 | ||
862a2d83 | 203 | /* Everything is big-endian. */ |
9db1d521 | 204 | #define BITS_BIG_ENDIAN 1 |
9db1d521 | 205 | #define BYTES_BIG_ENDIAN 1 |
9db1d521 HP |
206 | #define WORDS_BIG_ENDIAN 1 |
207 | ||
9db1d521 | 208 | /* Width of a word, in units (bytes). */ |
9db1d521 | 209 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) |
fe86047c | 210 | #ifndef IN_LIBGCC2 |
9db1d521 | 211 | #define MIN_UNITS_PER_WORD 4 |
fe86047c | 212 | #endif |
862a2d83 | 213 | #define MAX_BITS_PER_WORD 64 |
9db1d521 | 214 | |
862a2d83 | 215 | /* Function arguments and return values are promoted to word size. */ |
d4453b7a | 216 | #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \ |
9db1d521 HP |
217 | if (INTEGRAL_MODE_P (MODE) && \ |
218 | GET_MODE_SIZE (MODE) < UNITS_PER_WORD) { \ | |
219 | (MODE) = Pmode; \ | |
220 | } | |
221 | ||
9db1d521 | 222 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
9db1d521 HP |
223 | #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32) |
224 | ||
225 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
9db1d521 HP |
226 | #define STACK_BOUNDARY 64 |
227 | ||
228 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
9db1d521 HP |
229 | #define FUNCTION_BOUNDARY 32 |
230 | ||
231 | /* There is no point aligning anything to a rounder boundary than this. */ | |
9db1d521 HP |
232 | #define BIGGEST_ALIGNMENT 64 |
233 | ||
234 | /* Alignment of field after `int : 0' in a structure. */ | |
9db1d521 HP |
235 | #define EMPTY_FIELD_BOUNDARY 32 |
236 | ||
f710504c | 237 | /* Alignment on even addresses for LARL instruction. */ |
9db1d521 | 238 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) |
9db1d521 HP |
239 | #define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) |
240 | ||
862a2d83 | 241 | /* Alignment is not required by the hardware. */ |
9db1d521 HP |
242 | #define STRICT_ALIGNMENT 0 |
243 | ||
862a2d83 UW |
244 | /* Mode of stack savearea. |
245 | FUNCTION is VOIDmode because calling convention maintains SP. | |
246 | BLOCK needs Pmode for SP. | |
247 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ | |
248 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
249 | (LEVEL == SAVE_FUNCTION ? VOIDmode \ | |
43ab026f | 250 | : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode) |
862a2d83 | 251 | |
9db1d521 | 252 | |
862a2d83 | 253 | /* Type layout. */ |
9db1d521 | 254 | |
862a2d83 UW |
255 | /* Sizes in bits of the source language data types. */ |
256 | #define SHORT_TYPE_SIZE 16 | |
257 | #define INT_TYPE_SIZE 32 | |
258 | #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) | |
862a2d83 UW |
259 | #define LONG_LONG_TYPE_SIZE 64 |
260 | #define FLOAT_TYPE_SIZE 32 | |
261 | #define DOUBLE_TYPE_SIZE 64 | |
f61a2c7d AK |
262 | #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) |
263 | ||
264 | /* Define this to set long double type size to use in libgcc2.c, which can | |
265 | not depend on target_flags. */ | |
266 | #ifdef __LONG_DOUBLE_128__ | |
267 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 | |
268 | #else | |
269 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 | |
270 | #endif | |
271 | ||
272 | /* Work around target_flags dependency in ada/targtyps.c. */ | |
273 | #define WIDEST_HARDWARE_FP_SIZE 64 | |
862a2d83 UW |
274 | |
275 | /* We use "unsigned char" as default. */ | |
276 | #define DEFAULT_SIGNED_CHAR 0 | |
277 | ||
278 | ||
279 | /* Register usage. */ | |
280 | ||
281 | /* We have 16 general purpose registers (registers 0-15), | |
282 | and 16 floating point registers (registers 16-31). | |
283 | (On non-IEEE machines, we have only 4 fp registers.) | |
c7453384 | 284 | |
862a2d83 UW |
285 | Amongst the general purpose registers, some are used |
286 | for specific purposes: | |
287 | GPR 11: Hard frame pointer (if needed) | |
288 | GPR 12: Global offset table pointer (if needed) | |
289 | GPR 13: Literal pool base register | |
290 | GPR 14: Return address register | |
291 | GPR 15: Stack pointer | |
c7453384 | 292 | |
c5aa1d12 | 293 | Registers 32-35 are 'fake' hard registers that do not |
862a2d83 UW |
294 | correspond to actual hardware: |
295 | Reg 32: Argument pointer | |
296 | Reg 33: Condition code | |
c5aa1d12 UW |
297 | Reg 34: Frame pointer |
298 | Reg 35: Return address pointer | |
862a2d83 | 299 | |
c5aa1d12 UW |
300 | Registers 36 and 37 are mapped to access registers |
301 | 0 and 1, used to implement thread-local storage. */ | |
302 | ||
303 | #define FIRST_PSEUDO_REGISTER 38 | |
862a2d83 UW |
304 | |
305 | /* Standard register usage. */ | |
8e509cf9 UW |
306 | #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16) |
307 | #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16) | |
142cd70f | 308 | #define FP_REGNO_P(N) ((N) >= 16 && (N) < 32) |
8e509cf9 | 309 | #define CC_REGNO_P(N) ((N) == 33) |
a38e09bc | 310 | #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34 || (N) == 35) |
c5aa1d12 | 311 | #define ACCESS_REGNO_P(N) ((N) == 36 || (N) == 37) |
8e509cf9 UW |
312 | |
313 | #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) | |
314 | #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X))) | |
315 | #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) | |
316 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) | |
4888ec5d | 317 | #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X))) |
c5aa1d12 | 318 | #define ACCESS_REG_P(X) (REG_P (X) && ACCESS_REGNO_P (REGNO (X))) |
9db1d521 | 319 | |
862a2d83 | 320 | /* Set up fixed registers and calling convention: |
9db1d521 | 321 | |
862a2d83 UW |
322 | GPRs 0-5 are always call-clobbered, |
323 | GPRs 6-15 are always call-saved. | |
324 | GPR 12 is fixed if used as GOT pointer. | |
325 | GPR 13 is always fixed (as literal pool pointer). | |
545d16ff | 326 | GPR 14 is always fixed on S/390 machines (as return address). |
862a2d83 UW |
327 | GPR 15 is always fixed (as stack pointer). |
328 | The 'fake' hard registers are call-clobbered and fixed. | |
c5aa1d12 | 329 | The access registers are call-saved and fixed. |
9db1d521 | 330 | |
862a2d83 UW |
331 | On 31-bit, FPRs 18-19 are call-clobbered; |
332 | on 64-bit, FPRs 24-31 are call-clobbered. | |
333 | The remaining FPRs are call-saved. */ | |
9db1d521 HP |
334 | |
335 | #define FIXED_REGISTERS \ | |
336 | { 0, 0, 0, 0, \ | |
337 | 0, 0, 0, 0, \ | |
338 | 0, 0, 0, 0, \ | |
339 | 0, 1, 1, 1, \ | |
340 | 0, 0, 0, 0, \ | |
341 | 0, 0, 0, 0, \ | |
342 | 0, 0, 0, 0, \ | |
343 | 0, 0, 0, 0, \ | |
c5aa1d12 UW |
344 | 1, 1, 1, 1, \ |
345 | 1, 1 } | |
9db1d521 | 346 | |
9db1d521 HP |
347 | #define CALL_USED_REGISTERS \ |
348 | { 1, 1, 1, 1, \ | |
349 | 1, 1, 0, 0, \ | |
350 | 0, 0, 0, 0, \ | |
351 | 0, 1, 1, 1, \ | |
4023fb28 UW |
352 | 1, 1, 1, 1, \ |
353 | 1, 1, 1, 1, \ | |
354 | 1, 1, 1, 1, \ | |
355 | 1, 1, 1, 1, \ | |
c5aa1d12 UW |
356 | 1, 1, 1, 1, \ |
357 | 1, 1 } | |
4023fb28 | 358 | |
4023fb28 UW |
359 | #define CALL_REALLY_USED_REGISTERS \ |
360 | { 1, 1, 1, 1, \ | |
9db1d521 | 361 | 1, 1, 0, 0, \ |
4023fb28 UW |
362 | 0, 0, 0, 0, \ |
363 | 0, 0, 0, 0, \ | |
9db1d521 HP |
364 | 1, 1, 1, 1, \ |
365 | 1, 1, 1, 1, \ | |
366 | 1, 1, 1, 1, \ | |
4023fb28 | 367 | 1, 1, 1, 1, \ |
c5aa1d12 UW |
368 | 1, 1, 1, 1, \ |
369 | 0, 0 } | |
9db1d521 | 370 | |
38899e29 | 371 | #define CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage () |
9db1d521 | 372 | |
862a2d83 UW |
373 | /* Preferred register allocation order. */ |
374 | #define REG_ALLOC_ORDER \ | |
7633f08e | 375 | { 1, 2, 3, 4, 5, 0, 12, 11, 10, 9, 8, 7, 6, 14, 13, \ |
862a2d83 UW |
376 | 16, 17, 18, 19, 20, 21, 22, 23, \ |
377 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
c5aa1d12 | 378 | 15, 32, 33, 34, 35, 36, 37 } |
9db1d521 | 379 | |
9db1d521 | 380 | |
862a2d83 | 381 | /* Fitting values into registers. */ |
c7453384 | 382 | |
862a2d83 UW |
383 | /* Integer modes <= word size fit into any GPR. |
384 | Integer modes > word size fit into successive GPRs, starting with | |
385 | an even-numbered register. | |
386 | SImode and DImode fit into FPRs as well. | |
c7453384 | 387 | |
862a2d83 UW |
388 | Floating point modes <= word size fit into any FPR or GPR. |
389 | Floating point modes > word size (i.e. DFmode on 32-bit) fit | |
390 | into any FPR, or an even-odd GPR pair. | |
f61a2c7d | 391 | TFmode fits only into an even-odd FPR pair. |
c7453384 | 392 | |
862a2d83 UW |
393 | Complex floating point modes fit either into two FPRs, or into |
394 | successive GPRs (again starting with an even number). | |
f61a2c7d | 395 | TCmode fits only into two successive even-odd FPR pairs. |
c7453384 | 396 | |
862a2d83 | 397 | Condition code modes fit only into the CC register. */ |
9db1d521 | 398 | |
74aa8b4b AK |
399 | /* Because all registers in a class have the same size HARD_REGNO_NREGS |
400 | is equivalent to CLASS_MAX_NREGS. */ | |
9db1d521 | 401 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
74aa8b4b AK |
402 | s390_class_max_nregs (REGNO_REG_CLASS (REGNO), (MODE)) |
403 | ||
404 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
405 | s390_hard_regno_mode_ok ((REGNO), (MODE)) | |
406 | ||
407 | #define HARD_REGNO_RENAME_OK(FROM, TO) \ | |
7633f08e UW |
408 | s390_hard_regno_rename_ok (FROM, TO) |
409 | ||
9db1d521 HP |
410 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
411 | (((MODE1) == SFmode || (MODE1) == DFmode) \ | |
412 | == ((MODE2) == SFmode || (MODE2) == DFmode)) | |
413 | ||
862a2d83 UW |
414 | /* Maximum number of registers to represent a value of mode MODE |
415 | in a register of class CLASS. */ | |
416 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
74aa8b4b | 417 | s390_class_max_nregs ((CLASS), (MODE)) |
4023fb28 | 418 | |
862a2d83 UW |
419 | /* If a 4-byte value is loaded into a FPR, it is placed into the |
420 | *upper* half of the register, not the lower. Therefore, we | |
c5aa1d12 UW |
421 | cannot use SUBREGs to switch between modes in FP registers. |
422 | Likewise for access registers, since they have only half the | |
423 | word size on 64-bit. */ | |
f61a2c7d AK |
424 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ |
425 | (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ | |
426 | ? ((reg_classes_intersect_p (FP_REGS, CLASS) \ | |
427 | && (GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8)) \ | |
428 | || reg_classes_intersect_p (ACCESS_REGS, CLASS)) : 0) | |
9db1d521 | 429 | |
862a2d83 | 430 | /* Register classes. */ |
c7453384 | 431 | |
862a2d83 UW |
432 | /* We use the following register classes: |
433 | GENERAL_REGS All general purpose registers | |
434 | ADDR_REGS All general purpose registers except %r0 | |
435 | (These registers can be used in address generation) | |
436 | FP_REGS All floating point registers | |
c5aa1d12 UW |
437 | CC_REGS The condition code register |
438 | ACCESS_REGS The access registers | |
c7453384 | 439 | |
862a2d83 UW |
440 | GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS |
441 | ADDR_FP_REGS Union of ADDR_REGS and FP_REGS | |
c5aa1d12 UW |
442 | GENERAL_CC_REGS Union of GENERAL_REGS and CC_REGS |
443 | ADDR_CC_REGS Union of ADDR_REGS and CC_REGS | |
c7453384 | 444 | |
862a2d83 UW |
445 | NO_REGS No registers |
446 | ALL_REGS All registers | |
c7453384 | 447 | |
862a2d83 | 448 | Note that the 'fake' frame pointer and argument pointer registers |
c5aa1d12 | 449 | are included amongst the address registers here. */ |
9db1d521 HP |
450 | |
451 | enum reg_class | |
452 | { | |
c5aa1d12 | 453 | NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS, |
9dc62c00 | 454 | ADDR_CC_REGS, GENERAL_CC_REGS, |
4023fb28 UW |
455 | FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, |
456 | ALL_REGS, LIM_REG_CLASSES | |
9db1d521 | 457 | }; |
9db1d521 HP |
458 | #define N_REG_CLASSES (int) LIM_REG_CLASSES |
459 | ||
c5aa1d12 UW |
460 | #define REG_CLASS_NAMES \ |
461 | { "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS", \ | |
462 | "ADDR_CC_REGS", "GENERAL_CC_REGS", \ | |
463 | "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" } | |
9db1d521 | 464 | |
862a2d83 | 465 | /* Class -> register mapping. */ |
9db1d521 HP |
466 | #define REG_CLASS_CONTENTS \ |
467 | { \ | |
468 | { 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
9dc62c00 | 469 | { 0x00000000, 0x00000002 }, /* CC_REGS */ \ |
a38e09bc AK |
470 | { 0x0000fffe, 0x0000000d }, /* ADDR_REGS */ \ |
471 | { 0x0000ffff, 0x0000000d }, /* GENERAL_REGS */ \ | |
c5aa1d12 | 472 | { 0x00000000, 0x00000030 }, /* ACCESS_REGS */ \ |
9dc62c00 AK |
473 | { 0x0000fffe, 0x0000000f }, /* ADDR_CC_REGS */ \ |
474 | { 0x0000ffff, 0x0000000f }, /* GENERAL_CC_REGS */ \ | |
9db1d521 | 475 | { 0xffff0000, 0x00000000 }, /* FP_REGS */ \ |
a38e09bc AK |
476 | { 0xfffffffe, 0x0000000d }, /* ADDR_FP_REGS */ \ |
477 | { 0xffffffff, 0x0000000d }, /* GENERAL_FP_REGS */ \ | |
c5aa1d12 | 478 | { 0xffffffff, 0x0000003f }, /* ALL_REGS */ \ |
9db1d521 HP |
479 | } |
480 | ||
058e97ec VM |
481 | /* The following macro defines cover classes for Integrated Register |
482 | Allocator. Cover classes is a set of non-intersected register | |
483 | classes covering all hard registers used for register allocation | |
484 | purpose. Any move between two registers of a cover class should be | |
485 | cheaper than load or store of the registers. The macro value is | |
486 | array of register classes with LIM_REG_CLASSES used as the end | |
487 | marker. */ | |
488 | ||
489 | #define IRA_COVER_CLASSES \ | |
490 | { \ | |
491 | GENERAL_REGS, FP_REGS, CC_REGS, ACCESS_REGS, LIM_REG_CLASSES \ | |
492 | } | |
493 | ||
494 | /* In some case register allocation order is not enough for IRA to | |
495 | generate a good code. The following macro (if defined) increases | |
496 | cost of REGNO for a pseudo approximately by pseudo usage frequency | |
497 | multiplied by the macro value. | |
498 | ||
499 | We avoid usage of BASE_REGNUM by nonzero macro value because the | |
500 | reload can decide not to use the hard register because some | |
501 | constant was forced to be in memory. */ | |
502 | #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) \ | |
503 | (regno == BASE_REGNUM ? 0.0 : 0.5) | |
504 | ||
862a2d83 UW |
505 | /* Register -> class mapping. */ |
506 | extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; | |
507 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) | |
9db1d521 | 508 | |
862a2d83 UW |
509 | /* ADDR_REGS can be used as base or index register. */ |
510 | #define INDEX_REG_CLASS ADDR_REGS | |
511 | #define BASE_REG_CLASS ADDR_REGS | |
9db1d521 | 512 | |
862a2d83 UW |
513 | /* Check whether REGNO is a hard register of the suitable class |
514 | or a pseudo register currently allocated to one such. */ | |
515 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
516 | (((REGNO) < FIRST_PSEUDO_REGISTER \ | |
93fa8428 AK |
517 | && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \ |
518 | || ADDR_REGNO_P (reg_renumber[REGNO])) | |
862a2d83 | 519 | #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) |
9db1d521 | 520 | |
9db1d521 | 521 | |
862a2d83 UW |
522 | /* Given an rtx X being reloaded into a reg required to be in class CLASS, |
523 | return the class of reg to actually use. */ | |
524 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
525 | s390_preferred_reload_class ((X), (CLASS)) | |
9db1d521 | 526 | |
963fc8d0 AK |
527 | /* We need secondary memory to move data between GPRs and FPRs. With |
528 | DFP the ldgr lgdr instructions are available. But these | |
529 | instructions do not handle GPR pairs so it is not possible for 31 | |
530 | bit. */ | |
862a2d83 | 531 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ |
85dae55a AK |
532 | ((CLASS1) != (CLASS2) \ |
533 | && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS) \ | |
963fc8d0 | 534 | && (!TARGET_DFP || !TARGET_64BIT || GET_MODE_SIZE (MODE) != 8)) |
862a2d83 UW |
535 | |
536 | /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit | |
537 | because the movsi and movsf patterns don't handle r/f moves. */ | |
538 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
539 | (GET_MODE_BITSIZE (MODE) < 32 \ | |
540 | ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
541 | : MODE) | |
542 | ||
543 | ||
862a2d83 | 544 | /* Stack layout and calling conventions. */ |
c7453384 | 545 | |
862a2d83 UW |
546 | /* Our stack grows from higher to lower addresses. However, local variables |
547 | are accessed by positive offsets, and function arguments are stored at | |
548 | increasing addresses. */ | |
549 | #define STACK_GROWS_DOWNWARD | |
63296cb1 | 550 | #define FRAME_GROWS_DOWNWARD 1 |
862a2d83 | 551 | /* #undef ARGS_GROW_DOWNWARD */ |
9db1d521 | 552 | |
862a2d83 UW |
553 | /* The basic stack layout looks like this: the stack pointer points |
554 | to the register save area for called functions. Above that area | |
555 | is the location to place outgoing arguments. Above those follow | |
556 | dynamic allocations (alloca), and finally the local variables. */ | |
9db1d521 | 557 | |
862a2d83 UW |
558 | /* Offset from stack-pointer to first location of outgoing args. */ |
559 | #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96) | |
9db1d521 | 560 | |
862a2d83 | 561 | /* Offset within stack frame to start allocating local variables at. */ |
63296cb1 | 562 | #define STARTING_FRAME_OFFSET 0 |
9db1d521 | 563 | |
862a2d83 UW |
564 | /* Offset from the stack pointer register to an item dynamically |
565 | allocated on the stack, e.g., by `alloca'. */ | |
63296cb1 | 566 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ |
38173d38 | 567 | (STACK_POINTER_OFFSET + crtl->outgoing_args_size) |
9db1d521 | 568 | |
862a2d83 UW |
569 | /* Offset of first parameter from the argument pointer register value. |
570 | We have a fake argument pointer register that points directly to | |
571 | the argument area. */ | |
572 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
9db1d521 | 573 | |
c6d01079 AK |
574 | /* Defining this macro makes __builtin_frame_address(0) and |
575 | __builtin_return_address(0) work with -fomit-frame-pointer. */ | |
576 | #define INITIAL_FRAME_ADDRESS_RTX \ | |
577 | (TARGET_PACKED_STACK ? \ | |
578 | plus_constant (arg_pointer_rtx, -UNITS_PER_WORD) : \ | |
579 | plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET)) | |
580 | ||
c7453384 | 581 | /* The return address of the current frame is retrieved |
4023fb28 UW |
582 | from the initial value of register RETURN_REGNUM. |
583 | For frames farther back, we use the stack slot where | |
584 | the corresponding RETURN_REGNUM register was saved. */ | |
c6d01079 AK |
585 | #define DYNAMIC_CHAIN_ADDRESS(FRAME) \ |
586 | (TARGET_PACKED_STACK ? \ | |
587 | plus_constant ((FRAME), STACK_POINTER_OFFSET - UNITS_PER_WORD) : (FRAME)) | |
4023fb28 | 588 | |
c6d01079 | 589 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
5d4d885c | 590 | s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME))) |
9db1d521 | 591 | |
862a2d83 | 592 | /* In 31-bit mode, we need to mask off the high bit of return addresses. */ |
a556fd39 | 593 | #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff)) |
9db1d521 | 594 | |
4023fb28 | 595 | |
862a2d83 | 596 | /* Exception handling. */ |
c7453384 | 597 | |
862a2d83 UW |
598 | /* Describe calling conventions for DWARF-2 exception handling. */ |
599 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM) | |
4023fb28 | 600 | #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET |
9db1d521 HP |
601 | #define DWARF_FRAME_RETURN_COLUMN 14 |
602 | ||
603 | /* Describe how we implement __builtin_eh_return. */ | |
604 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM) | |
a38e09bc AK |
605 | #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx) |
606 | ||
18789f4e UW |
607 | /* Select a format to encode pointers in exception handling data. */ |
608 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
609 | (flag_pic \ | |
610 | ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ | |
611 | : DW_EH_PE_absptr) | |
612 | ||
9db1d521 | 613 | |
862a2d83 | 614 | /* Frame registers. */ |
9db1d521 | 615 | |
862a2d83 UW |
616 | #define STACK_POINTER_REGNUM 15 |
617 | #define FRAME_POINTER_REGNUM 34 | |
618 | #define HARD_FRAME_POINTER_REGNUM 11 | |
619 | #define ARG_POINTER_REGNUM 32 | |
a38e09bc | 620 | #define RETURN_ADDRESS_POINTER_REGNUM 35 |
9db1d521 | 621 | |
c7453384 EC |
622 | /* The static chain must be call-clobbered, but not used for |
623 | function argument passing. As register 1 is clobbered by | |
862a2d83 UW |
624 | the trampoline code, we only have one option. */ |
625 | #define STATIC_CHAIN_REGNUM 0 | |
9db1d521 | 626 | |
862a2d83 UW |
627 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
628 | To avoid ABI incompatibility, this number must not change even as | |
629 | 'fake' hard registers are added or removed. */ | |
630 | #define DWARF_FRAME_REGISTERS 34 | |
9db1d521 | 631 | |
9db1d521 | 632 | |
862a2d83 | 633 | /* Frame pointer and argument pointer elimination. */ |
9db1d521 | 634 | |
862a2d83 | 635 | #define FRAME_POINTER_REQUIRED 0 |
9db1d521 | 636 | |
7633f08e UW |
637 | #define ELIMINABLE_REGS \ |
638 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
639 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
640 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
641 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
642 | { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
643 | { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
644 | { BASE_REGNUM, BASE_REGNUM }} | |
9db1d521 | 645 | |
91086990 UW |
646 | #define CAN_ELIMINATE(FROM, TO) \ |
647 | s390_can_eliminate ((FROM), (TO)) | |
648 | ||
649 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
650 | (OFFSET) = s390_initial_elimination_offset ((FROM), (TO)) | |
9db1d521 | 651 | |
9db1d521 | 652 | |
862a2d83 | 653 | /* Stack arguments. */ |
c7453384 | 654 | |
862a2d83 UW |
655 | /* We need current_function_outgoing_args to be valid. */ |
656 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
9db1d521 | 657 | |
862a2d83 UW |
658 | /* Return doesn't modify the stack. */ |
659 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 | |
9db1d521 | 660 | |
9db1d521 | 661 | |
862a2d83 | 662 | /* Register arguments. */ |
c7453384 | 663 | |
9db1d521 HP |
664 | typedef struct s390_arg_structure |
665 | { | |
666 | int gprs; /* gpr so far */ | |
667 | int fprs; /* fpr so far */ | |
668 | } | |
669 | CUMULATIVE_ARGS; | |
670 | ||
07711f53 | 671 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \ |
9db1d521 HP |
672 | ((CUM).gprs=0, (CUM).fprs=0) |
673 | ||
9db1d521 | 674 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
994fe660 | 675 | s390_function_arg_advance (&CUM, MODE, TYPE, NAMED) |
9db1d521 | 676 | |
9db1d521 | 677 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
994fe660 | 678 | s390_function_arg (&CUM, MODE, TYPE, NAMED) |
9db1d521 | 679 | |
96e2afa8 AK |
680 | /* Arguments can be placed in general registers 2 to 6, or in floating |
681 | point registers 0 and 2 for 31 bit and fprs 0, 2, 4 and 6 for 64 | |
682 | bit. */ | |
862a2d83 | 683 | #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \ |
96e2afa8 | 684 | (N) == 16 || (N) == 17 || (TARGET_64BIT && ((N) == 18 || (N) == 19))) |
9db1d521 | 685 | |
9db1d521 | 686 | |
862a2d83 | 687 | /* Scalar return values. */ |
c7453384 | 688 | |
8c17530e UW |
689 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
690 | s390_function_value ((VALTYPE), VOIDmode) | |
691 | ||
692 | #define LIBCALL_VALUE(MODE) \ | |
693 | s390_function_value (NULL, (MODE)) | |
9db1d521 | 694 | |
862a2d83 | 695 | /* Only gpr 2 and fpr 0 are ever used as return registers. */ |
9db1d521 HP |
696 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16) |
697 | ||
9db1d521 | 698 | |
862a2d83 | 699 | /* Function entry and exit. */ |
c7453384 | 700 | |
862a2d83 UW |
701 | /* When returning from a function, the stack pointer does not matter. */ |
702 | #define EXIT_IGNORE_STACK 1 | |
9db1d521 | 703 | |
9db1d521 | 704 | |
862a2d83 | 705 | /* Profiling. */ |
9db1d521 HP |
706 | |
707 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
862a2d83 | 708 | s390_function_profiler ((FILE), ((LABELNO))) |
9db1d521 | 709 | |
c52a375d | 710 | #define PROFILE_BEFORE_PROLOGUE 1 |
9db1d521 | 711 | |
9db1d521 | 712 | |
862a2d83 | 713 | /* Trampolines for nested functions. */ |
9db1d521 | 714 | |
cadc42db | 715 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 32 : 16) |
9db1d521 | 716 | |
862a2d83 UW |
717 | #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \ |
718 | s390_initialize_trampoline ((ADDR), (FNADDR), (CXT)) | |
9db1d521 | 719 | |
862a2d83 UW |
720 | #define TRAMPOLINE_TEMPLATE(FILE) \ |
721 | s390_trampoline_template (FILE) | |
9db1d521 | 722 | |
9db1d521 | 723 | |
862a2d83 | 724 | /* Addressing modes, and classification of registers for them. */ |
9db1d521 | 725 | |
862a2d83 UW |
726 | /* Recognize any constant value that is a valid address. */ |
727 | #define CONSTANT_ADDRESS_P(X) 0 | |
9db1d521 | 728 | |
862a2d83 UW |
729 | /* Maximum number of registers that can appear in a valid memory address. */ |
730 | #define MAX_REGS_PER_ADDRESS 2 | |
9db1d521 | 731 | |
963fc8d0 AK |
732 | /* This definition replaces the formerly used 'm' constraint with a |
733 | different constraint letter in order to avoid changing semantics of | |
734 | the 'm' constraint when accepting new address formats in | |
735 | legitimate_address_p. The constraint letter defined here must not be | |
736 | used in insn definitions or inline assemblies. */ | |
737 | #define TARGET_MEM_CONSTRAINT 'e' | |
738 | ||
862a2d83 UW |
739 | /* S/390 has no mode dependent addresses. */ |
740 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) | |
9db1d521 HP |
741 | |
742 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a | |
743 | valid memory address for an instruction. | |
744 | The MODE argument is the machine mode for the MEM expression | |
862a2d83 | 745 | that wants to use this address. */ |
9db1d521 HP |
746 | #ifdef REG_OK_STRICT |
747 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
748 | { \ | |
749 | if (legitimate_address_p (MODE, X, 1)) \ | |
750 | goto ADDR; \ | |
751 | } | |
752 | #else | |
753 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
754 | { \ | |
755 | if (legitimate_address_p (MODE, X, 0)) \ | |
756 | goto ADDR; \ | |
757 | } | |
758 | #endif | |
759 | ||
9db1d521 HP |
760 | /* Try machine-dependent ways of modifying an illegitimate address |
761 | to be legitimate. If we find one, return the new, valid address. | |
762 | This macro is used in only one place: `memory_address' in explow.c. */ | |
9db1d521 HP |
763 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
764 | { \ | |
765 | (X) = legitimize_address (X, OLDX, MODE); \ | |
766 | if (memory_address_p (MODE, X)) \ | |
767 | goto WIN; \ | |
768 | } | |
769 | ||
0b540f12 UW |
770 | /* Try a machine-dependent way of reloading an illegitimate address |
771 | operand. If we find one, push the reload and jump to WIN. This | |
772 | macro is used in only one place: `find_reloads_address' in reload.c. */ | |
773 | #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ | |
774 | do { \ | |
0a2aaacc KG |
775 | rtx new_rtx = legitimize_reload_address (AD, MODE, OPNUM, (int)(TYPE)); \ |
776 | if (new_rtx) \ | |
0b540f12 | 777 | { \ |
0a2aaacc | 778 | (AD) = new_rtx; \ |
0b540f12 UW |
779 | goto WIN; \ |
780 | } \ | |
781 | } while (0) | |
782 | ||
862a2d83 UW |
783 | /* Nonzero if the constant value X is a legitimate general operand. |
784 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
785 | #define LEGITIMATE_CONSTANT_P(X) \ | |
786 | legitimate_constant_p (X) | |
9db1d521 | 787 | |
862a2d83 UW |
788 | /* Helper macro for s390.c and s390.md to check for symbolic constants. */ |
789 | #define SYMBOLIC_CONST(X) \ | |
790 | (GET_CODE (X) == SYMBOL_REF \ | |
791 | || GET_CODE (X) == LABEL_REF \ | |
792 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
9db1d521 | 793 | |
fd3cd001 UW |
794 | #define TLS_SYMBOLIC_CONST(X) \ |
795 | ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \ | |
796 | || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X))) | |
797 | ||
9db1d521 | 798 | |
862a2d83 | 799 | /* Condition codes. */ |
9db1d521 | 800 | |
862a2d83 UW |
801 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
802 | return the mode to be used for the comparison. */ | |
803 | #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y)) | |
c7453384 | 804 | |
68f9c5e2 UW |
805 | /* Canonicalize a comparison from one we don't have to one we do have. */ |
806 | #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ | |
807 | s390_canonicalize_comparison (&(CODE), &(OP0), &(OP1)) | |
808 | ||
862a2d83 UW |
809 | /* Define the information needed to generate branch and scc insns. This is |
810 | stored from the compare operation. Note that we can't use "rtx" here | |
811 | since it hasn't been defined! */ | |
e0374221 | 812 | extern struct rtx_def *s390_compare_op0, *s390_compare_op1, *s390_compare_emitted; |
9db1d521 | 813 | |
9db1d521 | 814 | |
862a2d83 | 815 | /* Relative costs of operations. */ |
9db1d521 | 816 | |
9db1d521 | 817 | /* On s390, copy between fprs and gprs is expensive. */ |
9db1d521 | 818 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
14b3e8ef UW |
819 | (( ( reg_classes_intersect_p ((CLASS1), GENERAL_REGS) \ |
820 | && reg_classes_intersect_p ((CLASS2), FP_REGS)) \ | |
821 | || ( reg_classes_intersect_p ((CLASS1), FP_REGS) \ | |
822 | && reg_classes_intersect_p ((CLASS2), GENERAL_REGS))) ? 10 : 1) | |
9db1d521 | 823 | |
9db1d521 HP |
824 | /* A C expression for the cost of moving data of mode M between a |
825 | register and memory. A value of 2 is the default; this cost is | |
862a2d83 | 826 | relative to those in `REGISTER_MOVE_COST'. */ |
9db1d521 HP |
827 | #define MEMORY_MOVE_COST(M, C, I) 1 |
828 | ||
829 | /* A C expression for the cost of a branch instruction. A value of 1 | |
830 | is the default; other values are interpreted relative to that. */ | |
3a4fd356 | 831 | #define BRANCH_COST(speed_p, predictable_p) 1 |
9db1d521 | 832 | |
862a2d83 UW |
833 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
834 | #define SLOW_BYTE_ACCESS 1 | |
835 | ||
c5443745 UW |
836 | /* An integer expression for the size in bits of the largest integer machine |
837 | mode that should actually be used. We allow pairs of registers. */ | |
838 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) | |
839 | ||
862a2d83 | 840 | /* The maximum number of bytes that a single instruction can move quickly |
ff482c8d | 841 | between memory and registers or between two memory locations. */ |
862a2d83 | 842 | #define MOVE_MAX (TARGET_64BIT ? 16 : 8) |
c5443745 | 843 | #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) |
862a2d83 | 844 | #define MAX_MOVE_MAX 16 |
9db1d521 | 845 | |
862a2d83 UW |
846 | /* Determine whether to use move_by_pieces or block move insn. */ |
847 | #define MOVE_BY_PIECES_P(SIZE, ALIGN) \ | |
848 | ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ | |
849 | || (TARGET_64BIT && (SIZE) == 8) ) | |
850 | ||
851 | /* Determine whether to use clear_by_pieces or block clear insn. */ | |
852 | #define CLEAR_BY_PIECES_P(SIZE, ALIGN) \ | |
853 | ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ | |
854 | || (TARGET_64BIT && (SIZE) == 8) ) | |
855 | ||
45d78e7f | 856 | /* This macro is used to determine whether store_by_pieces should be |
cfa31150 | 857 | called to "memcpy" storage when the source is a constant string. */ |
45d78e7f JJ |
858 | #define STORE_BY_PIECES_P(SIZE, ALIGN) MOVE_BY_PIECES_P (SIZE, ALIGN) |
859 | ||
cfa31150 SL |
860 | /* Likewise to decide whether to "memset" storage with byte values |
861 | other than zero. */ | |
862 | #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P (SIZE, ALIGN) | |
863 | ||
862a2d83 UW |
864 | /* Don't perform CSE on function addresses. */ |
865 | #define NO_FUNCTION_CSE | |
866 | ||
5f1b2ee6 AK |
867 | /* This value is used in tree-sra to decide whether it might benefical |
868 | to split a struct move into several word-size moves. For S/390 | |
869 | only small values make sense here since struct moves are relatively | |
870 | cheap thanks to mvc so the small default value choosen for archs | |
871 | with memmove patterns should be ok. But this value is multiplied | |
872 | in tree-sra with UNITS_PER_WORD to make a decision so we adjust it | |
873 | here to compensate for that factor since mvc costs exactly the same | |
874 | on 31 and 64 bit. */ | |
e04ad03d | 875 | #define MOVE_RATIO(speed) (TARGET_64BIT? 2 : 4) |
5f1b2ee6 | 876 | |
862a2d83 UW |
877 | |
878 | /* Sections. */ | |
879 | ||
880 | /* Output before read-only data. */ | |
881 | #define TEXT_SECTION_ASM_OP ".text" | |
882 | ||
883 | /* Output before writable (initialized) data. */ | |
884 | #define DATA_SECTION_ASM_OP ".data" | |
885 | ||
886 | /* Output before writable (uninitialized) data. */ | |
887 | #define BSS_SECTION_ASM_OP ".bss" | |
888 | ||
889 | /* S/390 constant pool breaks the devices in crtstuff.c to control section | |
890 | in where code resides. We have to write it as asm code. */ | |
891 | #ifndef __s390x__ | |
892 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
893 | asm (SECTION_OP "\n\ | |
894 | bras\t%r2,1f\n\ | |
895 | 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\ | |
896 | 1: l\t%r3,0(%r2)\n\ | |
897 | bas\t%r14,0(%r3,%r2)\n\ | |
898 | .previous"); | |
899 | #endif | |
63a1ff86 | 900 | |
862a2d83 UW |
901 | |
902 | /* Position independent code. */ | |
903 | ||
c7453384 | 904 | extern int flag_pic; |
862a2d83 UW |
905 | |
906 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM) | |
907 | ||
908 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) | |
63a1ff86 UW |
909 | |
910 | ||
911 | /* Assembler file format. */ | |
912 | ||
913 | /* Character to start a comment. */ | |
914 | #define ASM_COMMENT_START "#" | |
915 | ||
916 | /* Declare an uninitialized external linkage data object. */ | |
917 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
918 | asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) | |
919 | ||
920 | /* Globalizing directive for a label. */ | |
921 | #define GLOBAL_ASM_OP ".globl " | |
922 | ||
923 | /* Advance the location counter to a multiple of 2**LOG bytes. */ | |
924 | #define ASM_OUTPUT_ALIGN(FILE, LOG) \ | |
925 | if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG)) | |
926 | ||
927 | /* Advance the location counter by SIZE bytes. */ | |
928 | #define ASM_OUTPUT_SKIP(FILE, SIZE) \ | |
58e15542 | 929 | fprintf ((FILE), "\t.set\t.,.+"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) |
63a1ff86 | 930 | |
63a1ff86 UW |
931 | /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */ |
932 | #define LOCAL_LABEL_PREFIX "." | |
9db1d521 HP |
933 | |
934 | /* How to refer to registers in assembler output. This sequence is | |
935 | indexed by compiler's hard-register-number (see above). */ | |
9db1d521 HP |
936 | #define REGISTER_NAMES \ |
937 | { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ | |
a38e09bc | 938 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ |
9db1d521 | 939 | "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \ |
a38e09bc | 940 | "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \ |
c5aa1d12 | 941 | "%ap", "%cc", "%fp", "%rp", "%a0", "%a1" \ |
9db1d521 HP |
942 | } |
943 | ||
63a1ff86 | 944 | /* Print operand X (an rtx) in assembler syntax to file FILE. */ |
9db1d521 | 945 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) |
9db1d521 HP |
946 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) |
947 | ||
faeb9bb6 UW |
948 | /* Output machine-dependent UNSPECs in address constants. */ |
949 | #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ | |
950 | do { \ | |
951 | if (!s390_output_addr_const_extra (FILE, (X))) \ | |
952 | goto FAIL; \ | |
953 | } while (0); | |
954 | ||
63a1ff86 UW |
955 | /* Output an element of a case-vector that is absolute. */ |
956 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
957 | do { \ | |
958 | char buf[32]; \ | |
959 | fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \ | |
960 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ | |
961 | assemble_name ((FILE), buf); \ | |
962 | fputc ('\n', (FILE)); \ | |
963 | } while (0) | |
964 | ||
965 | /* Output an element of a case-vector that is relative. */ | |
966 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
967 | do { \ | |
968 | char buf[32]; \ | |
969 | fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \ | |
970 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ | |
971 | assemble_name ((FILE), buf); \ | |
972 | fputc ('-', (FILE)); \ | |
973 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \ | |
974 | assemble_name ((FILE), buf); \ | |
975 | fputc ('\n', (FILE)); \ | |
976 | } while (0) | |
977 | ||
9db1d521 | 978 | |
862a2d83 UW |
979 | /* Miscellaneous parameters. */ |
980 | ||
862a2d83 UW |
981 | /* Specify the machine mode that this machine uses for the index in the |
982 | tablejump instruction. */ | |
983 | #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) | |
984 | ||
862a2d83 UW |
985 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
986 | is done just by pretending it is already truncated. */ | |
987 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
988 | ||
989 | /* Specify the machine mode that pointers have. | |
990 | After generation of rtl, the compiler makes no further distinction | |
991 | between pointers and any other objects of this machine mode. */ | |
992 | #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode)) | |
993 | ||
c7453384 EC |
994 | /* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */ |
995 | #define POINTERS_EXTEND_UNSIGNED -1 | |
996 | ||
862a2d83 UW |
997 | /* A function address in a call instruction is a byte address (for |
998 | indexing purposes) so give the MEM rtx a byte's mode. */ | |
999 | #define FUNCTION_MODE QImode | |
1000 | ||
ec24698e UW |
1001 | /* Specify the value which is used when clz operand is zero. */ |
1002 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1) | |
1003 | ||
0bfc3f69 | 1004 | /* Machine-specific symbol_ref flags. */ |
963fc8d0 AK |
1005 | #define SYMBOL_FLAG_ALIGN1 (SYMBOL_FLAG_MACH_DEP << 0) |
1006 | #define SYMBOL_REF_ALIGN1_P(X) \ | |
1007 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN1)) | |
1008 | #define SYMBOL_FLAG_NOT_NATURALLY_ALIGNED (SYMBOL_FLAG_MACH_DEP << 1) | |
1009 | #define SYMBOL_REF_NOT_NATURALLY_ALIGNED_P(X) \ | |
1010 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_NOT_NATURALLY_ALIGNED)) | |
0bfc3f69 AS |
1011 | |
1012 | /* Check whether integer displacement is in range. */ | |
1013 | #define DISP_IN_RANGE(d) \ | |
1014 | (TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \ | |
1015 | : ((d) >= 0 && (d) <= 4095)) | |
1016 | ||
c7453384 | 1017 | #endif |