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9db1d521 | 1 | /* Definitions of target machine for GNU compiler, for IBM S/390 |
16c484c7 | 2 | Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
9db1d521 | 3 | Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
f314b9b1 | 4 | Ulrich Weigand (uweigand@de.ibm.com). |
9db1d521 HP |
5 | This file is part of GNU CC. |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #ifndef _S390_H | |
23 | #define _S390_H | |
24 | ||
9db1d521 HP |
25 | extern int flag_pic; |
26 | ||
27 | /* Run-time compilation parameters selecting different hardware subsets. */ | |
28 | ||
29 | extern int target_flags; | |
30 | ||
31 | /* Target macros checked at runtime of compiler. */ | |
32 | ||
33 | #define TARGET_HARD_FLOAT (target_flags & 1) | |
58d10f89 | 34 | #define TARGET_SOFT_FLOAT (!(target_flags & 1)) |
9db1d521 HP |
35 | #define TARGET_BACKCHAIN (target_flags & 2) |
36 | #define TARGET_SMALL_EXEC (target_flags & 4) | |
37 | #define TARGET_DEBUG_ARG (target_flags & 8) | |
38 | #define TARGET_64BIT (target_flags & 16) | |
39 | #define TARGET_MVCLE (target_flags & 32) | |
40 | ||
58d10f89 UW |
41 | #ifdef DEFAULT_TARGET_64BIT |
42 | #define TARGET_DEFAULT 0x13 | |
43 | #define TARGET_VERSION fprintf (stderr, " (zSeries)"); | |
44 | #else | |
9db1d521 | 45 | #define TARGET_DEFAULT 0x3 |
58d10f89 UW |
46 | #define TARGET_VERSION fprintf (stderr, " (S/390)"); |
47 | #endif | |
48 | ||
9db1d521 HP |
49 | |
50 | /* Macro to define tables used to set the flags. This is a list in braces | |
51 | of pairs in braces, each pair being { "NAME", VALUE } | |
52 | where VALUE is the bits to set or minus the bits to clear. | |
53 | An empty string NAME is used to identify the default VALUE. */ | |
54 | ||
55 | #define TARGET_SWITCHES \ | |
994fe660 UW |
56 | { { "hard-float", 1, N_("Use hardware fp")}, \ |
57 | { "soft-float", -1, N_("Don't use hardware fp")}, \ | |
58 | { "backchain", 2, N_("Set backchain")}, \ | |
59 | { "no-backchain", -2, N_("Don't set backchain (faster, but debug harder")}, \ | |
60 | { "small-exec", 4, N_("Use bras for execucable < 64k")}, \ | |
61 | { "no-small-exec",-4, N_("Don't use bras")}, \ | |
62 | { "debug", 8, N_("Additional debug prints")}, \ | |
63 | { "no-debug", -8, N_("Don't print additional debug prints")}, \ | |
64 | { "64", 16, N_("64 bit mode")}, \ | |
65 | { "31", -16, N_("31 bit mode")}, \ | |
66 | { "mvcle", 32, N_("mvcle use")}, \ | |
67 | { "no-mvcle", -32, N_("mvc&ex")}, \ | |
9db1d521 HP |
68 | { "", TARGET_DEFAULT, 0 } } |
69 | ||
70 | /* Define this to change the optimizations performed by default. */ | |
994fe660 | 71 | #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) optimization_options(LEVEL, SIZE) |
9db1d521 | 72 | |
4023fb28 UW |
73 | /* Sometimes certain combinations of command options do not make sense |
74 | on a particular target machine. You can define a macro | |
75 | `OVERRIDE_OPTIONS' to take account of this. This macro, if | |
76 | defined, is executed once just after all the command options have | |
77 | been parsed. */ | |
78 | #define OVERRIDE_OPTIONS override_options () | |
79 | ||
dd3fbd93 UW |
80 | /* Target CPU builtins. */ |
81 | #define TARGET_CPU_CPP_BUILTINS() \ | |
82 | do \ | |
83 | { \ | |
84 | builtin_assert ("cpu=s390"); \ | |
85 | builtin_assert ("machine=s390"); \ | |
86 | builtin_define ("__s390__"); \ | |
87 | if (TARGET_64BIT) \ | |
88 | builtin_define ("__s390x__"); \ | |
89 | } \ | |
90 | while (0) | |
4023fb28 | 91 | |
ba31d94e | 92 | /* Defines for real.c. */ |
70eeb10b UW |
93 | #define IEEE_FLOAT 1 |
94 | #define TARGET_IBM_FLOAT 0 | |
95 | #define TARGET_IEEE_FLOAT 1 | |
96 | ||
9db1d521 HP |
97 | /* The amount of space used for outgoing arguments. */ |
98 | ||
99 | extern int current_function_outgoing_args_size; | |
100 | ||
101 | /* Target machine storage layout. */ | |
102 | ||
103 | /* Define this if most significant bit is lowest numbered in instructions | |
104 | that operate on numbered bit-fields. */ | |
105 | ||
106 | #define BITS_BIG_ENDIAN 1 | |
107 | ||
108 | /* Define this if most significant byte of a word is the lowest numbered. */ | |
109 | ||
110 | #define BYTES_BIG_ENDIAN 1 | |
111 | ||
112 | /* Define this if MS word of a multiword is the lowest numbered. */ | |
113 | ||
114 | #define WORDS_BIG_ENDIAN 1 | |
115 | ||
f314b9b1 | 116 | #define MAX_BITS_PER_WORD 64 |
9db1d521 HP |
117 | |
118 | /* Width of a word, in units (bytes). */ | |
119 | ||
120 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) | |
121 | #define MIN_UNITS_PER_WORD 4 | |
122 | ||
9db1d521 HP |
123 | /* A C expression for the size in bits of the type `short' on the |
124 | target machine. If you don't define this, the default is half a | |
125 | word. (If this would be less than one storage unit, it is | |
126 | rounded up to one unit.) */ | |
127 | #define SHORT_TYPE_SIZE 16 | |
128 | ||
129 | /* A C expression for the size in bits of the type `int' on the | |
130 | target machine. If you don't define this, the default is one | |
131 | word. */ | |
132 | #define INT_TYPE_SIZE 32 | |
133 | ||
134 | /* A C expression for the size in bits of the type `long' on the | |
135 | target machine. If you don't define this, the default is one | |
136 | word. */ | |
137 | #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) | |
f314b9b1 | 138 | #define MAX_LONG_TYPE_SIZE 64 |
9db1d521 HP |
139 | |
140 | /* A C expression for the size in bits of the type `long long' on the | |
141 | target machine. If you don't define this, the default is two | |
142 | words. */ | |
143 | #define LONG_LONG_TYPE_SIZE 64 | |
144 | ||
145 | /* Right now we only support two floating point formats, the | |
146 | 32 and 64 bit ieee formats. */ | |
147 | ||
148 | #define FLOAT_TYPE_SIZE 32 | |
149 | #define DOUBLE_TYPE_SIZE 64 | |
150 | #define LONG_DOUBLE_TYPE_SIZE 64 | |
151 | ||
152 | /* Define this macro if it is advisable to hold scalars in registers | |
153 | in a wider mode than that declared by the program. In such cases, | |
154 | the value is constrained to be within the bounds of the declared | |
155 | type, but kept valid in the wider mode. The signedness of the | |
156 | extension may differ from that of the type. */ | |
157 | ||
158 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
159 | if (INTEGRAL_MODE_P (MODE) && \ | |
160 | GET_MODE_SIZE (MODE) < UNITS_PER_WORD) { \ | |
161 | (MODE) = Pmode; \ | |
162 | } | |
163 | ||
164 | /* Defining PROMOTE_FUNCTION_ARGS eliminates some unnecessary zero/sign | |
165 | extensions applied to char/short functions arguments. Defining | |
166 | PROMOTE_FUNCTION_RETURN does the same for function returns. */ | |
167 | ||
168 | #define PROMOTE_FUNCTION_ARGS | |
169 | #define PROMOTE_FUNCTION_RETURN | |
170 | #define PROMOTE_FOR_CALL_ONLY | |
171 | ||
172 | /* Allocation boundary (in *bits*) for storing pointers in memory. */ | |
173 | ||
174 | #define POINTER_BOUNDARY 32 | |
175 | ||
176 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ | |
177 | ||
178 | #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32) | |
179 | ||
180 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
181 | ||
182 | #define STACK_BOUNDARY 64 | |
183 | ||
184 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
185 | ||
186 | #define FUNCTION_BOUNDARY 32 | |
187 | ||
188 | /* There is no point aligning anything to a rounder boundary than this. */ | |
189 | ||
190 | #define BIGGEST_ALIGNMENT 64 | |
191 | ||
192 | /* Alignment of field after `int : 0' in a structure. */ | |
193 | ||
194 | #define EMPTY_FIELD_BOUNDARY 32 | |
195 | ||
f710504c | 196 | /* Alignment on even addresses for LARL instruction. */ |
9db1d521 HP |
197 | |
198 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) | |
199 | ||
200 | #define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) | |
201 | ||
202 | /* Define this if move instructions will actually fail to work when given | |
203 | unaligned data. */ | |
204 | ||
205 | #define STRICT_ALIGNMENT 0 | |
206 | ||
9db1d521 HP |
207 | /* Define target floating point format. */ |
208 | ||
209 | #undef TARGET_FLOAT_FORMAT | |
210 | #ifdef IEEE_FLOAT | |
211 | #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT | |
212 | #else | |
213 | #define TARGET_FLOAT_FORMAT IBM_FLOAT_FORMAT | |
214 | #endif | |
215 | ||
216 | /* Define if special allocation order desired. */ | |
217 | ||
218 | #define REG_ALLOC_ORDER \ | |
219 | { 1, 2, 3, 4, 5, 0, 14, 13, 12, 11, 10, 9, 8, 7, 6, \ | |
220 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
221 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
ff080aba | 222 | 15, 32, 33, 34 } |
9db1d521 HP |
223 | |
224 | /* Standard register usage. */ | |
225 | ||
994fe660 | 226 | #define INT_REGNO_P(N) ( (int)(N) >= 0 && (N) < 16 ) |
9db1d521 HP |
227 | #ifdef IEEE_FLOAT |
228 | #define FLOAT_REGNO_P(N) ( (N) >= 16 && (N) < 32 ) | |
229 | #else | |
230 | #define FLOAT_REGNO_P(N) ( (N) >= 16 && (N) < 20 ) | |
231 | #endif | |
232 | #define CC_REGNO_P(N) ( (N) == 33 ) | |
233 | ||
234 | /* Number of actual hardware registers. The hardware registers are | |
235 | assigned numbers for the compiler from 0 to just below | |
236 | FIRST_PSEUDO_REGISTER. | |
237 | All registers that the compiler knows about must be given numbers, | |
238 | even those that are not normally considered general registers. | |
239 | For the 390, we give the data registers numbers 0-15, | |
240 | and the floating point registers numbers 16-19. | |
241 | G5 and following have 16 IEEE floating point register, | |
242 | which get numbers 16-31. */ | |
243 | ||
4023fb28 UW |
244 | #define FIRST_PSEUDO_REGISTER 35 |
245 | ||
246 | /* Number of hardware registers that go into the DWARF-2 unwind info. | |
247 | If not defined, equals FIRST_PSEUDO_REGISTER. */ | |
248 | ||
249 | #define DWARF_FRAME_REGISTERS 34 | |
9db1d521 HP |
250 | |
251 | /* The following register have a fix usage | |
252 | GPR 12: GOT register points to the GOT, setup in prologue, | |
253 | GOT contains pointer to variables in shared libraries | |
254 | GPR 13: Base register setup in prologue to point to the | |
255 | literal table of each function | |
256 | GPR 14: Return registers holds the return address | |
257 | GPR 15: Stack pointer */ | |
258 | ||
5b43fed1 | 259 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM) |
9db1d521 HP |
260 | #define BASE_REGISTER 13 |
261 | #define RETURN_REGNUM 14 | |
262 | #define STACK_POINTER_REGNUM 15 | |
263 | ||
264 | #define FIXED_REGISTERS \ | |
265 | { 0, 0, 0, 0, \ | |
266 | 0, 0, 0, 0, \ | |
267 | 0, 0, 0, 0, \ | |
268 | 0, 1, 1, 1, \ | |
269 | 0, 0, 0, 0, \ | |
270 | 0, 0, 0, 0, \ | |
271 | 0, 0, 0, 0, \ | |
272 | 0, 0, 0, 0, \ | |
4023fb28 | 273 | 1, 1, 1 } |
9db1d521 HP |
274 | |
275 | /* 1 for registers not available across function calls. These must include | |
276 | the FIXED_REGISTERS and also any registers that can be used without being | |
277 | saved. | |
278 | The latter must include the registers where values are returned | |
279 | and the register where structure-value addresses are passed. */ | |
280 | ||
281 | #define CALL_USED_REGISTERS \ | |
282 | { 1, 1, 1, 1, \ | |
283 | 1, 1, 0, 0, \ | |
284 | 0, 0, 0, 0, \ | |
285 | 0, 1, 1, 1, \ | |
4023fb28 UW |
286 | 1, 1, 1, 1, \ |
287 | 1, 1, 1, 1, \ | |
288 | 1, 1, 1, 1, \ | |
289 | 1, 1, 1, 1, \ | |
290 | 1, 1, 1 } | |
291 | ||
292 | /* Like `CALL_USED_REGISTERS' except this macro doesn't require that | |
293 | the entire set of `FIXED_REGISTERS' be included. | |
294 | (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). */ | |
295 | ||
296 | #define CALL_REALLY_USED_REGISTERS \ | |
297 | { 1, 1, 1, 1, \ | |
9db1d521 | 298 | 1, 1, 0, 0, \ |
4023fb28 UW |
299 | 0, 0, 0, 0, \ |
300 | 0, 0, 0, 0, \ | |
9db1d521 HP |
301 | 1, 1, 1, 1, \ |
302 | 1, 1, 1, 1, \ | |
303 | 1, 1, 1, 1, \ | |
4023fb28 UW |
304 | 1, 1, 1, 1, \ |
305 | 1, 1, 1 } | |
9db1d521 | 306 | |
4023fb28 | 307 | /* Macro to conditionally modify fixed_regs/call_used_regs. */ |
9db1d521 HP |
308 | |
309 | #define CONDITIONAL_REGISTER_USAGE \ | |
310 | do \ | |
311 | { \ | |
4023fb28 UW |
312 | int i; \ |
313 | \ | |
9db1d521 HP |
314 | if (flag_pic) \ |
315 | { \ | |
316 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
317 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
318 | } \ | |
4023fb28 UW |
319 | if (TARGET_64BIT) \ |
320 | { \ | |
321 | for (i = 24; i < 32; i++) \ | |
322 | call_used_regs[i] = call_really_used_regs[i] = 0; \ | |
323 | } \ | |
324 | else \ | |
325 | { \ | |
326 | for (i = 18; i < 20; i++) \ | |
327 | call_used_regs[i] = call_really_used_regs[i] = 0; \ | |
328 | } \ | |
9db1d521 HP |
329 | } while (0) |
330 | ||
331 | /* The following register have a special usage | |
332 | GPR 11: Frame pointer if needed to point to automatic variables. | |
333 | GPR 32: In functions with more the 5 args this register | |
334 | points to that arguments, it is always eliminated | |
335 | with stack- or frame-pointer. | |
336 | GPR 33: Condition code 'register' */ | |
337 | ||
4023fb28 UW |
338 | #define HARD_FRAME_POINTER_REGNUM 11 |
339 | #define FRAME_POINTER_REGNUM 34 | |
9db1d521 HP |
340 | |
341 | #define ARG_POINTER_REGNUM 32 | |
342 | ||
343 | #define CC_REGNUM 33 | |
344 | ||
345 | /* We use the register %r0 to pass the static chain to a nested function. | |
346 | ||
347 | Note: It is assumed that this register is call-clobbered! | |
348 | We can't use any of the function-argument registers either, | |
349 | and register 1 is needed by the trampoline code, so we have | |
350 | no other choice but using this one ... */ | |
351 | ||
352 | #define STATIC_CHAIN_REGNUM 0 | |
353 | ||
354 | /* Return number of consecutive hard regs needed starting at reg REGNO | |
355 | to hold something of mode MODE. | |
356 | This is ordinarily the length in words of a value of mode MODE | |
357 | but can be less for certain modes in special long registers. */ | |
358 | ||
359 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
360 | (FLOAT_REGNO_P(REGNO)? \ | |
361 | (GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \ | |
362 | INT_REGNO_P(REGNO)? \ | |
363 | ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1) / UNITS_PER_WORD) : \ | |
364 | 1) | |
365 | ||
366 | /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. | |
367 | The gprs can hold QI, HI, SI, SF, DF, SC and DC. | |
368 | Even gprs can hold DI. | |
369 | The floating point registers can hold DF, SF, DC and SC. */ | |
370 | ||
371 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
372 | (FLOAT_REGNO_P(REGNO)? \ | |
373 | (GET_MODE_CLASS(MODE) == MODE_FLOAT || \ | |
4023fb28 UW |
374 | GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT || \ |
375 | (MODE) == SImode || (MODE) == DImode) : \ | |
9db1d521 | 376 | INT_REGNO_P(REGNO)? \ |
f314b9b1 | 377 | (HARD_REGNO_NREGS(REGNO, MODE) == 1 || !((REGNO) & 1)) : \ |
9db1d521 HP |
378 | CC_REGNO_P(REGNO)? \ |
379 | GET_MODE_CLASS (MODE) == MODE_CC : \ | |
380 | 0) | |
381 | ||
382 | /* Value is 1 if it is a good idea to tie two pseudo registers when one has | |
383 | mode MODE1 and one has mode MODE2. | |
384 | If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, | |
385 | for any hard reg, then this must be 0 for correct output. */ | |
386 | ||
387 | #define MODES_TIEABLE_P(MODE1, MODE2) \ | |
388 | (((MODE1) == SFmode || (MODE1) == DFmode) \ | |
389 | == ((MODE2) == SFmode || (MODE2) == DFmode)) | |
390 | ||
4023fb28 UW |
391 | /* If defined, gives a class of registers that cannot be used as the |
392 | operand of a SUBREG that changes the mode of the object illegally. */ | |
393 | ||
394 | #define CLASS_CANNOT_CHANGE_MODE FP_REGS | |
395 | ||
396 | /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */ | |
397 | ||
398 | #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \ | |
399 | (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)) | |
9db1d521 | 400 | |
9db1d521 HP |
401 | /* This is an array of structures. Each structure initializes one pair |
402 | of eliminable registers. The "from" register number is given first, | |
403 | followed by "to". Eliminations of the same "from" register are listed | |
404 | in order of preference. */ | |
405 | ||
406 | #define ELIMINABLE_REGS \ | |
407 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
4023fb28 | 408 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ |
9db1d521 | 409 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ |
4023fb28 | 410 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} |
9db1d521 HP |
411 | |
412 | #define CAN_ELIMINATE(FROM, TO) (1) | |
413 | ||
414 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ | |
415 | { if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ | |
416 | { (OFFSET) = 0; } \ | |
4023fb28 UW |
417 | else if ((FROM) == FRAME_POINTER_REGNUM \ |
418 | && (TO) == HARD_FRAME_POINTER_REGNUM) \ | |
419 | { (OFFSET) = 0; } \ | |
420 | else if ((FROM) == ARG_POINTER_REGNUM \ | |
421 | && (TO) == HARD_FRAME_POINTER_REGNUM) \ | |
9db1d521 HP |
422 | { (OFFSET) = s390_arg_frame_offset (); } \ |
423 | else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ | |
424 | { (OFFSET) = s390_arg_frame_offset (); } \ | |
b3656137 KG |
425 | else \ |
426 | abort(); \ | |
9db1d521 HP |
427 | } |
428 | ||
429 | #define CAN_DEBUG_WITHOUT_FP | |
430 | ||
431 | /* Value should be nonzero if functions must have frame pointers. | |
432 | Zero means the frame pointer need not be set up (and parms may be | |
433 | accessed via the stack pointer) in functions that seem suitable. | |
434 | This is computed in `reload', in reload1.c. */ | |
435 | ||
436 | #define FRAME_POINTER_REQUIRED 0 | |
437 | ||
438 | /* Define the classes of registers for register constraints in the | |
439 | machine description. Also define ranges of constants. | |
440 | ||
441 | One of the classes must always be named ALL_REGS and include all hard regs. | |
442 | If there is more than one class, another class must be named NO_REGS | |
443 | and contain no registers. | |
444 | ||
445 | The name GENERAL_REGS must be the name of a class (or an alias for | |
446 | another name such as ALL_REGS). This is the class of registers | |
447 | that is allowed by "g" or "r" in a register constraint. | |
448 | Also, registers outside this class are allocated only when | |
449 | instructions express preferences for them. | |
450 | ||
451 | The classes must be numbered in nondecreasing order; that is, | |
452 | a larger-numbered class must never be contained completely | |
453 | in a smaller-numbered class. | |
454 | ||
455 | For any two classes, it is very desirable that there be another | |
456 | class that represents their union. */ | |
457 | ||
458 | /*#define SMALL_REGISTER_CLASSES 1*/ | |
459 | ||
460 | enum reg_class | |
461 | { | |
462 | NO_REGS, ADDR_REGS, GENERAL_REGS, | |
4023fb28 UW |
463 | FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, |
464 | ALL_REGS, LIM_REG_CLASSES | |
9db1d521 HP |
465 | }; |
466 | ||
467 | #define N_REG_CLASSES (int) LIM_REG_CLASSES | |
468 | ||
469 | /* Give names of register classes as strings for dump file. */ | |
470 | ||
471 | #define REG_CLASS_NAMES \ | |
4023fb28 UW |
472 | { "NO_REGS", "ADDR_REGS", "GENERAL_REGS", \ |
473 | "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" } | |
9db1d521 HP |
474 | |
475 | /* Define which registers fit in which classes. This is an initializer for | |
476 | a vector of HARD_REG_SET of length N_REG_CLASSES. | |
477 | G5 and latter have 16 register and support IEEE floating point operations. */ | |
478 | ||
479 | #define REG_CLASS_CONTENTS \ | |
480 | { \ | |
481 | { 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
4023fb28 UW |
482 | { 0x0000fffe, 0x00000005 }, /* ADDR_REGS */ \ |
483 | { 0x0000ffff, 0x00000005 }, /* GENERAL_REGS */ \ | |
9db1d521 | 484 | { 0xffff0000, 0x00000000 }, /* FP_REGS */ \ |
4023fb28 UW |
485 | { 0xfffffffe, 0x00000005 }, /* ADDR_FP_REGS */ \ |
486 | { 0xffffffff, 0x00000005 }, /* GENERAL_FP_REGS */ \ | |
487 | { 0xffffffff, 0x00000007 }, /* ALL_REGS */ \ | |
9db1d521 HP |
488 | } |
489 | ||
490 | ||
491 | /* The same information, inverted: | |
492 | Return the class number of the smallest class containing | |
493 | reg number REGNO. This could be a conditional expression | |
494 | or could index an array. */ | |
495 | ||
496 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) | |
497 | ||
0139adca | 498 | extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; /* smalled class containing REGNO */ |
9db1d521 HP |
499 | |
500 | /* The class value for index registers, and the one for base regs. */ | |
501 | ||
502 | #define INDEX_REG_CLASS ADDR_REGS | |
503 | #define BASE_REG_CLASS ADDR_REGS | |
504 | ||
505 | /* Get reg_class from a letter such as appears in the machine description. */ | |
506 | ||
507 | #define REG_CLASS_FROM_LETTER(C) \ | |
508 | ((C) == 'a' ? ADDR_REGS : \ | |
509 | (C) == 'd' ? GENERAL_REGS : \ | |
510 | (C) == 'f' ? FP_REGS : NO_REGS) | |
511 | ||
512 | /* The letters I, J, K, L and M in a register constraint string can be used | |
513 | to stand for particular ranges of immediate operands. | |
514 | This macro defines what the ranges are. | |
515 | C is the letter, and VALUE is a constant value. | |
516 | Return 1 if VALUE is in the range specified by C. */ | |
517 | ||
518 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ | |
519 | ((C) == 'I' ? (unsigned long) (VALUE) < 256 : \ | |
520 | (C) == 'J' ? (unsigned long) (VALUE) < 4096 : \ | |
521 | (C) == 'K' ? (VALUE) >= -32768 && (VALUE) < 32768 : \ | |
522 | (C) == 'L' ? (unsigned long) (VALUE) < 65536 : 0) | |
523 | ||
524 | /* Similar, but for floating constants, and defining letters G and H. | |
525 | Here VALUE is the CONST_DOUBLE rtx itself. */ | |
526 | ||
527 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1 | |
528 | ||
529 | /* 'Q' means a memory-reference for a S-type operand. */ | |
530 | ||
531 | #define EXTRA_CONSTRAINT(OP, C) \ | |
ccfc6cc8 | 532 | ((C) == 'Q' ? q_constraint (OP) : \ |
9db1d521 HP |
533 | (C) == 'S' ? larl_operand (OP, GET_MODE (OP)) : 0) |
534 | ||
ccfc6cc8 UW |
535 | #define EXTRA_MEMORY_CONSTRAINT(C) ((C) == 'Q') |
536 | ||
9db1d521 HP |
537 | /* Given an rtx X being reloaded into a reg required to be in class CLASS, |
538 | return the class of reg to actually use. In general this is just CLASS; | |
539 | but on some machines in some cases it is preferable to use a more | |
540 | restrictive class. */ | |
541 | ||
4023fb28 UW |
542 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ |
543 | s390_preferred_reload_class ((X), (CLASS)) | |
9db1d521 HP |
544 | |
545 | /* Return the maximum number of consecutive registers needed to represent | |
546 | mode MODE in a register of class CLASS. */ | |
547 | ||
548 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
549 | ((CLASS) == FP_REGS ? \ | |
550 | (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \ | |
551 | (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
552 | ||
f3e9edff UW |
553 | /* We need a secondary reload when loading a PLUS which is |
554 | not a valid operand for LOAD ADDRESS. */ | |
555 | ||
556 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ | |
557 | s390_secondary_input_reload_class ((CLASS), (MODE), (IN)) | |
558 | ||
9db1d521 HP |
559 | /* If we are copying between FP registers and anything else, we need a memory |
560 | location. */ | |
561 | ||
562 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ | |
563 | ((CLASS1) != (CLASS2) && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS)) | |
564 | ||
565 | /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit | |
d65f7478 | 566 | because the movsi and movsf patterns don't handle r/f moves. */ |
9db1d521 HP |
567 | |
568 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
569 | (GET_MODE_BITSIZE (MODE) < 32 \ | |
570 | ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
571 | : MODE) | |
572 | ||
573 | ||
574 | /* A C expression whose value is nonzero if pseudos that have been | |
575 | assigned to registers of class CLASS would likely be spilled | |
576 | because registers of CLASS are needed for spill registers. | |
577 | ||
578 | The default value of this macro returns 1 if CLASS has exactly one | |
579 | register and zero otherwise. On most machines, this default | |
580 | should be used. Only define this macro to some other expression | |
581 | if pseudo allocated by `local-alloc.c' end up in memory because | |
582 | their hard registers were needed for spill registers. If this | |
583 | macro returns nonzero for those classes, those pseudos will only | |
584 | be allocated by `global.c', which knows how to reallocate the | |
585 | pseudo to another register. If there would not be another | |
586 | register available for reallocation, you should not change the | |
587 | definition of this macro since the only effect of such a | |
588 | definition would be to slow down register allocation. */ | |
589 | ||
590 | /* Stack layout; function entry, exit and calling. */ | |
591 | ||
4023fb28 UW |
592 | /* The return address of the current frame is retrieved |
593 | from the initial value of register RETURN_REGNUM. | |
594 | For frames farther back, we use the stack slot where | |
595 | the corresponding RETURN_REGNUM register was saved. */ | |
596 | ||
597 | #define DYNAMIC_CHAIN_ADDRESS(FRAME) \ | |
598 | ((FRAME) != hard_frame_pointer_rtx ? (FRAME) : \ | |
599 | plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET)) | |
600 | ||
601 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
602 | ((COUNT) == 0 ? get_hard_reg_initial_val (Pmode, RETURN_REGNUM) : \ | |
603 | gen_rtx_MEM (Pmode, \ | |
604 | memory_address (Pmode, \ | |
605 | plus_constant (DYNAMIC_CHAIN_ADDRESS ((FRAME)), \ | |
606 | RETURN_REGNUM * UNITS_PER_WORD)))) | |
9db1d521 HP |
607 | |
608 | /* The following macros will turn on dwarf2 exception hndling | |
609 | Other code location for this exception handling are | |
610 | in s390.md (eh_return insn) and in linux.c in the prologue. */ | |
611 | ||
612 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM) | |
613 | ||
614 | /* We have 31 bit mode. */ | |
615 | ||
58d10f89 | 616 | #define MASK_RETURN_ADDR (TARGET_64BIT ? GEN_INT (-1) : GEN_INT (0x7fffffff)) |
9db1d521 | 617 | |
4023fb28 UW |
618 | /* The offset from the incoming value of %sp to the top of the stack frame |
619 | for the current function. */ | |
620 | ||
621 | #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET | |
622 | ||
9db1d521 HP |
623 | /* Location, from where return address to load. */ |
624 | ||
625 | #define DWARF_FRAME_RETURN_COLUMN 14 | |
626 | ||
627 | /* Describe how we implement __builtin_eh_return. */ | |
628 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM) | |
629 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) | |
630 | #define EH_RETURN_HANDLER_RTX \ | |
f314b9b1 UW |
631 | gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, \ |
632 | TARGET_64BIT? -48 : -40)) | |
9db1d521 HP |
633 | |
634 | /* Define this if pushing a word on the stack makes the stack pointer a | |
635 | smaller address. */ | |
636 | ||
637 | #define STACK_GROWS_DOWNWARD | |
638 | ||
639 | /* Define this if the nominal address of the stack frame is at the | |
640 | high-address end of the local variables; that is, each additional local | |
641 | variable allocated goes at a more negative offset in the frame. */ | |
642 | ||
643 | /* #define FRAME_GROWS_DOWNWARD */ | |
644 | ||
645 | /* Offset from stack-pointer to first location of outgoing args. */ | |
646 | ||
647 | #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96) | |
648 | ||
649 | /* Offset within stack frame to start allocating local variables at. | |
650 | If FRAME_GROWS_DOWNWARD, this is the offset to the END of the | |
651 | first local allocated. Otherwise, it is the offset to the BEGINNING | |
652 | of the first local allocated. */ | |
653 | ||
654 | #define STARTING_FRAME_OFFSET \ | |
655 | (STACK_POINTER_OFFSET + current_function_outgoing_args_size) | |
656 | ||
657 | #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0 | |
658 | ||
659 | /* If we generate an insn to push BYTES bytes, this says how many the stack | |
660 | pointer really advances by. On S/390, we have no push instruction. */ | |
661 | ||
662 | /* #define PUSH_ROUNDING(BYTES) */ | |
663 | ||
664 | /* Accumulate the outgoing argument count so we can request the right | |
665 | DSA size and determine stack offset. */ | |
666 | ||
667 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
668 | ||
669 | /* Offset from the stack pointer register to an item dynamically | |
670 | allocated on the stack, e.g., by `alloca'. | |
671 | ||
672 | The default value for this macro is `STACK_POINTER_OFFSET' plus the | |
673 | length of the outgoing arguments. The default is correct for most | |
674 | machines. See `function.c' for details. */ | |
675 | #define STACK_DYNAMIC_OFFSET(FUNDECL) (STARTING_FRAME_OFFSET) | |
676 | ||
677 | /* Offset of first parameter from the argument pointer register value. | |
678 | On the S/390, we define the argument pointer to the start of the fixed | |
679 | area. */ | |
680 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
681 | ||
682 | /* Define this if stack space is still allocated for a parameter passed | |
683 | in a register. The value is the number of bytes allocated to this | |
684 | area. */ | |
685 | /* #define REG_PARM_STACK_SPACE(FNDECL) 32 */ | |
686 | ||
687 | /* Define this if the above stack space is to be considered part of the | |
688 | space allocated by the caller. */ | |
689 | /* #define OUTGOING_REG_PARM_STACK_SPACE */ | |
690 | ||
691 | /* 1 if N is a possible register number for function argument passing. | |
692 | On S390, general registers 2 - 6 and floating point register 0 and 2 | |
693 | are used in this way. */ | |
694 | ||
695 | #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \ | |
696 | (N) == 16 || (N) == 17) | |
697 | ||
698 | /* Define a data type for recording info about an argument list during | |
699 | the scan of that argument list. This data type should hold all | |
700 | necessary information about the function itself and about the args | |
701 | processed so far, enough to enable macros such as FUNCTION_ARG to | |
702 | determine where the next arg should go. */ | |
703 | ||
704 | typedef struct s390_arg_structure | |
705 | { | |
706 | int gprs; /* gpr so far */ | |
707 | int fprs; /* fpr so far */ | |
708 | } | |
709 | CUMULATIVE_ARGS; | |
710 | ||
711 | ||
712 | /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to | |
713 | a function whose data type is FNTYPE. | |
714 | For a library call, FNTYPE is 0. */ | |
715 | ||
716 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN) \ | |
717 | ((CUM).gprs=0, (CUM).fprs=0) | |
718 | ||
719 | /* Update the data in CUM to advance over an argument of mode MODE and | |
720 | data type TYPE. (TYPE is null for libcalls where that information | |
721 | may not be available.) */ | |
722 | ||
723 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ | |
994fe660 | 724 | s390_function_arg_advance (&CUM, MODE, TYPE, NAMED) |
9db1d521 HP |
725 | |
726 | /* Define where to put the arguments to a function. Value is zero to push | |
727 | the argument on the stack, or a hard register in which to store the | |
728 | argument. */ | |
729 | ||
730 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ | |
994fe660 | 731 | s390_function_arg (&CUM, MODE, TYPE, NAMED) |
9db1d521 HP |
732 | |
733 | /* Define where to expect the arguments of a function. Value is zero, if | |
734 | the argument is on the stack, or a hard register in which the argument | |
735 | is stored. It is the same like FUNCTION_ARG, except for unnamed args | |
736 | That means, that all in case of varargs used, the arguments are expected | |
737 | from the stack. | |
738 | S/390 has already space on the stack for args coming in registers, | |
739 | they are pushed in prologue, if needed. */ | |
740 | ||
741 | ||
742 | /* Define the `__builtin_va_list' type. */ | |
743 | ||
744 | #define BUILD_VA_LIST_TYPE(VALIST) \ | |
745 | (VALIST) = s390_build_va_list () | |
746 | ||
747 | /* Implement `va_start' for varargs and stdarg. */ | |
748 | ||
e5faf155 ZW |
749 | #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ |
750 | s390_va_start (valist, nextarg) | |
9db1d521 HP |
751 | |
752 | /* Implement `va_arg'. */ | |
753 | ||
754 | #define EXPAND_BUILTIN_VA_ARG(valist, type) \ | |
755 | s390_va_arg (valist, type) | |
756 | ||
757 | /* For an arg passed partly in registers and partly in memory, this is the | |
758 | number of registers used. For args passed entirely in registers or | |
759 | entirely in memory, zero. */ | |
760 | ||
761 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 | |
762 | ||
763 | ||
764 | /* Define if returning from a function call automatically pops the | |
765 | arguments described by the number-of-args field in the call. */ | |
766 | ||
767 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 | |
768 | ||
769 | ||
770 | /* Define how to find the value returned by a function. VALTYPE is the | |
771 | data type of the value (as a tree). | |
772 | If the precise function being called is known, FUNC is its FUNCTION_DECL; | |
773 | otherwise, FUNC is 15. */ | |
774 | ||
775 | #define RET_REG(MODE) ((GET_MODE_CLASS (MODE) == MODE_INT \ | |
776 | || TARGET_SOFT_FLOAT ) ? 2 : 16) | |
777 | ||
778 | ||
779 | /* for structs the address is passed, and the Callee makes a | |
780 | copy, only if needed */ | |
781 | ||
782 | #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ | |
783 | s390_function_arg_pass_by_reference (MODE, TYPE) | |
784 | ||
785 | ||
786 | /* Register 2 (and 3) for integral values | |
787 | or floating point register 0 (and 2) for fp values are used. */ | |
788 | ||
789 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ | |
790 | gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \ | |
791 | && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \ | |
792 | || POINTER_TYPE_P (VALTYPE) \ | |
793 | ? word_mode : TYPE_MODE (VALTYPE), \ | |
794 | TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_HARD_FLOAT ? 16 : 2) | |
795 | ||
796 | /* Define how to find the value returned by a library function assuming | |
797 | the value has mode MODE. */ | |
798 | ||
799 | #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, RET_REG (MODE)) | |
800 | ||
801 | /* 1 if N is a possible register number for a function value. */ | |
802 | ||
803 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16) | |
804 | ||
805 | /* The definition of this macro implies that there are cases where | |
806 | a scalar value cannot be returned in registers. */ | |
807 | ||
f314b9b1 UW |
808 | #define RETURN_IN_MEMORY(type) \ |
809 | (TYPE_MODE (type) == BLKmode || \ | |
810 | GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_INT || \ | |
811 | GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT) | |
9db1d521 HP |
812 | |
813 | /* Mode of stack savearea. | |
814 | FUNCTION is VOIDmode because calling convention maintains SP. | |
815 | BLOCK needs Pmode for SP. | |
816 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ | |
817 | ||
818 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
819 | (LEVEL == SAVE_FUNCTION ? VOIDmode \ | |
820 | : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? TImode : DImode) : Pmode) | |
821 | ||
822 | /* Structure value address is passed as invisible first argument (gpr 2). */ | |
823 | ||
824 | #define STRUCT_VALUE 0 | |
825 | ||
826 | /* This macro definition sets up a default value for `main' to return. */ | |
827 | ||
828 | #define DEFAULT_MAIN_RETURN c_expand_return (integer_zero_node) | |
829 | ||
830 | /* Length in units of the trampoline for entering a nested function. */ | |
831 | ||
832 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 36 : 20) | |
833 | ||
834 | /* Initialize the dynamic part of trampoline. */ | |
835 | ||
836 | #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \ | |
837 | s390_initialize_trampoline ((ADDR), (FNADDR), (CXT)) | |
838 | ||
839 | /* Template for constant part of trampoline. */ | |
840 | ||
841 | #define TRAMPOLINE_TEMPLATE(FILE) \ | |
842 | s390_trampoline_template (FILE) | |
843 | ||
844 | /* Output assembler code to FILE to increment profiler label # LABELNO | |
845 | for profiling a function entry. */ | |
846 | ||
847 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
4023fb28 | 848 | s390_function_profiler ((FILE), ((LABELNO))) |
9db1d521 | 849 | |
c52a375d | 850 | #define PROFILE_BEFORE_PROLOGUE 1 |
9db1d521 | 851 | |
9db1d521 HP |
852 | /* Define EXIT_IGNORE_STACK if, when returning from a function, the stack |
853 | pointer does not matter (provided there is a frame pointer). */ | |
854 | ||
855 | #define EXIT_IGNORE_STACK 1 | |
856 | ||
857 | /* Addressing modes, and classification of registers for them. */ | |
858 | ||
859 | /* #define HAVE_POST_INCREMENT */ | |
860 | /* #define HAVE_POST_DECREMENT */ | |
861 | ||
862 | /* #define HAVE_PRE_DECREMENT */ | |
863 | /* #define HAVE_PRE_INCREMENT */ | |
864 | ||
865 | /* These assume that REGNO is a hard or pseudo reg number. They give | |
866 | nonzero only if REGNO is a hard reg of the suitable class or a pseudo | |
867 | reg currently allocated to a suitable hard reg. | |
868 | These definitions are NOT overridden anywhere. */ | |
869 | ||
4023fb28 UW |
870 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ |
871 | (((REGNO) < FIRST_PSEUDO_REGISTER \ | |
872 | && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \ | |
9db1d521 HP |
873 | || (reg_renumber[REGNO] > 0 && reg_renumber[REGNO] < 16)) |
874 | ||
875 | #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) | |
876 | ||
877 | #define REGNO_OK_FOR_DATA_P(REGNO) \ | |
878 | ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16) | |
879 | ||
880 | #define REGNO_OK_FOR_FP_P(REGNO) \ | |
994fe660 | 881 | FLOAT_REGNO_P (REGNO) |
9db1d521 HP |
882 | |
883 | /* Now macros that check whether X is a register and also, | |
884 | strictly, whether it is in a specified class. */ | |
885 | ||
886 | /* 1 if X is a data register. */ | |
887 | ||
888 | #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X))) | |
889 | ||
890 | /* 1 if X is an fp register. */ | |
891 | ||
892 | #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) | |
893 | ||
894 | /* 1 if X is an address register. */ | |
895 | ||
896 | #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X))) | |
897 | ||
898 | /* Maximum number of registers that can appear in a valid memory address. */ | |
899 | ||
900 | #define MAX_REGS_PER_ADDRESS 2 | |
901 | ||
902 | /* Recognize any constant value that is a valid address. */ | |
903 | ||
904 | #define CONSTANT_ADDRESS_P(X) 0 | |
905 | ||
906 | #define SYMBOLIC_CONST(X) \ | |
907 | (GET_CODE (X) == SYMBOL_REF \ | |
908 | || GET_CODE (X) == LABEL_REF \ | |
909 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
910 | ||
911 | /* General operand is everything except SYMBOL_REF, CONST and CONST_DOUBLE | |
912 | they have to be forced to constant pool | |
913 | CONST_INT have to be forced into constant pool, if greater than | |
914 | 64k. Depending on the insn they have to be force into constant pool | |
915 | for smaller value; in this case we have to work with nonimmediate operand. */ | |
916 | ||
917 | #define LEGITIMATE_PIC_OPERAND_P(X) \ | |
918 | legitimate_pic_operand_p (X) | |
919 | ||
920 | /* Nonzero if the constant value X is a legitimate general operand. | |
921 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
922 | ||
923 | #define LEGITIMATE_CONSTANT_P(X) \ | |
924 | legitimate_constant_p (X) | |
925 | ||
926 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check | |
927 | its validity for a certain class. We have two alternate definitions | |
928 | for each of them. The usual definition accepts all pseudo regs; the | |
929 | other rejects them all. The symbol REG_OK_STRICT causes the latter | |
930 | definition to be used. | |
931 | ||
932 | Most source files want to accept pseudo regs in the hope that they will | |
933 | get allocated to the class that the insn wants them to be in. | |
934 | Some source files that are used after register allocation | |
935 | need to be strict. */ | |
936 | ||
937 | /* | |
938 | * Nonzero if X is a hard reg that can be used as an index or if it is | |
939 | * a pseudo reg. | |
940 | */ | |
941 | ||
4023fb28 UW |
942 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ |
943 | ((GET_MODE (X) == Pmode) && \ | |
944 | ((REGNO (X) >= FIRST_PSEUDO_REGISTER) \ | |
945 | || REGNO_REG_CLASS (REGNO (X)) == ADDR_REGS)) | |
9db1d521 HP |
946 | |
947 | /* Nonzero if X is a hard reg that can be used as a base reg or if it is | |
948 | a pseudo reg. */ | |
949 | ||
950 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) | |
951 | ||
952 | /* Nonzero if X is a hard reg that can be used as an index. */ | |
953 | ||
954 | #define REG_OK_FOR_INDEX_STRICT_P(X) \ | |
955 | ((GET_MODE (X) == Pmode) && (REGNO_OK_FOR_INDEX_P (REGNO (X)))) | |
956 | ||
957 | /* Nonzero if X is a hard reg that can be used as a base reg. */ | |
958 | ||
959 | #define REG_OK_FOR_BASE_STRICT_P(X) \ | |
960 | ((GET_MODE (X) == Pmode) && (REGNO_OK_FOR_BASE_P (REGNO (X)))) | |
961 | ||
962 | ||
963 | #ifndef REG_OK_STRICT | |
964 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X) | |
965 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X) | |
966 | #else | |
967 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X) | |
968 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X) | |
969 | #endif | |
970 | ||
971 | ||
972 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a | |
973 | valid memory address for an instruction. | |
974 | The MODE argument is the machine mode for the MEM expression | |
975 | that wants to use this address. | |
976 | ||
977 | The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, | |
978 | except for CONSTANT_ADDRESS_P which is actually machine-independent. */ | |
979 | ||
980 | #ifdef REG_OK_STRICT | |
981 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
982 | { \ | |
983 | if (legitimate_address_p (MODE, X, 1)) \ | |
984 | goto ADDR; \ | |
985 | } | |
986 | #else | |
987 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
988 | { \ | |
989 | if (legitimate_address_p (MODE, X, 0)) \ | |
990 | goto ADDR; \ | |
991 | } | |
992 | #endif | |
993 | ||
994 | ||
995 | /* S/390 has no mode dependent addresses. */ | |
996 | ||
997 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) | |
998 | ||
999 | /* Try machine-dependent ways of modifying an illegitimate address | |
1000 | to be legitimate. If we find one, return the new, valid address. | |
1001 | This macro is used in only one place: `memory_address' in explow.c. */ | |
1002 | ||
1003 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ | |
1004 | { \ | |
1005 | (X) = legitimize_address (X, OLDX, MODE); \ | |
1006 | if (memory_address_p (MODE, X)) \ | |
1007 | goto WIN; \ | |
1008 | } | |
1009 | ||
1010 | /* Specify the machine mode that this machine uses for the index in the | |
1011 | tablejump instruction. */ | |
1012 | ||
1013 | #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) | |
1014 | ||
1015 | /* Define this if the tablejump instruction expects the table to contain | |
1016 | offsets from the address of the table. | |
1017 | Do not define this if the table should contain absolute addresses. */ | |
1018 | ||
1019 | /* #define CASE_VECTOR_PC_RELATIVE */ | |
1020 | ||
1021 | /* Load from integral MODE < SI from memory into register makes sign_extend | |
1022 | or zero_extend | |
1023 | In our case sign_extension happens for Halfwords, other no extension. */ | |
1024 | ||
1025 | #define LOAD_EXTEND_OP(MODE) \ | |
1026 | (TARGET_64BIT ? ((MODE) == QImode ? ZERO_EXTEND : \ | |
1027 | (MODE) == HImode ? SIGN_EXTEND : NIL) \ | |
1028 | : ((MODE) == HImode ? SIGN_EXTEND : NIL)) | |
1029 | ||
9db1d521 HP |
1030 | /* Define this if fixuns_trunc is the same as fix_trunc. */ |
1031 | ||
1032 | /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */ | |
1033 | ||
1034 | /* We use "unsigned char" as default. */ | |
1035 | ||
1036 | #define DEFAULT_SIGNED_CHAR 0 | |
1037 | ||
33b679d1 UW |
1038 | /* The maximum number of bytes that a single instruction can move quickly |
1039 | between memory and registers or between two memory locations. */ | |
9db1d521 | 1040 | |
33b679d1 UW |
1041 | #define MOVE_MAX (TARGET_64BIT ? 16 : 8) |
1042 | #define MAX_MOVE_MAX 16 | |
1043 | ||
1044 | /* Determine whether to use move_by_pieces or block move insn. */ | |
1045 | ||
1046 | #define MOVE_BY_PIECES_P(SIZE, ALIGN) \ | |
1047 | ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ | |
1048 | || (TARGET_64BIT && (SIZE) == 8) ) | |
1049 | ||
1050 | /* Determine whether to use clear_by_pieces or block clear insn. */ | |
1051 | ||
1052 | #define CLEAR_BY_PIECES_P(SIZE, ALIGN) \ | |
1053 | ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ | |
1054 | || (TARGET_64BIT && (SIZE) == 8) ) | |
9db1d521 | 1055 | |
9db1d521 HP |
1056 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
1057 | ||
1058 | #define SLOW_BYTE_ACCESS 1 | |
1059 | ||
1060 | /* Define if shifts truncate the shift count which implies one can omit | |
1061 | a sign-extension or zero-extension of a shift count. */ | |
1062 | ||
1063 | /* #define SHIFT_COUNT_TRUNCATED */ | |
1064 | ||
1065 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1066 | is done just by pretending it is already truncated. */ | |
1067 | ||
1068 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1069 | ||
1070 | /* We assume that the store-condition-codes instructions store 0 for false | |
1071 | and some other value for true. This is the value stored for true. */ | |
1072 | ||
1073 | /* #define STORE_FLAG_VALUE -1 */ | |
1074 | ||
9db1d521 HP |
1075 | /* Don't perform CSE on function addresses. */ |
1076 | ||
1077 | #define NO_FUNCTION_CSE | |
1078 | ||
1079 | /* Specify the machine mode that pointers have. | |
1080 | After generation of rtl, the compiler makes no further distinction | |
1081 | between pointers and any other objects of this machine mode. */ | |
1082 | ||
994fe660 | 1083 | #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode)) |
9db1d521 HP |
1084 | |
1085 | /* A function address in a call instruction is a byte address (for | |
1086 | indexing purposes) so give the MEM rtx a byte's mode. */ | |
1087 | ||
1088 | #define FUNCTION_MODE QImode | |
1089 | ||
1090 | ||
1091 | /* A part of a C `switch' statement that describes the relative costs | |
1092 | of constant RTL expressions. It must contain `case' labels for | |
1093 | expression codes `const_int', `const', `symbol_ref', `label_ref' | |
1094 | and `const_double'. Each case must ultimately reach a `return' | |
1095 | statement to return the relative cost of the use of that kind of | |
1096 | constant value in an expression. The cost may depend on the | |
1097 | precise value of the constant, which is available for examination | |
1098 | in X, and the rtx code of the expression in which it is contained, | |
1099 | found in OUTER_CODE. | |
1100 | ||
1101 | CODE is the expression code--redundant, since it can be obtained | |
1102 | with `GET_CODE (X)'. */ | |
1103 | /* Force_const_mem does not work out of reload, because the saveable_obstack | |
1104 | is set to reload_obstack, which does not live long enough. | |
1105 | Because of this we cannot use force_const_mem in addsi3. | |
1106 | This leads to problems with gen_add2_insn with a constant greater | |
d65f7478 | 1107 | than a short. Because of that we give an addition of greater |
9db1d521 HP |
1108 | constants a cost of 3 (reload1.c 10096). */ |
1109 | ||
1110 | ||
1111 | #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ | |
1112 | case CONST: \ | |
1113 | if ((GET_CODE (XEXP (RTX, 0)) == MINUS) && \ | |
1114 | (GET_CODE (XEXP (XEXP (RTX, 0), 1)) != CONST_INT)) \ | |
1115 | return 1000; \ | |
1116 | case CONST_INT: \ | |
1117 | if ((OUTER_CODE == PLUS) && \ | |
1118 | ((INTVAL (RTX) > 32767) || \ | |
1119 | (INTVAL (RTX) < -32768))) \ | |
f314b9b1 | 1120 | return COSTS_N_INSNS (3); \ |
9db1d521 HP |
1121 | case LABEL_REF: \ |
1122 | case SYMBOL_REF: \ | |
1123 | case CONST_DOUBLE: \ | |
f314b9b1 | 1124 | return 0; \ |
9db1d521 HP |
1125 | |
1126 | ||
1127 | /* Like `CONST_COSTS' but applies to nonconstant RTL expressions. | |
1128 | This can be used, for example, to indicate how costly a multiply | |
1129 | instruction is. In writing this macro, you can use the construct | |
1130 | `COSTS_N_INSNS (N)' to specify a cost equal to N fast | |
1131 | instructions. OUTER_CODE is the code of the expression in which X | |
1132 | is contained. | |
1133 | ||
1134 | This macro is optional; do not define it if the default cost | |
1135 | assumptions are adequate for the target machine. */ | |
1136 | ||
1137 | #define RTX_COSTS(X, CODE, OUTER_CODE) \ | |
1138 | case ASHIFT: \ | |
1139 | case ASHIFTRT: \ | |
1140 | case LSHIFTRT: \ | |
1141 | case PLUS: \ | |
1142 | case AND: \ | |
1143 | case IOR: \ | |
1144 | case XOR: \ | |
1145 | case MINUS: \ | |
1146 | case NEG: \ | |
1147 | case NOT: \ | |
dea09b1b | 1148 | return COSTS_N_INSNS (1); \ |
9db1d521 HP |
1149 | case MULT: \ |
1150 | if (GET_MODE (XEXP (X, 0)) == DImode) \ | |
dea09b1b UW |
1151 | return COSTS_N_INSNS (40); \ |
1152 | else \ | |
1153 | return COSTS_N_INSNS (7); \ | |
9db1d521 HP |
1154 | case DIV: \ |
1155 | case UDIV: \ | |
1156 | case MOD: \ | |
1157 | case UMOD: \ | |
dea09b1b | 1158 | return COSTS_N_INSNS (33); |
9db1d521 HP |
1159 | |
1160 | ||
1161 | /* An expression giving the cost of an addressing mode that contains | |
1162 | ADDRESS. If not defined, the cost is computed from the ADDRESS | |
1163 | expression and the `CONST_COSTS' values. | |
1164 | ||
1165 | For most CISC machines, the default cost is a good approximation | |
1166 | of the true cost of the addressing mode. However, on RISC | |
1167 | machines, all instructions normally have the same length and | |
1168 | execution time. Hence all addresses will have equal costs. | |
1169 | ||
1170 | In cases where more than one form of an address is known, the form | |
1171 | with the lowest cost will be used. If multiple forms have the | |
1172 | same, lowest, cost, the one that is the most complex will be used. | |
1173 | ||
1174 | For example, suppose an address that is equal to the sum of a | |
1175 | register and a constant is used twice in the same basic block. | |
1176 | When this macro is not defined, the address will be computed in a | |
1177 | register and memory references will be indirect through that | |
1178 | register. On machines where the cost of the addressing mode | |
1179 | containing the sum is no higher than that of a simple indirect | |
1180 | reference, this will produce an additional instruction and | |
1181 | possibly require an additional register. Proper specification of | |
1182 | this macro eliminates this overhead for such machines. | |
1183 | ||
1184 | Similar use of this macro is made in strength reduction of loops. | |
1185 | ||
1186 | ADDRESS need not be valid as an address. In such a case, the cost | |
1187 | is not relevant and can be any value; invalid addresses need not be | |
1188 | assigned a different cost. | |
1189 | ||
1190 | On machines where an address involving more than one register is as | |
1191 | cheap as an address computation involving only one register, | |
1192 | defining `ADDRESS_COST' to reflect this can cause two registers to | |
1193 | be live over a region of code where only one would have been if | |
1194 | `ADDRESS_COST' were not defined in that manner. This effect should | |
1195 | be considered in the definition of this macro. Equivalent costs | |
1196 | should probably only be given to addresses with different numbers | |
1197 | of registers on machines with lots of registers. | |
1198 | ||
1199 | This macro will normally either not be defined or be defined as a | |
dea09b1b | 1200 | constant. */ |
9db1d521 | 1201 | |
dea09b1b | 1202 | #define ADDRESS_COST(RTX) s390_address_cost ((RTX)) |
9db1d521 HP |
1203 | |
1204 | /* On s390, copy between fprs and gprs is expensive. */ | |
1205 | ||
1206 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ | |
14b3e8ef UW |
1207 | (( ( reg_classes_intersect_p ((CLASS1), GENERAL_REGS) \ |
1208 | && reg_classes_intersect_p ((CLASS2), FP_REGS)) \ | |
1209 | || ( reg_classes_intersect_p ((CLASS1), FP_REGS) \ | |
1210 | && reg_classes_intersect_p ((CLASS2), GENERAL_REGS))) ? 10 : 1) | |
9db1d521 HP |
1211 | |
1212 | ||
1213 | /* A C expression for the cost of moving data of mode M between a | |
1214 | register and memory. A value of 2 is the default; this cost is | |
1215 | relative to those in `REGISTER_MOVE_COST'. | |
1216 | ||
1217 | If moving between registers and memory is more expensive than | |
1218 | between two registers, you should define this macro to express the | |
1219 | relative cost. */ | |
1220 | ||
1221 | #define MEMORY_MOVE_COST(M, C, I) 1 | |
1222 | ||
1223 | /* A C expression for the cost of a branch instruction. A value of 1 | |
1224 | is the default; other values are interpreted relative to that. */ | |
1225 | ||
1226 | #define BRANCH_COST 1 | |
1227 | ||
9db1d521 | 1228 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
d65f7478 | 1229 | return the mode to be used for the comparison. */ |
9db1d521 | 1230 | |
ba956982 | 1231 | #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y)) |
9db1d521 HP |
1232 | |
1233 | ||
1234 | /* Define the information needed to generate branch and scc insns. This is | |
1235 | stored from the compare operation. Note that we can't use "rtx" here | |
1236 | since it hasn't been defined! */ | |
1237 | ||
1238 | extern struct rtx_def *s390_compare_op0, *s390_compare_op1; | |
9db1d521 HP |
1239 | |
1240 | ||
1241 | /* How to refer to registers in assembler output. This sequence is | |
1242 | indexed by compiler's hard-register-number (see above). */ | |
1243 | ||
1244 | #define REGISTER_NAMES \ | |
1245 | { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ | |
1246 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ | |
1247 | "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \ | |
1248 | "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \ | |
4023fb28 | 1249 | "%ap", "%cc", "%fp" \ |
9db1d521 HP |
1250 | } |
1251 | ||
1252 | /* implicit call of memcpy, not bcopy */ | |
1253 | ||
1254 | #define TARGET_MEM_FUNCTIONS | |
1255 | ||
4c8c0dec JJ |
1256 | /* Either simplify a location expression, or return the original. */ |
1257 | ||
1258 | #define ASM_SIMPLIFY_DWARF_ADDR(X) \ | |
1259 | s390_simplify_dwarf_addr (X) | |
4023fb28 | 1260 | |
9db1d521 HP |
1261 | /* Print operand X (an rtx) in assembler syntax to file FILE. |
1262 | CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. | |
1263 | For `%' followed by punctuation, CODE is the punctuation and X is null. */ | |
1264 | ||
1265 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) | |
1266 | ||
1267 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) | |
1268 | ||
1269 | ||
1270 | /* Define the codes that are matched by predicates in aux-output.c. */ | |
1271 | ||
4023fb28 UW |
1272 | #define PREDICATE_CODES \ |
1273 | {"s_operand", { SUBREG, MEM }}, \ | |
1274 | {"s_imm_operand", { CONST_INT, CONST_DOUBLE, SUBREG, MEM }}, \ | |
1275 | {"bras_sym_operand",{ SYMBOL_REF, CONST }}, \ | |
1276 | {"larl_operand", { SYMBOL_REF, CONST, CONST_INT, CONST_DOUBLE }}, \ | |
1277 | {"load_multiple_operation", {PARALLEL}}, \ | |
1278 | {"store_multiple_operation", {PARALLEL}}, \ | |
f3e9edff | 1279 | {"const0_operand", { CONST_INT, CONST_DOUBLE }}, \ |
b2ccb744 UW |
1280 | {"consttable_operand", { SYMBOL_REF, LABEL_REF, CONST, \ |
1281 | CONST_INT, CONST_DOUBLE }}, \ | |
f3e9edff | 1282 | {"s390_plus_operand", { PLUS }}, |
4023fb28 UW |
1283 | |
1284 | ||
1285 | /* S/390 constant pool breaks the devices in crtstuff.c to control section | |
1286 | in where code resides. We have to write it as asm code. */ | |
1287 | #ifndef __s390x__ | |
cea3bd3e RH |
1288 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ |
1289 | asm (SECTION_OP "\n\ | |
3c9a08ec | 1290 | bras\t%r2,1f\n\ |
cea3bd3e | 1291 | 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\ |
3c9a08ec UW |
1292 | 1: l\t%r3,0(%r2)\n\ |
1293 | bas\t%r14,0(%r3,%r2)\n\ | |
cea3bd3e | 1294 | .previous"); |
4023fb28 | 1295 | #endif |
9db1d521 | 1296 | |
9db1d521 HP |
1297 | /* Constant Pool for all symbols operands which are changed with |
1298 | force_const_mem during insn generation (expand_insn). */ | |
1299 | ||
9db1d521 HP |
1300 | extern int s390_pool_count; |
1301 | extern int s390_nr_constants; | |
9db1d521 HP |
1302 | |
1303 | #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, fndecl, size) \ | |
1304 | { \ | |
9db1d521 HP |
1305 | struct pool_constant *pool; \ |
1306 | \ | |
1307 | if (s390_pool_count == -1) \ | |
1308 | { \ | |
1309 | s390_nr_constants = 0; \ | |
1310 | for (pool = first_pool; pool; pool = pool->next) \ | |
1311 | if (pool->mark) s390_nr_constants++; \ | |
1312 | return; \ | |
1313 | } \ | |
9db1d521 HP |
1314 | } |
1315 | ||
9db1d521 | 1316 | #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, EXP, MODE, ALIGN, LABELNO, WIN) \ |
c8af3574 | 1317 | { \ |
b2ccb744 | 1318 | fprintf (FILE, ".LC%d:\n", LABELNO); \ |
c8af3574 RH |
1319 | \ |
1320 | /* Output the value of the constant itself. */ \ | |
1321 | switch (GET_MODE_CLASS (MODE)) \ | |
1322 | { \ | |
1323 | case MODE_FLOAT: \ | |
1324 | if (GET_CODE (EXP) != CONST_DOUBLE) \ | |
1325 | abort (); \ | |
1326 | \ | |
b216cd4a ZW |
1327 | REAL_VALUE_FROM_CONST_DOUBLE (r, EXP); \ |
1328 | assemble_real (r, MODE, ALIGN); \ | |
c8af3574 RH |
1329 | break; \ |
1330 | \ | |
1331 | case MODE_INT: \ | |
1332 | case MODE_PARTIAL_INT: \ | |
1333 | if (flag_pic \ | |
1334 | && (GET_CODE (EXP) == CONST \ | |
1335 | || GET_CODE (EXP) == SYMBOL_REF \ | |
1336 | || GET_CODE (EXP) == LABEL_REF )) \ | |
1337 | { \ | |
301d03af | 1338 | fputs (integer_asm_op (UNITS_PER_WORD, TRUE), FILE); \ |
c8af3574 RH |
1339 | s390_output_symbolic_const (FILE, EXP); \ |
1340 | fputc ('\n', (FILE)); \ | |
1341 | } \ | |
1342 | else \ | |
4023fb28 UW |
1343 | { \ |
1344 | assemble_integer (EXP, GET_MODE_SIZE (MODE), ALIGN, 1); \ | |
1345 | if (GET_MODE_SIZE (MODE) == 1) \ | |
1346 | ASM_OUTPUT_SKIP ((FILE), 1); \ | |
1347 | } \ | |
c8af3574 RH |
1348 | break; \ |
1349 | \ | |
1350 | default: \ | |
1351 | abort (); \ | |
1352 | } \ | |
1353 | goto WIN; \ | |
9db1d521 HP |
1354 | } |
1355 | ||
c3cc6b78 UW |
1356 | /* In rare cases, correct code generation requires extra machine dependent |
1357 | processing between the second jump optimization pass and delayed branch | |
1358 | scheduling. On those machines, define this macro as a C statement to act on | |
1359 | the code starting at INSN. */ | |
1360 | ||
1361 | #define MACHINE_DEPENDENT_REORG(INSN) s390_machine_dependent_reorg (INSN) | |
1362 | ||
9db1d521 | 1363 | #endif |