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9db1d521 | 1 | /* Definitions of target machine for GNU compiler, for IBM S/390 |
16c484c7 | 2 | Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc. |
9db1d521 | 3 | Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
f314b9b1 | 4 | Ulrich Weigand (uweigand@de.ibm.com). |
9db1d521 HP |
5 | This file is part of GNU CC. |
6 | ||
7 | GNU CC is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 2, or (at your option) | |
10 | any later version. | |
11 | ||
12 | GNU CC is distributed in the hope that it will be useful, | |
13 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | GNU General Public License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GNU CC; see the file COPYING. If not, write to | |
19 | the Free Software Foundation, 59 Temple Place - Suite 330, | |
20 | Boston, MA 02111-1307, USA. */ | |
21 | ||
22 | #ifndef _S390_H | |
23 | #define _S390_H | |
24 | ||
42c78618 UW |
25 | /* Override the __fixdfdi etc. routines when building libgcc2. |
26 | ??? This should be done in a cleaner way ... */ | |
27 | #ifdef IN_LIBGCC2 | |
28 | #include <s390/fixdfdi.h> | |
29 | #endif | |
30 | ||
31 | ||
862a2d83 | 32 | /* Run-time target specification. */ |
9db1d521 | 33 | |
862a2d83 UW |
34 | /* Target CPU builtins. */ |
35 | #define TARGET_CPU_CPP_BUILTINS() \ | |
36 | do \ | |
37 | { \ | |
38 | builtin_assert ("cpu=s390"); \ | |
39 | builtin_assert ("machine=s390"); \ | |
40 | builtin_define ("__s390__"); \ | |
41 | if (TARGET_64BIT) \ | |
42 | builtin_define ("__s390x__"); \ | |
43 | } \ | |
44 | while (0) | |
9db1d521 | 45 | |
862a2d83 | 46 | /* Optional target features. */ |
9db1d521 HP |
47 | extern int target_flags; |
48 | ||
9db1d521 | 49 | #define TARGET_HARD_FLOAT (target_flags & 1) |
58d10f89 | 50 | #define TARGET_SOFT_FLOAT (!(target_flags & 1)) |
9db1d521 HP |
51 | #define TARGET_BACKCHAIN (target_flags & 2) |
52 | #define TARGET_SMALL_EXEC (target_flags & 4) | |
53 | #define TARGET_DEBUG_ARG (target_flags & 8) | |
54 | #define TARGET_64BIT (target_flags & 16) | |
55 | #define TARGET_MVCLE (target_flags & 32) | |
56 | ||
8e509cf9 UW |
57 | /* ??? Once this actually works, it could be made a runtime option. */ |
58 | #define TARGET_IBM_FLOAT 0 | |
59 | #define TARGET_IEEE_FLOAT 1 | |
60 | ||
58d10f89 UW |
61 | #ifdef DEFAULT_TARGET_64BIT |
62 | #define TARGET_DEFAULT 0x13 | |
58d10f89 | 63 | #else |
9db1d521 | 64 | #define TARGET_DEFAULT 0x3 |
58d10f89 UW |
65 | #endif |
66 | ||
9db1d521 | 67 | #define TARGET_SWITCHES \ |
994fe660 UW |
68 | { { "hard-float", 1, N_("Use hardware fp")}, \ |
69 | { "soft-float", -1, N_("Don't use hardware fp")}, \ | |
70 | { "backchain", 2, N_("Set backchain")}, \ | |
71 | { "no-backchain", -2, N_("Don't set backchain (faster, but debug harder")}, \ | |
72 | { "small-exec", 4, N_("Use bras for execucable < 64k")}, \ | |
73 | { "no-small-exec",-4, N_("Don't use bras")}, \ | |
74 | { "debug", 8, N_("Additional debug prints")}, \ | |
75 | { "no-debug", -8, N_("Don't print additional debug prints")}, \ | |
76 | { "64", 16, N_("64 bit mode")}, \ | |
77 | { "31", -16, N_("31 bit mode")}, \ | |
78 | { "mvcle", 32, N_("mvcle use")}, \ | |
79 | { "no-mvcle", -32, N_("mvc&ex")}, \ | |
9db1d521 HP |
80 | { "", TARGET_DEFAULT, 0 } } |
81 | ||
862a2d83 UW |
82 | /* Target version string. Overridden by the OS header. */ |
83 | #ifdef DEFAULT_TARGET_64BIT | |
84 | #define TARGET_VERSION fprintf (stderr, " (zSeries)"); | |
85 | #else | |
86 | #define TARGET_VERSION fprintf (stderr, " (S/390)"); | |
87 | #endif | |
9db1d521 | 88 | |
862a2d83 UW |
89 | /* Hooks to override options. */ |
90 | #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) optimization_options(LEVEL, SIZE) | |
4023fb28 UW |
91 | #define OVERRIDE_OPTIONS override_options () |
92 | ||
862a2d83 UW |
93 | /* Frame pointer is not used for debugging. */ |
94 | #define CAN_DEBUG_WITHOUT_FP | |
9db1d521 | 95 | |
9db1d521 HP |
96 | |
97 | /* Target machine storage layout. */ | |
98 | ||
862a2d83 | 99 | /* Everything is big-endian. */ |
9db1d521 | 100 | #define BITS_BIG_ENDIAN 1 |
9db1d521 | 101 | #define BYTES_BIG_ENDIAN 1 |
9db1d521 HP |
102 | #define WORDS_BIG_ENDIAN 1 |
103 | ||
9db1d521 | 104 | /* Width of a word, in units (bytes). */ |
9db1d521 HP |
105 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) |
106 | #define MIN_UNITS_PER_WORD 4 | |
862a2d83 | 107 | #define MAX_BITS_PER_WORD 64 |
9db1d521 | 108 | |
862a2d83 UW |
109 | /* Function arguments and return values are promoted to word size. */ |
110 | #define PROMOTE_FUNCTION_ARGS | |
111 | #define PROMOTE_FUNCTION_RETURN | |
112 | #define PROMOTE_FOR_CALL_ONLY | |
9db1d521 HP |
113 | |
114 | #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ | |
115 | if (INTEGRAL_MODE_P (MODE) && \ | |
116 | GET_MODE_SIZE (MODE) < UNITS_PER_WORD) { \ | |
117 | (MODE) = Pmode; \ | |
118 | } | |
119 | ||
9db1d521 | 120 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
9db1d521 HP |
121 | #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32) |
122 | ||
123 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
9db1d521 HP |
124 | #define STACK_BOUNDARY 64 |
125 | ||
126 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
9db1d521 HP |
127 | #define FUNCTION_BOUNDARY 32 |
128 | ||
129 | /* There is no point aligning anything to a rounder boundary than this. */ | |
9db1d521 HP |
130 | #define BIGGEST_ALIGNMENT 64 |
131 | ||
132 | /* Alignment of field after `int : 0' in a structure. */ | |
9db1d521 HP |
133 | #define EMPTY_FIELD_BOUNDARY 32 |
134 | ||
f710504c | 135 | /* Alignment on even addresses for LARL instruction. */ |
9db1d521 | 136 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) |
9db1d521 HP |
137 | #define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) |
138 | ||
862a2d83 | 139 | /* Alignment is not required by the hardware. */ |
9db1d521 HP |
140 | #define STRICT_ALIGNMENT 0 |
141 | ||
862a2d83 UW |
142 | /* Mode of stack savearea. |
143 | FUNCTION is VOIDmode because calling convention maintains SP. | |
144 | BLOCK needs Pmode for SP. | |
145 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ | |
146 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
147 | (LEVEL == SAVE_FUNCTION ? VOIDmode \ | |
148 | : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? TImode : DImode) : Pmode) | |
149 | ||
9db1d521 | 150 | /* Define target floating point format. */ |
8e509cf9 | 151 | #define TARGET_FLOAT_FORMAT \ |
862a2d83 | 152 | (TARGET_IEEE_FLOAT? IEEE_FLOAT_FORMAT : IBM_FLOAT_FORMAT) |
9db1d521 | 153 | |
9db1d521 | 154 | |
862a2d83 | 155 | /* Type layout. */ |
9db1d521 | 156 | |
862a2d83 UW |
157 | /* Sizes in bits of the source language data types. */ |
158 | #define SHORT_TYPE_SIZE 16 | |
159 | #define INT_TYPE_SIZE 32 | |
160 | #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) | |
161 | #define MAX_LONG_TYPE_SIZE 64 | |
162 | #define LONG_LONG_TYPE_SIZE 64 | |
163 | #define FLOAT_TYPE_SIZE 32 | |
164 | #define DOUBLE_TYPE_SIZE 64 | |
165 | #define LONG_DOUBLE_TYPE_SIZE 64 /* ??? Should support extended format. */ | |
166 | ||
167 | /* We use "unsigned char" as default. */ | |
168 | #define DEFAULT_SIGNED_CHAR 0 | |
169 | ||
170 | ||
171 | /* Register usage. */ | |
172 | ||
173 | /* We have 16 general purpose registers (registers 0-15), | |
174 | and 16 floating point registers (registers 16-31). | |
175 | (On non-IEEE machines, we have only 4 fp registers.) | |
176 | ||
177 | Amongst the general purpose registers, some are used | |
178 | for specific purposes: | |
179 | GPR 11: Hard frame pointer (if needed) | |
180 | GPR 12: Global offset table pointer (if needed) | |
181 | GPR 13: Literal pool base register | |
182 | GPR 14: Return address register | |
183 | GPR 15: Stack pointer | |
9db1d521 | 184 | |
862a2d83 UW |
185 | Registers 32-34 are 'fake' hard registers that do not |
186 | correspond to actual hardware: | |
187 | Reg 32: Argument pointer | |
188 | Reg 33: Condition code | |
189 | Reg 34: Frame pointer */ | |
190 | ||
191 | #define FIRST_PSEUDO_REGISTER 35 | |
192 | ||
193 | /* Standard register usage. */ | |
8e509cf9 UW |
194 | #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16) |
195 | #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16) | |
196 | #define FP_REGNO_P(N) ((N) >= 16 && (N) < (TARGET_IEEE_FLOAT? 32 : 20)) | |
197 | #define CC_REGNO_P(N) ((N) == 33) | |
198 | ||
199 | #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) | |
200 | #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X))) | |
201 | #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) | |
202 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) | |
9db1d521 | 203 | |
862a2d83 UW |
204 | #define BASE_REGISTER 13 |
205 | #define RETURN_REGNUM 14 | |
206 | #define CC_REGNUM 33 | |
4023fb28 | 207 | |
862a2d83 | 208 | /* Set up fixed registers and calling convention: |
9db1d521 | 209 | |
862a2d83 UW |
210 | GPRs 0-5 are always call-clobbered, |
211 | GPRs 6-15 are always call-saved. | |
212 | GPR 12 is fixed if used as GOT pointer. | |
213 | GPR 13 is always fixed (as literal pool pointer). | |
214 | GPR 14 is always fixed (as return address). | |
215 | GPR 15 is always fixed (as stack pointer). | |
216 | The 'fake' hard registers are call-clobbered and fixed. | |
9db1d521 | 217 | |
862a2d83 UW |
218 | On 31-bit, FPRs 18-19 are call-clobbered; |
219 | on 64-bit, FPRs 24-31 are call-clobbered. | |
220 | The remaining FPRs are call-saved. */ | |
9db1d521 HP |
221 | |
222 | #define FIXED_REGISTERS \ | |
223 | { 0, 0, 0, 0, \ | |
224 | 0, 0, 0, 0, \ | |
225 | 0, 0, 0, 0, \ | |
226 | 0, 1, 1, 1, \ | |
227 | 0, 0, 0, 0, \ | |
228 | 0, 0, 0, 0, \ | |
229 | 0, 0, 0, 0, \ | |
230 | 0, 0, 0, 0, \ | |
4023fb28 | 231 | 1, 1, 1 } |
9db1d521 | 232 | |
9db1d521 HP |
233 | #define CALL_USED_REGISTERS \ |
234 | { 1, 1, 1, 1, \ | |
235 | 1, 1, 0, 0, \ | |
236 | 0, 0, 0, 0, \ | |
237 | 0, 1, 1, 1, \ | |
4023fb28 UW |
238 | 1, 1, 1, 1, \ |
239 | 1, 1, 1, 1, \ | |
240 | 1, 1, 1, 1, \ | |
241 | 1, 1, 1, 1, \ | |
242 | 1, 1, 1 } | |
243 | ||
4023fb28 UW |
244 | #define CALL_REALLY_USED_REGISTERS \ |
245 | { 1, 1, 1, 1, \ | |
9db1d521 | 246 | 1, 1, 0, 0, \ |
4023fb28 UW |
247 | 0, 0, 0, 0, \ |
248 | 0, 0, 0, 0, \ | |
9db1d521 HP |
249 | 1, 1, 1, 1, \ |
250 | 1, 1, 1, 1, \ | |
251 | 1, 1, 1, 1, \ | |
4023fb28 UW |
252 | 1, 1, 1, 1, \ |
253 | 1, 1, 1 } | |
9db1d521 | 254 | |
9db1d521 HP |
255 | #define CONDITIONAL_REGISTER_USAGE \ |
256 | do \ | |
257 | { \ | |
4023fb28 UW |
258 | int i; \ |
259 | \ | |
9db1d521 HP |
260 | if (flag_pic) \ |
261 | { \ | |
262 | fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
263 | call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ | |
264 | } \ | |
4023fb28 UW |
265 | if (TARGET_64BIT) \ |
266 | { \ | |
267 | for (i = 24; i < 32; i++) \ | |
268 | call_used_regs[i] = call_really_used_regs[i] = 0; \ | |
269 | } \ | |
270 | else \ | |
271 | { \ | |
272 | for (i = 18; i < 20; i++) \ | |
273 | call_used_regs[i] = call_really_used_regs[i] = 0; \ | |
274 | } \ | |
9db1d521 HP |
275 | } while (0) |
276 | ||
862a2d83 UW |
277 | /* Preferred register allocation order. */ |
278 | #define REG_ALLOC_ORDER \ | |
279 | { 1, 2, 3, 4, 5, 0, 14, 13, 12, 11, 10, 9, 8, 7, 6, \ | |
280 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
281 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
282 | 15, 32, 33, 34 } | |
9db1d521 | 283 | |
9db1d521 | 284 | |
862a2d83 UW |
285 | /* Fitting values into registers. */ |
286 | ||
287 | /* Integer modes <= word size fit into any GPR. | |
288 | Integer modes > word size fit into successive GPRs, starting with | |
289 | an even-numbered register. | |
290 | SImode and DImode fit into FPRs as well. | |
291 | ||
292 | Floating point modes <= word size fit into any FPR or GPR. | |
293 | Floating point modes > word size (i.e. DFmode on 32-bit) fit | |
294 | into any FPR, or an even-odd GPR pair. | |
295 | ||
296 | Complex floating point modes fit either into two FPRs, or into | |
297 | successive GPRs (again starting with an even number). | |
298 | ||
299 | Condition code modes fit only into the CC register. */ | |
9db1d521 HP |
300 | |
301 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
8e509cf9 | 302 | (FP_REGNO_P(REGNO)? \ |
9db1d521 | 303 | (GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \ |
8e509cf9 | 304 | GENERAL_REGNO_P(REGNO)? \ |
9db1d521 HP |
305 | ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1) / UNITS_PER_WORD) : \ |
306 | 1) | |
307 | ||
9db1d521 | 308 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
8e509cf9 | 309 | (FP_REGNO_P(REGNO)? \ |
5d4d885c UW |
310 | ((MODE) == SImode || (MODE) == DImode || \ |
311 | GET_MODE_CLASS(MODE) == MODE_FLOAT || \ | |
312 | GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT) : \ | |
8e509cf9 | 313 | GENERAL_REGNO_P(REGNO)? \ |
f314b9b1 | 314 | (HARD_REGNO_NREGS(REGNO, MODE) == 1 || !((REGNO) & 1)) : \ |
9db1d521 HP |
315 | CC_REGNO_P(REGNO)? \ |
316 | GET_MODE_CLASS (MODE) == MODE_CC : \ | |
317 | 0) | |
318 | ||
9db1d521 HP |
319 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
320 | (((MODE1) == SFmode || (MODE1) == DFmode) \ | |
321 | == ((MODE2) == SFmode || (MODE2) == DFmode)) | |
322 | ||
862a2d83 UW |
323 | /* Maximum number of registers to represent a value of mode MODE |
324 | in a register of class CLASS. */ | |
325 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
326 | ((CLASS) == FP_REGS ? \ | |
327 | (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \ | |
328 | (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
4023fb28 | 329 | |
862a2d83 UW |
330 | /* If a 4-byte value is loaded into a FPR, it is placed into the |
331 | *upper* half of the register, not the lower. Therefore, we | |
332 | cannot use SUBREGs to switch between modes in FP registers. */ | |
cff9f8d5 AH |
333 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO) \ |
334 | (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) ? FP_REGS : NO_REGS) | |
9db1d521 | 335 | |
862a2d83 UW |
336 | /* Register classes. */ |
337 | ||
338 | /* We use the following register classes: | |
339 | GENERAL_REGS All general purpose registers | |
340 | ADDR_REGS All general purpose registers except %r0 | |
341 | (These registers can be used in address generation) | |
342 | FP_REGS All floating point registers | |
343 | ||
344 | GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS | |
345 | ADDR_FP_REGS Union of ADDR_REGS and FP_REGS | |
346 | ||
347 | NO_REGS No registers | |
348 | ALL_REGS All registers | |
9db1d521 | 349 | |
862a2d83 UW |
350 | Note that the 'fake' frame pointer and argument pointer registers |
351 | are included amongst the address registers here. The condition | |
352 | code register is only included in ALL_REGS. */ | |
9db1d521 HP |
353 | |
354 | enum reg_class | |
355 | { | |
356 | NO_REGS, ADDR_REGS, GENERAL_REGS, | |
4023fb28 UW |
357 | FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, |
358 | ALL_REGS, LIM_REG_CLASSES | |
9db1d521 | 359 | }; |
9db1d521 HP |
360 | #define N_REG_CLASSES (int) LIM_REG_CLASSES |
361 | ||
9db1d521 | 362 | #define REG_CLASS_NAMES \ |
4023fb28 UW |
363 | { "NO_REGS", "ADDR_REGS", "GENERAL_REGS", \ |
364 | "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" } | |
9db1d521 | 365 | |
862a2d83 | 366 | /* Class -> register mapping. */ |
9db1d521 HP |
367 | #define REG_CLASS_CONTENTS \ |
368 | { \ | |
369 | { 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
4023fb28 UW |
370 | { 0x0000fffe, 0x00000005 }, /* ADDR_REGS */ \ |
371 | { 0x0000ffff, 0x00000005 }, /* GENERAL_REGS */ \ | |
9db1d521 | 372 | { 0xffff0000, 0x00000000 }, /* FP_REGS */ \ |
4023fb28 UW |
373 | { 0xfffffffe, 0x00000005 }, /* ADDR_FP_REGS */ \ |
374 | { 0xffffffff, 0x00000005 }, /* GENERAL_FP_REGS */ \ | |
375 | { 0xffffffff, 0x00000007 }, /* ALL_REGS */ \ | |
9db1d521 HP |
376 | } |
377 | ||
862a2d83 UW |
378 | /* Register -> class mapping. */ |
379 | extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; | |
380 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) | |
9db1d521 | 381 | |
862a2d83 UW |
382 | /* ADDR_REGS can be used as base or index register. */ |
383 | #define INDEX_REG_CLASS ADDR_REGS | |
384 | #define BASE_REG_CLASS ADDR_REGS | |
9db1d521 | 385 | |
862a2d83 UW |
386 | /* Check whether REGNO is a hard register of the suitable class |
387 | or a pseudo register currently allocated to one such. */ | |
388 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
389 | (((REGNO) < FIRST_PSEUDO_REGISTER \ | |
390 | && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \ | |
391 | || (reg_renumber[REGNO] > 0 && reg_renumber[REGNO] < 16)) | |
392 | #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) | |
9db1d521 | 393 | |
9db1d521 | 394 | |
862a2d83 UW |
395 | /* Given an rtx X being reloaded into a reg required to be in class CLASS, |
396 | return the class of reg to actually use. */ | |
397 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
398 | s390_preferred_reload_class ((X), (CLASS)) | |
9db1d521 | 399 | |
862a2d83 UW |
400 | /* We need a secondary reload when loading a PLUS which is |
401 | not a valid operand for LOAD ADDRESS. */ | |
402 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ | |
403 | s390_secondary_input_reload_class ((CLASS), (MODE), (IN)) | |
9db1d521 | 404 | |
862a2d83 UW |
405 | /* We need secondary memory to move data between GPRs and FPRs. */ |
406 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ | |
407 | ((CLASS1) != (CLASS2) && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS)) | |
408 | ||
409 | /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit | |
410 | because the movsi and movsf patterns don't handle r/f moves. */ | |
411 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
412 | (GET_MODE_BITSIZE (MODE) < 32 \ | |
413 | ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
414 | : MODE) | |
415 | ||
416 | ||
417 | /* Define various machine-dependent constraint letters. */ | |
9db1d521 HP |
418 | |
419 | #define REG_CLASS_FROM_LETTER(C) \ | |
420 | ((C) == 'a' ? ADDR_REGS : \ | |
421 | (C) == 'd' ? GENERAL_REGS : \ | |
422 | (C) == 'f' ? FP_REGS : NO_REGS) | |
423 | ||
9db1d521 HP |
424 | #define CONST_OK_FOR_LETTER_P(VALUE, C) \ |
425 | ((C) == 'I' ? (unsigned long) (VALUE) < 256 : \ | |
426 | (C) == 'J' ? (unsigned long) (VALUE) < 4096 : \ | |
427 | (C) == 'K' ? (VALUE) >= -32768 && (VALUE) < 32768 : \ | |
428 | (C) == 'L' ? (unsigned long) (VALUE) < 65536 : 0) | |
429 | ||
9db1d521 HP |
430 | #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1 |
431 | ||
9db1d521 | 432 | #define EXTRA_CONSTRAINT(OP, C) \ |
ccfc6cc8 | 433 | ((C) == 'Q' ? q_constraint (OP) : \ |
9db1d521 HP |
434 | (C) == 'S' ? larl_operand (OP, GET_MODE (OP)) : 0) |
435 | ||
ccfc6cc8 UW |
436 | #define EXTRA_MEMORY_CONSTRAINT(C) ((C) == 'Q') |
437 | ||
9db1d521 | 438 | |
862a2d83 UW |
439 | /* Stack layout and calling conventions. */ |
440 | ||
441 | /* Our stack grows from higher to lower addresses. However, local variables | |
442 | are accessed by positive offsets, and function arguments are stored at | |
443 | increasing addresses. */ | |
444 | #define STACK_GROWS_DOWNWARD | |
445 | /* #undef FRAME_GROWS_DOWNWARD */ | |
446 | /* #undef ARGS_GROW_DOWNWARD */ | |
9db1d521 | 447 | |
862a2d83 UW |
448 | /* The basic stack layout looks like this: the stack pointer points |
449 | to the register save area for called functions. Above that area | |
450 | is the location to place outgoing arguments. Above those follow | |
451 | dynamic allocations (alloca), and finally the local variables. */ | |
9db1d521 | 452 | |
862a2d83 UW |
453 | /* Offset from stack-pointer to first location of outgoing args. */ |
454 | #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96) | |
9db1d521 | 455 | |
862a2d83 UW |
456 | /* Offset within stack frame to start allocating local variables at. */ |
457 | extern int current_function_outgoing_args_size; | |
458 | #define STARTING_FRAME_OFFSET \ | |
459 | (STACK_POINTER_OFFSET + current_function_outgoing_args_size) | |
9db1d521 | 460 | |
862a2d83 UW |
461 | /* Offset from the stack pointer register to an item dynamically |
462 | allocated on the stack, e.g., by `alloca'. */ | |
463 | #define STACK_DYNAMIC_OFFSET(FUNDECL) (STARTING_FRAME_OFFSET) | |
9db1d521 | 464 | |
862a2d83 UW |
465 | /* Offset of first parameter from the argument pointer register value. |
466 | We have a fake argument pointer register that points directly to | |
467 | the argument area. */ | |
468 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
9db1d521 | 469 | |
4023fb28 UW |
470 | /* The return address of the current frame is retrieved |
471 | from the initial value of register RETURN_REGNUM. | |
472 | For frames farther back, we use the stack slot where | |
473 | the corresponding RETURN_REGNUM register was saved. */ | |
474 | ||
475 | #define DYNAMIC_CHAIN_ADDRESS(FRAME) \ | |
476 | ((FRAME) != hard_frame_pointer_rtx ? (FRAME) : \ | |
477 | plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET)) | |
478 | ||
479 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ | |
5d4d885c | 480 | s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME))) |
9db1d521 | 481 | |
862a2d83 | 482 | /* In 31-bit mode, we need to mask off the high bit of return addresses. */ |
58d10f89 | 483 | #define MASK_RETURN_ADDR (TARGET_64BIT ? GEN_INT (-1) : GEN_INT (0x7fffffff)) |
9db1d521 | 484 | |
4023fb28 | 485 | |
862a2d83 UW |
486 | /* Exception handling. */ |
487 | ||
488 | /* Describe calling conventions for DWARF-2 exception handling. */ | |
489 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM) | |
4023fb28 | 490 | #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET |
9db1d521 HP |
491 | #define DWARF_FRAME_RETURN_COLUMN 14 |
492 | ||
493 | /* Describe how we implement __builtin_eh_return. */ | |
494 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM) | |
495 | #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) | |
496 | #define EH_RETURN_HANDLER_RTX \ | |
f314b9b1 UW |
497 | gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, \ |
498 | TARGET_64BIT? -48 : -40)) | |
9db1d521 | 499 | |
18789f4e UW |
500 | /* Select a format to encode pointers in exception handling data. */ |
501 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
502 | (flag_pic \ | |
503 | ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ | |
504 | : DW_EH_PE_absptr) | |
505 | ||
9db1d521 | 506 | |
862a2d83 | 507 | /* Frame registers. */ |
9db1d521 | 508 | |
862a2d83 UW |
509 | #define STACK_POINTER_REGNUM 15 |
510 | #define FRAME_POINTER_REGNUM 34 | |
511 | #define HARD_FRAME_POINTER_REGNUM 11 | |
512 | #define ARG_POINTER_REGNUM 32 | |
9db1d521 | 513 | |
862a2d83 UW |
514 | /* The static chain must be call-clobbered, but not used for |
515 | function argument passing. As register 1 is clobbered by | |
516 | the trampoline code, we only have one option. */ | |
517 | #define STATIC_CHAIN_REGNUM 0 | |
9db1d521 | 518 | |
862a2d83 UW |
519 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
520 | To avoid ABI incompatibility, this number must not change even as | |
521 | 'fake' hard registers are added or removed. */ | |
522 | #define DWARF_FRAME_REGISTERS 34 | |
9db1d521 | 523 | |
9db1d521 | 524 | |
862a2d83 | 525 | /* Frame pointer and argument pointer elimination. */ |
9db1d521 | 526 | |
862a2d83 | 527 | #define FRAME_POINTER_REQUIRED 0 |
9db1d521 HP |
528 | |
529 | #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0 | |
530 | ||
862a2d83 UW |
531 | #define ELIMINABLE_REGS \ |
532 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
533 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
534 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
535 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} | |
9db1d521 | 536 | |
862a2d83 | 537 | #define CAN_ELIMINATE(FROM, TO) (1) |
9db1d521 | 538 | |
862a2d83 UW |
539 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
540 | { if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ | |
541 | { (OFFSET) = 0; } \ | |
542 | else if ((FROM) == FRAME_POINTER_REGNUM \ | |
543 | && (TO) == HARD_FRAME_POINTER_REGNUM) \ | |
544 | { (OFFSET) = 0; } \ | |
545 | else if ((FROM) == ARG_POINTER_REGNUM \ | |
546 | && (TO) == HARD_FRAME_POINTER_REGNUM) \ | |
547 | { (OFFSET) = s390_arg_frame_offset (); } \ | |
548 | else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ | |
549 | { (OFFSET) = s390_arg_frame_offset (); } \ | |
550 | else \ | |
551 | abort(); \ | |
552 | } | |
9db1d521 | 553 | |
9db1d521 | 554 | |
862a2d83 UW |
555 | /* Stack arguments. */ |
556 | ||
557 | /* We need current_function_outgoing_args to be valid. */ | |
558 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
9db1d521 | 559 | |
862a2d83 UW |
560 | /* Return doesn't modify the stack. */ |
561 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 | |
9db1d521 | 562 | |
9db1d521 | 563 | |
862a2d83 UW |
564 | /* Register arguments. */ |
565 | ||
9db1d521 HP |
566 | typedef struct s390_arg_structure |
567 | { | |
568 | int gprs; /* gpr so far */ | |
569 | int fprs; /* fpr so far */ | |
570 | } | |
571 | CUMULATIVE_ARGS; | |
572 | ||
9db1d521 HP |
573 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN) \ |
574 | ((CUM).gprs=0, (CUM).fprs=0) | |
575 | ||
9db1d521 | 576 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
994fe660 | 577 | s390_function_arg_advance (&CUM, MODE, TYPE, NAMED) |
9db1d521 | 578 | |
9db1d521 | 579 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
994fe660 | 580 | s390_function_arg (&CUM, MODE, TYPE, NAMED) |
9db1d521 | 581 | |
9db1d521 HP |
582 | #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ |
583 | s390_function_arg_pass_by_reference (MODE, TYPE) | |
584 | ||
862a2d83 UW |
585 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 |
586 | ||
587 | /* Arguments can be placed in general registers 2 to 6, | |
588 | or in floating point registers 0 and 2. */ | |
589 | #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \ | |
590 | (N) == 16 || (N) == 17) | |
9db1d521 | 591 | |
9db1d521 | 592 | |
862a2d83 UW |
593 | /* Scalar return values. */ |
594 | ||
595 | /* We return scalars in general purpose register 2 for integral values, | |
596 | and floating point register 0 for fp values. */ | |
9db1d521 HP |
597 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
598 | gen_rtx_REG ((INTEGRAL_TYPE_P (VALTYPE) \ | |
599 | && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \ | |
600 | || POINTER_TYPE_P (VALTYPE) \ | |
601 | ? word_mode : TYPE_MODE (VALTYPE), \ | |
602 | TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_HARD_FLOAT ? 16 : 2) | |
603 | ||
604 | /* Define how to find the value returned by a library function assuming | |
605 | the value has mode MODE. */ | |
862a2d83 UW |
606 | #define RET_REG(MODE) ((GET_MODE_CLASS (MODE) == MODE_INT \ |
607 | || TARGET_SOFT_FLOAT ) ? 2 : 16) | |
9db1d521 HP |
608 | #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, RET_REG (MODE)) |
609 | ||
862a2d83 | 610 | /* Only gpr 2 and fpr 0 are ever used as return registers. */ |
9db1d521 HP |
611 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16) |
612 | ||
862a2d83 UW |
613 | |
614 | /* Aggregate return values. */ | |
615 | ||
9db1d521 HP |
616 | /* The definition of this macro implies that there are cases where |
617 | a scalar value cannot be returned in registers. */ | |
f314b9b1 UW |
618 | #define RETURN_IN_MEMORY(type) \ |
619 | (TYPE_MODE (type) == BLKmode || \ | |
620 | GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_INT || \ | |
621 | GET_MODE_CLASS (TYPE_MODE (type)) == MODE_COMPLEX_FLOAT) | |
9db1d521 | 622 | |
9db1d521 | 623 | /* Structure value address is passed as invisible first argument (gpr 2). */ |
9db1d521 HP |
624 | #define STRUCT_VALUE 0 |
625 | ||
9db1d521 | 626 | |
862a2d83 UW |
627 | /* Function entry and exit. */ |
628 | ||
629 | /* When returning from a function, the stack pointer does not matter. */ | |
630 | #define EXIT_IGNORE_STACK 1 | |
9db1d521 | 631 | |
9db1d521 | 632 | |
862a2d83 | 633 | /* Profiling. */ |
9db1d521 HP |
634 | |
635 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
862a2d83 | 636 | s390_function_profiler ((FILE), ((LABELNO))) |
9db1d521 | 637 | |
c52a375d | 638 | #define PROFILE_BEFORE_PROLOGUE 1 |
9db1d521 | 639 | |
9db1d521 | 640 | |
862a2d83 | 641 | /* Implementing the varargs macros. */ |
9db1d521 | 642 | |
862a2d83 UW |
643 | #define BUILD_VA_LIST_TYPE(VALIST) \ |
644 | (VALIST) = s390_build_va_list () | |
9db1d521 | 645 | |
862a2d83 UW |
646 | #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ |
647 | s390_va_start (valist, nextarg) | |
9db1d521 | 648 | |
862a2d83 UW |
649 | #define EXPAND_BUILTIN_VA_ARG(valist, type) \ |
650 | s390_va_arg (valist, type) | |
9db1d521 | 651 | |
9db1d521 | 652 | |
862a2d83 | 653 | /* Trampolines for nested functions. */ |
9db1d521 | 654 | |
862a2d83 | 655 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 36 : 20) |
9db1d521 | 656 | |
862a2d83 UW |
657 | #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \ |
658 | s390_initialize_trampoline ((ADDR), (FNADDR), (CXT)) | |
9db1d521 | 659 | |
862a2d83 UW |
660 | #define TRAMPOLINE_TEMPLATE(FILE) \ |
661 | s390_trampoline_template (FILE) | |
9db1d521 | 662 | |
9db1d521 | 663 | |
862a2d83 UW |
664 | /* Library calls. */ |
665 | ||
666 | /* We should use memcpy, not bcopy. */ | |
667 | #define TARGET_MEM_FUNCTIONS | |
9db1d521 | 668 | |
9db1d521 | 669 | |
862a2d83 | 670 | /* Addressing modes, and classification of registers for them. */ |
9db1d521 | 671 | |
862a2d83 UW |
672 | /* Recognize any constant value that is a valid address. */ |
673 | #define CONSTANT_ADDRESS_P(X) 0 | |
9db1d521 | 674 | |
862a2d83 UW |
675 | /* Maximum number of registers that can appear in a valid memory address. */ |
676 | #define MAX_REGS_PER_ADDRESS 2 | |
9db1d521 HP |
677 | |
678 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check | |
679 | its validity for a certain class. We have two alternate definitions | |
680 | for each of them. The usual definition accepts all pseudo regs; the | |
681 | other rejects them all. The symbol REG_OK_STRICT causes the latter | |
682 | definition to be used. | |
683 | ||
684 | Most source files want to accept pseudo regs in the hope that they will | |
685 | get allocated to the class that the insn wants them to be in. | |
686 | Some source files that are used after register allocation | |
687 | need to be strict. */ | |
688 | ||
4023fb28 UW |
689 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ |
690 | ((GET_MODE (X) == Pmode) && \ | |
691 | ((REGNO (X) >= FIRST_PSEUDO_REGISTER) \ | |
692 | || REGNO_REG_CLASS (REGNO (X)) == ADDR_REGS)) | |
9db1d521 | 693 | |
9db1d521 HP |
694 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) |
695 | ||
9db1d521 HP |
696 | #define REG_OK_FOR_INDEX_STRICT_P(X) \ |
697 | ((GET_MODE (X) == Pmode) && (REGNO_OK_FOR_INDEX_P (REGNO (X)))) | |
698 | ||
9db1d521 HP |
699 | #define REG_OK_FOR_BASE_STRICT_P(X) \ |
700 | ((GET_MODE (X) == Pmode) && (REGNO_OK_FOR_BASE_P (REGNO (X)))) | |
701 | ||
9db1d521 HP |
702 | #ifndef REG_OK_STRICT |
703 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X) | |
704 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X) | |
705 | #else | |
706 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X) | |
707 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X) | |
708 | #endif | |
709 | ||
862a2d83 UW |
710 | /* S/390 has no mode dependent addresses. */ |
711 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) | |
9db1d521 HP |
712 | |
713 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a | |
714 | valid memory address for an instruction. | |
715 | The MODE argument is the machine mode for the MEM expression | |
862a2d83 | 716 | that wants to use this address. */ |
9db1d521 HP |
717 | #ifdef REG_OK_STRICT |
718 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
719 | { \ | |
720 | if (legitimate_address_p (MODE, X, 1)) \ | |
721 | goto ADDR; \ | |
722 | } | |
723 | #else | |
724 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
725 | { \ | |
726 | if (legitimate_address_p (MODE, X, 0)) \ | |
727 | goto ADDR; \ | |
728 | } | |
729 | #endif | |
730 | ||
9db1d521 HP |
731 | /* Try machine-dependent ways of modifying an illegitimate address |
732 | to be legitimate. If we find one, return the new, valid address. | |
733 | This macro is used in only one place: `memory_address' in explow.c. */ | |
9db1d521 HP |
734 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
735 | { \ | |
736 | (X) = legitimize_address (X, OLDX, MODE); \ | |
737 | if (memory_address_p (MODE, X)) \ | |
738 | goto WIN; \ | |
739 | } | |
740 | ||
862a2d83 UW |
741 | /* Nonzero if the constant value X is a legitimate general operand. |
742 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
743 | #define LEGITIMATE_CONSTANT_P(X) \ | |
744 | legitimate_constant_p (X) | |
9db1d521 | 745 | |
862a2d83 UW |
746 | /* Helper macro for s390.c and s390.md to check for symbolic constants. */ |
747 | #define SYMBOLIC_CONST(X) \ | |
748 | (GET_CODE (X) == SYMBOL_REF \ | |
749 | || GET_CODE (X) == LABEL_REF \ | |
750 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
9db1d521 | 751 | |
9db1d521 | 752 | |
862a2d83 | 753 | /* Condition codes. */ |
9db1d521 | 754 | |
862a2d83 UW |
755 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
756 | return the mode to be used for the comparison. */ | |
757 | #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y)) | |
758 | ||
759 | /* Define the information needed to generate branch and scc insns. This is | |
760 | stored from the compare operation. Note that we can't use "rtx" here | |
761 | since it hasn't been defined! */ | |
762 | extern struct rtx_def *s390_compare_op0, *s390_compare_op1; | |
9db1d521 | 763 | |
9db1d521 | 764 | |
862a2d83 | 765 | /* Relative costs of operations. */ |
9db1d521 HP |
766 | |
767 | /* A part of a C `switch' statement that describes the relative costs | |
768 | of constant RTL expressions. It must contain `case' labels for | |
769 | expression codes `const_int', `const', `symbol_ref', `label_ref' | |
770 | and `const_double'. Each case must ultimately reach a `return' | |
771 | statement to return the relative cost of the use of that kind of | |
772 | constant value in an expression. The cost may depend on the | |
773 | precise value of the constant, which is available for examination | |
774 | in X, and the rtx code of the expression in which it is contained, | |
775 | found in OUTER_CODE. | |
776 | ||
777 | CODE is the expression code--redundant, since it can be obtained | |
778 | with `GET_CODE (X)'. */ | |
779 | /* Force_const_mem does not work out of reload, because the saveable_obstack | |
780 | is set to reload_obstack, which does not live long enough. | |
781 | Because of this we cannot use force_const_mem in addsi3. | |
782 | This leads to problems with gen_add2_insn with a constant greater | |
d65f7478 | 783 | than a short. Because of that we give an addition of greater |
9db1d521 HP |
784 | constants a cost of 3 (reload1.c 10096). */ |
785 | ||
9db1d521 HP |
786 | #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ |
787 | case CONST: \ | |
788 | if ((GET_CODE (XEXP (RTX, 0)) == MINUS) && \ | |
789 | (GET_CODE (XEXP (XEXP (RTX, 0), 1)) != CONST_INT)) \ | |
790 | return 1000; \ | |
791 | case CONST_INT: \ | |
792 | if ((OUTER_CODE == PLUS) && \ | |
793 | ((INTVAL (RTX) > 32767) || \ | |
794 | (INTVAL (RTX) < -32768))) \ | |
f314b9b1 | 795 | return COSTS_N_INSNS (3); \ |
9db1d521 HP |
796 | case LABEL_REF: \ |
797 | case SYMBOL_REF: \ | |
798 | case CONST_DOUBLE: \ | |
f314b9b1 | 799 | return 0; \ |
9db1d521 HP |
800 | |
801 | ||
802 | /* Like `CONST_COSTS' but applies to nonconstant RTL expressions. | |
803 | This can be used, for example, to indicate how costly a multiply | |
804 | instruction is. In writing this macro, you can use the construct | |
805 | `COSTS_N_INSNS (N)' to specify a cost equal to N fast | |
806 | instructions. OUTER_CODE is the code of the expression in which X | |
862a2d83 | 807 | is contained. */ |
9db1d521 HP |
808 | |
809 | #define RTX_COSTS(X, CODE, OUTER_CODE) \ | |
810 | case ASHIFT: \ | |
811 | case ASHIFTRT: \ | |
812 | case LSHIFTRT: \ | |
813 | case PLUS: \ | |
814 | case AND: \ | |
815 | case IOR: \ | |
816 | case XOR: \ | |
817 | case MINUS: \ | |
818 | case NEG: \ | |
819 | case NOT: \ | |
dea09b1b | 820 | return COSTS_N_INSNS (1); \ |
9db1d521 HP |
821 | case MULT: \ |
822 | if (GET_MODE (XEXP (X, 0)) == DImode) \ | |
dea09b1b UW |
823 | return COSTS_N_INSNS (40); \ |
824 | else \ | |
825 | return COSTS_N_INSNS (7); \ | |
9db1d521 HP |
826 | case DIV: \ |
827 | case UDIV: \ | |
828 | case MOD: \ | |
829 | case UMOD: \ | |
dea09b1b | 830 | return COSTS_N_INSNS (33); |
9db1d521 HP |
831 | |
832 | ||
833 | /* An expression giving the cost of an addressing mode that contains | |
834 | ADDRESS. If not defined, the cost is computed from the ADDRESS | |
862a2d83 | 835 | expression and the `CONST_COSTS' values. */ |
dea09b1b | 836 | #define ADDRESS_COST(RTX) s390_address_cost ((RTX)) |
9db1d521 HP |
837 | |
838 | /* On s390, copy between fprs and gprs is expensive. */ | |
9db1d521 | 839 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
14b3e8ef UW |
840 | (( ( reg_classes_intersect_p ((CLASS1), GENERAL_REGS) \ |
841 | && reg_classes_intersect_p ((CLASS2), FP_REGS)) \ | |
842 | || ( reg_classes_intersect_p ((CLASS1), FP_REGS) \ | |
843 | && reg_classes_intersect_p ((CLASS2), GENERAL_REGS))) ? 10 : 1) | |
9db1d521 | 844 | |
9db1d521 HP |
845 | /* A C expression for the cost of moving data of mode M between a |
846 | register and memory. A value of 2 is the default; this cost is | |
862a2d83 | 847 | relative to those in `REGISTER_MOVE_COST'. */ |
9db1d521 HP |
848 | #define MEMORY_MOVE_COST(M, C, I) 1 |
849 | ||
850 | /* A C expression for the cost of a branch instruction. A value of 1 | |
851 | is the default; other values are interpreted relative to that. */ | |
9db1d521 HP |
852 | #define BRANCH_COST 1 |
853 | ||
862a2d83 UW |
854 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
855 | #define SLOW_BYTE_ACCESS 1 | |
856 | ||
857 | /* The maximum number of bytes that a single instruction can move quickly | |
858 | between memory and registers or between two memory locations. */ | |
859 | #define MOVE_MAX (TARGET_64BIT ? 16 : 8) | |
860 | #define MAX_MOVE_MAX 16 | |
9db1d521 | 861 | |
862a2d83 UW |
862 | /* Determine whether to use move_by_pieces or block move insn. */ |
863 | #define MOVE_BY_PIECES_P(SIZE, ALIGN) \ | |
864 | ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ | |
865 | || (TARGET_64BIT && (SIZE) == 8) ) | |
866 | ||
867 | /* Determine whether to use clear_by_pieces or block clear insn. */ | |
868 | #define CLEAR_BY_PIECES_P(SIZE, ALIGN) \ | |
869 | ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ | |
870 | || (TARGET_64BIT && (SIZE) == 8) ) | |
871 | ||
872 | /* Don't perform CSE on function addresses. */ | |
873 | #define NO_FUNCTION_CSE | |
874 | ||
875 | ||
876 | /* Sections. */ | |
877 | ||
878 | /* Output before read-only data. */ | |
879 | #define TEXT_SECTION_ASM_OP ".text" | |
880 | ||
881 | /* Output before writable (initialized) data. */ | |
882 | #define DATA_SECTION_ASM_OP ".data" | |
883 | ||
884 | /* Output before writable (uninitialized) data. */ | |
885 | #define BSS_SECTION_ASM_OP ".bss" | |
886 | ||
887 | /* S/390 constant pool breaks the devices in crtstuff.c to control section | |
888 | in where code resides. We have to write it as asm code. */ | |
889 | #ifndef __s390x__ | |
890 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
891 | asm (SECTION_OP "\n\ | |
892 | bras\t%r2,1f\n\ | |
893 | 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\ | |
894 | 1: l\t%r3,0(%r2)\n\ | |
895 | bas\t%r14,0(%r3,%r2)\n\ | |
896 | .previous"); | |
897 | #endif | |
63a1ff86 | 898 | |
862a2d83 UW |
899 | |
900 | /* Position independent code. */ | |
901 | ||
902 | extern int flag_pic; | |
903 | ||
904 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM) | |
905 | ||
906 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) | |
63a1ff86 UW |
907 | |
908 | ||
909 | /* Assembler file format. */ | |
910 | ||
911 | /* Character to start a comment. */ | |
912 | #define ASM_COMMENT_START "#" | |
913 | ||
914 | /* Declare an uninitialized external linkage data object. */ | |
915 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
916 | asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) | |
917 | ||
918 | /* Globalizing directive for a label. */ | |
919 | #define GLOBAL_ASM_OP ".globl " | |
920 | ||
921 | /* Advance the location counter to a multiple of 2**LOG bytes. */ | |
922 | #define ASM_OUTPUT_ALIGN(FILE, LOG) \ | |
923 | if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG)) | |
924 | ||
925 | /* Advance the location counter by SIZE bytes. */ | |
926 | #define ASM_OUTPUT_SKIP(FILE, SIZE) \ | |
927 | fprintf ((FILE), "\t.set\t.,.+%u\n", (SIZE)) | |
928 | ||
63a1ff86 UW |
929 | /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */ |
930 | #define LOCAL_LABEL_PREFIX "." | |
9db1d521 | 931 | |
862a2d83 UW |
932 | /* Either simplify a location expression, or return the original. */ |
933 | #define ASM_SIMPLIFY_DWARF_ADDR(X) \ | |
934 | s390_simplify_dwarf_addr (X) | |
935 | ||
9db1d521 HP |
936 | /* How to refer to registers in assembler output. This sequence is |
937 | indexed by compiler's hard-register-number (see above). */ | |
9db1d521 HP |
938 | #define REGISTER_NAMES \ |
939 | { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ | |
940 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ | |
941 | "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \ | |
942 | "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \ | |
4023fb28 | 943 | "%ap", "%cc", "%fp" \ |
9db1d521 HP |
944 | } |
945 | ||
63a1ff86 | 946 | /* Print operand X (an rtx) in assembler syntax to file FILE. */ |
9db1d521 | 947 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) |
9db1d521 HP |
948 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) |
949 | ||
63a1ff86 UW |
950 | /* Output an element of a case-vector that is absolute. */ |
951 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
952 | do { \ | |
953 | char buf[32]; \ | |
954 | fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \ | |
955 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ | |
956 | assemble_name ((FILE), buf); \ | |
957 | fputc ('\n', (FILE)); \ | |
958 | } while (0) | |
959 | ||
960 | /* Output an element of a case-vector that is relative. */ | |
961 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
962 | do { \ | |
963 | char buf[32]; \ | |
964 | fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \ | |
965 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ | |
966 | assemble_name ((FILE), buf); \ | |
967 | fputc ('-', (FILE)); \ | |
968 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \ | |
969 | assemble_name ((FILE), buf); \ | |
970 | fputc ('\n', (FILE)); \ | |
971 | } while (0) | |
972 | ||
9db1d521 | 973 | |
9db1d521 HP |
974 | /* Constant Pool for all symbols operands which are changed with |
975 | force_const_mem during insn generation (expand_insn). */ | |
976 | ||
9db1d521 HP |
977 | extern int s390_pool_count; |
978 | extern int s390_nr_constants; | |
9db1d521 HP |
979 | |
980 | #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, fndecl, size) \ | |
981 | { \ | |
9db1d521 HP |
982 | struct pool_constant *pool; \ |
983 | \ | |
984 | if (s390_pool_count == -1) \ | |
985 | { \ | |
986 | s390_nr_constants = 0; \ | |
987 | for (pool = first_pool; pool; pool = pool->next) \ | |
988 | if (pool->mark) s390_nr_constants++; \ | |
989 | return; \ | |
990 | } \ | |
9db1d521 HP |
991 | } |
992 | ||
9db1d521 | 993 | #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, EXP, MODE, ALIGN, LABELNO, WIN) \ |
c8af3574 | 994 | { \ |
b2ccb744 | 995 | fprintf (FILE, ".LC%d:\n", LABELNO); \ |
c8af3574 RH |
996 | \ |
997 | /* Output the value of the constant itself. */ \ | |
998 | switch (GET_MODE_CLASS (MODE)) \ | |
999 | { \ | |
1000 | case MODE_FLOAT: \ | |
1001 | if (GET_CODE (EXP) != CONST_DOUBLE) \ | |
1002 | abort (); \ | |
1003 | \ | |
b216cd4a ZW |
1004 | REAL_VALUE_FROM_CONST_DOUBLE (r, EXP); \ |
1005 | assemble_real (r, MODE, ALIGN); \ | |
c8af3574 RH |
1006 | break; \ |
1007 | \ | |
1008 | case MODE_INT: \ | |
1009 | case MODE_PARTIAL_INT: \ | |
1010 | if (flag_pic \ | |
1011 | && (GET_CODE (EXP) == CONST \ | |
1012 | || GET_CODE (EXP) == SYMBOL_REF \ | |
1013 | || GET_CODE (EXP) == LABEL_REF )) \ | |
1014 | { \ | |
301d03af | 1015 | fputs (integer_asm_op (UNITS_PER_WORD, TRUE), FILE); \ |
c8af3574 RH |
1016 | s390_output_symbolic_const (FILE, EXP); \ |
1017 | fputc ('\n', (FILE)); \ | |
1018 | } \ | |
1019 | else \ | |
4023fb28 UW |
1020 | { \ |
1021 | assemble_integer (EXP, GET_MODE_SIZE (MODE), ALIGN, 1); \ | |
1022 | if (GET_MODE_SIZE (MODE) == 1) \ | |
1023 | ASM_OUTPUT_SKIP ((FILE), 1); \ | |
1024 | } \ | |
c8af3574 RH |
1025 | break; \ |
1026 | \ | |
1027 | default: \ | |
1028 | abort (); \ | |
1029 | } \ | |
1030 | goto WIN; \ | |
9db1d521 HP |
1031 | } |
1032 | ||
862a2d83 UW |
1033 | |
1034 | /* Miscellaneous parameters. */ | |
1035 | ||
1036 | /* Define the codes that are matched by predicates in aux-output.c. */ | |
1037 | #define PREDICATE_CODES \ | |
1038 | {"s_operand", { SUBREG, MEM }}, \ | |
1039 | {"s_imm_operand", { CONST_INT, CONST_DOUBLE, SUBREG, MEM }}, \ | |
1040 | {"bras_sym_operand",{ SYMBOL_REF, CONST }}, \ | |
1041 | {"larl_operand", { SYMBOL_REF, CONST, CONST_INT, CONST_DOUBLE }}, \ | |
1042 | {"load_multiple_operation", {PARALLEL}}, \ | |
1043 | {"store_multiple_operation", {PARALLEL}}, \ | |
1044 | {"const0_operand", { CONST_INT, CONST_DOUBLE }}, \ | |
1045 | {"consttable_operand", { SYMBOL_REF, LABEL_REF, CONST, \ | |
1046 | CONST_INT, CONST_DOUBLE }}, \ | |
1047 | {"s390_plus_operand", { PLUS }}, | |
1048 | ||
1049 | /* Specify the machine mode that this machine uses for the index in the | |
1050 | tablejump instruction. */ | |
1051 | #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) | |
1052 | ||
1053 | /* Load from integral MODE < SI from memory into register makes sign_extend | |
1054 | or zero_extend | |
1055 | In our case sign_extension happens for Halfwords, other no extension. */ | |
1056 | #define LOAD_EXTEND_OP(MODE) \ | |
1057 | (TARGET_64BIT ? ((MODE) == QImode ? ZERO_EXTEND : \ | |
1058 | (MODE) == HImode ? SIGN_EXTEND : NIL) \ | |
1059 | : ((MODE) == HImode ? SIGN_EXTEND : NIL)) | |
1060 | ||
1061 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits | |
1062 | is done just by pretending it is already truncated. */ | |
1063 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1064 | ||
1065 | /* Specify the machine mode that pointers have. | |
1066 | After generation of rtl, the compiler makes no further distinction | |
1067 | between pointers and any other objects of this machine mode. */ | |
1068 | #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode)) | |
1069 | ||
1070 | /* A function address in a call instruction is a byte address (for | |
1071 | indexing purposes) so give the MEM rtx a byte's mode. */ | |
1072 | #define FUNCTION_MODE QImode | |
1073 | ||
1074 | /* This macro definition sets up a default value for `main' to return. */ | |
1075 | #define DEFAULT_MAIN_RETURN c_expand_return (integer_zero_node) | |
1076 | ||
c3cc6b78 UW |
1077 | /* In rare cases, correct code generation requires extra machine dependent |
1078 | processing between the second jump optimization pass and delayed branch | |
1079 | scheduling. On those machines, define this macro as a C statement to act on | |
1080 | the code starting at INSN. */ | |
c3cc6b78 UW |
1081 | #define MACHINE_DEPENDENT_REORG(INSN) s390_machine_dependent_reorg (INSN) |
1082 | ||
9db1d521 | 1083 | #endif |