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9db1d521 | 1 | /* Definitions of target machine for GNU compiler, for IBM S/390 |
a5544970 | 2 | Copyright (C) 1999-2019 Free Software Foundation, Inc. |
9db1d521 | 3 | Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
0ff3dcd6 AK |
4 | Ulrich Weigand (uweigand@de.ibm.com). |
5 | Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 6 | |
58add37a | 7 | This file is part of GCC. |
9db1d521 | 8 | |
58add37a UW |
9 | GCC is free software; you can redistribute it and/or modify it under |
10 | the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | version. |
13 | ||
14 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | for more details. | |
9db1d521 HP |
18 | |
19 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. */ | |
9db1d521 HP |
22 | |
23 | #ifndef _S390_H | |
24 | #define _S390_H | |
25 | ||
f13e0d4e UW |
26 | /* Optional architectural facilities supported by the processor. */ |
27 | ||
28 | enum processor_flags | |
29 | { | |
30 | PF_IEEE_FLOAT = 1, | |
31 | PF_ZARCH = 2, | |
ec24698e | 32 | PF_LONG_DISPLACEMENT = 4, |
85dae55a | 33 | PF_EXTIMM = 8, |
93538e8e | 34 | PF_DFP = 16, |
65b1d8ea | 35 | PF_Z10 = 32, |
22ac2c2f | 36 | PF_Z196 = 64, |
5a3fe9b6 | 37 | PF_ZEC12 = 128, |
55ac540c AK |
38 | PF_TX = 256, |
39 | PF_Z13 = 512, | |
6654e96f | 40 | PF_VX = 1024, |
e9e8efc9 | 41 | PF_Z14 = 2048, |
511ea153 AK |
42 | PF_VXE = 4096, |
43 | PF_VXE2 = 8192, | |
44 | PF_ARCH13 = 16384 | |
f13e0d4e UW |
45 | }; |
46 | ||
90c6fd8a AK |
47 | /* This is necessary to avoid a warning about comparing different enum |
48 | types. */ | |
375a6bc6 | 49 | #define s390_tune_attr ((enum attr_cpu)(s390_tune > PROCESSOR_8561_ARCH13 ? PROCESSOR_8561_ARCH13 : s390_tune )) |
90c6fd8a | 50 | |
963fc8d0 AK |
51 | /* These flags indicate that the generated code should run on a cpu |
52 | providing the respective hardware facility regardless of the | |
53 | current cpu mode (ESA or z/Architecture). */ | |
54 | ||
f13e0d4e UW |
55 | #define TARGET_CPU_IEEE_FLOAT \ |
56 | (s390_arch_flags & PF_IEEE_FLOAT) | |
ec47b086 DV |
57 | #define TARGET_CPU_IEEE_FLOAT_P(opts) \ |
58 | (opts->x_s390_arch_flags & PF_IEEE_FLOAT) | |
f13e0d4e UW |
59 | #define TARGET_CPU_LONG_DISPLACEMENT \ |
60 | (s390_arch_flags & PF_LONG_DISPLACEMENT) | |
ec47b086 DV |
61 | #define TARGET_CPU_LONG_DISPLACEMENT_P(opts) \ |
62 | (opts->x_s390_arch_flags & PF_LONG_DISPLACEMENT) | |
ec24698e | 63 | #define TARGET_CPU_EXTIMM \ |
ec47b086 DV |
64 | (s390_arch_flags & PF_EXTIMM) |
65 | #define TARGET_CPU_EXTIMM_P(opts) \ | |
66 | (opts->x_s390_arch_flags & PF_EXTIMM) | |
85dae55a | 67 | #define TARGET_CPU_DFP \ |
ec47b086 DV |
68 | (s390_arch_flags & PF_DFP) |
69 | #define TARGET_CPU_DFP_P(opts) \ | |
70 | (opts->x_s390_arch_flags & PF_DFP) | |
93538e8e | 71 | #define TARGET_CPU_Z10 \ |
ec47b086 DV |
72 | (s390_arch_flags & PF_Z10) |
73 | #define TARGET_CPU_Z10_P(opts) \ | |
74 | (opts->x_s390_arch_flags & PF_Z10) | |
65b1d8ea | 75 | #define TARGET_CPU_Z196 \ |
ec47b086 DV |
76 | (s390_arch_flags & PF_Z196) |
77 | #define TARGET_CPU_Z196_P(opts) \ | |
78 | (opts->x_s390_arch_flags & PF_Z196) | |
22ac2c2f | 79 | #define TARGET_CPU_ZEC12 \ |
ec47b086 DV |
80 | (s390_arch_flags & PF_ZEC12) |
81 | #define TARGET_CPU_ZEC12_P(opts) \ | |
82 | (opts->x_s390_arch_flags & PF_ZEC12) | |
5a3fe9b6 | 83 | #define TARGET_CPU_HTM \ |
ec47b086 DV |
84 | (s390_arch_flags & PF_TX) |
85 | #define TARGET_CPU_HTM_P(opts) \ | |
86 | (opts->x_s390_arch_flags & PF_TX) | |
55ac540c | 87 | #define TARGET_CPU_Z13 \ |
ec47b086 DV |
88 | (s390_arch_flags & PF_Z13) |
89 | #define TARGET_CPU_Z13_P(opts) \ | |
6654e96f | 90 | (opts->x_s390_arch_flags & PF_Z13) |
55ac540c | 91 | #define TARGET_CPU_VX \ |
6654e96f | 92 | (s390_arch_flags & PF_VX) |
ec47b086 DV |
93 | #define TARGET_CPU_VX_P(opts) \ |
94 | (opts->x_s390_arch_flags & PF_VX) | |
e9e8efc9 AK |
95 | #define TARGET_CPU_Z14 \ |
96 | (s390_arch_flags & PF_Z14) | |
97 | #define TARGET_CPU_Z14_P(opts) \ | |
98 | (opts->x_s390_arch_flags & PF_Z14) | |
6654e96f AK |
99 | #define TARGET_CPU_VXE \ |
100 | (s390_arch_flags & PF_VXE) | |
101 | #define TARGET_CPU_VXE_P(opts) \ | |
102 | (opts->x_s390_arch_flags & PF_VXE) | |
511ea153 AK |
103 | #define TARGET_CPU_ARCH13 \ |
104 | (s390_arch_flags & PF_ARCH13) | |
105 | #define TARGET_CPU_ARCH13_P(opts) \ | |
106 | (opts->x_s390_arch_flags & PF_ARCH13) | |
107 | #define TARGET_CPU_VXE2 \ | |
108 | (s390_arch_flags & PF_VXE2) | |
109 | #define TARGET_CPU_VXE2_P(opts) \ | |
110 | (opts->x_s390_arch_flags & PF_VXE2) | |
ec47b086 DV |
111 | |
112 | #define TARGET_HARD_FLOAT_P(opts) (!TARGET_SOFT_FLOAT_P(opts)) | |
f13e0d4e | 113 | |
963fc8d0 AK |
114 | /* These flags indicate that the generated code should run on a cpu |
115 | providing the respective hardware facility when run in | |
116 | z/Architecture mode. */ | |
117 | ||
f13e0d4e | 118 | #define TARGET_LONG_DISPLACEMENT \ |
ec47b086 DV |
119 | (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT) |
120 | #define TARGET_LONG_DISPLACEMENT_P(opts) \ | |
121 | (TARGET_ZARCH_P (opts->x_target_flags) \ | |
122 | && TARGET_CPU_LONG_DISPLACEMENT_P (opts)) | |
ec24698e | 123 | #define TARGET_EXTIMM \ |
ec47b086 DV |
124 | (TARGET_ZARCH && TARGET_CPU_EXTIMM) |
125 | #define TARGET_EXTIMM_P(opts) \ | |
126 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_EXTIMM_P (opts)) | |
85dae55a | 127 | #define TARGET_DFP \ |
ec47b086 DV |
128 | (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT) |
129 | #define TARGET_DFP_P(opts) \ | |
130 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_DFP_P (opts) \ | |
131 | && TARGET_HARD_FLOAT_P (opts->x_target_flags)) | |
93538e8e | 132 | #define TARGET_Z10 \ |
ec47b086 DV |
133 | (TARGET_ZARCH && TARGET_CPU_Z10) |
134 | #define TARGET_Z10_P(opts) \ | |
135 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z10_P (opts)) | |
65b1d8ea | 136 | #define TARGET_Z196 \ |
ec47b086 DV |
137 | (TARGET_ZARCH && TARGET_CPU_Z196) |
138 | #define TARGET_Z196_P(opts) \ | |
139 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z196_P (opts)) | |
22ac2c2f | 140 | #define TARGET_ZEC12 \ |
ec47b086 DV |
141 | (TARGET_ZARCH && TARGET_CPU_ZEC12) |
142 | #define TARGET_ZEC12_P(opts) \ | |
143 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_ZEC12_P (opts)) | |
167f68ed | 144 | #define TARGET_HTM (TARGET_OPT_HTM) |
ec47b086 | 145 | #define TARGET_HTM_P(opts) (TARGET_OPT_HTM_P (opts->x_target_flags)) |
55ac540c | 146 | #define TARGET_Z13 \ |
ec47b086 DV |
147 | (TARGET_ZARCH && TARGET_CPU_Z13) |
148 | #define TARGET_Z13_P(opts) \ | |
149 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z13_P (opts)) | |
55ac540c | 150 | #define TARGET_VX \ |
ec47b086 DV |
151 | (TARGET_ZARCH && TARGET_CPU_VX && TARGET_OPT_VX && TARGET_HARD_FLOAT) |
152 | #define TARGET_VX_P(opts) \ | |
153 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_VX_P (opts) \ | |
154 | && TARGET_OPT_VX_P (opts->x_target_flags) \ | |
155 | && TARGET_HARD_FLOAT_P (opts->x_target_flags)) | |
e9e8efc9 AK |
156 | #define TARGET_Z14 (TARGET_ZARCH && TARGET_CPU_Z14) |
157 | #define TARGET_Z14_P(opts) \ | |
158 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z14_P (opts)) | |
6654e96f AK |
159 | #define TARGET_VXE \ |
160 | (TARGET_VX && TARGET_CPU_VXE) | |
161 | #define TARGET_VXE_P(opts) \ | |
162 | (TARGET_VX_P (opts) && TARGET_CPU_VXE_P (opts)) | |
511ea153 AK |
163 | #define TARGET_ARCH13 (TARGET_ZARCH && TARGET_CPU_ARCH13) |
164 | #define TARGET_ARCH13_P(opts) \ | |
165 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_ARCH13_P (opts)) | |
166 | #define TARGET_VXE2 \ | |
167 | (TARGET_VX && TARGET_CPU_VXE2) | |
168 | #define TARGET_VXE2_P(opts) \ | |
169 | (TARGET_VX_P (opts) && TARGET_CPU_VXE2_P (opts)) | |
ec47b086 DV |
170 | |
171 | #ifdef HAVE_AS_MACHINE_MACHINEMODE | |
172 | #define S390_USE_TARGET_ATTRIBUTE 1 | |
173 | #else | |
174 | #define S390_USE_TARGET_ATTRIBUTE 0 | |
175 | #endif | |
176 | ||
177 | #ifdef HAVE_AS_ARCHITECTURE_MODIFIERS | |
178 | #define S390_USE_ARCHITECTURE_MODIFIERS 1 | |
179 | #else | |
180 | #define S390_USE_ARCHITECTURE_MODIFIERS 0 | |
181 | #endif | |
182 | ||
183 | #if S390_USE_TARGET_ATTRIBUTE | |
184 | /* For switching between functions with different target attributes. */ | |
185 | #define SWITCHABLE_TARGET 1 | |
186 | #endif | |
65b1d8ea | 187 | |
089b05b1 DV |
188 | #define TARGET_SUPPORTS_WIDE_INT 1 |
189 | ||
55ac540c AK |
190 | /* Use the ABI introduced with IBM z13: |
191 | - pass vector arguments <= 16 bytes in VRs | |
192 | - align *all* vector types to 8 bytes */ | |
193 | #define TARGET_VX_ABI TARGET_VX | |
65b1d8ea AK |
194 | |
195 | #define TARGET_AVOID_CMP_AND_BRANCH (s390_tune == PROCESSOR_2817_Z196) | |
42c78618 | 196 | |
4de3a1e1 AK |
197 | /* Issue a write prefetch for the +4 cache line. */ |
198 | #define TARGET_SETMEM_PREFETCH_DISTANCE 1024 | |
199 | ||
200 | /* Expand to a C expressions evaluating to true if a setmem to VAL of | |
201 | length LEN should be emitted using prefetch instructions. */ | |
202 | #define TARGET_SETMEM_PFD(VAL,LEN) \ | |
203 | (TARGET_Z10 \ | |
204 | && (s390_tune < PROCESSOR_2964_Z13 || (VAL) != const0_rtx) \ | |
205 | && (!CONST_INT_P (LEN) || INTVAL ((LEN)) > TARGET_SETMEM_PREFETCH_DISTANCE)) | |
206 | ||
862a2d83 | 207 | /* Run-time target specification. */ |
9db1d521 | 208 | |
a771c4b3 UW |
209 | /* Defaults for option flags defined only on some subtargets. */ |
210 | #ifndef TARGET_TPF_PROFILING | |
211 | #define TARGET_TPF_PROFILING 0 | |
212 | #endif | |
213 | ||
4798630c D |
214 | /* This will be overridden by OS headers. */ |
215 | #define TARGET_TPF 0 | |
216 | ||
862a2d83 | 217 | /* Target CPU builtins. */ |
3af82a61 | 218 | #define TARGET_CPU_CPP_BUILTINS() s390_cpu_cpp_builtins (pfile) |
9db1d521 | 219 | |
b4c522fa IB |
220 | /* Target CPU versions for D. */ |
221 | #define TARGET_D_CPU_VERSIONS s390_d_target_versions | |
222 | ||
58d10f89 | 223 | #ifdef DEFAULT_TARGET_64BIT |
55ac540c | 224 | #define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP \ |
0ff3dcd6 | 225 | | MASK_OPT_HTM | MASK_OPT_VX) |
58d10f89 | 226 | #else |
85dae55a | 227 | #define TARGET_DEFAULT 0 |
58d10f89 UW |
228 | #endif |
229 | ||
f13e0d4e | 230 | /* Support for configure-time defaults. */ |
0ff3dcd6 | 231 | #define OPTION_DEFAULT_SPECS \ |
f13e0d4e UW |
232 | { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" }, \ |
233 | { "arch", "%{!march=*:-march=%(VALUE)}" }, \ | |
4723f0fb | 234 | { "tune", "%{!mtune=*:%{!march=*:-mtune=%(VALUE)}}" } |
f13e0d4e | 235 | |
63281f61 | 236 | #ifdef __s390__ |
cb0edc39 DV |
237 | extern const char *s390_host_detect_local_cpu (int argc, const char **argv); |
238 | # define EXTRA_SPEC_FUNCTIONS \ | |
239 | { "local_cpu_detect", s390_host_detect_local_cpu }, | |
240 | ||
b1b5aa2f DV |
241 | #define MARCH_MTUNE_NATIVE_SPECS \ |
242 | "%{mtune=native:%<mtune=native %:local_cpu_detect(tune)} " \ | |
243 | "%{march=native:%<march=native" \ | |
244 | " %:local_cpu_detect(arch %{mesa|mzarch:mesa_mzarch})}" | |
63281f61 DV |
245 | #else |
246 | # define MARCH_MTUNE_NATIVE_SPECS "" | |
247 | #endif | |
cb0edc39 | 248 | |
f13e0d4e | 249 | #ifdef DEFAULT_TARGET_64BIT |
b1b5aa2f | 250 | #define S390_TARGET_BITS_STRING "64" |
f13e0d4e | 251 | #else |
b1b5aa2f DV |
252 | #define S390_TARGET_BITS_STRING "31" |
253 | #endif | |
254 | ||
255 | /* Defaulting rules. */ | |
f13e0d4e | 256 | #define DRIVER_SELF_SPECS \ |
b1b5aa2f DV |
257 | MARCH_MTUNE_NATIVE_SPECS, \ |
258 | "%{!m31:%{!m64:-m" S390_TARGET_BITS_STRING "}}", \ | |
f13e0d4e | 259 | "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ |
6638efce | 260 | "%{!march=*:-march=z900}" |
f13e0d4e | 261 | |
638e37c2 | 262 | /* Constants needed to control the TEST DATA CLASS (TDC) instruction. */ |
0387c142 WG |
263 | #define S390_TDC_POSITIVE_ZERO (1 << 11) |
264 | #define S390_TDC_NEGATIVE_ZERO (1 << 10) | |
265 | #define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER (1 << 9) | |
266 | #define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER (1 << 8) | |
267 | #define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER (1 << 7) | |
268 | #define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER (1 << 6) | |
269 | #define S390_TDC_POSITIVE_INFINITY (1 << 5) | |
270 | #define S390_TDC_NEGATIVE_INFINITY (1 << 4) | |
271 | #define S390_TDC_POSITIVE_QUIET_NAN (1 << 3) | |
272 | #define S390_TDC_NEGATIVE_QUIET_NAN (1 << 2) | |
273 | #define S390_TDC_POSITIVE_SIGNALING_NAN (1 << 1) | |
274 | #define S390_TDC_NEGATIVE_SIGNALING_NAN (1 << 0) | |
275 | ||
276 | /* The following values are different for DFP. */ | |
277 | #define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9) | |
278 | #define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8) | |
279 | #define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER (1 << 7) | |
280 | #define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER (1 << 6) | |
281 | ||
f4aa3848 | 282 | /* For signbit, the BFP-DFP-difference makes no difference. */ |
0f67fa83 | 283 | #define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \ |
0ff3dcd6 AK |
284 | | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \ |
285 | | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\ | |
286 | | S390_TDC_NEGATIVE_INFINITY \ | |
287 | | S390_TDC_NEGATIVE_QUIET_NAN \ | |
0f67fa83 WG |
288 | | S390_TDC_NEGATIVE_SIGNALING_NAN ) |
289 | ||
638e37c2 WG |
290 | #define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \ |
291 | | S390_TDC_NEGATIVE_INFINITY ) | |
9db1d521 HP |
292 | |
293 | /* Target machine storage layout. */ | |
294 | ||
862a2d83 | 295 | /* Everything is big-endian. */ |
9db1d521 | 296 | #define BITS_BIG_ENDIAN 1 |
9db1d521 | 297 | #define BYTES_BIG_ENDIAN 1 |
9db1d521 HP |
298 | #define WORDS_BIG_ENDIAN 1 |
299 | ||
9602b6a1 AK |
300 | #define STACK_SIZE_MODE (Pmode) |
301 | ||
fe86047c | 302 | #ifndef IN_LIBGCC2 |
9602b6a1 AK |
303 | |
304 | /* Width of a word, in units (bytes). */ | |
305 | #define UNITS_PER_WORD (TARGET_ZARCH ? 8 : 4) | |
306 | ||
307 | /* Width of a pointer. To be used instead of UNITS_PER_WORD in | |
308 | ABI-relevant contexts. This always matches | |
309 | GET_MODE_SIZE (Pmode). */ | |
310 | #define UNITS_PER_LONG (TARGET_64BIT ? 8 : 4) | |
311 | #define MIN_UNITS_PER_WORD 4 | |
312 | #define MAX_BITS_PER_WORD 64 | |
313 | #else | |
314 | ||
315 | /* In libgcc, UNITS_PER_WORD has ABI-relevant effects, e.g. whether | |
316 | the library should export TImode functions or not. Thus, we have | |
317 | to redefine UNITS_PER_WORD depending on __s390x__ for libgcc. */ | |
318 | #ifdef __s390x__ | |
319 | #define UNITS_PER_WORD 8 | |
320 | #else | |
321 | #define UNITS_PER_WORD 4 | |
322 | #endif | |
fe86047c | 323 | #endif |
9602b6a1 AK |
324 | |
325 | /* Width of a pointer, in bits. */ | |
326 | #define POINTER_SIZE (TARGET_64BIT ? 64 : 32) | |
9db1d521 | 327 | |
9db1d521 | 328 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
9db1d521 HP |
329 | #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32) |
330 | ||
331 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
9db1d521 HP |
332 | #define STACK_BOUNDARY 64 |
333 | ||
334 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
d0de9e13 | 335 | #define FUNCTION_BOUNDARY 64 |
9db1d521 HP |
336 | |
337 | /* There is no point aligning anything to a rounder boundary than this. */ | |
9db1d521 HP |
338 | #define BIGGEST_ALIGNMENT 64 |
339 | ||
340 | /* Alignment of field after `int : 0' in a structure. */ | |
9db1d521 HP |
341 | #define EMPTY_FIELD_BOUNDARY 32 |
342 | ||
f710504c | 343 | /* Alignment on even addresses for LARL instruction. */ |
df8a1d28 | 344 | #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) |
9db1d521 | 345 | |
862a2d83 | 346 | /* Alignment is not required by the hardware. */ |
9db1d521 HP |
347 | #define STRICT_ALIGNMENT 0 |
348 | ||
862a2d83 UW |
349 | /* Mode of stack savearea. |
350 | FUNCTION is VOIDmode because calling convention maintains SP. | |
351 | BLOCK needs Pmode for SP. | |
352 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ | |
2d6744f4 AK |
353 | #define STACK_SAVEAREA_MODE(LEVEL) \ |
354 | ((LEVEL) == SAVE_FUNCTION ? VOIDmode \ | |
355 | : (LEVEL) == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode) | |
862a2d83 | 356 | |
9db1d521 | 357 | |
862a2d83 | 358 | /* Type layout. */ |
9db1d521 | 359 | |
862a2d83 UW |
360 | /* Sizes in bits of the source language data types. */ |
361 | #define SHORT_TYPE_SIZE 16 | |
362 | #define INT_TYPE_SIZE 32 | |
363 | #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) | |
862a2d83 UW |
364 | #define LONG_LONG_TYPE_SIZE 64 |
365 | #define FLOAT_TYPE_SIZE 32 | |
366 | #define DOUBLE_TYPE_SIZE 64 | |
f61a2c7d AK |
367 | #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) |
368 | ||
f61a2c7d AK |
369 | /* Work around target_flags dependency in ada/targtyps.c. */ |
370 | #define WIDEST_HARDWARE_FP_SIZE 64 | |
862a2d83 UW |
371 | |
372 | /* We use "unsigned char" as default. */ | |
373 | #define DEFAULT_SIGNED_CHAR 0 | |
374 | ||
375 | ||
376 | /* Register usage. */ | |
377 | ||
378 | /* We have 16 general purpose registers (registers 0-15), | |
379 | and 16 floating point registers (registers 16-31). | |
380 | (On non-IEEE machines, we have only 4 fp registers.) | |
c7453384 | 381 | |
862a2d83 UW |
382 | Amongst the general purpose registers, some are used |
383 | for specific purposes: | |
384 | GPR 11: Hard frame pointer (if needed) | |
385 | GPR 12: Global offset table pointer (if needed) | |
386 | GPR 13: Literal pool base register | |
387 | GPR 14: Return address register | |
388 | GPR 15: Stack pointer | |
c7453384 | 389 | |
c5aa1d12 | 390 | Registers 32-35 are 'fake' hard registers that do not |
862a2d83 UW |
391 | correspond to actual hardware: |
392 | Reg 32: Argument pointer | |
393 | Reg 33: Condition code | |
f4aa3848 | 394 | Reg 34: Frame pointer |
c5aa1d12 | 395 | Reg 35: Return address pointer |
862a2d83 | 396 | |
f4aa3848 | 397 | Registers 36 and 37 are mapped to access registers |
085261c8 AK |
398 | 0 and 1, used to implement thread-local storage. |
399 | ||
400 | Reg 38-53: Vector registers v16-v31 */ | |
c5aa1d12 | 401 | |
085261c8 | 402 | #define FIRST_PSEUDO_REGISTER 54 |
862a2d83 UW |
403 | |
404 | /* Standard register usage. */ | |
8e509cf9 UW |
405 | #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16) |
406 | #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16) | |
142cd70f | 407 | #define FP_REGNO_P(N) ((N) >= 16 && (N) < 32) |
8e509cf9 | 408 | #define CC_REGNO_P(N) ((N) == 33) |
a38e09bc | 409 | #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34 || (N) == 35) |
c5aa1d12 | 410 | #define ACCESS_REGNO_P(N) ((N) == 36 || (N) == 37) |
085261c8 AK |
411 | #define VECTOR_NOFP_REGNO_P(N) ((N) >= 38 && (N) <= 53) |
412 | #define VECTOR_REGNO_P(N) (FP_REGNO_P (N) || VECTOR_NOFP_REGNO_P (N)) | |
8e509cf9 UW |
413 | |
414 | #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) | |
415 | #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X))) | |
416 | #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) | |
417 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) | |
4888ec5d | 418 | #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X))) |
c5aa1d12 | 419 | #define ACCESS_REG_P(X) (REG_P (X) && ACCESS_REGNO_P (REGNO (X))) |
085261c8 AK |
420 | #define VECTOR_NOFP_REG_P(X) (REG_P (X) && VECTOR_NOFP_REGNO_P (REGNO (X))) |
421 | #define VECTOR_REG_P(X) (REG_P (X) && VECTOR_REGNO_P (REGNO (X))) | |
9db1d521 | 422 | |
862a2d83 | 423 | /* Set up fixed registers and calling convention: |
9db1d521 | 424 | |
862a2d83 UW |
425 | GPRs 0-5 are always call-clobbered, |
426 | GPRs 6-15 are always call-saved. | |
427 | GPR 12 is fixed if used as GOT pointer. | |
428 | GPR 13 is always fixed (as literal pool pointer). | |
545d16ff | 429 | GPR 14 is always fixed on S/390 machines (as return address). |
862a2d83 UW |
430 | GPR 15 is always fixed (as stack pointer). |
431 | The 'fake' hard registers are call-clobbered and fixed. | |
c5aa1d12 | 432 | The access registers are call-saved and fixed. |
9db1d521 | 433 | |
862a2d83 UW |
434 | On 31-bit, FPRs 18-19 are call-clobbered; |
435 | on 64-bit, FPRs 24-31 are call-clobbered. | |
085261c8 AK |
436 | The remaining FPRs are call-saved. |
437 | ||
438 | All non-FP vector registers are call-clobbered v16-v31. */ | |
9db1d521 HP |
439 | |
440 | #define FIXED_REGISTERS \ | |
0ff3dcd6 AK |
441 | { 0, 0, 0, 0, \ |
442 | 0, 0, 0, 0, \ | |
443 | 0, 0, 0, 0, \ | |
9db1d521 | 444 | 0, 1, 1, 1, \ |
0ff3dcd6 AK |
445 | 0, 0, 0, 0, \ |
446 | 0, 0, 0, 0, \ | |
447 | 0, 0, 0, 0, \ | |
448 | 0, 0, 0, 0, \ | |
c5aa1d12 | 449 | 1, 1, 1, 1, \ |
085261c8 | 450 | 1, 1, \ |
0ff3dcd6 AK |
451 | 0, 0, 0, 0, \ |
452 | 0, 0, 0, 0, \ | |
453 | 0, 0, 0, 0, \ | |
085261c8 | 454 | 0, 0, 0, 0 } |
9db1d521 | 455 | |
4023fb28 | 456 | #define CALL_REALLY_USED_REGISTERS \ |
0ff3dcd6 AK |
457 | { 1, 1, 1, 1, /* r0 - r15 */ \ |
458 | 1, 1, 0, 0, \ | |
459 | 0, 0, 0, 0, \ | |
4023fb28 | 460 | 0, 0, 0, 0, \ |
0ff3dcd6 AK |
461 | 1, 1, 1, 1, /* f0 (16) - f15 (31) */ \ |
462 | 1, 1, 1, 1, \ | |
463 | 1, 1, 1, 1, \ | |
464 | 1, 1, 1, 1, \ | |
085261c8 | 465 | 1, 1, 1, 1, /* arg, cc, fp, ret addr */ \ |
0ff3dcd6 AK |
466 | 0, 0, /* a0 (36), a1 (37) */ \ |
467 | 1, 1, 1, 1, /* v16 (38) - v23 (45) */ \ | |
c5aa1d12 | 468 | 1, 1, 1, 1, \ |
0ff3dcd6 | 469 | 1, 1, 1, 1, /* v24 (46) - v31 (53) */ \ |
085261c8 | 470 | 1, 1, 1, 1 } |
9db1d521 | 471 | |
862a2d83 | 472 | /* Preferred register allocation order. */ |
085261c8 AK |
473 | #define REG_ALLOC_ORDER \ |
474 | { 1, 2, 3, 4, 5, 0, 12, 11, 10, 9, 8, 7, 6, 14, 13, \ | |
475 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
476 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
0ff3dcd6 | 477 | 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, \ |
085261c8 | 478 | 15, 32, 33, 34, 35, 36, 37 } |
9db1d521 | 479 | |
9db1d521 | 480 | |
74aa8b4b | 481 | #define HARD_REGNO_RENAME_OK(FROM, TO) \ |
2d6744f4 | 482 | s390_hard_regno_rename_ok ((FROM), (TO)) |
7633f08e | 483 | |
862a2d83 UW |
484 | /* Maximum number of registers to represent a value of mode MODE |
485 | in a register of class CLASS. */ | |
0ff3dcd6 | 486 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
74aa8b4b | 487 | s390_class_max_nregs ((CLASS), (MODE)) |
4023fb28 | 488 | |
eca98038 AK |
489 | /* We can reverse a CC mode safely if we know whether it comes from a |
490 | floating point compare or not. With the vector modes it is encoded | |
491 | as part of the mode. | |
492 | FIXME: It might make sense to do this for other cc modes as well. */ | |
493 | #define REVERSIBLE_CC_MODE(MODE) \ | |
494 | ((MODE) == CCVIALLmode || (MODE) == CCVIANYmode \ | |
495 | || (MODE) == CCVFALLmode || (MODE) == CCVFANYmode) | |
496 | ||
497 | /* Given a condition code and a mode, return the inverse condition. */ | |
498 | #define REVERSE_CONDITION(CODE, MODE) s390_reverse_condition (MODE, CODE) | |
499 | ||
500 | ||
862a2d83 | 501 | /* Register classes. */ |
c7453384 | 502 | |
862a2d83 UW |
503 | /* We use the following register classes: |
504 | GENERAL_REGS All general purpose registers | |
505 | ADDR_REGS All general purpose registers except %r0 | |
0ff3dcd6 | 506 | (These registers can be used in address generation) |
862a2d83 | 507 | FP_REGS All floating point registers |
c5aa1d12 UW |
508 | CC_REGS The condition code register |
509 | ACCESS_REGS The access registers | |
c7453384 | 510 | |
862a2d83 UW |
511 | GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS |
512 | ADDR_FP_REGS Union of ADDR_REGS and FP_REGS | |
c5aa1d12 UW |
513 | GENERAL_CC_REGS Union of GENERAL_REGS and CC_REGS |
514 | ADDR_CC_REGS Union of ADDR_REGS and CC_REGS | |
c7453384 | 515 | |
862a2d83 UW |
516 | NO_REGS No registers |
517 | ALL_REGS All registers | |
c7453384 | 518 | |
862a2d83 | 519 | Note that the 'fake' frame pointer and argument pointer registers |
c5aa1d12 | 520 | are included amongst the address registers here. */ |
9db1d521 HP |
521 | |
522 | enum reg_class | |
523 | { | |
c5aa1d12 | 524 | NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS, |
f4aa3848 | 525 | ADDR_CC_REGS, GENERAL_CC_REGS, |
4023fb28 | 526 | FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, |
085261c8 | 527 | VEC_REGS, ADDR_VEC_REGS, GENERAL_VEC_REGS, |
4023fb28 | 528 | ALL_REGS, LIM_REG_CLASSES |
9db1d521 | 529 | }; |
9db1d521 HP |
530 | #define N_REG_CLASSES (int) LIM_REG_CLASSES |
531 | ||
c5aa1d12 UW |
532 | #define REG_CLASS_NAMES \ |
533 | { "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS", \ | |
534 | "ADDR_CC_REGS", "GENERAL_CC_REGS", \ | |
085261c8 AK |
535 | "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", \ |
536 | "VEC_REGS", "ADDR_VEC_REGS", "GENERAL_VEC_REGS", \ | |
537 | "ALL_REGS" } | |
9db1d521 | 538 | |
862a2d83 | 539 | /* Class -> register mapping. */ |
085261c8 AK |
540 | #define REG_CLASS_CONTENTS \ |
541 | { \ | |
9db1d521 | 542 | { 0x00000000, 0x00000000 }, /* NO_REGS */ \ |
9dc62c00 | 543 | { 0x00000000, 0x00000002 }, /* CC_REGS */ \ |
a38e09bc AK |
544 | { 0x0000fffe, 0x0000000d }, /* ADDR_REGS */ \ |
545 | { 0x0000ffff, 0x0000000d }, /* GENERAL_REGS */ \ | |
c5aa1d12 | 546 | { 0x00000000, 0x00000030 }, /* ACCESS_REGS */ \ |
9dc62c00 AK |
547 | { 0x0000fffe, 0x0000000f }, /* ADDR_CC_REGS */ \ |
548 | { 0x0000ffff, 0x0000000f }, /* GENERAL_CC_REGS */ \ | |
9db1d521 | 549 | { 0xffff0000, 0x00000000 }, /* FP_REGS */ \ |
a38e09bc AK |
550 | { 0xfffffffe, 0x0000000d }, /* ADDR_FP_REGS */ \ |
551 | { 0xffffffff, 0x0000000d }, /* GENERAL_FP_REGS */ \ | |
085261c8 AK |
552 | { 0xffff0000, 0x003fffc0 }, /* VEC_REGS */ \ |
553 | { 0xfffffffe, 0x003fffcd }, /* ADDR_VEC_REGS */ \ | |
554 | { 0xffffffff, 0x003fffcd }, /* GENERAL_VEC_REGS */ \ | |
555 | { 0xffffffff, 0x003fffff }, /* ALL_REGS */ \ | |
9db1d521 HP |
556 | } |
557 | ||
058e97ec VM |
558 | /* In some case register allocation order is not enough for IRA to |
559 | generate a good code. The following macro (if defined) increases | |
560 | cost of REGNO for a pseudo approximately by pseudo usage frequency | |
561 | multiplied by the macro value. | |
562 | ||
563 | We avoid usage of BASE_REGNUM by nonzero macro value because the | |
564 | reload can decide not to use the hard register because some | |
565 | constant was forced to be in memory. */ | |
566 | #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) \ | |
2d6744f4 | 567 | ((regno) != BASE_REGNUM ? 0.0 : 0.5) |
058e97ec | 568 | |
862a2d83 UW |
569 | /* Register -> class mapping. */ |
570 | extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; | |
571 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) | |
9db1d521 | 572 | |
862a2d83 UW |
573 | /* ADDR_REGS can be used as base or index register. */ |
574 | #define INDEX_REG_CLASS ADDR_REGS | |
575 | #define BASE_REG_CLASS ADDR_REGS | |
9db1d521 | 576 | |
862a2d83 UW |
577 | /* Check whether REGNO is a hard register of the suitable class |
578 | or a pseudo register currently allocated to one such. */ | |
579 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
0ff3dcd6 AK |
580 | (((REGNO) < FIRST_PSEUDO_REGISTER \ |
581 | && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \ | |
93fa8428 | 582 | || ADDR_REGNO_P (reg_renumber[REGNO])) |
862a2d83 | 583 | #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) |
9db1d521 | 584 | |
9db1d521 | 585 | |
862a2d83 | 586 | /* Stack layout and calling conventions. */ |
c7453384 | 587 | |
862a2d83 UW |
588 | /* Our stack grows from higher to lower addresses. However, local variables |
589 | are accessed by positive offsets, and function arguments are stored at | |
590 | increasing addresses. */ | |
62f9f30b | 591 | #define STACK_GROWS_DOWNWARD 1 |
63296cb1 | 592 | #define FRAME_GROWS_DOWNWARD 1 |
862a2d83 | 593 | /* #undef ARGS_GROW_DOWNWARD */ |
9db1d521 | 594 | |
862a2d83 UW |
595 | /* The basic stack layout looks like this: the stack pointer points |
596 | to the register save area for called functions. Above that area | |
597 | is the location to place outgoing arguments. Above those follow | |
598 | dynamic allocations (alloca), and finally the local variables. */ | |
9db1d521 | 599 | |
862a2d83 UW |
600 | /* Offset from stack-pointer to first location of outgoing args. */ |
601 | #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96) | |
9db1d521 | 602 | |
862a2d83 UW |
603 | /* Offset from the stack pointer register to an item dynamically |
604 | allocated on the stack, e.g., by `alloca'. */ | |
63296cb1 | 605 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ |
38173d38 | 606 | (STACK_POINTER_OFFSET + crtl->outgoing_args_size) |
9db1d521 | 607 | |
862a2d83 UW |
608 | /* Offset of first parameter from the argument pointer register value. |
609 | We have a fake argument pointer register that points directly to | |
610 | the argument area. */ | |
611 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
9db1d521 | 612 | |
f4aa3848 | 613 | /* Defining this macro makes __builtin_frame_address(0) and |
c6d01079 AK |
614 | __builtin_return_address(0) work with -fomit-frame-pointer. */ |
615 | #define INITIAL_FRAME_ADDRESS_RTX \ | |
0a81f074 | 616 | (plus_constant (Pmode, arg_pointer_rtx, -STACK_POINTER_OFFSET)) |
c6d01079 | 617 | |
c7453384 | 618 | /* The return address of the current frame is retrieved |
4023fb28 UW |
619 | from the initial value of register RETURN_REGNUM. |
620 | For frames farther back, we use the stack slot where | |
621 | the corresponding RETURN_REGNUM register was saved. */ | |
c6d01079 AK |
622 | #define DYNAMIC_CHAIN_ADDRESS(FRAME) \ |
623 | (TARGET_PACKED_STACK ? \ | |
0a81f074 RS |
624 | plus_constant (Pmode, (FRAME), \ |
625 | STACK_POINTER_OFFSET - UNITS_PER_LONG) : (FRAME)) | |
4023fb28 | 626 | |
78791a80 AK |
627 | /* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of |
628 | builtin_frame_address. Otherwise arg pointer - | |
629 | STACK_POINTER_OFFSET would be returned for | |
630 | __builtin_frame_address(0) what might result in an address pointing | |
631 | somewhere into the middle of the local variables since the packed | |
632 | stack layout generally does not need all the bytes in the register | |
633 | save area. */ | |
634 | #define FRAME_ADDR_RTX(FRAME) \ | |
635 | DYNAMIC_CHAIN_ADDRESS ((FRAME)) | |
636 | ||
c6d01079 | 637 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
5d4d885c | 638 | s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME))) |
9db1d521 | 639 | |
862a2d83 | 640 | /* In 31-bit mode, we need to mask off the high bit of return addresses. */ |
a556fd39 | 641 | #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff)) |
9db1d521 | 642 | |
4023fb28 | 643 | |
862a2d83 | 644 | /* Exception handling. */ |
c7453384 | 645 | |
862a2d83 UW |
646 | /* Describe calling conventions for DWARF-2 exception handling. */ |
647 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM) | |
4023fb28 | 648 | #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET |
9db1d521 HP |
649 | #define DWARF_FRAME_RETURN_COLUMN 14 |
650 | ||
651 | /* Describe how we implement __builtin_eh_return. */ | |
652 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM) | |
a38e09bc | 653 | #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx) |
f4aa3848 | 654 | |
18789f4e UW |
655 | /* Select a format to encode pointers in exception handling data. */ |
656 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
657 | (flag_pic \ | |
658 | ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ | |
659 | : DW_EH_PE_absptr) | |
660 | ||
9602b6a1 AK |
661 | /* Register save slot alignment. */ |
662 | #define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_LONG) | |
663 | ||
f276b762 AK |
664 | /* Let the assembler generate debug line info. */ |
665 | #define DWARF2_ASM_LINE_DEBUG_INFO 1 | |
666 | ||
085261c8 AK |
667 | /* Define the dwarf register mapping. |
668 | v16-v31 -> 68-83 | |
669 | rX -> X otherwise */ | |
2d6744f4 AK |
670 | #define DBX_REGISTER_NUMBER(regno) \ |
671 | (((regno) >= 38 && (regno) <= 53) ? (regno) + 30 : (regno)) | |
9db1d521 | 672 | |
862a2d83 | 673 | /* Frame registers. */ |
9db1d521 | 674 | |
862a2d83 UW |
675 | #define STACK_POINTER_REGNUM 15 |
676 | #define FRAME_POINTER_REGNUM 34 | |
677 | #define HARD_FRAME_POINTER_REGNUM 11 | |
678 | #define ARG_POINTER_REGNUM 32 | |
a38e09bc | 679 | #define RETURN_ADDRESS_POINTER_REGNUM 35 |
9db1d521 | 680 | |
c7453384 EC |
681 | /* The static chain must be call-clobbered, but not used for |
682 | function argument passing. As register 1 is clobbered by | |
862a2d83 UW |
683 | the trampoline code, we only have one option. */ |
684 | #define STATIC_CHAIN_REGNUM 0 | |
9db1d521 | 685 | |
862a2d83 UW |
686 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
687 | To avoid ABI incompatibility, this number must not change even as | |
688 | 'fake' hard registers are added or removed. */ | |
689 | #define DWARF_FRAME_REGISTERS 34 | |
9db1d521 | 690 | |
9db1d521 | 691 | |
862a2d83 | 692 | /* Frame pointer and argument pointer elimination. */ |
9db1d521 | 693 | |
7633f08e UW |
694 | #define ELIMINABLE_REGS \ |
695 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
696 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
697 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
698 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
699 | { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
700 | { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
701 | { BASE_REGNUM, BASE_REGNUM }} | |
9db1d521 | 702 | |
91086990 UW |
703 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
704 | (OFFSET) = s390_initial_elimination_offset ((FROM), (TO)) | |
9db1d521 | 705 | |
9db1d521 | 706 | |
862a2d83 | 707 | /* Stack arguments. */ |
c7453384 | 708 | |
862a2d83 UW |
709 | /* We need current_function_outgoing_args to be valid. */ |
710 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
9db1d521 | 711 | |
9db1d521 | 712 | |
862a2d83 | 713 | /* Register arguments. */ |
c7453384 | 714 | |
9db1d521 HP |
715 | typedef struct s390_arg_structure |
716 | { | |
717 | int gprs; /* gpr so far */ | |
718 | int fprs; /* fpr so far */ | |
085261c8 | 719 | int vrs; /* vr so far */ |
9db1d521 HP |
720 | } |
721 | CUMULATIVE_ARGS; | |
722 | ||
07711f53 | 723 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \ |
085261c8 AK |
724 | ((CUM).gprs=0, (CUM).fprs=0, (CUM).vrs=0) |
725 | ||
726 | #define FIRST_VEC_ARG_REGNO 46 | |
727 | #define LAST_VEC_ARG_REGNO 53 | |
9db1d521 | 728 | |
96e2afa8 AK |
729 | /* Arguments can be placed in general registers 2 to 6, or in floating |
730 | point registers 0 and 2 for 31 bit and fprs 0, 2, 4 and 6 for 64 | |
731 | bit. */ | |
085261c8 AK |
732 | #define FUNCTION_ARG_REGNO_P(N) \ |
733 | (((N) >=2 && (N) < 7) || (N) == 16 || (N) == 17 \ | |
734 | || (TARGET_64BIT && ((N) == 18 || (N) == 19)) \ | |
735 | || (TARGET_VX && ((N) >= FIRST_VEC_ARG_REGNO && (N) <= LAST_VEC_ARG_REGNO))) | |
9db1d521 | 736 | |
9db1d521 | 737 | |
085261c8 AK |
738 | /* Only gpr 2, fpr 0, and v24 are ever used as return registers. */ |
739 | #define FUNCTION_VALUE_REGNO_P(N) \ | |
740 | ((N) == 2 || (N) == 16 \ | |
741 | || (TARGET_VX && (N) == FIRST_VEC_ARG_REGNO)) | |
9db1d521 | 742 | |
9db1d521 | 743 | |
862a2d83 | 744 | /* Function entry and exit. */ |
c7453384 | 745 | |
862a2d83 UW |
746 | /* When returning from a function, the stack pointer does not matter. */ |
747 | #define EXIT_IGNORE_STACK 1 | |
9db1d521 | 748 | |
9db1d521 | 749 | |
862a2d83 | 750 | /* Profiling. */ |
9db1d521 | 751 | |
0ff3dcd6 | 752 | #define FUNCTION_PROFILER(FILE, LABELNO) \ |
862a2d83 | 753 | s390_function_profiler ((FILE), ((LABELNO))) |
9db1d521 | 754 | |
c52a375d | 755 | #define PROFILE_BEFORE_PROLOGUE 1 |
9db1d521 | 756 | |
9db1d521 | 757 | |
862a2d83 | 758 | /* Trampolines for nested functions. */ |
9db1d521 | 759 | |
b81ecf6f RH |
760 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 32 : 16) |
761 | #define TRAMPOLINE_ALIGNMENT BITS_PER_WORD | |
9db1d521 | 762 | |
862a2d83 | 763 | /* Addressing modes, and classification of registers for them. */ |
9db1d521 | 764 | |
862a2d83 UW |
765 | /* Recognize any constant value that is a valid address. */ |
766 | #define CONSTANT_ADDRESS_P(X) 0 | |
9db1d521 | 767 | |
862a2d83 UW |
768 | /* Maximum number of registers that can appear in a valid memory address. */ |
769 | #define MAX_REGS_PER_ADDRESS 2 | |
9db1d521 | 770 | |
963fc8d0 | 771 | /* This definition replaces the formerly used 'm' constraint with a |
c6c3dba9 PB |
772 | different constraint letter in order to avoid changing semantics of |
773 | the 'm' constraint when accepting new address formats in | |
774 | TARGET_LEGITIMATE_ADDRESS_P. The constraint letter defined here | |
775 | must not be used in insn definitions or inline assemblies. */ | |
963fc8d0 AK |
776 | #define TARGET_MEM_CONSTRAINT 'e' |
777 | ||
0b540f12 UW |
778 | /* Try a machine-dependent way of reloading an illegitimate address |
779 | operand. If we find one, push the reload and jump to WIN. This | |
780 | macro is used in only one place: `find_reloads_address' in reload.c. */ | |
781 | #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ | |
2d6744f4 AK |
782 | do { \ |
783 | rtx new_rtx = legitimize_reload_address ((AD), (MODE), \ | |
784 | (OPNUM), (int)(TYPE)); \ | |
785 | if (new_rtx) \ | |
786 | { \ | |
787 | (AD) = new_rtx; \ | |
788 | goto WIN; \ | |
789 | } \ | |
790 | } while (0) | |
0b540f12 | 791 | |
862a2d83 | 792 | /* Helper macro for s390.c and s390.md to check for symbolic constants. */ |
2d6744f4 AK |
793 | #define SYMBOLIC_CONST(X) \ |
794 | (GET_CODE (X) == SYMBOL_REF \ | |
795 | || GET_CODE (X) == LABEL_REF \ | |
796 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
9db1d521 | 797 | |
2d6744f4 AK |
798 | #define TLS_SYMBOLIC_CONST(X) \ |
799 | ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \ | |
800 | || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X))) | |
fd3cd001 | 801 | |
9db1d521 | 802 | |
862a2d83 | 803 | /* Condition codes. */ |
9db1d521 | 804 | |
862a2d83 UW |
805 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
806 | return the mode to be used for the comparison. */ | |
807 | #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y)) | |
c7453384 | 808 | |
862a2d83 | 809 | /* Relative costs of operations. */ |
9db1d521 | 810 | |
9db1d521 HP |
811 | /* A C expression for the cost of a branch instruction. A value of 1 |
812 | is the default; other values are interpreted relative to that. */ | |
3d427cc1 | 813 | #define BRANCH_COST(speed_p, predictable_p) s390_branch_cost |
9db1d521 | 814 | |
862a2d83 UW |
815 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
816 | #define SLOW_BYTE_ACCESS 1 | |
817 | ||
c5443745 | 818 | /* An integer expression for the size in bits of the largest integer machine |
f4aa3848 | 819 | mode that should actually be used. We allow pairs of registers. */ |
c5443745 UW |
820 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) |
821 | ||
862a2d83 | 822 | /* The maximum number of bytes that a single instruction can move quickly |
ff482c8d | 823 | between memory and registers or between two memory locations. */ |
9602b6a1 AK |
824 | #define MOVE_MAX (TARGET_ZARCH ? 16 : 8) |
825 | #define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4) | |
862a2d83 | 826 | #define MAX_MOVE_MAX 16 |
9db1d521 | 827 | |
862a2d83 | 828 | /* Don't perform CSE on function addresses. */ |
1e8552c2 | 829 | #define NO_FUNCTION_CSE 1 |
862a2d83 | 830 | |
5f1b2ee6 AK |
831 | /* This value is used in tree-sra to decide whether it might benefical |
832 | to split a struct move into several word-size moves. For S/390 | |
833 | only small values make sense here since struct moves are relatively | |
073a8998 | 834 | cheap thanks to mvc so the small default value chosen for archs |
5f1b2ee6 AK |
835 | with memmove patterns should be ok. But this value is multiplied |
836 | in tree-sra with UNITS_PER_WORD to make a decision so we adjust it | |
837 | here to compensate for that factor since mvc costs exactly the same | |
838 | on 31 and 64 bit. */ | |
e04ad03d | 839 | #define MOVE_RATIO(speed) (TARGET_64BIT? 2 : 4) |
5f1b2ee6 | 840 | |
862a2d83 UW |
841 | |
842 | /* Sections. */ | |
843 | ||
844 | /* Output before read-only data. */ | |
845 | #define TEXT_SECTION_ASM_OP ".text" | |
846 | ||
847 | /* Output before writable (initialized) data. */ | |
848 | #define DATA_SECTION_ASM_OP ".data" | |
849 | ||
850 | /* Output before writable (uninitialized) data. */ | |
851 | #define BSS_SECTION_ASM_OP ".bss" | |
852 | ||
853 | /* S/390 constant pool breaks the devices in crtstuff.c to control section | |
854 | in where code resides. We have to write it as asm code. */ | |
855 | #ifndef __s390x__ | |
856 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
857 | asm (SECTION_OP "\n\ | |
858 | bras\t%r2,1f\n\ | |
859 | 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\ | |
860 | 1: l\t%r3,0(%r2)\n\ | |
861 | bas\t%r14,0(%r3,%r2)\n\ | |
862 | .previous"); | |
863 | #endif | |
63a1ff86 | 864 | |
862a2d83 UW |
865 | |
866 | /* Position independent code. */ | |
867 | ||
862a2d83 UW |
868 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM) |
869 | ||
870 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) | |
63a1ff86 | 871 | |
935b5226 AK |
872 | #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE |
873 | #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 | |
874 | #endif | |
875 | ||
63a1ff86 UW |
876 | |
877 | /* Assembler file format. */ | |
878 | ||
879 | /* Character to start a comment. */ | |
880 | #define ASM_COMMENT_START "#" | |
881 | ||
882 | /* Declare an uninitialized external linkage data object. */ | |
2d6744f4 AK |
883 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ |
884 | asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN)) | |
63a1ff86 UW |
885 | |
886 | /* Globalizing directive for a label. */ | |
887 | #define GLOBAL_ASM_OP ".globl " | |
888 | ||
889 | /* Advance the location counter to a multiple of 2**LOG bytes. */ | |
890 | #define ASM_OUTPUT_ALIGN(FILE, LOG) \ | |
891 | if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG)) | |
892 | ||
893 | /* Advance the location counter by SIZE bytes. */ | |
894 | #define ASM_OUTPUT_SKIP(FILE, SIZE) \ | |
16998094 | 895 | fprintf ((FILE), "\t.set\t.,.+" HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) |
63a1ff86 | 896 | |
63a1ff86 UW |
897 | /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */ |
898 | #define LOCAL_LABEL_PREFIX "." | |
9db1d521 | 899 | |
5d304e47 | 900 | #define LABEL_ALIGN(LABEL) \ |
2d6744f4 | 901 | s390_label_align ((LABEL)) |
5d304e47 | 902 | |
9db1d521 HP |
903 | /* How to refer to registers in assembler output. This sequence is |
904 | indexed by compiler's hard-register-number (see above). */ | |
9db1d521 | 905 | #define REGISTER_NAMES \ |
085261c8 AK |
906 | { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ |
907 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ | |
908 | "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \ | |
909 | "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \ | |
910 | "%ap", "%cc", "%fp", "%rp", "%a0", "%a1", \ | |
911 | "%v16", "%v18", "%v20", "%v22", "%v17", "%v19", "%v21", "%v23", \ | |
912 | "%v24", "%v26", "%v28", "%v30", "%v25", "%v27", "%v29", "%v31" \ | |
913 | } | |
914 | ||
915 | #define ADDITIONAL_REGISTER_NAMES \ | |
916 | { { "v0", 16 }, { "v2", 17 }, { "v4", 18 }, { "v6", 19 }, \ | |
917 | { "v1", 20 }, { "v3", 21 }, { "v5", 22 }, { "v7", 23 }, \ | |
918 | { "v8", 24 }, { "v10", 25 }, { "v12", 26 }, { "v14", 27 }, \ | |
919 | { "v9", 28 }, { "v11", 29 }, { "v13", 30 }, { "v15", 31 } }; | |
9db1d521 | 920 | |
63a1ff86 | 921 | /* Print operand X (an rtx) in assembler syntax to file FILE. */ |
2d6744f4 AK |
922 | #define PRINT_OPERAND(FILE, X, CODE) print_operand ((FILE), (X), (CODE)) |
923 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address ((FILE), (ADDR)) | |
9db1d521 | 924 | |
63a1ff86 UW |
925 | /* Output an element of a case-vector that is absolute. */ |
926 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
927 | do { \ | |
928 | char buf[32]; \ | |
9602b6a1 | 929 | fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ |
63a1ff86 UW |
930 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ |
931 | assemble_name ((FILE), buf); \ | |
932 | fputc ('\n', (FILE)); \ | |
933 | } while (0) | |
934 | ||
935 | /* Output an element of a case-vector that is relative. */ | |
936 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
937 | do { \ | |
938 | char buf[32]; \ | |
9602b6a1 | 939 | fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ |
63a1ff86 UW |
940 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ |
941 | assemble_name ((FILE), buf); \ | |
942 | fputc ('-', (FILE)); \ | |
943 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \ | |
944 | assemble_name ((FILE), buf); \ | |
945 | fputc ('\n', (FILE)); \ | |
946 | } while (0) | |
947 | ||
177bc204 RS |
948 | /* Mark the return register as used by the epilogue so that we can |
949 | use it in unadorned (return) and (simple_return) instructions. */ | |
950 | #define EPILOGUE_USES(REGNO) ((REGNO) == RETURN_REGNUM) | |
951 | ||
d0de9e13 | 952 | #undef ASM_OUTPUT_FUNCTION_LABEL |
2d6744f4 AK |
953 | #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ |
954 | s390_asm_output_function_label ((FILE), (NAME), (DECL)) | |
9db1d521 | 955 | |
ec47b086 DV |
956 | #if S390_USE_TARGET_ATTRIBUTE |
957 | /* Hook to output .machine and .machinemode at start of function. */ | |
958 | #undef ASM_OUTPUT_FUNCTION_PREFIX | |
959 | #define ASM_OUTPUT_FUNCTION_PREFIX s390_asm_output_function_prefix | |
960 | ||
961 | /* Hook to output .machine and .machinemode at end of function. */ | |
962 | #undef ASM_DECLARE_FUNCTION_SIZE | |
963 | #define ASM_DECLARE_FUNCTION_SIZE s390_asm_declare_function_size | |
964 | #endif | |
965 | ||
862a2d83 UW |
966 | /* Miscellaneous parameters. */ |
967 | ||
862a2d83 UW |
968 | /* Specify the machine mode that this machine uses for the index in the |
969 | tablejump instruction. */ | |
970 | #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) | |
971 | ||
862a2d83 UW |
972 | /* Specify the machine mode that pointers have. |
973 | After generation of rtl, the compiler makes no further distinction | |
974 | between pointers and any other objects of this machine mode. */ | |
501623d4 | 975 | #define Pmode (TARGET_64BIT ? DImode : SImode) |
862a2d83 | 976 | |
c7453384 EC |
977 | /* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */ |
978 | #define POINTERS_EXTEND_UNSIGNED -1 | |
979 | ||
862a2d83 UW |
980 | /* A function address in a call instruction is a byte address (for |
981 | indexing purposes) so give the MEM rtx a byte's mode. */ | |
982 | #define FUNCTION_MODE QImode | |
983 | ||
ec24698e UW |
984 | /* Specify the value which is used when clz operand is zero. */ |
985 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1) | |
986 | ||
0bfc3f69 | 987 | /* Machine-specific symbol_ref flags. */ |
e63d44c2 RD |
988 | #define SYMBOL_FLAG_ALIGN_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT |
989 | #define SYMBOL_FLAG_ALIGN_MASK \ | |
990 | ((SYMBOL_FLAG_MACH_DEP << 0) | (SYMBOL_FLAG_MACH_DEP << 1)) | |
991 | ||
992 | #define SYMBOL_FLAG_SET_ALIGN(X, A) \ | |
993 | (SYMBOL_REF_FLAGS (X) = (SYMBOL_REF_FLAGS (X) & ~SYMBOL_FLAG_ALIGN_MASK) \ | |
994 | | (A << SYMBOL_FLAG_ALIGN_SHIFT)) | |
995 | ||
996 | #define SYMBOL_FLAG_GET_ALIGN(X) \ | |
997 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN_MASK) >> SYMBOL_FLAG_ALIGN_SHIFT) | |
998 | ||
999 | /* Helpers to access symbol_ref flags. They are used in | |
1000 | check_symref_alignment() and larl_operand to detect if the | |
1001 | available alignment matches the required one. We do not use | |
1002 | a positive check like _ALIGN2 because in that case we would have | |
1003 | to annotate every symbol_ref. However, we only want to touch | |
1004 | the symbol_refs that can be misaligned and assume that the others | |
1005 | are correctly aligned. Hence, if a symbol_ref does not have | |
1006 | a _NOTALIGN flag it is supposed to be correctly aligned. */ | |
2d6744f4 AK |
1007 | #define SYMBOL_FLAG_SET_NOTALIGN2(X) SYMBOL_FLAG_SET_ALIGN((X), 1) |
1008 | #define SYMBOL_FLAG_SET_NOTALIGN4(X) SYMBOL_FLAG_SET_ALIGN((X), 2) | |
1009 | #define SYMBOL_FLAG_SET_NOTALIGN8(X) SYMBOL_FLAG_SET_ALIGN((X), 3) | |
e63d44c2 RD |
1010 | |
1011 | #define SYMBOL_FLAG_NOTALIGN2_P(X) (SYMBOL_FLAG_GET_ALIGN(X) == 1) | |
2d6744f4 | 1012 | #define SYMBOL_FLAG_NOTALIGN4_P(X) (SYMBOL_FLAG_GET_ALIGN(X) == 2 \ |
e63d44c2 | 1013 | || SYMBOL_FLAG_GET_ALIGN(X) == 1) |
2d6744f4 AK |
1014 | #define SYMBOL_FLAG_NOTALIGN8_P(X) (SYMBOL_FLAG_GET_ALIGN(X) == 3 \ |
1015 | || SYMBOL_FLAG_GET_ALIGN(X) == 2 \ | |
e63d44c2 | 1016 | || SYMBOL_FLAG_GET_ALIGN(X) == 1) |
0bfc3f69 | 1017 | |
085261c8 AK |
1018 | /* Check whether integer displacement is in range for a short displacement. */ |
1019 | #define SHORT_DISP_IN_RANGE(d) ((d) >= 0 && (d) <= 4095) | |
1020 | ||
0bfc3f69 | 1021 | /* Check whether integer displacement is in range. */ |
2d6744f4 AK |
1022 | #define DISP_IN_RANGE(d) \ |
1023 | (TARGET_LONG_DISPLACEMENT \ | |
1024 | ? ((d) >= -524288 && (d) <= 524287) \ | |
1025 | : SHORT_DISP_IN_RANGE(d)) | |
0bfc3f69 | 1026 | |
24a235c8 CB |
1027 | /* Reads can reuse write prefetches, used by tree-ssa-prefetch-loops.c. */ |
1028 | #define READ_CAN_USE_WRITE_PREFETCH 1 | |
677f3fa8 JM |
1029 | |
1030 | extern const int processor_flags_table[]; | |
085261c8 | 1031 | |
52d4aa4f IL |
1032 | struct s390_processor |
1033 | { | |
1034 | /* The preferred name to be used in user visible output. */ | |
1035 | const char *const name; | |
1036 | /* CPU name as it should be passed to Binutils via .machine */ | |
1037 | const char *const binutils_name; | |
1038 | const enum processor_type processor; | |
1039 | const struct processor_costs *cost; | |
1040 | int arch_level; | |
1041 | }; | |
1042 | ||
1043 | extern const struct s390_processor processor_table[]; | |
1044 | ||
085261c8 AK |
1045 | /* The truth element value for vector comparisons. Our instructions |
1046 | always generate -1 in that case. */ | |
1047 | #define VECTOR_STORE_FLAG_VALUE(MODE) CONSTM1_RTX (GET_MODE_INNER (MODE)) | |
1048 | ||
3af82a61 AK |
1049 | /* Target pragma. */ |
1050 | ||
67914693 | 1051 | /* resolve_overloaded_builtin cannot be defined the normal way since |
3af82a61 AK |
1052 | it is defined in code which technically belongs to the |
1053 | front-end. */ | |
1054 | #define REGISTER_TARGET_PRAGMAS() \ | |
1055 | do { \ | |
1056 | s390_register_target_pragmas (); \ | |
1057 | } while (0) | |
1058 | ||
84b4c7b5 AK |
1059 | #ifndef USED_FOR_TARGET |
1060 | /* The following structure is embedded in the machine | |
1061 | specific part of struct function. */ | |
1062 | ||
1063 | struct GTY (()) s390_frame_layout | |
1064 | { | |
1065 | /* Offset within stack frame. */ | |
1066 | HOST_WIDE_INT gprs_offset; | |
1067 | HOST_WIDE_INT f0_offset; | |
1068 | HOST_WIDE_INT f4_offset; | |
1069 | HOST_WIDE_INT f8_offset; | |
1070 | HOST_WIDE_INT backchain_offset; | |
1071 | ||
1072 | /* Number of first and last gpr where slots in the register | |
1073 | save area are reserved for. */ | |
1074 | int first_save_gpr_slot; | |
1075 | int last_save_gpr_slot; | |
1076 | ||
1077 | /* Location (FP register number) where GPRs (r0-r15) should | |
1078 | be saved to. | |
1079 | 0 - does not need to be saved at all | |
1080 | -1 - stack slot */ | |
1081 | #define SAVE_SLOT_NONE 0 | |
1082 | #define SAVE_SLOT_STACK -1 | |
1083 | signed char gpr_save_slots[16]; | |
1084 | ||
1085 | /* Number of first and last gpr to be saved, restored. */ | |
1086 | int first_save_gpr; | |
1087 | int first_restore_gpr; | |
1088 | int last_save_gpr; | |
1089 | int last_restore_gpr; | |
1090 | ||
1091 | /* Bits standing for floating point registers. Set, if the | |
1092 | respective register has to be saved. Starting with reg 16 (f0) | |
1093 | at the rightmost bit. | |
1094 | Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | |
1095 | fpr 15 13 11 9 14 12 10 8 7 5 3 1 6 4 2 0 | |
1096 | reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 */ | |
1097 | unsigned int fpr_bitmap; | |
1098 | ||
1099 | /* Number of floating point registers f8-f15 which must be saved. */ | |
1100 | int high_fprs; | |
1101 | ||
1102 | /* Set if return address needs to be saved. | |
1103 | This flag is set by s390_return_addr_rtx if it could not use | |
1104 | the initial value of r14 and therefore depends on r14 saved | |
1105 | to the stack. */ | |
1106 | bool save_return_addr_p; | |
1107 | ||
1108 | /* Size of stack frame. */ | |
1109 | HOST_WIDE_INT frame_size; | |
1110 | }; | |
1111 | ||
1112 | ||
1113 | /* Define the structure for the machine field in struct function. */ | |
1114 | ||
1115 | struct GTY(()) machine_function | |
1116 | { | |
1117 | struct s390_frame_layout frame_layout; | |
1118 | ||
1119 | /* Literal pool base register. */ | |
1120 | rtx base_reg; | |
1121 | ||
84b4c7b5 AK |
1122 | bool has_landing_pad_p; |
1123 | ||
1124 | /* True if the current function may contain a tbegin clobbering | |
1125 | FPRs. */ | |
1126 | bool tbegin_p; | |
1127 | ||
1128 | /* For -fsplit-stack support: A stack local which holds a pointer to | |
1129 | the stack arguments for a function with a variable number of | |
1130 | arguments. This is set at the start of the function and is used | |
1131 | to initialize the overflow_arg_area field of the va_list | |
1132 | structure. */ | |
1133 | rtx split_stack_varargs_pointer; | |
1134 | ||
1135 | enum indirect_branch indirect_branch_jump; | |
1136 | enum indirect_branch indirect_branch_call; | |
1137 | ||
1138 | enum indirect_branch function_return_mem; | |
1139 | enum indirect_branch function_return_reg; | |
1140 | }; | |
1141 | #endif | |
1142 | ||
1143 | #define TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION \ | |
1144 | (cfun->machine->function_return_reg != indirect_branch_keep \ | |
1145 | || cfun->machine->function_return_mem != indirect_branch_keep) | |
1146 | ||
1147 | #define TARGET_INDIRECT_BRANCH_NOBP_RET \ | |
1148 | ((cfun->machine->function_return_reg != indirect_branch_keep \ | |
1149 | && !s390_return_addr_from_memory ()) \ | |
1150 | || (cfun->machine->function_return_mem != indirect_branch_keep \ | |
1151 | && s390_return_addr_from_memory ())) | |
1152 | ||
1153 | #define TARGET_INDIRECT_BRANCH_NOBP_JUMP \ | |
1154 | (cfun->machine->indirect_branch_jump != indirect_branch_keep) | |
1155 | ||
1156 | #define TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK \ | |
1157 | (cfun->machine->indirect_branch_jump == indirect_branch_thunk \ | |
1158 | || cfun->machine->indirect_branch_jump == indirect_branch_thunk_extern) | |
1159 | ||
1160 | #define TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK \ | |
1161 | (cfun->machine->indirect_branch_jump == indirect_branch_thunk_inline) | |
1162 | ||
1163 | #define TARGET_INDIRECT_BRANCH_NOBP_CALL \ | |
1164 | (cfun->machine->indirect_branch_call != indirect_branch_keep) | |
1165 | ||
1166 | #ifndef TARGET_DEFAULT_INDIRECT_BRANCH_TABLE | |
1167 | #define TARGET_DEFAULT_INDIRECT_BRANCH_TABLE 0 | |
1168 | #endif | |
1169 | ||
1170 | #define TARGET_INDIRECT_BRANCH_THUNK_NAME_EXRL "__s390_indirect_jump_r%d" | |
1171 | #define TARGET_INDIRECT_BRANCH_THUNK_NAME_EX "__s390_indirect_jump_r%duse_r%d" | |
1172 | ||
1173 | #define TARGET_INDIRECT_BRANCH_TABLE s390_indirect_branch_table | |
1174 | ||
1175 | ||
085261c8 | 1176 | #endif /* S390_H */ |