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9db1d521 | 1 | /* Definitions of target machine for GNU compiler, for IBM S/390 |
5624e564 | 2 | Copyright (C) 1999-2015 Free Software Foundation, Inc. |
9db1d521 | 3 | Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
f314b9b1 | 4 | Ulrich Weigand (uweigand@de.ibm.com). |
963fc8d0 | 5 | Andreas Krebbel (Andreas.Krebbel@de.ibm.com) |
9db1d521 | 6 | |
58add37a | 7 | This file is part of GCC. |
9db1d521 | 8 | |
58add37a UW |
9 | GCC is free software; you can redistribute it and/or modify it under |
10 | the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | version. |
13 | ||
14 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | for more details. | |
9db1d521 HP |
18 | |
19 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. */ | |
9db1d521 HP |
22 | |
23 | #ifndef _S390_H | |
24 | #define _S390_H | |
25 | ||
f13e0d4e UW |
26 | /* Optional architectural facilities supported by the processor. */ |
27 | ||
28 | enum processor_flags | |
29 | { | |
30 | PF_IEEE_FLOAT = 1, | |
31 | PF_ZARCH = 2, | |
ec24698e | 32 | PF_LONG_DISPLACEMENT = 4, |
85dae55a | 33 | PF_EXTIMM = 8, |
93538e8e | 34 | PF_DFP = 16, |
65b1d8ea | 35 | PF_Z10 = 32, |
22ac2c2f | 36 | PF_Z196 = 64, |
5a3fe9b6 AK |
37 | PF_ZEC12 = 128, |
38 | PF_TX = 256 | |
f13e0d4e UW |
39 | }; |
40 | ||
90c6fd8a AK |
41 | /* This is necessary to avoid a warning about comparing different enum |
42 | types. */ | |
43 | #define s390_tune_attr ((enum attr_cpu)s390_tune) | |
44 | ||
963fc8d0 AK |
45 | /* These flags indicate that the generated code should run on a cpu |
46 | providing the respective hardware facility regardless of the | |
47 | current cpu mode (ESA or z/Architecture). */ | |
48 | ||
f13e0d4e UW |
49 | #define TARGET_CPU_IEEE_FLOAT \ |
50 | (s390_arch_flags & PF_IEEE_FLOAT) | |
51 | #define TARGET_CPU_ZARCH \ | |
52 | (s390_arch_flags & PF_ZARCH) | |
53 | #define TARGET_CPU_LONG_DISPLACEMENT \ | |
54 | (s390_arch_flags & PF_LONG_DISPLACEMENT) | |
ec24698e UW |
55 | #define TARGET_CPU_EXTIMM \ |
56 | (s390_arch_flags & PF_EXTIMM) | |
85dae55a AK |
57 | #define TARGET_CPU_DFP \ |
58 | (s390_arch_flags & PF_DFP) | |
93538e8e AK |
59 | #define TARGET_CPU_Z10 \ |
60 | (s390_arch_flags & PF_Z10) | |
65b1d8ea AK |
61 | #define TARGET_CPU_Z196 \ |
62 | (s390_arch_flags & PF_Z196) | |
22ac2c2f AK |
63 | #define TARGET_CPU_ZEC12 \ |
64 | (s390_arch_flags & PF_ZEC12) | |
5a3fe9b6 AK |
65 | #define TARGET_CPU_HTM \ |
66 | (s390_arch_flags & PF_TX) | |
f13e0d4e | 67 | |
963fc8d0 AK |
68 | /* These flags indicate that the generated code should run on a cpu |
69 | providing the respective hardware facility when run in | |
70 | z/Architecture mode. */ | |
71 | ||
f13e0d4e UW |
72 | #define TARGET_LONG_DISPLACEMENT \ |
73 | (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT) | |
ec24698e UW |
74 | #define TARGET_EXTIMM \ |
75 | (TARGET_ZARCH && TARGET_CPU_EXTIMM) | |
85dae55a | 76 | #define TARGET_DFP \ |
fb068247 | 77 | (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT) |
93538e8e AK |
78 | #define TARGET_Z10 \ |
79 | (TARGET_ZARCH && TARGET_CPU_Z10) | |
65b1d8ea AK |
80 | #define TARGET_Z196 \ |
81 | (TARGET_ZARCH && TARGET_CPU_Z196) | |
22ac2c2f AK |
82 | #define TARGET_ZEC12 \ |
83 | (TARGET_ZARCH && TARGET_CPU_ZEC12) | |
167f68ed | 84 | #define TARGET_HTM (TARGET_OPT_HTM) |
65b1d8ea AK |
85 | |
86 | ||
87 | #define TARGET_AVOID_CMP_AND_BRANCH (s390_tune == PROCESSOR_2817_Z196) | |
42c78618 | 88 | |
862a2d83 | 89 | /* Run-time target specification. */ |
9db1d521 | 90 | |
a771c4b3 UW |
91 | /* Defaults for option flags defined only on some subtargets. */ |
92 | #ifndef TARGET_TPF_PROFILING | |
93 | #define TARGET_TPF_PROFILING 0 | |
94 | #endif | |
95 | ||
4798630c D |
96 | /* This will be overridden by OS headers. */ |
97 | #define TARGET_TPF 0 | |
98 | ||
862a2d83 | 99 | /* Target CPU builtins. */ |
5a3fe9b6 AK |
100 | #define TARGET_CPU_CPP_BUILTINS() \ |
101 | do \ | |
102 | { \ | |
103 | builtin_assert ("cpu=s390"); \ | |
104 | builtin_assert ("machine=s390"); \ | |
105 | builtin_define ("__s390__"); \ | |
106 | if (TARGET_ZARCH) \ | |
107 | builtin_define ("__zarch__"); \ | |
108 | if (TARGET_64BIT) \ | |
109 | builtin_define ("__s390x__"); \ | |
110 | if (TARGET_LONG_DOUBLE_128) \ | |
111 | builtin_define ("__LONG_DOUBLE_128__"); \ | |
112 | if (TARGET_HTM) \ | |
113 | builtin_define ("__HTM__"); \ | |
114 | } \ | |
862a2d83 | 115 | while (0) |
9db1d521 | 116 | |
58d10f89 | 117 | #ifdef DEFAULT_TARGET_64BIT |
5a3fe9b6 | 118 | #define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP | MASK_OPT_HTM) |
58d10f89 | 119 | #else |
85dae55a | 120 | #define TARGET_DEFAULT 0 |
58d10f89 UW |
121 | #endif |
122 | ||
f13e0d4e UW |
123 | /* Support for configure-time defaults. */ |
124 | #define OPTION_DEFAULT_SPECS \ | |
125 | { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" }, \ | |
126 | { "arch", "%{!march=*:-march=%(VALUE)}" }, \ | |
127 | { "tune", "%{!mtune=*:-mtune=%(VALUE)}" } | |
128 | ||
129 | /* Defaulting rules. */ | |
130 | #ifdef DEFAULT_TARGET_64BIT | |
131 | #define DRIVER_SELF_SPECS \ | |
132 | "%{!m31:%{!m64:-m64}}", \ | |
133 | "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ | |
134 | "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}" | |
135 | #else | |
136 | #define DRIVER_SELF_SPECS \ | |
137 | "%{!m31:%{!m64:-m31}}", \ | |
138 | "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ | |
139 | "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}" | |
140 | #endif | |
141 | ||
638e37c2 | 142 | /* Constants needed to control the TEST DATA CLASS (TDC) instruction. */ |
0387c142 WG |
143 | #define S390_TDC_POSITIVE_ZERO (1 << 11) |
144 | #define S390_TDC_NEGATIVE_ZERO (1 << 10) | |
145 | #define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER (1 << 9) | |
146 | #define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER (1 << 8) | |
147 | #define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER (1 << 7) | |
148 | #define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER (1 << 6) | |
149 | #define S390_TDC_POSITIVE_INFINITY (1 << 5) | |
150 | #define S390_TDC_NEGATIVE_INFINITY (1 << 4) | |
151 | #define S390_TDC_POSITIVE_QUIET_NAN (1 << 3) | |
152 | #define S390_TDC_NEGATIVE_QUIET_NAN (1 << 2) | |
153 | #define S390_TDC_POSITIVE_SIGNALING_NAN (1 << 1) | |
154 | #define S390_TDC_NEGATIVE_SIGNALING_NAN (1 << 0) | |
155 | ||
156 | /* The following values are different for DFP. */ | |
157 | #define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9) | |
158 | #define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8) | |
159 | #define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER (1 << 7) | |
160 | #define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER (1 << 6) | |
161 | ||
f4aa3848 | 162 | /* For signbit, the BFP-DFP-difference makes no difference. */ |
0f67fa83 | 163 | #define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \ |
0387c142 WG |
164 | | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \ |
165 | | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\ | |
0f67fa83 WG |
166 | | S390_TDC_NEGATIVE_INFINITY \ |
167 | | S390_TDC_NEGATIVE_QUIET_NAN \ | |
168 | | S390_TDC_NEGATIVE_SIGNALING_NAN ) | |
169 | ||
638e37c2 WG |
170 | #define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \ |
171 | | S390_TDC_NEGATIVE_INFINITY ) | |
9db1d521 | 172 | |
a5ba7b92 AK |
173 | /* This is used by float.h to define the float_t and double_t data |
174 | types. For historical reasons both are double on s390 what cannot | |
175 | be changed anymore. */ | |
176 | #define TARGET_FLT_EVAL_METHOD 1 | |
177 | ||
9db1d521 HP |
178 | /* Target machine storage layout. */ |
179 | ||
862a2d83 | 180 | /* Everything is big-endian. */ |
9db1d521 | 181 | #define BITS_BIG_ENDIAN 1 |
9db1d521 | 182 | #define BYTES_BIG_ENDIAN 1 |
9db1d521 HP |
183 | #define WORDS_BIG_ENDIAN 1 |
184 | ||
9602b6a1 AK |
185 | #define STACK_SIZE_MODE (Pmode) |
186 | ||
fe86047c | 187 | #ifndef IN_LIBGCC2 |
9602b6a1 AK |
188 | |
189 | /* Width of a word, in units (bytes). */ | |
190 | #define UNITS_PER_WORD (TARGET_ZARCH ? 8 : 4) | |
191 | ||
192 | /* Width of a pointer. To be used instead of UNITS_PER_WORD in | |
193 | ABI-relevant contexts. This always matches | |
194 | GET_MODE_SIZE (Pmode). */ | |
195 | #define UNITS_PER_LONG (TARGET_64BIT ? 8 : 4) | |
196 | #define MIN_UNITS_PER_WORD 4 | |
197 | #define MAX_BITS_PER_WORD 64 | |
198 | #else | |
199 | ||
200 | /* In libgcc, UNITS_PER_WORD has ABI-relevant effects, e.g. whether | |
201 | the library should export TImode functions or not. Thus, we have | |
202 | to redefine UNITS_PER_WORD depending on __s390x__ for libgcc. */ | |
203 | #ifdef __s390x__ | |
204 | #define UNITS_PER_WORD 8 | |
205 | #else | |
206 | #define UNITS_PER_WORD 4 | |
207 | #endif | |
fe86047c | 208 | #endif |
9602b6a1 AK |
209 | |
210 | /* Width of a pointer, in bits. */ | |
211 | #define POINTER_SIZE (TARGET_64BIT ? 64 : 32) | |
9db1d521 | 212 | |
9db1d521 | 213 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
9db1d521 HP |
214 | #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32) |
215 | ||
216 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
9db1d521 HP |
217 | #define STACK_BOUNDARY 64 |
218 | ||
219 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
d0de9e13 | 220 | #define FUNCTION_BOUNDARY 64 |
9db1d521 HP |
221 | |
222 | /* There is no point aligning anything to a rounder boundary than this. */ | |
9db1d521 HP |
223 | #define BIGGEST_ALIGNMENT 64 |
224 | ||
225 | /* Alignment of field after `int : 0' in a structure. */ | |
9db1d521 HP |
226 | #define EMPTY_FIELD_BOUNDARY 32 |
227 | ||
f710504c | 228 | /* Alignment on even addresses for LARL instruction. */ |
9db1d521 | 229 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) |
df8a1d28 | 230 | #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) |
9db1d521 | 231 | |
862a2d83 | 232 | /* Alignment is not required by the hardware. */ |
9db1d521 HP |
233 | #define STRICT_ALIGNMENT 0 |
234 | ||
862a2d83 UW |
235 | /* Mode of stack savearea. |
236 | FUNCTION is VOIDmode because calling convention maintains SP. | |
237 | BLOCK needs Pmode for SP. | |
238 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ | |
239 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
240 | (LEVEL == SAVE_FUNCTION ? VOIDmode \ | |
43ab026f | 241 | : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode) |
862a2d83 | 242 | |
9db1d521 | 243 | |
862a2d83 | 244 | /* Type layout. */ |
9db1d521 | 245 | |
862a2d83 UW |
246 | /* Sizes in bits of the source language data types. */ |
247 | #define SHORT_TYPE_SIZE 16 | |
248 | #define INT_TYPE_SIZE 32 | |
249 | #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) | |
862a2d83 UW |
250 | #define LONG_LONG_TYPE_SIZE 64 |
251 | #define FLOAT_TYPE_SIZE 32 | |
252 | #define DOUBLE_TYPE_SIZE 64 | |
f61a2c7d AK |
253 | #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) |
254 | ||
f61a2c7d AK |
255 | /* Work around target_flags dependency in ada/targtyps.c. */ |
256 | #define WIDEST_HARDWARE_FP_SIZE 64 | |
862a2d83 UW |
257 | |
258 | /* We use "unsigned char" as default. */ | |
259 | #define DEFAULT_SIGNED_CHAR 0 | |
260 | ||
261 | ||
262 | /* Register usage. */ | |
263 | ||
264 | /* We have 16 general purpose registers (registers 0-15), | |
265 | and 16 floating point registers (registers 16-31). | |
266 | (On non-IEEE machines, we have only 4 fp registers.) | |
c7453384 | 267 | |
862a2d83 UW |
268 | Amongst the general purpose registers, some are used |
269 | for specific purposes: | |
270 | GPR 11: Hard frame pointer (if needed) | |
271 | GPR 12: Global offset table pointer (if needed) | |
272 | GPR 13: Literal pool base register | |
273 | GPR 14: Return address register | |
274 | GPR 15: Stack pointer | |
c7453384 | 275 | |
c5aa1d12 | 276 | Registers 32-35 are 'fake' hard registers that do not |
862a2d83 UW |
277 | correspond to actual hardware: |
278 | Reg 32: Argument pointer | |
279 | Reg 33: Condition code | |
f4aa3848 | 280 | Reg 34: Frame pointer |
c5aa1d12 | 281 | Reg 35: Return address pointer |
862a2d83 | 282 | |
f4aa3848 | 283 | Registers 36 and 37 are mapped to access registers |
c5aa1d12 UW |
284 | 0 and 1, used to implement thread-local storage. */ |
285 | ||
286 | #define FIRST_PSEUDO_REGISTER 38 | |
862a2d83 UW |
287 | |
288 | /* Standard register usage. */ | |
8e509cf9 UW |
289 | #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16) |
290 | #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16) | |
142cd70f | 291 | #define FP_REGNO_P(N) ((N) >= 16 && (N) < 32) |
8e509cf9 | 292 | #define CC_REGNO_P(N) ((N) == 33) |
a38e09bc | 293 | #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34 || (N) == 35) |
c5aa1d12 | 294 | #define ACCESS_REGNO_P(N) ((N) == 36 || (N) == 37) |
8e509cf9 UW |
295 | |
296 | #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) | |
297 | #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X))) | |
298 | #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) | |
299 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) | |
4888ec5d | 300 | #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X))) |
c5aa1d12 | 301 | #define ACCESS_REG_P(X) (REG_P (X) && ACCESS_REGNO_P (REGNO (X))) |
9db1d521 | 302 | |
862a2d83 | 303 | /* Set up fixed registers and calling convention: |
9db1d521 | 304 | |
862a2d83 UW |
305 | GPRs 0-5 are always call-clobbered, |
306 | GPRs 6-15 are always call-saved. | |
307 | GPR 12 is fixed if used as GOT pointer. | |
308 | GPR 13 is always fixed (as literal pool pointer). | |
545d16ff | 309 | GPR 14 is always fixed on S/390 machines (as return address). |
862a2d83 UW |
310 | GPR 15 is always fixed (as stack pointer). |
311 | The 'fake' hard registers are call-clobbered and fixed. | |
c5aa1d12 | 312 | The access registers are call-saved and fixed. |
9db1d521 | 313 | |
862a2d83 UW |
314 | On 31-bit, FPRs 18-19 are call-clobbered; |
315 | on 64-bit, FPRs 24-31 are call-clobbered. | |
316 | The remaining FPRs are call-saved. */ | |
9db1d521 HP |
317 | |
318 | #define FIXED_REGISTERS \ | |
319 | { 0, 0, 0, 0, \ | |
320 | 0, 0, 0, 0, \ | |
321 | 0, 0, 0, 0, \ | |
322 | 0, 1, 1, 1, \ | |
323 | 0, 0, 0, 0, \ | |
324 | 0, 0, 0, 0, \ | |
325 | 0, 0, 0, 0, \ | |
326 | 0, 0, 0, 0, \ | |
c5aa1d12 UW |
327 | 1, 1, 1, 1, \ |
328 | 1, 1 } | |
9db1d521 | 329 | |
9db1d521 HP |
330 | #define CALL_USED_REGISTERS \ |
331 | { 1, 1, 1, 1, \ | |
332 | 1, 1, 0, 0, \ | |
333 | 0, 0, 0, 0, \ | |
334 | 0, 1, 1, 1, \ | |
4023fb28 UW |
335 | 1, 1, 1, 1, \ |
336 | 1, 1, 1, 1, \ | |
337 | 1, 1, 1, 1, \ | |
338 | 1, 1, 1, 1, \ | |
c5aa1d12 UW |
339 | 1, 1, 1, 1, \ |
340 | 1, 1 } | |
4023fb28 | 341 | |
4023fb28 UW |
342 | #define CALL_REALLY_USED_REGISTERS \ |
343 | { 1, 1, 1, 1, \ | |
9db1d521 | 344 | 1, 1, 0, 0, \ |
4023fb28 UW |
345 | 0, 0, 0, 0, \ |
346 | 0, 0, 0, 0, \ | |
9db1d521 HP |
347 | 1, 1, 1, 1, \ |
348 | 1, 1, 1, 1, \ | |
349 | 1, 1, 1, 1, \ | |
4023fb28 | 350 | 1, 1, 1, 1, \ |
c5aa1d12 UW |
351 | 1, 1, 1, 1, \ |
352 | 0, 0 } | |
9db1d521 | 353 | |
862a2d83 UW |
354 | /* Preferred register allocation order. */ |
355 | #define REG_ALLOC_ORDER \ | |
7633f08e | 356 | { 1, 2, 3, 4, 5, 0, 12, 11, 10, 9, 8, 7, 6, 14, 13, \ |
862a2d83 UW |
357 | 16, 17, 18, 19, 20, 21, 22, 23, \ |
358 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
c5aa1d12 | 359 | 15, 32, 33, 34, 35, 36, 37 } |
9db1d521 | 360 | |
9db1d521 | 361 | |
862a2d83 | 362 | /* Fitting values into registers. */ |
c7453384 | 363 | |
862a2d83 UW |
364 | /* Integer modes <= word size fit into any GPR. |
365 | Integer modes > word size fit into successive GPRs, starting with | |
366 | an even-numbered register. | |
367 | SImode and DImode fit into FPRs as well. | |
c7453384 | 368 | |
862a2d83 UW |
369 | Floating point modes <= word size fit into any FPR or GPR. |
370 | Floating point modes > word size (i.e. DFmode on 32-bit) fit | |
371 | into any FPR, or an even-odd GPR pair. | |
f61a2c7d | 372 | TFmode fits only into an even-odd FPR pair. |
c7453384 | 373 | |
862a2d83 UW |
374 | Complex floating point modes fit either into two FPRs, or into |
375 | successive GPRs (again starting with an even number). | |
f61a2c7d | 376 | TCmode fits only into two successive even-odd FPR pairs. |
c7453384 | 377 | |
862a2d83 | 378 | Condition code modes fit only into the CC register. */ |
9db1d521 | 379 | |
74aa8b4b AK |
380 | /* Because all registers in a class have the same size HARD_REGNO_NREGS |
381 | is equivalent to CLASS_MAX_NREGS. */ | |
9db1d521 | 382 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
74aa8b4b AK |
383 | s390_class_max_nregs (REGNO_REG_CLASS (REGNO), (MODE)) |
384 | ||
385 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
386 | s390_hard_regno_mode_ok ((REGNO), (MODE)) | |
387 | ||
388 | #define HARD_REGNO_RENAME_OK(FROM, TO) \ | |
7633f08e UW |
389 | s390_hard_regno_rename_ok (FROM, TO) |
390 | ||
9db1d521 HP |
391 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
392 | (((MODE1) == SFmode || (MODE1) == DFmode) \ | |
393 | == ((MODE2) == SFmode || (MODE2) == DFmode)) | |
394 | ||
9602b6a1 AK |
395 | /* When generating code that runs in z/Architecture mode, |
396 | but conforms to the 31-bit ABI, GPRs can hold 8 bytes; | |
397 | the ABI guarantees only that the lower 4 bytes are | |
398 | saved across calls, however. */ | |
399 | #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ | |
400 | (!TARGET_64BIT && TARGET_ZARCH \ | |
401 | && GET_MODE_SIZE (MODE) > 4 \ | |
402 | && (((REGNO) >= 6 && (REGNO) <= 15) || (REGNO) == 32)) | |
403 | ||
862a2d83 UW |
404 | /* Maximum number of registers to represent a value of mode MODE |
405 | in a register of class CLASS. */ | |
406 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
74aa8b4b | 407 | s390_class_max_nregs ((CLASS), (MODE)) |
4023fb28 | 408 | |
862a2d83 UW |
409 | /* If a 4-byte value is loaded into a FPR, it is placed into the |
410 | *upper* half of the register, not the lower. Therefore, we | |
c5aa1d12 UW |
411 | cannot use SUBREGs to switch between modes in FP registers. |
412 | Likewise for access registers, since they have only half the | |
413 | word size on 64-bit. */ | |
f61a2c7d AK |
414 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ |
415 | (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ | |
416 | ? ((reg_classes_intersect_p (FP_REGS, CLASS) \ | |
417 | && (GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8)) \ | |
418 | || reg_classes_intersect_p (ACCESS_REGS, CLASS)) : 0) | |
9db1d521 | 419 | |
862a2d83 | 420 | /* Register classes. */ |
c7453384 | 421 | |
862a2d83 UW |
422 | /* We use the following register classes: |
423 | GENERAL_REGS All general purpose registers | |
424 | ADDR_REGS All general purpose registers except %r0 | |
425 | (These registers can be used in address generation) | |
426 | FP_REGS All floating point registers | |
c5aa1d12 UW |
427 | CC_REGS The condition code register |
428 | ACCESS_REGS The access registers | |
c7453384 | 429 | |
862a2d83 UW |
430 | GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS |
431 | ADDR_FP_REGS Union of ADDR_REGS and FP_REGS | |
c5aa1d12 UW |
432 | GENERAL_CC_REGS Union of GENERAL_REGS and CC_REGS |
433 | ADDR_CC_REGS Union of ADDR_REGS and CC_REGS | |
c7453384 | 434 | |
862a2d83 UW |
435 | NO_REGS No registers |
436 | ALL_REGS All registers | |
c7453384 | 437 | |
862a2d83 | 438 | Note that the 'fake' frame pointer and argument pointer registers |
c5aa1d12 | 439 | are included amongst the address registers here. */ |
9db1d521 HP |
440 | |
441 | enum reg_class | |
442 | { | |
c5aa1d12 | 443 | NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS, |
f4aa3848 | 444 | ADDR_CC_REGS, GENERAL_CC_REGS, |
4023fb28 UW |
445 | FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, |
446 | ALL_REGS, LIM_REG_CLASSES | |
9db1d521 | 447 | }; |
9db1d521 HP |
448 | #define N_REG_CLASSES (int) LIM_REG_CLASSES |
449 | ||
c5aa1d12 UW |
450 | #define REG_CLASS_NAMES \ |
451 | { "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS", \ | |
452 | "ADDR_CC_REGS", "GENERAL_CC_REGS", \ | |
453 | "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" } | |
9db1d521 | 454 | |
862a2d83 | 455 | /* Class -> register mapping. */ |
9db1d521 HP |
456 | #define REG_CLASS_CONTENTS \ |
457 | { \ | |
458 | { 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
9dc62c00 | 459 | { 0x00000000, 0x00000002 }, /* CC_REGS */ \ |
a38e09bc AK |
460 | { 0x0000fffe, 0x0000000d }, /* ADDR_REGS */ \ |
461 | { 0x0000ffff, 0x0000000d }, /* GENERAL_REGS */ \ | |
c5aa1d12 | 462 | { 0x00000000, 0x00000030 }, /* ACCESS_REGS */ \ |
9dc62c00 AK |
463 | { 0x0000fffe, 0x0000000f }, /* ADDR_CC_REGS */ \ |
464 | { 0x0000ffff, 0x0000000f }, /* GENERAL_CC_REGS */ \ | |
9db1d521 | 465 | { 0xffff0000, 0x00000000 }, /* FP_REGS */ \ |
a38e09bc AK |
466 | { 0xfffffffe, 0x0000000d }, /* ADDR_FP_REGS */ \ |
467 | { 0xffffffff, 0x0000000d }, /* GENERAL_FP_REGS */ \ | |
c5aa1d12 | 468 | { 0xffffffff, 0x0000003f }, /* ALL_REGS */ \ |
9db1d521 HP |
469 | } |
470 | ||
058e97ec VM |
471 | /* In some case register allocation order is not enough for IRA to |
472 | generate a good code. The following macro (if defined) increases | |
473 | cost of REGNO for a pseudo approximately by pseudo usage frequency | |
474 | multiplied by the macro value. | |
475 | ||
476 | We avoid usage of BASE_REGNUM by nonzero macro value because the | |
477 | reload can decide not to use the hard register because some | |
478 | constant was forced to be in memory. */ | |
479 | #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) \ | |
dba0dd68 | 480 | (regno != BASE_REGNUM ? 0.0 : 0.5) |
058e97ec | 481 | |
862a2d83 UW |
482 | /* Register -> class mapping. */ |
483 | extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; | |
484 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) | |
9db1d521 | 485 | |
862a2d83 UW |
486 | /* ADDR_REGS can be used as base or index register. */ |
487 | #define INDEX_REG_CLASS ADDR_REGS | |
488 | #define BASE_REG_CLASS ADDR_REGS | |
9db1d521 | 489 | |
862a2d83 UW |
490 | /* Check whether REGNO is a hard register of the suitable class |
491 | or a pseudo register currently allocated to one such. */ | |
492 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
493 | (((REGNO) < FIRST_PSEUDO_REGISTER \ | |
93fa8428 AK |
494 | && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \ |
495 | || ADDR_REGNO_P (reg_renumber[REGNO])) | |
862a2d83 | 496 | #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) |
9db1d521 | 497 | |
9db1d521 | 498 | |
963fc8d0 AK |
499 | /* We need secondary memory to move data between GPRs and FPRs. With |
500 | DFP the ldgr lgdr instructions are available. But these | |
501 | instructions do not handle GPR pairs so it is not possible for 31 | |
502 | bit. */ | |
862a2d83 | 503 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ |
85dae55a AK |
504 | ((CLASS1) != (CLASS2) \ |
505 | && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS) \ | |
963fc8d0 | 506 | && (!TARGET_DFP || !TARGET_64BIT || GET_MODE_SIZE (MODE) != 8)) |
862a2d83 UW |
507 | |
508 | /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit | |
509 | because the movsi and movsf patterns don't handle r/f moves. */ | |
510 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
511 | (GET_MODE_BITSIZE (MODE) < 32 \ | |
512 | ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
513 | : MODE) | |
514 | ||
515 | ||
862a2d83 | 516 | /* Stack layout and calling conventions. */ |
c7453384 | 517 | |
862a2d83 UW |
518 | /* Our stack grows from higher to lower addresses. However, local variables |
519 | are accessed by positive offsets, and function arguments are stored at | |
520 | increasing addresses. */ | |
521 | #define STACK_GROWS_DOWNWARD | |
63296cb1 | 522 | #define FRAME_GROWS_DOWNWARD 1 |
862a2d83 | 523 | /* #undef ARGS_GROW_DOWNWARD */ |
9db1d521 | 524 | |
862a2d83 UW |
525 | /* The basic stack layout looks like this: the stack pointer points |
526 | to the register save area for called functions. Above that area | |
527 | is the location to place outgoing arguments. Above those follow | |
528 | dynamic allocations (alloca), and finally the local variables. */ | |
9db1d521 | 529 | |
862a2d83 UW |
530 | /* Offset from stack-pointer to first location of outgoing args. */ |
531 | #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96) | |
9db1d521 | 532 | |
862a2d83 | 533 | /* Offset within stack frame to start allocating local variables at. */ |
63296cb1 | 534 | #define STARTING_FRAME_OFFSET 0 |
9db1d521 | 535 | |
862a2d83 UW |
536 | /* Offset from the stack pointer register to an item dynamically |
537 | allocated on the stack, e.g., by `alloca'. */ | |
63296cb1 | 538 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ |
38173d38 | 539 | (STACK_POINTER_OFFSET + crtl->outgoing_args_size) |
9db1d521 | 540 | |
862a2d83 UW |
541 | /* Offset of first parameter from the argument pointer register value. |
542 | We have a fake argument pointer register that points directly to | |
543 | the argument area. */ | |
544 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
9db1d521 | 545 | |
f4aa3848 | 546 | /* Defining this macro makes __builtin_frame_address(0) and |
c6d01079 AK |
547 | __builtin_return_address(0) work with -fomit-frame-pointer. */ |
548 | #define INITIAL_FRAME_ADDRESS_RTX \ | |
0a81f074 | 549 | (plus_constant (Pmode, arg_pointer_rtx, -STACK_POINTER_OFFSET)) |
c6d01079 | 550 | |
c7453384 | 551 | /* The return address of the current frame is retrieved |
4023fb28 UW |
552 | from the initial value of register RETURN_REGNUM. |
553 | For frames farther back, we use the stack slot where | |
554 | the corresponding RETURN_REGNUM register was saved. */ | |
c6d01079 AK |
555 | #define DYNAMIC_CHAIN_ADDRESS(FRAME) \ |
556 | (TARGET_PACKED_STACK ? \ | |
0a81f074 RS |
557 | plus_constant (Pmode, (FRAME), \ |
558 | STACK_POINTER_OFFSET - UNITS_PER_LONG) : (FRAME)) | |
4023fb28 | 559 | |
78791a80 AK |
560 | /* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of |
561 | builtin_frame_address. Otherwise arg pointer - | |
562 | STACK_POINTER_OFFSET would be returned for | |
563 | __builtin_frame_address(0) what might result in an address pointing | |
564 | somewhere into the middle of the local variables since the packed | |
565 | stack layout generally does not need all the bytes in the register | |
566 | save area. */ | |
567 | #define FRAME_ADDR_RTX(FRAME) \ | |
568 | DYNAMIC_CHAIN_ADDRESS ((FRAME)) | |
569 | ||
c6d01079 | 570 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
5d4d885c | 571 | s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME))) |
9db1d521 | 572 | |
862a2d83 | 573 | /* In 31-bit mode, we need to mask off the high bit of return addresses. */ |
a556fd39 | 574 | #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff)) |
9db1d521 | 575 | |
4023fb28 | 576 | |
862a2d83 | 577 | /* Exception handling. */ |
c7453384 | 578 | |
862a2d83 UW |
579 | /* Describe calling conventions for DWARF-2 exception handling. */ |
580 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM) | |
4023fb28 | 581 | #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET |
9db1d521 HP |
582 | #define DWARF_FRAME_RETURN_COLUMN 14 |
583 | ||
584 | /* Describe how we implement __builtin_eh_return. */ | |
585 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM) | |
a38e09bc | 586 | #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx) |
f4aa3848 | 587 | |
18789f4e UW |
588 | /* Select a format to encode pointers in exception handling data. */ |
589 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
590 | (flag_pic \ | |
591 | ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ | |
592 | : DW_EH_PE_absptr) | |
593 | ||
9602b6a1 AK |
594 | /* Register save slot alignment. */ |
595 | #define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_LONG) | |
596 | ||
f276b762 AK |
597 | /* Let the assembler generate debug line info. */ |
598 | #define DWARF2_ASM_LINE_DEBUG_INFO 1 | |
599 | ||
9db1d521 | 600 | |
862a2d83 | 601 | /* Frame registers. */ |
9db1d521 | 602 | |
862a2d83 UW |
603 | #define STACK_POINTER_REGNUM 15 |
604 | #define FRAME_POINTER_REGNUM 34 | |
605 | #define HARD_FRAME_POINTER_REGNUM 11 | |
606 | #define ARG_POINTER_REGNUM 32 | |
a38e09bc | 607 | #define RETURN_ADDRESS_POINTER_REGNUM 35 |
9db1d521 | 608 | |
c7453384 EC |
609 | /* The static chain must be call-clobbered, but not used for |
610 | function argument passing. As register 1 is clobbered by | |
862a2d83 UW |
611 | the trampoline code, we only have one option. */ |
612 | #define STATIC_CHAIN_REGNUM 0 | |
9db1d521 | 613 | |
862a2d83 UW |
614 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
615 | To avoid ABI incompatibility, this number must not change even as | |
616 | 'fake' hard registers are added or removed. */ | |
617 | #define DWARF_FRAME_REGISTERS 34 | |
9db1d521 | 618 | |
9db1d521 | 619 | |
862a2d83 | 620 | /* Frame pointer and argument pointer elimination. */ |
9db1d521 | 621 | |
7633f08e UW |
622 | #define ELIMINABLE_REGS \ |
623 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
624 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
625 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
626 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
627 | { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
628 | { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
629 | { BASE_REGNUM, BASE_REGNUM }} | |
9db1d521 | 630 | |
91086990 UW |
631 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
632 | (OFFSET) = s390_initial_elimination_offset ((FROM), (TO)) | |
9db1d521 | 633 | |
9db1d521 | 634 | |
862a2d83 | 635 | /* Stack arguments. */ |
c7453384 | 636 | |
862a2d83 UW |
637 | /* We need current_function_outgoing_args to be valid. */ |
638 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
9db1d521 | 639 | |
9db1d521 | 640 | |
862a2d83 | 641 | /* Register arguments. */ |
c7453384 | 642 | |
9db1d521 HP |
643 | typedef struct s390_arg_structure |
644 | { | |
645 | int gprs; /* gpr so far */ | |
646 | int fprs; /* fpr so far */ | |
647 | } | |
648 | CUMULATIVE_ARGS; | |
649 | ||
07711f53 | 650 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \ |
9db1d521 HP |
651 | ((CUM).gprs=0, (CUM).fprs=0) |
652 | ||
96e2afa8 AK |
653 | /* Arguments can be placed in general registers 2 to 6, or in floating |
654 | point registers 0 and 2 for 31 bit and fprs 0, 2, 4 and 6 for 64 | |
655 | bit. */ | |
862a2d83 | 656 | #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \ |
96e2afa8 | 657 | (N) == 16 || (N) == 17 || (TARGET_64BIT && ((N) == 18 || (N) == 19))) |
9db1d521 | 658 | |
9db1d521 | 659 | |
862a2d83 | 660 | /* Only gpr 2 and fpr 0 are ever used as return registers. */ |
9db1d521 HP |
661 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16) |
662 | ||
9db1d521 | 663 | |
862a2d83 | 664 | /* Function entry and exit. */ |
c7453384 | 665 | |
862a2d83 UW |
666 | /* When returning from a function, the stack pointer does not matter. */ |
667 | #define EXIT_IGNORE_STACK 1 | |
9db1d521 | 668 | |
9db1d521 | 669 | |
862a2d83 | 670 | /* Profiling. */ |
9db1d521 HP |
671 | |
672 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
862a2d83 | 673 | s390_function_profiler ((FILE), ((LABELNO))) |
9db1d521 | 674 | |
c52a375d | 675 | #define PROFILE_BEFORE_PROLOGUE 1 |
9db1d521 | 676 | |
9db1d521 | 677 | |
862a2d83 | 678 | /* Trampolines for nested functions. */ |
9db1d521 | 679 | |
b81ecf6f RH |
680 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 32 : 16) |
681 | #define TRAMPOLINE_ALIGNMENT BITS_PER_WORD | |
9db1d521 | 682 | |
862a2d83 | 683 | /* Addressing modes, and classification of registers for them. */ |
9db1d521 | 684 | |
862a2d83 UW |
685 | /* Recognize any constant value that is a valid address. */ |
686 | #define CONSTANT_ADDRESS_P(X) 0 | |
9db1d521 | 687 | |
862a2d83 UW |
688 | /* Maximum number of registers that can appear in a valid memory address. */ |
689 | #define MAX_REGS_PER_ADDRESS 2 | |
9db1d521 | 690 | |
963fc8d0 | 691 | /* This definition replaces the formerly used 'm' constraint with a |
c6c3dba9 PB |
692 | different constraint letter in order to avoid changing semantics of |
693 | the 'm' constraint when accepting new address formats in | |
694 | TARGET_LEGITIMATE_ADDRESS_P. The constraint letter defined here | |
695 | must not be used in insn definitions or inline assemblies. */ | |
963fc8d0 AK |
696 | #define TARGET_MEM_CONSTRAINT 'e' |
697 | ||
0b540f12 UW |
698 | /* Try a machine-dependent way of reloading an illegitimate address |
699 | operand. If we find one, push the reload and jump to WIN. This | |
700 | macro is used in only one place: `find_reloads_address' in reload.c. */ | |
701 | #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ | |
702 | do { \ | |
0a2aaacc KG |
703 | rtx new_rtx = legitimize_reload_address (AD, MODE, OPNUM, (int)(TYPE)); \ |
704 | if (new_rtx) \ | |
0b540f12 | 705 | { \ |
0a2aaacc | 706 | (AD) = new_rtx; \ |
0b540f12 UW |
707 | goto WIN; \ |
708 | } \ | |
709 | } while (0) | |
710 | ||
862a2d83 UW |
711 | /* Helper macro for s390.c and s390.md to check for symbolic constants. */ |
712 | #define SYMBOLIC_CONST(X) \ | |
713 | (GET_CODE (X) == SYMBOL_REF \ | |
714 | || GET_CODE (X) == LABEL_REF \ | |
715 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
9db1d521 | 716 | |
fd3cd001 UW |
717 | #define TLS_SYMBOLIC_CONST(X) \ |
718 | ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \ | |
719 | || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X))) | |
720 | ||
9db1d521 | 721 | |
862a2d83 | 722 | /* Condition codes. */ |
9db1d521 | 723 | |
862a2d83 UW |
724 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
725 | return the mode to be used for the comparison. */ | |
726 | #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y)) | |
c7453384 | 727 | |
862a2d83 | 728 | /* Relative costs of operations. */ |
9db1d521 | 729 | |
9db1d521 HP |
730 | /* A C expression for the cost of a branch instruction. A value of 1 |
731 | is the default; other values are interpreted relative to that. */ | |
3d427cc1 | 732 | #define BRANCH_COST(speed_p, predictable_p) s390_branch_cost |
9db1d521 | 733 | |
862a2d83 UW |
734 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
735 | #define SLOW_BYTE_ACCESS 1 | |
736 | ||
c5443745 | 737 | /* An integer expression for the size in bits of the largest integer machine |
f4aa3848 | 738 | mode that should actually be used. We allow pairs of registers. */ |
c5443745 UW |
739 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) |
740 | ||
862a2d83 | 741 | /* The maximum number of bytes that a single instruction can move quickly |
ff482c8d | 742 | between memory and registers or between two memory locations. */ |
9602b6a1 AK |
743 | #define MOVE_MAX (TARGET_ZARCH ? 16 : 8) |
744 | #define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4) | |
862a2d83 | 745 | #define MAX_MOVE_MAX 16 |
9db1d521 | 746 | |
862a2d83 | 747 | /* Don't perform CSE on function addresses. */ |
1e8552c2 | 748 | #define NO_FUNCTION_CSE 1 |
862a2d83 | 749 | |
5f1b2ee6 AK |
750 | /* This value is used in tree-sra to decide whether it might benefical |
751 | to split a struct move into several word-size moves. For S/390 | |
752 | only small values make sense here since struct moves are relatively | |
073a8998 | 753 | cheap thanks to mvc so the small default value chosen for archs |
5f1b2ee6 AK |
754 | with memmove patterns should be ok. But this value is multiplied |
755 | in tree-sra with UNITS_PER_WORD to make a decision so we adjust it | |
756 | here to compensate for that factor since mvc costs exactly the same | |
757 | on 31 and 64 bit. */ | |
e04ad03d | 758 | #define MOVE_RATIO(speed) (TARGET_64BIT? 2 : 4) |
5f1b2ee6 | 759 | |
862a2d83 UW |
760 | |
761 | /* Sections. */ | |
762 | ||
763 | /* Output before read-only data. */ | |
764 | #define TEXT_SECTION_ASM_OP ".text" | |
765 | ||
766 | /* Output before writable (initialized) data. */ | |
767 | #define DATA_SECTION_ASM_OP ".data" | |
768 | ||
769 | /* Output before writable (uninitialized) data. */ | |
770 | #define BSS_SECTION_ASM_OP ".bss" | |
771 | ||
772 | /* S/390 constant pool breaks the devices in crtstuff.c to control section | |
773 | in where code resides. We have to write it as asm code. */ | |
774 | #ifndef __s390x__ | |
775 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
776 | asm (SECTION_OP "\n\ | |
777 | bras\t%r2,1f\n\ | |
778 | 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\ | |
779 | 1: l\t%r3,0(%r2)\n\ | |
780 | bas\t%r14,0(%r3,%r2)\n\ | |
781 | .previous"); | |
782 | #endif | |
63a1ff86 | 783 | |
862a2d83 UW |
784 | |
785 | /* Position independent code. */ | |
786 | ||
862a2d83 UW |
787 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM) |
788 | ||
789 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) | |
63a1ff86 UW |
790 | |
791 | ||
792 | /* Assembler file format. */ | |
793 | ||
794 | /* Character to start a comment. */ | |
795 | #define ASM_COMMENT_START "#" | |
796 | ||
797 | /* Declare an uninitialized external linkage data object. */ | |
798 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
799 | asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) | |
800 | ||
801 | /* Globalizing directive for a label. */ | |
802 | #define GLOBAL_ASM_OP ".globl " | |
803 | ||
804 | /* Advance the location counter to a multiple of 2**LOG bytes. */ | |
805 | #define ASM_OUTPUT_ALIGN(FILE, LOG) \ | |
806 | if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG)) | |
807 | ||
808 | /* Advance the location counter by SIZE bytes. */ | |
809 | #define ASM_OUTPUT_SKIP(FILE, SIZE) \ | |
58e15542 | 810 | fprintf ((FILE), "\t.set\t.,.+"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) |
63a1ff86 | 811 | |
63a1ff86 UW |
812 | /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */ |
813 | #define LOCAL_LABEL_PREFIX "." | |
9db1d521 | 814 | |
5d304e47 AK |
815 | #define LABEL_ALIGN(LABEL) \ |
816 | s390_label_align (LABEL) | |
817 | ||
9db1d521 HP |
818 | /* How to refer to registers in assembler output. This sequence is |
819 | indexed by compiler's hard-register-number (see above). */ | |
9db1d521 HP |
820 | #define REGISTER_NAMES \ |
821 | { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ | |
a38e09bc | 822 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ |
9db1d521 | 823 | "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \ |
a38e09bc | 824 | "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \ |
c5aa1d12 | 825 | "%ap", "%cc", "%fp", "%rp", "%a0", "%a1" \ |
9db1d521 HP |
826 | } |
827 | ||
63a1ff86 | 828 | /* Print operand X (an rtx) in assembler syntax to file FILE. */ |
9db1d521 | 829 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) |
9db1d521 HP |
830 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) |
831 | ||
63a1ff86 UW |
832 | /* Output an element of a case-vector that is absolute. */ |
833 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
834 | do { \ | |
835 | char buf[32]; \ | |
9602b6a1 | 836 | fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ |
63a1ff86 UW |
837 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ |
838 | assemble_name ((FILE), buf); \ | |
839 | fputc ('\n', (FILE)); \ | |
840 | } while (0) | |
841 | ||
842 | /* Output an element of a case-vector that is relative. */ | |
843 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
844 | do { \ | |
845 | char buf[32]; \ | |
9602b6a1 | 846 | fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ |
63a1ff86 UW |
847 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ |
848 | assemble_name ((FILE), buf); \ | |
849 | fputc ('-', (FILE)); \ | |
850 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \ | |
851 | assemble_name ((FILE), buf); \ | |
852 | fputc ('\n', (FILE)); \ | |
853 | } while (0) | |
854 | ||
177bc204 RS |
855 | /* Mark the return register as used by the epilogue so that we can |
856 | use it in unadorned (return) and (simple_return) instructions. */ | |
857 | #define EPILOGUE_USES(REGNO) ((REGNO) == RETURN_REGNUM) | |
858 | ||
d0de9e13 DV |
859 | #undef ASM_OUTPUT_FUNCTION_LABEL |
860 | #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ | |
861 | s390_asm_output_function_label (FILE, NAME, DECL) | |
9db1d521 | 862 | |
862a2d83 UW |
863 | /* Miscellaneous parameters. */ |
864 | ||
862a2d83 UW |
865 | /* Specify the machine mode that this machine uses for the index in the |
866 | tablejump instruction. */ | |
867 | #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) | |
868 | ||
862a2d83 UW |
869 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
870 | is done just by pretending it is already truncated. */ | |
871 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
872 | ||
873 | /* Specify the machine mode that pointers have. | |
874 | After generation of rtl, the compiler makes no further distinction | |
875 | between pointers and any other objects of this machine mode. */ | |
ef4bddc2 | 876 | #define Pmode ((machine_mode) (TARGET_64BIT ? DImode : SImode)) |
862a2d83 | 877 | |
c7453384 EC |
878 | /* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */ |
879 | #define POINTERS_EXTEND_UNSIGNED -1 | |
880 | ||
862a2d83 UW |
881 | /* A function address in a call instruction is a byte address (for |
882 | indexing purposes) so give the MEM rtx a byte's mode. */ | |
883 | #define FUNCTION_MODE QImode | |
884 | ||
ec24698e UW |
885 | /* Specify the value which is used when clz operand is zero. */ |
886 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1) | |
887 | ||
0bfc3f69 | 888 | /* Machine-specific symbol_ref flags. */ |
963fc8d0 AK |
889 | #define SYMBOL_FLAG_ALIGN1 (SYMBOL_FLAG_MACH_DEP << 0) |
890 | #define SYMBOL_REF_ALIGN1_P(X) \ | |
891 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN1)) | |
892 | #define SYMBOL_FLAG_NOT_NATURALLY_ALIGNED (SYMBOL_FLAG_MACH_DEP << 1) | |
893 | #define SYMBOL_REF_NOT_NATURALLY_ALIGNED_P(X) \ | |
894 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_NOT_NATURALLY_ALIGNED)) | |
0bfc3f69 AS |
895 | |
896 | /* Check whether integer displacement is in range. */ | |
897 | #define DISP_IN_RANGE(d) \ | |
898 | (TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \ | |
899 | : ((d) >= 0 && (d) <= 4095)) | |
900 | ||
24a235c8 CB |
901 | /* Reads can reuse write prefetches, used by tree-ssa-prefetch-loops.c. */ |
902 | #define READ_CAN_USE_WRITE_PREFETCH 1 | |
677f3fa8 JM |
903 | |
904 | extern const int processor_flags_table[]; | |
c7453384 | 905 | #endif |