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9db1d521 | 1 | /* Definitions of target machine for GNU compiler, for IBM S/390 |
283334f0 KH |
2 | Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004 |
3 | Free Software Foundation, Inc. | |
9db1d521 | 4 | Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
f314b9b1 | 5 | Ulrich Weigand (uweigand@de.ibm.com). |
9db1d521 | 6 | |
58add37a | 7 | This file is part of GCC. |
9db1d521 | 8 | |
58add37a UW |
9 | GCC is free software; you can redistribute it and/or modify it under |
10 | the terms of the GNU General Public License as published by the Free | |
11 | Software Foundation; either version 2, or (at your option) any later | |
12 | version. | |
13 | ||
14 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | for more details. | |
9db1d521 HP |
18 | |
19 | You should have received a copy of the GNU General Public License | |
58add37a UW |
20 | along with GCC; see the file COPYING. If not, write to the Free |
21 | Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
22 | 02111-1307, USA. */ | |
9db1d521 HP |
23 | |
24 | #ifndef _S390_H | |
25 | #define _S390_H | |
26 | ||
42c78618 UW |
27 | /* Override the __fixdfdi etc. routines when building libgcc2. |
28 | ??? This should be done in a cleaner way ... */ | |
fe86047c | 29 | #if defined (IN_LIBGCC2) && !defined (__s390x__) |
ca11c37c | 30 | #include <config/s390/fixdfdi.h> |
42c78618 UW |
31 | #endif |
32 | ||
c7453384 | 33 | /* Which processor to generate code or schedule for. The cpu attribute |
1fec52be HP |
34 | defines a list that mirrors this list, so changes to s390.md must be |
35 | made at the same time. */ | |
36 | ||
37 | enum processor_type | |
38 | { | |
c7453384 EC |
39 | PROCESSOR_9672_G5, |
40 | PROCESSOR_9672_G6, | |
41 | PROCESSOR_2064_Z900, | |
f13e0d4e | 42 | PROCESSOR_2084_Z990, |
1fec52be HP |
43 | PROCESSOR_max |
44 | }; | |
45 | ||
f13e0d4e UW |
46 | /* Optional architectural facilities supported by the processor. */ |
47 | ||
48 | enum processor_flags | |
49 | { | |
50 | PF_IEEE_FLOAT = 1, | |
51 | PF_ZARCH = 2, | |
52 | PF_LONG_DISPLACEMENT = 4 | |
53 | }; | |
54 | ||
55 | extern enum processor_type s390_tune; | |
56 | extern enum processor_flags s390_tune_flags; | |
be2c2a4b | 57 | extern const char *s390_tune_string; |
1fec52be HP |
58 | |
59 | extern enum processor_type s390_arch; | |
f13e0d4e | 60 | extern enum processor_flags s390_arch_flags; |
1fec52be HP |
61 | extern const char *s390_arch_string; |
62 | ||
adf39f8f AK |
63 | extern const char *s390_backchain_string; |
64 | ||
d75f90f1 AK |
65 | extern const char *s390_warn_framesize_string; |
66 | extern const char *s390_warn_dynamicstack_string; | |
67 | extern const char *s390_stack_size_string; | |
68 | extern const char *s390_stack_guard_string; | |
69 | ||
f13e0d4e UW |
70 | #define TARGET_CPU_IEEE_FLOAT \ |
71 | (s390_arch_flags & PF_IEEE_FLOAT) | |
72 | #define TARGET_CPU_ZARCH \ | |
73 | (s390_arch_flags & PF_ZARCH) | |
74 | #define TARGET_CPU_LONG_DISPLACEMENT \ | |
75 | (s390_arch_flags & PF_LONG_DISPLACEMENT) | |
76 | ||
77 | #define TARGET_LONG_DISPLACEMENT \ | |
78 | (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT) | |
1fec52be | 79 | |
42c78618 | 80 | |
862a2d83 | 81 | /* Run-time target specification. */ |
9db1d521 | 82 | |
862a2d83 UW |
83 | /* Target CPU builtins. */ |
84 | #define TARGET_CPU_CPP_BUILTINS() \ | |
85 | do \ | |
86 | { \ | |
87 | builtin_assert ("cpu=s390"); \ | |
88 | builtin_assert ("machine=s390"); \ | |
89 | builtin_define ("__s390__"); \ | |
90 | if (TARGET_64BIT) \ | |
91 | builtin_define ("__s390x__"); \ | |
92 | } \ | |
93 | while (0) | |
9db1d521 | 94 | |
862a2d83 | 95 | /* Optional target features. */ |
9db1d521 HP |
96 | extern int target_flags; |
97 | ||
1fec52be | 98 | #define MASK_HARD_FLOAT 0x01 |
1fec52be HP |
99 | #define MASK_SMALL_EXEC 0x04 |
100 | #define MASK_DEBUG_ARG 0x08 | |
101 | #define MASK_64BIT 0x10 | |
102 | #define MASK_ZARCH 0x20 | |
103 | #define MASK_MVCLE 0x40 | |
3839e36a | 104 | #define MASK_TPF_PROFILING 0x80 |
f2d226e1 | 105 | #define MASK_NO_FUSED_MADD 0x100 |
1fec52be HP |
106 | |
107 | #define TARGET_HARD_FLOAT (target_flags & MASK_HARD_FLOAT) | |
108 | #define TARGET_SOFT_FLOAT (!(target_flags & MASK_HARD_FLOAT)) | |
1fec52be HP |
109 | #define TARGET_SMALL_EXEC (target_flags & MASK_SMALL_EXEC) |
110 | #define TARGET_DEBUG_ARG (target_flags & MASK_DEBUG_ARG) | |
111 | #define TARGET_64BIT (target_flags & MASK_64BIT) | |
112 | #define TARGET_ZARCH (target_flags & MASK_ZARCH) | |
113 | #define TARGET_MVCLE (target_flags & MASK_MVCLE) | |
3839e36a | 114 | #define TARGET_TPF_PROFILING (target_flags & MASK_TPF_PROFILING) |
f2d226e1 AK |
115 | #define TARGET_NO_FUSED_MADD (target_flags & MASK_NO_FUSED_MADD) |
116 | #define TARGET_FUSED_MADD (! TARGET_NO_FUSED_MADD) | |
9db1d521 | 117 | |
adf39f8f AK |
118 | #define TARGET_BACKCHAIN (s390_backchain_string[0] == '1') |
119 | #define TARGET_KERNEL_BACKCHAIN (s390_backchain_string[0] == '2') | |
120 | ||
8e509cf9 UW |
121 | /* ??? Once this actually works, it could be made a runtime option. */ |
122 | #define TARGET_IBM_FLOAT 0 | |
123 | #define TARGET_IEEE_FLOAT 1 | |
124 | ||
58d10f89 | 125 | #ifdef DEFAULT_TARGET_64BIT |
590fcf48 | 126 | #define TARGET_DEFAULT 0x31 |
58d10f89 | 127 | #else |
590fcf48 | 128 | #define TARGET_DEFAULT 0x1 |
58d10f89 UW |
129 | #endif |
130 | ||
f2d226e1 AK |
131 | #define TARGET_SWITCHES \ |
132 | { { "hard-float", 1, N_("Use hardware fp")}, \ | |
133 | { "soft-float", -1, N_("Don't use hardware fp")}, \ | |
f2d226e1 AK |
134 | { "small-exec", 4, N_("Use bras for executable < 64k")}, \ |
135 | { "no-small-exec", -4, N_("Don't use bras")}, \ | |
136 | { "debug", 8, N_("Additional debug prints")}, \ | |
137 | { "no-debug", -8, N_("Don't print additional debug prints")}, \ | |
138 | { "64", 16, N_("64 bit ABI")}, \ | |
139 | { "31", -16, N_("31 bit ABI")}, \ | |
140 | { "zarch", 32, N_("z/Architecture")}, \ | |
141 | { "esa", -32, N_("ESA/390 architecture")}, \ | |
142 | { "mvcle", 64, N_("mvcle use")}, \ | |
143 | { "no-mvcle", -64, N_("mvc&ex")}, \ | |
f26c1794 EC |
144 | { "tpf-trace", 128, N_("enable tpf OS tracing code")}, \ |
145 | { "no-tpf-trace", -128, N_("disable tpf OS tracing code")}, \ | |
f2d226e1 AK |
146 | { "no-fused-madd", 256, N_("disable fused multiply/add instructions")},\ |
147 | { "fused-madd", -256, N_("enable fused multiply/add instructions")}, \ | |
9db1d521 HP |
148 | { "", TARGET_DEFAULT, 0 } } |
149 | ||
d75f90f1 AK |
150 | #define TARGET_OPTIONS \ |
151 | { { "tune=", &s390_tune_string, \ | |
152 | N_("Schedule code for given CPU"), 0}, \ | |
153 | { "arch=", &s390_arch_string, \ | |
154 | N_("Generate code for given CPU"), 0}, \ | |
155 | { "backchain", &s390_backchain_string, \ | |
156 | N_("Set backchain"), "1"}, \ | |
157 | { "no-backchain", &s390_backchain_string, \ | |
158 | N_("Do not set backchain"), ""}, \ | |
159 | { "kernel-backchain", &s390_backchain_string, \ | |
160 | N_("Set backchain appropriate for the linux kernel"), "2"}, \ | |
161 | { "warn-framesize=", &s390_warn_framesize_string, \ | |
162 | N_("Warn if a single function's framesize exceeds the given framesize"), \ | |
163 | 0}, \ | |
164 | { "warn-dynamicstack", &s390_warn_dynamicstack_string, \ | |
165 | N_("Warn if a function uses alloca or creates an array with dynamic size"),\ | |
166 | 0}, \ | |
167 | { "stack-size=", &s390_stack_size_string, \ | |
168 | N_("Emit extra code in the function prologue in order to trap if the stack"\ | |
169 | "size exceeds the given limit"), 0}, \ | |
170 | { "stack-guard=", &s390_stack_guard_string, \ | |
171 | N_("Set the max. number of bytes which has to be left to stack size " \ | |
172 | "before a trap instruction is triggered"), 0}, \ | |
1fec52be HP |
173 | } |
174 | ||
f13e0d4e UW |
175 | /* Support for configure-time defaults. */ |
176 | #define OPTION_DEFAULT_SPECS \ | |
177 | { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" }, \ | |
178 | { "arch", "%{!march=*:-march=%(VALUE)}" }, \ | |
179 | { "tune", "%{!mtune=*:-mtune=%(VALUE)}" } | |
180 | ||
181 | /* Defaulting rules. */ | |
182 | #ifdef DEFAULT_TARGET_64BIT | |
183 | #define DRIVER_SELF_SPECS \ | |
184 | "%{!m31:%{!m64:-m64}}", \ | |
185 | "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ | |
186 | "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}" | |
187 | #else | |
188 | #define DRIVER_SELF_SPECS \ | |
189 | "%{!m31:%{!m64:-m31}}", \ | |
190 | "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ | |
191 | "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}" | |
192 | #endif | |
193 | ||
862a2d83 UW |
194 | /* Target version string. Overridden by the OS header. */ |
195 | #ifdef DEFAULT_TARGET_64BIT | |
196 | #define TARGET_VERSION fprintf (stderr, " (zSeries)"); | |
197 | #else | |
198 | #define TARGET_VERSION fprintf (stderr, " (S/390)"); | |
199 | #endif | |
9db1d521 | 200 | |
862a2d83 UW |
201 | /* Hooks to override options. */ |
202 | #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) optimization_options(LEVEL, SIZE) | |
4023fb28 UW |
203 | #define OVERRIDE_OPTIONS override_options () |
204 | ||
862a2d83 UW |
205 | /* Frame pointer is not used for debugging. */ |
206 | #define CAN_DEBUG_WITHOUT_FP | |
9db1d521 | 207 | |
9db1d521 | 208 | |
fe86047c UW |
209 | /* In libgcc2, determine target settings as compile-time constants. */ |
210 | #ifdef IN_LIBGCC2 | |
211 | #undef TARGET_64BIT | |
212 | #ifdef __s390x__ | |
213 | #define TARGET_64BIT 1 | |
214 | #else | |
215 | #define TARGET_64BIT 0 | |
216 | #endif | |
217 | #endif | |
218 | ||
219 | ||
9db1d521 HP |
220 | /* Target machine storage layout. */ |
221 | ||
862a2d83 | 222 | /* Everything is big-endian. */ |
9db1d521 | 223 | #define BITS_BIG_ENDIAN 1 |
9db1d521 | 224 | #define BYTES_BIG_ENDIAN 1 |
9db1d521 HP |
225 | #define WORDS_BIG_ENDIAN 1 |
226 | ||
9db1d521 | 227 | /* Width of a word, in units (bytes). */ |
9db1d521 | 228 | #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) |
fe86047c | 229 | #ifndef IN_LIBGCC2 |
9db1d521 | 230 | #define MIN_UNITS_PER_WORD 4 |
fe86047c | 231 | #endif |
862a2d83 | 232 | #define MAX_BITS_PER_WORD 64 |
9db1d521 | 233 | |
862a2d83 | 234 | /* Function arguments and return values are promoted to word size. */ |
d4453b7a | 235 | #define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \ |
9db1d521 HP |
236 | if (INTEGRAL_MODE_P (MODE) && \ |
237 | GET_MODE_SIZE (MODE) < UNITS_PER_WORD) { \ | |
238 | (MODE) = Pmode; \ | |
239 | } | |
240 | ||
9db1d521 | 241 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
9db1d521 HP |
242 | #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32) |
243 | ||
244 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
9db1d521 HP |
245 | #define STACK_BOUNDARY 64 |
246 | ||
247 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
9db1d521 HP |
248 | #define FUNCTION_BOUNDARY 32 |
249 | ||
250 | /* There is no point aligning anything to a rounder boundary than this. */ | |
9db1d521 HP |
251 | #define BIGGEST_ALIGNMENT 64 |
252 | ||
253 | /* Alignment of field after `int : 0' in a structure. */ | |
9db1d521 HP |
254 | #define EMPTY_FIELD_BOUNDARY 32 |
255 | ||
f710504c | 256 | /* Alignment on even addresses for LARL instruction. */ |
9db1d521 | 257 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) |
9db1d521 HP |
258 | #define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) |
259 | ||
862a2d83 | 260 | /* Alignment is not required by the hardware. */ |
9db1d521 HP |
261 | #define STRICT_ALIGNMENT 0 |
262 | ||
862a2d83 UW |
263 | /* Mode of stack savearea. |
264 | FUNCTION is VOIDmode because calling convention maintains SP. | |
265 | BLOCK needs Pmode for SP. | |
266 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ | |
267 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
268 | (LEVEL == SAVE_FUNCTION ? VOIDmode \ | |
43ab026f | 269 | : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode) |
862a2d83 | 270 | |
9db1d521 | 271 | /* Define target floating point format. */ |
8e509cf9 | 272 | #define TARGET_FLOAT_FORMAT \ |
862a2d83 | 273 | (TARGET_IEEE_FLOAT? IEEE_FLOAT_FORMAT : IBM_FLOAT_FORMAT) |
9db1d521 | 274 | |
9db1d521 | 275 | |
862a2d83 | 276 | /* Type layout. */ |
9db1d521 | 277 | |
862a2d83 UW |
278 | /* Sizes in bits of the source language data types. */ |
279 | #define SHORT_TYPE_SIZE 16 | |
280 | #define INT_TYPE_SIZE 32 | |
281 | #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) | |
862a2d83 UW |
282 | #define LONG_LONG_TYPE_SIZE 64 |
283 | #define FLOAT_TYPE_SIZE 32 | |
284 | #define DOUBLE_TYPE_SIZE 64 | |
285 | #define LONG_DOUBLE_TYPE_SIZE 64 /* ??? Should support extended format. */ | |
286 | ||
287 | /* We use "unsigned char" as default. */ | |
288 | #define DEFAULT_SIGNED_CHAR 0 | |
289 | ||
290 | ||
291 | /* Register usage. */ | |
292 | ||
293 | /* We have 16 general purpose registers (registers 0-15), | |
294 | and 16 floating point registers (registers 16-31). | |
295 | (On non-IEEE machines, we have only 4 fp registers.) | |
c7453384 | 296 | |
862a2d83 UW |
297 | Amongst the general purpose registers, some are used |
298 | for specific purposes: | |
299 | GPR 11: Hard frame pointer (if needed) | |
300 | GPR 12: Global offset table pointer (if needed) | |
301 | GPR 13: Literal pool base register | |
302 | GPR 14: Return address register | |
303 | GPR 15: Stack pointer | |
c7453384 | 304 | |
862a2d83 UW |
305 | Registers 32-34 are 'fake' hard registers that do not |
306 | correspond to actual hardware: | |
307 | Reg 32: Argument pointer | |
308 | Reg 33: Condition code | |
309 | Reg 34: Frame pointer */ | |
310 | ||
a38e09bc | 311 | #define FIRST_PSEUDO_REGISTER 36 |
862a2d83 UW |
312 | |
313 | /* Standard register usage. */ | |
8e509cf9 UW |
314 | #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16) |
315 | #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16) | |
316 | #define FP_REGNO_P(N) ((N) >= 16 && (N) < (TARGET_IEEE_FLOAT? 32 : 20)) | |
317 | #define CC_REGNO_P(N) ((N) == 33) | |
a38e09bc | 318 | #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34 || (N) == 35) |
8e509cf9 UW |
319 | |
320 | #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) | |
321 | #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X))) | |
322 | #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) | |
323 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) | |
4888ec5d | 324 | #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X))) |
9db1d521 | 325 | |
ed9676cf | 326 | #define SIBCALL_REGNUM 1 |
490ceeb4 | 327 | #define BASE_REGNUM 13 |
862a2d83 UW |
328 | #define RETURN_REGNUM 14 |
329 | #define CC_REGNUM 33 | |
4023fb28 | 330 | |
862a2d83 | 331 | /* Set up fixed registers and calling convention: |
9db1d521 | 332 | |
862a2d83 UW |
333 | GPRs 0-5 are always call-clobbered, |
334 | GPRs 6-15 are always call-saved. | |
335 | GPR 12 is fixed if used as GOT pointer. | |
336 | GPR 13 is always fixed (as literal pool pointer). | |
545d16ff | 337 | GPR 14 is always fixed on S/390 machines (as return address). |
862a2d83 UW |
338 | GPR 15 is always fixed (as stack pointer). |
339 | The 'fake' hard registers are call-clobbered and fixed. | |
9db1d521 | 340 | |
862a2d83 UW |
341 | On 31-bit, FPRs 18-19 are call-clobbered; |
342 | on 64-bit, FPRs 24-31 are call-clobbered. | |
343 | The remaining FPRs are call-saved. */ | |
9db1d521 HP |
344 | |
345 | #define FIXED_REGISTERS \ | |
346 | { 0, 0, 0, 0, \ | |
347 | 0, 0, 0, 0, \ | |
348 | 0, 0, 0, 0, \ | |
349 | 0, 1, 1, 1, \ | |
350 | 0, 0, 0, 0, \ | |
351 | 0, 0, 0, 0, \ | |
352 | 0, 0, 0, 0, \ | |
353 | 0, 0, 0, 0, \ | |
a38e09bc | 354 | 1, 1, 1, 1 } |
9db1d521 | 355 | |
9db1d521 HP |
356 | #define CALL_USED_REGISTERS \ |
357 | { 1, 1, 1, 1, \ | |
358 | 1, 1, 0, 0, \ | |
359 | 0, 0, 0, 0, \ | |
360 | 0, 1, 1, 1, \ | |
4023fb28 UW |
361 | 1, 1, 1, 1, \ |
362 | 1, 1, 1, 1, \ | |
363 | 1, 1, 1, 1, \ | |
364 | 1, 1, 1, 1, \ | |
a38e09bc | 365 | 1, 1, 1, 1 } |
4023fb28 | 366 | |
4023fb28 UW |
367 | #define CALL_REALLY_USED_REGISTERS \ |
368 | { 1, 1, 1, 1, \ | |
9db1d521 | 369 | 1, 1, 0, 0, \ |
4023fb28 UW |
370 | 0, 0, 0, 0, \ |
371 | 0, 0, 0, 0, \ | |
9db1d521 HP |
372 | 1, 1, 1, 1, \ |
373 | 1, 1, 1, 1, \ | |
374 | 1, 1, 1, 1, \ | |
4023fb28 | 375 | 1, 1, 1, 1, \ |
a38e09bc | 376 | 1, 1, 1, 1 } |
9db1d521 | 377 | |
38899e29 | 378 | #define CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage () |
9db1d521 | 379 | |
862a2d83 UW |
380 | /* Preferred register allocation order. */ |
381 | #define REG_ALLOC_ORDER \ | |
545d16ff | 382 | { 1, 2, 3, 4, 5, 0, 13, 12, 11, 10, 9, 8, 7, 6, 14, \ |
862a2d83 UW |
383 | 16, 17, 18, 19, 20, 21, 22, 23, \ |
384 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
a38e09bc | 385 | 15, 32, 33, 34, 35 } |
9db1d521 | 386 | |
9db1d521 | 387 | |
862a2d83 | 388 | /* Fitting values into registers. */ |
c7453384 | 389 | |
862a2d83 UW |
390 | /* Integer modes <= word size fit into any GPR. |
391 | Integer modes > word size fit into successive GPRs, starting with | |
392 | an even-numbered register. | |
393 | SImode and DImode fit into FPRs as well. | |
c7453384 | 394 | |
862a2d83 UW |
395 | Floating point modes <= word size fit into any FPR or GPR. |
396 | Floating point modes > word size (i.e. DFmode on 32-bit) fit | |
397 | into any FPR, or an even-odd GPR pair. | |
c7453384 | 398 | |
862a2d83 UW |
399 | Complex floating point modes fit either into two FPRs, or into |
400 | successive GPRs (again starting with an even number). | |
c7453384 | 401 | |
862a2d83 | 402 | Condition code modes fit only into the CC register. */ |
9db1d521 HP |
403 | |
404 | #define HARD_REGNO_NREGS(REGNO, MODE) \ | |
8e509cf9 | 405 | (FP_REGNO_P(REGNO)? \ |
9db1d521 | 406 | (GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \ |
8e509cf9 | 407 | GENERAL_REGNO_P(REGNO)? \ |
9db1d521 HP |
408 | ((GET_MODE_SIZE(MODE)+UNITS_PER_WORD-1) / UNITS_PER_WORD) : \ |
409 | 1) | |
410 | ||
9db1d521 | 411 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ |
8e509cf9 | 412 | (FP_REGNO_P(REGNO)? \ |
5d4d885c UW |
413 | ((MODE) == SImode || (MODE) == DImode || \ |
414 | GET_MODE_CLASS(MODE) == MODE_FLOAT || \ | |
415 | GET_MODE_CLASS(MODE) == MODE_COMPLEX_FLOAT) : \ | |
8e509cf9 | 416 | GENERAL_REGNO_P(REGNO)? \ |
f314b9b1 | 417 | (HARD_REGNO_NREGS(REGNO, MODE) == 1 || !((REGNO) & 1)) : \ |
9db1d521 HP |
418 | CC_REGNO_P(REGNO)? \ |
419 | GET_MODE_CLASS (MODE) == MODE_CC : \ | |
4888ec5d | 420 | FRAME_REGNO_P(REGNO)? \ |
bab0b43b | 421 | (enum machine_mode) (MODE) == Pmode : \ |
9db1d521 HP |
422 | 0) |
423 | ||
9db1d521 HP |
424 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
425 | (((MODE1) == SFmode || (MODE1) == DFmode) \ | |
426 | == ((MODE2) == SFmode || (MODE2) == DFmode)) | |
427 | ||
862a2d83 UW |
428 | /* Maximum number of registers to represent a value of mode MODE |
429 | in a register of class CLASS. */ | |
430 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
431 | ((CLASS) == FP_REGS ? \ | |
432 | (GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT ? 2 : 1) : \ | |
433 | (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) | |
4023fb28 | 434 | |
862a2d83 UW |
435 | /* If a 4-byte value is loaded into a FPR, it is placed into the |
436 | *upper* half of the register, not the lower. Therefore, we | |
437 | cannot use SUBREGs to switch between modes in FP registers. */ | |
b0c42aed JH |
438 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ |
439 | (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ | |
440 | ? reg_classes_intersect_p (FP_REGS, CLASS) : 0) | |
9db1d521 | 441 | |
862a2d83 | 442 | /* Register classes. */ |
c7453384 | 443 | |
862a2d83 UW |
444 | /* We use the following register classes: |
445 | GENERAL_REGS All general purpose registers | |
446 | ADDR_REGS All general purpose registers except %r0 | |
447 | (These registers can be used in address generation) | |
448 | FP_REGS All floating point registers | |
c7453384 | 449 | |
862a2d83 UW |
450 | GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS |
451 | ADDR_FP_REGS Union of ADDR_REGS and FP_REGS | |
c7453384 | 452 | |
862a2d83 UW |
453 | NO_REGS No registers |
454 | ALL_REGS All registers | |
c7453384 | 455 | |
862a2d83 UW |
456 | Note that the 'fake' frame pointer and argument pointer registers |
457 | are included amongst the address registers here. The condition | |
458 | code register is only included in ALL_REGS. */ | |
9db1d521 HP |
459 | |
460 | enum reg_class | |
461 | { | |
462 | NO_REGS, ADDR_REGS, GENERAL_REGS, | |
4023fb28 UW |
463 | FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, |
464 | ALL_REGS, LIM_REG_CLASSES | |
9db1d521 | 465 | }; |
9db1d521 HP |
466 | #define N_REG_CLASSES (int) LIM_REG_CLASSES |
467 | ||
9db1d521 | 468 | #define REG_CLASS_NAMES \ |
4023fb28 UW |
469 | { "NO_REGS", "ADDR_REGS", "GENERAL_REGS", \ |
470 | "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" } | |
9db1d521 | 471 | |
862a2d83 | 472 | /* Class -> register mapping. */ |
9db1d521 HP |
473 | #define REG_CLASS_CONTENTS \ |
474 | { \ | |
475 | { 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
a38e09bc AK |
476 | { 0x0000fffe, 0x0000000d }, /* ADDR_REGS */ \ |
477 | { 0x0000ffff, 0x0000000d }, /* GENERAL_REGS */ \ | |
9db1d521 | 478 | { 0xffff0000, 0x00000000 }, /* FP_REGS */ \ |
a38e09bc AK |
479 | { 0xfffffffe, 0x0000000d }, /* ADDR_FP_REGS */ \ |
480 | { 0xffffffff, 0x0000000d }, /* GENERAL_FP_REGS */ \ | |
481 | { 0xffffffff, 0x0000000f }, /* ALL_REGS */ \ | |
9db1d521 HP |
482 | } |
483 | ||
862a2d83 UW |
484 | /* Register -> class mapping. */ |
485 | extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; | |
486 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) | |
9db1d521 | 487 | |
862a2d83 UW |
488 | /* ADDR_REGS can be used as base or index register. */ |
489 | #define INDEX_REG_CLASS ADDR_REGS | |
490 | #define BASE_REG_CLASS ADDR_REGS | |
9db1d521 | 491 | |
862a2d83 UW |
492 | /* Check whether REGNO is a hard register of the suitable class |
493 | or a pseudo register currently allocated to one such. */ | |
494 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
495 | (((REGNO) < FIRST_PSEUDO_REGISTER \ | |
496 | && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \ | |
497 | || (reg_renumber[REGNO] > 0 && reg_renumber[REGNO] < 16)) | |
498 | #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) | |
9db1d521 | 499 | |
9db1d521 | 500 | |
862a2d83 UW |
501 | /* Given an rtx X being reloaded into a reg required to be in class CLASS, |
502 | return the class of reg to actually use. */ | |
503 | #define PREFERRED_RELOAD_CLASS(X, CLASS) \ | |
504 | s390_preferred_reload_class ((X), (CLASS)) | |
9db1d521 | 505 | |
862a2d83 UW |
506 | /* We need a secondary reload when loading a PLUS which is |
507 | not a valid operand for LOAD ADDRESS. */ | |
508 | #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \ | |
509 | s390_secondary_input_reload_class ((CLASS), (MODE), (IN)) | |
9db1d521 | 510 | |
dc65c307 UW |
511 | /* We need a secondary reload when storing a double-word |
512 | to a non-offsettable memory address. */ | |
513 | #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, OUT) \ | |
514 | s390_secondary_output_reload_class ((CLASS), (MODE), (OUT)) | |
515 | ||
862a2d83 UW |
516 | /* We need secondary memory to move data between GPRs and FPRs. */ |
517 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ | |
518 | ((CLASS1) != (CLASS2) && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS)) | |
519 | ||
520 | /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit | |
521 | because the movsi and movsf patterns don't handle r/f moves. */ | |
522 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
523 | (GET_MODE_BITSIZE (MODE) < 32 \ | |
524 | ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
525 | : MODE) | |
526 | ||
527 | ||
528 | /* Define various machine-dependent constraint letters. */ | |
9db1d521 HP |
529 | |
530 | #define REG_CLASS_FROM_LETTER(C) \ | |
531 | ((C) == 'a' ? ADDR_REGS : \ | |
532 | (C) == 'd' ? GENERAL_REGS : \ | |
533 | (C) == 'f' ? FP_REGS : NO_REGS) | |
534 | ||
f19a9af7 AK |
535 | #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \ |
536 | s390_const_ok_for_constraint_p ((VALUE), (C), (STR)) | |
9db1d521 | 537 | |
f19a9af7 | 538 | #define CONST_DOUBLE_OK_FOR_CONSTRAINT_P(VALUE, C, STR) 1 |
9db1d521 | 539 | |
f19a9af7 AK |
540 | #define EXTRA_CONSTRAINT_STR(OP, C, STR) \ |
541 | s390_extra_constraint_str ((OP), (C), (STR)) | |
d3632d41 UW |
542 | #define EXTRA_MEMORY_CONSTRAINT(C, STR) \ |
543 | ((C) == 'Q' || (C) == 'R' || (C) == 'S' || (C) == 'T') | |
544 | #define EXTRA_ADDRESS_CONSTRAINT(C, STR) \ | |
ac32b25e | 545 | ((C) == 'U' || (C) == 'W' || (C) == 'Y') |
ccfc6cc8 | 546 | |
f19a9af7 AK |
547 | #define CONSTRAINT_LEN(C, STR) \ |
548 | ((C) == 'N' ? 5 : DEFAULT_CONSTRAINT_LEN ((C), (STR))) | |
9db1d521 | 549 | |
862a2d83 | 550 | /* Stack layout and calling conventions. */ |
c7453384 | 551 | |
862a2d83 UW |
552 | /* Our stack grows from higher to lower addresses. However, local variables |
553 | are accessed by positive offsets, and function arguments are stored at | |
554 | increasing addresses. */ | |
555 | #define STACK_GROWS_DOWNWARD | |
556 | /* #undef FRAME_GROWS_DOWNWARD */ | |
557 | /* #undef ARGS_GROW_DOWNWARD */ | |
9db1d521 | 558 | |
862a2d83 UW |
559 | /* The basic stack layout looks like this: the stack pointer points |
560 | to the register save area for called functions. Above that area | |
561 | is the location to place outgoing arguments. Above those follow | |
562 | dynamic allocations (alloca), and finally the local variables. */ | |
9db1d521 | 563 | |
862a2d83 UW |
564 | /* Offset from stack-pointer to first location of outgoing args. */ |
565 | #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96) | |
9db1d521 | 566 | |
862a2d83 UW |
567 | /* Offset within stack frame to start allocating local variables at. */ |
568 | extern int current_function_outgoing_args_size; | |
569 | #define STARTING_FRAME_OFFSET \ | |
570 | (STACK_POINTER_OFFSET + current_function_outgoing_args_size) | |
9db1d521 | 571 | |
862a2d83 UW |
572 | /* Offset from the stack pointer register to an item dynamically |
573 | allocated on the stack, e.g., by `alloca'. */ | |
574 | #define STACK_DYNAMIC_OFFSET(FUNDECL) (STARTING_FRAME_OFFSET) | |
9db1d521 | 575 | |
862a2d83 UW |
576 | /* Offset of first parameter from the argument pointer register value. |
577 | We have a fake argument pointer register that points directly to | |
578 | the argument area. */ | |
579 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
9db1d521 | 580 | |
c7453384 | 581 | /* The return address of the current frame is retrieved |
4023fb28 UW |
582 | from the initial value of register RETURN_REGNUM. |
583 | For frames farther back, we use the stack slot where | |
584 | the corresponding RETURN_REGNUM register was saved. */ | |
585 | ||
adf39f8f AK |
586 | #define DYNAMIC_CHAIN_ADDRESS(FRAME) \ |
587 | (TARGET_BACKCHAIN ? \ | |
588 | ((FRAME) != hard_frame_pointer_rtx ? (FRAME) : \ | |
589 | plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET)) : \ | |
590 | ((FRAME) != hard_frame_pointer_rtx ? \ | |
591 | plus_constant ((FRAME), STACK_POINTER_OFFSET - UNITS_PER_WORD) : \ | |
592 | plus_constant (arg_pointer_rtx, -UNITS_PER_WORD))) | |
c7453384 | 593 | |
4023fb28 | 594 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
5d4d885c | 595 | s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME))) |
9db1d521 | 596 | |
862a2d83 | 597 | /* In 31-bit mode, we need to mask off the high bit of return addresses. */ |
a556fd39 | 598 | #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff)) |
9db1d521 | 599 | |
4023fb28 | 600 | |
862a2d83 | 601 | /* Exception handling. */ |
c7453384 | 602 | |
862a2d83 UW |
603 | /* Describe calling conventions for DWARF-2 exception handling. */ |
604 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM) | |
4023fb28 | 605 | #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET |
9db1d521 HP |
606 | #define DWARF_FRAME_RETURN_COLUMN 14 |
607 | ||
608 | /* Describe how we implement __builtin_eh_return. */ | |
609 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM) | |
a38e09bc AK |
610 | #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx) |
611 | ||
18789f4e UW |
612 | /* Select a format to encode pointers in exception handling data. */ |
613 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
614 | (flag_pic \ | |
615 | ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ | |
616 | : DW_EH_PE_absptr) | |
617 | ||
9db1d521 | 618 | |
862a2d83 | 619 | /* Frame registers. */ |
9db1d521 | 620 | |
862a2d83 UW |
621 | #define STACK_POINTER_REGNUM 15 |
622 | #define FRAME_POINTER_REGNUM 34 | |
623 | #define HARD_FRAME_POINTER_REGNUM 11 | |
624 | #define ARG_POINTER_REGNUM 32 | |
a38e09bc | 625 | #define RETURN_ADDRESS_POINTER_REGNUM 35 |
9db1d521 | 626 | |
c7453384 EC |
627 | /* The static chain must be call-clobbered, but not used for |
628 | function argument passing. As register 1 is clobbered by | |
862a2d83 UW |
629 | the trampoline code, we only have one option. */ |
630 | #define STATIC_CHAIN_REGNUM 0 | |
9db1d521 | 631 | |
862a2d83 UW |
632 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
633 | To avoid ABI incompatibility, this number must not change even as | |
634 | 'fake' hard registers are added or removed. */ | |
635 | #define DWARF_FRAME_REGISTERS 34 | |
9db1d521 | 636 | |
9db1d521 | 637 | |
862a2d83 | 638 | /* Frame pointer and argument pointer elimination. */ |
9db1d521 | 639 | |
862a2d83 | 640 | #define FRAME_POINTER_REQUIRED 0 |
9db1d521 HP |
641 | |
642 | #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) (DEPTH) = 0 | |
643 | ||
a38e09bc AK |
644 | #define ELIMINABLE_REGS \ |
645 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
646 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
647 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
648 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ | |
649 | { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ | |
650 | { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} | |
9db1d521 | 651 | |
862a2d83 | 652 | #define CAN_ELIMINATE(FROM, TO) (1) |
9db1d521 | 653 | |
862a2d83 UW |
654 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
655 | { if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ | |
656 | { (OFFSET) = 0; } \ | |
657 | else if ((FROM) == FRAME_POINTER_REGNUM \ | |
658 | && (TO) == HARD_FRAME_POINTER_REGNUM) \ | |
659 | { (OFFSET) = 0; } \ | |
660 | else if ((FROM) == ARG_POINTER_REGNUM \ | |
661 | && (TO) == HARD_FRAME_POINTER_REGNUM) \ | |
662 | { (OFFSET) = s390_arg_frame_offset (); } \ | |
663 | else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ | |
664 | { (OFFSET) = s390_arg_frame_offset (); } \ | |
a38e09bc AK |
665 | else if ((FROM) == RETURN_ADDRESS_POINTER_REGNUM \ |
666 | && ((TO) == STACK_POINTER_REGNUM \ | |
667 | || (TO) == HARD_FRAME_POINTER_REGNUM)) \ | |
668 | { (OFFSET) = s390_return_address_offset (); } \ | |
862a2d83 UW |
669 | else \ |
670 | abort(); \ | |
671 | } | |
9db1d521 | 672 | |
9db1d521 | 673 | |
862a2d83 | 674 | /* Stack arguments. */ |
c7453384 | 675 | |
862a2d83 UW |
676 | /* We need current_function_outgoing_args to be valid. */ |
677 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
9db1d521 | 678 | |
862a2d83 UW |
679 | /* Return doesn't modify the stack. */ |
680 | #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 | |
9db1d521 | 681 | |
9db1d521 | 682 | |
862a2d83 | 683 | /* Register arguments. */ |
c7453384 | 684 | |
9db1d521 HP |
685 | typedef struct s390_arg_structure |
686 | { | |
687 | int gprs; /* gpr so far */ | |
688 | int fprs; /* fpr so far */ | |
689 | } | |
690 | CUMULATIVE_ARGS; | |
691 | ||
07711f53 | 692 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \ |
9db1d521 HP |
693 | ((CUM).gprs=0, (CUM).fprs=0) |
694 | ||
9db1d521 | 695 | #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ |
994fe660 | 696 | s390_function_arg_advance (&CUM, MODE, TYPE, NAMED) |
9db1d521 | 697 | |
9db1d521 | 698 | #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ |
994fe660 | 699 | s390_function_arg (&CUM, MODE, TYPE, NAMED) |
9db1d521 | 700 | |
862a2d83 UW |
701 | #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 |
702 | ||
703 | /* Arguments can be placed in general registers 2 to 6, | |
704 | or in floating point registers 0 and 2. */ | |
705 | #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \ | |
706 | (N) == 16 || (N) == 17) | |
9db1d521 | 707 | |
9db1d521 | 708 | |
862a2d83 | 709 | /* Scalar return values. */ |
c7453384 | 710 | |
8c17530e UW |
711 | #define FUNCTION_VALUE(VALTYPE, FUNC) \ |
712 | s390_function_value ((VALTYPE), VOIDmode) | |
713 | ||
714 | #define LIBCALL_VALUE(MODE) \ | |
715 | s390_function_value (NULL, (MODE)) | |
9db1d521 | 716 | |
862a2d83 | 717 | /* Only gpr 2 and fpr 0 are ever used as return registers. */ |
9db1d521 HP |
718 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16) |
719 | ||
9db1d521 | 720 | |
862a2d83 | 721 | /* Function entry and exit. */ |
c7453384 | 722 | |
862a2d83 UW |
723 | /* When returning from a function, the stack pointer does not matter. */ |
724 | #define EXIT_IGNORE_STACK 1 | |
9db1d521 | 725 | |
9db1d521 | 726 | |
862a2d83 | 727 | /* Profiling. */ |
9db1d521 HP |
728 | |
729 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
862a2d83 | 730 | s390_function_profiler ((FILE), ((LABELNO))) |
9db1d521 | 731 | |
c52a375d | 732 | #define PROFILE_BEFORE_PROLOGUE 1 |
9db1d521 | 733 | |
9db1d521 | 734 | |
862a2d83 | 735 | /* Implementing the varargs macros. */ |
9db1d521 | 736 | |
862a2d83 UW |
737 | #define EXPAND_BUILTIN_VA_START(valist, nextarg) \ |
738 | s390_va_start (valist, nextarg) | |
9db1d521 | 739 | |
862a2d83 | 740 | /* Trampolines for nested functions. */ |
9db1d521 | 741 | |
862a2d83 | 742 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 36 : 20) |
9db1d521 | 743 | |
862a2d83 UW |
744 | #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, CXT) \ |
745 | s390_initialize_trampoline ((ADDR), (FNADDR), (CXT)) | |
9db1d521 | 746 | |
862a2d83 UW |
747 | #define TRAMPOLINE_TEMPLATE(FILE) \ |
748 | s390_trampoline_template (FILE) | |
9db1d521 | 749 | |
9db1d521 | 750 | |
862a2d83 | 751 | /* Addressing modes, and classification of registers for them. */ |
9db1d521 | 752 | |
862a2d83 UW |
753 | /* Recognize any constant value that is a valid address. */ |
754 | #define CONSTANT_ADDRESS_P(X) 0 | |
9db1d521 | 755 | |
862a2d83 UW |
756 | /* Maximum number of registers that can appear in a valid memory address. */ |
757 | #define MAX_REGS_PER_ADDRESS 2 | |
9db1d521 HP |
758 | |
759 | /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check | |
760 | its validity for a certain class. We have two alternate definitions | |
761 | for each of them. The usual definition accepts all pseudo regs; the | |
762 | other rejects them all. The symbol REG_OK_STRICT causes the latter | |
763 | definition to be used. | |
764 | ||
765 | Most source files want to accept pseudo regs in the hope that they will | |
766 | get allocated to the class that the insn wants them to be in. | |
767 | Some source files that are used after register allocation | |
768 | need to be strict. */ | |
769 | ||
4023fb28 UW |
770 | #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ |
771 | ((GET_MODE (X) == Pmode) && \ | |
772 | ((REGNO (X) >= FIRST_PSEUDO_REGISTER) \ | |
c7453384 | 773 | || REGNO_REG_CLASS (REGNO (X)) == ADDR_REGS)) |
9db1d521 | 774 | |
9db1d521 HP |
775 | #define REG_OK_FOR_BASE_NONSTRICT_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) |
776 | ||
9db1d521 HP |
777 | #define REG_OK_FOR_INDEX_STRICT_P(X) \ |
778 | ((GET_MODE (X) == Pmode) && (REGNO_OK_FOR_INDEX_P (REGNO (X)))) | |
779 | ||
9db1d521 HP |
780 | #define REG_OK_FOR_BASE_STRICT_P(X) \ |
781 | ((GET_MODE (X) == Pmode) && (REGNO_OK_FOR_BASE_P (REGNO (X)))) | |
782 | ||
9db1d521 HP |
783 | #ifndef REG_OK_STRICT |
784 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X) | |
785 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X) | |
786 | #else | |
787 | #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X) | |
788 | #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X) | |
789 | #endif | |
790 | ||
862a2d83 UW |
791 | /* S/390 has no mode dependent addresses. */ |
792 | #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) | |
9db1d521 HP |
793 | |
794 | /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a | |
795 | valid memory address for an instruction. | |
796 | The MODE argument is the machine mode for the MEM expression | |
862a2d83 | 797 | that wants to use this address. */ |
9db1d521 HP |
798 | #ifdef REG_OK_STRICT |
799 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
800 | { \ | |
801 | if (legitimate_address_p (MODE, X, 1)) \ | |
802 | goto ADDR; \ | |
803 | } | |
804 | #else | |
805 | #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ | |
806 | { \ | |
807 | if (legitimate_address_p (MODE, X, 0)) \ | |
808 | goto ADDR; \ | |
809 | } | |
810 | #endif | |
811 | ||
9db1d521 HP |
812 | /* Try machine-dependent ways of modifying an illegitimate address |
813 | to be legitimate. If we find one, return the new, valid address. | |
814 | This macro is used in only one place: `memory_address' in explow.c. */ | |
9db1d521 HP |
815 | #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ |
816 | { \ | |
817 | (X) = legitimize_address (X, OLDX, MODE); \ | |
818 | if (memory_address_p (MODE, X)) \ | |
819 | goto WIN; \ | |
820 | } | |
821 | ||
0b540f12 UW |
822 | /* Try a machine-dependent way of reloading an illegitimate address |
823 | operand. If we find one, push the reload and jump to WIN. This | |
824 | macro is used in only one place: `find_reloads_address' in reload.c. */ | |
825 | #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ | |
826 | do { \ | |
827 | rtx new = legitimize_reload_address (AD, MODE, OPNUM, (int)(TYPE)); \ | |
828 | if (new) \ | |
829 | { \ | |
830 | (AD) = new; \ | |
831 | goto WIN; \ | |
832 | } \ | |
833 | } while (0) | |
834 | ||
862a2d83 UW |
835 | /* Nonzero if the constant value X is a legitimate general operand. |
836 | It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ | |
837 | #define LEGITIMATE_CONSTANT_P(X) \ | |
838 | legitimate_constant_p (X) | |
9db1d521 | 839 | |
862a2d83 UW |
840 | /* Helper macro for s390.c and s390.md to check for symbolic constants. */ |
841 | #define SYMBOLIC_CONST(X) \ | |
842 | (GET_CODE (X) == SYMBOL_REF \ | |
843 | || GET_CODE (X) == LABEL_REF \ | |
844 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
9db1d521 | 845 | |
fd3cd001 UW |
846 | #define TLS_SYMBOLIC_CONST(X) \ |
847 | ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \ | |
848 | || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X))) | |
849 | ||
9db1d521 | 850 | |
862a2d83 | 851 | /* Condition codes. */ |
9db1d521 | 852 | |
862a2d83 UW |
853 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
854 | return the mode to be used for the comparison. */ | |
855 | #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y)) | |
c7453384 | 856 | |
68f9c5e2 UW |
857 | /* Canonicalize a comparison from one we don't have to one we do have. */ |
858 | #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ | |
859 | s390_canonicalize_comparison (&(CODE), &(OP0), &(OP1)) | |
860 | ||
862a2d83 UW |
861 | /* Define the information needed to generate branch and scc insns. This is |
862 | stored from the compare operation. Note that we can't use "rtx" here | |
863 | since it hasn't been defined! */ | |
864 | extern struct rtx_def *s390_compare_op0, *s390_compare_op1; | |
9db1d521 | 865 | |
9db1d521 | 866 | |
862a2d83 | 867 | /* Relative costs of operations. */ |
9db1d521 | 868 | |
9db1d521 | 869 | /* On s390, copy between fprs and gprs is expensive. */ |
9db1d521 | 870 | #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ |
14b3e8ef UW |
871 | (( ( reg_classes_intersect_p ((CLASS1), GENERAL_REGS) \ |
872 | && reg_classes_intersect_p ((CLASS2), FP_REGS)) \ | |
873 | || ( reg_classes_intersect_p ((CLASS1), FP_REGS) \ | |
874 | && reg_classes_intersect_p ((CLASS2), GENERAL_REGS))) ? 10 : 1) | |
9db1d521 | 875 | |
9db1d521 HP |
876 | /* A C expression for the cost of moving data of mode M between a |
877 | register and memory. A value of 2 is the default; this cost is | |
862a2d83 | 878 | relative to those in `REGISTER_MOVE_COST'. */ |
9db1d521 HP |
879 | #define MEMORY_MOVE_COST(M, C, I) 1 |
880 | ||
881 | /* A C expression for the cost of a branch instruction. A value of 1 | |
882 | is the default; other values are interpreted relative to that. */ | |
9db1d521 HP |
883 | #define BRANCH_COST 1 |
884 | ||
862a2d83 UW |
885 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
886 | #define SLOW_BYTE_ACCESS 1 | |
887 | ||
c5443745 UW |
888 | /* An integer expression for the size in bits of the largest integer machine |
889 | mode that should actually be used. We allow pairs of registers. */ | |
890 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) | |
891 | ||
862a2d83 | 892 | /* The maximum number of bytes that a single instruction can move quickly |
ff482c8d | 893 | between memory and registers or between two memory locations. */ |
862a2d83 | 894 | #define MOVE_MAX (TARGET_64BIT ? 16 : 8) |
c5443745 | 895 | #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) |
862a2d83 | 896 | #define MAX_MOVE_MAX 16 |
9db1d521 | 897 | |
862a2d83 UW |
898 | /* Determine whether to use move_by_pieces or block move insn. */ |
899 | #define MOVE_BY_PIECES_P(SIZE, ALIGN) \ | |
900 | ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ | |
901 | || (TARGET_64BIT && (SIZE) == 8) ) | |
902 | ||
903 | /* Determine whether to use clear_by_pieces or block clear insn. */ | |
904 | #define CLEAR_BY_PIECES_P(SIZE, ALIGN) \ | |
905 | ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ | |
906 | || (TARGET_64BIT && (SIZE) == 8) ) | |
907 | ||
45d78e7f JJ |
908 | /* This macro is used to determine whether store_by_pieces should be |
909 | called to "memset" storage with byte values other than zero, or | |
910 | to "memcpy" storage when the source is a constant string. */ | |
911 | #define STORE_BY_PIECES_P(SIZE, ALIGN) MOVE_BY_PIECES_P (SIZE, ALIGN) | |
912 | ||
862a2d83 UW |
913 | /* Don't perform CSE on function addresses. */ |
914 | #define NO_FUNCTION_CSE | |
915 | ||
916 | ||
917 | /* Sections. */ | |
918 | ||
919 | /* Output before read-only data. */ | |
920 | #define TEXT_SECTION_ASM_OP ".text" | |
921 | ||
922 | /* Output before writable (initialized) data. */ | |
923 | #define DATA_SECTION_ASM_OP ".data" | |
924 | ||
925 | /* Output before writable (uninitialized) data. */ | |
926 | #define BSS_SECTION_ASM_OP ".bss" | |
927 | ||
928 | /* S/390 constant pool breaks the devices in crtstuff.c to control section | |
929 | in where code resides. We have to write it as asm code. */ | |
930 | #ifndef __s390x__ | |
931 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
932 | asm (SECTION_OP "\n\ | |
933 | bras\t%r2,1f\n\ | |
934 | 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\ | |
935 | 1: l\t%r3,0(%r2)\n\ | |
936 | bas\t%r14,0(%r3,%r2)\n\ | |
937 | .previous"); | |
938 | #endif | |
63a1ff86 | 939 | |
862a2d83 UW |
940 | |
941 | /* Position independent code. */ | |
942 | ||
c7453384 | 943 | extern int flag_pic; |
862a2d83 UW |
944 | |
945 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM) | |
946 | ||
947 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) | |
63a1ff86 UW |
948 | |
949 | ||
950 | /* Assembler file format. */ | |
951 | ||
952 | /* Character to start a comment. */ | |
953 | #define ASM_COMMENT_START "#" | |
954 | ||
955 | /* Declare an uninitialized external linkage data object. */ | |
956 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
957 | asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) | |
958 | ||
959 | /* Globalizing directive for a label. */ | |
960 | #define GLOBAL_ASM_OP ".globl " | |
961 | ||
962 | /* Advance the location counter to a multiple of 2**LOG bytes. */ | |
963 | #define ASM_OUTPUT_ALIGN(FILE, LOG) \ | |
964 | if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG)) | |
965 | ||
966 | /* Advance the location counter by SIZE bytes. */ | |
967 | #define ASM_OUTPUT_SKIP(FILE, SIZE) \ | |
58e15542 | 968 | fprintf ((FILE), "\t.set\t.,.+"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) |
63a1ff86 | 969 | |
63a1ff86 UW |
970 | /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */ |
971 | #define LOCAL_LABEL_PREFIX "." | |
9db1d521 HP |
972 | |
973 | /* How to refer to registers in assembler output. This sequence is | |
974 | indexed by compiler's hard-register-number (see above). */ | |
9db1d521 HP |
975 | #define REGISTER_NAMES \ |
976 | { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ | |
a38e09bc | 977 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ |
9db1d521 | 978 | "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \ |
a38e09bc AK |
979 | "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \ |
980 | "%ap", "%cc", "%fp", "%rp" \ | |
9db1d521 HP |
981 | } |
982 | ||
6b2300b3 JJ |
983 | /* Emit a dtp-relative reference to a TLS variable. */ |
984 | ||
985 | #ifdef HAVE_AS_TLS | |
986 | #define ASM_OUTPUT_DWARF_DTPREL(FILE, SIZE, X) \ | |
987 | s390_output_dwarf_dtprel (FILE, SIZE, X) | |
988 | #endif | |
989 | ||
63a1ff86 | 990 | /* Print operand X (an rtx) in assembler syntax to file FILE. */ |
9db1d521 | 991 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) |
9db1d521 HP |
992 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) |
993 | ||
faeb9bb6 UW |
994 | /* Output machine-dependent UNSPECs in address constants. */ |
995 | #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ | |
996 | do { \ | |
997 | if (!s390_output_addr_const_extra (FILE, (X))) \ | |
998 | goto FAIL; \ | |
999 | } while (0); | |
1000 | ||
63a1ff86 UW |
1001 | /* Output an element of a case-vector that is absolute. */ |
1002 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
1003 | do { \ | |
1004 | char buf[32]; \ | |
1005 | fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \ | |
1006 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ | |
1007 | assemble_name ((FILE), buf); \ | |
1008 | fputc ('\n', (FILE)); \ | |
1009 | } while (0) | |
1010 | ||
1011 | /* Output an element of a case-vector that is relative. */ | |
1012 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
1013 | do { \ | |
1014 | char buf[32]; \ | |
1015 | fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \ | |
1016 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ | |
1017 | assemble_name ((FILE), buf); \ | |
1018 | fputc ('-', (FILE)); \ | |
1019 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \ | |
1020 | assemble_name ((FILE), buf); \ | |
1021 | fputc ('\n', (FILE)); \ | |
1022 | } while (0) | |
1023 | ||
9db1d521 | 1024 | |
862a2d83 UW |
1025 | /* Miscellaneous parameters. */ |
1026 | ||
1027 | /* Define the codes that are matched by predicates in aux-output.c. */ | |
1028 | #define PREDICATE_CODES \ | |
1029 | {"s_operand", { SUBREG, MEM }}, \ | |
1030 | {"s_imm_operand", { CONST_INT, CONST_DOUBLE, SUBREG, MEM }}, \ | |
ac32b25e | 1031 | {"shift_count_operand", { REG, SUBREG, PLUS, CONST_INT }}, \ |
862a2d83 UW |
1032 | {"bras_sym_operand",{ SYMBOL_REF, CONST }}, \ |
1033 | {"larl_operand", { SYMBOL_REF, CONST, CONST_INT, CONST_DOUBLE }}, \ | |
1034 | {"load_multiple_operation", {PARALLEL}}, \ | |
1035 | {"store_multiple_operation", {PARALLEL}}, \ | |
1036 | {"const0_operand", { CONST_INT, CONST_DOUBLE }}, \ | |
1037 | {"consttable_operand", { SYMBOL_REF, LABEL_REF, CONST, \ | |
1038 | CONST_INT, CONST_DOUBLE }}, \ | |
e69166de | 1039 | {"s390_plus_operand", { PLUS }}, \ |
5d880bd2 UW |
1040 | {"s390_alc_comparison", { ZERO_EXTEND, SIGN_EXTEND, \ |
1041 | LTU, GTU, LEU, GEU }}, \ | |
1042 | {"s390_slb_comparison", { ZERO_EXTEND, SIGN_EXTEND, \ | |
1043 | LTU, GTU, LEU, GEU }}, | |
862a2d83 UW |
1044 | |
1045 | /* Specify the machine mode that this machine uses for the index in the | |
1046 | tablejump instruction. */ | |
1047 | #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) | |
1048 | ||
862a2d83 UW |
1049 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
1050 | is done just by pretending it is already truncated. */ | |
1051 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
1052 | ||
1053 | /* Specify the machine mode that pointers have. | |
1054 | After generation of rtl, the compiler makes no further distinction | |
1055 | between pointers and any other objects of this machine mode. */ | |
1056 | #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode)) | |
1057 | ||
c7453384 EC |
1058 | /* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */ |
1059 | #define POINTERS_EXTEND_UNSIGNED -1 | |
1060 | ||
862a2d83 UW |
1061 | /* A function address in a call instruction is a byte address (for |
1062 | indexing purposes) so give the MEM rtx a byte's mode. */ | |
1063 | #define FUNCTION_MODE QImode | |
1064 | ||
c7453384 | 1065 | #endif |