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9db1d521 | 1 | /* Definitions of target machine for GNU compiler, for IBM S/390 |
a5544970 | 2 | Copyright (C) 1999-2019 Free Software Foundation, Inc. |
9db1d521 | 3 | Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
0ff3dcd6 AK |
4 | Ulrich Weigand (uweigand@de.ibm.com). |
5 | Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 6 | |
58add37a | 7 | This file is part of GCC. |
9db1d521 | 8 | |
58add37a UW |
9 | GCC is free software; you can redistribute it and/or modify it under |
10 | the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | version. |
13 | ||
14 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | for more details. | |
9db1d521 HP |
18 | |
19 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. */ | |
9db1d521 HP |
22 | |
23 | #ifndef _S390_H | |
24 | #define _S390_H | |
25 | ||
f13e0d4e UW |
26 | /* Optional architectural facilities supported by the processor. */ |
27 | ||
28 | enum processor_flags | |
29 | { | |
30 | PF_IEEE_FLOAT = 1, | |
31 | PF_ZARCH = 2, | |
ec24698e | 32 | PF_LONG_DISPLACEMENT = 4, |
85dae55a | 33 | PF_EXTIMM = 8, |
93538e8e | 34 | PF_DFP = 16, |
65b1d8ea | 35 | PF_Z10 = 32, |
22ac2c2f | 36 | PF_Z196 = 64, |
5a3fe9b6 | 37 | PF_ZEC12 = 128, |
55ac540c AK |
38 | PF_TX = 256, |
39 | PF_Z13 = 512, | |
6654e96f | 40 | PF_VX = 1024, |
e9e8efc9 | 41 | PF_Z14 = 2048, |
6654e96f | 42 | PF_VXE = 4096 |
f13e0d4e UW |
43 | }; |
44 | ||
90c6fd8a AK |
45 | /* This is necessary to avoid a warning about comparing different enum |
46 | types. */ | |
6654e96f | 47 | #define s390_tune_attr ((enum attr_cpu)(s390_tune > PROCESSOR_2964_Z13 ? PROCESSOR_2964_Z13 : s390_tune )) |
90c6fd8a | 48 | |
963fc8d0 AK |
49 | /* These flags indicate that the generated code should run on a cpu |
50 | providing the respective hardware facility regardless of the | |
51 | current cpu mode (ESA or z/Architecture). */ | |
52 | ||
f13e0d4e UW |
53 | #define TARGET_CPU_IEEE_FLOAT \ |
54 | (s390_arch_flags & PF_IEEE_FLOAT) | |
ec47b086 DV |
55 | #define TARGET_CPU_IEEE_FLOAT_P(opts) \ |
56 | (opts->x_s390_arch_flags & PF_IEEE_FLOAT) | |
f13e0d4e UW |
57 | #define TARGET_CPU_LONG_DISPLACEMENT \ |
58 | (s390_arch_flags & PF_LONG_DISPLACEMENT) | |
ec47b086 DV |
59 | #define TARGET_CPU_LONG_DISPLACEMENT_P(opts) \ |
60 | (opts->x_s390_arch_flags & PF_LONG_DISPLACEMENT) | |
ec24698e | 61 | #define TARGET_CPU_EXTIMM \ |
ec47b086 DV |
62 | (s390_arch_flags & PF_EXTIMM) |
63 | #define TARGET_CPU_EXTIMM_P(opts) \ | |
64 | (opts->x_s390_arch_flags & PF_EXTIMM) | |
85dae55a | 65 | #define TARGET_CPU_DFP \ |
ec47b086 DV |
66 | (s390_arch_flags & PF_DFP) |
67 | #define TARGET_CPU_DFP_P(opts) \ | |
68 | (opts->x_s390_arch_flags & PF_DFP) | |
93538e8e | 69 | #define TARGET_CPU_Z10 \ |
ec47b086 DV |
70 | (s390_arch_flags & PF_Z10) |
71 | #define TARGET_CPU_Z10_P(opts) \ | |
72 | (opts->x_s390_arch_flags & PF_Z10) | |
65b1d8ea | 73 | #define TARGET_CPU_Z196 \ |
ec47b086 DV |
74 | (s390_arch_flags & PF_Z196) |
75 | #define TARGET_CPU_Z196_P(opts) \ | |
76 | (opts->x_s390_arch_flags & PF_Z196) | |
22ac2c2f | 77 | #define TARGET_CPU_ZEC12 \ |
ec47b086 DV |
78 | (s390_arch_flags & PF_ZEC12) |
79 | #define TARGET_CPU_ZEC12_P(opts) \ | |
80 | (opts->x_s390_arch_flags & PF_ZEC12) | |
5a3fe9b6 | 81 | #define TARGET_CPU_HTM \ |
ec47b086 DV |
82 | (s390_arch_flags & PF_TX) |
83 | #define TARGET_CPU_HTM_P(opts) \ | |
84 | (opts->x_s390_arch_flags & PF_TX) | |
55ac540c | 85 | #define TARGET_CPU_Z13 \ |
ec47b086 DV |
86 | (s390_arch_flags & PF_Z13) |
87 | #define TARGET_CPU_Z13_P(opts) \ | |
6654e96f | 88 | (opts->x_s390_arch_flags & PF_Z13) |
55ac540c | 89 | #define TARGET_CPU_VX \ |
6654e96f | 90 | (s390_arch_flags & PF_VX) |
ec47b086 DV |
91 | #define TARGET_CPU_VX_P(opts) \ |
92 | (opts->x_s390_arch_flags & PF_VX) | |
e9e8efc9 AK |
93 | #define TARGET_CPU_Z14 \ |
94 | (s390_arch_flags & PF_Z14) | |
95 | #define TARGET_CPU_Z14_P(opts) \ | |
96 | (opts->x_s390_arch_flags & PF_Z14) | |
6654e96f AK |
97 | #define TARGET_CPU_VXE \ |
98 | (s390_arch_flags & PF_VXE) | |
99 | #define TARGET_CPU_VXE_P(opts) \ | |
100 | (opts->x_s390_arch_flags & PF_VXE) | |
ec47b086 DV |
101 | |
102 | #define TARGET_HARD_FLOAT_P(opts) (!TARGET_SOFT_FLOAT_P(opts)) | |
f13e0d4e | 103 | |
963fc8d0 AK |
104 | /* These flags indicate that the generated code should run on a cpu |
105 | providing the respective hardware facility when run in | |
106 | z/Architecture mode. */ | |
107 | ||
f13e0d4e | 108 | #define TARGET_LONG_DISPLACEMENT \ |
ec47b086 DV |
109 | (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT) |
110 | #define TARGET_LONG_DISPLACEMENT_P(opts) \ | |
111 | (TARGET_ZARCH_P (opts->x_target_flags) \ | |
112 | && TARGET_CPU_LONG_DISPLACEMENT_P (opts)) | |
ec24698e | 113 | #define TARGET_EXTIMM \ |
ec47b086 DV |
114 | (TARGET_ZARCH && TARGET_CPU_EXTIMM) |
115 | #define TARGET_EXTIMM_P(opts) \ | |
116 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_EXTIMM_P (opts)) | |
85dae55a | 117 | #define TARGET_DFP \ |
ec47b086 DV |
118 | (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT) |
119 | #define TARGET_DFP_P(opts) \ | |
120 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_DFP_P (opts) \ | |
121 | && TARGET_HARD_FLOAT_P (opts->x_target_flags)) | |
93538e8e | 122 | #define TARGET_Z10 \ |
ec47b086 DV |
123 | (TARGET_ZARCH && TARGET_CPU_Z10) |
124 | #define TARGET_Z10_P(opts) \ | |
125 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z10_P (opts)) | |
65b1d8ea | 126 | #define TARGET_Z196 \ |
ec47b086 DV |
127 | (TARGET_ZARCH && TARGET_CPU_Z196) |
128 | #define TARGET_Z196_P(opts) \ | |
129 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z196_P (opts)) | |
22ac2c2f | 130 | #define TARGET_ZEC12 \ |
ec47b086 DV |
131 | (TARGET_ZARCH && TARGET_CPU_ZEC12) |
132 | #define TARGET_ZEC12_P(opts) \ | |
133 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_ZEC12_P (opts)) | |
167f68ed | 134 | #define TARGET_HTM (TARGET_OPT_HTM) |
ec47b086 | 135 | #define TARGET_HTM_P(opts) (TARGET_OPT_HTM_P (opts->x_target_flags)) |
55ac540c | 136 | #define TARGET_Z13 \ |
ec47b086 DV |
137 | (TARGET_ZARCH && TARGET_CPU_Z13) |
138 | #define TARGET_Z13_P(opts) \ | |
139 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z13_P (opts)) | |
55ac540c | 140 | #define TARGET_VX \ |
ec47b086 DV |
141 | (TARGET_ZARCH && TARGET_CPU_VX && TARGET_OPT_VX && TARGET_HARD_FLOAT) |
142 | #define TARGET_VX_P(opts) \ | |
143 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_VX_P (opts) \ | |
144 | && TARGET_OPT_VX_P (opts->x_target_flags) \ | |
145 | && TARGET_HARD_FLOAT_P (opts->x_target_flags)) | |
e9e8efc9 AK |
146 | #define TARGET_Z14 (TARGET_ZARCH && TARGET_CPU_Z14) |
147 | #define TARGET_Z14_P(opts) \ | |
148 | (TARGET_ZARCH_P (opts->x_target_flags) && TARGET_CPU_Z14_P (opts)) | |
6654e96f AK |
149 | #define TARGET_VXE \ |
150 | (TARGET_VX && TARGET_CPU_VXE) | |
151 | #define TARGET_VXE_P(opts) \ | |
152 | (TARGET_VX_P (opts) && TARGET_CPU_VXE_P (opts)) | |
ec47b086 DV |
153 | |
154 | #ifdef HAVE_AS_MACHINE_MACHINEMODE | |
155 | #define S390_USE_TARGET_ATTRIBUTE 1 | |
156 | #else | |
157 | #define S390_USE_TARGET_ATTRIBUTE 0 | |
158 | #endif | |
159 | ||
160 | #ifdef HAVE_AS_ARCHITECTURE_MODIFIERS | |
161 | #define S390_USE_ARCHITECTURE_MODIFIERS 1 | |
162 | #else | |
163 | #define S390_USE_ARCHITECTURE_MODIFIERS 0 | |
164 | #endif | |
165 | ||
166 | #if S390_USE_TARGET_ATTRIBUTE | |
167 | /* For switching between functions with different target attributes. */ | |
168 | #define SWITCHABLE_TARGET 1 | |
169 | #endif | |
65b1d8ea | 170 | |
089b05b1 DV |
171 | #define TARGET_SUPPORTS_WIDE_INT 1 |
172 | ||
55ac540c AK |
173 | /* Use the ABI introduced with IBM z13: |
174 | - pass vector arguments <= 16 bytes in VRs | |
175 | - align *all* vector types to 8 bytes */ | |
176 | #define TARGET_VX_ABI TARGET_VX | |
65b1d8ea AK |
177 | |
178 | #define TARGET_AVOID_CMP_AND_BRANCH (s390_tune == PROCESSOR_2817_Z196) | |
42c78618 | 179 | |
4de3a1e1 AK |
180 | /* Issue a write prefetch for the +4 cache line. */ |
181 | #define TARGET_SETMEM_PREFETCH_DISTANCE 1024 | |
182 | ||
183 | /* Expand to a C expressions evaluating to true if a setmem to VAL of | |
184 | length LEN should be emitted using prefetch instructions. */ | |
185 | #define TARGET_SETMEM_PFD(VAL,LEN) \ | |
186 | (TARGET_Z10 \ | |
187 | && (s390_tune < PROCESSOR_2964_Z13 || (VAL) != const0_rtx) \ | |
188 | && (!CONST_INT_P (LEN) || INTVAL ((LEN)) > TARGET_SETMEM_PREFETCH_DISTANCE)) | |
189 | ||
862a2d83 | 190 | /* Run-time target specification. */ |
9db1d521 | 191 | |
a771c4b3 UW |
192 | /* Defaults for option flags defined only on some subtargets. */ |
193 | #ifndef TARGET_TPF_PROFILING | |
194 | #define TARGET_TPF_PROFILING 0 | |
195 | #endif | |
196 | ||
4798630c D |
197 | /* This will be overridden by OS headers. */ |
198 | #define TARGET_TPF 0 | |
199 | ||
862a2d83 | 200 | /* Target CPU builtins. */ |
3af82a61 | 201 | #define TARGET_CPU_CPP_BUILTINS() s390_cpu_cpp_builtins (pfile) |
9db1d521 | 202 | |
b4c522fa IB |
203 | /* Target CPU versions for D. */ |
204 | #define TARGET_D_CPU_VERSIONS s390_d_target_versions | |
205 | ||
58d10f89 | 206 | #ifdef DEFAULT_TARGET_64BIT |
55ac540c | 207 | #define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP \ |
0ff3dcd6 | 208 | | MASK_OPT_HTM | MASK_OPT_VX) |
58d10f89 | 209 | #else |
85dae55a | 210 | #define TARGET_DEFAULT 0 |
58d10f89 UW |
211 | #endif |
212 | ||
f13e0d4e | 213 | /* Support for configure-time defaults. */ |
0ff3dcd6 | 214 | #define OPTION_DEFAULT_SPECS \ |
f13e0d4e UW |
215 | { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" }, \ |
216 | { "arch", "%{!march=*:-march=%(VALUE)}" }, \ | |
4723f0fb | 217 | { "tune", "%{!mtune=*:%{!march=*:-mtune=%(VALUE)}}" } |
f13e0d4e | 218 | |
63281f61 | 219 | #ifdef __s390__ |
cb0edc39 DV |
220 | extern const char *s390_host_detect_local_cpu (int argc, const char **argv); |
221 | # define EXTRA_SPEC_FUNCTIONS \ | |
222 | { "local_cpu_detect", s390_host_detect_local_cpu }, | |
223 | ||
b1b5aa2f DV |
224 | #define MARCH_MTUNE_NATIVE_SPECS \ |
225 | "%{mtune=native:%<mtune=native %:local_cpu_detect(tune)} " \ | |
226 | "%{march=native:%<march=native" \ | |
227 | " %:local_cpu_detect(arch %{mesa|mzarch:mesa_mzarch})}" | |
63281f61 DV |
228 | #else |
229 | # define MARCH_MTUNE_NATIVE_SPECS "" | |
230 | #endif | |
cb0edc39 | 231 | |
f13e0d4e | 232 | #ifdef DEFAULT_TARGET_64BIT |
b1b5aa2f | 233 | #define S390_TARGET_BITS_STRING "64" |
f13e0d4e | 234 | #else |
b1b5aa2f DV |
235 | #define S390_TARGET_BITS_STRING "31" |
236 | #endif | |
237 | ||
238 | /* Defaulting rules. */ | |
f13e0d4e | 239 | #define DRIVER_SELF_SPECS \ |
b1b5aa2f DV |
240 | MARCH_MTUNE_NATIVE_SPECS, \ |
241 | "%{!m31:%{!m64:-m" S390_TARGET_BITS_STRING "}}", \ | |
f13e0d4e | 242 | "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ |
6638efce | 243 | "%{!march=*:-march=z900}" |
f13e0d4e | 244 | |
638e37c2 | 245 | /* Constants needed to control the TEST DATA CLASS (TDC) instruction. */ |
0387c142 WG |
246 | #define S390_TDC_POSITIVE_ZERO (1 << 11) |
247 | #define S390_TDC_NEGATIVE_ZERO (1 << 10) | |
248 | #define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER (1 << 9) | |
249 | #define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER (1 << 8) | |
250 | #define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER (1 << 7) | |
251 | #define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER (1 << 6) | |
252 | #define S390_TDC_POSITIVE_INFINITY (1 << 5) | |
253 | #define S390_TDC_NEGATIVE_INFINITY (1 << 4) | |
254 | #define S390_TDC_POSITIVE_QUIET_NAN (1 << 3) | |
255 | #define S390_TDC_NEGATIVE_QUIET_NAN (1 << 2) | |
256 | #define S390_TDC_POSITIVE_SIGNALING_NAN (1 << 1) | |
257 | #define S390_TDC_NEGATIVE_SIGNALING_NAN (1 << 0) | |
258 | ||
259 | /* The following values are different for DFP. */ | |
260 | #define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9) | |
261 | #define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8) | |
262 | #define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER (1 << 7) | |
263 | #define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER (1 << 6) | |
264 | ||
f4aa3848 | 265 | /* For signbit, the BFP-DFP-difference makes no difference. */ |
0f67fa83 | 266 | #define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \ |
0ff3dcd6 AK |
267 | | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \ |
268 | | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\ | |
269 | | S390_TDC_NEGATIVE_INFINITY \ | |
270 | | S390_TDC_NEGATIVE_QUIET_NAN \ | |
0f67fa83 WG |
271 | | S390_TDC_NEGATIVE_SIGNALING_NAN ) |
272 | ||
638e37c2 WG |
273 | #define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \ |
274 | | S390_TDC_NEGATIVE_INFINITY ) | |
9db1d521 HP |
275 | |
276 | /* Target machine storage layout. */ | |
277 | ||
862a2d83 | 278 | /* Everything is big-endian. */ |
9db1d521 | 279 | #define BITS_BIG_ENDIAN 1 |
9db1d521 | 280 | #define BYTES_BIG_ENDIAN 1 |
9db1d521 HP |
281 | #define WORDS_BIG_ENDIAN 1 |
282 | ||
9602b6a1 AK |
283 | #define STACK_SIZE_MODE (Pmode) |
284 | ||
fe86047c | 285 | #ifndef IN_LIBGCC2 |
9602b6a1 AK |
286 | |
287 | /* Width of a word, in units (bytes). */ | |
288 | #define UNITS_PER_WORD (TARGET_ZARCH ? 8 : 4) | |
289 | ||
290 | /* Width of a pointer. To be used instead of UNITS_PER_WORD in | |
291 | ABI-relevant contexts. This always matches | |
292 | GET_MODE_SIZE (Pmode). */ | |
293 | #define UNITS_PER_LONG (TARGET_64BIT ? 8 : 4) | |
294 | #define MIN_UNITS_PER_WORD 4 | |
295 | #define MAX_BITS_PER_WORD 64 | |
296 | #else | |
297 | ||
298 | /* In libgcc, UNITS_PER_WORD has ABI-relevant effects, e.g. whether | |
299 | the library should export TImode functions or not. Thus, we have | |
300 | to redefine UNITS_PER_WORD depending on __s390x__ for libgcc. */ | |
301 | #ifdef __s390x__ | |
302 | #define UNITS_PER_WORD 8 | |
303 | #else | |
304 | #define UNITS_PER_WORD 4 | |
305 | #endif | |
fe86047c | 306 | #endif |
9602b6a1 AK |
307 | |
308 | /* Width of a pointer, in bits. */ | |
309 | #define POINTER_SIZE (TARGET_64BIT ? 64 : 32) | |
9db1d521 | 310 | |
9db1d521 | 311 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
9db1d521 HP |
312 | #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32) |
313 | ||
314 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
9db1d521 HP |
315 | #define STACK_BOUNDARY 64 |
316 | ||
317 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
d0de9e13 | 318 | #define FUNCTION_BOUNDARY 64 |
9db1d521 HP |
319 | |
320 | /* There is no point aligning anything to a rounder boundary than this. */ | |
9db1d521 HP |
321 | #define BIGGEST_ALIGNMENT 64 |
322 | ||
323 | /* Alignment of field after `int : 0' in a structure. */ | |
9db1d521 HP |
324 | #define EMPTY_FIELD_BOUNDARY 32 |
325 | ||
f710504c | 326 | /* Alignment on even addresses for LARL instruction. */ |
df8a1d28 | 327 | #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) |
9db1d521 | 328 | |
862a2d83 | 329 | /* Alignment is not required by the hardware. */ |
9db1d521 HP |
330 | #define STRICT_ALIGNMENT 0 |
331 | ||
862a2d83 UW |
332 | /* Mode of stack savearea. |
333 | FUNCTION is VOIDmode because calling convention maintains SP. | |
334 | BLOCK needs Pmode for SP. | |
335 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ | |
2d6744f4 AK |
336 | #define STACK_SAVEAREA_MODE(LEVEL) \ |
337 | ((LEVEL) == SAVE_FUNCTION ? VOIDmode \ | |
338 | : (LEVEL) == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode) | |
862a2d83 | 339 | |
9db1d521 | 340 | |
862a2d83 | 341 | /* Type layout. */ |
9db1d521 | 342 | |
862a2d83 UW |
343 | /* Sizes in bits of the source language data types. */ |
344 | #define SHORT_TYPE_SIZE 16 | |
345 | #define INT_TYPE_SIZE 32 | |
346 | #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) | |
862a2d83 UW |
347 | #define LONG_LONG_TYPE_SIZE 64 |
348 | #define FLOAT_TYPE_SIZE 32 | |
349 | #define DOUBLE_TYPE_SIZE 64 | |
f61a2c7d AK |
350 | #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) |
351 | ||
f61a2c7d AK |
352 | /* Work around target_flags dependency in ada/targtyps.c. */ |
353 | #define WIDEST_HARDWARE_FP_SIZE 64 | |
862a2d83 UW |
354 | |
355 | /* We use "unsigned char" as default. */ | |
356 | #define DEFAULT_SIGNED_CHAR 0 | |
357 | ||
358 | ||
359 | /* Register usage. */ | |
360 | ||
361 | /* We have 16 general purpose registers (registers 0-15), | |
362 | and 16 floating point registers (registers 16-31). | |
363 | (On non-IEEE machines, we have only 4 fp registers.) | |
c7453384 | 364 | |
862a2d83 UW |
365 | Amongst the general purpose registers, some are used |
366 | for specific purposes: | |
367 | GPR 11: Hard frame pointer (if needed) | |
368 | GPR 12: Global offset table pointer (if needed) | |
369 | GPR 13: Literal pool base register | |
370 | GPR 14: Return address register | |
371 | GPR 15: Stack pointer | |
c7453384 | 372 | |
c5aa1d12 | 373 | Registers 32-35 are 'fake' hard registers that do not |
862a2d83 UW |
374 | correspond to actual hardware: |
375 | Reg 32: Argument pointer | |
376 | Reg 33: Condition code | |
f4aa3848 | 377 | Reg 34: Frame pointer |
c5aa1d12 | 378 | Reg 35: Return address pointer |
862a2d83 | 379 | |
f4aa3848 | 380 | Registers 36 and 37 are mapped to access registers |
085261c8 AK |
381 | 0 and 1, used to implement thread-local storage. |
382 | ||
383 | Reg 38-53: Vector registers v16-v31 */ | |
c5aa1d12 | 384 | |
085261c8 | 385 | #define FIRST_PSEUDO_REGISTER 54 |
862a2d83 UW |
386 | |
387 | /* Standard register usage. */ | |
8e509cf9 UW |
388 | #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16) |
389 | #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16) | |
142cd70f | 390 | #define FP_REGNO_P(N) ((N) >= 16 && (N) < 32) |
8e509cf9 | 391 | #define CC_REGNO_P(N) ((N) == 33) |
a38e09bc | 392 | #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34 || (N) == 35) |
c5aa1d12 | 393 | #define ACCESS_REGNO_P(N) ((N) == 36 || (N) == 37) |
085261c8 AK |
394 | #define VECTOR_NOFP_REGNO_P(N) ((N) >= 38 && (N) <= 53) |
395 | #define VECTOR_REGNO_P(N) (FP_REGNO_P (N) || VECTOR_NOFP_REGNO_P (N)) | |
8e509cf9 UW |
396 | |
397 | #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) | |
398 | #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X))) | |
399 | #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) | |
400 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) | |
4888ec5d | 401 | #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X))) |
c5aa1d12 | 402 | #define ACCESS_REG_P(X) (REG_P (X) && ACCESS_REGNO_P (REGNO (X))) |
085261c8 AK |
403 | #define VECTOR_NOFP_REG_P(X) (REG_P (X) && VECTOR_NOFP_REGNO_P (REGNO (X))) |
404 | #define VECTOR_REG_P(X) (REG_P (X) && VECTOR_REGNO_P (REGNO (X))) | |
9db1d521 | 405 | |
862a2d83 | 406 | /* Set up fixed registers and calling convention: |
9db1d521 | 407 | |
862a2d83 UW |
408 | GPRs 0-5 are always call-clobbered, |
409 | GPRs 6-15 are always call-saved. | |
410 | GPR 12 is fixed if used as GOT pointer. | |
411 | GPR 13 is always fixed (as literal pool pointer). | |
545d16ff | 412 | GPR 14 is always fixed on S/390 machines (as return address). |
862a2d83 UW |
413 | GPR 15 is always fixed (as stack pointer). |
414 | The 'fake' hard registers are call-clobbered and fixed. | |
c5aa1d12 | 415 | The access registers are call-saved and fixed. |
9db1d521 | 416 | |
862a2d83 UW |
417 | On 31-bit, FPRs 18-19 are call-clobbered; |
418 | on 64-bit, FPRs 24-31 are call-clobbered. | |
085261c8 AK |
419 | The remaining FPRs are call-saved. |
420 | ||
421 | All non-FP vector registers are call-clobbered v16-v31. */ | |
9db1d521 HP |
422 | |
423 | #define FIXED_REGISTERS \ | |
0ff3dcd6 AK |
424 | { 0, 0, 0, 0, \ |
425 | 0, 0, 0, 0, \ | |
426 | 0, 0, 0, 0, \ | |
9db1d521 | 427 | 0, 1, 1, 1, \ |
0ff3dcd6 AK |
428 | 0, 0, 0, 0, \ |
429 | 0, 0, 0, 0, \ | |
430 | 0, 0, 0, 0, \ | |
431 | 0, 0, 0, 0, \ | |
c5aa1d12 | 432 | 1, 1, 1, 1, \ |
085261c8 | 433 | 1, 1, \ |
0ff3dcd6 AK |
434 | 0, 0, 0, 0, \ |
435 | 0, 0, 0, 0, \ | |
436 | 0, 0, 0, 0, \ | |
085261c8 | 437 | 0, 0, 0, 0 } |
9db1d521 | 438 | |
9db1d521 | 439 | #define CALL_USED_REGISTERS \ |
0ff3dcd6 AK |
440 | { 1, 1, 1, 1, \ |
441 | 1, 1, 0, 0, \ | |
442 | 0, 0, 0, 0, \ | |
9db1d521 | 443 | 0, 1, 1, 1, \ |
c5aa1d12 | 444 | 1, 1, 1, 1, \ |
085261c8 | 445 | 1, 1, 1, 1, \ |
0ff3dcd6 AK |
446 | 1, 1, 1, 1, \ |
447 | 1, 1, 1, 1, \ | |
448 | 1, 1, 1, 1, \ | |
449 | 1, 1, \ | |
450 | 1, 1, 1, 1, \ | |
451 | 1, 1, 1, 1, \ | |
452 | 1, 1, 1, 1, \ | |
085261c8 | 453 | 1, 1, 1, 1 } |
4023fb28 | 454 | |
4023fb28 | 455 | #define CALL_REALLY_USED_REGISTERS \ |
0ff3dcd6 AK |
456 | { 1, 1, 1, 1, /* r0 - r15 */ \ |
457 | 1, 1, 0, 0, \ | |
458 | 0, 0, 0, 0, \ | |
4023fb28 | 459 | 0, 0, 0, 0, \ |
0ff3dcd6 AK |
460 | 1, 1, 1, 1, /* f0 (16) - f15 (31) */ \ |
461 | 1, 1, 1, 1, \ | |
462 | 1, 1, 1, 1, \ | |
463 | 1, 1, 1, 1, \ | |
085261c8 | 464 | 1, 1, 1, 1, /* arg, cc, fp, ret addr */ \ |
0ff3dcd6 AK |
465 | 0, 0, /* a0 (36), a1 (37) */ \ |
466 | 1, 1, 1, 1, /* v16 (38) - v23 (45) */ \ | |
c5aa1d12 | 467 | 1, 1, 1, 1, \ |
0ff3dcd6 | 468 | 1, 1, 1, 1, /* v24 (46) - v31 (53) */ \ |
085261c8 | 469 | 1, 1, 1, 1 } |
9db1d521 | 470 | |
862a2d83 | 471 | /* Preferred register allocation order. */ |
085261c8 AK |
472 | #define REG_ALLOC_ORDER \ |
473 | { 1, 2, 3, 4, 5, 0, 12, 11, 10, 9, 8, 7, 6, 14, 13, \ | |
474 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
475 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
0ff3dcd6 | 476 | 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, \ |
085261c8 | 477 | 15, 32, 33, 34, 35, 36, 37 } |
9db1d521 | 478 | |
9db1d521 | 479 | |
74aa8b4b | 480 | #define HARD_REGNO_RENAME_OK(FROM, TO) \ |
2d6744f4 | 481 | s390_hard_regno_rename_ok ((FROM), (TO)) |
7633f08e | 482 | |
862a2d83 UW |
483 | /* Maximum number of registers to represent a value of mode MODE |
484 | in a register of class CLASS. */ | |
0ff3dcd6 | 485 | #define CLASS_MAX_NREGS(CLASS, MODE) \ |
74aa8b4b | 486 | s390_class_max_nregs ((CLASS), (MODE)) |
4023fb28 | 487 | |
eca98038 AK |
488 | /* We can reverse a CC mode safely if we know whether it comes from a |
489 | floating point compare or not. With the vector modes it is encoded | |
490 | as part of the mode. | |
491 | FIXME: It might make sense to do this for other cc modes as well. */ | |
492 | #define REVERSIBLE_CC_MODE(MODE) \ | |
493 | ((MODE) == CCVIALLmode || (MODE) == CCVIANYmode \ | |
494 | || (MODE) == CCVFALLmode || (MODE) == CCVFANYmode) | |
495 | ||
496 | /* Given a condition code and a mode, return the inverse condition. */ | |
497 | #define REVERSE_CONDITION(CODE, MODE) s390_reverse_condition (MODE, CODE) | |
498 | ||
499 | ||
862a2d83 | 500 | /* Register classes. */ |
c7453384 | 501 | |
862a2d83 UW |
502 | /* We use the following register classes: |
503 | GENERAL_REGS All general purpose registers | |
504 | ADDR_REGS All general purpose registers except %r0 | |
0ff3dcd6 | 505 | (These registers can be used in address generation) |
862a2d83 | 506 | FP_REGS All floating point registers |
c5aa1d12 UW |
507 | CC_REGS The condition code register |
508 | ACCESS_REGS The access registers | |
c7453384 | 509 | |
862a2d83 UW |
510 | GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS |
511 | ADDR_FP_REGS Union of ADDR_REGS and FP_REGS | |
c5aa1d12 UW |
512 | GENERAL_CC_REGS Union of GENERAL_REGS and CC_REGS |
513 | ADDR_CC_REGS Union of ADDR_REGS and CC_REGS | |
c7453384 | 514 | |
862a2d83 UW |
515 | NO_REGS No registers |
516 | ALL_REGS All registers | |
c7453384 | 517 | |
862a2d83 | 518 | Note that the 'fake' frame pointer and argument pointer registers |
c5aa1d12 | 519 | are included amongst the address registers here. */ |
9db1d521 HP |
520 | |
521 | enum reg_class | |
522 | { | |
c5aa1d12 | 523 | NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS, |
f4aa3848 | 524 | ADDR_CC_REGS, GENERAL_CC_REGS, |
4023fb28 | 525 | FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, |
085261c8 | 526 | VEC_REGS, ADDR_VEC_REGS, GENERAL_VEC_REGS, |
4023fb28 | 527 | ALL_REGS, LIM_REG_CLASSES |
9db1d521 | 528 | }; |
9db1d521 HP |
529 | #define N_REG_CLASSES (int) LIM_REG_CLASSES |
530 | ||
c5aa1d12 UW |
531 | #define REG_CLASS_NAMES \ |
532 | { "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS", \ | |
533 | "ADDR_CC_REGS", "GENERAL_CC_REGS", \ | |
085261c8 AK |
534 | "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", \ |
535 | "VEC_REGS", "ADDR_VEC_REGS", "GENERAL_VEC_REGS", \ | |
536 | "ALL_REGS" } | |
9db1d521 | 537 | |
862a2d83 | 538 | /* Class -> register mapping. */ |
085261c8 AK |
539 | #define REG_CLASS_CONTENTS \ |
540 | { \ | |
9db1d521 | 541 | { 0x00000000, 0x00000000 }, /* NO_REGS */ \ |
9dc62c00 | 542 | { 0x00000000, 0x00000002 }, /* CC_REGS */ \ |
a38e09bc AK |
543 | { 0x0000fffe, 0x0000000d }, /* ADDR_REGS */ \ |
544 | { 0x0000ffff, 0x0000000d }, /* GENERAL_REGS */ \ | |
c5aa1d12 | 545 | { 0x00000000, 0x00000030 }, /* ACCESS_REGS */ \ |
9dc62c00 AK |
546 | { 0x0000fffe, 0x0000000f }, /* ADDR_CC_REGS */ \ |
547 | { 0x0000ffff, 0x0000000f }, /* GENERAL_CC_REGS */ \ | |
9db1d521 | 548 | { 0xffff0000, 0x00000000 }, /* FP_REGS */ \ |
a38e09bc AK |
549 | { 0xfffffffe, 0x0000000d }, /* ADDR_FP_REGS */ \ |
550 | { 0xffffffff, 0x0000000d }, /* GENERAL_FP_REGS */ \ | |
085261c8 AK |
551 | { 0xffff0000, 0x003fffc0 }, /* VEC_REGS */ \ |
552 | { 0xfffffffe, 0x003fffcd }, /* ADDR_VEC_REGS */ \ | |
553 | { 0xffffffff, 0x003fffcd }, /* GENERAL_VEC_REGS */ \ | |
554 | { 0xffffffff, 0x003fffff }, /* ALL_REGS */ \ | |
9db1d521 HP |
555 | } |
556 | ||
058e97ec VM |
557 | /* In some case register allocation order is not enough for IRA to |
558 | generate a good code. The following macro (if defined) increases | |
559 | cost of REGNO for a pseudo approximately by pseudo usage frequency | |
560 | multiplied by the macro value. | |
561 | ||
562 | We avoid usage of BASE_REGNUM by nonzero macro value because the | |
563 | reload can decide not to use the hard register because some | |
564 | constant was forced to be in memory. */ | |
565 | #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) \ | |
2d6744f4 | 566 | ((regno) != BASE_REGNUM ? 0.0 : 0.5) |
058e97ec | 567 | |
862a2d83 UW |
568 | /* Register -> class mapping. */ |
569 | extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; | |
570 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) | |
9db1d521 | 571 | |
862a2d83 UW |
572 | /* ADDR_REGS can be used as base or index register. */ |
573 | #define INDEX_REG_CLASS ADDR_REGS | |
574 | #define BASE_REG_CLASS ADDR_REGS | |
9db1d521 | 575 | |
862a2d83 UW |
576 | /* Check whether REGNO is a hard register of the suitable class |
577 | or a pseudo register currently allocated to one such. */ | |
578 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
0ff3dcd6 AK |
579 | (((REGNO) < FIRST_PSEUDO_REGISTER \ |
580 | && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \ | |
93fa8428 | 581 | || ADDR_REGNO_P (reg_renumber[REGNO])) |
862a2d83 | 582 | #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) |
9db1d521 | 583 | |
9db1d521 | 584 | |
862a2d83 | 585 | /* Stack layout and calling conventions. */ |
c7453384 | 586 | |
862a2d83 UW |
587 | /* Our stack grows from higher to lower addresses. However, local variables |
588 | are accessed by positive offsets, and function arguments are stored at | |
589 | increasing addresses. */ | |
62f9f30b | 590 | #define STACK_GROWS_DOWNWARD 1 |
63296cb1 | 591 | #define FRAME_GROWS_DOWNWARD 1 |
862a2d83 | 592 | /* #undef ARGS_GROW_DOWNWARD */ |
9db1d521 | 593 | |
862a2d83 UW |
594 | /* The basic stack layout looks like this: the stack pointer points |
595 | to the register save area for called functions. Above that area | |
596 | is the location to place outgoing arguments. Above those follow | |
597 | dynamic allocations (alloca), and finally the local variables. */ | |
9db1d521 | 598 | |
862a2d83 UW |
599 | /* Offset from stack-pointer to first location of outgoing args. */ |
600 | #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96) | |
9db1d521 | 601 | |
862a2d83 UW |
602 | /* Offset from the stack pointer register to an item dynamically |
603 | allocated on the stack, e.g., by `alloca'. */ | |
63296cb1 | 604 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ |
38173d38 | 605 | (STACK_POINTER_OFFSET + crtl->outgoing_args_size) |
9db1d521 | 606 | |
862a2d83 UW |
607 | /* Offset of first parameter from the argument pointer register value. |
608 | We have a fake argument pointer register that points directly to | |
609 | the argument area. */ | |
610 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
9db1d521 | 611 | |
f4aa3848 | 612 | /* Defining this macro makes __builtin_frame_address(0) and |
c6d01079 AK |
613 | __builtin_return_address(0) work with -fomit-frame-pointer. */ |
614 | #define INITIAL_FRAME_ADDRESS_RTX \ | |
0a81f074 | 615 | (plus_constant (Pmode, arg_pointer_rtx, -STACK_POINTER_OFFSET)) |
c6d01079 | 616 | |
c7453384 | 617 | /* The return address of the current frame is retrieved |
4023fb28 UW |
618 | from the initial value of register RETURN_REGNUM. |
619 | For frames farther back, we use the stack slot where | |
620 | the corresponding RETURN_REGNUM register was saved. */ | |
c6d01079 AK |
621 | #define DYNAMIC_CHAIN_ADDRESS(FRAME) \ |
622 | (TARGET_PACKED_STACK ? \ | |
0a81f074 RS |
623 | plus_constant (Pmode, (FRAME), \ |
624 | STACK_POINTER_OFFSET - UNITS_PER_LONG) : (FRAME)) | |
4023fb28 | 625 | |
78791a80 AK |
626 | /* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of |
627 | builtin_frame_address. Otherwise arg pointer - | |
628 | STACK_POINTER_OFFSET would be returned for | |
629 | __builtin_frame_address(0) what might result in an address pointing | |
630 | somewhere into the middle of the local variables since the packed | |
631 | stack layout generally does not need all the bytes in the register | |
632 | save area. */ | |
633 | #define FRAME_ADDR_RTX(FRAME) \ | |
634 | DYNAMIC_CHAIN_ADDRESS ((FRAME)) | |
635 | ||
c6d01079 | 636 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
5d4d885c | 637 | s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME))) |
9db1d521 | 638 | |
862a2d83 | 639 | /* In 31-bit mode, we need to mask off the high bit of return addresses. */ |
a556fd39 | 640 | #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff)) |
9db1d521 | 641 | |
4023fb28 | 642 | |
862a2d83 | 643 | /* Exception handling. */ |
c7453384 | 644 | |
862a2d83 UW |
645 | /* Describe calling conventions for DWARF-2 exception handling. */ |
646 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM) | |
4023fb28 | 647 | #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET |
9db1d521 HP |
648 | #define DWARF_FRAME_RETURN_COLUMN 14 |
649 | ||
650 | /* Describe how we implement __builtin_eh_return. */ | |
651 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM) | |
a38e09bc | 652 | #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx) |
f4aa3848 | 653 | |
18789f4e UW |
654 | /* Select a format to encode pointers in exception handling data. */ |
655 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
656 | (flag_pic \ | |
657 | ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ | |
658 | : DW_EH_PE_absptr) | |
659 | ||
9602b6a1 AK |
660 | /* Register save slot alignment. */ |
661 | #define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_LONG) | |
662 | ||
f276b762 AK |
663 | /* Let the assembler generate debug line info. */ |
664 | #define DWARF2_ASM_LINE_DEBUG_INFO 1 | |
665 | ||
085261c8 AK |
666 | /* Define the dwarf register mapping. |
667 | v16-v31 -> 68-83 | |
668 | rX -> X otherwise */ | |
2d6744f4 AK |
669 | #define DBX_REGISTER_NUMBER(regno) \ |
670 | (((regno) >= 38 && (regno) <= 53) ? (regno) + 30 : (regno)) | |
9db1d521 | 671 | |
862a2d83 | 672 | /* Frame registers. */ |
9db1d521 | 673 | |
862a2d83 UW |
674 | #define STACK_POINTER_REGNUM 15 |
675 | #define FRAME_POINTER_REGNUM 34 | |
676 | #define HARD_FRAME_POINTER_REGNUM 11 | |
677 | #define ARG_POINTER_REGNUM 32 | |
a38e09bc | 678 | #define RETURN_ADDRESS_POINTER_REGNUM 35 |
9db1d521 | 679 | |
c7453384 EC |
680 | /* The static chain must be call-clobbered, but not used for |
681 | function argument passing. As register 1 is clobbered by | |
862a2d83 UW |
682 | the trampoline code, we only have one option. */ |
683 | #define STATIC_CHAIN_REGNUM 0 | |
9db1d521 | 684 | |
862a2d83 UW |
685 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
686 | To avoid ABI incompatibility, this number must not change even as | |
687 | 'fake' hard registers are added or removed. */ | |
688 | #define DWARF_FRAME_REGISTERS 34 | |
9db1d521 | 689 | |
9db1d521 | 690 | |
862a2d83 | 691 | /* Frame pointer and argument pointer elimination. */ |
9db1d521 | 692 | |
7633f08e UW |
693 | #define ELIMINABLE_REGS \ |
694 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
695 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
696 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
697 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
698 | { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
699 | { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
700 | { BASE_REGNUM, BASE_REGNUM }} | |
9db1d521 | 701 | |
91086990 UW |
702 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
703 | (OFFSET) = s390_initial_elimination_offset ((FROM), (TO)) | |
9db1d521 | 704 | |
9db1d521 | 705 | |
862a2d83 | 706 | /* Stack arguments. */ |
c7453384 | 707 | |
862a2d83 UW |
708 | /* We need current_function_outgoing_args to be valid. */ |
709 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
9db1d521 | 710 | |
9db1d521 | 711 | |
862a2d83 | 712 | /* Register arguments. */ |
c7453384 | 713 | |
9db1d521 HP |
714 | typedef struct s390_arg_structure |
715 | { | |
716 | int gprs; /* gpr so far */ | |
717 | int fprs; /* fpr so far */ | |
085261c8 | 718 | int vrs; /* vr so far */ |
9db1d521 HP |
719 | } |
720 | CUMULATIVE_ARGS; | |
721 | ||
07711f53 | 722 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \ |
085261c8 AK |
723 | ((CUM).gprs=0, (CUM).fprs=0, (CUM).vrs=0) |
724 | ||
725 | #define FIRST_VEC_ARG_REGNO 46 | |
726 | #define LAST_VEC_ARG_REGNO 53 | |
9db1d521 | 727 | |
96e2afa8 AK |
728 | /* Arguments can be placed in general registers 2 to 6, or in floating |
729 | point registers 0 and 2 for 31 bit and fprs 0, 2, 4 and 6 for 64 | |
730 | bit. */ | |
085261c8 AK |
731 | #define FUNCTION_ARG_REGNO_P(N) \ |
732 | (((N) >=2 && (N) < 7) || (N) == 16 || (N) == 17 \ | |
733 | || (TARGET_64BIT && ((N) == 18 || (N) == 19)) \ | |
734 | || (TARGET_VX && ((N) >= FIRST_VEC_ARG_REGNO && (N) <= LAST_VEC_ARG_REGNO))) | |
9db1d521 | 735 | |
9db1d521 | 736 | |
085261c8 AK |
737 | /* Only gpr 2, fpr 0, and v24 are ever used as return registers. */ |
738 | #define FUNCTION_VALUE_REGNO_P(N) \ | |
739 | ((N) == 2 || (N) == 16 \ | |
740 | || (TARGET_VX && (N) == FIRST_VEC_ARG_REGNO)) | |
9db1d521 | 741 | |
9db1d521 | 742 | |
862a2d83 | 743 | /* Function entry and exit. */ |
c7453384 | 744 | |
862a2d83 UW |
745 | /* When returning from a function, the stack pointer does not matter. */ |
746 | #define EXIT_IGNORE_STACK 1 | |
9db1d521 | 747 | |
9db1d521 | 748 | |
862a2d83 | 749 | /* Profiling. */ |
9db1d521 | 750 | |
0ff3dcd6 | 751 | #define FUNCTION_PROFILER(FILE, LABELNO) \ |
862a2d83 | 752 | s390_function_profiler ((FILE), ((LABELNO))) |
9db1d521 | 753 | |
c52a375d | 754 | #define PROFILE_BEFORE_PROLOGUE 1 |
9db1d521 | 755 | |
9db1d521 | 756 | |
862a2d83 | 757 | /* Trampolines for nested functions. */ |
9db1d521 | 758 | |
b81ecf6f RH |
759 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 32 : 16) |
760 | #define TRAMPOLINE_ALIGNMENT BITS_PER_WORD | |
9db1d521 | 761 | |
862a2d83 | 762 | /* Addressing modes, and classification of registers for them. */ |
9db1d521 | 763 | |
862a2d83 UW |
764 | /* Recognize any constant value that is a valid address. */ |
765 | #define CONSTANT_ADDRESS_P(X) 0 | |
9db1d521 | 766 | |
862a2d83 UW |
767 | /* Maximum number of registers that can appear in a valid memory address. */ |
768 | #define MAX_REGS_PER_ADDRESS 2 | |
9db1d521 | 769 | |
963fc8d0 | 770 | /* This definition replaces the formerly used 'm' constraint with a |
c6c3dba9 PB |
771 | different constraint letter in order to avoid changing semantics of |
772 | the 'm' constraint when accepting new address formats in | |
773 | TARGET_LEGITIMATE_ADDRESS_P. The constraint letter defined here | |
774 | must not be used in insn definitions or inline assemblies. */ | |
963fc8d0 AK |
775 | #define TARGET_MEM_CONSTRAINT 'e' |
776 | ||
0b540f12 UW |
777 | /* Try a machine-dependent way of reloading an illegitimate address |
778 | operand. If we find one, push the reload and jump to WIN. This | |
779 | macro is used in only one place: `find_reloads_address' in reload.c. */ | |
780 | #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ | |
2d6744f4 AK |
781 | do { \ |
782 | rtx new_rtx = legitimize_reload_address ((AD), (MODE), \ | |
783 | (OPNUM), (int)(TYPE)); \ | |
784 | if (new_rtx) \ | |
785 | { \ | |
786 | (AD) = new_rtx; \ | |
787 | goto WIN; \ | |
788 | } \ | |
789 | } while (0) | |
0b540f12 | 790 | |
862a2d83 | 791 | /* Helper macro for s390.c and s390.md to check for symbolic constants. */ |
2d6744f4 AK |
792 | #define SYMBOLIC_CONST(X) \ |
793 | (GET_CODE (X) == SYMBOL_REF \ | |
794 | || GET_CODE (X) == LABEL_REF \ | |
795 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
9db1d521 | 796 | |
2d6744f4 AK |
797 | #define TLS_SYMBOLIC_CONST(X) \ |
798 | ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \ | |
799 | || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X))) | |
fd3cd001 | 800 | |
9db1d521 | 801 | |
862a2d83 | 802 | /* Condition codes. */ |
9db1d521 | 803 | |
862a2d83 UW |
804 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
805 | return the mode to be used for the comparison. */ | |
806 | #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y)) | |
c7453384 | 807 | |
862a2d83 | 808 | /* Relative costs of operations. */ |
9db1d521 | 809 | |
9db1d521 HP |
810 | /* A C expression for the cost of a branch instruction. A value of 1 |
811 | is the default; other values are interpreted relative to that. */ | |
3d427cc1 | 812 | #define BRANCH_COST(speed_p, predictable_p) s390_branch_cost |
9db1d521 | 813 | |
862a2d83 UW |
814 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
815 | #define SLOW_BYTE_ACCESS 1 | |
816 | ||
c5443745 | 817 | /* An integer expression for the size in bits of the largest integer machine |
f4aa3848 | 818 | mode that should actually be used. We allow pairs of registers. */ |
c5443745 UW |
819 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) |
820 | ||
862a2d83 | 821 | /* The maximum number of bytes that a single instruction can move quickly |
ff482c8d | 822 | between memory and registers or between two memory locations. */ |
9602b6a1 AK |
823 | #define MOVE_MAX (TARGET_ZARCH ? 16 : 8) |
824 | #define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4) | |
862a2d83 | 825 | #define MAX_MOVE_MAX 16 |
9db1d521 | 826 | |
862a2d83 | 827 | /* Don't perform CSE on function addresses. */ |
1e8552c2 | 828 | #define NO_FUNCTION_CSE 1 |
862a2d83 | 829 | |
5f1b2ee6 AK |
830 | /* This value is used in tree-sra to decide whether it might benefical |
831 | to split a struct move into several word-size moves. For S/390 | |
832 | only small values make sense here since struct moves are relatively | |
073a8998 | 833 | cheap thanks to mvc so the small default value chosen for archs |
5f1b2ee6 AK |
834 | with memmove patterns should be ok. But this value is multiplied |
835 | in tree-sra with UNITS_PER_WORD to make a decision so we adjust it | |
836 | here to compensate for that factor since mvc costs exactly the same | |
837 | on 31 and 64 bit. */ | |
e04ad03d | 838 | #define MOVE_RATIO(speed) (TARGET_64BIT? 2 : 4) |
5f1b2ee6 | 839 | |
862a2d83 UW |
840 | |
841 | /* Sections. */ | |
842 | ||
843 | /* Output before read-only data. */ | |
844 | #define TEXT_SECTION_ASM_OP ".text" | |
845 | ||
846 | /* Output before writable (initialized) data. */ | |
847 | #define DATA_SECTION_ASM_OP ".data" | |
848 | ||
849 | /* Output before writable (uninitialized) data. */ | |
850 | #define BSS_SECTION_ASM_OP ".bss" | |
851 | ||
852 | /* S/390 constant pool breaks the devices in crtstuff.c to control section | |
853 | in where code resides. We have to write it as asm code. */ | |
854 | #ifndef __s390x__ | |
855 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
856 | asm (SECTION_OP "\n\ | |
857 | bras\t%r2,1f\n\ | |
858 | 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\ | |
859 | 1: l\t%r3,0(%r2)\n\ | |
860 | bas\t%r14,0(%r3,%r2)\n\ | |
861 | .previous"); | |
862 | #endif | |
63a1ff86 | 863 | |
862a2d83 UW |
864 | |
865 | /* Position independent code. */ | |
866 | ||
862a2d83 UW |
867 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM) |
868 | ||
869 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) | |
63a1ff86 | 870 | |
935b5226 AK |
871 | #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE |
872 | #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 | |
873 | #endif | |
874 | ||
63a1ff86 UW |
875 | |
876 | /* Assembler file format. */ | |
877 | ||
878 | /* Character to start a comment. */ | |
879 | #define ASM_COMMENT_START "#" | |
880 | ||
881 | /* Declare an uninitialized external linkage data object. */ | |
2d6744f4 AK |
882 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ |
883 | asm_output_aligned_bss ((FILE), (DECL), (NAME), (SIZE), (ALIGN)) | |
63a1ff86 UW |
884 | |
885 | /* Globalizing directive for a label. */ | |
886 | #define GLOBAL_ASM_OP ".globl " | |
887 | ||
888 | /* Advance the location counter to a multiple of 2**LOG bytes. */ | |
889 | #define ASM_OUTPUT_ALIGN(FILE, LOG) \ | |
890 | if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG)) | |
891 | ||
892 | /* Advance the location counter by SIZE bytes. */ | |
893 | #define ASM_OUTPUT_SKIP(FILE, SIZE) \ | |
16998094 | 894 | fprintf ((FILE), "\t.set\t.,.+" HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) |
63a1ff86 | 895 | |
63a1ff86 UW |
896 | /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */ |
897 | #define LOCAL_LABEL_PREFIX "." | |
9db1d521 | 898 | |
5d304e47 | 899 | #define LABEL_ALIGN(LABEL) \ |
2d6744f4 | 900 | s390_label_align ((LABEL)) |
5d304e47 | 901 | |
9db1d521 HP |
902 | /* How to refer to registers in assembler output. This sequence is |
903 | indexed by compiler's hard-register-number (see above). */ | |
9db1d521 | 904 | #define REGISTER_NAMES \ |
085261c8 AK |
905 | { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ |
906 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ | |
907 | "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \ | |
908 | "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \ | |
909 | "%ap", "%cc", "%fp", "%rp", "%a0", "%a1", \ | |
910 | "%v16", "%v18", "%v20", "%v22", "%v17", "%v19", "%v21", "%v23", \ | |
911 | "%v24", "%v26", "%v28", "%v30", "%v25", "%v27", "%v29", "%v31" \ | |
912 | } | |
913 | ||
914 | #define ADDITIONAL_REGISTER_NAMES \ | |
915 | { { "v0", 16 }, { "v2", 17 }, { "v4", 18 }, { "v6", 19 }, \ | |
916 | { "v1", 20 }, { "v3", 21 }, { "v5", 22 }, { "v7", 23 }, \ | |
917 | { "v8", 24 }, { "v10", 25 }, { "v12", 26 }, { "v14", 27 }, \ | |
918 | { "v9", 28 }, { "v11", 29 }, { "v13", 30 }, { "v15", 31 } }; | |
9db1d521 | 919 | |
63a1ff86 | 920 | /* Print operand X (an rtx) in assembler syntax to file FILE. */ |
2d6744f4 AK |
921 | #define PRINT_OPERAND(FILE, X, CODE) print_operand ((FILE), (X), (CODE)) |
922 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address ((FILE), (ADDR)) | |
9db1d521 | 923 | |
63a1ff86 UW |
924 | /* Output an element of a case-vector that is absolute. */ |
925 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
926 | do { \ | |
927 | char buf[32]; \ | |
9602b6a1 | 928 | fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ |
63a1ff86 UW |
929 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ |
930 | assemble_name ((FILE), buf); \ | |
931 | fputc ('\n', (FILE)); \ | |
932 | } while (0) | |
933 | ||
934 | /* Output an element of a case-vector that is relative. */ | |
935 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
936 | do { \ | |
937 | char buf[32]; \ | |
9602b6a1 | 938 | fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ |
63a1ff86 UW |
939 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ |
940 | assemble_name ((FILE), buf); \ | |
941 | fputc ('-', (FILE)); \ | |
942 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \ | |
943 | assemble_name ((FILE), buf); \ | |
944 | fputc ('\n', (FILE)); \ | |
945 | } while (0) | |
946 | ||
177bc204 RS |
947 | /* Mark the return register as used by the epilogue so that we can |
948 | use it in unadorned (return) and (simple_return) instructions. */ | |
949 | #define EPILOGUE_USES(REGNO) ((REGNO) == RETURN_REGNUM) | |
950 | ||
d0de9e13 | 951 | #undef ASM_OUTPUT_FUNCTION_LABEL |
2d6744f4 AK |
952 | #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ |
953 | s390_asm_output_function_label ((FILE), (NAME), (DECL)) | |
9db1d521 | 954 | |
ec47b086 DV |
955 | #if S390_USE_TARGET_ATTRIBUTE |
956 | /* Hook to output .machine and .machinemode at start of function. */ | |
957 | #undef ASM_OUTPUT_FUNCTION_PREFIX | |
958 | #define ASM_OUTPUT_FUNCTION_PREFIX s390_asm_output_function_prefix | |
959 | ||
960 | /* Hook to output .machine and .machinemode at end of function. */ | |
961 | #undef ASM_DECLARE_FUNCTION_SIZE | |
962 | #define ASM_DECLARE_FUNCTION_SIZE s390_asm_declare_function_size | |
963 | #endif | |
964 | ||
862a2d83 UW |
965 | /* Miscellaneous parameters. */ |
966 | ||
862a2d83 UW |
967 | /* Specify the machine mode that this machine uses for the index in the |
968 | tablejump instruction. */ | |
969 | #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) | |
970 | ||
862a2d83 UW |
971 | /* Specify the machine mode that pointers have. |
972 | After generation of rtl, the compiler makes no further distinction | |
973 | between pointers and any other objects of this machine mode. */ | |
501623d4 | 974 | #define Pmode (TARGET_64BIT ? DImode : SImode) |
862a2d83 | 975 | |
c7453384 EC |
976 | /* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */ |
977 | #define POINTERS_EXTEND_UNSIGNED -1 | |
978 | ||
862a2d83 UW |
979 | /* A function address in a call instruction is a byte address (for |
980 | indexing purposes) so give the MEM rtx a byte's mode. */ | |
981 | #define FUNCTION_MODE QImode | |
982 | ||
ec24698e UW |
983 | /* Specify the value which is used when clz operand is zero. */ |
984 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1) | |
985 | ||
0bfc3f69 | 986 | /* Machine-specific symbol_ref flags. */ |
e63d44c2 RD |
987 | #define SYMBOL_FLAG_ALIGN_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT |
988 | #define SYMBOL_FLAG_ALIGN_MASK \ | |
989 | ((SYMBOL_FLAG_MACH_DEP << 0) | (SYMBOL_FLAG_MACH_DEP << 1)) | |
990 | ||
991 | #define SYMBOL_FLAG_SET_ALIGN(X, A) \ | |
992 | (SYMBOL_REF_FLAGS (X) = (SYMBOL_REF_FLAGS (X) & ~SYMBOL_FLAG_ALIGN_MASK) \ | |
993 | | (A << SYMBOL_FLAG_ALIGN_SHIFT)) | |
994 | ||
995 | #define SYMBOL_FLAG_GET_ALIGN(X) \ | |
996 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN_MASK) >> SYMBOL_FLAG_ALIGN_SHIFT) | |
997 | ||
998 | /* Helpers to access symbol_ref flags. They are used in | |
999 | check_symref_alignment() and larl_operand to detect if the | |
1000 | available alignment matches the required one. We do not use | |
1001 | a positive check like _ALIGN2 because in that case we would have | |
1002 | to annotate every symbol_ref. However, we only want to touch | |
1003 | the symbol_refs that can be misaligned and assume that the others | |
1004 | are correctly aligned. Hence, if a symbol_ref does not have | |
1005 | a _NOTALIGN flag it is supposed to be correctly aligned. */ | |
2d6744f4 AK |
1006 | #define SYMBOL_FLAG_SET_NOTALIGN2(X) SYMBOL_FLAG_SET_ALIGN((X), 1) |
1007 | #define SYMBOL_FLAG_SET_NOTALIGN4(X) SYMBOL_FLAG_SET_ALIGN((X), 2) | |
1008 | #define SYMBOL_FLAG_SET_NOTALIGN8(X) SYMBOL_FLAG_SET_ALIGN((X), 3) | |
e63d44c2 RD |
1009 | |
1010 | #define SYMBOL_FLAG_NOTALIGN2_P(X) (SYMBOL_FLAG_GET_ALIGN(X) == 1) | |
2d6744f4 | 1011 | #define SYMBOL_FLAG_NOTALIGN4_P(X) (SYMBOL_FLAG_GET_ALIGN(X) == 2 \ |
e63d44c2 | 1012 | || SYMBOL_FLAG_GET_ALIGN(X) == 1) |
2d6744f4 AK |
1013 | #define SYMBOL_FLAG_NOTALIGN8_P(X) (SYMBOL_FLAG_GET_ALIGN(X) == 3 \ |
1014 | || SYMBOL_FLAG_GET_ALIGN(X) == 2 \ | |
e63d44c2 | 1015 | || SYMBOL_FLAG_GET_ALIGN(X) == 1) |
0bfc3f69 | 1016 | |
085261c8 AK |
1017 | /* Check whether integer displacement is in range for a short displacement. */ |
1018 | #define SHORT_DISP_IN_RANGE(d) ((d) >= 0 && (d) <= 4095) | |
1019 | ||
0bfc3f69 | 1020 | /* Check whether integer displacement is in range. */ |
2d6744f4 AK |
1021 | #define DISP_IN_RANGE(d) \ |
1022 | (TARGET_LONG_DISPLACEMENT \ | |
1023 | ? ((d) >= -524288 && (d) <= 524287) \ | |
1024 | : SHORT_DISP_IN_RANGE(d)) | |
0bfc3f69 | 1025 | |
24a235c8 CB |
1026 | /* Reads can reuse write prefetches, used by tree-ssa-prefetch-loops.c. */ |
1027 | #define READ_CAN_USE_WRITE_PREFETCH 1 | |
677f3fa8 JM |
1028 | |
1029 | extern const int processor_flags_table[]; | |
085261c8 | 1030 | |
52d4aa4f IL |
1031 | struct s390_processor |
1032 | { | |
1033 | /* The preferred name to be used in user visible output. */ | |
1034 | const char *const name; | |
1035 | /* CPU name as it should be passed to Binutils via .machine */ | |
1036 | const char *const binutils_name; | |
1037 | const enum processor_type processor; | |
1038 | const struct processor_costs *cost; | |
1039 | int arch_level; | |
1040 | }; | |
1041 | ||
1042 | extern const struct s390_processor processor_table[]; | |
1043 | ||
085261c8 AK |
1044 | /* The truth element value for vector comparisons. Our instructions |
1045 | always generate -1 in that case. */ | |
1046 | #define VECTOR_STORE_FLAG_VALUE(MODE) CONSTM1_RTX (GET_MODE_INNER (MODE)) | |
1047 | ||
3af82a61 AK |
1048 | /* Target pragma. */ |
1049 | ||
1050 | /* resolve_overloaded_builtin can not be defined the normal way since | |
1051 | it is defined in code which technically belongs to the | |
1052 | front-end. */ | |
1053 | #define REGISTER_TARGET_PRAGMAS() \ | |
1054 | do { \ | |
1055 | s390_register_target_pragmas (); \ | |
1056 | } while (0) | |
1057 | ||
84b4c7b5 AK |
1058 | #ifndef USED_FOR_TARGET |
1059 | /* The following structure is embedded in the machine | |
1060 | specific part of struct function. */ | |
1061 | ||
1062 | struct GTY (()) s390_frame_layout | |
1063 | { | |
1064 | /* Offset within stack frame. */ | |
1065 | HOST_WIDE_INT gprs_offset; | |
1066 | HOST_WIDE_INT f0_offset; | |
1067 | HOST_WIDE_INT f4_offset; | |
1068 | HOST_WIDE_INT f8_offset; | |
1069 | HOST_WIDE_INT backchain_offset; | |
1070 | ||
1071 | /* Number of first and last gpr where slots in the register | |
1072 | save area are reserved for. */ | |
1073 | int first_save_gpr_slot; | |
1074 | int last_save_gpr_slot; | |
1075 | ||
1076 | /* Location (FP register number) where GPRs (r0-r15) should | |
1077 | be saved to. | |
1078 | 0 - does not need to be saved at all | |
1079 | -1 - stack slot */ | |
1080 | #define SAVE_SLOT_NONE 0 | |
1081 | #define SAVE_SLOT_STACK -1 | |
1082 | signed char gpr_save_slots[16]; | |
1083 | ||
1084 | /* Number of first and last gpr to be saved, restored. */ | |
1085 | int first_save_gpr; | |
1086 | int first_restore_gpr; | |
1087 | int last_save_gpr; | |
1088 | int last_restore_gpr; | |
1089 | ||
1090 | /* Bits standing for floating point registers. Set, if the | |
1091 | respective register has to be saved. Starting with reg 16 (f0) | |
1092 | at the rightmost bit. | |
1093 | Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | |
1094 | fpr 15 13 11 9 14 12 10 8 7 5 3 1 6 4 2 0 | |
1095 | reg 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 */ | |
1096 | unsigned int fpr_bitmap; | |
1097 | ||
1098 | /* Number of floating point registers f8-f15 which must be saved. */ | |
1099 | int high_fprs; | |
1100 | ||
1101 | /* Set if return address needs to be saved. | |
1102 | This flag is set by s390_return_addr_rtx if it could not use | |
1103 | the initial value of r14 and therefore depends on r14 saved | |
1104 | to the stack. */ | |
1105 | bool save_return_addr_p; | |
1106 | ||
1107 | /* Size of stack frame. */ | |
1108 | HOST_WIDE_INT frame_size; | |
1109 | }; | |
1110 | ||
1111 | ||
1112 | /* Define the structure for the machine field in struct function. */ | |
1113 | ||
1114 | struct GTY(()) machine_function | |
1115 | { | |
1116 | struct s390_frame_layout frame_layout; | |
1117 | ||
1118 | /* Literal pool base register. */ | |
1119 | rtx base_reg; | |
1120 | ||
84b4c7b5 AK |
1121 | bool has_landing_pad_p; |
1122 | ||
1123 | /* True if the current function may contain a tbegin clobbering | |
1124 | FPRs. */ | |
1125 | bool tbegin_p; | |
1126 | ||
1127 | /* For -fsplit-stack support: A stack local which holds a pointer to | |
1128 | the stack arguments for a function with a variable number of | |
1129 | arguments. This is set at the start of the function and is used | |
1130 | to initialize the overflow_arg_area field of the va_list | |
1131 | structure. */ | |
1132 | rtx split_stack_varargs_pointer; | |
1133 | ||
1134 | enum indirect_branch indirect_branch_jump; | |
1135 | enum indirect_branch indirect_branch_call; | |
1136 | ||
1137 | enum indirect_branch function_return_mem; | |
1138 | enum indirect_branch function_return_reg; | |
1139 | }; | |
1140 | #endif | |
1141 | ||
1142 | #define TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION \ | |
1143 | (cfun->machine->function_return_reg != indirect_branch_keep \ | |
1144 | || cfun->machine->function_return_mem != indirect_branch_keep) | |
1145 | ||
1146 | #define TARGET_INDIRECT_BRANCH_NOBP_RET \ | |
1147 | ((cfun->machine->function_return_reg != indirect_branch_keep \ | |
1148 | && !s390_return_addr_from_memory ()) \ | |
1149 | || (cfun->machine->function_return_mem != indirect_branch_keep \ | |
1150 | && s390_return_addr_from_memory ())) | |
1151 | ||
1152 | #define TARGET_INDIRECT_BRANCH_NOBP_JUMP \ | |
1153 | (cfun->machine->indirect_branch_jump != indirect_branch_keep) | |
1154 | ||
1155 | #define TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK \ | |
1156 | (cfun->machine->indirect_branch_jump == indirect_branch_thunk \ | |
1157 | || cfun->machine->indirect_branch_jump == indirect_branch_thunk_extern) | |
1158 | ||
1159 | #define TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK \ | |
1160 | (cfun->machine->indirect_branch_jump == indirect_branch_thunk_inline) | |
1161 | ||
1162 | #define TARGET_INDIRECT_BRANCH_NOBP_CALL \ | |
1163 | (cfun->machine->indirect_branch_call != indirect_branch_keep) | |
1164 | ||
1165 | #ifndef TARGET_DEFAULT_INDIRECT_BRANCH_TABLE | |
1166 | #define TARGET_DEFAULT_INDIRECT_BRANCH_TABLE 0 | |
1167 | #endif | |
1168 | ||
1169 | #define TARGET_INDIRECT_BRANCH_THUNK_NAME_EXRL "__s390_indirect_jump_r%d" | |
1170 | #define TARGET_INDIRECT_BRANCH_THUNK_NAME_EX "__s390_indirect_jump_r%duse_r%d" | |
1171 | ||
1172 | #define TARGET_INDIRECT_BRANCH_TABLE s390_indirect_branch_table | |
1173 | ||
1174 | ||
085261c8 | 1175 | #endif /* S390_H */ |