]>
Commit | Line | Data |
---|---|---|
9db1d521 | 1 | /* Definitions of target machine for GNU compiler, for IBM S/390 |
2f83c7d6 | 2 | Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, |
0f8ab434 | 3 | 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. |
9db1d521 | 4 | Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
f314b9b1 | 5 | Ulrich Weigand (uweigand@de.ibm.com). |
963fc8d0 | 6 | Andreas Krebbel (Andreas.Krebbel@de.ibm.com) |
9db1d521 | 7 | |
58add37a | 8 | This file is part of GCC. |
9db1d521 | 9 | |
58add37a UW |
10 | GCC is free software; you can redistribute it and/or modify it under |
11 | the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 12 | Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
13 | version. |
14 | ||
15 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
16 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
17 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
18 | for more details. | |
9db1d521 HP |
19 | |
20 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
21 | along with GCC; see the file COPYING3. If not see |
22 | <http://www.gnu.org/licenses/>. */ | |
9db1d521 HP |
23 | |
24 | #ifndef _S390_H | |
25 | #define _S390_H | |
26 | ||
f13e0d4e UW |
27 | /* Optional architectural facilities supported by the processor. */ |
28 | ||
29 | enum processor_flags | |
30 | { | |
31 | PF_IEEE_FLOAT = 1, | |
32 | PF_ZARCH = 2, | |
ec24698e | 33 | PF_LONG_DISPLACEMENT = 4, |
85dae55a | 34 | PF_EXTIMM = 8, |
93538e8e | 35 | PF_DFP = 16, |
65b1d8ea AK |
36 | PF_Z10 = 32, |
37 | PF_Z196 = 64 | |
f13e0d4e UW |
38 | }; |
39 | ||
90c6fd8a AK |
40 | /* This is necessary to avoid a warning about comparing different enum |
41 | types. */ | |
42 | #define s390_tune_attr ((enum attr_cpu)s390_tune) | |
43 | ||
963fc8d0 AK |
44 | /* These flags indicate that the generated code should run on a cpu |
45 | providing the respective hardware facility regardless of the | |
46 | current cpu mode (ESA or z/Architecture). */ | |
47 | ||
f13e0d4e UW |
48 | #define TARGET_CPU_IEEE_FLOAT \ |
49 | (s390_arch_flags & PF_IEEE_FLOAT) | |
50 | #define TARGET_CPU_ZARCH \ | |
51 | (s390_arch_flags & PF_ZARCH) | |
52 | #define TARGET_CPU_LONG_DISPLACEMENT \ | |
53 | (s390_arch_flags & PF_LONG_DISPLACEMENT) | |
ec24698e UW |
54 | #define TARGET_CPU_EXTIMM \ |
55 | (s390_arch_flags & PF_EXTIMM) | |
85dae55a AK |
56 | #define TARGET_CPU_DFP \ |
57 | (s390_arch_flags & PF_DFP) | |
93538e8e AK |
58 | #define TARGET_CPU_Z10 \ |
59 | (s390_arch_flags & PF_Z10) | |
65b1d8ea AK |
60 | #define TARGET_CPU_Z196 \ |
61 | (s390_arch_flags & PF_Z196) | |
f13e0d4e | 62 | |
963fc8d0 AK |
63 | /* These flags indicate that the generated code should run on a cpu |
64 | providing the respective hardware facility when run in | |
65 | z/Architecture mode. */ | |
66 | ||
f13e0d4e UW |
67 | #define TARGET_LONG_DISPLACEMENT \ |
68 | (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT) | |
ec24698e UW |
69 | #define TARGET_EXTIMM \ |
70 | (TARGET_ZARCH && TARGET_CPU_EXTIMM) | |
85dae55a | 71 | #define TARGET_DFP \ |
fb068247 | 72 | (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT) |
93538e8e AK |
73 | #define TARGET_Z10 \ |
74 | (TARGET_ZARCH && TARGET_CPU_Z10) | |
65b1d8ea AK |
75 | #define TARGET_Z196 \ |
76 | (TARGET_ZARCH && TARGET_CPU_Z196) | |
77 | ||
78 | ||
79 | #define TARGET_AVOID_CMP_AND_BRANCH (s390_tune == PROCESSOR_2817_Z196) | |
42c78618 | 80 | |
862a2d83 | 81 | /* Run-time target specification. */ |
9db1d521 | 82 | |
a771c4b3 UW |
83 | /* Defaults for option flags defined only on some subtargets. */ |
84 | #ifndef TARGET_TPF_PROFILING | |
85 | #define TARGET_TPF_PROFILING 0 | |
86 | #endif | |
87 | ||
4798630c D |
88 | /* This will be overridden by OS headers. */ |
89 | #define TARGET_TPF 0 | |
90 | ||
862a2d83 UW |
91 | /* Target CPU builtins. */ |
92 | #define TARGET_CPU_CPP_BUILTINS() \ | |
93 | do \ | |
94 | { \ | |
95 | builtin_assert ("cpu=s390"); \ | |
96 | builtin_assert ("machine=s390"); \ | |
97 | builtin_define ("__s390__"); \ | |
9602b6a1 AK |
98 | if (TARGET_ZARCH) \ |
99 | builtin_define ("__zarch__"); \ | |
862a2d83 UW |
100 | if (TARGET_64BIT) \ |
101 | builtin_define ("__s390x__"); \ | |
f61a2c7d AK |
102 | if (TARGET_LONG_DOUBLE_128) \ |
103 | builtin_define ("__LONG_DOUBLE_128__"); \ | |
862a2d83 UW |
104 | } \ |
105 | while (0) | |
9db1d521 | 106 | |
58d10f89 | 107 | #ifdef DEFAULT_TARGET_64BIT |
47d94c1a | 108 | #define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP) |
58d10f89 | 109 | #else |
85dae55a | 110 | #define TARGET_DEFAULT 0 |
58d10f89 UW |
111 | #endif |
112 | ||
f13e0d4e UW |
113 | /* Support for configure-time defaults. */ |
114 | #define OPTION_DEFAULT_SPECS \ | |
115 | { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" }, \ | |
116 | { "arch", "%{!march=*:-march=%(VALUE)}" }, \ | |
117 | { "tune", "%{!mtune=*:-mtune=%(VALUE)}" } | |
118 | ||
119 | /* Defaulting rules. */ | |
120 | #ifdef DEFAULT_TARGET_64BIT | |
121 | #define DRIVER_SELF_SPECS \ | |
122 | "%{!m31:%{!m64:-m64}}", \ | |
123 | "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ | |
124 | "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}" | |
125 | #else | |
126 | #define DRIVER_SELF_SPECS \ | |
127 | "%{!m31:%{!m64:-m31}}", \ | |
128 | "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ | |
129 | "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}" | |
130 | #endif | |
131 | ||
638e37c2 | 132 | /* Constants needed to control the TEST DATA CLASS (TDC) instruction. */ |
0387c142 WG |
133 | #define S390_TDC_POSITIVE_ZERO (1 << 11) |
134 | #define S390_TDC_NEGATIVE_ZERO (1 << 10) | |
135 | #define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER (1 << 9) | |
136 | #define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER (1 << 8) | |
137 | #define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER (1 << 7) | |
138 | #define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER (1 << 6) | |
139 | #define S390_TDC_POSITIVE_INFINITY (1 << 5) | |
140 | #define S390_TDC_NEGATIVE_INFINITY (1 << 4) | |
141 | #define S390_TDC_POSITIVE_QUIET_NAN (1 << 3) | |
142 | #define S390_TDC_NEGATIVE_QUIET_NAN (1 << 2) | |
143 | #define S390_TDC_POSITIVE_SIGNALING_NAN (1 << 1) | |
144 | #define S390_TDC_NEGATIVE_SIGNALING_NAN (1 << 0) | |
145 | ||
146 | /* The following values are different for DFP. */ | |
147 | #define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9) | |
148 | #define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8) | |
149 | #define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER (1 << 7) | |
150 | #define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER (1 << 6) | |
151 | ||
f4aa3848 | 152 | /* For signbit, the BFP-DFP-difference makes no difference. */ |
0f67fa83 | 153 | #define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \ |
0387c142 WG |
154 | | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \ |
155 | | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\ | |
0f67fa83 WG |
156 | | S390_TDC_NEGATIVE_INFINITY \ |
157 | | S390_TDC_NEGATIVE_QUIET_NAN \ | |
158 | | S390_TDC_NEGATIVE_SIGNALING_NAN ) | |
159 | ||
638e37c2 WG |
160 | #define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \ |
161 | | S390_TDC_NEGATIVE_INFINITY ) | |
9db1d521 HP |
162 | |
163 | /* Target machine storage layout. */ | |
164 | ||
862a2d83 | 165 | /* Everything is big-endian. */ |
9db1d521 | 166 | #define BITS_BIG_ENDIAN 1 |
9db1d521 | 167 | #define BYTES_BIG_ENDIAN 1 |
9db1d521 HP |
168 | #define WORDS_BIG_ENDIAN 1 |
169 | ||
9602b6a1 AK |
170 | #define STACK_SIZE_MODE (Pmode) |
171 | ||
fe86047c | 172 | #ifndef IN_LIBGCC2 |
9602b6a1 AK |
173 | |
174 | /* Width of a word, in units (bytes). */ | |
175 | #define UNITS_PER_WORD (TARGET_ZARCH ? 8 : 4) | |
176 | ||
177 | /* Width of a pointer. To be used instead of UNITS_PER_WORD in | |
178 | ABI-relevant contexts. This always matches | |
179 | GET_MODE_SIZE (Pmode). */ | |
180 | #define UNITS_PER_LONG (TARGET_64BIT ? 8 : 4) | |
181 | #define MIN_UNITS_PER_WORD 4 | |
182 | #define MAX_BITS_PER_WORD 64 | |
183 | #else | |
184 | ||
185 | /* In libgcc, UNITS_PER_WORD has ABI-relevant effects, e.g. whether | |
186 | the library should export TImode functions or not. Thus, we have | |
187 | to redefine UNITS_PER_WORD depending on __s390x__ for libgcc. */ | |
188 | #ifdef __s390x__ | |
189 | #define UNITS_PER_WORD 8 | |
190 | #else | |
191 | #define UNITS_PER_WORD 4 | |
192 | #endif | |
fe86047c | 193 | #endif |
9602b6a1 AK |
194 | |
195 | /* Width of a pointer, in bits. */ | |
196 | #define POINTER_SIZE (TARGET_64BIT ? 64 : 32) | |
9db1d521 | 197 | |
9db1d521 | 198 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
9db1d521 HP |
199 | #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32) |
200 | ||
201 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
9db1d521 HP |
202 | #define STACK_BOUNDARY 64 |
203 | ||
204 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
9db1d521 HP |
205 | #define FUNCTION_BOUNDARY 32 |
206 | ||
207 | /* There is no point aligning anything to a rounder boundary than this. */ | |
9db1d521 HP |
208 | #define BIGGEST_ALIGNMENT 64 |
209 | ||
210 | /* Alignment of field after `int : 0' in a structure. */ | |
9db1d521 HP |
211 | #define EMPTY_FIELD_BOUNDARY 32 |
212 | ||
f710504c | 213 | /* Alignment on even addresses for LARL instruction. */ |
9db1d521 | 214 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) |
9db1d521 HP |
215 | #define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) |
216 | ||
862a2d83 | 217 | /* Alignment is not required by the hardware. */ |
9db1d521 HP |
218 | #define STRICT_ALIGNMENT 0 |
219 | ||
862a2d83 UW |
220 | /* Mode of stack savearea. |
221 | FUNCTION is VOIDmode because calling convention maintains SP. | |
222 | BLOCK needs Pmode for SP. | |
223 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ | |
224 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
225 | (LEVEL == SAVE_FUNCTION ? VOIDmode \ | |
43ab026f | 226 | : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode) |
862a2d83 | 227 | |
9db1d521 | 228 | |
862a2d83 | 229 | /* Type layout. */ |
9db1d521 | 230 | |
862a2d83 UW |
231 | /* Sizes in bits of the source language data types. */ |
232 | #define SHORT_TYPE_SIZE 16 | |
233 | #define INT_TYPE_SIZE 32 | |
234 | #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) | |
862a2d83 UW |
235 | #define LONG_LONG_TYPE_SIZE 64 |
236 | #define FLOAT_TYPE_SIZE 32 | |
237 | #define DOUBLE_TYPE_SIZE 64 | |
f61a2c7d AK |
238 | #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) |
239 | ||
240 | /* Define this to set long double type size to use in libgcc2.c, which can | |
241 | not depend on target_flags. */ | |
242 | #ifdef __LONG_DOUBLE_128__ | |
243 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 | |
244 | #else | |
245 | #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 | |
246 | #endif | |
247 | ||
248 | /* Work around target_flags dependency in ada/targtyps.c. */ | |
249 | #define WIDEST_HARDWARE_FP_SIZE 64 | |
862a2d83 UW |
250 | |
251 | /* We use "unsigned char" as default. */ | |
252 | #define DEFAULT_SIGNED_CHAR 0 | |
253 | ||
254 | ||
255 | /* Register usage. */ | |
256 | ||
257 | /* We have 16 general purpose registers (registers 0-15), | |
258 | and 16 floating point registers (registers 16-31). | |
259 | (On non-IEEE machines, we have only 4 fp registers.) | |
c7453384 | 260 | |
862a2d83 UW |
261 | Amongst the general purpose registers, some are used |
262 | for specific purposes: | |
263 | GPR 11: Hard frame pointer (if needed) | |
264 | GPR 12: Global offset table pointer (if needed) | |
265 | GPR 13: Literal pool base register | |
266 | GPR 14: Return address register | |
267 | GPR 15: Stack pointer | |
c7453384 | 268 | |
c5aa1d12 | 269 | Registers 32-35 are 'fake' hard registers that do not |
862a2d83 UW |
270 | correspond to actual hardware: |
271 | Reg 32: Argument pointer | |
272 | Reg 33: Condition code | |
f4aa3848 | 273 | Reg 34: Frame pointer |
c5aa1d12 | 274 | Reg 35: Return address pointer |
862a2d83 | 275 | |
f4aa3848 | 276 | Registers 36 and 37 are mapped to access registers |
c5aa1d12 UW |
277 | 0 and 1, used to implement thread-local storage. */ |
278 | ||
279 | #define FIRST_PSEUDO_REGISTER 38 | |
862a2d83 UW |
280 | |
281 | /* Standard register usage. */ | |
8e509cf9 UW |
282 | #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16) |
283 | #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16) | |
142cd70f | 284 | #define FP_REGNO_P(N) ((N) >= 16 && (N) < 32) |
8e509cf9 | 285 | #define CC_REGNO_P(N) ((N) == 33) |
a38e09bc | 286 | #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34 || (N) == 35) |
c5aa1d12 | 287 | #define ACCESS_REGNO_P(N) ((N) == 36 || (N) == 37) |
8e509cf9 UW |
288 | |
289 | #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) | |
290 | #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X))) | |
291 | #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) | |
292 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) | |
4888ec5d | 293 | #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X))) |
c5aa1d12 | 294 | #define ACCESS_REG_P(X) (REG_P (X) && ACCESS_REGNO_P (REGNO (X))) |
9db1d521 | 295 | |
862a2d83 | 296 | /* Set up fixed registers and calling convention: |
9db1d521 | 297 | |
862a2d83 UW |
298 | GPRs 0-5 are always call-clobbered, |
299 | GPRs 6-15 are always call-saved. | |
300 | GPR 12 is fixed if used as GOT pointer. | |
301 | GPR 13 is always fixed (as literal pool pointer). | |
545d16ff | 302 | GPR 14 is always fixed on S/390 machines (as return address). |
862a2d83 UW |
303 | GPR 15 is always fixed (as stack pointer). |
304 | The 'fake' hard registers are call-clobbered and fixed. | |
c5aa1d12 | 305 | The access registers are call-saved and fixed. |
9db1d521 | 306 | |
862a2d83 UW |
307 | On 31-bit, FPRs 18-19 are call-clobbered; |
308 | on 64-bit, FPRs 24-31 are call-clobbered. | |
309 | The remaining FPRs are call-saved. */ | |
9db1d521 HP |
310 | |
311 | #define FIXED_REGISTERS \ | |
312 | { 0, 0, 0, 0, \ | |
313 | 0, 0, 0, 0, \ | |
314 | 0, 0, 0, 0, \ | |
315 | 0, 1, 1, 1, \ | |
316 | 0, 0, 0, 0, \ | |
317 | 0, 0, 0, 0, \ | |
318 | 0, 0, 0, 0, \ | |
319 | 0, 0, 0, 0, \ | |
c5aa1d12 UW |
320 | 1, 1, 1, 1, \ |
321 | 1, 1 } | |
9db1d521 | 322 | |
9db1d521 HP |
323 | #define CALL_USED_REGISTERS \ |
324 | { 1, 1, 1, 1, \ | |
325 | 1, 1, 0, 0, \ | |
326 | 0, 0, 0, 0, \ | |
327 | 0, 1, 1, 1, \ | |
4023fb28 UW |
328 | 1, 1, 1, 1, \ |
329 | 1, 1, 1, 1, \ | |
330 | 1, 1, 1, 1, \ | |
331 | 1, 1, 1, 1, \ | |
c5aa1d12 UW |
332 | 1, 1, 1, 1, \ |
333 | 1, 1 } | |
4023fb28 | 334 | |
4023fb28 UW |
335 | #define CALL_REALLY_USED_REGISTERS \ |
336 | { 1, 1, 1, 1, \ | |
9db1d521 | 337 | 1, 1, 0, 0, \ |
4023fb28 UW |
338 | 0, 0, 0, 0, \ |
339 | 0, 0, 0, 0, \ | |
9db1d521 HP |
340 | 1, 1, 1, 1, \ |
341 | 1, 1, 1, 1, \ | |
342 | 1, 1, 1, 1, \ | |
4023fb28 | 343 | 1, 1, 1, 1, \ |
c5aa1d12 UW |
344 | 1, 1, 1, 1, \ |
345 | 0, 0 } | |
9db1d521 | 346 | |
862a2d83 UW |
347 | /* Preferred register allocation order. */ |
348 | #define REG_ALLOC_ORDER \ | |
7633f08e | 349 | { 1, 2, 3, 4, 5, 0, 12, 11, 10, 9, 8, 7, 6, 14, 13, \ |
862a2d83 UW |
350 | 16, 17, 18, 19, 20, 21, 22, 23, \ |
351 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
c5aa1d12 | 352 | 15, 32, 33, 34, 35, 36, 37 } |
9db1d521 | 353 | |
9db1d521 | 354 | |
862a2d83 | 355 | /* Fitting values into registers. */ |
c7453384 | 356 | |
862a2d83 UW |
357 | /* Integer modes <= word size fit into any GPR. |
358 | Integer modes > word size fit into successive GPRs, starting with | |
359 | an even-numbered register. | |
360 | SImode and DImode fit into FPRs as well. | |
c7453384 | 361 | |
862a2d83 UW |
362 | Floating point modes <= word size fit into any FPR or GPR. |
363 | Floating point modes > word size (i.e. DFmode on 32-bit) fit | |
364 | into any FPR, or an even-odd GPR pair. | |
f61a2c7d | 365 | TFmode fits only into an even-odd FPR pair. |
c7453384 | 366 | |
862a2d83 UW |
367 | Complex floating point modes fit either into two FPRs, or into |
368 | successive GPRs (again starting with an even number). | |
f61a2c7d | 369 | TCmode fits only into two successive even-odd FPR pairs. |
c7453384 | 370 | |
862a2d83 | 371 | Condition code modes fit only into the CC register. */ |
9db1d521 | 372 | |
74aa8b4b AK |
373 | /* Because all registers in a class have the same size HARD_REGNO_NREGS |
374 | is equivalent to CLASS_MAX_NREGS. */ | |
9db1d521 | 375 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
74aa8b4b AK |
376 | s390_class_max_nregs (REGNO_REG_CLASS (REGNO), (MODE)) |
377 | ||
378 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
379 | s390_hard_regno_mode_ok ((REGNO), (MODE)) | |
380 | ||
381 | #define HARD_REGNO_RENAME_OK(FROM, TO) \ | |
7633f08e UW |
382 | s390_hard_regno_rename_ok (FROM, TO) |
383 | ||
9db1d521 HP |
384 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
385 | (((MODE1) == SFmode || (MODE1) == DFmode) \ | |
386 | == ((MODE2) == SFmode || (MODE2) == DFmode)) | |
387 | ||
9602b6a1 AK |
388 | /* When generating code that runs in z/Architecture mode, |
389 | but conforms to the 31-bit ABI, GPRs can hold 8 bytes; | |
390 | the ABI guarantees only that the lower 4 bytes are | |
391 | saved across calls, however. */ | |
392 | #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ | |
393 | (!TARGET_64BIT && TARGET_ZARCH \ | |
394 | && GET_MODE_SIZE (MODE) > 4 \ | |
395 | && (((REGNO) >= 6 && (REGNO) <= 15) || (REGNO) == 32)) | |
396 | ||
862a2d83 UW |
397 | /* Maximum number of registers to represent a value of mode MODE |
398 | in a register of class CLASS. */ | |
399 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
74aa8b4b | 400 | s390_class_max_nregs ((CLASS), (MODE)) |
4023fb28 | 401 | |
862a2d83 UW |
402 | /* If a 4-byte value is loaded into a FPR, it is placed into the |
403 | *upper* half of the register, not the lower. Therefore, we | |
c5aa1d12 UW |
404 | cannot use SUBREGs to switch between modes in FP registers. |
405 | Likewise for access registers, since they have only half the | |
406 | word size on 64-bit. */ | |
f61a2c7d AK |
407 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ |
408 | (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ | |
409 | ? ((reg_classes_intersect_p (FP_REGS, CLASS) \ | |
410 | && (GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8)) \ | |
411 | || reg_classes_intersect_p (ACCESS_REGS, CLASS)) : 0) | |
9db1d521 | 412 | |
862a2d83 | 413 | /* Register classes. */ |
c7453384 | 414 | |
862a2d83 UW |
415 | /* We use the following register classes: |
416 | GENERAL_REGS All general purpose registers | |
417 | ADDR_REGS All general purpose registers except %r0 | |
418 | (These registers can be used in address generation) | |
419 | FP_REGS All floating point registers | |
c5aa1d12 UW |
420 | CC_REGS The condition code register |
421 | ACCESS_REGS The access registers | |
c7453384 | 422 | |
862a2d83 UW |
423 | GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS |
424 | ADDR_FP_REGS Union of ADDR_REGS and FP_REGS | |
c5aa1d12 UW |
425 | GENERAL_CC_REGS Union of GENERAL_REGS and CC_REGS |
426 | ADDR_CC_REGS Union of ADDR_REGS and CC_REGS | |
c7453384 | 427 | |
862a2d83 UW |
428 | NO_REGS No registers |
429 | ALL_REGS All registers | |
c7453384 | 430 | |
862a2d83 | 431 | Note that the 'fake' frame pointer and argument pointer registers |
c5aa1d12 | 432 | are included amongst the address registers here. */ |
9db1d521 HP |
433 | |
434 | enum reg_class | |
435 | { | |
c5aa1d12 | 436 | NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS, |
f4aa3848 | 437 | ADDR_CC_REGS, GENERAL_CC_REGS, |
4023fb28 UW |
438 | FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, |
439 | ALL_REGS, LIM_REG_CLASSES | |
9db1d521 | 440 | }; |
9db1d521 HP |
441 | #define N_REG_CLASSES (int) LIM_REG_CLASSES |
442 | ||
c5aa1d12 UW |
443 | #define REG_CLASS_NAMES \ |
444 | { "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS", \ | |
445 | "ADDR_CC_REGS", "GENERAL_CC_REGS", \ | |
446 | "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" } | |
9db1d521 | 447 | |
862a2d83 | 448 | /* Class -> register mapping. */ |
9db1d521 HP |
449 | #define REG_CLASS_CONTENTS \ |
450 | { \ | |
451 | { 0x00000000, 0x00000000 }, /* NO_REGS */ \ | |
9dc62c00 | 452 | { 0x00000000, 0x00000002 }, /* CC_REGS */ \ |
a38e09bc AK |
453 | { 0x0000fffe, 0x0000000d }, /* ADDR_REGS */ \ |
454 | { 0x0000ffff, 0x0000000d }, /* GENERAL_REGS */ \ | |
c5aa1d12 | 455 | { 0x00000000, 0x00000030 }, /* ACCESS_REGS */ \ |
9dc62c00 AK |
456 | { 0x0000fffe, 0x0000000f }, /* ADDR_CC_REGS */ \ |
457 | { 0x0000ffff, 0x0000000f }, /* GENERAL_CC_REGS */ \ | |
9db1d521 | 458 | { 0xffff0000, 0x00000000 }, /* FP_REGS */ \ |
a38e09bc AK |
459 | { 0xfffffffe, 0x0000000d }, /* ADDR_FP_REGS */ \ |
460 | { 0xffffffff, 0x0000000d }, /* GENERAL_FP_REGS */ \ | |
c5aa1d12 | 461 | { 0xffffffff, 0x0000003f }, /* ALL_REGS */ \ |
9db1d521 HP |
462 | } |
463 | ||
058e97ec VM |
464 | /* In some case register allocation order is not enough for IRA to |
465 | generate a good code. The following macro (if defined) increases | |
466 | cost of REGNO for a pseudo approximately by pseudo usage frequency | |
467 | multiplied by the macro value. | |
468 | ||
469 | We avoid usage of BASE_REGNUM by nonzero macro value because the | |
470 | reload can decide not to use the hard register because some | |
471 | constant was forced to be in memory. */ | |
472 | #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) \ | |
473 | (regno == BASE_REGNUM ? 0.0 : 0.5) | |
474 | ||
862a2d83 UW |
475 | /* Register -> class mapping. */ |
476 | extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; | |
477 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) | |
9db1d521 | 478 | |
862a2d83 UW |
479 | /* ADDR_REGS can be used as base or index register. */ |
480 | #define INDEX_REG_CLASS ADDR_REGS | |
481 | #define BASE_REG_CLASS ADDR_REGS | |
9db1d521 | 482 | |
862a2d83 UW |
483 | /* Check whether REGNO is a hard register of the suitable class |
484 | or a pseudo register currently allocated to one such. */ | |
485 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
486 | (((REGNO) < FIRST_PSEUDO_REGISTER \ | |
93fa8428 AK |
487 | && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \ |
488 | || ADDR_REGNO_P (reg_renumber[REGNO])) | |
862a2d83 | 489 | #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) |
9db1d521 | 490 | |
9db1d521 | 491 | |
963fc8d0 AK |
492 | /* We need secondary memory to move data between GPRs and FPRs. With |
493 | DFP the ldgr lgdr instructions are available. But these | |
494 | instructions do not handle GPR pairs so it is not possible for 31 | |
495 | bit. */ | |
862a2d83 | 496 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ |
85dae55a AK |
497 | ((CLASS1) != (CLASS2) \ |
498 | && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS) \ | |
963fc8d0 | 499 | && (!TARGET_DFP || !TARGET_64BIT || GET_MODE_SIZE (MODE) != 8)) |
862a2d83 UW |
500 | |
501 | /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit | |
502 | because the movsi and movsf patterns don't handle r/f moves. */ | |
503 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
504 | (GET_MODE_BITSIZE (MODE) < 32 \ | |
505 | ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
506 | : MODE) | |
507 | ||
508 | ||
862a2d83 | 509 | /* Stack layout and calling conventions. */ |
c7453384 | 510 | |
862a2d83 UW |
511 | /* Our stack grows from higher to lower addresses. However, local variables |
512 | are accessed by positive offsets, and function arguments are stored at | |
513 | increasing addresses. */ | |
514 | #define STACK_GROWS_DOWNWARD | |
63296cb1 | 515 | #define FRAME_GROWS_DOWNWARD 1 |
862a2d83 | 516 | /* #undef ARGS_GROW_DOWNWARD */ |
9db1d521 | 517 | |
862a2d83 UW |
518 | /* The basic stack layout looks like this: the stack pointer points |
519 | to the register save area for called functions. Above that area | |
520 | is the location to place outgoing arguments. Above those follow | |
521 | dynamic allocations (alloca), and finally the local variables. */ | |
9db1d521 | 522 | |
862a2d83 UW |
523 | /* Offset from stack-pointer to first location of outgoing args. */ |
524 | #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96) | |
9db1d521 | 525 | |
862a2d83 | 526 | /* Offset within stack frame to start allocating local variables at. */ |
63296cb1 | 527 | #define STARTING_FRAME_OFFSET 0 |
9db1d521 | 528 | |
862a2d83 UW |
529 | /* Offset from the stack pointer register to an item dynamically |
530 | allocated on the stack, e.g., by `alloca'. */ | |
63296cb1 | 531 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ |
38173d38 | 532 | (STACK_POINTER_OFFSET + crtl->outgoing_args_size) |
9db1d521 | 533 | |
862a2d83 UW |
534 | /* Offset of first parameter from the argument pointer register value. |
535 | We have a fake argument pointer register that points directly to | |
536 | the argument area. */ | |
537 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
9db1d521 | 538 | |
f4aa3848 | 539 | /* Defining this macro makes __builtin_frame_address(0) and |
c6d01079 AK |
540 | __builtin_return_address(0) work with -fomit-frame-pointer. */ |
541 | #define INITIAL_FRAME_ADDRESS_RTX \ | |
0a81f074 | 542 | (plus_constant (Pmode, arg_pointer_rtx, -STACK_POINTER_OFFSET)) |
c6d01079 | 543 | |
c7453384 | 544 | /* The return address of the current frame is retrieved |
4023fb28 UW |
545 | from the initial value of register RETURN_REGNUM. |
546 | For frames farther back, we use the stack slot where | |
547 | the corresponding RETURN_REGNUM register was saved. */ | |
c6d01079 AK |
548 | #define DYNAMIC_CHAIN_ADDRESS(FRAME) \ |
549 | (TARGET_PACKED_STACK ? \ | |
0a81f074 RS |
550 | plus_constant (Pmode, (FRAME), \ |
551 | STACK_POINTER_OFFSET - UNITS_PER_LONG) : (FRAME)) | |
4023fb28 | 552 | |
78791a80 AK |
553 | /* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of |
554 | builtin_frame_address. Otherwise arg pointer - | |
555 | STACK_POINTER_OFFSET would be returned for | |
556 | __builtin_frame_address(0) what might result in an address pointing | |
557 | somewhere into the middle of the local variables since the packed | |
558 | stack layout generally does not need all the bytes in the register | |
559 | save area. */ | |
560 | #define FRAME_ADDR_RTX(FRAME) \ | |
561 | DYNAMIC_CHAIN_ADDRESS ((FRAME)) | |
562 | ||
c6d01079 | 563 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
5d4d885c | 564 | s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME))) |
9db1d521 | 565 | |
862a2d83 | 566 | /* In 31-bit mode, we need to mask off the high bit of return addresses. */ |
a556fd39 | 567 | #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff)) |
9db1d521 | 568 | |
4023fb28 | 569 | |
862a2d83 | 570 | /* Exception handling. */ |
c7453384 | 571 | |
862a2d83 UW |
572 | /* Describe calling conventions for DWARF-2 exception handling. */ |
573 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM) | |
4023fb28 | 574 | #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET |
9db1d521 HP |
575 | #define DWARF_FRAME_RETURN_COLUMN 14 |
576 | ||
577 | /* Describe how we implement __builtin_eh_return. */ | |
578 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM) | |
a38e09bc | 579 | #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx) |
f4aa3848 | 580 | |
18789f4e UW |
581 | /* Select a format to encode pointers in exception handling data. */ |
582 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
583 | (flag_pic \ | |
584 | ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ | |
585 | : DW_EH_PE_absptr) | |
586 | ||
9602b6a1 AK |
587 | /* Register save slot alignment. */ |
588 | #define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_LONG) | |
589 | ||
9db1d521 | 590 | |
862a2d83 | 591 | /* Frame registers. */ |
9db1d521 | 592 | |
862a2d83 UW |
593 | #define STACK_POINTER_REGNUM 15 |
594 | #define FRAME_POINTER_REGNUM 34 | |
595 | #define HARD_FRAME_POINTER_REGNUM 11 | |
596 | #define ARG_POINTER_REGNUM 32 | |
a38e09bc | 597 | #define RETURN_ADDRESS_POINTER_REGNUM 35 |
9db1d521 | 598 | |
c7453384 EC |
599 | /* The static chain must be call-clobbered, but not used for |
600 | function argument passing. As register 1 is clobbered by | |
862a2d83 UW |
601 | the trampoline code, we only have one option. */ |
602 | #define STATIC_CHAIN_REGNUM 0 | |
9db1d521 | 603 | |
862a2d83 UW |
604 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
605 | To avoid ABI incompatibility, this number must not change even as | |
606 | 'fake' hard registers are added or removed. */ | |
607 | #define DWARF_FRAME_REGISTERS 34 | |
9db1d521 | 608 | |
9db1d521 | 609 | |
862a2d83 | 610 | /* Frame pointer and argument pointer elimination. */ |
9db1d521 | 611 | |
7633f08e UW |
612 | #define ELIMINABLE_REGS \ |
613 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
614 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
615 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
616 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
617 | { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
618 | { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
619 | { BASE_REGNUM, BASE_REGNUM }} | |
9db1d521 | 620 | |
91086990 UW |
621 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
622 | (OFFSET) = s390_initial_elimination_offset ((FROM), (TO)) | |
9db1d521 | 623 | |
9db1d521 | 624 | |
862a2d83 | 625 | /* Stack arguments. */ |
c7453384 | 626 | |
862a2d83 UW |
627 | /* We need current_function_outgoing_args to be valid. */ |
628 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
9db1d521 | 629 | |
9db1d521 | 630 | |
862a2d83 | 631 | /* Register arguments. */ |
c7453384 | 632 | |
9db1d521 HP |
633 | typedef struct s390_arg_structure |
634 | { | |
635 | int gprs; /* gpr so far */ | |
636 | int fprs; /* fpr so far */ | |
637 | } | |
638 | CUMULATIVE_ARGS; | |
639 | ||
07711f53 | 640 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \ |
9db1d521 HP |
641 | ((CUM).gprs=0, (CUM).fprs=0) |
642 | ||
96e2afa8 AK |
643 | /* Arguments can be placed in general registers 2 to 6, or in floating |
644 | point registers 0 and 2 for 31 bit and fprs 0, 2, 4 and 6 for 64 | |
645 | bit. */ | |
862a2d83 | 646 | #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \ |
96e2afa8 | 647 | (N) == 16 || (N) == 17 || (TARGET_64BIT && ((N) == 18 || (N) == 19))) |
9db1d521 | 648 | |
9db1d521 | 649 | |
862a2d83 | 650 | /* Only gpr 2 and fpr 0 are ever used as return registers. */ |
9db1d521 HP |
651 | #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16) |
652 | ||
9db1d521 | 653 | |
862a2d83 | 654 | /* Function entry and exit. */ |
c7453384 | 655 | |
862a2d83 UW |
656 | /* When returning from a function, the stack pointer does not matter. */ |
657 | #define EXIT_IGNORE_STACK 1 | |
9db1d521 | 658 | |
9db1d521 | 659 | |
862a2d83 | 660 | /* Profiling. */ |
9db1d521 HP |
661 | |
662 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
862a2d83 | 663 | s390_function_profiler ((FILE), ((LABELNO))) |
9db1d521 | 664 | |
c52a375d | 665 | #define PROFILE_BEFORE_PROLOGUE 1 |
9db1d521 | 666 | |
9db1d521 | 667 | |
862a2d83 | 668 | /* Trampolines for nested functions. */ |
9db1d521 | 669 | |
b81ecf6f RH |
670 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 32 : 16) |
671 | #define TRAMPOLINE_ALIGNMENT BITS_PER_WORD | |
9db1d521 | 672 | |
862a2d83 | 673 | /* Addressing modes, and classification of registers for them. */ |
9db1d521 | 674 | |
862a2d83 UW |
675 | /* Recognize any constant value that is a valid address. */ |
676 | #define CONSTANT_ADDRESS_P(X) 0 | |
9db1d521 | 677 | |
862a2d83 UW |
678 | /* Maximum number of registers that can appear in a valid memory address. */ |
679 | #define MAX_REGS_PER_ADDRESS 2 | |
9db1d521 | 680 | |
963fc8d0 | 681 | /* This definition replaces the formerly used 'm' constraint with a |
c6c3dba9 PB |
682 | different constraint letter in order to avoid changing semantics of |
683 | the 'm' constraint when accepting new address formats in | |
684 | TARGET_LEGITIMATE_ADDRESS_P. The constraint letter defined here | |
685 | must not be used in insn definitions or inline assemblies. */ | |
963fc8d0 AK |
686 | #define TARGET_MEM_CONSTRAINT 'e' |
687 | ||
0b540f12 UW |
688 | /* Try a machine-dependent way of reloading an illegitimate address |
689 | operand. If we find one, push the reload and jump to WIN. This | |
690 | macro is used in only one place: `find_reloads_address' in reload.c. */ | |
691 | #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ | |
692 | do { \ | |
0a2aaacc KG |
693 | rtx new_rtx = legitimize_reload_address (AD, MODE, OPNUM, (int)(TYPE)); \ |
694 | if (new_rtx) \ | |
0b540f12 | 695 | { \ |
0a2aaacc | 696 | (AD) = new_rtx; \ |
0b540f12 UW |
697 | goto WIN; \ |
698 | } \ | |
699 | } while (0) | |
700 | ||
862a2d83 UW |
701 | /* Helper macro for s390.c and s390.md to check for symbolic constants. */ |
702 | #define SYMBOLIC_CONST(X) \ | |
703 | (GET_CODE (X) == SYMBOL_REF \ | |
704 | || GET_CODE (X) == LABEL_REF \ | |
705 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
9db1d521 | 706 | |
fd3cd001 UW |
707 | #define TLS_SYMBOLIC_CONST(X) \ |
708 | ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \ | |
709 | || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X))) | |
710 | ||
9db1d521 | 711 | |
862a2d83 | 712 | /* Condition codes. */ |
9db1d521 | 713 | |
862a2d83 UW |
714 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
715 | return the mode to be used for the comparison. */ | |
716 | #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y)) | |
c7453384 | 717 | |
68f9c5e2 UW |
718 | /* Canonicalize a comparison from one we don't have to one we do have. */ |
719 | #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ | |
720 | s390_canonicalize_comparison (&(CODE), &(OP0), &(OP1)) | |
721 | ||
862a2d83 | 722 | /* Relative costs of operations. */ |
9db1d521 | 723 | |
9db1d521 HP |
724 | /* A C expression for the cost of a branch instruction. A value of 1 |
725 | is the default; other values are interpreted relative to that. */ | |
3d427cc1 | 726 | #define BRANCH_COST(speed_p, predictable_p) s390_branch_cost |
9db1d521 | 727 | |
862a2d83 UW |
728 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
729 | #define SLOW_BYTE_ACCESS 1 | |
730 | ||
c5443745 | 731 | /* An integer expression for the size in bits of the largest integer machine |
f4aa3848 | 732 | mode that should actually be used. We allow pairs of registers. */ |
c5443745 UW |
733 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) |
734 | ||
862a2d83 | 735 | /* The maximum number of bytes that a single instruction can move quickly |
ff482c8d | 736 | between memory and registers or between two memory locations. */ |
9602b6a1 AK |
737 | #define MOVE_MAX (TARGET_ZARCH ? 16 : 8) |
738 | #define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4) | |
862a2d83 | 739 | #define MAX_MOVE_MAX 16 |
9db1d521 | 740 | |
862a2d83 UW |
741 | /* Determine whether to use move_by_pieces or block move insn. */ |
742 | #define MOVE_BY_PIECES_P(SIZE, ALIGN) \ | |
743 | ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ | |
9602b6a1 | 744 | || (TARGET_ZARCH && (SIZE) == 8) ) |
862a2d83 UW |
745 | |
746 | /* Determine whether to use clear_by_pieces or block clear insn. */ | |
747 | #define CLEAR_BY_PIECES_P(SIZE, ALIGN) \ | |
748 | ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ | |
9602b6a1 | 749 | || (TARGET_ZARCH && (SIZE) == 8) ) |
862a2d83 | 750 | |
45d78e7f | 751 | /* This macro is used to determine whether store_by_pieces should be |
cfa31150 | 752 | called to "memcpy" storage when the source is a constant string. */ |
45d78e7f JJ |
753 | #define STORE_BY_PIECES_P(SIZE, ALIGN) MOVE_BY_PIECES_P (SIZE, ALIGN) |
754 | ||
cfa31150 SL |
755 | /* Likewise to decide whether to "memset" storage with byte values |
756 | other than zero. */ | |
757 | #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P (SIZE, ALIGN) | |
758 | ||
862a2d83 UW |
759 | /* Don't perform CSE on function addresses. */ |
760 | #define NO_FUNCTION_CSE | |
761 | ||
5f1b2ee6 AK |
762 | /* This value is used in tree-sra to decide whether it might benefical |
763 | to split a struct move into several word-size moves. For S/390 | |
764 | only small values make sense here since struct moves are relatively | |
765 | cheap thanks to mvc so the small default value choosen for archs | |
766 | with memmove patterns should be ok. But this value is multiplied | |
767 | in tree-sra with UNITS_PER_WORD to make a decision so we adjust it | |
768 | here to compensate for that factor since mvc costs exactly the same | |
769 | on 31 and 64 bit. */ | |
e04ad03d | 770 | #define MOVE_RATIO(speed) (TARGET_64BIT? 2 : 4) |
5f1b2ee6 | 771 | |
862a2d83 UW |
772 | |
773 | /* Sections. */ | |
774 | ||
775 | /* Output before read-only data. */ | |
776 | #define TEXT_SECTION_ASM_OP ".text" | |
777 | ||
778 | /* Output before writable (initialized) data. */ | |
779 | #define DATA_SECTION_ASM_OP ".data" | |
780 | ||
781 | /* Output before writable (uninitialized) data. */ | |
782 | #define BSS_SECTION_ASM_OP ".bss" | |
783 | ||
784 | /* S/390 constant pool breaks the devices in crtstuff.c to control section | |
785 | in where code resides. We have to write it as asm code. */ | |
786 | #ifndef __s390x__ | |
787 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
788 | asm (SECTION_OP "\n\ | |
789 | bras\t%r2,1f\n\ | |
790 | 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\ | |
791 | 1: l\t%r3,0(%r2)\n\ | |
792 | bas\t%r14,0(%r3,%r2)\n\ | |
793 | .previous"); | |
794 | #endif | |
63a1ff86 | 795 | |
862a2d83 UW |
796 | |
797 | /* Position independent code. */ | |
798 | ||
862a2d83 UW |
799 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM) |
800 | ||
801 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) | |
63a1ff86 UW |
802 | |
803 | ||
804 | /* Assembler file format. */ | |
805 | ||
806 | /* Character to start a comment. */ | |
807 | #define ASM_COMMENT_START "#" | |
808 | ||
809 | /* Declare an uninitialized external linkage data object. */ | |
810 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
811 | asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) | |
812 | ||
813 | /* Globalizing directive for a label. */ | |
814 | #define GLOBAL_ASM_OP ".globl " | |
815 | ||
816 | /* Advance the location counter to a multiple of 2**LOG bytes. */ | |
817 | #define ASM_OUTPUT_ALIGN(FILE, LOG) \ | |
818 | if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG)) | |
819 | ||
820 | /* Advance the location counter by SIZE bytes. */ | |
821 | #define ASM_OUTPUT_SKIP(FILE, SIZE) \ | |
58e15542 | 822 | fprintf ((FILE), "\t.set\t.,.+"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) |
63a1ff86 | 823 | |
63a1ff86 UW |
824 | /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */ |
825 | #define LOCAL_LABEL_PREFIX "." | |
9db1d521 | 826 | |
5d304e47 AK |
827 | #define LABEL_ALIGN(LABEL) \ |
828 | s390_label_align (LABEL) | |
829 | ||
9db1d521 HP |
830 | /* How to refer to registers in assembler output. This sequence is |
831 | indexed by compiler's hard-register-number (see above). */ | |
9db1d521 HP |
832 | #define REGISTER_NAMES \ |
833 | { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ | |
a38e09bc | 834 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ |
9db1d521 | 835 | "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \ |
a38e09bc | 836 | "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \ |
c5aa1d12 | 837 | "%ap", "%cc", "%fp", "%rp", "%a0", "%a1" \ |
9db1d521 HP |
838 | } |
839 | ||
63a1ff86 | 840 | /* Print operand X (an rtx) in assembler syntax to file FILE. */ |
9db1d521 | 841 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) |
9db1d521 HP |
842 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) |
843 | ||
63a1ff86 UW |
844 | /* Output an element of a case-vector that is absolute. */ |
845 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
846 | do { \ | |
847 | char buf[32]; \ | |
9602b6a1 | 848 | fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ |
63a1ff86 UW |
849 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ |
850 | assemble_name ((FILE), buf); \ | |
851 | fputc ('\n', (FILE)); \ | |
852 | } while (0) | |
853 | ||
854 | /* Output an element of a case-vector that is relative. */ | |
855 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
856 | do { \ | |
857 | char buf[32]; \ | |
9602b6a1 | 858 | fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ |
63a1ff86 UW |
859 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ |
860 | assemble_name ((FILE), buf); \ | |
861 | fputc ('-', (FILE)); \ | |
862 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \ | |
863 | assemble_name ((FILE), buf); \ | |
864 | fputc ('\n', (FILE)); \ | |
865 | } while (0) | |
866 | ||
9db1d521 | 867 | |
862a2d83 UW |
868 | /* Miscellaneous parameters. */ |
869 | ||
862a2d83 UW |
870 | /* Specify the machine mode that this machine uses for the index in the |
871 | tablejump instruction. */ | |
872 | #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) | |
873 | ||
862a2d83 UW |
874 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
875 | is done just by pretending it is already truncated. */ | |
876 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
877 | ||
878 | /* Specify the machine mode that pointers have. | |
879 | After generation of rtl, the compiler makes no further distinction | |
880 | between pointers and any other objects of this machine mode. */ | |
881 | #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode)) | |
882 | ||
c7453384 EC |
883 | /* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */ |
884 | #define POINTERS_EXTEND_UNSIGNED -1 | |
885 | ||
862a2d83 UW |
886 | /* A function address in a call instruction is a byte address (for |
887 | indexing purposes) so give the MEM rtx a byte's mode. */ | |
888 | #define FUNCTION_MODE QImode | |
889 | ||
ec24698e UW |
890 | /* Specify the value which is used when clz operand is zero. */ |
891 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1) | |
892 | ||
0bfc3f69 | 893 | /* Machine-specific symbol_ref flags. */ |
963fc8d0 AK |
894 | #define SYMBOL_FLAG_ALIGN1 (SYMBOL_FLAG_MACH_DEP << 0) |
895 | #define SYMBOL_REF_ALIGN1_P(X) \ | |
896 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN1)) | |
897 | #define SYMBOL_FLAG_NOT_NATURALLY_ALIGNED (SYMBOL_FLAG_MACH_DEP << 1) | |
898 | #define SYMBOL_REF_NOT_NATURALLY_ALIGNED_P(X) \ | |
899 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_NOT_NATURALLY_ALIGNED)) | |
0bfc3f69 AS |
900 | |
901 | /* Check whether integer displacement is in range. */ | |
902 | #define DISP_IN_RANGE(d) \ | |
903 | (TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \ | |
904 | : ((d) >= 0 && (d) <= 4095)) | |
905 | ||
24a235c8 CB |
906 | /* Reads can reuse write prefetches, used by tree-ssa-prefetch-loops.c. */ |
907 | #define READ_CAN_USE_WRITE_PREFETCH 1 | |
677f3fa8 JM |
908 | |
909 | extern const int processor_flags_table[]; | |
c7453384 | 910 | #endif |