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9db1d521 | 1 | /* Definitions of target machine for GNU compiler, for IBM S/390 |
5624e564 | 2 | Copyright (C) 1999-2015 Free Software Foundation, Inc. |
9db1d521 | 3 | Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
f314b9b1 | 4 | Ulrich Weigand (uweigand@de.ibm.com). |
963fc8d0 | 5 | Andreas Krebbel (Andreas.Krebbel@de.ibm.com) |
9db1d521 | 6 | |
58add37a | 7 | This file is part of GCC. |
9db1d521 | 8 | |
58add37a UW |
9 | GCC is free software; you can redistribute it and/or modify it under |
10 | the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | version. |
13 | ||
14 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | for more details. | |
9db1d521 HP |
18 | |
19 | You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | along with GCC; see the file COPYING3. If not see |
21 | <http://www.gnu.org/licenses/>. */ | |
9db1d521 HP |
22 | |
23 | #ifndef _S390_H | |
24 | #define _S390_H | |
25 | ||
f13e0d4e UW |
26 | /* Optional architectural facilities supported by the processor. */ |
27 | ||
28 | enum processor_flags | |
29 | { | |
30 | PF_IEEE_FLOAT = 1, | |
31 | PF_ZARCH = 2, | |
ec24698e | 32 | PF_LONG_DISPLACEMENT = 4, |
85dae55a | 33 | PF_EXTIMM = 8, |
93538e8e | 34 | PF_DFP = 16, |
65b1d8ea | 35 | PF_Z10 = 32, |
22ac2c2f | 36 | PF_Z196 = 64, |
5a3fe9b6 | 37 | PF_ZEC12 = 128, |
55ac540c AK |
38 | PF_TX = 256, |
39 | PF_Z13 = 512, | |
40 | PF_VX = 1024 | |
f13e0d4e UW |
41 | }; |
42 | ||
90c6fd8a AK |
43 | /* This is necessary to avoid a warning about comparing different enum |
44 | types. */ | |
45 | #define s390_tune_attr ((enum attr_cpu)s390_tune) | |
46 | ||
963fc8d0 AK |
47 | /* These flags indicate that the generated code should run on a cpu |
48 | providing the respective hardware facility regardless of the | |
49 | current cpu mode (ESA or z/Architecture). */ | |
50 | ||
f13e0d4e UW |
51 | #define TARGET_CPU_IEEE_FLOAT \ |
52 | (s390_arch_flags & PF_IEEE_FLOAT) | |
53 | #define TARGET_CPU_ZARCH \ | |
54 | (s390_arch_flags & PF_ZARCH) | |
55 | #define TARGET_CPU_LONG_DISPLACEMENT \ | |
56 | (s390_arch_flags & PF_LONG_DISPLACEMENT) | |
ec24698e UW |
57 | #define TARGET_CPU_EXTIMM \ |
58 | (s390_arch_flags & PF_EXTIMM) | |
85dae55a AK |
59 | #define TARGET_CPU_DFP \ |
60 | (s390_arch_flags & PF_DFP) | |
93538e8e AK |
61 | #define TARGET_CPU_Z10 \ |
62 | (s390_arch_flags & PF_Z10) | |
65b1d8ea AK |
63 | #define TARGET_CPU_Z196 \ |
64 | (s390_arch_flags & PF_Z196) | |
22ac2c2f AK |
65 | #define TARGET_CPU_ZEC12 \ |
66 | (s390_arch_flags & PF_ZEC12) | |
5a3fe9b6 AK |
67 | #define TARGET_CPU_HTM \ |
68 | (s390_arch_flags & PF_TX) | |
55ac540c AK |
69 | #define TARGET_CPU_Z13 \ |
70 | (s390_arch_flags & PF_Z13) | |
71 | #define TARGET_CPU_VX \ | |
72 | (s390_arch_flags & PF_VX) | |
f13e0d4e | 73 | |
963fc8d0 AK |
74 | /* These flags indicate that the generated code should run on a cpu |
75 | providing the respective hardware facility when run in | |
76 | z/Architecture mode. */ | |
77 | ||
f13e0d4e UW |
78 | #define TARGET_LONG_DISPLACEMENT \ |
79 | (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT) | |
ec24698e UW |
80 | #define TARGET_EXTIMM \ |
81 | (TARGET_ZARCH && TARGET_CPU_EXTIMM) | |
85dae55a | 82 | #define TARGET_DFP \ |
fb068247 | 83 | (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT) |
93538e8e AK |
84 | #define TARGET_Z10 \ |
85 | (TARGET_ZARCH && TARGET_CPU_Z10) | |
65b1d8ea AK |
86 | #define TARGET_Z196 \ |
87 | (TARGET_ZARCH && TARGET_CPU_Z196) | |
22ac2c2f AK |
88 | #define TARGET_ZEC12 \ |
89 | (TARGET_ZARCH && TARGET_CPU_ZEC12) | |
167f68ed | 90 | #define TARGET_HTM (TARGET_OPT_HTM) |
55ac540c AK |
91 | #define TARGET_Z13 \ |
92 | (TARGET_ZARCH && TARGET_CPU_Z13) | |
93 | #define TARGET_VX \ | |
94 | (TARGET_ZARCH && TARGET_CPU_VX && TARGET_OPT_VX && TARGET_HARD_FLOAT) | |
65b1d8ea | 95 | |
55ac540c AK |
96 | /* Use the ABI introduced with IBM z13: |
97 | - pass vector arguments <= 16 bytes in VRs | |
98 | - align *all* vector types to 8 bytes */ | |
99 | #define TARGET_VX_ABI TARGET_VX | |
65b1d8ea AK |
100 | |
101 | #define TARGET_AVOID_CMP_AND_BRANCH (s390_tune == PROCESSOR_2817_Z196) | |
42c78618 | 102 | |
862a2d83 | 103 | /* Run-time target specification. */ |
9db1d521 | 104 | |
a771c4b3 UW |
105 | /* Defaults for option flags defined only on some subtargets. */ |
106 | #ifndef TARGET_TPF_PROFILING | |
107 | #define TARGET_TPF_PROFILING 0 | |
108 | #endif | |
109 | ||
4798630c D |
110 | /* This will be overridden by OS headers. */ |
111 | #define TARGET_TPF 0 | |
112 | ||
862a2d83 | 113 | /* Target CPU builtins. */ |
3af82a61 | 114 | #define TARGET_CPU_CPP_BUILTINS() s390_cpu_cpp_builtins (pfile) |
9db1d521 | 115 | |
58d10f89 | 116 | #ifdef DEFAULT_TARGET_64BIT |
55ac540c AK |
117 | #define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP \ |
118 | | MASK_OPT_HTM | MASK_OPT_VX) | |
58d10f89 | 119 | #else |
85dae55a | 120 | #define TARGET_DEFAULT 0 |
58d10f89 UW |
121 | #endif |
122 | ||
f13e0d4e UW |
123 | /* Support for configure-time defaults. */ |
124 | #define OPTION_DEFAULT_SPECS \ | |
125 | { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" }, \ | |
126 | { "arch", "%{!march=*:-march=%(VALUE)}" }, \ | |
127 | { "tune", "%{!mtune=*:-mtune=%(VALUE)}" } | |
128 | ||
63281f61 | 129 | #ifdef __s390__ |
cb0edc39 DV |
130 | extern const char *s390_host_detect_local_cpu (int argc, const char **argv); |
131 | # define EXTRA_SPEC_FUNCTIONS \ | |
132 | { "local_cpu_detect", s390_host_detect_local_cpu }, | |
133 | ||
134 | # define MARCH_MTUNE_NATIVE_SPECS \ | |
135 | " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ | |
136 | " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" | |
63281f61 DV |
137 | #else |
138 | # define MARCH_MTUNE_NATIVE_SPECS "" | |
139 | #endif | |
cb0edc39 | 140 | |
f13e0d4e UW |
141 | /* Defaulting rules. */ |
142 | #ifdef DEFAULT_TARGET_64BIT | |
143 | #define DRIVER_SELF_SPECS \ | |
144 | "%{!m31:%{!m64:-m64}}", \ | |
145 | "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ | |
cb0edc39 DV |
146 | "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}", \ |
147 | MARCH_MTUNE_NATIVE_SPECS | |
f13e0d4e UW |
148 | #else |
149 | #define DRIVER_SELF_SPECS \ | |
150 | "%{!m31:%{!m64:-m31}}", \ | |
151 | "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ | |
cb0edc39 DV |
152 | "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}", \ |
153 | MARCH_MTUNE_NATIVE_SPECS | |
f13e0d4e UW |
154 | #endif |
155 | ||
638e37c2 | 156 | /* Constants needed to control the TEST DATA CLASS (TDC) instruction. */ |
0387c142 WG |
157 | #define S390_TDC_POSITIVE_ZERO (1 << 11) |
158 | #define S390_TDC_NEGATIVE_ZERO (1 << 10) | |
159 | #define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER (1 << 9) | |
160 | #define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER (1 << 8) | |
161 | #define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER (1 << 7) | |
162 | #define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER (1 << 6) | |
163 | #define S390_TDC_POSITIVE_INFINITY (1 << 5) | |
164 | #define S390_TDC_NEGATIVE_INFINITY (1 << 4) | |
165 | #define S390_TDC_POSITIVE_QUIET_NAN (1 << 3) | |
166 | #define S390_TDC_NEGATIVE_QUIET_NAN (1 << 2) | |
167 | #define S390_TDC_POSITIVE_SIGNALING_NAN (1 << 1) | |
168 | #define S390_TDC_NEGATIVE_SIGNALING_NAN (1 << 0) | |
169 | ||
170 | /* The following values are different for DFP. */ | |
171 | #define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9) | |
172 | #define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8) | |
173 | #define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER (1 << 7) | |
174 | #define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER (1 << 6) | |
175 | ||
f4aa3848 | 176 | /* For signbit, the BFP-DFP-difference makes no difference. */ |
0f67fa83 | 177 | #define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \ |
0387c142 WG |
178 | | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \ |
179 | | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\ | |
0f67fa83 WG |
180 | | S390_TDC_NEGATIVE_INFINITY \ |
181 | | S390_TDC_NEGATIVE_QUIET_NAN \ | |
182 | | S390_TDC_NEGATIVE_SIGNALING_NAN ) | |
183 | ||
638e37c2 WG |
184 | #define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \ |
185 | | S390_TDC_NEGATIVE_INFINITY ) | |
9db1d521 | 186 | |
a5ba7b92 AK |
187 | /* This is used by float.h to define the float_t and double_t data |
188 | types. For historical reasons both are double on s390 what cannot | |
189 | be changed anymore. */ | |
190 | #define TARGET_FLT_EVAL_METHOD 1 | |
191 | ||
9db1d521 HP |
192 | /* Target machine storage layout. */ |
193 | ||
862a2d83 | 194 | /* Everything is big-endian. */ |
9db1d521 | 195 | #define BITS_BIG_ENDIAN 1 |
9db1d521 | 196 | #define BYTES_BIG_ENDIAN 1 |
9db1d521 HP |
197 | #define WORDS_BIG_ENDIAN 1 |
198 | ||
9602b6a1 AK |
199 | #define STACK_SIZE_MODE (Pmode) |
200 | ||
085261c8 AK |
201 | /* Vector arguments are left-justified when placed on the stack during |
202 | parameter passing. */ | |
203 | #define FUNCTION_ARG_PADDING(MODE, TYPE) \ | |
204 | (s390_function_arg_vector ((MODE), (TYPE)) \ | |
205 | ? upward \ | |
206 | : DEFAULT_FUNCTION_ARG_PADDING ((MODE), (TYPE))) | |
207 | ||
fe86047c | 208 | #ifndef IN_LIBGCC2 |
9602b6a1 AK |
209 | |
210 | /* Width of a word, in units (bytes). */ | |
211 | #define UNITS_PER_WORD (TARGET_ZARCH ? 8 : 4) | |
212 | ||
213 | /* Width of a pointer. To be used instead of UNITS_PER_WORD in | |
214 | ABI-relevant contexts. This always matches | |
215 | GET_MODE_SIZE (Pmode). */ | |
216 | #define UNITS_PER_LONG (TARGET_64BIT ? 8 : 4) | |
217 | #define MIN_UNITS_PER_WORD 4 | |
218 | #define MAX_BITS_PER_WORD 64 | |
219 | #else | |
220 | ||
221 | /* In libgcc, UNITS_PER_WORD has ABI-relevant effects, e.g. whether | |
222 | the library should export TImode functions or not. Thus, we have | |
223 | to redefine UNITS_PER_WORD depending on __s390x__ for libgcc. */ | |
224 | #ifdef __s390x__ | |
225 | #define UNITS_PER_WORD 8 | |
226 | #else | |
227 | #define UNITS_PER_WORD 4 | |
228 | #endif | |
fe86047c | 229 | #endif |
9602b6a1 AK |
230 | |
231 | /* Width of a pointer, in bits. */ | |
232 | #define POINTER_SIZE (TARGET_64BIT ? 64 : 32) | |
9db1d521 | 233 | |
9db1d521 | 234 | /* Allocation boundary (in *bits*) for storing arguments in argument list. */ |
9db1d521 HP |
235 | #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32) |
236 | ||
237 | /* Boundary (in *bits*) on which stack pointer should be aligned. */ | |
9db1d521 HP |
238 | #define STACK_BOUNDARY 64 |
239 | ||
240 | /* Allocation boundary (in *bits*) for the code of a function. */ | |
d0de9e13 | 241 | #define FUNCTION_BOUNDARY 64 |
9db1d521 HP |
242 | |
243 | /* There is no point aligning anything to a rounder boundary than this. */ | |
9db1d521 HP |
244 | #define BIGGEST_ALIGNMENT 64 |
245 | ||
246 | /* Alignment of field after `int : 0' in a structure. */ | |
9db1d521 HP |
247 | #define EMPTY_FIELD_BOUNDARY 32 |
248 | ||
f710504c | 249 | /* Alignment on even addresses for LARL instruction. */ |
9db1d521 | 250 | #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) |
df8a1d28 | 251 | #define DATA_ABI_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) |
9db1d521 | 252 | |
862a2d83 | 253 | /* Alignment is not required by the hardware. */ |
9db1d521 HP |
254 | #define STRICT_ALIGNMENT 0 |
255 | ||
862a2d83 UW |
256 | /* Mode of stack savearea. |
257 | FUNCTION is VOIDmode because calling convention maintains SP. | |
258 | BLOCK needs Pmode for SP. | |
259 | NONLOCAL needs twice Pmode to maintain both backchain and SP. */ | |
260 | #define STACK_SAVEAREA_MODE(LEVEL) \ | |
261 | (LEVEL == SAVE_FUNCTION ? VOIDmode \ | |
43ab026f | 262 | : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode) |
862a2d83 | 263 | |
9db1d521 | 264 | |
862a2d83 | 265 | /* Type layout. */ |
9db1d521 | 266 | |
862a2d83 UW |
267 | /* Sizes in bits of the source language data types. */ |
268 | #define SHORT_TYPE_SIZE 16 | |
269 | #define INT_TYPE_SIZE 32 | |
270 | #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) | |
862a2d83 UW |
271 | #define LONG_LONG_TYPE_SIZE 64 |
272 | #define FLOAT_TYPE_SIZE 32 | |
273 | #define DOUBLE_TYPE_SIZE 64 | |
f61a2c7d AK |
274 | #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) |
275 | ||
f61a2c7d AK |
276 | /* Work around target_flags dependency in ada/targtyps.c. */ |
277 | #define WIDEST_HARDWARE_FP_SIZE 64 | |
862a2d83 UW |
278 | |
279 | /* We use "unsigned char" as default. */ | |
280 | #define DEFAULT_SIGNED_CHAR 0 | |
281 | ||
282 | ||
283 | /* Register usage. */ | |
284 | ||
285 | /* We have 16 general purpose registers (registers 0-15), | |
286 | and 16 floating point registers (registers 16-31). | |
287 | (On non-IEEE machines, we have only 4 fp registers.) | |
c7453384 | 288 | |
862a2d83 UW |
289 | Amongst the general purpose registers, some are used |
290 | for specific purposes: | |
291 | GPR 11: Hard frame pointer (if needed) | |
292 | GPR 12: Global offset table pointer (if needed) | |
293 | GPR 13: Literal pool base register | |
294 | GPR 14: Return address register | |
295 | GPR 15: Stack pointer | |
c7453384 | 296 | |
c5aa1d12 | 297 | Registers 32-35 are 'fake' hard registers that do not |
862a2d83 UW |
298 | correspond to actual hardware: |
299 | Reg 32: Argument pointer | |
300 | Reg 33: Condition code | |
f4aa3848 | 301 | Reg 34: Frame pointer |
c5aa1d12 | 302 | Reg 35: Return address pointer |
862a2d83 | 303 | |
f4aa3848 | 304 | Registers 36 and 37 are mapped to access registers |
085261c8 AK |
305 | 0 and 1, used to implement thread-local storage. |
306 | ||
307 | Reg 38-53: Vector registers v16-v31 */ | |
c5aa1d12 | 308 | |
085261c8 | 309 | #define FIRST_PSEUDO_REGISTER 54 |
862a2d83 UW |
310 | |
311 | /* Standard register usage. */ | |
8e509cf9 UW |
312 | #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16) |
313 | #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16) | |
142cd70f | 314 | #define FP_REGNO_P(N) ((N) >= 16 && (N) < 32) |
8e509cf9 | 315 | #define CC_REGNO_P(N) ((N) == 33) |
a38e09bc | 316 | #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34 || (N) == 35) |
c5aa1d12 | 317 | #define ACCESS_REGNO_P(N) ((N) == 36 || (N) == 37) |
085261c8 AK |
318 | #define VECTOR_NOFP_REGNO_P(N) ((N) >= 38 && (N) <= 53) |
319 | #define VECTOR_REGNO_P(N) (FP_REGNO_P (N) || VECTOR_NOFP_REGNO_P (N)) | |
8e509cf9 UW |
320 | |
321 | #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) | |
322 | #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X))) | |
323 | #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) | |
324 | #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) | |
4888ec5d | 325 | #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X))) |
c5aa1d12 | 326 | #define ACCESS_REG_P(X) (REG_P (X) && ACCESS_REGNO_P (REGNO (X))) |
085261c8 AK |
327 | #define VECTOR_NOFP_REG_P(X) (REG_P (X) && VECTOR_NOFP_REGNO_P (REGNO (X))) |
328 | #define VECTOR_REG_P(X) (REG_P (X) && VECTOR_REGNO_P (REGNO (X))) | |
9db1d521 | 329 | |
862a2d83 | 330 | /* Set up fixed registers and calling convention: |
9db1d521 | 331 | |
862a2d83 UW |
332 | GPRs 0-5 are always call-clobbered, |
333 | GPRs 6-15 are always call-saved. | |
334 | GPR 12 is fixed if used as GOT pointer. | |
335 | GPR 13 is always fixed (as literal pool pointer). | |
545d16ff | 336 | GPR 14 is always fixed on S/390 machines (as return address). |
862a2d83 UW |
337 | GPR 15 is always fixed (as stack pointer). |
338 | The 'fake' hard registers are call-clobbered and fixed. | |
c5aa1d12 | 339 | The access registers are call-saved and fixed. |
9db1d521 | 340 | |
862a2d83 UW |
341 | On 31-bit, FPRs 18-19 are call-clobbered; |
342 | on 64-bit, FPRs 24-31 are call-clobbered. | |
085261c8 AK |
343 | The remaining FPRs are call-saved. |
344 | ||
345 | All non-FP vector registers are call-clobbered v16-v31. */ | |
9db1d521 HP |
346 | |
347 | #define FIXED_REGISTERS \ | |
348 | { 0, 0, 0, 0, \ | |
349 | 0, 0, 0, 0, \ | |
350 | 0, 0, 0, 0, \ | |
351 | 0, 1, 1, 1, \ | |
352 | 0, 0, 0, 0, \ | |
353 | 0, 0, 0, 0, \ | |
354 | 0, 0, 0, 0, \ | |
355 | 0, 0, 0, 0, \ | |
c5aa1d12 | 356 | 1, 1, 1, 1, \ |
085261c8 AK |
357 | 1, 1, \ |
358 | 0, 0, 0, 0, \ | |
359 | 0, 0, 0, 0, \ | |
360 | 0, 0, 0, 0, \ | |
361 | 0, 0, 0, 0 } | |
9db1d521 | 362 | |
9db1d521 HP |
363 | #define CALL_USED_REGISTERS \ |
364 | { 1, 1, 1, 1, \ | |
365 | 1, 1, 0, 0, \ | |
366 | 0, 0, 0, 0, \ | |
367 | 0, 1, 1, 1, \ | |
4023fb28 UW |
368 | 1, 1, 1, 1, \ |
369 | 1, 1, 1, 1, \ | |
370 | 1, 1, 1, 1, \ | |
371 | 1, 1, 1, 1, \ | |
c5aa1d12 | 372 | 1, 1, 1, 1, \ |
085261c8 AK |
373 | 1, 1, \ |
374 | 1, 1, 1, 1, \ | |
375 | 1, 1, 1, 1, \ | |
376 | 1, 1, 1, 1, \ | |
377 | 1, 1, 1, 1 } | |
4023fb28 | 378 | |
4023fb28 | 379 | #define CALL_REALLY_USED_REGISTERS \ |
085261c8 | 380 | { 1, 1, 1, 1, /* r0 - r15 */ \ |
9db1d521 | 381 | 1, 1, 0, 0, \ |
4023fb28 UW |
382 | 0, 0, 0, 0, \ |
383 | 0, 0, 0, 0, \ | |
085261c8 | 384 | 1, 1, 1, 1, /* f0 (16) - f15 (31) */ \ |
9db1d521 HP |
385 | 1, 1, 1, 1, \ |
386 | 1, 1, 1, 1, \ | |
387 | 1, 1, 1, 1, \ | |
085261c8 AK |
388 | 1, 1, 1, 1, /* arg, cc, fp, ret addr */ \ |
389 | 0, 0, /* a0 (36), a1 (37) */ \ | |
390 | 1, 1, 1, 1, /* v16 (38) - v23 (45) */ \ | |
c5aa1d12 | 391 | 1, 1, 1, 1, \ |
085261c8 AK |
392 | 1, 1, 1, 1, /* v24 (46) - v31 (53) */ \ |
393 | 1, 1, 1, 1 } | |
9db1d521 | 394 | |
862a2d83 | 395 | /* Preferred register allocation order. */ |
085261c8 AK |
396 | #define REG_ALLOC_ORDER \ |
397 | { 1, 2, 3, 4, 5, 0, 12, 11, 10, 9, 8, 7, 6, 14, 13, \ | |
398 | 16, 17, 18, 19, 20, 21, 22, 23, \ | |
399 | 24, 25, 26, 27, 28, 29, 30, 31, \ | |
400 | 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, \ | |
401 | 15, 32, 33, 34, 35, 36, 37 } | |
9db1d521 | 402 | |
9db1d521 | 403 | |
862a2d83 | 404 | /* Fitting values into registers. */ |
c7453384 | 405 | |
862a2d83 UW |
406 | /* Integer modes <= word size fit into any GPR. |
407 | Integer modes > word size fit into successive GPRs, starting with | |
408 | an even-numbered register. | |
409 | SImode and DImode fit into FPRs as well. | |
c7453384 | 410 | |
862a2d83 UW |
411 | Floating point modes <= word size fit into any FPR or GPR. |
412 | Floating point modes > word size (i.e. DFmode on 32-bit) fit | |
413 | into any FPR, or an even-odd GPR pair. | |
f61a2c7d | 414 | TFmode fits only into an even-odd FPR pair. |
c7453384 | 415 | |
862a2d83 UW |
416 | Complex floating point modes fit either into two FPRs, or into |
417 | successive GPRs (again starting with an even number). | |
f61a2c7d | 418 | TCmode fits only into two successive even-odd FPR pairs. |
c7453384 | 419 | |
862a2d83 | 420 | Condition code modes fit only into the CC register. */ |
9db1d521 | 421 | |
74aa8b4b AK |
422 | /* Because all registers in a class have the same size HARD_REGNO_NREGS |
423 | is equivalent to CLASS_MAX_NREGS. */ | |
9db1d521 | 424 | #define HARD_REGNO_NREGS(REGNO, MODE) \ |
74aa8b4b AK |
425 | s390_class_max_nregs (REGNO_REG_CLASS (REGNO), (MODE)) |
426 | ||
427 | #define HARD_REGNO_MODE_OK(REGNO, MODE) \ | |
428 | s390_hard_regno_mode_ok ((REGNO), (MODE)) | |
429 | ||
430 | #define HARD_REGNO_RENAME_OK(FROM, TO) \ | |
7633f08e UW |
431 | s390_hard_regno_rename_ok (FROM, TO) |
432 | ||
9db1d521 HP |
433 | #define MODES_TIEABLE_P(MODE1, MODE2) \ |
434 | (((MODE1) == SFmode || (MODE1) == DFmode) \ | |
435 | == ((MODE2) == SFmode || (MODE2) == DFmode)) | |
436 | ||
9602b6a1 AK |
437 | /* When generating code that runs in z/Architecture mode, |
438 | but conforms to the 31-bit ABI, GPRs can hold 8 bytes; | |
439 | the ABI guarantees only that the lower 4 bytes are | |
440 | saved across calls, however. */ | |
085261c8 AK |
441 | #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ |
442 | ((!TARGET_64BIT && TARGET_ZARCH \ | |
443 | && GET_MODE_SIZE (MODE) > 4 \ | |
444 | && (((REGNO) >= 6 && (REGNO) <= 15) || (REGNO) == 32)) \ | |
445 | || (TARGET_VX \ | |
446 | && GET_MODE_SIZE (MODE) > 8 \ | |
447 | && (((TARGET_64BIT && (REGNO) >= 24 && (REGNO) <= 31)) \ | |
448 | || (!TARGET_64BIT && ((REGNO) == 18 || (REGNO) == 19))))) | |
9602b6a1 | 449 | |
862a2d83 UW |
450 | /* Maximum number of registers to represent a value of mode MODE |
451 | in a register of class CLASS. */ | |
452 | #define CLASS_MAX_NREGS(CLASS, MODE) \ | |
74aa8b4b | 453 | s390_class_max_nregs ((CLASS), (MODE)) |
4023fb28 | 454 | |
f61a2c7d | 455 | #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ |
085261c8 | 456 | s390_cannot_change_mode_class ((FROM), (TO), (CLASS)) |
9db1d521 | 457 | |
862a2d83 | 458 | /* Register classes. */ |
c7453384 | 459 | |
862a2d83 UW |
460 | /* We use the following register classes: |
461 | GENERAL_REGS All general purpose registers | |
462 | ADDR_REGS All general purpose registers except %r0 | |
463 | (These registers can be used in address generation) | |
464 | FP_REGS All floating point registers | |
c5aa1d12 UW |
465 | CC_REGS The condition code register |
466 | ACCESS_REGS The access registers | |
c7453384 | 467 | |
862a2d83 UW |
468 | GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS |
469 | ADDR_FP_REGS Union of ADDR_REGS and FP_REGS | |
c5aa1d12 UW |
470 | GENERAL_CC_REGS Union of GENERAL_REGS and CC_REGS |
471 | ADDR_CC_REGS Union of ADDR_REGS and CC_REGS | |
c7453384 | 472 | |
862a2d83 UW |
473 | NO_REGS No registers |
474 | ALL_REGS All registers | |
c7453384 | 475 | |
862a2d83 | 476 | Note that the 'fake' frame pointer and argument pointer registers |
c5aa1d12 | 477 | are included amongst the address registers here. */ |
9db1d521 HP |
478 | |
479 | enum reg_class | |
480 | { | |
c5aa1d12 | 481 | NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS, |
f4aa3848 | 482 | ADDR_CC_REGS, GENERAL_CC_REGS, |
4023fb28 | 483 | FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, |
085261c8 | 484 | VEC_REGS, ADDR_VEC_REGS, GENERAL_VEC_REGS, |
4023fb28 | 485 | ALL_REGS, LIM_REG_CLASSES |
9db1d521 | 486 | }; |
9db1d521 HP |
487 | #define N_REG_CLASSES (int) LIM_REG_CLASSES |
488 | ||
c5aa1d12 UW |
489 | #define REG_CLASS_NAMES \ |
490 | { "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS", \ | |
491 | "ADDR_CC_REGS", "GENERAL_CC_REGS", \ | |
085261c8 AK |
492 | "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", \ |
493 | "VEC_REGS", "ADDR_VEC_REGS", "GENERAL_VEC_REGS", \ | |
494 | "ALL_REGS" } | |
9db1d521 | 495 | |
862a2d83 | 496 | /* Class -> register mapping. */ |
085261c8 AK |
497 | #define REG_CLASS_CONTENTS \ |
498 | { \ | |
9db1d521 | 499 | { 0x00000000, 0x00000000 }, /* NO_REGS */ \ |
9dc62c00 | 500 | { 0x00000000, 0x00000002 }, /* CC_REGS */ \ |
a38e09bc AK |
501 | { 0x0000fffe, 0x0000000d }, /* ADDR_REGS */ \ |
502 | { 0x0000ffff, 0x0000000d }, /* GENERAL_REGS */ \ | |
c5aa1d12 | 503 | { 0x00000000, 0x00000030 }, /* ACCESS_REGS */ \ |
9dc62c00 AK |
504 | { 0x0000fffe, 0x0000000f }, /* ADDR_CC_REGS */ \ |
505 | { 0x0000ffff, 0x0000000f }, /* GENERAL_CC_REGS */ \ | |
9db1d521 | 506 | { 0xffff0000, 0x00000000 }, /* FP_REGS */ \ |
a38e09bc AK |
507 | { 0xfffffffe, 0x0000000d }, /* ADDR_FP_REGS */ \ |
508 | { 0xffffffff, 0x0000000d }, /* GENERAL_FP_REGS */ \ | |
085261c8 AK |
509 | { 0xffff0000, 0x003fffc0 }, /* VEC_REGS */ \ |
510 | { 0xfffffffe, 0x003fffcd }, /* ADDR_VEC_REGS */ \ | |
511 | { 0xffffffff, 0x003fffcd }, /* GENERAL_VEC_REGS */ \ | |
512 | { 0xffffffff, 0x003fffff }, /* ALL_REGS */ \ | |
9db1d521 HP |
513 | } |
514 | ||
058e97ec VM |
515 | /* In some case register allocation order is not enough for IRA to |
516 | generate a good code. The following macro (if defined) increases | |
517 | cost of REGNO for a pseudo approximately by pseudo usage frequency | |
518 | multiplied by the macro value. | |
519 | ||
520 | We avoid usage of BASE_REGNUM by nonzero macro value because the | |
521 | reload can decide not to use the hard register because some | |
522 | constant was forced to be in memory. */ | |
523 | #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) \ | |
dba0dd68 | 524 | (regno != BASE_REGNUM ? 0.0 : 0.5) |
058e97ec | 525 | |
862a2d83 UW |
526 | /* Register -> class mapping. */ |
527 | extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; | |
528 | #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) | |
9db1d521 | 529 | |
862a2d83 UW |
530 | /* ADDR_REGS can be used as base or index register. */ |
531 | #define INDEX_REG_CLASS ADDR_REGS | |
532 | #define BASE_REG_CLASS ADDR_REGS | |
9db1d521 | 533 | |
862a2d83 UW |
534 | /* Check whether REGNO is a hard register of the suitable class |
535 | or a pseudo register currently allocated to one such. */ | |
536 | #define REGNO_OK_FOR_INDEX_P(REGNO) \ | |
537 | (((REGNO) < FIRST_PSEUDO_REGISTER \ | |
93fa8428 AK |
538 | && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \ |
539 | || ADDR_REGNO_P (reg_renumber[REGNO])) | |
862a2d83 | 540 | #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) |
9db1d521 | 541 | |
9db1d521 | 542 | |
085261c8 AK |
543 | /* We need secondary memory to move data between GPRs and FPRs. |
544 | ||
545 | - With DFP the ldgr lgdr instructions are available. Due to the | |
546 | different alignment we cannot use them for SFmode. For 31 bit a | |
547 | 64 bit value in GPR would be a register pair so here we still | |
548 | need to go via memory. | |
549 | ||
550 | - With z13 we can do the SF/SImode moves with vlgvf. Due to the | |
551 | overlapping of FPRs and VRs we still disallow TF/TD modes to be | |
552 | in full VRs so as before also on z13 we do these moves via | |
553 | memory. | |
554 | ||
555 | FIXME: Should we try splitting it into two vlgvg's/vlvg's instead? */ | |
556 | #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ | |
557 | (((reg_classes_intersect_p (CLASS1, VEC_REGS) \ | |
558 | && reg_classes_intersect_p (CLASS2, GENERAL_REGS)) \ | |
559 | || (reg_classes_intersect_p (CLASS1, GENERAL_REGS) \ | |
560 | && reg_classes_intersect_p (CLASS2, VEC_REGS))) \ | |
561 | && (!TARGET_DFP || !TARGET_64BIT || GET_MODE_SIZE (MODE) != 8) \ | |
562 | && (!TARGET_VX || (SCALAR_FLOAT_MODE_P (MODE) \ | |
563 | && GET_MODE_SIZE (MODE) > 8))) | |
862a2d83 UW |
564 | |
565 | /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit | |
566 | because the movsi and movsf patterns don't handle r/f moves. */ | |
567 | #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ | |
568 | (GET_MODE_BITSIZE (MODE) < 32 \ | |
569 | ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ | |
570 | : MODE) | |
571 | ||
572 | ||
862a2d83 | 573 | /* Stack layout and calling conventions. */ |
c7453384 | 574 | |
862a2d83 UW |
575 | /* Our stack grows from higher to lower addresses. However, local variables |
576 | are accessed by positive offsets, and function arguments are stored at | |
577 | increasing addresses. */ | |
62f9f30b | 578 | #define STACK_GROWS_DOWNWARD 1 |
63296cb1 | 579 | #define FRAME_GROWS_DOWNWARD 1 |
862a2d83 | 580 | /* #undef ARGS_GROW_DOWNWARD */ |
9db1d521 | 581 | |
862a2d83 UW |
582 | /* The basic stack layout looks like this: the stack pointer points |
583 | to the register save area for called functions. Above that area | |
584 | is the location to place outgoing arguments. Above those follow | |
585 | dynamic allocations (alloca), and finally the local variables. */ | |
9db1d521 | 586 | |
862a2d83 UW |
587 | /* Offset from stack-pointer to first location of outgoing args. */ |
588 | #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96) | |
9db1d521 | 589 | |
862a2d83 | 590 | /* Offset within stack frame to start allocating local variables at. */ |
63296cb1 | 591 | #define STARTING_FRAME_OFFSET 0 |
9db1d521 | 592 | |
862a2d83 UW |
593 | /* Offset from the stack pointer register to an item dynamically |
594 | allocated on the stack, e.g., by `alloca'. */ | |
63296cb1 | 595 | #define STACK_DYNAMIC_OFFSET(FUNDECL) \ |
38173d38 | 596 | (STACK_POINTER_OFFSET + crtl->outgoing_args_size) |
9db1d521 | 597 | |
862a2d83 UW |
598 | /* Offset of first parameter from the argument pointer register value. |
599 | We have a fake argument pointer register that points directly to | |
600 | the argument area. */ | |
601 | #define FIRST_PARM_OFFSET(FNDECL) 0 | |
9db1d521 | 602 | |
f4aa3848 | 603 | /* Defining this macro makes __builtin_frame_address(0) and |
c6d01079 AK |
604 | __builtin_return_address(0) work with -fomit-frame-pointer. */ |
605 | #define INITIAL_FRAME_ADDRESS_RTX \ | |
0a81f074 | 606 | (plus_constant (Pmode, arg_pointer_rtx, -STACK_POINTER_OFFSET)) |
c6d01079 | 607 | |
c7453384 | 608 | /* The return address of the current frame is retrieved |
4023fb28 UW |
609 | from the initial value of register RETURN_REGNUM. |
610 | For frames farther back, we use the stack slot where | |
611 | the corresponding RETURN_REGNUM register was saved. */ | |
c6d01079 AK |
612 | #define DYNAMIC_CHAIN_ADDRESS(FRAME) \ |
613 | (TARGET_PACKED_STACK ? \ | |
0a81f074 RS |
614 | plus_constant (Pmode, (FRAME), \ |
615 | STACK_POINTER_OFFSET - UNITS_PER_LONG) : (FRAME)) | |
4023fb28 | 616 | |
78791a80 AK |
617 | /* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of |
618 | builtin_frame_address. Otherwise arg pointer - | |
619 | STACK_POINTER_OFFSET would be returned for | |
620 | __builtin_frame_address(0) what might result in an address pointing | |
621 | somewhere into the middle of the local variables since the packed | |
622 | stack layout generally does not need all the bytes in the register | |
623 | save area. */ | |
624 | #define FRAME_ADDR_RTX(FRAME) \ | |
625 | DYNAMIC_CHAIN_ADDRESS ((FRAME)) | |
626 | ||
c6d01079 | 627 | #define RETURN_ADDR_RTX(COUNT, FRAME) \ |
5d4d885c | 628 | s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME))) |
9db1d521 | 629 | |
862a2d83 | 630 | /* In 31-bit mode, we need to mask off the high bit of return addresses. */ |
a556fd39 | 631 | #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff)) |
9db1d521 | 632 | |
4023fb28 | 633 | |
862a2d83 | 634 | /* Exception handling. */ |
c7453384 | 635 | |
862a2d83 UW |
636 | /* Describe calling conventions for DWARF-2 exception handling. */ |
637 | #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM) | |
4023fb28 | 638 | #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET |
9db1d521 HP |
639 | #define DWARF_FRAME_RETURN_COLUMN 14 |
640 | ||
641 | /* Describe how we implement __builtin_eh_return. */ | |
642 | #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM) | |
a38e09bc | 643 | #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx) |
f4aa3848 | 644 | |
18789f4e UW |
645 | /* Select a format to encode pointers in exception handling data. */ |
646 | #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ | |
647 | (flag_pic \ | |
648 | ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ | |
649 | : DW_EH_PE_absptr) | |
650 | ||
9602b6a1 AK |
651 | /* Register save slot alignment. */ |
652 | #define DWARF_CIE_DATA_ALIGNMENT (-UNITS_PER_LONG) | |
653 | ||
f276b762 AK |
654 | /* Let the assembler generate debug line info. */ |
655 | #define DWARF2_ASM_LINE_DEBUG_INFO 1 | |
656 | ||
085261c8 AK |
657 | /* Define the dwarf register mapping. |
658 | v16-v31 -> 68-83 | |
659 | rX -> X otherwise */ | |
660 | #define DBX_REGISTER_NUMBER(regno) \ | |
661 | ((regno >= 38 && regno <= 53) ? regno + 30 : regno) | |
9db1d521 | 662 | |
862a2d83 | 663 | /* Frame registers. */ |
9db1d521 | 664 | |
862a2d83 UW |
665 | #define STACK_POINTER_REGNUM 15 |
666 | #define FRAME_POINTER_REGNUM 34 | |
667 | #define HARD_FRAME_POINTER_REGNUM 11 | |
668 | #define ARG_POINTER_REGNUM 32 | |
a38e09bc | 669 | #define RETURN_ADDRESS_POINTER_REGNUM 35 |
9db1d521 | 670 | |
c7453384 EC |
671 | /* The static chain must be call-clobbered, but not used for |
672 | function argument passing. As register 1 is clobbered by | |
862a2d83 UW |
673 | the trampoline code, we only have one option. */ |
674 | #define STATIC_CHAIN_REGNUM 0 | |
9db1d521 | 675 | |
862a2d83 UW |
676 | /* Number of hardware registers that go into the DWARF-2 unwind info. |
677 | To avoid ABI incompatibility, this number must not change even as | |
678 | 'fake' hard registers are added or removed. */ | |
679 | #define DWARF_FRAME_REGISTERS 34 | |
9db1d521 | 680 | |
9db1d521 | 681 | |
862a2d83 | 682 | /* Frame pointer and argument pointer elimination. */ |
9db1d521 | 683 | |
7633f08e UW |
684 | #define ELIMINABLE_REGS \ |
685 | {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
686 | { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
687 | { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
688 | { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
689 | { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ | |
690 | { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ | |
691 | { BASE_REGNUM, BASE_REGNUM }} | |
9db1d521 | 692 | |
91086990 UW |
693 | #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ |
694 | (OFFSET) = s390_initial_elimination_offset ((FROM), (TO)) | |
9db1d521 | 695 | |
9db1d521 | 696 | |
862a2d83 | 697 | /* Stack arguments. */ |
c7453384 | 698 | |
862a2d83 UW |
699 | /* We need current_function_outgoing_args to be valid. */ |
700 | #define ACCUMULATE_OUTGOING_ARGS 1 | |
9db1d521 | 701 | |
9db1d521 | 702 | |
862a2d83 | 703 | /* Register arguments. */ |
c7453384 | 704 | |
9db1d521 HP |
705 | typedef struct s390_arg_structure |
706 | { | |
707 | int gprs; /* gpr so far */ | |
708 | int fprs; /* fpr so far */ | |
085261c8 | 709 | int vrs; /* vr so far */ |
9db1d521 HP |
710 | } |
711 | CUMULATIVE_ARGS; | |
712 | ||
07711f53 | 713 | #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \ |
085261c8 AK |
714 | ((CUM).gprs=0, (CUM).fprs=0, (CUM).vrs=0) |
715 | ||
716 | #define FIRST_VEC_ARG_REGNO 46 | |
717 | #define LAST_VEC_ARG_REGNO 53 | |
9db1d521 | 718 | |
96e2afa8 AK |
719 | /* Arguments can be placed in general registers 2 to 6, or in floating |
720 | point registers 0 and 2 for 31 bit and fprs 0, 2, 4 and 6 for 64 | |
721 | bit. */ | |
085261c8 AK |
722 | #define FUNCTION_ARG_REGNO_P(N) \ |
723 | (((N) >=2 && (N) < 7) || (N) == 16 || (N) == 17 \ | |
724 | || (TARGET_64BIT && ((N) == 18 || (N) == 19)) \ | |
725 | || (TARGET_VX && ((N) >= FIRST_VEC_ARG_REGNO && (N) <= LAST_VEC_ARG_REGNO))) | |
9db1d521 | 726 | |
9db1d521 | 727 | |
085261c8 AK |
728 | /* Only gpr 2, fpr 0, and v24 are ever used as return registers. */ |
729 | #define FUNCTION_VALUE_REGNO_P(N) \ | |
730 | ((N) == 2 || (N) == 16 \ | |
731 | || (TARGET_VX && (N) == FIRST_VEC_ARG_REGNO)) | |
9db1d521 | 732 | |
9db1d521 | 733 | |
862a2d83 | 734 | /* Function entry and exit. */ |
c7453384 | 735 | |
862a2d83 UW |
736 | /* When returning from a function, the stack pointer does not matter. */ |
737 | #define EXIT_IGNORE_STACK 1 | |
9db1d521 | 738 | |
9db1d521 | 739 | |
862a2d83 | 740 | /* Profiling. */ |
9db1d521 HP |
741 | |
742 | #define FUNCTION_PROFILER(FILE, LABELNO) \ | |
862a2d83 | 743 | s390_function_profiler ((FILE), ((LABELNO))) |
9db1d521 | 744 | |
c52a375d | 745 | #define PROFILE_BEFORE_PROLOGUE 1 |
9db1d521 | 746 | |
9db1d521 | 747 | |
862a2d83 | 748 | /* Trampolines for nested functions. */ |
9db1d521 | 749 | |
b81ecf6f RH |
750 | #define TRAMPOLINE_SIZE (TARGET_64BIT ? 32 : 16) |
751 | #define TRAMPOLINE_ALIGNMENT BITS_PER_WORD | |
9db1d521 | 752 | |
862a2d83 | 753 | /* Addressing modes, and classification of registers for them. */ |
9db1d521 | 754 | |
862a2d83 UW |
755 | /* Recognize any constant value that is a valid address. */ |
756 | #define CONSTANT_ADDRESS_P(X) 0 | |
9db1d521 | 757 | |
862a2d83 UW |
758 | /* Maximum number of registers that can appear in a valid memory address. */ |
759 | #define MAX_REGS_PER_ADDRESS 2 | |
9db1d521 | 760 | |
963fc8d0 | 761 | /* This definition replaces the formerly used 'm' constraint with a |
c6c3dba9 PB |
762 | different constraint letter in order to avoid changing semantics of |
763 | the 'm' constraint when accepting new address formats in | |
764 | TARGET_LEGITIMATE_ADDRESS_P. The constraint letter defined here | |
765 | must not be used in insn definitions or inline assemblies. */ | |
963fc8d0 AK |
766 | #define TARGET_MEM_CONSTRAINT 'e' |
767 | ||
0b540f12 UW |
768 | /* Try a machine-dependent way of reloading an illegitimate address |
769 | operand. If we find one, push the reload and jump to WIN. This | |
770 | macro is used in only one place: `find_reloads_address' in reload.c. */ | |
771 | #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ | |
772 | do { \ | |
0a2aaacc KG |
773 | rtx new_rtx = legitimize_reload_address (AD, MODE, OPNUM, (int)(TYPE)); \ |
774 | if (new_rtx) \ | |
0b540f12 | 775 | { \ |
0a2aaacc | 776 | (AD) = new_rtx; \ |
0b540f12 UW |
777 | goto WIN; \ |
778 | } \ | |
779 | } while (0) | |
780 | ||
862a2d83 UW |
781 | /* Helper macro for s390.c and s390.md to check for symbolic constants. */ |
782 | #define SYMBOLIC_CONST(X) \ | |
783 | (GET_CODE (X) == SYMBOL_REF \ | |
784 | || GET_CODE (X) == LABEL_REF \ | |
785 | || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) | |
9db1d521 | 786 | |
fd3cd001 UW |
787 | #define TLS_SYMBOLIC_CONST(X) \ |
788 | ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \ | |
789 | || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X))) | |
790 | ||
9db1d521 | 791 | |
862a2d83 | 792 | /* Condition codes. */ |
9db1d521 | 793 | |
862a2d83 UW |
794 | /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, |
795 | return the mode to be used for the comparison. */ | |
796 | #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y)) | |
c7453384 | 797 | |
862a2d83 | 798 | /* Relative costs of operations. */ |
9db1d521 | 799 | |
9db1d521 HP |
800 | /* A C expression for the cost of a branch instruction. A value of 1 |
801 | is the default; other values are interpreted relative to that. */ | |
3d427cc1 | 802 | #define BRANCH_COST(speed_p, predictable_p) s390_branch_cost |
9db1d521 | 803 | |
862a2d83 UW |
804 | /* Nonzero if access to memory by bytes is slow and undesirable. */ |
805 | #define SLOW_BYTE_ACCESS 1 | |
806 | ||
c5443745 | 807 | /* An integer expression for the size in bits of the largest integer machine |
f4aa3848 | 808 | mode that should actually be used. We allow pairs of registers. */ |
c5443745 UW |
809 | #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) |
810 | ||
862a2d83 | 811 | /* The maximum number of bytes that a single instruction can move quickly |
ff482c8d | 812 | between memory and registers or between two memory locations. */ |
9602b6a1 AK |
813 | #define MOVE_MAX (TARGET_ZARCH ? 16 : 8) |
814 | #define MOVE_MAX_PIECES (TARGET_ZARCH ? 8 : 4) | |
862a2d83 | 815 | #define MAX_MOVE_MAX 16 |
9db1d521 | 816 | |
862a2d83 | 817 | /* Don't perform CSE on function addresses. */ |
1e8552c2 | 818 | #define NO_FUNCTION_CSE 1 |
862a2d83 | 819 | |
5f1b2ee6 AK |
820 | /* This value is used in tree-sra to decide whether it might benefical |
821 | to split a struct move into several word-size moves. For S/390 | |
822 | only small values make sense here since struct moves are relatively | |
073a8998 | 823 | cheap thanks to mvc so the small default value chosen for archs |
5f1b2ee6 AK |
824 | with memmove patterns should be ok. But this value is multiplied |
825 | in tree-sra with UNITS_PER_WORD to make a decision so we adjust it | |
826 | here to compensate for that factor since mvc costs exactly the same | |
827 | on 31 and 64 bit. */ | |
e04ad03d | 828 | #define MOVE_RATIO(speed) (TARGET_64BIT? 2 : 4) |
5f1b2ee6 | 829 | |
862a2d83 UW |
830 | |
831 | /* Sections. */ | |
832 | ||
833 | /* Output before read-only data. */ | |
834 | #define TEXT_SECTION_ASM_OP ".text" | |
835 | ||
836 | /* Output before writable (initialized) data. */ | |
837 | #define DATA_SECTION_ASM_OP ".data" | |
838 | ||
839 | /* Output before writable (uninitialized) data. */ | |
840 | #define BSS_SECTION_ASM_OP ".bss" | |
841 | ||
842 | /* S/390 constant pool breaks the devices in crtstuff.c to control section | |
843 | in where code resides. We have to write it as asm code. */ | |
844 | #ifndef __s390x__ | |
845 | #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ | |
846 | asm (SECTION_OP "\n\ | |
847 | bras\t%r2,1f\n\ | |
848 | 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\ | |
849 | 1: l\t%r3,0(%r2)\n\ | |
850 | bas\t%r14,0(%r3,%r2)\n\ | |
851 | .previous"); | |
852 | #endif | |
63a1ff86 | 853 | |
862a2d83 UW |
854 | |
855 | /* Position independent code. */ | |
856 | ||
862a2d83 UW |
857 | #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM) |
858 | ||
859 | #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) | |
63a1ff86 UW |
860 | |
861 | ||
862 | /* Assembler file format. */ | |
863 | ||
864 | /* Character to start a comment. */ | |
865 | #define ASM_COMMENT_START "#" | |
866 | ||
867 | /* Declare an uninitialized external linkage data object. */ | |
868 | #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ | |
869 | asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) | |
870 | ||
871 | /* Globalizing directive for a label. */ | |
872 | #define GLOBAL_ASM_OP ".globl " | |
873 | ||
874 | /* Advance the location counter to a multiple of 2**LOG bytes. */ | |
875 | #define ASM_OUTPUT_ALIGN(FILE, LOG) \ | |
876 | if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG)) | |
877 | ||
878 | /* Advance the location counter by SIZE bytes. */ | |
879 | #define ASM_OUTPUT_SKIP(FILE, SIZE) \ | |
16998094 | 880 | fprintf ((FILE), "\t.set\t.,.+" HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) |
63a1ff86 | 881 | |
63a1ff86 UW |
882 | /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */ |
883 | #define LOCAL_LABEL_PREFIX "." | |
9db1d521 | 884 | |
5d304e47 AK |
885 | #define LABEL_ALIGN(LABEL) \ |
886 | s390_label_align (LABEL) | |
887 | ||
9db1d521 HP |
888 | /* How to refer to registers in assembler output. This sequence is |
889 | indexed by compiler's hard-register-number (see above). */ | |
9db1d521 | 890 | #define REGISTER_NAMES \ |
085261c8 AK |
891 | { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ |
892 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ | |
893 | "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \ | |
894 | "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \ | |
895 | "%ap", "%cc", "%fp", "%rp", "%a0", "%a1", \ | |
896 | "%v16", "%v18", "%v20", "%v22", "%v17", "%v19", "%v21", "%v23", \ | |
897 | "%v24", "%v26", "%v28", "%v30", "%v25", "%v27", "%v29", "%v31" \ | |
898 | } | |
899 | ||
900 | #define ADDITIONAL_REGISTER_NAMES \ | |
901 | { { "v0", 16 }, { "v2", 17 }, { "v4", 18 }, { "v6", 19 }, \ | |
902 | { "v1", 20 }, { "v3", 21 }, { "v5", 22 }, { "v7", 23 }, \ | |
903 | { "v8", 24 }, { "v10", 25 }, { "v12", 26 }, { "v14", 27 }, \ | |
904 | { "v9", 28 }, { "v11", 29 }, { "v13", 30 }, { "v15", 31 } }; | |
9db1d521 | 905 | |
63a1ff86 | 906 | /* Print operand X (an rtx) in assembler syntax to file FILE. */ |
9db1d521 | 907 | #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) |
9db1d521 HP |
908 | #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) |
909 | ||
63a1ff86 UW |
910 | /* Output an element of a case-vector that is absolute. */ |
911 | #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ | |
912 | do { \ | |
913 | char buf[32]; \ | |
9602b6a1 | 914 | fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ |
63a1ff86 UW |
915 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ |
916 | assemble_name ((FILE), buf); \ | |
917 | fputc ('\n', (FILE)); \ | |
918 | } while (0) | |
919 | ||
920 | /* Output an element of a case-vector that is relative. */ | |
921 | #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ | |
922 | do { \ | |
923 | char buf[32]; \ | |
9602b6a1 | 924 | fputs (integer_asm_op (UNITS_PER_LONG, TRUE), (FILE)); \ |
63a1ff86 UW |
925 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ |
926 | assemble_name ((FILE), buf); \ | |
927 | fputc ('-', (FILE)); \ | |
928 | ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \ | |
929 | assemble_name ((FILE), buf); \ | |
930 | fputc ('\n', (FILE)); \ | |
931 | } while (0) | |
932 | ||
177bc204 RS |
933 | /* Mark the return register as used by the epilogue so that we can |
934 | use it in unadorned (return) and (simple_return) instructions. */ | |
935 | #define EPILOGUE_USES(REGNO) ((REGNO) == RETURN_REGNUM) | |
936 | ||
d0de9e13 DV |
937 | #undef ASM_OUTPUT_FUNCTION_LABEL |
938 | #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ | |
939 | s390_asm_output_function_label (FILE, NAME, DECL) | |
9db1d521 | 940 | |
862a2d83 UW |
941 | /* Miscellaneous parameters. */ |
942 | ||
862a2d83 UW |
943 | /* Specify the machine mode that this machine uses for the index in the |
944 | tablejump instruction. */ | |
945 | #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) | |
946 | ||
862a2d83 UW |
947 | /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits |
948 | is done just by pretending it is already truncated. */ | |
949 | #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 | |
950 | ||
951 | /* Specify the machine mode that pointers have. | |
952 | After generation of rtl, the compiler makes no further distinction | |
953 | between pointers and any other objects of this machine mode. */ | |
ef4bddc2 | 954 | #define Pmode ((machine_mode) (TARGET_64BIT ? DImode : SImode)) |
862a2d83 | 955 | |
c7453384 EC |
956 | /* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */ |
957 | #define POINTERS_EXTEND_UNSIGNED -1 | |
958 | ||
862a2d83 UW |
959 | /* A function address in a call instruction is a byte address (for |
960 | indexing purposes) so give the MEM rtx a byte's mode. */ | |
961 | #define FUNCTION_MODE QImode | |
962 | ||
ec24698e UW |
963 | /* Specify the value which is used when clz operand is zero. */ |
964 | #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1) | |
965 | ||
0bfc3f69 | 966 | /* Machine-specific symbol_ref flags. */ |
963fc8d0 AK |
967 | #define SYMBOL_FLAG_ALIGN1 (SYMBOL_FLAG_MACH_DEP << 0) |
968 | #define SYMBOL_REF_ALIGN1_P(X) \ | |
969 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN1)) | |
970 | #define SYMBOL_FLAG_NOT_NATURALLY_ALIGNED (SYMBOL_FLAG_MACH_DEP << 1) | |
971 | #define SYMBOL_REF_NOT_NATURALLY_ALIGNED_P(X) \ | |
972 | ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_NOT_NATURALLY_ALIGNED)) | |
0bfc3f69 | 973 | |
085261c8 AK |
974 | /* Check whether integer displacement is in range for a short displacement. */ |
975 | #define SHORT_DISP_IN_RANGE(d) ((d) >= 0 && (d) <= 4095) | |
976 | ||
0bfc3f69 AS |
977 | /* Check whether integer displacement is in range. */ |
978 | #define DISP_IN_RANGE(d) \ | |
979 | (TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \ | |
085261c8 | 980 | : SHORT_DISP_IN_RANGE(d)) |
0bfc3f69 | 981 | |
24a235c8 CB |
982 | /* Reads can reuse write prefetches, used by tree-ssa-prefetch-loops.c. */ |
983 | #define READ_CAN_USE_WRITE_PREFETCH 1 | |
677f3fa8 JM |
984 | |
985 | extern const int processor_flags_table[]; | |
085261c8 AK |
986 | |
987 | /* The truth element value for vector comparisons. Our instructions | |
988 | always generate -1 in that case. */ | |
989 | #define VECTOR_STORE_FLAG_VALUE(MODE) CONSTM1_RTX (GET_MODE_INNER (MODE)) | |
990 | ||
3af82a61 AK |
991 | /* Target pragma. */ |
992 | ||
993 | /* resolve_overloaded_builtin can not be defined the normal way since | |
994 | it is defined in code which technically belongs to the | |
995 | front-end. */ | |
996 | #define REGISTER_TARGET_PRAGMAS() \ | |
997 | do { \ | |
998 | s390_register_target_pragmas (); \ | |
999 | } while (0) | |
1000 | ||
085261c8 | 1001 | #endif /* S390_H */ |