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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
9c3c3dcc | 2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005 |
283334f0 | 3 | ;; Free Software Foundation, Inc. |
9db1d521 | 4 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
f314b9b1 | 5 | ;; Ulrich Weigand (uweigand@de.ibm.com). |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
11 | ;; Software Foundation; either version 2, or (at your option) any later | |
12 | ;; version. | |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
58add37a | 20 | ;; along with GCC; see the file COPYING. If not, write to the Free |
39d14dda KC |
21 | ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA |
22 | ;; 02110-1301, USA. | |
9db1d521 HP |
23 | |
24 | ;; | |
25 | ;; Special constraints for s/390 machine description: | |
26 | ;; | |
27 | ;; a -- Any address register from 1 to 15. | |
9dc62c00 | 28 | ;; c -- Condition code register 33. |
9db1d521 | 29 | ;; d -- Any register from 0 to 15. |
09366c43 AS |
30 | ;; f -- Floating point registers. |
31 | ;; t -- Access registers 36 and 37. | |
d096725d | 32 | ;; G -- Const double zero operand |
9db1d521 HP |
33 | ;; I -- An 8-bit constant (0..255). |
34 | ;; J -- A 12-bit constant (0..4095). | |
35 | ;; K -- A 16-bit constant (-32768..32767). | |
2f7e5a0d | 36 | ;; L -- Value appropriate as displacement. |
f19a9af7 AK |
37 | ;; (0..4095) for short displacement |
38 | ;; (-524288..524287) for long displacement | |
39 | ;; M -- Constant integer with a value of 0x7fffffff. | |
40 | ;; N -- Multiple letter constraint followed by 4 parameter letters. | |
0dfa6c5e UW |
41 | ;; 0..9,x: number of the part counting from most to least significant |
42 | ;; H,Q: mode of the part | |
43 | ;; D,S,H: mode of the containing operand | |
44 | ;; 0,F: value of the other parts (F - all bits set) | |
2f7e5a0d | 45 | ;; |
f19a9af7 | 46 | ;; The constraint matches if the specified part of a constant |
0dfa6c5e UW |
47 | ;; has a value different from its other parts. If the letter x |
48 | ;; is specified instead of a part number, the constraint matches | |
49 | ;; if there is any single part with non-default value. | |
f19a9af7 AK |
50 | ;; Q -- Memory reference without index register and with short displacement. |
51 | ;; R -- Memory reference with index register and short displacement. | |
52 | ;; S -- Memory reference without index register but with long displacement. | |
53 | ;; T -- Memory reference with index register and long displacement. | |
0dfa6c5e UW |
54 | ;; A -- Multiple letter constraint followed by Q, R, S, or T: |
55 | ;; Offsettable memory reference of type specified by second letter. | |
e221ef54 UW |
56 | ;; B -- Multiple letter constraint followed by Q, R, S, or T: |
57 | ;; Memory reference of the type specified by second letter that | |
58 | ;; does *not* refer to a literal pool entry. | |
f19a9af7 AK |
59 | ;; U -- Pointer with short displacement. |
60 | ;; W -- Pointer with long displacement. | |
61 | ;; Y -- Shift count operand. | |
9db1d521 HP |
62 | ;; |
63 | ;; Special formats used for outputting 390 instructions. | |
64 | ;; | |
f19a9af7 AK |
65 | ;; %C: print opcode suffix for branch condition. |
66 | ;; %D: print opcode suffix for inverse branch condition. | |
67 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
68 | ;; %O: print only the displacement of a memory reference. | |
69 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 70 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
71 | ;; %N: print the second word of a DImode operand. |
72 | ;; %M: print the second word of a TImode operand. | |
73 | ||
74 | ;; %b: print integer X as if it's an unsigned byte. | |
75 | ;; %x: print integer X as if it's an unsigned word. | |
76 | ;; %h: print integer X as if it's a signed word. | |
77 | ;; %i: print the first nonzero HImode part of X | |
78 | ;; %j: print the first HImode part unequal to 0xffff of X | |
79 | ||
9db1d521 HP |
80 | ;; |
81 | ;; We have a special constraint for pattern matching. | |
82 | ;; | |
83 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
84 | ;; | |
9db1d521 | 85 | |
fd3cd001 UW |
86 | ;; |
87 | ;; UNSPEC usage | |
88 | ;; | |
89 | ||
90 | (define_constants | |
10bbf137 UW |
91 | [; Miscellaneous |
92 | (UNSPEC_ROUND 1) | |
5b022de5 | 93 | (UNSPEC_CMPINT 2) |
10bbf137 UW |
94 | (UNSPEC_SETHIGH 10) |
95 | ||
96 | ; GOT/PLT and lt-relative accesses | |
fd7643fb UW |
97 | (UNSPEC_LTREL_OFFSET 100) |
98 | (UNSPEC_LTREL_BASE 101) | |
99 | (UNSPEC_GOTENT 110) | |
100 | (UNSPEC_GOT 111) | |
101 | (UNSPEC_GOTOFF 112) | |
102 | (UNSPEC_PLT 113) | |
103 | (UNSPEC_PLTOFF 114) | |
104 | ||
105 | ; Literal pool | |
106 | (UNSPEC_RELOAD_BASE 210) | |
5af2f3d3 | 107 | (UNSPEC_MAIN_BASE 211) |
585539a1 | 108 | (UNSPEC_LTREF 212) |
9bb86f41 UW |
109 | (UNSPEC_INSN 213) |
110 | (UNSPEC_EXECUTE 214) | |
fd7643fb UW |
111 | |
112 | ; TLS relocation specifiers | |
fd3cd001 UW |
113 | (UNSPEC_TLSGD 500) |
114 | (UNSPEC_TLSLDM 501) | |
115 | (UNSPEC_NTPOFF 502) | |
116 | (UNSPEC_DTPOFF 503) | |
117 | (UNSPEC_GOTNTPOFF 504) | |
118 | (UNSPEC_INDNTPOFF 505) | |
119 | ||
120 | ; TLS support | |
fd3cd001 UW |
121 | (UNSPEC_TLSLDM_NTPOFF 511) |
122 | (UNSPEC_TLS_LOAD 512) | |
91d39d71 UW |
123 | |
124 | ; String Functions | |
125 | (UNSPEC_SRST 600) | |
fd3cd001 UW |
126 | ]) |
127 | ||
128 | ;; | |
129 | ;; UNSPEC_VOLATILE usage | |
130 | ;; | |
131 | ||
132 | (define_constants | |
10bbf137 UW |
133 | [; Blockage |
134 | (UNSPECV_BLOCKAGE 0) | |
135 | ||
2f7e5a0d EC |
136 | ; TPF Support |
137 | (UNSPECV_TPF_PROLOGUE 20) | |
138 | (UNSPECV_TPF_EPILOGUE 21) | |
139 | ||
10bbf137 | 140 | ; Literal pool |
fd7643fb | 141 | (UNSPECV_POOL 200) |
9bb86f41 UW |
142 | (UNSPECV_POOL_SECTION 201) |
143 | (UNSPECV_POOL_ALIGN 202) | |
416cf582 | 144 | (UNSPECV_POOL_ENTRY 203) |
fd7643fb UW |
145 | (UNSPECV_MAIN_POOL 300) |
146 | ||
147 | ; TLS support | |
fd3cd001 | 148 | (UNSPECV_SET_TP 500) |
e0374221 AS |
149 | |
150 | ; Atomic Support | |
151 | (UNSPECV_MB 700) | |
152 | (UNSPECV_CAS 701) | |
fd3cd001 UW |
153 | ]) |
154 | ||
ae156f85 AS |
155 | ;; |
156 | ;; Registers | |
157 | ;; | |
158 | ||
159 | (define_constants | |
160 | [ | |
161 | ; Sibling call register. | |
162 | (SIBCALL_REGNUM 1) | |
163 | ; Literal pool base register. | |
164 | (BASE_REGNUM 13) | |
165 | ; Return address register. | |
166 | (RETURN_REGNUM 14) | |
167 | ; Condition code register. | |
168 | (CC_REGNUM 33) | |
169 | ; Thread local storage pointer register. | |
170 | (TP_REGNUM 36) | |
171 | ]) | |
172 | ||
fd3cd001 | 173 | |
29a74354 UW |
174 | ;; Instruction operand type as used in the Principles of Operation. |
175 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 176 | |
29a74354 UW |
177 | (define_attr "op_type" |
178 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY" | |
b628bd8e | 179 | (const_string "NN")) |
9db1d521 | 180 | |
29a74354 | 181 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 182 | |
077dab3b | 183 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 184 | cs,vs,store,sem,idiv, |
ed0e512a | 185 | imulhi,imulsi,imuldi, |
cfdb984b AS |
186 | branch,jsr,fsimpdf,fsimpsf, |
187 | floaddf,floadsf,fstoredf,fstoresf, | |
188 | fmuldf,fmulsf,fdivdf,fdivsf, | |
189 | ftoi,itof,fsqrtdf,fsqrtsf, | |
a036c6f7 | 190 | other" |
29a74354 UW |
191 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
192 | (eq_attr "op_type" "SS") (const_string "cs")] | |
193 | (const_string "integer"))) | |
9db1d521 | 194 | |
29a74354 UW |
195 | ;; Another attribute used for scheduling purposes: |
196 | ;; agen: Instruction uses the address generation unit | |
197 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
198 | |
199 | (define_attr "atype" "agen,reg" | |
b628bd8e | 200 | (cond [(eq_attr "op_type" "E") (const_string "reg") |
077dab3b HP |
201 | (eq_attr "op_type" "RR") (const_string "reg") |
202 | (eq_attr "op_type" "RX") (const_string "agen") | |
203 | (eq_attr "op_type" "RI") (const_string "reg") | |
204 | (eq_attr "op_type" "RRE") (const_string "reg") | |
205 | (eq_attr "op_type" "RS") (const_string "agen") | |
206 | (eq_attr "op_type" "RSI") (const_string "agen") | |
207 | (eq_attr "op_type" "S") (const_string "agen") | |
208 | (eq_attr "op_type" "SI") (const_string "agen") | |
209 | (eq_attr "op_type" "SS") (const_string "agen") | |
210 | (eq_attr "op_type" "SSE") (const_string "agen") | |
211 | (eq_attr "op_type" "RXE") (const_string "agen") | |
212 | (eq_attr "op_type" "RSE") (const_string "agen") | |
d3632d41 UW |
213 | (eq_attr "op_type" "RIL") (const_string "agen") |
214 | (eq_attr "op_type" "RXY") (const_string "agen") | |
215 | (eq_attr "op_type" "RSY") (const_string "agen") | |
216 | (eq_attr "op_type" "SIY") (const_string "agen")] | |
b628bd8e | 217 | (const_string "agen"))) |
9db1d521 | 218 | |
9db1d521 HP |
219 | ;; Length in bytes. |
220 | ||
221 | (define_attr "length" "" | |
b628bd8e | 222 | (cond [(eq_attr "op_type" "E") (const_int 2) |
9db1d521 HP |
223 | (eq_attr "op_type" "RR") (const_int 2) |
224 | (eq_attr "op_type" "RX") (const_int 4) | |
225 | (eq_attr "op_type" "RI") (const_int 4) | |
226 | (eq_attr "op_type" "RRE") (const_int 4) | |
227 | (eq_attr "op_type" "RS") (const_int 4) | |
228 | (eq_attr "op_type" "RSI") (const_int 4) | |
9db1d521 HP |
229 | (eq_attr "op_type" "S") (const_int 4) |
230 | (eq_attr "op_type" "SI") (const_int 4) | |
231 | (eq_attr "op_type" "SS") (const_int 6) | |
232 | (eq_attr "op_type" "SSE") (const_int 6) | |
233 | (eq_attr "op_type" "RXE") (const_int 6) | |
234 | (eq_attr "op_type" "RSE") (const_int 6) | |
d3632d41 UW |
235 | (eq_attr "op_type" "RIL") (const_int 6) |
236 | (eq_attr "op_type" "RXY") (const_int 6) | |
237 | (eq_attr "op_type" "RSY") (const_int 6) | |
238 | (eq_attr "op_type" "SIY") (const_int 6)] | |
b628bd8e | 239 | (const_int 6))) |
9db1d521 | 240 | |
29a74354 UW |
241 | |
242 | ;; Processor type. This attribute must exactly match the processor_type | |
243 | ;; enumeration in s390.h. The current machine description does not | |
244 | ;; distinguish between g5 and g6, but there are differences between the two | |
245 | ;; CPUs could in theory be modeled. | |
246 | ||
247 | (define_attr "cpu" "g5,g6,z900,z990" | |
248 | (const (symbol_ref "s390_tune"))) | |
249 | ||
250 | ;; Pipeline description for z900. For lack of anything better, | |
251 | ;; this description is also used for the g5 and g6. | |
252 | (include "2064.md") | |
253 | ||
254 | ;; Pipeline description for z990. | |
255 | (include "2084.md") | |
256 | ||
0bfc3f69 AS |
257 | ;; Predicates |
258 | (include "predicates.md") | |
259 | ||
f52c81dd AS |
260 | |
261 | ;; Macros | |
262 | ||
f5905b37 AS |
263 | ;; This mode macro allows DF and SF patterns to be generated from the |
264 | ;; same template. | |
265 | (define_mode_macro FPR [DF SF]) | |
266 | ||
9a91a21f | 267 | ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d AS |
268 | ;; from the same template. |
269 | (define_mode_macro GPR [(DI "TARGET_64BIT") SI]) | |
9a91a21f | 270 | (define_mode_macro DSI [DI SI]) |
9db2f16d AS |
271 | |
272 | ;; This mode macro allows :P to be used for patterns that operate on | |
273 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. | |
274 | (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) | |
275 | ||
f52c81dd AS |
276 | ;; This mode macro allows the QI and HI patterns to be defined from |
277 | ;; the same template. | |
278 | (define_mode_macro HQI [HI QI]) | |
279 | ||
342cf42b AS |
280 | ;; This mode macro allows the integer patterns to be defined from the |
281 | ;; same template. | |
282 | (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI]) | |
283 | ||
fa77b251 AS |
284 | ;; This macro allows to unify all 'bCOND' expander patterns. |
285 | (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered | |
286 | ordered uneq unlt ungt unle unge ltgt]) | |
287 | ||
9a91a21f AS |
288 | ;; This macro allows to unify all 'sCOND' patterns. |
289 | (define_code_macro SCOND [ltu gtu leu geu]) | |
290 | ||
f337b930 AS |
291 | ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from |
292 | ;; the same template. | |
293 | (define_code_macro SHIFT [ashift lshiftrt]) | |
294 | ||
295 | ||
f5905b37 AS |
296 | ;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode |
297 | ;; and "ltebr" in SFmode. | |
298 | (define_mode_attr de [(DF "d") (SF "e")]) | |
299 | ||
300 | ;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode | |
301 | ;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern. | |
302 | (define_mode_attr dee [(DF "d") (SF "ee")]) | |
303 | ||
f337b930 AS |
304 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in |
305 | ;; 'ashift' and "srdl" in 'lshiftrt'. | |
306 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
307 | ||
308 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
309 | ;; pattern itself and the corresponding function calls. | |
310 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) | |
9a91a21f AS |
311 | |
312 | ;; This attribute handles differences in the instruction 'type' and will result | |
313 | ;; in "RRE" for DImode and "RR" for SImode. | |
314 | (define_mode_attr E [(DI "E") (SI "")]) | |
315 | ||
316 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode | |
317 | ;; and "lcr" in SImode. | |
318 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 319 | |
2f8f8434 AS |
320 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
321 | ;; and "cfdbr" in SImode. | |
322 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
323 | ||
f52c81dd AS |
324 | ;; ICM mask required to load MODE value into the highest subreg |
325 | ;; of a SImode register. | |
326 | (define_mode_attr icm_hi [(HI "12") (QI "8")]) | |
327 | ||
328 | ;; ICM mask required to load MODE value into the lowest subreg | |
329 | ;; of a SImode register. | |
330 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
331 | ||
f6ee577c AS |
332 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
333 | ;; HImode and "llgc" in QImode. | |
334 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
335 | ||
a1aed706 AS |
336 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
337 | ;; in SImode. | |
338 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
339 | ||
f52c81dd AS |
340 | ;; Maximum unsigned integer that fits in MODE. |
341 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
342 | ||
343 | ||
9db1d521 HP |
344 | ;; |
345 | ;;- Compare instructions. | |
346 | ;; | |
347 | ||
9db2f16d | 348 | (define_expand "cmp<mode>" |
ae156f85 | 349 | [(set (reg:CC CC_REGNUM) |
9db2f16d AS |
350 | (compare:CC (match_operand:GPR 0 "register_operand" "") |
351 | (match_operand:GPR 1 "general_operand" "")))] | |
9db1d521 | 352 | "" |
9db1d521 HP |
353 | { |
354 | s390_compare_op0 = operands[0]; | |
355 | s390_compare_op1 = operands[1]; | |
356 | DONE; | |
10bbf137 | 357 | }) |
9db1d521 | 358 | |
f5905b37 | 359 | (define_expand "cmp<mode>" |
ae156f85 | 360 | [(set (reg:CC CC_REGNUM) |
f5905b37 AS |
361 | (compare:CC (match_operand:FPR 0 "register_operand" "") |
362 | (match_operand:FPR 1 "general_operand" "")))] | |
9db1d521 | 363 | "TARGET_HARD_FLOAT" |
9db1d521 HP |
364 | { |
365 | s390_compare_op0 = operands[0]; | |
366 | s390_compare_op1 = operands[1]; | |
367 | DONE; | |
10bbf137 | 368 | }) |
9db1d521 HP |
369 | |
370 | ||
07893d4f | 371 | ; Test-under-Mask instructions |
9db1d521 | 372 | |
07893d4f | 373 | (define_insn "*tmqi_mem" |
ae156f85 | 374 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
375 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
376 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
377 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 378 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 379 | "@ |
fc0ea003 UW |
380 | tm\t%S0,%b1 |
381 | tmy\t%S0,%b1" | |
d3632d41 | 382 | [(set_attr "op_type" "SI,SIY")]) |
9db1d521 | 383 | |
05b9aaaa | 384 | (define_insn "*tmdi_reg" |
ae156f85 | 385 | [(set (reg CC_REGNUM) |
f19a9af7 | 386 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 387 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
388 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
389 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
05b9aaaa | 390 | "TARGET_64BIT |
3ed99cc9 | 391 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
392 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
393 | "@ | |
394 | tmhh\t%0,%i1 | |
395 | tmhl\t%0,%i1 | |
396 | tmlh\t%0,%i1 | |
397 | tmll\t%0,%i1" | |
05b9aaaa UW |
398 | [(set_attr "op_type" "RI")]) |
399 | ||
400 | (define_insn "*tmsi_reg" | |
ae156f85 | 401 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
402 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
403 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
404 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 405 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
406 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
407 | "@ | |
408 | tmh\t%0,%i1 | |
409 | tml\t%0,%i1" | |
05b9aaaa UW |
410 | [(set_attr "op_type" "RI")]) |
411 | ||
f52c81dd | 412 | (define_insn "*tm<mode>_full" |
ae156f85 | 413 | [(set (reg CC_REGNUM) |
f52c81dd AS |
414 | (compare (match_operand:HQI 0 "register_operand" "d") |
415 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 416 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 417 | "tml\t%0,<max_uint>" |
07893d4f | 418 | [(set_attr "op_type" "RI")]) |
9db1d521 | 419 | |
07893d4f UW |
420 | |
421 | ; Load-and-Test instructions | |
422 | ||
423 | (define_insn "*tstdi_sign" | |
ae156f85 | 424 | [(set (reg CC_REGNUM) |
07893d4f UW |
425 | (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0) |
426 | (const_int 32)) (const_int 32)) | |
427 | (match_operand:DI 1 "const0_operand" ""))) | |
428 | (set (match_operand:DI 2 "register_operand" "=d") | |
429 | (sign_extend:DI (match_dup 0)))] | |
430 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 431 | "ltgfr\t%2,%0" |
07893d4f UW |
432 | [(set_attr "op_type" "RRE")]) |
433 | ||
434 | (define_insn "*tstdi" | |
ae156f85 | 435 | [(set (reg CC_REGNUM) |
07893d4f UW |
436 | (compare (match_operand:DI 0 "register_operand" "d") |
437 | (match_operand:DI 1 "const0_operand" ""))) | |
438 | (set (match_operand:DI 2 "register_operand" "=d") | |
439 | (match_dup 0))] | |
440 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 441 | "ltgr\t%2,%0" |
07893d4f | 442 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 443 | |
07893d4f | 444 | (define_insn "*tstdi_cconly" |
ae156f85 | 445 | [(set (reg CC_REGNUM) |
07893d4f UW |
446 | (compare (match_operand:DI 0 "register_operand" "d") |
447 | (match_operand:DI 1 "const0_operand" "")))] | |
448 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 449 | "ltgr\t%0,%0" |
07893d4f | 450 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 451 | |
07893d4f | 452 | (define_insn "*tstdi_cconly_31" |
ae156f85 | 453 | [(set (reg CC_REGNUM) |
07893d4f UW |
454 | (compare (match_operand:DI 0 "register_operand" "d") |
455 | (match_operand:DI 1 "const0_operand" "")))] | |
456 | "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" | |
d40c829f | 457 | "srda\t%0,0" |
077dab3b HP |
458 | [(set_attr "op_type" "RS") |
459 | (set_attr "atype" "reg")]) | |
460 | ||
4023fb28 | 461 | |
07893d4f | 462 | (define_insn "*tstsi" |
ae156f85 | 463 | [(set (reg CC_REGNUM) |
d3632d41 | 464 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 465 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 466 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f UW |
467 | (match_dup 0))] |
468 | "s390_match_ccmode(insn, CCSmode)" | |
469 | "@ | |
d40c829f | 470 | ltr\t%2,%0 |
fc0ea003 UW |
471 | icm\t%2,15,%S0 |
472 | icmy\t%2,15,%S0" | |
d3632d41 | 473 | [(set_attr "op_type" "RR,RS,RSY")]) |
9db1d521 | 474 | |
07893d4f | 475 | (define_insn "*tstsi_cconly" |
ae156f85 | 476 | [(set (reg CC_REGNUM) |
d3632d41 | 477 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 478 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 479 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
480 | "s390_match_ccmode(insn, CCSmode)" |
481 | "@ | |
d40c829f | 482 | ltr\t%0,%0 |
fc0ea003 UW |
483 | icm\t%2,15,%S0 |
484 | icmy\t%2,15,%S0" | |
d3632d41 | 485 | [(set_attr "op_type" "RR,RS,RSY")]) |
4023fb28 | 486 | |
07893d4f | 487 | (define_insn "*tstsi_cconly2" |
ae156f85 | 488 | [(set (reg CC_REGNUM) |
07893d4f UW |
489 | (compare (match_operand:SI 0 "register_operand" "d") |
490 | (match_operand:SI 1 "const0_operand" "")))] | |
491 | "s390_match_ccmode(insn, CCSmode)" | |
d40c829f | 492 | "ltr\t%0,%0" |
07893d4f | 493 | [(set_attr "op_type" "RR")]) |
4023fb28 | 494 | |
f52c81dd | 495 | (define_insn "*tst<mode>CCT" |
ae156f85 | 496 | [(set (reg CC_REGNUM) |
f52c81dd AS |
497 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
498 | (match_operand:HQI 1 "const0_operand" ""))) | |
499 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
500 | (match_dup 0))] |
501 | "s390_match_ccmode(insn, CCTmode)" | |
502 | "@ | |
f52c81dd AS |
503 | icm\t%2,<icm_lo>,%S0 |
504 | icmy\t%2,<icm_lo>,%S0 | |
505 | tml\t%0,<max_uint>" | |
d3632d41 | 506 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 UW |
507 | |
508 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 509 | [(set (reg CC_REGNUM) |
d3632d41 | 510 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 511 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 512 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
513 | "s390_match_ccmode(insn, CCTmode)" |
514 | "@ | |
fc0ea003 UW |
515 | icm\t%2,3,%S0 |
516 | icmy\t%2,3,%S0 | |
d40c829f | 517 | tml\t%0,65535" |
d3632d41 | 518 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 | 519 | |
3af97654 | 520 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 521 | [(set (reg CC_REGNUM) |
d3632d41 | 522 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
523 | (match_operand:QI 1 "const0_operand" "")))] |
524 | "s390_match_ccmode(insn, CCTmode)" | |
525 | "@ | |
fc0ea003 UW |
526 | cli\t%S0,0 |
527 | cliy\t%S0,0 | |
d40c829f | 528 | tml\t%0,255" |
d3632d41 | 529 | [(set_attr "op_type" "SI,SIY,RI")]) |
3af97654 | 530 | |
f52c81dd | 531 | (define_insn "*tst<mode>" |
ae156f85 | 532 | [(set (reg CC_REGNUM) |
f52c81dd AS |
533 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
534 | (match_operand:HQI 1 "const0_operand" ""))) | |
535 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
536 | (match_dup 0))] |
537 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 538 | "@ |
f52c81dd AS |
539 | icm\t%2,<icm_lo>,%S0 |
540 | icmy\t%2,<icm_lo>,%S0" | |
d3632d41 | 541 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 542 | |
f52c81dd | 543 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 544 | [(set (reg CC_REGNUM) |
f52c81dd AS |
545 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
546 | (match_operand:HQI 1 "const0_operand" ""))) | |
547 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 548 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 549 | "@ |
f52c81dd AS |
550 | icm\t%2,<icm_lo>,%S0 |
551 | icmy\t%2,<icm_lo>,%S0" | |
d3632d41 UW |
552 | [(set_attr "op_type" "RS,RSY")]) |
553 | ||
9db1d521 | 554 | |
575f7c2b UW |
555 | ; Compare (equality) instructions |
556 | ||
557 | (define_insn "*cmpdi_cct" | |
ae156f85 | 558 | [(set (reg CC_REGNUM) |
e221ef54 UW |
559 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q") |
560 | (match_operand:DI 1 "general_operand" "d,K,m,BQ")))] | |
561 | "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT" | |
575f7c2b UW |
562 | "@ |
563 | cgr\t%0,%1 | |
f4f41b4e | 564 | cghi\t%0,%h1 |
575f7c2b | 565 | cg\t%0,%1 |
19b63d8e | 566 | #" |
e221ef54 | 567 | [(set_attr "op_type" "RRE,RI,RXY,SS")]) |
575f7c2b UW |
568 | |
569 | (define_insn "*cmpsi_cct" | |
ae156f85 | 570 | [(set (reg CC_REGNUM) |
e221ef54 UW |
571 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
572 | (match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))] | |
573 | "s390_match_ccmode (insn, CCTmode)" | |
575f7c2b UW |
574 | "@ |
575 | cr\t%0,%1 | |
f4f41b4e | 576 | chi\t%0,%h1 |
575f7c2b UW |
577 | c\t%0,%1 |
578 | cy\t%0,%1 | |
19b63d8e | 579 | #" |
e221ef54 | 580 | [(set_attr "op_type" "RR,RI,RX,RXY,SS")]) |
575f7c2b UW |
581 | |
582 | ||
07893d4f | 583 | ; Compare (signed) instructions |
4023fb28 | 584 | |
07893d4f | 585 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 586 | [(set (reg CC_REGNUM) |
07893d4f UW |
587 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
588 | (match_operand:DI 0 "register_operand" "d,d")))] | |
589 | "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" | |
4023fb28 | 590 | "@ |
d40c829f UW |
591 | cgfr\t%0,%1 |
592 | cgf\t%0,%1" | |
d3632d41 | 593 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 594 | |
07893d4f | 595 | (define_insn "*cmpdi_ccs" |
ae156f85 | 596 | [(set (reg CC_REGNUM) |
07893d4f UW |
597 | (compare (match_operand:DI 0 "register_operand" "d,d,d") |
598 | (match_operand:DI 1 "general_operand" "d,K,m")))] | |
599 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
600 | "@ | |
d40c829f | 601 | cgr\t%0,%1 |
f4f41b4e | 602 | cghi\t%0,%h1 |
d40c829f | 603 | cg\t%0,%1" |
d3632d41 | 604 | [(set_attr "op_type" "RRE,RI,RXY")]) |
c7453384 | 605 | |
07893d4f | 606 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 607 | [(set (reg CC_REGNUM) |
d3632d41 UW |
608 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")) |
609 | (match_operand:SI 0 "register_operand" "d,d")))] | |
07893d4f | 610 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 611 | "@ |
d40c829f UW |
612 | ch\t%0,%1 |
613 | chy\t%0,%1" | |
d3632d41 | 614 | [(set_attr "op_type" "RX,RXY")]) |
4023fb28 | 615 | |
07893d4f | 616 | (define_insn "*cmpsi_ccs" |
ae156f85 | 617 | [(set (reg CC_REGNUM) |
d3632d41 UW |
618 | (compare (match_operand:SI 0 "register_operand" "d,d,d,d") |
619 | (match_operand:SI 1 "general_operand" "d,K,R,T")))] | |
9db1d521 | 620 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 621 | "@ |
d40c829f | 622 | cr\t%0,%1 |
f4f41b4e | 623 | chi\t%0,%h1 |
d40c829f UW |
624 | c\t%0,%1 |
625 | cy\t%0,%1" | |
d3632d41 | 626 | [(set_attr "op_type" "RR,RI,RX,RXY")]) |
c7453384 | 627 | |
07893d4f UW |
628 | |
629 | ; Compare (unsigned) instructions | |
9db1d521 | 630 | |
07893d4f | 631 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 632 | [(set (reg CC_REGNUM) |
07893d4f UW |
633 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
634 | (match_operand:DI 0 "register_operand" "d,d")))] | |
575f7c2b | 635 | "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT" |
07893d4f | 636 | "@ |
d40c829f UW |
637 | clgfr\t%0,%1 |
638 | clgf\t%0,%1" | |
d3632d41 | 639 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 640 | |
07893d4f | 641 | (define_insn "*cmpdi_ccu" |
ae156f85 | 642 | [(set (reg CC_REGNUM) |
e221ef54 UW |
643 | (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ") |
644 | (match_operand:DI 1 "general_operand" "d,m,BQ,Q")))] | |
645 | "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT" | |
07893d4f | 646 | "@ |
d40c829f | 647 | clgr\t%0,%1 |
575f7c2b | 648 | clg\t%0,%1 |
e221ef54 | 649 | # |
19b63d8e | 650 | #" |
e221ef54 | 651 | [(set_attr "op_type" "RRE,RXY,SS,SS")]) |
9db1d521 | 652 | |
07893d4f | 653 | (define_insn "*cmpsi_ccu" |
ae156f85 | 654 | [(set (reg CC_REGNUM) |
e221ef54 UW |
655 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ") |
656 | (match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))] | |
657 | "s390_match_ccmode (insn, CCUmode)" | |
07893d4f | 658 | "@ |
d40c829f UW |
659 | clr\t%0,%1 |
660 | cl\t%0,%1 | |
575f7c2b | 661 | cly\t%0,%1 |
e221ef54 | 662 | # |
19b63d8e | 663 | #" |
e221ef54 | 664 | [(set_attr "op_type" "RR,RX,RXY,SS,SS")]) |
9db1d521 | 665 | |
07893d4f | 666 | (define_insn "*cmphi_ccu" |
ae156f85 | 667 | [(set (reg CC_REGNUM) |
e221ef54 UW |
668 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ") |
669 | (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))] | |
575f7c2b | 670 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 671 | && !register_operand (operands[1], HImode)" |
d3632d41 | 672 | "@ |
fc0ea003 UW |
673 | clm\t%0,3,%S1 |
674 | clmy\t%0,3,%S1 | |
e221ef54 | 675 | # |
19b63d8e | 676 | #" |
e221ef54 | 677 | [(set_attr "op_type" "RS,RSY,SS,SS")]) |
9db1d521 HP |
678 | |
679 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 680 | [(set (reg CC_REGNUM) |
e221ef54 UW |
681 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
682 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 683 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 684 | && !register_operand (operands[1], QImode)" |
d3632d41 | 685 | "@ |
fc0ea003 UW |
686 | clm\t%0,1,%S1 |
687 | clmy\t%0,1,%S1 | |
688 | cli\t%S0,%b1 | |
689 | cliy\t%S0,%b1 | |
e221ef54 | 690 | # |
19b63d8e | 691 | #" |
e221ef54 | 692 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")]) |
9db1d521 HP |
693 | |
694 | ||
19b63d8e UW |
695 | ; Block compare (CLC) instruction patterns. |
696 | ||
697 | (define_insn "*clc" | |
ae156f85 | 698 | [(set (reg CC_REGNUM) |
d4f52f0e | 699 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
700 | (match_operand:BLK 1 "memory_operand" "Q"))) |
701 | (use (match_operand 2 "const_int_operand" "n"))] | |
702 | "s390_match_ccmode (insn, CCUmode) | |
703 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 704 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 705 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
706 | |
707 | (define_split | |
ae156f85 | 708 | [(set (reg CC_REGNUM) |
19b63d8e UW |
709 | (compare (match_operand 0 "memory_operand" "") |
710 | (match_operand 1 "memory_operand" "")))] | |
711 | "reload_completed | |
712 | && s390_match_ccmode (insn, CCUmode) | |
713 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
714 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
715 | [(parallel | |
716 | [(set (match_dup 0) (match_dup 1)) | |
717 | (use (match_dup 2))])] | |
718 | { | |
719 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
720 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
721 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
722 | ||
723 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
724 | operands[0], operands[1]); | |
725 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
726 | }) | |
727 | ||
728 | ||
f5905b37 | 729 | ; (DF|SF) instructions |
9db1d521 | 730 | |
f5905b37 | 731 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 732 | [(set (reg CC_REGNUM) |
f5905b37 AS |
733 | (compare (match_operand:FPR 0 "register_operand" "f") |
734 | (match_operand:FPR 1 "const0_operand" "")))] | |
9db1d521 | 735 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 736 | "lt<de>br\t%0,%0" |
077dab3b | 737 | [(set_attr "op_type" "RRE") |
f5905b37 | 738 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 739 | |
f5905b37 | 740 | (define_insn "*cmp<mode>_ccs_0_ibm" |
ae156f85 | 741 | [(set (reg CC_REGNUM) |
f5905b37 AS |
742 | (compare (match_operand:FPR 0 "register_operand" "f") |
743 | (match_operand:FPR 1 "const0_operand" "")))] | |
9db1d521 | 744 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
f5905b37 | 745 | "lt<de>r\t%0,%0" |
077dab3b | 746 | [(set_attr "op_type" "RR") |
f5905b37 | 747 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 748 | |
f5905b37 | 749 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 750 | [(set (reg CC_REGNUM) |
f5905b37 AS |
751 | (compare (match_operand:FPR 0 "register_operand" "f,f") |
752 | (match_operand:FPR 1 "general_operand" "f,R")))] | |
9db1d521 HP |
753 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
754 | "@ | |
f5905b37 AS |
755 | c<de>br\t%0,%1 |
756 | c<de>b\t%0,%1" | |
077dab3b | 757 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 758 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 759 | |
f5905b37 | 760 | (define_insn "*cmp<mode>_ccs_ibm" |
ae156f85 | 761 | [(set (reg CC_REGNUM) |
f5905b37 AS |
762 | (compare (match_operand:FPR 0 "register_operand" "f,f") |
763 | (match_operand:FPR 1 "general_operand" "f,R")))] | |
9db1d521 HP |
764 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
765 | "@ | |
f5905b37 AS |
766 | c<de>r\t%0,%1 |
767 | c<de>\t%0,%1" | |
077dab3b | 768 | [(set_attr "op_type" "RR,RX") |
f5905b37 | 769 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 HP |
770 | |
771 | ||
772 | ;; | |
773 | ;;- Move instructions. | |
774 | ;; | |
775 | ||
776 | ; | |
777 | ; movti instruction pattern(s). | |
778 | ; | |
779 | ||
780 | (define_insn "movti" | |
d3632d41 UW |
781 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q") |
782 | (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))] | |
9db1d521 | 783 | "TARGET_64BIT" |
4023fb28 | 784 | "@ |
fc0ea003 UW |
785 | lmg\t%0,%N0,%S1 |
786 | stmg\t%1,%N1,%S0 | |
4023fb28 | 787 | # |
9b7c75b9 | 788 | # |
19b63d8e | 789 | #" |
b628bd8e UW |
790 | [(set_attr "op_type" "RSY,RSY,*,*,SS") |
791 | (set_attr "type" "lm,stm,*,*,*")]) | |
4023fb28 UW |
792 | |
793 | (define_split | |
794 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
795 | (match_operand:TI 1 "general_operand" ""))] | |
796 | "TARGET_64BIT && reload_completed | |
dc65c307 | 797 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
798 | [(set (match_dup 2) (match_dup 4)) |
799 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 800 | { |
dc65c307 UW |
801 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
802 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
803 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
804 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
805 | }) | |
806 | ||
807 | (define_split | |
808 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
809 | (match_operand:TI 1 "general_operand" ""))] | |
810 | "TARGET_64BIT && reload_completed | |
811 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" | |
812 | [(set (match_dup 2) (match_dup 4)) | |
813 | (set (match_dup 3) (match_dup 5))] | |
814 | { | |
815 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
816 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
817 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
818 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
819 | }) | |
4023fb28 UW |
820 | |
821 | (define_split | |
822 | [(set (match_operand:TI 0 "register_operand" "") | |
823 | (match_operand:TI 1 "memory_operand" ""))] | |
824 | "TARGET_64BIT && reload_completed | |
825 | && !s_operand (operands[1], VOIDmode)" | |
a41c6c53 | 826 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
827 | { |
828 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
829 | s390_load_address (addr, XEXP (operands[1], 0)); | |
830 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
831 | }) |
832 | ||
833 | (define_expand "reload_outti" | |
9c3c3dcc | 834 | [(parallel [(match_operand:TI 0 "" "") |
dc65c307 UW |
835 | (match_operand:TI 1 "register_operand" "d") |
836 | (match_operand:DI 2 "register_operand" "=&a")])] | |
837 | "TARGET_64BIT" | |
838 | { | |
9c3c3dcc | 839 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 840 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
841 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
842 | emit_move_insn (operands[0], operands[1]); | |
843 | DONE; | |
844 | }) | |
9db1d521 HP |
845 | |
846 | ; | |
847 | ; movdi instruction pattern(s). | |
848 | ; | |
849 | ||
9db1d521 HP |
850 | (define_expand "movdi" |
851 | [(set (match_operand:DI 0 "general_operand" "") | |
852 | (match_operand:DI 1 "general_operand" ""))] | |
853 | "" | |
9db1d521 | 854 | { |
fd3cd001 UW |
855 | /* Handle symbolic constants. */ |
856 | if (TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
857 | emit_symbolic_move (operands); | |
10bbf137 | 858 | }) |
9db1d521 | 859 | |
4023fb28 UW |
860 | (define_insn "*movdi_larl" |
861 | [(set (match_operand:DI 0 "register_operand" "=d") | |
862 | (match_operand:DI 1 "larl_operand" "X"))] | |
863 | "TARGET_64BIT | |
8e509cf9 | 864 | && !FP_REG_P (operands[0])" |
d40c829f | 865 | "larl\t%0,%1" |
4023fb28 | 866 | [(set_attr "op_type" "RIL") |
077dab3b | 867 | (set_attr "type" "larl")]) |
4023fb28 | 868 | |
9db1d521 | 869 | (define_insn "*movdi_64" |
2f7e5a0d | 870 | [(set (match_operand:DI 0 "nonimmediate_operand" |
c5aa1d12 | 871 | "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") |
2f7e5a0d | 872 | (match_operand:DI 1 "general_operand" |
c5aa1d12 | 873 | "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))] |
9db1d521 HP |
874 | "TARGET_64BIT" |
875 | "@ | |
f19a9af7 AK |
876 | lghi\t%0,%h1 |
877 | llihh\t%0,%i1 | |
878 | llihl\t%0,%i1 | |
879 | llilh\t%0,%i1 | |
880 | llill\t%0,%i1 | |
881 | lay\t%0,%a1 | |
d40c829f UW |
882 | lgr\t%0,%1 |
883 | lg\t%0,%1 | |
884 | stg\t%1,%0 | |
885 | ldr\t%0,%1 | |
886 | ld\t%0,%1 | |
887 | ldy\t%0,%1 | |
888 | std\t%1,%0 | |
889 | stdy\t%1,%0 | |
c5aa1d12 UW |
890 | # |
891 | # | |
892 | stam\t%1,%N1,%S0 | |
893 | lam\t%0,%N0,%S1 | |
19b63d8e | 894 | #" |
b628bd8e UW |
895 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY, |
896 | RR,RX,RXY,RX,RXY,*,*,RS,RS,SS") | |
897 | (set_attr "type" "*,*,*,*,*,la,lr,load,store, | |
cfdb984b | 898 | floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")]) |
c5aa1d12 UW |
899 | |
900 | (define_split | |
901 | [(set (match_operand:DI 0 "register_operand" "") | |
902 | (match_operand:DI 1 "register_operand" ""))] | |
903 | "TARGET_64BIT && ACCESS_REG_P (operands[1])" | |
904 | [(set (match_dup 2) (match_dup 3)) | |
905 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
906 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
907 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
908 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
909 | ||
910 | (define_split | |
911 | [(set (match_operand:DI 0 "register_operand" "") | |
912 | (match_operand:DI 1 "register_operand" ""))] | |
913 | "TARGET_64BIT && ACCESS_REG_P (operands[0]) | |
914 | && dead_or_set_p (insn, operands[1])" | |
915 | [(set (match_dup 3) (match_dup 2)) | |
916 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
917 | (set (match_dup 4) (match_dup 2))] | |
918 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
919 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
920 | ||
921 | (define_split | |
922 | [(set (match_operand:DI 0 "register_operand" "") | |
923 | (match_operand:DI 1 "register_operand" ""))] | |
924 | "TARGET_64BIT && ACCESS_REG_P (operands[0]) | |
925 | && !dead_or_set_p (insn, operands[1])" | |
926 | [(set (match_dup 3) (match_dup 2)) | |
927 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
928 | (set (match_dup 4) (match_dup 2)) | |
929 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
930 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
931 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
932 | |
933 | (define_insn "*movdi_31" | |
d3632d41 UW |
934 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q") |
935 | (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))] | |
9db1d521 | 936 | "!TARGET_64BIT" |
4023fb28 | 937 | "@ |
fc0ea003 UW |
938 | lm\t%0,%N0,%S1 |
939 | stm\t%1,%N1,%S0 | |
4023fb28 UW |
940 | # |
941 | # | |
d40c829f UW |
942 | ldr\t%0,%1 |
943 | ld\t%0,%1 | |
944 | ldy\t%0,%1 | |
945 | std\t%1,%0 | |
946 | stdy\t%1,%0 | |
19b63d8e | 947 | #" |
b628bd8e | 948 | [(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS") |
cfdb984b | 949 | (set_attr "type" "lm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")]) |
4023fb28 UW |
950 | |
951 | (define_split | |
952 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
953 | (match_operand:DI 1 "general_operand" ""))] | |
954 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 955 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
956 | [(set (match_dup 2) (match_dup 4)) |
957 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 958 | { |
dc65c307 UW |
959 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
960 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
961 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
962 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
963 | }) | |
964 | ||
965 | (define_split | |
966 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
967 | (match_operand:DI 1 "general_operand" ""))] | |
968 | "!TARGET_64BIT && reload_completed | |
969 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" | |
970 | [(set (match_dup 2) (match_dup 4)) | |
971 | (set (match_dup 3) (match_dup 5))] | |
972 | { | |
973 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
974 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
975 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
976 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
977 | }) | |
9db1d521 | 978 | |
4023fb28 UW |
979 | (define_split |
980 | [(set (match_operand:DI 0 "register_operand" "") | |
981 | (match_operand:DI 1 "memory_operand" ""))] | |
982 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 983 | && !FP_REG_P (operands[0]) |
4023fb28 | 984 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 985 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
986 | { |
987 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
988 | s390_load_address (addr, XEXP (operands[1], 0)); | |
989 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
990 | }) |
991 | ||
992 | (define_expand "reload_outdi" | |
9c3c3dcc | 993 | [(parallel [(match_operand:DI 0 "" "") |
dc65c307 UW |
994 | (match_operand:DI 1 "register_operand" "d") |
995 | (match_operand:SI 2 "register_operand" "=&a")])] | |
996 | "!TARGET_64BIT" | |
997 | { | |
9c3c3dcc | 998 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 999 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1000 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1001 | emit_move_insn (operands[0], operands[1]); | |
1002 | DONE; | |
1003 | }) | |
9db1d521 | 1004 | |
84817c5d UW |
1005 | (define_peephole2 |
1006 | [(set (match_operand:DI 0 "register_operand" "") | |
1007 | (mem:DI (match_operand 1 "address_operand" "")))] | |
1008 | "TARGET_64BIT | |
1009 | && !FP_REG_P (operands[0]) | |
1010 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1011 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1012 | && get_pool_mode (operands[1]) == DImode | |
1013 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1014 | [(set (match_dup 0) (match_dup 2))] | |
1015 | "operands[2] = get_pool_constant (operands[1]);") | |
1016 | ||
7bdff56f UW |
1017 | (define_insn "*la_64" |
1018 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
1019 | (match_operand:QI 1 "address_operand" "U,W"))] | |
1020 | "TARGET_64BIT" | |
1021 | "@ | |
1022 | la\t%0,%a1 | |
1023 | lay\t%0,%a1" | |
1024 | [(set_attr "op_type" "RX,RXY") | |
1025 | (set_attr "type" "la")]) | |
1026 | ||
1027 | (define_peephole2 | |
1028 | [(parallel | |
1029 | [(set (match_operand:DI 0 "register_operand" "") | |
1030 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1031 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1032 | "TARGET_64BIT |
e1d5ee28 | 1033 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1034 | [(set (match_dup 0) (match_dup 1))] |
1035 | "") | |
1036 | ||
1037 | (define_peephole2 | |
1038 | [(set (match_operand:DI 0 "register_operand" "") | |
1039 | (match_operand:DI 1 "register_operand" "")) | |
1040 | (parallel | |
1041 | [(set (match_dup 0) | |
1042 | (plus:DI (match_dup 0) | |
1043 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1044 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1045 | "TARGET_64BIT |
1046 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1047 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1048 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1049 | "") | |
1050 | ||
1051 | (define_expand "reload_indi" | |
1052 | [(parallel [(match_operand:DI 0 "register_operand" "=a") | |
1053 | (match_operand:DI 1 "s390_plus_operand" "") | |
1054 | (match_operand:DI 2 "register_operand" "=&a")])] | |
1055 | "TARGET_64BIT" | |
1056 | { | |
1057 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1058 | DONE; | |
1059 | }) | |
1060 | ||
9db1d521 HP |
1061 | ; |
1062 | ; movsi instruction pattern(s). | |
1063 | ; | |
1064 | ||
9db1d521 HP |
1065 | (define_expand "movsi" |
1066 | [(set (match_operand:SI 0 "general_operand" "") | |
1067 | (match_operand:SI 1 "general_operand" ""))] | |
1068 | "" | |
9db1d521 | 1069 | { |
fd3cd001 UW |
1070 | /* Handle symbolic constants. */ |
1071 | if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
1072 | emit_symbolic_move (operands); | |
10bbf137 | 1073 | }) |
9db1d521 | 1074 | |
9e8327e3 UW |
1075 | (define_insn "*movsi_larl" |
1076 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1077 | (match_operand:SI 1 "larl_operand" "X"))] | |
1078 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1079 | && !FP_REG_P (operands[0])" | |
1080 | "larl\t%0,%1" | |
1081 | [(set_attr "op_type" "RIL") | |
1082 | (set_attr "type" "larl")]) | |
1083 | ||
f19a9af7 | 1084 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1085 | [(set (match_operand:SI 0 "nonimmediate_operand" |
c5aa1d12 | 1086 | "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") |
2f7e5a0d | 1087 | (match_operand:SI 1 "general_operand" |
c5aa1d12 | 1088 | "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))] |
f19a9af7 | 1089 | "TARGET_ZARCH" |
9db1d521 | 1090 | "@ |
f19a9af7 AK |
1091 | lhi\t%0,%h1 |
1092 | llilh\t%0,%i1 | |
1093 | llill\t%0,%i1 | |
1094 | lay\t%0,%a1 | |
d40c829f UW |
1095 | lr\t%0,%1 |
1096 | l\t%0,%1 | |
1097 | ly\t%0,%1 | |
1098 | st\t%1,%0 | |
1099 | sty\t%1,%0 | |
1100 | ler\t%0,%1 | |
1101 | le\t%0,%1 | |
1102 | ley\t%0,%1 | |
1103 | ste\t%1,%0 | |
1104 | stey\t%1,%0 | |
c5aa1d12 UW |
1105 | ear\t%0,%1 |
1106 | sar\t%0,%1 | |
1107 | stam\t%1,%1,%S0 | |
1108 | lam\t%0,%0,%S1 | |
19b63d8e | 1109 | #" |
b628bd8e UW |
1110 | [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY, |
1111 | RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS") | |
1112 | (set_attr "type" "*,*,*,la,lr,load,load,store,store, | |
cfdb984b | 1113 | floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")]) |
f19a9af7 AK |
1114 | |
1115 | (define_insn "*movsi_esa" | |
c5aa1d12 UW |
1116 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q") |
1117 | (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))] | |
f19a9af7 AK |
1118 | "!TARGET_ZARCH" |
1119 | "@ | |
1120 | lhi\t%0,%h1 | |
1121 | lr\t%0,%1 | |
1122 | l\t%0,%1 | |
1123 | st\t%1,%0 | |
1124 | ler\t%0,%1 | |
1125 | le\t%0,%1 | |
1126 | ste\t%1,%0 | |
c5aa1d12 UW |
1127 | ear\t%0,%1 |
1128 | sar\t%0,%1 | |
1129 | stam\t%1,%1,%S0 | |
1130 | lam\t%0,%0,%S1 | |
19b63d8e | 1131 | #" |
c5aa1d12 | 1132 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS") |
cfdb984b | 1133 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")]) |
9db1d521 | 1134 | |
84817c5d UW |
1135 | (define_peephole2 |
1136 | [(set (match_operand:SI 0 "register_operand" "") | |
1137 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1138 | "!FP_REG_P (operands[0]) | |
1139 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1140 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1141 | && get_pool_mode (operands[1]) == SImode | |
1142 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1143 | [(set (match_dup 0) (match_dup 2))] | |
1144 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 1145 | |
7bdff56f UW |
1146 | (define_insn "*la_31" |
1147 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1148 | (match_operand:QI 1 "address_operand" "U,W"))] | |
1149 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" | |
1150 | "@ | |
1151 | la\t%0,%a1 | |
1152 | lay\t%0,%a1" | |
1153 | [(set_attr "op_type" "RX,RXY") | |
1154 | (set_attr "type" "la")]) | |
1155 | ||
1156 | (define_peephole2 | |
1157 | [(parallel | |
1158 | [(set (match_operand:SI 0 "register_operand" "") | |
1159 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1160 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1161 | "!TARGET_64BIT |
e1d5ee28 | 1162 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1163 | [(set (match_dup 0) (match_dup 1))] |
1164 | "") | |
1165 | ||
1166 | (define_peephole2 | |
1167 | [(set (match_operand:SI 0 "register_operand" "") | |
1168 | (match_operand:SI 1 "register_operand" "")) | |
1169 | (parallel | |
1170 | [(set (match_dup 0) | |
1171 | (plus:SI (match_dup 0) | |
1172 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1173 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1174 | "!TARGET_64BIT |
1175 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1176 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1177 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
1178 | "") | |
1179 | ||
1180 | (define_insn "*la_31_and" | |
1181 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1182 | (and:SI (match_operand:QI 1 "address_operand" "U,W") | |
1183 | (const_int 2147483647)))] | |
1184 | "!TARGET_64BIT" | |
1185 | "@ | |
1186 | la\t%0,%a1 | |
1187 | lay\t%0,%a1" | |
1188 | [(set_attr "op_type" "RX,RXY") | |
1189 | (set_attr "type" "la")]) | |
1190 | ||
1191 | (define_insn_and_split "*la_31_and_cc" | |
1192 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1193 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
1194 | (const_int 2147483647))) | |
ae156f85 | 1195 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
1196 | "!TARGET_64BIT" |
1197 | "#" | |
1198 | "&& reload_completed" | |
1199 | [(set (match_dup 0) | |
1200 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
1201 | "" | |
1202 | [(set_attr "op_type" "RX") | |
1203 | (set_attr "type" "la")]) | |
1204 | ||
1205 | (define_insn "force_la_31" | |
1206 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1207 | (match_operand:QI 1 "address_operand" "U,W")) | |
1208 | (use (const_int 0))] | |
1209 | "!TARGET_64BIT" | |
1210 | "@ | |
1211 | la\t%0,%a1 | |
1212 | lay\t%0,%a1" | |
1213 | [(set_attr "op_type" "RX") | |
1214 | (set_attr "type" "la")]) | |
1215 | ||
1216 | (define_expand "reload_insi" | |
1217 | [(parallel [(match_operand:SI 0 "register_operand" "=a") | |
1218 | (match_operand:SI 1 "s390_plus_operand" "") | |
1219 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1220 | "!TARGET_64BIT" | |
1221 | { | |
1222 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1223 | DONE; | |
1224 | }) | |
1225 | ||
9db1d521 HP |
1226 | ; |
1227 | ; movhi instruction pattern(s). | |
1228 | ; | |
1229 | ||
02ed3c5e UW |
1230 | (define_expand "movhi" |
1231 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
1232 | (match_operand:HI 1 "general_operand" ""))] | |
1233 | "" | |
1234 | { | |
2f7e5a0d | 1235 | /* Make it explicit that loading a register from memory |
02ed3c5e UW |
1236 | always sign-extends (at least) to SImode. */ |
1237 | if (optimize && !no_new_pseudos | |
1238 | && register_operand (operands[0], VOIDmode) | |
8fff4fc1 | 1239 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
1240 | { |
1241 | rtx tmp = gen_reg_rtx (SImode); | |
1242 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
1243 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); | |
1244 | operands[1] = gen_lowpart (HImode, tmp); | |
1245 | } | |
1246 | }) | |
1247 | ||
1248 | (define_insn "*movhi" | |
d3632d41 UW |
1249 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q") |
1250 | (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))] | |
9db1d521 HP |
1251 | "" |
1252 | "@ | |
d40c829f UW |
1253 | lr\t%0,%1 |
1254 | lhi\t%0,%h1 | |
1255 | lh\t%0,%1 | |
1256 | lhy\t%0,%1 | |
1257 | sth\t%1,%0 | |
1258 | sthy\t%1,%0 | |
19b63d8e | 1259 | #" |
d3632d41 | 1260 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS") |
b628bd8e | 1261 | (set_attr "type" "lr,*,*,*,store,store,*")]) |
9db1d521 | 1262 | |
84817c5d UW |
1263 | (define_peephole2 |
1264 | [(set (match_operand:HI 0 "register_operand" "") | |
1265 | (mem:HI (match_operand 1 "address_operand" "")))] | |
1266 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1267 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1268 | && get_pool_mode (operands[1]) == HImode | |
1269 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1270 | [(set (match_dup 0) (match_dup 2))] | |
1271 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1272 | |
9db1d521 HP |
1273 | ; |
1274 | ; movqi instruction pattern(s). | |
1275 | ; | |
1276 | ||
02ed3c5e UW |
1277 | (define_expand "movqi" |
1278 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1279 | (match_operand:QI 1 "general_operand" ""))] | |
1280 | "" | |
1281 | { | |
c19ec8f9 | 1282 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 1283 | is just as fast as a QImode load. */ |
c19ec8f9 | 1284 | if (TARGET_ZARCH && optimize && !no_new_pseudos |
02ed3c5e | 1285 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1286 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 1287 | { |
c19ec8f9 UW |
1288 | rtx tmp = gen_reg_rtx (word_mode); |
1289 | rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]); | |
02ed3c5e UW |
1290 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); |
1291 | operands[1] = gen_lowpart (QImode, tmp); | |
1292 | } | |
1293 | }) | |
4023fb28 | 1294 | |
02ed3c5e | 1295 | (define_insn "*movqi" |
d3632d41 UW |
1296 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") |
1297 | (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))] | |
9db1d521 HP |
1298 | "" |
1299 | "@ | |
d40c829f UW |
1300 | lr\t%0,%1 |
1301 | lhi\t%0,%b1 | |
1302 | ic\t%0,%1 | |
1303 | icy\t%0,%1 | |
1304 | stc\t%1,%0 | |
1305 | stcy\t%1,%0 | |
fc0ea003 UW |
1306 | mvi\t%S0,%b1 |
1307 | mviy\t%S0,%b1 | |
19b63d8e | 1308 | #" |
d3632d41 | 1309 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") |
b628bd8e | 1310 | (set_attr "type" "lr,*,*,*,store,store,store,store,*")]) |
9db1d521 | 1311 | |
84817c5d UW |
1312 | (define_peephole2 |
1313 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1314 | (mem:QI (match_operand 1 "address_operand" "")))] | |
1315 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1316 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1317 | && get_pool_mode (operands[1]) == QImode | |
1318 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1319 | [(set (match_dup 0) (match_dup 2))] | |
1320 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1321 | |
9db1d521 | 1322 | ; |
05b9aaaa | 1323 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
1324 | ; |
1325 | ||
1326 | (define_insn "*movstrictqi" | |
d3632d41 UW |
1327 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
1328 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 1329 | "" |
d3632d41 | 1330 | "@ |
d40c829f UW |
1331 | ic\t%0,%1 |
1332 | icy\t%0,%1" | |
d3632d41 | 1333 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 HP |
1334 | |
1335 | ; | |
1336 | ; movstricthi instruction pattern(s). | |
1337 | ; | |
1338 | ||
1339 | (define_insn "*movstricthi" | |
d3632d41 | 1340 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 1341 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 1342 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 1343 | "" |
d3632d41 | 1344 | "@ |
fc0ea003 UW |
1345 | icm\t%0,3,%S1 |
1346 | icmy\t%0,3,%S1" | |
d3632d41 | 1347 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 HP |
1348 | |
1349 | ; | |
1350 | ; movstrictsi instruction pattern(s). | |
1351 | ; | |
1352 | ||
05b9aaaa | 1353 | (define_insn "movstrictsi" |
c5aa1d12 UW |
1354 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
1355 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9db1d521 HP |
1356 | "TARGET_64BIT" |
1357 | "@ | |
d40c829f UW |
1358 | lr\t%0,%1 |
1359 | l\t%0,%1 | |
c5aa1d12 UW |
1360 | ly\t%0,%1 |
1361 | ear\t%0,%1" | |
1362 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
1363 | (set_attr "type" "lr,load,load,*")]) | |
9db1d521 HP |
1364 | |
1365 | ; | |
1366 | ; movdf instruction pattern(s). | |
1367 | ; | |
1368 | ||
1369 | (define_expand "movdf" | |
1370 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1371 | (match_operand:DF 1 "general_operand" ""))] | |
1372 | "" | |
13c025c1 | 1373 | "") |
9db1d521 HP |
1374 | |
1375 | (define_insn "*movdf_64" | |
d096725d AS |
1376 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q") |
1377 | (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))] | |
4023fb28 | 1378 | "TARGET_64BIT" |
9db1d521 | 1379 | "@ |
d096725d | 1380 | lzdr\t%0 |
d40c829f UW |
1381 | ldr\t%0,%1 |
1382 | ld\t%0,%1 | |
1383 | ldy\t%0,%1 | |
1384 | std\t%1,%0 | |
1385 | stdy\t%1,%0 | |
1386 | lgr\t%0,%1 | |
1387 | lg\t%0,%1 | |
1388 | stg\t%1,%0 | |
19b63d8e | 1389 | #" |
d096725d AS |
1390 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") |
1391 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")]) | |
9db1d521 HP |
1392 | |
1393 | (define_insn "*movdf_31" | |
d096725d AS |
1394 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,Q,d,o,Q") |
1395 | (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,d,dKm,d,Q"))] | |
4023fb28 | 1396 | "!TARGET_64BIT" |
9db1d521 | 1397 | "@ |
d096725d | 1398 | lzdr\t%0 |
d40c829f UW |
1399 | ldr\t%0,%1 |
1400 | ld\t%0,%1 | |
1401 | ldy\t%0,%1 | |
1402 | std\t%1,%0 | |
1403 | stdy\t%1,%0 | |
fc0ea003 UW |
1404 | lm\t%0,%N0,%S1 |
1405 | stm\t%1,%N1,%S0 | |
4023fb28 | 1406 | # |
9b7c75b9 | 1407 | # |
19b63d8e | 1408 | #" |
d096725d AS |
1409 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RS,*,*,SS") |
1410 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lm,stm,*,*,*")]) | |
4023fb28 UW |
1411 | |
1412 | (define_split | |
1413 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1414 | (match_operand:DF 1 "general_operand" ""))] | |
1415 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 1416 | && s390_split_ok_p (operands[0], operands[1], DFmode, 0)" |
4023fb28 UW |
1417 | [(set (match_dup 2) (match_dup 4)) |
1418 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1419 | { |
dc65c307 UW |
1420 | operands[2] = operand_subword (operands[0], 0, 0, DFmode); |
1421 | operands[3] = operand_subword (operands[0], 1, 0, DFmode); | |
1422 | operands[4] = operand_subword (operands[1], 0, 0, DFmode); | |
1423 | operands[5] = operand_subword (operands[1], 1, 0, DFmode); | |
1424 | }) | |
1425 | ||
1426 | (define_split | |
1427 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1428 | (match_operand:DF 1 "general_operand" ""))] | |
1429 | "!TARGET_64BIT && reload_completed | |
1430 | && s390_split_ok_p (operands[0], operands[1], DFmode, 1)" | |
1431 | [(set (match_dup 2) (match_dup 4)) | |
1432 | (set (match_dup 3) (match_dup 5))] | |
1433 | { | |
1434 | operands[2] = operand_subword (operands[0], 1, 0, DFmode); | |
1435 | operands[3] = operand_subword (operands[0], 0, 0, DFmode); | |
1436 | operands[4] = operand_subword (operands[1], 1, 0, DFmode); | |
1437 | operands[5] = operand_subword (operands[1], 0, 0, DFmode); | |
1438 | }) | |
9db1d521 | 1439 | |
4023fb28 UW |
1440 | (define_split |
1441 | [(set (match_operand:DF 0 "register_operand" "") | |
1442 | (match_operand:DF 1 "memory_operand" ""))] | |
1443 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 1444 | && !FP_REG_P (operands[0]) |
4023fb28 | 1445 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1446 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1447 | { |
1448 | rtx addr = operand_subword (operands[0], 1, 0, DFmode); | |
1449 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1450 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1451 | }) |
1452 | ||
1453 | (define_expand "reload_outdf" | |
9c3c3dcc | 1454 | [(parallel [(match_operand:DF 0 "" "") |
dc65c307 UW |
1455 | (match_operand:DF 1 "register_operand" "d") |
1456 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1457 | "!TARGET_64BIT" | |
1458 | { | |
9c3c3dcc | 1459 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1460 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1461 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1462 | emit_move_insn (operands[0], operands[1]); | |
1463 | DONE; | |
1464 | }) | |
9db1d521 HP |
1465 | |
1466 | ; | |
1467 | ; movsf instruction pattern(s). | |
1468 | ; | |
1469 | ||
13c025c1 | 1470 | (define_insn "movsf" |
d096725d AS |
1471 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q") |
1472 | (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))] | |
4023fb28 | 1473 | "" |
9db1d521 | 1474 | "@ |
d096725d | 1475 | lzer\t%0 |
d40c829f UW |
1476 | ler\t%0,%1 |
1477 | le\t%0,%1 | |
1478 | ley\t%0,%1 | |
1479 | ste\t%1,%0 | |
1480 | stey\t%1,%0 | |
1481 | lr\t%0,%1 | |
1482 | l\t%0,%1 | |
1483 | ly\t%0,%1 | |
1484 | st\t%1,%0 | |
1485 | sty\t%1,%0 | |
19b63d8e | 1486 | #" |
d096725d AS |
1487 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") |
1488 | (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf, | |
b628bd8e | 1489 | lr,load,load,store,store,*")]) |
4023fb28 | 1490 | |
9dc62c00 AK |
1491 | ; |
1492 | ; movcc instruction pattern | |
1493 | ; | |
1494 | ||
1495 | (define_insn "movcc" | |
1496 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
1497 | (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))] | |
1498 | "" | |
1499 | "@ | |
1500 | lr\t%0,%1 | |
1501 | tmh\t%1,12288 | |
1502 | ipm\t%0 | |
1503 | st\t%0,%1 | |
1504 | sty\t%0,%1 | |
1505 | l\t%1,%0 | |
1506 | ly\t%1,%0" | |
8dd3b235 AK |
1507 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
1508 | (set_attr "type" "lr,*,*,store,store,load,load")]) | |
9dc62c00 | 1509 | |
19b63d8e UW |
1510 | ; |
1511 | ; Block move (MVC) patterns. | |
1512 | ; | |
1513 | ||
1514 | (define_insn "*mvc" | |
1515 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
1516 | (match_operand:BLK 1 "memory_operand" "Q")) | |
1517 | (use (match_operand 2 "const_int_operand" "n"))] | |
1518 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1519 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 1520 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1521 | |
1522 | (define_split | |
1523 | [(set (match_operand 0 "memory_operand" "") | |
1524 | (match_operand 1 "memory_operand" ""))] | |
1525 | "reload_completed | |
1526 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1527 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1528 | [(parallel | |
1529 | [(set (match_dup 0) (match_dup 1)) | |
1530 | (use (match_dup 2))])] | |
1531 | { | |
1532 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1533 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1534 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1535 | }) | |
1536 | ||
1537 | (define_peephole2 | |
1538 | [(parallel | |
1539 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1540 | (match_operand:BLK 1 "memory_operand" "")) | |
1541 | (use (match_operand 2 "const_int_operand" ""))]) | |
1542 | (parallel | |
1543 | [(set (match_operand:BLK 3 "memory_operand" "") | |
1544 | (match_operand:BLK 4 "memory_operand" "")) | |
1545 | (use (match_operand 5 "const_int_operand" ""))])] | |
1546 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
1547 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
1548 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" | |
1549 | [(parallel | |
1550 | [(set (match_dup 6) (match_dup 7)) | |
1551 | (use (match_dup 8))])] | |
1552 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
1553 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
1554 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
1555 | ||
1556 | ||
9db1d521 HP |
1557 | ; |
1558 | ; load_multiple pattern(s). | |
1559 | ; | |
22ea6b4f UW |
1560 | ; ??? Due to reload problems with replacing registers inside match_parallel |
1561 | ; we currently support load_multiple/store_multiple only after reload. | |
1562 | ; | |
9db1d521 HP |
1563 | |
1564 | (define_expand "load_multiple" | |
1565 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1566 | (match_operand 1 "" "")) | |
1567 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 1568 | "reload_completed" |
9db1d521 | 1569 | { |
c19ec8f9 | 1570 | enum machine_mode mode; |
9db1d521 HP |
1571 | int regno; |
1572 | int count; | |
1573 | rtx from; | |
4023fb28 | 1574 | int i, off; |
9db1d521 HP |
1575 | |
1576 | /* Support only loading a constant number of fixed-point registers from | |
1577 | memory and only bother with this if more than two */ | |
1578 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1579 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1580 | || INTVAL (operands[2]) > 16 |
1581 | || GET_CODE (operands[1]) != MEM | |
1582 | || GET_CODE (operands[0]) != REG | |
1583 | || REGNO (operands[0]) >= 16) | |
1584 | FAIL; | |
1585 | ||
1586 | count = INTVAL (operands[2]); | |
1587 | regno = REGNO (operands[0]); | |
c19ec8f9 UW |
1588 | mode = GET_MODE (operands[0]); |
1589 | if (mode != SImode && mode != word_mode) | |
1590 | FAIL; | |
9db1d521 HP |
1591 | |
1592 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1593 | if (no_new_pseudos) |
1594 | { | |
1595 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
1596 | { | |
1597 | from = XEXP (operands[1], 0); | |
1598 | off = 0; | |
1599 | } | |
1600 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
1601 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
1602 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
1603 | { | |
1604 | from = XEXP (XEXP (operands[1], 0), 0); | |
1605 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
1606 | } | |
1607 | else | |
1608 | FAIL; | |
4023fb28 UW |
1609 | } |
1610 | else | |
1611 | { | |
1612 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
1613 | off = 0; | |
1614 | } | |
9db1d521 HP |
1615 | |
1616 | for (i = 0; i < count; i++) | |
1617 | XVECEXP (operands[3], 0, i) | |
c19ec8f9 UW |
1618 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), |
1619 | change_address (operands[1], mode, | |
1620 | plus_constant (from, off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 1621 | }) |
9db1d521 HP |
1622 | |
1623 | (define_insn "*load_multiple_di" | |
1624 | [(match_parallel 0 "load_multiple_operation" | |
1625 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 1626 | (match_operand:DI 2 "s_operand" "QS"))])] |
22ea6b4f | 1627 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
1628 | { |
1629 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1630 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 1631 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 1632 | } |
d3632d41 | 1633 | [(set_attr "op_type" "RSY") |
4023fb28 | 1634 | (set_attr "type" "lm")]) |
9db1d521 HP |
1635 | |
1636 | (define_insn "*load_multiple_si" | |
1637 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
1638 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
1639 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 1640 | "reload_completed" |
9db1d521 HP |
1641 | { |
1642 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1643 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 1644 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 1645 | } |
d3632d41 | 1646 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1647 | (set_attr "type" "lm")]) |
9db1d521 HP |
1648 | |
1649 | ; | |
c7453384 | 1650 | ; store multiple pattern(s). |
9db1d521 HP |
1651 | ; |
1652 | ||
1653 | (define_expand "store_multiple" | |
1654 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1655 | (match_operand 1 "" "")) | |
1656 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 1657 | "reload_completed" |
9db1d521 | 1658 | { |
c19ec8f9 | 1659 | enum machine_mode mode; |
9db1d521 HP |
1660 | int regno; |
1661 | int count; | |
1662 | rtx to; | |
4023fb28 | 1663 | int i, off; |
9db1d521 HP |
1664 | |
1665 | /* Support only storing a constant number of fixed-point registers to | |
1666 | memory and only bother with this if more than two. */ | |
1667 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1668 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1669 | || INTVAL (operands[2]) > 16 |
1670 | || GET_CODE (operands[0]) != MEM | |
1671 | || GET_CODE (operands[1]) != REG | |
1672 | || REGNO (operands[1]) >= 16) | |
1673 | FAIL; | |
1674 | ||
1675 | count = INTVAL (operands[2]); | |
1676 | regno = REGNO (operands[1]); | |
c19ec8f9 UW |
1677 | mode = GET_MODE (operands[1]); |
1678 | if (mode != SImode && mode != word_mode) | |
1679 | FAIL; | |
9db1d521 HP |
1680 | |
1681 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1682 | |
1683 | if (no_new_pseudos) | |
1684 | { | |
1685 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
1686 | { | |
1687 | to = XEXP (operands[0], 0); | |
1688 | off = 0; | |
1689 | } | |
1690 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
1691 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
1692 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
1693 | { | |
1694 | to = XEXP (XEXP (operands[0], 0), 0); | |
1695 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
1696 | } | |
1697 | else | |
1698 | FAIL; | |
4023fb28 | 1699 | } |
c7453384 | 1700 | else |
4023fb28 UW |
1701 | { |
1702 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
1703 | off = 0; | |
1704 | } | |
9db1d521 HP |
1705 | |
1706 | for (i = 0; i < count; i++) | |
1707 | XVECEXP (operands[3], 0, i) | |
1708 | = gen_rtx_SET (VOIDmode, | |
c19ec8f9 UW |
1709 | change_address (operands[0], mode, |
1710 | plus_constant (to, off + i * GET_MODE_SIZE (mode))), | |
1711 | gen_rtx_REG (mode, regno + i)); | |
10bbf137 | 1712 | }) |
9db1d521 HP |
1713 | |
1714 | (define_insn "*store_multiple_di" | |
1715 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 1716 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 1717 | (match_operand:DI 2 "register_operand" "r"))])] |
22ea6b4f | 1718 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
1719 | { |
1720 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1721 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 1722 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 1723 | } |
d3632d41 | 1724 | [(set_attr "op_type" "RSY") |
4023fb28 | 1725 | (set_attr "type" "stm")]) |
9db1d521 HP |
1726 | |
1727 | ||
1728 | (define_insn "*store_multiple_si" | |
1729 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
1730 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
1731 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 1732 | "reload_completed" |
9db1d521 HP |
1733 | { |
1734 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1735 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 1736 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 1737 | } |
d3632d41 | 1738 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1739 | (set_attr "type" "stm")]) |
9db1d521 HP |
1740 | |
1741 | ;; | |
1742 | ;; String instructions. | |
1743 | ;; | |
1744 | ||
9bb86f41 UW |
1745 | (define_insn "*execute" |
1746 | [(match_parallel 0 "" | |
1747 | [(unspec [(match_operand 1 "register_operand" "a") | |
1748 | (match_operand:BLK 2 "memory_operand" "R") | |
1749 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
1750 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
1751 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
1752 | "ex\t%1,%2" | |
29a74354 UW |
1753 | [(set_attr "op_type" "RX") |
1754 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
1755 | |
1756 | ||
91d39d71 UW |
1757 | ; |
1758 | ; strlenM instruction pattern(s). | |
1759 | ; | |
1760 | ||
9db2f16d | 1761 | (define_expand "strlen<mode>" |
91d39d71 | 1762 | [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" "")) |
2f7e5a0d | 1763 | (parallel |
91d39d71 | 1764 | [(set (match_dup 4) |
9db2f16d | 1765 | (unspec:P [(const_int 0) |
91d39d71 UW |
1766 | (match_operand:BLK 1 "memory_operand" "") |
1767 | (reg:QI 0) | |
1768 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) | |
9db2f16d | 1769 | (clobber (scratch:P)) |
ae156f85 | 1770 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 1771 | (parallel |
9db2f16d AS |
1772 | [(set (match_operand:P 0 "register_operand" "") |
1773 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 1774 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 1775 | "" |
91d39d71 | 1776 | { |
9db2f16d AS |
1777 | operands[4] = gen_reg_rtx (Pmode); |
1778 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
1779 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
1780 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
1781 | }) | |
1782 | ||
9db2f16d AS |
1783 | (define_insn "*strlen<mode>" |
1784 | [(set (match_operand:P 0 "register_operand" "=a") | |
1785 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
1786 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
91d39d71 UW |
1787 | (reg:QI 0) |
1788 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) | |
9db2f16d | 1789 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 1790 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 1791 | "" |
91d39d71 | 1792 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
1793 | [(set_attr "length" "8") |
1794 | (set_attr "type" "vs")]) | |
91d39d71 | 1795 | |
9db1d521 | 1796 | ; |
70128ad9 | 1797 | ; movmemM instruction pattern(s). |
9db1d521 HP |
1798 | ; |
1799 | ||
9db2f16d | 1800 | (define_expand "movmem<mode>" |
a41c6c53 UW |
1801 | [(set (match_operand:BLK 0 "memory_operand" "") |
1802 | (match_operand:BLK 1 "memory_operand" "")) | |
9db2f16d | 1803 | (use (match_operand:GPR 2 "general_operand" "")) |
a41c6c53 UW |
1804 | (match_operand 3 "" "")] |
1805 | "" | |
70128ad9 | 1806 | "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 1807 | |
ecbe845e UW |
1808 | ; Move a block that is up to 256 bytes in length. |
1809 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 1810 | |
70128ad9 | 1811 | (define_expand "movmem_short" |
b9404c99 UW |
1812 | [(parallel |
1813 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1814 | (match_operand:BLK 1 "memory_operand" "")) | |
1815 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 1816 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
1817 | (clobber (match_dup 3))])] |
1818 | "" | |
1819 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 1820 | |
70128ad9 | 1821 | (define_insn "*movmem_short" |
9bb86f41 UW |
1822 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q") |
1823 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q")) | |
1824 | (use (match_operand 2 "nonmemory_operand" "n,a,a")) | |
1825 | (use (match_operand 3 "immediate_operand" "X,R,X")) | |
1826 | (clobber (match_scratch 4 "=X,X,&a"))] | |
b9404c99 | 1827 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
9bb86f41 UW |
1828 | && GET_MODE (operands[4]) == Pmode" |
1829 | "#" | |
b628bd8e | 1830 | [(set_attr "type" "cs")]) |
ecbe845e | 1831 | |
9bb86f41 UW |
1832 | (define_split |
1833 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1834 | (match_operand:BLK 1 "memory_operand" "")) | |
1835 | (use (match_operand 2 "const_int_operand" "")) | |
1836 | (use (match_operand 3 "immediate_operand" "")) | |
1837 | (clobber (scratch))] | |
1838 | "reload_completed" | |
1839 | [(parallel | |
1840 | [(set (match_dup 0) (match_dup 1)) | |
1841 | (use (match_dup 2))])] | |
1842 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 1843 | |
9bb86f41 UW |
1844 | (define_split |
1845 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1846 | (match_operand:BLK 1 "memory_operand" "")) | |
1847 | (use (match_operand 2 "register_operand" "")) | |
1848 | (use (match_operand 3 "memory_operand" "")) | |
1849 | (clobber (scratch))] | |
1850 | "reload_completed" | |
1851 | [(parallel | |
1852 | [(unspec [(match_dup 2) (match_dup 3) | |
1853 | (const_int 0)] UNSPEC_EXECUTE) | |
1854 | (set (match_dup 0) (match_dup 1)) | |
1855 | (use (const_int 1))])] | |
1856 | "") | |
1857 | ||
1858 | (define_split | |
1859 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1860 | (match_operand:BLK 1 "memory_operand" "")) | |
1861 | (use (match_operand 2 "register_operand" "")) | |
1862 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
1863 | (clobber (match_operand 3 "register_operand" ""))] | |
1864 | "reload_completed && TARGET_CPU_ZARCH" | |
1865 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
1866 | (parallel | |
1867 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) | |
1868 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
1869 | (set (match_dup 0) (match_dup 1)) | |
1870 | (use (const_int 1))])] | |
1871 | "operands[4] = gen_label_rtx ();") | |
1872 | ||
a41c6c53 | 1873 | ; Move a block of arbitrary length. |
9db1d521 | 1874 | |
70128ad9 | 1875 | (define_expand "movmem_long" |
b9404c99 UW |
1876 | [(parallel |
1877 | [(clobber (match_dup 2)) | |
1878 | (clobber (match_dup 3)) | |
1879 | (set (match_operand:BLK 0 "memory_operand" "") | |
1880 | (match_operand:BLK 1 "memory_operand" "")) | |
1881 | (use (match_operand 2 "general_operand" "")) | |
1882 | (use (match_dup 3)) | |
ae156f85 | 1883 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
1884 | "" |
1885 | { | |
1886 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
1887 | rtx reg0 = gen_reg_rtx (dword_mode); | |
1888 | rtx reg1 = gen_reg_rtx (dword_mode); | |
1889 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
1890 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
1891 | rtx len0 = gen_lowpart (Pmode, reg0); | |
1892 | rtx len1 = gen_lowpart (Pmode, reg1); | |
1893 | ||
1894 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
1895 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
1896 | emit_move_insn (len0, operands[2]); | |
1897 | ||
1898 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
1899 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
1900 | emit_move_insn (len1, operands[2]); | |
1901 | ||
1902 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
1903 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
1904 | operands[2] = reg0; | |
1905 | operands[3] = reg1; | |
1906 | }) | |
1907 | ||
a1aed706 AS |
1908 | (define_insn "*movmem_long" |
1909 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
1910 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
1911 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
1912 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
1913 | (use (match_dup 2)) |
1914 | (use (match_dup 3)) | |
ae156f85 | 1915 | (clobber (reg:CC CC_REGNUM))] |
a1aed706 | 1916 | "" |
d40c829f | 1917 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
1918 | [(set_attr "length" "8") |
1919 | (set_attr "type" "vs")]) | |
9db1d521 HP |
1920 | |
1921 | ; | |
57e84f18 | 1922 | ; setmemM instruction pattern(s). |
9db1d521 HP |
1923 | ; |
1924 | ||
57e84f18 | 1925 | (define_expand "setmem<mode>" |
a41c6c53 | 1926 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 1927 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 1928 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 1929 | (match_operand 3 "" "")] |
a41c6c53 | 1930 | "" |
6d057022 | 1931 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 1932 | |
a41c6c53 | 1933 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
1934 | ; The block length is taken as (operands[1] % 256) + 1. |
1935 | ||
70128ad9 | 1936 | (define_expand "clrmem_short" |
b9404c99 UW |
1937 | [(parallel |
1938 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1939 | (const_int 0)) | |
1940 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 1941 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 1942 | (clobber (match_dup 2)) |
ae156f85 | 1943 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
1944 | "" |
1945 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 1946 | |
70128ad9 | 1947 | (define_insn "*clrmem_short" |
9bb86f41 | 1948 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q") |
a41c6c53 | 1949 | (const_int 0)) |
9bb86f41 UW |
1950 | (use (match_operand 1 "nonmemory_operand" "n,a,a")) |
1951 | (use (match_operand 2 "immediate_operand" "X,R,X")) | |
1952 | (clobber (match_scratch 3 "=X,X,&a")) | |
ae156f85 | 1953 | (clobber (reg:CC CC_REGNUM))] |
b9404c99 | 1954 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode) |
9bb86f41 UW |
1955 | && GET_MODE (operands[3]) == Pmode" |
1956 | "#" | |
b628bd8e | 1957 | [(set_attr "type" "cs")]) |
9bb86f41 UW |
1958 | |
1959 | (define_split | |
1960 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1961 | (const_int 0)) | |
1962 | (use (match_operand 1 "const_int_operand" "")) | |
1963 | (use (match_operand 2 "immediate_operand" "")) | |
1964 | (clobber (scratch)) | |
ae156f85 | 1965 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
1966 | "reload_completed" |
1967 | [(parallel | |
1968 | [(set (match_dup 0) (const_int 0)) | |
1969 | (use (match_dup 1)) | |
ae156f85 | 1970 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 1971 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 1972 | |
9bb86f41 UW |
1973 | (define_split |
1974 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1975 | (const_int 0)) | |
1976 | (use (match_operand 1 "register_operand" "")) | |
1977 | (use (match_operand 2 "memory_operand" "")) | |
1978 | (clobber (scratch)) | |
ae156f85 | 1979 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
1980 | "reload_completed" |
1981 | [(parallel | |
1982 | [(unspec [(match_dup 1) (match_dup 2) | |
1983 | (const_int 0)] UNSPEC_EXECUTE) | |
1984 | (set (match_dup 0) (const_int 0)) | |
1985 | (use (const_int 1)) | |
ae156f85 | 1986 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 1987 | "") |
9db1d521 | 1988 | |
9bb86f41 UW |
1989 | (define_split |
1990 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1991 | (const_int 0)) | |
1992 | (use (match_operand 1 "register_operand" "")) | |
1993 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
1994 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 1995 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
1996 | "reload_completed && TARGET_CPU_ZARCH" |
1997 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
1998 | (parallel | |
1999 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) | |
2000 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2001 | (set (match_dup 0) (const_int 0)) | |
2002 | (use (const_int 1)) | |
ae156f85 | 2003 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
2004 | "operands[3] = gen_label_rtx ();") |
2005 | ||
6d057022 | 2006 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 2007 | |
6d057022 | 2008 | (define_expand "setmem_long" |
b9404c99 UW |
2009 | [(parallel |
2010 | [(clobber (match_dup 1)) | |
2011 | (set (match_operand:BLK 0 "memory_operand" "") | |
6d057022 | 2012 | (match_operand 2 "shift_count_operand" "")) |
b9404c99 | 2013 | (use (match_operand 1 "general_operand" "")) |
6d057022 | 2014 | (use (match_dup 3)) |
ae156f85 | 2015 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 2016 | "" |
a41c6c53 | 2017 | { |
b9404c99 UW |
2018 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; |
2019 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2020 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2021 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2022 | rtx len0 = gen_lowpart (Pmode, reg0); | |
9db1d521 | 2023 | |
b9404c99 UW |
2024 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); |
2025 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2026 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 2027 | |
b9404c99 | 2028 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 2029 | |
b9404c99 UW |
2030 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
2031 | operands[1] = reg0; | |
6d057022 | 2032 | operands[3] = reg1; |
b9404c99 | 2033 | }) |
a41c6c53 | 2034 | |
6d057022 | 2035 | (define_insn "*setmem_long" |
a1aed706 | 2036 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 AS |
2037 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
2038 | (match_operand 2 "shift_count_operand" "Y")) | |
2039 | (use (match_dup 3)) | |
a1aed706 | 2040 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 2041 | (clobber (reg:CC CC_REGNUM))] |
a1aed706 | 2042 | "" |
6d057022 | 2043 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
2044 | [(set_attr "length" "8") |
2045 | (set_attr "type" "vs")]) | |
9db1d521 HP |
2046 | |
2047 | ; | |
358b8f01 | 2048 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
2049 | ; |
2050 | ||
358b8f01 | 2051 | (define_expand "cmpmemsi" |
a41c6c53 UW |
2052 | [(set (match_operand:SI 0 "register_operand" "") |
2053 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
2054 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
2055 | (use (match_operand:SI 3 "general_operand" "")) | |
2056 | (use (match_operand:SI 4 "" ""))] | |
2057 | "" | |
c7453384 | 2058 | "s390_expand_cmpmem (operands[0], operands[1], |
a41c6c53 | 2059 | operands[2], operands[3]); DONE;") |
9db1d521 | 2060 | |
a41c6c53 UW |
2061 | ; Compare a block that is up to 256 bytes in length. |
2062 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2063 | |
b9404c99 UW |
2064 | (define_expand "cmpmem_short" |
2065 | [(parallel | |
ae156f85 | 2066 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 2067 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
2068 | (match_operand:BLK 1 "memory_operand" ""))) |
2069 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2070 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2071 | (clobber (match_dup 3))])] |
2072 | "" | |
2073 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2074 | |
b9404c99 | 2075 | (define_insn "*cmpmem_short" |
ae156f85 | 2076 | [(set (reg:CCU CC_REGNUM) |
d4f52f0e | 2077 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q") |
9bb86f41 UW |
2078 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))) |
2079 | (use (match_operand 2 "nonmemory_operand" "n,a,a")) | |
2080 | (use (match_operand 3 "immediate_operand" "X,R,X")) | |
2081 | (clobber (match_scratch 4 "=X,X,&a"))] | |
b9404c99 | 2082 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
9bb86f41 UW |
2083 | && GET_MODE (operands[4]) == Pmode" |
2084 | "#" | |
b628bd8e | 2085 | [(set_attr "type" "cs")]) |
9db1d521 | 2086 | |
9bb86f41 | 2087 | (define_split |
ae156f85 | 2088 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
2089 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
2090 | (match_operand:BLK 1 "memory_operand" ""))) | |
2091 | (use (match_operand 2 "const_int_operand" "")) | |
2092 | (use (match_operand 3 "immediate_operand" "")) | |
2093 | (clobber (scratch))] | |
2094 | "reload_completed" | |
2095 | [(parallel | |
ae156f85 | 2096 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
2097 | (use (match_dup 2))])] |
2098 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 2099 | |
9bb86f41 | 2100 | (define_split |
ae156f85 | 2101 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
2102 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
2103 | (match_operand:BLK 1 "memory_operand" ""))) | |
2104 | (use (match_operand 2 "register_operand" "")) | |
2105 | (use (match_operand 3 "memory_operand" "")) | |
2106 | (clobber (scratch))] | |
2107 | "reload_completed" | |
2108 | [(parallel | |
2109 | [(unspec [(match_dup 2) (match_dup 3) | |
2110 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 2111 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
2112 | (use (const_int 1))])] |
2113 | "") | |
2114 | ||
2115 | (define_split | |
ae156f85 | 2116 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
2117 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
2118 | (match_operand:BLK 1 "memory_operand" ""))) | |
2119 | (use (match_operand 2 "register_operand" "")) | |
2120 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2121 | (clobber (match_operand 3 "register_operand" ""))] | |
2122 | "reload_completed && TARGET_CPU_ZARCH" | |
2123 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
2124 | (parallel | |
2125 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) | |
2126 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
ae156f85 | 2127 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
2128 | (use (const_int 1))])] |
2129 | "operands[4] = gen_label_rtx ();") | |
2130 | ||
a41c6c53 | 2131 | ; Compare a block of arbitrary length. |
9db1d521 | 2132 | |
b9404c99 UW |
2133 | (define_expand "cmpmem_long" |
2134 | [(parallel | |
2135 | [(clobber (match_dup 2)) | |
2136 | (clobber (match_dup 3)) | |
ae156f85 | 2137 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 2138 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
2139 | (match_operand:BLK 1 "memory_operand" ""))) |
2140 | (use (match_operand 2 "general_operand" "")) | |
2141 | (use (match_dup 3))])] | |
2142 | "" | |
2143 | { | |
2144 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
2145 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2146 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2147 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2148 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
2149 | rtx len0 = gen_lowpart (Pmode, reg0); | |
2150 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2151 | ||
2152 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
2153 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2154 | emit_move_insn (len0, operands[2]); | |
2155 | ||
2156 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
2157 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2158 | emit_move_insn (len1, operands[2]); | |
2159 | ||
2160 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2161 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2162 | operands[2] = reg0; | |
2163 | operands[3] = reg1; | |
2164 | }) | |
2165 | ||
a1aed706 AS |
2166 | (define_insn "*cmpmem_long" |
2167 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2168 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 2169 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
2170 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
2171 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
2172 | (use (match_dup 2)) |
2173 | (use (match_dup 3))] | |
a1aed706 | 2174 | "" |
287ff198 | 2175 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2176 | [(set_attr "length" "8") |
2177 | (set_attr "type" "vs")]) | |
9db1d521 | 2178 | |
02887425 UW |
2179 | ; Convert CCUmode condition code to integer. |
2180 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 2181 | |
02887425 | 2182 | (define_insn_and_split "cmpint" |
9db1d521 | 2183 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 UW |
2184 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
2185 | UNSPEC_CMPINT)) | |
ae156f85 | 2186 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2187 | "" |
02887425 UW |
2188 | "#" |
2189 | "reload_completed" | |
2190 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
2191 | (parallel | |
2192 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 2193 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
2194 | |
2195 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 2196 | [(set (reg CC_REGNUM) |
02887425 UW |
2197 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
2198 | UNSPEC_CMPINT) | |
2199 | (const_int 0))) | |
2200 | (set (match_operand:SI 0 "register_operand" "=d") | |
2201 | (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))] | |
2202 | "s390_match_ccmode (insn, CCSmode)" | |
2203 | "#" | |
2204 | "&& reload_completed" | |
2205 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
2206 | (parallel | |
2207 | [(set (match_dup 2) (match_dup 3)) | |
2208 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 2209 | { |
02887425 UW |
2210 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
2211 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
2212 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
2213 | }) | |
9db1d521 | 2214 | |
02887425 | 2215 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 2216 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 UW |
2217 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
2218 | UNSPEC_CMPINT))) | |
ae156f85 | 2219 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2220 | "TARGET_64BIT" |
02887425 UW |
2221 | "#" |
2222 | "&& reload_completed" | |
2223 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
2224 | (parallel | |
2225 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 2226 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
2227 | |
2228 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 2229 | [(set (reg CC_REGNUM) |
02887425 UW |
2230 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
2231 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] | |
2232 | UNSPEC_CMPINT) 0) | |
2233 | (const_int 32)) (const_int 32)) | |
2234 | (const_int 0))) | |
2235 | (set (match_operand:DI 0 "register_operand" "=d") | |
2236 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))] | |
2237 | "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT" | |
2238 | "#" | |
2239 | "&& reload_completed" | |
2240 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
2241 | (parallel | |
2242 | [(set (match_dup 2) (match_dup 3)) | |
2243 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 2244 | { |
02887425 UW |
2245 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
2246 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
2247 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
2248 | }) | |
9db1d521 | 2249 | |
4023fb28 | 2250 | |
9db1d521 HP |
2251 | ;; |
2252 | ;;- Conversion instructions. | |
2253 | ;; | |
2254 | ||
4023fb28 | 2255 | |
f52c81dd | 2256 | (define_insn "*sethigh<mode>si" |
d3632d41 | 2257 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
f52c81dd | 2258 | (unspec:SI [(match_operand:HQI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
ae156f85 | 2259 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 2260 | "" |
d3632d41 | 2261 | "@ |
f52c81dd AS |
2262 | icm\t%0,<icm_hi>,%S1 |
2263 | icmy\t%0,<icm_hi>,%S1" | |
d3632d41 | 2264 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 UW |
2265 | |
2266 | (define_insn "*sethighqidi_64" | |
2267 | [(set (match_operand:DI 0 "register_operand" "=d") | |
10bbf137 | 2268 | (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH)) |
ae156f85 | 2269 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 2270 | "TARGET_64BIT" |
fc0ea003 | 2271 | "icmh\t%0,8,%S1" |
d3632d41 | 2272 | [(set_attr "op_type" "RSY")]) |
4023fb28 UW |
2273 | |
2274 | (define_insn "*sethighqidi_31" | |
d3632d41 | 2275 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
10bbf137 | 2276 | (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
ae156f85 | 2277 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 2278 | "!TARGET_64BIT" |
d3632d41 | 2279 | "@ |
fc0ea003 UW |
2280 | icm\t%0,8,%S1 |
2281 | icmy\t%0,8,%S1" | |
d3632d41 | 2282 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 | 2283 | |
cc7ab9b7 UW |
2284 | (define_insn_and_split "*extractqi" |
2285 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2286 | (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") | |
2287 | (match_operand 2 "const_int_operand" "n") | |
2288 | (const_int 0))) | |
ae156f85 | 2289 | (clobber (reg:CC CC_REGNUM))] |
cc7ab9b7 | 2290 | "!TARGET_64BIT |
4023fb28 | 2291 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8" |
cc7ab9b7 UW |
2292 | "#" |
2293 | "&& reload_completed" | |
4023fb28 | 2294 | [(parallel |
10bbf137 | 2295 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
ae156f85 | 2296 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 2297 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] |
4023fb28 UW |
2298 | { |
2299 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
2300 | operands[1] = change_address (operands[1], QImode, 0); | |
b628bd8e | 2301 | }) |
4023fb28 | 2302 | |
cc7ab9b7 UW |
2303 | (define_insn_and_split "*extracthi" |
2304 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2305 | (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") | |
2306 | (match_operand 2 "const_int_operand" "n") | |
2307 | (const_int 0))) | |
ae156f85 | 2308 | (clobber (reg:CC CC_REGNUM))] |
cc7ab9b7 | 2309 | "!TARGET_64BIT |
4023fb28 | 2310 | && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16" |
cc7ab9b7 UW |
2311 | "#" |
2312 | "&& reload_completed" | |
4023fb28 | 2313 | [(parallel |
10bbf137 | 2314 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
ae156f85 | 2315 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 2316 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] |
4023fb28 UW |
2317 | { |
2318 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
2319 | operands[1] = change_address (operands[1], HImode, 0); | |
b628bd8e | 2320 | }) |
4023fb28 | 2321 | |
9db1d521 HP |
2322 | ; |
2323 | ; extendsidi2 instruction pattern(s). | |
2324 | ; | |
2325 | ||
4023fb28 UW |
2326 | (define_expand "extendsidi2" |
2327 | [(set (match_operand:DI 0 "register_operand" "") | |
2328 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2329 | "" | |
2330 | " | |
2331 | { | |
2332 | if (!TARGET_64BIT) | |
2333 | { | |
9f37ccb1 UW |
2334 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2335 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); | |
2336 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
2337 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
2338 | DONE; |
2339 | } | |
2340 | } | |
2341 | ") | |
2342 | ||
2343 | (define_insn "*extendsidi2" | |
9db1d521 HP |
2344 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2345 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2346 | "TARGET_64BIT" | |
2347 | "@ | |
d40c829f UW |
2348 | lgfr\t%0,%1 |
2349 | lgf\t%0,%1" | |
d3632d41 | 2350 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2351 | |
9db1d521 | 2352 | ; |
f6ee577c | 2353 | ; extend(hi|qi)di2 instruction pattern(s). |
9db1d521 HP |
2354 | ; |
2355 | ||
f6ee577c | 2356 | (define_expand "extend<mode>di2" |
4023fb28 | 2357 | [(set (match_operand:DI 0 "register_operand" "") |
f6ee577c | 2358 | (sign_extend:DI (match_operand:HQI 1 "register_operand" "")))] |
4023fb28 UW |
2359 | "" |
2360 | " | |
2361 | { | |
2362 | if (!TARGET_64BIT) | |
2363 | { | |
2364 | rtx tmp = gen_reg_rtx (SImode); | |
f6ee577c | 2365 | emit_insn (gen_extend<mode>si2 (tmp, operands[1])); |
4023fb28 UW |
2366 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
2367 | DONE; | |
2368 | } | |
2369 | else | |
2370 | { | |
f6ee577c AS |
2371 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE (DImode) - |
2372 | GET_MODE_BITSIZE (<MODE>mode)); | |
4023fb28 | 2373 | operands[1] = gen_lowpart (DImode, operands[1]); |
f6ee577c AS |
2374 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); |
2375 | emit_insn (gen_ashrdi3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
2376 | DONE; |
2377 | } | |
2378 | } | |
2379 | ") | |
2380 | ||
2381 | (define_insn "*extendhidi2" | |
9db1d521 | 2382 | [(set (match_operand:DI 0 "register_operand" "=d") |
4023fb28 | 2383 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] |
9db1d521 | 2384 | "TARGET_64BIT" |
d40c829f | 2385 | "lgh\t%0,%1" |
d3632d41 | 2386 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2387 | |
d3632d41 UW |
2388 | (define_insn "*extendqidi2" |
2389 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2390 | (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))] | |
2391 | "TARGET_64BIT && TARGET_LONG_DISPLACEMENT" | |
d40c829f | 2392 | "lgb\t%0,%1" |
d3632d41 UW |
2393 | [(set_attr "op_type" "RXY")]) |
2394 | ||
19796784 AK |
2395 | (define_insn_and_split "*extendqidi2_short_displ" |
2396 | [(set (match_operand:DI 0 "register_operand" "=d") | |
59f8a8be | 2397 | (sign_extend:DI (match_operand:QI 1 "s_operand" "Q"))) |
ae156f85 | 2398 | (clobber (reg:CC CC_REGNUM))] |
19796784 AK |
2399 | "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT" |
2400 | "#" | |
2401 | "&& reload_completed" | |
4023fb28 | 2402 | [(parallel |
10bbf137 | 2403 | [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH)) |
ae156f85 | 2404 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 UW |
2405 | (parallel |
2406 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56))) | |
ae156f85 | 2407 | (clobber (reg:CC CC_REGNUM))])] |
4023fb28 | 2408 | "") |
9db1d521 HP |
2409 | |
2410 | ; | |
f6ee577c | 2411 | ; extend(hi|qi)si2 instruction pattern(s). |
9db1d521 HP |
2412 | ; |
2413 | ||
f6ee577c | 2414 | (define_expand "extend<mode>si2" |
4023fb28 | 2415 | [(set (match_operand:SI 0 "register_operand" "") |
f6ee577c | 2416 | (sign_extend:SI (match_operand:HQI 1 "register_operand" "")))] |
9db1d521 | 2417 | "" |
4023fb28 UW |
2418 | " |
2419 | { | |
f6ee577c AS |
2420 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE(SImode) - |
2421 | GET_MODE_BITSIZE(<MODE>mode)); | |
4023fb28 | 2422 | operands[1] = gen_lowpart (SImode, operands[1]); |
f6ee577c AS |
2423 | emit_insn (gen_ashlsi3 (operands[0], operands[1], bitcount)); |
2424 | emit_insn (gen_ashrsi3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
2425 | DONE; |
2426 | } | |
2427 | ") | |
9db1d521 | 2428 | |
4023fb28 | 2429 | (define_insn "*extendhisi2" |
d3632d41 UW |
2430 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
2431 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
4023fb28 | 2432 | "" |
d3632d41 | 2433 | "@ |
d40c829f UW |
2434 | lh\t%0,%1 |
2435 | lhy\t%0,%1" | |
d3632d41 | 2436 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 | 2437 | |
d3632d41 UW |
2438 | (define_insn "*extendqisi2" |
2439 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2440 | (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2441 | "TARGET_LONG_DISPLACEMENT" |
d40c829f | 2442 | "lb\t%0,%1" |
d3632d41 UW |
2443 | [(set_attr "op_type" "RXY")]) |
2444 | ||
eb457a7a | 2445 | (define_insn_and_split "*extendqisi2_short_displ" |
19796784 | 2446 | [(set (match_operand:SI 0 "register_operand" "=d") |
59f8a8be | 2447 | (sign_extend:SI (match_operand:QI 1 "s_operand" "Q"))) |
ae156f85 | 2448 | (clobber (reg:CC CC_REGNUM))] |
19796784 AK |
2449 | "!TARGET_LONG_DISPLACEMENT" |
2450 | "#" | |
2451 | "&& reload_completed" | |
4023fb28 | 2452 | [(parallel |
10bbf137 | 2453 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
ae156f85 | 2454 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 UW |
2455 | (parallel |
2456 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24))) | |
ae156f85 | 2457 | (clobber (reg:CC CC_REGNUM))])] |
4023fb28 | 2458 | "") |
9db1d521 HP |
2459 | |
2460 | ; | |
2461 | ; extendqihi2 instruction pattern(s). | |
2462 | ; | |
2463 | ||
9db1d521 HP |
2464 | |
2465 | ; | |
2466 | ; zero_extendsidi2 instruction pattern(s). | |
2467 | ; | |
2468 | ||
4023fb28 UW |
2469 | (define_expand "zero_extendsidi2" |
2470 | [(set (match_operand:DI 0 "register_operand" "") | |
2471 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2472 | "" | |
2473 | " | |
2474 | { | |
2475 | if (!TARGET_64BIT) | |
2476 | { | |
9f37ccb1 UW |
2477 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2478 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); | |
2479 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
2480 | DONE; |
2481 | } | |
2482 | } | |
2483 | ") | |
2484 | ||
2485 | (define_insn "*zero_extendsidi2" | |
9db1d521 HP |
2486 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2487 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2488 | "TARGET_64BIT" | |
2489 | "@ | |
d40c829f UW |
2490 | llgfr\t%0,%1 |
2491 | llgf\t%0,%1" | |
d3632d41 | 2492 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2493 | |
9db1d521 | 2494 | ; |
f6ee577c | 2495 | ; zero_extend(hi|qi)di2 instruction pattern(s). |
9db1d521 HP |
2496 | ; |
2497 | ||
f6ee577c | 2498 | (define_expand "zero_extend<mode>di2" |
4023fb28 | 2499 | [(set (match_operand:DI 0 "register_operand" "") |
f6ee577c | 2500 | (zero_extend:DI (match_operand:HQI 1 "register_operand" "")))] |
4023fb28 UW |
2501 | "" |
2502 | " | |
2503 | { | |
2504 | if (!TARGET_64BIT) | |
2505 | { | |
2506 | rtx tmp = gen_reg_rtx (SImode); | |
f6ee577c | 2507 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); |
4023fb28 UW |
2508 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); |
2509 | DONE; | |
2510 | } | |
2511 | else | |
2512 | { | |
f6ee577c AS |
2513 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - |
2514 | GET_MODE_BITSIZE(<MODE>mode)); | |
4023fb28 | 2515 | operands[1] = gen_lowpart (DImode, operands[1]); |
f6ee577c AS |
2516 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); |
2517 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
2518 | DONE; |
2519 | } | |
2520 | } | |
2521 | ") | |
9db1d521 | 2522 | |
f6ee577c | 2523 | (define_insn "*zero_extend<mode>di2" |
4023fb28 | 2524 | [(set (match_operand:DI 0 "register_operand" "=d") |
f6ee577c | 2525 | (zero_extend:DI (match_operand:HQI 1 "memory_operand" "m")))] |
9db1d521 | 2526 | "TARGET_64BIT" |
f6ee577c | 2527 | "llg<hc>\t%0,%1" |
d3632d41 | 2528 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2529 | |
288e517f AK |
2530 | ; |
2531 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
2532 | ; | |
2533 | ||
d6083c7d UW |
2534 | (define_insn "*llgt_sidi" |
2535 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2536 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) | |
2537 | (const_int 2147483647)))] | |
2538 | "TARGET_64BIT" | |
2539 | "llgt\t%0,%1" | |
2540 | [(set_attr "op_type" "RXE")]) | |
2541 | ||
2542 | (define_insn_and_split "*llgt_sidi_split" | |
2543 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2544 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) | |
2545 | (const_int 2147483647))) | |
ae156f85 | 2546 | (clobber (reg:CC CC_REGNUM))] |
d6083c7d UW |
2547 | "TARGET_64BIT" |
2548 | "#" | |
2549 | "&& reload_completed" | |
2550 | [(set (match_dup 0) | |
2551 | (and:DI (subreg:DI (match_dup 1) 0) | |
2552 | (const_int 2147483647)))] | |
2553 | "") | |
2554 | ||
288e517f AK |
2555 | (define_insn "*llgt_sisi" |
2556 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
2557 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m") | |
2558 | (const_int 2147483647)))] | |
2559 | "TARGET_64BIT" | |
2560 | "@ | |
2561 | llgtr\t%0,%1 | |
2562 | llgt\t%0,%1" | |
2563 | [(set_attr "op_type" "RRE,RXE")]) | |
2564 | ||
288e517f AK |
2565 | (define_insn "*llgt_didi" |
2566 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2567 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
2568 | (const_int 2147483647)))] | |
2569 | "TARGET_64BIT" | |
2570 | "@ | |
2571 | llgtr\t%0,%1 | |
2572 | llgt\t%0,%N1" | |
2573 | [(set_attr "op_type" "RRE,RXE")]) | |
2574 | ||
f19a9af7 | 2575 | (define_split |
f6ee577c AS |
2576 | [(set (match_operand:GPR 0 "register_operand" "") |
2577 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
2578 | (const_int 2147483647))) | |
ae156f85 | 2579 | (clobber (reg:CC CC_REGNUM))] |
f19a9af7 | 2580 | "TARGET_64BIT && reload_completed" |
288e517f | 2581 | [(set (match_dup 0) |
f6ee577c AS |
2582 | (and:GPR (match_dup 1) |
2583 | (const_int 2147483647)))] | |
288e517f AK |
2584 | "") |
2585 | ||
9db1d521 | 2586 | ; |
f6ee577c | 2587 | ; zero_extend(hi|qi)si2 instruction pattern(s). |
9db1d521 HP |
2588 | ; |
2589 | ||
f6ee577c | 2590 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 2591 | [(set (match_operand:SI 0 "register_operand" "") |
f6ee577c | 2592 | (zero_extend:SI (match_operand:HQI 1 "register_operand" "")))] |
9db1d521 | 2593 | "" |
4023fb28 UW |
2594 | " |
2595 | { | |
2596 | operands[1] = gen_lowpart (SImode, operands[1]); | |
f6ee577c AS |
2597 | emit_insn (gen_andsi3 (operands[0], operands[1], |
2598 | GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1))); | |
4023fb28 UW |
2599 | DONE; |
2600 | } | |
2601 | ") | |
9db1d521 | 2602 | |
f6ee577c | 2603 | (define_insn "*zero_extend<mode>si2_64" |
9db1d521 | 2604 | [(set (match_operand:SI 0 "register_operand" "=d") |
f6ee577c | 2605 | (zero_extend:SI (match_operand:HQI 1 "memory_operand" "m")))] |
f4f41b4e | 2606 | "TARGET_ZARCH" |
f6ee577c | 2607 | "llg<hc>\t%0,%1" |
d3632d41 | 2608 | [(set_attr "op_type" "RXY")]) |
cc7ab9b7 UW |
2609 | |
2610 | (define_insn_and_split "*zero_extendhisi2_31" | |
2611 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 2612 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
ae156f85 | 2613 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 2614 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2615 | "#" |
2616 | "&& reload_completed" | |
2617 | [(set (match_dup 0) (const_int 0)) | |
2618 | (parallel | |
2619 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 2620 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 2621 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 2622 | |
cc7ab9b7 UW |
2623 | (define_insn_and_split "*zero_extendqisi2_31" |
2624 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
2625 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2626 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2627 | "#" |
2628 | "&& reload_completed" | |
2629 | [(set (match_dup 0) (const_int 0)) | |
2630 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 2631 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 2632 | |
9db1d521 HP |
2633 | ; |
2634 | ; zero_extendqihi2 instruction pattern(s). | |
2635 | ; | |
2636 | ||
9db1d521 HP |
2637 | (define_expand "zero_extendqihi2" |
2638 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 2639 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
9e8327e3 | 2640 | "TARGET_ZARCH" |
9db1d521 HP |
2641 | " |
2642 | { | |
4023fb28 UW |
2643 | operands[1] = gen_lowpart (HImode, operands[1]); |
2644 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
2645 | DONE; | |
2646 | } | |
2647 | ") | |
9db1d521 | 2648 | |
4023fb28 | 2649 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 2650 | [(set (match_operand:HI 0 "register_operand" "=d") |
cc7ab9b7 | 2651 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] |
9e8327e3 | 2652 | "TARGET_ZARCH" |
d40c829f | 2653 | "llgc\t%0,%1" |
d3632d41 | 2654 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2655 | |
cc7ab9b7 UW |
2656 | (define_insn_and_split "*zero_extendqihi2_31" |
2657 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
2658 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2659 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2660 | "#" |
2661 | "&& reload_completed" | |
2662 | [(set (match_dup 0) (const_int 0)) | |
2663 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 2664 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 UW |
2665 | |
2666 | ||
9db1d521 | 2667 | ; |
2f8f8434 | 2668 | ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s). |
9db1d521 HP |
2669 | ; |
2670 | ||
2f8f8434 AS |
2671 | (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2" |
2672 | [(set (match_operand:GPR 0 "register_operand" "") | |
2673 | (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))] | |
2674 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2675 | { |
2676 | rtx label1 = gen_label_rtx (); | |
2677 | rtx label2 = gen_label_rtx (); | |
2f8f8434 AS |
2678 | rtx temp = gen_reg_rtx (<FPR:MODE>mode); |
2679 | REAL_VALUE_TYPE cmp, sub; | |
2680 | ||
2681 | operands[1] = force_reg (<FPR:MODE>mode, operands[1]); | |
2682 | real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1); | |
2683 | real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode)); | |
2684 | ||
2685 | emit_insn (gen_cmp<FPR:mode> (operands[1], | |
2686 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode))); | |
9db1d521 | 2687 | emit_jump_insn (gen_blt (label1)); |
2f8f8434 AS |
2688 | emit_insn (gen_sub<FPR:mode>3 (temp, operands[1], |
2689 | CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode))); | |
2690 | emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp, | |
2691 | GEN_INT(7))); | |
f314b9b1 | 2692 | emit_jump (label2); |
9db1d521 HP |
2693 | |
2694 | emit_label (label1); | |
2f8f8434 AS |
2695 | emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], |
2696 | operands[1], GEN_INT(5))); | |
9db1d521 HP |
2697 | emit_label (label2); |
2698 | DONE; | |
10bbf137 | 2699 | }) |
9db1d521 | 2700 | |
2f8f8434 | 2701 | (define_expand "fix_trunc<FPR:mode>di2" |
9db1d521 | 2702 | [(set (match_operand:DI 0 "register_operand" "") |
2f8f8434 | 2703 | (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))] |
9db1d521 | 2704 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
9db1d521 | 2705 | { |
2f8f8434 AS |
2706 | operands[1] = force_reg (<FPR:MODE>mode, operands[1]); |
2707 | emit_insn (gen_fix_trunc<FPR:mode>di2_ieee (operands[0], operands[1], | |
2708 | GEN_INT(5))); | |
9db1d521 | 2709 | DONE; |
10bbf137 | 2710 | }) |
9db1d521 | 2711 | |
2f8f8434 AS |
2712 | (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee" |
2713 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
2714 | (fix:GPR (match_operand:FPR 1 "register_operand" "f"))) | |
2715 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
ae156f85 | 2716 | (clobber (reg:CC CC_REGNUM))] |
2f8f8434 AS |
2717 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
2718 | "c<GPR:gf><FPR:de>br\t%0,%h2,%1" | |
9db1d521 | 2719 | [(set_attr "op_type" "RRE") |
077dab3b | 2720 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
2721 | |
2722 | ; | |
2f8f8434 | 2723 | ; fix_truncdfsi2 instruction pattern(s). |
9db1d521 HP |
2724 | ; |
2725 | ||
9db1d521 HP |
2726 | (define_expand "fix_truncdfsi2" |
2727 | [(set (match_operand:SI 0 "register_operand" "") | |
2728 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
2729 | "TARGET_HARD_FLOAT" | |
9db1d521 | 2730 | { |
c7453384 | 2731 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
2732 | { |
2733 | /* This is the algorithm from POP chapter A.5.7.2. */ | |
2734 | ||
c19ec8f9 | 2735 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
4023fb28 UW |
2736 | rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000); |
2737 | rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000); | |
9db1d521 HP |
2738 | |
2739 | operands[1] = force_reg (DFmode, operands[1]); | |
c7453384 | 2740 | emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1], |
9db1d521 | 2741 | two31r, two32, temp)); |
c7453384 EC |
2742 | } |
2743 | else | |
9db1d521 HP |
2744 | { |
2745 | operands[1] = force_reg (DFmode, operands[1]); | |
2746 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2747 | } | |
2748 | ||
2749 | DONE; | |
10bbf137 | 2750 | }) |
9db1d521 | 2751 | |
9db1d521 HP |
2752 | (define_insn "fix_truncdfsi2_ibm" |
2753 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2754 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f"))) | |
4023fb28 UW |
2755 | (use (match_operand:DI 2 "immediate_operand" "m")) |
2756 | (use (match_operand:DI 3 "immediate_operand" "m")) | |
9db1d521 | 2757 | (use (match_operand:BLK 4 "memory_operand" "m")) |
ae156f85 | 2758 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2759 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
9db1d521 | 2760 | { |
d40c829f UW |
2761 | output_asm_insn ("sd\t%1,%2", operands); |
2762 | output_asm_insn ("aw\t%1,%3", operands); | |
2763 | output_asm_insn ("std\t%1,%4", operands); | |
2764 | output_asm_insn ("xi\t%N4,128", operands); | |
2765 | return "l\t%0,%N4"; | |
10bbf137 | 2766 | } |
b628bd8e | 2767 | [(set_attr "length" "20")]) |
9db1d521 HP |
2768 | |
2769 | ; | |
2f8f8434 | 2770 | ; fix_truncsfsi2 instruction pattern(s). |
9db1d521 HP |
2771 | ; |
2772 | ||
9db1d521 HP |
2773 | (define_expand "fix_truncsfsi2" |
2774 | [(set (match_operand:SI 0 "register_operand" "") | |
2775 | (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
2776 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
2777 | { |
2778 | if (TARGET_IBM_FLOAT) | |
2779 | { | |
2780 | /* Convert to DFmode and then use the POP algorithm. */ | |
2781 | rtx temp = gen_reg_rtx (DFmode); | |
2782 | emit_insn (gen_extendsfdf2 (temp, operands[1])); | |
2783 | emit_insn (gen_fix_truncdfsi2 (operands[0], temp)); | |
2784 | } | |
2785 | else | |
2786 | { | |
2787 | operands[1] = force_reg (SFmode, operands[1]); | |
2788 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2789 | } | |
2790 | ||
2791 | DONE; | |
10bbf137 | 2792 | }) |
9db1d521 | 2793 | |
9db1d521 | 2794 | ; |
f5905b37 | 2795 | ; floatdi(df|sf)2 instruction pattern(s). |
9db1d521 HP |
2796 | ; |
2797 | ||
f5905b37 AS |
2798 | (define_insn "floatdi<mode>2" |
2799 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
2800 | (float:FPR (match_operand:DI 1 "register_operand" "d")))] | |
9db1d521 | 2801 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 2802 | "c<de>gbr\t%0,%1" |
9db1d521 | 2803 | [(set_attr "op_type" "RRE") |
077dab3b | 2804 | (set_attr "type" "itof" )]) |
9db1d521 HP |
2805 | |
2806 | ; | |
2807 | ; floatsidf2 instruction pattern(s). | |
2808 | ; | |
2809 | ||
2810 | (define_expand "floatsidf2" | |
a036c6f7 UW |
2811 | [(set (match_operand:DF 0 "register_operand" "") |
2812 | (float:DF (match_operand:SI 1 "register_operand" "")))] | |
9db1d521 | 2813 | "TARGET_HARD_FLOAT" |
9db1d521 | 2814 | { |
c7453384 | 2815 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
2816 | { |
2817 | /* This is the algorithm from POP chapter A.5.7.1. */ | |
2818 | ||
c19ec8f9 | 2819 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
c7453384 | 2820 | rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000); |
9db1d521 HP |
2821 | |
2822 | emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp)); | |
2823 | DONE; | |
2824 | } | |
10bbf137 | 2825 | }) |
9db1d521 HP |
2826 | |
2827 | (define_insn "floatsidf2_ieee" | |
2828 | [(set (match_operand:DF 0 "register_operand" "=f") | |
a036c6f7 | 2829 | (float:DF (match_operand:SI 1 "register_operand" "d")))] |
9db1d521 | 2830 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 2831 | "cdfbr\t%0,%1" |
9db1d521 | 2832 | [(set_attr "op_type" "RRE") |
077dab3b | 2833 | (set_attr "type" "itof" )]) |
9db1d521 HP |
2834 | |
2835 | (define_insn "floatsidf2_ibm" | |
2836 | [(set (match_operand:DF 0 "register_operand" "=f") | |
2837 | (float:DF (match_operand:SI 1 "register_operand" "d"))) | |
4023fb28 | 2838 | (use (match_operand:DI 2 "immediate_operand" "m")) |
9db1d521 | 2839 | (use (match_operand:BLK 3 "memory_operand" "m")) |
ae156f85 | 2840 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2841 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
9db1d521 | 2842 | { |
d40c829f UW |
2843 | output_asm_insn ("st\t%1,%N3", operands); |
2844 | output_asm_insn ("xi\t%N3,128", operands); | |
2845 | output_asm_insn ("mvc\t%O3(4,%R3),%2", operands); | |
2846 | output_asm_insn ("ld\t%0,%3", operands); | |
2847 | return "sd\t%0,%2"; | |
10bbf137 | 2848 | } |
b628bd8e | 2849 | [(set_attr "length" "20")]) |
9db1d521 HP |
2850 | |
2851 | ; | |
2852 | ; floatsisf2 instruction pattern(s). | |
2853 | ; | |
2854 | ||
2855 | (define_expand "floatsisf2" | |
a036c6f7 UW |
2856 | [(set (match_operand:SF 0 "register_operand" "") |
2857 | (float:SF (match_operand:SI 1 "register_operand" "")))] | |
9db1d521 | 2858 | "TARGET_HARD_FLOAT" |
9db1d521 HP |
2859 | { |
2860 | if (TARGET_IBM_FLOAT) | |
2861 | { | |
2862 | /* Use the POP algorithm to convert to DFmode and then truncate. */ | |
2863 | rtx temp = gen_reg_rtx (DFmode); | |
2864 | emit_insn (gen_floatsidf2 (temp, operands[1])); | |
2865 | emit_insn (gen_truncdfsf2 (operands[0], temp)); | |
2866 | DONE; | |
2867 | } | |
10bbf137 | 2868 | }) |
9db1d521 HP |
2869 | |
2870 | (define_insn "floatsisf2_ieee" | |
2871 | [(set (match_operand:SF 0 "register_operand" "=f") | |
a036c6f7 | 2872 | (float:SF (match_operand:SI 1 "register_operand" "d")))] |
9db1d521 | 2873 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 2874 | "cefbr\t%0,%1" |
9db1d521 | 2875 | [(set_attr "op_type" "RRE") |
077dab3b | 2876 | (set_attr "type" "itof" )]) |
9db1d521 HP |
2877 | |
2878 | ; | |
2879 | ; truncdfsf2 instruction pattern(s). | |
2880 | ; | |
2881 | ||
2882 | (define_expand "truncdfsf2" | |
2883 | [(set (match_operand:SF 0 "register_operand" "") | |
a036c6f7 | 2884 | (float_truncate:SF (match_operand:DF 1 "register_operand" "")))] |
9db1d521 | 2885 | "TARGET_HARD_FLOAT" |
4023fb28 | 2886 | "") |
9db1d521 HP |
2887 | |
2888 | (define_insn "truncdfsf2_ieee" | |
2889 | [(set (match_operand:SF 0 "register_operand" "=f") | |
a036c6f7 | 2890 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] |
9db1d521 | 2891 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 2892 | "ledbr\t%0,%1" |
ce50cae8 | 2893 | [(set_attr "op_type" "RRE")]) |
9db1d521 HP |
2894 | |
2895 | (define_insn "truncdfsf2_ibm" | |
2896 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
a036c6f7 | 2897 | (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))] |
9db1d521 HP |
2898 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
2899 | "@ | |
a036c6f7 | 2900 | ler\t%0,%1 |
d40c829f | 2901 | le\t%0,%1" |
4023fb28 | 2902 | [(set_attr "op_type" "RR,RX") |
cfdb984b | 2903 | (set_attr "type" "floadsf")]) |
9db1d521 HP |
2904 | |
2905 | ; | |
2906 | ; extendsfdf2 instruction pattern(s). | |
2907 | ; | |
2908 | ||
2909 | (define_expand "extendsfdf2" | |
2910 | [(set (match_operand:DF 0 "register_operand" "") | |
2911 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] | |
2912 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
2913 | { |
2914 | if (TARGET_IBM_FLOAT) | |
2915 | { | |
2916 | emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1])); | |
2917 | DONE; | |
2918 | } | |
10bbf137 | 2919 | }) |
9db1d521 HP |
2920 | |
2921 | (define_insn "extendsfdf2_ieee" | |
2922 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 2923 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))] |
9db1d521 HP |
2924 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
2925 | "@ | |
d40c829f UW |
2926 | ldebr\t%0,%1 |
2927 | ldeb\t%0,%1" | |
077dab3b | 2928 | [(set_attr "op_type" "RRE,RXE") |
cfdb984b | 2929 | (set_attr "type" "floadsf")]) |
9db1d521 HP |
2930 | |
2931 | (define_insn "extendsfdf2_ibm" | |
2932 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 2933 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R"))) |
ae156f85 | 2934 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
2935 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
2936 | "@ | |
d40c829f UW |
2937 | sdr\t%0,%0\;ler\t%0,%1 |
2938 | sdr\t%0,%0\;le\t%0,%1" | |
b628bd8e | 2939 | [(set_attr "length" "4,6") |
cfdb984b | 2940 | (set_attr "type" "floadsf")]) |
9db1d521 HP |
2941 | |
2942 | ||
2943 | ;; | |
fae778eb | 2944 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 2945 | ;; |
fae778eb | 2946 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
2947 | ; because of unpredictable Bits in Register for Halfword and Byte |
2948 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
2949 | ||
07893d4f UW |
2950 | ;; |
2951 | ;;- Add instructions. | |
2952 | ;; | |
2953 | ||
1c7b1b7e UW |
2954 | ; |
2955 | ; addti3 instruction pattern(s). | |
2956 | ; | |
2957 | ||
2958 | (define_insn_and_split "addti3" | |
2959 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
2960 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") | |
2961 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 2962 | (clobber (reg:CC CC_REGNUM))] |
1c7b1b7e UW |
2963 | "TARGET_64BIT" |
2964 | "#" | |
2965 | "&& reload_completed" | |
2966 | [(parallel | |
ae156f85 | 2967 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
2968 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
2969 | (match_dup 7))) | |
2970 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
2971 | (parallel | |
2972 | [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
2973 | (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)))) |
2974 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
2975 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
2976 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
2977 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
2978 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
2979 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 2980 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 2981 | |
07893d4f UW |
2982 | ; |
2983 | ; adddi3 instruction pattern(s). | |
2984 | ; | |
2985 | ||
07893d4f UW |
2986 | (define_insn "*adddi3_sign" |
2987 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2988 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
2989 | (match_operand:DI 1 "register_operand" "0,0"))) | |
ae156f85 | 2990 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
2991 | "TARGET_64BIT" |
2992 | "@ | |
d40c829f UW |
2993 | agfr\t%0,%2 |
2994 | agf\t%0,%2" | |
d3632d41 | 2995 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
2996 | |
2997 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 2998 | [(set (reg CC_REGNUM) |
07893d4f UW |
2999 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3000 | (match_operand:DI 1 "register_operand" "0,0")) | |
3001 | (const_int 0))) | |
3002 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3003 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
3004 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3005 | "@ | |
d40c829f UW |
3006 | algfr\t%0,%2 |
3007 | algf\t%0,%2" | |
d3632d41 | 3008 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3009 | |
3010 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 3011 | [(set (reg CC_REGNUM) |
07893d4f UW |
3012 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3013 | (match_operand:DI 1 "register_operand" "0,0")) | |
3014 | (const_int 0))) | |
3015 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3016 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3017 | "@ | |
d40c829f UW |
3018 | algfr\t%0,%2 |
3019 | algf\t%0,%2" | |
d3632d41 | 3020 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3021 | |
3022 | (define_insn "*adddi3_zero" | |
3023 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3024 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3025 | (match_operand:DI 1 "register_operand" "0,0"))) | |
ae156f85 | 3026 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
3027 | "TARGET_64BIT" |
3028 | "@ | |
d40c829f UW |
3029 | algfr\t%0,%2 |
3030 | algf\t%0,%2" | |
d3632d41 | 3031 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3032 | |
0a3bdf9d | 3033 | (define_insn "*adddi3_imm_cc" |
ae156f85 | 3034 | [(set (reg CC_REGNUM) |
0a3bdf9d UW |
3035 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0") |
3036 | (match_operand:DI 2 "const_int_operand" "K")) | |
3037 | (const_int 0))) | |
3038 | (set (match_operand:DI 0 "register_operand" "=d") | |
3039 | (plus:DI (match_dup 1) (match_dup 2)))] | |
c7453384 EC |
3040 | "TARGET_64BIT |
3041 | && s390_match_ccmode (insn, CCAmode) | |
f19a9af7 | 3042 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")" |
d40c829f | 3043 | "aghi\t%0,%h2" |
077dab3b | 3044 | [(set_attr "op_type" "RI")]) |
0a3bdf9d | 3045 | |
b2ba71ca | 3046 | (define_insn "*adddi3_carry1_cc" |
ae156f85 | 3047 | [(set (reg CC_REGNUM) |
b2ba71ca UW |
3048 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
3049 | (match_operand:DI 2 "general_operand" "d,m")) | |
3050 | (match_dup 1))) | |
3051 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3052 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3053 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3054 | "@ | |
3055 | algr\t%0,%2 | |
3056 | alg\t%0,%2" | |
3057 | [(set_attr "op_type" "RRE,RXY")]) | |
3058 | ||
3059 | (define_insn "*adddi3_carry1_cconly" | |
ae156f85 | 3060 | [(set (reg CC_REGNUM) |
b2ba71ca UW |
3061 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
3062 | (match_operand:DI 2 "general_operand" "d,m")) | |
3063 | (match_dup 1))) | |
3064 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3065 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3066 | "@ | |
3067 | algr\t%0,%2 | |
3068 | alg\t%0,%2" | |
3069 | [(set_attr "op_type" "RRE,RXY")]) | |
3070 | ||
3071 | (define_insn "*adddi3_carry2_cc" | |
ae156f85 | 3072 | [(set (reg CC_REGNUM) |
b2ba71ca UW |
3073 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
3074 | (match_operand:DI 2 "general_operand" "d,m")) | |
3075 | (match_dup 2))) | |
3076 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3077 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3078 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3079 | "@ | |
3080 | algr\t%0,%2 | |
3081 | alg\t%0,%2" | |
3082 | [(set_attr "op_type" "RRE,RXY")]) | |
3083 | ||
3084 | (define_insn "*adddi3_carry2_cconly" | |
ae156f85 | 3085 | [(set (reg CC_REGNUM) |
b2ba71ca UW |
3086 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
3087 | (match_operand:DI 2 "general_operand" "d,m")) | |
3088 | (match_dup 2))) | |
3089 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3090 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3091 | "@ | |
3092 | algr\t%0,%2 | |
3093 | alg\t%0,%2" | |
3094 | [(set_attr "op_type" "RRE,RXY")]) | |
3095 | ||
07893d4f | 3096 | (define_insn "*adddi3_cc" |
ae156f85 | 3097 | [(set (reg CC_REGNUM) |
96fd3851 | 3098 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3099 | (match_operand:DI 2 "general_operand" "d,m")) |
3100 | (const_int 0))) | |
3101 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3102 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3103 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3104 | "@ | |
d40c829f UW |
3105 | algr\t%0,%2 |
3106 | alg\t%0,%2" | |
d3632d41 | 3107 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3108 | |
07893d4f | 3109 | (define_insn "*adddi3_cconly" |
ae156f85 | 3110 | [(set (reg CC_REGNUM) |
96fd3851 | 3111 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3112 | (match_operand:DI 2 "general_operand" "d,m")) |
3113 | (const_int 0))) | |
3114 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3115 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3116 | "@ | |
d40c829f UW |
3117 | algr\t%0,%2 |
3118 | alg\t%0,%2" | |
d3632d41 | 3119 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3120 | |
07893d4f | 3121 | (define_insn "*adddi3_cconly2" |
ae156f85 | 3122 | [(set (reg CC_REGNUM) |
96fd3851 | 3123 | (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3124 | (neg:SI (match_operand:DI 2 "general_operand" "d,m")))) |
3125 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3126 | "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT" | |
9db1d521 | 3127 | "@ |
d40c829f UW |
3128 | algr\t%0,%2 |
3129 | alg\t%0,%2" | |
d3632d41 | 3130 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3131 | |
07893d4f | 3132 | (define_insn "*adddi3_64" |
9db1d521 | 3133 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
96fd3851 | 3134 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
9db1d521 | 3135 | (match_operand:DI 2 "general_operand" "d,K,m") ) ) |
ae156f85 | 3136 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3137 | "TARGET_64BIT" |
3138 | "@ | |
d40c829f UW |
3139 | agr\t%0,%2 |
3140 | aghi\t%0,%h2 | |
3141 | ag\t%0,%2" | |
d3632d41 | 3142 | [(set_attr "op_type" "RRE,RI,RXY")]) |
9db1d521 | 3143 | |
e69166de UW |
3144 | (define_insn_and_split "*adddi3_31z" |
3145 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3146 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") | |
3147 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 3148 | (clobber (reg:CC CC_REGNUM))] |
e69166de UW |
3149 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
3150 | "#" | |
3151 | "&& reload_completed" | |
3152 | [(parallel | |
ae156f85 | 3153 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
3154 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
3155 | (match_dup 7))) | |
3156 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3157 | (parallel | |
3158 | [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
3159 | (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)))) |
3160 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
3161 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3162 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3163 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3164 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3165 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 3166 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 3167 | |
07893d4f UW |
3168 | (define_insn_and_split "*adddi3_31" |
3169 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
96fd3851 | 3170 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 3171 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 3172 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 3173 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
3174 | "#" |
3175 | "&& reload_completed" | |
3176 | [(parallel | |
3177 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 3178 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 3179 | (parallel |
ae156f85 | 3180 | [(set (reg:CCL1 CC_REGNUM) |
07893d4f UW |
3181 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
3182 | (match_dup 7))) | |
3183 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3184 | (set (pc) | |
ae156f85 | 3185 | (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) |
07893d4f UW |
3186 | (pc) |
3187 | (label_ref (match_dup 9)))) | |
3188 | (parallel | |
3189 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
ae156f85 | 3190 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 3191 | (match_dup 9)] |
97c6f7ad UW |
3192 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3193 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3194 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3195 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3196 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3197 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 3198 | operands[9] = gen_label_rtx ();") |
9db1d521 HP |
3199 | |
3200 | (define_expand "adddi3" | |
07893d4f UW |
3201 | [(parallel |
3202 | [(set (match_operand:DI 0 "register_operand" "") | |
96fd3851 | 3203 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
07893d4f | 3204 | (match_operand:DI 2 "general_operand" ""))) |
ae156f85 | 3205 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 3206 | "" |
07893d4f | 3207 | "") |
9db1d521 | 3208 | |
9db1d521 HP |
3209 | ; |
3210 | ; addsi3 instruction pattern(s). | |
3211 | ; | |
9db1d521 | 3212 | |
0a3bdf9d | 3213 | (define_insn "*addsi3_imm_cc" |
ae156f85 | 3214 | [(set (reg CC_REGNUM) |
0a3bdf9d UW |
3215 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
3216 | (match_operand:SI 2 "const_int_operand" "K")) | |
3217 | (const_int 0))) | |
3218 | (set (match_operand:SI 0 "register_operand" "=d") | |
3219 | (plus:SI (match_dup 1) (match_dup 2)))] | |
3220 | "s390_match_ccmode (insn, CCAmode) | |
f19a9af7 | 3221 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")" |
d40c829f | 3222 | "ahi\t%0,%h2" |
077dab3b | 3223 | [(set_attr "op_type" "RI")]) |
0a3bdf9d | 3224 | |
07893d4f | 3225 | (define_insn "*addsi3_carry1_cc" |
ae156f85 | 3226 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3227 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3228 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3229 | (match_dup 1))) |
d3632d41 | 3230 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3231 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3232 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3233 | "@ |
d40c829f UW |
3234 | alr\t%0,%2 |
3235 | al\t%0,%2 | |
3236 | aly\t%0,%2" | |
d3632d41 | 3237 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3238 | |
3239 | (define_insn "*addsi3_carry1_cconly" | |
ae156f85 | 3240 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3241 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3242 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3243 | (match_dup 1))) |
d3632d41 | 3244 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3245 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3246 | "@ |
d40c829f UW |
3247 | alr\t%0,%2 |
3248 | al\t%0,%2 | |
3249 | aly\t%0,%2" | |
d3632d41 | 3250 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3251 | |
3252 | (define_insn "*addsi3_carry2_cc" | |
ae156f85 | 3253 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3254 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3255 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3256 | (match_dup 2))) |
d3632d41 | 3257 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3258 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3259 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3260 | "@ |
d40c829f UW |
3261 | alr\t%0,%2 |
3262 | al\t%0,%2 | |
3263 | aly\t%0,%2" | |
d3632d41 | 3264 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3265 | |
3266 | (define_insn "*addsi3_carry2_cconly" | |
ae156f85 | 3267 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3268 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3269 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3270 | (match_dup 2))) |
d3632d41 | 3271 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3272 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3273 | "@ |
d40c829f UW |
3274 | alr\t%0,%2 |
3275 | al\t%0,%2 | |
3276 | aly\t%0,%2" | |
d3632d41 | 3277 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f | 3278 | |
9db1d521 | 3279 | (define_insn "*addsi3_cc" |
ae156f85 | 3280 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3281 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3282 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3283 | (const_int 0))) |
d3632d41 | 3284 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 | 3285 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3286 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3287 | "@ |
d40c829f UW |
3288 | alr\t%0,%2 |
3289 | al\t%0,%2 | |
3290 | aly\t%0,%2" | |
d3632d41 | 3291 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
3292 | |
3293 | (define_insn "*addsi3_cconly" | |
ae156f85 | 3294 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3295 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3296 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3297 | (const_int 0))) |
d3632d41 | 3298 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3299 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3300 | "@ |
d40c829f UW |
3301 | alr\t%0,%2 |
3302 | al\t%0,%2 | |
3303 | aly\t%0,%2" | |
d3632d41 | 3304 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
3305 | |
3306 | (define_insn "*addsi3_cconly2" | |
ae156f85 | 3307 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3308 | (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3309 | (neg:SI (match_operand:SI 2 "general_operand" "d,R,T")))) | |
3310 | (clobber (match_scratch:SI 0 "=d,d,d"))] | |
b2ba71ca | 3311 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3312 | "@ |
d40c829f UW |
3313 | alr\t%0,%2 |
3314 | al\t%0,%2 | |
3315 | aly\t%0,%2" | |
d3632d41 | 3316 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 3317 | |
07893d4f | 3318 | (define_insn "*addsi3_sign" |
d3632d41 | 3319 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
f0ad121f UW |
3320 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) |
3321 | (match_operand:SI 1 "register_operand" "0,0"))) | |
ae156f85 | 3322 | (clobber (reg:CC CC_REGNUM))] |
07893d4f | 3323 | "" |
d3632d41 | 3324 | "@ |
d40c829f UW |
3325 | ah\t%0,%2 |
3326 | ahy\t%0,%2" | |
d3632d41 | 3327 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f | 3328 | |
9db1d521 | 3329 | (define_insn "addsi3" |
d3632d41 UW |
3330 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
3331 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
3332 | (match_operand:SI 2 "general_operand" "d,K,R,T"))) | |
ae156f85 | 3333 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3334 | "" |
3335 | "@ | |
d40c829f UW |
3336 | ar\t%0,%2 |
3337 | ahi\t%0,%h2 | |
3338 | a\t%0,%2 | |
3339 | ay\t%0,%2" | |
d3632d41 | 3340 | [(set_attr "op_type" "RR,RI,RX,RXY")]) |
9db1d521 | 3341 | |
9db1d521 | 3342 | ; |
f5905b37 | 3343 | ; add(df|sf)3 instruction pattern(s). |
9db1d521 HP |
3344 | ; |
3345 | ||
f5905b37 | 3346 | (define_expand "add<mode>3" |
9db1d521 | 3347 | [(parallel |
f5905b37 AS |
3348 | [(set (match_operand:FPR 0 "register_operand" "=f,f") |
3349 | (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
3350 | (match_operand:FPR 2 "general_operand" "f,R"))) | |
ae156f85 | 3351 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
3352 | "TARGET_HARD_FLOAT" |
3353 | "") | |
3354 | ||
f5905b37 AS |
3355 | (define_insn "*add<mode>3" |
3356 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
3357 | (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
3358 | (match_operand:FPR 2 "general_operand" "f,R"))) | |
ae156f85 | 3359 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3360 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3361 | "@ | |
f5905b37 AS |
3362 | a<de>br\t%0,%2 |
3363 | a<de>b\t%0,%2" | |
ce50cae8 | 3364 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 3365 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 3366 | |
f5905b37 | 3367 | (define_insn "*add<mode>3_cc" |
ae156f85 | 3368 | [(set (reg CC_REGNUM) |
f5905b37 AS |
3369 | (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") |
3370 | (match_operand:FPR 2 "general_operand" "f,R")) | |
3371 | (match_operand:FPR 3 "const0_operand" ""))) | |
3372 | (set (match_operand:FPR 0 "register_operand" "=f,f") | |
3373 | (plus:FPR (match_dup 1) (match_dup 2)))] | |
3ef093a8 AK |
3374 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3375 | "@ | |
f5905b37 AS |
3376 | a<de>br\t%0,%2 |
3377 | a<de>b\t%0,%2" | |
3ef093a8 | 3378 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 3379 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 3380 | |
f5905b37 | 3381 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 3382 | [(set (reg CC_REGNUM) |
f5905b37 AS |
3383 | (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") |
3384 | (match_operand:FPR 2 "general_operand" "f,R")) | |
3385 | (match_operand:FPR 3 "const0_operand" ""))) | |
3386 | (clobber (match_scratch:FPR 0 "=f,f"))] | |
3ef093a8 AK |
3387 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3388 | "@ | |
f5905b37 AS |
3389 | a<de>br\t%0,%2 |
3390 | a<de>b\t%0,%2" | |
3ef093a8 | 3391 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 3392 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 3393 | |
f5905b37 AS |
3394 | (define_insn "*add<mode>3_ibm" |
3395 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
3396 | (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
3397 | (match_operand:FPR 2 "general_operand" "f,R"))) | |
ae156f85 | 3398 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3399 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
3400 | "@ | |
f5905b37 AS |
3401 | a<de>r\t%0,%2 |
3402 | a<de>\t%0,%2" | |
9db1d521 | 3403 | [(set_attr "op_type" "RR,RX") |
f5905b37 | 3404 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 HP |
3405 | |
3406 | ||
3407 | ;; | |
3408 | ;;- Subtract instructions. | |
3409 | ;; | |
3410 | ||
1c7b1b7e UW |
3411 | ; |
3412 | ; subti3 instruction pattern(s). | |
3413 | ; | |
3414 | ||
3415 | (define_insn_and_split "subti3" | |
3416 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
3417 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
3418 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 3419 | (clobber (reg:CC CC_REGNUM))] |
1c7b1b7e UW |
3420 | "TARGET_64BIT" |
3421 | "#" | |
3422 | "&& reload_completed" | |
3423 | [(parallel | |
ae156f85 | 3424 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
3425 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
3426 | (match_dup 7))) | |
3427 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
3428 | (parallel | |
3429 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
3430 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
3431 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
3432 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
3433 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
3434 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
3435 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
3436 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 3437 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 3438 | |
9db1d521 HP |
3439 | ; |
3440 | ; subdi3 instruction pattern(s). | |
3441 | ; | |
3442 | ||
07893d4f UW |
3443 | (define_insn "*subdi3_sign" |
3444 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3445 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3446 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
ae156f85 | 3447 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
3448 | "TARGET_64BIT" |
3449 | "@ | |
d40c829f UW |
3450 | sgfr\t%0,%2 |
3451 | sgf\t%0,%2" | |
d3632d41 | 3452 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3453 | |
3454 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 3455 | [(set (reg CC_REGNUM) |
07893d4f UW |
3456 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3457 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3458 | (const_int 0))) | |
3459 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3460 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
3461 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3462 | "@ | |
d40c829f UW |
3463 | slgfr\t%0,%2 |
3464 | slgf\t%0,%2" | |
d3632d41 | 3465 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3466 | |
3467 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 3468 | [(set (reg CC_REGNUM) |
07893d4f UW |
3469 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3470 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3471 | (const_int 0))) | |
3472 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3473 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3474 | "@ | |
d40c829f UW |
3475 | slgfr\t%0,%2 |
3476 | slgf\t%0,%2" | |
d3632d41 | 3477 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3478 | |
3479 | (define_insn "*subdi3_zero" | |
3480 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3481 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3482 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
ae156f85 | 3483 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
3484 | "TARGET_64BIT" |
3485 | "@ | |
d40c829f UW |
3486 | slgfr\t%0,%2 |
3487 | slgf\t%0,%2" | |
d3632d41 | 3488 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3489 | |
b2ba71ca | 3490 | (define_insn "*subdi3_borrow_cc" |
ae156f85 | 3491 | [(set (reg CC_REGNUM) |
b2ba71ca UW |
3492 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3493 | (match_operand:DI 2 "general_operand" "d,m")) | |
3494 | (match_dup 1))) | |
3495 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3496 | (minus:DI (match_dup 1) (match_dup 2)))] | |
3497 | "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" | |
3498 | "@ | |
3499 | slgr\t%0,%2 | |
3500 | slg\t%0,%2" | |
3501 | [(set_attr "op_type" "RRE,RXY")]) | |
3502 | ||
3503 | (define_insn "*subdi3_borrow_cconly" | |
ae156f85 | 3504 | [(set (reg CC_REGNUM) |
b2ba71ca UW |
3505 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3506 | (match_operand:DI 2 "general_operand" "d,m")) | |
3507 | (match_dup 1))) | |
3508 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3509 | "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" | |
3510 | "@ | |
3511 | slgr\t%0,%2 | |
3512 | slg\t%0,%2" | |
3513 | [(set_attr "op_type" "RRE,RXY")]) | |
3514 | ||
07893d4f | 3515 | (define_insn "*subdi3_cc" |
ae156f85 | 3516 | [(set (reg CC_REGNUM) |
07893d4f UW |
3517 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3518 | (match_operand:DI 2 "general_operand" "d,m")) | |
3519 | (const_int 0))) | |
3520 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3521 | (minus:DI (match_dup 1) (match_dup 2)))] | |
b2ba71ca | 3522 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
07893d4f | 3523 | "@ |
d40c829f UW |
3524 | slgr\t%0,%2 |
3525 | slg\t%0,%2" | |
d3632d41 | 3526 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3527 | |
5d880bd2 | 3528 | (define_insn "*subdi3_cc2" |
ae156f85 | 3529 | [(set (reg CC_REGNUM) |
5d880bd2 UW |
3530 | (compare (match_operand:DI 1 "register_operand" "0,0") |
3531 | (match_operand:DI 2 "general_operand" "d,m"))) | |
3532 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3533 | (minus:DI (match_dup 1) (match_dup 2)))] | |
3534 | "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT" | |
3535 | "@ | |
3536 | slgr\t%0,%2 | |
3537 | slg\t%0,%2" | |
3538 | [(set_attr "op_type" "RRE,RXY")]) | |
3539 | ||
07893d4f | 3540 | (define_insn "*subdi3_cconly" |
ae156f85 | 3541 | [(set (reg CC_REGNUM) |
07893d4f UW |
3542 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3543 | (match_operand:DI 2 "general_operand" "d,m")) | |
3544 | (const_int 0))) | |
3545 | (clobber (match_scratch:DI 0 "=d,d"))] | |
b2ba71ca | 3546 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
07893d4f | 3547 | "@ |
d40c829f UW |
3548 | slgr\t%0,%2 |
3549 | slg\t%0,%2" | |
d3632d41 | 3550 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3551 | |
5d880bd2 | 3552 | (define_insn "*subdi3_cconly2" |
ae156f85 | 3553 | [(set (reg CC_REGNUM) |
5d880bd2 UW |
3554 | (compare (match_operand:DI 1 "register_operand" "0,0") |
3555 | (match_operand:DI 2 "general_operand" "d,m"))) | |
3556 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3557 | "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT" | |
3558 | "@ | |
3559 | slgr\t%0,%2 | |
3560 | slg\t%0,%2" | |
3561 | [(set_attr "op_type" "RRE,RXY")]) | |
3562 | ||
9db1d521 HP |
3563 | (define_insn "*subdi3_64" |
3564 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3565 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3566 | (match_operand:DI 2 "general_operand" "d,m") ) ) | |
ae156f85 | 3567 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3568 | "TARGET_64BIT" |
3569 | "@ | |
d40c829f UW |
3570 | sgr\t%0,%2 |
3571 | sg\t%0,%2" | |
077dab3b | 3572 | [(set_attr "op_type" "RRE,RRE")]) |
9db1d521 | 3573 | |
e69166de UW |
3574 | (define_insn_and_split "*subdi3_31z" |
3575 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3576 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
3577 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 3578 | (clobber (reg:CC CC_REGNUM))] |
e69166de UW |
3579 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
3580 | "#" | |
3581 | "&& reload_completed" | |
3582 | [(parallel | |
ae156f85 | 3583 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
3584 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
3585 | (match_dup 7))) | |
3586 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
3587 | (parallel | |
3588 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
3589 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
3590 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
3591 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3592 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3593 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3594 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3595 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 3596 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 3597 | |
07893d4f UW |
3598 | (define_insn_and_split "*subdi3_31" |
3599 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3600 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 3601 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 3602 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 3603 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
3604 | "#" |
3605 | "&& reload_completed" | |
3606 | [(parallel | |
3607 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 3608 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 3609 | (parallel |
ae156f85 | 3610 | [(set (reg:CCL2 CC_REGNUM) |
07893d4f UW |
3611 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
3612 | (match_dup 7))) | |
3613 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
3614 | (set (pc) | |
ae156f85 | 3615 | (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) |
07893d4f UW |
3616 | (pc) |
3617 | (label_ref (match_dup 9)))) | |
3618 | (parallel | |
3619 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
ae156f85 | 3620 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 3621 | (match_dup 9)] |
97c6f7ad UW |
3622 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3623 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3624 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3625 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3626 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3627 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 3628 | operands[9] = gen_label_rtx ();") |
07893d4f UW |
3629 | |
3630 | (define_expand "subdi3" | |
3631 | [(parallel | |
3632 | [(set (match_operand:DI 0 "register_operand" "") | |
3633 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
3634 | (match_operand:DI 2 "general_operand" ""))) | |
ae156f85 | 3635 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 3636 | "" |
07893d4f | 3637 | "") |
9db1d521 HP |
3638 | |
3639 | ; | |
3640 | ; subsi3 instruction pattern(s). | |
3641 | ; | |
3642 | ||
07893d4f | 3643 | (define_insn "*subsi3_borrow_cc" |
ae156f85 | 3644 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3645 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3646 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3647 | (match_dup 1))) |
d3632d41 | 3648 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3649 | (minus:SI (match_dup 1) (match_dup 2)))] |
b2ba71ca | 3650 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 3651 | "@ |
d40c829f UW |
3652 | slr\t%0,%2 |
3653 | sl\t%0,%2 | |
3654 | sly\t%0,%2" | |
d3632d41 | 3655 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3656 | |
3657 | (define_insn "*subsi3_borrow_cconly" | |
ae156f85 | 3658 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3659 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3660 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3661 | (match_dup 1))) |
d3632d41 | 3662 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
b2ba71ca | 3663 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 3664 | "@ |
d40c829f UW |
3665 | slr\t%0,%2 |
3666 | sl\t%0,%2 | |
3667 | sly\t%0,%2" | |
b2ba71ca | 3668 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f | 3669 | |
9db1d521 | 3670 | (define_insn "*subsi3_cc" |
ae156f85 | 3671 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3672 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3673 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3674 | (const_int 0))) |
d3632d41 | 3675 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 | 3676 | (minus:SI (match_dup 1) (match_dup 2)))] |
b2ba71ca | 3677 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3678 | "@ |
d40c829f UW |
3679 | slr\t%0,%2 |
3680 | sl\t%0,%2 | |
3681 | sly\t%0,%2" | |
d3632d41 | 3682 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 3683 | |
5d880bd2 | 3684 | (define_insn "*subsi3_cc2" |
ae156f85 | 3685 | [(set (reg CC_REGNUM) |
5d880bd2 UW |
3686 | (compare (match_operand:SI 1 "register_operand" "0,0,0") |
3687 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
3688 | (set (match_operand:SI 0 "register_operand" "=d,d,d") | |
3689 | (minus:SI (match_dup 1) (match_dup 2)))] | |
3690 | "s390_match_ccmode (insn, CCL3mode)" | |
3691 | "@ | |
3692 | slr\t%0,%2 | |
3693 | sl\t%0,%2 | |
3694 | sly\t%0,%2" | |
3695 | [(set_attr "op_type" "RR,RX,RXY")]) | |
3696 | ||
9db1d521 | 3697 | (define_insn "*subsi3_cconly" |
ae156f85 | 3698 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3699 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3700 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3701 | (const_int 0))) |
d3632d41 | 3702 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
b2ba71ca | 3703 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3704 | "@ |
d40c829f UW |
3705 | slr\t%0,%2 |
3706 | sl\t%0,%2 | |
3707 | sly\t%0,%2" | |
d3632d41 | 3708 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 3709 | |
5d880bd2 | 3710 | (define_insn "*subsi3_cconly2" |
ae156f85 | 3711 | [(set (reg CC_REGNUM) |
5d880bd2 UW |
3712 | (compare (match_operand:SI 1 "register_operand" "0,0,0") |
3713 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
3714 | (clobber (match_scratch:SI 0 "=d,d,d"))] | |
3715 | "s390_match_ccmode (insn, CCL3mode)" | |
3716 | "@ | |
3717 | slr\t%0,%2 | |
3718 | sl\t%0,%2 | |
3719 | sly\t%0,%2" | |
3720 | [(set_attr "op_type" "RR,RX,RXY")]) | |
3721 | ||
07893d4f | 3722 | (define_insn "*subsi3_sign" |
d3632d41 UW |
3723 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3724 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
3725 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
ae156f85 | 3726 | (clobber (reg:CC CC_REGNUM))] |
07893d4f | 3727 | "" |
d3632d41 | 3728 | "@ |
d40c829f UW |
3729 | sh\t%0,%2 |
3730 | shy\t%0,%2" | |
d3632d41 | 3731 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f | 3732 | |
9db1d521 | 3733 | (define_insn "subsi3" |
d3632d41 UW |
3734 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
3735 | (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") | |
3736 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
ae156f85 | 3737 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3738 | "" |
3739 | "@ | |
d40c829f UW |
3740 | sr\t%0,%2 |
3741 | s\t%0,%2 | |
3742 | sy\t%0,%2" | |
d3632d41 | 3743 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 3744 | |
9db1d521 HP |
3745 | |
3746 | ; | |
f5905b37 | 3747 | ; sub(df|sf)3 instruction pattern(s). |
9db1d521 HP |
3748 | ; |
3749 | ||
f5905b37 | 3750 | (define_expand "sub<mode>3" |
9db1d521 | 3751 | [(parallel |
f5905b37 AS |
3752 | [(set (match_operand:FPR 0 "register_operand" "=f,f") |
3753 | (minus:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
3754 | (match_operand:FPR 2 "general_operand" "f,R"))) | |
ae156f85 | 3755 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
3756 | "TARGET_HARD_FLOAT" |
3757 | "") | |
3758 | ||
f5905b37 AS |
3759 | (define_insn "*sub<mode>3" |
3760 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
3761 | (minus:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
3762 | (match_operand:FPR 2 "general_operand" "f,R"))) | |
ae156f85 | 3763 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3764 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3765 | "@ | |
f5905b37 AS |
3766 | s<de>br\t%0,%2 |
3767 | s<de>b\t%0,%2" | |
ce50cae8 | 3768 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 3769 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 3770 | |
f5905b37 | 3771 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 3772 | [(set (reg CC_REGNUM) |
f5905b37 AS |
3773 | (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0") |
3774 | (match_operand:FPR 2 "general_operand" "f,R")) | |
3775 | (match_operand:FPR 3 "const0_operand" ""))) | |
3776 | (set (match_operand:FPR 0 "register_operand" "=f,f") | |
3777 | (minus:FPR (match_dup 1) (match_dup 2)))] | |
3ef093a8 AK |
3778 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3779 | "@ | |
f5905b37 AS |
3780 | s<de>br\t%0,%2 |
3781 | s<de>b\t%0,%2" | |
3ef093a8 | 3782 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 3783 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 3784 | |
f5905b37 | 3785 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 3786 | [(set (reg CC_REGNUM) |
f5905b37 AS |
3787 | (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0") |
3788 | (match_operand:FPR 2 "general_operand" "f,R")) | |
3789 | (match_operand:FPR 3 "const0_operand" ""))) | |
3790 | (clobber (match_scratch:FPR 0 "=f,f"))] | |
3ef093a8 AK |
3791 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3792 | "@ | |
f5905b37 AS |
3793 | s<de>br\t%0,%2 |
3794 | s<de>b\t%0,%2" | |
3ef093a8 | 3795 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 3796 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 3797 | |
f5905b37 AS |
3798 | (define_insn "*sub<mode>3_ibm" |
3799 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
3800 | (minus:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
3801 | (match_operand:FPR 2 "general_operand" "f,R"))) | |
ae156f85 | 3802 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3803 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
3804 | "@ | |
f5905b37 AS |
3805 | s<de>r\t%0,%2 |
3806 | s<de>\t%0,%2" | |
9db1d521 | 3807 | [(set_attr "op_type" "RR,RX") |
f5905b37 | 3808 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 HP |
3809 | |
3810 | ||
e69166de UW |
3811 | ;; |
3812 | ;;- Conditional add/subtract instructions. | |
3813 | ;; | |
3814 | ||
3815 | ; | |
9a91a21f | 3816 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
3817 | ; |
3818 | ||
9a91a21f | 3819 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 3820 | [(set (reg CC_REGNUM) |
e69166de | 3821 | (compare |
9a91a21f AS |
3822 | (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0") |
3823 | (match_operand:GPR 2 "general_operand" "d,m")) | |
3824 | (match_operand:GPR 3 "s390_alc_comparison" "")) | |
e69166de | 3825 | (const_int 0))) |
9a91a21f AS |
3826 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
3827 | (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 3828 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 3829 | "@ |
9a91a21f AS |
3830 | alc<g>r\t%0,%2 |
3831 | alc<g>\t%0,%2" | |
e69166de UW |
3832 | [(set_attr "op_type" "RRE,RXY")]) |
3833 | ||
9a91a21f AS |
3834 | (define_insn "*add<mode>3_alc" |
3835 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3836 | (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0") | |
3837 | (match_operand:GPR 2 "general_operand" "d,m")) | |
3838 | (match_operand:GPR 3 "s390_alc_comparison" ""))) | |
ae156f85 | 3839 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 3840 | "TARGET_CPU_ZARCH" |
e69166de | 3841 | "@ |
9a91a21f AS |
3842 | alc<g>r\t%0,%2 |
3843 | alc<g>\t%0,%2" | |
e69166de UW |
3844 | [(set_attr "op_type" "RRE,RXY")]) |
3845 | ||
9a91a21f | 3846 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 3847 | [(set (reg CC_REGNUM) |
e69166de | 3848 | (compare |
9a91a21f AS |
3849 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
3850 | (match_operand:GPR 2 "general_operand" "d,m")) | |
3851 | (match_operand:GPR 3 "s390_slb_comparison" "")) | |
e69166de | 3852 | (const_int 0))) |
9a91a21f AS |
3853 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
3854 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 3855 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 3856 | "@ |
9a91a21f AS |
3857 | slb<g>r\t%0,%2 |
3858 | slb<g>\t%0,%2" | |
e69166de UW |
3859 | [(set_attr "op_type" "RRE,RXY")]) |
3860 | ||
9a91a21f AS |
3861 | (define_insn "*sub<mode>3_slb" |
3862 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3863 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
3864 | (match_operand:GPR 2 "general_operand" "d,m")) | |
3865 | (match_operand:GPR 3 "s390_slb_comparison" ""))) | |
ae156f85 | 3866 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 3867 | "TARGET_CPU_ZARCH" |
e69166de | 3868 | "@ |
9a91a21f AS |
3869 | slb<g>r\t%0,%2 |
3870 | slb<g>\t%0,%2" | |
e69166de UW |
3871 | [(set_attr "op_type" "RRE,RXY")]) |
3872 | ||
9a91a21f AS |
3873 | (define_expand "add<mode>cc" |
3874 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 3875 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
3876 | (match_operand:GPR 2 "register_operand" "") |
3877 | (match_operand:GPR 3 "const_int_operand" "")] | |
5d880bd2 UW |
3878 | "TARGET_CPU_ZARCH" |
3879 | "if (!s390_expand_addcc (GET_CODE (operands[1]), | |
3880 | s390_compare_op0, s390_compare_op1, | |
3881 | operands[0], operands[2], | |
3882 | operands[3])) FAIL; DONE;") | |
3883 | ||
3884 | ; | |
3885 | ; scond instruction pattern(s). | |
3886 | ; | |
3887 | ||
9a91a21f AS |
3888 | (define_insn_and_split "*scond<mode>" |
3889 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
3890 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 3891 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
3892 | "TARGET_CPU_ZARCH" |
3893 | "#" | |
3894 | "&& reload_completed" | |
3895 | [(set (match_dup 0) (const_int 0)) | |
3896 | (parallel | |
9a91a21f | 3897 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0)) |
5d880bd2 | 3898 | (match_dup 1))) |
ae156f85 | 3899 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 3900 | "") |
5d880bd2 | 3901 | |
9a91a21f AS |
3902 | (define_insn_and_split "*scond<mode>_neg" |
3903 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
3904 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 3905 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
3906 | "TARGET_CPU_ZARCH" |
3907 | "#" | |
3908 | "&& reload_completed" | |
3909 | [(set (match_dup 0) (const_int 0)) | |
3910 | (parallel | |
9a91a21f AS |
3911 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
3912 | (match_dup 1))) | |
ae156f85 | 3913 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 3914 | (parallel |
9a91a21f | 3915 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 3916 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 3917 | "") |
5d880bd2 | 3918 | |
5d880bd2 | 3919 | |
9a91a21f AS |
3920 | (define_expand "s<code>" |
3921 | [(set (match_operand:SI 0 "register_operand" "") | |
3922 | (SCOND (match_dup 0) | |
3923 | (match_dup 0)))] | |
5d880bd2 | 3924 | "TARGET_CPU_ZARCH" |
9a91a21f | 3925 | "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1, |
5d880bd2 UW |
3926 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
3927 | ||
e69166de | 3928 | |
9db1d521 HP |
3929 | ;; |
3930 | ;;- Multiply instructions. | |
3931 | ;; | |
3932 | ||
4023fb28 UW |
3933 | ; |
3934 | ; muldi3 instruction pattern(s). | |
3935 | ; | |
9db1d521 | 3936 | |
07893d4f UW |
3937 | (define_insn "*muldi3_sign" |
3938 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3939 | (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")) | |
3940 | (match_operand:DI 1 "register_operand" "0,0")))] | |
3941 | "TARGET_64BIT" | |
3942 | "@ | |
d40c829f UW |
3943 | msgfr\t%0,%2 |
3944 | msgf\t%0,%2" | |
d3632d41 | 3945 | [(set_attr "op_type" "RRE,RXY") |
ed0e512a | 3946 | (set_attr "type" "imuldi")]) |
07893d4f | 3947 | |
4023fb28 | 3948 | (define_insn "muldi3" |
9db1d521 | 3949 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
96fd3851 | 3950 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
07893d4f | 3951 | (match_operand:DI 2 "general_operand" "d,K,m")))] |
9db1d521 HP |
3952 | "TARGET_64BIT" |
3953 | "@ | |
d40c829f UW |
3954 | msgr\t%0,%2 |
3955 | mghi\t%0,%h2 | |
3956 | msg\t%0,%2" | |
d3632d41 | 3957 | [(set_attr "op_type" "RRE,RI,RXY") |
ed0e512a | 3958 | (set_attr "type" "imuldi")]) |
f2d3c02a | 3959 | |
9db1d521 HP |
3960 | ; |
3961 | ; mulsi3 instruction pattern(s). | |
3962 | ; | |
3963 | ||
f1e77d83 UW |
3964 | (define_insn "*mulsi3_sign" |
3965 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3966 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R")) | |
3967 | (match_operand:SI 1 "register_operand" "0")))] | |
3968 | "" | |
3969 | "mh\t%0,%2" | |
3970 | [(set_attr "op_type" "RX") | |
ed0e512a | 3971 | (set_attr "type" "imulhi")]) |
f1e77d83 | 3972 | |
9db1d521 | 3973 | (define_insn "mulsi3" |
d3632d41 UW |
3974 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
3975 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
3976 | (match_operand:SI 2 "general_operand" "d,K,R,T")))] | |
9db1d521 HP |
3977 | "" |
3978 | "@ | |
d40c829f UW |
3979 | msr\t%0,%2 |
3980 | mhi\t%0,%h2 | |
3981 | ms\t%0,%2 | |
3982 | msy\t%0,%2" | |
d3632d41 | 3983 | [(set_attr "op_type" "RRE,RI,RX,RXY") |
ed0e512a | 3984 | (set_attr "type" "imulsi,imulhi,imulsi,imulsi")]) |
9db1d521 | 3985 | |
4023fb28 UW |
3986 | ; |
3987 | ; mulsidi3 instruction pattern(s). | |
3988 | ; | |
3989 | ||
f1e77d83 UW |
3990 | (define_insn "mulsidi3" |
3991 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3992 | (mult:DI (sign_extend:DI | |
3993 | (match_operand:SI 1 "register_operand" "%0,0")) | |
3994 | (sign_extend:DI | |
3995 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))] | |
4023fb28 | 3996 | "!TARGET_64BIT" |
f1e77d83 UW |
3997 | "@ |
3998 | mr\t%0,%2 | |
3999 | m\t%0,%2" | |
4000 | [(set_attr "op_type" "RR,RX") | |
ed0e512a | 4001 | (set_attr "type" "imulsi")]) |
4023fb28 | 4002 | |
f1e77d83 UW |
4003 | ; |
4004 | ; umulsidi3 instruction pattern(s). | |
4005 | ; | |
c7453384 | 4006 | |
f1e77d83 UW |
4007 | (define_insn "umulsidi3" |
4008 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4009 | (mult:DI (zero_extend:DI | |
4010 | (match_operand:SI 1 "register_operand" "%0,0")) | |
4011 | (zero_extend:DI | |
4012 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))] | |
4013 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4014 | "@ | |
4015 | mlr\t%0,%2 | |
4016 | ml\t%0,%2" | |
4017 | [(set_attr "op_type" "RRE,RXY") | |
ed0e512a | 4018 | (set_attr "type" "imulsi")]) |
c7453384 | 4019 | |
9db1d521 | 4020 | ; |
f5905b37 | 4021 | ; mul(df|sf)3 instruction pattern(s). |
9db1d521 HP |
4022 | ; |
4023 | ||
f5905b37 AS |
4024 | (define_expand "mul<mode>3" |
4025 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4026 | (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
4027 | (match_operand:FPR 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4028 | "TARGET_HARD_FLOAT" |
4029 | "") | |
4030 | ||
f5905b37 AS |
4031 | (define_insn "*mul<mode>3" |
4032 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4033 | (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
4034 | (match_operand:FPR 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4035 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4036 | "@ | |
f5905b37 AS |
4037 | m<dee>br\t%0,%2 |
4038 | m<dee>b\t%0,%2" | |
ce50cae8 | 4039 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4040 | (set_attr "type" "fmul<mode>")]) |
9db1d521 | 4041 | |
f5905b37 AS |
4042 | (define_insn "*mul<mode>3_ibm" |
4043 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4044 | (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
4045 | (match_operand:FPR 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4046 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4047 | "@ | |
f5905b37 AS |
4048 | m<de>r\t%0,%2 |
4049 | m<de>\t%0,%2" | |
9db1d521 | 4050 | [(set_attr "op_type" "RR,RX") |
f5905b37 | 4051 | (set_attr "type" "fmul<mode>")]) |
9db1d521 | 4052 | |
f5905b37 AS |
4053 | (define_insn "*fmadd<mode>" |
4054 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4055 | (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f") | |
4056 | (match_operand:FPR 2 "nonimmediate_operand" "f,R")) | |
4057 | (match_operand:FPR 3 "register_operand" "0,0")))] | |
f2d226e1 | 4058 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 | 4059 | "@ |
f5905b37 AS |
4060 | ma<de>br\t%0,%1,%2 |
4061 | ma<de>b\t%0,%1,%2" | |
a1b892b5 | 4062 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4063 | (set_attr "type" "fmul<mode>")]) |
a1b892b5 | 4064 | |
f5905b37 AS |
4065 | (define_insn "*fmsub<mode>" |
4066 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4067 | (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f") | |
4068 | (match_operand:FPR 2 "nonimmediate_operand" "f,R")) | |
4069 | (match_operand:FPR 3 "register_operand" "0,0")))] | |
f2d226e1 | 4070 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 | 4071 | "@ |
f5905b37 AS |
4072 | ms<de>br\t%0,%1,%2 |
4073 | ms<de>b\t%0,%1,%2" | |
ce50cae8 | 4074 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4075 | (set_attr "type" "fmul<mode>")]) |
9db1d521 HP |
4076 | |
4077 | ;; | |
4078 | ;;- Divide and modulo instructions. | |
4079 | ;; | |
4080 | ||
4081 | ; | |
4023fb28 | 4082 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
4083 | ; |
4084 | ||
4023fb28 UW |
4085 | (define_expand "divmoddi4" |
4086 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 4087 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
4088 | (match_operand:DI 2 "general_operand" ""))) |
4089 | (set (match_operand:DI 3 "general_operand" "") | |
4090 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
4091 | (clobber (match_dup 4))] | |
9db1d521 | 4092 | "TARGET_64BIT" |
9db1d521 | 4093 | { |
f1e77d83 | 4094 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
4095 | |
4096 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
4097 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
4098 | |
4099 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 4100 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
4101 | |
4102 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4103 | REG_NOTES (insn) = | |
4104 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4105 | ||
4106 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4107 | REG_NOTES (insn) = | |
4108 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4109 | |
9db1d521 | 4110 | DONE; |
10bbf137 | 4111 | }) |
9db1d521 HP |
4112 | |
4113 | (define_insn "divmodtidi3" | |
4023fb28 UW |
4114 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
4115 | (ior:TI | |
4023fb28 UW |
4116 | (ashift:TI |
4117 | (zero_extend:TI | |
5665e398 UW |
4118 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
4119 | (match_operand:DI 2 "general_operand" "d,m"))) | |
4120 | (const_int 64)) | |
4121 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9db1d521 HP |
4122 | "TARGET_64BIT" |
4123 | "@ | |
d40c829f UW |
4124 | dsgr\t%0,%2 |
4125 | dsg\t%0,%2" | |
d3632d41 | 4126 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4127 | (set_attr "type" "idiv")]) |
9db1d521 | 4128 | |
4023fb28 UW |
4129 | (define_insn "divmodtisi3" |
4130 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
4131 | (ior:TI | |
4023fb28 UW |
4132 | (ashift:TI |
4133 | (zero_extend:TI | |
5665e398 | 4134 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 4135 | (sign_extend:DI |
5665e398 UW |
4136 | (match_operand:SI 2 "nonimmediate_operand" "d,m")))) |
4137 | (const_int 64)) | |
4138 | (zero_extend:TI | |
4139 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9db1d521 | 4140 | "TARGET_64BIT" |
4023fb28 | 4141 | "@ |
d40c829f UW |
4142 | dsgfr\t%0,%2 |
4143 | dsgf\t%0,%2" | |
d3632d41 | 4144 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4145 | (set_attr "type" "idiv")]) |
9db1d521 | 4146 | |
4023fb28 UW |
4147 | ; |
4148 | ; udivmoddi4 instruction pattern(s). | |
4149 | ; | |
9db1d521 | 4150 | |
4023fb28 UW |
4151 | (define_expand "udivmoddi4" |
4152 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
4153 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
4154 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
4155 | (set (match_operand:DI 3 "general_operand" "") | |
4156 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
4157 | (clobber (match_dup 4))] | |
9db1d521 | 4158 | "TARGET_64BIT" |
9db1d521 | 4159 | { |
4023fb28 UW |
4160 | rtx insn, div_equal, mod_equal, equal; |
4161 | ||
4162 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
4163 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
4164 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
4165 | gen_rtx_ASHIFT (TImode, |
4166 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
4167 | GEN_INT (64)), |
4168 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
4169 | |
4170 | operands[4] = gen_reg_rtx(TImode); | |
4171 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4172 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); | |
4173 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
4174 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); | |
4175 | REG_NOTES (insn) = | |
4176 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4177 | ||
4178 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4179 | REG_NOTES (insn) = | |
4180 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4181 | ||
4182 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4183 | REG_NOTES (insn) = | |
4184 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4185 | |
9db1d521 | 4186 | DONE; |
10bbf137 | 4187 | }) |
9db1d521 HP |
4188 | |
4189 | (define_insn "udivmodtidi3" | |
4023fb28 | 4190 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 4191 | (ior:TI |
5665e398 UW |
4192 | (ashift:TI |
4193 | (zero_extend:TI | |
4194 | (truncate:DI | |
2f7e5a0d EC |
4195 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
4196 | (zero_extend:TI | |
5665e398 UW |
4197 | (match_operand:DI 2 "nonimmediate_operand" "d,m"))))) |
4198 | (const_int 64)) | |
4199 | (zero_extend:TI | |
4200 | (truncate:DI | |
4201 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9db1d521 HP |
4202 | "TARGET_64BIT" |
4203 | "@ | |
d40c829f UW |
4204 | dlgr\t%0,%2 |
4205 | dlg\t%0,%2" | |
d3632d41 | 4206 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4207 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4208 | |
4209 | ; | |
4023fb28 | 4210 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
4211 | ; |
4212 | ||
4023fb28 UW |
4213 | (define_expand "divmodsi4" |
4214 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4215 | (div:SI (match_operand:SI 1 "general_operand" "") | |
4216 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4217 | (set (match_operand:SI 3 "general_operand" "") | |
4218 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
4219 | (clobber (match_dup 4))] | |
9db1d521 | 4220 | "!TARGET_64BIT" |
9db1d521 | 4221 | { |
4023fb28 UW |
4222 | rtx insn, div_equal, mod_equal, equal; |
4223 | ||
4224 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
4225 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
4226 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4227 | gen_rtx_ASHIFT (DImode, |
4228 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
4229 | GEN_INT (32)), |
4230 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
4231 | |
4232 | operands[4] = gen_reg_rtx(DImode); | |
4233 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
4234 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); | |
4235 | REG_NOTES (insn) = | |
4236 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4237 | ||
4238 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4239 | REG_NOTES (insn) = | |
4240 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4241 | ||
4242 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4243 | REG_NOTES (insn) = | |
4244 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4245 | |
9db1d521 | 4246 | DONE; |
10bbf137 | 4247 | }) |
9db1d521 HP |
4248 | |
4249 | (define_insn "divmoddisi3" | |
4023fb28 | 4250 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 4251 | (ior:DI |
5665e398 UW |
4252 | (ashift:DI |
4253 | (zero_extend:DI | |
4254 | (truncate:SI | |
2f7e5a0d EC |
4255 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
4256 | (sign_extend:DI | |
5665e398 UW |
4257 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
4258 | (const_int 32)) | |
4259 | (zero_extend:DI | |
4260 | (truncate:SI | |
4261 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9db1d521 HP |
4262 | "!TARGET_64BIT" |
4263 | "@ | |
d40c829f UW |
4264 | dr\t%0,%2 |
4265 | d\t%0,%2" | |
9db1d521 | 4266 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4267 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4268 | |
4269 | ; | |
4270 | ; udivsi3 and umodsi3 instruction pattern(s). | |
4271 | ; | |
4272 | ||
f1e77d83 UW |
4273 | (define_expand "udivmodsi4" |
4274 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4275 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4276 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4277 | (set (match_operand:SI 3 "general_operand" "") | |
4278 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
4279 | (clobber (match_dup 4))] | |
4280 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4281 | { | |
4282 | rtx insn, div_equal, mod_equal, equal; | |
4283 | ||
4284 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4285 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4286 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
4287 | gen_rtx_ASHIFT (DImode, |
4288 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
4289 | GEN_INT (32)), |
4290 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
4291 | |
4292 | operands[4] = gen_reg_rtx(DImode); | |
4293 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4294 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); | |
4295 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
4296 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); | |
4297 | REG_NOTES (insn) = | |
4298 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4299 | ||
4300 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4301 | REG_NOTES (insn) = | |
4302 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4303 | ||
4304 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4305 | REG_NOTES (insn) = | |
4306 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
4307 | ||
4308 | DONE; | |
4309 | }) | |
4310 | ||
4311 | (define_insn "udivmoddisi3" | |
4312 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 4313 | (ior:DI |
5665e398 UW |
4314 | (ashift:DI |
4315 | (zero_extend:DI | |
4316 | (truncate:SI | |
2f7e5a0d EC |
4317 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
4318 | (zero_extend:DI | |
5665e398 UW |
4319 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))) |
4320 | (const_int 32)) | |
4321 | (zero_extend:DI | |
4322 | (truncate:SI | |
4323 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
f1e77d83 UW |
4324 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
4325 | "@ | |
4326 | dlr\t%0,%2 | |
4327 | dl\t%0,%2" | |
4328 | [(set_attr "op_type" "RRE,RXY") | |
4329 | (set_attr "type" "idiv")]) | |
4023fb28 | 4330 | |
9db1d521 HP |
4331 | (define_expand "udivsi3" |
4332 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4333 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
4334 | (match_operand:SI 2 "general_operand" ""))) |
4335 | (clobber (match_dup 3))] | |
f1e77d83 | 4336 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 4337 | { |
4023fb28 UW |
4338 | rtx insn, udiv_equal, umod_equal, equal; |
4339 | ||
4340 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4341 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4342 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4343 | gen_rtx_ASHIFT (DImode, |
4344 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
4345 | GEN_INT (32)), |
4346 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 4347 | |
4023fb28 | 4348 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
4349 | |
4350 | if (CONSTANT_P (operands[2])) | |
4351 | { | |
4352 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
4353 | { | |
4354 | rtx label1 = gen_label_rtx (); | |
4355 | ||
4023fb28 UW |
4356 | operands[1] = make_safe_from (operands[1], operands[0]); |
4357 | emit_move_insn (operands[0], const0_rtx); | |
4358 | emit_insn (gen_cmpsi (operands[1], operands[2])); | |
9db1d521 | 4359 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 | 4360 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
4361 | emit_label (label1); |
4362 | } | |
4363 | else | |
4364 | { | |
c7453384 EC |
4365 | operands[2] = force_reg (SImode, operands[2]); |
4366 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4367 | |
4368 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4369 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4370 | operands[2])); | |
4371 | REG_NOTES (insn) = | |
4372 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4373 | |
4374 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4375 | gen_lowpart (SImode, operands[3])); |
4376 | REG_NOTES (insn) = | |
c7453384 | 4377 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4378 | udiv_equal, REG_NOTES (insn)); |
9db1d521 HP |
4379 | } |
4380 | } | |
4381 | else | |
c7453384 | 4382 | { |
9db1d521 HP |
4383 | rtx label1 = gen_label_rtx (); |
4384 | rtx label2 = gen_label_rtx (); | |
4385 | rtx label3 = gen_label_rtx (); | |
4386 | ||
c7453384 EC |
4387 | operands[1] = force_reg (SImode, operands[1]); |
4388 | operands[1] = make_safe_from (operands[1], operands[0]); | |
4389 | operands[2] = force_reg (SImode, operands[2]); | |
4390 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4391 | |
4392 | emit_move_insn (operands[0], const0_rtx); | |
9db1d521 HP |
4393 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
4394 | emit_jump_insn (gen_bgtu (label3)); | |
220a826e | 4395 | emit_insn (gen_cmpsi (operands[2], const0_rtx)); |
9db1d521 HP |
4396 | emit_jump_insn (gen_blt (label2)); |
4397 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4398 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
4399 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
4400 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4401 | operands[2])); | |
4402 | REG_NOTES (insn) = | |
4403 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4404 | |
4405 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4406 | gen_lowpart (SImode, operands[3])); |
4407 | REG_NOTES (insn) = | |
c7453384 | 4408 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4409 | udiv_equal, REG_NOTES (insn)); |
f314b9b1 | 4410 | emit_jump (label3); |
9db1d521 | 4411 | emit_label (label1); |
4023fb28 | 4412 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 4413 | emit_jump (label3); |
9db1d521 | 4414 | emit_label (label2); |
4023fb28 | 4415 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
4416 | emit_label (label3); |
4417 | } | |
c7453384 | 4418 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 4419 | DONE; |
10bbf137 | 4420 | }) |
9db1d521 HP |
4421 | |
4422 | (define_expand "umodsi3" | |
4423 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4424 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
4425 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
4426 | (clobber (match_dup 3))] | |
f1e77d83 | 4427 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 4428 | { |
4023fb28 UW |
4429 | rtx insn, udiv_equal, umod_equal, equal; |
4430 | ||
4431 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4432 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4433 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4434 | gen_rtx_ASHIFT (DImode, |
4435 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
4436 | GEN_INT (32)), |
4437 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 4438 | |
4023fb28 | 4439 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
4440 | |
4441 | if (CONSTANT_P (operands[2])) | |
4442 | { | |
4443 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
4444 | { | |
4445 | rtx label1 = gen_label_rtx (); | |
4446 | ||
4023fb28 UW |
4447 | operands[1] = make_safe_from (operands[1], operands[0]); |
4448 | emit_move_insn (operands[0], operands[1]); | |
4449 | emit_insn (gen_cmpsi (operands[0], operands[2])); | |
9db1d521 | 4450 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 UW |
4451 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
4452 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
4453 | emit_label (label1); |
4454 | } | |
4455 | else | |
4456 | { | |
c7453384 EC |
4457 | operands[2] = force_reg (SImode, operands[2]); |
4458 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4459 | |
4460 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4461 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4462 | operands[2])); | |
4463 | REG_NOTES (insn) = | |
4464 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4465 | |
4466 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4467 | gen_highpart (SImode, operands[3])); |
4468 | REG_NOTES (insn) = | |
c7453384 | 4469 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4470 | umod_equal, REG_NOTES (insn)); |
9db1d521 HP |
4471 | } |
4472 | } | |
4473 | else | |
4474 | { | |
4475 | rtx label1 = gen_label_rtx (); | |
4476 | rtx label2 = gen_label_rtx (); | |
4477 | rtx label3 = gen_label_rtx (); | |
4478 | ||
c7453384 EC |
4479 | operands[1] = force_reg (SImode, operands[1]); |
4480 | operands[1] = make_safe_from (operands[1], operands[0]); | |
4481 | operands[2] = force_reg (SImode, operands[2]); | |
4482 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 4483 | |
c7453384 | 4484 | emit_move_insn(operands[0], operands[1]); |
4023fb28 | 4485 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
9db1d521 | 4486 | emit_jump_insn (gen_bgtu (label3)); |
220a826e | 4487 | emit_insn (gen_cmpsi (operands[2], const0_rtx)); |
9db1d521 HP |
4488 | emit_jump_insn (gen_blt (label2)); |
4489 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4490 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
4491 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
4492 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4493 | operands[2])); | |
4494 | REG_NOTES (insn) = | |
4495 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4496 | |
4497 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4498 | gen_highpart (SImode, operands[3])); |
4499 | REG_NOTES (insn) = | |
c7453384 | 4500 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4501 | umod_equal, REG_NOTES (insn)); |
f314b9b1 | 4502 | emit_jump (label3); |
9db1d521 | 4503 | emit_label (label1); |
4023fb28 | 4504 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 4505 | emit_jump (label3); |
9db1d521 | 4506 | emit_label (label2); |
4023fb28 | 4507 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
4508 | emit_label (label3); |
4509 | } | |
9db1d521 | 4510 | DONE; |
10bbf137 | 4511 | }) |
9db1d521 HP |
4512 | |
4513 | ; | |
f5905b37 | 4514 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
4515 | ; |
4516 | ||
f5905b37 AS |
4517 | (define_expand "div<mode>3" |
4518 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4519 | (div:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
4520 | (match_operand:FPR 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4521 | "TARGET_HARD_FLOAT" |
4522 | "") | |
4523 | ||
f5905b37 AS |
4524 | (define_insn "*div<mode>3" |
4525 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4526 | (div:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
4527 | (match_operand:FPR 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4528 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4529 | "@ | |
f5905b37 AS |
4530 | d<de>br\t%0,%2 |
4531 | d<de>b\t%0,%2" | |
ce50cae8 | 4532 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4533 | (set_attr "type" "fdiv<mode>")]) |
9db1d521 | 4534 | |
f5905b37 AS |
4535 | (define_insn "*div<mode>3_ibm" |
4536 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4537 | (div:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
4538 | (match_operand:FPR 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4539 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4540 | "@ | |
f5905b37 AS |
4541 | d<de>r\t%0,%2 |
4542 | d<de>\t%0,%2" | |
9db1d521 | 4543 | [(set_attr "op_type" "RR,RX") |
f5905b37 | 4544 | (set_attr "type" "fdiv<mode>")]) |
9db1d521 HP |
4545 | |
4546 | ||
4547 | ;; | |
4548 | ;;- And instructions. | |
4549 | ;; | |
4550 | ||
047d35ed AS |
4551 | (define_expand "and<mode>3" |
4552 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
4553 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
4554 | (match_operand:INT 2 "general_operand" ""))) | |
4555 | (clobber (reg:CC CC_REGNUM))] | |
4556 | "" | |
4557 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
4558 | ||
9db1d521 HP |
4559 | ; |
4560 | ; anddi3 instruction pattern(s). | |
4561 | ; | |
4562 | ||
4563 | (define_insn "*anddi3_cc" | |
ae156f85 | 4564 | [(set (reg CC_REGNUM) |
96fd3851 | 4565 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 4566 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 | 4567 | (const_int 0))) |
4023fb28 | 4568 | (set (match_operand:DI 0 "register_operand" "=d,d") |
9db1d521 HP |
4569 | (and:DI (match_dup 1) (match_dup 2)))] |
4570 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
4571 | "@ | |
d40c829f UW |
4572 | ngr\t%0,%2 |
4573 | ng\t%0,%2" | |
d3632d41 | 4574 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 HP |
4575 | |
4576 | (define_insn "*anddi3_cconly" | |
ae156f85 | 4577 | [(set (reg CC_REGNUM) |
96fd3851 | 4578 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 4579 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 HP |
4580 | (const_int 0))) |
4581 | (clobber (match_scratch:DI 0 "=d,d"))] | |
68f9c5e2 UW |
4582 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT |
4583 | /* Do not steal TM patterns. */ | |
4584 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 4585 | "@ |
d40c829f UW |
4586 | ngr\t%0,%2 |
4587 | ng\t%0,%2" | |
d3632d41 | 4588 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 4589 | |
8cb66696 | 4590 | (define_insn "*anddi3" |
0dfa6c5e | 4591 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") |
8cb66696 | 4592 | (and:DI (match_operand:DI 1 "nonimmediate_operand" |
0dfa6c5e | 4593 | "%d,o,0,0,0,0,0,0,0,0") |
8cb66696 | 4594 | (match_operand:DI 2 "general_operand" |
0dfa6c5e | 4595 | "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q"))) |
ae156f85 | 4596 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
4597 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
4598 | "@ | |
4599 | # | |
4600 | # | |
4601 | nihh\t%0,%j2 | |
4602 | nihl\t%0,%j2 | |
4603 | nilh\t%0,%j2 | |
4604 | nill\t%0,%j2 | |
4605 | ngr\t%0,%2 | |
4606 | ng\t%0,%2 | |
0dfa6c5e | 4607 | # |
19b63d8e | 4608 | #" |
0dfa6c5e UW |
4609 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")]) |
4610 | ||
4611 | (define_split | |
4612 | [(set (match_operand:DI 0 "s_operand" "") | |
4613 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 4614 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
4615 | "reload_completed" |
4616 | [(parallel | |
4617 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 4618 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 4619 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 4620 | |
9db1d521 HP |
4621 | |
4622 | ; | |
4623 | ; andsi3 instruction pattern(s). | |
4624 | ; | |
4625 | ||
4626 | (define_insn "*andsi3_cc" | |
ae156f85 | 4627 | [(set (reg CC_REGNUM) |
d3632d41 UW |
4628 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
4629 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 4630 | (const_int 0))) |
d3632d41 | 4631 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 HP |
4632 | (and:SI (match_dup 1) (match_dup 2)))] |
4633 | "s390_match_ccmode(insn, CCTmode)" | |
4634 | "@ | |
d40c829f UW |
4635 | nr\t%0,%2 |
4636 | n\t%0,%2 | |
4637 | ny\t%0,%2" | |
d3632d41 | 4638 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
4639 | |
4640 | (define_insn "*andsi3_cconly" | |
ae156f85 | 4641 | [(set (reg CC_REGNUM) |
d3632d41 UW |
4642 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
4643 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 4644 | (const_int 0))) |
d3632d41 | 4645 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
68f9c5e2 UW |
4646 | "s390_match_ccmode(insn, CCTmode) |
4647 | /* Do not steal TM patterns. */ | |
4648 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 4649 | "@ |
d40c829f UW |
4650 | nr\t%0,%2 |
4651 | n\t%0,%2 | |
4652 | ny\t%0,%2" | |
d3632d41 | 4653 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 4654 | |
f19a9af7 | 4655 | (define_insn "*andsi3_zarch" |
0dfa6c5e UW |
4656 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,AQ,Q") |
4657 | (and:SI (match_operand:SI 1 "nonimmediate_operand" | |
4658 | "%d,o,0,0,0,0,0,0,0") | |
4659 | (match_operand:SI 2 "general_operand" | |
4660 | "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q"))) | |
ae156f85 | 4661 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 4662 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 4663 | "@ |
f19a9af7 AK |
4664 | # |
4665 | # | |
4666 | nilh\t%0,%j2 | |
2f7e5a0d | 4667 | nill\t%0,%j2 |
d40c829f UW |
4668 | nr\t%0,%2 |
4669 | n\t%0,%2 | |
8cb66696 | 4670 | ny\t%0,%2 |
0dfa6c5e | 4671 | # |
19b63d8e | 4672 | #" |
0dfa6c5e | 4673 | [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SI,SS")]) |
f19a9af7 AK |
4674 | |
4675 | (define_insn "*andsi3_esa" | |
0dfa6c5e UW |
4676 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
4677 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
4678 | (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q"))) | |
ae156f85 | 4679 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 4680 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
4681 | "@ |
4682 | nr\t%0,%2 | |
8cb66696 | 4683 | n\t%0,%2 |
0dfa6c5e | 4684 | # |
19b63d8e | 4685 | #" |
0dfa6c5e UW |
4686 | [(set_attr "op_type" "RR,RX,SI,SS")]) |
4687 | ||
4688 | (define_split | |
4689 | [(set (match_operand:SI 0 "s_operand" "") | |
4690 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 4691 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
4692 | "reload_completed" |
4693 | [(parallel | |
4694 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 4695 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 4696 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 4697 | |
9db1d521 HP |
4698 | ; |
4699 | ; andhi3 instruction pattern(s). | |
4700 | ; | |
4701 | ||
8cb66696 | 4702 | (define_insn "*andhi3_zarch" |
0dfa6c5e UW |
4703 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
4704 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
4705 | (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q"))) | |
ae156f85 | 4706 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 4707 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 4708 | "@ |
d40c829f | 4709 | nr\t%0,%2 |
8cb66696 | 4710 | nill\t%0,%x2 |
0dfa6c5e | 4711 | # |
19b63d8e | 4712 | #" |
0dfa6c5e | 4713 | [(set_attr "op_type" "RR,RI,SI,SS")]) |
8cb66696 UW |
4714 | |
4715 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
4716 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
4717 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
4718 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 4719 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
4720 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4721 | "@ | |
4722 | nr\t%0,%2 | |
0dfa6c5e | 4723 | # |
19b63d8e | 4724 | #" |
0dfa6c5e UW |
4725 | [(set_attr "op_type" "RR,SI,SS")]) |
4726 | ||
4727 | (define_split | |
4728 | [(set (match_operand:HI 0 "s_operand" "") | |
4729 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 4730 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
4731 | "reload_completed" |
4732 | [(parallel | |
4733 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 4734 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 4735 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 4736 | |
9db1d521 HP |
4737 | ; |
4738 | ; andqi3 instruction pattern(s). | |
4739 | ; | |
4740 | ||
8cb66696 UW |
4741 | (define_insn "*andqi3_zarch" |
4742 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
4743 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
4744 | (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
ae156f85 | 4745 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 4746 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 4747 | "@ |
d40c829f | 4748 | nr\t%0,%2 |
8cb66696 | 4749 | nill\t%0,%b2 |
fc0ea003 UW |
4750 | ni\t%S0,%b2 |
4751 | niy\t%S0,%b2 | |
19b63d8e | 4752 | #" |
8cb66696 UW |
4753 | [(set_attr "op_type" "RR,RI,SI,SIY,SS")]) |
4754 | ||
4755 | (define_insn "*andqi3_esa" | |
4756 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
4757 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
4758 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 4759 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 4760 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 4761 | "@ |
8cb66696 | 4762 | nr\t%0,%2 |
fc0ea003 | 4763 | ni\t%S0,%b2 |
19b63d8e | 4764 | #" |
8cb66696 | 4765 | [(set_attr "op_type" "RR,SI,SS")]) |
4023fb28 | 4766 | |
19b63d8e UW |
4767 | ; |
4768 | ; Block and (NC) patterns. | |
4769 | ; | |
4770 | ||
4771 | (define_insn "*nc" | |
4772 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
4773 | (and:BLK (match_dup 0) | |
4774 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
4775 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 4776 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 4777 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 4778 | "nc\t%O0(%2,%R0),%S1" |
b628bd8e | 4779 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
4780 | |
4781 | (define_split | |
4782 | [(set (match_operand 0 "memory_operand" "") | |
4783 | (and (match_dup 0) | |
4784 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 4785 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
4786 | "reload_completed |
4787 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
4788 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
4789 | [(parallel | |
4790 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
4791 | (use (match_dup 2)) | |
ae156f85 | 4792 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
4793 | { |
4794 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
4795 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
4796 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
4797 | }) | |
4798 | ||
4799 | (define_peephole2 | |
4800 | [(parallel | |
4801 | [(set (match_operand:BLK 0 "memory_operand" "") | |
4802 | (and:BLK (match_dup 0) | |
4803 | (match_operand:BLK 1 "memory_operand" ""))) | |
4804 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 4805 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
4806 | (parallel |
4807 | [(set (match_operand:BLK 3 "memory_operand" "") | |
4808 | (and:BLK (match_dup 3) | |
4809 | (match_operand:BLK 4 "memory_operand" ""))) | |
4810 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 4811 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
4812 | "s390_offset_p (operands[0], operands[3], operands[2]) |
4813 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
4814 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" | |
4815 | [(parallel | |
4816 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
4817 | (use (match_dup 8)) | |
ae156f85 | 4818 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
4819 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
4820 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
4821 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
4822 | ||
9db1d521 HP |
4823 | |
4824 | ;; | |
4825 | ;;- Bit set (inclusive or) instructions. | |
4826 | ;; | |
4827 | ||
047d35ed AS |
4828 | (define_expand "ior<mode>3" |
4829 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
4830 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
4831 | (match_operand:INT 2 "general_operand" ""))) | |
4832 | (clobber (reg:CC CC_REGNUM))] | |
4833 | "" | |
4834 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
4835 | ||
9db1d521 HP |
4836 | ; |
4837 | ; iordi3 instruction pattern(s). | |
4838 | ; | |
4839 | ||
4023fb28 | 4840 | (define_insn "*iordi3_cc" |
ae156f85 | 4841 | [(set (reg CC_REGNUM) |
96fd3851 | 4842 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
4843 | (match_operand:DI 2 "general_operand" "d,m")) |
4844 | (const_int 0))) | |
4845 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4846 | (ior:DI (match_dup 1) (match_dup 2)))] | |
4847 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
4848 | "@ | |
d40c829f UW |
4849 | ogr\t%0,%2 |
4850 | og\t%0,%2" | |
d3632d41 | 4851 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
4852 | |
4853 | (define_insn "*iordi3_cconly" | |
ae156f85 | 4854 | [(set (reg CC_REGNUM) |
96fd3851 | 4855 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
4856 | (match_operand:DI 2 "general_operand" "d,m")) |
4857 | (const_int 0))) | |
4858 | (clobber (match_scratch:DI 0 "=d,d"))] | |
4859 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
4860 | "@ | |
d40c829f UW |
4861 | ogr\t%0,%2 |
4862 | og\t%0,%2" | |
d3632d41 | 4863 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 4864 | |
8cb66696 | 4865 | (define_insn "*iordi3" |
0dfa6c5e | 4866 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q") |
bad82153 | 4867 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0") |
8cb66696 | 4868 | (match_operand:DI 2 "general_operand" |
0dfa6c5e | 4869 | "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q"))) |
ae156f85 | 4870 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 4871 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
9db1d521 | 4872 | "@ |
f19a9af7 AK |
4873 | oihh\t%0,%i2 |
4874 | oihl\t%0,%i2 | |
4875 | oilh\t%0,%i2 | |
4876 | oill\t%0,%i2 | |
d40c829f | 4877 | ogr\t%0,%2 |
8cb66696 | 4878 | og\t%0,%2 |
0dfa6c5e | 4879 | # |
19b63d8e | 4880 | #" |
0dfa6c5e UW |
4881 | [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")]) |
4882 | ||
4883 | (define_split | |
4884 | [(set (match_operand:DI 0 "s_operand" "") | |
4885 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 4886 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
4887 | "reload_completed" |
4888 | [(parallel | |
4889 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 4890 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 4891 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 4892 | |
9db1d521 HP |
4893 | ; |
4894 | ; iorsi3 instruction pattern(s). | |
4895 | ; | |
4896 | ||
4023fb28 | 4897 | (define_insn "*iorsi3_cc" |
ae156f85 | 4898 | [(set (reg CC_REGNUM) |
d3632d41 UW |
4899 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
4900 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 4901 | (const_int 0))) |
d3632d41 | 4902 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
4023fb28 UW |
4903 | (ior:SI (match_dup 1) (match_dup 2)))] |
4904 | "s390_match_ccmode(insn, CCTmode)" | |
4905 | "@ | |
d40c829f UW |
4906 | or\t%0,%2 |
4907 | o\t%0,%2 | |
4908 | oy\t%0,%2" | |
d3632d41 | 4909 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
4910 | |
4911 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 4912 | [(set (reg CC_REGNUM) |
d3632d41 UW |
4913 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
4914 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 4915 | (const_int 0))) |
d3632d41 | 4916 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
4023fb28 UW |
4917 | "s390_match_ccmode(insn, CCTmode)" |
4918 | "@ | |
d40c829f UW |
4919 | or\t%0,%2 |
4920 | o\t%0,%2 | |
4921 | oy\t%0,%2" | |
d3632d41 | 4922 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 | 4923 | |
8cb66696 | 4924 | (define_insn "*iorsi3_zarch" |
0dfa6c5e | 4925 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q") |
bad82153 | 4926 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0") |
0dfa6c5e | 4927 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q"))) |
ae156f85 | 4928 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 4929 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 4930 | "@ |
f19a9af7 AK |
4931 | oilh\t%0,%i2 |
4932 | oill\t%0,%i2 | |
d40c829f UW |
4933 | or\t%0,%2 |
4934 | o\t%0,%2 | |
8cb66696 | 4935 | oy\t%0,%2 |
0dfa6c5e | 4936 | # |
19b63d8e | 4937 | #" |
0dfa6c5e | 4938 | [(set_attr "op_type" "RI,RI,RR,RX,RXY,SI,SS")]) |
8cb66696 UW |
4939 | |
4940 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 4941 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 4942 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 4943 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 4944 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 4945 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
4946 | "@ |
4947 | or\t%0,%2 | |
8cb66696 | 4948 | o\t%0,%2 |
0dfa6c5e | 4949 | # |
19b63d8e | 4950 | #" |
0dfa6c5e UW |
4951 | [(set_attr "op_type" "RR,RX,SI,SS")]) |
4952 | ||
4953 | (define_split | |
4954 | [(set (match_operand:SI 0 "s_operand" "") | |
4955 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 4956 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
4957 | "reload_completed" |
4958 | [(parallel | |
4959 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 4960 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 4961 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 4962 | |
4023fb28 UW |
4963 | ; |
4964 | ; iorhi3 instruction pattern(s). | |
4965 | ; | |
4966 | ||
8cb66696 | 4967 | (define_insn "*iorhi3_zarch" |
0dfa6c5e UW |
4968 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
4969 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
4970 | (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q"))) | |
ae156f85 | 4971 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 4972 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 4973 | "@ |
d40c829f | 4974 | or\t%0,%2 |
8cb66696 | 4975 | oill\t%0,%x2 |
0dfa6c5e | 4976 | # |
19b63d8e | 4977 | #" |
0dfa6c5e | 4978 | [(set_attr "op_type" "RR,RI,SI,SS")]) |
8cb66696 UW |
4979 | |
4980 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
4981 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
4982 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
4983 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 4984 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
4985 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4986 | "@ | |
4987 | or\t%0,%2 | |
0dfa6c5e | 4988 | # |
19b63d8e | 4989 | #" |
0dfa6c5e UW |
4990 | [(set_attr "op_type" "RR,SI,SS")]) |
4991 | ||
4992 | (define_split | |
4993 | [(set (match_operand:HI 0 "s_operand" "") | |
4994 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 4995 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
4996 | "reload_completed" |
4997 | [(parallel | |
4998 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 4999 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5000 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 5001 | |
9db1d521 | 5002 | ; |
4023fb28 | 5003 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
5004 | ; |
5005 | ||
8cb66696 UW |
5006 | (define_insn "*iorqi3_zarch" |
5007 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
5008 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5009 | (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
ae156f85 | 5010 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5011 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5012 | "@ |
d40c829f | 5013 | or\t%0,%2 |
8cb66696 | 5014 | oill\t%0,%b2 |
fc0ea003 UW |
5015 | oi\t%S0,%b2 |
5016 | oiy\t%S0,%b2 | |
19b63d8e | 5017 | #" |
8cb66696 UW |
5018 | [(set_attr "op_type" "RR,RI,SI,SIY,SS")]) |
5019 | ||
5020 | (define_insn "*iorqi3_esa" | |
5021 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
5022 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
5023 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 5024 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5025 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5026 | "@ |
8cb66696 | 5027 | or\t%0,%2 |
fc0ea003 | 5028 | oi\t%S0,%b2 |
19b63d8e | 5029 | #" |
8cb66696 | 5030 | [(set_attr "op_type" "RR,SI,SS")]) |
9db1d521 | 5031 | |
19b63d8e UW |
5032 | ; |
5033 | ; Block inclusive or (OC) patterns. | |
5034 | ; | |
5035 | ||
5036 | (define_insn "*oc" | |
5037 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5038 | (ior:BLK (match_dup 0) | |
5039 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5040 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 5041 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 5042 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 5043 | "oc\t%O0(%2,%R0),%S1" |
b628bd8e | 5044 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5045 | |
5046 | (define_split | |
5047 | [(set (match_operand 0 "memory_operand" "") | |
5048 | (ior (match_dup 0) | |
5049 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 5050 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
5051 | "reload_completed |
5052 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5053 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
5054 | [(parallel | |
5055 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
5056 | (use (match_dup 2)) | |
ae156f85 | 5057 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5058 | { |
5059 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
5060 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
5061 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
5062 | }) | |
5063 | ||
5064 | (define_peephole2 | |
5065 | [(parallel | |
5066 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5067 | (ior:BLK (match_dup 0) | |
5068 | (match_operand:BLK 1 "memory_operand" ""))) | |
5069 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 5070 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
5071 | (parallel |
5072 | [(set (match_operand:BLK 3 "memory_operand" "") | |
5073 | (ior:BLK (match_dup 3) | |
5074 | (match_operand:BLK 4 "memory_operand" ""))) | |
5075 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 5076 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5077 | "s390_offset_p (operands[0], operands[3], operands[2]) |
5078 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
5079 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" | |
5080 | [(parallel | |
5081 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
5082 | (use (match_dup 8)) | |
ae156f85 | 5083 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5084 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
5085 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
5086 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
5087 | ||
9db1d521 HP |
5088 | |
5089 | ;; | |
5090 | ;;- Xor instructions. | |
5091 | ;; | |
5092 | ||
047d35ed AS |
5093 | (define_expand "xor<mode>3" |
5094 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
5095 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
5096 | (match_operand:INT 2 "general_operand" ""))) | |
5097 | (clobber (reg:CC CC_REGNUM))] | |
5098 | "" | |
5099 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
5100 | ||
9db1d521 HP |
5101 | ; |
5102 | ; xordi3 instruction pattern(s). | |
5103 | ; | |
5104 | ||
4023fb28 | 5105 | (define_insn "*xordi3_cc" |
ae156f85 | 5106 | [(set (reg CC_REGNUM) |
96fd3851 | 5107 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5108 | (match_operand:DI 2 "general_operand" "d,m")) |
5109 | (const_int 0))) | |
5110 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5111 | (xor:DI (match_dup 1) (match_dup 2)))] | |
5112 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5113 | "@ | |
d40c829f UW |
5114 | xgr\t%0,%2 |
5115 | xg\t%0,%2" | |
d3632d41 | 5116 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5117 | |
5118 | (define_insn "*xordi3_cconly" | |
ae156f85 | 5119 | [(set (reg CC_REGNUM) |
96fd3851 | 5120 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5121 | (match_operand:DI 2 "general_operand" "d,m")) |
5122 | (const_int 0))) | |
5123 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5124 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5125 | "@ | |
d40c829f UW |
5126 | xgr\t%0,%2 |
5127 | xr\t%0,%2" | |
d3632d41 | 5128 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 5129 | |
8cb66696 | 5130 | (define_insn "*xordi3" |
0dfa6c5e UW |
5131 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5132 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
5133 | (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q"))) | |
ae156f85 | 5134 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5135 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5136 | "@ |
d40c829f | 5137 | xgr\t%0,%2 |
8cb66696 | 5138 | xg\t%0,%2 |
0dfa6c5e | 5139 | # |
19b63d8e | 5140 | #" |
0dfa6c5e UW |
5141 | [(set_attr "op_type" "RRE,RXY,SI,SS")]) |
5142 | ||
5143 | (define_split | |
5144 | [(set (match_operand:DI 0 "s_operand" "") | |
5145 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 5146 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5147 | "reload_completed" |
5148 | [(parallel | |
5149 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5150 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5151 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 5152 | |
9db1d521 HP |
5153 | ; |
5154 | ; xorsi3 instruction pattern(s). | |
5155 | ; | |
5156 | ||
4023fb28 | 5157 | (define_insn "*xorsi3_cc" |
ae156f85 | 5158 | [(set (reg CC_REGNUM) |
d3632d41 UW |
5159 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5160 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5161 | (const_int 0))) |
d3632d41 | 5162 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
4023fb28 UW |
5163 | (xor:SI (match_dup 1) (match_dup 2)))] |
5164 | "s390_match_ccmode(insn, CCTmode)" | |
5165 | "@ | |
d40c829f UW |
5166 | xr\t%0,%2 |
5167 | x\t%0,%2 | |
5168 | xy\t%0,%2" | |
d3632d41 | 5169 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5170 | |
5171 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 5172 | [(set (reg CC_REGNUM) |
d3632d41 UW |
5173 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5174 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5175 | (const_int 0))) |
d3632d41 | 5176 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
4023fb28 UW |
5177 | "s390_match_ccmode(insn, CCTmode)" |
5178 | "@ | |
d40c829f UW |
5179 | xr\t%0,%2 |
5180 | x\t%0,%2 | |
5181 | xy\t%0,%2" | |
d3632d41 | 5182 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 5183 | |
8cb66696 | 5184 | (define_insn "*xorsi3" |
0dfa6c5e UW |
5185 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q") |
5186 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5187 | (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q"))) | |
ae156f85 | 5188 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5189 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 5190 | "@ |
d40c829f UW |
5191 | xr\t%0,%2 |
5192 | x\t%0,%2 | |
8cb66696 | 5193 | xy\t%0,%2 |
0dfa6c5e | 5194 | # |
19b63d8e | 5195 | #" |
0dfa6c5e UW |
5196 | [(set_attr "op_type" "RR,RX,RXY,SI,SS")]) |
5197 | ||
5198 | (define_split | |
5199 | [(set (match_operand:SI 0 "s_operand" "") | |
5200 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 5201 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5202 | "reload_completed" |
5203 | [(parallel | |
5204 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5205 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5206 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 5207 | |
9db1d521 HP |
5208 | ; |
5209 | ; xorhi3 instruction pattern(s). | |
5210 | ; | |
5211 | ||
8cb66696 | 5212 | (define_insn "*xorhi3" |
0dfa6c5e UW |
5213 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
5214 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
5215 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 5216 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
5217 | "s390_logical_operator_ok_p (operands)" |
5218 | "@ | |
5219 | xr\t%0,%2 | |
0dfa6c5e | 5220 | # |
19b63d8e | 5221 | #" |
0dfa6c5e UW |
5222 | [(set_attr "op_type" "RR,SI,SS")]) |
5223 | ||
5224 | (define_split | |
5225 | [(set (match_operand:HI 0 "s_operand" "") | |
5226 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 5227 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5228 | "reload_completed" |
5229 | [(parallel | |
5230 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5231 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5232 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 5233 | |
9db1d521 HP |
5234 | ; |
5235 | ; xorqi3 instruction pattern(s). | |
5236 | ; | |
5237 | ||
8cb66696 UW |
5238 | (define_insn "*xorqi3" |
5239 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q") | |
5240 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0") | |
5241 | (match_operand:QI 2 "general_operand" "d,n,n,Q"))) | |
ae156f85 | 5242 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5243 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 5244 | "@ |
8cb66696 | 5245 | xr\t%0,%2 |
fc0ea003 UW |
5246 | xi\t%S0,%b2 |
5247 | xiy\t%S0,%b2 | |
19b63d8e | 5248 | #" |
8cb66696 | 5249 | [(set_attr "op_type" "RR,SI,SIY,SS")]) |
4023fb28 | 5250 | |
19b63d8e UW |
5251 | ; |
5252 | ; Block exclusive or (XC) patterns. | |
5253 | ; | |
5254 | ||
5255 | (define_insn "*xc" | |
5256 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5257 | (xor:BLK (match_dup 0) | |
5258 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5259 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 5260 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 5261 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 5262 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 5263 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5264 | |
5265 | (define_split | |
5266 | [(set (match_operand 0 "memory_operand" "") | |
5267 | (xor (match_dup 0) | |
5268 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 5269 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
5270 | "reload_completed |
5271 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5272 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
5273 | [(parallel | |
5274 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
5275 | (use (match_dup 2)) | |
ae156f85 | 5276 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5277 | { |
5278 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
5279 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
5280 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
5281 | }) | |
5282 | ||
5283 | (define_peephole2 | |
5284 | [(parallel | |
5285 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5286 | (xor:BLK (match_dup 0) | |
5287 | (match_operand:BLK 1 "memory_operand" ""))) | |
5288 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 5289 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
5290 | (parallel |
5291 | [(set (match_operand:BLK 3 "memory_operand" "") | |
5292 | (xor:BLK (match_dup 3) | |
5293 | (match_operand:BLK 4 "memory_operand" ""))) | |
5294 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 5295 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5296 | "s390_offset_p (operands[0], operands[3], operands[2]) |
5297 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
5298 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" | |
5299 | [(parallel | |
5300 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
5301 | (use (match_dup 8)) | |
ae156f85 | 5302 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5303 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
5304 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
5305 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
5306 | ||
5307 | ; | |
5308 | ; Block xor (XC) patterns with src == dest. | |
5309 | ; | |
5310 | ||
5311 | (define_insn "*xc_zero" | |
5312 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5313 | (const_int 0)) | |
5314 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 5315 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 5316 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 5317 | "xc\t%O0(%1,%R0),%S0" |
b628bd8e | 5318 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5319 | |
5320 | (define_peephole2 | |
5321 | [(parallel | |
5322 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5323 | (const_int 0)) | |
5324 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 5325 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
5326 | (parallel |
5327 | [(set (match_operand:BLK 2 "memory_operand" "") | |
5328 | (const_int 0)) | |
5329 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 5330 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5331 | "s390_offset_p (operands[0], operands[2], operands[1]) |
5332 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
5333 | [(parallel | |
5334 | [(set (match_dup 4) (const_int 0)) | |
5335 | (use (match_dup 5)) | |
ae156f85 | 5336 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5337 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
5338 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
5339 | ||
9db1d521 HP |
5340 | |
5341 | ;; | |
5342 | ;;- Negate instructions. | |
5343 | ;; | |
5344 | ||
5345 | ; | |
9a91a21f | 5346 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
5347 | ; |
5348 | ||
9a91a21f | 5349 | (define_expand "neg<mode>2" |
9db1d521 | 5350 | [(parallel |
9a91a21f AS |
5351 | [(set (match_operand:DSI 0 "register_operand" "=d") |
5352 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 5353 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
5354 | "" |
5355 | "") | |
5356 | ||
26a89301 | 5357 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 5358 | [(set (reg CC_REGNUM) |
26a89301 UW |
5359 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
5360 | (match_operand:SI 1 "register_operand" "d") 0) | |
5361 | (const_int 32)) (const_int 32))) | |
5362 | (const_int 0))) | |
5363 | (set (match_operand:DI 0 "register_operand" "=d") | |
5364 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
5365 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
5366 | "lcgfr\t%0,%1" | |
5367 | [(set_attr "op_type" "RRE")]) | |
5368 | ||
5369 | (define_insn "*negdi2_sign" | |
5370 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5371 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 5372 | (clobber (reg:CC CC_REGNUM))] |
26a89301 UW |
5373 | "TARGET_64BIT" |
5374 | "lcgfr\t%0,%1" | |
5375 | [(set_attr "op_type" "RRE")]) | |
5376 | ||
9a91a21f | 5377 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 5378 | [(set (reg CC_REGNUM) |
9a91a21f | 5379 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 5380 | (const_int 0))) |
9a91a21f AS |
5381 | (set (match_operand:GPR 0 "register_operand" "=d") |
5382 | (neg:GPR (match_dup 1)))] | |
5383 | "s390_match_ccmode (insn, CCAmode)" | |
5384 | "lc<g>r\t%0,%1" | |
5385 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 5386 | |
9a91a21f | 5387 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 5388 | [(set (reg CC_REGNUM) |
9a91a21f | 5389 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 5390 | (const_int 0))) |
9a91a21f AS |
5391 | (clobber (match_scratch:GPR 0 "=d"))] |
5392 | "s390_match_ccmode (insn, CCAmode)" | |
5393 | "lc<g>r\t%0,%1" | |
5394 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 5395 | |
9a91a21f AS |
5396 | (define_insn "*neg<mode>2" |
5397 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5398 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 5399 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
5400 | "" |
5401 | "lc<g>r\t%0,%1" | |
5402 | [(set_attr "op_type" "RR<E>")]) | |
9db1d521 | 5403 | |
26a89301 | 5404 | (define_insn_and_split "*negdi2_31" |
9db1d521 HP |
5405 | [(set (match_operand:DI 0 "register_operand" "=d") |
5406 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 5407 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 5408 | "!TARGET_64BIT" |
26a89301 UW |
5409 | "#" |
5410 | "&& reload_completed" | |
5411 | [(parallel | |
5412 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 5413 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 5414 | (parallel |
ae156f85 | 5415 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
5416 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
5417 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
5418 | (set (pc) | |
ae156f85 | 5419 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
5420 | (pc) |
5421 | (label_ref (match_dup 6)))) | |
5422 | (parallel | |
5423 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 5424 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
5425 | (match_dup 6)] |
5426 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
5427 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
5428 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
5429 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
5430 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 5431 | |
9db1d521 | 5432 | ; |
f5905b37 | 5433 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
5434 | ; |
5435 | ||
f5905b37 | 5436 | (define_expand "neg<mode>2" |
9db1d521 | 5437 | [(parallel |
f5905b37 AS |
5438 | [(set (match_operand:FPR 0 "register_operand" "=f") |
5439 | (neg:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 5440 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
5441 | "TARGET_HARD_FLOAT" |
5442 | "") | |
5443 | ||
f5905b37 | 5444 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 5445 | [(set (reg CC_REGNUM) |
f5905b37 AS |
5446 | (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f")) |
5447 | (match_operand:FPR 2 "const0_operand" ""))) | |
5448 | (set (match_operand:FPR 0 "register_operand" "=f") | |
5449 | (neg:FPR (match_dup 1)))] | |
26a89301 | 5450 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 5451 | "lc<de>br\t%0,%1" |
26a89301 | 5452 | [(set_attr "op_type" "RRE") |
f5905b37 | 5453 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 5454 | |
f5905b37 | 5455 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 5456 | [(set (reg CC_REGNUM) |
f5905b37 AS |
5457 | (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f")) |
5458 | (match_operand:FPR 2 "const0_operand" ""))) | |
5459 | (clobber (match_scratch:FPR 0 "=f"))] | |
26a89301 | 5460 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 5461 | "lc<de>br\t%0,%1" |
26a89301 | 5462 | [(set_attr "op_type" "RRE") |
f5905b37 | 5463 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 5464 | |
f5905b37 AS |
5465 | (define_insn "*neg<mode>2" |
5466 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
5467 | (neg:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 5468 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 5469 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 5470 | "lc<de>br\t%0,%1" |
077dab3b | 5471 | [(set_attr "op_type" "RRE") |
f5905b37 | 5472 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 5473 | |
f5905b37 AS |
5474 | (define_insn "*neg<mode>2_ibm" |
5475 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
5476 | (neg:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 5477 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 5478 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
f5905b37 | 5479 | "lc<de>r\t%0,%1" |
077dab3b | 5480 | [(set_attr "op_type" "RR") |
f5905b37 | 5481 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 HP |
5482 | |
5483 | ||
5484 | ;; | |
5485 | ;;- Absolute value instructions. | |
5486 | ;; | |
5487 | ||
5488 | ; | |
9a91a21f | 5489 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
5490 | ; |
5491 | ||
26a89301 | 5492 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 5493 | [(set (reg CC_REGNUM) |
26a89301 UW |
5494 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
5495 | (match_operand:SI 1 "register_operand" "d") 0) | |
5496 | (const_int 32)) (const_int 32))) | |
5497 | (const_int 0))) | |
5498 | (set (match_operand:DI 0 "register_operand" "=d") | |
5499 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
5500 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
5501 | "lpgfr\t%0,%1" | |
5502 | [(set_attr "op_type" "RRE")]) | |
5503 | ||
5504 | (define_insn "*absdi2_sign" | |
5505 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5506 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 5507 | (clobber (reg:CC CC_REGNUM))] |
26a89301 UW |
5508 | "TARGET_64BIT" |
5509 | "lpgfr\t%0,%1" | |
5510 | [(set_attr "op_type" "RRE")]) | |
5511 | ||
9a91a21f | 5512 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 5513 | [(set (reg CC_REGNUM) |
9a91a21f | 5514 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 5515 | (const_int 0))) |
9a91a21f AS |
5516 | (set (match_operand:GPR 0 "register_operand" "=d") |
5517 | (abs:GPR (match_dup 1)))] | |
26a89301 | 5518 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f AS |
5519 | "lp<g>r\t%0,%1" |
5520 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 5521 | |
9a91a21f | 5522 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 5523 | [(set (reg CC_REGNUM) |
9a91a21f | 5524 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 5525 | (const_int 0))) |
9a91a21f | 5526 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 5527 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f AS |
5528 | "lp<g>r\t%0,%1" |
5529 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 5530 | |
9a91a21f AS |
5531 | (define_insn "abs<mode>2" |
5532 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5533 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 5534 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 5535 | "" |
9a91a21f AS |
5536 | "lp<g>r\t%0,%1" |
5537 | [(set_attr "op_type" "RR<E>")]) | |
9db1d521 | 5538 | |
9db1d521 | 5539 | ; |
f5905b37 | 5540 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
5541 | ; |
5542 | ||
f5905b37 | 5543 | (define_expand "abs<mode>2" |
9db1d521 | 5544 | [(parallel |
f5905b37 AS |
5545 | [(set (match_operand:FPR 0 "register_operand" "=f") |
5546 | (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 5547 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
5548 | "TARGET_HARD_FLOAT" |
5549 | "") | |
5550 | ||
f5905b37 | 5551 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 5552 | [(set (reg CC_REGNUM) |
f5905b37 AS |
5553 | (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f")) |
5554 | (match_operand:FPR 2 "const0_operand" ""))) | |
5555 | (set (match_operand:FPR 0 "register_operand" "=f") | |
5556 | (abs:FPR (match_dup 1)))] | |
26a89301 | 5557 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 5558 | "lp<de>br\t%0,%1" |
26a89301 | 5559 | [(set_attr "op_type" "RRE") |
f5905b37 | 5560 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 5561 | |
f5905b37 | 5562 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 5563 | [(set (reg CC_REGNUM) |
f5905b37 AS |
5564 | (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f")) |
5565 | (match_operand:FPR 2 "const0_operand" ""))) | |
5566 | (clobber (match_scratch:FPR 0 "=f"))] | |
26a89301 | 5567 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 5568 | "lp<de>br\t%0,%1" |
26a89301 | 5569 | [(set_attr "op_type" "RRE") |
f5905b37 | 5570 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 5571 | |
f5905b37 AS |
5572 | (define_insn "*abs<mode>2" |
5573 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
5574 | (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 5575 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 5576 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 5577 | "lp<de>br\t%0,%1" |
077dab3b | 5578 | [(set_attr "op_type" "RRE") |
f5905b37 | 5579 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 5580 | |
f5905b37 AS |
5581 | (define_insn "*abs<mode>2_ibm" |
5582 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
5583 | (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 5584 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 5585 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
f5905b37 | 5586 | "lp<de>r\t%0,%1" |
077dab3b | 5587 | [(set_attr "op_type" "RR") |
f5905b37 | 5588 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 5589 | |
3ef093a8 AK |
5590 | ;; |
5591 | ;;- Negated absolute value instructions | |
5592 | ;; | |
5593 | ||
5594 | ; | |
5595 | ; Integer | |
5596 | ; | |
5597 | ||
26a89301 | 5598 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 5599 | [(set (reg CC_REGNUM) |
26a89301 UW |
5600 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
5601 | (match_operand:SI 1 "register_operand" "d") 0) | |
5602 | (const_int 32)) (const_int 32)))) | |
5603 | (const_int 0))) | |
5604 | (set (match_operand:DI 0 "register_operand" "=d") | |
5605 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
5606 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
5607 | "lngfr\t%0,%1" | |
5608 | [(set_attr "op_type" "RRE")]) | |
5609 | ||
5610 | (define_insn "*negabsdi2_sign" | |
5611 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5612 | (neg:DI (abs:DI (sign_extend:DI | |
5613 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 5614 | (clobber (reg:CC CC_REGNUM))] |
26a89301 UW |
5615 | "TARGET_64BIT" |
5616 | "lngfr\t%0,%1" | |
5617 | [(set_attr "op_type" "RRE")]) | |
3ef093a8 | 5618 | |
9a91a21f | 5619 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 5620 | [(set (reg CC_REGNUM) |
9a91a21f | 5621 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 5622 | (const_int 0))) |
9a91a21f AS |
5623 | (set (match_operand:GPR 0 "register_operand" "=d") |
5624 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 5625 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f AS |
5626 | "ln<g>r\t%0,%1" |
5627 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 5628 | |
9a91a21f | 5629 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 5630 | [(set (reg CC_REGNUM) |
9a91a21f | 5631 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 5632 | (const_int 0))) |
9a91a21f | 5633 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 5634 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f AS |
5635 | "ln<g>r\t%0,%1" |
5636 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 5637 | |
9a91a21f AS |
5638 | (define_insn "*negabs<mode>2" |
5639 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5640 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 5641 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 5642 | "" |
9a91a21f AS |
5643 | "ln<g>r\t%0,%1" |
5644 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 5645 | |
3ef093a8 AK |
5646 | ; |
5647 | ; Floating point | |
5648 | ; | |
5649 | ||
f5905b37 | 5650 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 5651 | [(set (reg CC_REGNUM) |
f5905b37 AS |
5652 | (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) |
5653 | (match_operand:FPR 2 "const0_operand" ""))) | |
5654 | (set (match_operand:FPR 0 "register_operand" "=f") | |
5655 | (neg:FPR (abs:FPR (match_dup 1))))] | |
26a89301 | 5656 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 5657 | "ln<de>br\t%0,%1" |
26a89301 | 5658 | [(set_attr "op_type" "RRE") |
f5905b37 | 5659 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 5660 | |
f5905b37 | 5661 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 5662 | [(set (reg CC_REGNUM) |
f5905b37 AS |
5663 | (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) |
5664 | (match_operand:FPR 2 "const0_operand" ""))) | |
5665 | (clobber (match_scratch:FPR 0 "=f"))] | |
26a89301 | 5666 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 5667 | "ln<de>br\t%0,%1" |
26a89301 | 5668 | [(set_attr "op_type" "RRE") |
f5905b37 | 5669 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 5670 | |
f5905b37 AS |
5671 | (define_insn "*negabs<mode>2" |
5672 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
5673 | (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))) | |
ae156f85 | 5674 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 5675 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 5676 | "ln<de>br\t%0,%1" |
26a89301 | 5677 | [(set_attr "op_type" "RRE") |
f5905b37 | 5678 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 5679 | |
4023fb28 UW |
5680 | ;; |
5681 | ;;- Square root instructions. | |
5682 | ;; | |
5683 | ||
5684 | ; | |
f5905b37 | 5685 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
5686 | ; |
5687 | ||
f5905b37 AS |
5688 | (define_insn "sqrt<mode>2" |
5689 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
5690 | (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))] | |
4023fb28 UW |
5691 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
5692 | "@ | |
f5905b37 AS |
5693 | sq<de>br\t%0,%1 |
5694 | sq<de>b\t%0,%1" | |
a036c6f7 | 5695 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 5696 | (set_attr "type" "fsqrt<mode>")]) |
4023fb28 | 5697 | |
9db1d521 HP |
5698 | |
5699 | ;; | |
5700 | ;;- One complement instructions. | |
5701 | ;; | |
5702 | ||
5703 | ; | |
342cf42b | 5704 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 5705 | ; |
c7453384 | 5706 | |
342cf42b | 5707 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 5708 | [(parallel |
342cf42b AS |
5709 | [(set (match_operand:INT 0 "register_operand" "") |
5710 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
5711 | (const_int -1))) | |
ae156f85 | 5712 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5713 | "" |
4023fb28 | 5714 | "") |
9db1d521 HP |
5715 | |
5716 | ||
5717 | ;; | |
5718 | ;;- Rotate instructions. | |
5719 | ;; | |
5720 | ||
5721 | ; | |
9a91a21f | 5722 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
5723 | ; |
5724 | ||
9a91a21f AS |
5725 | (define_insn "rotl<mode>3" |
5726 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5727 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
5728 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9e8327e3 | 5729 | "TARGET_CPU_ZARCH" |
9a91a21f | 5730 | "rll<g>\t%0,%1,%Y2" |
077dab3b HP |
5731 | [(set_attr "op_type" "RSE") |
5732 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
5733 | |
5734 | ||
5735 | ;; | |
f337b930 | 5736 | ;;- Shift instructions. |
9db1d521 | 5737 | ;; |
9db1d521 HP |
5738 | |
5739 | ; | |
f337b930 | 5740 | ; (ashl|lshr)di3 instruction pattern(s). |
9db1d521 HP |
5741 | ; |
5742 | ||
f337b930 | 5743 | (define_expand "<shift>di3" |
ecbe845e | 5744 | [(set (match_operand:DI 0 "register_operand" "") |
f337b930 AS |
5745 | (SHIFT:DI (match_operand:DI 1 "register_operand" "") |
5746 | (match_operand:SI 2 "shift_count_operand" "")))] | |
9db1d521 HP |
5747 | "" |
5748 | "") | |
5749 | ||
f337b930 | 5750 | (define_insn "*<shift>di3_31" |
ac32b25e | 5751 | [(set (match_operand:DI 0 "register_operand" "=d") |
f337b930 AS |
5752 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") |
5753 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 5754 | "!TARGET_64BIT" |
f337b930 | 5755 | "s<lr>dl\t%0,%Y2" |
077dab3b HP |
5756 | [(set_attr "op_type" "RS") |
5757 | (set_attr "atype" "reg")]) | |
9db1d521 | 5758 | |
f337b930 | 5759 | (define_insn "*<shift>di3_64" |
ac32b25e | 5760 | [(set (match_operand:DI 0 "register_operand" "=d") |
f337b930 AS |
5761 | (SHIFT:DI (match_operand:DI 1 "register_operand" "d") |
5762 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 5763 | "TARGET_64BIT" |
f337b930 | 5764 | "s<lr>lg\t%0,%1,%Y2" |
077dab3b HP |
5765 | [(set_attr "op_type" "RSE") |
5766 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
5767 | |
5768 | ; | |
5769 | ; ashrdi3 instruction pattern(s). | |
5770 | ; | |
5771 | ||
5772 | (define_expand "ashrdi3" | |
5773 | [(parallel | |
5774 | [(set (match_operand:DI 0 "register_operand" "") | |
5775 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
ac32b25e | 5776 | (match_operand:SI 2 "shift_count_operand" ""))) |
ae156f85 | 5777 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
5778 | "" |
5779 | "") | |
5780 | ||
ecbe845e | 5781 | (define_insn "*ashrdi3_cc_31" |
ae156f85 | 5782 | [(set (reg CC_REGNUM) |
ac32b25e UW |
5783 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
5784 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 5785 | (const_int 0))) |
ac32b25e | 5786 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e UW |
5787 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
5788 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" | |
ac32b25e | 5789 | "srda\t%0,%Y2" |
077dab3b HP |
5790 | [(set_attr "op_type" "RS") |
5791 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
5792 | |
5793 | (define_insn "*ashrdi3_cconly_31" | |
ae156f85 | 5794 | [(set (reg CC_REGNUM) |
ac32b25e UW |
5795 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
5796 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 5797 | (const_int 0))) |
ac32b25e | 5798 | (clobber (match_scratch:DI 0 "=d"))] |
ecbe845e | 5799 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 5800 | "srda\t%0,%Y2" |
077dab3b HP |
5801 | [(set_attr "op_type" "RS") |
5802 | (set_attr "atype" "reg")]) | |
ecbe845e | 5803 | |
9db1d521 | 5804 | (define_insn "*ashrdi3_31" |
ac32b25e UW |
5805 | [(set (match_operand:DI 0 "register_operand" "=d") |
5806 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
5807 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
ae156f85 | 5808 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 5809 | "!TARGET_64BIT" |
ac32b25e | 5810 | "srda\t%0,%Y2" |
077dab3b HP |
5811 | [(set_attr "op_type" "RS") |
5812 | (set_attr "atype" "reg")]) | |
c7453384 | 5813 | |
ecbe845e | 5814 | (define_insn "*ashrdi3_cc_64" |
ae156f85 | 5815 | [(set (reg CC_REGNUM) |
ac32b25e UW |
5816 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") |
5817 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 5818 | (const_int 0))) |
ac32b25e | 5819 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e UW |
5820 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
5821 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
ac32b25e | 5822 | "srag\t%0,%1,%Y2" |
077dab3b HP |
5823 | [(set_attr "op_type" "RSE") |
5824 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
5825 | |
5826 | (define_insn "*ashrdi3_cconly_64" | |
ae156f85 | 5827 | [(set (reg CC_REGNUM) |
ac32b25e UW |
5828 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") |
5829 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 5830 | (const_int 0))) |
ac32b25e | 5831 | (clobber (match_scratch:DI 0 "=d"))] |
ecbe845e | 5832 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" |
ac32b25e | 5833 | "srag\t%0,%1,%Y2" |
077dab3b HP |
5834 | [(set_attr "op_type" "RSE") |
5835 | (set_attr "atype" "reg")]) | |
ecbe845e | 5836 | |
9db1d521 | 5837 | (define_insn "*ashrdi3_64" |
ac32b25e UW |
5838 | [(set (match_operand:DI 0 "register_operand" "=d") |
5839 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
5840 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
ae156f85 | 5841 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 5842 | "TARGET_64BIT" |
ac32b25e | 5843 | "srag\t%0,%1,%Y2" |
077dab3b HP |
5844 | [(set_attr "op_type" "RSE") |
5845 | (set_attr "atype" "reg")]) | |
5846 | ||
9db1d521 HP |
5847 | |
5848 | ; | |
f337b930 | 5849 | ; (ashl|lshr)si3 instruction pattern(s). |
9db1d521 | 5850 | ; |
9db1d521 | 5851 | |
f337b930 | 5852 | (define_insn "<shift>si3" |
ac32b25e | 5853 | [(set (match_operand:SI 0 "register_operand" "=d") |
f337b930 AS |
5854 | (SHIFT:SI (match_operand:SI 1 "register_operand" "0") |
5855 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 5856 | "" |
f337b930 | 5857 | "s<lr>l\t%0,%Y2" |
077dab3b HP |
5858 | [(set_attr "op_type" "RS") |
5859 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
5860 | |
5861 | ; | |
5862 | ; ashrsi3 instruction pattern(s). | |
5863 | ; | |
5864 | ||
ecbe845e | 5865 | (define_insn "*ashrsi3_cc" |
ae156f85 | 5866 | [(set (reg CC_REGNUM) |
ac32b25e UW |
5867 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") |
5868 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 5869 | (const_int 0))) |
ac32b25e | 5870 | (set (match_operand:SI 0 "register_operand" "=d") |
ecbe845e UW |
5871 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
5872 | "s390_match_ccmode(insn, CCSmode)" | |
ac32b25e | 5873 | "sra\t%0,%Y2" |
077dab3b HP |
5874 | [(set_attr "op_type" "RS") |
5875 | (set_attr "atype" "reg")]) | |
5876 | ||
ecbe845e UW |
5877 | |
5878 | (define_insn "*ashrsi3_cconly" | |
ae156f85 | 5879 | [(set (reg CC_REGNUM) |
ac32b25e UW |
5880 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") |
5881 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 5882 | (const_int 0))) |
ac32b25e | 5883 | (clobber (match_scratch:SI 0 "=d"))] |
ecbe845e | 5884 | "s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 5885 | "sra\t%0,%Y2" |
077dab3b HP |
5886 | [(set_attr "op_type" "RS") |
5887 | (set_attr "atype" "reg")]) | |
ecbe845e | 5888 | |
9db1d521 | 5889 | (define_insn "ashrsi3" |
ac32b25e UW |
5890 | [(set (match_operand:SI 0 "register_operand" "=d") |
5891 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
5892 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
ae156f85 | 5893 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 5894 | "" |
ac32b25e | 5895 | "sra\t%0,%Y2" |
077dab3b HP |
5896 | [(set_attr "op_type" "RS") |
5897 | (set_attr "atype" "reg")]) | |
9db1d521 | 5898 | |
9db1d521 | 5899 | |
9db1d521 HP |
5900 | ;; |
5901 | ;; Branch instruction patterns. | |
5902 | ;; | |
5903 | ||
fa77b251 AS |
5904 | (define_expand "b<code>" |
5905 | [(set (pc) | |
5906 | (if_then_else (COMPARE (match_operand 0 "" "") | |
5907 | (const_int 0)) | |
5908 | (match_dup 0) | |
5909 | (pc)))] | |
ba956982 | 5910 | "" |
6590e19a | 5911 | "s390_emit_jump (operands[0], |
fa77b251 | 5912 | s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;") |
ba956982 | 5913 | |
9db1d521 HP |
5914 | |
5915 | ;; | |
5916 | ;;- Conditional jump instructions. | |
5917 | ;; | |
5918 | ||
6590e19a UW |
5919 | (define_insn "*cjump_64" |
5920 | [(set (pc) | |
5921 | (if_then_else | |
ae156f85 | 5922 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
5923 | (label_ref (match_operand 0 "" "")) |
5924 | (pc)))] | |
5925 | "TARGET_CPU_ZARCH" | |
9db1d521 | 5926 | { |
13e58269 | 5927 | if (get_attr_length (insn) == 4) |
d40c829f | 5928 | return "j%C1\t%l0"; |
6590e19a | 5929 | else |
d40c829f | 5930 | return "jg%C1\t%l0"; |
6590e19a UW |
5931 | } |
5932 | [(set_attr "op_type" "RI") | |
5933 | (set_attr "type" "branch") | |
5934 | (set (attr "length") | |
5935 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
5936 | (const_int 4) (const_int 6)))]) | |
5937 | ||
5938 | (define_insn "*cjump_31" | |
5939 | [(set (pc) | |
5940 | (if_then_else | |
ae156f85 | 5941 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
5942 | (label_ref (match_operand 0 "" "")) |
5943 | (pc)))] | |
5944 | "!TARGET_CPU_ZARCH" | |
5945 | { | |
8d933e31 AS |
5946 | gcc_assert (get_attr_length (insn) == 4); |
5947 | return "j%C1\t%l0"; | |
10bbf137 | 5948 | } |
9db1d521 | 5949 | [(set_attr "op_type" "RI") |
077dab3b | 5950 | (set_attr "type" "branch") |
13e58269 | 5951 | (set (attr "length") |
6590e19a UW |
5952 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
5953 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
5954 | (const_int 4) (const_int 6)) | |
5955 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
5956 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 5957 | |
f314b9b1 | 5958 | (define_insn "*cjump_long" |
6590e19a UW |
5959 | [(set (pc) |
5960 | (if_then_else | |
ae156f85 | 5961 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
5962 | (match_operand 0 "address_operand" "U") |
5963 | (pc)))] | |
9db1d521 | 5964 | "" |
f314b9b1 UW |
5965 | { |
5966 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 5967 | return "b%C1r\t%0"; |
f314b9b1 | 5968 | else |
d40c829f | 5969 | return "b%C1\t%a0"; |
10bbf137 | 5970 | } |
c7453384 | 5971 | [(set (attr "op_type") |
f314b9b1 UW |
5972 | (if_then_else (match_operand 0 "register_operand" "") |
5973 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 5974 | (set_attr "type" "branch") |
077dab3b | 5975 | (set_attr "atype" "agen")]) |
9db1d521 HP |
5976 | |
5977 | ||
5978 | ;; | |
5979 | ;;- Negated conditional jump instructions. | |
5980 | ;; | |
5981 | ||
6590e19a UW |
5982 | (define_insn "*icjump_64" |
5983 | [(set (pc) | |
5984 | (if_then_else | |
ae156f85 | 5985 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
5986 | (pc) |
5987 | (label_ref (match_operand 0 "" ""))))] | |
5988 | "TARGET_CPU_ZARCH" | |
c7453384 | 5989 | { |
13e58269 | 5990 | if (get_attr_length (insn) == 4) |
d40c829f | 5991 | return "j%D1\t%l0"; |
6590e19a | 5992 | else |
d40c829f | 5993 | return "jg%D1\t%l0"; |
6590e19a UW |
5994 | } |
5995 | [(set_attr "op_type" "RI") | |
5996 | (set_attr "type" "branch") | |
5997 | (set (attr "length") | |
5998 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
5999 | (const_int 4) (const_int 6)))]) | |
6000 | ||
6001 | (define_insn "*icjump_31" | |
6002 | [(set (pc) | |
6003 | (if_then_else | |
ae156f85 | 6004 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
6005 | (pc) |
6006 | (label_ref (match_operand 0 "" ""))))] | |
6007 | "!TARGET_CPU_ZARCH" | |
6008 | { | |
8d933e31 AS |
6009 | gcc_assert (get_attr_length (insn) == 4); |
6010 | return "j%D1\t%l0"; | |
10bbf137 | 6011 | } |
9db1d521 | 6012 | [(set_attr "op_type" "RI") |
077dab3b | 6013 | (set_attr "type" "branch") |
13e58269 | 6014 | (set (attr "length") |
6590e19a UW |
6015 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6016 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6017 | (const_int 4) (const_int 6)) | |
6018 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6019 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 6020 | |
f314b9b1 | 6021 | (define_insn "*icjump_long" |
6590e19a UW |
6022 | [(set (pc) |
6023 | (if_then_else | |
ae156f85 | 6024 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
6025 | (pc) |
6026 | (match_operand 0 "address_operand" "U")))] | |
9db1d521 | 6027 | "" |
f314b9b1 UW |
6028 | { |
6029 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6030 | return "b%D1r\t%0"; |
f314b9b1 | 6031 | else |
d40c829f | 6032 | return "b%D1\t%a0"; |
10bbf137 | 6033 | } |
c7453384 | 6034 | [(set (attr "op_type") |
f314b9b1 UW |
6035 | (if_then_else (match_operand 0 "register_operand" "") |
6036 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6037 | (set_attr "type" "branch") |
6038 | (set_attr "atype" "agen")]) | |
9db1d521 | 6039 | |
4456530d HP |
6040 | ;; |
6041 | ;;- Trap instructions. | |
6042 | ;; | |
6043 | ||
6044 | (define_insn "trap" | |
6045 | [(trap_if (const_int 1) (const_int 0))] | |
6046 | "" | |
d40c829f | 6047 | "j\t.+2" |
6590e19a | 6048 | [(set_attr "op_type" "RI") |
077dab3b | 6049 | (set_attr "type" "branch")]) |
4456530d HP |
6050 | |
6051 | (define_expand "conditional_trap" | |
6590e19a UW |
6052 | [(trap_if (match_operand 0 "comparison_operator" "") |
6053 | (match_operand 1 "general_operand" ""))] | |
4456530d | 6054 | "" |
4456530d | 6055 | { |
6590e19a UW |
6056 | if (operands[1] != const0_rtx) FAIL; |
6057 | operands[0] = s390_emit_compare (GET_CODE (operands[0]), | |
6058 | s390_compare_op0, s390_compare_op1); | |
10bbf137 | 6059 | }) |
4456530d HP |
6060 | |
6061 | (define_insn "*trap" | |
ae156f85 | 6062 | [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4456530d HP |
6063 | (const_int 0))] |
6064 | "" | |
d40c829f | 6065 | "j%C0\t.+2"; |
077dab3b HP |
6066 | [(set_attr "op_type" "RI") |
6067 | (set_attr "type" "branch")]) | |
9db1d521 HP |
6068 | |
6069 | ;; | |
0a3bdf9d | 6070 | ;;- Loop instructions. |
9db1d521 | 6071 | ;; |
0a3bdf9d UW |
6072 | ;; This is all complicated by the fact that since this is a jump insn |
6073 | ;; we must handle our own output reloads. | |
c7453384 | 6074 | |
0a3bdf9d UW |
6075 | (define_expand "doloop_end" |
6076 | [(use (match_operand 0 "" "")) ; loop pseudo | |
6077 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
6078 | (use (match_operand 2 "" "")) ; max iterations | |
6079 | (use (match_operand 3 "" "")) ; loop level | |
6080 | (use (match_operand 4 "" ""))] ; label | |
6081 | "" | |
0a3bdf9d | 6082 | { |
6590e19a UW |
6083 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
6084 | emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0])); | |
6085 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) | |
6086 | emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0])); | |
0a3bdf9d UW |
6087 | else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) |
6088 | emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); | |
6089 | else | |
6090 | FAIL; | |
6091 | ||
6092 | DONE; | |
10bbf137 | 6093 | }) |
0a3bdf9d | 6094 | |
6590e19a | 6095 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
6096 | [(set (pc) |
6097 | (if_then_else | |
6098 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6099 | (const_int 1)) | |
6100 | (label_ref (match_operand 0 "" "")) | |
6101 | (pc))) | |
bd446804 | 6102 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") |
0a3bdf9d | 6103 | (plus:SI (match_dup 1) (const_int -1))) |
eb862a88 | 6104 | (clobber (match_scratch:SI 3 "=X,&1")) |
ae156f85 | 6105 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 6106 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
6107 | { |
6108 | if (which_alternative != 0) | |
10bbf137 | 6109 | return "#"; |
0a3bdf9d | 6110 | else if (get_attr_length (insn) == 4) |
d40c829f | 6111 | return "brct\t%1,%l0"; |
6590e19a | 6112 | else |
545d16ff | 6113 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
6114 | } |
6115 | "&& reload_completed | |
6116 | && (! REG_P (operands[2]) | |
6117 | || ! rtx_equal_p (operands[1], operands[2]))" | |
ae156f85 | 6118 | [(parallel [(set (reg:CCAN CC_REGNUM) |
6590e19a UW |
6119 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
6120 | (const_int 0))) | |
6121 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
6122 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 6123 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
6124 | (label_ref (match_dup 0)) |
6125 | (pc)))] | |
6126 | "" | |
6127 | [(set_attr "op_type" "RI") | |
6128 | (set_attr "type" "branch") | |
6129 | (set (attr "length") | |
6130 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6131 | (const_int 4) (const_int 10)))]) | |
6132 | ||
6133 | (define_insn_and_split "doloop_si31" | |
6134 | [(set (pc) | |
6135 | (if_then_else | |
6136 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6137 | (const_int 1)) | |
6138 | (label_ref (match_operand 0 "" "")) | |
6139 | (pc))) | |
6140 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") | |
6141 | (plus:SI (match_dup 1) (const_int -1))) | |
eb862a88 | 6142 | (clobber (match_scratch:SI 3 "=X,&1")) |
ae156f85 | 6143 | (clobber (reg:CC CC_REGNUM))] |
6590e19a UW |
6144 | "!TARGET_CPU_ZARCH" |
6145 | { | |
6146 | if (which_alternative != 0) | |
6147 | return "#"; | |
6148 | else if (get_attr_length (insn) == 4) | |
6149 | return "brct\t%1,%l0"; | |
0a3bdf9d | 6150 | else |
8d933e31 | 6151 | gcc_unreachable (); |
10bbf137 | 6152 | } |
6590e19a UW |
6153 | "&& reload_completed |
6154 | && (! REG_P (operands[2]) | |
6155 | || ! rtx_equal_p (operands[1], operands[2]))" | |
ae156f85 | 6156 | [(parallel [(set (reg:CCAN CC_REGNUM) |
6590e19a UW |
6157 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
6158 | (const_int 0))) | |
6159 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
6160 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 6161 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
6162 | (label_ref (match_dup 0)) |
6163 | (pc)))] | |
6164 | "" | |
0a3bdf9d | 6165 | [(set_attr "op_type" "RI") |
077dab3b | 6166 | (set_attr "type" "branch") |
0a3bdf9d | 6167 | (set (attr "length") |
6590e19a UW |
6168 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6169 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6170 | (const_int 4) (const_int 6)) | |
6171 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6172 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 6173 | |
0a3bdf9d UW |
6174 | (define_insn "*doloop_si_long" |
6175 | [(set (pc) | |
6176 | (if_then_else | |
6177 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6178 | (const_int 1)) | |
d3632d41 | 6179 | (match_operand 0 "address_operand" "U,U") |
0a3bdf9d UW |
6180 | (pc))) |
6181 | (set (match_operand:SI 2 "register_operand" "=1,?*m*d") | |
6182 | (plus:SI (match_dup 1) (const_int -1))) | |
eb862a88 | 6183 | (clobber (match_scratch:SI 3 "=X,&1")) |
ae156f85 | 6184 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 6185 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
6186 | { |
6187 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6188 | return "bctr\t%1,%0"; |
0a3bdf9d | 6189 | else |
d40c829f | 6190 | return "bct\t%1,%a0"; |
10bbf137 | 6191 | } |
c7453384 | 6192 | [(set (attr "op_type") |
0a3bdf9d UW |
6193 | (if_then_else (match_operand 0 "register_operand" "") |
6194 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6195 | (set_attr "type" "branch") |
6196 | (set_attr "atype" "agen")]) | |
0a3bdf9d | 6197 | |
6590e19a | 6198 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
6199 | [(set (pc) |
6200 | (if_then_else | |
6201 | (ne (match_operand:DI 1 "register_operand" "d,d") | |
6202 | (const_int 1)) | |
6203 | (label_ref (match_operand 0 "" "")) | |
6204 | (pc))) | |
eb862a88 | 6205 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d") |
0a3bdf9d | 6206 | (plus:DI (match_dup 1) (const_int -1))) |
eb862a88 | 6207 | (clobber (match_scratch:DI 3 "=X,&1")) |
ae156f85 | 6208 | (clobber (reg:CC CC_REGNUM))] |
0a3bdf9d | 6209 | "TARGET_64BIT" |
0a3bdf9d UW |
6210 | { |
6211 | if (which_alternative != 0) | |
10bbf137 | 6212 | return "#"; |
0a3bdf9d | 6213 | else if (get_attr_length (insn) == 4) |
d40c829f | 6214 | return "brctg\t%1,%l0"; |
0a3bdf9d | 6215 | else |
545d16ff | 6216 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 6217 | } |
6590e19a | 6218 | "&& reload_completed |
0a3bdf9d UW |
6219 | && (! REG_P (operands[2]) |
6220 | || ! rtx_equal_p (operands[1], operands[2]))" | |
ae156f85 | 6221 | [(parallel [(set (reg:CCAN CC_REGNUM) |
0a3bdf9d UW |
6222 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
6223 | (const_int 0))) | |
6224 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
6225 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 6226 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 6227 | (label_ref (match_dup 0)) |
0a3bdf9d | 6228 | (pc)))] |
6590e19a UW |
6229 | "" |
6230 | [(set_attr "op_type" "RI") | |
6231 | (set_attr "type" "branch") | |
6232 | (set (attr "length") | |
6233 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6234 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
6235 | |
6236 | ;; | |
6237 | ;;- Unconditional jump instructions. | |
6238 | ;; | |
6239 | ||
6240 | ; | |
6241 | ; jump instruction pattern(s). | |
6242 | ; | |
6243 | ||
6590e19a UW |
6244 | (define_expand "jump" |
6245 | [(match_operand 0 "" "")] | |
9db1d521 | 6246 | "" |
6590e19a UW |
6247 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
6248 | ||
6249 | (define_insn "*jump64" | |
6250 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
6251 | "TARGET_CPU_ZARCH" | |
9db1d521 | 6252 | { |
13e58269 | 6253 | if (get_attr_length (insn) == 4) |
d40c829f | 6254 | return "j\t%l0"; |
6590e19a | 6255 | else |
d40c829f | 6256 | return "jg\t%l0"; |
6590e19a UW |
6257 | } |
6258 | [(set_attr "op_type" "RI") | |
6259 | (set_attr "type" "branch") | |
6260 | (set (attr "length") | |
6261 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6262 | (const_int 4) (const_int 6)))]) | |
6263 | ||
6264 | (define_insn "*jump31" | |
6265 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
6266 | "!TARGET_CPU_ZARCH" | |
6267 | { | |
8d933e31 AS |
6268 | gcc_assert (get_attr_length (insn) == 4); |
6269 | return "j\t%l0"; | |
10bbf137 | 6270 | } |
9db1d521 | 6271 | [(set_attr "op_type" "RI") |
077dab3b | 6272 | (set_attr "type" "branch") |
13e58269 | 6273 | (set (attr "length") |
6590e19a UW |
6274 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6275 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6276 | (const_int 4) (const_int 6)) | |
6277 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6278 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
6279 | |
6280 | ; | |
6281 | ; indirect-jump instruction pattern(s). | |
6282 | ; | |
6283 | ||
6284 | (define_insn "indirect_jump" | |
d3632d41 | 6285 | [(set (pc) (match_operand 0 "address_operand" "U"))] |
9db1d521 | 6286 | "" |
f314b9b1 UW |
6287 | { |
6288 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6289 | return "br\t%0"; |
f314b9b1 | 6290 | else |
d40c829f | 6291 | return "b\t%a0"; |
10bbf137 | 6292 | } |
c7453384 | 6293 | [(set (attr "op_type") |
f314b9b1 UW |
6294 | (if_then_else (match_operand 0 "register_operand" "") |
6295 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6296 | (set_attr "type" "branch") |
6297 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
6298 | |
6299 | ; | |
f314b9b1 | 6300 | ; casesi instruction pattern(s). |
9db1d521 HP |
6301 | ; |
6302 | ||
f314b9b1 | 6303 | (define_insn "casesi_jump" |
d3632d41 | 6304 | [(set (pc) (match_operand 0 "address_operand" "U")) |
f314b9b1 | 6305 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 6306 | "" |
9db1d521 | 6307 | { |
f314b9b1 | 6308 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 6309 | return "br\t%0"; |
f314b9b1 | 6310 | else |
d40c829f | 6311 | return "b\t%a0"; |
10bbf137 | 6312 | } |
c7453384 | 6313 | [(set (attr "op_type") |
f314b9b1 UW |
6314 | (if_then_else (match_operand 0 "register_operand" "") |
6315 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6316 | (set_attr "type" "branch") |
6317 | (set_attr "atype" "agen")]) | |
9db1d521 | 6318 | |
f314b9b1 UW |
6319 | (define_expand "casesi" |
6320 | [(match_operand:SI 0 "general_operand" "") | |
6321 | (match_operand:SI 1 "general_operand" "") | |
6322 | (match_operand:SI 2 "general_operand" "") | |
6323 | (label_ref (match_operand 3 "" "")) | |
6324 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 6325 | "" |
f314b9b1 UW |
6326 | { |
6327 | rtx index = gen_reg_rtx (SImode); | |
6328 | rtx base = gen_reg_rtx (Pmode); | |
6329 | rtx target = gen_reg_rtx (Pmode); | |
6330 | ||
6331 | emit_move_insn (index, operands[0]); | |
6332 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
6333 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 6334 | operands[4]); |
f314b9b1 UW |
6335 | |
6336 | if (Pmode != SImode) | |
6337 | index = convert_to_mode (Pmode, index, 1); | |
6338 | if (GET_CODE (index) != REG) | |
6339 | index = copy_to_mode_reg (Pmode, index); | |
6340 | ||
6341 | if (TARGET_64BIT) | |
6342 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
6343 | else | |
a556fd39 | 6344 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 6345 | |
f314b9b1 UW |
6346 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
6347 | ||
542a8afa | 6348 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
6349 | emit_move_insn (target, index); |
6350 | ||
6351 | if (flag_pic) | |
6352 | target = gen_rtx_PLUS (Pmode, base, target); | |
6353 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
6354 | ||
6355 | DONE; | |
10bbf137 | 6356 | }) |
9db1d521 HP |
6357 | |
6358 | ||
6359 | ;; | |
6360 | ;;- Jump to subroutine. | |
6361 | ;; | |
6362 | ;; | |
6363 | ||
6364 | ; | |
6365 | ; untyped call instruction pattern(s). | |
6366 | ; | |
6367 | ||
6368 | ;; Call subroutine returning any type. | |
6369 | (define_expand "untyped_call" | |
6370 | [(parallel [(call (match_operand 0 "" "") | |
6371 | (const_int 0)) | |
6372 | (match_operand 1 "" "") | |
6373 | (match_operand 2 "" "")])] | |
6374 | "" | |
9db1d521 HP |
6375 | { |
6376 | int i; | |
6377 | ||
6378 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
6379 | ||
6380 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
6381 | { | |
6382 | rtx set = XVECEXP (operands[2], 0, i); | |
6383 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
6384 | } | |
6385 | ||
6386 | /* The optimizer does not know that the call sets the function value | |
6387 | registers we stored in the result block. We avoid problems by | |
6388 | claiming that all hard registers are used and clobbered at this | |
6389 | point. */ | |
6390 | emit_insn (gen_blockage ()); | |
6391 | ||
6392 | DONE; | |
10bbf137 | 6393 | }) |
9db1d521 HP |
6394 | |
6395 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
6396 | ;; all of memory. This blocks insns from being moved across this point. | |
6397 | ||
6398 | (define_insn "blockage" | |
10bbf137 | 6399 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 6400 | "" |
4023fb28 | 6401 | "" |
d5869ca0 UW |
6402 | [(set_attr "type" "none") |
6403 | (set_attr "length" "0")]) | |
4023fb28 | 6404 | |
9db1d521 | 6405 | ; |
ed9676cf | 6406 | ; sibcall patterns |
9db1d521 HP |
6407 | ; |
6408 | ||
ed9676cf | 6409 | (define_expand "sibcall" |
44b8152b | 6410 | [(call (match_operand 0 "" "") |
ed9676cf | 6411 | (match_operand 1 "" ""))] |
9db1d521 | 6412 | "" |
9db1d521 | 6413 | { |
ed9676cf AK |
6414 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
6415 | DONE; | |
6416 | }) | |
9db1d521 | 6417 | |
ed9676cf | 6418 | (define_insn "*sibcall_br" |
ae156f85 | 6419 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 6420 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 6421 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
6422 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
6423 | "br\t%%r1" | |
6424 | [(set_attr "op_type" "RR") | |
6425 | (set_attr "type" "branch") | |
6426 | (set_attr "atype" "agen")]) | |
9db1d521 | 6427 | |
ed9676cf AK |
6428 | (define_insn "*sibcall_brc" |
6429 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
6430 | (match_operand 1 "const_int_operand" "n"))] | |
6431 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
6432 | "j\t%0" | |
6433 | [(set_attr "op_type" "RI") | |
6434 | (set_attr "type" "branch")]) | |
9db1d521 | 6435 | |
ed9676cf AK |
6436 | (define_insn "*sibcall_brcl" |
6437 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
6438 | (match_operand 1 "const_int_operand" "n"))] | |
6439 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
6440 | "jg\t%0" | |
6441 | [(set_attr "op_type" "RIL") | |
6442 | (set_attr "type" "branch")]) | |
44b8152b | 6443 | |
ed9676cf AK |
6444 | ; |
6445 | ; sibcall_value patterns | |
6446 | ; | |
9e8327e3 | 6447 | |
ed9676cf AK |
6448 | (define_expand "sibcall_value" |
6449 | [(set (match_operand 0 "" "") | |
6450 | (call (match_operand 1 "" "") | |
6451 | (match_operand 2 "" "")))] | |
6452 | "" | |
6453 | { | |
6454 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 6455 | DONE; |
10bbf137 | 6456 | }) |
9db1d521 | 6457 | |
ed9676cf AK |
6458 | (define_insn "*sibcall_value_br" |
6459 | [(set (match_operand 0 "" "") | |
ae156f85 | 6460 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 6461 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 6462 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
6463 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
6464 | "br\t%%r1" | |
6465 | [(set_attr "op_type" "RR") | |
6466 | (set_attr "type" "branch") | |
6467 | (set_attr "atype" "agen")]) | |
6468 | ||
6469 | (define_insn "*sibcall_value_brc" | |
6470 | [(set (match_operand 0 "" "") | |
6471 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
6472 | (match_operand 2 "const_int_operand" "n")))] | |
6473 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
6474 | "j\t%1" | |
6475 | [(set_attr "op_type" "RI") | |
6476 | (set_attr "type" "branch")]) | |
6477 | ||
6478 | (define_insn "*sibcall_value_brcl" | |
6479 | [(set (match_operand 0 "" "") | |
6480 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
6481 | (match_operand 2 "const_int_operand" "n")))] | |
6482 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
6483 | "jg\t%1" | |
6484 | [(set_attr "op_type" "RIL") | |
6485 | (set_attr "type" "branch")]) | |
6486 | ||
6487 | ||
6488 | ; | |
6489 | ; call instruction pattern(s). | |
6490 | ; | |
6491 | ||
6492 | (define_expand "call" | |
6493 | [(call (match_operand 0 "" "") | |
6494 | (match_operand 1 "" "")) | |
6495 | (use (match_operand 2 "" ""))] | |
44b8152b | 6496 | "" |
ed9676cf | 6497 | { |
2f7e5a0d | 6498 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
6499 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
6500 | DONE; | |
6501 | }) | |
44b8152b | 6502 | |
9e8327e3 UW |
6503 | (define_insn "*bras" |
6504 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
6505 | (match_operand 1 "const_int_operand" "n")) | |
6506 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
6507 | "!SIBLING_CALL_P (insn) |
6508 | && TARGET_SMALL_EXEC | |
ed9676cf | 6509 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 6510 | "bras\t%2,%0" |
9db1d521 | 6511 | [(set_attr "op_type" "RI") |
4023fb28 | 6512 | (set_attr "type" "jsr")]) |
9db1d521 | 6513 | |
9e8327e3 UW |
6514 | (define_insn "*brasl" |
6515 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
6516 | (match_operand 1 "const_int_operand" "n")) | |
6517 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
6518 | "!SIBLING_CALL_P (insn) |
6519 | && TARGET_CPU_ZARCH | |
ed9676cf | 6520 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
6521 | "brasl\t%2,%0" |
6522 | [(set_attr "op_type" "RIL") | |
077dab3b | 6523 | (set_attr "type" "jsr")]) |
9db1d521 | 6524 | |
9e8327e3 UW |
6525 | (define_insn "*basr" |
6526 | [(call (mem:QI (match_operand 0 "address_operand" "U")) | |
6527 | (match_operand 1 "const_int_operand" "n")) | |
6528 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 6529 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
6530 | { |
6531 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
6532 | return "basr\t%2,%0"; | |
6533 | else | |
6534 | return "bas\t%2,%a0"; | |
6535 | } | |
6536 | [(set (attr "op_type") | |
6537 | (if_then_else (match_operand 0 "register_operand" "") | |
6538 | (const_string "RR") (const_string "RX"))) | |
6539 | (set_attr "type" "jsr") | |
6540 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
6541 | |
6542 | ; | |
6543 | ; call_value instruction pattern(s). | |
6544 | ; | |
6545 | ||
6546 | (define_expand "call_value" | |
44b8152b UW |
6547 | [(set (match_operand 0 "" "") |
6548 | (call (match_operand 1 "" "") | |
6549 | (match_operand 2 "" ""))) | |
6550 | (use (match_operand 3 "" ""))] | |
9db1d521 | 6551 | "" |
9db1d521 | 6552 | { |
2f7e5a0d | 6553 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 6554 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 6555 | DONE; |
10bbf137 | 6556 | }) |
9db1d521 | 6557 | |
9e8327e3 | 6558 | (define_insn "*bras_r" |
c19ec8f9 | 6559 | [(set (match_operand 0 "" "") |
9e8327e3 | 6560 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 6561 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 6562 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
6563 | "!SIBLING_CALL_P (insn) |
6564 | && TARGET_SMALL_EXEC | |
ed9676cf | 6565 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 6566 | "bras\t%3,%1" |
9db1d521 | 6567 | [(set_attr "op_type" "RI") |
f2d3c02a | 6568 | (set_attr "type" "jsr")]) |
9db1d521 | 6569 | |
9e8327e3 | 6570 | (define_insn "*brasl_r" |
c19ec8f9 | 6571 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
6572 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
6573 | (match_operand 2 "const_int_operand" "n"))) | |
6574 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
6575 | "!SIBLING_CALL_P (insn) |
6576 | && TARGET_CPU_ZARCH | |
ed9676cf | 6577 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
6578 | "brasl\t%3,%1" |
6579 | [(set_attr "op_type" "RIL") | |
077dab3b | 6580 | (set_attr "type" "jsr")]) |
9db1d521 | 6581 | |
9e8327e3 | 6582 | (define_insn "*basr_r" |
c19ec8f9 | 6583 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
6584 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
6585 | (match_operand 2 "const_int_operand" "n"))) | |
6586 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 6587 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
6588 | { |
6589 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
6590 | return "basr\t%3,%1"; | |
6591 | else | |
6592 | return "bas\t%3,%a1"; | |
6593 | } | |
6594 | [(set (attr "op_type") | |
6595 | (if_then_else (match_operand 1 "register_operand" "") | |
6596 | (const_string "RR") (const_string "RX"))) | |
6597 | (set_attr "type" "jsr") | |
6598 | (set_attr "atype" "agen")]) | |
9db1d521 | 6599 | |
fd3cd001 UW |
6600 | ;; |
6601 | ;;- Thread-local storage support. | |
6602 | ;; | |
6603 | ||
c5aa1d12 | 6604 | (define_expand "get_tp_64" |
ae156f85 | 6605 | [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))] |
fd3cd001 | 6606 | "TARGET_64BIT" |
c5aa1d12 | 6607 | "") |
fd3cd001 | 6608 | |
c5aa1d12 | 6609 | (define_expand "get_tp_31" |
ae156f85 | 6610 | [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))] |
fd3cd001 | 6611 | "!TARGET_64BIT" |
c5aa1d12 | 6612 | "") |
fd3cd001 | 6613 | |
c5aa1d12 | 6614 | (define_expand "set_tp_64" |
ae156f85 AS |
6615 | [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" "")) |
6616 | (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))] | |
fd3cd001 | 6617 | "TARGET_64BIT" |
c5aa1d12 | 6618 | "") |
fd3cd001 | 6619 | |
c5aa1d12 | 6620 | (define_expand "set_tp_31" |
ae156f85 AS |
6621 | [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" "")) |
6622 | (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))] | |
fd3cd001 | 6623 | "!TARGET_64BIT" |
c5aa1d12 UW |
6624 | "") |
6625 | ||
6626 | (define_insn "*set_tp" | |
ae156f85 | 6627 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
6628 | "" |
6629 | "" | |
6630 | [(set_attr "type" "none") | |
6631 | (set_attr "length" "0")]) | |
c7453384 | 6632 | |
fd3cd001 UW |
6633 | (define_insn "*tls_load_64" |
6634 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6635 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
6636 | (match_operand:DI 2 "" "")] | |
6637 | UNSPEC_TLS_LOAD))] | |
6638 | "TARGET_64BIT" | |
d40c829f | 6639 | "lg\t%0,%1%J2" |
fd3cd001 UW |
6640 | [(set_attr "op_type" "RXE")]) |
6641 | ||
6642 | (define_insn "*tls_load_31" | |
d3632d41 UW |
6643 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6644 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
6645 | (match_operand:SI 2 "" "")] |
6646 | UNSPEC_TLS_LOAD))] | |
6647 | "!TARGET_64BIT" | |
d3632d41 | 6648 | "@ |
d40c829f UW |
6649 | l\t%0,%1%J2 |
6650 | ly\t%0,%1%J2" | |
d3632d41 | 6651 | [(set_attr "op_type" "RX,RXY")]) |
fd3cd001 | 6652 | |
9e8327e3 | 6653 | (define_insn "*bras_tls" |
c19ec8f9 | 6654 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
6655 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
6656 | (match_operand 2 "const_int_operand" "n"))) | |
6657 | (clobber (match_operand 3 "register_operand" "=r")) | |
6658 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
6659 | "!SIBLING_CALL_P (insn) |
6660 | && TARGET_SMALL_EXEC | |
ed9676cf | 6661 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 6662 | "bras\t%3,%1%J4" |
fd3cd001 UW |
6663 | [(set_attr "op_type" "RI") |
6664 | (set_attr "type" "jsr")]) | |
6665 | ||
9e8327e3 | 6666 | (define_insn "*brasl_tls" |
c19ec8f9 | 6667 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
6668 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
6669 | (match_operand 2 "const_int_operand" "n"))) | |
6670 | (clobber (match_operand 3 "register_operand" "=r")) | |
6671 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
6672 | "!SIBLING_CALL_P (insn) |
6673 | && TARGET_CPU_ZARCH | |
ed9676cf | 6674 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
6675 | "brasl\t%3,%1%J4" |
6676 | [(set_attr "op_type" "RIL") | |
fd3cd001 UW |
6677 | (set_attr "type" "jsr")]) |
6678 | ||
9e8327e3 | 6679 | (define_insn "*basr_tls" |
c19ec8f9 | 6680 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
6681 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
6682 | (match_operand 2 "const_int_operand" "n"))) | |
6683 | (clobber (match_operand 3 "register_operand" "=r")) | |
6684 | (use (match_operand 4 "" ""))] | |
ed9676cf | 6685 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
6686 | { |
6687 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
6688 | return "basr\t%3,%1%J4"; | |
6689 | else | |
6690 | return "bas\t%3,%a1%J4"; | |
6691 | } | |
6692 | [(set (attr "op_type") | |
6693 | (if_then_else (match_operand 1 "register_operand" "") | |
6694 | (const_string "RR") (const_string "RX"))) | |
6695 | (set_attr "type" "jsr") | |
6696 | (set_attr "atype" "agen")]) | |
fd3cd001 | 6697 | |
e0374221 AS |
6698 | ;; |
6699 | ;;- Atomic operations | |
6700 | ;; | |
6701 | ||
6702 | ; | |
6703 | ; memory barrier pattern. | |
6704 | ; | |
6705 | ||
6706 | (define_expand "memory_barrier" | |
6707 | [(set (mem:BLK (match_dup 0)) | |
6708 | (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))] | |
6709 | "" | |
6710 | { | |
6711 | operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode)); | |
6712 | MEM_VOLATILE_P (operands[0]) = 1; | |
6713 | }) | |
6714 | ||
6715 | (define_insn "*memory_barrier" | |
6716 | [(set (match_operand:BLK 0 "" "") | |
6717 | (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))] | |
6718 | "" | |
6719 | "bcr\t15,0" | |
6720 | [(set_attr "op_type" "RR")]) | |
6721 | ||
6722 | ; | |
6723 | ; compare and swap patterns. | |
6724 | ; | |
6725 | ||
6726 | (define_insn "sync_compare_and_swap<mode>" | |
6727 | [(set (match_operand:GPR 0 "register_operand" "=r") | |
6728 | (match_operand:GPR 1 "memory_operand" "+Q")) | |
6729 | (set (match_dup 1) | |
6730 | (unspec_volatile:GPR | |
6731 | [(match_dup 1) | |
6732 | (match_operand:GPR 2 "register_operand" "0") | |
6733 | (match_operand:GPR 3 "register_operand" "r")] | |
6734 | UNSPECV_CAS)) | |
6735 | (clobber (reg:CC CC_REGNUM))] | |
6736 | "" | |
6737 | "cs<g>\t%0,%3,%S1" | |
6738 | [(set_attr "op_type" "RS<E>") | |
6739 | (set_attr "type" "sem")]) | |
6740 | ||
6741 | (define_expand "sync_compare_and_swap_cc<mode>" | |
6742 | [(parallel | |
6743 | [(set (match_operand:GPR 0 "register_operand" "") | |
6744 | (match_operand:GPR 1 "memory_operand" "")) | |
6745 | (set (match_dup 1) | |
6746 | (unspec_volatile:GPR | |
6747 | [(match_dup 1) | |
6748 | (match_operand:GPR 2 "register_operand" "") | |
6749 | (match_operand:GPR 3 "register_operand" "")] | |
6750 | UNSPECV_CAS)) | |
6751 | (set (match_dup 4) | |
6752 | (compare:CCZ (match_dup 1) (match_dup 2)))])] | |
6753 | "" | |
6754 | { | |
6755 | operands[4] = gen_rtx_REG (CCZmode, CC_REGNUM); | |
6756 | s390_compare_op0 = operands[1]; | |
6757 | s390_compare_op1 = operands[2]; | |
6758 | s390_compare_emitted = operands[4]; | |
6759 | }) | |
6760 | ||
6761 | (define_insn "*sync_compare_and_swap_cc<mode>" | |
6762 | [(set (match_operand:GPR 0 "register_operand" "=r") | |
6763 | (match_operand:GPR 1 "memory_operand" "+Q")) | |
6764 | (set (match_dup 1) | |
6765 | (unspec_volatile:GPR | |
6766 | [(match_dup 1) | |
6767 | (match_operand:GPR 2 "register_operand" "0") | |
6768 | (match_operand:GPR 3 "register_operand" "r")] | |
6769 | UNSPECV_CAS)) | |
6770 | (set (reg:CCZ CC_REGNUM) | |
6771 | (compare:CCZ (match_dup 1) (match_dup 2)))] | |
6772 | "" | |
6773 | "cs<g>\t%0,%3,%S1" | |
6774 | [(set_attr "op_type" "RS<E>") | |
6775 | (set_attr "type" "sem")]) | |
6776 | ||
6777 | ||
9db1d521 HP |
6778 | ;; |
6779 | ;;- Miscellaneous instructions. | |
6780 | ;; | |
6781 | ||
6782 | ; | |
6783 | ; allocate stack instruction pattern(s). | |
6784 | ; | |
6785 | ||
6786 | (define_expand "allocate_stack" | |
ef44a6ff UW |
6787 | [(match_operand 0 "general_operand" "") |
6788 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 6789 | "TARGET_BACKCHAIN" |
9db1d521 | 6790 | { |
ef44a6ff | 6791 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 6792 | |
ef44a6ff UW |
6793 | emit_move_insn (temp, s390_back_chain_rtx ()); |
6794 | anti_adjust_stack (operands[1]); | |
6795 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 6796 | |
ef44a6ff UW |
6797 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
6798 | DONE; | |
10bbf137 | 6799 | }) |
9db1d521 HP |
6800 | |
6801 | ||
6802 | ; | |
43ab026f | 6803 | ; setjmp instruction pattern. |
9db1d521 HP |
6804 | ; |
6805 | ||
9db1d521 | 6806 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 6807 | [(match_operand 0 "" "")] |
f314b9b1 | 6808 | "flag_pic" |
9db1d521 | 6809 | { |
585539a1 | 6810 | emit_insn (s390_load_got ()); |
fd7643fb | 6811 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); |
9db1d521 | 6812 | DONE; |
fd7643fb | 6813 | }) |
9db1d521 | 6814 | |
9db1d521 HP |
6815 | ;; These patterns say how to save and restore the stack pointer. We need not |
6816 | ;; save the stack pointer at function level since we are careful to | |
6817 | ;; preserve the backchain. At block level, we have to restore the backchain | |
6818 | ;; when we restore the stack pointer. | |
6819 | ;; | |
6820 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
6821 | ;; backchain and restore both. Note that in the nonlocal case, the | |
6822 | ;; save area is a memory location. | |
6823 | ||
6824 | (define_expand "save_stack_function" | |
6825 | [(match_operand 0 "general_operand" "") | |
6826 | (match_operand 1 "general_operand" "")] | |
6827 | "" | |
6828 | "DONE;") | |
6829 | ||
6830 | (define_expand "restore_stack_function" | |
6831 | [(match_operand 0 "general_operand" "") | |
6832 | (match_operand 1 "general_operand" "")] | |
6833 | "" | |
6834 | "DONE;") | |
6835 | ||
6836 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
6837 | [(match_operand 0 "register_operand" "") |
6838 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 6839 | "TARGET_BACKCHAIN" |
9db1d521 | 6840 | { |
ef44a6ff UW |
6841 | rtx temp = gen_reg_rtx (Pmode); |
6842 | ||
6843 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
6844 | emit_move_insn (operands[0], operands[1]); | |
6845 | emit_move_insn (s390_back_chain_rtx (), temp); | |
6846 | ||
6847 | DONE; | |
10bbf137 | 6848 | }) |
9db1d521 HP |
6849 | |
6850 | (define_expand "save_stack_nonlocal" | |
6851 | [(match_operand 0 "memory_operand" "") | |
6852 | (match_operand 1 "register_operand" "")] | |
6853 | "" | |
9db1d521 | 6854 | { |
ef44a6ff UW |
6855 | enum machine_mode mode = TARGET_64BIT ? OImode : TImode; |
6856 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); | |
6857 | ||
6858 | /* Copy the backchain to the first word, sp to the second and the | |
6859 | literal pool base to the third. */ | |
6860 | ||
b3d31392 | 6861 | if (TARGET_BACKCHAIN) |
ef44a6ff UW |
6862 | { |
6863 | rtx temp = force_reg (Pmode, s390_back_chain_rtx ()); | |
6864 | emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp); | |
6865 | } | |
6866 | ||
6867 | emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]); | |
6868 | emit_move_insn (operand_subword (operands[0], 2, 0, mode), base); | |
9db1d521 | 6869 | |
9db1d521 | 6870 | DONE; |
10bbf137 | 6871 | }) |
9db1d521 HP |
6872 | |
6873 | (define_expand "restore_stack_nonlocal" | |
6874 | [(match_operand 0 "register_operand" "") | |
6875 | (match_operand 1 "memory_operand" "")] | |
6876 | "" | |
9db1d521 | 6877 | { |
ef44a6ff | 6878 | enum machine_mode mode = TARGET_64BIT ? OImode : TImode; |
490ceeb4 | 6879 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 6880 | rtx temp = NULL_RTX; |
9db1d521 | 6881 | |
43ab026f | 6882 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 6883 | literal pool base from the third. */ |
43ab026f | 6884 | |
b3d31392 | 6885 | if (TARGET_BACKCHAIN) |
ef44a6ff UW |
6886 | temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode)); |
6887 | ||
6888 | emit_move_insn (base, operand_subword (operands[1], 2, 0, mode)); | |
6889 | emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode)); | |
6890 | ||
6891 | if (temp) | |
6892 | emit_move_insn (s390_back_chain_rtx (), temp); | |
6893 | ||
6894 | emit_insn (gen_rtx_USE (VOIDmode, base)); | |
9db1d521 | 6895 | DONE; |
10bbf137 | 6896 | }) |
9db1d521 | 6897 | |
7bcebb25 AK |
6898 | (define_expand "exception_receiver" |
6899 | [(const_int 0)] | |
6900 | "" | |
6901 | { | |
6902 | s390_set_has_landing_pad_p (true); | |
6903 | DONE; | |
6904 | }) | |
9db1d521 HP |
6905 | |
6906 | ; | |
6907 | ; nop instruction pattern(s). | |
6908 | ; | |
6909 | ||
6910 | (define_insn "nop" | |
6911 | [(const_int 0)] | |
6912 | "" | |
d40c829f | 6913 | "lr\t0,0" |
9db1d521 HP |
6914 | [(set_attr "op_type" "RR")]) |
6915 | ||
6916 | ||
6917 | ; | |
6918 | ; Special literal pool access instruction pattern(s). | |
6919 | ; | |
6920 | ||
416cf582 UW |
6921 | (define_insn "*pool_entry" |
6922 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
6923 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 6924 | "" |
9db1d521 | 6925 | { |
416cf582 UW |
6926 | enum machine_mode mode = GET_MODE (PATTERN (insn)); |
6927 | unsigned int align = GET_MODE_BITSIZE (mode); | |
faeb9bb6 | 6928 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
6929 | return ""; |
6930 | } | |
b628bd8e | 6931 | [(set (attr "length") |
416cf582 | 6932 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 6933 | |
9bb86f41 UW |
6934 | (define_insn "pool_align" |
6935 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
6936 | UNSPECV_POOL_ALIGN)] | |
6937 | "" | |
6938 | ".align\t%0" | |
b628bd8e | 6939 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 6940 | |
9bb86f41 UW |
6941 | (define_insn "pool_section_start" |
6942 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
6943 | "" | |
6944 | ".section\t.rodata" | |
b628bd8e | 6945 | [(set_attr "length" "0")]) |
b2ccb744 | 6946 | |
9bb86f41 UW |
6947 | (define_insn "pool_section_end" |
6948 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
6949 | "" | |
b2ccb744 | 6950 | ".previous" |
b628bd8e | 6951 | [(set_attr "length" "0")]) |
b2ccb744 | 6952 | |
5af2f3d3 | 6953 | (define_insn "main_base_31_small" |
9e8327e3 UW |
6954 | [(set (match_operand 0 "register_operand" "=a") |
6955 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
6956 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
6957 | "basr\t%0,0" |
6958 | [(set_attr "op_type" "RR") | |
6959 | (set_attr "type" "la")]) | |
6960 | ||
6961 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
6962 | [(set (match_operand 0 "register_operand" "=a") |
6963 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 6964 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 6965 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 UW |
6966 | "bras\t%0,%2" |
6967 | [(set_attr "op_type" "RI")]) | |
6968 | ||
6969 | (define_insn "main_base_64" | |
9e8327e3 UW |
6970 | [(set (match_operand 0 "register_operand" "=a") |
6971 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
6972 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
6973 | "larl\t%0,%1" |
6974 | [(set_attr "op_type" "RIL") | |
6975 | (set_attr "type" "larl")]) | |
6976 | ||
6977 | (define_insn "main_pool" | |
585539a1 UW |
6978 | [(set (match_operand 0 "register_operand" "=a") |
6979 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
6980 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
6981 | { |
6982 | gcc_unreachable (); | |
6983 | } | |
b628bd8e | 6984 | [(set (attr "type") |
ea77e738 UW |
6985 | (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) |
6986 | (const_string "larl") (const_string "la")))]) | |
5af2f3d3 | 6987 | |
aee4e0db | 6988 | (define_insn "reload_base_31" |
9e8327e3 UW |
6989 | [(set (match_operand 0 "register_operand" "=a") |
6990 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
6991 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 6992 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e UW |
6993 | [(set_attr "length" "6") |
6994 | (set_attr "type" "la")]) | |
b2ccb744 | 6995 | |
aee4e0db | 6996 | (define_insn "reload_base_64" |
9e8327e3 UW |
6997 | [(set (match_operand 0 "register_operand" "=a") |
6998 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
6999 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7000 | "larl\t%0,%1" |
aee4e0db | 7001 | [(set_attr "op_type" "RIL") |
077dab3b | 7002 | (set_attr "type" "larl")]) |
aee4e0db | 7003 | |
aee4e0db | 7004 | (define_insn "pool" |
fd7643fb | 7005 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 7006 | "" |
8d933e31 AS |
7007 | { |
7008 | gcc_unreachable (); | |
7009 | } | |
b628bd8e | 7010 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 7011 | |
4023fb28 UW |
7012 | ;; |
7013 | ;; Insns related to generating the function prologue and epilogue. | |
7014 | ;; | |
7015 | ||
7016 | ||
7017 | (define_expand "prologue" | |
7018 | [(use (const_int 0))] | |
7019 | "" | |
10bbf137 | 7020 | "s390_emit_prologue (); DONE;") |
4023fb28 | 7021 | |
2f7e5a0d EC |
7022 | (define_insn "prologue_tpf" |
7023 | [(unspec_volatile [(const_int 0)] UNSPECV_TPF_PROLOGUE) | |
7024 | (clobber (reg:DI 1))] | |
3839e36a | 7025 | "TARGET_TPF_PROFILING" |
9e811ecd JT |
7026 | "larl\t%%r1,.+14\;tm\t4065,255\;bnz\t4064" |
7027 | [(set_attr "length" "14")]) | |
2f7e5a0d | 7028 | |
4023fb28 UW |
7029 | (define_expand "epilogue" |
7030 | [(use (const_int 1))] | |
7031 | "" | |
ed9676cf AK |
7032 | "s390_emit_epilogue (false); DONE;") |
7033 | ||
2f7e5a0d EC |
7034 | (define_insn "epilogue_tpf" |
7035 | [(unspec_volatile [(const_int 0)] UNSPECV_TPF_EPILOGUE) | |
7036 | (clobber (reg:DI 1))] | |
3839e36a | 7037 | "TARGET_TPF_PROFILING" |
9e811ecd JT |
7038 | "larl\t%%r1,.+14\;tm\t4071,255\;bnz\t4070" |
7039 | [(set_attr "length" "14")]) | |
2f7e5a0d | 7040 | |
ed9676cf AK |
7041 | (define_expand "sibcall_epilogue" |
7042 | [(use (const_int 0))] | |
7043 | "" | |
7044 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 7045 | |
9e8327e3 | 7046 | (define_insn "*return" |
4023fb28 | 7047 | [(return) |
9e8327e3 UW |
7048 | (use (match_operand 0 "register_operand" "a"))] |
7049 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7050 | "br\t%0" |
4023fb28 | 7051 | [(set_attr "op_type" "RR") |
c7453384 | 7052 | (set_attr "type" "jsr") |
077dab3b | 7053 | (set_attr "atype" "agen")]) |
4023fb28 | 7054 | |
4023fb28 | 7055 | |
c7453384 | 7056 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 7057 | ;; pointer. This is used for compatibility. |
c7453384 EC |
7058 | |
7059 | (define_expand "ptr_extend" | |
7060 | [(set (match_operand:DI 0 "register_operand" "=r") | |
7061 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 7062 | "TARGET_64BIT" |
c7453384 | 7063 | { |
c7453384 EC |
7064 | emit_insn (gen_anddi3 (operands[0], |
7065 | gen_lowpart (DImode, operands[1]), | |
7066 | GEN_INT (0x7fffffff))); | |
c7453384 | 7067 | DONE; |
10bbf137 | 7068 | }) |
4798630c D |
7069 | |
7070 | ;; Instruction definition to expand eh_return macro to support | |
7071 | ;; swapping in special linkage return addresses. | |
7072 | ||
7073 | (define_expand "eh_return" | |
7074 | [(use (match_operand 0 "register_operand" ""))] | |
7075 | "TARGET_TPF" | |
7076 | { | |
7077 | s390_emit_tpf_eh_return (operands[0]); | |
7078 | DONE; | |
7079 | }) | |
7080 |