]>
Commit | Line | Data |
---|---|---|
9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
9c3c3dcc | 2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005 |
283334f0 | 3 | ;; Free Software Foundation, Inc. |
9db1d521 | 4 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
f314b9b1 | 5 | ;; Ulrich Weigand (uweigand@de.ibm.com). |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
11 | ;; Software Foundation; either version 2, or (at your option) any later | |
12 | ;; version. | |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
58add37a UW |
20 | ;; along with GCC; see the file COPYING. If not, write to the Free |
21 | ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
22 | ;; 02111-1307, USA. | |
9db1d521 HP |
23 | |
24 | ;; | |
25 | ;; Special constraints for s/390 machine description: | |
26 | ;; | |
27 | ;; a -- Any address register from 1 to 15. | |
9dc62c00 | 28 | ;; c -- Condition code register 33. |
9db1d521 HP |
29 | ;; d -- Any register from 0 to 15. |
30 | ;; I -- An 8-bit constant (0..255). | |
31 | ;; J -- A 12-bit constant (0..4095). | |
32 | ;; K -- A 16-bit constant (-32768..32767). | |
2f7e5a0d | 33 | ;; L -- Value appropriate as displacement. |
f19a9af7 AK |
34 | ;; (0..4095) for short displacement |
35 | ;; (-524288..524287) for long displacement | |
36 | ;; M -- Constant integer with a value of 0x7fffffff. | |
37 | ;; N -- Multiple letter constraint followed by 4 parameter letters. | |
0dfa6c5e UW |
38 | ;; 0..9,x: number of the part counting from most to least significant |
39 | ;; H,Q: mode of the part | |
40 | ;; D,S,H: mode of the containing operand | |
41 | ;; 0,F: value of the other parts (F - all bits set) | |
2f7e5a0d | 42 | ;; |
f19a9af7 | 43 | ;; The constraint matches if the specified part of a constant |
0dfa6c5e UW |
44 | ;; has a value different from its other parts. If the letter x |
45 | ;; is specified instead of a part number, the constraint matches | |
46 | ;; if there is any single part with non-default value. | |
f19a9af7 AK |
47 | ;; Q -- Memory reference without index register and with short displacement. |
48 | ;; R -- Memory reference with index register and short displacement. | |
49 | ;; S -- Memory reference without index register but with long displacement. | |
50 | ;; T -- Memory reference with index register and long displacement. | |
0dfa6c5e UW |
51 | ;; A -- Multiple letter constraint followed by Q, R, S, or T: |
52 | ;; Offsettable memory reference of type specified by second letter. | |
e221ef54 UW |
53 | ;; B -- Multiple letter constraint followed by Q, R, S, or T: |
54 | ;; Memory reference of the type specified by second letter that | |
55 | ;; does *not* refer to a literal pool entry. | |
f19a9af7 AK |
56 | ;; U -- Pointer with short displacement. |
57 | ;; W -- Pointer with long displacement. | |
58 | ;; Y -- Shift count operand. | |
9db1d521 HP |
59 | ;; |
60 | ;; Special formats used for outputting 390 instructions. | |
61 | ;; | |
f19a9af7 AK |
62 | ;; %C: print opcode suffix for branch condition. |
63 | ;; %D: print opcode suffix for inverse branch condition. | |
64 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
65 | ;; %O: print only the displacement of a memory reference. | |
66 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 67 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
68 | ;; %N: print the second word of a DImode operand. |
69 | ;; %M: print the second word of a TImode operand. | |
70 | ||
71 | ;; %b: print integer X as if it's an unsigned byte. | |
72 | ;; %x: print integer X as if it's an unsigned word. | |
73 | ;; %h: print integer X as if it's a signed word. | |
74 | ;; %i: print the first nonzero HImode part of X | |
75 | ;; %j: print the first HImode part unequal to 0xffff of X | |
76 | ||
9db1d521 HP |
77 | ;; |
78 | ;; We have a special constraint for pattern matching. | |
79 | ;; | |
80 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
81 | ;; | |
9db1d521 | 82 | |
fd3cd001 UW |
83 | ;; |
84 | ;; UNSPEC usage | |
85 | ;; | |
86 | ||
87 | (define_constants | |
10bbf137 UW |
88 | [; Miscellaneous |
89 | (UNSPEC_ROUND 1) | |
5b022de5 | 90 | (UNSPEC_CMPINT 2) |
10bbf137 UW |
91 | (UNSPEC_SETHIGH 10) |
92 | ||
93 | ; GOT/PLT and lt-relative accesses | |
fd7643fb UW |
94 | (UNSPEC_LTREL_OFFSET 100) |
95 | (UNSPEC_LTREL_BASE 101) | |
96 | (UNSPEC_GOTENT 110) | |
97 | (UNSPEC_GOT 111) | |
98 | (UNSPEC_GOTOFF 112) | |
99 | (UNSPEC_PLT 113) | |
100 | (UNSPEC_PLTOFF 114) | |
101 | ||
102 | ; Literal pool | |
103 | (UNSPEC_RELOAD_BASE 210) | |
5af2f3d3 | 104 | (UNSPEC_MAIN_BASE 211) |
585539a1 | 105 | (UNSPEC_LTREF 212) |
9bb86f41 UW |
106 | (UNSPEC_INSN 213) |
107 | (UNSPEC_EXECUTE 214) | |
fd7643fb UW |
108 | |
109 | ; TLS relocation specifiers | |
fd3cd001 UW |
110 | (UNSPEC_TLSGD 500) |
111 | (UNSPEC_TLSLDM 501) | |
112 | (UNSPEC_NTPOFF 502) | |
113 | (UNSPEC_DTPOFF 503) | |
114 | (UNSPEC_GOTNTPOFF 504) | |
115 | (UNSPEC_INDNTPOFF 505) | |
116 | ||
117 | ; TLS support | |
fd3cd001 UW |
118 | (UNSPEC_TLSLDM_NTPOFF 511) |
119 | (UNSPEC_TLS_LOAD 512) | |
91d39d71 UW |
120 | |
121 | ; String Functions | |
122 | (UNSPEC_SRST 600) | |
fd3cd001 UW |
123 | ]) |
124 | ||
125 | ;; | |
126 | ;; UNSPEC_VOLATILE usage | |
127 | ;; | |
128 | ||
129 | (define_constants | |
10bbf137 UW |
130 | [; Blockage |
131 | (UNSPECV_BLOCKAGE 0) | |
132 | ||
2f7e5a0d EC |
133 | ; TPF Support |
134 | (UNSPECV_TPF_PROLOGUE 20) | |
135 | (UNSPECV_TPF_EPILOGUE 21) | |
136 | ||
10bbf137 | 137 | ; Literal pool |
fd7643fb | 138 | (UNSPECV_POOL 200) |
9bb86f41 UW |
139 | (UNSPECV_POOL_SECTION 201) |
140 | (UNSPECV_POOL_ALIGN 202) | |
416cf582 | 141 | (UNSPECV_POOL_ENTRY 203) |
fd7643fb UW |
142 | (UNSPECV_MAIN_POOL 300) |
143 | ||
144 | ; TLS support | |
fd3cd001 UW |
145 | (UNSPECV_SET_TP 500) |
146 | ]) | |
147 | ||
148 | ||
29a74354 UW |
149 | ;; Instruction operand type as used in the Principles of Operation. |
150 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 151 | |
29a74354 UW |
152 | (define_attr "op_type" |
153 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY" | |
b628bd8e | 154 | (const_string "NN")) |
9db1d521 | 155 | |
29a74354 | 156 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 157 | |
077dab3b HP |
158 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
159 | cs,vs,store,imul,idiv, | |
160 | branch,jsr,fsimpd,fsimps, | |
161 | floadd,floads,fstored, fstores, | |
162 | fmuld,fmuls,fdivd,fdivs, | |
163 | ftoi,itof,fsqrtd,fsqrts, | |
a036c6f7 | 164 | other" |
29a74354 UW |
165 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
166 | (eq_attr "op_type" "SS") (const_string "cs")] | |
167 | (const_string "integer"))) | |
9db1d521 | 168 | |
29a74354 UW |
169 | ;; Another attribute used for scheduling purposes: |
170 | ;; agen: Instruction uses the address generation unit | |
171 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
172 | |
173 | (define_attr "atype" "agen,reg" | |
b628bd8e | 174 | (cond [(eq_attr "op_type" "E") (const_string "reg") |
077dab3b HP |
175 | (eq_attr "op_type" "RR") (const_string "reg") |
176 | (eq_attr "op_type" "RX") (const_string "agen") | |
177 | (eq_attr "op_type" "RI") (const_string "reg") | |
178 | (eq_attr "op_type" "RRE") (const_string "reg") | |
179 | (eq_attr "op_type" "RS") (const_string "agen") | |
180 | (eq_attr "op_type" "RSI") (const_string "agen") | |
181 | (eq_attr "op_type" "S") (const_string "agen") | |
182 | (eq_attr "op_type" "SI") (const_string "agen") | |
183 | (eq_attr "op_type" "SS") (const_string "agen") | |
184 | (eq_attr "op_type" "SSE") (const_string "agen") | |
185 | (eq_attr "op_type" "RXE") (const_string "agen") | |
186 | (eq_attr "op_type" "RSE") (const_string "agen") | |
d3632d41 UW |
187 | (eq_attr "op_type" "RIL") (const_string "agen") |
188 | (eq_attr "op_type" "RXY") (const_string "agen") | |
189 | (eq_attr "op_type" "RSY") (const_string "agen") | |
190 | (eq_attr "op_type" "SIY") (const_string "agen")] | |
b628bd8e | 191 | (const_string "agen"))) |
9db1d521 | 192 | |
9db1d521 HP |
193 | ;; Length in bytes. |
194 | ||
195 | (define_attr "length" "" | |
b628bd8e | 196 | (cond [(eq_attr "op_type" "E") (const_int 2) |
9db1d521 HP |
197 | (eq_attr "op_type" "RR") (const_int 2) |
198 | (eq_attr "op_type" "RX") (const_int 4) | |
199 | (eq_attr "op_type" "RI") (const_int 4) | |
200 | (eq_attr "op_type" "RRE") (const_int 4) | |
201 | (eq_attr "op_type" "RS") (const_int 4) | |
202 | (eq_attr "op_type" "RSI") (const_int 4) | |
9db1d521 HP |
203 | (eq_attr "op_type" "S") (const_int 4) |
204 | (eq_attr "op_type" "SI") (const_int 4) | |
205 | (eq_attr "op_type" "SS") (const_int 6) | |
206 | (eq_attr "op_type" "SSE") (const_int 6) | |
207 | (eq_attr "op_type" "RXE") (const_int 6) | |
208 | (eq_attr "op_type" "RSE") (const_int 6) | |
d3632d41 UW |
209 | (eq_attr "op_type" "RIL") (const_int 6) |
210 | (eq_attr "op_type" "RXY") (const_int 6) | |
211 | (eq_attr "op_type" "RSY") (const_int 6) | |
212 | (eq_attr "op_type" "SIY") (const_int 6)] | |
b628bd8e | 213 | (const_int 6))) |
9db1d521 | 214 | |
29a74354 UW |
215 | |
216 | ;; Processor type. This attribute must exactly match the processor_type | |
217 | ;; enumeration in s390.h. The current machine description does not | |
218 | ;; distinguish between g5 and g6, but there are differences between the two | |
219 | ;; CPUs could in theory be modeled. | |
220 | ||
221 | (define_attr "cpu" "g5,g6,z900,z990" | |
222 | (const (symbol_ref "s390_tune"))) | |
223 | ||
224 | ;; Pipeline description for z900. For lack of anything better, | |
225 | ;; this description is also used for the g5 and g6. | |
226 | (include "2064.md") | |
227 | ||
228 | ;; Pipeline description for z990. | |
229 | (include "2084.md") | |
230 | ||
9db1d521 HP |
231 | ;; |
232 | ;;- Compare instructions. | |
233 | ;; | |
234 | ||
235 | (define_expand "cmpdi" | |
236 | [(set (reg:CC 33) | |
237 | (compare:CC (match_operand:DI 0 "register_operand" "") | |
238 | (match_operand:DI 1 "general_operand" "")))] | |
239 | "TARGET_64BIT" | |
9db1d521 HP |
240 | { |
241 | s390_compare_op0 = operands[0]; | |
242 | s390_compare_op1 = operands[1]; | |
243 | DONE; | |
10bbf137 | 244 | }) |
9db1d521 HP |
245 | |
246 | (define_expand "cmpsi" | |
247 | [(set (reg:CC 33) | |
248 | (compare:CC (match_operand:SI 0 "register_operand" "") | |
249 | (match_operand:SI 1 "general_operand" "")))] | |
250 | "" | |
9db1d521 HP |
251 | { |
252 | s390_compare_op0 = operands[0]; | |
253 | s390_compare_op1 = operands[1]; | |
254 | DONE; | |
10bbf137 | 255 | }) |
9db1d521 | 256 | |
9db1d521 HP |
257 | (define_expand "cmpdf" |
258 | [(set (reg:CC 33) | |
259 | (compare:CC (match_operand:DF 0 "register_operand" "") | |
260 | (match_operand:DF 1 "general_operand" "")))] | |
261 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
262 | { |
263 | s390_compare_op0 = operands[0]; | |
264 | s390_compare_op1 = operands[1]; | |
265 | DONE; | |
10bbf137 | 266 | }) |
9db1d521 HP |
267 | |
268 | (define_expand "cmpsf" | |
269 | [(set (reg:CC 33) | |
270 | (compare:CC (match_operand:SF 0 "register_operand" "") | |
271 | (match_operand:SF 1 "general_operand" "")))] | |
272 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
273 | { |
274 | s390_compare_op0 = operands[0]; | |
275 | s390_compare_op1 = operands[1]; | |
276 | DONE; | |
10bbf137 | 277 | }) |
9db1d521 HP |
278 | |
279 | ||
07893d4f | 280 | ; Test-under-Mask instructions |
9db1d521 | 281 | |
07893d4f | 282 | (define_insn "*tmqi_mem" |
9db1d521 | 283 | [(set (reg 33) |
68f9c5e2 UW |
284 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
285 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
286 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
07893d4f | 287 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))" |
d3632d41 | 288 | "@ |
fc0ea003 UW |
289 | tm\t%S0,%b1 |
290 | tmy\t%S0,%b1" | |
d3632d41 | 291 | [(set_attr "op_type" "SI,SIY")]) |
9db1d521 | 292 | |
05b9aaaa UW |
293 | (define_insn "*tmdi_reg" |
294 | [(set (reg 33) | |
f19a9af7 | 295 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 296 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
297 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
298 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
05b9aaaa UW |
299 | "TARGET_64BIT |
300 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) | |
f19a9af7 AK |
301 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
302 | "@ | |
303 | tmhh\t%0,%i1 | |
304 | tmhl\t%0,%i1 | |
305 | tmlh\t%0,%i1 | |
306 | tmll\t%0,%i1" | |
05b9aaaa UW |
307 | [(set_attr "op_type" "RI")]) |
308 | ||
309 | (define_insn "*tmsi_reg" | |
310 | [(set (reg 33) | |
f19a9af7 AK |
311 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
312 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
313 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
05b9aaaa | 314 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) |
f19a9af7 AK |
315 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
316 | "@ | |
317 | tmh\t%0,%i1 | |
318 | tml\t%0,%i1" | |
05b9aaaa UW |
319 | [(set_attr "op_type" "RI")]) |
320 | ||
07893d4f | 321 | (define_insn "*tmhi_full" |
9db1d521 | 322 | [(set (reg 33) |
07893d4f UW |
323 | (compare (match_operand:HI 0 "register_operand" "d") |
324 | (match_operand:HI 1 "immediate_operand" "n")))] | |
a556fd39 | 325 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))" |
d40c829f | 326 | "tml\t%0,65535" |
fc0ea003 | 327 | [(set_attr "op_type" "RI")]) |
9db1d521 | 328 | |
07893d4f | 329 | (define_insn "*tmqi_full" |
9db1d521 | 330 | [(set (reg 33) |
07893d4f UW |
331 | (compare (match_operand:QI 0 "register_operand" "d") |
332 | (match_operand:QI 1 "immediate_operand" "n")))] | |
a556fd39 | 333 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))" |
d40c829f | 334 | "tml\t%0,255" |
07893d4f | 335 | [(set_attr "op_type" "RI")]) |
9db1d521 | 336 | |
07893d4f UW |
337 | |
338 | ; Load-and-Test instructions | |
339 | ||
340 | (define_insn "*tstdi_sign" | |
9db1d521 | 341 | [(set (reg 33) |
07893d4f UW |
342 | (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0) |
343 | (const_int 32)) (const_int 32)) | |
344 | (match_operand:DI 1 "const0_operand" ""))) | |
345 | (set (match_operand:DI 2 "register_operand" "=d") | |
346 | (sign_extend:DI (match_dup 0)))] | |
347 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 348 | "ltgfr\t%2,%0" |
07893d4f UW |
349 | [(set_attr "op_type" "RRE")]) |
350 | ||
351 | (define_insn "*tstdi" | |
9db1d521 | 352 | [(set (reg 33) |
07893d4f UW |
353 | (compare (match_operand:DI 0 "register_operand" "d") |
354 | (match_operand:DI 1 "const0_operand" ""))) | |
355 | (set (match_operand:DI 2 "register_operand" "=d") | |
356 | (match_dup 0))] | |
357 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 358 | "ltgr\t%2,%0" |
07893d4f | 359 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 360 | |
07893d4f | 361 | (define_insn "*tstdi_cconly" |
9db1d521 | 362 | [(set (reg 33) |
07893d4f UW |
363 | (compare (match_operand:DI 0 "register_operand" "d") |
364 | (match_operand:DI 1 "const0_operand" "")))] | |
365 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 366 | "ltgr\t%0,%0" |
07893d4f | 367 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 368 | |
07893d4f UW |
369 | (define_insn "*tstdi_cconly_31" |
370 | [(set (reg 33) | |
371 | (compare (match_operand:DI 0 "register_operand" "d") | |
372 | (match_operand:DI 1 "const0_operand" "")))] | |
373 | "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" | |
d40c829f | 374 | "srda\t%0,0" |
077dab3b HP |
375 | [(set_attr "op_type" "RS") |
376 | (set_attr "atype" "reg")]) | |
377 | ||
4023fb28 | 378 | |
07893d4f UW |
379 | (define_insn "*tstsi" |
380 | [(set (reg 33) | |
d3632d41 | 381 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 382 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 383 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f UW |
384 | (match_dup 0))] |
385 | "s390_match_ccmode(insn, CCSmode)" | |
386 | "@ | |
d40c829f | 387 | ltr\t%2,%0 |
fc0ea003 UW |
388 | icm\t%2,15,%S0 |
389 | icmy\t%2,15,%S0" | |
d3632d41 | 390 | [(set_attr "op_type" "RR,RS,RSY")]) |
9db1d521 | 391 | |
07893d4f | 392 | (define_insn "*tstsi_cconly" |
4023fb28 | 393 | [(set (reg 33) |
d3632d41 | 394 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 395 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 396 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
397 | "s390_match_ccmode(insn, CCSmode)" |
398 | "@ | |
d40c829f | 399 | ltr\t%0,%0 |
fc0ea003 UW |
400 | icm\t%2,15,%S0 |
401 | icmy\t%2,15,%S0" | |
d3632d41 | 402 | [(set_attr "op_type" "RR,RS,RSY")]) |
4023fb28 | 403 | |
07893d4f UW |
404 | (define_insn "*tstsi_cconly2" |
405 | [(set (reg 33) | |
406 | (compare (match_operand:SI 0 "register_operand" "d") | |
407 | (match_operand:SI 1 "const0_operand" "")))] | |
408 | "s390_match_ccmode(insn, CCSmode)" | |
d40c829f | 409 | "ltr\t%0,%0" |
07893d4f | 410 | [(set_attr "op_type" "RR")]) |
4023fb28 | 411 | |
3af97654 UW |
412 | (define_insn "*tsthiCCT" |
413 | [(set (reg 33) | |
d3632d41 | 414 | (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 | 415 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 416 | (set (match_operand:HI 2 "register_operand" "=d,d,0") |
3af97654 UW |
417 | (match_dup 0))] |
418 | "s390_match_ccmode(insn, CCTmode)" | |
419 | "@ | |
fc0ea003 UW |
420 | icm\t%2,3,%S0 |
421 | icmy\t%2,3,%S0 | |
d40c829f | 422 | tml\t%0,65535" |
d3632d41 | 423 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 UW |
424 | |
425 | (define_insn "*tsthiCCT_cconly" | |
426 | [(set (reg 33) | |
d3632d41 | 427 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 428 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 429 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
430 | "s390_match_ccmode(insn, CCTmode)" |
431 | "@ | |
fc0ea003 UW |
432 | icm\t%2,3,%S0 |
433 | icmy\t%2,3,%S0 | |
d40c829f | 434 | tml\t%0,65535" |
d3632d41 | 435 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 | 436 | |
07893d4f | 437 | (define_insn "*tsthi" |
9db1d521 | 438 | [(set (reg 33) |
d3632d41 | 439 | (compare (match_operand:HI 0 "s_operand" "Q,S") |
9db1d521 | 440 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 441 | (set (match_operand:HI 2 "register_operand" "=d,d") |
9db1d521 HP |
442 | (match_dup 0))] |
443 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 444 | "@ |
fc0ea003 UW |
445 | icm\t%2,3,%S0 |
446 | icmy\t%2,3,%S0" | |
d3632d41 | 447 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 448 | |
07893d4f | 449 | (define_insn "*tsthi_cconly" |
9db1d521 | 450 | [(set (reg 33) |
d3632d41 | 451 | (compare (match_operand:HI 0 "s_operand" "Q,S") |
9db1d521 | 452 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 453 | (clobber (match_scratch:HI 2 "=d,d"))] |
9db1d521 | 454 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 455 | "@ |
fc0ea003 UW |
456 | icm\t%2,3,%S0 |
457 | icmy\t%2,3,%S0" | |
d3632d41 | 458 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 459 | |
3af97654 UW |
460 | (define_insn "*tstqiCCT" |
461 | [(set (reg 33) | |
d3632d41 | 462 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 | 463 | (match_operand:QI 1 "const0_operand" ""))) |
d3632d41 | 464 | (set (match_operand:QI 2 "register_operand" "=d,d,0") |
3af97654 UW |
465 | (match_dup 0))] |
466 | "s390_match_ccmode(insn, CCTmode)" | |
467 | "@ | |
fc0ea003 UW |
468 | icm\t%2,1,%S0 |
469 | icmy\t%2,1,%S0 | |
d40c829f | 470 | tml\t%0,255" |
d3632d41 | 471 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 UW |
472 | |
473 | (define_insn "*tstqiCCT_cconly" | |
474 | [(set (reg 33) | |
d3632d41 | 475 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
476 | (match_operand:QI 1 "const0_operand" "")))] |
477 | "s390_match_ccmode(insn, CCTmode)" | |
478 | "@ | |
fc0ea003 UW |
479 | cli\t%S0,0 |
480 | cliy\t%S0,0 | |
d40c829f | 481 | tml\t%0,255" |
d3632d41 | 482 | [(set_attr "op_type" "SI,SIY,RI")]) |
3af97654 | 483 | |
07893d4f | 484 | (define_insn "*tstqi" |
9db1d521 | 485 | [(set (reg 33) |
d3632d41 | 486 | (compare (match_operand:QI 0 "s_operand" "Q,S") |
07893d4f | 487 | (match_operand:QI 1 "const0_operand" ""))) |
d3632d41 | 488 | (set (match_operand:QI 2 "register_operand" "=d,d") |
07893d4f UW |
489 | (match_dup 0))] |
490 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 491 | "@ |
fc0ea003 UW |
492 | icm\t%2,1,%S0 |
493 | icmy\t%2,1,%S0" | |
d3632d41 | 494 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 495 | |
07893d4f | 496 | (define_insn "*tstqi_cconly" |
9db1d521 | 497 | [(set (reg 33) |
d3632d41 | 498 | (compare (match_operand:QI 0 "s_operand" "Q,S") |
07893d4f | 499 | (match_operand:QI 1 "const0_operand" ""))) |
d3632d41 | 500 | (clobber (match_scratch:QI 2 "=d,d"))] |
07893d4f | 501 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 502 | "@ |
fc0ea003 UW |
503 | icm\t%2,1,%S0 |
504 | icmy\t%2,1,%S0" | |
d3632d41 UW |
505 | [(set_attr "op_type" "RS,RSY")]) |
506 | ||
9db1d521 | 507 | |
575f7c2b UW |
508 | ; Compare (equality) instructions |
509 | ||
510 | (define_insn "*cmpdi_cct" | |
511 | [(set (reg 33) | |
e221ef54 UW |
512 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q") |
513 | (match_operand:DI 1 "general_operand" "d,K,m,BQ")))] | |
514 | "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT" | |
575f7c2b UW |
515 | "@ |
516 | cgr\t%0,%1 | |
f4f41b4e | 517 | cghi\t%0,%h1 |
575f7c2b | 518 | cg\t%0,%1 |
19b63d8e | 519 | #" |
e221ef54 | 520 | [(set_attr "op_type" "RRE,RI,RXY,SS")]) |
575f7c2b UW |
521 | |
522 | (define_insn "*cmpsi_cct" | |
523 | [(set (reg 33) | |
e221ef54 UW |
524 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
525 | (match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))] | |
526 | "s390_match_ccmode (insn, CCTmode)" | |
575f7c2b UW |
527 | "@ |
528 | cr\t%0,%1 | |
f4f41b4e | 529 | chi\t%0,%h1 |
575f7c2b UW |
530 | c\t%0,%1 |
531 | cy\t%0,%1 | |
19b63d8e | 532 | #" |
e221ef54 | 533 | [(set_attr "op_type" "RR,RI,RX,RXY,SS")]) |
575f7c2b UW |
534 | |
535 | ||
07893d4f | 536 | ; Compare (signed) instructions |
4023fb28 | 537 | |
07893d4f | 538 | (define_insn "*cmpdi_ccs_sign" |
4023fb28 | 539 | [(set (reg 33) |
07893d4f UW |
540 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
541 | (match_operand:DI 0 "register_operand" "d,d")))] | |
542 | "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" | |
4023fb28 | 543 | "@ |
d40c829f UW |
544 | cgfr\t%0,%1 |
545 | cgf\t%0,%1" | |
d3632d41 | 546 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 547 | |
07893d4f | 548 | (define_insn "*cmpdi_ccs" |
4023fb28 | 549 | [(set (reg 33) |
07893d4f UW |
550 | (compare (match_operand:DI 0 "register_operand" "d,d,d") |
551 | (match_operand:DI 1 "general_operand" "d,K,m")))] | |
552 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
553 | "@ | |
d40c829f | 554 | cgr\t%0,%1 |
f4f41b4e | 555 | cghi\t%0,%h1 |
d40c829f | 556 | cg\t%0,%1" |
d3632d41 | 557 | [(set_attr "op_type" "RRE,RI,RXY")]) |
c7453384 | 558 | |
07893d4f UW |
559 | (define_insn "*cmpsi_ccs_sign" |
560 | [(set (reg 33) | |
d3632d41 UW |
561 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")) |
562 | (match_operand:SI 0 "register_operand" "d,d")))] | |
07893d4f | 563 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 564 | "@ |
d40c829f UW |
565 | ch\t%0,%1 |
566 | chy\t%0,%1" | |
d3632d41 | 567 | [(set_attr "op_type" "RX,RXY")]) |
4023fb28 | 568 | |
07893d4f | 569 | (define_insn "*cmpsi_ccs" |
9db1d521 | 570 | [(set (reg 33) |
d3632d41 UW |
571 | (compare (match_operand:SI 0 "register_operand" "d,d,d,d") |
572 | (match_operand:SI 1 "general_operand" "d,K,R,T")))] | |
9db1d521 | 573 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 574 | "@ |
d40c829f | 575 | cr\t%0,%1 |
f4f41b4e | 576 | chi\t%0,%h1 |
d40c829f UW |
577 | c\t%0,%1 |
578 | cy\t%0,%1" | |
d3632d41 | 579 | [(set_attr "op_type" "RR,RI,RX,RXY")]) |
c7453384 | 580 | |
07893d4f UW |
581 | |
582 | ; Compare (unsigned) instructions | |
9db1d521 | 583 | |
07893d4f | 584 | (define_insn "*cmpdi_ccu_zero" |
9db1d521 | 585 | [(set (reg 33) |
07893d4f UW |
586 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
587 | (match_operand:DI 0 "register_operand" "d,d")))] | |
575f7c2b | 588 | "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT" |
07893d4f | 589 | "@ |
d40c829f UW |
590 | clgfr\t%0,%1 |
591 | clgf\t%0,%1" | |
d3632d41 | 592 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 593 | |
07893d4f | 594 | (define_insn "*cmpdi_ccu" |
9db1d521 | 595 | [(set (reg 33) |
e221ef54 UW |
596 | (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ") |
597 | (match_operand:DI 1 "general_operand" "d,m,BQ,Q")))] | |
598 | "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT" | |
07893d4f | 599 | "@ |
d40c829f | 600 | clgr\t%0,%1 |
575f7c2b | 601 | clg\t%0,%1 |
e221ef54 | 602 | # |
19b63d8e | 603 | #" |
e221ef54 | 604 | [(set_attr "op_type" "RRE,RXY,SS,SS")]) |
9db1d521 | 605 | |
07893d4f | 606 | (define_insn "*cmpsi_ccu" |
9db1d521 | 607 | [(set (reg 33) |
e221ef54 UW |
608 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ") |
609 | (match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))] | |
610 | "s390_match_ccmode (insn, CCUmode)" | |
07893d4f | 611 | "@ |
d40c829f UW |
612 | clr\t%0,%1 |
613 | cl\t%0,%1 | |
575f7c2b | 614 | cly\t%0,%1 |
e221ef54 | 615 | # |
19b63d8e | 616 | #" |
e221ef54 | 617 | [(set_attr "op_type" "RR,RX,RXY,SS,SS")]) |
9db1d521 | 618 | |
07893d4f | 619 | (define_insn "*cmphi_ccu" |
9db1d521 | 620 | [(set (reg 33) |
e221ef54 UW |
621 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ") |
622 | (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))] | |
575f7c2b | 623 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 624 | && !register_operand (operands[1], HImode)" |
d3632d41 | 625 | "@ |
fc0ea003 UW |
626 | clm\t%0,3,%S1 |
627 | clmy\t%0,3,%S1 | |
e221ef54 | 628 | # |
19b63d8e | 629 | #" |
e221ef54 | 630 | [(set_attr "op_type" "RS,RSY,SS,SS")]) |
9db1d521 HP |
631 | |
632 | (define_insn "*cmpqi_ccu" | |
633 | [(set (reg 33) | |
e221ef54 UW |
634 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
635 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 636 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 637 | && !register_operand (operands[1], QImode)" |
d3632d41 | 638 | "@ |
fc0ea003 UW |
639 | clm\t%0,1,%S1 |
640 | clmy\t%0,1,%S1 | |
641 | cli\t%S0,%b1 | |
642 | cliy\t%S0,%b1 | |
e221ef54 | 643 | # |
19b63d8e | 644 | #" |
e221ef54 | 645 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")]) |
9db1d521 HP |
646 | |
647 | ||
19b63d8e UW |
648 | ; Block compare (CLC) instruction patterns. |
649 | ||
650 | (define_insn "*clc" | |
651 | [(set (reg 33) | |
d4f52f0e | 652 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
653 | (match_operand:BLK 1 "memory_operand" "Q"))) |
654 | (use (match_operand 2 "const_int_operand" "n"))] | |
655 | "s390_match_ccmode (insn, CCUmode) | |
656 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 657 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 658 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
659 | |
660 | (define_split | |
661 | [(set (reg 33) | |
662 | (compare (match_operand 0 "memory_operand" "") | |
663 | (match_operand 1 "memory_operand" "")))] | |
664 | "reload_completed | |
665 | && s390_match_ccmode (insn, CCUmode) | |
666 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
667 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
668 | [(parallel | |
669 | [(set (match_dup 0) (match_dup 1)) | |
670 | (use (match_dup 2))])] | |
671 | { | |
672 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
673 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
674 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
675 | ||
676 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
677 | operands[0], operands[1]); | |
678 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
679 | }) | |
680 | ||
681 | ||
9db1d521 HP |
682 | ; DF instructions |
683 | ||
684 | (define_insn "*cmpdf_ccs_0" | |
685 | [(set (reg 33) | |
686 | (compare (match_operand:DF 0 "register_operand" "f") | |
687 | (match_operand:DF 1 "const0_operand" "")))] | |
688 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 689 | "ltdbr\t%0,%0" |
077dab3b HP |
690 | [(set_attr "op_type" "RRE") |
691 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
692 | |
693 | (define_insn "*cmpdf_ccs_0_ibm" | |
694 | [(set (reg 33) | |
695 | (compare (match_operand:DF 0 "register_operand" "f") | |
696 | (match_operand:DF 1 "const0_operand" "")))] | |
697 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 698 | "ltdr\t%0,%0" |
077dab3b HP |
699 | [(set_attr "op_type" "RR") |
700 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
701 | |
702 | (define_insn "*cmpdf_ccs" | |
703 | [(set (reg 33) | |
704 | (compare (match_operand:DF 0 "register_operand" "f,f") | |
d3632d41 | 705 | (match_operand:DF 1 "general_operand" "f,R")))] |
9db1d521 HP |
706 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
707 | "@ | |
d40c829f UW |
708 | cdbr\t%0,%1 |
709 | cdb\t%0,%1" | |
ce50cae8 | 710 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 711 | (set_attr "type" "fsimpd")]) |
9db1d521 HP |
712 | |
713 | (define_insn "*cmpdf_ccs_ibm" | |
714 | [(set (reg 33) | |
715 | (compare (match_operand:DF 0 "register_operand" "f,f") | |
d3632d41 | 716 | (match_operand:DF 1 "general_operand" "f,R")))] |
9db1d521 HP |
717 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
718 | "@ | |
d40c829f UW |
719 | cdr\t%0,%1 |
720 | cd\t%0,%1" | |
9db1d521 | 721 | [(set_attr "op_type" "RR,RX") |
077dab3b | 722 | (set_attr "type" "fsimpd")]) |
9db1d521 HP |
723 | |
724 | ||
725 | ; SF instructions | |
726 | ||
727 | (define_insn "*cmpsf_ccs_0" | |
728 | [(set (reg 33) | |
729 | (compare (match_operand:SF 0 "register_operand" "f") | |
730 | (match_operand:SF 1 "const0_operand" "")))] | |
731 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 732 | "ltebr\t%0,%0" |
077dab3b HP |
733 | [(set_attr "op_type" "RRE") |
734 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
735 | |
736 | (define_insn "*cmpsf_ccs_0_ibm" | |
737 | [(set (reg 33) | |
738 | (compare (match_operand:SF 0 "register_operand" "f") | |
739 | (match_operand:SF 1 "const0_operand" "")))] | |
740 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 741 | "lter\t%0,%0" |
077dab3b HP |
742 | [(set_attr "op_type" "RR") |
743 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
744 | |
745 | (define_insn "*cmpsf_ccs" | |
746 | [(set (reg 33) | |
747 | (compare (match_operand:SF 0 "register_operand" "f,f") | |
d3632d41 | 748 | (match_operand:SF 1 "general_operand" "f,R")))] |
9db1d521 HP |
749 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
750 | "@ | |
d40c829f UW |
751 | cebr\t%0,%1 |
752 | ceb\t%0,%1" | |
077dab3b HP |
753 | [(set_attr "op_type" "RRE,RXE") |
754 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
755 | |
756 | (define_insn "*cmpsf_ccs" | |
757 | [(set (reg 33) | |
758 | (compare (match_operand:SF 0 "register_operand" "f,f") | |
d3632d41 | 759 | (match_operand:SF 1 "general_operand" "f,R")))] |
9db1d521 HP |
760 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
761 | "@ | |
d40c829f UW |
762 | cer\t%0,%1 |
763 | ce\t%0,%1" | |
077dab3b HP |
764 | [(set_attr "op_type" "RR,RX") |
765 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
766 | |
767 | ||
768 | ;; | |
769 | ;;- Move instructions. | |
770 | ;; | |
771 | ||
772 | ; | |
773 | ; movti instruction pattern(s). | |
774 | ; | |
775 | ||
776 | (define_insn "movti" | |
d3632d41 UW |
777 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q") |
778 | (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))] | |
9db1d521 | 779 | "TARGET_64BIT" |
4023fb28 | 780 | "@ |
fc0ea003 UW |
781 | lmg\t%0,%N0,%S1 |
782 | stmg\t%1,%N1,%S0 | |
4023fb28 | 783 | # |
9b7c75b9 | 784 | # |
19b63d8e | 785 | #" |
b628bd8e UW |
786 | [(set_attr "op_type" "RSY,RSY,*,*,SS") |
787 | (set_attr "type" "lm,stm,*,*,*")]) | |
4023fb28 UW |
788 | |
789 | (define_split | |
790 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
791 | (match_operand:TI 1 "general_operand" ""))] | |
792 | "TARGET_64BIT && reload_completed | |
dc65c307 | 793 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
794 | [(set (match_dup 2) (match_dup 4)) |
795 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 796 | { |
dc65c307 UW |
797 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
798 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
799 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
800 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
801 | }) | |
802 | ||
803 | (define_split | |
804 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
805 | (match_operand:TI 1 "general_operand" ""))] | |
806 | "TARGET_64BIT && reload_completed | |
807 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" | |
808 | [(set (match_dup 2) (match_dup 4)) | |
809 | (set (match_dup 3) (match_dup 5))] | |
810 | { | |
811 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
812 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
813 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
814 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
815 | }) | |
4023fb28 UW |
816 | |
817 | (define_split | |
818 | [(set (match_operand:TI 0 "register_operand" "") | |
819 | (match_operand:TI 1 "memory_operand" ""))] | |
820 | "TARGET_64BIT && reload_completed | |
821 | && !s_operand (operands[1], VOIDmode)" | |
a41c6c53 | 822 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
823 | { |
824 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
825 | s390_load_address (addr, XEXP (operands[1], 0)); | |
826 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
827 | }) |
828 | ||
829 | (define_expand "reload_outti" | |
9c3c3dcc | 830 | [(parallel [(match_operand:TI 0 "" "") |
dc65c307 UW |
831 | (match_operand:TI 1 "register_operand" "d") |
832 | (match_operand:DI 2 "register_operand" "=&a")])] | |
833 | "TARGET_64BIT" | |
834 | { | |
9c3c3dcc | 835 | gcc_assert (MEM_P (operands[0])); |
dc65c307 UW |
836 | s390_load_address (operands[2], XEXP (operands[0], 0)); |
837 | operands[0] = replace_equiv_address (operands[0], operands[2]); | |
838 | emit_move_insn (operands[0], operands[1]); | |
839 | DONE; | |
840 | }) | |
9db1d521 HP |
841 | |
842 | ; | |
843 | ; movdi instruction pattern(s). | |
844 | ; | |
845 | ||
9db1d521 HP |
846 | (define_expand "movdi" |
847 | [(set (match_operand:DI 0 "general_operand" "") | |
848 | (match_operand:DI 1 "general_operand" ""))] | |
849 | "" | |
9db1d521 | 850 | { |
fd3cd001 UW |
851 | /* Handle symbolic constants. */ |
852 | if (TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
853 | emit_symbolic_move (operands); | |
10bbf137 | 854 | }) |
9db1d521 | 855 | |
4023fb28 UW |
856 | (define_insn "*movdi_larl" |
857 | [(set (match_operand:DI 0 "register_operand" "=d") | |
858 | (match_operand:DI 1 "larl_operand" "X"))] | |
859 | "TARGET_64BIT | |
8e509cf9 | 860 | && !FP_REG_P (operands[0])" |
d40c829f | 861 | "larl\t%0,%1" |
4023fb28 | 862 | [(set_attr "op_type" "RIL") |
077dab3b | 863 | (set_attr "type" "larl")]) |
4023fb28 | 864 | |
9db1d521 | 865 | (define_insn "*movdi_64" |
2f7e5a0d | 866 | [(set (match_operand:DI 0 "nonimmediate_operand" |
c5aa1d12 | 867 | "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") |
2f7e5a0d | 868 | (match_operand:DI 1 "general_operand" |
c5aa1d12 | 869 | "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))] |
9db1d521 HP |
870 | "TARGET_64BIT" |
871 | "@ | |
f19a9af7 AK |
872 | lghi\t%0,%h1 |
873 | llihh\t%0,%i1 | |
874 | llihl\t%0,%i1 | |
875 | llilh\t%0,%i1 | |
876 | llill\t%0,%i1 | |
877 | lay\t%0,%a1 | |
d40c829f UW |
878 | lgr\t%0,%1 |
879 | lg\t%0,%1 | |
880 | stg\t%1,%0 | |
881 | ldr\t%0,%1 | |
882 | ld\t%0,%1 | |
883 | ldy\t%0,%1 | |
884 | std\t%1,%0 | |
885 | stdy\t%1,%0 | |
c5aa1d12 UW |
886 | # |
887 | # | |
888 | stam\t%1,%N1,%S0 | |
889 | lam\t%0,%N0,%S1 | |
19b63d8e | 890 | #" |
b628bd8e UW |
891 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY, |
892 | RR,RX,RXY,RX,RXY,*,*,RS,RS,SS") | |
893 | (set_attr "type" "*,*,*,*,*,la,lr,load,store, | |
894 | floadd,floadd,floadd,fstored,fstored,*,*,*,*,*")]) | |
c5aa1d12 UW |
895 | |
896 | (define_split | |
897 | [(set (match_operand:DI 0 "register_operand" "") | |
898 | (match_operand:DI 1 "register_operand" ""))] | |
899 | "TARGET_64BIT && ACCESS_REG_P (operands[1])" | |
900 | [(set (match_dup 2) (match_dup 3)) | |
901 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
902 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
903 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
904 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
905 | ||
906 | (define_split | |
907 | [(set (match_operand:DI 0 "register_operand" "") | |
908 | (match_operand:DI 1 "register_operand" ""))] | |
909 | "TARGET_64BIT && ACCESS_REG_P (operands[0]) | |
910 | && dead_or_set_p (insn, operands[1])" | |
911 | [(set (match_dup 3) (match_dup 2)) | |
912 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
913 | (set (match_dup 4) (match_dup 2))] | |
914 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
915 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
916 | ||
917 | (define_split | |
918 | [(set (match_operand:DI 0 "register_operand" "") | |
919 | (match_operand:DI 1 "register_operand" ""))] | |
920 | "TARGET_64BIT && ACCESS_REG_P (operands[0]) | |
921 | && !dead_or_set_p (insn, operands[1])" | |
922 | [(set (match_dup 3) (match_dup 2)) | |
923 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
924 | (set (match_dup 4) (match_dup 2)) | |
925 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
926 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
927 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
928 | |
929 | (define_insn "*movdi_31" | |
d3632d41 UW |
930 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q") |
931 | (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))] | |
9db1d521 | 932 | "!TARGET_64BIT" |
4023fb28 | 933 | "@ |
fc0ea003 UW |
934 | lm\t%0,%N0,%S1 |
935 | stm\t%1,%N1,%S0 | |
4023fb28 UW |
936 | # |
937 | # | |
d40c829f UW |
938 | ldr\t%0,%1 |
939 | ld\t%0,%1 | |
940 | ldy\t%0,%1 | |
941 | std\t%1,%0 | |
942 | stdy\t%1,%0 | |
19b63d8e | 943 | #" |
b628bd8e UW |
944 | [(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS") |
945 | (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,*")]) | |
4023fb28 UW |
946 | |
947 | (define_split | |
948 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
949 | (match_operand:DI 1 "general_operand" ""))] | |
950 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 951 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
952 | [(set (match_dup 2) (match_dup 4)) |
953 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 954 | { |
dc65c307 UW |
955 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
956 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
957 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
958 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
959 | }) | |
960 | ||
961 | (define_split | |
962 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
963 | (match_operand:DI 1 "general_operand" ""))] | |
964 | "!TARGET_64BIT && reload_completed | |
965 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" | |
966 | [(set (match_dup 2) (match_dup 4)) | |
967 | (set (match_dup 3) (match_dup 5))] | |
968 | { | |
969 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
970 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
971 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
972 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
973 | }) | |
9db1d521 | 974 | |
4023fb28 UW |
975 | (define_split |
976 | [(set (match_operand:DI 0 "register_operand" "") | |
977 | (match_operand:DI 1 "memory_operand" ""))] | |
978 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 979 | && !FP_REG_P (operands[0]) |
4023fb28 | 980 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 981 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
982 | { |
983 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
984 | s390_load_address (addr, XEXP (operands[1], 0)); | |
985 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
986 | }) |
987 | ||
988 | (define_expand "reload_outdi" | |
9c3c3dcc | 989 | [(parallel [(match_operand:DI 0 "" "") |
dc65c307 UW |
990 | (match_operand:DI 1 "register_operand" "d") |
991 | (match_operand:SI 2 "register_operand" "=&a")])] | |
992 | "!TARGET_64BIT" | |
993 | { | |
9c3c3dcc | 994 | gcc_assert (MEM_P (operands[0])); |
dc65c307 UW |
995 | s390_load_address (operands[2], XEXP (operands[0], 0)); |
996 | operands[0] = replace_equiv_address (operands[0], operands[2]); | |
997 | emit_move_insn (operands[0], operands[1]); | |
998 | DONE; | |
999 | }) | |
9db1d521 | 1000 | |
84817c5d UW |
1001 | (define_peephole2 |
1002 | [(set (match_operand:DI 0 "register_operand" "") | |
1003 | (mem:DI (match_operand 1 "address_operand" "")))] | |
1004 | "TARGET_64BIT | |
1005 | && !FP_REG_P (operands[0]) | |
1006 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1007 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1008 | && get_pool_mode (operands[1]) == DImode | |
1009 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1010 | [(set (match_dup 0) (match_dup 2))] | |
1011 | "operands[2] = get_pool_constant (operands[1]);") | |
1012 | ||
7bdff56f UW |
1013 | (define_insn "*la_64" |
1014 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
1015 | (match_operand:QI 1 "address_operand" "U,W"))] | |
1016 | "TARGET_64BIT" | |
1017 | "@ | |
1018 | la\t%0,%a1 | |
1019 | lay\t%0,%a1" | |
1020 | [(set_attr "op_type" "RX,RXY") | |
1021 | (set_attr "type" "la")]) | |
1022 | ||
1023 | (define_peephole2 | |
1024 | [(parallel | |
1025 | [(set (match_operand:DI 0 "register_operand" "") | |
1026 | (match_operand:QI 1 "address_operand" "")) | |
1027 | (clobber (reg:CC 33))])] | |
1028 | "TARGET_64BIT | |
e1d5ee28 | 1029 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1030 | [(set (match_dup 0) (match_dup 1))] |
1031 | "") | |
1032 | ||
1033 | (define_peephole2 | |
1034 | [(set (match_operand:DI 0 "register_operand" "") | |
1035 | (match_operand:DI 1 "register_operand" "")) | |
1036 | (parallel | |
1037 | [(set (match_dup 0) | |
1038 | (plus:DI (match_dup 0) | |
1039 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
1040 | (clobber (reg:CC 33))])] | |
1041 | "TARGET_64BIT | |
1042 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1043 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1044 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1045 | "") | |
1046 | ||
1047 | (define_expand "reload_indi" | |
1048 | [(parallel [(match_operand:DI 0 "register_operand" "=a") | |
1049 | (match_operand:DI 1 "s390_plus_operand" "") | |
1050 | (match_operand:DI 2 "register_operand" "=&a")])] | |
1051 | "TARGET_64BIT" | |
1052 | { | |
1053 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1054 | DONE; | |
1055 | }) | |
1056 | ||
9db1d521 HP |
1057 | ; |
1058 | ; movsi instruction pattern(s). | |
1059 | ; | |
1060 | ||
9db1d521 HP |
1061 | (define_expand "movsi" |
1062 | [(set (match_operand:SI 0 "general_operand" "") | |
1063 | (match_operand:SI 1 "general_operand" ""))] | |
1064 | "" | |
9db1d521 | 1065 | { |
fd3cd001 UW |
1066 | /* Handle symbolic constants. */ |
1067 | if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
1068 | emit_symbolic_move (operands); | |
10bbf137 | 1069 | }) |
9db1d521 | 1070 | |
9e8327e3 UW |
1071 | (define_insn "*movsi_larl" |
1072 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1073 | (match_operand:SI 1 "larl_operand" "X"))] | |
1074 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1075 | && !FP_REG_P (operands[0])" | |
1076 | "larl\t%0,%1" | |
1077 | [(set_attr "op_type" "RIL") | |
1078 | (set_attr "type" "larl")]) | |
1079 | ||
f19a9af7 | 1080 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1081 | [(set (match_operand:SI 0 "nonimmediate_operand" |
c5aa1d12 | 1082 | "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") |
2f7e5a0d | 1083 | (match_operand:SI 1 "general_operand" |
c5aa1d12 | 1084 | "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))] |
f19a9af7 | 1085 | "TARGET_ZARCH" |
9db1d521 | 1086 | "@ |
f19a9af7 AK |
1087 | lhi\t%0,%h1 |
1088 | llilh\t%0,%i1 | |
1089 | llill\t%0,%i1 | |
1090 | lay\t%0,%a1 | |
d40c829f UW |
1091 | lr\t%0,%1 |
1092 | l\t%0,%1 | |
1093 | ly\t%0,%1 | |
1094 | st\t%1,%0 | |
1095 | sty\t%1,%0 | |
1096 | ler\t%0,%1 | |
1097 | le\t%0,%1 | |
1098 | ley\t%0,%1 | |
1099 | ste\t%1,%0 | |
1100 | stey\t%1,%0 | |
c5aa1d12 UW |
1101 | ear\t%0,%1 |
1102 | sar\t%0,%1 | |
1103 | stam\t%1,%1,%S0 | |
1104 | lam\t%0,%0,%S1 | |
19b63d8e | 1105 | #" |
b628bd8e UW |
1106 | [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY, |
1107 | RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS") | |
1108 | (set_attr "type" "*,*,*,la,lr,load,load,store,store, | |
1109 | floads,floads,floads,fstores,fstores,*,*,*,*,*")]) | |
f19a9af7 AK |
1110 | |
1111 | (define_insn "*movsi_esa" | |
c5aa1d12 UW |
1112 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q") |
1113 | (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))] | |
f19a9af7 AK |
1114 | "!TARGET_ZARCH" |
1115 | "@ | |
1116 | lhi\t%0,%h1 | |
1117 | lr\t%0,%1 | |
1118 | l\t%0,%1 | |
1119 | st\t%1,%0 | |
1120 | ler\t%0,%1 | |
1121 | le\t%0,%1 | |
1122 | ste\t%1,%0 | |
c5aa1d12 UW |
1123 | ear\t%0,%1 |
1124 | sar\t%0,%1 | |
1125 | stam\t%1,%1,%S0 | |
1126 | lam\t%0,%0,%S1 | |
19b63d8e | 1127 | #" |
c5aa1d12 | 1128 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS") |
b628bd8e | 1129 | (set_attr "type" "*,lr,load,store,floads,floads,fstores,*,*,*,*,*")]) |
9db1d521 | 1130 | |
84817c5d UW |
1131 | (define_peephole2 |
1132 | [(set (match_operand:SI 0 "register_operand" "") | |
1133 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1134 | "!FP_REG_P (operands[0]) | |
1135 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1136 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1137 | && get_pool_mode (operands[1]) == SImode | |
1138 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1139 | [(set (match_dup 0) (match_dup 2))] | |
1140 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 1141 | |
7bdff56f UW |
1142 | (define_insn "*la_31" |
1143 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1144 | (match_operand:QI 1 "address_operand" "U,W"))] | |
1145 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" | |
1146 | "@ | |
1147 | la\t%0,%a1 | |
1148 | lay\t%0,%a1" | |
1149 | [(set_attr "op_type" "RX,RXY") | |
1150 | (set_attr "type" "la")]) | |
1151 | ||
1152 | (define_peephole2 | |
1153 | [(parallel | |
1154 | [(set (match_operand:SI 0 "register_operand" "") | |
1155 | (match_operand:QI 1 "address_operand" "")) | |
1156 | (clobber (reg:CC 33))])] | |
1157 | "!TARGET_64BIT | |
e1d5ee28 | 1158 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1159 | [(set (match_dup 0) (match_dup 1))] |
1160 | "") | |
1161 | ||
1162 | (define_peephole2 | |
1163 | [(set (match_operand:SI 0 "register_operand" "") | |
1164 | (match_operand:SI 1 "register_operand" "")) | |
1165 | (parallel | |
1166 | [(set (match_dup 0) | |
1167 | (plus:SI (match_dup 0) | |
1168 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
1169 | (clobber (reg:CC 33))])] | |
1170 | "!TARGET_64BIT | |
1171 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1172 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1173 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
1174 | "") | |
1175 | ||
1176 | (define_insn "*la_31_and" | |
1177 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1178 | (and:SI (match_operand:QI 1 "address_operand" "U,W") | |
1179 | (const_int 2147483647)))] | |
1180 | "!TARGET_64BIT" | |
1181 | "@ | |
1182 | la\t%0,%a1 | |
1183 | lay\t%0,%a1" | |
1184 | [(set_attr "op_type" "RX,RXY") | |
1185 | (set_attr "type" "la")]) | |
1186 | ||
1187 | (define_insn_and_split "*la_31_and_cc" | |
1188 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1189 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
1190 | (const_int 2147483647))) | |
1191 | (clobber (reg:CC 33))] | |
1192 | "!TARGET_64BIT" | |
1193 | "#" | |
1194 | "&& reload_completed" | |
1195 | [(set (match_dup 0) | |
1196 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
1197 | "" | |
1198 | [(set_attr "op_type" "RX") | |
1199 | (set_attr "type" "la")]) | |
1200 | ||
1201 | (define_insn "force_la_31" | |
1202 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1203 | (match_operand:QI 1 "address_operand" "U,W")) | |
1204 | (use (const_int 0))] | |
1205 | "!TARGET_64BIT" | |
1206 | "@ | |
1207 | la\t%0,%a1 | |
1208 | lay\t%0,%a1" | |
1209 | [(set_attr "op_type" "RX") | |
1210 | (set_attr "type" "la")]) | |
1211 | ||
1212 | (define_expand "reload_insi" | |
1213 | [(parallel [(match_operand:SI 0 "register_operand" "=a") | |
1214 | (match_operand:SI 1 "s390_plus_operand" "") | |
1215 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1216 | "!TARGET_64BIT" | |
1217 | { | |
1218 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1219 | DONE; | |
1220 | }) | |
1221 | ||
9db1d521 HP |
1222 | ; |
1223 | ; movhi instruction pattern(s). | |
1224 | ; | |
1225 | ||
02ed3c5e UW |
1226 | (define_expand "movhi" |
1227 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
1228 | (match_operand:HI 1 "general_operand" ""))] | |
1229 | "" | |
1230 | { | |
2f7e5a0d | 1231 | /* Make it explicit that loading a register from memory |
02ed3c5e UW |
1232 | always sign-extends (at least) to SImode. */ |
1233 | if (optimize && !no_new_pseudos | |
1234 | && register_operand (operands[0], VOIDmode) | |
8fff4fc1 | 1235 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
1236 | { |
1237 | rtx tmp = gen_reg_rtx (SImode); | |
1238 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
1239 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); | |
1240 | operands[1] = gen_lowpart (HImode, tmp); | |
1241 | } | |
1242 | }) | |
1243 | ||
1244 | (define_insn "*movhi" | |
d3632d41 UW |
1245 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q") |
1246 | (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))] | |
9db1d521 HP |
1247 | "" |
1248 | "@ | |
d40c829f UW |
1249 | lr\t%0,%1 |
1250 | lhi\t%0,%h1 | |
1251 | lh\t%0,%1 | |
1252 | lhy\t%0,%1 | |
1253 | sth\t%1,%0 | |
1254 | sthy\t%1,%0 | |
19b63d8e | 1255 | #" |
d3632d41 | 1256 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS") |
b628bd8e | 1257 | (set_attr "type" "lr,*,*,*,store,store,*")]) |
9db1d521 | 1258 | |
84817c5d UW |
1259 | (define_peephole2 |
1260 | [(set (match_operand:HI 0 "register_operand" "") | |
1261 | (mem:HI (match_operand 1 "address_operand" "")))] | |
1262 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1263 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1264 | && get_pool_mode (operands[1]) == HImode | |
1265 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1266 | [(set (match_dup 0) (match_dup 2))] | |
1267 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1268 | |
9db1d521 HP |
1269 | ; |
1270 | ; movqi instruction pattern(s). | |
1271 | ; | |
1272 | ||
02ed3c5e UW |
1273 | (define_expand "movqi" |
1274 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1275 | (match_operand:QI 1 "general_operand" ""))] | |
1276 | "" | |
1277 | { | |
c19ec8f9 | 1278 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 1279 | is just as fast as a QImode load. */ |
c19ec8f9 | 1280 | if (TARGET_ZARCH && optimize && !no_new_pseudos |
02ed3c5e | 1281 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1282 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 1283 | { |
c19ec8f9 UW |
1284 | rtx tmp = gen_reg_rtx (word_mode); |
1285 | rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]); | |
02ed3c5e UW |
1286 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); |
1287 | operands[1] = gen_lowpart (QImode, tmp); | |
1288 | } | |
1289 | }) | |
4023fb28 | 1290 | |
02ed3c5e | 1291 | (define_insn "*movqi" |
d3632d41 UW |
1292 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") |
1293 | (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))] | |
9db1d521 HP |
1294 | "" |
1295 | "@ | |
d40c829f UW |
1296 | lr\t%0,%1 |
1297 | lhi\t%0,%b1 | |
1298 | ic\t%0,%1 | |
1299 | icy\t%0,%1 | |
1300 | stc\t%1,%0 | |
1301 | stcy\t%1,%0 | |
fc0ea003 UW |
1302 | mvi\t%S0,%b1 |
1303 | mviy\t%S0,%b1 | |
19b63d8e | 1304 | #" |
d3632d41 | 1305 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") |
b628bd8e | 1306 | (set_attr "type" "lr,*,*,*,store,store,store,store,*")]) |
9db1d521 | 1307 | |
84817c5d UW |
1308 | (define_peephole2 |
1309 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1310 | (mem:QI (match_operand 1 "address_operand" "")))] | |
1311 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1312 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1313 | && get_pool_mode (operands[1]) == QImode | |
1314 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1315 | [(set (match_dup 0) (match_dup 2))] | |
1316 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1317 | |
9db1d521 | 1318 | ; |
05b9aaaa | 1319 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
1320 | ; |
1321 | ||
1322 | (define_insn "*movstrictqi" | |
d3632d41 UW |
1323 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
1324 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 1325 | "" |
d3632d41 | 1326 | "@ |
d40c829f UW |
1327 | ic\t%0,%1 |
1328 | icy\t%0,%1" | |
d3632d41 | 1329 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 HP |
1330 | |
1331 | ; | |
1332 | ; movstricthi instruction pattern(s). | |
1333 | ; | |
1334 | ||
1335 | (define_insn "*movstricthi" | |
d3632d41 | 1336 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 1337 | (match_operand:HI 1 "memory_operand" "Q,S")) |
9db1d521 HP |
1338 | (clobber (reg:CC 33))] |
1339 | "" | |
d3632d41 | 1340 | "@ |
fc0ea003 UW |
1341 | icm\t%0,3,%S1 |
1342 | icmy\t%0,3,%S1" | |
d3632d41 | 1343 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 HP |
1344 | |
1345 | ; | |
1346 | ; movstrictsi instruction pattern(s). | |
1347 | ; | |
1348 | ||
05b9aaaa | 1349 | (define_insn "movstrictsi" |
c5aa1d12 UW |
1350 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
1351 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9db1d521 HP |
1352 | "TARGET_64BIT" |
1353 | "@ | |
d40c829f UW |
1354 | lr\t%0,%1 |
1355 | l\t%0,%1 | |
c5aa1d12 UW |
1356 | ly\t%0,%1 |
1357 | ear\t%0,%1" | |
1358 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
1359 | (set_attr "type" "lr,load,load,*")]) | |
9db1d521 HP |
1360 | |
1361 | ; | |
1362 | ; movdf instruction pattern(s). | |
1363 | ; | |
1364 | ||
1365 | (define_expand "movdf" | |
1366 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1367 | (match_operand:DF 1 "general_operand" ""))] | |
1368 | "" | |
13c025c1 | 1369 | "") |
9db1d521 HP |
1370 | |
1371 | (define_insn "*movdf_64" | |
d3632d41 UW |
1372 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q") |
1373 | (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))] | |
4023fb28 | 1374 | "TARGET_64BIT" |
9db1d521 | 1375 | "@ |
d40c829f UW |
1376 | ldr\t%0,%1 |
1377 | ld\t%0,%1 | |
1378 | ldy\t%0,%1 | |
1379 | std\t%1,%0 | |
1380 | stdy\t%1,%0 | |
1381 | lgr\t%0,%1 | |
1382 | lg\t%0,%1 | |
1383 | stg\t%1,%0 | |
19b63d8e | 1384 | #" |
d3632d41 | 1385 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") |
b628bd8e | 1386 | (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,*")]) |
9db1d521 HP |
1387 | |
1388 | (define_insn "*movdf_31" | |
d3632d41 UW |
1389 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q") |
1390 | (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))] | |
4023fb28 | 1391 | "!TARGET_64BIT" |
9db1d521 | 1392 | "@ |
d40c829f UW |
1393 | ldr\t%0,%1 |
1394 | ld\t%0,%1 | |
1395 | ldy\t%0,%1 | |
1396 | std\t%1,%0 | |
1397 | stdy\t%1,%0 | |
fc0ea003 UW |
1398 | lm\t%0,%N0,%S1 |
1399 | stm\t%1,%N1,%S0 | |
4023fb28 | 1400 | # |
9b7c75b9 | 1401 | # |
19b63d8e | 1402 | #" |
b628bd8e UW |
1403 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,*,*,SS") |
1404 | (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,*")]) | |
4023fb28 UW |
1405 | |
1406 | (define_split | |
1407 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1408 | (match_operand:DF 1 "general_operand" ""))] | |
1409 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 1410 | && s390_split_ok_p (operands[0], operands[1], DFmode, 0)" |
4023fb28 UW |
1411 | [(set (match_dup 2) (match_dup 4)) |
1412 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1413 | { |
dc65c307 UW |
1414 | operands[2] = operand_subword (operands[0], 0, 0, DFmode); |
1415 | operands[3] = operand_subword (operands[0], 1, 0, DFmode); | |
1416 | operands[4] = operand_subword (operands[1], 0, 0, DFmode); | |
1417 | operands[5] = operand_subword (operands[1], 1, 0, DFmode); | |
1418 | }) | |
1419 | ||
1420 | (define_split | |
1421 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1422 | (match_operand:DF 1 "general_operand" ""))] | |
1423 | "!TARGET_64BIT && reload_completed | |
1424 | && s390_split_ok_p (operands[0], operands[1], DFmode, 1)" | |
1425 | [(set (match_dup 2) (match_dup 4)) | |
1426 | (set (match_dup 3) (match_dup 5))] | |
1427 | { | |
1428 | operands[2] = operand_subword (operands[0], 1, 0, DFmode); | |
1429 | operands[3] = operand_subword (operands[0], 0, 0, DFmode); | |
1430 | operands[4] = operand_subword (operands[1], 1, 0, DFmode); | |
1431 | operands[5] = operand_subword (operands[1], 0, 0, DFmode); | |
1432 | }) | |
9db1d521 | 1433 | |
4023fb28 UW |
1434 | (define_split |
1435 | [(set (match_operand:DF 0 "register_operand" "") | |
1436 | (match_operand:DF 1 "memory_operand" ""))] | |
1437 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 1438 | && !FP_REG_P (operands[0]) |
4023fb28 | 1439 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1440 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1441 | { |
1442 | rtx addr = operand_subword (operands[0], 1, 0, DFmode); | |
1443 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1444 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1445 | }) |
1446 | ||
1447 | (define_expand "reload_outdf" | |
9c3c3dcc | 1448 | [(parallel [(match_operand:DF 0 "" "") |
dc65c307 UW |
1449 | (match_operand:DF 1 "register_operand" "d") |
1450 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1451 | "!TARGET_64BIT" | |
1452 | { | |
9c3c3dcc | 1453 | gcc_assert (MEM_P (operands[0])); |
dc65c307 UW |
1454 | s390_load_address (operands[2], XEXP (operands[0], 0)); |
1455 | operands[0] = replace_equiv_address (operands[0], operands[2]); | |
1456 | emit_move_insn (operands[0], operands[1]); | |
1457 | DONE; | |
1458 | }) | |
9db1d521 HP |
1459 | |
1460 | ; | |
1461 | ; movsf instruction pattern(s). | |
1462 | ; | |
1463 | ||
13c025c1 | 1464 | (define_insn "movsf" |
d3632d41 UW |
1465 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q") |
1466 | (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))] | |
4023fb28 | 1467 | "" |
9db1d521 | 1468 | "@ |
d40c829f UW |
1469 | ler\t%0,%1 |
1470 | le\t%0,%1 | |
1471 | ley\t%0,%1 | |
1472 | ste\t%1,%0 | |
1473 | stey\t%1,%0 | |
1474 | lr\t%0,%1 | |
1475 | l\t%0,%1 | |
1476 | ly\t%0,%1 | |
1477 | st\t%1,%0 | |
1478 | sty\t%1,%0 | |
19b63d8e | 1479 | #" |
d3632d41 | 1480 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") |
b628bd8e UW |
1481 | (set_attr "type" "floads,floads,floads,fstores,fstores, |
1482 | lr,load,load,store,store,*")]) | |
4023fb28 | 1483 | |
9dc62c00 AK |
1484 | ; |
1485 | ; movcc instruction pattern | |
1486 | ; | |
1487 | ||
1488 | (define_insn "movcc" | |
1489 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
1490 | (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))] | |
1491 | "" | |
1492 | "@ | |
1493 | lr\t%0,%1 | |
1494 | tmh\t%1,12288 | |
1495 | ipm\t%0 | |
1496 | st\t%0,%1 | |
1497 | sty\t%0,%1 | |
1498 | l\t%1,%0 | |
1499 | ly\t%1,%0" | |
8dd3b235 AK |
1500 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
1501 | (set_attr "type" "lr,*,*,store,store,load,load")]) | |
9dc62c00 | 1502 | |
19b63d8e UW |
1503 | ; |
1504 | ; Block move (MVC) patterns. | |
1505 | ; | |
1506 | ||
1507 | (define_insn "*mvc" | |
1508 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
1509 | (match_operand:BLK 1 "memory_operand" "Q")) | |
1510 | (use (match_operand 2 "const_int_operand" "n"))] | |
1511 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1512 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 1513 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1514 | |
1515 | (define_split | |
1516 | [(set (match_operand 0 "memory_operand" "") | |
1517 | (match_operand 1 "memory_operand" ""))] | |
1518 | "reload_completed | |
1519 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1520 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1521 | [(parallel | |
1522 | [(set (match_dup 0) (match_dup 1)) | |
1523 | (use (match_dup 2))])] | |
1524 | { | |
1525 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1526 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1527 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1528 | }) | |
1529 | ||
1530 | (define_peephole2 | |
1531 | [(parallel | |
1532 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1533 | (match_operand:BLK 1 "memory_operand" "")) | |
1534 | (use (match_operand 2 "const_int_operand" ""))]) | |
1535 | (parallel | |
1536 | [(set (match_operand:BLK 3 "memory_operand" "") | |
1537 | (match_operand:BLK 4 "memory_operand" "")) | |
1538 | (use (match_operand 5 "const_int_operand" ""))])] | |
1539 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
1540 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
1541 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" | |
1542 | [(parallel | |
1543 | [(set (match_dup 6) (match_dup 7)) | |
1544 | (use (match_dup 8))])] | |
1545 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
1546 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
1547 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
1548 | ||
1549 | ||
9db1d521 HP |
1550 | ; |
1551 | ; load_multiple pattern(s). | |
1552 | ; | |
22ea6b4f UW |
1553 | ; ??? Due to reload problems with replacing registers inside match_parallel |
1554 | ; we currently support load_multiple/store_multiple only after reload. | |
1555 | ; | |
9db1d521 HP |
1556 | |
1557 | (define_expand "load_multiple" | |
1558 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1559 | (match_operand 1 "" "")) | |
1560 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 1561 | "reload_completed" |
9db1d521 | 1562 | { |
c19ec8f9 | 1563 | enum machine_mode mode; |
9db1d521 HP |
1564 | int regno; |
1565 | int count; | |
1566 | rtx from; | |
4023fb28 | 1567 | int i, off; |
9db1d521 HP |
1568 | |
1569 | /* Support only loading a constant number of fixed-point registers from | |
1570 | memory and only bother with this if more than two */ | |
1571 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1572 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1573 | || INTVAL (operands[2]) > 16 |
1574 | || GET_CODE (operands[1]) != MEM | |
1575 | || GET_CODE (operands[0]) != REG | |
1576 | || REGNO (operands[0]) >= 16) | |
1577 | FAIL; | |
1578 | ||
1579 | count = INTVAL (operands[2]); | |
1580 | regno = REGNO (operands[0]); | |
c19ec8f9 UW |
1581 | mode = GET_MODE (operands[0]); |
1582 | if (mode != SImode && mode != word_mode) | |
1583 | FAIL; | |
9db1d521 HP |
1584 | |
1585 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1586 | if (no_new_pseudos) |
1587 | { | |
1588 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
1589 | { | |
1590 | from = XEXP (operands[1], 0); | |
1591 | off = 0; | |
1592 | } | |
1593 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
1594 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
1595 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
1596 | { | |
1597 | from = XEXP (XEXP (operands[1], 0), 0); | |
1598 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
1599 | } | |
1600 | else | |
1601 | FAIL; | |
4023fb28 UW |
1602 | } |
1603 | else | |
1604 | { | |
1605 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
1606 | off = 0; | |
1607 | } | |
9db1d521 HP |
1608 | |
1609 | for (i = 0; i < count; i++) | |
1610 | XVECEXP (operands[3], 0, i) | |
c19ec8f9 UW |
1611 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), |
1612 | change_address (operands[1], mode, | |
1613 | plus_constant (from, off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 1614 | }) |
9db1d521 HP |
1615 | |
1616 | (define_insn "*load_multiple_di" | |
1617 | [(match_parallel 0 "load_multiple_operation" | |
1618 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 1619 | (match_operand:DI 2 "s_operand" "QS"))])] |
22ea6b4f | 1620 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
1621 | { |
1622 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1623 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 1624 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 1625 | } |
d3632d41 | 1626 | [(set_attr "op_type" "RSY") |
4023fb28 | 1627 | (set_attr "type" "lm")]) |
9db1d521 HP |
1628 | |
1629 | (define_insn "*load_multiple_si" | |
1630 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
1631 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
1632 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 1633 | "reload_completed" |
9db1d521 HP |
1634 | { |
1635 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1636 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 1637 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 1638 | } |
d3632d41 | 1639 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1640 | (set_attr "type" "lm")]) |
9db1d521 HP |
1641 | |
1642 | ; | |
c7453384 | 1643 | ; store multiple pattern(s). |
9db1d521 HP |
1644 | ; |
1645 | ||
1646 | (define_expand "store_multiple" | |
1647 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1648 | (match_operand 1 "" "")) | |
1649 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 1650 | "reload_completed" |
9db1d521 | 1651 | { |
c19ec8f9 | 1652 | enum machine_mode mode; |
9db1d521 HP |
1653 | int regno; |
1654 | int count; | |
1655 | rtx to; | |
4023fb28 | 1656 | int i, off; |
9db1d521 HP |
1657 | |
1658 | /* Support only storing a constant number of fixed-point registers to | |
1659 | memory and only bother with this if more than two. */ | |
1660 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1661 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1662 | || INTVAL (operands[2]) > 16 |
1663 | || GET_CODE (operands[0]) != MEM | |
1664 | || GET_CODE (operands[1]) != REG | |
1665 | || REGNO (operands[1]) >= 16) | |
1666 | FAIL; | |
1667 | ||
1668 | count = INTVAL (operands[2]); | |
1669 | regno = REGNO (operands[1]); | |
c19ec8f9 UW |
1670 | mode = GET_MODE (operands[1]); |
1671 | if (mode != SImode && mode != word_mode) | |
1672 | FAIL; | |
9db1d521 HP |
1673 | |
1674 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1675 | |
1676 | if (no_new_pseudos) | |
1677 | { | |
1678 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
1679 | { | |
1680 | to = XEXP (operands[0], 0); | |
1681 | off = 0; | |
1682 | } | |
1683 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
1684 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
1685 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
1686 | { | |
1687 | to = XEXP (XEXP (operands[0], 0), 0); | |
1688 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
1689 | } | |
1690 | else | |
1691 | FAIL; | |
4023fb28 | 1692 | } |
c7453384 | 1693 | else |
4023fb28 UW |
1694 | { |
1695 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
1696 | off = 0; | |
1697 | } | |
9db1d521 HP |
1698 | |
1699 | for (i = 0; i < count; i++) | |
1700 | XVECEXP (operands[3], 0, i) | |
1701 | = gen_rtx_SET (VOIDmode, | |
c19ec8f9 UW |
1702 | change_address (operands[0], mode, |
1703 | plus_constant (to, off + i * GET_MODE_SIZE (mode))), | |
1704 | gen_rtx_REG (mode, regno + i)); | |
10bbf137 | 1705 | }) |
9db1d521 HP |
1706 | |
1707 | (define_insn "*store_multiple_di" | |
1708 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 1709 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 1710 | (match_operand:DI 2 "register_operand" "r"))])] |
22ea6b4f | 1711 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
1712 | { |
1713 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1714 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 1715 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 1716 | } |
d3632d41 | 1717 | [(set_attr "op_type" "RSY") |
4023fb28 | 1718 | (set_attr "type" "stm")]) |
9db1d521 HP |
1719 | |
1720 | ||
1721 | (define_insn "*store_multiple_si" | |
1722 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
1723 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
1724 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 1725 | "reload_completed" |
9db1d521 HP |
1726 | { |
1727 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1728 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 1729 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 1730 | } |
d3632d41 | 1731 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1732 | (set_attr "type" "stm")]) |
9db1d521 HP |
1733 | |
1734 | ;; | |
1735 | ;; String instructions. | |
1736 | ;; | |
1737 | ||
9bb86f41 UW |
1738 | (define_insn "*execute" |
1739 | [(match_parallel 0 "" | |
1740 | [(unspec [(match_operand 1 "register_operand" "a") | |
1741 | (match_operand:BLK 2 "memory_operand" "R") | |
1742 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
1743 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
1744 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
1745 | "ex\t%1,%2" | |
29a74354 UW |
1746 | [(set_attr "op_type" "RX") |
1747 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
1748 | |
1749 | ||
91d39d71 UW |
1750 | ; |
1751 | ; strlenM instruction pattern(s). | |
1752 | ; | |
1753 | ||
1754 | (define_expand "strlendi" | |
1755 | [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" "")) | |
2f7e5a0d | 1756 | (parallel |
91d39d71 UW |
1757 | [(set (match_dup 4) |
1758 | (unspec:DI [(const_int 0) | |
1759 | (match_operand:BLK 1 "memory_operand" "") | |
1760 | (reg:QI 0) | |
1761 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) | |
1762 | (clobber (scratch:DI)) | |
1763 | (clobber (reg:CC 33))]) | |
1764 | (parallel | |
1765 | [(set (match_operand:DI 0 "register_operand" "") | |
1766 | (minus:DI (match_dup 4) (match_dup 5))) | |
1767 | (clobber (reg:CC 33))])] | |
1768 | "TARGET_64BIT" | |
1769 | { | |
1770 | operands[4] = gen_reg_rtx (DImode); | |
1771 | operands[5] = gen_reg_rtx (DImode); | |
1772 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
1773 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
1774 | }) | |
1775 | ||
1776 | (define_insn "*strlendi" | |
1777 | [(set (match_operand:DI 0 "register_operand" "=a") | |
1778 | (unspec:DI [(match_operand:DI 2 "general_operand" "0") | |
1779 | (mem:BLK (match_operand:DI 3 "register_operand" "1")) | |
1780 | (reg:QI 0) | |
1781 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) | |
1782 | (clobber (match_scratch:DI 1 "=a")) | |
1783 | (clobber (reg:CC 33))] | |
1784 | "TARGET_64BIT" | |
1785 | "srst\t%0,%1\;jo\t.-4" | |
b628bd8e UW |
1786 | [(set_attr "length" "8") |
1787 | (set_attr "type" "vs")]) | |
91d39d71 UW |
1788 | |
1789 | (define_expand "strlensi" | |
1790 | [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" "")) | |
2f7e5a0d | 1791 | (parallel |
91d39d71 UW |
1792 | [(set (match_dup 4) |
1793 | (unspec:SI [(const_int 0) | |
1794 | (match_operand:BLK 1 "memory_operand" "") | |
1795 | (reg:QI 0) | |
1796 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) | |
1797 | (clobber (scratch:SI)) | |
1798 | (clobber (reg:CC 33))]) | |
1799 | (parallel | |
1800 | [(set (match_operand:SI 0 "register_operand" "") | |
1801 | (minus:SI (match_dup 4) (match_dup 5))) | |
1802 | (clobber (reg:CC 33))])] | |
1803 | "!TARGET_64BIT" | |
1804 | { | |
1805 | operands[4] = gen_reg_rtx (SImode); | |
1806 | operands[5] = gen_reg_rtx (SImode); | |
1807 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
1808 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
1809 | }) | |
1810 | ||
1811 | (define_insn "*strlensi" | |
1812 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1813 | (unspec:SI [(match_operand:SI 2 "general_operand" "0") | |
1814 | (mem:BLK (match_operand:SI 3 "register_operand" "1")) | |
1815 | (reg:QI 0) | |
1816 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) | |
1817 | (clobber (match_scratch:SI 1 "=a")) | |
2f7e5a0d | 1818 | (clobber (reg:CC 33))] |
91d39d71 UW |
1819 | "!TARGET_64BIT" |
1820 | "srst\t%0,%1\;jo\t.-4" | |
b628bd8e UW |
1821 | [(set_attr "length" "8") |
1822 | (set_attr "type" "vs")]) | |
91d39d71 | 1823 | |
9db1d521 | 1824 | ; |
70128ad9 | 1825 | ; movmemM instruction pattern(s). |
9db1d521 HP |
1826 | ; |
1827 | ||
70128ad9 | 1828 | (define_expand "movmemdi" |
a41c6c53 UW |
1829 | [(set (match_operand:BLK 0 "memory_operand" "") |
1830 | (match_operand:BLK 1 "memory_operand" "")) | |
1831 | (use (match_operand:DI 2 "general_operand" "")) | |
1832 | (match_operand 3 "" "")] | |
1833 | "TARGET_64BIT" | |
70128ad9 | 1834 | "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 1835 | |
70128ad9 | 1836 | (define_expand "movmemsi" |
a41c6c53 UW |
1837 | [(set (match_operand:BLK 0 "memory_operand" "") |
1838 | (match_operand:BLK 1 "memory_operand" "")) | |
1839 | (use (match_operand:SI 2 "general_operand" "")) | |
1840 | (match_operand 3 "" "")] | |
1841 | "" | |
70128ad9 | 1842 | "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 1843 | |
ecbe845e UW |
1844 | ; Move a block that is up to 256 bytes in length. |
1845 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 1846 | |
70128ad9 | 1847 | (define_expand "movmem_short" |
b9404c99 UW |
1848 | [(parallel |
1849 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1850 | (match_operand:BLK 1 "memory_operand" "")) | |
1851 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 1852 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
1853 | (clobber (match_dup 3))])] |
1854 | "" | |
1855 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 1856 | |
70128ad9 | 1857 | (define_insn "*movmem_short" |
9bb86f41 UW |
1858 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q") |
1859 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q")) | |
1860 | (use (match_operand 2 "nonmemory_operand" "n,a,a")) | |
1861 | (use (match_operand 3 "immediate_operand" "X,R,X")) | |
1862 | (clobber (match_scratch 4 "=X,X,&a"))] | |
b9404c99 | 1863 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
9bb86f41 UW |
1864 | && GET_MODE (operands[4]) == Pmode" |
1865 | "#" | |
b628bd8e | 1866 | [(set_attr "type" "cs")]) |
ecbe845e | 1867 | |
9bb86f41 UW |
1868 | (define_split |
1869 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1870 | (match_operand:BLK 1 "memory_operand" "")) | |
1871 | (use (match_operand 2 "const_int_operand" "")) | |
1872 | (use (match_operand 3 "immediate_operand" "")) | |
1873 | (clobber (scratch))] | |
1874 | "reload_completed" | |
1875 | [(parallel | |
1876 | [(set (match_dup 0) (match_dup 1)) | |
1877 | (use (match_dup 2))])] | |
1878 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 1879 | |
9bb86f41 UW |
1880 | (define_split |
1881 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1882 | (match_operand:BLK 1 "memory_operand" "")) | |
1883 | (use (match_operand 2 "register_operand" "")) | |
1884 | (use (match_operand 3 "memory_operand" "")) | |
1885 | (clobber (scratch))] | |
1886 | "reload_completed" | |
1887 | [(parallel | |
1888 | [(unspec [(match_dup 2) (match_dup 3) | |
1889 | (const_int 0)] UNSPEC_EXECUTE) | |
1890 | (set (match_dup 0) (match_dup 1)) | |
1891 | (use (const_int 1))])] | |
1892 | "") | |
1893 | ||
1894 | (define_split | |
1895 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1896 | (match_operand:BLK 1 "memory_operand" "")) | |
1897 | (use (match_operand 2 "register_operand" "")) | |
1898 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
1899 | (clobber (match_operand 3 "register_operand" ""))] | |
1900 | "reload_completed && TARGET_CPU_ZARCH" | |
1901 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
1902 | (parallel | |
1903 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) | |
1904 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
1905 | (set (match_dup 0) (match_dup 1)) | |
1906 | (use (const_int 1))])] | |
1907 | "operands[4] = gen_label_rtx ();") | |
1908 | ||
a41c6c53 | 1909 | ; Move a block of arbitrary length. |
9db1d521 | 1910 | |
70128ad9 | 1911 | (define_expand "movmem_long" |
b9404c99 UW |
1912 | [(parallel |
1913 | [(clobber (match_dup 2)) | |
1914 | (clobber (match_dup 3)) | |
1915 | (set (match_operand:BLK 0 "memory_operand" "") | |
1916 | (match_operand:BLK 1 "memory_operand" "")) | |
1917 | (use (match_operand 2 "general_operand" "")) | |
1918 | (use (match_dup 3)) | |
1919 | (clobber (reg:CC 33))])] | |
1920 | "" | |
1921 | { | |
1922 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
1923 | rtx reg0 = gen_reg_rtx (dword_mode); | |
1924 | rtx reg1 = gen_reg_rtx (dword_mode); | |
1925 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
1926 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
1927 | rtx len0 = gen_lowpart (Pmode, reg0); | |
1928 | rtx len1 = gen_lowpart (Pmode, reg1); | |
1929 | ||
1930 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
1931 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
1932 | emit_move_insn (len0, operands[2]); | |
1933 | ||
1934 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
1935 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
1936 | emit_move_insn (len1, operands[2]); | |
1937 | ||
1938 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
1939 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
1940 | operands[2] = reg0; | |
1941 | operands[3] = reg1; | |
1942 | }) | |
1943 | ||
70128ad9 | 1944 | (define_insn "*movmem_long_64" |
b9404c99 UW |
1945 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
1946 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
1947 | (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
1948 | (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))) | |
1949 | (use (match_dup 2)) | |
1950 | (use (match_dup 3)) | |
9db1d521 | 1951 | (clobber (reg:CC 33))] |
9f37ccb1 | 1952 | "TARGET_64BIT" |
d40c829f | 1953 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
1954 | [(set_attr "length" "8") |
1955 | (set_attr "type" "vs")]) | |
9db1d521 | 1956 | |
70128ad9 | 1957 | (define_insn "*movmem_long_31" |
b9404c99 UW |
1958 | [(clobber (match_operand:DI 0 "register_operand" "=d")) |
1959 | (clobber (match_operand:DI 1 "register_operand" "=d")) | |
1960 | (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
1961 | (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))) | |
1962 | (use (match_dup 2)) | |
1963 | (use (match_dup 3)) | |
9db1d521 | 1964 | (clobber (reg:CC 33))] |
9f37ccb1 | 1965 | "!TARGET_64BIT" |
d40c829f | 1966 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
1967 | [(set_attr "length" "8") |
1968 | (set_attr "type" "vs")]) | |
9db1d521 HP |
1969 | |
1970 | ; | |
70128ad9 | 1971 | ; clrmemM instruction pattern(s). |
9db1d521 HP |
1972 | ; |
1973 | ||
70128ad9 | 1974 | (define_expand "clrmemdi" |
a41c6c53 | 1975 | [(set (match_operand:BLK 0 "memory_operand" "") |
9db1d521 HP |
1976 | (const_int 0)) |
1977 | (use (match_operand:DI 1 "general_operand" "")) | |
1978 | (match_operand 2 "" "")] | |
1979 | "TARGET_64BIT" | |
70128ad9 | 1980 | "s390_expand_clrmem (operands[0], operands[1]); DONE;") |
9db1d521 | 1981 | |
70128ad9 | 1982 | (define_expand "clrmemsi" |
a41c6c53 | 1983 | [(set (match_operand:BLK 0 "memory_operand" "") |
9db1d521 HP |
1984 | (const_int 0)) |
1985 | (use (match_operand:SI 1 "general_operand" "")) | |
1986 | (match_operand 2 "" "")] | |
a41c6c53 | 1987 | "" |
70128ad9 | 1988 | "s390_expand_clrmem (operands[0], operands[1]); DONE;") |
9db1d521 | 1989 | |
a41c6c53 | 1990 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
1991 | ; The block length is taken as (operands[1] % 256) + 1. |
1992 | ||
70128ad9 | 1993 | (define_expand "clrmem_short" |
b9404c99 UW |
1994 | [(parallel |
1995 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1996 | (const_int 0)) | |
1997 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 1998 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
1999 | (clobber (match_dup 2)) |
2000 | (clobber (reg:CC 33))])] | |
2001 | "" | |
2002 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2003 | |
70128ad9 | 2004 | (define_insn "*clrmem_short" |
9bb86f41 | 2005 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q") |
a41c6c53 | 2006 | (const_int 0)) |
9bb86f41 UW |
2007 | (use (match_operand 1 "nonmemory_operand" "n,a,a")) |
2008 | (use (match_operand 2 "immediate_operand" "X,R,X")) | |
2009 | (clobber (match_scratch 3 "=X,X,&a")) | |
a41c6c53 | 2010 | (clobber (reg:CC 33))] |
b9404c99 | 2011 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode) |
9bb86f41 UW |
2012 | && GET_MODE (operands[3]) == Pmode" |
2013 | "#" | |
b628bd8e | 2014 | [(set_attr "type" "cs")]) |
9bb86f41 UW |
2015 | |
2016 | (define_split | |
2017 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2018 | (const_int 0)) | |
2019 | (use (match_operand 1 "const_int_operand" "")) | |
2020 | (use (match_operand 2 "immediate_operand" "")) | |
2021 | (clobber (scratch)) | |
2022 | (clobber (reg:CC 33))] | |
2023 | "reload_completed" | |
2024 | [(parallel | |
2025 | [(set (match_dup 0) (const_int 0)) | |
2026 | (use (match_dup 1)) | |
2027 | (clobber (reg:CC 33))])] | |
2028 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") | |
9db1d521 | 2029 | |
9bb86f41 UW |
2030 | (define_split |
2031 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2032 | (const_int 0)) | |
2033 | (use (match_operand 1 "register_operand" "")) | |
2034 | (use (match_operand 2 "memory_operand" "")) | |
2035 | (clobber (scratch)) | |
2036 | (clobber (reg:CC 33))] | |
2037 | "reload_completed" | |
2038 | [(parallel | |
2039 | [(unspec [(match_dup 1) (match_dup 2) | |
2040 | (const_int 0)] UNSPEC_EXECUTE) | |
2041 | (set (match_dup 0) (const_int 0)) | |
2042 | (use (const_int 1)) | |
2043 | (clobber (reg:CC 33))])] | |
2044 | "") | |
9db1d521 | 2045 | |
9bb86f41 UW |
2046 | (define_split |
2047 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2048 | (const_int 0)) | |
2049 | (use (match_operand 1 "register_operand" "")) | |
2050 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2051 | (clobber (match_operand 2 "register_operand" "")) | |
2052 | (clobber (reg:CC 33))] | |
2053 | "reload_completed && TARGET_CPU_ZARCH" | |
2054 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
2055 | (parallel | |
2056 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) | |
2057 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2058 | (set (match_dup 0) (const_int 0)) | |
2059 | (use (const_int 1)) | |
2060 | (clobber (reg:CC 33))])] | |
2061 | "operands[3] = gen_label_rtx ();") | |
2062 | ||
b9404c99 UW |
2063 | ; Clear a block of arbitrary length. |
2064 | ||
70128ad9 | 2065 | (define_expand "clrmem_long" |
b9404c99 UW |
2066 | [(parallel |
2067 | [(clobber (match_dup 1)) | |
2068 | (set (match_operand:BLK 0 "memory_operand" "") | |
2069 | (const_int 0)) | |
2070 | (use (match_operand 1 "general_operand" "")) | |
2071 | (use (match_dup 2)) | |
2072 | (clobber (reg:CC 33))])] | |
2073 | "" | |
a41c6c53 | 2074 | { |
b9404c99 UW |
2075 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; |
2076 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2077 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2078 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2079 | rtx len0 = gen_lowpart (Pmode, reg0); | |
9db1d521 | 2080 | |
b9404c99 UW |
2081 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); |
2082 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2083 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 2084 | |
b9404c99 | 2085 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 2086 | |
b9404c99 UW |
2087 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
2088 | operands[1] = reg0; | |
2089 | operands[2] = reg1; | |
2090 | }) | |
a41c6c53 | 2091 | |
70128ad9 | 2092 | (define_insn "*clrmem_long_64" |
b9404c99 UW |
2093 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
2094 | (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
9db1d521 | 2095 | (const_int 0)) |
b9404c99 | 2096 | (use (match_dup 2)) |
9f37ccb1 | 2097 | (use (match_operand:TI 1 "register_operand" "d")) |
9db1d521 HP |
2098 | (clobber (reg:CC 33))] |
2099 | "TARGET_64BIT" | |
d40c829f | 2100 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2101 | [(set_attr "length" "8") |
2102 | (set_attr "type" "vs")]) | |
9db1d521 | 2103 | |
70128ad9 | 2104 | (define_insn "*clrmem_long_31" |
b9404c99 UW |
2105 | [(clobber (match_operand:DI 0 "register_operand" "=d")) |
2106 | (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
9db1d521 | 2107 | (const_int 0)) |
b9404c99 | 2108 | (use (match_dup 2)) |
9f37ccb1 | 2109 | (use (match_operand:DI 1 "register_operand" "d")) |
9db1d521 HP |
2110 | (clobber (reg:CC 33))] |
2111 | "!TARGET_64BIT" | |
d40c829f | 2112 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2113 | [(set_attr "length" "8") |
2114 | (set_attr "type" "vs")]) | |
9db1d521 HP |
2115 | |
2116 | ; | |
358b8f01 | 2117 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
2118 | ; |
2119 | ||
358b8f01 | 2120 | (define_expand "cmpmemsi" |
a41c6c53 UW |
2121 | [(set (match_operand:SI 0 "register_operand" "") |
2122 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
2123 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
2124 | (use (match_operand:SI 3 "general_operand" "")) | |
2125 | (use (match_operand:SI 4 "" ""))] | |
2126 | "" | |
c7453384 | 2127 | "s390_expand_cmpmem (operands[0], operands[1], |
a41c6c53 | 2128 | operands[2], operands[3]); DONE;") |
9db1d521 | 2129 | |
a41c6c53 UW |
2130 | ; Compare a block that is up to 256 bytes in length. |
2131 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2132 | |
b9404c99 UW |
2133 | (define_expand "cmpmem_short" |
2134 | [(parallel | |
5b022de5 UW |
2135 | [(set (reg:CCU 33) |
2136 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
b9404c99 UW |
2137 | (match_operand:BLK 1 "memory_operand" ""))) |
2138 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2139 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2140 | (clobber (match_dup 3))])] |
2141 | "" | |
2142 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2143 | |
b9404c99 | 2144 | (define_insn "*cmpmem_short" |
5b022de5 | 2145 | [(set (reg:CCU 33) |
d4f52f0e | 2146 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q") |
9bb86f41 UW |
2147 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))) |
2148 | (use (match_operand 2 "nonmemory_operand" "n,a,a")) | |
2149 | (use (match_operand 3 "immediate_operand" "X,R,X")) | |
2150 | (clobber (match_scratch 4 "=X,X,&a"))] | |
b9404c99 | 2151 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
9bb86f41 UW |
2152 | && GET_MODE (operands[4]) == Pmode" |
2153 | "#" | |
b628bd8e | 2154 | [(set_attr "type" "cs")]) |
9db1d521 | 2155 | |
9bb86f41 UW |
2156 | (define_split |
2157 | [(set (reg:CCU 33) | |
2158 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
2159 | (match_operand:BLK 1 "memory_operand" ""))) | |
2160 | (use (match_operand 2 "const_int_operand" "")) | |
2161 | (use (match_operand 3 "immediate_operand" "")) | |
2162 | (clobber (scratch))] | |
2163 | "reload_completed" | |
2164 | [(parallel | |
2165 | [(set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1))) | |
2166 | (use (match_dup 2))])] | |
2167 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 2168 | |
9bb86f41 UW |
2169 | (define_split |
2170 | [(set (reg:CCU 33) | |
2171 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
2172 | (match_operand:BLK 1 "memory_operand" ""))) | |
2173 | (use (match_operand 2 "register_operand" "")) | |
2174 | (use (match_operand 3 "memory_operand" "")) | |
2175 | (clobber (scratch))] | |
2176 | "reload_completed" | |
2177 | [(parallel | |
2178 | [(unspec [(match_dup 2) (match_dup 3) | |
2179 | (const_int 0)] UNSPEC_EXECUTE) | |
2180 | (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1))) | |
2181 | (use (const_int 1))])] | |
2182 | "") | |
2183 | ||
2184 | (define_split | |
2185 | [(set (reg:CCU 33) | |
2186 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
2187 | (match_operand:BLK 1 "memory_operand" ""))) | |
2188 | (use (match_operand 2 "register_operand" "")) | |
2189 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2190 | (clobber (match_operand 3 "register_operand" ""))] | |
2191 | "reload_completed && TARGET_CPU_ZARCH" | |
2192 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
2193 | (parallel | |
2194 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) | |
2195 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
2196 | (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1))) | |
2197 | (use (const_int 1))])] | |
2198 | "operands[4] = gen_label_rtx ();") | |
2199 | ||
a41c6c53 | 2200 | ; Compare a block of arbitrary length. |
9db1d521 | 2201 | |
b9404c99 UW |
2202 | (define_expand "cmpmem_long" |
2203 | [(parallel | |
2204 | [(clobber (match_dup 2)) | |
2205 | (clobber (match_dup 3)) | |
5b022de5 UW |
2206 | (set (reg:CCU 33) |
2207 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
b9404c99 UW |
2208 | (match_operand:BLK 1 "memory_operand" ""))) |
2209 | (use (match_operand 2 "general_operand" "")) | |
2210 | (use (match_dup 3))])] | |
2211 | "" | |
2212 | { | |
2213 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
2214 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2215 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2216 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2217 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
2218 | rtx len0 = gen_lowpart (Pmode, reg0); | |
2219 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2220 | ||
2221 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
2222 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2223 | emit_move_insn (len0, operands[2]); | |
2224 | ||
2225 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
2226 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2227 | emit_move_insn (len1, operands[2]); | |
2228 | ||
2229 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2230 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2231 | operands[2] = reg0; | |
2232 | operands[3] = reg1; | |
2233 | }) | |
2234 | ||
2235 | (define_insn "*cmpmem_long_64" | |
4023fb28 UW |
2236 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
2237 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
5b022de5 UW |
2238 | (set (reg:CCU 33) |
2239 | (compare:CCU (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
f8766020 HP |
2240 | (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))) |
2241 | (use (match_dup 2)) | |
2242 | (use (match_dup 3))] | |
9db1d521 | 2243 | "TARGET_64BIT" |
287ff198 | 2244 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2245 | [(set_attr "length" "8") |
2246 | (set_attr "type" "vs")]) | |
9db1d521 | 2247 | |
b9404c99 | 2248 | (define_insn "*cmpmem_long_31" |
4023fb28 UW |
2249 | [(clobber (match_operand:DI 0 "register_operand" "=d")) |
2250 | (clobber (match_operand:DI 1 "register_operand" "=d")) | |
5b022de5 UW |
2251 | (set (reg:CCU 33) |
2252 | (compare:CCU (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
f8766020 HP |
2253 | (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))) |
2254 | (use (match_dup 2)) | |
2255 | (use (match_dup 3))] | |
9db1d521 | 2256 | "!TARGET_64BIT" |
287ff198 | 2257 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2258 | [(set_attr "length" "8") |
2259 | (set_attr "type" "vs")]) | |
9db1d521 | 2260 | |
02887425 UW |
2261 | ; Convert CCUmode condition code to integer. |
2262 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 2263 | |
02887425 | 2264 | (define_insn_and_split "cmpint" |
9db1d521 | 2265 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 UW |
2266 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
2267 | UNSPEC_CMPINT)) | |
2268 | (clobber (reg:CC 33))] | |
9db1d521 | 2269 | "" |
02887425 UW |
2270 | "#" |
2271 | "reload_completed" | |
2272 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
2273 | (parallel | |
2274 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
2275 | (clobber (reg:CC 33))])]) | |
2276 | ||
2277 | (define_insn_and_split "*cmpint_cc" | |
2278 | [(set (reg 33) | |
2279 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] | |
2280 | UNSPEC_CMPINT) | |
2281 | (const_int 0))) | |
2282 | (set (match_operand:SI 0 "register_operand" "=d") | |
2283 | (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))] | |
2284 | "s390_match_ccmode (insn, CCSmode)" | |
2285 | "#" | |
2286 | "&& reload_completed" | |
2287 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
2288 | (parallel | |
2289 | [(set (match_dup 2) (match_dup 3)) | |
2290 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 2291 | { |
02887425 UW |
2292 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
2293 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
2294 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
2295 | }) | |
9db1d521 | 2296 | |
02887425 | 2297 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 2298 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 UW |
2299 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
2300 | UNSPEC_CMPINT))) | |
2301 | (clobber (reg:CC 33))] | |
9db1d521 | 2302 | "TARGET_64BIT" |
02887425 UW |
2303 | "#" |
2304 | "&& reload_completed" | |
2305 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
2306 | (parallel | |
2307 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
2308 | (clobber (reg:CC 33))])]) | |
2309 | ||
2310 | (define_insn_and_split "*cmpint_sign_cc" | |
2311 | [(set (reg 33) | |
2312 | (compare (ashiftrt:DI (ashift:DI (subreg:DI | |
2313 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] | |
2314 | UNSPEC_CMPINT) 0) | |
2315 | (const_int 32)) (const_int 32)) | |
2316 | (const_int 0))) | |
2317 | (set (match_operand:DI 0 "register_operand" "=d") | |
2318 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))] | |
2319 | "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT" | |
2320 | "#" | |
2321 | "&& reload_completed" | |
2322 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
2323 | (parallel | |
2324 | [(set (match_dup 2) (match_dup 3)) | |
2325 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 2326 | { |
02887425 UW |
2327 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
2328 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
2329 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
2330 | }) | |
9db1d521 | 2331 | |
4023fb28 | 2332 | |
9db1d521 HP |
2333 | ;; |
2334 | ;;- Conversion instructions. | |
2335 | ;; | |
2336 | ||
4023fb28 | 2337 | (define_insn "*sethighqisi" |
d3632d41 | 2338 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
10bbf137 | 2339 | (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2340 | (clobber (reg:CC 33))] |
2341 | "" | |
d3632d41 | 2342 | "@ |
fc0ea003 UW |
2343 | icm\t%0,8,%S1 |
2344 | icmy\t%0,8,%S1" | |
d3632d41 | 2345 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 UW |
2346 | |
2347 | (define_insn "*sethighhisi" | |
d3632d41 | 2348 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
10bbf137 | 2349 | (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2350 | (clobber (reg:CC 33))] |
2351 | "" | |
d3632d41 | 2352 | "@ |
fc0ea003 UW |
2353 | icm\t%0,12,%S1 |
2354 | icmy\t%0,12,%S1" | |
d3632d41 | 2355 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 UW |
2356 | |
2357 | (define_insn "*sethighqidi_64" | |
2358 | [(set (match_operand:DI 0 "register_operand" "=d") | |
10bbf137 | 2359 | (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2360 | (clobber (reg:CC 33))] |
2361 | "TARGET_64BIT" | |
fc0ea003 | 2362 | "icmh\t%0,8,%S1" |
d3632d41 | 2363 | [(set_attr "op_type" "RSY")]) |
4023fb28 UW |
2364 | |
2365 | (define_insn "*sethighqidi_31" | |
d3632d41 | 2366 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
10bbf137 | 2367 | (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2368 | (clobber (reg:CC 33))] |
2369 | "!TARGET_64BIT" | |
d3632d41 | 2370 | "@ |
fc0ea003 UW |
2371 | icm\t%0,8,%S1 |
2372 | icmy\t%0,8,%S1" | |
d3632d41 | 2373 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 | 2374 | |
cc7ab9b7 UW |
2375 | (define_insn_and_split "*extractqi" |
2376 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2377 | (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") | |
2378 | (match_operand 2 "const_int_operand" "n") | |
2379 | (const_int 0))) | |
2380 | (clobber (reg:CC 33))] | |
2381 | "!TARGET_64BIT | |
4023fb28 | 2382 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8" |
cc7ab9b7 UW |
2383 | "#" |
2384 | "&& reload_completed" | |
4023fb28 | 2385 | [(parallel |
10bbf137 | 2386 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2387 | (clobber (reg:CC 33))]) |
2388 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] | |
4023fb28 UW |
2389 | { |
2390 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
2391 | operands[1] = change_address (operands[1], QImode, 0); | |
b628bd8e | 2392 | }) |
4023fb28 | 2393 | |
cc7ab9b7 UW |
2394 | (define_insn_and_split "*extracthi" |
2395 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2396 | (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") | |
2397 | (match_operand 2 "const_int_operand" "n") | |
2398 | (const_int 0))) | |
2399 | (clobber (reg:CC 33))] | |
2400 | "!TARGET_64BIT | |
4023fb28 | 2401 | && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16" |
cc7ab9b7 UW |
2402 | "#" |
2403 | "&& reload_completed" | |
4023fb28 | 2404 | [(parallel |
10bbf137 | 2405 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2406 | (clobber (reg:CC 33))]) |
2407 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] | |
4023fb28 UW |
2408 | { |
2409 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
2410 | operands[1] = change_address (operands[1], HImode, 0); | |
b628bd8e | 2411 | }) |
4023fb28 | 2412 | |
9db1d521 HP |
2413 | ; |
2414 | ; extendsidi2 instruction pattern(s). | |
2415 | ; | |
2416 | ||
4023fb28 UW |
2417 | (define_expand "extendsidi2" |
2418 | [(set (match_operand:DI 0 "register_operand" "") | |
2419 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2420 | "" | |
2421 | " | |
2422 | { | |
2423 | if (!TARGET_64BIT) | |
2424 | { | |
9f37ccb1 UW |
2425 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2426 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); | |
2427 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
2428 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
2429 | DONE; |
2430 | } | |
2431 | } | |
2432 | ") | |
2433 | ||
2434 | (define_insn "*extendsidi2" | |
9db1d521 HP |
2435 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2436 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2437 | "TARGET_64BIT" | |
2438 | "@ | |
d40c829f UW |
2439 | lgfr\t%0,%1 |
2440 | lgf\t%0,%1" | |
d3632d41 | 2441 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2442 | |
9db1d521 HP |
2443 | ; |
2444 | ; extendhidi2 instruction pattern(s). | |
2445 | ; | |
2446 | ||
4023fb28 UW |
2447 | (define_expand "extendhidi2" |
2448 | [(set (match_operand:DI 0 "register_operand" "") | |
2449 | (sign_extend:DI (match_operand:HI 1 "register_operand" "")))] | |
2450 | "" | |
2451 | " | |
2452 | { | |
2453 | if (!TARGET_64BIT) | |
2454 | { | |
2455 | rtx tmp = gen_reg_rtx (SImode); | |
2456 | emit_insn (gen_extendhisi2 (tmp, operands[1])); | |
2457 | emit_insn (gen_extendsidi2 (operands[0], tmp)); | |
2458 | DONE; | |
2459 | } | |
2460 | else | |
2461 | { | |
2462 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2463 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); | |
c7453384 | 2464 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48))); |
4023fb28 UW |
2465 | DONE; |
2466 | } | |
2467 | } | |
2468 | ") | |
2469 | ||
2470 | (define_insn "*extendhidi2" | |
9db1d521 | 2471 | [(set (match_operand:DI 0 "register_operand" "=d") |
4023fb28 | 2472 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] |
9db1d521 | 2473 | "TARGET_64BIT" |
d40c829f | 2474 | "lgh\t%0,%1" |
d3632d41 | 2475 | [(set_attr "op_type" "RXY")]) |
9db1d521 HP |
2476 | |
2477 | ; | |
2478 | ; extendqidi2 instruction pattern(s). | |
2479 | ; | |
2480 | ||
4023fb28 UW |
2481 | (define_expand "extendqidi2" |
2482 | [(set (match_operand:DI 0 "register_operand" "") | |
2483 | (sign_extend:DI (match_operand:QI 1 "register_operand" "")))] | |
2484 | "" | |
2485 | " | |
2486 | { | |
2487 | if (!TARGET_64BIT) | |
2488 | { | |
2489 | rtx tmp = gen_reg_rtx (SImode); | |
2490 | emit_insn (gen_extendqisi2 (tmp, operands[1])); | |
2491 | emit_insn (gen_extendsidi2 (operands[0], tmp)); | |
2492 | DONE; | |
2493 | } | |
2494 | else | |
2495 | { | |
2496 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2497 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); | |
c7453384 | 2498 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56))); |
4023fb28 UW |
2499 | DONE; |
2500 | } | |
2501 | } | |
2502 | ") | |
2503 | ||
d3632d41 UW |
2504 | (define_insn "*extendqidi2" |
2505 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2506 | (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))] | |
2507 | "TARGET_64BIT && TARGET_LONG_DISPLACEMENT" | |
d40c829f | 2508 | "lgb\t%0,%1" |
d3632d41 UW |
2509 | [(set_attr "op_type" "RXY")]) |
2510 | ||
19796784 AK |
2511 | (define_insn_and_split "*extendqidi2_short_displ" |
2512 | [(set (match_operand:DI 0 "register_operand" "=d") | |
59f8a8be UW |
2513 | (sign_extend:DI (match_operand:QI 1 "s_operand" "Q"))) |
2514 | (clobber (reg:CC 33))] | |
19796784 AK |
2515 | "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT" |
2516 | "#" | |
2517 | "&& reload_completed" | |
4023fb28 | 2518 | [(parallel |
10bbf137 | 2519 | [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2520 | (clobber (reg:CC 33))]) |
2521 | (parallel | |
2522 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56))) | |
2523 | (clobber (reg:CC 33))])] | |
2524 | "") | |
9db1d521 HP |
2525 | |
2526 | ; | |
2527 | ; extendhisi2 instruction pattern(s). | |
2528 | ; | |
2529 | ||
4023fb28 UW |
2530 | (define_expand "extendhisi2" |
2531 | [(set (match_operand:SI 0 "register_operand" "") | |
2532 | (sign_extend:SI (match_operand:HI 1 "register_operand" "")))] | |
9db1d521 | 2533 | "" |
4023fb28 UW |
2534 | " |
2535 | { | |
2536 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2537 | emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16))); | |
c7453384 | 2538 | emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16))); |
4023fb28 UW |
2539 | DONE; |
2540 | } | |
2541 | ") | |
9db1d521 | 2542 | |
4023fb28 | 2543 | (define_insn "*extendhisi2" |
d3632d41 UW |
2544 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
2545 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
4023fb28 | 2546 | "" |
d3632d41 | 2547 | "@ |
d40c829f UW |
2548 | lh\t%0,%1 |
2549 | lhy\t%0,%1" | |
d3632d41 | 2550 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 HP |
2551 | |
2552 | ; | |
2553 | ; extendqisi2 instruction pattern(s). | |
2554 | ; | |
2555 | ||
4023fb28 UW |
2556 | (define_expand "extendqisi2" |
2557 | [(set (match_operand:SI 0 "register_operand" "") | |
2558 | (sign_extend:SI (match_operand:QI 1 "register_operand" "")))] | |
9db1d521 | 2559 | "" |
4023fb28 UW |
2560 | " |
2561 | { | |
2562 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2563 | emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24))); | |
c7453384 | 2564 | emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24))); |
4023fb28 UW |
2565 | DONE; |
2566 | } | |
2567 | ") | |
9db1d521 | 2568 | |
d3632d41 UW |
2569 | (define_insn "*extendqisi2" |
2570 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2571 | (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2572 | "TARGET_LONG_DISPLACEMENT" |
d40c829f | 2573 | "lb\t%0,%1" |
d3632d41 UW |
2574 | [(set_attr "op_type" "RXY")]) |
2575 | ||
eb457a7a | 2576 | (define_insn_and_split "*extendqisi2_short_displ" |
19796784 | 2577 | [(set (match_operand:SI 0 "register_operand" "=d") |
59f8a8be UW |
2578 | (sign_extend:SI (match_operand:QI 1 "s_operand" "Q"))) |
2579 | (clobber (reg:CC 33))] | |
19796784 AK |
2580 | "!TARGET_LONG_DISPLACEMENT" |
2581 | "#" | |
2582 | "&& reload_completed" | |
4023fb28 | 2583 | [(parallel |
10bbf137 | 2584 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2585 | (clobber (reg:CC 33))]) |
2586 | (parallel | |
2587 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24))) | |
2588 | (clobber (reg:CC 33))])] | |
2589 | "") | |
9db1d521 HP |
2590 | |
2591 | ; | |
2592 | ; extendqihi2 instruction pattern(s). | |
2593 | ; | |
2594 | ||
9db1d521 HP |
2595 | |
2596 | ; | |
2597 | ; zero_extendsidi2 instruction pattern(s). | |
2598 | ; | |
2599 | ||
4023fb28 UW |
2600 | (define_expand "zero_extendsidi2" |
2601 | [(set (match_operand:DI 0 "register_operand" "") | |
2602 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2603 | "" | |
2604 | " | |
2605 | { | |
2606 | if (!TARGET_64BIT) | |
2607 | { | |
9f37ccb1 UW |
2608 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2609 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); | |
2610 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
2611 | DONE; |
2612 | } | |
2613 | } | |
2614 | ") | |
2615 | ||
2616 | (define_insn "*zero_extendsidi2" | |
9db1d521 HP |
2617 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2618 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2619 | "TARGET_64BIT" | |
2620 | "@ | |
d40c829f UW |
2621 | llgfr\t%0,%1 |
2622 | llgf\t%0,%1" | |
d3632d41 | 2623 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2624 | |
9db1d521 HP |
2625 | ; |
2626 | ; zero_extendhidi2 instruction pattern(s). | |
2627 | ; | |
2628 | ||
4023fb28 UW |
2629 | (define_expand "zero_extendhidi2" |
2630 | [(set (match_operand:DI 0 "register_operand" "") | |
2631 | (zero_extend:DI (match_operand:HI 1 "register_operand" "")))] | |
2632 | "" | |
2633 | " | |
2634 | { | |
2635 | if (!TARGET_64BIT) | |
2636 | { | |
2637 | rtx tmp = gen_reg_rtx (SImode); | |
2638 | emit_insn (gen_zero_extendhisi2 (tmp, operands[1])); | |
2639 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
2640 | DONE; | |
2641 | } | |
2642 | else | |
2643 | { | |
2644 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2645 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); | |
c7453384 | 2646 | emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48))); |
4023fb28 UW |
2647 | DONE; |
2648 | } | |
2649 | } | |
2650 | ") | |
9db1d521 | 2651 | |
4023fb28 UW |
2652 | (define_insn "*zero_extendhidi2" |
2653 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2654 | (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))] | |
9db1d521 | 2655 | "TARGET_64BIT" |
d40c829f | 2656 | "llgh\t%0,%1" |
d3632d41 | 2657 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2658 | |
288e517f AK |
2659 | ; |
2660 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
2661 | ; | |
2662 | ||
2663 | (define_insn "*llgt_sisi" | |
2664 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
2665 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m") | |
2666 | (const_int 2147483647)))] | |
2667 | "TARGET_64BIT" | |
2668 | "@ | |
2669 | llgtr\t%0,%1 | |
2670 | llgt\t%0,%1" | |
2671 | [(set_attr "op_type" "RRE,RXE")]) | |
2672 | ||
f19a9af7 AK |
2673 | (define_split |
2674 | [(set (match_operand:SI 0 "register_operand" "") | |
2675 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
288e517f AK |
2676 | (const_int 2147483647))) |
2677 | (clobber (reg:CC 33))] | |
f19a9af7 | 2678 | "TARGET_64BIT && reload_completed" |
288e517f AK |
2679 | [(set (match_dup 0) |
2680 | (and:SI (match_dup 1) | |
2681 | (const_int 2147483647)))] | |
2682 | "") | |
2683 | ||
2684 | (define_insn "*llgt_didi" | |
2685 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2686 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
2687 | (const_int 2147483647)))] | |
2688 | "TARGET_64BIT" | |
2689 | "@ | |
2690 | llgtr\t%0,%1 | |
2691 | llgt\t%0,%N1" | |
2692 | [(set_attr "op_type" "RRE,RXE")]) | |
2693 | ||
f19a9af7 AK |
2694 | (define_split |
2695 | [(set (match_operand:DI 0 "register_operand" "") | |
2696 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
288e517f AK |
2697 | (const_int 2147483647))) |
2698 | (clobber (reg:CC 33))] | |
f19a9af7 | 2699 | "TARGET_64BIT && reload_completed" |
288e517f AK |
2700 | [(set (match_dup 0) |
2701 | (and:DI (match_dup 1) | |
2702 | (const_int 2147483647)))] | |
2703 | "") | |
2704 | ||
2705 | (define_insn "*llgt_sidi" | |
2706 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2707 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) | |
2708 | (const_int 2147483647)))] | |
2709 | "TARGET_64BIT" | |
2710 | "llgt\t%0,%1" | |
2711 | [(set_attr "op_type" "RXE")]) | |
2712 | ||
2713 | (define_insn_and_split "*llgt_sidi_split" | |
2714 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2f7e5a0d | 2715 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) |
288e517f AK |
2716 | (const_int 2147483647))) |
2717 | (clobber (reg:CC 33))] | |
2718 | "TARGET_64BIT" | |
2719 | "#" | |
2720 | "&& reload_completed" | |
2721 | [(set (match_dup 0) | |
2f7e5a0d | 2722 | (and:DI (subreg:DI (match_dup 1) 0) |
288e517f AK |
2723 | (const_int 2147483647)))] |
2724 | "") | |
2725 | ||
9db1d521 | 2726 | ; |
4023fb28 | 2727 | ; zero_extendqidi2 instruction pattern(s) |
9db1d521 HP |
2728 | ; |
2729 | ||
4023fb28 UW |
2730 | (define_expand "zero_extendqidi2" |
2731 | [(set (match_operand:DI 0 "register_operand" "") | |
2732 | (zero_extend:DI (match_operand:QI 1 "register_operand" "")))] | |
9db1d521 HP |
2733 | "" |
2734 | " | |
2735 | { | |
2736 | if (!TARGET_64BIT) | |
2737 | { | |
4023fb28 UW |
2738 | rtx tmp = gen_reg_rtx (SImode); |
2739 | emit_insn (gen_zero_extendqisi2 (tmp, operands[1])); | |
2740 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
9db1d521 HP |
2741 | DONE; |
2742 | } | |
4023fb28 UW |
2743 | else |
2744 | { | |
2745 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2746 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); | |
c7453384 | 2747 | emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56))); |
4023fb28 UW |
2748 | DONE; |
2749 | } | |
2750 | } | |
2751 | ") | |
9db1d521 | 2752 | |
4023fb28 UW |
2753 | (define_insn "*zero_extendqidi2" |
2754 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2755 | (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))] | |
9db1d521 | 2756 | "TARGET_64BIT" |
d40c829f | 2757 | "llgc\t%0,%1" |
d3632d41 | 2758 | [(set_attr "op_type" "RXY")]) |
9db1d521 HP |
2759 | |
2760 | ; | |
4023fb28 | 2761 | ; zero_extendhisi2 instruction pattern(s). |
9db1d521 HP |
2762 | ; |
2763 | ||
4023fb28 UW |
2764 | (define_expand "zero_extendhisi2" |
2765 | [(set (match_operand:SI 0 "register_operand" "") | |
2766 | (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] | |
9db1d521 | 2767 | "" |
4023fb28 UW |
2768 | " |
2769 | { | |
2770 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2771 | emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff))); | |
2772 | DONE; | |
2773 | } | |
2774 | ") | |
9db1d521 | 2775 | |
4023fb28 | 2776 | (define_insn "*zero_extendhisi2_64" |
9db1d521 | 2777 | [(set (match_operand:SI 0 "register_operand" "=d") |
4023fb28 | 2778 | (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] |
f4f41b4e | 2779 | "TARGET_ZARCH" |
d40c829f | 2780 | "llgh\t%0,%1" |
d3632d41 | 2781 | [(set_attr "op_type" "RXY")]) |
cc7ab9b7 UW |
2782 | |
2783 | (define_insn_and_split "*zero_extendhisi2_31" | |
2784 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 2785 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
cc7ab9b7 | 2786 | (clobber (reg:CC 33))] |
f4f41b4e | 2787 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2788 | "#" |
2789 | "&& reload_completed" | |
2790 | [(set (match_dup 0) (const_int 0)) | |
2791 | (parallel | |
2792 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
2793 | (clobber (reg:CC 33))])] | |
b628bd8e | 2794 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 2795 | |
4023fb28 UW |
2796 | ; |
2797 | ; zero_extendqisi2 instruction pattern(s). | |
2798 | ; | |
9db1d521 HP |
2799 | |
2800 | (define_expand "zero_extendqisi2" | |
2801 | [(set (match_operand:SI 0 "register_operand" "") | |
4023fb28 | 2802 | (zero_extend:SI (match_operand:QI 1 "register_operand" "")))] |
9db1d521 HP |
2803 | "" |
2804 | " | |
2805 | { | |
4023fb28 UW |
2806 | operands[1] = gen_lowpart (SImode, operands[1]); |
2807 | emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff))); | |
2808 | DONE; | |
2809 | } | |
2810 | ") | |
9db1d521 | 2811 | |
4023fb28 UW |
2812 | (define_insn "*zero_extendqisi2_64" |
2813 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2814 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2815 | "TARGET_ZARCH" |
d40c829f | 2816 | "llgc\t%0,%1" |
d3632d41 | 2817 | [(set_attr "op_type" "RXY")]) |
cc7ab9b7 UW |
2818 | |
2819 | (define_insn_and_split "*zero_extendqisi2_31" | |
2820 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
2821 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2822 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2823 | "#" |
2824 | "&& reload_completed" | |
2825 | [(set (match_dup 0) (const_int 0)) | |
2826 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 2827 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 2828 | |
9db1d521 HP |
2829 | ; |
2830 | ; zero_extendqihi2 instruction pattern(s). | |
2831 | ; | |
2832 | ||
9db1d521 HP |
2833 | (define_expand "zero_extendqihi2" |
2834 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 2835 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
9e8327e3 | 2836 | "TARGET_ZARCH" |
9db1d521 HP |
2837 | " |
2838 | { | |
4023fb28 UW |
2839 | operands[1] = gen_lowpart (HImode, operands[1]); |
2840 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
2841 | DONE; | |
2842 | } | |
2843 | ") | |
9db1d521 | 2844 | |
4023fb28 | 2845 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 2846 | [(set (match_operand:HI 0 "register_operand" "=d") |
cc7ab9b7 | 2847 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] |
9e8327e3 | 2848 | "TARGET_ZARCH" |
d40c829f | 2849 | "llgc\t%0,%1" |
d3632d41 | 2850 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2851 | |
cc7ab9b7 UW |
2852 | (define_insn_and_split "*zero_extendqihi2_31" |
2853 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
2854 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2855 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2856 | "#" |
2857 | "&& reload_completed" | |
2858 | [(set (match_dup 0) (const_int 0)) | |
2859 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 2860 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 UW |
2861 | |
2862 | ||
9db1d521 HP |
2863 | ; |
2864 | ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s). | |
2865 | ; | |
2866 | ||
2867 | (define_expand "fixuns_truncdfdi2" | |
2868 | [(set (match_operand:DI 0 "register_operand" "") | |
2869 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))] | |
2870 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2871 | { |
2872 | rtx label1 = gen_label_rtx (); | |
2873 | rtx label2 = gen_label_rtx (); | |
2874 | rtx temp = gen_reg_rtx (DFmode); | |
2875 | operands[1] = force_reg (DFmode, operands[1]); | |
2876 | ||
c7453384 | 2877 | emit_insn (gen_cmpdf (operands[1], |
4023fb28 | 2878 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 2879 | REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode))); |
9db1d521 | 2880 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
2881 | emit_insn (gen_subdf3 (temp, operands[1], |
2882 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2883 | REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode))); |
9db1d521 | 2884 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7))); |
f314b9b1 | 2885 | emit_jump (label2); |
9db1d521 HP |
2886 | |
2887 | emit_label (label1); | |
2888 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2889 | emit_label (label2); | |
2890 | DONE; | |
10bbf137 | 2891 | }) |
9db1d521 HP |
2892 | |
2893 | (define_expand "fix_truncdfdi2" | |
2894 | [(set (match_operand:DI 0 "register_operand" "") | |
2895 | (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
2896 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2897 | { |
2898 | operands[1] = force_reg (DFmode, operands[1]); | |
2899 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2900 | DONE; | |
10bbf137 | 2901 | }) |
9db1d521 HP |
2902 | |
2903 | (define_insn "fix_truncdfdi2_ieee" | |
2904 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2905 | (fix:DI (match_operand:DF 1 "register_operand" "f"))) | |
10bbf137 | 2906 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2907 | (clobber (reg:CC 33))] |
2908 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2909 | "cgdbr\t%0,%h2,%1" |
9db1d521 | 2910 | [(set_attr "op_type" "RRE") |
077dab3b | 2911 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
2912 | |
2913 | ; | |
2914 | ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s). | |
2915 | ; | |
2916 | ||
2917 | (define_expand "fixuns_truncdfsi2" | |
2918 | [(set (match_operand:SI 0 "register_operand" "") | |
2919 | (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))] | |
2920 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2921 | { |
2922 | rtx label1 = gen_label_rtx (); | |
2923 | rtx label2 = gen_label_rtx (); | |
2924 | rtx temp = gen_reg_rtx (DFmode); | |
2925 | ||
2926 | operands[1] = force_reg (DFmode,operands[1]); | |
c7453384 | 2927 | emit_insn (gen_cmpdf (operands[1], |
4023fb28 | 2928 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 2929 | REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode))); |
9db1d521 | 2930 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
2931 | emit_insn (gen_subdf3 (temp, operands[1], |
2932 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2933 | REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode))); |
9db1d521 | 2934 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7))); |
f314b9b1 | 2935 | emit_jump (label2); |
9db1d521 HP |
2936 | |
2937 | emit_label (label1); | |
2938 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2939 | emit_label (label2); | |
2940 | DONE; | |
10bbf137 | 2941 | }) |
9db1d521 HP |
2942 | |
2943 | (define_expand "fix_truncdfsi2" | |
2944 | [(set (match_operand:SI 0 "register_operand" "") | |
2945 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
2946 | "TARGET_HARD_FLOAT" | |
9db1d521 | 2947 | { |
c7453384 | 2948 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
2949 | { |
2950 | /* This is the algorithm from POP chapter A.5.7.2. */ | |
2951 | ||
c19ec8f9 | 2952 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
4023fb28 UW |
2953 | rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000); |
2954 | rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000); | |
9db1d521 HP |
2955 | |
2956 | operands[1] = force_reg (DFmode, operands[1]); | |
c7453384 | 2957 | emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1], |
9db1d521 | 2958 | two31r, two32, temp)); |
c7453384 EC |
2959 | } |
2960 | else | |
9db1d521 HP |
2961 | { |
2962 | operands[1] = force_reg (DFmode, operands[1]); | |
2963 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2964 | } | |
2965 | ||
2966 | DONE; | |
10bbf137 | 2967 | }) |
9db1d521 HP |
2968 | |
2969 | (define_insn "fix_truncdfsi2_ieee" | |
2970 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2971 | (fix:SI (match_operand:DF 1 "register_operand" "f"))) | |
10bbf137 | 2972 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2973 | (clobber (reg:CC 33))] |
2974 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2975 | "cfdbr\t%0,%h2,%1" |
9db1d521 | 2976 | [(set_attr "op_type" "RRE") |
a036c6f7 | 2977 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
2978 | |
2979 | (define_insn "fix_truncdfsi2_ibm" | |
2980 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2981 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f"))) | |
4023fb28 UW |
2982 | (use (match_operand:DI 2 "immediate_operand" "m")) |
2983 | (use (match_operand:DI 3 "immediate_operand" "m")) | |
9db1d521 HP |
2984 | (use (match_operand:BLK 4 "memory_operand" "m")) |
2985 | (clobber (reg:CC 33))] | |
2986 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
9db1d521 | 2987 | { |
d40c829f UW |
2988 | output_asm_insn ("sd\t%1,%2", operands); |
2989 | output_asm_insn ("aw\t%1,%3", operands); | |
2990 | output_asm_insn ("std\t%1,%4", operands); | |
2991 | output_asm_insn ("xi\t%N4,128", operands); | |
2992 | return "l\t%0,%N4"; | |
10bbf137 | 2993 | } |
b628bd8e | 2994 | [(set_attr "length" "20")]) |
9db1d521 HP |
2995 | |
2996 | ; | |
2997 | ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s). | |
2998 | ; | |
2999 | ||
3000 | (define_expand "fixuns_truncsfdi2" | |
3001 | [(set (match_operand:DI 0 "register_operand" "") | |
3002 | (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))] | |
3003 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
3004 | { |
3005 | rtx label1 = gen_label_rtx (); | |
3006 | rtx label2 = gen_label_rtx (); | |
3007 | rtx temp = gen_reg_rtx (SFmode); | |
3008 | ||
3009 | operands[1] = force_reg (SFmode, operands[1]); | |
c7453384 | 3010 | emit_insn (gen_cmpsf (operands[1], |
4023fb28 | 3011 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 3012 | REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode))); |
9db1d521 HP |
3013 | emit_jump_insn (gen_blt (label1)); |
3014 | ||
4023fb28 UW |
3015 | emit_insn (gen_subsf3 (temp, operands[1], |
3016 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 3017 | REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode))); |
9db1d521 | 3018 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7))); |
f314b9b1 | 3019 | emit_jump (label2); |
9db1d521 HP |
3020 | |
3021 | emit_label (label1); | |
3022 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
3023 | emit_label (label2); | |
3024 | DONE; | |
10bbf137 | 3025 | }) |
9db1d521 HP |
3026 | |
3027 | (define_expand "fix_truncsfdi2" | |
3028 | [(set (match_operand:DI 0 "register_operand" "") | |
3029 | (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
3030 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
3031 | { |
3032 | operands[1] = force_reg (SFmode, operands[1]); | |
3033 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
3034 | DONE; | |
10bbf137 | 3035 | }) |
9db1d521 HP |
3036 | |
3037 | (define_insn "fix_truncsfdi2_ieee" | |
3038 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3039 | (fix:DI (match_operand:SF 1 "register_operand" "f"))) | |
10bbf137 | 3040 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
3041 | (clobber (reg:CC 33))] |
3042 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 3043 | "cgebr\t%0,%h2,%1" |
9db1d521 | 3044 | [(set_attr "op_type" "RRE") |
077dab3b | 3045 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
3046 | |
3047 | ; | |
3048 | ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s). | |
3049 | ; | |
3050 | ||
3051 | (define_expand "fixuns_truncsfsi2" | |
3052 | [(set (match_operand:SI 0 "register_operand" "") | |
3053 | (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))] | |
3054 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
3055 | { |
3056 | rtx label1 = gen_label_rtx (); | |
3057 | rtx label2 = gen_label_rtx (); | |
3058 | rtx temp = gen_reg_rtx (SFmode); | |
3059 | ||
3060 | operands[1] = force_reg (SFmode, operands[1]); | |
4023fb28 UW |
3061 | emit_insn (gen_cmpsf (operands[1], |
3062 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 3063 | REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode))); |
9db1d521 | 3064 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
3065 | emit_insn (gen_subsf3 (temp, operands[1], |
3066 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 3067 | REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode))); |
9db1d521 | 3068 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7))); |
f314b9b1 | 3069 | emit_jump (label2); |
9db1d521 HP |
3070 | |
3071 | emit_label (label1); | |
3072 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
3073 | emit_label (label2); | |
3074 | DONE; | |
10bbf137 | 3075 | }) |
9db1d521 HP |
3076 | |
3077 | (define_expand "fix_truncsfsi2" | |
3078 | [(set (match_operand:SI 0 "register_operand" "") | |
3079 | (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
3080 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
3081 | { |
3082 | if (TARGET_IBM_FLOAT) | |
3083 | { | |
3084 | /* Convert to DFmode and then use the POP algorithm. */ | |
3085 | rtx temp = gen_reg_rtx (DFmode); | |
3086 | emit_insn (gen_extendsfdf2 (temp, operands[1])); | |
3087 | emit_insn (gen_fix_truncdfsi2 (operands[0], temp)); | |
3088 | } | |
3089 | else | |
3090 | { | |
3091 | operands[1] = force_reg (SFmode, operands[1]); | |
3092 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
3093 | } | |
3094 | ||
3095 | DONE; | |
10bbf137 | 3096 | }) |
9db1d521 HP |
3097 | |
3098 | (define_insn "fix_truncsfsi2_ieee" | |
3099 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3100 | (fix:SI (match_operand:SF 1 "register_operand" "f"))) | |
10bbf137 | 3101 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
3102 | (clobber (reg:CC 33))] |
3103 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 3104 | "cfebr\t%0,%h2,%1" |
9db1d521 | 3105 | [(set_attr "op_type" "RRE") |
077dab3b | 3106 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
3107 | |
3108 | ; | |
3109 | ; floatdidf2 instruction pattern(s). | |
3110 | ; | |
3111 | ||
3112 | (define_insn "floatdidf2" | |
3113 | [(set (match_operand:DF 0 "register_operand" "=f") | |
a036c6f7 | 3114 | (float:DF (match_operand:DI 1 "register_operand" "d")))] |
9db1d521 | 3115 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3116 | "cdgbr\t%0,%1" |
9db1d521 | 3117 | [(set_attr "op_type" "RRE") |
f0bf1270 | 3118 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3119 | |
3120 | ; | |
3121 | ; floatdisf2 instruction pattern(s). | |
3122 | ; | |
3123 | ||
3124 | (define_insn "floatdisf2" | |
3125 | [(set (match_operand:SF 0 "register_operand" "=f") | |
a036c6f7 | 3126 | (float:SF (match_operand:DI 1 "register_operand" "d")))] |
9db1d521 | 3127 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3128 | "cegbr\t%0,%1" |
9db1d521 | 3129 | [(set_attr "op_type" "RRE") |
077dab3b | 3130 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3131 | |
3132 | ; | |
3133 | ; floatsidf2 instruction pattern(s). | |
3134 | ; | |
3135 | ||
3136 | (define_expand "floatsidf2" | |
a036c6f7 UW |
3137 | [(set (match_operand:DF 0 "register_operand" "") |
3138 | (float:DF (match_operand:SI 1 "register_operand" "")))] | |
9db1d521 | 3139 | "TARGET_HARD_FLOAT" |
9db1d521 | 3140 | { |
c7453384 | 3141 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
3142 | { |
3143 | /* This is the algorithm from POP chapter A.5.7.1. */ | |
3144 | ||
c19ec8f9 | 3145 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
c7453384 | 3146 | rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000); |
9db1d521 HP |
3147 | |
3148 | emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp)); | |
3149 | DONE; | |
3150 | } | |
10bbf137 | 3151 | }) |
9db1d521 HP |
3152 | |
3153 | (define_insn "floatsidf2_ieee" | |
3154 | [(set (match_operand:DF 0 "register_operand" "=f") | |
a036c6f7 | 3155 | (float:DF (match_operand:SI 1 "register_operand" "d")))] |
9db1d521 | 3156 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3157 | "cdfbr\t%0,%1" |
9db1d521 | 3158 | [(set_attr "op_type" "RRE") |
077dab3b | 3159 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3160 | |
3161 | (define_insn "floatsidf2_ibm" | |
3162 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3163 | (float:DF (match_operand:SI 1 "register_operand" "d"))) | |
4023fb28 | 3164 | (use (match_operand:DI 2 "immediate_operand" "m")) |
9db1d521 HP |
3165 | (use (match_operand:BLK 3 "memory_operand" "m")) |
3166 | (clobber (reg:CC 33))] | |
3167 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
9db1d521 | 3168 | { |
d40c829f UW |
3169 | output_asm_insn ("st\t%1,%N3", operands); |
3170 | output_asm_insn ("xi\t%N3,128", operands); | |
3171 | output_asm_insn ("mvc\t%O3(4,%R3),%2", operands); | |
3172 | output_asm_insn ("ld\t%0,%3", operands); | |
3173 | return "sd\t%0,%2"; | |
10bbf137 | 3174 | } |
b628bd8e | 3175 | [(set_attr "length" "20")]) |
9db1d521 HP |
3176 | |
3177 | ; | |
3178 | ; floatsisf2 instruction pattern(s). | |
3179 | ; | |
3180 | ||
3181 | (define_expand "floatsisf2" | |
a036c6f7 UW |
3182 | [(set (match_operand:SF 0 "register_operand" "") |
3183 | (float:SF (match_operand:SI 1 "register_operand" "")))] | |
9db1d521 | 3184 | "TARGET_HARD_FLOAT" |
9db1d521 HP |
3185 | { |
3186 | if (TARGET_IBM_FLOAT) | |
3187 | { | |
3188 | /* Use the POP algorithm to convert to DFmode and then truncate. */ | |
3189 | rtx temp = gen_reg_rtx (DFmode); | |
3190 | emit_insn (gen_floatsidf2 (temp, operands[1])); | |
3191 | emit_insn (gen_truncdfsf2 (operands[0], temp)); | |
3192 | DONE; | |
3193 | } | |
10bbf137 | 3194 | }) |
9db1d521 HP |
3195 | |
3196 | (define_insn "floatsisf2_ieee" | |
3197 | [(set (match_operand:SF 0 "register_operand" "=f") | |
a036c6f7 | 3198 | (float:SF (match_operand:SI 1 "register_operand" "d")))] |
9db1d521 | 3199 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3200 | "cefbr\t%0,%1" |
9db1d521 | 3201 | [(set_attr "op_type" "RRE") |
077dab3b | 3202 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3203 | |
3204 | ; | |
3205 | ; truncdfsf2 instruction pattern(s). | |
3206 | ; | |
3207 | ||
3208 | (define_expand "truncdfsf2" | |
3209 | [(set (match_operand:SF 0 "register_operand" "") | |
a036c6f7 | 3210 | (float_truncate:SF (match_operand:DF 1 "register_operand" "")))] |
9db1d521 | 3211 | "TARGET_HARD_FLOAT" |
4023fb28 | 3212 | "") |
9db1d521 HP |
3213 | |
3214 | (define_insn "truncdfsf2_ieee" | |
3215 | [(set (match_operand:SF 0 "register_operand" "=f") | |
a036c6f7 | 3216 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] |
9db1d521 | 3217 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3218 | "ledbr\t%0,%1" |
ce50cae8 | 3219 | [(set_attr "op_type" "RRE")]) |
9db1d521 HP |
3220 | |
3221 | (define_insn "truncdfsf2_ibm" | |
3222 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
a036c6f7 | 3223 | (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))] |
9db1d521 HP |
3224 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
3225 | "@ | |
a036c6f7 | 3226 | ler\t%0,%1 |
d40c829f | 3227 | le\t%0,%1" |
4023fb28 | 3228 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3229 | (set_attr "type" "floads,floads")]) |
9db1d521 HP |
3230 | |
3231 | ; | |
3232 | ; extendsfdf2 instruction pattern(s). | |
3233 | ; | |
3234 | ||
3235 | (define_expand "extendsfdf2" | |
3236 | [(set (match_operand:DF 0 "register_operand" "") | |
3237 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] | |
3238 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
3239 | { |
3240 | if (TARGET_IBM_FLOAT) | |
3241 | { | |
3242 | emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1])); | |
3243 | DONE; | |
3244 | } | |
10bbf137 | 3245 | }) |
9db1d521 HP |
3246 | |
3247 | (define_insn "extendsfdf2_ieee" | |
3248 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 3249 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))] |
9db1d521 HP |
3250 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3251 | "@ | |
d40c829f UW |
3252 | ldebr\t%0,%1 |
3253 | ldeb\t%0,%1" | |
077dab3b HP |
3254 | [(set_attr "op_type" "RRE,RXE") |
3255 | (set_attr "type" "floads,floads")]) | |
9db1d521 HP |
3256 | |
3257 | (define_insn "extendsfdf2_ibm" | |
3258 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 3259 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R"))) |
9db1d521 HP |
3260 | (clobber (reg:CC 33))] |
3261 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3262 | "@ | |
d40c829f UW |
3263 | sdr\t%0,%0\;ler\t%0,%1 |
3264 | sdr\t%0,%0\;le\t%0,%1" | |
b628bd8e | 3265 | [(set_attr "length" "4,6") |
a036c6f7 | 3266 | (set_attr "type" "floads,floads")]) |
9db1d521 HP |
3267 | |
3268 | ||
3269 | ;; | |
fae778eb | 3270 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 3271 | ;; |
fae778eb | 3272 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
3273 | ; because of unpredictable Bits in Register for Halfword and Byte |
3274 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
3275 | ||
07893d4f UW |
3276 | ;; |
3277 | ;;- Add instructions. | |
3278 | ;; | |
3279 | ||
1c7b1b7e UW |
3280 | ; |
3281 | ; addti3 instruction pattern(s). | |
3282 | ; | |
3283 | ||
3284 | (define_insn_and_split "addti3" | |
3285 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
3286 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") | |
3287 | (match_operand:TI 2 "general_operand" "do") ) ) | |
3288 | (clobber (reg:CC 33))] | |
3289 | "TARGET_64BIT" | |
3290 | "#" | |
3291 | "&& reload_completed" | |
3292 | [(parallel | |
3293 | [(set (reg:CCL1 33) | |
3294 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) | |
3295 | (match_dup 7))) | |
3296 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
3297 | (parallel | |
3298 | [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5)) | |
3299 | (ltu:DI (reg:CCL1 33) (const_int 0)))) | |
3300 | (clobber (reg:CC 33))])] | |
3301 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
3302 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
3303 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
3304 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
3305 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 3306 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 3307 | |
07893d4f UW |
3308 | ; |
3309 | ; adddi3 instruction pattern(s). | |
3310 | ; | |
3311 | ||
07893d4f UW |
3312 | (define_insn "*adddi3_sign" |
3313 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3314 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3315 | (match_operand:DI 1 "register_operand" "0,0"))) | |
3316 | (clobber (reg:CC 33))] | |
3317 | "TARGET_64BIT" | |
3318 | "@ | |
d40c829f UW |
3319 | agfr\t%0,%2 |
3320 | agf\t%0,%2" | |
d3632d41 | 3321 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3322 | |
3323 | (define_insn "*adddi3_zero_cc" | |
c7453384 | 3324 | [(set (reg 33) |
07893d4f UW |
3325 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3326 | (match_operand:DI 1 "register_operand" "0,0")) | |
3327 | (const_int 0))) | |
3328 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3329 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
3330 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3331 | "@ | |
d40c829f UW |
3332 | algfr\t%0,%2 |
3333 | algf\t%0,%2" | |
d3632d41 | 3334 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3335 | |
3336 | (define_insn "*adddi3_zero_cconly" | |
c7453384 | 3337 | [(set (reg 33) |
07893d4f UW |
3338 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3339 | (match_operand:DI 1 "register_operand" "0,0")) | |
3340 | (const_int 0))) | |
3341 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3342 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3343 | "@ | |
d40c829f UW |
3344 | algfr\t%0,%2 |
3345 | algf\t%0,%2" | |
d3632d41 | 3346 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3347 | |
3348 | (define_insn "*adddi3_zero" | |
3349 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3350 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3351 | (match_operand:DI 1 "register_operand" "0,0"))) | |
3352 | (clobber (reg:CC 33))] | |
3353 | "TARGET_64BIT" | |
3354 | "@ | |
d40c829f UW |
3355 | algfr\t%0,%2 |
3356 | algf\t%0,%2" | |
d3632d41 | 3357 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3358 | |
0a3bdf9d | 3359 | (define_insn "*adddi3_imm_cc" |
c7453384 | 3360 | [(set (reg 33) |
0a3bdf9d UW |
3361 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0") |
3362 | (match_operand:DI 2 "const_int_operand" "K")) | |
3363 | (const_int 0))) | |
3364 | (set (match_operand:DI 0 "register_operand" "=d") | |
3365 | (plus:DI (match_dup 1) (match_dup 2)))] | |
c7453384 EC |
3366 | "TARGET_64BIT |
3367 | && s390_match_ccmode (insn, CCAmode) | |
f19a9af7 | 3368 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")" |
d40c829f | 3369 | "aghi\t%0,%h2" |
077dab3b | 3370 | [(set_attr "op_type" "RI")]) |
0a3bdf9d | 3371 | |
b2ba71ca UW |
3372 | (define_insn "*adddi3_carry1_cc" |
3373 | [(set (reg 33) | |
3374 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3375 | (match_operand:DI 2 "general_operand" "d,m")) | |
3376 | (match_dup 1))) | |
3377 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3378 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3379 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3380 | "@ | |
3381 | algr\t%0,%2 | |
3382 | alg\t%0,%2" | |
3383 | [(set_attr "op_type" "RRE,RXY")]) | |
3384 | ||
3385 | (define_insn "*adddi3_carry1_cconly" | |
3386 | [(set (reg 33) | |
3387 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3388 | (match_operand:DI 2 "general_operand" "d,m")) | |
3389 | (match_dup 1))) | |
3390 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3391 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3392 | "@ | |
3393 | algr\t%0,%2 | |
3394 | alg\t%0,%2" | |
3395 | [(set_attr "op_type" "RRE,RXY")]) | |
3396 | ||
3397 | (define_insn "*adddi3_carry2_cc" | |
3398 | [(set (reg 33) | |
3399 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3400 | (match_operand:DI 2 "general_operand" "d,m")) | |
3401 | (match_dup 2))) | |
3402 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3403 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3404 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3405 | "@ | |
3406 | algr\t%0,%2 | |
3407 | alg\t%0,%2" | |
3408 | [(set_attr "op_type" "RRE,RXY")]) | |
3409 | ||
3410 | (define_insn "*adddi3_carry2_cconly" | |
3411 | [(set (reg 33) | |
3412 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3413 | (match_operand:DI 2 "general_operand" "d,m")) | |
3414 | (match_dup 2))) | |
3415 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3416 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3417 | "@ | |
3418 | algr\t%0,%2 | |
3419 | alg\t%0,%2" | |
3420 | [(set_attr "op_type" "RRE,RXY")]) | |
3421 | ||
07893d4f | 3422 | (define_insn "*adddi3_cc" |
c7453384 | 3423 | [(set (reg 33) |
96fd3851 | 3424 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3425 | (match_operand:DI 2 "general_operand" "d,m")) |
3426 | (const_int 0))) | |
3427 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3428 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3429 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3430 | "@ | |
d40c829f UW |
3431 | algr\t%0,%2 |
3432 | alg\t%0,%2" | |
d3632d41 | 3433 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3434 | |
07893d4f | 3435 | (define_insn "*adddi3_cconly" |
c7453384 | 3436 | [(set (reg 33) |
96fd3851 | 3437 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3438 | (match_operand:DI 2 "general_operand" "d,m")) |
3439 | (const_int 0))) | |
3440 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3441 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3442 | "@ | |
d40c829f UW |
3443 | algr\t%0,%2 |
3444 | alg\t%0,%2" | |
d3632d41 | 3445 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3446 | |
07893d4f | 3447 | (define_insn "*adddi3_cconly2" |
c7453384 | 3448 | [(set (reg 33) |
96fd3851 | 3449 | (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3450 | (neg:SI (match_operand:DI 2 "general_operand" "d,m")))) |
3451 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3452 | "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT" | |
9db1d521 | 3453 | "@ |
d40c829f UW |
3454 | algr\t%0,%2 |
3455 | alg\t%0,%2" | |
d3632d41 | 3456 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3457 | |
07893d4f | 3458 | (define_insn "*adddi3_64" |
9db1d521 | 3459 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
96fd3851 | 3460 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
9db1d521 HP |
3461 | (match_operand:DI 2 "general_operand" "d,K,m") ) ) |
3462 | (clobber (reg:CC 33))] | |
3463 | "TARGET_64BIT" | |
3464 | "@ | |
d40c829f UW |
3465 | agr\t%0,%2 |
3466 | aghi\t%0,%h2 | |
3467 | ag\t%0,%2" | |
d3632d41 | 3468 | [(set_attr "op_type" "RRE,RI,RXY")]) |
9db1d521 | 3469 | |
e69166de UW |
3470 | (define_insn_and_split "*adddi3_31z" |
3471 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3472 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") | |
3473 | (match_operand:DI 2 "general_operand" "do") ) ) | |
3474 | (clobber (reg:CC 33))] | |
3475 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
3476 | "#" | |
3477 | "&& reload_completed" | |
3478 | [(parallel | |
3479 | [(set (reg:CCL1 33) | |
3480 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) | |
3481 | (match_dup 7))) | |
3482 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3483 | (parallel | |
3484 | [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5)) | |
3485 | (ltu:SI (reg:CCL1 33) (const_int 0)))) | |
3486 | (clobber (reg:CC 33))])] | |
3487 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
3488 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3489 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3490 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3491 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 3492 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 3493 | |
07893d4f UW |
3494 | (define_insn_and_split "*adddi3_31" |
3495 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
96fd3851 | 3496 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 3497 | (match_operand:DI 2 "general_operand" "do") ) ) |
9db1d521 | 3498 | (clobber (reg:CC 33))] |
e69166de | 3499 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
3500 | "#" |
3501 | "&& reload_completed" | |
3502 | [(parallel | |
3503 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
3504 | (clobber (reg:CC 33))]) | |
3505 | (parallel | |
3506 | [(set (reg:CCL1 33) | |
3507 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) | |
3508 | (match_dup 7))) | |
3509 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3510 | (set (pc) | |
3511 | (if_then_else (ltu (reg:CCL1 33) (const_int 0)) | |
3512 | (pc) | |
3513 | (label_ref (match_dup 9)))) | |
3514 | (parallel | |
3515 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
3516 | (clobber (reg:CC 33))]) | |
3517 | (match_dup 9)] | |
97c6f7ad UW |
3518 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3519 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3520 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3521 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3522 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3523 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 3524 | operands[9] = gen_label_rtx ();") |
9db1d521 HP |
3525 | |
3526 | (define_expand "adddi3" | |
07893d4f UW |
3527 | [(parallel |
3528 | [(set (match_operand:DI 0 "register_operand" "") | |
96fd3851 | 3529 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
07893d4f UW |
3530 | (match_operand:DI 2 "general_operand" ""))) |
3531 | (clobber (reg:CC 33))])] | |
9db1d521 | 3532 | "" |
07893d4f | 3533 | "") |
9db1d521 | 3534 | |
9db1d521 HP |
3535 | ; |
3536 | ; addsi3 instruction pattern(s). | |
3537 | ; | |
9db1d521 | 3538 | |
0a3bdf9d | 3539 | (define_insn "*addsi3_imm_cc" |
c7453384 | 3540 | [(set (reg 33) |
0a3bdf9d UW |
3541 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
3542 | (match_operand:SI 2 "const_int_operand" "K")) | |
3543 | (const_int 0))) | |
3544 | (set (match_operand:SI 0 "register_operand" "=d") | |
3545 | (plus:SI (match_dup 1) (match_dup 2)))] | |
3546 | "s390_match_ccmode (insn, CCAmode) | |
f19a9af7 | 3547 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")" |
d40c829f | 3548 | "ahi\t%0,%h2" |
077dab3b | 3549 | [(set_attr "op_type" "RI")]) |
0a3bdf9d | 3550 | |
07893d4f | 3551 | (define_insn "*addsi3_carry1_cc" |
c7453384 | 3552 | [(set (reg 33) |
d3632d41 UW |
3553 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3554 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3555 | (match_dup 1))) |
d3632d41 | 3556 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3557 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3558 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3559 | "@ |
d40c829f UW |
3560 | alr\t%0,%2 |
3561 | al\t%0,%2 | |
3562 | aly\t%0,%2" | |
d3632d41 | 3563 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3564 | |
3565 | (define_insn "*addsi3_carry1_cconly" | |
c7453384 | 3566 | [(set (reg 33) |
d3632d41 UW |
3567 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3568 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3569 | (match_dup 1))) |
d3632d41 | 3570 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3571 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3572 | "@ |
d40c829f UW |
3573 | alr\t%0,%2 |
3574 | al\t%0,%2 | |
3575 | aly\t%0,%2" | |
d3632d41 | 3576 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3577 | |
3578 | (define_insn "*addsi3_carry2_cc" | |
c7453384 | 3579 | [(set (reg 33) |
d3632d41 UW |
3580 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3581 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3582 | (match_dup 2))) |
d3632d41 | 3583 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3584 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3585 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3586 | "@ |
d40c829f UW |
3587 | alr\t%0,%2 |
3588 | al\t%0,%2 | |
3589 | aly\t%0,%2" | |
d3632d41 | 3590 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3591 | |
3592 | (define_insn "*addsi3_carry2_cconly" | |
c7453384 | 3593 | [(set (reg 33) |
d3632d41 UW |
3594 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3595 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3596 | (match_dup 2))) |
d3632d41 | 3597 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3598 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3599 | "@ |
d40c829f UW |
3600 | alr\t%0,%2 |
3601 | al\t%0,%2 | |
3602 | aly\t%0,%2" | |
d3632d41 | 3603 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f | 3604 | |
9db1d521 | 3605 | (define_insn "*addsi3_cc" |
c7453384 | 3606 | [(set (reg 33) |
d3632d41 UW |
3607 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3608 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3609 | (const_int 0))) |
d3632d41 | 3610 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 | 3611 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3612 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3613 | "@ |
d40c829f UW |
3614 | alr\t%0,%2 |
3615 | al\t%0,%2 | |
3616 | aly\t%0,%2" | |
d3632d41 | 3617 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
3618 | |
3619 | (define_insn "*addsi3_cconly" | |
c7453384 | 3620 | [(set (reg 33) |
d3632d41 UW |
3621 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3622 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3623 | (const_int 0))) |
d3632d41 | 3624 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3625 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3626 | "@ |
d40c829f UW |
3627 | alr\t%0,%2 |
3628 | al\t%0,%2 | |
3629 | aly\t%0,%2" | |
d3632d41 | 3630 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
3631 | |
3632 | (define_insn "*addsi3_cconly2" | |
c7453384 | 3633 | [(set (reg 33) |
d3632d41 UW |
3634 | (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3635 | (neg:SI (match_operand:SI 2 "general_operand" "d,R,T")))) | |
3636 | (clobber (match_scratch:SI 0 "=d,d,d"))] | |
b2ba71ca | 3637 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3638 | "@ |
d40c829f UW |
3639 | alr\t%0,%2 |
3640 | al\t%0,%2 | |
3641 | aly\t%0,%2" | |
d3632d41 | 3642 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 3643 | |
07893d4f | 3644 | (define_insn "*addsi3_sign" |
d3632d41 | 3645 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
f0ad121f UW |
3646 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) |
3647 | (match_operand:SI 1 "register_operand" "0,0"))) | |
07893d4f UW |
3648 | (clobber (reg:CC 33))] |
3649 | "" | |
d3632d41 | 3650 | "@ |
d40c829f UW |
3651 | ah\t%0,%2 |
3652 | ahy\t%0,%2" | |
d3632d41 | 3653 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f | 3654 | |
9db1d521 | 3655 | (define_insn "addsi3" |
d3632d41 UW |
3656 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
3657 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
3658 | (match_operand:SI 2 "general_operand" "d,K,R,T"))) | |
9db1d521 HP |
3659 | (clobber (reg:CC 33))] |
3660 | "" | |
3661 | "@ | |
d40c829f UW |
3662 | ar\t%0,%2 |
3663 | ahi\t%0,%h2 | |
3664 | a\t%0,%2 | |
3665 | ay\t%0,%2" | |
d3632d41 | 3666 | [(set_attr "op_type" "RR,RI,RX,RXY")]) |
9db1d521 | 3667 | |
9db1d521 HP |
3668 | ; |
3669 | ; adddf3 instruction pattern(s). | |
3670 | ; | |
3671 | ||
3672 | (define_expand "adddf3" | |
3673 | [(parallel | |
3674 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3675 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3676 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3677 | (clobber (reg:CC 33))])] |
3678 | "TARGET_HARD_FLOAT" | |
3679 | "") | |
3680 | ||
3681 | (define_insn "*adddf3" | |
3682 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3683 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3684 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3685 | (clobber (reg:CC 33))] |
3686 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3687 | "@ | |
d40c829f UW |
3688 | adbr\t%0,%2 |
3689 | adb\t%0,%2" | |
ce50cae8 | 3690 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 3691 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 | 3692 | |
3ef093a8 AK |
3693 | (define_insn "*adddf3_cc" |
3694 | [(set (reg 33) | |
3695 | (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
3696 | (match_operand:DF 2 "general_operand" "f,R")) | |
3697 | (match_operand:DF 3 "const0_operand" ""))) | |
3698 | (set (match_operand:DF 0 "register_operand" "=f,f") | |
3699 | (plus:DF (match_dup 1) (match_dup 2)))] | |
3700 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3701 | "@ | |
d40c829f UW |
3702 | adbr\t%0,%2 |
3703 | adb\t%0,%2" | |
3ef093a8 AK |
3704 | [(set_attr "op_type" "RRE,RXE") |
3705 | (set_attr "type" "fsimpd,fsimpd")]) | |
3706 | ||
3707 | (define_insn "*adddf3_cconly" | |
3708 | [(set (reg 33) | |
3709 | (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
3710 | (match_operand:DF 2 "general_operand" "f,R")) | |
3711 | (match_operand:DF 3 "const0_operand" ""))) | |
3712 | (clobber (match_scratch:DF 0 "=f,f"))] | |
3713 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3714 | "@ | |
d40c829f UW |
3715 | adbr\t%0,%2 |
3716 | adb\t%0,%2" | |
3ef093a8 AK |
3717 | [(set_attr "op_type" "RRE,RXE") |
3718 | (set_attr "type" "fsimpd,fsimpd")]) | |
3719 | ||
9db1d521 HP |
3720 | (define_insn "*adddf3_ibm" |
3721 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3722 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3723 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3724 | (clobber (reg:CC 33))] |
3725 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3726 | "@ | |
d40c829f UW |
3727 | adr\t%0,%2 |
3728 | ad\t%0,%2" | |
9db1d521 | 3729 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3730 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 HP |
3731 | |
3732 | ; | |
3733 | ; addsf3 instruction pattern(s). | |
3734 | ; | |
3735 | ||
3736 | (define_expand "addsf3" | |
3737 | [(parallel | |
3738 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3739 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3740 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3741 | (clobber (reg:CC 33))])] |
3742 | "TARGET_HARD_FLOAT" | |
3743 | "") | |
3744 | ||
3745 | (define_insn "*addsf3" | |
3746 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3747 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3748 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3749 | (clobber (reg:CC 33))] |
3750 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3751 | "@ | |
d40c829f UW |
3752 | aebr\t%0,%2 |
3753 | aeb\t%0,%2" | |
ce50cae8 | 3754 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 3755 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 | 3756 | |
3ef093a8 AK |
3757 | (define_insn "*addsf3_cc" |
3758 | [(set (reg 33) | |
3759 | (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
3760 | (match_operand:SF 2 "general_operand" "f,R")) | |
3761 | (match_operand:SF 3 "const0_operand" ""))) | |
3762 | (set (match_operand:SF 0 "register_operand" "=f,f") | |
3763 | (plus:SF (match_dup 1) (match_dup 2)))] | |
3764 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3765 | "@ | |
d40c829f UW |
3766 | aebr\t%0,%2 |
3767 | aeb\t%0,%2" | |
3ef093a8 AK |
3768 | [(set_attr "op_type" "RRE,RXE") |
3769 | (set_attr "type" "fsimps,fsimps")]) | |
3770 | ||
3771 | (define_insn "*addsf3_cconly" | |
3772 | [(set (reg 33) | |
3773 | (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
3774 | (match_operand:SF 2 "general_operand" "f,R")) | |
3775 | (match_operand:SF 3 "const0_operand" ""))) | |
3776 | (clobber (match_scratch:SF 0 "=f,f"))] | |
3777 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3778 | "@ | |
d40c829f UW |
3779 | aebr\t%0,%2 |
3780 | aeb\t%0,%2" | |
3ef093a8 AK |
3781 | [(set_attr "op_type" "RRE,RXE") |
3782 | (set_attr "type" "fsimps,fsimps")]) | |
3783 | ||
9db1d521 HP |
3784 | (define_insn "*addsf3" |
3785 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3786 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3787 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3788 | (clobber (reg:CC 33))] |
3789 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3790 | "@ | |
d40c829f UW |
3791 | aer\t%0,%2 |
3792 | ae\t%0,%2" | |
9db1d521 | 3793 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3794 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 HP |
3795 | |
3796 | ||
3797 | ;; | |
3798 | ;;- Subtract instructions. | |
3799 | ;; | |
3800 | ||
1c7b1b7e UW |
3801 | ; |
3802 | ; subti3 instruction pattern(s). | |
3803 | ; | |
3804 | ||
3805 | (define_insn_and_split "subti3" | |
3806 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
3807 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
3808 | (match_operand:TI 2 "general_operand" "do") ) ) | |
3809 | (clobber (reg:CC 33))] | |
3810 | "TARGET_64BIT" | |
3811 | "#" | |
3812 | "&& reload_completed" | |
3813 | [(parallel | |
3814 | [(set (reg:CCL2 33) | |
3815 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) | |
3816 | (match_dup 7))) | |
3817 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
3818 | (parallel | |
3819 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
3820 | (gtu:DI (reg:CCL2 33) (const_int 0)))) | |
3821 | (clobber (reg:CC 33))])] | |
3822 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
3823 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
3824 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
3825 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
3826 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 3827 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 3828 | |
9db1d521 HP |
3829 | ; |
3830 | ; subdi3 instruction pattern(s). | |
3831 | ; | |
3832 | ||
07893d4f UW |
3833 | (define_insn "*subdi3_sign" |
3834 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3835 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3836 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
3837 | (clobber (reg:CC 33))] | |
3838 | "TARGET_64BIT" | |
3839 | "@ | |
d40c829f UW |
3840 | sgfr\t%0,%2 |
3841 | sgf\t%0,%2" | |
d3632d41 | 3842 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3843 | |
3844 | (define_insn "*subdi3_zero_cc" | |
c7453384 | 3845 | [(set (reg 33) |
07893d4f UW |
3846 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3847 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3848 | (const_int 0))) | |
3849 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3850 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
3851 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3852 | "@ | |
d40c829f UW |
3853 | slgfr\t%0,%2 |
3854 | slgf\t%0,%2" | |
d3632d41 | 3855 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3856 | |
3857 | (define_insn "*subdi3_zero_cconly" | |
c7453384 | 3858 | [(set (reg 33) |
07893d4f UW |
3859 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3860 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3861 | (const_int 0))) | |
3862 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3863 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3864 | "@ | |
d40c829f UW |
3865 | slgfr\t%0,%2 |
3866 | slgf\t%0,%2" | |
d3632d41 | 3867 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3868 | |
3869 | (define_insn "*subdi3_zero" | |
3870 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3871 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3872 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
3873 | (clobber (reg:CC 33))] | |
3874 | "TARGET_64BIT" | |
3875 | "@ | |
d40c829f UW |
3876 | slgfr\t%0,%2 |
3877 | slgf\t%0,%2" | |
d3632d41 | 3878 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3879 | |
b2ba71ca UW |
3880 | (define_insn "*subdi3_borrow_cc" |
3881 | [(set (reg 33) | |
3882 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3883 | (match_operand:DI 2 "general_operand" "d,m")) | |
3884 | (match_dup 1))) | |
3885 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3886 | (minus:DI (match_dup 1) (match_dup 2)))] | |
3887 | "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" | |
3888 | "@ | |
3889 | slgr\t%0,%2 | |
3890 | slg\t%0,%2" | |
3891 | [(set_attr "op_type" "RRE,RXY")]) | |
3892 | ||
3893 | (define_insn "*subdi3_borrow_cconly" | |
3894 | [(set (reg 33) | |
3895 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3896 | (match_operand:DI 2 "general_operand" "d,m")) | |
3897 | (match_dup 1))) | |
3898 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3899 | "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" | |
3900 | "@ | |
3901 | slgr\t%0,%2 | |
3902 | slg\t%0,%2" | |
3903 | [(set_attr "op_type" "RRE,RXY")]) | |
3904 | ||
07893d4f UW |
3905 | (define_insn "*subdi3_cc" |
3906 | [(set (reg 33) | |
3907 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3908 | (match_operand:DI 2 "general_operand" "d,m")) | |
3909 | (const_int 0))) | |
3910 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3911 | (minus:DI (match_dup 1) (match_dup 2)))] | |
b2ba71ca | 3912 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
07893d4f | 3913 | "@ |
d40c829f UW |
3914 | slgr\t%0,%2 |
3915 | slg\t%0,%2" | |
d3632d41 | 3916 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3917 | |
5d880bd2 UW |
3918 | (define_insn "*subdi3_cc2" |
3919 | [(set (reg 33) | |
3920 | (compare (match_operand:DI 1 "register_operand" "0,0") | |
3921 | (match_operand:DI 2 "general_operand" "d,m"))) | |
3922 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3923 | (minus:DI (match_dup 1) (match_dup 2)))] | |
3924 | "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT" | |
3925 | "@ | |
3926 | slgr\t%0,%2 | |
3927 | slg\t%0,%2" | |
3928 | [(set_attr "op_type" "RRE,RXY")]) | |
3929 | ||
07893d4f UW |
3930 | (define_insn "*subdi3_cconly" |
3931 | [(set (reg 33) | |
3932 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3933 | (match_operand:DI 2 "general_operand" "d,m")) | |
3934 | (const_int 0))) | |
3935 | (clobber (match_scratch:DI 0 "=d,d"))] | |
b2ba71ca | 3936 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
07893d4f | 3937 | "@ |
d40c829f UW |
3938 | slgr\t%0,%2 |
3939 | slg\t%0,%2" | |
d3632d41 | 3940 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3941 | |
5d880bd2 UW |
3942 | (define_insn "*subdi3_cconly2" |
3943 | [(set (reg 33) | |
3944 | (compare (match_operand:DI 1 "register_operand" "0,0") | |
3945 | (match_operand:DI 2 "general_operand" "d,m"))) | |
3946 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3947 | "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT" | |
3948 | "@ | |
3949 | slgr\t%0,%2 | |
3950 | slg\t%0,%2" | |
3951 | [(set_attr "op_type" "RRE,RXY")]) | |
3952 | ||
9db1d521 HP |
3953 | (define_insn "*subdi3_64" |
3954 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3955 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3956 | (match_operand:DI 2 "general_operand" "d,m") ) ) | |
3957 | (clobber (reg:CC 33))] | |
3958 | "TARGET_64BIT" | |
3959 | "@ | |
d40c829f UW |
3960 | sgr\t%0,%2 |
3961 | sg\t%0,%2" | |
077dab3b | 3962 | [(set_attr "op_type" "RRE,RRE")]) |
9db1d521 | 3963 | |
e69166de UW |
3964 | (define_insn_and_split "*subdi3_31z" |
3965 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3966 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
3967 | (match_operand:DI 2 "general_operand" "do") ) ) | |
3968 | (clobber (reg:CC 33))] | |
3969 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
3970 | "#" | |
3971 | "&& reload_completed" | |
3972 | [(parallel | |
3973 | [(set (reg:CCL2 33) | |
3974 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) | |
3975 | (match_dup 7))) | |
3976 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
3977 | (parallel | |
3978 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
3979 | (gtu:SI (reg:CCL2 33) (const_int 0)))) | |
3980 | (clobber (reg:CC 33))])] | |
3981 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
3982 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3983 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3984 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3985 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 3986 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 3987 | |
07893d4f UW |
3988 | (define_insn_and_split "*subdi3_31" |
3989 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3990 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 3991 | (match_operand:DI 2 "general_operand" "do") ) ) |
9db1d521 | 3992 | (clobber (reg:CC 33))] |
e69166de | 3993 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
3994 | "#" |
3995 | "&& reload_completed" | |
3996 | [(parallel | |
3997 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
3998 | (clobber (reg:CC 33))]) | |
3999 | (parallel | |
4000 | [(set (reg:CCL2 33) | |
4001 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) | |
4002 | (match_dup 7))) | |
4003 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
4004 | (set (pc) | |
4005 | (if_then_else (gtu (reg:CCL2 33) (const_int 0)) | |
4006 | (pc) | |
4007 | (label_ref (match_dup 9)))) | |
4008 | (parallel | |
4009 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
4010 | (clobber (reg:CC 33))]) | |
4011 | (match_dup 9)] | |
97c6f7ad UW |
4012 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4013 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4014 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4015 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4016 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4017 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 4018 | operands[9] = gen_label_rtx ();") |
07893d4f UW |
4019 | |
4020 | (define_expand "subdi3" | |
4021 | [(parallel | |
4022 | [(set (match_operand:DI 0 "register_operand" "") | |
4023 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
4024 | (match_operand:DI 2 "general_operand" ""))) | |
4025 | (clobber (reg:CC 33))])] | |
9db1d521 | 4026 | "" |
07893d4f | 4027 | "") |
9db1d521 HP |
4028 | |
4029 | ; | |
4030 | ; subsi3 instruction pattern(s). | |
4031 | ; | |
4032 | ||
07893d4f UW |
4033 | (define_insn "*subsi3_borrow_cc" |
4034 | [(set (reg 33) | |
d3632d41 UW |
4035 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
4036 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 4037 | (match_dup 1))) |
d3632d41 | 4038 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 4039 | (minus:SI (match_dup 1) (match_dup 2)))] |
b2ba71ca | 4040 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 4041 | "@ |
d40c829f UW |
4042 | slr\t%0,%2 |
4043 | sl\t%0,%2 | |
4044 | sly\t%0,%2" | |
d3632d41 | 4045 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
4046 | |
4047 | (define_insn "*subsi3_borrow_cconly" | |
4048 | [(set (reg 33) | |
d3632d41 UW |
4049 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
4050 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 4051 | (match_dup 1))) |
d3632d41 | 4052 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
b2ba71ca | 4053 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 4054 | "@ |
d40c829f UW |
4055 | slr\t%0,%2 |
4056 | sl\t%0,%2 | |
4057 | sly\t%0,%2" | |
b2ba71ca | 4058 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f | 4059 | |
9db1d521 HP |
4060 | (define_insn "*subsi3_cc" |
4061 | [(set (reg 33) | |
d3632d41 UW |
4062 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
4063 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 4064 | (const_int 0))) |
d3632d41 | 4065 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 | 4066 | (minus:SI (match_dup 1) (match_dup 2)))] |
b2ba71ca | 4067 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4068 | "@ |
d40c829f UW |
4069 | slr\t%0,%2 |
4070 | sl\t%0,%2 | |
4071 | sly\t%0,%2" | |
d3632d41 | 4072 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 4073 | |
5d880bd2 UW |
4074 | (define_insn "*subsi3_cc2" |
4075 | [(set (reg 33) | |
4076 | (compare (match_operand:SI 1 "register_operand" "0,0,0") | |
4077 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
4078 | (set (match_operand:SI 0 "register_operand" "=d,d,d") | |
4079 | (minus:SI (match_dup 1) (match_dup 2)))] | |
4080 | "s390_match_ccmode (insn, CCL3mode)" | |
4081 | "@ | |
4082 | slr\t%0,%2 | |
4083 | sl\t%0,%2 | |
4084 | sly\t%0,%2" | |
4085 | [(set_attr "op_type" "RR,RX,RXY")]) | |
4086 | ||
9db1d521 HP |
4087 | (define_insn "*subsi3_cconly" |
4088 | [(set (reg 33) | |
d3632d41 UW |
4089 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
4090 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 4091 | (const_int 0))) |
d3632d41 | 4092 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
b2ba71ca | 4093 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4094 | "@ |
d40c829f UW |
4095 | slr\t%0,%2 |
4096 | sl\t%0,%2 | |
4097 | sly\t%0,%2" | |
d3632d41 | 4098 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 4099 | |
5d880bd2 UW |
4100 | (define_insn "*subsi3_cconly2" |
4101 | [(set (reg 33) | |
4102 | (compare (match_operand:SI 1 "register_operand" "0,0,0") | |
4103 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
4104 | (clobber (match_scratch:SI 0 "=d,d,d"))] | |
4105 | "s390_match_ccmode (insn, CCL3mode)" | |
4106 | "@ | |
4107 | slr\t%0,%2 | |
4108 | sl\t%0,%2 | |
4109 | sly\t%0,%2" | |
4110 | [(set_attr "op_type" "RR,RX,RXY")]) | |
4111 | ||
07893d4f | 4112 | (define_insn "*subsi3_sign" |
d3632d41 UW |
4113 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4114 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
4115 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
07893d4f UW |
4116 | (clobber (reg:CC 33))] |
4117 | "" | |
d3632d41 | 4118 | "@ |
d40c829f UW |
4119 | sh\t%0,%2 |
4120 | shy\t%0,%2" | |
d3632d41 | 4121 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f | 4122 | |
9db1d521 | 4123 | (define_insn "subsi3" |
d3632d41 UW |
4124 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
4125 | (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") | |
4126 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
9db1d521 HP |
4127 | (clobber (reg:CC 33))] |
4128 | "" | |
4129 | "@ | |
d40c829f UW |
4130 | sr\t%0,%2 |
4131 | s\t%0,%2 | |
4132 | sy\t%0,%2" | |
d3632d41 | 4133 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 4134 | |
9db1d521 HP |
4135 | |
4136 | ; | |
4137 | ; subdf3 instruction pattern(s). | |
4138 | ; | |
4139 | ||
4140 | (define_expand "subdf3" | |
4141 | [(parallel | |
4142 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4143 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 4144 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4145 | (clobber (reg:CC 33))])] |
4146 | "TARGET_HARD_FLOAT" | |
4147 | "") | |
4148 | ||
4149 | (define_insn "*subdf3" | |
4150 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4151 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 4152 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4153 | (clobber (reg:CC 33))] |
4154 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4155 | "@ | |
d40c829f UW |
4156 | sdbr\t%0,%2 |
4157 | sdb\t%0,%2" | |
ce50cae8 | 4158 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4159 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 | 4160 | |
3ef093a8 AK |
4161 | (define_insn "*subdf3_cc" |
4162 | [(set (reg 33) | |
4dbb5970 | 4163 | (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0") |
3ef093a8 AK |
4164 | (match_operand:DF 2 "general_operand" "f,R")) |
4165 | (match_operand:DF 3 "const0_operand" ""))) | |
4166 | (set (match_operand:DF 0 "register_operand" "=f,f") | |
db09b5b6 | 4167 | (minus:DF (match_dup 1) (match_dup 2)))] |
3ef093a8 AK |
4168 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4169 | "@ | |
d40c829f UW |
4170 | sdbr\t%0,%2 |
4171 | sdb\t%0,%2" | |
3ef093a8 AK |
4172 | [(set_attr "op_type" "RRE,RXE") |
4173 | (set_attr "type" "fsimpd,fsimpd")]) | |
4174 | ||
4175 | (define_insn "*subdf3_cconly" | |
4176 | [(set (reg 33) | |
4dbb5970 | 4177 | (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0") |
3ef093a8 AK |
4178 | (match_operand:DF 2 "general_operand" "f,R")) |
4179 | (match_operand:DF 3 "const0_operand" ""))) | |
4180 | (clobber (match_scratch:DF 0 "=f,f"))] | |
4181 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4182 | "@ | |
d40c829f UW |
4183 | sdbr\t%0,%2 |
4184 | sdb\t%0,%2" | |
3ef093a8 AK |
4185 | [(set_attr "op_type" "RRE,RXE") |
4186 | (set_attr "type" "fsimpd,fsimpd")]) | |
4187 | ||
9db1d521 HP |
4188 | (define_insn "*subdf3_ibm" |
4189 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4190 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 4191 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4192 | (clobber (reg:CC 33))] |
4193 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
4194 | "@ | |
d40c829f UW |
4195 | sdr\t%0,%2 |
4196 | sd\t%0,%2" | |
9db1d521 | 4197 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4198 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 HP |
4199 | |
4200 | ; | |
4201 | ; subsf3 instruction pattern(s). | |
4202 | ; | |
4203 | ||
4204 | (define_expand "subsf3" | |
4205 | [(parallel | |
4206 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4207 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4208 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4209 | (clobber (reg:CC 33))])] |
4210 | "TARGET_HARD_FLOAT" | |
4211 | "") | |
4212 | ||
4213 | (define_insn "*subsf3" | |
4214 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4215 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4216 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4217 | (clobber (reg:CC 33))] |
4218 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4219 | "@ | |
d40c829f UW |
4220 | sebr\t%0,%2 |
4221 | seb\t%0,%2" | |
ce50cae8 | 4222 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4223 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 | 4224 | |
3ef093a8 AK |
4225 | (define_insn "*subsf3_cc" |
4226 | [(set (reg 33) | |
4dbb5970 | 4227 | (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0") |
3ef093a8 AK |
4228 | (match_operand:SF 2 "general_operand" "f,R")) |
4229 | (match_operand:SF 3 "const0_operand" ""))) | |
4230 | (set (match_operand:SF 0 "register_operand" "=f,f") | |
4231 | (minus:SF (match_dup 1) (match_dup 2)))] | |
4232 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4233 | "@ | |
d40c829f UW |
4234 | sebr\t%0,%2 |
4235 | seb\t%0,%2" | |
3ef093a8 AK |
4236 | [(set_attr "op_type" "RRE,RXE") |
4237 | (set_attr "type" "fsimps,fsimps")]) | |
4238 | ||
4239 | (define_insn "*subsf3_cconly" | |
4240 | [(set (reg 33) | |
4dbb5970 | 4241 | (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0") |
3ef093a8 AK |
4242 | (match_operand:SF 2 "general_operand" "f,R")) |
4243 | (match_operand:SF 3 "const0_operand" ""))) | |
4244 | (clobber (match_scratch:SF 0 "=f,f"))] | |
4245 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4246 | "@ | |
d40c829f UW |
4247 | sebr\t%0,%2 |
4248 | seb\t%0,%2" | |
3ef093a8 AK |
4249 | [(set_attr "op_type" "RRE,RXE") |
4250 | (set_attr "type" "fsimps,fsimps")]) | |
4251 | ||
9db1d521 HP |
4252 | (define_insn "*subsf3_ibm" |
4253 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4254 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4255 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4256 | (clobber (reg:CC 33))] |
4257 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
4258 | "@ | |
d40c829f UW |
4259 | ser\t%0,%2 |
4260 | se\t%0,%2" | |
9db1d521 | 4261 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4262 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 HP |
4263 | |
4264 | ||
e69166de UW |
4265 | ;; |
4266 | ;;- Conditional add/subtract instructions. | |
4267 | ;; | |
4268 | ||
4269 | ; | |
4270 | ; adddicc instruction pattern(s). | |
4271 | ; | |
4272 | ||
4273 | (define_insn "*adddi3_alc_cc" | |
2f7e5a0d | 4274 | [(set (reg 33) |
e69166de UW |
4275 | (compare |
4276 | (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
4277 | (match_operand:DI 2 "general_operand" "d,m")) | |
4278 | (match_operand:DI 3 "s390_alc_comparison" "")) | |
4279 | (const_int 0))) | |
4280 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4281 | (plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 4282 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
e69166de | 4283 | "@ |
fc0ea003 UW |
4284 | alcgr\t%0,%2 |
4285 | alcg\t%0,%2" | |
e69166de UW |
4286 | [(set_attr "op_type" "RRE,RXY")]) |
4287 | ||
4288 | (define_insn "*adddi3_alc" | |
4289 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4290 | (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
4291 | (match_operand:DI 2 "general_operand" "d,m")) | |
4292 | (match_operand:DI 3 "s390_alc_comparison" ""))) | |
2f7e5a0d EC |
4293 | (clobber (reg:CC 33))] |
4294 | "TARGET_64BIT" | |
e69166de | 4295 | "@ |
fc0ea003 UW |
4296 | alcgr\t%0,%2 |
4297 | alcg\t%0,%2" | |
e69166de UW |
4298 | [(set_attr "op_type" "RRE,RXY")]) |
4299 | ||
4300 | (define_insn "*subdi3_slb_cc" | |
2f7e5a0d | 4301 | [(set (reg 33) |
e69166de UW |
4302 | (compare |
4303 | (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
4304 | (match_operand:DI 2 "general_operand" "d,m")) | |
4305 | (match_operand:DI 3 "s390_slb_comparison" "")) | |
4306 | (const_int 0))) | |
4307 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4308 | (minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 4309 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
e69166de | 4310 | "@ |
fc0ea003 UW |
4311 | slbgr\t%0,%2 |
4312 | slbg\t%0,%2" | |
e69166de UW |
4313 | [(set_attr "op_type" "RRE,RXY")]) |
4314 | ||
4315 | (define_insn "*subdi3_slb" | |
4316 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4317 | (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
4318 | (match_operand:DI 2 "general_operand" "d,m")) | |
4319 | (match_operand:DI 3 "s390_slb_comparison" ""))) | |
2f7e5a0d EC |
4320 | (clobber (reg:CC 33))] |
4321 | "TARGET_64BIT" | |
e69166de | 4322 | "@ |
fc0ea003 UW |
4323 | slbgr\t%0,%2 |
4324 | slbg\t%0,%2" | |
e69166de UW |
4325 | [(set_attr "op_type" "RRE,RXY")]) |
4326 | ||
5d880bd2 UW |
4327 | (define_expand "adddicc" |
4328 | [(match_operand:DI 0 "register_operand" "") | |
4329 | (match_operand 1 "comparison_operator" "") | |
4330 | (match_operand:DI 2 "register_operand" "") | |
4331 | (match_operand:DI 3 "const_int_operand" "")] | |
4332 | "TARGET_64BIT" | |
4333 | "if (!s390_expand_addcc (GET_CODE (operands[1]), | |
4334 | s390_compare_op0, s390_compare_op1, | |
4335 | operands[0], operands[2], | |
4336 | operands[3])) FAIL; DONE;") | |
4337 | ||
e69166de UW |
4338 | ; |
4339 | ; addsicc instruction pattern(s). | |
4340 | ; | |
4341 | ||
4342 | (define_insn "*addsi3_alc_cc" | |
2f7e5a0d | 4343 | [(set (reg 33) |
e69166de UW |
4344 | (compare |
4345 | (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
4346 | (match_operand:SI 2 "general_operand" "d,m")) | |
4347 | (match_operand:SI 3 "s390_alc_comparison" "")) | |
4348 | (const_int 0))) | |
4349 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
4350 | (plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 4351 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 4352 | "@ |
fc0ea003 UW |
4353 | alcr\t%0,%2 |
4354 | alc\t%0,%2" | |
e69166de UW |
4355 | [(set_attr "op_type" "RRE,RXY")]) |
4356 | ||
4357 | (define_insn "*addsi3_alc" | |
4358 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4359 | (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
4360 | (match_operand:SI 2 "general_operand" "d,m")) | |
4361 | (match_operand:SI 3 "s390_alc_comparison" ""))) | |
4362 | (clobber (reg:CC 33))] | |
2f7e5a0d | 4363 | "TARGET_CPU_ZARCH" |
e69166de | 4364 | "@ |
fc0ea003 UW |
4365 | alcr\t%0,%2 |
4366 | alc\t%0,%2" | |
e69166de UW |
4367 | [(set_attr "op_type" "RRE,RXY")]) |
4368 | ||
4369 | (define_insn "*subsi3_slb_cc" | |
2f7e5a0d | 4370 | [(set (reg 33) |
e69166de UW |
4371 | (compare |
4372 | (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
4373 | (match_operand:SI 2 "general_operand" "d,m")) | |
4374 | (match_operand:SI 3 "s390_slb_comparison" "")) | |
4375 | (const_int 0))) | |
4376 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
4377 | (minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 4378 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 4379 | "@ |
fc0ea003 UW |
4380 | slbr\t%0,%2 |
4381 | slb\t%0,%2" | |
e69166de UW |
4382 | [(set_attr "op_type" "RRE,RXY")]) |
4383 | ||
4384 | (define_insn "*subsi3_slb" | |
4385 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4386 | (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
4387 | (match_operand:SI 2 "general_operand" "d,m")) | |
4388 | (match_operand:SI 3 "s390_slb_comparison" ""))) | |
2f7e5a0d EC |
4389 | (clobber (reg:CC 33))] |
4390 | "TARGET_CPU_ZARCH" | |
e69166de | 4391 | "@ |
fc0ea003 UW |
4392 | slbr\t%0,%2 |
4393 | slb\t%0,%2" | |
e69166de UW |
4394 | [(set_attr "op_type" "RRE,RXY")]) |
4395 | ||
5d880bd2 UW |
4396 | (define_expand "addsicc" |
4397 | [(match_operand:SI 0 "register_operand" "") | |
4398 | (match_operand 1 "comparison_operator" "") | |
4399 | (match_operand:SI 2 "register_operand" "") | |
4400 | (match_operand:SI 3 "const_int_operand" "")] | |
4401 | "TARGET_CPU_ZARCH" | |
4402 | "if (!s390_expand_addcc (GET_CODE (operands[1]), | |
4403 | s390_compare_op0, s390_compare_op1, | |
4404 | operands[0], operands[2], | |
4405 | operands[3])) FAIL; DONE;") | |
4406 | ||
4407 | ; | |
4408 | ; scond instruction pattern(s). | |
4409 | ; | |
4410 | ||
4411 | (define_insn_and_split "*sconddi" | |
4412 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
4413 | (match_operand:DI 1 "s390_alc_comparison" "")) | |
4414 | (clobber (reg:CC 33))] | |
4415 | "TARGET_64BIT" | |
4416 | "#" | |
4417 | "&& reload_completed" | |
4418 | [(set (match_dup 0) (const_int 0)) | |
4419 | (parallel | |
4420 | [(set (match_dup 0) (plus:DI (plus:DI (match_dup 0) (match_dup 0)) | |
4421 | (match_dup 1))) | |
4422 | (clobber (reg:CC 33))])] | |
b628bd8e | 4423 | "") |
5d880bd2 UW |
4424 | |
4425 | (define_insn_and_split "*scondsi" | |
4426 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
4427 | (match_operand:SI 1 "s390_alc_comparison" "")) | |
4428 | (clobber (reg:CC 33))] | |
4429 | "TARGET_CPU_ZARCH" | |
4430 | "#" | |
4431 | "&& reload_completed" | |
4432 | [(set (match_dup 0) (const_int 0)) | |
4433 | (parallel | |
4434 | [(set (match_dup 0) (plus:SI (plus:SI (match_dup 0) (match_dup 0)) | |
4435 | (match_dup 1))) | |
4436 | (clobber (reg:CC 33))])] | |
b628bd8e | 4437 | "") |
5d880bd2 UW |
4438 | |
4439 | (define_insn_and_split "*sconddi_neg" | |
4440 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
4441 | (match_operand:DI 1 "s390_slb_comparison" "")) | |
4442 | (clobber (reg:CC 33))] | |
4443 | "TARGET_64BIT" | |
4444 | "#" | |
4445 | "&& reload_completed" | |
4446 | [(set (match_dup 0) (const_int 0)) | |
4447 | (parallel | |
4448 | [(set (match_dup 0) (minus:DI (minus:DI (match_dup 0) (match_dup 0)) | |
4449 | (match_dup 1))) | |
4450 | (clobber (reg:CC 33))]) | |
4451 | (parallel | |
4452 | [(set (match_dup 0) (neg:DI (match_dup 0))) | |
4453 | (clobber (reg:CC 33))])] | |
b628bd8e | 4454 | "") |
5d880bd2 UW |
4455 | |
4456 | (define_insn_and_split "*scondsi_neg" | |
4457 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
4458 | (match_operand:SI 1 "s390_slb_comparison" "")) | |
4459 | (clobber (reg:CC 33))] | |
4460 | "TARGET_CPU_ZARCH" | |
4461 | "#" | |
4462 | "&& reload_completed" | |
4463 | [(set (match_dup 0) (const_int 0)) | |
4464 | (parallel | |
4465 | [(set (match_dup 0) (minus:SI (minus:SI (match_dup 0) (match_dup 0)) | |
4466 | (match_dup 1))) | |
4467 | (clobber (reg:CC 33))]) | |
4468 | (parallel | |
4469 | [(set (match_dup 0) (neg:SI (match_dup 0))) | |
4470 | (clobber (reg:CC 33))])] | |
b628bd8e | 4471 | "") |
5d880bd2 UW |
4472 | |
4473 | (define_expand "sltu" | |
4474 | [(match_operand:SI 0 "register_operand" "")] | |
4475 | "TARGET_CPU_ZARCH" | |
4476 | "if (!s390_expand_addcc (LTU, s390_compare_op0, s390_compare_op1, | |
4477 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") | |
4478 | ||
4479 | (define_expand "sgtu" | |
4480 | [(match_operand:SI 0 "register_operand" "")] | |
4481 | "TARGET_CPU_ZARCH" | |
4482 | "if (!s390_expand_addcc (GTU, s390_compare_op0, s390_compare_op1, | |
4483 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") | |
4484 | ||
4485 | (define_expand "sleu" | |
4486 | [(match_operand:SI 0 "register_operand" "")] | |
4487 | "TARGET_CPU_ZARCH" | |
4488 | "if (!s390_expand_addcc (LEU, s390_compare_op0, s390_compare_op1, | |
4489 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") | |
4490 | ||
4491 | (define_expand "sgeu" | |
4492 | [(match_operand:SI 0 "register_operand" "")] | |
4493 | "TARGET_CPU_ZARCH" | |
4494 | "if (!s390_expand_addcc (GEU, s390_compare_op0, s390_compare_op1, | |
4495 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") | |
4496 | ||
e69166de | 4497 | |
9db1d521 HP |
4498 | ;; |
4499 | ;;- Multiply instructions. | |
4500 | ;; | |
4501 | ||
4023fb28 UW |
4502 | ; |
4503 | ; muldi3 instruction pattern(s). | |
4504 | ; | |
9db1d521 | 4505 | |
07893d4f UW |
4506 | (define_insn "*muldi3_sign" |
4507 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4508 | (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")) | |
4509 | (match_operand:DI 1 "register_operand" "0,0")))] | |
4510 | "TARGET_64BIT" | |
4511 | "@ | |
d40c829f UW |
4512 | msgfr\t%0,%2 |
4513 | msgf\t%0,%2" | |
d3632d41 | 4514 | [(set_attr "op_type" "RRE,RXY") |
07893d4f UW |
4515 | (set_attr "type" "imul")]) |
4516 | ||
4023fb28 | 4517 | (define_insn "muldi3" |
9db1d521 | 4518 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
96fd3851 | 4519 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
07893d4f | 4520 | (match_operand:DI 2 "general_operand" "d,K,m")))] |
9db1d521 HP |
4521 | "TARGET_64BIT" |
4522 | "@ | |
d40c829f UW |
4523 | msgr\t%0,%2 |
4524 | mghi\t%0,%h2 | |
4525 | msg\t%0,%2" | |
d3632d41 | 4526 | [(set_attr "op_type" "RRE,RI,RXY") |
f2d3c02a HP |
4527 | (set_attr "type" "imul")]) |
4528 | ||
9db1d521 HP |
4529 | ; |
4530 | ; mulsi3 instruction pattern(s). | |
4531 | ; | |
4532 | ||
f1e77d83 UW |
4533 | (define_insn "*mulsi3_sign" |
4534 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4535 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R")) | |
4536 | (match_operand:SI 1 "register_operand" "0")))] | |
4537 | "" | |
4538 | "mh\t%0,%2" | |
4539 | [(set_attr "op_type" "RX") | |
4540 | (set_attr "type" "imul")]) | |
4541 | ||
9db1d521 | 4542 | (define_insn "mulsi3" |
d3632d41 UW |
4543 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4544 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
4545 | (match_operand:SI 2 "general_operand" "d,K,R,T")))] | |
9db1d521 HP |
4546 | "" |
4547 | "@ | |
d40c829f UW |
4548 | msr\t%0,%2 |
4549 | mhi\t%0,%h2 | |
4550 | ms\t%0,%2 | |
4551 | msy\t%0,%2" | |
d3632d41 | 4552 | [(set_attr "op_type" "RRE,RI,RX,RXY") |
f2d3c02a | 4553 | (set_attr "type" "imul")]) |
9db1d521 | 4554 | |
4023fb28 UW |
4555 | ; |
4556 | ; mulsidi3 instruction pattern(s). | |
4557 | ; | |
4558 | ||
f1e77d83 UW |
4559 | (define_insn "mulsidi3" |
4560 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4561 | (mult:DI (sign_extend:DI | |
4562 | (match_operand:SI 1 "register_operand" "%0,0")) | |
4563 | (sign_extend:DI | |
4564 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))] | |
4023fb28 | 4565 | "!TARGET_64BIT" |
f1e77d83 UW |
4566 | "@ |
4567 | mr\t%0,%2 | |
4568 | m\t%0,%2" | |
4569 | [(set_attr "op_type" "RR,RX") | |
4570 | (set_attr "type" "imul")]) | |
4023fb28 | 4571 | |
f1e77d83 UW |
4572 | ; |
4573 | ; umulsidi3 instruction pattern(s). | |
4574 | ; | |
c7453384 | 4575 | |
f1e77d83 UW |
4576 | (define_insn "umulsidi3" |
4577 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4578 | (mult:DI (zero_extend:DI | |
4579 | (match_operand:SI 1 "register_operand" "%0,0")) | |
4580 | (zero_extend:DI | |
4581 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))] | |
4582 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4583 | "@ | |
4584 | mlr\t%0,%2 | |
4585 | ml\t%0,%2" | |
4586 | [(set_attr "op_type" "RRE,RXY") | |
f2d3c02a | 4587 | (set_attr "type" "imul")]) |
c7453384 | 4588 | |
9db1d521 HP |
4589 | ; |
4590 | ; muldf3 instruction pattern(s). | |
4591 | ; | |
4592 | ||
4593 | (define_expand "muldf3" | |
553e5ce9 UW |
4594 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
4595 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
4596 | (match_operand:DF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4597 | "TARGET_HARD_FLOAT" |
4598 | "") | |
4599 | ||
4600 | (define_insn "*muldf3" | |
4601 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 4602 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4603 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4604 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4605 | "@ | |
d40c829f UW |
4606 | mdbr\t%0,%2 |
4607 | mdb\t%0,%2" | |
ce50cae8 | 4608 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4609 | (set_attr "type" "fmuld")]) |
9db1d521 HP |
4610 | |
4611 | (define_insn "*muldf3_ibm" | |
4612 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 4613 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4614 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4615 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4616 | "@ | |
d40c829f UW |
4617 | mdr\t%0,%2 |
4618 | md\t%0,%2" | |
9db1d521 | 4619 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4620 | (set_attr "type" "fmuld")]) |
9db1d521 | 4621 | |
a1b892b5 AK |
4622 | (define_insn "*fmadddf" |
4623 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4624 | (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f") | |
4625 | (match_operand:DF 2 "nonimmediate_operand" "f,R")) | |
4626 | (match_operand:DF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4627 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4628 | "@ |
4629 | madbr\t%0,%1,%2 | |
4630 | madb\t%0,%1,%2" | |
4631 | [(set_attr "op_type" "RRE,RXE") | |
4632 | (set_attr "type" "fmuld")]) | |
4633 | ||
4634 | (define_insn "*fmsubdf" | |
4635 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4636 | (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f") | |
4637 | (match_operand:DF 2 "nonimmediate_operand" "f,R")) | |
4638 | (match_operand:DF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4639 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4640 | "@ |
4641 | msdbr\t%0,%1,%2 | |
4642 | msdb\t%0,%1,%2" | |
4643 | [(set_attr "op_type" "RRE,RXE") | |
4644 | (set_attr "type" "fmuld")]) | |
4645 | ||
9db1d521 HP |
4646 | ; |
4647 | ; mulsf3 instruction pattern(s). | |
4648 | ; | |
4649 | ||
4650 | (define_expand "mulsf3" | |
553e5ce9 UW |
4651 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
4652 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
4653 | (match_operand:SF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4654 | "TARGET_HARD_FLOAT" |
4655 | "") | |
4656 | ||
4657 | (define_insn "*mulsf3" | |
4658 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 4659 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4660 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4661 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4662 | "@ | |
d40c829f UW |
4663 | meebr\t%0,%2 |
4664 | meeb\t%0,%2" | |
ce50cae8 | 4665 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4666 | (set_attr "type" "fmuls")]) |
9db1d521 HP |
4667 | |
4668 | (define_insn "*mulsf3_ibm" | |
4669 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 4670 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4671 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4672 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4673 | "@ | |
d40c829f UW |
4674 | mer\t%0,%2 |
4675 | me\t%0,%2" | |
9db1d521 | 4676 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4677 | (set_attr "type" "fmuls")]) |
9db1d521 | 4678 | |
a1b892b5 AK |
4679 | (define_insn "*fmaddsf" |
4680 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4681 | (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f") | |
4682 | (match_operand:SF 2 "nonimmediate_operand" "f,R")) | |
4683 | (match_operand:SF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4684 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4685 | "@ |
4686 | maebr\t%0,%1,%2 | |
4687 | maeb\t%0,%1,%2" | |
4688 | [(set_attr "op_type" "RRE,RXE") | |
4689 | (set_attr "type" "fmuls")]) | |
4690 | ||
4691 | (define_insn "*fmsubsf" | |
4692 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4693 | (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f") | |
4694 | (match_operand:SF 2 "nonimmediate_operand" "f,R")) | |
4695 | (match_operand:SF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4696 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4697 | "@ |
4698 | msebr\t%0,%1,%2 | |
4699 | mseb\t%0,%1,%2" | |
4700 | [(set_attr "op_type" "RRE,RXE") | |
4701 | (set_attr "type" "fmuls")]) | |
9db1d521 HP |
4702 | |
4703 | ;; | |
4704 | ;;- Divide and modulo instructions. | |
4705 | ;; | |
4706 | ||
4707 | ; | |
4023fb28 | 4708 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
4709 | ; |
4710 | ||
4023fb28 UW |
4711 | (define_expand "divmoddi4" |
4712 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 4713 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
4714 | (match_operand:DI 2 "general_operand" ""))) |
4715 | (set (match_operand:DI 3 "general_operand" "") | |
4716 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
4717 | (clobber (match_dup 4))] | |
9db1d521 | 4718 | "TARGET_64BIT" |
9db1d521 | 4719 | { |
f1e77d83 | 4720 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
4721 | |
4722 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
4723 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
4724 | |
4725 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 4726 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
4727 | |
4728 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4729 | REG_NOTES (insn) = | |
4730 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4731 | ||
4732 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4733 | REG_NOTES (insn) = | |
4734 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4735 | |
9db1d521 | 4736 | DONE; |
10bbf137 | 4737 | }) |
9db1d521 HP |
4738 | |
4739 | (define_insn "divmodtidi3" | |
4023fb28 UW |
4740 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
4741 | (ior:TI | |
4023fb28 UW |
4742 | (ashift:TI |
4743 | (zero_extend:TI | |
5665e398 UW |
4744 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
4745 | (match_operand:DI 2 "general_operand" "d,m"))) | |
4746 | (const_int 64)) | |
4747 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9db1d521 HP |
4748 | "TARGET_64BIT" |
4749 | "@ | |
d40c829f UW |
4750 | dsgr\t%0,%2 |
4751 | dsg\t%0,%2" | |
d3632d41 | 4752 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4753 | (set_attr "type" "idiv")]) |
9db1d521 | 4754 | |
4023fb28 UW |
4755 | (define_insn "divmodtisi3" |
4756 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
4757 | (ior:TI | |
4023fb28 UW |
4758 | (ashift:TI |
4759 | (zero_extend:TI | |
5665e398 | 4760 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 4761 | (sign_extend:DI |
5665e398 UW |
4762 | (match_operand:SI 2 "nonimmediate_operand" "d,m")))) |
4763 | (const_int 64)) | |
4764 | (zero_extend:TI | |
4765 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9db1d521 | 4766 | "TARGET_64BIT" |
4023fb28 | 4767 | "@ |
d40c829f UW |
4768 | dsgfr\t%0,%2 |
4769 | dsgf\t%0,%2" | |
d3632d41 | 4770 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4771 | (set_attr "type" "idiv")]) |
9db1d521 | 4772 | |
4023fb28 UW |
4773 | ; |
4774 | ; udivmoddi4 instruction pattern(s). | |
4775 | ; | |
9db1d521 | 4776 | |
4023fb28 UW |
4777 | (define_expand "udivmoddi4" |
4778 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
4779 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
4780 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
4781 | (set (match_operand:DI 3 "general_operand" "") | |
4782 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
4783 | (clobber (match_dup 4))] | |
9db1d521 | 4784 | "TARGET_64BIT" |
9db1d521 | 4785 | { |
4023fb28 UW |
4786 | rtx insn, div_equal, mod_equal, equal; |
4787 | ||
4788 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
4789 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
4790 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
4791 | gen_rtx_ASHIFT (TImode, |
4792 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
4793 | GEN_INT (64)), |
4794 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
4795 | |
4796 | operands[4] = gen_reg_rtx(TImode); | |
4797 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4798 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); | |
4799 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
4800 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); | |
4801 | REG_NOTES (insn) = | |
4802 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4803 | ||
4804 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4805 | REG_NOTES (insn) = | |
4806 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4807 | ||
4808 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4809 | REG_NOTES (insn) = | |
4810 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4811 | |
9db1d521 | 4812 | DONE; |
10bbf137 | 4813 | }) |
9db1d521 HP |
4814 | |
4815 | (define_insn "udivmodtidi3" | |
4023fb28 | 4816 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 4817 | (ior:TI |
5665e398 UW |
4818 | (ashift:TI |
4819 | (zero_extend:TI | |
4820 | (truncate:DI | |
2f7e5a0d EC |
4821 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
4822 | (zero_extend:TI | |
5665e398 UW |
4823 | (match_operand:DI 2 "nonimmediate_operand" "d,m"))))) |
4824 | (const_int 64)) | |
4825 | (zero_extend:TI | |
4826 | (truncate:DI | |
4827 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9db1d521 HP |
4828 | "TARGET_64BIT" |
4829 | "@ | |
d40c829f UW |
4830 | dlgr\t%0,%2 |
4831 | dlg\t%0,%2" | |
d3632d41 | 4832 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4833 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4834 | |
4835 | ; | |
4023fb28 | 4836 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
4837 | ; |
4838 | ||
4023fb28 UW |
4839 | (define_expand "divmodsi4" |
4840 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4841 | (div:SI (match_operand:SI 1 "general_operand" "") | |
4842 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4843 | (set (match_operand:SI 3 "general_operand" "") | |
4844 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
4845 | (clobber (match_dup 4))] | |
9db1d521 | 4846 | "!TARGET_64BIT" |
9db1d521 | 4847 | { |
4023fb28 UW |
4848 | rtx insn, div_equal, mod_equal, equal; |
4849 | ||
4850 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
4851 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
4852 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4853 | gen_rtx_ASHIFT (DImode, |
4854 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
4855 | GEN_INT (32)), |
4856 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
4857 | |
4858 | operands[4] = gen_reg_rtx(DImode); | |
4859 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
4860 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); | |
4861 | REG_NOTES (insn) = | |
4862 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4863 | ||
4864 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4865 | REG_NOTES (insn) = | |
4866 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4867 | ||
4868 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4869 | REG_NOTES (insn) = | |
4870 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4871 | |
9db1d521 | 4872 | DONE; |
10bbf137 | 4873 | }) |
9db1d521 HP |
4874 | |
4875 | (define_insn "divmoddisi3" | |
4023fb28 | 4876 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 4877 | (ior:DI |
5665e398 UW |
4878 | (ashift:DI |
4879 | (zero_extend:DI | |
4880 | (truncate:SI | |
2f7e5a0d EC |
4881 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
4882 | (sign_extend:DI | |
5665e398 UW |
4883 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
4884 | (const_int 32)) | |
4885 | (zero_extend:DI | |
4886 | (truncate:SI | |
4887 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9db1d521 HP |
4888 | "!TARGET_64BIT" |
4889 | "@ | |
d40c829f UW |
4890 | dr\t%0,%2 |
4891 | d\t%0,%2" | |
9db1d521 | 4892 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4893 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4894 | |
4895 | ; | |
4896 | ; udivsi3 and umodsi3 instruction pattern(s). | |
4897 | ; | |
4898 | ||
f1e77d83 UW |
4899 | (define_expand "udivmodsi4" |
4900 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4901 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4902 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4903 | (set (match_operand:SI 3 "general_operand" "") | |
4904 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
4905 | (clobber (match_dup 4))] | |
4906 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4907 | { | |
4908 | rtx insn, div_equal, mod_equal, equal; | |
4909 | ||
4910 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4911 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4912 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
4913 | gen_rtx_ASHIFT (DImode, |
4914 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
4915 | GEN_INT (32)), |
4916 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
4917 | |
4918 | operands[4] = gen_reg_rtx(DImode); | |
4919 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4920 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); | |
4921 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
4922 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); | |
4923 | REG_NOTES (insn) = | |
4924 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4925 | ||
4926 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4927 | REG_NOTES (insn) = | |
4928 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4929 | ||
4930 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4931 | REG_NOTES (insn) = | |
4932 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
4933 | ||
4934 | DONE; | |
4935 | }) | |
4936 | ||
4937 | (define_insn "udivmoddisi3" | |
4938 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 4939 | (ior:DI |
5665e398 UW |
4940 | (ashift:DI |
4941 | (zero_extend:DI | |
4942 | (truncate:SI | |
2f7e5a0d EC |
4943 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
4944 | (zero_extend:DI | |
5665e398 UW |
4945 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))) |
4946 | (const_int 32)) | |
4947 | (zero_extend:DI | |
4948 | (truncate:SI | |
4949 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
f1e77d83 UW |
4950 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
4951 | "@ | |
4952 | dlr\t%0,%2 | |
4953 | dl\t%0,%2" | |
4954 | [(set_attr "op_type" "RRE,RXY") | |
4955 | (set_attr "type" "idiv")]) | |
4023fb28 | 4956 | |
9db1d521 HP |
4957 | (define_expand "udivsi3" |
4958 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4959 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
4960 | (match_operand:SI 2 "general_operand" ""))) |
4961 | (clobber (match_dup 3))] | |
f1e77d83 | 4962 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 4963 | { |
4023fb28 UW |
4964 | rtx insn, udiv_equal, umod_equal, equal; |
4965 | ||
4966 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4967 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4968 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4969 | gen_rtx_ASHIFT (DImode, |
4970 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
4971 | GEN_INT (32)), |
4972 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 4973 | |
4023fb28 | 4974 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
4975 | |
4976 | if (CONSTANT_P (operands[2])) | |
4977 | { | |
4978 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
4979 | { | |
4980 | rtx label1 = gen_label_rtx (); | |
4981 | ||
4023fb28 UW |
4982 | operands[1] = make_safe_from (operands[1], operands[0]); |
4983 | emit_move_insn (operands[0], const0_rtx); | |
4984 | emit_insn (gen_cmpsi (operands[1], operands[2])); | |
9db1d521 | 4985 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 | 4986 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
4987 | emit_label (label1); |
4988 | } | |
4989 | else | |
4990 | { | |
c7453384 EC |
4991 | operands[2] = force_reg (SImode, operands[2]); |
4992 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4993 | |
4994 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4995 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4996 | operands[2])); | |
4997 | REG_NOTES (insn) = | |
4998 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4999 | |
5000 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
5001 | gen_lowpart (SImode, operands[3])); |
5002 | REG_NOTES (insn) = | |
c7453384 | 5003 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 5004 | udiv_equal, REG_NOTES (insn)); |
9db1d521 HP |
5005 | } |
5006 | } | |
5007 | else | |
c7453384 | 5008 | { |
9db1d521 HP |
5009 | rtx label1 = gen_label_rtx (); |
5010 | rtx label2 = gen_label_rtx (); | |
5011 | rtx label3 = gen_label_rtx (); | |
5012 | ||
c7453384 EC |
5013 | operands[1] = force_reg (SImode, operands[1]); |
5014 | operands[1] = make_safe_from (operands[1], operands[0]); | |
5015 | operands[2] = force_reg (SImode, operands[2]); | |
5016 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
5017 | |
5018 | emit_move_insn (operands[0], const0_rtx); | |
9db1d521 HP |
5019 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
5020 | emit_jump_insn (gen_bgtu (label3)); | |
220a826e | 5021 | emit_insn (gen_cmpsi (operands[2], const0_rtx)); |
9db1d521 HP |
5022 | emit_jump_insn (gen_blt (label2)); |
5023 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
5024 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
5025 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
5026 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5027 | operands[2])); | |
5028 | REG_NOTES (insn) = | |
5029 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
5030 | |
5031 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
5032 | gen_lowpart (SImode, operands[3])); |
5033 | REG_NOTES (insn) = | |
c7453384 | 5034 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 5035 | udiv_equal, REG_NOTES (insn)); |
f314b9b1 | 5036 | emit_jump (label3); |
9db1d521 | 5037 | emit_label (label1); |
4023fb28 | 5038 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 5039 | emit_jump (label3); |
9db1d521 | 5040 | emit_label (label2); |
4023fb28 | 5041 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
5042 | emit_label (label3); |
5043 | } | |
c7453384 | 5044 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 5045 | DONE; |
10bbf137 | 5046 | }) |
9db1d521 HP |
5047 | |
5048 | (define_expand "umodsi3" | |
5049 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5050 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
5051 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
5052 | (clobber (match_dup 3))] | |
f1e77d83 | 5053 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 5054 | { |
4023fb28 UW |
5055 | rtx insn, udiv_equal, umod_equal, equal; |
5056 | ||
5057 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
5058 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
5059 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
5060 | gen_rtx_ASHIFT (DImode, |
5061 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
5062 | GEN_INT (32)), |
5063 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 5064 | |
4023fb28 | 5065 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
5066 | |
5067 | if (CONSTANT_P (operands[2])) | |
5068 | { | |
5069 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
5070 | { | |
5071 | rtx label1 = gen_label_rtx (); | |
5072 | ||
4023fb28 UW |
5073 | operands[1] = make_safe_from (operands[1], operands[0]); |
5074 | emit_move_insn (operands[0], operands[1]); | |
5075 | emit_insn (gen_cmpsi (operands[0], operands[2])); | |
9db1d521 | 5076 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 UW |
5077 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
5078 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
5079 | emit_label (label1); |
5080 | } | |
5081 | else | |
5082 | { | |
c7453384 EC |
5083 | operands[2] = force_reg (SImode, operands[2]); |
5084 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
5085 | |
5086 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
5087 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5088 | operands[2])); | |
5089 | REG_NOTES (insn) = | |
5090 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
5091 | |
5092 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
5093 | gen_highpart (SImode, operands[3])); |
5094 | REG_NOTES (insn) = | |
c7453384 | 5095 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 5096 | umod_equal, REG_NOTES (insn)); |
9db1d521 HP |
5097 | } |
5098 | } | |
5099 | else | |
5100 | { | |
5101 | rtx label1 = gen_label_rtx (); | |
5102 | rtx label2 = gen_label_rtx (); | |
5103 | rtx label3 = gen_label_rtx (); | |
5104 | ||
c7453384 EC |
5105 | operands[1] = force_reg (SImode, operands[1]); |
5106 | operands[1] = make_safe_from (operands[1], operands[0]); | |
5107 | operands[2] = force_reg (SImode, operands[2]); | |
5108 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 5109 | |
c7453384 | 5110 | emit_move_insn(operands[0], operands[1]); |
4023fb28 | 5111 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
9db1d521 | 5112 | emit_jump_insn (gen_bgtu (label3)); |
220a826e | 5113 | emit_insn (gen_cmpsi (operands[2], const0_rtx)); |
9db1d521 HP |
5114 | emit_jump_insn (gen_blt (label2)); |
5115 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
5116 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
5117 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
5118 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5119 | operands[2])); | |
5120 | REG_NOTES (insn) = | |
5121 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
5122 | |
5123 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
5124 | gen_highpart (SImode, operands[3])); |
5125 | REG_NOTES (insn) = | |
c7453384 | 5126 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 5127 | umod_equal, REG_NOTES (insn)); |
f314b9b1 | 5128 | emit_jump (label3); |
9db1d521 | 5129 | emit_label (label1); |
4023fb28 | 5130 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 5131 | emit_jump (label3); |
9db1d521 | 5132 | emit_label (label2); |
4023fb28 | 5133 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
5134 | emit_label (label3); |
5135 | } | |
9db1d521 | 5136 | DONE; |
10bbf137 | 5137 | }) |
9db1d521 HP |
5138 | |
5139 | ; | |
5140 | ; divdf3 instruction pattern(s). | |
5141 | ; | |
5142 | ||
5143 | (define_expand "divdf3" | |
553e5ce9 UW |
5144 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
5145 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
5146 | (match_operand:DF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
5147 | "TARGET_HARD_FLOAT" |
5148 | "") | |
5149 | ||
5150 | (define_insn "*divdf3" | |
4023fb28 UW |
5151 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
5152 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
553e5ce9 | 5153 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
5154 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
5155 | "@ | |
d40c829f UW |
5156 | ddbr\t%0,%2 |
5157 | ddb\t%0,%2" | |
ce50cae8 | 5158 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 5159 | (set_attr "type" "fdivd")]) |
9db1d521 HP |
5160 | |
5161 | (define_insn "*divdf3_ibm" | |
4023fb28 UW |
5162 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
5163 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
553e5ce9 | 5164 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
5165 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
5166 | "@ | |
d40c829f UW |
5167 | ddr\t%0,%2 |
5168 | dd\t%0,%2" | |
9db1d521 | 5169 | [(set_attr "op_type" "RR,RX") |
077dab3b | 5170 | (set_attr "type" "fdivd")]) |
9db1d521 HP |
5171 | |
5172 | ; | |
5173 | ; divsf3 instruction pattern(s). | |
5174 | ; | |
5175 | ||
5176 | (define_expand "divsf3" | |
553e5ce9 UW |
5177 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
5178 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
5179 | (match_operand:SF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
5180 | "TARGET_HARD_FLOAT" |
5181 | "") | |
5182 | ||
5183 | (define_insn "*divsf3" | |
4023fb28 UW |
5184 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
5185 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
553e5ce9 | 5186 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
5187 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
5188 | "@ | |
d40c829f UW |
5189 | debr\t%0,%2 |
5190 | deb\t%0,%2" | |
ce50cae8 | 5191 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 5192 | (set_attr "type" "fdivs")]) |
9db1d521 HP |
5193 | |
5194 | (define_insn "*divsf3" | |
4023fb28 UW |
5195 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
5196 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
553e5ce9 | 5197 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
5198 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
5199 | "@ | |
d40c829f UW |
5200 | der\t%0,%2 |
5201 | de\t%0,%2" | |
9db1d521 | 5202 | [(set_attr "op_type" "RR,RX") |
077dab3b | 5203 | (set_attr "type" "fdivs")]) |
9db1d521 HP |
5204 | |
5205 | ||
5206 | ;; | |
5207 | ;;- And instructions. | |
5208 | ;; | |
5209 | ||
5210 | ; | |
5211 | ; anddi3 instruction pattern(s). | |
5212 | ; | |
5213 | ||
5214 | (define_insn "*anddi3_cc" | |
5215 | [(set (reg 33) | |
96fd3851 | 5216 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 5217 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 | 5218 | (const_int 0))) |
4023fb28 | 5219 | (set (match_operand:DI 0 "register_operand" "=d,d") |
9db1d521 HP |
5220 | (and:DI (match_dup 1) (match_dup 2)))] |
5221 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5222 | "@ | |
d40c829f UW |
5223 | ngr\t%0,%2 |
5224 | ng\t%0,%2" | |
d3632d41 | 5225 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 HP |
5226 | |
5227 | (define_insn "*anddi3_cconly" | |
5228 | [(set (reg 33) | |
96fd3851 | 5229 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 5230 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 HP |
5231 | (const_int 0))) |
5232 | (clobber (match_scratch:DI 0 "=d,d"))] | |
68f9c5e2 UW |
5233 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT |
5234 | /* Do not steal TM patterns. */ | |
5235 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 5236 | "@ |
d40c829f UW |
5237 | ngr\t%0,%2 |
5238 | ng\t%0,%2" | |
d3632d41 | 5239 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 5240 | |
8cb66696 | 5241 | (define_insn "*anddi3" |
0dfa6c5e | 5242 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") |
8cb66696 | 5243 | (and:DI (match_operand:DI 1 "nonimmediate_operand" |
0dfa6c5e | 5244 | "%d,o,0,0,0,0,0,0,0,0") |
8cb66696 | 5245 | (match_operand:DI 2 "general_operand" |
0dfa6c5e | 5246 | "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q"))) |
4023fb28 | 5247 | (clobber (reg:CC 33))] |
8cb66696 UW |
5248 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
5249 | "@ | |
5250 | # | |
5251 | # | |
5252 | nihh\t%0,%j2 | |
5253 | nihl\t%0,%j2 | |
5254 | nilh\t%0,%j2 | |
5255 | nill\t%0,%j2 | |
5256 | ngr\t%0,%2 | |
5257 | ng\t%0,%2 | |
0dfa6c5e | 5258 | # |
19b63d8e | 5259 | #" |
0dfa6c5e UW |
5260 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")]) |
5261 | ||
5262 | (define_split | |
5263 | [(set (match_operand:DI 0 "s_operand" "") | |
5264 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
5265 | (clobber (reg:CC 33))] | |
5266 | "reload_completed" | |
5267 | [(parallel | |
5268 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
5269 | (clobber (reg:CC 33))])] | |
5270 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") | |
4023fb28 | 5271 | |
8cb66696 UW |
5272 | (define_expand "anddi3" |
5273 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
5274 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
5275 | (match_operand:DI 2 "general_operand" ""))) | |
4023fb28 | 5276 | (clobber (reg:CC 33))] |
8cb66696 UW |
5277 | "TARGET_64BIT" |
5278 | "s390_expand_logical_operator (AND, DImode, operands); DONE;") | |
9db1d521 HP |
5279 | |
5280 | ; | |
5281 | ; andsi3 instruction pattern(s). | |
5282 | ; | |
5283 | ||
5284 | (define_insn "*andsi3_cc" | |
5285 | [(set (reg 33) | |
d3632d41 UW |
5286 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5287 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 5288 | (const_int 0))) |
d3632d41 | 5289 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 HP |
5290 | (and:SI (match_dup 1) (match_dup 2)))] |
5291 | "s390_match_ccmode(insn, CCTmode)" | |
5292 | "@ | |
d40c829f UW |
5293 | nr\t%0,%2 |
5294 | n\t%0,%2 | |
5295 | ny\t%0,%2" | |
d3632d41 | 5296 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
5297 | |
5298 | (define_insn "*andsi3_cconly" | |
5299 | [(set (reg 33) | |
d3632d41 UW |
5300 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5301 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 5302 | (const_int 0))) |
d3632d41 | 5303 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
68f9c5e2 UW |
5304 | "s390_match_ccmode(insn, CCTmode) |
5305 | /* Do not steal TM patterns. */ | |
5306 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 5307 | "@ |
d40c829f UW |
5308 | nr\t%0,%2 |
5309 | n\t%0,%2 | |
5310 | ny\t%0,%2" | |
d3632d41 | 5311 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 5312 | |
f19a9af7 | 5313 | (define_insn "*andsi3_zarch" |
0dfa6c5e UW |
5314 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,AQ,Q") |
5315 | (and:SI (match_operand:SI 1 "nonimmediate_operand" | |
5316 | "%d,o,0,0,0,0,0,0,0") | |
5317 | (match_operand:SI 2 "general_operand" | |
5318 | "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q"))) | |
9db1d521 | 5319 | (clobber (reg:CC 33))] |
8cb66696 | 5320 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5321 | "@ |
f19a9af7 AK |
5322 | # |
5323 | # | |
5324 | nilh\t%0,%j2 | |
2f7e5a0d | 5325 | nill\t%0,%j2 |
d40c829f UW |
5326 | nr\t%0,%2 |
5327 | n\t%0,%2 | |
8cb66696 | 5328 | ny\t%0,%2 |
0dfa6c5e | 5329 | # |
19b63d8e | 5330 | #" |
0dfa6c5e | 5331 | [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SI,SS")]) |
f19a9af7 AK |
5332 | |
5333 | (define_insn "*andsi3_esa" | |
0dfa6c5e UW |
5334 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5335 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
5336 | (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q"))) | |
f19a9af7 | 5337 | (clobber (reg:CC 33))] |
8cb66696 | 5338 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
5339 | "@ |
5340 | nr\t%0,%2 | |
8cb66696 | 5341 | n\t%0,%2 |
0dfa6c5e | 5342 | # |
19b63d8e | 5343 | #" |
0dfa6c5e UW |
5344 | [(set_attr "op_type" "RR,RX,SI,SS")]) |
5345 | ||
5346 | (define_split | |
5347 | [(set (match_operand:SI 0 "s_operand" "") | |
5348 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
5349 | (clobber (reg:CC 33))] | |
5350 | "reload_completed" | |
5351 | [(parallel | |
5352 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
5353 | (clobber (reg:CC 33))])] | |
5354 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") | |
4023fb28 | 5355 | |
8cb66696 UW |
5356 | (define_expand "andsi3" |
5357 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
5358 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
5359 | (match_operand:SI 2 "general_operand" ""))) | |
4023fb28 UW |
5360 | (clobber (reg:CC 33))] |
5361 | "" | |
8cb66696 | 5362 | "s390_expand_logical_operator (AND, SImode, operands); DONE;") |
9db1d521 HP |
5363 | |
5364 | ; | |
5365 | ; andhi3 instruction pattern(s). | |
5366 | ; | |
5367 | ||
8cb66696 | 5368 | (define_insn "*andhi3_zarch" |
0dfa6c5e UW |
5369 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5370 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
5371 | (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q"))) | |
4023fb28 | 5372 | (clobber (reg:CC 33))] |
8cb66696 | 5373 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5374 | "@ |
d40c829f | 5375 | nr\t%0,%2 |
8cb66696 | 5376 | nill\t%0,%x2 |
0dfa6c5e | 5377 | # |
19b63d8e | 5378 | #" |
0dfa6c5e | 5379 | [(set_attr "op_type" "RR,RI,SI,SS")]) |
8cb66696 UW |
5380 | |
5381 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
5382 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
5383 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
5384 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
4023fb28 | 5385 | (clobber (reg:CC 33))] |
8cb66696 UW |
5386 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
5387 | "@ | |
5388 | nr\t%0,%2 | |
0dfa6c5e | 5389 | # |
19b63d8e | 5390 | #" |
0dfa6c5e UW |
5391 | [(set_attr "op_type" "RR,SI,SS")]) |
5392 | ||
5393 | (define_split | |
5394 | [(set (match_operand:HI 0 "s_operand" "") | |
5395 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
5396 | (clobber (reg:CC 33))] | |
5397 | "reload_completed" | |
5398 | [(parallel | |
5399 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
5400 | (clobber (reg:CC 33))])] | |
5401 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") | |
9db1d521 | 5402 | |
8cb66696 UW |
5403 | (define_expand "andhi3" |
5404 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
5405 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
5406 | (match_operand:HI 2 "general_operand" ""))) | |
9db1d521 HP |
5407 | (clobber (reg:CC 33))] |
5408 | "" | |
8cb66696 | 5409 | "s390_expand_logical_operator (AND, HImode, operands); DONE;") |
9db1d521 HP |
5410 | |
5411 | ; | |
5412 | ; andqi3 instruction pattern(s). | |
5413 | ; | |
5414 | ||
8cb66696 UW |
5415 | (define_insn "*andqi3_zarch" |
5416 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
5417 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5418 | (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
4023fb28 | 5419 | (clobber (reg:CC 33))] |
8cb66696 | 5420 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5421 | "@ |
d40c829f | 5422 | nr\t%0,%2 |
8cb66696 | 5423 | nill\t%0,%b2 |
fc0ea003 UW |
5424 | ni\t%S0,%b2 |
5425 | niy\t%S0,%b2 | |
19b63d8e | 5426 | #" |
8cb66696 UW |
5427 | [(set_attr "op_type" "RR,RI,SI,SIY,SS")]) |
5428 | ||
5429 | (define_insn "*andqi3_esa" | |
5430 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
5431 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
5432 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
9db1d521 | 5433 | (clobber (reg:CC 33))] |
8cb66696 | 5434 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5435 | "@ |
8cb66696 | 5436 | nr\t%0,%2 |
fc0ea003 | 5437 | ni\t%S0,%b2 |
19b63d8e | 5438 | #" |
8cb66696 | 5439 | [(set_attr "op_type" "RR,SI,SS")]) |
4023fb28 | 5440 | |
8cb66696 UW |
5441 | (define_expand "andqi3" |
5442 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
5443 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
5444 | (match_operand:QI 2 "general_operand" ""))) | |
4023fb28 UW |
5445 | (clobber (reg:CC 33))] |
5446 | "" | |
8cb66696 | 5447 | "s390_expand_logical_operator (AND, QImode, operands); DONE;") |
9db1d521 | 5448 | |
19b63d8e UW |
5449 | ; |
5450 | ; Block and (NC) patterns. | |
5451 | ; | |
5452 | ||
5453 | (define_insn "*nc" | |
5454 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5455 | (and:BLK (match_dup 0) | |
5456 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5457 | (use (match_operand 2 "const_int_operand" "n")) | |
5458 | (clobber (reg:CC 33))] | |
5459 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 5460 | "nc\t%O0(%2,%R0),%S1" |
b628bd8e | 5461 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5462 | |
5463 | (define_split | |
5464 | [(set (match_operand 0 "memory_operand" "") | |
5465 | (and (match_dup 0) | |
5466 | (match_operand 1 "memory_operand" ""))) | |
5467 | (clobber (reg:CC 33))] | |
5468 | "reload_completed | |
5469 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5470 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
5471 | [(parallel | |
5472 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
5473 | (use (match_dup 2)) | |
5474 | (clobber (reg:CC 33))])] | |
5475 | { | |
5476 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
5477 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
5478 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
5479 | }) | |
5480 | ||
5481 | (define_peephole2 | |
5482 | [(parallel | |
5483 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5484 | (and:BLK (match_dup 0) | |
5485 | (match_operand:BLK 1 "memory_operand" ""))) | |
5486 | (use (match_operand 2 "const_int_operand" "")) | |
5487 | (clobber (reg:CC 33))]) | |
5488 | (parallel | |
5489 | [(set (match_operand:BLK 3 "memory_operand" "") | |
5490 | (and:BLK (match_dup 3) | |
5491 | (match_operand:BLK 4 "memory_operand" ""))) | |
5492 | (use (match_operand 5 "const_int_operand" "")) | |
5493 | (clobber (reg:CC 33))])] | |
5494 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
5495 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
5496 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" | |
5497 | [(parallel | |
5498 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
5499 | (use (match_dup 8)) | |
5500 | (clobber (reg:CC 33))])] | |
5501 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
5502 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
5503 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
5504 | ||
9db1d521 HP |
5505 | |
5506 | ;; | |
5507 | ;;- Bit set (inclusive or) instructions. | |
5508 | ;; | |
5509 | ||
5510 | ; | |
5511 | ; iordi3 instruction pattern(s). | |
5512 | ; | |
5513 | ||
4023fb28 UW |
5514 | (define_insn "*iordi3_cc" |
5515 | [(set (reg 33) | |
96fd3851 | 5516 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5517 | (match_operand:DI 2 "general_operand" "d,m")) |
5518 | (const_int 0))) | |
5519 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5520 | (ior:DI (match_dup 1) (match_dup 2)))] | |
5521 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5522 | "@ | |
d40c829f UW |
5523 | ogr\t%0,%2 |
5524 | og\t%0,%2" | |
d3632d41 | 5525 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5526 | |
5527 | (define_insn "*iordi3_cconly" | |
5528 | [(set (reg 33) | |
96fd3851 | 5529 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5530 | (match_operand:DI 2 "general_operand" "d,m")) |
5531 | (const_int 0))) | |
5532 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5533 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5534 | "@ | |
d40c829f UW |
5535 | ogr\t%0,%2 |
5536 | og\t%0,%2" | |
d3632d41 | 5537 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 5538 | |
8cb66696 | 5539 | (define_insn "*iordi3" |
0dfa6c5e | 5540 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q") |
bad82153 | 5541 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0") |
8cb66696 | 5542 | (match_operand:DI 2 "general_operand" |
0dfa6c5e | 5543 | "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q"))) |
9db1d521 | 5544 | (clobber (reg:CC 33))] |
8cb66696 | 5545 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5546 | "@ |
f19a9af7 AK |
5547 | oihh\t%0,%i2 |
5548 | oihl\t%0,%i2 | |
5549 | oilh\t%0,%i2 | |
5550 | oill\t%0,%i2 | |
d40c829f | 5551 | ogr\t%0,%2 |
8cb66696 | 5552 | og\t%0,%2 |
0dfa6c5e | 5553 | # |
19b63d8e | 5554 | #" |
0dfa6c5e UW |
5555 | [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")]) |
5556 | ||
5557 | (define_split | |
5558 | [(set (match_operand:DI 0 "s_operand" "") | |
5559 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
5560 | (clobber (reg:CC 33))] | |
5561 | "reload_completed" | |
5562 | [(parallel | |
5563 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
5564 | (clobber (reg:CC 33))])] | |
5565 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") | |
4023fb28 | 5566 | |
8cb66696 UW |
5567 | (define_expand "iordi3" |
5568 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
5569 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
5570 | (match_operand:DI 2 "general_operand" ""))) | |
4023fb28 | 5571 | (clobber (reg:CC 33))] |
8cb66696 UW |
5572 | "TARGET_64BIT" |
5573 | "s390_expand_logical_operator (IOR, DImode, operands); DONE;") | |
9db1d521 HP |
5574 | |
5575 | ; | |
5576 | ; iorsi3 instruction pattern(s). | |
5577 | ; | |
5578 | ||
4023fb28 UW |
5579 | (define_insn "*iorsi3_cc" |
5580 | [(set (reg 33) | |
d3632d41 UW |
5581 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5582 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5583 | (const_int 0))) |
d3632d41 | 5584 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
4023fb28 UW |
5585 | (ior:SI (match_dup 1) (match_dup 2)))] |
5586 | "s390_match_ccmode(insn, CCTmode)" | |
5587 | "@ | |
d40c829f UW |
5588 | or\t%0,%2 |
5589 | o\t%0,%2 | |
5590 | oy\t%0,%2" | |
d3632d41 | 5591 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5592 | |
5593 | (define_insn "*iorsi3_cconly" | |
5594 | [(set (reg 33) | |
d3632d41 UW |
5595 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5596 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5597 | (const_int 0))) |
d3632d41 | 5598 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
4023fb28 UW |
5599 | "s390_match_ccmode(insn, CCTmode)" |
5600 | "@ | |
d40c829f UW |
5601 | or\t%0,%2 |
5602 | o\t%0,%2 | |
5603 | oy\t%0,%2" | |
d3632d41 | 5604 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 | 5605 | |
8cb66696 | 5606 | (define_insn "*iorsi3_zarch" |
0dfa6c5e | 5607 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q") |
bad82153 | 5608 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0") |
0dfa6c5e | 5609 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q"))) |
4023fb28 | 5610 | (clobber (reg:CC 33))] |
8cb66696 | 5611 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5612 | "@ |
f19a9af7 AK |
5613 | oilh\t%0,%i2 |
5614 | oill\t%0,%i2 | |
d40c829f UW |
5615 | or\t%0,%2 |
5616 | o\t%0,%2 | |
8cb66696 | 5617 | oy\t%0,%2 |
0dfa6c5e | 5618 | # |
19b63d8e | 5619 | #" |
0dfa6c5e | 5620 | [(set_attr "op_type" "RI,RI,RR,RX,RXY,SI,SS")]) |
8cb66696 UW |
5621 | |
5622 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 5623 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 5624 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 5625 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
f19a9af7 | 5626 | (clobber (reg:CC 33))] |
8cb66696 | 5627 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
5628 | "@ |
5629 | or\t%0,%2 | |
8cb66696 | 5630 | o\t%0,%2 |
0dfa6c5e | 5631 | # |
19b63d8e | 5632 | #" |
0dfa6c5e UW |
5633 | [(set_attr "op_type" "RR,RX,SI,SS")]) |
5634 | ||
5635 | (define_split | |
5636 | [(set (match_operand:SI 0 "s_operand" "") | |
5637 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
5638 | (clobber (reg:CC 33))] | |
5639 | "reload_completed" | |
5640 | [(parallel | |
5641 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
5642 | (clobber (reg:CC 33))])] | |
5643 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") | |
4023fb28 | 5644 | |
8cb66696 UW |
5645 | (define_expand "iorsi3" |
5646 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
5647 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
5648 | (match_operand:SI 2 "general_operand" ""))) | |
4023fb28 UW |
5649 | (clobber (reg:CC 33))] |
5650 | "" | |
8cb66696 | 5651 | "s390_expand_logical_operator (IOR, SImode, operands); DONE;") |
4023fb28 UW |
5652 | |
5653 | ; | |
5654 | ; iorhi3 instruction pattern(s). | |
5655 | ; | |
5656 | ||
8cb66696 | 5657 | (define_insn "*iorhi3_zarch" |
0dfa6c5e UW |
5658 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5659 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
5660 | (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q"))) | |
4023fb28 | 5661 | (clobber (reg:CC 33))] |
8cb66696 | 5662 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5663 | "@ |
d40c829f | 5664 | or\t%0,%2 |
8cb66696 | 5665 | oill\t%0,%x2 |
0dfa6c5e | 5666 | # |
19b63d8e | 5667 | #" |
0dfa6c5e | 5668 | [(set_attr "op_type" "RR,RI,SI,SS")]) |
8cb66696 UW |
5669 | |
5670 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
5671 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
5672 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
5673 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
4023fb28 | 5674 | (clobber (reg:CC 33))] |
8cb66696 UW |
5675 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
5676 | "@ | |
5677 | or\t%0,%2 | |
0dfa6c5e | 5678 | # |
19b63d8e | 5679 | #" |
0dfa6c5e UW |
5680 | [(set_attr "op_type" "RR,SI,SS")]) |
5681 | ||
5682 | (define_split | |
5683 | [(set (match_operand:HI 0 "s_operand" "") | |
5684 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
5685 | (clobber (reg:CC 33))] | |
5686 | "reload_completed" | |
5687 | [(parallel | |
5688 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
5689 | (clobber (reg:CC 33))])] | |
5690 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") | |
9db1d521 | 5691 | |
8cb66696 UW |
5692 | (define_expand "iorhi3" |
5693 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
5694 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
5695 | (match_operand:HI 2 "general_operand" ""))) | |
9db1d521 HP |
5696 | (clobber (reg:CC 33))] |
5697 | "" | |
8cb66696 | 5698 | "s390_expand_logical_operator (IOR, HImode, operands); DONE;") |
9db1d521 HP |
5699 | |
5700 | ; | |
4023fb28 | 5701 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
5702 | ; |
5703 | ||
8cb66696 UW |
5704 | (define_insn "*iorqi3_zarch" |
5705 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
5706 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5707 | (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
4023fb28 | 5708 | (clobber (reg:CC 33))] |
8cb66696 | 5709 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5710 | "@ |
d40c829f | 5711 | or\t%0,%2 |
8cb66696 | 5712 | oill\t%0,%b2 |
fc0ea003 UW |
5713 | oi\t%S0,%b2 |
5714 | oiy\t%S0,%b2 | |
19b63d8e | 5715 | #" |
8cb66696 UW |
5716 | [(set_attr "op_type" "RR,RI,SI,SIY,SS")]) |
5717 | ||
5718 | (define_insn "*iorqi3_esa" | |
5719 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
5720 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
5721 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
4023fb28 | 5722 | (clobber (reg:CC 33))] |
8cb66696 | 5723 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5724 | "@ |
8cb66696 | 5725 | or\t%0,%2 |
fc0ea003 | 5726 | oi\t%S0,%b2 |
19b63d8e | 5727 | #" |
8cb66696 | 5728 | [(set_attr "op_type" "RR,SI,SS")]) |
9db1d521 | 5729 | |
8cb66696 UW |
5730 | (define_expand "iorqi3" |
5731 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
5732 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
5733 | (match_operand:QI 2 "general_operand" ""))) | |
9db1d521 HP |
5734 | (clobber (reg:CC 33))] |
5735 | "" | |
8cb66696 | 5736 | "s390_expand_logical_operator (IOR, QImode, operands); DONE;") |
9db1d521 | 5737 | |
19b63d8e UW |
5738 | ; |
5739 | ; Block inclusive or (OC) patterns. | |
5740 | ; | |
5741 | ||
5742 | (define_insn "*oc" | |
5743 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5744 | (ior:BLK (match_dup 0) | |
5745 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5746 | (use (match_operand 2 "const_int_operand" "n")) | |
5747 | (clobber (reg:CC 33))] | |
5748 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 5749 | "oc\t%O0(%2,%R0),%S1" |
b628bd8e | 5750 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5751 | |
5752 | (define_split | |
5753 | [(set (match_operand 0 "memory_operand" "") | |
5754 | (ior (match_dup 0) | |
5755 | (match_operand 1 "memory_operand" ""))) | |
5756 | (clobber (reg:CC 33))] | |
5757 | "reload_completed | |
5758 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5759 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
5760 | [(parallel | |
5761 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
5762 | (use (match_dup 2)) | |
5763 | (clobber (reg:CC 33))])] | |
5764 | { | |
5765 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
5766 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
5767 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
5768 | }) | |
5769 | ||
5770 | (define_peephole2 | |
5771 | [(parallel | |
5772 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5773 | (ior:BLK (match_dup 0) | |
5774 | (match_operand:BLK 1 "memory_operand" ""))) | |
5775 | (use (match_operand 2 "const_int_operand" "")) | |
5776 | (clobber (reg:CC 33))]) | |
5777 | (parallel | |
5778 | [(set (match_operand:BLK 3 "memory_operand" "") | |
5779 | (ior:BLK (match_dup 3) | |
5780 | (match_operand:BLK 4 "memory_operand" ""))) | |
5781 | (use (match_operand 5 "const_int_operand" "")) | |
5782 | (clobber (reg:CC 33))])] | |
5783 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
5784 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
5785 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" | |
5786 | [(parallel | |
5787 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
5788 | (use (match_dup 8)) | |
5789 | (clobber (reg:CC 33))])] | |
5790 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
5791 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
5792 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
5793 | ||
9db1d521 HP |
5794 | |
5795 | ;; | |
5796 | ;;- Xor instructions. | |
5797 | ;; | |
5798 | ||
5799 | ; | |
5800 | ; xordi3 instruction pattern(s). | |
5801 | ; | |
5802 | ||
4023fb28 UW |
5803 | (define_insn "*xordi3_cc" |
5804 | [(set (reg 33) | |
96fd3851 | 5805 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5806 | (match_operand:DI 2 "general_operand" "d,m")) |
5807 | (const_int 0))) | |
5808 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5809 | (xor:DI (match_dup 1) (match_dup 2)))] | |
5810 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5811 | "@ | |
d40c829f UW |
5812 | xgr\t%0,%2 |
5813 | xg\t%0,%2" | |
d3632d41 | 5814 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5815 | |
5816 | (define_insn "*xordi3_cconly" | |
5817 | [(set (reg 33) | |
96fd3851 | 5818 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5819 | (match_operand:DI 2 "general_operand" "d,m")) |
5820 | (const_int 0))) | |
5821 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5822 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5823 | "@ | |
d40c829f UW |
5824 | xgr\t%0,%2 |
5825 | xr\t%0,%2" | |
d3632d41 | 5826 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 5827 | |
8cb66696 | 5828 | (define_insn "*xordi3" |
0dfa6c5e UW |
5829 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5830 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
5831 | (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q"))) | |
9db1d521 | 5832 | (clobber (reg:CC 33))] |
8cb66696 | 5833 | "TARGET_64BIT && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5834 | "@ |
d40c829f | 5835 | xgr\t%0,%2 |
8cb66696 | 5836 | xg\t%0,%2 |
0dfa6c5e | 5837 | # |
19b63d8e | 5838 | #" |
0dfa6c5e UW |
5839 | [(set_attr "op_type" "RRE,RXY,SI,SS")]) |
5840 | ||
5841 | (define_split | |
5842 | [(set (match_operand:DI 0 "s_operand" "") | |
5843 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
5844 | (clobber (reg:CC 33))] | |
5845 | "reload_completed" | |
5846 | [(parallel | |
5847 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
5848 | (clobber (reg:CC 33))])] | |
5849 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") | |
4023fb28 | 5850 | |
8cb66696 UW |
5851 | (define_expand "xordi3" |
5852 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
5853 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
5854 | (match_operand:DI 2 "general_operand" ""))) | |
4023fb28 | 5855 | (clobber (reg:CC 33))] |
8cb66696 UW |
5856 | "TARGET_64BIT" |
5857 | "s390_expand_logical_operator (XOR, DImode, operands); DONE;") | |
9db1d521 HP |
5858 | |
5859 | ; | |
5860 | ; xorsi3 instruction pattern(s). | |
5861 | ; | |
5862 | ||
4023fb28 UW |
5863 | (define_insn "*xorsi3_cc" |
5864 | [(set (reg 33) | |
d3632d41 UW |
5865 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5866 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5867 | (const_int 0))) |
d3632d41 | 5868 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
4023fb28 UW |
5869 | (xor:SI (match_dup 1) (match_dup 2)))] |
5870 | "s390_match_ccmode(insn, CCTmode)" | |
5871 | "@ | |
d40c829f UW |
5872 | xr\t%0,%2 |
5873 | x\t%0,%2 | |
5874 | xy\t%0,%2" | |
d3632d41 | 5875 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5876 | |
5877 | (define_insn "*xorsi3_cconly" | |
5878 | [(set (reg 33) | |
d3632d41 UW |
5879 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5880 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5881 | (const_int 0))) |
d3632d41 | 5882 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
4023fb28 UW |
5883 | "s390_match_ccmode(insn, CCTmode)" |
5884 | "@ | |
d40c829f UW |
5885 | xr\t%0,%2 |
5886 | x\t%0,%2 | |
5887 | xy\t%0,%2" | |
d3632d41 | 5888 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 5889 | |
8cb66696 | 5890 | (define_insn "*xorsi3" |
0dfa6c5e UW |
5891 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q") |
5892 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5893 | (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q"))) | |
9db1d521 | 5894 | (clobber (reg:CC 33))] |
8cb66696 | 5895 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 5896 | "@ |
d40c829f UW |
5897 | xr\t%0,%2 |
5898 | x\t%0,%2 | |
8cb66696 | 5899 | xy\t%0,%2 |
0dfa6c5e | 5900 | # |
19b63d8e | 5901 | #" |
0dfa6c5e UW |
5902 | [(set_attr "op_type" "RR,RX,RXY,SI,SS")]) |
5903 | ||
5904 | (define_split | |
5905 | [(set (match_operand:SI 0 "s_operand" "") | |
5906 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
5907 | (clobber (reg:CC 33))] | |
5908 | "reload_completed" | |
5909 | [(parallel | |
5910 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
5911 | (clobber (reg:CC 33))])] | |
5912 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") | |
8cb66696 UW |
5913 | |
5914 | (define_expand "xorsi3" | |
5915 | [(set (match_operand:SI 0 "nonimmediate_operand" "") | |
5916 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
5917 | (match_operand:SI 2 "general_operand" ""))) | |
4023fb28 UW |
5918 | (clobber (reg:CC 33))] |
5919 | "" | |
8cb66696 | 5920 | "s390_expand_logical_operator (XOR, SImode, operands); DONE;") |
9db1d521 HP |
5921 | |
5922 | ; | |
5923 | ; xorhi3 instruction pattern(s). | |
5924 | ; | |
5925 | ||
8cb66696 | 5926 | (define_insn "*xorhi3" |
0dfa6c5e UW |
5927 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
5928 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
5929 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
4023fb28 | 5930 | (clobber (reg:CC 33))] |
8cb66696 UW |
5931 | "s390_logical_operator_ok_p (operands)" |
5932 | "@ | |
5933 | xr\t%0,%2 | |
0dfa6c5e | 5934 | # |
19b63d8e | 5935 | #" |
0dfa6c5e UW |
5936 | [(set_attr "op_type" "RR,SI,SS")]) |
5937 | ||
5938 | (define_split | |
5939 | [(set (match_operand:HI 0 "s_operand" "") | |
5940 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
5941 | (clobber (reg:CC 33))] | |
5942 | "reload_completed" | |
5943 | [(parallel | |
5944 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
5945 | (clobber (reg:CC 33))])] | |
5946 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") | |
9db1d521 | 5947 | |
8cb66696 UW |
5948 | (define_expand "xorhi3" |
5949 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
5950 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "") | |
5951 | (match_operand:HI 2 "general_operand" ""))) | |
9db1d521 HP |
5952 | (clobber (reg:CC 33))] |
5953 | "" | |
8cb66696 | 5954 | "s390_expand_logical_operator (XOR, HImode, operands); DONE;") |
9db1d521 HP |
5955 | |
5956 | ; | |
5957 | ; xorqi3 instruction pattern(s). | |
5958 | ; | |
5959 | ||
8cb66696 UW |
5960 | (define_insn "*xorqi3" |
5961 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q") | |
5962 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0") | |
5963 | (match_operand:QI 2 "general_operand" "d,n,n,Q"))) | |
4023fb28 | 5964 | (clobber (reg:CC 33))] |
8cb66696 | 5965 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 5966 | "@ |
8cb66696 | 5967 | xr\t%0,%2 |
fc0ea003 UW |
5968 | xi\t%S0,%b2 |
5969 | xiy\t%S0,%b2 | |
19b63d8e | 5970 | #" |
8cb66696 | 5971 | [(set_attr "op_type" "RR,SI,SIY,SS")]) |
4023fb28 | 5972 | |
8cb66696 UW |
5973 | (define_expand "xorqi3" |
5974 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
5975 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "") | |
5976 | (match_operand:QI 2 "general_operand" ""))) | |
4023fb28 UW |
5977 | (clobber (reg:CC 33))] |
5978 | "" | |
8cb66696 | 5979 | "s390_expand_logical_operator (XOR, QImode, operands); DONE;") |
9db1d521 | 5980 | |
19b63d8e UW |
5981 | ; |
5982 | ; Block exclusive or (XC) patterns. | |
5983 | ; | |
5984 | ||
5985 | (define_insn "*xc" | |
5986 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5987 | (xor:BLK (match_dup 0) | |
5988 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5989 | (use (match_operand 2 "const_int_operand" "n")) | |
5990 | (clobber (reg:CC 33))] | |
5991 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 5992 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 5993 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5994 | |
5995 | (define_split | |
5996 | [(set (match_operand 0 "memory_operand" "") | |
5997 | (xor (match_dup 0) | |
5998 | (match_operand 1 "memory_operand" ""))) | |
5999 | (clobber (reg:CC 33))] | |
6000 | "reload_completed | |
6001 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
6002 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
6003 | [(parallel | |
6004 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
6005 | (use (match_dup 2)) | |
6006 | (clobber (reg:CC 33))])] | |
6007 | { | |
6008 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
6009 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
6010 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
6011 | }) | |
6012 | ||
6013 | (define_peephole2 | |
6014 | [(parallel | |
6015 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6016 | (xor:BLK (match_dup 0) | |
6017 | (match_operand:BLK 1 "memory_operand" ""))) | |
6018 | (use (match_operand 2 "const_int_operand" "")) | |
6019 | (clobber (reg:CC 33))]) | |
6020 | (parallel | |
6021 | [(set (match_operand:BLK 3 "memory_operand" "") | |
6022 | (xor:BLK (match_dup 3) | |
6023 | (match_operand:BLK 4 "memory_operand" ""))) | |
6024 | (use (match_operand 5 "const_int_operand" "")) | |
6025 | (clobber (reg:CC 33))])] | |
6026 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
6027 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
6028 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" | |
6029 | [(parallel | |
6030 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
6031 | (use (match_dup 8)) | |
6032 | (clobber (reg:CC 33))])] | |
6033 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
6034 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
6035 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
6036 | ||
6037 | ; | |
6038 | ; Block xor (XC) patterns with src == dest. | |
6039 | ; | |
6040 | ||
6041 | (define_insn "*xc_zero" | |
6042 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
6043 | (const_int 0)) | |
6044 | (use (match_operand 1 "const_int_operand" "n")) | |
6045 | (clobber (reg:CC 33))] | |
6046 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" | |
fc0ea003 | 6047 | "xc\t%O0(%1,%R0),%S0" |
b628bd8e | 6048 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
6049 | |
6050 | (define_peephole2 | |
6051 | [(parallel | |
6052 | [(set (match_operand:BLK 0 "memory_operand" "") | |
6053 | (const_int 0)) | |
6054 | (use (match_operand 1 "const_int_operand" "")) | |
6055 | (clobber (reg:CC 33))]) | |
6056 | (parallel | |
6057 | [(set (match_operand:BLK 2 "memory_operand" "") | |
6058 | (const_int 0)) | |
6059 | (use (match_operand 3 "const_int_operand" "")) | |
6060 | (clobber (reg:CC 33))])] | |
6061 | "s390_offset_p (operands[0], operands[2], operands[1]) | |
6062 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
6063 | [(parallel | |
6064 | [(set (match_dup 4) (const_int 0)) | |
6065 | (use (match_dup 5)) | |
6066 | (clobber (reg:CC 33))])] | |
6067 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
6068 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
6069 | ||
9db1d521 HP |
6070 | |
6071 | ;; | |
6072 | ;;- Negate instructions. | |
6073 | ;; | |
6074 | ||
6075 | ; | |
6076 | ; negdi2 instruction pattern(s). | |
6077 | ; | |
6078 | ||
6079 | (define_expand "negdi2" | |
6080 | [(parallel | |
6081 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6082 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
6083 | (clobber (reg:CC 33))])] | |
6084 | "" | |
6085 | "") | |
6086 | ||
26a89301 UW |
6087 | (define_insn "*negdi2_sign_cc" |
6088 | [(set (reg 33) | |
6089 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI | |
6090 | (match_operand:SI 1 "register_operand" "d") 0) | |
6091 | (const_int 32)) (const_int 32))) | |
6092 | (const_int 0))) | |
6093 | (set (match_operand:DI 0 "register_operand" "=d") | |
6094 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
6095 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6096 | "lcgfr\t%0,%1" | |
6097 | [(set_attr "op_type" "RRE")]) | |
6098 | ||
6099 | (define_insn "*negdi2_sign" | |
6100 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6101 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
6102 | (clobber (reg:CC 33))] | |
6103 | "TARGET_64BIT" | |
6104 | "lcgfr\t%0,%1" | |
6105 | [(set_attr "op_type" "RRE")]) | |
6106 | ||
6107 | (define_insn "*negdi2_cc" | |
6108 | [(set (reg 33) | |
6109 | (compare (neg:DI (match_operand:DI 1 "register_operand" "d")) | |
6110 | (const_int 0))) | |
6111 | (set (match_operand:DI 0 "register_operand" "=d") | |
6112 | (neg:DI (match_dup 1)))] | |
6113 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6114 | "lcgr\t%0,%1" | |
6115 | [(set_attr "op_type" "RRE")]) | |
6116 | ||
6117 | (define_insn "*negdi2_cconly" | |
6118 | [(set (reg 33) | |
6119 | (compare (neg:DI (match_operand:DI 1 "register_operand" "d")) | |
6120 | (const_int 0))) | |
6121 | (clobber (match_scratch:DI 0 "=d"))] | |
6122 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6123 | "lcgr\t%0,%1" | |
6124 | [(set_attr "op_type" "RRE")]) | |
6125 | ||
9db1d521 HP |
6126 | (define_insn "*negdi2_64" |
6127 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6128 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
6129 | (clobber (reg:CC 33))] | |
6130 | "TARGET_64BIT" | |
d40c829f | 6131 | "lcgr\t%0,%1" |
26a89301 | 6132 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 6133 | |
26a89301 | 6134 | (define_insn_and_split "*negdi2_31" |
9db1d521 HP |
6135 | [(set (match_operand:DI 0 "register_operand" "=d") |
6136 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
6137 | (clobber (reg:CC 33))] | |
6138 | "!TARGET_64BIT" | |
26a89301 UW |
6139 | "#" |
6140 | "&& reload_completed" | |
6141 | [(parallel | |
6142 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
6143 | (clobber (reg:CC 33))]) | |
6144 | (parallel | |
6145 | [(set (reg:CCAP 33) | |
6146 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) | |
6147 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
6148 | (set (pc) | |
6149 | (if_then_else (ne (reg:CCAP 33) (const_int 0)) | |
6150 | (pc) | |
6151 | (label_ref (match_dup 6)))) | |
6152 | (parallel | |
6153 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
6154 | (clobber (reg:CC 33))]) | |
6155 | (match_dup 6)] | |
6156 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
6157 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
6158 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
6159 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
6160 | operands[6] = gen_label_rtx ();") | |
9db1d521 HP |
6161 | |
6162 | ; | |
6163 | ; negsi2 instruction pattern(s). | |
6164 | ; | |
6165 | ||
26a89301 UW |
6166 | (define_insn "*negsi2_cc" |
6167 | [(set (reg 33) | |
6168 | (compare (neg:SI (match_operand:SI 1 "register_operand" "d")) | |
6169 | (const_int 0))) | |
6170 | (set (match_operand:SI 0 "register_operand" "=d") | |
6171 | (neg:SI (match_dup 1)))] | |
6172 | "s390_match_ccmode (insn, CCAmode)" | |
6173 | "lcr\t%0,%1" | |
6174 | [(set_attr "op_type" "RR")]) | |
6175 | ||
6176 | (define_insn "*negsi2_cconly" | |
6177 | [(set (reg 33) | |
6178 | (compare (neg:SI (match_operand:SI 1 "register_operand" "d")) | |
6179 | (const_int 0))) | |
6180 | (clobber (match_scratch:SI 0 "=d"))] | |
6181 | "s390_match_ccmode (insn, CCAmode)" | |
6182 | "lcr\t%0,%1" | |
6183 | [(set_attr "op_type" "RR")]) | |
6184 | ||
9db1d521 HP |
6185 | (define_insn "negsi2" |
6186 | [(set (match_operand:SI 0 "register_operand" "=d") | |
6187 | (neg:SI (match_operand:SI 1 "register_operand" "d"))) | |
6188 | (clobber (reg:CC 33))] | |
6189 | "" | |
d40c829f | 6190 | "lcr\t%0,%1" |
f2d3c02a | 6191 | [(set_attr "op_type" "RR")]) |
9db1d521 HP |
6192 | |
6193 | ; | |
6194 | ; negdf2 instruction pattern(s). | |
6195 | ; | |
6196 | ||
6197 | (define_expand "negdf2" | |
6198 | [(parallel | |
6199 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6200 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
6201 | (clobber (reg:CC 33))])] | |
6202 | "TARGET_HARD_FLOAT" | |
6203 | "") | |
6204 | ||
26a89301 UW |
6205 | (define_insn "*negdf2_cc" |
6206 | [(set (reg 33) | |
6207 | (compare (neg:DF (match_operand:DF 1 "register_operand" "f")) | |
6208 | (match_operand:DF 2 "const0_operand" ""))) | |
6209 | (set (match_operand:DF 0 "register_operand" "=f") | |
6210 | (neg:DF (match_dup 1)))] | |
6211 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6212 | "lcdbr\t%0,%1" | |
6213 | [(set_attr "op_type" "RRE") | |
6214 | (set_attr "type" "fsimpd")]) | |
6215 | ||
6216 | (define_insn "*negdf2_cconly" | |
6217 | [(set (reg 33) | |
6218 | (compare (neg:DF (match_operand:DF 1 "register_operand" "f")) | |
6219 | (match_operand:DF 2 "const0_operand" ""))) | |
6220 | (clobber (match_scratch:DF 0 "=f"))] | |
6221 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6222 | "lcdbr\t%0,%1" | |
6223 | [(set_attr "op_type" "RRE") | |
6224 | (set_attr "type" "fsimpd")]) | |
6225 | ||
9db1d521 HP |
6226 | (define_insn "*negdf2" |
6227 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6228 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
6229 | (clobber (reg:CC 33))] | |
6230 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 6231 | "lcdbr\t%0,%1" |
077dab3b HP |
6232 | [(set_attr "op_type" "RRE") |
6233 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
6234 | |
6235 | (define_insn "*negdf2_ibm" | |
6236 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6237 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
6238 | (clobber (reg:CC 33))] | |
6239 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 6240 | "lcdr\t%0,%1" |
077dab3b HP |
6241 | [(set_attr "op_type" "RR") |
6242 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
6243 | |
6244 | ; | |
6245 | ; negsf2 instruction pattern(s). | |
6246 | ; | |
6247 | ||
6248 | (define_expand "negsf2" | |
6249 | [(parallel | |
6250 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6251 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
6252 | (clobber (reg:CC 33))])] | |
6253 | "TARGET_HARD_FLOAT" | |
6254 | "") | |
6255 | ||
26a89301 UW |
6256 | (define_insn "*negsf2_cc" |
6257 | [(set (reg 33) | |
6258 | (compare (neg:SF (match_operand:SF 1 "register_operand" "f")) | |
6259 | (match_operand:SF 2 "const0_operand" ""))) | |
6260 | (set (match_operand:SF 0 "register_operand" "=f") | |
6261 | (neg:SF (match_dup 1)))] | |
6262 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6263 | "lcebr\t%0,%1" | |
6264 | [(set_attr "op_type" "RRE") | |
6265 | (set_attr "type" "fsimps")]) | |
6266 | ||
6267 | (define_insn "*negsf2_cconly" | |
6268 | [(set (reg 33) | |
6269 | (compare (neg:SF (match_operand:SF 1 "register_operand" "f")) | |
6270 | (match_operand:SF 2 "const0_operand" ""))) | |
6271 | (clobber (match_scratch:SF 0 "=f"))] | |
6272 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6273 | "lcebr\t%0,%1" | |
6274 | [(set_attr "op_type" "RRE") | |
6275 | (set_attr "type" "fsimps")]) | |
6276 | ||
9db1d521 HP |
6277 | (define_insn "*negsf2" |
6278 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6279 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
6280 | (clobber (reg:CC 33))] | |
6281 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 6282 | "lcebr\t%0,%1" |
077dab3b HP |
6283 | [(set_attr "op_type" "RRE") |
6284 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
6285 | |
6286 | (define_insn "*negsf2" | |
6287 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6288 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
6289 | (clobber (reg:CC 33))] | |
6290 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 6291 | "lcer\t%0,%1" |
077dab3b HP |
6292 | [(set_attr "op_type" "RR") |
6293 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
6294 | |
6295 | ||
6296 | ;; | |
6297 | ;;- Absolute value instructions. | |
6298 | ;; | |
6299 | ||
6300 | ; | |
6301 | ; absdi2 instruction pattern(s). | |
6302 | ; | |
6303 | ||
26a89301 UW |
6304 | (define_insn "*absdi2_sign_cc" |
6305 | [(set (reg 33) | |
6306 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI | |
6307 | (match_operand:SI 1 "register_operand" "d") 0) | |
6308 | (const_int 32)) (const_int 32))) | |
6309 | (const_int 0))) | |
6310 | (set (match_operand:DI 0 "register_operand" "=d") | |
6311 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
6312 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6313 | "lpgfr\t%0,%1" | |
6314 | [(set_attr "op_type" "RRE")]) | |
6315 | ||
6316 | (define_insn "*absdi2_sign" | |
6317 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6318 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
6319 | (clobber (reg:CC 33))] | |
6320 | "TARGET_64BIT" | |
6321 | "lpgfr\t%0,%1" | |
6322 | [(set_attr "op_type" "RRE")]) | |
6323 | ||
6324 | (define_insn "*absdi2_cc" | |
6325 | [(set (reg 33) | |
6326 | (compare (abs:DI (match_operand:DI 1 "register_operand" "d")) | |
6327 | (const_int 0))) | |
6328 | (set (match_operand:DI 0 "register_operand" "=d") | |
6329 | (abs:DI (match_dup 1)))] | |
6330 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6331 | "lpgr\t%0,%1" | |
6332 | [(set_attr "op_type" "RRE")]) | |
6333 | ||
6334 | (define_insn "*absdi2_cconly" | |
6335 | [(set (reg 33) | |
6336 | (compare (abs:DI (match_operand:DI 1 "register_operand" "d")) | |
6337 | (const_int 0))) | |
6338 | (clobber (match_scratch:DI 0 "=d"))] | |
6339 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6340 | "lpgr\t%0,%1" | |
6341 | [(set_attr "op_type" "RRE")]) | |
6342 | ||
9db1d521 HP |
6343 | (define_insn "absdi2" |
6344 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6345 | (abs:DI (match_operand:DI 1 "register_operand" "d"))) | |
6346 | (clobber (reg:CC 33))] | |
6347 | "TARGET_64BIT" | |
d40c829f | 6348 | "lpgr\t%0,%1" |
f2d3c02a | 6349 | [(set_attr "op_type" "RRE")]) |
9db1d521 HP |
6350 | |
6351 | ; | |
6352 | ; abssi2 instruction pattern(s). | |
6353 | ; | |
6354 | ||
26a89301 UW |
6355 | (define_insn "*abssi2_cc" |
6356 | [(set (reg 33) | |
6357 | (compare (abs:SI (match_operand:SI 1 "register_operand" "d")) | |
6358 | (const_int 0))) | |
6359 | (set (match_operand:SI 0 "register_operand" "=d") | |
6360 | (abs:SI (match_dup 1)))] | |
6361 | "s390_match_ccmode (insn, CCAmode)" | |
6362 | "lpr\t%0,%1" | |
6363 | [(set_attr "op_type" "RR")]) | |
6364 | ||
6365 | (define_insn "*abssi2_cconly" | |
6366 | [(set (reg 33) | |
6367 | (compare (abs:SI (match_operand:SI 1 "register_operand" "d")) | |
6368 | (const_int 0))) | |
6369 | (clobber (match_scratch:SI 0 "=d"))] | |
6370 | "s390_match_ccmode (insn, CCAmode)" | |
6371 | "lpr\t%0,%1" | |
6372 | [(set_attr "op_type" "RR")]) | |
6373 | ||
9db1d521 HP |
6374 | (define_insn "abssi2" |
6375 | [(set (match_operand:SI 0 "register_operand" "=d") | |
6376 | (abs:SI (match_operand:SI 1 "register_operand" "d"))) | |
6377 | (clobber (reg:CC 33))] | |
6378 | "" | |
d40c829f | 6379 | "lpr\t%0,%1" |
f2d3c02a | 6380 | [(set_attr "op_type" "RR")]) |
9db1d521 | 6381 | |
9db1d521 HP |
6382 | ; |
6383 | ; absdf2 instruction pattern(s). | |
6384 | ; | |
6385 | ||
6386 | (define_expand "absdf2" | |
6387 | [(parallel | |
6388 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6389 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
6390 | (clobber (reg:CC 33))])] | |
6391 | "TARGET_HARD_FLOAT" | |
6392 | "") | |
6393 | ||
26a89301 UW |
6394 | (define_insn "*absdf2_cc" |
6395 | [(set (reg 33) | |
6396 | (compare (abs:DF (match_operand:DF 1 "register_operand" "f")) | |
6397 | (match_operand:DF 2 "const0_operand" ""))) | |
6398 | (set (match_operand:DF 0 "register_operand" "=f") | |
6399 | (abs:DF (match_dup 1)))] | |
6400 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6401 | "lpdbr\t%0,%1" | |
6402 | [(set_attr "op_type" "RRE") | |
6403 | (set_attr "type" "fsimpd")]) | |
6404 | ||
6405 | (define_insn "*absdf2_cconly" | |
6406 | [(set (reg 33) | |
6407 | (compare (abs:DF (match_operand:DF 1 "register_operand" "f")) | |
6408 | (match_operand:DF 2 "const0_operand" ""))) | |
6409 | (clobber (match_scratch:DF 0 "=f"))] | |
6410 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6411 | "lpdbr\t%0,%1" | |
6412 | [(set_attr "op_type" "RRE") | |
6413 | (set_attr "type" "fsimpd")]) | |
6414 | ||
9db1d521 HP |
6415 | (define_insn "*absdf2" |
6416 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6417 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
6418 | (clobber (reg:CC 33))] | |
6419 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 6420 | "lpdbr\t%0,%1" |
077dab3b HP |
6421 | [(set_attr "op_type" "RRE") |
6422 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
6423 | |
6424 | (define_insn "*absdf2_ibm" | |
6425 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6426 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
6427 | (clobber (reg:CC 33))] | |
6428 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 6429 | "lpdr\t%0,%1" |
077dab3b HP |
6430 | [(set_attr "op_type" "RR") |
6431 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
6432 | |
6433 | ; | |
6434 | ; abssf2 instruction pattern(s). | |
6435 | ; | |
6436 | ||
6437 | (define_expand "abssf2" | |
6438 | [(parallel | |
6439 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6440 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
6441 | (clobber (reg:CC 33))])] | |
6442 | "TARGET_HARD_FLOAT" | |
6443 | "") | |
6444 | ||
26a89301 UW |
6445 | (define_insn "*abssf2_cc" |
6446 | [(set (reg 33) | |
6447 | (compare (abs:SF (match_operand:SF 1 "register_operand" "f")) | |
6448 | (match_operand:SF 2 "const0_operand" ""))) | |
6449 | (set (match_operand:SF 0 "register_operand" "=f") | |
6450 | (abs:SF (match_dup 1)))] | |
6451 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6452 | "lpebr\t%0,%1" | |
6453 | [(set_attr "op_type" "RRE") | |
6454 | (set_attr "type" "fsimps")]) | |
6455 | ||
6456 | (define_insn "*abssf2_cconly" | |
6457 | [(set (reg 33) | |
6458 | (compare (abs:SF (match_operand:SF 1 "register_operand" "f")) | |
6459 | (match_operand:SF 2 "const0_operand" ""))) | |
6460 | (clobber (match_scratch:SF 0 "=f"))] | |
6461 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6462 | "lpebr\t%0,%1" | |
6463 | [(set_attr "op_type" "RRE") | |
6464 | (set_attr "type" "fsimps")]) | |
6465 | ||
9db1d521 HP |
6466 | (define_insn "*abssf2" |
6467 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6468 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
6469 | (clobber (reg:CC 33))] | |
6470 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 6471 | "lpebr\t%0,%1" |
077dab3b HP |
6472 | [(set_attr "op_type" "RRE") |
6473 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
6474 | |
6475 | (define_insn "*abssf2_ibm" | |
6476 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6477 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
6478 | (clobber (reg:CC 33))] | |
6479 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 6480 | "lper\t%0,%1" |
077dab3b HP |
6481 | [(set_attr "op_type" "RR") |
6482 | (set_attr "type" "fsimps")]) | |
9db1d521 | 6483 | |
3ef093a8 AK |
6484 | ;; |
6485 | ;;- Negated absolute value instructions | |
6486 | ;; | |
6487 | ||
6488 | ; | |
6489 | ; Integer | |
6490 | ; | |
6491 | ||
26a89301 UW |
6492 | (define_insn "*negabsdi2_sign_cc" |
6493 | [(set (reg 33) | |
6494 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI | |
6495 | (match_operand:SI 1 "register_operand" "d") 0) | |
6496 | (const_int 32)) (const_int 32)))) | |
6497 | (const_int 0))) | |
6498 | (set (match_operand:DI 0 "register_operand" "=d") | |
6499 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
6500 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6501 | "lngfr\t%0,%1" | |
6502 | [(set_attr "op_type" "RRE")]) | |
6503 | ||
6504 | (define_insn "*negabsdi2_sign" | |
6505 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6506 | (neg:DI (abs:DI (sign_extend:DI | |
6507 | (match_operand:SI 1 "register_operand" "d"))))) | |
3ef093a8 | 6508 | (clobber (reg:CC 33))] |
26a89301 UW |
6509 | "TARGET_64BIT" |
6510 | "lngfr\t%0,%1" | |
6511 | [(set_attr "op_type" "RRE")]) | |
3ef093a8 | 6512 | |
26a89301 UW |
6513 | (define_insn "*negabsdi2_cc" |
6514 | [(set (reg 33) | |
6515 | (compare (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d"))) | |
6516 | (const_int 0))) | |
6517 | (set (match_operand:DI 0 "register_operand" "=d") | |
6518 | (neg:DI (abs:DI (match_dup 1))))] | |
6519 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6520 | "lngr\t%0,%1" | |
6521 | [(set_attr "op_type" "RRE")]) | |
6522 | ||
6523 | (define_insn "*negabsdi2_cconly" | |
6524 | [(set (reg 33) | |
6525 | (compare (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d"))) | |
6526 | (const_int 0))) | |
6527 | (clobber (match_scratch:DI 0 "=d"))] | |
6528 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6529 | "lngr\t%0,%1" | |
6530 | [(set_attr "op_type" "RRE")]) | |
6531 | ||
3ef093a8 AK |
6532 | (define_insn "*negabsdi2" |
6533 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6534 | (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))) | |
6535 | (clobber (reg:CC 33))] | |
6536 | "TARGET_64BIT" | |
d40c829f | 6537 | "lngr\t%0,%1" |
3ef093a8 AK |
6538 | [(set_attr "op_type" "RRE")]) |
6539 | ||
26a89301 UW |
6540 | (define_insn "*negabssi2_cc" |
6541 | [(set (reg 33) | |
6542 | (compare (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d"))) | |
6543 | (const_int 0))) | |
6544 | (set (match_operand:SI 0 "register_operand" "=d") | |
6545 | (neg:SI (abs:SI (match_dup 1))))] | |
6546 | "s390_match_ccmode (insn, CCAmode)" | |
6547 | "lnr\t%0,%1" | |
6548 | [(set_attr "op_type" "RR")]) | |
6549 | ||
6550 | (define_insn "*negabssi2_cconly" | |
6551 | [(set (reg 33) | |
6552 | (compare (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d"))) | |
6553 | (const_int 0))) | |
6554 | (clobber (match_scratch:SI 0 "=d"))] | |
6555 | "s390_match_ccmode (insn, CCAmode)" | |
6556 | "lnr\t%0,%1" | |
6557 | [(set_attr "op_type" "RR")]) | |
6558 | ||
6559 | (define_insn "*negabssi2" | |
6560 | [(set (match_operand:SI 0 "register_operand" "=d") | |
6561 | (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))) | |
6562 | (clobber (reg:CC 33))] | |
6563 | "" | |
6564 | "lnr\t%0,%1" | |
6565 | [(set_attr "op_type" "RR")]) | |
6566 | ||
3ef093a8 AK |
6567 | ; |
6568 | ; Floating point | |
6569 | ; | |
6570 | ||
26a89301 UW |
6571 | (define_insn "*negabsdf2_cc" |
6572 | [(set (reg 33) | |
6573 | (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
6574 | (match_operand:DF 2 "const0_operand" ""))) | |
6575 | (set (match_operand:DF 0 "register_operand" "=f") | |
6576 | (neg:DF (abs:DF (match_dup 1))))] | |
6577 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6578 | "lndbr\t%0,%1" | |
3ef093a8 | 6579 | [(set_attr "op_type" "RRE") |
26a89301 UW |
6580 | (set_attr "type" "fsimpd")]) |
6581 | ||
6582 | (define_insn "*negabsdf2_cconly" | |
6583 | [(set (reg 33) | |
6584 | (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
6585 | (match_operand:DF 2 "const0_operand" ""))) | |
6586 | (clobber (match_scratch:DF 0 "=f"))] | |
6587 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6588 | "lndbr\t%0,%1" | |
6589 | [(set_attr "op_type" "RRE") | |
6590 | (set_attr "type" "fsimpd")]) | |
6591 | ||
3ef093a8 AK |
6592 | (define_insn "*negabsdf2" |
6593 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6594 | (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))) | |
6595 | (clobber (reg:CC 33))] | |
6596 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 6597 | "lndbr\t%0,%1" |
3ef093a8 AK |
6598 | [(set_attr "op_type" "RRE") |
6599 | (set_attr "type" "fsimpd")]) | |
6600 | ||
26a89301 UW |
6601 | (define_insn "*negabssf2_cc" |
6602 | [(set (reg 33) | |
6603 | (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
6604 | (match_operand:SF 2 "const0_operand" ""))) | |
6605 | (set (match_operand:SF 0 "register_operand" "=f") | |
6606 | (neg:SF (abs:SF (match_dup 1))))] | |
6607 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6608 | "lnebr\t%0,%1" | |
6609 | [(set_attr "op_type" "RRE") | |
6610 | (set_attr "type" "fsimps")]) | |
6611 | ||
6612 | (define_insn "*negabssf2_cconly" | |
6613 | [(set (reg 33) | |
6614 | (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
6615 | (match_operand:SF 2 "const0_operand" ""))) | |
6616 | (clobber (match_scratch:SF 0 "=f"))] | |
6617 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6618 | "lnebr\t%0,%1" | |
6619 | [(set_attr "op_type" "RRE") | |
6620 | (set_attr "type" "fsimps")]) | |
6621 | ||
6622 | (define_insn "*negabssf2" | |
6623 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6624 | (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))) | |
6625 | (clobber (reg:CC 33))] | |
6626 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
6627 | "lnebr\t%0,%1" | |
6628 | [(set_attr "op_type" "RRE") | |
6629 | (set_attr "type" "fsimps")]) | |
6630 | ||
4023fb28 UW |
6631 | ;; |
6632 | ;;- Square root instructions. | |
6633 | ;; | |
6634 | ||
6635 | ; | |
6636 | ; sqrtdf2 instruction pattern(s). | |
6637 | ; | |
6638 | ||
6639 | (define_insn "sqrtdf2" | |
6640 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 6641 | (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))] |
4023fb28 UW |
6642 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
6643 | "@ | |
d40c829f UW |
6644 | sqdbr\t%0,%1 |
6645 | sqdb\t%0,%1" | |
a036c6f7 UW |
6646 | [(set_attr "op_type" "RRE,RXE") |
6647 | (set_attr "type" "fsqrtd")]) | |
4023fb28 UW |
6648 | |
6649 | ; | |
6650 | ; sqrtsf2 instruction pattern(s). | |
6651 | ; | |
6652 | ||
6653 | (define_insn "sqrtsf2" | |
6654 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
d3632d41 | 6655 | (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))] |
4023fb28 UW |
6656 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
6657 | "@ | |
d40c829f UW |
6658 | sqebr\t%0,%1 |
6659 | sqeb\t%0,%1" | |
a036c6f7 UW |
6660 | [(set_attr "op_type" "RRE,RXE") |
6661 | (set_attr "type" "fsqrts")]) | |
9db1d521 HP |
6662 | |
6663 | ;; | |
6664 | ;;- One complement instructions. | |
6665 | ;; | |
6666 | ||
6667 | ; | |
6668 | ; one_cmpldi2 instruction pattern(s). | |
6669 | ; | |
c7453384 | 6670 | |
9db1d521 HP |
6671 | (define_expand "one_cmpldi2" |
6672 | [(parallel | |
4023fb28 UW |
6673 | [(set (match_operand:DI 0 "register_operand" "") |
6674 | (xor:DI (match_operand:DI 1 "register_operand" "") | |
6675 | (const_int -1))) | |
9db1d521 HP |
6676 | (clobber (reg:CC 33))])] |
6677 | "TARGET_64BIT" | |
4023fb28 | 6678 | "") |
c7453384 | 6679 | |
9db1d521 HP |
6680 | ; |
6681 | ; one_cmplsi2 instruction pattern(s). | |
6682 | ; | |
c7453384 | 6683 | |
9db1d521 HP |
6684 | (define_expand "one_cmplsi2" |
6685 | [(parallel | |
4023fb28 UW |
6686 | [(set (match_operand:SI 0 "register_operand" "") |
6687 | (xor:SI (match_operand:SI 1 "register_operand" "") | |
6688 | (const_int -1))) | |
9db1d521 HP |
6689 | (clobber (reg:CC 33))])] |
6690 | "" | |
4023fb28 | 6691 | "") |
c7453384 | 6692 | |
9db1d521 HP |
6693 | ; |
6694 | ; one_cmplhi2 instruction pattern(s). | |
6695 | ; | |
c7453384 | 6696 | |
9db1d521 HP |
6697 | (define_expand "one_cmplhi2" |
6698 | [(parallel | |
4023fb28 UW |
6699 | [(set (match_operand:HI 0 "register_operand" "") |
6700 | (xor:HI (match_operand:HI 1 "register_operand" "") | |
6701 | (const_int -1))) | |
9db1d521 HP |
6702 | (clobber (reg:CC 33))])] |
6703 | "" | |
4023fb28 | 6704 | "") |
c7453384 | 6705 | |
9db1d521 HP |
6706 | ; |
6707 | ; one_cmplqi2 instruction pattern(s). | |
6708 | ; | |
c7453384 | 6709 | |
4023fb28 UW |
6710 | (define_expand "one_cmplqi2" |
6711 | [(parallel | |
6712 | [(set (match_operand:QI 0 "register_operand" "") | |
6713 | (xor:QI (match_operand:QI 1 "register_operand" "") | |
6714 | (const_int -1))) | |
6715 | (clobber (reg:CC 33))])] | |
9db1d521 | 6716 | "" |
4023fb28 | 6717 | "") |
9db1d521 HP |
6718 | |
6719 | ||
6720 | ;; | |
6721 | ;;- Rotate instructions. | |
6722 | ;; | |
6723 | ||
6724 | ; | |
6725 | ; rotldi3 instruction pattern(s). | |
6726 | ; | |
6727 | ||
6728 | (define_insn "rotldi3" | |
ac32b25e UW |
6729 | [(set (match_operand:DI 0 "register_operand" "=d") |
6730 | (rotate:DI (match_operand:DI 1 "register_operand" "d") | |
6731 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6732 | "TARGET_64BIT" |
ac32b25e | 6733 | "rllg\t%0,%1,%Y2" |
077dab3b HP |
6734 | [(set_attr "op_type" "RSE") |
6735 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6736 | |
6737 | ; | |
6738 | ; rotlsi3 instruction pattern(s). | |
6739 | ; | |
6740 | ||
6741 | (define_insn "rotlsi3" | |
ac32b25e UW |
6742 | [(set (match_operand:SI 0 "register_operand" "=d") |
6743 | (rotate:SI (match_operand:SI 1 "register_operand" "d") | |
6744 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9e8327e3 | 6745 | "TARGET_CPU_ZARCH" |
ac32b25e | 6746 | "rll\t%0,%1,%Y2" |
077dab3b HP |
6747 | [(set_attr "op_type" "RSE") |
6748 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6749 | |
6750 | ||
6751 | ;; | |
6752 | ;;- Arithmetic shift instructions. | |
6753 | ;; | |
9db1d521 HP |
6754 | |
6755 | ; | |
6756 | ; ashldi3 instruction pattern(s). | |
6757 | ; | |
6758 | ||
6759 | (define_expand "ashldi3" | |
ecbe845e UW |
6760 | [(set (match_operand:DI 0 "register_operand" "") |
6761 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
ac32b25e | 6762 | (match_operand:SI 2 "shift_count_operand" "")))] |
9db1d521 HP |
6763 | "" |
6764 | "") | |
6765 | ||
6766 | (define_insn "*ashldi3_31" | |
ac32b25e UW |
6767 | [(set (match_operand:DI 0 "register_operand" "=d") |
6768 | (ashift:DI (match_operand:DI 1 "register_operand" "0") | |
6769 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6770 | "!TARGET_64BIT" |
ac32b25e | 6771 | "sldl\t%0,%Y2" |
077dab3b HP |
6772 | [(set_attr "op_type" "RS") |
6773 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6774 | |
6775 | (define_insn "*ashldi3_64" | |
ac32b25e UW |
6776 | [(set (match_operand:DI 0 "register_operand" "=d") |
6777 | (ashift:DI (match_operand:DI 1 "register_operand" "d") | |
6778 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6779 | "TARGET_64BIT" |
ac32b25e | 6780 | "sllg\t%0,%1,%Y2" |
077dab3b HP |
6781 | [(set_attr "op_type" "RSE") |
6782 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6783 | |
6784 | ; | |
6785 | ; ashrdi3 instruction pattern(s). | |
6786 | ; | |
6787 | ||
6788 | (define_expand "ashrdi3" | |
6789 | [(parallel | |
6790 | [(set (match_operand:DI 0 "register_operand" "") | |
6791 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
ac32b25e | 6792 | (match_operand:SI 2 "shift_count_operand" ""))) |
9db1d521 HP |
6793 | (clobber (reg:CC 33))])] |
6794 | "" | |
6795 | "") | |
6796 | ||
ecbe845e UW |
6797 | (define_insn "*ashrdi3_cc_31" |
6798 | [(set (reg 33) | |
ac32b25e UW |
6799 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
6800 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6801 | (const_int 0))) |
ac32b25e | 6802 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e UW |
6803 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6804 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" | |
ac32b25e | 6805 | "srda\t%0,%Y2" |
077dab3b HP |
6806 | [(set_attr "op_type" "RS") |
6807 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
6808 | |
6809 | (define_insn "*ashrdi3_cconly_31" | |
6810 | [(set (reg 33) | |
ac32b25e UW |
6811 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
6812 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6813 | (const_int 0))) |
ac32b25e | 6814 | (clobber (match_scratch:DI 0 "=d"))] |
ecbe845e | 6815 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 6816 | "srda\t%0,%Y2" |
077dab3b HP |
6817 | [(set_attr "op_type" "RS") |
6818 | (set_attr "atype" "reg")]) | |
ecbe845e | 6819 | |
9db1d521 | 6820 | (define_insn "*ashrdi3_31" |
ac32b25e UW |
6821 | [(set (match_operand:DI 0 "register_operand" "=d") |
6822 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
6823 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
9db1d521 HP |
6824 | (clobber (reg:CC 33))] |
6825 | "!TARGET_64BIT" | |
ac32b25e | 6826 | "srda\t%0,%Y2" |
077dab3b HP |
6827 | [(set_attr "op_type" "RS") |
6828 | (set_attr "atype" "reg")]) | |
c7453384 | 6829 | |
ecbe845e UW |
6830 | (define_insn "*ashrdi3_cc_64" |
6831 | [(set (reg 33) | |
ac32b25e UW |
6832 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") |
6833 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6834 | (const_int 0))) |
ac32b25e | 6835 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e UW |
6836 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6837 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
ac32b25e | 6838 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6839 | [(set_attr "op_type" "RSE") |
6840 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
6841 | |
6842 | (define_insn "*ashrdi3_cconly_64" | |
6843 | [(set (reg 33) | |
ac32b25e UW |
6844 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") |
6845 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6846 | (const_int 0))) |
ac32b25e | 6847 | (clobber (match_scratch:DI 0 "=d"))] |
ecbe845e | 6848 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" |
ac32b25e | 6849 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6850 | [(set_attr "op_type" "RSE") |
6851 | (set_attr "atype" "reg")]) | |
ecbe845e | 6852 | |
9db1d521 | 6853 | (define_insn "*ashrdi3_64" |
ac32b25e UW |
6854 | [(set (match_operand:DI 0 "register_operand" "=d") |
6855 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
6856 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
9db1d521 HP |
6857 | (clobber (reg:CC 33))] |
6858 | "TARGET_64BIT" | |
ac32b25e | 6859 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6860 | [(set_attr "op_type" "RSE") |
6861 | (set_attr "atype" "reg")]) | |
6862 | ||
9db1d521 HP |
6863 | |
6864 | ; | |
6865 | ; ashlsi3 instruction pattern(s). | |
6866 | ; | |
9db1d521 HP |
6867 | |
6868 | (define_insn "ashlsi3" | |
ac32b25e UW |
6869 | [(set (match_operand:SI 0 "register_operand" "=d") |
6870 | (ashift:SI (match_operand:SI 1 "register_operand" "0") | |
6871 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6872 | "" |
ac32b25e | 6873 | "sll\t%0,%Y2" |
077dab3b HP |
6874 | [(set_attr "op_type" "RS") |
6875 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6876 | |
6877 | ; | |
6878 | ; ashrsi3 instruction pattern(s). | |
6879 | ; | |
6880 | ||
ecbe845e UW |
6881 | (define_insn "*ashrsi3_cc" |
6882 | [(set (reg 33) | |
ac32b25e UW |
6883 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") |
6884 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6885 | (const_int 0))) |
ac32b25e | 6886 | (set (match_operand:SI 0 "register_operand" "=d") |
ecbe845e UW |
6887 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
6888 | "s390_match_ccmode(insn, CCSmode)" | |
ac32b25e | 6889 | "sra\t%0,%Y2" |
077dab3b HP |
6890 | [(set_attr "op_type" "RS") |
6891 | (set_attr "atype" "reg")]) | |
6892 | ||
ecbe845e UW |
6893 | |
6894 | (define_insn "*ashrsi3_cconly" | |
6895 | [(set (reg 33) | |
ac32b25e UW |
6896 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") |
6897 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6898 | (const_int 0))) |
ac32b25e | 6899 | (clobber (match_scratch:SI 0 "=d"))] |
ecbe845e | 6900 | "s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 6901 | "sra\t%0,%Y2" |
077dab3b HP |
6902 | [(set_attr "op_type" "RS") |
6903 | (set_attr "atype" "reg")]) | |
ecbe845e | 6904 | |
9db1d521 | 6905 | (define_insn "ashrsi3" |
ac32b25e UW |
6906 | [(set (match_operand:SI 0 "register_operand" "=d") |
6907 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
6908 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
9db1d521 HP |
6909 | (clobber (reg:CC 33))] |
6910 | "" | |
ac32b25e | 6911 | "sra\t%0,%Y2" |
077dab3b HP |
6912 | [(set_attr "op_type" "RS") |
6913 | (set_attr "atype" "reg")]) | |
9db1d521 | 6914 | |
9db1d521 HP |
6915 | |
6916 | ;; | |
6917 | ;;- logical shift instructions. | |
6918 | ;; | |
6919 | ||
6920 | ; | |
6921 | ; lshrdi3 instruction pattern(s). | |
6922 | ; | |
6923 | ||
6924 | (define_expand "lshrdi3" | |
ecbe845e UW |
6925 | [(set (match_operand:DI 0 "register_operand" "") |
6926 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
ac32b25e | 6927 | (match_operand:SI 2 "shift_count_operand" "")))] |
9db1d521 HP |
6928 | "" |
6929 | "") | |
6930 | ||
6931 | (define_insn "*lshrdi3_31" | |
ac32b25e UW |
6932 | [(set (match_operand:DI 0 "register_operand" "=d") |
6933 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
6934 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6935 | "!TARGET_64BIT" |
ac32b25e UW |
6936 | "srdl\t%0,%Y2" |
6937 | [(set_attr "op_type" "RS") | |
077dab3b | 6938 | (set_attr "atype" "reg")]) |
9db1d521 HP |
6939 | |
6940 | (define_insn "*lshrdi3_64" | |
ac32b25e UW |
6941 | [(set (match_operand:DI 0 "register_operand" "=d") |
6942 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
6943 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6944 | "TARGET_64BIT" |
ac32b25e UW |
6945 | "srlg\t%0,%1,%Y2" |
6946 | [(set_attr "op_type" "RSE") | |
077dab3b | 6947 | (set_attr "atype" "reg")]) |
9db1d521 HP |
6948 | |
6949 | ; | |
6950 | ; lshrsi3 instruction pattern(s). | |
6951 | ; | |
6952 | ||
6953 | (define_insn "lshrsi3" | |
ac32b25e UW |
6954 | [(set (match_operand:SI 0 "register_operand" "=d") |
6955 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
6956 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6957 | "" |
ac32b25e | 6958 | "srl\t%0,%Y2" |
077dab3b HP |
6959 | [(set_attr "op_type" "RS") |
6960 | (set_attr "atype" "reg")]) | |
9db1d521 | 6961 | |
9db1d521 HP |
6962 | |
6963 | ;; | |
6964 | ;; Branch instruction patterns. | |
6965 | ;; | |
6966 | ||
6967 | (define_expand "beq" | |
6590e19a | 6968 | [(match_operand 0 "" "")] |
9db1d521 | 6969 | "" |
6590e19a UW |
6970 | "s390_emit_jump (operands[0], |
6971 | s390_emit_compare (EQ, s390_compare_op0, s390_compare_op1)); DONE;") | |
9db1d521 HP |
6972 | |
6973 | (define_expand "bne" | |
6590e19a | 6974 | [(match_operand 0 "" "")] |
9db1d521 | 6975 | "" |
6590e19a UW |
6976 | "s390_emit_jump (operands[0], |
6977 | s390_emit_compare (NE, s390_compare_op0, s390_compare_op1)); DONE;") | |
9db1d521 HP |
6978 | |
6979 | (define_expand "bgt" | |
6590e19a | 6980 | [(match_operand 0 "" "")] |
9db1d521 | 6981 | "" |
6590e19a UW |
6982 | "s390_emit_jump (operands[0], |
6983 | s390_emit_compare (GT, s390_compare_op0, s390_compare_op1)); DONE;") | |
9db1d521 HP |
6984 | |
6985 | (define_expand "bgtu" | |
6590e19a | 6986 | [(match_operand 0 "" "")] |
9db1d521 | 6987 | "" |
6590e19a UW |
6988 | "s390_emit_jump (operands[0], |
6989 | s390_emit_compare (GTU, s390_compare_op0, s390_compare_op1)); DONE;") | |
9db1d521 HP |
6990 | |
6991 | (define_expand "blt" | |
6590e19a | 6992 | [(match_operand 0 "" "")] |
9db1d521 | 6993 | "" |
6590e19a UW |
6994 | "s390_emit_jump (operands[0], |
6995 | s390_emit_compare (LT, s390_compare_op0, s390_compare_op1)); DONE;") | |
9db1d521 HP |
6996 | |
6997 | (define_expand "bltu" | |
6590e19a | 6998 | [(match_operand 0 "" "")] |
9db1d521 | 6999 | "" |
6590e19a UW |
7000 | "s390_emit_jump (operands[0], |
7001 | s390_emit_compare (LTU, s390_compare_op0, s390_compare_op1)); DONE;") | |
9db1d521 HP |
7002 | |
7003 | (define_expand "bge" | |
6590e19a | 7004 | [(match_operand 0 "" "")] |
9db1d521 | 7005 | "" |
6590e19a UW |
7006 | "s390_emit_jump (operands[0], |
7007 | s390_emit_compare (GE, s390_compare_op0, s390_compare_op1)); DONE;") | |
9db1d521 HP |
7008 | |
7009 | (define_expand "bgeu" | |
6590e19a | 7010 | [(match_operand 0 "" "")] |
9db1d521 | 7011 | "" |
6590e19a UW |
7012 | "s390_emit_jump (operands[0], |
7013 | s390_emit_compare (GEU, s390_compare_op0, s390_compare_op1)); DONE;") | |
9db1d521 HP |
7014 | |
7015 | (define_expand "ble" | |
6590e19a | 7016 | [(match_operand 0 "" "")] |
9db1d521 | 7017 | "" |
6590e19a UW |
7018 | "s390_emit_jump (operands[0], |
7019 | s390_emit_compare (LE, s390_compare_op0, s390_compare_op1)); DONE;") | |
9db1d521 HP |
7020 | |
7021 | (define_expand "bleu" | |
6590e19a | 7022 | [(match_operand 0 "" "")] |
9db1d521 | 7023 | "" |
6590e19a UW |
7024 | "s390_emit_jump (operands[0], |
7025 | s390_emit_compare (LEU, s390_compare_op0, s390_compare_op1)); DONE;") | |
9db1d521 | 7026 | |
ba956982 | 7027 | (define_expand "bunordered" |
6590e19a | 7028 | [(match_operand 0 "" "")] |
ba956982 | 7029 | "" |
6590e19a UW |
7030 | "s390_emit_jump (operands[0], |
7031 | s390_emit_compare (UNORDERED, s390_compare_op0, s390_compare_op1)); DONE;") | |
ba956982 UW |
7032 | |
7033 | (define_expand "bordered" | |
6590e19a | 7034 | [(match_operand 0 "" "")] |
ba956982 | 7035 | "" |
6590e19a UW |
7036 | "s390_emit_jump (operands[0], |
7037 | s390_emit_compare (ORDERED, s390_compare_op0, s390_compare_op1)); DONE;") | |
ba956982 UW |
7038 | |
7039 | (define_expand "buneq" | |
6590e19a | 7040 | [(match_operand 0 "" "")] |
ba956982 | 7041 | "" |
6590e19a UW |
7042 | "s390_emit_jump (operands[0], |
7043 | s390_emit_compare (UNEQ, s390_compare_op0, s390_compare_op1)); DONE;") | |
ba956982 UW |
7044 | |
7045 | (define_expand "bunlt" | |
6590e19a | 7046 | [(match_operand 0 "" "")] |
ba956982 | 7047 | "" |
6590e19a UW |
7048 | "s390_emit_jump (operands[0], |
7049 | s390_emit_compare (UNLT, s390_compare_op0, s390_compare_op1)); DONE;") | |
ba956982 | 7050 | |
6590e19a UW |
7051 | (define_expand "bungt" |
7052 | [(match_operand 0 "" "")] | |
ba956982 | 7053 | "" |
6590e19a UW |
7054 | "s390_emit_jump (operands[0], |
7055 | s390_emit_compare (UNGT, s390_compare_op0, s390_compare_op1)); DONE;") | |
ba956982 UW |
7056 | |
7057 | (define_expand "bunle" | |
6590e19a | 7058 | [(match_operand 0 "" "")] |
ba956982 | 7059 | "" |
6590e19a UW |
7060 | "s390_emit_jump (operands[0], |
7061 | s390_emit_compare (UNLE, s390_compare_op0, s390_compare_op1)); DONE;") | |
7062 | ||
7063 | (define_expand "bunge" | |
7064 | [(match_operand 0 "" "")] | |
7065 | "" | |
7066 | "s390_emit_jump (operands[0], | |
7067 | s390_emit_compare (UNGE, s390_compare_op0, s390_compare_op1)); DONE;") | |
ba956982 UW |
7068 | |
7069 | (define_expand "bltgt" | |
6590e19a | 7070 | [(match_operand 0 "" "")] |
ba956982 | 7071 | "" |
6590e19a UW |
7072 | "s390_emit_jump (operands[0], |
7073 | s390_emit_compare (LTGT, s390_compare_op0, s390_compare_op1)); DONE;") | |
ba956982 | 7074 | |
9db1d521 HP |
7075 | |
7076 | ;; | |
7077 | ;;- Conditional jump instructions. | |
7078 | ;; | |
7079 | ||
6590e19a UW |
7080 | (define_insn "*cjump_64" |
7081 | [(set (pc) | |
7082 | (if_then_else | |
5b022de5 | 7083 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
6590e19a UW |
7084 | (label_ref (match_operand 0 "" "")) |
7085 | (pc)))] | |
7086 | "TARGET_CPU_ZARCH" | |
9db1d521 | 7087 | { |
13e58269 | 7088 | if (get_attr_length (insn) == 4) |
d40c829f | 7089 | return "j%C1\t%l0"; |
6590e19a | 7090 | else |
d40c829f | 7091 | return "jg%C1\t%l0"; |
6590e19a UW |
7092 | } |
7093 | [(set_attr "op_type" "RI") | |
7094 | (set_attr "type" "branch") | |
7095 | (set (attr "length") | |
7096 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7097 | (const_int 4) (const_int 6)))]) | |
7098 | ||
7099 | (define_insn "*cjump_31" | |
7100 | [(set (pc) | |
7101 | (if_then_else | |
5b022de5 | 7102 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
6590e19a UW |
7103 | (label_ref (match_operand 0 "" "")) |
7104 | (pc)))] | |
7105 | "!TARGET_CPU_ZARCH" | |
7106 | { | |
7107 | if (get_attr_length (insn) == 4) | |
7108 | return "j%C1\t%l0"; | |
9db1d521 | 7109 | else |
13e58269 | 7110 | abort (); |
10bbf137 | 7111 | } |
9db1d521 | 7112 | [(set_attr "op_type" "RI") |
077dab3b | 7113 | (set_attr "type" "branch") |
13e58269 | 7114 | (set (attr "length") |
6590e19a UW |
7115 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
7116 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7117 | (const_int 4) (const_int 6)) | |
7118 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7119 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 7120 | |
f314b9b1 | 7121 | (define_insn "*cjump_long" |
6590e19a UW |
7122 | [(set (pc) |
7123 | (if_then_else | |
5b022de5 | 7124 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
6590e19a UW |
7125 | (match_operand 0 "address_operand" "U") |
7126 | (pc)))] | |
9db1d521 | 7127 | "" |
f314b9b1 UW |
7128 | { |
7129 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7130 | return "b%C1r\t%0"; |
f314b9b1 | 7131 | else |
d40c829f | 7132 | return "b%C1\t%a0"; |
10bbf137 | 7133 | } |
c7453384 | 7134 | [(set (attr "op_type") |
f314b9b1 UW |
7135 | (if_then_else (match_operand 0 "register_operand" "") |
7136 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 7137 | (set_attr "type" "branch") |
077dab3b | 7138 | (set_attr "atype" "agen")]) |
9db1d521 HP |
7139 | |
7140 | ||
7141 | ;; | |
7142 | ;;- Negated conditional jump instructions. | |
7143 | ;; | |
7144 | ||
6590e19a UW |
7145 | (define_insn "*icjump_64" |
7146 | [(set (pc) | |
7147 | (if_then_else | |
5b022de5 | 7148 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
6590e19a UW |
7149 | (pc) |
7150 | (label_ref (match_operand 0 "" ""))))] | |
7151 | "TARGET_CPU_ZARCH" | |
c7453384 | 7152 | { |
13e58269 | 7153 | if (get_attr_length (insn) == 4) |
d40c829f | 7154 | return "j%D1\t%l0"; |
6590e19a | 7155 | else |
d40c829f | 7156 | return "jg%D1\t%l0"; |
6590e19a UW |
7157 | } |
7158 | [(set_attr "op_type" "RI") | |
7159 | (set_attr "type" "branch") | |
7160 | (set (attr "length") | |
7161 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7162 | (const_int 4) (const_int 6)))]) | |
7163 | ||
7164 | (define_insn "*icjump_31" | |
7165 | [(set (pc) | |
7166 | (if_then_else | |
5b022de5 | 7167 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
6590e19a UW |
7168 | (pc) |
7169 | (label_ref (match_operand 0 "" ""))))] | |
7170 | "!TARGET_CPU_ZARCH" | |
7171 | { | |
7172 | if (get_attr_length (insn) == 4) | |
7173 | return "j%D1\t%l0"; | |
9db1d521 | 7174 | else |
13e58269 | 7175 | abort (); |
10bbf137 | 7176 | } |
9db1d521 | 7177 | [(set_attr "op_type" "RI") |
077dab3b | 7178 | (set_attr "type" "branch") |
13e58269 | 7179 | (set (attr "length") |
6590e19a UW |
7180 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
7181 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7182 | (const_int 4) (const_int 6)) | |
7183 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7184 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 7185 | |
f314b9b1 | 7186 | (define_insn "*icjump_long" |
6590e19a UW |
7187 | [(set (pc) |
7188 | (if_then_else | |
5b022de5 | 7189 | (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)]) |
6590e19a UW |
7190 | (pc) |
7191 | (match_operand 0 "address_operand" "U")))] | |
9db1d521 | 7192 | "" |
f314b9b1 UW |
7193 | { |
7194 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7195 | return "b%D1r\t%0"; |
f314b9b1 | 7196 | else |
d40c829f | 7197 | return "b%D1\t%a0"; |
10bbf137 | 7198 | } |
c7453384 | 7199 | [(set (attr "op_type") |
f314b9b1 UW |
7200 | (if_then_else (match_operand 0 "register_operand" "") |
7201 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
7202 | (set_attr "type" "branch") |
7203 | (set_attr "atype" "agen")]) | |
9db1d521 | 7204 | |
4456530d HP |
7205 | ;; |
7206 | ;;- Trap instructions. | |
7207 | ;; | |
7208 | ||
7209 | (define_insn "trap" | |
7210 | [(trap_if (const_int 1) (const_int 0))] | |
7211 | "" | |
d40c829f | 7212 | "j\t.+2" |
6590e19a | 7213 | [(set_attr "op_type" "RI") |
077dab3b | 7214 | (set_attr "type" "branch")]) |
4456530d HP |
7215 | |
7216 | (define_expand "conditional_trap" | |
6590e19a UW |
7217 | [(trap_if (match_operand 0 "comparison_operator" "") |
7218 | (match_operand 1 "general_operand" ""))] | |
4456530d | 7219 | "" |
4456530d | 7220 | { |
6590e19a UW |
7221 | if (operands[1] != const0_rtx) FAIL; |
7222 | operands[0] = s390_emit_compare (GET_CODE (operands[0]), | |
7223 | s390_compare_op0, s390_compare_op1); | |
10bbf137 | 7224 | }) |
4456530d HP |
7225 | |
7226 | (define_insn "*trap" | |
5b022de5 | 7227 | [(trap_if (match_operator 0 "s390_comparison" [(reg 33) (const_int 0)]) |
4456530d HP |
7228 | (const_int 0))] |
7229 | "" | |
d40c829f | 7230 | "j%C0\t.+2"; |
077dab3b HP |
7231 | [(set_attr "op_type" "RI") |
7232 | (set_attr "type" "branch")]) | |
9db1d521 HP |
7233 | |
7234 | ;; | |
0a3bdf9d | 7235 | ;;- Loop instructions. |
9db1d521 | 7236 | ;; |
0a3bdf9d UW |
7237 | ;; This is all complicated by the fact that since this is a jump insn |
7238 | ;; we must handle our own output reloads. | |
c7453384 | 7239 | |
0a3bdf9d UW |
7240 | (define_expand "doloop_end" |
7241 | [(use (match_operand 0 "" "")) ; loop pseudo | |
7242 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
7243 | (use (match_operand 2 "" "")) ; max iterations | |
7244 | (use (match_operand 3 "" "")) ; loop level | |
7245 | (use (match_operand 4 "" ""))] ; label | |
7246 | "" | |
0a3bdf9d | 7247 | { |
6590e19a UW |
7248 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
7249 | emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0])); | |
7250 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) | |
7251 | emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0])); | |
0a3bdf9d UW |
7252 | else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) |
7253 | emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); | |
7254 | else | |
7255 | FAIL; | |
7256 | ||
7257 | DONE; | |
10bbf137 | 7258 | }) |
0a3bdf9d | 7259 | |
6590e19a | 7260 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
7261 | [(set (pc) |
7262 | (if_then_else | |
7263 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
7264 | (const_int 1)) | |
7265 | (label_ref (match_operand 0 "" "")) | |
7266 | (pc))) | |
bd446804 | 7267 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") |
0a3bdf9d | 7268 | (plus:SI (match_dup 1) (const_int -1))) |
eb862a88 | 7269 | (clobber (match_scratch:SI 3 "=X,&1")) |
0a3bdf9d | 7270 | (clobber (reg:CC 33))] |
6590e19a | 7271 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
7272 | { |
7273 | if (which_alternative != 0) | |
10bbf137 | 7274 | return "#"; |
0a3bdf9d | 7275 | else if (get_attr_length (insn) == 4) |
d40c829f | 7276 | return "brct\t%1,%l0"; |
6590e19a | 7277 | else |
545d16ff | 7278 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
7279 | } |
7280 | "&& reload_completed | |
7281 | && (! REG_P (operands[2]) | |
7282 | || ! rtx_equal_p (operands[1], operands[2]))" | |
eb862a88 | 7283 | [(parallel [(set (reg:CCAN 33) |
6590e19a UW |
7284 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
7285 | (const_int 0))) | |
7286 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
7287 | (set (match_dup 2) (match_dup 3)) | |
7288 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
7289 | (label_ref (match_dup 0)) | |
7290 | (pc)))] | |
7291 | "" | |
7292 | [(set_attr "op_type" "RI") | |
7293 | (set_attr "type" "branch") | |
7294 | (set (attr "length") | |
7295 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7296 | (const_int 4) (const_int 10)))]) | |
7297 | ||
7298 | (define_insn_and_split "doloop_si31" | |
7299 | [(set (pc) | |
7300 | (if_then_else | |
7301 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
7302 | (const_int 1)) | |
7303 | (label_ref (match_operand 0 "" "")) | |
7304 | (pc))) | |
7305 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") | |
7306 | (plus:SI (match_dup 1) (const_int -1))) | |
eb862a88 | 7307 | (clobber (match_scratch:SI 3 "=X,&1")) |
6590e19a UW |
7308 | (clobber (reg:CC 33))] |
7309 | "!TARGET_CPU_ZARCH" | |
7310 | { | |
7311 | if (which_alternative != 0) | |
7312 | return "#"; | |
7313 | else if (get_attr_length (insn) == 4) | |
7314 | return "brct\t%1,%l0"; | |
0a3bdf9d UW |
7315 | else |
7316 | abort (); | |
10bbf137 | 7317 | } |
6590e19a UW |
7318 | "&& reload_completed |
7319 | && (! REG_P (operands[2]) | |
7320 | || ! rtx_equal_p (operands[1], operands[2]))" | |
eb862a88 | 7321 | [(parallel [(set (reg:CCAN 33) |
6590e19a UW |
7322 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
7323 | (const_int 0))) | |
7324 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
7325 | (set (match_dup 2) (match_dup 3)) | |
7326 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
7327 | (label_ref (match_dup 0)) | |
7328 | (pc)))] | |
7329 | "" | |
0a3bdf9d | 7330 | [(set_attr "op_type" "RI") |
077dab3b | 7331 | (set_attr "type" "branch") |
0a3bdf9d | 7332 | (set (attr "length") |
6590e19a UW |
7333 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
7334 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7335 | (const_int 4) (const_int 6)) | |
7336 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7337 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 7338 | |
0a3bdf9d UW |
7339 | (define_insn "*doloop_si_long" |
7340 | [(set (pc) | |
7341 | (if_then_else | |
7342 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
7343 | (const_int 1)) | |
d3632d41 | 7344 | (match_operand 0 "address_operand" "U,U") |
0a3bdf9d UW |
7345 | (pc))) |
7346 | (set (match_operand:SI 2 "register_operand" "=1,?*m*d") | |
7347 | (plus:SI (match_dup 1) (const_int -1))) | |
eb862a88 | 7348 | (clobber (match_scratch:SI 3 "=X,&1")) |
0a3bdf9d | 7349 | (clobber (reg:CC 33))] |
6590e19a | 7350 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
7351 | { |
7352 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7353 | return "bctr\t%1,%0"; |
0a3bdf9d | 7354 | else |
d40c829f | 7355 | return "bct\t%1,%a0"; |
10bbf137 | 7356 | } |
c7453384 | 7357 | [(set (attr "op_type") |
0a3bdf9d UW |
7358 | (if_then_else (match_operand 0 "register_operand" "") |
7359 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
7360 | (set_attr "type" "branch") |
7361 | (set_attr "atype" "agen")]) | |
0a3bdf9d | 7362 | |
6590e19a | 7363 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
7364 | [(set (pc) |
7365 | (if_then_else | |
7366 | (ne (match_operand:DI 1 "register_operand" "d,d") | |
7367 | (const_int 1)) | |
7368 | (label_ref (match_operand 0 "" "")) | |
7369 | (pc))) | |
eb862a88 | 7370 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d") |
0a3bdf9d | 7371 | (plus:DI (match_dup 1) (const_int -1))) |
eb862a88 | 7372 | (clobber (match_scratch:DI 3 "=X,&1")) |
0a3bdf9d UW |
7373 | (clobber (reg:CC 33))] |
7374 | "TARGET_64BIT" | |
0a3bdf9d UW |
7375 | { |
7376 | if (which_alternative != 0) | |
10bbf137 | 7377 | return "#"; |
0a3bdf9d | 7378 | else if (get_attr_length (insn) == 4) |
d40c829f | 7379 | return "brctg\t%1,%l0"; |
0a3bdf9d | 7380 | else |
545d16ff | 7381 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 7382 | } |
6590e19a | 7383 | "&& reload_completed |
0a3bdf9d UW |
7384 | && (! REG_P (operands[2]) |
7385 | || ! rtx_equal_p (operands[1], operands[2]))" | |
eb862a88 | 7386 | [(parallel [(set (reg:CCAN 33) |
0a3bdf9d UW |
7387 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
7388 | (const_int 0))) | |
7389 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
7390 | (set (match_dup 2) (match_dup 3)) | |
7391 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
6590e19a | 7392 | (label_ref (match_dup 0)) |
0a3bdf9d | 7393 | (pc)))] |
6590e19a UW |
7394 | "" |
7395 | [(set_attr "op_type" "RI") | |
7396 | (set_attr "type" "branch") | |
7397 | (set (attr "length") | |
7398 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7399 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
7400 | |
7401 | ;; | |
7402 | ;;- Unconditional jump instructions. | |
7403 | ;; | |
7404 | ||
7405 | ; | |
7406 | ; jump instruction pattern(s). | |
7407 | ; | |
7408 | ||
6590e19a UW |
7409 | (define_expand "jump" |
7410 | [(match_operand 0 "" "")] | |
9db1d521 | 7411 | "" |
6590e19a UW |
7412 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
7413 | ||
7414 | (define_insn "*jump64" | |
7415 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
7416 | "TARGET_CPU_ZARCH" | |
9db1d521 | 7417 | { |
13e58269 | 7418 | if (get_attr_length (insn) == 4) |
d40c829f | 7419 | return "j\t%l0"; |
6590e19a | 7420 | else |
d40c829f | 7421 | return "jg\t%l0"; |
6590e19a UW |
7422 | } |
7423 | [(set_attr "op_type" "RI") | |
7424 | (set_attr "type" "branch") | |
7425 | (set (attr "length") | |
7426 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7427 | (const_int 4) (const_int 6)))]) | |
7428 | ||
7429 | (define_insn "*jump31" | |
7430 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
7431 | "!TARGET_CPU_ZARCH" | |
7432 | { | |
7433 | if (get_attr_length (insn) == 4) | |
7434 | return "j\t%l0"; | |
9db1d521 | 7435 | else |
13e58269 | 7436 | abort (); |
10bbf137 | 7437 | } |
9db1d521 | 7438 | [(set_attr "op_type" "RI") |
077dab3b | 7439 | (set_attr "type" "branch") |
13e58269 | 7440 | (set (attr "length") |
6590e19a UW |
7441 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
7442 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7443 | (const_int 4) (const_int 6)) | |
7444 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
7445 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
7446 | |
7447 | ; | |
7448 | ; indirect-jump instruction pattern(s). | |
7449 | ; | |
7450 | ||
7451 | (define_insn "indirect_jump" | |
d3632d41 | 7452 | [(set (pc) (match_operand 0 "address_operand" "U"))] |
9db1d521 | 7453 | "" |
f314b9b1 UW |
7454 | { |
7455 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 7456 | return "br\t%0"; |
f314b9b1 | 7457 | else |
d40c829f | 7458 | return "b\t%a0"; |
10bbf137 | 7459 | } |
c7453384 | 7460 | [(set (attr "op_type") |
f314b9b1 UW |
7461 | (if_then_else (match_operand 0 "register_operand" "") |
7462 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
7463 | (set_attr "type" "branch") |
7464 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
7465 | |
7466 | ; | |
f314b9b1 | 7467 | ; casesi instruction pattern(s). |
9db1d521 HP |
7468 | ; |
7469 | ||
f314b9b1 | 7470 | (define_insn "casesi_jump" |
d3632d41 | 7471 | [(set (pc) (match_operand 0 "address_operand" "U")) |
f314b9b1 | 7472 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 7473 | "" |
9db1d521 | 7474 | { |
f314b9b1 | 7475 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 7476 | return "br\t%0"; |
f314b9b1 | 7477 | else |
d40c829f | 7478 | return "b\t%a0"; |
10bbf137 | 7479 | } |
c7453384 | 7480 | [(set (attr "op_type") |
f314b9b1 UW |
7481 | (if_then_else (match_operand 0 "register_operand" "") |
7482 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
7483 | (set_attr "type" "branch") |
7484 | (set_attr "atype" "agen")]) | |
9db1d521 | 7485 | |
f314b9b1 UW |
7486 | (define_expand "casesi" |
7487 | [(match_operand:SI 0 "general_operand" "") | |
7488 | (match_operand:SI 1 "general_operand" "") | |
7489 | (match_operand:SI 2 "general_operand" "") | |
7490 | (label_ref (match_operand 3 "" "")) | |
7491 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 7492 | "" |
f314b9b1 UW |
7493 | { |
7494 | rtx index = gen_reg_rtx (SImode); | |
7495 | rtx base = gen_reg_rtx (Pmode); | |
7496 | rtx target = gen_reg_rtx (Pmode); | |
7497 | ||
7498 | emit_move_insn (index, operands[0]); | |
7499 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
7500 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 7501 | operands[4]); |
f314b9b1 UW |
7502 | |
7503 | if (Pmode != SImode) | |
7504 | index = convert_to_mode (Pmode, index, 1); | |
7505 | if (GET_CODE (index) != REG) | |
7506 | index = copy_to_mode_reg (Pmode, index); | |
7507 | ||
7508 | if (TARGET_64BIT) | |
7509 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
7510 | else | |
a556fd39 | 7511 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 7512 | |
f314b9b1 UW |
7513 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
7514 | ||
542a8afa | 7515 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
7516 | emit_move_insn (target, index); |
7517 | ||
7518 | if (flag_pic) | |
7519 | target = gen_rtx_PLUS (Pmode, base, target); | |
7520 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
7521 | ||
7522 | DONE; | |
10bbf137 | 7523 | }) |
9db1d521 HP |
7524 | |
7525 | ||
7526 | ;; | |
7527 | ;;- Jump to subroutine. | |
7528 | ;; | |
7529 | ;; | |
7530 | ||
7531 | ; | |
7532 | ; untyped call instruction pattern(s). | |
7533 | ; | |
7534 | ||
7535 | ;; Call subroutine returning any type. | |
7536 | (define_expand "untyped_call" | |
7537 | [(parallel [(call (match_operand 0 "" "") | |
7538 | (const_int 0)) | |
7539 | (match_operand 1 "" "") | |
7540 | (match_operand 2 "" "")])] | |
7541 | "" | |
9db1d521 HP |
7542 | { |
7543 | int i; | |
7544 | ||
7545 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
7546 | ||
7547 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
7548 | { | |
7549 | rtx set = XVECEXP (operands[2], 0, i); | |
7550 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
7551 | } | |
7552 | ||
7553 | /* The optimizer does not know that the call sets the function value | |
7554 | registers we stored in the result block. We avoid problems by | |
7555 | claiming that all hard registers are used and clobbered at this | |
7556 | point. */ | |
7557 | emit_insn (gen_blockage ()); | |
7558 | ||
7559 | DONE; | |
10bbf137 | 7560 | }) |
9db1d521 HP |
7561 | |
7562 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
7563 | ;; all of memory. This blocks insns from being moved across this point. | |
7564 | ||
7565 | (define_insn "blockage" | |
10bbf137 | 7566 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 7567 | "" |
4023fb28 | 7568 | "" |
d5869ca0 UW |
7569 | [(set_attr "type" "none") |
7570 | (set_attr "length" "0")]) | |
4023fb28 | 7571 | |
9db1d521 | 7572 | ; |
ed9676cf | 7573 | ; sibcall patterns |
9db1d521 HP |
7574 | ; |
7575 | ||
ed9676cf | 7576 | (define_expand "sibcall" |
44b8152b | 7577 | [(call (match_operand 0 "" "") |
ed9676cf | 7578 | (match_operand 1 "" ""))] |
9db1d521 | 7579 | "" |
9db1d521 | 7580 | { |
ed9676cf AK |
7581 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
7582 | DONE; | |
7583 | }) | |
9db1d521 | 7584 | |
ed9676cf AK |
7585 | (define_insn "*sibcall_br" |
7586 | [(call (mem:QI (reg 1)) | |
7587 | (match_operand 0 "const_int_operand" "n"))] | |
2f7e5a0d | 7588 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
7589 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
7590 | "br\t%%r1" | |
7591 | [(set_attr "op_type" "RR") | |
7592 | (set_attr "type" "branch") | |
7593 | (set_attr "atype" "agen")]) | |
9db1d521 | 7594 | |
ed9676cf AK |
7595 | (define_insn "*sibcall_brc" |
7596 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7597 | (match_operand 1 "const_int_operand" "n"))] | |
7598 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
7599 | "j\t%0" | |
7600 | [(set_attr "op_type" "RI") | |
7601 | (set_attr "type" "branch")]) | |
9db1d521 | 7602 | |
ed9676cf AK |
7603 | (define_insn "*sibcall_brcl" |
7604 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7605 | (match_operand 1 "const_int_operand" "n"))] | |
7606 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
7607 | "jg\t%0" | |
7608 | [(set_attr "op_type" "RIL") | |
7609 | (set_attr "type" "branch")]) | |
44b8152b | 7610 | |
ed9676cf AK |
7611 | ; |
7612 | ; sibcall_value patterns | |
7613 | ; | |
9e8327e3 | 7614 | |
ed9676cf AK |
7615 | (define_expand "sibcall_value" |
7616 | [(set (match_operand 0 "" "") | |
7617 | (call (match_operand 1 "" "") | |
7618 | (match_operand 2 "" "")))] | |
7619 | "" | |
7620 | { | |
7621 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 7622 | DONE; |
10bbf137 | 7623 | }) |
9db1d521 | 7624 | |
ed9676cf AK |
7625 | (define_insn "*sibcall_value_br" |
7626 | [(set (match_operand 0 "" "") | |
7627 | (call (mem:QI (reg 1)) | |
7628 | (match_operand 1 "const_int_operand" "n")))] | |
2f7e5a0d | 7629 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
7630 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
7631 | "br\t%%r1" | |
7632 | [(set_attr "op_type" "RR") | |
7633 | (set_attr "type" "branch") | |
7634 | (set_attr "atype" "agen")]) | |
7635 | ||
7636 | (define_insn "*sibcall_value_brc" | |
7637 | [(set (match_operand 0 "" "") | |
7638 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
7639 | (match_operand 2 "const_int_operand" "n")))] | |
7640 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
7641 | "j\t%1" | |
7642 | [(set_attr "op_type" "RI") | |
7643 | (set_attr "type" "branch")]) | |
7644 | ||
7645 | (define_insn "*sibcall_value_brcl" | |
7646 | [(set (match_operand 0 "" "") | |
7647 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
7648 | (match_operand 2 "const_int_operand" "n")))] | |
7649 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
7650 | "jg\t%1" | |
7651 | [(set_attr "op_type" "RIL") | |
7652 | (set_attr "type" "branch")]) | |
7653 | ||
7654 | ||
7655 | ; | |
7656 | ; call instruction pattern(s). | |
7657 | ; | |
7658 | ||
7659 | (define_expand "call" | |
7660 | [(call (match_operand 0 "" "") | |
7661 | (match_operand 1 "" "")) | |
7662 | (use (match_operand 2 "" ""))] | |
44b8152b | 7663 | "" |
ed9676cf | 7664 | { |
2f7e5a0d | 7665 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
7666 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
7667 | DONE; | |
7668 | }) | |
44b8152b | 7669 | |
9e8327e3 UW |
7670 | (define_insn "*bras" |
7671 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7672 | (match_operand 1 "const_int_operand" "n")) | |
7673 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
7674 | "!SIBLING_CALL_P (insn) |
7675 | && TARGET_SMALL_EXEC | |
ed9676cf | 7676 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 7677 | "bras\t%2,%0" |
9db1d521 | 7678 | [(set_attr "op_type" "RI") |
4023fb28 | 7679 | (set_attr "type" "jsr")]) |
9db1d521 | 7680 | |
9e8327e3 UW |
7681 | (define_insn "*brasl" |
7682 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7683 | (match_operand 1 "const_int_operand" "n")) | |
7684 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
7685 | "!SIBLING_CALL_P (insn) |
7686 | && TARGET_CPU_ZARCH | |
ed9676cf | 7687 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
7688 | "brasl\t%2,%0" |
7689 | [(set_attr "op_type" "RIL") | |
077dab3b | 7690 | (set_attr "type" "jsr")]) |
9db1d521 | 7691 | |
9e8327e3 UW |
7692 | (define_insn "*basr" |
7693 | [(call (mem:QI (match_operand 0 "address_operand" "U")) | |
7694 | (match_operand 1 "const_int_operand" "n")) | |
7695 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 7696 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
7697 | { |
7698 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7699 | return "basr\t%2,%0"; | |
7700 | else | |
7701 | return "bas\t%2,%a0"; | |
7702 | } | |
7703 | [(set (attr "op_type") | |
7704 | (if_then_else (match_operand 0 "register_operand" "") | |
7705 | (const_string "RR") (const_string "RX"))) | |
7706 | (set_attr "type" "jsr") | |
7707 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
7708 | |
7709 | ; | |
7710 | ; call_value instruction pattern(s). | |
7711 | ; | |
7712 | ||
7713 | (define_expand "call_value" | |
44b8152b UW |
7714 | [(set (match_operand 0 "" "") |
7715 | (call (match_operand 1 "" "") | |
7716 | (match_operand 2 "" ""))) | |
7717 | (use (match_operand 3 "" ""))] | |
9db1d521 | 7718 | "" |
9db1d521 | 7719 | { |
2f7e5a0d | 7720 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 7721 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 7722 | DONE; |
10bbf137 | 7723 | }) |
9db1d521 | 7724 | |
9e8327e3 | 7725 | (define_insn "*bras_r" |
c19ec8f9 | 7726 | [(set (match_operand 0 "" "") |
9e8327e3 | 7727 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 7728 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 7729 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
7730 | "!SIBLING_CALL_P (insn) |
7731 | && TARGET_SMALL_EXEC | |
ed9676cf | 7732 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 7733 | "bras\t%3,%1" |
9db1d521 | 7734 | [(set_attr "op_type" "RI") |
f2d3c02a | 7735 | (set_attr "type" "jsr")]) |
9db1d521 | 7736 | |
9e8327e3 | 7737 | (define_insn "*brasl_r" |
c19ec8f9 | 7738 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7739 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7740 | (match_operand 2 "const_int_operand" "n"))) | |
7741 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
7742 | "!SIBLING_CALL_P (insn) |
7743 | && TARGET_CPU_ZARCH | |
ed9676cf | 7744 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7745 | "brasl\t%3,%1" |
7746 | [(set_attr "op_type" "RIL") | |
077dab3b | 7747 | (set_attr "type" "jsr")]) |
9db1d521 | 7748 | |
9e8327e3 | 7749 | (define_insn "*basr_r" |
c19ec8f9 | 7750 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7751 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
7752 | (match_operand 2 "const_int_operand" "n"))) | |
7753 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 7754 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7755 | { |
7756 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7757 | return "basr\t%3,%1"; | |
7758 | else | |
7759 | return "bas\t%3,%a1"; | |
7760 | } | |
7761 | [(set (attr "op_type") | |
7762 | (if_then_else (match_operand 1 "register_operand" "") | |
7763 | (const_string "RR") (const_string "RX"))) | |
7764 | (set_attr "type" "jsr") | |
7765 | (set_attr "atype" "agen")]) | |
9db1d521 | 7766 | |
fd3cd001 UW |
7767 | ;; |
7768 | ;;- Thread-local storage support. | |
7769 | ;; | |
7770 | ||
c5aa1d12 UW |
7771 | (define_expand "get_tp_64" |
7772 | [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI 36))] | |
fd3cd001 | 7773 | "TARGET_64BIT" |
c5aa1d12 | 7774 | "") |
fd3cd001 | 7775 | |
c5aa1d12 UW |
7776 | (define_expand "get_tp_31" |
7777 | [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI 36))] | |
fd3cd001 | 7778 | "!TARGET_64BIT" |
c5aa1d12 | 7779 | "") |
fd3cd001 | 7780 | |
c5aa1d12 UW |
7781 | (define_expand "set_tp_64" |
7782 | [(set (reg:DI 36) (match_operand:DI 0 "nonimmediate_operand" "")) | |
7783 | (unspec_volatile [(reg:DI 36)] UNSPECV_SET_TP)] | |
fd3cd001 | 7784 | "TARGET_64BIT" |
c5aa1d12 | 7785 | "") |
fd3cd001 | 7786 | |
c5aa1d12 UW |
7787 | (define_expand "set_tp_31" |
7788 | [(set (reg:SI 36) (match_operand:SI 0 "nonimmediate_operand" "")) | |
7789 | (unspec_volatile [(reg:SI 36)] UNSPECV_SET_TP)] | |
fd3cd001 | 7790 | "!TARGET_64BIT" |
c5aa1d12 UW |
7791 | "") |
7792 | ||
7793 | (define_insn "*set_tp" | |
7794 | [(unspec_volatile [(reg 36)] UNSPECV_SET_TP)] | |
7795 | "" | |
7796 | "" | |
7797 | [(set_attr "type" "none") | |
7798 | (set_attr "length" "0")]) | |
c7453384 | 7799 | |
fd3cd001 UW |
7800 | (define_insn "*tls_load_64" |
7801 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7802 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
7803 | (match_operand:DI 2 "" "")] | |
7804 | UNSPEC_TLS_LOAD))] | |
7805 | "TARGET_64BIT" | |
d40c829f | 7806 | "lg\t%0,%1%J2" |
fd3cd001 UW |
7807 | [(set_attr "op_type" "RXE")]) |
7808 | ||
7809 | (define_insn "*tls_load_31" | |
d3632d41 UW |
7810 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
7811 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
7812 | (match_operand:SI 2 "" "")] |
7813 | UNSPEC_TLS_LOAD))] | |
7814 | "!TARGET_64BIT" | |
d3632d41 | 7815 | "@ |
d40c829f UW |
7816 | l\t%0,%1%J2 |
7817 | ly\t%0,%1%J2" | |
d3632d41 | 7818 | [(set_attr "op_type" "RX,RXY")]) |
fd3cd001 | 7819 | |
9e8327e3 | 7820 | (define_insn "*bras_tls" |
c19ec8f9 | 7821 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7822 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7823 | (match_operand 2 "const_int_operand" "n"))) | |
7824 | (clobber (match_operand 3 "register_operand" "=r")) | |
7825 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
7826 | "!SIBLING_CALL_P (insn) |
7827 | && TARGET_SMALL_EXEC | |
ed9676cf | 7828 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 7829 | "bras\t%3,%1%J4" |
fd3cd001 UW |
7830 | [(set_attr "op_type" "RI") |
7831 | (set_attr "type" "jsr")]) | |
7832 | ||
9e8327e3 | 7833 | (define_insn "*brasl_tls" |
c19ec8f9 | 7834 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7835 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7836 | (match_operand 2 "const_int_operand" "n"))) | |
7837 | (clobber (match_operand 3 "register_operand" "=r")) | |
7838 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
7839 | "!SIBLING_CALL_P (insn) |
7840 | && TARGET_CPU_ZARCH | |
ed9676cf | 7841 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7842 | "brasl\t%3,%1%J4" |
7843 | [(set_attr "op_type" "RIL") | |
fd3cd001 UW |
7844 | (set_attr "type" "jsr")]) |
7845 | ||
9e8327e3 | 7846 | (define_insn "*basr_tls" |
c19ec8f9 | 7847 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7848 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
7849 | (match_operand 2 "const_int_operand" "n"))) | |
7850 | (clobber (match_operand 3 "register_operand" "=r")) | |
7851 | (use (match_operand 4 "" ""))] | |
ed9676cf | 7852 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7853 | { |
7854 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7855 | return "basr\t%3,%1%J4"; | |
7856 | else | |
7857 | return "bas\t%3,%a1%J4"; | |
7858 | } | |
7859 | [(set (attr "op_type") | |
7860 | (if_then_else (match_operand 1 "register_operand" "") | |
7861 | (const_string "RR") (const_string "RX"))) | |
7862 | (set_attr "type" "jsr") | |
7863 | (set_attr "atype" "agen")]) | |
fd3cd001 | 7864 | |
9db1d521 HP |
7865 | ;; |
7866 | ;;- Miscellaneous instructions. | |
7867 | ;; | |
7868 | ||
7869 | ; | |
7870 | ; allocate stack instruction pattern(s). | |
7871 | ; | |
7872 | ||
7873 | (define_expand "allocate_stack" | |
ef44a6ff UW |
7874 | [(match_operand 0 "general_operand" "") |
7875 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 7876 | "TARGET_BACKCHAIN" |
9db1d521 | 7877 | { |
ef44a6ff | 7878 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 7879 | |
ef44a6ff UW |
7880 | emit_move_insn (temp, s390_back_chain_rtx ()); |
7881 | anti_adjust_stack (operands[1]); | |
7882 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 7883 | |
ef44a6ff UW |
7884 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
7885 | DONE; | |
10bbf137 | 7886 | }) |
9db1d521 HP |
7887 | |
7888 | ||
7889 | ; | |
43ab026f | 7890 | ; setjmp instruction pattern. |
9db1d521 HP |
7891 | ; |
7892 | ||
9db1d521 | 7893 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 7894 | [(match_operand 0 "" "")] |
f314b9b1 | 7895 | "flag_pic" |
9db1d521 | 7896 | { |
585539a1 | 7897 | emit_insn (s390_load_got ()); |
fd7643fb | 7898 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); |
9db1d521 | 7899 | DONE; |
fd7643fb | 7900 | }) |
9db1d521 | 7901 | |
9db1d521 HP |
7902 | ;; These patterns say how to save and restore the stack pointer. We need not |
7903 | ;; save the stack pointer at function level since we are careful to | |
7904 | ;; preserve the backchain. At block level, we have to restore the backchain | |
7905 | ;; when we restore the stack pointer. | |
7906 | ;; | |
7907 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
7908 | ;; backchain and restore both. Note that in the nonlocal case, the | |
7909 | ;; save area is a memory location. | |
7910 | ||
7911 | (define_expand "save_stack_function" | |
7912 | [(match_operand 0 "general_operand" "") | |
7913 | (match_operand 1 "general_operand" "")] | |
7914 | "" | |
7915 | "DONE;") | |
7916 | ||
7917 | (define_expand "restore_stack_function" | |
7918 | [(match_operand 0 "general_operand" "") | |
7919 | (match_operand 1 "general_operand" "")] | |
7920 | "" | |
7921 | "DONE;") | |
7922 | ||
7923 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
7924 | [(match_operand 0 "register_operand" "") |
7925 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 7926 | "TARGET_BACKCHAIN" |
9db1d521 | 7927 | { |
ef44a6ff UW |
7928 | rtx temp = gen_reg_rtx (Pmode); |
7929 | ||
7930 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
7931 | emit_move_insn (operands[0], operands[1]); | |
7932 | emit_move_insn (s390_back_chain_rtx (), temp); | |
7933 | ||
7934 | DONE; | |
10bbf137 | 7935 | }) |
9db1d521 HP |
7936 | |
7937 | (define_expand "save_stack_nonlocal" | |
7938 | [(match_operand 0 "memory_operand" "") | |
7939 | (match_operand 1 "register_operand" "")] | |
7940 | "" | |
9db1d521 | 7941 | { |
ef44a6ff UW |
7942 | enum machine_mode mode = TARGET_64BIT ? OImode : TImode; |
7943 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); | |
7944 | ||
7945 | /* Copy the backchain to the first word, sp to the second and the | |
7946 | literal pool base to the third. */ | |
7947 | ||
b3d31392 | 7948 | if (TARGET_BACKCHAIN) |
ef44a6ff UW |
7949 | { |
7950 | rtx temp = force_reg (Pmode, s390_back_chain_rtx ()); | |
7951 | emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp); | |
7952 | } | |
7953 | ||
7954 | emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]); | |
7955 | emit_move_insn (operand_subword (operands[0], 2, 0, mode), base); | |
9db1d521 | 7956 | |
9db1d521 | 7957 | DONE; |
10bbf137 | 7958 | }) |
9db1d521 HP |
7959 | |
7960 | (define_expand "restore_stack_nonlocal" | |
7961 | [(match_operand 0 "register_operand" "") | |
7962 | (match_operand 1 "memory_operand" "")] | |
7963 | "" | |
9db1d521 | 7964 | { |
ef44a6ff | 7965 | enum machine_mode mode = TARGET_64BIT ? OImode : TImode; |
490ceeb4 | 7966 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 7967 | rtx temp = NULL_RTX; |
9db1d521 | 7968 | |
43ab026f | 7969 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 7970 | literal pool base from the third. */ |
43ab026f | 7971 | |
b3d31392 | 7972 | if (TARGET_BACKCHAIN) |
ef44a6ff UW |
7973 | temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode)); |
7974 | ||
7975 | emit_move_insn (base, operand_subword (operands[1], 2, 0, mode)); | |
7976 | emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode)); | |
7977 | ||
7978 | if (temp) | |
7979 | emit_move_insn (s390_back_chain_rtx (), temp); | |
7980 | ||
7981 | emit_insn (gen_rtx_USE (VOIDmode, base)); | |
9db1d521 | 7982 | DONE; |
10bbf137 | 7983 | }) |
9db1d521 HP |
7984 | |
7985 | ||
7986 | ; | |
7987 | ; nop instruction pattern(s). | |
7988 | ; | |
7989 | ||
7990 | (define_insn "nop" | |
7991 | [(const_int 0)] | |
7992 | "" | |
d40c829f | 7993 | "lr\t0,0" |
9db1d521 HP |
7994 | [(set_attr "op_type" "RR")]) |
7995 | ||
7996 | ||
7997 | ; | |
7998 | ; Special literal pool access instruction pattern(s). | |
7999 | ; | |
8000 | ||
416cf582 UW |
8001 | (define_insn "*pool_entry" |
8002 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
8003 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 8004 | "" |
9db1d521 | 8005 | { |
416cf582 UW |
8006 | enum machine_mode mode = GET_MODE (PATTERN (insn)); |
8007 | unsigned int align = GET_MODE_BITSIZE (mode); | |
faeb9bb6 | 8008 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
8009 | return ""; |
8010 | } | |
b628bd8e | 8011 | [(set (attr "length") |
416cf582 | 8012 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 8013 | |
9bb86f41 UW |
8014 | (define_insn "pool_align" |
8015 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
8016 | UNSPECV_POOL_ALIGN)] | |
8017 | "" | |
8018 | ".align\t%0" | |
b628bd8e | 8019 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 8020 | |
9bb86f41 UW |
8021 | (define_insn "pool_section_start" |
8022 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
8023 | "" | |
8024 | ".section\t.rodata" | |
b628bd8e | 8025 | [(set_attr "length" "0")]) |
b2ccb744 | 8026 | |
9bb86f41 UW |
8027 | (define_insn "pool_section_end" |
8028 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
8029 | "" | |
b2ccb744 | 8030 | ".previous" |
b628bd8e | 8031 | [(set_attr "length" "0")]) |
b2ccb744 | 8032 | |
5af2f3d3 | 8033 | (define_insn "main_base_31_small" |
9e8327e3 UW |
8034 | [(set (match_operand 0 "register_operand" "=a") |
8035 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
8036 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
8037 | "basr\t%0,0" |
8038 | [(set_attr "op_type" "RR") | |
8039 | (set_attr "type" "la")]) | |
8040 | ||
8041 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
8042 | [(set (match_operand 0 "register_operand" "=a") |
8043 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 8044 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 8045 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 UW |
8046 | "bras\t%0,%2" |
8047 | [(set_attr "op_type" "RI")]) | |
8048 | ||
8049 | (define_insn "main_base_64" | |
9e8327e3 UW |
8050 | [(set (match_operand 0 "register_operand" "=a") |
8051 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
8052 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
8053 | "larl\t%0,%1" |
8054 | [(set_attr "op_type" "RIL") | |
8055 | (set_attr "type" "larl")]) | |
8056 | ||
8057 | (define_insn "main_pool" | |
585539a1 UW |
8058 | [(set (match_operand 0 "register_operand" "=a") |
8059 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
8060 | "GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 | 8061 | "* abort ();" |
b628bd8e | 8062 | [(set (attr "type") |
ea77e738 UW |
8063 | (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) |
8064 | (const_string "larl") (const_string "la")))]) | |
5af2f3d3 | 8065 | |
aee4e0db | 8066 | (define_insn "reload_base_31" |
9e8327e3 UW |
8067 | [(set (match_operand 0 "register_operand" "=a") |
8068 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
8069 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 8070 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e UW |
8071 | [(set_attr "length" "6") |
8072 | (set_attr "type" "la")]) | |
b2ccb744 | 8073 | |
aee4e0db | 8074 | (define_insn "reload_base_64" |
9e8327e3 UW |
8075 | [(set (match_operand 0 "register_operand" "=a") |
8076 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
8077 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 8078 | "larl\t%0,%1" |
aee4e0db | 8079 | [(set_attr "op_type" "RIL") |
077dab3b | 8080 | (set_attr "type" "larl")]) |
aee4e0db | 8081 | |
aee4e0db | 8082 | (define_insn "pool" |
fd7643fb | 8083 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db UW |
8084 | "" |
8085 | "* abort ();" | |
b628bd8e | 8086 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 8087 | |
4023fb28 UW |
8088 | ;; |
8089 | ;; Insns related to generating the function prologue and epilogue. | |
8090 | ;; | |
8091 | ||
8092 | ||
8093 | (define_expand "prologue" | |
8094 | [(use (const_int 0))] | |
8095 | "" | |
10bbf137 | 8096 | "s390_emit_prologue (); DONE;") |
4023fb28 | 8097 | |
2f7e5a0d EC |
8098 | (define_insn "prologue_tpf" |
8099 | [(unspec_volatile [(const_int 0)] UNSPECV_TPF_PROLOGUE) | |
8100 | (clobber (reg:DI 1))] | |
3839e36a | 8101 | "TARGET_TPF_PROFILING" |
2f7e5a0d EC |
8102 | "bas\t%%r1,4064" |
8103 | [(set_attr "type" "jsr") | |
8104 | (set_attr "op_type" "RX")]) | |
8105 | ||
4023fb28 UW |
8106 | (define_expand "epilogue" |
8107 | [(use (const_int 1))] | |
8108 | "" | |
ed9676cf AK |
8109 | "s390_emit_epilogue (false); DONE;") |
8110 | ||
2f7e5a0d EC |
8111 | (define_insn "epilogue_tpf" |
8112 | [(unspec_volatile [(const_int 0)] UNSPECV_TPF_EPILOGUE) | |
8113 | (clobber (reg:DI 1))] | |
3839e36a | 8114 | "TARGET_TPF_PROFILING" |
2f7e5a0d EC |
8115 | "bas\t%%r1,4070" |
8116 | [(set_attr "type" "jsr") | |
8117 | (set_attr "op_type" "RX")]) | |
8118 | ||
8119 | ||
ed9676cf AK |
8120 | (define_expand "sibcall_epilogue" |
8121 | [(use (const_int 0))] | |
8122 | "" | |
8123 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 8124 | |
9e8327e3 | 8125 | (define_insn "*return" |
4023fb28 | 8126 | [(return) |
9e8327e3 UW |
8127 | (use (match_operand 0 "register_operand" "a"))] |
8128 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 8129 | "br\t%0" |
4023fb28 | 8130 | [(set_attr "op_type" "RR") |
c7453384 | 8131 | (set_attr "type" "jsr") |
077dab3b | 8132 | (set_attr "atype" "agen")]) |
4023fb28 | 8133 | |
4023fb28 | 8134 | |
c7453384 | 8135 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 8136 | ;; pointer. This is used for compatibility. |
c7453384 EC |
8137 | |
8138 | (define_expand "ptr_extend" | |
8139 | [(set (match_operand:DI 0 "register_operand" "=r") | |
8140 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 8141 | "TARGET_64BIT" |
c7453384 | 8142 | { |
c7453384 EC |
8143 | emit_insn (gen_anddi3 (operands[0], |
8144 | gen_lowpart (DImode, operands[1]), | |
8145 | GEN_INT (0x7fffffff))); | |
c7453384 | 8146 | DONE; |
10bbf137 | 8147 | }) |
4798630c D |
8148 | |
8149 | ;; Instruction definition to expand eh_return macro to support | |
8150 | ;; swapping in special linkage return addresses. | |
8151 | ||
8152 | (define_expand "eh_return" | |
8153 | [(use (match_operand 0 "register_operand" ""))] | |
8154 | "TARGET_TPF" | |
8155 | { | |
8156 | s390_emit_tpf_eh_return (operands[0]); | |
8157 | DONE; | |
8158 | }) | |
8159 |