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Commit | Line | Data |
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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
85ec4feb | 2 | ;; Copyright (C) 1999-2018 Free Software Foundation, Inc. |
9db1d521 | 3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
4 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
5 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | ;; version. |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
22 | |
23 | ;; | |
cd8dc1f9 | 24 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 25 | ;; |
cd8dc1f9 | 26 | |
9db1d521 HP |
27 | ;; Special formats used for outputting 390 instructions. |
28 | ;; | |
f19a9af7 AK |
29 | ;; %C: print opcode suffix for branch condition. |
30 | ;; %D: print opcode suffix for inverse branch condition. | |
31 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 32 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
33 | ;; %O: print only the displacement of a memory reference. |
34 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 35 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
36 | ;; %N: print the second word of a DImode operand. |
37 | ;; %M: print the second word of a TImode operand. | |
da48f5ec | 38 | ;; %Y: print shift count operand. |
f4aa3848 | 39 | ;; |
f19a9af7 | 40 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 41 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
42 | ;; %x: print integer X as if it's an unsigned halfword. |
43 | ;; %h: print integer X as if it's a signed halfword. | |
44 | ;; %i: print the first nonzero HImode part of X. | |
45 | ;; %j: print the first HImode part unequal to -1 of X. | |
46 | ;; %k: print the first nonzero SImode part of X. | |
47 | ;; %m: print the first SImode part unequal to -1 of X. | |
48 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
49 | ;; |
50 | ;; We have a special constraint for pattern matching. | |
51 | ;; | |
52 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
53 | ;; | |
9db1d521 | 54 | |
fd3cd001 UW |
55 | ;; |
56 | ;; UNSPEC usage | |
57 | ;; | |
58 | ||
30a49b23 AK |
59 | (define_c_enum "unspec" [ |
60 | ; Miscellaneous | |
61 | UNSPEC_ROUND | |
30a49b23 AK |
62 | UNSPEC_ICM |
63 | UNSPEC_TIE | |
10bbf137 | 64 | |
5a3fe9b6 AK |
65 | ; Convert CC into a str comparison result and copy it into an |
66 | ; integer register | |
67 | ; cc0->0, cc1->1, cc2->-1, (cc3->-1) | |
68 | UNSPEC_STRCMPCC_TO_INT | |
69 | ||
70 | ; Copy CC as is into the lower 2 bits of an integer register | |
71 | UNSPEC_CC_TO_INT | |
72 | ||
da0dcab1 DV |
73 | ; The right hand side of an setmem |
74 | UNSPEC_REPLICATE_BYTE | |
75 | ||
10bbf137 | 76 | ; GOT/PLT and lt-relative accesses |
30a49b23 AK |
77 | UNSPEC_LTREL_OFFSET |
78 | UNSPEC_LTREL_BASE | |
79 | UNSPEC_POOL_OFFSET | |
80 | UNSPEC_GOTENT | |
81 | UNSPEC_GOT | |
82 | UNSPEC_GOTOFF | |
83 | UNSPEC_PLT | |
84 | UNSPEC_PLTOFF | |
fd7643fb UW |
85 | |
86 | ; Literal pool | |
30a49b23 AK |
87 | UNSPEC_RELOAD_BASE |
88 | UNSPEC_MAIN_BASE | |
89 | UNSPEC_LTREF | |
90 | UNSPEC_INSN | |
91 | UNSPEC_EXECUTE | |
84b4c7b5 | 92 | UNSPEC_EXECUTE_JUMP |
fd7643fb | 93 | |
1a8c13b3 | 94 | ; Atomic Support |
30a49b23 | 95 | UNSPEC_MB |
78ce265b | 96 | UNSPEC_MOVA |
1a8c13b3 | 97 | |
fd7643fb | 98 | ; TLS relocation specifiers |
30a49b23 AK |
99 | UNSPEC_TLSGD |
100 | UNSPEC_TLSLDM | |
101 | UNSPEC_NTPOFF | |
102 | UNSPEC_DTPOFF | |
103 | UNSPEC_GOTNTPOFF | |
104 | UNSPEC_INDNTPOFF | |
fd3cd001 UW |
105 | |
106 | ; TLS support | |
30a49b23 AK |
107 | UNSPEC_TLSLDM_NTPOFF |
108 | UNSPEC_TLS_LOAD | |
91d39d71 UW |
109 | |
110 | ; String Functions | |
30a49b23 AK |
111 | UNSPEC_SRST |
112 | UNSPEC_MVST | |
638e37c2 | 113 | |
7b8acc34 | 114 | ; Stack Smashing Protector |
30a49b23 AK |
115 | UNSPEC_SP_SET |
116 | UNSPEC_SP_TEST | |
85dae55a | 117 | |
4cb4721f MK |
118 | ; Split stack support |
119 | UNSPEC_STACK_CHECK | |
120 | ||
638e37c2 | 121 | ; Test Data Class (TDC) |
30a49b23 | 122 | UNSPEC_TDC_INSN |
65b1d8ea AK |
123 | |
124 | ; Population Count | |
30a49b23 AK |
125 | UNSPEC_POPCNT |
126 | UNSPEC_COPYSIGN | |
d12a76f3 AK |
127 | |
128 | ; Load FP Integer | |
129 | UNSPEC_FPINT_FLOOR | |
130 | UNSPEC_FPINT_BTRUNC | |
131 | UNSPEC_FPINT_ROUND | |
132 | UNSPEC_FPINT_CEIL | |
133 | UNSPEC_FPINT_NEARBYINT | |
134 | UNSPEC_FPINT_RINT | |
085261c8 | 135 | |
3af82a61 AK |
136 | UNSPEC_LCBB |
137 | ||
085261c8 | 138 | ; Vector |
3af82a61 AK |
139 | UNSPEC_VEC_SMULT_HI |
140 | UNSPEC_VEC_UMULT_HI | |
141 | UNSPEC_VEC_SMULT_LO | |
085261c8 AK |
142 | UNSPEC_VEC_SMULT_EVEN |
143 | UNSPEC_VEC_UMULT_EVEN | |
144 | UNSPEC_VEC_SMULT_ODD | |
145 | UNSPEC_VEC_UMULT_ODD | |
3af82a61 AK |
146 | |
147 | UNSPEC_VEC_VMAL | |
148 | UNSPEC_VEC_VMAH | |
149 | UNSPEC_VEC_VMALH | |
150 | UNSPEC_VEC_VMAE | |
151 | UNSPEC_VEC_VMALE | |
152 | UNSPEC_VEC_VMAO | |
153 | UNSPEC_VEC_VMALO | |
154 | ||
155 | UNSPEC_VEC_GATHER | |
156 | UNSPEC_VEC_EXTRACT | |
157 | UNSPEC_VEC_INSERT_AND_ZERO | |
158 | UNSPEC_VEC_LOAD_BNDRY | |
085261c8 | 159 | UNSPEC_VEC_LOAD_LEN |
76794c52 | 160 | UNSPEC_VEC_LOAD_LEN_R |
3af82a61 AK |
161 | UNSPEC_VEC_MERGEH |
162 | UNSPEC_VEC_MERGEL | |
163 | UNSPEC_VEC_PACK | |
164 | UNSPEC_VEC_PACK_SATURATE | |
165 | UNSPEC_VEC_PACK_SATURATE_CC | |
166 | UNSPEC_VEC_PACK_SATURATE_GENCC | |
167 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE | |
168 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC | |
169 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC | |
170 | UNSPEC_VEC_PERM | |
171 | UNSPEC_VEC_PERMI | |
172 | UNSPEC_VEC_EXTEND | |
173 | UNSPEC_VEC_STORE_LEN | |
76794c52 AK |
174 | UNSPEC_VEC_STORE_LEN_R |
175 | UNSPEC_VEC_VBPERM | |
3af82a61 AK |
176 | UNSPEC_VEC_UNPACKH |
177 | UNSPEC_VEC_UNPACKH_L | |
178 | UNSPEC_VEC_UNPACKL | |
179 | UNSPEC_VEC_UNPACKL_L | |
180 | UNSPEC_VEC_ADDC | |
3af82a61 AK |
181 | UNSPEC_VEC_ADDE_U128 |
182 | UNSPEC_VEC_ADDEC_U128 | |
183 | UNSPEC_VEC_AVG | |
184 | UNSPEC_VEC_AVGU | |
185 | UNSPEC_VEC_CHECKSUM | |
186 | UNSPEC_VEC_GFMSUM | |
187 | UNSPEC_VEC_GFMSUM_128 | |
188 | UNSPEC_VEC_GFMSUM_ACCUM | |
189 | UNSPEC_VEC_GFMSUM_ACCUM_128 | |
190 | UNSPEC_VEC_SET | |
191 | ||
192 | UNSPEC_VEC_VSUMG | |
193 | UNSPEC_VEC_VSUMQ | |
194 | UNSPEC_VEC_VSUM | |
195 | UNSPEC_VEC_RL_MASK | |
196 | UNSPEC_VEC_SLL | |
197 | UNSPEC_VEC_SLB | |
198 | UNSPEC_VEC_SLDB | |
199 | UNSPEC_VEC_SRAL | |
200 | UNSPEC_VEC_SRAB | |
201 | UNSPEC_VEC_SRL | |
202 | UNSPEC_VEC_SRLB | |
203 | ||
3af82a61 | 204 | UNSPEC_VEC_SUBC |
3af82a61 AK |
205 | UNSPEC_VEC_SUBE_U128 |
206 | UNSPEC_VEC_SUBEC_U128 | |
207 | ||
208 | UNSPEC_VEC_TEST_MASK | |
209 | ||
210 | UNSPEC_VEC_VFAE | |
211 | UNSPEC_VEC_VFAECC | |
212 | ||
213 | UNSPEC_VEC_VFEE | |
214 | UNSPEC_VEC_VFEECC | |
085261c8 AK |
215 | UNSPEC_VEC_VFENE |
216 | UNSPEC_VEC_VFENECC | |
3af82a61 AK |
217 | |
218 | UNSPEC_VEC_VISTR | |
219 | UNSPEC_VEC_VISTRCC | |
220 | ||
221 | UNSPEC_VEC_VSTRC | |
222 | UNSPEC_VEC_VSTRCCC | |
223 | ||
224 | UNSPEC_VEC_VCDGB | |
225 | UNSPEC_VEC_VCDLGB | |
226 | ||
227 | UNSPEC_VEC_VCGDB | |
228 | UNSPEC_VEC_VCLGDB | |
229 | ||
76794c52 | 230 | UNSPEC_VEC_VFI |
3af82a61 | 231 | |
76794c52 AK |
232 | UNSPEC_VEC_VFLL ; vector fp load lengthened |
233 | UNSPEC_VEC_VFLR ; vector fp load rounded | |
3af82a61 | 234 | |
76794c52 AK |
235 | UNSPEC_VEC_VFTCI |
236 | UNSPEC_VEC_VFTCICC | |
237 | ||
238 | UNSPEC_VEC_MSUM | |
239 | ||
240 | UNSPEC_VEC_VFMIN | |
241 | UNSPEC_VEC_VFMAX | |
085261c8 | 242 | ]) |
fd3cd001 UW |
243 | |
244 | ;; | |
245 | ;; UNSPEC_VOLATILE usage | |
246 | ;; | |
247 | ||
30a49b23 AK |
248 | (define_c_enum "unspecv" [ |
249 | ; Blockage | |
250 | UNSPECV_BLOCKAGE | |
10bbf137 | 251 | |
2f7e5a0d | 252 | ; TPF Support |
30a49b23 AK |
253 | UNSPECV_TPF_PROLOGUE |
254 | UNSPECV_TPF_EPILOGUE | |
2f7e5a0d | 255 | |
10bbf137 | 256 | ; Literal pool |
30a49b23 AK |
257 | UNSPECV_POOL |
258 | UNSPECV_POOL_SECTION | |
259 | UNSPECV_POOL_ALIGN | |
260 | UNSPECV_POOL_ENTRY | |
261 | UNSPECV_MAIN_POOL | |
fd7643fb UW |
262 | |
263 | ; TLS support | |
30a49b23 | 264 | UNSPECV_SET_TP |
e0374221 AS |
265 | |
266 | ; Atomic Support | |
30a49b23 AK |
267 | UNSPECV_CAS |
268 | UNSPECV_ATOMIC_OP | |
5a3fe9b6 | 269 | |
aad98a61 AK |
270 | ; Non-branch nops used for compare-and-branch adjustments on z10 |
271 | UNSPECV_NOP_LR_0 | |
272 | UNSPECV_NOP_LR_1 | |
273 | ||
f8af0e30 DV |
274 | ; Hotpatching (unremovable NOPs) |
275 | UNSPECV_NOP_2_BYTE | |
276 | UNSPECV_NOP_4_BYTE | |
277 | UNSPECV_NOP_6_BYTE | |
278 | ||
5a3fe9b6 AK |
279 | ; Transactional Execution support |
280 | UNSPECV_TBEGIN | |
2561451d | 281 | UNSPECV_TBEGIN_TDB |
5a3fe9b6 AK |
282 | UNSPECV_TBEGINC |
283 | UNSPECV_TEND | |
284 | UNSPECV_TABORT | |
285 | UNSPECV_ETND | |
286 | UNSPECV_NTSTG | |
287 | UNSPECV_PPA | |
004f64e1 AK |
288 | |
289 | ; Set and get floating point control register | |
290 | UNSPECV_SFPC | |
291 | UNSPECV_EFPC | |
4cb4721f MK |
292 | |
293 | ; Split stack support | |
294 | UNSPECV_SPLIT_STACK_CALL | |
295 | UNSPECV_SPLIT_STACK_DATA | |
539405d5 AK |
296 | |
297 | UNSPECV_OSC_BREAK | |
fd3cd001 UW |
298 | ]) |
299 | ||
ae156f85 AS |
300 | ;; |
301 | ;; Registers | |
302 | ;; | |
303 | ||
35dd9a0e AK |
304 | ; Registers with special meaning |
305 | ||
ae156f85 AS |
306 | (define_constants |
307 | [ | |
308 | ; Sibling call register. | |
309 | (SIBCALL_REGNUM 1) | |
84b4c7b5 AK |
310 | ; A call-clobbered reg which can be used in indirect branch thunks |
311 | (INDIRECT_BRANCH_THUNK_REGNUM 1) | |
ae156f85 AS |
312 | ; Literal pool base register. |
313 | (BASE_REGNUM 13) | |
314 | ; Return address register. | |
315 | (RETURN_REGNUM 14) | |
82c6f58a AK |
316 | ; Stack pointer register. |
317 | (STACK_REGNUM 15) | |
ae156f85 AS |
318 | ; Condition code register. |
319 | (CC_REGNUM 33) | |
f4aa3848 | 320 | ; Thread local storage pointer register. |
ae156f85 AS |
321 | (TP_REGNUM 36) |
322 | ]) | |
323 | ||
35dd9a0e AK |
324 | ; Hardware register names |
325 | ||
326 | (define_constants | |
327 | [ | |
328 | ; General purpose registers | |
329 | (GPR0_REGNUM 0) | |
af344a30 | 330 | (GPR1_REGNUM 1) |
82379bdf AK |
331 | (GPR2_REGNUM 2) |
332 | (GPR6_REGNUM 6) | |
35dd9a0e AK |
333 | ; Floating point registers. |
334 | (FPR0_REGNUM 16) | |
2cf4c39e AK |
335 | (FPR1_REGNUM 20) |
336 | (FPR2_REGNUM 17) | |
337 | (FPR3_REGNUM 21) | |
338 | (FPR4_REGNUM 18) | |
339 | (FPR5_REGNUM 22) | |
340 | (FPR6_REGNUM 19) | |
341 | (FPR7_REGNUM 23) | |
342 | (FPR8_REGNUM 24) | |
343 | (FPR9_REGNUM 28) | |
344 | (FPR10_REGNUM 25) | |
345 | (FPR11_REGNUM 29) | |
346 | (FPR12_REGNUM 26) | |
347 | (FPR13_REGNUM 30) | |
348 | (FPR14_REGNUM 27) | |
349 | (FPR15_REGNUM 31) | |
085261c8 AK |
350 | (VR0_REGNUM 16) |
351 | (VR16_REGNUM 38) | |
352 | (VR23_REGNUM 45) | |
353 | (VR24_REGNUM 46) | |
354 | (VR31_REGNUM 53) | |
35dd9a0e AK |
355 | ]) |
356 | ||
ae8e301e AK |
357 | ; Rounding modes for binary floating point numbers |
358 | (define_constants | |
359 | [(BFP_RND_CURRENT 0) | |
360 | (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1) | |
361 | (BFP_RND_PREP_FOR_SHORT_PREC 3) | |
362 | (BFP_RND_NEAREST_TIE_TO_EVEN 4) | |
363 | (BFP_RND_TOWARD_0 5) | |
364 | (BFP_RND_TOWARD_INF 6) | |
365 | (BFP_RND_TOWARD_MINF 7)]) | |
366 | ||
367 | ; Rounding modes for decimal floating point numbers | |
368 | ; 1-7 were introduced with the floating point extension facility | |
369 | ; available with z196 | |
370 | ; With these rounding modes (1-7) a quantum exception might occur | |
371 | ; which is suppressed for the other modes. | |
372 | (define_constants | |
373 | [(DFP_RND_CURRENT 0) | |
374 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1) | |
375 | (DFP_RND_CURRENT_QUANTEXC 2) | |
376 | (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC 3) | |
377 | (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC 4) | |
378 | (DFP_RND_TOWARD_0_QUANTEXC 5) | |
379 | (DFP_RND_TOWARD_INF_QUANTEXC 6) | |
380 | (DFP_RND_TOWARD_MINF_QUANTEXC 7) | |
381 | (DFP_RND_NEAREST_TIE_TO_EVEN 8) | |
382 | (DFP_RND_TOWARD_0 9) | |
383 | (DFP_RND_TOWARD_INF 10) | |
384 | (DFP_RND_TOWARD_MINF 11) | |
385 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0 12) | |
386 | (DFP_RND_NEAREST_TIE_TO_0 13) | |
387 | (DFP_RND_AWAY_FROM_0 14) | |
388 | (DFP_RND_PREP_FOR_SHORT_PREC 15)]) | |
389 | ||
35dd9a0e AK |
390 | ;; |
391 | ;; PFPO GPR0 argument format | |
392 | ;; | |
393 | ||
394 | (define_constants | |
395 | [ | |
396 | ; PFPO operation type | |
397 | (PFPO_CONVERT 0x1000000) | |
398 | ; PFPO operand types | |
399 | (PFPO_OP_TYPE_SF 0x5) | |
400 | (PFPO_OP_TYPE_DF 0x6) | |
401 | (PFPO_OP_TYPE_TF 0x7) | |
402 | (PFPO_OP_TYPE_SD 0x8) | |
403 | (PFPO_OP_TYPE_DD 0x9) | |
404 | (PFPO_OP_TYPE_TD 0xa) | |
405 | ; Bitposition of operand types | |
406 | (PFPO_OP0_TYPE_SHIFT 16) | |
407 | (PFPO_OP1_TYPE_SHIFT 8) | |
408 | ]) | |
409 | ||
5a3fe9b6 AK |
410 | ; Immediate operands for tbegin and tbeginc |
411 | (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c | |
412 | (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08 | |
fd3cd001 | 413 | |
29a74354 UW |
414 | ;; Instruction operand type as used in the Principles of Operation. |
415 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 416 | |
29a74354 | 417 | (define_attr "op_type" |
76794c52 | 418 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX,VSI" |
b628bd8e | 419 | (const_string "NN")) |
9db1d521 | 420 | |
29a74354 | 421 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 422 | |
077dab3b | 423 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 424 | cs,vs,store,sem,idiv, |
ed0e512a | 425 | imulhi,imulsi,imuldi, |
2cdece44 | 426 | branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, |
f61a2c7d AK |
427 | floadtf,floaddf,floadsf,fstoredf,fstoresf, |
428 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 | 429 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
65b1d8ea | 430 | fmadddf,fmaddsf, |
9381e3f1 WG |
431 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, |
432 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
433 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
434 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
435 | ftoidfp, other" | |
29a74354 UW |
436 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
437 | (eq_attr "op_type" "SS") (const_string "cs")] | |
438 | (const_string "integer"))) | |
9db1d521 | 439 | |
29a74354 UW |
440 | ;; Another attribute used for scheduling purposes: |
441 | ;; agen: Instruction uses the address generation unit | |
442 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
443 | |
444 | (define_attr "atype" "agen,reg" | |
62d3f261 | 445 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF") |
0101708c AS |
446 | (const_string "reg") |
447 | (const_string "agen"))) | |
9db1d521 | 448 | |
9381e3f1 WG |
449 | ;; Properties concerning Z10 execution grouping and value forwarding. |
450 | ;; z10_super: instruction is superscalar. | |
451 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
452 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
453 | ;; target register. It can forward this value to a second instruction that reads | |
454 | ;; the same register if that second instruction is issued in the same group. | |
455 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
456 | ;; instruction in the S pipe writes to the register, then the T instruction | |
457 | ;; can immediately read the new value. | |
458 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
459 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
9381e3f1 WG |
460 | ;; |
461 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
462 | ||
463 | ||
464 | (define_attr "z10prop" "none, | |
465 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
466 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
467 | z10_rec, | |
468 | z10_fr, z10_fr_A3, z10_fr_E1, | |
e3cba5e5 | 469 | z10_c" |
9381e3f1 WG |
470 | (const_string "none")) |
471 | ||
65b1d8ea AK |
472 | ;; Properties concerning Z196 decoding |
473 | ;; z196_alone: must group alone | |
474 | ;; z196_end: ends a group | |
475 | ;; z196_cracked: instruction is cracked or expanded | |
476 | (define_attr "z196prop" "none, | |
477 | z196_alone, z196_ends, | |
478 | z196_cracked" | |
479 | (const_string "none")) | |
9381e3f1 | 480 | |
84b4c7b5 AK |
481 | ; mnemonics which only get defined through if_then_else currently |
482 | ; don't get added to the list values automatically and hence need to | |
483 | ; be listed here. | |
8cc6307c | 484 | (define_attr "mnemonic" "b,bas,basr,bc,bcr_flush,unknown" (const_string "unknown")) |
22ac2c2f | 485 | |
9db1d521 HP |
486 | ;; Length in bytes. |
487 | ||
488 | (define_attr "length" "" | |
62d3f261 AK |
489 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
490 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)] | |
b628bd8e | 491 | (const_int 6))) |
9db1d521 | 492 | |
29a74354 UW |
493 | |
494 | ;; Processor type. This attribute must exactly match the processor_type | |
52d4aa4f | 495 | ;; enumeration in s390.h. |
29a74354 | 496 | |
52d4aa4f | 497 | (define_attr "cpu" "z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,arch12" |
90c6fd8a | 498 | (const (symbol_ref "s390_tune_attr"))) |
29a74354 | 499 | |
b5e0425c | 500 | (define_attr "cpu_facility" |
6654e96f | 501 | "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,arch12,vxe" |
3af8e996 AK |
502 | (const_string "standard")) |
503 | ||
504 | (define_attr "enabled" "" | |
505 | (cond [(eq_attr "cpu_facility" "standard") | |
506 | (const_int 1) | |
507 | ||
508 | (and (eq_attr "cpu_facility" "ieee") | |
d7f99b2c | 509 | (match_test "TARGET_CPU_IEEE_FLOAT")) |
3af8e996 AK |
510 | (const_int 1) |
511 | ||
512 | (and (eq_attr "cpu_facility" "zarch") | |
d7f99b2c | 513 | (match_test "TARGET_ZARCH")) |
3af8e996 AK |
514 | (const_int 1) |
515 | ||
516 | (and (eq_attr "cpu_facility" "longdisp") | |
d7f99b2c | 517 | (match_test "TARGET_LONG_DISPLACEMENT")) |
3af8e996 AK |
518 | (const_int 1) |
519 | ||
520 | (and (eq_attr "cpu_facility" "extimm") | |
d7f99b2c | 521 | (match_test "TARGET_EXTIMM")) |
3af8e996 AK |
522 | (const_int 1) |
523 | ||
524 | (and (eq_attr "cpu_facility" "dfp") | |
d7f99b2c | 525 | (match_test "TARGET_DFP")) |
93538e8e AK |
526 | (const_int 1) |
527 | ||
8cc6307c | 528 | (eq_attr "cpu_facility" "cpu_zarch") |
b5e0425c AK |
529 | (const_int 1) |
530 | ||
93538e8e | 531 | (and (eq_attr "cpu_facility" "z10") |
d7f99b2c | 532 | (match_test "TARGET_Z10")) |
65b1d8ea AK |
533 | (const_int 1) |
534 | ||
535 | (and (eq_attr "cpu_facility" "z196") | |
d7f99b2c | 536 | (match_test "TARGET_Z196")) |
22ac2c2f AK |
537 | (const_int 1) |
538 | ||
539 | (and (eq_attr "cpu_facility" "zEC12") | |
540 | (match_test "TARGET_ZEC12")) | |
55ac540c AK |
541 | (const_int 1) |
542 | ||
285363a1 | 543 | (and (eq_attr "cpu_facility" "vx") |
55ac540c | 544 | (match_test "TARGET_VX")) |
bf749919 DV |
545 | (const_int 1) |
546 | ||
547 | (and (eq_attr "cpu_facility" "z13") | |
548 | (match_test "TARGET_Z13")) | |
549 | (const_int 1) | |
6654e96f AK |
550 | |
551 | (and (eq_attr "cpu_facility" "arch12") | |
552 | (match_test "TARGET_ARCH12")) | |
553 | (const_int 1) | |
554 | ||
555 | (and (eq_attr "cpu_facility" "vxe") | |
556 | (match_test "TARGET_VXE")) | |
557 | (const_int 1) | |
bf749919 | 558 | ] |
3af8e996 AK |
559 | (const_int 0))) |
560 | ||
52d4aa4f | 561 | ;; Pipeline description for z900. |
29a74354 UW |
562 | (include "2064.md") |
563 | ||
3443392a | 564 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
565 | (include "2084.md") |
566 | ||
9381e3f1 WG |
567 | ;; Pipeline description for z10 |
568 | (include "2097.md") | |
569 | ||
65b1d8ea AK |
570 | ;; Pipeline description for z196 |
571 | (include "2817.md") | |
572 | ||
22ac2c2f AK |
573 | ;; Pipeline description for zEC12 |
574 | (include "2827.md") | |
575 | ||
23902021 AK |
576 | ;; Pipeline description for z13 |
577 | (include "2964.md") | |
578 | ||
0bfc3f69 AS |
579 | ;; Predicates |
580 | (include "predicates.md") | |
581 | ||
cd8dc1f9 WG |
582 | ;; Constraint definitions |
583 | (include "constraints.md") | |
584 | ||
a8ba31f2 EC |
585 | ;; Other includes |
586 | (include "tpf.md") | |
f52c81dd | 587 | |
3abcb3a7 | 588 | ;; Iterators |
f52c81dd | 589 | |
085261c8 AK |
590 | (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF]) |
591 | ||
3abcb3a7 | 592 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 593 | ;; same template. |
f4aa3848 | 594 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
0387c142 | 595 | (SD "TARGET_HARD_DFP")]) |
3abcb3a7 HPN |
596 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
597 | (define_mode_iterator BFP [TF DF SF]) | |
598 | (define_mode_iterator DFP [TD DD]) | |
599 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
600 | (define_mode_iterator DSF [DF SF]) | |
601 | (define_mode_iterator SD_SF [SF SD]) | |
602 | (define_mode_iterator DD_DF [DF DD]) | |
603 | (define_mode_iterator TD_TF [TF TD]) | |
604 | ||
3abcb3a7 | 605 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 606 | ;; from the same template. |
9602b6a1 | 607 | (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) |
78ce265b | 608 | (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) |
3abcb3a7 | 609 | (define_mode_iterator DSI [DI SI]) |
78ce265b | 610 | (define_mode_iterator TDI [TI DI]) |
9db2f16d | 611 | |
3abcb3a7 | 612 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 613 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 | 614 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
9db2f16d | 615 | |
78ce265b RH |
616 | ;; These macros refer to the actual word_mode of the configuration. |
617 | ;; This is equal to Pmode except on 31-bit machines in zarch mode. | |
9602b6a1 AK |
618 | (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) |
619 | (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) | |
620 | ||
6e0d70c9 AK |
621 | ;; Used by the umul pattern to express modes having half the size. |
622 | (define_mode_attr DWH [(TI "DI") (DI "SI")]) | |
623 | (define_mode_attr dwh [(TI "di") (DI "si")]) | |
624 | ||
3abcb3a7 | 625 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 626 | ;; the same template. |
3abcb3a7 | 627 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 628 | |
3abcb3a7 | 629 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 630 | ;; same template. |
9602b6a1 | 631 | (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) |
78ce265b | 632 | (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) |
64c744b9 | 633 | (define_mode_iterator SINT [SI HI QI]) |
342cf42b | 634 | |
3abcb3a7 | 635 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 636 | ;; the same template. |
3abcb3a7 | 637 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 638 | |
d12a76f3 | 639 | ;; This iterator allows r[ox]sbg to be defined with the same template |
571e408a RH |
640 | (define_code_iterator IXOR [ior xor]) |
641 | ||
d12a76f3 AK |
642 | ;; This iterator is used to expand the patterns for the nearest |
643 | ;; integer functions. | |
644 | (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC | |
645 | UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL | |
646 | UNSPEC_FPINT_NEARBYINT]) | |
647 | (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor") | |
648 | (UNSPEC_FPINT_BTRUNC "btrunc") | |
649 | (UNSPEC_FPINT_ROUND "round") | |
650 | (UNSPEC_FPINT_CEIL "ceil") | |
651 | (UNSPEC_FPINT_NEARBYINT "nearbyint")]) | |
652 | (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7") | |
653 | (UNSPEC_FPINT_BTRUNC "5") | |
654 | (UNSPEC_FPINT_ROUND "1") | |
655 | (UNSPEC_FPINT_CEIL "6") | |
656 | (UNSPEC_FPINT_NEARBYINT "0")]) | |
657 | ||
3abcb3a7 HPN |
658 | ;; This iterator and attribute allow to combine most atomic operations. |
659 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
65b1d8ea | 660 | (define_code_iterator ATOMIC_Z196 [and ior xor plus]) |
cf5b43b0 | 661 | (define_code_attr atomic [(and "and") (ior "or") (xor "xor") |
45d18331 | 662 | (plus "add") (minus "sub") (mult "nand")]) |
65b1d8ea | 663 | (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) |
45d18331 | 664 | |
f4aa3848 | 665 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
609e7e80 AK |
666 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. |
667 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) | |
f337b930 | 668 | |
f4aa3848 AK |
669 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
670 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
609e7e80 AK |
671 | ;; SDmode. |
672 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 673 | |
609e7e80 | 674 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
675 | ;; Likewise for "<RXe>". |
676 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
677 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
678 | ||
609e7e80 | 679 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 680 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
681 | ;; dfp variants in a single insn definition. |
682 | ||
62d3f261 AK |
683 | ;; These mode attributes are supposed to be used in the `enabled' insn |
684 | ;; attribute to disable certain alternatives for certain modes. | |
685 | (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")]) | |
686 | (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")]) | |
687 | (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")]) | |
688 | (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0") | |
689 | (TD "0") (DD "0") (DD "0") | |
690 | (TI "0") (DI "*") (SI "0")]) | |
2de2b3f9 AK |
691 | (define_mode_attr DF [(TF "0") (DF "*") (SF "0") |
692 | (TD "0") (DD "0") (DD "0") | |
693 | (TI "0") (DI "0") (SI "0")]) | |
694 | (define_mode_attr SF [(TF "0") (DF "0") (SF "*") | |
695 | (TD "0") (DD "0") (DD "0") | |
696 | (TI "0") (DI "0") (SI "0")]) | |
f5905b37 | 697 | |
85dae55a AK |
698 | ;; This attribute is used in the operand constraint list |
699 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
700 | ;; TFmode values are represented by a fp register pair. Since the | |
701 | ;; sign bit instructions only handle single source and target fp registers | |
702 | ;; these instructions can only be used for TFmode values if the source and | |
703 | ;; target operand uses the same fp register. | |
704 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
705 | ||
3abcb3a7 | 706 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
707 | ;; within instruction mnemonics. |
708 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
709 | ||
0387c142 WG |
710 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
711 | ;; modes and to an empty string for bfp modes. | |
712 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
713 | ||
1b48c8cc AS |
714 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
715 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
716 | ;; version only operates on one register. | |
717 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
718 | ||
719 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
720 | ;; version only operates on one register. The DImode version needs an additional | |
721 | ;; register for the assembler output. | |
722 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
723 | |
724 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
725 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
726 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
727 | ||
728 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 729 | ;; pattern itself and the corresponding function calls. |
f337b930 | 730 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
731 | |
732 | ;; This attribute handles differences in the instruction 'type' and will result | |
733 | ;; in "RRE" for DImode and "RR" for SImode. | |
734 | (define_mode_attr E [(DI "E") (SI "")]) | |
735 | ||
3298c037 AK |
736 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
737 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
738 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
739 | ||
8006eaa6 AS |
740 | ;; This attribute handles differences in the instruction 'type' and will result |
741 | ;; in "RSE" for TImode and "RS" for DImode. | |
742 | (define_mode_attr TE [(TI "E") (DI "")]) | |
743 | ||
9a91a21f AS |
744 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
745 | ;; and "lcr" in SImode. | |
746 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 747 | |
3298c037 AK |
748 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
749 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
750 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
751 | ;; variant for long displacements. | |
752 | (define_mode_attr y [(DI "g") (SI "y")]) | |
753 | ||
9602b6a1 | 754 | ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode |
8006eaa6 AS |
755 | ;; and "cds" in DImode. |
756 | (define_mode_attr tg [(TI "g") (DI "")]) | |
757 | ||
78ce265b RH |
758 | ;; In TDI templates, a string like "c<d>sg". |
759 | (define_mode_attr td [(TI "d") (DI "")]) | |
760 | ||
2f8f8434 AS |
761 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
762 | ;; and "cfdbr" in SImode. | |
763 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
764 | ||
65b1d8ea AK |
765 | ;; In GPR templates, a string like sll<gk> will expand to sllg for DI |
766 | ;; and sllk for SI. This way it is possible to merge the new z196 SI | |
767 | ;; 3 operands shift instructions into the existing patterns. | |
768 | (define_mode_attr gk [(DI "g") (SI "k")]) | |
769 | ||
f52c81dd AS |
770 | ;; ICM mask required to load MODE value into the lowest subreg |
771 | ;; of a SImode register. | |
772 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
773 | ||
f6ee577c AS |
774 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
775 | ;; HImode and "llgc" in QImode. | |
776 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
777 | ||
a1aed706 AS |
778 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
779 | ;; in SImode. | |
780 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
781 | ||
609e7e80 AK |
782 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
783 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
784 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
785 | ||
f52c81dd AS |
786 | ;; Maximum unsigned integer that fits in MODE. |
787 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
788 | ||
75ca1b39 RH |
789 | ;; Start and end field computations for RISBG et al. |
790 | (define_mode_attr bfstart [(DI "s") (SI "t")]) | |
791 | (define_mode_attr bfend [(DI "e") (SI "f")]) | |
792 | ||
2542ef05 RH |
793 | ;; In place of GET_MODE_BITSIZE (<MODE>mode) |
794 | (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) | |
576987fc DV |
795 | ;; 64 - bitsize |
796 | (define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")]) | |
797 | (define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")]) | |
2542ef05 | 798 | |
da0dcab1 DV |
799 | ;; In place of GET_MODE_SIZE (<MODE>mode) |
800 | (define_mode_attr modesize [(DI "8") (SI "4")]) | |
801 | ||
177bc204 RS |
802 | ;; Allow return and simple_return to be defined from a single template. |
803 | (define_code_iterator ANY_RETURN [return simple_return]) | |
804 | ||
6e5b5de8 AK |
805 | |
806 | ||
807 | ; Condition code modes generated by vector fp comparisons. These will | |
808 | ; be used also in single element mode. | |
809 | (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE]) | |
810 | ; Used with VFCMP to expand part of the mnemonic | |
811 | ; For fp we have a mismatch: eq in the insn name - e in asm | |
812 | (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) | |
a6a2b532 | 813 | (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVIH "h") (CCVIHU "hl") (CCVFH "h") (CCVFHE "he")]) |
6e5b5de8 | 814 | |
191eb16d AK |
815 | ;; Subst pattern definitions |
816 | (include "subst.md") | |
6e5b5de8 | 817 | |
085261c8 AK |
818 | (include "vector.md") |
819 | ||
9db1d521 HP |
820 | ;; |
821 | ;;- Compare instructions. | |
822 | ;; | |
823 | ||
07893d4f | 824 | ; Test-under-Mask instructions |
9db1d521 | 825 | |
07893d4f | 826 | (define_insn "*tmqi_mem" |
ae156f85 | 827 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
828 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
829 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
830 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 831 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 832 | "@ |
fc0ea003 UW |
833 | tm\t%S0,%b1 |
834 | tmy\t%S0,%b1" | |
9381e3f1 | 835 | [(set_attr "op_type" "SI,SIY") |
3e4be43f | 836 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 837 | (set_attr "z10prop" "z10_super,z10_super")]) |
9db1d521 | 838 | |
05b9aaaa | 839 | (define_insn "*tmdi_reg" |
ae156f85 | 840 | [(set (reg CC_REGNUM) |
f19a9af7 | 841 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 842 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
843 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
844 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
9602b6a1 | 845 | "TARGET_ZARCH |
3ed99cc9 | 846 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
847 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
848 | "@ | |
849 | tmhh\t%0,%i1 | |
850 | tmhl\t%0,%i1 | |
851 | tmlh\t%0,%i1 | |
852 | tmll\t%0,%i1" | |
9381e3f1 WG |
853 | [(set_attr "op_type" "RI") |
854 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
855 | |
856 | (define_insn "*tmsi_reg" | |
ae156f85 | 857 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
858 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
859 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
860 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 861 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
862 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
863 | "@ | |
864 | tmh\t%0,%i1 | |
865 | tml\t%0,%i1" | |
729e750f WG |
866 | [(set_attr "op_type" "RI") |
867 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 868 | |
f52c81dd | 869 | (define_insn "*tm<mode>_full" |
ae156f85 | 870 | [(set (reg CC_REGNUM) |
f52c81dd AS |
871 | (compare (match_operand:HQI 0 "register_operand" "d") |
872 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 873 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 874 | "tml\t%0,<max_uint>" |
729e750f WG |
875 | [(set_attr "op_type" "RI") |
876 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 877 | |
07893d4f | 878 | |
08a5aaa2 | 879 | ; |
07893d4f | 880 | ; Load-and-Test instructions |
08a5aaa2 AS |
881 | ; |
882 | ||
c0220ea4 | 883 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
884 | |
885 | (define_insn "*tstdi_sign" | |
ae156f85 | 886 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
887 | (compare |
888 | (ashiftrt:DI | |
889 | (ashift:DI | |
3e4be43f | 890 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0) |
963fc8d0 AK |
891 | (const_int 32)) (const_int 32)) |
892 | (match_operand:DI 1 "const0_operand" ""))) | |
893 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f | 894 | (sign_extend:DI (match_dup 0)))] |
9602b6a1 | 895 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" |
963fc8d0 AK |
896 | "ltgfr\t%2,%0 |
897 | ltgf\t%2,%0" | |
898 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
899 | (set_attr "cpu_facility" "*,z10") |
900 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 901 | |
43a09b63 | 902 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 903 | (define_insn "*tst<mode>_extimm" |
ec24698e | 904 | [(set (reg CC_REGNUM) |
3e4be43f | 905 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") |
08a5aaa2 AS |
906 | (match_operand:GPR 1 "const0_operand" ""))) |
907 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 908 | (match_dup 0))] |
08a5aaa2 | 909 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 910 | "@ |
08a5aaa2 AS |
911 | lt<g>r\t%2,%0 |
912 | lt<g>\t%2,%0" | |
9381e3f1 | 913 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 914 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 915 | |
97160c9b DV |
916 | ; Peephole to combine a load-and-test from volatile memory which combine does |
917 | ; not do. | |
918 | (define_peephole2 | |
919 | [(set (match_operand:GPR 0 "register_operand") | |
920 | (match_operand:GPR 2 "memory_operand")) | |
921 | (set (reg CC_REGNUM) | |
922 | (compare (match_dup 0) (match_operand:GPR 1 "const0_operand")))] | |
923 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM | |
924 | && GENERAL_REG_P (operands[0]) | |
925 | && satisfies_constraint_T (operands[2])" | |
926 | [(parallel | |
927 | [(set (reg:CCS CC_REGNUM) | |
928 | (compare:CCS (match_dup 2) (match_dup 1))) | |
929 | (set (match_dup 0) (match_dup 2))])]) | |
930 | ||
43a09b63 | 931 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 932 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 933 | [(set (reg CC_REGNUM) |
3e4be43f | 934 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") |
08a5aaa2 AS |
935 | (match_operand:GPR 1 "const0_operand" ""))) |
936 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
937 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 938 | "@ |
08a5aaa2 AS |
939 | lt<g>r\t%0,%0 |
940 | lt<g>\t%2,%0" | |
9381e3f1 | 941 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 942 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 943 | |
07893d4f | 944 | (define_insn "*tstdi" |
ae156f85 | 945 | [(set (reg CC_REGNUM) |
07893d4f UW |
946 | (compare (match_operand:DI 0 "register_operand" "d") |
947 | (match_operand:DI 1 "const0_operand" ""))) | |
948 | (set (match_operand:DI 2 "register_operand" "=d") | |
949 | (match_dup 0))] | |
9602b6a1 | 950 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 951 | "ltgr\t%2,%0" |
9381e3f1 WG |
952 | [(set_attr "op_type" "RRE") |
953 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 954 | |
07893d4f | 955 | (define_insn "*tstsi" |
ae156f85 | 956 | [(set (reg CC_REGNUM) |
d3632d41 | 957 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 958 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 959 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 960 | (match_dup 0))] |
ec24698e | 961 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 962 | "@ |
d40c829f | 963 | ltr\t%2,%0 |
fc0ea003 UW |
964 | icm\t%2,15,%S0 |
965 | icmy\t%2,15,%S0" | |
9381e3f1 | 966 | [(set_attr "op_type" "RR,RS,RSY") |
3e4be43f | 967 | (set_attr "cpu_facility" "*,*,longdisp") |
9381e3f1 | 968 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 969 | |
07893d4f | 970 | (define_insn "*tstsi_cconly" |
ae156f85 | 971 | [(set (reg CC_REGNUM) |
d3632d41 | 972 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 973 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 974 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
975 | "s390_match_ccmode(insn, CCSmode)" |
976 | "@ | |
d40c829f | 977 | ltr\t%0,%0 |
fc0ea003 UW |
978 | icm\t%2,15,%S0 |
979 | icmy\t%2,15,%S0" | |
9381e3f1 | 980 | [(set_attr "op_type" "RR,RS,RSY") |
3e4be43f | 981 | (set_attr "cpu_facility" "*,*,longdisp") |
9381e3f1 | 982 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) |
4023fb28 | 983 | |
08a5aaa2 AS |
984 | (define_insn "*tstdi_cconly_31" |
985 | [(set (reg CC_REGNUM) | |
986 | (compare (match_operand:DI 0 "register_operand" "d") | |
987 | (match_operand:DI 1 "const0_operand" "")))] | |
9602b6a1 | 988 | "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" |
08a5aaa2 AS |
989 | "srda\t%0,0" |
990 | [(set_attr "op_type" "RS") | |
991 | (set_attr "atype" "reg")]) | |
992 | ||
43a09b63 | 993 | ; ltr, ltgr |
08a5aaa2 | 994 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 995 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
996 | (compare (match_operand:GPR 0 "register_operand" "d") |
997 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 998 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 999 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
1000 | [(set_attr "op_type" "RR<E>") |
1001 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 1002 | |
c0220ea4 | 1003 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 1004 | |
f52c81dd | 1005 | (define_insn "*tst<mode>CCT" |
ae156f85 | 1006 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1007 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
1008 | (match_operand:HQI 1 "const0_operand" ""))) | |
1009 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
1010 | (match_dup 0))] |
1011 | "s390_match_ccmode(insn, CCTmode)" | |
1012 | "@ | |
f52c81dd AS |
1013 | icm\t%2,<icm_lo>,%S0 |
1014 | icmy\t%2,<icm_lo>,%S0 | |
1015 | tml\t%0,<max_uint>" | |
9381e3f1 | 1016 | [(set_attr "op_type" "RS,RSY,RI") |
3e4be43f | 1017 | (set_attr "cpu_facility" "*,longdisp,*") |
9381e3f1 | 1018 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) |
3af97654 UW |
1019 | |
1020 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 1021 | [(set (reg CC_REGNUM) |
d3632d41 | 1022 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 1023 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 1024 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
1025 | "s390_match_ccmode(insn, CCTmode)" |
1026 | "@ | |
fc0ea003 UW |
1027 | icm\t%2,3,%S0 |
1028 | icmy\t%2,3,%S0 | |
d40c829f | 1029 | tml\t%0,65535" |
9381e3f1 | 1030 | [(set_attr "op_type" "RS,RSY,RI") |
3e4be43f | 1031 | (set_attr "cpu_facility" "*,longdisp,*") |
9381e3f1 | 1032 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) |
3af97654 | 1033 | |
3af97654 | 1034 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 1035 | [(set (reg CC_REGNUM) |
d3632d41 | 1036 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
1037 | (match_operand:QI 1 "const0_operand" "")))] |
1038 | "s390_match_ccmode(insn, CCTmode)" | |
1039 | "@ | |
fc0ea003 UW |
1040 | cli\t%S0,0 |
1041 | cliy\t%S0,0 | |
d40c829f | 1042 | tml\t%0,255" |
9381e3f1 | 1043 | [(set_attr "op_type" "SI,SIY,RI") |
3e4be43f | 1044 | (set_attr "cpu_facility" "*,longdisp,*") |
729e750f | 1045 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 1046 | |
f52c81dd | 1047 | (define_insn "*tst<mode>" |
ae156f85 | 1048 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1049 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1050 | (match_operand:HQI 1 "const0_operand" ""))) | |
1051 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
1052 | (match_dup 0))] |
1053 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 1054 | "@ |
f52c81dd AS |
1055 | icm\t%2,<icm_lo>,%S0 |
1056 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 | 1057 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 1058 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1059 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 | 1060 | |
f52c81dd | 1061 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 1062 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1063 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1064 | (match_operand:HQI 1 "const0_operand" ""))) | |
1065 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 1066 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 1067 | "@ |
f52c81dd AS |
1068 | icm\t%2,<icm_lo>,%S0 |
1069 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 | 1070 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 1071 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1072 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
d3632d41 | 1073 | |
9db1d521 | 1074 | |
575f7c2b UW |
1075 | ; Compare (equality) instructions |
1076 | ||
1077 | (define_insn "*cmpdi_cct" | |
ae156f85 | 1078 | [(set (reg CC_REGNUM) |
ec24698e | 1079 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
3e4be43f | 1080 | (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))] |
9602b6a1 | 1081 | "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" |
575f7c2b UW |
1082 | "@ |
1083 | cgr\t%0,%1 | |
f4f41b4e | 1084 | cghi\t%0,%h1 |
ec24698e | 1085 | cgfi\t%0,%1 |
575f7c2b | 1086 | cg\t%0,%1 |
19b63d8e | 1087 | #" |
9381e3f1 WG |
1088 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
1089 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
1090 | |
1091 | (define_insn "*cmpsi_cct" | |
ae156f85 | 1092 | [(set (reg CC_REGNUM) |
ec24698e UW |
1093 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
1094 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 1095 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
1096 | "@ |
1097 | cr\t%0,%1 | |
f4f41b4e | 1098 | chi\t%0,%h1 |
ec24698e | 1099 | cfi\t%0,%1 |
575f7c2b UW |
1100 | c\t%0,%1 |
1101 | cy\t%0,%1 | |
19b63d8e | 1102 | #" |
9381e3f1 | 1103 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
3e4be43f | 1104 | (set_attr "cpu_facility" "*,*,*,*,longdisp,*") |
e3cba5e5 | 1105 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) |
575f7c2b | 1106 | |
07893d4f | 1107 | ; Compare (signed) instructions |
4023fb28 | 1108 | |
07893d4f | 1109 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 1110 | [(set (reg CC_REGNUM) |
963fc8d0 | 1111 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
3e4be43f | 1112 | "d,T,b")) |
963fc8d0 | 1113 | (match_operand:DI 0 "register_operand" "d, d,d")))] |
9602b6a1 | 1114 | "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" |
4023fb28 | 1115 | "@ |
d40c829f | 1116 | cgfr\t%0,%1 |
963fc8d0 AK |
1117 | cgf\t%0,%1 |
1118 | cgfrl\t%0,%1" | |
1119 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 1120 | (set_attr "z10prop" "z10_c,*,*") |
963fc8d0 | 1121 | (set_attr "type" "*,*,larl")]) |
4023fb28 | 1122 | |
9381e3f1 WG |
1123 | |
1124 | ||
07893d4f | 1125 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 1126 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1127 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
1128 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 1129 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 1130 | "@ |
d40c829f | 1131 | ch\t%0,%1 |
963fc8d0 AK |
1132 | chy\t%0,%1 |
1133 | chrl\t%0,%1" | |
1134 | [(set_attr "op_type" "RX,RXY,RIL") | |
3e4be43f | 1135 | (set_attr "cpu_facility" "*,longdisp,z10") |
65b1d8ea AK |
1136 | (set_attr "type" "*,*,larl") |
1137 | (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")]) | |
963fc8d0 AK |
1138 | |
1139 | (define_insn "*cmphi_ccs_z10" | |
1140 | [(set (reg CC_REGNUM) | |
1141 | (compare (match_operand:HI 0 "s_operand" "Q") | |
1142 | (match_operand:HI 1 "immediate_operand" "K")))] | |
1143 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
1144 | "chhsi\t%0,%1" | |
65b1d8ea AK |
1145 | [(set_attr "op_type" "SIL") |
1146 | (set_attr "z196prop" "z196_cracked")]) | |
963fc8d0 AK |
1147 | |
1148 | (define_insn "*cmpdi_ccs_signhi_rl" | |
1149 | [(set (reg CC_REGNUM) | |
3e4be43f | 1150 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b")) |
963fc8d0 AK |
1151 | (match_operand:GPR 0 "register_operand" "d,d")))] |
1152 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
1153 | "@ | |
1154 | cgh\t%0,%1 | |
1155 | cghrl\t%0,%1" | |
1156 | [(set_attr "op_type" "RXY,RIL") | |
1157 | (set_attr "type" "*,larl")]) | |
4023fb28 | 1158 | |
963fc8d0 | 1159 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 1160 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1161 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1162 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
1163 | "d,d,Q, d,d,d,d") | |
1164 | (match_operand:GPR 1 "general_operand" | |
1165 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 1166 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 1167 | "@ |
3298c037 AK |
1168 | c<g>r\t%0,%1 |
1169 | c<g>hi\t%0,%h1 | |
963fc8d0 | 1170 | c<g>hsi\t%0,%h1 |
3298c037 AK |
1171 | c<g>fi\t%0,%1 |
1172 | c<g>\t%0,%1 | |
963fc8d0 AK |
1173 | c<y>\t%0,%1 |
1174 | c<g>rl\t%0,%1" | |
1175 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
3e4be43f | 1176 | (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10") |
9381e3f1 WG |
1177 | (set_attr "type" "*,*,*,*,*,*,larl") |
1178 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) | |
c7453384 | 1179 | |
07893d4f UW |
1180 | |
1181 | ; Compare (unsigned) instructions | |
9db1d521 | 1182 | |
963fc8d0 AK |
1183 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
1184 | [(set (reg CC_REGNUM) | |
1185 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
1186 | "larl_operand" "X"))) | |
1187 | (match_operand:SI 0 "register_operand" "d")))] | |
1188 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1189 | "clhrl\t%0,%1" | |
1190 | [(set_attr "op_type" "RIL") | |
729e750f WG |
1191 | (set_attr "type" "larl") |
1192 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 AK |
1193 | |
1194 | ; clhrl, clghrl | |
1195 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
1196 | [(set (reg CC_REGNUM) | |
1197 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
1198 | "larl_operand" "X"))) | |
1199 | (match_operand:GPR 0 "register_operand" "d")))] | |
1200 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1201 | "cl<g>hrl\t%0,%1" | |
1202 | [(set_attr "op_type" "RIL") | |
9381e3f1 WG |
1203 | (set_attr "type" "larl") |
1204 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 | 1205 | |
07893d4f | 1206 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 1207 | [(set (reg CC_REGNUM) |
963fc8d0 | 1208 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
3e4be43f UW |
1209 | "d,T,b")) |
1210 | (match_operand:DI 0 "register_operand" "d,d,d")))] | |
9602b6a1 | 1211 | "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" |
07893d4f | 1212 | "@ |
d40c829f | 1213 | clgfr\t%0,%1 |
963fc8d0 AK |
1214 | clgf\t%0,%1 |
1215 | clgfrl\t%0,%1" | |
1216 | [(set_attr "op_type" "RRE,RXY,RIL") | |
1217 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 WG |
1218 | (set_attr "type" "*,*,larl") |
1219 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) | |
9db1d521 | 1220 | |
07893d4f | 1221 | (define_insn "*cmpdi_ccu" |
ae156f85 | 1222 | [(set (reg CC_REGNUM) |
963fc8d0 | 1223 | (compare (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1224 | "d, d,d,Q,d, Q,BQ") |
963fc8d0 | 1225 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1226 | "d,Op,b,D,T,BQ,Q")))] |
9602b6a1 | 1227 | "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" |
07893d4f | 1228 | "@ |
d40c829f | 1229 | clgr\t%0,%1 |
ec24698e | 1230 | clgfi\t%0,%1 |
963fc8d0 AK |
1231 | clgrl\t%0,%1 |
1232 | clghsi\t%0,%x1 | |
575f7c2b | 1233 | clg\t%0,%1 |
e221ef54 | 1234 | # |
19b63d8e | 1235 | #" |
963fc8d0 AK |
1236 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
1237 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 WG |
1238 | (set_attr "type" "*,*,larl,*,*,*,*") |
1239 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 1240 | |
07893d4f | 1241 | (define_insn "*cmpsi_ccu" |
ae156f85 | 1242 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1243 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
1244 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 1245 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 1246 | "@ |
d40c829f | 1247 | clr\t%0,%1 |
ec24698e | 1248 | clfi\t%0,%o1 |
963fc8d0 AK |
1249 | clrl\t%0,%1 |
1250 | clfhsi\t%0,%x1 | |
d40c829f | 1251 | cl\t%0,%1 |
575f7c2b | 1252 | cly\t%0,%1 |
e221ef54 | 1253 | # |
19b63d8e | 1254 | #" |
963fc8d0 | 1255 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
3e4be43f | 1256 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*") |
9381e3f1 WG |
1257 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
1258 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 1259 | |
07893d4f | 1260 | (define_insn "*cmphi_ccu" |
ae156f85 | 1261 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1262 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
1263 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 1264 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1265 | && !register_operand (operands[1], HImode)" |
d3632d41 | 1266 | "@ |
fc0ea003 UW |
1267 | clm\t%0,3,%S1 |
1268 | clmy\t%0,3,%S1 | |
963fc8d0 | 1269 | clhhsi\t%0,%1 |
e221ef54 | 1270 | # |
19b63d8e | 1271 | #" |
963fc8d0 | 1272 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
3e4be43f | 1273 | (set_attr "cpu_facility" "*,longdisp,z10,*,*") |
9381e3f1 | 1274 | (set_attr "z10prop" "*,*,z10_super,*,*")]) |
9db1d521 HP |
1275 | |
1276 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 1277 | [(set (reg CC_REGNUM) |
e221ef54 UW |
1278 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
1279 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 1280 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1281 | && !register_operand (operands[1], QImode)" |
d3632d41 | 1282 | "@ |
fc0ea003 UW |
1283 | clm\t%0,1,%S1 |
1284 | clmy\t%0,1,%S1 | |
1285 | cli\t%S0,%b1 | |
1286 | cliy\t%S0,%b1 | |
e221ef54 | 1287 | # |
19b63d8e | 1288 | #" |
9381e3f1 | 1289 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
3e4be43f | 1290 | (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*") |
9381e3f1 | 1291 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) |
9db1d521 HP |
1292 | |
1293 | ||
19b63d8e UW |
1294 | ; Block compare (CLC) instruction patterns. |
1295 | ||
1296 | (define_insn "*clc" | |
ae156f85 | 1297 | [(set (reg CC_REGNUM) |
d4f52f0e | 1298 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
1299 | (match_operand:BLK 1 "memory_operand" "Q"))) |
1300 | (use (match_operand 2 "const_int_operand" "n"))] | |
1301 | "s390_match_ccmode (insn, CCUmode) | |
1302 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1303 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 1304 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1305 | |
1306 | (define_split | |
ae156f85 | 1307 | [(set (reg CC_REGNUM) |
19b63d8e UW |
1308 | (compare (match_operand 0 "memory_operand" "") |
1309 | (match_operand 1 "memory_operand" "")))] | |
1310 | "reload_completed | |
1311 | && s390_match_ccmode (insn, CCUmode) | |
1312 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1313 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1314 | [(parallel | |
1315 | [(set (match_dup 0) (match_dup 1)) | |
1316 | (use (match_dup 2))])] | |
1317 | { | |
1318 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1319 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1320 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1321 | ||
1322 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
1323 | operands[0], operands[1]); | |
1324 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
1325 | }) | |
1326 | ||
1327 | ||
609e7e80 | 1328 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 1329 | |
e325aba2 AK |
1330 | |
1331 | ; load and test instructions turn SNaN into QNaN what is not | |
1332 | ; acceptable if the target will be used afterwards. On the other hand | |
1333 | ; they are quite convenient for implementing comparisons with 0.0. So | |
1334 | ; try to enable them via splitter if the value isn't needed anymore. | |
1335 | ||
609e7e80 | 1336 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 1337 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 1338 | [(set (reg CC_REGNUM) |
e325aba2 AK |
1339 | (compare (match_operand:FP 0 "register_operand" "f") |
1340 | (match_operand:FP 1 "const0_operand" ""))) | |
1341 | (clobber (match_operand:FP 2 "register_operand" "=0"))] | |
142cd70f | 1342 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 1343 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 1344 | [(set_attr "op_type" "RRE") |
9381e3f1 | 1345 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1346 | |
e325aba2 AK |
1347 | (define_split |
1348 | [(set (match_operand 0 "cc_reg_operand") | |
1349 | (compare (match_operand:FP 1 "register_operand") | |
1350 | (match_operand:FP 2 "const0_operand")))] | |
1351 | "TARGET_HARD_FLOAT && REG_P (operands[1]) && dead_or_set_p (insn, operands[1])" | |
1352 | [(parallel | |
1353 | [(set (match_dup 0) (match_dup 3)) | |
1354 | (clobber (match_dup 1))])] | |
1355 | { | |
1356 | /* s390_match_ccmode requires the compare to have the same CC mode | |
1357 | as the CC destination register. */ | |
1358 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[0]), | |
1359 | operands[1], operands[2]); | |
1360 | }) | |
1361 | ||
1362 | ||
2de2b3f9 AK |
1363 | ; VX: TFmode in FPR pairs: use cxbr instead of wfcxb |
1364 | ; cxtr, cdtr, cxbr, cdbr, cebr, cdb, ceb, wfcsb, wfcdb | |
f5905b37 | 1365 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1366 | [(set (reg CC_REGNUM) |
2de2b3f9 AK |
1367 | (compare (match_operand:FP 0 "register_operand" "f,f,v,v") |
1368 | (match_operand:FP 1 "general_operand" "f,R,v,v")))] | |
142cd70f | 1369 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 1370 | "@ |
609e7e80 | 1371 | c<xde><bt>r\t%0,%1 |
77c585ca | 1372 | c<xde>b\t%0,%1 |
2de2b3f9 AK |
1373 | wfcdb\t%0,%1 |
1374 | wfcsb\t%0,%1" | |
1375 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
1376 | (set_attr "cpu_facility" "*,*,vx,vxe") | |
1377 | (set_attr "enabled" "*,<DSF>,<DF>,<SF>")]) | |
963fc8d0 AK |
1378 | |
1379 | ; Compare and Branch instructions | |
1380 | ||
1381 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
1382 | ; The following instructions do a complementary access of their second |
1383 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
1384 | (define_insn "*cmp_and_br_signed_<mode>" |
1385 | [(set (pc) | |
1386 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1387 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1388 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1389 | (label_ref (match_operand 3 "" "")) | |
1390 | (pc))) | |
1391 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1392 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1393 | { |
1394 | if (get_attr_length (insn) == 6) | |
1395 | return which_alternative ? | |
1396 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1397 | else | |
1398 | return which_alternative ? | |
1399 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1400 | } | |
1401 | [(set_attr "op_type" "RIE") | |
1402 | (set_attr "type" "branch") | |
e3cba5e5 | 1403 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1404 | (set (attr "length") |
1405 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1406 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1407 | ; 10 byte for cgr/jg | |
1408 | ||
1409 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1410 | ; The following instructions do a complementary access of their second |
1411 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1412 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1413 | [(set (pc) | |
1414 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1415 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1416 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1417 | (label_ref (match_operand 3 "" "")) | |
1418 | (pc))) | |
1419 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1420 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1421 | { |
1422 | if (get_attr_length (insn) == 6) | |
1423 | return which_alternative ? | |
1424 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1425 | else | |
1426 | return which_alternative ? | |
1427 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1428 | } | |
1429 | [(set_attr "op_type" "RIE") | |
1430 | (set_attr "type" "branch") | |
e3cba5e5 | 1431 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1432 | (set (attr "length") |
1433 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1434 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1435 | ; 10 byte for clgr/jg | |
1436 | ||
b0f86a7e AK |
1437 | ; And now the same two patterns as above but with a negated CC mask. |
1438 | ||
1439 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1440 | ; The following instructions do a complementary access of their second | |
1441 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1442 | (define_insn "*icmp_and_br_signed_<mode>" | |
1443 | [(set (pc) | |
1444 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1445 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1446 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1447 | (pc) | |
1448 | (label_ref (match_operand 3 "" "")))) | |
1449 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1450 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1451 | { |
1452 | if (get_attr_length (insn) == 6) | |
1453 | return which_alternative ? | |
1454 | "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; | |
1455 | else | |
1456 | return which_alternative ? | |
1457 | "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; | |
1458 | } | |
1459 | [(set_attr "op_type" "RIE") | |
1460 | (set_attr "type" "branch") | |
1461 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1462 | (set (attr "length") | |
1463 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1464 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1465 | ; 10 byte for cgr/jg | |
1466 | ||
1467 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1468 | ; The following instructions do a complementary access of their second | |
1469 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
1470 | (define_insn "*icmp_and_br_unsigned_<mode>" | |
1471 | [(set (pc) | |
1472 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1473 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1474 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1475 | (pc) | |
1476 | (label_ref (match_operand 3 "" "")))) | |
1477 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1478 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1479 | { |
1480 | if (get_attr_length (insn) == 6) | |
1481 | return which_alternative ? | |
1482 | "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; | |
1483 | else | |
1484 | return which_alternative ? | |
1485 | "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; | |
1486 | } | |
1487 | [(set_attr "op_type" "RIE") | |
1488 | (set_attr "type" "branch") | |
1489 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1490 | (set (attr "length") | |
1491 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1492 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1493 | ; 10 byte for clgr/jg | |
1494 | ||
9db1d521 HP |
1495 | ;; |
1496 | ;;- Move instructions. | |
1497 | ;; | |
1498 | ||
1499 | ; | |
1500 | ; movti instruction pattern(s). | |
1501 | ; | |
1502 | ||
3cb9ee2f AK |
1503 | |
1504 | ; Separate out the register pair alternative since constraints (P) are | |
1505 | ; not able to deal with const_wide_int's. But predicates do. | |
1506 | (define_insn "*movti_bigconst" | |
1507 | [(set (match_operand:TI 0 "register_operand" "=d") | |
1508 | (match_operand:TI 1 "reload_const_wide_int_operand" ""))] | |
1509 | "TARGET_ZARCH" | |
1510 | "#") | |
1511 | ||
085261c8 AK |
1512 | ; FIXME: More constants are possible by enabling jxx, jyy constraints |
1513 | ; for TImode (use double-int for the calculations) | |
9db1d521 | 1514 | (define_insn "movti" |
3cb9ee2f AK |
1515 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R, d,o") |
1516 | (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,dT,d"))] | |
9602b6a1 | 1517 | "TARGET_ZARCH" |
4023fb28 | 1518 | "@ |
fc0ea003 UW |
1519 | lmg\t%0,%N0,%S1 |
1520 | stmg\t%1,%N1,%S0 | |
085261c8 AK |
1521 | vlr\t%v0,%v1 |
1522 | vzero\t%v0 | |
1523 | vone\t%v0 | |
1524 | vlvgp\t%v0,%1,%N1 | |
1525 | # | |
1526 | vl\t%v0,%1 | |
1527 | vst\t%v1,%0 | |
4023fb28 | 1528 | # |
19b63d8e | 1529 | #" |
085261c8 AK |
1530 | [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*") |
1531 | (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*") | |
285363a1 | 1532 | (set_attr "cpu_facility" "*,*,vx,vx,vx,vx,vx,vx,vx,*,*")]) |
4023fb28 UW |
1533 | |
1534 | (define_split | |
1535 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1536 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1537 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
1538 | && !s_operand (operands[0], TImode) |
1539 | && !s_operand (operands[1], TImode) | |
dc65c307 | 1540 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1541 | [(set (match_dup 2) (match_dup 4)) |
1542 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1543 | { |
dc65c307 UW |
1544 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1545 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1546 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1547 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1548 | }) | |
1549 | ||
1550 | (define_split | |
1551 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1552 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1553 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
1554 | && !s_operand (operands[0], TImode) |
1555 | && !s_operand (operands[1], TImode) | |
dc65c307 UW |
1556 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" |
1557 | [(set (match_dup 2) (match_dup 4)) | |
1558 | (set (match_dup 3) (match_dup 5))] | |
1559 | { | |
1560 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1561 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1562 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1563 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1564 | }) | |
4023fb28 | 1565 | |
085261c8 AK |
1566 | ; Use part of the TImode target reg to perform the address |
1567 | ; calculation. If the TImode value is supposed to be copied into a VR | |
1568 | ; this splitter is not necessary. | |
4023fb28 UW |
1569 | (define_split |
1570 | [(set (match_operand:TI 0 "register_operand" "") | |
1571 | (match_operand:TI 1 "memory_operand" ""))] | |
9602b6a1 | 1572 | "TARGET_ZARCH && reload_completed |
085261c8 | 1573 | && !VECTOR_REG_P (operands[0]) |
4023fb28 | 1574 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1575 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1576 | { |
1577 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
9602b6a1 | 1578 | addr = gen_lowpart (Pmode, addr); |
a41c6c53 UW |
1579 | s390_load_address (addr, XEXP (operands[1], 0)); |
1580 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1581 | }) |
1582 | ||
833cd70a | 1583 | |
085261c8 AK |
1584 | ; Split a VR -> GPR TImode move into 2 vector load GR from VR element. |
1585 | ; For the higher order bits we do simply a DImode move while the | |
1586 | ; second part is done via vec extract. Both will end up as vlgvg. | |
1587 | (define_split | |
1588 | [(set (match_operand:TI 0 "register_operand" "") | |
1589 | (match_operand:TI 1 "register_operand" ""))] | |
1590 | "TARGET_VX && reload_completed | |
1591 | && GENERAL_REG_P (operands[0]) | |
1592 | && VECTOR_REG_P (operands[1])" | |
1593 | [(set (match_dup 2) (match_dup 4)) | |
1594 | (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)] | |
1595 | UNSPEC_VEC_EXTRACT))] | |
1596 | { | |
1597 | operands[2] = operand_subword (operands[0], 0, 0, TImode); | |
1598 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1599 | operands[4] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
1600 | operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1])); | |
1601 | }) | |
1602 | ||
833cd70a AK |
1603 | ; |
1604 | ; Patterns used for secondary reloads | |
1605 | ; | |
1606 | ||
963fc8d0 AK |
1607 | ; z10 provides move instructions accepting larl memory operands. |
1608 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1609 | ; These patterns are also used for unaligned SI and DI accesses. | |
1610 | ||
085261c8 AK |
1611 | (define_expand "reload<ALL:mode><P:mode>_tomem_z10" |
1612 | [(parallel [(match_operand:ALL 0 "memory_operand" "") | |
1613 | (match_operand:ALL 1 "register_operand" "=d") | |
1614 | (match_operand:P 2 "register_operand" "=&a")])] | |
963fc8d0 AK |
1615 | "TARGET_Z10" |
1616 | { | |
1617 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1618 | DONE; | |
1619 | }) | |
1620 | ||
085261c8 AK |
1621 | (define_expand "reload<ALL:mode><P:mode>_toreg_z10" |
1622 | [(parallel [(match_operand:ALL 0 "register_operand" "=d") | |
1623 | (match_operand:ALL 1 "memory_operand" "") | |
1624 | (match_operand:P 2 "register_operand" "=a")])] | |
963fc8d0 AK |
1625 | "TARGET_Z10" |
1626 | { | |
1627 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1628 | DONE; | |
1629 | }) | |
1630 | ||
1631 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1632 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1633 | (match_operand:P 1 "larl_operand" "") | |
1634 | (match_operand:P 2 "register_operand" "=a")])] | |
1635 | "TARGET_Z10" | |
1636 | { | |
1637 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1638 | DONE; | |
1639 | }) | |
1640 | ||
833cd70a AK |
1641 | ; Handles loading a PLUS (load address) expression |
1642 | ||
1643 | (define_expand "reload<mode>_plus" | |
1644 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1645 | (match_operand:P 1 "s390_plus_operand" "") | |
1646 | (match_operand:P 2 "register_operand" "=&a")])] | |
1647 | "" | |
1648 | { | |
1649 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1650 | DONE; | |
1651 | }) | |
1652 | ||
085261c8 AK |
1653 | ; Not all the indirect memory access instructions support the full |
1654 | ; format (long disp + index + base). So whenever a move from/to such | |
1655 | ; an address is required and the instruction cannot deal with it we do | |
1656 | ; a load address into a scratch register first and use this as the new | |
1657 | ; base register. | |
1658 | ; This in particular is used for: | |
1659 | ; - non-offsetable memory accesses for multiword moves | |
1660 | ; - full vector reg moves with long displacements | |
833cd70a | 1661 | |
085261c8 | 1662 | (define_expand "reload<mode>_la_in" |
833cd70a AK |
1663 | [(parallel [(match_operand 0 "register_operand" "") |
1664 | (match_operand 1 "" "") | |
1665 | (match_operand:P 2 "register_operand" "=&a")])] | |
1666 | "" | |
1667 | { | |
1668 | gcc_assert (MEM_P (operands[1])); | |
1669 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1670 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1671 | emit_move_insn (operands[0], operands[1]); | |
1672 | DONE; | |
1673 | }) | |
1674 | ||
085261c8 | 1675 | (define_expand "reload<mode>_la_out" |
833cd70a AK |
1676 | [(parallel [(match_operand 0 "" "") |
1677 | (match_operand 1 "register_operand" "") | |
1678 | (match_operand:P 2 "register_operand" "=&a")])] | |
1679 | "" | |
dc65c307 | 1680 | { |
9c3c3dcc | 1681 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1682 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1683 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1684 | emit_move_insn (operands[0], operands[1]); | |
1685 | DONE; | |
1686 | }) | |
9db1d521 | 1687 | |
1f9e1fc6 AK |
1688 | (define_expand "reload<mode>_PIC_addr" |
1689 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1690 | (match_operand 1 "larl_operand" "") | |
1691 | (match_operand:P 2 "register_operand" "=a")])] | |
1692 | "" | |
1693 | { | |
0a2aaacc KG |
1694 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1695 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1696 | }) |
1697 | ||
9db1d521 HP |
1698 | ; |
1699 | ; movdi instruction pattern(s). | |
1700 | ; | |
1701 | ||
9db1d521 HP |
1702 | (define_expand "movdi" |
1703 | [(set (match_operand:DI 0 "general_operand" "") | |
1704 | (match_operand:DI 1 "general_operand" ""))] | |
1705 | "" | |
9db1d521 | 1706 | { |
fd3cd001 | 1707 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1708 | if (TARGET_64BIT |
1709 | && (SYMBOLIC_CONST (operands[1]) | |
1710 | || (GET_CODE (operands[1]) == PLUS | |
1711 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1712 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1713 | emit_symbolic_move (operands); |
10bbf137 | 1714 | }) |
9db1d521 | 1715 | |
4023fb28 UW |
1716 | (define_insn "*movdi_larl" |
1717 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1718 | (match_operand:DI 1 "larl_operand" "X"))] | |
1719 | "TARGET_64BIT | |
8e509cf9 | 1720 | && !FP_REG_P (operands[0])" |
d40c829f | 1721 | "larl\t%0,%1" |
4023fb28 | 1722 | [(set_attr "op_type" "RIL") |
9381e3f1 WG |
1723 | (set_attr "type" "larl") |
1724 | (set_attr "z10prop" "z10_super_A1")]) | |
4023fb28 | 1725 | |
3af8e996 | 1726 | (define_insn "*movdi_64" |
85dae55a | 1727 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1728 | "=d, d, d, d, d, d, d, d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R") |
85dae55a | 1729 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1730 | " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v"))] |
9602b6a1 | 1731 | "TARGET_ZARCH" |
85dae55a AK |
1732 | "@ |
1733 | lghi\t%0,%h1 | |
1734 | llihh\t%0,%i1 | |
1735 | llihl\t%0,%i1 | |
1736 | llilh\t%0,%i1 | |
1737 | llill\t%0,%i1 | |
1738 | lgfi\t%0,%1 | |
1739 | llihf\t%0,%k1 | |
1740 | llilf\t%0,%k1 | |
1741 | ldgr\t%0,%1 | |
1742 | lgdr\t%0,%1 | |
1743 | lay\t%0,%a1 | |
963fc8d0 | 1744 | lgrl\t%0,%1 |
85dae55a AK |
1745 | lgr\t%0,%1 |
1746 | lg\t%0,%1 | |
1747 | stg\t%1,%0 | |
1748 | ldr\t%0,%1 | |
1749 | ld\t%0,%1 | |
1750 | ldy\t%0,%1 | |
1751 | std\t%1,%0 | |
1752 | stdy\t%1,%0 | |
963fc8d0 AK |
1753 | stgrl\t%1,%0 |
1754 | mvghi\t%0,%1 | |
85dae55a AK |
1755 | # |
1756 | # | |
1757 | stam\t%1,%N1,%S0 | |
085261c8 AK |
1758 | lam\t%0,%N0,%S1 |
1759 | vleig\t%v0,%h1,0 | |
1760 | vlr\t%v0,%v1 | |
1761 | vlvgg\t%v0,%1,0 | |
1762 | vlgvg\t%0,%v1,0 | |
1763 | vleg\t%v0,%1,0 | |
1764 | vsteg\t%v1,%0,0" | |
963fc8d0 | 1765 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
085261c8 | 1766 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
963fc8d0 | 1767 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
085261c8 AK |
1768 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*, |
1769 | *,*,*,*,*,*,*") | |
3af8e996 | 1770 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1771 | z10,*,*,*,*,*,longdisp,*,longdisp, |
285363a1 | 1772 | z10,z10,*,*,*,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
1773 | (set_attr "z10prop" "z10_fwd_A1, |
1774 | z10_fwd_E1, | |
1775 | z10_fwd_E1, | |
1776 | z10_fwd_E1, | |
1777 | z10_fwd_E1, | |
1778 | z10_fwd_A1, | |
1779 | z10_fwd_E1, | |
1780 | z10_fwd_E1, | |
1781 | *, | |
1782 | *, | |
1783 | z10_fwd_A1, | |
1784 | z10_fwd_A3, | |
1785 | z10_fr_E1, | |
1786 | z10_fwd_A3, | |
1787 | z10_rec, | |
1788 | *, | |
1789 | *, | |
1790 | *, | |
1791 | *, | |
1792 | *, | |
1793 | z10_rec, | |
1794 | z10_super, | |
1795 | *, | |
1796 | *, | |
1797 | *, | |
085261c8 | 1798 | *,*,*,*,*,*,*") |
9381e3f1 | 1799 | ]) |
c5aa1d12 UW |
1800 | |
1801 | (define_split | |
1802 | [(set (match_operand:DI 0 "register_operand" "") | |
1803 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1804 | "TARGET_ZARCH && ACCESS_REG_P (operands[1])" |
c5aa1d12 UW |
1805 | [(set (match_dup 2) (match_dup 3)) |
1806 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1807 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1808 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1809 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1810 | ||
1811 | (define_split | |
1812 | [(set (match_operand:DI 0 "register_operand" "") | |
1813 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1814 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1815 | && dead_or_set_p (insn, operands[1])" |
1816 | [(set (match_dup 3) (match_dup 2)) | |
1817 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1818 | (set (match_dup 4) (match_dup 2))] | |
1819 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1820 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1821 | ||
1822 | (define_split | |
1823 | [(set (match_operand:DI 0 "register_operand" "") | |
1824 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1825 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1826 | && !dead_or_set_p (insn, operands[1])" |
1827 | [(set (match_dup 3) (match_dup 2)) | |
1828 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1829 | (set (match_dup 4) (match_dup 2)) | |
1830 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1831 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1832 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1833 | |
1834 | (define_insn "*movdi_31" | |
963fc8d0 | 1835 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1836 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1837 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1838 | " Q,S,d,d,dPT,d, *f, R, T,*f,*f,b"))] |
9602b6a1 | 1839 | "!TARGET_ZARCH" |
4023fb28 | 1840 | "@ |
fc0ea003 | 1841 | lm\t%0,%N0,%S1 |
c4d50129 | 1842 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1843 | stm\t%1,%N1,%S0 |
c4d50129 | 1844 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1845 | # |
1846 | # | |
d40c829f UW |
1847 | ldr\t%0,%1 |
1848 | ld\t%0,%1 | |
1849 | ldy\t%0,%1 | |
1850 | std\t%1,%0 | |
1851 | stdy\t%1,%0 | |
19b63d8e | 1852 | #" |
f2dc2f86 AK |
1853 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1854 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
3e4be43f | 1855 | (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")]) |
963fc8d0 AK |
1856 | |
1857 | ; For a load from a symbol ref we can use one of the target registers | |
1858 | ; together with larl to load the address. | |
1859 | (define_split | |
1860 | [(set (match_operand:DI 0 "register_operand" "") | |
1861 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1862 | "!TARGET_ZARCH && reload_completed && TARGET_Z10 |
963fc8d0 AK |
1863 | && larl_operand (XEXP (operands[1], 0), SImode)" |
1864 | [(set (match_dup 2) (match_dup 3)) | |
1865 | (set (match_dup 0) (match_dup 1))] | |
1866 | { | |
1867 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1868 | operands[3] = XEXP (operands[1], 0); | |
1869 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1870 | }) | |
4023fb28 UW |
1871 | |
1872 | (define_split | |
1873 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1874 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1875 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
1876 | && !s_operand (operands[0], DImode) |
1877 | && !s_operand (operands[1], DImode) | |
dc65c307 | 1878 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1879 | [(set (match_dup 2) (match_dup 4)) |
1880 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1881 | { |
dc65c307 UW |
1882 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1883 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1884 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1885 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1886 | }) | |
1887 | ||
1888 | (define_split | |
1889 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1890 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1891 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
1892 | && !s_operand (operands[0], DImode) |
1893 | && !s_operand (operands[1], DImode) | |
dc65c307 UW |
1894 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" |
1895 | [(set (match_dup 2) (match_dup 4)) | |
1896 | (set (match_dup 3) (match_dup 5))] | |
1897 | { | |
1898 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1899 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1900 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1901 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1902 | }) | |
9db1d521 | 1903 | |
4023fb28 UW |
1904 | (define_split |
1905 | [(set (match_operand:DI 0 "register_operand" "") | |
1906 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1907 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 1908 | && !FP_REG_P (operands[0]) |
4023fb28 | 1909 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1910 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1911 | { |
1912 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1913 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1914 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1915 | }) |
1916 | ||
84817c5d UW |
1917 | (define_peephole2 |
1918 | [(set (match_operand:DI 0 "register_operand" "") | |
1919 | (mem:DI (match_operand 1 "address_operand" "")))] | |
9602b6a1 | 1920 | "TARGET_ZARCH |
84817c5d UW |
1921 | && !FP_REG_P (operands[0]) |
1922 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1923 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1924 | && get_pool_mode (operands[1]) == DImode | |
1925 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1926 | [(set (match_dup 0) (match_dup 2))] | |
1927 | "operands[2] = get_pool_constant (operands[1]);") | |
1928 | ||
7bdff56f UW |
1929 | (define_insn "*la_64" |
1930 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 1931 | (match_operand:QI 1 "address_operand" "ZR,ZT"))] |
7bdff56f UW |
1932 | "TARGET_64BIT" |
1933 | "@ | |
1934 | la\t%0,%a1 | |
1935 | lay\t%0,%a1" | |
1936 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 1937 | (set_attr "type" "la") |
3e4be43f | 1938 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1939 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
1940 | |
1941 | (define_peephole2 | |
1942 | [(parallel | |
1943 | [(set (match_operand:DI 0 "register_operand" "") | |
1944 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1945 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1946 | "TARGET_64BIT |
e1d5ee28 | 1947 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1948 | [(set (match_dup 0) (match_dup 1))] |
1949 | "") | |
1950 | ||
1951 | (define_peephole2 | |
1952 | [(set (match_operand:DI 0 "register_operand" "") | |
1953 | (match_operand:DI 1 "register_operand" "")) | |
1954 | (parallel | |
1955 | [(set (match_dup 0) | |
1956 | (plus:DI (match_dup 0) | |
1957 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1958 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1959 | "TARGET_64BIT |
1960 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1961 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1962 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1963 | "") | |
1964 | ||
9db1d521 HP |
1965 | ; |
1966 | ; movsi instruction pattern(s). | |
1967 | ; | |
1968 | ||
9db1d521 HP |
1969 | (define_expand "movsi" |
1970 | [(set (match_operand:SI 0 "general_operand" "") | |
1971 | (match_operand:SI 1 "general_operand" ""))] | |
1972 | "" | |
9db1d521 | 1973 | { |
fd3cd001 | 1974 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1975 | if (!TARGET_64BIT |
1976 | && (SYMBOLIC_CONST (operands[1]) | |
1977 | || (GET_CODE (operands[1]) == PLUS | |
1978 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1979 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 1980 | emit_symbolic_move (operands); |
10bbf137 | 1981 | }) |
9db1d521 | 1982 | |
9e8327e3 UW |
1983 | (define_insn "*movsi_larl" |
1984 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1985 | (match_operand:SI 1 "larl_operand" "X"))] | |
8cc6307c | 1986 | "!TARGET_64BIT |
9e8327e3 UW |
1987 | && !FP_REG_P (operands[0])" |
1988 | "larl\t%0,%1" | |
1989 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1990 | (set_attr "type" "larl") |
729e750f | 1991 | (set_attr "z10prop" "z10_fwd_A1")]) |
9e8327e3 | 1992 | |
f19a9af7 | 1993 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1994 | [(set (match_operand:SI 0 "nonimmediate_operand" |
3e4be43f | 1995 | "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R") |
2f7e5a0d | 1996 | (match_operand:SI 1 "general_operand" |
3e4be43f | 1997 | " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))] |
f19a9af7 | 1998 | "TARGET_ZARCH" |
9db1d521 | 1999 | "@ |
f19a9af7 AK |
2000 | lhi\t%0,%h1 |
2001 | llilh\t%0,%i1 | |
2002 | llill\t%0,%i1 | |
ec24698e | 2003 | iilf\t%0,%o1 |
f19a9af7 | 2004 | lay\t%0,%a1 |
963fc8d0 | 2005 | lrl\t%0,%1 |
d40c829f UW |
2006 | lr\t%0,%1 |
2007 | l\t%0,%1 | |
2008 | ly\t%0,%1 | |
2009 | st\t%1,%0 | |
2010 | sty\t%1,%0 | |
ae1c6198 | 2011 | ldr\t%0,%1 |
d40c829f | 2012 | ler\t%0,%1 |
085261c8 | 2013 | lde\t%0,%1 |
d40c829f UW |
2014 | le\t%0,%1 |
2015 | ley\t%0,%1 | |
2016 | ste\t%1,%0 | |
2017 | stey\t%1,%0 | |
c5aa1d12 UW |
2018 | ear\t%0,%1 |
2019 | sar\t%0,%1 | |
2020 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
2021 | strl\t%1,%0 |
2022 | mvhi\t%0,%1 | |
085261c8 AK |
2023 | lam\t%0,%0,%S1 |
2024 | vleif\t%v0,%h1,0 | |
2025 | vlr\t%v0,%v1 | |
2026 | vlvgf\t%v0,%1,0 | |
2027 | vlgvf\t%0,%v1,0 | |
2028 | vlef\t%v0,%1,0 | |
2029 | vstef\t%v1,%0,0" | |
963fc8d0 | 2030 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
ae1c6198 | 2031 | RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
9381e3f1 WG |
2032 | (set_attr "type" "*, |
2033 | *, | |
2034 | *, | |
2035 | *, | |
2036 | la, | |
2037 | larl, | |
2038 | lr, | |
2039 | load, | |
2040 | load, | |
2041 | store, | |
2042 | store, | |
2043 | floadsf, | |
2044 | floadsf, | |
2045 | floadsf, | |
085261c8 AK |
2046 | floadsf, |
2047 | floadsf, | |
9381e3f1 WG |
2048 | fstoresf, |
2049 | fstoresf, | |
2050 | *, | |
2051 | *, | |
2052 | *, | |
2053 | larl, | |
2054 | *, | |
085261c8 | 2055 | *,*,*,*,*,*,*") |
963fc8d0 | 2056 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
285363a1 | 2057 | vx,*,vx,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2058 | (set_attr "z10prop" "z10_fwd_A1, |
2059 | z10_fwd_E1, | |
2060 | z10_fwd_E1, | |
2061 | z10_fwd_A1, | |
2062 | z10_fwd_A1, | |
2063 | z10_fwd_A3, | |
2064 | z10_fr_E1, | |
2065 | z10_fwd_A3, | |
2066 | z10_fwd_A3, | |
729e750f | 2067 | z10_rec, |
9381e3f1 WG |
2068 | z10_rec, |
2069 | *, | |
2070 | *, | |
2071 | *, | |
2072 | *, | |
2073 | *, | |
085261c8 AK |
2074 | *, |
2075 | *, | |
9381e3f1 WG |
2076 | z10_super_E1, |
2077 | z10_super, | |
2078 | *, | |
2079 | z10_rec, | |
2080 | z10_super, | |
085261c8 | 2081 | *,*,*,*,*,*,*")]) |
f19a9af7 AK |
2082 | |
2083 | (define_insn "*movsi_esa" | |
085261c8 AK |
2084 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t") |
2085 | (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
2086 | "!TARGET_ZARCH" |
2087 | "@ | |
2088 | lhi\t%0,%h1 | |
2089 | lr\t%0,%1 | |
2090 | l\t%0,%1 | |
2091 | st\t%1,%0 | |
ae1c6198 | 2092 | ldr\t%0,%1 |
f19a9af7 | 2093 | ler\t%0,%1 |
085261c8 | 2094 | lde\t%0,%1 |
f19a9af7 AK |
2095 | le\t%0,%1 |
2096 | ste\t%1,%0 | |
c5aa1d12 UW |
2097 | ear\t%0,%1 |
2098 | sar\t%0,%1 | |
2099 | stam\t%1,%1,%S0 | |
f2dc2f86 | 2100 | lam\t%0,%0,%S1" |
ae1c6198 | 2101 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS") |
085261c8 AK |
2102 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*") |
2103 | (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1, | |
2104 | z10_super,*,*") | |
285363a1 | 2105 | (set_attr "cpu_facility" "*,*,*,*,vx,*,vx,*,*,*,*,*,*") |
9381e3f1 | 2106 | ]) |
9db1d521 | 2107 | |
84817c5d UW |
2108 | (define_peephole2 |
2109 | [(set (match_operand:SI 0 "register_operand" "") | |
2110 | (mem:SI (match_operand 1 "address_operand" "")))] | |
2111 | "!FP_REG_P (operands[0]) | |
2112 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2113 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2114 | && get_pool_mode (operands[1]) == SImode | |
2115 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
2116 | [(set (match_dup 0) (match_dup 2))] | |
2117 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 2118 | |
7bdff56f UW |
2119 | (define_insn "*la_31" |
2120 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2121 | (match_operand:QI 1 "address_operand" "ZR,ZT"))] |
7bdff56f UW |
2122 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
2123 | "@ | |
2124 | la\t%0,%a1 | |
2125 | lay\t%0,%a1" | |
2126 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2127 | (set_attr "type" "la") |
3e4be43f | 2128 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2129 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2130 | |
2131 | (define_peephole2 | |
2132 | [(parallel | |
2133 | [(set (match_operand:SI 0 "register_operand" "") | |
2134 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 2135 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 2136 | "!TARGET_64BIT |
e1d5ee28 | 2137 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
2138 | [(set (match_dup 0) (match_dup 1))] |
2139 | "") | |
2140 | ||
2141 | (define_peephole2 | |
2142 | [(set (match_operand:SI 0 "register_operand" "") | |
2143 | (match_operand:SI 1 "register_operand" "")) | |
2144 | (parallel | |
2145 | [(set (match_dup 0) | |
2146 | (plus:SI (match_dup 0) | |
2147 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 2148 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
2149 | "!TARGET_64BIT |
2150 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 2151 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
2152 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
2153 | "") | |
2154 | ||
2155 | (define_insn "*la_31_and" | |
2156 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2157 | (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT") |
7bdff56f UW |
2158 | (const_int 2147483647)))] |
2159 | "!TARGET_64BIT" | |
2160 | "@ | |
2161 | la\t%0,%a1 | |
2162 | lay\t%0,%a1" | |
2163 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2164 | (set_attr "type" "la") |
3e4be43f | 2165 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2166 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2167 | |
2168 | (define_insn_and_split "*la_31_and_cc" | |
2169 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2170 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
2171 | (const_int 2147483647))) | |
ae156f85 | 2172 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
2173 | "!TARGET_64BIT" |
2174 | "#" | |
2175 | "&& reload_completed" | |
2176 | [(set (match_dup 0) | |
2177 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
2178 | "" | |
2179 | [(set_attr "op_type" "RX") | |
2180 | (set_attr "type" "la")]) | |
2181 | ||
2182 | (define_insn "force_la_31" | |
2183 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2184 | (match_operand:QI 1 "address_operand" "ZR,ZT")) |
7bdff56f UW |
2185 | (use (const_int 0))] |
2186 | "!TARGET_64BIT" | |
2187 | "@ | |
2188 | la\t%0,%a1 | |
2189 | lay\t%0,%a1" | |
2190 | [(set_attr "op_type" "RX") | |
9381e3f1 | 2191 | (set_attr "type" "la") |
3e4be43f | 2192 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2193 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f | 2194 | |
9db1d521 HP |
2195 | ; |
2196 | ; movhi instruction pattern(s). | |
2197 | ; | |
2198 | ||
02ed3c5e UW |
2199 | (define_expand "movhi" |
2200 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
2201 | (match_operand:HI 1 "general_operand" ""))] | |
2202 | "" | |
2203 | { | |
2f7e5a0d | 2204 | /* Make it explicit that loading a register from memory |
02ed3c5e | 2205 | always sign-extends (at least) to SImode. */ |
b3a13419 | 2206 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 2207 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2208 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
2209 | { |
2210 | rtx tmp = gen_reg_rtx (SImode); | |
2211 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
f7df4a84 | 2212 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2213 | operands[1] = gen_lowpart (HImode, tmp); |
2214 | } | |
2215 | }) | |
2216 | ||
2217 | (define_insn "*movhi" | |
3e4be43f UW |
2218 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R") |
2219 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))] | |
9db1d521 HP |
2220 | "" |
2221 | "@ | |
d40c829f UW |
2222 | lr\t%0,%1 |
2223 | lhi\t%0,%h1 | |
2224 | lh\t%0,%1 | |
2225 | lhy\t%0,%1 | |
963fc8d0 | 2226 | lhrl\t%0,%1 |
d40c829f UW |
2227 | sth\t%1,%0 |
2228 | sthy\t%1,%0 | |
963fc8d0 | 2229 | sthrl\t%1,%0 |
085261c8 AK |
2230 | mvhhi\t%0,%1 |
2231 | vleih\t%v0,%h1,0 | |
2232 | vlr\t%v0,%v1 | |
2233 | vlvgh\t%v0,%1,0 | |
2234 | vlgvh\t%0,%v1,0 | |
2235 | vleh\t%v0,%1,0 | |
2236 | vsteh\t%v1,%0,0" | |
2237 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX") | |
2238 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*") | |
285363a1 | 2239 | (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2240 | (set_attr "z10prop" "z10_fr_E1, |
2241 | z10_fwd_A1, | |
2242 | z10_super_E1, | |
2243 | z10_super_E1, | |
2244 | z10_super_E1, | |
729e750f | 2245 | z10_rec, |
9381e3f1 WG |
2246 | z10_rec, |
2247 | z10_rec, | |
085261c8 | 2248 | z10_super,*,*,*,*,*,*")]) |
9db1d521 | 2249 | |
84817c5d UW |
2250 | (define_peephole2 |
2251 | [(set (match_operand:HI 0 "register_operand" "") | |
2252 | (mem:HI (match_operand 1 "address_operand" "")))] | |
2253 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2254 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2255 | && get_pool_mode (operands[1]) == HImode | |
2256 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2257 | [(set (match_dup 0) (match_dup 2))] | |
2258 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2259 | |
9db1d521 HP |
2260 | ; |
2261 | ; movqi instruction pattern(s). | |
2262 | ; | |
2263 | ||
02ed3c5e UW |
2264 | (define_expand "movqi" |
2265 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2266 | (match_operand:QI 1 "general_operand" ""))] | |
2267 | "" | |
2268 | { | |
c19ec8f9 | 2269 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 2270 | is just as fast as a QImode load. */ |
b3a13419 | 2271 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 2272 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2273 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 2274 | { |
9602b6a1 AK |
2275 | rtx tmp = gen_reg_rtx (DImode); |
2276 | rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
f7df4a84 | 2277 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2278 | operands[1] = gen_lowpart (QImode, tmp); |
2279 | } | |
2280 | }) | |
4023fb28 | 2281 | |
02ed3c5e | 2282 | (define_insn "*movqi" |
3e4be43f UW |
2283 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R") |
2284 | (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))] | |
9db1d521 HP |
2285 | "" |
2286 | "@ | |
d40c829f UW |
2287 | lr\t%0,%1 |
2288 | lhi\t%0,%b1 | |
2289 | ic\t%0,%1 | |
2290 | icy\t%0,%1 | |
2291 | stc\t%1,%0 | |
2292 | stcy\t%1,%0 | |
fc0ea003 | 2293 | mvi\t%S0,%b1 |
0a88561f | 2294 | mviy\t%S0,%b1 |
085261c8 AK |
2295 | # |
2296 | vleib\t%v0,%b1,0 | |
2297 | vlr\t%v0,%v1 | |
2298 | vlvgb\t%v0,%1,0 | |
2299 | vlgvb\t%0,%v1,0 | |
2300 | vleb\t%v0,%1,0 | |
2301 | vsteb\t%v1,%0,0" | |
2302 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX") | |
2303 | (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*") | |
285363a1 | 2304 | (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2305 | (set_attr "z10prop" "z10_fr_E1, |
2306 | z10_fwd_A1, | |
2307 | z10_super_E1, | |
2308 | z10_super_E1, | |
729e750f | 2309 | z10_rec, |
9381e3f1 WG |
2310 | z10_rec, |
2311 | z10_super, | |
0a88561f | 2312 | z10_super, |
085261c8 | 2313 | *,*,*,*,*,*,*")]) |
9db1d521 | 2314 | |
84817c5d UW |
2315 | (define_peephole2 |
2316 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2317 | (mem:QI (match_operand 1 "address_operand" "")))] | |
2318 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2319 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2320 | && get_pool_mode (operands[1]) == QImode | |
2321 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2322 | [(set (match_dup 0) (match_dup 2))] | |
2323 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2324 | |
9db1d521 | 2325 | ; |
05b9aaaa | 2326 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
2327 | ; |
2328 | ||
2329 | (define_insn "*movstrictqi" | |
d3632d41 UW |
2330 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
2331 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 2332 | "" |
d3632d41 | 2333 | "@ |
d40c829f UW |
2334 | ic\t%0,%1 |
2335 | icy\t%0,%1" | |
9381e3f1 | 2336 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 2337 | (set_attr "cpu_facility" "*,longdisp") |
729e750f | 2338 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2339 | |
2340 | ; | |
2341 | ; movstricthi instruction pattern(s). | |
2342 | ; | |
2343 | ||
2344 | (define_insn "*movstricthi" | |
d3632d41 | 2345 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 2346 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 2347 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2348 | "" |
d3632d41 | 2349 | "@ |
fc0ea003 UW |
2350 | icm\t%0,3,%S1 |
2351 | icmy\t%0,3,%S1" | |
9381e3f1 | 2352 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2353 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2354 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2355 | |
2356 | ; | |
2357 | ; movstrictsi instruction pattern(s). | |
2358 | ; | |
2359 | ||
05b9aaaa | 2360 | (define_insn "movstrictsi" |
c5aa1d12 UW |
2361 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
2362 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9602b6a1 | 2363 | "TARGET_ZARCH" |
9db1d521 | 2364 | "@ |
d40c829f UW |
2365 | lr\t%0,%1 |
2366 | l\t%0,%1 | |
c5aa1d12 UW |
2367 | ly\t%0,%1 |
2368 | ear\t%0,%1" | |
2369 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 | 2370 | (set_attr "type" "lr,load,load,*") |
3e4be43f | 2371 | (set_attr "cpu_facility" "*,*,longdisp,*") |
9381e3f1 | 2372 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) |
9db1d521 | 2373 | |
f61a2c7d | 2374 | ; |
609e7e80 | 2375 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
2376 | ; |
2377 | ||
609e7e80 AK |
2378 | (define_expand "mov<mode>" |
2379 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
2380 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
2381 | "" |
2382 | "") | |
2383 | ||
609e7e80 | 2384 | (define_insn "*mov<mode>_64" |
3e4be43f UW |
2385 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o") |
2386 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))] | |
9602b6a1 | 2387 | "TARGET_ZARCH" |
f61a2c7d | 2388 | "@ |
65b1d8ea | 2389 | lzxr\t%0 |
f61a2c7d AK |
2390 | lxr\t%0,%1 |
2391 | # | |
2392 | # | |
2393 | lmg\t%0,%N0,%S1 | |
2394 | stmg\t%1,%N1,%S0 | |
2395 | # | |
f61a2c7d | 2396 | #" |
65b1d8ea AK |
2397 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
2398 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") | |
2399 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) | |
f61a2c7d | 2400 | |
609e7e80 | 2401 | (define_insn "*mov<mode>_31" |
65b1d8ea AK |
2402 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
2403 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
9602b6a1 | 2404 | "!TARGET_ZARCH" |
f61a2c7d | 2405 | "@ |
65b1d8ea | 2406 | lzxr\t%0 |
f61a2c7d AK |
2407 | lxr\t%0,%1 |
2408 | # | |
f61a2c7d | 2409 | #" |
65b1d8ea AK |
2410 | [(set_attr "op_type" "RRE,RRE,*,*") |
2411 | (set_attr "type" "fsimptf,fsimptf,*,*") | |
2412 | (set_attr "cpu_facility" "z196,*,*,*")]) | |
f61a2c7d AK |
2413 | |
2414 | ; TFmode in GPRs splitters | |
2415 | ||
2416 | (define_split | |
609e7e80 AK |
2417 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2418 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2419 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
2420 | && !s_operand (operands[0], <MODE>mode) |
2421 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2422 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
2423 | [(set (match_dup 2) (match_dup 4)) |
2424 | (set (match_dup 3) (match_dup 5))] | |
2425 | { | |
609e7e80 AK |
2426 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2427 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2428 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2429 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
2430 | }) |
2431 | ||
2432 | (define_split | |
609e7e80 AK |
2433 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2434 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2435 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
2436 | && !s_operand (operands[0], <MODE>mode) |
2437 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2438 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
2439 | [(set (match_dup 2) (match_dup 4)) |
2440 | (set (match_dup 3) (match_dup 5))] | |
2441 | { | |
609e7e80 AK |
2442 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2443 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2444 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2445 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
2446 | }) |
2447 | ||
2448 | (define_split | |
609e7e80 AK |
2449 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2450 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9602b6a1 | 2451 | "TARGET_ZARCH && reload_completed |
085261c8 | 2452 | && GENERAL_REG_P (operands[0]) |
f61a2c7d AK |
2453 | && !s_operand (operands[1], VOIDmode)" |
2454 | [(set (match_dup 0) (match_dup 1))] | |
2455 | { | |
609e7e80 | 2456 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a9e6994a | 2457 | addr = gen_lowpart (Pmode, addr); |
f61a2c7d AK |
2458 | s390_load_address (addr, XEXP (operands[1], 0)); |
2459 | operands[1] = replace_equiv_address (operands[1], addr); | |
2460 | }) | |
2461 | ||
7b6baae1 | 2462 | ; TFmode in BFPs splitters |
f61a2c7d AK |
2463 | |
2464 | (define_split | |
609e7e80 AK |
2465 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2466 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 2467 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
2468 | && FP_REG_P (operands[0])" |
2469 | [(set (match_dup 2) (match_dup 4)) | |
2470 | (set (match_dup 3) (match_dup 5))] | |
2471 | { | |
609e7e80 AK |
2472 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
2473 | <MODE>mode, 0); | |
2474 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
2475 | <MODE>mode, 8); | |
2476 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
2477 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
2478 | }) |
2479 | ||
2480 | (define_split | |
609e7e80 AK |
2481 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
2482 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
2483 | "reload_completed && offsettable_memref_p (operands[0]) |
2484 | && FP_REG_P (operands[1])" | |
2485 | [(set (match_dup 2) (match_dup 4)) | |
2486 | (set (match_dup 3) (match_dup 5))] | |
2487 | { | |
609e7e80 AK |
2488 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
2489 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
2490 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2491 | <MODE>mode, 0); | |
2492 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2493 | <MODE>mode, 8); | |
f61a2c7d AK |
2494 | }) |
2495 | ||
9db1d521 | 2496 | ; |
609e7e80 | 2497 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
2498 | ; |
2499 | ||
609e7e80 AK |
2500 | (define_expand "mov<mode>" |
2501 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2502 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 2503 | "" |
13c025c1 | 2504 | "") |
9db1d521 | 2505 | |
609e7e80 AK |
2506 | (define_insn "*mov<mode>_64dfp" |
2507 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
590961cf | 2508 | "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,v,d,v,R") |
609e7e80 | 2509 | (match_operand:DD_DF 1 "general_operand" |
590961cf | 2510 | " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,G,d,v,R,v"))] |
9602b6a1 | 2511 | "TARGET_DFP" |
85dae55a | 2512 | "@ |
65b1d8ea | 2513 | lzdr\t%0 |
85dae55a AK |
2514 | ldr\t%0,%1 |
2515 | ldgr\t%0,%1 | |
2516 | lgdr\t%0,%1 | |
2517 | ld\t%0,%1 | |
2518 | ldy\t%0,%1 | |
2519 | std\t%1,%0 | |
2520 | stdy\t%1,%0 | |
45e5214c | 2521 | lghi\t%0,0 |
85dae55a | 2522 | lgr\t%0,%1 |
085261c8 | 2523 | lgrl\t%0,%1 |
85dae55a | 2524 | lg\t%0,%1 |
085261c8 AK |
2525 | stgrl\t%1,%0 |
2526 | stg\t%1,%0 | |
2527 | vlr\t%v0,%v1 | |
590961cf | 2528 | vleig\t%v0,0,0 |
085261c8 AK |
2529 | vlvgg\t%v0,%1,0 |
2530 | vlgvg\t%0,%v1,0 | |
2531 | vleg\t%0,%1,0 | |
2532 | vsteg\t%1,%0,0" | |
590961cf | 2533 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRI,VRS,VRS,VRX,VRX") |
65b1d8ea | 2534 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, |
590961cf AK |
2535 | fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,*,load,store") |
2536 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*,*") | |
2537 | (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx,vx")]) | |
85dae55a | 2538 | |
609e7e80 | 2539 | (define_insn "*mov<mode>_64" |
590961cf AK |
2540 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T") |
2541 | (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d"))] | |
9602b6a1 | 2542 | "TARGET_ZARCH" |
9db1d521 | 2543 | "@ |
65b1d8ea | 2544 | lzdr\t%0 |
d40c829f UW |
2545 | ldr\t%0,%1 |
2546 | ld\t%0,%1 | |
2547 | ldy\t%0,%1 | |
2548 | std\t%1,%0 | |
2549 | stdy\t%1,%0 | |
45e5214c | 2550 | lghi\t%0,0 |
d40c829f | 2551 | lgr\t%0,%1 |
085261c8 | 2552 | lgrl\t%0,%1 |
d40c829f | 2553 | lg\t%0,%1 |
085261c8 | 2554 | stgrl\t%1,%0 |
590961cf AK |
2555 | stg\t%1,%0" |
2556 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY") | |
65b1d8ea | 2557 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, |
590961cf AK |
2558 | fstore<mode>,fstore<mode>,*,lr,load,load,store,store") |
2559 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") | |
2560 | (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*")]) | |
609e7e80 AK |
2561 | |
2562 | (define_insn "*mov<mode>_31" | |
2563 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
3e4be43f | 2564 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2565 | (match_operand:DD_DF 1 "general_operand" |
3e4be43f | 2566 | " G,f,R,T,f,f,Q,S,d,d,dPT,d"))] |
9602b6a1 | 2567 | "!TARGET_ZARCH" |
9db1d521 | 2568 | "@ |
65b1d8ea | 2569 | lzdr\t%0 |
d40c829f UW |
2570 | ldr\t%0,%1 |
2571 | ld\t%0,%1 | |
2572 | ldy\t%0,%1 | |
2573 | std\t%1,%0 | |
2574 | stdy\t%1,%0 | |
fc0ea003 | 2575 | lm\t%0,%N0,%S1 |
c4d50129 | 2576 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2577 | stm\t%1,%N1,%S0 |
c4d50129 | 2578 | stmy\t%1,%N1,%S0 |
4023fb28 | 2579 | # |
19b63d8e | 2580 | #" |
65b1d8ea AK |
2581 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
2582 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2583 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") | |
3e4be43f | 2584 | (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")]) |
4023fb28 UW |
2585 | |
2586 | (define_split | |
609e7e80 AK |
2587 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2588 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2589 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
2590 | && !s_operand (operands[0], <MODE>mode) |
2591 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2592 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2593 | [(set (match_dup 2) (match_dup 4)) |
2594 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2595 | { |
609e7e80 AK |
2596 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2597 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2598 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2599 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2600 | }) |
2601 | ||
2602 | (define_split | |
609e7e80 AK |
2603 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2604 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2605 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
2606 | && !s_operand (operands[0], <MODE>mode) |
2607 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2608 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2609 | [(set (match_dup 2) (match_dup 4)) |
2610 | (set (match_dup 3) (match_dup 5))] | |
2611 | { | |
609e7e80 AK |
2612 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2613 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2614 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2615 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2616 | }) |
9db1d521 | 2617 | |
4023fb28 | 2618 | (define_split |
609e7e80 AK |
2619 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2620 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
9602b6a1 | 2621 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 2622 | && !FP_REG_P (operands[0]) |
4023fb28 | 2623 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2624 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2625 | { |
609e7e80 | 2626 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2627 | s390_load_address (addr, XEXP (operands[1], 0)); |
2628 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2629 | }) |
2630 | ||
9db1d521 | 2631 | ; |
609e7e80 | 2632 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2633 | ; |
2634 | ||
609e7e80 AK |
2635 | (define_insn "mov<mode>" |
2636 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
3e4be43f | 2637 | "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R") |
609e7e80 | 2638 | (match_operand:SD_SF 1 "general_operand" |
3e4be43f | 2639 | " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))] |
4023fb28 | 2640 | "" |
9db1d521 | 2641 | "@ |
65b1d8ea | 2642 | lzer\t%0 |
ae1c6198 | 2643 | ldr\t%0,%1 |
d40c829f | 2644 | ler\t%0,%1 |
085261c8 | 2645 | lde\t%0,%1 |
d40c829f UW |
2646 | le\t%0,%1 |
2647 | ley\t%0,%1 | |
2648 | ste\t%1,%0 | |
2649 | stey\t%1,%0 | |
45e5214c | 2650 | lhi\t%0,0 |
d40c829f | 2651 | lr\t%0,%1 |
085261c8 | 2652 | lrl\t%0,%1 |
d40c829f UW |
2653 | l\t%0,%1 |
2654 | ly\t%0,%1 | |
085261c8 | 2655 | strl\t%1,%0 |
d40c829f | 2656 | st\t%1,%0 |
085261c8 AK |
2657 | sty\t%1,%0 |
2658 | vlr\t%v0,%v1 | |
298f4647 | 2659 | vleif\t%v0,0,0 |
085261c8 AK |
2660 | vlvgf\t%v0,%1,0 |
2661 | vlgvf\t%0,%v1,0 | |
298f4647 AK |
2662 | vlef\t%0,%1,0 |
2663 | vstef\t%1,%0,0" | |
ae1c6198 | 2664 | [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX") |
085261c8 AK |
2665 | (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>, |
2666 | fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store") | |
2667 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*") | |
285363a1 | 2668 | (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx")]) |
4023fb28 | 2669 | |
9dc62c00 AK |
2670 | ; |
2671 | ; movcc instruction pattern | |
2672 | ; | |
2673 | ||
2674 | (define_insn "movcc" | |
2675 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
5a3fe9b6 | 2676 | (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))] |
9dc62c00 AK |
2677 | "" |
2678 | "@ | |
2679 | lr\t%0,%1 | |
2680 | tmh\t%1,12288 | |
2681 | ipm\t%0 | |
a71f0749 DV |
2682 | l\t%0,%1 |
2683 | ly\t%0,%1 | |
2684 | st\t%1,%0 | |
2685 | sty\t%1,%0" | |
8dd3b235 | 2686 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
a71f0749 | 2687 | (set_attr "type" "lr,*,*,load,load,store,store") |
3e4be43f | 2688 | (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp") |
a71f0749 | 2689 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") |
65b1d8ea | 2690 | (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) |
9dc62c00 | 2691 | |
19b63d8e UW |
2692 | ; |
2693 | ; Block move (MVC) patterns. | |
2694 | ; | |
2695 | ||
2696 | (define_insn "*mvc" | |
2697 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2698 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2699 | (use (match_operand 2 "const_int_operand" "n"))] | |
2700 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2701 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2702 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2703 | |
0a88561f AK |
2704 | ; This splitter converts a QI to QI mode copy into a BLK mode copy in |
2705 | ; order to have it implemented with mvc. | |
2706 | ||
2707 | (define_split | |
2708 | [(set (match_operand:QI 0 "memory_operand" "") | |
2709 | (match_operand:QI 1 "memory_operand" ""))] | |
2710 | "reload_completed" | |
2711 | [(parallel | |
2712 | [(set (match_dup 0) (match_dup 1)) | |
2713 | (use (const_int 1))])] | |
2714 | { | |
2715 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
2716 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2717 | }) | |
2718 | ||
2719 | ||
19b63d8e UW |
2720 | (define_peephole2 |
2721 | [(parallel | |
2722 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2723 | (match_operand:BLK 1 "memory_operand" "")) | |
2724 | (use (match_operand 2 "const_int_operand" ""))]) | |
2725 | (parallel | |
2726 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2727 | (match_operand:BLK 4 "memory_operand" "")) | |
2728 | (use (match_operand 5 "const_int_operand" ""))])] | |
f9dcf14a AK |
2729 | "((INTVAL (operands[2]) > 16 && INTVAL (operands[5]) > 16) |
2730 | || (INTVAL (operands[2]) + INTVAL (operands[5]) <= 16)) | |
2731 | && s390_offset_p (operands[0], operands[3], operands[2]) | |
19b63d8e | 2732 | && s390_offset_p (operands[1], operands[4], operands[2]) |
9381e3f1 | 2733 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2734 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2735 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2736 | [(parallel | |
2737 | [(set (match_dup 6) (match_dup 7)) | |
2738 | (use (match_dup 8))])] | |
2739 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2740 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2741 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2742 | ||
f9dcf14a AK |
2743 | (define_peephole2 |
2744 | [(parallel | |
2745 | [(set (match_operand:BLK 0 "plus16_Q_operand" "") | |
2746 | (match_operand:BLK 1 "plus16_Q_operand" "")) | |
2747 | (use (match_operand 2 "const_int_operand" ""))])] | |
2748 | "INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32" | |
2749 | [(parallel | |
2750 | [(set (match_dup 0) (match_dup 1)) | |
2751 | (use (const_int 16))]) | |
2752 | (parallel | |
2753 | [(set (match_dup 3) (match_dup 4)) | |
2754 | (use (match_dup 5))])] | |
2755 | "operands[3] = change_address (operands[0], VOIDmode, | |
2756 | plus_constant (Pmode, XEXP (operands[0], 0), 16)); | |
2757 | operands[4] = change_address (operands[1], VOIDmode, | |
2758 | plus_constant (Pmode, XEXP (operands[1], 0), 16)); | |
2759 | operands[5] = GEN_INT (INTVAL (operands[2]) - 16);") | |
2760 | ||
19b63d8e | 2761 | |
9db1d521 HP |
2762 | ; |
2763 | ; load_multiple pattern(s). | |
2764 | ; | |
22ea6b4f UW |
2765 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2766 | ; we currently support load_multiple/store_multiple only after reload. | |
2767 | ; | |
9db1d521 HP |
2768 | |
2769 | (define_expand "load_multiple" | |
2770 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2771 | (match_operand 1 "" "")) | |
2772 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2773 | "reload_completed" |
9db1d521 | 2774 | { |
ef4bddc2 | 2775 | machine_mode mode; |
9db1d521 HP |
2776 | int regno; |
2777 | int count; | |
2778 | rtx from; | |
4023fb28 | 2779 | int i, off; |
9db1d521 HP |
2780 | |
2781 | /* Support only loading a constant number of fixed-point registers from | |
2782 | memory and only bother with this if more than two */ | |
2783 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2784 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2785 | || INTVAL (operands[2]) > 16 |
2786 | || GET_CODE (operands[1]) != MEM | |
2787 | || GET_CODE (operands[0]) != REG | |
2788 | || REGNO (operands[0]) >= 16) | |
2789 | FAIL; | |
2790 | ||
2791 | count = INTVAL (operands[2]); | |
2792 | regno = REGNO (operands[0]); | |
c19ec8f9 | 2793 | mode = GET_MODE (operands[0]); |
9602b6a1 | 2794 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2795 | FAIL; |
9db1d521 HP |
2796 | |
2797 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2798 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2799 | { |
2800 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2801 | { | |
2802 | from = XEXP (operands[1], 0); | |
2803 | off = 0; | |
2804 | } | |
2805 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2806 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2807 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2808 | { | |
2809 | from = XEXP (XEXP (operands[1], 0), 0); | |
2810 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2811 | } | |
2812 | else | |
2813 | FAIL; | |
4023fb28 UW |
2814 | } |
2815 | else | |
2816 | { | |
2817 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2818 | off = 0; | |
2819 | } | |
9db1d521 HP |
2820 | |
2821 | for (i = 0; i < count; i++) | |
2822 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2823 | = gen_rtx_SET (gen_rtx_REG (mode, regno + i), |
c19ec8f9 | 2824 | change_address (operands[1], mode, |
0a81f074 RS |
2825 | plus_constant (Pmode, from, |
2826 | off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2827 | }) |
9db1d521 HP |
2828 | |
2829 | (define_insn "*load_multiple_di" | |
2830 | [(match_parallel 0 "load_multiple_operation" | |
2831 | [(set (match_operand:DI 1 "register_operand" "=r") | |
3e4be43f | 2832 | (match_operand:DI 2 "s_operand" "S"))])] |
9602b6a1 | 2833 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2834 | { |
2835 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2836 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2837 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2838 | } |
d3632d41 | 2839 | [(set_attr "op_type" "RSY") |
4023fb28 | 2840 | (set_attr "type" "lm")]) |
9db1d521 HP |
2841 | |
2842 | (define_insn "*load_multiple_si" | |
2843 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2844 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2845 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2846 | "reload_completed" |
9db1d521 HP |
2847 | { |
2848 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2849 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2850 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2851 | } |
d3632d41 | 2852 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2853 | (set_attr "cpu_facility" "*,longdisp") |
4023fb28 | 2854 | (set_attr "type" "lm")]) |
9db1d521 HP |
2855 | |
2856 | ; | |
c7453384 | 2857 | ; store multiple pattern(s). |
9db1d521 HP |
2858 | ; |
2859 | ||
2860 | (define_expand "store_multiple" | |
2861 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2862 | (match_operand 1 "" "")) | |
2863 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2864 | "reload_completed" |
9db1d521 | 2865 | { |
ef4bddc2 | 2866 | machine_mode mode; |
9db1d521 HP |
2867 | int regno; |
2868 | int count; | |
2869 | rtx to; | |
4023fb28 | 2870 | int i, off; |
9db1d521 HP |
2871 | |
2872 | /* Support only storing a constant number of fixed-point registers to | |
2873 | memory and only bother with this if more than two. */ | |
2874 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2875 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2876 | || INTVAL (operands[2]) > 16 |
2877 | || GET_CODE (operands[0]) != MEM | |
2878 | || GET_CODE (operands[1]) != REG | |
2879 | || REGNO (operands[1]) >= 16) | |
2880 | FAIL; | |
2881 | ||
2882 | count = INTVAL (operands[2]); | |
2883 | regno = REGNO (operands[1]); | |
c19ec8f9 | 2884 | mode = GET_MODE (operands[1]); |
9602b6a1 | 2885 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2886 | FAIL; |
9db1d521 HP |
2887 | |
2888 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2889 | |
b3a13419 | 2890 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2891 | { |
2892 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2893 | { | |
2894 | to = XEXP (operands[0], 0); | |
2895 | off = 0; | |
2896 | } | |
2897 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2898 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2899 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2900 | { | |
2901 | to = XEXP (XEXP (operands[0], 0), 0); | |
2902 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2903 | } | |
2904 | else | |
2905 | FAIL; | |
4023fb28 | 2906 | } |
c7453384 | 2907 | else |
4023fb28 UW |
2908 | { |
2909 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2910 | off = 0; | |
2911 | } | |
9db1d521 HP |
2912 | |
2913 | for (i = 0; i < count; i++) | |
2914 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2915 | = gen_rtx_SET (change_address (operands[0], mode, |
0a81f074 RS |
2916 | plus_constant (Pmode, to, |
2917 | off + i * GET_MODE_SIZE (mode))), | |
c19ec8f9 | 2918 | gen_rtx_REG (mode, regno + i)); |
10bbf137 | 2919 | }) |
9db1d521 HP |
2920 | |
2921 | (define_insn "*store_multiple_di" | |
2922 | [(match_parallel 0 "store_multiple_operation" | |
3e4be43f | 2923 | [(set (match_operand:DI 1 "s_operand" "=S") |
9db1d521 | 2924 | (match_operand:DI 2 "register_operand" "r"))])] |
9602b6a1 | 2925 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2926 | { |
2927 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2928 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2929 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 2930 | } |
d3632d41 | 2931 | [(set_attr "op_type" "RSY") |
4023fb28 | 2932 | (set_attr "type" "stm")]) |
9db1d521 HP |
2933 | |
2934 | ||
2935 | (define_insn "*store_multiple_si" | |
2936 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
2937 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
2938 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 2939 | "reload_completed" |
9db1d521 HP |
2940 | { |
2941 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2942 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2943 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 2944 | } |
d3632d41 | 2945 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2946 | (set_attr "cpu_facility" "*,longdisp") |
4023fb28 | 2947 | (set_attr "type" "stm")]) |
9db1d521 HP |
2948 | |
2949 | ;; | |
2950 | ;; String instructions. | |
2951 | ;; | |
2952 | ||
963fc8d0 | 2953 | (define_insn "*execute_rl" |
2771c2f9 | 2954 | [(match_parallel 0 "execute_operation" |
963fc8d0 AK |
2955 | [(unspec [(match_operand 1 "register_operand" "a") |
2956 | (match_operand 2 "" "") | |
2957 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
2958 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2959 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2960 | "exrl\t%1,%3" | |
2961 | [(set_attr "op_type" "RIL") | |
2962 | (set_attr "type" "cs")]) | |
2963 | ||
9bb86f41 | 2964 | (define_insn "*execute" |
2771c2f9 | 2965 | [(match_parallel 0 "execute_operation" |
9bb86f41 UW |
2966 | [(unspec [(match_operand 1 "register_operand" "a") |
2967 | (match_operand:BLK 2 "memory_operand" "R") | |
2968 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
2969 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2970 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2971 | "ex\t%1,%2" | |
29a74354 UW |
2972 | [(set_attr "op_type" "RX") |
2973 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
2974 | |
2975 | ||
91d39d71 UW |
2976 | ; |
2977 | ; strlenM instruction pattern(s). | |
2978 | ; | |
2979 | ||
9db2f16d | 2980 | (define_expand "strlen<mode>" |
085261c8 AK |
2981 | [(match_operand:P 0 "register_operand" "") ; result |
2982 | (match_operand:BLK 1 "memory_operand" "") ; input string | |
2983 | (match_operand:SI 2 "immediate_operand" "") ; search character | |
2984 | (match_operand:SI 3 "immediate_operand" "")] ; known alignment | |
2985 | "" | |
2986 | { | |
2987 | if (!TARGET_VX || operands[2] != const0_rtx) | |
2988 | emit_insn (gen_strlen_srst<mode> (operands[0], operands[1], | |
2989 | operands[2], operands[3])); | |
2990 | else | |
2991 | s390_expand_vec_strlen (operands[0], operands[1], operands[3]); | |
2992 | ||
2993 | DONE; | |
2994 | }) | |
2995 | ||
2996 | (define_expand "strlen_srst<mode>" | |
ccbdc0d4 | 2997 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 2998 | (parallel |
91d39d71 | 2999 | [(set (match_dup 4) |
9db2f16d | 3000 | (unspec:P [(const_int 0) |
91d39d71 | 3001 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 3002 | (reg:SI 0) |
91d39d71 | 3003 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 3004 | (clobber (scratch:P)) |
ae156f85 | 3005 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 3006 | (parallel |
9db2f16d AS |
3007 | [(set (match_operand:P 0 "register_operand" "") |
3008 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 3009 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 3010 | "" |
91d39d71 | 3011 | { |
9db2f16d AS |
3012 | operands[4] = gen_reg_rtx (Pmode); |
3013 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
3014 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3015 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
3016 | }) | |
3017 | ||
9db2f16d AS |
3018 | (define_insn "*strlen<mode>" |
3019 | [(set (match_operand:P 0 "register_operand" "=a") | |
3020 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
3021 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 3022 | (reg:SI 0) |
91d39d71 | 3023 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 3024 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 3025 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 3026 | "" |
91d39d71 | 3027 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
3028 | [(set_attr "length" "8") |
3029 | (set_attr "type" "vs")]) | |
91d39d71 | 3030 | |
ccbdc0d4 AS |
3031 | ; |
3032 | ; cmpstrM instruction pattern(s). | |
3033 | ; | |
3034 | ||
3035 | (define_expand "cmpstrsi" | |
3036 | [(set (reg:SI 0) (const_int 0)) | |
3037 | (parallel | |
3038 | [(clobber (match_operand 3 "" "")) | |
3039 | (clobber (match_dup 4)) | |
3040 | (set (reg:CCU CC_REGNUM) | |
3041 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
3042 | (match_operand:BLK 2 "memory_operand" ""))) | |
3043 | (use (reg:SI 0))]) | |
3044 | (parallel | |
3045 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3046 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT)) |
ccbdc0d4 AS |
3047 | (clobber (reg:CC CC_REGNUM))])] |
3048 | "" | |
3049 | { | |
3050 | /* As the result of CMPINT is inverted compared to what we need, | |
3051 | we have to swap the operands. */ | |
3052 | rtx op1 = operands[2]; | |
3053 | rtx op2 = operands[1]; | |
3054 | rtx addr1 = gen_reg_rtx (Pmode); | |
3055 | rtx addr2 = gen_reg_rtx (Pmode); | |
3056 | ||
3057 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
3058 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
3059 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
3060 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
3061 | operands[3] = addr1; | |
3062 | operands[4] = addr2; | |
3063 | }) | |
3064 | ||
3065 | (define_insn "*cmpstr<mode>" | |
3066 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
3067 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
3068 | (set (reg:CCU CC_REGNUM) | |
3069 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
3070 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
3071 | (use (reg:SI 0))] | |
3072 | "" | |
3073 | "clst\t%0,%1\;jo\t.-4" | |
3074 | [(set_attr "length" "8") | |
3075 | (set_attr "type" "vs")]) | |
9381e3f1 | 3076 | |
742090fc AS |
3077 | ; |
3078 | ; movstr instruction pattern. | |
3079 | ; | |
3080 | ||
3081 | (define_expand "movstr" | |
4a7dec25 DV |
3082 | [(match_operand 0 "register_operand" "") |
3083 | (match_operand 1 "memory_operand" "") | |
3084 | (match_operand 2 "memory_operand" "")] | |
3085 | "" | |
3086 | { | |
3087 | if (TARGET_64BIT) | |
3088 | emit_insn (gen_movstrdi (operands[0], operands[1], operands[2])); | |
3089 | else | |
3090 | emit_insn (gen_movstrsi (operands[0], operands[1], operands[2])); | |
3091 | DONE; | |
3092 | }) | |
3093 | ||
3094 | (define_expand "movstr<P:mode>" | |
742090fc | 3095 | [(set (reg:SI 0) (const_int 0)) |
9381e3f1 | 3096 | (parallel |
742090fc AS |
3097 | [(clobber (match_dup 3)) |
3098 | (set (match_operand:BLK 1 "memory_operand" "") | |
3099 | (match_operand:BLK 2 "memory_operand" "")) | |
4a7dec25 DV |
3100 | (set (match_operand:P 0 "register_operand" "") |
3101 | (unspec:P [(match_dup 1) | |
742090fc AS |
3102 | (match_dup 2) |
3103 | (reg:SI 0)] UNSPEC_MVST)) | |
3104 | (clobber (reg:CC CC_REGNUM))])] | |
3105 | "" | |
3106 | { | |
859a4c0e AK |
3107 | rtx addr1, addr2; |
3108 | ||
3109 | if (TARGET_VX && optimize_function_for_speed_p (cfun)) | |
3110 | { | |
3111 | s390_expand_vec_movstr (operands[0], operands[1], operands[2]); | |
3112 | DONE; | |
3113 | } | |
3114 | ||
3115 | addr1 = gen_reg_rtx (Pmode); | |
3116 | addr2 = gen_reg_rtx (Pmode); | |
742090fc AS |
3117 | |
3118 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
3119 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
3120 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3121 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
3122 | operands[3] = addr2; | |
3123 | }) | |
3124 | ||
3125 | (define_insn "*movstr" | |
3126 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
3127 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
3128 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
3129 | (set (match_operand:P 0 "register_operand" "=d") | |
4a7dec25 | 3130 | (unspec:P [(mem:BLK (match_dup 1)) |
742090fc AS |
3131 | (mem:BLK (match_dup 3)) |
3132 | (reg:SI 0)] UNSPEC_MVST)) | |
3133 | (clobber (reg:CC CC_REGNUM))] | |
3134 | "" | |
3135 | "mvst\t%1,%2\;jo\t.-4" | |
3136 | [(set_attr "length" "8") | |
3137 | (set_attr "type" "vs")]) | |
9381e3f1 | 3138 | |
742090fc | 3139 | |
9db1d521 | 3140 | ; |
70128ad9 | 3141 | ; movmemM instruction pattern(s). |
9db1d521 HP |
3142 | ; |
3143 | ||
9db2f16d | 3144 | (define_expand "movmem<mode>" |
963fc8d0 AK |
3145 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
3146 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
3147 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
3148 | (match_operand 3 "" "")] |
3149 | "" | |
367d32f3 AK |
3150 | { |
3151 | if (s390_expand_movmem (operands[0], operands[1], operands[2])) | |
3152 | DONE; | |
3153 | else | |
3154 | FAIL; | |
3155 | }) | |
9db1d521 | 3156 | |
ecbe845e UW |
3157 | ; Move a block that is up to 256 bytes in length. |
3158 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3159 | |
70128ad9 | 3160 | (define_expand "movmem_short" |
b9404c99 UW |
3161 | [(parallel |
3162 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3163 | (match_operand:BLK 1 "memory_operand" "")) | |
3164 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3165 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3166 | (clobber (match_dup 3))])] |
3167 | "" | |
3168 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 3169 | |
70128ad9 | 3170 | (define_insn "*movmem_short" |
963fc8d0 AK |
3171 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
3172 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
3173 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3174 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3175 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3176 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3177 | "#" |
963fc8d0 | 3178 | [(set_attr "type" "cs") |
b5e0425c | 3179 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
ecbe845e | 3180 | |
9bb86f41 UW |
3181 | (define_split |
3182 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3183 | (match_operand:BLK 1 "memory_operand" "")) | |
3184 | (use (match_operand 2 "const_int_operand" "")) | |
3185 | (use (match_operand 3 "immediate_operand" "")) | |
3186 | (clobber (scratch))] | |
3187 | "reload_completed" | |
3188 | [(parallel | |
3189 | [(set (match_dup 0) (match_dup 1)) | |
3190 | (use (match_dup 2))])] | |
3191 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3192 | |
9bb86f41 UW |
3193 | (define_split |
3194 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3195 | (match_operand:BLK 1 "memory_operand" "")) | |
3196 | (use (match_operand 2 "register_operand" "")) | |
3197 | (use (match_operand 3 "memory_operand" "")) | |
3198 | (clobber (scratch))] | |
3199 | "reload_completed" | |
3200 | [(parallel | |
3201 | [(unspec [(match_dup 2) (match_dup 3) | |
3202 | (const_int 0)] UNSPEC_EXECUTE) | |
3203 | (set (match_dup 0) (match_dup 1)) | |
3204 | (use (const_int 1))])] | |
3205 | "") | |
3206 | ||
963fc8d0 AK |
3207 | (define_split |
3208 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3209 | (match_operand:BLK 1 "memory_operand" "")) | |
3210 | (use (match_operand 2 "register_operand" "")) | |
3211 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3212 | (clobber (scratch))] | |
3213 | "TARGET_Z10 && reload_completed" | |
3214 | [(parallel | |
3215 | [(unspec [(match_dup 2) (const_int 0) | |
3216 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3217 | (set (match_dup 0) (match_dup 1)) | |
3218 | (use (const_int 1))])] | |
3219 | "operands[3] = gen_label_rtx ();") | |
3220 | ||
9bb86f41 UW |
3221 | (define_split |
3222 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3223 | (match_operand:BLK 1 "memory_operand" "")) | |
3224 | (use (match_operand 2 "register_operand" "")) | |
3225 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3226 | (clobber (match_operand 3 "register_operand" ""))] | |
8cc6307c | 3227 | "reload_completed" |
9bb86f41 UW |
3228 | [(set (match_dup 3) (label_ref (match_dup 4))) |
3229 | (parallel | |
9381e3f1 | 3230 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
3231 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
3232 | (set (match_dup 0) (match_dup 1)) | |
3233 | (use (const_int 1))])] | |
3234 | "operands[4] = gen_label_rtx ();") | |
3235 | ||
a41c6c53 | 3236 | ; Move a block of arbitrary length. |
9db1d521 | 3237 | |
70128ad9 | 3238 | (define_expand "movmem_long" |
b9404c99 UW |
3239 | [(parallel |
3240 | [(clobber (match_dup 2)) | |
3241 | (clobber (match_dup 3)) | |
3242 | (set (match_operand:BLK 0 "memory_operand" "") | |
3243 | (match_operand:BLK 1 "memory_operand" "")) | |
3244 | (use (match_operand 2 "general_operand" "")) | |
3245 | (use (match_dup 3)) | |
ae156f85 | 3246 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3247 | "" |
3248 | { | |
ef4bddc2 RS |
3249 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3250 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3251 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3252 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3253 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3254 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3255 | rtx len0 = gen_lowpart (Pmode, reg0); |
3256 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3257 | ||
c41c1387 | 3258 | emit_clobber (reg0); |
b9404c99 UW |
3259 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3260 | emit_move_insn (len0, operands[2]); | |
3261 | ||
c41c1387 | 3262 | emit_clobber (reg1); |
b9404c99 UW |
3263 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3264 | emit_move_insn (len1, operands[2]); | |
3265 | ||
3266 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3267 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3268 | operands[2] = reg0; | |
3269 | operands[3] = reg1; | |
3270 | }) | |
3271 | ||
a1aed706 AS |
3272 | (define_insn "*movmem_long" |
3273 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3274 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
3275 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
3276 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
3277 | (use (match_dup 2)) |
3278 | (use (match_dup 3)) | |
ae156f85 | 3279 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 AK |
3280 | "TARGET_64BIT || !TARGET_ZARCH" |
3281 | "mvcle\t%0,%1,0\;jo\t.-4" | |
3282 | [(set_attr "length" "8") | |
3283 | (set_attr "type" "vs")]) | |
3284 | ||
3285 | (define_insn "*movmem_long_31z" | |
3286 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3287 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3288 | (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3289 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) | |
3290 | (use (match_dup 2)) | |
3291 | (use (match_dup 3)) | |
3292 | (clobber (reg:CC CC_REGNUM))] | |
3293 | "!TARGET_64BIT && TARGET_ZARCH" | |
d40c829f | 3294 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3295 | [(set_attr "length" "8") |
3296 | (set_attr "type" "vs")]) | |
9db1d521 | 3297 | |
638e37c2 WG |
3298 | |
3299 | ; | |
3300 | ; Test data class. | |
3301 | ; | |
3302 | ||
0f67fa83 WG |
3303 | (define_expand "signbit<mode>2" |
3304 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3305 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3306 | (match_dup 2)] | |
0f67fa83 WG |
3307 | UNSPEC_TDC_INSN)) |
3308 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3309 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
0f67fa83 WG |
3310 | "TARGET_HARD_FLOAT" |
3311 | { | |
3312 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
3313 | }) | |
3314 | ||
638e37c2 WG |
3315 | (define_expand "isinf<mode>2" |
3316 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3317 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3318 | (match_dup 2)] | |
638e37c2 WG |
3319 | UNSPEC_TDC_INSN)) |
3320 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3321 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
142cd70f | 3322 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
3323 | { |
3324 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
3325 | }) | |
3326 | ||
085261c8 AK |
3327 | ; This extracts CC into a GPR properly shifted. The actual IPM |
3328 | ; instruction will be issued by reload. The constraint of operand 1 | |
3329 | ; forces reload to use a GPR. So reload will issue a movcc insn for | |
3330 | ; copying CC into a GPR first. | |
5a3fe9b6 | 3331 | (define_insn_and_split "*cc_to_int" |
085261c8 | 3332 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
5a3fe9b6 AK |
3333 | (unspec:SI [(match_operand 1 "register_operand" "0")] |
3334 | UNSPEC_CC_TO_INT))] | |
3335 | "operands != NULL" | |
3336 | "#" | |
3337 | "reload_completed" | |
3338 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
3339 | ||
638e37c2 WG |
3340 | ; This insn is used to generate all variants of the Test Data Class |
3341 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
3342 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 3343 | ; specifying the required test(s). |
638e37c2 | 3344 | ; |
be5de7a1 | 3345 | ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet |
638e37c2 WG |
3346 | (define_insn "*TDC_insn_<mode>" |
3347 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 3348 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 3349 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 3350 | "TARGET_HARD_FLOAT" |
0387c142 | 3351 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 3352 | [(set_attr "op_type" "RXE") |
9381e3f1 | 3353 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 | 3354 | |
638e37c2 WG |
3355 | |
3356 | ||
9db1d521 | 3357 | ; |
57e84f18 | 3358 | ; setmemM instruction pattern(s). |
9db1d521 HP |
3359 | ; |
3360 | ||
57e84f18 | 3361 | (define_expand "setmem<mode>" |
a41c6c53 | 3362 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 3363 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 3364 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 3365 | (match_operand 3 "" "")] |
a41c6c53 | 3366 | "" |
6d057022 | 3367 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 3368 | |
a41c6c53 | 3369 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
3370 | ; The block length is taken as (operands[1] % 256) + 1. |
3371 | ||
70128ad9 | 3372 | (define_expand "clrmem_short" |
b9404c99 UW |
3373 | [(parallel |
3374 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3375 | (const_int 0)) | |
3376 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 3377 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 3378 | (clobber (match_dup 2)) |
ae156f85 | 3379 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3380 | "" |
3381 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3382 | |
70128ad9 | 3383 | (define_insn "*clrmem_short" |
963fc8d0 | 3384 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 3385 | (const_int 0)) |
963fc8d0 AK |
3386 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
3387 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
1eae36f0 | 3388 | (clobber (match_scratch:P 3 "=X,X,X,&a")) |
ae156f85 | 3389 | (clobber (reg:CC CC_REGNUM))] |
1eae36f0 | 3390 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" |
9bb86f41 | 3391 | "#" |
963fc8d0 | 3392 | [(set_attr "type" "cs") |
b5e0425c | 3393 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9bb86f41 UW |
3394 | |
3395 | (define_split | |
3396 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3397 | (const_int 0)) | |
3398 | (use (match_operand 1 "const_int_operand" "")) | |
3399 | (use (match_operand 2 "immediate_operand" "")) | |
3400 | (clobber (scratch)) | |
ae156f85 | 3401 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3402 | "reload_completed" |
3403 | [(parallel | |
3404 | [(set (match_dup 0) (const_int 0)) | |
3405 | (use (match_dup 1)) | |
ae156f85 | 3406 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3407 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 3408 | |
9bb86f41 UW |
3409 | (define_split |
3410 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3411 | (const_int 0)) | |
3412 | (use (match_operand 1 "register_operand" "")) | |
3413 | (use (match_operand 2 "memory_operand" "")) | |
3414 | (clobber (scratch)) | |
ae156f85 | 3415 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3416 | "reload_completed" |
3417 | [(parallel | |
3418 | [(unspec [(match_dup 1) (match_dup 2) | |
3419 | (const_int 0)] UNSPEC_EXECUTE) | |
3420 | (set (match_dup 0) (const_int 0)) | |
3421 | (use (const_int 1)) | |
ae156f85 | 3422 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3423 | "") |
9db1d521 | 3424 | |
963fc8d0 AK |
3425 | (define_split |
3426 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3427 | (const_int 0)) | |
3428 | (use (match_operand 1 "register_operand" "")) | |
3429 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3430 | (clobber (scratch)) | |
3431 | (clobber (reg:CC CC_REGNUM))] | |
3432 | "TARGET_Z10 && reload_completed" | |
3433 | [(parallel | |
3434 | [(unspec [(match_dup 1) (const_int 0) | |
3435 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3436 | (set (match_dup 0) (const_int 0)) | |
3437 | (use (const_int 1)) | |
3438 | (clobber (reg:CC CC_REGNUM))])] | |
3439 | "operands[3] = gen_label_rtx ();") | |
3440 | ||
9bb86f41 UW |
3441 | (define_split |
3442 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3443 | (const_int 0)) | |
3444 | (use (match_operand 1 "register_operand" "")) | |
3445 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3446 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 3447 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 3448 | "reload_completed" |
9bb86f41 UW |
3449 | [(set (match_dup 2) (label_ref (match_dup 3))) |
3450 | (parallel | |
9381e3f1 | 3451 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
3452 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
3453 | (set (match_dup 0) (const_int 0)) | |
3454 | (use (const_int 1)) | |
ae156f85 | 3455 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
3456 | "operands[3] = gen_label_rtx ();") |
3457 | ||
9381e3f1 | 3458 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 3459 | |
da0dcab1 | 3460 | (define_expand "setmem_long_<P:mode>" |
b9404c99 UW |
3461 | [(parallel |
3462 | [(clobber (match_dup 1)) | |
3463 | (set (match_operand:BLK 0 "memory_operand" "") | |
dd95128b | 3464 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "") |
da0dcab1 | 3465 | (match_dup 4)] UNSPEC_REPLICATE_BYTE)) |
6d057022 | 3466 | (use (match_dup 3)) |
ae156f85 | 3467 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 3468 | "" |
a41c6c53 | 3469 | { |
ef4bddc2 RS |
3470 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3471 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3472 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3473 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3474 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
b9404c99 | 3475 | rtx len0 = gen_lowpart (Pmode, reg0); |
9db1d521 | 3476 | |
c41c1387 | 3477 | emit_clobber (reg0); |
b9404c99 UW |
3478 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3479 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 3480 | |
b9404c99 | 3481 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 3482 | |
b9404c99 UW |
3483 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
3484 | operands[1] = reg0; | |
6d057022 | 3485 | operands[3] = reg1; |
da0dcab1 | 3486 | operands[4] = gen_lowpart (Pmode, operands[1]); |
b9404c99 | 3487 | }) |
a41c6c53 | 3488 | |
da0dcab1 DV |
3489 | ; Patterns for 31 bit + Esa and 64 bit + Zarch. |
3490 | ||
db340c73 | 3491 | (define_insn "*setmem_long" |
a1aed706 | 3492 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 3493 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
dd95128b | 3494 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y") |
da0dcab1 DV |
3495 | (subreg:P (match_dup 3) <modesize>)] |
3496 | UNSPEC_REPLICATE_BYTE)) | |
a1aed706 | 3497 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 3498 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3499 | "TARGET_64BIT || !TARGET_ZARCH" |
6d057022 | 3500 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
3501 | [(set_attr "length" "8") |
3502 | (set_attr "type" "vs")]) | |
9db1d521 | 3503 | |
db340c73 AK |
3504 | (define_insn "*setmem_long_and" |
3505 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3506 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
d876f5cd | 3507 | (unspec:BLK [(zero_extend:P (match_operand:QI 2 "setmem_operand" "Y")) |
db340c73 AK |
3508 | (subreg:P (match_dup 3) <modesize>)] |
3509 | UNSPEC_REPLICATE_BYTE)) | |
3510 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
3511 | (clobber (reg:CC CC_REGNUM))] | |
d876f5cd | 3512 | "(TARGET_64BIT || !TARGET_ZARCH)" |
db340c73 AK |
3513 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3514 | [(set_attr "length" "8") | |
3515 | (set_attr "type" "vs")]) | |
3516 | ||
da0dcab1 DV |
3517 | ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets |
3518 | ; of the SImode subregs. | |
3519 | ||
db340c73 | 3520 | (define_insn "*setmem_long_31z" |
9602b6a1 AK |
3521 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
3522 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
dd95128b | 3523 | (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y") |
da0dcab1 | 3524 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
9602b6a1 AK |
3525 | (use (match_operand:TI 1 "register_operand" "d")) |
3526 | (clobber (reg:CC CC_REGNUM))] | |
3527 | "!TARGET_64BIT && TARGET_ZARCH" | |
4989e88a AK |
3528 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3529 | [(set_attr "length" "8") | |
3530 | (set_attr "type" "vs")]) | |
9602b6a1 | 3531 | |
db340c73 AK |
3532 | (define_insn "*setmem_long_and_31z" |
3533 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3534 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
d876f5cd | 3535 | (unspec:BLK [(zero_extend:SI (match_operand:QI 2 "setmem_operand" "Y")) |
db340c73 AK |
3536 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
3537 | (use (match_operand:TI 1 "register_operand" "d")) | |
3538 | (clobber (reg:CC CC_REGNUM))] | |
d876f5cd | 3539 | "(!TARGET_64BIT && TARGET_ZARCH)" |
db340c73 AK |
3540 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3541 | [(set_attr "length" "8") | |
3542 | (set_attr "type" "vs")]) | |
3543 | ||
9db1d521 | 3544 | ; |
358b8f01 | 3545 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
3546 | ; |
3547 | ||
358b8f01 | 3548 | (define_expand "cmpmemsi" |
a41c6c53 UW |
3549 | [(set (match_operand:SI 0 "register_operand" "") |
3550 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
3551 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
3552 | (use (match_operand:SI 3 "general_operand" "")) | |
3553 | (use (match_operand:SI 4 "" ""))] | |
3554 | "" | |
367d32f3 AK |
3555 | { |
3556 | if (s390_expand_cmpmem (operands[0], operands[1], | |
3557 | operands[2], operands[3])) | |
3558 | DONE; | |
3559 | else | |
3560 | FAIL; | |
3561 | }) | |
9db1d521 | 3562 | |
a41c6c53 UW |
3563 | ; Compare a block that is up to 256 bytes in length. |
3564 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3565 | |
b9404c99 UW |
3566 | (define_expand "cmpmem_short" |
3567 | [(parallel | |
ae156f85 | 3568 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 3569 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3570 | (match_operand:BLK 1 "memory_operand" ""))) |
3571 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3572 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3573 | (clobber (match_dup 3))])] |
3574 | "" | |
3575 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3576 | |
b9404c99 | 3577 | (define_insn "*cmpmem_short" |
ae156f85 | 3578 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
3579 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
3580 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
3581 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3582 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3583 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3584 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3585 | "#" |
963fc8d0 | 3586 | [(set_attr "type" "cs") |
b5e0425c | 3587 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9db1d521 | 3588 | |
9bb86f41 | 3589 | (define_split |
ae156f85 | 3590 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3591 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3592 | (match_operand:BLK 1 "memory_operand" ""))) | |
3593 | (use (match_operand 2 "const_int_operand" "")) | |
3594 | (use (match_operand 3 "immediate_operand" "")) | |
3595 | (clobber (scratch))] | |
3596 | "reload_completed" | |
3597 | [(parallel | |
ae156f85 | 3598 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3599 | (use (match_dup 2))])] |
3600 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3601 | |
9bb86f41 | 3602 | (define_split |
ae156f85 | 3603 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3604 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3605 | (match_operand:BLK 1 "memory_operand" ""))) | |
3606 | (use (match_operand 2 "register_operand" "")) | |
3607 | (use (match_operand 3 "memory_operand" "")) | |
3608 | (clobber (scratch))] | |
3609 | "reload_completed" | |
3610 | [(parallel | |
3611 | [(unspec [(match_dup 2) (match_dup 3) | |
3612 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 3613 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3614 | (use (const_int 1))])] |
3615 | "") | |
3616 | ||
963fc8d0 AK |
3617 | (define_split |
3618 | [(set (reg:CCU CC_REGNUM) | |
3619 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3620 | (match_operand:BLK 1 "memory_operand" ""))) | |
3621 | (use (match_operand 2 "register_operand" "")) | |
3622 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3623 | (clobber (scratch))] | |
3624 | "TARGET_Z10 && reload_completed" | |
3625 | [(parallel | |
3626 | [(unspec [(match_dup 2) (const_int 0) | |
3627 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
3628 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
3629 | (use (const_int 1))])] | |
3630 | "operands[4] = gen_label_rtx ();") | |
3631 | ||
9bb86f41 | 3632 | (define_split |
ae156f85 | 3633 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3634 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3635 | (match_operand:BLK 1 "memory_operand" ""))) | |
3636 | (use (match_operand 2 "register_operand" "")) | |
3637 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3638 | (clobber (match_operand 3 "register_operand" ""))] | |
8cc6307c | 3639 | "reload_completed" |
9bb86f41 UW |
3640 | [(set (match_dup 3) (label_ref (match_dup 4))) |
3641 | (parallel | |
9381e3f1 | 3642 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 3643 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 3644 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3645 | (use (const_int 1))])] |
3646 | "operands[4] = gen_label_rtx ();") | |
3647 | ||
a41c6c53 | 3648 | ; Compare a block of arbitrary length. |
9db1d521 | 3649 | |
b9404c99 UW |
3650 | (define_expand "cmpmem_long" |
3651 | [(parallel | |
3652 | [(clobber (match_dup 2)) | |
3653 | (clobber (match_dup 3)) | |
ae156f85 | 3654 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 3655 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3656 | (match_operand:BLK 1 "memory_operand" ""))) |
3657 | (use (match_operand 2 "general_operand" "")) | |
3658 | (use (match_dup 3))])] | |
3659 | "" | |
3660 | { | |
ef4bddc2 RS |
3661 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3662 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3663 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3664 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3665 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3666 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3667 | rtx len0 = gen_lowpart (Pmode, reg0); |
3668 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3669 | ||
c41c1387 | 3670 | emit_clobber (reg0); |
b9404c99 UW |
3671 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3672 | emit_move_insn (len0, operands[2]); | |
3673 | ||
c41c1387 | 3674 | emit_clobber (reg1); |
b9404c99 UW |
3675 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3676 | emit_move_insn (len1, operands[2]); | |
3677 | ||
3678 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3679 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3680 | operands[2] = reg0; | |
3681 | operands[3] = reg1; | |
3682 | }) | |
3683 | ||
a1aed706 AS |
3684 | (define_insn "*cmpmem_long" |
3685 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3686 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3687 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3688 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3689 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3690 | (use (match_dup 2)) |
3691 | (use (match_dup 3))] | |
9602b6a1 | 3692 | "TARGET_64BIT || !TARGET_ZARCH" |
287ff198 | 3693 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3694 | [(set_attr "length" "8") |
3695 | (set_attr "type" "vs")]) | |
9db1d521 | 3696 | |
9602b6a1 AK |
3697 | (define_insn "*cmpmem_long_31z" |
3698 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3699 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3700 | (set (reg:CCU CC_REGNUM) | |
3701 | (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3702 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) | |
3703 | (use (match_dup 2)) | |
3704 | (use (match_dup 3))] | |
3705 | "!TARGET_64BIT && TARGET_ZARCH" | |
3706 | "clcle\t%0,%1,0\;jo\t.-4" | |
3707 | [(set_attr "op_type" "NN") | |
3708 | (set_attr "type" "vs") | |
3709 | (set_attr "length" "8")]) | |
3710 | ||
02887425 UW |
3711 | ; Convert CCUmode condition code to integer. |
3712 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3713 | |
02887425 | 3714 | (define_insn_and_split "cmpint" |
9db1d521 | 3715 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3716 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3717 | UNSPEC_STRCMPCC_TO_INT)) |
ae156f85 | 3718 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3719 | "" |
02887425 UW |
3720 | "#" |
3721 | "reload_completed" | |
3722 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3723 | (parallel | |
3724 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3725 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3726 | |
3727 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3728 | [(set (reg CC_REGNUM) |
02887425 | 3729 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3730 | UNSPEC_STRCMPCC_TO_INT) |
02887425 UW |
3731 | (const_int 0))) |
3732 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3733 | (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))] |
02887425 UW |
3734 | "s390_match_ccmode (insn, CCSmode)" |
3735 | "#" | |
3736 | "&& reload_completed" | |
3737 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3738 | (parallel | |
3739 | [(set (match_dup 2) (match_dup 3)) | |
3740 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3741 | { |
02887425 UW |
3742 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3743 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3744 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3745 | }) | |
9db1d521 | 3746 | |
02887425 | 3747 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3748 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3749 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3750 | UNSPEC_STRCMPCC_TO_INT))) |
ae156f85 | 3751 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3752 | "TARGET_ZARCH" |
02887425 UW |
3753 | "#" |
3754 | "&& reload_completed" | |
3755 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3756 | (parallel | |
3757 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3758 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3759 | |
3760 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3761 | [(set (reg CC_REGNUM) |
9381e3f1 | 3762 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3763 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3764 | UNSPEC_STRCMPCC_TO_INT) 0) |
02887425 UW |
3765 | (const_int 32)) (const_int 32)) |
3766 | (const_int 0))) | |
3767 | (set (match_operand:DI 0 "register_operand" "=d") | |
5a3fe9b6 | 3768 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))] |
9602b6a1 | 3769 | "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" |
02887425 UW |
3770 | "#" |
3771 | "&& reload_completed" | |
3772 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3773 | (parallel | |
3774 | [(set (match_dup 2) (match_dup 3)) | |
3775 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3776 | { |
02887425 UW |
3777 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3778 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3779 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3780 | }) | |
9db1d521 | 3781 | |
4023fb28 | 3782 | |
9db1d521 HP |
3783 | ;; |
3784 | ;;- Conversion instructions. | |
3785 | ;; | |
3786 | ||
6fa05db6 | 3787 | (define_insn "*sethighpartsi" |
d3632d41 | 3788 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3789 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3790 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3791 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3792 | "" |
d3632d41 | 3793 | "@ |
6fa05db6 AS |
3794 | icm\t%0,%2,%S1 |
3795 | icmy\t%0,%2,%S1" | |
9381e3f1 | 3796 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3797 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 3798 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
4023fb28 | 3799 | |
6fa05db6 | 3800 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3801 | [(set (match_operand:DI 0 "register_operand" "=d") |
3e4be43f | 3802 | (unspec:DI [(match_operand:BLK 1 "s_operand" "S") |
6fa05db6 | 3803 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) |
ae156f85 | 3804 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3805 | "TARGET_ZARCH" |
6fa05db6 | 3806 | "icmh\t%0,%2,%S1" |
729e750f WG |
3807 | [(set_attr "op_type" "RSY") |
3808 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3809 | |
6fa05db6 | 3810 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3811 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3812 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3813 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3814 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3815 | "!TARGET_ZARCH" |
d3632d41 | 3816 | "@ |
6fa05db6 AS |
3817 | icm\t%0,%2,%S1 |
3818 | icmy\t%0,%2,%S1" | |
9381e3f1 | 3819 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3820 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 WG |
3821 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
3822 | ||
1a2e356e RH |
3823 | ; |
3824 | ; extv instruction patterns | |
3825 | ; | |
3826 | ||
3827 | ; FIXME: This expander needs to be converted from DI to GPR as well | |
3828 | ; after resolving some issues with it. | |
3829 | ||
3830 | (define_expand "extzv" | |
3831 | [(parallel | |
3832 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3833 | (zero_extract:DI | |
3834 | (match_operand:DI 1 "register_operand" "d") | |
3835 | (match_operand 2 "const_int_operand" "") ; size | |
3836 | (match_operand 3 "const_int_operand" ""))) ; start | |
3837 | (clobber (reg:CC CC_REGNUM))])] | |
3838 | "TARGET_Z10" | |
3839 | { | |
0f6f72e8 DV |
3840 | if (! EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64)) |
3841 | FAIL; | |
1a2e356e RH |
3842 | /* Starting with zEC12 there is risbgn not clobbering CC. */ |
3843 | if (TARGET_ZEC12) | |
3844 | { | |
3845 | emit_move_insn (operands[0], | |
3846 | gen_rtx_ZERO_EXTRACT (DImode, | |
3847 | operands[1], | |
3848 | operands[2], | |
3849 | operands[3])); | |
3850 | DONE; | |
3851 | } | |
3852 | }) | |
3853 | ||
64c744b9 | 3854 | (define_insn "*extzv<mode><clobbercc_or_nocc>" |
1a2e356e RH |
3855 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3856 | (zero_extract:GPR | |
3857 | (match_operand:GPR 1 "register_operand" "d") | |
3858 | (match_operand 2 "const_int_operand" "") ; size | |
64c744b9 DV |
3859 | (match_operand 3 "const_int_operand" ""))) ; start |
3860 | ] | |
0f6f72e8 DV |
3861 | "<z10_or_zEC12_cond> |
3862 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), | |
3863 | GET_MODE_BITSIZE (<MODE>mode))" | |
64c744b9 DV |
3864 | "<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift |
3865 | [(set_attr "op_type" "RIE") | |
3866 | (set_attr "z10prop" "z10_super_E1")]) | |
1a2e356e | 3867 | |
64c744b9 DV |
3868 | ; 64 bit: (a & -16) | ((b >> 8) & 15) |
3869 | (define_insn "*extzvdi<clobbercc_or_nocc>_lshiftrt" | |
3870 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3871 | (match_operand 1 "const_int_operand" "") ; size | |
3872 | (match_operand 2 "const_int_operand" "")) ; start | |
3873 | (lshiftrt:DI (match_operand:DI 3 "register_operand" "d") | |
3874 | (match_operand:DI 4 "nonzero_shift_count_operand" "")))] | |
3875 | "<z10_or_zEC12_cond> | |
0f6f72e8 | 3876 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
64c744b9 DV |
3877 | && 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])" |
3878 | "<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4" | |
3879 | [(set_attr "op_type" "RIE") | |
3880 | (set_attr "z10prop" "z10_super_E1")]) | |
3881 | ||
3882 | ; 32 bit: (a & -16) | ((b >> 8) & 15) | |
3883 | (define_insn "*<risbg_n>_ior_and_sr_ze" | |
3884 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3885 | (ior:SI (and:SI | |
3886 | (match_operand:SI 1 "register_operand" "0") | |
3887 | (match_operand:SI 2 "const_int_operand" "")) | |
3888 | (subreg:SI | |
3889 | (zero_extract:DI | |
3890 | (match_operand:DI 3 "register_operand" "d") | |
3891 | (match_operand 4 "const_int_operand" "") ; size | |
3892 | (match_operand 5 "const_int_operand" "")) ; start | |
3893 | 4)))] | |
3894 | "<z10_or_zEC12_cond> | |
0f6f72e8 | 3895 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64) |
64c744b9 DV |
3896 | && UINTVAL (operands[2]) == (~(0ULL) << UINTVAL (operands[4]))" |
3897 | "<risbg_n>\t%0,%3,64-%4,63,%4+%5" | |
3898 | [(set_attr "op_type" "RIE") | |
3899 | (set_attr "z10prop" "z10_super_E1")]) | |
3900 | ||
3901 | ; ((int)foo >> 10) & 1; | |
3902 | (define_insn "*extract1bitdi<clobbercc_or_nocc>" | |
3903 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3904 | (ne:DI (zero_extract:DI | |
3905 | (match_operand:DI 1 "register_operand" "d") | |
3906 | (const_int 1) ; size | |
3907 | (match_operand 2 "const_int_operand" "")) ; start | |
3908 | (const_int 0)))] | |
0f6f72e8 DV |
3909 | "<z10_or_zEC12_cond> |
3910 | && EXTRACT_ARGS_IN_RANGE (1, INTVAL (operands[2]), 64)" | |
64c744b9 DV |
3911 | "<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift |
3912 | [(set_attr "op_type" "RIE") | |
3913 | (set_attr "z10prop" "z10_super_E1")]) | |
3914 | ||
3915 | (define_insn "*<risbg_n>_and_subregdi_rotr" | |
3916 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3917 | (and:DI (subreg:DI | |
3918 | (rotate:SINT (match_operand:SINT 1 "register_operand" "d") | |
3919 | (match_operand:SINT 2 "const_int_operand" "")) 0) | |
3920 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3921 | "<z10_or_zEC12_cond> | |
3922 | && UINTVAL (operands[3]) < (1ULL << (UINTVAL (operands[2]) & 0x3f))" | |
3923 | "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift | |
3924 | [(set_attr "op_type" "RIE") | |
3925 | (set_attr "z10prop" "z10_super_E1")]) | |
3926 | ||
3927 | (define_insn "*<risbg_n>_and_subregdi_rotl" | |
3928 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3929 | (and:DI (subreg:DI | |
3930 | (rotate:SINT (match_operand:SINT 1 "register_operand" "d") | |
3931 | (match_operand:SINT 2 "const_int_operand" "")) 0) | |
3932 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3933 | "<z10_or_zEC12_cond> | |
3934 | && !(UINTVAL (operands[3]) & ((1ULL << (UINTVAL (operands[2]) & 0x3f)) - 1))" | |
3935 | "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift | |
3936 | [(set_attr "op_type" "RIE") | |
3937 | (set_attr "z10prop" "z10_super_E1")]) | |
3938 | ||
3939 | (define_insn "*<risbg_n>_di_and_rot" | |
3940 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3941 | (and:DI (rotate:DI (match_operand:DI 1 "register_operand" "d") | |
3942 | (match_operand:DI 2 "const_int_operand" "")) | |
3943 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3944 | "<z10_or_zEC12_cond>" | |
3945 | "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift | |
1a2e356e RH |
3946 | [(set_attr "op_type" "RIE") |
3947 | (set_attr "z10prop" "z10_super_E1")]) | |
4023fb28 | 3948 | |
1a2e356e | 3949 | (define_insn_and_split "*pre_z10_extzv<mode>" |
6fa05db6 | 3950 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3e4be43f | 3951 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "S") |
1a2e356e | 3952 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3953 | (const_int 0))) |
ae156f85 | 3954 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3955 | "!TARGET_Z10" |
cc7ab9b7 UW |
3956 | "#" |
3957 | "&& reload_completed" | |
4023fb28 | 3958 | [(parallel |
6fa05db6 | 3959 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3960 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 3961 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 3962 | { |
6fa05db6 AS |
3963 | int bitsize = INTVAL (operands[2]); |
3964 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3965 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3966 | ||
3967 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3968 | set_mem_size (operands[1], size); |
2542ef05 | 3969 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 | 3970 | operands[3] = GEN_INT (mask); |
b628bd8e | 3971 | }) |
4023fb28 | 3972 | |
1a2e356e | 3973 | (define_insn_and_split "*pre_z10_extv<mode>" |
6fa05db6 | 3974 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3e4be43f | 3975 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "S") |
1a2e356e | 3976 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3977 | (const_int 0))) |
ae156f85 | 3978 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3979 | "" |
cc7ab9b7 UW |
3980 | "#" |
3981 | "&& reload_completed" | |
4023fb28 | 3982 | [(parallel |
6fa05db6 | 3983 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3984 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
3985 | (parallel |
3986 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
3987 | (clobber (reg:CC CC_REGNUM))])] | |
3988 | { | |
3989 | int bitsize = INTVAL (operands[2]); | |
3990 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3991 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3992 | ||
3993 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3994 | set_mem_size (operands[1], size); |
2542ef05 | 3995 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 AS |
3996 | operands[3] = GEN_INT (mask); |
3997 | }) | |
3998 | ||
3999 | ; | |
4000 | ; insv instruction patterns | |
4001 | ; | |
4002 | ||
4003 | (define_expand "insv" | |
4004 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
4005 | (match_operand 1 "const_int_operand" "") | |
4006 | (match_operand 2 "const_int_operand" "")) | |
4007 | (match_operand 3 "general_operand" ""))] | |
4008 | "" | |
4023fb28 | 4009 | { |
6fa05db6 AS |
4010 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
4011 | DONE; | |
4012 | FAIL; | |
b628bd8e | 4013 | }) |
4023fb28 | 4014 | |
2542ef05 RH |
4015 | |
4016 | ; The normal RTL expansion will never generate a zero_extract where | |
4017 | ; the location operand isn't word mode. However, we do this in the | |
4018 | ; back-end when generating atomic operations. See s390_two_part_insv. | |
64c744b9 | 4019 | (define_insn "*insv<mode><clobbercc_or_nocc>" |
22ac2c2f | 4020 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") |
2542ef05 RH |
4021 | (match_operand 1 "const_int_operand" "I") ; size |
4022 | (match_operand 2 "const_int_operand" "I")) ; pos | |
22ac2c2f | 4023 | (match_operand:GPR 3 "nonimmediate_operand" "d"))] |
64c744b9 | 4024 | "<z10_or_zEC12_cond> |
0f6f72e8 DV |
4025 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), |
4026 | GET_MODE_BITSIZE (<MODE>mode)) | |
2542ef05 | 4027 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
64c744b9 | 4028 | "<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1" |
9381e3f1 WG |
4029 | [(set_attr "op_type" "RIE") |
4030 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 4031 | |
22ac2c2f AK |
4032 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest |
4033 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
64c744b9 DV |
4034 | (define_insn "*insv<mode><clobbercc_or_nocc>_noshift" |
4035 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d") | |
4036 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d,0") | |
75ca1b39 | 4037 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
64c744b9 | 4038 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0,d") |
75ca1b39 | 4039 | (match_operand:GPR 4 "const_int_operand" ""))))] |
64c744b9 DV |
4040 | "<z10_or_zEC12_cond> && INTVAL (operands[2]) == ~INTVAL (operands[4])" |
4041 | "@ | |
4042 | <risbg_n>\t%0,%1,%<bfstart>2,%<bfend>2,0 | |
4043 | <risbg_n>\t%0,%3,%<bfstart>4,%<bfend>4,0" | |
4044 | [(set_attr "op_type" "RIE") | |
4045 | (set_attr "z10prop" "z10_super_E1")]) | |
22ac2c2f | 4046 | |
64c744b9 DV |
4047 | (define_insn "*insv_z10_noshift_cc" |
4048 | [(set (reg CC_REGNUM) | |
4049 | (compare | |
4050 | (ior:DI | |
4051 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") | |
4052 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4053 | (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") | |
4054 | (match_operand:DI 4 "const_int_operand" ""))) | |
4055 | (const_int 0))) | |
4056 | (set (match_operand:DI 0 "nonimmediate_operand" "=d,d") | |
4057 | (ior:DI (and:DI (match_dup 1) (match_dup 2)) | |
4058 | (and:DI (match_dup 3) (match_dup 4))))] | |
4059 | "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) | |
4060 | && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
4061 | "@ | |
4062 | risbg\t%0,%1,%s2,%e2,0 | |
4063 | risbg\t%0,%3,%s4,%e4,0" | |
4064 | [(set_attr "op_type" "RIE") | |
4065 | (set_attr "z10prop" "z10_super_E1")]) | |
4066 | ||
4067 | (define_insn "*insv_z10_noshift_cconly" | |
4068 | [(set | |
4069 | (reg CC_REGNUM) | |
4070 | (compare | |
4071 | (ior:DI | |
4072 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") | |
4073 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4074 | (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") | |
4075 | (match_operand:DI 4 "const_int_operand" ""))) | |
4076 | (const_int 0))) | |
4077 | (clobber (match_scratch:DI 0 "=d,d"))] | |
4078 | "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) | |
4079 | && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
4080 | "@ | |
4081 | risbg\t%0,%1,%s2,%e2,0 | |
4082 | risbg\t%0,%3,%s4,%e4,0" | |
9381e3f1 WG |
4083 | [(set_attr "op_type" "RIE") |
4084 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 4085 | |
3d44ff99 AK |
4086 | ; Implement appending Y on the left of S bits of X |
4087 | ; x = (y << s) | (x & ((1 << s) - 1)) | |
64c744b9 | 4088 | (define_insn "*insv<mode><clobbercc_or_nocc>_appendbitsleft" |
3d44ff99 AK |
4089 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4090 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") | |
4091 | (match_operand:GPR 2 "immediate_operand" "")) | |
4092 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") | |
4093 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
64c744b9 DV |
4094 | "<z10_or_zEC12_cond> |
4095 | && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1" | |
4096 | "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4" | |
3d44ff99 AK |
4097 | [(set_attr "op_type" "RIE") |
4098 | (set_attr "z10prop" "z10_super_E1")]) | |
4099 | ||
64c744b9 DV |
4100 | ; a = ((i32)a & -16777216) | (((ui32)b) >> 8) |
4101 | (define_insn "*<risbg_n>_<mode>_ior_and_lshiftrt" | |
4102 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4103 | (ior:GPR (and:GPR | |
4104 | (match_operand:GPR 1 "register_operand" "0") | |
4105 | (match_operand:GPR 2 "const_int_operand" "")) | |
4106 | (lshiftrt:GPR | |
4107 | (match_operand:GPR 3 "register_operand" "d") | |
4108 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
4109 | "<z10_or_zEC12_cond> && UINTVAL (operands[2]) | |
4110 | == (~(0ULL) << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))" | |
4111 | "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4" | |
4112 | [(set_attr "op_type" "RIE") | |
4113 | (set_attr "z10prop" "z10_super_E1")]) | |
4114 | ||
4115 | ; (ui32)(((ui64)x) >> 48) | ((i32)y & -65536); | |
4116 | (define_insn "*<risbg_n>_sidi_ior_and_lshiftrt" | |
4117 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4118 | (ior:SI (and:SI | |
4119 | (match_operand:SI 1 "register_operand" "0") | |
4120 | (match_operand:SI 2 "const_int_operand" "")) | |
4121 | (subreg:SI | |
4122 | (lshiftrt:DI | |
4123 | (match_operand:DI 3 "register_operand" "d") | |
4124 | (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))] | |
4125 | "<z10_or_zEC12_cond> | |
4126 | && UINTVAL (operands[2]) == ~(~(0ULL) >> UINTVAL (operands[4]))" | |
4127 | "<risbg_n>\t%0,%3,%4,63,64-%4" | |
4128 | [(set_attr "op_type" "RIE") | |
4129 | (set_attr "z10prop" "z10_super_E1")]) | |
4130 | ||
4131 | ; (ui32)(((ui64)x) >> 12) & -4 | |
4132 | (define_insn "*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>" | |
4133 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4134 | (and:SI | |
4135 | (subreg:SI (lshiftrt:DI | |
4136 | (match_operand:DI 1 "register_operand" "d") | |
4137 | (match_operand:DI 2 "nonzero_shift_count_operand" "")) 4) | |
4138 | (match_operand:SI 3 "contiguous_bitmask_nowrap_operand" "")))] | |
4139 | "<z10_or_zEC12_cond>" | |
4140 | "<risbg_n>\t%0,%1,%t3,128+%f3,64-%2" | |
3d44ff99 AK |
4141 | [(set_attr "op_type" "RIE") |
4142 | (set_attr "z10prop" "z10_super_E1")]) | |
4143 | ||
4144 | ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting | |
4145 | ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1)) | |
4146 | ; -> z = y >> d; z = risbg; | |
4147 | ||
4148 | (define_split | |
4149 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
4150 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
4151 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4152 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
4153 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
4154 | "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 4155 | [(set (match_dup 6) |
3d44ff99 AK |
4156 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
4157 | (set (match_dup 0) | |
1d11f7ce | 4158 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
4159 | (ashift:GPR (match_dup 3) (match_dup 4))))] |
4160 | { | |
4161 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
3168e073 | 4162 | if (reg_overlap_mentioned_p (operands[0], operands[3])) |
1d11f7ce AK |
4163 | { |
4164 | if (!can_create_pseudo_p ()) | |
4165 | FAIL; | |
4166 | operands[6] = gen_reg_rtx (<MODE>mode); | |
4167 | } | |
4168 | else | |
4169 | operands[6] = operands[0]; | |
3d44ff99 AK |
4170 | }) |
4171 | ||
4172 | (define_split | |
4173 | [(parallel | |
4174 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
4175 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
4176 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4177 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
4178 | (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) | |
4179 | (clobber (reg:CC CC_REGNUM))])] | |
4180 | "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 4181 | [(set (match_dup 6) |
3d44ff99 AK |
4182 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
4183 | (parallel | |
4184 | [(set (match_dup 0) | |
1d11f7ce | 4185 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
4186 | (ashift:GPR (match_dup 3) (match_dup 4)))) |
4187 | (clobber (reg:CC CC_REGNUM))])] | |
4188 | { | |
4189 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
3168e073 | 4190 | if (reg_overlap_mentioned_p (operands[0], operands[3])) |
1d11f7ce AK |
4191 | { |
4192 | if (!can_create_pseudo_p ()) | |
4193 | FAIL; | |
4194 | operands[6] = gen_reg_rtx (<MODE>mode); | |
4195 | } | |
4196 | else | |
4197 | operands[6] = operands[0]; | |
3d44ff99 AK |
4198 | }) |
4199 | ||
50dc4eed | 4200 | ; rosbg, rxsbg |
571e408a | 4201 | (define_insn "*r<noxa>sbg_<mode>_noshift" |
963fc8d0 | 4202 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
571e408a RH |
4203 | (IXOR:GPR |
4204 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4205 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
4206 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
963fc8d0 | 4207 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 | 4208 | "TARGET_Z10" |
571e408a RH |
4209 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0" |
4210 | [(set_attr "op_type" "RIE")]) | |
4211 | ||
50dc4eed | 4212 | ; rosbg, rxsbg |
571e408a RH |
4213 | (define_insn "*r<noxa>sbg_di_rotl" |
4214 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") | |
4215 | (IXOR:DI | |
4216 | (and:DI | |
4217 | (rotate:DI | |
4218 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
4219 | (match_operand:DI 3 "const_int_operand" "")) | |
4220 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4221 | (match_operand:DI 4 "nonimmediate_operand" "0"))) | |
4222 | (clobber (reg:CC CC_REGNUM))] | |
4223 | "TARGET_Z10" | |
4224 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3" | |
4225 | [(set_attr "op_type" "RIE")]) | |
4226 | ||
50dc4eed | 4227 | ; rosbg, rxsbg |
f3d90045 | 4228 | (define_insn "*r<noxa>sbg_<mode>_srl_bitmask" |
571e408a RH |
4229 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4230 | (IXOR:GPR | |
4231 | (and:GPR | |
4232 | (lshiftrt:GPR | |
4233 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4234 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 4235 | (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) |
571e408a RH |
4236 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) |
4237 | (clobber (reg:CC CC_REGNUM))] | |
4238 | "TARGET_Z10 | |
4239 | && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), | |
4240 | INTVAL (operands[2]))" | |
4241 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3" | |
4242 | [(set_attr "op_type" "RIE")]) | |
4243 | ||
50dc4eed | 4244 | ; rosbg, rxsbg |
f3d90045 | 4245 | (define_insn "*r<noxa>sbg_<mode>_sll_bitmask" |
571e408a RH |
4246 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4247 | (IXOR:GPR | |
4248 | (and:GPR | |
4249 | (ashift:GPR | |
4250 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4251 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 4252 | (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) |
571e408a RH |
4253 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) |
4254 | (clobber (reg:CC CC_REGNUM))] | |
4255 | "TARGET_Z10 | |
4256 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]), | |
4257 | INTVAL (operands[2]))" | |
4258 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3" | |
963fc8d0 AK |
4259 | [(set_attr "op_type" "RIE")]) |
4260 | ||
f3d90045 DV |
4261 | ;; unsigned {int,long} a, b |
4262 | ;; a = a | (b << const_int) | |
4263 | ;; a = a ^ (b << const_int) | |
50dc4eed | 4264 | ; rosbg, rxsbg |
f3d90045 DV |
4265 | (define_insn "*r<noxa>sbg_<mode>_sll" |
4266 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
4267 | (IXOR:GPR | |
4268 | (ashift:GPR | |
4269 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4270 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4271 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
4272 | (clobber (reg:CC CC_REGNUM))] | |
4273 | "TARGET_Z10" | |
576987fc | 4274 | "r<noxa>sbg\t%0,%1,<bitoff>,63-%2,%2" |
f3d90045 DV |
4275 | [(set_attr "op_type" "RIE")]) |
4276 | ||
4277 | ;; unsigned {int,long} a, b | |
4278 | ;; a = a | (b >> const_int) | |
4279 | ;; a = a ^ (b >> const_int) | |
50dc4eed | 4280 | ; rosbg, rxsbg |
f3d90045 DV |
4281 | (define_insn "*r<noxa>sbg_<mode>_srl" |
4282 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
4283 | (IXOR:GPR | |
4284 | (lshiftrt:GPR | |
4285 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4286 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4287 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
4288 | (clobber (reg:CC CC_REGNUM))] | |
4289 | "TARGET_Z10" | |
576987fc | 4290 | "r<noxa>sbg\t%0,%1,<bitoff_plus>%2,63,64-%2" |
f3d90045 DV |
4291 | [(set_attr "op_type" "RIE")]) |
4292 | ||
5bb33936 RH |
4293 | ;; These two are generated by combine for s.bf &= val. |
4294 | ;; ??? For bitfields smaller than 32-bits, we wind up with SImode | |
4295 | ;; shifts and ands, which results in some truly awful patterns | |
4296 | ;; including subregs of operations. Rather unnecessisarily, IMO. | |
4297 | ;; Instead of | |
4298 | ;; | |
4299 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4300 | ;; (const_int 24 [0x18]) | |
4301 | ;; (const_int 0 [0])) | |
4302 | ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4303 | ;; (const_int 40 [0x28])) 4) | |
4304 | ;; (reg:SI 4 %r4 [ y+4 ])) 0)) | |
4305 | ;; | |
4306 | ;; we should instead generate | |
4307 | ;; | |
4308 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4309 | ;; (const_int 24 [0x18]) | |
4310 | ;; (const_int 0 [0])) | |
4311 | ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4312 | ;; (const_int 40 [0x28])) | |
4313 | ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0))) | |
4314 | ;; | |
4315 | ;; by noticing that we can push down the outer paradoxical subreg | |
4316 | ;; into the operation. | |
4317 | ||
4318 | (define_insn "*insv_rnsbg_noshift" | |
4319 | [(set (zero_extract:DI | |
4320 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4321 | (match_operand 1 "const_int_operand" "") | |
4322 | (match_operand 2 "const_int_operand" "")) | |
4323 | (and:DI | |
4324 | (match_dup 0) | |
4325 | (match_operand:DI 3 "nonimmediate_operand" "d"))) | |
4326 | (clobber (reg:CC CC_REGNUM))] | |
4327 | "TARGET_Z10 | |
0f6f72e8 | 4328 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
5bb33936 RH |
4329 | && INTVAL (operands[1]) + INTVAL (operands[2]) == 64" |
4330 | "rnsbg\t%0,%3,%2,63,0" | |
4331 | [(set_attr "op_type" "RIE")]) | |
4332 | ||
4333 | (define_insn "*insv_rnsbg_srl" | |
4334 | [(set (zero_extract:DI | |
4335 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4336 | (match_operand 1 "const_int_operand" "") | |
4337 | (match_operand 2 "const_int_operand" "")) | |
4338 | (and:DI | |
4339 | (lshiftrt:DI | |
4340 | (match_dup 0) | |
4341 | (match_operand 3 "const_int_operand" "")) | |
4342 | (match_operand:DI 4 "nonimmediate_operand" "d"))) | |
4343 | (clobber (reg:CC CC_REGNUM))] | |
4344 | "TARGET_Z10 | |
0f6f72e8 | 4345 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
5bb33936 RH |
4346 | && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])" |
4347 | "rnsbg\t%0,%4,%2,%2+%1-1,%3" | |
4348 | [(set_attr "op_type" "RIE")]) | |
4349 | ||
6fa05db6 | 4350 | (define_insn "*insv<mode>_mem_reg" |
9602b6a1 | 4351 | [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") |
6fa05db6 AS |
4352 | (match_operand 1 "const_int_operand" "n,n") |
4353 | (const_int 0)) | |
9602b6a1 | 4354 | (match_operand:W 2 "register_operand" "d,d"))] |
0f6f72e8 DV |
4355 | "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) |
4356 | && INTVAL (operands[1]) > 0 | |
6fa05db6 AS |
4357 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) |
4358 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4359 | { | |
4360 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4361 | ||
4362 | operands[1] = GEN_INT ((1ul << size) - 1); | |
9381e3f1 | 4363 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
4364 | : "stcmy\t%2,%1,%S0"; |
4365 | } | |
9381e3f1 | 4366 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 4367 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 4368 | (set_attr "z10prop" "z10_super,z10_super")]) |
6fa05db6 AS |
4369 | |
4370 | (define_insn "*insvdi_mem_reghigh" | |
3e4be43f | 4371 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S") |
6fa05db6 AS |
4372 | (match_operand 1 "const_int_operand" "n") |
4373 | (const_int 0)) | |
4374 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
4375 | (const_int 32)))] | |
9602b6a1 | 4376 | "TARGET_ZARCH |
0f6f72e8 | 4377 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) |
6fa05db6 AS |
4378 | && INTVAL (operands[1]) > 0 |
4379 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
4380 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4381 | { | |
4382 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4383 | ||
4384 | operands[1] = GEN_INT ((1ul << size) - 1); | |
4385 | return "stcmh\t%2,%1,%S0"; | |
4386 | } | |
9381e3f1 WG |
4387 | [(set_attr "op_type" "RSY") |
4388 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 | 4389 | |
9602b6a1 AK |
4390 | (define_insn "*insvdi_reg_imm" |
4391 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4392 | (const_int 16) | |
4393 | (match_operand 1 "const_int_operand" "n")) | |
4394 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6fa05db6 | 4395 | "TARGET_ZARCH |
0f6f72e8 | 4396 | && EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64) |
6fa05db6 AS |
4397 | && INTVAL (operands[1]) >= 0 |
4398 | && INTVAL (operands[1]) < BITS_PER_WORD | |
4399 | && INTVAL (operands[1]) % 16 == 0" | |
4400 | { | |
4401 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
4402 | { | |
4403 | case 64: return "iihh\t%0,%x2"; break; | |
4404 | case 48: return "iihl\t%0,%x2"; break; | |
4405 | case 32: return "iilh\t%0,%x2"; break; | |
4406 | case 16: return "iill\t%0,%x2"; break; | |
4407 | default: gcc_unreachable(); | |
4408 | } | |
4409 | } | |
9381e3f1 WG |
4410 | [(set_attr "op_type" "RI") |
4411 | (set_attr "z10prop" "z10_super_E1")]) | |
4412 | ||
9fec758d WG |
4413 | ; Update the left-most 32 bit of a DI. |
4414 | (define_insn "*insv_h_di_reg_extimm" | |
4415 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4416 | (const_int 32) | |
4417 | (const_int 0)) | |
4418 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4419 | "TARGET_EXTIMM" | |
4420 | "iihf\t%0,%o1" | |
4421 | [(set_attr "op_type" "RIL") | |
4422 | (set_attr "z10prop" "z10_fwd_E1")]) | |
6fa05db6 | 4423 | |
d378b983 RH |
4424 | ; Update the right-most 32 bit of a DI. |
4425 | (define_insn "*insv_l_di_reg_extimm" | |
4426 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4427 | (const_int 32) | |
4428 | (const_int 32)) | |
4429 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4430 | "TARGET_EXTIMM" | |
4431 | "iilf\t%0,%o1" | |
9381e3f1 | 4432 | [(set_attr "op_type" "RIL") |
9fec758d | 4433 | (set_attr "z10prop" "z10_fwd_A1")]) |
6fa05db6 | 4434 | |
9db1d521 HP |
4435 | ; |
4436 | ; extendsidi2 instruction pattern(s). | |
4437 | ; | |
4438 | ||
4023fb28 UW |
4439 | (define_expand "extendsidi2" |
4440 | [(set (match_operand:DI 0 "register_operand" "") | |
4441 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4442 | "" | |
4023fb28 | 4443 | { |
9602b6a1 | 4444 | if (!TARGET_ZARCH) |
4023fb28 | 4445 | { |
c41c1387 | 4446 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4447 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
4448 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
4449 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
4450 | DONE; |
4451 | } | |
ec24698e | 4452 | }) |
4023fb28 UW |
4453 | |
4454 | (define_insn "*extendsidi2" | |
963fc8d0 | 4455 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4456 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] |
9602b6a1 | 4457 | "TARGET_ZARCH" |
9db1d521 | 4458 | "@ |
d40c829f | 4459 | lgfr\t%0,%1 |
963fc8d0 AK |
4460 | lgf\t%0,%1 |
4461 | lgfrl\t%0,%1" | |
4462 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4463 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4464 | (set_attr "cpu_facility" "*,*,z10") |
4465 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4466 | |
9db1d521 | 4467 | ; |
56477c21 | 4468 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4469 | ; |
4470 | ||
56477c21 AS |
4471 | (define_expand "extend<HQI:mode><DSI:mode>2" |
4472 | [(set (match_operand:DSI 0 "register_operand" "") | |
4473 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 4474 | "" |
4023fb28 | 4475 | { |
9602b6a1 | 4476 | if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) |
4023fb28 UW |
4477 | { |
4478 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 4479 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
4480 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
4481 | DONE; | |
4482 | } | |
ec24698e | 4483 | else if (!TARGET_EXTIMM) |
4023fb28 | 4484 | { |
2542ef05 | 4485 | rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>); |
56477c21 AS |
4486 | |
4487 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
4488 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
4489 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
4490 | DONE; |
4491 | } | |
ec24698e UW |
4492 | }) |
4493 | ||
56477c21 AS |
4494 | ; |
4495 | ; extendhidi2 instruction pattern(s). | |
4496 | ; | |
4497 | ||
ec24698e | 4498 | (define_insn "*extendhidi2_extimm" |
963fc8d0 | 4499 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4500 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))] |
9602b6a1 | 4501 | "TARGET_ZARCH && TARGET_EXTIMM" |
ec24698e UW |
4502 | "@ |
4503 | lghr\t%0,%1 | |
963fc8d0 AK |
4504 | lgh\t%0,%1 |
4505 | lghrl\t%0,%1" | |
4506 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4507 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4508 | (set_attr "cpu_facility" "extimm,extimm,z10") |
4509 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
4510 | |
4511 | (define_insn "*extendhidi2" | |
9db1d521 | 4512 | [(set (match_operand:DI 0 "register_operand" "=d") |
3e4be43f | 4513 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))] |
9602b6a1 | 4514 | "TARGET_ZARCH" |
d40c829f | 4515 | "lgh\t%0,%1" |
9381e3f1 WG |
4516 | [(set_attr "op_type" "RXY") |
4517 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 4518 | |
9db1d521 | 4519 | ; |
56477c21 | 4520 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
4521 | ; |
4522 | ||
ec24698e | 4523 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
4524 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4525 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
4526 | "TARGET_EXTIMM" |
4527 | "@ | |
4528 | lhr\t%0,%1 | |
4529 | lh\t%0,%1 | |
963fc8d0 AK |
4530 | lhy\t%0,%1 |
4531 | lhrl\t%0,%1" | |
4532 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
4533 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 WG |
4534 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
4535 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4536 | |
4023fb28 | 4537 | (define_insn "*extendhisi2" |
d3632d41 UW |
4538 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4539 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 4540 | "!TARGET_EXTIMM" |
d3632d41 | 4541 | "@ |
d40c829f UW |
4542 | lh\t%0,%1 |
4543 | lhy\t%0,%1" | |
9381e3f1 | 4544 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 4545 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 4546 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 | 4547 | |
56477c21 AS |
4548 | ; |
4549 | ; extendqi(si|di)2 instruction pattern(s). | |
4550 | ; | |
4551 | ||
43a09b63 | 4552 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
4553 | (define_insn "*extendqi<mode>2_extimm" |
4554 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3e4be43f | 4555 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))] |
ec24698e UW |
4556 | "TARGET_EXTIMM" |
4557 | "@ | |
56477c21 AS |
4558 | l<g>br\t%0,%1 |
4559 | l<g>b\t%0,%1" | |
9381e3f1 WG |
4560 | [(set_attr "op_type" "RRE,RXY") |
4561 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 4562 | |
43a09b63 | 4563 | ; lb, lgb |
56477c21 AS |
4564 | (define_insn "*extendqi<mode>2" |
4565 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 4566 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))] |
56477c21 AS |
4567 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
4568 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
4569 | [(set_attr "op_type" "RXY") |
4570 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 4571 | |
56477c21 AS |
4572 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
4573 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4574 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 4575 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 4576 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
4577 | "#" |
4578 | "&& reload_completed" | |
4023fb28 | 4579 | [(parallel |
56477c21 | 4580 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 4581 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 4582 | (parallel |
56477c21 | 4583 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 4584 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
4585 | { |
4586 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4587 | set_mem_size (operands[1], GET_MODE_SIZE (QImode)); |
2542ef05 | 4588 | operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT); |
6fa05db6 | 4589 | }) |
9db1d521 | 4590 | |
9db1d521 HP |
4591 | ; |
4592 | ; zero_extendsidi2 instruction pattern(s). | |
4593 | ; | |
4594 | ||
4023fb28 UW |
4595 | (define_expand "zero_extendsidi2" |
4596 | [(set (match_operand:DI 0 "register_operand" "") | |
4597 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4598 | "" | |
4023fb28 | 4599 | { |
9602b6a1 | 4600 | if (!TARGET_ZARCH) |
4023fb28 | 4601 | { |
c41c1387 | 4602 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4603 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
4604 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
4605 | DONE; |
4606 | } | |
ec24698e | 4607 | }) |
4023fb28 UW |
4608 | |
4609 | (define_insn "*zero_extendsidi2" | |
963fc8d0 | 4610 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4611 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] |
9602b6a1 | 4612 | "TARGET_ZARCH" |
9db1d521 | 4613 | "@ |
d40c829f | 4614 | llgfr\t%0,%1 |
963fc8d0 AK |
4615 | llgf\t%0,%1 |
4616 | llgfrl\t%0,%1" | |
4617 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4618 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4619 | (set_attr "cpu_facility" "*,*,z10") |
4620 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) | |
9db1d521 | 4621 | |
288e517f AK |
4622 | ; |
4623 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
4624 | ; | |
4625 | ||
d6083c7d UW |
4626 | (define_insn "*llgt_sidi" |
4627 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 4628 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) |
d6083c7d | 4629 | (const_int 2147483647)))] |
9602b6a1 | 4630 | "TARGET_ZARCH" |
d6083c7d | 4631 | "llgt\t%0,%1" |
9381e3f1 WG |
4632 | [(set_attr "op_type" "RXE") |
4633 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
4634 | |
4635 | (define_insn_and_split "*llgt_sidi_split" | |
4636 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 4637 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) |
d6083c7d | 4638 | (const_int 2147483647))) |
ae156f85 | 4639 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4640 | "TARGET_ZARCH" |
d6083c7d UW |
4641 | "#" |
4642 | "&& reload_completed" | |
4643 | [(set (match_dup 0) | |
4644 | (and:DI (subreg:DI (match_dup 1) 0) | |
4645 | (const_int 2147483647)))] | |
4646 | "") | |
4647 | ||
288e517f AK |
4648 | (define_insn "*llgt_sisi" |
4649 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 4650 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T") |
288e517f | 4651 | (const_int 2147483647)))] |
c4d50129 | 4652 | "TARGET_ZARCH" |
288e517f AK |
4653 | "@ |
4654 | llgtr\t%0,%1 | |
4655 | llgt\t%0,%1" | |
9381e3f1 WG |
4656 | [(set_attr "op_type" "RRE,RXE") |
4657 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4658 | |
288e517f AK |
4659 | (define_insn "*llgt_didi" |
4660 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4661 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
4662 | (const_int 2147483647)))] | |
9602b6a1 | 4663 | "TARGET_ZARCH" |
288e517f AK |
4664 | "@ |
4665 | llgtr\t%0,%1 | |
4666 | llgt\t%0,%N1" | |
9381e3f1 WG |
4667 | [(set_attr "op_type" "RRE,RXE") |
4668 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4669 | |
f19a9af7 | 4670 | (define_split |
9602b6a1 AK |
4671 | [(set (match_operand:DSI 0 "register_operand" "") |
4672 | (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") | |
f6ee577c | 4673 | (const_int 2147483647))) |
ae156f85 | 4674 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 4675 | "TARGET_ZARCH && reload_completed" |
288e517f | 4676 | [(set (match_dup 0) |
9602b6a1 | 4677 | (and:DSI (match_dup 1) |
f6ee577c | 4678 | (const_int 2147483647)))] |
288e517f AK |
4679 | "") |
4680 | ||
9db1d521 | 4681 | ; |
56477c21 | 4682 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4683 | ; |
4684 | ||
56477c21 AS |
4685 | (define_expand "zero_extend<mode>di2" |
4686 | [(set (match_operand:DI 0 "register_operand" "") | |
4687 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4688 | "" | |
4689 | { | |
9602b6a1 | 4690 | if (!TARGET_ZARCH) |
56477c21 AS |
4691 | { |
4692 | rtx tmp = gen_reg_rtx (SImode); | |
4693 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
4694 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
4695 | DONE; | |
4696 | } | |
4697 | else if (!TARGET_EXTIMM) | |
4698 | { | |
2542ef05 | 4699 | rtx bitcount = GEN_INT (64 - <HQI:bitsize>); |
56477c21 AS |
4700 | operands[1] = gen_lowpart (DImode, operands[1]); |
4701 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
4702 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
4703 | DONE; | |
4704 | } | |
4705 | }) | |
4706 | ||
f6ee577c | 4707 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 4708 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 4709 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 4710 | "" |
4023fb28 | 4711 | { |
ec24698e UW |
4712 | if (!TARGET_EXTIMM) |
4713 | { | |
4714 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 4715 | emit_insn (gen_andsi3 (operands[0], operands[1], |
2542ef05 | 4716 | GEN_INT ((1 << <HQI:bitsize>) - 1))); |
ec24698e | 4717 | DONE; |
56477c21 | 4718 | } |
ec24698e UW |
4719 | }) |
4720 | ||
963fc8d0 AK |
4721 | ; llhrl, llghrl |
4722 | (define_insn "*zero_extendhi<mode>2_z10" | |
4723 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
3e4be43f | 4724 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))] |
963fc8d0 AK |
4725 | "TARGET_Z10" |
4726 | "@ | |
4727 | ll<g>hr\t%0,%1 | |
4728 | ll<g>h\t%0,%1 | |
4729 | ll<g>hrl\t%0,%1" | |
4730 | [(set_attr "op_type" "RXY,RRE,RIL") | |
4731 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4732 | (set_attr "cpu_facility" "*,*,z10") |
729e750f | 4733 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) |
963fc8d0 | 4734 | |
43a09b63 | 4735 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
4736 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
4737 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3e4be43f | 4738 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))] |
ec24698e UW |
4739 | "TARGET_EXTIMM" |
4740 | "@ | |
56477c21 AS |
4741 | ll<g><hc>r\t%0,%1 |
4742 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
4743 | [(set_attr "op_type" "RRE,RXY") |
4744 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 4745 | |
43a09b63 | 4746 | ; llgh, llgc |
56477c21 AS |
4747 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
4748 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 4749 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))] |
ec24698e | 4750 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 4751 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
4752 | [(set_attr "op_type" "RXY") |
4753 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
4754 | |
4755 | (define_insn_and_split "*zero_extendhisi2_31" | |
4756 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3e4be43f | 4757 | (zero_extend:SI (match_operand:HI 1 "s_operand" "S"))) |
ae156f85 | 4758 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 4759 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4760 | "#" |
4761 | "&& reload_completed" | |
4762 | [(set (match_dup 0) (const_int 0)) | |
4763 | (parallel | |
4764 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 4765 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4766 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 4767 | |
cc7ab9b7 UW |
4768 | (define_insn_and_split "*zero_extendqisi2_31" |
4769 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3e4be43f | 4770 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))] |
9e8327e3 | 4771 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4772 | "#" |
4773 | "&& reload_completed" | |
4774 | [(set (match_dup 0) (const_int 0)) | |
4775 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4776 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 4777 | |
9db1d521 HP |
4778 | ; |
4779 | ; zero_extendqihi2 instruction pattern(s). | |
4780 | ; | |
4781 | ||
9db1d521 HP |
4782 | (define_expand "zero_extendqihi2" |
4783 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 4784 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 4785 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 4786 | { |
4023fb28 UW |
4787 | operands[1] = gen_lowpart (HImode, operands[1]); |
4788 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
4789 | DONE; | |
ec24698e | 4790 | }) |
9db1d521 | 4791 | |
4023fb28 | 4792 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 4793 | [(set (match_operand:HI 0 "register_operand" "=d") |
3e4be43f | 4794 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] |
ec24698e | 4795 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 4796 | "llgc\t%0,%1" |
9381e3f1 WG |
4797 | [(set_attr "op_type" "RXY") |
4798 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 4799 | |
cc7ab9b7 UW |
4800 | (define_insn_and_split "*zero_extendqihi2_31" |
4801 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
3e4be43f | 4802 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] |
9e8327e3 | 4803 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4804 | "#" |
4805 | "&& reload_completed" | |
4806 | [(set (match_dup 0) (const_int 0)) | |
4807 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4808 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 4809 | |
609e7e80 | 4810 | ; |
9751ad6e | 4811 | ; fixuns_trunc(dd|td|sf|df|tf)(si|di)2 expander |
609e7e80 AK |
4812 | ; |
4813 | ||
9751ad6e AK |
4814 | ; This is the only entry point for fixuns_trunc. It multiplexes the |
4815 | ; expansion to either the *_emu expanders below for pre z196 machines | |
4816 | ; or emits the default pattern otherwise. | |
4817 | (define_expand "fixuns_trunc<FP:mode><GPR:mode>2" | |
609e7e80 | 4818 | [(parallel |
9751ad6e AK |
4819 | [(set (match_operand:GPR 0 "register_operand" "") |
4820 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" ""))) | |
4821 | (unspec:GPR [(match_dup 2)] UNSPEC_ROUND) | |
65b1d8ea | 4822 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e | 4823 | "TARGET_HARD_FLOAT" |
609e7e80 | 4824 | { |
65b1d8ea AK |
4825 | if (!TARGET_Z196) |
4826 | { | |
9751ad6e AK |
4827 | /* We don't provide emulation for TD|DD->SI. */ |
4828 | if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT | |
4829 | && <GPR:MODE>mode == SImode) | |
4830 | FAIL; | |
4831 | emit_insn (gen_fixuns_trunc<FP:mode><GPR:mode>2_emu (operands[0], | |
4832 | operands[1])); | |
65b1d8ea AK |
4833 | DONE; |
4834 | } | |
9751ad6e AK |
4835 | |
4836 | if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT) | |
4837 | operands[2] = GEN_INT (DFP_RND_TOWARD_0); | |
4838 | else | |
4839 | operands[2] = GEN_INT (BFP_RND_TOWARD_0); | |
609e7e80 AK |
4840 | }) |
4841 | ||
9751ad6e AK |
4842 | ; (sf|df|tf)->unsigned (si|di) |
4843 | ||
4844 | ; Emulate the unsigned conversion with the signed version for pre z196 | |
4845 | ; machines. | |
4846 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2_emu" | |
4847 | [(parallel | |
4848 | [(set (match_operand:GPR 0 "register_operand" "") | |
4849 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) | |
4850 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) | |
4851 | (clobber (reg:CC CC_REGNUM))])] | |
4852 | "!TARGET_Z196 && TARGET_HARD_FLOAT" | |
4853 | { | |
4854 | rtx_code_label *label1 = gen_label_rtx (); | |
4855 | rtx_code_label *label2 = gen_label_rtx (); | |
4856 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); | |
4857 | REAL_VALUE_TYPE cmp, sub; | |
4858 | ||
4859 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); | |
4860 | real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode); | |
4861 | real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode); | |
4862 | ||
4863 | emit_cmp_and_jump_insns (operands[1], | |
4864 | const_double_from_real_value (cmp, <BFP:MODE>mode), | |
4865 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4866 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], | |
4867 | const_double_from_real_value (sub, <BFP:MODE>mode))); | |
4868 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, | |
4869 | GEN_INT (BFP_RND_TOWARD_MINF))); | |
4870 | emit_jump (label2); | |
4871 | ||
4872 | emit_label (label1); | |
4873 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], | |
4874 | operands[1], | |
4875 | GEN_INT (BFP_RND_TOWARD_0))); | |
4876 | emit_label (label2); | |
4877 | DONE; | |
4878 | }) | |
4879 | ||
4880 | ; dd->unsigned di | |
4881 | ||
4882 | ; Emulate the unsigned conversion with the signed version for pre z196 | |
4883 | ; machines. | |
4884 | (define_expand "fixuns_truncdddi2_emu" | |
65b1d8ea AK |
4885 | [(parallel |
4886 | [(set (match_operand:DI 0 "register_operand" "") | |
9751ad6e | 4887 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) |
ae8e301e | 4888 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea AK |
4889 | (clobber (reg:CC CC_REGNUM))])] |
4890 | ||
9751ad6e | 4891 | "!TARGET_Z196 && TARGET_HARD_DFP" |
609e7e80 | 4892 | { |
9751ad6e AK |
4893 | rtx_code_label *label1 = gen_label_rtx (); |
4894 | rtx_code_label *label2 = gen_label_rtx (); | |
4895 | rtx temp = gen_reg_rtx (TDmode); | |
4896 | REAL_VALUE_TYPE cmp, sub; | |
4897 | ||
4898 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4899 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4900 | ||
4901 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
4902 | solution is doing the check and the subtraction in TD mode and using a | |
4903 | TD -> DI convert afterwards. */ | |
4904 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
4905 | temp = force_reg (TDmode, temp); | |
4906 | emit_cmp_and_jump_insns (temp, | |
4907 | const_double_from_real_value (cmp, TDmode), | |
4908 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4909 | emit_insn (gen_subtd3 (temp, temp, | |
4910 | const_double_from_real_value (sub, TDmode))); | |
4911 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, | |
4912 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
4913 | emit_jump (label2); | |
4914 | ||
4915 | emit_label (label1); | |
4916 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], | |
4917 | GEN_INT (DFP_RND_TOWARD_0))); | |
4918 | emit_label (label2); | |
4919 | DONE; | |
609e7e80 | 4920 | }) |
cc7ab9b7 | 4921 | |
9751ad6e | 4922 | ; td->unsigned di |
9db1d521 | 4923 | |
9751ad6e AK |
4924 | ; Emulate the unsigned conversion with the signed version for pre z196 |
4925 | ; machines. | |
4926 | (define_expand "fixuns_trunctddi2_emu" | |
65b1d8ea | 4927 | [(parallel |
9751ad6e AK |
4928 | [(set (match_operand:DI 0 "register_operand" "") |
4929 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) | |
4930 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) | |
65b1d8ea | 4931 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e AK |
4932 | |
4933 | "!TARGET_Z196 && TARGET_HARD_DFP" | |
9db1d521 | 4934 | { |
9751ad6e AK |
4935 | rtx_code_label *label1 = gen_label_rtx (); |
4936 | rtx_code_label *label2 = gen_label_rtx (); | |
4937 | rtx temp = gen_reg_rtx (TDmode); | |
4938 | REAL_VALUE_TYPE cmp, sub; | |
4939 | ||
4940 | operands[1] = force_reg (TDmode, operands[1]); | |
4941 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4942 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4943 | ||
4944 | emit_cmp_and_jump_insns (operands[1], | |
4945 | const_double_from_real_value (cmp, TDmode), | |
4946 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4947 | emit_insn (gen_subtd3 (temp, operands[1], | |
4948 | const_double_from_real_value (sub, TDmode))); | |
4949 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, | |
4950 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
4951 | emit_jump (label2); | |
4952 | ||
4953 | emit_label (label1); | |
4954 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], | |
4955 | GEN_INT (DFP_RND_TOWARD_0))); | |
4956 | emit_label (label2); | |
4957 | DONE; | |
10bbf137 | 4958 | }) |
9db1d521 | 4959 | |
9751ad6e AK |
4960 | ; Just a dummy to make the code in the first expander a bit easier. |
4961 | (define_expand "fixuns_trunc<mode>si2_emu" | |
65b1d8ea AK |
4962 | [(parallel |
4963 | [(set (match_operand:SI 0 "register_operand" "") | |
4964 | (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) | |
9751ad6e | 4965 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea | 4966 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e AK |
4967 | |
4968 | "!TARGET_Z196 && TARGET_HARD_DFP" | |
4969 | { | |
4970 | FAIL; | |
4971 | }) | |
4972 | ||
65b1d8ea AK |
4973 | |
4974 | ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. | |
4975 | ||
9751ad6e AK |
4976 | ; df -> unsigned di |
4977 | (define_insn "*fixuns_truncdfdi2_vx" | |
6e5b5de8 AK |
4978 | [(set (match_operand:DI 0 "register_operand" "=d,v") |
4979 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
4980 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
4981 | (clobber (reg:CC CC_REGNUM))] | |
9751ad6e AK |
4982 | "TARGET_VX && TARGET_HARD_FLOAT" |
4983 | "@ | |
4984 | clgdbr\t%0,%h2,%1,0 | |
4985 | wclgdb\t%v0,%v1,0,%h2" | |
4986 | [(set_attr "op_type" "RRF,VRR") | |
4987 | (set_attr "type" "ftoi")]) | |
6e5b5de8 | 4988 | |
9751ad6e | 4989 | ; (dd|td|sf|df|tf)->unsigned (di|si) |
65b1d8ea AK |
4990 | ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr |
4991 | ; clfdtr, clfxtr, clgdtr, clgxtr | |
4992 | (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" | |
6e5b5de8 AK |
4993 | [(set (match_operand:GPR 0 "register_operand" "=d") |
4994 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) | |
4995 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
65b1d8ea | 4996 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 | 4997 | "TARGET_Z196 && TARGET_HARD_FLOAT |
a579871b | 4998 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)" |
65b1d8ea AK |
4999 | "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" |
5000 | [(set_attr "op_type" "RRF") | |
5001 | (set_attr "type" "ftoi")]) | |
5002 | ||
b60cb710 AK |
5003 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
5004 | [(set (match_operand:GPR 0 "register_operand" "") | |
5005 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
5006 | "TARGET_HARD_FLOAT" | |
9db1d521 | 5007 | { |
b60cb710 | 5008 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
ae8e301e | 5009 | GEN_INT (BFP_RND_TOWARD_0))); |
9db1d521 | 5010 | DONE; |
10bbf137 | 5011 | }) |
9db1d521 | 5012 | |
6e5b5de8 AK |
5013 | (define_insn "*fix_truncdfdi2_bfp_z13" |
5014 | [(set (match_operand:DI 0 "register_operand" "=d,v") | |
5015 | (fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
5016 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
5017 | (clobber (reg:CC CC_REGNUM))] | |
a579871b | 5018 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5019 | "@ |
5020 | cgdbr\t%0,%h2,%1 | |
5021 | wcgdb\t%v0,%v1,0,%h2" | |
5022 | [(set_attr "op_type" "RRE,VRR") | |
5023 | (set_attr "type" "ftoi")]) | |
5024 | ||
43a09b63 | 5025 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
6e5b5de8 AK |
5026 | (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp" |
5027 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5028 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
5029 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
ae156f85 | 5030 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 AK |
5031 | "TARGET_HARD_FLOAT |
5032 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)" | |
7b6baae1 | 5033 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 5034 | [(set_attr "op_type" "RRE") |
077dab3b | 5035 | (set_attr "type" "ftoi")]) |
9db1d521 | 5036 | |
6e5b5de8 AK |
5037 | (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
5038 | [(parallel | |
5039 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5040 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
5041 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
5042 | (clobber (reg:CC CC_REGNUM))])] | |
5043 | "TARGET_HARD_FLOAT") | |
609e7e80 AK |
5044 | ; |
5045 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
5046 | ; | |
5047 | ||
99cd7dd0 AK |
5048 | (define_expand "fix_trunc<mode>di2" |
5049 | [(set (match_operand:DI 0 "register_operand" "") | |
5050 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
9602b6a1 | 5051 | "TARGET_ZARCH && TARGET_HARD_DFP" |
99cd7dd0 AK |
5052 | { |
5053 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
5054 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
ae8e301e | 5055 | GEN_INT (DFP_RND_TOWARD_0))); |
99cd7dd0 AK |
5056 | DONE; |
5057 | }) | |
5058 | ||
609e7e80 | 5059 | ; cgxtr, cgdtr |
99cd7dd0 | 5060 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
5061 | [(set (match_operand:DI 0 "register_operand" "=d") |
5062 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
5063 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
5064 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 5065 | "TARGET_ZARCH && TARGET_HARD_DFP" |
609e7e80 AK |
5066 | "cg<DFP:xde>tr\t%0,%h2,%1" |
5067 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 5068 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
5069 | |
5070 | ||
f61a2c7d AK |
5071 | ; |
5072 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
5073 | ; | |
5074 | ||
5075 | (define_expand "fix_trunctf<mode>2" | |
5076 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
5077 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
ae8e301e | 5078 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) |
f61a2c7d | 5079 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5080 | "TARGET_HARD_FLOAT" |
142cd70f | 5081 | "") |
9db1d521 | 5082 | |
9db1d521 | 5083 | |
9db1d521 | 5084 | ; |
142cd70f | 5085 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
5086 | ; |
5087 | ||
609e7e80 | 5088 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 5089 | (define_insn "floatdi<mode>2" |
62d3f261 AK |
5090 | [(set (match_operand:FP 0 "register_operand" "=f,v") |
5091 | (float:FP (match_operand:DI 1 "register_operand" "d,v")))] | |
9602b6a1 | 5092 | "TARGET_ZARCH && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5093 | "@ |
5094 | c<xde>g<bt>r\t%0,%1 | |
5095 | wcdgb\t%v0,%v1,0,0" | |
5096 | [(set_attr "op_type" "RRE,VRR") | |
5097 | (set_attr "type" "itof<mode>" ) | |
285363a1 | 5098 | (set_attr "cpu_facility" "*,vx") |
62d3f261 | 5099 | (set_attr "enabled" "*,<DFDI>")]) |
9db1d521 | 5100 | |
43a09b63 | 5101 | ; cxfbr, cdfbr, cefbr |
142cd70f | 5102 | (define_insn "floatsi<mode>2" |
7b6baae1 AK |
5103 | [(set (match_operand:BFP 0 "register_operand" "=f") |
5104 | (float:BFP (match_operand:SI 1 "register_operand" "d")))] | |
142cd70f | 5105 | "TARGET_HARD_FLOAT" |
f61a2c7d AK |
5106 | "c<xde>fbr\t%0,%1" |
5107 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 5108 | (set_attr "type" "itof<mode>" )]) |
f61a2c7d | 5109 | |
65b1d8ea AK |
5110 | ; cxftr, cdftr |
5111 | (define_insn "floatsi<mode>2" | |
5112 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5113 | (float:DFP (match_operand:SI 1 "register_operand" "d")))] | |
5114 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
5115 | "c<xde>ftr\t%0,0,%1,0" | |
5116 | [(set_attr "op_type" "RRE") | |
5117 | (set_attr "type" "itof<mode>" )]) | |
5118 | ||
5119 | ; | |
5120 | ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). | |
5121 | ; | |
5122 | ||
6e5b5de8 AK |
5123 | (define_insn "*floatunsdidf2_z13" |
5124 | [(set (match_operand:DF 0 "register_operand" "=f,v") | |
5125 | (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))] | |
a579871b | 5126 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5127 | "@ |
5128 | cdlgbr\t%0,0,%1,0 | |
5129 | wcdlgb\t%v0,%v1,0,0" | |
5130 | [(set_attr "op_type" "RRE,VRR") | |
5131 | (set_attr "type" "itofdf")]) | |
5132 | ||
65b1d8ea AK |
5133 | ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr |
5134 | ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr | |
6e5b5de8 AK |
5135 | (define_insn "*floatuns<GPR:mode><FP:mode>2" |
5136 | [(set (match_operand:FP 0 "register_operand" "=f") | |
5137 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] | |
5138 | "TARGET_Z196 && TARGET_HARD_FLOAT | |
5139 | && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)" | |
65b1d8ea AK |
5140 | "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" |
5141 | [(set_attr "op_type" "RRE") | |
6e5b5de8 AK |
5142 | (set_attr "type" "itof<FP:mode>")]) |
5143 | ||
5144 | (define_expand "floatuns<GPR:mode><FP:mode>2" | |
5145 | [(set (match_operand:FP 0 "register_operand" "") | |
5146 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))] | |
5147 | "TARGET_Z196 && TARGET_HARD_FLOAT") | |
f61a2c7d | 5148 | |
9db1d521 HP |
5149 | ; |
5150 | ; truncdfsf2 instruction pattern(s). | |
5151 | ; | |
5152 | ||
142cd70f | 5153 | (define_insn "truncdfsf2" |
6e5b5de8 AK |
5154 | [(set (match_operand:SF 0 "register_operand" "=f,v") |
5155 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))] | |
142cd70f | 5156 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5157 | "@ |
5158 | ledbr\t%0,%1 | |
5159 | wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed | |
5160 | ; According to BFP rounding mode | |
5161 | [(set_attr "op_type" "RRE,VRR") | |
5162 | (set_attr "type" "ftruncdf") | |
285363a1 | 5163 | (set_attr "cpu_facility" "*,vx")]) |
9db1d521 | 5164 | |
f61a2c7d | 5165 | ; |
142cd70f | 5166 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
5167 | ; |
5168 | ||
142cd70f AK |
5169 | ; ldxbr, lexbr |
5170 | (define_insn "trunctf<mode>2" | |
5171 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
5172 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 5173 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
5174 | "TARGET_HARD_FLOAT" |
5175 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 5176 | [(set_attr "length" "6") |
9381e3f1 | 5177 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 5178 | |
609e7e80 AK |
5179 | ; |
5180 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
5181 | ; | |
5182 | ||
432d4670 AK |
5183 | |
5184 | (define_expand "trunctddd2" | |
5185 | [(parallel | |
5186 | [(set (match_operand:DD 0 "register_operand" "") | |
5187 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) | |
5188 | (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND) | |
5189 | (clobber (scratch:TD))])] | |
5190 | "TARGET_HARD_DFP") | |
5191 | ||
5192 | (define_insn "*trunctddd2" | |
609e7e80 | 5193 | [(set (match_operand:DD 0 "register_operand" "=f") |
bf259a77 | 5194 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
432d4670 AK |
5195 | (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND) |
5196 | (clobber (match_scratch:TD 3 "=f"))] | |
fb068247 | 5197 | "TARGET_HARD_DFP" |
432d4670 | 5198 | "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3" |
bf259a77 | 5199 | [(set_attr "length" "6") |
9381e3f1 | 5200 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
5201 | |
5202 | (define_insn "truncddsd2" | |
5203 | [(set (match_operand:SD 0 "register_operand" "=f") | |
5204 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 5205 | "TARGET_HARD_DFP" |
609e7e80 AK |
5206 | "ledtr\t%0,0,%1,0" |
5207 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 5208 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 5209 | |
feade5a8 AK |
5210 | (define_expand "trunctdsd2" |
5211 | [(parallel | |
d5a216fa | 5212 | [(set (match_dup 2) |
feade5a8 | 5213 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) |
432d4670 | 5214 | (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND) |
d5a216fa | 5215 | (clobber (match_scratch:TD 3 ""))]) |
feade5a8 | 5216 | (set (match_operand:SD 0 "register_operand" "") |
d5a216fa | 5217 | (float_truncate:SD (match_dup 2)))] |
feade5a8 AK |
5218 | "TARGET_HARD_DFP" |
5219 | { | |
d5a216fa | 5220 | operands[2] = gen_reg_rtx (DDmode); |
feade5a8 AK |
5221 | }) |
5222 | ||
9db1d521 | 5223 | ; |
142cd70f | 5224 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
5225 | ; |
5226 | ||
2de2b3f9 | 5227 | ; wflls |
6e5b5de8 AK |
5228 | (define_insn "*extendsfdf2_z13" |
5229 | [(set (match_operand:DF 0 "register_operand" "=f,f,v") | |
5230 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))] | |
a579871b | 5231 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5232 | "@ |
5233 | ldebr\t%0,%1 | |
5234 | ldeb\t%0,%1 | |
5235 | wldeb\t%v0,%v1" | |
5236 | [(set_attr "op_type" "RRE,RXE,VRR") | |
5237 | (set_attr "type" "fsimpdf, floaddf,fsimpdf")]) | |
5238 | ||
142cd70f | 5239 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
6e5b5de8 AK |
5240 | (define_insn "*extend<DSF:mode><BFP:mode>2" |
5241 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
142cd70f AK |
5242 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] |
5243 | "TARGET_HARD_FLOAT | |
6e5b5de8 AK |
5244 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode) |
5245 | && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)" | |
f61a2c7d | 5246 | "@ |
142cd70f AK |
5247 | l<BFP:xde><DSF:xde>br\t%0,%1 |
5248 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
6e5b5de8 AK |
5249 | [(set_attr "op_type" "RRE,RXE") |
5250 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) | |
5251 | ||
5252 | (define_expand "extend<DSF:mode><BFP:mode>2" | |
5253 | [(set (match_operand:BFP 0 "register_operand" "") | |
5254 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))] | |
5255 | "TARGET_HARD_FLOAT | |
5256 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)") | |
f61a2c7d | 5257 | |
609e7e80 AK |
5258 | ; |
5259 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
5260 | ; | |
5261 | ||
5262 | (define_insn "extendddtd2" | |
5263 | [(set (match_operand:TD 0 "register_operand" "=f") | |
5264 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 5265 | "TARGET_HARD_DFP" |
609e7e80 AK |
5266 | "lxdtr\t%0,%1,0" |
5267 | [(set_attr "op_type" "RRF") | |
5268 | (set_attr "type" "fsimptf")]) | |
5269 | ||
5270 | (define_insn "extendsddd2" | |
5271 | [(set (match_operand:DD 0 "register_operand" "=f") | |
5272 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 5273 | "TARGET_HARD_DFP" |
609e7e80 AK |
5274 | "ldetr\t%0,%1,0" |
5275 | [(set_attr "op_type" "RRF") | |
5276 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 5277 | |
feade5a8 AK |
5278 | (define_expand "extendsdtd2" |
5279 | [(set (match_dup 2) | |
5280 | (float_extend:DD (match_operand:SD 1 "register_operand" ""))) | |
5281 | (set (match_operand:TD 0 "register_operand" "") | |
5282 | (float_extend:TD (match_dup 2)))] | |
5283 | "TARGET_HARD_DFP" | |
5284 | { | |
5285 | operands[2] = gen_reg_rtx (DDmode); | |
5286 | }) | |
5287 | ||
d12a76f3 AK |
5288 | ; Binary Floating Point - load fp integer |
5289 | ||
5290 | ; Expanders for: floor, btrunc, round, ceil, and nearbyint | |
5291 | ; For all of them the inexact exceptions are suppressed. | |
5292 | ||
5293 | ; fiebra, fidbra, fixbra | |
5294 | (define_insn "<FPINT:fpint_name><BFP:mode>2" | |
5295 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
5296 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
5297 | FPINT))] | |
5298 | "TARGET_Z196" | |
5299 | "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
5300 | [(set_attr "op_type" "RRF") | |
5301 | (set_attr "type" "fsimp<BFP:mode>")]) | |
5302 | ||
5303 | ; rint is supposed to raise an inexact exception so we can use the | |
5304 | ; older instructions. | |
5305 | ||
5306 | ; fiebr, fidbr, fixbr | |
5307 | (define_insn "rint<BFP:mode>2" | |
5308 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
5309 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
5310 | UNSPEC_FPINT_RINT))] | |
5311 | "" | |
5312 | "fi<BFP:xde>br\t%0,0,%1" | |
5313 | [(set_attr "op_type" "RRF") | |
5314 | (set_attr "type" "fsimp<BFP:mode>")]) | |
5315 | ||
5316 | ||
5317 | ; Decimal Floating Point - load fp integer | |
5318 | ||
5319 | ; fidtr, fixtr | |
5320 | (define_insn "<FPINT:fpint_name><DFP:mode>2" | |
5321 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5322 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5323 | FPINT))] | |
5324 | "TARGET_HARD_DFP" | |
5325 | "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
5326 | [(set_attr "op_type" "RRF") | |
5327 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5328 | ||
5329 | ; fidtr, fixtr | |
5330 | (define_insn "rint<DFP:mode>2" | |
5331 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5332 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5333 | UNSPEC_FPINT_RINT))] | |
5334 | "TARGET_HARD_DFP" | |
5335 | "fi<DFP:xde>tr\t%0,0,%1,0" | |
5336 | [(set_attr "op_type" "RRF") | |
5337 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5338 | ||
5339 | ; | |
35dd9a0e AK |
5340 | ; Binary <-> Decimal floating point trunc patterns |
5341 | ; | |
5342 | ||
5343 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
5344 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5345 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5346 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5347 | (clobber (reg:CC CC_REGNUM)) |
5348 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5349 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5350 | "pfpo") |
5351 | ||
5352 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
5353 | [(set (reg:BFP FPR0_REGNUM) | |
2cf4c39e | 5354 | (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5355 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5356 | (clobber (reg:CC CC_REGNUM)) |
5357 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5358 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5359 | "pfpo") |
5360 | ||
5361 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5362 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5363 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5364 | (parallel | |
5365 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5366 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5367 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5368 | (clobber (reg:CC CC_REGNUM)) |
5369 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5370 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5371 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5372 | "TARGET_HARD_DFP |
35dd9a0e AK |
5373 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5374 | { | |
5375 | HOST_WIDE_INT flags; | |
5376 | ||
5377 | flags = (PFPO_CONVERT | | |
5378 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5379 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5380 | ||
5381 | operands[2] = GEN_INT (flags); | |
5382 | }) | |
5383 | ||
5384 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5385 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5386 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5387 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5388 | (parallel | |
2cf4c39e | 5389 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5390 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5391 | (clobber (reg:CC CC_REGNUM)) |
5392 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5393 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5394 | "TARGET_HARD_DFP |
35dd9a0e AK |
5395 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
5396 | { | |
5397 | HOST_WIDE_INT flags; | |
5398 | ||
5399 | flags = (PFPO_CONVERT | | |
5400 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5401 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5402 | ||
5403 | operands[2] = GEN_INT (flags); | |
5404 | }) | |
5405 | ||
5406 | ; | |
5407 | ; Binary <-> Decimal floating point extend patterns | |
5408 | ; | |
5409 | ||
5410 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5411 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5412 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5413 | (clobber (reg:CC CC_REGNUM)) |
5414 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5415 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5416 | "pfpo") |
5417 | ||
5418 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5419 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5420 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5421 | (clobber (reg:CC CC_REGNUM)) |
5422 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5423 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5424 | "pfpo") |
5425 | ||
5426 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5427 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5428 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5429 | (parallel | |
5430 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5431 | (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5432 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5433 | (clobber (reg:CC CC_REGNUM)) |
5434 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5435 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5436 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5437 | "TARGET_HARD_DFP |
35dd9a0e AK |
5438 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5439 | { | |
5440 | HOST_WIDE_INT flags; | |
5441 | ||
5442 | flags = (PFPO_CONVERT | | |
5443 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5444 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5445 | ||
5446 | operands[2] = GEN_INT (flags); | |
5447 | }) | |
5448 | ||
5449 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5450 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5451 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5452 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5453 | (parallel | |
2cf4c39e | 5454 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5455 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5456 | (clobber (reg:CC CC_REGNUM)) |
5457 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5458 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5459 | "TARGET_HARD_DFP |
35dd9a0e AK |
5460 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
5461 | { | |
5462 | HOST_WIDE_INT flags; | |
5463 | ||
5464 | flags = (PFPO_CONVERT | | |
5465 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5466 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5467 | ||
5468 | operands[2] = GEN_INT (flags); | |
5469 | }) | |
5470 | ||
5471 | ||
9db1d521 | 5472 | ;; |
fae778eb | 5473 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 5474 | ;; |
fae778eb | 5475 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
5476 | ; because of unpredictable Bits in Register for Halfword and Byte |
5477 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
5478 | ||
07893d4f UW |
5479 | ;; |
5480 | ;;- Add instructions. | |
5481 | ;; | |
5482 | ||
1c7b1b7e UW |
5483 | ; |
5484 | ; addti3 instruction pattern(s). | |
5485 | ; | |
5486 | ||
085261c8 AK |
5487 | (define_expand "addti3" |
5488 | [(parallel | |
5489 | [(set (match_operand:TI 0 "register_operand" "") | |
5490 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "") | |
5491 | (match_operand:TI 2 "general_operand" "") ) ) | |
5492 | (clobber (reg:CC CC_REGNUM))])] | |
5493 | "TARGET_ZARCH" | |
5494 | { | |
5495 | /* For z13 we have vaq which doesn't set CC. */ | |
5496 | if (TARGET_VX) | |
5497 | { | |
5498 | emit_insn (gen_rtx_SET (operands[0], | |
5499 | gen_rtx_PLUS (TImode, | |
5500 | copy_to_mode_reg (TImode, operands[1]), | |
5501 | copy_to_mode_reg (TImode, operands[2])))); | |
5502 | DONE; | |
5503 | } | |
5504 | }) | |
5505 | ||
5506 | (define_insn_and_split "*addti3" | |
5507 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
1c7b1b7e | 5508 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
085261c8 | 5509 | (match_operand:TI 2 "general_operand" "do") ) ) |
ae156f85 | 5510 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5511 | "TARGET_ZARCH" |
1c7b1b7e UW |
5512 | "#" |
5513 | "&& reload_completed" | |
5514 | [(parallel | |
ae156f85 | 5515 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
5516 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
5517 | (match_dup 7))) | |
5518 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
5519 | (parallel | |
a94a76a7 UW |
5520 | [(set (match_dup 3) (plus:DI |
5521 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5522 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5523 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
5524 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5525 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5526 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5527 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5528 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5529 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5530 | [(set_attr "op_type" "*") | |
5531 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 5532 | |
07893d4f UW |
5533 | ; |
5534 | ; adddi3 instruction pattern(s). | |
5535 | ; | |
5536 | ||
3298c037 AK |
5537 | (define_expand "adddi3" |
5538 | [(parallel | |
963fc8d0 | 5539 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
5540 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
5541 | (match_operand:DI 2 "general_operand" ""))) | |
5542 | (clobber (reg:CC CC_REGNUM))])] | |
5543 | "" | |
5544 | "") | |
5545 | ||
07893d4f UW |
5546 | (define_insn "*adddi3_sign" |
5547 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 5548 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 5549 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5550 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5551 | "TARGET_ZARCH" |
07893d4f | 5552 | "@ |
d40c829f UW |
5553 | agfr\t%0,%2 |
5554 | agf\t%0,%2" | |
65b1d8ea AK |
5555 | [(set_attr "op_type" "RRE,RXY") |
5556 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
07893d4f UW |
5557 | |
5558 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 5559 | [(set (reg CC_REGNUM) |
3e4be43f | 5560 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f UW |
5561 | (match_operand:DI 1 "register_operand" "0,0")) |
5562 | (const_int 0))) | |
5563 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5564 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
9602b6a1 | 5565 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5566 | "@ |
d40c829f UW |
5567 | algfr\t%0,%2 |
5568 | algf\t%0,%2" | |
9381e3f1 WG |
5569 | [(set_attr "op_type" "RRE,RXY") |
5570 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5571 | |
5572 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 5573 | [(set (reg CC_REGNUM) |
3e4be43f | 5574 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f UW |
5575 | (match_operand:DI 1 "register_operand" "0,0")) |
5576 | (const_int 0))) | |
5577 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5578 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5579 | "@ |
d40c829f UW |
5580 | algfr\t%0,%2 |
5581 | algf\t%0,%2" | |
9381e3f1 WG |
5582 | [(set_attr "op_type" "RRE,RXY") |
5583 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5584 | |
5585 | (define_insn "*adddi3_zero" | |
5586 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 5587 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 5588 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5589 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5590 | "TARGET_ZARCH" |
07893d4f | 5591 | "@ |
d40c829f UW |
5592 | algfr\t%0,%2 |
5593 | algf\t%0,%2" | |
9381e3f1 WG |
5594 | [(set_attr "op_type" "RRE,RXY") |
5595 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 5596 | |
e69166de | 5597 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 5598 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
5599 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
5600 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5601 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 5602 | "!TARGET_ZARCH" |
e69166de UW |
5603 | "#" |
5604 | "&& reload_completed" | |
5605 | [(parallel | |
ae156f85 | 5606 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
5607 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5608 | (match_dup 7))) | |
5609 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5610 | (parallel | |
a94a76a7 UW |
5611 | [(set (match_dup 3) (plus:SI |
5612 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5613 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5614 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
5615 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5616 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5617 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5618 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5619 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 5620 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 5621 | |
3298c037 AK |
5622 | ; |
5623 | ; addsi3 instruction pattern(s). | |
5624 | ; | |
5625 | ||
5626 | (define_expand "addsi3" | |
07893d4f | 5627 | [(parallel |
963fc8d0 | 5628 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
5629 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
5630 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 5631 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5632 | "" |
07893d4f | 5633 | "") |
9db1d521 | 5634 | |
3298c037 AK |
5635 | (define_insn "*addsi3_sign" |
5636 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5637 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5638 | (match_operand:SI 1 "register_operand" "0,0"))) | |
5639 | (clobber (reg:CC CC_REGNUM))] | |
5640 | "" | |
5641 | "@ | |
5642 | ah\t%0,%2 | |
5643 | ahy\t%0,%2" | |
65b1d8ea | 5644 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 5645 | (set_attr "cpu_facility" "*,longdisp") |
65b1d8ea | 5646 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) |
3298c037 | 5647 | |
9db1d521 | 5648 | ; |
3298c037 | 5649 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 5650 | ; |
9db1d521 | 5651 | |
65b1d8ea | 5652 | ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 5653 | (define_insn "*add<mode>3" |
3e4be43f UW |
5654 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S") |
5655 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0") | |
5656 | (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) ) | |
3298c037 AK |
5657 | (clobber (reg:CC CC_REGNUM))] |
5658 | "" | |
ec24698e | 5659 | "@ |
3298c037 | 5660 | a<g>r\t%0,%2 |
65b1d8ea | 5661 | a<g>rk\t%0,%1,%2 |
3298c037 | 5662 | a<g>hi\t%0,%h2 |
65b1d8ea | 5663 | a<g>hik\t%0,%1,%h2 |
3298c037 AK |
5664 | al<g>fi\t%0,%2 |
5665 | sl<g>fi\t%0,%n2 | |
5666 | a<g>\t%0,%2 | |
963fc8d0 AK |
5667 | a<y>\t%0,%2 |
5668 | a<g>si\t%0,%c2" | |
65b1d8ea | 5669 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") |
3e4be43f | 5670 | (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10") |
65b1d8ea AK |
5671 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, |
5672 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
0a3bdf9d | 5673 | |
65b1d8ea | 5674 | ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik |
3298c037 | 5675 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 5676 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5677 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5678 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5679 | (match_dup 1))) |
65b1d8ea | 5680 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") |
3298c037 | 5681 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5682 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5683 | "@ |
3298c037 | 5684 | al<g>r\t%0,%2 |
65b1d8ea | 5685 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5686 | al<g>fi\t%0,%2 |
5687 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5688 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5689 | al<g>\t%0,%2 |
963fc8d0 AK |
5690 | al<y>\t%0,%2 |
5691 | al<g>si\t%0,%c2" | |
65b1d8ea | 5692 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5693 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5694 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, |
5695 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5696 | |
65b1d8ea | 5697 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5698 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 5699 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5700 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5701 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5702 | (match_dup 1))) |
65b1d8ea | 5703 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5704 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5705 | "@ |
3298c037 | 5706 | al<g>r\t%0,%2 |
65b1d8ea | 5707 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5708 | al<g>\t%0,%2 |
5709 | al<y>\t%0,%2" | |
65b1d8ea | 5710 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5711 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5712 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5713 | |
65b1d8ea | 5714 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5715 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 5716 | [(set (reg CC_REGNUM) |
3e4be43f UW |
5717 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5718 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5719 | (match_dup 2))) |
3e4be43f | 5720 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") |
3298c037 | 5721 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5722 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5723 | "@ |
3298c037 | 5724 | al<g>r\t%0,%2 |
65b1d8ea | 5725 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5726 | al<g>fi\t%0,%2 |
5727 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5728 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5729 | al<g>\t%0,%2 |
963fc8d0 AK |
5730 | al<y>\t%0,%2 |
5731 | al<g>si\t%0,%c2" | |
65b1d8ea | 5732 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5733 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5734 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, |
5735 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5736 | |
65b1d8ea | 5737 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5738 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 5739 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5740 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5741 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5742 | (match_dup 2))) |
65b1d8ea | 5743 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5744 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5745 | "@ |
3298c037 | 5746 | al<g>r\t%0,%2 |
65b1d8ea | 5747 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5748 | al<g>\t%0,%2 |
5749 | al<y>\t%0,%2" | |
65b1d8ea | 5750 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5751 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5752 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5753 | |
65b1d8ea | 5754 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5755 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5756 | [(set (reg CC_REGNUM) |
3e4be43f UW |
5757 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5758 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
9db1d521 | 5759 | (const_int 0))) |
3e4be43f | 5760 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") |
3298c037 | 5761 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5762 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5763 | "@ |
3298c037 | 5764 | al<g>r\t%0,%2 |
65b1d8ea | 5765 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5766 | al<g>fi\t%0,%2 |
5767 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5768 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5769 | al<g>\t%0,%2 |
963fc8d0 AK |
5770 | al<y>\t%0,%2 |
5771 | al<g>si\t%0,%c2" | |
65b1d8ea | 5772 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5773 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5774 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, |
5775 | *,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5776 | |
65b1d8ea | 5777 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5778 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5779 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5780 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5781 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5782 | (const_int 0))) |
65b1d8ea | 5783 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5784 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5785 | "@ |
3298c037 | 5786 | al<g>r\t%0,%2 |
65b1d8ea | 5787 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5788 | al<g>\t%0,%2 |
5789 | al<y>\t%0,%2" | |
65b1d8ea | 5790 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5791 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5792 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
9db1d521 | 5793 | |
65b1d8ea | 5794 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5795 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 5796 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5797 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5798 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) | |
5799 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
3298c037 | 5800 | "s390_match_ccmode(insn, CCLmode)" |
d3632d41 | 5801 | "@ |
3298c037 | 5802 | al<g>r\t%0,%2 |
65b1d8ea | 5803 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5804 | al<g>\t%0,%2 |
5805 | al<y>\t%0,%2" | |
65b1d8ea | 5806 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5807 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5808 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5809 | |
963fc8d0 | 5810 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
5811 | (define_insn "*add<mode>3_imm_cc" |
5812 | [(set (reg CC_REGNUM) | |
65b1d8ea | 5813 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") |
3e4be43f | 5814 | (match_operand:GPR 2 "const_int_operand" " K, K,Os,C")) |
3298c037 | 5815 | (const_int 0))) |
3e4be43f | 5816 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S") |
3298c037 AK |
5817 | (plus:GPR (match_dup 1) (match_dup 2)))] |
5818 | "s390_match_ccmode (insn, CCAmode) | |
5819 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
2542ef05 RH |
5820 | || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
5821 | /* Avoid INT32_MIN on 32 bit. */ | |
5822 | && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" | |
9db1d521 | 5823 | "@ |
3298c037 | 5824 | a<g>hi\t%0,%h2 |
65b1d8ea | 5825 | a<g>hik\t%0,%1,%h2 |
963fc8d0 AK |
5826 | a<g>fi\t%0,%2 |
5827 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
5828 | [(set_attr "op_type" "RI,RIE,RIL,SIY") |
5829 | (set_attr "cpu_facility" "*,z196,extimm,z10") | |
5830 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5831 | |
7d2fd075 AK |
5832 | (define_insn "*adddi3_sign" |
5833 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5834 | (plus:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) | |
5835 | (match_operand:DI 1 "register_operand" "0"))) | |
5836 | (clobber (reg:CC CC_REGNUM))] | |
5837 | "TARGET_ARCH12" | |
5838 | "agh\t%0,%2" | |
5839 | [(set_attr "op_type" "RXY")]) | |
5840 | ||
9db1d521 | 5841 | ; |
609e7e80 | 5842 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5843 | ; |
5844 | ||
609e7e80 | 5845 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
6e5b5de8 | 5846 | ; FIXME: wfadb does not clobber cc |
142cd70f | 5847 | (define_insn "add<mode>3" |
2de2b3f9 AK |
5848 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
5849 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v") | |
5850 | (match_operand:FP 2 "general_operand" "f,f,R,v,v"))) | |
ae156f85 | 5851 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5852 | "TARGET_HARD_FLOAT" |
9db1d521 | 5853 | "@ |
62d3f261 AK |
5854 | a<xde>tr\t%0,%1,%2 |
5855 | a<xde>br\t%0,%2 | |
6e5b5de8 | 5856 | a<xde>b\t%0,%2 |
2de2b3f9 AK |
5857 | wfadb\t%v0,%v1,%v2 |
5858 | wfasb\t%v0,%v1,%v2" | |
5859 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 5860 | (set_attr "type" "fsimp<mode>") |
2de2b3f9 AK |
5861 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
5862 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 5863 | |
609e7e80 | 5864 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5865 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5866 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5867 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
5868 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5869 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5870 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 5871 | (plus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 5872 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5873 | "@ |
62d3f261 AK |
5874 | a<xde>tr\t%0,%1,%2 |
5875 | a<xde>br\t%0,%2 | |
f61a2c7d | 5876 | a<xde>b\t%0,%2" |
62d3f261 AK |
5877 | [(set_attr "op_type" "RRF,RRE,RXE") |
5878 | (set_attr "type" "fsimp<mode>") | |
5879 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5880 | |
609e7e80 | 5881 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5882 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5883 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5884 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
5885 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5886 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5887 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 5888 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5889 | "@ |
62d3f261 AK |
5890 | a<xde>tr\t%0,%1,%2 |
5891 | a<xde>br\t%0,%2 | |
f61a2c7d | 5892 | a<xde>b\t%0,%2" |
62d3f261 AK |
5893 | [(set_attr "op_type" "RRF,RRE,RXE") |
5894 | (set_attr "type" "fsimp<mode>") | |
5895 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5896 | |
72a4ddf2 AK |
5897 | ; |
5898 | ; Pointer add instruction patterns | |
5899 | ; | |
5900 | ||
5901 | ; This will match "*la_64" | |
5902 | (define_expand "addptrdi3" | |
5903 | [(set (match_operand:DI 0 "register_operand" "") | |
5904 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
5905 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
5906 | "TARGET_64BIT" | |
5907 | { | |
72a4ddf2 AK |
5908 | if (GET_CODE (operands[2]) == CONST_INT) |
5909 | { | |
357ddc7d TV |
5910 | HOST_WIDE_INT c = INTVAL (operands[2]); |
5911 | ||
72a4ddf2 AK |
5912 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
5913 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
5914 | { | |
5915 | operands[2] = force_const_mem (DImode, operands[2]); | |
5916 | operands[2] = force_reg (DImode, operands[2]); | |
5917 | } | |
5918 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
5919 | operands[2] = force_reg (DImode, operands[2]); | |
5920 | } | |
5921 | }) | |
5922 | ||
5923 | ; For 31 bit we have to prevent the generated pattern from matching | |
5924 | ; normal ADDs since la only does a 31 bit add. This is supposed to | |
5925 | ; match "force_la_31". | |
5926 | (define_expand "addptrsi3" | |
5927 | [(parallel | |
5928 | [(set (match_operand:SI 0 "register_operand" "") | |
5929 | (plus:SI (match_operand:SI 1 "register_operand" "") | |
5930 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
5931 | (use (const_int 0))])] | |
5932 | "!TARGET_64BIT" | |
5933 | { | |
72a4ddf2 AK |
5934 | if (GET_CODE (operands[2]) == CONST_INT) |
5935 | { | |
357ddc7d TV |
5936 | HOST_WIDE_INT c = INTVAL (operands[2]); |
5937 | ||
72a4ddf2 AK |
5938 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
5939 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
5940 | { | |
5941 | operands[2] = force_const_mem (SImode, operands[2]); | |
5942 | operands[2] = force_reg (SImode, operands[2]); | |
5943 | } | |
5944 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
5945 | operands[2] = force_reg (SImode, operands[2]); | |
5946 | } | |
5947 | }) | |
9db1d521 HP |
5948 | |
5949 | ;; | |
5950 | ;;- Subtract instructions. | |
5951 | ;; | |
5952 | ||
1c7b1b7e UW |
5953 | ; |
5954 | ; subti3 instruction pattern(s). | |
5955 | ; | |
5956 | ||
085261c8 AK |
5957 | (define_expand "subti3" |
5958 | [(parallel | |
5959 | [(set (match_operand:TI 0 "register_operand" "") | |
5960 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
5961 | (match_operand:TI 2 "general_operand" "") ) ) | |
5962 | (clobber (reg:CC CC_REGNUM))])] | |
5963 | "TARGET_ZARCH" | |
5964 | { | |
2d71f118 | 5965 | /* For z13 we have vsq which doesn't set CC. */ |
085261c8 AK |
5966 | if (TARGET_VX) |
5967 | { | |
5968 | emit_insn (gen_rtx_SET (operands[0], | |
5969 | gen_rtx_MINUS (TImode, | |
5970 | operands[1], | |
5971 | copy_to_mode_reg (TImode, operands[2])))); | |
5972 | DONE; | |
5973 | } | |
5974 | }) | |
5975 | ||
5976 | (define_insn_and_split "*subti3" | |
5977 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
5978 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
5979 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 5980 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5981 | "TARGET_ZARCH" |
1c7b1b7e UW |
5982 | "#" |
5983 | "&& reload_completed" | |
5984 | [(parallel | |
ae156f85 | 5985 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
5986 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
5987 | (match_dup 7))) | |
5988 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
5989 | (parallel | |
5990 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
5991 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
5992 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
5993 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5994 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5995 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5996 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5997 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5998 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5999 | [(set_attr "op_type" "*") | |
6000 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 6001 | |
9db1d521 HP |
6002 | ; |
6003 | ; subdi3 instruction pattern(s). | |
6004 | ; | |
6005 | ||
3298c037 AK |
6006 | (define_expand "subdi3" |
6007 | [(parallel | |
6008 | [(set (match_operand:DI 0 "register_operand" "") | |
6009 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
6010 | (match_operand:DI 2 "general_operand" ""))) | |
6011 | (clobber (reg:CC CC_REGNUM))])] | |
6012 | "" | |
6013 | "") | |
6014 | ||
07893d4f UW |
6015 | (define_insn "*subdi3_sign" |
6016 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
6017 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3e4be43f | 6018 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) |
ae156f85 | 6019 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6020 | "TARGET_ZARCH" |
07893d4f | 6021 | "@ |
d40c829f UW |
6022 | sgfr\t%0,%2 |
6023 | sgf\t%0,%2" | |
9381e3f1 | 6024 | [(set_attr "op_type" "RRE,RXY") |
65b1d8ea AK |
6025 | (set_attr "z10prop" "z10_c,*") |
6026 | (set_attr "z196prop" "z196_cracked")]) | |
07893d4f UW |
6027 | |
6028 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 6029 | [(set (reg CC_REGNUM) |
07893d4f | 6030 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6031 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) |
07893d4f UW |
6032 | (const_int 0))) |
6033 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
6034 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
9602b6a1 | 6035 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 6036 | "@ |
d40c829f UW |
6037 | slgfr\t%0,%2 |
6038 | slgf\t%0,%2" | |
9381e3f1 WG |
6039 | [(set_attr "op_type" "RRE,RXY") |
6040 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
6041 | |
6042 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 6043 | [(set (reg CC_REGNUM) |
07893d4f | 6044 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6045 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) |
07893d4f UW |
6046 | (const_int 0))) |
6047 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 6048 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 6049 | "@ |
d40c829f UW |
6050 | slgfr\t%0,%2 |
6051 | slgf\t%0,%2" | |
9381e3f1 WG |
6052 | [(set_attr "op_type" "RRE,RXY") |
6053 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
6054 | |
6055 | (define_insn "*subdi3_zero" | |
6056 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
6057 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3e4be43f | 6058 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) |
ae156f85 | 6059 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6060 | "TARGET_ZARCH" |
07893d4f | 6061 | "@ |
d40c829f UW |
6062 | slgfr\t%0,%2 |
6063 | slgf\t%0,%2" | |
9381e3f1 WG |
6064 | [(set_attr "op_type" "RRE,RXY") |
6065 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 6066 | |
e69166de UW |
6067 | (define_insn_and_split "*subdi3_31z" |
6068 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
6069 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
6070 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 6071 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6072 | "!TARGET_ZARCH" |
e69166de UW |
6073 | "#" |
6074 | "&& reload_completed" | |
6075 | [(parallel | |
ae156f85 | 6076 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
6077 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
6078 | (match_dup 7))) | |
6079 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
6080 | (parallel | |
6081 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
6082 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
6083 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
6084 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
6085 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
6086 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
6087 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
6088 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 6089 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 6090 | |
3298c037 AK |
6091 | ; |
6092 | ; subsi3 instruction pattern(s). | |
6093 | ; | |
6094 | ||
6095 | (define_expand "subsi3" | |
07893d4f | 6096 | [(parallel |
3298c037 AK |
6097 | [(set (match_operand:SI 0 "register_operand" "") |
6098 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
6099 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 6100 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 6101 | "" |
07893d4f | 6102 | "") |
9db1d521 | 6103 | |
3298c037 AK |
6104 | (define_insn "*subsi3_sign" |
6105 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
6106 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
6107 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
6108 | (clobber (reg:CC CC_REGNUM))] | |
6109 | "" | |
6110 | "@ | |
6111 | sh\t%0,%2 | |
6112 | shy\t%0,%2" | |
65b1d8ea | 6113 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 6114 | (set_attr "cpu_facility" "*,longdisp") |
65b1d8ea | 6115 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) |
3298c037 | 6116 | |
9db1d521 | 6117 | ; |
3298c037 | 6118 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
6119 | ; |
6120 | ||
65b1d8ea | 6121 | ; sr, s, sy, sgr, sg, srk, sgrk |
3298c037 | 6122 | (define_insn "*sub<mode>3" |
65b1d8ea AK |
6123 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
6124 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") | |
6125 | (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) | |
3298c037 AK |
6126 | (clobber (reg:CC CC_REGNUM))] |
6127 | "" | |
6128 | "@ | |
6129 | s<g>r\t%0,%2 | |
65b1d8ea | 6130 | s<g>rk\t%0,%1,%2 |
3298c037 AK |
6131 | s<g>\t%0,%2 |
6132 | s<y>\t%0,%2" | |
65b1d8ea | 6133 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6134 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6135 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
3298c037 | 6136 | |
65b1d8ea | 6137 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6138 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 6139 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6140 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6141 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 6142 | (match_dup 1))) |
65b1d8ea | 6143 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 6144 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 6145 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 6146 | "@ |
3298c037 | 6147 | sl<g>r\t%0,%2 |
65b1d8ea | 6148 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6149 | sl<g>\t%0,%2 |
6150 | sl<y>\t%0,%2" | |
65b1d8ea | 6151 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6152 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6153 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 6154 | |
65b1d8ea | 6155 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6156 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 6157 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6158 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6159 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 6160 | (match_dup 1))) |
65b1d8ea | 6161 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 6162 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 6163 | "@ |
3298c037 | 6164 | sl<g>r\t%0,%2 |
65b1d8ea | 6165 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6166 | sl<g>\t%0,%2 |
6167 | sl<y>\t%0,%2" | |
65b1d8ea | 6168 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6169 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6170 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 6171 | |
65b1d8ea | 6172 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6173 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 6174 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6175 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6176 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 6177 | (const_int 0))) |
65b1d8ea | 6178 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 6179 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 6180 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 6181 | "@ |
3298c037 | 6182 | sl<g>r\t%0,%2 |
65b1d8ea | 6183 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6184 | sl<g>\t%0,%2 |
6185 | sl<y>\t%0,%2" | |
65b1d8ea | 6186 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6187 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6188 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9db1d521 | 6189 | |
65b1d8ea | 6190 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6191 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 6192 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6193 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6194 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
6195 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
3298c037 | 6196 | (minus:GPR (match_dup 1) (match_dup 2)))] |
5d880bd2 UW |
6197 | "s390_match_ccmode (insn, CCL3mode)" |
6198 | "@ | |
3298c037 | 6199 | sl<g>r\t%0,%2 |
65b1d8ea | 6200 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6201 | sl<g>\t%0,%2 |
6202 | sl<y>\t%0,%2" | |
65b1d8ea | 6203 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6204 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6205 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
5d880bd2 | 6206 | |
65b1d8ea | 6207 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6208 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6209 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6210 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6211 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 6212 | (const_int 0))) |
65b1d8ea | 6213 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 6214 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 6215 | "@ |
3298c037 | 6216 | sl<g>r\t%0,%2 |
65b1d8ea | 6217 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6218 | sl<g>\t%0,%2 |
6219 | sl<y>\t%0,%2" | |
65b1d8ea | 6220 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6221 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6222 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9381e3f1 | 6223 | |
9db1d521 | 6224 | |
65b1d8ea | 6225 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6226 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 6227 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6228 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6229 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
6230 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
5d880bd2 UW |
6231 | "s390_match_ccmode (insn, CCL3mode)" |
6232 | "@ | |
3298c037 | 6233 | sl<g>r\t%0,%2 |
65b1d8ea | 6234 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6235 | sl<g>\t%0,%2 |
6236 | sl<y>\t%0,%2" | |
65b1d8ea | 6237 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6238 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6239 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9381e3f1 | 6240 | |
7d2fd075 AK |
6241 | (define_insn "*subdi3_sign" |
6242 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6243 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
6244 | (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")))) | |
6245 | (clobber (reg:CC CC_REGNUM))] | |
6246 | "TARGET_ARCH12" | |
6247 | "sgh\t%0,%2" | |
6248 | [(set_attr "op_type" "RXY")]) | |
6249 | ||
9db1d521 HP |
6250 | |
6251 | ; | |
609e7e80 | 6252 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6253 | ; |
6254 | ||
2de2b3f9 | 6255 | ; FIXME: (clobber (match_scratch:CC 3 "=c,c,c,X,X")) does not work - why? |
d46f24b6 | 6256 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 6257 | (define_insn "sub<mode>3" |
2de2b3f9 AK |
6258 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
6259 | (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v") | |
6260 | (match_operand:FP 2 "general_operand" "f,f,R,v,v"))) | |
ae156f85 | 6261 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 6262 | "TARGET_HARD_FLOAT" |
9db1d521 | 6263 | "@ |
62d3f261 AK |
6264 | s<xde>tr\t%0,%1,%2 |
6265 | s<xde>br\t%0,%2 | |
6e5b5de8 | 6266 | s<xde>b\t%0,%2 |
2de2b3f9 AK |
6267 | wfsdb\t%v0,%v1,%v2 |
6268 | wfssb\t%v0,%v1,%v2" | |
6269 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6270 | (set_attr "type" "fsimp<mode>") |
2de2b3f9 AK |
6271 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
6272 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 6273 | |
d46f24b6 | 6274 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6275 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 6276 | [(set (reg CC_REGNUM) |
62d3f261 | 6277 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
2de2b3f9 | 6278 | (match_operand:FP 2 "general_operand" "f,f,R")) |
609e7e80 | 6279 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6280 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 6281 | (minus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 6282 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6283 | "@ |
62d3f261 AK |
6284 | s<xde>tr\t%0,%1,%2 |
6285 | s<xde>br\t%0,%2 | |
f61a2c7d | 6286 | s<xde>b\t%0,%2" |
62d3f261 AK |
6287 | [(set_attr "op_type" "RRF,RRE,RXE") |
6288 | (set_attr "type" "fsimp<mode>") | |
6289 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6290 | |
d46f24b6 | 6291 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6292 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6293 | [(set (reg CC_REGNUM) |
62d3f261 AK |
6294 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
6295 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 6296 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6297 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 6298 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6299 | "@ |
62d3f261 AK |
6300 | s<xde>tr\t%0,%1,%2 |
6301 | s<xde>br\t%0,%2 | |
f61a2c7d | 6302 | s<xde>b\t%0,%2" |
62d3f261 AK |
6303 | [(set_attr "op_type" "RRF,RRE,RXE") |
6304 | (set_attr "type" "fsimp<mode>") | |
6305 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6306 | |
9db1d521 | 6307 | |
e69166de UW |
6308 | ;; |
6309 | ;;- Conditional add/subtract instructions. | |
6310 | ;; | |
6311 | ||
6312 | ; | |
9a91a21f | 6313 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
6314 | ; |
6315 | ||
a996720c UW |
6316 | ; the following 4 patterns are used when the result of an add with |
6317 | ; carry is checked for an overflow condition | |
6318 | ||
6319 | ; op1 + op2 + c < op1 | |
6320 | ||
6321 | ; alcr, alc, alcgr, alcg | |
6322 | (define_insn "*add<mode>3_alc_carry1_cc" | |
6323 | [(set (reg CC_REGNUM) | |
6324 | (compare | |
6325 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6326 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6327 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6328 | (match_dup 1))) |
6329 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6330 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
8cc6307c | 6331 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6332 | "@ |
6333 | alc<g>r\t%0,%2 | |
6334 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6335 | [(set_attr "op_type" "RRE,RXY") |
6336 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6337 | |
6338 | ; alcr, alc, alcgr, alcg | |
6339 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
6340 | [(set (reg CC_REGNUM) | |
6341 | (compare | |
6342 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6343 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6344 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6345 | (match_dup 1))) |
6346 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
8cc6307c | 6347 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6348 | "@ |
6349 | alc<g>r\t%0,%2 | |
6350 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6351 | [(set_attr "op_type" "RRE,RXY") |
6352 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6353 | |
6354 | ; op1 + op2 + c < op2 | |
6355 | ||
6356 | ; alcr, alc, alcgr, alcg | |
6357 | (define_insn "*add<mode>3_alc_carry2_cc" | |
6358 | [(set (reg CC_REGNUM) | |
6359 | (compare | |
6360 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6361 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6362 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6363 | (match_dup 2))) |
6364 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6365 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
8cc6307c | 6366 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6367 | "@ |
6368 | alc<g>r\t%0,%2 | |
6369 | alc<g>\t%0,%2" | |
6370 | [(set_attr "op_type" "RRE,RXY")]) | |
6371 | ||
6372 | ; alcr, alc, alcgr, alcg | |
6373 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
6374 | [(set (reg CC_REGNUM) | |
6375 | (compare | |
6376 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6377 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6378 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6379 | (match_dup 2))) |
6380 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
8cc6307c | 6381 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6382 | "@ |
6383 | alc<g>r\t%0,%2 | |
6384 | alc<g>\t%0,%2" | |
6385 | [(set_attr "op_type" "RRE,RXY")]) | |
6386 | ||
43a09b63 | 6387 | ; alcr, alc, alcgr, alcg |
9a91a21f | 6388 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 6389 | [(set (reg CC_REGNUM) |
e69166de | 6390 | (compare |
a94a76a7 UW |
6391 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6392 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6393 | (match_operand:GPR 2 "general_operand" "d,T")) |
e69166de | 6394 | (const_int 0))) |
9a91a21f | 6395 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 6396 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
8cc6307c | 6397 | "s390_match_ccmode (insn, CCLmode)" |
e69166de | 6398 | "@ |
9a91a21f AS |
6399 | alc<g>r\t%0,%2 |
6400 | alc<g>\t%0,%2" | |
e69166de UW |
6401 | [(set_attr "op_type" "RRE,RXY")]) |
6402 | ||
43a09b63 | 6403 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
6404 | (define_insn "*add<mode>3_alc" |
6405 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
6406 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6407 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6408 | (match_operand:GPR 2 "general_operand" "d,T"))) |
ae156f85 | 6409 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6410 | "" |
e69166de | 6411 | "@ |
9a91a21f AS |
6412 | alc<g>r\t%0,%2 |
6413 | alc<g>\t%0,%2" | |
e69166de UW |
6414 | [(set_attr "op_type" "RRE,RXY")]) |
6415 | ||
43a09b63 | 6416 | ; slbr, slb, slbgr, slbg |
9a91a21f | 6417 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 6418 | [(set (reg CC_REGNUM) |
e69166de | 6419 | (compare |
9a91a21f | 6420 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
3e4be43f | 6421 | (match_operand:GPR 2 "general_operand" "d,T")) |
9a91a21f | 6422 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 6423 | (const_int 0))) |
9a91a21f AS |
6424 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
6425 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
8cc6307c | 6426 | "s390_match_ccmode (insn, CCLmode)" |
e69166de | 6427 | "@ |
9a91a21f AS |
6428 | slb<g>r\t%0,%2 |
6429 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6430 | [(set_attr "op_type" "RRE,RXY") |
6431 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6432 | |
43a09b63 | 6433 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
6434 | (define_insn "*sub<mode>3_slb" |
6435 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
6436 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
3e4be43f | 6437 | (match_operand:GPR 2 "general_operand" "d,T")) |
9a91a21f | 6438 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 6439 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6440 | "" |
e69166de | 6441 | "@ |
9a91a21f AS |
6442 | slb<g>r\t%0,%2 |
6443 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6444 | [(set_attr "op_type" "RRE,RXY") |
6445 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6446 | |
9a91a21f AS |
6447 | (define_expand "add<mode>cc" |
6448 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 6449 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
6450 | (match_operand:GPR 2 "register_operand" "") |
6451 | (match_operand:GPR 3 "const_int_operand" "")] | |
8cc6307c | 6452 | "" |
9381e3f1 | 6453 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
f90b7a5a | 6454 | XEXP (operands[1], 0), XEXP (operands[1], 1), |
9381e3f1 | 6455 | operands[0], operands[2], |
5d880bd2 UW |
6456 | operands[3])) FAIL; DONE;") |
6457 | ||
6458 | ; | |
6459 | ; scond instruction pattern(s). | |
6460 | ; | |
6461 | ||
9a91a21f AS |
6462 | (define_insn_and_split "*scond<mode>" |
6463 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6464 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 6465 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6466 | "" |
5d880bd2 UW |
6467 | "#" |
6468 | "&& reload_completed" | |
6469 | [(set (match_dup 0) (const_int 0)) | |
6470 | (parallel | |
a94a76a7 UW |
6471 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
6472 | (match_dup 0))) | |
ae156f85 | 6473 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6474 | "") |
5d880bd2 | 6475 | |
9a91a21f AS |
6476 | (define_insn_and_split "*scond<mode>_neg" |
6477 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6478 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 6479 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6480 | "" |
5d880bd2 UW |
6481 | "#" |
6482 | "&& reload_completed" | |
6483 | [(set (match_dup 0) (const_int 0)) | |
6484 | (parallel | |
9a91a21f AS |
6485 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
6486 | (match_dup 1))) | |
ae156f85 | 6487 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 6488 | (parallel |
9a91a21f | 6489 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 6490 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6491 | "") |
5d880bd2 | 6492 | |
5d880bd2 | 6493 | |
f90b7a5a | 6494 | (define_expand "cstore<mode>4" |
9a91a21f | 6495 | [(set (match_operand:SI 0 "register_operand" "") |
f90b7a5a PB |
6496 | (match_operator:SI 1 "s390_scond_operator" |
6497 | [(match_operand:GPR 2 "register_operand" "") | |
6498 | (match_operand:GPR 3 "general_operand" "")]))] | |
8cc6307c | 6499 | "" |
f90b7a5a | 6500 | "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], |
5d880bd2 UW |
6501 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
6502 | ||
f90b7a5a | 6503 | (define_expand "cstorecc4" |
69950452 | 6504 | [(parallel |
f90b7a5a PB |
6505 | [(set (match_operand:SI 0 "register_operand" "") |
6506 | (match_operator:SI 1 "s390_eqne_operator" | |
3ea685e7 | 6507 | [(match_operand 2 "cc_reg_operand") |
f90b7a5a | 6508 | (match_operand 3 "const0_operand")])) |
69950452 AS |
6509 | (clobber (reg:CC CC_REGNUM))])] |
6510 | "" | |
3ea685e7 DV |
6511 | "machine_mode mode = GET_MODE (operands[2]); |
6512 | if (TARGET_Z196) | |
6513 | { | |
6514 | rtx cond, ite; | |
6515 | ||
6516 | if (GET_CODE (operands[1]) == NE) | |
6517 | cond = gen_rtx_NE (VOIDmode, operands[2], const0_rtx); | |
6518 | else | |
6519 | cond = gen_rtx_EQ (VOIDmode, operands[2], const0_rtx); | |
6520 | ite = gen_rtx_IF_THEN_ELSE (SImode, cond, const1_rtx, const0_rtx); | |
6521 | emit_insn (gen_rtx_SET (operands[0], ite)); | |
6522 | } | |
6523 | else | |
6524 | { | |
6525 | if (mode != CCZ1mode) | |
6526 | FAIL; | |
6527 | emit_insn (gen_sne (operands[0], operands[2])); | |
6528 | if (GET_CODE (operands[1]) == EQ) | |
6529 | emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); | |
6530 | } | |
f90b7a5a | 6531 | DONE;") |
69950452 | 6532 | |
f90b7a5a | 6533 | (define_insn_and_split "sne" |
69950452 | 6534 | [(set (match_operand:SI 0 "register_operand" "=d") |
9381e3f1 | 6535 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
6536 | (const_int 0))) |
6537 | (clobber (reg:CC CC_REGNUM))] | |
6538 | "" | |
6539 | "#" | |
6540 | "reload_completed" | |
6541 | [(parallel | |
6542 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
6543 | (clobber (reg:CC CC_REGNUM))])]) | |
6544 | ||
e69166de | 6545 | |
65b1d8ea AK |
6546 | ;; |
6547 | ;; - Conditional move instructions (introduced with z196) | |
6548 | ;; | |
6549 | ||
6550 | (define_expand "mov<mode>cc" | |
6551 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
6552 | (if_then_else:GPR (match_operand 1 "comparison_operator" "") | |
6553 | (match_operand:GPR 2 "nonimmediate_operand" "") | |
6554 | (match_operand:GPR 3 "nonimmediate_operand" "")))] | |
6555 | "TARGET_Z196" | |
7477de01 AK |
6556 | { |
6557 | /* Emit the comparison insn in case we do not already have a comparison result. */ | |
6558 | if (!s390_comparison (operands[1], VOIDmode)) | |
6559 | operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
6560 | XEXP (operands[1], 0), | |
6561 | XEXP (operands[1], 1)); | |
6562 | }) | |
65b1d8ea | 6563 | |
bf749919 | 6564 | ; locr, loc, stoc, locgr, locg, stocg, lochi, locghi |
561f6312 AK |
6565 | (define_insn "*mov<mode>cc" |
6566 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S,S") | |
65b1d8ea AK |
6567 | (if_then_else:GPR |
6568 | (match_operator 1 "s390_comparison" | |
561f6312 | 6569 | [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c") |
5a3fe9b6 | 6570 | (match_operand 5 "const_int_operand" "")]) |
561f6312 AK |
6571 | (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0") |
6572 | (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d")))] | |
65b1d8ea AK |
6573 | "TARGET_Z196" |
6574 | "@ | |
6575 | loc<g>r%C1\t%0,%3 | |
6576 | loc<g>r%D1\t%0,%4 | |
a6510374 AK |
6577 | loc<g>%C1\t%0,%3 |
6578 | loc<g>%D1\t%0,%4 | |
bf749919 DV |
6579 | loc<g>hi%C1\t%0,%h3 |
6580 | loc<g>hi%D1\t%0,%h4 | |
a6510374 | 6581 | stoc<g>%C1\t%3,%0 |
561f6312 AK |
6582 | stoc<g>%D1\t%4,%0" |
6583 | [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY") | |
6584 | (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*")]) | |
65b1d8ea | 6585 | |
9db1d521 HP |
6586 | ;; |
6587 | ;;- Multiply instructions. | |
6588 | ;; | |
6589 | ||
4023fb28 UW |
6590 | ; |
6591 | ; muldi3 instruction pattern(s). | |
6592 | ; | |
9db1d521 | 6593 | |
7d2fd075 AK |
6594 | (define_expand "muldi3" |
6595 | [(parallel | |
6596 | [(set (match_operand:DI 0 "register_operand") | |
6597 | (mult:DI (match_operand:DI 1 "nonimmediate_operand") | |
6598 | (match_operand:DI 2 "general_operand"))) | |
6599 | (clobber (reg:CC CC_REGNUM))])] | |
6600 | "TARGET_ZARCH") | |
6601 | ||
07893d4f UW |
6602 | (define_insn "*muldi3_sign" |
6603 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 6604 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 6605 | (match_operand:DI 1 "register_operand" "0,0")))] |
9602b6a1 | 6606 | "TARGET_ZARCH" |
07893d4f | 6607 | "@ |
d40c829f UW |
6608 | msgfr\t%0,%2 |
6609 | msgf\t%0,%2" | |
963fc8d0 AK |
6610 | [(set_attr "op_type" "RRE,RXY") |
6611 | (set_attr "type" "imuldi")]) | |
07893d4f | 6612 | |
7d2fd075 AK |
6613 | (define_insn "*muldi3" |
6614 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d") | |
6615 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0,0,0") | |
6616 | (match_operand:DI 2 "general_operand" "d,d,K,T,Os"))) | |
6617 | (clobber (match_scratch:CC 3 "=X,c,X,X,X"))] | |
9602b6a1 | 6618 | "TARGET_ZARCH" |
9db1d521 | 6619 | "@ |
d40c829f | 6620 | msgr\t%0,%2 |
7d2fd075 | 6621 | msgrkc\t%0,%1,%2 |
d40c829f | 6622 | mghi\t%0,%h2 |
963fc8d0 AK |
6623 | msg\t%0,%2 |
6624 | msgfi\t%0,%2" | |
7d2fd075 | 6625 | [(set_attr "op_type" "RRE,RRF,RI,RXY,RIL") |
963fc8d0 | 6626 | (set_attr "type" "imuldi") |
7d2fd075 AK |
6627 | (set_attr "cpu_facility" "*,arch12,*,*,z10")]) |
6628 | ||
6629 | (define_insn "mulditi3" | |
6630 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6631 | (mult:TI (sign_extend:TI | |
6632 | (match_operand:DI 1 "register_operand" "%d,0")) | |
6633 | (sign_extend:TI | |
6634 | (match_operand:DI 2 "nonimmediate_operand" " d,T"))))] | |
6635 | "TARGET_ARCH12" | |
6636 | "@ | |
6637 | mgrk\t%0,%1,%2 | |
6638 | mg\t%0,%2" | |
6639 | [(set_attr "op_type" "RRF,RXY")]) | |
6640 | ||
6641 | ; Combine likes op1 and op2 to be swapped sometimes. | |
6642 | (define_insn "mulditi3_2" | |
6643 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6644 | (mult:TI (sign_extend:TI | |
6645 | (match_operand:DI 1 "nonimmediate_operand" "%d,T")) | |
6646 | (sign_extend:TI | |
6647 | (match_operand:DI 2 "register_operand" " d,0"))))] | |
6648 | "TARGET_ARCH12" | |
6649 | "@ | |
6650 | mgrk\t%0,%1,%2 | |
6651 | mg\t%0,%1" | |
6652 | [(set_attr "op_type" "RRF,RXY")]) | |
6653 | ||
6654 | (define_insn "*muldi3_sign" | |
6655 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6656 | (mult:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) | |
6657 | (match_operand:DI 1 "register_operand" "0")))] | |
6658 | "TARGET_ARCH12" | |
6659 | "mgh\t%0,%2" | |
6660 | [(set_attr "op_type" "RXY")]) | |
6661 | ||
f2d3c02a | 6662 | |
9db1d521 HP |
6663 | ; |
6664 | ; mulsi3 instruction pattern(s). | |
6665 | ; | |
6666 | ||
7d2fd075 AK |
6667 | (define_expand "mulsi3" |
6668 | [(parallel | |
6669 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") | |
6670 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6671 | (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) | |
6672 | (clobber (reg:CC CC_REGNUM))])] | |
6673 | "") | |
6674 | ||
f1e77d83 | 6675 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
6676 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6677 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
6678 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 6679 | "" |
963fc8d0 AK |
6680 | "@ |
6681 | mh\t%0,%2 | |
6682 | mhy\t%0,%2" | |
6683 | [(set_attr "op_type" "RX,RXY") | |
6684 | (set_attr "type" "imulhi") | |
6685 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 6686 | |
7d2fd075 AK |
6687 | (define_insn "*mulsi3" |
6688 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") | |
6689 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6690 | (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) | |
6691 | (clobber (match_scratch:CC 3 "=X,c,X,X,X,X"))] | |
9db1d521 HP |
6692 | "" |
6693 | "@ | |
d40c829f | 6694 | msr\t%0,%2 |
7d2fd075 | 6695 | msrkc\t%0,%1,%2 |
d40c829f UW |
6696 | mhi\t%0,%h2 |
6697 | ms\t%0,%2 | |
963fc8d0 AK |
6698 | msy\t%0,%2 |
6699 | msfi\t%0,%2" | |
7d2fd075 AK |
6700 | [(set_attr "op_type" "RRE,RRF,RI,RX,RXY,RIL") |
6701 | (set_attr "type" "imulsi,*,imulhi,imulsi,imulsi,imulsi") | |
6702 | (set_attr "cpu_facility" "*,arch12,*,*,longdisp,z10")]) | |
9db1d521 | 6703 | |
4023fb28 UW |
6704 | ; |
6705 | ; mulsidi3 instruction pattern(s). | |
6706 | ; | |
6707 | ||
f1e77d83 | 6708 | (define_insn "mulsidi3" |
963fc8d0 | 6709 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 6710 | (mult:DI (sign_extend:DI |
963fc8d0 | 6711 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 6712 | (sign_extend:DI |
963fc8d0 | 6713 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
9602b6a1 | 6714 | "!TARGET_ZARCH" |
f1e77d83 UW |
6715 | "@ |
6716 | mr\t%0,%2 | |
963fc8d0 AK |
6717 | m\t%0,%2 |
6718 | mfy\t%0,%2" | |
6719 | [(set_attr "op_type" "RR,RX,RXY") | |
6720 | (set_attr "type" "imulsi") | |
6721 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 6722 | |
f1e77d83 | 6723 | ; |
6e0d70c9 | 6724 | ; umul instruction pattern(s). |
f1e77d83 | 6725 | ; |
c7453384 | 6726 | |
6e0d70c9 AK |
6727 | ; mlr, ml, mlgr, mlg |
6728 | (define_insn "umul<dwh><mode>3" | |
3e4be43f | 6729 | [(set (match_operand:DW 0 "register_operand" "=d,d") |
6e0d70c9 | 6730 | (mult:DW (zero_extend:DW |
3e4be43f | 6731 | (match_operand:<DWH> 1 "register_operand" "%0,0")) |
6e0d70c9 | 6732 | (zero_extend:DW |
3e4be43f | 6733 | (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))] |
8cc6307c | 6734 | "" |
f1e77d83 | 6735 | "@ |
6e0d70c9 AK |
6736 | ml<tg>r\t%0,%2 |
6737 | ml<tg>\t%0,%2" | |
f1e77d83 | 6738 | [(set_attr "op_type" "RRE,RXY") |
6e0d70c9 | 6739 | (set_attr "type" "imul<dwh>")]) |
c7453384 | 6740 | |
9db1d521 | 6741 | ; |
609e7e80 | 6742 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6743 | ; |
6744 | ||
9381e3f1 | 6745 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 6746 | (define_insn "mul<mode>3" |
2de2b3f9 AK |
6747 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
6748 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v") | |
6749 | (match_operand:FP 2 "general_operand" "f,f,R,v,v")))] | |
142cd70f | 6750 | "TARGET_HARD_FLOAT" |
9db1d521 | 6751 | "@ |
62d3f261 AK |
6752 | m<xdee>tr\t%0,%1,%2 |
6753 | m<xdee>br\t%0,%2 | |
6e5b5de8 | 6754 | m<xdee>b\t%0,%2 |
2de2b3f9 AK |
6755 | wfmdb\t%v0,%v1,%v2 |
6756 | wfmsb\t%v0,%v1,%v2" | |
6757 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6758 | (set_attr "type" "fmul<mode>") |
2de2b3f9 AK |
6759 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
6760 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 6761 | |
9381e3f1 | 6762 | ; madbr, maebr, maxb, madb, maeb |
d7ecb504 | 6763 | (define_insn "fma<mode>4" |
2de2b3f9 AK |
6764 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v") |
6765 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v") | |
6766 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v") | |
6767 | (match_operand:DSF 3 "register_operand" "0,0,v,v")))] | |
d7ecb504 | 6768 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6769 | "@ |
f61a2c7d | 6770 | ma<xde>br\t%0,%1,%2 |
6e5b5de8 | 6771 | ma<xde>b\t%0,%1,%2 |
2de2b3f9 AK |
6772 | wfmadb\t%v0,%v1,%v2,%v3 |
6773 | wfmasb\t%v0,%v1,%v2,%v3" | |
6774 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6775 | (set_attr "type" "fmadd<mode>") |
2de2b3f9 AK |
6776 | (set_attr "cpu_facility" "*,*,vx,vxe") |
6777 | (set_attr "enabled" "*,*,<DF>,<SF>")]) | |
a1b892b5 | 6778 | |
43a09b63 | 6779 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
d7ecb504 | 6780 | (define_insn "fms<mode>4" |
2de2b3f9 AK |
6781 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v") |
6782 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v") | |
6783 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v") | |
6784 | (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v,v"))))] | |
d7ecb504 | 6785 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6786 | "@ |
f61a2c7d | 6787 | ms<xde>br\t%0,%1,%2 |
6e5b5de8 | 6788 | ms<xde>b\t%0,%1,%2 |
2de2b3f9 AK |
6789 | wfmsdb\t%v0,%v1,%v2,%v3 |
6790 | wfmssb\t%v0,%v1,%v2,%v3" | |
6791 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6792 | (set_attr "type" "fmadd<mode>") |
2de2b3f9 AK |
6793 | (set_attr "cpu_facility" "*,*,vx,vxe") |
6794 | (set_attr "enabled" "*,*,<DF>,<SF>")]) | |
9db1d521 HP |
6795 | |
6796 | ;; | |
6797 | ;;- Divide and modulo instructions. | |
6798 | ;; | |
6799 | ||
6800 | ; | |
4023fb28 | 6801 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
6802 | ; |
6803 | ||
4023fb28 UW |
6804 | (define_expand "divmoddi4" |
6805 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 6806 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
6807 | (match_operand:DI 2 "general_operand" ""))) |
6808 | (set (match_operand:DI 3 "general_operand" "") | |
6809 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
6810 | (clobber (match_dup 4))] | |
9602b6a1 | 6811 | "TARGET_ZARCH" |
9db1d521 | 6812 | { |
d8485bdb TS |
6813 | rtx div_equal, mod_equal; |
6814 | rtx_insn *insn; | |
4023fb28 UW |
6815 | |
6816 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
6817 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
6818 | |
6819 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 6820 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
6821 | |
6822 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6823 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6824 | |
6825 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6826 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6827 | |
9db1d521 | 6828 | DONE; |
10bbf137 | 6829 | }) |
9db1d521 HP |
6830 | |
6831 | (define_insn "divmodtidi3" | |
4023fb28 UW |
6832 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
6833 | (ior:TI | |
4023fb28 UW |
6834 | (ashift:TI |
6835 | (zero_extend:TI | |
5665e398 | 6836 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6837 | (match_operand:DI 2 "general_operand" "d,T"))) |
5665e398 UW |
6838 | (const_int 64)) |
6839 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9602b6a1 | 6840 | "TARGET_ZARCH" |
9db1d521 | 6841 | "@ |
d40c829f UW |
6842 | dsgr\t%0,%2 |
6843 | dsg\t%0,%2" | |
d3632d41 | 6844 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6845 | (set_attr "type" "idiv")]) |
9db1d521 | 6846 | |
4023fb28 UW |
6847 | (define_insn "divmodtisi3" |
6848 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6849 | (ior:TI | |
4023fb28 UW |
6850 | (ashift:TI |
6851 | (zero_extend:TI | |
5665e398 | 6852 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 6853 | (sign_extend:DI |
3e4be43f | 6854 | (match_operand:SI 2 "nonimmediate_operand" "d,T")))) |
5665e398 UW |
6855 | (const_int 64)) |
6856 | (zero_extend:TI | |
6857 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9602b6a1 | 6858 | "TARGET_ZARCH" |
4023fb28 | 6859 | "@ |
d40c829f UW |
6860 | dsgfr\t%0,%2 |
6861 | dsgf\t%0,%2" | |
d3632d41 | 6862 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6863 | (set_attr "type" "idiv")]) |
9db1d521 | 6864 | |
4023fb28 UW |
6865 | ; |
6866 | ; udivmoddi4 instruction pattern(s). | |
6867 | ; | |
9db1d521 | 6868 | |
4023fb28 UW |
6869 | (define_expand "udivmoddi4" |
6870 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
6871 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
6872 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
6873 | (set (match_operand:DI 3 "general_operand" "") | |
6874 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
6875 | (clobber (match_dup 4))] | |
9602b6a1 | 6876 | "TARGET_ZARCH" |
9db1d521 | 6877 | { |
d8485bdb TS |
6878 | rtx div_equal, mod_equal, equal; |
6879 | rtx_insn *insn; | |
4023fb28 UW |
6880 | |
6881 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
6882 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
6883 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
6884 | gen_rtx_ASHIFT (TImode, |
6885 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
6886 | GEN_INT (64)), |
6887 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
6888 | |
6889 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 6890 | emit_clobber (operands[4]); |
4023fb28 UW |
6891 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
6892 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 6893 | |
4023fb28 | 6894 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6895 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
6896 | |
6897 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6898 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6899 | |
6900 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6901 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6902 | |
9db1d521 | 6903 | DONE; |
10bbf137 | 6904 | }) |
9db1d521 HP |
6905 | |
6906 | (define_insn "udivmodtidi3" | |
4023fb28 | 6907 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 6908 | (ior:TI |
5665e398 UW |
6909 | (ashift:TI |
6910 | (zero_extend:TI | |
6911 | (truncate:DI | |
2f7e5a0d EC |
6912 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
6913 | (zero_extend:TI | |
3e4be43f | 6914 | (match_operand:DI 2 "nonimmediate_operand" "d,T"))))) |
5665e398 UW |
6915 | (const_int 64)) |
6916 | (zero_extend:TI | |
6917 | (truncate:DI | |
6918 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9602b6a1 | 6919 | "TARGET_ZARCH" |
9db1d521 | 6920 | "@ |
d40c829f UW |
6921 | dlgr\t%0,%2 |
6922 | dlg\t%0,%2" | |
d3632d41 | 6923 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6924 | (set_attr "type" "idiv")]) |
9db1d521 HP |
6925 | |
6926 | ; | |
4023fb28 | 6927 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
6928 | ; |
6929 | ||
4023fb28 UW |
6930 | (define_expand "divmodsi4" |
6931 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
6932 | (div:SI (match_operand:SI 1 "general_operand" "") | |
6933 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
6934 | (set (match_operand:SI 3 "general_operand" "") | |
6935 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
6936 | (clobber (match_dup 4))] | |
9602b6a1 | 6937 | "!TARGET_ZARCH" |
9db1d521 | 6938 | { |
d8485bdb TS |
6939 | rtx div_equal, mod_equal, equal; |
6940 | rtx_insn *insn; | |
4023fb28 UW |
6941 | |
6942 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
6943 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
6944 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
6945 | gen_rtx_ASHIFT (DImode, |
6946 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
6947 | GEN_INT (32)), |
6948 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
6949 | |
6950 | operands[4] = gen_reg_rtx(DImode); | |
6951 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 6952 | |
4023fb28 | 6953 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6954 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
6955 | |
6956 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 6957 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6958 | |
6959 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 6960 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6961 | |
9db1d521 | 6962 | DONE; |
10bbf137 | 6963 | }) |
9db1d521 HP |
6964 | |
6965 | (define_insn "divmoddisi3" | |
4023fb28 | 6966 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 6967 | (ior:DI |
5665e398 UW |
6968 | (ashift:DI |
6969 | (zero_extend:DI | |
6970 | (truncate:SI | |
2f7e5a0d EC |
6971 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
6972 | (sign_extend:DI | |
5665e398 UW |
6973 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
6974 | (const_int 32)) | |
6975 | (zero_extend:DI | |
6976 | (truncate:SI | |
6977 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 6978 | "!TARGET_ZARCH" |
9db1d521 | 6979 | "@ |
d40c829f UW |
6980 | dr\t%0,%2 |
6981 | d\t%0,%2" | |
9db1d521 | 6982 | [(set_attr "op_type" "RR,RX") |
077dab3b | 6983 | (set_attr "type" "idiv")]) |
9db1d521 HP |
6984 | |
6985 | ; | |
6986 | ; udivsi3 and umodsi3 instruction pattern(s). | |
6987 | ; | |
6988 | ||
f1e77d83 UW |
6989 | (define_expand "udivmodsi4" |
6990 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
6991 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
6992 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
6993 | (set (match_operand:SI 3 "general_operand" "") | |
6994 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
6995 | (clobber (match_dup 4))] | |
8cc6307c | 6996 | "!TARGET_ZARCH" |
f1e77d83 | 6997 | { |
d8485bdb TS |
6998 | rtx div_equal, mod_equal, equal; |
6999 | rtx_insn *insn; | |
f1e77d83 UW |
7000 | |
7001 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
7002 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
7003 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
7004 | gen_rtx_ASHIFT (DImode, |
7005 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
7006 | GEN_INT (32)), |
7007 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
7008 | |
7009 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 7010 | emit_clobber (operands[4]); |
f1e77d83 UW |
7011 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
7012 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 7013 | |
f1e77d83 | 7014 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 7015 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
7016 | |
7017 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 7018 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
7019 | |
7020 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 7021 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
7022 | |
7023 | DONE; | |
7024 | }) | |
7025 | ||
7026 | (define_insn "udivmoddisi3" | |
7027 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 7028 | (ior:DI |
5665e398 UW |
7029 | (ashift:DI |
7030 | (zero_extend:DI | |
7031 | (truncate:SI | |
2f7e5a0d EC |
7032 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
7033 | (zero_extend:DI | |
3e4be43f | 7034 | (match_operand:SI 2 "nonimmediate_operand" "d,T"))))) |
5665e398 UW |
7035 | (const_int 32)) |
7036 | (zero_extend:DI | |
7037 | (truncate:SI | |
7038 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
8cc6307c | 7039 | "!TARGET_ZARCH" |
f1e77d83 UW |
7040 | "@ |
7041 | dlr\t%0,%2 | |
7042 | dl\t%0,%2" | |
7043 | [(set_attr "op_type" "RRE,RXY") | |
7044 | (set_attr "type" "idiv")]) | |
4023fb28 | 7045 | |
9db1d521 | 7046 | ; |
f5905b37 | 7047 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
7048 | ; |
7049 | ||
609e7e80 | 7050 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 7051 | (define_insn "div<mode>3" |
2de2b3f9 AK |
7052 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
7053 | (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v") | |
7054 | (match_operand:FP 2 "general_operand" "f,f,R,v,v")))] | |
142cd70f | 7055 | "TARGET_HARD_FLOAT" |
9db1d521 | 7056 | "@ |
62d3f261 AK |
7057 | d<xde>tr\t%0,%1,%2 |
7058 | d<xde>br\t%0,%2 | |
6e5b5de8 | 7059 | d<xde>b\t%0,%2 |
2de2b3f9 AK |
7060 | wfddb\t%v0,%v1,%v2 |
7061 | wfdsb\t%v0,%v1,%v2" | |
7062 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 7063 | (set_attr "type" "fdiv<mode>") |
2de2b3f9 AK |
7064 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
7065 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 7066 | |
9db1d521 HP |
7067 | |
7068 | ;; | |
7069 | ;;- And instructions. | |
7070 | ;; | |
7071 | ||
047d35ed AS |
7072 | (define_expand "and<mode>3" |
7073 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7074 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7075 | (match_operand:INT 2 "general_operand" ""))) | |
7076 | (clobber (reg:CC CC_REGNUM))] | |
7077 | "" | |
7078 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
7079 | ||
9db1d521 HP |
7080 | ; |
7081 | ; anddi3 instruction pattern(s). | |
7082 | ; | |
7083 | ||
7084 | (define_insn "*anddi3_cc" | |
ae156f85 | 7085 | [(set (reg CC_REGNUM) |
e3140518 | 7086 | (compare |
3e4be43f | 7087 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") |
c2586c82 | 7088 | (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) |
e3140518 | 7089 | (const_int 0))) |
3e4be43f | 7090 | (set (match_operand:DI 0 "register_operand" "=d,d,d, d") |
9db1d521 | 7091 | (and:DI (match_dup 1) (match_dup 2)))] |
e3140518 | 7092 | "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" |
9db1d521 | 7093 | "@ |
d40c829f | 7094 | ngr\t%0,%2 |
65b1d8ea | 7095 | ngrk\t%0,%1,%2 |
e3140518 RH |
7096 | ng\t%0,%2 |
7097 | risbg\t%0,%1,%s2,128+%e2,0" | |
7098 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
7099 | (set_attr "cpu_facility" "*,z196,*,z10") | |
7100 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7101 | |
7102 | (define_insn "*anddi3_cconly" | |
ae156f85 | 7103 | [(set (reg CC_REGNUM) |
e3140518 | 7104 | (compare |
3e4be43f | 7105 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") |
c2586c82 | 7106 | (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) |
9db1d521 | 7107 | (const_int 0))) |
3e4be43f | 7108 | (clobber (match_scratch:DI 0 "=d,d,d, d"))] |
e3140518 RH |
7109 | "TARGET_ZARCH |
7110 | && s390_match_ccmode(insn, CCTmode) | |
68f9c5e2 UW |
7111 | /* Do not steal TM patterns. */ |
7112 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 7113 | "@ |
d40c829f | 7114 | ngr\t%0,%2 |
65b1d8ea | 7115 | ngrk\t%0,%1,%2 |
e3140518 RH |
7116 | ng\t%0,%2 |
7117 | risbg\t%0,%1,%s2,128+%e2,0" | |
7118 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
7119 | (set_attr "cpu_facility" "*,z196,*,z10") | |
7120 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 7121 | |
3af8e996 | 7122 | (define_insn "*anddi3" |
65b1d8ea | 7123 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 7124 | "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q") |
e3140518 RH |
7125 | (and:DI |
7126 | (match_operand:DI 1 "nonimmediate_operand" | |
3e4be43f | 7127 | "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0") |
e3140518 | 7128 | (match_operand:DI 2 "general_operand" |
c2586c82 | 7129 | "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDw,NxQDF,Q"))) |
ec24698e | 7130 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7131 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7132 | "@ |
7133 | # | |
7134 | # | |
7135 | nihh\t%0,%j2 | |
7136 | nihl\t%0,%j2 | |
7137 | nilh\t%0,%j2 | |
7138 | nill\t%0,%j2 | |
7139 | nihf\t%0,%m2 | |
7140 | nilf\t%0,%m2 | |
7141 | ngr\t%0,%2 | |
65b1d8ea | 7142 | ngrk\t%0,%1,%2 |
ec24698e | 7143 | ng\t%0,%2 |
e3140518 | 7144 | risbg\t%0,%1,%s2,128+%e2,0 |
ec24698e UW |
7145 | # |
7146 | #" | |
e3140518 RH |
7147 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS") |
7148 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*") | |
9381e3f1 WG |
7149 | (set_attr "z10prop" "*, |
7150 | *, | |
7151 | z10_super_E1, | |
7152 | z10_super_E1, | |
7153 | z10_super_E1, | |
7154 | z10_super_E1, | |
7155 | z10_super_E1, | |
7156 | z10_super_E1, | |
7157 | z10_super_E1, | |
65b1d8ea | 7158 | *, |
9381e3f1 | 7159 | z10_super_E1, |
e3140518 | 7160 | z10_super_E1, |
9381e3f1 WG |
7161 | *, |
7162 | *")]) | |
0dfa6c5e UW |
7163 | |
7164 | (define_split | |
7165 | [(set (match_operand:DI 0 "s_operand" "") | |
7166 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7167 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7168 | "reload_completed" |
7169 | [(parallel | |
7170 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7171 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7172 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7173 | |
1a2e356e | 7174 | ;; These two are what combine generates for (ashift (zero_extract)). |
64c744b9 | 7175 | (define_insn "*extzv_<mode>_srl<clobbercc_or_nocc>" |
1a2e356e RH |
7176 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7177 | (and:GPR (lshiftrt:GPR | |
7178 | (match_operand:GPR 1 "register_operand" "d") | |
7179 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 7180 | (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] |
64c744b9 | 7181 | "<z10_or_zEC12_cond> |
1a2e356e RH |
7182 | /* Note that even for the SImode pattern, the rotate is always DImode. */ |
7183 | && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]), | |
7184 | INTVAL (operands[3]))" | |
64c744b9 | 7185 | "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2" |
1a2e356e RH |
7186 | [(set_attr "op_type" "RIE") |
7187 | (set_attr "z10prop" "z10_super_E1")]) | |
7188 | ||
64c744b9 | 7189 | (define_insn "*extzv_<mode>_sll<clobbercc_or_nocc>" |
1a2e356e RH |
7190 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7191 | (and:GPR (ashift:GPR | |
7192 | (match_operand:GPR 1 "register_operand" "d") | |
7193 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 7194 | (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] |
64c744b9 | 7195 | "<z10_or_zEC12_cond> |
1a2e356e RH |
7196 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]), |
7197 | INTVAL (operands[3]))" | |
64c744b9 | 7198 | "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,%2" |
1a2e356e RH |
7199 | [(set_attr "op_type" "RIE") |
7200 | (set_attr "z10prop" "z10_super_E1")]) | |
7201 | ||
9db1d521 HP |
7202 | |
7203 | ; | |
7204 | ; andsi3 instruction pattern(s). | |
7205 | ; | |
7206 | ||
7207 | (define_insn "*andsi3_cc" | |
ae156f85 | 7208 | [(set (reg CC_REGNUM) |
e3140518 RH |
7209 | (compare |
7210 | (and:SI | |
7211 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7212 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7213 | (const_int 0))) | |
7214 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d") | |
9db1d521 HP |
7215 | (and:SI (match_dup 1) (match_dup 2)))] |
7216 | "s390_match_ccmode(insn, CCTmode)" | |
7217 | "@ | |
ec24698e | 7218 | nilf\t%0,%o2 |
d40c829f | 7219 | nr\t%0,%2 |
65b1d8ea | 7220 | nrk\t%0,%1,%2 |
d40c829f | 7221 | n\t%0,%2 |
e3140518 RH |
7222 | ny\t%0,%2 |
7223 | risbg\t%0,%1,%t2,128+%f2,0" | |
7224 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
3e4be43f | 7225 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") |
e3140518 RH |
7226 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
7227 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7228 | |
7229 | (define_insn "*andsi3_cconly" | |
ae156f85 | 7230 | [(set (reg CC_REGNUM) |
e3140518 RH |
7231 | (compare |
7232 | (and:SI | |
7233 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7234 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7235 | (const_int 0))) | |
7236 | (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))] | |
68f9c5e2 UW |
7237 | "s390_match_ccmode(insn, CCTmode) |
7238 | /* Do not steal TM patterns. */ | |
7239 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 7240 | "@ |
ec24698e | 7241 | nilf\t%0,%o2 |
d40c829f | 7242 | nr\t%0,%2 |
65b1d8ea | 7243 | nrk\t%0,%1,%2 |
d40c829f | 7244 | n\t%0,%2 |
e3140518 RH |
7245 | ny\t%0,%2 |
7246 | risbg\t%0,%1,%t2,128+%f2,0" | |
7247 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
3e4be43f | 7248 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") |
65b1d8ea | 7249 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
e3140518 | 7250 | z10_super_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 7251 | |
f19a9af7 | 7252 | (define_insn "*andsi3_zarch" |
65b1d8ea | 7253 | [(set (match_operand:SI 0 "nonimmediate_operand" |
e3140518 | 7254 | "=d,d, d, d, d,d,d,d,d, d, AQ,Q") |
0dfa6c5e | 7255 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
e3140518 | 7256 | "%d,o, 0, 0, 0,0,d,0,0, d, 0,0") |
0dfa6c5e | 7257 | (match_operand:SI 2 "general_operand" |
c2586c82 | 7258 | " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSw,NxQSF,Q"))) |
ae156f85 | 7259 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7260 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7261 | "@ |
f19a9af7 AK |
7262 | # |
7263 | # | |
7264 | nilh\t%0,%j2 | |
2f7e5a0d | 7265 | nill\t%0,%j2 |
ec24698e | 7266 | nilf\t%0,%o2 |
d40c829f | 7267 | nr\t%0,%2 |
65b1d8ea | 7268 | nrk\t%0,%1,%2 |
d40c829f | 7269 | n\t%0,%2 |
8cb66696 | 7270 | ny\t%0,%2 |
e3140518 | 7271 | risbg\t%0,%1,%t2,128+%f2,0 |
0dfa6c5e | 7272 | # |
19b63d8e | 7273 | #" |
e3140518 | 7274 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") |
3e4be43f | 7275 | (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*") |
9381e3f1 WG |
7276 | (set_attr "z10prop" "*, |
7277 | *, | |
7278 | z10_super_E1, | |
7279 | z10_super_E1, | |
7280 | z10_super_E1, | |
7281 | z10_super_E1, | |
65b1d8ea | 7282 | *, |
9381e3f1 WG |
7283 | z10_super_E1, |
7284 | z10_super_E1, | |
e3140518 | 7285 | z10_super_E1, |
9381e3f1 WG |
7286 | *, |
7287 | *")]) | |
f19a9af7 AK |
7288 | |
7289 | (define_insn "*andsi3_esa" | |
65b1d8ea AK |
7290 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") |
7291 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") | |
7292 | (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) | |
ae156f85 | 7293 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7294 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7295 | "@ |
7296 | nr\t%0,%2 | |
8cb66696 | 7297 | n\t%0,%2 |
0dfa6c5e | 7298 | # |
19b63d8e | 7299 | #" |
9381e3f1 WG |
7300 | [(set_attr "op_type" "RR,RX,SI,SS") |
7301 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
7302 | ||
0dfa6c5e UW |
7303 | |
7304 | (define_split | |
7305 | [(set (match_operand:SI 0 "s_operand" "") | |
7306 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7307 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7308 | "reload_completed" |
7309 | [(parallel | |
7310 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7311 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7312 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7313 | |
9db1d521 HP |
7314 | ; |
7315 | ; andhi3 instruction pattern(s). | |
7316 | ; | |
7317 | ||
8cb66696 | 7318 | (define_insn "*andhi3_zarch" |
65b1d8ea AK |
7319 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7320 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7321 | (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) | |
ae156f85 | 7322 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7323 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7324 | "@ |
d40c829f | 7325 | nr\t%0,%2 |
65b1d8ea | 7326 | nrk\t%0,%1,%2 |
8cb66696 | 7327 | nill\t%0,%x2 |
0dfa6c5e | 7328 | # |
19b63d8e | 7329 | #" |
65b1d8ea AK |
7330 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7331 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7332 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") | |
9381e3f1 | 7333 | ]) |
8cb66696 UW |
7334 | |
7335 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
7336 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7337 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7338 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 7339 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7340 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7341 | "@ | |
7342 | nr\t%0,%2 | |
0dfa6c5e | 7343 | # |
19b63d8e | 7344 | #" |
9381e3f1 WG |
7345 | [(set_attr "op_type" "RR,SI,SS") |
7346 | (set_attr "z10prop" "z10_super_E1,*,*") | |
7347 | ]) | |
0dfa6c5e UW |
7348 | |
7349 | (define_split | |
7350 | [(set (match_operand:HI 0 "s_operand" "") | |
7351 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7352 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7353 | "reload_completed" |
7354 | [(parallel | |
7355 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7356 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7357 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 7358 | |
9db1d521 HP |
7359 | ; |
7360 | ; andqi3 instruction pattern(s). | |
7361 | ; | |
7362 | ||
8cb66696 | 7363 | (define_insn "*andqi3_zarch" |
65b1d8ea AK |
7364 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7365 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7366 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7367 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7368 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7369 | "@ |
d40c829f | 7370 | nr\t%0,%2 |
65b1d8ea | 7371 | nrk\t%0,%1,%2 |
8cb66696 | 7372 | nill\t%0,%b2 |
fc0ea003 UW |
7373 | ni\t%S0,%b2 |
7374 | niy\t%S0,%b2 | |
19b63d8e | 7375 | #" |
65b1d8ea | 7376 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
3e4be43f | 7377 | (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") |
65b1d8ea | 7378 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) |
8cb66696 UW |
7379 | |
7380 | (define_insn "*andqi3_esa" | |
7381 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7382 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7383 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7384 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7385 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7386 | "@ |
8cb66696 | 7387 | nr\t%0,%2 |
fc0ea003 | 7388 | ni\t%S0,%b2 |
19b63d8e | 7389 | #" |
9381e3f1 WG |
7390 | [(set_attr "op_type" "RR,SI,SS") |
7391 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 7392 | |
deb9351f DV |
7393 | ; |
7394 | ; And with complement | |
7395 | ; | |
7396 | ; c = ~b & a = (b & a) ^ a | |
7397 | ||
7398 | (define_insn_and_split "*andc_split_<mode>" | |
7399 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
7400 | (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" "")) | |
7401 | (match_operand:GPR 2 "general_operand" ""))) | |
7402 | (clobber (reg:CC CC_REGNUM))] | |
ad7ab32e DV |
7403 | "! reload_completed |
7404 | && (GET_CODE (operands[0]) != MEM | |
7405 | /* Ensure that s390_logical_operator_ok_p will succeed even | |
7406 | on the split xor if (b & a) is stored into a pseudo. */ | |
7407 | || rtx_equal_p (operands[0], operands[2]))" | |
deb9351f DV |
7408 | "#" |
7409 | "&& 1" | |
7410 | [ | |
7411 | (parallel | |
7412 | [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2))) | |
7413 | (clobber (reg:CC CC_REGNUM))]) | |
7414 | (parallel | |
7415 | [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2))) | |
7416 | (clobber (reg:CC CC_REGNUM))])] | |
7417 | { | |
7418 | if (reg_overlap_mentioned_p (operands[0], operands[2])) | |
7419 | operands[3] = gen_reg_rtx (<MODE>mode); | |
7420 | else | |
7421 | operands[3] = operands[0]; | |
7422 | }) | |
7423 | ||
19b63d8e UW |
7424 | ; |
7425 | ; Block and (NC) patterns. | |
7426 | ; | |
7427 | ||
7428 | (define_insn "*nc" | |
7429 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7430 | (and:BLK (match_dup 0) | |
7431 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7432 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7433 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7434 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7435 | "nc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7436 | [(set_attr "op_type" "SS") |
7437 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7438 | |
7439 | (define_split | |
7440 | [(set (match_operand 0 "memory_operand" "") | |
7441 | (and (match_dup 0) | |
7442 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7443 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7444 | "reload_completed |
7445 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7446 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7447 | [(parallel | |
7448 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
7449 | (use (match_dup 2)) | |
ae156f85 | 7450 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7451 | { |
7452 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7453 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7454 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7455 | }) | |
7456 | ||
7457 | (define_peephole2 | |
7458 | [(parallel | |
7459 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7460 | (and:BLK (match_dup 0) | |
7461 | (match_operand:BLK 1 "memory_operand" ""))) | |
7462 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7463 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7464 | (parallel |
7465 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7466 | (and:BLK (match_dup 3) | |
7467 | (match_operand:BLK 4 "memory_operand" ""))) | |
7468 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7469 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7470 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7471 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7472 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7473 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7474 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7475 | [(parallel | |
7476 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
7477 | (use (match_dup 8)) | |
ae156f85 | 7478 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7479 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7480 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7481 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7482 | ||
9db1d521 HP |
7483 | |
7484 | ;; | |
7485 | ;;- Bit set (inclusive or) instructions. | |
7486 | ;; | |
7487 | ||
047d35ed AS |
7488 | (define_expand "ior<mode>3" |
7489 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7490 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7491 | (match_operand:INT 2 "general_operand" ""))) | |
7492 | (clobber (reg:CC CC_REGNUM))] | |
7493 | "" | |
7494 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
7495 | ||
9db1d521 HP |
7496 | ; |
7497 | ; iordi3 instruction pattern(s). | |
7498 | ; | |
7499 | ||
4023fb28 | 7500 | (define_insn "*iordi3_cc" |
ae156f85 | 7501 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7502 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7503 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7504 | (const_int 0))) |
3e4be43f | 7505 | (set (match_operand:DI 0 "register_operand" "=d,d,d") |
4023fb28 | 7506 | (ior:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7507 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7508 | "@ |
d40c829f | 7509 | ogr\t%0,%2 |
65b1d8ea | 7510 | ogrk\t%0,%1,%2 |
d40c829f | 7511 | og\t%0,%2" |
65b1d8ea AK |
7512 | [(set_attr "op_type" "RRE,RRF,RXY") |
7513 | (set_attr "cpu_facility" "*,z196,*") | |
7514 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 UW |
7515 | |
7516 | (define_insn "*iordi3_cconly" | |
ae156f85 | 7517 | [(set (reg CC_REGNUM) |
65b1d8ea | 7518 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
3e4be43f | 7519 | (match_operand:DI 2 "general_operand" " d,d,T")) |
4023fb28 | 7520 | (const_int 0))) |
65b1d8ea | 7521 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 7522 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7523 | "@ |
d40c829f | 7524 | ogr\t%0,%2 |
65b1d8ea | 7525 | ogrk\t%0,%1,%2 |
d40c829f | 7526 | og\t%0,%2" |
65b1d8ea AK |
7527 | [(set_attr "op_type" "RRE,RRF,RXY") |
7528 | (set_attr "cpu_facility" "*,z196,*") | |
7529 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7530 | |
3af8e996 | 7531 | (define_insn "*iordi3" |
65b1d8ea | 7532 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 7533 | "=d, d, d, d, d, d,d,d,d, AQ,Q") |
65b1d8ea | 7534 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" |
3e4be43f | 7535 | " %0, 0, 0, 0, 0, 0,0,d,0, 0,0") |
ec24698e | 7536 | (match_operand:DI 2 "general_operand" |
3e4be43f | 7537 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q"))) |
ec24698e | 7538 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7539 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7540 | "@ |
7541 | oihh\t%0,%i2 | |
7542 | oihl\t%0,%i2 | |
7543 | oilh\t%0,%i2 | |
7544 | oill\t%0,%i2 | |
7545 | oihf\t%0,%k2 | |
7546 | oilf\t%0,%k2 | |
7547 | ogr\t%0,%2 | |
65b1d8ea | 7548 | ogrk\t%0,%1,%2 |
ec24698e UW |
7549 | og\t%0,%2 |
7550 | # | |
7551 | #" | |
65b1d8ea AK |
7552 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
7553 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
7554 | (set_attr "z10prop" "z10_super_E1, |
7555 | z10_super_E1, | |
7556 | z10_super_E1, | |
7557 | z10_super_E1, | |
7558 | z10_super_E1, | |
7559 | z10_super_E1, | |
7560 | z10_super_E1, | |
65b1d8ea | 7561 | *, |
9381e3f1 WG |
7562 | z10_super_E1, |
7563 | *, | |
7564 | *")]) | |
0dfa6c5e UW |
7565 | |
7566 | (define_split | |
7567 | [(set (match_operand:DI 0 "s_operand" "") | |
7568 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7569 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7570 | "reload_completed" |
7571 | [(parallel | |
7572 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7573 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7574 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7575 | |
9db1d521 HP |
7576 | ; |
7577 | ; iorsi3 instruction pattern(s). | |
7578 | ; | |
7579 | ||
4023fb28 | 7580 | (define_insn "*iorsi3_cc" |
ae156f85 | 7581 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7582 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7583 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7584 | (const_int 0))) |
65b1d8ea | 7585 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7586 | (ior:SI (match_dup 1) (match_dup 2)))] |
7587 | "s390_match_ccmode(insn, CCTmode)" | |
7588 | "@ | |
ec24698e | 7589 | oilf\t%0,%o2 |
d40c829f | 7590 | or\t%0,%2 |
65b1d8ea | 7591 | ork\t%0,%1,%2 |
d40c829f UW |
7592 | o\t%0,%2 |
7593 | oy\t%0,%2" | |
65b1d8ea | 7594 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7595 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea | 7596 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
4023fb28 UW |
7597 | |
7598 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 7599 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7600 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7601 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7602 | (const_int 0))) |
65b1d8ea | 7603 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7604 | "s390_match_ccmode(insn, CCTmode)" |
7605 | "@ | |
ec24698e | 7606 | oilf\t%0,%o2 |
d40c829f | 7607 | or\t%0,%2 |
65b1d8ea | 7608 | ork\t%0,%1,%2 |
d40c829f UW |
7609 | o\t%0,%2 |
7610 | oy\t%0,%2" | |
65b1d8ea | 7611 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7612 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea | 7613 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
4023fb28 | 7614 | |
8cb66696 | 7615 | (define_insn "*iorsi3_zarch" |
65b1d8ea AK |
7616 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") |
7617 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") | |
7618 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7619 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7620 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7621 | "@ |
f19a9af7 AK |
7622 | oilh\t%0,%i2 |
7623 | oill\t%0,%i2 | |
ec24698e | 7624 | oilf\t%0,%o2 |
d40c829f | 7625 | or\t%0,%2 |
65b1d8ea | 7626 | ork\t%0,%1,%2 |
d40c829f | 7627 | o\t%0,%2 |
8cb66696 | 7628 | oy\t%0,%2 |
0dfa6c5e | 7629 | # |
19b63d8e | 7630 | #" |
65b1d8ea | 7631 | [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
3e4be43f | 7632 | (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*") |
9381e3f1 WG |
7633 | (set_attr "z10prop" "z10_super_E1, |
7634 | z10_super_E1, | |
7635 | z10_super_E1, | |
7636 | z10_super_E1, | |
65b1d8ea | 7637 | *, |
9381e3f1 WG |
7638 | z10_super_E1, |
7639 | z10_super_E1, | |
7640 | *, | |
7641 | *")]) | |
8cb66696 UW |
7642 | |
7643 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 7644 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 7645 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 7646 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 7647 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7648 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7649 | "@ |
7650 | or\t%0,%2 | |
8cb66696 | 7651 | o\t%0,%2 |
0dfa6c5e | 7652 | # |
19b63d8e | 7653 | #" |
9381e3f1 WG |
7654 | [(set_attr "op_type" "RR,RX,SI,SS") |
7655 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7656 | |
7657 | (define_split | |
7658 | [(set (match_operand:SI 0 "s_operand" "") | |
7659 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7660 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7661 | "reload_completed" |
7662 | [(parallel | |
7663 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7664 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7665 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7666 | |
4023fb28 UW |
7667 | ; |
7668 | ; iorhi3 instruction pattern(s). | |
7669 | ; | |
7670 | ||
8cb66696 | 7671 | (define_insn "*iorhi3_zarch" |
65b1d8ea AK |
7672 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7673 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7674 | (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) | |
ae156f85 | 7675 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7676 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7677 | "@ |
d40c829f | 7678 | or\t%0,%2 |
65b1d8ea | 7679 | ork\t%0,%1,%2 |
8cb66696 | 7680 | oill\t%0,%x2 |
0dfa6c5e | 7681 | # |
19b63d8e | 7682 | #" |
65b1d8ea AK |
7683 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7684 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7685 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) | |
8cb66696 UW |
7686 | |
7687 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
7688 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7689 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7690 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 7691 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7692 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7693 | "@ | |
7694 | or\t%0,%2 | |
0dfa6c5e | 7695 | # |
19b63d8e | 7696 | #" |
9381e3f1 WG |
7697 | [(set_attr "op_type" "RR,SI,SS") |
7698 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7699 | |
7700 | (define_split | |
7701 | [(set (match_operand:HI 0 "s_operand" "") | |
7702 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7703 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7704 | "reload_completed" |
7705 | [(parallel | |
7706 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7707 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7708 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 7709 | |
9db1d521 | 7710 | ; |
4023fb28 | 7711 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
7712 | ; |
7713 | ||
8cb66696 | 7714 | (define_insn "*iorqi3_zarch" |
65b1d8ea AK |
7715 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7716 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7717 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7718 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7719 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7720 | "@ |
d40c829f | 7721 | or\t%0,%2 |
65b1d8ea | 7722 | ork\t%0,%1,%2 |
8cb66696 | 7723 | oill\t%0,%b2 |
fc0ea003 UW |
7724 | oi\t%S0,%b2 |
7725 | oiy\t%S0,%b2 | |
19b63d8e | 7726 | #" |
65b1d8ea | 7727 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
3e4be43f | 7728 | (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") |
65b1d8ea AK |
7729 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, |
7730 | z10_super,z10_super,*")]) | |
8cb66696 UW |
7731 | |
7732 | (define_insn "*iorqi3_esa" | |
7733 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7734 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7735 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7736 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7737 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7738 | "@ |
8cb66696 | 7739 | or\t%0,%2 |
fc0ea003 | 7740 | oi\t%S0,%b2 |
19b63d8e | 7741 | #" |
9381e3f1 WG |
7742 | [(set_attr "op_type" "RR,SI,SS") |
7743 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 7744 | |
19b63d8e UW |
7745 | ; |
7746 | ; Block inclusive or (OC) patterns. | |
7747 | ; | |
7748 | ||
7749 | (define_insn "*oc" | |
7750 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7751 | (ior:BLK (match_dup 0) | |
7752 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7753 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7754 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7755 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7756 | "oc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7757 | [(set_attr "op_type" "SS") |
7758 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7759 | |
7760 | (define_split | |
7761 | [(set (match_operand 0 "memory_operand" "") | |
7762 | (ior (match_dup 0) | |
7763 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7764 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7765 | "reload_completed |
7766 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7767 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7768 | [(parallel | |
7769 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
7770 | (use (match_dup 2)) | |
ae156f85 | 7771 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7772 | { |
7773 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7774 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7775 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7776 | }) | |
7777 | ||
7778 | (define_peephole2 | |
7779 | [(parallel | |
7780 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7781 | (ior:BLK (match_dup 0) | |
7782 | (match_operand:BLK 1 "memory_operand" ""))) | |
7783 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7784 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7785 | (parallel |
7786 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7787 | (ior:BLK (match_dup 3) | |
7788 | (match_operand:BLK 4 "memory_operand" ""))) | |
7789 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7790 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7791 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7792 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7793 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7794 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7795 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7796 | [(parallel | |
7797 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
7798 | (use (match_dup 8)) | |
ae156f85 | 7799 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7800 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7801 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7802 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7803 | ||
9db1d521 HP |
7804 | |
7805 | ;; | |
7806 | ;;- Xor instructions. | |
7807 | ;; | |
7808 | ||
047d35ed AS |
7809 | (define_expand "xor<mode>3" |
7810 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7811 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7812 | (match_operand:INT 2 "general_operand" ""))) | |
7813 | (clobber (reg:CC CC_REGNUM))] | |
7814 | "" | |
7815 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
7816 | ||
3c91f126 AK |
7817 | ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing |
7818 | ; simplifications. So its better to have something matching. | |
7819 | (define_split | |
7820 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7821 | (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))] | |
7822 | "" | |
7823 | [(parallel | |
7824 | [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2))) | |
7825 | (clobber (reg:CC CC_REGNUM))])] | |
7826 | { | |
7827 | operands[2] = constm1_rtx; | |
7828 | if (!s390_logical_operator_ok_p (operands)) | |
7829 | FAIL; | |
7830 | }) | |
7831 | ||
9db1d521 HP |
7832 | ; |
7833 | ; xordi3 instruction pattern(s). | |
7834 | ; | |
7835 | ||
4023fb28 | 7836 | (define_insn "*xordi3_cc" |
ae156f85 | 7837 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7838 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7839 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7840 | (const_int 0))) |
3e4be43f | 7841 | (set (match_operand:DI 0 "register_operand" "=d,d,d") |
4023fb28 | 7842 | (xor:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7843 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7844 | "@ |
d40c829f | 7845 | xgr\t%0,%2 |
65b1d8ea | 7846 | xgrk\t%0,%1,%2 |
d40c829f | 7847 | xg\t%0,%2" |
65b1d8ea | 7848 | [(set_attr "op_type" "RRE,RRF,RXY") |
5490de28 | 7849 | (set_attr "cpu_facility" "*,z196,*") |
65b1d8ea | 7850 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) |
4023fb28 UW |
7851 | |
7852 | (define_insn "*xordi3_cconly" | |
ae156f85 | 7853 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7854 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7855 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7856 | (const_int 0))) |
3e4be43f | 7857 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 7858 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7859 | "@ |
d40c829f | 7860 | xgr\t%0,%2 |
65b1d8ea | 7861 | xgrk\t%0,%1,%2 |
c7fd8cd8 | 7862 | xg\t%0,%2" |
65b1d8ea AK |
7863 | [(set_attr "op_type" "RRE,RRF,RXY") |
7864 | (set_attr "cpu_facility" "*,z196,*") | |
7865 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7866 | |
3af8e996 | 7867 | (define_insn "*xordi3" |
3e4be43f UW |
7868 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q") |
7869 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0") | |
7870 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q"))) | |
ec24698e | 7871 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7872 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7873 | "@ |
7874 | xihf\t%0,%k2 | |
7875 | xilf\t%0,%k2 | |
7876 | xgr\t%0,%2 | |
65b1d8ea | 7877 | xgrk\t%0,%1,%2 |
ec24698e UW |
7878 | xg\t%0,%2 |
7879 | # | |
7880 | #" | |
65b1d8ea AK |
7881 | [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") |
7882 | (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") | |
7883 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, | |
7884 | *,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7885 | |
7886 | (define_split | |
7887 | [(set (match_operand:DI 0 "s_operand" "") | |
7888 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7889 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7890 | "reload_completed" |
7891 | [(parallel | |
7892 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7893 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7894 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 7895 | |
9db1d521 HP |
7896 | ; |
7897 | ; xorsi3 instruction pattern(s). | |
7898 | ; | |
7899 | ||
4023fb28 | 7900 | (define_insn "*xorsi3_cc" |
ae156f85 | 7901 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7902 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7903 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7904 | (const_int 0))) |
65b1d8ea | 7905 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7906 | (xor:SI (match_dup 1) (match_dup 2)))] |
7907 | "s390_match_ccmode(insn, CCTmode)" | |
7908 | "@ | |
ec24698e | 7909 | xilf\t%0,%o2 |
d40c829f | 7910 | xr\t%0,%2 |
65b1d8ea | 7911 | xrk\t%0,%1,%2 |
d40c829f UW |
7912 | x\t%0,%2 |
7913 | xy\t%0,%2" | |
65b1d8ea | 7914 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7915 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea AK |
7916 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
7917 | z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
7918 | |
7919 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 7920 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7921 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7922 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7923 | (const_int 0))) |
65b1d8ea | 7924 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7925 | "s390_match_ccmode(insn, CCTmode)" |
7926 | "@ | |
ec24698e | 7927 | xilf\t%0,%o2 |
d40c829f | 7928 | xr\t%0,%2 |
65b1d8ea | 7929 | xrk\t%0,%1,%2 |
d40c829f UW |
7930 | x\t%0,%2 |
7931 | xy\t%0,%2" | |
65b1d8ea | 7932 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7933 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea AK |
7934 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
7935 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 7936 | |
8cb66696 | 7937 | (define_insn "*xorsi3" |
65b1d8ea AK |
7938 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") |
7939 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") | |
7940 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7941 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7942 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 7943 | "@ |
ec24698e | 7944 | xilf\t%0,%o2 |
d40c829f | 7945 | xr\t%0,%2 |
65b1d8ea | 7946 | xrk\t%0,%1,%2 |
d40c829f | 7947 | x\t%0,%2 |
8cb66696 | 7948 | xy\t%0,%2 |
0dfa6c5e | 7949 | # |
19b63d8e | 7950 | #" |
65b1d8ea | 7951 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") |
3e4be43f | 7952 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*") |
65b1d8ea AK |
7953 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
7954 | z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7955 | |
7956 | (define_split | |
7957 | [(set (match_operand:SI 0 "s_operand" "") | |
7958 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7959 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7960 | "reload_completed" |
7961 | [(parallel | |
7962 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7963 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7964 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 7965 | |
9db1d521 HP |
7966 | ; |
7967 | ; xorhi3 instruction pattern(s). | |
7968 | ; | |
7969 | ||
8cb66696 | 7970 | (define_insn "*xorhi3" |
65b1d8ea AK |
7971 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7972 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") | |
7973 | (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) | |
ae156f85 | 7974 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7975 | "s390_logical_operator_ok_p (operands)" |
7976 | "@ | |
ec24698e | 7977 | xilf\t%0,%x2 |
8cb66696 | 7978 | xr\t%0,%2 |
65b1d8ea | 7979 | xrk\t%0,%1,%2 |
0dfa6c5e | 7980 | # |
19b63d8e | 7981 | #" |
65b1d8ea AK |
7982 | [(set_attr "op_type" "RIL,RR,RRF,SI,SS") |
7983 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7984 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) | |
0dfa6c5e UW |
7985 | |
7986 | (define_split | |
7987 | [(set (match_operand:HI 0 "s_operand" "") | |
7988 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7989 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7990 | "reload_completed" |
7991 | [(parallel | |
7992 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7993 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7994 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 7995 | |
9db1d521 HP |
7996 | ; |
7997 | ; xorqi3 instruction pattern(s). | |
7998 | ; | |
7999 | ||
8cb66696 | 8000 | (define_insn "*xorqi3" |
65b1d8ea AK |
8001 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
8002 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") | |
8003 | (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) | |
ae156f85 | 8004 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8005 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 8006 | "@ |
ec24698e | 8007 | xilf\t%0,%b2 |
8cb66696 | 8008 | xr\t%0,%2 |
65b1d8ea | 8009 | xrk\t%0,%1,%2 |
fc0ea003 UW |
8010 | xi\t%S0,%b2 |
8011 | xiy\t%S0,%b2 | |
19b63d8e | 8012 | #" |
65b1d8ea | 8013 | [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") |
3e4be43f | 8014 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,*") |
65b1d8ea | 8015 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) |
9381e3f1 | 8016 | |
4023fb28 | 8017 | |
19b63d8e UW |
8018 | ; |
8019 | ; Block exclusive or (XC) patterns. | |
8020 | ; | |
8021 | ||
8022 | (define_insn "*xc" | |
8023 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8024 | (xor:BLK (match_dup 0) | |
8025 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
8026 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 8027 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8028 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 8029 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 8030 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
8031 | |
8032 | (define_split | |
8033 | [(set (match_operand 0 "memory_operand" "") | |
8034 | (xor (match_dup 0) | |
8035 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 8036 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
8037 | "reload_completed |
8038 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
8039 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
8040 | [(parallel | |
8041 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
8042 | (use (match_dup 2)) | |
ae156f85 | 8043 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8044 | { |
8045 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
8046 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
8047 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
8048 | }) | |
8049 | ||
8050 | (define_peephole2 | |
8051 | [(parallel | |
8052 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8053 | (xor:BLK (match_dup 0) | |
8054 | (match_operand:BLK 1 "memory_operand" ""))) | |
8055 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 8056 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8057 | (parallel |
8058 | [(set (match_operand:BLK 3 "memory_operand" "") | |
8059 | (xor:BLK (match_dup 3) | |
8060 | (match_operand:BLK 4 "memory_operand" ""))) | |
8061 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 8062 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8063 | "s390_offset_p (operands[0], operands[3], operands[2]) |
8064 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 8065 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 8066 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
8067 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
8068 | [(parallel | |
8069 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
8070 | (use (match_dup 8)) | |
ae156f85 | 8071 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8072 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8073 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
8074 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
8075 | ||
8076 | ; | |
8077 | ; Block xor (XC) patterns with src == dest. | |
8078 | ; | |
8079 | ||
8080 | (define_insn "*xc_zero" | |
8081 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8082 | (const_int 0)) | |
8083 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 8084 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8085 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 8086 | "xc\t%O0(%1,%R0),%S0" |
65b1d8ea AK |
8087 | [(set_attr "op_type" "SS") |
8088 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
8089 | |
8090 | (define_peephole2 | |
8091 | [(parallel | |
8092 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8093 | (const_int 0)) | |
8094 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 8095 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8096 | (parallel |
8097 | [(set (match_operand:BLK 2 "memory_operand" "") | |
8098 | (const_int 0)) | |
8099 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 8100 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8101 | "s390_offset_p (operands[0], operands[2], operands[1]) |
8102 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
8103 | [(parallel | |
8104 | [(set (match_dup 4) (const_int 0)) | |
8105 | (use (match_dup 5)) | |
ae156f85 | 8106 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8107 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8108 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
8109 | ||
9db1d521 HP |
8110 | |
8111 | ;; | |
8112 | ;;- Negate instructions. | |
8113 | ;; | |
8114 | ||
8115 | ; | |
9a91a21f | 8116 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
8117 | ; |
8118 | ||
9a91a21f | 8119 | (define_expand "neg<mode>2" |
9db1d521 | 8120 | [(parallel |
9a91a21f AS |
8121 | [(set (match_operand:DSI 0 "register_operand" "=d") |
8122 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 8123 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8124 | "" |
8125 | "") | |
8126 | ||
26a89301 | 8127 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 8128 | [(set (reg CC_REGNUM) |
26a89301 UW |
8129 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8130 | (match_operand:SI 1 "register_operand" "d") 0) | |
8131 | (const_int 32)) (const_int 32))) | |
8132 | (const_int 0))) | |
8133 | (set (match_operand:DI 0 "register_operand" "=d") | |
8134 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8135 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8136 | "lcgfr\t%0,%1" |
729e750f WG |
8137 | [(set_attr "op_type" "RRE") |
8138 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8139 | |
26a89301 UW |
8140 | (define_insn "*negdi2_sign" |
8141 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8142 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8143 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8144 | "TARGET_ZARCH" |
26a89301 | 8145 | "lcgfr\t%0,%1" |
729e750f WG |
8146 | [(set_attr "op_type" "RRE") |
8147 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8148 | |
43a09b63 | 8149 | ; lcr, lcgr |
9a91a21f | 8150 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8151 | [(set (reg CC_REGNUM) |
9a91a21f | 8152 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8153 | (const_int 0))) |
9a91a21f AS |
8154 | (set (match_operand:GPR 0 "register_operand" "=d") |
8155 | (neg:GPR (match_dup 1)))] | |
8156 | "s390_match_ccmode (insn, CCAmode)" | |
8157 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8158 | [(set_attr "op_type" "RR<E>") |
8159 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
8160 | |
8161 | ; lcr, lcgr | |
9a91a21f | 8162 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8163 | [(set (reg CC_REGNUM) |
9a91a21f | 8164 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8165 | (const_int 0))) |
9a91a21f AS |
8166 | (clobber (match_scratch:GPR 0 "=d"))] |
8167 | "s390_match_ccmode (insn, CCAmode)" | |
8168 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8169 | [(set_attr "op_type" "RR<E>") |
8170 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
8171 | |
8172 | ; lcr, lcgr | |
9a91a21f AS |
8173 | (define_insn "*neg<mode>2" |
8174 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8175 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8176 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
8177 | "" |
8178 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8179 | [(set_attr "op_type" "RR<E>") |
8180 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 8181 | |
b7d19263 | 8182 | (define_insn "*negdi2_31" |
9db1d521 HP |
8183 | [(set (match_operand:DI 0 "register_operand" "=d") |
8184 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 8185 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8186 | "!TARGET_ZARCH" |
b7d19263 AK |
8187 | "#") |
8188 | ||
8189 | ; Split a DImode NEG on 31bit into 2 SImode NEGs | |
8190 | ||
8191 | ; Doing the twos complement separately on the SImode parts does an | |
8192 | ; unwanted +1 on the high part which needs to be subtracted afterwards | |
8193 | ; ... unless the +1 on the low part created an overflow. | |
8194 | ||
8195 | (define_split | |
8196 | [(set (match_operand:DI 0 "register_operand" "") | |
8197 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8198 | (clobber (reg:CC CC_REGNUM))] | |
8199 | "!TARGET_ZARCH | |
8200 | && (REGNO (operands[0]) == REGNO (operands[1]) | |
8201 | || s390_split_ok_p (operands[0], operands[1], DImode, 0)) | |
8202 | && reload_completed" | |
26a89301 UW |
8203 | [(parallel |
8204 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 8205 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 8206 | (parallel |
ae156f85 | 8207 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
8208 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
8209 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
8210 | (set (pc) | |
ae156f85 | 8211 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
8212 | (pc) |
8213 | (label_ref (match_dup 6)))) | |
8214 | (parallel | |
8215 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 8216 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
8217 | (match_dup 6)] |
8218 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8219 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8220 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8221 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8222 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 8223 | |
b7d19263 AK |
8224 | ; Like above but first make a copy of the low part of the src operand |
8225 | ; since it might overlap with the high part of the destination. | |
8226 | ||
8227 | (define_split | |
8228 | [(set (match_operand:DI 0 "register_operand" "") | |
8229 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8230 | (clobber (reg:CC CC_REGNUM))] | |
8231 | "!TARGET_ZARCH | |
8232 | && s390_split_ok_p (operands[0], operands[1], DImode, 1) | |
8233 | && reload_completed" | |
8234 | [; Make a backup of op5 first | |
8235 | (set (match_dup 4) (match_dup 5)) | |
8236 | ; Setting op2 here might clobber op5 | |
8237 | (parallel | |
8238 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
8239 | (clobber (reg:CC CC_REGNUM))]) | |
8240 | (parallel | |
8241 | [(set (reg:CCAP CC_REGNUM) | |
8242 | (compare:CCAP (neg:SI (match_dup 4)) (const_int 0))) | |
8243 | (set (match_dup 4) (neg:SI (match_dup 4)))]) | |
8244 | (set (pc) | |
8245 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) | |
8246 | (pc) | |
8247 | (label_ref (match_dup 6)))) | |
8248 | (parallel | |
8249 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
8250 | (clobber (reg:CC CC_REGNUM))]) | |
8251 | (match_dup 6)] | |
8252 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8253 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8254 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8255 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8256 | operands[6] = gen_label_rtx ();") | |
8257 | ||
9db1d521 | 8258 | ; |
f5905b37 | 8259 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8260 | ; |
8261 | ||
f5905b37 | 8262 | (define_expand "neg<mode>2" |
9db1d521 | 8263 | [(parallel |
2de2b3f9 AK |
8264 | [(set (match_operand:BFP 0 "register_operand") |
8265 | (neg:BFP (match_operand:BFP 1 "register_operand"))) | |
ae156f85 | 8266 | (clobber (reg:CC CC_REGNUM))])] |
2de2b3f9 | 8267 | "TARGET_HARD_FLOAT") |
9db1d521 | 8268 | |
43a09b63 | 8269 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 8270 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8271 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8272 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8273 | (match_operand:BFP 2 "const0_operand" ""))) | |
8274 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8275 | (neg:BFP (match_dup 1)))] | |
142cd70f | 8276 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8277 | "lc<xde>br\t%0,%1" |
26a89301 | 8278 | [(set_attr "op_type" "RRE") |
f5905b37 | 8279 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8280 | |
8281 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 8282 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8283 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8284 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8285 | (match_operand:BFP 2 "const0_operand" ""))) | |
8286 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8287 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8288 | "lc<xde>br\t%0,%1" |
26a89301 | 8289 | [(set_attr "op_type" "RRE") |
f5905b37 | 8290 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8291 | |
85dae55a AK |
8292 | ; lcdfr |
8293 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
8294 | [(set (match_operand:FP 0 "register_operand" "=f") |
8295 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8296 | "TARGET_DFP" |
85dae55a AK |
8297 | "lcdfr\t%0,%1" |
8298 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8299 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8300 | |
43a09b63 | 8301 | ; lcxbr, lcdbr, lcebr |
6e5b5de8 | 8302 | ; FIXME: wflcdb does not clobber cc |
2de2b3f9 | 8303 | ; FIXME: Does wflcdb ever match here? |
f5905b37 | 8304 | (define_insn "*neg<mode>2" |
2de2b3f9 AK |
8305 | [(set (match_operand:BFP 0 "register_operand" "=f,v,v") |
8306 | (neg:BFP (match_operand:BFP 1 "register_operand" "f,v,v"))) | |
ae156f85 | 8307 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8308 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8309 | "@ |
8310 | lc<xde>br\t%0,%1 | |
2de2b3f9 AK |
8311 | wflcdb\t%0,%1 |
8312 | wflcsb\t%0,%1" | |
8313 | [(set_attr "op_type" "RRE,VRR,VRR") | |
8314 | (set_attr "cpu_facility" "*,vx,vxe") | |
8315 | (set_attr "type" "fsimp<mode>,*,*") | |
8316 | (set_attr "enabled" "*,<DF>,<SF>")]) | |
9db1d521 | 8317 | |
9db1d521 HP |
8318 | |
8319 | ;; | |
8320 | ;;- Absolute value instructions. | |
8321 | ;; | |
8322 | ||
8323 | ; | |
9a91a21f | 8324 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
8325 | ; |
8326 | ||
26a89301 | 8327 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 8328 | [(set (reg CC_REGNUM) |
26a89301 UW |
8329 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8330 | (match_operand:SI 1 "register_operand" "d") 0) | |
8331 | (const_int 32)) (const_int 32))) | |
8332 | (const_int 0))) | |
8333 | (set (match_operand:DI 0 "register_operand" "=d") | |
8334 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8335 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8336 | "lpgfr\t%0,%1" |
729e750f WG |
8337 | [(set_attr "op_type" "RRE") |
8338 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
8339 | |
8340 | (define_insn "*absdi2_sign" | |
8341 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8342 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8343 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8344 | "TARGET_ZARCH" |
26a89301 | 8345 | "lpgfr\t%0,%1" |
729e750f WG |
8346 | [(set_attr "op_type" "RRE") |
8347 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8348 | |
43a09b63 | 8349 | ; lpr, lpgr |
9a91a21f | 8350 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8351 | [(set (reg CC_REGNUM) |
9a91a21f | 8352 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 8353 | (const_int 0))) |
9a91a21f AS |
8354 | (set (match_operand:GPR 0 "register_operand" "=d") |
8355 | (abs:GPR (match_dup 1)))] | |
26a89301 | 8356 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8357 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8358 | [(set_attr "op_type" "RR<E>") |
8359 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 8360 | |
9381e3f1 | 8361 | ; lpr, lpgr |
9a91a21f | 8362 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8363 | [(set (reg CC_REGNUM) |
9a91a21f | 8364 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8365 | (const_int 0))) |
9a91a21f | 8366 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8367 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8368 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8369 | [(set_attr "op_type" "RR<E>") |
8370 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8371 | |
8372 | ; lpr, lpgr | |
9a91a21f AS |
8373 | (define_insn "abs<mode>2" |
8374 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8375 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8376 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 8377 | "" |
9a91a21f | 8378 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8379 | [(set_attr "op_type" "RR<E>") |
8380 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 8381 | |
9db1d521 | 8382 | ; |
f5905b37 | 8383 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8384 | ; |
8385 | ||
f5905b37 | 8386 | (define_expand "abs<mode>2" |
9db1d521 | 8387 | [(parallel |
7b6baae1 AK |
8388 | [(set (match_operand:BFP 0 "register_operand" "=f") |
8389 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 8390 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8391 | "TARGET_HARD_FLOAT" |
8392 | "") | |
8393 | ||
43a09b63 | 8394 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 8395 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8396 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8397 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8398 | (match_operand:BFP 2 "const0_operand" ""))) | |
8399 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8400 | (abs:BFP (match_dup 1)))] | |
142cd70f | 8401 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8402 | "lp<xde>br\t%0,%1" |
26a89301 | 8403 | [(set_attr "op_type" "RRE") |
f5905b37 | 8404 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8405 | |
8406 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 8407 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8408 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8409 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8410 | (match_operand:BFP 2 "const0_operand" ""))) | |
8411 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8412 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8413 | "lp<xde>br\t%0,%1" |
26a89301 | 8414 | [(set_attr "op_type" "RRE") |
f5905b37 | 8415 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8416 | |
85dae55a AK |
8417 | ; lpdfr |
8418 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
8419 | [(set (match_operand:FP 0 "register_operand" "=f") |
8420 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8421 | "TARGET_DFP" |
85dae55a AK |
8422 | "lpdfr\t%0,%1" |
8423 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8424 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8425 | |
43a09b63 | 8426 | ; lpxbr, lpdbr, lpebr |
6e5b5de8 | 8427 | ; FIXME: wflpdb does not clobber cc |
f5905b37 | 8428 | (define_insn "*abs<mode>2" |
62d3f261 AK |
8429 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8430 | (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))) | |
ae156f85 | 8431 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8432 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8433 | "@ |
8434 | lp<xde>br\t%0,%1 | |
8435 | wflpdb\t%0,%1" | |
8436 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8437 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8438 | (set_attr "type" "fsimp<mode>,*") |
8439 | (set_attr "enabled" "*,<DFDI>")]) | |
9db1d521 | 8440 | |
9db1d521 | 8441 | |
3ef093a8 AK |
8442 | ;; |
8443 | ;;- Negated absolute value instructions | |
8444 | ;; | |
8445 | ||
8446 | ; | |
8447 | ; Integer | |
8448 | ; | |
8449 | ||
26a89301 | 8450 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 8451 | [(set (reg CC_REGNUM) |
26a89301 UW |
8452 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8453 | (match_operand:SI 1 "register_operand" "d") 0) | |
8454 | (const_int 32)) (const_int 32)))) | |
8455 | (const_int 0))) | |
8456 | (set (match_operand:DI 0 "register_operand" "=d") | |
8457 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
9602b6a1 | 8458 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8459 | "lngfr\t%0,%1" |
729e750f WG |
8460 | [(set_attr "op_type" "RRE") |
8461 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8462 | |
26a89301 UW |
8463 | (define_insn "*negabsdi2_sign" |
8464 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8465 | (neg:DI (abs:DI (sign_extend:DI | |
8466 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 8467 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8468 | "TARGET_ZARCH" |
26a89301 | 8469 | "lngfr\t%0,%1" |
729e750f WG |
8470 | [(set_attr "op_type" "RRE") |
8471 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 8472 | |
43a09b63 | 8473 | ; lnr, lngr |
9a91a21f | 8474 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8475 | [(set (reg CC_REGNUM) |
9a91a21f | 8476 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8477 | (const_int 0))) |
9a91a21f AS |
8478 | (set (match_operand:GPR 0 "register_operand" "=d") |
8479 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 8480 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8481 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8482 | [(set_attr "op_type" "RR<E>") |
8483 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8484 | |
8485 | ; lnr, lngr | |
9a91a21f | 8486 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8487 | [(set (reg CC_REGNUM) |
9a91a21f | 8488 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8489 | (const_int 0))) |
9a91a21f | 8490 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8491 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8492 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8493 | [(set_attr "op_type" "RR<E>") |
8494 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8495 | |
8496 | ; lnr, lngr | |
9a91a21f AS |
8497 | (define_insn "*negabs<mode>2" |
8498 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8499 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 8500 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 8501 | "" |
9a91a21f | 8502 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8503 | [(set_attr "op_type" "RR<E>") |
8504 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8505 | |
3ef093a8 AK |
8506 | ; |
8507 | ; Floating point | |
8508 | ; | |
8509 | ||
43a09b63 | 8510 | ; lnxbr, lndbr, lnebr |
f5905b37 | 8511 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8512 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8513 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8514 | (match_operand:BFP 2 "const0_operand" ""))) | |
8515 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8516 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 8517 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8518 | "ln<xde>br\t%0,%1" |
26a89301 | 8519 | [(set_attr "op_type" "RRE") |
f5905b37 | 8520 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8521 | |
8522 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 8523 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8524 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8525 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8526 | (match_operand:BFP 2 "const0_operand" ""))) | |
8527 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8528 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8529 | "ln<xde>br\t%0,%1" |
26a89301 | 8530 | [(set_attr "op_type" "RRE") |
f5905b37 | 8531 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8532 | |
85dae55a AK |
8533 | ; lndfr |
8534 | (define_insn "*negabs<mode>2_nocc" | |
609e7e80 AK |
8535 | [(set (match_operand:FP 0 "register_operand" "=f") |
8536 | (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 8537 | "TARGET_DFP" |
85dae55a AK |
8538 | "lndfr\t%0,%1" |
8539 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8540 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8541 | |
43a09b63 | 8542 | ; lnxbr, lndbr, lnebr |
6e5b5de8 | 8543 | ; FIXME: wflndb does not clobber cc |
f5905b37 | 8544 | (define_insn "*negabs<mode>2" |
62d3f261 AK |
8545 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8546 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))) | |
ae156f85 | 8547 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8548 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8549 | "@ |
8550 | ln<xde>br\t%0,%1 | |
8551 | wflndb\t%0,%1" | |
8552 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8553 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8554 | (set_attr "type" "fsimp<mode>,*") |
8555 | (set_attr "enabled" "*,<DFDI>")]) | |
26a89301 | 8556 | |
4023fb28 UW |
8557 | ;; |
8558 | ;;- Square root instructions. | |
8559 | ;; | |
8560 | ||
8561 | ; | |
f5905b37 | 8562 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
8563 | ; |
8564 | ||
9381e3f1 | 8565 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 8566 | (define_insn "sqrt<mode>2" |
62d3f261 AK |
8567 | [(set (match_operand:BFP 0 "register_operand" "=f,f,v") |
8568 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))] | |
142cd70f | 8569 | "TARGET_HARD_FLOAT" |
4023fb28 | 8570 | "@ |
f61a2c7d | 8571 | sq<xde>br\t%0,%1 |
6e5b5de8 AK |
8572 | sq<xde>b\t%0,%1 |
8573 | wfsqdb\t%v0,%v1" | |
8574 | [(set_attr "op_type" "RRE,RXE,VRR") | |
8575 | (set_attr "type" "fsqrt<mode>") | |
285363a1 | 8576 | (set_attr "cpu_facility" "*,*,vx") |
62d3f261 | 8577 | (set_attr "enabled" "*,<DSF>,<DFDI>")]) |
4023fb28 | 8578 | |
9db1d521 HP |
8579 | |
8580 | ;; | |
8581 | ;;- One complement instructions. | |
8582 | ;; | |
8583 | ||
8584 | ; | |
342cf42b | 8585 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 8586 | ; |
c7453384 | 8587 | |
342cf42b | 8588 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 8589 | [(parallel |
342cf42b AS |
8590 | [(set (match_operand:INT 0 "register_operand" "") |
8591 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
8592 | (const_int -1))) | |
ae156f85 | 8593 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 8594 | "" |
4023fb28 | 8595 | "") |
9db1d521 HP |
8596 | |
8597 | ||
ec24698e UW |
8598 | ;; |
8599 | ;; Find leftmost bit instructions. | |
8600 | ;; | |
8601 | ||
8602 | (define_expand "clzdi2" | |
8603 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8604 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 8605 | "TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e | 8606 | { |
d8485bdb TS |
8607 | rtx_insn *insn; |
8608 | rtx clz_equal; | |
ec24698e | 8609 | rtx wide_reg = gen_reg_rtx (TImode); |
406fde6e | 8610 | rtx msb = gen_rtx_CONST_INT (DImode, HOST_WIDE_INT_1U << 63); |
ec24698e UW |
8611 | |
8612 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
8613 | ||
8614 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
8615 | ||
9381e3f1 | 8616 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 8617 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
8618 | |
8619 | DONE; | |
8620 | }) | |
8621 | ||
8622 | (define_insn "clztidi2" | |
8623 | [(set (match_operand:TI 0 "register_operand" "=d") | |
8624 | (ior:TI | |
9381e3f1 WG |
8625 | (ashift:TI |
8626 | (zero_extend:TI | |
ec24698e UW |
8627 | (xor:DI (match_operand:DI 1 "register_operand" "d") |
8628 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
8629 | (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
9381e3f1 | 8630 | |
ec24698e UW |
8631 | (const_int 64)) |
8632 | (zero_extend:TI (clz:DI (match_dup 1))))) | |
8633 | (clobber (reg:CC CC_REGNUM))] | |
406fde6e | 8634 | "UINTVAL (operands[2]) == HOST_WIDE_INT_1U << 63 |
9602b6a1 | 8635 | && TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
8636 | "flogr\t%0,%1" |
8637 | [(set_attr "op_type" "RRE")]) | |
8638 | ||
8639 | ||
9db1d521 HP |
8640 | ;; |
8641 | ;;- Rotate instructions. | |
8642 | ;; | |
8643 | ||
8644 | ; | |
9a91a21f | 8645 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
8646 | ; |
8647 | ||
191eb16d AK |
8648 | (define_expand "rotl<mode>3" |
8649 | [(set (match_operand:GPR 0 "register_operand" "") | |
8650 | (rotate:GPR (match_operand:GPR 1 "register_operand" "") | |
8651 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
8cc6307c | 8652 | "" |
191eb16d | 8653 | "") |
9db1d521 | 8654 | |
43a09b63 | 8655 | ; rll, rllg |
191eb16d AK |
8656 | (define_insn "*rotl<mode>3<addr_style_op><masked_op>" |
8657 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8658 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
8659 | (match_operand:SI 2 "nonmemory_operand" "an")))] | |
8cc6307c | 8660 | "" |
191eb16d | 8661 | "rll<g>\t%0,%1,<addr_style_op_ops>" |
4989e88a | 8662 | [(set_attr "op_type" "RSE") |
9381e3f1 | 8663 | (set_attr "atype" "reg") |
191eb16d | 8664 | (set_attr "z10prop" "z10_super_E1")]) |
4989e88a | 8665 | |
9db1d521 HP |
8666 | |
8667 | ;; | |
f337b930 | 8668 | ;;- Shift instructions. |
9db1d521 | 8669 | ;; |
9db1d521 HP |
8670 | |
8671 | ; | |
1b48c8cc | 8672 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
65b1d8ea | 8673 | ; Left shifts and logical right shifts |
9db1d521 | 8674 | |
1b48c8cc AS |
8675 | (define_expand "<shift><mode>3" |
8676 | [(set (match_operand:DSI 0 "register_operand" "") | |
8677 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
adf22b3f | 8678 | (match_operand:SI 2 "nonmemory_operand" "")))] |
9db1d521 HP |
8679 | "" |
8680 | "") | |
8681 | ||
adf22b3f | 8682 | ; ESA 64 bit register pair shift with reg or imm shift count |
43a09b63 | 8683 | ; sldl, srdl |
adf22b3f AK |
8684 | (define_insn "*<shift>di3_31<addr_style_op><masked_op>" |
8685 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8686 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
8687 | (match_operand:SI 2 "nonmemory_operand" "an")))] | |
9602b6a1 | 8688 | "!TARGET_ZARCH" |
adf22b3f | 8689 | "s<lr>dl\t%0,<addr_style_op_ops>" |
077dab3b | 8690 | [(set_attr "op_type" "RS") |
65b1d8ea AK |
8691 | (set_attr "atype" "reg") |
8692 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8693 | |
adf22b3f AK |
8694 | |
8695 | ; 64 bit register shift with reg or imm shift count | |
65b1d8ea | 8696 | ; sll, srl, sllg, srlg, sllk, srlk |
adf22b3f AK |
8697 | (define_insn "*<shift><mode>3<addr_style_op><masked_op>" |
8698 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
8699 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
8700 | (match_operand:SI 2 "nonmemory_operand" "an,an")))] | |
1b48c8cc | 8701 | "" |
65b1d8ea | 8702 | "@ |
adf22b3f AK |
8703 | s<lr>l<g>\t%0,<1><addr_style_op_ops> |
8704 | s<lr>l<gk>\t%0,%1,<addr_style_op_ops>" | |
65b1d8ea AK |
8705 | [(set_attr "op_type" "RS<E>,RSY") |
8706 | (set_attr "atype" "reg,reg") | |
8707 | (set_attr "cpu_facility" "*,z196") | |
adf22b3f | 8708 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8709 | |
9db1d521 | 8710 | ; |
1b48c8cc | 8711 | ; ashr(di|si)3 instruction pattern(s). |
65b1d8ea | 8712 | ; Arithmetic right shifts |
9db1d521 | 8713 | |
1b48c8cc | 8714 | (define_expand "ashr<mode>3" |
9db1d521 | 8715 | [(parallel |
1b48c8cc AS |
8716 | [(set (match_operand:DSI 0 "register_operand" "") |
8717 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
a9fcf821 | 8718 | (match_operand:SI 2 "nonmemory_operand" ""))) |
ae156f85 | 8719 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8720 | "" |
8721 | "") | |
8722 | ||
a9fcf821 AK |
8723 | ; FIXME: The number of alternatives is doubled here to match the fix |
8724 | ; number of 2 in the subst pattern for the (clobber (match_scratch... | |
8725 | ; The right fix should be to support match_scratch in the output | |
8726 | ; pattern of a define_subst. | |
8727 | (define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>" | |
8728 | [(set (match_operand:DI 0 "register_operand" "=d, d") | |
8729 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0, 0") | |
8730 | (match_operand:SI 2 "nonmemory_operand" "an,an"))) | |
ae156f85 | 8731 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8732 | "!TARGET_ZARCH" |
65b1d8ea | 8733 | "@ |
a9fcf821 AK |
8734 | srda\t%0,<addr_style_op_cc_ops> |
8735 | srda\t%0,<addr_style_op_cc_ops>" | |
8736 | [(set_attr "op_type" "RS") | |
8737 | (set_attr "atype" "reg")]) | |
ecbe845e | 8738 | |
ecbe845e | 8739 | |
43a09b63 | 8740 | ; sra, srag |
a9fcf821 AK |
8741 | (define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>" |
8742 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
8743 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
8744 | (match_operand:SI 2 "nonmemory_operand" "an,an"))) | |
ae156f85 | 8745 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc | 8746 | "" |
65b1d8ea | 8747 | "@ |
a9fcf821 AK |
8748 | sra<g>\t%0,<1><addr_style_op_cc_ops> |
8749 | sra<gk>\t%0,%1,<addr_style_op_cc_ops>" | |
65b1d8ea | 8750 | [(set_attr "op_type" "RS<E>,RSY") |
a9fcf821 | 8751 | (set_attr "atype" "reg") |
01496eca | 8752 | (set_attr "cpu_facility" "*,z196") |
65b1d8ea | 8753 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8754 | |
9db1d521 | 8755 | |
9db1d521 HP |
8756 | ;; |
8757 | ;; Branch instruction patterns. | |
8758 | ;; | |
8759 | ||
f90b7a5a | 8760 | (define_expand "cbranch<mode>4" |
fa77b251 | 8761 | [(set (pc) |
f90b7a5a PB |
8762 | (if_then_else (match_operator 0 "comparison_operator" |
8763 | [(match_operand:GPR 1 "register_operand" "") | |
8764 | (match_operand:GPR 2 "general_operand" "")]) | |
8765 | (label_ref (match_operand 3 "" "")) | |
fa77b251 | 8766 | (pc)))] |
ba956982 | 8767 | "" |
f90b7a5a PB |
8768 | "s390_emit_jump (operands[3], |
8769 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8770 | DONE;") | |
8771 | ||
8772 | (define_expand "cbranch<mode>4" | |
8773 | [(set (pc) | |
8774 | (if_then_else (match_operator 0 "comparison_operator" | |
8775 | [(match_operand:FP 1 "register_operand" "") | |
8776 | (match_operand:FP 2 "general_operand" "")]) | |
8777 | (label_ref (match_operand 3 "" "")) | |
8778 | (pc)))] | |
8779 | "TARGET_HARD_FLOAT" | |
8780 | "s390_emit_jump (operands[3], | |
8781 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8782 | DONE;") | |
8783 | ||
8784 | (define_expand "cbranchcc4" | |
8785 | [(set (pc) | |
de6fba39 | 8786 | (if_then_else (match_operator 0 "s390_comparison" |
f90b7a5a | 8787 | [(match_operand 1 "cc_reg_operand" "") |
de6fba39 | 8788 | (match_operand 2 "const_int_operand" "")]) |
f90b7a5a PB |
8789 | (label_ref (match_operand 3 "" "")) |
8790 | (pc)))] | |
de6fba39 UW |
8791 | "" |
8792 | "") | |
ba956982 | 8793 | |
9db1d521 HP |
8794 | |
8795 | ;; | |
8796 | ;;- Conditional jump instructions. | |
8797 | ;; | |
8798 | ||
6590e19a UW |
8799 | (define_insn "*cjump_64" |
8800 | [(set (pc) | |
8801 | (if_then_else | |
5a3fe9b6 AK |
8802 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
8803 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
8804 | (label_ref (match_operand 0 "" "")) |
8805 | (pc)))] | |
8cc6307c | 8806 | "" |
9db1d521 | 8807 | { |
13e58269 | 8808 | if (get_attr_length (insn) == 4) |
d40c829f | 8809 | return "j%C1\t%l0"; |
6590e19a | 8810 | else |
d40c829f | 8811 | return "jg%C1\t%l0"; |
6590e19a UW |
8812 | } |
8813 | [(set_attr "op_type" "RI") | |
8814 | (set_attr "type" "branch") | |
8815 | (set (attr "length") | |
8816 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8817 | (const_int 4) (const_int 6)))]) | |
8818 | ||
f314b9b1 | 8819 | (define_insn "*cjump_long" |
6590e19a UW |
8820 | [(set (pc) |
8821 | (if_then_else | |
ae156f85 | 8822 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4fe6dea8 | 8823 | (match_operand 0 "address_operand" "ZQZR") |
6590e19a | 8824 | (pc)))] |
84b4c7b5 | 8825 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
f314b9b1 UW |
8826 | { |
8827 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8828 | return "b%C1r\t%0"; |
f314b9b1 | 8829 | else |
d40c829f | 8830 | return "b%C1\t%a0"; |
10bbf137 | 8831 | } |
c7453384 | 8832 | [(set (attr "op_type") |
f314b9b1 UW |
8833 | (if_then_else (match_operand 0 "register_operand" "") |
8834 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
8835 | (set (attr "mnemonic") |
8836 | (if_then_else (match_operand 0 "register_operand" "") | |
8837 | (const_string "bcr") (const_string "bc"))) | |
6590e19a | 8838 | (set_attr "type" "branch") |
077dab3b | 8839 | (set_attr "atype" "agen")]) |
9db1d521 | 8840 | |
177bc204 RS |
8841 | ;; A conditional return instruction. |
8842 | (define_insn "*c<code>" | |
8843 | [(set (pc) | |
8844 | (if_then_else | |
8845 | (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
8846 | (ANY_RETURN) | |
8847 | (pc)))] | |
8848 | "s390_can_use_<code>_insn ()" | |
84b4c7b5 AK |
8849 | { |
8850 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
8851 | { | |
8852 | s390_indirect_branch_via_thunk (RETURN_REGNUM, | |
8853 | INVALID_REGNUM, | |
8854 | operands[0], | |
8855 | s390_indirect_branch_type_return); | |
8856 | return ""; | |
8857 | } | |
8858 | else | |
8859 | return "b%C0r\t%%r14"; | |
8860 | } | |
8861 | [(set (attr "op_type") | |
8862 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
8863 | (const_string "RIL") | |
8864 | (const_string "RR"))) | |
8865 | (set (attr "mnemonic") | |
8866 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
8867 | (const_string "brcl") | |
8868 | (const_string "bcr"))) | |
177bc204 RS |
8869 | (set_attr "type" "jsr") |
8870 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
8871 | |
8872 | ;; | |
8873 | ;;- Negated conditional jump instructions. | |
8874 | ;; | |
8875 | ||
6590e19a UW |
8876 | (define_insn "*icjump_64" |
8877 | [(set (pc) | |
8878 | (if_then_else | |
ae156f85 | 8879 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
8880 | (pc) |
8881 | (label_ref (match_operand 0 "" ""))))] | |
8cc6307c | 8882 | "" |
c7453384 | 8883 | { |
13e58269 | 8884 | if (get_attr_length (insn) == 4) |
d40c829f | 8885 | return "j%D1\t%l0"; |
6590e19a | 8886 | else |
d40c829f | 8887 | return "jg%D1\t%l0"; |
6590e19a UW |
8888 | } |
8889 | [(set_attr "op_type" "RI") | |
8890 | (set_attr "type" "branch") | |
8891 | (set (attr "length") | |
8892 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8893 | (const_int 4) (const_int 6)))]) | |
8894 | ||
f314b9b1 | 8895 | (define_insn "*icjump_long" |
6590e19a UW |
8896 | [(set (pc) |
8897 | (if_then_else | |
ae156f85 | 8898 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a | 8899 | (pc) |
4fe6dea8 | 8900 | (match_operand 0 "address_operand" "ZQZR")))] |
84b4c7b5 | 8901 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
f314b9b1 UW |
8902 | { |
8903 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8904 | return "b%D1r\t%0"; |
f314b9b1 | 8905 | else |
d40c829f | 8906 | return "b%D1\t%a0"; |
10bbf137 | 8907 | } |
c7453384 | 8908 | [(set (attr "op_type") |
f314b9b1 UW |
8909 | (if_then_else (match_operand 0 "register_operand" "") |
8910 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
8911 | (set (attr "mnemonic") |
8912 | (if_then_else (match_operand 0 "register_operand" "") | |
8913 | (const_string "bcr") (const_string "bc"))) | |
077dab3b HP |
8914 | (set_attr "type" "branch") |
8915 | (set_attr "atype" "agen")]) | |
9db1d521 | 8916 | |
4456530d HP |
8917 | ;; |
8918 | ;;- Trap instructions. | |
8919 | ;; | |
8920 | ||
8921 | (define_insn "trap" | |
8922 | [(trap_if (const_int 1) (const_int 0))] | |
8923 | "" | |
d40c829f | 8924 | "j\t.+2" |
6590e19a | 8925 | [(set_attr "op_type" "RI") |
077dab3b | 8926 | (set_attr "type" "branch")]) |
4456530d | 8927 | |
f90b7a5a PB |
8928 | (define_expand "ctrap<mode>4" |
8929 | [(trap_if (match_operator 0 "comparison_operator" | |
8930 | [(match_operand:GPR 1 "register_operand" "") | |
8931 | (match_operand:GPR 2 "general_operand" "")]) | |
8932 | (match_operand 3 "const0_operand" ""))] | |
4456530d | 8933 | "" |
f90b7a5a PB |
8934 | { |
8935 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
8936 | operands[1], operands[2]); | |
8937 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
8938 | DONE; | |
8939 | }) | |
8940 | ||
8941 | (define_expand "ctrap<mode>4" | |
8942 | [(trap_if (match_operator 0 "comparison_operator" | |
8943 | [(match_operand:FP 1 "register_operand" "") | |
8944 | (match_operand:FP 2 "general_operand" "")]) | |
8945 | (match_operand 3 "const0_operand" ""))] | |
8946 | "" | |
8947 | { | |
8948 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
8949 | operands[1], operands[2]); | |
8950 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
8951 | DONE; | |
8952 | }) | |
4456530d | 8953 | |
f90b7a5a PB |
8954 | (define_insn "condtrap" |
8955 | [(trap_if (match_operator 0 "s390_comparison" | |
8956 | [(match_operand 1 "cc_reg_operand" "c") | |
8957 | (const_int 0)]) | |
4456530d HP |
8958 | (const_int 0))] |
8959 | "" | |
d40c829f | 8960 | "j%C0\t.+2"; |
077dab3b HP |
8961 | [(set_attr "op_type" "RI") |
8962 | (set_attr "type" "branch")]) | |
9db1d521 | 8963 | |
963fc8d0 AK |
8964 | ; crt, cgrt, cit, cgit |
8965 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
8966 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
8967 | [(match_operand:GPR 1 "register_operand" "d,d") | |
8968 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
8969 | (const_int 0))] | |
8970 | "TARGET_Z10" | |
8971 | "@ | |
8972 | c<g>rt%C0\t%1,%2 | |
8973 | c<g>it%C0\t%1,%h2" | |
8974 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 8975 | (set_attr "type" "branch") |
729e750f | 8976 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 8977 | |
22ac2c2f | 8978 | ; clrt, clgrt, clfit, clgit, clt, clgt |
963fc8d0 AK |
8979 | (define_insn "*cmp_and_trap_unsigned_int<mode>" |
8980 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
3e4be43f UW |
8981 | [(match_operand:GPR 1 "register_operand" "d,d,d") |
8982 | (match_operand:GPR 2 "general_operand" "d,D,T")]) | |
963fc8d0 AK |
8983 | (const_int 0))] |
8984 | "TARGET_Z10" | |
8985 | "@ | |
8986 | cl<g>rt%C0\t%1,%2 | |
22ac2c2f AK |
8987 | cl<gf>it%C0\t%1,%x2 |
8988 | cl<g>t%C0\t%1,%2" | |
8989 | [(set_attr "op_type" "RRF,RIE,RSY") | |
8990 | (set_attr "type" "branch") | |
8991 | (set_attr "z10prop" "z10_super_c,z10_super,*") | |
8992 | (set_attr "cpu_facility" "z10,z10,zEC12")]) | |
8993 | ||
8994 | ; lat, lgat | |
8995 | (define_insn "*load_and_trap<mode>" | |
3e4be43f | 8996 | [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T") |
22ac2c2f AK |
8997 | (const_int 0)) |
8998 | (const_int 0)) | |
8999 | (set (match_operand:GPR 1 "register_operand" "=d") | |
9000 | (match_dup 0))] | |
9001 | "TARGET_ZEC12" | |
9002 | "l<g>at\t%1,%0" | |
9003 | [(set_attr "op_type" "RXY")]) | |
9004 | ||
963fc8d0 | 9005 | |
9db1d521 | 9006 | ;; |
0a3bdf9d | 9007 | ;;- Loop instructions. |
9db1d521 | 9008 | ;; |
0a3bdf9d UW |
9009 | ;; This is all complicated by the fact that since this is a jump insn |
9010 | ;; we must handle our own output reloads. | |
c7453384 | 9011 | |
f1149235 AK |
9012 | ;; branch on index |
9013 | ||
9014 | ; This splitter will be matched by combine and has to add the 2 moves | |
9015 | ; necessary to load the compare and the increment values into a | |
9016 | ; register pair as needed by brxle. | |
9017 | ||
9018 | (define_insn_and_split "*brx_stage1_<GPR:mode>" | |
9019 | [(set (pc) | |
9020 | (if_then_else | |
9021 | (match_operator 6 "s390_brx_operator" | |
9022 | [(plus:GPR (match_operand:GPR 1 "register_operand" "") | |
9023 | (match_operand:GPR 2 "general_operand" "")) | |
9024 | (match_operand:GPR 3 "register_operand" "")]) | |
9025 | (label_ref (match_operand 0 "" "")) | |
9026 | (pc))) | |
9027 | (set (match_operand:GPR 4 "nonimmediate_operand" "") | |
9028 | (plus:GPR (match_dup 1) (match_dup 2))) | |
9029 | (clobber (match_scratch:GPR 5 ""))] | |
8cc6307c | 9030 | "" |
f1149235 AK |
9031 | "#" |
9032 | "!reload_completed && !reload_in_progress" | |
9033 | [(set (match_dup 7) (match_dup 2)) ; the increment | |
9034 | (set (match_dup 8) (match_dup 3)) ; the comparison value | |
9035 | (parallel [(set (pc) | |
9036 | (if_then_else | |
9037 | (match_op_dup 6 | |
9038 | [(plus:GPR (match_dup 1) (match_dup 7)) | |
9039 | (match_dup 8)]) | |
9040 | (label_ref (match_dup 0)) | |
9041 | (pc))) | |
9042 | (set (match_dup 4) | |
9043 | (plus:GPR (match_dup 1) (match_dup 7))) | |
9044 | (clobber (match_dup 5)) | |
9045 | (clobber (reg:CC CC_REGNUM))])] | |
9046 | { | |
9047 | rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); | |
9048 | operands[7] = gen_lowpart (<GPR:MODE>mode, | |
9049 | gen_highpart (word_mode, dreg)); | |
9050 | operands[8] = gen_lowpart (<GPR:MODE>mode, | |
9051 | gen_lowpart (word_mode, dreg)); | |
9052 | }) | |
9053 | ||
9054 | ; brxlg, brxhg | |
9055 | ||
9056 | (define_insn_and_split "*brxg_64bit" | |
9057 | [(set (pc) | |
9058 | (if_then_else | |
9059 | (match_operator 5 "s390_brx_operator" | |
9060 | [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") | |
9061 | (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) | |
9062 | (subreg:DI (match_dup 2) 8)]) | |
9063 | (label_ref (match_operand 0 "" "")) | |
9064 | (pc))) | |
9065 | (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") | |
9066 | (plus:DI (match_dup 1) | |
9067 | (subreg:DI (match_dup 2) 0))) | |
9068 | (clobber (match_scratch:DI 4 "=X,&1,&?d")) | |
9069 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9070 | "TARGET_ZARCH" |
f1149235 AK |
9071 | { |
9072 | if (which_alternative != 0) | |
9073 | return "#"; | |
9074 | else if (get_attr_length (insn) == 6) | |
9075 | return "brx%E5g\t%1,%2,%l0"; | |
9076 | else | |
9077 | return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; | |
9078 | } | |
9079 | "&& reload_completed | |
9080 | && (!REG_P (operands[3]) | |
9081 | || !rtx_equal_p (operands[1], operands[3]))" | |
9082 | [(set (match_dup 4) (match_dup 1)) | |
9083 | (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) | |
9084 | (clobber (reg:CC CC_REGNUM))]) | |
9085 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) | |
9086 | (set (match_dup 3) (match_dup 4)) | |
9087 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9088 | (label_ref (match_dup 0)) | |
9089 | (pc)))] | |
9090 | "" | |
9091 | [(set_attr "op_type" "RIE") | |
9092 | (set_attr "type" "branch") | |
9093 | (set (attr "length") | |
9094 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9095 | (const_int 6) (const_int 16)))]) | |
9096 | ||
9097 | ; brxle, brxh | |
9098 | ||
9099 | (define_insn_and_split "*brx_64bit" | |
9100 | [(set (pc) | |
9101 | (if_then_else | |
9102 | (match_operator 5 "s390_brx_operator" | |
9103 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9104 | (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) | |
9105 | (subreg:SI (match_dup 2) 12)]) | |
9106 | (label_ref (match_operand 0 "" "")) | |
9107 | (pc))) | |
9108 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9109 | (plus:SI (match_dup 1) | |
9110 | (subreg:SI (match_dup 2) 4))) | |
9111 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9112 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9113 | "TARGET_ZARCH" |
f1149235 AK |
9114 | { |
9115 | if (which_alternative != 0) | |
9116 | return "#"; | |
9117 | else if (get_attr_length (insn) == 6) | |
9118 | return "brx%C5\t%1,%2,%l0"; | |
9119 | else | |
9120 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9121 | } | |
9122 | "&& reload_completed | |
9123 | && (!REG_P (operands[3]) | |
9124 | || !rtx_equal_p (operands[1], operands[3]))" | |
9125 | [(set (match_dup 4) (match_dup 1)) | |
9126 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9127 | (clobber (reg:CC CC_REGNUM))]) | |
9128 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) | |
9129 | (set (match_dup 3) (match_dup 4)) | |
9130 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9131 | (label_ref (match_dup 0)) | |
9132 | (pc)))] | |
9133 | "" | |
9134 | [(set_attr "op_type" "RSI") | |
9135 | (set_attr "type" "branch") | |
9136 | (set (attr "length") | |
9137 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9138 | (const_int 6) (const_int 14)))]) | |
9139 | ||
9140 | ; brxle, brxh | |
9141 | ||
9142 | (define_insn_and_split "*brx_31bit" | |
9143 | [(set (pc) | |
9144 | (if_then_else | |
9145 | (match_operator 5 "s390_brx_operator" | |
9146 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9147 | (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) | |
9148 | (subreg:SI (match_dup 2) 4)]) | |
9149 | (label_ref (match_operand 0 "" "")) | |
9150 | (pc))) | |
9151 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9152 | (plus:SI (match_dup 1) | |
9153 | (subreg:SI (match_dup 2) 0))) | |
9154 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9155 | (clobber (reg:CC CC_REGNUM))] | |
8cc6307c | 9156 | "!TARGET_ZARCH" |
f1149235 AK |
9157 | { |
9158 | if (which_alternative != 0) | |
9159 | return "#"; | |
9160 | else if (get_attr_length (insn) == 6) | |
9161 | return "brx%C5\t%1,%2,%l0"; | |
9162 | else | |
9163 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9164 | } | |
9165 | "&& reload_completed | |
9166 | && (!REG_P (operands[3]) | |
9167 | || !rtx_equal_p (operands[1], operands[3]))" | |
9168 | [(set (match_dup 4) (match_dup 1)) | |
9169 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) | |
9170 | (clobber (reg:CC CC_REGNUM))]) | |
9171 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9172 | (set (match_dup 3) (match_dup 4)) | |
9173 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9174 | (label_ref (match_dup 0)) | |
9175 | (pc)))] | |
9176 | "" | |
9177 | [(set_attr "op_type" "RSI") | |
9178 | (set_attr "type" "branch") | |
9179 | (set (attr "length") | |
9180 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9181 | (const_int 6) (const_int 14)))]) | |
9182 | ||
9183 | ||
9184 | ;; branch on count | |
9185 | ||
0a3bdf9d UW |
9186 | (define_expand "doloop_end" |
9187 | [(use (match_operand 0 "" "")) ; loop pseudo | |
1d0216c8 | 9188 | (use (match_operand 1 "" ""))] ; label |
0a3bdf9d | 9189 | "" |
0a3bdf9d | 9190 | { |
8cc6307c | 9191 | if (GET_MODE (operands[0]) == SImode) |
1d0216c8 | 9192 | emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0])); |
9602b6a1 | 9193 | else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) |
1d0216c8 | 9194 | emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0])); |
0a3bdf9d UW |
9195 | else |
9196 | FAIL; | |
9197 | ||
9198 | DONE; | |
10bbf137 | 9199 | }) |
0a3bdf9d | 9200 | |
6590e19a | 9201 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
9202 | [(set (pc) |
9203 | (if_then_else | |
7e665d18 | 9204 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9205 | (const_int 1)) |
9206 | (label_ref (match_operand 0 "" "")) | |
9207 | (pc))) | |
7e665d18 | 9208 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9209 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9210 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9211 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 9212 | "" |
0a3bdf9d UW |
9213 | { |
9214 | if (which_alternative != 0) | |
10bbf137 | 9215 | return "#"; |
0a3bdf9d | 9216 | else if (get_attr_length (insn) == 4) |
d40c829f | 9217 | return "brct\t%1,%l0"; |
6590e19a | 9218 | else |
545d16ff | 9219 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
9220 | } |
9221 | "&& reload_completed | |
9222 | && (! REG_P (operands[2]) | |
9223 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9224 | [(set (match_dup 3) (match_dup 1)) |
9225 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9226 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9227 | (const_int 0))) | |
9228 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9229 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9230 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9231 | (label_ref (match_dup 0)) |
9232 | (pc)))] | |
9233 | "" | |
9234 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9235 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9236 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9237 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9238 | (set_attr "type" "branch") |
9239 | (set (attr "length") | |
9240 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9241 | (const_int 4) (const_int 10)))]) | |
9242 | ||
6590e19a | 9243 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
9244 | [(set (pc) |
9245 | (if_then_else | |
7e665d18 | 9246 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9247 | (const_int 1)) |
9248 | (label_ref (match_operand 0 "" "")) | |
9249 | (pc))) | |
7e665d18 | 9250 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9251 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 9252 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 9253 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 9254 | "TARGET_ZARCH" |
0a3bdf9d UW |
9255 | { |
9256 | if (which_alternative != 0) | |
10bbf137 | 9257 | return "#"; |
0a3bdf9d | 9258 | else if (get_attr_length (insn) == 4) |
d40c829f | 9259 | return "brctg\t%1,%l0"; |
0a3bdf9d | 9260 | else |
545d16ff | 9261 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 9262 | } |
6590e19a | 9263 | "&& reload_completed |
0a3bdf9d UW |
9264 | && (! REG_P (operands[2]) |
9265 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9266 | [(set (match_dup 3) (match_dup 1)) |
9267 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
9268 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
9269 | (const_int 0))) | |
9270 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
9271 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9272 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 9273 | (label_ref (match_dup 0)) |
0a3bdf9d | 9274 | (pc)))] |
6590e19a UW |
9275 | "" |
9276 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9277 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9278 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9279 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9280 | (set_attr "type" "branch") |
9281 | (set (attr "length") | |
9282 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9283 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
9284 | |
9285 | ;; | |
9286 | ;;- Unconditional jump instructions. | |
9287 | ;; | |
9288 | ||
9289 | ; | |
9290 | ; jump instruction pattern(s). | |
9291 | ; | |
9292 | ||
6590e19a UW |
9293 | (define_expand "jump" |
9294 | [(match_operand 0 "" "")] | |
9db1d521 | 9295 | "" |
6590e19a UW |
9296 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
9297 | ||
9298 | (define_insn "*jump64" | |
9299 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
8cc6307c | 9300 | "" |
9db1d521 | 9301 | { |
13e58269 | 9302 | if (get_attr_length (insn) == 4) |
d40c829f | 9303 | return "j\t%l0"; |
6590e19a | 9304 | else |
d40c829f | 9305 | return "jg\t%l0"; |
6590e19a UW |
9306 | } |
9307 | [(set_attr "op_type" "RI") | |
9308 | (set_attr "type" "branch") | |
9309 | (set (attr "length") | |
9310 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9311 | (const_int 4) (const_int 6)))]) | |
9312 | ||
9db1d521 HP |
9313 | ; |
9314 | ; indirect-jump instruction pattern(s). | |
9315 | ; | |
9316 | ||
2841f550 AK |
9317 | (define_expand "indirect_jump" |
9318 | [(set (pc) (match_operand 0 "nonimmediate_operand" ""))] | |
9db1d521 | 9319 | "" |
f314b9b1 | 9320 | { |
2841f550 AK |
9321 | if (address_operand (operands[0], GET_MODE (operands[0]))) |
9322 | ; | |
9323 | else if (TARGET_ARCH12 | |
9324 | && GET_MODE (operands[0]) == Pmode | |
9325 | && memory_operand (operands[0], Pmode)) | |
9326 | ; | |
f314b9b1 | 9327 | else |
2841f550 | 9328 | operands[0] = force_reg (Pmode, operands[0]); |
84b4c7b5 AK |
9329 | |
9330 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK) | |
9331 | { | |
9332 | operands[0] = force_reg (Pmode, operands[0]); | |
9333 | if (TARGET_CPU_Z10) | |
9334 | { | |
9335 | if (TARGET_64BIT) | |
9336 | emit_jump_insn (gen_indirect_jump_via_thunkdi_z10 (operands[0])); | |
9337 | else | |
9338 | emit_jump_insn (gen_indirect_jump_via_thunksi_z10 (operands[0])); | |
9339 | } | |
9340 | else | |
9341 | { | |
9342 | if (TARGET_64BIT) | |
9343 | emit_jump_insn (gen_indirect_jump_via_thunkdi (operands[0])); | |
9344 | else | |
9345 | emit_jump_insn (gen_indirect_jump_via_thunksi (operands[0])); | |
9346 | } | |
9347 | DONE; | |
9348 | } | |
9349 | ||
9350 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK) | |
9351 | { | |
9352 | operands[0] = force_reg (Pmode, operands[0]); | |
9353 | rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
9354 | if (TARGET_CPU_Z10) | |
9355 | { | |
9356 | if (TARGET_64BIT) | |
9357 | emit_jump_insn (gen_indirect_jump_via_inlinethunkdi_z10 (operands[0], | |
9358 | label_ref)); | |
9359 | else | |
9360 | emit_jump_insn (gen_indirect_jump_via_inlinethunksi_z10 (operands[0], | |
9361 | label_ref)); | |
9362 | } | |
9363 | else | |
9364 | { | |
9365 | if (TARGET_64BIT) | |
9366 | emit_jump_insn (gen_indirect_jump_via_inlinethunkdi (operands[0], | |
9367 | label_ref, | |
9368 | force_reg (Pmode, label_ref))); | |
9369 | else | |
9370 | emit_jump_insn (gen_indirect_jump_via_inlinethunksi (operands[0], | |
9371 | label_ref, | |
9372 | force_reg (Pmode, label_ref))); | |
9373 | } | |
9374 | DONE; | |
9375 | } | |
2841f550 AK |
9376 | }) |
9377 | ||
9378 | (define_insn "*indirect_jump" | |
9379 | [(set (pc) | |
84b4c7b5 AK |
9380 | (match_operand 0 "address_operand" "ZR"))] |
9381 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK" | |
9382 | { | |
9383 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9384 | return "br\t%0"; | |
9385 | else | |
9386 | return "b\t%a0"; | |
9387 | } | |
9388 | [(set (attr "op_type") | |
9389 | (if_then_else (match_operand 0 "register_operand" "") | |
9390 | (const_string "RR") (const_string "RX"))) | |
9391 | (set (attr "mnemonic") | |
9392 | (if_then_else (match_operand 0 "register_operand" "") | |
9393 | (const_string "br") (const_string "b"))) | |
2841f550 | 9394 | (set_attr "type" "branch") |
84b4c7b5 AK |
9395 | (set_attr "atype" "agen")]) |
9396 | ||
9397 | (define_insn "indirect_jump_via_thunk<mode>_z10" | |
9398 | [(set (pc) | |
9399 | (match_operand:P 0 "register_operand" "a"))] | |
9400 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9401 | && TARGET_CPU_Z10" | |
9402 | { | |
9403 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9404 | INVALID_REGNUM, | |
9405 | NULL_RTX, | |
9406 | s390_indirect_branch_type_jump); | |
9407 | return ""; | |
9408 | } | |
9409 | [(set_attr "op_type" "RIL") | |
9410 | (set_attr "mnemonic" "jg") | |
9411 | (set_attr "type" "branch") | |
9412 | (set_attr "atype" "agen")]) | |
9413 | ||
9414 | (define_insn "indirect_jump_via_thunk<mode>" | |
9415 | [(set (pc) | |
9416 | (match_operand:P 0 "register_operand" " a")) | |
9417 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
9418 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9419 | && !TARGET_CPU_Z10" | |
9420 | { | |
9421 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9422 | INVALID_REGNUM, | |
9423 | NULL_RTX, | |
9424 | s390_indirect_branch_type_jump); | |
9425 | return ""; | |
9426 | } | |
9427 | [(set_attr "op_type" "RIL") | |
9428 | (set_attr "mnemonic" "jg") | |
9429 | (set_attr "type" "branch") | |
9430 | (set_attr "atype" "agen")]) | |
9431 | ||
9432 | ||
9433 | ; The label_ref is wrapped into an if_then_else in order to hide it | |
9434 | ; from mark_jump_label. Without this the label_ref would become the | |
9435 | ; ONLY jump target of that jump breaking the control flow graph. | |
9436 | (define_insn "indirect_jump_via_inlinethunk<mode>_z10" | |
9437 | [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X") | |
9438 | (const_int 0) | |
9439 | (const_int 0)) | |
9440 | (const_int 0)] UNSPEC_EXECUTE_JUMP) | |
9441 | (set (pc) (match_operand:P 0 "register_operand" "a"))] | |
9442 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9443 | && TARGET_CPU_Z10" | |
9444 | { | |
9445 | s390_indirect_branch_via_inline_thunk (operands[1]); | |
9446 | return ""; | |
9447 | } | |
9448 | [(set_attr "op_type" "RIL") | |
9449 | (set_attr "type" "branch") | |
9450 | (set_attr "length" "10")]) | |
9451 | ||
9452 | (define_insn "indirect_jump_via_inlinethunk<mode>" | |
9453 | [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X") | |
9454 | (const_int 0) | |
9455 | (const_int 0)) | |
9456 | (match_operand:P 2 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) | |
9457 | (set (pc) (match_operand:P 0 "register_operand" "a"))] | |
9458 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9459 | && !TARGET_CPU_Z10" | |
9460 | { | |
9461 | s390_indirect_branch_via_inline_thunk (operands[2]); | |
9462 | return ""; | |
9463 | } | |
9464 | [(set_attr "op_type" "RX") | |
9465 | (set_attr "type" "branch") | |
9466 | (set_attr "length" "8")]) | |
2841f550 AK |
9467 | |
9468 | ; FIXME: LRA does not appear to be able to deal with MEMs being | |
9469 | ; checked against address constraints like ZR above. So make this a | |
9470 | ; separate pattern for now. | |
9471 | (define_insn "*indirect2_jump" | |
9472 | [(set (pc) | |
9473 | (match_operand 0 "nonimmediate_operand" "a,T"))] | |
84b4c7b5 | 9474 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
2841f550 AK |
9475 | "@ |
9476 | br\t%0 | |
9477 | bi\t%0" | |
9478 | [(set_attr "op_type" "RR,RXY") | |
9479 | (set_attr "type" "branch") | |
9480 | (set_attr "atype" "agen") | |
9481 | (set_attr "cpu_facility" "*,arch12")]) | |
9db1d521 HP |
9482 | |
9483 | ; | |
f314b9b1 | 9484 | ; casesi instruction pattern(s). |
9db1d521 HP |
9485 | ; |
9486 | ||
84b4c7b5 AK |
9487 | (define_expand "casesi_jump" |
9488 | [(parallel | |
9489 | [(set (pc) (match_operand 0 "address_operand")) | |
9490 | (use (label_ref (match_operand 1 "")))])] | |
9db1d521 | 9491 | "" |
84b4c7b5 AK |
9492 | { |
9493 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK) | |
9494 | { | |
9495 | operands[0] = force_reg (GET_MODE (operands[0]), operands[0]); | |
9496 | ||
9497 | if (TARGET_CPU_Z10) | |
9498 | { | |
9499 | if (TARGET_64BIT) | |
9500 | emit_jump_insn (gen_casesi_jump_via_thunkdi_z10 (operands[0], | |
9501 | operands[1])); | |
9502 | else | |
9503 | emit_jump_insn (gen_casesi_jump_via_thunksi_z10 (operands[0], | |
9504 | operands[1])); | |
9505 | } | |
9506 | else | |
9507 | { | |
9508 | if (TARGET_64BIT) | |
9509 | emit_jump_insn (gen_casesi_jump_via_thunkdi (operands[0], | |
9510 | operands[1])); | |
9511 | else | |
9512 | emit_jump_insn (gen_casesi_jump_via_thunksi (operands[0], | |
9513 | operands[1])); | |
9514 | } | |
9515 | DONE; | |
9516 | } | |
9517 | ||
9518 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK) | |
9519 | { | |
9520 | operands[0] = force_reg (Pmode, operands[0]); | |
9521 | rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
9522 | if (TARGET_CPU_Z10) | |
9523 | { | |
9524 | if (TARGET_64BIT) | |
9525 | emit_jump_insn (gen_casesi_jump_via_inlinethunkdi_z10 (operands[0], | |
9526 | operands[1], | |
9527 | label_ref)); | |
9528 | else | |
9529 | emit_jump_insn (gen_casesi_jump_via_inlinethunksi_z10 (operands[0], | |
9530 | operands[1], | |
9531 | label_ref)); | |
9532 | } | |
9533 | else | |
9534 | { | |
9535 | if (TARGET_64BIT) | |
9536 | emit_jump_insn (gen_casesi_jump_via_inlinethunkdi (operands[0], | |
9537 | operands[1], | |
9538 | label_ref, | |
9539 | force_reg (Pmode, label_ref))); | |
9540 | else | |
9541 | emit_jump_insn (gen_casesi_jump_via_inlinethunksi (operands[0], | |
9542 | operands[1], | |
9543 | label_ref, | |
9544 | force_reg (Pmode, label_ref))); | |
9545 | } | |
9546 | DONE; | |
9547 | } | |
9548 | }) | |
9549 | ||
9550 | (define_insn "*casesi_jump" | |
9551 | [(set (pc) (match_operand 0 "address_operand" "ZR")) | |
9552 | (use (label_ref (match_operand 1 "" "")))] | |
9553 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK" | |
9db1d521 | 9554 | { |
f314b9b1 | 9555 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 9556 | return "br\t%0"; |
f314b9b1 | 9557 | else |
d40c829f | 9558 | return "b\t%a0"; |
10bbf137 | 9559 | } |
c7453384 | 9560 | [(set (attr "op_type") |
f314b9b1 UW |
9561 | (if_then_else (match_operand 0 "register_operand" "") |
9562 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
9563 | (set (attr "mnemonic") |
9564 | (if_then_else (match_operand 0 "register_operand" "") | |
9565 | (const_string "br") (const_string "b"))) | |
9566 | (set_attr "type" "branch") | |
9567 | (set_attr "atype" "agen")]) | |
9568 | ||
9569 | (define_insn "casesi_jump_via_thunk<mode>_z10" | |
9570 | [(set (pc) (match_operand:P 0 "register_operand" "a")) | |
9571 | (use (label_ref (match_operand 1 "" "")))] | |
9572 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9573 | && TARGET_CPU_Z10" | |
9574 | { | |
9575 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9576 | INVALID_REGNUM, | |
9577 | NULL_RTX, | |
9578 | s390_indirect_branch_type_jump); | |
9579 | return ""; | |
9580 | } | |
9581 | [(set_attr "op_type" "RIL") | |
9582 | (set_attr "mnemonic" "jg") | |
9583 | (set_attr "type" "branch") | |
9584 | (set_attr "atype" "agen")]) | |
9585 | ||
9586 | (define_insn "casesi_jump_via_thunk<mode>" | |
9587 | [(set (pc) (match_operand:P 0 "register_operand" "a")) | |
9588 | (use (label_ref (match_operand 1 "" ""))) | |
9589 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
9590 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9591 | && !TARGET_CPU_Z10" | |
9592 | { | |
9593 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9594 | INVALID_REGNUM, | |
9595 | NULL_RTX, | |
9596 | s390_indirect_branch_type_jump); | |
9597 | return ""; | |
9598 | } | |
9599 | [(set_attr "op_type" "RIL") | |
9600 | (set_attr "mnemonic" "jg") | |
077dab3b HP |
9601 | (set_attr "type" "branch") |
9602 | (set_attr "atype" "agen")]) | |
9db1d521 | 9603 | |
84b4c7b5 AK |
9604 | |
9605 | ; The label_ref is wrapped into an if_then_else in order to hide it | |
9606 | ; from mark_jump_label. Without this the label_ref would become the | |
9607 | ; ONLY jump target of that jump breaking the control flow graph. | |
9608 | (define_insn "casesi_jump_via_inlinethunk<mode>_z10" | |
9609 | [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X") | |
9610 | (const_int 0) | |
9611 | (const_int 0)) | |
9612 | (const_int 0)] UNSPEC_EXECUTE_JUMP) | |
9613 | (set (pc) (match_operand:P 0 "register_operand" "a")) | |
9614 | (use (label_ref (match_operand 1 "" "")))] | |
9615 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9616 | && TARGET_CPU_Z10" | |
9617 | { | |
9618 | s390_indirect_branch_via_inline_thunk (operands[2]); | |
9619 | return ""; | |
9620 | } | |
9621 | [(set_attr "op_type" "RIL") | |
9622 | (set_attr "type" "cs") | |
9623 | (set_attr "length" "10")]) | |
9624 | ||
9625 | (define_insn "casesi_jump_via_inlinethunk<mode>" | |
9626 | [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X") | |
9627 | (const_int 0) | |
9628 | (const_int 0)) | |
9629 | (match_operand:P 3 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) | |
9630 | (set (pc) (match_operand:P 0 "register_operand" "a")) | |
9631 | (use (label_ref (match_operand 1 "" "")))] | |
9632 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9633 | && !TARGET_CPU_Z10" | |
9634 | { | |
9635 | s390_indirect_branch_via_inline_thunk (operands[3]); | |
9636 | return ""; | |
9637 | } | |
9638 | [(set_attr "op_type" "RX") | |
9639 | (set_attr "type" "cs") | |
9640 | (set_attr "length" "8")]) | |
9641 | ||
f314b9b1 UW |
9642 | (define_expand "casesi" |
9643 | [(match_operand:SI 0 "general_operand" "") | |
9644 | (match_operand:SI 1 "general_operand" "") | |
9645 | (match_operand:SI 2 "general_operand" "") | |
9646 | (label_ref (match_operand 3 "" "")) | |
9647 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 9648 | "" |
f314b9b1 UW |
9649 | { |
9650 | rtx index = gen_reg_rtx (SImode); | |
9651 | rtx base = gen_reg_rtx (Pmode); | |
9652 | rtx target = gen_reg_rtx (Pmode); | |
9653 | ||
9654 | emit_move_insn (index, operands[0]); | |
9655 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
9656 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 9657 | operands[4]); |
f314b9b1 UW |
9658 | |
9659 | if (Pmode != SImode) | |
9660 | index = convert_to_mode (Pmode, index, 1); | |
9661 | if (GET_CODE (index) != REG) | |
9662 | index = copy_to_mode_reg (Pmode, index); | |
9663 | ||
9664 | if (TARGET_64BIT) | |
9665 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
9666 | else | |
a556fd39 | 9667 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 9668 | |
f314b9b1 UW |
9669 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
9670 | ||
542a8afa | 9671 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
9672 | emit_move_insn (target, index); |
9673 | ||
9674 | if (flag_pic) | |
9675 | target = gen_rtx_PLUS (Pmode, base, target); | |
9676 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
9677 | ||
9678 | DONE; | |
10bbf137 | 9679 | }) |
9db1d521 HP |
9680 | |
9681 | ||
9682 | ;; | |
9683 | ;;- Jump to subroutine. | |
9684 | ;; | |
9685 | ;; | |
9686 | ||
9687 | ; | |
9688 | ; untyped call instruction pattern(s). | |
9689 | ; | |
9690 | ||
9691 | ;; Call subroutine returning any type. | |
9692 | (define_expand "untyped_call" | |
9693 | [(parallel [(call (match_operand 0 "" "") | |
9694 | (const_int 0)) | |
9695 | (match_operand 1 "" "") | |
9696 | (match_operand 2 "" "")])] | |
9697 | "" | |
9db1d521 HP |
9698 | { |
9699 | int i; | |
9700 | ||
9701 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
9702 | ||
9703 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
9704 | { | |
9705 | rtx set = XVECEXP (operands[2], 0, i); | |
9706 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
9707 | } | |
9708 | ||
9709 | /* The optimizer does not know that the call sets the function value | |
9710 | registers we stored in the result block. We avoid problems by | |
9711 | claiming that all hard registers are used and clobbered at this | |
9712 | point. */ | |
9713 | emit_insn (gen_blockage ()); | |
9714 | ||
9715 | DONE; | |
10bbf137 | 9716 | }) |
9db1d521 HP |
9717 | |
9718 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
9719 | ;; all of memory. This blocks insns from being moved across this point. | |
9720 | ||
9721 | (define_insn "blockage" | |
10bbf137 | 9722 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 9723 | "" |
4023fb28 | 9724 | "" |
d5869ca0 UW |
9725 | [(set_attr "type" "none") |
9726 | (set_attr "length" "0")]) | |
4023fb28 | 9727 | |
9db1d521 | 9728 | ; |
ed9676cf | 9729 | ; sibcall patterns |
9db1d521 HP |
9730 | ; |
9731 | ||
ed9676cf | 9732 | (define_expand "sibcall" |
44b8152b | 9733 | [(call (match_operand 0 "" "") |
ed9676cf | 9734 | (match_operand 1 "" ""))] |
9db1d521 | 9735 | "" |
9db1d521 | 9736 | { |
ed9676cf AK |
9737 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
9738 | DONE; | |
9739 | }) | |
9db1d521 | 9740 | |
ed9676cf | 9741 | (define_insn "*sibcall_br" |
ae156f85 | 9742 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9743 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 9744 | "SIBLING_CALL_P (insn) |
ed9676cf | 9745 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
84b4c7b5 AK |
9746 | { |
9747 | if (TARGET_INDIRECT_BRANCH_NOBP_CALL) | |
9748 | { | |
9749 | gcc_assert (TARGET_CPU_Z10); | |
9750 | s390_indirect_branch_via_thunk (SIBCALL_REGNUM, | |
9751 | INVALID_REGNUM, | |
9752 | NULL_RTX, | |
9753 | s390_indirect_branch_type_call); | |
9754 | return ""; | |
9755 | } | |
9756 | else | |
9757 | return "br\t%%r1"; | |
9758 | } | |
9759 | [(set (attr "op_type") | |
9760 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
9761 | (const_string "RIL") | |
9762 | (const_string "RR"))) | |
9763 | (set (attr "mnemonic") | |
9764 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
9765 | (const_string "jg") | |
9766 | (const_string "br"))) | |
ed9676cf AK |
9767 | (set_attr "type" "branch") |
9768 | (set_attr "atype" "agen")]) | |
9db1d521 | 9769 | |
ed9676cf AK |
9770 | (define_insn "*sibcall_brc" |
9771 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9772 | (match_operand 1 "const_int_operand" "n"))] | |
9773 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9774 | "j\t%0" | |
9775 | [(set_attr "op_type" "RI") | |
9776 | (set_attr "type" "branch")]) | |
9db1d521 | 9777 | |
ed9676cf AK |
9778 | (define_insn "*sibcall_brcl" |
9779 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9780 | (match_operand 1 "const_int_operand" "n"))] | |
8cc6307c | 9781 | "SIBLING_CALL_P (insn)" |
ed9676cf AK |
9782 | "jg\t%0" |
9783 | [(set_attr "op_type" "RIL") | |
9784 | (set_attr "type" "branch")]) | |
44b8152b | 9785 | |
ed9676cf AK |
9786 | ; |
9787 | ; sibcall_value patterns | |
9788 | ; | |
9e8327e3 | 9789 | |
ed9676cf AK |
9790 | (define_expand "sibcall_value" |
9791 | [(set (match_operand 0 "" "") | |
9792 | (call (match_operand 1 "" "") | |
9793 | (match_operand 2 "" "")))] | |
9794 | "" | |
9795 | { | |
9796 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 9797 | DONE; |
10bbf137 | 9798 | }) |
9db1d521 | 9799 | |
ed9676cf AK |
9800 | (define_insn "*sibcall_value_br" |
9801 | [(set (match_operand 0 "" "") | |
ae156f85 | 9802 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9803 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 9804 | "SIBLING_CALL_P (insn) |
ed9676cf | 9805 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
84b4c7b5 AK |
9806 | { |
9807 | if (TARGET_INDIRECT_BRANCH_NOBP_CALL) | |
9808 | { | |
9809 | gcc_assert (TARGET_CPU_Z10); | |
9810 | s390_indirect_branch_via_thunk (SIBCALL_REGNUM, | |
9811 | INVALID_REGNUM, | |
9812 | NULL_RTX, | |
9813 | s390_indirect_branch_type_call); | |
9814 | return ""; | |
9815 | } | |
9816 | else | |
9817 | return "br\t%%r1"; | |
9818 | } | |
9819 | [(set (attr "op_type") | |
9820 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
9821 | (const_string "RIL") | |
9822 | (const_string "RR"))) | |
9823 | (set (attr "mnemonic") | |
9824 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
9825 | (const_string "jg") | |
9826 | (const_string "br"))) | |
ed9676cf AK |
9827 | (set_attr "type" "branch") |
9828 | (set_attr "atype" "agen")]) | |
9829 | ||
9830 | (define_insn "*sibcall_value_brc" | |
9831 | [(set (match_operand 0 "" "") | |
9832 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9833 | (match_operand 2 "const_int_operand" "n")))] | |
9834 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9835 | "j\t%1" | |
9836 | [(set_attr "op_type" "RI") | |
9837 | (set_attr "type" "branch")]) | |
9838 | ||
9839 | (define_insn "*sibcall_value_brcl" | |
9840 | [(set (match_operand 0 "" "") | |
9841 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9842 | (match_operand 2 "const_int_operand" "n")))] | |
8cc6307c | 9843 | "SIBLING_CALL_P (insn)" |
ed9676cf AK |
9844 | "jg\t%1" |
9845 | [(set_attr "op_type" "RIL") | |
9846 | (set_attr "type" "branch")]) | |
9847 | ||
9848 | ||
9849 | ; | |
9850 | ; call instruction pattern(s). | |
9851 | ; | |
9852 | ||
9853 | (define_expand "call" | |
9854 | [(call (match_operand 0 "" "") | |
9855 | (match_operand 1 "" "")) | |
9856 | (use (match_operand 2 "" ""))] | |
44b8152b | 9857 | "" |
ed9676cf | 9858 | { |
2f7e5a0d | 9859 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
9860 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
9861 | DONE; | |
9862 | }) | |
44b8152b | 9863 | |
9e8327e3 UW |
9864 | (define_insn "*bras" |
9865 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9866 | (match_operand 1 "const_int_operand" "n")) | |
9867 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
9868 | "!SIBLING_CALL_P (insn) |
9869 | && TARGET_SMALL_EXEC | |
ed9676cf | 9870 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 9871 | "bras\t%2,%0" |
9db1d521 | 9872 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9873 | (set_attr "type" "jsr") |
9874 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9875 | |
9e8327e3 UW |
9876 | (define_insn "*brasl" |
9877 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9878 | (match_operand 1 "const_int_operand" "n")) | |
9879 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d | 9880 | "!SIBLING_CALL_P (insn) |
8cc6307c | 9881 | |
ed9676cf | 9882 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
9883 | "brasl\t%2,%0" |
9884 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9885 | (set_attr "type" "jsr") |
9886 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9887 | |
9e8327e3 | 9888 | (define_insn "*basr" |
3e4be43f | 9889 | [(call (mem:QI (match_operand 0 "address_operand" "ZR")) |
9e8327e3 UW |
9890 | (match_operand 1 "const_int_operand" "n")) |
9891 | (clobber (match_operand 2 "register_operand" "=r"))] | |
84b4c7b5 AK |
9892 | "!TARGET_INDIRECT_BRANCH_NOBP_CALL |
9893 | && !SIBLING_CALL_P (insn) | |
9894 | && GET_MODE (operands[2]) == Pmode" | |
9e8327e3 UW |
9895 | { |
9896 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9897 | return "basr\t%2,%0"; | |
9898 | else | |
9899 | return "bas\t%2,%a0"; | |
9900 | } | |
9901 | [(set (attr "op_type") | |
9902 | (if_then_else (match_operand 0 "register_operand" "") | |
9903 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
9904 | (set (attr "mnemonic") |
9905 | (if_then_else (match_operand 0 "register_operand" "") | |
9906 | (const_string "basr") (const_string "bas"))) | |
9907 | (set_attr "type" "jsr") | |
9908 | (set_attr "atype" "agen") | |
9909 | (set_attr "z196prop" "z196_cracked")]) | |
9910 | ||
9911 | (define_insn "*basr_via_thunk<mode>_z10" | |
9912 | [(call (mem:QI (match_operand:P 0 "register_operand" "a")) | |
9913 | (match_operand 1 "const_int_operand" "n")) | |
9914 | (clobber (match_operand:P 2 "register_operand" "=&r"))] | |
9915 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
9916 | && TARGET_CPU_Z10 | |
9917 | && !SIBLING_CALL_P (insn)" | |
9918 | { | |
9919 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9920 | REGNO (operands[2]), | |
9921 | NULL_RTX, | |
9922 | s390_indirect_branch_type_call); | |
9923 | return ""; | |
9924 | } | |
9925 | [(set_attr "op_type" "RIL") | |
9926 | (set_attr "mnemonic" "brasl") | |
9927 | (set_attr "type" "jsr") | |
9928 | (set_attr "atype" "agen") | |
9929 | (set_attr "z196prop" "z196_cracked")]) | |
9930 | ||
9931 | (define_insn "*basr_via_thunk<mode>" | |
9932 | [(call (mem:QI (match_operand:P 0 "register_operand" "a")) | |
9933 | (match_operand 1 "const_int_operand" "n")) | |
9934 | (clobber (match_operand:P 2 "register_operand" "=&r")) | |
9935 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
9936 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
9937 | && !TARGET_CPU_Z10 | |
9938 | && !SIBLING_CALL_P (insn)" | |
9939 | { | |
9940 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9941 | REGNO (operands[2]), | |
9942 | NULL_RTX, | |
9943 | s390_indirect_branch_type_call); | |
9944 | return ""; | |
9945 | } | |
9946 | [(set_attr "op_type" "RIL") | |
9947 | (set_attr "mnemonic" "brasl") | |
9e8327e3 | 9948 | (set_attr "type" "jsr") |
65b1d8ea AK |
9949 | (set_attr "atype" "agen") |
9950 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 HP |
9951 | |
9952 | ; | |
9953 | ; call_value instruction pattern(s). | |
9954 | ; | |
9955 | ||
9956 | (define_expand "call_value" | |
44b8152b UW |
9957 | [(set (match_operand 0 "" "") |
9958 | (call (match_operand 1 "" "") | |
9959 | (match_operand 2 "" ""))) | |
9960 | (use (match_operand 3 "" ""))] | |
9db1d521 | 9961 | "" |
9db1d521 | 9962 | { |
2f7e5a0d | 9963 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 9964 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 9965 | DONE; |
10bbf137 | 9966 | }) |
9db1d521 | 9967 | |
9e8327e3 | 9968 | (define_insn "*bras_r" |
c19ec8f9 | 9969 | [(set (match_operand 0 "" "") |
9e8327e3 | 9970 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 9971 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 9972 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
9973 | "!SIBLING_CALL_P (insn) |
9974 | && TARGET_SMALL_EXEC | |
ed9676cf | 9975 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 9976 | "bras\t%3,%1" |
9db1d521 | 9977 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9978 | (set_attr "type" "jsr") |
9979 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9980 | |
9e8327e3 | 9981 | (define_insn "*brasl_r" |
c19ec8f9 | 9982 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9983 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9984 | (match_operand 2 "const_int_operand" "n"))) | |
9985 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d | 9986 | "!SIBLING_CALL_P (insn) |
8cc6307c | 9987 | |
ed9676cf | 9988 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9989 | "brasl\t%3,%1" |
9990 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9991 | (set_attr "type" "jsr") |
9992 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9993 | |
9e8327e3 | 9994 | (define_insn "*basr_r" |
c19ec8f9 | 9995 | [(set (match_operand 0 "" "") |
3e4be43f | 9996 | (call (mem:QI (match_operand 1 "address_operand" "ZR")) |
9e8327e3 UW |
9997 | (match_operand 2 "const_int_operand" "n"))) |
9998 | (clobber (match_operand 3 "register_operand" "=r"))] | |
84b4c7b5 AK |
9999 | "!TARGET_INDIRECT_BRANCH_NOBP_CALL |
10000 | && !SIBLING_CALL_P (insn) | |
10001 | && GET_MODE (operands[3]) == Pmode" | |
9e8327e3 UW |
10002 | { |
10003 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10004 | return "basr\t%3,%1"; | |
10005 | else | |
10006 | return "bas\t%3,%a1"; | |
10007 | } | |
10008 | [(set (attr "op_type") | |
10009 | (if_then_else (match_operand 1 "register_operand" "") | |
10010 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
10011 | (set (attr "mnemonic") |
10012 | (if_then_else (match_operand 1 "register_operand" "") | |
10013 | (const_string "basr") (const_string "bas"))) | |
10014 | (set_attr "type" "jsr") | |
10015 | (set_attr "atype" "agen") | |
10016 | (set_attr "z196prop" "z196_cracked")]) | |
10017 | ||
10018 | (define_insn "*basr_r_via_thunk_z10" | |
10019 | [(set (match_operand 0 "" "") | |
10020 | (call (mem:QI (match_operand 1 "register_operand" "a")) | |
10021 | (match_operand 2 "const_int_operand" "n"))) | |
10022 | (clobber (match_operand 3 "register_operand" "=&r"))] | |
10023 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10024 | && TARGET_CPU_Z10 | |
10025 | && !SIBLING_CALL_P (insn) | |
10026 | && GET_MODE (operands[3]) == Pmode" | |
10027 | { | |
10028 | s390_indirect_branch_via_thunk (REGNO (operands[1]), | |
10029 | REGNO (operands[3]), | |
10030 | NULL_RTX, | |
10031 | s390_indirect_branch_type_call); | |
10032 | return ""; | |
10033 | } | |
10034 | [(set_attr "op_type" "RIL") | |
10035 | (set_attr "mnemonic" "brasl") | |
10036 | (set_attr "type" "jsr") | |
10037 | (set_attr "atype" "agen") | |
10038 | (set_attr "z196prop" "z196_cracked")]) | |
10039 | ||
10040 | (define_insn "*basr_r_via_thunk" | |
10041 | [(set (match_operand 0 "" "") | |
10042 | (call (mem:QI (match_operand 1 "register_operand" "a")) | |
10043 | (match_operand 2 "const_int_operand" "n"))) | |
10044 | (clobber (match_operand 3 "register_operand" "=&r")) | |
10045 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
10046 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10047 | && !TARGET_CPU_Z10 | |
10048 | && !SIBLING_CALL_P (insn) | |
10049 | && GET_MODE (operands[3]) == Pmode" | |
10050 | { | |
10051 | s390_indirect_branch_via_thunk (REGNO (operands[1]), | |
10052 | REGNO (operands[3]), | |
10053 | NULL_RTX, | |
10054 | s390_indirect_branch_type_call); | |
10055 | return ""; | |
10056 | } | |
10057 | [(set_attr "op_type" "RIL") | |
10058 | (set_attr "mnemonic" "brasl") | |
9e8327e3 | 10059 | (set_attr "type" "jsr") |
65b1d8ea AK |
10060 | (set_attr "atype" "agen") |
10061 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10062 | |
fd3cd001 UW |
10063 | ;; |
10064 | ;;- Thread-local storage support. | |
10065 | ;; | |
10066 | ||
f959607b CLT |
10067 | (define_expand "get_thread_pointer<mode>" |
10068 | [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))] | |
10069 | "" | |
c5aa1d12 | 10070 | "") |
fd3cd001 | 10071 | |
f959607b CLT |
10072 | (define_expand "set_thread_pointer<mode>" |
10073 | [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) | |
10074 | (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] | |
10075 | "" | |
c5aa1d12 UW |
10076 | "") |
10077 | ||
10078 | (define_insn "*set_tp" | |
ae156f85 | 10079 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
10080 | "" |
10081 | "" | |
10082 | [(set_attr "type" "none") | |
10083 | (set_attr "length" "0")]) | |
c7453384 | 10084 | |
fd3cd001 UW |
10085 | (define_insn "*tls_load_64" |
10086 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 10087 | (unspec:DI [(match_operand:DI 1 "memory_operand" "T") |
fd3cd001 UW |
10088 | (match_operand:DI 2 "" "")] |
10089 | UNSPEC_TLS_LOAD))] | |
10090 | "TARGET_64BIT" | |
d40c829f | 10091 | "lg\t%0,%1%J2" |
9381e3f1 WG |
10092 | [(set_attr "op_type" "RXE") |
10093 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
10094 | |
10095 | (define_insn "*tls_load_31" | |
d3632d41 UW |
10096 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
10097 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
10098 | (match_operand:SI 2 "" "")] |
10099 | UNSPEC_TLS_LOAD))] | |
10100 | "!TARGET_64BIT" | |
d3632d41 | 10101 | "@ |
d40c829f UW |
10102 | l\t%0,%1%J2 |
10103 | ly\t%0,%1%J2" | |
9381e3f1 | 10104 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 10105 | (set_attr "type" "load") |
3e4be43f | 10106 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 10107 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 10108 | |
9e8327e3 | 10109 | (define_insn "*bras_tls" |
c19ec8f9 | 10110 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10111 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10112 | (match_operand 2 "const_int_operand" "n"))) | |
10113 | (clobber (match_operand 3 "register_operand" "=r")) | |
10114 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
10115 | "!SIBLING_CALL_P (insn) |
10116 | && TARGET_SMALL_EXEC | |
ed9676cf | 10117 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 10118 | "bras\t%3,%1%J4" |
fd3cd001 | 10119 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
10120 | (set_attr "type" "jsr") |
10121 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 10122 | |
9e8327e3 | 10123 | (define_insn "*brasl_tls" |
c19ec8f9 | 10124 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10125 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10126 | (match_operand 2 "const_int_operand" "n"))) | |
10127 | (clobber (match_operand 3 "register_operand" "=r")) | |
10128 | (use (match_operand 4 "" ""))] | |
2f7e5a0d | 10129 | "!SIBLING_CALL_P (insn) |
8cc6307c | 10130 | |
ed9676cf | 10131 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10132 | "brasl\t%3,%1%J4" |
10133 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
10134 | (set_attr "type" "jsr") |
10135 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 10136 | |
9e8327e3 | 10137 | (define_insn "*basr_tls" |
c19ec8f9 | 10138 | [(set (match_operand 0 "" "") |
3e4be43f | 10139 | (call (mem:QI (match_operand 1 "address_operand" "ZR")) |
9e8327e3 UW |
10140 | (match_operand 2 "const_int_operand" "n"))) |
10141 | (clobber (match_operand 3 "register_operand" "=r")) | |
10142 | (use (match_operand 4 "" ""))] | |
ed9676cf | 10143 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10144 | { |
10145 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10146 | return "basr\t%3,%1%J4"; | |
10147 | else | |
10148 | return "bas\t%3,%a1%J4"; | |
10149 | } | |
10150 | [(set (attr "op_type") | |
10151 | (if_then_else (match_operand 1 "register_operand" "") | |
10152 | (const_string "RR") (const_string "RX"))) | |
10153 | (set_attr "type" "jsr") | |
65b1d8ea AK |
10154 | (set_attr "atype" "agen") |
10155 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 10156 | |
e0374221 AS |
10157 | ;; |
10158 | ;;- Atomic operations | |
10159 | ;; | |
10160 | ||
10161 | ; | |
78ce265b | 10162 | ; memory barrier patterns. |
e0374221 AS |
10163 | ; |
10164 | ||
78ce265b RH |
10165 | (define_expand "mem_thread_fence" |
10166 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
10167 | "" | |
10168 | { | |
10169 | /* Unless this is a SEQ_CST fence, the s390 memory model is strong | |
10170 | enough not to require barriers of any kind. */ | |
46b35980 | 10171 | if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0])))) |
78ce265b RH |
10172 | { |
10173 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
10174 | MEM_VOLATILE_P (mem) = 1; | |
10175 | emit_insn (gen_mem_thread_fence_1 (mem)); | |
10176 | } | |
10177 | DONE; | |
e0374221 AS |
10178 | }) |
10179 | ||
78ce265b RH |
10180 | ; Although bcr is superscalar on Z10, this variant will never |
10181 | ; become part of an execution group. | |
a9cc3f58 AK |
10182 | ; With z196 we can make use of the fast-BCR-serialization facility. |
10183 | ; This allows for a slightly faster sync which is sufficient for our | |
10184 | ; purposes. | |
78ce265b | 10185 | (define_insn "mem_thread_fence_1" |
e0374221 | 10186 | [(set (match_operand:BLK 0 "" "") |
1a8c13b3 | 10187 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 | 10188 | "" |
a9cc3f58 AK |
10189 | { |
10190 | if (TARGET_Z196) | |
10191 | return "bcr\t14,0"; | |
10192 | else | |
10193 | return "bcr\t15,0"; | |
10194 | } | |
10195 | [(set_attr "op_type" "RR") | |
10196 | (set_attr "mnemonic" "bcr_flush") | |
10197 | (set_attr "z196prop" "z196_alone")]) | |
1a8c13b3 | 10198 | |
78ce265b RH |
10199 | ; |
10200 | ; atomic load/store operations | |
10201 | ; | |
10202 | ||
10203 | ; Atomic loads need not examine the memory model at all. | |
10204 | (define_expand "atomic_load<mode>" | |
10205 | [(match_operand:DINT 0 "register_operand") ;; output | |
10206 | (match_operand:DINT 1 "memory_operand") ;; memory | |
10207 | (match_operand:SI 2 "const_int_operand")] ;; model | |
10208 | "" | |
10209 | { | |
75cc21e2 AK |
10210 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
10211 | FAIL; | |
10212 | ||
78ce265b RH |
10213 | if (<MODE>mode == TImode) |
10214 | emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); | |
10215 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
10216 | emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); | |
10217 | else | |
10218 | emit_move_insn (operands[0], operands[1]); | |
10219 | DONE; | |
10220 | }) | |
10221 | ||
10222 | ; Different from movdi_31 in that we want no splitters. | |
10223 | (define_insn "atomic_loaddi_1" | |
10224 | [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") | |
10225 | (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] | |
10226 | UNSPEC_MOVA))] | |
10227 | "!TARGET_ZARCH" | |
10228 | "@ | |
10229 | lm\t%0,%M0,%S1 | |
10230 | lmy\t%0,%M0,%S1 | |
10231 | ld\t%0,%1 | |
10232 | ldy\t%0,%1" | |
10233 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
3e4be43f | 10234 | (set_attr "cpu_facility" "*,longdisp,*,longdisp") |
78ce265b RH |
10235 | (set_attr "type" "lm,lm,floaddf,floaddf")]) |
10236 | ||
10237 | (define_insn "atomic_loadti_1" | |
10238 | [(set (match_operand:TI 0 "register_operand" "=r") | |
3e4be43f | 10239 | (unspec:TI [(match_operand:TI 1 "memory_operand" "T")] |
78ce265b RH |
10240 | UNSPEC_MOVA))] |
10241 | "TARGET_ZARCH" | |
10242 | "lpq\t%0,%1" | |
10243 | [(set_attr "op_type" "RXY") | |
10244 | (set_attr "type" "other")]) | |
10245 | ||
10246 | ; Atomic stores must(?) enforce sequential consistency. | |
10247 | (define_expand "atomic_store<mode>" | |
10248 | [(match_operand:DINT 0 "memory_operand") ;; memory | |
10249 | (match_operand:DINT 1 "register_operand") ;; input | |
10250 | (match_operand:SI 2 "const_int_operand")] ;; model | |
10251 | "" | |
10252 | { | |
46b35980 | 10253 | enum memmodel model = memmodel_from_int (INTVAL (operands[2])); |
78ce265b | 10254 | |
75cc21e2 AK |
10255 | if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0]))) |
10256 | FAIL; | |
10257 | ||
78ce265b RH |
10258 | if (<MODE>mode == TImode) |
10259 | emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); | |
10260 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
10261 | emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); | |
10262 | else | |
10263 | emit_move_insn (operands[0], operands[1]); | |
46b35980 | 10264 | if (is_mm_seq_cst (model)) |
78ce265b RH |
10265 | emit_insn (gen_mem_thread_fence (operands[2])); |
10266 | DONE; | |
10267 | }) | |
10268 | ||
10269 | ; Different from movdi_31 in that we want no splitters. | |
10270 | (define_insn "atomic_storedi_1" | |
10271 | [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") | |
10272 | (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] | |
10273 | UNSPEC_MOVA))] | |
10274 | "!TARGET_ZARCH" | |
10275 | "@ | |
10276 | stm\t%1,%N1,%S0 | |
10277 | stmy\t%1,%N1,%S0 | |
10278 | std %1,%0 | |
10279 | stdy %1,%0" | |
10280 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
3e4be43f | 10281 | (set_attr "cpu_facility" "*,longdisp,*,longdisp") |
78ce265b RH |
10282 | (set_attr "type" "stm,stm,fstoredf,fstoredf")]) |
10283 | ||
10284 | (define_insn "atomic_storeti_1" | |
3e4be43f | 10285 | [(set (match_operand:TI 0 "memory_operand" "=T") |
78ce265b RH |
10286 | (unspec:TI [(match_operand:TI 1 "register_operand" "r")] |
10287 | UNSPEC_MOVA))] | |
10288 | "TARGET_ZARCH" | |
10289 | "stpq\t%1,%0" | |
10290 | [(set_attr "op_type" "RXY") | |
10291 | (set_attr "type" "other")]) | |
e0374221 AS |
10292 | |
10293 | ; | |
10294 | ; compare and swap patterns. | |
10295 | ; | |
10296 | ||
78ce265b RH |
10297 | (define_expand "atomic_compare_and_swap<mode>" |
10298 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
03db9ab5 DV |
10299 | (match_operand:DINT 1 "nonimmediate_operand");; oldval output |
10300 | (match_operand:DINT 2 "s_operand") ;; memory | |
10301 | (match_operand:DINT 3 "general_operand") ;; expected intput | |
10302 | (match_operand:DINT 4 "general_operand") ;; newval intput | |
78ce265b RH |
10303 | (match_operand:SI 5 "const_int_operand") ;; is_weak |
10304 | (match_operand:SI 6 "const_int_operand") ;; success model | |
10305 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
10306 | "" | |
10307 | { | |
03db9ab5 DV |
10308 | if (GET_MODE_BITSIZE (<MODE>mode) >= 16 |
10309 | && GET_MODE_BITSIZE (<MODE>mode) > MEM_ALIGN (operands[2])) | |
75cc21e2 AK |
10310 | FAIL; |
10311 | ||
03db9ab5 DV |
10312 | s390_expand_cs (<MODE>mode, operands[0], operands[1], operands[2], |
10313 | operands[3], operands[4], INTVAL (operands[5])); | |
10314 | DONE;}) | |
3093f076 | 10315 | |
78ce265b RH |
10316 | (define_expand "atomic_compare_and_swap<mode>_internal" |
10317 | [(parallel | |
10318 | [(set (match_operand:DGPR 0 "register_operand") | |
03db9ab5 | 10319 | (match_operand:DGPR 1 "s_operand")) |
78ce265b RH |
10320 | (set (match_dup 1) |
10321 | (unspec_volatile:DGPR | |
10322 | [(match_dup 1) | |
10323 | (match_operand:DGPR 2 "register_operand") | |
10324 | (match_operand:DGPR 3 "register_operand")] | |
10325 | UNSPECV_CAS)) | |
03db9ab5 DV |
10326 | (set (match_operand 4 "cc_reg_operand") |
10327 | (match_dup 5))])] | |
10328 | "GET_MODE (operands[4]) == CCZmode | |
10329 | || GET_MODE (operands[4]) == CCZ1mode" | |
10330 | { | |
10331 | operands[5] | |
10332 | = gen_rtx_COMPARE (GET_MODE (operands[4]), operands[1], operands[2]); | |
10333 | }) | |
78ce265b RH |
10334 | |
10335 | ; cdsg, csg | |
10336 | (define_insn "*atomic_compare_and_swap<mode>_1" | |
10337 | [(set (match_operand:TDI 0 "register_operand" "=r") | |
58814c76 | 10338 | (match_operand:TDI 1 "memory_operand" "+S")) |
8006eaa6 | 10339 | (set (match_dup 1) |
78ce265b | 10340 | (unspec_volatile:TDI |
8006eaa6 | 10341 | [(match_dup 1) |
78ce265b RH |
10342 | (match_operand:TDI 2 "register_operand" "0") |
10343 | (match_operand:TDI 3 "register_operand" "r")] | |
8006eaa6 | 10344 | UNSPECV_CAS)) |
03db9ab5 DV |
10345 | (set (reg CC_REGNUM) |
10346 | (compare (match_dup 1) (match_dup 2)))] | |
10347 | "TARGET_ZARCH | |
10348 | && s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10349 | "c<td>sg\t%0,%3,%S1" |
10350 | [(set_attr "op_type" "RSY") | |
8006eaa6 AS |
10351 | (set_attr "type" "sem")]) |
10352 | ||
78ce265b RH |
10353 | ; cds, cdsy |
10354 | (define_insn "*atomic_compare_and_swapdi_2" | |
10355 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
58814c76 | 10356 | (match_operand:DI 1 "memory_operand" "+Q,S")) |
e0374221 | 10357 | (set (match_dup 1) |
78ce265b RH |
10358 | (unspec_volatile:DI |
10359 | [(match_dup 1) | |
10360 | (match_operand:DI 2 "register_operand" "0,0") | |
10361 | (match_operand:DI 3 "register_operand" "r,r")] | |
10362 | UNSPECV_CAS)) | |
03db9ab5 DV |
10363 | (set (reg CC_REGNUM) |
10364 | (compare (match_dup 1) (match_dup 2)))] | |
10365 | "!TARGET_ZARCH | |
10366 | && s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10367 | "@ |
10368 | cds\t%0,%3,%S1 | |
10369 | cdsy\t%0,%3,%S1" | |
10370 | [(set_attr "op_type" "RS,RSY") | |
3e4be43f | 10371 | (set_attr "cpu_facility" "*,longdisp") |
78ce265b RH |
10372 | (set_attr "type" "sem")]) |
10373 | ||
10374 | ; cs, csy | |
10375 | (define_insn "*atomic_compare_and_swapsi_3" | |
10376 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
58814c76 | 10377 | (match_operand:SI 1 "memory_operand" "+Q,S")) |
78ce265b RH |
10378 | (set (match_dup 1) |
10379 | (unspec_volatile:SI | |
e0374221 | 10380 | [(match_dup 1) |
78ce265b RH |
10381 | (match_operand:SI 2 "register_operand" "0,0") |
10382 | (match_operand:SI 3 "register_operand" "r,r")] | |
e0374221 | 10383 | UNSPECV_CAS)) |
03db9ab5 DV |
10384 | (set (reg CC_REGNUM) |
10385 | (compare (match_dup 1) (match_dup 2)))] | |
10386 | "s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10387 | "@ |
10388 | cs\t%0,%3,%S1 | |
10389 | csy\t%0,%3,%S1" | |
10390 | [(set_attr "op_type" "RS,RSY") | |
3e4be43f | 10391 | (set_attr "cpu_facility" "*,longdisp") |
e0374221 AS |
10392 | (set_attr "type" "sem")]) |
10393 | ||
45d18331 AS |
10394 | ; |
10395 | ; Other atomic instruction patterns. | |
10396 | ; | |
10397 | ||
65b1d8ea AK |
10398 | ; z196 load and add, xor, or and and instructions |
10399 | ||
78ce265b RH |
10400 | (define_expand "atomic_fetch_<atomic><mode>" |
10401 | [(match_operand:GPR 0 "register_operand") ;; val out | |
10402 | (ATOMIC_Z196:GPR | |
10403 | (match_operand:GPR 1 "memory_operand") ;; memory | |
10404 | (match_operand:GPR 2 "register_operand")) ;; val in | |
10405 | (match_operand:SI 3 "const_int_operand")] ;; model | |
65b1d8ea | 10406 | "TARGET_Z196" |
78ce265b | 10407 | { |
75cc21e2 AK |
10408 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
10409 | FAIL; | |
10410 | ||
78ce265b RH |
10411 | emit_insn (gen_atomic_fetch_<atomic><mode>_iaf |
10412 | (operands[0], operands[1], operands[2])); | |
10413 | DONE; | |
10414 | }) | |
65b1d8ea AK |
10415 | |
10416 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
78ce265b RH |
10417 | (define_insn "atomic_fetch_<atomic><mode>_iaf" |
10418 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 10419 | (match_operand:GPR 1 "memory_operand" "+S")) |
78ce265b RH |
10420 | (set (match_dup 1) |
10421 | (unspec_volatile:GPR | |
10422 | [(ATOMIC_Z196:GPR (match_dup 1) | |
10423 | (match_operand:GPR 2 "general_operand" "d"))] | |
10424 | UNSPECV_ATOMIC_OP)) | |
10425 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 10426 | "TARGET_Z196" |
78ce265b RH |
10427 | "la<noxa><g>\t%0,%2,%1" |
10428 | [(set_attr "op_type" "RSY") | |
10429 | (set_attr "type" "sem")]) | |
65b1d8ea | 10430 | |
78ce265b RH |
10431 | ;; For SImode and larger, the optabs.c code will do just fine in |
10432 | ;; expanding a compare-and-swap loop. For QI/HImode, we can do | |
10433 | ;; better by expanding our own loop. | |
65b1d8ea | 10434 | |
78ce265b RH |
10435 | (define_expand "atomic_<atomic><mode>" |
10436 | [(ATOMIC:HQI | |
10437 | (match_operand:HQI 0 "memory_operand") ;; memory | |
10438 | (match_operand:HQI 1 "general_operand")) ;; val in | |
10439 | (match_operand:SI 2 "const_int_operand")] ;; model | |
45d18331 | 10440 | "" |
78ce265b RH |
10441 | { |
10442 | s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], | |
10443 | operands[1], false); | |
10444 | DONE; | |
10445 | }) | |
45d18331 | 10446 | |
78ce265b RH |
10447 | (define_expand "atomic_fetch_<atomic><mode>" |
10448 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10449 | (ATOMIC:HQI | |
10450 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10451 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10452 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 10453 | "" |
78ce265b RH |
10454 | { |
10455 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10456 | operands[2], false); | |
10457 | DONE; | |
10458 | }) | |
10459 | ||
10460 | (define_expand "atomic_<atomic>_fetch<mode>" | |
10461 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10462 | (ATOMIC:HQI | |
10463 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10464 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10465 | (match_operand:SI 3 "const_int_operand")] ;; model | |
10466 | "" | |
10467 | { | |
10468 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10469 | operands[2], true); | |
10470 | DONE; | |
10471 | }) | |
10472 | ||
03db9ab5 DV |
10473 | ;; Pattern to implement atomic_exchange with a compare-and-swap loop. The code |
10474 | ;; generated by the middleend is not good. | |
78ce265b | 10475 | (define_expand "atomic_exchange<mode>" |
03db9ab5 DV |
10476 | [(match_operand:DINT 0 "register_operand") ;; val out |
10477 | (match_operand:DINT 1 "s_operand") ;; memory | |
10478 | (match_operand:DINT 2 "general_operand") ;; val in | |
78ce265b | 10479 | (match_operand:SI 3 "const_int_operand")] ;; model |
45d18331 | 10480 | "" |
78ce265b | 10481 | { |
03db9ab5 DV |
10482 | if (<MODE>mode != QImode |
10483 | && MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (<MODE>mode)) | |
10484 | FAIL; | |
10485 | if (<MODE>mode == HImode || <MODE>mode == QImode) | |
10486 | s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], operands[2], | |
10487 | false); | |
10488 | else if (<MODE>mode == SImode || TARGET_ZARCH) | |
10489 | s390_expand_atomic_exchange_tdsi (operands[0], operands[1], operands[2]); | |
10490 | else | |
10491 | FAIL; | |
78ce265b RH |
10492 | DONE; |
10493 | }) | |
45d18331 | 10494 | |
9db1d521 HP |
10495 | ;; |
10496 | ;;- Miscellaneous instructions. | |
10497 | ;; | |
10498 | ||
10499 | ; | |
10500 | ; allocate stack instruction pattern(s). | |
10501 | ; | |
10502 | ||
10503 | (define_expand "allocate_stack" | |
ef44a6ff UW |
10504 | [(match_operand 0 "general_operand" "") |
10505 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 10506 | "TARGET_BACKCHAIN" |
9db1d521 | 10507 | { |
ef44a6ff | 10508 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 10509 | |
ef44a6ff UW |
10510 | emit_move_insn (temp, s390_back_chain_rtx ()); |
10511 | anti_adjust_stack (operands[1]); | |
10512 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 10513 | |
ef44a6ff UW |
10514 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
10515 | DONE; | |
10bbf137 | 10516 | }) |
9db1d521 HP |
10517 | |
10518 | ||
10519 | ; | |
43ab026f | 10520 | ; setjmp instruction pattern. |
9db1d521 HP |
10521 | ; |
10522 | ||
9db1d521 | 10523 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 10524 | [(match_operand 0 "" "")] |
f314b9b1 | 10525 | "flag_pic" |
9db1d521 | 10526 | { |
585539a1 | 10527 | emit_insn (s390_load_got ()); |
c41c1387 | 10528 | emit_use (pic_offset_table_rtx); |
9db1d521 | 10529 | DONE; |
fd7643fb | 10530 | }) |
9db1d521 | 10531 | |
9db1d521 HP |
10532 | ;; These patterns say how to save and restore the stack pointer. We need not |
10533 | ;; save the stack pointer at function level since we are careful to | |
10534 | ;; preserve the backchain. At block level, we have to restore the backchain | |
10535 | ;; when we restore the stack pointer. | |
10536 | ;; | |
10537 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
10538 | ;; backchain and restore both. Note that in the nonlocal case, the | |
10539 | ;; save area is a memory location. | |
10540 | ||
10541 | (define_expand "save_stack_function" | |
10542 | [(match_operand 0 "general_operand" "") | |
10543 | (match_operand 1 "general_operand" "")] | |
10544 | "" | |
10545 | "DONE;") | |
10546 | ||
10547 | (define_expand "restore_stack_function" | |
10548 | [(match_operand 0 "general_operand" "") | |
10549 | (match_operand 1 "general_operand" "")] | |
10550 | "" | |
10551 | "DONE;") | |
10552 | ||
10553 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
10554 | [(match_operand 0 "register_operand" "") |
10555 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 10556 | "TARGET_BACKCHAIN" |
9db1d521 | 10557 | { |
ef44a6ff UW |
10558 | rtx temp = gen_reg_rtx (Pmode); |
10559 | ||
10560 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
10561 | emit_move_insn (operands[0], operands[1]); | |
10562 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10563 | ||
10564 | DONE; | |
10bbf137 | 10565 | }) |
9db1d521 HP |
10566 | |
10567 | (define_expand "save_stack_nonlocal" | |
10568 | [(match_operand 0 "memory_operand" "") | |
10569 | (match_operand 1 "register_operand" "")] | |
10570 | "" | |
9db1d521 | 10571 | { |
ef44a6ff UW |
10572 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
10573 | ||
10574 | /* Copy the backchain to the first word, sp to the second and the | |
10575 | literal pool base to the third. */ | |
10576 | ||
9602b6a1 AK |
10577 | rtx save_bc = adjust_address (operands[0], Pmode, 0); |
10578 | rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); | |
10579 | rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10580 | ||
b3d31392 | 10581 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10582 | emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); |
ef44a6ff | 10583 | |
9602b6a1 AK |
10584 | emit_move_insn (save_sp, operands[1]); |
10585 | emit_move_insn (save_bp, base); | |
9db1d521 | 10586 | |
9db1d521 | 10587 | DONE; |
10bbf137 | 10588 | }) |
9db1d521 HP |
10589 | |
10590 | (define_expand "restore_stack_nonlocal" | |
10591 | [(match_operand 0 "register_operand" "") | |
10592 | (match_operand 1 "memory_operand" "")] | |
10593 | "" | |
9db1d521 | 10594 | { |
490ceeb4 | 10595 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 10596 | rtx temp = NULL_RTX; |
9db1d521 | 10597 | |
43ab026f | 10598 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 10599 | literal pool base from the third. */ |
43ab026f | 10600 | |
9602b6a1 AK |
10601 | rtx save_bc = adjust_address (operands[1], Pmode, 0); |
10602 | rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); | |
10603 | rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10604 | ||
b3d31392 | 10605 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10606 | temp = force_reg (Pmode, save_bc); |
9381e3f1 | 10607 | |
9602b6a1 AK |
10608 | emit_move_insn (base, save_bp); |
10609 | emit_move_insn (operands[0], save_sp); | |
ef44a6ff UW |
10610 | |
10611 | if (temp) | |
10612 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10613 | ||
c41c1387 | 10614 | emit_use (base); |
9db1d521 | 10615 | DONE; |
10bbf137 | 10616 | }) |
9db1d521 | 10617 | |
7bcebb25 AK |
10618 | (define_expand "exception_receiver" |
10619 | [(const_int 0)] | |
10620 | "" | |
10621 | { | |
10622 | s390_set_has_landing_pad_p (true); | |
10623 | DONE; | |
10624 | }) | |
9db1d521 HP |
10625 | |
10626 | ; | |
10627 | ; nop instruction pattern(s). | |
10628 | ; | |
10629 | ||
10630 | (define_insn "nop" | |
10631 | [(const_int 0)] | |
10632 | "" | |
aad98a61 AK |
10633 | "nopr\t%%r0" |
10634 | [(set_attr "op_type" "RR")]) | |
10635 | ||
10636 | ; non-branch NOPs required for optimizing compare-and-branch patterns | |
10637 | ; on z10 | |
10638 | ||
10639 | (define_insn "nop_lr0" | |
10640 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_0)] | |
10641 | "" | |
d40c829f | 10642 | "lr\t0,0" |
729e750f WG |
10643 | [(set_attr "op_type" "RR") |
10644 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 10645 | |
aad98a61 AK |
10646 | (define_insn "nop_lr1" |
10647 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_1)] | |
d277db6b WG |
10648 | "" |
10649 | "lr\t1,1" | |
10650 | [(set_attr "op_type" "RR")]) | |
10651 | ||
f8af0e30 DV |
10652 | ;;- Undeletable nops (used for hotpatching) |
10653 | ||
10654 | (define_insn "nop_2_byte" | |
10655 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)] | |
10656 | "" | |
4bbc8970 | 10657 | "nopr\t%%r0" |
f8af0e30 DV |
10658 | [(set_attr "op_type" "RR")]) |
10659 | ||
10660 | (define_insn "nop_4_byte" | |
10661 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)] | |
10662 | "" | |
10663 | "nop\t0" | |
10664 | [(set_attr "op_type" "RX")]) | |
10665 | ||
10666 | (define_insn "nop_6_byte" | |
10667 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)] | |
8cc6307c | 10668 | "" |
f8af0e30 DV |
10669 | "brcl\t0, 0" |
10670 | [(set_attr "op_type" "RIL")]) | |
10671 | ||
9db1d521 HP |
10672 | |
10673 | ; | |
10674 | ; Special literal pool access instruction pattern(s). | |
10675 | ; | |
10676 | ||
416cf582 UW |
10677 | (define_insn "*pool_entry" |
10678 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
10679 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 10680 | "" |
9db1d521 | 10681 | { |
ef4bddc2 | 10682 | machine_mode mode = GET_MODE (PATTERN (insn)); |
416cf582 | 10683 | unsigned int align = GET_MODE_BITSIZE (mode); |
faeb9bb6 | 10684 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
10685 | return ""; |
10686 | } | |
b628bd8e | 10687 | [(set (attr "length") |
416cf582 | 10688 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 10689 | |
9bb86f41 UW |
10690 | (define_insn "pool_align" |
10691 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
10692 | UNSPECV_POOL_ALIGN)] | |
10693 | "" | |
10694 | ".align\t%0" | |
b628bd8e | 10695 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 10696 | |
9bb86f41 UW |
10697 | (define_insn "pool_section_start" |
10698 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
10699 | "" | |
b929b470 MK |
10700 | { |
10701 | switch_to_section (targetm.asm_out.function_rodata_section | |
10702 | (current_function_decl)); | |
10703 | return ""; | |
10704 | } | |
b628bd8e | 10705 | [(set_attr "length" "0")]) |
b2ccb744 | 10706 | |
9bb86f41 UW |
10707 | (define_insn "pool_section_end" |
10708 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
10709 | "" | |
b929b470 MK |
10710 | { |
10711 | switch_to_section (current_function_section ()); | |
10712 | return ""; | |
10713 | } | |
b628bd8e | 10714 | [(set_attr "length" "0")]) |
b2ccb744 | 10715 | |
5af2f3d3 | 10716 | (define_insn "main_base_64" |
9e8327e3 UW |
10717 | [(set (match_operand 0 "register_operand" "=a") |
10718 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
8cc6307c | 10719 | "GET_MODE (operands[0]) == Pmode" |
5af2f3d3 UW |
10720 | "larl\t%0,%1" |
10721 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 10722 | (set_attr "type" "larl") |
729e750f | 10723 | (set_attr "z10prop" "z10_fwd_A1")]) |
5af2f3d3 UW |
10724 | |
10725 | (define_insn "main_pool" | |
585539a1 UW |
10726 | [(set (match_operand 0 "register_operand" "=a") |
10727 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
10728 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
10729 | { |
10730 | gcc_unreachable (); | |
10731 | } | |
9381e3f1 | 10732 | [(set (attr "type") |
8cc6307c | 10733 | (const_string "larl"))]) |
b2ccb744 | 10734 | |
aee4e0db | 10735 | (define_insn "reload_base_64" |
9e8327e3 UW |
10736 | [(set (match_operand 0 "register_operand" "=a") |
10737 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
8cc6307c | 10738 | "GET_MODE (operands[0]) == Pmode" |
d40c829f | 10739 | "larl\t%0,%1" |
aee4e0db | 10740 | [(set_attr "op_type" "RIL") |
9381e3f1 | 10741 | (set_attr "type" "larl") |
729e750f | 10742 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 10743 | |
aee4e0db | 10744 | (define_insn "pool" |
fd7643fb | 10745 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 10746 | "" |
8d933e31 AS |
10747 | { |
10748 | gcc_unreachable (); | |
10749 | } | |
b628bd8e | 10750 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 10751 | |
4023fb28 UW |
10752 | ;; |
10753 | ;; Insns related to generating the function prologue and epilogue. | |
10754 | ;; | |
10755 | ||
10756 | ||
10757 | (define_expand "prologue" | |
10758 | [(use (const_int 0))] | |
10759 | "" | |
10bbf137 | 10760 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
10761 | |
10762 | (define_expand "epilogue" | |
10763 | [(use (const_int 1))] | |
10764 | "" | |
ed9676cf AK |
10765 | "s390_emit_epilogue (false); DONE;") |
10766 | ||
10767 | (define_expand "sibcall_epilogue" | |
10768 | [(use (const_int 0))] | |
10769 | "" | |
10770 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 10771 | |
177bc204 RS |
10772 | ;; A direct return instruction, without using an epilogue. |
10773 | (define_insn "<code>" | |
10774 | [(ANY_RETURN)] | |
10775 | "s390_can_use_<code>_insn ()" | |
84b4c7b5 AK |
10776 | { |
10777 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
10778 | { | |
10779 | /* The target is always r14 so there is no clobber | |
10780 | of r1 needed for pre z10 targets. */ | |
10781 | s390_indirect_branch_via_thunk (RETURN_REGNUM, | |
10782 | INVALID_REGNUM, | |
10783 | NULL_RTX, | |
10784 | s390_indirect_branch_type_return); | |
10785 | return ""; | |
10786 | } | |
10787 | else | |
10788 | return "br\t%%r14"; | |
10789 | } | |
10790 | [(set (attr "op_type") | |
10791 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
10792 | (const_string "RIL") | |
10793 | (const_string "RR"))) | |
10794 | (set (attr "mnemonic") | |
10795 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
10796 | (const_string "jg") | |
10797 | (const_string "br"))) | |
177bc204 RS |
10798 | (set_attr "type" "jsr") |
10799 | (set_attr "atype" "agen")]) | |
10800 | ||
84b4c7b5 AK |
10801 | |
10802 | (define_expand "return_use" | |
10803 | [(parallel | |
10804 | [(return) | |
10805 | (use (match_operand 0 "register_operand" "a"))])] | |
10806 | "" | |
10807 | { | |
10808 | if (!TARGET_CPU_Z10 | |
10809 | && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION) | |
10810 | { | |
10811 | if (TARGET_64BIT) | |
10812 | emit_jump_insn (gen_returndi_prez10 (operands[0])); | |
10813 | else | |
10814 | emit_jump_insn (gen_returnsi_prez10 (operands[0])); | |
10815 | DONE; | |
10816 | } | |
10817 | }) | |
10818 | ||
10819 | (define_insn "*return<mode>" | |
4023fb28 | 10820 | [(return) |
84b4c7b5 AK |
10821 | (use (match_operand:P 0 "register_operand" "a"))] |
10822 | "TARGET_CPU_Z10 || !TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION" | |
10823 | { | |
10824 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
10825 | { | |
10826 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10827 | INVALID_REGNUM, | |
10828 | NULL_RTX, | |
10829 | s390_indirect_branch_type_return); | |
10830 | return ""; | |
10831 | } | |
10832 | else | |
10833 | return "br\t%0"; | |
10834 | } | |
10835 | [(set (attr "op_type") | |
10836 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
10837 | (const_string "RIL") | |
10838 | (const_string "RR"))) | |
10839 | (set (attr "mnemonic") | |
10840 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
10841 | (const_string "jg") | |
10842 | (const_string "br"))) | |
10843 | (set_attr "type" "jsr") | |
10844 | (set_attr "atype" "agen")]) | |
10845 | ||
10846 | (define_insn "return<mode>_prez10" | |
10847 | [(return) | |
10848 | (use (match_operand:P 0 "register_operand" "a")) | |
10849 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
10850 | "!TARGET_CPU_Z10 && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION" | |
10851 | { | |
10852 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
10853 | { | |
10854 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10855 | INVALID_REGNUM, | |
10856 | NULL_RTX, | |
10857 | s390_indirect_branch_type_return); | |
10858 | return ""; | |
10859 | } | |
10860 | else | |
10861 | return "br\t%0"; | |
10862 | } | |
10863 | [(set (attr "op_type") | |
10864 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
10865 | (const_string "RIL") | |
10866 | (const_string "RR"))) | |
10867 | (set (attr "mnemonic") | |
10868 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
10869 | (const_string "jg") | |
10870 | (const_string "br"))) | |
c7453384 | 10871 | (set_attr "type" "jsr") |
077dab3b | 10872 | (set_attr "atype" "agen")]) |
4023fb28 | 10873 | |
4023fb28 | 10874 | |
c7453384 | 10875 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 10876 | ;; pointer. This is used for compatibility. |
c7453384 EC |
10877 | |
10878 | (define_expand "ptr_extend" | |
10879 | [(set (match_operand:DI 0 "register_operand" "=r") | |
10880 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 10881 | "TARGET_64BIT" |
c7453384 | 10882 | { |
c7453384 EC |
10883 | emit_insn (gen_anddi3 (operands[0], |
10884 | gen_lowpart (DImode, operands[1]), | |
10885 | GEN_INT (0x7fffffff))); | |
c7453384 | 10886 | DONE; |
10bbf137 | 10887 | }) |
4798630c D |
10888 | |
10889 | ;; Instruction definition to expand eh_return macro to support | |
10890 | ;; swapping in special linkage return addresses. | |
10891 | ||
10892 | (define_expand "eh_return" | |
10893 | [(use (match_operand 0 "register_operand" ""))] | |
10894 | "TARGET_TPF" | |
10895 | { | |
10896 | s390_emit_tpf_eh_return (operands[0]); | |
10897 | DONE; | |
10898 | }) | |
10899 | ||
7b8acc34 AK |
10900 | ; |
10901 | ; Stack Protector Patterns | |
10902 | ; | |
10903 | ||
10904 | (define_expand "stack_protect_set" | |
10905 | [(set (match_operand 0 "memory_operand" "") | |
10906 | (match_operand 1 "memory_operand" ""))] | |
10907 | "" | |
10908 | { | |
10909 | #ifdef TARGET_THREAD_SSP_OFFSET | |
10910 | operands[1] | |
10911 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
10912 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
10913 | #endif | |
10914 | if (TARGET_64BIT) | |
10915 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
10916 | else | |
10917 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
10918 | ||
10919 | DONE; | |
10920 | }) | |
10921 | ||
10922 | (define_insn "stack_protect_set<mode>" | |
10923 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
10924 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
10925 | "" | |
10926 | "mvc\t%O0(%G0,%R0),%S1" | |
10927 | [(set_attr "op_type" "SS")]) | |
10928 | ||
10929 | (define_expand "stack_protect_test" | |
10930 | [(set (reg:CC CC_REGNUM) | |
10931 | (compare (match_operand 0 "memory_operand" "") | |
10932 | (match_operand 1 "memory_operand" ""))) | |
10933 | (match_operand 2 "" "")] | |
10934 | "" | |
10935 | { | |
f90b7a5a | 10936 | rtx cc_reg, test; |
7b8acc34 AK |
10937 | #ifdef TARGET_THREAD_SSP_OFFSET |
10938 | operands[1] | |
10939 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
10940 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
10941 | #endif | |
7b8acc34 AK |
10942 | if (TARGET_64BIT) |
10943 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
10944 | else | |
10945 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
10946 | ||
f90b7a5a PB |
10947 | cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); |
10948 | test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); | |
10949 | emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); | |
7b8acc34 AK |
10950 | DONE; |
10951 | }) | |
10952 | ||
10953 | (define_insn "stack_protect_test<mode>" | |
10954 | [(set (reg:CCZ CC_REGNUM) | |
10955 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
10956 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
10957 | "" | |
10958 | "clc\t%O0(%G0,%R0),%S1" | |
10959 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
10960 | |
10961 | ; This is used in s390_emit_prologue in order to prevent insns | |
10962 | ; adjusting the stack pointer to be moved over insns writing stack | |
10963 | ; slots using a copy of the stack pointer in a different register. | |
10964 | (define_insn "stack_tie" | |
10965 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
10966 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
10967 | "" | |
10968 | "" | |
10969 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
10970 | |
10971 | ||
82c6f58a AK |
10972 | (define_insn "stack_restore_from_fpr" |
10973 | [(set (reg:DI STACK_REGNUM) | |
10974 | (match_operand:DI 0 "register_operand" "f")) | |
10975 | (clobber (mem:BLK (scratch)))] | |
10976 | "TARGET_Z10" | |
10977 | "lgdr\t%%r15,%0" | |
10978 | [(set_attr "op_type" "RRE")]) | |
10979 | ||
963fc8d0 AK |
10980 | ; |
10981 | ; Data prefetch patterns | |
10982 | ; | |
10983 | ||
10984 | (define_insn "prefetch" | |
3e4be43f UW |
10985 | [(prefetch (match_operand 0 "address_operand" "ZT,X") |
10986 | (match_operand:SI 1 "const_int_operand" " n,n") | |
10987 | (match_operand:SI 2 "const_int_operand" " n,n"))] | |
22d72dbc | 10988 | "TARGET_Z10" |
963fc8d0 | 10989 | { |
4fe6dea8 AK |
10990 | switch (which_alternative) |
10991 | { | |
10992 | case 0: | |
4fe6dea8 | 10993 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; |
22d72dbc | 10994 | case 1: |
4fe6dea8 AK |
10995 | if (larl_operand (operands[0], Pmode)) |
10996 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
a65593a4 | 10997 | /* fallthrough */ |
4fe6dea8 AK |
10998 | default: |
10999 | ||
11000 | /* This might be reached for symbolic operands with an odd | |
11001 | addend. We simply omit the prefetch for such rare cases. */ | |
11002 | ||
11003 | return ""; | |
11004 | } | |
9381e3f1 | 11005 | } |
22d72dbc AK |
11006 | [(set_attr "type" "load,larl") |
11007 | (set_attr "op_type" "RXY,RIL") | |
65b1d8ea AK |
11008 | (set_attr "z10prop" "z10_super") |
11009 | (set_attr "z196prop" "z196_alone")]) | |
07da44ab AK |
11010 | |
11011 | ||
11012 | ; | |
11013 | ; Byte swap instructions | |
11014 | ; | |
11015 | ||
511f5bb1 AK |
11016 | ; FIXME: There is also mvcin but we cannot use it since src and target |
11017 | ; may overlap. | |
50dc4eed | 11018 | ; lrvr, lrv, strv, lrvgr, lrvg, strvg |
07da44ab | 11019 | (define_insn "bswap<mode>2" |
3e4be43f UW |
11020 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T") |
11021 | (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))] | |
8cc6307c | 11022 | "" |
07da44ab AK |
11023 | "@ |
11024 | lrv<g>r\t%0,%1 | |
6f5a59d1 AK |
11025 | lrv<g>\t%0,%1 |
11026 | strv<g>\t%1,%0" | |
11027 | [(set_attr "type" "*,load,store") | |
11028 | (set_attr "op_type" "RRE,RXY,RXY") | |
07da44ab | 11029 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 11030 | |
511f5bb1 | 11031 | (define_insn "bswaphi2" |
3e4be43f UW |
11032 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T") |
11033 | (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))] | |
8cc6307c | 11034 | "" |
6f5a59d1 AK |
11035 | "@ |
11036 | # | |
11037 | lrvh\t%0,%1 | |
11038 | strvh\t%1,%0" | |
11039 | [(set_attr "type" "*,load,store") | |
11040 | (set_attr "op_type" "RRE,RXY,RXY") | |
511f5bb1 | 11041 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 11042 | |
6f5a59d1 AK |
11043 | (define_split |
11044 | [(set (match_operand:HI 0 "register_operand" "") | |
11045 | (bswap:HI (match_operand:HI 1 "register_operand" "")))] | |
8cc6307c | 11046 | "" |
6f5a59d1 | 11047 | [(set (match_dup 2) (bswap:SI (match_dup 3))) |
9060e335 | 11048 | (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))] |
6f5a59d1 | 11049 | { |
9060e335 | 11050 | operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0); |
6f5a59d1 AK |
11051 | operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0); |
11052 | }) | |
11053 | ||
11054 | ||
65b1d8ea AK |
11055 | ; |
11056 | ; Population count instruction | |
11057 | ; | |
11058 | ||
11059 | ; The S/390 popcount instruction counts the bits of op1 in 8 byte | |
11060 | ; portions and stores the result in the corresponding bytes in op0. | |
11061 | (define_insn "*popcount<mode>" | |
11062 | [(set (match_operand:INT 0 "register_operand" "=d") | |
11063 | (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) | |
11064 | (clobber (reg:CC CC_REGNUM))] | |
11065 | "TARGET_Z196" | |
11066 | "popcnt\t%0,%1" | |
11067 | [(set_attr "op_type" "RRE")]) | |
11068 | ||
11069 | (define_expand "popcountdi2" | |
11070 | [; popcnt op0, op1 | |
11071 | (parallel [(set (match_operand:DI 0 "register_operand" "") | |
11072 | (unspec:DI [(match_operand:DI 1 "register_operand")] | |
11073 | UNSPEC_POPCNT)) | |
11074 | (clobber (reg:CC CC_REGNUM))]) | |
11075 | ; sllg op2, op0, 32 | |
11076 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) | |
11077 | ; agr op0, op2 | |
11078 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11079 | (clobber (reg:CC CC_REGNUM))]) | |
11080 | ; sllg op2, op0, 16 | |
17465c6e | 11081 | (set (match_dup 2) |
65b1d8ea AK |
11082 | (ashift:DI (match_dup 0) (const_int 16))) |
11083 | ; agr op0, op2 | |
11084 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11085 | (clobber (reg:CC CC_REGNUM))]) | |
11086 | ; sllg op2, op0, 8 | |
11087 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) | |
11088 | ; agr op0, op2 | |
11089 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11090 | (clobber (reg:CC CC_REGNUM))]) | |
11091 | ; srlg op0, op0, 56 | |
11092 | (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] | |
11093 | "TARGET_Z196 && TARGET_64BIT" | |
11094 | "operands[2] = gen_reg_rtx (DImode);") | |
11095 | ||
11096 | (define_expand "popcountsi2" | |
11097 | [; popcnt op0, op1 | |
11098 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
11099 | (unspec:SI [(match_operand:SI 1 "register_operand")] | |
11100 | UNSPEC_POPCNT)) | |
11101 | (clobber (reg:CC CC_REGNUM))]) | |
11102 | ; sllk op2, op0, 16 | |
17465c6e | 11103 | (set (match_dup 2) |
65b1d8ea AK |
11104 | (ashift:SI (match_dup 0) (const_int 16))) |
11105 | ; ar op0, op2 | |
11106 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11107 | (clobber (reg:CC CC_REGNUM))]) | |
11108 | ; sllk op2, op0, 8 | |
11109 | (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) | |
11110 | ; ar op0, op2 | |
11111 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11112 | (clobber (reg:CC CC_REGNUM))]) | |
11113 | ; srl op0, op0, 24 | |
11114 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | |
11115 | "TARGET_Z196" | |
11116 | "operands[2] = gen_reg_rtx (SImode);") | |
11117 | ||
11118 | (define_expand "popcounthi2" | |
11119 | [; popcnt op0, op1 | |
11120 | (parallel [(set (match_operand:HI 0 "register_operand" "") | |
11121 | (unspec:HI [(match_operand:HI 1 "register_operand")] | |
11122 | UNSPEC_POPCNT)) | |
11123 | (clobber (reg:CC CC_REGNUM))]) | |
11124 | ; sllk op2, op0, 8 | |
17465c6e | 11125 | (set (match_dup 2) |
65b1d8ea AK |
11126 | (ashift:SI (match_dup 0) (const_int 8))) |
11127 | ; ar op0, op2 | |
11128 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11129 | (clobber (reg:CC CC_REGNUM))]) | |
11130 | ; srl op0, op0, 8 | |
11131 | (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] | |
11132 | "TARGET_Z196" | |
11133 | "operands[2] = gen_reg_rtx (SImode);") | |
11134 | ||
11135 | (define_expand "popcountqi2" | |
11136 | [; popcnt op0, op1 | |
11137 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
11138 | (unspec:QI [(match_operand:QI 1 "register_operand")] | |
11139 | UNSPEC_POPCNT)) | |
11140 | (clobber (reg:CC CC_REGNUM))])] | |
11141 | "TARGET_Z196" | |
11142 | "") | |
11143 | ||
11144 | ;; | |
11145 | ;;- Copy sign instructions | |
11146 | ;; | |
11147 | ||
11148 | (define_insn "copysign<mode>3" | |
11149 | [(set (match_operand:FP 0 "register_operand" "=f") | |
11150 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
11151 | (match_operand:FP 2 "register_operand" "f")] | |
11152 | UNSPEC_COPYSIGN))] | |
11153 | "TARGET_Z196" | |
11154 | "cpsdr\t%0,%2,%1" | |
11155 | [(set_attr "op_type" "RRF") | |
11156 | (set_attr "type" "fsimp<mode>")]) | |
5a3fe9b6 AK |
11157 | |
11158 | ||
11159 | ;; | |
11160 | ;;- Transactional execution instructions | |
11161 | ;; | |
11162 | ||
11163 | ; This splitter helps combine to make use of CC directly when | |
11164 | ; comparing the integer result of a tbegin builtin with a constant. | |
11165 | ; The unspec is already removed by canonicalize_comparison. So this | |
11166 | ; splitters only job is to turn the PARALLEL into separate insns | |
11167 | ; again. Unfortunately this only works with the very first cc/int | |
11168 | ; compare since combine is not able to deal with data flow across | |
11169 | ; basic block boundaries. | |
11170 | ||
11171 | ; It needs to be an insn pattern as well since combine does not apply | |
11172 | ; the splitter directly. Combine would only use it if it actually | |
11173 | ; would reduce the number of instructions. | |
11174 | (define_insn_and_split "*ccraw_to_int" | |
11175 | [(set (pc) | |
11176 | (if_then_else | |
11177 | (match_operator 0 "s390_eqne_operator" | |
11178 | [(reg:CCRAW CC_REGNUM) | |
11179 | (match_operand 1 "const_int_operand" "")]) | |
11180 | (label_ref (match_operand 2 "" "")) | |
11181 | (pc))) | |
11182 | (set (match_operand:SI 3 "register_operand" "=d") | |
11183 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] | |
11184 | "" | |
11185 | "#" | |
11186 | "" | |
11187 | [(set (match_dup 3) | |
11188 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) | |
11189 | (set (pc) | |
11190 | (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)]) | |
11191 | (label_ref (match_dup 2)) | |
11192 | (pc)))] | |
11193 | "") | |
11194 | ||
11195 | ; Non-constrained transaction begin | |
11196 | ||
11197 | (define_expand "tbegin" | |
ee163e72 AK |
11198 | [(match_operand:SI 0 "register_operand" "") |
11199 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
11200 | "TARGET_HTM" |
11201 | { | |
11202 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true); | |
11203 | DONE; | |
11204 | }) | |
11205 | ||
11206 | (define_expand "tbegin_nofloat" | |
ee163e72 AK |
11207 | [(match_operand:SI 0 "register_operand" "") |
11208 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
11209 | "TARGET_HTM" |
11210 | { | |
11211 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false); | |
11212 | DONE; | |
11213 | }) | |
11214 | ||
11215 | (define_expand "tbegin_retry" | |
ee163e72 AK |
11216 | [(match_operand:SI 0 "register_operand" "") |
11217 | (match_operand:BLK 1 "memory_operand" "") | |
11218 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
11219 | "TARGET_HTM" |
11220 | { | |
11221 | s390_expand_tbegin (operands[0], operands[1], operands[2], true); | |
11222 | DONE; | |
11223 | }) | |
11224 | ||
11225 | (define_expand "tbegin_retry_nofloat" | |
ee163e72 AK |
11226 | [(match_operand:SI 0 "register_operand" "") |
11227 | (match_operand:BLK 1 "memory_operand" "") | |
11228 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
11229 | "TARGET_HTM" |
11230 | { | |
11231 | s390_expand_tbegin (operands[0], operands[1], operands[2], false); | |
11232 | DONE; | |
11233 | }) | |
11234 | ||
c914ac45 AK |
11235 | ; Clobber VRs since they don't get restored |
11236 | (define_insn "tbegin_1_z13" | |
11237 | [(set (reg:CCRAW CC_REGNUM) | |
11238 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] | |
11239 | UNSPECV_TBEGIN)) | |
11240 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
11241 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
11242 | (clobber (reg:TI 16)) (clobber (reg:TI 38)) | |
11243 | (clobber (reg:TI 17)) (clobber (reg:TI 39)) | |
11244 | (clobber (reg:TI 18)) (clobber (reg:TI 40)) | |
11245 | (clobber (reg:TI 19)) (clobber (reg:TI 41)) | |
11246 | (clobber (reg:TI 20)) (clobber (reg:TI 42)) | |
11247 | (clobber (reg:TI 21)) (clobber (reg:TI 43)) | |
11248 | (clobber (reg:TI 22)) (clobber (reg:TI 44)) | |
11249 | (clobber (reg:TI 23)) (clobber (reg:TI 45)) | |
11250 | (clobber (reg:TI 24)) (clobber (reg:TI 46)) | |
11251 | (clobber (reg:TI 25)) (clobber (reg:TI 47)) | |
11252 | (clobber (reg:TI 26)) (clobber (reg:TI 48)) | |
11253 | (clobber (reg:TI 27)) (clobber (reg:TI 49)) | |
11254 | (clobber (reg:TI 28)) (clobber (reg:TI 50)) | |
11255 | (clobber (reg:TI 29)) (clobber (reg:TI 51)) | |
11256 | (clobber (reg:TI 30)) (clobber (reg:TI 52)) | |
11257 | (clobber (reg:TI 31)) (clobber (reg:TI 53))] | |
11258 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
11259 | ; not supposed to be used for immediates (see genpreds.c). | |
11260 | "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11261 | "tbegin\t%1,%x0" | |
11262 | [(set_attr "op_type" "SIL")]) | |
11263 | ||
5a3fe9b6 AK |
11264 | (define_insn "tbegin_1" |
11265 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d | 11266 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
5a3fe9b6 | 11267 | UNSPECV_TBEGIN)) |
2561451d AK |
11268 | (set (match_operand:BLK 1 "memory_operand" "=Q") |
11269 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
5a3fe9b6 AK |
11270 | (clobber (reg:DF 16)) |
11271 | (clobber (reg:DF 17)) | |
11272 | (clobber (reg:DF 18)) | |
11273 | (clobber (reg:DF 19)) | |
11274 | (clobber (reg:DF 20)) | |
11275 | (clobber (reg:DF 21)) | |
11276 | (clobber (reg:DF 22)) | |
11277 | (clobber (reg:DF 23)) | |
11278 | (clobber (reg:DF 24)) | |
11279 | (clobber (reg:DF 25)) | |
11280 | (clobber (reg:DF 26)) | |
11281 | (clobber (reg:DF 27)) | |
11282 | (clobber (reg:DF 28)) | |
11283 | (clobber (reg:DF 29)) | |
11284 | (clobber (reg:DF 30)) | |
11285 | (clobber (reg:DF 31))] | |
11286 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
11287 | ; not supposed to be used for immediates (see genpreds.c). | |
2561451d AK |
11288 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" |
11289 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
11290 | [(set_attr "op_type" "SIL")]) |
11291 | ||
11292 | ; Same as above but without the FPR clobbers | |
11293 | (define_insn "tbegin_nofloat_1" | |
11294 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d AK |
11295 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
11296 | UNSPECV_TBEGIN)) | |
11297 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
11298 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))] | |
11299 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11300 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
11301 | [(set_attr "op_type" "SIL")]) |
11302 | ||
11303 | ||
11304 | ; Constrained transaction begin | |
11305 | ||
11306 | (define_expand "tbeginc" | |
11307 | [(set (reg:CCRAW CC_REGNUM) | |
11308 | (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)] | |
11309 | UNSPECV_TBEGINC))] | |
11310 | "TARGET_HTM" | |
11311 | "") | |
11312 | ||
11313 | (define_insn "*tbeginc_1" | |
11314 | [(set (reg:CCRAW CC_REGNUM) | |
11315 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")] | |
11316 | UNSPECV_TBEGINC))] | |
11317 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11318 | "tbeginc\t0,%x0" | |
11319 | [(set_attr "op_type" "SIL")]) | |
11320 | ||
11321 | ; Transaction end | |
11322 | ||
11323 | (define_expand "tend" | |
11324 | [(set (reg:CCRAW CC_REGNUM) | |
11325 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND)) | |
ee163e72 | 11326 | (set (match_operand:SI 0 "register_operand" "") |
5a3fe9b6 AK |
11327 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] |
11328 | "TARGET_HTM" | |
11329 | "") | |
11330 | ||
11331 | (define_insn "*tend_1" | |
11332 | [(set (reg:CCRAW CC_REGNUM) | |
11333 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))] | |
11334 | "TARGET_HTM" | |
11335 | "tend" | |
11336 | [(set_attr "op_type" "S")]) | |
11337 | ||
11338 | ; Transaction abort | |
11339 | ||
11340 | (define_expand "tabort" | |
eae48192 | 11341 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")] |
5a3fe9b6 AK |
11342 | UNSPECV_TABORT)] |
11343 | "TARGET_HTM && operands != NULL" | |
11344 | { | |
11345 | if (CONST_INT_P (operands[0]) | |
11346 | && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255) | |
11347 | { | |
f3981e7e | 11348 | error ("invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC |
5a3fe9b6 AK |
11349 | ". Values in range 0 through 255 are reserved.", |
11350 | INTVAL (operands[0])); | |
11351 | FAIL; | |
11352 | } | |
11353 | }) | |
11354 | ||
11355 | (define_insn "*tabort_1" | |
eae48192 | 11356 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")] |
5a3fe9b6 AK |
11357 | UNSPECV_TABORT)] |
11358 | "TARGET_HTM && operands != NULL" | |
11359 | "tabort\t%Y0" | |
11360 | [(set_attr "op_type" "S")]) | |
11361 | ||
eae48192 AK |
11362 | (define_insn "*tabort_1_plus" |
11363 | [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand" "a") | |
11364 | (match_operand:SI 1 "const_int_operand" "J"))] | |
11365 | UNSPECV_TABORT)] | |
11366 | "TARGET_HTM && operands != NULL | |
11367 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")" | |
11368 | "tabort\t%1(%0)" | |
11369 | [(set_attr "op_type" "S")]) | |
11370 | ||
5a3fe9b6 AK |
11371 | ; Transaction extract nesting depth |
11372 | ||
11373 | (define_insn "etnd" | |
11374 | [(set (match_operand:SI 0 "register_operand" "=d") | |
11375 | (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))] | |
11376 | "TARGET_HTM" | |
11377 | "etnd\t%0" | |
11378 | [(set_attr "op_type" "RRE")]) | |
11379 | ||
11380 | ; Non-transactional store | |
11381 | ||
11382 | (define_insn "ntstg" | |
3e4be43f | 11383 | [(set (match_operand:DI 0 "memory_operand" "=T") |
5a3fe9b6 AK |
11384 | (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] |
11385 | UNSPECV_NTSTG))] | |
11386 | "TARGET_HTM" | |
11387 | "ntstg\t%1,%0" | |
11388 | [(set_attr "op_type" "RXY")]) | |
11389 | ||
11390 | ; Transaction perform processor assist | |
11391 | ||
11392 | (define_expand "tx_assist" | |
2561451d AK |
11393 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "") |
11394 | (reg:SI GPR0_REGNUM) | |
5a3fe9b6 AK |
11395 | (const_int 1)] |
11396 | UNSPECV_PPA)] | |
11397 | "TARGET_HTM" | |
2561451d | 11398 | "") |
5a3fe9b6 AK |
11399 | |
11400 | (define_insn "*ppa" | |
11401 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") | |
11402 | (match_operand:SI 1 "register_operand" "d") | |
11403 | (match_operand 2 "const_int_operand" "I")] | |
11404 | UNSPECV_PPA)] | |
11405 | "TARGET_HTM && INTVAL (operands[2]) < 16" | |
2561451d | 11406 | "ppa\t%0,%1,%2" |
5a3fe9b6 | 11407 | [(set_attr "op_type" "RRF")]) |
004f64e1 AK |
11408 | |
11409 | ||
11410 | ; Set and get floating point control register | |
11411 | ||
3af82a61 | 11412 | (define_insn "sfpc" |
004f64e1 AK |
11413 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] |
11414 | UNSPECV_SFPC)] | |
11415 | "TARGET_HARD_FLOAT" | |
11416 | "sfpc\t%0") | |
11417 | ||
3af82a61 | 11418 | (define_insn "efpc" |
004f64e1 AK |
11419 | [(set (match_operand:SI 0 "register_operand" "=d") |
11420 | (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))] | |
11421 | "TARGET_HARD_FLOAT" | |
11422 | "efpc\t%0") | |
3af82a61 AK |
11423 | |
11424 | ||
11425 | ; Load count to block boundary | |
11426 | ||
11427 | (define_insn "lcbb" | |
11428 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3e4be43f | 11429 | (unspec:SI [(match_operand 1 "address_operand" "ZR") |
3af82a61 AK |
11430 | (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB)) |
11431 | (clobber (reg:CC CC_REGNUM))] | |
11432 | "TARGET_Z13" | |
9a36359e | 11433 | "lcbb\t%0,%a1,%b2" |
3af82a61 | 11434 | [(set_attr "op_type" "VRX")]) |
4cb4721f MK |
11435 | |
11436 | ; Handle -fsplit-stack. | |
11437 | ||
11438 | (define_expand "split_stack_prologue" | |
11439 | [(const_int 0)] | |
11440 | "" | |
11441 | { | |
11442 | s390_expand_split_stack_prologue (); | |
11443 | DONE; | |
11444 | }) | |
11445 | ||
11446 | ;; If there are operand 0 bytes available on the stack, jump to | |
11447 | ;; operand 1. | |
11448 | ||
11449 | (define_expand "split_stack_space_check" | |
11450 | [(set (pc) (if_then_else | |
11451 | (ltu (minus (reg 15) | |
11452 | (match_operand 0 "register_operand")) | |
11453 | (unspec [(const_int 0)] UNSPEC_STACK_CHECK)) | |
11454 | (label_ref (match_operand 1)) | |
11455 | (pc)))] | |
11456 | "" | |
11457 | { | |
11458 | /* Offset from thread pointer to __private_ss. */ | |
11459 | int psso = TARGET_64BIT ? 0x38 : 0x20; | |
11460 | rtx tp = s390_get_thread_pointer (); | |
11461 | rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso)); | |
11462 | rtx reg = gen_reg_rtx (Pmode); | |
11463 | rtx cc; | |
11464 | if (TARGET_64BIT) | |
11465 | emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0])); | |
11466 | else | |
11467 | emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0])); | |
11468 | cc = s390_emit_compare (GT, reg, guard); | |
11469 | s390_emit_jump (operands[1], cc); | |
11470 | ||
11471 | DONE; | |
11472 | }) | |
11473 | ||
11474 | ;; __morestack parameter block for split stack prologue. Parameters are: | |
11475 | ;; parameter block label, label to be called by __morestack, frame size, | |
11476 | ;; stack parameter size. | |
11477 | ||
11478 | (define_insn "split_stack_data" | |
11479 | [(unspec_volatile [(match_operand 0 "" "X") | |
11480 | (match_operand 1 "" "X") | |
11481 | (match_operand 2 "const_int_operand" "X") | |
11482 | (match_operand 3 "const_int_operand" "X")] | |
11483 | UNSPECV_SPLIT_STACK_DATA)] | |
8cc6307c | 11484 | "" |
4cb4721f MK |
11485 | { |
11486 | switch_to_section (targetm.asm_out.function_rodata_section | |
11487 | (current_function_decl)); | |
11488 | ||
11489 | if (TARGET_64BIT) | |
11490 | output_asm_insn (".align\t8", operands); | |
11491 | else | |
11492 | output_asm_insn (".align\t4", operands); | |
11493 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
11494 | CODE_LABEL_NUMBER (operands[0])); | |
11495 | if (TARGET_64BIT) | |
11496 | { | |
11497 | output_asm_insn (".quad\t%2", operands); | |
11498 | output_asm_insn (".quad\t%3", operands); | |
11499 | output_asm_insn (".quad\t%1-%0", operands); | |
11500 | } | |
11501 | else | |
11502 | { | |
11503 | output_asm_insn (".long\t%2", operands); | |
11504 | output_asm_insn (".long\t%3", operands); | |
11505 | output_asm_insn (".long\t%1-%0", operands); | |
11506 | } | |
11507 | ||
11508 | switch_to_section (current_function_section ()); | |
11509 | return ""; | |
11510 | } | |
11511 | [(set_attr "length" "0")]) | |
11512 | ||
11513 | ||
11514 | ;; A jg with minimal fuss for use in split stack prologue. | |
11515 | ||
11516 | (define_expand "split_stack_call" | |
11517 | [(match_operand 0 "bras_sym_operand" "X") | |
11518 | (match_operand 1 "" "")] | |
8cc6307c | 11519 | "" |
4cb4721f MK |
11520 | { |
11521 | if (TARGET_64BIT) | |
11522 | emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1])); | |
11523 | else | |
11524 | emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1])); | |
11525 | DONE; | |
11526 | }) | |
11527 | ||
11528 | (define_insn "split_stack_call_<mode>" | |
11529 | [(set (pc) (label_ref (match_operand 1 "" ""))) | |
11530 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
11531 | (reg:P 1)] | |
11532 | UNSPECV_SPLIT_STACK_CALL))] | |
8cc6307c | 11533 | "" |
4cb4721f MK |
11534 | "jg\t%0" |
11535 | [(set_attr "op_type" "RIL") | |
11536 | (set_attr "type" "branch")]) | |
11537 | ||
11538 | ;; Also a conditional one. | |
11539 | ||
11540 | (define_expand "split_stack_cond_call" | |
11541 | [(match_operand 0 "bras_sym_operand" "X") | |
11542 | (match_operand 1 "" "") | |
11543 | (match_operand 2 "" "")] | |
8cc6307c | 11544 | "" |
4cb4721f MK |
11545 | { |
11546 | if (TARGET_64BIT) | |
11547 | emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2])); | |
11548 | else | |
11549 | emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2])); | |
11550 | DONE; | |
11551 | }) | |
11552 | ||
11553 | (define_insn "split_stack_cond_call_<mode>" | |
11554 | [(set (pc) | |
11555 | (if_then_else | |
11556 | (match_operand 1 "" "") | |
11557 | (label_ref (match_operand 2 "" "")) | |
11558 | (pc))) | |
11559 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
11560 | (reg:P 1)] | |
11561 | UNSPECV_SPLIT_STACK_CALL))] | |
8cc6307c | 11562 | "" |
4cb4721f MK |
11563 | "jg%C1\t%0" |
11564 | [(set_attr "op_type" "RIL") | |
11565 | (set_attr "type" "branch")]) | |
539405d5 AK |
11566 | |
11567 | (define_insn "osc_break" | |
11568 | [(unspec_volatile [(const_int 0)] UNSPECV_OSC_BREAK)] | |
11569 | "" | |
11570 | "bcr\t7,%%r0" | |
11571 | [(set_attr "op_type" "RR")]) |