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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
c161ecf7 | 2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. |
9db1d521 | 3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
f314b9b1 | 4 | ;; Ulrich Weigand (uweigand@de.ibm.com). |
9db1d521 | 5 | |
58add37a UW |
6 | ;; This file is part of GCC. |
7 | ||
8 | ;; GCC is free software; you can redistribute it and/or modify it under | |
9 | ;; the terms of the GNU General Public License as published by the Free | |
10 | ;; Software Foundation; either version 2, or (at your option) any later | |
11 | ;; version. | |
12 | ||
13 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
14 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
15 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
16 | ;; for more details. | |
9db1d521 HP |
17 | |
18 | ;; You should have received a copy of the GNU General Public License | |
58add37a UW |
19 | ;; along with GCC; see the file COPYING. If not, write to the Free |
20 | ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
21 | ;; 02111-1307, USA. | |
9db1d521 HP |
22 | |
23 | ;; | |
24 | ;; Special constraints for s/390 machine description: | |
25 | ;; | |
26 | ;; a -- Any address register from 1 to 15. | |
27 | ;; d -- Any register from 0 to 15. | |
28 | ;; I -- An 8-bit constant (0..255). | |
29 | ;; J -- A 12-bit constant (0..4095). | |
30 | ;; K -- A 16-bit constant (-32768..32767). | |
31 | ;; Q -- A memory reference without index-register. | |
32 | ;; S -- Valid operand for the LARL instruction. | |
33 | ;; | |
34 | ;; Special formats used for outputting 390 instructions. | |
35 | ;; | |
36 | ;; %b -- Print a constant byte integer. xy | |
37 | ;; %h -- Print a signed 16-bit. wxyz | |
38 | ;; %N -- Print next register (second word of a DImode reg) or next word. | |
39 | ;; %M -- Print next register (second word of a TImode reg) or next word. | |
40 | ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)). | |
41 | ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)). | |
42 | ;; | |
43 | ;; We have a special constraint for pattern matching. | |
44 | ;; | |
45 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
46 | ;; | |
9db1d521 | 47 | |
fd3cd001 UW |
48 | ;; |
49 | ;; UNSPEC usage | |
50 | ;; | |
51 | ||
52 | (define_constants | |
10bbf137 UW |
53 | [; Miscellaneous |
54 | (UNSPEC_ROUND 1) | |
55 | (UNSPEC_SETHIGH 10) | |
56 | ||
57 | ; GOT/PLT and lt-relative accesses | |
fd7643fb UW |
58 | (UNSPEC_LTREL_OFFSET 100) |
59 | (UNSPEC_LTREL_BASE 101) | |
60 | (UNSPEC_GOTENT 110) | |
61 | (UNSPEC_GOT 111) | |
62 | (UNSPEC_GOTOFF 112) | |
63 | (UNSPEC_PLT 113) | |
64 | (UNSPEC_PLTOFF 114) | |
65 | ||
66 | ; Literal pool | |
67 | (UNSPEC_RELOAD_BASE 210) | |
5af2f3d3 | 68 | (UNSPEC_MAIN_BASE 211) |
fd7643fb UW |
69 | |
70 | ; TLS relocation specifiers | |
fd3cd001 UW |
71 | (UNSPEC_TLSGD 500) |
72 | (UNSPEC_TLSLDM 501) | |
73 | (UNSPEC_NTPOFF 502) | |
74 | (UNSPEC_DTPOFF 503) | |
75 | (UNSPEC_GOTNTPOFF 504) | |
76 | (UNSPEC_INDNTPOFF 505) | |
77 | ||
78 | ; TLS support | |
79 | (UNSPEC_TP 510) | |
80 | (UNSPEC_TLSLDM_NTPOFF 511) | |
81 | (UNSPEC_TLS_LOAD 512) | |
82 | ]) | |
83 | ||
84 | ;; | |
85 | ;; UNSPEC_VOLATILE usage | |
86 | ;; | |
87 | ||
88 | (define_constants | |
10bbf137 UW |
89 | [; Blockage |
90 | (UNSPECV_BLOCKAGE 0) | |
91 | ||
92 | ; Literal pool | |
fd7643fb UW |
93 | (UNSPECV_POOL 200) |
94 | (UNSPECV_POOL_START 201) | |
95 | (UNSPECV_POOL_END 202) | |
416cf582 | 96 | (UNSPECV_POOL_ENTRY 203) |
fd7643fb UW |
97 | (UNSPECV_MAIN_POOL 300) |
98 | ||
99 | ; TLS support | |
fd3cd001 UW |
100 | (UNSPECV_SET_TP 500) |
101 | ]) | |
102 | ||
103 | ||
1fec52be HP |
104 | ;; Processor type. This attribute must exactly match the processor_type |
105 | ;; enumeration in s390.h. | |
106 | ||
f13e0d4e UW |
107 | (define_attr "cpu" "g5,g6,z900,z990" |
108 | (const (symbol_ref "s390_tune"))) | |
9db1d521 | 109 | |
f2d3c02a HP |
110 | ;; Define an insn type attribute. This is used in function unit delay |
111 | ;; computations. | |
9db1d521 | 112 | |
077dab3b HP |
113 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
114 | cs,vs,store,imul,idiv, | |
115 | branch,jsr,fsimpd,fsimps, | |
116 | floadd,floads,fstored, fstores, | |
117 | fmuld,fmuls,fdivd,fdivs, | |
118 | ftoi,itof,fsqrtd,fsqrts, | |
119 | other,o2,o3" | |
c7453384 | 120 | (const_string "integer")) |
9db1d521 | 121 | |
077dab3b | 122 | ;; Operand type. Used to default length attribute values |
9db1d521 | 123 | |
077dab3b | 124 | (define_attr "op_type" |
d3632d41 | 125 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY" |
077dab3b HP |
126 | (const_string "RX")) |
127 | ||
128 | ;; Insn are devide in two classes: | |
129 | ;; agen: Insn using agen | |
130 | ;; reg: Insn not using agen | |
131 | ||
132 | (define_attr "atype" "agen,reg" | |
133 | (cond [ (eq_attr "op_type" "E") (const_string "reg") | |
134 | (eq_attr "op_type" "RR") (const_string "reg") | |
135 | (eq_attr "op_type" "RX") (const_string "agen") | |
136 | (eq_attr "op_type" "RI") (const_string "reg") | |
137 | (eq_attr "op_type" "RRE") (const_string "reg") | |
138 | (eq_attr "op_type" "RS") (const_string "agen") | |
139 | (eq_attr "op_type" "RSI") (const_string "agen") | |
140 | (eq_attr "op_type" "S") (const_string "agen") | |
141 | (eq_attr "op_type" "SI") (const_string "agen") | |
142 | (eq_attr "op_type" "SS") (const_string "agen") | |
143 | (eq_attr "op_type" "SSE") (const_string "agen") | |
144 | (eq_attr "op_type" "RXE") (const_string "agen") | |
145 | (eq_attr "op_type" "RSE") (const_string "agen") | |
d3632d41 UW |
146 | (eq_attr "op_type" "RIL") (const_string "agen") |
147 | (eq_attr "op_type" "RXY") (const_string "agen") | |
148 | (eq_attr "op_type" "RSY") (const_string "agen") | |
149 | (eq_attr "op_type" "SIY") (const_string "agen")] | |
077dab3b | 150 | (const_string "reg"))) |
9db1d521 | 151 | |
c7453384 | 152 | ;; Generic pipeline function unit. |
9db1d521 | 153 | |
4023fb28 UW |
154 | (define_function_unit "integer" 1 0 |
155 | (eq_attr "type" "none") 0 0) | |
156 | ||
f2d3c02a HP |
157 | (define_function_unit "integer" 1 0 |
158 | (eq_attr "type" "integer") 1 1) | |
9db1d521 | 159 | |
077dab3b HP |
160 | (define_function_unit "integer" 1 0 |
161 | (eq_attr "type" "fsimpd") 1 1) | |
162 | ||
163 | (define_function_unit "integer" 1 0 | |
164 | (eq_attr "type" "fsimps") 1 1) | |
165 | ||
f2d3c02a HP |
166 | (define_function_unit "integer" 1 0 |
167 | (eq_attr "type" "load") 1 1) | |
9db1d521 | 168 | |
077dab3b HP |
169 | (define_function_unit "integer" 1 0 |
170 | (eq_attr "type" "floadd") 1 1) | |
171 | ||
172 | (define_function_unit "integer" 1 0 | |
173 | (eq_attr "type" "floads") 1 1) | |
174 | ||
f2d3c02a HP |
175 | (define_function_unit "integer" 1 0 |
176 | (eq_attr "type" "la") 1 1) | |
9db1d521 | 177 | |
077dab3b HP |
178 | (define_function_unit "integer" 1 0 |
179 | (eq_attr "type" "larl") 1 1) | |
180 | ||
f2d3c02a HP |
181 | (define_function_unit "integer" 1 0 |
182 | (eq_attr "type" "lr") 1 1) | |
9db1d521 | 183 | |
077dab3b HP |
184 | (define_function_unit "integer" 1 0 |
185 | (eq_attr "type" "branch") 1 1) | |
186 | ||
f2d3c02a HP |
187 | (define_function_unit "integer" 1 0 |
188 | (eq_attr "type" "store") 1 1) | |
9db1d521 | 189 | |
077dab3b HP |
190 | (define_function_unit "integer" 1 0 |
191 | (eq_attr "type" "fstored") 1 1) | |
192 | ||
193 | (define_function_unit "integer" 1 0 | |
194 | (eq_attr "type" "fstores") 1 1) | |
195 | ||
4023fb28 UW |
196 | (define_function_unit "integer" 1 0 |
197 | (eq_attr "type" "lm") 2 2) | |
198 | ||
199 | (define_function_unit "integer" 1 0 | |
200 | (eq_attr "type" "stm") 2 2) | |
201 | ||
202 | (define_function_unit "integer" 1 0 | |
203 | (eq_attr "type" "cs") 5 5) | |
204 | ||
205 | (define_function_unit "integer" 1 0 | |
206 | (eq_attr "type" "vs") 30 30) | |
207 | ||
f2d3c02a HP |
208 | (define_function_unit "integer" 1 0 |
209 | (eq_attr "type" "jsr") 5 5) | |
9db1d521 | 210 | |
f2d3c02a HP |
211 | (define_function_unit "integer" 1 0 |
212 | (eq_attr "type" "imul") 7 7) | |
213 | ||
214 | (define_function_unit "integer" 1 0 | |
077dab3b HP |
215 | (eq_attr "type" "fmuld") 6 6) |
216 | ||
217 | (define_function_unit "integer" 1 0 | |
218 | (eq_attr "type" "fmuls") 6 6) | |
9db1d521 | 219 | |
f2d3c02a HP |
220 | (define_function_unit "integer" 1 0 |
221 | (eq_attr "type" "idiv") 33 33) | |
9db1d521 | 222 | |
f2d3c02a | 223 | (define_function_unit "integer" 1 0 |
077dab3b HP |
224 | (eq_attr "type" "fdivd") 33 33) |
225 | ||
226 | (define_function_unit "integer" 1 0 | |
227 | (eq_attr "type" "fdivs") 33 33) | |
228 | ||
229 | (define_function_unit "integer" 1 0 | |
230 | (eq_attr "type" "fsqrtd") 30 30) | |
231 | ||
232 | (define_function_unit "integer" 1 0 | |
233 | (eq_attr "type" "fsqrts") 30 30) | |
234 | ||
235 | (define_function_unit "integer" 1 0 | |
236 | (eq_attr "type" "ftoi") 2 2) | |
237 | ||
238 | (define_function_unit "integer" 1 0 | |
239 | (eq_attr "type" "itof") 2 2) | |
9db1d521 | 240 | |
f2d3c02a HP |
241 | (define_function_unit "integer" 1 0 |
242 | (eq_attr "type" "o2") 2 2) | |
9db1d521 | 243 | |
f2d3c02a HP |
244 | (define_function_unit "integer" 1 0 |
245 | (eq_attr "type" "o3") 3 3) | |
9db1d521 | 246 | |
f2d3c02a HP |
247 | (define_function_unit "integer" 1 0 |
248 | (eq_attr "type" "other") 5 5) | |
249 | ||
077dab3b | 250 | ;; Pipeline description for z900 |
9db1d521 | 251 | |
077dab3b | 252 | (include "2064.md") |
52609473 | 253 | (include "2084.md") |
9db1d521 HP |
254 | |
255 | ;; Length in bytes. | |
256 | ||
257 | (define_attr "length" "" | |
258 | (cond [ (eq_attr "op_type" "E") (const_int 2) | |
259 | (eq_attr "op_type" "RR") (const_int 2) | |
260 | (eq_attr "op_type" "RX") (const_int 4) | |
261 | (eq_attr "op_type" "RI") (const_int 4) | |
262 | (eq_attr "op_type" "RRE") (const_int 4) | |
263 | (eq_attr "op_type" "RS") (const_int 4) | |
264 | (eq_attr "op_type" "RSI") (const_int 4) | |
9db1d521 HP |
265 | (eq_attr "op_type" "S") (const_int 4) |
266 | (eq_attr "op_type" "SI") (const_int 4) | |
267 | (eq_attr "op_type" "SS") (const_int 6) | |
268 | (eq_attr "op_type" "SSE") (const_int 6) | |
269 | (eq_attr "op_type" "RXE") (const_int 6) | |
270 | (eq_attr "op_type" "RSE") (const_int 6) | |
d3632d41 UW |
271 | (eq_attr "op_type" "RIL") (const_int 6) |
272 | (eq_attr "op_type" "RXY") (const_int 6) | |
273 | (eq_attr "op_type" "RSY") (const_int 6) | |
274 | (eq_attr "op_type" "SIY") (const_int 6)] | |
9db1d521 HP |
275 | (const_int 4))) |
276 | ||
277 | ;; Define attributes for `asm' insns. | |
278 | ||
f2d3c02a | 279 | (define_asm_attributes [(set_attr "type" "other") |
9db1d521 HP |
280 | (set_attr "op_type" "NN")]) |
281 | ||
282 | ;; | |
283 | ;; Condition Codes | |
284 | ;; | |
285 | ; | |
286 | ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR) | |
287 | ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA) | |
288 | ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM) | |
289 | ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM) | |
290 | ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML) | |
c7453384 | 291 | |
9db1d521 HP |
292 | ; CCZ -> CCL / CCZ1 |
293 | ; CCZ1 -> CCA/CCU/CCS/CCT | |
294 | ; CCS -> CCA | |
c7453384 | 295 | |
9db1d521 HP |
296 | ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST |
297 | ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT | |
298 | ||
299 | ||
300 | ;; | |
301 | ;;- Compare instructions. | |
302 | ;; | |
303 | ||
304 | (define_expand "cmpdi" | |
305 | [(set (reg:CC 33) | |
306 | (compare:CC (match_operand:DI 0 "register_operand" "") | |
307 | (match_operand:DI 1 "general_operand" "")))] | |
308 | "TARGET_64BIT" | |
9db1d521 HP |
309 | { |
310 | s390_compare_op0 = operands[0]; | |
311 | s390_compare_op1 = operands[1]; | |
312 | DONE; | |
10bbf137 | 313 | }) |
9db1d521 HP |
314 | |
315 | (define_expand "cmpsi" | |
316 | [(set (reg:CC 33) | |
317 | (compare:CC (match_operand:SI 0 "register_operand" "") | |
318 | (match_operand:SI 1 "general_operand" "")))] | |
319 | "" | |
9db1d521 HP |
320 | { |
321 | s390_compare_op0 = operands[0]; | |
322 | s390_compare_op1 = operands[1]; | |
323 | DONE; | |
10bbf137 | 324 | }) |
9db1d521 | 325 | |
9db1d521 HP |
326 | (define_expand "cmpdf" |
327 | [(set (reg:CC 33) | |
328 | (compare:CC (match_operand:DF 0 "register_operand" "") | |
329 | (match_operand:DF 1 "general_operand" "")))] | |
330 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
331 | { |
332 | s390_compare_op0 = operands[0]; | |
333 | s390_compare_op1 = operands[1]; | |
334 | DONE; | |
10bbf137 | 335 | }) |
9db1d521 HP |
336 | |
337 | (define_expand "cmpsf" | |
338 | [(set (reg:CC 33) | |
339 | (compare:CC (match_operand:SF 0 "register_operand" "") | |
340 | (match_operand:SF 1 "general_operand" "")))] | |
341 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
342 | { |
343 | s390_compare_op0 = operands[0]; | |
344 | s390_compare_op1 = operands[1]; | |
345 | DONE; | |
10bbf137 | 346 | }) |
9db1d521 HP |
347 | |
348 | ||
07893d4f | 349 | ; Test-under-Mask (zero_extract) instructions |
9db1d521 | 350 | |
07893d4f | 351 | (define_insn "*tmdi_ext" |
9db1d521 HP |
352 | [(set (reg 33) |
353 | (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d") | |
4023fb28 UW |
354 | (match_operand:DI 1 "const_int_operand" "n") |
355 | (match_operand:DI 2 "const_int_operand" "n")) | |
9db1d521 | 356 | (const_int 0)))] |
4023fb28 | 357 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT |
c7453384 | 358 | && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 |
4023fb28 UW |
359 | && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64 |
360 | && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4 | |
361 | == INTVAL (operands[2]) >> 4" | |
9db1d521 | 362 | { |
4023fb28 UW |
363 | int part = INTVAL (operands[2]) >> 4; |
364 | int block = (1 << INTVAL (operands[1])) - 1; | |
365 | int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15); | |
9db1d521 | 366 | |
4023fb28 | 367 | operands[2] = GEN_INT (block << shift); |
9db1d521 | 368 | |
4023fb28 UW |
369 | switch (part) |
370 | { | |
d40c829f UW |
371 | case 0: return "tmhh\t%0,%x2"; |
372 | case 1: return "tmhl\t%0,%x2"; | |
373 | case 2: return "tmlh\t%0,%x2"; | |
374 | case 3: return "tmll\t%0,%x2"; | |
4023fb28 UW |
375 | default: abort (); |
376 | } | |
10bbf137 | 377 | } |
4023fb28 UW |
378 | [(set_attr "op_type" "RI")]) |
379 | ||
07893d4f | 380 | (define_insn "*tmsi_ext" |
9db1d521 | 381 | [(set (reg 33) |
07893d4f UW |
382 | (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d") |
383 | (match_operand:SI 1 "const_int_operand" "n") | |
384 | (match_operand:SI 2 "const_int_operand" "n")) | |
9db1d521 | 385 | (const_int 0)))] |
07893d4f | 386 | "s390_match_ccmode(insn, CCTmode) |
c7453384 | 387 | && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 |
07893d4f UW |
388 | && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32 |
389 | && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4 | |
390 | == INTVAL (operands[2]) >> 4" | |
9db1d521 | 391 | { |
07893d4f UW |
392 | int part = INTVAL (operands[2]) >> 4; |
393 | int block = (1 << INTVAL (operands[1])) - 1; | |
394 | int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15); | |
395 | ||
396 | operands[2] = GEN_INT (block << shift); | |
9db1d521 | 397 | |
4023fb28 | 398 | switch (part) |
9db1d521 | 399 | { |
d40c829f UW |
400 | case 0: return "tmh\t%0,%x2"; |
401 | case 1: return "tml\t%0,%x2"; | |
4023fb28 | 402 | default: abort (); |
9db1d521 | 403 | } |
10bbf137 | 404 | } |
4023fb28 UW |
405 | [(set_attr "op_type" "RI")]) |
406 | ||
07893d4f | 407 | (define_insn "*tmqi_ext" |
4023fb28 | 408 | [(set (reg 33) |
d3632d41 UW |
409 | (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,S") |
410 | (match_operand:SI 1 "const_int_operand" "n,n") | |
411 | (match_operand:SI 2 "const_int_operand" "n,n")) | |
4023fb28 | 412 | (const_int 0)))] |
07893d4f | 413 | "s390_match_ccmode(insn, CCTmode) |
c7453384 | 414 | && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 |
07893d4f | 415 | && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8" |
4023fb28 | 416 | { |
07893d4f UW |
417 | int block = (1 << INTVAL (operands[1])) - 1; |
418 | int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]); | |
9db1d521 | 419 | |
07893d4f | 420 | operands[2] = GEN_INT (block << shift); |
d40c829f | 421 | return which_alternative == 0 ? "tm\t%0,%b2" : "tmy\t%0,%b2"; |
10bbf137 | 422 | } |
d3632d41 | 423 | [(set_attr "op_type" "SI,SIY")]) |
9db1d521 | 424 | |
07893d4f | 425 | ; Test-under-Mask instructions |
9db1d521 | 426 | |
07893d4f UW |
427 | (define_insn "*tmdi_mem" |
428 | [(set (reg 33) | |
d3632d41 UW |
429 | (compare (and:DI (match_operand:DI 0 "memory_operand" "Q,S") |
430 | (match_operand:DI 1 "immediate_operand" "n,n")) | |
431 | (match_operand:DI 2 "immediate_operand" "n,n")))] | |
9e8327e3 | 432 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) |
07893d4f | 433 | && s390_single_qi (operands[1], DImode, 0) >= 0" |
07893d4f UW |
434 | { |
435 | int part = s390_single_qi (operands[1], DImode, 0); | |
436 | operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part)); | |
437 | ||
c7453384 | 438 | operands[0] = gen_rtx_MEM (QImode, |
07893d4f | 439 | plus_constant (XEXP (operands[0], 0), part)); |
d40c829f | 440 | return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1"; |
10bbf137 | 441 | } |
d3632d41 | 442 | [(set_attr "op_type" "SI,SIY")]) |
07893d4f UW |
443 | |
444 | (define_insn "*tmsi_mem" | |
4023fb28 | 445 | [(set (reg 33) |
d3632d41 UW |
446 | (compare (and:SI (match_operand:SI 0 "memory_operand" "Q,S") |
447 | (match_operand:SI 1 "immediate_operand" "n,n")) | |
448 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
07893d4f | 449 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) |
4023fb28 | 450 | && s390_single_qi (operands[1], SImode, 0) >= 0" |
4023fb28 UW |
451 | { |
452 | int part = s390_single_qi (operands[1], SImode, 0); | |
453 | operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part)); | |
454 | ||
c7453384 | 455 | operands[0] = gen_rtx_MEM (QImode, |
4023fb28 | 456 | plus_constant (XEXP (operands[0], 0), part)); |
d40c829f | 457 | return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1"; |
10bbf137 | 458 | } |
077dab3b | 459 | [(set_attr "op_type" "SI")]) |
9db1d521 | 460 | |
07893d4f | 461 | (define_insn "*tmhi_mem" |
9db1d521 | 462 | [(set (reg 33) |
d3632d41 UW |
463 | (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q,S") 0) |
464 | (match_operand:SI 1 "immediate_operand" "n,n")) | |
465 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
07893d4f UW |
466 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) |
467 | && s390_single_qi (operands[1], HImode, 0) >= 0" | |
07893d4f UW |
468 | { |
469 | int part = s390_single_qi (operands[1], HImode, 0); | |
470 | operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part)); | |
9db1d521 | 471 | |
c7453384 | 472 | operands[0] = gen_rtx_MEM (QImode, |
07893d4f | 473 | plus_constant (XEXP (operands[0], 0), part)); |
d40c829f | 474 | return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1"; |
10bbf137 | 475 | } |
077dab3b | 476 | [(set_attr "op_type" "SI")]) |
9db1d521 | 477 | |
07893d4f | 478 | (define_insn "*tmqi_mem" |
9db1d521 | 479 | [(set (reg 33) |
d3632d41 UW |
480 | (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q,S") 0) |
481 | (match_operand:SI 1 "immediate_operand" "n,n")) | |
482 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
07893d4f | 483 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))" |
d3632d41 | 484 | "@ |
d40c829f UW |
485 | tm\t%0,%b1 |
486 | tmy\t%0,%b1" | |
d3632d41 | 487 | [(set_attr "op_type" "SI,SIY")]) |
9db1d521 | 488 | |
05b9aaaa UW |
489 | (define_insn "*tmdi_reg" |
490 | [(set (reg 33) | |
491 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d") | |
492 | (match_operand:DI 1 "immediate_operand" "n")) | |
493 | (match_operand:DI 2 "immediate_operand" "n")))] | |
494 | "TARGET_64BIT | |
495 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) | |
496 | && s390_single_hi (operands[1], DImode, 0) >= 0" | |
05b9aaaa UW |
497 | { |
498 | int part = s390_single_hi (operands[1], DImode, 0); | |
499 | operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part)); | |
500 | ||
501 | switch (part) | |
502 | { | |
d40c829f UW |
503 | case 0: return "tmhh\t%0,%x1"; |
504 | case 1: return "tmhl\t%0,%x1"; | |
505 | case 2: return "tmlh\t%0,%x1"; | |
506 | case 3: return "tmll\t%0,%x1"; | |
05b9aaaa UW |
507 | default: abort (); |
508 | } | |
10bbf137 | 509 | } |
05b9aaaa UW |
510 | [(set_attr "op_type" "RI")]) |
511 | ||
512 | (define_insn "*tmsi_reg" | |
513 | [(set (reg 33) | |
514 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d") | |
515 | (match_operand:SI 1 "immediate_operand" "n")) | |
516 | (match_operand:SI 2 "immediate_operand" "n")))] | |
517 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) | |
518 | && s390_single_hi (operands[1], SImode, 0) >= 0" | |
05b9aaaa UW |
519 | { |
520 | int part = s390_single_hi (operands[1], SImode, 0); | |
521 | operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part)); | |
522 | ||
523 | switch (part) | |
524 | { | |
d40c829f UW |
525 | case 0: return "tmh\t%0,%x1"; |
526 | case 1: return "tml\t%0,%x1"; | |
05b9aaaa UW |
527 | default: abort (); |
528 | } | |
10bbf137 | 529 | } |
05b9aaaa UW |
530 | [(set_attr "op_type" "RI")]) |
531 | ||
07893d4f | 532 | (define_insn "*tmhi_full" |
9db1d521 | 533 | [(set (reg 33) |
07893d4f UW |
534 | (compare (match_operand:HI 0 "register_operand" "d") |
535 | (match_operand:HI 1 "immediate_operand" "n")))] | |
536 | "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))" | |
d40c829f | 537 | "tml\t%0,65535" |
07893d4f | 538 | [(set_attr "op_type" "RX")]) |
9db1d521 | 539 | |
07893d4f | 540 | (define_insn "*tmqi_full" |
9db1d521 | 541 | [(set (reg 33) |
07893d4f UW |
542 | (compare (match_operand:QI 0 "register_operand" "d") |
543 | (match_operand:QI 1 "immediate_operand" "n")))] | |
544 | "s390_match_ccmode (insn, s390_tm_ccmode (GEN_INT (-1), operands[1], 1))" | |
d40c829f | 545 | "tml\t%0,255" |
07893d4f | 546 | [(set_attr "op_type" "RI")]) |
9db1d521 | 547 | |
07893d4f UW |
548 | |
549 | ; Load-and-Test instructions | |
550 | ||
551 | (define_insn "*tstdi_sign" | |
9db1d521 | 552 | [(set (reg 33) |
07893d4f UW |
553 | (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0) |
554 | (const_int 32)) (const_int 32)) | |
555 | (match_operand:DI 1 "const0_operand" ""))) | |
556 | (set (match_operand:DI 2 "register_operand" "=d") | |
557 | (sign_extend:DI (match_dup 0)))] | |
558 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 559 | "ltgfr\t%2,%0" |
07893d4f UW |
560 | [(set_attr "op_type" "RRE")]) |
561 | ||
562 | (define_insn "*tstdi" | |
9db1d521 | 563 | [(set (reg 33) |
07893d4f UW |
564 | (compare (match_operand:DI 0 "register_operand" "d") |
565 | (match_operand:DI 1 "const0_operand" ""))) | |
566 | (set (match_operand:DI 2 "register_operand" "=d") | |
567 | (match_dup 0))] | |
568 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 569 | "ltgr\t%2,%0" |
07893d4f | 570 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 571 | |
07893d4f | 572 | (define_insn "*tstdi_cconly" |
9db1d521 | 573 | [(set (reg 33) |
07893d4f UW |
574 | (compare (match_operand:DI 0 "register_operand" "d") |
575 | (match_operand:DI 1 "const0_operand" "")))] | |
576 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 577 | "ltgr\t%0,%0" |
07893d4f | 578 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 579 | |
07893d4f UW |
580 | (define_insn "*tstdi_cconly_31" |
581 | [(set (reg 33) | |
582 | (compare (match_operand:DI 0 "register_operand" "d") | |
583 | (match_operand:DI 1 "const0_operand" "")))] | |
584 | "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" | |
d40c829f | 585 | "srda\t%0,0" |
077dab3b HP |
586 | [(set_attr "op_type" "RS") |
587 | (set_attr "atype" "reg")]) | |
588 | ||
4023fb28 | 589 | |
07893d4f UW |
590 | (define_insn "*tstsi" |
591 | [(set (reg 33) | |
d3632d41 | 592 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 593 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 594 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f UW |
595 | (match_dup 0))] |
596 | "s390_match_ccmode(insn, CCSmode)" | |
597 | "@ | |
d40c829f UW |
598 | ltr\t%2,%0 |
599 | icm\t%2,15,%0 | |
600 | icmy\t%2,15,%0" | |
d3632d41 | 601 | [(set_attr "op_type" "RR,RS,RSY")]) |
9db1d521 | 602 | |
07893d4f | 603 | (define_insn "*tstsi_cconly" |
4023fb28 | 604 | [(set (reg 33) |
d3632d41 | 605 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 606 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 607 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
608 | "s390_match_ccmode(insn, CCSmode)" |
609 | "@ | |
d40c829f UW |
610 | ltr\t%0,%0 |
611 | icm\t%2,15,%0 | |
612 | icmy\t%2,15,%0" | |
d3632d41 | 613 | [(set_attr "op_type" "RR,RS,RSY")]) |
4023fb28 | 614 | |
07893d4f UW |
615 | (define_insn "*tstsi_cconly2" |
616 | [(set (reg 33) | |
617 | (compare (match_operand:SI 0 "register_operand" "d") | |
618 | (match_operand:SI 1 "const0_operand" "")))] | |
619 | "s390_match_ccmode(insn, CCSmode)" | |
d40c829f | 620 | "ltr\t%0,%0" |
07893d4f | 621 | [(set_attr "op_type" "RR")]) |
4023fb28 | 622 | |
3af97654 UW |
623 | (define_insn "*tsthiCCT" |
624 | [(set (reg 33) | |
d3632d41 | 625 | (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 | 626 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 627 | (set (match_operand:HI 2 "register_operand" "=d,d,0") |
3af97654 UW |
628 | (match_dup 0))] |
629 | "s390_match_ccmode(insn, CCTmode)" | |
630 | "@ | |
d40c829f UW |
631 | icm\t%2,3,%0 |
632 | icmy\t%2,3,%0 | |
633 | tml\t%0,65535" | |
d3632d41 | 634 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 UW |
635 | |
636 | (define_insn "*tsthiCCT_cconly" | |
637 | [(set (reg 33) | |
d3632d41 | 638 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 639 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 640 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
641 | "s390_match_ccmode(insn, CCTmode)" |
642 | "@ | |
d40c829f UW |
643 | icm\t%2,3,%0 |
644 | icmy\t%2,3,%0 | |
645 | tml\t%0,65535" | |
d3632d41 | 646 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 | 647 | |
07893d4f | 648 | (define_insn "*tsthi" |
9db1d521 | 649 | [(set (reg 33) |
d3632d41 | 650 | (compare (match_operand:HI 0 "s_operand" "Q,S") |
9db1d521 | 651 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 652 | (set (match_operand:HI 2 "register_operand" "=d,d") |
9db1d521 HP |
653 | (match_dup 0))] |
654 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 655 | "@ |
d40c829f UW |
656 | icm\t%2,3,%0 |
657 | icmy\t%2,3,%0" | |
d3632d41 | 658 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 659 | |
07893d4f | 660 | (define_insn "*tsthi_cconly" |
9db1d521 | 661 | [(set (reg 33) |
d3632d41 | 662 | (compare (match_operand:HI 0 "s_operand" "Q,S") |
9db1d521 | 663 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 664 | (clobber (match_scratch:HI 2 "=d,d"))] |
9db1d521 | 665 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 666 | "@ |
d40c829f UW |
667 | icm\t%2,3,%0 |
668 | icmy\t%2,3,%0" | |
d3632d41 | 669 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 670 | |
3af97654 UW |
671 | (define_insn "*tstqiCCT" |
672 | [(set (reg 33) | |
d3632d41 | 673 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 | 674 | (match_operand:QI 1 "const0_operand" ""))) |
d3632d41 | 675 | (set (match_operand:QI 2 "register_operand" "=d,d,0") |
3af97654 UW |
676 | (match_dup 0))] |
677 | "s390_match_ccmode(insn, CCTmode)" | |
678 | "@ | |
d40c829f UW |
679 | icm\t%2,1,%0 |
680 | icmy\t%2,1,%0 | |
681 | tml\t%0,255" | |
d3632d41 | 682 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 UW |
683 | |
684 | (define_insn "*tstqiCCT_cconly" | |
685 | [(set (reg 33) | |
d3632d41 | 686 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
687 | (match_operand:QI 1 "const0_operand" "")))] |
688 | "s390_match_ccmode(insn, CCTmode)" | |
689 | "@ | |
d40c829f UW |
690 | cli\t%0,0 |
691 | cliy\t%0,0 | |
692 | tml\t%0,255" | |
d3632d41 | 693 | [(set_attr "op_type" "SI,SIY,RI")]) |
3af97654 | 694 | |
07893d4f | 695 | (define_insn "*tstqi" |
9db1d521 | 696 | [(set (reg 33) |
d3632d41 | 697 | (compare (match_operand:QI 0 "s_operand" "Q,S") |
07893d4f | 698 | (match_operand:QI 1 "const0_operand" ""))) |
d3632d41 | 699 | (set (match_operand:QI 2 "register_operand" "=d,d") |
07893d4f UW |
700 | (match_dup 0))] |
701 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 702 | "@ |
d40c829f UW |
703 | icm\t%2,1,%0 |
704 | icmy\t%2,1,%0" | |
d3632d41 | 705 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 706 | |
07893d4f | 707 | (define_insn "*tstqi_cconly" |
9db1d521 | 708 | [(set (reg 33) |
d3632d41 | 709 | (compare (match_operand:QI 0 "s_operand" "Q,S") |
07893d4f | 710 | (match_operand:QI 1 "const0_operand" ""))) |
d3632d41 | 711 | (clobber (match_scratch:QI 2 "=d,d"))] |
07893d4f | 712 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 713 | "@ |
d40c829f UW |
714 | icm\t%2,1,%0 |
715 | icmy\t%2,1,%0" | |
d3632d41 UW |
716 | [(set_attr "op_type" "RS,RSY")]) |
717 | ||
9db1d521 | 718 | |
07893d4f | 719 | ; Compare (signed) instructions |
4023fb28 | 720 | |
07893d4f | 721 | (define_insn "*cmpdi_ccs_sign" |
4023fb28 | 722 | [(set (reg 33) |
07893d4f UW |
723 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
724 | (match_operand:DI 0 "register_operand" "d,d")))] | |
725 | "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" | |
4023fb28 | 726 | "@ |
d40c829f UW |
727 | cgfr\t%0,%1 |
728 | cgf\t%0,%1" | |
d3632d41 | 729 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 730 | |
07893d4f | 731 | (define_insn "*cmpdi_ccs" |
4023fb28 | 732 | [(set (reg 33) |
07893d4f UW |
733 | (compare (match_operand:DI 0 "register_operand" "d,d,d") |
734 | (match_operand:DI 1 "general_operand" "d,K,m")))] | |
735 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
736 | "@ | |
d40c829f UW |
737 | cgr\t%0,%1 |
738 | cghi\t%0,%c1 | |
739 | cg\t%0,%1" | |
d3632d41 | 740 | [(set_attr "op_type" "RRE,RI,RXY")]) |
c7453384 | 741 | |
07893d4f UW |
742 | (define_insn "*cmpsi_ccs_sign" |
743 | [(set (reg 33) | |
d3632d41 UW |
744 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")) |
745 | (match_operand:SI 0 "register_operand" "d,d")))] | |
07893d4f | 746 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 747 | "@ |
d40c829f UW |
748 | ch\t%0,%1 |
749 | chy\t%0,%1" | |
d3632d41 | 750 | [(set_attr "op_type" "RX,RXY")]) |
4023fb28 | 751 | |
07893d4f | 752 | (define_insn "*cmpsi_ccs" |
9db1d521 | 753 | [(set (reg 33) |
d3632d41 UW |
754 | (compare (match_operand:SI 0 "register_operand" "d,d,d,d") |
755 | (match_operand:SI 1 "general_operand" "d,K,R,T")))] | |
9db1d521 | 756 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 757 | "@ |
d40c829f UW |
758 | cr\t%0,%1 |
759 | chi\t%0,%c1 | |
760 | c\t%0,%1 | |
761 | cy\t%0,%1" | |
d3632d41 | 762 | [(set_attr "op_type" "RR,RI,RX,RXY")]) |
c7453384 | 763 | |
07893d4f UW |
764 | |
765 | ; Compare (unsigned) instructions | |
9db1d521 | 766 | |
07893d4f | 767 | (define_insn "*cmpdi_ccu_zero" |
9db1d521 | 768 | [(set (reg 33) |
07893d4f UW |
769 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
770 | (match_operand:DI 0 "register_operand" "d,d")))] | |
771 | "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT" | |
772 | "@ | |
d40c829f UW |
773 | clgfr\t%0,%1 |
774 | clgf\t%0,%1" | |
d3632d41 | 775 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 776 | |
07893d4f | 777 | (define_insn "*cmpdi_ccu" |
9db1d521 | 778 | [(set (reg 33) |
07893d4f UW |
779 | (compare (match_operand:DI 0 "register_operand" "d,d") |
780 | (match_operand:DI 1 "general_operand" "d,m")))] | |
781 | "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT" | |
782 | "@ | |
d40c829f UW |
783 | clgr\t%0,%1 |
784 | clg\t%0,%1" | |
d3632d41 | 785 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 786 | |
07893d4f | 787 | (define_insn "*cmpsi_ccu" |
9db1d521 | 788 | [(set (reg 33) |
d3632d41 UW |
789 | (compare (match_operand:SI 0 "register_operand" "d,d,d") |
790 | (match_operand:SI 1 "general_operand" "d,R,T")))] | |
07893d4f UW |
791 | "s390_match_ccmode(insn, CCUmode)" |
792 | "@ | |
d40c829f UW |
793 | clr\t%0,%1 |
794 | cl\t%0,%1 | |
795 | cly\t%0,%1" | |
d3632d41 | 796 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 797 | |
07893d4f | 798 | (define_insn "*cmphi_ccu" |
9db1d521 | 799 | [(set (reg 33) |
d3632d41 UW |
800 | (compare (match_operand:HI 0 "register_operand" "d,d") |
801 | (match_operand:HI 1 "s_imm_operand" "Q,S")))] | |
9db1d521 | 802 | "s390_match_ccmode(insn, CCUmode)" |
d3632d41 | 803 | "@ |
d40c829f UW |
804 | clm\t%0,3,%1 |
805 | clmy\t%0,3,%1" | |
d3632d41 | 806 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 HP |
807 | |
808 | (define_insn "*cmpqi_ccu" | |
809 | [(set (reg 33) | |
d3632d41 UW |
810 | (compare (match_operand:QI 0 "register_operand" "d,d") |
811 | (match_operand:QI 1 "s_imm_operand" "Q,S")))] | |
9db1d521 | 812 | "s390_match_ccmode(insn, CCUmode)" |
d3632d41 | 813 | "@ |
d40c829f UW |
814 | clm\t%0,1,%1 |
815 | clmy\t%0,1,%1" | |
d3632d41 | 816 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 817 | |
07893d4f | 818 | (define_insn "*cli" |
9db1d521 | 819 | [(set (reg 33) |
d3632d41 UW |
820 | (compare (match_operand:QI 0 "memory_operand" "Q,S") |
821 | (match_operand:QI 1 "immediate_operand" "n,n")))] | |
07893d4f | 822 | "s390_match_ccmode (insn, CCUmode)" |
d3632d41 | 823 | "@ |
d40c829f UW |
824 | cli\t%0,%b1 |
825 | cliy\t%0,%b1" | |
d3632d41 | 826 | [(set_attr "op_type" "SI,SIY")]) |
9db1d521 | 827 | |
07893d4f UW |
828 | (define_insn "*cmpdi_ccu_mem" |
829 | [(set (reg 33) | |
ccfc6cc8 UW |
830 | (compare (match_operand:DI 0 "s_operand" "Q") |
831 | (match_operand:DI 1 "s_imm_operand" "Q")))] | |
07893d4f | 832 | "s390_match_ccmode(insn, CCUmode)" |
d40c829f | 833 | "clc\t%O0(8,%R0),%1" |
077dab3b | 834 | [(set_attr "op_type" "SS")]) |
07893d4f UW |
835 | |
836 | (define_insn "*cmpsi_ccu_mem" | |
837 | [(set (reg 33) | |
ccfc6cc8 UW |
838 | (compare (match_operand:SI 0 "s_operand" "Q") |
839 | (match_operand:SI 1 "s_imm_operand" "Q")))] | |
07893d4f | 840 | "s390_match_ccmode(insn, CCUmode)" |
d40c829f | 841 | "clc\t%O0(4,%R0),%1" |
077dab3b | 842 | [(set_attr "op_type" "SS")]) |
07893d4f UW |
843 | |
844 | (define_insn "*cmphi_ccu_mem" | |
845 | [(set (reg 33) | |
ccfc6cc8 UW |
846 | (compare (match_operand:HI 0 "s_operand" "Q") |
847 | (match_operand:HI 1 "s_imm_operand" "Q")))] | |
07893d4f | 848 | "s390_match_ccmode(insn, CCUmode)" |
d40c829f | 849 | "clc\t%O0(2,%R0),%1" |
077dab3b | 850 | [(set_attr "op_type" "SS")]) |
07893d4f | 851 | |
9db1d521 HP |
852 | (define_insn "*cmpqi_ccu_mem" |
853 | [(set (reg 33) | |
ccfc6cc8 UW |
854 | (compare (match_operand:QI 0 "s_operand" "Q") |
855 | (match_operand:QI 1 "s_imm_operand" "Q")))] | |
9db1d521 | 856 | "s390_match_ccmode(insn, CCUmode)" |
d40c829f | 857 | "clc\t%O0(1,%R0),%1" |
077dab3b | 858 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
859 | |
860 | ||
861 | ; DF instructions | |
862 | ||
863 | (define_insn "*cmpdf_ccs_0" | |
864 | [(set (reg 33) | |
865 | (compare (match_operand:DF 0 "register_operand" "f") | |
866 | (match_operand:DF 1 "const0_operand" "")))] | |
867 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 868 | "ltdbr\t%0,%0" |
077dab3b HP |
869 | [(set_attr "op_type" "RRE") |
870 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
871 | |
872 | (define_insn "*cmpdf_ccs_0_ibm" | |
873 | [(set (reg 33) | |
874 | (compare (match_operand:DF 0 "register_operand" "f") | |
875 | (match_operand:DF 1 "const0_operand" "")))] | |
876 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 877 | "ltdr\t%0,%0" |
077dab3b HP |
878 | [(set_attr "op_type" "RR") |
879 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
880 | |
881 | (define_insn "*cmpdf_ccs" | |
882 | [(set (reg 33) | |
883 | (compare (match_operand:DF 0 "register_operand" "f,f") | |
d3632d41 | 884 | (match_operand:DF 1 "general_operand" "f,R")))] |
9db1d521 HP |
885 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
886 | "@ | |
d40c829f UW |
887 | cdbr\t%0,%1 |
888 | cdb\t%0,%1" | |
ce50cae8 | 889 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 890 | (set_attr "type" "fsimpd")]) |
9db1d521 HP |
891 | |
892 | (define_insn "*cmpdf_ccs_ibm" | |
893 | [(set (reg 33) | |
894 | (compare (match_operand:DF 0 "register_operand" "f,f") | |
d3632d41 | 895 | (match_operand:DF 1 "general_operand" "f,R")))] |
9db1d521 HP |
896 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
897 | "@ | |
d40c829f UW |
898 | cdr\t%0,%1 |
899 | cd\t%0,%1" | |
9db1d521 | 900 | [(set_attr "op_type" "RR,RX") |
077dab3b | 901 | (set_attr "type" "fsimpd")]) |
9db1d521 HP |
902 | |
903 | ||
904 | ; SF instructions | |
905 | ||
906 | (define_insn "*cmpsf_ccs_0" | |
907 | [(set (reg 33) | |
908 | (compare (match_operand:SF 0 "register_operand" "f") | |
909 | (match_operand:SF 1 "const0_operand" "")))] | |
910 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 911 | "ltebr\t%0,%0" |
077dab3b HP |
912 | [(set_attr "op_type" "RRE") |
913 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
914 | |
915 | (define_insn "*cmpsf_ccs_0_ibm" | |
916 | [(set (reg 33) | |
917 | (compare (match_operand:SF 0 "register_operand" "f") | |
918 | (match_operand:SF 1 "const0_operand" "")))] | |
919 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 920 | "lter\t%0,%0" |
077dab3b HP |
921 | [(set_attr "op_type" "RR") |
922 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
923 | |
924 | (define_insn "*cmpsf_ccs" | |
925 | [(set (reg 33) | |
926 | (compare (match_operand:SF 0 "register_operand" "f,f") | |
d3632d41 | 927 | (match_operand:SF 1 "general_operand" "f,R")))] |
9db1d521 HP |
928 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
929 | "@ | |
d40c829f UW |
930 | cebr\t%0,%1 |
931 | ceb\t%0,%1" | |
077dab3b HP |
932 | [(set_attr "op_type" "RRE,RXE") |
933 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
934 | |
935 | (define_insn "*cmpsf_ccs" | |
936 | [(set (reg 33) | |
937 | (compare (match_operand:SF 0 "register_operand" "f,f") | |
d3632d41 | 938 | (match_operand:SF 1 "general_operand" "f,R")))] |
9db1d521 HP |
939 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
940 | "@ | |
d40c829f UW |
941 | cer\t%0,%1 |
942 | ce\t%0,%1" | |
077dab3b HP |
943 | [(set_attr "op_type" "RR,RX") |
944 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
945 | |
946 | ||
947 | ;; | |
948 | ;;- Move instructions. | |
949 | ;; | |
950 | ||
951 | ; | |
952 | ; movti instruction pattern(s). | |
953 | ; | |
954 | ||
955 | (define_insn "movti" | |
d3632d41 UW |
956 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q") |
957 | (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))] | |
9db1d521 | 958 | "TARGET_64BIT" |
4023fb28 | 959 | "@ |
d40c829f UW |
960 | lmg\t%0,%N0,%1 |
961 | stmg\t%1,%N1,%0 | |
4023fb28 | 962 | # |
9b7c75b9 | 963 | # |
d40c829f | 964 | mvc\t%O0(16,%R0),%1" |
d3632d41 | 965 | [(set_attr "op_type" "RSY,RSY,NN,NN,SS") |
fe03d631 | 966 | (set_attr "type" "lm,stm,*,*,cs")]) |
4023fb28 UW |
967 | |
968 | (define_split | |
969 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
970 | (match_operand:TI 1 "general_operand" ""))] | |
971 | "TARGET_64BIT && reload_completed | |
dc65c307 | 972 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
973 | [(set (match_dup 2) (match_dup 4)) |
974 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 975 | { |
dc65c307 UW |
976 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
977 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
978 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
979 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
980 | }) | |
981 | ||
982 | (define_split | |
983 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
984 | (match_operand:TI 1 "general_operand" ""))] | |
985 | "TARGET_64BIT && reload_completed | |
986 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" | |
987 | [(set (match_dup 2) (match_dup 4)) | |
988 | (set (match_dup 3) (match_dup 5))] | |
989 | { | |
990 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
991 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
992 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
993 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
994 | }) | |
4023fb28 UW |
995 | |
996 | (define_split | |
997 | [(set (match_operand:TI 0 "register_operand" "") | |
998 | (match_operand:TI 1 "memory_operand" ""))] | |
999 | "TARGET_64BIT && reload_completed | |
1000 | && !s_operand (operands[1], VOIDmode)" | |
a41c6c53 | 1001 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1002 | { |
1003 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
1004 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1005 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1006 | }) |
1007 | ||
1008 | (define_expand "reload_outti" | |
1009 | [(parallel [(match_operand:TI 0 "memory_operand" "") | |
1010 | (match_operand:TI 1 "register_operand" "d") | |
1011 | (match_operand:DI 2 "register_operand" "=&a")])] | |
1012 | "TARGET_64BIT" | |
1013 | { | |
1014 | s390_load_address (operands[2], XEXP (operands[0], 0)); | |
1015 | operands[0] = replace_equiv_address (operands[0], operands[2]); | |
1016 | emit_move_insn (operands[0], operands[1]); | |
1017 | DONE; | |
1018 | }) | |
9db1d521 HP |
1019 | |
1020 | ; | |
1021 | ; movdi instruction pattern(s). | |
1022 | ; | |
1023 | ||
9db1d521 HP |
1024 | (define_expand "movdi" |
1025 | [(set (match_operand:DI 0 "general_operand" "") | |
1026 | (match_operand:DI 1 "general_operand" ""))] | |
1027 | "" | |
9db1d521 | 1028 | { |
fd3cd001 UW |
1029 | /* Handle symbolic constants. */ |
1030 | if (TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
1031 | emit_symbolic_move (operands); | |
4023fb28 UW |
1032 | |
1033 | /* During and after reload, we need to force constants | |
1034 | to the literal pool ourselves, if necessary. */ | |
1035 | if ((reload_in_progress || reload_completed) | |
c7453384 | 1036 | && CONSTANT_P (operands[1]) |
4023fb28 | 1037 | && (!legitimate_reload_constant_p (operands[1]) |
8e509cf9 | 1038 | || FP_REG_P (operands[0]))) |
4023fb28 | 1039 | operands[1] = force_const_mem (DImode, operands[1]); |
10bbf137 | 1040 | }) |
9db1d521 | 1041 | |
4023fb28 UW |
1042 | (define_insn "*movdi_lhi" |
1043 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1044 | (match_operand:DI 1 "immediate_operand" "K"))] | |
1045 | "TARGET_64BIT | |
1046 | && GET_CODE (operands[1]) == CONST_INT | |
1047 | && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K') | |
8e509cf9 | 1048 | && !FP_REG_P (operands[0])" |
d40c829f | 1049 | "lghi\t%0,%h1" |
077dab3b | 1050 | [(set_attr "op_type" "RI")]) |
4023fb28 UW |
1051 | |
1052 | (define_insn "*movdi_lli" | |
1053 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1054 | (match_operand:DI 1 "immediate_operand" "n"))] | |
1055 | "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0 | |
8e509cf9 | 1056 | && !FP_REG_P (operands[0])" |
4023fb28 UW |
1057 | { |
1058 | int part = s390_single_hi (operands[1], DImode, 0); | |
1059 | operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part)); | |
1060 | ||
1061 | switch (part) | |
1062 | { | |
d40c829f UW |
1063 | case 0: return "llihh\t%0,%x1"; |
1064 | case 1: return "llihl\t%0,%x1"; | |
1065 | case 2: return "llilh\t%0,%x1"; | |
1066 | case 3: return "llill\t%0,%x1"; | |
4023fb28 UW |
1067 | default: abort (); |
1068 | } | |
10bbf137 | 1069 | } |
077dab3b | 1070 | [(set_attr "op_type" "RI")]) |
4023fb28 | 1071 | |
d3632d41 UW |
1072 | (define_insn "*movdi_lay" |
1073 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1074 | (match_operand:DI 1 "address_operand" "p"))] | |
c7453384 | 1075 | "TARGET_64BIT |
d3632d41 UW |
1076 | && TARGET_LONG_DISPLACEMENT |
1077 | && GET_CODE (operands[1]) == CONST_INT | |
1078 | && !FP_REG_P (operands[0])" | |
d40c829f | 1079 | "lay\t%0,%a1" |
d3632d41 UW |
1080 | [(set_attr "op_type" "RXY") |
1081 | (set_attr "type" "la")]) | |
1082 | ||
4023fb28 UW |
1083 | (define_insn "*movdi_larl" |
1084 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1085 | (match_operand:DI 1 "larl_operand" "X"))] | |
1086 | "TARGET_64BIT | |
8e509cf9 | 1087 | && !FP_REG_P (operands[0])" |
d40c829f | 1088 | "larl\t%0,%1" |
4023fb28 | 1089 | [(set_attr "op_type" "RIL") |
077dab3b | 1090 | (set_attr "type" "larl")]) |
4023fb28 | 1091 | |
9db1d521 | 1092 | (define_insn "*movdi_64" |
d3632d41 UW |
1093 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,!*f,!*f,!*f,!R,!T,?Q") |
1094 | (match_operand:DI 1 "general_operand" "d,m,d,*f,R,T,*f,*f,?Q"))] | |
9db1d521 HP |
1095 | "TARGET_64BIT" |
1096 | "@ | |
d40c829f UW |
1097 | lgr\t%0,%1 |
1098 | lg\t%0,%1 | |
1099 | stg\t%1,%0 | |
1100 | ldr\t%0,%1 | |
1101 | ld\t%0,%1 | |
1102 | ldy\t%0,%1 | |
1103 | std\t%1,%0 | |
1104 | stdy\t%1,%0 | |
1105 | mvc\t%O0(8,%R0),%1" | |
d3632d41 UW |
1106 | [(set_attr "op_type" "RRE,RXY,RXY,RR,RX,RXY,RX,RXY,SS") |
1107 | (set_attr "type" "lr,load,store,floadd,floadd,floadd,fstored,fstored,cs")]) | |
9db1d521 HP |
1108 | |
1109 | (define_insn "*movdi_31" | |
d3632d41 UW |
1110 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q") |
1111 | (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))] | |
9db1d521 | 1112 | "!TARGET_64BIT" |
4023fb28 | 1113 | "@ |
d40c829f UW |
1114 | lm\t%0,%N0,%1 |
1115 | stm\t%1,%N1,%0 | |
4023fb28 UW |
1116 | # |
1117 | # | |
d40c829f UW |
1118 | ldr\t%0,%1 |
1119 | ld\t%0,%1 | |
1120 | ldy\t%0,%1 | |
1121 | std\t%1,%0 | |
1122 | stdy\t%1,%0 | |
1123 | mvc\t%O0(8,%R0),%1" | |
d3632d41 UW |
1124 | [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RXY,RX,RXY,SS") |
1125 | (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,cs")]) | |
4023fb28 UW |
1126 | |
1127 | (define_split | |
1128 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1129 | (match_operand:DI 1 "general_operand" ""))] | |
1130 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 1131 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1132 | [(set (match_dup 2) (match_dup 4)) |
1133 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1134 | { |
dc65c307 UW |
1135 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1136 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1137 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1138 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1139 | }) | |
1140 | ||
1141 | (define_split | |
1142 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1143 | (match_operand:DI 1 "general_operand" ""))] | |
1144 | "!TARGET_64BIT && reload_completed | |
1145 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" | |
1146 | [(set (match_dup 2) (match_dup 4)) | |
1147 | (set (match_dup 3) (match_dup 5))] | |
1148 | { | |
1149 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1150 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1151 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1152 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1153 | }) | |
9db1d521 | 1154 | |
4023fb28 UW |
1155 | (define_split |
1156 | [(set (match_operand:DI 0 "register_operand" "") | |
1157 | (match_operand:DI 1 "memory_operand" ""))] | |
1158 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 1159 | && !FP_REG_P (operands[0]) |
4023fb28 | 1160 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1161 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1162 | { |
1163 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1164 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1165 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1166 | }) |
1167 | ||
1168 | (define_expand "reload_outdi" | |
1169 | [(parallel [(match_operand:DI 0 "memory_operand" "") | |
1170 | (match_operand:DI 1 "register_operand" "d") | |
1171 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1172 | "!TARGET_64BIT" | |
1173 | { | |
1174 | s390_load_address (operands[2], XEXP (operands[0], 0)); | |
1175 | operands[0] = replace_equiv_address (operands[0], operands[2]); | |
1176 | emit_move_insn (operands[0], operands[1]); | |
1177 | DONE; | |
1178 | }) | |
9db1d521 | 1179 | |
84817c5d UW |
1180 | (define_peephole2 |
1181 | [(set (match_operand:DI 0 "register_operand" "") | |
1182 | (mem:DI (match_operand 1 "address_operand" "")))] | |
1183 | "TARGET_64BIT | |
1184 | && !FP_REG_P (operands[0]) | |
1185 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1186 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1187 | && get_pool_mode (operands[1]) == DImode | |
1188 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1189 | [(set (match_dup 0) (match_dup 2))] | |
1190 | "operands[2] = get_pool_constant (operands[1]);") | |
1191 | ||
9db1d521 HP |
1192 | ; |
1193 | ; movsi instruction pattern(s). | |
1194 | ; | |
1195 | ||
9db1d521 HP |
1196 | (define_expand "movsi" |
1197 | [(set (match_operand:SI 0 "general_operand" "") | |
1198 | (match_operand:SI 1 "general_operand" ""))] | |
1199 | "" | |
9db1d521 | 1200 | { |
fd3cd001 UW |
1201 | /* Handle symbolic constants. */ |
1202 | if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
1203 | emit_symbolic_move (operands); | |
ba956982 | 1204 | |
c7453384 EC |
1205 | /* expr.c tries to load an effective address using |
1206 | force_reg. This fails because we don't have a | |
ba956982 UW |
1207 | generic load_address pattern. Convert the move |
1208 | to a proper arithmetic operation instead, unless | |
1209 | it is guaranteed to be OK. */ | |
1210 | if (GET_CODE (operands[1]) == PLUS | |
1211 | && !legitimate_la_operand_p (operands[1])) | |
1212 | { | |
1213 | operands[1] = force_operand (operands[1], operands[0]); | |
1214 | if (operands[1] == operands[0]) | |
1215 | DONE; | |
1216 | } | |
4023fb28 UW |
1217 | |
1218 | /* During and after reload, we need to force constants | |
1219 | to the literal pool ourselves, if necessary. */ | |
1220 | if ((reload_in_progress || reload_completed) | |
c7453384 | 1221 | && CONSTANT_P (operands[1]) |
4023fb28 | 1222 | && (!legitimate_reload_constant_p (operands[1]) |
8e509cf9 | 1223 | || FP_REG_P (operands[0]))) |
4023fb28 | 1224 | operands[1] = force_const_mem (SImode, operands[1]); |
10bbf137 | 1225 | }) |
9db1d521 | 1226 | |
4023fb28 UW |
1227 | (define_insn "*movsi_lhi" |
1228 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1229 | (match_operand:SI 1 "immediate_operand" "K"))] | |
1230 | "GET_CODE (operands[1]) == CONST_INT | |
1231 | && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K') | |
8e509cf9 | 1232 | && !FP_REG_P (operands[0])" |
d40c829f | 1233 | "lhi\t%0,%h1" |
4023fb28 UW |
1234 | [(set_attr "op_type" "RI")]) |
1235 | ||
1236 | (define_insn "*movsi_lli" | |
1237 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1238 | (match_operand:SI 1 "immediate_operand" "n"))] | |
9e8327e3 | 1239 | "TARGET_ZARCH && s390_single_hi (operands[1], SImode, 0) >= 0 |
8e509cf9 | 1240 | && !FP_REG_P (operands[0])" |
4023fb28 UW |
1241 | { |
1242 | int part = s390_single_hi (operands[1], SImode, 0); | |
1243 | operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part)); | |
1244 | ||
1245 | switch (part) | |
1246 | { | |
d40c829f UW |
1247 | case 0: return "llilh\t%0,%x1"; |
1248 | case 1: return "llill\t%0,%x1"; | |
4023fb28 UW |
1249 | default: abort (); |
1250 | } | |
10bbf137 | 1251 | } |
4023fb28 UW |
1252 | [(set_attr "op_type" "RI")]) |
1253 | ||
d3632d41 UW |
1254 | (define_insn "*movsi_lay" |
1255 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1256 | (match_operand:SI 1 "address_operand" "p"))] | |
1257 | "TARGET_LONG_DISPLACEMENT | |
1258 | && GET_CODE (operands[1]) == CONST_INT | |
1259 | && !FP_REG_P (operands[0])" | |
d40c829f | 1260 | "lay\t%0,%a1" |
d3632d41 UW |
1261 | [(set_attr "op_type" "RXY") |
1262 | (set_attr "type" "la")]) | |
1263 | ||
9e8327e3 UW |
1264 | (define_insn "*movsi_larl" |
1265 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1266 | (match_operand:SI 1 "larl_operand" "X"))] | |
1267 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1268 | && !FP_REG_P (operands[0])" | |
1269 | "larl\t%0,%1" | |
1270 | [(set_attr "op_type" "RIL") | |
1271 | (set_attr "type" "larl")]) | |
1272 | ||
9db1d521 | 1273 | (define_insn "*movsi" |
d3632d41 UW |
1274 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,T,!*f,!*f,!*f,!R,!T,?Q") |
1275 | (match_operand:SI 1 "general_operand" "d,R,T,d,d,*f,R,T,*f,*f,?Q"))] | |
9db1d521 HP |
1276 | "" |
1277 | "@ | |
d40c829f UW |
1278 | lr\t%0,%1 |
1279 | l\t%0,%1 | |
1280 | ly\t%0,%1 | |
1281 | st\t%1,%0 | |
1282 | sty\t%1,%0 | |
1283 | ler\t%0,%1 | |
1284 | le\t%0,%1 | |
1285 | ley\t%0,%1 | |
1286 | ste\t%1,%0 | |
1287 | stey\t%1,%0 | |
1288 | mvc\t%O0(4,%R0),%1" | |
d3632d41 UW |
1289 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") |
1290 | (set_attr "type" "lr,load,load,store,store,floads,floads,floads,fstores,fstores,cs")]) | |
9db1d521 | 1291 | |
84817c5d UW |
1292 | (define_peephole2 |
1293 | [(set (match_operand:SI 0 "register_operand" "") | |
1294 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1295 | "!FP_REG_P (operands[0]) | |
1296 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1297 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1298 | && get_pool_mode (operands[1]) == SImode | |
1299 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1300 | [(set (match_dup 0) (match_dup 2))] | |
1301 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 HP |
1302 | |
1303 | ; | |
1304 | ; movhi instruction pattern(s). | |
1305 | ; | |
1306 | ||
02ed3c5e UW |
1307 | (define_expand "movhi" |
1308 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
1309 | (match_operand:HI 1 "general_operand" ""))] | |
1310 | "" | |
1311 | { | |
1312 | /* Make it explicit that loading a register from memory | |
1313 | always sign-extends (at least) to SImode. */ | |
1314 | if (optimize && !no_new_pseudos | |
1315 | && register_operand (operands[0], VOIDmode) | |
d71a8c3b UW |
1316 | && GET_CODE (operands[1]) == MEM |
1317 | && GET_CODE (XEXP (operands[1], 0)) != ADDRESSOF) | |
02ed3c5e UW |
1318 | { |
1319 | rtx tmp = gen_reg_rtx (SImode); | |
1320 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
1321 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); | |
1322 | operands[1] = gen_lowpart (HImode, tmp); | |
1323 | } | |
1324 | }) | |
1325 | ||
1326 | (define_insn "*movhi" | |
d3632d41 UW |
1327 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q") |
1328 | (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))] | |
9db1d521 HP |
1329 | "" |
1330 | "@ | |
d40c829f UW |
1331 | lr\t%0,%1 |
1332 | lhi\t%0,%h1 | |
1333 | lh\t%0,%1 | |
1334 | lhy\t%0,%1 | |
1335 | sth\t%1,%0 | |
1336 | sthy\t%1,%0 | |
1337 | mvc\t%O0(2,%R0),%1" | |
d3632d41 UW |
1338 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS") |
1339 | (set_attr "type" "lr,*,*,*,store,store,cs")]) | |
9db1d521 | 1340 | |
84817c5d UW |
1341 | (define_peephole2 |
1342 | [(set (match_operand:HI 0 "register_operand" "") | |
1343 | (mem:HI (match_operand 1 "address_operand" "")))] | |
1344 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1345 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1346 | && get_pool_mode (operands[1]) == HImode | |
1347 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1348 | [(set (match_dup 0) (match_dup 2))] | |
1349 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1350 | |
9db1d521 HP |
1351 | ; |
1352 | ; movqi instruction pattern(s). | |
1353 | ; | |
1354 | ||
02ed3c5e UW |
1355 | (define_expand "movqi" |
1356 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1357 | (match_operand:QI 1 "general_operand" ""))] | |
1358 | "" | |
1359 | { | |
c19ec8f9 | 1360 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 1361 | is just as fast as a QImode load. */ |
c19ec8f9 | 1362 | if (TARGET_ZARCH && optimize && !no_new_pseudos |
02ed3c5e | 1363 | && register_operand (operands[0], VOIDmode) |
d71a8c3b UW |
1364 | && GET_CODE (operands[1]) == MEM |
1365 | && GET_CODE (XEXP (operands[1], 0)) != ADDRESSOF) | |
02ed3c5e | 1366 | { |
c19ec8f9 UW |
1367 | rtx tmp = gen_reg_rtx (word_mode); |
1368 | rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]); | |
02ed3c5e UW |
1369 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); |
1370 | operands[1] = gen_lowpart (QImode, tmp); | |
1371 | } | |
1372 | }) | |
4023fb28 | 1373 | |
02ed3c5e | 1374 | (define_insn "*movqi" |
d3632d41 UW |
1375 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") |
1376 | (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))] | |
9db1d521 HP |
1377 | "" |
1378 | "@ | |
d40c829f UW |
1379 | lr\t%0,%1 |
1380 | lhi\t%0,%b1 | |
1381 | ic\t%0,%1 | |
1382 | icy\t%0,%1 | |
1383 | stc\t%1,%0 | |
1384 | stcy\t%1,%0 | |
1385 | mvi\t%0,%b1 | |
1386 | mviy\t%0,%b1 | |
1387 | mvc\t%O0(1,%R0),%1" | |
d3632d41 UW |
1388 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") |
1389 | (set_attr "type" "lr,*,*,*,store,store,store,store,cs")]) | |
9db1d521 | 1390 | |
84817c5d UW |
1391 | (define_peephole2 |
1392 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1393 | (mem:QI (match_operand 1 "address_operand" "")))] | |
1394 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1395 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1396 | && get_pool_mode (operands[1]) == QImode | |
1397 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1398 | [(set (match_dup 0) (match_dup 2))] | |
1399 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1400 | |
9db1d521 | 1401 | ; |
05b9aaaa | 1402 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
1403 | ; |
1404 | ||
1405 | (define_insn "*movstrictqi" | |
d3632d41 UW |
1406 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
1407 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 1408 | "" |
d3632d41 | 1409 | "@ |
d40c829f UW |
1410 | ic\t%0,%1 |
1411 | icy\t%0,%1" | |
d3632d41 | 1412 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 HP |
1413 | |
1414 | ; | |
1415 | ; movstricthi instruction pattern(s). | |
1416 | ; | |
1417 | ||
1418 | (define_insn "*movstricthi" | |
d3632d41 UW |
1419 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
1420 | (match_operand:HI 1 "s_imm_operand" "Q,S")) | |
9db1d521 HP |
1421 | (clobber (reg:CC 33))] |
1422 | "" | |
d3632d41 | 1423 | "@ |
d40c829f UW |
1424 | icm\t%0,3,%1 |
1425 | icmy\t%0,3,%1" | |
d3632d41 | 1426 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 HP |
1427 | |
1428 | ; | |
1429 | ; movstrictsi instruction pattern(s). | |
1430 | ; | |
1431 | ||
05b9aaaa | 1432 | (define_insn "movstrictsi" |
d3632d41 UW |
1433 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d")) |
1434 | (match_operand:SI 1 "general_operand" "d,R,T"))] | |
9db1d521 HP |
1435 | "TARGET_64BIT" |
1436 | "@ | |
d40c829f UW |
1437 | lr\t%0,%1 |
1438 | l\t%0,%1 | |
1439 | ly\t%0,%1" | |
d3632d41 UW |
1440 | [(set_attr "op_type" "RR,RX,RXY") |
1441 | (set_attr "type" "lr,load,load")]) | |
9db1d521 HP |
1442 | |
1443 | ; | |
1444 | ; movdf instruction pattern(s). | |
1445 | ; | |
1446 | ||
1447 | (define_expand "movdf" | |
1448 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1449 | (match_operand:DF 1 "general_operand" ""))] | |
1450 | "" | |
9db1d521 | 1451 | { |
4023fb28 UW |
1452 | /* During and after reload, we need to force constants |
1453 | to the literal pool ourselves, if necessary. */ | |
1454 | if ((reload_in_progress || reload_completed) | |
1455 | && CONSTANT_P (operands[1])) | |
1456 | operands[1] = force_const_mem (DFmode, operands[1]); | |
10bbf137 | 1457 | }) |
9db1d521 HP |
1458 | |
1459 | (define_insn "*movdf_64" | |
d3632d41 UW |
1460 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q") |
1461 | (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))] | |
4023fb28 | 1462 | "TARGET_64BIT" |
9db1d521 | 1463 | "@ |
d40c829f UW |
1464 | ldr\t%0,%1 |
1465 | ld\t%0,%1 | |
1466 | ldy\t%0,%1 | |
1467 | std\t%1,%0 | |
1468 | stdy\t%1,%0 | |
1469 | lgr\t%0,%1 | |
1470 | lg\t%0,%1 | |
1471 | stg\t%1,%0 | |
1472 | mvc\t%O0(8,%R0),%1" | |
d3632d41 UW |
1473 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") |
1474 | (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,cs")]) | |
9db1d521 HP |
1475 | |
1476 | (define_insn "*movdf_31" | |
d3632d41 UW |
1477 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q") |
1478 | (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))] | |
4023fb28 | 1479 | "!TARGET_64BIT" |
9db1d521 | 1480 | "@ |
d40c829f UW |
1481 | ldr\t%0,%1 |
1482 | ld\t%0,%1 | |
1483 | ldy\t%0,%1 | |
1484 | std\t%1,%0 | |
1485 | stdy\t%1,%0 | |
1486 | lm\t%0,%N0,%1 | |
1487 | stm\t%1,%N1,%0 | |
4023fb28 | 1488 | # |
9b7c75b9 | 1489 | # |
d40c829f | 1490 | mvc\t%O0(8,%R0),%1" |
d3632d41 UW |
1491 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,NN,NN,SS") |
1492 | (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,cs")]) | |
4023fb28 UW |
1493 | |
1494 | (define_split | |
1495 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1496 | (match_operand:DF 1 "general_operand" ""))] | |
1497 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 1498 | && s390_split_ok_p (operands[0], operands[1], DFmode, 0)" |
4023fb28 UW |
1499 | [(set (match_dup 2) (match_dup 4)) |
1500 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1501 | { |
dc65c307 UW |
1502 | operands[2] = operand_subword (operands[0], 0, 0, DFmode); |
1503 | operands[3] = operand_subword (operands[0], 1, 0, DFmode); | |
1504 | operands[4] = operand_subword (operands[1], 0, 0, DFmode); | |
1505 | operands[5] = operand_subword (operands[1], 1, 0, DFmode); | |
1506 | }) | |
1507 | ||
1508 | (define_split | |
1509 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1510 | (match_operand:DF 1 "general_operand" ""))] | |
1511 | "!TARGET_64BIT && reload_completed | |
1512 | && s390_split_ok_p (operands[0], operands[1], DFmode, 1)" | |
1513 | [(set (match_dup 2) (match_dup 4)) | |
1514 | (set (match_dup 3) (match_dup 5))] | |
1515 | { | |
1516 | operands[2] = operand_subword (operands[0], 1, 0, DFmode); | |
1517 | operands[3] = operand_subword (operands[0], 0, 0, DFmode); | |
1518 | operands[4] = operand_subword (operands[1], 1, 0, DFmode); | |
1519 | operands[5] = operand_subword (operands[1], 0, 0, DFmode); | |
1520 | }) | |
9db1d521 | 1521 | |
4023fb28 UW |
1522 | (define_split |
1523 | [(set (match_operand:DF 0 "register_operand" "") | |
1524 | (match_operand:DF 1 "memory_operand" ""))] | |
1525 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 1526 | && !FP_REG_P (operands[0]) |
4023fb28 | 1527 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1528 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1529 | { |
1530 | rtx addr = operand_subword (operands[0], 1, 0, DFmode); | |
1531 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1532 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1533 | }) |
1534 | ||
1535 | (define_expand "reload_outdf" | |
1536 | [(parallel [(match_operand:DF 0 "memory_operand" "") | |
1537 | (match_operand:DF 1 "register_operand" "d") | |
1538 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1539 | "!TARGET_64BIT" | |
1540 | { | |
1541 | s390_load_address (operands[2], XEXP (operands[0], 0)); | |
1542 | operands[0] = replace_equiv_address (operands[0], operands[2]); | |
1543 | emit_move_insn (operands[0], operands[1]); | |
1544 | DONE; | |
1545 | }) | |
9db1d521 HP |
1546 | |
1547 | ; | |
1548 | ; movsf instruction pattern(s). | |
1549 | ; | |
1550 | ||
1551 | (define_expand "movsf" | |
1552 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
1553 | (match_operand:SF 1 "general_operand" ""))] | |
1554 | "" | |
9db1d521 | 1555 | { |
4023fb28 UW |
1556 | /* During and after reload, we need to force constants |
1557 | to the literal pool ourselves, if necessary. */ | |
1558 | if ((reload_in_progress || reload_completed) | |
1559 | && CONSTANT_P (operands[1])) | |
1560 | operands[1] = force_const_mem (SFmode, operands[1]); | |
10bbf137 | 1561 | }) |
9db1d521 | 1562 | |
4023fb28 | 1563 | (define_insn "*movsf" |
d3632d41 UW |
1564 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q") |
1565 | (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))] | |
4023fb28 | 1566 | "" |
9db1d521 | 1567 | "@ |
d40c829f UW |
1568 | ler\t%0,%1 |
1569 | le\t%0,%1 | |
1570 | ley\t%0,%1 | |
1571 | ste\t%1,%0 | |
1572 | stey\t%1,%0 | |
1573 | lr\t%0,%1 | |
1574 | l\t%0,%1 | |
1575 | ly\t%0,%1 | |
1576 | st\t%1,%0 | |
1577 | sty\t%1,%0 | |
1578 | mvc\t%O0(4,%R0),%1" | |
d3632d41 UW |
1579 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") |
1580 | (set_attr "type" "floads,floads,floads,fstores,fstores,lr,load,load,store,store,cs")]) | |
4023fb28 | 1581 | |
9db1d521 HP |
1582 | ; |
1583 | ; load_multiple pattern(s). | |
1584 | ; | |
1585 | ||
1586 | (define_expand "load_multiple" | |
1587 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1588 | (match_operand 1 "" "")) | |
1589 | (use (match_operand 2 "" ""))])] | |
1590 | "" | |
9db1d521 | 1591 | { |
c19ec8f9 | 1592 | enum machine_mode mode; |
9db1d521 HP |
1593 | int regno; |
1594 | int count; | |
1595 | rtx from; | |
4023fb28 | 1596 | int i, off; |
9db1d521 HP |
1597 | |
1598 | /* Support only loading a constant number of fixed-point registers from | |
1599 | memory and only bother with this if more than two */ | |
1600 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1601 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1602 | || INTVAL (operands[2]) > 16 |
1603 | || GET_CODE (operands[1]) != MEM | |
1604 | || GET_CODE (operands[0]) != REG | |
1605 | || REGNO (operands[0]) >= 16) | |
1606 | FAIL; | |
1607 | ||
1608 | count = INTVAL (operands[2]); | |
1609 | regno = REGNO (operands[0]); | |
c19ec8f9 UW |
1610 | mode = GET_MODE (operands[0]); |
1611 | if (mode != SImode && mode != word_mode) | |
1612 | FAIL; | |
9db1d521 HP |
1613 | |
1614 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1615 | if (no_new_pseudos) |
1616 | { | |
1617 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
1618 | { | |
1619 | from = XEXP (operands[1], 0); | |
1620 | off = 0; | |
1621 | } | |
1622 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
1623 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
1624 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
1625 | { | |
1626 | from = XEXP (XEXP (operands[1], 0), 0); | |
1627 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
1628 | } | |
1629 | else | |
1630 | FAIL; | |
1631 | ||
1632 | if (from == frame_pointer_rtx || from == arg_pointer_rtx) | |
1633 | FAIL; | |
1634 | } | |
1635 | else | |
1636 | { | |
1637 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
1638 | off = 0; | |
1639 | } | |
9db1d521 HP |
1640 | |
1641 | for (i = 0; i < count; i++) | |
1642 | XVECEXP (operands[3], 0, i) | |
c19ec8f9 UW |
1643 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), |
1644 | change_address (operands[1], mode, | |
1645 | plus_constant (from, off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 1646 | }) |
9db1d521 HP |
1647 | |
1648 | (define_insn "*load_multiple_di" | |
1649 | [(match_parallel 0 "load_multiple_operation" | |
1650 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 1651 | (match_operand:DI 2 "s_operand" "QS"))])] |
c19ec8f9 | 1652 | "word_mode == DImode" |
9db1d521 HP |
1653 | { |
1654 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1655 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
d40c829f | 1656 | return "lmg\t%1,%0,%2"; |
10bbf137 | 1657 | } |
d3632d41 | 1658 | [(set_attr "op_type" "RSY") |
4023fb28 | 1659 | (set_attr "type" "lm")]) |
9db1d521 HP |
1660 | |
1661 | (define_insn "*load_multiple_si" | |
1662 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
1663 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
1664 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
9db1d521 | 1665 | "" |
9db1d521 HP |
1666 | { |
1667 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1668 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
d40c829f | 1669 | return which_alternative == 0 ? "lm\t%1,%0,%2" : "lmy\t%1,%0,%2"; |
10bbf137 | 1670 | } |
d3632d41 | 1671 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1672 | (set_attr "type" "lm")]) |
9db1d521 HP |
1673 | |
1674 | ; | |
c7453384 | 1675 | ; store multiple pattern(s). |
9db1d521 HP |
1676 | ; |
1677 | ||
1678 | (define_expand "store_multiple" | |
1679 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1680 | (match_operand 1 "" "")) | |
1681 | (use (match_operand 2 "" ""))])] | |
1682 | "" | |
9db1d521 | 1683 | { |
c19ec8f9 | 1684 | enum machine_mode mode; |
9db1d521 HP |
1685 | int regno; |
1686 | int count; | |
1687 | rtx to; | |
4023fb28 | 1688 | int i, off; |
9db1d521 HP |
1689 | |
1690 | /* Support only storing a constant number of fixed-point registers to | |
1691 | memory and only bother with this if more than two. */ | |
1692 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1693 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1694 | || INTVAL (operands[2]) > 16 |
1695 | || GET_CODE (operands[0]) != MEM | |
1696 | || GET_CODE (operands[1]) != REG | |
1697 | || REGNO (operands[1]) >= 16) | |
1698 | FAIL; | |
1699 | ||
1700 | count = INTVAL (operands[2]); | |
1701 | regno = REGNO (operands[1]); | |
c19ec8f9 UW |
1702 | mode = GET_MODE (operands[1]); |
1703 | if (mode != SImode && mode != word_mode) | |
1704 | FAIL; | |
9db1d521 HP |
1705 | |
1706 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1707 | |
1708 | if (no_new_pseudos) | |
1709 | { | |
1710 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
1711 | { | |
1712 | to = XEXP (operands[0], 0); | |
1713 | off = 0; | |
1714 | } | |
1715 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
1716 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
1717 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
1718 | { | |
1719 | to = XEXP (XEXP (operands[0], 0), 0); | |
1720 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
1721 | } | |
1722 | else | |
1723 | FAIL; | |
1724 | ||
1725 | if (to == frame_pointer_rtx || to == arg_pointer_rtx) | |
1726 | FAIL; | |
1727 | } | |
c7453384 | 1728 | else |
4023fb28 UW |
1729 | { |
1730 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
1731 | off = 0; | |
1732 | } | |
9db1d521 HP |
1733 | |
1734 | for (i = 0; i < count; i++) | |
1735 | XVECEXP (operands[3], 0, i) | |
1736 | = gen_rtx_SET (VOIDmode, | |
c19ec8f9 UW |
1737 | change_address (operands[0], mode, |
1738 | plus_constant (to, off + i * GET_MODE_SIZE (mode))), | |
1739 | gen_rtx_REG (mode, regno + i)); | |
10bbf137 | 1740 | }) |
9db1d521 HP |
1741 | |
1742 | (define_insn "*store_multiple_di" | |
1743 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 1744 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 1745 | (match_operand:DI 2 "register_operand" "r"))])] |
c19ec8f9 | 1746 | "word_mode == DImode" |
9db1d521 HP |
1747 | { |
1748 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1749 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
d40c829f | 1750 | return "stmg\t%2,%0,%1"; |
10bbf137 | 1751 | } |
d3632d41 | 1752 | [(set_attr "op_type" "RSY") |
4023fb28 | 1753 | (set_attr "type" "stm")]) |
9db1d521 HP |
1754 | |
1755 | ||
1756 | (define_insn "*store_multiple_si" | |
1757 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
1758 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
1759 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
9db1d521 | 1760 | "" |
9db1d521 HP |
1761 | { |
1762 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1763 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
d40c829f | 1764 | return which_alternative == 0 ? "stm\t%2,%0,%1" : "stmy\t%2,%0,%1"; |
10bbf137 | 1765 | } |
d3632d41 | 1766 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1767 | (set_attr "type" "stm")]) |
9db1d521 HP |
1768 | |
1769 | ;; | |
1770 | ;; String instructions. | |
1771 | ;; | |
1772 | ||
1773 | ; | |
a41c6c53 | 1774 | ; movstrM instruction pattern(s). |
9db1d521 HP |
1775 | ; |
1776 | ||
1777 | (define_expand "movstrdi" | |
a41c6c53 UW |
1778 | [(set (match_operand:BLK 0 "memory_operand" "") |
1779 | (match_operand:BLK 1 "memory_operand" "")) | |
1780 | (use (match_operand:DI 2 "general_operand" "")) | |
1781 | (match_operand 3 "" "")] | |
1782 | "TARGET_64BIT" | |
1783 | "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;") | |
9db1d521 HP |
1784 | |
1785 | (define_expand "movstrsi" | |
a41c6c53 UW |
1786 | [(set (match_operand:BLK 0 "memory_operand" "") |
1787 | (match_operand:BLK 1 "memory_operand" "")) | |
1788 | (use (match_operand:SI 2 "general_operand" "")) | |
1789 | (match_operand 3 "" "")] | |
1790 | "" | |
1791 | "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;") | |
9db1d521 | 1792 | |
ecbe845e UW |
1793 | ; Move a block that is up to 256 bytes in length. |
1794 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 1795 | |
b9404c99 UW |
1796 | (define_expand "movstr_short" |
1797 | [(parallel | |
1798 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1799 | (match_operand:BLK 1 "memory_operand" "")) | |
1800 | (use (match_operand 2 "nonmemory_operand" "")) | |
1801 | (clobber (match_dup 3))])] | |
1802 | "" | |
1803 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 1804 | |
b9404c99 | 1805 | (define_insn "*movstr_short" |
a41c6c53 UW |
1806 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q") |
1807 | (match_operand:BLK 1 "memory_operand" "Q,Q")) | |
b9404c99 UW |
1808 | (use (match_operand 2 "nonmemory_operand" "n,a")) |
1809 | (clobber (match_scratch 3 "=X,&a"))] | |
1810 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) | |
1811 | && GET_MODE (operands[3]) == Pmode" | |
ecbe845e UW |
1812 | { |
1813 | switch (which_alternative) | |
1814 | { | |
1815 | case 0: | |
d40c829f | 1816 | return "mvc\t%O0(%b2+1,%R0),%1"; |
ecbe845e UW |
1817 | |
1818 | case 1: | |
d40c829f UW |
1819 | output_asm_insn ("bras\t%3,.+10", operands); |
1820 | output_asm_insn ("mvc\t%O0(1,%R0),%1", operands); | |
1821 | return "ex\t%2,0(%3)"; | |
9db1d521 | 1822 | |
ecbe845e UW |
1823 | default: |
1824 | abort (); | |
1825 | } | |
10bbf137 | 1826 | } |
ecbe845e | 1827 | [(set_attr "op_type" "SS,NN") |
a41c6c53 | 1828 | (set_attr "type" "cs,cs") |
077dab3b | 1829 | (set_attr "atype" "*,agen") |
ecbe845e | 1830 | (set_attr "length" "*,14")]) |
9db1d521 | 1831 | |
a41c6c53 | 1832 | ; Move a block of arbitrary length. |
9db1d521 | 1833 | |
b9404c99 UW |
1834 | (define_expand "movstr_long" |
1835 | [(parallel | |
1836 | [(clobber (match_dup 2)) | |
1837 | (clobber (match_dup 3)) | |
1838 | (set (match_operand:BLK 0 "memory_operand" "") | |
1839 | (match_operand:BLK 1 "memory_operand" "")) | |
1840 | (use (match_operand 2 "general_operand" "")) | |
1841 | (use (match_dup 3)) | |
1842 | (clobber (reg:CC 33))])] | |
1843 | "" | |
1844 | { | |
1845 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
1846 | rtx reg0 = gen_reg_rtx (dword_mode); | |
1847 | rtx reg1 = gen_reg_rtx (dword_mode); | |
1848 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
1849 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
1850 | rtx len0 = gen_lowpart (Pmode, reg0); | |
1851 | rtx len1 = gen_lowpart (Pmode, reg1); | |
1852 | ||
1853 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
1854 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
1855 | emit_move_insn (len0, operands[2]); | |
1856 | ||
1857 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
1858 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
1859 | emit_move_insn (len1, operands[2]); | |
1860 | ||
1861 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
1862 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
1863 | operands[2] = reg0; | |
1864 | operands[3] = reg1; | |
1865 | }) | |
1866 | ||
1867 | (define_insn "*movstr_long_64" | |
1868 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
1869 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
1870 | (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
1871 | (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))) | |
1872 | (use (match_dup 2)) | |
1873 | (use (match_dup 3)) | |
9db1d521 | 1874 | (clobber (reg:CC 33))] |
9f37ccb1 | 1875 | "TARGET_64BIT" |
d40c829f | 1876 | "mvcle\t%0,%1,0\;jo\t.-4" |
9db1d521 | 1877 | [(set_attr "op_type" "NN") |
a41c6c53 | 1878 | (set_attr "type" "vs") |
9db1d521 HP |
1879 | (set_attr "length" "8")]) |
1880 | ||
b9404c99 UW |
1881 | (define_insn "*movstr_long_31" |
1882 | [(clobber (match_operand:DI 0 "register_operand" "=d")) | |
1883 | (clobber (match_operand:DI 1 "register_operand" "=d")) | |
1884 | (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
1885 | (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))) | |
1886 | (use (match_dup 2)) | |
1887 | (use (match_dup 3)) | |
9db1d521 | 1888 | (clobber (reg:CC 33))] |
9f37ccb1 | 1889 | "!TARGET_64BIT" |
d40c829f | 1890 | "mvcle\t%0,%1,0\;jo\t.-4" |
a41c6c53 UW |
1891 | [(set_attr "op_type" "NN") |
1892 | (set_attr "type" "vs") | |
a41c6c53 | 1893 | (set_attr "length" "8")]) |
9db1d521 HP |
1894 | |
1895 | ; | |
a41c6c53 | 1896 | ; clrstrM instruction pattern(s). |
9db1d521 HP |
1897 | ; |
1898 | ||
1899 | (define_expand "clrstrdi" | |
a41c6c53 | 1900 | [(set (match_operand:BLK 0 "memory_operand" "") |
9db1d521 HP |
1901 | (const_int 0)) |
1902 | (use (match_operand:DI 1 "general_operand" "")) | |
1903 | (match_operand 2 "" "")] | |
1904 | "TARGET_64BIT" | |
a41c6c53 | 1905 | "s390_expand_clrstr (operands[0], operands[1]); DONE;") |
9db1d521 HP |
1906 | |
1907 | (define_expand "clrstrsi" | |
a41c6c53 | 1908 | [(set (match_operand:BLK 0 "memory_operand" "") |
9db1d521 HP |
1909 | (const_int 0)) |
1910 | (use (match_operand:SI 1 "general_operand" "")) | |
1911 | (match_operand 2 "" "")] | |
a41c6c53 UW |
1912 | "" |
1913 | "s390_expand_clrstr (operands[0], operands[1]); DONE;") | |
9db1d521 | 1914 | |
a41c6c53 | 1915 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
1916 | ; The block length is taken as (operands[1] % 256) + 1. |
1917 | ||
1918 | (define_expand "clrstr_short" | |
1919 | [(parallel | |
1920 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1921 | (const_int 0)) | |
1922 | (use (match_operand 1 "nonmemory_operand" "")) | |
1923 | (clobber (match_dup 2)) | |
1924 | (clobber (reg:CC 33))])] | |
1925 | "" | |
1926 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 1927 | |
b9404c99 | 1928 | (define_insn "*clrstr_short" |
a41c6c53 UW |
1929 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q") |
1930 | (const_int 0)) | |
b9404c99 UW |
1931 | (use (match_operand 1 "nonmemory_operand" "n,a")) |
1932 | (clobber (match_scratch 2 "=X,&a")) | |
a41c6c53 | 1933 | (clobber (reg:CC 33))] |
b9404c99 UW |
1934 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode) |
1935 | && GET_MODE (operands[2]) == Pmode" | |
a41c6c53 UW |
1936 | { |
1937 | switch (which_alternative) | |
1938 | { | |
1939 | case 0: | |
d40c829f | 1940 | return "xc\t%O0(%b1+1,%R0),%0"; |
9db1d521 | 1941 | |
a41c6c53 | 1942 | case 1: |
d40c829f UW |
1943 | output_asm_insn ("bras\t%2,.+10", operands); |
1944 | output_asm_insn ("xc\t%O0(1,%R0),%0", operands); | |
1945 | return "ex\t%1,0(%2)"; | |
9db1d521 | 1946 | |
a41c6c53 UW |
1947 | default: |
1948 | abort (); | |
1949 | } | |
10bbf137 | 1950 | } |
a41c6c53 UW |
1951 | [(set_attr "op_type" "SS,NN") |
1952 | (set_attr "type" "cs,cs") | |
077dab3b | 1953 | (set_attr "atype" "*,agen") |
a41c6c53 | 1954 | (set_attr "length" "*,14")]) |
9db1d521 | 1955 | |
b9404c99 UW |
1956 | ; Clear a block of arbitrary length. |
1957 | ||
1958 | (define_expand "clrstr_long" | |
1959 | [(parallel | |
1960 | [(clobber (match_dup 1)) | |
1961 | (set (match_operand:BLK 0 "memory_operand" "") | |
1962 | (const_int 0)) | |
1963 | (use (match_operand 1 "general_operand" "")) | |
1964 | (use (match_dup 2)) | |
1965 | (clobber (reg:CC 33))])] | |
1966 | "" | |
a41c6c53 | 1967 | { |
b9404c99 UW |
1968 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; |
1969 | rtx reg0 = gen_reg_rtx (dword_mode); | |
1970 | rtx reg1 = gen_reg_rtx (dword_mode); | |
1971 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
1972 | rtx len0 = gen_lowpart (Pmode, reg0); | |
9db1d521 | 1973 | |
b9404c99 UW |
1974 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); |
1975 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
1976 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 1977 | |
b9404c99 | 1978 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 1979 | |
b9404c99 UW |
1980 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
1981 | operands[1] = reg0; | |
1982 | operands[2] = reg1; | |
1983 | }) | |
a41c6c53 | 1984 | |
b9404c99 UW |
1985 | (define_insn "*clrstr_long_64" |
1986 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
1987 | (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
9db1d521 | 1988 | (const_int 0)) |
b9404c99 | 1989 | (use (match_dup 2)) |
9f37ccb1 | 1990 | (use (match_operand:TI 1 "register_operand" "d")) |
9db1d521 HP |
1991 | (clobber (reg:CC 33))] |
1992 | "TARGET_64BIT" | |
d40c829f | 1993 | "mvcle\t%0,%1,0\;jo\t.-4" |
9db1d521 | 1994 | [(set_attr "op_type" "NN") |
4023fb28 | 1995 | (set_attr "type" "vs") |
9db1d521 HP |
1996 | (set_attr "length" "8")]) |
1997 | ||
b9404c99 UW |
1998 | (define_insn "*clrstr_long_31" |
1999 | [(clobber (match_operand:DI 0 "register_operand" "=d")) | |
2000 | (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
9db1d521 | 2001 | (const_int 0)) |
b9404c99 | 2002 | (use (match_dup 2)) |
9f37ccb1 | 2003 | (use (match_operand:DI 1 "register_operand" "d")) |
9db1d521 HP |
2004 | (clobber (reg:CC 33))] |
2005 | "!TARGET_64BIT" | |
d40c829f | 2006 | "mvcle\t%0,%1,0\;jo\t.-4" |
9db1d521 | 2007 | [(set_attr "op_type" "NN") |
4023fb28 | 2008 | (set_attr "type" "vs") |
9db1d521 HP |
2009 | (set_attr "length" "8")]) |
2010 | ||
2011 | ; | |
358b8f01 | 2012 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
2013 | ; |
2014 | ||
358b8f01 | 2015 | (define_expand "cmpmemdi" |
a41c6c53 UW |
2016 | [(set (match_operand:DI 0 "register_operand" "") |
2017 | (compare:DI (match_operand:BLK 1 "memory_operand" "") | |
2018 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
2019 | (use (match_operand:DI 3 "general_operand" "")) | |
2020 | (use (match_operand:DI 4 "" ""))] | |
2021 | "TARGET_64BIT" | |
c7453384 | 2022 | "s390_expand_cmpmem (operands[0], operands[1], |
a41c6c53 | 2023 | operands[2], operands[3]); DONE;") |
9db1d521 | 2024 | |
358b8f01 | 2025 | (define_expand "cmpmemsi" |
a41c6c53 UW |
2026 | [(set (match_operand:SI 0 "register_operand" "") |
2027 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
2028 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
2029 | (use (match_operand:SI 3 "general_operand" "")) | |
2030 | (use (match_operand:SI 4 "" ""))] | |
2031 | "" | |
c7453384 | 2032 | "s390_expand_cmpmem (operands[0], operands[1], |
a41c6c53 | 2033 | operands[2], operands[3]); DONE;") |
9db1d521 | 2034 | |
a41c6c53 UW |
2035 | ; Compare a block that is up to 256 bytes in length. |
2036 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2037 | |
b9404c99 UW |
2038 | (define_expand "cmpmem_short" |
2039 | [(parallel | |
2040 | [(set (reg:CCS 33) | |
2041 | (compare:CCS (match_operand:BLK 0 "memory_operand" "") | |
2042 | (match_operand:BLK 1 "memory_operand" ""))) | |
2043 | (use (match_operand 2 "nonmemory_operand" "")) | |
2044 | (clobber (match_dup 3))])] | |
2045 | "" | |
2046 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2047 | |
b9404c99 | 2048 | (define_insn "*cmpmem_short" |
a41c6c53 UW |
2049 | [(set (reg:CCS 33) |
2050 | (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q") | |
2051 | (match_operand:BLK 1 "memory_operand" "Q,Q"))) | |
b9404c99 UW |
2052 | (use (match_operand 2 "nonmemory_operand" "n,a")) |
2053 | (clobber (match_scratch 3 "=X,&a"))] | |
2054 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) | |
2055 | && GET_MODE (operands[3]) == Pmode" | |
9db1d521 | 2056 | { |
a41c6c53 | 2057 | switch (which_alternative) |
9db1d521 | 2058 | { |
a41c6c53 | 2059 | case 0: |
d40c829f | 2060 | return "clc\t%O0(%b2+1,%R0),%1"; |
9db1d521 | 2061 | |
a41c6c53 | 2062 | case 1: |
d40c829f UW |
2063 | output_asm_insn ("bras\t%3,.+10", operands); |
2064 | output_asm_insn ("clc\t%O0(1,%R0),%1", operands); | |
2065 | return "ex\t%2,0(%3)"; | |
9db1d521 | 2066 | |
a41c6c53 UW |
2067 | default: |
2068 | abort (); | |
9db1d521 | 2069 | } |
10bbf137 | 2070 | } |
a41c6c53 UW |
2071 | [(set_attr "op_type" "SS,NN") |
2072 | (set_attr "type" "cs,cs") | |
077dab3b | 2073 | (set_attr "atype" "*,agen") |
a41c6c53 | 2074 | (set_attr "length" "*,14")]) |
9db1d521 | 2075 | |
a41c6c53 | 2076 | ; Compare a block of arbitrary length. |
9db1d521 | 2077 | |
b9404c99 UW |
2078 | (define_expand "cmpmem_long" |
2079 | [(parallel | |
2080 | [(clobber (match_dup 2)) | |
2081 | (clobber (match_dup 3)) | |
2082 | (set (reg:CCS 33) | |
2083 | (compare:CCS (match_operand:BLK 0 "memory_operand" "") | |
2084 | (match_operand:BLK 1 "memory_operand" ""))) | |
2085 | (use (match_operand 2 "general_operand" "")) | |
2086 | (use (match_dup 3))])] | |
2087 | "" | |
2088 | { | |
2089 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
2090 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2091 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2092 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2093 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
2094 | rtx len0 = gen_lowpart (Pmode, reg0); | |
2095 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2096 | ||
2097 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
2098 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2099 | emit_move_insn (len0, operands[2]); | |
2100 | ||
2101 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
2102 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2103 | emit_move_insn (len1, operands[2]); | |
2104 | ||
2105 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2106 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2107 | operands[2] = reg0; | |
2108 | operands[3] = reg1; | |
2109 | }) | |
2110 | ||
2111 | (define_insn "*cmpmem_long_64" | |
4023fb28 UW |
2112 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
2113 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
2114 | (set (reg:CCS 33) | |
2115 | (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
f8766020 HP |
2116 | (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))) |
2117 | (use (match_dup 2)) | |
2118 | (use (match_dup 3))] | |
9db1d521 | 2119 | "TARGET_64BIT" |
d40c829f | 2120 | "clcl\t%0,%1" |
9db1d521 | 2121 | [(set_attr "op_type" "RR") |
4023fb28 | 2122 | (set_attr "type" "vs")]) |
9db1d521 | 2123 | |
b9404c99 | 2124 | (define_insn "*cmpmem_long_31" |
4023fb28 UW |
2125 | [(clobber (match_operand:DI 0 "register_operand" "=d")) |
2126 | (clobber (match_operand:DI 1 "register_operand" "=d")) | |
2127 | (set (reg:CCS 33) | |
2128 | (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
f8766020 HP |
2129 | (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))) |
2130 | (use (match_dup 2)) | |
2131 | (use (match_dup 3))] | |
9db1d521 | 2132 | "!TARGET_64BIT" |
d40c829f | 2133 | "clcl\t%0,%1" |
9db1d521 | 2134 | [(set_attr "op_type" "RR") |
4023fb28 | 2135 | (set_attr "type" "vs")]) |
9db1d521 HP |
2136 | |
2137 | ; Convert condition code to integer in range (-1, 0, 1) | |
2138 | ||
2139 | (define_insn "cmpint_si" | |
2140 | [(set (match_operand:SI 0 "register_operand" "=d") | |
ba956982 | 2141 | (compare:SI (reg:CCS 33) (const_int 0)))] |
9db1d521 | 2142 | "" |
9db1d521 | 2143 | { |
d40c829f UW |
2144 | output_asm_insn ("lhi\t%0,1", operands); |
2145 | output_asm_insn ("jh\t.+12", operands); | |
2146 | output_asm_insn ("jl\t.+6", operands); | |
2147 | output_asm_insn ("sr\t%0,%0", operands); | |
2148 | return "lcr\t%0,%0"; | |
10bbf137 | 2149 | } |
9db1d521 HP |
2150 | [(set_attr "op_type" "NN") |
2151 | (set_attr "length" "16") | |
f2d3c02a | 2152 | (set_attr "type" "other")]) |
9db1d521 HP |
2153 | |
2154 | (define_insn "cmpint_di" | |
2155 | [(set (match_operand:DI 0 "register_operand" "=d") | |
ba956982 | 2156 | (compare:DI (reg:CCS 33) (const_int 0)))] |
9db1d521 | 2157 | "TARGET_64BIT" |
9db1d521 | 2158 | { |
d40c829f | 2159 | output_asm_insn ("lghi\t%0,1", operands); |
fd87a357 UW |
2160 | output_asm_insn ("jh\t.+16", operands); |
2161 | output_asm_insn ("jl\t.+8", operands); | |
d40c829f UW |
2162 | output_asm_insn ("sgr\t%0,%0", operands); |
2163 | return "lcgr\t%0,%0"; | |
10bbf137 | 2164 | } |
9db1d521 | 2165 | [(set_attr "op_type" "NN") |
fd87a357 | 2166 | (set_attr "length" "20") |
f2d3c02a | 2167 | (set_attr "type" "other")]) |
9db1d521 | 2168 | |
4023fb28 | 2169 | |
9db1d521 HP |
2170 | ;; |
2171 | ;;- Conversion instructions. | |
2172 | ;; | |
2173 | ||
4023fb28 | 2174 | (define_insn "*sethighqisi" |
d3632d41 | 2175 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
10bbf137 | 2176 | (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2177 | (clobber (reg:CC 33))] |
2178 | "" | |
d3632d41 | 2179 | "@ |
d40c829f UW |
2180 | icm\t%0,8,%1 |
2181 | icmy\t%0,8,%1" | |
d3632d41 | 2182 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 UW |
2183 | |
2184 | (define_insn "*sethighhisi" | |
d3632d41 | 2185 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
10bbf137 | 2186 | (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2187 | (clobber (reg:CC 33))] |
2188 | "" | |
d3632d41 | 2189 | "@ |
d40c829f UW |
2190 | icm\t%0,12,%1 |
2191 | icmy\t%0,12,%1" | |
d3632d41 | 2192 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 UW |
2193 | |
2194 | (define_insn "*sethighqidi_64" | |
2195 | [(set (match_operand:DI 0 "register_operand" "=d") | |
10bbf137 | 2196 | (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2197 | (clobber (reg:CC 33))] |
2198 | "TARGET_64BIT" | |
d40c829f | 2199 | "icmh\t%0,8,%1" |
d3632d41 | 2200 | [(set_attr "op_type" "RSY")]) |
4023fb28 UW |
2201 | |
2202 | (define_insn "*sethighqidi_31" | |
d3632d41 | 2203 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
10bbf137 | 2204 | (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2205 | (clobber (reg:CC 33))] |
2206 | "!TARGET_64BIT" | |
d3632d41 | 2207 | "@ |
d40c829f UW |
2208 | icm\t%0,8,%1 |
2209 | icmy\t%0,8,%1" | |
d3632d41 | 2210 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 | 2211 | |
cc7ab9b7 UW |
2212 | (define_insn_and_split "*extractqi" |
2213 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2214 | (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") | |
2215 | (match_operand 2 "const_int_operand" "n") | |
2216 | (const_int 0))) | |
2217 | (clobber (reg:CC 33))] | |
2218 | "!TARGET_64BIT | |
4023fb28 | 2219 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8" |
cc7ab9b7 UW |
2220 | "#" |
2221 | "&& reload_completed" | |
4023fb28 | 2222 | [(parallel |
10bbf137 | 2223 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2224 | (clobber (reg:CC 33))]) |
2225 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] | |
4023fb28 UW |
2226 | { |
2227 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
2228 | operands[1] = change_address (operands[1], QImode, 0); | |
10bbf137 | 2229 | } |
0796c16a | 2230 | [(set_attr "atype" "agen")]) |
4023fb28 | 2231 | |
cc7ab9b7 UW |
2232 | (define_insn_and_split "*extracthi" |
2233 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2234 | (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") | |
2235 | (match_operand 2 "const_int_operand" "n") | |
2236 | (const_int 0))) | |
2237 | (clobber (reg:CC 33))] | |
2238 | "!TARGET_64BIT | |
4023fb28 | 2239 | && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16" |
cc7ab9b7 UW |
2240 | "#" |
2241 | "&& reload_completed" | |
4023fb28 | 2242 | [(parallel |
10bbf137 | 2243 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2244 | (clobber (reg:CC 33))]) |
2245 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] | |
4023fb28 UW |
2246 | { |
2247 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
2248 | operands[1] = change_address (operands[1], HImode, 0); | |
10bbf137 | 2249 | } |
0796c16a | 2250 | [(set_attr "atype" "agen")]) |
4023fb28 | 2251 | |
9db1d521 HP |
2252 | ; |
2253 | ; extendsidi2 instruction pattern(s). | |
2254 | ; | |
2255 | ||
4023fb28 UW |
2256 | (define_expand "extendsidi2" |
2257 | [(set (match_operand:DI 0 "register_operand" "") | |
2258 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2259 | "" | |
2260 | " | |
2261 | { | |
2262 | if (!TARGET_64BIT) | |
2263 | { | |
9f37ccb1 UW |
2264 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2265 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); | |
2266 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
2267 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
2268 | DONE; |
2269 | } | |
2270 | } | |
2271 | ") | |
2272 | ||
2273 | (define_insn "*extendsidi2" | |
9db1d521 HP |
2274 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2275 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2276 | "TARGET_64BIT" | |
2277 | "@ | |
d40c829f UW |
2278 | lgfr\t%0,%1 |
2279 | lgf\t%0,%1" | |
d3632d41 | 2280 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2281 | |
9db1d521 HP |
2282 | ; |
2283 | ; extendhidi2 instruction pattern(s). | |
2284 | ; | |
2285 | ||
4023fb28 UW |
2286 | (define_expand "extendhidi2" |
2287 | [(set (match_operand:DI 0 "register_operand" "") | |
2288 | (sign_extend:DI (match_operand:HI 1 "register_operand" "")))] | |
2289 | "" | |
2290 | " | |
2291 | { | |
2292 | if (!TARGET_64BIT) | |
2293 | { | |
2294 | rtx tmp = gen_reg_rtx (SImode); | |
2295 | emit_insn (gen_extendhisi2 (tmp, operands[1])); | |
2296 | emit_insn (gen_extendsidi2 (operands[0], tmp)); | |
2297 | DONE; | |
2298 | } | |
2299 | else | |
2300 | { | |
2301 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2302 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); | |
c7453384 | 2303 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48))); |
4023fb28 UW |
2304 | DONE; |
2305 | } | |
2306 | } | |
2307 | ") | |
2308 | ||
2309 | (define_insn "*extendhidi2" | |
9db1d521 | 2310 | [(set (match_operand:DI 0 "register_operand" "=d") |
4023fb28 | 2311 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] |
9db1d521 | 2312 | "TARGET_64BIT" |
d40c829f | 2313 | "lgh\t%0,%1" |
d3632d41 | 2314 | [(set_attr "op_type" "RXY")]) |
9db1d521 HP |
2315 | |
2316 | ; | |
2317 | ; extendqidi2 instruction pattern(s). | |
2318 | ; | |
2319 | ||
4023fb28 UW |
2320 | (define_expand "extendqidi2" |
2321 | [(set (match_operand:DI 0 "register_operand" "") | |
2322 | (sign_extend:DI (match_operand:QI 1 "register_operand" "")))] | |
2323 | "" | |
2324 | " | |
2325 | { | |
2326 | if (!TARGET_64BIT) | |
2327 | { | |
2328 | rtx tmp = gen_reg_rtx (SImode); | |
2329 | emit_insn (gen_extendqisi2 (tmp, operands[1])); | |
2330 | emit_insn (gen_extendsidi2 (operands[0], tmp)); | |
2331 | DONE; | |
2332 | } | |
2333 | else | |
2334 | { | |
2335 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2336 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); | |
c7453384 | 2337 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56))); |
4023fb28 UW |
2338 | DONE; |
2339 | } | |
2340 | } | |
2341 | ") | |
2342 | ||
d3632d41 UW |
2343 | (define_insn "*extendqidi2" |
2344 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2345 | (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))] | |
2346 | "TARGET_64BIT && TARGET_LONG_DISPLACEMENT" | |
d40c829f | 2347 | "lgb\t%0,%1" |
d3632d41 UW |
2348 | [(set_attr "op_type" "RXY")]) |
2349 | ||
4023fb28 UW |
2350 | (define_split |
2351 | [(set (match_operand:DI 0 "register_operand" "") | |
2352 | (sign_extend:DI (match_operand:QI 1 "s_operand" "")))] | |
d3632d41 | 2353 | "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT && !reload_completed" |
4023fb28 | 2354 | [(parallel |
10bbf137 | 2355 | [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2356 | (clobber (reg:CC 33))]) |
2357 | (parallel | |
2358 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56))) | |
2359 | (clobber (reg:CC 33))])] | |
2360 | "") | |
9db1d521 HP |
2361 | |
2362 | ; | |
2363 | ; extendhisi2 instruction pattern(s). | |
2364 | ; | |
2365 | ||
4023fb28 UW |
2366 | (define_expand "extendhisi2" |
2367 | [(set (match_operand:SI 0 "register_operand" "") | |
2368 | (sign_extend:SI (match_operand:HI 1 "register_operand" "")))] | |
9db1d521 | 2369 | "" |
4023fb28 UW |
2370 | " |
2371 | { | |
2372 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2373 | emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16))); | |
c7453384 | 2374 | emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16))); |
4023fb28 UW |
2375 | DONE; |
2376 | } | |
2377 | ") | |
9db1d521 | 2378 | |
4023fb28 | 2379 | (define_insn "*extendhisi2" |
d3632d41 UW |
2380 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
2381 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
4023fb28 | 2382 | "" |
d3632d41 | 2383 | "@ |
d40c829f UW |
2384 | lh\t%0,%1 |
2385 | lhy\t%0,%1" | |
d3632d41 | 2386 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 HP |
2387 | |
2388 | ; | |
2389 | ; extendqisi2 instruction pattern(s). | |
2390 | ; | |
2391 | ||
4023fb28 UW |
2392 | (define_expand "extendqisi2" |
2393 | [(set (match_operand:SI 0 "register_operand" "") | |
2394 | (sign_extend:SI (match_operand:QI 1 "register_operand" "")))] | |
9db1d521 | 2395 | "" |
4023fb28 UW |
2396 | " |
2397 | { | |
2398 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2399 | emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24))); | |
c7453384 | 2400 | emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24))); |
4023fb28 UW |
2401 | DONE; |
2402 | } | |
2403 | ") | |
9db1d521 | 2404 | |
d3632d41 UW |
2405 | (define_insn "*extendqisi2" |
2406 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2407 | (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2408 | "TARGET_LONG_DISPLACEMENT" |
d40c829f | 2409 | "lb\t%0,%1" |
d3632d41 UW |
2410 | [(set_attr "op_type" "RXY")]) |
2411 | ||
4023fb28 UW |
2412 | (define_split |
2413 | [(set (match_operand:SI 0 "register_operand" "") | |
2414 | (sign_extend:SI (match_operand:QI 1 "s_operand" "")))] | |
9e8327e3 | 2415 | "!TARGET_LONG_DISPLACEMENT && !reload_completed" |
4023fb28 | 2416 | [(parallel |
10bbf137 | 2417 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2418 | (clobber (reg:CC 33))]) |
2419 | (parallel | |
2420 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24))) | |
2421 | (clobber (reg:CC 33))])] | |
2422 | "") | |
9db1d521 HP |
2423 | |
2424 | ; | |
2425 | ; extendqihi2 instruction pattern(s). | |
2426 | ; | |
2427 | ||
9db1d521 HP |
2428 | |
2429 | ; | |
2430 | ; zero_extendsidi2 instruction pattern(s). | |
2431 | ; | |
2432 | ||
4023fb28 UW |
2433 | (define_expand "zero_extendsidi2" |
2434 | [(set (match_operand:DI 0 "register_operand" "") | |
2435 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2436 | "" | |
2437 | " | |
2438 | { | |
2439 | if (!TARGET_64BIT) | |
2440 | { | |
9f37ccb1 UW |
2441 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2442 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); | |
2443 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
2444 | DONE; |
2445 | } | |
2446 | } | |
2447 | ") | |
2448 | ||
2449 | (define_insn "*zero_extendsidi2" | |
9db1d521 HP |
2450 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2451 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2452 | "TARGET_64BIT" | |
2453 | "@ | |
d40c829f UW |
2454 | llgfr\t%0,%1 |
2455 | llgf\t%0,%1" | |
d3632d41 | 2456 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2457 | |
9db1d521 HP |
2458 | ; |
2459 | ; zero_extendhidi2 instruction pattern(s). | |
2460 | ; | |
2461 | ||
4023fb28 UW |
2462 | (define_expand "zero_extendhidi2" |
2463 | [(set (match_operand:DI 0 "register_operand" "") | |
2464 | (zero_extend:DI (match_operand:HI 1 "register_operand" "")))] | |
2465 | "" | |
2466 | " | |
2467 | { | |
2468 | if (!TARGET_64BIT) | |
2469 | { | |
2470 | rtx tmp = gen_reg_rtx (SImode); | |
2471 | emit_insn (gen_zero_extendhisi2 (tmp, operands[1])); | |
2472 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
2473 | DONE; | |
2474 | } | |
2475 | else | |
2476 | { | |
2477 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2478 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); | |
c7453384 | 2479 | emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48))); |
4023fb28 UW |
2480 | DONE; |
2481 | } | |
2482 | } | |
2483 | ") | |
9db1d521 | 2484 | |
4023fb28 UW |
2485 | (define_insn "*zero_extendhidi2" |
2486 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2487 | (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))] | |
9db1d521 | 2488 | "TARGET_64BIT" |
d40c829f | 2489 | "llgh\t%0,%1" |
d3632d41 | 2490 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2491 | |
288e517f AK |
2492 | ; |
2493 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
2494 | ; | |
2495 | ||
2496 | (define_insn "*llgt_sisi" | |
2497 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
2498 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m") | |
2499 | (const_int 2147483647)))] | |
2500 | "TARGET_64BIT" | |
2501 | "@ | |
2502 | llgtr\t%0,%1 | |
2503 | llgt\t%0,%1" | |
2504 | [(set_attr "op_type" "RRE,RXE")]) | |
2505 | ||
2506 | (define_insn_and_split "*llgt_sisi_split" | |
2507 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
2508 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m") | |
2509 | (const_int 2147483647))) | |
2510 | (clobber (reg:CC 33))] | |
2511 | "TARGET_64BIT" | |
2512 | "#" | |
2513 | "&& reload_completed" | |
2514 | [(set (match_dup 0) | |
2515 | (and:SI (match_dup 1) | |
2516 | (const_int 2147483647)))] | |
2517 | "") | |
2518 | ||
2519 | (define_insn "*llgt_didi" | |
2520 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2521 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
2522 | (const_int 2147483647)))] | |
2523 | "TARGET_64BIT" | |
2524 | "@ | |
2525 | llgtr\t%0,%1 | |
2526 | llgt\t%0,%N1" | |
2527 | [(set_attr "op_type" "RRE,RXE")]) | |
2528 | ||
2529 | (define_insn_and_split "*llgt_didi_split" | |
2530 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2531 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
2532 | (const_int 2147483647))) | |
2533 | (clobber (reg:CC 33))] | |
2534 | "TARGET_64BIT" | |
2535 | "#" | |
2536 | "&& reload_completed" | |
2537 | [(set (match_dup 0) | |
2538 | (and:DI (match_dup 1) | |
2539 | (const_int 2147483647)))] | |
2540 | "") | |
2541 | ||
2542 | (define_insn "*llgt_sidi" | |
2543 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2544 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) | |
2545 | (const_int 2147483647)))] | |
2546 | "TARGET_64BIT" | |
2547 | "llgt\t%0,%1" | |
2548 | [(set_attr "op_type" "RXE")]) | |
2549 | ||
2550 | (define_insn_and_split "*llgt_sidi_split" | |
2551 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2552 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) | |
2553 | (const_int 2147483647))) | |
2554 | (clobber (reg:CC 33))] | |
2555 | "TARGET_64BIT" | |
2556 | "#" | |
2557 | "&& reload_completed" | |
2558 | [(set (match_dup 0) | |
2559 | (and:DI (subreg:DI (match_dup 1) 0) | |
2560 | (const_int 2147483647)))] | |
2561 | "") | |
2562 | ||
9db1d521 | 2563 | ; |
4023fb28 | 2564 | ; zero_extendqidi2 instruction pattern(s) |
9db1d521 HP |
2565 | ; |
2566 | ||
4023fb28 UW |
2567 | (define_expand "zero_extendqidi2" |
2568 | [(set (match_operand:DI 0 "register_operand" "") | |
2569 | (zero_extend:DI (match_operand:QI 1 "register_operand" "")))] | |
9db1d521 HP |
2570 | "" |
2571 | " | |
2572 | { | |
2573 | if (!TARGET_64BIT) | |
2574 | { | |
4023fb28 UW |
2575 | rtx tmp = gen_reg_rtx (SImode); |
2576 | emit_insn (gen_zero_extendqisi2 (tmp, operands[1])); | |
2577 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
9db1d521 HP |
2578 | DONE; |
2579 | } | |
4023fb28 UW |
2580 | else |
2581 | { | |
2582 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2583 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); | |
c7453384 | 2584 | emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56))); |
4023fb28 UW |
2585 | DONE; |
2586 | } | |
2587 | } | |
2588 | ") | |
9db1d521 | 2589 | |
4023fb28 UW |
2590 | (define_insn "*zero_extendqidi2" |
2591 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2592 | (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))] | |
9db1d521 | 2593 | "TARGET_64BIT" |
d40c829f | 2594 | "llgc\t%0,%1" |
d3632d41 | 2595 | [(set_attr "op_type" "RXY")]) |
9db1d521 HP |
2596 | |
2597 | ; | |
4023fb28 | 2598 | ; zero_extendhisi2 instruction pattern(s). |
9db1d521 HP |
2599 | ; |
2600 | ||
4023fb28 UW |
2601 | (define_expand "zero_extendhisi2" |
2602 | [(set (match_operand:SI 0 "register_operand" "") | |
2603 | (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] | |
9db1d521 | 2604 | "" |
4023fb28 UW |
2605 | " |
2606 | { | |
2607 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2608 | emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff))); | |
2609 | DONE; | |
2610 | } | |
2611 | ") | |
9db1d521 | 2612 | |
4023fb28 | 2613 | (define_insn "*zero_extendhisi2_64" |
9db1d521 | 2614 | [(set (match_operand:SI 0 "register_operand" "=d") |
4023fb28 | 2615 | (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] |
9db1d521 | 2616 | "TARGET_64BIT" |
d40c829f | 2617 | "llgh\t%0,%1" |
d3632d41 | 2618 | [(set_attr "op_type" "RXY")]) |
cc7ab9b7 UW |
2619 | |
2620 | (define_insn_and_split "*zero_extendhisi2_31" | |
2621 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 2622 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
cc7ab9b7 UW |
2623 | (clobber (reg:CC 33))] |
2624 | "!TARGET_64BIT" | |
2625 | "#" | |
2626 | "&& reload_completed" | |
2627 | [(set (match_dup 0) (const_int 0)) | |
2628 | (parallel | |
2629 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
2630 | (clobber (reg:CC 33))])] | |
2631 | "operands[2] = gen_lowpart (HImode, operands[0]);" | |
0796c16a | 2632 | [(set_attr "atype" "agen")]) |
c7453384 | 2633 | |
4023fb28 UW |
2634 | ; |
2635 | ; zero_extendqisi2 instruction pattern(s). | |
2636 | ; | |
9db1d521 HP |
2637 | |
2638 | (define_expand "zero_extendqisi2" | |
2639 | [(set (match_operand:SI 0 "register_operand" "") | |
4023fb28 | 2640 | (zero_extend:SI (match_operand:QI 1 "register_operand" "")))] |
9db1d521 HP |
2641 | "" |
2642 | " | |
2643 | { | |
4023fb28 UW |
2644 | operands[1] = gen_lowpart (SImode, operands[1]); |
2645 | emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff))); | |
2646 | DONE; | |
2647 | } | |
2648 | ") | |
9db1d521 | 2649 | |
4023fb28 UW |
2650 | (define_insn "*zero_extendqisi2_64" |
2651 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2652 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2653 | "TARGET_ZARCH" |
d40c829f | 2654 | "llgc\t%0,%1" |
d3632d41 | 2655 | [(set_attr "op_type" "RXY")]) |
cc7ab9b7 UW |
2656 | |
2657 | (define_insn_and_split "*zero_extendqisi2_31" | |
2658 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
2659 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2660 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2661 | "#" |
2662 | "&& reload_completed" | |
2663 | [(set (match_dup 0) (const_int 0)) | |
2664 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
2665 | "operands[2] = gen_lowpart (QImode, operands[0]);" | |
0796c16a | 2666 | [(set_attr "atype" "agen")]) |
c7453384 | 2667 | |
9db1d521 HP |
2668 | ; |
2669 | ; zero_extendqihi2 instruction pattern(s). | |
2670 | ; | |
2671 | ||
9db1d521 HP |
2672 | (define_expand "zero_extendqihi2" |
2673 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 2674 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
9e8327e3 | 2675 | "TARGET_ZARCH" |
9db1d521 HP |
2676 | " |
2677 | { | |
4023fb28 UW |
2678 | operands[1] = gen_lowpart (HImode, operands[1]); |
2679 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
2680 | DONE; | |
2681 | } | |
2682 | ") | |
9db1d521 | 2683 | |
4023fb28 | 2684 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 2685 | [(set (match_operand:HI 0 "register_operand" "=d") |
cc7ab9b7 | 2686 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] |
9e8327e3 | 2687 | "TARGET_ZARCH" |
d40c829f | 2688 | "llgc\t%0,%1" |
d3632d41 | 2689 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2690 | |
cc7ab9b7 UW |
2691 | (define_insn_and_split "*zero_extendqihi2_31" |
2692 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
2693 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2694 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2695 | "#" |
2696 | "&& reload_completed" | |
2697 | [(set (match_dup 0) (const_int 0)) | |
2698 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
2699 | "operands[2] = gen_lowpart (QImode, operands[0]);" | |
0796c16a | 2700 | [(set_attr "atype" "agen")]) |
cc7ab9b7 UW |
2701 | |
2702 | ||
9db1d521 HP |
2703 | ; |
2704 | ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s). | |
2705 | ; | |
2706 | ||
2707 | (define_expand "fixuns_truncdfdi2" | |
2708 | [(set (match_operand:DI 0 "register_operand" "") | |
2709 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))] | |
2710 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2711 | { |
2712 | rtx label1 = gen_label_rtx (); | |
2713 | rtx label2 = gen_label_rtx (); | |
2714 | rtx temp = gen_reg_rtx (DFmode); | |
2715 | operands[1] = force_reg (DFmode, operands[1]); | |
2716 | ||
c7453384 | 2717 | emit_insn (gen_cmpdf (operands[1], |
4023fb28 | 2718 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 2719 | REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode))); |
9db1d521 | 2720 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
2721 | emit_insn (gen_subdf3 (temp, operands[1], |
2722 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2723 | REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode))); |
9db1d521 | 2724 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7))); |
f314b9b1 | 2725 | emit_jump (label2); |
9db1d521 HP |
2726 | |
2727 | emit_label (label1); | |
2728 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2729 | emit_label (label2); | |
2730 | DONE; | |
10bbf137 | 2731 | }) |
9db1d521 HP |
2732 | |
2733 | (define_expand "fix_truncdfdi2" | |
2734 | [(set (match_operand:DI 0 "register_operand" "") | |
2735 | (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
2736 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2737 | { |
2738 | operands[1] = force_reg (DFmode, operands[1]); | |
2739 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2740 | DONE; | |
10bbf137 | 2741 | }) |
9db1d521 HP |
2742 | |
2743 | (define_insn "fix_truncdfdi2_ieee" | |
2744 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2745 | (fix:DI (match_operand:DF 1 "register_operand" "f"))) | |
10bbf137 | 2746 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2747 | (clobber (reg:CC 33))] |
2748 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2749 | "cgdbr\t%0,%h2,%1" |
9db1d521 | 2750 | [(set_attr "op_type" "RRE") |
077dab3b | 2751 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
2752 | |
2753 | ; | |
2754 | ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s). | |
2755 | ; | |
2756 | ||
2757 | (define_expand "fixuns_truncdfsi2" | |
2758 | [(set (match_operand:SI 0 "register_operand" "") | |
2759 | (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))] | |
2760 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2761 | { |
2762 | rtx label1 = gen_label_rtx (); | |
2763 | rtx label2 = gen_label_rtx (); | |
2764 | rtx temp = gen_reg_rtx (DFmode); | |
2765 | ||
2766 | operands[1] = force_reg (DFmode,operands[1]); | |
c7453384 | 2767 | emit_insn (gen_cmpdf (operands[1], |
4023fb28 | 2768 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 2769 | REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode))); |
9db1d521 | 2770 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
2771 | emit_insn (gen_subdf3 (temp, operands[1], |
2772 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2773 | REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode))); |
9db1d521 | 2774 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7))); |
f314b9b1 | 2775 | emit_jump (label2); |
9db1d521 HP |
2776 | |
2777 | emit_label (label1); | |
2778 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2779 | emit_label (label2); | |
2780 | DONE; | |
10bbf137 | 2781 | }) |
9db1d521 HP |
2782 | |
2783 | (define_expand "fix_truncdfsi2" | |
2784 | [(set (match_operand:SI 0 "register_operand" "") | |
2785 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
2786 | "TARGET_HARD_FLOAT" | |
9db1d521 | 2787 | { |
c7453384 | 2788 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
2789 | { |
2790 | /* This is the algorithm from POP chapter A.5.7.2. */ | |
2791 | ||
c19ec8f9 | 2792 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
4023fb28 UW |
2793 | rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000); |
2794 | rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000); | |
9db1d521 HP |
2795 | |
2796 | operands[1] = force_reg (DFmode, operands[1]); | |
c7453384 | 2797 | emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1], |
9db1d521 | 2798 | two31r, two32, temp)); |
c7453384 EC |
2799 | } |
2800 | else | |
9db1d521 HP |
2801 | { |
2802 | operands[1] = force_reg (DFmode, operands[1]); | |
2803 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2804 | } | |
2805 | ||
2806 | DONE; | |
10bbf137 | 2807 | }) |
9db1d521 HP |
2808 | |
2809 | (define_insn "fix_truncdfsi2_ieee" | |
2810 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2811 | (fix:SI (match_operand:DF 1 "register_operand" "f"))) | |
10bbf137 | 2812 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2813 | (clobber (reg:CC 33))] |
2814 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2815 | "cfdbr\t%0,%h2,%1" |
9db1d521 | 2816 | [(set_attr "op_type" "RRE") |
4023fb28 | 2817 | (set_attr "type" "other" )]) |
9db1d521 HP |
2818 | |
2819 | (define_insn "fix_truncdfsi2_ibm" | |
2820 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2821 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f"))) | |
4023fb28 UW |
2822 | (use (match_operand:DI 2 "immediate_operand" "m")) |
2823 | (use (match_operand:DI 3 "immediate_operand" "m")) | |
9db1d521 HP |
2824 | (use (match_operand:BLK 4 "memory_operand" "m")) |
2825 | (clobber (reg:CC 33))] | |
2826 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
9db1d521 | 2827 | { |
d40c829f UW |
2828 | output_asm_insn ("sd\t%1,%2", operands); |
2829 | output_asm_insn ("aw\t%1,%3", operands); | |
2830 | output_asm_insn ("std\t%1,%4", operands); | |
2831 | output_asm_insn ("xi\t%N4,128", operands); | |
2832 | return "l\t%0,%N4"; | |
10bbf137 | 2833 | } |
9db1d521 | 2834 | [(set_attr "op_type" "NN") |
077dab3b HP |
2835 | (set_attr "type" "ftoi") |
2836 | (set_attr "atype" "agen") | |
9db1d521 HP |
2837 | (set_attr "length" "20")]) |
2838 | ||
2839 | ; | |
2840 | ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s). | |
2841 | ; | |
2842 | ||
2843 | (define_expand "fixuns_truncsfdi2" | |
2844 | [(set (match_operand:DI 0 "register_operand" "") | |
2845 | (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))] | |
2846 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2847 | { |
2848 | rtx label1 = gen_label_rtx (); | |
2849 | rtx label2 = gen_label_rtx (); | |
2850 | rtx temp = gen_reg_rtx (SFmode); | |
2851 | ||
2852 | operands[1] = force_reg (SFmode, operands[1]); | |
c7453384 | 2853 | emit_insn (gen_cmpsf (operands[1], |
4023fb28 | 2854 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 2855 | REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode))); |
9db1d521 HP |
2856 | emit_jump_insn (gen_blt (label1)); |
2857 | ||
4023fb28 UW |
2858 | emit_insn (gen_subsf3 (temp, operands[1], |
2859 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2860 | REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode))); |
9db1d521 | 2861 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7))); |
f314b9b1 | 2862 | emit_jump (label2); |
9db1d521 HP |
2863 | |
2864 | emit_label (label1); | |
2865 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2866 | emit_label (label2); | |
2867 | DONE; | |
10bbf137 | 2868 | }) |
9db1d521 HP |
2869 | |
2870 | (define_expand "fix_truncsfdi2" | |
2871 | [(set (match_operand:DI 0 "register_operand" "") | |
2872 | (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
2873 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2874 | { |
2875 | operands[1] = force_reg (SFmode, operands[1]); | |
2876 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2877 | DONE; | |
10bbf137 | 2878 | }) |
9db1d521 HP |
2879 | |
2880 | (define_insn "fix_truncsfdi2_ieee" | |
2881 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2882 | (fix:DI (match_operand:SF 1 "register_operand" "f"))) | |
10bbf137 | 2883 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2884 | (clobber (reg:CC 33))] |
2885 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2886 | "cgebr\t%0,%h2,%1" |
9db1d521 | 2887 | [(set_attr "op_type" "RRE") |
077dab3b | 2888 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
2889 | |
2890 | ; | |
2891 | ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s). | |
2892 | ; | |
2893 | ||
2894 | (define_expand "fixuns_truncsfsi2" | |
2895 | [(set (match_operand:SI 0 "register_operand" "") | |
2896 | (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))] | |
2897 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2898 | { |
2899 | rtx label1 = gen_label_rtx (); | |
2900 | rtx label2 = gen_label_rtx (); | |
2901 | rtx temp = gen_reg_rtx (SFmode); | |
2902 | ||
2903 | operands[1] = force_reg (SFmode, operands[1]); | |
4023fb28 UW |
2904 | emit_insn (gen_cmpsf (operands[1], |
2905 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2906 | REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode))); |
9db1d521 | 2907 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
2908 | emit_insn (gen_subsf3 (temp, operands[1], |
2909 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2910 | REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode))); |
9db1d521 | 2911 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7))); |
f314b9b1 | 2912 | emit_jump (label2); |
9db1d521 HP |
2913 | |
2914 | emit_label (label1); | |
2915 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2916 | emit_label (label2); | |
2917 | DONE; | |
10bbf137 | 2918 | }) |
9db1d521 HP |
2919 | |
2920 | (define_expand "fix_truncsfsi2" | |
2921 | [(set (match_operand:SI 0 "register_operand" "") | |
2922 | (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
2923 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
2924 | { |
2925 | if (TARGET_IBM_FLOAT) | |
2926 | { | |
2927 | /* Convert to DFmode and then use the POP algorithm. */ | |
2928 | rtx temp = gen_reg_rtx (DFmode); | |
2929 | emit_insn (gen_extendsfdf2 (temp, operands[1])); | |
2930 | emit_insn (gen_fix_truncdfsi2 (operands[0], temp)); | |
2931 | } | |
2932 | else | |
2933 | { | |
2934 | operands[1] = force_reg (SFmode, operands[1]); | |
2935 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2936 | } | |
2937 | ||
2938 | DONE; | |
10bbf137 | 2939 | }) |
9db1d521 HP |
2940 | |
2941 | (define_insn "fix_truncsfsi2_ieee" | |
2942 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2943 | (fix:SI (match_operand:SF 1 "register_operand" "f"))) | |
10bbf137 | 2944 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2945 | (clobber (reg:CC 33))] |
2946 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2947 | "cfebr\t%0,%h2,%1" |
9db1d521 | 2948 | [(set_attr "op_type" "RRE") |
077dab3b | 2949 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
2950 | |
2951 | ; | |
2952 | ; floatdidf2 instruction pattern(s). | |
2953 | ; | |
2954 | ||
2955 | (define_insn "floatdidf2" | |
2956 | [(set (match_operand:DF 0 "register_operand" "=f") | |
4023fb28 UW |
2957 | (float:DF (match_operand:DI 1 "register_operand" "d"))) |
2958 | (clobber (reg:CC 33))] | |
9db1d521 | 2959 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 2960 | "cdgbr\t%0,%1" |
9db1d521 | 2961 | [(set_attr "op_type" "RRE") |
f0bf1270 | 2962 | (set_attr "type" "itof" )]) |
9db1d521 HP |
2963 | |
2964 | ; | |
2965 | ; floatdisf2 instruction pattern(s). | |
2966 | ; | |
2967 | ||
2968 | (define_insn "floatdisf2" | |
2969 | [(set (match_operand:SF 0 "register_operand" "=f") | |
4023fb28 UW |
2970 | (float:SF (match_operand:DI 1 "register_operand" "d"))) |
2971 | (clobber (reg:CC 33))] | |
9db1d521 | 2972 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 2973 | "cegbr\t%0,%1" |
9db1d521 | 2974 | [(set_attr "op_type" "RRE") |
077dab3b | 2975 | (set_attr "type" "itof" )]) |
9db1d521 HP |
2976 | |
2977 | ; | |
2978 | ; floatsidf2 instruction pattern(s). | |
2979 | ; | |
2980 | ||
2981 | (define_expand "floatsidf2" | |
4023fb28 UW |
2982 | [(parallel |
2983 | [(set (match_operand:DF 0 "register_operand" "") | |
2984 | (float:DF (match_operand:SI 1 "register_operand" ""))) | |
2985 | (clobber (reg:CC 33))])] | |
9db1d521 | 2986 | "TARGET_HARD_FLOAT" |
9db1d521 | 2987 | { |
c7453384 | 2988 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
2989 | { |
2990 | /* This is the algorithm from POP chapter A.5.7.1. */ | |
2991 | ||
c19ec8f9 | 2992 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
c7453384 | 2993 | rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000); |
9db1d521 HP |
2994 | |
2995 | emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp)); | |
2996 | DONE; | |
2997 | } | |
10bbf137 | 2998 | }) |
9db1d521 HP |
2999 | |
3000 | (define_insn "floatsidf2_ieee" | |
3001 | [(set (match_operand:DF 0 "register_operand" "=f") | |
4023fb28 UW |
3002 | (float:DF (match_operand:SI 1 "register_operand" "d"))) |
3003 | (clobber (reg:CC 33))] | |
9db1d521 | 3004 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3005 | "cdfbr\t%0,%1" |
9db1d521 | 3006 | [(set_attr "op_type" "RRE") |
077dab3b | 3007 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3008 | |
3009 | (define_insn "floatsidf2_ibm" | |
3010 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3011 | (float:DF (match_operand:SI 1 "register_operand" "d"))) | |
4023fb28 | 3012 | (use (match_operand:DI 2 "immediate_operand" "m")) |
9db1d521 HP |
3013 | (use (match_operand:BLK 3 "memory_operand" "m")) |
3014 | (clobber (reg:CC 33))] | |
3015 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
9db1d521 | 3016 | { |
d40c829f UW |
3017 | output_asm_insn ("st\t%1,%N3", operands); |
3018 | output_asm_insn ("xi\t%N3,128", operands); | |
3019 | output_asm_insn ("mvc\t%O3(4,%R3),%2", operands); | |
3020 | output_asm_insn ("ld\t%0,%3", operands); | |
3021 | return "sd\t%0,%2"; | |
10bbf137 | 3022 | } |
9db1d521 | 3023 | [(set_attr "op_type" "NN") |
4023fb28 | 3024 | (set_attr "type" "other" ) |
077dab3b | 3025 | (set_attr "atype" "agen") |
9db1d521 HP |
3026 | (set_attr "length" "20")]) |
3027 | ||
3028 | ; | |
3029 | ; floatsisf2 instruction pattern(s). | |
3030 | ; | |
3031 | ||
3032 | (define_expand "floatsisf2" | |
4023fb28 UW |
3033 | [(parallel |
3034 | [(set (match_operand:SF 0 "register_operand" "") | |
3035 | (float:SF (match_operand:SI 1 "register_operand" ""))) | |
3036 | (clobber (reg:CC 33))])] | |
9db1d521 | 3037 | "TARGET_HARD_FLOAT" |
9db1d521 HP |
3038 | { |
3039 | if (TARGET_IBM_FLOAT) | |
3040 | { | |
3041 | /* Use the POP algorithm to convert to DFmode and then truncate. */ | |
3042 | rtx temp = gen_reg_rtx (DFmode); | |
3043 | emit_insn (gen_floatsidf2 (temp, operands[1])); | |
3044 | emit_insn (gen_truncdfsf2 (operands[0], temp)); | |
3045 | DONE; | |
3046 | } | |
10bbf137 | 3047 | }) |
9db1d521 HP |
3048 | |
3049 | (define_insn "floatsisf2_ieee" | |
3050 | [(set (match_operand:SF 0 "register_operand" "=f") | |
4023fb28 UW |
3051 | (float:SF (match_operand:SI 1 "register_operand" "d"))) |
3052 | (clobber (reg:CC 33))] | |
9db1d521 | 3053 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3054 | "cefbr\t%0,%1" |
9db1d521 | 3055 | [(set_attr "op_type" "RRE") |
077dab3b | 3056 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3057 | |
3058 | ; | |
3059 | ; truncdfsf2 instruction pattern(s). | |
3060 | ; | |
3061 | ||
3062 | (define_expand "truncdfsf2" | |
3063 | [(set (match_operand:SF 0 "register_operand" "") | |
3064 | (float_truncate:SF (match_operand:DF 1 "general_operand" "")))] | |
3065 | "TARGET_HARD_FLOAT" | |
4023fb28 | 3066 | "") |
9db1d521 HP |
3067 | |
3068 | (define_insn "truncdfsf2_ieee" | |
3069 | [(set (match_operand:SF 0 "register_operand" "=f") | |
4023fb28 | 3070 | (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))] |
9db1d521 | 3071 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3072 | "ledbr\t%0,%1" |
ce50cae8 | 3073 | [(set_attr "op_type" "RRE")]) |
9db1d521 HP |
3074 | |
3075 | (define_insn "truncdfsf2_ibm" | |
3076 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
d3632d41 | 3077 | (float_truncate:SF (match_operand:DF 1 "general_operand" "f,R")))] |
9db1d521 HP |
3078 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
3079 | "@ | |
d40c829f UW |
3080 | lrer\t%0,%1 |
3081 | le\t%0,%1" | |
4023fb28 | 3082 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3083 | (set_attr "type" "floads,floads")]) |
9db1d521 HP |
3084 | |
3085 | ; | |
3086 | ; extendsfdf2 instruction pattern(s). | |
3087 | ; | |
3088 | ||
3089 | (define_expand "extendsfdf2" | |
3090 | [(set (match_operand:DF 0 "register_operand" "") | |
3091 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] | |
3092 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
3093 | { |
3094 | if (TARGET_IBM_FLOAT) | |
3095 | { | |
3096 | emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1])); | |
3097 | DONE; | |
3098 | } | |
10bbf137 | 3099 | }) |
9db1d521 HP |
3100 | |
3101 | (define_insn "extendsfdf2_ieee" | |
3102 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 3103 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))] |
9db1d521 HP |
3104 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3105 | "@ | |
d40c829f UW |
3106 | ldebr\t%0,%1 |
3107 | ldeb\t%0,%1" | |
077dab3b HP |
3108 | [(set_attr "op_type" "RRE,RXE") |
3109 | (set_attr "type" "floads,floads")]) | |
9db1d521 HP |
3110 | |
3111 | (define_insn "extendsfdf2_ibm" | |
3112 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 3113 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R"))) |
9db1d521 HP |
3114 | (clobber (reg:CC 33))] |
3115 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3116 | "@ | |
d40c829f UW |
3117 | sdr\t%0,%0\;ler\t%0,%1 |
3118 | sdr\t%0,%0\;le\t%0,%1" | |
077dab3b HP |
3119 | [(set_attr "op_type" "NN,NN") |
3120 | (set_attr "atype" "reg,agen") | |
3121 | (set_attr "length" "4,6") | |
c7453384 | 3122 | (set_attr "type" "o2,o2")]) |
9db1d521 HP |
3123 | |
3124 | ||
3125 | ;; | |
fae778eb | 3126 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 3127 | ;; |
fae778eb | 3128 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
3129 | ; because of unpredictable Bits in Register for Halfword and Byte |
3130 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
3131 | ||
07893d4f UW |
3132 | ;; |
3133 | ;;- Add instructions. | |
3134 | ;; | |
3135 | ||
3136 | ; | |
3137 | ; adddi3 instruction pattern(s). | |
3138 | ; | |
3139 | ||
07893d4f UW |
3140 | (define_insn "*adddi3_sign" |
3141 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3142 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3143 | (match_operand:DI 1 "register_operand" "0,0"))) | |
3144 | (clobber (reg:CC 33))] | |
3145 | "TARGET_64BIT" | |
3146 | "@ | |
d40c829f UW |
3147 | agfr\t%0,%2 |
3148 | agf\t%0,%2" | |
d3632d41 | 3149 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3150 | |
3151 | (define_insn "*adddi3_zero_cc" | |
c7453384 | 3152 | [(set (reg 33) |
07893d4f UW |
3153 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3154 | (match_operand:DI 1 "register_operand" "0,0")) | |
3155 | (const_int 0))) | |
3156 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3157 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
3158 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3159 | "@ | |
d40c829f UW |
3160 | algfr\t%0,%2 |
3161 | algf\t%0,%2" | |
d3632d41 | 3162 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3163 | |
3164 | (define_insn "*adddi3_zero_cconly" | |
c7453384 | 3165 | [(set (reg 33) |
07893d4f UW |
3166 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3167 | (match_operand:DI 1 "register_operand" "0,0")) | |
3168 | (const_int 0))) | |
3169 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3170 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3171 | "@ | |
d40c829f UW |
3172 | algfr\t%0,%2 |
3173 | algf\t%0,%2" | |
d3632d41 | 3174 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3175 | |
3176 | (define_insn "*adddi3_zero" | |
3177 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3178 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3179 | (match_operand:DI 1 "register_operand" "0,0"))) | |
3180 | (clobber (reg:CC 33))] | |
3181 | "TARGET_64BIT" | |
3182 | "@ | |
d40c829f UW |
3183 | algfr\t%0,%2 |
3184 | algf\t%0,%2" | |
d3632d41 | 3185 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3186 | |
0a3bdf9d | 3187 | (define_insn "*adddi3_imm_cc" |
c7453384 | 3188 | [(set (reg 33) |
0a3bdf9d UW |
3189 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0") |
3190 | (match_operand:DI 2 "const_int_operand" "K")) | |
3191 | (const_int 0))) | |
3192 | (set (match_operand:DI 0 "register_operand" "=d") | |
3193 | (plus:DI (match_dup 1) (match_dup 2)))] | |
c7453384 EC |
3194 | "TARGET_64BIT |
3195 | && s390_match_ccmode (insn, CCAmode) | |
0a3bdf9d | 3196 | && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')" |
d40c829f | 3197 | "aghi\t%0,%h2" |
077dab3b | 3198 | [(set_attr "op_type" "RI")]) |
0a3bdf9d | 3199 | |
b2ba71ca UW |
3200 | (define_insn "*adddi3_carry1_cc" |
3201 | [(set (reg 33) | |
3202 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3203 | (match_operand:DI 2 "general_operand" "d,m")) | |
3204 | (match_dup 1))) | |
3205 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3206 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3207 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3208 | "@ | |
3209 | algr\t%0,%2 | |
3210 | alg\t%0,%2" | |
3211 | [(set_attr "op_type" "RRE,RXY")]) | |
3212 | ||
3213 | (define_insn "*adddi3_carry1_cconly" | |
3214 | [(set (reg 33) | |
3215 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3216 | (match_operand:DI 2 "general_operand" "d,m")) | |
3217 | (match_dup 1))) | |
3218 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3219 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3220 | "@ | |
3221 | algr\t%0,%2 | |
3222 | alg\t%0,%2" | |
3223 | [(set_attr "op_type" "RRE,RXY")]) | |
3224 | ||
3225 | (define_insn "*adddi3_carry2_cc" | |
3226 | [(set (reg 33) | |
3227 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3228 | (match_operand:DI 2 "general_operand" "d,m")) | |
3229 | (match_dup 2))) | |
3230 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3231 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3232 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3233 | "@ | |
3234 | algr\t%0,%2 | |
3235 | alg\t%0,%2" | |
3236 | [(set_attr "op_type" "RRE,RXY")]) | |
3237 | ||
3238 | (define_insn "*adddi3_carry2_cconly" | |
3239 | [(set (reg 33) | |
3240 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3241 | (match_operand:DI 2 "general_operand" "d,m")) | |
3242 | (match_dup 2))) | |
3243 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3244 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3245 | "@ | |
3246 | algr\t%0,%2 | |
3247 | alg\t%0,%2" | |
3248 | [(set_attr "op_type" "RRE,RXY")]) | |
3249 | ||
07893d4f | 3250 | (define_insn "*adddi3_cc" |
c7453384 | 3251 | [(set (reg 33) |
96fd3851 | 3252 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3253 | (match_operand:DI 2 "general_operand" "d,m")) |
3254 | (const_int 0))) | |
3255 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3256 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3257 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3258 | "@ | |
d40c829f UW |
3259 | algr\t%0,%2 |
3260 | alg\t%0,%2" | |
d3632d41 | 3261 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3262 | |
07893d4f | 3263 | (define_insn "*adddi3_cconly" |
c7453384 | 3264 | [(set (reg 33) |
96fd3851 | 3265 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3266 | (match_operand:DI 2 "general_operand" "d,m")) |
3267 | (const_int 0))) | |
3268 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3269 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3270 | "@ | |
d40c829f UW |
3271 | algr\t%0,%2 |
3272 | alg\t%0,%2" | |
d3632d41 | 3273 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3274 | |
07893d4f | 3275 | (define_insn "*adddi3_cconly2" |
c7453384 | 3276 | [(set (reg 33) |
96fd3851 | 3277 | (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3278 | (neg:SI (match_operand:DI 2 "general_operand" "d,m")))) |
3279 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3280 | "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT" | |
9db1d521 | 3281 | "@ |
d40c829f UW |
3282 | algr\t%0,%2 |
3283 | alg\t%0,%2" | |
d3632d41 | 3284 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3285 | |
07893d4f | 3286 | (define_insn "*adddi3_64" |
9db1d521 | 3287 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
96fd3851 | 3288 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
9db1d521 HP |
3289 | (match_operand:DI 2 "general_operand" "d,K,m") ) ) |
3290 | (clobber (reg:CC 33))] | |
3291 | "TARGET_64BIT" | |
3292 | "@ | |
d40c829f UW |
3293 | agr\t%0,%2 |
3294 | aghi\t%0,%h2 | |
3295 | ag\t%0,%2" | |
d3632d41 | 3296 | [(set_attr "op_type" "RRE,RI,RXY")]) |
9db1d521 | 3297 | |
e69166de UW |
3298 | (define_insn_and_split "*adddi3_31z" |
3299 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3300 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") | |
3301 | (match_operand:DI 2 "general_operand" "do") ) ) | |
3302 | (clobber (reg:CC 33))] | |
3303 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
3304 | "#" | |
3305 | "&& reload_completed" | |
3306 | [(parallel | |
3307 | [(set (reg:CCL1 33) | |
3308 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) | |
3309 | (match_dup 7))) | |
3310 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3311 | (parallel | |
3312 | [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5)) | |
3313 | (ltu:SI (reg:CCL1 33) (const_int 0)))) | |
3314 | (clobber (reg:CC 33))])] | |
3315 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
3316 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3317 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3318 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3319 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3320 | operands[8] = operand_subword (operands[2], 1, 0, DImode);" | |
3321 | [(set_attr "op_type" "NN")]) | |
3322 | ||
07893d4f UW |
3323 | (define_insn_and_split "*adddi3_31" |
3324 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
96fd3851 | 3325 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 3326 | (match_operand:DI 2 "general_operand" "do") ) ) |
9db1d521 | 3327 | (clobber (reg:CC 33))] |
e69166de | 3328 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
3329 | "#" |
3330 | "&& reload_completed" | |
3331 | [(parallel | |
3332 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
3333 | (clobber (reg:CC 33))]) | |
3334 | (parallel | |
3335 | [(set (reg:CCL1 33) | |
3336 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) | |
3337 | (match_dup 7))) | |
3338 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3339 | (set (pc) | |
3340 | (if_then_else (ltu (reg:CCL1 33) (const_int 0)) | |
3341 | (pc) | |
3342 | (label_ref (match_dup 9)))) | |
3343 | (parallel | |
3344 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
3345 | (clobber (reg:CC 33))]) | |
3346 | (match_dup 9)] | |
97c6f7ad UW |
3347 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3348 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3349 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3350 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3351 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3352 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
07893d4f | 3353 | operands[9] = gen_label_rtx ();" |
0796c16a | 3354 | [(set_attr "op_type" "NN")]) |
9db1d521 HP |
3355 | |
3356 | (define_expand "adddi3" | |
07893d4f UW |
3357 | [(parallel |
3358 | [(set (match_operand:DI 0 "register_operand" "") | |
96fd3851 | 3359 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
07893d4f UW |
3360 | (match_operand:DI 2 "general_operand" ""))) |
3361 | (clobber (reg:CC 33))])] | |
9db1d521 | 3362 | "" |
07893d4f | 3363 | "") |
9db1d521 | 3364 | |
f3e9edff | 3365 | (define_insn "*la_64" |
d3632d41 UW |
3366 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
3367 | (match_operand:QI 1 "address_operand" "U,W"))] | |
9db1d521 | 3368 | "TARGET_64BIT" |
d3632d41 | 3369 | "@ |
d40c829f UW |
3370 | la\t%0,%a1 |
3371 | lay\t%0,%a1" | |
d3632d41 | 3372 | [(set_attr "op_type" "RX,RXY") |
9db1d521 HP |
3373 | (set_attr "type" "la")]) |
3374 | ||
4888ec5d UW |
3375 | (define_peephole2 |
3376 | [(parallel | |
3377 | [(set (match_operand:DI 0 "register_operand" "") | |
3378 | (match_operand:QI 1 "address_operand" "")) | |
3379 | (clobber (reg:CC 33))])] | |
3380 | "TARGET_64BIT | |
3381 | && strict_memory_address_p (VOIDmode, operands[1]) | |
3382 | && preferred_la_operand_p (operands[1])" | |
3383 | [(set (match_dup 0) (match_dup 1))] | |
3384 | "") | |
3385 | ||
3386 | (define_peephole2 | |
3387 | [(set (match_operand:DI 0 "register_operand" "") | |
3388 | (match_operand:DI 1 "register_operand" "")) | |
3389 | (parallel | |
3390 | [(set (match_dup 0) | |
3391 | (plus:DI (match_dup 0) | |
3392 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
3393 | (clobber (reg:CC 33))])] | |
3394 | "TARGET_64BIT | |
3395 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
3396 | && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (DImode, operands[1], operands[2])) | |
3397 | && preferred_la_operand_p (gen_rtx_PLUS (DImode, operands[1], operands[2]))" | |
3398 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] | |
3399 | "") | |
3400 | ||
f3e9edff UW |
3401 | (define_expand "reload_indi" |
3402 | [(parallel [(match_operand:DI 0 "register_operand" "=a") | |
3403 | (match_operand:DI 1 "s390_plus_operand" "") | |
7974fe63 | 3404 | (match_operand:DI 2 "register_operand" "=&a")])] |
9db1d521 | 3405 | "TARGET_64BIT" |
4023fb28 | 3406 | { |
f3e9edff UW |
3407 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); |
3408 | DONE; | |
10bbf137 | 3409 | }) |
4023fb28 | 3410 | |
c7453384 | 3411 | |
9db1d521 HP |
3412 | ; |
3413 | ; addsi3 instruction pattern(s). | |
3414 | ; | |
9db1d521 | 3415 | |
0a3bdf9d | 3416 | (define_insn "*addsi3_imm_cc" |
c7453384 | 3417 | [(set (reg 33) |
0a3bdf9d UW |
3418 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
3419 | (match_operand:SI 2 "const_int_operand" "K")) | |
3420 | (const_int 0))) | |
3421 | (set (match_operand:SI 0 "register_operand" "=d") | |
3422 | (plus:SI (match_dup 1) (match_dup 2)))] | |
3423 | "s390_match_ccmode (insn, CCAmode) | |
3424 | && CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K')" | |
d40c829f | 3425 | "ahi\t%0,%h2" |
077dab3b | 3426 | [(set_attr "op_type" "RI")]) |
0a3bdf9d | 3427 | |
07893d4f | 3428 | (define_insn "*addsi3_carry1_cc" |
c7453384 | 3429 | [(set (reg 33) |
d3632d41 UW |
3430 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3431 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3432 | (match_dup 1))) |
d3632d41 | 3433 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3434 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3435 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3436 | "@ |
d40c829f UW |
3437 | alr\t%0,%2 |
3438 | al\t%0,%2 | |
3439 | aly\t%0,%2" | |
d3632d41 | 3440 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3441 | |
3442 | (define_insn "*addsi3_carry1_cconly" | |
c7453384 | 3443 | [(set (reg 33) |
d3632d41 UW |
3444 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3445 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3446 | (match_dup 1))) |
d3632d41 | 3447 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3448 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3449 | "@ |
d40c829f UW |
3450 | alr\t%0,%2 |
3451 | al\t%0,%2 | |
3452 | aly\t%0,%2" | |
d3632d41 | 3453 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3454 | |
3455 | (define_insn "*addsi3_carry2_cc" | |
c7453384 | 3456 | [(set (reg 33) |
d3632d41 UW |
3457 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3458 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3459 | (match_dup 2))) |
d3632d41 | 3460 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3461 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3462 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3463 | "@ |
d40c829f UW |
3464 | alr\t%0,%2 |
3465 | al\t%0,%2 | |
3466 | aly\t%0,%2" | |
d3632d41 | 3467 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3468 | |
3469 | (define_insn "*addsi3_carry2_cconly" | |
c7453384 | 3470 | [(set (reg 33) |
d3632d41 UW |
3471 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3472 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3473 | (match_dup 2))) |
d3632d41 | 3474 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3475 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3476 | "@ |
d40c829f UW |
3477 | alr\t%0,%2 |
3478 | al\t%0,%2 | |
3479 | aly\t%0,%2" | |
d3632d41 | 3480 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f | 3481 | |
9db1d521 | 3482 | (define_insn "*addsi3_cc" |
c7453384 | 3483 | [(set (reg 33) |
d3632d41 UW |
3484 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3485 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3486 | (const_int 0))) |
d3632d41 | 3487 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 | 3488 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3489 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3490 | "@ |
d40c829f UW |
3491 | alr\t%0,%2 |
3492 | al\t%0,%2 | |
3493 | aly\t%0,%2" | |
d3632d41 | 3494 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
3495 | |
3496 | (define_insn "*addsi3_cconly" | |
c7453384 | 3497 | [(set (reg 33) |
d3632d41 UW |
3498 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3499 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3500 | (const_int 0))) |
d3632d41 | 3501 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3502 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3503 | "@ |
d40c829f UW |
3504 | alr\t%0,%2 |
3505 | al\t%0,%2 | |
3506 | aly\t%0,%2" | |
d3632d41 | 3507 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
3508 | |
3509 | (define_insn "*addsi3_cconly2" | |
c7453384 | 3510 | [(set (reg 33) |
d3632d41 UW |
3511 | (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3512 | (neg:SI (match_operand:SI 2 "general_operand" "d,R,T")))) | |
3513 | (clobber (match_scratch:SI 0 "=d,d,d"))] | |
b2ba71ca | 3514 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3515 | "@ |
d40c829f UW |
3516 | alr\t%0,%2 |
3517 | al\t%0,%2 | |
3518 | aly\t%0,%2" | |
d3632d41 | 3519 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 3520 | |
07893d4f | 3521 | (define_insn "*addsi3_sign" |
d3632d41 UW |
3522 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3523 | (plus:SI (match_operand:SI 1 "register_operand" "0,0") | |
3524 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
07893d4f UW |
3525 | (clobber (reg:CC 33))] |
3526 | "" | |
d3632d41 | 3527 | "@ |
d40c829f UW |
3528 | ah\t%0,%2 |
3529 | ahy\t%0,%2" | |
d3632d41 | 3530 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f | 3531 | |
9db1d521 | 3532 | (define_insn "addsi3" |
d3632d41 UW |
3533 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
3534 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
3535 | (match_operand:SI 2 "general_operand" "d,K,R,T"))) | |
9db1d521 HP |
3536 | (clobber (reg:CC 33))] |
3537 | "" | |
3538 | "@ | |
d40c829f UW |
3539 | ar\t%0,%2 |
3540 | ahi\t%0,%h2 | |
3541 | a\t%0,%2 | |
3542 | ay\t%0,%2" | |
d3632d41 | 3543 | [(set_attr "op_type" "RR,RI,RX,RXY")]) |
9db1d521 | 3544 | |
f3e9edff | 3545 | (define_insn "*la_31" |
d3632d41 UW |
3546 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3547 | (match_operand:QI 1 "address_operand" "U,W"))] | |
100c7420 | 3548 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
d3632d41 | 3549 | "@ |
d40c829f UW |
3550 | la\t%0,%a1 |
3551 | lay\t%0,%a1" | |
d3632d41 | 3552 | [(set_attr "op_type" "RX,RXY") |
100c7420 UW |
3553 | (set_attr "type" "la")]) |
3554 | ||
4888ec5d UW |
3555 | (define_peephole2 |
3556 | [(parallel | |
3557 | [(set (match_operand:SI 0 "register_operand" "") | |
3558 | (match_operand:QI 1 "address_operand" "")) | |
3559 | (clobber (reg:CC 33))])] | |
3560 | "!TARGET_64BIT | |
3561 | && strict_memory_address_p (VOIDmode, operands[1]) | |
3562 | && preferred_la_operand_p (operands[1])" | |
3563 | [(set (match_dup 0) (match_dup 1))] | |
3564 | "") | |
3565 | ||
3566 | (define_peephole2 | |
3567 | [(set (match_operand:SI 0 "register_operand" "") | |
3568 | (match_operand:SI 1 "register_operand" "")) | |
3569 | (parallel | |
3570 | [(set (match_dup 0) | |
3571 | (plus:SI (match_dup 0) | |
3572 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
3573 | (clobber (reg:CC 33))])] | |
3574 | "!TARGET_64BIT | |
3575 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
3576 | && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (SImode, operands[1], operands[2])) | |
3577 | && preferred_la_operand_p (gen_rtx_PLUS (SImode, operands[1], operands[2]))" | |
3578 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] | |
3579 | "") | |
3580 | ||
100c7420 | 3581 | (define_insn "*la_31_and" |
d3632d41 UW |
3582 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3583 | (and:SI (match_operand:QI 1 "address_operand" "U,W") | |
100c7420 UW |
3584 | (const_int 2147483647)))] |
3585 | "!TARGET_64BIT" | |
d3632d41 | 3586 | "@ |
d40c829f UW |
3587 | la\t%0,%a1 |
3588 | lay\t%0,%a1" | |
d3632d41 | 3589 | [(set_attr "op_type" "RX,RXY") |
9db1d521 | 3590 | (set_attr "type" "la")]) |
100c7420 UW |
3591 | |
3592 | (define_insn_and_split "*la_31_and_cc" | |
3593 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3594 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
3595 | (const_int 2147483647))) | |
3596 | (clobber (reg:CC 33))] | |
3597 | "!TARGET_64BIT" | |
3598 | "#" | |
3599 | "&& reload_completed" | |
c7453384 | 3600 | [(set (match_dup 0) |
100c7420 UW |
3601 | (and:SI (match_dup 1) (const_int 2147483647)))] |
3602 | "" | |
3603 | [(set_attr "op_type" "RX") | |
100c7420 | 3604 | (set_attr "type" "la")]) |
9db1d521 | 3605 | |
a41c6c53 | 3606 | (define_insn "force_la_31" |
d3632d41 UW |
3607 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3608 | (match_operand:QI 1 "address_operand" "U,W")) | |
a41c6c53 UW |
3609 | (use (const_int 0))] |
3610 | "!TARGET_64BIT" | |
d3632d41 | 3611 | "@ |
d40c829f UW |
3612 | la\t%0,%a1 |
3613 | lay\t%0,%a1" | |
a41c6c53 | 3614 | [(set_attr "op_type" "RX") |
a41c6c53 UW |
3615 | (set_attr "type" "la")]) |
3616 | ||
f3e9edff UW |
3617 | (define_expand "reload_insi" |
3618 | [(parallel [(match_operand:SI 0 "register_operand" "=a") | |
3619 | (match_operand:SI 1 "s390_plus_operand" "") | |
7974fe63 | 3620 | (match_operand:SI 2 "register_operand" "=&a")])] |
f3e9edff | 3621 | "!TARGET_64BIT" |
4023fb28 | 3622 | { |
f3e9edff UW |
3623 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); |
3624 | DONE; | |
10bbf137 | 3625 | }) |
bc1fa59c | 3626 | |
9db1d521 | 3627 | |
9db1d521 HP |
3628 | ; |
3629 | ; adddf3 instruction pattern(s). | |
3630 | ; | |
3631 | ||
3632 | (define_expand "adddf3" | |
3633 | [(parallel | |
3634 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3635 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3636 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3637 | (clobber (reg:CC 33))])] |
3638 | "TARGET_HARD_FLOAT" | |
3639 | "") | |
3640 | ||
3641 | (define_insn "*adddf3" | |
3642 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3643 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3644 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3645 | (clobber (reg:CC 33))] |
3646 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3647 | "@ | |
d40c829f UW |
3648 | adbr\t%0,%2 |
3649 | adb\t%0,%2" | |
ce50cae8 | 3650 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 3651 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 | 3652 | |
3ef093a8 AK |
3653 | (define_insn "*adddf3_cc" |
3654 | [(set (reg 33) | |
3655 | (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
3656 | (match_operand:DF 2 "general_operand" "f,R")) | |
3657 | (match_operand:DF 3 "const0_operand" ""))) | |
3658 | (set (match_operand:DF 0 "register_operand" "=f,f") | |
3659 | (plus:DF (match_dup 1) (match_dup 2)))] | |
3660 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3661 | "@ | |
d40c829f UW |
3662 | adbr\t%0,%2 |
3663 | adb\t%0,%2" | |
3ef093a8 AK |
3664 | [(set_attr "op_type" "RRE,RXE") |
3665 | (set_attr "type" "fsimpd,fsimpd")]) | |
3666 | ||
3667 | (define_insn "*adddf3_cconly" | |
3668 | [(set (reg 33) | |
3669 | (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
3670 | (match_operand:DF 2 "general_operand" "f,R")) | |
3671 | (match_operand:DF 3 "const0_operand" ""))) | |
3672 | (clobber (match_scratch:DF 0 "=f,f"))] | |
3673 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3674 | "@ | |
d40c829f UW |
3675 | adbr\t%0,%2 |
3676 | adb\t%0,%2" | |
3ef093a8 AK |
3677 | [(set_attr "op_type" "RRE,RXE") |
3678 | (set_attr "type" "fsimpd,fsimpd")]) | |
3679 | ||
9db1d521 HP |
3680 | (define_insn "*adddf3_ibm" |
3681 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3682 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3683 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3684 | (clobber (reg:CC 33))] |
3685 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3686 | "@ | |
d40c829f UW |
3687 | adr\t%0,%2 |
3688 | ad\t%0,%2" | |
9db1d521 | 3689 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3690 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 HP |
3691 | |
3692 | ; | |
3693 | ; addsf3 instruction pattern(s). | |
3694 | ; | |
3695 | ||
3696 | (define_expand "addsf3" | |
3697 | [(parallel | |
3698 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3699 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3700 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3701 | (clobber (reg:CC 33))])] |
3702 | "TARGET_HARD_FLOAT" | |
3703 | "") | |
3704 | ||
3705 | (define_insn "*addsf3" | |
3706 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3707 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3708 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3709 | (clobber (reg:CC 33))] |
3710 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3711 | "@ | |
d40c829f UW |
3712 | aebr\t%0,%2 |
3713 | aeb\t%0,%2" | |
ce50cae8 | 3714 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 3715 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 | 3716 | |
3ef093a8 AK |
3717 | (define_insn "*addsf3_cc" |
3718 | [(set (reg 33) | |
3719 | (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
3720 | (match_operand:SF 2 "general_operand" "f,R")) | |
3721 | (match_operand:SF 3 "const0_operand" ""))) | |
3722 | (set (match_operand:SF 0 "register_operand" "=f,f") | |
3723 | (plus:SF (match_dup 1) (match_dup 2)))] | |
3724 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3725 | "@ | |
d40c829f UW |
3726 | aebr\t%0,%2 |
3727 | aeb\t%0,%2" | |
3ef093a8 AK |
3728 | [(set_attr "op_type" "RRE,RXE") |
3729 | (set_attr "type" "fsimps,fsimps")]) | |
3730 | ||
3731 | (define_insn "*addsf3_cconly" | |
3732 | [(set (reg 33) | |
3733 | (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
3734 | (match_operand:SF 2 "general_operand" "f,R")) | |
3735 | (match_operand:SF 3 "const0_operand" ""))) | |
3736 | (clobber (match_scratch:SF 0 "=f,f"))] | |
3737 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3738 | "@ | |
d40c829f UW |
3739 | aebr\t%0,%2 |
3740 | aeb\t%0,%2" | |
3ef093a8 AK |
3741 | [(set_attr "op_type" "RRE,RXE") |
3742 | (set_attr "type" "fsimps,fsimps")]) | |
3743 | ||
9db1d521 HP |
3744 | (define_insn "*addsf3" |
3745 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3746 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3747 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3748 | (clobber (reg:CC 33))] |
3749 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3750 | "@ | |
d40c829f UW |
3751 | aer\t%0,%2 |
3752 | ae\t%0,%2" | |
9db1d521 | 3753 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3754 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 HP |
3755 | |
3756 | ||
3757 | ;; | |
3758 | ;;- Subtract instructions. | |
3759 | ;; | |
3760 | ||
3761 | ; | |
3762 | ; subdi3 instruction pattern(s). | |
3763 | ; | |
3764 | ||
07893d4f UW |
3765 | (define_insn "*subdi3_sign" |
3766 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3767 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3768 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
3769 | (clobber (reg:CC 33))] | |
3770 | "TARGET_64BIT" | |
3771 | "@ | |
d40c829f UW |
3772 | sgfr\t%0,%2 |
3773 | sgf\t%0,%2" | |
d3632d41 | 3774 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3775 | |
3776 | (define_insn "*subdi3_zero_cc" | |
c7453384 | 3777 | [(set (reg 33) |
07893d4f UW |
3778 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3779 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3780 | (const_int 0))) | |
3781 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3782 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
3783 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3784 | "@ | |
d40c829f UW |
3785 | slgfr\t%0,%2 |
3786 | slgf\t%0,%2" | |
d3632d41 | 3787 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3788 | |
3789 | (define_insn "*subdi3_zero_cconly" | |
c7453384 | 3790 | [(set (reg 33) |
07893d4f UW |
3791 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3792 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3793 | (const_int 0))) | |
3794 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3795 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3796 | "@ | |
d40c829f UW |
3797 | slgfr\t%0,%2 |
3798 | slgf\t%0,%2" | |
d3632d41 | 3799 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3800 | |
3801 | (define_insn "*subdi3_zero" | |
3802 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3803 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3804 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
3805 | (clobber (reg:CC 33))] | |
3806 | "TARGET_64BIT" | |
3807 | "@ | |
d40c829f UW |
3808 | slgfr\t%0,%2 |
3809 | slgf\t%0,%2" | |
d3632d41 | 3810 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3811 | |
b2ba71ca UW |
3812 | (define_insn "*subdi3_borrow_cc" |
3813 | [(set (reg 33) | |
3814 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3815 | (match_operand:DI 2 "general_operand" "d,m")) | |
3816 | (match_dup 1))) | |
3817 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3818 | (minus:DI (match_dup 1) (match_dup 2)))] | |
3819 | "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" | |
3820 | "@ | |
3821 | slgr\t%0,%2 | |
3822 | slg\t%0,%2" | |
3823 | [(set_attr "op_type" "RRE,RXY")]) | |
3824 | ||
3825 | (define_insn "*subdi3_borrow_cconly" | |
3826 | [(set (reg 33) | |
3827 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3828 | (match_operand:DI 2 "general_operand" "d,m")) | |
3829 | (match_dup 1))) | |
3830 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3831 | "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" | |
3832 | "@ | |
3833 | slgr\t%0,%2 | |
3834 | slg\t%0,%2" | |
3835 | [(set_attr "op_type" "RRE,RXY")]) | |
3836 | ||
07893d4f UW |
3837 | (define_insn "*subdi3_cc" |
3838 | [(set (reg 33) | |
3839 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3840 | (match_operand:DI 2 "general_operand" "d,m")) | |
3841 | (const_int 0))) | |
3842 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3843 | (minus:DI (match_dup 1) (match_dup 2)))] | |
b2ba71ca | 3844 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
07893d4f | 3845 | "@ |
d40c829f UW |
3846 | slgr\t%0,%2 |
3847 | slg\t%0,%2" | |
d3632d41 | 3848 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3849 | |
3850 | (define_insn "*subdi3_cconly" | |
3851 | [(set (reg 33) | |
3852 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3853 | (match_operand:DI 2 "general_operand" "d,m")) | |
3854 | (const_int 0))) | |
3855 | (clobber (match_scratch:DI 0 "=d,d"))] | |
b2ba71ca | 3856 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
07893d4f | 3857 | "@ |
d40c829f UW |
3858 | slgr\t%0,%2 |
3859 | slg\t%0,%2" | |
d3632d41 | 3860 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3861 | |
9db1d521 HP |
3862 | (define_insn "*subdi3_64" |
3863 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3864 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3865 | (match_operand:DI 2 "general_operand" "d,m") ) ) | |
3866 | (clobber (reg:CC 33))] | |
3867 | "TARGET_64BIT" | |
3868 | "@ | |
d40c829f UW |
3869 | sgr\t%0,%2 |
3870 | sg\t%0,%2" | |
077dab3b | 3871 | [(set_attr "op_type" "RRE,RRE")]) |
9db1d521 | 3872 | |
e69166de UW |
3873 | (define_insn_and_split "*subdi3_31z" |
3874 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3875 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
3876 | (match_operand:DI 2 "general_operand" "do") ) ) | |
3877 | (clobber (reg:CC 33))] | |
3878 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
3879 | "#" | |
3880 | "&& reload_completed" | |
3881 | [(parallel | |
3882 | [(set (reg:CCL2 33) | |
3883 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) | |
3884 | (match_dup 7))) | |
3885 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
3886 | (parallel | |
3887 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
3888 | (gtu:SI (reg:CCL2 33) (const_int 0)))) | |
3889 | (clobber (reg:CC 33))])] | |
3890 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
3891 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3892 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3893 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3894 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3895 | operands[8] = operand_subword (operands[2], 1, 0, DImode);" | |
3896 | [(set_attr "op_type" "NN")]) | |
3897 | ||
07893d4f UW |
3898 | (define_insn_and_split "*subdi3_31" |
3899 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3900 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 3901 | (match_operand:DI 2 "general_operand" "do") ) ) |
9db1d521 | 3902 | (clobber (reg:CC 33))] |
e69166de | 3903 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
3904 | "#" |
3905 | "&& reload_completed" | |
3906 | [(parallel | |
3907 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
3908 | (clobber (reg:CC 33))]) | |
3909 | (parallel | |
3910 | [(set (reg:CCL2 33) | |
3911 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) | |
3912 | (match_dup 7))) | |
3913 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
3914 | (set (pc) | |
3915 | (if_then_else (gtu (reg:CCL2 33) (const_int 0)) | |
3916 | (pc) | |
3917 | (label_ref (match_dup 9)))) | |
3918 | (parallel | |
3919 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
3920 | (clobber (reg:CC 33))]) | |
3921 | (match_dup 9)] | |
97c6f7ad UW |
3922 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3923 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3924 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3925 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3926 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3927 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
07893d4f | 3928 | operands[9] = gen_label_rtx ();" |
0796c16a | 3929 | [(set_attr "op_type" "NN")]) |
07893d4f UW |
3930 | |
3931 | (define_expand "subdi3" | |
3932 | [(parallel | |
3933 | [(set (match_operand:DI 0 "register_operand" "") | |
3934 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
3935 | (match_operand:DI 2 "general_operand" ""))) | |
3936 | (clobber (reg:CC 33))])] | |
9db1d521 | 3937 | "" |
07893d4f | 3938 | "") |
9db1d521 HP |
3939 | |
3940 | ; | |
3941 | ; subsi3 instruction pattern(s). | |
3942 | ; | |
3943 | ||
07893d4f UW |
3944 | (define_insn "*subsi3_borrow_cc" |
3945 | [(set (reg 33) | |
d3632d41 UW |
3946 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3947 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3948 | (match_dup 1))) |
d3632d41 | 3949 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3950 | (minus:SI (match_dup 1) (match_dup 2)))] |
b2ba71ca | 3951 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 3952 | "@ |
d40c829f UW |
3953 | slr\t%0,%2 |
3954 | sl\t%0,%2 | |
3955 | sly\t%0,%2" | |
d3632d41 | 3956 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3957 | |
3958 | (define_insn "*subsi3_borrow_cconly" | |
3959 | [(set (reg 33) | |
d3632d41 UW |
3960 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3961 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3962 | (match_dup 1))) |
d3632d41 | 3963 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
b2ba71ca | 3964 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 3965 | "@ |
d40c829f UW |
3966 | slr\t%0,%2 |
3967 | sl\t%0,%2 | |
3968 | sly\t%0,%2" | |
b2ba71ca | 3969 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f | 3970 | |
9db1d521 HP |
3971 | (define_insn "*subsi3_cc" |
3972 | [(set (reg 33) | |
d3632d41 UW |
3973 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3974 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3975 | (const_int 0))) |
d3632d41 | 3976 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 | 3977 | (minus:SI (match_dup 1) (match_dup 2)))] |
b2ba71ca | 3978 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3979 | "@ |
d40c829f UW |
3980 | slr\t%0,%2 |
3981 | sl\t%0,%2 | |
3982 | sly\t%0,%2" | |
d3632d41 | 3983 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
3984 | |
3985 | (define_insn "*subsi3_cconly" | |
3986 | [(set (reg 33) | |
d3632d41 UW |
3987 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3988 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3989 | (const_int 0))) |
d3632d41 | 3990 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
b2ba71ca | 3991 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3992 | "@ |
d40c829f UW |
3993 | slr\t%0,%2 |
3994 | sl\t%0,%2 | |
3995 | sly\t%0,%2" | |
d3632d41 | 3996 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 3997 | |
07893d4f | 3998 | (define_insn "*subsi3_sign" |
d3632d41 UW |
3999 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4000 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
4001 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
07893d4f UW |
4002 | (clobber (reg:CC 33))] |
4003 | "" | |
d3632d41 | 4004 | "@ |
d40c829f UW |
4005 | sh\t%0,%2 |
4006 | shy\t%0,%2" | |
d3632d41 | 4007 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f | 4008 | |
9db1d521 | 4009 | (define_insn "subsi3" |
d3632d41 UW |
4010 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
4011 | (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") | |
4012 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
9db1d521 HP |
4013 | (clobber (reg:CC 33))] |
4014 | "" | |
4015 | "@ | |
d40c829f UW |
4016 | sr\t%0,%2 |
4017 | s\t%0,%2 | |
4018 | sy\t%0,%2" | |
d3632d41 | 4019 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 4020 | |
9db1d521 HP |
4021 | |
4022 | ; | |
4023 | ; subdf3 instruction pattern(s). | |
4024 | ; | |
4025 | ||
4026 | (define_expand "subdf3" | |
4027 | [(parallel | |
4028 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4029 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 4030 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4031 | (clobber (reg:CC 33))])] |
4032 | "TARGET_HARD_FLOAT" | |
4033 | "") | |
4034 | ||
4035 | (define_insn "*subdf3" | |
4036 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4037 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 4038 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4039 | (clobber (reg:CC 33))] |
4040 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4041 | "@ | |
d40c829f UW |
4042 | sdbr\t%0,%2 |
4043 | sdb\t%0,%2" | |
ce50cae8 | 4044 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4045 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 | 4046 | |
3ef093a8 AK |
4047 | (define_insn "*subdf3_cc" |
4048 | [(set (reg 33) | |
4049 | (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
4050 | (match_operand:DF 2 "general_operand" "f,R")) | |
4051 | (match_operand:DF 3 "const0_operand" ""))) | |
4052 | (set (match_operand:DF 0 "register_operand" "=f,f") | |
4053 | (plus:DF (match_dup 1) (match_dup 2)))] | |
4054 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4055 | "@ | |
d40c829f UW |
4056 | sdbr\t%0,%2 |
4057 | sdb\t%0,%2" | |
3ef093a8 AK |
4058 | [(set_attr "op_type" "RRE,RXE") |
4059 | (set_attr "type" "fsimpd,fsimpd")]) | |
4060 | ||
4061 | (define_insn "*subdf3_cconly" | |
4062 | [(set (reg 33) | |
4063 | (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
4064 | (match_operand:DF 2 "general_operand" "f,R")) | |
4065 | (match_operand:DF 3 "const0_operand" ""))) | |
4066 | (clobber (match_scratch:DF 0 "=f,f"))] | |
4067 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4068 | "@ | |
d40c829f UW |
4069 | sdbr\t%0,%2 |
4070 | sdb\t%0,%2" | |
3ef093a8 AK |
4071 | [(set_attr "op_type" "RRE,RXE") |
4072 | (set_attr "type" "fsimpd,fsimpd")]) | |
4073 | ||
9db1d521 HP |
4074 | (define_insn "*subdf3_ibm" |
4075 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4076 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 4077 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4078 | (clobber (reg:CC 33))] |
4079 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
4080 | "@ | |
d40c829f UW |
4081 | sdr\t%0,%2 |
4082 | sd\t%0,%2" | |
9db1d521 | 4083 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4084 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 HP |
4085 | |
4086 | ; | |
4087 | ; subsf3 instruction pattern(s). | |
4088 | ; | |
4089 | ||
4090 | (define_expand "subsf3" | |
4091 | [(parallel | |
4092 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4093 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4094 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4095 | (clobber (reg:CC 33))])] |
4096 | "TARGET_HARD_FLOAT" | |
4097 | "") | |
4098 | ||
4099 | (define_insn "*subsf3" | |
4100 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4101 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4102 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4103 | (clobber (reg:CC 33))] |
4104 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4105 | "@ | |
d40c829f UW |
4106 | sebr\t%0,%2 |
4107 | seb\t%0,%2" | |
ce50cae8 | 4108 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4109 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 | 4110 | |
3ef093a8 AK |
4111 | (define_insn "*subsf3_cc" |
4112 | [(set (reg 33) | |
4113 | (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
4114 | (match_operand:SF 2 "general_operand" "f,R")) | |
4115 | (match_operand:SF 3 "const0_operand" ""))) | |
4116 | (set (match_operand:SF 0 "register_operand" "=f,f") | |
4117 | (minus:SF (match_dup 1) (match_dup 2)))] | |
4118 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4119 | "@ | |
d40c829f UW |
4120 | sebr\t%0,%2 |
4121 | seb\t%0,%2" | |
3ef093a8 AK |
4122 | [(set_attr "op_type" "RRE,RXE") |
4123 | (set_attr "type" "fsimps,fsimps")]) | |
4124 | ||
4125 | (define_insn "*subsf3_cconly" | |
4126 | [(set (reg 33) | |
4127 | (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
4128 | (match_operand:SF 2 "general_operand" "f,R")) | |
4129 | (match_operand:SF 3 "const0_operand" ""))) | |
4130 | (clobber (match_scratch:SF 0 "=f,f"))] | |
4131 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4132 | "@ | |
d40c829f UW |
4133 | sebr\t%0,%2 |
4134 | seb\t%0,%2" | |
3ef093a8 AK |
4135 | [(set_attr "op_type" "RRE,RXE") |
4136 | (set_attr "type" "fsimps,fsimps")]) | |
4137 | ||
9db1d521 HP |
4138 | (define_insn "*subsf3_ibm" |
4139 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4140 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4141 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4142 | (clobber (reg:CC 33))] |
4143 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
4144 | "@ | |
d40c829f UW |
4145 | ser\t%0,%2 |
4146 | se\t%0,%2" | |
9db1d521 | 4147 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4148 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 HP |
4149 | |
4150 | ||
e69166de UW |
4151 | ;; |
4152 | ;;- Conditional add/subtract instructions. | |
4153 | ;; | |
4154 | ||
4155 | ; | |
4156 | ; adddicc instruction pattern(s). | |
4157 | ; | |
4158 | ||
4159 | (define_insn "*adddi3_alc_cc" | |
4160 | [(set (reg 33) | |
4161 | (compare | |
4162 | (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
4163 | (match_operand:DI 2 "general_operand" "d,m")) | |
4164 | (match_operand:DI 3 "s390_alc_comparison" "")) | |
4165 | (const_int 0))) | |
4166 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4167 | (plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4168 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
4169 | "@ | |
4170 | alcgr\\t%0,%2 | |
4171 | alcg\\t%0,%2" | |
4172 | [(set_attr "op_type" "RRE,RXY")]) | |
4173 | ||
4174 | (define_insn "*adddi3_alc" | |
4175 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4176 | (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
4177 | (match_operand:DI 2 "general_operand" "d,m")) | |
4178 | (match_operand:DI 3 "s390_alc_comparison" ""))) | |
4179 | (clobber (reg:CC 33))] | |
4180 | "TARGET_64BIT" | |
4181 | "@ | |
4182 | alcgr\\t%0,%2 | |
4183 | alcg\\t%0,%2" | |
4184 | [(set_attr "op_type" "RRE,RXY")]) | |
4185 | ||
4186 | (define_insn "*subdi3_slb_cc" | |
4187 | [(set (reg 33) | |
4188 | (compare | |
4189 | (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
4190 | (match_operand:DI 2 "general_operand" "d,m")) | |
4191 | (match_operand:DI 3 "s390_slb_comparison" "")) | |
4192 | (const_int 0))) | |
4193 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4194 | (minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4195 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
4196 | "@ | |
4197 | slbgr\\t%0,%2 | |
4198 | slbg\\t%0,%2" | |
4199 | [(set_attr "op_type" "RRE,RXY")]) | |
4200 | ||
4201 | (define_insn "*subdi3_slb" | |
4202 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4203 | (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
4204 | (match_operand:DI 2 "general_operand" "d,m")) | |
4205 | (match_operand:DI 3 "s390_slb_comparison" ""))) | |
4206 | (clobber (reg:CC 33))] | |
4207 | "TARGET_64BIT" | |
4208 | "@ | |
4209 | slbgr\\t%0,%2 | |
4210 | slbg\\t%0,%2" | |
4211 | [(set_attr "op_type" "RRE,RXY")]) | |
4212 | ||
4213 | ; | |
4214 | ; addsicc instruction pattern(s). | |
4215 | ; | |
4216 | ||
4217 | (define_insn "*addsi3_alc_cc" | |
4218 | [(set (reg 33) | |
4219 | (compare | |
4220 | (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
4221 | (match_operand:SI 2 "general_operand" "d,m")) | |
4222 | (match_operand:SI 3 "s390_alc_comparison" "")) | |
4223 | (const_int 0))) | |
4224 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
4225 | (plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4226 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" | |
4227 | "@ | |
4228 | alcr\\t%0,%2 | |
4229 | alc\\t%0,%2" | |
4230 | [(set_attr "op_type" "RRE,RXY")]) | |
4231 | ||
4232 | (define_insn "*addsi3_alc" | |
4233 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4234 | (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
4235 | (match_operand:SI 2 "general_operand" "d,m")) | |
4236 | (match_operand:SI 3 "s390_alc_comparison" ""))) | |
4237 | (clobber (reg:CC 33))] | |
4238 | "TARGET_CPU_ZARCH" | |
4239 | "@ | |
4240 | alcr\\t%0,%2 | |
4241 | alc\\t%0,%2" | |
4242 | [(set_attr "op_type" "RRE,RXY")]) | |
4243 | ||
4244 | (define_insn "*subsi3_slb_cc" | |
4245 | [(set (reg 33) | |
4246 | (compare | |
4247 | (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
4248 | (match_operand:SI 2 "general_operand" "d,m")) | |
4249 | (match_operand:SI 3 "s390_slb_comparison" "")) | |
4250 | (const_int 0))) | |
4251 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
4252 | (minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4253 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" | |
4254 | "@ | |
4255 | slbr\\t%0,%2 | |
4256 | slb\\t%0,%2" | |
4257 | [(set_attr "op_type" "RRE,RXY")]) | |
4258 | ||
4259 | (define_insn "*subsi3_slb" | |
4260 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4261 | (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
4262 | (match_operand:SI 2 "general_operand" "d,m")) | |
4263 | (match_operand:SI 3 "s390_slb_comparison" ""))) | |
4264 | (clobber (reg:CC 33))] | |
4265 | "TARGET_CPU_ZARCH" | |
4266 | "@ | |
4267 | slbr\\t%0,%2 | |
4268 | slb\\t%0,%2" | |
4269 | [(set_attr "op_type" "RRE,RXY")]) | |
4270 | ||
4271 | ||
9db1d521 HP |
4272 | ;; |
4273 | ;;- Multiply instructions. | |
4274 | ;; | |
4275 | ||
4023fb28 UW |
4276 | ; |
4277 | ; muldi3 instruction pattern(s). | |
4278 | ; | |
9db1d521 | 4279 | |
07893d4f UW |
4280 | (define_insn "*muldi3_sign" |
4281 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4282 | (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")) | |
4283 | (match_operand:DI 1 "register_operand" "0,0")))] | |
4284 | "TARGET_64BIT" | |
4285 | "@ | |
d40c829f UW |
4286 | msgfr\t%0,%2 |
4287 | msgf\t%0,%2" | |
d3632d41 | 4288 | [(set_attr "op_type" "RRE,RXY") |
07893d4f UW |
4289 | (set_attr "type" "imul")]) |
4290 | ||
4023fb28 | 4291 | (define_insn "muldi3" |
9db1d521 | 4292 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
96fd3851 | 4293 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
07893d4f | 4294 | (match_operand:DI 2 "general_operand" "d,K,m")))] |
9db1d521 HP |
4295 | "TARGET_64BIT" |
4296 | "@ | |
d40c829f UW |
4297 | msgr\t%0,%2 |
4298 | mghi\t%0,%h2 | |
4299 | msg\t%0,%2" | |
d3632d41 | 4300 | [(set_attr "op_type" "RRE,RI,RXY") |
f2d3c02a HP |
4301 | (set_attr "type" "imul")]) |
4302 | ||
9db1d521 HP |
4303 | ; |
4304 | ; mulsi3 instruction pattern(s). | |
4305 | ; | |
4306 | ||
f1e77d83 UW |
4307 | (define_insn "*mulsi3_sign" |
4308 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4309 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R")) | |
4310 | (match_operand:SI 1 "register_operand" "0")))] | |
4311 | "" | |
4312 | "mh\t%0,%2" | |
4313 | [(set_attr "op_type" "RX") | |
4314 | (set_attr "type" "imul")]) | |
4315 | ||
9db1d521 | 4316 | (define_insn "mulsi3" |
d3632d41 UW |
4317 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4318 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
4319 | (match_operand:SI 2 "general_operand" "d,K,R,T")))] | |
9db1d521 HP |
4320 | "" |
4321 | "@ | |
d40c829f UW |
4322 | msr\t%0,%2 |
4323 | mhi\t%0,%h2 | |
4324 | ms\t%0,%2 | |
4325 | msy\t%0,%2" | |
d3632d41 | 4326 | [(set_attr "op_type" "RRE,RI,RX,RXY") |
f2d3c02a | 4327 | (set_attr "type" "imul")]) |
9db1d521 | 4328 | |
4023fb28 UW |
4329 | ; |
4330 | ; mulsidi3 instruction pattern(s). | |
4331 | ; | |
4332 | ||
f1e77d83 UW |
4333 | (define_insn "mulsidi3" |
4334 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4335 | (mult:DI (sign_extend:DI | |
4336 | (match_operand:SI 1 "register_operand" "%0,0")) | |
4337 | (sign_extend:DI | |
4338 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))] | |
4023fb28 | 4339 | "!TARGET_64BIT" |
f1e77d83 UW |
4340 | "@ |
4341 | mr\t%0,%2 | |
4342 | m\t%0,%2" | |
4343 | [(set_attr "op_type" "RR,RX") | |
4344 | (set_attr "type" "imul")]) | |
4023fb28 | 4345 | |
f1e77d83 UW |
4346 | ; |
4347 | ; umulsidi3 instruction pattern(s). | |
4348 | ; | |
c7453384 | 4349 | |
f1e77d83 UW |
4350 | (define_insn "umulsidi3" |
4351 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4352 | (mult:DI (zero_extend:DI | |
4353 | (match_operand:SI 1 "register_operand" "%0,0")) | |
4354 | (zero_extend:DI | |
4355 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))] | |
4356 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4357 | "@ | |
4358 | mlr\t%0,%2 | |
4359 | ml\t%0,%2" | |
4360 | [(set_attr "op_type" "RRE,RXY") | |
f2d3c02a | 4361 | (set_attr "type" "imul")]) |
c7453384 | 4362 | |
9db1d521 HP |
4363 | ; |
4364 | ; muldf3 instruction pattern(s). | |
4365 | ; | |
4366 | ||
4367 | (define_expand "muldf3" | |
553e5ce9 UW |
4368 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
4369 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
4370 | (match_operand:DF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4371 | "TARGET_HARD_FLOAT" |
4372 | "") | |
4373 | ||
4374 | (define_insn "*muldf3" | |
4375 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 4376 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4377 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4378 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4379 | "@ | |
d40c829f UW |
4380 | mdbr\t%0,%2 |
4381 | mdb\t%0,%2" | |
ce50cae8 | 4382 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4383 | (set_attr "type" "fmuld")]) |
9db1d521 HP |
4384 | |
4385 | (define_insn "*muldf3_ibm" | |
4386 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 4387 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4388 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4389 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4390 | "@ | |
d40c829f UW |
4391 | mdr\t%0,%2 |
4392 | md\t%0,%2" | |
9db1d521 | 4393 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4394 | (set_attr "type" "fmuld")]) |
9db1d521 | 4395 | |
a1b892b5 AK |
4396 | (define_insn "*fmadddf" |
4397 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4398 | (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f") | |
4399 | (match_operand:DF 2 "nonimmediate_operand" "f,R")) | |
4400 | (match_operand:DF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4401 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4402 | "@ |
4403 | madbr\t%0,%1,%2 | |
4404 | madb\t%0,%1,%2" | |
4405 | [(set_attr "op_type" "RRE,RXE") | |
4406 | (set_attr "type" "fmuld")]) | |
4407 | ||
4408 | (define_insn "*fmsubdf" | |
4409 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4410 | (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f") | |
4411 | (match_operand:DF 2 "nonimmediate_operand" "f,R")) | |
4412 | (match_operand:DF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4413 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4414 | "@ |
4415 | msdbr\t%0,%1,%2 | |
4416 | msdb\t%0,%1,%2" | |
4417 | [(set_attr "op_type" "RRE,RXE") | |
4418 | (set_attr "type" "fmuld")]) | |
4419 | ||
9db1d521 HP |
4420 | ; |
4421 | ; mulsf3 instruction pattern(s). | |
4422 | ; | |
4423 | ||
4424 | (define_expand "mulsf3" | |
553e5ce9 UW |
4425 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
4426 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
4427 | (match_operand:SF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4428 | "TARGET_HARD_FLOAT" |
4429 | "") | |
4430 | ||
4431 | (define_insn "*mulsf3" | |
4432 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 4433 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4434 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4435 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4436 | "@ | |
d40c829f UW |
4437 | meebr\t%0,%2 |
4438 | meeb\t%0,%2" | |
ce50cae8 | 4439 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4440 | (set_attr "type" "fmuls")]) |
9db1d521 HP |
4441 | |
4442 | (define_insn "*mulsf3_ibm" | |
4443 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 4444 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4445 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4446 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4447 | "@ | |
d40c829f UW |
4448 | mer\t%0,%2 |
4449 | me\t%0,%2" | |
9db1d521 | 4450 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4451 | (set_attr "type" "fmuls")]) |
9db1d521 | 4452 | |
a1b892b5 AK |
4453 | (define_insn "*fmaddsf" |
4454 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4455 | (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f") | |
4456 | (match_operand:SF 2 "nonimmediate_operand" "f,R")) | |
4457 | (match_operand:SF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4458 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4459 | "@ |
4460 | maebr\t%0,%1,%2 | |
4461 | maeb\t%0,%1,%2" | |
4462 | [(set_attr "op_type" "RRE,RXE") | |
4463 | (set_attr "type" "fmuls")]) | |
4464 | ||
4465 | (define_insn "*fmsubsf" | |
4466 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4467 | (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f") | |
4468 | (match_operand:SF 2 "nonimmediate_operand" "f,R")) | |
4469 | (match_operand:SF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4470 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4471 | "@ |
4472 | msebr\t%0,%1,%2 | |
4473 | mseb\t%0,%1,%2" | |
4474 | [(set_attr "op_type" "RRE,RXE") | |
4475 | (set_attr "type" "fmuls")]) | |
9db1d521 HP |
4476 | |
4477 | ;; | |
4478 | ;;- Divide and modulo instructions. | |
4479 | ;; | |
4480 | ||
4481 | ; | |
4023fb28 | 4482 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
4483 | ; |
4484 | ||
4023fb28 UW |
4485 | (define_expand "divmoddi4" |
4486 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 4487 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
4488 | (match_operand:DI 2 "general_operand" ""))) |
4489 | (set (match_operand:DI 3 "general_operand" "") | |
4490 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
4491 | (clobber (match_dup 4))] | |
9db1d521 | 4492 | "TARGET_64BIT" |
9db1d521 | 4493 | { |
f1e77d83 | 4494 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
4495 | |
4496 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
4497 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
4498 | |
4499 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 4500 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
4501 | |
4502 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4503 | REG_NOTES (insn) = | |
4504 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4505 | ||
4506 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4507 | REG_NOTES (insn) = | |
4508 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4509 | |
9db1d521 | 4510 | DONE; |
10bbf137 | 4511 | }) |
9db1d521 HP |
4512 | |
4513 | (define_insn "divmodtidi3" | |
4023fb28 UW |
4514 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
4515 | (ior:TI | |
4516 | (zero_extend:TI | |
f1e77d83 | 4517 | (div:DI (match_operand:DI 1 "register_operand" "0,0") |
4023fb28 UW |
4518 | (match_operand:DI 2 "general_operand" "d,m"))) |
4519 | (ashift:TI | |
4520 | (zero_extend:TI | |
f1e77d83 | 4521 | (mod:DI (match_dup 1) |
4023fb28 UW |
4522 | (match_dup 2))) |
4523 | (const_int 64))))] | |
9db1d521 HP |
4524 | "TARGET_64BIT" |
4525 | "@ | |
d40c829f UW |
4526 | dsgr\t%0,%2 |
4527 | dsg\t%0,%2" | |
d3632d41 | 4528 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4529 | (set_attr "type" "idiv")]) |
9db1d521 | 4530 | |
4023fb28 UW |
4531 | (define_insn "divmodtisi3" |
4532 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
4533 | (ior:TI | |
4534 | (zero_extend:TI | |
f1e77d83 | 4535 | (div:DI (match_operand:DI 1 "register_operand" "0,0") |
4023fb28 UW |
4536 | (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")))) |
4537 | (ashift:TI | |
4538 | (zero_extend:TI | |
f1e77d83 | 4539 | (mod:DI (match_dup 1) |
4023fb28 UW |
4540 | (sign_extend:DI (match_dup 2)))) |
4541 | (const_int 64))))] | |
9db1d521 | 4542 | "TARGET_64BIT" |
4023fb28 | 4543 | "@ |
d40c829f UW |
4544 | dsgfr\t%0,%2 |
4545 | dsgf\t%0,%2" | |
d3632d41 | 4546 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4547 | (set_attr "type" "idiv")]) |
9db1d521 | 4548 | |
4023fb28 UW |
4549 | ; |
4550 | ; udivmoddi4 instruction pattern(s). | |
4551 | ; | |
9db1d521 | 4552 | |
4023fb28 UW |
4553 | (define_expand "udivmoddi4" |
4554 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
4555 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
4556 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
4557 | (set (match_operand:DI 3 "general_operand" "") | |
4558 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
4559 | (clobber (match_dup 4))] | |
9db1d521 | 4560 | "TARGET_64BIT" |
9db1d521 | 4561 | { |
4023fb28 UW |
4562 | rtx insn, div_equal, mod_equal, equal; |
4563 | ||
4564 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
4565 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
4566 | equal = gen_rtx_IOR (TImode, | |
4567 | gen_rtx_ZERO_EXTEND (TImode, div_equal), | |
4568 | gen_rtx_ASHIFT (TImode, | |
4569 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
4570 | GEN_INT (64))); | |
4571 | ||
4572 | operands[4] = gen_reg_rtx(TImode); | |
4573 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4574 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); | |
4575 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
4576 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); | |
4577 | REG_NOTES (insn) = | |
4578 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4579 | ||
4580 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4581 | REG_NOTES (insn) = | |
4582 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4583 | ||
4584 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4585 | REG_NOTES (insn) = | |
4586 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4587 | |
9db1d521 | 4588 | DONE; |
10bbf137 | 4589 | }) |
9db1d521 HP |
4590 | |
4591 | (define_insn "udivmodtidi3" | |
4023fb28 | 4592 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
c7453384 | 4593 | (ior:TI (zero_extend:TI |
4023fb28 UW |
4594 | (truncate:DI |
4595 | (udiv:TI (match_operand:TI 1 "register_operand" "0,0") | |
4596 | (zero_extend:TI | |
4597 | (match_operand:DI 2 "nonimmediate_operand" "d,m"))))) | |
4598 | (ashift:TI | |
4599 | (zero_extend:TI | |
4600 | (truncate:DI | |
4601 | (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2))))) | |
4602 | (const_int 64))))] | |
9db1d521 HP |
4603 | "TARGET_64BIT" |
4604 | "@ | |
d40c829f UW |
4605 | dlgr\t%0,%2 |
4606 | dlg\t%0,%2" | |
d3632d41 | 4607 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4608 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4609 | |
4610 | ; | |
4023fb28 | 4611 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
4612 | ; |
4613 | ||
4023fb28 UW |
4614 | (define_expand "divmodsi4" |
4615 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4616 | (div:SI (match_operand:SI 1 "general_operand" "") | |
4617 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4618 | (set (match_operand:SI 3 "general_operand" "") | |
4619 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
4620 | (clobber (match_dup 4))] | |
9db1d521 | 4621 | "!TARGET_64BIT" |
9db1d521 | 4622 | { |
4023fb28 UW |
4623 | rtx insn, div_equal, mod_equal, equal; |
4624 | ||
4625 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
4626 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
4627 | equal = gen_rtx_IOR (DImode, | |
4628 | gen_rtx_ZERO_EXTEND (DImode, div_equal), | |
4629 | gen_rtx_ASHIFT (DImode, | |
4630 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
4631 | GEN_INT (32))); | |
4632 | ||
4633 | operands[4] = gen_reg_rtx(DImode); | |
4634 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
4635 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); | |
4636 | REG_NOTES (insn) = | |
4637 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4638 | ||
4639 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4640 | REG_NOTES (insn) = | |
4641 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4642 | ||
4643 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4644 | REG_NOTES (insn) = | |
4645 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4646 | |
9db1d521 | 4647 | DONE; |
10bbf137 | 4648 | }) |
9db1d521 HP |
4649 | |
4650 | (define_insn "divmoddisi3" | |
4023fb28 UW |
4651 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
4652 | (ior:DI (zero_extend:DI | |
4653 | (truncate:SI | |
4654 | (div:DI (match_operand:DI 1 "register_operand" "0,0") | |
c7453384 | 4655 | (sign_extend:DI |
d3632d41 | 4656 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
4023fb28 UW |
4657 | (ashift:DI |
4658 | (zero_extend:DI | |
4659 | (truncate:SI | |
4660 | (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2))))) | |
4661 | (const_int 32))))] | |
9db1d521 HP |
4662 | "!TARGET_64BIT" |
4663 | "@ | |
d40c829f UW |
4664 | dr\t%0,%2 |
4665 | d\t%0,%2" | |
9db1d521 | 4666 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4667 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4668 | |
4669 | ; | |
4670 | ; udivsi3 and umodsi3 instruction pattern(s). | |
4671 | ; | |
4672 | ||
f1e77d83 UW |
4673 | (define_expand "udivmodsi4" |
4674 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4675 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4676 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4677 | (set (match_operand:SI 3 "general_operand" "") | |
4678 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
4679 | (clobber (match_dup 4))] | |
4680 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4681 | { | |
4682 | rtx insn, div_equal, mod_equal, equal; | |
4683 | ||
4684 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4685 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4686 | equal = gen_rtx_IOR (DImode, | |
4687 | gen_rtx_ZERO_EXTEND (DImode, div_equal), | |
4688 | gen_rtx_ASHIFT (DImode, | |
4689 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
4690 | GEN_INT (32))); | |
4691 | ||
4692 | operands[4] = gen_reg_rtx(DImode); | |
4693 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4694 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); | |
4695 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
4696 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); | |
4697 | REG_NOTES (insn) = | |
4698 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4699 | ||
4700 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4701 | REG_NOTES (insn) = | |
4702 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4703 | ||
4704 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4705 | REG_NOTES (insn) = | |
4706 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
4707 | ||
4708 | DONE; | |
4709 | }) | |
4710 | ||
4711 | (define_insn "udivmoddisi3" | |
4712 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4713 | (ior:DI (zero_extend:DI | |
4714 | (truncate:SI | |
4715 | (udiv:DI (match_operand:DI 1 "register_operand" "0,0") | |
4716 | (zero_extend:DI | |
4717 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))) | |
4718 | (ashift:DI | |
4719 | (zero_extend:DI | |
4720 | (truncate:SI | |
4721 | (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2))))) | |
4722 | (const_int 32))))] | |
4723 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4724 | "@ | |
4725 | dlr\t%0,%2 | |
4726 | dl\t%0,%2" | |
4727 | [(set_attr "op_type" "RRE,RXY") | |
4728 | (set_attr "type" "idiv")]) | |
4023fb28 | 4729 | |
9db1d521 HP |
4730 | (define_expand "udivsi3" |
4731 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4732 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
4733 | (match_operand:SI 2 "general_operand" ""))) |
4734 | (clobber (match_dup 3))] | |
f1e77d83 | 4735 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 4736 | { |
4023fb28 UW |
4737 | rtx insn, udiv_equal, umod_equal, equal; |
4738 | ||
4739 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4740 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4741 | equal = gen_rtx_IOR (DImode, | |
4742 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal), | |
4743 | gen_rtx_ASHIFT (DImode, | |
4744 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
4745 | GEN_INT (32))); | |
9db1d521 | 4746 | |
4023fb28 | 4747 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
4748 | |
4749 | if (CONSTANT_P (operands[2])) | |
4750 | { | |
4751 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
4752 | { | |
4753 | rtx label1 = gen_label_rtx (); | |
4754 | ||
4023fb28 UW |
4755 | operands[1] = make_safe_from (operands[1], operands[0]); |
4756 | emit_move_insn (operands[0], const0_rtx); | |
4757 | emit_insn (gen_cmpsi (operands[1], operands[2])); | |
9db1d521 | 4758 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 | 4759 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
4760 | emit_label (label1); |
4761 | } | |
4762 | else | |
4763 | { | |
c7453384 EC |
4764 | operands[2] = force_reg (SImode, operands[2]); |
4765 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4766 | |
4767 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4768 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4769 | operands[2])); | |
4770 | REG_NOTES (insn) = | |
4771 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4772 | |
4773 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4774 | gen_lowpart (SImode, operands[3])); |
4775 | REG_NOTES (insn) = | |
c7453384 | 4776 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4777 | udiv_equal, REG_NOTES (insn)); |
9db1d521 HP |
4778 | } |
4779 | } | |
4780 | else | |
c7453384 | 4781 | { |
9db1d521 HP |
4782 | rtx label1 = gen_label_rtx (); |
4783 | rtx label2 = gen_label_rtx (); | |
4784 | rtx label3 = gen_label_rtx (); | |
4785 | ||
c7453384 EC |
4786 | operands[1] = force_reg (SImode, operands[1]); |
4787 | operands[1] = make_safe_from (operands[1], operands[0]); | |
4788 | operands[2] = force_reg (SImode, operands[2]); | |
4789 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4790 | |
4791 | emit_move_insn (operands[0], const0_rtx); | |
9db1d521 HP |
4792 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
4793 | emit_jump_insn (gen_bgtu (label3)); | |
4794 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4795 | emit_jump_insn (gen_blt (label2)); | |
4796 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4797 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
4798 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
4799 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4800 | operands[2])); | |
4801 | REG_NOTES (insn) = | |
4802 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4803 | |
4804 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4805 | gen_lowpart (SImode, operands[3])); |
4806 | REG_NOTES (insn) = | |
c7453384 | 4807 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4808 | udiv_equal, REG_NOTES (insn)); |
f314b9b1 | 4809 | emit_jump (label3); |
9db1d521 | 4810 | emit_label (label1); |
4023fb28 | 4811 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 4812 | emit_jump (label3); |
9db1d521 | 4813 | emit_label (label2); |
4023fb28 | 4814 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
4815 | emit_label (label3); |
4816 | } | |
c7453384 | 4817 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 4818 | DONE; |
10bbf137 | 4819 | }) |
9db1d521 HP |
4820 | |
4821 | (define_expand "umodsi3" | |
4822 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4823 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
4824 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
4825 | (clobber (match_dup 3))] | |
f1e77d83 | 4826 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 4827 | { |
4023fb28 UW |
4828 | rtx insn, udiv_equal, umod_equal, equal; |
4829 | ||
4830 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4831 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4832 | equal = gen_rtx_IOR (DImode, | |
4833 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal), | |
4834 | gen_rtx_ASHIFT (DImode, | |
4835 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
4836 | GEN_INT (32))); | |
9db1d521 | 4837 | |
4023fb28 | 4838 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
4839 | |
4840 | if (CONSTANT_P (operands[2])) | |
4841 | { | |
4842 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
4843 | { | |
4844 | rtx label1 = gen_label_rtx (); | |
4845 | ||
4023fb28 UW |
4846 | operands[1] = make_safe_from (operands[1], operands[0]); |
4847 | emit_move_insn (operands[0], operands[1]); | |
4848 | emit_insn (gen_cmpsi (operands[0], operands[2])); | |
9db1d521 | 4849 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 UW |
4850 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
4851 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
4852 | emit_label (label1); |
4853 | } | |
4854 | else | |
4855 | { | |
c7453384 EC |
4856 | operands[2] = force_reg (SImode, operands[2]); |
4857 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4858 | |
4859 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4860 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4861 | operands[2])); | |
4862 | REG_NOTES (insn) = | |
4863 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4864 | |
4865 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4866 | gen_highpart (SImode, operands[3])); |
4867 | REG_NOTES (insn) = | |
c7453384 | 4868 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4869 | umod_equal, REG_NOTES (insn)); |
9db1d521 HP |
4870 | } |
4871 | } | |
4872 | else | |
4873 | { | |
4874 | rtx label1 = gen_label_rtx (); | |
4875 | rtx label2 = gen_label_rtx (); | |
4876 | rtx label3 = gen_label_rtx (); | |
4877 | ||
c7453384 EC |
4878 | operands[1] = force_reg (SImode, operands[1]); |
4879 | operands[1] = make_safe_from (operands[1], operands[0]); | |
4880 | operands[2] = force_reg (SImode, operands[2]); | |
4881 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 4882 | |
c7453384 | 4883 | emit_move_insn(operands[0], operands[1]); |
4023fb28 | 4884 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
9db1d521 HP |
4885 | emit_jump_insn (gen_bgtu (label3)); |
4886 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4887 | emit_jump_insn (gen_blt (label2)); | |
4888 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4889 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
4890 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
4891 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4892 | operands[2])); | |
4893 | REG_NOTES (insn) = | |
4894 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4895 | |
4896 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4897 | gen_highpart (SImode, operands[3])); |
4898 | REG_NOTES (insn) = | |
c7453384 | 4899 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4900 | umod_equal, REG_NOTES (insn)); |
f314b9b1 | 4901 | emit_jump (label3); |
9db1d521 | 4902 | emit_label (label1); |
4023fb28 | 4903 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 4904 | emit_jump (label3); |
9db1d521 | 4905 | emit_label (label2); |
4023fb28 | 4906 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
4907 | emit_label (label3); |
4908 | } | |
9db1d521 | 4909 | DONE; |
10bbf137 | 4910 | }) |
9db1d521 HP |
4911 | |
4912 | ; | |
4913 | ; divdf3 instruction pattern(s). | |
4914 | ; | |
4915 | ||
4916 | (define_expand "divdf3" | |
553e5ce9 UW |
4917 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
4918 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
4919 | (match_operand:DF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4920 | "TARGET_HARD_FLOAT" |
4921 | "") | |
4922 | ||
4923 | (define_insn "*divdf3" | |
4023fb28 UW |
4924 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
4925 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
553e5ce9 | 4926 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4927 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4928 | "@ | |
d40c829f UW |
4929 | ddbr\t%0,%2 |
4930 | ddb\t%0,%2" | |
ce50cae8 | 4931 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4932 | (set_attr "type" "fdivd")]) |
9db1d521 HP |
4933 | |
4934 | (define_insn "*divdf3_ibm" | |
4023fb28 UW |
4935 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
4936 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
553e5ce9 | 4937 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4938 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4939 | "@ | |
d40c829f UW |
4940 | ddr\t%0,%2 |
4941 | dd\t%0,%2" | |
9db1d521 | 4942 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4943 | (set_attr "type" "fdivd")]) |
9db1d521 HP |
4944 | |
4945 | ; | |
4946 | ; divsf3 instruction pattern(s). | |
4947 | ; | |
4948 | ||
4949 | (define_expand "divsf3" | |
553e5ce9 UW |
4950 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
4951 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
4952 | (match_operand:SF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4953 | "TARGET_HARD_FLOAT" |
4954 | "") | |
4955 | ||
4956 | (define_insn "*divsf3" | |
4023fb28 UW |
4957 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
4958 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
553e5ce9 | 4959 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4960 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4961 | "@ | |
d40c829f UW |
4962 | debr\t%0,%2 |
4963 | deb\t%0,%2" | |
ce50cae8 | 4964 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4965 | (set_attr "type" "fdivs")]) |
9db1d521 HP |
4966 | |
4967 | (define_insn "*divsf3" | |
4023fb28 UW |
4968 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
4969 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
553e5ce9 | 4970 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4971 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4972 | "@ | |
d40c829f UW |
4973 | der\t%0,%2 |
4974 | de\t%0,%2" | |
9db1d521 | 4975 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4976 | (set_attr "type" "fdivs")]) |
9db1d521 HP |
4977 | |
4978 | ||
4979 | ;; | |
4980 | ;;- And instructions. | |
4981 | ;; | |
4982 | ||
4983 | ; | |
4984 | ; anddi3 instruction pattern(s). | |
4985 | ; | |
4986 | ||
4987 | (define_insn "*anddi3_cc" | |
4988 | [(set (reg 33) | |
96fd3851 | 4989 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 4990 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 | 4991 | (const_int 0))) |
4023fb28 | 4992 | (set (match_operand:DI 0 "register_operand" "=d,d") |
9db1d521 HP |
4993 | (and:DI (match_dup 1) (match_dup 2)))] |
4994 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
4995 | "@ | |
d40c829f UW |
4996 | ngr\t%0,%2 |
4997 | ng\t%0,%2" | |
d3632d41 | 4998 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 HP |
4999 | |
5000 | (define_insn "*anddi3_cconly" | |
5001 | [(set (reg 33) | |
96fd3851 | 5002 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 5003 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 HP |
5004 | (const_int 0))) |
5005 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5006 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5007 | "@ | |
d40c829f UW |
5008 | ngr\t%0,%2 |
5009 | ng\t%0,%2" | |
d3632d41 | 5010 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 5011 | |
4023fb28 UW |
5012 | (define_insn "*anddi3_ni" |
5013 | [(set (match_operand:DI 0 "register_operand" "=d") | |
05b9aaaa | 5014 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "0") |
4023fb28 UW |
5015 | (match_operand:DI 2 "immediate_operand" "n"))) |
5016 | (clobber (reg:CC 33))] | |
5017 | "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0" | |
4023fb28 UW |
5018 | { |
5019 | int part = s390_single_hi (operands[2], DImode, -1); | |
5020 | operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part)); | |
5021 | ||
5022 | switch (part) | |
5023 | { | |
d40c829f UW |
5024 | case 0: return "nihh\t%0,%x2"; |
5025 | case 1: return "nihl\t%0,%x2"; | |
5026 | case 2: return "nilh\t%0,%x2"; | |
5027 | case 3: return "nill\t%0,%x2"; | |
4023fb28 UW |
5028 | default: abort (); |
5029 | } | |
10bbf137 | 5030 | } |
077dab3b | 5031 | [(set_attr "op_type" "RI")]) |
4023fb28 | 5032 | |
9db1d521 | 5033 | (define_insn "anddi3" |
4023fb28 | 5034 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
96fd3851 | 5035 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 5036 | (match_operand:DI 2 "general_operand" "d,m"))) |
9db1d521 HP |
5037 | (clobber (reg:CC 33))] |
5038 | "TARGET_64BIT" | |
5039 | "@ | |
d40c829f UW |
5040 | ngr\t%0,%2 |
5041 | ng\t%0,%2" | |
d3632d41 | 5042 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5043 | |
5044 | (define_insn "*anddi3_ss" | |
ccfc6cc8 | 5045 | [(set (match_operand:DI 0 "s_operand" "=Q") |
4023fb28 | 5046 | (and:DI (match_dup 0) |
ccfc6cc8 | 5047 | (match_operand:DI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5048 | (clobber (reg:CC 33))] |
5049 | "" | |
d40c829f | 5050 | "nc\t%O0(8,%R0),%1" |
077dab3b | 5051 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5052 | |
5053 | (define_insn "*anddi3_ss_inv" | |
ccfc6cc8 UW |
5054 | [(set (match_operand:DI 0 "s_operand" "=Q") |
5055 | (and:DI (match_operand:DI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
5056 | (match_dup 0))) |
5057 | (clobber (reg:CC 33))] | |
5058 | "" | |
d40c829f | 5059 | "nc\t%O0(8,%R0),%1" |
077dab3b | 5060 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5061 | |
5062 | ; | |
5063 | ; andsi3 instruction pattern(s). | |
5064 | ; | |
5065 | ||
5066 | (define_insn "*andsi3_cc" | |
5067 | [(set (reg 33) | |
d3632d41 UW |
5068 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5069 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 5070 | (const_int 0))) |
d3632d41 | 5071 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 HP |
5072 | (and:SI (match_dup 1) (match_dup 2)))] |
5073 | "s390_match_ccmode(insn, CCTmode)" | |
5074 | "@ | |
d40c829f UW |
5075 | nr\t%0,%2 |
5076 | n\t%0,%2 | |
5077 | ny\t%0,%2" | |
d3632d41 | 5078 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
5079 | |
5080 | (define_insn "*andsi3_cconly" | |
5081 | [(set (reg 33) | |
d3632d41 UW |
5082 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5083 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 5084 | (const_int 0))) |
d3632d41 | 5085 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
9db1d521 HP |
5086 | "s390_match_ccmode(insn, CCTmode)" |
5087 | "@ | |
d40c829f UW |
5088 | nr\t%0,%2 |
5089 | n\t%0,%2 | |
5090 | ny\t%0,%2" | |
d3632d41 | 5091 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 5092 | |
4023fb28 UW |
5093 | (define_insn "*andsi3_ni" |
5094 | [(set (match_operand:SI 0 "register_operand" "=d") | |
05b9aaaa | 5095 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
4023fb28 UW |
5096 | (match_operand:SI 2 "immediate_operand" "n"))) |
5097 | (clobber (reg:CC 33))] | |
9e8327e3 | 5098 | "TARGET_ZARCH && s390_single_hi (operands[2], SImode, -1) >= 0" |
4023fb28 UW |
5099 | { |
5100 | int part = s390_single_hi (operands[2], SImode, -1); | |
5101 | operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part)); | |
5102 | ||
5103 | switch (part) | |
5104 | { | |
d40c829f UW |
5105 | case 0: return "nilh\t%0,%x2"; |
5106 | case 1: return "nill\t%0,%x2"; | |
4023fb28 UW |
5107 | default: abort (); |
5108 | } | |
10bbf137 | 5109 | } |
077dab3b | 5110 | [(set_attr "op_type" "RI")]) |
4023fb28 | 5111 | |
9db1d521 | 5112 | (define_insn "andsi3" |
d3632d41 UW |
5113 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
5114 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") | |
5115 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
9db1d521 HP |
5116 | (clobber (reg:CC 33))] |
5117 | "" | |
5118 | "@ | |
d40c829f UW |
5119 | nr\t%0,%2 |
5120 | n\t%0,%2 | |
5121 | ny\t%0,%2" | |
d3632d41 | 5122 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5123 | |
5124 | (define_insn "*andsi3_ss" | |
ccfc6cc8 | 5125 | [(set (match_operand:SI 0 "s_operand" "=Q") |
4023fb28 | 5126 | (and:SI (match_dup 0) |
ccfc6cc8 | 5127 | (match_operand:SI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5128 | (clobber (reg:CC 33))] |
5129 | "" | |
d40c829f | 5130 | "nc\t%O0(4,%R0),%1" |
077dab3b | 5131 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5132 | |
5133 | (define_insn "*andsi3_ss_inv" | |
ccfc6cc8 UW |
5134 | [(set (match_operand:SI 0 "s_operand" "=Q") |
5135 | (and:SI (match_operand:SI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
5136 | (match_dup 0))) |
5137 | (clobber (reg:CC 33))] | |
5138 | "" | |
d40c829f | 5139 | "nc\t%O0(4,%R0),%1" |
077dab3b | 5140 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5141 | |
5142 | ; | |
5143 | ; andhi3 instruction pattern(s). | |
5144 | ; | |
5145 | ||
4023fb28 UW |
5146 | (define_insn "*andhi3_ni" |
5147 | [(set (match_operand:HI 0 "register_operand" "=d,d") | |
5148 | (and:HI (match_operand:HI 1 "register_operand" "%0,0") | |
5149 | (match_operand:HI 2 "nonmemory_operand" "d,n"))) | |
5150 | (clobber (reg:CC 33))] | |
9e8327e3 | 5151 | "TARGET_ZARCH" |
4023fb28 | 5152 | "@ |
d40c829f UW |
5153 | nr\t%0,%2 |
5154 | nill\t%0,%x2" | |
077dab3b | 5155 | [(set_attr "op_type" "RR,RI")]) |
4023fb28 UW |
5156 | |
5157 | (define_insn "andhi3" | |
5158 | [(set (match_operand:HI 0 "register_operand" "=d") | |
5159 | (and:HI (match_operand:HI 1 "register_operand" "%0") | |
5160 | (match_operand:HI 2 "nonmemory_operand" "d"))) | |
5161 | (clobber (reg:CC 33))] | |
9db1d521 | 5162 | "" |
d40c829f | 5163 | "nr\t%0,%2" |
077dab3b | 5164 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5165 | |
5166 | (define_insn "*andhi3_ss" | |
ccfc6cc8 | 5167 | [(set (match_operand:HI 0 "s_operand" "=Q") |
4023fb28 | 5168 | (and:HI (match_dup 0) |
ccfc6cc8 | 5169 | (match_operand:HI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5170 | (clobber (reg:CC 33))] |
5171 | "" | |
d40c829f | 5172 | "nc\t%O0(2,%R0),%1" |
077dab3b | 5173 | [(set_attr "op_type" "SS")]) |
9db1d521 | 5174 | |
4023fb28 | 5175 | (define_insn "*andhi3_ss_inv" |
ccfc6cc8 UW |
5176 | [(set (match_operand:HI 0 "s_operand" "=Q") |
5177 | (and:HI (match_operand:HI 1 "s_imm_operand" "Q") | |
4023fb28 | 5178 | (match_dup 0))) |
9db1d521 HP |
5179 | (clobber (reg:CC 33))] |
5180 | "" | |
d40c829f | 5181 | "nc\t%O0(2,%R0),%1" |
077dab3b | 5182 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5183 | |
5184 | ; | |
5185 | ; andqi3 instruction pattern(s). | |
5186 | ; | |
5187 | ||
4023fb28 UW |
5188 | (define_insn "*andqi3_ni" |
5189 | [(set (match_operand:QI 0 "register_operand" "=d,d") | |
5190 | (and:QI (match_operand:QI 1 "register_operand" "%0,0") | |
5191 | (match_operand:QI 2 "nonmemory_operand" "d,n"))) | |
5192 | (clobber (reg:CC 33))] | |
9e8327e3 | 5193 | "TARGET_ZARCH" |
4023fb28 | 5194 | "@ |
d40c829f UW |
5195 | nr\t%0,%2 |
5196 | nill\t%0,%b2" | |
077dab3b | 5197 | [(set_attr "op_type" "RR,RI")]) |
4023fb28 | 5198 | |
9db1d521 | 5199 | (define_insn "andqi3" |
4023fb28 UW |
5200 | [(set (match_operand:QI 0 "register_operand" "=d") |
5201 | (and:QI (match_operand:QI 1 "register_operand" "%0") | |
5202 | (match_operand:QI 2 "nonmemory_operand" "d"))) | |
5203 | (clobber (reg:CC 33))] | |
5204 | "" | |
d40c829f | 5205 | "nr\t%0,%2" |
077dab3b | 5206 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5207 | |
5208 | (define_insn "*andqi3_ss" | |
d3632d41 | 5209 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
4023fb28 | 5210 | (and:QI (match_dup 0) |
d3632d41 | 5211 | (match_operand:QI 1 "s_imm_operand" "n,n,Q"))) |
9db1d521 HP |
5212 | (clobber (reg:CC 33))] |
5213 | "" | |
5214 | "@ | |
d40c829f UW |
5215 | ni\t%0,%b1 |
5216 | niy\t%0,%b1 | |
5217 | nc\t%O0(1,%R0),%1" | |
d3632d41 | 5218 | [(set_attr "op_type" "SI,SIY,SS")]) |
4023fb28 UW |
5219 | |
5220 | (define_insn "*andqi3_ss_inv" | |
d3632d41 UW |
5221 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
5222 | (and:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q") | |
4023fb28 UW |
5223 | (match_dup 0))) |
5224 | (clobber (reg:CC 33))] | |
5225 | "" | |
5226 | "@ | |
d40c829f UW |
5227 | ni\t%0,%b1 |
5228 | niy\t%0,%b1 | |
5229 | nc\t%O0(1,%R0),%1" | |
d3632d41 | 5230 | [(set_attr "op_type" "SI,SIY,SS")]) |
9db1d521 HP |
5231 | |
5232 | ||
5233 | ;; | |
5234 | ;;- Bit set (inclusive or) instructions. | |
5235 | ;; | |
5236 | ||
5237 | ; | |
5238 | ; iordi3 instruction pattern(s). | |
5239 | ; | |
5240 | ||
4023fb28 UW |
5241 | (define_insn "*iordi3_cc" |
5242 | [(set (reg 33) | |
96fd3851 | 5243 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5244 | (match_operand:DI 2 "general_operand" "d,m")) |
5245 | (const_int 0))) | |
5246 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5247 | (ior:DI (match_dup 1) (match_dup 2)))] | |
5248 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5249 | "@ | |
d40c829f UW |
5250 | ogr\t%0,%2 |
5251 | og\t%0,%2" | |
d3632d41 | 5252 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5253 | |
5254 | (define_insn "*iordi3_cconly" | |
5255 | [(set (reg 33) | |
96fd3851 | 5256 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5257 | (match_operand:DI 2 "general_operand" "d,m")) |
5258 | (const_int 0))) | |
5259 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5260 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5261 | "@ | |
d40c829f UW |
5262 | ogr\t%0,%2 |
5263 | og\t%0,%2" | |
d3632d41 | 5264 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5265 | |
5266 | (define_insn "*iordi3_oi" | |
5267 | [(set (match_operand:DI 0 "register_operand" "=d") | |
c707d0b0 | 5268 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "0") |
4023fb28 UW |
5269 | (match_operand:DI 2 "immediate_operand" "n"))) |
5270 | (clobber (reg:CC 33))] | |
5271 | "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0" | |
4023fb28 UW |
5272 | { |
5273 | int part = s390_single_hi (operands[2], DImode, 0); | |
5274 | operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part)); | |
5275 | ||
5276 | switch (part) | |
5277 | { | |
d40c829f UW |
5278 | case 0: return "oihh\t%0,%x2"; |
5279 | case 1: return "oihl\t%0,%x2"; | |
5280 | case 2: return "oilh\t%0,%x2"; | |
5281 | case 3: return "oill\t%0,%x2"; | |
4023fb28 UW |
5282 | default: abort (); |
5283 | } | |
10bbf137 | 5284 | } |
077dab3b | 5285 | [(set_attr "op_type" "RI")]) |
4023fb28 | 5286 | |
9db1d521 | 5287 | (define_insn "iordi3" |
4023fb28 | 5288 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
96fd3851 | 5289 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 5290 | (match_operand:DI 2 "general_operand" "d,m"))) |
9db1d521 HP |
5291 | (clobber (reg:CC 33))] |
5292 | "TARGET_64BIT" | |
5293 | "@ | |
d40c829f UW |
5294 | ogr\t%0,%2 |
5295 | og\t%0,%2" | |
d3632d41 | 5296 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5297 | |
5298 | (define_insn "*iordi3_ss" | |
ccfc6cc8 | 5299 | [(set (match_operand:DI 0 "s_operand" "=Q") |
4023fb28 | 5300 | (ior:DI (match_dup 0) |
ccfc6cc8 | 5301 | (match_operand:DI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5302 | (clobber (reg:CC 33))] |
5303 | "" | |
d40c829f | 5304 | "oc\t%O0(8,%R0),%1" |
077dab3b | 5305 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5306 | |
5307 | (define_insn "*iordi3_ss_inv" | |
ccfc6cc8 UW |
5308 | [(set (match_operand:DI 0 "s_operand" "=Q") |
5309 | (ior:DI (match_operand:DI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
5310 | (match_dup 0))) |
5311 | (clobber (reg:CC 33))] | |
5312 | "" | |
d40c829f | 5313 | "oc\t%O0(8,%R0),%1" |
077dab3b | 5314 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5315 | |
5316 | ; | |
5317 | ; iorsi3 instruction pattern(s). | |
5318 | ; | |
5319 | ||
4023fb28 UW |
5320 | (define_insn "*iorsi3_cc" |
5321 | [(set (reg 33) | |
d3632d41 UW |
5322 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5323 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5324 | (const_int 0))) |
d3632d41 | 5325 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
4023fb28 UW |
5326 | (ior:SI (match_dup 1) (match_dup 2)))] |
5327 | "s390_match_ccmode(insn, CCTmode)" | |
5328 | "@ | |
d40c829f UW |
5329 | or\t%0,%2 |
5330 | o\t%0,%2 | |
5331 | oy\t%0,%2" | |
d3632d41 | 5332 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5333 | |
5334 | (define_insn "*iorsi3_cconly" | |
5335 | [(set (reg 33) | |
d3632d41 UW |
5336 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5337 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5338 | (const_int 0))) |
d3632d41 | 5339 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
4023fb28 UW |
5340 | "s390_match_ccmode(insn, CCTmode)" |
5341 | "@ | |
d40c829f UW |
5342 | or\t%0,%2 |
5343 | o\t%0,%2 | |
5344 | oy\t%0,%2" | |
d3632d41 | 5345 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5346 | |
5347 | (define_insn "*iorsi3_oi" | |
5348 | [(set (match_operand:SI 0 "register_operand" "=d") | |
c707d0b0 | 5349 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
4023fb28 UW |
5350 | (match_operand:SI 2 "immediate_operand" "n"))) |
5351 | (clobber (reg:CC 33))] | |
9e8327e3 | 5352 | "TARGET_ZARCH && s390_single_hi (operands[2], SImode, 0) >= 0" |
4023fb28 UW |
5353 | { |
5354 | int part = s390_single_hi (operands[2], SImode, 0); | |
5355 | operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part)); | |
5356 | ||
5357 | switch (part) | |
5358 | { | |
d40c829f UW |
5359 | case 0: return "oilh\t%0,%x2"; |
5360 | case 1: return "oill\t%0,%x2"; | |
4023fb28 UW |
5361 | default: abort (); |
5362 | } | |
10bbf137 | 5363 | } |
077dab3b | 5364 | [(set_attr "op_type" "RI")]) |
4023fb28 UW |
5365 | |
5366 | (define_insn "iorsi3" | |
d3632d41 UW |
5367 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
5368 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") | |
5369 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
4023fb28 UW |
5370 | (clobber (reg:CC 33))] |
5371 | "" | |
5372 | "@ | |
d40c829f UW |
5373 | or\t%0,%2 |
5374 | o\t%0,%2 | |
5375 | oy\t%0,%2" | |
d3632d41 | 5376 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5377 | |
5378 | (define_insn "*iorsi3_ss" | |
ccfc6cc8 | 5379 | [(set (match_operand:SI 0 "s_operand" "=Q") |
4023fb28 | 5380 | (ior:SI (match_dup 0) |
ccfc6cc8 | 5381 | (match_operand:SI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5382 | (clobber (reg:CC 33))] |
5383 | "" | |
d40c829f | 5384 | "oc\t%O0(4,%R0),%1" |
077dab3b | 5385 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5386 | |
5387 | (define_insn "*iorsi3_ss_inv" | |
ccfc6cc8 UW |
5388 | [(set (match_operand:SI 0 "s_operand" "=Q") |
5389 | (ior:SI (match_operand:SI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
5390 | (match_dup 0))) |
5391 | (clobber (reg:CC 33))] | |
5392 | "" | |
d40c829f | 5393 | "oc\t%O0(4,%R0),%1" |
077dab3b | 5394 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5395 | |
5396 | ; | |
5397 | ; iorhi3 instruction pattern(s). | |
5398 | ; | |
5399 | ||
5400 | (define_insn "*iorhi3_oi" | |
5401 | [(set (match_operand:HI 0 "register_operand" "=d,d") | |
5402 | (ior:HI (match_operand:HI 1 "register_operand" "%0,0") | |
5403 | (match_operand:HI 2 "nonmemory_operand" "d,n"))) | |
5404 | (clobber (reg:CC 33))] | |
9e8327e3 | 5405 | "TARGET_ZARCH" |
4023fb28 | 5406 | "@ |
d40c829f UW |
5407 | or\t%0,%2 |
5408 | oill\t%0,%x2" | |
077dab3b | 5409 | [(set_attr "op_type" "RR,RI")]) |
4023fb28 UW |
5410 | |
5411 | (define_insn "iorhi3" | |
5412 | [(set (match_operand:HI 0 "register_operand" "=d") | |
5413 | (ior:HI (match_operand:HI 1 "register_operand" "%0") | |
5414 | (match_operand:HI 2 "nonmemory_operand" "d"))) | |
5415 | (clobber (reg:CC 33))] | |
9db1d521 | 5416 | "" |
d40c829f | 5417 | "or\t%0,%2" |
077dab3b | 5418 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5419 | |
5420 | (define_insn "*iorhi3_ss" | |
ccfc6cc8 | 5421 | [(set (match_operand:HI 0 "s_operand" "=Q") |
4023fb28 | 5422 | (ior:HI (match_dup 0) |
ccfc6cc8 | 5423 | (match_operand:HI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5424 | (clobber (reg:CC 33))] |
5425 | "" | |
d40c829f | 5426 | "oc\t%O0(2,%R0),%1" |
077dab3b | 5427 | [(set_attr "op_type" "SS")]) |
9db1d521 | 5428 | |
4023fb28 | 5429 | (define_insn "*iorhi3_ss_inv" |
ccfc6cc8 UW |
5430 | [(set (match_operand:HI 0 "s_operand" "=Q") |
5431 | (ior:HI (match_operand:HI 1 "s_imm_operand" "Q") | |
4023fb28 | 5432 | (match_dup 0))) |
9db1d521 HP |
5433 | (clobber (reg:CC 33))] |
5434 | "" | |
d40c829f | 5435 | "oc\t%O0(2,%R0),%1" |
077dab3b | 5436 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5437 | |
5438 | ; | |
4023fb28 | 5439 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
5440 | ; |
5441 | ||
4023fb28 UW |
5442 | (define_insn "*iorqi3_oi" |
5443 | [(set (match_operand:QI 0 "register_operand" "=d,d") | |
5444 | (ior:QI (match_operand:QI 1 "register_operand" "%0,0") | |
5445 | (match_operand:QI 2 "nonmemory_operand" "d,n"))) | |
5446 | (clobber (reg:CC 33))] | |
9e8327e3 | 5447 | "TARGET_ZARCH" |
4023fb28 | 5448 | "@ |
d40c829f UW |
5449 | or\t%0,%2 |
5450 | oill\t%0,%b2" | |
077dab3b | 5451 | [(set_attr "op_type" "RR,RI")]) |
9db1d521 | 5452 | |
4023fb28 UW |
5453 | (define_insn "iorqi3" |
5454 | [(set (match_operand:QI 0 "register_operand" "=d") | |
5455 | (ior:QI (match_operand:QI 1 "register_operand" "%0") | |
5456 | (match_operand:QI 2 "nonmemory_operand" "d"))) | |
5457 | (clobber (reg:CC 33))] | |
5458 | "" | |
d40c829f | 5459 | "or\t%0,%2" |
077dab3b | 5460 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5461 | |
5462 | (define_insn "*iorqi3_ss" | |
d3632d41 | 5463 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
4023fb28 | 5464 | (ior:QI (match_dup 0) |
d3632d41 | 5465 | (match_operand:QI 1 "s_imm_operand" "n,n,Q"))) |
9db1d521 HP |
5466 | (clobber (reg:CC 33))] |
5467 | "" | |
5468 | "@ | |
d40c829f UW |
5469 | oi\t%0,%b1 |
5470 | oiy\t%0,%b1 | |
5471 | oc\t%O0(1,%R0),%1" | |
d3632d41 | 5472 | [(set_attr "op_type" "SI,SIY,SS")]) |
9db1d521 | 5473 | |
4023fb28 | 5474 | (define_insn "*iorqi3_ss_inv" |
d3632d41 UW |
5475 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
5476 | (ior:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q") | |
4023fb28 | 5477 | (match_dup 0))) |
9db1d521 HP |
5478 | (clobber (reg:CC 33))] |
5479 | "" | |
5480 | "@ | |
d40c829f UW |
5481 | oi\t%0,%b1 |
5482 | oiy\t%0,%b1 | |
5483 | oc\t%O0(1,%R0),%1" | |
d3632d41 | 5484 | [(set_attr "op_type" "SI,SIY,SS")]) |
9db1d521 HP |
5485 | |
5486 | ||
5487 | ;; | |
5488 | ;;- Xor instructions. | |
5489 | ;; | |
5490 | ||
5491 | ; | |
5492 | ; xordi3 instruction pattern(s). | |
5493 | ; | |
5494 | ||
4023fb28 UW |
5495 | (define_insn "*xordi3_cc" |
5496 | [(set (reg 33) | |
96fd3851 | 5497 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5498 | (match_operand:DI 2 "general_operand" "d,m")) |
5499 | (const_int 0))) | |
5500 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5501 | (xor:DI (match_dup 1) (match_dup 2)))] | |
5502 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5503 | "@ | |
d40c829f UW |
5504 | xgr\t%0,%2 |
5505 | xg\t%0,%2" | |
d3632d41 | 5506 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5507 | |
5508 | (define_insn "*xordi3_cconly" | |
5509 | [(set (reg 33) | |
96fd3851 | 5510 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5511 | (match_operand:DI 2 "general_operand" "d,m")) |
5512 | (const_int 0))) | |
5513 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5514 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5515 | "@ | |
d40c829f UW |
5516 | xgr\t%0,%2 |
5517 | xr\t%0,%2" | |
d3632d41 | 5518 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 5519 | |
9db1d521 | 5520 | (define_insn "xordi3" |
4023fb28 | 5521 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
96fd3851 | 5522 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 5523 | (match_operand:DI 2 "general_operand" "d,m"))) |
9db1d521 HP |
5524 | (clobber (reg:CC 33))] |
5525 | "TARGET_64BIT" | |
5526 | "@ | |
d40c829f UW |
5527 | xgr\t%0,%2 |
5528 | xg\t%0,%2" | |
d3632d41 | 5529 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5530 | |
5531 | (define_insn "*xordi3_ss" | |
ccfc6cc8 | 5532 | [(set (match_operand:DI 0 "s_operand" "=Q") |
4023fb28 | 5533 | (xor:DI (match_dup 0) |
ccfc6cc8 | 5534 | (match_operand:DI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5535 | (clobber (reg:CC 33))] |
5536 | "" | |
d40c829f | 5537 | "xc\t%O0(8,%R0),%1" |
077dab3b | 5538 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5539 | |
5540 | (define_insn "*xordi3_ss_inv" | |
ccfc6cc8 UW |
5541 | [(set (match_operand:DI 0 "s_operand" "=Q") |
5542 | (xor:DI (match_operand:DI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
5543 | (match_dup 0))) |
5544 | (clobber (reg:CC 33))] | |
5545 | "" | |
d40c829f | 5546 | "xc\t%O0(8,%R0),%1" |
077dab3b | 5547 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5548 | |
5549 | ; | |
5550 | ; xorsi3 instruction pattern(s). | |
5551 | ; | |
5552 | ||
4023fb28 UW |
5553 | (define_insn "*xorsi3_cc" |
5554 | [(set (reg 33) | |
d3632d41 UW |
5555 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5556 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5557 | (const_int 0))) |
d3632d41 | 5558 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
4023fb28 UW |
5559 | (xor:SI (match_dup 1) (match_dup 2)))] |
5560 | "s390_match_ccmode(insn, CCTmode)" | |
5561 | "@ | |
d40c829f UW |
5562 | xr\t%0,%2 |
5563 | x\t%0,%2 | |
5564 | xy\t%0,%2" | |
d3632d41 | 5565 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5566 | |
5567 | (define_insn "*xorsi3_cconly" | |
5568 | [(set (reg 33) | |
d3632d41 UW |
5569 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5570 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5571 | (const_int 0))) |
d3632d41 | 5572 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
4023fb28 UW |
5573 | "s390_match_ccmode(insn, CCTmode)" |
5574 | "@ | |
d40c829f UW |
5575 | xr\t%0,%2 |
5576 | x\t%0,%2 | |
5577 | xy\t%0,%2" | |
d3632d41 | 5578 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 5579 | |
4023fb28 | 5580 | (define_insn "xorsi3" |
d3632d41 UW |
5581 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
5582 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") | |
5583 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
9db1d521 HP |
5584 | (clobber (reg:CC 33))] |
5585 | "" | |
5586 | "@ | |
d40c829f UW |
5587 | xr\t%0,%2 |
5588 | x\t%0,%2 | |
5589 | xy\t%0,%2" | |
d3632d41 | 5590 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5591 | |
5592 | (define_insn "*xorsi3_ss" | |
ccfc6cc8 | 5593 | [(set (match_operand:SI 0 "s_operand" "=Q") |
4023fb28 | 5594 | (xor:SI (match_dup 0) |
ccfc6cc8 | 5595 | (match_operand:SI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5596 | (clobber (reg:CC 33))] |
5597 | "" | |
d40c829f | 5598 | "xc\t%O0(4,%R0),%1" |
077dab3b | 5599 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5600 | |
5601 | (define_insn "*xorsi3_ss_inv" | |
ccfc6cc8 UW |
5602 | [(set (match_operand:SI 0 "s_operand" "=Q") |
5603 | (xor:SI (match_operand:SI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
5604 | (match_dup 0))) |
5605 | (clobber (reg:CC 33))] | |
5606 | "" | |
d40c829f | 5607 | "xc\t%O0(4,%R0),%1" |
077dab3b | 5608 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5609 | |
5610 | ; | |
5611 | ; xorhi3 instruction pattern(s). | |
5612 | ; | |
5613 | ||
4023fb28 UW |
5614 | (define_insn "xorhi3" |
5615 | [(set (match_operand:HI 0 "register_operand" "=d") | |
5616 | (xor:HI (match_operand:HI 1 "register_operand" "%0") | |
5617 | (match_operand:HI 2 "nonmemory_operand" "d"))) | |
5618 | (clobber (reg:CC 33))] | |
9db1d521 | 5619 | "" |
d40c829f | 5620 | "xr\t%0,%2" |
d3632d41 | 5621 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5622 | |
5623 | (define_insn "*xorhi3_ss" | |
ccfc6cc8 | 5624 | [(set (match_operand:HI 0 "s_operand" "=Q") |
4023fb28 | 5625 | (xor:HI (match_dup 0) |
ccfc6cc8 | 5626 | (match_operand:HI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5627 | (clobber (reg:CC 33))] |
5628 | "" | |
d40c829f | 5629 | "xc\t%O0(2,%R0),%1" |
077dab3b | 5630 | [(set_attr "op_type" "SS")]) |
9db1d521 | 5631 | |
4023fb28 | 5632 | (define_insn "*xorhi3_ss_inv" |
ccfc6cc8 UW |
5633 | [(set (match_operand:HI 0 "s_operand" "=Q") |
5634 | (xor:HI (match_operand:HI 1 "s_imm_operand" "Q") | |
4023fb28 | 5635 | (match_dup 0))) |
9db1d521 HP |
5636 | (clobber (reg:CC 33))] |
5637 | "" | |
d40c829f | 5638 | "xc\t%O0(2,%R0),%1" |
077dab3b | 5639 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5640 | |
5641 | ; | |
5642 | ; xorqi3 instruction pattern(s). | |
5643 | ; | |
5644 | ||
5645 | (define_insn "xorqi3" | |
4023fb28 UW |
5646 | [(set (match_operand:QI 0 "register_operand" "=d") |
5647 | (xor:QI (match_operand:QI 1 "register_operand" "%0") | |
5648 | (match_operand:QI 2 "nonmemory_operand" "d"))) | |
5649 | (clobber (reg:CC 33))] | |
5650 | "" | |
d40c829f | 5651 | "xr\t%0,%2" |
077dab3b | 5652 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5653 | |
5654 | (define_insn "*xorqi3_ss" | |
d3632d41 | 5655 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
4023fb28 | 5656 | (xor:QI (match_dup 0) |
d3632d41 | 5657 | (match_operand:QI 1 "s_imm_operand" "n,n,Q"))) |
9db1d521 HP |
5658 | (clobber (reg:CC 33))] |
5659 | "" | |
5660 | "@ | |
d40c829f UW |
5661 | xi\t%0,%b1 |
5662 | xiy\t%0,%b1 | |
5663 | xc\t%O0(1,%R0),%1" | |
d3632d41 | 5664 | [(set_attr "op_type" "SI,SIY,SS")]) |
4023fb28 UW |
5665 | |
5666 | (define_insn "*xorqi3_ss_inv" | |
d3632d41 UW |
5667 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
5668 | (xor:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q") | |
4023fb28 UW |
5669 | (match_dup 0))) |
5670 | (clobber (reg:CC 33))] | |
5671 | "" | |
5672 | "@ | |
d40c829f UW |
5673 | xi\t%0,%b1 |
5674 | xiy\t%0,%b1 | |
5675 | xc\t%O0(1,%R0),%1" | |
d3632d41 | 5676 | [(set_attr "op_type" "SI,SIY,SS")]) |
9db1d521 HP |
5677 | |
5678 | ||
5679 | ;; | |
5680 | ;;- Negate instructions. | |
5681 | ;; | |
5682 | ||
5683 | ; | |
5684 | ; negdi2 instruction pattern(s). | |
5685 | ; | |
5686 | ||
5687 | (define_expand "negdi2" | |
5688 | [(parallel | |
5689 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5690 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
5691 | (clobber (reg:CC 33))])] | |
5692 | "" | |
5693 | "") | |
5694 | ||
5695 | (define_insn "*negdi2_64" | |
5696 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5697 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
5698 | (clobber (reg:CC 33))] | |
5699 | "TARGET_64BIT" | |
d40c829f | 5700 | "lcgr\t%0,%1" |
f2d3c02a | 5701 | [(set_attr "op_type" "RR")]) |
9db1d521 HP |
5702 | |
5703 | (define_insn "*negdi2_31" | |
5704 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5705 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
5706 | (clobber (reg:CC 33))] | |
5707 | "!TARGET_64BIT" | |
9db1d521 HP |
5708 | { |
5709 | rtx xop[1]; | |
5710 | xop[0] = gen_label_rtx (); | |
d40c829f UW |
5711 | output_asm_insn ("lcr\t%0,%1", operands); |
5712 | output_asm_insn ("lcr\t%N0,%N1", operands); | |
5713 | output_asm_insn ("je\t%l0", xop); | |
5714 | output_asm_insn ("bctr\t%0,0", operands); | |
47798692 | 5715 | targetm.asm_out.internal_label (asm_out_file, "L", |
9db1d521 | 5716 | CODE_LABEL_NUMBER (xop[0])); |
10bbf137 UW |
5717 | return ""; |
5718 | } | |
9db1d521 | 5719 | [(set_attr "op_type" "NN") |
4023fb28 UW |
5720 | (set_attr "type" "other") |
5721 | (set_attr "length" "10")]) | |
9db1d521 HP |
5722 | |
5723 | ; | |
5724 | ; negsi2 instruction pattern(s). | |
5725 | ; | |
5726 | ||
5727 | (define_insn "negsi2" | |
5728 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5729 | (neg:SI (match_operand:SI 1 "register_operand" "d"))) | |
5730 | (clobber (reg:CC 33))] | |
5731 | "" | |
d40c829f | 5732 | "lcr\t%0,%1" |
f2d3c02a | 5733 | [(set_attr "op_type" "RR")]) |
9db1d521 HP |
5734 | |
5735 | ; | |
5736 | ; negdf2 instruction pattern(s). | |
5737 | ; | |
5738 | ||
5739 | (define_expand "negdf2" | |
5740 | [(parallel | |
5741 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5742 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
5743 | (clobber (reg:CC 33))])] | |
5744 | "TARGET_HARD_FLOAT" | |
5745 | "") | |
5746 | ||
5747 | (define_insn "*negdf2" | |
5748 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5749 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
5750 | (clobber (reg:CC 33))] | |
5751 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 5752 | "lcdbr\t%0,%1" |
077dab3b HP |
5753 | [(set_attr "op_type" "RRE") |
5754 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
5755 | |
5756 | (define_insn "*negdf2_ibm" | |
5757 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5758 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
5759 | (clobber (reg:CC 33))] | |
5760 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 5761 | "lcdr\t%0,%1" |
077dab3b HP |
5762 | [(set_attr "op_type" "RR") |
5763 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
5764 | |
5765 | ; | |
5766 | ; negsf2 instruction pattern(s). | |
5767 | ; | |
5768 | ||
5769 | (define_expand "negsf2" | |
5770 | [(parallel | |
5771 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5772 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
5773 | (clobber (reg:CC 33))])] | |
5774 | "TARGET_HARD_FLOAT" | |
5775 | "") | |
5776 | ||
5777 | (define_insn "*negsf2" | |
5778 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5779 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
5780 | (clobber (reg:CC 33))] | |
5781 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 5782 | "lcebr\t%0,%1" |
077dab3b HP |
5783 | [(set_attr "op_type" "RRE") |
5784 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
5785 | |
5786 | (define_insn "*negsf2" | |
5787 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5788 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
5789 | (clobber (reg:CC 33))] | |
5790 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 5791 | "lcer\t%0,%1" |
077dab3b HP |
5792 | [(set_attr "op_type" "RR") |
5793 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
5794 | |
5795 | ||
5796 | ;; | |
5797 | ;;- Absolute value instructions. | |
5798 | ;; | |
5799 | ||
5800 | ; | |
5801 | ; absdi2 instruction pattern(s). | |
5802 | ; | |
5803 | ||
5804 | (define_insn "absdi2" | |
5805 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5806 | (abs:DI (match_operand:DI 1 "register_operand" "d"))) | |
5807 | (clobber (reg:CC 33))] | |
5808 | "TARGET_64BIT" | |
d40c829f | 5809 | "lpgr\t%0,%1" |
f2d3c02a | 5810 | [(set_attr "op_type" "RRE")]) |
9db1d521 HP |
5811 | |
5812 | ; | |
5813 | ; abssi2 instruction pattern(s). | |
5814 | ; | |
5815 | ||
5816 | (define_insn "abssi2" | |
5817 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5818 | (abs:SI (match_operand:SI 1 "register_operand" "d"))) | |
5819 | (clobber (reg:CC 33))] | |
5820 | "" | |
d40c829f | 5821 | "lpr\t%0,%1" |
f2d3c02a | 5822 | [(set_attr "op_type" "RR")]) |
9db1d521 | 5823 | |
9db1d521 HP |
5824 | ; |
5825 | ; absdf2 instruction pattern(s). | |
5826 | ; | |
5827 | ||
5828 | (define_expand "absdf2" | |
5829 | [(parallel | |
5830 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5831 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
5832 | (clobber (reg:CC 33))])] | |
5833 | "TARGET_HARD_FLOAT" | |
5834 | "") | |
5835 | ||
5836 | (define_insn "*absdf2" | |
5837 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5838 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
5839 | (clobber (reg:CC 33))] | |
5840 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 5841 | "lpdbr\t%0,%1" |
077dab3b HP |
5842 | [(set_attr "op_type" "RRE") |
5843 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
5844 | |
5845 | (define_insn "*absdf2_ibm" | |
5846 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5847 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
5848 | (clobber (reg:CC 33))] | |
5849 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 5850 | "lpdr\t%0,%1" |
077dab3b HP |
5851 | [(set_attr "op_type" "RR") |
5852 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
5853 | |
5854 | ; | |
5855 | ; abssf2 instruction pattern(s). | |
5856 | ; | |
5857 | ||
5858 | (define_expand "abssf2" | |
5859 | [(parallel | |
5860 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5861 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
5862 | (clobber (reg:CC 33))])] | |
5863 | "TARGET_HARD_FLOAT" | |
5864 | "") | |
5865 | ||
5866 | (define_insn "*abssf2" | |
5867 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5868 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
5869 | (clobber (reg:CC 33))] | |
5870 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 5871 | "lpebr\t%0,%1" |
077dab3b HP |
5872 | [(set_attr "op_type" "RRE") |
5873 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
5874 | |
5875 | (define_insn "*abssf2_ibm" | |
5876 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5877 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
5878 | (clobber (reg:CC 33))] | |
5879 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 5880 | "lper\t%0,%1" |
077dab3b HP |
5881 | [(set_attr "op_type" "RR") |
5882 | (set_attr "type" "fsimps")]) | |
9db1d521 | 5883 | |
3ef093a8 AK |
5884 | ;; |
5885 | ;;- Negated absolute value instructions | |
5886 | ;; | |
5887 | ||
5888 | ; | |
5889 | ; Integer | |
5890 | ; | |
5891 | ||
5892 | (define_insn "*negabssi2" | |
5893 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5894 | (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))) | |
5895 | (clobber (reg:CC 33))] | |
5896 | "" | |
d40c829f | 5897 | "lnr\t%0,%1" |
3ef093a8 AK |
5898 | [(set_attr "op_type" "RR")]) |
5899 | ||
5900 | (define_insn "*negabsdi2" | |
5901 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5902 | (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))) | |
5903 | (clobber (reg:CC 33))] | |
5904 | "TARGET_64BIT" | |
d40c829f | 5905 | "lngr\t%0,%1" |
3ef093a8 AK |
5906 | [(set_attr "op_type" "RRE")]) |
5907 | ||
5908 | ; | |
5909 | ; Floating point | |
5910 | ; | |
5911 | ||
5912 | (define_insn "*negabssf2" | |
5913 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5914 | (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))) | |
5915 | (clobber (reg:CC 33))] | |
5916 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 5917 | "lnebr\t%0,%1" |
3ef093a8 AK |
5918 | [(set_attr "op_type" "RRE") |
5919 | (set_attr "type" "fsimps")]) | |
5920 | ||
5921 | (define_insn "*negabsdf2" | |
5922 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5923 | (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))) | |
5924 | (clobber (reg:CC 33))] | |
5925 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 5926 | "lndbr\t%0,%1" |
3ef093a8 AK |
5927 | [(set_attr "op_type" "RRE") |
5928 | (set_attr "type" "fsimpd")]) | |
5929 | ||
4023fb28 UW |
5930 | ;; |
5931 | ;;- Square root instructions. | |
5932 | ;; | |
5933 | ||
5934 | ; | |
5935 | ; sqrtdf2 instruction pattern(s). | |
5936 | ; | |
5937 | ||
5938 | (define_insn "sqrtdf2" | |
5939 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 5940 | (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))] |
4023fb28 UW |
5941 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
5942 | "@ | |
d40c829f UW |
5943 | sqdbr\t%0,%1 |
5944 | sqdb\t%0,%1" | |
d3632d41 | 5945 | [(set_attr "op_type" "RRE,RXE")]) |
4023fb28 UW |
5946 | |
5947 | ; | |
5948 | ; sqrtsf2 instruction pattern(s). | |
5949 | ; | |
5950 | ||
5951 | (define_insn "sqrtsf2" | |
5952 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
d3632d41 | 5953 | (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))] |
4023fb28 UW |
5954 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
5955 | "@ | |
d40c829f UW |
5956 | sqebr\t%0,%1 |
5957 | sqeb\t%0,%1" | |
d3632d41 | 5958 | [(set_attr "op_type" "RRE,RXE")]) |
9db1d521 HP |
5959 | |
5960 | ;; | |
5961 | ;;- One complement instructions. | |
5962 | ;; | |
5963 | ||
5964 | ; | |
5965 | ; one_cmpldi2 instruction pattern(s). | |
5966 | ; | |
c7453384 | 5967 | |
9db1d521 HP |
5968 | (define_expand "one_cmpldi2" |
5969 | [(parallel | |
4023fb28 UW |
5970 | [(set (match_operand:DI 0 "register_operand" "") |
5971 | (xor:DI (match_operand:DI 1 "register_operand" "") | |
5972 | (const_int -1))) | |
9db1d521 HP |
5973 | (clobber (reg:CC 33))])] |
5974 | "TARGET_64BIT" | |
4023fb28 | 5975 | "") |
c7453384 | 5976 | |
9db1d521 HP |
5977 | ; |
5978 | ; one_cmplsi2 instruction pattern(s). | |
5979 | ; | |
c7453384 | 5980 | |
9db1d521 HP |
5981 | (define_expand "one_cmplsi2" |
5982 | [(parallel | |
4023fb28 UW |
5983 | [(set (match_operand:SI 0 "register_operand" "") |
5984 | (xor:SI (match_operand:SI 1 "register_operand" "") | |
5985 | (const_int -1))) | |
9db1d521 HP |
5986 | (clobber (reg:CC 33))])] |
5987 | "" | |
4023fb28 | 5988 | "") |
c7453384 | 5989 | |
9db1d521 HP |
5990 | ; |
5991 | ; one_cmplhi2 instruction pattern(s). | |
5992 | ; | |
c7453384 | 5993 | |
9db1d521 HP |
5994 | (define_expand "one_cmplhi2" |
5995 | [(parallel | |
4023fb28 UW |
5996 | [(set (match_operand:HI 0 "register_operand" "") |
5997 | (xor:HI (match_operand:HI 1 "register_operand" "") | |
5998 | (const_int -1))) | |
9db1d521 HP |
5999 | (clobber (reg:CC 33))])] |
6000 | "" | |
4023fb28 | 6001 | "") |
c7453384 | 6002 | |
9db1d521 HP |
6003 | ; |
6004 | ; one_cmplqi2 instruction pattern(s). | |
6005 | ; | |
c7453384 | 6006 | |
4023fb28 UW |
6007 | (define_expand "one_cmplqi2" |
6008 | [(parallel | |
6009 | [(set (match_operand:QI 0 "register_operand" "") | |
6010 | (xor:QI (match_operand:QI 1 "register_operand" "") | |
6011 | (const_int -1))) | |
6012 | (clobber (reg:CC 33))])] | |
9db1d521 | 6013 | "" |
4023fb28 | 6014 | "") |
9db1d521 HP |
6015 | |
6016 | ||
6017 | ;; | |
6018 | ;;- Rotate instructions. | |
6019 | ;; | |
6020 | ||
6021 | ; | |
6022 | ; rotldi3 instruction pattern(s). | |
6023 | ; | |
6024 | ||
6025 | (define_insn "rotldi3" | |
ac32b25e UW |
6026 | [(set (match_operand:DI 0 "register_operand" "=d") |
6027 | (rotate:DI (match_operand:DI 1 "register_operand" "d") | |
6028 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6029 | "TARGET_64BIT" |
ac32b25e | 6030 | "rllg\t%0,%1,%Y2" |
077dab3b HP |
6031 | [(set_attr "op_type" "RSE") |
6032 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6033 | |
6034 | ; | |
6035 | ; rotlsi3 instruction pattern(s). | |
6036 | ; | |
6037 | ||
6038 | (define_insn "rotlsi3" | |
ac32b25e UW |
6039 | [(set (match_operand:SI 0 "register_operand" "=d") |
6040 | (rotate:SI (match_operand:SI 1 "register_operand" "d") | |
6041 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9e8327e3 | 6042 | "TARGET_CPU_ZARCH" |
ac32b25e | 6043 | "rll\t%0,%1,%Y2" |
077dab3b HP |
6044 | [(set_attr "op_type" "RSE") |
6045 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6046 | |
6047 | ||
6048 | ;; | |
6049 | ;;- Arithmetic shift instructions. | |
6050 | ;; | |
9db1d521 HP |
6051 | |
6052 | ; | |
6053 | ; ashldi3 instruction pattern(s). | |
6054 | ; | |
6055 | ||
6056 | (define_expand "ashldi3" | |
ecbe845e UW |
6057 | [(set (match_operand:DI 0 "register_operand" "") |
6058 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
ac32b25e | 6059 | (match_operand:SI 2 "shift_count_operand" "")))] |
9db1d521 HP |
6060 | "" |
6061 | "") | |
6062 | ||
6063 | (define_insn "*ashldi3_31" | |
ac32b25e UW |
6064 | [(set (match_operand:DI 0 "register_operand" "=d") |
6065 | (ashift:DI (match_operand:DI 1 "register_operand" "0") | |
6066 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6067 | "!TARGET_64BIT" |
ac32b25e | 6068 | "sldl\t%0,%Y2" |
077dab3b HP |
6069 | [(set_attr "op_type" "RS") |
6070 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6071 | |
6072 | (define_insn "*ashldi3_64" | |
ac32b25e UW |
6073 | [(set (match_operand:DI 0 "register_operand" "=d") |
6074 | (ashift:DI (match_operand:DI 1 "register_operand" "d") | |
6075 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6076 | "TARGET_64BIT" |
ac32b25e | 6077 | "sllg\t%0,%1,%Y2" |
077dab3b HP |
6078 | [(set_attr "op_type" "RSE") |
6079 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6080 | |
6081 | ; | |
6082 | ; ashrdi3 instruction pattern(s). | |
6083 | ; | |
6084 | ||
6085 | (define_expand "ashrdi3" | |
6086 | [(parallel | |
6087 | [(set (match_operand:DI 0 "register_operand" "") | |
6088 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
ac32b25e | 6089 | (match_operand:SI 2 "shift_count_operand" ""))) |
9db1d521 HP |
6090 | (clobber (reg:CC 33))])] |
6091 | "" | |
6092 | "") | |
6093 | ||
ecbe845e UW |
6094 | (define_insn "*ashrdi3_cc_31" |
6095 | [(set (reg 33) | |
ac32b25e UW |
6096 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
6097 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6098 | (const_int 0))) |
ac32b25e | 6099 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e UW |
6100 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6101 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" | |
ac32b25e | 6102 | "srda\t%0,%Y2" |
077dab3b HP |
6103 | [(set_attr "op_type" "RS") |
6104 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
6105 | |
6106 | (define_insn "*ashrdi3_cconly_31" | |
6107 | [(set (reg 33) | |
ac32b25e UW |
6108 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
6109 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6110 | (const_int 0))) |
ac32b25e | 6111 | (clobber (match_scratch:DI 0 "=d"))] |
ecbe845e | 6112 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 6113 | "srda\t%0,%Y2" |
077dab3b HP |
6114 | [(set_attr "op_type" "RS") |
6115 | (set_attr "atype" "reg")]) | |
ecbe845e | 6116 | |
9db1d521 | 6117 | (define_insn "*ashrdi3_31" |
ac32b25e UW |
6118 | [(set (match_operand:DI 0 "register_operand" "=d") |
6119 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
6120 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
9db1d521 HP |
6121 | (clobber (reg:CC 33))] |
6122 | "!TARGET_64BIT" | |
ac32b25e | 6123 | "srda\t%0,%Y2" |
077dab3b HP |
6124 | [(set_attr "op_type" "RS") |
6125 | (set_attr "atype" "reg")]) | |
c7453384 | 6126 | |
ecbe845e UW |
6127 | (define_insn "*ashrdi3_cc_64" |
6128 | [(set (reg 33) | |
ac32b25e UW |
6129 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") |
6130 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6131 | (const_int 0))) |
ac32b25e | 6132 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e UW |
6133 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6134 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
ac32b25e | 6135 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6136 | [(set_attr "op_type" "RSE") |
6137 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
6138 | |
6139 | (define_insn "*ashrdi3_cconly_64" | |
6140 | [(set (reg 33) | |
ac32b25e UW |
6141 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") |
6142 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6143 | (const_int 0))) |
ac32b25e | 6144 | (clobber (match_scratch:DI 0 "=d"))] |
ecbe845e | 6145 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" |
ac32b25e | 6146 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6147 | [(set_attr "op_type" "RSE") |
6148 | (set_attr "atype" "reg")]) | |
ecbe845e | 6149 | |
9db1d521 | 6150 | (define_insn "*ashrdi3_64" |
ac32b25e UW |
6151 | [(set (match_operand:DI 0 "register_operand" "=d") |
6152 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
6153 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
9db1d521 HP |
6154 | (clobber (reg:CC 33))] |
6155 | "TARGET_64BIT" | |
ac32b25e | 6156 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6157 | [(set_attr "op_type" "RSE") |
6158 | (set_attr "atype" "reg")]) | |
6159 | ||
9db1d521 HP |
6160 | |
6161 | ; | |
6162 | ; ashlsi3 instruction pattern(s). | |
6163 | ; | |
9db1d521 HP |
6164 | |
6165 | (define_insn "ashlsi3" | |
ac32b25e UW |
6166 | [(set (match_operand:SI 0 "register_operand" "=d") |
6167 | (ashift:SI (match_operand:SI 1 "register_operand" "0") | |
6168 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6169 | "" |
ac32b25e | 6170 | "sll\t%0,%Y2" |
077dab3b HP |
6171 | [(set_attr "op_type" "RS") |
6172 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6173 | |
6174 | ; | |
6175 | ; ashrsi3 instruction pattern(s). | |
6176 | ; | |
6177 | ||
ecbe845e UW |
6178 | (define_insn "*ashrsi3_cc" |
6179 | [(set (reg 33) | |
ac32b25e UW |
6180 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") |
6181 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6182 | (const_int 0))) |
ac32b25e | 6183 | (set (match_operand:SI 0 "register_operand" "=d") |
ecbe845e UW |
6184 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
6185 | "s390_match_ccmode(insn, CCSmode)" | |
ac32b25e | 6186 | "sra\t%0,%Y2" |
077dab3b HP |
6187 | [(set_attr "op_type" "RS") |
6188 | (set_attr "atype" "reg")]) | |
6189 | ||
ecbe845e UW |
6190 | |
6191 | (define_insn "*ashrsi3_cconly" | |
6192 | [(set (reg 33) | |
ac32b25e UW |
6193 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") |
6194 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6195 | (const_int 0))) |
ac32b25e | 6196 | (clobber (match_scratch:SI 0 "=d"))] |
ecbe845e | 6197 | "s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 6198 | "sra\t%0,%Y2" |
077dab3b HP |
6199 | [(set_attr "op_type" "RS") |
6200 | (set_attr "atype" "reg")]) | |
ecbe845e | 6201 | |
9db1d521 | 6202 | (define_insn "ashrsi3" |
ac32b25e UW |
6203 | [(set (match_operand:SI 0 "register_operand" "=d") |
6204 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
6205 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
9db1d521 HP |
6206 | (clobber (reg:CC 33))] |
6207 | "" | |
ac32b25e | 6208 | "sra\t%0,%Y2" |
077dab3b HP |
6209 | [(set_attr "op_type" "RS") |
6210 | (set_attr "atype" "reg")]) | |
9db1d521 | 6211 | |
9db1d521 HP |
6212 | |
6213 | ;; | |
6214 | ;;- logical shift instructions. | |
6215 | ;; | |
6216 | ||
6217 | ; | |
6218 | ; lshrdi3 instruction pattern(s). | |
6219 | ; | |
6220 | ||
6221 | (define_expand "lshrdi3" | |
ecbe845e UW |
6222 | [(set (match_operand:DI 0 "register_operand" "") |
6223 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
ac32b25e | 6224 | (match_operand:SI 2 "shift_count_operand" "")))] |
9db1d521 HP |
6225 | "" |
6226 | "") | |
6227 | ||
6228 | (define_insn "*lshrdi3_31" | |
ac32b25e UW |
6229 | [(set (match_operand:DI 0 "register_operand" "=d") |
6230 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
6231 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6232 | "!TARGET_64BIT" |
ac32b25e UW |
6233 | "srdl\t%0,%Y2" |
6234 | [(set_attr "op_type" "RS") | |
077dab3b | 6235 | (set_attr "atype" "reg")]) |
9db1d521 HP |
6236 | |
6237 | (define_insn "*lshrdi3_64" | |
ac32b25e UW |
6238 | [(set (match_operand:DI 0 "register_operand" "=d") |
6239 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
6240 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6241 | "TARGET_64BIT" |
ac32b25e UW |
6242 | "srlg\t%0,%1,%Y2" |
6243 | [(set_attr "op_type" "RSE") | |
077dab3b | 6244 | (set_attr "atype" "reg")]) |
9db1d521 HP |
6245 | |
6246 | ; | |
6247 | ; lshrsi3 instruction pattern(s). | |
6248 | ; | |
6249 | ||
6250 | (define_insn "lshrsi3" | |
ac32b25e UW |
6251 | [(set (match_operand:SI 0 "register_operand" "=d") |
6252 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
6253 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6254 | "" |
ac32b25e | 6255 | "srl\t%0,%Y2" |
077dab3b HP |
6256 | [(set_attr "op_type" "RS") |
6257 | (set_attr "atype" "reg")]) | |
9db1d521 | 6258 | |
9db1d521 HP |
6259 | |
6260 | ;; | |
6261 | ;; Branch instruction patterns. | |
6262 | ;; | |
6263 | ||
6264 | (define_expand "beq" | |
6265 | [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2))) | |
6266 | (set (pc) | |
6267 | (if_then_else (eq (reg:CCZ 33) (const_int 0)) | |
6268 | (label_ref (match_operand 0 "" "")) | |
6269 | (pc)))] | |
6270 | "" | |
10bbf137 | 6271 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
6272 | |
6273 | (define_expand "bne" | |
6274 | [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2))) | |
6275 | (set (pc) | |
6276 | (if_then_else (ne (reg:CCZ 33) (const_int 0)) | |
6277 | (label_ref (match_operand 0 "" "")) | |
6278 | (pc)))] | |
6279 | "" | |
10bbf137 | 6280 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
6281 | |
6282 | (define_expand "bgt" | |
6283 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6284 | (set (pc) | |
6285 | (if_then_else (gt (reg:CCS 33) (const_int 0)) | |
6286 | (label_ref (match_operand 0 "" "")) | |
6287 | (pc)))] | |
6288 | "" | |
10bbf137 | 6289 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
6290 | |
6291 | (define_expand "bgtu" | |
6292 | [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) | |
6293 | (set (pc) | |
6294 | (if_then_else (gtu (reg:CCU 33) (const_int 0)) | |
6295 | (label_ref (match_operand 0 "" "")) | |
6296 | (pc)))] | |
6297 | "" | |
10bbf137 | 6298 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
6299 | |
6300 | (define_expand "blt" | |
6301 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6302 | (set (pc) | |
6303 | (if_then_else (lt (reg:CCS 33) (const_int 0)) | |
6304 | (label_ref (match_operand 0 "" "")) | |
6305 | (pc)))] | |
6306 | "" | |
10bbf137 | 6307 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
6308 | |
6309 | (define_expand "bltu" | |
6310 | [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) | |
6311 | (set (pc) | |
6312 | (if_then_else (ltu (reg:CCU 33) (const_int 0)) | |
6313 | (label_ref (match_operand 0 "" "")) | |
6314 | (pc)))] | |
6315 | "" | |
10bbf137 | 6316 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
6317 | |
6318 | (define_expand "bge" | |
6319 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6320 | (set (pc) | |
6321 | (if_then_else (ge (reg:CCS 33) (const_int 0)) | |
6322 | (label_ref (match_operand 0 "" "")) | |
6323 | (pc)))] | |
6324 | "" | |
10bbf137 | 6325 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
6326 | |
6327 | (define_expand "bgeu" | |
6328 | [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) | |
6329 | (set (pc) | |
6330 | (if_then_else (geu (reg:CCU 33) (const_int 0)) | |
6331 | (label_ref (match_operand 0 "" "")) | |
6332 | (pc)))] | |
6333 | "" | |
10bbf137 | 6334 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
6335 | |
6336 | (define_expand "ble" | |
6337 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6338 | (set (pc) | |
6339 | (if_then_else (le (reg:CCS 33) (const_int 0)) | |
6340 | (label_ref (match_operand 0 "" "")) | |
6341 | (pc)))] | |
6342 | "" | |
10bbf137 | 6343 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
6344 | |
6345 | (define_expand "bleu" | |
6346 | [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) | |
6347 | (set (pc) | |
6348 | (if_then_else (leu (reg:CCU 33) (const_int 0)) | |
6349 | (label_ref (match_operand 0 "" "")) | |
6350 | (pc)))] | |
6351 | "" | |
10bbf137 | 6352 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 | 6353 | |
ba956982 UW |
6354 | (define_expand "bunordered" |
6355 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6356 | (set (pc) | |
6357 | (if_then_else (unordered (reg:CCS 33) (const_int 0)) | |
6358 | (label_ref (match_operand 0 "" "")) | |
6359 | (pc)))] | |
6360 | "" | |
10bbf137 | 6361 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
6362 | |
6363 | (define_expand "bordered" | |
6364 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6365 | (set (pc) | |
6366 | (if_then_else (ordered (reg:CCS 33) (const_int 0)) | |
6367 | (label_ref (match_operand 0 "" "")) | |
6368 | (pc)))] | |
6369 | "" | |
10bbf137 | 6370 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
6371 | |
6372 | (define_expand "buneq" | |
6373 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6374 | (set (pc) | |
6375 | (if_then_else (uneq (reg:CCS 33) (const_int 0)) | |
6376 | (label_ref (match_operand 0 "" "")) | |
6377 | (pc)))] | |
6378 | "" | |
10bbf137 | 6379 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
6380 | |
6381 | (define_expand "bungt" | |
6382 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6383 | (set (pc) | |
6384 | (if_then_else (ungt (reg:CCS 33) (const_int 0)) | |
6385 | (label_ref (match_operand 0 "" "")) | |
6386 | (pc)))] | |
6387 | "" | |
10bbf137 | 6388 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
6389 | |
6390 | (define_expand "bunlt" | |
6391 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6392 | (set (pc) | |
6393 | (if_then_else (unlt (reg:CCS 33) (const_int 0)) | |
6394 | (label_ref (match_operand 0 "" "")) | |
6395 | (pc)))] | |
6396 | "" | |
10bbf137 | 6397 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
6398 | |
6399 | (define_expand "bunge" | |
6400 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6401 | (set (pc) | |
6402 | (if_then_else (unge (reg:CCS 33) (const_int 0)) | |
6403 | (label_ref (match_operand 0 "" "")) | |
6404 | (pc)))] | |
6405 | "" | |
10bbf137 | 6406 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
6407 | |
6408 | (define_expand "bunle" | |
6409 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6410 | (set (pc) | |
6411 | (if_then_else (unle (reg:CCS 33) (const_int 0)) | |
6412 | (label_ref (match_operand 0 "" "")) | |
6413 | (pc)))] | |
6414 | "" | |
10bbf137 | 6415 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
6416 | |
6417 | (define_expand "bltgt" | |
6418 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6419 | (set (pc) | |
6420 | (if_then_else (ltgt (reg:CCS 33) (const_int 0)) | |
6421 | (label_ref (match_operand 0 "" "")) | |
6422 | (pc)))] | |
6423 | "" | |
10bbf137 | 6424 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 | 6425 | |
9db1d521 HP |
6426 | |
6427 | ;; | |
6428 | ;;- Conditional jump instructions. | |
6429 | ;; | |
6430 | ||
6431 | (define_insn "cjump" | |
6432 | [(set (pc) | |
c7453384 | 6433 | (if_then_else |
9db1d521 HP |
6434 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) |
6435 | (label_ref (match_operand 0 "" "")) | |
6436 | (pc)))] | |
6437 | "" | |
9db1d521 | 6438 | { |
13e58269 | 6439 | if (get_attr_length (insn) == 4) |
d40c829f | 6440 | return "j%C1\t%l0"; |
9e8327e3 | 6441 | else if (TARGET_CPU_ZARCH) |
d40c829f | 6442 | return "jg%C1\t%l0"; |
9db1d521 | 6443 | else |
13e58269 | 6444 | abort (); |
10bbf137 | 6445 | } |
9db1d521 | 6446 | [(set_attr "op_type" "RI") |
077dab3b | 6447 | (set_attr "type" "branch") |
13e58269 UW |
6448 | (set (attr "length") |
6449 | (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6450 | (const_int 4) | |
9e8327e3 | 6451 | (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) |
13e58269 UW |
6452 | (const_int 6) |
6453 | (eq (symbol_ref "flag_pic") (const_int 0)) | |
6454 | (const_int 6)] (const_int 8)))]) | |
9db1d521 | 6455 | |
f314b9b1 | 6456 | (define_insn "*cjump_long" |
9db1d521 HP |
6457 | [(set (pc) |
6458 | (if_then_else | |
6459 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
d3632d41 | 6460 | (match_operand 0 "address_operand" "U") |
9db1d521 HP |
6461 | (pc)))] |
6462 | "" | |
f314b9b1 UW |
6463 | { |
6464 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6465 | return "b%C1r\t%0"; |
f314b9b1 | 6466 | else |
d40c829f | 6467 | return "b%C1\t%a0"; |
10bbf137 | 6468 | } |
c7453384 | 6469 | [(set (attr "op_type") |
f314b9b1 UW |
6470 | (if_then_else (match_operand 0 "register_operand" "") |
6471 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6472 | (set_attr "type" "branch") |
6473 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
6474 | |
6475 | ||
6476 | ;; | |
6477 | ;;- Negated conditional jump instructions. | |
6478 | ;; | |
6479 | ||
6480 | (define_insn "icjump" | |
6481 | [(set (pc) | |
6482 | (if_then_else | |
6483 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
c7453384 | 6484 | (pc) |
9db1d521 HP |
6485 | (label_ref (match_operand 0 "" ""))))] |
6486 | "" | |
c7453384 | 6487 | { |
13e58269 | 6488 | if (get_attr_length (insn) == 4) |
d40c829f | 6489 | return "j%D1\t%l0"; |
9e8327e3 | 6490 | else if (TARGET_CPU_ZARCH) |
d40c829f | 6491 | return "jg%D1\t%l0"; |
9db1d521 | 6492 | else |
13e58269 | 6493 | abort (); |
10bbf137 | 6494 | } |
9db1d521 | 6495 | [(set_attr "op_type" "RI") |
077dab3b | 6496 | (set_attr "type" "branch") |
13e58269 UW |
6497 | (set (attr "length") |
6498 | (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6499 | (const_int 4) | |
9e8327e3 | 6500 | (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) |
13e58269 UW |
6501 | (const_int 6) |
6502 | (eq (symbol_ref "flag_pic") (const_int 0)) | |
6503 | (const_int 6)] (const_int 8)))]) | |
9db1d521 | 6504 | |
f314b9b1 | 6505 | (define_insn "*icjump_long" |
9db1d521 HP |
6506 | [(set (pc) |
6507 | (if_then_else | |
6508 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
f314b9b1 | 6509 | (pc) |
d3632d41 | 6510 | (match_operand 0 "address_operand" "U")))] |
9db1d521 | 6511 | "" |
f314b9b1 UW |
6512 | { |
6513 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6514 | return "b%D1r\t%0"; |
f314b9b1 | 6515 | else |
d40c829f | 6516 | return "b%D1\t%a0"; |
10bbf137 | 6517 | } |
c7453384 | 6518 | [(set (attr "op_type") |
f314b9b1 UW |
6519 | (if_then_else (match_operand 0 "register_operand" "") |
6520 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6521 | (set_attr "type" "branch") |
6522 | (set_attr "atype" "agen")]) | |
9db1d521 | 6523 | |
4456530d HP |
6524 | ;; |
6525 | ;;- Trap instructions. | |
6526 | ;; | |
6527 | ||
6528 | (define_insn "trap" | |
6529 | [(trap_if (const_int 1) (const_int 0))] | |
6530 | "" | |
d40c829f | 6531 | "j\t.+2" |
077dab3b HP |
6532 | [(set_attr "op_type" "RX") |
6533 | (set_attr "type" "branch")]) | |
4456530d HP |
6534 | |
6535 | (define_expand "conditional_trap" | |
6536 | [(set (match_dup 2) (match_dup 3)) | |
6537 | (trap_if (match_operator 0 "comparison_operator" | |
6538 | [(match_dup 2) (const_int 0)]) | |
6539 | (match_operand:SI 1 "general_operand" ""))] | |
6540 | "" | |
4456530d HP |
6541 | { |
6542 | enum machine_mode ccmode; | |
6543 | ||
c7453384 | 6544 | if (operands[1] != const0_rtx) FAIL; |
4456530d | 6545 | |
c7453384 EC |
6546 | ccmode = s390_select_ccmode (GET_CODE (operands[0]), |
6547 | s390_compare_op0, s390_compare_op1); | |
4456530d HP |
6548 | operands[2] = gen_rtx_REG (ccmode, 33); |
6549 | operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1); | |
10bbf137 | 6550 | }) |
4456530d HP |
6551 | |
6552 | (define_insn "*trap" | |
6553 | [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)]) | |
6554 | (const_int 0))] | |
6555 | "" | |
d40c829f | 6556 | "j%C0\t.+2"; |
077dab3b HP |
6557 | [(set_attr "op_type" "RI") |
6558 | (set_attr "type" "branch")]) | |
9db1d521 HP |
6559 | |
6560 | ;; | |
0a3bdf9d | 6561 | ;;- Loop instructions. |
9db1d521 | 6562 | ;; |
0a3bdf9d UW |
6563 | ;; This is all complicated by the fact that since this is a jump insn |
6564 | ;; we must handle our own output reloads. | |
c7453384 | 6565 | |
0a3bdf9d UW |
6566 | (define_expand "doloop_end" |
6567 | [(use (match_operand 0 "" "")) ; loop pseudo | |
6568 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
6569 | (use (match_operand 2 "" "")) ; max iterations | |
6570 | (use (match_operand 3 "" "")) ; loop level | |
6571 | (use (match_operand 4 "" ""))] ; label | |
6572 | "" | |
0a3bdf9d UW |
6573 | { |
6574 | if (GET_MODE (operands[0]) == SImode) | |
6575 | emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0])); | |
6576 | else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) | |
6577 | emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); | |
6578 | else | |
6579 | FAIL; | |
6580 | ||
6581 | DONE; | |
10bbf137 | 6582 | }) |
0a3bdf9d UW |
6583 | |
6584 | (define_insn "doloop_si" | |
6585 | [(set (pc) | |
6586 | (if_then_else | |
6587 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6588 | (const_int 1)) | |
6589 | (label_ref (match_operand 0 "" "")) | |
6590 | (pc))) | |
6591 | (set (match_operand:SI 2 "register_operand" "=1,?*m*d") | |
6592 | (plus:SI (match_dup 1) (const_int -1))) | |
6593 | (clobber (match_scratch:SI 3 "=X,&d")) | |
6594 | (clobber (reg:CC 33))] | |
6595 | "" | |
0a3bdf9d UW |
6596 | { |
6597 | if (which_alternative != 0) | |
10bbf137 | 6598 | return "#"; |
0a3bdf9d | 6599 | else if (get_attr_length (insn) == 4) |
d40c829f | 6600 | return "brct\t%1,%l0"; |
545d16ff UW |
6601 | else if (TARGET_CPU_ZARCH) |
6602 | return "ahi\t%1,-1\;jgne\t%l0"; | |
0a3bdf9d UW |
6603 | else |
6604 | abort (); | |
10bbf137 | 6605 | } |
0a3bdf9d | 6606 | [(set_attr "op_type" "RI") |
077dab3b | 6607 | (set_attr "type" "branch") |
0a3bdf9d UW |
6608 | (set (attr "length") |
6609 | (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6610 | (const_int 4) | |
9e8327e3 | 6611 | (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) |
0a3bdf9d | 6612 | (const_int 10) |
0a3bdf9d UW |
6613 | (eq (symbol_ref "flag_pic") (const_int 0)) |
6614 | (const_int 6)] (const_int 8)))]) | |
9db1d521 | 6615 | |
0a3bdf9d UW |
6616 | (define_insn "*doloop_si_long" |
6617 | [(set (pc) | |
6618 | (if_then_else | |
6619 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6620 | (const_int 1)) | |
d3632d41 | 6621 | (match_operand 0 "address_operand" "U,U") |
0a3bdf9d UW |
6622 | (pc))) |
6623 | (set (match_operand:SI 2 "register_operand" "=1,?*m*d") | |
6624 | (plus:SI (match_dup 1) (const_int -1))) | |
6625 | (clobber (match_scratch:SI 3 "=X,&d")) | |
6626 | (clobber (reg:CC 33))] | |
6627 | "" | |
0a3bdf9d UW |
6628 | { |
6629 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6630 | return "bctr\t%1,%0"; |
0a3bdf9d | 6631 | else |
d40c829f | 6632 | return "bct\t%1,%a0"; |
10bbf137 | 6633 | } |
c7453384 | 6634 | [(set (attr "op_type") |
0a3bdf9d UW |
6635 | (if_then_else (match_operand 0 "register_operand" "") |
6636 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6637 | (set_attr "type" "branch") |
6638 | (set_attr "atype" "agen")]) | |
0a3bdf9d UW |
6639 | |
6640 | (define_split | |
6641 | [(set (pc) | |
6642 | (if_then_else (ne (match_operand:SI 1 "register_operand" "") | |
6643 | (const_int 1)) | |
6644 | (match_operand 0 "" "") | |
6645 | (pc))) | |
6646 | (set (match_operand:SI 2 "nonimmediate_operand" "") | |
6647 | (plus:SI (match_dup 1) (const_int -1))) | |
6648 | (clobber (match_scratch:SI 3 "")) | |
6649 | (clobber (reg:CC 33))] | |
6650 | "reload_completed | |
6651 | && (! REG_P (operands[2]) | |
6652 | || ! rtx_equal_p (operands[1], operands[2]))" | |
6653 | [(set (match_dup 3) (match_dup 1)) | |
6654 | (parallel [(set (reg:CCAN 33) | |
6655 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) | |
6656 | (const_int 0))) | |
6657 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
6658 | (set (match_dup 2) (match_dup 3)) | |
6659 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
6660 | (match_dup 0) | |
6661 | (pc)))] | |
6662 | "") | |
9db1d521 | 6663 | |
0a3bdf9d UW |
6664 | (define_insn "doloop_di" |
6665 | [(set (pc) | |
6666 | (if_then_else | |
6667 | (ne (match_operand:DI 1 "register_operand" "d,d") | |
6668 | (const_int 1)) | |
6669 | (label_ref (match_operand 0 "" "")) | |
6670 | (pc))) | |
6671 | (set (match_operand:DI 2 "register_operand" "=1,?*m*r") | |
6672 | (plus:DI (match_dup 1) (const_int -1))) | |
6673 | (clobber (match_scratch:DI 3 "=X,&d")) | |
6674 | (clobber (reg:CC 33))] | |
6675 | "TARGET_64BIT" | |
0a3bdf9d UW |
6676 | { |
6677 | if (which_alternative != 0) | |
10bbf137 | 6678 | return "#"; |
0a3bdf9d | 6679 | else if (get_attr_length (insn) == 4) |
d40c829f | 6680 | return "brctg\t%1,%l0"; |
0a3bdf9d | 6681 | else |
545d16ff | 6682 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 6683 | } |
0a3bdf9d | 6684 | [(set_attr "op_type" "RI") |
077dab3b | 6685 | (set_attr "type" "branch") |
0a3bdf9d UW |
6686 | (set (attr "length") |
6687 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
545d16ff | 6688 | (const_int 4) (const_int 10)))]) |
0a3bdf9d UW |
6689 | |
6690 | (define_split | |
6691 | [(set (pc) | |
6692 | (if_then_else (ne (match_operand:DI 1 "register_operand" "") | |
6693 | (const_int 1)) | |
6694 | (match_operand 0 "" "") | |
6695 | (pc))) | |
6696 | (set (match_operand:DI 2 "nonimmediate_operand" "") | |
6697 | (plus:DI (match_dup 1) (const_int -1))) | |
6698 | (clobber (match_scratch:DI 3 "")) | |
6699 | (clobber (reg:CC 33))] | |
6700 | "reload_completed | |
6701 | && (! REG_P (operands[2]) | |
6702 | || ! rtx_equal_p (operands[1], operands[2]))" | |
6703 | [(set (match_dup 3) (match_dup 1)) | |
6704 | (parallel [(set (reg:CCAN 33) | |
6705 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) | |
6706 | (const_int 0))) | |
6707 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
6708 | (set (match_dup 2) (match_dup 3)) | |
6709 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
6710 | (match_dup 0) | |
6711 | (pc)))] | |
6712 | "") | |
9db1d521 HP |
6713 | |
6714 | ;; | |
6715 | ;;- Unconditional jump instructions. | |
6716 | ;; | |
6717 | ||
6718 | ; | |
6719 | ; jump instruction pattern(s). | |
6720 | ; | |
6721 | ||
6722 | (define_insn "jump" | |
6723 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
6724 | "" | |
9db1d521 | 6725 | { |
13e58269 | 6726 | if (get_attr_length (insn) == 4) |
d40c829f | 6727 | return "j\t%l0"; |
9e8327e3 | 6728 | else if (TARGET_CPU_ZARCH) |
d40c829f | 6729 | return "jg\t%l0"; |
9db1d521 | 6730 | else |
13e58269 | 6731 | abort (); |
10bbf137 | 6732 | } |
9db1d521 | 6733 | [(set_attr "op_type" "RI") |
077dab3b | 6734 | (set_attr "type" "branch") |
13e58269 UW |
6735 | (set (attr "length") |
6736 | (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6737 | (const_int 4) | |
9e8327e3 | 6738 | (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) |
13e58269 UW |
6739 | (const_int 6) |
6740 | (eq (symbol_ref "flag_pic") (const_int 0)) | |
6741 | (const_int 6)] (const_int 8)))]) | |
9db1d521 HP |
6742 | |
6743 | ; | |
6744 | ; indirect-jump instruction pattern(s). | |
6745 | ; | |
6746 | ||
6747 | (define_insn "indirect_jump" | |
d3632d41 | 6748 | [(set (pc) (match_operand 0 "address_operand" "U"))] |
9db1d521 | 6749 | "" |
f314b9b1 UW |
6750 | { |
6751 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6752 | return "br\t%0"; |
f314b9b1 | 6753 | else |
d40c829f | 6754 | return "b\t%a0"; |
10bbf137 | 6755 | } |
c7453384 | 6756 | [(set (attr "op_type") |
f314b9b1 UW |
6757 | (if_then_else (match_operand 0 "register_operand" "") |
6758 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6759 | (set_attr "type" "branch") |
6760 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
6761 | |
6762 | ; | |
f314b9b1 | 6763 | ; casesi instruction pattern(s). |
9db1d521 HP |
6764 | ; |
6765 | ||
f314b9b1 | 6766 | (define_insn "casesi_jump" |
d3632d41 | 6767 | [(set (pc) (match_operand 0 "address_operand" "U")) |
f314b9b1 | 6768 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 6769 | "" |
9db1d521 | 6770 | { |
f314b9b1 | 6771 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 6772 | return "br\t%0"; |
f314b9b1 | 6773 | else |
d40c829f | 6774 | return "b\t%a0"; |
10bbf137 | 6775 | } |
c7453384 | 6776 | [(set (attr "op_type") |
f314b9b1 UW |
6777 | (if_then_else (match_operand 0 "register_operand" "") |
6778 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6779 | (set_attr "type" "branch") |
6780 | (set_attr "atype" "agen")]) | |
9db1d521 | 6781 | |
f314b9b1 UW |
6782 | (define_expand "casesi" |
6783 | [(match_operand:SI 0 "general_operand" "") | |
6784 | (match_operand:SI 1 "general_operand" "") | |
6785 | (match_operand:SI 2 "general_operand" "") | |
6786 | (label_ref (match_operand 3 "" "")) | |
6787 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 6788 | "" |
f314b9b1 UW |
6789 | { |
6790 | rtx index = gen_reg_rtx (SImode); | |
6791 | rtx base = gen_reg_rtx (Pmode); | |
6792 | rtx target = gen_reg_rtx (Pmode); | |
6793 | ||
6794 | emit_move_insn (index, operands[0]); | |
6795 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
6796 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 6797 | operands[4]); |
f314b9b1 UW |
6798 | |
6799 | if (Pmode != SImode) | |
6800 | index = convert_to_mode (Pmode, index, 1); | |
6801 | if (GET_CODE (index) != REG) | |
6802 | index = copy_to_mode_reg (Pmode, index); | |
6803 | ||
6804 | if (TARGET_64BIT) | |
6805 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
6806 | else | |
6807 | emit_insn (gen_ashlsi3 (index, index, GEN_INT (2))); | |
9db1d521 | 6808 | |
f314b9b1 UW |
6809 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
6810 | ||
6811 | index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index)); | |
6812 | emit_move_insn (target, index); | |
6813 | ||
6814 | if (flag_pic) | |
6815 | target = gen_rtx_PLUS (Pmode, base, target); | |
6816 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
6817 | ||
6818 | DONE; | |
10bbf137 | 6819 | }) |
9db1d521 HP |
6820 | |
6821 | ||
6822 | ;; | |
6823 | ;;- Jump to subroutine. | |
6824 | ;; | |
6825 | ;; | |
6826 | ||
6827 | ; | |
6828 | ; untyped call instruction pattern(s). | |
6829 | ; | |
6830 | ||
6831 | ;; Call subroutine returning any type. | |
6832 | (define_expand "untyped_call" | |
6833 | [(parallel [(call (match_operand 0 "" "") | |
6834 | (const_int 0)) | |
6835 | (match_operand 1 "" "") | |
6836 | (match_operand 2 "" "")])] | |
6837 | "" | |
9db1d521 HP |
6838 | { |
6839 | int i; | |
6840 | ||
6841 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
6842 | ||
6843 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
6844 | { | |
6845 | rtx set = XVECEXP (operands[2], 0, i); | |
6846 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
6847 | } | |
6848 | ||
6849 | /* The optimizer does not know that the call sets the function value | |
6850 | registers we stored in the result block. We avoid problems by | |
6851 | claiming that all hard registers are used and clobbered at this | |
6852 | point. */ | |
6853 | emit_insn (gen_blockage ()); | |
6854 | ||
6855 | DONE; | |
10bbf137 | 6856 | }) |
9db1d521 HP |
6857 | |
6858 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
6859 | ;; all of memory. This blocks insns from being moved across this point. | |
6860 | ||
6861 | (define_insn "blockage" | |
10bbf137 | 6862 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 6863 | "" |
4023fb28 | 6864 | "" |
d5869ca0 UW |
6865 | [(set_attr "type" "none") |
6866 | (set_attr "length" "0")]) | |
4023fb28 | 6867 | |
9db1d521 HP |
6868 | |
6869 | ||
6870 | ; | |
6871 | ; call instruction pattern(s). | |
6872 | ; | |
6873 | ||
6874 | (define_expand "call" | |
44b8152b UW |
6875 | [(call (match_operand 0 "" "") |
6876 | (match_operand 1 "" "")) | |
6877 | (use (match_operand 2 "" ""))] | |
9db1d521 | 6878 | "" |
9db1d521 | 6879 | { |
9e8327e3 | 6880 | bool plt_call = false; |
44b8152b | 6881 | rtx insn; |
9db1d521 HP |
6882 | |
6883 | /* Direct function calls need special treatment. */ | |
6884 | if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) | |
6885 | { | |
6886 | rtx sym = XEXP (operands[0], 0); | |
6887 | ||
6888 | /* When calling a global routine in PIC mode, we must | |
6889 | replace the symbol itself with the PLT stub. */ | |
114278e7 | 6890 | if (flag_pic && !SYMBOL_REF_LOCAL_P (sym)) |
9db1d521 | 6891 | { |
fd7643fb | 6892 | sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT); |
9db1d521 | 6893 | sym = gen_rtx_CONST (Pmode, sym); |
9e8327e3 | 6894 | plt_call = true; |
9db1d521 HP |
6895 | } |
6896 | ||
c7453384 | 6897 | /* Unless we can use the bras(l) insn, force the |
9db1d521 | 6898 | routine address into a register. */ |
9e8327e3 | 6899 | if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH) |
fd7643fb UW |
6900 | { |
6901 | if (flag_pic) | |
6902 | sym = legitimize_pic_address (sym, 0); | |
6903 | else | |
6904 | sym = force_reg (Pmode, sym); | |
6905 | } | |
9db1d521 HP |
6906 | |
6907 | operands[0] = gen_rtx_MEM (QImode, sym); | |
6908 | } | |
44b8152b UW |
6909 | |
6910 | /* Emit insn. */ | |
6911 | insn = emit_call_insn (gen_call_exp (operands[0], operands[1], | |
6912 | gen_rtx_REG (Pmode, RETURN_REGNUM))); | |
9e8327e3 UW |
6913 | |
6914 | /* 31-bit PLT stubs use the GOT register implicitly. */ | |
6915 | if (!TARGET_64BIT && plt_call) | |
6916 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); | |
6917 | ||
44b8152b | 6918 | DONE; |
10bbf137 | 6919 | }) |
9db1d521 | 6920 | |
44b8152b UW |
6921 | (define_expand "call_exp" |
6922 | [(parallel [(call (match_operand 0 "" "") | |
6923 | (match_operand 1 "" "")) | |
6924 | (clobber (match_operand 2 "" ""))])] | |
6925 | "" | |
6926 | "") | |
6927 | ||
9e8327e3 UW |
6928 | (define_insn "*bras" |
6929 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
6930 | (match_operand 1 "const_int_operand" "n")) | |
6931 | (clobber (match_operand 2 "register_operand" "=r"))] | |
6932 | "TARGET_SMALL_EXEC && GET_MODE (operands[2]) == Pmode" | |
d40c829f | 6933 | "bras\t%2,%0" |
9db1d521 | 6934 | [(set_attr "op_type" "RI") |
4023fb28 | 6935 | (set_attr "type" "jsr")]) |
9db1d521 | 6936 | |
9e8327e3 UW |
6937 | (define_insn "*brasl" |
6938 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
6939 | (match_operand 1 "const_int_operand" "n")) | |
6940 | (clobber (match_operand 2 "register_operand" "=r"))] | |
6941 | "TARGET_CPU_ZARCH && GET_MODE (operands[2]) == Pmode" | |
6942 | "brasl\t%2,%0" | |
6943 | [(set_attr "op_type" "RIL") | |
077dab3b | 6944 | (set_attr "type" "jsr")]) |
9db1d521 | 6945 | |
9e8327e3 UW |
6946 | (define_insn "*basr" |
6947 | [(call (mem:QI (match_operand 0 "address_operand" "U")) | |
6948 | (match_operand 1 "const_int_operand" "n")) | |
6949 | (clobber (match_operand 2 "register_operand" "=r"))] | |
6950 | "GET_MODE (operands[2]) == Pmode" | |
6951 | { | |
6952 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
6953 | return "basr\t%2,%0"; | |
6954 | else | |
6955 | return "bas\t%2,%a0"; | |
6956 | } | |
6957 | [(set (attr "op_type") | |
6958 | (if_then_else (match_operand 0 "register_operand" "") | |
6959 | (const_string "RR") (const_string "RX"))) | |
6960 | (set_attr "type" "jsr") | |
6961 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
6962 | |
6963 | ; | |
6964 | ; call_value instruction pattern(s). | |
6965 | ; | |
6966 | ||
6967 | (define_expand "call_value" | |
44b8152b UW |
6968 | [(set (match_operand 0 "" "") |
6969 | (call (match_operand 1 "" "") | |
6970 | (match_operand 2 "" ""))) | |
6971 | (use (match_operand 3 "" ""))] | |
9db1d521 | 6972 | "" |
9db1d521 | 6973 | { |
9e8327e3 | 6974 | bool plt_call = false; |
44b8152b | 6975 | rtx insn; |
9db1d521 HP |
6976 | |
6977 | /* Direct function calls need special treatment. */ | |
6978 | if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) | |
6979 | { | |
6980 | rtx sym = XEXP (operands[1], 0); | |
6981 | ||
6982 | /* When calling a global routine in PIC mode, we must | |
6983 | replace the symbol itself with the PLT stub. */ | |
114278e7 | 6984 | if (flag_pic && !SYMBOL_REF_LOCAL_P (sym)) |
9db1d521 | 6985 | { |
fd7643fb | 6986 | sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT); |
9db1d521 | 6987 | sym = gen_rtx_CONST (Pmode, sym); |
9e8327e3 | 6988 | plt_call = true; |
9db1d521 HP |
6989 | } |
6990 | ||
c7453384 | 6991 | /* Unless we can use the bras(l) insn, force the |
9db1d521 | 6992 | routine address into a register. */ |
9e8327e3 | 6993 | if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH) |
9db1d521 | 6994 | { |
fd7643fb UW |
6995 | if (flag_pic) |
6996 | sym = legitimize_pic_address (sym, 0); | |
6997 | else | |
6998 | sym = force_reg (Pmode, sym); | |
9db1d521 HP |
6999 | } |
7000 | ||
7001 | operands[1] = gen_rtx_MEM (QImode, sym); | |
7002 | } | |
44b8152b UW |
7003 | |
7004 | /* Emit insn. */ | |
7005 | insn = emit_call_insn ( | |
7006 | gen_call_value_exp (operands[0], operands[1], operands[2], | |
7007 | gen_rtx_REG (Pmode, RETURN_REGNUM))); | |
9e8327e3 UW |
7008 | |
7009 | /* 31-bit PLT stubs use the GOT register implicitly. */ | |
7010 | if (!TARGET_64BIT && plt_call) | |
7011 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); | |
7012 | ||
44b8152b | 7013 | DONE; |
10bbf137 | 7014 | }) |
9db1d521 | 7015 | |
44b8152b UW |
7016 | (define_expand "call_value_exp" |
7017 | [(parallel [(set (match_operand 0 "" "") | |
7018 | (call (match_operand 1 "" "") | |
7019 | (match_operand 2 "" ""))) | |
7020 | (clobber (match_operand 3 "" ""))])] | |
7021 | "" | |
7022 | "") | |
7023 | ||
9e8327e3 | 7024 | (define_insn "*bras_r" |
c19ec8f9 | 7025 | [(set (match_operand 0 "" "") |
9e8327e3 | 7026 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 7027 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 UW |
7028 | (clobber (match_operand 3 "register_operand" "=r"))] |
7029 | "TARGET_SMALL_EXEC && GET_MODE (operands[3]) == Pmode" | |
d40c829f | 7030 | "bras\t%3,%1" |
9db1d521 | 7031 | [(set_attr "op_type" "RI") |
f2d3c02a | 7032 | (set_attr "type" "jsr")]) |
9db1d521 | 7033 | |
9e8327e3 | 7034 | (define_insn "*brasl_r" |
c19ec8f9 | 7035 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7036 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7037 | (match_operand 2 "const_int_operand" "n"))) | |
7038 | (clobber (match_operand 3 "register_operand" "=r"))] | |
7039 | "TARGET_CPU_ZARCH && GET_MODE (operands[3]) == Pmode" | |
7040 | "brasl\t%3,%1" | |
7041 | [(set_attr "op_type" "RIL") | |
077dab3b | 7042 | (set_attr "type" "jsr")]) |
9db1d521 | 7043 | |
9e8327e3 | 7044 | (define_insn "*basr_r" |
c19ec8f9 | 7045 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7046 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
7047 | (match_operand 2 "const_int_operand" "n"))) | |
7048 | (clobber (match_operand 3 "register_operand" "=r"))] | |
7049 | "GET_MODE (operands[3]) == Pmode" | |
7050 | { | |
7051 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7052 | return "basr\t%3,%1"; | |
7053 | else | |
7054 | return "bas\t%3,%a1"; | |
7055 | } | |
7056 | [(set (attr "op_type") | |
7057 | (if_then_else (match_operand 1 "register_operand" "") | |
7058 | (const_string "RR") (const_string "RX"))) | |
7059 | (set_attr "type" "jsr") | |
7060 | (set_attr "atype" "agen")]) | |
9db1d521 | 7061 | |
fd3cd001 UW |
7062 | ;; |
7063 | ;;- Thread-local storage support. | |
7064 | ;; | |
7065 | ||
7066 | (define_insn "get_tp_64" | |
7067 | [(set (match_operand:DI 0 "nonimmediate_operand" "=??d,Q") | |
7068 | (unspec:DI [(const_int 0)] UNSPEC_TP))] | |
7069 | "TARGET_64BIT" | |
7070 | "@ | |
d40c829f UW |
7071 | ear\t%0,%%a0\;sllg\t%0,%0,32\;ear\t%0,%%a1 |
7072 | stam\t%%a0,%%a1,%0" | |
fd3cd001 UW |
7073 | [(set_attr "op_type" "NN,RS") |
7074 | (set_attr "atype" "reg,*") | |
7075 | (set_attr "type" "o3,*") | |
7076 | (set_attr "length" "14,*")]) | |
7077 | ||
7078 | (define_insn "get_tp_31" | |
7079 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,Q") | |
7080 | (unspec:SI [(const_int 0)] UNSPEC_TP))] | |
7081 | "!TARGET_64BIT" | |
7082 | "@ | |
d40c829f UW |
7083 | ear\t%0,%%a0 |
7084 | stam\t%%a0,%%a0,%0" | |
fd3cd001 UW |
7085 | [(set_attr "op_type" "RRE,RS")]) |
7086 | ||
7087 | (define_insn "set_tp_64" | |
7088 | [(unspec_volatile [(match_operand:DI 0 "general_operand" "??d,Q")] UNSPECV_SET_TP) | |
7089 | (clobber (match_scratch:SI 1 "=d,X"))] | |
7090 | "TARGET_64BIT" | |
7091 | "@ | |
d40c829f UW |
7092 | sar\t%%a1,%0\;srlg\t%1,%0,32\;sar\t%%a0,%1 |
7093 | lam\t%%a0,%%a1,%0" | |
fd3cd001 UW |
7094 | [(set_attr "op_type" "NN,RS") |
7095 | (set_attr "atype" "reg,*") | |
7096 | (set_attr "type" "o3,*") | |
7097 | (set_attr "length" "14,*")]) | |
7098 | ||
7099 | (define_insn "set_tp_31" | |
7100 | [(unspec_volatile [(match_operand:SI 0 "general_operand" "d,Q")] UNSPECV_SET_TP)] | |
7101 | "!TARGET_64BIT" | |
7102 | "@ | |
d40c829f UW |
7103 | sar\t%%a0,%0 |
7104 | lam\t%%a0,%%a0,%0" | |
fd3cd001 | 7105 | [(set_attr "op_type" "RRE,RS")]) |
c7453384 | 7106 | |
fd3cd001 UW |
7107 | (define_insn "*tls_load_64" |
7108 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7109 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
7110 | (match_operand:DI 2 "" "")] | |
7111 | UNSPEC_TLS_LOAD))] | |
7112 | "TARGET_64BIT" | |
d40c829f | 7113 | "lg\t%0,%1%J2" |
fd3cd001 UW |
7114 | [(set_attr "op_type" "RXE")]) |
7115 | ||
7116 | (define_insn "*tls_load_31" | |
d3632d41 UW |
7117 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
7118 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
7119 | (match_operand:SI 2 "" "")] |
7120 | UNSPEC_TLS_LOAD))] | |
7121 | "!TARGET_64BIT" | |
d3632d41 | 7122 | "@ |
d40c829f UW |
7123 | l\t%0,%1%J2 |
7124 | ly\t%0,%1%J2" | |
d3632d41 | 7125 | [(set_attr "op_type" "RX,RXY")]) |
fd3cd001 UW |
7126 | |
7127 | (define_expand "call_value_tls" | |
7128 | [(set (match_operand 0 "" "") | |
7129 | (call (const_int 0) (const_int 0))) | |
7130 | (use (match_operand 1 "" ""))] | |
7131 | "" | |
fd3cd001 UW |
7132 | { |
7133 | rtx insn, sym; | |
7134 | ||
7135 | if (!flag_pic) | |
7136 | abort (); | |
7137 | ||
7138 | sym = s390_tls_get_offset (); | |
fd7643fb | 7139 | sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT); |
fd3cd001 UW |
7140 | sym = gen_rtx_CONST (Pmode, sym); |
7141 | ||
c7453384 | 7142 | /* Unless we can use the bras(l) insn, force the |
fd3cd001 | 7143 | routine address into a register. */ |
9e8327e3 | 7144 | if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH) |
fd3cd001 | 7145 | { |
fd7643fb UW |
7146 | if (flag_pic) |
7147 | sym = legitimize_pic_address (sym, 0); | |
7148 | else | |
7149 | sym = force_reg (Pmode, sym); | |
fd3cd001 UW |
7150 | } |
7151 | ||
7152 | sym = gen_rtx_MEM (QImode, sym); | |
7153 | ||
7154 | /* Emit insn. */ | |
7155 | insn = emit_call_insn ( | |
7156 | gen_call_value_tls_exp (operands[0], sym, const0_rtx, | |
7157 | gen_rtx_REG (Pmode, RETURN_REGNUM), | |
7158 | operands[1])); | |
7159 | ||
7160 | /* The calling convention of __tls_get_offset uses the | |
7161 | GOT register implicitly. */ | |
7162 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); | |
7163 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), operands[0]); | |
7164 | CONST_OR_PURE_CALL_P (insn) = 1; | |
7165 | ||
7166 | DONE; | |
10bbf137 | 7167 | }) |
fd3cd001 UW |
7168 | |
7169 | (define_expand "call_value_tls_exp" | |
7170 | [(parallel [(set (match_operand 0 "" "") | |
7171 | (call (match_operand 1 "" "") | |
7172 | (match_operand 2 "" ""))) | |
7173 | (clobber (match_operand 3 "" "")) | |
7174 | (use (match_operand 4 "" ""))])] | |
7175 | "" | |
7176 | "") | |
7177 | ||
9e8327e3 | 7178 | (define_insn "*bras_tls" |
c19ec8f9 | 7179 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7180 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7181 | (match_operand 2 "const_int_operand" "n"))) | |
7182 | (clobber (match_operand 3 "register_operand" "=r")) | |
7183 | (use (match_operand 4 "" ""))] | |
7184 | "TARGET_SMALL_EXEC && GET_MODE (operands[3]) == Pmode" | |
d40c829f | 7185 | "bras\t%3,%1%J4" |
fd3cd001 UW |
7186 | [(set_attr "op_type" "RI") |
7187 | (set_attr "type" "jsr")]) | |
7188 | ||
9e8327e3 | 7189 | (define_insn "*brasl_tls" |
c19ec8f9 | 7190 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7191 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7192 | (match_operand 2 "const_int_operand" "n"))) | |
7193 | (clobber (match_operand 3 "register_operand" "=r")) | |
7194 | (use (match_operand 4 "" ""))] | |
7195 | "TARGET_CPU_ZARCH && GET_MODE (operands[3]) == Pmode" | |
7196 | "brasl\t%3,%1%J4" | |
7197 | [(set_attr "op_type" "RIL") | |
fd3cd001 UW |
7198 | (set_attr "type" "jsr")]) |
7199 | ||
9e8327e3 | 7200 | (define_insn "*basr_tls" |
c19ec8f9 | 7201 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7202 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
7203 | (match_operand 2 "const_int_operand" "n"))) | |
7204 | (clobber (match_operand 3 "register_operand" "=r")) | |
7205 | (use (match_operand 4 "" ""))] | |
7206 | "GET_MODE (operands[3]) == Pmode" | |
7207 | { | |
7208 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7209 | return "basr\t%3,%1%J4"; | |
7210 | else | |
7211 | return "bas\t%3,%a1%J4"; | |
7212 | } | |
7213 | [(set (attr "op_type") | |
7214 | (if_then_else (match_operand 1 "register_operand" "") | |
7215 | (const_string "RR") (const_string "RX"))) | |
7216 | (set_attr "type" "jsr") | |
7217 | (set_attr "atype" "agen")]) | |
fd3cd001 | 7218 | |
9db1d521 HP |
7219 | ;; |
7220 | ;;- Miscellaneous instructions. | |
7221 | ;; | |
7222 | ||
7223 | ; | |
7224 | ; allocate stack instruction pattern(s). | |
7225 | ; | |
7226 | ||
7227 | (define_expand "allocate_stack" | |
7228 | [(set (reg 15) | |
7229 | (plus (reg 15) (match_operand 1 "general_operand" ""))) | |
7230 | (set (match_operand 0 "general_operand" "") | |
7231 | (reg 15))] | |
7232 | "" | |
9db1d521 HP |
7233 | { |
7234 | rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM); | |
7235 | rtx chain = gen_rtx (MEM, Pmode, stack); | |
7236 | rtx temp = gen_reg_rtx (Pmode); | |
c7453384 | 7237 | |
9db1d521 HP |
7238 | emit_move_insn (temp, chain); |
7239 | ||
7240 | if (TARGET_64BIT) | |
7241 | emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1]))); | |
7242 | else | |
7243 | emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1]))); | |
7244 | ||
7245 | emit_move_insn (chain, temp); | |
7246 | ||
c7453384 | 7247 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
9db1d521 | 7248 | DONE; |
10bbf137 | 7249 | }) |
9db1d521 HP |
7250 | |
7251 | ||
7252 | ; | |
43ab026f | 7253 | ; setjmp instruction pattern. |
9db1d521 HP |
7254 | ; |
7255 | ||
9db1d521 | 7256 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 7257 | [(match_operand 0 "" "")] |
f314b9b1 | 7258 | "flag_pic" |
9db1d521 | 7259 | { |
fd7643fb UW |
7260 | s390_load_got (false); |
7261 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); | |
9db1d521 | 7262 | DONE; |
fd7643fb | 7263 | }) |
9db1d521 | 7264 | |
9db1d521 HP |
7265 | ;; These patterns say how to save and restore the stack pointer. We need not |
7266 | ;; save the stack pointer at function level since we are careful to | |
7267 | ;; preserve the backchain. At block level, we have to restore the backchain | |
7268 | ;; when we restore the stack pointer. | |
7269 | ;; | |
7270 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
7271 | ;; backchain and restore both. Note that in the nonlocal case, the | |
7272 | ;; save area is a memory location. | |
7273 | ||
7274 | (define_expand "save_stack_function" | |
7275 | [(match_operand 0 "general_operand" "") | |
7276 | (match_operand 1 "general_operand" "")] | |
7277 | "" | |
7278 | "DONE;") | |
7279 | ||
7280 | (define_expand "restore_stack_function" | |
7281 | [(match_operand 0 "general_operand" "") | |
7282 | (match_operand 1 "general_operand" "")] | |
7283 | "" | |
7284 | "DONE;") | |
7285 | ||
7286 | (define_expand "restore_stack_block" | |
7287 | [(use (match_operand 0 "register_operand" "")) | |
7288 | (set (match_dup 2) (match_dup 3)) | |
7289 | (set (match_dup 0) (match_operand 1 "register_operand" "")) | |
7290 | (set (match_dup 3) (match_dup 2))] | |
7291 | "" | |
9db1d521 HP |
7292 | { |
7293 | operands[2] = gen_reg_rtx (Pmode); | |
7294 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); | |
10bbf137 | 7295 | }) |
9db1d521 HP |
7296 | |
7297 | (define_expand "save_stack_nonlocal" | |
7298 | [(match_operand 0 "memory_operand" "") | |
7299 | (match_operand 1 "register_operand" "")] | |
7300 | "" | |
9db1d521 HP |
7301 | { |
7302 | rtx temp = gen_reg_rtx (Pmode); | |
7303 | ||
43ab026f AK |
7304 | /* Copy the backchain to the first word, sp to the second and the literal pool |
7305 | base to the third. */ | |
7306 | emit_move_insn (operand_subword (operands[0], 2, 0, | |
7307 | TARGET_64BIT ? OImode : TImode), | |
7308 | gen_rtx_REG (Pmode, BASE_REGISTER)); | |
9db1d521 HP |
7309 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
7310 | emit_move_insn (operand_subword (operands[0], 0, 0, | |
43ab026f | 7311 | TARGET_64BIT ? OImode : TImode), |
9db1d521 HP |
7312 | temp); |
7313 | emit_move_insn (operand_subword (operands[0], 1, 0, | |
43ab026f | 7314 | TARGET_64BIT ? OImode : TImode), |
9db1d521 HP |
7315 | operands[1]); |
7316 | DONE; | |
10bbf137 | 7317 | }) |
9db1d521 HP |
7318 | |
7319 | (define_expand "restore_stack_nonlocal" | |
7320 | [(match_operand 0 "register_operand" "") | |
7321 | (match_operand 1 "memory_operand" "")] | |
7322 | "" | |
9db1d521 HP |
7323 | { |
7324 | rtx temp = gen_reg_rtx (Pmode); | |
43ab026f | 7325 | rtx base = gen_rtx_REG (Pmode, BASE_REGISTER); |
9db1d521 | 7326 | |
43ab026f AK |
7327 | /* Restore the backchain from the first word, sp from the second and the |
7328 | literal pool base from the third. */ | |
9db1d521 HP |
7329 | emit_move_insn (temp, |
7330 | operand_subword (operands[1], 0, 0, | |
43ab026f | 7331 | TARGET_64BIT ? OImode : TImode)); |
9db1d521 HP |
7332 | emit_move_insn (operands[0], |
7333 | operand_subword (operands[1], 1, 0, | |
43ab026f | 7334 | TARGET_64BIT ? OImode : TImode)); |
9db1d521 | 7335 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
43ab026f AK |
7336 | emit_move_insn (base, |
7337 | operand_subword (operands[1], 2, 0, | |
7338 | TARGET_64BIT ? OImode : TImode)); | |
7339 | emit_insn (gen_rtx_USE (VOIDmode, base)); | |
7340 | ||
9db1d521 | 7341 | DONE; |
10bbf137 | 7342 | }) |
9db1d521 HP |
7343 | |
7344 | ||
7345 | ; | |
7346 | ; nop instruction pattern(s). | |
7347 | ; | |
7348 | ||
7349 | (define_insn "nop" | |
7350 | [(const_int 0)] | |
7351 | "" | |
d40c829f | 7352 | "lr\t0,0" |
9db1d521 HP |
7353 | [(set_attr "op_type" "RR")]) |
7354 | ||
7355 | ||
7356 | ; | |
7357 | ; Special literal pool access instruction pattern(s). | |
7358 | ; | |
7359 | ||
416cf582 UW |
7360 | (define_insn "*pool_entry" |
7361 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
7362 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 7363 | "" |
9db1d521 | 7364 | { |
416cf582 UW |
7365 | enum machine_mode mode = GET_MODE (PATTERN (insn)); |
7366 | unsigned int align = GET_MODE_BITSIZE (mode); | |
7367 | s390_output_pool_entry (asm_out_file, operands[0], mode, align); | |
fd7643fb UW |
7368 | return ""; |
7369 | } | |
416cf582 UW |
7370 | [(set_attr "op_type" "NN") |
7371 | (set (attr "length") | |
7372 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) | |
b2ccb744 UW |
7373 | |
7374 | (define_insn "pool_start_31" | |
fd7643fb | 7375 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)] |
9e8327e3 | 7376 | "!TARGET_CPU_ZARCH" |
d40c829f | 7377 | ".align\t4" |
b2ccb744 UW |
7378 | [(set_attr "op_type" "NN") |
7379 | (set_attr "length" "2")]) | |
7380 | ||
7381 | (define_insn "pool_end_31" | |
fd7643fb | 7382 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)] |
9e8327e3 | 7383 | "!TARGET_CPU_ZARCH" |
d40c829f | 7384 | ".align\t2" |
b2ccb744 UW |
7385 | [(set_attr "op_type" "NN") |
7386 | (set_attr "length" "2")]) | |
7387 | ||
7388 | (define_insn "pool_start_64" | |
fd7643fb | 7389 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)] |
9e8327e3 | 7390 | "TARGET_CPU_ZARCH" |
d40c829f | 7391 | ".section\t.rodata\;.align\t8" |
b2ccb744 UW |
7392 | [(set_attr "op_type" "NN") |
7393 | (set_attr "length" "0")]) | |
7394 | ||
7395 | (define_insn "pool_end_64" | |
fd7643fb | 7396 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)] |
9e8327e3 | 7397 | "TARGET_CPU_ZARCH" |
b2ccb744 UW |
7398 | ".previous" |
7399 | [(set_attr "op_type" "NN") | |
7400 | (set_attr "length" "0")]) | |
7401 | ||
5af2f3d3 | 7402 | (define_insn "main_base_31_small" |
9e8327e3 UW |
7403 | [(set (match_operand 0 "register_operand" "=a") |
7404 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
7405 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
7406 | "basr\t%0,0" |
7407 | [(set_attr "op_type" "RR") | |
7408 | (set_attr "type" "la")]) | |
7409 | ||
7410 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
7411 | [(set (match_operand 0 "register_operand" "=a") |
7412 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 7413 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 7414 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 UW |
7415 | "bras\t%0,%2" |
7416 | [(set_attr "op_type" "RI")]) | |
7417 | ||
7418 | (define_insn "main_base_64" | |
9e8327e3 UW |
7419 | [(set (match_operand 0 "register_operand" "=a") |
7420 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
7421 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
7422 | "larl\t%0,%1" |
7423 | [(set_attr "op_type" "RIL") | |
7424 | (set_attr "type" "larl")]) | |
7425 | ||
7426 | (define_insn "main_pool" | |
7427 | [(unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL)] | |
7428 | "" | |
7429 | "* abort ();" | |
7430 | [(set_attr "op_type" "NN")]) | |
7431 | ||
aee4e0db | 7432 | (define_insn "reload_base_31" |
9e8327e3 UW |
7433 | [(set (match_operand 0 "register_operand" "=a") |
7434 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
7435 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7436 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
9db1d521 | 7437 | [(set_attr "op_type" "NN") |
b2ccb744 UW |
7438 | (set_attr "type" "la") |
7439 | (set_attr "length" "6")]) | |
7440 | ||
aee4e0db | 7441 | (define_insn "reload_base_64" |
9e8327e3 UW |
7442 | [(set (match_operand 0 "register_operand" "=a") |
7443 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
7444 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7445 | "larl\t%0,%1" |
aee4e0db | 7446 | [(set_attr "op_type" "RIL") |
077dab3b | 7447 | (set_attr "type" "larl")]) |
aee4e0db | 7448 | |
aee4e0db | 7449 | (define_insn "pool" |
fd7643fb | 7450 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db UW |
7451 | "" |
7452 | "* abort ();" | |
7453 | [(set_attr "op_type" "NN") | |
7454 | (set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) | |
9db1d521 | 7455 | |
4023fb28 UW |
7456 | ;; |
7457 | ;; Insns related to generating the function prologue and epilogue. | |
7458 | ;; | |
7459 | ||
7460 | ||
7461 | (define_expand "prologue" | |
7462 | [(use (const_int 0))] | |
7463 | "" | |
10bbf137 | 7464 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
7465 | |
7466 | (define_expand "epilogue" | |
7467 | [(use (const_int 1))] | |
7468 | "" | |
10bbf137 | 7469 | "s390_emit_epilogue (); DONE;") |
4023fb28 | 7470 | |
9e8327e3 | 7471 | (define_insn "*return" |
4023fb28 | 7472 | [(return) |
9e8327e3 UW |
7473 | (use (match_operand 0 "register_operand" "a"))] |
7474 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7475 | "br\t%0" |
4023fb28 | 7476 | [(set_attr "op_type" "RR") |
c7453384 | 7477 | (set_attr "type" "jsr") |
077dab3b | 7478 | (set_attr "atype" "agen")]) |
4023fb28 | 7479 | |
4023fb28 | 7480 | |
c7453384 EC |
7481 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
7482 | ;; pointer. This is used for compatability. | |
7483 | ||
7484 | (define_expand "ptr_extend" | |
7485 | [(set (match_operand:DI 0 "register_operand" "=r") | |
7486 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 7487 | "TARGET_64BIT" |
c7453384 | 7488 | { |
c7453384 EC |
7489 | emit_insn (gen_anddi3 (operands[0], |
7490 | gen_lowpart (DImode, operands[1]), | |
7491 | GEN_INT (0x7fffffff))); | |
c7453384 | 7492 | DONE; |
10bbf137 | 7493 | }) |