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Commit | Line | Data |
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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
5624e564 | 2 | ;; Copyright (C) 1999-2015 Free Software Foundation, Inc. |
9db1d521 | 3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
4 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
5 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | ;; version. |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
22 | |
23 | ;; | |
cd8dc1f9 | 24 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 25 | ;; |
cd8dc1f9 | 26 | |
9db1d521 HP |
27 | ;; Special formats used for outputting 390 instructions. |
28 | ;; | |
f19a9af7 AK |
29 | ;; %C: print opcode suffix for branch condition. |
30 | ;; %D: print opcode suffix for inverse branch condition. | |
31 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 32 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
33 | ;; %O: print only the displacement of a memory reference. |
34 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 35 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
36 | ;; %N: print the second word of a DImode operand. |
37 | ;; %M: print the second word of a TImode operand. | |
da48f5ec | 38 | ;; %Y: print shift count operand. |
f4aa3848 | 39 | ;; |
f19a9af7 | 40 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 41 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
42 | ;; %x: print integer X as if it's an unsigned halfword. |
43 | ;; %h: print integer X as if it's a signed halfword. | |
44 | ;; %i: print the first nonzero HImode part of X. | |
45 | ;; %j: print the first HImode part unequal to -1 of X. | |
46 | ;; %k: print the first nonzero SImode part of X. | |
47 | ;; %m: print the first SImode part unequal to -1 of X. | |
48 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
49 | ;; |
50 | ;; We have a special constraint for pattern matching. | |
51 | ;; | |
52 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
53 | ;; | |
9db1d521 | 54 | |
fd3cd001 UW |
55 | ;; |
56 | ;; UNSPEC usage | |
57 | ;; | |
58 | ||
30a49b23 AK |
59 | (define_c_enum "unspec" [ |
60 | ; Miscellaneous | |
61 | UNSPEC_ROUND | |
30a49b23 AK |
62 | UNSPEC_ICM |
63 | UNSPEC_TIE | |
10bbf137 | 64 | |
5a3fe9b6 AK |
65 | ; Convert CC into a str comparison result and copy it into an |
66 | ; integer register | |
67 | ; cc0->0, cc1->1, cc2->-1, (cc3->-1) | |
68 | UNSPEC_STRCMPCC_TO_INT | |
69 | ||
70 | ; Copy CC as is into the lower 2 bits of an integer register | |
71 | UNSPEC_CC_TO_INT | |
72 | ||
10bbf137 | 73 | ; GOT/PLT and lt-relative accesses |
30a49b23 AK |
74 | UNSPEC_LTREL_OFFSET |
75 | UNSPEC_LTREL_BASE | |
76 | UNSPEC_POOL_OFFSET | |
77 | UNSPEC_GOTENT | |
78 | UNSPEC_GOT | |
79 | UNSPEC_GOTOFF | |
80 | UNSPEC_PLT | |
81 | UNSPEC_PLTOFF | |
fd7643fb UW |
82 | |
83 | ; Literal pool | |
30a49b23 AK |
84 | UNSPEC_RELOAD_BASE |
85 | UNSPEC_MAIN_BASE | |
86 | UNSPEC_LTREF | |
87 | UNSPEC_INSN | |
88 | UNSPEC_EXECUTE | |
fd7643fb | 89 | |
1a8c13b3 | 90 | ; Atomic Support |
30a49b23 | 91 | UNSPEC_MB |
78ce265b | 92 | UNSPEC_MOVA |
1a8c13b3 | 93 | |
fd7643fb | 94 | ; TLS relocation specifiers |
30a49b23 AK |
95 | UNSPEC_TLSGD |
96 | UNSPEC_TLSLDM | |
97 | UNSPEC_NTPOFF | |
98 | UNSPEC_DTPOFF | |
99 | UNSPEC_GOTNTPOFF | |
100 | UNSPEC_INDNTPOFF | |
fd3cd001 UW |
101 | |
102 | ; TLS support | |
30a49b23 AK |
103 | UNSPEC_TLSLDM_NTPOFF |
104 | UNSPEC_TLS_LOAD | |
91d39d71 UW |
105 | |
106 | ; String Functions | |
30a49b23 AK |
107 | UNSPEC_SRST |
108 | UNSPEC_MVST | |
638e37c2 | 109 | |
7b8acc34 | 110 | ; Stack Smashing Protector |
30a49b23 AK |
111 | UNSPEC_SP_SET |
112 | UNSPEC_SP_TEST | |
85dae55a | 113 | |
638e37c2 | 114 | ; Test Data Class (TDC) |
30a49b23 | 115 | UNSPEC_TDC_INSN |
65b1d8ea AK |
116 | |
117 | ; Population Count | |
30a49b23 AK |
118 | UNSPEC_POPCNT |
119 | UNSPEC_COPYSIGN | |
d12a76f3 AK |
120 | |
121 | ; Load FP Integer | |
122 | UNSPEC_FPINT_FLOOR | |
123 | UNSPEC_FPINT_BTRUNC | |
124 | UNSPEC_FPINT_ROUND | |
125 | UNSPEC_FPINT_CEIL | |
126 | UNSPEC_FPINT_NEARBYINT | |
127 | UNSPEC_FPINT_RINT | |
085261c8 | 128 | |
3af82a61 AK |
129 | UNSPEC_LCBB |
130 | ||
085261c8 | 131 | ; Vector |
3af82a61 AK |
132 | UNSPEC_VEC_SMULT_HI |
133 | UNSPEC_VEC_UMULT_HI | |
134 | UNSPEC_VEC_SMULT_LO | |
085261c8 AK |
135 | UNSPEC_VEC_SMULT_EVEN |
136 | UNSPEC_VEC_UMULT_EVEN | |
137 | UNSPEC_VEC_SMULT_ODD | |
138 | UNSPEC_VEC_UMULT_ODD | |
3af82a61 AK |
139 | |
140 | UNSPEC_VEC_VMAL | |
141 | UNSPEC_VEC_VMAH | |
142 | UNSPEC_VEC_VMALH | |
143 | UNSPEC_VEC_VMAE | |
144 | UNSPEC_VEC_VMALE | |
145 | UNSPEC_VEC_VMAO | |
146 | UNSPEC_VEC_VMALO | |
147 | ||
148 | UNSPEC_VEC_GATHER | |
149 | UNSPEC_VEC_EXTRACT | |
150 | UNSPEC_VEC_INSERT_AND_ZERO | |
151 | UNSPEC_VEC_LOAD_BNDRY | |
085261c8 | 152 | UNSPEC_VEC_LOAD_LEN |
3af82a61 AK |
153 | UNSPEC_VEC_MERGEH |
154 | UNSPEC_VEC_MERGEL | |
155 | UNSPEC_VEC_PACK | |
156 | UNSPEC_VEC_PACK_SATURATE | |
157 | UNSPEC_VEC_PACK_SATURATE_CC | |
158 | UNSPEC_VEC_PACK_SATURATE_GENCC | |
159 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE | |
160 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC | |
161 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC | |
162 | UNSPEC_VEC_PERM | |
163 | UNSPEC_VEC_PERMI | |
164 | UNSPEC_VEC_EXTEND | |
165 | UNSPEC_VEC_STORE_LEN | |
166 | UNSPEC_VEC_UNPACKH | |
167 | UNSPEC_VEC_UNPACKH_L | |
168 | UNSPEC_VEC_UNPACKL | |
169 | UNSPEC_VEC_UNPACKL_L | |
170 | UNSPEC_VEC_ADDC | |
171 | UNSPEC_VEC_ADDC_U128 | |
172 | UNSPEC_VEC_ADDE_U128 | |
173 | UNSPEC_VEC_ADDEC_U128 | |
174 | UNSPEC_VEC_AVG | |
175 | UNSPEC_VEC_AVGU | |
176 | UNSPEC_VEC_CHECKSUM | |
177 | UNSPEC_VEC_GFMSUM | |
178 | UNSPEC_VEC_GFMSUM_128 | |
179 | UNSPEC_VEC_GFMSUM_ACCUM | |
180 | UNSPEC_VEC_GFMSUM_ACCUM_128 | |
181 | UNSPEC_VEC_SET | |
182 | ||
183 | UNSPEC_VEC_VSUMG | |
184 | UNSPEC_VEC_VSUMQ | |
185 | UNSPEC_VEC_VSUM | |
186 | UNSPEC_VEC_RL_MASK | |
187 | UNSPEC_VEC_SLL | |
188 | UNSPEC_VEC_SLB | |
189 | UNSPEC_VEC_SLDB | |
190 | UNSPEC_VEC_SRAL | |
191 | UNSPEC_VEC_SRAB | |
192 | UNSPEC_VEC_SRL | |
193 | UNSPEC_VEC_SRLB | |
194 | ||
195 | UNSPEC_VEC_SUB_U128 | |
196 | UNSPEC_VEC_SUBC | |
197 | UNSPEC_VEC_SUBC_U128 | |
198 | UNSPEC_VEC_SUBE_U128 | |
199 | UNSPEC_VEC_SUBEC_U128 | |
200 | ||
201 | UNSPEC_VEC_TEST_MASK | |
202 | ||
203 | UNSPEC_VEC_VFAE | |
204 | UNSPEC_VEC_VFAECC | |
205 | ||
206 | UNSPEC_VEC_VFEE | |
207 | UNSPEC_VEC_VFEECC | |
085261c8 AK |
208 | UNSPEC_VEC_VFENE |
209 | UNSPEC_VEC_VFENECC | |
3af82a61 AK |
210 | |
211 | UNSPEC_VEC_VISTR | |
212 | UNSPEC_VEC_VISTRCC | |
213 | ||
214 | UNSPEC_VEC_VSTRC | |
215 | UNSPEC_VEC_VSTRCCC | |
216 | ||
217 | UNSPEC_VEC_VCDGB | |
218 | UNSPEC_VEC_VCDLGB | |
219 | ||
220 | UNSPEC_VEC_VCGDB | |
221 | UNSPEC_VEC_VCLGDB | |
222 | ||
223 | UNSPEC_VEC_VFIDB | |
224 | ||
225 | UNSPEC_VEC_VLDEB | |
226 | UNSPEC_VEC_VLEDB | |
227 | ||
228 | UNSPEC_VEC_VFTCIDB | |
229 | UNSPEC_VEC_VFTCIDBCC | |
085261c8 | 230 | ]) |
fd3cd001 UW |
231 | |
232 | ;; | |
233 | ;; UNSPEC_VOLATILE usage | |
234 | ;; | |
235 | ||
30a49b23 AK |
236 | (define_c_enum "unspecv" [ |
237 | ; Blockage | |
238 | UNSPECV_BLOCKAGE | |
10bbf137 | 239 | |
2f7e5a0d | 240 | ; TPF Support |
30a49b23 AK |
241 | UNSPECV_TPF_PROLOGUE |
242 | UNSPECV_TPF_EPILOGUE | |
2f7e5a0d | 243 | |
10bbf137 | 244 | ; Literal pool |
30a49b23 AK |
245 | UNSPECV_POOL |
246 | UNSPECV_POOL_SECTION | |
247 | UNSPECV_POOL_ALIGN | |
248 | UNSPECV_POOL_ENTRY | |
249 | UNSPECV_MAIN_POOL | |
fd7643fb UW |
250 | |
251 | ; TLS support | |
30a49b23 | 252 | UNSPECV_SET_TP |
e0374221 AS |
253 | |
254 | ; Atomic Support | |
30a49b23 AK |
255 | UNSPECV_CAS |
256 | UNSPECV_ATOMIC_OP | |
5a3fe9b6 | 257 | |
f8af0e30 DV |
258 | ; Hotpatching (unremovable NOPs) |
259 | UNSPECV_NOP_2_BYTE | |
260 | UNSPECV_NOP_4_BYTE | |
261 | UNSPECV_NOP_6_BYTE | |
262 | ||
5a3fe9b6 AK |
263 | ; Transactional Execution support |
264 | UNSPECV_TBEGIN | |
2561451d | 265 | UNSPECV_TBEGIN_TDB |
5a3fe9b6 AK |
266 | UNSPECV_TBEGINC |
267 | UNSPECV_TEND | |
268 | UNSPECV_TABORT | |
269 | UNSPECV_ETND | |
270 | UNSPECV_NTSTG | |
271 | UNSPECV_PPA | |
004f64e1 AK |
272 | |
273 | ; Set and get floating point control register | |
274 | UNSPECV_SFPC | |
275 | UNSPECV_EFPC | |
fd3cd001 UW |
276 | ]) |
277 | ||
ae156f85 AS |
278 | ;; |
279 | ;; Registers | |
280 | ;; | |
281 | ||
35dd9a0e AK |
282 | ; Registers with special meaning |
283 | ||
ae156f85 AS |
284 | (define_constants |
285 | [ | |
286 | ; Sibling call register. | |
287 | (SIBCALL_REGNUM 1) | |
288 | ; Literal pool base register. | |
289 | (BASE_REGNUM 13) | |
290 | ; Return address register. | |
291 | (RETURN_REGNUM 14) | |
292 | ; Condition code register. | |
293 | (CC_REGNUM 33) | |
f4aa3848 | 294 | ; Thread local storage pointer register. |
ae156f85 AS |
295 | (TP_REGNUM 36) |
296 | ]) | |
297 | ||
35dd9a0e AK |
298 | ; Hardware register names |
299 | ||
300 | (define_constants | |
301 | [ | |
302 | ; General purpose registers | |
303 | (GPR0_REGNUM 0) | |
af344a30 | 304 | (GPR1_REGNUM 1) |
35dd9a0e AK |
305 | ; Floating point registers. |
306 | (FPR0_REGNUM 16) | |
2cf4c39e AK |
307 | (FPR1_REGNUM 20) |
308 | (FPR2_REGNUM 17) | |
309 | (FPR3_REGNUM 21) | |
310 | (FPR4_REGNUM 18) | |
311 | (FPR5_REGNUM 22) | |
312 | (FPR6_REGNUM 19) | |
313 | (FPR7_REGNUM 23) | |
314 | (FPR8_REGNUM 24) | |
315 | (FPR9_REGNUM 28) | |
316 | (FPR10_REGNUM 25) | |
317 | (FPR11_REGNUM 29) | |
318 | (FPR12_REGNUM 26) | |
319 | (FPR13_REGNUM 30) | |
320 | (FPR14_REGNUM 27) | |
321 | (FPR15_REGNUM 31) | |
085261c8 AK |
322 | (VR0_REGNUM 16) |
323 | (VR16_REGNUM 38) | |
324 | (VR23_REGNUM 45) | |
325 | (VR24_REGNUM 46) | |
326 | (VR31_REGNUM 53) | |
35dd9a0e AK |
327 | ]) |
328 | ||
329 | ;; | |
330 | ;; PFPO GPR0 argument format | |
331 | ;; | |
332 | ||
333 | (define_constants | |
334 | [ | |
335 | ; PFPO operation type | |
336 | (PFPO_CONVERT 0x1000000) | |
337 | ; PFPO operand types | |
338 | (PFPO_OP_TYPE_SF 0x5) | |
339 | (PFPO_OP_TYPE_DF 0x6) | |
340 | (PFPO_OP_TYPE_TF 0x7) | |
341 | (PFPO_OP_TYPE_SD 0x8) | |
342 | (PFPO_OP_TYPE_DD 0x9) | |
343 | (PFPO_OP_TYPE_TD 0xa) | |
344 | ; Bitposition of operand types | |
345 | (PFPO_OP0_TYPE_SHIFT 16) | |
346 | (PFPO_OP1_TYPE_SHIFT 8) | |
347 | ]) | |
348 | ||
5a3fe9b6 AK |
349 | ; Immediate operands for tbegin and tbeginc |
350 | (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c | |
351 | (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08 | |
fd3cd001 | 352 | |
29a74354 UW |
353 | ;; Instruction operand type as used in the Principles of Operation. |
354 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 355 | |
29a74354 | 356 | (define_attr "op_type" |
085261c8 | 357 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX" |
b628bd8e | 358 | (const_string "NN")) |
9db1d521 | 359 | |
29a74354 | 360 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 361 | |
077dab3b | 362 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 363 | cs,vs,store,sem,idiv, |
ed0e512a | 364 | imulhi,imulsi,imuldi, |
2cdece44 | 365 | branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, |
f61a2c7d AK |
366 | floadtf,floaddf,floadsf,fstoredf,fstoresf, |
367 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 | 368 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
65b1d8ea | 369 | fmadddf,fmaddsf, |
9381e3f1 WG |
370 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, |
371 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
372 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
373 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
374 | ftoidfp, other" | |
29a74354 UW |
375 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
376 | (eq_attr "op_type" "SS") (const_string "cs")] | |
377 | (const_string "integer"))) | |
9db1d521 | 378 | |
29a74354 UW |
379 | ;; Another attribute used for scheduling purposes: |
380 | ;; agen: Instruction uses the address generation unit | |
381 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
382 | |
383 | (define_attr "atype" "agen,reg" | |
c68e7b86 | 384 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR") |
0101708c AS |
385 | (const_string "reg") |
386 | (const_string "agen"))) | |
9db1d521 | 387 | |
9381e3f1 WG |
388 | ;; Properties concerning Z10 execution grouping and value forwarding. |
389 | ;; z10_super: instruction is superscalar. | |
390 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
391 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
392 | ;; target register. It can forward this value to a second instruction that reads | |
393 | ;; the same register if that second instruction is issued in the same group. | |
394 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
395 | ;; instruction in the S pipe writes to the register, then the T instruction | |
396 | ;; can immediately read the new value. | |
397 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
398 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
9381e3f1 WG |
399 | ;; |
400 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
401 | ||
402 | ||
403 | (define_attr "z10prop" "none, | |
404 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
405 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
406 | z10_rec, | |
407 | z10_fr, z10_fr_A3, z10_fr_E1, | |
e3cba5e5 | 408 | z10_c" |
9381e3f1 WG |
409 | (const_string "none")) |
410 | ||
65b1d8ea AK |
411 | ;; Properties concerning Z196 decoding |
412 | ;; z196_alone: must group alone | |
413 | ;; z196_end: ends a group | |
414 | ;; z196_cracked: instruction is cracked or expanded | |
415 | (define_attr "z196prop" "none, | |
416 | z196_alone, z196_ends, | |
417 | z196_cracked" | |
418 | (const_string "none")) | |
9381e3f1 | 419 | |
a9cc3f58 | 420 | (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown")) |
22ac2c2f | 421 | |
9db1d521 HP |
422 | ;; Length in bytes. |
423 | ||
424 | (define_attr "length" "" | |
963fc8d0 AK |
425 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
426 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)] | |
b628bd8e | 427 | (const_int 6))) |
9db1d521 | 428 | |
29a74354 UW |
429 | |
430 | ;; Processor type. This attribute must exactly match the processor_type | |
431 | ;; enumeration in s390.h. The current machine description does not | |
432 | ;; distinguish between g5 and g6, but there are differences between the two | |
433 | ;; CPUs could in theory be modeled. | |
434 | ||
55ac540c | 435 | (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13" |
90c6fd8a | 436 | (const (symbol_ref "s390_tune_attr"))) |
29a74354 | 437 | |
b5e0425c | 438 | (define_attr "cpu_facility" |
55ac540c | 439 | "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec" |
3af8e996 AK |
440 | (const_string "standard")) |
441 | ||
442 | (define_attr "enabled" "" | |
443 | (cond [(eq_attr "cpu_facility" "standard") | |
444 | (const_int 1) | |
445 | ||
446 | (and (eq_attr "cpu_facility" "ieee") | |
d7f99b2c | 447 | (match_test "TARGET_CPU_IEEE_FLOAT")) |
3af8e996 AK |
448 | (const_int 1) |
449 | ||
450 | (and (eq_attr "cpu_facility" "zarch") | |
d7f99b2c | 451 | (match_test "TARGET_ZARCH")) |
3af8e996 AK |
452 | (const_int 1) |
453 | ||
454 | (and (eq_attr "cpu_facility" "longdisp") | |
d7f99b2c | 455 | (match_test "TARGET_LONG_DISPLACEMENT")) |
3af8e996 AK |
456 | (const_int 1) |
457 | ||
458 | (and (eq_attr "cpu_facility" "extimm") | |
d7f99b2c | 459 | (match_test "TARGET_EXTIMM")) |
3af8e996 AK |
460 | (const_int 1) |
461 | ||
462 | (and (eq_attr "cpu_facility" "dfp") | |
d7f99b2c | 463 | (match_test "TARGET_DFP")) |
93538e8e AK |
464 | (const_int 1) |
465 | ||
b5e0425c AK |
466 | (and (eq_attr "cpu_facility" "cpu_zarch") |
467 | (match_test "TARGET_CPU_ZARCH")) | |
468 | (const_int 1) | |
469 | ||
93538e8e | 470 | (and (eq_attr "cpu_facility" "z10") |
d7f99b2c | 471 | (match_test "TARGET_Z10")) |
65b1d8ea AK |
472 | (const_int 1) |
473 | ||
474 | (and (eq_attr "cpu_facility" "z196") | |
d7f99b2c | 475 | (match_test "TARGET_Z196")) |
22ac2c2f AK |
476 | (const_int 1) |
477 | ||
478 | (and (eq_attr "cpu_facility" "zEC12") | |
479 | (match_test "TARGET_ZEC12")) | |
55ac540c AK |
480 | (const_int 1) |
481 | ||
482 | (and (eq_attr "cpu_facility" "vec") | |
483 | (match_test "TARGET_VX")) | |
3af8e996 AK |
484 | (const_int 1)] |
485 | (const_int 0))) | |
486 | ||
29a74354 UW |
487 | ;; Pipeline description for z900. For lack of anything better, |
488 | ;; this description is also used for the g5 and g6. | |
489 | (include "2064.md") | |
490 | ||
3443392a | 491 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
492 | (include "2084.md") |
493 | ||
9381e3f1 WG |
494 | ;; Pipeline description for z10 |
495 | (include "2097.md") | |
496 | ||
65b1d8ea AK |
497 | ;; Pipeline description for z196 |
498 | (include "2817.md") | |
499 | ||
22ac2c2f AK |
500 | ;; Pipeline description for zEC12 |
501 | (include "2827.md") | |
502 | ||
0bfc3f69 AS |
503 | ;; Predicates |
504 | (include "predicates.md") | |
505 | ||
cd8dc1f9 WG |
506 | ;; Constraint definitions |
507 | (include "constraints.md") | |
508 | ||
a8ba31f2 EC |
509 | ;; Other includes |
510 | (include "tpf.md") | |
f52c81dd | 511 | |
3abcb3a7 | 512 | ;; Iterators |
f52c81dd | 513 | |
085261c8 AK |
514 | (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF]) |
515 | ||
3abcb3a7 | 516 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 517 | ;; same template. |
f4aa3848 | 518 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
0387c142 | 519 | (SD "TARGET_HARD_DFP")]) |
3abcb3a7 HPN |
520 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
521 | (define_mode_iterator BFP [TF DF SF]) | |
522 | (define_mode_iterator DFP [TD DD]) | |
523 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
524 | (define_mode_iterator DSF [DF SF]) | |
525 | (define_mode_iterator SD_SF [SF SD]) | |
526 | (define_mode_iterator DD_DF [DF DD]) | |
527 | (define_mode_iterator TD_TF [TF TD]) | |
528 | ||
3abcb3a7 | 529 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 530 | ;; from the same template. |
9602b6a1 | 531 | (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) |
78ce265b | 532 | (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) |
3abcb3a7 | 533 | (define_mode_iterator DSI [DI SI]) |
78ce265b | 534 | (define_mode_iterator TDI [TI DI]) |
9db2f16d | 535 | |
3abcb3a7 | 536 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 537 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 | 538 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
9db2f16d | 539 | |
78ce265b RH |
540 | ;; These macros refer to the actual word_mode of the configuration. |
541 | ;; This is equal to Pmode except on 31-bit machines in zarch mode. | |
9602b6a1 AK |
542 | (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) |
543 | (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) | |
544 | ||
6e0d70c9 AK |
545 | ;; Used by the umul pattern to express modes having half the size. |
546 | (define_mode_attr DWH [(TI "DI") (DI "SI")]) | |
547 | (define_mode_attr dwh [(TI "di") (DI "si")]) | |
548 | ||
3abcb3a7 | 549 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 550 | ;; the same template. |
3abcb3a7 | 551 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 552 | |
3abcb3a7 | 553 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 554 | ;; same template. |
9602b6a1 | 555 | (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) |
78ce265b | 556 | (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) |
342cf42b | 557 | |
3abcb3a7 | 558 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 559 | ;; the same template. |
3abcb3a7 | 560 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 561 | |
d12a76f3 | 562 | ;; This iterator allows r[ox]sbg to be defined with the same template |
571e408a RH |
563 | (define_code_iterator IXOR [ior xor]) |
564 | ||
d12a76f3 AK |
565 | ;; This iterator is used to expand the patterns for the nearest |
566 | ;; integer functions. | |
567 | (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC | |
568 | UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL | |
569 | UNSPEC_FPINT_NEARBYINT]) | |
570 | (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor") | |
571 | (UNSPEC_FPINT_BTRUNC "btrunc") | |
572 | (UNSPEC_FPINT_ROUND "round") | |
573 | (UNSPEC_FPINT_CEIL "ceil") | |
574 | (UNSPEC_FPINT_NEARBYINT "nearbyint")]) | |
575 | (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7") | |
576 | (UNSPEC_FPINT_BTRUNC "5") | |
577 | (UNSPEC_FPINT_ROUND "1") | |
578 | (UNSPEC_FPINT_CEIL "6") | |
579 | (UNSPEC_FPINT_NEARBYINT "0")]) | |
580 | ||
3abcb3a7 HPN |
581 | ;; This iterator and attribute allow to combine most atomic operations. |
582 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
65b1d8ea | 583 | (define_code_iterator ATOMIC_Z196 [and ior xor plus]) |
cf5b43b0 | 584 | (define_code_attr atomic [(and "and") (ior "or") (xor "xor") |
45d18331 | 585 | (plus "add") (minus "sub") (mult "nand")]) |
65b1d8ea | 586 | (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) |
45d18331 | 587 | |
f4aa3848 | 588 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
609e7e80 AK |
589 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. |
590 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) | |
f337b930 | 591 | |
f4aa3848 AK |
592 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
593 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
609e7e80 AK |
594 | ;; SDmode. |
595 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 596 | |
609e7e80 | 597 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
598 | ;; Likewise for "<RXe>". |
599 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
600 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
601 | ||
609e7e80 | 602 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 603 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
604 | ;; dfp variants in a single insn definition. |
605 | ||
3abcb3a7 | 606 | ;; This attribute is used to set op_type accordingly. |
f4aa3848 | 607 | (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR") |
609e7e80 AK |
608 | (DD "RRR") (SD "RRR")]) |
609 | ||
f4aa3848 | 610 | ;; This attribute is used in the operand constraint list in order to have the |
609e7e80 AK |
611 | ;; first and the second operand match for bfp modes. |
612 | (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")]) | |
613 | ||
6e5b5de8 AK |
614 | ;; This attribute is used to merge the scalar vector instructions into |
615 | ;; the FP patterns. For non-supported modes (all but DF) it expands | |
616 | ;; to constraints which are supposed to be matched by an earlier | |
617 | ;; variant. | |
618 | (define_mode_attr v0 [(TF "0") (DF "v") (SF "0") (TD "0") (DD "0") (DD "0") (TI "0") (DI "v") (SI "0")]) | |
619 | (define_mode_attr vf [(TF "f") (DF "v") (SF "f") (TD "f") (DD "f") (DD "f") (TI "f") (DI "v") (SI "f")]) | |
620 | (define_mode_attr vd [(TF "d") (DF "v") (SF "d") (TD "d") (DD "d") (DD "d") (TI "d") (DI "v") (SI "d")]) | |
621 | ||
f4aa3848 | 622 | ;; This attribute is used in the operand list of the instruction to have an |
609e7e80 AK |
623 | ;; additional operand for the dfp instructions. |
624 | (define_mode_attr op1 [(TF "") (DF "") (SF "") | |
625 | (TD "%1,") (DD "%1,") (SD "%1,")]) | |
626 | ||
f5905b37 | 627 | |
85dae55a AK |
628 | ;; This attribute is used in the operand constraint list |
629 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
630 | ;; TFmode values are represented by a fp register pair. Since the | |
631 | ;; sign bit instructions only handle single source and target fp registers | |
632 | ;; these instructions can only be used for TFmode values if the source and | |
633 | ;; target operand uses the same fp register. | |
634 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
635 | ||
609e7e80 AK |
636 | ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise. |
637 | ;; This is used to disable the memory alternative in TFmode patterns. | |
638 | (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")]) | |
639 | ||
3abcb3a7 | 640 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
641 | ;; within instruction mnemonics. |
642 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
643 | ||
0387c142 WG |
644 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
645 | ;; modes and to an empty string for bfp modes. | |
646 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
647 | ||
1b48c8cc AS |
648 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
649 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
650 | ;; version only operates on one register. | |
651 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
652 | ||
653 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
654 | ;; version only operates on one register. The DImode version needs an additional | |
655 | ;; register for the assembler output. | |
656 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
657 | |
658 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
659 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
660 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
661 | ||
662 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 663 | ;; pattern itself and the corresponding function calls. |
f337b930 | 664 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
665 | |
666 | ;; This attribute handles differences in the instruction 'type' and will result | |
667 | ;; in "RRE" for DImode and "RR" for SImode. | |
668 | (define_mode_attr E [(DI "E") (SI "")]) | |
669 | ||
3298c037 AK |
670 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
671 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
672 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
673 | ||
8006eaa6 AS |
674 | ;; This attribute handles differences in the instruction 'type' and will result |
675 | ;; in "RSE" for TImode and "RS" for DImode. | |
676 | (define_mode_attr TE [(TI "E") (DI "")]) | |
677 | ||
9a91a21f AS |
678 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
679 | ;; and "lcr" in SImode. | |
680 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 681 | |
3298c037 AK |
682 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
683 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
684 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
685 | ;; variant for long displacements. | |
686 | (define_mode_attr y [(DI "g") (SI "y")]) | |
687 | ||
9602b6a1 | 688 | ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode |
8006eaa6 AS |
689 | ;; and "cds" in DImode. |
690 | (define_mode_attr tg [(TI "g") (DI "")]) | |
691 | ||
78ce265b RH |
692 | ;; In TDI templates, a string like "c<d>sg". |
693 | (define_mode_attr td [(TI "d") (DI "")]) | |
694 | ||
2f8f8434 AS |
695 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
696 | ;; and "cfdbr" in SImode. | |
697 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
698 | ||
65b1d8ea AK |
699 | ;; In GPR templates, a string like sll<gk> will expand to sllg for DI |
700 | ;; and sllk for SI. This way it is possible to merge the new z196 SI | |
701 | ;; 3 operands shift instructions into the existing patterns. | |
702 | (define_mode_attr gk [(DI "g") (SI "k")]) | |
703 | ||
f52c81dd AS |
704 | ;; ICM mask required to load MODE value into the lowest subreg |
705 | ;; of a SImode register. | |
706 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
707 | ||
f6ee577c AS |
708 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
709 | ;; HImode and "llgc" in QImode. | |
710 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
711 | ||
a1aed706 AS |
712 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
713 | ;; in SImode. | |
714 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
715 | ||
609e7e80 AK |
716 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
717 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
718 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
719 | ||
f52c81dd AS |
720 | ;; Maximum unsigned integer that fits in MODE. |
721 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
722 | ||
75ca1b39 RH |
723 | ;; Start and end field computations for RISBG et al. |
724 | (define_mode_attr bfstart [(DI "s") (SI "t")]) | |
725 | (define_mode_attr bfend [(DI "e") (SI "f")]) | |
726 | ||
2542ef05 RH |
727 | ;; In place of GET_MODE_BITSIZE (<MODE>mode) |
728 | (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) | |
729 | ||
177bc204 RS |
730 | ;; Allow return and simple_return to be defined from a single template. |
731 | (define_code_iterator ANY_RETURN [return simple_return]) | |
732 | ||
6e5b5de8 AK |
733 | |
734 | ||
735 | ; Condition code modes generated by vector fp comparisons. These will | |
736 | ; be used also in single element mode. | |
737 | (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE]) | |
738 | ; Used with VFCMP to expand part of the mnemonic | |
739 | ; For fp we have a mismatch: eq in the insn name - e in asm | |
740 | (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) | |
3af82a61 | 741 | (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")]) |
6e5b5de8 AK |
742 | |
743 | ||
085261c8 AK |
744 | (include "vector.md") |
745 | ||
9db1d521 HP |
746 | ;; |
747 | ;;- Compare instructions. | |
748 | ;; | |
749 | ||
07893d4f | 750 | ; Test-under-Mask instructions |
9db1d521 | 751 | |
07893d4f | 752 | (define_insn "*tmqi_mem" |
ae156f85 | 753 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
754 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
755 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
756 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 757 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 758 | "@ |
fc0ea003 UW |
759 | tm\t%S0,%b1 |
760 | tmy\t%S0,%b1" | |
9381e3f1 WG |
761 | [(set_attr "op_type" "SI,SIY") |
762 | (set_attr "z10prop" "z10_super,z10_super")]) | |
9db1d521 | 763 | |
05b9aaaa | 764 | (define_insn "*tmdi_reg" |
ae156f85 | 765 | [(set (reg CC_REGNUM) |
f19a9af7 | 766 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 767 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
768 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
769 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
9602b6a1 | 770 | "TARGET_ZARCH |
3ed99cc9 | 771 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
772 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
773 | "@ | |
774 | tmhh\t%0,%i1 | |
775 | tmhl\t%0,%i1 | |
776 | tmlh\t%0,%i1 | |
777 | tmll\t%0,%i1" | |
9381e3f1 WG |
778 | [(set_attr "op_type" "RI") |
779 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
780 | |
781 | (define_insn "*tmsi_reg" | |
ae156f85 | 782 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
783 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
784 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
785 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 786 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
787 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
788 | "@ | |
789 | tmh\t%0,%i1 | |
790 | tml\t%0,%i1" | |
729e750f WG |
791 | [(set_attr "op_type" "RI") |
792 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 793 | |
f52c81dd | 794 | (define_insn "*tm<mode>_full" |
ae156f85 | 795 | [(set (reg CC_REGNUM) |
f52c81dd AS |
796 | (compare (match_operand:HQI 0 "register_operand" "d") |
797 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 798 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 799 | "tml\t%0,<max_uint>" |
729e750f WG |
800 | [(set_attr "op_type" "RI") |
801 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 802 | |
07893d4f | 803 | |
08a5aaa2 | 804 | ; |
07893d4f | 805 | ; Load-and-Test instructions |
08a5aaa2 AS |
806 | ; |
807 | ||
c0220ea4 | 808 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
809 | |
810 | (define_insn "*tstdi_sign" | |
ae156f85 | 811 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
812 | (compare |
813 | (ashiftrt:DI | |
814 | (ashift:DI | |
815 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0) | |
816 | (const_int 32)) (const_int 32)) | |
817 | (match_operand:DI 1 "const0_operand" ""))) | |
818 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f | 819 | (sign_extend:DI (match_dup 0)))] |
9602b6a1 | 820 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" |
963fc8d0 AK |
821 | "ltgfr\t%2,%0 |
822 | ltgf\t%2,%0" | |
823 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
824 | (set_attr "cpu_facility" "*,z10") |
825 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 826 | |
43a09b63 | 827 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 828 | (define_insn "*tst<mode>_extimm" |
ec24698e | 829 | [(set (reg CC_REGNUM) |
fb492564 | 830 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
831 | (match_operand:GPR 1 "const0_operand" ""))) |
832 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 833 | (match_dup 0))] |
08a5aaa2 | 834 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 835 | "@ |
08a5aaa2 AS |
836 | lt<g>r\t%2,%0 |
837 | lt<g>\t%2,%0" | |
9381e3f1 | 838 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 839 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 840 | |
43a09b63 | 841 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 842 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 843 | [(set (reg CC_REGNUM) |
fb492564 | 844 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
845 | (match_operand:GPR 1 "const0_operand" ""))) |
846 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
847 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 848 | "@ |
08a5aaa2 AS |
849 | lt<g>r\t%0,%0 |
850 | lt<g>\t%2,%0" | |
9381e3f1 | 851 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 852 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 853 | |
07893d4f | 854 | (define_insn "*tstdi" |
ae156f85 | 855 | [(set (reg CC_REGNUM) |
07893d4f UW |
856 | (compare (match_operand:DI 0 "register_operand" "d") |
857 | (match_operand:DI 1 "const0_operand" ""))) | |
858 | (set (match_operand:DI 2 "register_operand" "=d") | |
859 | (match_dup 0))] | |
9602b6a1 | 860 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 861 | "ltgr\t%2,%0" |
9381e3f1 WG |
862 | [(set_attr "op_type" "RRE") |
863 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 864 | |
07893d4f | 865 | (define_insn "*tstsi" |
ae156f85 | 866 | [(set (reg CC_REGNUM) |
d3632d41 | 867 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 868 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 869 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 870 | (match_dup 0))] |
ec24698e | 871 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 872 | "@ |
d40c829f | 873 | ltr\t%2,%0 |
fc0ea003 UW |
874 | icm\t%2,15,%S0 |
875 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
876 | [(set_attr "op_type" "RR,RS,RSY") |
877 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 878 | |
07893d4f | 879 | (define_insn "*tstsi_cconly" |
ae156f85 | 880 | [(set (reg CC_REGNUM) |
d3632d41 | 881 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 882 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 883 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
884 | "s390_match_ccmode(insn, CCSmode)" |
885 | "@ | |
d40c829f | 886 | ltr\t%0,%0 |
fc0ea003 UW |
887 | icm\t%2,15,%S0 |
888 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
889 | [(set_attr "op_type" "RR,RS,RSY") |
890 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 891 | |
08a5aaa2 AS |
892 | (define_insn "*tstdi_cconly_31" |
893 | [(set (reg CC_REGNUM) | |
894 | (compare (match_operand:DI 0 "register_operand" "d") | |
895 | (match_operand:DI 1 "const0_operand" "")))] | |
9602b6a1 | 896 | "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" |
08a5aaa2 AS |
897 | "srda\t%0,0" |
898 | [(set_attr "op_type" "RS") | |
899 | (set_attr "atype" "reg")]) | |
900 | ||
43a09b63 | 901 | ; ltr, ltgr |
08a5aaa2 | 902 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 903 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
904 | (compare (match_operand:GPR 0 "register_operand" "d") |
905 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 906 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 907 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
908 | [(set_attr "op_type" "RR<E>") |
909 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 910 | |
c0220ea4 | 911 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 912 | |
f52c81dd | 913 | (define_insn "*tst<mode>CCT" |
ae156f85 | 914 | [(set (reg CC_REGNUM) |
f52c81dd AS |
915 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
916 | (match_operand:HQI 1 "const0_operand" ""))) | |
917 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
918 | (match_dup 0))] |
919 | "s390_match_ccmode(insn, CCTmode)" | |
920 | "@ | |
f52c81dd AS |
921 | icm\t%2,<icm_lo>,%S0 |
922 | icmy\t%2,<icm_lo>,%S0 | |
923 | tml\t%0,<max_uint>" | |
9381e3f1 WG |
924 | [(set_attr "op_type" "RS,RSY,RI") |
925 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 UW |
926 | |
927 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 928 | [(set (reg CC_REGNUM) |
d3632d41 | 929 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 930 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 931 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
932 | "s390_match_ccmode(insn, CCTmode)" |
933 | "@ | |
fc0ea003 UW |
934 | icm\t%2,3,%S0 |
935 | icmy\t%2,3,%S0 | |
d40c829f | 936 | tml\t%0,65535" |
9381e3f1 WG |
937 | [(set_attr "op_type" "RS,RSY,RI") |
938 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 | 939 | |
3af97654 | 940 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 941 | [(set (reg CC_REGNUM) |
d3632d41 | 942 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
943 | (match_operand:QI 1 "const0_operand" "")))] |
944 | "s390_match_ccmode(insn, CCTmode)" | |
945 | "@ | |
fc0ea003 UW |
946 | cli\t%S0,0 |
947 | cliy\t%S0,0 | |
d40c829f | 948 | tml\t%0,255" |
9381e3f1 | 949 | [(set_attr "op_type" "SI,SIY,RI") |
729e750f | 950 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 951 | |
f52c81dd | 952 | (define_insn "*tst<mode>" |
ae156f85 | 953 | [(set (reg CC_REGNUM) |
f52c81dd AS |
954 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
955 | (match_operand:HQI 1 "const0_operand" ""))) | |
956 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
957 | (match_dup 0))] |
958 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 959 | "@ |
f52c81dd AS |
960 | icm\t%2,<icm_lo>,%S0 |
961 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
962 | [(set_attr "op_type" "RS,RSY") |
963 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 964 | |
f52c81dd | 965 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 966 | [(set (reg CC_REGNUM) |
f52c81dd AS |
967 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
968 | (match_operand:HQI 1 "const0_operand" ""))) | |
969 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 970 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 971 | "@ |
f52c81dd AS |
972 | icm\t%2,<icm_lo>,%S0 |
973 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
974 | [(set_attr "op_type" "RS,RSY") |
975 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
d3632d41 | 976 | |
9db1d521 | 977 | |
575f7c2b UW |
978 | ; Compare (equality) instructions |
979 | ||
980 | (define_insn "*cmpdi_cct" | |
ae156f85 | 981 | [(set (reg CC_REGNUM) |
ec24698e | 982 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
fb492564 | 983 | (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))] |
9602b6a1 | 984 | "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" |
575f7c2b UW |
985 | "@ |
986 | cgr\t%0,%1 | |
f4f41b4e | 987 | cghi\t%0,%h1 |
ec24698e | 988 | cgfi\t%0,%1 |
575f7c2b | 989 | cg\t%0,%1 |
19b63d8e | 990 | #" |
9381e3f1 WG |
991 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
992 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
993 | |
994 | (define_insn "*cmpsi_cct" | |
ae156f85 | 995 | [(set (reg CC_REGNUM) |
ec24698e UW |
996 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
997 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 998 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
999 | "@ |
1000 | cr\t%0,%1 | |
f4f41b4e | 1001 | chi\t%0,%h1 |
ec24698e | 1002 | cfi\t%0,%1 |
575f7c2b UW |
1003 | c\t%0,%1 |
1004 | cy\t%0,%1 | |
19b63d8e | 1005 | #" |
9381e3f1 | 1006 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
e3cba5e5 | 1007 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) |
575f7c2b | 1008 | |
07893d4f | 1009 | ; Compare (signed) instructions |
4023fb28 | 1010 | |
07893d4f | 1011 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 1012 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1013 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
1014 | "d,RT,b")) | |
1015 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
9602b6a1 | 1016 | "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" |
4023fb28 | 1017 | "@ |
d40c829f | 1018 | cgfr\t%0,%1 |
963fc8d0 AK |
1019 | cgf\t%0,%1 |
1020 | cgfrl\t%0,%1" | |
1021 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 1022 | (set_attr "z10prop" "z10_c,*,*") |
963fc8d0 | 1023 | (set_attr "type" "*,*,larl")]) |
4023fb28 | 1024 | |
9381e3f1 WG |
1025 | |
1026 | ||
07893d4f | 1027 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 1028 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1029 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
1030 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 1031 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 1032 | "@ |
d40c829f | 1033 | ch\t%0,%1 |
963fc8d0 AK |
1034 | chy\t%0,%1 |
1035 | chrl\t%0,%1" | |
1036 | [(set_attr "op_type" "RX,RXY,RIL") | |
1037 | (set_attr "cpu_facility" "*,*,z10") | |
65b1d8ea AK |
1038 | (set_attr "type" "*,*,larl") |
1039 | (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")]) | |
963fc8d0 AK |
1040 | |
1041 | (define_insn "*cmphi_ccs_z10" | |
1042 | [(set (reg CC_REGNUM) | |
1043 | (compare (match_operand:HI 0 "s_operand" "Q") | |
1044 | (match_operand:HI 1 "immediate_operand" "K")))] | |
1045 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
1046 | "chhsi\t%0,%1" | |
65b1d8ea AK |
1047 | [(set_attr "op_type" "SIL") |
1048 | (set_attr "z196prop" "z196_cracked")]) | |
963fc8d0 AK |
1049 | |
1050 | (define_insn "*cmpdi_ccs_signhi_rl" | |
1051 | [(set (reg CC_REGNUM) | |
1052 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b")) | |
1053 | (match_operand:GPR 0 "register_operand" "d,d")))] | |
1054 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
1055 | "@ | |
1056 | cgh\t%0,%1 | |
1057 | cghrl\t%0,%1" | |
1058 | [(set_attr "op_type" "RXY,RIL") | |
1059 | (set_attr "type" "*,larl")]) | |
4023fb28 | 1060 | |
963fc8d0 | 1061 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 1062 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1063 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1064 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
1065 | "d,d,Q, d,d,d,d") | |
1066 | (match_operand:GPR 1 "general_operand" | |
1067 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 1068 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 1069 | "@ |
3298c037 AK |
1070 | c<g>r\t%0,%1 |
1071 | c<g>hi\t%0,%h1 | |
963fc8d0 | 1072 | c<g>hsi\t%0,%h1 |
3298c037 AK |
1073 | c<g>fi\t%0,%1 |
1074 | c<g>\t%0,%1 | |
963fc8d0 AK |
1075 | c<y>\t%0,%1 |
1076 | c<g>rl\t%0,%1" | |
1077 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
1078 | (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10") | |
9381e3f1 WG |
1079 | (set_attr "type" "*,*,*,*,*,*,larl") |
1080 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) | |
c7453384 | 1081 | |
07893d4f UW |
1082 | |
1083 | ; Compare (unsigned) instructions | |
9db1d521 | 1084 | |
963fc8d0 AK |
1085 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
1086 | [(set (reg CC_REGNUM) | |
1087 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
1088 | "larl_operand" "X"))) | |
1089 | (match_operand:SI 0 "register_operand" "d")))] | |
1090 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1091 | "clhrl\t%0,%1" | |
1092 | [(set_attr "op_type" "RIL") | |
729e750f WG |
1093 | (set_attr "type" "larl") |
1094 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 AK |
1095 | |
1096 | ; clhrl, clghrl | |
1097 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
1098 | [(set (reg CC_REGNUM) | |
1099 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
1100 | "larl_operand" "X"))) | |
1101 | (match_operand:GPR 0 "register_operand" "d")))] | |
1102 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1103 | "cl<g>hrl\t%0,%1" | |
1104 | [(set_attr "op_type" "RIL") | |
9381e3f1 WG |
1105 | (set_attr "type" "larl") |
1106 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 | 1107 | |
07893d4f | 1108 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 1109 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1110 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
1111 | "d,RT,b")) | |
1112 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
9602b6a1 | 1113 | "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" |
07893d4f | 1114 | "@ |
d40c829f | 1115 | clgfr\t%0,%1 |
963fc8d0 AK |
1116 | clgf\t%0,%1 |
1117 | clgfrl\t%0,%1" | |
1118 | [(set_attr "op_type" "RRE,RXY,RIL") | |
1119 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 WG |
1120 | (set_attr "type" "*,*,larl") |
1121 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) | |
9db1d521 | 1122 | |
07893d4f | 1123 | (define_insn "*cmpdi_ccu" |
ae156f85 | 1124 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1125 | (compare (match_operand:DI 0 "nonimmediate_operand" |
1126 | "d, d,d,Q, d, Q,BQ") | |
1127 | (match_operand:DI 1 "general_operand" | |
1128 | "d,Op,b,D,RT,BQ,Q")))] | |
9602b6a1 | 1129 | "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" |
07893d4f | 1130 | "@ |
d40c829f | 1131 | clgr\t%0,%1 |
ec24698e | 1132 | clgfi\t%0,%1 |
963fc8d0 AK |
1133 | clgrl\t%0,%1 |
1134 | clghsi\t%0,%x1 | |
575f7c2b | 1135 | clg\t%0,%1 |
e221ef54 | 1136 | # |
19b63d8e | 1137 | #" |
963fc8d0 AK |
1138 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
1139 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 WG |
1140 | (set_attr "type" "*,*,larl,*,*,*,*") |
1141 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 1142 | |
07893d4f | 1143 | (define_insn "*cmpsi_ccu" |
ae156f85 | 1144 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1145 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
1146 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 1147 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 1148 | "@ |
d40c829f | 1149 | clr\t%0,%1 |
ec24698e | 1150 | clfi\t%0,%o1 |
963fc8d0 AK |
1151 | clrl\t%0,%1 |
1152 | clfhsi\t%0,%x1 | |
d40c829f | 1153 | cl\t%0,%1 |
575f7c2b | 1154 | cly\t%0,%1 |
e221ef54 | 1155 | # |
19b63d8e | 1156 | #" |
963fc8d0 AK |
1157 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
1158 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*") | |
9381e3f1 WG |
1159 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
1160 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 1161 | |
07893d4f | 1162 | (define_insn "*cmphi_ccu" |
ae156f85 | 1163 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1164 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
1165 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 1166 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1167 | && !register_operand (operands[1], HImode)" |
d3632d41 | 1168 | "@ |
fc0ea003 UW |
1169 | clm\t%0,3,%S1 |
1170 | clmy\t%0,3,%S1 | |
963fc8d0 | 1171 | clhhsi\t%0,%1 |
e221ef54 | 1172 | # |
19b63d8e | 1173 | #" |
963fc8d0 | 1174 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
9381e3f1 WG |
1175 | (set_attr "cpu_facility" "*,*,z10,*,*") |
1176 | (set_attr "z10prop" "*,*,z10_super,*,*")]) | |
9db1d521 HP |
1177 | |
1178 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 1179 | [(set (reg CC_REGNUM) |
e221ef54 UW |
1180 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
1181 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 1182 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1183 | && !register_operand (operands[1], QImode)" |
d3632d41 | 1184 | "@ |
fc0ea003 UW |
1185 | clm\t%0,1,%S1 |
1186 | clmy\t%0,1,%S1 | |
1187 | cli\t%S0,%b1 | |
1188 | cliy\t%S0,%b1 | |
e221ef54 | 1189 | # |
19b63d8e | 1190 | #" |
9381e3f1 WG |
1191 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
1192 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) | |
9db1d521 HP |
1193 | |
1194 | ||
19b63d8e UW |
1195 | ; Block compare (CLC) instruction patterns. |
1196 | ||
1197 | (define_insn "*clc" | |
ae156f85 | 1198 | [(set (reg CC_REGNUM) |
d4f52f0e | 1199 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
1200 | (match_operand:BLK 1 "memory_operand" "Q"))) |
1201 | (use (match_operand 2 "const_int_operand" "n"))] | |
1202 | "s390_match_ccmode (insn, CCUmode) | |
1203 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1204 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 1205 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1206 | |
1207 | (define_split | |
ae156f85 | 1208 | [(set (reg CC_REGNUM) |
19b63d8e UW |
1209 | (compare (match_operand 0 "memory_operand" "") |
1210 | (match_operand 1 "memory_operand" "")))] | |
1211 | "reload_completed | |
1212 | && s390_match_ccmode (insn, CCUmode) | |
1213 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1214 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1215 | [(parallel | |
1216 | [(set (match_dup 0) (match_dup 1)) | |
1217 | (use (match_dup 2))])] | |
1218 | { | |
1219 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1220 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1221 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1222 | ||
1223 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
1224 | operands[0], operands[1]); | |
1225 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
1226 | }) | |
1227 | ||
1228 | ||
609e7e80 | 1229 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 1230 | |
609e7e80 | 1231 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 1232 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 1233 | [(set (reg CC_REGNUM) |
609e7e80 AK |
1234 | (compare (match_operand:FP 0 "register_operand" "f") |
1235 | (match_operand:FP 1 "const0_operand" "")))] | |
142cd70f | 1236 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 1237 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 1238 | [(set_attr "op_type" "RRE") |
9381e3f1 | 1239 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1240 | |
be5de7a1 | 1241 | ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb |
f5905b37 | 1242 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1243 | [(set (reg CC_REGNUM) |
609e7e80 AK |
1244 | (compare (match_operand:FP 0 "register_operand" "f,f") |
1245 | (match_operand:FP 1 "general_operand" "f,<Rf>")))] | |
142cd70f | 1246 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 1247 | "@ |
609e7e80 | 1248 | c<xde><bt>r\t%0,%1 |
f61a2c7d | 1249 | c<xde>b\t%0,%1" |
077dab3b | 1250 | [(set_attr "op_type" "RRE,RXE") |
9381e3f1 | 1251 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1252 | |
6e5b5de8 AK |
1253 | ; wfcedbs, wfchdbs, wfchedbs |
1254 | (define_insn "*vec_cmp<insn_cmp>df_cconly" | |
1255 | [(set (reg:VFCMP CC_REGNUM) | |
1256 | (compare:VFCMP (match_operand:DF 0 "register_operand" "v") | |
1257 | (match_operand:DF 1 "register_operand" "v"))) | |
1258 | (clobber (match_scratch:V2DI 2 "=v"))] | |
1259 | "TARGET_Z13 && TARGET_HARD_FLOAT" | |
1260 | "wfc<asm_fcmp>dbs\t%v2,%v0,%v1" | |
1261 | [(set_attr "op_type" "VRR")]) | |
963fc8d0 AK |
1262 | |
1263 | ; Compare and Branch instructions | |
1264 | ||
1265 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
1266 | ; The following instructions do a complementary access of their second |
1267 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
1268 | (define_insn "*cmp_and_br_signed_<mode>" |
1269 | [(set (pc) | |
1270 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1271 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1272 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1273 | (label_ref (match_operand 3 "" "")) | |
1274 | (pc))) | |
1275 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1276 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1277 | { |
1278 | if (get_attr_length (insn) == 6) | |
1279 | return which_alternative ? | |
1280 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1281 | else | |
1282 | return which_alternative ? | |
1283 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1284 | } | |
1285 | [(set_attr "op_type" "RIE") | |
1286 | (set_attr "type" "branch") | |
e3cba5e5 | 1287 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1288 | (set (attr "length") |
1289 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1290 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1291 | ; 10 byte for cgr/jg | |
1292 | ||
1293 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1294 | ; The following instructions do a complementary access of their second |
1295 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1296 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1297 | [(set (pc) | |
1298 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1299 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1300 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1301 | (label_ref (match_operand 3 "" "")) | |
1302 | (pc))) | |
1303 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1304 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1305 | { |
1306 | if (get_attr_length (insn) == 6) | |
1307 | return which_alternative ? | |
1308 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1309 | else | |
1310 | return which_alternative ? | |
1311 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1312 | } | |
1313 | [(set_attr "op_type" "RIE") | |
1314 | (set_attr "type" "branch") | |
e3cba5e5 | 1315 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1316 | (set (attr "length") |
1317 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1318 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1319 | ; 10 byte for clgr/jg | |
1320 | ||
b0f86a7e AK |
1321 | ; And now the same two patterns as above but with a negated CC mask. |
1322 | ||
1323 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1324 | ; The following instructions do a complementary access of their second | |
1325 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1326 | (define_insn "*icmp_and_br_signed_<mode>" | |
1327 | [(set (pc) | |
1328 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1329 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1330 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1331 | (pc) | |
1332 | (label_ref (match_operand 3 "" "")))) | |
1333 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1334 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1335 | { |
1336 | if (get_attr_length (insn) == 6) | |
1337 | return which_alternative ? | |
1338 | "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; | |
1339 | else | |
1340 | return which_alternative ? | |
1341 | "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; | |
1342 | } | |
1343 | [(set_attr "op_type" "RIE") | |
1344 | (set_attr "type" "branch") | |
1345 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1346 | (set (attr "length") | |
1347 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1348 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1349 | ; 10 byte for cgr/jg | |
1350 | ||
1351 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1352 | ; The following instructions do a complementary access of their second | |
1353 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
1354 | (define_insn "*icmp_and_br_unsigned_<mode>" | |
1355 | [(set (pc) | |
1356 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1357 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1358 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1359 | (pc) | |
1360 | (label_ref (match_operand 3 "" "")))) | |
1361 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1362 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1363 | { |
1364 | if (get_attr_length (insn) == 6) | |
1365 | return which_alternative ? | |
1366 | "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; | |
1367 | else | |
1368 | return which_alternative ? | |
1369 | "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; | |
1370 | } | |
1371 | [(set_attr "op_type" "RIE") | |
1372 | (set_attr "type" "branch") | |
1373 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1374 | (set (attr "length") | |
1375 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1376 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1377 | ; 10 byte for clgr/jg | |
1378 | ||
9db1d521 HP |
1379 | ;; |
1380 | ;;- Move instructions. | |
1381 | ;; | |
1382 | ||
1383 | ; | |
1384 | ; movti instruction pattern(s). | |
1385 | ; | |
1386 | ||
085261c8 AK |
1387 | ; FIXME: More constants are possible by enabling jxx, jyy constraints |
1388 | ; for TImode (use double-int for the calculations) | |
9db1d521 | 1389 | (define_insn "movti" |
085261c8 AK |
1390 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,v, v, v,v,d, v,QR, d,o") |
1391 | (match_operand:TI 1 "general_operand" "QS, d,v,j00,jm1,d,v,QR, v,dPRT,d"))] | |
9602b6a1 | 1392 | "TARGET_ZARCH" |
4023fb28 | 1393 | "@ |
fc0ea003 UW |
1394 | lmg\t%0,%N0,%S1 |
1395 | stmg\t%1,%N1,%S0 | |
085261c8 AK |
1396 | vlr\t%v0,%v1 |
1397 | vzero\t%v0 | |
1398 | vone\t%v0 | |
1399 | vlvgp\t%v0,%1,%N1 | |
1400 | # | |
1401 | vl\t%v0,%1 | |
1402 | vst\t%v1,%0 | |
4023fb28 | 1403 | # |
19b63d8e | 1404 | #" |
085261c8 AK |
1405 | [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*") |
1406 | (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*") | |
1407 | (set_attr "cpu_facility" "*,*,vec,vec,vec,vec,vec,vec,vec,*,*")]) | |
4023fb28 UW |
1408 | |
1409 | (define_split | |
1410 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1411 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1412 | "TARGET_ZARCH && reload_completed |
dc65c307 | 1413 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1414 | [(set (match_dup 2) (match_dup 4)) |
1415 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1416 | { |
dc65c307 UW |
1417 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1418 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1419 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1420 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1421 | }) | |
1422 | ||
1423 | (define_split | |
1424 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1425 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1426 | "TARGET_ZARCH && reload_completed |
dc65c307 UW |
1427 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" |
1428 | [(set (match_dup 2) (match_dup 4)) | |
1429 | (set (match_dup 3) (match_dup 5))] | |
1430 | { | |
1431 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1432 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1433 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1434 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1435 | }) | |
4023fb28 | 1436 | |
085261c8 AK |
1437 | ; Use part of the TImode target reg to perform the address |
1438 | ; calculation. If the TImode value is supposed to be copied into a VR | |
1439 | ; this splitter is not necessary. | |
4023fb28 UW |
1440 | (define_split |
1441 | [(set (match_operand:TI 0 "register_operand" "") | |
1442 | (match_operand:TI 1 "memory_operand" ""))] | |
9602b6a1 | 1443 | "TARGET_ZARCH && reload_completed |
085261c8 | 1444 | && !VECTOR_REG_P (operands[0]) |
4023fb28 | 1445 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1446 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1447 | { |
1448 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
9602b6a1 | 1449 | addr = gen_lowpart (Pmode, addr); |
a41c6c53 UW |
1450 | s390_load_address (addr, XEXP (operands[1], 0)); |
1451 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1452 | }) |
1453 | ||
833cd70a | 1454 | |
085261c8 AK |
1455 | ; Split a VR -> GPR TImode move into 2 vector load GR from VR element. |
1456 | ; For the higher order bits we do simply a DImode move while the | |
1457 | ; second part is done via vec extract. Both will end up as vlgvg. | |
1458 | (define_split | |
1459 | [(set (match_operand:TI 0 "register_operand" "") | |
1460 | (match_operand:TI 1 "register_operand" ""))] | |
1461 | "TARGET_VX && reload_completed | |
1462 | && GENERAL_REG_P (operands[0]) | |
1463 | && VECTOR_REG_P (operands[1])" | |
1464 | [(set (match_dup 2) (match_dup 4)) | |
1465 | (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)] | |
1466 | UNSPEC_VEC_EXTRACT))] | |
1467 | { | |
1468 | operands[2] = operand_subword (operands[0], 0, 0, TImode); | |
1469 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1470 | operands[4] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
1471 | operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1])); | |
1472 | }) | |
1473 | ||
833cd70a AK |
1474 | ; |
1475 | ; Patterns used for secondary reloads | |
1476 | ; | |
1477 | ||
963fc8d0 AK |
1478 | ; z10 provides move instructions accepting larl memory operands. |
1479 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1480 | ; These patterns are also used for unaligned SI and DI accesses. | |
1481 | ||
085261c8 AK |
1482 | (define_expand "reload<ALL:mode><P:mode>_tomem_z10" |
1483 | [(parallel [(match_operand:ALL 0 "memory_operand" "") | |
1484 | (match_operand:ALL 1 "register_operand" "=d") | |
1485 | (match_operand:P 2 "register_operand" "=&a")])] | |
963fc8d0 AK |
1486 | "TARGET_Z10" |
1487 | { | |
1488 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1489 | DONE; | |
1490 | }) | |
1491 | ||
085261c8 AK |
1492 | (define_expand "reload<ALL:mode><P:mode>_toreg_z10" |
1493 | [(parallel [(match_operand:ALL 0 "register_operand" "=d") | |
1494 | (match_operand:ALL 1 "memory_operand" "") | |
1495 | (match_operand:P 2 "register_operand" "=a")])] | |
963fc8d0 AK |
1496 | "TARGET_Z10" |
1497 | { | |
1498 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1499 | DONE; | |
1500 | }) | |
1501 | ||
1502 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1503 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1504 | (match_operand:P 1 "larl_operand" "") | |
1505 | (match_operand:P 2 "register_operand" "=a")])] | |
1506 | "TARGET_Z10" | |
1507 | { | |
1508 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1509 | DONE; | |
1510 | }) | |
1511 | ||
833cd70a AK |
1512 | ; Handles loading a PLUS (load address) expression |
1513 | ||
1514 | (define_expand "reload<mode>_plus" | |
1515 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1516 | (match_operand:P 1 "s390_plus_operand" "") | |
1517 | (match_operand:P 2 "register_operand" "=&a")])] | |
1518 | "" | |
1519 | { | |
1520 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1521 | DONE; | |
1522 | }) | |
1523 | ||
085261c8 AK |
1524 | ; Not all the indirect memory access instructions support the full |
1525 | ; format (long disp + index + base). So whenever a move from/to such | |
1526 | ; an address is required and the instruction cannot deal with it we do | |
1527 | ; a load address into a scratch register first and use this as the new | |
1528 | ; base register. | |
1529 | ; This in particular is used for: | |
1530 | ; - non-offsetable memory accesses for multiword moves | |
1531 | ; - full vector reg moves with long displacements | |
833cd70a | 1532 | |
085261c8 | 1533 | (define_expand "reload<mode>_la_in" |
833cd70a AK |
1534 | [(parallel [(match_operand 0 "register_operand" "") |
1535 | (match_operand 1 "" "") | |
1536 | (match_operand:P 2 "register_operand" "=&a")])] | |
1537 | "" | |
1538 | { | |
1539 | gcc_assert (MEM_P (operands[1])); | |
1540 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1541 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1542 | emit_move_insn (operands[0], operands[1]); | |
1543 | DONE; | |
1544 | }) | |
1545 | ||
085261c8 | 1546 | (define_expand "reload<mode>_la_out" |
833cd70a AK |
1547 | [(parallel [(match_operand 0 "" "") |
1548 | (match_operand 1 "register_operand" "") | |
1549 | (match_operand:P 2 "register_operand" "=&a")])] | |
1550 | "" | |
dc65c307 | 1551 | { |
9c3c3dcc | 1552 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1553 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1554 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1555 | emit_move_insn (operands[0], operands[1]); | |
1556 | DONE; | |
1557 | }) | |
9db1d521 | 1558 | |
1f9e1fc6 AK |
1559 | (define_expand "reload<mode>_PIC_addr" |
1560 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1561 | (match_operand 1 "larl_operand" "") | |
1562 | (match_operand:P 2 "register_operand" "=a")])] | |
1563 | "" | |
1564 | { | |
0a2aaacc KG |
1565 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1566 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1567 | }) |
1568 | ||
9db1d521 HP |
1569 | ; |
1570 | ; movdi instruction pattern(s). | |
1571 | ; | |
1572 | ||
9db1d521 HP |
1573 | (define_expand "movdi" |
1574 | [(set (match_operand:DI 0 "general_operand" "") | |
1575 | (match_operand:DI 1 "general_operand" ""))] | |
1576 | "" | |
9db1d521 | 1577 | { |
fd3cd001 | 1578 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1579 | if (TARGET_64BIT |
1580 | && (SYMBOLIC_CONST (operands[1]) | |
1581 | || (GET_CODE (operands[1]) == PLUS | |
1582 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1583 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1584 | emit_symbolic_move (operands); |
10bbf137 | 1585 | }) |
9db1d521 | 1586 | |
4023fb28 UW |
1587 | (define_insn "*movdi_larl" |
1588 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1589 | (match_operand:DI 1 "larl_operand" "X"))] | |
1590 | "TARGET_64BIT | |
8e509cf9 | 1591 | && !FP_REG_P (operands[0])" |
d40c829f | 1592 | "larl\t%0,%1" |
4023fb28 | 1593 | [(set_attr "op_type" "RIL") |
9381e3f1 WG |
1594 | (set_attr "type" "larl") |
1595 | (set_attr "z10prop" "z10_super_A1")]) | |
4023fb28 | 1596 | |
3af8e996 | 1597 | (define_insn "*movdi_64" |
85dae55a | 1598 | [(set (match_operand:DI 0 "nonimmediate_operand" |
085261c8 | 1599 | "=d, d, d, d, d, d, d, d,f,d,d,d,d, d,RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d, v,QR") |
85dae55a | 1600 | (match_operand:DI 1 "general_operand" |
085261c8 | 1601 | " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,QR, v"))] |
9602b6a1 | 1602 | "TARGET_ZARCH" |
85dae55a AK |
1603 | "@ |
1604 | lghi\t%0,%h1 | |
1605 | llihh\t%0,%i1 | |
1606 | llihl\t%0,%i1 | |
1607 | llilh\t%0,%i1 | |
1608 | llill\t%0,%i1 | |
1609 | lgfi\t%0,%1 | |
1610 | llihf\t%0,%k1 | |
1611 | llilf\t%0,%k1 | |
1612 | ldgr\t%0,%1 | |
1613 | lgdr\t%0,%1 | |
1614 | lay\t%0,%a1 | |
963fc8d0 | 1615 | lgrl\t%0,%1 |
85dae55a AK |
1616 | lgr\t%0,%1 |
1617 | lg\t%0,%1 | |
1618 | stg\t%1,%0 | |
1619 | ldr\t%0,%1 | |
1620 | ld\t%0,%1 | |
1621 | ldy\t%0,%1 | |
1622 | std\t%1,%0 | |
1623 | stdy\t%1,%0 | |
963fc8d0 AK |
1624 | stgrl\t%1,%0 |
1625 | mvghi\t%0,%1 | |
85dae55a AK |
1626 | # |
1627 | # | |
1628 | stam\t%1,%N1,%S0 | |
085261c8 AK |
1629 | lam\t%0,%N0,%S1 |
1630 | vleig\t%v0,%h1,0 | |
1631 | vlr\t%v0,%v1 | |
1632 | vlvgg\t%v0,%1,0 | |
1633 | vlgvg\t%0,%v1,0 | |
1634 | vleg\t%v0,%1,0 | |
1635 | vsteg\t%v1,%0,0" | |
963fc8d0 | 1636 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
085261c8 | 1637 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
963fc8d0 | 1638 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
085261c8 AK |
1639 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*, |
1640 | *,*,*,*,*,*,*") | |
3af8e996 | 1641 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1642 | z10,*,*,*,*,*,longdisp,*,longdisp, |
085261c8 | 1643 | z10,z10,*,*,*,*,vec,vec,vec,vec,vec,vec") |
9381e3f1 WG |
1644 | (set_attr "z10prop" "z10_fwd_A1, |
1645 | z10_fwd_E1, | |
1646 | z10_fwd_E1, | |
1647 | z10_fwd_E1, | |
1648 | z10_fwd_E1, | |
1649 | z10_fwd_A1, | |
1650 | z10_fwd_E1, | |
1651 | z10_fwd_E1, | |
1652 | *, | |
1653 | *, | |
1654 | z10_fwd_A1, | |
1655 | z10_fwd_A3, | |
1656 | z10_fr_E1, | |
1657 | z10_fwd_A3, | |
1658 | z10_rec, | |
1659 | *, | |
1660 | *, | |
1661 | *, | |
1662 | *, | |
1663 | *, | |
1664 | z10_rec, | |
1665 | z10_super, | |
1666 | *, | |
1667 | *, | |
1668 | *, | |
085261c8 | 1669 | *,*,*,*,*,*,*") |
9381e3f1 | 1670 | ]) |
c5aa1d12 UW |
1671 | |
1672 | (define_split | |
1673 | [(set (match_operand:DI 0 "register_operand" "") | |
1674 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1675 | "TARGET_ZARCH && ACCESS_REG_P (operands[1])" |
c5aa1d12 UW |
1676 | [(set (match_dup 2) (match_dup 3)) |
1677 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1678 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1679 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1680 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1681 | ||
1682 | (define_split | |
1683 | [(set (match_operand:DI 0 "register_operand" "") | |
1684 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1685 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1686 | && dead_or_set_p (insn, operands[1])" |
1687 | [(set (match_dup 3) (match_dup 2)) | |
1688 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1689 | (set (match_dup 4) (match_dup 2))] | |
1690 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1691 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1692 | ||
1693 | (define_split | |
1694 | [(set (match_operand:DI 0 "register_operand" "") | |
1695 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1696 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1697 | && !dead_or_set_p (insn, operands[1])" |
1698 | [(set (match_dup 3) (match_dup 2)) | |
1699 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1700 | (set (match_dup 4) (match_dup 2)) | |
1701 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1702 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1703 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1704 | |
1705 | (define_insn "*movdi_31" | |
963fc8d0 | 1706 | [(set (match_operand:DI 0 "nonimmediate_operand" |
f2dc2f86 | 1707 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1708 | (match_operand:DI 1 "general_operand" |
f2dc2f86 | 1709 | " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))] |
9602b6a1 | 1710 | "!TARGET_ZARCH" |
4023fb28 | 1711 | "@ |
fc0ea003 | 1712 | lm\t%0,%N0,%S1 |
c4d50129 | 1713 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1714 | stm\t%1,%N1,%S0 |
c4d50129 | 1715 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1716 | # |
1717 | # | |
d40c829f UW |
1718 | ldr\t%0,%1 |
1719 | ld\t%0,%1 | |
1720 | ldy\t%0,%1 | |
1721 | std\t%1,%0 | |
1722 | stdy\t%1,%0 | |
19b63d8e | 1723 | #" |
f2dc2f86 AK |
1724 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1725 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
1726 | (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")]) | |
963fc8d0 AK |
1727 | |
1728 | ; For a load from a symbol ref we can use one of the target registers | |
1729 | ; together with larl to load the address. | |
1730 | (define_split | |
1731 | [(set (match_operand:DI 0 "register_operand" "") | |
1732 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1733 | "!TARGET_ZARCH && reload_completed && TARGET_Z10 |
963fc8d0 AK |
1734 | && larl_operand (XEXP (operands[1], 0), SImode)" |
1735 | [(set (match_dup 2) (match_dup 3)) | |
1736 | (set (match_dup 0) (match_dup 1))] | |
1737 | { | |
1738 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1739 | operands[3] = XEXP (operands[1], 0); | |
1740 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1741 | }) | |
4023fb28 UW |
1742 | |
1743 | (define_split | |
1744 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1745 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1746 | "!TARGET_ZARCH && reload_completed |
dc65c307 | 1747 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1748 | [(set (match_dup 2) (match_dup 4)) |
1749 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1750 | { |
dc65c307 UW |
1751 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1752 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1753 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1754 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1755 | }) | |
1756 | ||
1757 | (define_split | |
1758 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1759 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1760 | "!TARGET_ZARCH && reload_completed |
dc65c307 UW |
1761 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" |
1762 | [(set (match_dup 2) (match_dup 4)) | |
1763 | (set (match_dup 3) (match_dup 5))] | |
1764 | { | |
1765 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1766 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1767 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1768 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1769 | }) | |
9db1d521 | 1770 | |
4023fb28 UW |
1771 | (define_split |
1772 | [(set (match_operand:DI 0 "register_operand" "") | |
1773 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1774 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 1775 | && !FP_REG_P (operands[0]) |
4023fb28 | 1776 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1777 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1778 | { |
1779 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1780 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1781 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1782 | }) |
1783 | ||
84817c5d UW |
1784 | (define_peephole2 |
1785 | [(set (match_operand:DI 0 "register_operand" "") | |
1786 | (mem:DI (match_operand 1 "address_operand" "")))] | |
9602b6a1 | 1787 | "TARGET_ZARCH |
84817c5d UW |
1788 | && !FP_REG_P (operands[0]) |
1789 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1790 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1791 | && get_pool_mode (operands[1]) == DImode | |
1792 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1793 | [(set (match_dup 0) (match_dup 2))] | |
1794 | "operands[2] = get_pool_constant (operands[1]);") | |
1795 | ||
7bdff56f UW |
1796 | (define_insn "*la_64" |
1797 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1798 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
7bdff56f UW |
1799 | "TARGET_64BIT" |
1800 | "@ | |
1801 | la\t%0,%a1 | |
1802 | lay\t%0,%a1" | |
1803 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1804 | (set_attr "type" "la") |
1805 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1806 | |
1807 | (define_peephole2 | |
1808 | [(parallel | |
1809 | [(set (match_operand:DI 0 "register_operand" "") | |
1810 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1811 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1812 | "TARGET_64BIT |
e1d5ee28 | 1813 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1814 | [(set (match_dup 0) (match_dup 1))] |
1815 | "") | |
1816 | ||
1817 | (define_peephole2 | |
1818 | [(set (match_operand:DI 0 "register_operand" "") | |
1819 | (match_operand:DI 1 "register_operand" "")) | |
1820 | (parallel | |
1821 | [(set (match_dup 0) | |
1822 | (plus:DI (match_dup 0) | |
1823 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1824 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1825 | "TARGET_64BIT |
1826 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1827 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1828 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1829 | "") | |
1830 | ||
9db1d521 HP |
1831 | ; |
1832 | ; movsi instruction pattern(s). | |
1833 | ; | |
1834 | ||
9db1d521 HP |
1835 | (define_expand "movsi" |
1836 | [(set (match_operand:SI 0 "general_operand" "") | |
1837 | (match_operand:SI 1 "general_operand" ""))] | |
1838 | "" | |
9db1d521 | 1839 | { |
fd3cd001 | 1840 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1841 | if (!TARGET_64BIT |
1842 | && (SYMBOLIC_CONST (operands[1]) | |
1843 | || (GET_CODE (operands[1]) == PLUS | |
1844 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1845 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 1846 | emit_symbolic_move (operands); |
10bbf137 | 1847 | }) |
9db1d521 | 1848 | |
9e8327e3 UW |
1849 | (define_insn "*movsi_larl" |
1850 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1851 | (match_operand:SI 1 "larl_operand" "X"))] | |
1852 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1853 | && !FP_REG_P (operands[0])" | |
1854 | "larl\t%0,%1" | |
1855 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1856 | (set_attr "type" "larl") |
729e750f | 1857 | (set_attr "z10prop" "z10_fwd_A1")]) |
9e8327e3 | 1858 | |
f19a9af7 | 1859 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1860 | [(set (match_operand:SI 0 "nonimmediate_operand" |
085261c8 | 1861 | "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d, v,QR") |
2f7e5a0d | 1862 | (match_operand:SI 1 "general_operand" |
085261c8 | 1863 | " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,QR, v"))] |
f19a9af7 | 1864 | "TARGET_ZARCH" |
9db1d521 | 1865 | "@ |
f19a9af7 AK |
1866 | lhi\t%0,%h1 |
1867 | llilh\t%0,%i1 | |
1868 | llill\t%0,%i1 | |
ec24698e | 1869 | iilf\t%0,%o1 |
f19a9af7 | 1870 | lay\t%0,%a1 |
963fc8d0 | 1871 | lrl\t%0,%1 |
d40c829f UW |
1872 | lr\t%0,%1 |
1873 | l\t%0,%1 | |
1874 | ly\t%0,%1 | |
1875 | st\t%1,%0 | |
1876 | sty\t%1,%0 | |
085261c8 | 1877 | lder\t%0,%1 |
d40c829f | 1878 | ler\t%0,%1 |
085261c8 | 1879 | lde\t%0,%1 |
d40c829f UW |
1880 | le\t%0,%1 |
1881 | ley\t%0,%1 | |
1882 | ste\t%1,%0 | |
1883 | stey\t%1,%0 | |
c5aa1d12 UW |
1884 | ear\t%0,%1 |
1885 | sar\t%0,%1 | |
1886 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
1887 | strl\t%1,%0 |
1888 | mvhi\t%0,%1 | |
085261c8 AK |
1889 | lam\t%0,%0,%S1 |
1890 | vleif\t%v0,%h1,0 | |
1891 | vlr\t%v0,%v1 | |
1892 | vlvgf\t%v0,%1,0 | |
1893 | vlgvf\t%0,%v1,0 | |
1894 | vlef\t%v0,%1,0 | |
1895 | vstef\t%v1,%0,0" | |
963fc8d0 | 1896 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
085261c8 | 1897 | RRE,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
9381e3f1 WG |
1898 | (set_attr "type" "*, |
1899 | *, | |
1900 | *, | |
1901 | *, | |
1902 | la, | |
1903 | larl, | |
1904 | lr, | |
1905 | load, | |
1906 | load, | |
1907 | store, | |
1908 | store, | |
1909 | floadsf, | |
1910 | floadsf, | |
1911 | floadsf, | |
085261c8 AK |
1912 | floadsf, |
1913 | floadsf, | |
9381e3f1 WG |
1914 | fstoresf, |
1915 | fstoresf, | |
1916 | *, | |
1917 | *, | |
1918 | *, | |
1919 | larl, | |
1920 | *, | |
085261c8 | 1921 | *,*,*,*,*,*,*") |
963fc8d0 | 1922 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
085261c8 | 1923 | vec,*,vec,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vec,vec,vec,vec,vec,vec") |
9381e3f1 WG |
1924 | (set_attr "z10prop" "z10_fwd_A1, |
1925 | z10_fwd_E1, | |
1926 | z10_fwd_E1, | |
1927 | z10_fwd_A1, | |
1928 | z10_fwd_A1, | |
1929 | z10_fwd_A3, | |
1930 | z10_fr_E1, | |
1931 | z10_fwd_A3, | |
1932 | z10_fwd_A3, | |
729e750f | 1933 | z10_rec, |
9381e3f1 WG |
1934 | z10_rec, |
1935 | *, | |
1936 | *, | |
1937 | *, | |
1938 | *, | |
1939 | *, | |
085261c8 AK |
1940 | *, |
1941 | *, | |
9381e3f1 WG |
1942 | z10_super_E1, |
1943 | z10_super, | |
1944 | *, | |
1945 | z10_rec, | |
1946 | z10_super, | |
085261c8 | 1947 | *,*,*,*,*,*,*")]) |
f19a9af7 AK |
1948 | |
1949 | (define_insn "*movsi_esa" | |
085261c8 AK |
1950 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t") |
1951 | (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
1952 | "!TARGET_ZARCH" |
1953 | "@ | |
1954 | lhi\t%0,%h1 | |
1955 | lr\t%0,%1 | |
1956 | l\t%0,%1 | |
1957 | st\t%1,%0 | |
085261c8 | 1958 | lder\t%0,%1 |
f19a9af7 | 1959 | ler\t%0,%1 |
085261c8 | 1960 | lde\t%0,%1 |
f19a9af7 AK |
1961 | le\t%0,%1 |
1962 | ste\t%1,%0 | |
c5aa1d12 UW |
1963 | ear\t%0,%1 |
1964 | sar\t%0,%1 | |
1965 | stam\t%1,%1,%S0 | |
f2dc2f86 | 1966 | lam\t%0,%0,%S1" |
085261c8 AK |
1967 | [(set_attr "op_type" "RI,RR,RX,RX,RRE,RR,RXE,RX,RX,RRE,RRE,RS,RS") |
1968 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*") | |
1969 | (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1, | |
1970 | z10_super,*,*") | |
1971 | (set_attr "cpu_facility" "*,*,*,*,vec,*,vec,*,*,*,*,*,*") | |
9381e3f1 | 1972 | ]) |
9db1d521 | 1973 | |
84817c5d UW |
1974 | (define_peephole2 |
1975 | [(set (match_operand:SI 0 "register_operand" "") | |
1976 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1977 | "!FP_REG_P (operands[0]) | |
1978 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1979 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1980 | && get_pool_mode (operands[1]) == SImode | |
1981 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1982 | [(set (match_dup 0) (match_dup 2))] | |
1983 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 1984 | |
7bdff56f UW |
1985 | (define_insn "*la_31" |
1986 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1987 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
7bdff56f UW |
1988 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
1989 | "@ | |
1990 | la\t%0,%a1 | |
1991 | lay\t%0,%a1" | |
1992 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1993 | (set_attr "type" "la") |
1994 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1995 | |
1996 | (define_peephole2 | |
1997 | [(parallel | |
1998 | [(set (match_operand:SI 0 "register_operand" "") | |
1999 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 2000 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 2001 | "!TARGET_64BIT |
e1d5ee28 | 2002 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
2003 | [(set (match_dup 0) (match_dup 1))] |
2004 | "") | |
2005 | ||
2006 | (define_peephole2 | |
2007 | [(set (match_operand:SI 0 "register_operand" "") | |
2008 | (match_operand:SI 1 "register_operand" "")) | |
2009 | (parallel | |
2010 | [(set (match_dup 0) | |
2011 | (plus:SI (match_dup 0) | |
2012 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 2013 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
2014 | "!TARGET_64BIT |
2015 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 2016 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
2017 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
2018 | "") | |
2019 | ||
2020 | (define_insn "*la_31_and" | |
2021 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 2022 | (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT") |
7bdff56f UW |
2023 | (const_int 2147483647)))] |
2024 | "!TARGET_64BIT" | |
2025 | "@ | |
2026 | la\t%0,%a1 | |
2027 | lay\t%0,%a1" | |
2028 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
2029 | (set_attr "type" "la") |
2030 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
2031 | |
2032 | (define_insn_and_split "*la_31_and_cc" | |
2033 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2034 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
2035 | (const_int 2147483647))) | |
ae156f85 | 2036 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
2037 | "!TARGET_64BIT" |
2038 | "#" | |
2039 | "&& reload_completed" | |
2040 | [(set (match_dup 0) | |
2041 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
2042 | "" | |
2043 | [(set_attr "op_type" "RX") | |
2044 | (set_attr "type" "la")]) | |
2045 | ||
2046 | (define_insn "force_la_31" | |
2047 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 2048 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")) |
7bdff56f UW |
2049 | (use (const_int 0))] |
2050 | "!TARGET_64BIT" | |
2051 | "@ | |
2052 | la\t%0,%a1 | |
2053 | lay\t%0,%a1" | |
2054 | [(set_attr "op_type" "RX") | |
9381e3f1 WG |
2055 | (set_attr "type" "la") |
2056 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f | 2057 | |
9db1d521 HP |
2058 | ; |
2059 | ; movhi instruction pattern(s). | |
2060 | ; | |
2061 | ||
02ed3c5e UW |
2062 | (define_expand "movhi" |
2063 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
2064 | (match_operand:HI 1 "general_operand" ""))] | |
2065 | "" | |
2066 | { | |
2f7e5a0d | 2067 | /* Make it explicit that loading a register from memory |
02ed3c5e | 2068 | always sign-extends (at least) to SImode. */ |
b3a13419 | 2069 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 2070 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2071 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
2072 | { |
2073 | rtx tmp = gen_reg_rtx (SImode); | |
2074 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
f7df4a84 | 2075 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2076 | operands[1] = gen_lowpart (HImode, tmp); |
2077 | } | |
2078 | }) | |
2079 | ||
2080 | (define_insn "*movhi" | |
085261c8 AK |
2081 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d, v,QR") |
2082 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,QR, v"))] | |
9db1d521 HP |
2083 | "" |
2084 | "@ | |
d40c829f UW |
2085 | lr\t%0,%1 |
2086 | lhi\t%0,%h1 | |
2087 | lh\t%0,%1 | |
2088 | lhy\t%0,%1 | |
963fc8d0 | 2089 | lhrl\t%0,%1 |
d40c829f UW |
2090 | sth\t%1,%0 |
2091 | sthy\t%1,%0 | |
963fc8d0 | 2092 | sthrl\t%1,%0 |
085261c8 AK |
2093 | mvhhi\t%0,%1 |
2094 | vleih\t%v0,%h1,0 | |
2095 | vlr\t%v0,%v1 | |
2096 | vlvgh\t%v0,%1,0 | |
2097 | vlgvh\t%0,%v1,0 | |
2098 | vleh\t%v0,%1,0 | |
2099 | vsteh\t%v1,%0,0" | |
2100 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX") | |
2101 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*") | |
2102 | (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,vec,vec,vec,vec,vec,vec") | |
9381e3f1 WG |
2103 | (set_attr "z10prop" "z10_fr_E1, |
2104 | z10_fwd_A1, | |
2105 | z10_super_E1, | |
2106 | z10_super_E1, | |
2107 | z10_super_E1, | |
729e750f | 2108 | z10_rec, |
9381e3f1 WG |
2109 | z10_rec, |
2110 | z10_rec, | |
085261c8 | 2111 | z10_super,*,*,*,*,*,*")]) |
9db1d521 | 2112 | |
84817c5d UW |
2113 | (define_peephole2 |
2114 | [(set (match_operand:HI 0 "register_operand" "") | |
2115 | (mem:HI (match_operand 1 "address_operand" "")))] | |
2116 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2117 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2118 | && get_pool_mode (operands[1]) == HImode | |
2119 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2120 | [(set (match_dup 0) (match_dup 2))] | |
2121 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2122 | |
9db1d521 HP |
2123 | ; |
2124 | ; movqi instruction pattern(s). | |
2125 | ; | |
2126 | ||
02ed3c5e UW |
2127 | (define_expand "movqi" |
2128 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2129 | (match_operand:QI 1 "general_operand" ""))] | |
2130 | "" | |
2131 | { | |
c19ec8f9 | 2132 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 2133 | is just as fast as a QImode load. */ |
b3a13419 | 2134 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 2135 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2136 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 2137 | { |
9602b6a1 AK |
2138 | rtx tmp = gen_reg_rtx (DImode); |
2139 | rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
f7df4a84 | 2140 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2141 | operands[1] = gen_lowpart (QImode, tmp); |
2142 | } | |
2143 | }) | |
4023fb28 | 2144 | |
02ed3c5e | 2145 | (define_insn "*movqi" |
085261c8 AK |
2146 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d, v,QR") |
2147 | (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,QR, v"))] | |
9db1d521 HP |
2148 | "" |
2149 | "@ | |
d40c829f UW |
2150 | lr\t%0,%1 |
2151 | lhi\t%0,%b1 | |
2152 | ic\t%0,%1 | |
2153 | icy\t%0,%1 | |
2154 | stc\t%1,%0 | |
2155 | stcy\t%1,%0 | |
fc0ea003 | 2156 | mvi\t%S0,%b1 |
0a88561f | 2157 | mviy\t%S0,%b1 |
085261c8 AK |
2158 | # |
2159 | vleib\t%v0,%b1,0 | |
2160 | vlr\t%v0,%v1 | |
2161 | vlvgb\t%v0,%1,0 | |
2162 | vlgvb\t%0,%v1,0 | |
2163 | vleb\t%v0,%1,0 | |
2164 | vsteb\t%v1,%0,0" | |
2165 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX") | |
2166 | (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*") | |
2167 | (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,vec,vec,vec,vec,vec,vec") | |
9381e3f1 WG |
2168 | (set_attr "z10prop" "z10_fr_E1, |
2169 | z10_fwd_A1, | |
2170 | z10_super_E1, | |
2171 | z10_super_E1, | |
729e750f | 2172 | z10_rec, |
9381e3f1 WG |
2173 | z10_rec, |
2174 | z10_super, | |
0a88561f | 2175 | z10_super, |
085261c8 | 2176 | *,*,*,*,*,*,*")]) |
9db1d521 | 2177 | |
84817c5d UW |
2178 | (define_peephole2 |
2179 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2180 | (mem:QI (match_operand 1 "address_operand" "")))] | |
2181 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2182 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2183 | && get_pool_mode (operands[1]) == QImode | |
2184 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2185 | [(set (match_dup 0) (match_dup 2))] | |
2186 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2187 | |
9db1d521 | 2188 | ; |
05b9aaaa | 2189 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
2190 | ; |
2191 | ||
2192 | (define_insn "*movstrictqi" | |
d3632d41 UW |
2193 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
2194 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 2195 | "" |
d3632d41 | 2196 | "@ |
d40c829f UW |
2197 | ic\t%0,%1 |
2198 | icy\t%0,%1" | |
9381e3f1 | 2199 | [(set_attr "op_type" "RX,RXY") |
729e750f | 2200 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2201 | |
2202 | ; | |
2203 | ; movstricthi instruction pattern(s). | |
2204 | ; | |
2205 | ||
2206 | (define_insn "*movstricthi" | |
d3632d41 | 2207 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 2208 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 2209 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2210 | "" |
d3632d41 | 2211 | "@ |
fc0ea003 UW |
2212 | icm\t%0,3,%S1 |
2213 | icmy\t%0,3,%S1" | |
9381e3f1 WG |
2214 | [(set_attr "op_type" "RS,RSY") |
2215 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
2216 | |
2217 | ; | |
2218 | ; movstrictsi instruction pattern(s). | |
2219 | ; | |
2220 | ||
05b9aaaa | 2221 | (define_insn "movstrictsi" |
c5aa1d12 UW |
2222 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
2223 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9602b6a1 | 2224 | "TARGET_ZARCH" |
9db1d521 | 2225 | "@ |
d40c829f UW |
2226 | lr\t%0,%1 |
2227 | l\t%0,%1 | |
c5aa1d12 UW |
2228 | ly\t%0,%1 |
2229 | ear\t%0,%1" | |
2230 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 WG |
2231 | (set_attr "type" "lr,load,load,*") |
2232 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) | |
9db1d521 | 2233 | |
f61a2c7d | 2234 | ; |
609e7e80 | 2235 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
2236 | ; |
2237 | ||
609e7e80 AK |
2238 | (define_expand "mov<mode>" |
2239 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
2240 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
2241 | "" |
2242 | "") | |
2243 | ||
609e7e80 | 2244 | (define_insn "*mov<mode>_64" |
65b1d8ea AK |
2245 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o") |
2246 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))] | |
9602b6a1 | 2247 | "TARGET_ZARCH" |
f61a2c7d | 2248 | "@ |
65b1d8ea | 2249 | lzxr\t%0 |
f61a2c7d AK |
2250 | lxr\t%0,%1 |
2251 | # | |
2252 | # | |
2253 | lmg\t%0,%N0,%S1 | |
2254 | stmg\t%1,%N1,%S0 | |
2255 | # | |
f61a2c7d | 2256 | #" |
65b1d8ea AK |
2257 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
2258 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") | |
2259 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) | |
f61a2c7d | 2260 | |
609e7e80 | 2261 | (define_insn "*mov<mode>_31" |
65b1d8ea AK |
2262 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
2263 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
9602b6a1 | 2264 | "!TARGET_ZARCH" |
f61a2c7d | 2265 | "@ |
65b1d8ea | 2266 | lzxr\t%0 |
f61a2c7d AK |
2267 | lxr\t%0,%1 |
2268 | # | |
f61a2c7d | 2269 | #" |
65b1d8ea AK |
2270 | [(set_attr "op_type" "RRE,RRE,*,*") |
2271 | (set_attr "type" "fsimptf,fsimptf,*,*") | |
2272 | (set_attr "cpu_facility" "z196,*,*,*")]) | |
f61a2c7d AK |
2273 | |
2274 | ; TFmode in GPRs splitters | |
2275 | ||
2276 | (define_split | |
609e7e80 AK |
2277 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2278 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2279 | "TARGET_ZARCH && reload_completed |
609e7e80 | 2280 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
2281 | [(set (match_dup 2) (match_dup 4)) |
2282 | (set (match_dup 3) (match_dup 5))] | |
2283 | { | |
609e7e80 AK |
2284 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2285 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2286 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2287 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
2288 | }) |
2289 | ||
2290 | (define_split | |
609e7e80 AK |
2291 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2292 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2293 | "TARGET_ZARCH && reload_completed |
609e7e80 | 2294 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
2295 | [(set (match_dup 2) (match_dup 4)) |
2296 | (set (match_dup 3) (match_dup 5))] | |
2297 | { | |
609e7e80 AK |
2298 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2299 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2300 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2301 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
2302 | }) |
2303 | ||
2304 | (define_split | |
609e7e80 AK |
2305 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2306 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9602b6a1 | 2307 | "TARGET_ZARCH && reload_completed |
085261c8 | 2308 | && GENERAL_REG_P (operands[0]) |
f61a2c7d AK |
2309 | && !s_operand (operands[1], VOIDmode)" |
2310 | [(set (match_dup 0) (match_dup 1))] | |
2311 | { | |
609e7e80 | 2312 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a9e6994a | 2313 | addr = gen_lowpart (Pmode, addr); |
f61a2c7d AK |
2314 | s390_load_address (addr, XEXP (operands[1], 0)); |
2315 | operands[1] = replace_equiv_address (operands[1], addr); | |
2316 | }) | |
2317 | ||
7b6baae1 | 2318 | ; TFmode in BFPs splitters |
f61a2c7d AK |
2319 | |
2320 | (define_split | |
609e7e80 AK |
2321 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2322 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 2323 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
2324 | && FP_REG_P (operands[0])" |
2325 | [(set (match_dup 2) (match_dup 4)) | |
2326 | (set (match_dup 3) (match_dup 5))] | |
2327 | { | |
609e7e80 AK |
2328 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
2329 | <MODE>mode, 0); | |
2330 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
2331 | <MODE>mode, 8); | |
2332 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
2333 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
2334 | }) |
2335 | ||
2336 | (define_split | |
609e7e80 AK |
2337 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
2338 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
2339 | "reload_completed && offsettable_memref_p (operands[0]) |
2340 | && FP_REG_P (operands[1])" | |
2341 | [(set (match_dup 2) (match_dup 4)) | |
2342 | (set (match_dup 3) (match_dup 5))] | |
2343 | { | |
609e7e80 AK |
2344 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
2345 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
2346 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2347 | <MODE>mode, 0); | |
2348 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2349 | <MODE>mode, 8); | |
f61a2c7d AK |
2350 | }) |
2351 | ||
9db1d521 | 2352 | ; |
609e7e80 | 2353 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
2354 | ; |
2355 | ||
609e7e80 AK |
2356 | (define_expand "mov<mode>" |
2357 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2358 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 2359 | "" |
13c025c1 | 2360 | "") |
9db1d521 | 2361 | |
609e7e80 AK |
2362 | (define_insn "*mov<mode>_64dfp" |
2363 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
085261c8 | 2364 | "=f,f,f,d,f,f,R,T,d,d,d, d,b,RT,v,v,d,v,QR") |
609e7e80 | 2365 | (match_operand:DD_DF 1 "general_operand" |
085261c8 | 2366 | " G,f,d,f,R,T,f,f,G,d,b,RT,d, d,v,d,v,QR,v"))] |
9602b6a1 | 2367 | "TARGET_DFP" |
85dae55a | 2368 | "@ |
65b1d8ea | 2369 | lzdr\t%0 |
85dae55a AK |
2370 | ldr\t%0,%1 |
2371 | ldgr\t%0,%1 | |
2372 | lgdr\t%0,%1 | |
2373 | ld\t%0,%1 | |
2374 | ldy\t%0,%1 | |
2375 | std\t%1,%0 | |
2376 | stdy\t%1,%0 | |
45e5214c | 2377 | lghi\t%0,0 |
85dae55a | 2378 | lgr\t%0,%1 |
085261c8 | 2379 | lgrl\t%0,%1 |
85dae55a | 2380 | lg\t%0,%1 |
085261c8 AK |
2381 | stgrl\t%1,%0 |
2382 | stg\t%1,%0 | |
2383 | vlr\t%v0,%v1 | |
2384 | vlvgg\t%v0,%1,0 | |
2385 | vlgvg\t%0,%v1,0 | |
2386 | vleg\t%0,%1,0 | |
2387 | vsteg\t%1,%0,0" | |
2388 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRS,VRS,VRX,VRX") | |
65b1d8ea | 2389 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, |
085261c8 AK |
2390 | fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store") |
2391 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*") | |
2392 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")]) | |
85dae55a | 2393 | |
609e7e80 | 2394 | (define_insn "*mov<mode>_64" |
085261c8 AK |
2395 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d, d,b,RT,v,v,QR") |
2396 | (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,RT,d, d,v,QR,v"))] | |
9602b6a1 | 2397 | "TARGET_ZARCH" |
9db1d521 | 2398 | "@ |
65b1d8ea | 2399 | lzdr\t%0 |
d40c829f UW |
2400 | ldr\t%0,%1 |
2401 | ld\t%0,%1 | |
2402 | ldy\t%0,%1 | |
2403 | std\t%1,%0 | |
2404 | stdy\t%1,%0 | |
45e5214c | 2405 | lghi\t%0,0 |
d40c829f | 2406 | lgr\t%0,%1 |
085261c8 | 2407 | lgrl\t%0,%1 |
d40c829f | 2408 | lg\t%0,%1 |
085261c8 AK |
2409 | stgrl\t%1,%0 |
2410 | stg\t%1,%0 | |
2411 | vlr\t%v0,%v1 | |
2412 | vleg\t%v0,%1,0 | |
2413 | vsteg\t%v1,%0,0" | |
2414 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRX,VRX") | |
65b1d8ea | 2415 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, |
085261c8 AK |
2416 | fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store") |
2417 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*") | |
2418 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec")]) | |
609e7e80 AK |
2419 | |
2420 | (define_insn "*mov<mode>_31" | |
2421 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
65b1d8ea | 2422 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2423 | (match_operand:DD_DF 1 "general_operand" |
65b1d8ea | 2424 | " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))] |
9602b6a1 | 2425 | "!TARGET_ZARCH" |
9db1d521 | 2426 | "@ |
65b1d8ea | 2427 | lzdr\t%0 |
d40c829f UW |
2428 | ldr\t%0,%1 |
2429 | ld\t%0,%1 | |
2430 | ldy\t%0,%1 | |
2431 | std\t%1,%0 | |
2432 | stdy\t%1,%0 | |
fc0ea003 | 2433 | lm\t%0,%N0,%S1 |
c4d50129 | 2434 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2435 | stm\t%1,%N1,%S0 |
c4d50129 | 2436 | stmy\t%1,%N1,%S0 |
4023fb28 | 2437 | # |
19b63d8e | 2438 | #" |
65b1d8ea AK |
2439 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
2440 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2441 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") | |
2442 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) | |
4023fb28 UW |
2443 | |
2444 | (define_split | |
609e7e80 AK |
2445 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2446 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2447 | "!TARGET_ZARCH && reload_completed |
609e7e80 | 2448 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2449 | [(set (match_dup 2) (match_dup 4)) |
2450 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2451 | { |
609e7e80 AK |
2452 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2453 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2454 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2455 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2456 | }) |
2457 | ||
2458 | (define_split | |
609e7e80 AK |
2459 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2460 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2461 | "!TARGET_ZARCH && reload_completed |
609e7e80 | 2462 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2463 | [(set (match_dup 2) (match_dup 4)) |
2464 | (set (match_dup 3) (match_dup 5))] | |
2465 | { | |
609e7e80 AK |
2466 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2467 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2468 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2469 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2470 | }) |
9db1d521 | 2471 | |
4023fb28 | 2472 | (define_split |
609e7e80 AK |
2473 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2474 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
9602b6a1 | 2475 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 2476 | && !FP_REG_P (operands[0]) |
4023fb28 | 2477 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2478 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2479 | { |
609e7e80 | 2480 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2481 | s390_load_address (addr, XEXP (operands[1], 0)); |
2482 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2483 | }) |
2484 | ||
9db1d521 | 2485 | ; |
609e7e80 | 2486 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2487 | ; |
2488 | ||
609e7e80 AK |
2489 | (define_insn "mov<mode>" |
2490 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
085261c8 | 2491 | "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,QR") |
609e7e80 | 2492 | (match_operand:SD_SF 1 "general_operand" |
085261c8 | 2493 | " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,QR,v"))] |
4023fb28 | 2494 | "" |
9db1d521 | 2495 | "@ |
65b1d8ea | 2496 | lzer\t%0 |
085261c8 | 2497 | lder\t%0,%1 |
d40c829f | 2498 | ler\t%0,%1 |
085261c8 | 2499 | lde\t%0,%1 |
d40c829f UW |
2500 | le\t%0,%1 |
2501 | ley\t%0,%1 | |
2502 | ste\t%1,%0 | |
2503 | stey\t%1,%0 | |
45e5214c | 2504 | lhi\t%0,0 |
d40c829f | 2505 | lr\t%0,%1 |
085261c8 | 2506 | lrl\t%0,%1 |
d40c829f UW |
2507 | l\t%0,%1 |
2508 | ly\t%0,%1 | |
085261c8 | 2509 | strl\t%1,%0 |
d40c829f | 2510 | st\t%1,%0 |
085261c8 AK |
2511 | sty\t%1,%0 |
2512 | vlr\t%v0,%v1 | |
2513 | vleif\t%v0,0 | |
2514 | vlvgf\t%v0,%1,0 | |
2515 | vlgvf\t%0,%v1,0 | |
2516 | vleg\t%0,%1,0 | |
2517 | vsteg\t%1,%0,0" | |
2518 | [(set_attr "op_type" "RRE,RRE,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX") | |
2519 | (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>, | |
2520 | fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store") | |
2521 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*") | |
2522 | (set_attr "cpu_facility" "z196,vec,*,vec,*,*,*,*,*,*,z10,*,*,z10,*,*,vec,vec,vec,vec,vec,vec")]) | |
4023fb28 | 2523 | |
9dc62c00 AK |
2524 | ; |
2525 | ; movcc instruction pattern | |
2526 | ; | |
2527 | ||
2528 | (define_insn "movcc" | |
2529 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
5a3fe9b6 | 2530 | (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))] |
9dc62c00 AK |
2531 | "" |
2532 | "@ | |
2533 | lr\t%0,%1 | |
2534 | tmh\t%1,12288 | |
2535 | ipm\t%0 | |
a71f0749 DV |
2536 | l\t%0,%1 |
2537 | ly\t%0,%1 | |
2538 | st\t%1,%0 | |
2539 | sty\t%1,%0" | |
8dd3b235 | 2540 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
a71f0749 DV |
2541 | (set_attr "type" "lr,*,*,load,load,store,store") |
2542 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") | |
65b1d8ea | 2543 | (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) |
9dc62c00 | 2544 | |
19b63d8e UW |
2545 | ; |
2546 | ; Block move (MVC) patterns. | |
2547 | ; | |
2548 | ||
2549 | (define_insn "*mvc" | |
2550 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2551 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2552 | (use (match_operand 2 "const_int_operand" "n"))] | |
2553 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2554 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2555 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2556 | |
0a88561f AK |
2557 | ; This splitter converts a QI to QI mode copy into a BLK mode copy in |
2558 | ; order to have it implemented with mvc. | |
2559 | ||
2560 | (define_split | |
2561 | [(set (match_operand:QI 0 "memory_operand" "") | |
2562 | (match_operand:QI 1 "memory_operand" ""))] | |
2563 | "reload_completed" | |
2564 | [(parallel | |
2565 | [(set (match_dup 0) (match_dup 1)) | |
2566 | (use (const_int 1))])] | |
2567 | { | |
2568 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
2569 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2570 | }) | |
2571 | ||
2572 | ||
19b63d8e UW |
2573 | (define_peephole2 |
2574 | [(parallel | |
2575 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2576 | (match_operand:BLK 1 "memory_operand" "")) | |
2577 | (use (match_operand 2 "const_int_operand" ""))]) | |
2578 | (parallel | |
2579 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2580 | (match_operand:BLK 4 "memory_operand" "")) | |
2581 | (use (match_operand 5 "const_int_operand" ""))])] | |
2582 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
2583 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 2584 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2585 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2586 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2587 | [(parallel | |
2588 | [(set (match_dup 6) (match_dup 7)) | |
2589 | (use (match_dup 8))])] | |
2590 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2591 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2592 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2593 | ||
2594 | ||
9db1d521 HP |
2595 | ; |
2596 | ; load_multiple pattern(s). | |
2597 | ; | |
22ea6b4f UW |
2598 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2599 | ; we currently support load_multiple/store_multiple only after reload. | |
2600 | ; | |
9db1d521 HP |
2601 | |
2602 | (define_expand "load_multiple" | |
2603 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2604 | (match_operand 1 "" "")) | |
2605 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2606 | "reload_completed" |
9db1d521 | 2607 | { |
ef4bddc2 | 2608 | machine_mode mode; |
9db1d521 HP |
2609 | int regno; |
2610 | int count; | |
2611 | rtx from; | |
4023fb28 | 2612 | int i, off; |
9db1d521 HP |
2613 | |
2614 | /* Support only loading a constant number of fixed-point registers from | |
2615 | memory and only bother with this if more than two */ | |
2616 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2617 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2618 | || INTVAL (operands[2]) > 16 |
2619 | || GET_CODE (operands[1]) != MEM | |
2620 | || GET_CODE (operands[0]) != REG | |
2621 | || REGNO (operands[0]) >= 16) | |
2622 | FAIL; | |
2623 | ||
2624 | count = INTVAL (operands[2]); | |
2625 | regno = REGNO (operands[0]); | |
c19ec8f9 | 2626 | mode = GET_MODE (operands[0]); |
9602b6a1 | 2627 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2628 | FAIL; |
9db1d521 HP |
2629 | |
2630 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2631 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2632 | { |
2633 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2634 | { | |
2635 | from = XEXP (operands[1], 0); | |
2636 | off = 0; | |
2637 | } | |
2638 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2639 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2640 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2641 | { | |
2642 | from = XEXP (XEXP (operands[1], 0), 0); | |
2643 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2644 | } | |
2645 | else | |
2646 | FAIL; | |
4023fb28 UW |
2647 | } |
2648 | else | |
2649 | { | |
2650 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2651 | off = 0; | |
2652 | } | |
9db1d521 HP |
2653 | |
2654 | for (i = 0; i < count; i++) | |
2655 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2656 | = gen_rtx_SET (gen_rtx_REG (mode, regno + i), |
c19ec8f9 | 2657 | change_address (operands[1], mode, |
0a81f074 RS |
2658 | plus_constant (Pmode, from, |
2659 | off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2660 | }) |
9db1d521 HP |
2661 | |
2662 | (define_insn "*load_multiple_di" | |
2663 | [(match_parallel 0 "load_multiple_operation" | |
2664 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 2665 | (match_operand:DI 2 "s_operand" "QS"))])] |
9602b6a1 | 2666 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2667 | { |
2668 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2669 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2670 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2671 | } |
d3632d41 | 2672 | [(set_attr "op_type" "RSY") |
4023fb28 | 2673 | (set_attr "type" "lm")]) |
9db1d521 HP |
2674 | |
2675 | (define_insn "*load_multiple_si" | |
2676 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2677 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2678 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2679 | "reload_completed" |
9db1d521 HP |
2680 | { |
2681 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2682 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2683 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2684 | } |
d3632d41 | 2685 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2686 | (set_attr "type" "lm")]) |
9db1d521 HP |
2687 | |
2688 | ; | |
c7453384 | 2689 | ; store multiple pattern(s). |
9db1d521 HP |
2690 | ; |
2691 | ||
2692 | (define_expand "store_multiple" | |
2693 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2694 | (match_operand 1 "" "")) | |
2695 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2696 | "reload_completed" |
9db1d521 | 2697 | { |
ef4bddc2 | 2698 | machine_mode mode; |
9db1d521 HP |
2699 | int regno; |
2700 | int count; | |
2701 | rtx to; | |
4023fb28 | 2702 | int i, off; |
9db1d521 HP |
2703 | |
2704 | /* Support only storing a constant number of fixed-point registers to | |
2705 | memory and only bother with this if more than two. */ | |
2706 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2707 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2708 | || INTVAL (operands[2]) > 16 |
2709 | || GET_CODE (operands[0]) != MEM | |
2710 | || GET_CODE (operands[1]) != REG | |
2711 | || REGNO (operands[1]) >= 16) | |
2712 | FAIL; | |
2713 | ||
2714 | count = INTVAL (operands[2]); | |
2715 | regno = REGNO (operands[1]); | |
c19ec8f9 | 2716 | mode = GET_MODE (operands[1]); |
9602b6a1 | 2717 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2718 | FAIL; |
9db1d521 HP |
2719 | |
2720 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2721 | |
b3a13419 | 2722 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2723 | { |
2724 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2725 | { | |
2726 | to = XEXP (operands[0], 0); | |
2727 | off = 0; | |
2728 | } | |
2729 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2730 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2731 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2732 | { | |
2733 | to = XEXP (XEXP (operands[0], 0), 0); | |
2734 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2735 | } | |
2736 | else | |
2737 | FAIL; | |
4023fb28 | 2738 | } |
c7453384 | 2739 | else |
4023fb28 UW |
2740 | { |
2741 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2742 | off = 0; | |
2743 | } | |
9db1d521 HP |
2744 | |
2745 | for (i = 0; i < count; i++) | |
2746 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2747 | = gen_rtx_SET (change_address (operands[0], mode, |
0a81f074 RS |
2748 | plus_constant (Pmode, to, |
2749 | off + i * GET_MODE_SIZE (mode))), | |
c19ec8f9 | 2750 | gen_rtx_REG (mode, regno + i)); |
10bbf137 | 2751 | }) |
9db1d521 HP |
2752 | |
2753 | (define_insn "*store_multiple_di" | |
2754 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 2755 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 2756 | (match_operand:DI 2 "register_operand" "r"))])] |
9602b6a1 | 2757 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2758 | { |
2759 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2760 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2761 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 2762 | } |
d3632d41 | 2763 | [(set_attr "op_type" "RSY") |
4023fb28 | 2764 | (set_attr "type" "stm")]) |
9db1d521 HP |
2765 | |
2766 | ||
2767 | (define_insn "*store_multiple_si" | |
2768 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
2769 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
2770 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 2771 | "reload_completed" |
9db1d521 HP |
2772 | { |
2773 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2774 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2775 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 2776 | } |
d3632d41 | 2777 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2778 | (set_attr "type" "stm")]) |
9db1d521 HP |
2779 | |
2780 | ;; | |
2781 | ;; String instructions. | |
2782 | ;; | |
2783 | ||
963fc8d0 | 2784 | (define_insn "*execute_rl" |
2771c2f9 | 2785 | [(match_parallel 0 "execute_operation" |
963fc8d0 AK |
2786 | [(unspec [(match_operand 1 "register_operand" "a") |
2787 | (match_operand 2 "" "") | |
2788 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
2789 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2790 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2791 | "exrl\t%1,%3" | |
2792 | [(set_attr "op_type" "RIL") | |
2793 | (set_attr "type" "cs")]) | |
2794 | ||
9bb86f41 | 2795 | (define_insn "*execute" |
2771c2f9 | 2796 | [(match_parallel 0 "execute_operation" |
9bb86f41 UW |
2797 | [(unspec [(match_operand 1 "register_operand" "a") |
2798 | (match_operand:BLK 2 "memory_operand" "R") | |
2799 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
2800 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2801 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2802 | "ex\t%1,%2" | |
29a74354 UW |
2803 | [(set_attr "op_type" "RX") |
2804 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
2805 | |
2806 | ||
91d39d71 UW |
2807 | ; |
2808 | ; strlenM instruction pattern(s). | |
2809 | ; | |
2810 | ||
9db2f16d | 2811 | (define_expand "strlen<mode>" |
085261c8 AK |
2812 | [(match_operand:P 0 "register_operand" "") ; result |
2813 | (match_operand:BLK 1 "memory_operand" "") ; input string | |
2814 | (match_operand:SI 2 "immediate_operand" "") ; search character | |
2815 | (match_operand:SI 3 "immediate_operand" "")] ; known alignment | |
2816 | "" | |
2817 | { | |
2818 | if (!TARGET_VX || operands[2] != const0_rtx) | |
2819 | emit_insn (gen_strlen_srst<mode> (operands[0], operands[1], | |
2820 | operands[2], operands[3])); | |
2821 | else | |
2822 | s390_expand_vec_strlen (operands[0], operands[1], operands[3]); | |
2823 | ||
2824 | DONE; | |
2825 | }) | |
2826 | ||
2827 | (define_expand "strlen_srst<mode>" | |
ccbdc0d4 | 2828 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 2829 | (parallel |
91d39d71 | 2830 | [(set (match_dup 4) |
9db2f16d | 2831 | (unspec:P [(const_int 0) |
91d39d71 | 2832 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 2833 | (reg:SI 0) |
91d39d71 | 2834 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2835 | (clobber (scratch:P)) |
ae156f85 | 2836 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 2837 | (parallel |
9db2f16d AS |
2838 | [(set (match_operand:P 0 "register_operand" "") |
2839 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 2840 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 2841 | "" |
91d39d71 | 2842 | { |
9db2f16d AS |
2843 | operands[4] = gen_reg_rtx (Pmode); |
2844 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
2845 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2846 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
2847 | }) | |
2848 | ||
9db2f16d AS |
2849 | (define_insn "*strlen<mode>" |
2850 | [(set (match_operand:P 0 "register_operand" "=a") | |
2851 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
2852 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 2853 | (reg:SI 0) |
91d39d71 | 2854 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2855 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 2856 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 2857 | "" |
91d39d71 | 2858 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
2859 | [(set_attr "length" "8") |
2860 | (set_attr "type" "vs")]) | |
91d39d71 | 2861 | |
ccbdc0d4 AS |
2862 | ; |
2863 | ; cmpstrM instruction pattern(s). | |
2864 | ; | |
2865 | ||
2866 | (define_expand "cmpstrsi" | |
2867 | [(set (reg:SI 0) (const_int 0)) | |
2868 | (parallel | |
2869 | [(clobber (match_operand 3 "" "")) | |
2870 | (clobber (match_dup 4)) | |
2871 | (set (reg:CCU CC_REGNUM) | |
2872 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
2873 | (match_operand:BLK 2 "memory_operand" ""))) | |
2874 | (use (reg:SI 0))]) | |
2875 | (parallel | |
2876 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 2877 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT)) |
ccbdc0d4 AS |
2878 | (clobber (reg:CC CC_REGNUM))])] |
2879 | "" | |
2880 | { | |
2881 | /* As the result of CMPINT is inverted compared to what we need, | |
2882 | we have to swap the operands. */ | |
2883 | rtx op1 = operands[2]; | |
2884 | rtx op2 = operands[1]; | |
2885 | rtx addr1 = gen_reg_rtx (Pmode); | |
2886 | rtx addr2 = gen_reg_rtx (Pmode); | |
2887 | ||
2888 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
2889 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
2890 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
2891 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
2892 | operands[3] = addr1; | |
2893 | operands[4] = addr2; | |
2894 | }) | |
2895 | ||
2896 | (define_insn "*cmpstr<mode>" | |
2897 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
2898 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
2899 | (set (reg:CCU CC_REGNUM) | |
2900 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
2901 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
2902 | (use (reg:SI 0))] | |
2903 | "" | |
2904 | "clst\t%0,%1\;jo\t.-4" | |
2905 | [(set_attr "length" "8") | |
2906 | (set_attr "type" "vs")]) | |
9381e3f1 | 2907 | |
742090fc AS |
2908 | ; |
2909 | ; movstr instruction pattern. | |
2910 | ; | |
2911 | ||
2912 | (define_expand "movstr" | |
2913 | [(set (reg:SI 0) (const_int 0)) | |
9381e3f1 | 2914 | (parallel |
742090fc AS |
2915 | [(clobber (match_dup 3)) |
2916 | (set (match_operand:BLK 1 "memory_operand" "") | |
2917 | (match_operand:BLK 2 "memory_operand" "")) | |
2918 | (set (match_operand 0 "register_operand" "") | |
9381e3f1 | 2919 | (unspec [(match_dup 1) |
742090fc AS |
2920 | (match_dup 2) |
2921 | (reg:SI 0)] UNSPEC_MVST)) | |
2922 | (clobber (reg:CC CC_REGNUM))])] | |
2923 | "" | |
2924 | { | |
2925 | rtx addr1 = gen_reg_rtx (Pmode); | |
2926 | rtx addr2 = gen_reg_rtx (Pmode); | |
2927 | ||
2928 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2929 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
2930 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2931 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
2932 | operands[3] = addr2; | |
2933 | }) | |
2934 | ||
2935 | (define_insn "*movstr" | |
2936 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
2937 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
2938 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
2939 | (set (match_operand:P 0 "register_operand" "=d") | |
9381e3f1 | 2940 | (unspec [(mem:BLK (match_dup 1)) |
742090fc AS |
2941 | (mem:BLK (match_dup 3)) |
2942 | (reg:SI 0)] UNSPEC_MVST)) | |
2943 | (clobber (reg:CC CC_REGNUM))] | |
2944 | "" | |
2945 | "mvst\t%1,%2\;jo\t.-4" | |
2946 | [(set_attr "length" "8") | |
2947 | (set_attr "type" "vs")]) | |
9381e3f1 | 2948 | |
742090fc | 2949 | |
9db1d521 | 2950 | ; |
70128ad9 | 2951 | ; movmemM instruction pattern(s). |
9db1d521 HP |
2952 | ; |
2953 | ||
9db2f16d | 2954 | (define_expand "movmem<mode>" |
963fc8d0 AK |
2955 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
2956 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
2957 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
2958 | (match_operand 3 "" "")] |
2959 | "" | |
367d32f3 AK |
2960 | { |
2961 | if (s390_expand_movmem (operands[0], operands[1], operands[2])) | |
2962 | DONE; | |
2963 | else | |
2964 | FAIL; | |
2965 | }) | |
9db1d521 | 2966 | |
ecbe845e UW |
2967 | ; Move a block that is up to 256 bytes in length. |
2968 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2969 | |
70128ad9 | 2970 | (define_expand "movmem_short" |
b9404c99 UW |
2971 | [(parallel |
2972 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2973 | (match_operand:BLK 1 "memory_operand" "")) | |
2974 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2975 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2976 | (clobber (match_dup 3))])] |
2977 | "" | |
2978 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 2979 | |
70128ad9 | 2980 | (define_insn "*movmem_short" |
963fc8d0 AK |
2981 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
2982 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
2983 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
2984 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
2985 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
2986 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 2987 | "#" |
963fc8d0 | 2988 | [(set_attr "type" "cs") |
b5e0425c | 2989 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
ecbe845e | 2990 | |
9bb86f41 UW |
2991 | (define_split |
2992 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2993 | (match_operand:BLK 1 "memory_operand" "")) | |
2994 | (use (match_operand 2 "const_int_operand" "")) | |
2995 | (use (match_operand 3 "immediate_operand" "")) | |
2996 | (clobber (scratch))] | |
2997 | "reload_completed" | |
2998 | [(parallel | |
2999 | [(set (match_dup 0) (match_dup 1)) | |
3000 | (use (match_dup 2))])] | |
3001 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3002 | |
9bb86f41 UW |
3003 | (define_split |
3004 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3005 | (match_operand:BLK 1 "memory_operand" "")) | |
3006 | (use (match_operand 2 "register_operand" "")) | |
3007 | (use (match_operand 3 "memory_operand" "")) | |
3008 | (clobber (scratch))] | |
3009 | "reload_completed" | |
3010 | [(parallel | |
3011 | [(unspec [(match_dup 2) (match_dup 3) | |
3012 | (const_int 0)] UNSPEC_EXECUTE) | |
3013 | (set (match_dup 0) (match_dup 1)) | |
3014 | (use (const_int 1))])] | |
3015 | "") | |
3016 | ||
963fc8d0 AK |
3017 | (define_split |
3018 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3019 | (match_operand:BLK 1 "memory_operand" "")) | |
3020 | (use (match_operand 2 "register_operand" "")) | |
3021 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3022 | (clobber (scratch))] | |
3023 | "TARGET_Z10 && reload_completed" | |
3024 | [(parallel | |
3025 | [(unspec [(match_dup 2) (const_int 0) | |
3026 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3027 | (set (match_dup 0) (match_dup 1)) | |
3028 | (use (const_int 1))])] | |
3029 | "operands[3] = gen_label_rtx ();") | |
3030 | ||
9bb86f41 UW |
3031 | (define_split |
3032 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3033 | (match_operand:BLK 1 "memory_operand" "")) | |
3034 | (use (match_operand 2 "register_operand" "")) | |
3035 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3036 | (clobber (match_operand 3 "register_operand" ""))] | |
3037 | "reload_completed && TARGET_CPU_ZARCH" | |
3038 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3039 | (parallel | |
9381e3f1 | 3040 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
3041 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
3042 | (set (match_dup 0) (match_dup 1)) | |
3043 | (use (const_int 1))])] | |
3044 | "operands[4] = gen_label_rtx ();") | |
3045 | ||
a41c6c53 | 3046 | ; Move a block of arbitrary length. |
9db1d521 | 3047 | |
70128ad9 | 3048 | (define_expand "movmem_long" |
b9404c99 UW |
3049 | [(parallel |
3050 | [(clobber (match_dup 2)) | |
3051 | (clobber (match_dup 3)) | |
3052 | (set (match_operand:BLK 0 "memory_operand" "") | |
3053 | (match_operand:BLK 1 "memory_operand" "")) | |
3054 | (use (match_operand 2 "general_operand" "")) | |
3055 | (use (match_dup 3)) | |
ae156f85 | 3056 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3057 | "" |
3058 | { | |
ef4bddc2 RS |
3059 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3060 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3061 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3062 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3063 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3064 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3065 | rtx len0 = gen_lowpart (Pmode, reg0); |
3066 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3067 | ||
c41c1387 | 3068 | emit_clobber (reg0); |
b9404c99 UW |
3069 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3070 | emit_move_insn (len0, operands[2]); | |
3071 | ||
c41c1387 | 3072 | emit_clobber (reg1); |
b9404c99 UW |
3073 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3074 | emit_move_insn (len1, operands[2]); | |
3075 | ||
3076 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3077 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3078 | operands[2] = reg0; | |
3079 | operands[3] = reg1; | |
3080 | }) | |
3081 | ||
a1aed706 AS |
3082 | (define_insn "*movmem_long" |
3083 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3084 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
3085 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
3086 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
3087 | (use (match_dup 2)) |
3088 | (use (match_dup 3)) | |
ae156f85 | 3089 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 AK |
3090 | "TARGET_64BIT || !TARGET_ZARCH" |
3091 | "mvcle\t%0,%1,0\;jo\t.-4" | |
3092 | [(set_attr "length" "8") | |
3093 | (set_attr "type" "vs")]) | |
3094 | ||
3095 | (define_insn "*movmem_long_31z" | |
3096 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3097 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3098 | (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3099 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) | |
3100 | (use (match_dup 2)) | |
3101 | (use (match_dup 3)) | |
3102 | (clobber (reg:CC CC_REGNUM))] | |
3103 | "!TARGET_64BIT && TARGET_ZARCH" | |
d40c829f | 3104 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3105 | [(set_attr "length" "8") |
3106 | (set_attr "type" "vs")]) | |
9db1d521 | 3107 | |
638e37c2 WG |
3108 | |
3109 | ; | |
3110 | ; Test data class. | |
3111 | ; | |
3112 | ||
0f67fa83 WG |
3113 | (define_expand "signbit<mode>2" |
3114 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3115 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3116 | (match_dup 2)] | |
0f67fa83 WG |
3117 | UNSPEC_TDC_INSN)) |
3118 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3119 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
0f67fa83 WG |
3120 | "TARGET_HARD_FLOAT" |
3121 | { | |
3122 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
3123 | }) | |
3124 | ||
638e37c2 WG |
3125 | (define_expand "isinf<mode>2" |
3126 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3127 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3128 | (match_dup 2)] | |
638e37c2 WG |
3129 | UNSPEC_TDC_INSN)) |
3130 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3131 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
142cd70f | 3132 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
3133 | { |
3134 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
3135 | }) | |
3136 | ||
085261c8 AK |
3137 | ; This extracts CC into a GPR properly shifted. The actual IPM |
3138 | ; instruction will be issued by reload. The constraint of operand 1 | |
3139 | ; forces reload to use a GPR. So reload will issue a movcc insn for | |
3140 | ; copying CC into a GPR first. | |
5a3fe9b6 | 3141 | (define_insn_and_split "*cc_to_int" |
085261c8 | 3142 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
5a3fe9b6 AK |
3143 | (unspec:SI [(match_operand 1 "register_operand" "0")] |
3144 | UNSPEC_CC_TO_INT))] | |
3145 | "operands != NULL" | |
3146 | "#" | |
3147 | "reload_completed" | |
3148 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
3149 | ||
638e37c2 WG |
3150 | ; This insn is used to generate all variants of the Test Data Class |
3151 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
3152 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 3153 | ; specifying the required test(s). |
638e37c2 | 3154 | ; |
be5de7a1 | 3155 | ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet |
638e37c2 WG |
3156 | (define_insn "*TDC_insn_<mode>" |
3157 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 3158 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 3159 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 3160 | "TARGET_HARD_FLOAT" |
0387c142 | 3161 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 3162 | [(set_attr "op_type" "RXE") |
9381e3f1 | 3163 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 | 3164 | |
638e37c2 WG |
3165 | |
3166 | ||
9db1d521 | 3167 | ; |
57e84f18 | 3168 | ; setmemM instruction pattern(s). |
9db1d521 HP |
3169 | ; |
3170 | ||
57e84f18 | 3171 | (define_expand "setmem<mode>" |
a41c6c53 | 3172 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 3173 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 3174 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 3175 | (match_operand 3 "" "")] |
a41c6c53 | 3176 | "" |
6d057022 | 3177 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 3178 | |
a41c6c53 | 3179 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
3180 | ; The block length is taken as (operands[1] % 256) + 1. |
3181 | ||
70128ad9 | 3182 | (define_expand "clrmem_short" |
b9404c99 UW |
3183 | [(parallel |
3184 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3185 | (const_int 0)) | |
3186 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 3187 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 3188 | (clobber (match_dup 2)) |
ae156f85 | 3189 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3190 | "" |
3191 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3192 | |
70128ad9 | 3193 | (define_insn "*clrmem_short" |
963fc8d0 | 3194 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 3195 | (const_int 0)) |
963fc8d0 AK |
3196 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
3197 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
1eae36f0 | 3198 | (clobber (match_scratch:P 3 "=X,X,X,&a")) |
ae156f85 | 3199 | (clobber (reg:CC CC_REGNUM))] |
1eae36f0 | 3200 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" |
9bb86f41 | 3201 | "#" |
963fc8d0 | 3202 | [(set_attr "type" "cs") |
b5e0425c | 3203 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9bb86f41 UW |
3204 | |
3205 | (define_split | |
3206 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3207 | (const_int 0)) | |
3208 | (use (match_operand 1 "const_int_operand" "")) | |
3209 | (use (match_operand 2 "immediate_operand" "")) | |
3210 | (clobber (scratch)) | |
ae156f85 | 3211 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3212 | "reload_completed" |
3213 | [(parallel | |
3214 | [(set (match_dup 0) (const_int 0)) | |
3215 | (use (match_dup 1)) | |
ae156f85 | 3216 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3217 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 3218 | |
9bb86f41 UW |
3219 | (define_split |
3220 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3221 | (const_int 0)) | |
3222 | (use (match_operand 1 "register_operand" "")) | |
3223 | (use (match_operand 2 "memory_operand" "")) | |
3224 | (clobber (scratch)) | |
ae156f85 | 3225 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3226 | "reload_completed" |
3227 | [(parallel | |
3228 | [(unspec [(match_dup 1) (match_dup 2) | |
3229 | (const_int 0)] UNSPEC_EXECUTE) | |
3230 | (set (match_dup 0) (const_int 0)) | |
3231 | (use (const_int 1)) | |
ae156f85 | 3232 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3233 | "") |
9db1d521 | 3234 | |
963fc8d0 AK |
3235 | (define_split |
3236 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3237 | (const_int 0)) | |
3238 | (use (match_operand 1 "register_operand" "")) | |
3239 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3240 | (clobber (scratch)) | |
3241 | (clobber (reg:CC CC_REGNUM))] | |
3242 | "TARGET_Z10 && reload_completed" | |
3243 | [(parallel | |
3244 | [(unspec [(match_dup 1) (const_int 0) | |
3245 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3246 | (set (match_dup 0) (const_int 0)) | |
3247 | (use (const_int 1)) | |
3248 | (clobber (reg:CC CC_REGNUM))])] | |
3249 | "operands[3] = gen_label_rtx ();") | |
3250 | ||
9bb86f41 UW |
3251 | (define_split |
3252 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3253 | (const_int 0)) | |
3254 | (use (match_operand 1 "register_operand" "")) | |
3255 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3256 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 3257 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3258 | "reload_completed && TARGET_CPU_ZARCH" |
3259 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
3260 | (parallel | |
9381e3f1 | 3261 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
3262 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
3263 | (set (match_dup 0) (const_int 0)) | |
3264 | (use (const_int 1)) | |
ae156f85 | 3265 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
3266 | "operands[3] = gen_label_rtx ();") |
3267 | ||
9381e3f1 | 3268 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 3269 | |
6d057022 | 3270 | (define_expand "setmem_long" |
b9404c99 UW |
3271 | [(parallel |
3272 | [(clobber (match_dup 1)) | |
3273 | (set (match_operand:BLK 0 "memory_operand" "") | |
4989e88a | 3274 | (match_operand 2 "shift_count_or_setmem_operand" "")) |
b9404c99 | 3275 | (use (match_operand 1 "general_operand" "")) |
6d057022 | 3276 | (use (match_dup 3)) |
ae156f85 | 3277 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 3278 | "" |
a41c6c53 | 3279 | { |
ef4bddc2 RS |
3280 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3281 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3282 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3283 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3284 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
b9404c99 | 3285 | rtx len0 = gen_lowpart (Pmode, reg0); |
9db1d521 | 3286 | |
c41c1387 | 3287 | emit_clobber (reg0); |
b9404c99 UW |
3288 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3289 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 3290 | |
b9404c99 | 3291 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 3292 | |
b9404c99 UW |
3293 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
3294 | operands[1] = reg0; | |
6d057022 | 3295 | operands[3] = reg1; |
b9404c99 | 3296 | }) |
a41c6c53 | 3297 | |
6d057022 | 3298 | (define_insn "*setmem_long" |
a1aed706 | 3299 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 3300 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
4989e88a | 3301 | (match_operand 2 "shift_count_or_setmem_operand" "Y")) |
6d057022 | 3302 | (use (match_dup 3)) |
a1aed706 | 3303 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 3304 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3305 | "TARGET_64BIT || !TARGET_ZARCH" |
6d057022 | 3306 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
3307 | [(set_attr "length" "8") |
3308 | (set_attr "type" "vs")]) | |
9db1d521 | 3309 | |
4989e88a AK |
3310 | (define_insn "*setmem_long_and" |
3311 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3312 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
3313 | (and (match_operand 2 "shift_count_or_setmem_operand" "Y") | |
3314 | (match_operand 4 "const_int_operand" "n"))) | |
3315 | (use (match_dup 3)) | |
3316 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
3317 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 AK |
3318 | "(TARGET_64BIT || !TARGET_ZARCH) && |
3319 | (INTVAL (operands[4]) & 255) == 255" | |
3320 | "mvcle\t%0,%1,%Y2\;jo\t.-4" | |
3321 | [(set_attr "length" "8") | |
3322 | (set_attr "type" "vs")]) | |
3323 | ||
3324 | (define_insn "*setmem_long_31z" | |
3325 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3326 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
3327 | (match_operand 2 "shift_count_or_setmem_operand" "Y")) | |
3328 | (use (match_dup 3)) | |
3329 | (use (match_operand:TI 1 "register_operand" "d")) | |
3330 | (clobber (reg:CC CC_REGNUM))] | |
3331 | "!TARGET_64BIT && TARGET_ZARCH" | |
4989e88a AK |
3332 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3333 | [(set_attr "length" "8") | |
3334 | (set_attr "type" "vs")]) | |
9602b6a1 | 3335 | |
9db1d521 | 3336 | ; |
358b8f01 | 3337 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
3338 | ; |
3339 | ||
358b8f01 | 3340 | (define_expand "cmpmemsi" |
a41c6c53 UW |
3341 | [(set (match_operand:SI 0 "register_operand" "") |
3342 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
3343 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
3344 | (use (match_operand:SI 3 "general_operand" "")) | |
3345 | (use (match_operand:SI 4 "" ""))] | |
3346 | "" | |
367d32f3 AK |
3347 | { |
3348 | if (s390_expand_cmpmem (operands[0], operands[1], | |
3349 | operands[2], operands[3])) | |
3350 | DONE; | |
3351 | else | |
3352 | FAIL; | |
3353 | }) | |
9db1d521 | 3354 | |
a41c6c53 UW |
3355 | ; Compare a block that is up to 256 bytes in length. |
3356 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3357 | |
b9404c99 UW |
3358 | (define_expand "cmpmem_short" |
3359 | [(parallel | |
ae156f85 | 3360 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 3361 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3362 | (match_operand:BLK 1 "memory_operand" ""))) |
3363 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3364 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3365 | (clobber (match_dup 3))])] |
3366 | "" | |
3367 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3368 | |
b9404c99 | 3369 | (define_insn "*cmpmem_short" |
ae156f85 | 3370 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
3371 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
3372 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
3373 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3374 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3375 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3376 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3377 | "#" |
963fc8d0 | 3378 | [(set_attr "type" "cs") |
b5e0425c | 3379 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9db1d521 | 3380 | |
9bb86f41 | 3381 | (define_split |
ae156f85 | 3382 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3383 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3384 | (match_operand:BLK 1 "memory_operand" ""))) | |
3385 | (use (match_operand 2 "const_int_operand" "")) | |
3386 | (use (match_operand 3 "immediate_operand" "")) | |
3387 | (clobber (scratch))] | |
3388 | "reload_completed" | |
3389 | [(parallel | |
ae156f85 | 3390 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3391 | (use (match_dup 2))])] |
3392 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3393 | |
9bb86f41 | 3394 | (define_split |
ae156f85 | 3395 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3396 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3397 | (match_operand:BLK 1 "memory_operand" ""))) | |
3398 | (use (match_operand 2 "register_operand" "")) | |
3399 | (use (match_operand 3 "memory_operand" "")) | |
3400 | (clobber (scratch))] | |
3401 | "reload_completed" | |
3402 | [(parallel | |
3403 | [(unspec [(match_dup 2) (match_dup 3) | |
3404 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 3405 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3406 | (use (const_int 1))])] |
3407 | "") | |
3408 | ||
963fc8d0 AK |
3409 | (define_split |
3410 | [(set (reg:CCU CC_REGNUM) | |
3411 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3412 | (match_operand:BLK 1 "memory_operand" ""))) | |
3413 | (use (match_operand 2 "register_operand" "")) | |
3414 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3415 | (clobber (scratch))] | |
3416 | "TARGET_Z10 && reload_completed" | |
3417 | [(parallel | |
3418 | [(unspec [(match_dup 2) (const_int 0) | |
3419 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
3420 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
3421 | (use (const_int 1))])] | |
3422 | "operands[4] = gen_label_rtx ();") | |
3423 | ||
9bb86f41 | 3424 | (define_split |
ae156f85 | 3425 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3426 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3427 | (match_operand:BLK 1 "memory_operand" ""))) | |
3428 | (use (match_operand 2 "register_operand" "")) | |
3429 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3430 | (clobber (match_operand 3 "register_operand" ""))] | |
3431 | "reload_completed && TARGET_CPU_ZARCH" | |
3432 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3433 | (parallel | |
9381e3f1 | 3434 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 3435 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 3436 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3437 | (use (const_int 1))])] |
3438 | "operands[4] = gen_label_rtx ();") | |
3439 | ||
a41c6c53 | 3440 | ; Compare a block of arbitrary length. |
9db1d521 | 3441 | |
b9404c99 UW |
3442 | (define_expand "cmpmem_long" |
3443 | [(parallel | |
3444 | [(clobber (match_dup 2)) | |
3445 | (clobber (match_dup 3)) | |
ae156f85 | 3446 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 3447 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3448 | (match_operand:BLK 1 "memory_operand" ""))) |
3449 | (use (match_operand 2 "general_operand" "")) | |
3450 | (use (match_dup 3))])] | |
3451 | "" | |
3452 | { | |
ef4bddc2 RS |
3453 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3454 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3455 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3456 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3457 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3458 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3459 | rtx len0 = gen_lowpart (Pmode, reg0); |
3460 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3461 | ||
c41c1387 | 3462 | emit_clobber (reg0); |
b9404c99 UW |
3463 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3464 | emit_move_insn (len0, operands[2]); | |
3465 | ||
c41c1387 | 3466 | emit_clobber (reg1); |
b9404c99 UW |
3467 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3468 | emit_move_insn (len1, operands[2]); | |
3469 | ||
3470 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3471 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3472 | operands[2] = reg0; | |
3473 | operands[3] = reg1; | |
3474 | }) | |
3475 | ||
a1aed706 AS |
3476 | (define_insn "*cmpmem_long" |
3477 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3478 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3479 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3480 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3481 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3482 | (use (match_dup 2)) |
3483 | (use (match_dup 3))] | |
9602b6a1 | 3484 | "TARGET_64BIT || !TARGET_ZARCH" |
287ff198 | 3485 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3486 | [(set_attr "length" "8") |
3487 | (set_attr "type" "vs")]) | |
9db1d521 | 3488 | |
9602b6a1 AK |
3489 | (define_insn "*cmpmem_long_31z" |
3490 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3491 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3492 | (set (reg:CCU CC_REGNUM) | |
3493 | (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3494 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) | |
3495 | (use (match_dup 2)) | |
3496 | (use (match_dup 3))] | |
3497 | "!TARGET_64BIT && TARGET_ZARCH" | |
3498 | "clcle\t%0,%1,0\;jo\t.-4" | |
3499 | [(set_attr "op_type" "NN") | |
3500 | (set_attr "type" "vs") | |
3501 | (set_attr "length" "8")]) | |
3502 | ||
02887425 UW |
3503 | ; Convert CCUmode condition code to integer. |
3504 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3505 | |
02887425 | 3506 | (define_insn_and_split "cmpint" |
9db1d521 | 3507 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3508 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3509 | UNSPEC_STRCMPCC_TO_INT)) |
ae156f85 | 3510 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3511 | "" |
02887425 UW |
3512 | "#" |
3513 | "reload_completed" | |
3514 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3515 | (parallel | |
3516 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3517 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3518 | |
3519 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3520 | [(set (reg CC_REGNUM) |
02887425 | 3521 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3522 | UNSPEC_STRCMPCC_TO_INT) |
02887425 UW |
3523 | (const_int 0))) |
3524 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3525 | (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))] |
02887425 UW |
3526 | "s390_match_ccmode (insn, CCSmode)" |
3527 | "#" | |
3528 | "&& reload_completed" | |
3529 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3530 | (parallel | |
3531 | [(set (match_dup 2) (match_dup 3)) | |
3532 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3533 | { |
02887425 UW |
3534 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3535 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3536 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3537 | }) | |
9db1d521 | 3538 | |
02887425 | 3539 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3540 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3541 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3542 | UNSPEC_STRCMPCC_TO_INT))) |
ae156f85 | 3543 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3544 | "TARGET_ZARCH" |
02887425 UW |
3545 | "#" |
3546 | "&& reload_completed" | |
3547 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3548 | (parallel | |
3549 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3550 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3551 | |
3552 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3553 | [(set (reg CC_REGNUM) |
9381e3f1 | 3554 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3555 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3556 | UNSPEC_STRCMPCC_TO_INT) 0) |
02887425 UW |
3557 | (const_int 32)) (const_int 32)) |
3558 | (const_int 0))) | |
3559 | (set (match_operand:DI 0 "register_operand" "=d") | |
5a3fe9b6 | 3560 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))] |
9602b6a1 | 3561 | "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" |
02887425 UW |
3562 | "#" |
3563 | "&& reload_completed" | |
3564 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3565 | (parallel | |
3566 | [(set (match_dup 2) (match_dup 3)) | |
3567 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3568 | { |
02887425 UW |
3569 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3570 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3571 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3572 | }) | |
9db1d521 | 3573 | |
4023fb28 | 3574 | |
9db1d521 HP |
3575 | ;; |
3576 | ;;- Conversion instructions. | |
3577 | ;; | |
3578 | ||
6fa05db6 | 3579 | (define_insn "*sethighpartsi" |
d3632d41 | 3580 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3581 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3582 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3583 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3584 | "" |
d3632d41 | 3585 | "@ |
6fa05db6 AS |
3586 | icm\t%0,%2,%S1 |
3587 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3588 | [(set_attr "op_type" "RS,RSY") |
3589 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4023fb28 | 3590 | |
6fa05db6 | 3591 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3592 | [(set (match_operand:DI 0 "register_operand" "=d") |
6fa05db6 AS |
3593 | (unspec:DI [(match_operand:BLK 1 "s_operand" "QS") |
3594 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) | |
ae156f85 | 3595 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3596 | "TARGET_ZARCH" |
6fa05db6 | 3597 | "icmh\t%0,%2,%S1" |
729e750f WG |
3598 | [(set_attr "op_type" "RSY") |
3599 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3600 | |
6fa05db6 | 3601 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3602 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3603 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3604 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3605 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3606 | "!TARGET_ZARCH" |
d3632d41 | 3607 | "@ |
6fa05db6 AS |
3608 | icm\t%0,%2,%S1 |
3609 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3610 | [(set_attr "op_type" "RS,RSY") |
3611 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
3612 | ||
1a2e356e RH |
3613 | ; |
3614 | ; extv instruction patterns | |
3615 | ; | |
3616 | ||
3617 | ; FIXME: This expander needs to be converted from DI to GPR as well | |
3618 | ; after resolving some issues with it. | |
3619 | ||
3620 | (define_expand "extzv" | |
3621 | [(parallel | |
3622 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3623 | (zero_extract:DI | |
3624 | (match_operand:DI 1 "register_operand" "d") | |
3625 | (match_operand 2 "const_int_operand" "") ; size | |
3626 | (match_operand 3 "const_int_operand" ""))) ; start | |
3627 | (clobber (reg:CC CC_REGNUM))])] | |
3628 | "TARGET_Z10" | |
3629 | { | |
3630 | /* Starting with zEC12 there is risbgn not clobbering CC. */ | |
3631 | if (TARGET_ZEC12) | |
3632 | { | |
3633 | emit_move_insn (operands[0], | |
3634 | gen_rtx_ZERO_EXTRACT (DImode, | |
3635 | operands[1], | |
3636 | operands[2], | |
3637 | operands[3])); | |
3638 | DONE; | |
3639 | } | |
3640 | }) | |
3641 | ||
3642 | (define_insn "*extzv<mode>_zEC12" | |
3643 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3644 | (zero_extract:GPR | |
3645 | (match_operand:GPR 1 "register_operand" "d") | |
3646 | (match_operand 2 "const_int_operand" "") ; size | |
3647 | (match_operand 3 "const_int_operand" "")))] ; start] | |
3648 | "TARGET_ZEC12" | |
3649 | "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift | |
3650 | [(set_attr "op_type" "RIE")]) | |
3651 | ||
3652 | (define_insn "*extzv<mode>_z10" | |
3653 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3654 | (zero_extract:GPR | |
3655 | (match_operand:GPR 1 "register_operand" "d") | |
3656 | (match_operand 2 "const_int_operand" "") ; size | |
3657 | (match_operand 3 "const_int_operand" ""))) ; start | |
3658 | (clobber (reg:CC CC_REGNUM))] | |
3659 | "TARGET_Z10" | |
3660 | "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift | |
3661 | [(set_attr "op_type" "RIE") | |
3662 | (set_attr "z10prop" "z10_super_E1")]) | |
4023fb28 | 3663 | |
1a2e356e | 3664 | (define_insn_and_split "*pre_z10_extzv<mode>" |
6fa05db6 AS |
3665 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3666 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
1a2e356e | 3667 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3668 | (const_int 0))) |
ae156f85 | 3669 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3670 | "!TARGET_Z10" |
cc7ab9b7 UW |
3671 | "#" |
3672 | "&& reload_completed" | |
4023fb28 | 3673 | [(parallel |
6fa05db6 | 3674 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3675 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 3676 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 3677 | { |
6fa05db6 AS |
3678 | int bitsize = INTVAL (operands[2]); |
3679 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3680 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3681 | ||
3682 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3683 | set_mem_size (operands[1], size); |
2542ef05 | 3684 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 | 3685 | operands[3] = GEN_INT (mask); |
b628bd8e | 3686 | }) |
4023fb28 | 3687 | |
1a2e356e | 3688 | (define_insn_and_split "*pre_z10_extv<mode>" |
6fa05db6 AS |
3689 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3690 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
1a2e356e | 3691 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3692 | (const_int 0))) |
ae156f85 | 3693 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3694 | "" |
cc7ab9b7 UW |
3695 | "#" |
3696 | "&& reload_completed" | |
4023fb28 | 3697 | [(parallel |
6fa05db6 | 3698 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3699 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
3700 | (parallel |
3701 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
3702 | (clobber (reg:CC CC_REGNUM))])] | |
3703 | { | |
3704 | int bitsize = INTVAL (operands[2]); | |
3705 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3706 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3707 | ||
3708 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3709 | set_mem_size (operands[1], size); |
2542ef05 | 3710 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 AS |
3711 | operands[3] = GEN_INT (mask); |
3712 | }) | |
3713 | ||
3714 | ; | |
3715 | ; insv instruction patterns | |
3716 | ; | |
3717 | ||
3718 | (define_expand "insv" | |
3719 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
3720 | (match_operand 1 "const_int_operand" "") | |
3721 | (match_operand 2 "const_int_operand" "")) | |
3722 | (match_operand 3 "general_operand" ""))] | |
3723 | "" | |
4023fb28 | 3724 | { |
6fa05db6 AS |
3725 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
3726 | DONE; | |
3727 | FAIL; | |
b628bd8e | 3728 | }) |
4023fb28 | 3729 | |
2542ef05 RH |
3730 | |
3731 | ; The normal RTL expansion will never generate a zero_extract where | |
3732 | ; the location operand isn't word mode. However, we do this in the | |
3733 | ; back-end when generating atomic operations. See s390_two_part_insv. | |
22ac2c2f AK |
3734 | (define_insn "*insv<mode>_zEC12" |
3735 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") | |
2542ef05 RH |
3736 | (match_operand 1 "const_int_operand" "I") ; size |
3737 | (match_operand 2 "const_int_operand" "I")) ; pos | |
22ac2c2f AK |
3738 | (match_operand:GPR 3 "nonimmediate_operand" "d"))] |
3739 | "TARGET_ZEC12 | |
2542ef05 RH |
3740 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
3741 | "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1" | |
22ac2c2f AK |
3742 | [(set_attr "op_type" "RIE")]) |
3743 | ||
963fc8d0 AK |
3744 | (define_insn "*insv<mode>_z10" |
3745 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") | |
2542ef05 RH |
3746 | (match_operand 1 "const_int_operand" "I") ; size |
3747 | (match_operand 2 "const_int_operand" "I")) ; pos | |
963fc8d0 AK |
3748 | (match_operand:GPR 3 "nonimmediate_operand" "d")) |
3749 | (clobber (reg:CC CC_REGNUM))] | |
3750 | "TARGET_Z10 | |
2542ef05 RH |
3751 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
3752 | "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1" | |
9381e3f1 WG |
3753 | [(set_attr "op_type" "RIE") |
3754 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 3755 | |
22ac2c2f AK |
3756 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest |
3757 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
3758 | (define_insn "*insv<mode>_zEC12_noshift" | |
3759 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3760 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
75ca1b39 | 3761 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
22ac2c2f | 3762 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") |
75ca1b39 RH |
3763 | (match_operand:GPR 4 "const_int_operand" ""))))] |
3764 | "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
3765 | "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0" | |
22ac2c2f AK |
3766 | [(set_attr "op_type" "RIE")]) |
3767 | ||
963fc8d0 AK |
3768 | (define_insn "*insv<mode>_z10_noshift" |
3769 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3770 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
75ca1b39 | 3771 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
963fc8d0 | 3772 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") |
75ca1b39 | 3773 | (match_operand:GPR 4 "const_int_operand" "")))) |
963fc8d0 | 3774 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 RH |
3775 | "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])" |
3776 | "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0" | |
9381e3f1 WG |
3777 | [(set_attr "op_type" "RIE") |
3778 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 3779 | |
3d44ff99 AK |
3780 | ; Implement appending Y on the left of S bits of X |
3781 | ; x = (y << s) | (x & ((1 << s) - 1)) | |
3782 | (define_insn "*insv<mode>_zEC12_appendbitsleft" | |
3783 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3784 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") | |
3785 | (match_operand:GPR 2 "immediate_operand" "")) | |
3786 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") | |
3787 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
3788 | "TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1" | |
3789 | "risbgn\t%0,%3,64-<bitsize>,64-%4-1,%4" | |
3790 | [(set_attr "op_type" "RIE") | |
3791 | (set_attr "z10prop" "z10_super_E1")]) | |
3792 | ||
3793 | (define_insn "*insv<mode>_z10_appendbitsleft" | |
3794 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3795 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") | |
3796 | (match_operand:GPR 2 "immediate_operand" "")) | |
3797 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") | |
3798 | (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) | |
3799 | (clobber (reg:CC CC_REGNUM))] | |
3800 | "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1" | |
3801 | "risbg\t%0,%3,64-<bitsize>,64-%4-1,%4" | |
3802 | [(set_attr "op_type" "RIE") | |
3803 | (set_attr "z10prop" "z10_super_E1")]) | |
3804 | ||
3805 | ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting | |
3806 | ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1)) | |
3807 | ; -> z = y >> d; z = risbg; | |
3808 | ||
3809 | (define_split | |
3810 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
3811 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
3812 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
3813 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
3814 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
3815 | "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
3816 | [(set (match_dup 0) | |
3817 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) | |
3818 | (set (match_dup 0) | |
3819 | (ior:GPR (and:GPR (match_dup 0) (match_dup 5)) | |
3820 | (ashift:GPR (match_dup 3) (match_dup 4))))] | |
3821 | { | |
3822 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
3823 | }) | |
3824 | ||
3825 | (define_split | |
3826 | [(parallel | |
3827 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
3828 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
3829 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
3830 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
3831 | (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) | |
3832 | (clobber (reg:CC CC_REGNUM))])] | |
3833 | "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
3834 | [(set (match_dup 0) | |
3835 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) | |
3836 | (parallel | |
3837 | [(set (match_dup 0) | |
3838 | (ior:GPR (and:GPR (match_dup 0) (match_dup 5)) | |
3839 | (ashift:GPR (match_dup 3) (match_dup 4)))) | |
3840 | (clobber (reg:CC CC_REGNUM))])] | |
3841 | { | |
3842 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
3843 | }) | |
3844 | ||
571e408a | 3845 | (define_insn "*r<noxa>sbg_<mode>_noshift" |
963fc8d0 | 3846 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
571e408a RH |
3847 | (IXOR:GPR |
3848 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3849 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
3850 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
963fc8d0 | 3851 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 | 3852 | "TARGET_Z10" |
571e408a RH |
3853 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0" |
3854 | [(set_attr "op_type" "RIE")]) | |
3855 | ||
3856 | (define_insn "*r<noxa>sbg_di_rotl" | |
3857 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") | |
3858 | (IXOR:DI | |
3859 | (and:DI | |
3860 | (rotate:DI | |
3861 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
3862 | (match_operand:DI 3 "const_int_operand" "")) | |
3863 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
3864 | (match_operand:DI 4 "nonimmediate_operand" "0"))) | |
3865 | (clobber (reg:CC CC_REGNUM))] | |
3866 | "TARGET_Z10" | |
3867 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3" | |
3868 | [(set_attr "op_type" "RIE")]) | |
3869 | ||
3870 | (define_insn "*r<noxa>sbg_<mode>_srl" | |
3871 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3872 | (IXOR:GPR | |
3873 | (and:GPR | |
3874 | (lshiftrt:GPR | |
3875 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3876 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
3877 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
3878 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) | |
3879 | (clobber (reg:CC CC_REGNUM))] | |
3880 | "TARGET_Z10 | |
3881 | && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), | |
3882 | INTVAL (operands[2]))" | |
3883 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3" | |
3884 | [(set_attr "op_type" "RIE")]) | |
3885 | ||
3886 | (define_insn "*r<noxa>sbg_<mode>_sll" | |
3887 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3888 | (IXOR:GPR | |
3889 | (and:GPR | |
3890 | (ashift:GPR | |
3891 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3892 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
3893 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
3894 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) | |
3895 | (clobber (reg:CC CC_REGNUM))] | |
3896 | "TARGET_Z10 | |
3897 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]), | |
3898 | INTVAL (operands[2]))" | |
3899 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3" | |
963fc8d0 AK |
3900 | [(set_attr "op_type" "RIE")]) |
3901 | ||
5bb33936 RH |
3902 | ;; These two are generated by combine for s.bf &= val. |
3903 | ;; ??? For bitfields smaller than 32-bits, we wind up with SImode | |
3904 | ;; shifts and ands, which results in some truly awful patterns | |
3905 | ;; including subregs of operations. Rather unnecessisarily, IMO. | |
3906 | ;; Instead of | |
3907 | ;; | |
3908 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
3909 | ;; (const_int 24 [0x18]) | |
3910 | ;; (const_int 0 [0])) | |
3911 | ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
3912 | ;; (const_int 40 [0x28])) 4) | |
3913 | ;; (reg:SI 4 %r4 [ y+4 ])) 0)) | |
3914 | ;; | |
3915 | ;; we should instead generate | |
3916 | ;; | |
3917 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
3918 | ;; (const_int 24 [0x18]) | |
3919 | ;; (const_int 0 [0])) | |
3920 | ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
3921 | ;; (const_int 40 [0x28])) | |
3922 | ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0))) | |
3923 | ;; | |
3924 | ;; by noticing that we can push down the outer paradoxical subreg | |
3925 | ;; into the operation. | |
3926 | ||
3927 | (define_insn "*insv_rnsbg_noshift" | |
3928 | [(set (zero_extract:DI | |
3929 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
3930 | (match_operand 1 "const_int_operand" "") | |
3931 | (match_operand 2 "const_int_operand" "")) | |
3932 | (and:DI | |
3933 | (match_dup 0) | |
3934 | (match_operand:DI 3 "nonimmediate_operand" "d"))) | |
3935 | (clobber (reg:CC CC_REGNUM))] | |
3936 | "TARGET_Z10 | |
3937 | && INTVAL (operands[1]) + INTVAL (operands[2]) == 64" | |
3938 | "rnsbg\t%0,%3,%2,63,0" | |
3939 | [(set_attr "op_type" "RIE")]) | |
3940 | ||
3941 | (define_insn "*insv_rnsbg_srl" | |
3942 | [(set (zero_extract:DI | |
3943 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
3944 | (match_operand 1 "const_int_operand" "") | |
3945 | (match_operand 2 "const_int_operand" "")) | |
3946 | (and:DI | |
3947 | (lshiftrt:DI | |
3948 | (match_dup 0) | |
3949 | (match_operand 3 "const_int_operand" "")) | |
3950 | (match_operand:DI 4 "nonimmediate_operand" "d"))) | |
3951 | (clobber (reg:CC CC_REGNUM))] | |
3952 | "TARGET_Z10 | |
3953 | && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])" | |
3954 | "rnsbg\t%0,%4,%2,%2+%1-1,%3" | |
3955 | [(set_attr "op_type" "RIE")]) | |
3956 | ||
6fa05db6 | 3957 | (define_insn "*insv<mode>_mem_reg" |
9602b6a1 | 3958 | [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") |
6fa05db6 AS |
3959 | (match_operand 1 "const_int_operand" "n,n") |
3960 | (const_int 0)) | |
9602b6a1 | 3961 | (match_operand:W 2 "register_operand" "d,d"))] |
6fa05db6 AS |
3962 | "INTVAL (operands[1]) > 0 |
3963 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
3964 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
3965 | { | |
3966 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
3967 | ||
3968 | operands[1] = GEN_INT ((1ul << size) - 1); | |
9381e3f1 | 3969 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
3970 | : "stcmy\t%2,%1,%S0"; |
3971 | } | |
9381e3f1 WG |
3972 | [(set_attr "op_type" "RS,RSY") |
3973 | (set_attr "z10prop" "z10_super,z10_super")]) | |
6fa05db6 AS |
3974 | |
3975 | (define_insn "*insvdi_mem_reghigh" | |
3976 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") | |
3977 | (match_operand 1 "const_int_operand" "n") | |
3978 | (const_int 0)) | |
3979 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
3980 | (const_int 32)))] | |
9602b6a1 | 3981 | "TARGET_ZARCH |
6fa05db6 AS |
3982 | && INTVAL (operands[1]) > 0 |
3983 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
3984 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
3985 | { | |
3986 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
3987 | ||
3988 | operands[1] = GEN_INT ((1ul << size) - 1); | |
3989 | return "stcmh\t%2,%1,%S0"; | |
3990 | } | |
9381e3f1 WG |
3991 | [(set_attr "op_type" "RSY") |
3992 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 | 3993 | |
9602b6a1 AK |
3994 | (define_insn "*insvdi_reg_imm" |
3995 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3996 | (const_int 16) | |
3997 | (match_operand 1 "const_int_operand" "n")) | |
3998 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6fa05db6 AS |
3999 | "TARGET_ZARCH |
4000 | && INTVAL (operands[1]) >= 0 | |
4001 | && INTVAL (operands[1]) < BITS_PER_WORD | |
4002 | && INTVAL (operands[1]) % 16 == 0" | |
4003 | { | |
4004 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
4005 | { | |
4006 | case 64: return "iihh\t%0,%x2"; break; | |
4007 | case 48: return "iihl\t%0,%x2"; break; | |
4008 | case 32: return "iilh\t%0,%x2"; break; | |
4009 | case 16: return "iill\t%0,%x2"; break; | |
4010 | default: gcc_unreachable(); | |
4011 | } | |
4012 | } | |
9381e3f1 WG |
4013 | [(set_attr "op_type" "RI") |
4014 | (set_attr "z10prop" "z10_super_E1")]) | |
4015 | ||
9fec758d WG |
4016 | ; Update the left-most 32 bit of a DI. |
4017 | (define_insn "*insv_h_di_reg_extimm" | |
4018 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4019 | (const_int 32) | |
4020 | (const_int 0)) | |
4021 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4022 | "TARGET_EXTIMM" | |
4023 | "iihf\t%0,%o1" | |
4024 | [(set_attr "op_type" "RIL") | |
4025 | (set_attr "z10prop" "z10_fwd_E1")]) | |
6fa05db6 | 4026 | |
d378b983 RH |
4027 | ; Update the right-most 32 bit of a DI. |
4028 | (define_insn "*insv_l_di_reg_extimm" | |
4029 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4030 | (const_int 32) | |
4031 | (const_int 32)) | |
4032 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4033 | "TARGET_EXTIMM" | |
4034 | "iilf\t%0,%o1" | |
9381e3f1 | 4035 | [(set_attr "op_type" "RIL") |
9fec758d | 4036 | (set_attr "z10prop" "z10_fwd_A1")]) |
6fa05db6 | 4037 | |
9db1d521 HP |
4038 | ; |
4039 | ; extendsidi2 instruction pattern(s). | |
4040 | ; | |
4041 | ||
4023fb28 UW |
4042 | (define_expand "extendsidi2" |
4043 | [(set (match_operand:DI 0 "register_operand" "") | |
4044 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4045 | "" | |
4023fb28 | 4046 | { |
9602b6a1 | 4047 | if (!TARGET_ZARCH) |
4023fb28 | 4048 | { |
c41c1387 | 4049 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4050 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
4051 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
4052 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
4053 | DONE; |
4054 | } | |
ec24698e | 4055 | }) |
4023fb28 UW |
4056 | |
4057 | (define_insn "*extendsidi2" | |
963fc8d0 AK |
4058 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
4059 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9602b6a1 | 4060 | "TARGET_ZARCH" |
9db1d521 | 4061 | "@ |
d40c829f | 4062 | lgfr\t%0,%1 |
963fc8d0 AK |
4063 | lgf\t%0,%1 |
4064 | lgfrl\t%0,%1" | |
4065 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4066 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4067 | (set_attr "cpu_facility" "*,*,z10") |
4068 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4069 | |
9db1d521 | 4070 | ; |
56477c21 | 4071 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4072 | ; |
4073 | ||
56477c21 AS |
4074 | (define_expand "extend<HQI:mode><DSI:mode>2" |
4075 | [(set (match_operand:DSI 0 "register_operand" "") | |
4076 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 4077 | "" |
4023fb28 | 4078 | { |
9602b6a1 | 4079 | if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) |
4023fb28 UW |
4080 | { |
4081 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 4082 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
4083 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
4084 | DONE; | |
4085 | } | |
ec24698e | 4086 | else if (!TARGET_EXTIMM) |
4023fb28 | 4087 | { |
2542ef05 | 4088 | rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>); |
56477c21 AS |
4089 | |
4090 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
4091 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
4092 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
4093 | DONE; |
4094 | } | |
ec24698e UW |
4095 | }) |
4096 | ||
56477c21 AS |
4097 | ; |
4098 | ; extendhidi2 instruction pattern(s). | |
4099 | ; | |
4100 | ||
ec24698e | 4101 | (define_insn "*extendhidi2_extimm" |
963fc8d0 AK |
4102 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
4103 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))] | |
9602b6a1 | 4104 | "TARGET_ZARCH && TARGET_EXTIMM" |
ec24698e UW |
4105 | "@ |
4106 | lghr\t%0,%1 | |
963fc8d0 AK |
4107 | lgh\t%0,%1 |
4108 | lghrl\t%0,%1" | |
4109 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4110 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4111 | (set_attr "cpu_facility" "extimm,extimm,z10") |
4112 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
4113 | |
4114 | (define_insn "*extendhidi2" | |
9db1d521 | 4115 | [(set (match_operand:DI 0 "register_operand" "=d") |
fb492564 | 4116 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] |
9602b6a1 | 4117 | "TARGET_ZARCH" |
d40c829f | 4118 | "lgh\t%0,%1" |
9381e3f1 WG |
4119 | [(set_attr "op_type" "RXY") |
4120 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 4121 | |
9db1d521 | 4122 | ; |
56477c21 | 4123 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
4124 | ; |
4125 | ||
ec24698e | 4126 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
4127 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4128 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
4129 | "TARGET_EXTIMM" |
4130 | "@ | |
4131 | lhr\t%0,%1 | |
4132 | lh\t%0,%1 | |
963fc8d0 AK |
4133 | lhy\t%0,%1 |
4134 | lhrl\t%0,%1" | |
4135 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
4136 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 WG |
4137 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
4138 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4139 | |
4023fb28 | 4140 | (define_insn "*extendhisi2" |
d3632d41 UW |
4141 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4142 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 4143 | "!TARGET_EXTIMM" |
d3632d41 | 4144 | "@ |
d40c829f UW |
4145 | lh\t%0,%1 |
4146 | lhy\t%0,%1" | |
9381e3f1 WG |
4147 | [(set_attr "op_type" "RX,RXY") |
4148 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4149 | |
56477c21 AS |
4150 | ; |
4151 | ; extendqi(si|di)2 instruction pattern(s). | |
4152 | ; | |
4153 | ||
43a09b63 | 4154 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
4155 | (define_insn "*extendqi<mode>2_extimm" |
4156 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 4157 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
4158 | "TARGET_EXTIMM" |
4159 | "@ | |
56477c21 AS |
4160 | l<g>br\t%0,%1 |
4161 | l<g>b\t%0,%1" | |
9381e3f1 WG |
4162 | [(set_attr "op_type" "RRE,RXY") |
4163 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 4164 | |
43a09b63 | 4165 | ; lb, lgb |
56477c21 AS |
4166 | (define_insn "*extendqi<mode>2" |
4167 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 4168 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))] |
56477c21 AS |
4169 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
4170 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
4171 | [(set_attr "op_type" "RXY") |
4172 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 4173 | |
56477c21 AS |
4174 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
4175 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4176 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 4177 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 4178 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
4179 | "#" |
4180 | "&& reload_completed" | |
4023fb28 | 4181 | [(parallel |
56477c21 | 4182 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 4183 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 4184 | (parallel |
56477c21 | 4185 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 4186 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
4187 | { |
4188 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4189 | set_mem_size (operands[1], GET_MODE_SIZE (QImode)); |
2542ef05 | 4190 | operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT); |
6fa05db6 | 4191 | }) |
9db1d521 | 4192 | |
9db1d521 HP |
4193 | ; |
4194 | ; zero_extendsidi2 instruction pattern(s). | |
4195 | ; | |
4196 | ||
4023fb28 UW |
4197 | (define_expand "zero_extendsidi2" |
4198 | [(set (match_operand:DI 0 "register_operand" "") | |
4199 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4200 | "" | |
4023fb28 | 4201 | { |
9602b6a1 | 4202 | if (!TARGET_ZARCH) |
4023fb28 | 4203 | { |
c41c1387 | 4204 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4205 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
4206 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
4207 | DONE; |
4208 | } | |
ec24698e | 4209 | }) |
4023fb28 UW |
4210 | |
4211 | (define_insn "*zero_extendsidi2" | |
963fc8d0 AK |
4212 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
4213 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9602b6a1 | 4214 | "TARGET_ZARCH" |
9db1d521 | 4215 | "@ |
d40c829f | 4216 | llgfr\t%0,%1 |
963fc8d0 AK |
4217 | llgf\t%0,%1 |
4218 | llgfrl\t%0,%1" | |
4219 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4220 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4221 | (set_attr "cpu_facility" "*,*,z10") |
4222 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) | |
9db1d521 | 4223 | |
288e517f AK |
4224 | ; |
4225 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
4226 | ; | |
4227 | ||
d6083c7d UW |
4228 | (define_insn "*llgt_sidi" |
4229 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 4230 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d | 4231 | (const_int 2147483647)))] |
9602b6a1 | 4232 | "TARGET_ZARCH" |
d6083c7d | 4233 | "llgt\t%0,%1" |
9381e3f1 WG |
4234 | [(set_attr "op_type" "RXE") |
4235 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
4236 | |
4237 | (define_insn_and_split "*llgt_sidi_split" | |
4238 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 4239 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d | 4240 | (const_int 2147483647))) |
ae156f85 | 4241 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4242 | "TARGET_ZARCH" |
d6083c7d UW |
4243 | "#" |
4244 | "&& reload_completed" | |
4245 | [(set (match_dup 0) | |
4246 | (and:DI (subreg:DI (match_dup 1) 0) | |
4247 | (const_int 2147483647)))] | |
4248 | "") | |
4249 | ||
288e517f AK |
4250 | (define_insn "*llgt_sisi" |
4251 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
fb492564 | 4252 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT") |
288e517f | 4253 | (const_int 2147483647)))] |
c4d50129 | 4254 | "TARGET_ZARCH" |
288e517f AK |
4255 | "@ |
4256 | llgtr\t%0,%1 | |
4257 | llgt\t%0,%1" | |
9381e3f1 WG |
4258 | [(set_attr "op_type" "RRE,RXE") |
4259 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4260 | |
288e517f AK |
4261 | (define_insn "*llgt_didi" |
4262 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4263 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
4264 | (const_int 2147483647)))] | |
9602b6a1 | 4265 | "TARGET_ZARCH" |
288e517f AK |
4266 | "@ |
4267 | llgtr\t%0,%1 | |
4268 | llgt\t%0,%N1" | |
9381e3f1 WG |
4269 | [(set_attr "op_type" "RRE,RXE") |
4270 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4271 | |
f19a9af7 | 4272 | (define_split |
9602b6a1 AK |
4273 | [(set (match_operand:DSI 0 "register_operand" "") |
4274 | (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") | |
f6ee577c | 4275 | (const_int 2147483647))) |
ae156f85 | 4276 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 4277 | "TARGET_ZARCH && reload_completed" |
288e517f | 4278 | [(set (match_dup 0) |
9602b6a1 | 4279 | (and:DSI (match_dup 1) |
f6ee577c | 4280 | (const_int 2147483647)))] |
288e517f AK |
4281 | "") |
4282 | ||
9db1d521 | 4283 | ; |
56477c21 | 4284 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4285 | ; |
4286 | ||
56477c21 AS |
4287 | (define_expand "zero_extend<mode>di2" |
4288 | [(set (match_operand:DI 0 "register_operand" "") | |
4289 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4290 | "" | |
4291 | { | |
9602b6a1 | 4292 | if (!TARGET_ZARCH) |
56477c21 AS |
4293 | { |
4294 | rtx tmp = gen_reg_rtx (SImode); | |
4295 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
4296 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
4297 | DONE; | |
4298 | } | |
4299 | else if (!TARGET_EXTIMM) | |
4300 | { | |
2542ef05 | 4301 | rtx bitcount = GEN_INT (64 - <HQI:bitsize>); |
56477c21 AS |
4302 | operands[1] = gen_lowpart (DImode, operands[1]); |
4303 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
4304 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
4305 | DONE; | |
4306 | } | |
4307 | }) | |
4308 | ||
f6ee577c | 4309 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 4310 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 4311 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 4312 | "" |
4023fb28 | 4313 | { |
ec24698e UW |
4314 | if (!TARGET_EXTIMM) |
4315 | { | |
4316 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 4317 | emit_insn (gen_andsi3 (operands[0], operands[1], |
2542ef05 | 4318 | GEN_INT ((1 << <HQI:bitsize>) - 1))); |
ec24698e | 4319 | DONE; |
56477c21 | 4320 | } |
ec24698e UW |
4321 | }) |
4322 | ||
963fc8d0 AK |
4323 | ; llhrl, llghrl |
4324 | (define_insn "*zero_extendhi<mode>2_z10" | |
4325 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
4326 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))] | |
4327 | "TARGET_Z10" | |
4328 | "@ | |
4329 | ll<g>hr\t%0,%1 | |
4330 | ll<g>h\t%0,%1 | |
4331 | ll<g>hrl\t%0,%1" | |
4332 | [(set_attr "op_type" "RXY,RRE,RIL") | |
4333 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4334 | (set_attr "cpu_facility" "*,*,z10") |
729e750f | 4335 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) |
963fc8d0 | 4336 | |
43a09b63 | 4337 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
4338 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
4339 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 4340 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
4341 | "TARGET_EXTIMM" |
4342 | "@ | |
56477c21 AS |
4343 | ll<g><hc>r\t%0,%1 |
4344 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
4345 | [(set_attr "op_type" "RRE,RXY") |
4346 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 4347 | |
43a09b63 | 4348 | ; llgh, llgc |
56477c21 AS |
4349 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
4350 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 4351 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))] |
ec24698e | 4352 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 4353 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
4354 | [(set_attr "op_type" "RXY") |
4355 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
4356 | |
4357 | (define_insn_and_split "*zero_extendhisi2_31" | |
4358 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 4359 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
ae156f85 | 4360 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 4361 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4362 | "#" |
4363 | "&& reload_completed" | |
4364 | [(set (match_dup 0) (const_int 0)) | |
4365 | (parallel | |
4366 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 4367 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4368 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 4369 | |
cc7ab9b7 UW |
4370 | (define_insn_and_split "*zero_extendqisi2_31" |
4371 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
fb492564 | 4372 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 4373 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4374 | "#" |
4375 | "&& reload_completed" | |
4376 | [(set (match_dup 0) (const_int 0)) | |
4377 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4378 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 4379 | |
9db1d521 HP |
4380 | ; |
4381 | ; zero_extendqihi2 instruction pattern(s). | |
4382 | ; | |
4383 | ||
9db1d521 HP |
4384 | (define_expand "zero_extendqihi2" |
4385 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 4386 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 4387 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 4388 | { |
4023fb28 UW |
4389 | operands[1] = gen_lowpart (HImode, operands[1]); |
4390 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
4391 | DONE; | |
ec24698e | 4392 | }) |
9db1d521 | 4393 | |
4023fb28 | 4394 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 4395 | [(set (match_operand:HI 0 "register_operand" "=d") |
fb492564 | 4396 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
ec24698e | 4397 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 4398 | "llgc\t%0,%1" |
9381e3f1 WG |
4399 | [(set_attr "op_type" "RXY") |
4400 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 4401 | |
cc7ab9b7 UW |
4402 | (define_insn_and_split "*zero_extendqihi2_31" |
4403 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
fb492564 | 4404 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 4405 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4406 | "#" |
4407 | "&& reload_completed" | |
4408 | [(set (match_dup 0) (const_int 0)) | |
4409 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4410 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 4411 | |
609e7e80 AK |
4412 | ; |
4413 | ; fixuns_trunc(dd|td)di2 instruction pattern(s). | |
4414 | ; | |
4415 | ||
4416 | (define_expand "fixuns_truncdddi2" | |
4417 | [(parallel | |
4418 | [(set (match_operand:DI 0 "register_operand" "") | |
4419 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) | |
65b1d8ea AK |
4420 | (unspec:DI [(const_int 5)] UNSPEC_ROUND) |
4421 | (clobber (reg:CC CC_REGNUM))])] | |
9381e3f1 | 4422 | |
fb068247 | 4423 | "TARGET_HARD_DFP" |
609e7e80 | 4424 | { |
65b1d8ea AK |
4425 | if (!TARGET_Z196) |
4426 | { | |
19f8b229 TS |
4427 | rtx_code_label *label1 = gen_label_rtx (); |
4428 | rtx_code_label *label2 = gen_label_rtx (); | |
65b1d8ea AK |
4429 | rtx temp = gen_reg_rtx (TDmode); |
4430 | REAL_VALUE_TYPE cmp, sub; | |
4431 | ||
4432 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4433 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4434 | ||
4435 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
4436 | solution is doing the check and the subtraction in TD mode and using a | |
4437 | TD -> DI convert afterwards. */ | |
4438 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
4439 | temp = force_reg (TDmode, temp); | |
4440 | emit_cmp_and_jump_insns (temp, | |
555affd7 | 4441 | const_double_from_real_value (cmp, TDmode), |
65b1d8ea AK |
4442 | LT, NULL_RTX, VOIDmode, 0, label1); |
4443 | emit_insn (gen_subtd3 (temp, temp, | |
555affd7 | 4444 | const_double_from_real_value (sub, TDmode))); |
65b1d8ea AK |
4445 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); |
4446 | emit_jump (label2); | |
4447 | ||
4448 | emit_label (label1); | |
4449 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9))); | |
4450 | emit_label (label2); | |
4451 | DONE; | |
4452 | } | |
609e7e80 AK |
4453 | }) |
4454 | ||
4455 | (define_expand "fixuns_trunctddi2" | |
65b1d8ea AK |
4456 | [(parallel |
4457 | [(set (match_operand:DI 0 "register_operand" "") | |
4458 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) | |
4459 | (unspec:DI [(const_int 5)] UNSPEC_ROUND) | |
4460 | (clobber (reg:CC CC_REGNUM))])] | |
4461 | ||
fb068247 | 4462 | "TARGET_HARD_DFP" |
609e7e80 | 4463 | { |
65b1d8ea AK |
4464 | if (!TARGET_Z196) |
4465 | { | |
19f8b229 TS |
4466 | rtx_code_label *label1 = gen_label_rtx (); |
4467 | rtx_code_label *label2 = gen_label_rtx (); | |
65b1d8ea AK |
4468 | rtx temp = gen_reg_rtx (TDmode); |
4469 | REAL_VALUE_TYPE cmp, sub; | |
4470 | ||
4471 | operands[1] = force_reg (TDmode, operands[1]); | |
4472 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4473 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4474 | ||
4475 | emit_cmp_and_jump_insns (operands[1], | |
555affd7 | 4476 | const_double_from_real_value (cmp, TDmode), |
65b1d8ea AK |
4477 | LT, NULL_RTX, VOIDmode, 0, label1); |
4478 | emit_insn (gen_subtd3 (temp, operands[1], | |
555affd7 | 4479 | const_double_from_real_value (sub, TDmode))); |
65b1d8ea AK |
4480 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); |
4481 | emit_jump (label2); | |
4482 | ||
4483 | emit_label (label1); | |
4484 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9))); | |
4485 | emit_label (label2); | |
4486 | DONE; | |
4487 | } | |
609e7e80 | 4488 | }) |
cc7ab9b7 | 4489 | |
9db1d521 | 4490 | ; |
65b1d8ea | 4491 | ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2 |
609e7e80 | 4492 | ; instruction pattern(s). |
9db1d521 HP |
4493 | ; |
4494 | ||
7b6baae1 | 4495 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2" |
65b1d8ea AK |
4496 | [(parallel |
4497 | [(set (match_operand:GPR 0 "register_operand" "") | |
4498 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) | |
4499 | (unspec:GPR [(const_int 5)] UNSPEC_ROUND) | |
4500 | (clobber (reg:CC CC_REGNUM))])] | |
142cd70f | 4501 | "TARGET_HARD_FLOAT" |
9db1d521 | 4502 | { |
65b1d8ea AK |
4503 | if (!TARGET_Z196) |
4504 | { | |
19f8b229 TS |
4505 | rtx_code_label *label1 = gen_label_rtx (); |
4506 | rtx_code_label *label2 = gen_label_rtx (); | |
65b1d8ea AK |
4507 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); |
4508 | REAL_VALUE_TYPE cmp, sub; | |
4509 | ||
4510 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); | |
2542ef05 RH |
4511 | real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode); |
4512 | real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode); | |
65b1d8ea AK |
4513 | |
4514 | emit_cmp_and_jump_insns (operands[1], | |
555affd7 | 4515 | const_double_from_real_value (cmp, <BFP:MODE>mode), |
65b1d8ea AK |
4516 | LT, NULL_RTX, VOIDmode, 0, label1); |
4517 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], | |
555affd7 | 4518 | const_double_from_real_value (sub, <BFP:MODE>mode))); |
65b1d8ea AK |
4519 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, |
4520 | GEN_INT (7))); | |
4521 | emit_jump (label2); | |
4522 | ||
4523 | emit_label (label1); | |
4524 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], | |
4525 | operands[1], GEN_INT (5))); | |
4526 | emit_label (label2); | |
4527 | DONE; | |
4528 | } | |
10bbf137 | 4529 | }) |
9db1d521 | 4530 | |
65b1d8ea AK |
4531 | ; fixuns_trunc(td|dd)si2 expander |
4532 | (define_expand "fixuns_trunc<mode>si2" | |
4533 | [(parallel | |
4534 | [(set (match_operand:SI 0 "register_operand" "") | |
4535 | (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) | |
4536 | (unspec:SI [(const_int 5)] UNSPEC_ROUND) | |
4537 | (clobber (reg:CC CC_REGNUM))])] | |
8540e6e8 | 4538 | "TARGET_Z196 && TARGET_HARD_DFP" |
65b1d8ea AK |
4539 | "") |
4540 | ||
4541 | ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. | |
4542 | ||
6e5b5de8 AK |
4543 | (define_insn "*fixuns_truncdfdi2_z13" |
4544 | [(set (match_operand:DI 0 "register_operand" "=d,v") | |
4545 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
4546 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
4547 | (clobber (reg:CC CC_REGNUM))] | |
4548 | "TARGET_Z13 && TARGET_HARD_FLOAT" | |
4549 | "@ | |
4550 | clgdbr\t%0,%h2,%1,0 | |
4551 | wclgdb\t%v0,%v1,0,%h2" | |
4552 | [(set_attr "op_type" "RRF,VRR") | |
4553 | (set_attr "type" "ftoi")]) | |
4554 | ||
65b1d8ea AK |
4555 | ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr |
4556 | ; clfdtr, clfxtr, clgdtr, clgxtr | |
4557 | (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" | |
6e5b5de8 AK |
4558 | [(set (match_operand:GPR 0 "register_operand" "=d") |
4559 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) | |
4560 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
65b1d8ea | 4561 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 AK |
4562 | "TARGET_Z196 && TARGET_HARD_FLOAT |
4563 | && (!TARGET_Z13 || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)" | |
65b1d8ea AK |
4564 | "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" |
4565 | [(set_attr "op_type" "RRF") | |
4566 | (set_attr "type" "ftoi")]) | |
4567 | ||
b60cb710 AK |
4568 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
4569 | [(set (match_operand:GPR 0 "register_operand" "") | |
4570 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
4571 | "TARGET_HARD_FLOAT" | |
9db1d521 | 4572 | { |
b60cb710 AK |
4573 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
4574 | GEN_INT (5))); | |
9db1d521 | 4575 | DONE; |
10bbf137 | 4576 | }) |
9db1d521 | 4577 | |
6e5b5de8 AK |
4578 | (define_insn "*fix_truncdfdi2_bfp_z13" |
4579 | [(set (match_operand:DI 0 "register_operand" "=d,v") | |
4580 | (fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
4581 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
4582 | (clobber (reg:CC CC_REGNUM))] | |
4583 | "TARGET_Z13 && TARGET_HARD_FLOAT" | |
4584 | "@ | |
4585 | cgdbr\t%0,%h2,%1 | |
4586 | wcgdb\t%v0,%v1,0,%h2" | |
4587 | [(set_attr "op_type" "RRE,VRR") | |
4588 | (set_attr "type" "ftoi")]) | |
4589 | ||
43a09b63 | 4590 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
6e5b5de8 AK |
4591 | (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp" |
4592 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4593 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
4594 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
ae156f85 | 4595 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 AK |
4596 | "TARGET_HARD_FLOAT |
4597 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)" | |
7b6baae1 | 4598 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 4599 | [(set_attr "op_type" "RRE") |
077dab3b | 4600 | (set_attr "type" "ftoi")]) |
9db1d521 | 4601 | |
6e5b5de8 AK |
4602 | (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
4603 | [(parallel | |
4604 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4605 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
4606 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4607 | (clobber (reg:CC CC_REGNUM))])] | |
4608 | "TARGET_HARD_FLOAT") | |
609e7e80 AK |
4609 | ; |
4610 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
4611 | ; | |
4612 | ||
99cd7dd0 AK |
4613 | (define_expand "fix_trunc<mode>di2" |
4614 | [(set (match_operand:DI 0 "register_operand" "") | |
4615 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
9602b6a1 | 4616 | "TARGET_ZARCH && TARGET_HARD_DFP" |
99cd7dd0 AK |
4617 | { |
4618 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
4619 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
4620 | GEN_INT (9))); | |
4621 | DONE; | |
4622 | }) | |
4623 | ||
609e7e80 | 4624 | ; cgxtr, cgdtr |
99cd7dd0 | 4625 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
4626 | [(set (match_operand:DI 0 "register_operand" "=d") |
4627 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
4628 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4629 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 4630 | "TARGET_ZARCH && TARGET_HARD_DFP" |
609e7e80 AK |
4631 | "cg<DFP:xde>tr\t%0,%h2,%1" |
4632 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 4633 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
4634 | |
4635 | ||
f61a2c7d AK |
4636 | ; |
4637 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
4638 | ; | |
4639 | ||
4640 | (define_expand "fix_trunctf<mode>2" | |
4641 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
4642 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
4643 | (unspec:GPR [(const_int 5)] UNSPEC_ROUND) | |
4644 | (clobber (reg:CC CC_REGNUM))])] | |
9db1d521 | 4645 | "TARGET_HARD_FLOAT" |
142cd70f | 4646 | "") |
9db1d521 | 4647 | |
9db1d521 | 4648 | |
9db1d521 | 4649 | ; |
142cd70f | 4650 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
4651 | ; |
4652 | ||
609e7e80 | 4653 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 4654 | (define_insn "floatdi<mode>2" |
6e5b5de8 AK |
4655 | [(set (match_operand:FP 0 "register_operand" "=f,<vf>") |
4656 | (float:FP (match_operand:DI 1 "register_operand" "d,<vd>")))] | |
9602b6a1 | 4657 | "TARGET_ZARCH && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
4658 | "@ |
4659 | c<xde>g<bt>r\t%0,%1 | |
4660 | wcdgb\t%v0,%v1,0,0" | |
4661 | [(set_attr "op_type" "RRE,VRR") | |
4662 | (set_attr "type" "itof<mode>" ) | |
4663 | (set_attr "cpu_facility" "*,vec")]) | |
9db1d521 | 4664 | |
43a09b63 | 4665 | ; cxfbr, cdfbr, cefbr |
142cd70f | 4666 | (define_insn "floatsi<mode>2" |
7b6baae1 AK |
4667 | [(set (match_operand:BFP 0 "register_operand" "=f") |
4668 | (float:BFP (match_operand:SI 1 "register_operand" "d")))] | |
142cd70f | 4669 | "TARGET_HARD_FLOAT" |
f61a2c7d AK |
4670 | "c<xde>fbr\t%0,%1" |
4671 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 4672 | (set_attr "type" "itof<mode>" )]) |
f61a2c7d | 4673 | |
65b1d8ea AK |
4674 | ; cxftr, cdftr |
4675 | (define_insn "floatsi<mode>2" | |
4676 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
4677 | (float:DFP (match_operand:SI 1 "register_operand" "d")))] | |
4678 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
4679 | "c<xde>ftr\t%0,0,%1,0" | |
4680 | [(set_attr "op_type" "RRE") | |
4681 | (set_attr "type" "itof<mode>" )]) | |
4682 | ||
4683 | ; | |
4684 | ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). | |
4685 | ; | |
4686 | ||
6e5b5de8 AK |
4687 | (define_insn "*floatunsdidf2_z13" |
4688 | [(set (match_operand:DF 0 "register_operand" "=f,v") | |
4689 | (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))] | |
4690 | "TARGET_Z13 && TARGET_HARD_FLOAT" | |
4691 | "@ | |
4692 | cdlgbr\t%0,0,%1,0 | |
4693 | wcdlgb\t%v0,%v1,0,0" | |
4694 | [(set_attr "op_type" "RRE,VRR") | |
4695 | (set_attr "type" "itofdf")]) | |
4696 | ||
65b1d8ea AK |
4697 | ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr |
4698 | ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr | |
6e5b5de8 AK |
4699 | (define_insn "*floatuns<GPR:mode><FP:mode>2" |
4700 | [(set (match_operand:FP 0 "register_operand" "=f") | |
4701 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] | |
4702 | "TARGET_Z196 && TARGET_HARD_FLOAT | |
4703 | && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)" | |
65b1d8ea AK |
4704 | "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" |
4705 | [(set_attr "op_type" "RRE") | |
6e5b5de8 AK |
4706 | (set_attr "type" "itof<FP:mode>")]) |
4707 | ||
4708 | (define_expand "floatuns<GPR:mode><FP:mode>2" | |
4709 | [(set (match_operand:FP 0 "register_operand" "") | |
4710 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))] | |
4711 | "TARGET_Z196 && TARGET_HARD_FLOAT") | |
f61a2c7d | 4712 | |
9db1d521 HP |
4713 | ; |
4714 | ; truncdfsf2 instruction pattern(s). | |
4715 | ; | |
4716 | ||
142cd70f | 4717 | (define_insn "truncdfsf2" |
6e5b5de8 AK |
4718 | [(set (match_operand:SF 0 "register_operand" "=f,v") |
4719 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))] | |
142cd70f | 4720 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
4721 | "@ |
4722 | ledbr\t%0,%1 | |
4723 | wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed | |
4724 | ; According to BFP rounding mode | |
4725 | [(set_attr "op_type" "RRE,VRR") | |
4726 | (set_attr "type" "ftruncdf") | |
4727 | (set_attr "cpu_facility" "*,vec")]) | |
9db1d521 | 4728 | |
f61a2c7d | 4729 | ; |
142cd70f | 4730 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
4731 | ; |
4732 | ||
142cd70f AK |
4733 | ; ldxbr, lexbr |
4734 | (define_insn "trunctf<mode>2" | |
4735 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
4736 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 4737 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
4738 | "TARGET_HARD_FLOAT" |
4739 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 4740 | [(set_attr "length" "6") |
9381e3f1 | 4741 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 4742 | |
609e7e80 AK |
4743 | ; |
4744 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
4745 | ; | |
4746 | ||
4747 | (define_insn "trunctddd2" | |
4748 | [(set (match_operand:DD 0 "register_operand" "=f") | |
bf259a77 AK |
4749 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
4750 | (clobber (match_scratch:TD 2 "=f"))] | |
fb068247 | 4751 | "TARGET_HARD_DFP" |
bf259a77 AK |
4752 | "ldxtr\t%2,0,%1,0\;ldr\t%0,%2" |
4753 | [(set_attr "length" "6") | |
9381e3f1 | 4754 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
4755 | |
4756 | (define_insn "truncddsd2" | |
4757 | [(set (match_operand:SD 0 "register_operand" "=f") | |
4758 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4759 | "TARGET_HARD_DFP" |
609e7e80 AK |
4760 | "ledtr\t%0,0,%1,0" |
4761 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 4762 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 4763 | |
feade5a8 AK |
4764 | (define_expand "trunctdsd2" |
4765 | [(parallel | |
4766 | [(set (match_dup 3) | |
4767 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) | |
4768 | (clobber (match_scratch:TD 2 ""))]) | |
4769 | (set (match_operand:SD 0 "register_operand" "") | |
4770 | (float_truncate:SD (match_dup 3)))] | |
4771 | "TARGET_HARD_DFP" | |
4772 | { | |
4773 | operands[3] = gen_reg_rtx (DDmode); | |
4774 | }) | |
4775 | ||
9db1d521 | 4776 | ; |
142cd70f | 4777 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
4778 | ; |
4779 | ||
6e5b5de8 AK |
4780 | (define_insn "*extendsfdf2_z13" |
4781 | [(set (match_operand:DF 0 "register_operand" "=f,f,v") | |
4782 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))] | |
4783 | "TARGET_Z13 && TARGET_HARD_FLOAT" | |
4784 | "@ | |
4785 | ldebr\t%0,%1 | |
4786 | ldeb\t%0,%1 | |
4787 | wldeb\t%v0,%v1" | |
4788 | [(set_attr "op_type" "RRE,RXE,VRR") | |
4789 | (set_attr "type" "fsimpdf, floaddf,fsimpdf")]) | |
4790 | ||
142cd70f | 4791 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
6e5b5de8 AK |
4792 | (define_insn "*extend<DSF:mode><BFP:mode>2" |
4793 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
142cd70f AK |
4794 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] |
4795 | "TARGET_HARD_FLOAT | |
6e5b5de8 AK |
4796 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode) |
4797 | && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)" | |
f61a2c7d | 4798 | "@ |
142cd70f AK |
4799 | l<BFP:xde><DSF:xde>br\t%0,%1 |
4800 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
6e5b5de8 AK |
4801 | [(set_attr "op_type" "RRE,RXE") |
4802 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) | |
4803 | ||
4804 | (define_expand "extend<DSF:mode><BFP:mode>2" | |
4805 | [(set (match_operand:BFP 0 "register_operand" "") | |
4806 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))] | |
4807 | "TARGET_HARD_FLOAT | |
4808 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)") | |
f61a2c7d | 4809 | |
609e7e80 AK |
4810 | ; |
4811 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
4812 | ; | |
4813 | ||
4814 | (define_insn "extendddtd2" | |
4815 | [(set (match_operand:TD 0 "register_operand" "=f") | |
4816 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4817 | "TARGET_HARD_DFP" |
609e7e80 AK |
4818 | "lxdtr\t%0,%1,0" |
4819 | [(set_attr "op_type" "RRF") | |
4820 | (set_attr "type" "fsimptf")]) | |
4821 | ||
4822 | (define_insn "extendsddd2" | |
4823 | [(set (match_operand:DD 0 "register_operand" "=f") | |
4824 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 4825 | "TARGET_HARD_DFP" |
609e7e80 AK |
4826 | "ldetr\t%0,%1,0" |
4827 | [(set_attr "op_type" "RRF") | |
4828 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 4829 | |
feade5a8 AK |
4830 | (define_expand "extendsdtd2" |
4831 | [(set (match_dup 2) | |
4832 | (float_extend:DD (match_operand:SD 1 "register_operand" ""))) | |
4833 | (set (match_operand:TD 0 "register_operand" "") | |
4834 | (float_extend:TD (match_dup 2)))] | |
4835 | "TARGET_HARD_DFP" | |
4836 | { | |
4837 | operands[2] = gen_reg_rtx (DDmode); | |
4838 | }) | |
4839 | ||
d12a76f3 AK |
4840 | ; Binary Floating Point - load fp integer |
4841 | ||
4842 | ; Expanders for: floor, btrunc, round, ceil, and nearbyint | |
4843 | ; For all of them the inexact exceptions are suppressed. | |
4844 | ||
4845 | ; fiebra, fidbra, fixbra | |
4846 | (define_insn "<FPINT:fpint_name><BFP:mode>2" | |
4847 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
4848 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
4849 | FPINT))] | |
4850 | "TARGET_Z196" | |
4851 | "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
4852 | [(set_attr "op_type" "RRF") | |
4853 | (set_attr "type" "fsimp<BFP:mode>")]) | |
4854 | ||
4855 | ; rint is supposed to raise an inexact exception so we can use the | |
4856 | ; older instructions. | |
4857 | ||
4858 | ; fiebr, fidbr, fixbr | |
4859 | (define_insn "rint<BFP:mode>2" | |
4860 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
4861 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
4862 | UNSPEC_FPINT_RINT))] | |
4863 | "" | |
4864 | "fi<BFP:xde>br\t%0,0,%1" | |
4865 | [(set_attr "op_type" "RRF") | |
4866 | (set_attr "type" "fsimp<BFP:mode>")]) | |
4867 | ||
4868 | ||
4869 | ; Decimal Floating Point - load fp integer | |
4870 | ||
4871 | ; fidtr, fixtr | |
4872 | (define_insn "<FPINT:fpint_name><DFP:mode>2" | |
4873 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
4874 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
4875 | FPINT))] | |
4876 | "TARGET_HARD_DFP" | |
4877 | "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
4878 | [(set_attr "op_type" "RRF") | |
4879 | (set_attr "type" "fsimp<DFP:mode>")]) | |
4880 | ||
4881 | ; fidtr, fixtr | |
4882 | (define_insn "rint<DFP:mode>2" | |
4883 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
4884 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
4885 | UNSPEC_FPINT_RINT))] | |
4886 | "TARGET_HARD_DFP" | |
4887 | "fi<DFP:xde>tr\t%0,0,%1,0" | |
4888 | [(set_attr "op_type" "RRF") | |
4889 | (set_attr "type" "fsimp<DFP:mode>")]) | |
4890 | ||
4891 | ; | |
35dd9a0e AK |
4892 | ; Binary <-> Decimal floating point trunc patterns |
4893 | ; | |
4894 | ||
4895 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
4896 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 4897 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 4898 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
4899 | (clobber (reg:CC CC_REGNUM)) |
4900 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 4901 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4902 | "pfpo") |
4903 | ||
4904 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
4905 | [(set (reg:BFP FPR0_REGNUM) | |
2cf4c39e | 4906 | (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 4907 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
4908 | (clobber (reg:CC CC_REGNUM)) |
4909 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 4910 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4911 | "pfpo") |
4912 | ||
4913 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 4914 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
4915 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
4916 | (parallel | |
4917 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 4918 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 4919 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
4920 | (clobber (reg:CC CC_REGNUM)) |
4921 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
4922 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
4923 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 4924 | "TARGET_HARD_DFP |
35dd9a0e AK |
4925 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
4926 | { | |
4927 | HOST_WIDE_INT flags; | |
4928 | ||
4929 | flags = (PFPO_CONVERT | | |
4930 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4931 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4932 | ||
4933 | operands[2] = GEN_INT (flags); | |
4934 | }) | |
4935 | ||
4936 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 4937 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
4938 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
4939 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4940 | (parallel | |
2cf4c39e | 4941 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 4942 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
4943 | (clobber (reg:CC CC_REGNUM)) |
4944 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 4945 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 4946 | "TARGET_HARD_DFP |
35dd9a0e AK |
4947 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
4948 | { | |
4949 | HOST_WIDE_INT flags; | |
4950 | ||
4951 | flags = (PFPO_CONVERT | | |
4952 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4953 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4954 | ||
4955 | operands[2] = GEN_INT (flags); | |
4956 | }) | |
4957 | ||
4958 | ; | |
4959 | ; Binary <-> Decimal floating point extend patterns | |
4960 | ; | |
4961 | ||
4962 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 4963 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 4964 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
4965 | (clobber (reg:CC CC_REGNUM)) |
4966 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 4967 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4968 | "pfpo") |
4969 | ||
4970 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 4971 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 4972 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
4973 | (clobber (reg:CC CC_REGNUM)) |
4974 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 4975 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4976 | "pfpo") |
4977 | ||
4978 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 4979 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
4980 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
4981 | (parallel | |
4982 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 4983 | (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 4984 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
4985 | (clobber (reg:CC CC_REGNUM)) |
4986 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
4987 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
4988 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 4989 | "TARGET_HARD_DFP |
35dd9a0e AK |
4990 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
4991 | { | |
4992 | HOST_WIDE_INT flags; | |
4993 | ||
4994 | flags = (PFPO_CONVERT | | |
4995 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4996 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4997 | ||
4998 | operands[2] = GEN_INT (flags); | |
4999 | }) | |
5000 | ||
5001 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5002 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5003 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5004 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5005 | (parallel | |
2cf4c39e | 5006 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5007 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5008 | (clobber (reg:CC CC_REGNUM)) |
5009 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5010 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5011 | "TARGET_HARD_DFP |
35dd9a0e AK |
5012 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
5013 | { | |
5014 | HOST_WIDE_INT flags; | |
5015 | ||
5016 | flags = (PFPO_CONVERT | | |
5017 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5018 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5019 | ||
5020 | operands[2] = GEN_INT (flags); | |
5021 | }) | |
5022 | ||
5023 | ||
9db1d521 | 5024 | ;; |
fae778eb | 5025 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 5026 | ;; |
fae778eb | 5027 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
5028 | ; because of unpredictable Bits in Register for Halfword and Byte |
5029 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
5030 | ||
07893d4f UW |
5031 | ;; |
5032 | ;;- Add instructions. | |
5033 | ;; | |
5034 | ||
1c7b1b7e UW |
5035 | ; |
5036 | ; addti3 instruction pattern(s). | |
5037 | ; | |
5038 | ||
085261c8 AK |
5039 | (define_expand "addti3" |
5040 | [(parallel | |
5041 | [(set (match_operand:TI 0 "register_operand" "") | |
5042 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "") | |
5043 | (match_operand:TI 2 "general_operand" "") ) ) | |
5044 | (clobber (reg:CC CC_REGNUM))])] | |
5045 | "TARGET_ZARCH" | |
5046 | { | |
5047 | /* For z13 we have vaq which doesn't set CC. */ | |
5048 | if (TARGET_VX) | |
5049 | { | |
5050 | emit_insn (gen_rtx_SET (operands[0], | |
5051 | gen_rtx_PLUS (TImode, | |
5052 | copy_to_mode_reg (TImode, operands[1]), | |
5053 | copy_to_mode_reg (TImode, operands[2])))); | |
5054 | DONE; | |
5055 | } | |
5056 | }) | |
5057 | ||
5058 | (define_insn_and_split "*addti3" | |
5059 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
1c7b1b7e | 5060 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
085261c8 | 5061 | (match_operand:TI 2 "general_operand" "do") ) ) |
ae156f85 | 5062 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5063 | "TARGET_ZARCH" |
1c7b1b7e UW |
5064 | "#" |
5065 | "&& reload_completed" | |
5066 | [(parallel | |
ae156f85 | 5067 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
5068 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
5069 | (match_dup 7))) | |
5070 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
5071 | (parallel | |
a94a76a7 UW |
5072 | [(set (match_dup 3) (plus:DI |
5073 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5074 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5075 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
5076 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5077 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5078 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5079 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5080 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5081 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5082 | [(set_attr "op_type" "*") | |
5083 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 5084 | |
07893d4f UW |
5085 | ; |
5086 | ; adddi3 instruction pattern(s). | |
5087 | ; | |
5088 | ||
3298c037 AK |
5089 | (define_expand "adddi3" |
5090 | [(parallel | |
963fc8d0 | 5091 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
5092 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
5093 | (match_operand:DI 2 "general_operand" ""))) | |
5094 | (clobber (reg:CC CC_REGNUM))])] | |
5095 | "" | |
5096 | "") | |
5097 | ||
07893d4f UW |
5098 | (define_insn "*adddi3_sign" |
5099 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 5100 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 5101 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5102 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5103 | "TARGET_ZARCH" |
07893d4f | 5104 | "@ |
d40c829f UW |
5105 | agfr\t%0,%2 |
5106 | agf\t%0,%2" | |
65b1d8ea AK |
5107 | [(set_attr "op_type" "RRE,RXY") |
5108 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
07893d4f UW |
5109 | |
5110 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 5111 | [(set (reg CC_REGNUM) |
fb492564 | 5112 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
5113 | (match_operand:DI 1 "register_operand" "0,0")) |
5114 | (const_int 0))) | |
5115 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5116 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
9602b6a1 | 5117 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5118 | "@ |
d40c829f UW |
5119 | algfr\t%0,%2 |
5120 | algf\t%0,%2" | |
9381e3f1 WG |
5121 | [(set_attr "op_type" "RRE,RXY") |
5122 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5123 | |
5124 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 5125 | [(set (reg CC_REGNUM) |
fb492564 | 5126 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
5127 | (match_operand:DI 1 "register_operand" "0,0")) |
5128 | (const_int 0))) | |
5129 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5130 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5131 | "@ |
d40c829f UW |
5132 | algfr\t%0,%2 |
5133 | algf\t%0,%2" | |
9381e3f1 WG |
5134 | [(set_attr "op_type" "RRE,RXY") |
5135 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5136 | |
5137 | (define_insn "*adddi3_zero" | |
5138 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 5139 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 5140 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5141 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5142 | "TARGET_ZARCH" |
07893d4f | 5143 | "@ |
d40c829f UW |
5144 | algfr\t%0,%2 |
5145 | algf\t%0,%2" | |
9381e3f1 WG |
5146 | [(set_attr "op_type" "RRE,RXY") |
5147 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 5148 | |
e69166de | 5149 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 5150 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
5151 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
5152 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5153 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5154 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
5155 | "#" |
5156 | "&& reload_completed" | |
5157 | [(parallel | |
ae156f85 | 5158 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
5159 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5160 | (match_dup 7))) | |
5161 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5162 | (parallel | |
a94a76a7 UW |
5163 | [(set (match_dup 3) (plus:SI |
5164 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5165 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5166 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
5167 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5168 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5169 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5170 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5171 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 5172 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 5173 | |
07893d4f | 5174 | (define_insn_and_split "*adddi3_31" |
963fc8d0 | 5175 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
96fd3851 | 5176 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 5177 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 5178 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 5179 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
5180 | "#" |
5181 | "&& reload_completed" | |
5182 | [(parallel | |
5183 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 5184 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5185 | (parallel |
ae156f85 | 5186 | [(set (reg:CCL1 CC_REGNUM) |
07893d4f UW |
5187 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5188 | (match_dup 7))) | |
5189 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5190 | (set (pc) | |
ae156f85 | 5191 | (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) |
07893d4f UW |
5192 | (pc) |
5193 | (label_ref (match_dup 9)))) | |
5194 | (parallel | |
5195 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
ae156f85 | 5196 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5197 | (match_dup 9)] |
97c6f7ad UW |
5198 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5199 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5200 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5201 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5202 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
5203 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 5204 | operands[9] = gen_label_rtx ();") |
9db1d521 | 5205 | |
3298c037 AK |
5206 | ; |
5207 | ; addsi3 instruction pattern(s). | |
5208 | ; | |
5209 | ||
5210 | (define_expand "addsi3" | |
07893d4f | 5211 | [(parallel |
963fc8d0 | 5212 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
5213 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
5214 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 5215 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5216 | "" |
07893d4f | 5217 | "") |
9db1d521 | 5218 | |
3298c037 AK |
5219 | (define_insn "*addsi3_sign" |
5220 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5221 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5222 | (match_operand:SI 1 "register_operand" "0,0"))) | |
5223 | (clobber (reg:CC CC_REGNUM))] | |
5224 | "" | |
5225 | "@ | |
5226 | ah\t%0,%2 | |
5227 | ahy\t%0,%2" | |
65b1d8ea AK |
5228 | [(set_attr "op_type" "RX,RXY") |
5229 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
3298c037 | 5230 | |
9db1d521 | 5231 | ; |
3298c037 | 5232 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 5233 | ; |
9db1d521 | 5234 | |
65b1d8ea | 5235 | ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 5236 | (define_insn "*add<mode>3" |
65b1d8ea AK |
5237 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS") |
5238 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0") | |
5239 | (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) ) | |
3298c037 AK |
5240 | (clobber (reg:CC CC_REGNUM))] |
5241 | "" | |
ec24698e | 5242 | "@ |
3298c037 | 5243 | a<g>r\t%0,%2 |
65b1d8ea | 5244 | a<g>rk\t%0,%1,%2 |
3298c037 | 5245 | a<g>hi\t%0,%h2 |
65b1d8ea | 5246 | a<g>hik\t%0,%1,%h2 |
3298c037 AK |
5247 | al<g>fi\t%0,%2 |
5248 | sl<g>fi\t%0,%n2 | |
5249 | a<g>\t%0,%2 | |
963fc8d0 AK |
5250 | a<y>\t%0,%2 |
5251 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
5252 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") |
5253 | (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10") | |
5254 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, | |
5255 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
0a3bdf9d | 5256 | |
65b1d8ea | 5257 | ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik |
3298c037 | 5258 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 5259 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5260 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5261 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5262 | (match_dup 1))) |
65b1d8ea | 5263 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") |
3298c037 | 5264 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5265 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5266 | "@ |
3298c037 | 5267 | al<g>r\t%0,%2 |
65b1d8ea | 5268 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5269 | al<g>fi\t%0,%2 |
5270 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5271 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5272 | al<g>\t%0,%2 |
963fc8d0 AK |
5273 | al<y>\t%0,%2 |
5274 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
5275 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
5276 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
5277 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, | |
5278 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5279 | |
65b1d8ea | 5280 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5281 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 5282 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5283 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5284 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5285 | (match_dup 1))) |
65b1d8ea | 5286 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5287 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5288 | "@ |
3298c037 | 5289 | al<g>r\t%0,%2 |
65b1d8ea | 5290 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5291 | al<g>\t%0,%2 |
5292 | al<y>\t%0,%2" | |
65b1d8ea AK |
5293 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5294 | (set_attr "cpu_facility" "*,z196,*,*") | |
5295 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5296 | |
65b1d8ea | 5297 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5298 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 5299 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5300 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") |
5301 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) | |
07893d4f | 5302 | (match_dup 2))) |
65b1d8ea | 5303 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") |
3298c037 | 5304 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5305 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5306 | "@ |
3298c037 | 5307 | al<g>r\t%0,%2 |
65b1d8ea | 5308 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5309 | al<g>fi\t%0,%2 |
5310 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5311 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5312 | al<g>\t%0,%2 |
963fc8d0 AK |
5313 | al<y>\t%0,%2 |
5314 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
5315 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
5316 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
5317 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, | |
5318 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5319 | |
65b1d8ea | 5320 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5321 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 5322 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5323 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5324 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5325 | (match_dup 2))) |
65b1d8ea | 5326 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5327 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5328 | "@ |
3298c037 | 5329 | al<g>r\t%0,%2 |
65b1d8ea | 5330 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5331 | al<g>\t%0,%2 |
5332 | al<y>\t%0,%2" | |
65b1d8ea AK |
5333 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5334 | (set_attr "cpu_facility" "*,z196,*,*") | |
5335 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5336 | |
65b1d8ea | 5337 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5338 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5339 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5340 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") |
5341 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) | |
9db1d521 | 5342 | (const_int 0))) |
65b1d8ea | 5343 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") |
3298c037 | 5344 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5345 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5346 | "@ |
3298c037 | 5347 | al<g>r\t%0,%2 |
65b1d8ea | 5348 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5349 | al<g>fi\t%0,%2 |
5350 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5351 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5352 | al<g>\t%0,%2 |
963fc8d0 AK |
5353 | al<y>\t%0,%2 |
5354 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
5355 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
5356 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
5357 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, | |
5358 | *,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5359 | |
65b1d8ea | 5360 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5361 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5362 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5363 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5364 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5365 | (const_int 0))) |
65b1d8ea | 5366 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5367 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5368 | "@ |
3298c037 | 5369 | al<g>r\t%0,%2 |
65b1d8ea | 5370 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5371 | al<g>\t%0,%2 |
5372 | al<y>\t%0,%2" | |
65b1d8ea AK |
5373 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5374 | (set_attr "cpu_facility" "*,z196,*,*") | |
5375 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5376 | |
65b1d8ea | 5377 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5378 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 5379 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5380 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5381 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) | |
5382 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
3298c037 | 5383 | "s390_match_ccmode(insn, CCLmode)" |
d3632d41 | 5384 | "@ |
3298c037 | 5385 | al<g>r\t%0,%2 |
65b1d8ea | 5386 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5387 | al<g>\t%0,%2 |
5388 | al<y>\t%0,%2" | |
65b1d8ea AK |
5389 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5390 | (set_attr "cpu_facility" "*,z196,*,*") | |
5391 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5392 | |
963fc8d0 | 5393 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
5394 | (define_insn "*add<mode>3_imm_cc" |
5395 | [(set (reg CC_REGNUM) | |
65b1d8ea AK |
5396 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") |
5397 | (match_operand:GPR 2 "const_int_operand" " K, K,Os, C")) | |
3298c037 | 5398 | (const_int 0))) |
65b1d8ea | 5399 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS") |
3298c037 AK |
5400 | (plus:GPR (match_dup 1) (match_dup 2)))] |
5401 | "s390_match_ccmode (insn, CCAmode) | |
5402 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
2542ef05 RH |
5403 | || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
5404 | /* Avoid INT32_MIN on 32 bit. */ | |
5405 | && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" | |
9db1d521 | 5406 | "@ |
3298c037 | 5407 | a<g>hi\t%0,%h2 |
65b1d8ea | 5408 | a<g>hik\t%0,%1,%h2 |
963fc8d0 AK |
5409 | a<g>fi\t%0,%2 |
5410 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
5411 | [(set_attr "op_type" "RI,RIE,RIL,SIY") |
5412 | (set_attr "cpu_facility" "*,z196,extimm,z10") | |
5413 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5414 | |
9db1d521 | 5415 | ; |
609e7e80 | 5416 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5417 | ; |
5418 | ||
609e7e80 | 5419 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
6e5b5de8 | 5420 | ; FIXME: wfadb does not clobber cc |
142cd70f | 5421 | (define_insn "add<mode>3" |
6e5b5de8 AK |
5422 | [(set (match_operand:FP 0 "register_operand" "=f, f,<vf>") |
5423 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>, 0,<v0>") | |
5424 | (match_operand:FP 2 "general_operand" "f,<Rf>,<vf>"))) | |
ae156f85 | 5425 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5426 | "TARGET_HARD_FLOAT" |
9db1d521 | 5427 | "@ |
609e7e80 | 5428 | a<xde><bt>r\t%0,<op1>%2 |
6e5b5de8 AK |
5429 | a<xde>b\t%0,%2 |
5430 | wfadb\t%v0,%v1,%v2" | |
5431 | [(set_attr "op_type" "<RRer>,RXE,VRR") | |
5432 | (set_attr "type" "fsimp<mode>") | |
5433 | (set_attr "cpu_facility" "*,*,vec")]) | |
9db1d521 | 5434 | |
609e7e80 | 5435 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5436 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5437 | [(set (reg CC_REGNUM) |
609e7e80 AK |
5438 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") |
5439 | (match_operand:FP 2 "general_operand" " f,<Rf>")) | |
5440 | (match_operand:FP 3 "const0_operand" ""))) | |
5441 | (set (match_operand:FP 0 "register_operand" "=f,f") | |
5442 | (plus:FP (match_dup 1) (match_dup 2)))] | |
142cd70f | 5443 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5444 | "@ |
609e7e80 | 5445 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5446 | a<xde>b\t%0,%2" |
609e7e80 | 5447 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5448 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 5449 | |
609e7e80 | 5450 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5451 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5452 | [(set (reg CC_REGNUM) |
609e7e80 AK |
5453 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") |
5454 | (match_operand:FP 2 "general_operand" " f,<Rf>")) | |
5455 | (match_operand:FP 3 "const0_operand" ""))) | |
5456 | (clobber (match_scratch:FP 0 "=f,f"))] | |
142cd70f | 5457 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5458 | "@ |
609e7e80 | 5459 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5460 | a<xde>b\t%0,%2" |
609e7e80 | 5461 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5462 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 5463 | |
72a4ddf2 AK |
5464 | ; |
5465 | ; Pointer add instruction patterns | |
5466 | ; | |
5467 | ||
5468 | ; This will match "*la_64" | |
5469 | (define_expand "addptrdi3" | |
5470 | [(set (match_operand:DI 0 "register_operand" "") | |
5471 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
5472 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
5473 | "TARGET_64BIT" | |
5474 | { | |
72a4ddf2 AK |
5475 | if (GET_CODE (operands[2]) == CONST_INT) |
5476 | { | |
357ddc7d TV |
5477 | HOST_WIDE_INT c = INTVAL (operands[2]); |
5478 | ||
72a4ddf2 AK |
5479 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
5480 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
5481 | { | |
5482 | operands[2] = force_const_mem (DImode, operands[2]); | |
5483 | operands[2] = force_reg (DImode, operands[2]); | |
5484 | } | |
5485 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
5486 | operands[2] = force_reg (DImode, operands[2]); | |
5487 | } | |
5488 | }) | |
5489 | ||
5490 | ; For 31 bit we have to prevent the generated pattern from matching | |
5491 | ; normal ADDs since la only does a 31 bit add. This is supposed to | |
5492 | ; match "force_la_31". | |
5493 | (define_expand "addptrsi3" | |
5494 | [(parallel | |
5495 | [(set (match_operand:SI 0 "register_operand" "") | |
5496 | (plus:SI (match_operand:SI 1 "register_operand" "") | |
5497 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
5498 | (use (const_int 0))])] | |
5499 | "!TARGET_64BIT" | |
5500 | { | |
72a4ddf2 AK |
5501 | if (GET_CODE (operands[2]) == CONST_INT) |
5502 | { | |
357ddc7d TV |
5503 | HOST_WIDE_INT c = INTVAL (operands[2]); |
5504 | ||
72a4ddf2 AK |
5505 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
5506 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
5507 | { | |
5508 | operands[2] = force_const_mem (SImode, operands[2]); | |
5509 | operands[2] = force_reg (SImode, operands[2]); | |
5510 | } | |
5511 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
5512 | operands[2] = force_reg (SImode, operands[2]); | |
5513 | } | |
5514 | }) | |
9db1d521 HP |
5515 | |
5516 | ;; | |
5517 | ;;- Subtract instructions. | |
5518 | ;; | |
5519 | ||
1c7b1b7e UW |
5520 | ; |
5521 | ; subti3 instruction pattern(s). | |
5522 | ; | |
5523 | ||
085261c8 AK |
5524 | (define_expand "subti3" |
5525 | [(parallel | |
5526 | [(set (match_operand:TI 0 "register_operand" "") | |
5527 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
5528 | (match_operand:TI 2 "general_operand" "") ) ) | |
5529 | (clobber (reg:CC CC_REGNUM))])] | |
5530 | "TARGET_ZARCH" | |
5531 | { | |
5532 | /* For z13 we have vaq which doesn't set CC. */ | |
5533 | if (TARGET_VX) | |
5534 | { | |
5535 | emit_insn (gen_rtx_SET (operands[0], | |
5536 | gen_rtx_MINUS (TImode, | |
5537 | operands[1], | |
5538 | copy_to_mode_reg (TImode, operands[2])))); | |
5539 | DONE; | |
5540 | } | |
5541 | }) | |
5542 | ||
5543 | (define_insn_and_split "*subti3" | |
5544 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
5545 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
5546 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 5547 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5548 | "TARGET_ZARCH" |
1c7b1b7e UW |
5549 | "#" |
5550 | "&& reload_completed" | |
5551 | [(parallel | |
ae156f85 | 5552 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
5553 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
5554 | (match_dup 7))) | |
5555 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
5556 | (parallel | |
5557 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
5558 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
5559 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
5560 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5561 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5562 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5563 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5564 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5565 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5566 | [(set_attr "op_type" "*") | |
5567 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 5568 | |
9db1d521 HP |
5569 | ; |
5570 | ; subdi3 instruction pattern(s). | |
5571 | ; | |
5572 | ||
3298c037 AK |
5573 | (define_expand "subdi3" |
5574 | [(parallel | |
5575 | [(set (match_operand:DI 0 "register_operand" "") | |
5576 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
5577 | (match_operand:DI 2 "general_operand" ""))) | |
5578 | (clobber (reg:CC CC_REGNUM))])] | |
5579 | "" | |
5580 | "") | |
5581 | ||
07893d4f UW |
5582 | (define_insn "*subdi3_sign" |
5583 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5584 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 5585 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 5586 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5587 | "TARGET_ZARCH" |
07893d4f | 5588 | "@ |
d40c829f UW |
5589 | sgfr\t%0,%2 |
5590 | sgf\t%0,%2" | |
9381e3f1 | 5591 | [(set_attr "op_type" "RRE,RXY") |
65b1d8ea AK |
5592 | (set_attr "z10prop" "z10_c,*") |
5593 | (set_attr "z196prop" "z196_cracked")]) | |
07893d4f UW |
5594 | |
5595 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 5596 | [(set (reg CC_REGNUM) |
07893d4f | 5597 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 5598 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
5599 | (const_int 0))) |
5600 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5601 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
9602b6a1 | 5602 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5603 | "@ |
d40c829f UW |
5604 | slgfr\t%0,%2 |
5605 | slgf\t%0,%2" | |
9381e3f1 WG |
5606 | [(set_attr "op_type" "RRE,RXY") |
5607 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
5608 | |
5609 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 5610 | [(set (reg CC_REGNUM) |
07893d4f | 5611 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 5612 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
5613 | (const_int 0))) |
5614 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5615 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5616 | "@ |
d40c829f UW |
5617 | slgfr\t%0,%2 |
5618 | slgf\t%0,%2" | |
9381e3f1 WG |
5619 | [(set_attr "op_type" "RRE,RXY") |
5620 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
5621 | |
5622 | (define_insn "*subdi3_zero" | |
5623 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5624 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 5625 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 5626 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5627 | "TARGET_ZARCH" |
07893d4f | 5628 | "@ |
d40c829f UW |
5629 | slgfr\t%0,%2 |
5630 | slgf\t%0,%2" | |
9381e3f1 WG |
5631 | [(set_attr "op_type" "RRE,RXY") |
5632 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 5633 | |
e69166de UW |
5634 | (define_insn_and_split "*subdi3_31z" |
5635 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
5636 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
5637 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5638 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5639 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
5640 | "#" |
5641 | "&& reload_completed" | |
5642 | [(parallel | |
ae156f85 | 5643 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
5644 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
5645 | (match_dup 7))) | |
5646 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
5647 | (parallel | |
5648 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
5649 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
5650 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
5651 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5652 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5653 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5654 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5655 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 5656 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 5657 | |
07893d4f UW |
5658 | (define_insn_and_split "*subdi3_31" |
5659 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
5660 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 5661 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 5662 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 5663 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
5664 | "#" |
5665 | "&& reload_completed" | |
5666 | [(parallel | |
5667 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 5668 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5669 | (parallel |
ae156f85 | 5670 | [(set (reg:CCL2 CC_REGNUM) |
07893d4f UW |
5671 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
5672 | (match_dup 7))) | |
5673 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
5674 | (set (pc) | |
ae156f85 | 5675 | (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) |
07893d4f UW |
5676 | (pc) |
5677 | (label_ref (match_dup 9)))) | |
5678 | (parallel | |
5679 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
ae156f85 | 5680 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5681 | (match_dup 9)] |
97c6f7ad UW |
5682 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5683 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5684 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5685 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5686 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
5687 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 5688 | operands[9] = gen_label_rtx ();") |
07893d4f | 5689 | |
3298c037 AK |
5690 | ; |
5691 | ; subsi3 instruction pattern(s). | |
5692 | ; | |
5693 | ||
5694 | (define_expand "subsi3" | |
07893d4f | 5695 | [(parallel |
3298c037 AK |
5696 | [(set (match_operand:SI 0 "register_operand" "") |
5697 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
5698 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 5699 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5700 | "" |
07893d4f | 5701 | "") |
9db1d521 | 5702 | |
3298c037 AK |
5703 | (define_insn "*subsi3_sign" |
5704 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5705 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
5706 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
5707 | (clobber (reg:CC CC_REGNUM))] | |
5708 | "" | |
5709 | "@ | |
5710 | sh\t%0,%2 | |
5711 | shy\t%0,%2" | |
65b1d8ea AK |
5712 | [(set_attr "op_type" "RX,RXY") |
5713 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
3298c037 | 5714 | |
9db1d521 | 5715 | ; |
3298c037 | 5716 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
5717 | ; |
5718 | ||
65b1d8ea | 5719 | ; sr, s, sy, sgr, sg, srk, sgrk |
3298c037 | 5720 | (define_insn "*sub<mode>3" |
65b1d8ea AK |
5721 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
5722 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") | |
5723 | (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) | |
3298c037 AK |
5724 | (clobber (reg:CC CC_REGNUM))] |
5725 | "" | |
5726 | "@ | |
5727 | s<g>r\t%0,%2 | |
65b1d8ea | 5728 | s<g>rk\t%0,%1,%2 |
3298c037 AK |
5729 | s<g>\t%0,%2 |
5730 | s<y>\t%0,%2" | |
65b1d8ea AK |
5731 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5732 | (set_attr "cpu_facility" "*,z196,*,*") | |
5733 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
3298c037 | 5734 | |
65b1d8ea | 5735 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5736 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 5737 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5738 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5739 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5740 | (match_dup 1))) |
65b1d8ea | 5741 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 5742 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 5743 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 5744 | "@ |
3298c037 | 5745 | sl<g>r\t%0,%2 |
65b1d8ea | 5746 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5747 | sl<g>\t%0,%2 |
5748 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5749 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5750 | (set_attr "cpu_facility" "*,z196,*,*") | |
5751 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5752 | |
65b1d8ea | 5753 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5754 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 5755 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5756 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5757 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5758 | (match_dup 1))) |
65b1d8ea | 5759 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 5760 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 5761 | "@ |
3298c037 | 5762 | sl<g>r\t%0,%2 |
65b1d8ea | 5763 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5764 | sl<g>\t%0,%2 |
5765 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5766 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5767 | (set_attr "cpu_facility" "*,z196,*,*") | |
5768 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5769 | |
65b1d8ea | 5770 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5771 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 5772 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5773 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5774 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5775 | (const_int 0))) |
65b1d8ea | 5776 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 5777 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 5778 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5779 | "@ |
3298c037 | 5780 | sl<g>r\t%0,%2 |
65b1d8ea | 5781 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5782 | sl<g>\t%0,%2 |
5783 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5784 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5785 | (set_attr "cpu_facility" "*,z196,*,*") | |
5786 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5787 | |
65b1d8ea | 5788 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5789 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 5790 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5791 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5792 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
5793 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
3298c037 | 5794 | (minus:GPR (match_dup 1) (match_dup 2)))] |
5d880bd2 UW |
5795 | "s390_match_ccmode (insn, CCL3mode)" |
5796 | "@ | |
3298c037 | 5797 | sl<g>r\t%0,%2 |
65b1d8ea | 5798 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5799 | sl<g>\t%0,%2 |
5800 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5801 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5802 | (set_attr "cpu_facility" "*,z196,*,*") | |
5803 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
5d880bd2 | 5804 | |
65b1d8ea | 5805 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5806 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 5807 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5808 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5809 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5810 | (const_int 0))) |
65b1d8ea | 5811 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 5812 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5813 | "@ |
3298c037 | 5814 | sl<g>r\t%0,%2 |
65b1d8ea | 5815 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5816 | sl<g>\t%0,%2 |
5817 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5818 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5819 | (set_attr "cpu_facility" "*,z196,*,*") | |
5820 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9381e3f1 | 5821 | |
9db1d521 | 5822 | |
65b1d8ea | 5823 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5824 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 5825 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5826 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5827 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
5828 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
5d880bd2 UW |
5829 | "s390_match_ccmode (insn, CCL3mode)" |
5830 | "@ | |
3298c037 | 5831 | sl<g>r\t%0,%2 |
65b1d8ea | 5832 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5833 | sl<g>\t%0,%2 |
5834 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5835 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5836 | (set_attr "cpu_facility" "*,z196,*,*") | |
5837 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9381e3f1 | 5838 | |
9db1d521 HP |
5839 | |
5840 | ; | |
609e7e80 | 5841 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5842 | ; |
5843 | ||
d46f24b6 | 5844 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 5845 | (define_insn "sub<mode>3" |
6e5b5de8 AK |
5846 | [(set (match_operand:FP 0 "register_operand" "=f, f,<vf>") |
5847 | (minus:FP (match_operand:FP 1 "register_operand" "<f0>, 0,<v0>") | |
5848 | (match_operand:FP 2 "general_operand" "f,<Rf>,<vf>"))) | |
ae156f85 | 5849 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5850 | "TARGET_HARD_FLOAT" |
9db1d521 | 5851 | "@ |
609e7e80 | 5852 | s<xde><bt>r\t%0,<op1>%2 |
6e5b5de8 AK |
5853 | s<xde>b\t%0,%2 |
5854 | wfsdb\t%v0,%v1,%v2" | |
5855 | [(set_attr "op_type" "<RRer>,RXE,VRR") | |
5856 | (set_attr "type" "fsimp<mode>") | |
5857 | (set_attr "cpu_facility" "*,*,vec")]) | |
9db1d521 | 5858 | |
d46f24b6 | 5859 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 5860 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 5861 | [(set (reg CC_REGNUM) |
609e7e80 | 5862 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") |
142cd70f | 5863 | (match_operand:FP 2 "general_operand" "f,<Rf>")) |
609e7e80 AK |
5864 | (match_operand:FP 3 "const0_operand" ""))) |
5865 | (set (match_operand:FP 0 "register_operand" "=f,f") | |
5866 | (minus:FP (match_dup 1) (match_dup 2)))] | |
142cd70f | 5867 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5868 | "@ |
609e7e80 | 5869 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5870 | s<xde>b\t%0,%2" |
609e7e80 | 5871 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5872 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 5873 | |
d46f24b6 | 5874 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 5875 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 5876 | [(set (reg CC_REGNUM) |
609e7e80 AK |
5877 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") |
5878 | (match_operand:FP 2 "general_operand" "f,<Rf>")) | |
5879 | (match_operand:FP 3 "const0_operand" ""))) | |
5880 | (clobber (match_scratch:FP 0 "=f,f"))] | |
142cd70f | 5881 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5882 | "@ |
609e7e80 | 5883 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5884 | s<xde>b\t%0,%2" |
609e7e80 | 5885 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5886 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 5887 | |
9db1d521 | 5888 | |
e69166de UW |
5889 | ;; |
5890 | ;;- Conditional add/subtract instructions. | |
5891 | ;; | |
5892 | ||
5893 | ; | |
9a91a21f | 5894 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
5895 | ; |
5896 | ||
a996720c UW |
5897 | ; the following 4 patterns are used when the result of an add with |
5898 | ; carry is checked for an overflow condition | |
5899 | ||
5900 | ; op1 + op2 + c < op1 | |
5901 | ||
5902 | ; alcr, alc, alcgr, alcg | |
5903 | (define_insn "*add<mode>3_alc_carry1_cc" | |
5904 | [(set (reg CC_REGNUM) | |
5905 | (compare | |
5906 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5907 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5908 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5909 | (match_dup 1))) |
5910 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
5911 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
5912 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5913 | "@ | |
5914 | alc<g>r\t%0,%2 | |
5915 | alc<g>\t%0,%2" | |
65b1d8ea AK |
5916 | [(set_attr "op_type" "RRE,RXY") |
5917 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
5918 | |
5919 | ; alcr, alc, alcgr, alcg | |
5920 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
5921 | [(set (reg CC_REGNUM) | |
5922 | (compare | |
5923 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5924 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5925 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5926 | (match_dup 1))) |
5927 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
5928 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5929 | "@ | |
5930 | alc<g>r\t%0,%2 | |
5931 | alc<g>\t%0,%2" | |
65b1d8ea AK |
5932 | [(set_attr "op_type" "RRE,RXY") |
5933 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
5934 | |
5935 | ; op1 + op2 + c < op2 | |
5936 | ||
5937 | ; alcr, alc, alcgr, alcg | |
5938 | (define_insn "*add<mode>3_alc_carry2_cc" | |
5939 | [(set (reg CC_REGNUM) | |
5940 | (compare | |
5941 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5942 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5943 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5944 | (match_dup 2))) |
5945 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
5946 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
5947 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5948 | "@ | |
5949 | alc<g>r\t%0,%2 | |
5950 | alc<g>\t%0,%2" | |
5951 | [(set_attr "op_type" "RRE,RXY")]) | |
5952 | ||
5953 | ; alcr, alc, alcgr, alcg | |
5954 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
5955 | [(set (reg CC_REGNUM) | |
5956 | (compare | |
5957 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5958 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5959 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5960 | (match_dup 2))) |
5961 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
5962 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5963 | "@ | |
5964 | alc<g>r\t%0,%2 | |
5965 | alc<g>\t%0,%2" | |
5966 | [(set_attr "op_type" "RRE,RXY")]) | |
5967 | ||
43a09b63 | 5968 | ; alcr, alc, alcgr, alcg |
9a91a21f | 5969 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 5970 | [(set (reg CC_REGNUM) |
e69166de | 5971 | (compare |
a94a76a7 UW |
5972 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
5973 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5974 | (match_operand:GPR 2 "general_operand" "d,RT")) |
e69166de | 5975 | (const_int 0))) |
9a91a21f | 5976 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 5977 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
2f7e5a0d | 5978 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 5979 | "@ |
9a91a21f AS |
5980 | alc<g>r\t%0,%2 |
5981 | alc<g>\t%0,%2" | |
e69166de UW |
5982 | [(set_attr "op_type" "RRE,RXY")]) |
5983 | ||
43a09b63 | 5984 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
5985 | (define_insn "*add<mode>3_alc" |
5986 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
5987 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
5988 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5989 | (match_operand:GPR 2 "general_operand" "d,RT"))) |
ae156f85 | 5990 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 5991 | "TARGET_CPU_ZARCH" |
e69166de | 5992 | "@ |
9a91a21f AS |
5993 | alc<g>r\t%0,%2 |
5994 | alc<g>\t%0,%2" | |
e69166de UW |
5995 | [(set_attr "op_type" "RRE,RXY")]) |
5996 | ||
43a09b63 | 5997 | ; slbr, slb, slbgr, slbg |
9a91a21f | 5998 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 5999 | [(set (reg CC_REGNUM) |
e69166de | 6000 | (compare |
9a91a21f | 6001 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
fb492564 | 6002 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 6003 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 6004 | (const_int 0))) |
9a91a21f AS |
6005 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
6006 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 6007 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 6008 | "@ |
9a91a21f AS |
6009 | slb<g>r\t%0,%2 |
6010 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6011 | [(set_attr "op_type" "RRE,RXY") |
6012 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6013 | |
43a09b63 | 6014 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
6015 | (define_insn "*sub<mode>3_slb" |
6016 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
6017 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
fb492564 | 6018 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 6019 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 6020 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 6021 | "TARGET_CPU_ZARCH" |
e69166de | 6022 | "@ |
9a91a21f AS |
6023 | slb<g>r\t%0,%2 |
6024 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6025 | [(set_attr "op_type" "RRE,RXY") |
6026 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6027 | |
9a91a21f AS |
6028 | (define_expand "add<mode>cc" |
6029 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 6030 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
6031 | (match_operand:GPR 2 "register_operand" "") |
6032 | (match_operand:GPR 3 "const_int_operand" "")] | |
5d880bd2 | 6033 | "TARGET_CPU_ZARCH" |
9381e3f1 | 6034 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
f90b7a5a | 6035 | XEXP (operands[1], 0), XEXP (operands[1], 1), |
9381e3f1 | 6036 | operands[0], operands[2], |
5d880bd2 UW |
6037 | operands[3])) FAIL; DONE;") |
6038 | ||
6039 | ; | |
6040 | ; scond instruction pattern(s). | |
6041 | ; | |
6042 | ||
9a91a21f AS |
6043 | (define_insn_and_split "*scond<mode>" |
6044 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6045 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 6046 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
6047 | "TARGET_CPU_ZARCH" |
6048 | "#" | |
6049 | "&& reload_completed" | |
6050 | [(set (match_dup 0) (const_int 0)) | |
6051 | (parallel | |
a94a76a7 UW |
6052 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
6053 | (match_dup 0))) | |
ae156f85 | 6054 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6055 | "") |
5d880bd2 | 6056 | |
9a91a21f AS |
6057 | (define_insn_and_split "*scond<mode>_neg" |
6058 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6059 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 6060 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
6061 | "TARGET_CPU_ZARCH" |
6062 | "#" | |
6063 | "&& reload_completed" | |
6064 | [(set (match_dup 0) (const_int 0)) | |
6065 | (parallel | |
9a91a21f AS |
6066 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
6067 | (match_dup 1))) | |
ae156f85 | 6068 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 6069 | (parallel |
9a91a21f | 6070 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 6071 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6072 | "") |
5d880bd2 | 6073 | |
5d880bd2 | 6074 | |
f90b7a5a | 6075 | (define_expand "cstore<mode>4" |
9a91a21f | 6076 | [(set (match_operand:SI 0 "register_operand" "") |
f90b7a5a PB |
6077 | (match_operator:SI 1 "s390_scond_operator" |
6078 | [(match_operand:GPR 2 "register_operand" "") | |
6079 | (match_operand:GPR 3 "general_operand" "")]))] | |
5d880bd2 | 6080 | "TARGET_CPU_ZARCH" |
f90b7a5a | 6081 | "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], |
5d880bd2 UW |
6082 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
6083 | ||
f90b7a5a | 6084 | (define_expand "cstorecc4" |
69950452 | 6085 | [(parallel |
f90b7a5a PB |
6086 | [(set (match_operand:SI 0 "register_operand" "") |
6087 | (match_operator:SI 1 "s390_eqne_operator" | |
6088 | [(match_operand:CCZ1 2 "register_operand") | |
6089 | (match_operand 3 "const0_operand")])) | |
69950452 AS |
6090 | (clobber (reg:CC CC_REGNUM))])] |
6091 | "" | |
f90b7a5a PB |
6092 | "emit_insn (gen_sne (operands[0], operands[2])); |
6093 | if (GET_CODE (operands[1]) == EQ) | |
6094 | emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); | |
6095 | DONE;") | |
69950452 | 6096 | |
f90b7a5a | 6097 | (define_insn_and_split "sne" |
69950452 | 6098 | [(set (match_operand:SI 0 "register_operand" "=d") |
9381e3f1 | 6099 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
6100 | (const_int 0))) |
6101 | (clobber (reg:CC CC_REGNUM))] | |
6102 | "" | |
6103 | "#" | |
6104 | "reload_completed" | |
6105 | [(parallel | |
6106 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
6107 | (clobber (reg:CC CC_REGNUM))])]) | |
6108 | ||
e69166de | 6109 | |
65b1d8ea AK |
6110 | ;; |
6111 | ;; - Conditional move instructions (introduced with z196) | |
6112 | ;; | |
6113 | ||
6114 | (define_expand "mov<mode>cc" | |
6115 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
6116 | (if_then_else:GPR (match_operand 1 "comparison_operator" "") | |
6117 | (match_operand:GPR 2 "nonimmediate_operand" "") | |
6118 | (match_operand:GPR 3 "nonimmediate_operand" "")))] | |
6119 | "TARGET_Z196" | |
7477de01 AK |
6120 | { |
6121 | /* Emit the comparison insn in case we do not already have a comparison result. */ | |
6122 | if (!s390_comparison (operands[1], VOIDmode)) | |
6123 | operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
6124 | XEXP (operands[1], 0), | |
6125 | XEXP (operands[1], 1)); | |
6126 | }) | |
65b1d8ea | 6127 | |
27037b5f | 6128 | ; locr, loc, stoc, locgr, locg, stocg |
65b1d8ea AK |
6129 | (define_insn_and_split "*mov<mode>cc" |
6130 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d") | |
6131 | (if_then_else:GPR | |
6132 | (match_operator 1 "s390_comparison" | |
6133 | [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c") | |
5a3fe9b6 | 6134 | (match_operand 5 "const_int_operand" "")]) |
65b1d8ea AK |
6135 | (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS") |
6136 | (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))] | |
6137 | "TARGET_Z196" | |
6138 | "@ | |
6139 | loc<g>r%C1\t%0,%3 | |
6140 | loc<g>r%D1\t%0,%4 | |
a6510374 AK |
6141 | loc<g>%C1\t%0,%3 |
6142 | loc<g>%D1\t%0,%4 | |
6143 | stoc<g>%C1\t%3,%0 | |
6144 | stoc<g>%D1\t%4,%0 | |
65b1d8ea AK |
6145 | #" |
6146 | "&& reload_completed | |
6147 | && MEM_P (operands[3]) && MEM_P (operands[4])" | |
6148 | [(set (match_dup 0) | |
6149 | (if_then_else:GPR | |
6150 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
6151 | (match_dup 3) | |
6152 | (match_dup 0))) | |
6153 | (set (match_dup 0) | |
6154 | (if_then_else:GPR | |
6155 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
6156 | (match_dup 0) | |
6157 | (match_dup 4)))] | |
6158 | "" | |
6159 | [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")]) | |
6160 | ||
9db1d521 HP |
6161 | ;; |
6162 | ;;- Multiply instructions. | |
6163 | ;; | |
6164 | ||
4023fb28 UW |
6165 | ; |
6166 | ; muldi3 instruction pattern(s). | |
6167 | ; | |
9db1d521 | 6168 | |
07893d4f UW |
6169 | (define_insn "*muldi3_sign" |
6170 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
963fc8d0 | 6171 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 6172 | (match_operand:DI 1 "register_operand" "0,0")))] |
9602b6a1 | 6173 | "TARGET_ZARCH" |
07893d4f | 6174 | "@ |
d40c829f UW |
6175 | msgfr\t%0,%2 |
6176 | msgf\t%0,%2" | |
963fc8d0 AK |
6177 | [(set_attr "op_type" "RRE,RXY") |
6178 | (set_attr "type" "imuldi")]) | |
07893d4f | 6179 | |
4023fb28 | 6180 | (define_insn "muldi3" |
963fc8d0 AK |
6181 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") |
6182 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
6183 | (match_operand:DI 2 "general_operand" "d,K,RT,Os")))] | |
9602b6a1 | 6184 | "TARGET_ZARCH" |
9db1d521 | 6185 | "@ |
d40c829f UW |
6186 | msgr\t%0,%2 |
6187 | mghi\t%0,%h2 | |
963fc8d0 AK |
6188 | msg\t%0,%2 |
6189 | msgfi\t%0,%2" | |
6190 | [(set_attr "op_type" "RRE,RI,RXY,RIL") | |
6191 | (set_attr "type" "imuldi") | |
6192 | (set_attr "cpu_facility" "*,*,*,z10")]) | |
f2d3c02a | 6193 | |
9db1d521 HP |
6194 | ; |
6195 | ; mulsi3 instruction pattern(s). | |
6196 | ; | |
6197 | ||
f1e77d83 | 6198 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
6199 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6200 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
6201 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 6202 | "" |
963fc8d0 AK |
6203 | "@ |
6204 | mh\t%0,%2 | |
6205 | mhy\t%0,%2" | |
6206 | [(set_attr "op_type" "RX,RXY") | |
6207 | (set_attr "type" "imulhi") | |
6208 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 6209 | |
9db1d521 | 6210 | (define_insn "mulsi3" |
963fc8d0 AK |
6211 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
6212 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
6213 | (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))] | |
9db1d521 HP |
6214 | "" |
6215 | "@ | |
d40c829f UW |
6216 | msr\t%0,%2 |
6217 | mhi\t%0,%h2 | |
6218 | ms\t%0,%2 | |
963fc8d0 AK |
6219 | msy\t%0,%2 |
6220 | msfi\t%0,%2" | |
6221 | [(set_attr "op_type" "RRE,RI,RX,RXY,RIL") | |
6222 | (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi") | |
6223 | (set_attr "cpu_facility" "*,*,*,*,z10")]) | |
9db1d521 | 6224 | |
4023fb28 UW |
6225 | ; |
6226 | ; mulsidi3 instruction pattern(s). | |
6227 | ; | |
6228 | ||
f1e77d83 | 6229 | (define_insn "mulsidi3" |
963fc8d0 | 6230 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 6231 | (mult:DI (sign_extend:DI |
963fc8d0 | 6232 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 6233 | (sign_extend:DI |
963fc8d0 | 6234 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
9602b6a1 | 6235 | "!TARGET_ZARCH" |
f1e77d83 UW |
6236 | "@ |
6237 | mr\t%0,%2 | |
963fc8d0 AK |
6238 | m\t%0,%2 |
6239 | mfy\t%0,%2" | |
6240 | [(set_attr "op_type" "RR,RX,RXY") | |
6241 | (set_attr "type" "imulsi") | |
6242 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 6243 | |
f1e77d83 | 6244 | ; |
6e0d70c9 | 6245 | ; umul instruction pattern(s). |
f1e77d83 | 6246 | ; |
c7453384 | 6247 | |
6e0d70c9 AK |
6248 | ; mlr, ml, mlgr, mlg |
6249 | (define_insn "umul<dwh><mode>3" | |
6250 | [(set (match_operand:DW 0 "register_operand" "=d, d") | |
6251 | (mult:DW (zero_extend:DW | |
6252 | (match_operand:<DWH> 1 "register_operand" "%0, 0")) | |
6253 | (zero_extend:DW | |
6254 | (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))] | |
6255 | "TARGET_CPU_ZARCH" | |
f1e77d83 | 6256 | "@ |
6e0d70c9 AK |
6257 | ml<tg>r\t%0,%2 |
6258 | ml<tg>\t%0,%2" | |
f1e77d83 | 6259 | [(set_attr "op_type" "RRE,RXY") |
6e0d70c9 | 6260 | (set_attr "type" "imul<dwh>")]) |
c7453384 | 6261 | |
9db1d521 | 6262 | ; |
609e7e80 | 6263 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6264 | ; |
6265 | ||
9381e3f1 | 6266 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 6267 | (define_insn "mul<mode>3" |
6e5b5de8 AK |
6268 | [(set (match_operand:FP 0 "register_operand" "=f, f,<vf>") |
6269 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>, 0,<v0>") | |
6270 | (match_operand:FP 2 "general_operand" "f,<Rf>,<vf>")))] | |
142cd70f | 6271 | "TARGET_HARD_FLOAT" |
9db1d521 | 6272 | "@ |
609e7e80 | 6273 | m<xdee><bt>r\t%0,<op1>%2 |
6e5b5de8 AK |
6274 | m<xdee>b\t%0,%2 |
6275 | wfmdb\t%v0,%v1,%v2" | |
6276 | [(set_attr "op_type" "<RRer>,RXE,VRR") | |
6277 | (set_attr "type" "fmul<mode>") | |
6278 | (set_attr "cpu_facility" "*,*,vec")]) | |
9db1d521 | 6279 | |
9381e3f1 | 6280 | ; madbr, maebr, maxb, madb, maeb |
d7ecb504 | 6281 | (define_insn "fma<mode>4" |
6e5b5de8 AK |
6282 | [(set (match_operand:DSF 0 "register_operand" "=f,f,<vf>") |
6283 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,<vf>") | |
6284 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,<vf>") | |
6285 | (match_operand:DSF 3 "register_operand" "0,0,<v0>")))] | |
d7ecb504 | 6286 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6287 | "@ |
f61a2c7d | 6288 | ma<xde>br\t%0,%1,%2 |
6e5b5de8 AK |
6289 | ma<xde>b\t%0,%1,%2 |
6290 | wfmadb\t%v0,%v1,%v2,%v3" | |
6291 | [(set_attr "op_type" "RRE,RXE,VRR") | |
6292 | (set_attr "type" "fmadd<mode>") | |
6293 | (set_attr "cpu_facility" "*,*,vec")]) | |
a1b892b5 | 6294 | |
43a09b63 | 6295 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
d7ecb504 | 6296 | (define_insn "fms<mode>4" |
6e5b5de8 AK |
6297 | [(set (match_operand:DSF 0 "register_operand" "=f,f,<vf>") |
6298 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,<vf>") | |
6299 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,<vf>") | |
6300 | (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,<v0>"))))] | |
d7ecb504 | 6301 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6302 | "@ |
f61a2c7d | 6303 | ms<xde>br\t%0,%1,%2 |
6e5b5de8 AK |
6304 | ms<xde>b\t%0,%1,%2 |
6305 | wfmsdb\t%v0,%v1,%v2,%v3" | |
6306 | [(set_attr "op_type" "RRE,RXE,VRR") | |
6307 | (set_attr "type" "fmadd<mode>") | |
6308 | (set_attr "cpu_facility" "*,*,vec")]) | |
9db1d521 HP |
6309 | |
6310 | ;; | |
6311 | ;;- Divide and modulo instructions. | |
6312 | ;; | |
6313 | ||
6314 | ; | |
4023fb28 | 6315 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
6316 | ; |
6317 | ||
4023fb28 UW |
6318 | (define_expand "divmoddi4" |
6319 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 6320 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
6321 | (match_operand:DI 2 "general_operand" ""))) |
6322 | (set (match_operand:DI 3 "general_operand" "") | |
6323 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
6324 | (clobber (match_dup 4))] | |
9602b6a1 | 6325 | "TARGET_ZARCH" |
9db1d521 | 6326 | { |
f1e77d83 | 6327 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
6328 | |
6329 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
6330 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
6331 | |
6332 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 6333 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
6334 | |
6335 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6336 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6337 | |
6338 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6339 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6340 | |
9db1d521 | 6341 | DONE; |
10bbf137 | 6342 | }) |
9db1d521 HP |
6343 | |
6344 | (define_insn "divmodtidi3" | |
4023fb28 UW |
6345 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
6346 | (ior:TI | |
4023fb28 UW |
6347 | (ashift:TI |
6348 | (zero_extend:TI | |
5665e398 | 6349 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 6350 | (match_operand:DI 2 "general_operand" "d,RT"))) |
5665e398 UW |
6351 | (const_int 64)) |
6352 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9602b6a1 | 6353 | "TARGET_ZARCH" |
9db1d521 | 6354 | "@ |
d40c829f UW |
6355 | dsgr\t%0,%2 |
6356 | dsg\t%0,%2" | |
d3632d41 | 6357 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6358 | (set_attr "type" "idiv")]) |
9db1d521 | 6359 | |
4023fb28 UW |
6360 | (define_insn "divmodtisi3" |
6361 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6362 | (ior:TI | |
4023fb28 UW |
6363 | (ashift:TI |
6364 | (zero_extend:TI | |
5665e398 | 6365 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 6366 | (sign_extend:DI |
fb492564 | 6367 | (match_operand:SI 2 "nonimmediate_operand" "d,RT")))) |
5665e398 UW |
6368 | (const_int 64)) |
6369 | (zero_extend:TI | |
6370 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9602b6a1 | 6371 | "TARGET_ZARCH" |
4023fb28 | 6372 | "@ |
d40c829f UW |
6373 | dsgfr\t%0,%2 |
6374 | dsgf\t%0,%2" | |
d3632d41 | 6375 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6376 | (set_attr "type" "idiv")]) |
9db1d521 | 6377 | |
4023fb28 UW |
6378 | ; |
6379 | ; udivmoddi4 instruction pattern(s). | |
6380 | ; | |
9db1d521 | 6381 | |
4023fb28 UW |
6382 | (define_expand "udivmoddi4" |
6383 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
6384 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
6385 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
6386 | (set (match_operand:DI 3 "general_operand" "") | |
6387 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
6388 | (clobber (match_dup 4))] | |
9602b6a1 | 6389 | "TARGET_ZARCH" |
9db1d521 | 6390 | { |
4023fb28 UW |
6391 | rtx insn, div_equal, mod_equal, equal; |
6392 | ||
6393 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
6394 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
6395 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
6396 | gen_rtx_ASHIFT (TImode, |
6397 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
6398 | GEN_INT (64)), |
6399 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
6400 | |
6401 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 6402 | emit_clobber (operands[4]); |
4023fb28 UW |
6403 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
6404 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 6405 | |
4023fb28 | 6406 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6407 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
6408 | |
6409 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6410 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6411 | |
6412 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6413 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6414 | |
9db1d521 | 6415 | DONE; |
10bbf137 | 6416 | }) |
9db1d521 HP |
6417 | |
6418 | (define_insn "udivmodtidi3" | |
4023fb28 | 6419 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 6420 | (ior:TI |
5665e398 UW |
6421 | (ashift:TI |
6422 | (zero_extend:TI | |
6423 | (truncate:DI | |
2f7e5a0d EC |
6424 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
6425 | (zero_extend:TI | |
fb492564 | 6426 | (match_operand:DI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
6427 | (const_int 64)) |
6428 | (zero_extend:TI | |
6429 | (truncate:DI | |
6430 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9602b6a1 | 6431 | "TARGET_ZARCH" |
9db1d521 | 6432 | "@ |
d40c829f UW |
6433 | dlgr\t%0,%2 |
6434 | dlg\t%0,%2" | |
d3632d41 | 6435 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6436 | (set_attr "type" "idiv")]) |
9db1d521 HP |
6437 | |
6438 | ; | |
4023fb28 | 6439 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
6440 | ; |
6441 | ||
4023fb28 UW |
6442 | (define_expand "divmodsi4" |
6443 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
6444 | (div:SI (match_operand:SI 1 "general_operand" "") | |
6445 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
6446 | (set (match_operand:SI 3 "general_operand" "") | |
6447 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
6448 | (clobber (match_dup 4))] | |
9602b6a1 | 6449 | "!TARGET_ZARCH" |
9db1d521 | 6450 | { |
4023fb28 UW |
6451 | rtx insn, div_equal, mod_equal, equal; |
6452 | ||
6453 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
6454 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
6455 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
6456 | gen_rtx_ASHIFT (DImode, |
6457 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
6458 | GEN_INT (32)), |
6459 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
6460 | |
6461 | operands[4] = gen_reg_rtx(DImode); | |
6462 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 6463 | |
4023fb28 | 6464 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6465 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
6466 | |
6467 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 6468 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6469 | |
6470 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 6471 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6472 | |
9db1d521 | 6473 | DONE; |
10bbf137 | 6474 | }) |
9db1d521 HP |
6475 | |
6476 | (define_insn "divmoddisi3" | |
4023fb28 | 6477 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 6478 | (ior:DI |
5665e398 UW |
6479 | (ashift:DI |
6480 | (zero_extend:DI | |
6481 | (truncate:SI | |
2f7e5a0d EC |
6482 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
6483 | (sign_extend:DI | |
5665e398 UW |
6484 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
6485 | (const_int 32)) | |
6486 | (zero_extend:DI | |
6487 | (truncate:SI | |
6488 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 6489 | "!TARGET_ZARCH" |
9db1d521 | 6490 | "@ |
d40c829f UW |
6491 | dr\t%0,%2 |
6492 | d\t%0,%2" | |
9db1d521 | 6493 | [(set_attr "op_type" "RR,RX") |
077dab3b | 6494 | (set_attr "type" "idiv")]) |
9db1d521 HP |
6495 | |
6496 | ; | |
6497 | ; udivsi3 and umodsi3 instruction pattern(s). | |
6498 | ; | |
6499 | ||
f1e77d83 UW |
6500 | (define_expand "udivmodsi4" |
6501 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
6502 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
6503 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
6504 | (set (match_operand:SI 3 "general_operand" "") | |
6505 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
6506 | (clobber (match_dup 4))] | |
9602b6a1 | 6507 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
6508 | { |
6509 | rtx insn, div_equal, mod_equal, equal; | |
6510 | ||
6511 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
6512 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
6513 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
6514 | gen_rtx_ASHIFT (DImode, |
6515 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
6516 | GEN_INT (32)), |
6517 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
6518 | |
6519 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 6520 | emit_clobber (operands[4]); |
f1e77d83 UW |
6521 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
6522 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 6523 | |
f1e77d83 | 6524 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6525 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
6526 | |
6527 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 6528 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
6529 | |
6530 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 6531 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
6532 | |
6533 | DONE; | |
6534 | }) | |
6535 | ||
6536 | (define_insn "udivmoddisi3" | |
6537 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 6538 | (ior:DI |
5665e398 UW |
6539 | (ashift:DI |
6540 | (zero_extend:DI | |
6541 | (truncate:SI | |
2f7e5a0d EC |
6542 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
6543 | (zero_extend:DI | |
fb492564 | 6544 | (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
6545 | (const_int 32)) |
6546 | (zero_extend:DI | |
6547 | (truncate:SI | |
6548 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 6549 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
6550 | "@ |
6551 | dlr\t%0,%2 | |
6552 | dl\t%0,%2" | |
6553 | [(set_attr "op_type" "RRE,RXY") | |
6554 | (set_attr "type" "idiv")]) | |
4023fb28 | 6555 | |
9db1d521 HP |
6556 | (define_expand "udivsi3" |
6557 | [(set (match_operand:SI 0 "register_operand" "=d") | |
6558 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
6559 | (match_operand:SI 2 "general_operand" ""))) |
6560 | (clobber (match_dup 3))] | |
9602b6a1 | 6561 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 6562 | { |
4023fb28 UW |
6563 | rtx insn, udiv_equal, umod_equal, equal; |
6564 | ||
6565 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
6566 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
6567 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
6568 | gen_rtx_ASHIFT (DImode, |
6569 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
6570 | GEN_INT (32)), |
6571 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 6572 | |
4023fb28 | 6573 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
6574 | |
6575 | if (CONSTANT_P (operands[2])) | |
6576 | { | |
6577 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
6578 | { | |
19f8b229 | 6579 | rtx_code_label *label1 = gen_label_rtx (); |
9db1d521 | 6580 | |
4023fb28 UW |
6581 | operands[1] = make_safe_from (operands[1], operands[0]); |
6582 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
6583 | emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX, |
6584 | SImode, 1, label1); | |
4023fb28 | 6585 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
6586 | emit_label (label1); |
6587 | } | |
6588 | else | |
6589 | { | |
c7453384 EC |
6590 | operands[2] = force_reg (SImode, operands[2]); |
6591 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
6592 | |
6593 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
6594 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6595 | operands[2])); | |
bd94cb6e | 6596 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6597 | |
6598 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6599 | gen_lowpart (SImode, operands[3])); |
bd94cb6e | 6600 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
9db1d521 HP |
6601 | } |
6602 | } | |
6603 | else | |
c7453384 | 6604 | { |
19f8b229 TS |
6605 | rtx_code_label *label1 = gen_label_rtx (); |
6606 | rtx_code_label *label2 = gen_label_rtx (); | |
6607 | rtx_code_label *label3 = gen_label_rtx (); | |
9db1d521 | 6608 | |
c7453384 EC |
6609 | operands[1] = force_reg (SImode, operands[1]); |
6610 | operands[1] = make_safe_from (operands[1], operands[0]); | |
6611 | operands[2] = force_reg (SImode, operands[2]); | |
6612 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
6613 | |
6614 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
6615 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
6616 | SImode, 1, label3); | |
6617 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
6618 | SImode, 0, label2); | |
6619 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
6620 | SImode, 0, label1); | |
4023fb28 UW |
6621 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
6622 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6623 | operands[2])); | |
bd94cb6e | 6624 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6625 | |
6626 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6627 | gen_lowpart (SImode, operands[3])); |
bd94cb6e SB |
6628 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
6629 | ||
f314b9b1 | 6630 | emit_jump (label3); |
9db1d521 | 6631 | emit_label (label1); |
4023fb28 | 6632 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 6633 | emit_jump (label3); |
9db1d521 | 6634 | emit_label (label2); |
4023fb28 | 6635 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
6636 | emit_label (label3); |
6637 | } | |
c7453384 | 6638 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 6639 | DONE; |
10bbf137 | 6640 | }) |
9db1d521 HP |
6641 | |
6642 | (define_expand "umodsi3" | |
6643 | [(set (match_operand:SI 0 "register_operand" "=d") | |
6644 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
6645 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
6646 | (clobber (match_dup 3))] | |
9602b6a1 | 6647 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 6648 | { |
4023fb28 UW |
6649 | rtx insn, udiv_equal, umod_equal, equal; |
6650 | ||
6651 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
6652 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
6653 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
6654 | gen_rtx_ASHIFT (DImode, |
6655 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
6656 | GEN_INT (32)), |
6657 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 6658 | |
4023fb28 | 6659 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
6660 | |
6661 | if (CONSTANT_P (operands[2])) | |
6662 | { | |
6663 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
6664 | { | |
19f8b229 | 6665 | rtx_code_label *label1 = gen_label_rtx (); |
9db1d521 | 6666 | |
4023fb28 UW |
6667 | operands[1] = make_safe_from (operands[1], operands[0]); |
6668 | emit_move_insn (operands[0], operands[1]); | |
f90b7a5a PB |
6669 | emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX, |
6670 | SImode, 1, label1); | |
4023fb28 UW |
6671 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
6672 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
6673 | emit_label (label1); |
6674 | } | |
6675 | else | |
6676 | { | |
c7453384 EC |
6677 | operands[2] = force_reg (SImode, operands[2]); |
6678 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
6679 | |
6680 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
6681 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6682 | operands[2])); | |
bd94cb6e | 6683 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6684 | |
6685 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6686 | gen_highpart (SImode, operands[3])); |
bd94cb6e | 6687 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
9db1d521 HP |
6688 | } |
6689 | } | |
6690 | else | |
6691 | { | |
19f8b229 TS |
6692 | rtx_code_label *label1 = gen_label_rtx (); |
6693 | rtx_code_label *label2 = gen_label_rtx (); | |
6694 | rtx_code_label *label3 = gen_label_rtx (); | |
9db1d521 | 6695 | |
c7453384 EC |
6696 | operands[1] = force_reg (SImode, operands[1]); |
6697 | operands[1] = make_safe_from (operands[1], operands[0]); | |
6698 | operands[2] = force_reg (SImode, operands[2]); | |
6699 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 6700 | |
c7453384 | 6701 | emit_move_insn(operands[0], operands[1]); |
f90b7a5a PB |
6702 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
6703 | SImode, 1, label3); | |
6704 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
6705 | SImode, 0, label2); | |
6706 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
6707 | SImode, 0, label1); | |
4023fb28 UW |
6708 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
6709 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6710 | operands[2])); | |
bd94cb6e | 6711 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6712 | |
6713 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6714 | gen_highpart (SImode, operands[3])); |
bd94cb6e SB |
6715 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
6716 | ||
f314b9b1 | 6717 | emit_jump (label3); |
9db1d521 | 6718 | emit_label (label1); |
4023fb28 | 6719 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 6720 | emit_jump (label3); |
9db1d521 | 6721 | emit_label (label2); |
4023fb28 | 6722 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
6723 | emit_label (label3); |
6724 | } | |
9db1d521 | 6725 | DONE; |
10bbf137 | 6726 | }) |
9db1d521 HP |
6727 | |
6728 | ; | |
f5905b37 | 6729 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
6730 | ; |
6731 | ||
609e7e80 | 6732 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 6733 | (define_insn "div<mode>3" |
6e5b5de8 AK |
6734 | [(set (match_operand:FP 0 "register_operand" "=f, f,<vf>") |
6735 | (div:FP (match_operand:FP 1 "register_operand" "<f0>, 0,<v0>") | |
6736 | (match_operand:FP 2 "general_operand" "f,<Rf>,<vf>")))] | |
142cd70f | 6737 | "TARGET_HARD_FLOAT" |
9db1d521 | 6738 | "@ |
609e7e80 | 6739 | d<xde><bt>r\t%0,<op1>%2 |
6e5b5de8 AK |
6740 | d<xde>b\t%0,%2 |
6741 | wfddb\t%v0,%v1,%v2" | |
6742 | [(set_attr "op_type" "<RRer>,RXE,VRR") | |
6743 | (set_attr "type" "fdiv<mode>") | |
6744 | (set_attr "cpu_facility" "*,*,vec")]) | |
9db1d521 | 6745 | |
9db1d521 HP |
6746 | |
6747 | ;; | |
6748 | ;;- And instructions. | |
6749 | ;; | |
6750 | ||
047d35ed AS |
6751 | (define_expand "and<mode>3" |
6752 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6753 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6754 | (match_operand:INT 2 "general_operand" ""))) | |
6755 | (clobber (reg:CC CC_REGNUM))] | |
6756 | "" | |
6757 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
6758 | ||
9db1d521 HP |
6759 | ; |
6760 | ; anddi3 instruction pattern(s). | |
6761 | ; | |
6762 | ||
6763 | (define_insn "*anddi3_cc" | |
ae156f85 | 6764 | [(set (reg CC_REGNUM) |
e3140518 RH |
6765 | (compare |
6766 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d") | |
6767 | (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq")) | |
6768 | (const_int 0))) | |
6769 | (set (match_operand:DI 0 "register_operand" "=d,d, d, d") | |
9db1d521 | 6770 | (and:DI (match_dup 1) (match_dup 2)))] |
e3140518 | 6771 | "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" |
9db1d521 | 6772 | "@ |
d40c829f | 6773 | ngr\t%0,%2 |
65b1d8ea | 6774 | ngrk\t%0,%1,%2 |
e3140518 RH |
6775 | ng\t%0,%2 |
6776 | risbg\t%0,%1,%s2,128+%e2,0" | |
6777 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
6778 | (set_attr "cpu_facility" "*,z196,*,z10") | |
6779 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
6780 | |
6781 | (define_insn "*anddi3_cconly" | |
ae156f85 | 6782 | [(set (reg CC_REGNUM) |
e3140518 RH |
6783 | (compare |
6784 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d") | |
6785 | (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq")) | |
9db1d521 | 6786 | (const_int 0))) |
e3140518 RH |
6787 | (clobber (match_scratch:DI 0 "=d,d, d, d"))] |
6788 | "TARGET_ZARCH | |
6789 | && s390_match_ccmode(insn, CCTmode) | |
68f9c5e2 UW |
6790 | /* Do not steal TM patterns. */ |
6791 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 6792 | "@ |
d40c829f | 6793 | ngr\t%0,%2 |
65b1d8ea | 6794 | ngrk\t%0,%1,%2 |
e3140518 RH |
6795 | ng\t%0,%2 |
6796 | risbg\t%0,%1,%s2,128+%e2,0" | |
6797 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
6798 | (set_attr "cpu_facility" "*,z196,*,z10") | |
6799 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 6800 | |
3af8e996 | 6801 | (define_insn "*anddi3" |
65b1d8ea | 6802 | [(set (match_operand:DI 0 "nonimmediate_operand" |
e3140518 RH |
6803 | "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q") |
6804 | (and:DI | |
6805 | (match_operand:DI 1 "nonimmediate_operand" | |
6806 | "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0") | |
6807 | (match_operand:DI 2 "general_operand" | |
6808 | "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q"))) | |
ec24698e | 6809 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6810 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6811 | "@ |
6812 | # | |
6813 | # | |
6814 | nihh\t%0,%j2 | |
6815 | nihl\t%0,%j2 | |
6816 | nilh\t%0,%j2 | |
6817 | nill\t%0,%j2 | |
6818 | nihf\t%0,%m2 | |
6819 | nilf\t%0,%m2 | |
6820 | ngr\t%0,%2 | |
65b1d8ea | 6821 | ngrk\t%0,%1,%2 |
ec24698e | 6822 | ng\t%0,%2 |
e3140518 | 6823 | risbg\t%0,%1,%s2,128+%e2,0 |
ec24698e UW |
6824 | # |
6825 | #" | |
e3140518 RH |
6826 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS") |
6827 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*") | |
9381e3f1 WG |
6828 | (set_attr "z10prop" "*, |
6829 | *, | |
6830 | z10_super_E1, | |
6831 | z10_super_E1, | |
6832 | z10_super_E1, | |
6833 | z10_super_E1, | |
6834 | z10_super_E1, | |
6835 | z10_super_E1, | |
6836 | z10_super_E1, | |
65b1d8ea | 6837 | *, |
9381e3f1 | 6838 | z10_super_E1, |
e3140518 | 6839 | z10_super_E1, |
9381e3f1 WG |
6840 | *, |
6841 | *")]) | |
0dfa6c5e UW |
6842 | |
6843 | (define_split | |
6844 | [(set (match_operand:DI 0 "s_operand" "") | |
6845 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6846 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6847 | "reload_completed" |
6848 | [(parallel | |
6849 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6850 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6851 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 6852 | |
1a2e356e RH |
6853 | ;; These two are what combine generates for (ashift (zero_extract)). |
6854 | (define_insn "*extzv_<mode>_srl" | |
6855 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6856 | (and:GPR (lshiftrt:GPR | |
6857 | (match_operand:GPR 1 "register_operand" "d") | |
6858 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
6859 | (match_operand:GPR 3 "contiguous_bitmask_operand" ""))) | |
6860 | (clobber (reg:CC CC_REGNUM))] | |
6861 | "TARGET_Z10 | |
6862 | /* Note that even for the SImode pattern, the rotate is always DImode. */ | |
6863 | && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]), | |
6864 | INTVAL (operands[3]))" | |
6865 | "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2" | |
6866 | [(set_attr "op_type" "RIE") | |
6867 | (set_attr "z10prop" "z10_super_E1")]) | |
6868 | ||
6869 | (define_insn "*extzv_<mode>_sll" | |
6870 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6871 | (and:GPR (ashift:GPR | |
6872 | (match_operand:GPR 1 "register_operand" "d") | |
6873 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
6874 | (match_operand:GPR 3 "contiguous_bitmask_operand" ""))) | |
6875 | (clobber (reg:CC CC_REGNUM))] | |
6876 | "TARGET_Z10 | |
6877 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]), | |
6878 | INTVAL (operands[3]))" | |
6879 | "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2" | |
6880 | [(set_attr "op_type" "RIE") | |
6881 | (set_attr "z10prop" "z10_super_E1")]) | |
6882 | ||
9db1d521 HP |
6883 | |
6884 | ; | |
6885 | ; andsi3 instruction pattern(s). | |
6886 | ; | |
6887 | ||
6888 | (define_insn "*andsi3_cc" | |
ae156f85 | 6889 | [(set (reg CC_REGNUM) |
e3140518 RH |
6890 | (compare |
6891 | (and:SI | |
6892 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
6893 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
6894 | (const_int 0))) | |
6895 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d") | |
9db1d521 HP |
6896 | (and:SI (match_dup 1) (match_dup 2)))] |
6897 | "s390_match_ccmode(insn, CCTmode)" | |
6898 | "@ | |
ec24698e | 6899 | nilf\t%0,%o2 |
d40c829f | 6900 | nr\t%0,%2 |
65b1d8ea | 6901 | nrk\t%0,%1,%2 |
d40c829f | 6902 | n\t%0,%2 |
e3140518 RH |
6903 | ny\t%0,%2 |
6904 | risbg\t%0,%1,%t2,128+%f2,0" | |
6905 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
6906 | (set_attr "cpu_facility" "*,*,z196,*,*,z10") | |
6907 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
6908 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
6909 | |
6910 | (define_insn "*andsi3_cconly" | |
ae156f85 | 6911 | [(set (reg CC_REGNUM) |
e3140518 RH |
6912 | (compare |
6913 | (and:SI | |
6914 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
6915 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
6916 | (const_int 0))) | |
6917 | (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))] | |
68f9c5e2 UW |
6918 | "s390_match_ccmode(insn, CCTmode) |
6919 | /* Do not steal TM patterns. */ | |
6920 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 6921 | "@ |
ec24698e | 6922 | nilf\t%0,%o2 |
d40c829f | 6923 | nr\t%0,%2 |
65b1d8ea | 6924 | nrk\t%0,%1,%2 |
d40c829f | 6925 | n\t%0,%2 |
e3140518 RH |
6926 | ny\t%0,%2 |
6927 | risbg\t%0,%1,%t2,128+%f2,0" | |
6928 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
6929 | (set_attr "cpu_facility" "*,*,z196,*,*,z10") | |
65b1d8ea | 6930 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
e3140518 | 6931 | z10_super_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 6932 | |
f19a9af7 | 6933 | (define_insn "*andsi3_zarch" |
65b1d8ea | 6934 | [(set (match_operand:SI 0 "nonimmediate_operand" |
e3140518 | 6935 | "=d,d, d, d, d,d,d,d,d, d, AQ,Q") |
0dfa6c5e | 6936 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
e3140518 | 6937 | "%d,o, 0, 0, 0,0,d,0,0, d, 0,0") |
0dfa6c5e | 6938 | (match_operand:SI 2 "general_operand" |
e3140518 | 6939 | " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q"))) |
ae156f85 | 6940 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6941 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 6942 | "@ |
f19a9af7 AK |
6943 | # |
6944 | # | |
6945 | nilh\t%0,%j2 | |
2f7e5a0d | 6946 | nill\t%0,%j2 |
ec24698e | 6947 | nilf\t%0,%o2 |
d40c829f | 6948 | nr\t%0,%2 |
65b1d8ea | 6949 | nrk\t%0,%1,%2 |
d40c829f | 6950 | n\t%0,%2 |
8cb66696 | 6951 | ny\t%0,%2 |
e3140518 | 6952 | risbg\t%0,%1,%t2,128+%f2,0 |
0dfa6c5e | 6953 | # |
19b63d8e | 6954 | #" |
e3140518 RH |
6955 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") |
6956 | (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*") | |
9381e3f1 WG |
6957 | (set_attr "z10prop" "*, |
6958 | *, | |
6959 | z10_super_E1, | |
6960 | z10_super_E1, | |
6961 | z10_super_E1, | |
6962 | z10_super_E1, | |
65b1d8ea | 6963 | *, |
9381e3f1 WG |
6964 | z10_super_E1, |
6965 | z10_super_E1, | |
e3140518 | 6966 | z10_super_E1, |
9381e3f1 WG |
6967 | *, |
6968 | *")]) | |
f19a9af7 AK |
6969 | |
6970 | (define_insn "*andsi3_esa" | |
65b1d8ea AK |
6971 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") |
6972 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") | |
6973 | (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) | |
ae156f85 | 6974 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6975 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
6976 | "@ |
6977 | nr\t%0,%2 | |
8cb66696 | 6978 | n\t%0,%2 |
0dfa6c5e | 6979 | # |
19b63d8e | 6980 | #" |
9381e3f1 WG |
6981 | [(set_attr "op_type" "RR,RX,SI,SS") |
6982 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
6983 | ||
0dfa6c5e UW |
6984 | |
6985 | (define_split | |
6986 | [(set (match_operand:SI 0 "s_operand" "") | |
6987 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 6988 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6989 | "reload_completed" |
6990 | [(parallel | |
6991 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6992 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6993 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 6994 | |
9db1d521 HP |
6995 | ; |
6996 | ; andhi3 instruction pattern(s). | |
6997 | ; | |
6998 | ||
8cb66696 | 6999 | (define_insn "*andhi3_zarch" |
65b1d8ea AK |
7000 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7001 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7002 | (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) | |
ae156f85 | 7003 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7004 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7005 | "@ |
d40c829f | 7006 | nr\t%0,%2 |
65b1d8ea | 7007 | nrk\t%0,%1,%2 |
8cb66696 | 7008 | nill\t%0,%x2 |
0dfa6c5e | 7009 | # |
19b63d8e | 7010 | #" |
65b1d8ea AK |
7011 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7012 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7013 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") | |
9381e3f1 | 7014 | ]) |
8cb66696 UW |
7015 | |
7016 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
7017 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7018 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7019 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 7020 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7021 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7022 | "@ | |
7023 | nr\t%0,%2 | |
0dfa6c5e | 7024 | # |
19b63d8e | 7025 | #" |
9381e3f1 WG |
7026 | [(set_attr "op_type" "RR,SI,SS") |
7027 | (set_attr "z10prop" "z10_super_E1,*,*") | |
7028 | ]) | |
0dfa6c5e UW |
7029 | |
7030 | (define_split | |
7031 | [(set (match_operand:HI 0 "s_operand" "") | |
7032 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7033 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7034 | "reload_completed" |
7035 | [(parallel | |
7036 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7037 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7038 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 7039 | |
9db1d521 HP |
7040 | ; |
7041 | ; andqi3 instruction pattern(s). | |
7042 | ; | |
7043 | ||
8cb66696 | 7044 | (define_insn "*andqi3_zarch" |
65b1d8ea AK |
7045 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7046 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7047 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7048 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7049 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7050 | "@ |
d40c829f | 7051 | nr\t%0,%2 |
65b1d8ea | 7052 | nrk\t%0,%1,%2 |
8cb66696 | 7053 | nill\t%0,%b2 |
fc0ea003 UW |
7054 | ni\t%S0,%b2 |
7055 | niy\t%S0,%b2 | |
19b63d8e | 7056 | #" |
65b1d8ea AK |
7057 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
7058 | (set_attr "cpu_facility" "*,z196,*,*,*,*") | |
7059 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) | |
8cb66696 UW |
7060 | |
7061 | (define_insn "*andqi3_esa" | |
7062 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7063 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7064 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7065 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7066 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7067 | "@ |
8cb66696 | 7068 | nr\t%0,%2 |
fc0ea003 | 7069 | ni\t%S0,%b2 |
19b63d8e | 7070 | #" |
9381e3f1 WG |
7071 | [(set_attr "op_type" "RR,SI,SS") |
7072 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 7073 | |
19b63d8e UW |
7074 | ; |
7075 | ; Block and (NC) patterns. | |
7076 | ; | |
7077 | ||
7078 | (define_insn "*nc" | |
7079 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7080 | (and:BLK (match_dup 0) | |
7081 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7082 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7083 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7084 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7085 | "nc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7086 | [(set_attr "op_type" "SS") |
7087 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7088 | |
7089 | (define_split | |
7090 | [(set (match_operand 0 "memory_operand" "") | |
7091 | (and (match_dup 0) | |
7092 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7093 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7094 | "reload_completed |
7095 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7096 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7097 | [(parallel | |
7098 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
7099 | (use (match_dup 2)) | |
ae156f85 | 7100 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7101 | { |
7102 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7103 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7104 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7105 | }) | |
7106 | ||
7107 | (define_peephole2 | |
7108 | [(parallel | |
7109 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7110 | (and:BLK (match_dup 0) | |
7111 | (match_operand:BLK 1 "memory_operand" ""))) | |
7112 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7113 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7114 | (parallel |
7115 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7116 | (and:BLK (match_dup 3) | |
7117 | (match_operand:BLK 4 "memory_operand" ""))) | |
7118 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7119 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7120 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7121 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7122 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7123 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7124 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7125 | [(parallel | |
7126 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
7127 | (use (match_dup 8)) | |
ae156f85 | 7128 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7129 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7130 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7131 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7132 | ||
9db1d521 HP |
7133 | |
7134 | ;; | |
7135 | ;;- Bit set (inclusive or) instructions. | |
7136 | ;; | |
7137 | ||
047d35ed AS |
7138 | (define_expand "ior<mode>3" |
7139 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7140 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7141 | (match_operand:INT 2 "general_operand" ""))) | |
7142 | (clobber (reg:CC CC_REGNUM))] | |
7143 | "" | |
7144 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
7145 | ||
9db1d521 HP |
7146 | ; |
7147 | ; iordi3 instruction pattern(s). | |
7148 | ; | |
7149 | ||
4023fb28 | 7150 | (define_insn "*iordi3_cc" |
ae156f85 | 7151 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7152 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
7153 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 7154 | (const_int 0))) |
65b1d8ea | 7155 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
4023fb28 | 7156 | (ior:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7157 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7158 | "@ |
d40c829f | 7159 | ogr\t%0,%2 |
65b1d8ea | 7160 | ogrk\t%0,%1,%2 |
d40c829f | 7161 | og\t%0,%2" |
65b1d8ea AK |
7162 | [(set_attr "op_type" "RRE,RRF,RXY") |
7163 | (set_attr "cpu_facility" "*,z196,*") | |
7164 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 UW |
7165 | |
7166 | (define_insn "*iordi3_cconly" | |
ae156f85 | 7167 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7168 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7169 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 7170 | (const_int 0))) |
65b1d8ea | 7171 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 7172 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7173 | "@ |
d40c829f | 7174 | ogr\t%0,%2 |
65b1d8ea | 7175 | ogrk\t%0,%1,%2 |
d40c829f | 7176 | og\t%0,%2" |
65b1d8ea AK |
7177 | [(set_attr "op_type" "RRE,RRF,RXY") |
7178 | (set_attr "cpu_facility" "*,z196,*") | |
7179 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7180 | |
3af8e996 | 7181 | (define_insn "*iordi3" |
65b1d8ea AK |
7182 | [(set (match_operand:DI 0 "nonimmediate_operand" |
7183 | "=d, d, d, d, d, d,d,d, d, AQ,Q") | |
7184 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" | |
7185 | " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0") | |
ec24698e | 7186 | (match_operand:DI 2 "general_operand" |
65b1d8ea | 7187 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) |
ec24698e | 7188 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7189 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7190 | "@ |
7191 | oihh\t%0,%i2 | |
7192 | oihl\t%0,%i2 | |
7193 | oilh\t%0,%i2 | |
7194 | oill\t%0,%i2 | |
7195 | oihf\t%0,%k2 | |
7196 | oilf\t%0,%k2 | |
7197 | ogr\t%0,%2 | |
65b1d8ea | 7198 | ogrk\t%0,%1,%2 |
ec24698e UW |
7199 | og\t%0,%2 |
7200 | # | |
7201 | #" | |
65b1d8ea AK |
7202 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
7203 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
7204 | (set_attr "z10prop" "z10_super_E1, |
7205 | z10_super_E1, | |
7206 | z10_super_E1, | |
7207 | z10_super_E1, | |
7208 | z10_super_E1, | |
7209 | z10_super_E1, | |
7210 | z10_super_E1, | |
65b1d8ea | 7211 | *, |
9381e3f1 WG |
7212 | z10_super_E1, |
7213 | *, | |
7214 | *")]) | |
0dfa6c5e UW |
7215 | |
7216 | (define_split | |
7217 | [(set (match_operand:DI 0 "s_operand" "") | |
7218 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7219 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7220 | "reload_completed" |
7221 | [(parallel | |
7222 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7223 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7224 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7225 | |
9db1d521 HP |
7226 | ; |
7227 | ; iorsi3 instruction pattern(s). | |
7228 | ; | |
7229 | ||
4023fb28 | 7230 | (define_insn "*iorsi3_cc" |
ae156f85 | 7231 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7232 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7233 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7234 | (const_int 0))) |
65b1d8ea | 7235 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7236 | (ior:SI (match_dup 1) (match_dup 2)))] |
7237 | "s390_match_ccmode(insn, CCTmode)" | |
7238 | "@ | |
ec24698e | 7239 | oilf\t%0,%o2 |
d40c829f | 7240 | or\t%0,%2 |
65b1d8ea | 7241 | ork\t%0,%1,%2 |
d40c829f UW |
7242 | o\t%0,%2 |
7243 | oy\t%0,%2" | |
65b1d8ea AK |
7244 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
7245 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7246 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
7247 | |
7248 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 7249 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7250 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7251 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7252 | (const_int 0))) |
65b1d8ea | 7253 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7254 | "s390_match_ccmode(insn, CCTmode)" |
7255 | "@ | |
ec24698e | 7256 | oilf\t%0,%o2 |
d40c829f | 7257 | or\t%0,%2 |
65b1d8ea | 7258 | ork\t%0,%1,%2 |
d40c829f UW |
7259 | o\t%0,%2 |
7260 | oy\t%0,%2" | |
65b1d8ea AK |
7261 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
7262 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7263 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 7264 | |
8cb66696 | 7265 | (define_insn "*iorsi3_zarch" |
65b1d8ea AK |
7266 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") |
7267 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") | |
7268 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7269 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7270 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7271 | "@ |
f19a9af7 AK |
7272 | oilh\t%0,%i2 |
7273 | oill\t%0,%i2 | |
ec24698e | 7274 | oilf\t%0,%o2 |
d40c829f | 7275 | or\t%0,%2 |
65b1d8ea | 7276 | ork\t%0,%1,%2 |
d40c829f | 7277 | o\t%0,%2 |
8cb66696 | 7278 | oy\t%0,%2 |
0dfa6c5e | 7279 | # |
19b63d8e | 7280 | #" |
65b1d8ea AK |
7281 | [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
7282 | (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*") | |
9381e3f1 WG |
7283 | (set_attr "z10prop" "z10_super_E1, |
7284 | z10_super_E1, | |
7285 | z10_super_E1, | |
7286 | z10_super_E1, | |
65b1d8ea | 7287 | *, |
9381e3f1 WG |
7288 | z10_super_E1, |
7289 | z10_super_E1, | |
7290 | *, | |
7291 | *")]) | |
8cb66696 UW |
7292 | |
7293 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 7294 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 7295 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 7296 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 7297 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7298 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7299 | "@ |
7300 | or\t%0,%2 | |
8cb66696 | 7301 | o\t%0,%2 |
0dfa6c5e | 7302 | # |
19b63d8e | 7303 | #" |
9381e3f1 WG |
7304 | [(set_attr "op_type" "RR,RX,SI,SS") |
7305 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7306 | |
7307 | (define_split | |
7308 | [(set (match_operand:SI 0 "s_operand" "") | |
7309 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7310 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7311 | "reload_completed" |
7312 | [(parallel | |
7313 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7314 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7315 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7316 | |
4023fb28 UW |
7317 | ; |
7318 | ; iorhi3 instruction pattern(s). | |
7319 | ; | |
7320 | ||
8cb66696 | 7321 | (define_insn "*iorhi3_zarch" |
65b1d8ea AK |
7322 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7323 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7324 | (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) | |
ae156f85 | 7325 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7326 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7327 | "@ |
d40c829f | 7328 | or\t%0,%2 |
65b1d8ea | 7329 | ork\t%0,%1,%2 |
8cb66696 | 7330 | oill\t%0,%x2 |
0dfa6c5e | 7331 | # |
19b63d8e | 7332 | #" |
65b1d8ea AK |
7333 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7334 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7335 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) | |
8cb66696 UW |
7336 | |
7337 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
7338 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7339 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7340 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 7341 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7342 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7343 | "@ | |
7344 | or\t%0,%2 | |
0dfa6c5e | 7345 | # |
19b63d8e | 7346 | #" |
9381e3f1 WG |
7347 | [(set_attr "op_type" "RR,SI,SS") |
7348 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7349 | |
7350 | (define_split | |
7351 | [(set (match_operand:HI 0 "s_operand" "") | |
7352 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7353 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7354 | "reload_completed" |
7355 | [(parallel | |
7356 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7357 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7358 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 7359 | |
9db1d521 | 7360 | ; |
4023fb28 | 7361 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
7362 | ; |
7363 | ||
8cb66696 | 7364 | (define_insn "*iorqi3_zarch" |
65b1d8ea AK |
7365 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7366 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7367 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7368 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7369 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7370 | "@ |
d40c829f | 7371 | or\t%0,%2 |
65b1d8ea | 7372 | ork\t%0,%1,%2 |
8cb66696 | 7373 | oill\t%0,%b2 |
fc0ea003 UW |
7374 | oi\t%S0,%b2 |
7375 | oiy\t%S0,%b2 | |
19b63d8e | 7376 | #" |
65b1d8ea AK |
7377 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
7378 | (set_attr "cpu_facility" "*,z196,*,*,*,*") | |
7379 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, | |
7380 | z10_super,z10_super,*")]) | |
8cb66696 UW |
7381 | |
7382 | (define_insn "*iorqi3_esa" | |
7383 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7384 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7385 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7386 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7387 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7388 | "@ |
8cb66696 | 7389 | or\t%0,%2 |
fc0ea003 | 7390 | oi\t%S0,%b2 |
19b63d8e | 7391 | #" |
9381e3f1 WG |
7392 | [(set_attr "op_type" "RR,SI,SS") |
7393 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 7394 | |
19b63d8e UW |
7395 | ; |
7396 | ; Block inclusive or (OC) patterns. | |
7397 | ; | |
7398 | ||
7399 | (define_insn "*oc" | |
7400 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7401 | (ior:BLK (match_dup 0) | |
7402 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7403 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7404 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7405 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7406 | "oc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7407 | [(set_attr "op_type" "SS") |
7408 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7409 | |
7410 | (define_split | |
7411 | [(set (match_operand 0 "memory_operand" "") | |
7412 | (ior (match_dup 0) | |
7413 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7414 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7415 | "reload_completed |
7416 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7417 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7418 | [(parallel | |
7419 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
7420 | (use (match_dup 2)) | |
ae156f85 | 7421 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7422 | { |
7423 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7424 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7425 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7426 | }) | |
7427 | ||
7428 | (define_peephole2 | |
7429 | [(parallel | |
7430 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7431 | (ior:BLK (match_dup 0) | |
7432 | (match_operand:BLK 1 "memory_operand" ""))) | |
7433 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7434 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7435 | (parallel |
7436 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7437 | (ior:BLK (match_dup 3) | |
7438 | (match_operand:BLK 4 "memory_operand" ""))) | |
7439 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7440 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7441 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7442 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7443 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7444 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7445 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7446 | [(parallel | |
7447 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
7448 | (use (match_dup 8)) | |
ae156f85 | 7449 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7450 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7451 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7452 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7453 | ||
9db1d521 HP |
7454 | |
7455 | ;; | |
7456 | ;;- Xor instructions. | |
7457 | ;; | |
7458 | ||
047d35ed AS |
7459 | (define_expand "xor<mode>3" |
7460 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7461 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7462 | (match_operand:INT 2 "general_operand" ""))) | |
7463 | (clobber (reg:CC CC_REGNUM))] | |
7464 | "" | |
7465 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
7466 | ||
3c91f126 AK |
7467 | ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing |
7468 | ; simplifications. So its better to have something matching. | |
7469 | (define_split | |
7470 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7471 | (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))] | |
7472 | "" | |
7473 | [(parallel | |
7474 | [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2))) | |
7475 | (clobber (reg:CC CC_REGNUM))])] | |
7476 | { | |
7477 | operands[2] = constm1_rtx; | |
7478 | if (!s390_logical_operator_ok_p (operands)) | |
7479 | FAIL; | |
7480 | }) | |
7481 | ||
9db1d521 HP |
7482 | ; |
7483 | ; xordi3 instruction pattern(s). | |
7484 | ; | |
7485 | ||
4023fb28 | 7486 | (define_insn "*xordi3_cc" |
ae156f85 | 7487 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7488 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
7489 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 7490 | (const_int 0))) |
65b1d8ea | 7491 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
4023fb28 | 7492 | (xor:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7493 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7494 | "@ |
d40c829f | 7495 | xgr\t%0,%2 |
65b1d8ea | 7496 | xgrk\t%0,%1,%2 |
d40c829f | 7497 | xg\t%0,%2" |
65b1d8ea | 7498 | [(set_attr "op_type" "RRE,RRF,RXY") |
5490de28 | 7499 | (set_attr "cpu_facility" "*,z196,*") |
65b1d8ea | 7500 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) |
4023fb28 UW |
7501 | |
7502 | (define_insn "*xordi3_cconly" | |
ae156f85 | 7503 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7504 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
7505 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 7506 | (const_int 0))) |
65b1d8ea | 7507 | (clobber (match_scratch:DI 0 "=d,d, d"))] |
9602b6a1 | 7508 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7509 | "@ |
d40c829f | 7510 | xgr\t%0,%2 |
65b1d8ea | 7511 | xgrk\t%0,%1,%2 |
c7fd8cd8 | 7512 | xg\t%0,%2" |
65b1d8ea AK |
7513 | [(set_attr "op_type" "RRE,RRF,RXY") |
7514 | (set_attr "cpu_facility" "*,z196,*") | |
7515 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7516 | |
3af8e996 | 7517 | (define_insn "*xordi3" |
65b1d8ea AK |
7518 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q") |
7519 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0") | |
7520 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) | |
ec24698e | 7521 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7522 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7523 | "@ |
7524 | xihf\t%0,%k2 | |
7525 | xilf\t%0,%k2 | |
7526 | xgr\t%0,%2 | |
65b1d8ea | 7527 | xgrk\t%0,%1,%2 |
ec24698e UW |
7528 | xg\t%0,%2 |
7529 | # | |
7530 | #" | |
65b1d8ea AK |
7531 | [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") |
7532 | (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") | |
7533 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, | |
7534 | *,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7535 | |
7536 | (define_split | |
7537 | [(set (match_operand:DI 0 "s_operand" "") | |
7538 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7539 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7540 | "reload_completed" |
7541 | [(parallel | |
7542 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7543 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7544 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 7545 | |
9db1d521 HP |
7546 | ; |
7547 | ; xorsi3 instruction pattern(s). | |
7548 | ; | |
7549 | ||
4023fb28 | 7550 | (define_insn "*xorsi3_cc" |
ae156f85 | 7551 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7552 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7553 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7554 | (const_int 0))) |
65b1d8ea | 7555 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7556 | (xor:SI (match_dup 1) (match_dup 2)))] |
7557 | "s390_match_ccmode(insn, CCTmode)" | |
7558 | "@ | |
ec24698e | 7559 | xilf\t%0,%o2 |
d40c829f | 7560 | xr\t%0,%2 |
65b1d8ea | 7561 | xrk\t%0,%1,%2 |
d40c829f UW |
7562 | x\t%0,%2 |
7563 | xy\t%0,%2" | |
65b1d8ea AK |
7564 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
7565 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7566 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
7567 | z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
7568 | |
7569 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 7570 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7571 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7572 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7573 | (const_int 0))) |
65b1d8ea | 7574 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7575 | "s390_match_ccmode(insn, CCTmode)" |
7576 | "@ | |
ec24698e | 7577 | xilf\t%0,%o2 |
d40c829f | 7578 | xr\t%0,%2 |
65b1d8ea | 7579 | xrk\t%0,%1,%2 |
d40c829f UW |
7580 | x\t%0,%2 |
7581 | xy\t%0,%2" | |
65b1d8ea AK |
7582 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
7583 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7584 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
7585 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 7586 | |
8cb66696 | 7587 | (define_insn "*xorsi3" |
65b1d8ea AK |
7588 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") |
7589 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") | |
7590 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7591 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7592 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 7593 | "@ |
ec24698e | 7594 | xilf\t%0,%o2 |
d40c829f | 7595 | xr\t%0,%2 |
65b1d8ea | 7596 | xrk\t%0,%1,%2 |
d40c829f | 7597 | x\t%0,%2 |
8cb66696 | 7598 | xy\t%0,%2 |
0dfa6c5e | 7599 | # |
19b63d8e | 7600 | #" |
65b1d8ea AK |
7601 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") |
7602 | (set_attr "cpu_facility" "*,*,z196,*,*,*,*") | |
7603 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
7604 | z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7605 | |
7606 | (define_split | |
7607 | [(set (match_operand:SI 0 "s_operand" "") | |
7608 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7609 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7610 | "reload_completed" |
7611 | [(parallel | |
7612 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7613 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7614 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 7615 | |
9db1d521 HP |
7616 | ; |
7617 | ; xorhi3 instruction pattern(s). | |
7618 | ; | |
7619 | ||
8cb66696 | 7620 | (define_insn "*xorhi3" |
65b1d8ea AK |
7621 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7622 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") | |
7623 | (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) | |
ae156f85 | 7624 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7625 | "s390_logical_operator_ok_p (operands)" |
7626 | "@ | |
ec24698e | 7627 | xilf\t%0,%x2 |
8cb66696 | 7628 | xr\t%0,%2 |
65b1d8ea | 7629 | xrk\t%0,%1,%2 |
0dfa6c5e | 7630 | # |
19b63d8e | 7631 | #" |
65b1d8ea AK |
7632 | [(set_attr "op_type" "RIL,RR,RRF,SI,SS") |
7633 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7634 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) | |
0dfa6c5e UW |
7635 | |
7636 | (define_split | |
7637 | [(set (match_operand:HI 0 "s_operand" "") | |
7638 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7639 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7640 | "reload_completed" |
7641 | [(parallel | |
7642 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7643 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7644 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 7645 | |
9db1d521 HP |
7646 | ; |
7647 | ; xorqi3 instruction pattern(s). | |
7648 | ; | |
7649 | ||
8cb66696 | 7650 | (define_insn "*xorqi3" |
65b1d8ea AK |
7651 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7652 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") | |
7653 | (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) | |
ae156f85 | 7654 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7655 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 7656 | "@ |
ec24698e | 7657 | xilf\t%0,%b2 |
8cb66696 | 7658 | xr\t%0,%2 |
65b1d8ea | 7659 | xrk\t%0,%1,%2 |
fc0ea003 UW |
7660 | xi\t%S0,%b2 |
7661 | xiy\t%S0,%b2 | |
19b63d8e | 7662 | #" |
65b1d8ea AK |
7663 | [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") |
7664 | (set_attr "cpu_facility" "*,*,z196,*,*,*") | |
7665 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) | |
9381e3f1 | 7666 | |
4023fb28 | 7667 | |
19b63d8e UW |
7668 | ; |
7669 | ; Block exclusive or (XC) patterns. | |
7670 | ; | |
7671 | ||
7672 | (define_insn "*xc" | |
7673 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7674 | (xor:BLK (match_dup 0) | |
7675 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7676 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7677 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7678 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7679 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 7680 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
7681 | |
7682 | (define_split | |
7683 | [(set (match_operand 0 "memory_operand" "") | |
7684 | (xor (match_dup 0) | |
7685 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7686 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7687 | "reload_completed |
7688 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7689 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7690 | [(parallel | |
7691 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
7692 | (use (match_dup 2)) | |
ae156f85 | 7693 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7694 | { |
7695 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7696 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7697 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7698 | }) | |
7699 | ||
7700 | (define_peephole2 | |
7701 | [(parallel | |
7702 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7703 | (xor:BLK (match_dup 0) | |
7704 | (match_operand:BLK 1 "memory_operand" ""))) | |
7705 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7706 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7707 | (parallel |
7708 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7709 | (xor:BLK (match_dup 3) | |
7710 | (match_operand:BLK 4 "memory_operand" ""))) | |
7711 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7712 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7713 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7714 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7715 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7716 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7717 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7718 | [(parallel | |
7719 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
7720 | (use (match_dup 8)) | |
ae156f85 | 7721 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7722 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7723 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7724 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7725 | ||
7726 | ; | |
7727 | ; Block xor (XC) patterns with src == dest. | |
7728 | ; | |
7729 | ||
7730 | (define_insn "*xc_zero" | |
7731 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7732 | (const_int 0)) | |
7733 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 7734 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7735 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 7736 | "xc\t%O0(%1,%R0),%S0" |
65b1d8ea AK |
7737 | [(set_attr "op_type" "SS") |
7738 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7739 | |
7740 | (define_peephole2 | |
7741 | [(parallel | |
7742 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7743 | (const_int 0)) | |
7744 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 7745 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7746 | (parallel |
7747 | [(set (match_operand:BLK 2 "memory_operand" "") | |
7748 | (const_int 0)) | |
7749 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 7750 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7751 | "s390_offset_p (operands[0], operands[2], operands[1]) |
7752 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
7753 | [(parallel | |
7754 | [(set (match_dup 4) (const_int 0)) | |
7755 | (use (match_dup 5)) | |
ae156f85 | 7756 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7757 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7758 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
7759 | ||
9db1d521 HP |
7760 | |
7761 | ;; | |
7762 | ;;- Negate instructions. | |
7763 | ;; | |
7764 | ||
7765 | ; | |
9a91a21f | 7766 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
7767 | ; |
7768 | ||
9a91a21f | 7769 | (define_expand "neg<mode>2" |
9db1d521 | 7770 | [(parallel |
9a91a21f AS |
7771 | [(set (match_operand:DSI 0 "register_operand" "=d") |
7772 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 7773 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7774 | "" |
7775 | "") | |
7776 | ||
26a89301 | 7777 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 7778 | [(set (reg CC_REGNUM) |
26a89301 UW |
7779 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
7780 | (match_operand:SI 1 "register_operand" "d") 0) | |
7781 | (const_int 32)) (const_int 32))) | |
7782 | (const_int 0))) | |
7783 | (set (match_operand:DI 0 "register_operand" "=d") | |
7784 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 7785 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 7786 | "lcgfr\t%0,%1" |
729e750f WG |
7787 | [(set_attr "op_type" "RRE") |
7788 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 7789 | |
26a89301 UW |
7790 | (define_insn "*negdi2_sign" |
7791 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7792 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 7793 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7794 | "TARGET_ZARCH" |
26a89301 | 7795 | "lcgfr\t%0,%1" |
729e750f WG |
7796 | [(set_attr "op_type" "RRE") |
7797 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 7798 | |
43a09b63 | 7799 | ; lcr, lcgr |
9a91a21f | 7800 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 7801 | [(set (reg CC_REGNUM) |
9a91a21f | 7802 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 7803 | (const_int 0))) |
9a91a21f AS |
7804 | (set (match_operand:GPR 0 "register_operand" "=d") |
7805 | (neg:GPR (match_dup 1)))] | |
7806 | "s390_match_ccmode (insn, CCAmode)" | |
7807 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
7808 | [(set_attr "op_type" "RR<E>") |
7809 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
7810 | |
7811 | ; lcr, lcgr | |
9a91a21f | 7812 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 7813 | [(set (reg CC_REGNUM) |
9a91a21f | 7814 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 7815 | (const_int 0))) |
9a91a21f AS |
7816 | (clobber (match_scratch:GPR 0 "=d"))] |
7817 | "s390_match_ccmode (insn, CCAmode)" | |
7818 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
7819 | [(set_attr "op_type" "RR<E>") |
7820 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
7821 | |
7822 | ; lcr, lcgr | |
9a91a21f AS |
7823 | (define_insn "*neg<mode>2" |
7824 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7825 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 7826 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
7827 | "" |
7828 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
7829 | [(set_attr "op_type" "RR<E>") |
7830 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 7831 | |
b7d19263 | 7832 | (define_insn "*negdi2_31" |
9db1d521 HP |
7833 | [(set (match_operand:DI 0 "register_operand" "=d") |
7834 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 7835 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7836 | "!TARGET_ZARCH" |
b7d19263 AK |
7837 | "#") |
7838 | ||
7839 | ; Split a DImode NEG on 31bit into 2 SImode NEGs | |
7840 | ||
7841 | ; Doing the twos complement separately on the SImode parts does an | |
7842 | ; unwanted +1 on the high part which needs to be subtracted afterwards | |
7843 | ; ... unless the +1 on the low part created an overflow. | |
7844 | ||
7845 | (define_split | |
7846 | [(set (match_operand:DI 0 "register_operand" "") | |
7847 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
7848 | (clobber (reg:CC CC_REGNUM))] | |
7849 | "!TARGET_ZARCH | |
7850 | && (REGNO (operands[0]) == REGNO (operands[1]) | |
7851 | || s390_split_ok_p (operands[0], operands[1], DImode, 0)) | |
7852 | && reload_completed" | |
26a89301 UW |
7853 | [(parallel |
7854 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 7855 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 7856 | (parallel |
ae156f85 | 7857 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
7858 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
7859 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
7860 | (set (pc) | |
ae156f85 | 7861 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
7862 | (pc) |
7863 | (label_ref (match_dup 6)))) | |
7864 | (parallel | |
7865 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 7866 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
7867 | (match_dup 6)] |
7868 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
7869 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
7870 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
7871 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
7872 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 7873 | |
b7d19263 AK |
7874 | ; Like above but first make a copy of the low part of the src operand |
7875 | ; since it might overlap with the high part of the destination. | |
7876 | ||
7877 | (define_split | |
7878 | [(set (match_operand:DI 0 "register_operand" "") | |
7879 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
7880 | (clobber (reg:CC CC_REGNUM))] | |
7881 | "!TARGET_ZARCH | |
7882 | && s390_split_ok_p (operands[0], operands[1], DImode, 1) | |
7883 | && reload_completed" | |
7884 | [; Make a backup of op5 first | |
7885 | (set (match_dup 4) (match_dup 5)) | |
7886 | ; Setting op2 here might clobber op5 | |
7887 | (parallel | |
7888 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
7889 | (clobber (reg:CC CC_REGNUM))]) | |
7890 | (parallel | |
7891 | [(set (reg:CCAP CC_REGNUM) | |
7892 | (compare:CCAP (neg:SI (match_dup 4)) (const_int 0))) | |
7893 | (set (match_dup 4) (neg:SI (match_dup 4)))]) | |
7894 | (set (pc) | |
7895 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) | |
7896 | (pc) | |
7897 | (label_ref (match_dup 6)))) | |
7898 | (parallel | |
7899 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
7900 | (clobber (reg:CC CC_REGNUM))]) | |
7901 | (match_dup 6)] | |
7902 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
7903 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
7904 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
7905 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
7906 | operands[6] = gen_label_rtx ();") | |
7907 | ||
9db1d521 | 7908 | ; |
f5905b37 | 7909 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
7910 | ; |
7911 | ||
f5905b37 | 7912 | (define_expand "neg<mode>2" |
9db1d521 | 7913 | [(parallel |
7b6baae1 AK |
7914 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7915 | (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7916 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7917 | "TARGET_HARD_FLOAT" |
7918 | "") | |
7919 | ||
43a09b63 | 7920 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 7921 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 7922 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7923 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
7924 | (match_operand:BFP 2 "const0_operand" ""))) | |
7925 | (set (match_operand:BFP 0 "register_operand" "=f") | |
7926 | (neg:BFP (match_dup 1)))] | |
142cd70f | 7927 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7928 | "lc<xde>br\t%0,%1" |
26a89301 | 7929 | [(set_attr "op_type" "RRE") |
f5905b37 | 7930 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
7931 | |
7932 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 7933 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 7934 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7935 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
7936 | (match_operand:BFP 2 "const0_operand" ""))) | |
7937 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 7938 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7939 | "lc<xde>br\t%0,%1" |
26a89301 | 7940 | [(set_attr "op_type" "RRE") |
f5905b37 | 7941 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 7942 | |
85dae55a AK |
7943 | ; lcdfr |
7944 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
7945 | [(set (match_operand:FP 0 "register_operand" "=f") |
7946 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 7947 | "TARGET_DFP" |
85dae55a AK |
7948 | "lcdfr\t%0,%1" |
7949 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 7950 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 7951 | |
43a09b63 | 7952 | ; lcxbr, lcdbr, lcebr |
6e5b5de8 | 7953 | ; FIXME: wflcdb does not clobber cc |
f5905b37 | 7954 | (define_insn "*neg<mode>2" |
6e5b5de8 AK |
7955 | [(set (match_operand:BFP 0 "register_operand" "=f,<vf>") |
7956 | (neg:BFP (match_operand:BFP 1 "register_operand" "f,<vf>"))) | |
ae156f85 | 7957 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 7958 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
7959 | "@ |
7960 | lc<xde>br\t%0,%1 | |
7961 | wflcdb\t%0,%1" | |
7962 | [(set_attr "op_type" "RRE,VRR") | |
7963 | (set_attr "cpu_facility" "*,vec") | |
7964 | (set_attr "type" "fsimp<mode>,*")]) | |
9db1d521 | 7965 | |
9db1d521 HP |
7966 | |
7967 | ;; | |
7968 | ;;- Absolute value instructions. | |
7969 | ;; | |
7970 | ||
7971 | ; | |
9a91a21f | 7972 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
7973 | ; |
7974 | ||
26a89301 | 7975 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 7976 | [(set (reg CC_REGNUM) |
26a89301 UW |
7977 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
7978 | (match_operand:SI 1 "register_operand" "d") 0) | |
7979 | (const_int 32)) (const_int 32))) | |
7980 | (const_int 0))) | |
7981 | (set (match_operand:DI 0 "register_operand" "=d") | |
7982 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 7983 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 7984 | "lpgfr\t%0,%1" |
729e750f WG |
7985 | [(set_attr "op_type" "RRE") |
7986 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
7987 | |
7988 | (define_insn "*absdi2_sign" | |
7989 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7990 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 7991 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7992 | "TARGET_ZARCH" |
26a89301 | 7993 | "lpgfr\t%0,%1" |
729e750f WG |
7994 | [(set_attr "op_type" "RRE") |
7995 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 7996 | |
43a09b63 | 7997 | ; lpr, lpgr |
9a91a21f | 7998 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 7999 | [(set (reg CC_REGNUM) |
9a91a21f | 8000 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 8001 | (const_int 0))) |
9a91a21f AS |
8002 | (set (match_operand:GPR 0 "register_operand" "=d") |
8003 | (abs:GPR (match_dup 1)))] | |
26a89301 | 8004 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8005 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8006 | [(set_attr "op_type" "RR<E>") |
8007 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 8008 | |
9381e3f1 | 8009 | ; lpr, lpgr |
9a91a21f | 8010 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8011 | [(set (reg CC_REGNUM) |
9a91a21f | 8012 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8013 | (const_int 0))) |
9a91a21f | 8014 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8015 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8016 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8017 | [(set_attr "op_type" "RR<E>") |
8018 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8019 | |
8020 | ; lpr, lpgr | |
9a91a21f AS |
8021 | (define_insn "abs<mode>2" |
8022 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8023 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8024 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 8025 | "" |
9a91a21f | 8026 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8027 | [(set_attr "op_type" "RR<E>") |
8028 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 8029 | |
9db1d521 | 8030 | ; |
f5905b37 | 8031 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8032 | ; |
8033 | ||
f5905b37 | 8034 | (define_expand "abs<mode>2" |
9db1d521 | 8035 | [(parallel |
7b6baae1 AK |
8036 | [(set (match_operand:BFP 0 "register_operand" "=f") |
8037 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 8038 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8039 | "TARGET_HARD_FLOAT" |
8040 | "") | |
8041 | ||
43a09b63 | 8042 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 8043 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8044 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8045 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8046 | (match_operand:BFP 2 "const0_operand" ""))) | |
8047 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8048 | (abs:BFP (match_dup 1)))] | |
142cd70f | 8049 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8050 | "lp<xde>br\t%0,%1" |
26a89301 | 8051 | [(set_attr "op_type" "RRE") |
f5905b37 | 8052 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8053 | |
8054 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 8055 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8056 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8057 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8058 | (match_operand:BFP 2 "const0_operand" ""))) | |
8059 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8060 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8061 | "lp<xde>br\t%0,%1" |
26a89301 | 8062 | [(set_attr "op_type" "RRE") |
f5905b37 | 8063 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8064 | |
85dae55a AK |
8065 | ; lpdfr |
8066 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
8067 | [(set (match_operand:FP 0 "register_operand" "=f") |
8068 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8069 | "TARGET_DFP" |
85dae55a AK |
8070 | "lpdfr\t%0,%1" |
8071 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8072 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8073 | |
43a09b63 | 8074 | ; lpxbr, lpdbr, lpebr |
6e5b5de8 | 8075 | ; FIXME: wflpdb does not clobber cc |
f5905b37 | 8076 | (define_insn "*abs<mode>2" |
6e5b5de8 AK |
8077 | [(set (match_operand:BFP 0 "register_operand" "=f,<vf>") |
8078 | (abs:BFP (match_operand:BFP 1 "register_operand" "f,<vf>"))) | |
ae156f85 | 8079 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8080 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8081 | "@ |
8082 | lp<xde>br\t%0,%1 | |
8083 | wflpdb\t%0,%1" | |
8084 | [(set_attr "op_type" "RRE,VRR") | |
8085 | (set_attr "cpu_facility" "*,vec") | |
8086 | (set_attr "type" "fsimp<mode>,*")]) | |
9db1d521 | 8087 | |
9db1d521 | 8088 | |
3ef093a8 AK |
8089 | ;; |
8090 | ;;- Negated absolute value instructions | |
8091 | ;; | |
8092 | ||
8093 | ; | |
8094 | ; Integer | |
8095 | ; | |
8096 | ||
26a89301 | 8097 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 8098 | [(set (reg CC_REGNUM) |
26a89301 UW |
8099 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8100 | (match_operand:SI 1 "register_operand" "d") 0) | |
8101 | (const_int 32)) (const_int 32)))) | |
8102 | (const_int 0))) | |
8103 | (set (match_operand:DI 0 "register_operand" "=d") | |
8104 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
9602b6a1 | 8105 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8106 | "lngfr\t%0,%1" |
729e750f WG |
8107 | [(set_attr "op_type" "RRE") |
8108 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8109 | |
26a89301 UW |
8110 | (define_insn "*negabsdi2_sign" |
8111 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8112 | (neg:DI (abs:DI (sign_extend:DI | |
8113 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 8114 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8115 | "TARGET_ZARCH" |
26a89301 | 8116 | "lngfr\t%0,%1" |
729e750f WG |
8117 | [(set_attr "op_type" "RRE") |
8118 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 8119 | |
43a09b63 | 8120 | ; lnr, lngr |
9a91a21f | 8121 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8122 | [(set (reg CC_REGNUM) |
9a91a21f | 8123 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8124 | (const_int 0))) |
9a91a21f AS |
8125 | (set (match_operand:GPR 0 "register_operand" "=d") |
8126 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 8127 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8128 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8129 | [(set_attr "op_type" "RR<E>") |
8130 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8131 | |
8132 | ; lnr, lngr | |
9a91a21f | 8133 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8134 | [(set (reg CC_REGNUM) |
9a91a21f | 8135 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8136 | (const_int 0))) |
9a91a21f | 8137 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8138 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8139 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8140 | [(set_attr "op_type" "RR<E>") |
8141 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8142 | |
8143 | ; lnr, lngr | |
9a91a21f AS |
8144 | (define_insn "*negabs<mode>2" |
8145 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8146 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 8147 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 8148 | "" |
9a91a21f | 8149 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8150 | [(set_attr "op_type" "RR<E>") |
8151 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8152 | |
3ef093a8 AK |
8153 | ; |
8154 | ; Floating point | |
8155 | ; | |
8156 | ||
43a09b63 | 8157 | ; lnxbr, lndbr, lnebr |
f5905b37 | 8158 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8159 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8160 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8161 | (match_operand:BFP 2 "const0_operand" ""))) | |
8162 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8163 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 8164 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8165 | "ln<xde>br\t%0,%1" |
26a89301 | 8166 | [(set_attr "op_type" "RRE") |
f5905b37 | 8167 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8168 | |
8169 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 8170 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8171 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8172 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8173 | (match_operand:BFP 2 "const0_operand" ""))) | |
8174 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8175 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8176 | "ln<xde>br\t%0,%1" |
26a89301 | 8177 | [(set_attr "op_type" "RRE") |
f5905b37 | 8178 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8179 | |
85dae55a AK |
8180 | ; lndfr |
8181 | (define_insn "*negabs<mode>2_nocc" | |
609e7e80 AK |
8182 | [(set (match_operand:FP 0 "register_operand" "=f") |
8183 | (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 8184 | "TARGET_DFP" |
85dae55a AK |
8185 | "lndfr\t%0,%1" |
8186 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8187 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8188 | |
43a09b63 | 8189 | ; lnxbr, lndbr, lnebr |
6e5b5de8 | 8190 | ; FIXME: wflndb does not clobber cc |
f5905b37 | 8191 | (define_insn "*negabs<mode>2" |
6e5b5de8 AK |
8192 | [(set (match_operand:BFP 0 "register_operand" "=f,<vf>") |
8193 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,<vf>")))) | |
ae156f85 | 8194 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8195 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8196 | "@ |
8197 | ln<xde>br\t%0,%1 | |
8198 | wflndb\t%0,%1" | |
8199 | [(set_attr "op_type" "RRE,VRR") | |
8200 | (set_attr "cpu_facility" "*,vec") | |
8201 | (set_attr "type" "fsimp<mode>,*")]) | |
26a89301 | 8202 | |
4023fb28 UW |
8203 | ;; |
8204 | ;;- Square root instructions. | |
8205 | ;; | |
8206 | ||
8207 | ; | |
f5905b37 | 8208 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
8209 | ; |
8210 | ||
9381e3f1 | 8211 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 8212 | (define_insn "sqrt<mode>2" |
6e5b5de8 AK |
8213 | [(set (match_operand:BFP 0 "register_operand" "=f, f,<vf>") |
8214 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>,<vf>")))] | |
142cd70f | 8215 | "TARGET_HARD_FLOAT" |
4023fb28 | 8216 | "@ |
f61a2c7d | 8217 | sq<xde>br\t%0,%1 |
6e5b5de8 AK |
8218 | sq<xde>b\t%0,%1 |
8219 | wfsqdb\t%v0,%v1" | |
8220 | [(set_attr "op_type" "RRE,RXE,VRR") | |
8221 | (set_attr "type" "fsqrt<mode>") | |
8222 | (set_attr "cpu_facility" "*,*,vec")]) | |
4023fb28 | 8223 | |
9db1d521 HP |
8224 | |
8225 | ;; | |
8226 | ;;- One complement instructions. | |
8227 | ;; | |
8228 | ||
8229 | ; | |
342cf42b | 8230 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 8231 | ; |
c7453384 | 8232 | |
342cf42b | 8233 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 8234 | [(parallel |
342cf42b AS |
8235 | [(set (match_operand:INT 0 "register_operand" "") |
8236 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
8237 | (const_int -1))) | |
ae156f85 | 8238 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 8239 | "" |
4023fb28 | 8240 | "") |
9db1d521 HP |
8241 | |
8242 | ||
ec24698e UW |
8243 | ;; |
8244 | ;; Find leftmost bit instructions. | |
8245 | ;; | |
8246 | ||
8247 | (define_expand "clzdi2" | |
8248 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8249 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 8250 | "TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
8251 | { |
8252 | rtx insn, clz_equal; | |
8253 | rtx wide_reg = gen_reg_rtx (TImode); | |
8254 | rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63); | |
8255 | ||
8256 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
8257 | ||
8258 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
8259 | ||
9381e3f1 | 8260 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 8261 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
8262 | |
8263 | DONE; | |
8264 | }) | |
8265 | ||
8266 | (define_insn "clztidi2" | |
8267 | [(set (match_operand:TI 0 "register_operand" "=d") | |
8268 | (ior:TI | |
9381e3f1 WG |
8269 | (ashift:TI |
8270 | (zero_extend:TI | |
ec24698e UW |
8271 | (xor:DI (match_operand:DI 1 "register_operand" "d") |
8272 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
8273 | (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
9381e3f1 | 8274 | |
ec24698e UW |
8275 | (const_int 64)) |
8276 | (zero_extend:TI (clz:DI (match_dup 1))))) | |
8277 | (clobber (reg:CC CC_REGNUM))] | |
9381e3f1 | 8278 | "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) |
ec24698e | 8279 | == (unsigned HOST_WIDE_INT) 1 << 63 |
9602b6a1 | 8280 | && TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
8281 | "flogr\t%0,%1" |
8282 | [(set_attr "op_type" "RRE")]) | |
8283 | ||
8284 | ||
9db1d521 HP |
8285 | ;; |
8286 | ;;- Rotate instructions. | |
8287 | ;; | |
8288 | ||
8289 | ; | |
9a91a21f | 8290 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
8291 | ; |
8292 | ||
43a09b63 | 8293 | ; rll, rllg |
9a91a21f AS |
8294 | (define_insn "rotl<mode>3" |
8295 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8296 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
4989e88a | 8297 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9e8327e3 | 8298 | "TARGET_CPU_ZARCH" |
9a91a21f | 8299 | "rll<g>\t%0,%1,%Y2" |
077dab3b | 8300 | [(set_attr "op_type" "RSE") |
9381e3f1 WG |
8301 | (set_attr "atype" "reg") |
8302 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 8303 | |
43a09b63 | 8304 | ; rll, rllg |
4989e88a AK |
8305 | (define_insn "*rotl<mode>3_and" |
8306 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8307 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
8308 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
8309 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
8310 | "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63" | |
8311 | "rll<g>\t%0,%1,%Y2" | |
8312 | [(set_attr "op_type" "RSE") | |
9381e3f1 WG |
8313 | (set_attr "atype" "reg") |
8314 | (set_attr "z10prop" "z10_super_E1")]) | |
4989e88a | 8315 | |
9db1d521 HP |
8316 | |
8317 | ;; | |
f337b930 | 8318 | ;;- Shift instructions. |
9db1d521 | 8319 | ;; |
9db1d521 HP |
8320 | |
8321 | ; | |
1b48c8cc | 8322 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
65b1d8ea | 8323 | ; Left shifts and logical right shifts |
9db1d521 | 8324 | |
1b48c8cc AS |
8325 | (define_expand "<shift><mode>3" |
8326 | [(set (match_operand:DSI 0 "register_operand" "") | |
8327 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
8328 | (match_operand:SI 2 "shift_count_or_setmem_operand" "")))] | |
9db1d521 HP |
8329 | "" |
8330 | "") | |
8331 | ||
43a09b63 | 8332 | ; sldl, srdl |
f337b930 | 8333 | (define_insn "*<shift>di3_31" |
ac32b25e | 8334 | [(set (match_operand:DI 0 "register_operand" "=d") |
f337b930 | 8335 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 8336 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9602b6a1 | 8337 | "!TARGET_ZARCH" |
f337b930 | 8338 | "s<lr>dl\t%0,%Y2" |
077dab3b | 8339 | [(set_attr "op_type" "RS") |
65b1d8ea AK |
8340 | (set_attr "atype" "reg") |
8341 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8342 | |
65b1d8ea | 8343 | ; sll, srl, sllg, srlg, sllk, srlk |
1b48c8cc | 8344 | (define_insn "*<shift><mode>3" |
65b1d8ea AK |
8345 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
8346 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
8347 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))] | |
1b48c8cc | 8348 | "" |
65b1d8ea AK |
8349 | "@ |
8350 | s<lr>l<g>\t%0,<1>%Y2 | |
8351 | s<lr>l<gk>\t%0,%1,%Y2" | |
8352 | [(set_attr "op_type" "RS<E>,RSY") | |
8353 | (set_attr "atype" "reg,reg") | |
8354 | (set_attr "cpu_facility" "*,z196") | |
8355 | (set_attr "z10prop" "z10_super_E1,*")]) | |
9db1d521 | 8356 | |
43a09b63 | 8357 | ; sldl, srdl |
4989e88a AK |
8358 | (define_insn "*<shift>di3_31_and" |
8359 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8360 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
8361 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
8362 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
9602b6a1 | 8363 | "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" |
4989e88a AK |
8364 | "s<lr>dl\t%0,%Y2" |
8365 | [(set_attr "op_type" "RS") | |
8366 | (set_attr "atype" "reg")]) | |
8367 | ||
65b1d8ea | 8368 | ; sll, srl, sllg, srlg, sllk, srlk |
1b48c8cc | 8369 | (define_insn "*<shift><mode>3_and" |
65b1d8ea AK |
8370 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
8371 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
8372 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
8373 | (match_operand:SI 3 "const_int_operand" "n,n"))))] | |
1b48c8cc | 8374 | "(INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
8375 | "@ |
8376 | s<lr>l<g>\t%0,<1>%Y2 | |
8377 | s<lr>l<gk>\t%0,%1,%Y2" | |
8378 | [(set_attr "op_type" "RS<E>,RSY") | |
8379 | (set_attr "atype" "reg,reg") | |
8380 | (set_attr "cpu_facility" "*,z196") | |
8381 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 8382 | |
9db1d521 | 8383 | ; |
1b48c8cc | 8384 | ; ashr(di|si)3 instruction pattern(s). |
65b1d8ea | 8385 | ; Arithmetic right shifts |
9db1d521 | 8386 | |
1b48c8cc | 8387 | (define_expand "ashr<mode>3" |
9db1d521 | 8388 | [(parallel |
1b48c8cc AS |
8389 | [(set (match_operand:DSI 0 "register_operand" "") |
8390 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
8391 | (match_operand:SI 2 "shift_count_or_setmem_operand" ""))) | |
ae156f85 | 8392 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8393 | "" |
8394 | "") | |
8395 | ||
ecbe845e | 8396 | (define_insn "*ashrdi3_cc_31" |
ae156f85 | 8397 | [(set (reg CC_REGNUM) |
ac32b25e | 8398 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 8399 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 8400 | (const_int 0))) |
ac32b25e | 8401 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e | 8402 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 8403 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 8404 | "srda\t%0,%Y2" |
077dab3b HP |
8405 | [(set_attr "op_type" "RS") |
8406 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
8407 | |
8408 | (define_insn "*ashrdi3_cconly_31" | |
ae156f85 | 8409 | [(set (reg CC_REGNUM) |
ac32b25e | 8410 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 8411 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 8412 | (const_int 0))) |
ac32b25e | 8413 | (clobber (match_scratch:DI 0 "=d"))] |
9602b6a1 | 8414 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 8415 | "srda\t%0,%Y2" |
077dab3b HP |
8416 | [(set_attr "op_type" "RS") |
8417 | (set_attr "atype" "reg")]) | |
ecbe845e | 8418 | |
9db1d521 | 8419 | (define_insn "*ashrdi3_31" |
ac32b25e UW |
8420 | [(set (match_operand:DI 0 "register_operand" "=d") |
8421 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
4989e88a | 8422 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) |
ae156f85 | 8423 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8424 | "!TARGET_ZARCH" |
ac32b25e | 8425 | "srda\t%0,%Y2" |
077dab3b HP |
8426 | [(set_attr "op_type" "RS") |
8427 | (set_attr "atype" "reg")]) | |
c7453384 | 8428 | |
65b1d8ea | 8429 | ; sra, srag, srak |
1b48c8cc | 8430 | (define_insn "*ashr<mode>3_cc" |
ae156f85 | 8431 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8432 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
8433 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) | |
ecbe845e | 8434 | (const_int 0))) |
65b1d8ea | 8435 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
1b48c8cc AS |
8436 | (ashiftrt:GPR (match_dup 1) (match_dup 2)))] |
8437 | "s390_match_ccmode(insn, CCSmode)" | |
65b1d8ea AK |
8438 | "@ |
8439 | sra<g>\t%0,<1>%Y2 | |
8440 | sra<gk>\t%0,%1,%Y2" | |
8441 | [(set_attr "op_type" "RS<E>,RSY") | |
8442 | (set_attr "atype" "reg,reg") | |
8443 | (set_attr "cpu_facility" "*,z196") | |
8444 | (set_attr "z10prop" "z10_super_E1,*")]) | |
ecbe845e | 8445 | |
65b1d8ea | 8446 | ; sra, srag, srak |
1b48c8cc | 8447 | (define_insn "*ashr<mode>3_cconly" |
ae156f85 | 8448 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8449 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
8450 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) | |
ecbe845e | 8451 | (const_int 0))) |
65b1d8ea | 8452 | (clobber (match_scratch:GPR 0 "=d,d"))] |
1b48c8cc | 8453 | "s390_match_ccmode(insn, CCSmode)" |
65b1d8ea AK |
8454 | "@ |
8455 | sra<g>\t%0,<1>%Y2 | |
8456 | sra<gk>\t%0,%1,%Y2" | |
8457 | [(set_attr "op_type" "RS<E>,RSY") | |
8458 | (set_attr "atype" "reg,reg") | |
8459 | (set_attr "cpu_facility" "*,z196") | |
8460 | (set_attr "z10prop" "z10_super_E1,*")]) | |
ecbe845e | 8461 | |
43a09b63 | 8462 | ; sra, srag |
1b48c8cc | 8463 | (define_insn "*ashr<mode>3" |
65b1d8ea AK |
8464 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
8465 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
8466 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))) | |
ae156f85 | 8467 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc | 8468 | "" |
65b1d8ea AK |
8469 | "@ |
8470 | sra<g>\t%0,<1>%Y2 | |
8471 | sra<gk>\t%0,%1,%Y2" | |
8472 | [(set_attr "op_type" "RS<E>,RSY") | |
8473 | (set_attr "atype" "reg,reg") | |
8474 | (set_attr "cpu_facility" "*,z196") | |
8475 | (set_attr "z10prop" "z10_super_E1,*")]) | |
077dab3b | 8476 | |
9db1d521 | 8477 | |
4989e88a AK |
8478 | ; shift pattern with implicit ANDs |
8479 | ||
8480 | (define_insn "*ashrdi3_cc_31_and" | |
8481 | [(set (reg CC_REGNUM) | |
8482 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
8483 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
8484 | (match_operand:SI 3 "const_int_operand" "n"))) | |
8485 | (const_int 0))) | |
8486 | (set (match_operand:DI 0 "register_operand" "=d") | |
8487 | (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] | |
9602b6a1 | 8488 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) |
4989e88a AK |
8489 | && (INTVAL (operands[3]) & 63) == 63" |
8490 | "srda\t%0,%Y2" | |
8491 | [(set_attr "op_type" "RS") | |
8492 | (set_attr "atype" "reg")]) | |
8493 | ||
8494 | (define_insn "*ashrdi3_cconly_31_and" | |
8495 | [(set (reg CC_REGNUM) | |
8496 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
8497 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
8498 | (match_operand:SI 3 "const_int_operand" "n"))) | |
8499 | (const_int 0))) | |
8500 | (clobber (match_scratch:DI 0 "=d"))] | |
9602b6a1 | 8501 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) |
4989e88a AK |
8502 | && (INTVAL (operands[3]) & 63) == 63" |
8503 | "srda\t%0,%Y2" | |
8504 | [(set_attr "op_type" "RS") | |
8505 | (set_attr "atype" "reg")]) | |
8506 | ||
8507 | (define_insn "*ashrdi3_31_and" | |
8508 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8509 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
8510 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
8511 | (match_operand:SI 3 "const_int_operand" "n")))) | |
8512 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8513 | "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" |
4989e88a AK |
8514 | "srda\t%0,%Y2" |
8515 | [(set_attr "op_type" "RS") | |
8516 | (set_attr "atype" "reg")]) | |
8517 | ||
65b1d8ea | 8518 | ; sra, srag, srak |
1b48c8cc | 8519 | (define_insn "*ashr<mode>3_cc_and" |
4989e88a | 8520 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8521 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
8522 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
8523 | (match_operand:SI 3 "const_int_operand" "n,n"))) | |
4989e88a | 8524 | (const_int 0))) |
65b1d8ea | 8525 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
1b48c8cc | 8526 | (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] |
4989e88a | 8527 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
8528 | "@ |
8529 | sra<g>\t%0,<1>%Y2 | |
8530 | sra<gk>\t%0,%1,%Y2" | |
8531 | [(set_attr "op_type" "RS<E>,RSY") | |
8532 | (set_attr "atype" "reg,reg") | |
8533 | (set_attr "cpu_facility" "*,z196") | |
8534 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 8535 | |
65b1d8ea | 8536 | ; sra, srag, srak |
1b48c8cc | 8537 | (define_insn "*ashr<mode>3_cconly_and" |
4989e88a | 8538 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8539 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
8540 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
8541 | (match_operand:SI 3 "const_int_operand" "n,n"))) | |
4989e88a | 8542 | (const_int 0))) |
65b1d8ea | 8543 | (clobber (match_scratch:GPR 0 "=d,d"))] |
4989e88a | 8544 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
8545 | "@ |
8546 | sra<g>\t%0,<1>%Y2 | |
8547 | sra<gk>\t%0,%1,%Y2" | |
8548 | [(set_attr "op_type" "RS<E>,RSY") | |
8549 | (set_attr "atype" "reg,reg") | |
8550 | (set_attr "cpu_facility" "*,z196") | |
8551 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 8552 | |
65b1d8ea | 8553 | ; sra, srag, srak |
1b48c8cc | 8554 | (define_insn "*ashr<mode>3_and" |
65b1d8ea AK |
8555 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
8556 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
8557 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
8558 | (match_operand:SI 3 "const_int_operand" "n,n")))) | |
4989e88a AK |
8559 | (clobber (reg:CC CC_REGNUM))] |
8560 | "(INTVAL (operands[3]) & 63) == 63" | |
65b1d8ea AK |
8561 | "@ |
8562 | sra<g>\t%0,<1>%Y2 | |
8563 | sra<gk>\t%0,%1,%Y2" | |
8564 | [(set_attr "op_type" "RS<E>,RSY") | |
8565 | (set_attr "atype" "reg,reg") | |
01496eca | 8566 | (set_attr "cpu_facility" "*,z196") |
65b1d8ea | 8567 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8568 | |
9db1d521 | 8569 | |
9db1d521 HP |
8570 | ;; |
8571 | ;; Branch instruction patterns. | |
8572 | ;; | |
8573 | ||
f90b7a5a | 8574 | (define_expand "cbranch<mode>4" |
fa77b251 | 8575 | [(set (pc) |
f90b7a5a PB |
8576 | (if_then_else (match_operator 0 "comparison_operator" |
8577 | [(match_operand:GPR 1 "register_operand" "") | |
8578 | (match_operand:GPR 2 "general_operand" "")]) | |
8579 | (label_ref (match_operand 3 "" "")) | |
fa77b251 | 8580 | (pc)))] |
ba956982 | 8581 | "" |
f90b7a5a PB |
8582 | "s390_emit_jump (operands[3], |
8583 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8584 | DONE;") | |
8585 | ||
8586 | (define_expand "cbranch<mode>4" | |
8587 | [(set (pc) | |
8588 | (if_then_else (match_operator 0 "comparison_operator" | |
8589 | [(match_operand:FP 1 "register_operand" "") | |
8590 | (match_operand:FP 2 "general_operand" "")]) | |
8591 | (label_ref (match_operand 3 "" "")) | |
8592 | (pc)))] | |
8593 | "TARGET_HARD_FLOAT" | |
8594 | "s390_emit_jump (operands[3], | |
8595 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8596 | DONE;") | |
8597 | ||
8598 | (define_expand "cbranchcc4" | |
8599 | [(set (pc) | |
de6fba39 | 8600 | (if_then_else (match_operator 0 "s390_comparison" |
f90b7a5a | 8601 | [(match_operand 1 "cc_reg_operand" "") |
de6fba39 | 8602 | (match_operand 2 "const_int_operand" "")]) |
f90b7a5a PB |
8603 | (label_ref (match_operand 3 "" "")) |
8604 | (pc)))] | |
de6fba39 UW |
8605 | "" |
8606 | "") | |
ba956982 | 8607 | |
9db1d521 HP |
8608 | |
8609 | ;; | |
8610 | ;;- Conditional jump instructions. | |
8611 | ;; | |
8612 | ||
6590e19a UW |
8613 | (define_insn "*cjump_64" |
8614 | [(set (pc) | |
8615 | (if_then_else | |
5a3fe9b6 AK |
8616 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
8617 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
8618 | (label_ref (match_operand 0 "" "")) |
8619 | (pc)))] | |
8620 | "TARGET_CPU_ZARCH" | |
9db1d521 | 8621 | { |
13e58269 | 8622 | if (get_attr_length (insn) == 4) |
d40c829f | 8623 | return "j%C1\t%l0"; |
6590e19a | 8624 | else |
d40c829f | 8625 | return "jg%C1\t%l0"; |
6590e19a UW |
8626 | } |
8627 | [(set_attr "op_type" "RI") | |
8628 | (set_attr "type" "branch") | |
8629 | (set (attr "length") | |
8630 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8631 | (const_int 4) (const_int 6)))]) | |
8632 | ||
8633 | (define_insn "*cjump_31" | |
8634 | [(set (pc) | |
8635 | (if_then_else | |
5a3fe9b6 AK |
8636 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
8637 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
8638 | (label_ref (match_operand 0 "" "")) |
8639 | (pc)))] | |
8640 | "!TARGET_CPU_ZARCH" | |
8641 | { | |
8d933e31 AS |
8642 | gcc_assert (get_attr_length (insn) == 4); |
8643 | return "j%C1\t%l0"; | |
10bbf137 | 8644 | } |
9db1d521 | 8645 | [(set_attr "op_type" "RI") |
077dab3b | 8646 | (set_attr "type" "branch") |
13e58269 | 8647 | (set (attr "length") |
d7f99b2c | 8648 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8649 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8650 | (const_int 4) (const_int 6)) | |
8651 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8652 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 8653 | |
f314b9b1 | 8654 | (define_insn "*cjump_long" |
6590e19a UW |
8655 | [(set (pc) |
8656 | (if_then_else | |
ae156f85 | 8657 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4fe6dea8 | 8658 | (match_operand 0 "address_operand" "ZQZR") |
6590e19a | 8659 | (pc)))] |
9db1d521 | 8660 | "" |
f314b9b1 UW |
8661 | { |
8662 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8663 | return "b%C1r\t%0"; |
f314b9b1 | 8664 | else |
d40c829f | 8665 | return "b%C1\t%a0"; |
10bbf137 | 8666 | } |
c7453384 | 8667 | [(set (attr "op_type") |
f314b9b1 UW |
8668 | (if_then_else (match_operand 0 "register_operand" "") |
8669 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 8670 | (set_attr "type" "branch") |
077dab3b | 8671 | (set_attr "atype" "agen")]) |
9db1d521 | 8672 | |
177bc204 RS |
8673 | ;; A conditional return instruction. |
8674 | (define_insn "*c<code>" | |
8675 | [(set (pc) | |
8676 | (if_then_else | |
8677 | (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
8678 | (ANY_RETURN) | |
8679 | (pc)))] | |
8680 | "s390_can_use_<code>_insn ()" | |
8681 | "b%C0r\t%%r14" | |
8682 | [(set_attr "op_type" "RR") | |
8683 | (set_attr "type" "jsr") | |
8684 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
8685 | |
8686 | ;; | |
8687 | ;;- Negated conditional jump instructions. | |
8688 | ;; | |
8689 | ||
6590e19a UW |
8690 | (define_insn "*icjump_64" |
8691 | [(set (pc) | |
8692 | (if_then_else | |
ae156f85 | 8693 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
8694 | (pc) |
8695 | (label_ref (match_operand 0 "" ""))))] | |
8696 | "TARGET_CPU_ZARCH" | |
c7453384 | 8697 | { |
13e58269 | 8698 | if (get_attr_length (insn) == 4) |
d40c829f | 8699 | return "j%D1\t%l0"; |
6590e19a | 8700 | else |
d40c829f | 8701 | return "jg%D1\t%l0"; |
6590e19a UW |
8702 | } |
8703 | [(set_attr "op_type" "RI") | |
8704 | (set_attr "type" "branch") | |
8705 | (set (attr "length") | |
8706 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8707 | (const_int 4) (const_int 6)))]) | |
8708 | ||
8709 | (define_insn "*icjump_31" | |
8710 | [(set (pc) | |
8711 | (if_then_else | |
ae156f85 | 8712 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
8713 | (pc) |
8714 | (label_ref (match_operand 0 "" ""))))] | |
8715 | "!TARGET_CPU_ZARCH" | |
8716 | { | |
8d933e31 AS |
8717 | gcc_assert (get_attr_length (insn) == 4); |
8718 | return "j%D1\t%l0"; | |
10bbf137 | 8719 | } |
9db1d521 | 8720 | [(set_attr "op_type" "RI") |
077dab3b | 8721 | (set_attr "type" "branch") |
13e58269 | 8722 | (set (attr "length") |
d7f99b2c | 8723 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8724 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8725 | (const_int 4) (const_int 6)) | |
8726 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8727 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 8728 | |
f314b9b1 | 8729 | (define_insn "*icjump_long" |
6590e19a UW |
8730 | [(set (pc) |
8731 | (if_then_else | |
ae156f85 | 8732 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a | 8733 | (pc) |
4fe6dea8 | 8734 | (match_operand 0 "address_operand" "ZQZR")))] |
9db1d521 | 8735 | "" |
f314b9b1 UW |
8736 | { |
8737 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8738 | return "b%D1r\t%0"; |
f314b9b1 | 8739 | else |
d40c829f | 8740 | return "b%D1\t%a0"; |
10bbf137 | 8741 | } |
c7453384 | 8742 | [(set (attr "op_type") |
f314b9b1 UW |
8743 | (if_then_else (match_operand 0 "register_operand" "") |
8744 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
8745 | (set_attr "type" "branch") |
8746 | (set_attr "atype" "agen")]) | |
9db1d521 | 8747 | |
4456530d HP |
8748 | ;; |
8749 | ;;- Trap instructions. | |
8750 | ;; | |
8751 | ||
8752 | (define_insn "trap" | |
8753 | [(trap_if (const_int 1) (const_int 0))] | |
8754 | "" | |
d40c829f | 8755 | "j\t.+2" |
6590e19a | 8756 | [(set_attr "op_type" "RI") |
077dab3b | 8757 | (set_attr "type" "branch")]) |
4456530d | 8758 | |
f90b7a5a PB |
8759 | (define_expand "ctrap<mode>4" |
8760 | [(trap_if (match_operator 0 "comparison_operator" | |
8761 | [(match_operand:GPR 1 "register_operand" "") | |
8762 | (match_operand:GPR 2 "general_operand" "")]) | |
8763 | (match_operand 3 "const0_operand" ""))] | |
4456530d | 8764 | "" |
f90b7a5a PB |
8765 | { |
8766 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
8767 | operands[1], operands[2]); | |
8768 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
8769 | DONE; | |
8770 | }) | |
8771 | ||
8772 | (define_expand "ctrap<mode>4" | |
8773 | [(trap_if (match_operator 0 "comparison_operator" | |
8774 | [(match_operand:FP 1 "register_operand" "") | |
8775 | (match_operand:FP 2 "general_operand" "")]) | |
8776 | (match_operand 3 "const0_operand" ""))] | |
8777 | "" | |
8778 | { | |
8779 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
8780 | operands[1], operands[2]); | |
8781 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
8782 | DONE; | |
8783 | }) | |
4456530d | 8784 | |
f90b7a5a PB |
8785 | (define_insn "condtrap" |
8786 | [(trap_if (match_operator 0 "s390_comparison" | |
8787 | [(match_operand 1 "cc_reg_operand" "c") | |
8788 | (const_int 0)]) | |
4456530d HP |
8789 | (const_int 0))] |
8790 | "" | |
d40c829f | 8791 | "j%C0\t.+2"; |
077dab3b HP |
8792 | [(set_attr "op_type" "RI") |
8793 | (set_attr "type" "branch")]) | |
9db1d521 | 8794 | |
963fc8d0 AK |
8795 | ; crt, cgrt, cit, cgit |
8796 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
8797 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
8798 | [(match_operand:GPR 1 "register_operand" "d,d") | |
8799 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
8800 | (const_int 0))] | |
8801 | "TARGET_Z10" | |
8802 | "@ | |
8803 | c<g>rt%C0\t%1,%2 | |
8804 | c<g>it%C0\t%1,%h2" | |
8805 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 8806 | (set_attr "type" "branch") |
729e750f | 8807 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 8808 | |
22ac2c2f | 8809 | ; clrt, clgrt, clfit, clgit, clt, clgt |
963fc8d0 AK |
8810 | (define_insn "*cmp_and_trap_unsigned_int<mode>" |
8811 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
22ac2c2f AK |
8812 | [(match_operand:GPR 1 "register_operand" "d,d, d") |
8813 | (match_operand:GPR 2 "general_operand" "d,D,RT")]) | |
963fc8d0 AK |
8814 | (const_int 0))] |
8815 | "TARGET_Z10" | |
8816 | "@ | |
8817 | cl<g>rt%C0\t%1,%2 | |
22ac2c2f AK |
8818 | cl<gf>it%C0\t%1,%x2 |
8819 | cl<g>t%C0\t%1,%2" | |
8820 | [(set_attr "op_type" "RRF,RIE,RSY") | |
8821 | (set_attr "type" "branch") | |
8822 | (set_attr "z10prop" "z10_super_c,z10_super,*") | |
8823 | (set_attr "cpu_facility" "z10,z10,zEC12")]) | |
8824 | ||
8825 | ; lat, lgat | |
8826 | (define_insn "*load_and_trap<mode>" | |
8827 | [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT") | |
8828 | (const_int 0)) | |
8829 | (const_int 0)) | |
8830 | (set (match_operand:GPR 1 "register_operand" "=d") | |
8831 | (match_dup 0))] | |
8832 | "TARGET_ZEC12" | |
8833 | "l<g>at\t%1,%0" | |
8834 | [(set_attr "op_type" "RXY")]) | |
8835 | ||
963fc8d0 | 8836 | |
9db1d521 | 8837 | ;; |
0a3bdf9d | 8838 | ;;- Loop instructions. |
9db1d521 | 8839 | ;; |
0a3bdf9d UW |
8840 | ;; This is all complicated by the fact that since this is a jump insn |
8841 | ;; we must handle our own output reloads. | |
c7453384 | 8842 | |
f1149235 AK |
8843 | ;; branch on index |
8844 | ||
8845 | ; This splitter will be matched by combine and has to add the 2 moves | |
8846 | ; necessary to load the compare and the increment values into a | |
8847 | ; register pair as needed by brxle. | |
8848 | ||
8849 | (define_insn_and_split "*brx_stage1_<GPR:mode>" | |
8850 | [(set (pc) | |
8851 | (if_then_else | |
8852 | (match_operator 6 "s390_brx_operator" | |
8853 | [(plus:GPR (match_operand:GPR 1 "register_operand" "") | |
8854 | (match_operand:GPR 2 "general_operand" "")) | |
8855 | (match_operand:GPR 3 "register_operand" "")]) | |
8856 | (label_ref (match_operand 0 "" "")) | |
8857 | (pc))) | |
8858 | (set (match_operand:GPR 4 "nonimmediate_operand" "") | |
8859 | (plus:GPR (match_dup 1) (match_dup 2))) | |
8860 | (clobber (match_scratch:GPR 5 ""))] | |
8861 | "TARGET_CPU_ZARCH" | |
8862 | "#" | |
8863 | "!reload_completed && !reload_in_progress" | |
8864 | [(set (match_dup 7) (match_dup 2)) ; the increment | |
8865 | (set (match_dup 8) (match_dup 3)) ; the comparison value | |
8866 | (parallel [(set (pc) | |
8867 | (if_then_else | |
8868 | (match_op_dup 6 | |
8869 | [(plus:GPR (match_dup 1) (match_dup 7)) | |
8870 | (match_dup 8)]) | |
8871 | (label_ref (match_dup 0)) | |
8872 | (pc))) | |
8873 | (set (match_dup 4) | |
8874 | (plus:GPR (match_dup 1) (match_dup 7))) | |
8875 | (clobber (match_dup 5)) | |
8876 | (clobber (reg:CC CC_REGNUM))])] | |
8877 | { | |
8878 | rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); | |
8879 | operands[7] = gen_lowpart (<GPR:MODE>mode, | |
8880 | gen_highpart (word_mode, dreg)); | |
8881 | operands[8] = gen_lowpart (<GPR:MODE>mode, | |
8882 | gen_lowpart (word_mode, dreg)); | |
8883 | }) | |
8884 | ||
8885 | ; brxlg, brxhg | |
8886 | ||
8887 | (define_insn_and_split "*brxg_64bit" | |
8888 | [(set (pc) | |
8889 | (if_then_else | |
8890 | (match_operator 5 "s390_brx_operator" | |
8891 | [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") | |
8892 | (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) | |
8893 | (subreg:DI (match_dup 2) 8)]) | |
8894 | (label_ref (match_operand 0 "" "")) | |
8895 | (pc))) | |
8896 | (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") | |
8897 | (plus:DI (match_dup 1) | |
8898 | (subreg:DI (match_dup 2) 0))) | |
8899 | (clobber (match_scratch:DI 4 "=X,&1,&?d")) | |
8900 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8901 | "TARGET_ZARCH" |
f1149235 AK |
8902 | { |
8903 | if (which_alternative != 0) | |
8904 | return "#"; | |
8905 | else if (get_attr_length (insn) == 6) | |
8906 | return "brx%E5g\t%1,%2,%l0"; | |
8907 | else | |
8908 | return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; | |
8909 | } | |
8910 | "&& reload_completed | |
8911 | && (!REG_P (operands[3]) | |
8912 | || !rtx_equal_p (operands[1], operands[3]))" | |
8913 | [(set (match_dup 4) (match_dup 1)) | |
8914 | (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) | |
8915 | (clobber (reg:CC CC_REGNUM))]) | |
8916 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) | |
8917 | (set (match_dup 3) (match_dup 4)) | |
8918 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
8919 | (label_ref (match_dup 0)) | |
8920 | (pc)))] | |
8921 | "" | |
8922 | [(set_attr "op_type" "RIE") | |
8923 | (set_attr "type" "branch") | |
8924 | (set (attr "length") | |
8925 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8926 | (const_int 6) (const_int 16)))]) | |
8927 | ||
8928 | ; brxle, brxh | |
8929 | ||
8930 | (define_insn_and_split "*brx_64bit" | |
8931 | [(set (pc) | |
8932 | (if_then_else | |
8933 | (match_operator 5 "s390_brx_operator" | |
8934 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
8935 | (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) | |
8936 | (subreg:SI (match_dup 2) 12)]) | |
8937 | (label_ref (match_operand 0 "" "")) | |
8938 | (pc))) | |
8939 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
8940 | (plus:SI (match_dup 1) | |
8941 | (subreg:SI (match_dup 2) 4))) | |
8942 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
8943 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8944 | "TARGET_ZARCH" |
f1149235 AK |
8945 | { |
8946 | if (which_alternative != 0) | |
8947 | return "#"; | |
8948 | else if (get_attr_length (insn) == 6) | |
8949 | return "brx%C5\t%1,%2,%l0"; | |
8950 | else | |
8951 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
8952 | } | |
8953 | "&& reload_completed | |
8954 | && (!REG_P (operands[3]) | |
8955 | || !rtx_equal_p (operands[1], operands[3]))" | |
8956 | [(set (match_dup 4) (match_dup 1)) | |
8957 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
8958 | (clobber (reg:CC CC_REGNUM))]) | |
8959 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) | |
8960 | (set (match_dup 3) (match_dup 4)) | |
8961 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
8962 | (label_ref (match_dup 0)) | |
8963 | (pc)))] | |
8964 | "" | |
8965 | [(set_attr "op_type" "RSI") | |
8966 | (set_attr "type" "branch") | |
8967 | (set (attr "length") | |
8968 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8969 | (const_int 6) (const_int 14)))]) | |
8970 | ||
8971 | ; brxle, brxh | |
8972 | ||
8973 | (define_insn_and_split "*brx_31bit" | |
8974 | [(set (pc) | |
8975 | (if_then_else | |
8976 | (match_operator 5 "s390_brx_operator" | |
8977 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
8978 | (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) | |
8979 | (subreg:SI (match_dup 2) 4)]) | |
8980 | (label_ref (match_operand 0 "" "")) | |
8981 | (pc))) | |
8982 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
8983 | (plus:SI (match_dup 1) | |
8984 | (subreg:SI (match_dup 2) 0))) | |
8985 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
8986 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8987 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1149235 AK |
8988 | { |
8989 | if (which_alternative != 0) | |
8990 | return "#"; | |
8991 | else if (get_attr_length (insn) == 6) | |
8992 | return "brx%C5\t%1,%2,%l0"; | |
8993 | else | |
8994 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
8995 | } | |
8996 | "&& reload_completed | |
8997 | && (!REG_P (operands[3]) | |
8998 | || !rtx_equal_p (operands[1], operands[3]))" | |
8999 | [(set (match_dup 4) (match_dup 1)) | |
9000 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) | |
9001 | (clobber (reg:CC CC_REGNUM))]) | |
9002 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9003 | (set (match_dup 3) (match_dup 4)) | |
9004 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9005 | (label_ref (match_dup 0)) | |
9006 | (pc)))] | |
9007 | "" | |
9008 | [(set_attr "op_type" "RSI") | |
9009 | (set_attr "type" "branch") | |
9010 | (set (attr "length") | |
9011 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9012 | (const_int 6) (const_int 14)))]) | |
9013 | ||
9014 | ||
9015 | ;; branch on count | |
9016 | ||
0a3bdf9d UW |
9017 | (define_expand "doloop_end" |
9018 | [(use (match_operand 0 "" "")) ; loop pseudo | |
1d0216c8 | 9019 | (use (match_operand 1 "" ""))] ; label |
0a3bdf9d | 9020 | "" |
0a3bdf9d | 9021 | { |
6590e19a | 9022 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
1d0216c8 | 9023 | emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0])); |
6590e19a | 9024 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) |
1d0216c8 | 9025 | emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0])); |
9602b6a1 | 9026 | else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) |
1d0216c8 | 9027 | emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0])); |
0a3bdf9d UW |
9028 | else |
9029 | FAIL; | |
9030 | ||
9031 | DONE; | |
10bbf137 | 9032 | }) |
0a3bdf9d | 9033 | |
6590e19a | 9034 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
9035 | [(set (pc) |
9036 | (if_then_else | |
7e665d18 | 9037 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9038 | (const_int 1)) |
9039 | (label_ref (match_operand 0 "" "")) | |
9040 | (pc))) | |
7e665d18 | 9041 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9042 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9043 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9044 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 9045 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
9046 | { |
9047 | if (which_alternative != 0) | |
10bbf137 | 9048 | return "#"; |
0a3bdf9d | 9049 | else if (get_attr_length (insn) == 4) |
d40c829f | 9050 | return "brct\t%1,%l0"; |
6590e19a | 9051 | else |
545d16ff | 9052 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
9053 | } |
9054 | "&& reload_completed | |
9055 | && (! REG_P (operands[2]) | |
9056 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9057 | [(set (match_dup 3) (match_dup 1)) |
9058 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9059 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9060 | (const_int 0))) | |
9061 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9062 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9063 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9064 | (label_ref (match_dup 0)) |
9065 | (pc)))] | |
9066 | "" | |
9067 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9068 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9069 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9070 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9071 | (set_attr "type" "branch") |
9072 | (set (attr "length") | |
9073 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9074 | (const_int 4) (const_int 10)))]) | |
9075 | ||
9076 | (define_insn_and_split "doloop_si31" | |
9077 | [(set (pc) | |
9078 | (if_then_else | |
7e665d18 | 9079 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
6590e19a UW |
9080 | (const_int 1)) |
9081 | (label_ref (match_operand 0 "" "")) | |
9082 | (pc))) | |
7e665d18 | 9083 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
6590e19a | 9084 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9085 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9086 | (clobber (reg:CC CC_REGNUM))] |
6590e19a UW |
9087 | "!TARGET_CPU_ZARCH" |
9088 | { | |
9089 | if (which_alternative != 0) | |
9090 | return "#"; | |
9091 | else if (get_attr_length (insn) == 4) | |
9092 | return "brct\t%1,%l0"; | |
0a3bdf9d | 9093 | else |
8d933e31 | 9094 | gcc_unreachable (); |
10bbf137 | 9095 | } |
6590e19a UW |
9096 | "&& reload_completed |
9097 | && (! REG_P (operands[2]) | |
9098 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9099 | [(set (match_dup 3) (match_dup 1)) |
9100 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9101 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9102 | (const_int 0))) | |
9103 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9104 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9105 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9106 | (label_ref (match_dup 0)) |
9107 | (pc)))] | |
9108 | "" | |
0a3bdf9d | 9109 | [(set_attr "op_type" "RI") |
9381e3f1 WG |
9110 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9111 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9112 | (set_attr "z10prop" "z10_super_E1") |
077dab3b | 9113 | (set_attr "type" "branch") |
0a3bdf9d | 9114 | (set (attr "length") |
d7f99b2c | 9115 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
9116 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9117 | (const_int 4) (const_int 6)) | |
9118 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9119 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 9120 | |
0a3bdf9d UW |
9121 | (define_insn "*doloop_si_long" |
9122 | [(set (pc) | |
9123 | (if_then_else | |
7e665d18 | 9124 | (ne (match_operand:SI 1 "register_operand" "d") |
0a3bdf9d | 9125 | (const_int 1)) |
4fe6dea8 | 9126 | (match_operand 0 "address_operand" "ZQZR") |
0a3bdf9d | 9127 | (pc))) |
7e665d18 | 9128 | (set (match_operand:SI 2 "register_operand" "=1") |
0a3bdf9d | 9129 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9130 | (clobber (match_scratch:SI 3 "=X")) |
ae156f85 | 9131 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 9132 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
9133 | { |
9134 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9135 | return "bctr\t%1,%0"; |
0a3bdf9d | 9136 | else |
d40c829f | 9137 | return "bct\t%1,%a0"; |
10bbf137 | 9138 | } |
c7453384 | 9139 | [(set (attr "op_type") |
0a3bdf9d UW |
9140 | (if_then_else (match_operand 0 "register_operand" "") |
9141 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 9142 | (set_attr "type" "branch") |
729e750f | 9143 | (set_attr "atype" "agen") |
65b1d8ea AK |
9144 | (set_attr "z10prop" "z10_c") |
9145 | (set_attr "z196prop" "z196_cracked")]) | |
0a3bdf9d | 9146 | |
6590e19a | 9147 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
9148 | [(set (pc) |
9149 | (if_then_else | |
7e665d18 | 9150 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9151 | (const_int 1)) |
9152 | (label_ref (match_operand 0 "" "")) | |
9153 | (pc))) | |
7e665d18 | 9154 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9155 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 9156 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 9157 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 9158 | "TARGET_ZARCH" |
0a3bdf9d UW |
9159 | { |
9160 | if (which_alternative != 0) | |
10bbf137 | 9161 | return "#"; |
0a3bdf9d | 9162 | else if (get_attr_length (insn) == 4) |
d40c829f | 9163 | return "brctg\t%1,%l0"; |
0a3bdf9d | 9164 | else |
545d16ff | 9165 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 9166 | } |
6590e19a | 9167 | "&& reload_completed |
0a3bdf9d UW |
9168 | && (! REG_P (operands[2]) |
9169 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9170 | [(set (match_dup 3) (match_dup 1)) |
9171 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
9172 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
9173 | (const_int 0))) | |
9174 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
9175 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9176 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 9177 | (label_ref (match_dup 0)) |
0a3bdf9d | 9178 | (pc)))] |
6590e19a UW |
9179 | "" |
9180 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9181 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9182 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9183 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9184 | (set_attr "type" "branch") |
9185 | (set (attr "length") | |
9186 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9187 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
9188 | |
9189 | ;; | |
9190 | ;;- Unconditional jump instructions. | |
9191 | ;; | |
9192 | ||
9193 | ; | |
9194 | ; jump instruction pattern(s). | |
9195 | ; | |
9196 | ||
6590e19a UW |
9197 | (define_expand "jump" |
9198 | [(match_operand 0 "" "")] | |
9db1d521 | 9199 | "" |
6590e19a UW |
9200 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
9201 | ||
9202 | (define_insn "*jump64" | |
9203 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
9204 | "TARGET_CPU_ZARCH" | |
9db1d521 | 9205 | { |
13e58269 | 9206 | if (get_attr_length (insn) == 4) |
d40c829f | 9207 | return "j\t%l0"; |
6590e19a | 9208 | else |
d40c829f | 9209 | return "jg\t%l0"; |
6590e19a UW |
9210 | } |
9211 | [(set_attr "op_type" "RI") | |
9212 | (set_attr "type" "branch") | |
9213 | (set (attr "length") | |
9214 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9215 | (const_int 4) (const_int 6)))]) | |
9216 | ||
9217 | (define_insn "*jump31" | |
9218 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
9219 | "!TARGET_CPU_ZARCH" | |
9220 | { | |
8d933e31 AS |
9221 | gcc_assert (get_attr_length (insn) == 4); |
9222 | return "j\t%l0"; | |
10bbf137 | 9223 | } |
9db1d521 | 9224 | [(set_attr "op_type" "RI") |
077dab3b | 9225 | (set_attr "type" "branch") |
13e58269 | 9226 | (set (attr "length") |
d7f99b2c | 9227 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
9228 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9229 | (const_int 4) (const_int 6)) | |
9230 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9231 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
9232 | |
9233 | ; | |
9234 | ; indirect-jump instruction pattern(s). | |
9235 | ; | |
9236 | ||
9237 | (define_insn "indirect_jump" | |
4fe6dea8 | 9238 | [(set (pc) (match_operand 0 "address_operand" "ZQZR"))] |
9db1d521 | 9239 | "" |
f314b9b1 UW |
9240 | { |
9241 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9242 | return "br\t%0"; |
f314b9b1 | 9243 | else |
d40c829f | 9244 | return "b\t%a0"; |
10bbf137 | 9245 | } |
c7453384 | 9246 | [(set (attr "op_type") |
f314b9b1 UW |
9247 | (if_then_else (match_operand 0 "register_operand" "") |
9248 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 9249 | (set_attr "type" "branch") |
729e750f | 9250 | (set_attr "atype" "agen")]) |
9db1d521 HP |
9251 | |
9252 | ; | |
f314b9b1 | 9253 | ; casesi instruction pattern(s). |
9db1d521 HP |
9254 | ; |
9255 | ||
f314b9b1 | 9256 | (define_insn "casesi_jump" |
4fe6dea8 | 9257 | [(set (pc) (match_operand 0 "address_operand" "ZQZR")) |
f314b9b1 | 9258 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 9259 | "" |
9db1d521 | 9260 | { |
f314b9b1 | 9261 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 9262 | return "br\t%0"; |
f314b9b1 | 9263 | else |
d40c829f | 9264 | return "b\t%a0"; |
10bbf137 | 9265 | } |
c7453384 | 9266 | [(set (attr "op_type") |
f314b9b1 UW |
9267 | (if_then_else (match_operand 0 "register_operand" "") |
9268 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
9269 | (set_attr "type" "branch") |
9270 | (set_attr "atype" "agen")]) | |
9db1d521 | 9271 | |
f314b9b1 UW |
9272 | (define_expand "casesi" |
9273 | [(match_operand:SI 0 "general_operand" "") | |
9274 | (match_operand:SI 1 "general_operand" "") | |
9275 | (match_operand:SI 2 "general_operand" "") | |
9276 | (label_ref (match_operand 3 "" "")) | |
9277 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 9278 | "" |
f314b9b1 UW |
9279 | { |
9280 | rtx index = gen_reg_rtx (SImode); | |
9281 | rtx base = gen_reg_rtx (Pmode); | |
9282 | rtx target = gen_reg_rtx (Pmode); | |
9283 | ||
9284 | emit_move_insn (index, operands[0]); | |
9285 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
9286 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 9287 | operands[4]); |
f314b9b1 UW |
9288 | |
9289 | if (Pmode != SImode) | |
9290 | index = convert_to_mode (Pmode, index, 1); | |
9291 | if (GET_CODE (index) != REG) | |
9292 | index = copy_to_mode_reg (Pmode, index); | |
9293 | ||
9294 | if (TARGET_64BIT) | |
9295 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
9296 | else | |
a556fd39 | 9297 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 9298 | |
f314b9b1 UW |
9299 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
9300 | ||
542a8afa | 9301 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
9302 | emit_move_insn (target, index); |
9303 | ||
9304 | if (flag_pic) | |
9305 | target = gen_rtx_PLUS (Pmode, base, target); | |
9306 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
9307 | ||
9308 | DONE; | |
10bbf137 | 9309 | }) |
9db1d521 HP |
9310 | |
9311 | ||
9312 | ;; | |
9313 | ;;- Jump to subroutine. | |
9314 | ;; | |
9315 | ;; | |
9316 | ||
9317 | ; | |
9318 | ; untyped call instruction pattern(s). | |
9319 | ; | |
9320 | ||
9321 | ;; Call subroutine returning any type. | |
9322 | (define_expand "untyped_call" | |
9323 | [(parallel [(call (match_operand 0 "" "") | |
9324 | (const_int 0)) | |
9325 | (match_operand 1 "" "") | |
9326 | (match_operand 2 "" "")])] | |
9327 | "" | |
9db1d521 HP |
9328 | { |
9329 | int i; | |
9330 | ||
9331 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
9332 | ||
9333 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
9334 | { | |
9335 | rtx set = XVECEXP (operands[2], 0, i); | |
9336 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
9337 | } | |
9338 | ||
9339 | /* The optimizer does not know that the call sets the function value | |
9340 | registers we stored in the result block. We avoid problems by | |
9341 | claiming that all hard registers are used and clobbered at this | |
9342 | point. */ | |
9343 | emit_insn (gen_blockage ()); | |
9344 | ||
9345 | DONE; | |
10bbf137 | 9346 | }) |
9db1d521 HP |
9347 | |
9348 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
9349 | ;; all of memory. This blocks insns from being moved across this point. | |
9350 | ||
9351 | (define_insn "blockage" | |
10bbf137 | 9352 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 9353 | "" |
4023fb28 | 9354 | "" |
d5869ca0 UW |
9355 | [(set_attr "type" "none") |
9356 | (set_attr "length" "0")]) | |
4023fb28 | 9357 | |
9db1d521 | 9358 | ; |
ed9676cf | 9359 | ; sibcall patterns |
9db1d521 HP |
9360 | ; |
9361 | ||
ed9676cf | 9362 | (define_expand "sibcall" |
44b8152b | 9363 | [(call (match_operand 0 "" "") |
ed9676cf | 9364 | (match_operand 1 "" ""))] |
9db1d521 | 9365 | "" |
9db1d521 | 9366 | { |
ed9676cf AK |
9367 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
9368 | DONE; | |
9369 | }) | |
9db1d521 | 9370 | |
ed9676cf | 9371 | (define_insn "*sibcall_br" |
ae156f85 | 9372 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9373 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 9374 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
9375 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
9376 | "br\t%%r1" | |
9377 | [(set_attr "op_type" "RR") | |
9378 | (set_attr "type" "branch") | |
9379 | (set_attr "atype" "agen")]) | |
9db1d521 | 9380 | |
ed9676cf AK |
9381 | (define_insn "*sibcall_brc" |
9382 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9383 | (match_operand 1 "const_int_operand" "n"))] | |
9384 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9385 | "j\t%0" | |
9386 | [(set_attr "op_type" "RI") | |
9387 | (set_attr "type" "branch")]) | |
9db1d521 | 9388 | |
ed9676cf AK |
9389 | (define_insn "*sibcall_brcl" |
9390 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9391 | (match_operand 1 "const_int_operand" "n"))] | |
9392 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
9393 | "jg\t%0" | |
9394 | [(set_attr "op_type" "RIL") | |
9395 | (set_attr "type" "branch")]) | |
44b8152b | 9396 | |
ed9676cf AK |
9397 | ; |
9398 | ; sibcall_value patterns | |
9399 | ; | |
9e8327e3 | 9400 | |
ed9676cf AK |
9401 | (define_expand "sibcall_value" |
9402 | [(set (match_operand 0 "" "") | |
9403 | (call (match_operand 1 "" "") | |
9404 | (match_operand 2 "" "")))] | |
9405 | "" | |
9406 | { | |
9407 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 9408 | DONE; |
10bbf137 | 9409 | }) |
9db1d521 | 9410 | |
ed9676cf AK |
9411 | (define_insn "*sibcall_value_br" |
9412 | [(set (match_operand 0 "" "") | |
ae156f85 | 9413 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9414 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 9415 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
9416 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
9417 | "br\t%%r1" | |
9418 | [(set_attr "op_type" "RR") | |
9419 | (set_attr "type" "branch") | |
9420 | (set_attr "atype" "agen")]) | |
9421 | ||
9422 | (define_insn "*sibcall_value_brc" | |
9423 | [(set (match_operand 0 "" "") | |
9424 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9425 | (match_operand 2 "const_int_operand" "n")))] | |
9426 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9427 | "j\t%1" | |
9428 | [(set_attr "op_type" "RI") | |
9429 | (set_attr "type" "branch")]) | |
9430 | ||
9431 | (define_insn "*sibcall_value_brcl" | |
9432 | [(set (match_operand 0 "" "") | |
9433 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9434 | (match_operand 2 "const_int_operand" "n")))] | |
9435 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
9436 | "jg\t%1" | |
9437 | [(set_attr "op_type" "RIL") | |
9438 | (set_attr "type" "branch")]) | |
9439 | ||
9440 | ||
9441 | ; | |
9442 | ; call instruction pattern(s). | |
9443 | ; | |
9444 | ||
9445 | (define_expand "call" | |
9446 | [(call (match_operand 0 "" "") | |
9447 | (match_operand 1 "" "")) | |
9448 | (use (match_operand 2 "" ""))] | |
44b8152b | 9449 | "" |
ed9676cf | 9450 | { |
2f7e5a0d | 9451 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
9452 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
9453 | DONE; | |
9454 | }) | |
44b8152b | 9455 | |
9e8327e3 UW |
9456 | (define_insn "*bras" |
9457 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9458 | (match_operand 1 "const_int_operand" "n")) | |
9459 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
9460 | "!SIBLING_CALL_P (insn) |
9461 | && TARGET_SMALL_EXEC | |
ed9676cf | 9462 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 9463 | "bras\t%2,%0" |
9db1d521 | 9464 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9465 | (set_attr "type" "jsr") |
9466 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9467 | |
9e8327e3 UW |
9468 | (define_insn "*brasl" |
9469 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9470 | (match_operand 1 "const_int_operand" "n")) | |
9471 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
9472 | "!SIBLING_CALL_P (insn) |
9473 | && TARGET_CPU_ZARCH | |
ed9676cf | 9474 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
9475 | "brasl\t%2,%0" |
9476 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9477 | (set_attr "type" "jsr") |
9478 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9479 | |
9e8327e3 | 9480 | (define_insn "*basr" |
4fe6dea8 | 9481 | [(call (mem:QI (match_operand 0 "address_operand" "ZQZR")) |
9e8327e3 UW |
9482 | (match_operand 1 "const_int_operand" "n")) |
9483 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 9484 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
9485 | { |
9486 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9487 | return "basr\t%2,%0"; | |
9488 | else | |
9489 | return "bas\t%2,%a0"; | |
9490 | } | |
9491 | [(set (attr "op_type") | |
9492 | (if_then_else (match_operand 0 "register_operand" "") | |
9493 | (const_string "RR") (const_string "RX"))) | |
9494 | (set_attr "type" "jsr") | |
65b1d8ea AK |
9495 | (set_attr "atype" "agen") |
9496 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 HP |
9497 | |
9498 | ; | |
9499 | ; call_value instruction pattern(s). | |
9500 | ; | |
9501 | ||
9502 | (define_expand "call_value" | |
44b8152b UW |
9503 | [(set (match_operand 0 "" "") |
9504 | (call (match_operand 1 "" "") | |
9505 | (match_operand 2 "" ""))) | |
9506 | (use (match_operand 3 "" ""))] | |
9db1d521 | 9507 | "" |
9db1d521 | 9508 | { |
2f7e5a0d | 9509 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 9510 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 9511 | DONE; |
10bbf137 | 9512 | }) |
9db1d521 | 9513 | |
9e8327e3 | 9514 | (define_insn "*bras_r" |
c19ec8f9 | 9515 | [(set (match_operand 0 "" "") |
9e8327e3 | 9516 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 9517 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 9518 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
9519 | "!SIBLING_CALL_P (insn) |
9520 | && TARGET_SMALL_EXEC | |
ed9676cf | 9521 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 9522 | "bras\t%3,%1" |
9db1d521 | 9523 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9524 | (set_attr "type" "jsr") |
9525 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9526 | |
9e8327e3 | 9527 | (define_insn "*brasl_r" |
c19ec8f9 | 9528 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9529 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9530 | (match_operand 2 "const_int_operand" "n"))) | |
9531 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
9532 | "!SIBLING_CALL_P (insn) |
9533 | && TARGET_CPU_ZARCH | |
ed9676cf | 9534 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9535 | "brasl\t%3,%1" |
9536 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9537 | (set_attr "type" "jsr") |
9538 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9539 | |
9e8327e3 | 9540 | (define_insn "*basr_r" |
c19ec8f9 | 9541 | [(set (match_operand 0 "" "") |
4fe6dea8 | 9542 | (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
9e8327e3 UW |
9543 | (match_operand 2 "const_int_operand" "n"))) |
9544 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 9545 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9546 | { |
9547 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9548 | return "basr\t%3,%1"; | |
9549 | else | |
9550 | return "bas\t%3,%a1"; | |
9551 | } | |
9552 | [(set (attr "op_type") | |
9553 | (if_then_else (match_operand 1 "register_operand" "") | |
9554 | (const_string "RR") (const_string "RX"))) | |
9555 | (set_attr "type" "jsr") | |
65b1d8ea AK |
9556 | (set_attr "atype" "agen") |
9557 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9558 | |
fd3cd001 UW |
9559 | ;; |
9560 | ;;- Thread-local storage support. | |
9561 | ;; | |
9562 | ||
f959607b CLT |
9563 | (define_expand "get_thread_pointer<mode>" |
9564 | [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))] | |
9565 | "" | |
c5aa1d12 | 9566 | "") |
fd3cd001 | 9567 | |
f959607b CLT |
9568 | (define_expand "set_thread_pointer<mode>" |
9569 | [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) | |
9570 | (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] | |
9571 | "" | |
c5aa1d12 UW |
9572 | "") |
9573 | ||
9574 | (define_insn "*set_tp" | |
ae156f85 | 9575 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
9576 | "" |
9577 | "" | |
9578 | [(set_attr "type" "none") | |
9579 | (set_attr "length" "0")]) | |
c7453384 | 9580 | |
fd3cd001 UW |
9581 | (define_insn "*tls_load_64" |
9582 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 9583 | (unspec:DI [(match_operand:DI 1 "memory_operand" "RT") |
fd3cd001 UW |
9584 | (match_operand:DI 2 "" "")] |
9585 | UNSPEC_TLS_LOAD))] | |
9586 | "TARGET_64BIT" | |
d40c829f | 9587 | "lg\t%0,%1%J2" |
9381e3f1 WG |
9588 | [(set_attr "op_type" "RXE") |
9589 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
9590 | |
9591 | (define_insn "*tls_load_31" | |
d3632d41 UW |
9592 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
9593 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
9594 | (match_operand:SI 2 "" "")] |
9595 | UNSPEC_TLS_LOAD))] | |
9596 | "!TARGET_64BIT" | |
d3632d41 | 9597 | "@ |
d40c829f UW |
9598 | l\t%0,%1%J2 |
9599 | ly\t%0,%1%J2" | |
9381e3f1 | 9600 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 9601 | (set_attr "type" "load") |
9381e3f1 | 9602 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 9603 | |
9e8327e3 | 9604 | (define_insn "*bras_tls" |
c19ec8f9 | 9605 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9606 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9607 | (match_operand 2 "const_int_operand" "n"))) | |
9608 | (clobber (match_operand 3 "register_operand" "=r")) | |
9609 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
9610 | "!SIBLING_CALL_P (insn) |
9611 | && TARGET_SMALL_EXEC | |
ed9676cf | 9612 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 9613 | "bras\t%3,%1%J4" |
fd3cd001 | 9614 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9615 | (set_attr "type" "jsr") |
9616 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9617 | |
9e8327e3 | 9618 | (define_insn "*brasl_tls" |
c19ec8f9 | 9619 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9620 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9621 | (match_operand 2 "const_int_operand" "n"))) | |
9622 | (clobber (match_operand 3 "register_operand" "=r")) | |
9623 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
9624 | "!SIBLING_CALL_P (insn) |
9625 | && TARGET_CPU_ZARCH | |
ed9676cf | 9626 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9627 | "brasl\t%3,%1%J4" |
9628 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9629 | (set_attr "type" "jsr") |
9630 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9631 | |
9e8327e3 | 9632 | (define_insn "*basr_tls" |
c19ec8f9 | 9633 | [(set (match_operand 0 "" "") |
4fe6dea8 | 9634 | (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
9e8327e3 UW |
9635 | (match_operand 2 "const_int_operand" "n"))) |
9636 | (clobber (match_operand 3 "register_operand" "=r")) | |
9637 | (use (match_operand 4 "" ""))] | |
ed9676cf | 9638 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9639 | { |
9640 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9641 | return "basr\t%3,%1%J4"; | |
9642 | else | |
9643 | return "bas\t%3,%a1%J4"; | |
9644 | } | |
9645 | [(set (attr "op_type") | |
9646 | (if_then_else (match_operand 1 "register_operand" "") | |
9647 | (const_string "RR") (const_string "RX"))) | |
9648 | (set_attr "type" "jsr") | |
65b1d8ea AK |
9649 | (set_attr "atype" "agen") |
9650 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9651 | |
e0374221 AS |
9652 | ;; |
9653 | ;;- Atomic operations | |
9654 | ;; | |
9655 | ||
9656 | ; | |
78ce265b | 9657 | ; memory barrier patterns. |
e0374221 AS |
9658 | ; |
9659 | ||
78ce265b RH |
9660 | (define_expand "mem_signal_fence" |
9661 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
e0374221 AS |
9662 | "" |
9663 | { | |
78ce265b RH |
9664 | /* The s390 memory model is strong enough not to require any |
9665 | barrier in order to synchronize a thread with itself. */ | |
9666 | DONE; | |
9667 | }) | |
9668 | ||
9669 | (define_expand "mem_thread_fence" | |
9670 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
9671 | "" | |
9672 | { | |
9673 | /* Unless this is a SEQ_CST fence, the s390 memory model is strong | |
9674 | enough not to require barriers of any kind. */ | |
46b35980 | 9675 | if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0])))) |
78ce265b RH |
9676 | { |
9677 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
9678 | MEM_VOLATILE_P (mem) = 1; | |
9679 | emit_insn (gen_mem_thread_fence_1 (mem)); | |
9680 | } | |
9681 | DONE; | |
e0374221 AS |
9682 | }) |
9683 | ||
78ce265b RH |
9684 | ; Although bcr is superscalar on Z10, this variant will never |
9685 | ; become part of an execution group. | |
a9cc3f58 AK |
9686 | ; With z196 we can make use of the fast-BCR-serialization facility. |
9687 | ; This allows for a slightly faster sync which is sufficient for our | |
9688 | ; purposes. | |
78ce265b | 9689 | (define_insn "mem_thread_fence_1" |
e0374221 | 9690 | [(set (match_operand:BLK 0 "" "") |
1a8c13b3 | 9691 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 | 9692 | "" |
a9cc3f58 AK |
9693 | { |
9694 | if (TARGET_Z196) | |
9695 | return "bcr\t14,0"; | |
9696 | else | |
9697 | return "bcr\t15,0"; | |
9698 | } | |
9699 | [(set_attr "op_type" "RR") | |
9700 | (set_attr "mnemonic" "bcr_flush") | |
9701 | (set_attr "z196prop" "z196_alone")]) | |
1a8c13b3 | 9702 | |
78ce265b RH |
9703 | ; |
9704 | ; atomic load/store operations | |
9705 | ; | |
9706 | ||
9707 | ; Atomic loads need not examine the memory model at all. | |
9708 | (define_expand "atomic_load<mode>" | |
9709 | [(match_operand:DINT 0 "register_operand") ;; output | |
9710 | (match_operand:DINT 1 "memory_operand") ;; memory | |
9711 | (match_operand:SI 2 "const_int_operand")] ;; model | |
9712 | "" | |
9713 | { | |
75cc21e2 AK |
9714 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
9715 | FAIL; | |
9716 | ||
78ce265b RH |
9717 | if (<MODE>mode == TImode) |
9718 | emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); | |
9719 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
9720 | emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); | |
9721 | else | |
9722 | emit_move_insn (operands[0], operands[1]); | |
9723 | DONE; | |
9724 | }) | |
9725 | ||
9726 | ; Different from movdi_31 in that we want no splitters. | |
9727 | (define_insn "atomic_loaddi_1" | |
9728 | [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") | |
9729 | (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] | |
9730 | UNSPEC_MOVA))] | |
9731 | "!TARGET_ZARCH" | |
9732 | "@ | |
9733 | lm\t%0,%M0,%S1 | |
9734 | lmy\t%0,%M0,%S1 | |
9735 | ld\t%0,%1 | |
9736 | ldy\t%0,%1" | |
9737 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
9738 | (set_attr "type" "lm,lm,floaddf,floaddf")]) | |
9739 | ||
9740 | (define_insn "atomic_loadti_1" | |
9741 | [(set (match_operand:TI 0 "register_operand" "=r") | |
9742 | (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")] | |
9743 | UNSPEC_MOVA))] | |
9744 | "TARGET_ZARCH" | |
9745 | "lpq\t%0,%1" | |
9746 | [(set_attr "op_type" "RXY") | |
9747 | (set_attr "type" "other")]) | |
9748 | ||
9749 | ; Atomic stores must(?) enforce sequential consistency. | |
9750 | (define_expand "atomic_store<mode>" | |
9751 | [(match_operand:DINT 0 "memory_operand") ;; memory | |
9752 | (match_operand:DINT 1 "register_operand") ;; input | |
9753 | (match_operand:SI 2 "const_int_operand")] ;; model | |
9754 | "" | |
9755 | { | |
46b35980 | 9756 | enum memmodel model = memmodel_from_int (INTVAL (operands[2])); |
78ce265b | 9757 | |
75cc21e2 AK |
9758 | if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0]))) |
9759 | FAIL; | |
9760 | ||
78ce265b RH |
9761 | if (<MODE>mode == TImode) |
9762 | emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); | |
9763 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
9764 | emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); | |
9765 | else | |
9766 | emit_move_insn (operands[0], operands[1]); | |
46b35980 | 9767 | if (is_mm_seq_cst (model)) |
78ce265b RH |
9768 | emit_insn (gen_mem_thread_fence (operands[2])); |
9769 | DONE; | |
9770 | }) | |
9771 | ||
9772 | ; Different from movdi_31 in that we want no splitters. | |
9773 | (define_insn "atomic_storedi_1" | |
9774 | [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") | |
9775 | (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] | |
9776 | UNSPEC_MOVA))] | |
9777 | "!TARGET_ZARCH" | |
9778 | "@ | |
9779 | stm\t%1,%N1,%S0 | |
9780 | stmy\t%1,%N1,%S0 | |
9781 | std %1,%0 | |
9782 | stdy %1,%0" | |
9783 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
9784 | (set_attr "type" "stm,stm,fstoredf,fstoredf")]) | |
9785 | ||
9786 | (define_insn "atomic_storeti_1" | |
9787 | [(set (match_operand:TI 0 "memory_operand" "=RT") | |
9788 | (unspec:TI [(match_operand:TI 1 "register_operand" "r")] | |
9789 | UNSPEC_MOVA))] | |
9790 | "TARGET_ZARCH" | |
9791 | "stpq\t%1,%0" | |
9792 | [(set_attr "op_type" "RXY") | |
9793 | (set_attr "type" "other")]) | |
e0374221 AS |
9794 | |
9795 | ; | |
9796 | ; compare and swap patterns. | |
9797 | ; | |
9798 | ||
78ce265b RH |
9799 | (define_expand "atomic_compare_and_swap<mode>" |
9800 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
215770ad | 9801 | (match_operand:DGPR 1 "nonimmediate_operand");; oldval output |
78ce265b RH |
9802 | (match_operand:DGPR 2 "memory_operand") ;; memory |
9803 | (match_operand:DGPR 3 "register_operand") ;; expected intput | |
9804 | (match_operand:DGPR 4 "register_operand") ;; newval intput | |
9805 | (match_operand:SI 5 "const_int_operand") ;; is_weak | |
9806 | (match_operand:SI 6 "const_int_operand") ;; success model | |
9807 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
9808 | "" | |
9809 | { | |
215770ad UW |
9810 | rtx cc, cmp, output = operands[1]; |
9811 | ||
9812 | if (!register_operand (output, <MODE>mode)) | |
9813 | output = gen_reg_rtx (<MODE>mode); | |
9814 | ||
75cc21e2 AK |
9815 | if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2]))) |
9816 | FAIL; | |
9817 | ||
78ce265b | 9818 | emit_insn (gen_atomic_compare_and_swap<mode>_internal |
215770ad UW |
9819 | (output, operands[2], operands[3], operands[4])); |
9820 | ||
9821 | /* We deliberately accept non-register operands in the predicate | |
9822 | to ensure the write back to the output operand happens *before* | |
9823 | the store-flags code below. This makes it easier for combine | |
9824 | to merge the store-flags code with a potential test-and-branch | |
9825 | pattern following (immediately!) afterwards. */ | |
9826 | if (output != operands[1]) | |
9827 | emit_move_insn (operands[1], output); | |
9828 | ||
78ce265b RH |
9829 | cc = gen_rtx_REG (CCZ1mode, CC_REGNUM); |
9830 | cmp = gen_rtx_EQ (SImode, cc, const0_rtx); | |
9831 | emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx)); | |
9832 | DONE; | |
9833 | }) | |
e0374221 | 9834 | |
78ce265b RH |
9835 | (define_expand "atomic_compare_and_swap<mode>" |
9836 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
215770ad | 9837 | (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output |
78ce265b RH |
9838 | (match_operand:HQI 2 "memory_operand") ;; memory |
9839 | (match_operand:HQI 3 "general_operand") ;; expected intput | |
9840 | (match_operand:HQI 4 "general_operand") ;; newval intput | |
9841 | (match_operand:SI 5 "const_int_operand") ;; is_weak | |
9842 | (match_operand:SI 6 "const_int_operand") ;; success model | |
9843 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
3093f076 | 9844 | "" |
78ce265b RH |
9845 | { |
9846 | s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2], | |
9847 | operands[3], operands[4], INTVAL (operands[5])); | |
9848 | DONE; | |
9849 | }) | |
3093f076 | 9850 | |
78ce265b RH |
9851 | (define_expand "atomic_compare_and_swap<mode>_internal" |
9852 | [(parallel | |
9853 | [(set (match_operand:DGPR 0 "register_operand") | |
9854 | (match_operand:DGPR 1 "memory_operand")) | |
9855 | (set (match_dup 1) | |
9856 | (unspec_volatile:DGPR | |
9857 | [(match_dup 1) | |
9858 | (match_operand:DGPR 2 "register_operand") | |
9859 | (match_operand:DGPR 3 "register_operand")] | |
9860 | UNSPECV_CAS)) | |
9861 | (set (reg:CCZ1 CC_REGNUM) | |
9862 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
9863 | "") | |
9864 | ||
9865 | ; cdsg, csg | |
9866 | (define_insn "*atomic_compare_and_swap<mode>_1" | |
9867 | [(set (match_operand:TDI 0 "register_operand" "=r") | |
9868 | (match_operand:TDI 1 "memory_operand" "+QS")) | |
8006eaa6 | 9869 | (set (match_dup 1) |
78ce265b | 9870 | (unspec_volatile:TDI |
8006eaa6 | 9871 | [(match_dup 1) |
78ce265b RH |
9872 | (match_operand:TDI 2 "register_operand" "0") |
9873 | (match_operand:TDI 3 "register_operand" "r")] | |
8006eaa6 AS |
9874 | UNSPECV_CAS)) |
9875 | (set (reg:CCZ1 CC_REGNUM) | |
9876 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
78ce265b RH |
9877 | "TARGET_ZARCH" |
9878 | "c<td>sg\t%0,%3,%S1" | |
9879 | [(set_attr "op_type" "RSY") | |
8006eaa6 AS |
9880 | (set_attr "type" "sem")]) |
9881 | ||
78ce265b RH |
9882 | ; cds, cdsy |
9883 | (define_insn "*atomic_compare_and_swapdi_2" | |
9884 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
9885 | (match_operand:DI 1 "memory_operand" "+Q,S")) | |
e0374221 | 9886 | (set (match_dup 1) |
78ce265b RH |
9887 | (unspec_volatile:DI |
9888 | [(match_dup 1) | |
9889 | (match_operand:DI 2 "register_operand" "0,0") | |
9890 | (match_operand:DI 3 "register_operand" "r,r")] | |
9891 | UNSPECV_CAS)) | |
9892 | (set (reg:CCZ1 CC_REGNUM) | |
9893 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
9894 | "!TARGET_ZARCH" | |
9895 | "@ | |
9896 | cds\t%0,%3,%S1 | |
9897 | cdsy\t%0,%3,%S1" | |
9898 | [(set_attr "op_type" "RS,RSY") | |
9899 | (set_attr "type" "sem")]) | |
9900 | ||
9901 | ; cs, csy | |
9902 | (define_insn "*atomic_compare_and_swapsi_3" | |
9903 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
9904 | (match_operand:SI 1 "memory_operand" "+Q,S")) | |
9905 | (set (match_dup 1) | |
9906 | (unspec_volatile:SI | |
e0374221 | 9907 | [(match_dup 1) |
78ce265b RH |
9908 | (match_operand:SI 2 "register_operand" "0,0") |
9909 | (match_operand:SI 3 "register_operand" "r,r")] | |
e0374221 | 9910 | UNSPECV_CAS)) |
69950452 AS |
9911 | (set (reg:CCZ1 CC_REGNUM) |
9912 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
9381e3f1 | 9913 | "" |
78ce265b RH |
9914 | "@ |
9915 | cs\t%0,%3,%S1 | |
9916 | csy\t%0,%3,%S1" | |
9917 | [(set_attr "op_type" "RS,RSY") | |
e0374221 AS |
9918 | (set_attr "type" "sem")]) |
9919 | ||
45d18331 AS |
9920 | ; |
9921 | ; Other atomic instruction patterns. | |
9922 | ; | |
9923 | ||
65b1d8ea AK |
9924 | ; z196 load and add, xor, or and and instructions |
9925 | ||
78ce265b RH |
9926 | (define_expand "atomic_fetch_<atomic><mode>" |
9927 | [(match_operand:GPR 0 "register_operand") ;; val out | |
9928 | (ATOMIC_Z196:GPR | |
9929 | (match_operand:GPR 1 "memory_operand") ;; memory | |
9930 | (match_operand:GPR 2 "register_operand")) ;; val in | |
9931 | (match_operand:SI 3 "const_int_operand")] ;; model | |
65b1d8ea | 9932 | "TARGET_Z196" |
78ce265b | 9933 | { |
75cc21e2 AK |
9934 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
9935 | FAIL; | |
9936 | ||
78ce265b RH |
9937 | emit_insn (gen_atomic_fetch_<atomic><mode>_iaf |
9938 | (operands[0], operands[1], operands[2])); | |
9939 | DONE; | |
9940 | }) | |
65b1d8ea AK |
9941 | |
9942 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
78ce265b RH |
9943 | (define_insn "atomic_fetch_<atomic><mode>_iaf" |
9944 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
9945 | (match_operand:GPR 1 "memory_operand" "+QS")) | |
9946 | (set (match_dup 1) | |
9947 | (unspec_volatile:GPR | |
9948 | [(ATOMIC_Z196:GPR (match_dup 1) | |
9949 | (match_operand:GPR 2 "general_operand" "d"))] | |
9950 | UNSPECV_ATOMIC_OP)) | |
9951 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 9952 | "TARGET_Z196" |
78ce265b RH |
9953 | "la<noxa><g>\t%0,%2,%1" |
9954 | [(set_attr "op_type" "RSY") | |
9955 | (set_attr "type" "sem")]) | |
65b1d8ea | 9956 | |
78ce265b RH |
9957 | ;; For SImode and larger, the optabs.c code will do just fine in |
9958 | ;; expanding a compare-and-swap loop. For QI/HImode, we can do | |
9959 | ;; better by expanding our own loop. | |
65b1d8ea | 9960 | |
78ce265b RH |
9961 | (define_expand "atomic_<atomic><mode>" |
9962 | [(ATOMIC:HQI | |
9963 | (match_operand:HQI 0 "memory_operand") ;; memory | |
9964 | (match_operand:HQI 1 "general_operand")) ;; val in | |
9965 | (match_operand:SI 2 "const_int_operand")] ;; model | |
45d18331 | 9966 | "" |
78ce265b RH |
9967 | { |
9968 | s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], | |
9969 | operands[1], false); | |
9970 | DONE; | |
9971 | }) | |
45d18331 | 9972 | |
78ce265b RH |
9973 | (define_expand "atomic_fetch_<atomic><mode>" |
9974 | [(match_operand:HQI 0 "register_operand") ;; val out | |
9975 | (ATOMIC:HQI | |
9976 | (match_operand:HQI 1 "memory_operand") ;; memory | |
9977 | (match_operand:HQI 2 "general_operand")) ;; val in | |
9978 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 9979 | "" |
78ce265b RH |
9980 | { |
9981 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
9982 | operands[2], false); | |
9983 | DONE; | |
9984 | }) | |
9985 | ||
9986 | (define_expand "atomic_<atomic>_fetch<mode>" | |
9987 | [(match_operand:HQI 0 "register_operand") ;; val out | |
9988 | (ATOMIC:HQI | |
9989 | (match_operand:HQI 1 "memory_operand") ;; memory | |
9990 | (match_operand:HQI 2 "general_operand")) ;; val in | |
9991 | (match_operand:SI 3 "const_int_operand")] ;; model | |
9992 | "" | |
9993 | { | |
9994 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
9995 | operands[2], true); | |
9996 | DONE; | |
9997 | }) | |
9998 | ||
9999 | (define_expand "atomic_exchange<mode>" | |
10000 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10001 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10002 | (match_operand:HQI 2 "general_operand") ;; val in | |
10003 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 10004 | "" |
78ce265b RH |
10005 | { |
10006 | s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], | |
10007 | operands[2], false); | |
10008 | DONE; | |
10009 | }) | |
45d18331 | 10010 | |
9db1d521 HP |
10011 | ;; |
10012 | ;;- Miscellaneous instructions. | |
10013 | ;; | |
10014 | ||
10015 | ; | |
10016 | ; allocate stack instruction pattern(s). | |
10017 | ; | |
10018 | ||
10019 | (define_expand "allocate_stack" | |
ef44a6ff UW |
10020 | [(match_operand 0 "general_operand" "") |
10021 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 10022 | "TARGET_BACKCHAIN" |
9db1d521 | 10023 | { |
ef44a6ff | 10024 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 10025 | |
ef44a6ff UW |
10026 | emit_move_insn (temp, s390_back_chain_rtx ()); |
10027 | anti_adjust_stack (operands[1]); | |
10028 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 10029 | |
ef44a6ff UW |
10030 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
10031 | DONE; | |
10bbf137 | 10032 | }) |
9db1d521 HP |
10033 | |
10034 | ||
10035 | ; | |
43ab026f | 10036 | ; setjmp instruction pattern. |
9db1d521 HP |
10037 | ; |
10038 | ||
9db1d521 | 10039 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 10040 | [(match_operand 0 "" "")] |
f314b9b1 | 10041 | "flag_pic" |
9db1d521 | 10042 | { |
585539a1 | 10043 | emit_insn (s390_load_got ()); |
c41c1387 | 10044 | emit_use (pic_offset_table_rtx); |
9db1d521 | 10045 | DONE; |
fd7643fb | 10046 | }) |
9db1d521 | 10047 | |
9db1d521 HP |
10048 | ;; These patterns say how to save and restore the stack pointer. We need not |
10049 | ;; save the stack pointer at function level since we are careful to | |
10050 | ;; preserve the backchain. At block level, we have to restore the backchain | |
10051 | ;; when we restore the stack pointer. | |
10052 | ;; | |
10053 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
10054 | ;; backchain and restore both. Note that in the nonlocal case, the | |
10055 | ;; save area is a memory location. | |
10056 | ||
10057 | (define_expand "save_stack_function" | |
10058 | [(match_operand 0 "general_operand" "") | |
10059 | (match_operand 1 "general_operand" "")] | |
10060 | "" | |
10061 | "DONE;") | |
10062 | ||
10063 | (define_expand "restore_stack_function" | |
10064 | [(match_operand 0 "general_operand" "") | |
10065 | (match_operand 1 "general_operand" "")] | |
10066 | "" | |
10067 | "DONE;") | |
10068 | ||
10069 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
10070 | [(match_operand 0 "register_operand" "") |
10071 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 10072 | "TARGET_BACKCHAIN" |
9db1d521 | 10073 | { |
ef44a6ff UW |
10074 | rtx temp = gen_reg_rtx (Pmode); |
10075 | ||
10076 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
10077 | emit_move_insn (operands[0], operands[1]); | |
10078 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10079 | ||
10080 | DONE; | |
10bbf137 | 10081 | }) |
9db1d521 HP |
10082 | |
10083 | (define_expand "save_stack_nonlocal" | |
10084 | [(match_operand 0 "memory_operand" "") | |
10085 | (match_operand 1 "register_operand" "")] | |
10086 | "" | |
9db1d521 | 10087 | { |
ef44a6ff UW |
10088 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
10089 | ||
10090 | /* Copy the backchain to the first word, sp to the second and the | |
10091 | literal pool base to the third. */ | |
10092 | ||
9602b6a1 AK |
10093 | rtx save_bc = adjust_address (operands[0], Pmode, 0); |
10094 | rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); | |
10095 | rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10096 | ||
b3d31392 | 10097 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10098 | emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); |
ef44a6ff | 10099 | |
9602b6a1 AK |
10100 | emit_move_insn (save_sp, operands[1]); |
10101 | emit_move_insn (save_bp, base); | |
9db1d521 | 10102 | |
9db1d521 | 10103 | DONE; |
10bbf137 | 10104 | }) |
9db1d521 HP |
10105 | |
10106 | (define_expand "restore_stack_nonlocal" | |
10107 | [(match_operand 0 "register_operand" "") | |
10108 | (match_operand 1 "memory_operand" "")] | |
10109 | "" | |
9db1d521 | 10110 | { |
490ceeb4 | 10111 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 10112 | rtx temp = NULL_RTX; |
9db1d521 | 10113 | |
43ab026f | 10114 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 10115 | literal pool base from the third. */ |
43ab026f | 10116 | |
9602b6a1 AK |
10117 | rtx save_bc = adjust_address (operands[1], Pmode, 0); |
10118 | rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); | |
10119 | rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10120 | ||
b3d31392 | 10121 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10122 | temp = force_reg (Pmode, save_bc); |
9381e3f1 | 10123 | |
9602b6a1 AK |
10124 | emit_move_insn (base, save_bp); |
10125 | emit_move_insn (operands[0], save_sp); | |
ef44a6ff UW |
10126 | |
10127 | if (temp) | |
10128 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10129 | ||
c41c1387 | 10130 | emit_use (base); |
9db1d521 | 10131 | DONE; |
10bbf137 | 10132 | }) |
9db1d521 | 10133 | |
7bcebb25 AK |
10134 | (define_expand "exception_receiver" |
10135 | [(const_int 0)] | |
10136 | "" | |
10137 | { | |
10138 | s390_set_has_landing_pad_p (true); | |
10139 | DONE; | |
10140 | }) | |
9db1d521 HP |
10141 | |
10142 | ; | |
10143 | ; nop instruction pattern(s). | |
10144 | ; | |
10145 | ||
10146 | (define_insn "nop" | |
10147 | [(const_int 0)] | |
10148 | "" | |
d40c829f | 10149 | "lr\t0,0" |
729e750f WG |
10150 | [(set_attr "op_type" "RR") |
10151 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 10152 | |
d277db6b WG |
10153 | (define_insn "nop1" |
10154 | [(const_int 1)] | |
10155 | "" | |
10156 | "lr\t1,1" | |
10157 | [(set_attr "op_type" "RR")]) | |
10158 | ||
f8af0e30 DV |
10159 | ;;- Undeletable nops (used for hotpatching) |
10160 | ||
10161 | (define_insn "nop_2_byte" | |
10162 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)] | |
10163 | "" | |
10164 | "nopr\t%%r7" | |
10165 | [(set_attr "op_type" "RR")]) | |
10166 | ||
10167 | (define_insn "nop_4_byte" | |
10168 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)] | |
10169 | "" | |
10170 | "nop\t0" | |
10171 | [(set_attr "op_type" "RX")]) | |
10172 | ||
10173 | (define_insn "nop_6_byte" | |
10174 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)] | |
10175 | "TARGET_CPU_ZARCH" | |
10176 | "brcl\t0, 0" | |
10177 | [(set_attr "op_type" "RIL")]) | |
10178 | ||
9db1d521 HP |
10179 | |
10180 | ; | |
10181 | ; Special literal pool access instruction pattern(s). | |
10182 | ; | |
10183 | ||
416cf582 UW |
10184 | (define_insn "*pool_entry" |
10185 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
10186 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 10187 | "" |
9db1d521 | 10188 | { |
ef4bddc2 | 10189 | machine_mode mode = GET_MODE (PATTERN (insn)); |
416cf582 | 10190 | unsigned int align = GET_MODE_BITSIZE (mode); |
faeb9bb6 | 10191 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
10192 | return ""; |
10193 | } | |
b628bd8e | 10194 | [(set (attr "length") |
416cf582 | 10195 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 10196 | |
9bb86f41 UW |
10197 | (define_insn "pool_align" |
10198 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
10199 | UNSPECV_POOL_ALIGN)] | |
10200 | "" | |
10201 | ".align\t%0" | |
b628bd8e | 10202 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 10203 | |
9bb86f41 UW |
10204 | (define_insn "pool_section_start" |
10205 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
10206 | "" | |
10207 | ".section\t.rodata" | |
b628bd8e | 10208 | [(set_attr "length" "0")]) |
b2ccb744 | 10209 | |
9bb86f41 UW |
10210 | (define_insn "pool_section_end" |
10211 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
10212 | "" | |
b2ccb744 | 10213 | ".previous" |
b628bd8e | 10214 | [(set_attr "length" "0")]) |
b2ccb744 | 10215 | |
5af2f3d3 | 10216 | (define_insn "main_base_31_small" |
9e8327e3 UW |
10217 | [(set (match_operand 0 "register_operand" "=a") |
10218 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
10219 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
10220 | "basr\t%0,0" |
10221 | [(set_attr "op_type" "RR") | |
65b1d8ea AK |
10222 | (set_attr "type" "la") |
10223 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
10224 | |
10225 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
10226 | [(set (match_operand 0 "register_operand" "=a") |
10227 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 10228 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 10229 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 | 10230 | "bras\t%0,%2" |
65b1d8ea AK |
10231 | [(set_attr "op_type" "RI") |
10232 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
10233 | |
10234 | (define_insn "main_base_64" | |
9e8327e3 UW |
10235 | [(set (match_operand 0 "register_operand" "=a") |
10236 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
10237 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
10238 | "larl\t%0,%1" |
10239 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 10240 | (set_attr "type" "larl") |
729e750f | 10241 | (set_attr "z10prop" "z10_fwd_A1")]) |
5af2f3d3 UW |
10242 | |
10243 | (define_insn "main_pool" | |
585539a1 UW |
10244 | [(set (match_operand 0 "register_operand" "=a") |
10245 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
10246 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
10247 | { |
10248 | gcc_unreachable (); | |
10249 | } | |
9381e3f1 | 10250 | [(set (attr "type") |
d7f99b2c | 10251 | (if_then_else (match_test "TARGET_CPU_ZARCH") |
ea77e738 | 10252 | (const_string "larl") (const_string "la")))]) |
5af2f3d3 | 10253 | |
aee4e0db | 10254 | (define_insn "reload_base_31" |
9e8327e3 UW |
10255 | [(set (match_operand 0 "register_operand" "=a") |
10256 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
10257 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10258 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e | 10259 | [(set_attr "length" "6") |
65b1d8ea AK |
10260 | (set_attr "type" "la") |
10261 | (set_attr "z196prop" "z196_cracked")]) | |
b2ccb744 | 10262 | |
aee4e0db | 10263 | (define_insn "reload_base_64" |
9e8327e3 UW |
10264 | [(set (match_operand 0 "register_operand" "=a") |
10265 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
10266 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10267 | "larl\t%0,%1" |
aee4e0db | 10268 | [(set_attr "op_type" "RIL") |
9381e3f1 | 10269 | (set_attr "type" "larl") |
729e750f | 10270 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 10271 | |
aee4e0db | 10272 | (define_insn "pool" |
fd7643fb | 10273 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 10274 | "" |
8d933e31 AS |
10275 | { |
10276 | gcc_unreachable (); | |
10277 | } | |
b628bd8e | 10278 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 10279 | |
4023fb28 UW |
10280 | ;; |
10281 | ;; Insns related to generating the function prologue and epilogue. | |
10282 | ;; | |
10283 | ||
10284 | ||
10285 | (define_expand "prologue" | |
10286 | [(use (const_int 0))] | |
10287 | "" | |
10bbf137 | 10288 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
10289 | |
10290 | (define_expand "epilogue" | |
10291 | [(use (const_int 1))] | |
10292 | "" | |
ed9676cf AK |
10293 | "s390_emit_epilogue (false); DONE;") |
10294 | ||
10295 | (define_expand "sibcall_epilogue" | |
10296 | [(use (const_int 0))] | |
10297 | "" | |
10298 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 10299 | |
177bc204 RS |
10300 | ;; A direct return instruction, without using an epilogue. |
10301 | (define_insn "<code>" | |
10302 | [(ANY_RETURN)] | |
10303 | "s390_can_use_<code>_insn ()" | |
10304 | "br\t%%r14" | |
10305 | [(set_attr "op_type" "RR") | |
10306 | (set_attr "type" "jsr") | |
10307 | (set_attr "atype" "agen")]) | |
10308 | ||
9e8327e3 | 10309 | (define_insn "*return" |
4023fb28 | 10310 | [(return) |
9e8327e3 UW |
10311 | (use (match_operand 0 "register_operand" "a"))] |
10312 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10313 | "br\t%0" |
4023fb28 | 10314 | [(set_attr "op_type" "RR") |
c7453384 | 10315 | (set_attr "type" "jsr") |
077dab3b | 10316 | (set_attr "atype" "agen")]) |
4023fb28 | 10317 | |
4023fb28 | 10318 | |
c7453384 | 10319 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 10320 | ;; pointer. This is used for compatibility. |
c7453384 EC |
10321 | |
10322 | (define_expand "ptr_extend" | |
10323 | [(set (match_operand:DI 0 "register_operand" "=r") | |
10324 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 10325 | "TARGET_64BIT" |
c7453384 | 10326 | { |
c7453384 EC |
10327 | emit_insn (gen_anddi3 (operands[0], |
10328 | gen_lowpart (DImode, operands[1]), | |
10329 | GEN_INT (0x7fffffff))); | |
c7453384 | 10330 | DONE; |
10bbf137 | 10331 | }) |
4798630c D |
10332 | |
10333 | ;; Instruction definition to expand eh_return macro to support | |
10334 | ;; swapping in special linkage return addresses. | |
10335 | ||
10336 | (define_expand "eh_return" | |
10337 | [(use (match_operand 0 "register_operand" ""))] | |
10338 | "TARGET_TPF" | |
10339 | { | |
10340 | s390_emit_tpf_eh_return (operands[0]); | |
10341 | DONE; | |
10342 | }) | |
10343 | ||
7b8acc34 AK |
10344 | ; |
10345 | ; Stack Protector Patterns | |
10346 | ; | |
10347 | ||
10348 | (define_expand "stack_protect_set" | |
10349 | [(set (match_operand 0 "memory_operand" "") | |
10350 | (match_operand 1 "memory_operand" ""))] | |
10351 | "" | |
10352 | { | |
10353 | #ifdef TARGET_THREAD_SSP_OFFSET | |
10354 | operands[1] | |
10355 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
10356 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
10357 | #endif | |
10358 | if (TARGET_64BIT) | |
10359 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
10360 | else | |
10361 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
10362 | ||
10363 | DONE; | |
10364 | }) | |
10365 | ||
10366 | (define_insn "stack_protect_set<mode>" | |
10367 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
10368 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
10369 | "" | |
10370 | "mvc\t%O0(%G0,%R0),%S1" | |
10371 | [(set_attr "op_type" "SS")]) | |
10372 | ||
10373 | (define_expand "stack_protect_test" | |
10374 | [(set (reg:CC CC_REGNUM) | |
10375 | (compare (match_operand 0 "memory_operand" "") | |
10376 | (match_operand 1 "memory_operand" ""))) | |
10377 | (match_operand 2 "" "")] | |
10378 | "" | |
10379 | { | |
f90b7a5a | 10380 | rtx cc_reg, test; |
7b8acc34 AK |
10381 | #ifdef TARGET_THREAD_SSP_OFFSET |
10382 | operands[1] | |
10383 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
10384 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
10385 | #endif | |
7b8acc34 AK |
10386 | if (TARGET_64BIT) |
10387 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
10388 | else | |
10389 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
10390 | ||
f90b7a5a PB |
10391 | cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); |
10392 | test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); | |
10393 | emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); | |
7b8acc34 AK |
10394 | DONE; |
10395 | }) | |
10396 | ||
10397 | (define_insn "stack_protect_test<mode>" | |
10398 | [(set (reg:CCZ CC_REGNUM) | |
10399 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
10400 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
10401 | "" | |
10402 | "clc\t%O0(%G0,%R0),%S1" | |
10403 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
10404 | |
10405 | ; This is used in s390_emit_prologue in order to prevent insns | |
10406 | ; adjusting the stack pointer to be moved over insns writing stack | |
10407 | ; slots using a copy of the stack pointer in a different register. | |
10408 | (define_insn "stack_tie" | |
10409 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
10410 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
10411 | "" | |
10412 | "" | |
10413 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
10414 | |
10415 | ||
10416 | ; | |
10417 | ; Data prefetch patterns | |
10418 | ; | |
10419 | ||
10420 | (define_insn "prefetch" | |
22d72dbc AK |
10421 | [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X") |
10422 | (match_operand:SI 1 "const_int_operand" " n,n") | |
10423 | (match_operand:SI 2 "const_int_operand" " n,n"))] | |
10424 | "TARGET_Z10" | |
963fc8d0 | 10425 | { |
4fe6dea8 AK |
10426 | switch (which_alternative) |
10427 | { | |
10428 | case 0: | |
4fe6dea8 | 10429 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; |
22d72dbc | 10430 | case 1: |
4fe6dea8 AK |
10431 | if (larl_operand (operands[0], Pmode)) |
10432 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
10433 | default: | |
10434 | ||
10435 | /* This might be reached for symbolic operands with an odd | |
10436 | addend. We simply omit the prefetch for such rare cases. */ | |
10437 | ||
10438 | return ""; | |
10439 | } | |
9381e3f1 | 10440 | } |
22d72dbc AK |
10441 | [(set_attr "type" "load,larl") |
10442 | (set_attr "op_type" "RXY,RIL") | |
65b1d8ea AK |
10443 | (set_attr "z10prop" "z10_super") |
10444 | (set_attr "z196prop" "z196_alone")]) | |
07da44ab AK |
10445 | |
10446 | ||
10447 | ; | |
10448 | ; Byte swap instructions | |
10449 | ; | |
10450 | ||
511f5bb1 AK |
10451 | ; FIXME: There is also mvcin but we cannot use it since src and target |
10452 | ; may overlap. | |
07da44ab | 10453 | (define_insn "bswap<mode>2" |
6f5a59d1 AK |
10454 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,RT") |
10455 | (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT, d")))] | |
677fbff4 | 10456 | "TARGET_CPU_ZARCH" |
07da44ab AK |
10457 | "@ |
10458 | lrv<g>r\t%0,%1 | |
6f5a59d1 AK |
10459 | lrv<g>\t%0,%1 |
10460 | strv<g>\t%1,%0" | |
10461 | [(set_attr "type" "*,load,store") | |
10462 | (set_attr "op_type" "RRE,RXY,RXY") | |
07da44ab | 10463 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 10464 | |
511f5bb1 | 10465 | (define_insn "bswaphi2" |
6f5a59d1 AK |
10466 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d, d,RT") |
10467 | (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,RT, d")))] | |
511f5bb1 | 10468 | "TARGET_CPU_ZARCH" |
6f5a59d1 AK |
10469 | "@ |
10470 | # | |
10471 | lrvh\t%0,%1 | |
10472 | strvh\t%1,%0" | |
10473 | [(set_attr "type" "*,load,store") | |
10474 | (set_attr "op_type" "RRE,RXY,RXY") | |
511f5bb1 | 10475 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 10476 | |
6f5a59d1 AK |
10477 | (define_split |
10478 | [(set (match_operand:HI 0 "register_operand" "") | |
10479 | (bswap:HI (match_operand:HI 1 "register_operand" "")))] | |
10480 | "TARGET_CPU_ZARCH" | |
10481 | [(set (match_dup 2) (bswap:SI (match_dup 3))) | |
10482 | (set (match_dup 2) (lshiftrt:SI (match_dup 2) | |
10483 | (const_int 16))) | |
10484 | (set (match_dup 0) (subreg:HI (match_dup 2) 2))] | |
10485 | { | |
10486 | operands[2] = gen_reg_rtx (SImode); | |
10487 | operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0); | |
10488 | }) | |
10489 | ||
10490 | ||
65b1d8ea AK |
10491 | ; |
10492 | ; Population count instruction | |
10493 | ; | |
10494 | ||
10495 | ; The S/390 popcount instruction counts the bits of op1 in 8 byte | |
10496 | ; portions and stores the result in the corresponding bytes in op0. | |
10497 | (define_insn "*popcount<mode>" | |
10498 | [(set (match_operand:INT 0 "register_operand" "=d") | |
10499 | (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) | |
10500 | (clobber (reg:CC CC_REGNUM))] | |
10501 | "TARGET_Z196" | |
10502 | "popcnt\t%0,%1" | |
10503 | [(set_attr "op_type" "RRE")]) | |
10504 | ||
10505 | (define_expand "popcountdi2" | |
10506 | [; popcnt op0, op1 | |
10507 | (parallel [(set (match_operand:DI 0 "register_operand" "") | |
10508 | (unspec:DI [(match_operand:DI 1 "register_operand")] | |
10509 | UNSPEC_POPCNT)) | |
10510 | (clobber (reg:CC CC_REGNUM))]) | |
10511 | ; sllg op2, op0, 32 | |
10512 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) | |
10513 | ; agr op0, op2 | |
10514 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10515 | (clobber (reg:CC CC_REGNUM))]) | |
10516 | ; sllg op2, op0, 16 | |
17465c6e | 10517 | (set (match_dup 2) |
65b1d8ea AK |
10518 | (ashift:DI (match_dup 0) (const_int 16))) |
10519 | ; agr op0, op2 | |
10520 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10521 | (clobber (reg:CC CC_REGNUM))]) | |
10522 | ; sllg op2, op0, 8 | |
10523 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) | |
10524 | ; agr op0, op2 | |
10525 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10526 | (clobber (reg:CC CC_REGNUM))]) | |
10527 | ; srlg op0, op0, 56 | |
10528 | (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] | |
10529 | "TARGET_Z196 && TARGET_64BIT" | |
10530 | "operands[2] = gen_reg_rtx (DImode);") | |
10531 | ||
10532 | (define_expand "popcountsi2" | |
10533 | [; popcnt op0, op1 | |
10534 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
10535 | (unspec:SI [(match_operand:SI 1 "register_operand")] | |
10536 | UNSPEC_POPCNT)) | |
10537 | (clobber (reg:CC CC_REGNUM))]) | |
10538 | ; sllk op2, op0, 16 | |
17465c6e | 10539 | (set (match_dup 2) |
65b1d8ea AK |
10540 | (ashift:SI (match_dup 0) (const_int 16))) |
10541 | ; ar op0, op2 | |
10542 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
10543 | (clobber (reg:CC CC_REGNUM))]) | |
10544 | ; sllk op2, op0, 8 | |
10545 | (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) | |
10546 | ; ar op0, op2 | |
10547 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
10548 | (clobber (reg:CC CC_REGNUM))]) | |
10549 | ; srl op0, op0, 24 | |
10550 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | |
10551 | "TARGET_Z196" | |
10552 | "operands[2] = gen_reg_rtx (SImode);") | |
10553 | ||
10554 | (define_expand "popcounthi2" | |
10555 | [; popcnt op0, op1 | |
10556 | (parallel [(set (match_operand:HI 0 "register_operand" "") | |
10557 | (unspec:HI [(match_operand:HI 1 "register_operand")] | |
10558 | UNSPEC_POPCNT)) | |
10559 | (clobber (reg:CC CC_REGNUM))]) | |
10560 | ; sllk op2, op0, 8 | |
17465c6e | 10561 | (set (match_dup 2) |
65b1d8ea AK |
10562 | (ashift:SI (match_dup 0) (const_int 8))) |
10563 | ; ar op0, op2 | |
10564 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
10565 | (clobber (reg:CC CC_REGNUM))]) | |
10566 | ; srl op0, op0, 8 | |
10567 | (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] | |
10568 | "TARGET_Z196" | |
10569 | "operands[2] = gen_reg_rtx (SImode);") | |
10570 | ||
10571 | (define_expand "popcountqi2" | |
10572 | [; popcnt op0, op1 | |
10573 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
10574 | (unspec:QI [(match_operand:QI 1 "register_operand")] | |
10575 | UNSPEC_POPCNT)) | |
10576 | (clobber (reg:CC CC_REGNUM))])] | |
10577 | "TARGET_Z196" | |
10578 | "") | |
10579 | ||
10580 | ;; | |
10581 | ;;- Copy sign instructions | |
10582 | ;; | |
10583 | ||
10584 | (define_insn "copysign<mode>3" | |
10585 | [(set (match_operand:FP 0 "register_operand" "=f") | |
10586 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
10587 | (match_operand:FP 2 "register_operand" "f")] | |
10588 | UNSPEC_COPYSIGN))] | |
10589 | "TARGET_Z196" | |
10590 | "cpsdr\t%0,%2,%1" | |
10591 | [(set_attr "op_type" "RRF") | |
10592 | (set_attr "type" "fsimp<mode>")]) | |
5a3fe9b6 AK |
10593 | |
10594 | ||
10595 | ;; | |
10596 | ;;- Transactional execution instructions | |
10597 | ;; | |
10598 | ||
10599 | ; This splitter helps combine to make use of CC directly when | |
10600 | ; comparing the integer result of a tbegin builtin with a constant. | |
10601 | ; The unspec is already removed by canonicalize_comparison. So this | |
10602 | ; splitters only job is to turn the PARALLEL into separate insns | |
10603 | ; again. Unfortunately this only works with the very first cc/int | |
10604 | ; compare since combine is not able to deal with data flow across | |
10605 | ; basic block boundaries. | |
10606 | ||
10607 | ; It needs to be an insn pattern as well since combine does not apply | |
10608 | ; the splitter directly. Combine would only use it if it actually | |
10609 | ; would reduce the number of instructions. | |
10610 | (define_insn_and_split "*ccraw_to_int" | |
10611 | [(set (pc) | |
10612 | (if_then_else | |
10613 | (match_operator 0 "s390_eqne_operator" | |
10614 | [(reg:CCRAW CC_REGNUM) | |
10615 | (match_operand 1 "const_int_operand" "")]) | |
10616 | (label_ref (match_operand 2 "" "")) | |
10617 | (pc))) | |
10618 | (set (match_operand:SI 3 "register_operand" "=d") | |
10619 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] | |
10620 | "" | |
10621 | "#" | |
10622 | "" | |
10623 | [(set (match_dup 3) | |
10624 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) | |
10625 | (set (pc) | |
10626 | (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)]) | |
10627 | (label_ref (match_dup 2)) | |
10628 | (pc)))] | |
10629 | "") | |
10630 | ||
10631 | ; Non-constrained transaction begin | |
10632 | ||
10633 | (define_expand "tbegin" | |
ee163e72 AK |
10634 | [(match_operand:SI 0 "register_operand" "") |
10635 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
10636 | "TARGET_HTM" |
10637 | { | |
10638 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true); | |
10639 | DONE; | |
10640 | }) | |
10641 | ||
10642 | (define_expand "tbegin_nofloat" | |
ee163e72 AK |
10643 | [(match_operand:SI 0 "register_operand" "") |
10644 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
10645 | "TARGET_HTM" |
10646 | { | |
10647 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false); | |
10648 | DONE; | |
10649 | }) | |
10650 | ||
10651 | (define_expand "tbegin_retry" | |
ee163e72 AK |
10652 | [(match_operand:SI 0 "register_operand" "") |
10653 | (match_operand:BLK 1 "memory_operand" "") | |
10654 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
10655 | "TARGET_HTM" |
10656 | { | |
10657 | s390_expand_tbegin (operands[0], operands[1], operands[2], true); | |
10658 | DONE; | |
10659 | }) | |
10660 | ||
10661 | (define_expand "tbegin_retry_nofloat" | |
ee163e72 AK |
10662 | [(match_operand:SI 0 "register_operand" "") |
10663 | (match_operand:BLK 1 "memory_operand" "") | |
10664 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
10665 | "TARGET_HTM" |
10666 | { | |
10667 | s390_expand_tbegin (operands[0], operands[1], operands[2], false); | |
10668 | DONE; | |
10669 | }) | |
10670 | ||
c914ac45 AK |
10671 | ; Clobber VRs since they don't get restored |
10672 | (define_insn "tbegin_1_z13" | |
10673 | [(set (reg:CCRAW CC_REGNUM) | |
10674 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] | |
10675 | UNSPECV_TBEGIN)) | |
10676 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
10677 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
10678 | (clobber (reg:TI 16)) (clobber (reg:TI 38)) | |
10679 | (clobber (reg:TI 17)) (clobber (reg:TI 39)) | |
10680 | (clobber (reg:TI 18)) (clobber (reg:TI 40)) | |
10681 | (clobber (reg:TI 19)) (clobber (reg:TI 41)) | |
10682 | (clobber (reg:TI 20)) (clobber (reg:TI 42)) | |
10683 | (clobber (reg:TI 21)) (clobber (reg:TI 43)) | |
10684 | (clobber (reg:TI 22)) (clobber (reg:TI 44)) | |
10685 | (clobber (reg:TI 23)) (clobber (reg:TI 45)) | |
10686 | (clobber (reg:TI 24)) (clobber (reg:TI 46)) | |
10687 | (clobber (reg:TI 25)) (clobber (reg:TI 47)) | |
10688 | (clobber (reg:TI 26)) (clobber (reg:TI 48)) | |
10689 | (clobber (reg:TI 27)) (clobber (reg:TI 49)) | |
10690 | (clobber (reg:TI 28)) (clobber (reg:TI 50)) | |
10691 | (clobber (reg:TI 29)) (clobber (reg:TI 51)) | |
10692 | (clobber (reg:TI 30)) (clobber (reg:TI 52)) | |
10693 | (clobber (reg:TI 31)) (clobber (reg:TI 53))] | |
10694 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
10695 | ; not supposed to be used for immediates (see genpreds.c). | |
10696 | "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
10697 | "tbegin\t%1,%x0" | |
10698 | [(set_attr "op_type" "SIL")]) | |
10699 | ||
5a3fe9b6 AK |
10700 | (define_insn "tbegin_1" |
10701 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d | 10702 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
5a3fe9b6 | 10703 | UNSPECV_TBEGIN)) |
2561451d AK |
10704 | (set (match_operand:BLK 1 "memory_operand" "=Q") |
10705 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
5a3fe9b6 AK |
10706 | (clobber (reg:DF 16)) |
10707 | (clobber (reg:DF 17)) | |
10708 | (clobber (reg:DF 18)) | |
10709 | (clobber (reg:DF 19)) | |
10710 | (clobber (reg:DF 20)) | |
10711 | (clobber (reg:DF 21)) | |
10712 | (clobber (reg:DF 22)) | |
10713 | (clobber (reg:DF 23)) | |
10714 | (clobber (reg:DF 24)) | |
10715 | (clobber (reg:DF 25)) | |
10716 | (clobber (reg:DF 26)) | |
10717 | (clobber (reg:DF 27)) | |
10718 | (clobber (reg:DF 28)) | |
10719 | (clobber (reg:DF 29)) | |
10720 | (clobber (reg:DF 30)) | |
10721 | (clobber (reg:DF 31))] | |
10722 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
10723 | ; not supposed to be used for immediates (see genpreds.c). | |
2561451d AK |
10724 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" |
10725 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
10726 | [(set_attr "op_type" "SIL")]) |
10727 | ||
10728 | ; Same as above but without the FPR clobbers | |
10729 | (define_insn "tbegin_nofloat_1" | |
10730 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d AK |
10731 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
10732 | UNSPECV_TBEGIN)) | |
10733 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
10734 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))] | |
10735 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
10736 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
10737 | [(set_attr "op_type" "SIL")]) |
10738 | ||
10739 | ||
10740 | ; Constrained transaction begin | |
10741 | ||
10742 | (define_expand "tbeginc" | |
10743 | [(set (reg:CCRAW CC_REGNUM) | |
10744 | (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)] | |
10745 | UNSPECV_TBEGINC))] | |
10746 | "TARGET_HTM" | |
10747 | "") | |
10748 | ||
10749 | (define_insn "*tbeginc_1" | |
10750 | [(set (reg:CCRAW CC_REGNUM) | |
10751 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")] | |
10752 | UNSPECV_TBEGINC))] | |
10753 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
10754 | "tbeginc\t0,%x0" | |
10755 | [(set_attr "op_type" "SIL")]) | |
10756 | ||
10757 | ; Transaction end | |
10758 | ||
10759 | (define_expand "tend" | |
10760 | [(set (reg:CCRAW CC_REGNUM) | |
10761 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND)) | |
ee163e72 | 10762 | (set (match_operand:SI 0 "register_operand" "") |
5a3fe9b6 AK |
10763 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] |
10764 | "TARGET_HTM" | |
10765 | "") | |
10766 | ||
10767 | (define_insn "*tend_1" | |
10768 | [(set (reg:CCRAW CC_REGNUM) | |
10769 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))] | |
10770 | "TARGET_HTM" | |
10771 | "tend" | |
10772 | [(set_attr "op_type" "S")]) | |
10773 | ||
10774 | ; Transaction abort | |
10775 | ||
10776 | (define_expand "tabort" | |
ee163e72 | 10777 | [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "")] |
5a3fe9b6 AK |
10778 | UNSPECV_TABORT)] |
10779 | "TARGET_HTM && operands != NULL" | |
10780 | { | |
10781 | if (CONST_INT_P (operands[0]) | |
10782 | && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255) | |
10783 | { | |
10784 | error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC | |
10785 | ". Values in range 0 through 255 are reserved.", | |
10786 | INTVAL (operands[0])); | |
10787 | FAIL; | |
10788 | } | |
10789 | }) | |
10790 | ||
10791 | (define_insn "*tabort_1" | |
ee163e72 | 10792 | [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "Y")] |
5a3fe9b6 AK |
10793 | UNSPECV_TABORT)] |
10794 | "TARGET_HTM && operands != NULL" | |
10795 | "tabort\t%Y0" | |
10796 | [(set_attr "op_type" "S")]) | |
10797 | ||
10798 | ; Transaction extract nesting depth | |
10799 | ||
10800 | (define_insn "etnd" | |
10801 | [(set (match_operand:SI 0 "register_operand" "=d") | |
10802 | (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))] | |
10803 | "TARGET_HTM" | |
10804 | "etnd\t%0" | |
10805 | [(set_attr "op_type" "RRE")]) | |
10806 | ||
10807 | ; Non-transactional store | |
10808 | ||
10809 | (define_insn "ntstg" | |
10810 | [(set (match_operand:DI 0 "memory_operand" "=RT") | |
10811 | (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] | |
10812 | UNSPECV_NTSTG))] | |
10813 | "TARGET_HTM" | |
10814 | "ntstg\t%1,%0" | |
10815 | [(set_attr "op_type" "RXY")]) | |
10816 | ||
10817 | ; Transaction perform processor assist | |
10818 | ||
10819 | (define_expand "tx_assist" | |
2561451d AK |
10820 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "") |
10821 | (reg:SI GPR0_REGNUM) | |
5a3fe9b6 AK |
10822 | (const_int 1)] |
10823 | UNSPECV_PPA)] | |
10824 | "TARGET_HTM" | |
2561451d | 10825 | "") |
5a3fe9b6 AK |
10826 | |
10827 | (define_insn "*ppa" | |
10828 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") | |
10829 | (match_operand:SI 1 "register_operand" "d") | |
10830 | (match_operand 2 "const_int_operand" "I")] | |
10831 | UNSPECV_PPA)] | |
10832 | "TARGET_HTM && INTVAL (operands[2]) < 16" | |
2561451d | 10833 | "ppa\t%0,%1,%2" |
5a3fe9b6 | 10834 | [(set_attr "op_type" "RRF")]) |
004f64e1 AK |
10835 | |
10836 | ||
10837 | ; Set and get floating point control register | |
10838 | ||
3af82a61 | 10839 | (define_insn "sfpc" |
004f64e1 AK |
10840 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] |
10841 | UNSPECV_SFPC)] | |
10842 | "TARGET_HARD_FLOAT" | |
10843 | "sfpc\t%0") | |
10844 | ||
3af82a61 | 10845 | (define_insn "efpc" |
004f64e1 AK |
10846 | [(set (match_operand:SI 0 "register_operand" "=d") |
10847 | (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))] | |
10848 | "TARGET_HARD_FLOAT" | |
10849 | "efpc\t%0") | |
3af82a61 AK |
10850 | |
10851 | ||
10852 | ; Load count to block boundary | |
10853 | ||
10854 | (define_insn "lcbb" | |
10855 | [(set (match_operand:SI 0 "register_operand" "=d") | |
10856 | (unspec:SI [(match_operand:SI 1 "address_operand" "ZQZR") | |
10857 | (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB)) | |
10858 | (clobber (reg:CC CC_REGNUM))] | |
10859 | "TARGET_Z13" | |
10860 | "lcbb\t%0,%1,%b2" | |
10861 | [(set_attr "op_type" "VRX")]) |