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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
283334f0 KH |
2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004 |
3 | ;; Free Software Foundation, Inc. | |
9db1d521 | 4 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
f314b9b1 | 5 | ;; Ulrich Weigand (uweigand@de.ibm.com). |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
11 | ;; Software Foundation; either version 2, or (at your option) any later | |
12 | ;; version. | |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
58add37a UW |
20 | ;; along with GCC; see the file COPYING. If not, write to the Free |
21 | ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA | |
22 | ;; 02111-1307, USA. | |
9db1d521 HP |
23 | |
24 | ;; | |
25 | ;; Special constraints for s/390 machine description: | |
26 | ;; | |
27 | ;; a -- Any address register from 1 to 15. | |
28 | ;; d -- Any register from 0 to 15. | |
29 | ;; I -- An 8-bit constant (0..255). | |
30 | ;; J -- A 12-bit constant (0..4095). | |
31 | ;; K -- A 16-bit constant (-32768..32767). | |
f19a9af7 AK |
32 | ;; L -- Value appropriate as displacement. |
33 | ;; (0..4095) for short displacement | |
34 | ;; (-524288..524287) for long displacement | |
35 | ;; M -- Constant integer with a value of 0x7fffffff. | |
36 | ;; N -- Multiple letter constraint followed by 4 parameter letters. | |
37 | ;; 0..9: number of the part counting from most to least significant | |
38 | ;; H,Q: mode of the part | |
39 | ;; D,S,H: mode of the containing operand | |
40 | ;; 0,F: value of the other parts (F - all bits set) | |
41 | ;; | |
42 | ;; The constraint matches if the specified part of a constant | |
43 | ;; has a value different from its other parts. | |
44 | ;; Q -- Memory reference without index register and with short displacement. | |
45 | ;; R -- Memory reference with index register and short displacement. | |
46 | ;; S -- Memory reference without index register but with long displacement. | |
47 | ;; T -- Memory reference with index register and long displacement. | |
48 | ;; U -- Pointer with short displacement. | |
49 | ;; W -- Pointer with long displacement. | |
50 | ;; Y -- Shift count operand. | |
9db1d521 HP |
51 | ;; |
52 | ;; Special formats used for outputting 390 instructions. | |
53 | ;; | |
f19a9af7 AK |
54 | ;; %C: print opcode suffix for branch condition. |
55 | ;; %D: print opcode suffix for inverse branch condition. | |
56 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
57 | ;; %O: print only the displacement of a memory reference. | |
58 | ;; %R: print only the base register of a memory reference. | |
59 | ;; %N: print the second word of a DImode operand. | |
60 | ;; %M: print the second word of a TImode operand. | |
61 | ||
62 | ;; %b: print integer X as if it's an unsigned byte. | |
63 | ;; %x: print integer X as if it's an unsigned word. | |
64 | ;; %h: print integer X as if it's a signed word. | |
65 | ;; %i: print the first nonzero HImode part of X | |
66 | ;; %j: print the first HImode part unequal to 0xffff of X | |
67 | ||
9db1d521 HP |
68 | ;; |
69 | ;; We have a special constraint for pattern matching. | |
70 | ;; | |
71 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
72 | ;; | |
9db1d521 | 73 | |
fd3cd001 UW |
74 | ;; |
75 | ;; UNSPEC usage | |
76 | ;; | |
77 | ||
78 | (define_constants | |
10bbf137 UW |
79 | [; Miscellaneous |
80 | (UNSPEC_ROUND 1) | |
81 | (UNSPEC_SETHIGH 10) | |
82 | ||
83 | ; GOT/PLT and lt-relative accesses | |
fd7643fb UW |
84 | (UNSPEC_LTREL_OFFSET 100) |
85 | (UNSPEC_LTREL_BASE 101) | |
86 | (UNSPEC_GOTENT 110) | |
87 | (UNSPEC_GOT 111) | |
88 | (UNSPEC_GOTOFF 112) | |
89 | (UNSPEC_PLT 113) | |
90 | (UNSPEC_PLTOFF 114) | |
91 | ||
92 | ; Literal pool | |
93 | (UNSPEC_RELOAD_BASE 210) | |
5af2f3d3 | 94 | (UNSPEC_MAIN_BASE 211) |
fd7643fb UW |
95 | |
96 | ; TLS relocation specifiers | |
fd3cd001 UW |
97 | (UNSPEC_TLSGD 500) |
98 | (UNSPEC_TLSLDM 501) | |
99 | (UNSPEC_NTPOFF 502) | |
100 | (UNSPEC_DTPOFF 503) | |
101 | (UNSPEC_GOTNTPOFF 504) | |
102 | (UNSPEC_INDNTPOFF 505) | |
103 | ||
104 | ; TLS support | |
105 | (UNSPEC_TP 510) | |
106 | (UNSPEC_TLSLDM_NTPOFF 511) | |
107 | (UNSPEC_TLS_LOAD 512) | |
91d39d71 UW |
108 | |
109 | ; String Functions | |
110 | (UNSPEC_SRST 600) | |
fd3cd001 UW |
111 | ]) |
112 | ||
113 | ;; | |
114 | ;; UNSPEC_VOLATILE usage | |
115 | ;; | |
116 | ||
117 | (define_constants | |
10bbf137 UW |
118 | [; Blockage |
119 | (UNSPECV_BLOCKAGE 0) | |
120 | ||
121 | ; Literal pool | |
fd7643fb UW |
122 | (UNSPECV_POOL 200) |
123 | (UNSPECV_POOL_START 201) | |
124 | (UNSPECV_POOL_END 202) | |
416cf582 | 125 | (UNSPECV_POOL_ENTRY 203) |
fd7643fb UW |
126 | (UNSPECV_MAIN_POOL 300) |
127 | ||
128 | ; TLS support | |
fd3cd001 UW |
129 | (UNSPECV_SET_TP 500) |
130 | ]) | |
131 | ||
132 | ||
1fec52be HP |
133 | ;; Processor type. This attribute must exactly match the processor_type |
134 | ;; enumeration in s390.h. | |
135 | ||
f13e0d4e UW |
136 | (define_attr "cpu" "g5,g6,z900,z990" |
137 | (const (symbol_ref "s390_tune"))) | |
9db1d521 | 138 | |
f2d3c02a HP |
139 | ;; Define an insn type attribute. This is used in function unit delay |
140 | ;; computations. | |
9db1d521 | 141 | |
077dab3b HP |
142 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
143 | cs,vs,store,imul,idiv, | |
144 | branch,jsr,fsimpd,fsimps, | |
145 | floadd,floads,fstored, fstores, | |
146 | fmuld,fmuls,fdivd,fdivs, | |
147 | ftoi,itof,fsqrtd,fsqrts, | |
148 | other,o2,o3" | |
c7453384 | 149 | (const_string "integer")) |
9db1d521 | 150 | |
077dab3b | 151 | ;; Operand type. Used to default length attribute values |
9db1d521 | 152 | |
077dab3b | 153 | (define_attr "op_type" |
d3632d41 | 154 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY" |
077dab3b HP |
155 | (const_string "RX")) |
156 | ||
157 | ;; Insn are devide in two classes: | |
158 | ;; agen: Insn using agen | |
159 | ;; reg: Insn not using agen | |
160 | ||
161 | (define_attr "atype" "agen,reg" | |
162 | (cond [ (eq_attr "op_type" "E") (const_string "reg") | |
163 | (eq_attr "op_type" "RR") (const_string "reg") | |
164 | (eq_attr "op_type" "RX") (const_string "agen") | |
165 | (eq_attr "op_type" "RI") (const_string "reg") | |
166 | (eq_attr "op_type" "RRE") (const_string "reg") | |
167 | (eq_attr "op_type" "RS") (const_string "agen") | |
168 | (eq_attr "op_type" "RSI") (const_string "agen") | |
169 | (eq_attr "op_type" "S") (const_string "agen") | |
170 | (eq_attr "op_type" "SI") (const_string "agen") | |
171 | (eq_attr "op_type" "SS") (const_string "agen") | |
172 | (eq_attr "op_type" "SSE") (const_string "agen") | |
173 | (eq_attr "op_type" "RXE") (const_string "agen") | |
174 | (eq_attr "op_type" "RSE") (const_string "agen") | |
d3632d41 UW |
175 | (eq_attr "op_type" "RIL") (const_string "agen") |
176 | (eq_attr "op_type" "RXY") (const_string "agen") | |
177 | (eq_attr "op_type" "RSY") (const_string "agen") | |
178 | (eq_attr "op_type" "SIY") (const_string "agen")] | |
077dab3b | 179 | (const_string "reg"))) |
9db1d521 | 180 | |
c7453384 | 181 | ;; Generic pipeline function unit. |
9db1d521 | 182 | |
4023fb28 UW |
183 | (define_function_unit "integer" 1 0 |
184 | (eq_attr "type" "none") 0 0) | |
185 | ||
f2d3c02a HP |
186 | (define_function_unit "integer" 1 0 |
187 | (eq_attr "type" "integer") 1 1) | |
9db1d521 | 188 | |
077dab3b HP |
189 | (define_function_unit "integer" 1 0 |
190 | (eq_attr "type" "fsimpd") 1 1) | |
191 | ||
192 | (define_function_unit "integer" 1 0 | |
193 | (eq_attr "type" "fsimps") 1 1) | |
194 | ||
f2d3c02a HP |
195 | (define_function_unit "integer" 1 0 |
196 | (eq_attr "type" "load") 1 1) | |
9db1d521 | 197 | |
077dab3b HP |
198 | (define_function_unit "integer" 1 0 |
199 | (eq_attr "type" "floadd") 1 1) | |
200 | ||
201 | (define_function_unit "integer" 1 0 | |
202 | (eq_attr "type" "floads") 1 1) | |
203 | ||
f2d3c02a HP |
204 | (define_function_unit "integer" 1 0 |
205 | (eq_attr "type" "la") 1 1) | |
9db1d521 | 206 | |
077dab3b HP |
207 | (define_function_unit "integer" 1 0 |
208 | (eq_attr "type" "larl") 1 1) | |
209 | ||
f2d3c02a HP |
210 | (define_function_unit "integer" 1 0 |
211 | (eq_attr "type" "lr") 1 1) | |
9db1d521 | 212 | |
077dab3b HP |
213 | (define_function_unit "integer" 1 0 |
214 | (eq_attr "type" "branch") 1 1) | |
215 | ||
f2d3c02a HP |
216 | (define_function_unit "integer" 1 0 |
217 | (eq_attr "type" "store") 1 1) | |
9db1d521 | 218 | |
077dab3b HP |
219 | (define_function_unit "integer" 1 0 |
220 | (eq_attr "type" "fstored") 1 1) | |
221 | ||
222 | (define_function_unit "integer" 1 0 | |
223 | (eq_attr "type" "fstores") 1 1) | |
224 | ||
4023fb28 UW |
225 | (define_function_unit "integer" 1 0 |
226 | (eq_attr "type" "lm") 2 2) | |
227 | ||
228 | (define_function_unit "integer" 1 0 | |
229 | (eq_attr "type" "stm") 2 2) | |
230 | ||
231 | (define_function_unit "integer" 1 0 | |
232 | (eq_attr "type" "cs") 5 5) | |
233 | ||
234 | (define_function_unit "integer" 1 0 | |
235 | (eq_attr "type" "vs") 30 30) | |
236 | ||
f2d3c02a HP |
237 | (define_function_unit "integer" 1 0 |
238 | (eq_attr "type" "jsr") 5 5) | |
9db1d521 | 239 | |
f2d3c02a HP |
240 | (define_function_unit "integer" 1 0 |
241 | (eq_attr "type" "imul") 7 7) | |
242 | ||
243 | (define_function_unit "integer" 1 0 | |
077dab3b HP |
244 | (eq_attr "type" "fmuld") 6 6) |
245 | ||
246 | (define_function_unit "integer" 1 0 | |
247 | (eq_attr "type" "fmuls") 6 6) | |
9db1d521 | 248 | |
f2d3c02a HP |
249 | (define_function_unit "integer" 1 0 |
250 | (eq_attr "type" "idiv") 33 33) | |
9db1d521 | 251 | |
f2d3c02a | 252 | (define_function_unit "integer" 1 0 |
077dab3b HP |
253 | (eq_attr "type" "fdivd") 33 33) |
254 | ||
255 | (define_function_unit "integer" 1 0 | |
256 | (eq_attr "type" "fdivs") 33 33) | |
257 | ||
258 | (define_function_unit "integer" 1 0 | |
259 | (eq_attr "type" "fsqrtd") 30 30) | |
260 | ||
261 | (define_function_unit "integer" 1 0 | |
262 | (eq_attr "type" "fsqrts") 30 30) | |
263 | ||
264 | (define_function_unit "integer" 1 0 | |
265 | (eq_attr "type" "ftoi") 2 2) | |
266 | ||
267 | (define_function_unit "integer" 1 0 | |
268 | (eq_attr "type" "itof") 2 2) | |
9db1d521 | 269 | |
f2d3c02a HP |
270 | (define_function_unit "integer" 1 0 |
271 | (eq_attr "type" "o2") 2 2) | |
9db1d521 | 272 | |
f2d3c02a HP |
273 | (define_function_unit "integer" 1 0 |
274 | (eq_attr "type" "o3") 3 3) | |
9db1d521 | 275 | |
f2d3c02a HP |
276 | (define_function_unit "integer" 1 0 |
277 | (eq_attr "type" "other") 5 5) | |
278 | ||
077dab3b | 279 | ;; Pipeline description for z900 |
9db1d521 | 280 | |
077dab3b | 281 | (include "2064.md") |
52609473 | 282 | (include "2084.md") |
9db1d521 HP |
283 | |
284 | ;; Length in bytes. | |
285 | ||
286 | (define_attr "length" "" | |
287 | (cond [ (eq_attr "op_type" "E") (const_int 2) | |
288 | (eq_attr "op_type" "RR") (const_int 2) | |
289 | (eq_attr "op_type" "RX") (const_int 4) | |
290 | (eq_attr "op_type" "RI") (const_int 4) | |
291 | (eq_attr "op_type" "RRE") (const_int 4) | |
292 | (eq_attr "op_type" "RS") (const_int 4) | |
293 | (eq_attr "op_type" "RSI") (const_int 4) | |
9db1d521 HP |
294 | (eq_attr "op_type" "S") (const_int 4) |
295 | (eq_attr "op_type" "SI") (const_int 4) | |
296 | (eq_attr "op_type" "SS") (const_int 6) | |
297 | (eq_attr "op_type" "SSE") (const_int 6) | |
298 | (eq_attr "op_type" "RXE") (const_int 6) | |
299 | (eq_attr "op_type" "RSE") (const_int 6) | |
d3632d41 UW |
300 | (eq_attr "op_type" "RIL") (const_int 6) |
301 | (eq_attr "op_type" "RXY") (const_int 6) | |
302 | (eq_attr "op_type" "RSY") (const_int 6) | |
303 | (eq_attr "op_type" "SIY") (const_int 6)] | |
9db1d521 HP |
304 | (const_int 4))) |
305 | ||
306 | ;; Define attributes for `asm' insns. | |
307 | ||
f2d3c02a | 308 | (define_asm_attributes [(set_attr "type" "other") |
9db1d521 HP |
309 | (set_attr "op_type" "NN")]) |
310 | ||
311 | ;; | |
312 | ;; Condition Codes | |
313 | ;; | |
314 | ; | |
315 | ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR) | |
316 | ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA) | |
317 | ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM) | |
318 | ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM) | |
319 | ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML) | |
c7453384 | 320 | |
9db1d521 HP |
321 | ; CCZ -> CCL / CCZ1 |
322 | ; CCZ1 -> CCA/CCU/CCS/CCT | |
323 | ; CCS -> CCA | |
c7453384 | 324 | |
9db1d521 HP |
325 | ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST |
326 | ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT | |
327 | ||
328 | ||
329 | ;; | |
330 | ;;- Compare instructions. | |
331 | ;; | |
332 | ||
333 | (define_expand "cmpdi" | |
334 | [(set (reg:CC 33) | |
335 | (compare:CC (match_operand:DI 0 "register_operand" "") | |
336 | (match_operand:DI 1 "general_operand" "")))] | |
337 | "TARGET_64BIT" | |
9db1d521 HP |
338 | { |
339 | s390_compare_op0 = operands[0]; | |
340 | s390_compare_op1 = operands[1]; | |
341 | DONE; | |
10bbf137 | 342 | }) |
9db1d521 HP |
343 | |
344 | (define_expand "cmpsi" | |
345 | [(set (reg:CC 33) | |
346 | (compare:CC (match_operand:SI 0 "register_operand" "") | |
347 | (match_operand:SI 1 "general_operand" "")))] | |
348 | "" | |
9db1d521 HP |
349 | { |
350 | s390_compare_op0 = operands[0]; | |
351 | s390_compare_op1 = operands[1]; | |
352 | DONE; | |
10bbf137 | 353 | }) |
9db1d521 | 354 | |
9db1d521 HP |
355 | (define_expand "cmpdf" |
356 | [(set (reg:CC 33) | |
357 | (compare:CC (match_operand:DF 0 "register_operand" "") | |
358 | (match_operand:DF 1 "general_operand" "")))] | |
359 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
360 | { |
361 | s390_compare_op0 = operands[0]; | |
362 | s390_compare_op1 = operands[1]; | |
363 | DONE; | |
10bbf137 | 364 | }) |
9db1d521 HP |
365 | |
366 | (define_expand "cmpsf" | |
367 | [(set (reg:CC 33) | |
368 | (compare:CC (match_operand:SF 0 "register_operand" "") | |
369 | (match_operand:SF 1 "general_operand" "")))] | |
370 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
371 | { |
372 | s390_compare_op0 = operands[0]; | |
373 | s390_compare_op1 = operands[1]; | |
374 | DONE; | |
10bbf137 | 375 | }) |
9db1d521 HP |
376 | |
377 | ||
07893d4f | 378 | ; Test-under-Mask (zero_extract) instructions |
9db1d521 | 379 | |
07893d4f | 380 | (define_insn "*tmdi_ext" |
9db1d521 HP |
381 | [(set (reg 33) |
382 | (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d") | |
4023fb28 UW |
383 | (match_operand:DI 1 "const_int_operand" "n") |
384 | (match_operand:DI 2 "const_int_operand" "n")) | |
9db1d521 | 385 | (const_int 0)))] |
4023fb28 | 386 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT |
c7453384 | 387 | && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 |
4023fb28 UW |
388 | && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64 |
389 | && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4 | |
390 | == INTVAL (operands[2]) >> 4" | |
9db1d521 | 391 | { |
4023fb28 UW |
392 | int part = INTVAL (operands[2]) >> 4; |
393 | int block = (1 << INTVAL (operands[1])) - 1; | |
394 | int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15); | |
9db1d521 | 395 | |
4023fb28 | 396 | operands[2] = GEN_INT (block << shift); |
9db1d521 | 397 | |
4023fb28 UW |
398 | switch (part) |
399 | { | |
d40c829f UW |
400 | case 0: return "tmhh\t%0,%x2"; |
401 | case 1: return "tmhl\t%0,%x2"; | |
402 | case 2: return "tmlh\t%0,%x2"; | |
403 | case 3: return "tmll\t%0,%x2"; | |
4023fb28 UW |
404 | default: abort (); |
405 | } | |
10bbf137 | 406 | } |
4023fb28 UW |
407 | [(set_attr "op_type" "RI")]) |
408 | ||
07893d4f | 409 | (define_insn "*tmsi_ext" |
9db1d521 | 410 | [(set (reg 33) |
07893d4f UW |
411 | (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d") |
412 | (match_operand:SI 1 "const_int_operand" "n") | |
413 | (match_operand:SI 2 "const_int_operand" "n")) | |
9db1d521 | 414 | (const_int 0)))] |
07893d4f | 415 | "s390_match_ccmode(insn, CCTmode) |
c7453384 | 416 | && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 |
07893d4f UW |
417 | && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32 |
418 | && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4 | |
419 | == INTVAL (operands[2]) >> 4" | |
9db1d521 | 420 | { |
07893d4f UW |
421 | int part = INTVAL (operands[2]) >> 4; |
422 | int block = (1 << INTVAL (operands[1])) - 1; | |
423 | int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15); | |
424 | ||
425 | operands[2] = GEN_INT (block << shift); | |
9db1d521 | 426 | |
4023fb28 | 427 | switch (part) |
9db1d521 | 428 | { |
d40c829f UW |
429 | case 0: return "tmh\t%0,%x2"; |
430 | case 1: return "tml\t%0,%x2"; | |
4023fb28 | 431 | default: abort (); |
9db1d521 | 432 | } |
10bbf137 | 433 | } |
4023fb28 UW |
434 | [(set_attr "op_type" "RI")]) |
435 | ||
19796784 | 436 | (define_insn "*tmqisi_ext" |
4023fb28 | 437 | [(set (reg 33) |
d3632d41 UW |
438 | (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,S") |
439 | (match_operand:SI 1 "const_int_operand" "n,n") | |
440 | (match_operand:SI 2 "const_int_operand" "n,n")) | |
4023fb28 | 441 | (const_int 0)))] |
19796784 | 442 | "!TARGET_64BIT && s390_match_ccmode(insn, CCTmode) |
c7453384 | 443 | && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 |
07893d4f | 444 | && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8" |
4023fb28 | 445 | { |
07893d4f UW |
446 | int block = (1 << INTVAL (operands[1])) - 1; |
447 | int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]); | |
9db1d521 | 448 | |
07893d4f | 449 | operands[2] = GEN_INT (block << shift); |
d40c829f | 450 | return which_alternative == 0 ? "tm\t%0,%b2" : "tmy\t%0,%b2"; |
10bbf137 | 451 | } |
d3632d41 | 452 | [(set_attr "op_type" "SI,SIY")]) |
9db1d521 | 453 | |
19796784 AK |
454 | (define_insn "*tmqidi_ext" |
455 | [(set (reg 33) | |
456 | (compare (zero_extract:DI (match_operand:QI 0 "memory_operand" "Q,S") | |
457 | (match_operand:SI 1 "const_int_operand" "n,n") | |
458 | (match_operand:SI 2 "const_int_operand" "n,n")) | |
459 | (const_int 0)))] | |
460 | "TARGET_64BIT && s390_match_ccmode(insn, CCTmode) | |
461 | && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 | |
462 | && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8" | |
463 | { | |
464 | int block = (1 << INTVAL (operands[1])) - 1; | |
465 | int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]); | |
466 | ||
467 | operands[2] = GEN_INT (block << shift); | |
468 | return which_alternative == 0 ? "tm\t%0,%b2" : "tmy\t%0,%b2"; | |
469 | } | |
470 | [(set_attr "op_type" "SI,SIY")]) | |
471 | ||
472 | ||
07893d4f | 473 | ; Test-under-Mask instructions |
9db1d521 | 474 | |
07893d4f UW |
475 | (define_insn "*tmdi_mem" |
476 | [(set (reg 33) | |
d3632d41 UW |
477 | (compare (and:DI (match_operand:DI 0 "memory_operand" "Q,S") |
478 | (match_operand:DI 1 "immediate_operand" "n,n")) | |
479 | (match_operand:DI 2 "immediate_operand" "n,n")))] | |
9e8327e3 | 480 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) |
f19a9af7 | 481 | && s390_single_part (operands[1], DImode, QImode, 0) >= 0" |
07893d4f | 482 | { |
f19a9af7 AK |
483 | int part = s390_single_part (operands[1], DImode, QImode, 0); |
484 | operands[1] = GEN_INT (s390_extract_part (operands[1], QImode, 0)); | |
07893d4f | 485 | |
c7453384 | 486 | operands[0] = gen_rtx_MEM (QImode, |
07893d4f | 487 | plus_constant (XEXP (operands[0], 0), part)); |
d40c829f | 488 | return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1"; |
10bbf137 | 489 | } |
d3632d41 | 490 | [(set_attr "op_type" "SI,SIY")]) |
07893d4f UW |
491 | |
492 | (define_insn "*tmsi_mem" | |
4023fb28 | 493 | [(set (reg 33) |
d3632d41 UW |
494 | (compare (and:SI (match_operand:SI 0 "memory_operand" "Q,S") |
495 | (match_operand:SI 1 "immediate_operand" "n,n")) | |
496 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
07893d4f | 497 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) |
f19a9af7 | 498 | && s390_single_part (operands[1], SImode, QImode, 0) >= 0" |
4023fb28 | 499 | { |
f19a9af7 AK |
500 | int part = s390_single_part (operands[1], SImode, QImode, 0); |
501 | operands[1] = GEN_INT (s390_extract_part (operands[1], QImode, 0)); | |
4023fb28 | 502 | |
c7453384 | 503 | operands[0] = gen_rtx_MEM (QImode, |
4023fb28 | 504 | plus_constant (XEXP (operands[0], 0), part)); |
d40c829f | 505 | return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1"; |
10bbf137 | 506 | } |
077dab3b | 507 | [(set_attr "op_type" "SI")]) |
9db1d521 | 508 | |
07893d4f | 509 | (define_insn "*tmhi_mem" |
9db1d521 | 510 | [(set (reg 33) |
d3632d41 UW |
511 | (compare (and:SI (subreg:SI (match_operand:HI 0 "memory_operand" "Q,S") 0) |
512 | (match_operand:SI 1 "immediate_operand" "n,n")) | |
513 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
07893d4f | 514 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0)) |
f19a9af7 | 515 | && s390_single_part (operands[1], HImode, QImode, 0) >= 0" |
07893d4f | 516 | { |
f19a9af7 AK |
517 | int part = s390_single_part (operands[1], HImode, QImode, 0); |
518 | operands[1] = GEN_INT (s390_extract_part (operands[1], QImode, 0)); | |
9db1d521 | 519 | |
c7453384 | 520 | operands[0] = gen_rtx_MEM (QImode, |
07893d4f | 521 | plus_constant (XEXP (operands[0], 0), part)); |
d40c829f | 522 | return which_alternative == 0 ? "tm\t%0,%b1" : "tmy\t%0,%b1"; |
10bbf137 | 523 | } |
077dab3b | 524 | [(set_attr "op_type" "SI")]) |
9db1d521 | 525 | |
07893d4f | 526 | (define_insn "*tmqi_mem" |
9db1d521 | 527 | [(set (reg 33) |
d3632d41 UW |
528 | (compare (and:SI (subreg:SI (match_operand:QI 0 "memory_operand" "Q,S") 0) |
529 | (match_operand:SI 1 "immediate_operand" "n,n")) | |
530 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
07893d4f | 531 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))" |
d3632d41 | 532 | "@ |
d40c829f UW |
533 | tm\t%0,%b1 |
534 | tmy\t%0,%b1" | |
d3632d41 | 535 | [(set_attr "op_type" "SI,SIY")]) |
9db1d521 | 536 | |
05b9aaaa UW |
537 | (define_insn "*tmdi_reg" |
538 | [(set (reg 33) | |
f19a9af7 AK |
539 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
540 | (match_operand:DI 1 "immediate_operand" | |
541 | "N0HD0,N1HD0,N2HD0,N3HD0")) | |
542 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
05b9aaaa UW |
543 | "TARGET_64BIT |
544 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) | |
f19a9af7 AK |
545 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
546 | "@ | |
547 | tmhh\t%0,%i1 | |
548 | tmhl\t%0,%i1 | |
549 | tmlh\t%0,%i1 | |
550 | tmll\t%0,%i1" | |
05b9aaaa UW |
551 | [(set_attr "op_type" "RI")]) |
552 | ||
553 | (define_insn "*tmsi_reg" | |
554 | [(set (reg 33) | |
f19a9af7 AK |
555 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
556 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
557 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
05b9aaaa | 558 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1)) |
f19a9af7 AK |
559 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
560 | "@ | |
561 | tmh\t%0,%i1 | |
562 | tml\t%0,%i1" | |
05b9aaaa UW |
563 | [(set_attr "op_type" "RI")]) |
564 | ||
07893d4f | 565 | (define_insn "*tmhi_full" |
9db1d521 | 566 | [(set (reg 33) |
07893d4f UW |
567 | (compare (match_operand:HI 0 "register_operand" "d") |
568 | (match_operand:HI 1 "immediate_operand" "n")))] | |
a556fd39 | 569 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))" |
d40c829f | 570 | "tml\t%0,65535" |
07893d4f | 571 | [(set_attr "op_type" "RX")]) |
9db1d521 | 572 | |
07893d4f | 573 | (define_insn "*tmqi_full" |
9db1d521 | 574 | [(set (reg 33) |
07893d4f UW |
575 | (compare (match_operand:QI 0 "register_operand" "d") |
576 | (match_operand:QI 1 "immediate_operand" "n")))] | |
a556fd39 | 577 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))" |
d40c829f | 578 | "tml\t%0,255" |
07893d4f | 579 | [(set_attr "op_type" "RI")]) |
9db1d521 | 580 | |
07893d4f UW |
581 | |
582 | ; Load-and-Test instructions | |
583 | ||
584 | (define_insn "*tstdi_sign" | |
9db1d521 | 585 | [(set (reg 33) |
07893d4f UW |
586 | (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0) |
587 | (const_int 32)) (const_int 32)) | |
588 | (match_operand:DI 1 "const0_operand" ""))) | |
589 | (set (match_operand:DI 2 "register_operand" "=d") | |
590 | (sign_extend:DI (match_dup 0)))] | |
591 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 592 | "ltgfr\t%2,%0" |
07893d4f UW |
593 | [(set_attr "op_type" "RRE")]) |
594 | ||
595 | (define_insn "*tstdi" | |
9db1d521 | 596 | [(set (reg 33) |
07893d4f UW |
597 | (compare (match_operand:DI 0 "register_operand" "d") |
598 | (match_operand:DI 1 "const0_operand" ""))) | |
599 | (set (match_operand:DI 2 "register_operand" "=d") | |
600 | (match_dup 0))] | |
601 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 602 | "ltgr\t%2,%0" |
07893d4f | 603 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 604 | |
07893d4f | 605 | (define_insn "*tstdi_cconly" |
9db1d521 | 606 | [(set (reg 33) |
07893d4f UW |
607 | (compare (match_operand:DI 0 "register_operand" "d") |
608 | (match_operand:DI 1 "const0_operand" "")))] | |
609 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 610 | "ltgr\t%0,%0" |
07893d4f | 611 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 612 | |
07893d4f UW |
613 | (define_insn "*tstdi_cconly_31" |
614 | [(set (reg 33) | |
615 | (compare (match_operand:DI 0 "register_operand" "d") | |
616 | (match_operand:DI 1 "const0_operand" "")))] | |
617 | "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" | |
d40c829f | 618 | "srda\t%0,0" |
077dab3b HP |
619 | [(set_attr "op_type" "RS") |
620 | (set_attr "atype" "reg")]) | |
621 | ||
4023fb28 | 622 | |
07893d4f UW |
623 | (define_insn "*tstsi" |
624 | [(set (reg 33) | |
d3632d41 | 625 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 626 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 627 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f UW |
628 | (match_dup 0))] |
629 | "s390_match_ccmode(insn, CCSmode)" | |
630 | "@ | |
d40c829f UW |
631 | ltr\t%2,%0 |
632 | icm\t%2,15,%0 | |
633 | icmy\t%2,15,%0" | |
d3632d41 | 634 | [(set_attr "op_type" "RR,RS,RSY")]) |
9db1d521 | 635 | |
07893d4f | 636 | (define_insn "*tstsi_cconly" |
4023fb28 | 637 | [(set (reg 33) |
d3632d41 | 638 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 639 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 640 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
641 | "s390_match_ccmode(insn, CCSmode)" |
642 | "@ | |
d40c829f UW |
643 | ltr\t%0,%0 |
644 | icm\t%2,15,%0 | |
645 | icmy\t%2,15,%0" | |
d3632d41 | 646 | [(set_attr "op_type" "RR,RS,RSY")]) |
4023fb28 | 647 | |
07893d4f UW |
648 | (define_insn "*tstsi_cconly2" |
649 | [(set (reg 33) | |
650 | (compare (match_operand:SI 0 "register_operand" "d") | |
651 | (match_operand:SI 1 "const0_operand" "")))] | |
652 | "s390_match_ccmode(insn, CCSmode)" | |
d40c829f | 653 | "ltr\t%0,%0" |
07893d4f | 654 | [(set_attr "op_type" "RR")]) |
4023fb28 | 655 | |
3af97654 UW |
656 | (define_insn "*tsthiCCT" |
657 | [(set (reg 33) | |
d3632d41 | 658 | (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 | 659 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 660 | (set (match_operand:HI 2 "register_operand" "=d,d,0") |
3af97654 UW |
661 | (match_dup 0))] |
662 | "s390_match_ccmode(insn, CCTmode)" | |
663 | "@ | |
d40c829f UW |
664 | icm\t%2,3,%0 |
665 | icmy\t%2,3,%0 | |
666 | tml\t%0,65535" | |
d3632d41 | 667 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 UW |
668 | |
669 | (define_insn "*tsthiCCT_cconly" | |
670 | [(set (reg 33) | |
d3632d41 | 671 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 672 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 673 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
674 | "s390_match_ccmode(insn, CCTmode)" |
675 | "@ | |
d40c829f UW |
676 | icm\t%2,3,%0 |
677 | icmy\t%2,3,%0 | |
678 | tml\t%0,65535" | |
d3632d41 | 679 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 | 680 | |
07893d4f | 681 | (define_insn "*tsthi" |
9db1d521 | 682 | [(set (reg 33) |
d3632d41 | 683 | (compare (match_operand:HI 0 "s_operand" "Q,S") |
9db1d521 | 684 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 685 | (set (match_operand:HI 2 "register_operand" "=d,d") |
9db1d521 HP |
686 | (match_dup 0))] |
687 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 688 | "@ |
d40c829f UW |
689 | icm\t%2,3,%0 |
690 | icmy\t%2,3,%0" | |
d3632d41 | 691 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 692 | |
07893d4f | 693 | (define_insn "*tsthi_cconly" |
9db1d521 | 694 | [(set (reg 33) |
d3632d41 | 695 | (compare (match_operand:HI 0 "s_operand" "Q,S") |
9db1d521 | 696 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 697 | (clobber (match_scratch:HI 2 "=d,d"))] |
9db1d521 | 698 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 699 | "@ |
d40c829f UW |
700 | icm\t%2,3,%0 |
701 | icmy\t%2,3,%0" | |
d3632d41 | 702 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 703 | |
3af97654 UW |
704 | (define_insn "*tstqiCCT" |
705 | [(set (reg 33) | |
d3632d41 | 706 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 | 707 | (match_operand:QI 1 "const0_operand" ""))) |
d3632d41 | 708 | (set (match_operand:QI 2 "register_operand" "=d,d,0") |
3af97654 UW |
709 | (match_dup 0))] |
710 | "s390_match_ccmode(insn, CCTmode)" | |
711 | "@ | |
d40c829f UW |
712 | icm\t%2,1,%0 |
713 | icmy\t%2,1,%0 | |
714 | tml\t%0,255" | |
d3632d41 | 715 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 UW |
716 | |
717 | (define_insn "*tstqiCCT_cconly" | |
718 | [(set (reg 33) | |
d3632d41 | 719 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
720 | (match_operand:QI 1 "const0_operand" "")))] |
721 | "s390_match_ccmode(insn, CCTmode)" | |
722 | "@ | |
d40c829f UW |
723 | cli\t%0,0 |
724 | cliy\t%0,0 | |
725 | tml\t%0,255" | |
d3632d41 | 726 | [(set_attr "op_type" "SI,SIY,RI")]) |
3af97654 | 727 | |
07893d4f | 728 | (define_insn "*tstqi" |
9db1d521 | 729 | [(set (reg 33) |
d3632d41 | 730 | (compare (match_operand:QI 0 "s_operand" "Q,S") |
07893d4f | 731 | (match_operand:QI 1 "const0_operand" ""))) |
d3632d41 | 732 | (set (match_operand:QI 2 "register_operand" "=d,d") |
07893d4f UW |
733 | (match_dup 0))] |
734 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 735 | "@ |
d40c829f UW |
736 | icm\t%2,1,%0 |
737 | icmy\t%2,1,%0" | |
d3632d41 | 738 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 739 | |
07893d4f | 740 | (define_insn "*tstqi_cconly" |
9db1d521 | 741 | [(set (reg 33) |
d3632d41 | 742 | (compare (match_operand:QI 0 "s_operand" "Q,S") |
07893d4f | 743 | (match_operand:QI 1 "const0_operand" ""))) |
d3632d41 | 744 | (clobber (match_scratch:QI 2 "=d,d"))] |
07893d4f | 745 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 746 | "@ |
d40c829f UW |
747 | icm\t%2,1,%0 |
748 | icmy\t%2,1,%0" | |
d3632d41 UW |
749 | [(set_attr "op_type" "RS,RSY")]) |
750 | ||
9db1d521 | 751 | |
07893d4f | 752 | ; Compare (signed) instructions |
4023fb28 | 753 | |
07893d4f | 754 | (define_insn "*cmpdi_ccs_sign" |
4023fb28 | 755 | [(set (reg 33) |
07893d4f UW |
756 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
757 | (match_operand:DI 0 "register_operand" "d,d")))] | |
758 | "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" | |
4023fb28 | 759 | "@ |
d40c829f UW |
760 | cgfr\t%0,%1 |
761 | cgf\t%0,%1" | |
d3632d41 | 762 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 763 | |
07893d4f | 764 | (define_insn "*cmpdi_ccs" |
4023fb28 | 765 | [(set (reg 33) |
07893d4f UW |
766 | (compare (match_operand:DI 0 "register_operand" "d,d,d") |
767 | (match_operand:DI 1 "general_operand" "d,K,m")))] | |
768 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
769 | "@ | |
d40c829f UW |
770 | cgr\t%0,%1 |
771 | cghi\t%0,%c1 | |
772 | cg\t%0,%1" | |
d3632d41 | 773 | [(set_attr "op_type" "RRE,RI,RXY")]) |
c7453384 | 774 | |
07893d4f UW |
775 | (define_insn "*cmpsi_ccs_sign" |
776 | [(set (reg 33) | |
d3632d41 UW |
777 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")) |
778 | (match_operand:SI 0 "register_operand" "d,d")))] | |
07893d4f | 779 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 780 | "@ |
d40c829f UW |
781 | ch\t%0,%1 |
782 | chy\t%0,%1" | |
d3632d41 | 783 | [(set_attr "op_type" "RX,RXY")]) |
4023fb28 | 784 | |
07893d4f | 785 | (define_insn "*cmpsi_ccs" |
9db1d521 | 786 | [(set (reg 33) |
d3632d41 UW |
787 | (compare (match_operand:SI 0 "register_operand" "d,d,d,d") |
788 | (match_operand:SI 1 "general_operand" "d,K,R,T")))] | |
9db1d521 | 789 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 790 | "@ |
d40c829f UW |
791 | cr\t%0,%1 |
792 | chi\t%0,%c1 | |
793 | c\t%0,%1 | |
794 | cy\t%0,%1" | |
d3632d41 | 795 | [(set_attr "op_type" "RR,RI,RX,RXY")]) |
c7453384 | 796 | |
07893d4f UW |
797 | |
798 | ; Compare (unsigned) instructions | |
9db1d521 | 799 | |
07893d4f | 800 | (define_insn "*cmpdi_ccu_zero" |
9db1d521 | 801 | [(set (reg 33) |
07893d4f UW |
802 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
803 | (match_operand:DI 0 "register_operand" "d,d")))] | |
804 | "s390_match_ccmode(insn, CCURmode) && TARGET_64BIT" | |
805 | "@ | |
d40c829f UW |
806 | clgfr\t%0,%1 |
807 | clgf\t%0,%1" | |
d3632d41 | 808 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 809 | |
07893d4f | 810 | (define_insn "*cmpdi_ccu" |
9db1d521 | 811 | [(set (reg 33) |
07893d4f UW |
812 | (compare (match_operand:DI 0 "register_operand" "d,d") |
813 | (match_operand:DI 1 "general_operand" "d,m")))] | |
814 | "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT" | |
815 | "@ | |
d40c829f UW |
816 | clgr\t%0,%1 |
817 | clg\t%0,%1" | |
d3632d41 | 818 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 819 | |
07893d4f | 820 | (define_insn "*cmpsi_ccu" |
9db1d521 | 821 | [(set (reg 33) |
d3632d41 UW |
822 | (compare (match_operand:SI 0 "register_operand" "d,d,d") |
823 | (match_operand:SI 1 "general_operand" "d,R,T")))] | |
07893d4f UW |
824 | "s390_match_ccmode(insn, CCUmode)" |
825 | "@ | |
d40c829f UW |
826 | clr\t%0,%1 |
827 | cl\t%0,%1 | |
828 | cly\t%0,%1" | |
d3632d41 | 829 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 830 | |
07893d4f | 831 | (define_insn "*cmphi_ccu" |
9db1d521 | 832 | [(set (reg 33) |
d3632d41 UW |
833 | (compare (match_operand:HI 0 "register_operand" "d,d") |
834 | (match_operand:HI 1 "s_imm_operand" "Q,S")))] | |
9db1d521 | 835 | "s390_match_ccmode(insn, CCUmode)" |
d3632d41 | 836 | "@ |
d40c829f UW |
837 | clm\t%0,3,%1 |
838 | clmy\t%0,3,%1" | |
d3632d41 | 839 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 HP |
840 | |
841 | (define_insn "*cmpqi_ccu" | |
842 | [(set (reg 33) | |
d3632d41 UW |
843 | (compare (match_operand:QI 0 "register_operand" "d,d") |
844 | (match_operand:QI 1 "s_imm_operand" "Q,S")))] | |
9db1d521 | 845 | "s390_match_ccmode(insn, CCUmode)" |
d3632d41 | 846 | "@ |
d40c829f UW |
847 | clm\t%0,1,%1 |
848 | clmy\t%0,1,%1" | |
d3632d41 | 849 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 850 | |
07893d4f | 851 | (define_insn "*cli" |
9db1d521 | 852 | [(set (reg 33) |
d3632d41 UW |
853 | (compare (match_operand:QI 0 "memory_operand" "Q,S") |
854 | (match_operand:QI 1 "immediate_operand" "n,n")))] | |
07893d4f | 855 | "s390_match_ccmode (insn, CCUmode)" |
d3632d41 | 856 | "@ |
d40c829f UW |
857 | cli\t%0,%b1 |
858 | cliy\t%0,%b1" | |
d3632d41 | 859 | [(set_attr "op_type" "SI,SIY")]) |
9db1d521 | 860 | |
07893d4f UW |
861 | (define_insn "*cmpdi_ccu_mem" |
862 | [(set (reg 33) | |
ccfc6cc8 UW |
863 | (compare (match_operand:DI 0 "s_operand" "Q") |
864 | (match_operand:DI 1 "s_imm_operand" "Q")))] | |
07893d4f | 865 | "s390_match_ccmode(insn, CCUmode)" |
d40c829f | 866 | "clc\t%O0(8,%R0),%1" |
077dab3b | 867 | [(set_attr "op_type" "SS")]) |
07893d4f UW |
868 | |
869 | (define_insn "*cmpsi_ccu_mem" | |
870 | [(set (reg 33) | |
ccfc6cc8 UW |
871 | (compare (match_operand:SI 0 "s_operand" "Q") |
872 | (match_operand:SI 1 "s_imm_operand" "Q")))] | |
07893d4f | 873 | "s390_match_ccmode(insn, CCUmode)" |
d40c829f | 874 | "clc\t%O0(4,%R0),%1" |
077dab3b | 875 | [(set_attr "op_type" "SS")]) |
07893d4f UW |
876 | |
877 | (define_insn "*cmphi_ccu_mem" | |
878 | [(set (reg 33) | |
ccfc6cc8 UW |
879 | (compare (match_operand:HI 0 "s_operand" "Q") |
880 | (match_operand:HI 1 "s_imm_operand" "Q")))] | |
07893d4f | 881 | "s390_match_ccmode(insn, CCUmode)" |
d40c829f | 882 | "clc\t%O0(2,%R0),%1" |
077dab3b | 883 | [(set_attr "op_type" "SS")]) |
07893d4f | 884 | |
9db1d521 HP |
885 | (define_insn "*cmpqi_ccu_mem" |
886 | [(set (reg 33) | |
ccfc6cc8 UW |
887 | (compare (match_operand:QI 0 "s_operand" "Q") |
888 | (match_operand:QI 1 "s_imm_operand" "Q")))] | |
9db1d521 | 889 | "s390_match_ccmode(insn, CCUmode)" |
d40c829f | 890 | "clc\t%O0(1,%R0),%1" |
077dab3b | 891 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
892 | |
893 | ||
894 | ; DF instructions | |
895 | ||
896 | (define_insn "*cmpdf_ccs_0" | |
897 | [(set (reg 33) | |
898 | (compare (match_operand:DF 0 "register_operand" "f") | |
899 | (match_operand:DF 1 "const0_operand" "")))] | |
900 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 901 | "ltdbr\t%0,%0" |
077dab3b HP |
902 | [(set_attr "op_type" "RRE") |
903 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
904 | |
905 | (define_insn "*cmpdf_ccs_0_ibm" | |
906 | [(set (reg 33) | |
907 | (compare (match_operand:DF 0 "register_operand" "f") | |
908 | (match_operand:DF 1 "const0_operand" "")))] | |
909 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 910 | "ltdr\t%0,%0" |
077dab3b HP |
911 | [(set_attr "op_type" "RR") |
912 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
913 | |
914 | (define_insn "*cmpdf_ccs" | |
915 | [(set (reg 33) | |
916 | (compare (match_operand:DF 0 "register_operand" "f,f") | |
d3632d41 | 917 | (match_operand:DF 1 "general_operand" "f,R")))] |
9db1d521 HP |
918 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
919 | "@ | |
d40c829f UW |
920 | cdbr\t%0,%1 |
921 | cdb\t%0,%1" | |
ce50cae8 | 922 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 923 | (set_attr "type" "fsimpd")]) |
9db1d521 HP |
924 | |
925 | (define_insn "*cmpdf_ccs_ibm" | |
926 | [(set (reg 33) | |
927 | (compare (match_operand:DF 0 "register_operand" "f,f") | |
d3632d41 | 928 | (match_operand:DF 1 "general_operand" "f,R")))] |
9db1d521 HP |
929 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
930 | "@ | |
d40c829f UW |
931 | cdr\t%0,%1 |
932 | cd\t%0,%1" | |
9db1d521 | 933 | [(set_attr "op_type" "RR,RX") |
077dab3b | 934 | (set_attr "type" "fsimpd")]) |
9db1d521 HP |
935 | |
936 | ||
937 | ; SF instructions | |
938 | ||
939 | (define_insn "*cmpsf_ccs_0" | |
940 | [(set (reg 33) | |
941 | (compare (match_operand:SF 0 "register_operand" "f") | |
942 | (match_operand:SF 1 "const0_operand" "")))] | |
943 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 944 | "ltebr\t%0,%0" |
077dab3b HP |
945 | [(set_attr "op_type" "RRE") |
946 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
947 | |
948 | (define_insn "*cmpsf_ccs_0_ibm" | |
949 | [(set (reg 33) | |
950 | (compare (match_operand:SF 0 "register_operand" "f") | |
951 | (match_operand:SF 1 "const0_operand" "")))] | |
952 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 953 | "lter\t%0,%0" |
077dab3b HP |
954 | [(set_attr "op_type" "RR") |
955 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
956 | |
957 | (define_insn "*cmpsf_ccs" | |
958 | [(set (reg 33) | |
959 | (compare (match_operand:SF 0 "register_operand" "f,f") | |
d3632d41 | 960 | (match_operand:SF 1 "general_operand" "f,R")))] |
9db1d521 HP |
961 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
962 | "@ | |
d40c829f UW |
963 | cebr\t%0,%1 |
964 | ceb\t%0,%1" | |
077dab3b HP |
965 | [(set_attr "op_type" "RRE,RXE") |
966 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
967 | |
968 | (define_insn "*cmpsf_ccs" | |
969 | [(set (reg 33) | |
970 | (compare (match_operand:SF 0 "register_operand" "f,f") | |
d3632d41 | 971 | (match_operand:SF 1 "general_operand" "f,R")))] |
9db1d521 HP |
972 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
973 | "@ | |
d40c829f UW |
974 | cer\t%0,%1 |
975 | ce\t%0,%1" | |
077dab3b HP |
976 | [(set_attr "op_type" "RR,RX") |
977 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
978 | |
979 | ||
980 | ;; | |
981 | ;;- Move instructions. | |
982 | ;; | |
983 | ||
984 | ; | |
985 | ; movti instruction pattern(s). | |
986 | ; | |
987 | ||
988 | (define_insn "movti" | |
d3632d41 UW |
989 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q") |
990 | (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))] | |
9db1d521 | 991 | "TARGET_64BIT" |
4023fb28 | 992 | "@ |
d40c829f UW |
993 | lmg\t%0,%N0,%1 |
994 | stmg\t%1,%N1,%0 | |
4023fb28 | 995 | # |
9b7c75b9 | 996 | # |
d40c829f | 997 | mvc\t%O0(16,%R0),%1" |
d3632d41 | 998 | [(set_attr "op_type" "RSY,RSY,NN,NN,SS") |
fe03d631 | 999 | (set_attr "type" "lm,stm,*,*,cs")]) |
4023fb28 UW |
1000 | |
1001 | (define_split | |
1002 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1003 | (match_operand:TI 1 "general_operand" ""))] | |
1004 | "TARGET_64BIT && reload_completed | |
dc65c307 | 1005 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1006 | [(set (match_dup 2) (match_dup 4)) |
1007 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1008 | { |
dc65c307 UW |
1009 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1010 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1011 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1012 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1013 | }) | |
1014 | ||
1015 | (define_split | |
1016 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1017 | (match_operand:TI 1 "general_operand" ""))] | |
1018 | "TARGET_64BIT && reload_completed | |
1019 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" | |
1020 | [(set (match_dup 2) (match_dup 4)) | |
1021 | (set (match_dup 3) (match_dup 5))] | |
1022 | { | |
1023 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1024 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1025 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1026 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1027 | }) | |
4023fb28 UW |
1028 | |
1029 | (define_split | |
1030 | [(set (match_operand:TI 0 "register_operand" "") | |
1031 | (match_operand:TI 1 "memory_operand" ""))] | |
1032 | "TARGET_64BIT && reload_completed | |
1033 | && !s_operand (operands[1], VOIDmode)" | |
a41c6c53 | 1034 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1035 | { |
1036 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
1037 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1038 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1039 | }) |
1040 | ||
1041 | (define_expand "reload_outti" | |
1042 | [(parallel [(match_operand:TI 0 "memory_operand" "") | |
1043 | (match_operand:TI 1 "register_operand" "d") | |
1044 | (match_operand:DI 2 "register_operand" "=&a")])] | |
1045 | "TARGET_64BIT" | |
1046 | { | |
1047 | s390_load_address (operands[2], XEXP (operands[0], 0)); | |
1048 | operands[0] = replace_equiv_address (operands[0], operands[2]); | |
1049 | emit_move_insn (operands[0], operands[1]); | |
1050 | DONE; | |
1051 | }) | |
9db1d521 HP |
1052 | |
1053 | ; | |
1054 | ; movdi instruction pattern(s). | |
1055 | ; | |
1056 | ||
9db1d521 HP |
1057 | (define_expand "movdi" |
1058 | [(set (match_operand:DI 0 "general_operand" "") | |
1059 | (match_operand:DI 1 "general_operand" ""))] | |
1060 | "" | |
9db1d521 | 1061 | { |
fd3cd001 UW |
1062 | /* Handle symbolic constants. */ |
1063 | if (TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
1064 | emit_symbolic_move (operands); | |
4023fb28 UW |
1065 | |
1066 | /* During and after reload, we need to force constants | |
1067 | to the literal pool ourselves, if necessary. */ | |
1068 | if ((reload_in_progress || reload_completed) | |
c7453384 | 1069 | && CONSTANT_P (operands[1]) |
4023fb28 | 1070 | && (!legitimate_reload_constant_p (operands[1]) |
8e509cf9 | 1071 | || FP_REG_P (operands[0]))) |
4023fb28 | 1072 | operands[1] = force_const_mem (DImode, operands[1]); |
10bbf137 | 1073 | }) |
9db1d521 | 1074 | |
4023fb28 UW |
1075 | (define_insn "*movdi_larl" |
1076 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1077 | (match_operand:DI 1 "larl_operand" "X"))] | |
1078 | "TARGET_64BIT | |
8e509cf9 | 1079 | && !FP_REG_P (operands[0])" |
d40c829f | 1080 | "larl\t%0,%1" |
4023fb28 | 1081 | [(set_attr "op_type" "RIL") |
077dab3b | 1082 | (set_attr "type" "larl")]) |
4023fb28 | 1083 | |
9db1d521 | 1084 | (define_insn "*movdi_64" |
f19a9af7 AK |
1085 | [(set (match_operand:DI 0 "nonimmediate_operand" |
1086 | "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,?Q") | |
1087 | (match_operand:DI 1 "general_operand" | |
1088 | "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,?Q"))] | |
9db1d521 HP |
1089 | "TARGET_64BIT" |
1090 | "@ | |
f19a9af7 AK |
1091 | lghi\t%0,%h1 |
1092 | llihh\t%0,%i1 | |
1093 | llihl\t%0,%i1 | |
1094 | llilh\t%0,%i1 | |
1095 | llill\t%0,%i1 | |
1096 | lay\t%0,%a1 | |
d40c829f UW |
1097 | lgr\t%0,%1 |
1098 | lg\t%0,%1 | |
1099 | stg\t%1,%0 | |
1100 | ldr\t%0,%1 | |
1101 | ld\t%0,%1 | |
1102 | ldy\t%0,%1 | |
1103 | std\t%1,%0 | |
1104 | stdy\t%1,%0 | |
1105 | mvc\t%O0(8,%R0),%1" | |
f19a9af7 AK |
1106 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,RR,RX,RXY,RX,RXY,SS") |
1107 | (set_attr "type" "*,*,*,*,*,la,lr,load,store,floadd,floadd,floadd, | |
1108 | fstored,fstored,cs")]) | |
9db1d521 HP |
1109 | |
1110 | (define_insn "*movdi_31" | |
d3632d41 UW |
1111 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q") |
1112 | (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))] | |
9db1d521 | 1113 | "!TARGET_64BIT" |
4023fb28 | 1114 | "@ |
d40c829f UW |
1115 | lm\t%0,%N0,%1 |
1116 | stm\t%1,%N1,%0 | |
4023fb28 UW |
1117 | # |
1118 | # | |
d40c829f UW |
1119 | ldr\t%0,%1 |
1120 | ld\t%0,%1 | |
1121 | ldy\t%0,%1 | |
1122 | std\t%1,%0 | |
1123 | stdy\t%1,%0 | |
1124 | mvc\t%O0(8,%R0),%1" | |
d3632d41 UW |
1125 | [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RXY,RX,RXY,SS") |
1126 | (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,cs")]) | |
4023fb28 UW |
1127 | |
1128 | (define_split | |
1129 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1130 | (match_operand:DI 1 "general_operand" ""))] | |
1131 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 1132 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1133 | [(set (match_dup 2) (match_dup 4)) |
1134 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1135 | { |
dc65c307 UW |
1136 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1137 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1138 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1139 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1140 | }) | |
1141 | ||
1142 | (define_split | |
1143 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1144 | (match_operand:DI 1 "general_operand" ""))] | |
1145 | "!TARGET_64BIT && reload_completed | |
1146 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" | |
1147 | [(set (match_dup 2) (match_dup 4)) | |
1148 | (set (match_dup 3) (match_dup 5))] | |
1149 | { | |
1150 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1151 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1152 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1153 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1154 | }) | |
9db1d521 | 1155 | |
4023fb28 UW |
1156 | (define_split |
1157 | [(set (match_operand:DI 0 "register_operand" "") | |
1158 | (match_operand:DI 1 "memory_operand" ""))] | |
1159 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 1160 | && !FP_REG_P (operands[0]) |
4023fb28 | 1161 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1162 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1163 | { |
1164 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1165 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1166 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1167 | }) |
1168 | ||
1169 | (define_expand "reload_outdi" | |
1170 | [(parallel [(match_operand:DI 0 "memory_operand" "") | |
1171 | (match_operand:DI 1 "register_operand" "d") | |
1172 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1173 | "!TARGET_64BIT" | |
1174 | { | |
1175 | s390_load_address (operands[2], XEXP (operands[0], 0)); | |
1176 | operands[0] = replace_equiv_address (operands[0], operands[2]); | |
1177 | emit_move_insn (operands[0], operands[1]); | |
1178 | DONE; | |
1179 | }) | |
9db1d521 | 1180 | |
84817c5d UW |
1181 | (define_peephole2 |
1182 | [(set (match_operand:DI 0 "register_operand" "") | |
1183 | (mem:DI (match_operand 1 "address_operand" "")))] | |
1184 | "TARGET_64BIT | |
1185 | && !FP_REG_P (operands[0]) | |
1186 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1187 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1188 | && get_pool_mode (operands[1]) == DImode | |
1189 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1190 | [(set (match_dup 0) (match_dup 2))] | |
1191 | "operands[2] = get_pool_constant (operands[1]);") | |
1192 | ||
7bdff56f UW |
1193 | (define_insn "*la_64" |
1194 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
1195 | (match_operand:QI 1 "address_operand" "U,W"))] | |
1196 | "TARGET_64BIT" | |
1197 | "@ | |
1198 | la\t%0,%a1 | |
1199 | lay\t%0,%a1" | |
1200 | [(set_attr "op_type" "RX,RXY") | |
1201 | (set_attr "type" "la")]) | |
1202 | ||
1203 | (define_peephole2 | |
1204 | [(parallel | |
1205 | [(set (match_operand:DI 0 "register_operand" "") | |
1206 | (match_operand:QI 1 "address_operand" "")) | |
1207 | (clobber (reg:CC 33))])] | |
1208 | "TARGET_64BIT | |
1209 | && strict_memory_address_p (VOIDmode, operands[1]) | |
1210 | && preferred_la_operand_p (operands[1])" | |
1211 | [(set (match_dup 0) (match_dup 1))] | |
1212 | "") | |
1213 | ||
1214 | (define_peephole2 | |
1215 | [(set (match_operand:DI 0 "register_operand" "") | |
1216 | (match_operand:DI 1 "register_operand" "")) | |
1217 | (parallel | |
1218 | [(set (match_dup 0) | |
1219 | (plus:DI (match_dup 0) | |
1220 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
1221 | (clobber (reg:CC 33))])] | |
1222 | "TARGET_64BIT | |
1223 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
1224 | && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (DImode, operands[1], operands[2])) | |
1225 | && preferred_la_operand_p (gen_rtx_PLUS (DImode, operands[1], operands[2]))" | |
1226 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] | |
1227 | "") | |
1228 | ||
1229 | (define_expand "reload_indi" | |
1230 | [(parallel [(match_operand:DI 0 "register_operand" "=a") | |
1231 | (match_operand:DI 1 "s390_plus_operand" "") | |
1232 | (match_operand:DI 2 "register_operand" "=&a")])] | |
1233 | "TARGET_64BIT" | |
1234 | { | |
1235 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1236 | DONE; | |
1237 | }) | |
1238 | ||
9db1d521 HP |
1239 | ; |
1240 | ; movsi instruction pattern(s). | |
1241 | ; | |
1242 | ||
9db1d521 HP |
1243 | (define_expand "movsi" |
1244 | [(set (match_operand:SI 0 "general_operand" "") | |
1245 | (match_operand:SI 1 "general_operand" ""))] | |
1246 | "" | |
9db1d521 | 1247 | { |
fd3cd001 UW |
1248 | /* Handle symbolic constants. */ |
1249 | if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
1250 | emit_symbolic_move (operands); | |
ba956982 | 1251 | |
c7453384 EC |
1252 | /* expr.c tries to load an effective address using |
1253 | force_reg. This fails because we don't have a | |
ba956982 UW |
1254 | generic load_address pattern. Convert the move |
1255 | to a proper arithmetic operation instead, unless | |
1256 | it is guaranteed to be OK. */ | |
1257 | if (GET_CODE (operands[1]) == PLUS | |
1258 | && !legitimate_la_operand_p (operands[1])) | |
1259 | { | |
1260 | operands[1] = force_operand (operands[1], operands[0]); | |
1261 | if (operands[1] == operands[0]) | |
1262 | DONE; | |
1263 | } | |
4023fb28 UW |
1264 | |
1265 | /* During and after reload, we need to force constants | |
1266 | to the literal pool ourselves, if necessary. */ | |
1267 | if ((reload_in_progress || reload_completed) | |
c7453384 | 1268 | && CONSTANT_P (operands[1]) |
4023fb28 | 1269 | && (!legitimate_reload_constant_p (operands[1]) |
8e509cf9 | 1270 | || FP_REG_P (operands[0]))) |
4023fb28 | 1271 | operands[1] = force_const_mem (SImode, operands[1]); |
10bbf137 | 1272 | }) |
9db1d521 | 1273 | |
9e8327e3 UW |
1274 | (define_insn "*movsi_larl" |
1275 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1276 | (match_operand:SI 1 "larl_operand" "X"))] | |
1277 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1278 | && !FP_REG_P (operands[0])" | |
1279 | "larl\t%0,%1" | |
1280 | [(set_attr "op_type" "RIL") | |
1281 | (set_attr "type" "larl")]) | |
1282 | ||
f19a9af7 AK |
1283 | (define_insn "*movsi_zarch" |
1284 | [(set (match_operand:SI 0 "nonimmediate_operand" | |
1285 | "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,?Q") | |
1286 | (match_operand:SI 1 "general_operand" | |
1287 | "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,?Q"))] | |
1288 | "TARGET_ZARCH" | |
9db1d521 | 1289 | "@ |
f19a9af7 AK |
1290 | lhi\t%0,%h1 |
1291 | llilh\t%0,%i1 | |
1292 | llill\t%0,%i1 | |
1293 | lay\t%0,%a1 | |
d40c829f UW |
1294 | lr\t%0,%1 |
1295 | l\t%0,%1 | |
1296 | ly\t%0,%1 | |
1297 | st\t%1,%0 | |
1298 | sty\t%1,%0 | |
1299 | ler\t%0,%1 | |
1300 | le\t%0,%1 | |
1301 | ley\t%0,%1 | |
1302 | ste\t%1,%0 | |
1303 | stey\t%1,%0 | |
1304 | mvc\t%O0(4,%R0),%1" | |
f19a9af7 AK |
1305 | [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") |
1306 | (set_attr "type" "*,*,*,la,lr,load,load,store,store,floads,floads,floads,fstores,fstores,cs")]) | |
1307 | ||
1308 | (define_insn "*movsi_esa" | |
1309 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,?Q") | |
1310 | (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,?Q"))] | |
1311 | "!TARGET_ZARCH" | |
1312 | "@ | |
1313 | lhi\t%0,%h1 | |
1314 | lr\t%0,%1 | |
1315 | l\t%0,%1 | |
1316 | st\t%1,%0 | |
1317 | ler\t%0,%1 | |
1318 | le\t%0,%1 | |
1319 | ste\t%1,%0 | |
1320 | mvc\t%O0(4,%R0),%1" | |
1321 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,SS") | |
1322 | (set_attr "type" "*,lr,load,store,floads,floads,fstores,cs")]) | |
9db1d521 | 1323 | |
84817c5d UW |
1324 | (define_peephole2 |
1325 | [(set (match_operand:SI 0 "register_operand" "") | |
1326 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1327 | "!FP_REG_P (operands[0]) | |
1328 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1329 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1330 | && get_pool_mode (operands[1]) == SImode | |
1331 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1332 | [(set (match_dup 0) (match_dup 2))] | |
1333 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 1334 | |
7bdff56f UW |
1335 | (define_insn "*la_31" |
1336 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1337 | (match_operand:QI 1 "address_operand" "U,W"))] | |
1338 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" | |
1339 | "@ | |
1340 | la\t%0,%a1 | |
1341 | lay\t%0,%a1" | |
1342 | [(set_attr "op_type" "RX,RXY") | |
1343 | (set_attr "type" "la")]) | |
1344 | ||
1345 | (define_peephole2 | |
1346 | [(parallel | |
1347 | [(set (match_operand:SI 0 "register_operand" "") | |
1348 | (match_operand:QI 1 "address_operand" "")) | |
1349 | (clobber (reg:CC 33))])] | |
1350 | "!TARGET_64BIT | |
1351 | && strict_memory_address_p (VOIDmode, operands[1]) | |
1352 | && preferred_la_operand_p (operands[1])" | |
1353 | [(set (match_dup 0) (match_dup 1))] | |
1354 | "") | |
1355 | ||
1356 | (define_peephole2 | |
1357 | [(set (match_operand:SI 0 "register_operand" "") | |
1358 | (match_operand:SI 1 "register_operand" "")) | |
1359 | (parallel | |
1360 | [(set (match_dup 0) | |
1361 | (plus:SI (match_dup 0) | |
1362 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
1363 | (clobber (reg:CC 33))])] | |
1364 | "!TARGET_64BIT | |
1365 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
1366 | && strict_memory_address_p (VOIDmode, gen_rtx_PLUS (SImode, operands[1], operands[2])) | |
1367 | && preferred_la_operand_p (gen_rtx_PLUS (SImode, operands[1], operands[2]))" | |
1368 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] | |
1369 | "") | |
1370 | ||
1371 | (define_insn "*la_31_and" | |
1372 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1373 | (and:SI (match_operand:QI 1 "address_operand" "U,W") | |
1374 | (const_int 2147483647)))] | |
1375 | "!TARGET_64BIT" | |
1376 | "@ | |
1377 | la\t%0,%a1 | |
1378 | lay\t%0,%a1" | |
1379 | [(set_attr "op_type" "RX,RXY") | |
1380 | (set_attr "type" "la")]) | |
1381 | ||
1382 | (define_insn_and_split "*la_31_and_cc" | |
1383 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1384 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
1385 | (const_int 2147483647))) | |
1386 | (clobber (reg:CC 33))] | |
1387 | "!TARGET_64BIT" | |
1388 | "#" | |
1389 | "&& reload_completed" | |
1390 | [(set (match_dup 0) | |
1391 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
1392 | "" | |
1393 | [(set_attr "op_type" "RX") | |
1394 | (set_attr "type" "la")]) | |
1395 | ||
1396 | (define_insn "force_la_31" | |
1397 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1398 | (match_operand:QI 1 "address_operand" "U,W")) | |
1399 | (use (const_int 0))] | |
1400 | "!TARGET_64BIT" | |
1401 | "@ | |
1402 | la\t%0,%a1 | |
1403 | lay\t%0,%a1" | |
1404 | [(set_attr "op_type" "RX") | |
1405 | (set_attr "type" "la")]) | |
1406 | ||
1407 | (define_expand "reload_insi" | |
1408 | [(parallel [(match_operand:SI 0 "register_operand" "=a") | |
1409 | (match_operand:SI 1 "s390_plus_operand" "") | |
1410 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1411 | "!TARGET_64BIT" | |
1412 | { | |
1413 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1414 | DONE; | |
1415 | }) | |
1416 | ||
9db1d521 HP |
1417 | ; |
1418 | ; movhi instruction pattern(s). | |
1419 | ; | |
1420 | ||
02ed3c5e UW |
1421 | (define_expand "movhi" |
1422 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
1423 | (match_operand:HI 1 "general_operand" ""))] | |
1424 | "" | |
1425 | { | |
1426 | /* Make it explicit that loading a register from memory | |
1427 | always sign-extends (at least) to SImode. */ | |
1428 | if (optimize && !no_new_pseudos | |
1429 | && register_operand (operands[0], VOIDmode) | |
d71a8c3b UW |
1430 | && GET_CODE (operands[1]) == MEM |
1431 | && GET_CODE (XEXP (operands[1], 0)) != ADDRESSOF) | |
02ed3c5e UW |
1432 | { |
1433 | rtx tmp = gen_reg_rtx (SImode); | |
1434 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
1435 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); | |
1436 | operands[1] = gen_lowpart (HImode, tmp); | |
1437 | } | |
1438 | }) | |
1439 | ||
1440 | (define_insn "*movhi" | |
d3632d41 UW |
1441 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q") |
1442 | (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))] | |
9db1d521 HP |
1443 | "" |
1444 | "@ | |
d40c829f UW |
1445 | lr\t%0,%1 |
1446 | lhi\t%0,%h1 | |
1447 | lh\t%0,%1 | |
1448 | lhy\t%0,%1 | |
1449 | sth\t%1,%0 | |
1450 | sthy\t%1,%0 | |
1451 | mvc\t%O0(2,%R0),%1" | |
d3632d41 UW |
1452 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS") |
1453 | (set_attr "type" "lr,*,*,*,store,store,cs")]) | |
9db1d521 | 1454 | |
84817c5d UW |
1455 | (define_peephole2 |
1456 | [(set (match_operand:HI 0 "register_operand" "") | |
1457 | (mem:HI (match_operand 1 "address_operand" "")))] | |
1458 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1459 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1460 | && get_pool_mode (operands[1]) == HImode | |
1461 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1462 | [(set (match_dup 0) (match_dup 2))] | |
1463 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1464 | |
9db1d521 HP |
1465 | ; |
1466 | ; movqi instruction pattern(s). | |
1467 | ; | |
1468 | ||
02ed3c5e UW |
1469 | (define_expand "movqi" |
1470 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1471 | (match_operand:QI 1 "general_operand" ""))] | |
1472 | "" | |
1473 | { | |
c19ec8f9 | 1474 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 1475 | is just as fast as a QImode load. */ |
c19ec8f9 | 1476 | if (TARGET_ZARCH && optimize && !no_new_pseudos |
02ed3c5e | 1477 | && register_operand (operands[0], VOIDmode) |
d71a8c3b UW |
1478 | && GET_CODE (operands[1]) == MEM |
1479 | && GET_CODE (XEXP (operands[1], 0)) != ADDRESSOF) | |
02ed3c5e | 1480 | { |
c19ec8f9 UW |
1481 | rtx tmp = gen_reg_rtx (word_mode); |
1482 | rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]); | |
02ed3c5e UW |
1483 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); |
1484 | operands[1] = gen_lowpart (QImode, tmp); | |
1485 | } | |
1486 | }) | |
4023fb28 | 1487 | |
02ed3c5e | 1488 | (define_insn "*movqi" |
d3632d41 UW |
1489 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") |
1490 | (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))] | |
9db1d521 HP |
1491 | "" |
1492 | "@ | |
d40c829f UW |
1493 | lr\t%0,%1 |
1494 | lhi\t%0,%b1 | |
1495 | ic\t%0,%1 | |
1496 | icy\t%0,%1 | |
1497 | stc\t%1,%0 | |
1498 | stcy\t%1,%0 | |
1499 | mvi\t%0,%b1 | |
1500 | mviy\t%0,%b1 | |
1501 | mvc\t%O0(1,%R0),%1" | |
d3632d41 UW |
1502 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") |
1503 | (set_attr "type" "lr,*,*,*,store,store,store,store,cs")]) | |
9db1d521 | 1504 | |
84817c5d UW |
1505 | (define_peephole2 |
1506 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1507 | (mem:QI (match_operand 1 "address_operand" "")))] | |
1508 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1509 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1510 | && get_pool_mode (operands[1]) == QImode | |
1511 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1512 | [(set (match_dup 0) (match_dup 2))] | |
1513 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1514 | |
9db1d521 | 1515 | ; |
05b9aaaa | 1516 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
1517 | ; |
1518 | ||
1519 | (define_insn "*movstrictqi" | |
d3632d41 UW |
1520 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
1521 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 1522 | "" |
d3632d41 | 1523 | "@ |
d40c829f UW |
1524 | ic\t%0,%1 |
1525 | icy\t%0,%1" | |
d3632d41 | 1526 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 HP |
1527 | |
1528 | ; | |
1529 | ; movstricthi instruction pattern(s). | |
1530 | ; | |
1531 | ||
1532 | (define_insn "*movstricthi" | |
d3632d41 UW |
1533 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
1534 | (match_operand:HI 1 "s_imm_operand" "Q,S")) | |
9db1d521 HP |
1535 | (clobber (reg:CC 33))] |
1536 | "" | |
d3632d41 | 1537 | "@ |
d40c829f UW |
1538 | icm\t%0,3,%1 |
1539 | icmy\t%0,3,%1" | |
d3632d41 | 1540 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 HP |
1541 | |
1542 | ; | |
1543 | ; movstrictsi instruction pattern(s). | |
1544 | ; | |
1545 | ||
05b9aaaa | 1546 | (define_insn "movstrictsi" |
d3632d41 UW |
1547 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d")) |
1548 | (match_operand:SI 1 "general_operand" "d,R,T"))] | |
9db1d521 HP |
1549 | "TARGET_64BIT" |
1550 | "@ | |
d40c829f UW |
1551 | lr\t%0,%1 |
1552 | l\t%0,%1 | |
1553 | ly\t%0,%1" | |
d3632d41 UW |
1554 | [(set_attr "op_type" "RR,RX,RXY") |
1555 | (set_attr "type" "lr,load,load")]) | |
9db1d521 HP |
1556 | |
1557 | ; | |
1558 | ; movdf instruction pattern(s). | |
1559 | ; | |
1560 | ||
1561 | (define_expand "movdf" | |
1562 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1563 | (match_operand:DF 1 "general_operand" ""))] | |
1564 | "" | |
9db1d521 | 1565 | { |
4023fb28 UW |
1566 | /* During and after reload, we need to force constants |
1567 | to the literal pool ourselves, if necessary. */ | |
1568 | if ((reload_in_progress || reload_completed) | |
1569 | && CONSTANT_P (operands[1])) | |
1570 | operands[1] = force_const_mem (DFmode, operands[1]); | |
10bbf137 | 1571 | }) |
9db1d521 HP |
1572 | |
1573 | (define_insn "*movdf_64" | |
d3632d41 UW |
1574 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q") |
1575 | (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))] | |
4023fb28 | 1576 | "TARGET_64BIT" |
9db1d521 | 1577 | "@ |
d40c829f UW |
1578 | ldr\t%0,%1 |
1579 | ld\t%0,%1 | |
1580 | ldy\t%0,%1 | |
1581 | std\t%1,%0 | |
1582 | stdy\t%1,%0 | |
1583 | lgr\t%0,%1 | |
1584 | lg\t%0,%1 | |
1585 | stg\t%1,%0 | |
1586 | mvc\t%O0(8,%R0),%1" | |
d3632d41 UW |
1587 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") |
1588 | (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,cs")]) | |
9db1d521 HP |
1589 | |
1590 | (define_insn "*movdf_31" | |
d3632d41 UW |
1591 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q") |
1592 | (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))] | |
4023fb28 | 1593 | "!TARGET_64BIT" |
9db1d521 | 1594 | "@ |
d40c829f UW |
1595 | ldr\t%0,%1 |
1596 | ld\t%0,%1 | |
1597 | ldy\t%0,%1 | |
1598 | std\t%1,%0 | |
1599 | stdy\t%1,%0 | |
1600 | lm\t%0,%N0,%1 | |
1601 | stm\t%1,%N1,%0 | |
4023fb28 | 1602 | # |
9b7c75b9 | 1603 | # |
d40c829f | 1604 | mvc\t%O0(8,%R0),%1" |
d3632d41 UW |
1605 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,NN,NN,SS") |
1606 | (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,cs")]) | |
4023fb28 UW |
1607 | |
1608 | (define_split | |
1609 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1610 | (match_operand:DF 1 "general_operand" ""))] | |
1611 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 1612 | && s390_split_ok_p (operands[0], operands[1], DFmode, 0)" |
4023fb28 UW |
1613 | [(set (match_dup 2) (match_dup 4)) |
1614 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1615 | { |
dc65c307 UW |
1616 | operands[2] = operand_subword (operands[0], 0, 0, DFmode); |
1617 | operands[3] = operand_subword (operands[0], 1, 0, DFmode); | |
1618 | operands[4] = operand_subword (operands[1], 0, 0, DFmode); | |
1619 | operands[5] = operand_subword (operands[1], 1, 0, DFmode); | |
1620 | }) | |
1621 | ||
1622 | (define_split | |
1623 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1624 | (match_operand:DF 1 "general_operand" ""))] | |
1625 | "!TARGET_64BIT && reload_completed | |
1626 | && s390_split_ok_p (operands[0], operands[1], DFmode, 1)" | |
1627 | [(set (match_dup 2) (match_dup 4)) | |
1628 | (set (match_dup 3) (match_dup 5))] | |
1629 | { | |
1630 | operands[2] = operand_subword (operands[0], 1, 0, DFmode); | |
1631 | operands[3] = operand_subword (operands[0], 0, 0, DFmode); | |
1632 | operands[4] = operand_subword (operands[1], 1, 0, DFmode); | |
1633 | operands[5] = operand_subword (operands[1], 0, 0, DFmode); | |
1634 | }) | |
9db1d521 | 1635 | |
4023fb28 UW |
1636 | (define_split |
1637 | [(set (match_operand:DF 0 "register_operand" "") | |
1638 | (match_operand:DF 1 "memory_operand" ""))] | |
1639 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 1640 | && !FP_REG_P (operands[0]) |
4023fb28 | 1641 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1642 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1643 | { |
1644 | rtx addr = operand_subword (operands[0], 1, 0, DFmode); | |
1645 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1646 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1647 | }) |
1648 | ||
1649 | (define_expand "reload_outdf" | |
1650 | [(parallel [(match_operand:DF 0 "memory_operand" "") | |
1651 | (match_operand:DF 1 "register_operand" "d") | |
1652 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1653 | "!TARGET_64BIT" | |
1654 | { | |
1655 | s390_load_address (operands[2], XEXP (operands[0], 0)); | |
1656 | operands[0] = replace_equiv_address (operands[0], operands[2]); | |
1657 | emit_move_insn (operands[0], operands[1]); | |
1658 | DONE; | |
1659 | }) | |
9db1d521 HP |
1660 | |
1661 | ; | |
1662 | ; movsf instruction pattern(s). | |
1663 | ; | |
1664 | ||
1665 | (define_expand "movsf" | |
1666 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
1667 | (match_operand:SF 1 "general_operand" ""))] | |
1668 | "" | |
9db1d521 | 1669 | { |
4023fb28 UW |
1670 | /* During and after reload, we need to force constants |
1671 | to the literal pool ourselves, if necessary. */ | |
1672 | if ((reload_in_progress || reload_completed) | |
1673 | && CONSTANT_P (operands[1])) | |
1674 | operands[1] = force_const_mem (SFmode, operands[1]); | |
10bbf137 | 1675 | }) |
9db1d521 | 1676 | |
4023fb28 | 1677 | (define_insn "*movsf" |
d3632d41 UW |
1678 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q") |
1679 | (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))] | |
4023fb28 | 1680 | "" |
9db1d521 | 1681 | "@ |
d40c829f UW |
1682 | ler\t%0,%1 |
1683 | le\t%0,%1 | |
1684 | ley\t%0,%1 | |
1685 | ste\t%1,%0 | |
1686 | stey\t%1,%0 | |
1687 | lr\t%0,%1 | |
1688 | l\t%0,%1 | |
1689 | ly\t%0,%1 | |
1690 | st\t%1,%0 | |
1691 | sty\t%1,%0 | |
1692 | mvc\t%O0(4,%R0),%1" | |
d3632d41 UW |
1693 | [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") |
1694 | (set_attr "type" "floads,floads,floads,fstores,fstores,lr,load,load,store,store,cs")]) | |
4023fb28 | 1695 | |
9db1d521 HP |
1696 | ; |
1697 | ; load_multiple pattern(s). | |
1698 | ; | |
22ea6b4f UW |
1699 | ; ??? Due to reload problems with replacing registers inside match_parallel |
1700 | ; we currently support load_multiple/store_multiple only after reload. | |
1701 | ; | |
9db1d521 HP |
1702 | |
1703 | (define_expand "load_multiple" | |
1704 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1705 | (match_operand 1 "" "")) | |
1706 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 1707 | "reload_completed" |
9db1d521 | 1708 | { |
c19ec8f9 | 1709 | enum machine_mode mode; |
9db1d521 HP |
1710 | int regno; |
1711 | int count; | |
1712 | rtx from; | |
4023fb28 | 1713 | int i, off; |
9db1d521 HP |
1714 | |
1715 | /* Support only loading a constant number of fixed-point registers from | |
1716 | memory and only bother with this if more than two */ | |
1717 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1718 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1719 | || INTVAL (operands[2]) > 16 |
1720 | || GET_CODE (operands[1]) != MEM | |
1721 | || GET_CODE (operands[0]) != REG | |
1722 | || REGNO (operands[0]) >= 16) | |
1723 | FAIL; | |
1724 | ||
1725 | count = INTVAL (operands[2]); | |
1726 | regno = REGNO (operands[0]); | |
c19ec8f9 UW |
1727 | mode = GET_MODE (operands[0]); |
1728 | if (mode != SImode && mode != word_mode) | |
1729 | FAIL; | |
9db1d521 HP |
1730 | |
1731 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1732 | if (no_new_pseudos) |
1733 | { | |
1734 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
1735 | { | |
1736 | from = XEXP (operands[1], 0); | |
1737 | off = 0; | |
1738 | } | |
1739 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
1740 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
1741 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
1742 | { | |
1743 | from = XEXP (XEXP (operands[1], 0), 0); | |
1744 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
1745 | } | |
1746 | else | |
1747 | FAIL; | |
1748 | ||
1749 | if (from == frame_pointer_rtx || from == arg_pointer_rtx) | |
1750 | FAIL; | |
1751 | } | |
1752 | else | |
1753 | { | |
1754 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
1755 | off = 0; | |
1756 | } | |
9db1d521 HP |
1757 | |
1758 | for (i = 0; i < count; i++) | |
1759 | XVECEXP (operands[3], 0, i) | |
c19ec8f9 UW |
1760 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), |
1761 | change_address (operands[1], mode, | |
1762 | plus_constant (from, off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 1763 | }) |
9db1d521 HP |
1764 | |
1765 | (define_insn "*load_multiple_di" | |
1766 | [(match_parallel 0 "load_multiple_operation" | |
1767 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 1768 | (match_operand:DI 2 "s_operand" "QS"))])] |
22ea6b4f | 1769 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
1770 | { |
1771 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1772 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
d40c829f | 1773 | return "lmg\t%1,%0,%2"; |
10bbf137 | 1774 | } |
d3632d41 | 1775 | [(set_attr "op_type" "RSY") |
4023fb28 | 1776 | (set_attr "type" "lm")]) |
9db1d521 HP |
1777 | |
1778 | (define_insn "*load_multiple_si" | |
1779 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
1780 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
1781 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 1782 | "reload_completed" |
9db1d521 HP |
1783 | { |
1784 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1785 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
d40c829f | 1786 | return which_alternative == 0 ? "lm\t%1,%0,%2" : "lmy\t%1,%0,%2"; |
10bbf137 | 1787 | } |
d3632d41 | 1788 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1789 | (set_attr "type" "lm")]) |
9db1d521 HP |
1790 | |
1791 | ; | |
c7453384 | 1792 | ; store multiple pattern(s). |
9db1d521 HP |
1793 | ; |
1794 | ||
1795 | (define_expand "store_multiple" | |
1796 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1797 | (match_operand 1 "" "")) | |
1798 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 1799 | "reload_completed" |
9db1d521 | 1800 | { |
c19ec8f9 | 1801 | enum machine_mode mode; |
9db1d521 HP |
1802 | int regno; |
1803 | int count; | |
1804 | rtx to; | |
4023fb28 | 1805 | int i, off; |
9db1d521 HP |
1806 | |
1807 | /* Support only storing a constant number of fixed-point registers to | |
1808 | memory and only bother with this if more than two. */ | |
1809 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1810 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1811 | || INTVAL (operands[2]) > 16 |
1812 | || GET_CODE (operands[0]) != MEM | |
1813 | || GET_CODE (operands[1]) != REG | |
1814 | || REGNO (operands[1]) >= 16) | |
1815 | FAIL; | |
1816 | ||
1817 | count = INTVAL (operands[2]); | |
1818 | regno = REGNO (operands[1]); | |
c19ec8f9 UW |
1819 | mode = GET_MODE (operands[1]); |
1820 | if (mode != SImode && mode != word_mode) | |
1821 | FAIL; | |
9db1d521 HP |
1822 | |
1823 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1824 | |
1825 | if (no_new_pseudos) | |
1826 | { | |
1827 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
1828 | { | |
1829 | to = XEXP (operands[0], 0); | |
1830 | off = 0; | |
1831 | } | |
1832 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
1833 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
1834 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
1835 | { | |
1836 | to = XEXP (XEXP (operands[0], 0), 0); | |
1837 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
1838 | } | |
1839 | else | |
1840 | FAIL; | |
1841 | ||
1842 | if (to == frame_pointer_rtx || to == arg_pointer_rtx) | |
1843 | FAIL; | |
1844 | } | |
c7453384 | 1845 | else |
4023fb28 UW |
1846 | { |
1847 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
1848 | off = 0; | |
1849 | } | |
9db1d521 HP |
1850 | |
1851 | for (i = 0; i < count; i++) | |
1852 | XVECEXP (operands[3], 0, i) | |
1853 | = gen_rtx_SET (VOIDmode, | |
c19ec8f9 UW |
1854 | change_address (operands[0], mode, |
1855 | plus_constant (to, off + i * GET_MODE_SIZE (mode))), | |
1856 | gen_rtx_REG (mode, regno + i)); | |
10bbf137 | 1857 | }) |
9db1d521 HP |
1858 | |
1859 | (define_insn "*store_multiple_di" | |
1860 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 1861 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 1862 | (match_operand:DI 2 "register_operand" "r"))])] |
22ea6b4f | 1863 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
1864 | { |
1865 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1866 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
d40c829f | 1867 | return "stmg\t%2,%0,%1"; |
10bbf137 | 1868 | } |
d3632d41 | 1869 | [(set_attr "op_type" "RSY") |
4023fb28 | 1870 | (set_attr "type" "stm")]) |
9db1d521 HP |
1871 | |
1872 | ||
1873 | (define_insn "*store_multiple_si" | |
1874 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
1875 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
1876 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 1877 | "reload_completed" |
9db1d521 HP |
1878 | { |
1879 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1880 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
d40c829f | 1881 | return which_alternative == 0 ? "stm\t%2,%0,%1" : "stmy\t%2,%0,%1"; |
10bbf137 | 1882 | } |
d3632d41 | 1883 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1884 | (set_attr "type" "stm")]) |
9db1d521 HP |
1885 | |
1886 | ;; | |
1887 | ;; String instructions. | |
1888 | ;; | |
1889 | ||
91d39d71 UW |
1890 | ; |
1891 | ; strlenM instruction pattern(s). | |
1892 | ; | |
1893 | ||
1894 | (define_expand "strlendi" | |
1895 | [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" "")) | |
1896 | (parallel | |
1897 | [(set (match_dup 4) | |
1898 | (unspec:DI [(const_int 0) | |
1899 | (match_operand:BLK 1 "memory_operand" "") | |
1900 | (reg:QI 0) | |
1901 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) | |
1902 | (clobber (scratch:DI)) | |
1903 | (clobber (reg:CC 33))]) | |
1904 | (parallel | |
1905 | [(set (match_operand:DI 0 "register_operand" "") | |
1906 | (minus:DI (match_dup 4) (match_dup 5))) | |
1907 | (clobber (reg:CC 33))])] | |
1908 | "TARGET_64BIT" | |
1909 | { | |
1910 | operands[4] = gen_reg_rtx (DImode); | |
1911 | operands[5] = gen_reg_rtx (DImode); | |
1912 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
1913 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
1914 | }) | |
1915 | ||
1916 | (define_insn "*strlendi" | |
1917 | [(set (match_operand:DI 0 "register_operand" "=a") | |
1918 | (unspec:DI [(match_operand:DI 2 "general_operand" "0") | |
1919 | (mem:BLK (match_operand:DI 3 "register_operand" "1")) | |
1920 | (reg:QI 0) | |
1921 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) | |
1922 | (clobber (match_scratch:DI 1 "=a")) | |
1923 | (clobber (reg:CC 33))] | |
1924 | "TARGET_64BIT" | |
1925 | "srst\t%0,%1\;jo\t.-4" | |
1926 | [(set_attr "op_type" "NN") | |
1927 | (set_attr "type" "vs") | |
1928 | (set_attr "length" "8")]) | |
1929 | ||
1930 | (define_expand "strlensi" | |
1931 | [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" "")) | |
1932 | (parallel | |
1933 | [(set (match_dup 4) | |
1934 | (unspec:SI [(const_int 0) | |
1935 | (match_operand:BLK 1 "memory_operand" "") | |
1936 | (reg:QI 0) | |
1937 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) | |
1938 | (clobber (scratch:SI)) | |
1939 | (clobber (reg:CC 33))]) | |
1940 | (parallel | |
1941 | [(set (match_operand:SI 0 "register_operand" "") | |
1942 | (minus:SI (match_dup 4) (match_dup 5))) | |
1943 | (clobber (reg:CC 33))])] | |
1944 | "!TARGET_64BIT" | |
1945 | { | |
1946 | operands[4] = gen_reg_rtx (SImode); | |
1947 | operands[5] = gen_reg_rtx (SImode); | |
1948 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
1949 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
1950 | }) | |
1951 | ||
1952 | (define_insn "*strlensi" | |
1953 | [(set (match_operand:SI 0 "register_operand" "=a") | |
1954 | (unspec:SI [(match_operand:SI 2 "general_operand" "0") | |
1955 | (mem:BLK (match_operand:SI 3 "register_operand" "1")) | |
1956 | (reg:QI 0) | |
1957 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) | |
1958 | (clobber (match_scratch:SI 1 "=a")) | |
1959 | (clobber (reg:CC 33))] | |
1960 | "!TARGET_64BIT" | |
1961 | "srst\t%0,%1\;jo\t.-4" | |
1962 | [(set_attr "op_type" "NN") | |
1963 | (set_attr "type" "vs") | |
1964 | (set_attr "length" "8")]) | |
1965 | ||
9db1d521 | 1966 | ; |
a41c6c53 | 1967 | ; movstrM instruction pattern(s). |
9db1d521 HP |
1968 | ; |
1969 | ||
1970 | (define_expand "movstrdi" | |
a41c6c53 UW |
1971 | [(set (match_operand:BLK 0 "memory_operand" "") |
1972 | (match_operand:BLK 1 "memory_operand" "")) | |
1973 | (use (match_operand:DI 2 "general_operand" "")) | |
1974 | (match_operand 3 "" "")] | |
1975 | "TARGET_64BIT" | |
1976 | "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;") | |
9db1d521 HP |
1977 | |
1978 | (define_expand "movstrsi" | |
a41c6c53 UW |
1979 | [(set (match_operand:BLK 0 "memory_operand" "") |
1980 | (match_operand:BLK 1 "memory_operand" "")) | |
1981 | (use (match_operand:SI 2 "general_operand" "")) | |
1982 | (match_operand 3 "" "")] | |
1983 | "" | |
1984 | "s390_expand_movstr (operands[0], operands[1], operands[2]); DONE;") | |
9db1d521 | 1985 | |
ecbe845e UW |
1986 | ; Move a block that is up to 256 bytes in length. |
1987 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 1988 | |
b9404c99 UW |
1989 | (define_expand "movstr_short" |
1990 | [(parallel | |
1991 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1992 | (match_operand:BLK 1 "memory_operand" "")) | |
1993 | (use (match_operand 2 "nonmemory_operand" "")) | |
1994 | (clobber (match_dup 3))])] | |
1995 | "" | |
1996 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 1997 | |
b9404c99 | 1998 | (define_insn "*movstr_short" |
a41c6c53 UW |
1999 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q") |
2000 | (match_operand:BLK 1 "memory_operand" "Q,Q")) | |
b9404c99 UW |
2001 | (use (match_operand 2 "nonmemory_operand" "n,a")) |
2002 | (clobber (match_scratch 3 "=X,&a"))] | |
2003 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) | |
2004 | && GET_MODE (operands[3]) == Pmode" | |
ecbe845e UW |
2005 | { |
2006 | switch (which_alternative) | |
2007 | { | |
2008 | case 0: | |
d40c829f | 2009 | return "mvc\t%O0(%b2+1,%R0),%1"; |
ecbe845e UW |
2010 | |
2011 | case 1: | |
d40c829f UW |
2012 | output_asm_insn ("bras\t%3,.+10", operands); |
2013 | output_asm_insn ("mvc\t%O0(1,%R0),%1", operands); | |
2014 | return "ex\t%2,0(%3)"; | |
9db1d521 | 2015 | |
ecbe845e UW |
2016 | default: |
2017 | abort (); | |
2018 | } | |
10bbf137 | 2019 | } |
ecbe845e | 2020 | [(set_attr "op_type" "SS,NN") |
a41c6c53 | 2021 | (set_attr "type" "cs,cs") |
077dab3b | 2022 | (set_attr "atype" "*,agen") |
ecbe845e | 2023 | (set_attr "length" "*,14")]) |
9db1d521 | 2024 | |
a41c6c53 | 2025 | ; Move a block of arbitrary length. |
9db1d521 | 2026 | |
b9404c99 UW |
2027 | (define_expand "movstr_long" |
2028 | [(parallel | |
2029 | [(clobber (match_dup 2)) | |
2030 | (clobber (match_dup 3)) | |
2031 | (set (match_operand:BLK 0 "memory_operand" "") | |
2032 | (match_operand:BLK 1 "memory_operand" "")) | |
2033 | (use (match_operand 2 "general_operand" "")) | |
2034 | (use (match_dup 3)) | |
2035 | (clobber (reg:CC 33))])] | |
2036 | "" | |
2037 | { | |
2038 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
2039 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2040 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2041 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2042 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
2043 | rtx len0 = gen_lowpart (Pmode, reg0); | |
2044 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2045 | ||
2046 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
2047 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2048 | emit_move_insn (len0, operands[2]); | |
2049 | ||
2050 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
2051 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2052 | emit_move_insn (len1, operands[2]); | |
2053 | ||
2054 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2055 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2056 | operands[2] = reg0; | |
2057 | operands[3] = reg1; | |
2058 | }) | |
2059 | ||
2060 | (define_insn "*movstr_long_64" | |
2061 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
2062 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
2063 | (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
2064 | (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))) | |
2065 | (use (match_dup 2)) | |
2066 | (use (match_dup 3)) | |
9db1d521 | 2067 | (clobber (reg:CC 33))] |
9f37ccb1 | 2068 | "TARGET_64BIT" |
d40c829f | 2069 | "mvcle\t%0,%1,0\;jo\t.-4" |
9db1d521 | 2070 | [(set_attr "op_type" "NN") |
a41c6c53 | 2071 | (set_attr "type" "vs") |
9db1d521 HP |
2072 | (set_attr "length" "8")]) |
2073 | ||
b9404c99 UW |
2074 | (define_insn "*movstr_long_31" |
2075 | [(clobber (match_operand:DI 0 "register_operand" "=d")) | |
2076 | (clobber (match_operand:DI 1 "register_operand" "=d")) | |
2077 | (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
2078 | (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))) | |
2079 | (use (match_dup 2)) | |
2080 | (use (match_dup 3)) | |
9db1d521 | 2081 | (clobber (reg:CC 33))] |
9f37ccb1 | 2082 | "!TARGET_64BIT" |
d40c829f | 2083 | "mvcle\t%0,%1,0\;jo\t.-4" |
a41c6c53 UW |
2084 | [(set_attr "op_type" "NN") |
2085 | (set_attr "type" "vs") | |
a41c6c53 | 2086 | (set_attr "length" "8")]) |
9db1d521 HP |
2087 | |
2088 | ; | |
a41c6c53 | 2089 | ; clrstrM instruction pattern(s). |
9db1d521 HP |
2090 | ; |
2091 | ||
2092 | (define_expand "clrstrdi" | |
a41c6c53 | 2093 | [(set (match_operand:BLK 0 "memory_operand" "") |
9db1d521 HP |
2094 | (const_int 0)) |
2095 | (use (match_operand:DI 1 "general_operand" "")) | |
2096 | (match_operand 2 "" "")] | |
2097 | "TARGET_64BIT" | |
a41c6c53 | 2098 | "s390_expand_clrstr (operands[0], operands[1]); DONE;") |
9db1d521 HP |
2099 | |
2100 | (define_expand "clrstrsi" | |
a41c6c53 | 2101 | [(set (match_operand:BLK 0 "memory_operand" "") |
9db1d521 HP |
2102 | (const_int 0)) |
2103 | (use (match_operand:SI 1 "general_operand" "")) | |
2104 | (match_operand 2 "" "")] | |
a41c6c53 UW |
2105 | "" |
2106 | "s390_expand_clrstr (operands[0], operands[1]); DONE;") | |
9db1d521 | 2107 | |
a41c6c53 | 2108 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
2109 | ; The block length is taken as (operands[1] % 256) + 1. |
2110 | ||
2111 | (define_expand "clrstr_short" | |
2112 | [(parallel | |
2113 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2114 | (const_int 0)) | |
2115 | (use (match_operand 1 "nonmemory_operand" "")) | |
2116 | (clobber (match_dup 2)) | |
2117 | (clobber (reg:CC 33))])] | |
2118 | "" | |
2119 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2120 | |
b9404c99 | 2121 | (define_insn "*clrstr_short" |
a41c6c53 UW |
2122 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q") |
2123 | (const_int 0)) | |
b9404c99 UW |
2124 | (use (match_operand 1 "nonmemory_operand" "n,a")) |
2125 | (clobber (match_scratch 2 "=X,&a")) | |
a41c6c53 | 2126 | (clobber (reg:CC 33))] |
b9404c99 UW |
2127 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode) |
2128 | && GET_MODE (operands[2]) == Pmode" | |
a41c6c53 UW |
2129 | { |
2130 | switch (which_alternative) | |
2131 | { | |
2132 | case 0: | |
d40c829f | 2133 | return "xc\t%O0(%b1+1,%R0),%0"; |
9db1d521 | 2134 | |
a41c6c53 | 2135 | case 1: |
d40c829f UW |
2136 | output_asm_insn ("bras\t%2,.+10", operands); |
2137 | output_asm_insn ("xc\t%O0(1,%R0),%0", operands); | |
2138 | return "ex\t%1,0(%2)"; | |
9db1d521 | 2139 | |
a41c6c53 UW |
2140 | default: |
2141 | abort (); | |
2142 | } | |
10bbf137 | 2143 | } |
a41c6c53 UW |
2144 | [(set_attr "op_type" "SS,NN") |
2145 | (set_attr "type" "cs,cs") | |
077dab3b | 2146 | (set_attr "atype" "*,agen") |
a41c6c53 | 2147 | (set_attr "length" "*,14")]) |
9db1d521 | 2148 | |
b9404c99 UW |
2149 | ; Clear a block of arbitrary length. |
2150 | ||
2151 | (define_expand "clrstr_long" | |
2152 | [(parallel | |
2153 | [(clobber (match_dup 1)) | |
2154 | (set (match_operand:BLK 0 "memory_operand" "") | |
2155 | (const_int 0)) | |
2156 | (use (match_operand 1 "general_operand" "")) | |
2157 | (use (match_dup 2)) | |
2158 | (clobber (reg:CC 33))])] | |
2159 | "" | |
a41c6c53 | 2160 | { |
b9404c99 UW |
2161 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; |
2162 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2163 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2164 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2165 | rtx len0 = gen_lowpart (Pmode, reg0); | |
9db1d521 | 2166 | |
b9404c99 UW |
2167 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); |
2168 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2169 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 2170 | |
b9404c99 | 2171 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 2172 | |
b9404c99 UW |
2173 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
2174 | operands[1] = reg0; | |
2175 | operands[2] = reg1; | |
2176 | }) | |
a41c6c53 | 2177 | |
b9404c99 UW |
2178 | (define_insn "*clrstr_long_64" |
2179 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
2180 | (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
9db1d521 | 2181 | (const_int 0)) |
b9404c99 | 2182 | (use (match_dup 2)) |
9f37ccb1 | 2183 | (use (match_operand:TI 1 "register_operand" "d")) |
9db1d521 HP |
2184 | (clobber (reg:CC 33))] |
2185 | "TARGET_64BIT" | |
d40c829f | 2186 | "mvcle\t%0,%1,0\;jo\t.-4" |
9db1d521 | 2187 | [(set_attr "op_type" "NN") |
4023fb28 | 2188 | (set_attr "type" "vs") |
9db1d521 HP |
2189 | (set_attr "length" "8")]) |
2190 | ||
b9404c99 UW |
2191 | (define_insn "*clrstr_long_31" |
2192 | [(clobber (match_operand:DI 0 "register_operand" "=d")) | |
2193 | (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
9db1d521 | 2194 | (const_int 0)) |
b9404c99 | 2195 | (use (match_dup 2)) |
9f37ccb1 | 2196 | (use (match_operand:DI 1 "register_operand" "d")) |
9db1d521 HP |
2197 | (clobber (reg:CC 33))] |
2198 | "!TARGET_64BIT" | |
d40c829f | 2199 | "mvcle\t%0,%1,0\;jo\t.-4" |
9db1d521 | 2200 | [(set_attr "op_type" "NN") |
4023fb28 | 2201 | (set_attr "type" "vs") |
9db1d521 HP |
2202 | (set_attr "length" "8")]) |
2203 | ||
2204 | ; | |
358b8f01 | 2205 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
2206 | ; |
2207 | ||
358b8f01 | 2208 | (define_expand "cmpmemdi" |
a41c6c53 UW |
2209 | [(set (match_operand:DI 0 "register_operand" "") |
2210 | (compare:DI (match_operand:BLK 1 "memory_operand" "") | |
2211 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
2212 | (use (match_operand:DI 3 "general_operand" "")) | |
2213 | (use (match_operand:DI 4 "" ""))] | |
2214 | "TARGET_64BIT" | |
c7453384 | 2215 | "s390_expand_cmpmem (operands[0], operands[1], |
a41c6c53 | 2216 | operands[2], operands[3]); DONE;") |
9db1d521 | 2217 | |
358b8f01 | 2218 | (define_expand "cmpmemsi" |
a41c6c53 UW |
2219 | [(set (match_operand:SI 0 "register_operand" "") |
2220 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
2221 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
2222 | (use (match_operand:SI 3 "general_operand" "")) | |
2223 | (use (match_operand:SI 4 "" ""))] | |
2224 | "" | |
c7453384 | 2225 | "s390_expand_cmpmem (operands[0], operands[1], |
a41c6c53 | 2226 | operands[2], operands[3]); DONE;") |
9db1d521 | 2227 | |
a41c6c53 UW |
2228 | ; Compare a block that is up to 256 bytes in length. |
2229 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2230 | |
b9404c99 UW |
2231 | (define_expand "cmpmem_short" |
2232 | [(parallel | |
2233 | [(set (reg:CCS 33) | |
2234 | (compare:CCS (match_operand:BLK 0 "memory_operand" "") | |
2235 | (match_operand:BLK 1 "memory_operand" ""))) | |
2236 | (use (match_operand 2 "nonmemory_operand" "")) | |
2237 | (clobber (match_dup 3))])] | |
2238 | "" | |
2239 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2240 | |
b9404c99 | 2241 | (define_insn "*cmpmem_short" |
a41c6c53 UW |
2242 | [(set (reg:CCS 33) |
2243 | (compare:CCS (match_operand:BLK 0 "memory_operand" "=Q,Q") | |
2244 | (match_operand:BLK 1 "memory_operand" "Q,Q"))) | |
b9404c99 UW |
2245 | (use (match_operand 2 "nonmemory_operand" "n,a")) |
2246 | (clobber (match_scratch 3 "=X,&a"))] | |
2247 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) | |
2248 | && GET_MODE (operands[3]) == Pmode" | |
9db1d521 | 2249 | { |
a41c6c53 | 2250 | switch (which_alternative) |
9db1d521 | 2251 | { |
a41c6c53 | 2252 | case 0: |
d40c829f | 2253 | return "clc\t%O0(%b2+1,%R0),%1"; |
9db1d521 | 2254 | |
a41c6c53 | 2255 | case 1: |
d40c829f UW |
2256 | output_asm_insn ("bras\t%3,.+10", operands); |
2257 | output_asm_insn ("clc\t%O0(1,%R0),%1", operands); | |
2258 | return "ex\t%2,0(%3)"; | |
9db1d521 | 2259 | |
a41c6c53 UW |
2260 | default: |
2261 | abort (); | |
9db1d521 | 2262 | } |
10bbf137 | 2263 | } |
a41c6c53 UW |
2264 | [(set_attr "op_type" "SS,NN") |
2265 | (set_attr "type" "cs,cs") | |
077dab3b | 2266 | (set_attr "atype" "*,agen") |
a41c6c53 | 2267 | (set_attr "length" "*,14")]) |
9db1d521 | 2268 | |
a41c6c53 | 2269 | ; Compare a block of arbitrary length. |
9db1d521 | 2270 | |
b9404c99 UW |
2271 | (define_expand "cmpmem_long" |
2272 | [(parallel | |
2273 | [(clobber (match_dup 2)) | |
2274 | (clobber (match_dup 3)) | |
2275 | (set (reg:CCS 33) | |
2276 | (compare:CCS (match_operand:BLK 0 "memory_operand" "") | |
2277 | (match_operand:BLK 1 "memory_operand" ""))) | |
2278 | (use (match_operand 2 "general_operand" "")) | |
2279 | (use (match_dup 3))])] | |
2280 | "" | |
2281 | { | |
2282 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
2283 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2284 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2285 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2286 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
2287 | rtx len0 = gen_lowpart (Pmode, reg0); | |
2288 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2289 | ||
2290 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
2291 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2292 | emit_move_insn (len0, operands[2]); | |
2293 | ||
2294 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
2295 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2296 | emit_move_insn (len1, operands[2]); | |
2297 | ||
2298 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2299 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2300 | operands[2] = reg0; | |
2301 | operands[3] = reg1; | |
2302 | }) | |
2303 | ||
2304 | (define_insn "*cmpmem_long_64" | |
4023fb28 UW |
2305 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
2306 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
2307 | (set (reg:CCS 33) | |
2308 | (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
f8766020 HP |
2309 | (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))) |
2310 | (use (match_dup 2)) | |
2311 | (use (match_dup 3))] | |
9db1d521 | 2312 | "TARGET_64BIT" |
287ff198 UW |
2313 | "clcle\t%0,%1,0\;jo\t.-4" |
2314 | [(set_attr "op_type" "NN") | |
2315 | (set_attr "type" "vs") | |
2316 | (set_attr "length" "8")]) | |
9db1d521 | 2317 | |
b9404c99 | 2318 | (define_insn "*cmpmem_long_31" |
4023fb28 UW |
2319 | [(clobber (match_operand:DI 0 "register_operand" "=d")) |
2320 | (clobber (match_operand:DI 1 "register_operand" "=d")) | |
2321 | (set (reg:CCS 33) | |
2322 | (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
f8766020 HP |
2323 | (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))) |
2324 | (use (match_dup 2)) | |
2325 | (use (match_dup 3))] | |
9db1d521 | 2326 | "!TARGET_64BIT" |
287ff198 UW |
2327 | "clcle\t%0,%1,0\;jo\t.-4" |
2328 | [(set_attr "op_type" "NN") | |
2329 | (set_attr "type" "vs") | |
2330 | (set_attr "length" "8")]) | |
9db1d521 HP |
2331 | |
2332 | ; Convert condition code to integer in range (-1, 0, 1) | |
2333 | ||
2334 | (define_insn "cmpint_si" | |
2335 | [(set (match_operand:SI 0 "register_operand" "=d") | |
ba956982 | 2336 | (compare:SI (reg:CCS 33) (const_int 0)))] |
9db1d521 | 2337 | "" |
9db1d521 | 2338 | { |
d40c829f UW |
2339 | output_asm_insn ("lhi\t%0,1", operands); |
2340 | output_asm_insn ("jh\t.+12", operands); | |
2341 | output_asm_insn ("jl\t.+6", operands); | |
2342 | output_asm_insn ("sr\t%0,%0", operands); | |
2343 | return "lcr\t%0,%0"; | |
10bbf137 | 2344 | } |
9db1d521 HP |
2345 | [(set_attr "op_type" "NN") |
2346 | (set_attr "length" "16") | |
f2d3c02a | 2347 | (set_attr "type" "other")]) |
9db1d521 HP |
2348 | |
2349 | (define_insn "cmpint_di" | |
2350 | [(set (match_operand:DI 0 "register_operand" "=d") | |
ba956982 | 2351 | (compare:DI (reg:CCS 33) (const_int 0)))] |
9db1d521 | 2352 | "TARGET_64BIT" |
9db1d521 | 2353 | { |
d40c829f | 2354 | output_asm_insn ("lghi\t%0,1", operands); |
fd87a357 UW |
2355 | output_asm_insn ("jh\t.+16", operands); |
2356 | output_asm_insn ("jl\t.+8", operands); | |
d40c829f UW |
2357 | output_asm_insn ("sgr\t%0,%0", operands); |
2358 | return "lcgr\t%0,%0"; | |
10bbf137 | 2359 | } |
9db1d521 | 2360 | [(set_attr "op_type" "NN") |
fd87a357 | 2361 | (set_attr "length" "20") |
f2d3c02a | 2362 | (set_attr "type" "other")]) |
9db1d521 | 2363 | |
4023fb28 | 2364 | |
9db1d521 HP |
2365 | ;; |
2366 | ;;- Conversion instructions. | |
2367 | ;; | |
2368 | ||
4023fb28 | 2369 | (define_insn "*sethighqisi" |
d3632d41 | 2370 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
10bbf137 | 2371 | (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2372 | (clobber (reg:CC 33))] |
2373 | "" | |
d3632d41 | 2374 | "@ |
d40c829f UW |
2375 | icm\t%0,8,%1 |
2376 | icmy\t%0,8,%1" | |
d3632d41 | 2377 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 UW |
2378 | |
2379 | (define_insn "*sethighhisi" | |
d3632d41 | 2380 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
10bbf137 | 2381 | (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2382 | (clobber (reg:CC 33))] |
2383 | "" | |
d3632d41 | 2384 | "@ |
d40c829f UW |
2385 | icm\t%0,12,%1 |
2386 | icmy\t%0,12,%1" | |
d3632d41 | 2387 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 UW |
2388 | |
2389 | (define_insn "*sethighqidi_64" | |
2390 | [(set (match_operand:DI 0 "register_operand" "=d") | |
10bbf137 | 2391 | (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2392 | (clobber (reg:CC 33))] |
2393 | "TARGET_64BIT" | |
d40c829f | 2394 | "icmh\t%0,8,%1" |
d3632d41 | 2395 | [(set_attr "op_type" "RSY")]) |
4023fb28 UW |
2396 | |
2397 | (define_insn "*sethighqidi_31" | |
d3632d41 | 2398 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
10bbf137 | 2399 | (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH)) |
4023fb28 UW |
2400 | (clobber (reg:CC 33))] |
2401 | "!TARGET_64BIT" | |
d3632d41 | 2402 | "@ |
d40c829f UW |
2403 | icm\t%0,8,%1 |
2404 | icmy\t%0,8,%1" | |
d3632d41 | 2405 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 | 2406 | |
cc7ab9b7 UW |
2407 | (define_insn_and_split "*extractqi" |
2408 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2409 | (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") | |
2410 | (match_operand 2 "const_int_operand" "n") | |
2411 | (const_int 0))) | |
2412 | (clobber (reg:CC 33))] | |
2413 | "!TARGET_64BIT | |
4023fb28 | 2414 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8" |
cc7ab9b7 UW |
2415 | "#" |
2416 | "&& reload_completed" | |
4023fb28 | 2417 | [(parallel |
10bbf137 | 2418 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2419 | (clobber (reg:CC 33))]) |
2420 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] | |
4023fb28 UW |
2421 | { |
2422 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
2423 | operands[1] = change_address (operands[1], QImode, 0); | |
10bbf137 | 2424 | } |
0796c16a | 2425 | [(set_attr "atype" "agen")]) |
4023fb28 | 2426 | |
cc7ab9b7 UW |
2427 | (define_insn_and_split "*extracthi" |
2428 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2429 | (zero_extract:SI (match_operand:QI 1 "s_operand" "Q") | |
2430 | (match_operand 2 "const_int_operand" "n") | |
2431 | (const_int 0))) | |
2432 | (clobber (reg:CC 33))] | |
2433 | "!TARGET_64BIT | |
4023fb28 | 2434 | && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16" |
cc7ab9b7 UW |
2435 | "#" |
2436 | "&& reload_completed" | |
4023fb28 | 2437 | [(parallel |
10bbf137 | 2438 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2439 | (clobber (reg:CC 33))]) |
2440 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] | |
4023fb28 UW |
2441 | { |
2442 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
2443 | operands[1] = change_address (operands[1], HImode, 0); | |
10bbf137 | 2444 | } |
0796c16a | 2445 | [(set_attr "atype" "agen")]) |
4023fb28 | 2446 | |
9db1d521 HP |
2447 | ; |
2448 | ; extendsidi2 instruction pattern(s). | |
2449 | ; | |
2450 | ||
4023fb28 UW |
2451 | (define_expand "extendsidi2" |
2452 | [(set (match_operand:DI 0 "register_operand" "") | |
2453 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2454 | "" | |
2455 | " | |
2456 | { | |
2457 | if (!TARGET_64BIT) | |
2458 | { | |
9f37ccb1 UW |
2459 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2460 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); | |
2461 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
2462 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
2463 | DONE; |
2464 | } | |
2465 | } | |
2466 | ") | |
2467 | ||
2468 | (define_insn "*extendsidi2" | |
9db1d521 HP |
2469 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2470 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2471 | "TARGET_64BIT" | |
2472 | "@ | |
d40c829f UW |
2473 | lgfr\t%0,%1 |
2474 | lgf\t%0,%1" | |
d3632d41 | 2475 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2476 | |
9db1d521 HP |
2477 | ; |
2478 | ; extendhidi2 instruction pattern(s). | |
2479 | ; | |
2480 | ||
4023fb28 UW |
2481 | (define_expand "extendhidi2" |
2482 | [(set (match_operand:DI 0 "register_operand" "") | |
2483 | (sign_extend:DI (match_operand:HI 1 "register_operand" "")))] | |
2484 | "" | |
2485 | " | |
2486 | { | |
2487 | if (!TARGET_64BIT) | |
2488 | { | |
2489 | rtx tmp = gen_reg_rtx (SImode); | |
2490 | emit_insn (gen_extendhisi2 (tmp, operands[1])); | |
2491 | emit_insn (gen_extendsidi2 (operands[0], tmp)); | |
2492 | DONE; | |
2493 | } | |
2494 | else | |
2495 | { | |
2496 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2497 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); | |
c7453384 | 2498 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48))); |
4023fb28 UW |
2499 | DONE; |
2500 | } | |
2501 | } | |
2502 | ") | |
2503 | ||
2504 | (define_insn "*extendhidi2" | |
9db1d521 | 2505 | [(set (match_operand:DI 0 "register_operand" "=d") |
4023fb28 | 2506 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] |
9db1d521 | 2507 | "TARGET_64BIT" |
d40c829f | 2508 | "lgh\t%0,%1" |
d3632d41 | 2509 | [(set_attr "op_type" "RXY")]) |
9db1d521 HP |
2510 | |
2511 | ; | |
2512 | ; extendqidi2 instruction pattern(s). | |
2513 | ; | |
2514 | ||
4023fb28 UW |
2515 | (define_expand "extendqidi2" |
2516 | [(set (match_operand:DI 0 "register_operand" "") | |
2517 | (sign_extend:DI (match_operand:QI 1 "register_operand" "")))] | |
2518 | "" | |
2519 | " | |
2520 | { | |
2521 | if (!TARGET_64BIT) | |
2522 | { | |
2523 | rtx tmp = gen_reg_rtx (SImode); | |
2524 | emit_insn (gen_extendqisi2 (tmp, operands[1])); | |
2525 | emit_insn (gen_extendsidi2 (operands[0], tmp)); | |
2526 | DONE; | |
2527 | } | |
2528 | else | |
2529 | { | |
2530 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2531 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); | |
c7453384 | 2532 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56))); |
4023fb28 UW |
2533 | DONE; |
2534 | } | |
2535 | } | |
2536 | ") | |
2537 | ||
d3632d41 UW |
2538 | (define_insn "*extendqidi2" |
2539 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2540 | (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))] | |
2541 | "TARGET_64BIT && TARGET_LONG_DISPLACEMENT" | |
d40c829f | 2542 | "lgb\t%0,%1" |
d3632d41 UW |
2543 | [(set_attr "op_type" "RXY")]) |
2544 | ||
19796784 AK |
2545 | (define_insn_and_split "*extendqidi2_short_displ" |
2546 | [(set (match_operand:DI 0 "register_operand" "=d") | |
59f8a8be UW |
2547 | (sign_extend:DI (match_operand:QI 1 "s_operand" "Q"))) |
2548 | (clobber (reg:CC 33))] | |
19796784 AK |
2549 | "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT" |
2550 | "#" | |
2551 | "&& reload_completed" | |
4023fb28 | 2552 | [(parallel |
10bbf137 | 2553 | [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2554 | (clobber (reg:CC 33))]) |
2555 | (parallel | |
2556 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56))) | |
2557 | (clobber (reg:CC 33))])] | |
2558 | "") | |
9db1d521 HP |
2559 | |
2560 | ; | |
2561 | ; extendhisi2 instruction pattern(s). | |
2562 | ; | |
2563 | ||
4023fb28 UW |
2564 | (define_expand "extendhisi2" |
2565 | [(set (match_operand:SI 0 "register_operand" "") | |
2566 | (sign_extend:SI (match_operand:HI 1 "register_operand" "")))] | |
9db1d521 | 2567 | "" |
4023fb28 UW |
2568 | " |
2569 | { | |
2570 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2571 | emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16))); | |
c7453384 | 2572 | emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16))); |
4023fb28 UW |
2573 | DONE; |
2574 | } | |
2575 | ") | |
9db1d521 | 2576 | |
4023fb28 | 2577 | (define_insn "*extendhisi2" |
d3632d41 UW |
2578 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
2579 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
4023fb28 | 2580 | "" |
d3632d41 | 2581 | "@ |
d40c829f UW |
2582 | lh\t%0,%1 |
2583 | lhy\t%0,%1" | |
d3632d41 | 2584 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 HP |
2585 | |
2586 | ; | |
2587 | ; extendqisi2 instruction pattern(s). | |
2588 | ; | |
2589 | ||
4023fb28 UW |
2590 | (define_expand "extendqisi2" |
2591 | [(set (match_operand:SI 0 "register_operand" "") | |
2592 | (sign_extend:SI (match_operand:QI 1 "register_operand" "")))] | |
9db1d521 | 2593 | "" |
4023fb28 UW |
2594 | " |
2595 | { | |
2596 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2597 | emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24))); | |
c7453384 | 2598 | emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24))); |
4023fb28 UW |
2599 | DONE; |
2600 | } | |
2601 | ") | |
9db1d521 | 2602 | |
d3632d41 UW |
2603 | (define_insn "*extendqisi2" |
2604 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2605 | (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2606 | "TARGET_LONG_DISPLACEMENT" |
d40c829f | 2607 | "lb\t%0,%1" |
d3632d41 UW |
2608 | [(set_attr "op_type" "RXY")]) |
2609 | ||
eb457a7a | 2610 | (define_insn_and_split "*extendqisi2_short_displ" |
19796784 | 2611 | [(set (match_operand:SI 0 "register_operand" "=d") |
59f8a8be UW |
2612 | (sign_extend:SI (match_operand:QI 1 "s_operand" "Q"))) |
2613 | (clobber (reg:CC 33))] | |
19796784 AK |
2614 | "!TARGET_LONG_DISPLACEMENT" |
2615 | "#" | |
2616 | "&& reload_completed" | |
4023fb28 | 2617 | [(parallel |
10bbf137 | 2618 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH)) |
4023fb28 UW |
2619 | (clobber (reg:CC 33))]) |
2620 | (parallel | |
2621 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24))) | |
2622 | (clobber (reg:CC 33))])] | |
2623 | "") | |
9db1d521 HP |
2624 | |
2625 | ; | |
2626 | ; extendqihi2 instruction pattern(s). | |
2627 | ; | |
2628 | ||
9db1d521 HP |
2629 | |
2630 | ; | |
2631 | ; zero_extendsidi2 instruction pattern(s). | |
2632 | ; | |
2633 | ||
4023fb28 UW |
2634 | (define_expand "zero_extendsidi2" |
2635 | [(set (match_operand:DI 0 "register_operand" "") | |
2636 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2637 | "" | |
2638 | " | |
2639 | { | |
2640 | if (!TARGET_64BIT) | |
2641 | { | |
9f37ccb1 UW |
2642 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2643 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); | |
2644 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
2645 | DONE; |
2646 | } | |
2647 | } | |
2648 | ") | |
2649 | ||
2650 | (define_insn "*zero_extendsidi2" | |
9db1d521 HP |
2651 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2652 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2653 | "TARGET_64BIT" | |
2654 | "@ | |
d40c829f UW |
2655 | llgfr\t%0,%1 |
2656 | llgf\t%0,%1" | |
d3632d41 | 2657 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2658 | |
9db1d521 HP |
2659 | ; |
2660 | ; zero_extendhidi2 instruction pattern(s). | |
2661 | ; | |
2662 | ||
4023fb28 UW |
2663 | (define_expand "zero_extendhidi2" |
2664 | [(set (match_operand:DI 0 "register_operand" "") | |
2665 | (zero_extend:DI (match_operand:HI 1 "register_operand" "")))] | |
2666 | "" | |
2667 | " | |
2668 | { | |
2669 | if (!TARGET_64BIT) | |
2670 | { | |
2671 | rtx tmp = gen_reg_rtx (SImode); | |
2672 | emit_insn (gen_zero_extendhisi2 (tmp, operands[1])); | |
2673 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
2674 | DONE; | |
2675 | } | |
2676 | else | |
2677 | { | |
2678 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2679 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); | |
c7453384 | 2680 | emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48))); |
4023fb28 UW |
2681 | DONE; |
2682 | } | |
2683 | } | |
2684 | ") | |
9db1d521 | 2685 | |
4023fb28 UW |
2686 | (define_insn "*zero_extendhidi2" |
2687 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2688 | (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))] | |
9db1d521 | 2689 | "TARGET_64BIT" |
d40c829f | 2690 | "llgh\t%0,%1" |
d3632d41 | 2691 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2692 | |
288e517f AK |
2693 | ; |
2694 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
2695 | ; | |
2696 | ||
2697 | (define_insn "*llgt_sisi" | |
2698 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
2699 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m") | |
2700 | (const_int 2147483647)))] | |
2701 | "TARGET_64BIT" | |
2702 | "@ | |
2703 | llgtr\t%0,%1 | |
2704 | llgt\t%0,%1" | |
2705 | [(set_attr "op_type" "RRE,RXE")]) | |
2706 | ||
f19a9af7 AK |
2707 | (define_split |
2708 | [(set (match_operand:SI 0 "register_operand" "") | |
2709 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
288e517f AK |
2710 | (const_int 2147483647))) |
2711 | (clobber (reg:CC 33))] | |
f19a9af7 | 2712 | "TARGET_64BIT && reload_completed" |
288e517f AK |
2713 | [(set (match_dup 0) |
2714 | (and:SI (match_dup 1) | |
2715 | (const_int 2147483647)))] | |
2716 | "") | |
2717 | ||
2718 | (define_insn "*llgt_didi" | |
2719 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2720 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
2721 | (const_int 2147483647)))] | |
2722 | "TARGET_64BIT" | |
2723 | "@ | |
2724 | llgtr\t%0,%1 | |
2725 | llgt\t%0,%N1" | |
2726 | [(set_attr "op_type" "RRE,RXE")]) | |
2727 | ||
f19a9af7 AK |
2728 | (define_split |
2729 | [(set (match_operand:DI 0 "register_operand" "") | |
2730 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "") | |
288e517f AK |
2731 | (const_int 2147483647))) |
2732 | (clobber (reg:CC 33))] | |
f19a9af7 | 2733 | "TARGET_64BIT && reload_completed" |
288e517f AK |
2734 | [(set (match_dup 0) |
2735 | (and:DI (match_dup 1) | |
2736 | (const_int 2147483647)))] | |
2737 | "") | |
2738 | ||
2739 | (define_insn "*llgt_sidi" | |
2740 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2741 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) | |
2742 | (const_int 2147483647)))] | |
2743 | "TARGET_64BIT" | |
2744 | "llgt\t%0,%1" | |
2745 | [(set_attr "op_type" "RXE")]) | |
2746 | ||
2747 | (define_insn_and_split "*llgt_sidi_split" | |
2748 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2749 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) | |
2750 | (const_int 2147483647))) | |
2751 | (clobber (reg:CC 33))] | |
2752 | "TARGET_64BIT" | |
2753 | "#" | |
2754 | "&& reload_completed" | |
2755 | [(set (match_dup 0) | |
2756 | (and:DI (subreg:DI (match_dup 1) 0) | |
2757 | (const_int 2147483647)))] | |
2758 | "") | |
2759 | ||
9db1d521 | 2760 | ; |
4023fb28 | 2761 | ; zero_extendqidi2 instruction pattern(s) |
9db1d521 HP |
2762 | ; |
2763 | ||
4023fb28 UW |
2764 | (define_expand "zero_extendqidi2" |
2765 | [(set (match_operand:DI 0 "register_operand" "") | |
2766 | (zero_extend:DI (match_operand:QI 1 "register_operand" "")))] | |
9db1d521 HP |
2767 | "" |
2768 | " | |
2769 | { | |
2770 | if (!TARGET_64BIT) | |
2771 | { | |
4023fb28 UW |
2772 | rtx tmp = gen_reg_rtx (SImode); |
2773 | emit_insn (gen_zero_extendqisi2 (tmp, operands[1])); | |
2774 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
9db1d521 HP |
2775 | DONE; |
2776 | } | |
4023fb28 UW |
2777 | else |
2778 | { | |
2779 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2780 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); | |
c7453384 | 2781 | emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56))); |
4023fb28 UW |
2782 | DONE; |
2783 | } | |
2784 | } | |
2785 | ") | |
9db1d521 | 2786 | |
4023fb28 UW |
2787 | (define_insn "*zero_extendqidi2" |
2788 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2789 | (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))] | |
9db1d521 | 2790 | "TARGET_64BIT" |
d40c829f | 2791 | "llgc\t%0,%1" |
d3632d41 | 2792 | [(set_attr "op_type" "RXY")]) |
9db1d521 HP |
2793 | |
2794 | ; | |
4023fb28 | 2795 | ; zero_extendhisi2 instruction pattern(s). |
9db1d521 HP |
2796 | ; |
2797 | ||
4023fb28 UW |
2798 | (define_expand "zero_extendhisi2" |
2799 | [(set (match_operand:SI 0 "register_operand" "") | |
2800 | (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] | |
9db1d521 | 2801 | "" |
4023fb28 UW |
2802 | " |
2803 | { | |
2804 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2805 | emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff))); | |
2806 | DONE; | |
2807 | } | |
2808 | ") | |
9db1d521 | 2809 | |
4023fb28 | 2810 | (define_insn "*zero_extendhisi2_64" |
9db1d521 | 2811 | [(set (match_operand:SI 0 "register_operand" "=d") |
4023fb28 | 2812 | (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] |
9db1d521 | 2813 | "TARGET_64BIT" |
d40c829f | 2814 | "llgh\t%0,%1" |
d3632d41 | 2815 | [(set_attr "op_type" "RXY")]) |
cc7ab9b7 UW |
2816 | |
2817 | (define_insn_and_split "*zero_extendhisi2_31" | |
2818 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 2819 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
cc7ab9b7 UW |
2820 | (clobber (reg:CC 33))] |
2821 | "!TARGET_64BIT" | |
2822 | "#" | |
2823 | "&& reload_completed" | |
2824 | [(set (match_dup 0) (const_int 0)) | |
2825 | (parallel | |
2826 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
2827 | (clobber (reg:CC 33))])] | |
2828 | "operands[2] = gen_lowpart (HImode, operands[0]);" | |
0796c16a | 2829 | [(set_attr "atype" "agen")]) |
c7453384 | 2830 | |
4023fb28 UW |
2831 | ; |
2832 | ; zero_extendqisi2 instruction pattern(s). | |
2833 | ; | |
9db1d521 HP |
2834 | |
2835 | (define_expand "zero_extendqisi2" | |
2836 | [(set (match_operand:SI 0 "register_operand" "") | |
4023fb28 | 2837 | (zero_extend:SI (match_operand:QI 1 "register_operand" "")))] |
9db1d521 HP |
2838 | "" |
2839 | " | |
2840 | { | |
4023fb28 UW |
2841 | operands[1] = gen_lowpart (SImode, operands[1]); |
2842 | emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff))); | |
2843 | DONE; | |
2844 | } | |
2845 | ") | |
9db1d521 | 2846 | |
4023fb28 UW |
2847 | (define_insn "*zero_extendqisi2_64" |
2848 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2849 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2850 | "TARGET_ZARCH" |
d40c829f | 2851 | "llgc\t%0,%1" |
d3632d41 | 2852 | [(set_attr "op_type" "RXY")]) |
cc7ab9b7 UW |
2853 | |
2854 | (define_insn_and_split "*zero_extendqisi2_31" | |
2855 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
2856 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2857 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2858 | "#" |
2859 | "&& reload_completed" | |
2860 | [(set (match_dup 0) (const_int 0)) | |
2861 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
2862 | "operands[2] = gen_lowpart (QImode, operands[0]);" | |
0796c16a | 2863 | [(set_attr "atype" "agen")]) |
c7453384 | 2864 | |
9db1d521 HP |
2865 | ; |
2866 | ; zero_extendqihi2 instruction pattern(s). | |
2867 | ; | |
2868 | ||
9db1d521 HP |
2869 | (define_expand "zero_extendqihi2" |
2870 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 2871 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
9e8327e3 | 2872 | "TARGET_ZARCH" |
9db1d521 HP |
2873 | " |
2874 | { | |
4023fb28 UW |
2875 | operands[1] = gen_lowpart (HImode, operands[1]); |
2876 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
2877 | DONE; | |
2878 | } | |
2879 | ") | |
9db1d521 | 2880 | |
4023fb28 | 2881 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 2882 | [(set (match_operand:HI 0 "register_operand" "=d") |
cc7ab9b7 | 2883 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] |
9e8327e3 | 2884 | "TARGET_ZARCH" |
d40c829f | 2885 | "llgc\t%0,%1" |
d3632d41 | 2886 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2887 | |
cc7ab9b7 UW |
2888 | (define_insn_and_split "*zero_extendqihi2_31" |
2889 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
2890 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2891 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2892 | "#" |
2893 | "&& reload_completed" | |
2894 | [(set (match_dup 0) (const_int 0)) | |
2895 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
2896 | "operands[2] = gen_lowpart (QImode, operands[0]);" | |
0796c16a | 2897 | [(set_attr "atype" "agen")]) |
cc7ab9b7 UW |
2898 | |
2899 | ||
9db1d521 HP |
2900 | ; |
2901 | ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s). | |
2902 | ; | |
2903 | ||
2904 | (define_expand "fixuns_truncdfdi2" | |
2905 | [(set (match_operand:DI 0 "register_operand" "") | |
2906 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))] | |
2907 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2908 | { |
2909 | rtx label1 = gen_label_rtx (); | |
2910 | rtx label2 = gen_label_rtx (); | |
2911 | rtx temp = gen_reg_rtx (DFmode); | |
2912 | operands[1] = force_reg (DFmode, operands[1]); | |
2913 | ||
c7453384 | 2914 | emit_insn (gen_cmpdf (operands[1], |
4023fb28 | 2915 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 2916 | REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode))); |
9db1d521 | 2917 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
2918 | emit_insn (gen_subdf3 (temp, operands[1], |
2919 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2920 | REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode))); |
9db1d521 | 2921 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7))); |
f314b9b1 | 2922 | emit_jump (label2); |
9db1d521 HP |
2923 | |
2924 | emit_label (label1); | |
2925 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2926 | emit_label (label2); | |
2927 | DONE; | |
10bbf137 | 2928 | }) |
9db1d521 HP |
2929 | |
2930 | (define_expand "fix_truncdfdi2" | |
2931 | [(set (match_operand:DI 0 "register_operand" "") | |
2932 | (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
2933 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2934 | { |
2935 | operands[1] = force_reg (DFmode, operands[1]); | |
2936 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
2937 | DONE; | |
10bbf137 | 2938 | }) |
9db1d521 HP |
2939 | |
2940 | (define_insn "fix_truncdfdi2_ieee" | |
2941 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2942 | (fix:DI (match_operand:DF 1 "register_operand" "f"))) | |
10bbf137 | 2943 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
2944 | (clobber (reg:CC 33))] |
2945 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 2946 | "cgdbr\t%0,%h2,%1" |
9db1d521 | 2947 | [(set_attr "op_type" "RRE") |
077dab3b | 2948 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
2949 | |
2950 | ; | |
2951 | ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s). | |
2952 | ; | |
2953 | ||
2954 | (define_expand "fixuns_truncdfsi2" | |
2955 | [(set (match_operand:SI 0 "register_operand" "") | |
2956 | (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))] | |
2957 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2958 | { |
2959 | rtx label1 = gen_label_rtx (); | |
2960 | rtx label2 = gen_label_rtx (); | |
2961 | rtx temp = gen_reg_rtx (DFmode); | |
2962 | ||
2963 | operands[1] = force_reg (DFmode,operands[1]); | |
c7453384 | 2964 | emit_insn (gen_cmpdf (operands[1], |
4023fb28 | 2965 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 2966 | REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode))); |
9db1d521 | 2967 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
2968 | emit_insn (gen_subdf3 (temp, operands[1], |
2969 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 2970 | REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode))); |
9db1d521 | 2971 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7))); |
f314b9b1 | 2972 | emit_jump (label2); |
9db1d521 HP |
2973 | |
2974 | emit_label (label1); | |
2975 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
2976 | emit_label (label2); | |
2977 | DONE; | |
10bbf137 | 2978 | }) |
9db1d521 HP |
2979 | |
2980 | (define_expand "fix_truncdfsi2" | |
2981 | [(set (match_operand:SI 0 "register_operand" "") | |
2982 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
2983 | "TARGET_HARD_FLOAT" | |
9db1d521 | 2984 | { |
c7453384 | 2985 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
2986 | { |
2987 | /* This is the algorithm from POP chapter A.5.7.2. */ | |
2988 | ||
c19ec8f9 | 2989 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
4023fb28 UW |
2990 | rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000); |
2991 | rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000); | |
9db1d521 HP |
2992 | |
2993 | operands[1] = force_reg (DFmode, operands[1]); | |
c7453384 | 2994 | emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1], |
9db1d521 | 2995 | two31r, two32, temp)); |
c7453384 EC |
2996 | } |
2997 | else | |
9db1d521 HP |
2998 | { |
2999 | operands[1] = force_reg (DFmode, operands[1]); | |
3000 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
3001 | } | |
3002 | ||
3003 | DONE; | |
10bbf137 | 3004 | }) |
9db1d521 HP |
3005 | |
3006 | (define_insn "fix_truncdfsi2_ieee" | |
3007 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3008 | (fix:SI (match_operand:DF 1 "register_operand" "f"))) | |
10bbf137 | 3009 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
3010 | (clobber (reg:CC 33))] |
3011 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 3012 | "cfdbr\t%0,%h2,%1" |
9db1d521 | 3013 | [(set_attr "op_type" "RRE") |
4023fb28 | 3014 | (set_attr "type" "other" )]) |
9db1d521 HP |
3015 | |
3016 | (define_insn "fix_truncdfsi2_ibm" | |
3017 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3018 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f"))) | |
4023fb28 UW |
3019 | (use (match_operand:DI 2 "immediate_operand" "m")) |
3020 | (use (match_operand:DI 3 "immediate_operand" "m")) | |
9db1d521 HP |
3021 | (use (match_operand:BLK 4 "memory_operand" "m")) |
3022 | (clobber (reg:CC 33))] | |
3023 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
9db1d521 | 3024 | { |
d40c829f UW |
3025 | output_asm_insn ("sd\t%1,%2", operands); |
3026 | output_asm_insn ("aw\t%1,%3", operands); | |
3027 | output_asm_insn ("std\t%1,%4", operands); | |
3028 | output_asm_insn ("xi\t%N4,128", operands); | |
3029 | return "l\t%0,%N4"; | |
10bbf137 | 3030 | } |
9db1d521 | 3031 | [(set_attr "op_type" "NN") |
077dab3b HP |
3032 | (set_attr "type" "ftoi") |
3033 | (set_attr "atype" "agen") | |
9db1d521 HP |
3034 | (set_attr "length" "20")]) |
3035 | ||
3036 | ; | |
3037 | ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s). | |
3038 | ; | |
3039 | ||
3040 | (define_expand "fixuns_truncsfdi2" | |
3041 | [(set (match_operand:DI 0 "register_operand" "") | |
3042 | (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))] | |
3043 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
3044 | { |
3045 | rtx label1 = gen_label_rtx (); | |
3046 | rtx label2 = gen_label_rtx (); | |
3047 | rtx temp = gen_reg_rtx (SFmode); | |
3048 | ||
3049 | operands[1] = force_reg (SFmode, operands[1]); | |
c7453384 | 3050 | emit_insn (gen_cmpsf (operands[1], |
4023fb28 | 3051 | CONST_DOUBLE_FROM_REAL_VALUE ( |
10bbf137 | 3052 | REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode))); |
9db1d521 HP |
3053 | emit_jump_insn (gen_blt (label1)); |
3054 | ||
4023fb28 UW |
3055 | emit_insn (gen_subsf3 (temp, operands[1], |
3056 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 3057 | REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode))); |
9db1d521 | 3058 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7))); |
f314b9b1 | 3059 | emit_jump (label2); |
9db1d521 HP |
3060 | |
3061 | emit_label (label1); | |
3062 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
3063 | emit_label (label2); | |
3064 | DONE; | |
10bbf137 | 3065 | }) |
9db1d521 HP |
3066 | |
3067 | (define_expand "fix_truncsfdi2" | |
3068 | [(set (match_operand:DI 0 "register_operand" "") | |
3069 | (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
3070 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
3071 | { |
3072 | operands[1] = force_reg (SFmode, operands[1]); | |
3073 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
3074 | DONE; | |
10bbf137 | 3075 | }) |
9db1d521 HP |
3076 | |
3077 | (define_insn "fix_truncsfdi2_ieee" | |
3078 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3079 | (fix:DI (match_operand:SF 1 "register_operand" "f"))) | |
10bbf137 | 3080 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
3081 | (clobber (reg:CC 33))] |
3082 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 3083 | "cgebr\t%0,%h2,%1" |
9db1d521 | 3084 | [(set_attr "op_type" "RRE") |
077dab3b | 3085 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
3086 | |
3087 | ; | |
3088 | ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s). | |
3089 | ; | |
3090 | ||
3091 | (define_expand "fixuns_truncsfsi2" | |
3092 | [(set (match_operand:SI 0 "register_operand" "") | |
3093 | (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))] | |
3094 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
3095 | { |
3096 | rtx label1 = gen_label_rtx (); | |
3097 | rtx label2 = gen_label_rtx (); | |
3098 | rtx temp = gen_reg_rtx (SFmode); | |
3099 | ||
3100 | operands[1] = force_reg (SFmode, operands[1]); | |
4023fb28 UW |
3101 | emit_insn (gen_cmpsf (operands[1], |
3102 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 3103 | REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode))); |
9db1d521 | 3104 | emit_jump_insn (gen_blt (label1)); |
4023fb28 UW |
3105 | emit_insn (gen_subsf3 (temp, operands[1], |
3106 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
10bbf137 | 3107 | REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode))); |
9db1d521 | 3108 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7))); |
f314b9b1 | 3109 | emit_jump (label2); |
9db1d521 HP |
3110 | |
3111 | emit_label (label1); | |
3112 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
3113 | emit_label (label2); | |
3114 | DONE; | |
10bbf137 | 3115 | }) |
9db1d521 HP |
3116 | |
3117 | (define_expand "fix_truncsfsi2" | |
3118 | [(set (match_operand:SI 0 "register_operand" "") | |
3119 | (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
3120 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
3121 | { |
3122 | if (TARGET_IBM_FLOAT) | |
3123 | { | |
3124 | /* Convert to DFmode and then use the POP algorithm. */ | |
3125 | rtx temp = gen_reg_rtx (DFmode); | |
3126 | emit_insn (gen_extendsfdf2 (temp, operands[1])); | |
3127 | emit_insn (gen_fix_truncdfsi2 (operands[0], temp)); | |
3128 | } | |
3129 | else | |
3130 | { | |
3131 | operands[1] = force_reg (SFmode, operands[1]); | |
3132 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
3133 | } | |
3134 | ||
3135 | DONE; | |
10bbf137 | 3136 | }) |
9db1d521 HP |
3137 | |
3138 | (define_insn "fix_truncsfsi2_ieee" | |
3139 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3140 | (fix:SI (match_operand:SF 1 "register_operand" "f"))) | |
10bbf137 | 3141 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND) |
9db1d521 HP |
3142 | (clobber (reg:CC 33))] |
3143 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 3144 | "cfebr\t%0,%h2,%1" |
9db1d521 | 3145 | [(set_attr "op_type" "RRE") |
077dab3b | 3146 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
3147 | |
3148 | ; | |
3149 | ; floatdidf2 instruction pattern(s). | |
3150 | ; | |
3151 | ||
3152 | (define_insn "floatdidf2" | |
3153 | [(set (match_operand:DF 0 "register_operand" "=f") | |
4023fb28 UW |
3154 | (float:DF (match_operand:DI 1 "register_operand" "d"))) |
3155 | (clobber (reg:CC 33))] | |
9db1d521 | 3156 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3157 | "cdgbr\t%0,%1" |
9db1d521 | 3158 | [(set_attr "op_type" "RRE") |
f0bf1270 | 3159 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3160 | |
3161 | ; | |
3162 | ; floatdisf2 instruction pattern(s). | |
3163 | ; | |
3164 | ||
3165 | (define_insn "floatdisf2" | |
3166 | [(set (match_operand:SF 0 "register_operand" "=f") | |
4023fb28 UW |
3167 | (float:SF (match_operand:DI 1 "register_operand" "d"))) |
3168 | (clobber (reg:CC 33))] | |
9db1d521 | 3169 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3170 | "cegbr\t%0,%1" |
9db1d521 | 3171 | [(set_attr "op_type" "RRE") |
077dab3b | 3172 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3173 | |
3174 | ; | |
3175 | ; floatsidf2 instruction pattern(s). | |
3176 | ; | |
3177 | ||
3178 | (define_expand "floatsidf2" | |
4023fb28 UW |
3179 | [(parallel |
3180 | [(set (match_operand:DF 0 "register_operand" "") | |
3181 | (float:DF (match_operand:SI 1 "register_operand" ""))) | |
3182 | (clobber (reg:CC 33))])] | |
9db1d521 | 3183 | "TARGET_HARD_FLOAT" |
9db1d521 | 3184 | { |
c7453384 | 3185 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
3186 | { |
3187 | /* This is the algorithm from POP chapter A.5.7.1. */ | |
3188 | ||
c19ec8f9 | 3189 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
c7453384 | 3190 | rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000); |
9db1d521 HP |
3191 | |
3192 | emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp)); | |
3193 | DONE; | |
3194 | } | |
10bbf137 | 3195 | }) |
9db1d521 HP |
3196 | |
3197 | (define_insn "floatsidf2_ieee" | |
3198 | [(set (match_operand:DF 0 "register_operand" "=f") | |
4023fb28 UW |
3199 | (float:DF (match_operand:SI 1 "register_operand" "d"))) |
3200 | (clobber (reg:CC 33))] | |
9db1d521 | 3201 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3202 | "cdfbr\t%0,%1" |
9db1d521 | 3203 | [(set_attr "op_type" "RRE") |
077dab3b | 3204 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3205 | |
3206 | (define_insn "floatsidf2_ibm" | |
3207 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3208 | (float:DF (match_operand:SI 1 "register_operand" "d"))) | |
4023fb28 | 3209 | (use (match_operand:DI 2 "immediate_operand" "m")) |
9db1d521 HP |
3210 | (use (match_operand:BLK 3 "memory_operand" "m")) |
3211 | (clobber (reg:CC 33))] | |
3212 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
9db1d521 | 3213 | { |
d40c829f UW |
3214 | output_asm_insn ("st\t%1,%N3", operands); |
3215 | output_asm_insn ("xi\t%N3,128", operands); | |
3216 | output_asm_insn ("mvc\t%O3(4,%R3),%2", operands); | |
3217 | output_asm_insn ("ld\t%0,%3", operands); | |
3218 | return "sd\t%0,%2"; | |
10bbf137 | 3219 | } |
9db1d521 | 3220 | [(set_attr "op_type" "NN") |
4023fb28 | 3221 | (set_attr "type" "other" ) |
077dab3b | 3222 | (set_attr "atype" "agen") |
9db1d521 HP |
3223 | (set_attr "length" "20")]) |
3224 | ||
3225 | ; | |
3226 | ; floatsisf2 instruction pattern(s). | |
3227 | ; | |
3228 | ||
3229 | (define_expand "floatsisf2" | |
4023fb28 UW |
3230 | [(parallel |
3231 | [(set (match_operand:SF 0 "register_operand" "") | |
3232 | (float:SF (match_operand:SI 1 "register_operand" ""))) | |
3233 | (clobber (reg:CC 33))])] | |
9db1d521 | 3234 | "TARGET_HARD_FLOAT" |
9db1d521 HP |
3235 | { |
3236 | if (TARGET_IBM_FLOAT) | |
3237 | { | |
3238 | /* Use the POP algorithm to convert to DFmode and then truncate. */ | |
3239 | rtx temp = gen_reg_rtx (DFmode); | |
3240 | emit_insn (gen_floatsidf2 (temp, operands[1])); | |
3241 | emit_insn (gen_truncdfsf2 (operands[0], temp)); | |
3242 | DONE; | |
3243 | } | |
10bbf137 | 3244 | }) |
9db1d521 HP |
3245 | |
3246 | (define_insn "floatsisf2_ieee" | |
3247 | [(set (match_operand:SF 0 "register_operand" "=f") | |
4023fb28 UW |
3248 | (float:SF (match_operand:SI 1 "register_operand" "d"))) |
3249 | (clobber (reg:CC 33))] | |
9db1d521 | 3250 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3251 | "cefbr\t%0,%1" |
9db1d521 | 3252 | [(set_attr "op_type" "RRE") |
077dab3b | 3253 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3254 | |
3255 | ; | |
3256 | ; truncdfsf2 instruction pattern(s). | |
3257 | ; | |
3258 | ||
3259 | (define_expand "truncdfsf2" | |
3260 | [(set (match_operand:SF 0 "register_operand" "") | |
3261 | (float_truncate:SF (match_operand:DF 1 "general_operand" "")))] | |
3262 | "TARGET_HARD_FLOAT" | |
4023fb28 | 3263 | "") |
9db1d521 HP |
3264 | |
3265 | (define_insn "truncdfsf2_ieee" | |
3266 | [(set (match_operand:SF 0 "register_operand" "=f") | |
4023fb28 | 3267 | (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))] |
9db1d521 | 3268 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3269 | "ledbr\t%0,%1" |
ce50cae8 | 3270 | [(set_attr "op_type" "RRE")]) |
9db1d521 HP |
3271 | |
3272 | (define_insn "truncdfsf2_ibm" | |
3273 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
d3632d41 | 3274 | (float_truncate:SF (match_operand:DF 1 "general_operand" "f,R")))] |
9db1d521 HP |
3275 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
3276 | "@ | |
d40c829f UW |
3277 | lrer\t%0,%1 |
3278 | le\t%0,%1" | |
4023fb28 | 3279 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3280 | (set_attr "type" "floads,floads")]) |
9db1d521 HP |
3281 | |
3282 | ; | |
3283 | ; extendsfdf2 instruction pattern(s). | |
3284 | ; | |
3285 | ||
3286 | (define_expand "extendsfdf2" | |
3287 | [(set (match_operand:DF 0 "register_operand" "") | |
3288 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] | |
3289 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
3290 | { |
3291 | if (TARGET_IBM_FLOAT) | |
3292 | { | |
3293 | emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1])); | |
3294 | DONE; | |
3295 | } | |
10bbf137 | 3296 | }) |
9db1d521 HP |
3297 | |
3298 | (define_insn "extendsfdf2_ieee" | |
3299 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 3300 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))] |
9db1d521 HP |
3301 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3302 | "@ | |
d40c829f UW |
3303 | ldebr\t%0,%1 |
3304 | ldeb\t%0,%1" | |
077dab3b HP |
3305 | [(set_attr "op_type" "RRE,RXE") |
3306 | (set_attr "type" "floads,floads")]) | |
9db1d521 HP |
3307 | |
3308 | (define_insn "extendsfdf2_ibm" | |
3309 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 3310 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R"))) |
9db1d521 HP |
3311 | (clobber (reg:CC 33))] |
3312 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3313 | "@ | |
d40c829f UW |
3314 | sdr\t%0,%0\;ler\t%0,%1 |
3315 | sdr\t%0,%0\;le\t%0,%1" | |
077dab3b HP |
3316 | [(set_attr "op_type" "NN,NN") |
3317 | (set_attr "atype" "reg,agen") | |
3318 | (set_attr "length" "4,6") | |
c7453384 | 3319 | (set_attr "type" "o2,o2")]) |
9db1d521 HP |
3320 | |
3321 | ||
3322 | ;; | |
fae778eb | 3323 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 3324 | ;; |
fae778eb | 3325 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
3326 | ; because of unpredictable Bits in Register for Halfword and Byte |
3327 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
3328 | ||
07893d4f UW |
3329 | ;; |
3330 | ;;- Add instructions. | |
3331 | ;; | |
3332 | ||
1c7b1b7e UW |
3333 | ; |
3334 | ; addti3 instruction pattern(s). | |
3335 | ; | |
3336 | ||
3337 | (define_insn_and_split "addti3" | |
3338 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
3339 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") | |
3340 | (match_operand:TI 2 "general_operand" "do") ) ) | |
3341 | (clobber (reg:CC 33))] | |
3342 | "TARGET_64BIT" | |
3343 | "#" | |
3344 | "&& reload_completed" | |
3345 | [(parallel | |
3346 | [(set (reg:CCL1 33) | |
3347 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) | |
3348 | (match_dup 7))) | |
3349 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
3350 | (parallel | |
3351 | [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5)) | |
3352 | (ltu:DI (reg:CCL1 33) (const_int 0)))) | |
3353 | (clobber (reg:CC 33))])] | |
3354 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
3355 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
3356 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
3357 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
3358 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
3359 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" | |
3360 | [(set_attr "op_type" "NN")]) | |
3361 | ||
07893d4f UW |
3362 | ; |
3363 | ; adddi3 instruction pattern(s). | |
3364 | ; | |
3365 | ||
07893d4f UW |
3366 | (define_insn "*adddi3_sign" |
3367 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3368 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3369 | (match_operand:DI 1 "register_operand" "0,0"))) | |
3370 | (clobber (reg:CC 33))] | |
3371 | "TARGET_64BIT" | |
3372 | "@ | |
d40c829f UW |
3373 | agfr\t%0,%2 |
3374 | agf\t%0,%2" | |
d3632d41 | 3375 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3376 | |
3377 | (define_insn "*adddi3_zero_cc" | |
c7453384 | 3378 | [(set (reg 33) |
07893d4f UW |
3379 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3380 | (match_operand:DI 1 "register_operand" "0,0")) | |
3381 | (const_int 0))) | |
3382 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3383 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
3384 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3385 | "@ | |
d40c829f UW |
3386 | algfr\t%0,%2 |
3387 | algf\t%0,%2" | |
d3632d41 | 3388 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3389 | |
3390 | (define_insn "*adddi3_zero_cconly" | |
c7453384 | 3391 | [(set (reg 33) |
07893d4f UW |
3392 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3393 | (match_operand:DI 1 "register_operand" "0,0")) | |
3394 | (const_int 0))) | |
3395 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3396 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3397 | "@ | |
d40c829f UW |
3398 | algfr\t%0,%2 |
3399 | algf\t%0,%2" | |
d3632d41 | 3400 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3401 | |
3402 | (define_insn "*adddi3_zero" | |
3403 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3404 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3405 | (match_operand:DI 1 "register_operand" "0,0"))) | |
3406 | (clobber (reg:CC 33))] | |
3407 | "TARGET_64BIT" | |
3408 | "@ | |
d40c829f UW |
3409 | algfr\t%0,%2 |
3410 | algf\t%0,%2" | |
d3632d41 | 3411 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3412 | |
0a3bdf9d | 3413 | (define_insn "*adddi3_imm_cc" |
c7453384 | 3414 | [(set (reg 33) |
0a3bdf9d UW |
3415 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0") |
3416 | (match_operand:DI 2 "const_int_operand" "K")) | |
3417 | (const_int 0))) | |
3418 | (set (match_operand:DI 0 "register_operand" "=d") | |
3419 | (plus:DI (match_dup 1) (match_dup 2)))] | |
c7453384 EC |
3420 | "TARGET_64BIT |
3421 | && s390_match_ccmode (insn, CCAmode) | |
f19a9af7 | 3422 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")" |
d40c829f | 3423 | "aghi\t%0,%h2" |
077dab3b | 3424 | [(set_attr "op_type" "RI")]) |
0a3bdf9d | 3425 | |
b2ba71ca UW |
3426 | (define_insn "*adddi3_carry1_cc" |
3427 | [(set (reg 33) | |
3428 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3429 | (match_operand:DI 2 "general_operand" "d,m")) | |
3430 | (match_dup 1))) | |
3431 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3432 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3433 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3434 | "@ | |
3435 | algr\t%0,%2 | |
3436 | alg\t%0,%2" | |
3437 | [(set_attr "op_type" "RRE,RXY")]) | |
3438 | ||
3439 | (define_insn "*adddi3_carry1_cconly" | |
3440 | [(set (reg 33) | |
3441 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3442 | (match_operand:DI 2 "general_operand" "d,m")) | |
3443 | (match_dup 1))) | |
3444 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3445 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3446 | "@ | |
3447 | algr\t%0,%2 | |
3448 | alg\t%0,%2" | |
3449 | [(set_attr "op_type" "RRE,RXY")]) | |
3450 | ||
3451 | (define_insn "*adddi3_carry2_cc" | |
3452 | [(set (reg 33) | |
3453 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3454 | (match_operand:DI 2 "general_operand" "d,m")) | |
3455 | (match_dup 2))) | |
3456 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3457 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3458 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3459 | "@ | |
3460 | algr\t%0,%2 | |
3461 | alg\t%0,%2" | |
3462 | [(set_attr "op_type" "RRE,RXY")]) | |
3463 | ||
3464 | (define_insn "*adddi3_carry2_cconly" | |
3465 | [(set (reg 33) | |
3466 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
3467 | (match_operand:DI 2 "general_operand" "d,m")) | |
3468 | (match_dup 2))) | |
3469 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3470 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3471 | "@ | |
3472 | algr\t%0,%2 | |
3473 | alg\t%0,%2" | |
3474 | [(set_attr "op_type" "RRE,RXY")]) | |
3475 | ||
07893d4f | 3476 | (define_insn "*adddi3_cc" |
c7453384 | 3477 | [(set (reg 33) |
96fd3851 | 3478 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3479 | (match_operand:DI 2 "general_operand" "d,m")) |
3480 | (const_int 0))) | |
3481 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3482 | (plus:DI (match_dup 1) (match_dup 2)))] | |
3483 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3484 | "@ | |
d40c829f UW |
3485 | algr\t%0,%2 |
3486 | alg\t%0,%2" | |
d3632d41 | 3487 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3488 | |
07893d4f | 3489 | (define_insn "*adddi3_cconly" |
c7453384 | 3490 | [(set (reg 33) |
96fd3851 | 3491 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3492 | (match_operand:DI 2 "general_operand" "d,m")) |
3493 | (const_int 0))) | |
3494 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3495 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3496 | "@ | |
d40c829f UW |
3497 | algr\t%0,%2 |
3498 | alg\t%0,%2" | |
d3632d41 | 3499 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3500 | |
07893d4f | 3501 | (define_insn "*adddi3_cconly2" |
c7453384 | 3502 | [(set (reg 33) |
96fd3851 | 3503 | (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3504 | (neg:SI (match_operand:DI 2 "general_operand" "d,m")))) |
3505 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3506 | "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT" | |
9db1d521 | 3507 | "@ |
d40c829f UW |
3508 | algr\t%0,%2 |
3509 | alg\t%0,%2" | |
d3632d41 | 3510 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3511 | |
07893d4f | 3512 | (define_insn "*adddi3_64" |
9db1d521 | 3513 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
96fd3851 | 3514 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
9db1d521 HP |
3515 | (match_operand:DI 2 "general_operand" "d,K,m") ) ) |
3516 | (clobber (reg:CC 33))] | |
3517 | "TARGET_64BIT" | |
3518 | "@ | |
d40c829f UW |
3519 | agr\t%0,%2 |
3520 | aghi\t%0,%h2 | |
3521 | ag\t%0,%2" | |
d3632d41 | 3522 | [(set_attr "op_type" "RRE,RI,RXY")]) |
9db1d521 | 3523 | |
e69166de UW |
3524 | (define_insn_and_split "*adddi3_31z" |
3525 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3526 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") | |
3527 | (match_operand:DI 2 "general_operand" "do") ) ) | |
3528 | (clobber (reg:CC 33))] | |
3529 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
3530 | "#" | |
3531 | "&& reload_completed" | |
3532 | [(parallel | |
3533 | [(set (reg:CCL1 33) | |
3534 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) | |
3535 | (match_dup 7))) | |
3536 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3537 | (parallel | |
3538 | [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5)) | |
3539 | (ltu:SI (reg:CCL1 33) (const_int 0)))) | |
3540 | (clobber (reg:CC 33))])] | |
3541 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
3542 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3543 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3544 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3545 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3546 | operands[8] = operand_subword (operands[2], 1, 0, DImode);" | |
3547 | [(set_attr "op_type" "NN")]) | |
3548 | ||
07893d4f UW |
3549 | (define_insn_and_split "*adddi3_31" |
3550 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
96fd3851 | 3551 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 3552 | (match_operand:DI 2 "general_operand" "do") ) ) |
9db1d521 | 3553 | (clobber (reg:CC 33))] |
e69166de | 3554 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
3555 | "#" |
3556 | "&& reload_completed" | |
3557 | [(parallel | |
3558 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
3559 | (clobber (reg:CC 33))]) | |
3560 | (parallel | |
3561 | [(set (reg:CCL1 33) | |
3562 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) | |
3563 | (match_dup 7))) | |
3564 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3565 | (set (pc) | |
3566 | (if_then_else (ltu (reg:CCL1 33) (const_int 0)) | |
3567 | (pc) | |
3568 | (label_ref (match_dup 9)))) | |
3569 | (parallel | |
3570 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
3571 | (clobber (reg:CC 33))]) | |
3572 | (match_dup 9)] | |
97c6f7ad UW |
3573 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3574 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3575 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3576 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3577 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3578 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
07893d4f | 3579 | operands[9] = gen_label_rtx ();" |
0796c16a | 3580 | [(set_attr "op_type" "NN")]) |
9db1d521 HP |
3581 | |
3582 | (define_expand "adddi3" | |
07893d4f UW |
3583 | [(parallel |
3584 | [(set (match_operand:DI 0 "register_operand" "") | |
96fd3851 | 3585 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
07893d4f UW |
3586 | (match_operand:DI 2 "general_operand" ""))) |
3587 | (clobber (reg:CC 33))])] | |
9db1d521 | 3588 | "" |
07893d4f | 3589 | "") |
9db1d521 | 3590 | |
9db1d521 HP |
3591 | ; |
3592 | ; addsi3 instruction pattern(s). | |
3593 | ; | |
9db1d521 | 3594 | |
0a3bdf9d | 3595 | (define_insn "*addsi3_imm_cc" |
c7453384 | 3596 | [(set (reg 33) |
0a3bdf9d UW |
3597 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0") |
3598 | (match_operand:SI 2 "const_int_operand" "K")) | |
3599 | (const_int 0))) | |
3600 | (set (match_operand:SI 0 "register_operand" "=d") | |
3601 | (plus:SI (match_dup 1) (match_dup 2)))] | |
3602 | "s390_match_ccmode (insn, CCAmode) | |
f19a9af7 | 3603 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")" |
d40c829f | 3604 | "ahi\t%0,%h2" |
077dab3b | 3605 | [(set_attr "op_type" "RI")]) |
0a3bdf9d | 3606 | |
07893d4f | 3607 | (define_insn "*addsi3_carry1_cc" |
c7453384 | 3608 | [(set (reg 33) |
d3632d41 UW |
3609 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3610 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3611 | (match_dup 1))) |
d3632d41 | 3612 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3613 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3614 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3615 | "@ |
d40c829f UW |
3616 | alr\t%0,%2 |
3617 | al\t%0,%2 | |
3618 | aly\t%0,%2" | |
d3632d41 | 3619 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3620 | |
3621 | (define_insn "*addsi3_carry1_cconly" | |
c7453384 | 3622 | [(set (reg 33) |
d3632d41 UW |
3623 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3624 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3625 | (match_dup 1))) |
d3632d41 | 3626 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3627 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3628 | "@ |
d40c829f UW |
3629 | alr\t%0,%2 |
3630 | al\t%0,%2 | |
3631 | aly\t%0,%2" | |
d3632d41 | 3632 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3633 | |
3634 | (define_insn "*addsi3_carry2_cc" | |
c7453384 | 3635 | [(set (reg 33) |
d3632d41 UW |
3636 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3637 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3638 | (match_dup 2))) |
d3632d41 | 3639 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3640 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3641 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3642 | "@ |
d40c829f UW |
3643 | alr\t%0,%2 |
3644 | al\t%0,%2 | |
3645 | aly\t%0,%2" | |
d3632d41 | 3646 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3647 | |
3648 | (define_insn "*addsi3_carry2_cconly" | |
c7453384 | 3649 | [(set (reg 33) |
d3632d41 UW |
3650 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3651 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3652 | (match_dup 2))) |
d3632d41 | 3653 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3654 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3655 | "@ |
d40c829f UW |
3656 | alr\t%0,%2 |
3657 | al\t%0,%2 | |
3658 | aly\t%0,%2" | |
d3632d41 | 3659 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f | 3660 | |
9db1d521 | 3661 | (define_insn "*addsi3_cc" |
c7453384 | 3662 | [(set (reg 33) |
d3632d41 UW |
3663 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3664 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3665 | (const_int 0))) |
d3632d41 | 3666 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 | 3667 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3668 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3669 | "@ |
d40c829f UW |
3670 | alr\t%0,%2 |
3671 | al\t%0,%2 | |
3672 | aly\t%0,%2" | |
d3632d41 | 3673 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
3674 | |
3675 | (define_insn "*addsi3_cconly" | |
c7453384 | 3676 | [(set (reg 33) |
d3632d41 UW |
3677 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3678 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3679 | (const_int 0))) |
d3632d41 | 3680 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3681 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3682 | "@ |
d40c829f UW |
3683 | alr\t%0,%2 |
3684 | al\t%0,%2 | |
3685 | aly\t%0,%2" | |
d3632d41 | 3686 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
3687 | |
3688 | (define_insn "*addsi3_cconly2" | |
c7453384 | 3689 | [(set (reg 33) |
d3632d41 UW |
3690 | (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3691 | (neg:SI (match_operand:SI 2 "general_operand" "d,R,T")))) | |
3692 | (clobber (match_scratch:SI 0 "=d,d,d"))] | |
b2ba71ca | 3693 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3694 | "@ |
d40c829f UW |
3695 | alr\t%0,%2 |
3696 | al\t%0,%2 | |
3697 | aly\t%0,%2" | |
d3632d41 | 3698 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 3699 | |
07893d4f | 3700 | (define_insn "*addsi3_sign" |
d3632d41 UW |
3701 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
3702 | (plus:SI (match_operand:SI 1 "register_operand" "0,0") | |
3703 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
07893d4f UW |
3704 | (clobber (reg:CC 33))] |
3705 | "" | |
d3632d41 | 3706 | "@ |
d40c829f UW |
3707 | ah\t%0,%2 |
3708 | ahy\t%0,%2" | |
d3632d41 | 3709 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f | 3710 | |
9db1d521 | 3711 | (define_insn "addsi3" |
d3632d41 UW |
3712 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
3713 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
3714 | (match_operand:SI 2 "general_operand" "d,K,R,T"))) | |
9db1d521 HP |
3715 | (clobber (reg:CC 33))] |
3716 | "" | |
3717 | "@ | |
d40c829f UW |
3718 | ar\t%0,%2 |
3719 | ahi\t%0,%h2 | |
3720 | a\t%0,%2 | |
3721 | ay\t%0,%2" | |
d3632d41 | 3722 | [(set_attr "op_type" "RR,RI,RX,RXY")]) |
9db1d521 | 3723 | |
9db1d521 HP |
3724 | ; |
3725 | ; adddf3 instruction pattern(s). | |
3726 | ; | |
3727 | ||
3728 | (define_expand "adddf3" | |
3729 | [(parallel | |
3730 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3731 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3732 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3733 | (clobber (reg:CC 33))])] |
3734 | "TARGET_HARD_FLOAT" | |
3735 | "") | |
3736 | ||
3737 | (define_insn "*adddf3" | |
3738 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3739 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3740 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3741 | (clobber (reg:CC 33))] |
3742 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3743 | "@ | |
d40c829f UW |
3744 | adbr\t%0,%2 |
3745 | adb\t%0,%2" | |
ce50cae8 | 3746 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 3747 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 | 3748 | |
3ef093a8 AK |
3749 | (define_insn "*adddf3_cc" |
3750 | [(set (reg 33) | |
3751 | (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
3752 | (match_operand:DF 2 "general_operand" "f,R")) | |
3753 | (match_operand:DF 3 "const0_operand" ""))) | |
3754 | (set (match_operand:DF 0 "register_operand" "=f,f") | |
3755 | (plus:DF (match_dup 1) (match_dup 2)))] | |
3756 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3757 | "@ | |
d40c829f UW |
3758 | adbr\t%0,%2 |
3759 | adb\t%0,%2" | |
3ef093a8 AK |
3760 | [(set_attr "op_type" "RRE,RXE") |
3761 | (set_attr "type" "fsimpd,fsimpd")]) | |
3762 | ||
3763 | (define_insn "*adddf3_cconly" | |
3764 | [(set (reg 33) | |
3765 | (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
3766 | (match_operand:DF 2 "general_operand" "f,R")) | |
3767 | (match_operand:DF 3 "const0_operand" ""))) | |
3768 | (clobber (match_scratch:DF 0 "=f,f"))] | |
3769 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3770 | "@ | |
d40c829f UW |
3771 | adbr\t%0,%2 |
3772 | adb\t%0,%2" | |
3ef093a8 AK |
3773 | [(set_attr "op_type" "RRE,RXE") |
3774 | (set_attr "type" "fsimpd,fsimpd")]) | |
3775 | ||
9db1d521 HP |
3776 | (define_insn "*adddf3_ibm" |
3777 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 3778 | (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3779 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3780 | (clobber (reg:CC 33))] |
3781 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3782 | "@ | |
d40c829f UW |
3783 | adr\t%0,%2 |
3784 | ad\t%0,%2" | |
9db1d521 | 3785 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3786 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 HP |
3787 | |
3788 | ; | |
3789 | ; addsf3 instruction pattern(s). | |
3790 | ; | |
3791 | ||
3792 | (define_expand "addsf3" | |
3793 | [(parallel | |
3794 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3795 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3796 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3797 | (clobber (reg:CC 33))])] |
3798 | "TARGET_HARD_FLOAT" | |
3799 | "") | |
3800 | ||
3801 | (define_insn "*addsf3" | |
3802 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3803 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3804 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3805 | (clobber (reg:CC 33))] |
3806 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3807 | "@ | |
d40c829f UW |
3808 | aebr\t%0,%2 |
3809 | aeb\t%0,%2" | |
ce50cae8 | 3810 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 3811 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 | 3812 | |
3ef093a8 AK |
3813 | (define_insn "*addsf3_cc" |
3814 | [(set (reg 33) | |
3815 | (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
3816 | (match_operand:SF 2 "general_operand" "f,R")) | |
3817 | (match_operand:SF 3 "const0_operand" ""))) | |
3818 | (set (match_operand:SF 0 "register_operand" "=f,f") | |
3819 | (plus:SF (match_dup 1) (match_dup 2)))] | |
3820 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3821 | "@ | |
d40c829f UW |
3822 | aebr\t%0,%2 |
3823 | aeb\t%0,%2" | |
3ef093a8 AK |
3824 | [(set_attr "op_type" "RRE,RXE") |
3825 | (set_attr "type" "fsimps,fsimps")]) | |
3826 | ||
3827 | (define_insn "*addsf3_cconly" | |
3828 | [(set (reg 33) | |
3829 | (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
3830 | (match_operand:SF 2 "general_operand" "f,R")) | |
3831 | (match_operand:SF 3 "const0_operand" ""))) | |
3832 | (clobber (match_scratch:SF 0 "=f,f"))] | |
3833 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
3834 | "@ | |
d40c829f UW |
3835 | aebr\t%0,%2 |
3836 | aeb\t%0,%2" | |
3ef093a8 AK |
3837 | [(set_attr "op_type" "RRE,RXE") |
3838 | (set_attr "type" "fsimps,fsimps")]) | |
3839 | ||
9db1d521 HP |
3840 | (define_insn "*addsf3" |
3841 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 3842 | (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
d3632d41 | 3843 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
3844 | (clobber (reg:CC 33))] |
3845 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
3846 | "@ | |
d40c829f UW |
3847 | aer\t%0,%2 |
3848 | ae\t%0,%2" | |
9db1d521 | 3849 | [(set_attr "op_type" "RR,RX") |
077dab3b | 3850 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 HP |
3851 | |
3852 | ||
3853 | ;; | |
3854 | ;;- Subtract instructions. | |
3855 | ;; | |
3856 | ||
1c7b1b7e UW |
3857 | ; |
3858 | ; subti3 instruction pattern(s). | |
3859 | ; | |
3860 | ||
3861 | (define_insn_and_split "subti3" | |
3862 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
3863 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
3864 | (match_operand:TI 2 "general_operand" "do") ) ) | |
3865 | (clobber (reg:CC 33))] | |
3866 | "TARGET_64BIT" | |
3867 | "#" | |
3868 | "&& reload_completed" | |
3869 | [(parallel | |
3870 | [(set (reg:CCL2 33) | |
3871 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) | |
3872 | (match_dup 7))) | |
3873 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
3874 | (parallel | |
3875 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
3876 | (gtu:DI (reg:CCL2 33) (const_int 0)))) | |
3877 | (clobber (reg:CC 33))])] | |
3878 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
3879 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
3880 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
3881 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
3882 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
3883 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" | |
3884 | [(set_attr "op_type" "NN")]) | |
3885 | ||
9db1d521 HP |
3886 | ; |
3887 | ; subdi3 instruction pattern(s). | |
3888 | ; | |
3889 | ||
07893d4f UW |
3890 | (define_insn "*subdi3_sign" |
3891 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3892 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3893 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
3894 | (clobber (reg:CC 33))] | |
3895 | "TARGET_64BIT" | |
3896 | "@ | |
d40c829f UW |
3897 | sgfr\t%0,%2 |
3898 | sgf\t%0,%2" | |
d3632d41 | 3899 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3900 | |
3901 | (define_insn "*subdi3_zero_cc" | |
c7453384 | 3902 | [(set (reg 33) |
07893d4f UW |
3903 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3904 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3905 | (const_int 0))) | |
3906 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3907 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
3908 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3909 | "@ | |
d40c829f UW |
3910 | slgfr\t%0,%2 |
3911 | slgf\t%0,%2" | |
d3632d41 | 3912 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3913 | |
3914 | (define_insn "*subdi3_zero_cconly" | |
c7453384 | 3915 | [(set (reg 33) |
07893d4f UW |
3916 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3917 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3918 | (const_int 0))) | |
3919 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3920 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3921 | "@ | |
d40c829f UW |
3922 | slgfr\t%0,%2 |
3923 | slgf\t%0,%2" | |
d3632d41 | 3924 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3925 | |
3926 | (define_insn "*subdi3_zero" | |
3927 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3928 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3929 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
3930 | (clobber (reg:CC 33))] | |
3931 | "TARGET_64BIT" | |
3932 | "@ | |
d40c829f UW |
3933 | slgfr\t%0,%2 |
3934 | slgf\t%0,%2" | |
d3632d41 | 3935 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3936 | |
b2ba71ca UW |
3937 | (define_insn "*subdi3_borrow_cc" |
3938 | [(set (reg 33) | |
3939 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3940 | (match_operand:DI 2 "general_operand" "d,m")) | |
3941 | (match_dup 1))) | |
3942 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3943 | (minus:DI (match_dup 1) (match_dup 2)))] | |
3944 | "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" | |
3945 | "@ | |
3946 | slgr\t%0,%2 | |
3947 | slg\t%0,%2" | |
3948 | [(set_attr "op_type" "RRE,RXY")]) | |
3949 | ||
3950 | (define_insn "*subdi3_borrow_cconly" | |
3951 | [(set (reg 33) | |
3952 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3953 | (match_operand:DI 2 "general_operand" "d,m")) | |
3954 | (match_dup 1))) | |
3955 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3956 | "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" | |
3957 | "@ | |
3958 | slgr\t%0,%2 | |
3959 | slg\t%0,%2" | |
3960 | [(set_attr "op_type" "RRE,RXY")]) | |
3961 | ||
07893d4f UW |
3962 | (define_insn "*subdi3_cc" |
3963 | [(set (reg 33) | |
3964 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3965 | (match_operand:DI 2 "general_operand" "d,m")) | |
3966 | (const_int 0))) | |
3967 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3968 | (minus:DI (match_dup 1) (match_dup 2)))] | |
b2ba71ca | 3969 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
07893d4f | 3970 | "@ |
d40c829f UW |
3971 | slgr\t%0,%2 |
3972 | slg\t%0,%2" | |
d3632d41 | 3973 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3974 | |
3975 | (define_insn "*subdi3_cconly" | |
3976 | [(set (reg 33) | |
3977 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3978 | (match_operand:DI 2 "general_operand" "d,m")) | |
3979 | (const_int 0))) | |
3980 | (clobber (match_scratch:DI 0 "=d,d"))] | |
b2ba71ca | 3981 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
07893d4f | 3982 | "@ |
d40c829f UW |
3983 | slgr\t%0,%2 |
3984 | slg\t%0,%2" | |
d3632d41 | 3985 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3986 | |
9db1d521 HP |
3987 | (define_insn "*subdi3_64" |
3988 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3989 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3990 | (match_operand:DI 2 "general_operand" "d,m") ) ) | |
3991 | (clobber (reg:CC 33))] | |
3992 | "TARGET_64BIT" | |
3993 | "@ | |
d40c829f UW |
3994 | sgr\t%0,%2 |
3995 | sg\t%0,%2" | |
077dab3b | 3996 | [(set_attr "op_type" "RRE,RRE")]) |
9db1d521 | 3997 | |
e69166de UW |
3998 | (define_insn_and_split "*subdi3_31z" |
3999 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
4000 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
4001 | (match_operand:DI 2 "general_operand" "do") ) ) | |
4002 | (clobber (reg:CC 33))] | |
4003 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4004 | "#" | |
4005 | "&& reload_completed" | |
4006 | [(parallel | |
4007 | [(set (reg:CCL2 33) | |
4008 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) | |
4009 | (match_dup 7))) | |
4010 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
4011 | (parallel | |
4012 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
4013 | (gtu:SI (reg:CCL2 33) (const_int 0)))) | |
4014 | (clobber (reg:CC 33))])] | |
4015 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
4016 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4017 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4018 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4019 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4020 | operands[8] = operand_subword (operands[2], 1, 0, DImode);" | |
4021 | [(set_attr "op_type" "NN")]) | |
4022 | ||
07893d4f UW |
4023 | (define_insn_and_split "*subdi3_31" |
4024 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
4025 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 4026 | (match_operand:DI 2 "general_operand" "do") ) ) |
9db1d521 | 4027 | (clobber (reg:CC 33))] |
e69166de | 4028 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
4029 | "#" |
4030 | "&& reload_completed" | |
4031 | [(parallel | |
4032 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
4033 | (clobber (reg:CC 33))]) | |
4034 | (parallel | |
4035 | [(set (reg:CCL2 33) | |
4036 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) | |
4037 | (match_dup 7))) | |
4038 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
4039 | (set (pc) | |
4040 | (if_then_else (gtu (reg:CCL2 33) (const_int 0)) | |
4041 | (pc) | |
4042 | (label_ref (match_dup 9)))) | |
4043 | (parallel | |
4044 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
4045 | (clobber (reg:CC 33))]) | |
4046 | (match_dup 9)] | |
97c6f7ad UW |
4047 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
4048 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
4049 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
4050 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
4051 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
4052 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
07893d4f | 4053 | operands[9] = gen_label_rtx ();" |
0796c16a | 4054 | [(set_attr "op_type" "NN")]) |
07893d4f UW |
4055 | |
4056 | (define_expand "subdi3" | |
4057 | [(parallel | |
4058 | [(set (match_operand:DI 0 "register_operand" "") | |
4059 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
4060 | (match_operand:DI 2 "general_operand" ""))) | |
4061 | (clobber (reg:CC 33))])] | |
9db1d521 | 4062 | "" |
07893d4f | 4063 | "") |
9db1d521 HP |
4064 | |
4065 | ; | |
4066 | ; subsi3 instruction pattern(s). | |
4067 | ; | |
4068 | ||
07893d4f UW |
4069 | (define_insn "*subsi3_borrow_cc" |
4070 | [(set (reg 33) | |
d3632d41 UW |
4071 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
4072 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 4073 | (match_dup 1))) |
d3632d41 | 4074 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 4075 | (minus:SI (match_dup 1) (match_dup 2)))] |
b2ba71ca | 4076 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 4077 | "@ |
d40c829f UW |
4078 | slr\t%0,%2 |
4079 | sl\t%0,%2 | |
4080 | sly\t%0,%2" | |
d3632d41 | 4081 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
4082 | |
4083 | (define_insn "*subsi3_borrow_cconly" | |
4084 | [(set (reg 33) | |
d3632d41 UW |
4085 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
4086 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 4087 | (match_dup 1))) |
d3632d41 | 4088 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
b2ba71ca | 4089 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 4090 | "@ |
d40c829f UW |
4091 | slr\t%0,%2 |
4092 | sl\t%0,%2 | |
4093 | sly\t%0,%2" | |
b2ba71ca | 4094 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f | 4095 | |
9db1d521 HP |
4096 | (define_insn "*subsi3_cc" |
4097 | [(set (reg 33) | |
d3632d41 UW |
4098 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
4099 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 4100 | (const_int 0))) |
d3632d41 | 4101 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 | 4102 | (minus:SI (match_dup 1) (match_dup 2)))] |
b2ba71ca | 4103 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4104 | "@ |
d40c829f UW |
4105 | slr\t%0,%2 |
4106 | sl\t%0,%2 | |
4107 | sly\t%0,%2" | |
d3632d41 | 4108 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
4109 | |
4110 | (define_insn "*subsi3_cconly" | |
4111 | [(set (reg 33) | |
d3632d41 UW |
4112 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
4113 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 4114 | (const_int 0))) |
d3632d41 | 4115 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
b2ba71ca | 4116 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4117 | "@ |
d40c829f UW |
4118 | slr\t%0,%2 |
4119 | sl\t%0,%2 | |
4120 | sly\t%0,%2" | |
d3632d41 | 4121 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 4122 | |
07893d4f | 4123 | (define_insn "*subsi3_sign" |
d3632d41 UW |
4124 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4125 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
4126 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
07893d4f UW |
4127 | (clobber (reg:CC 33))] |
4128 | "" | |
d3632d41 | 4129 | "@ |
d40c829f UW |
4130 | sh\t%0,%2 |
4131 | shy\t%0,%2" | |
d3632d41 | 4132 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f | 4133 | |
9db1d521 | 4134 | (define_insn "subsi3" |
d3632d41 UW |
4135 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
4136 | (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") | |
4137 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
9db1d521 HP |
4138 | (clobber (reg:CC 33))] |
4139 | "" | |
4140 | "@ | |
d40c829f UW |
4141 | sr\t%0,%2 |
4142 | s\t%0,%2 | |
4143 | sy\t%0,%2" | |
d3632d41 | 4144 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 4145 | |
9db1d521 HP |
4146 | |
4147 | ; | |
4148 | ; subdf3 instruction pattern(s). | |
4149 | ; | |
4150 | ||
4151 | (define_expand "subdf3" | |
4152 | [(parallel | |
4153 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4154 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 4155 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4156 | (clobber (reg:CC 33))])] |
4157 | "TARGET_HARD_FLOAT" | |
4158 | "") | |
4159 | ||
4160 | (define_insn "*subdf3" | |
4161 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4162 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 4163 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4164 | (clobber (reg:CC 33))] |
4165 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4166 | "@ | |
d40c829f UW |
4167 | sdbr\t%0,%2 |
4168 | sdb\t%0,%2" | |
ce50cae8 | 4169 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4170 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 | 4171 | |
3ef093a8 AK |
4172 | (define_insn "*subdf3_cc" |
4173 | [(set (reg 33) | |
4dbb5970 | 4174 | (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0") |
3ef093a8 AK |
4175 | (match_operand:DF 2 "general_operand" "f,R")) |
4176 | (match_operand:DF 3 "const0_operand" ""))) | |
4177 | (set (match_operand:DF 0 "register_operand" "=f,f") | |
4178 | (plus:DF (match_dup 1) (match_dup 2)))] | |
4179 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4180 | "@ | |
d40c829f UW |
4181 | sdbr\t%0,%2 |
4182 | sdb\t%0,%2" | |
3ef093a8 AK |
4183 | [(set_attr "op_type" "RRE,RXE") |
4184 | (set_attr "type" "fsimpd,fsimpd")]) | |
4185 | ||
4186 | (define_insn "*subdf3_cconly" | |
4187 | [(set (reg 33) | |
4dbb5970 | 4188 | (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0") |
3ef093a8 AK |
4189 | (match_operand:DF 2 "general_operand" "f,R")) |
4190 | (match_operand:DF 3 "const0_operand" ""))) | |
4191 | (clobber (match_scratch:DF 0 "=f,f"))] | |
4192 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4193 | "@ | |
d40c829f UW |
4194 | sdbr\t%0,%2 |
4195 | sdb\t%0,%2" | |
3ef093a8 AK |
4196 | [(set_attr "op_type" "RRE,RXE") |
4197 | (set_attr "type" "fsimpd,fsimpd")]) | |
4198 | ||
9db1d521 HP |
4199 | (define_insn "*subdf3_ibm" |
4200 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4201 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
d3632d41 | 4202 | (match_operand:DF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4203 | (clobber (reg:CC 33))] |
4204 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
4205 | "@ | |
d40c829f UW |
4206 | sdr\t%0,%2 |
4207 | sd\t%0,%2" | |
9db1d521 | 4208 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4209 | (set_attr "type" "fsimpd,fsimpd")]) |
9db1d521 HP |
4210 | |
4211 | ; | |
4212 | ; subsf3 instruction pattern(s). | |
4213 | ; | |
4214 | ||
4215 | (define_expand "subsf3" | |
4216 | [(parallel | |
4217 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4218 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4219 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4220 | (clobber (reg:CC 33))])] |
4221 | "TARGET_HARD_FLOAT" | |
4222 | "") | |
4223 | ||
4224 | (define_insn "*subsf3" | |
4225 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4226 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4227 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4228 | (clobber (reg:CC 33))] |
4229 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4230 | "@ | |
d40c829f UW |
4231 | sebr\t%0,%2 |
4232 | seb\t%0,%2" | |
ce50cae8 | 4233 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4234 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 | 4235 | |
3ef093a8 AK |
4236 | (define_insn "*subsf3_cc" |
4237 | [(set (reg 33) | |
4dbb5970 | 4238 | (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0") |
3ef093a8 AK |
4239 | (match_operand:SF 2 "general_operand" "f,R")) |
4240 | (match_operand:SF 3 "const0_operand" ""))) | |
4241 | (set (match_operand:SF 0 "register_operand" "=f,f") | |
4242 | (minus:SF (match_dup 1) (match_dup 2)))] | |
4243 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4244 | "@ | |
d40c829f UW |
4245 | sebr\t%0,%2 |
4246 | seb\t%0,%2" | |
3ef093a8 AK |
4247 | [(set_attr "op_type" "RRE,RXE") |
4248 | (set_attr "type" "fsimps,fsimps")]) | |
4249 | ||
4250 | (define_insn "*subsf3_cconly" | |
4251 | [(set (reg 33) | |
4dbb5970 | 4252 | (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0") |
3ef093a8 AK |
4253 | (match_operand:SF 2 "general_operand" "f,R")) |
4254 | (match_operand:SF 3 "const0_operand" ""))) | |
4255 | (clobber (match_scratch:SF 0 "=f,f"))] | |
4256 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
4257 | "@ | |
d40c829f UW |
4258 | sebr\t%0,%2 |
4259 | seb\t%0,%2" | |
3ef093a8 AK |
4260 | [(set_attr "op_type" "RRE,RXE") |
4261 | (set_attr "type" "fsimps,fsimps")]) | |
4262 | ||
9db1d521 HP |
4263 | (define_insn "*subsf3_ibm" |
4264 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4265 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
d3632d41 | 4266 | (match_operand:SF 2 "general_operand" "f,R"))) |
9db1d521 HP |
4267 | (clobber (reg:CC 33))] |
4268 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
4269 | "@ | |
d40c829f UW |
4270 | ser\t%0,%2 |
4271 | se\t%0,%2" | |
9db1d521 | 4272 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4273 | (set_attr "type" "fsimps,fsimps")]) |
9db1d521 HP |
4274 | |
4275 | ||
e69166de UW |
4276 | ;; |
4277 | ;;- Conditional add/subtract instructions. | |
4278 | ;; | |
4279 | ||
4280 | ; | |
4281 | ; adddicc instruction pattern(s). | |
4282 | ; | |
4283 | ||
4284 | (define_insn "*adddi3_alc_cc" | |
4285 | [(set (reg 33) | |
4286 | (compare | |
4287 | (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
4288 | (match_operand:DI 2 "general_operand" "d,m")) | |
4289 | (match_operand:DI 3 "s390_alc_comparison" "")) | |
4290 | (const_int 0))) | |
4291 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4292 | (plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4293 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
4294 | "@ | |
4295 | alcgr\\t%0,%2 | |
4296 | alcg\\t%0,%2" | |
4297 | [(set_attr "op_type" "RRE,RXY")]) | |
4298 | ||
4299 | (define_insn "*adddi3_alc" | |
4300 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4301 | (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") | |
4302 | (match_operand:DI 2 "general_operand" "d,m")) | |
4303 | (match_operand:DI 3 "s390_alc_comparison" ""))) | |
4304 | (clobber (reg:CC 33))] | |
4305 | "TARGET_64BIT" | |
4306 | "@ | |
4307 | alcgr\\t%0,%2 | |
4308 | alcg\\t%0,%2" | |
4309 | [(set_attr "op_type" "RRE,RXY")]) | |
4310 | ||
4311 | (define_insn "*subdi3_slb_cc" | |
4312 | [(set (reg 33) | |
4313 | (compare | |
4314 | (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
4315 | (match_operand:DI 2 "general_operand" "d,m")) | |
4316 | (match_operand:DI 3 "s390_slb_comparison" "")) | |
4317 | (const_int 0))) | |
4318 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
4319 | (minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4320 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
4321 | "@ | |
4322 | slbgr\\t%0,%2 | |
4323 | slbg\\t%0,%2" | |
4324 | [(set_attr "op_type" "RRE,RXY")]) | |
4325 | ||
4326 | (define_insn "*subdi3_slb" | |
4327 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4328 | (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") | |
4329 | (match_operand:DI 2 "general_operand" "d,m")) | |
4330 | (match_operand:DI 3 "s390_slb_comparison" ""))) | |
4331 | (clobber (reg:CC 33))] | |
4332 | "TARGET_64BIT" | |
4333 | "@ | |
4334 | slbgr\\t%0,%2 | |
4335 | slbg\\t%0,%2" | |
4336 | [(set_attr "op_type" "RRE,RXY")]) | |
4337 | ||
4338 | ; | |
4339 | ; addsicc instruction pattern(s). | |
4340 | ; | |
4341 | ||
4342 | (define_insn "*addsi3_alc_cc" | |
4343 | [(set (reg 33) | |
4344 | (compare | |
4345 | (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
4346 | (match_operand:SI 2 "general_operand" "d,m")) | |
4347 | (match_operand:SI 3 "s390_alc_comparison" "")) | |
4348 | (const_int 0))) | |
4349 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
4350 | (plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4351 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" | |
4352 | "@ | |
4353 | alcr\\t%0,%2 | |
4354 | alc\\t%0,%2" | |
4355 | [(set_attr "op_type" "RRE,RXY")]) | |
4356 | ||
4357 | (define_insn "*addsi3_alc" | |
4358 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4359 | (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
4360 | (match_operand:SI 2 "general_operand" "d,m")) | |
4361 | (match_operand:SI 3 "s390_alc_comparison" ""))) | |
4362 | (clobber (reg:CC 33))] | |
4363 | "TARGET_CPU_ZARCH" | |
4364 | "@ | |
4365 | alcr\\t%0,%2 | |
4366 | alc\\t%0,%2" | |
4367 | [(set_attr "op_type" "RRE,RXY")]) | |
4368 | ||
4369 | (define_insn "*subsi3_slb_cc" | |
4370 | [(set (reg 33) | |
4371 | (compare | |
4372 | (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
4373 | (match_operand:SI 2 "general_operand" "d,m")) | |
4374 | (match_operand:SI 3 "s390_slb_comparison" "")) | |
4375 | (const_int 0))) | |
4376 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
4377 | (minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
4378 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" | |
4379 | "@ | |
4380 | slbr\\t%0,%2 | |
4381 | slb\\t%0,%2" | |
4382 | [(set_attr "op_type" "RRE,RXY")]) | |
4383 | ||
4384 | (define_insn "*subsi3_slb" | |
4385 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4386 | (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
4387 | (match_operand:SI 2 "general_operand" "d,m")) | |
4388 | (match_operand:SI 3 "s390_slb_comparison" ""))) | |
4389 | (clobber (reg:CC 33))] | |
4390 | "TARGET_CPU_ZARCH" | |
4391 | "@ | |
4392 | slbr\\t%0,%2 | |
4393 | slb\\t%0,%2" | |
4394 | [(set_attr "op_type" "RRE,RXY")]) | |
4395 | ||
4396 | ||
9db1d521 HP |
4397 | ;; |
4398 | ;;- Multiply instructions. | |
4399 | ;; | |
4400 | ||
4023fb28 UW |
4401 | ; |
4402 | ; muldi3 instruction pattern(s). | |
4403 | ; | |
9db1d521 | 4404 | |
07893d4f UW |
4405 | (define_insn "*muldi3_sign" |
4406 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4407 | (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")) | |
4408 | (match_operand:DI 1 "register_operand" "0,0")))] | |
4409 | "TARGET_64BIT" | |
4410 | "@ | |
d40c829f UW |
4411 | msgfr\t%0,%2 |
4412 | msgf\t%0,%2" | |
d3632d41 | 4413 | [(set_attr "op_type" "RRE,RXY") |
07893d4f UW |
4414 | (set_attr "type" "imul")]) |
4415 | ||
4023fb28 | 4416 | (define_insn "muldi3" |
9db1d521 | 4417 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
96fd3851 | 4418 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
07893d4f | 4419 | (match_operand:DI 2 "general_operand" "d,K,m")))] |
9db1d521 HP |
4420 | "TARGET_64BIT" |
4421 | "@ | |
d40c829f UW |
4422 | msgr\t%0,%2 |
4423 | mghi\t%0,%h2 | |
4424 | msg\t%0,%2" | |
d3632d41 | 4425 | [(set_attr "op_type" "RRE,RI,RXY") |
f2d3c02a HP |
4426 | (set_attr "type" "imul")]) |
4427 | ||
9db1d521 HP |
4428 | ; |
4429 | ; mulsi3 instruction pattern(s). | |
4430 | ; | |
4431 | ||
f1e77d83 UW |
4432 | (define_insn "*mulsi3_sign" |
4433 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4434 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R")) | |
4435 | (match_operand:SI 1 "register_operand" "0")))] | |
4436 | "" | |
4437 | "mh\t%0,%2" | |
4438 | [(set_attr "op_type" "RX") | |
4439 | (set_attr "type" "imul")]) | |
4440 | ||
9db1d521 | 4441 | (define_insn "mulsi3" |
d3632d41 UW |
4442 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4443 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
4444 | (match_operand:SI 2 "general_operand" "d,K,R,T")))] | |
9db1d521 HP |
4445 | "" |
4446 | "@ | |
d40c829f UW |
4447 | msr\t%0,%2 |
4448 | mhi\t%0,%h2 | |
4449 | ms\t%0,%2 | |
4450 | msy\t%0,%2" | |
d3632d41 | 4451 | [(set_attr "op_type" "RRE,RI,RX,RXY") |
f2d3c02a | 4452 | (set_attr "type" "imul")]) |
9db1d521 | 4453 | |
4023fb28 UW |
4454 | ; |
4455 | ; mulsidi3 instruction pattern(s). | |
4456 | ; | |
4457 | ||
f1e77d83 UW |
4458 | (define_insn "mulsidi3" |
4459 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4460 | (mult:DI (sign_extend:DI | |
4461 | (match_operand:SI 1 "register_operand" "%0,0")) | |
4462 | (sign_extend:DI | |
4463 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))] | |
4023fb28 | 4464 | "!TARGET_64BIT" |
f1e77d83 UW |
4465 | "@ |
4466 | mr\t%0,%2 | |
4467 | m\t%0,%2" | |
4468 | [(set_attr "op_type" "RR,RX") | |
4469 | (set_attr "type" "imul")]) | |
4023fb28 | 4470 | |
f1e77d83 UW |
4471 | ; |
4472 | ; umulsidi3 instruction pattern(s). | |
4473 | ; | |
c7453384 | 4474 | |
f1e77d83 UW |
4475 | (define_insn "umulsidi3" |
4476 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4477 | (mult:DI (zero_extend:DI | |
4478 | (match_operand:SI 1 "register_operand" "%0,0")) | |
4479 | (zero_extend:DI | |
4480 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))] | |
4481 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4482 | "@ | |
4483 | mlr\t%0,%2 | |
4484 | ml\t%0,%2" | |
4485 | [(set_attr "op_type" "RRE,RXY") | |
f2d3c02a | 4486 | (set_attr "type" "imul")]) |
c7453384 | 4487 | |
9db1d521 HP |
4488 | ; |
4489 | ; muldf3 instruction pattern(s). | |
4490 | ; | |
4491 | ||
4492 | (define_expand "muldf3" | |
553e5ce9 UW |
4493 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
4494 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") | |
4495 | (match_operand:DF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4496 | "TARGET_HARD_FLOAT" |
4497 | "") | |
4498 | ||
4499 | (define_insn "*muldf3" | |
4500 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 4501 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4502 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4503 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4504 | "@ | |
d40c829f UW |
4505 | mdbr\t%0,%2 |
4506 | mdb\t%0,%2" | |
ce50cae8 | 4507 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4508 | (set_attr "type" "fmuld")]) |
9db1d521 HP |
4509 | |
4510 | (define_insn "*muldf3_ibm" | |
4511 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
96fd3851 | 4512 | (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4513 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4514 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4515 | "@ | |
d40c829f UW |
4516 | mdr\t%0,%2 |
4517 | md\t%0,%2" | |
9db1d521 | 4518 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4519 | (set_attr "type" "fmuld")]) |
9db1d521 | 4520 | |
a1b892b5 AK |
4521 | (define_insn "*fmadddf" |
4522 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4523 | (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f") | |
4524 | (match_operand:DF 2 "nonimmediate_operand" "f,R")) | |
4525 | (match_operand:DF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4526 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4527 | "@ |
4528 | madbr\t%0,%1,%2 | |
4529 | madb\t%0,%1,%2" | |
4530 | [(set_attr "op_type" "RRE,RXE") | |
4531 | (set_attr "type" "fmuld")]) | |
4532 | ||
4533 | (define_insn "*fmsubdf" | |
4534 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
4535 | (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f") | |
4536 | (match_operand:DF 2 "nonimmediate_operand" "f,R")) | |
4537 | (match_operand:DF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4538 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4539 | "@ |
4540 | msdbr\t%0,%1,%2 | |
4541 | msdb\t%0,%1,%2" | |
4542 | [(set_attr "op_type" "RRE,RXE") | |
4543 | (set_attr "type" "fmuld")]) | |
4544 | ||
9db1d521 HP |
4545 | ; |
4546 | ; mulsf3 instruction pattern(s). | |
4547 | ; | |
4548 | ||
4549 | (define_expand "mulsf3" | |
553e5ce9 UW |
4550 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
4551 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") | |
4552 | (match_operand:SF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4553 | "TARGET_HARD_FLOAT" |
4554 | "") | |
4555 | ||
4556 | (define_insn "*mulsf3" | |
4557 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 4558 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4559 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4560 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4561 | "@ | |
d40c829f UW |
4562 | meebr\t%0,%2 |
4563 | meeb\t%0,%2" | |
ce50cae8 | 4564 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 4565 | (set_attr "type" "fmuls")]) |
9db1d521 HP |
4566 | |
4567 | (define_insn "*mulsf3_ibm" | |
4568 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
96fd3851 | 4569 | (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0") |
553e5ce9 | 4570 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
4571 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4572 | "@ | |
d40c829f UW |
4573 | mer\t%0,%2 |
4574 | me\t%0,%2" | |
9db1d521 | 4575 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4576 | (set_attr "type" "fmuls")]) |
9db1d521 | 4577 | |
a1b892b5 AK |
4578 | (define_insn "*fmaddsf" |
4579 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4580 | (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f") | |
4581 | (match_operand:SF 2 "nonimmediate_operand" "f,R")) | |
4582 | (match_operand:SF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4583 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4584 | "@ |
4585 | maebr\t%0,%1,%2 | |
4586 | maeb\t%0,%1,%2" | |
4587 | [(set_attr "op_type" "RRE,RXE") | |
4588 | (set_attr "type" "fmuls")]) | |
4589 | ||
4590 | (define_insn "*fmsubsf" | |
4591 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
4592 | (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f") | |
4593 | (match_operand:SF 2 "nonimmediate_operand" "f,R")) | |
4594 | (match_operand:SF 3 "register_operand" "0,0")))] | |
f2d226e1 | 4595 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 AK |
4596 | "@ |
4597 | msebr\t%0,%1,%2 | |
4598 | mseb\t%0,%1,%2" | |
4599 | [(set_attr "op_type" "RRE,RXE") | |
4600 | (set_attr "type" "fmuls")]) | |
9db1d521 HP |
4601 | |
4602 | ;; | |
4603 | ;;- Divide and modulo instructions. | |
4604 | ;; | |
4605 | ||
4606 | ; | |
4023fb28 | 4607 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
4608 | ; |
4609 | ||
4023fb28 UW |
4610 | (define_expand "divmoddi4" |
4611 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 4612 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
4613 | (match_operand:DI 2 "general_operand" ""))) |
4614 | (set (match_operand:DI 3 "general_operand" "") | |
4615 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
4616 | (clobber (match_dup 4))] | |
9db1d521 | 4617 | "TARGET_64BIT" |
9db1d521 | 4618 | { |
f1e77d83 | 4619 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
4620 | |
4621 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
4622 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
4623 | |
4624 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 4625 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
4626 | |
4627 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4628 | REG_NOTES (insn) = | |
4629 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4630 | ||
4631 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4632 | REG_NOTES (insn) = | |
4633 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4634 | |
9db1d521 | 4635 | DONE; |
10bbf137 | 4636 | }) |
9db1d521 HP |
4637 | |
4638 | (define_insn "divmodtidi3" | |
4023fb28 UW |
4639 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
4640 | (ior:TI | |
4023fb28 UW |
4641 | (ashift:TI |
4642 | (zero_extend:TI | |
5665e398 UW |
4643 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
4644 | (match_operand:DI 2 "general_operand" "d,m"))) | |
4645 | (const_int 64)) | |
4646 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9db1d521 HP |
4647 | "TARGET_64BIT" |
4648 | "@ | |
d40c829f UW |
4649 | dsgr\t%0,%2 |
4650 | dsg\t%0,%2" | |
d3632d41 | 4651 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4652 | (set_attr "type" "idiv")]) |
9db1d521 | 4653 | |
4023fb28 UW |
4654 | (define_insn "divmodtisi3" |
4655 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
4656 | (ior:TI | |
4023fb28 UW |
4657 | (ashift:TI |
4658 | (zero_extend:TI | |
5665e398 UW |
4659 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
4660 | (sign_extend:DI | |
4661 | (match_operand:SI 2 "nonimmediate_operand" "d,m")))) | |
4662 | (const_int 64)) | |
4663 | (zero_extend:TI | |
4664 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9db1d521 | 4665 | "TARGET_64BIT" |
4023fb28 | 4666 | "@ |
d40c829f UW |
4667 | dsgfr\t%0,%2 |
4668 | dsgf\t%0,%2" | |
d3632d41 | 4669 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4670 | (set_attr "type" "idiv")]) |
9db1d521 | 4671 | |
4023fb28 UW |
4672 | ; |
4673 | ; udivmoddi4 instruction pattern(s). | |
4674 | ; | |
9db1d521 | 4675 | |
4023fb28 UW |
4676 | (define_expand "udivmoddi4" |
4677 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
4678 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
4679 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
4680 | (set (match_operand:DI 3 "general_operand" "") | |
4681 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
4682 | (clobber (match_dup 4))] | |
9db1d521 | 4683 | "TARGET_64BIT" |
9db1d521 | 4684 | { |
4023fb28 UW |
4685 | rtx insn, div_equal, mod_equal, equal; |
4686 | ||
4687 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
4688 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
4689 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
4690 | gen_rtx_ASHIFT (TImode, |
4691 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
4692 | GEN_INT (64)), |
4693 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
4694 | |
4695 | operands[4] = gen_reg_rtx(TImode); | |
4696 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4697 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); | |
4698 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
4699 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); | |
4700 | REG_NOTES (insn) = | |
4701 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4702 | ||
4703 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4704 | REG_NOTES (insn) = | |
4705 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4706 | ||
4707 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4708 | REG_NOTES (insn) = | |
4709 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4710 | |
9db1d521 | 4711 | DONE; |
10bbf137 | 4712 | }) |
9db1d521 HP |
4713 | |
4714 | (define_insn "udivmodtidi3" | |
4023fb28 | 4715 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
5665e398 UW |
4716 | (ior:TI |
4717 | (ashift:TI | |
4718 | (zero_extend:TI | |
4719 | (truncate:DI | |
4720 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") | |
4721 | (zero_extend:TI | |
4722 | (match_operand:DI 2 "nonimmediate_operand" "d,m"))))) | |
4723 | (const_int 64)) | |
4724 | (zero_extend:TI | |
4725 | (truncate:DI | |
4726 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9db1d521 HP |
4727 | "TARGET_64BIT" |
4728 | "@ | |
d40c829f UW |
4729 | dlgr\t%0,%2 |
4730 | dlg\t%0,%2" | |
d3632d41 | 4731 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4732 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4733 | |
4734 | ; | |
4023fb28 | 4735 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
4736 | ; |
4737 | ||
4023fb28 UW |
4738 | (define_expand "divmodsi4" |
4739 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4740 | (div:SI (match_operand:SI 1 "general_operand" "") | |
4741 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4742 | (set (match_operand:SI 3 "general_operand" "") | |
4743 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
4744 | (clobber (match_dup 4))] | |
9db1d521 | 4745 | "!TARGET_64BIT" |
9db1d521 | 4746 | { |
4023fb28 UW |
4747 | rtx insn, div_equal, mod_equal, equal; |
4748 | ||
4749 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
4750 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
4751 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4752 | gen_rtx_ASHIFT (DImode, |
4753 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
4754 | GEN_INT (32)), |
4755 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
4756 | |
4757 | operands[4] = gen_reg_rtx(DImode); | |
4758 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
4759 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); | |
4760 | REG_NOTES (insn) = | |
4761 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4762 | ||
4763 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4764 | REG_NOTES (insn) = | |
4765 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4766 | ||
4767 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4768 | REG_NOTES (insn) = | |
4769 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4770 | |
9db1d521 | 4771 | DONE; |
10bbf137 | 4772 | }) |
9db1d521 HP |
4773 | |
4774 | (define_insn "divmoddisi3" | |
4023fb28 | 4775 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
5665e398 UW |
4776 | (ior:DI |
4777 | (ashift:DI | |
4778 | (zero_extend:DI | |
4779 | (truncate:SI | |
4780 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") | |
4781 | (sign_extend:DI | |
4782 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) | |
4783 | (const_int 32)) | |
4784 | (zero_extend:DI | |
4785 | (truncate:SI | |
4786 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9db1d521 HP |
4787 | "!TARGET_64BIT" |
4788 | "@ | |
d40c829f UW |
4789 | dr\t%0,%2 |
4790 | d\t%0,%2" | |
9db1d521 | 4791 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4792 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4793 | |
4794 | ; | |
4795 | ; udivsi3 and umodsi3 instruction pattern(s). | |
4796 | ; | |
4797 | ||
f1e77d83 UW |
4798 | (define_expand "udivmodsi4" |
4799 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4800 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4801 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4802 | (set (match_operand:SI 3 "general_operand" "") | |
4803 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
4804 | (clobber (match_dup 4))] | |
4805 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4806 | { | |
4807 | rtx insn, div_equal, mod_equal, equal; | |
4808 | ||
4809 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4810 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4811 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
4812 | gen_rtx_ASHIFT (DImode, |
4813 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
4814 | GEN_INT (32)), |
4815 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
4816 | |
4817 | operands[4] = gen_reg_rtx(DImode); | |
4818 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4819 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); | |
4820 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
4821 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); | |
4822 | REG_NOTES (insn) = | |
4823 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4824 | ||
4825 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4826 | REG_NOTES (insn) = | |
4827 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4828 | ||
4829 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4830 | REG_NOTES (insn) = | |
4831 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
4832 | ||
4833 | DONE; | |
4834 | }) | |
4835 | ||
4836 | (define_insn "udivmoddisi3" | |
4837 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5665e398 UW |
4838 | (ior:DI |
4839 | (ashift:DI | |
4840 | (zero_extend:DI | |
4841 | (truncate:SI | |
4842 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") | |
4843 | (zero_extend:DI | |
4844 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))) | |
4845 | (const_int 32)) | |
4846 | (zero_extend:DI | |
4847 | (truncate:SI | |
4848 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
f1e77d83 UW |
4849 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
4850 | "@ | |
4851 | dlr\t%0,%2 | |
4852 | dl\t%0,%2" | |
4853 | [(set_attr "op_type" "RRE,RXY") | |
4854 | (set_attr "type" "idiv")]) | |
4023fb28 | 4855 | |
9db1d521 HP |
4856 | (define_expand "udivsi3" |
4857 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4858 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
4859 | (match_operand:SI 2 "general_operand" ""))) |
4860 | (clobber (match_dup 3))] | |
f1e77d83 | 4861 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 4862 | { |
4023fb28 UW |
4863 | rtx insn, udiv_equal, umod_equal, equal; |
4864 | ||
4865 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4866 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4867 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4868 | gen_rtx_ASHIFT (DImode, |
4869 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
4870 | GEN_INT (32)), |
4871 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 4872 | |
4023fb28 | 4873 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
4874 | |
4875 | if (CONSTANT_P (operands[2])) | |
4876 | { | |
4877 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
4878 | { | |
4879 | rtx label1 = gen_label_rtx (); | |
4880 | ||
4023fb28 UW |
4881 | operands[1] = make_safe_from (operands[1], operands[0]); |
4882 | emit_move_insn (operands[0], const0_rtx); | |
4883 | emit_insn (gen_cmpsi (operands[1], operands[2])); | |
9db1d521 | 4884 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 | 4885 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
4886 | emit_label (label1); |
4887 | } | |
4888 | else | |
4889 | { | |
c7453384 EC |
4890 | operands[2] = force_reg (SImode, operands[2]); |
4891 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4892 | |
4893 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4894 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4895 | operands[2])); | |
4896 | REG_NOTES (insn) = | |
4897 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4898 | |
4899 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4900 | gen_lowpart (SImode, operands[3])); |
4901 | REG_NOTES (insn) = | |
c7453384 | 4902 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4903 | udiv_equal, REG_NOTES (insn)); |
9db1d521 HP |
4904 | } |
4905 | } | |
4906 | else | |
c7453384 | 4907 | { |
9db1d521 HP |
4908 | rtx label1 = gen_label_rtx (); |
4909 | rtx label2 = gen_label_rtx (); | |
4910 | rtx label3 = gen_label_rtx (); | |
4911 | ||
c7453384 EC |
4912 | operands[1] = force_reg (SImode, operands[1]); |
4913 | operands[1] = make_safe_from (operands[1], operands[0]); | |
4914 | operands[2] = force_reg (SImode, operands[2]); | |
4915 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4916 | |
4917 | emit_move_insn (operands[0], const0_rtx); | |
9db1d521 HP |
4918 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
4919 | emit_jump_insn (gen_bgtu (label3)); | |
4920 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4921 | emit_jump_insn (gen_blt (label2)); | |
4922 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4923 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
4924 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
4925 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4926 | operands[2])); | |
4927 | REG_NOTES (insn) = | |
4928 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4929 | |
4930 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4931 | gen_lowpart (SImode, operands[3])); |
4932 | REG_NOTES (insn) = | |
c7453384 | 4933 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4934 | udiv_equal, REG_NOTES (insn)); |
f314b9b1 | 4935 | emit_jump (label3); |
9db1d521 | 4936 | emit_label (label1); |
4023fb28 | 4937 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 4938 | emit_jump (label3); |
9db1d521 | 4939 | emit_label (label2); |
4023fb28 | 4940 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
4941 | emit_label (label3); |
4942 | } | |
c7453384 | 4943 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 4944 | DONE; |
10bbf137 | 4945 | }) |
9db1d521 HP |
4946 | |
4947 | (define_expand "umodsi3" | |
4948 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4949 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
4950 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
4951 | (clobber (match_dup 3))] | |
f1e77d83 | 4952 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 4953 | { |
4023fb28 UW |
4954 | rtx insn, udiv_equal, umod_equal, equal; |
4955 | ||
4956 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4957 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4958 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4959 | gen_rtx_ASHIFT (DImode, |
4960 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
4961 | GEN_INT (32)), |
4962 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 4963 | |
4023fb28 | 4964 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
4965 | |
4966 | if (CONSTANT_P (operands[2])) | |
4967 | { | |
4968 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
4969 | { | |
4970 | rtx label1 = gen_label_rtx (); | |
4971 | ||
4023fb28 UW |
4972 | operands[1] = make_safe_from (operands[1], operands[0]); |
4973 | emit_move_insn (operands[0], operands[1]); | |
4974 | emit_insn (gen_cmpsi (operands[0], operands[2])); | |
9db1d521 | 4975 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 UW |
4976 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
4977 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
4978 | emit_label (label1); |
4979 | } | |
4980 | else | |
4981 | { | |
c7453384 EC |
4982 | operands[2] = force_reg (SImode, operands[2]); |
4983 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4984 | |
4985 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4986 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4987 | operands[2])); | |
4988 | REG_NOTES (insn) = | |
4989 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4990 | |
4991 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4992 | gen_highpart (SImode, operands[3])); |
4993 | REG_NOTES (insn) = | |
c7453384 | 4994 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4995 | umod_equal, REG_NOTES (insn)); |
9db1d521 HP |
4996 | } |
4997 | } | |
4998 | else | |
4999 | { | |
5000 | rtx label1 = gen_label_rtx (); | |
5001 | rtx label2 = gen_label_rtx (); | |
5002 | rtx label3 = gen_label_rtx (); | |
5003 | ||
c7453384 EC |
5004 | operands[1] = force_reg (SImode, operands[1]); |
5005 | operands[1] = make_safe_from (operands[1], operands[0]); | |
5006 | operands[2] = force_reg (SImode, operands[2]); | |
5007 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 5008 | |
c7453384 | 5009 | emit_move_insn(operands[0], operands[1]); |
4023fb28 | 5010 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
9db1d521 HP |
5011 | emit_jump_insn (gen_bgtu (label3)); |
5012 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
5013 | emit_jump_insn (gen_blt (label2)); | |
5014 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
5015 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
5016 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
5017 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
5018 | operands[2])); | |
5019 | REG_NOTES (insn) = | |
5020 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
5021 | |
5022 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
5023 | gen_highpart (SImode, operands[3])); |
5024 | REG_NOTES (insn) = | |
c7453384 | 5025 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 5026 | umod_equal, REG_NOTES (insn)); |
f314b9b1 | 5027 | emit_jump (label3); |
9db1d521 | 5028 | emit_label (label1); |
4023fb28 | 5029 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 5030 | emit_jump (label3); |
9db1d521 | 5031 | emit_label (label2); |
4023fb28 | 5032 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
5033 | emit_label (label3); |
5034 | } | |
9db1d521 | 5035 | DONE; |
10bbf137 | 5036 | }) |
9db1d521 HP |
5037 | |
5038 | ; | |
5039 | ; divdf3 instruction pattern(s). | |
5040 | ; | |
5041 | ||
5042 | (define_expand "divdf3" | |
553e5ce9 UW |
5043 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
5044 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
5045 | (match_operand:DF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
5046 | "TARGET_HARD_FLOAT" |
5047 | "") | |
5048 | ||
5049 | (define_insn "*divdf3" | |
4023fb28 UW |
5050 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
5051 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
553e5ce9 | 5052 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
5053 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
5054 | "@ | |
d40c829f UW |
5055 | ddbr\t%0,%2 |
5056 | ddb\t%0,%2" | |
ce50cae8 | 5057 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 5058 | (set_attr "type" "fdivd")]) |
9db1d521 HP |
5059 | |
5060 | (define_insn "*divdf3_ibm" | |
4023fb28 UW |
5061 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
5062 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
553e5ce9 | 5063 | (match_operand:DF 2 "general_operand" "f,R")))] |
9db1d521 HP |
5064 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
5065 | "@ | |
d40c829f UW |
5066 | ddr\t%0,%2 |
5067 | dd\t%0,%2" | |
9db1d521 | 5068 | [(set_attr "op_type" "RR,RX") |
077dab3b | 5069 | (set_attr "type" "fdivd")]) |
9db1d521 HP |
5070 | |
5071 | ; | |
5072 | ; divsf3 instruction pattern(s). | |
5073 | ; | |
5074 | ||
5075 | (define_expand "divsf3" | |
553e5ce9 UW |
5076 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
5077 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
5078 | (match_operand:SF 2 "general_operand" "f,R")))] | |
9db1d521 HP |
5079 | "TARGET_HARD_FLOAT" |
5080 | "") | |
5081 | ||
5082 | (define_insn "*divsf3" | |
4023fb28 UW |
5083 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
5084 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
553e5ce9 | 5085 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
5086 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
5087 | "@ | |
d40c829f UW |
5088 | debr\t%0,%2 |
5089 | deb\t%0,%2" | |
ce50cae8 | 5090 | [(set_attr "op_type" "RRE,RXE") |
077dab3b | 5091 | (set_attr "type" "fdivs")]) |
9db1d521 HP |
5092 | |
5093 | (define_insn "*divsf3" | |
4023fb28 UW |
5094 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
5095 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
553e5ce9 | 5096 | (match_operand:SF 2 "general_operand" "f,R")))] |
9db1d521 HP |
5097 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
5098 | "@ | |
d40c829f UW |
5099 | der\t%0,%2 |
5100 | de\t%0,%2" | |
9db1d521 | 5101 | [(set_attr "op_type" "RR,RX") |
077dab3b | 5102 | (set_attr "type" "fdivs")]) |
9db1d521 HP |
5103 | |
5104 | ||
5105 | ;; | |
5106 | ;;- And instructions. | |
5107 | ;; | |
5108 | ||
5109 | ; | |
5110 | ; anddi3 instruction pattern(s). | |
5111 | ; | |
5112 | ||
5113 | (define_insn "*anddi3_cc" | |
5114 | [(set (reg 33) | |
96fd3851 | 5115 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 5116 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 | 5117 | (const_int 0))) |
4023fb28 | 5118 | (set (match_operand:DI 0 "register_operand" "=d,d") |
9db1d521 HP |
5119 | (and:DI (match_dup 1) (match_dup 2)))] |
5120 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5121 | "@ | |
d40c829f UW |
5122 | ngr\t%0,%2 |
5123 | ng\t%0,%2" | |
d3632d41 | 5124 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 HP |
5125 | |
5126 | (define_insn "*anddi3_cconly" | |
5127 | [(set (reg 33) | |
96fd3851 | 5128 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 5129 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 HP |
5130 | (const_int 0))) |
5131 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5132 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5133 | "@ | |
d40c829f UW |
5134 | ngr\t%0,%2 |
5135 | ng\t%0,%2" | |
d3632d41 | 5136 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 HP |
5137 | |
5138 | (define_insn "anddi3" | |
f19a9af7 AK |
5139 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d,d,d,d") |
5140 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o,0,0,0,0,0,0") | |
5141 | (match_operand:DI 2 "general_operand" | |
5142 | "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m"))) | |
5143 | (clobber (reg:CC 33))] | |
5144 | "TARGET_64BIT" | |
5145 | "@ | |
5146 | # | |
5147 | # | |
5148 | nihh\t%0,%j2 | |
5149 | nihl\t%0,%j2 | |
5150 | nilh\t%0,%j2 | |
5151 | nill\t%0,%j2 | |
5152 | ngr\t%0,%2 | |
5153 | ng\t%0,%2" | |
5154 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY")]) | |
4023fb28 UW |
5155 | |
5156 | (define_insn "*anddi3_ss" | |
ccfc6cc8 | 5157 | [(set (match_operand:DI 0 "s_operand" "=Q") |
4023fb28 | 5158 | (and:DI (match_dup 0) |
ccfc6cc8 | 5159 | (match_operand:DI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5160 | (clobber (reg:CC 33))] |
5161 | "" | |
d40c829f | 5162 | "nc\t%O0(8,%R0),%1" |
077dab3b | 5163 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5164 | |
5165 | (define_insn "*anddi3_ss_inv" | |
ccfc6cc8 UW |
5166 | [(set (match_operand:DI 0 "s_operand" "=Q") |
5167 | (and:DI (match_operand:DI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
5168 | (match_dup 0))) |
5169 | (clobber (reg:CC 33))] | |
5170 | "" | |
d40c829f | 5171 | "nc\t%O0(8,%R0),%1" |
077dab3b | 5172 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5173 | |
5174 | ; | |
5175 | ; andsi3 instruction pattern(s). | |
5176 | ; | |
5177 | ||
5178 | (define_insn "*andsi3_cc" | |
5179 | [(set (reg 33) | |
d3632d41 UW |
5180 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5181 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 5182 | (const_int 0))) |
d3632d41 | 5183 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 HP |
5184 | (and:SI (match_dup 1) (match_dup 2)))] |
5185 | "s390_match_ccmode(insn, CCTmode)" | |
5186 | "@ | |
d40c829f UW |
5187 | nr\t%0,%2 |
5188 | n\t%0,%2 | |
5189 | ny\t%0,%2" | |
d3632d41 | 5190 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
5191 | |
5192 | (define_insn "*andsi3_cconly" | |
5193 | [(set (reg 33) | |
d3632d41 UW |
5194 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5195 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 5196 | (const_int 0))) |
d3632d41 | 5197 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
9db1d521 HP |
5198 | "s390_match_ccmode(insn, CCTmode)" |
5199 | "@ | |
d40c829f UW |
5200 | nr\t%0,%2 |
5201 | n\t%0,%2 | |
5202 | ny\t%0,%2" | |
d3632d41 | 5203 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 5204 | |
f19a9af7 AK |
5205 | (define_expand "andsi3" |
5206 | [(parallel | |
5207 | [(set (match_operand:SI 0 "register_operand" "") | |
5208 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
5209 | (match_operand:SI 2 "general_operand" ""))) | |
5210 | (clobber (reg:CC 33))])] | |
5211 | "" | |
5212 | "") | |
4023fb28 | 5213 | |
f19a9af7 AK |
5214 | (define_insn "*andsi3_zarch" |
5215 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d,d") | |
5216 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,o,0,0,0,0,0") | |
5217 | (match_operand:SI 2 "general_operand" "M,M,N0HSF,N1HSF,d,R,T"))) | |
9db1d521 | 5218 | (clobber (reg:CC 33))] |
f19a9af7 | 5219 | "TARGET_ZARCH" |
9db1d521 | 5220 | "@ |
f19a9af7 AK |
5221 | # |
5222 | # | |
5223 | nilh\t%0,%j2 | |
5224 | nill\t%0,%j2 | |
d40c829f UW |
5225 | nr\t%0,%2 |
5226 | n\t%0,%2 | |
5227 | ny\t%0,%2" | |
f19a9af7 AK |
5228 | [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY")]) |
5229 | ||
5230 | (define_insn "*andsi3_esa" | |
5231 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5232 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0") | |
5233 | (match_operand:SI 2 "general_operand" "d,R"))) | |
5234 | (clobber (reg:CC 33))] | |
5235 | "!TARGET_ZARCH" | |
5236 | "@ | |
5237 | nr\t%0,%2 | |
5238 | n\t%0,%2" | |
5239 | [(set_attr "op_type" "RR,RX")]) | |
4023fb28 UW |
5240 | |
5241 | (define_insn "*andsi3_ss" | |
ccfc6cc8 | 5242 | [(set (match_operand:SI 0 "s_operand" "=Q") |
4023fb28 | 5243 | (and:SI (match_dup 0) |
ccfc6cc8 | 5244 | (match_operand:SI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5245 | (clobber (reg:CC 33))] |
5246 | "" | |
d40c829f | 5247 | "nc\t%O0(4,%R0),%1" |
077dab3b | 5248 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5249 | |
5250 | (define_insn "*andsi3_ss_inv" | |
ccfc6cc8 UW |
5251 | [(set (match_operand:SI 0 "s_operand" "=Q") |
5252 | (and:SI (match_operand:SI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
5253 | (match_dup 0))) |
5254 | (clobber (reg:CC 33))] | |
5255 | "" | |
d40c829f | 5256 | "nc\t%O0(4,%R0),%1" |
077dab3b | 5257 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5258 | |
5259 | ; | |
5260 | ; andhi3 instruction pattern(s). | |
5261 | ; | |
5262 | ||
4023fb28 UW |
5263 | (define_insn "*andhi3_ni" |
5264 | [(set (match_operand:HI 0 "register_operand" "=d,d") | |
5265 | (and:HI (match_operand:HI 1 "register_operand" "%0,0") | |
5266 | (match_operand:HI 2 "nonmemory_operand" "d,n"))) | |
5267 | (clobber (reg:CC 33))] | |
9e8327e3 | 5268 | "TARGET_ZARCH" |
4023fb28 | 5269 | "@ |
d40c829f UW |
5270 | nr\t%0,%2 |
5271 | nill\t%0,%x2" | |
077dab3b | 5272 | [(set_attr "op_type" "RR,RI")]) |
4023fb28 UW |
5273 | |
5274 | (define_insn "andhi3" | |
5275 | [(set (match_operand:HI 0 "register_operand" "=d") | |
5276 | (and:HI (match_operand:HI 1 "register_operand" "%0") | |
5277 | (match_operand:HI 2 "nonmemory_operand" "d"))) | |
5278 | (clobber (reg:CC 33))] | |
9db1d521 | 5279 | "" |
d40c829f | 5280 | "nr\t%0,%2" |
077dab3b | 5281 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5282 | |
5283 | (define_insn "*andhi3_ss" | |
ccfc6cc8 | 5284 | [(set (match_operand:HI 0 "s_operand" "=Q") |
4023fb28 | 5285 | (and:HI (match_dup 0) |
ccfc6cc8 | 5286 | (match_operand:HI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5287 | (clobber (reg:CC 33))] |
5288 | "" | |
d40c829f | 5289 | "nc\t%O0(2,%R0),%1" |
077dab3b | 5290 | [(set_attr "op_type" "SS")]) |
9db1d521 | 5291 | |
4023fb28 | 5292 | (define_insn "*andhi3_ss_inv" |
ccfc6cc8 UW |
5293 | [(set (match_operand:HI 0 "s_operand" "=Q") |
5294 | (and:HI (match_operand:HI 1 "s_imm_operand" "Q") | |
4023fb28 | 5295 | (match_dup 0))) |
9db1d521 HP |
5296 | (clobber (reg:CC 33))] |
5297 | "" | |
d40c829f | 5298 | "nc\t%O0(2,%R0),%1" |
077dab3b | 5299 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5300 | |
5301 | ; | |
5302 | ; andqi3 instruction pattern(s). | |
5303 | ; | |
5304 | ||
4023fb28 UW |
5305 | (define_insn "*andqi3_ni" |
5306 | [(set (match_operand:QI 0 "register_operand" "=d,d") | |
5307 | (and:QI (match_operand:QI 1 "register_operand" "%0,0") | |
5308 | (match_operand:QI 2 "nonmemory_operand" "d,n"))) | |
5309 | (clobber (reg:CC 33))] | |
9e8327e3 | 5310 | "TARGET_ZARCH" |
4023fb28 | 5311 | "@ |
d40c829f UW |
5312 | nr\t%0,%2 |
5313 | nill\t%0,%b2" | |
077dab3b | 5314 | [(set_attr "op_type" "RR,RI")]) |
4023fb28 | 5315 | |
9db1d521 | 5316 | (define_insn "andqi3" |
4023fb28 UW |
5317 | [(set (match_operand:QI 0 "register_operand" "=d") |
5318 | (and:QI (match_operand:QI 1 "register_operand" "%0") | |
5319 | (match_operand:QI 2 "nonmemory_operand" "d"))) | |
5320 | (clobber (reg:CC 33))] | |
5321 | "" | |
d40c829f | 5322 | "nr\t%0,%2" |
077dab3b | 5323 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5324 | |
5325 | (define_insn "*andqi3_ss" | |
d3632d41 | 5326 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
4023fb28 | 5327 | (and:QI (match_dup 0) |
d3632d41 | 5328 | (match_operand:QI 1 "s_imm_operand" "n,n,Q"))) |
9db1d521 HP |
5329 | (clobber (reg:CC 33))] |
5330 | "" | |
5331 | "@ | |
d40c829f UW |
5332 | ni\t%0,%b1 |
5333 | niy\t%0,%b1 | |
5334 | nc\t%O0(1,%R0),%1" | |
d3632d41 | 5335 | [(set_attr "op_type" "SI,SIY,SS")]) |
4023fb28 UW |
5336 | |
5337 | (define_insn "*andqi3_ss_inv" | |
d3632d41 UW |
5338 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
5339 | (and:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q") | |
4023fb28 UW |
5340 | (match_dup 0))) |
5341 | (clobber (reg:CC 33))] | |
5342 | "" | |
5343 | "@ | |
d40c829f UW |
5344 | ni\t%0,%b1 |
5345 | niy\t%0,%b1 | |
5346 | nc\t%O0(1,%R0),%1" | |
d3632d41 | 5347 | [(set_attr "op_type" "SI,SIY,SS")]) |
9db1d521 HP |
5348 | |
5349 | ||
5350 | ;; | |
5351 | ;;- Bit set (inclusive or) instructions. | |
5352 | ;; | |
5353 | ||
5354 | ; | |
5355 | ; iordi3 instruction pattern(s). | |
5356 | ; | |
5357 | ||
4023fb28 UW |
5358 | (define_insn "*iordi3_cc" |
5359 | [(set (reg 33) | |
96fd3851 | 5360 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5361 | (match_operand:DI 2 "general_operand" "d,m")) |
5362 | (const_int 0))) | |
5363 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5364 | (ior:DI (match_dup 1) (match_dup 2)))] | |
5365 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5366 | "@ | |
d40c829f UW |
5367 | ogr\t%0,%2 |
5368 | og\t%0,%2" | |
d3632d41 | 5369 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5370 | |
5371 | (define_insn "*iordi3_cconly" | |
5372 | [(set (reg 33) | |
96fd3851 | 5373 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5374 | (match_operand:DI 2 "general_operand" "d,m")) |
5375 | (const_int 0))) | |
5376 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5377 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5378 | "@ | |
d40c829f UW |
5379 | ogr\t%0,%2 |
5380 | og\t%0,%2" | |
d3632d41 | 5381 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 5382 | |
9db1d521 | 5383 | (define_insn "iordi3" |
f19a9af7 AK |
5384 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d,d") |
5385 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "0,0,0,0,0,0") | |
5386 | (match_operand:DI 2 "general_operand" "N0HD0,N1HD0,N2HD0,N3HD0,d,m"))) | |
9db1d521 HP |
5387 | (clobber (reg:CC 33))] |
5388 | "TARGET_64BIT" | |
5389 | "@ | |
f19a9af7 AK |
5390 | oihh\t%0,%i2 |
5391 | oihl\t%0,%i2 | |
5392 | oilh\t%0,%i2 | |
5393 | oill\t%0,%i2 | |
d40c829f UW |
5394 | ogr\t%0,%2 |
5395 | og\t%0,%2" | |
f19a9af7 | 5396 | [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY")]) |
4023fb28 UW |
5397 | |
5398 | (define_insn "*iordi3_ss" | |
ccfc6cc8 | 5399 | [(set (match_operand:DI 0 "s_operand" "=Q") |
4023fb28 | 5400 | (ior:DI (match_dup 0) |
ccfc6cc8 | 5401 | (match_operand:DI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5402 | (clobber (reg:CC 33))] |
5403 | "" | |
d40c829f | 5404 | "oc\t%O0(8,%R0),%1" |
077dab3b | 5405 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5406 | |
5407 | (define_insn "*iordi3_ss_inv" | |
ccfc6cc8 UW |
5408 | [(set (match_operand:DI 0 "s_operand" "=Q") |
5409 | (ior:DI (match_operand:DI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
5410 | (match_dup 0))) |
5411 | (clobber (reg:CC 33))] | |
5412 | "" | |
d40c829f | 5413 | "oc\t%O0(8,%R0),%1" |
077dab3b | 5414 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5415 | |
5416 | ; | |
5417 | ; iorsi3 instruction pattern(s). | |
5418 | ; | |
5419 | ||
4023fb28 UW |
5420 | (define_insn "*iorsi3_cc" |
5421 | [(set (reg 33) | |
d3632d41 UW |
5422 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5423 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5424 | (const_int 0))) |
d3632d41 | 5425 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
4023fb28 UW |
5426 | (ior:SI (match_dup 1) (match_dup 2)))] |
5427 | "s390_match_ccmode(insn, CCTmode)" | |
5428 | "@ | |
d40c829f UW |
5429 | or\t%0,%2 |
5430 | o\t%0,%2 | |
5431 | oy\t%0,%2" | |
d3632d41 | 5432 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5433 | |
5434 | (define_insn "*iorsi3_cconly" | |
5435 | [(set (reg 33) | |
d3632d41 UW |
5436 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5437 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5438 | (const_int 0))) |
d3632d41 | 5439 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
4023fb28 UW |
5440 | "s390_match_ccmode(insn, CCTmode)" |
5441 | "@ | |
d40c829f UW |
5442 | or\t%0,%2 |
5443 | o\t%0,%2 | |
5444 | oy\t%0,%2" | |
d3632d41 | 5445 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 | 5446 | |
f19a9af7 AK |
5447 | (define_expand "iorsi3" |
5448 | [(parallel | |
5449 | [(set (match_operand:SI 0 "register_operand" "") | |
5450 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
5451 | (match_operand:SI 2 "general_operand" ""))) | |
5452 | (clobber (reg:CC 33))])] | |
5453 | "" | |
5454 | "") | |
4023fb28 | 5455 | |
f19a9af7 AK |
5456 | (define_insn "iorsi3_zarch" |
5457 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") | |
5458 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0,0,0,0,0") | |
5459 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T"))) | |
4023fb28 | 5460 | (clobber (reg:CC 33))] |
f19a9af7 | 5461 | "TARGET_ZARCH" |
4023fb28 | 5462 | "@ |
f19a9af7 AK |
5463 | oilh\t%0,%i2 |
5464 | oill\t%0,%i2 | |
d40c829f UW |
5465 | or\t%0,%2 |
5466 | o\t%0,%2 | |
5467 | oy\t%0,%2" | |
f19a9af7 AK |
5468 | [(set_attr "op_type" "RI,RI,RR,RX,RXY")]) |
5469 | ||
5470 | (define_insn "iorsi3_esa" | |
5471 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5472 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") | |
5473 | (match_operand:SI 2 "general_operand" "d,R"))) | |
5474 | (clobber (reg:CC 33))] | |
5475 | "!TARGET_ZARCH" | |
5476 | "@ | |
5477 | or\t%0,%2 | |
5478 | o\t%0,%2" | |
5479 | [(set_attr "op_type" "RR,RX")]) | |
4023fb28 UW |
5480 | |
5481 | (define_insn "*iorsi3_ss" | |
ccfc6cc8 | 5482 | [(set (match_operand:SI 0 "s_operand" "=Q") |
4023fb28 | 5483 | (ior:SI (match_dup 0) |
ccfc6cc8 | 5484 | (match_operand:SI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5485 | (clobber (reg:CC 33))] |
5486 | "" | |
d40c829f | 5487 | "oc\t%O0(4,%R0),%1" |
077dab3b | 5488 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5489 | |
5490 | (define_insn "*iorsi3_ss_inv" | |
ccfc6cc8 UW |
5491 | [(set (match_operand:SI 0 "s_operand" "=Q") |
5492 | (ior:SI (match_operand:SI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
5493 | (match_dup 0))) |
5494 | (clobber (reg:CC 33))] | |
5495 | "" | |
d40c829f | 5496 | "oc\t%O0(4,%R0),%1" |
077dab3b | 5497 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5498 | |
5499 | ; | |
5500 | ; iorhi3 instruction pattern(s). | |
5501 | ; | |
5502 | ||
5503 | (define_insn "*iorhi3_oi" | |
5504 | [(set (match_operand:HI 0 "register_operand" "=d,d") | |
5505 | (ior:HI (match_operand:HI 1 "register_operand" "%0,0") | |
5506 | (match_operand:HI 2 "nonmemory_operand" "d,n"))) | |
5507 | (clobber (reg:CC 33))] | |
9e8327e3 | 5508 | "TARGET_ZARCH" |
4023fb28 | 5509 | "@ |
d40c829f UW |
5510 | or\t%0,%2 |
5511 | oill\t%0,%x2" | |
077dab3b | 5512 | [(set_attr "op_type" "RR,RI")]) |
4023fb28 UW |
5513 | |
5514 | (define_insn "iorhi3" | |
5515 | [(set (match_operand:HI 0 "register_operand" "=d") | |
5516 | (ior:HI (match_operand:HI 1 "register_operand" "%0") | |
5517 | (match_operand:HI 2 "nonmemory_operand" "d"))) | |
5518 | (clobber (reg:CC 33))] | |
9db1d521 | 5519 | "" |
d40c829f | 5520 | "or\t%0,%2" |
077dab3b | 5521 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5522 | |
5523 | (define_insn "*iorhi3_ss" | |
ccfc6cc8 | 5524 | [(set (match_operand:HI 0 "s_operand" "=Q") |
4023fb28 | 5525 | (ior:HI (match_dup 0) |
ccfc6cc8 | 5526 | (match_operand:HI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5527 | (clobber (reg:CC 33))] |
5528 | "" | |
d40c829f | 5529 | "oc\t%O0(2,%R0),%1" |
077dab3b | 5530 | [(set_attr "op_type" "SS")]) |
9db1d521 | 5531 | |
4023fb28 | 5532 | (define_insn "*iorhi3_ss_inv" |
ccfc6cc8 UW |
5533 | [(set (match_operand:HI 0 "s_operand" "=Q") |
5534 | (ior:HI (match_operand:HI 1 "s_imm_operand" "Q") | |
4023fb28 | 5535 | (match_dup 0))) |
9db1d521 HP |
5536 | (clobber (reg:CC 33))] |
5537 | "" | |
d40c829f | 5538 | "oc\t%O0(2,%R0),%1" |
077dab3b | 5539 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5540 | |
5541 | ; | |
4023fb28 | 5542 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
5543 | ; |
5544 | ||
4023fb28 UW |
5545 | (define_insn "*iorqi3_oi" |
5546 | [(set (match_operand:QI 0 "register_operand" "=d,d") | |
5547 | (ior:QI (match_operand:QI 1 "register_operand" "%0,0") | |
5548 | (match_operand:QI 2 "nonmemory_operand" "d,n"))) | |
5549 | (clobber (reg:CC 33))] | |
9e8327e3 | 5550 | "TARGET_ZARCH" |
4023fb28 | 5551 | "@ |
d40c829f UW |
5552 | or\t%0,%2 |
5553 | oill\t%0,%b2" | |
077dab3b | 5554 | [(set_attr "op_type" "RR,RI")]) |
9db1d521 | 5555 | |
4023fb28 UW |
5556 | (define_insn "iorqi3" |
5557 | [(set (match_operand:QI 0 "register_operand" "=d") | |
5558 | (ior:QI (match_operand:QI 1 "register_operand" "%0") | |
5559 | (match_operand:QI 2 "nonmemory_operand" "d"))) | |
5560 | (clobber (reg:CC 33))] | |
5561 | "" | |
d40c829f | 5562 | "or\t%0,%2" |
077dab3b | 5563 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5564 | |
5565 | (define_insn "*iorqi3_ss" | |
d3632d41 | 5566 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
4023fb28 | 5567 | (ior:QI (match_dup 0) |
d3632d41 | 5568 | (match_operand:QI 1 "s_imm_operand" "n,n,Q"))) |
9db1d521 HP |
5569 | (clobber (reg:CC 33))] |
5570 | "" | |
5571 | "@ | |
d40c829f UW |
5572 | oi\t%0,%b1 |
5573 | oiy\t%0,%b1 | |
5574 | oc\t%O0(1,%R0),%1" | |
d3632d41 | 5575 | [(set_attr "op_type" "SI,SIY,SS")]) |
9db1d521 | 5576 | |
4023fb28 | 5577 | (define_insn "*iorqi3_ss_inv" |
d3632d41 UW |
5578 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
5579 | (ior:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q") | |
4023fb28 | 5580 | (match_dup 0))) |
9db1d521 HP |
5581 | (clobber (reg:CC 33))] |
5582 | "" | |
5583 | "@ | |
d40c829f UW |
5584 | oi\t%0,%b1 |
5585 | oiy\t%0,%b1 | |
5586 | oc\t%O0(1,%R0),%1" | |
d3632d41 | 5587 | [(set_attr "op_type" "SI,SIY,SS")]) |
9db1d521 HP |
5588 | |
5589 | ||
5590 | ;; | |
5591 | ;;- Xor instructions. | |
5592 | ;; | |
5593 | ||
5594 | ; | |
5595 | ; xordi3 instruction pattern(s). | |
5596 | ; | |
5597 | ||
4023fb28 UW |
5598 | (define_insn "*xordi3_cc" |
5599 | [(set (reg 33) | |
96fd3851 | 5600 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5601 | (match_operand:DI 2 "general_operand" "d,m")) |
5602 | (const_int 0))) | |
5603 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5604 | (xor:DI (match_dup 1) (match_dup 2)))] | |
5605 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5606 | "@ | |
d40c829f UW |
5607 | xgr\t%0,%2 |
5608 | xg\t%0,%2" | |
d3632d41 | 5609 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5610 | |
5611 | (define_insn "*xordi3_cconly" | |
5612 | [(set (reg 33) | |
96fd3851 | 5613 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5614 | (match_operand:DI 2 "general_operand" "d,m")) |
5615 | (const_int 0))) | |
5616 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5617 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5618 | "@ | |
d40c829f UW |
5619 | xgr\t%0,%2 |
5620 | xr\t%0,%2" | |
d3632d41 | 5621 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 5622 | |
9db1d521 | 5623 | (define_insn "xordi3" |
4023fb28 | 5624 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
96fd3851 | 5625 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 5626 | (match_operand:DI 2 "general_operand" "d,m"))) |
9db1d521 HP |
5627 | (clobber (reg:CC 33))] |
5628 | "TARGET_64BIT" | |
5629 | "@ | |
d40c829f UW |
5630 | xgr\t%0,%2 |
5631 | xg\t%0,%2" | |
d3632d41 | 5632 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5633 | |
5634 | (define_insn "*xordi3_ss" | |
ccfc6cc8 | 5635 | [(set (match_operand:DI 0 "s_operand" "=Q") |
4023fb28 | 5636 | (xor:DI (match_dup 0) |
ccfc6cc8 | 5637 | (match_operand:DI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5638 | (clobber (reg:CC 33))] |
5639 | "" | |
d40c829f | 5640 | "xc\t%O0(8,%R0),%1" |
077dab3b | 5641 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5642 | |
5643 | (define_insn "*xordi3_ss_inv" | |
ccfc6cc8 UW |
5644 | [(set (match_operand:DI 0 "s_operand" "=Q") |
5645 | (xor:DI (match_operand:DI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
5646 | (match_dup 0))) |
5647 | (clobber (reg:CC 33))] | |
5648 | "" | |
d40c829f | 5649 | "xc\t%O0(8,%R0),%1" |
077dab3b | 5650 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5651 | |
5652 | ; | |
5653 | ; xorsi3 instruction pattern(s). | |
5654 | ; | |
5655 | ||
4023fb28 UW |
5656 | (define_insn "*xorsi3_cc" |
5657 | [(set (reg 33) | |
d3632d41 UW |
5658 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5659 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5660 | (const_int 0))) |
d3632d41 | 5661 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
4023fb28 UW |
5662 | (xor:SI (match_dup 1) (match_dup 2)))] |
5663 | "s390_match_ccmode(insn, CCTmode)" | |
5664 | "@ | |
d40c829f UW |
5665 | xr\t%0,%2 |
5666 | x\t%0,%2 | |
5667 | xy\t%0,%2" | |
d3632d41 | 5668 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5669 | |
5670 | (define_insn "*xorsi3_cconly" | |
5671 | [(set (reg 33) | |
d3632d41 UW |
5672 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
5673 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
4023fb28 | 5674 | (const_int 0))) |
d3632d41 | 5675 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
4023fb28 UW |
5676 | "s390_match_ccmode(insn, CCTmode)" |
5677 | "@ | |
d40c829f UW |
5678 | xr\t%0,%2 |
5679 | x\t%0,%2 | |
5680 | xy\t%0,%2" | |
d3632d41 | 5681 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 5682 | |
4023fb28 | 5683 | (define_insn "xorsi3" |
d3632d41 UW |
5684 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
5685 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") | |
5686 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
9db1d521 HP |
5687 | (clobber (reg:CC 33))] |
5688 | "" | |
5689 | "@ | |
d40c829f UW |
5690 | xr\t%0,%2 |
5691 | x\t%0,%2 | |
5692 | xy\t%0,%2" | |
d3632d41 | 5693 | [(set_attr "op_type" "RR,RX,RXY")]) |
4023fb28 UW |
5694 | |
5695 | (define_insn "*xorsi3_ss" | |
ccfc6cc8 | 5696 | [(set (match_operand:SI 0 "s_operand" "=Q") |
4023fb28 | 5697 | (xor:SI (match_dup 0) |
ccfc6cc8 | 5698 | (match_operand:SI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5699 | (clobber (reg:CC 33))] |
5700 | "" | |
d40c829f | 5701 | "xc\t%O0(4,%R0),%1" |
077dab3b | 5702 | [(set_attr "op_type" "SS")]) |
4023fb28 UW |
5703 | |
5704 | (define_insn "*xorsi3_ss_inv" | |
ccfc6cc8 UW |
5705 | [(set (match_operand:SI 0 "s_operand" "=Q") |
5706 | (xor:SI (match_operand:SI 1 "s_imm_operand" "Q") | |
4023fb28 UW |
5707 | (match_dup 0))) |
5708 | (clobber (reg:CC 33))] | |
5709 | "" | |
d40c829f | 5710 | "xc\t%O0(4,%R0),%1" |
077dab3b | 5711 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5712 | |
5713 | ; | |
5714 | ; xorhi3 instruction pattern(s). | |
5715 | ; | |
5716 | ||
4023fb28 UW |
5717 | (define_insn "xorhi3" |
5718 | [(set (match_operand:HI 0 "register_operand" "=d") | |
5719 | (xor:HI (match_operand:HI 1 "register_operand" "%0") | |
5720 | (match_operand:HI 2 "nonmemory_operand" "d"))) | |
5721 | (clobber (reg:CC 33))] | |
9db1d521 | 5722 | "" |
d40c829f | 5723 | "xr\t%0,%2" |
d3632d41 | 5724 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5725 | |
5726 | (define_insn "*xorhi3_ss" | |
ccfc6cc8 | 5727 | [(set (match_operand:HI 0 "s_operand" "=Q") |
4023fb28 | 5728 | (xor:HI (match_dup 0) |
ccfc6cc8 | 5729 | (match_operand:HI 1 "s_imm_operand" "Q"))) |
4023fb28 UW |
5730 | (clobber (reg:CC 33))] |
5731 | "" | |
d40c829f | 5732 | "xc\t%O0(2,%R0),%1" |
077dab3b | 5733 | [(set_attr "op_type" "SS")]) |
9db1d521 | 5734 | |
4023fb28 | 5735 | (define_insn "*xorhi3_ss_inv" |
ccfc6cc8 UW |
5736 | [(set (match_operand:HI 0 "s_operand" "=Q") |
5737 | (xor:HI (match_operand:HI 1 "s_imm_operand" "Q") | |
4023fb28 | 5738 | (match_dup 0))) |
9db1d521 HP |
5739 | (clobber (reg:CC 33))] |
5740 | "" | |
d40c829f | 5741 | "xc\t%O0(2,%R0),%1" |
077dab3b | 5742 | [(set_attr "op_type" "SS")]) |
9db1d521 HP |
5743 | |
5744 | ; | |
5745 | ; xorqi3 instruction pattern(s). | |
5746 | ; | |
5747 | ||
5748 | (define_insn "xorqi3" | |
4023fb28 UW |
5749 | [(set (match_operand:QI 0 "register_operand" "=d") |
5750 | (xor:QI (match_operand:QI 1 "register_operand" "%0") | |
5751 | (match_operand:QI 2 "nonmemory_operand" "d"))) | |
5752 | (clobber (reg:CC 33))] | |
5753 | "" | |
d40c829f | 5754 | "xr\t%0,%2" |
077dab3b | 5755 | [(set_attr "op_type" "RR")]) |
4023fb28 UW |
5756 | |
5757 | (define_insn "*xorqi3_ss" | |
d3632d41 | 5758 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
4023fb28 | 5759 | (xor:QI (match_dup 0) |
d3632d41 | 5760 | (match_operand:QI 1 "s_imm_operand" "n,n,Q"))) |
9db1d521 HP |
5761 | (clobber (reg:CC 33))] |
5762 | "" | |
5763 | "@ | |
d40c829f UW |
5764 | xi\t%0,%b1 |
5765 | xiy\t%0,%b1 | |
5766 | xc\t%O0(1,%R0),%1" | |
d3632d41 | 5767 | [(set_attr "op_type" "SI,SIY,SS")]) |
4023fb28 UW |
5768 | |
5769 | (define_insn "*xorqi3_ss_inv" | |
d3632d41 UW |
5770 | [(set (match_operand:QI 0 "s_operand" "=Q,S,Q") |
5771 | (xor:QI (match_operand:QI 1 "s_imm_operand" "n,n,Q") | |
4023fb28 UW |
5772 | (match_dup 0))) |
5773 | (clobber (reg:CC 33))] | |
5774 | "" | |
5775 | "@ | |
d40c829f UW |
5776 | xi\t%0,%b1 |
5777 | xiy\t%0,%b1 | |
5778 | xc\t%O0(1,%R0),%1" | |
d3632d41 | 5779 | [(set_attr "op_type" "SI,SIY,SS")]) |
9db1d521 HP |
5780 | |
5781 | ||
5782 | ;; | |
5783 | ;;- Negate instructions. | |
5784 | ;; | |
5785 | ||
5786 | ; | |
5787 | ; negdi2 instruction pattern(s). | |
5788 | ; | |
5789 | ||
5790 | (define_expand "negdi2" | |
5791 | [(parallel | |
5792 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5793 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
5794 | (clobber (reg:CC 33))])] | |
5795 | "" | |
5796 | "") | |
5797 | ||
5798 | (define_insn "*negdi2_64" | |
5799 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5800 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
5801 | (clobber (reg:CC 33))] | |
5802 | "TARGET_64BIT" | |
d40c829f | 5803 | "lcgr\t%0,%1" |
f2d3c02a | 5804 | [(set_attr "op_type" "RR")]) |
9db1d521 HP |
5805 | |
5806 | (define_insn "*negdi2_31" | |
5807 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5808 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
5809 | (clobber (reg:CC 33))] | |
5810 | "!TARGET_64BIT" | |
9db1d521 HP |
5811 | { |
5812 | rtx xop[1]; | |
5813 | xop[0] = gen_label_rtx (); | |
d40c829f UW |
5814 | output_asm_insn ("lcr\t%0,%1", operands); |
5815 | output_asm_insn ("lcr\t%N0,%N1", operands); | |
5816 | output_asm_insn ("je\t%l0", xop); | |
5817 | output_asm_insn ("bctr\t%0,0", operands); | |
47798692 | 5818 | targetm.asm_out.internal_label (asm_out_file, "L", |
9db1d521 | 5819 | CODE_LABEL_NUMBER (xop[0])); |
10bbf137 UW |
5820 | return ""; |
5821 | } | |
9db1d521 | 5822 | [(set_attr "op_type" "NN") |
4023fb28 UW |
5823 | (set_attr "type" "other") |
5824 | (set_attr "length" "10")]) | |
9db1d521 HP |
5825 | |
5826 | ; | |
5827 | ; negsi2 instruction pattern(s). | |
5828 | ; | |
5829 | ||
5830 | (define_insn "negsi2" | |
5831 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5832 | (neg:SI (match_operand:SI 1 "register_operand" "d"))) | |
5833 | (clobber (reg:CC 33))] | |
5834 | "" | |
d40c829f | 5835 | "lcr\t%0,%1" |
f2d3c02a | 5836 | [(set_attr "op_type" "RR")]) |
9db1d521 HP |
5837 | |
5838 | ; | |
5839 | ; negdf2 instruction pattern(s). | |
5840 | ; | |
5841 | ||
5842 | (define_expand "negdf2" | |
5843 | [(parallel | |
5844 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5845 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
5846 | (clobber (reg:CC 33))])] | |
5847 | "TARGET_HARD_FLOAT" | |
5848 | "") | |
5849 | ||
5850 | (define_insn "*negdf2" | |
5851 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5852 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
5853 | (clobber (reg:CC 33))] | |
5854 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 5855 | "lcdbr\t%0,%1" |
077dab3b HP |
5856 | [(set_attr "op_type" "RRE") |
5857 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
5858 | |
5859 | (define_insn "*negdf2_ibm" | |
5860 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5861 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
5862 | (clobber (reg:CC 33))] | |
5863 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 5864 | "lcdr\t%0,%1" |
077dab3b HP |
5865 | [(set_attr "op_type" "RR") |
5866 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
5867 | |
5868 | ; | |
5869 | ; negsf2 instruction pattern(s). | |
5870 | ; | |
5871 | ||
5872 | (define_expand "negsf2" | |
5873 | [(parallel | |
5874 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5875 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
5876 | (clobber (reg:CC 33))])] | |
5877 | "TARGET_HARD_FLOAT" | |
5878 | "") | |
5879 | ||
5880 | (define_insn "*negsf2" | |
5881 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5882 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
5883 | (clobber (reg:CC 33))] | |
5884 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 5885 | "lcebr\t%0,%1" |
077dab3b HP |
5886 | [(set_attr "op_type" "RRE") |
5887 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
5888 | |
5889 | (define_insn "*negsf2" | |
5890 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5891 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
5892 | (clobber (reg:CC 33))] | |
5893 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 5894 | "lcer\t%0,%1" |
077dab3b HP |
5895 | [(set_attr "op_type" "RR") |
5896 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
5897 | |
5898 | ||
5899 | ;; | |
5900 | ;;- Absolute value instructions. | |
5901 | ;; | |
5902 | ||
5903 | ; | |
5904 | ; absdi2 instruction pattern(s). | |
5905 | ; | |
5906 | ||
5907 | (define_insn "absdi2" | |
5908 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5909 | (abs:DI (match_operand:DI 1 "register_operand" "d"))) | |
5910 | (clobber (reg:CC 33))] | |
5911 | "TARGET_64BIT" | |
d40c829f | 5912 | "lpgr\t%0,%1" |
f2d3c02a | 5913 | [(set_attr "op_type" "RRE")]) |
9db1d521 HP |
5914 | |
5915 | ; | |
5916 | ; abssi2 instruction pattern(s). | |
5917 | ; | |
5918 | ||
5919 | (define_insn "abssi2" | |
5920 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5921 | (abs:SI (match_operand:SI 1 "register_operand" "d"))) | |
5922 | (clobber (reg:CC 33))] | |
5923 | "" | |
d40c829f | 5924 | "lpr\t%0,%1" |
f2d3c02a | 5925 | [(set_attr "op_type" "RR")]) |
9db1d521 | 5926 | |
9db1d521 HP |
5927 | ; |
5928 | ; absdf2 instruction pattern(s). | |
5929 | ; | |
5930 | ||
5931 | (define_expand "absdf2" | |
5932 | [(parallel | |
5933 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5934 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
5935 | (clobber (reg:CC 33))])] | |
5936 | "TARGET_HARD_FLOAT" | |
5937 | "") | |
5938 | ||
5939 | (define_insn "*absdf2" | |
5940 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5941 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
5942 | (clobber (reg:CC 33))] | |
5943 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 5944 | "lpdbr\t%0,%1" |
077dab3b HP |
5945 | [(set_attr "op_type" "RRE") |
5946 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
5947 | |
5948 | (define_insn "*absdf2_ibm" | |
5949 | [(set (match_operand:DF 0 "register_operand" "=f") | |
5950 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
5951 | (clobber (reg:CC 33))] | |
5952 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 5953 | "lpdr\t%0,%1" |
077dab3b HP |
5954 | [(set_attr "op_type" "RR") |
5955 | (set_attr "type" "fsimpd")]) | |
9db1d521 HP |
5956 | |
5957 | ; | |
5958 | ; abssf2 instruction pattern(s). | |
5959 | ; | |
5960 | ||
5961 | (define_expand "abssf2" | |
5962 | [(parallel | |
5963 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5964 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
5965 | (clobber (reg:CC 33))])] | |
5966 | "TARGET_HARD_FLOAT" | |
5967 | "") | |
5968 | ||
5969 | (define_insn "*abssf2" | |
5970 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5971 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
5972 | (clobber (reg:CC 33))] | |
5973 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 5974 | "lpebr\t%0,%1" |
077dab3b HP |
5975 | [(set_attr "op_type" "RRE") |
5976 | (set_attr "type" "fsimps")]) | |
9db1d521 HP |
5977 | |
5978 | (define_insn "*abssf2_ibm" | |
5979 | [(set (match_operand:SF 0 "register_operand" "=f") | |
5980 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
5981 | (clobber (reg:CC 33))] | |
5982 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
d40c829f | 5983 | "lper\t%0,%1" |
077dab3b HP |
5984 | [(set_attr "op_type" "RR") |
5985 | (set_attr "type" "fsimps")]) | |
9db1d521 | 5986 | |
3ef093a8 AK |
5987 | ;; |
5988 | ;;- Negated absolute value instructions | |
5989 | ;; | |
5990 | ||
5991 | ; | |
5992 | ; Integer | |
5993 | ; | |
5994 | ||
5995 | (define_insn "*negabssi2" | |
5996 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5997 | (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))) | |
5998 | (clobber (reg:CC 33))] | |
5999 | "" | |
d40c829f | 6000 | "lnr\t%0,%1" |
3ef093a8 AK |
6001 | [(set_attr "op_type" "RR")]) |
6002 | ||
6003 | (define_insn "*negabsdi2" | |
6004 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6005 | (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))) | |
6006 | (clobber (reg:CC 33))] | |
6007 | "TARGET_64BIT" | |
d40c829f | 6008 | "lngr\t%0,%1" |
3ef093a8 AK |
6009 | [(set_attr "op_type" "RRE")]) |
6010 | ||
6011 | ; | |
6012 | ; Floating point | |
6013 | ; | |
6014 | ||
6015 | (define_insn "*negabssf2" | |
6016 | [(set (match_operand:SF 0 "register_operand" "=f") | |
6017 | (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))) | |
6018 | (clobber (reg:CC 33))] | |
6019 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 6020 | "lnebr\t%0,%1" |
3ef093a8 AK |
6021 | [(set_attr "op_type" "RRE") |
6022 | (set_attr "type" "fsimps")]) | |
6023 | ||
6024 | (define_insn "*negabsdf2" | |
6025 | [(set (match_operand:DF 0 "register_operand" "=f") | |
6026 | (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))) | |
6027 | (clobber (reg:CC 33))] | |
6028 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
d40c829f | 6029 | "lndbr\t%0,%1" |
3ef093a8 AK |
6030 | [(set_attr "op_type" "RRE") |
6031 | (set_attr "type" "fsimpd")]) | |
6032 | ||
4023fb28 UW |
6033 | ;; |
6034 | ;;- Square root instructions. | |
6035 | ;; | |
6036 | ||
6037 | ; | |
6038 | ; sqrtdf2 instruction pattern(s). | |
6039 | ; | |
6040 | ||
6041 | (define_insn "sqrtdf2" | |
6042 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 6043 | (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))] |
4023fb28 UW |
6044 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
6045 | "@ | |
d40c829f UW |
6046 | sqdbr\t%0,%1 |
6047 | sqdb\t%0,%1" | |
d3632d41 | 6048 | [(set_attr "op_type" "RRE,RXE")]) |
4023fb28 UW |
6049 | |
6050 | ; | |
6051 | ; sqrtsf2 instruction pattern(s). | |
6052 | ; | |
6053 | ||
6054 | (define_insn "sqrtsf2" | |
6055 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
d3632d41 | 6056 | (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))] |
4023fb28 UW |
6057 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
6058 | "@ | |
d40c829f UW |
6059 | sqebr\t%0,%1 |
6060 | sqeb\t%0,%1" | |
d3632d41 | 6061 | [(set_attr "op_type" "RRE,RXE")]) |
9db1d521 HP |
6062 | |
6063 | ;; | |
6064 | ;;- One complement instructions. | |
6065 | ;; | |
6066 | ||
6067 | ; | |
6068 | ; one_cmpldi2 instruction pattern(s). | |
6069 | ; | |
c7453384 | 6070 | |
9db1d521 HP |
6071 | (define_expand "one_cmpldi2" |
6072 | [(parallel | |
4023fb28 UW |
6073 | [(set (match_operand:DI 0 "register_operand" "") |
6074 | (xor:DI (match_operand:DI 1 "register_operand" "") | |
6075 | (const_int -1))) | |
9db1d521 HP |
6076 | (clobber (reg:CC 33))])] |
6077 | "TARGET_64BIT" | |
4023fb28 | 6078 | "") |
c7453384 | 6079 | |
9db1d521 HP |
6080 | ; |
6081 | ; one_cmplsi2 instruction pattern(s). | |
6082 | ; | |
c7453384 | 6083 | |
9db1d521 HP |
6084 | (define_expand "one_cmplsi2" |
6085 | [(parallel | |
4023fb28 UW |
6086 | [(set (match_operand:SI 0 "register_operand" "") |
6087 | (xor:SI (match_operand:SI 1 "register_operand" "") | |
6088 | (const_int -1))) | |
9db1d521 HP |
6089 | (clobber (reg:CC 33))])] |
6090 | "" | |
4023fb28 | 6091 | "") |
c7453384 | 6092 | |
9db1d521 HP |
6093 | ; |
6094 | ; one_cmplhi2 instruction pattern(s). | |
6095 | ; | |
c7453384 | 6096 | |
9db1d521 HP |
6097 | (define_expand "one_cmplhi2" |
6098 | [(parallel | |
4023fb28 UW |
6099 | [(set (match_operand:HI 0 "register_operand" "") |
6100 | (xor:HI (match_operand:HI 1 "register_operand" "") | |
6101 | (const_int -1))) | |
9db1d521 HP |
6102 | (clobber (reg:CC 33))])] |
6103 | "" | |
4023fb28 | 6104 | "") |
c7453384 | 6105 | |
9db1d521 HP |
6106 | ; |
6107 | ; one_cmplqi2 instruction pattern(s). | |
6108 | ; | |
c7453384 | 6109 | |
4023fb28 UW |
6110 | (define_expand "one_cmplqi2" |
6111 | [(parallel | |
6112 | [(set (match_operand:QI 0 "register_operand" "") | |
6113 | (xor:QI (match_operand:QI 1 "register_operand" "") | |
6114 | (const_int -1))) | |
6115 | (clobber (reg:CC 33))])] | |
9db1d521 | 6116 | "" |
4023fb28 | 6117 | "") |
9db1d521 HP |
6118 | |
6119 | ||
6120 | ;; | |
6121 | ;;- Rotate instructions. | |
6122 | ;; | |
6123 | ||
6124 | ; | |
6125 | ; rotldi3 instruction pattern(s). | |
6126 | ; | |
6127 | ||
6128 | (define_insn "rotldi3" | |
ac32b25e UW |
6129 | [(set (match_operand:DI 0 "register_operand" "=d") |
6130 | (rotate:DI (match_operand:DI 1 "register_operand" "d") | |
6131 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6132 | "TARGET_64BIT" |
ac32b25e | 6133 | "rllg\t%0,%1,%Y2" |
077dab3b HP |
6134 | [(set_attr "op_type" "RSE") |
6135 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6136 | |
6137 | ; | |
6138 | ; rotlsi3 instruction pattern(s). | |
6139 | ; | |
6140 | ||
6141 | (define_insn "rotlsi3" | |
ac32b25e UW |
6142 | [(set (match_operand:SI 0 "register_operand" "=d") |
6143 | (rotate:SI (match_operand:SI 1 "register_operand" "d") | |
6144 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9e8327e3 | 6145 | "TARGET_CPU_ZARCH" |
ac32b25e | 6146 | "rll\t%0,%1,%Y2" |
077dab3b HP |
6147 | [(set_attr "op_type" "RSE") |
6148 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6149 | |
6150 | ||
6151 | ;; | |
6152 | ;;- Arithmetic shift instructions. | |
6153 | ;; | |
9db1d521 HP |
6154 | |
6155 | ; | |
6156 | ; ashldi3 instruction pattern(s). | |
6157 | ; | |
6158 | ||
6159 | (define_expand "ashldi3" | |
ecbe845e UW |
6160 | [(set (match_operand:DI 0 "register_operand" "") |
6161 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
ac32b25e | 6162 | (match_operand:SI 2 "shift_count_operand" "")))] |
9db1d521 HP |
6163 | "" |
6164 | "") | |
6165 | ||
6166 | (define_insn "*ashldi3_31" | |
ac32b25e UW |
6167 | [(set (match_operand:DI 0 "register_operand" "=d") |
6168 | (ashift:DI (match_operand:DI 1 "register_operand" "0") | |
6169 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6170 | "!TARGET_64BIT" |
ac32b25e | 6171 | "sldl\t%0,%Y2" |
077dab3b HP |
6172 | [(set_attr "op_type" "RS") |
6173 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6174 | |
6175 | (define_insn "*ashldi3_64" | |
ac32b25e UW |
6176 | [(set (match_operand:DI 0 "register_operand" "=d") |
6177 | (ashift:DI (match_operand:DI 1 "register_operand" "d") | |
6178 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6179 | "TARGET_64BIT" |
ac32b25e | 6180 | "sllg\t%0,%1,%Y2" |
077dab3b HP |
6181 | [(set_attr "op_type" "RSE") |
6182 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6183 | |
6184 | ; | |
6185 | ; ashrdi3 instruction pattern(s). | |
6186 | ; | |
6187 | ||
6188 | (define_expand "ashrdi3" | |
6189 | [(parallel | |
6190 | [(set (match_operand:DI 0 "register_operand" "") | |
6191 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
ac32b25e | 6192 | (match_operand:SI 2 "shift_count_operand" ""))) |
9db1d521 HP |
6193 | (clobber (reg:CC 33))])] |
6194 | "" | |
6195 | "") | |
6196 | ||
ecbe845e UW |
6197 | (define_insn "*ashrdi3_cc_31" |
6198 | [(set (reg 33) | |
ac32b25e UW |
6199 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
6200 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6201 | (const_int 0))) |
ac32b25e | 6202 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e UW |
6203 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6204 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" | |
ac32b25e | 6205 | "srda\t%0,%Y2" |
077dab3b HP |
6206 | [(set_attr "op_type" "RS") |
6207 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
6208 | |
6209 | (define_insn "*ashrdi3_cconly_31" | |
6210 | [(set (reg 33) | |
ac32b25e UW |
6211 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
6212 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6213 | (const_int 0))) |
ac32b25e | 6214 | (clobber (match_scratch:DI 0 "=d"))] |
ecbe845e | 6215 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 6216 | "srda\t%0,%Y2" |
077dab3b HP |
6217 | [(set_attr "op_type" "RS") |
6218 | (set_attr "atype" "reg")]) | |
ecbe845e | 6219 | |
9db1d521 | 6220 | (define_insn "*ashrdi3_31" |
ac32b25e UW |
6221 | [(set (match_operand:DI 0 "register_operand" "=d") |
6222 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
6223 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
9db1d521 HP |
6224 | (clobber (reg:CC 33))] |
6225 | "!TARGET_64BIT" | |
ac32b25e | 6226 | "srda\t%0,%Y2" |
077dab3b HP |
6227 | [(set_attr "op_type" "RS") |
6228 | (set_attr "atype" "reg")]) | |
c7453384 | 6229 | |
ecbe845e UW |
6230 | (define_insn "*ashrdi3_cc_64" |
6231 | [(set (reg 33) | |
ac32b25e UW |
6232 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") |
6233 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6234 | (const_int 0))) |
ac32b25e | 6235 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e UW |
6236 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6237 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
ac32b25e | 6238 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6239 | [(set_attr "op_type" "RSE") |
6240 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
6241 | |
6242 | (define_insn "*ashrdi3_cconly_64" | |
6243 | [(set (reg 33) | |
ac32b25e UW |
6244 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") |
6245 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6246 | (const_int 0))) |
ac32b25e | 6247 | (clobber (match_scratch:DI 0 "=d"))] |
ecbe845e | 6248 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" |
ac32b25e | 6249 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6250 | [(set_attr "op_type" "RSE") |
6251 | (set_attr "atype" "reg")]) | |
ecbe845e | 6252 | |
9db1d521 | 6253 | (define_insn "*ashrdi3_64" |
ac32b25e UW |
6254 | [(set (match_operand:DI 0 "register_operand" "=d") |
6255 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
6256 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
9db1d521 HP |
6257 | (clobber (reg:CC 33))] |
6258 | "TARGET_64BIT" | |
ac32b25e | 6259 | "srag\t%0,%1,%Y2" |
077dab3b HP |
6260 | [(set_attr "op_type" "RSE") |
6261 | (set_attr "atype" "reg")]) | |
6262 | ||
9db1d521 HP |
6263 | |
6264 | ; | |
6265 | ; ashlsi3 instruction pattern(s). | |
6266 | ; | |
9db1d521 HP |
6267 | |
6268 | (define_insn "ashlsi3" | |
ac32b25e UW |
6269 | [(set (match_operand:SI 0 "register_operand" "=d") |
6270 | (ashift:SI (match_operand:SI 1 "register_operand" "0") | |
6271 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6272 | "" |
ac32b25e | 6273 | "sll\t%0,%Y2" |
077dab3b HP |
6274 | [(set_attr "op_type" "RS") |
6275 | (set_attr "atype" "reg")]) | |
9db1d521 HP |
6276 | |
6277 | ; | |
6278 | ; ashrsi3 instruction pattern(s). | |
6279 | ; | |
6280 | ||
ecbe845e UW |
6281 | (define_insn "*ashrsi3_cc" |
6282 | [(set (reg 33) | |
ac32b25e UW |
6283 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") |
6284 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6285 | (const_int 0))) |
ac32b25e | 6286 | (set (match_operand:SI 0 "register_operand" "=d") |
ecbe845e UW |
6287 | (ashiftrt:SI (match_dup 1) (match_dup 2)))] |
6288 | "s390_match_ccmode(insn, CCSmode)" | |
ac32b25e | 6289 | "sra\t%0,%Y2" |
077dab3b HP |
6290 | [(set_attr "op_type" "RS") |
6291 | (set_attr "atype" "reg")]) | |
6292 | ||
ecbe845e UW |
6293 | |
6294 | (define_insn "*ashrsi3_cconly" | |
6295 | [(set (reg 33) | |
ac32b25e UW |
6296 | (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") |
6297 | (match_operand:SI 2 "shift_count_operand" "Y")) | |
ecbe845e | 6298 | (const_int 0))) |
ac32b25e | 6299 | (clobber (match_scratch:SI 0 "=d"))] |
ecbe845e | 6300 | "s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 6301 | "sra\t%0,%Y2" |
077dab3b HP |
6302 | [(set_attr "op_type" "RS") |
6303 | (set_attr "atype" "reg")]) | |
ecbe845e | 6304 | |
9db1d521 | 6305 | (define_insn "ashrsi3" |
ac32b25e UW |
6306 | [(set (match_operand:SI 0 "register_operand" "=d") |
6307 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
6308 | (match_operand:SI 2 "shift_count_operand" "Y"))) | |
9db1d521 HP |
6309 | (clobber (reg:CC 33))] |
6310 | "" | |
ac32b25e | 6311 | "sra\t%0,%Y2" |
077dab3b HP |
6312 | [(set_attr "op_type" "RS") |
6313 | (set_attr "atype" "reg")]) | |
9db1d521 | 6314 | |
9db1d521 HP |
6315 | |
6316 | ;; | |
6317 | ;;- logical shift instructions. | |
6318 | ;; | |
6319 | ||
6320 | ; | |
6321 | ; lshrdi3 instruction pattern(s). | |
6322 | ; | |
6323 | ||
6324 | (define_expand "lshrdi3" | |
ecbe845e UW |
6325 | [(set (match_operand:DI 0 "register_operand" "") |
6326 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
ac32b25e | 6327 | (match_operand:SI 2 "shift_count_operand" "")))] |
9db1d521 HP |
6328 | "" |
6329 | "") | |
6330 | ||
6331 | (define_insn "*lshrdi3_31" | |
ac32b25e UW |
6332 | [(set (match_operand:DI 0 "register_operand" "=d") |
6333 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
6334 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6335 | "!TARGET_64BIT" |
ac32b25e UW |
6336 | "srdl\t%0,%Y2" |
6337 | [(set_attr "op_type" "RS") | |
077dab3b | 6338 | (set_attr "atype" "reg")]) |
9db1d521 HP |
6339 | |
6340 | (define_insn "*lshrdi3_64" | |
ac32b25e UW |
6341 | [(set (match_operand:DI 0 "register_operand" "=d") |
6342 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") | |
6343 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6344 | "TARGET_64BIT" |
ac32b25e UW |
6345 | "srlg\t%0,%1,%Y2" |
6346 | [(set_attr "op_type" "RSE") | |
077dab3b | 6347 | (set_attr "atype" "reg")]) |
9db1d521 HP |
6348 | |
6349 | ; | |
6350 | ; lshrsi3 instruction pattern(s). | |
6351 | ; | |
6352 | ||
6353 | (define_insn "lshrsi3" | |
ac32b25e UW |
6354 | [(set (match_operand:SI 0 "register_operand" "=d") |
6355 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") | |
6356 | (match_operand:SI 2 "shift_count_operand" "Y")))] | |
9db1d521 | 6357 | "" |
ac32b25e | 6358 | "srl\t%0,%Y2" |
077dab3b HP |
6359 | [(set_attr "op_type" "RS") |
6360 | (set_attr "atype" "reg")]) | |
9db1d521 | 6361 | |
9db1d521 HP |
6362 | |
6363 | ;; | |
6364 | ;; Branch instruction patterns. | |
6365 | ;; | |
6366 | ||
6367 | (define_expand "beq" | |
6368 | [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2))) | |
6369 | (set (pc) | |
6370 | (if_then_else (eq (reg:CCZ 33) (const_int 0)) | |
6371 | (label_ref (match_operand 0 "" "")) | |
6372 | (pc)))] | |
6373 | "" | |
10bbf137 | 6374 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
6375 | |
6376 | (define_expand "bne" | |
6377 | [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2))) | |
6378 | (set (pc) | |
6379 | (if_then_else (ne (reg:CCZ 33) (const_int 0)) | |
6380 | (label_ref (match_operand 0 "" "")) | |
6381 | (pc)))] | |
6382 | "" | |
10bbf137 | 6383 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
6384 | |
6385 | (define_expand "bgt" | |
6386 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6387 | (set (pc) | |
6388 | (if_then_else (gt (reg:CCS 33) (const_int 0)) | |
6389 | (label_ref (match_operand 0 "" "")) | |
6390 | (pc)))] | |
6391 | "" | |
10bbf137 | 6392 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
6393 | |
6394 | (define_expand "bgtu" | |
6395 | [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) | |
6396 | (set (pc) | |
6397 | (if_then_else (gtu (reg:CCU 33) (const_int 0)) | |
6398 | (label_ref (match_operand 0 "" "")) | |
6399 | (pc)))] | |
6400 | "" | |
10bbf137 | 6401 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
6402 | |
6403 | (define_expand "blt" | |
6404 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6405 | (set (pc) | |
6406 | (if_then_else (lt (reg:CCS 33) (const_int 0)) | |
6407 | (label_ref (match_operand 0 "" "")) | |
6408 | (pc)))] | |
6409 | "" | |
10bbf137 | 6410 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
6411 | |
6412 | (define_expand "bltu" | |
6413 | [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) | |
6414 | (set (pc) | |
6415 | (if_then_else (ltu (reg:CCU 33) (const_int 0)) | |
6416 | (label_ref (match_operand 0 "" "")) | |
6417 | (pc)))] | |
6418 | "" | |
10bbf137 | 6419 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
6420 | |
6421 | (define_expand "bge" | |
6422 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6423 | (set (pc) | |
6424 | (if_then_else (ge (reg:CCS 33) (const_int 0)) | |
6425 | (label_ref (match_operand 0 "" "")) | |
6426 | (pc)))] | |
6427 | "" | |
10bbf137 | 6428 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
6429 | |
6430 | (define_expand "bgeu" | |
6431 | [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) | |
6432 | (set (pc) | |
6433 | (if_then_else (geu (reg:CCU 33) (const_int 0)) | |
6434 | (label_ref (match_operand 0 "" "")) | |
6435 | (pc)))] | |
6436 | "" | |
10bbf137 | 6437 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
6438 | |
6439 | (define_expand "ble" | |
6440 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6441 | (set (pc) | |
6442 | (if_then_else (le (reg:CCS 33) (const_int 0)) | |
6443 | (label_ref (match_operand 0 "" "")) | |
6444 | (pc)))] | |
6445 | "" | |
10bbf137 | 6446 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 HP |
6447 | |
6448 | (define_expand "bleu" | |
6449 | [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) | |
6450 | (set (pc) | |
6451 | (if_then_else (leu (reg:CCU 33) (const_int 0)) | |
6452 | (label_ref (match_operand 0 "" "")) | |
6453 | (pc)))] | |
6454 | "" | |
10bbf137 | 6455 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
9db1d521 | 6456 | |
ba956982 UW |
6457 | (define_expand "bunordered" |
6458 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6459 | (set (pc) | |
6460 | (if_then_else (unordered (reg:CCS 33) (const_int 0)) | |
6461 | (label_ref (match_operand 0 "" "")) | |
6462 | (pc)))] | |
6463 | "" | |
10bbf137 | 6464 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
6465 | |
6466 | (define_expand "bordered" | |
6467 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6468 | (set (pc) | |
6469 | (if_then_else (ordered (reg:CCS 33) (const_int 0)) | |
6470 | (label_ref (match_operand 0 "" "")) | |
6471 | (pc)))] | |
6472 | "" | |
10bbf137 | 6473 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
6474 | |
6475 | (define_expand "buneq" | |
6476 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6477 | (set (pc) | |
6478 | (if_then_else (uneq (reg:CCS 33) (const_int 0)) | |
6479 | (label_ref (match_operand 0 "" "")) | |
6480 | (pc)))] | |
6481 | "" | |
10bbf137 | 6482 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
6483 | |
6484 | (define_expand "bungt" | |
6485 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6486 | (set (pc) | |
6487 | (if_then_else (ungt (reg:CCS 33) (const_int 0)) | |
6488 | (label_ref (match_operand 0 "" "")) | |
6489 | (pc)))] | |
6490 | "" | |
10bbf137 | 6491 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
6492 | |
6493 | (define_expand "bunlt" | |
6494 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6495 | (set (pc) | |
6496 | (if_then_else (unlt (reg:CCS 33) (const_int 0)) | |
6497 | (label_ref (match_operand 0 "" "")) | |
6498 | (pc)))] | |
6499 | "" | |
10bbf137 | 6500 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
6501 | |
6502 | (define_expand "bunge" | |
6503 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6504 | (set (pc) | |
6505 | (if_then_else (unge (reg:CCS 33) (const_int 0)) | |
6506 | (label_ref (match_operand 0 "" "")) | |
6507 | (pc)))] | |
6508 | "" | |
10bbf137 | 6509 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
6510 | |
6511 | (define_expand "bunle" | |
6512 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6513 | (set (pc) | |
6514 | (if_then_else (unle (reg:CCS 33) (const_int 0)) | |
6515 | (label_ref (match_operand 0 "" "")) | |
6516 | (pc)))] | |
6517 | "" | |
10bbf137 | 6518 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 UW |
6519 | |
6520 | (define_expand "bltgt" | |
6521 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
6522 | (set (pc) | |
6523 | (if_then_else (ltgt (reg:CCS 33) (const_int 0)) | |
6524 | (label_ref (match_operand 0 "" "")) | |
6525 | (pc)))] | |
6526 | "" | |
10bbf137 | 6527 | "operands[1] = s390_compare_op0; operands[2] = s390_compare_op1;") |
ba956982 | 6528 | |
9db1d521 HP |
6529 | |
6530 | ;; | |
6531 | ;;- Conditional jump instructions. | |
6532 | ;; | |
6533 | ||
6534 | (define_insn "cjump" | |
6535 | [(set (pc) | |
c7453384 | 6536 | (if_then_else |
9db1d521 HP |
6537 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) |
6538 | (label_ref (match_operand 0 "" "")) | |
6539 | (pc)))] | |
6540 | "" | |
9db1d521 | 6541 | { |
13e58269 | 6542 | if (get_attr_length (insn) == 4) |
d40c829f | 6543 | return "j%C1\t%l0"; |
9e8327e3 | 6544 | else if (TARGET_CPU_ZARCH) |
d40c829f | 6545 | return "jg%C1\t%l0"; |
9db1d521 | 6546 | else |
13e58269 | 6547 | abort (); |
10bbf137 | 6548 | } |
9db1d521 | 6549 | [(set_attr "op_type" "RI") |
077dab3b | 6550 | (set_attr "type" "branch") |
13e58269 UW |
6551 | (set (attr "length") |
6552 | (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6553 | (const_int 4) | |
9e8327e3 | 6554 | (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) |
13e58269 UW |
6555 | (const_int 6) |
6556 | (eq (symbol_ref "flag_pic") (const_int 0)) | |
6557 | (const_int 6)] (const_int 8)))]) | |
9db1d521 | 6558 | |
f314b9b1 | 6559 | (define_insn "*cjump_long" |
9db1d521 HP |
6560 | [(set (pc) |
6561 | (if_then_else | |
6562 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
d3632d41 | 6563 | (match_operand 0 "address_operand" "U") |
9db1d521 HP |
6564 | (pc)))] |
6565 | "" | |
f314b9b1 UW |
6566 | { |
6567 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6568 | return "b%C1r\t%0"; |
f314b9b1 | 6569 | else |
d40c829f | 6570 | return "b%C1\t%a0"; |
10bbf137 | 6571 | } |
c7453384 | 6572 | [(set (attr "op_type") |
f314b9b1 UW |
6573 | (if_then_else (match_operand 0 "register_operand" "") |
6574 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6575 | (set_attr "type" "branch") |
6576 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
6577 | |
6578 | ||
6579 | ;; | |
6580 | ;;- Negated conditional jump instructions. | |
6581 | ;; | |
6582 | ||
6583 | (define_insn "icjump" | |
6584 | [(set (pc) | |
6585 | (if_then_else | |
6586 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
c7453384 | 6587 | (pc) |
9db1d521 HP |
6588 | (label_ref (match_operand 0 "" ""))))] |
6589 | "" | |
c7453384 | 6590 | { |
13e58269 | 6591 | if (get_attr_length (insn) == 4) |
d40c829f | 6592 | return "j%D1\t%l0"; |
9e8327e3 | 6593 | else if (TARGET_CPU_ZARCH) |
d40c829f | 6594 | return "jg%D1\t%l0"; |
9db1d521 | 6595 | else |
13e58269 | 6596 | abort (); |
10bbf137 | 6597 | } |
9db1d521 | 6598 | [(set_attr "op_type" "RI") |
077dab3b | 6599 | (set_attr "type" "branch") |
13e58269 UW |
6600 | (set (attr "length") |
6601 | (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6602 | (const_int 4) | |
9e8327e3 | 6603 | (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) |
13e58269 UW |
6604 | (const_int 6) |
6605 | (eq (symbol_ref "flag_pic") (const_int 0)) | |
6606 | (const_int 6)] (const_int 8)))]) | |
9db1d521 | 6607 | |
f314b9b1 | 6608 | (define_insn "*icjump_long" |
9db1d521 HP |
6609 | [(set (pc) |
6610 | (if_then_else | |
6611 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
f314b9b1 | 6612 | (pc) |
d3632d41 | 6613 | (match_operand 0 "address_operand" "U")))] |
9db1d521 | 6614 | "" |
f314b9b1 UW |
6615 | { |
6616 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6617 | return "b%D1r\t%0"; |
f314b9b1 | 6618 | else |
d40c829f | 6619 | return "b%D1\t%a0"; |
10bbf137 | 6620 | } |
c7453384 | 6621 | [(set (attr "op_type") |
f314b9b1 UW |
6622 | (if_then_else (match_operand 0 "register_operand" "") |
6623 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6624 | (set_attr "type" "branch") |
6625 | (set_attr "atype" "agen")]) | |
9db1d521 | 6626 | |
4456530d HP |
6627 | ;; |
6628 | ;;- Trap instructions. | |
6629 | ;; | |
6630 | ||
6631 | (define_insn "trap" | |
6632 | [(trap_if (const_int 1) (const_int 0))] | |
6633 | "" | |
d40c829f | 6634 | "j\t.+2" |
077dab3b HP |
6635 | [(set_attr "op_type" "RX") |
6636 | (set_attr "type" "branch")]) | |
4456530d HP |
6637 | |
6638 | (define_expand "conditional_trap" | |
6639 | [(set (match_dup 2) (match_dup 3)) | |
6640 | (trap_if (match_operator 0 "comparison_operator" | |
6641 | [(match_dup 2) (const_int 0)]) | |
6642 | (match_operand:SI 1 "general_operand" ""))] | |
6643 | "" | |
4456530d HP |
6644 | { |
6645 | enum machine_mode ccmode; | |
6646 | ||
c7453384 | 6647 | if (operands[1] != const0_rtx) FAIL; |
4456530d | 6648 | |
c7453384 EC |
6649 | ccmode = s390_select_ccmode (GET_CODE (operands[0]), |
6650 | s390_compare_op0, s390_compare_op1); | |
4456530d HP |
6651 | operands[2] = gen_rtx_REG (ccmode, 33); |
6652 | operands[3] = gen_rtx_COMPARE (ccmode, s390_compare_op0, s390_compare_op1); | |
10bbf137 | 6653 | }) |
4456530d HP |
6654 | |
6655 | (define_insn "*trap" | |
6656 | [(trap_if (match_operator 0 "comparison_operator" [(reg 33) (const_int 0)]) | |
6657 | (const_int 0))] | |
6658 | "" | |
d40c829f | 6659 | "j%C0\t.+2"; |
077dab3b HP |
6660 | [(set_attr "op_type" "RI") |
6661 | (set_attr "type" "branch")]) | |
9db1d521 HP |
6662 | |
6663 | ;; | |
0a3bdf9d | 6664 | ;;- Loop instructions. |
9db1d521 | 6665 | ;; |
0a3bdf9d UW |
6666 | ;; This is all complicated by the fact that since this is a jump insn |
6667 | ;; we must handle our own output reloads. | |
c7453384 | 6668 | |
0a3bdf9d UW |
6669 | (define_expand "doloop_end" |
6670 | [(use (match_operand 0 "" "")) ; loop pseudo | |
6671 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
6672 | (use (match_operand 2 "" "")) ; max iterations | |
6673 | (use (match_operand 3 "" "")) ; loop level | |
6674 | (use (match_operand 4 "" ""))] ; label | |
6675 | "" | |
0a3bdf9d UW |
6676 | { |
6677 | if (GET_MODE (operands[0]) == SImode) | |
6678 | emit_jump_insn (gen_doloop_si (operands[4], operands[0], operands[0])); | |
6679 | else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) | |
6680 | emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); | |
6681 | else | |
6682 | FAIL; | |
6683 | ||
6684 | DONE; | |
10bbf137 | 6685 | }) |
0a3bdf9d UW |
6686 | |
6687 | (define_insn "doloop_si" | |
6688 | [(set (pc) | |
6689 | (if_then_else | |
6690 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6691 | (const_int 1)) | |
6692 | (label_ref (match_operand 0 "" "")) | |
6693 | (pc))) | |
bd446804 | 6694 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") |
0a3bdf9d UW |
6695 | (plus:SI (match_dup 1) (const_int -1))) |
6696 | (clobber (match_scratch:SI 3 "=X,&d")) | |
6697 | (clobber (reg:CC 33))] | |
6698 | "" | |
0a3bdf9d UW |
6699 | { |
6700 | if (which_alternative != 0) | |
10bbf137 | 6701 | return "#"; |
0a3bdf9d | 6702 | else if (get_attr_length (insn) == 4) |
d40c829f | 6703 | return "brct\t%1,%l0"; |
545d16ff UW |
6704 | else if (TARGET_CPU_ZARCH) |
6705 | return "ahi\t%1,-1\;jgne\t%l0"; | |
0a3bdf9d UW |
6706 | else |
6707 | abort (); | |
10bbf137 | 6708 | } |
0a3bdf9d | 6709 | [(set_attr "op_type" "RI") |
077dab3b | 6710 | (set_attr "type" "branch") |
0a3bdf9d UW |
6711 | (set (attr "length") |
6712 | (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6713 | (const_int 4) | |
9e8327e3 | 6714 | (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) |
0a3bdf9d | 6715 | (const_int 10) |
0a3bdf9d UW |
6716 | (eq (symbol_ref "flag_pic") (const_int 0)) |
6717 | (const_int 6)] (const_int 8)))]) | |
9db1d521 | 6718 | |
0a3bdf9d UW |
6719 | (define_insn "*doloop_si_long" |
6720 | [(set (pc) | |
6721 | (if_then_else | |
6722 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6723 | (const_int 1)) | |
d3632d41 | 6724 | (match_operand 0 "address_operand" "U,U") |
0a3bdf9d UW |
6725 | (pc))) |
6726 | (set (match_operand:SI 2 "register_operand" "=1,?*m*d") | |
6727 | (plus:SI (match_dup 1) (const_int -1))) | |
6728 | (clobber (match_scratch:SI 3 "=X,&d")) | |
6729 | (clobber (reg:CC 33))] | |
6730 | "" | |
0a3bdf9d UW |
6731 | { |
6732 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6733 | return "bctr\t%1,%0"; |
0a3bdf9d | 6734 | else |
d40c829f | 6735 | return "bct\t%1,%a0"; |
10bbf137 | 6736 | } |
c7453384 | 6737 | [(set (attr "op_type") |
0a3bdf9d UW |
6738 | (if_then_else (match_operand 0 "register_operand" "") |
6739 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6740 | (set_attr "type" "branch") |
6741 | (set_attr "atype" "agen")]) | |
0a3bdf9d UW |
6742 | |
6743 | (define_split | |
6744 | [(set (pc) | |
6745 | (if_then_else (ne (match_operand:SI 1 "register_operand" "") | |
6746 | (const_int 1)) | |
6747 | (match_operand 0 "" "") | |
6748 | (pc))) | |
6749 | (set (match_operand:SI 2 "nonimmediate_operand" "") | |
6750 | (plus:SI (match_dup 1) (const_int -1))) | |
6751 | (clobber (match_scratch:SI 3 "")) | |
6752 | (clobber (reg:CC 33))] | |
6753 | "reload_completed | |
6754 | && (! REG_P (operands[2]) | |
6755 | || ! rtx_equal_p (operands[1], operands[2]))" | |
6756 | [(set (match_dup 3) (match_dup 1)) | |
6757 | (parallel [(set (reg:CCAN 33) | |
6758 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) | |
6759 | (const_int 0))) | |
6760 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
6761 | (set (match_dup 2) (match_dup 3)) | |
6762 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
6763 | (match_dup 0) | |
6764 | (pc)))] | |
6765 | "") | |
9db1d521 | 6766 | |
0a3bdf9d UW |
6767 | (define_insn "doloop_di" |
6768 | [(set (pc) | |
6769 | (if_then_else | |
6770 | (ne (match_operand:DI 1 "register_operand" "d,d") | |
6771 | (const_int 1)) | |
6772 | (label_ref (match_operand 0 "" "")) | |
6773 | (pc))) | |
bd446804 | 6774 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*r") |
0a3bdf9d UW |
6775 | (plus:DI (match_dup 1) (const_int -1))) |
6776 | (clobber (match_scratch:DI 3 "=X,&d")) | |
6777 | (clobber (reg:CC 33))] | |
6778 | "TARGET_64BIT" | |
0a3bdf9d UW |
6779 | { |
6780 | if (which_alternative != 0) | |
10bbf137 | 6781 | return "#"; |
0a3bdf9d | 6782 | else if (get_attr_length (insn) == 4) |
d40c829f | 6783 | return "brctg\t%1,%l0"; |
0a3bdf9d | 6784 | else |
545d16ff | 6785 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 6786 | } |
0a3bdf9d | 6787 | [(set_attr "op_type" "RI") |
077dab3b | 6788 | (set_attr "type" "branch") |
0a3bdf9d UW |
6789 | (set (attr "length") |
6790 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
545d16ff | 6791 | (const_int 4) (const_int 10)))]) |
0a3bdf9d UW |
6792 | |
6793 | (define_split | |
6794 | [(set (pc) | |
6795 | (if_then_else (ne (match_operand:DI 1 "register_operand" "") | |
6796 | (const_int 1)) | |
6797 | (match_operand 0 "" "") | |
6798 | (pc))) | |
6799 | (set (match_operand:DI 2 "nonimmediate_operand" "") | |
6800 | (plus:DI (match_dup 1) (const_int -1))) | |
6801 | (clobber (match_scratch:DI 3 "")) | |
6802 | (clobber (reg:CC 33))] | |
6803 | "reload_completed | |
6804 | && (! REG_P (operands[2]) | |
6805 | || ! rtx_equal_p (operands[1], operands[2]))" | |
6806 | [(set (match_dup 3) (match_dup 1)) | |
6807 | (parallel [(set (reg:CCAN 33) | |
6808 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) | |
6809 | (const_int 0))) | |
6810 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
6811 | (set (match_dup 2) (match_dup 3)) | |
6812 | (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0)) | |
6813 | (match_dup 0) | |
6814 | (pc)))] | |
6815 | "") | |
9db1d521 HP |
6816 | |
6817 | ;; | |
6818 | ;;- Unconditional jump instructions. | |
6819 | ;; | |
6820 | ||
6821 | ; | |
6822 | ; jump instruction pattern(s). | |
6823 | ; | |
6824 | ||
6825 | (define_insn "jump" | |
6826 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
6827 | "" | |
9db1d521 | 6828 | { |
13e58269 | 6829 | if (get_attr_length (insn) == 4) |
d40c829f | 6830 | return "j\t%l0"; |
9e8327e3 | 6831 | else if (TARGET_CPU_ZARCH) |
d40c829f | 6832 | return "jg\t%l0"; |
9db1d521 | 6833 | else |
13e58269 | 6834 | abort (); |
10bbf137 | 6835 | } |
9db1d521 | 6836 | [(set_attr "op_type" "RI") |
077dab3b | 6837 | (set_attr "type" "branch") |
13e58269 UW |
6838 | (set (attr "length") |
6839 | (cond [(lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6840 | (const_int 4) | |
9e8327e3 | 6841 | (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) |
13e58269 UW |
6842 | (const_int 6) |
6843 | (eq (symbol_ref "flag_pic") (const_int 0)) | |
6844 | (const_int 6)] (const_int 8)))]) | |
9db1d521 HP |
6845 | |
6846 | ; | |
6847 | ; indirect-jump instruction pattern(s). | |
6848 | ; | |
6849 | ||
6850 | (define_insn "indirect_jump" | |
d3632d41 | 6851 | [(set (pc) (match_operand 0 "address_operand" "U"))] |
9db1d521 | 6852 | "" |
f314b9b1 UW |
6853 | { |
6854 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6855 | return "br\t%0"; |
f314b9b1 | 6856 | else |
d40c829f | 6857 | return "b\t%a0"; |
10bbf137 | 6858 | } |
c7453384 | 6859 | [(set (attr "op_type") |
f314b9b1 UW |
6860 | (if_then_else (match_operand 0 "register_operand" "") |
6861 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6862 | (set_attr "type" "branch") |
6863 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
6864 | |
6865 | ; | |
f314b9b1 | 6866 | ; casesi instruction pattern(s). |
9db1d521 HP |
6867 | ; |
6868 | ||
f314b9b1 | 6869 | (define_insn "casesi_jump" |
d3632d41 | 6870 | [(set (pc) (match_operand 0 "address_operand" "U")) |
f314b9b1 | 6871 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 6872 | "" |
9db1d521 | 6873 | { |
f314b9b1 | 6874 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 6875 | return "br\t%0"; |
f314b9b1 | 6876 | else |
d40c829f | 6877 | return "b\t%a0"; |
10bbf137 | 6878 | } |
c7453384 | 6879 | [(set (attr "op_type") |
f314b9b1 UW |
6880 | (if_then_else (match_operand 0 "register_operand" "") |
6881 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6882 | (set_attr "type" "branch") |
6883 | (set_attr "atype" "agen")]) | |
9db1d521 | 6884 | |
f314b9b1 UW |
6885 | (define_expand "casesi" |
6886 | [(match_operand:SI 0 "general_operand" "") | |
6887 | (match_operand:SI 1 "general_operand" "") | |
6888 | (match_operand:SI 2 "general_operand" "") | |
6889 | (label_ref (match_operand 3 "" "")) | |
6890 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 6891 | "" |
f314b9b1 UW |
6892 | { |
6893 | rtx index = gen_reg_rtx (SImode); | |
6894 | rtx base = gen_reg_rtx (Pmode); | |
6895 | rtx target = gen_reg_rtx (Pmode); | |
6896 | ||
6897 | emit_move_insn (index, operands[0]); | |
6898 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
6899 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 6900 | operands[4]); |
f314b9b1 UW |
6901 | |
6902 | if (Pmode != SImode) | |
6903 | index = convert_to_mode (Pmode, index, 1); | |
6904 | if (GET_CODE (index) != REG) | |
6905 | index = copy_to_mode_reg (Pmode, index); | |
6906 | ||
6907 | if (TARGET_64BIT) | |
6908 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
6909 | else | |
a556fd39 | 6910 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 6911 | |
f314b9b1 UW |
6912 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
6913 | ||
6914 | index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index)); | |
cfa29496 UW |
6915 | RTX_UNCHANGING_P (index) = 1; |
6916 | MEM_NOTRAP_P (index) = 1; | |
f314b9b1 UW |
6917 | emit_move_insn (target, index); |
6918 | ||
6919 | if (flag_pic) | |
6920 | target = gen_rtx_PLUS (Pmode, base, target); | |
6921 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
6922 | ||
6923 | DONE; | |
10bbf137 | 6924 | }) |
9db1d521 HP |
6925 | |
6926 | ||
6927 | ;; | |
6928 | ;;- Jump to subroutine. | |
6929 | ;; | |
6930 | ;; | |
6931 | ||
6932 | ; | |
6933 | ; untyped call instruction pattern(s). | |
6934 | ; | |
6935 | ||
6936 | ;; Call subroutine returning any type. | |
6937 | (define_expand "untyped_call" | |
6938 | [(parallel [(call (match_operand 0 "" "") | |
6939 | (const_int 0)) | |
6940 | (match_operand 1 "" "") | |
6941 | (match_operand 2 "" "")])] | |
6942 | "" | |
9db1d521 HP |
6943 | { |
6944 | int i; | |
6945 | ||
6946 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
6947 | ||
6948 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
6949 | { | |
6950 | rtx set = XVECEXP (operands[2], 0, i); | |
6951 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
6952 | } | |
6953 | ||
6954 | /* The optimizer does not know that the call sets the function value | |
6955 | registers we stored in the result block. We avoid problems by | |
6956 | claiming that all hard registers are used and clobbered at this | |
6957 | point. */ | |
6958 | emit_insn (gen_blockage ()); | |
6959 | ||
6960 | DONE; | |
10bbf137 | 6961 | }) |
9db1d521 HP |
6962 | |
6963 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
6964 | ;; all of memory. This blocks insns from being moved across this point. | |
6965 | ||
6966 | (define_insn "blockage" | |
10bbf137 | 6967 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 6968 | "" |
4023fb28 | 6969 | "" |
d5869ca0 UW |
6970 | [(set_attr "type" "none") |
6971 | (set_attr "length" "0")]) | |
4023fb28 | 6972 | |
9db1d521 HP |
6973 | |
6974 | ||
6975 | ; | |
6976 | ; call instruction pattern(s). | |
6977 | ; | |
6978 | ||
6979 | (define_expand "call" | |
44b8152b UW |
6980 | [(call (match_operand 0 "" "") |
6981 | (match_operand 1 "" "")) | |
6982 | (use (match_operand 2 "" ""))] | |
9db1d521 | 6983 | "" |
9db1d521 | 6984 | { |
9e8327e3 | 6985 | bool plt_call = false; |
44b8152b | 6986 | rtx insn; |
9db1d521 HP |
6987 | |
6988 | /* Direct function calls need special treatment. */ | |
6989 | if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) | |
6990 | { | |
6991 | rtx sym = XEXP (operands[0], 0); | |
6992 | ||
6993 | /* When calling a global routine in PIC mode, we must | |
6994 | replace the symbol itself with the PLT stub. */ | |
114278e7 | 6995 | if (flag_pic && !SYMBOL_REF_LOCAL_P (sym)) |
9db1d521 | 6996 | { |
fd7643fb | 6997 | sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT); |
9db1d521 | 6998 | sym = gen_rtx_CONST (Pmode, sym); |
9e8327e3 | 6999 | plt_call = true; |
9db1d521 HP |
7000 | } |
7001 | ||
c7453384 | 7002 | /* Unless we can use the bras(l) insn, force the |
9db1d521 | 7003 | routine address into a register. */ |
9e8327e3 | 7004 | if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH) |
fd7643fb UW |
7005 | { |
7006 | if (flag_pic) | |
7007 | sym = legitimize_pic_address (sym, 0); | |
7008 | else | |
7009 | sym = force_reg (Pmode, sym); | |
7010 | } | |
9db1d521 HP |
7011 | |
7012 | operands[0] = gen_rtx_MEM (QImode, sym); | |
7013 | } | |
44b8152b UW |
7014 | |
7015 | /* Emit insn. */ | |
7016 | insn = emit_call_insn (gen_call_exp (operands[0], operands[1], | |
7017 | gen_rtx_REG (Pmode, RETURN_REGNUM))); | |
9e8327e3 UW |
7018 | |
7019 | /* 31-bit PLT stubs use the GOT register implicitly. */ | |
7020 | if (!TARGET_64BIT && plt_call) | |
7021 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); | |
7022 | ||
44b8152b | 7023 | DONE; |
10bbf137 | 7024 | }) |
9db1d521 | 7025 | |
44b8152b UW |
7026 | (define_expand "call_exp" |
7027 | [(parallel [(call (match_operand 0 "" "") | |
7028 | (match_operand 1 "" "")) | |
7029 | (clobber (match_operand 2 "" ""))])] | |
7030 | "" | |
7031 | "") | |
7032 | ||
9e8327e3 UW |
7033 | (define_insn "*bras" |
7034 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7035 | (match_operand 1 "const_int_operand" "n")) | |
7036 | (clobber (match_operand 2 "register_operand" "=r"))] | |
7037 | "TARGET_SMALL_EXEC && GET_MODE (operands[2]) == Pmode" | |
d40c829f | 7038 | "bras\t%2,%0" |
9db1d521 | 7039 | [(set_attr "op_type" "RI") |
4023fb28 | 7040 | (set_attr "type" "jsr")]) |
9db1d521 | 7041 | |
9e8327e3 UW |
7042 | (define_insn "*brasl" |
7043 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7044 | (match_operand 1 "const_int_operand" "n")) | |
7045 | (clobber (match_operand 2 "register_operand" "=r"))] | |
7046 | "TARGET_CPU_ZARCH && GET_MODE (operands[2]) == Pmode" | |
7047 | "brasl\t%2,%0" | |
7048 | [(set_attr "op_type" "RIL") | |
077dab3b | 7049 | (set_attr "type" "jsr")]) |
9db1d521 | 7050 | |
9e8327e3 UW |
7051 | (define_insn "*basr" |
7052 | [(call (mem:QI (match_operand 0 "address_operand" "U")) | |
7053 | (match_operand 1 "const_int_operand" "n")) | |
7054 | (clobber (match_operand 2 "register_operand" "=r"))] | |
7055 | "GET_MODE (operands[2]) == Pmode" | |
7056 | { | |
7057 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7058 | return "basr\t%2,%0"; | |
7059 | else | |
7060 | return "bas\t%2,%a0"; | |
7061 | } | |
7062 | [(set (attr "op_type") | |
7063 | (if_then_else (match_operand 0 "register_operand" "") | |
7064 | (const_string "RR") (const_string "RX"))) | |
7065 | (set_attr "type" "jsr") | |
7066 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
7067 | |
7068 | ; | |
7069 | ; call_value instruction pattern(s). | |
7070 | ; | |
7071 | ||
7072 | (define_expand "call_value" | |
44b8152b UW |
7073 | [(set (match_operand 0 "" "") |
7074 | (call (match_operand 1 "" "") | |
7075 | (match_operand 2 "" ""))) | |
7076 | (use (match_operand 3 "" ""))] | |
9db1d521 | 7077 | "" |
9db1d521 | 7078 | { |
9e8327e3 | 7079 | bool plt_call = false; |
44b8152b | 7080 | rtx insn; |
9db1d521 HP |
7081 | |
7082 | /* Direct function calls need special treatment. */ | |
7083 | if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) | |
7084 | { | |
7085 | rtx sym = XEXP (operands[1], 0); | |
7086 | ||
7087 | /* When calling a global routine in PIC mode, we must | |
7088 | replace the symbol itself with the PLT stub. */ | |
114278e7 | 7089 | if (flag_pic && !SYMBOL_REF_LOCAL_P (sym)) |
9db1d521 | 7090 | { |
fd7643fb | 7091 | sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT); |
9db1d521 | 7092 | sym = gen_rtx_CONST (Pmode, sym); |
9e8327e3 | 7093 | plt_call = true; |
9db1d521 HP |
7094 | } |
7095 | ||
c7453384 | 7096 | /* Unless we can use the bras(l) insn, force the |
9db1d521 | 7097 | routine address into a register. */ |
9e8327e3 | 7098 | if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH) |
9db1d521 | 7099 | { |
fd7643fb UW |
7100 | if (flag_pic) |
7101 | sym = legitimize_pic_address (sym, 0); | |
7102 | else | |
7103 | sym = force_reg (Pmode, sym); | |
9db1d521 HP |
7104 | } |
7105 | ||
7106 | operands[1] = gen_rtx_MEM (QImode, sym); | |
7107 | } | |
44b8152b UW |
7108 | |
7109 | /* Emit insn. */ | |
7110 | insn = emit_call_insn ( | |
7111 | gen_call_value_exp (operands[0], operands[1], operands[2], | |
7112 | gen_rtx_REG (Pmode, RETURN_REGNUM))); | |
9e8327e3 UW |
7113 | |
7114 | /* 31-bit PLT stubs use the GOT register implicitly. */ | |
7115 | if (!TARGET_64BIT && plt_call) | |
7116 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); | |
7117 | ||
44b8152b | 7118 | DONE; |
10bbf137 | 7119 | }) |
9db1d521 | 7120 | |
44b8152b UW |
7121 | (define_expand "call_value_exp" |
7122 | [(parallel [(set (match_operand 0 "" "") | |
7123 | (call (match_operand 1 "" "") | |
7124 | (match_operand 2 "" ""))) | |
7125 | (clobber (match_operand 3 "" ""))])] | |
7126 | "" | |
7127 | "") | |
7128 | ||
9e8327e3 | 7129 | (define_insn "*bras_r" |
c19ec8f9 | 7130 | [(set (match_operand 0 "" "") |
9e8327e3 | 7131 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 7132 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 UW |
7133 | (clobber (match_operand 3 "register_operand" "=r"))] |
7134 | "TARGET_SMALL_EXEC && GET_MODE (operands[3]) == Pmode" | |
d40c829f | 7135 | "bras\t%3,%1" |
9db1d521 | 7136 | [(set_attr "op_type" "RI") |
f2d3c02a | 7137 | (set_attr "type" "jsr")]) |
9db1d521 | 7138 | |
9e8327e3 | 7139 | (define_insn "*brasl_r" |
c19ec8f9 | 7140 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7141 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7142 | (match_operand 2 "const_int_operand" "n"))) | |
7143 | (clobber (match_operand 3 "register_operand" "=r"))] | |
7144 | "TARGET_CPU_ZARCH && GET_MODE (operands[3]) == Pmode" | |
7145 | "brasl\t%3,%1" | |
7146 | [(set_attr "op_type" "RIL") | |
077dab3b | 7147 | (set_attr "type" "jsr")]) |
9db1d521 | 7148 | |
9e8327e3 | 7149 | (define_insn "*basr_r" |
c19ec8f9 | 7150 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7151 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
7152 | (match_operand 2 "const_int_operand" "n"))) | |
7153 | (clobber (match_operand 3 "register_operand" "=r"))] | |
7154 | "GET_MODE (operands[3]) == Pmode" | |
7155 | { | |
7156 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7157 | return "basr\t%3,%1"; | |
7158 | else | |
7159 | return "bas\t%3,%a1"; | |
7160 | } | |
7161 | [(set (attr "op_type") | |
7162 | (if_then_else (match_operand 1 "register_operand" "") | |
7163 | (const_string "RR") (const_string "RX"))) | |
7164 | (set_attr "type" "jsr") | |
7165 | (set_attr "atype" "agen")]) | |
9db1d521 | 7166 | |
fd3cd001 UW |
7167 | ;; |
7168 | ;;- Thread-local storage support. | |
7169 | ;; | |
7170 | ||
7171 | (define_insn "get_tp_64" | |
7172 | [(set (match_operand:DI 0 "nonimmediate_operand" "=??d,Q") | |
7173 | (unspec:DI [(const_int 0)] UNSPEC_TP))] | |
7174 | "TARGET_64BIT" | |
7175 | "@ | |
d40c829f UW |
7176 | ear\t%0,%%a0\;sllg\t%0,%0,32\;ear\t%0,%%a1 |
7177 | stam\t%%a0,%%a1,%0" | |
fd3cd001 UW |
7178 | [(set_attr "op_type" "NN,RS") |
7179 | (set_attr "atype" "reg,*") | |
7180 | (set_attr "type" "o3,*") | |
7181 | (set_attr "length" "14,*")]) | |
7182 | ||
7183 | (define_insn "get_tp_31" | |
7184 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,Q") | |
7185 | (unspec:SI [(const_int 0)] UNSPEC_TP))] | |
7186 | "!TARGET_64BIT" | |
7187 | "@ | |
d40c829f UW |
7188 | ear\t%0,%%a0 |
7189 | stam\t%%a0,%%a0,%0" | |
fd3cd001 UW |
7190 | [(set_attr "op_type" "RRE,RS")]) |
7191 | ||
7192 | (define_insn "set_tp_64" | |
7193 | [(unspec_volatile [(match_operand:DI 0 "general_operand" "??d,Q")] UNSPECV_SET_TP) | |
7194 | (clobber (match_scratch:SI 1 "=d,X"))] | |
7195 | "TARGET_64BIT" | |
7196 | "@ | |
d40c829f UW |
7197 | sar\t%%a1,%0\;srlg\t%1,%0,32\;sar\t%%a0,%1 |
7198 | lam\t%%a0,%%a1,%0" | |
fd3cd001 UW |
7199 | [(set_attr "op_type" "NN,RS") |
7200 | (set_attr "atype" "reg,*") | |
7201 | (set_attr "type" "o3,*") | |
7202 | (set_attr "length" "14,*")]) | |
7203 | ||
7204 | (define_insn "set_tp_31" | |
7205 | [(unspec_volatile [(match_operand:SI 0 "general_operand" "d,Q")] UNSPECV_SET_TP)] | |
7206 | "!TARGET_64BIT" | |
7207 | "@ | |
d40c829f UW |
7208 | sar\t%%a0,%0 |
7209 | lam\t%%a0,%%a0,%0" | |
fd3cd001 | 7210 | [(set_attr "op_type" "RRE,RS")]) |
c7453384 | 7211 | |
fd3cd001 UW |
7212 | (define_insn "*tls_load_64" |
7213 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7214 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
7215 | (match_operand:DI 2 "" "")] | |
7216 | UNSPEC_TLS_LOAD))] | |
7217 | "TARGET_64BIT" | |
d40c829f | 7218 | "lg\t%0,%1%J2" |
fd3cd001 UW |
7219 | [(set_attr "op_type" "RXE")]) |
7220 | ||
7221 | (define_insn "*tls_load_31" | |
d3632d41 UW |
7222 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
7223 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
7224 | (match_operand:SI 2 "" "")] |
7225 | UNSPEC_TLS_LOAD))] | |
7226 | "!TARGET_64BIT" | |
d3632d41 | 7227 | "@ |
d40c829f UW |
7228 | l\t%0,%1%J2 |
7229 | ly\t%0,%1%J2" | |
d3632d41 | 7230 | [(set_attr "op_type" "RX,RXY")]) |
fd3cd001 UW |
7231 | |
7232 | (define_expand "call_value_tls" | |
7233 | [(set (match_operand 0 "" "") | |
7234 | (call (const_int 0) (const_int 0))) | |
7235 | (use (match_operand 1 "" ""))] | |
7236 | "" | |
fd3cd001 UW |
7237 | { |
7238 | rtx insn, sym; | |
7239 | ||
7240 | if (!flag_pic) | |
7241 | abort (); | |
7242 | ||
7243 | sym = s390_tls_get_offset (); | |
fd7643fb | 7244 | sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), UNSPEC_PLT); |
fd3cd001 UW |
7245 | sym = gen_rtx_CONST (Pmode, sym); |
7246 | ||
c7453384 | 7247 | /* Unless we can use the bras(l) insn, force the |
fd3cd001 | 7248 | routine address into a register. */ |
9e8327e3 | 7249 | if (!TARGET_SMALL_EXEC && !TARGET_CPU_ZARCH) |
fd3cd001 | 7250 | { |
fd7643fb UW |
7251 | if (flag_pic) |
7252 | sym = legitimize_pic_address (sym, 0); | |
7253 | else | |
7254 | sym = force_reg (Pmode, sym); | |
fd3cd001 UW |
7255 | } |
7256 | ||
7257 | sym = gen_rtx_MEM (QImode, sym); | |
7258 | ||
7259 | /* Emit insn. */ | |
7260 | insn = emit_call_insn ( | |
7261 | gen_call_value_tls_exp (operands[0], sym, const0_rtx, | |
7262 | gen_rtx_REG (Pmode, RETURN_REGNUM), | |
7263 | operands[1])); | |
7264 | ||
7265 | /* The calling convention of __tls_get_offset uses the | |
7266 | GOT register implicitly. */ | |
7267 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); | |
7268 | use_reg (&CALL_INSN_FUNCTION_USAGE (insn), operands[0]); | |
7269 | CONST_OR_PURE_CALL_P (insn) = 1; | |
7270 | ||
7271 | DONE; | |
10bbf137 | 7272 | }) |
fd3cd001 UW |
7273 | |
7274 | (define_expand "call_value_tls_exp" | |
7275 | [(parallel [(set (match_operand 0 "" "") | |
7276 | (call (match_operand 1 "" "") | |
7277 | (match_operand 2 "" ""))) | |
7278 | (clobber (match_operand 3 "" "")) | |
7279 | (use (match_operand 4 "" ""))])] | |
7280 | "" | |
7281 | "") | |
7282 | ||
9e8327e3 | 7283 | (define_insn "*bras_tls" |
c19ec8f9 | 7284 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7285 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7286 | (match_operand 2 "const_int_operand" "n"))) | |
7287 | (clobber (match_operand 3 "register_operand" "=r")) | |
7288 | (use (match_operand 4 "" ""))] | |
7289 | "TARGET_SMALL_EXEC && GET_MODE (operands[3]) == Pmode" | |
d40c829f | 7290 | "bras\t%3,%1%J4" |
fd3cd001 UW |
7291 | [(set_attr "op_type" "RI") |
7292 | (set_attr "type" "jsr")]) | |
7293 | ||
9e8327e3 | 7294 | (define_insn "*brasl_tls" |
c19ec8f9 | 7295 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7296 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7297 | (match_operand 2 "const_int_operand" "n"))) | |
7298 | (clobber (match_operand 3 "register_operand" "=r")) | |
7299 | (use (match_operand 4 "" ""))] | |
7300 | "TARGET_CPU_ZARCH && GET_MODE (operands[3]) == Pmode" | |
7301 | "brasl\t%3,%1%J4" | |
7302 | [(set_attr "op_type" "RIL") | |
fd3cd001 UW |
7303 | (set_attr "type" "jsr")]) |
7304 | ||
9e8327e3 | 7305 | (define_insn "*basr_tls" |
c19ec8f9 | 7306 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7307 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
7308 | (match_operand 2 "const_int_operand" "n"))) | |
7309 | (clobber (match_operand 3 "register_operand" "=r")) | |
7310 | (use (match_operand 4 "" ""))] | |
7311 | "GET_MODE (operands[3]) == Pmode" | |
7312 | { | |
7313 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7314 | return "basr\t%3,%1%J4"; | |
7315 | else | |
7316 | return "bas\t%3,%a1%J4"; | |
7317 | } | |
7318 | [(set (attr "op_type") | |
7319 | (if_then_else (match_operand 1 "register_operand" "") | |
7320 | (const_string "RR") (const_string "RX"))) | |
7321 | (set_attr "type" "jsr") | |
7322 | (set_attr "atype" "agen")]) | |
fd3cd001 | 7323 | |
9db1d521 HP |
7324 | ;; |
7325 | ;;- Miscellaneous instructions. | |
7326 | ;; | |
7327 | ||
7328 | ; | |
7329 | ; allocate stack instruction pattern(s). | |
7330 | ; | |
7331 | ||
7332 | (define_expand "allocate_stack" | |
7333 | [(set (reg 15) | |
7334 | (plus (reg 15) (match_operand 1 "general_operand" ""))) | |
7335 | (set (match_operand 0 "general_operand" "") | |
7336 | (reg 15))] | |
590fcf48 | 7337 | "TARGET_BACKCHAIN" |
9db1d521 | 7338 | { |
f1c25d3b KH |
7339 | rtx stack = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM); |
7340 | rtx chain = gen_rtx_MEM (Pmode, stack); | |
9db1d521 | 7341 | rtx temp = gen_reg_rtx (Pmode); |
c7453384 | 7342 | |
9db1d521 HP |
7343 | emit_move_insn (temp, chain); |
7344 | ||
7345 | if (TARGET_64BIT) | |
7346 | emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1]))); | |
7347 | else | |
7348 | emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1]))); | |
7349 | ||
7350 | emit_move_insn (chain, temp); | |
7351 | ||
c7453384 | 7352 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
9db1d521 | 7353 | DONE; |
10bbf137 | 7354 | }) |
9db1d521 HP |
7355 | |
7356 | ||
7357 | ; | |
43ab026f | 7358 | ; setjmp instruction pattern. |
9db1d521 HP |
7359 | ; |
7360 | ||
9db1d521 | 7361 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 7362 | [(match_operand 0 "" "")] |
f314b9b1 | 7363 | "flag_pic" |
9db1d521 | 7364 | { |
fd7643fb UW |
7365 | s390_load_got (false); |
7366 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); | |
9db1d521 | 7367 | DONE; |
fd7643fb | 7368 | }) |
9db1d521 | 7369 | |
9db1d521 HP |
7370 | ;; These patterns say how to save and restore the stack pointer. We need not |
7371 | ;; save the stack pointer at function level since we are careful to | |
7372 | ;; preserve the backchain. At block level, we have to restore the backchain | |
7373 | ;; when we restore the stack pointer. | |
7374 | ;; | |
7375 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
7376 | ;; backchain and restore both. Note that in the nonlocal case, the | |
7377 | ;; save area is a memory location. | |
7378 | ||
7379 | (define_expand "save_stack_function" | |
7380 | [(match_operand 0 "general_operand" "") | |
7381 | (match_operand 1 "general_operand" "")] | |
7382 | "" | |
7383 | "DONE;") | |
7384 | ||
7385 | (define_expand "restore_stack_function" | |
7386 | [(match_operand 0 "general_operand" "") | |
7387 | (match_operand 1 "general_operand" "")] | |
7388 | "" | |
7389 | "DONE;") | |
7390 | ||
7391 | (define_expand "restore_stack_block" | |
7392 | [(use (match_operand 0 "register_operand" "")) | |
7393 | (set (match_dup 2) (match_dup 3)) | |
7394 | (set (match_dup 0) (match_operand 1 "register_operand" "")) | |
7395 | (set (match_dup 3) (match_dup 2))] | |
7396 | "" | |
9db1d521 HP |
7397 | { |
7398 | operands[2] = gen_reg_rtx (Pmode); | |
7399 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); | |
10bbf137 | 7400 | }) |
9db1d521 HP |
7401 | |
7402 | (define_expand "save_stack_nonlocal" | |
7403 | [(match_operand 0 "memory_operand" "") | |
7404 | (match_operand 1 "register_operand" "")] | |
7405 | "" | |
9db1d521 HP |
7406 | { |
7407 | rtx temp = gen_reg_rtx (Pmode); | |
7408 | ||
43ab026f | 7409 | /* Copy the backchain to the first word, sp to the second and the literal pool |
ff482c8d | 7410 | base to the third. */ |
43ab026f AK |
7411 | emit_move_insn (operand_subword (operands[0], 2, 0, |
7412 | TARGET_64BIT ? OImode : TImode), | |
7413 | gen_rtx_REG (Pmode, BASE_REGISTER)); | |
9db1d521 HP |
7414 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); |
7415 | emit_move_insn (operand_subword (operands[0], 0, 0, | |
43ab026f | 7416 | TARGET_64BIT ? OImode : TImode), |
9db1d521 HP |
7417 | temp); |
7418 | emit_move_insn (operand_subword (operands[0], 1, 0, | |
43ab026f | 7419 | TARGET_64BIT ? OImode : TImode), |
9db1d521 HP |
7420 | operands[1]); |
7421 | DONE; | |
10bbf137 | 7422 | }) |
9db1d521 HP |
7423 | |
7424 | (define_expand "restore_stack_nonlocal" | |
7425 | [(match_operand 0 "register_operand" "") | |
7426 | (match_operand 1 "memory_operand" "")] | |
7427 | "" | |
9db1d521 HP |
7428 | { |
7429 | rtx temp = gen_reg_rtx (Pmode); | |
43ab026f | 7430 | rtx base = gen_rtx_REG (Pmode, BASE_REGISTER); |
9db1d521 | 7431 | |
43ab026f | 7432 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 7433 | literal pool base from the third. */ |
9db1d521 HP |
7434 | emit_move_insn (temp, |
7435 | operand_subword (operands[1], 0, 0, | |
43ab026f | 7436 | TARGET_64BIT ? OImode : TImode)); |
9db1d521 HP |
7437 | emit_move_insn (operands[0], |
7438 | operand_subword (operands[1], 1, 0, | |
43ab026f | 7439 | TARGET_64BIT ? OImode : TImode)); |
9db1d521 | 7440 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); |
43ab026f AK |
7441 | emit_move_insn (base, |
7442 | operand_subword (operands[1], 2, 0, | |
7443 | TARGET_64BIT ? OImode : TImode)); | |
7444 | emit_insn (gen_rtx_USE (VOIDmode, base)); | |
7445 | ||
9db1d521 | 7446 | DONE; |
10bbf137 | 7447 | }) |
9db1d521 HP |
7448 | |
7449 | ||
7450 | ; | |
7451 | ; nop instruction pattern(s). | |
7452 | ; | |
7453 | ||
7454 | (define_insn "nop" | |
7455 | [(const_int 0)] | |
7456 | "" | |
d40c829f | 7457 | "lr\t0,0" |
9db1d521 HP |
7458 | [(set_attr "op_type" "RR")]) |
7459 | ||
7460 | ||
7461 | ; | |
7462 | ; Special literal pool access instruction pattern(s). | |
7463 | ; | |
7464 | ||
416cf582 UW |
7465 | (define_insn "*pool_entry" |
7466 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
7467 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 7468 | "" |
9db1d521 | 7469 | { |
416cf582 UW |
7470 | enum machine_mode mode = GET_MODE (PATTERN (insn)); |
7471 | unsigned int align = GET_MODE_BITSIZE (mode); | |
faeb9bb6 | 7472 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
7473 | return ""; |
7474 | } | |
416cf582 UW |
7475 | [(set_attr "op_type" "NN") |
7476 | (set (attr "length") | |
7477 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) | |
b2ccb744 UW |
7478 | |
7479 | (define_insn "pool_start_31" | |
fd7643fb | 7480 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)] |
9e8327e3 | 7481 | "!TARGET_CPU_ZARCH" |
d40c829f | 7482 | ".align\t4" |
b2ccb744 UW |
7483 | [(set_attr "op_type" "NN") |
7484 | (set_attr "length" "2")]) | |
7485 | ||
7486 | (define_insn "pool_end_31" | |
fd7643fb | 7487 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)] |
9e8327e3 | 7488 | "!TARGET_CPU_ZARCH" |
d40c829f | 7489 | ".align\t2" |
b2ccb744 UW |
7490 | [(set_attr "op_type" "NN") |
7491 | (set_attr "length" "2")]) | |
7492 | ||
7493 | (define_insn "pool_start_64" | |
fd7643fb | 7494 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_START)] |
9e8327e3 | 7495 | "TARGET_CPU_ZARCH" |
d40c829f | 7496 | ".section\t.rodata\;.align\t8" |
b2ccb744 UW |
7497 | [(set_attr "op_type" "NN") |
7498 | (set_attr "length" "0")]) | |
7499 | ||
7500 | (define_insn "pool_end_64" | |
fd7643fb | 7501 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_END)] |
9e8327e3 | 7502 | "TARGET_CPU_ZARCH" |
b2ccb744 UW |
7503 | ".previous" |
7504 | [(set_attr "op_type" "NN") | |
7505 | (set_attr "length" "0")]) | |
7506 | ||
5af2f3d3 | 7507 | (define_insn "main_base_31_small" |
9e8327e3 UW |
7508 | [(set (match_operand 0 "register_operand" "=a") |
7509 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
7510 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
7511 | "basr\t%0,0" |
7512 | [(set_attr "op_type" "RR") | |
7513 | (set_attr "type" "la")]) | |
7514 | ||
7515 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
7516 | [(set (match_operand 0 "register_operand" "=a") |
7517 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 7518 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 7519 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 UW |
7520 | "bras\t%0,%2" |
7521 | [(set_attr "op_type" "RI")]) | |
7522 | ||
7523 | (define_insn "main_base_64" | |
9e8327e3 UW |
7524 | [(set (match_operand 0 "register_operand" "=a") |
7525 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
7526 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
7527 | "larl\t%0,%1" |
7528 | [(set_attr "op_type" "RIL") | |
7529 | (set_attr "type" "larl")]) | |
7530 | ||
7531 | (define_insn "main_pool" | |
7532 | [(unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL)] | |
7533 | "" | |
7534 | "* abort ();" | |
7535 | [(set_attr "op_type" "NN")]) | |
7536 | ||
aee4e0db | 7537 | (define_insn "reload_base_31" |
9e8327e3 UW |
7538 | [(set (match_operand 0 "register_operand" "=a") |
7539 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
7540 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7541 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
9db1d521 | 7542 | [(set_attr "op_type" "NN") |
b2ccb744 UW |
7543 | (set_attr "type" "la") |
7544 | (set_attr "length" "6")]) | |
7545 | ||
aee4e0db | 7546 | (define_insn "reload_base_64" |
9e8327e3 UW |
7547 | [(set (match_operand 0 "register_operand" "=a") |
7548 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
7549 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7550 | "larl\t%0,%1" |
aee4e0db | 7551 | [(set_attr "op_type" "RIL") |
077dab3b | 7552 | (set_attr "type" "larl")]) |
aee4e0db | 7553 | |
aee4e0db | 7554 | (define_insn "pool" |
fd7643fb | 7555 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db UW |
7556 | "" |
7557 | "* abort ();" | |
7558 | [(set_attr "op_type" "NN") | |
7559 | (set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) | |
9db1d521 | 7560 | |
4023fb28 UW |
7561 | ;; |
7562 | ;; Insns related to generating the function prologue and epilogue. | |
7563 | ;; | |
7564 | ||
7565 | ||
7566 | (define_expand "prologue" | |
7567 | [(use (const_int 0))] | |
7568 | "" | |
10bbf137 | 7569 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
7570 | |
7571 | (define_expand "epilogue" | |
7572 | [(use (const_int 1))] | |
7573 | "" | |
10bbf137 | 7574 | "s390_emit_epilogue (); DONE;") |
4023fb28 | 7575 | |
9e8327e3 | 7576 | (define_insn "*return" |
4023fb28 | 7577 | [(return) |
9e8327e3 UW |
7578 | (use (match_operand 0 "register_operand" "a"))] |
7579 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7580 | "br\t%0" |
4023fb28 | 7581 | [(set_attr "op_type" "RR") |
c7453384 | 7582 | (set_attr "type" "jsr") |
077dab3b | 7583 | (set_attr "atype" "agen")]) |
4023fb28 | 7584 | |
4023fb28 | 7585 | |
c7453384 | 7586 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 7587 | ;; pointer. This is used for compatibility. |
c7453384 EC |
7588 | |
7589 | (define_expand "ptr_extend" | |
7590 | [(set (match_operand:DI 0 "register_operand" "=r") | |
7591 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 7592 | "TARGET_64BIT" |
c7453384 | 7593 | { |
c7453384 EC |
7594 | emit_insn (gen_anddi3 (operands[0], |
7595 | gen_lowpart (DImode, operands[1]), | |
7596 | GEN_INT (0x7fffffff))); | |
c7453384 | 7597 | DONE; |
10bbf137 | 7598 | }) |