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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
9c3c3dcc | 2 | ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005 |
283334f0 | 3 | ;; Free Software Foundation, Inc. |
9db1d521 | 4 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
f314b9b1 | 5 | ;; Ulrich Weigand (uweigand@de.ibm.com). |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
11 | ;; Software Foundation; either version 2, or (at your option) any later | |
12 | ;; version. | |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
58add37a | 20 | ;; along with GCC; see the file COPYING. If not, write to the Free |
39d14dda KC |
21 | ;; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA |
22 | ;; 02110-1301, USA. | |
9db1d521 HP |
23 | |
24 | ;; | |
25 | ;; Special constraints for s/390 machine description: | |
26 | ;; | |
27 | ;; a -- Any address register from 1 to 15. | |
9dc62c00 | 28 | ;; c -- Condition code register 33. |
9db1d521 | 29 | ;; d -- Any register from 0 to 15. |
09366c43 AS |
30 | ;; f -- Floating point registers. |
31 | ;; t -- Access registers 36 and 37. | |
d096725d | 32 | ;; G -- Const double zero operand |
9db1d521 HP |
33 | ;; I -- An 8-bit constant (0..255). |
34 | ;; J -- A 12-bit constant (0..4095). | |
35 | ;; K -- A 16-bit constant (-32768..32767). | |
2f7e5a0d | 36 | ;; L -- Value appropriate as displacement. |
f19a9af7 AK |
37 | ;; (0..4095) for short displacement |
38 | ;; (-524288..524287) for long displacement | |
39 | ;; M -- Constant integer with a value of 0x7fffffff. | |
40 | ;; N -- Multiple letter constraint followed by 4 parameter letters. | |
0dfa6c5e UW |
41 | ;; 0..9,x: number of the part counting from most to least significant |
42 | ;; H,Q: mode of the part | |
43 | ;; D,S,H: mode of the containing operand | |
44 | ;; 0,F: value of the other parts (F - all bits set) | |
2f7e5a0d | 45 | ;; |
f19a9af7 | 46 | ;; The constraint matches if the specified part of a constant |
0dfa6c5e UW |
47 | ;; has a value different from its other parts. If the letter x |
48 | ;; is specified instead of a part number, the constraint matches | |
49 | ;; if there is any single part with non-default value. | |
ec24698e UW |
50 | ;; O -- Multiple letter constraint followed by 1 parameter. |
51 | ;; s: Signed extended immediate value (-2G .. 2G-1). | |
52 | ;; p: Positive extended immediate value (0 .. 4G-1). | |
53 | ;; n: Negative extended immediate value (-4G .. -1). | |
54 | ;; These constraints do not accept any operand if the machine does | |
55 | ;; not provide the extended-immediate facility. | |
11598938 | 56 | ;; P -- Any integer constant that can be loaded without literal pool. |
f19a9af7 AK |
57 | ;; Q -- Memory reference without index register and with short displacement. |
58 | ;; R -- Memory reference with index register and short displacement. | |
59 | ;; S -- Memory reference without index register but with long displacement. | |
60 | ;; T -- Memory reference with index register and long displacement. | |
0dfa6c5e UW |
61 | ;; A -- Multiple letter constraint followed by Q, R, S, or T: |
62 | ;; Offsettable memory reference of type specified by second letter. | |
e221ef54 UW |
63 | ;; B -- Multiple letter constraint followed by Q, R, S, or T: |
64 | ;; Memory reference of the type specified by second letter that | |
65 | ;; does *not* refer to a literal pool entry. | |
f19a9af7 AK |
66 | ;; U -- Pointer with short displacement. |
67 | ;; W -- Pointer with long displacement. | |
68 | ;; Y -- Shift count operand. | |
9db1d521 HP |
69 | ;; |
70 | ;; Special formats used for outputting 390 instructions. | |
71 | ;; | |
f19a9af7 AK |
72 | ;; %C: print opcode suffix for branch condition. |
73 | ;; %D: print opcode suffix for inverse branch condition. | |
74 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 75 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
76 | ;; %O: print only the displacement of a memory reference. |
77 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 78 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
79 | ;; %N: print the second word of a DImode operand. |
80 | ;; %M: print the second word of a TImode operand. | |
da48f5ec AK |
81 | ;; %Y: print shift count operand. |
82 | ;; | |
f19a9af7 | 83 | ;; %b: print integer X as if it's an unsigned byte. |
da48f5ec AK |
84 | ;; %x: print integer X as if it's an unsigned halfword. |
85 | ;; %h: print integer X as if it's a signed halfword. | |
86 | ;; %i: print the first nonzero HImode part of X. | |
87 | ;; %j: print the first HImode part unequal to -1 of X. | |
88 | ;; %k: print the first nonzero SImode part of X. | |
89 | ;; %m: print the first SImode part unequal to -1 of X. | |
90 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
91 | ;; |
92 | ;; We have a special constraint for pattern matching. | |
93 | ;; | |
94 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
95 | ;; | |
9db1d521 | 96 | |
fd3cd001 UW |
97 | ;; |
98 | ;; UNSPEC usage | |
99 | ;; | |
100 | ||
101 | (define_constants | |
10bbf137 UW |
102 | [; Miscellaneous |
103 | (UNSPEC_ROUND 1) | |
5b022de5 | 104 | (UNSPEC_CMPINT 2) |
6fa05db6 | 105 | (UNSPEC_ICM 10) |
10bbf137 UW |
106 | |
107 | ; GOT/PLT and lt-relative accesses | |
fd7643fb UW |
108 | (UNSPEC_LTREL_OFFSET 100) |
109 | (UNSPEC_LTREL_BASE 101) | |
110 | (UNSPEC_GOTENT 110) | |
111 | (UNSPEC_GOT 111) | |
112 | (UNSPEC_GOTOFF 112) | |
113 | (UNSPEC_PLT 113) | |
114 | (UNSPEC_PLTOFF 114) | |
115 | ||
116 | ; Literal pool | |
117 | (UNSPEC_RELOAD_BASE 210) | |
5af2f3d3 | 118 | (UNSPEC_MAIN_BASE 211) |
585539a1 | 119 | (UNSPEC_LTREF 212) |
9bb86f41 UW |
120 | (UNSPEC_INSN 213) |
121 | (UNSPEC_EXECUTE 214) | |
fd7643fb UW |
122 | |
123 | ; TLS relocation specifiers | |
fd3cd001 UW |
124 | (UNSPEC_TLSGD 500) |
125 | (UNSPEC_TLSLDM 501) | |
126 | (UNSPEC_NTPOFF 502) | |
127 | (UNSPEC_DTPOFF 503) | |
128 | (UNSPEC_GOTNTPOFF 504) | |
129 | (UNSPEC_INDNTPOFF 505) | |
130 | ||
131 | ; TLS support | |
fd3cd001 UW |
132 | (UNSPEC_TLSLDM_NTPOFF 511) |
133 | (UNSPEC_TLS_LOAD 512) | |
91d39d71 UW |
134 | |
135 | ; String Functions | |
7b8acc34 | 136 | (UNSPEC_SRST 600) |
742090fc | 137 | (UNSPEC_MVST 601) |
7b8acc34 AK |
138 | |
139 | ; Stack Smashing Protector | |
140 | (UNSPEC_SP_SET 700) | |
141 | (UNSPEC_SP_TEST 701) | |
fd3cd001 UW |
142 | ]) |
143 | ||
144 | ;; | |
145 | ;; UNSPEC_VOLATILE usage | |
146 | ;; | |
147 | ||
148 | (define_constants | |
10bbf137 UW |
149 | [; Blockage |
150 | (UNSPECV_BLOCKAGE 0) | |
151 | ||
2f7e5a0d EC |
152 | ; TPF Support |
153 | (UNSPECV_TPF_PROLOGUE 20) | |
154 | (UNSPECV_TPF_EPILOGUE 21) | |
155 | ||
10bbf137 | 156 | ; Literal pool |
fd7643fb | 157 | (UNSPECV_POOL 200) |
9bb86f41 UW |
158 | (UNSPECV_POOL_SECTION 201) |
159 | (UNSPECV_POOL_ALIGN 202) | |
416cf582 | 160 | (UNSPECV_POOL_ENTRY 203) |
fd7643fb UW |
161 | (UNSPECV_MAIN_POOL 300) |
162 | ||
163 | ; TLS support | |
fd3cd001 | 164 | (UNSPECV_SET_TP 500) |
e0374221 AS |
165 | |
166 | ; Atomic Support | |
167 | (UNSPECV_MB 700) | |
168 | (UNSPECV_CAS 701) | |
fd3cd001 UW |
169 | ]) |
170 | ||
ae156f85 AS |
171 | ;; |
172 | ;; Registers | |
173 | ;; | |
174 | ||
175 | (define_constants | |
176 | [ | |
177 | ; Sibling call register. | |
178 | (SIBCALL_REGNUM 1) | |
179 | ; Literal pool base register. | |
180 | (BASE_REGNUM 13) | |
181 | ; Return address register. | |
182 | (RETURN_REGNUM 14) | |
183 | ; Condition code register. | |
184 | (CC_REGNUM 33) | |
185 | ; Thread local storage pointer register. | |
186 | (TP_REGNUM 36) | |
187 | ]) | |
188 | ||
fd3cd001 | 189 | |
29a74354 UW |
190 | ;; Instruction operand type as used in the Principles of Operation. |
191 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 192 | |
29a74354 UW |
193 | (define_attr "op_type" |
194 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY" | |
b628bd8e | 195 | (const_string "NN")) |
9db1d521 | 196 | |
29a74354 | 197 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 198 | |
077dab3b | 199 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 200 | cs,vs,store,sem,idiv, |
ed0e512a | 201 | imulhi,imulsi,imuldi, |
cfdb984b AS |
202 | branch,jsr,fsimpdf,fsimpsf, |
203 | floaddf,floadsf,fstoredf,fstoresf, | |
204 | fmuldf,fmulsf,fdivdf,fdivsf, | |
205 | ftoi,itof,fsqrtdf,fsqrtsf, | |
a036c6f7 | 206 | other" |
29a74354 UW |
207 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
208 | (eq_attr "op_type" "SS") (const_string "cs")] | |
209 | (const_string "integer"))) | |
9db1d521 | 210 | |
29a74354 UW |
211 | ;; Another attribute used for scheduling purposes: |
212 | ;; agen: Instruction uses the address generation unit | |
213 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
214 | |
215 | (define_attr "atype" "agen,reg" | |
0101708c AS |
216 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE") |
217 | (const_string "reg") | |
218 | (const_string "agen"))) | |
9db1d521 | 219 | |
9db1d521 HP |
220 | ;; Length in bytes. |
221 | ||
222 | (define_attr "length" "" | |
0101708c AS |
223 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
224 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI") (const_int 4)] | |
b628bd8e | 225 | (const_int 6))) |
9db1d521 | 226 | |
29a74354 UW |
227 | |
228 | ;; Processor type. This attribute must exactly match the processor_type | |
229 | ;; enumeration in s390.h. The current machine description does not | |
230 | ;; distinguish between g5 and g6, but there are differences between the two | |
231 | ;; CPUs could in theory be modeled. | |
232 | ||
ec24698e | 233 | (define_attr "cpu" "g5,g6,z900,z990,z9_109" |
29a74354 UW |
234 | (const (symbol_ref "s390_tune"))) |
235 | ||
236 | ;; Pipeline description for z900. For lack of anything better, | |
237 | ;; this description is also used for the g5 and g6. | |
238 | (include "2064.md") | |
239 | ||
240 | ;; Pipeline description for z990. | |
241 | (include "2084.md") | |
242 | ||
0bfc3f69 AS |
243 | ;; Predicates |
244 | (include "predicates.md") | |
245 | ||
a8ba31f2 EC |
246 | ;; Other includes |
247 | (include "tpf.md") | |
f52c81dd AS |
248 | |
249 | ;; Macros | |
250 | ||
f5905b37 AS |
251 | ;; This mode macro allows DF and SF patterns to be generated from the |
252 | ;; same template. | |
253 | (define_mode_macro FPR [DF SF]) | |
254 | ||
8006eaa6 AS |
255 | ;; These mode macros allow 31-bit and 64-bit TDSI patterns to be generated |
256 | ;; from the same template. | |
257 | (define_mode_macro TDSI [(TI "TARGET_64BIT") DI SI]) | |
258 | ||
9a91a21f | 259 | ;; These mode macros allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d AS |
260 | ;; from the same template. |
261 | (define_mode_macro GPR [(DI "TARGET_64BIT") SI]) | |
9a91a21f | 262 | (define_mode_macro DSI [DI SI]) |
9db2f16d AS |
263 | |
264 | ;; This mode macro allows :P to be used for patterns that operate on | |
265 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. | |
8006eaa6 | 266 | (define_mode_macro DP [(TI "TARGET_64BIT") (DI "!TARGET_64BIT")]) |
9db2f16d AS |
267 | (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
268 | ||
f52c81dd AS |
269 | ;; This mode macro allows the QI and HI patterns to be defined from |
270 | ;; the same template. | |
271 | (define_mode_macro HQI [HI QI]) | |
272 | ||
342cf42b AS |
273 | ;; This mode macro allows the integer patterns to be defined from the |
274 | ;; same template. | |
275 | (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI]) | |
276 | ||
fa77b251 AS |
277 | ;; This macro allows to unify all 'bCOND' expander patterns. |
278 | (define_code_macro COMPARE [eq ne gt gtu lt ltu ge geu le leu unordered | |
279 | ordered uneq unlt ungt unle unge ltgt]) | |
280 | ||
9a91a21f AS |
281 | ;; This macro allows to unify all 'sCOND' patterns. |
282 | (define_code_macro SCOND [ltu gtu leu geu]) | |
283 | ||
f337b930 AS |
284 | ;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from |
285 | ;; the same template. | |
286 | (define_code_macro SHIFT [ashift lshiftrt]) | |
287 | ||
45d18331 AS |
288 | ;; These macros allow to combine most atomic operations. |
289 | (define_code_macro ATOMIC [and ior xor plus minus mult]) | |
290 | (define_code_attr atomic [(and "and") (ior "ior") (xor "xor") | |
291 | (plus "add") (minus "sub") (mult "nand")]) | |
292 | ||
f337b930 | 293 | |
f5905b37 AS |
294 | ;; In FPR templates, a string like "lt<de>br" will expand to "ltdbr" in DFmode |
295 | ;; and "ltebr" in SFmode. | |
296 | (define_mode_attr de [(DF "d") (SF "e")]) | |
297 | ||
298 | ;; In FPR templates, a string like "m<dee>br" will expand to "mdbr" in DFmode | |
299 | ;; and "meebr" in SFmode. This is needed for the 'mul<mode>3' pattern. | |
300 | (define_mode_attr dee [(DF "d") (SF "ee")]) | |
301 | ||
1b48c8cc AS |
302 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
303 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
304 | ;; version only operates on one register. | |
305 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
306 | ||
307 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
308 | ;; version only operates on one register. The DImode version needs an additional | |
309 | ;; register for the assembler output. | |
310 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
311 | ||
f337b930 AS |
312 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in |
313 | ;; 'ashift' and "srdl" in 'lshiftrt'. | |
314 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
315 | ||
316 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
317 | ;; pattern itself and the corresponding function calls. | |
318 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) | |
9a91a21f AS |
319 | |
320 | ;; This attribute handles differences in the instruction 'type' and will result | |
321 | ;; in "RRE" for DImode and "RR" for SImode. | |
322 | (define_mode_attr E [(DI "E") (SI "")]) | |
323 | ||
8006eaa6 AS |
324 | ;; This attribute handles differences in the instruction 'type' and will result |
325 | ;; in "RSE" for TImode and "RS" for DImode. | |
326 | (define_mode_attr TE [(TI "E") (DI "")]) | |
327 | ||
9a91a21f AS |
328 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
329 | ;; and "lcr" in SImode. | |
330 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 331 | |
8006eaa6 AS |
332 | ;; In DP templates, a string like "cds<g>" will expand to "cdsg" in TImode |
333 | ;; and "cds" in DImode. | |
334 | (define_mode_attr tg [(TI "g") (DI "")]) | |
335 | ||
2f8f8434 AS |
336 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
337 | ;; and "cfdbr" in SImode. | |
338 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
339 | ||
f52c81dd AS |
340 | ;; ICM mask required to load MODE value into the lowest subreg |
341 | ;; of a SImode register. | |
342 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
343 | ||
f6ee577c AS |
344 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
345 | ;; HImode and "llgc" in QImode. | |
346 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
347 | ||
a1aed706 AS |
348 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
349 | ;; in SImode. | |
350 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
351 | ||
f52c81dd AS |
352 | ;; Maximum unsigned integer that fits in MODE. |
353 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
354 | ||
355 | ||
9db1d521 HP |
356 | ;; |
357 | ;;- Compare instructions. | |
358 | ;; | |
359 | ||
9db2f16d | 360 | (define_expand "cmp<mode>" |
ae156f85 | 361 | [(set (reg:CC CC_REGNUM) |
9db2f16d AS |
362 | (compare:CC (match_operand:GPR 0 "register_operand" "") |
363 | (match_operand:GPR 1 "general_operand" "")))] | |
9db1d521 | 364 | "" |
9db1d521 HP |
365 | { |
366 | s390_compare_op0 = operands[0]; | |
367 | s390_compare_op1 = operands[1]; | |
368 | DONE; | |
10bbf137 | 369 | }) |
9db1d521 | 370 | |
f5905b37 | 371 | (define_expand "cmp<mode>" |
ae156f85 | 372 | [(set (reg:CC CC_REGNUM) |
f5905b37 AS |
373 | (compare:CC (match_operand:FPR 0 "register_operand" "") |
374 | (match_operand:FPR 1 "general_operand" "")))] | |
9db1d521 | 375 | "TARGET_HARD_FLOAT" |
9db1d521 HP |
376 | { |
377 | s390_compare_op0 = operands[0]; | |
378 | s390_compare_op1 = operands[1]; | |
379 | DONE; | |
10bbf137 | 380 | }) |
9db1d521 HP |
381 | |
382 | ||
07893d4f | 383 | ; Test-under-Mask instructions |
9db1d521 | 384 | |
07893d4f | 385 | (define_insn "*tmqi_mem" |
ae156f85 | 386 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
387 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
388 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
389 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 390 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 391 | "@ |
fc0ea003 UW |
392 | tm\t%S0,%b1 |
393 | tmy\t%S0,%b1" | |
d3632d41 | 394 | [(set_attr "op_type" "SI,SIY")]) |
9db1d521 | 395 | |
05b9aaaa | 396 | (define_insn "*tmdi_reg" |
ae156f85 | 397 | [(set (reg CC_REGNUM) |
f19a9af7 | 398 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 399 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
400 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
401 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
05b9aaaa | 402 | "TARGET_64BIT |
3ed99cc9 | 403 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
404 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
405 | "@ | |
406 | tmhh\t%0,%i1 | |
407 | tmhl\t%0,%i1 | |
408 | tmlh\t%0,%i1 | |
409 | tmll\t%0,%i1" | |
05b9aaaa UW |
410 | [(set_attr "op_type" "RI")]) |
411 | ||
412 | (define_insn "*tmsi_reg" | |
ae156f85 | 413 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
414 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
415 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
416 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 417 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
418 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
419 | "@ | |
420 | tmh\t%0,%i1 | |
421 | tml\t%0,%i1" | |
05b9aaaa UW |
422 | [(set_attr "op_type" "RI")]) |
423 | ||
f52c81dd | 424 | (define_insn "*tm<mode>_full" |
ae156f85 | 425 | [(set (reg CC_REGNUM) |
f52c81dd AS |
426 | (compare (match_operand:HQI 0 "register_operand" "d") |
427 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 428 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 429 | "tml\t%0,<max_uint>" |
07893d4f | 430 | [(set_attr "op_type" "RI")]) |
9db1d521 | 431 | |
07893d4f UW |
432 | |
433 | ; Load-and-Test instructions | |
434 | ||
435 | (define_insn "*tstdi_sign" | |
ae156f85 | 436 | [(set (reg CC_REGNUM) |
07893d4f UW |
437 | (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0) |
438 | (const_int 32)) (const_int 32)) | |
439 | (match_operand:DI 1 "const0_operand" ""))) | |
440 | (set (match_operand:DI 2 "register_operand" "=d") | |
441 | (sign_extend:DI (match_dup 0)))] | |
442 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 443 | "ltgfr\t%2,%0" |
07893d4f UW |
444 | [(set_attr "op_type" "RRE")]) |
445 | ||
ec24698e UW |
446 | (define_insn "*tstdi_extimm" |
447 | [(set (reg CC_REGNUM) | |
448 | (compare (match_operand:DI 0 "nonimmediate_operand" "d,m") | |
449 | (match_operand:DI 1 "const0_operand" ""))) | |
450 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
451 | (match_dup 0))] | |
452 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && TARGET_EXTIMM" | |
453 | "@ | |
454 | ltgr\t%2,%0 | |
455 | ltg\t%2,%0" | |
456 | [(set_attr "op_type" "RRE,RXY")]) | |
457 | ||
458 | (define_insn "*tstdi_cconly_extimm" | |
459 | [(set (reg CC_REGNUM) | |
460 | (compare (match_operand:DI 0 "nonimmediate_operand" "d,m") | |
461 | (match_operand:DI 1 "const0_operand" ""))) | |
462 | (clobber (match_scratch:DI 2 "=X,d"))] | |
463 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && TARGET_EXTIMM" | |
464 | "@ | |
465 | ltgr\t%0,%0 | |
466 | ltg\t%2,%0" | |
467 | [(set_attr "op_type" "RRE,RXY")]) | |
468 | ||
07893d4f | 469 | (define_insn "*tstdi" |
ae156f85 | 470 | [(set (reg CC_REGNUM) |
07893d4f UW |
471 | (compare (match_operand:DI 0 "register_operand" "d") |
472 | (match_operand:DI 1 "const0_operand" ""))) | |
473 | (set (match_operand:DI 2 "register_operand" "=d") | |
474 | (match_dup 0))] | |
ec24698e | 475 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT && !TARGET_EXTIMM" |
d40c829f | 476 | "ltgr\t%2,%0" |
07893d4f | 477 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 478 | |
07893d4f | 479 | (define_insn "*tstdi_cconly" |
ae156f85 | 480 | [(set (reg CC_REGNUM) |
07893d4f UW |
481 | (compare (match_operand:DI 0 "register_operand" "d") |
482 | (match_operand:DI 1 "const0_operand" "")))] | |
483 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
d40c829f | 484 | "ltgr\t%0,%0" |
07893d4f | 485 | [(set_attr "op_type" "RRE")]) |
9db1d521 | 486 | |
07893d4f | 487 | (define_insn "*tstdi_cconly_31" |
ae156f85 | 488 | [(set (reg CC_REGNUM) |
07893d4f UW |
489 | (compare (match_operand:DI 0 "register_operand" "d") |
490 | (match_operand:DI 1 "const0_operand" "")))] | |
491 | "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT" | |
d40c829f | 492 | "srda\t%0,0" |
077dab3b HP |
493 | [(set_attr "op_type" "RS") |
494 | (set_attr "atype" "reg")]) | |
495 | ||
ec24698e UW |
496 | (define_insn "*tstsi_extimm" |
497 | [(set (reg CC_REGNUM) | |
498 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,m") | |
499 | (match_operand:SI 1 "const0_operand" ""))) | |
500 | (set (match_operand:SI 2 "register_operand" "=d,d") | |
501 | (match_dup 0))] | |
502 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
503 | "@ | |
504 | ltr\t%2,%0 | |
505 | lt\t%2,%0" | |
506 | [(set_attr "op_type" "RR,RXY")]) | |
507 | ||
508 | (define_insn "*tstsi_cconly_extimm" | |
509 | [(set (reg CC_REGNUM) | |
510 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,m") | |
511 | (match_operand:SI 1 "const0_operand" ""))) | |
512 | (clobber (match_scratch:SI 2 "=X,d"))] | |
513 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
514 | "@ | |
515 | ltr\t%0,%0 | |
516 | lt\t%2,%0" | |
517 | [(set_attr "op_type" "RR,RXY")]) | |
4023fb28 | 518 | |
07893d4f | 519 | (define_insn "*tstsi" |
ae156f85 | 520 | [(set (reg CC_REGNUM) |
d3632d41 | 521 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 522 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 523 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 524 | (match_dup 0))] |
ec24698e | 525 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 526 | "@ |
d40c829f | 527 | ltr\t%2,%0 |
fc0ea003 UW |
528 | icm\t%2,15,%S0 |
529 | icmy\t%2,15,%S0" | |
d3632d41 | 530 | [(set_attr "op_type" "RR,RS,RSY")]) |
9db1d521 | 531 | |
07893d4f | 532 | (define_insn "*tstsi_cconly" |
ae156f85 | 533 | [(set (reg CC_REGNUM) |
d3632d41 | 534 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 535 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 536 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
537 | "s390_match_ccmode(insn, CCSmode)" |
538 | "@ | |
d40c829f | 539 | ltr\t%0,%0 |
fc0ea003 UW |
540 | icm\t%2,15,%S0 |
541 | icmy\t%2,15,%S0" | |
d3632d41 | 542 | [(set_attr "op_type" "RR,RS,RSY")]) |
4023fb28 | 543 | |
07893d4f | 544 | (define_insn "*tstsi_cconly2" |
ae156f85 | 545 | [(set (reg CC_REGNUM) |
07893d4f UW |
546 | (compare (match_operand:SI 0 "register_operand" "d") |
547 | (match_operand:SI 1 "const0_operand" "")))] | |
548 | "s390_match_ccmode(insn, CCSmode)" | |
d40c829f | 549 | "ltr\t%0,%0" |
07893d4f | 550 | [(set_attr "op_type" "RR")]) |
4023fb28 | 551 | |
f52c81dd | 552 | (define_insn "*tst<mode>CCT" |
ae156f85 | 553 | [(set (reg CC_REGNUM) |
f52c81dd AS |
554 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
555 | (match_operand:HQI 1 "const0_operand" ""))) | |
556 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
557 | (match_dup 0))] |
558 | "s390_match_ccmode(insn, CCTmode)" | |
559 | "@ | |
f52c81dd AS |
560 | icm\t%2,<icm_lo>,%S0 |
561 | icmy\t%2,<icm_lo>,%S0 | |
562 | tml\t%0,<max_uint>" | |
d3632d41 | 563 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 UW |
564 | |
565 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 566 | [(set (reg CC_REGNUM) |
d3632d41 | 567 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 568 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 569 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
570 | "s390_match_ccmode(insn, CCTmode)" |
571 | "@ | |
fc0ea003 UW |
572 | icm\t%2,3,%S0 |
573 | icmy\t%2,3,%S0 | |
d40c829f | 574 | tml\t%0,65535" |
d3632d41 | 575 | [(set_attr "op_type" "RS,RSY,RI")]) |
3af97654 | 576 | |
3af97654 | 577 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 578 | [(set (reg CC_REGNUM) |
d3632d41 | 579 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
580 | (match_operand:QI 1 "const0_operand" "")))] |
581 | "s390_match_ccmode(insn, CCTmode)" | |
582 | "@ | |
fc0ea003 UW |
583 | cli\t%S0,0 |
584 | cliy\t%S0,0 | |
d40c829f | 585 | tml\t%0,255" |
d3632d41 | 586 | [(set_attr "op_type" "SI,SIY,RI")]) |
3af97654 | 587 | |
f52c81dd | 588 | (define_insn "*tst<mode>" |
ae156f85 | 589 | [(set (reg CC_REGNUM) |
f52c81dd AS |
590 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
591 | (match_operand:HQI 1 "const0_operand" ""))) | |
592 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
593 | (match_dup 0))] |
594 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 595 | "@ |
f52c81dd AS |
596 | icm\t%2,<icm_lo>,%S0 |
597 | icmy\t%2,<icm_lo>,%S0" | |
d3632d41 | 598 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 | 599 | |
f52c81dd | 600 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 601 | [(set (reg CC_REGNUM) |
f52c81dd AS |
602 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
603 | (match_operand:HQI 1 "const0_operand" ""))) | |
604 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 605 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 606 | "@ |
f52c81dd AS |
607 | icm\t%2,<icm_lo>,%S0 |
608 | icmy\t%2,<icm_lo>,%S0" | |
d3632d41 UW |
609 | [(set_attr "op_type" "RS,RSY")]) |
610 | ||
9db1d521 | 611 | |
575f7c2b UW |
612 | ; Compare (equality) instructions |
613 | ||
614 | (define_insn "*cmpdi_cct" | |
ae156f85 | 615 | [(set (reg CC_REGNUM) |
ec24698e UW |
616 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
617 | (match_operand:DI 1 "general_operand" "d,K,Os,m,BQ")))] | |
e221ef54 | 618 | "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT" |
575f7c2b UW |
619 | "@ |
620 | cgr\t%0,%1 | |
f4f41b4e | 621 | cghi\t%0,%h1 |
ec24698e | 622 | cgfi\t%0,%1 |
575f7c2b | 623 | cg\t%0,%1 |
19b63d8e | 624 | #" |
ec24698e | 625 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS")]) |
575f7c2b UW |
626 | |
627 | (define_insn "*cmpsi_cct" | |
ae156f85 | 628 | [(set (reg CC_REGNUM) |
ec24698e UW |
629 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
630 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 631 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
632 | "@ |
633 | cr\t%0,%1 | |
f4f41b4e | 634 | chi\t%0,%h1 |
ec24698e | 635 | cfi\t%0,%1 |
575f7c2b UW |
636 | c\t%0,%1 |
637 | cy\t%0,%1 | |
19b63d8e | 638 | #" |
ec24698e | 639 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS")]) |
575f7c2b UW |
640 | |
641 | ||
07893d4f | 642 | ; Compare (signed) instructions |
4023fb28 | 643 | |
07893d4f | 644 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 645 | [(set (reg CC_REGNUM) |
07893d4f UW |
646 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
647 | (match_operand:DI 0 "register_operand" "d,d")))] | |
648 | "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT" | |
4023fb28 | 649 | "@ |
d40c829f UW |
650 | cgfr\t%0,%1 |
651 | cgf\t%0,%1" | |
d3632d41 | 652 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 653 | |
07893d4f | 654 | (define_insn "*cmpdi_ccs" |
ae156f85 | 655 | [(set (reg CC_REGNUM) |
ec24698e UW |
656 | (compare (match_operand:DI 0 "register_operand" "d,d,d,d") |
657 | (match_operand:DI 1 "general_operand" "d,K,Os,m")))] | |
07893d4f UW |
658 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" |
659 | "@ | |
d40c829f | 660 | cgr\t%0,%1 |
f4f41b4e | 661 | cghi\t%0,%h1 |
ec24698e | 662 | cgfi\t%0,%1 |
d40c829f | 663 | cg\t%0,%1" |
ec24698e | 664 | [(set_attr "op_type" "RRE,RI,RIL,RXY")]) |
c7453384 | 665 | |
07893d4f | 666 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 667 | [(set (reg CC_REGNUM) |
d3632d41 UW |
668 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")) |
669 | (match_operand:SI 0 "register_operand" "d,d")))] | |
07893d4f | 670 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 671 | "@ |
d40c829f UW |
672 | ch\t%0,%1 |
673 | chy\t%0,%1" | |
d3632d41 | 674 | [(set_attr "op_type" "RX,RXY")]) |
4023fb28 | 675 | |
07893d4f | 676 | (define_insn "*cmpsi_ccs" |
ae156f85 | 677 | [(set (reg CC_REGNUM) |
ec24698e UW |
678 | (compare (match_operand:SI 0 "register_operand" "d,d,d,d,d") |
679 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T")))] | |
9db1d521 | 680 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 681 | "@ |
d40c829f | 682 | cr\t%0,%1 |
f4f41b4e | 683 | chi\t%0,%h1 |
ec24698e | 684 | cfi\t%0,%1 |
d40c829f UW |
685 | c\t%0,%1 |
686 | cy\t%0,%1" | |
ec24698e | 687 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY")]) |
c7453384 | 688 | |
07893d4f UW |
689 | |
690 | ; Compare (unsigned) instructions | |
9db1d521 | 691 | |
07893d4f | 692 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 693 | [(set (reg CC_REGNUM) |
07893d4f UW |
694 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")) |
695 | (match_operand:DI 0 "register_operand" "d,d")))] | |
575f7c2b | 696 | "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT" |
07893d4f | 697 | "@ |
d40c829f UW |
698 | clgfr\t%0,%1 |
699 | clgf\t%0,%1" | |
d3632d41 | 700 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 701 | |
07893d4f | 702 | (define_insn "*cmpdi_ccu" |
ae156f85 | 703 | [(set (reg CC_REGNUM) |
ec24698e UW |
704 | (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,d,Q,BQ") |
705 | (match_operand:DI 1 "general_operand" "d,Op,m,BQ,Q")))] | |
e221ef54 | 706 | "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT" |
07893d4f | 707 | "@ |
d40c829f | 708 | clgr\t%0,%1 |
ec24698e | 709 | clgfi\t%0,%1 |
575f7c2b | 710 | clg\t%0,%1 |
e221ef54 | 711 | # |
19b63d8e | 712 | #" |
ec24698e | 713 | [(set_attr "op_type" "RRE,RIL,RXY,SS,SS")]) |
9db1d521 | 714 | |
07893d4f | 715 | (define_insn "*cmpsi_ccu" |
ae156f85 | 716 | [(set (reg CC_REGNUM) |
ec24698e UW |
717 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,d,Q,BQ") |
718 | (match_operand:SI 1 "general_operand" "d,Os,R,T,BQ,Q")))] | |
e221ef54 | 719 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 720 | "@ |
d40c829f | 721 | clr\t%0,%1 |
ec24698e | 722 | clfi\t%0,%o1 |
d40c829f | 723 | cl\t%0,%1 |
575f7c2b | 724 | cly\t%0,%1 |
e221ef54 | 725 | # |
19b63d8e | 726 | #" |
ec24698e | 727 | [(set_attr "op_type" "RR,RIL,RX,RXY,SS,SS")]) |
9db1d521 | 728 | |
07893d4f | 729 | (define_insn "*cmphi_ccu" |
ae156f85 | 730 | [(set (reg CC_REGNUM) |
e221ef54 UW |
731 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ") |
732 | (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))] | |
575f7c2b | 733 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 734 | && !register_operand (operands[1], HImode)" |
d3632d41 | 735 | "@ |
fc0ea003 UW |
736 | clm\t%0,3,%S1 |
737 | clmy\t%0,3,%S1 | |
e221ef54 | 738 | # |
19b63d8e | 739 | #" |
e221ef54 | 740 | [(set_attr "op_type" "RS,RSY,SS,SS")]) |
9db1d521 HP |
741 | |
742 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 743 | [(set (reg CC_REGNUM) |
e221ef54 UW |
744 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
745 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 746 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 747 | && !register_operand (operands[1], QImode)" |
d3632d41 | 748 | "@ |
fc0ea003 UW |
749 | clm\t%0,1,%S1 |
750 | clmy\t%0,1,%S1 | |
751 | cli\t%S0,%b1 | |
752 | cliy\t%S0,%b1 | |
e221ef54 | 753 | # |
19b63d8e | 754 | #" |
e221ef54 | 755 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")]) |
9db1d521 HP |
756 | |
757 | ||
19b63d8e UW |
758 | ; Block compare (CLC) instruction patterns. |
759 | ||
760 | (define_insn "*clc" | |
ae156f85 | 761 | [(set (reg CC_REGNUM) |
d4f52f0e | 762 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
763 | (match_operand:BLK 1 "memory_operand" "Q"))) |
764 | (use (match_operand 2 "const_int_operand" "n"))] | |
765 | "s390_match_ccmode (insn, CCUmode) | |
766 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 767 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 768 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
769 | |
770 | (define_split | |
ae156f85 | 771 | [(set (reg CC_REGNUM) |
19b63d8e UW |
772 | (compare (match_operand 0 "memory_operand" "") |
773 | (match_operand 1 "memory_operand" "")))] | |
774 | "reload_completed | |
775 | && s390_match_ccmode (insn, CCUmode) | |
776 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
777 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
778 | [(parallel | |
779 | [(set (match_dup 0) (match_dup 1)) | |
780 | (use (match_dup 2))])] | |
781 | { | |
782 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
783 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
784 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
785 | ||
786 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
787 | operands[0], operands[1]); | |
788 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
789 | }) | |
790 | ||
791 | ||
f5905b37 | 792 | ; (DF|SF) instructions |
9db1d521 | 793 | |
f5905b37 | 794 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 795 | [(set (reg CC_REGNUM) |
f5905b37 AS |
796 | (compare (match_operand:FPR 0 "register_operand" "f") |
797 | (match_operand:FPR 1 "const0_operand" "")))] | |
9db1d521 | 798 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 799 | "lt<de>br\t%0,%0" |
077dab3b | 800 | [(set_attr "op_type" "RRE") |
f5905b37 | 801 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 802 | |
f5905b37 | 803 | (define_insn "*cmp<mode>_ccs_0_ibm" |
ae156f85 | 804 | [(set (reg CC_REGNUM) |
f5905b37 AS |
805 | (compare (match_operand:FPR 0 "register_operand" "f") |
806 | (match_operand:FPR 1 "const0_operand" "")))] | |
9db1d521 | 807 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
f5905b37 | 808 | "lt<de>r\t%0,%0" |
077dab3b | 809 | [(set_attr "op_type" "RR") |
f5905b37 | 810 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 811 | |
f5905b37 | 812 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 813 | [(set (reg CC_REGNUM) |
f5905b37 AS |
814 | (compare (match_operand:FPR 0 "register_operand" "f,f") |
815 | (match_operand:FPR 1 "general_operand" "f,R")))] | |
9db1d521 HP |
816 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
817 | "@ | |
f5905b37 AS |
818 | c<de>br\t%0,%1 |
819 | c<de>b\t%0,%1" | |
077dab3b | 820 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 821 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 822 | |
f5905b37 | 823 | (define_insn "*cmp<mode>_ccs_ibm" |
ae156f85 | 824 | [(set (reg CC_REGNUM) |
f5905b37 AS |
825 | (compare (match_operand:FPR 0 "register_operand" "f,f") |
826 | (match_operand:FPR 1 "general_operand" "f,R")))] | |
9db1d521 HP |
827 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
828 | "@ | |
f5905b37 AS |
829 | c<de>r\t%0,%1 |
830 | c<de>\t%0,%1" | |
077dab3b | 831 | [(set_attr "op_type" "RR,RX") |
f5905b37 | 832 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 HP |
833 | |
834 | ||
835 | ;; | |
836 | ;;- Move instructions. | |
837 | ;; | |
838 | ||
839 | ; | |
840 | ; movti instruction pattern(s). | |
841 | ; | |
842 | ||
843 | (define_insn "movti" | |
d3632d41 | 844 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q") |
11598938 | 845 | (match_operand:TI 1 "general_operand" "QS,d,dPm,d,Q"))] |
9db1d521 | 846 | "TARGET_64BIT" |
4023fb28 | 847 | "@ |
fc0ea003 UW |
848 | lmg\t%0,%N0,%S1 |
849 | stmg\t%1,%N1,%S0 | |
4023fb28 | 850 | # |
9b7c75b9 | 851 | # |
19b63d8e | 852 | #" |
b628bd8e UW |
853 | [(set_attr "op_type" "RSY,RSY,*,*,SS") |
854 | (set_attr "type" "lm,stm,*,*,*")]) | |
4023fb28 UW |
855 | |
856 | (define_split | |
857 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
858 | (match_operand:TI 1 "general_operand" ""))] | |
859 | "TARGET_64BIT && reload_completed | |
dc65c307 | 860 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
861 | [(set (match_dup 2) (match_dup 4)) |
862 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 863 | { |
dc65c307 UW |
864 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
865 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
866 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
867 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
868 | }) | |
869 | ||
870 | (define_split | |
871 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
872 | (match_operand:TI 1 "general_operand" ""))] | |
873 | "TARGET_64BIT && reload_completed | |
874 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" | |
875 | [(set (match_dup 2) (match_dup 4)) | |
876 | (set (match_dup 3) (match_dup 5))] | |
877 | { | |
878 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
879 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
880 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
881 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
882 | }) | |
4023fb28 UW |
883 | |
884 | (define_split | |
885 | [(set (match_operand:TI 0 "register_operand" "") | |
886 | (match_operand:TI 1 "memory_operand" ""))] | |
887 | "TARGET_64BIT && reload_completed | |
888 | && !s_operand (operands[1], VOIDmode)" | |
a41c6c53 | 889 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
890 | { |
891 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
892 | s390_load_address (addr, XEXP (operands[1], 0)); | |
893 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
894 | }) |
895 | ||
896 | (define_expand "reload_outti" | |
9c3c3dcc | 897 | [(parallel [(match_operand:TI 0 "" "") |
dc65c307 UW |
898 | (match_operand:TI 1 "register_operand" "d") |
899 | (match_operand:DI 2 "register_operand" "=&a")])] | |
900 | "TARGET_64BIT" | |
901 | { | |
9c3c3dcc | 902 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 903 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
904 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
905 | emit_move_insn (operands[0], operands[1]); | |
906 | DONE; | |
907 | }) | |
9db1d521 HP |
908 | |
909 | ; | |
910 | ; movdi instruction pattern(s). | |
911 | ; | |
912 | ||
9db1d521 HP |
913 | (define_expand "movdi" |
914 | [(set (match_operand:DI 0 "general_operand" "") | |
915 | (match_operand:DI 1 "general_operand" ""))] | |
916 | "" | |
9db1d521 | 917 | { |
fd3cd001 UW |
918 | /* Handle symbolic constants. */ |
919 | if (TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
920 | emit_symbolic_move (operands); | |
10bbf137 | 921 | }) |
9db1d521 | 922 | |
4023fb28 UW |
923 | (define_insn "*movdi_larl" |
924 | [(set (match_operand:DI 0 "register_operand" "=d") | |
925 | (match_operand:DI 1 "larl_operand" "X"))] | |
926 | "TARGET_64BIT | |
8e509cf9 | 927 | && !FP_REG_P (operands[0])" |
d40c829f | 928 | "larl\t%0,%1" |
4023fb28 | 929 | [(set_attr "op_type" "RIL") |
077dab3b | 930 | (set_attr "type" "larl")]) |
4023fb28 | 931 | |
ec24698e UW |
932 | (define_insn "*movdi_64extimm" |
933 | [(set (match_operand:DI 0 "nonimmediate_operand" | |
934 | "=d,d,d,d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") | |
935 | (match_operand:DI 1 "general_operand" | |
936 | "K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))] | |
937 | "TARGET_64BIT && TARGET_EXTIMM" | |
938 | "@ | |
939 | lghi\t%0,%h1 | |
940 | llihh\t%0,%i1 | |
941 | llihl\t%0,%i1 | |
942 | llilh\t%0,%i1 | |
943 | llill\t%0,%i1 | |
944 | lgfi\t%0,%1 | |
945 | llihf\t%0,%k1 | |
946 | llilf\t%0,%k1 | |
947 | lay\t%0,%a1 | |
948 | lgr\t%0,%1 | |
949 | lg\t%0,%1 | |
950 | stg\t%1,%0 | |
951 | ldr\t%0,%1 | |
952 | ld\t%0,%1 | |
953 | ldy\t%0,%1 | |
954 | std\t%1,%0 | |
955 | stdy\t%1,%0 | |
956 | # | |
957 | # | |
958 | stam\t%1,%N1,%S0 | |
959 | lam\t%0,%N0,%S1 | |
960 | #" | |
961 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RXY,RRE,RXY,RXY, | |
962 | RR,RX,RXY,RX,RXY,*,*,RS,RS,SS") | |
963 | (set_attr "type" "*,*,*,*,*,*,*,*,la,lr,load,store, | |
964 | floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")]) | |
965 | ||
9db1d521 | 966 | (define_insn "*movdi_64" |
2f7e5a0d | 967 | [(set (match_operand:DI 0 "nonimmediate_operand" |
c5aa1d12 | 968 | "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") |
2f7e5a0d | 969 | (match_operand:DI 1 "general_operand" |
c5aa1d12 | 970 | "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))] |
ec24698e | 971 | "TARGET_64BIT && !TARGET_EXTIMM" |
9db1d521 | 972 | "@ |
f19a9af7 AK |
973 | lghi\t%0,%h1 |
974 | llihh\t%0,%i1 | |
975 | llihl\t%0,%i1 | |
976 | llilh\t%0,%i1 | |
977 | llill\t%0,%i1 | |
978 | lay\t%0,%a1 | |
d40c829f UW |
979 | lgr\t%0,%1 |
980 | lg\t%0,%1 | |
981 | stg\t%1,%0 | |
982 | ldr\t%0,%1 | |
983 | ld\t%0,%1 | |
984 | ldy\t%0,%1 | |
985 | std\t%1,%0 | |
986 | stdy\t%1,%0 | |
c5aa1d12 UW |
987 | # |
988 | # | |
989 | stam\t%1,%N1,%S0 | |
990 | lam\t%0,%N0,%S1 | |
19b63d8e | 991 | #" |
b628bd8e UW |
992 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY, |
993 | RR,RX,RXY,RX,RXY,*,*,RS,RS,SS") | |
994 | (set_attr "type" "*,*,*,*,*,la,lr,load,store, | |
cfdb984b | 995 | floaddf,floaddf,floaddf,fstoredf,fstoredf,*,*,*,*,*")]) |
c5aa1d12 UW |
996 | |
997 | (define_split | |
998 | [(set (match_operand:DI 0 "register_operand" "") | |
999 | (match_operand:DI 1 "register_operand" ""))] | |
1000 | "TARGET_64BIT && ACCESS_REG_P (operands[1])" | |
1001 | [(set (match_dup 2) (match_dup 3)) | |
1002 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1003 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1004 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1005 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1006 | ||
1007 | (define_split | |
1008 | [(set (match_operand:DI 0 "register_operand" "") | |
1009 | (match_operand:DI 1 "register_operand" ""))] | |
1010 | "TARGET_64BIT && ACCESS_REG_P (operands[0]) | |
1011 | && dead_or_set_p (insn, operands[1])" | |
1012 | [(set (match_dup 3) (match_dup 2)) | |
1013 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1014 | (set (match_dup 4) (match_dup 2))] | |
1015 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1016 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1017 | ||
1018 | (define_split | |
1019 | [(set (match_operand:DI 0 "register_operand" "") | |
1020 | (match_operand:DI 1 "register_operand" ""))] | |
1021 | "TARGET_64BIT && ACCESS_REG_P (operands[0]) | |
1022 | && !dead_or_set_p (insn, operands[1])" | |
1023 | [(set (match_dup 3) (match_dup 2)) | |
1024 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1025 | (set (match_dup 4) (match_dup 2)) | |
1026 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1027 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1028 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1029 | |
1030 | (define_insn "*movdi_31" | |
c4d50129 | 1031 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,Q,S,d,o,!*f,!*f,!*f,!R,!T,Q") |
11598938 | 1032 | (match_operand:DI 1 "general_operand" "Q,S,d,d,dPm,d,*f,R,T,*f,*f,Q"))] |
9db1d521 | 1033 | "!TARGET_64BIT" |
4023fb28 | 1034 | "@ |
fc0ea003 | 1035 | lm\t%0,%N0,%S1 |
c4d50129 | 1036 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1037 | stm\t%1,%N1,%S0 |
c4d50129 | 1038 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1039 | # |
1040 | # | |
d40c829f UW |
1041 | ldr\t%0,%1 |
1042 | ld\t%0,%1 | |
1043 | ldy\t%0,%1 | |
1044 | std\t%1,%0 | |
1045 | stdy\t%1,%0 | |
19b63d8e | 1046 | #" |
c4d50129 AK |
1047 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,SS") |
1048 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*")]) | |
4023fb28 UW |
1049 | |
1050 | (define_split | |
1051 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1052 | (match_operand:DI 1 "general_operand" ""))] | |
1053 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 1054 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1055 | [(set (match_dup 2) (match_dup 4)) |
1056 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1057 | { |
dc65c307 UW |
1058 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1059 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1060 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1061 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1062 | }) | |
1063 | ||
1064 | (define_split | |
1065 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1066 | (match_operand:DI 1 "general_operand" ""))] | |
1067 | "!TARGET_64BIT && reload_completed | |
1068 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" | |
1069 | [(set (match_dup 2) (match_dup 4)) | |
1070 | (set (match_dup 3) (match_dup 5))] | |
1071 | { | |
1072 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1073 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1074 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1075 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1076 | }) | |
9db1d521 | 1077 | |
4023fb28 UW |
1078 | (define_split |
1079 | [(set (match_operand:DI 0 "register_operand" "") | |
1080 | (match_operand:DI 1 "memory_operand" ""))] | |
1081 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 1082 | && !FP_REG_P (operands[0]) |
4023fb28 | 1083 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1084 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1085 | { |
1086 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1087 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1088 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1089 | }) |
1090 | ||
1091 | (define_expand "reload_outdi" | |
9c3c3dcc | 1092 | [(parallel [(match_operand:DI 0 "" "") |
dc65c307 UW |
1093 | (match_operand:DI 1 "register_operand" "d") |
1094 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1095 | "!TARGET_64BIT" | |
1096 | { | |
9c3c3dcc | 1097 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1098 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1099 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1100 | emit_move_insn (operands[0], operands[1]); | |
1101 | DONE; | |
1102 | }) | |
9db1d521 | 1103 | |
84817c5d UW |
1104 | (define_peephole2 |
1105 | [(set (match_operand:DI 0 "register_operand" "") | |
1106 | (mem:DI (match_operand 1 "address_operand" "")))] | |
1107 | "TARGET_64BIT | |
1108 | && !FP_REG_P (operands[0]) | |
1109 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1110 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1111 | && get_pool_mode (operands[1]) == DImode | |
1112 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1113 | [(set (match_dup 0) (match_dup 2))] | |
1114 | "operands[2] = get_pool_constant (operands[1]);") | |
1115 | ||
7bdff56f UW |
1116 | (define_insn "*la_64" |
1117 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
1118 | (match_operand:QI 1 "address_operand" "U,W"))] | |
1119 | "TARGET_64BIT" | |
1120 | "@ | |
1121 | la\t%0,%a1 | |
1122 | lay\t%0,%a1" | |
1123 | [(set_attr "op_type" "RX,RXY") | |
1124 | (set_attr "type" "la")]) | |
1125 | ||
1126 | (define_peephole2 | |
1127 | [(parallel | |
1128 | [(set (match_operand:DI 0 "register_operand" "") | |
1129 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1130 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1131 | "TARGET_64BIT |
e1d5ee28 | 1132 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1133 | [(set (match_dup 0) (match_dup 1))] |
1134 | "") | |
1135 | ||
1136 | (define_peephole2 | |
1137 | [(set (match_operand:DI 0 "register_operand" "") | |
1138 | (match_operand:DI 1 "register_operand" "")) | |
1139 | (parallel | |
1140 | [(set (match_dup 0) | |
1141 | (plus:DI (match_dup 0) | |
1142 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1143 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1144 | "TARGET_64BIT |
1145 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1146 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1147 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1148 | "") | |
1149 | ||
1150 | (define_expand "reload_indi" | |
1151 | [(parallel [(match_operand:DI 0 "register_operand" "=a") | |
1152 | (match_operand:DI 1 "s390_plus_operand" "") | |
1153 | (match_operand:DI 2 "register_operand" "=&a")])] | |
1154 | "TARGET_64BIT" | |
1155 | { | |
1156 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1157 | DONE; | |
1158 | }) | |
1159 | ||
9db1d521 HP |
1160 | ; |
1161 | ; movsi instruction pattern(s). | |
1162 | ; | |
1163 | ||
9db1d521 HP |
1164 | (define_expand "movsi" |
1165 | [(set (match_operand:SI 0 "general_operand" "") | |
1166 | (match_operand:SI 1 "general_operand" ""))] | |
1167 | "" | |
9db1d521 | 1168 | { |
fd3cd001 UW |
1169 | /* Handle symbolic constants. */ |
1170 | if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1])) | |
1171 | emit_symbolic_move (operands); | |
10bbf137 | 1172 | }) |
9db1d521 | 1173 | |
9e8327e3 UW |
1174 | (define_insn "*movsi_larl" |
1175 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1176 | (match_operand:SI 1 "larl_operand" "X"))] | |
1177 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1178 | && !FP_REG_P (operands[0])" | |
1179 | "larl\t%0,%1" | |
1180 | [(set_attr "op_type" "RIL") | |
1181 | (set_attr "type" "larl")]) | |
1182 | ||
f19a9af7 | 1183 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1184 | [(set (match_operand:SI 0 "nonimmediate_operand" |
ec24698e | 1185 | "=d,d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q") |
2f7e5a0d | 1186 | (match_operand:SI 1 "general_operand" |
ec24698e | 1187 | "K,N0HS0,N1HS0,Os,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))] |
f19a9af7 | 1188 | "TARGET_ZARCH" |
9db1d521 | 1189 | "@ |
f19a9af7 AK |
1190 | lhi\t%0,%h1 |
1191 | llilh\t%0,%i1 | |
1192 | llill\t%0,%i1 | |
ec24698e | 1193 | iilf\t%0,%o1 |
f19a9af7 | 1194 | lay\t%0,%a1 |
d40c829f UW |
1195 | lr\t%0,%1 |
1196 | l\t%0,%1 | |
1197 | ly\t%0,%1 | |
1198 | st\t%1,%0 | |
1199 | sty\t%1,%0 | |
1200 | ler\t%0,%1 | |
1201 | le\t%0,%1 | |
1202 | ley\t%0,%1 | |
1203 | ste\t%1,%0 | |
1204 | stey\t%1,%0 | |
c5aa1d12 UW |
1205 | ear\t%0,%1 |
1206 | sar\t%0,%1 | |
1207 | stam\t%1,%1,%S0 | |
1208 | lam\t%0,%0,%S1 | |
19b63d8e | 1209 | #" |
ec24698e | 1210 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RR,RX,RXY,RX,RXY, |
b628bd8e | 1211 | RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS") |
ec24698e | 1212 | (set_attr "type" "*,*,*,*,la,lr,load,load,store,store, |
cfdb984b | 1213 | floadsf,floadsf,floadsf,fstoresf,fstoresf,*,*,*,*,*")]) |
f19a9af7 AK |
1214 | |
1215 | (define_insn "*movsi_esa" | |
c5aa1d12 UW |
1216 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q") |
1217 | (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))] | |
f19a9af7 AK |
1218 | "!TARGET_ZARCH" |
1219 | "@ | |
1220 | lhi\t%0,%h1 | |
1221 | lr\t%0,%1 | |
1222 | l\t%0,%1 | |
1223 | st\t%1,%0 | |
1224 | ler\t%0,%1 | |
1225 | le\t%0,%1 | |
1226 | ste\t%1,%0 | |
c5aa1d12 UW |
1227 | ear\t%0,%1 |
1228 | sar\t%0,%1 | |
1229 | stam\t%1,%1,%S0 | |
1230 | lam\t%0,%0,%S1 | |
19b63d8e | 1231 | #" |
c5aa1d12 | 1232 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS") |
cfdb984b | 1233 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,fstoresf,*,*,*,*,*")]) |
9db1d521 | 1234 | |
84817c5d UW |
1235 | (define_peephole2 |
1236 | [(set (match_operand:SI 0 "register_operand" "") | |
1237 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1238 | "!FP_REG_P (operands[0]) | |
1239 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1240 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1241 | && get_pool_mode (operands[1]) == SImode | |
1242 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1243 | [(set (match_dup 0) (match_dup 2))] | |
1244 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 1245 | |
7bdff56f UW |
1246 | (define_insn "*la_31" |
1247 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1248 | (match_operand:QI 1 "address_operand" "U,W"))] | |
1249 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" | |
1250 | "@ | |
1251 | la\t%0,%a1 | |
1252 | lay\t%0,%a1" | |
1253 | [(set_attr "op_type" "RX,RXY") | |
1254 | (set_attr "type" "la")]) | |
1255 | ||
1256 | (define_peephole2 | |
1257 | [(parallel | |
1258 | [(set (match_operand:SI 0 "register_operand" "") | |
1259 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1260 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1261 | "!TARGET_64BIT |
e1d5ee28 | 1262 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1263 | [(set (match_dup 0) (match_dup 1))] |
1264 | "") | |
1265 | ||
1266 | (define_peephole2 | |
1267 | [(set (match_operand:SI 0 "register_operand" "") | |
1268 | (match_operand:SI 1 "register_operand" "")) | |
1269 | (parallel | |
1270 | [(set (match_dup 0) | |
1271 | (plus:SI (match_dup 0) | |
1272 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1273 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1274 | "!TARGET_64BIT |
1275 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1276 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1277 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
1278 | "") | |
1279 | ||
1280 | (define_insn "*la_31_and" | |
1281 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1282 | (and:SI (match_operand:QI 1 "address_operand" "U,W") | |
1283 | (const_int 2147483647)))] | |
1284 | "!TARGET_64BIT" | |
1285 | "@ | |
1286 | la\t%0,%a1 | |
1287 | lay\t%0,%a1" | |
1288 | [(set_attr "op_type" "RX,RXY") | |
1289 | (set_attr "type" "la")]) | |
1290 | ||
1291 | (define_insn_and_split "*la_31_and_cc" | |
1292 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1293 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
1294 | (const_int 2147483647))) | |
ae156f85 | 1295 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
1296 | "!TARGET_64BIT" |
1297 | "#" | |
1298 | "&& reload_completed" | |
1299 | [(set (match_dup 0) | |
1300 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
1301 | "" | |
1302 | [(set_attr "op_type" "RX") | |
1303 | (set_attr "type" "la")]) | |
1304 | ||
1305 | (define_insn "force_la_31" | |
1306 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
1307 | (match_operand:QI 1 "address_operand" "U,W")) | |
1308 | (use (const_int 0))] | |
1309 | "!TARGET_64BIT" | |
1310 | "@ | |
1311 | la\t%0,%a1 | |
1312 | lay\t%0,%a1" | |
1313 | [(set_attr "op_type" "RX") | |
1314 | (set_attr "type" "la")]) | |
1315 | ||
1316 | (define_expand "reload_insi" | |
1317 | [(parallel [(match_operand:SI 0 "register_operand" "=a") | |
1318 | (match_operand:SI 1 "s390_plus_operand" "") | |
1319 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1320 | "!TARGET_64BIT" | |
1321 | { | |
1322 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1323 | DONE; | |
1324 | }) | |
1325 | ||
9db1d521 HP |
1326 | ; |
1327 | ; movhi instruction pattern(s). | |
1328 | ; | |
1329 | ||
02ed3c5e UW |
1330 | (define_expand "movhi" |
1331 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
1332 | (match_operand:HI 1 "general_operand" ""))] | |
1333 | "" | |
1334 | { | |
2f7e5a0d | 1335 | /* Make it explicit that loading a register from memory |
02ed3c5e UW |
1336 | always sign-extends (at least) to SImode. */ |
1337 | if (optimize && !no_new_pseudos | |
1338 | && register_operand (operands[0], VOIDmode) | |
8fff4fc1 | 1339 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
1340 | { |
1341 | rtx tmp = gen_reg_rtx (SImode); | |
1342 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
1343 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); | |
1344 | operands[1] = gen_lowpart (HImode, tmp); | |
1345 | } | |
1346 | }) | |
1347 | ||
1348 | (define_insn "*movhi" | |
d3632d41 UW |
1349 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q") |
1350 | (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))] | |
9db1d521 HP |
1351 | "" |
1352 | "@ | |
d40c829f UW |
1353 | lr\t%0,%1 |
1354 | lhi\t%0,%h1 | |
1355 | lh\t%0,%1 | |
1356 | lhy\t%0,%1 | |
1357 | sth\t%1,%0 | |
1358 | sthy\t%1,%0 | |
19b63d8e | 1359 | #" |
d3632d41 | 1360 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS") |
b628bd8e | 1361 | (set_attr "type" "lr,*,*,*,store,store,*")]) |
9db1d521 | 1362 | |
84817c5d UW |
1363 | (define_peephole2 |
1364 | [(set (match_operand:HI 0 "register_operand" "") | |
1365 | (mem:HI (match_operand 1 "address_operand" "")))] | |
1366 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1367 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1368 | && get_pool_mode (operands[1]) == HImode | |
1369 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1370 | [(set (match_dup 0) (match_dup 2))] | |
1371 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1372 | |
9db1d521 HP |
1373 | ; |
1374 | ; movqi instruction pattern(s). | |
1375 | ; | |
1376 | ||
02ed3c5e UW |
1377 | (define_expand "movqi" |
1378 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1379 | (match_operand:QI 1 "general_operand" ""))] | |
1380 | "" | |
1381 | { | |
c19ec8f9 | 1382 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 1383 | is just as fast as a QImode load. */ |
c19ec8f9 | 1384 | if (TARGET_ZARCH && optimize && !no_new_pseudos |
02ed3c5e | 1385 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 1386 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 1387 | { |
c19ec8f9 UW |
1388 | rtx tmp = gen_reg_rtx (word_mode); |
1389 | rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]); | |
02ed3c5e UW |
1390 | emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); |
1391 | operands[1] = gen_lowpart (QImode, tmp); | |
1392 | } | |
1393 | }) | |
4023fb28 | 1394 | |
02ed3c5e | 1395 | (define_insn "*movqi" |
d3632d41 UW |
1396 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q") |
1397 | (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))] | |
9db1d521 HP |
1398 | "" |
1399 | "@ | |
d40c829f UW |
1400 | lr\t%0,%1 |
1401 | lhi\t%0,%b1 | |
1402 | ic\t%0,%1 | |
1403 | icy\t%0,%1 | |
1404 | stc\t%1,%0 | |
1405 | stcy\t%1,%0 | |
fc0ea003 UW |
1406 | mvi\t%S0,%b1 |
1407 | mviy\t%S0,%b1 | |
19b63d8e | 1408 | #" |
d3632d41 | 1409 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS") |
b628bd8e | 1410 | (set_attr "type" "lr,*,*,*,store,store,store,store,*")]) |
9db1d521 | 1411 | |
84817c5d UW |
1412 | (define_peephole2 |
1413 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
1414 | (mem:QI (match_operand 1 "address_operand" "")))] | |
1415 | "GET_CODE (operands[1]) == SYMBOL_REF | |
1416 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1417 | && get_pool_mode (operands[1]) == QImode | |
1418 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
1419 | [(set (match_dup 0) (match_dup 2))] | |
1420 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 1421 | |
9db1d521 | 1422 | ; |
05b9aaaa | 1423 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
1424 | ; |
1425 | ||
1426 | (define_insn "*movstrictqi" | |
d3632d41 UW |
1427 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
1428 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 1429 | "" |
d3632d41 | 1430 | "@ |
d40c829f UW |
1431 | ic\t%0,%1 |
1432 | icy\t%0,%1" | |
d3632d41 | 1433 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 HP |
1434 | |
1435 | ; | |
1436 | ; movstricthi instruction pattern(s). | |
1437 | ; | |
1438 | ||
1439 | (define_insn "*movstricthi" | |
d3632d41 | 1440 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 1441 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 1442 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 1443 | "" |
d3632d41 | 1444 | "@ |
fc0ea003 UW |
1445 | icm\t%0,3,%S1 |
1446 | icmy\t%0,3,%S1" | |
d3632d41 | 1447 | [(set_attr "op_type" "RS,RSY")]) |
9db1d521 HP |
1448 | |
1449 | ; | |
1450 | ; movstrictsi instruction pattern(s). | |
1451 | ; | |
1452 | ||
05b9aaaa | 1453 | (define_insn "movstrictsi" |
c5aa1d12 UW |
1454 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
1455 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9db1d521 HP |
1456 | "TARGET_64BIT" |
1457 | "@ | |
d40c829f UW |
1458 | lr\t%0,%1 |
1459 | l\t%0,%1 | |
c5aa1d12 UW |
1460 | ly\t%0,%1 |
1461 | ear\t%0,%1" | |
1462 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
1463 | (set_attr "type" "lr,load,load,*")]) | |
9db1d521 HP |
1464 | |
1465 | ; | |
1466 | ; movdf instruction pattern(s). | |
1467 | ; | |
1468 | ||
1469 | (define_expand "movdf" | |
1470 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1471 | (match_operand:DF 1 "general_operand" ""))] | |
1472 | "" | |
13c025c1 | 1473 | "") |
9db1d521 HP |
1474 | |
1475 | (define_insn "*movdf_64" | |
d096725d AS |
1476 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,m,?Q") |
1477 | (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,d,m,d,?Q"))] | |
4023fb28 | 1478 | "TARGET_64BIT" |
9db1d521 | 1479 | "@ |
d096725d | 1480 | lzdr\t%0 |
d40c829f UW |
1481 | ldr\t%0,%1 |
1482 | ld\t%0,%1 | |
1483 | ldy\t%0,%1 | |
1484 | std\t%1,%0 | |
1485 | stdy\t%1,%0 | |
1486 | lgr\t%0,%1 | |
1487 | lg\t%0,%1 | |
1488 | stg\t%1,%0 | |
19b63d8e | 1489 | #" |
d096725d AS |
1490 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS") |
1491 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,lr,load,store,*")]) | |
9db1d521 HP |
1492 | |
1493 | (define_insn "*movdf_31" | |
c4d50129 | 1494 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,Q,S,d,o,Q") |
11598938 | 1495 | (match_operand:DF 1 "general_operand" "G,f,R,T,f,f,Q,S,d,d,dPm,d,Q"))] |
4023fb28 | 1496 | "!TARGET_64BIT" |
9db1d521 | 1497 | "@ |
d096725d | 1498 | lzdr\t%0 |
d40c829f UW |
1499 | ldr\t%0,%1 |
1500 | ld\t%0,%1 | |
1501 | ldy\t%0,%1 | |
1502 | std\t%1,%0 | |
1503 | stdy\t%1,%0 | |
fc0ea003 | 1504 | lm\t%0,%N0,%S1 |
c4d50129 | 1505 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1506 | stm\t%1,%N1,%S0 |
c4d50129 | 1507 | stmy\t%1,%N1,%S0 |
4023fb28 | 1508 | # |
9b7c75b9 | 1509 | # |
19b63d8e | 1510 | #" |
c4d50129 AK |
1511 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*,SS") |
1512 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,fstoredf,fstoredf,\ | |
1513 | lm,lm,stm,stm,*,*,*")]) | |
4023fb28 UW |
1514 | |
1515 | (define_split | |
1516 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1517 | (match_operand:DF 1 "general_operand" ""))] | |
1518 | "!TARGET_64BIT && reload_completed | |
dc65c307 | 1519 | && s390_split_ok_p (operands[0], operands[1], DFmode, 0)" |
4023fb28 UW |
1520 | [(set (match_dup 2) (match_dup 4)) |
1521 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1522 | { |
dc65c307 UW |
1523 | operands[2] = operand_subword (operands[0], 0, 0, DFmode); |
1524 | operands[3] = operand_subword (operands[0], 1, 0, DFmode); | |
1525 | operands[4] = operand_subword (operands[1], 0, 0, DFmode); | |
1526 | operands[5] = operand_subword (operands[1], 1, 0, DFmode); | |
1527 | }) | |
1528 | ||
1529 | (define_split | |
1530 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
1531 | (match_operand:DF 1 "general_operand" ""))] | |
1532 | "!TARGET_64BIT && reload_completed | |
1533 | && s390_split_ok_p (operands[0], operands[1], DFmode, 1)" | |
1534 | [(set (match_dup 2) (match_dup 4)) | |
1535 | (set (match_dup 3) (match_dup 5))] | |
1536 | { | |
1537 | operands[2] = operand_subword (operands[0], 1, 0, DFmode); | |
1538 | operands[3] = operand_subword (operands[0], 0, 0, DFmode); | |
1539 | operands[4] = operand_subword (operands[1], 1, 0, DFmode); | |
1540 | operands[5] = operand_subword (operands[1], 0, 0, DFmode); | |
1541 | }) | |
9db1d521 | 1542 | |
4023fb28 UW |
1543 | (define_split |
1544 | [(set (match_operand:DF 0 "register_operand" "") | |
1545 | (match_operand:DF 1 "memory_operand" ""))] | |
1546 | "!TARGET_64BIT && reload_completed | |
8e509cf9 | 1547 | && !FP_REG_P (operands[0]) |
4023fb28 | 1548 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1549 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1550 | { |
1551 | rtx addr = operand_subword (operands[0], 1, 0, DFmode); | |
1552 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1553 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1554 | }) |
1555 | ||
1556 | (define_expand "reload_outdf" | |
9c3c3dcc | 1557 | [(parallel [(match_operand:DF 0 "" "") |
dc65c307 UW |
1558 | (match_operand:DF 1 "register_operand" "d") |
1559 | (match_operand:SI 2 "register_operand" "=&a")])] | |
1560 | "!TARGET_64BIT" | |
1561 | { | |
9c3c3dcc | 1562 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1563 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1564 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1565 | emit_move_insn (operands[0], operands[1]); | |
1566 | DONE; | |
1567 | }) | |
9db1d521 HP |
1568 | |
1569 | ; | |
1570 | ; movsf instruction pattern(s). | |
1571 | ; | |
1572 | ||
13c025c1 | 1573 | (define_insn "movsf" |
d096725d AS |
1574 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,R,T,?Q") |
1575 | (match_operand:SF 1 "general_operand" "G,f,R,T,f,f,d,R,T,d,d,?Q"))] | |
4023fb28 | 1576 | "" |
9db1d521 | 1577 | "@ |
d096725d | 1578 | lzer\t%0 |
d40c829f UW |
1579 | ler\t%0,%1 |
1580 | le\t%0,%1 | |
1581 | ley\t%0,%1 | |
1582 | ste\t%1,%0 | |
1583 | stey\t%1,%0 | |
1584 | lr\t%0,%1 | |
1585 | l\t%0,%1 | |
1586 | ly\t%0,%1 | |
1587 | st\t%1,%0 | |
1588 | sty\t%1,%0 | |
19b63d8e | 1589 | #" |
d096725d AS |
1590 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS") |
1591 | (set_attr "type" "fsimpsf,floadsf,floadsf,floadsf,fstoresf,fstoresf, | |
b628bd8e | 1592 | lr,load,load,store,store,*")]) |
4023fb28 | 1593 | |
9dc62c00 AK |
1594 | ; |
1595 | ; movcc instruction pattern | |
1596 | ; | |
1597 | ||
1598 | (define_insn "movcc" | |
1599 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
1600 | (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))] | |
1601 | "" | |
1602 | "@ | |
1603 | lr\t%0,%1 | |
1604 | tmh\t%1,12288 | |
1605 | ipm\t%0 | |
1606 | st\t%0,%1 | |
1607 | sty\t%0,%1 | |
1608 | l\t%1,%0 | |
1609 | ly\t%1,%0" | |
8dd3b235 AK |
1610 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
1611 | (set_attr "type" "lr,*,*,store,store,load,load")]) | |
9dc62c00 | 1612 | |
19b63d8e UW |
1613 | ; |
1614 | ; Block move (MVC) patterns. | |
1615 | ; | |
1616 | ||
1617 | (define_insn "*mvc" | |
1618 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
1619 | (match_operand:BLK 1 "memory_operand" "Q")) | |
1620 | (use (match_operand 2 "const_int_operand" "n"))] | |
1621 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1622 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 1623 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1624 | |
1625 | (define_split | |
1626 | [(set (match_operand 0 "memory_operand" "") | |
1627 | (match_operand 1 "memory_operand" ""))] | |
1628 | "reload_completed | |
1629 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1630 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1631 | [(parallel | |
1632 | [(set (match_dup 0) (match_dup 1)) | |
1633 | (use (match_dup 2))])] | |
1634 | { | |
1635 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1636 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1637 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1638 | }) | |
1639 | ||
1640 | (define_peephole2 | |
1641 | [(parallel | |
1642 | [(set (match_operand:BLK 0 "memory_operand" "") | |
1643 | (match_operand:BLK 1 "memory_operand" "")) | |
1644 | (use (match_operand 2 "const_int_operand" ""))]) | |
1645 | (parallel | |
1646 | [(set (match_operand:BLK 3 "memory_operand" "") | |
1647 | (match_operand:BLK 4 "memory_operand" "")) | |
1648 | (use (match_operand 5 "const_int_operand" ""))])] | |
1649 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
1650 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
bcf8c1cc AK |
1651 | && !s390_overlap_p (operands[0], operands[1], |
1652 | INTVAL (operands[2]) + INTVAL (operands[5])) | |
19b63d8e UW |
1653 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
1654 | [(parallel | |
1655 | [(set (match_dup 6) (match_dup 7)) | |
1656 | (use (match_dup 8))])] | |
1657 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
1658 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
1659 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
1660 | ||
1661 | ||
9db1d521 HP |
1662 | ; |
1663 | ; load_multiple pattern(s). | |
1664 | ; | |
22ea6b4f UW |
1665 | ; ??? Due to reload problems with replacing registers inside match_parallel |
1666 | ; we currently support load_multiple/store_multiple only after reload. | |
1667 | ; | |
9db1d521 HP |
1668 | |
1669 | (define_expand "load_multiple" | |
1670 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1671 | (match_operand 1 "" "")) | |
1672 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 1673 | "reload_completed" |
9db1d521 | 1674 | { |
c19ec8f9 | 1675 | enum machine_mode mode; |
9db1d521 HP |
1676 | int regno; |
1677 | int count; | |
1678 | rtx from; | |
4023fb28 | 1679 | int i, off; |
9db1d521 HP |
1680 | |
1681 | /* Support only loading a constant number of fixed-point registers from | |
1682 | memory and only bother with this if more than two */ | |
1683 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1684 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1685 | || INTVAL (operands[2]) > 16 |
1686 | || GET_CODE (operands[1]) != MEM | |
1687 | || GET_CODE (operands[0]) != REG | |
1688 | || REGNO (operands[0]) >= 16) | |
1689 | FAIL; | |
1690 | ||
1691 | count = INTVAL (operands[2]); | |
1692 | regno = REGNO (operands[0]); | |
c19ec8f9 UW |
1693 | mode = GET_MODE (operands[0]); |
1694 | if (mode != SImode && mode != word_mode) | |
1695 | FAIL; | |
9db1d521 HP |
1696 | |
1697 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1698 | if (no_new_pseudos) |
1699 | { | |
1700 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
1701 | { | |
1702 | from = XEXP (operands[1], 0); | |
1703 | off = 0; | |
1704 | } | |
1705 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
1706 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
1707 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
1708 | { | |
1709 | from = XEXP (XEXP (operands[1], 0), 0); | |
1710 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
1711 | } | |
1712 | else | |
1713 | FAIL; | |
4023fb28 UW |
1714 | } |
1715 | else | |
1716 | { | |
1717 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
1718 | off = 0; | |
1719 | } | |
9db1d521 HP |
1720 | |
1721 | for (i = 0; i < count; i++) | |
1722 | XVECEXP (operands[3], 0, i) | |
c19ec8f9 UW |
1723 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), |
1724 | change_address (operands[1], mode, | |
1725 | plus_constant (from, off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 1726 | }) |
9db1d521 HP |
1727 | |
1728 | (define_insn "*load_multiple_di" | |
1729 | [(match_parallel 0 "load_multiple_operation" | |
1730 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 1731 | (match_operand:DI 2 "s_operand" "QS"))])] |
22ea6b4f | 1732 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
1733 | { |
1734 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1735 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 1736 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 1737 | } |
d3632d41 | 1738 | [(set_attr "op_type" "RSY") |
4023fb28 | 1739 | (set_attr "type" "lm")]) |
9db1d521 HP |
1740 | |
1741 | (define_insn "*load_multiple_si" | |
1742 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
1743 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
1744 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 1745 | "reload_completed" |
9db1d521 HP |
1746 | { |
1747 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1748 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 1749 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 1750 | } |
d3632d41 | 1751 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1752 | (set_attr "type" "lm")]) |
9db1d521 HP |
1753 | |
1754 | ; | |
c7453384 | 1755 | ; store multiple pattern(s). |
9db1d521 HP |
1756 | ; |
1757 | ||
1758 | (define_expand "store_multiple" | |
1759 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
1760 | (match_operand 1 "" "")) | |
1761 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 1762 | "reload_completed" |
9db1d521 | 1763 | { |
c19ec8f9 | 1764 | enum machine_mode mode; |
9db1d521 HP |
1765 | int regno; |
1766 | int count; | |
1767 | rtx to; | |
4023fb28 | 1768 | int i, off; |
9db1d521 HP |
1769 | |
1770 | /* Support only storing a constant number of fixed-point registers to | |
1771 | memory and only bother with this if more than two. */ | |
1772 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 1773 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
1774 | || INTVAL (operands[2]) > 16 |
1775 | || GET_CODE (operands[0]) != MEM | |
1776 | || GET_CODE (operands[1]) != REG | |
1777 | || REGNO (operands[1]) >= 16) | |
1778 | FAIL; | |
1779 | ||
1780 | count = INTVAL (operands[2]); | |
1781 | regno = REGNO (operands[1]); | |
c19ec8f9 UW |
1782 | mode = GET_MODE (operands[1]); |
1783 | if (mode != SImode && mode != word_mode) | |
1784 | FAIL; | |
9db1d521 HP |
1785 | |
1786 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 UW |
1787 | |
1788 | if (no_new_pseudos) | |
1789 | { | |
1790 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
1791 | { | |
1792 | to = XEXP (operands[0], 0); | |
1793 | off = 0; | |
1794 | } | |
1795 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
1796 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
1797 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
1798 | { | |
1799 | to = XEXP (XEXP (operands[0], 0), 0); | |
1800 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
1801 | } | |
1802 | else | |
1803 | FAIL; | |
4023fb28 | 1804 | } |
c7453384 | 1805 | else |
4023fb28 UW |
1806 | { |
1807 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
1808 | off = 0; | |
1809 | } | |
9db1d521 HP |
1810 | |
1811 | for (i = 0; i < count; i++) | |
1812 | XVECEXP (operands[3], 0, i) | |
1813 | = gen_rtx_SET (VOIDmode, | |
c19ec8f9 UW |
1814 | change_address (operands[0], mode, |
1815 | plus_constant (to, off + i * GET_MODE_SIZE (mode))), | |
1816 | gen_rtx_REG (mode, regno + i)); | |
10bbf137 | 1817 | }) |
9db1d521 HP |
1818 | |
1819 | (define_insn "*store_multiple_di" | |
1820 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 1821 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 1822 | (match_operand:DI 2 "register_operand" "r"))])] |
22ea6b4f | 1823 | "reload_completed && word_mode == DImode" |
9db1d521 HP |
1824 | { |
1825 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1826 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 1827 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 1828 | } |
d3632d41 | 1829 | [(set_attr "op_type" "RSY") |
4023fb28 | 1830 | (set_attr "type" "stm")]) |
9db1d521 HP |
1831 | |
1832 | ||
1833 | (define_insn "*store_multiple_si" | |
1834 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
1835 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
1836 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 1837 | "reload_completed" |
9db1d521 HP |
1838 | { |
1839 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 1840 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 1841 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 1842 | } |
d3632d41 | 1843 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 1844 | (set_attr "type" "stm")]) |
9db1d521 HP |
1845 | |
1846 | ;; | |
1847 | ;; String instructions. | |
1848 | ;; | |
1849 | ||
9bb86f41 UW |
1850 | (define_insn "*execute" |
1851 | [(match_parallel 0 "" | |
1852 | [(unspec [(match_operand 1 "register_operand" "a") | |
1853 | (match_operand:BLK 2 "memory_operand" "R") | |
1854 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
1855 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
1856 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
1857 | "ex\t%1,%2" | |
29a74354 UW |
1858 | [(set_attr "op_type" "RX") |
1859 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
1860 | |
1861 | ||
91d39d71 UW |
1862 | ; |
1863 | ; strlenM instruction pattern(s). | |
1864 | ; | |
1865 | ||
9db2f16d | 1866 | (define_expand "strlen<mode>" |
ccbdc0d4 | 1867 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 1868 | (parallel |
91d39d71 | 1869 | [(set (match_dup 4) |
9db2f16d | 1870 | (unspec:P [(const_int 0) |
91d39d71 | 1871 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 1872 | (reg:SI 0) |
91d39d71 | 1873 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 1874 | (clobber (scratch:P)) |
ae156f85 | 1875 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 1876 | (parallel |
9db2f16d AS |
1877 | [(set (match_operand:P 0 "register_operand" "") |
1878 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 1879 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 1880 | "" |
91d39d71 | 1881 | { |
9db2f16d AS |
1882 | operands[4] = gen_reg_rtx (Pmode); |
1883 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
1884 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
1885 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
1886 | }) | |
1887 | ||
9db2f16d AS |
1888 | (define_insn "*strlen<mode>" |
1889 | [(set (match_operand:P 0 "register_operand" "=a") | |
1890 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
1891 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 1892 | (reg:SI 0) |
91d39d71 | 1893 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 1894 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 1895 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 1896 | "" |
91d39d71 | 1897 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
1898 | [(set_attr "length" "8") |
1899 | (set_attr "type" "vs")]) | |
91d39d71 | 1900 | |
ccbdc0d4 AS |
1901 | ; |
1902 | ; cmpstrM instruction pattern(s). | |
1903 | ; | |
1904 | ||
1905 | (define_expand "cmpstrsi" | |
1906 | [(set (reg:SI 0) (const_int 0)) | |
1907 | (parallel | |
1908 | [(clobber (match_operand 3 "" "")) | |
1909 | (clobber (match_dup 4)) | |
1910 | (set (reg:CCU CC_REGNUM) | |
1911 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
1912 | (match_operand:BLK 2 "memory_operand" ""))) | |
1913 | (use (reg:SI 0))]) | |
1914 | (parallel | |
1915 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1916 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_CMPINT)) | |
1917 | (clobber (reg:CC CC_REGNUM))])] | |
1918 | "" | |
1919 | { | |
1920 | /* As the result of CMPINT is inverted compared to what we need, | |
1921 | we have to swap the operands. */ | |
1922 | rtx op1 = operands[2]; | |
1923 | rtx op2 = operands[1]; | |
1924 | rtx addr1 = gen_reg_rtx (Pmode); | |
1925 | rtx addr2 = gen_reg_rtx (Pmode); | |
1926 | ||
1927 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
1928 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
1929 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
1930 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
1931 | operands[3] = addr1; | |
1932 | operands[4] = addr2; | |
1933 | }) | |
1934 | ||
1935 | (define_insn "*cmpstr<mode>" | |
1936 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
1937 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
1938 | (set (reg:CCU CC_REGNUM) | |
1939 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
1940 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
1941 | (use (reg:SI 0))] | |
1942 | "" | |
1943 | "clst\t%0,%1\;jo\t.-4" | |
1944 | [(set_attr "length" "8") | |
1945 | (set_attr "type" "vs")]) | |
1946 | ||
742090fc AS |
1947 | ; |
1948 | ; movstr instruction pattern. | |
1949 | ; | |
1950 | ||
1951 | (define_expand "movstr" | |
1952 | [(set (reg:SI 0) (const_int 0)) | |
1953 | (parallel | |
1954 | [(clobber (match_dup 3)) | |
1955 | (set (match_operand:BLK 1 "memory_operand" "") | |
1956 | (match_operand:BLK 2 "memory_operand" "")) | |
1957 | (set (match_operand 0 "register_operand" "") | |
1958 | (unspec [(match_dup 1) | |
1959 | (match_dup 2) | |
1960 | (reg:SI 0)] UNSPEC_MVST)) | |
1961 | (clobber (reg:CC CC_REGNUM))])] | |
1962 | "" | |
1963 | { | |
1964 | rtx addr1 = gen_reg_rtx (Pmode); | |
1965 | rtx addr2 = gen_reg_rtx (Pmode); | |
1966 | ||
1967 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
1968 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
1969 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
1970 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
1971 | operands[3] = addr2; | |
1972 | }) | |
1973 | ||
1974 | (define_insn "*movstr" | |
1975 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
1976 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
1977 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
1978 | (set (match_operand:P 0 "register_operand" "=d") | |
1979 | (unspec [(mem:BLK (match_dup 1)) | |
1980 | (mem:BLK (match_dup 3)) | |
1981 | (reg:SI 0)] UNSPEC_MVST)) | |
1982 | (clobber (reg:CC CC_REGNUM))] | |
1983 | "" | |
1984 | "mvst\t%1,%2\;jo\t.-4" | |
1985 | [(set_attr "length" "8") | |
1986 | (set_attr "type" "vs")]) | |
1987 | ||
1988 | ||
9db1d521 | 1989 | ; |
70128ad9 | 1990 | ; movmemM instruction pattern(s). |
9db1d521 HP |
1991 | ; |
1992 | ||
9db2f16d | 1993 | (define_expand "movmem<mode>" |
a41c6c53 UW |
1994 | [(set (match_operand:BLK 0 "memory_operand" "") |
1995 | (match_operand:BLK 1 "memory_operand" "")) | |
9db2f16d | 1996 | (use (match_operand:GPR 2 "general_operand" "")) |
a41c6c53 UW |
1997 | (match_operand 3 "" "")] |
1998 | "" | |
70128ad9 | 1999 | "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 2000 | |
ecbe845e UW |
2001 | ; Move a block that is up to 256 bytes in length. |
2002 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2003 | |
70128ad9 | 2004 | (define_expand "movmem_short" |
b9404c99 UW |
2005 | [(parallel |
2006 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2007 | (match_operand:BLK 1 "memory_operand" "")) | |
2008 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2009 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2010 | (clobber (match_dup 3))])] |
2011 | "" | |
2012 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 2013 | |
70128ad9 | 2014 | (define_insn "*movmem_short" |
9bb86f41 UW |
2015 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q") |
2016 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q")) | |
2017 | (use (match_operand 2 "nonmemory_operand" "n,a,a")) | |
2018 | (use (match_operand 3 "immediate_operand" "X,R,X")) | |
2019 | (clobber (match_scratch 4 "=X,X,&a"))] | |
b9404c99 | 2020 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
9bb86f41 UW |
2021 | && GET_MODE (operands[4]) == Pmode" |
2022 | "#" | |
b628bd8e | 2023 | [(set_attr "type" "cs")]) |
ecbe845e | 2024 | |
9bb86f41 UW |
2025 | (define_split |
2026 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2027 | (match_operand:BLK 1 "memory_operand" "")) | |
2028 | (use (match_operand 2 "const_int_operand" "")) | |
2029 | (use (match_operand 3 "immediate_operand" "")) | |
2030 | (clobber (scratch))] | |
2031 | "reload_completed" | |
2032 | [(parallel | |
2033 | [(set (match_dup 0) (match_dup 1)) | |
2034 | (use (match_dup 2))])] | |
2035 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 2036 | |
9bb86f41 UW |
2037 | (define_split |
2038 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2039 | (match_operand:BLK 1 "memory_operand" "")) | |
2040 | (use (match_operand 2 "register_operand" "")) | |
2041 | (use (match_operand 3 "memory_operand" "")) | |
2042 | (clobber (scratch))] | |
2043 | "reload_completed" | |
2044 | [(parallel | |
2045 | [(unspec [(match_dup 2) (match_dup 3) | |
2046 | (const_int 0)] UNSPEC_EXECUTE) | |
2047 | (set (match_dup 0) (match_dup 1)) | |
2048 | (use (const_int 1))])] | |
2049 | "") | |
2050 | ||
2051 | (define_split | |
2052 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2053 | (match_operand:BLK 1 "memory_operand" "")) | |
2054 | (use (match_operand 2 "register_operand" "")) | |
2055 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2056 | (clobber (match_operand 3 "register_operand" ""))] | |
2057 | "reload_completed && TARGET_CPU_ZARCH" | |
2058 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
2059 | (parallel | |
2060 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) | |
2061 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
2062 | (set (match_dup 0) (match_dup 1)) | |
2063 | (use (const_int 1))])] | |
2064 | "operands[4] = gen_label_rtx ();") | |
2065 | ||
a41c6c53 | 2066 | ; Move a block of arbitrary length. |
9db1d521 | 2067 | |
70128ad9 | 2068 | (define_expand "movmem_long" |
b9404c99 UW |
2069 | [(parallel |
2070 | [(clobber (match_dup 2)) | |
2071 | (clobber (match_dup 3)) | |
2072 | (set (match_operand:BLK 0 "memory_operand" "") | |
2073 | (match_operand:BLK 1 "memory_operand" "")) | |
2074 | (use (match_operand 2 "general_operand" "")) | |
2075 | (use (match_dup 3)) | |
ae156f85 | 2076 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
2077 | "" |
2078 | { | |
2079 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
2080 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2081 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2082 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2083 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
2084 | rtx len0 = gen_lowpart (Pmode, reg0); | |
2085 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2086 | ||
2087 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
2088 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2089 | emit_move_insn (len0, operands[2]); | |
2090 | ||
2091 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
2092 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2093 | emit_move_insn (len1, operands[2]); | |
2094 | ||
2095 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2096 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2097 | operands[2] = reg0; | |
2098 | operands[3] = reg1; | |
2099 | }) | |
2100 | ||
a1aed706 AS |
2101 | (define_insn "*movmem_long" |
2102 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2103 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
2104 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
2105 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
2106 | (use (match_dup 2)) |
2107 | (use (match_dup 3)) | |
ae156f85 | 2108 | (clobber (reg:CC CC_REGNUM))] |
a1aed706 | 2109 | "" |
d40c829f | 2110 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2111 | [(set_attr "length" "8") |
2112 | (set_attr "type" "vs")]) | |
9db1d521 HP |
2113 | |
2114 | ; | |
57e84f18 | 2115 | ; setmemM instruction pattern(s). |
9db1d521 HP |
2116 | ; |
2117 | ||
57e84f18 | 2118 | (define_expand "setmem<mode>" |
a41c6c53 | 2119 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 2120 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 2121 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 2122 | (match_operand 3 "" "")] |
a41c6c53 | 2123 | "" |
6d057022 | 2124 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 2125 | |
a41c6c53 | 2126 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
2127 | ; The block length is taken as (operands[1] % 256) + 1. |
2128 | ||
70128ad9 | 2129 | (define_expand "clrmem_short" |
b9404c99 UW |
2130 | [(parallel |
2131 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2132 | (const_int 0)) | |
2133 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 2134 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 2135 | (clobber (match_dup 2)) |
ae156f85 | 2136 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
2137 | "" |
2138 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2139 | |
70128ad9 | 2140 | (define_insn "*clrmem_short" |
9bb86f41 | 2141 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q") |
a41c6c53 | 2142 | (const_int 0)) |
9bb86f41 UW |
2143 | (use (match_operand 1 "nonmemory_operand" "n,a,a")) |
2144 | (use (match_operand 2 "immediate_operand" "X,R,X")) | |
2145 | (clobber (match_scratch 3 "=X,X,&a")) | |
ae156f85 | 2146 | (clobber (reg:CC CC_REGNUM))] |
b9404c99 | 2147 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode) |
9bb86f41 UW |
2148 | && GET_MODE (operands[3]) == Pmode" |
2149 | "#" | |
b628bd8e | 2150 | [(set_attr "type" "cs")]) |
9bb86f41 UW |
2151 | |
2152 | (define_split | |
2153 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2154 | (const_int 0)) | |
2155 | (use (match_operand 1 "const_int_operand" "")) | |
2156 | (use (match_operand 2 "immediate_operand" "")) | |
2157 | (clobber (scratch)) | |
ae156f85 | 2158 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2159 | "reload_completed" |
2160 | [(parallel | |
2161 | [(set (match_dup 0) (const_int 0)) | |
2162 | (use (match_dup 1)) | |
ae156f85 | 2163 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 2164 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 2165 | |
9bb86f41 UW |
2166 | (define_split |
2167 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2168 | (const_int 0)) | |
2169 | (use (match_operand 1 "register_operand" "")) | |
2170 | (use (match_operand 2 "memory_operand" "")) | |
2171 | (clobber (scratch)) | |
ae156f85 | 2172 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2173 | "reload_completed" |
2174 | [(parallel | |
2175 | [(unspec [(match_dup 1) (match_dup 2) | |
2176 | (const_int 0)] UNSPEC_EXECUTE) | |
2177 | (set (match_dup 0) (const_int 0)) | |
2178 | (use (const_int 1)) | |
ae156f85 | 2179 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 2180 | "") |
9db1d521 | 2181 | |
9bb86f41 UW |
2182 | (define_split |
2183 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2184 | (const_int 0)) | |
2185 | (use (match_operand 1 "register_operand" "")) | |
2186 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2187 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 2188 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
2189 | "reload_completed && TARGET_CPU_ZARCH" |
2190 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
2191 | (parallel | |
2192 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) | |
2193 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
2194 | (set (match_dup 0) (const_int 0)) | |
2195 | (use (const_int 1)) | |
ae156f85 | 2196 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
2197 | "operands[3] = gen_label_rtx ();") |
2198 | ||
6d057022 | 2199 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 2200 | |
6d057022 | 2201 | (define_expand "setmem_long" |
b9404c99 UW |
2202 | [(parallel |
2203 | [(clobber (match_dup 1)) | |
2204 | (set (match_operand:BLK 0 "memory_operand" "") | |
4989e88a | 2205 | (match_operand 2 "shift_count_or_setmem_operand" "")) |
b9404c99 | 2206 | (use (match_operand 1 "general_operand" "")) |
6d057022 | 2207 | (use (match_dup 3)) |
ae156f85 | 2208 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 2209 | "" |
a41c6c53 | 2210 | { |
b9404c99 UW |
2211 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; |
2212 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2213 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2214 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2215 | rtx len0 = gen_lowpart (Pmode, reg0); | |
9db1d521 | 2216 | |
b9404c99 UW |
2217 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); |
2218 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2219 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 2220 | |
b9404c99 | 2221 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 2222 | |
b9404c99 UW |
2223 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
2224 | operands[1] = reg0; | |
6d057022 | 2225 | operands[3] = reg1; |
b9404c99 | 2226 | }) |
a41c6c53 | 2227 | |
6d057022 | 2228 | (define_insn "*setmem_long" |
a1aed706 | 2229 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 2230 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
4989e88a | 2231 | (match_operand 2 "shift_count_or_setmem_operand" "Y")) |
6d057022 | 2232 | (use (match_dup 3)) |
a1aed706 | 2233 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 2234 | (clobber (reg:CC CC_REGNUM))] |
a1aed706 | 2235 | "" |
6d057022 | 2236 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
2237 | [(set_attr "length" "8") |
2238 | (set_attr "type" "vs")]) | |
9db1d521 | 2239 | |
4989e88a AK |
2240 | (define_insn "*setmem_long_and" |
2241 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2242 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
2243 | (and (match_operand 2 "shift_count_or_setmem_operand" "Y") | |
2244 | (match_operand 4 "const_int_operand" "n"))) | |
2245 | (use (match_dup 3)) | |
2246 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
2247 | (clobber (reg:CC CC_REGNUM))] | |
2248 | "(INTVAL (operands[4]) & 255) == 255" | |
2249 | "mvcle\t%0,%1,%Y2\;jo\t.-4" | |
2250 | [(set_attr "length" "8") | |
2251 | (set_attr "type" "vs")]) | |
9db1d521 | 2252 | ; |
358b8f01 | 2253 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
2254 | ; |
2255 | ||
358b8f01 | 2256 | (define_expand "cmpmemsi" |
a41c6c53 UW |
2257 | [(set (match_operand:SI 0 "register_operand" "") |
2258 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
2259 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
2260 | (use (match_operand:SI 3 "general_operand" "")) | |
2261 | (use (match_operand:SI 4 "" ""))] | |
2262 | "" | |
c7453384 | 2263 | "s390_expand_cmpmem (operands[0], operands[1], |
a41c6c53 | 2264 | operands[2], operands[3]); DONE;") |
9db1d521 | 2265 | |
a41c6c53 UW |
2266 | ; Compare a block that is up to 256 bytes in length. |
2267 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 2268 | |
b9404c99 UW |
2269 | (define_expand "cmpmem_short" |
2270 | [(parallel | |
ae156f85 | 2271 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 2272 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
2273 | (match_operand:BLK 1 "memory_operand" ""))) |
2274 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 2275 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
2276 | (clobber (match_dup 3))])] |
2277 | "" | |
2278 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 2279 | |
b9404c99 | 2280 | (define_insn "*cmpmem_short" |
ae156f85 | 2281 | [(set (reg:CCU CC_REGNUM) |
d4f52f0e | 2282 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q") |
9bb86f41 UW |
2283 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))) |
2284 | (use (match_operand 2 "nonmemory_operand" "n,a,a")) | |
2285 | (use (match_operand 3 "immediate_operand" "X,R,X")) | |
2286 | (clobber (match_scratch 4 "=X,X,&a"))] | |
b9404c99 | 2287 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode) |
9bb86f41 UW |
2288 | && GET_MODE (operands[4]) == Pmode" |
2289 | "#" | |
b628bd8e | 2290 | [(set_attr "type" "cs")]) |
9db1d521 | 2291 | |
9bb86f41 | 2292 | (define_split |
ae156f85 | 2293 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
2294 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
2295 | (match_operand:BLK 1 "memory_operand" ""))) | |
2296 | (use (match_operand 2 "const_int_operand" "")) | |
2297 | (use (match_operand 3 "immediate_operand" "")) | |
2298 | (clobber (scratch))] | |
2299 | "reload_completed" | |
2300 | [(parallel | |
ae156f85 | 2301 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
2302 | (use (match_dup 2))])] |
2303 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 2304 | |
9bb86f41 | 2305 | (define_split |
ae156f85 | 2306 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
2307 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
2308 | (match_operand:BLK 1 "memory_operand" ""))) | |
2309 | (use (match_operand 2 "register_operand" "")) | |
2310 | (use (match_operand 3 "memory_operand" "")) | |
2311 | (clobber (scratch))] | |
2312 | "reload_completed" | |
2313 | [(parallel | |
2314 | [(unspec [(match_dup 2) (match_dup 3) | |
2315 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 2316 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
2317 | (use (const_int 1))])] |
2318 | "") | |
2319 | ||
2320 | (define_split | |
ae156f85 | 2321 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
2322 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
2323 | (match_operand:BLK 1 "memory_operand" ""))) | |
2324 | (use (match_operand 2 "register_operand" "")) | |
2325 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
2326 | (clobber (match_operand 3 "register_operand" ""))] | |
2327 | "reload_completed && TARGET_CPU_ZARCH" | |
2328 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
2329 | (parallel | |
2330 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) | |
2331 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
ae156f85 | 2332 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
2333 | (use (const_int 1))])] |
2334 | "operands[4] = gen_label_rtx ();") | |
2335 | ||
a41c6c53 | 2336 | ; Compare a block of arbitrary length. |
9db1d521 | 2337 | |
b9404c99 UW |
2338 | (define_expand "cmpmem_long" |
2339 | [(parallel | |
2340 | [(clobber (match_dup 2)) | |
2341 | (clobber (match_dup 3)) | |
ae156f85 | 2342 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 2343 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
2344 | (match_operand:BLK 1 "memory_operand" ""))) |
2345 | (use (match_operand 2 "general_operand" "")) | |
2346 | (use (match_dup 3))])] | |
2347 | "" | |
2348 | { | |
2349 | enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode; | |
2350 | rtx reg0 = gen_reg_rtx (dword_mode); | |
2351 | rtx reg1 = gen_reg_rtx (dword_mode); | |
2352 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0)); | |
2353 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1)); | |
2354 | rtx len0 = gen_lowpart (Pmode, reg0); | |
2355 | rtx len1 = gen_lowpart (Pmode, reg1); | |
2356 | ||
2357 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0)); | |
2358 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); | |
2359 | emit_move_insn (len0, operands[2]); | |
2360 | ||
2361 | emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1)); | |
2362 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2363 | emit_move_insn (len1, operands[2]); | |
2364 | ||
2365 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
2366 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2367 | operands[2] = reg0; | |
2368 | operands[3] = reg1; | |
2369 | }) | |
2370 | ||
a1aed706 AS |
2371 | (define_insn "*cmpmem_long" |
2372 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
2373 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 2374 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
2375 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
2376 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
2377 | (use (match_dup 2)) |
2378 | (use (match_dup 3))] | |
a1aed706 | 2379 | "" |
287ff198 | 2380 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
2381 | [(set_attr "length" "8") |
2382 | (set_attr "type" "vs")]) | |
9db1d521 | 2383 | |
02887425 UW |
2384 | ; Convert CCUmode condition code to integer. |
2385 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 2386 | |
02887425 | 2387 | (define_insn_and_split "cmpint" |
9db1d521 | 2388 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 UW |
2389 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
2390 | UNSPEC_CMPINT)) | |
ae156f85 | 2391 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2392 | "" |
02887425 UW |
2393 | "#" |
2394 | "reload_completed" | |
2395 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
2396 | (parallel | |
2397 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 2398 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
2399 | |
2400 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 2401 | [(set (reg CC_REGNUM) |
02887425 UW |
2402 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
2403 | UNSPEC_CMPINT) | |
2404 | (const_int 0))) | |
2405 | (set (match_operand:SI 0 "register_operand" "=d") | |
2406 | (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))] | |
2407 | "s390_match_ccmode (insn, CCSmode)" | |
2408 | "#" | |
2409 | "&& reload_completed" | |
2410 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
2411 | (parallel | |
2412 | [(set (match_dup 2) (match_dup 3)) | |
2413 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 2414 | { |
02887425 UW |
2415 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
2416 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
2417 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
2418 | }) | |
9db1d521 | 2419 | |
02887425 | 2420 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 2421 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 UW |
2422 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
2423 | UNSPEC_CMPINT))) | |
ae156f85 | 2424 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2425 | "TARGET_64BIT" |
02887425 UW |
2426 | "#" |
2427 | "&& reload_completed" | |
2428 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
2429 | (parallel | |
2430 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 2431 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
2432 | |
2433 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 2434 | [(set (reg CC_REGNUM) |
02887425 UW |
2435 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
2436 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] | |
2437 | UNSPEC_CMPINT) 0) | |
2438 | (const_int 32)) (const_int 32)) | |
2439 | (const_int 0))) | |
2440 | (set (match_operand:DI 0 "register_operand" "=d") | |
2441 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))] | |
2442 | "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT" | |
2443 | "#" | |
2444 | "&& reload_completed" | |
2445 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
2446 | (parallel | |
2447 | [(set (match_dup 2) (match_dup 3)) | |
2448 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 2449 | { |
02887425 UW |
2450 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
2451 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
2452 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
2453 | }) | |
9db1d521 | 2454 | |
4023fb28 | 2455 | |
9db1d521 HP |
2456 | ;; |
2457 | ;;- Conversion instructions. | |
2458 | ;; | |
2459 | ||
6fa05db6 | 2460 | (define_insn "*sethighpartsi" |
d3632d41 | 2461 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
2462 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
2463 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 2464 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 2465 | "" |
d3632d41 | 2466 | "@ |
6fa05db6 AS |
2467 | icm\t%0,%2,%S1 |
2468 | icmy\t%0,%2,%S1" | |
d3632d41 | 2469 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 | 2470 | |
6fa05db6 | 2471 | (define_insn "*sethighpartdi_64" |
4023fb28 | 2472 | [(set (match_operand:DI 0 "register_operand" "=d") |
6fa05db6 AS |
2473 | (unspec:DI [(match_operand:BLK 1 "s_operand" "QS") |
2474 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) | |
ae156f85 | 2475 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 2476 | "TARGET_64BIT" |
6fa05db6 | 2477 | "icmh\t%0,%2,%S1" |
d3632d41 | 2478 | [(set_attr "op_type" "RSY")]) |
4023fb28 | 2479 | |
6fa05db6 | 2480 | (define_insn "*sethighpartdi_31" |
d3632d41 | 2481 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
2482 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
2483 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 2484 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 2485 | "!TARGET_64BIT" |
d3632d41 | 2486 | "@ |
6fa05db6 AS |
2487 | icm\t%0,%2,%S1 |
2488 | icmy\t%0,%2,%S1" | |
d3632d41 | 2489 | [(set_attr "op_type" "RS,RSY")]) |
4023fb28 | 2490 | |
6fa05db6 AS |
2491 | (define_insn_and_split "*extzv<mode>" |
2492 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
2493 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
2494 | (match_operand 2 "const_int_operand" "n") | |
2495 | (const_int 0))) | |
ae156f85 | 2496 | (clobber (reg:CC CC_REGNUM))] |
6fa05db6 AS |
2497 | "INTVAL (operands[2]) > 0 |
2498 | && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)" | |
cc7ab9b7 UW |
2499 | "#" |
2500 | "&& reload_completed" | |
4023fb28 | 2501 | [(parallel |
6fa05db6 | 2502 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 2503 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 2504 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 2505 | { |
6fa05db6 AS |
2506 | int bitsize = INTVAL (operands[2]); |
2507 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
2508 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
2509 | ||
2510 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2511 | set_mem_size (operands[1], GEN_INT (size)); | |
2512 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize); | |
2513 | operands[3] = GEN_INT (mask); | |
b628bd8e | 2514 | }) |
4023fb28 | 2515 | |
6fa05db6 AS |
2516 | (define_insn_and_split "*extv<mode>" |
2517 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
2518 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
2519 | (match_operand 2 "const_int_operand" "n") | |
2520 | (const_int 0))) | |
ae156f85 | 2521 | (clobber (reg:CC CC_REGNUM))] |
6fa05db6 AS |
2522 | "INTVAL (operands[2]) > 0 |
2523 | && INTVAL (operands[2]) <= GET_MODE_BITSIZE (SImode)" | |
cc7ab9b7 UW |
2524 | "#" |
2525 | "&& reload_completed" | |
4023fb28 | 2526 | [(parallel |
6fa05db6 | 2527 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 2528 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
2529 | (parallel |
2530 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
2531 | (clobber (reg:CC CC_REGNUM))])] | |
2532 | { | |
2533 | int bitsize = INTVAL (operands[2]); | |
2534 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
2535 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
2536 | ||
2537 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2538 | set_mem_size (operands[1], GEN_INT (size)); | |
2539 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - bitsize); | |
2540 | operands[3] = GEN_INT (mask); | |
2541 | }) | |
2542 | ||
2543 | ; | |
2544 | ; insv instruction patterns | |
2545 | ; | |
2546 | ||
2547 | (define_expand "insv" | |
2548 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
2549 | (match_operand 1 "const_int_operand" "") | |
2550 | (match_operand 2 "const_int_operand" "")) | |
2551 | (match_operand 3 "general_operand" ""))] | |
2552 | "" | |
4023fb28 | 2553 | { |
6fa05db6 AS |
2554 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
2555 | DONE; | |
2556 | FAIL; | |
b628bd8e | 2557 | }) |
4023fb28 | 2558 | |
6fa05db6 AS |
2559 | (define_insn "*insv<mode>_mem_reg" |
2560 | [(set (zero_extract:P (match_operand:QI 0 "memory_operand" "+Q,S") | |
2561 | (match_operand 1 "const_int_operand" "n,n") | |
2562 | (const_int 0)) | |
2563 | (match_operand:P 2 "register_operand" "d,d"))] | |
2564 | "INTVAL (operands[1]) > 0 | |
2565 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
2566 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
2567 | { | |
2568 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
2569 | ||
2570 | operands[1] = GEN_INT ((1ul << size) - 1); | |
2571 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" | |
2572 | : "stcmy\t%2,%1,%S0"; | |
2573 | } | |
2574 | [(set_attr "op_type" "RS,RSY")]) | |
2575 | ||
2576 | (define_insn "*insvdi_mem_reghigh" | |
2577 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") | |
2578 | (match_operand 1 "const_int_operand" "n") | |
2579 | (const_int 0)) | |
2580 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
2581 | (const_int 32)))] | |
2582 | "TARGET_64BIT | |
2583 | && INTVAL (operands[1]) > 0 | |
2584 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
2585 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
2586 | { | |
2587 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
2588 | ||
2589 | operands[1] = GEN_INT ((1ul << size) - 1); | |
2590 | return "stcmh\t%2,%1,%S0"; | |
2591 | } | |
2592 | [(set_attr "op_type" "RSY")]) | |
2593 | ||
2594 | (define_insn "*insv<mode>_reg_imm" | |
2595 | [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") | |
2596 | (const_int 16) | |
2597 | (match_operand 1 "const_int_operand" "n")) | |
0101708c | 2598 | (match_operand:P 2 "const_int_operand" "n"))] |
6fa05db6 AS |
2599 | "TARGET_ZARCH |
2600 | && INTVAL (operands[1]) >= 0 | |
2601 | && INTVAL (operands[1]) < BITS_PER_WORD | |
2602 | && INTVAL (operands[1]) % 16 == 0" | |
2603 | { | |
2604 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
2605 | { | |
2606 | case 64: return "iihh\t%0,%x2"; break; | |
2607 | case 48: return "iihl\t%0,%x2"; break; | |
2608 | case 32: return "iilh\t%0,%x2"; break; | |
2609 | case 16: return "iill\t%0,%x2"; break; | |
2610 | default: gcc_unreachable(); | |
2611 | } | |
2612 | } | |
2613 | [(set_attr "op_type" "RI")]) | |
2614 | ||
2615 | (define_insn "*insv<mode>_reg_extimm" | |
2616 | [(set (zero_extract:P (match_operand:P 0 "register_operand" "+d") | |
2617 | (const_int 32) | |
2618 | (match_operand 1 "const_int_operand" "n")) | |
0101708c | 2619 | (match_operand:P 2 "const_int_operand" "n"))] |
6fa05db6 AS |
2620 | "TARGET_EXTIMM |
2621 | && INTVAL (operands[1]) >= 0 | |
2622 | && INTVAL (operands[1]) < BITS_PER_WORD | |
2623 | && INTVAL (operands[1]) % 32 == 0" | |
2624 | { | |
2625 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
2626 | { | |
2627 | case 64: return "iihf\t%0,%o2"; break; | |
2628 | case 32: return "iilf\t%0,%o2"; break; | |
2629 | default: gcc_unreachable(); | |
2630 | } | |
2631 | } | |
2632 | [(set_attr "op_type" "RIL")]) | |
2633 | ||
9db1d521 HP |
2634 | ; |
2635 | ; extendsidi2 instruction pattern(s). | |
2636 | ; | |
2637 | ||
4023fb28 UW |
2638 | (define_expand "extendsidi2" |
2639 | [(set (match_operand:DI 0 "register_operand" "") | |
2640 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2641 | "" | |
4023fb28 UW |
2642 | { |
2643 | if (!TARGET_64BIT) | |
2644 | { | |
9f37ccb1 UW |
2645 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2646 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); | |
2647 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
2648 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
2649 | DONE; |
2650 | } | |
ec24698e | 2651 | }) |
4023fb28 UW |
2652 | |
2653 | (define_insn "*extendsidi2" | |
9db1d521 HP |
2654 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2655 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2656 | "TARGET_64BIT" | |
2657 | "@ | |
d40c829f UW |
2658 | lgfr\t%0,%1 |
2659 | lgf\t%0,%1" | |
d3632d41 | 2660 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2661 | |
9db1d521 | 2662 | ; |
56477c21 | 2663 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
2664 | ; |
2665 | ||
56477c21 AS |
2666 | (define_expand "extend<HQI:mode><DSI:mode>2" |
2667 | [(set (match_operand:DSI 0 "register_operand" "") | |
2668 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 2669 | "" |
4023fb28 | 2670 | { |
56477c21 | 2671 | if (<DSI:MODE>mode == DImode && !TARGET_64BIT) |
4023fb28 UW |
2672 | { |
2673 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 2674 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
2675 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
2676 | DONE; | |
2677 | } | |
ec24698e | 2678 | else if (!TARGET_EXTIMM) |
4023fb28 | 2679 | { |
56477c21 AS |
2680 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE (<DSI:MODE>mode) - |
2681 | GET_MODE_BITSIZE (<HQI:MODE>mode)); | |
2682 | ||
2683 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
2684 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
2685 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
2686 | DONE; |
2687 | } | |
ec24698e UW |
2688 | }) |
2689 | ||
56477c21 AS |
2690 | ; |
2691 | ; extendhidi2 instruction pattern(s). | |
2692 | ; | |
2693 | ||
ec24698e UW |
2694 | (define_insn "*extendhidi2_extimm" |
2695 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2696 | (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,m")))] | |
2697 | "TARGET_64BIT && TARGET_EXTIMM" | |
2698 | "@ | |
2699 | lghr\t%0,%1 | |
2700 | lgh\t%0,%1" | |
2701 | [(set_attr "op_type" "RRE,RXY")]) | |
4023fb28 UW |
2702 | |
2703 | (define_insn "*extendhidi2" | |
9db1d521 | 2704 | [(set (match_operand:DI 0 "register_operand" "=d") |
4023fb28 | 2705 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] |
9db1d521 | 2706 | "TARGET_64BIT" |
d40c829f | 2707 | "lgh\t%0,%1" |
d3632d41 | 2708 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2709 | |
9db1d521 | 2710 | ; |
56477c21 | 2711 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
2712 | ; |
2713 | ||
ec24698e UW |
2714 | (define_insn "*extendhisi2_extimm" |
2715 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
2716 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,T")))] | |
2717 | "TARGET_EXTIMM" | |
2718 | "@ | |
2719 | lhr\t%0,%1 | |
2720 | lh\t%0,%1 | |
2721 | lhy\t%0,%1" | |
2722 | [(set_attr "op_type" "RRE,RX,RXY")]) | |
9db1d521 | 2723 | |
4023fb28 | 2724 | (define_insn "*extendhisi2" |
d3632d41 UW |
2725 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
2726 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 2727 | "!TARGET_EXTIMM" |
d3632d41 | 2728 | "@ |
d40c829f UW |
2729 | lh\t%0,%1 |
2730 | lhy\t%0,%1" | |
d3632d41 | 2731 | [(set_attr "op_type" "RX,RXY")]) |
9db1d521 | 2732 | |
56477c21 AS |
2733 | ; |
2734 | ; extendqi(si|di)2 instruction pattern(s). | |
2735 | ; | |
2736 | ||
2737 | (define_insn "*extendqi<mode>2_extimm" | |
2738 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
2739 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,m")))] | |
ec24698e UW |
2740 | "TARGET_EXTIMM" |
2741 | "@ | |
56477c21 AS |
2742 | l<g>br\t%0,%1 |
2743 | l<g>b\t%0,%1" | |
ec24698e UW |
2744 | [(set_attr "op_type" "RRE,RXY")]) |
2745 | ||
56477c21 AS |
2746 | (define_insn "*extendqi<mode>2" |
2747 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
2748 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "m")))] | |
2749 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" | |
2750 | "l<g>b\t%0,%1" | |
d3632d41 UW |
2751 | [(set_attr "op_type" "RXY")]) |
2752 | ||
56477c21 AS |
2753 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
2754 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
2755 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 2756 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 2757 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
2758 | "#" |
2759 | "&& reload_completed" | |
4023fb28 | 2760 | [(parallel |
56477c21 | 2761 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 2762 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 2763 | (parallel |
56477c21 | 2764 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 2765 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
2766 | { |
2767 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2768 | set_mem_size (operands[1], GEN_INT (GET_MODE_SIZE (QImode))); | |
56477c21 AS |
2769 | operands[2] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) |
2770 | - GET_MODE_BITSIZE (QImode)); | |
6fa05db6 | 2771 | }) |
9db1d521 HP |
2772 | |
2773 | ; | |
2774 | ; extendqihi2 instruction pattern(s). | |
2775 | ; | |
2776 | ||
9db1d521 HP |
2777 | |
2778 | ; | |
2779 | ; zero_extendsidi2 instruction pattern(s). | |
2780 | ; | |
2781 | ||
4023fb28 UW |
2782 | (define_expand "zero_extendsidi2" |
2783 | [(set (match_operand:DI 0 "register_operand" "") | |
2784 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
2785 | "" | |
4023fb28 UW |
2786 | { |
2787 | if (!TARGET_64BIT) | |
2788 | { | |
9f37ccb1 UW |
2789 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
2790 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); | |
2791 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
2792 | DONE; |
2793 | } | |
ec24698e | 2794 | }) |
4023fb28 UW |
2795 | |
2796 | (define_insn "*zero_extendsidi2" | |
9db1d521 HP |
2797 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2798 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
2799 | "TARGET_64BIT" | |
2800 | "@ | |
d40c829f UW |
2801 | llgfr\t%0,%1 |
2802 | llgf\t%0,%1" | |
d3632d41 | 2803 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2804 | |
288e517f AK |
2805 | ; |
2806 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
2807 | ; | |
2808 | ||
d6083c7d UW |
2809 | (define_insn "*llgt_sidi" |
2810 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2811 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) | |
2812 | (const_int 2147483647)))] | |
2813 | "TARGET_64BIT" | |
2814 | "llgt\t%0,%1" | |
2815 | [(set_attr "op_type" "RXE")]) | |
2816 | ||
2817 | (define_insn_and_split "*llgt_sidi_split" | |
2818 | [(set (match_operand:DI 0 "register_operand" "=d") | |
2819 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) | |
2820 | (const_int 2147483647))) | |
ae156f85 | 2821 | (clobber (reg:CC CC_REGNUM))] |
d6083c7d UW |
2822 | "TARGET_64BIT" |
2823 | "#" | |
2824 | "&& reload_completed" | |
2825 | [(set (match_dup 0) | |
2826 | (and:DI (subreg:DI (match_dup 1) 0) | |
2827 | (const_int 2147483647)))] | |
2828 | "") | |
2829 | ||
288e517f AK |
2830 | (define_insn "*llgt_sisi" |
2831 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
2832 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m") | |
2833 | (const_int 2147483647)))] | |
c4d50129 | 2834 | "TARGET_ZARCH" |
288e517f AK |
2835 | "@ |
2836 | llgtr\t%0,%1 | |
2837 | llgt\t%0,%1" | |
2838 | [(set_attr "op_type" "RRE,RXE")]) | |
2839 | ||
288e517f AK |
2840 | (define_insn "*llgt_didi" |
2841 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2842 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
2843 | (const_int 2147483647)))] | |
2844 | "TARGET_64BIT" | |
2845 | "@ | |
2846 | llgtr\t%0,%1 | |
2847 | llgt\t%0,%N1" | |
2848 | [(set_attr "op_type" "RRE,RXE")]) | |
2849 | ||
f19a9af7 | 2850 | (define_split |
f6ee577c AS |
2851 | [(set (match_operand:GPR 0 "register_operand" "") |
2852 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
2853 | (const_int 2147483647))) | |
ae156f85 | 2854 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 2855 | "TARGET_ZARCH && reload_completed" |
288e517f | 2856 | [(set (match_dup 0) |
f6ee577c AS |
2857 | (and:GPR (match_dup 1) |
2858 | (const_int 2147483647)))] | |
288e517f AK |
2859 | "") |
2860 | ||
9db1d521 | 2861 | ; |
56477c21 | 2862 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
2863 | ; |
2864 | ||
56477c21 AS |
2865 | (define_expand "zero_extend<mode>di2" |
2866 | [(set (match_operand:DI 0 "register_operand" "") | |
2867 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
2868 | "" | |
2869 | { | |
2870 | if (!TARGET_64BIT) | |
2871 | { | |
2872 | rtx tmp = gen_reg_rtx (SImode); | |
2873 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
2874 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
2875 | DONE; | |
2876 | } | |
2877 | else if (!TARGET_EXTIMM) | |
2878 | { | |
2879 | rtx bitcount = GEN_INT (GET_MODE_BITSIZE(DImode) - | |
2880 | GET_MODE_BITSIZE(<MODE>mode)); | |
2881 | operands[1] = gen_lowpart (DImode, operands[1]); | |
2882 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
2883 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
2884 | DONE; | |
2885 | } | |
2886 | }) | |
2887 | ||
f6ee577c | 2888 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 2889 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 2890 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 2891 | "" |
4023fb28 | 2892 | { |
ec24698e UW |
2893 | if (!TARGET_EXTIMM) |
2894 | { | |
2895 | operands[1] = gen_lowpart (SImode, operands[1]); | |
2896 | emit_insn (gen_andsi3 (operands[0], operands[1], | |
2897 | GEN_INT ((1 << GET_MODE_BITSIZE(<MODE>mode)) - 1))); | |
2898 | DONE; | |
56477c21 | 2899 | } |
ec24698e UW |
2900 | }) |
2901 | ||
56477c21 AS |
2902 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
2903 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
2904 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,m")))] | |
ec24698e UW |
2905 | "TARGET_EXTIMM" |
2906 | "@ | |
56477c21 AS |
2907 | ll<g><hc>r\t%0,%1 |
2908 | ll<g><hc>\t%0,%1" | |
ec24698e | 2909 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 2910 | |
56477c21 AS |
2911 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
2912 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
2913 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "m")))] | |
ec24698e | 2914 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 2915 | "llg<hc>\t%0,%1" |
d3632d41 | 2916 | [(set_attr "op_type" "RXY")]) |
cc7ab9b7 UW |
2917 | |
2918 | (define_insn_and_split "*zero_extendhisi2_31" | |
2919 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 2920 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
ae156f85 | 2921 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 2922 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2923 | "#" |
2924 | "&& reload_completed" | |
2925 | [(set (match_dup 0) (const_int 0)) | |
2926 | (parallel | |
2927 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 2928 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 2929 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 2930 | |
cc7ab9b7 UW |
2931 | (define_insn_and_split "*zero_extendqisi2_31" |
2932 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
2933 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2934 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2935 | "#" |
2936 | "&& reload_completed" | |
2937 | [(set (match_dup 0) (const_int 0)) | |
2938 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 2939 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 2940 | |
9db1d521 HP |
2941 | ; |
2942 | ; zero_extendqihi2 instruction pattern(s). | |
2943 | ; | |
2944 | ||
9db1d521 HP |
2945 | (define_expand "zero_extendqihi2" |
2946 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 2947 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 2948 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 2949 | { |
4023fb28 UW |
2950 | operands[1] = gen_lowpart (HImode, operands[1]); |
2951 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
2952 | DONE; | |
ec24698e | 2953 | }) |
9db1d521 | 2954 | |
4023fb28 | 2955 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 2956 | [(set (match_operand:HI 0 "register_operand" "=d") |
cc7ab9b7 | 2957 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] |
ec24698e | 2958 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 2959 | "llgc\t%0,%1" |
d3632d41 | 2960 | [(set_attr "op_type" "RXY")]) |
9db1d521 | 2961 | |
cc7ab9b7 UW |
2962 | (define_insn_and_split "*zero_extendqihi2_31" |
2963 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
2964 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] | |
9e8327e3 | 2965 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
2966 | "#" |
2967 | "&& reload_completed" | |
2968 | [(set (match_dup 0) (const_int 0)) | |
2969 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 2970 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 UW |
2971 | |
2972 | ||
9db1d521 | 2973 | ; |
2f8f8434 | 2974 | ; fixuns_trunc(sf|df)(si|di)2 and fix_trunc(sf|df)(si|di)2 instruction pattern(s). |
9db1d521 HP |
2975 | ; |
2976 | ||
2f8f8434 AS |
2977 | (define_expand "fixuns_trunc<FPR:mode><GPR:mode>2" |
2978 | [(set (match_operand:GPR 0 "register_operand" "") | |
2979 | (unsigned_fix:GPR (match_operand:FPR 1 "register_operand" "")))] | |
2980 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
9db1d521 HP |
2981 | { |
2982 | rtx label1 = gen_label_rtx (); | |
2983 | rtx label2 = gen_label_rtx (); | |
2f8f8434 AS |
2984 | rtx temp = gen_reg_rtx (<FPR:MODE>mode); |
2985 | REAL_VALUE_TYPE cmp, sub; | |
2986 | ||
2987 | operands[1] = force_reg (<FPR:MODE>mode, operands[1]); | |
2988 | real_2expN (&cmp, GET_MODE_BITSIZE(<GPR:MODE>mode) - 1); | |
2989 | real_2expN (&sub, GET_MODE_BITSIZE(<GPR:MODE>mode)); | |
2990 | ||
2991 | emit_insn (gen_cmp<FPR:mode> (operands[1], | |
2992 | CONST_DOUBLE_FROM_REAL_VALUE (cmp, <FPR:MODE>mode))); | |
9db1d521 | 2993 | emit_jump_insn (gen_blt (label1)); |
2f8f8434 AS |
2994 | emit_insn (gen_sub<FPR:mode>3 (temp, operands[1], |
2995 | CONST_DOUBLE_FROM_REAL_VALUE (sub, <FPR:MODE>mode))); | |
2996 | emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], temp, | |
2997 | GEN_INT(7))); | |
f314b9b1 | 2998 | emit_jump (label2); |
9db1d521 HP |
2999 | |
3000 | emit_label (label1); | |
2f8f8434 AS |
3001 | emit_insn (gen_fix_trunc<FPR:mode><GPR:mode>2_ieee (operands[0], |
3002 | operands[1], GEN_INT(5))); | |
9db1d521 HP |
3003 | emit_label (label2); |
3004 | DONE; | |
10bbf137 | 3005 | }) |
9db1d521 | 3006 | |
2f8f8434 | 3007 | (define_expand "fix_trunc<FPR:mode>di2" |
9db1d521 | 3008 | [(set (match_operand:DI 0 "register_operand" "") |
2f8f8434 | 3009 | (fix:DI (match_operand:FPR 1 "nonimmediate_operand" "")))] |
9db1d521 | 3010 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
9db1d521 | 3011 | { |
2f8f8434 AS |
3012 | operands[1] = force_reg (<FPR:MODE>mode, operands[1]); |
3013 | emit_insn (gen_fix_trunc<FPR:mode>di2_ieee (operands[0], operands[1], | |
3014 | GEN_INT(5))); | |
9db1d521 | 3015 | DONE; |
10bbf137 | 3016 | }) |
9db1d521 | 3017 | |
2f8f8434 AS |
3018 | (define_insn "fix_trunc<FPR:mode><GPR:mode>2_ieee" |
3019 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3020 | (fix:GPR (match_operand:FPR 1 "register_operand" "f"))) | |
3021 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
ae156f85 | 3022 | (clobber (reg:CC CC_REGNUM))] |
2f8f8434 AS |
3023 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3024 | "c<GPR:gf><FPR:de>br\t%0,%h2,%1" | |
9db1d521 | 3025 | [(set_attr "op_type" "RRE") |
077dab3b | 3026 | (set_attr "type" "ftoi")]) |
9db1d521 HP |
3027 | |
3028 | ; | |
2f8f8434 | 3029 | ; fix_truncdfsi2 instruction pattern(s). |
9db1d521 HP |
3030 | ; |
3031 | ||
9db1d521 HP |
3032 | (define_expand "fix_truncdfsi2" |
3033 | [(set (match_operand:SI 0 "register_operand" "") | |
3034 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
3035 | "TARGET_HARD_FLOAT" | |
9db1d521 | 3036 | { |
c7453384 | 3037 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
3038 | { |
3039 | /* This is the algorithm from POP chapter A.5.7.2. */ | |
3040 | ||
c19ec8f9 | 3041 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
4023fb28 UW |
3042 | rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000); |
3043 | rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000); | |
9db1d521 HP |
3044 | |
3045 | operands[1] = force_reg (DFmode, operands[1]); | |
c7453384 | 3046 | emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1], |
9db1d521 | 3047 | two31r, two32, temp)); |
c7453384 EC |
3048 | } |
3049 | else | |
9db1d521 HP |
3050 | { |
3051 | operands[1] = force_reg (DFmode, operands[1]); | |
3052 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
3053 | } | |
3054 | ||
3055 | DONE; | |
10bbf137 | 3056 | }) |
9db1d521 | 3057 | |
9db1d521 HP |
3058 | (define_insn "fix_truncdfsi2_ibm" |
3059 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3060 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f"))) | |
4023fb28 UW |
3061 | (use (match_operand:DI 2 "immediate_operand" "m")) |
3062 | (use (match_operand:DI 3 "immediate_operand" "m")) | |
9db1d521 | 3063 | (use (match_operand:BLK 4 "memory_operand" "m")) |
ae156f85 | 3064 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3065 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
9db1d521 | 3066 | { |
d40c829f UW |
3067 | output_asm_insn ("sd\t%1,%2", operands); |
3068 | output_asm_insn ("aw\t%1,%3", operands); | |
3069 | output_asm_insn ("std\t%1,%4", operands); | |
3070 | output_asm_insn ("xi\t%N4,128", operands); | |
3071 | return "l\t%0,%N4"; | |
10bbf137 | 3072 | } |
b628bd8e | 3073 | [(set_attr "length" "20")]) |
9db1d521 HP |
3074 | |
3075 | ; | |
2f8f8434 | 3076 | ; fix_truncsfsi2 instruction pattern(s). |
9db1d521 HP |
3077 | ; |
3078 | ||
9db1d521 HP |
3079 | (define_expand "fix_truncsfsi2" |
3080 | [(set (match_operand:SI 0 "register_operand" "") | |
3081 | (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
3082 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
3083 | { |
3084 | if (TARGET_IBM_FLOAT) | |
3085 | { | |
3086 | /* Convert to DFmode and then use the POP algorithm. */ | |
3087 | rtx temp = gen_reg_rtx (DFmode); | |
3088 | emit_insn (gen_extendsfdf2 (temp, operands[1])); | |
3089 | emit_insn (gen_fix_truncdfsi2 (operands[0], temp)); | |
3090 | } | |
3091 | else | |
3092 | { | |
3093 | operands[1] = force_reg (SFmode, operands[1]); | |
3094 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
3095 | } | |
3096 | ||
3097 | DONE; | |
10bbf137 | 3098 | }) |
9db1d521 | 3099 | |
9db1d521 | 3100 | ; |
f5905b37 | 3101 | ; floatdi(df|sf)2 instruction pattern(s). |
9db1d521 HP |
3102 | ; |
3103 | ||
f5905b37 AS |
3104 | (define_insn "floatdi<mode>2" |
3105 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
3106 | (float:FPR (match_operand:DI 1 "register_operand" "d")))] | |
9db1d521 | 3107 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 3108 | "c<de>gbr\t%0,%1" |
9db1d521 | 3109 | [(set_attr "op_type" "RRE") |
077dab3b | 3110 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3111 | |
3112 | ; | |
3113 | ; floatsidf2 instruction pattern(s). | |
3114 | ; | |
3115 | ||
3116 | (define_expand "floatsidf2" | |
a036c6f7 UW |
3117 | [(set (match_operand:DF 0 "register_operand" "") |
3118 | (float:DF (match_operand:SI 1 "register_operand" "")))] | |
9db1d521 | 3119 | "TARGET_HARD_FLOAT" |
9db1d521 | 3120 | { |
c7453384 | 3121 | if (TARGET_IBM_FLOAT) |
9db1d521 HP |
3122 | { |
3123 | /* This is the algorithm from POP chapter A.5.7.1. */ | |
3124 | ||
c19ec8f9 | 3125 | rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD); |
c7453384 | 3126 | rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000); |
9db1d521 HP |
3127 | |
3128 | emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp)); | |
3129 | DONE; | |
3130 | } | |
10bbf137 | 3131 | }) |
9db1d521 HP |
3132 | |
3133 | (define_insn "floatsidf2_ieee" | |
3134 | [(set (match_operand:DF 0 "register_operand" "=f") | |
a036c6f7 | 3135 | (float:DF (match_operand:SI 1 "register_operand" "d")))] |
9db1d521 | 3136 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3137 | "cdfbr\t%0,%1" |
9db1d521 | 3138 | [(set_attr "op_type" "RRE") |
077dab3b | 3139 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3140 | |
3141 | (define_insn "floatsidf2_ibm" | |
3142 | [(set (match_operand:DF 0 "register_operand" "=f") | |
3143 | (float:DF (match_operand:SI 1 "register_operand" "d"))) | |
4023fb28 | 3144 | (use (match_operand:DI 2 "immediate_operand" "m")) |
9db1d521 | 3145 | (use (match_operand:BLK 3 "memory_operand" "m")) |
ae156f85 | 3146 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3147 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
9db1d521 | 3148 | { |
d40c829f UW |
3149 | output_asm_insn ("st\t%1,%N3", operands); |
3150 | output_asm_insn ("xi\t%N3,128", operands); | |
3151 | output_asm_insn ("mvc\t%O3(4,%R3),%2", operands); | |
3152 | output_asm_insn ("ld\t%0,%3", operands); | |
3153 | return "sd\t%0,%2"; | |
10bbf137 | 3154 | } |
b628bd8e | 3155 | [(set_attr "length" "20")]) |
9db1d521 HP |
3156 | |
3157 | ; | |
3158 | ; floatsisf2 instruction pattern(s). | |
3159 | ; | |
3160 | ||
3161 | (define_expand "floatsisf2" | |
a036c6f7 UW |
3162 | [(set (match_operand:SF 0 "register_operand" "") |
3163 | (float:SF (match_operand:SI 1 "register_operand" "")))] | |
9db1d521 | 3164 | "TARGET_HARD_FLOAT" |
9db1d521 HP |
3165 | { |
3166 | if (TARGET_IBM_FLOAT) | |
3167 | { | |
3168 | /* Use the POP algorithm to convert to DFmode and then truncate. */ | |
3169 | rtx temp = gen_reg_rtx (DFmode); | |
3170 | emit_insn (gen_floatsidf2 (temp, operands[1])); | |
3171 | emit_insn (gen_truncdfsf2 (operands[0], temp)); | |
3172 | DONE; | |
3173 | } | |
10bbf137 | 3174 | }) |
9db1d521 HP |
3175 | |
3176 | (define_insn "floatsisf2_ieee" | |
3177 | [(set (match_operand:SF 0 "register_operand" "=f") | |
a036c6f7 | 3178 | (float:SF (match_operand:SI 1 "register_operand" "d")))] |
9db1d521 | 3179 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3180 | "cefbr\t%0,%1" |
9db1d521 | 3181 | [(set_attr "op_type" "RRE") |
077dab3b | 3182 | (set_attr "type" "itof" )]) |
9db1d521 HP |
3183 | |
3184 | ; | |
3185 | ; truncdfsf2 instruction pattern(s). | |
3186 | ; | |
3187 | ||
3188 | (define_expand "truncdfsf2" | |
3189 | [(set (match_operand:SF 0 "register_operand" "") | |
a036c6f7 | 3190 | (float_truncate:SF (match_operand:DF 1 "register_operand" "")))] |
9db1d521 | 3191 | "TARGET_HARD_FLOAT" |
4023fb28 | 3192 | "") |
9db1d521 HP |
3193 | |
3194 | (define_insn "truncdfsf2_ieee" | |
3195 | [(set (match_operand:SF 0 "register_operand" "=f") | |
a036c6f7 | 3196 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))] |
9db1d521 | 3197 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
d40c829f | 3198 | "ledbr\t%0,%1" |
ce50cae8 | 3199 | [(set_attr "op_type" "RRE")]) |
9db1d521 HP |
3200 | |
3201 | (define_insn "truncdfsf2_ibm" | |
3202 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
a036c6f7 | 3203 | (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))] |
9db1d521 HP |
3204 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
3205 | "@ | |
a036c6f7 | 3206 | ler\t%0,%1 |
d40c829f | 3207 | le\t%0,%1" |
4023fb28 | 3208 | [(set_attr "op_type" "RR,RX") |
cfdb984b | 3209 | (set_attr "type" "floadsf")]) |
9db1d521 HP |
3210 | |
3211 | ; | |
3212 | ; extendsfdf2 instruction pattern(s). | |
3213 | ; | |
3214 | ||
3215 | (define_expand "extendsfdf2" | |
3216 | [(set (match_operand:DF 0 "register_operand" "") | |
3217 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] | |
3218 | "TARGET_HARD_FLOAT" | |
9db1d521 HP |
3219 | { |
3220 | if (TARGET_IBM_FLOAT) | |
3221 | { | |
3222 | emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1])); | |
3223 | DONE; | |
3224 | } | |
10bbf137 | 3225 | }) |
9db1d521 HP |
3226 | |
3227 | (define_insn "extendsfdf2_ieee" | |
3228 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 3229 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))] |
9db1d521 HP |
3230 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3231 | "@ | |
d40c829f UW |
3232 | ldebr\t%0,%1 |
3233 | ldeb\t%0,%1" | |
077dab3b | 3234 | [(set_attr "op_type" "RRE,RXE") |
cfdb984b | 3235 | (set_attr "type" "floadsf")]) |
9db1d521 HP |
3236 | |
3237 | (define_insn "extendsfdf2_ibm" | |
3238 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
d3632d41 | 3239 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R"))) |
ae156f85 | 3240 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3241 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
3242 | "@ | |
d40c829f UW |
3243 | sdr\t%0,%0\;ler\t%0,%1 |
3244 | sdr\t%0,%0\;le\t%0,%1" | |
b628bd8e | 3245 | [(set_attr "length" "4,6") |
cfdb984b | 3246 | (set_attr "type" "floadsf")]) |
9db1d521 HP |
3247 | |
3248 | ||
3249 | ;; | |
fae778eb | 3250 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 3251 | ;; |
fae778eb | 3252 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
3253 | ; because of unpredictable Bits in Register for Halfword and Byte |
3254 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
3255 | ||
07893d4f UW |
3256 | ;; |
3257 | ;;- Add instructions. | |
3258 | ;; | |
3259 | ||
1c7b1b7e UW |
3260 | ; |
3261 | ; addti3 instruction pattern(s). | |
3262 | ; | |
3263 | ||
3264 | (define_insn_and_split "addti3" | |
3265 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
3266 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") | |
3267 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 3268 | (clobber (reg:CC CC_REGNUM))] |
1c7b1b7e UW |
3269 | "TARGET_64BIT" |
3270 | "#" | |
3271 | "&& reload_completed" | |
3272 | [(parallel | |
ae156f85 | 3273 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
3274 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
3275 | (match_dup 7))) | |
3276 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
3277 | (parallel | |
3278 | [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
3279 | (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)))) |
3280 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
3281 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
3282 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
3283 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
3284 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
3285 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 3286 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 3287 | |
07893d4f UW |
3288 | ; |
3289 | ; adddi3 instruction pattern(s). | |
3290 | ; | |
3291 | ||
07893d4f UW |
3292 | (define_insn "*adddi3_sign" |
3293 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3294 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3295 | (match_operand:DI 1 "register_operand" "0,0"))) | |
ae156f85 | 3296 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
3297 | "TARGET_64BIT" |
3298 | "@ | |
d40c829f UW |
3299 | agfr\t%0,%2 |
3300 | agf\t%0,%2" | |
d3632d41 | 3301 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3302 | |
3303 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 3304 | [(set (reg CC_REGNUM) |
07893d4f UW |
3305 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3306 | (match_operand:DI 1 "register_operand" "0,0")) | |
3307 | (const_int 0))) | |
3308 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3309 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
3310 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3311 | "@ | |
d40c829f UW |
3312 | algfr\t%0,%2 |
3313 | algf\t%0,%2" | |
d3632d41 | 3314 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3315 | |
3316 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 3317 | [(set (reg CC_REGNUM) |
07893d4f UW |
3318 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) |
3319 | (match_operand:DI 1 "register_operand" "0,0")) | |
3320 | (const_int 0))) | |
3321 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3322 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3323 | "@ | |
d40c829f UW |
3324 | algfr\t%0,%2 |
3325 | algf\t%0,%2" | |
d3632d41 | 3326 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3327 | |
3328 | (define_insn "*adddi3_zero" | |
3329 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3330 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")) | |
3331 | (match_operand:DI 1 "register_operand" "0,0"))) | |
ae156f85 | 3332 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
3333 | "TARGET_64BIT" |
3334 | "@ | |
d40c829f UW |
3335 | algfr\t%0,%2 |
3336 | algf\t%0,%2" | |
d3632d41 | 3337 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3338 | |
0a3bdf9d | 3339 | (define_insn "*adddi3_imm_cc" |
ae156f85 | 3340 | [(set (reg CC_REGNUM) |
ec24698e UW |
3341 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0") |
3342 | (match_operand:DI 2 "const_int_operand" "K,Os")) | |
0a3bdf9d | 3343 | (const_int 0))) |
ec24698e | 3344 | (set (match_operand:DI 0 "register_operand" "=d,d") |
0a3bdf9d | 3345 | (plus:DI (match_dup 1) (match_dup 2)))] |
c7453384 EC |
3346 | "TARGET_64BIT |
3347 | && s390_match_ccmode (insn, CCAmode) | |
ec24698e UW |
3348 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") |
3349 | || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\"))" | |
3350 | "@ | |
3351 | aghi\t%0,%h2 | |
3352 | agfi\t%0,%2" | |
3353 | [(set_attr "op_type" "RI,RIL")]) | |
0a3bdf9d | 3354 | |
b2ba71ca | 3355 | (define_insn "*adddi3_carry1_cc" |
ae156f85 | 3356 | [(set (reg CC_REGNUM) |
ec24698e UW |
3357 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") |
3358 | (match_operand:DI 2 "general_operand" "d,Op,On,m")) | |
b2ba71ca | 3359 | (match_dup 1))) |
ec24698e | 3360 | (set (match_operand:DI 0 "register_operand" "=d,d,d,d") |
b2ba71ca UW |
3361 | (plus:DI (match_dup 1) (match_dup 2)))] |
3362 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3363 | "@ | |
3364 | algr\t%0,%2 | |
ec24698e UW |
3365 | algfi\t%0,%2 |
3366 | slgfi\t%0,%n2 | |
b2ba71ca | 3367 | alg\t%0,%2" |
ec24698e | 3368 | [(set_attr "op_type" "RRE,RIL,RIL,RXY")]) |
b2ba71ca UW |
3369 | |
3370 | (define_insn "*adddi3_carry1_cconly" | |
ae156f85 | 3371 | [(set (reg CC_REGNUM) |
b2ba71ca UW |
3372 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
3373 | (match_operand:DI 2 "general_operand" "d,m")) | |
3374 | (match_dup 1))) | |
3375 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3376 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3377 | "@ | |
3378 | algr\t%0,%2 | |
3379 | alg\t%0,%2" | |
3380 | [(set_attr "op_type" "RRE,RXY")]) | |
3381 | ||
3382 | (define_insn "*adddi3_carry2_cc" | |
ae156f85 | 3383 | [(set (reg CC_REGNUM) |
ec24698e UW |
3384 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") |
3385 | (match_operand:DI 2 "general_operand" "d,Op,On,m")) | |
b2ba71ca | 3386 | (match_dup 2))) |
ec24698e | 3387 | (set (match_operand:DI 0 "register_operand" "=d,d,d,d") |
b2ba71ca UW |
3388 | (plus:DI (match_dup 1) (match_dup 2)))] |
3389 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3390 | "@ | |
3391 | algr\t%0,%2 | |
ec24698e UW |
3392 | algfi\t%0,%2 |
3393 | slgfi\t%0,%n2 | |
b2ba71ca | 3394 | alg\t%0,%2" |
ec24698e | 3395 | [(set_attr "op_type" "RRE,RIL,RIL,RXY")]) |
b2ba71ca UW |
3396 | |
3397 | (define_insn "*adddi3_carry2_cconly" | |
ae156f85 | 3398 | [(set (reg CC_REGNUM) |
b2ba71ca UW |
3399 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
3400 | (match_operand:DI 2 "general_operand" "d,m")) | |
3401 | (match_dup 2))) | |
3402 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3403 | "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT" | |
3404 | "@ | |
3405 | algr\t%0,%2 | |
3406 | alg\t%0,%2" | |
3407 | [(set_attr "op_type" "RRE,RXY")]) | |
3408 | ||
07893d4f | 3409 | (define_insn "*adddi3_cc" |
ae156f85 | 3410 | [(set (reg CC_REGNUM) |
ec24698e UW |
3411 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") |
3412 | (match_operand:DI 2 "general_operand" "d,Op,On,m")) | |
07893d4f | 3413 | (const_int 0))) |
ec24698e | 3414 | (set (match_operand:DI 0 "register_operand" "=d,d,d,d") |
07893d4f UW |
3415 | (plus:DI (match_dup 1) (match_dup 2)))] |
3416 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3417 | "@ | |
d40c829f | 3418 | algr\t%0,%2 |
ec24698e UW |
3419 | algfi\t%0,%2 |
3420 | slgfi\t%0,%n2 | |
d40c829f | 3421 | alg\t%0,%2" |
ec24698e | 3422 | [(set_attr "op_type" "RRE,RIL,RIL,RXY")]) |
9db1d521 | 3423 | |
07893d4f | 3424 | (define_insn "*adddi3_cconly" |
ae156f85 | 3425 | [(set (reg CC_REGNUM) |
96fd3851 | 3426 | (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3427 | (match_operand:DI 2 "general_operand" "d,m")) |
3428 | (const_int 0))) | |
3429 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3430 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3431 | "@ | |
d40c829f UW |
3432 | algr\t%0,%2 |
3433 | alg\t%0,%2" | |
d3632d41 | 3434 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3435 | |
07893d4f | 3436 | (define_insn "*adddi3_cconly2" |
ae156f85 | 3437 | [(set (reg CC_REGNUM) |
96fd3851 | 3438 | (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
07893d4f UW |
3439 | (neg:SI (match_operand:DI 2 "general_operand" "d,m")))) |
3440 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3441 | "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT" | |
9db1d521 | 3442 | "@ |
d40c829f UW |
3443 | algr\t%0,%2 |
3444 | alg\t%0,%2" | |
d3632d41 | 3445 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 3446 | |
07893d4f | 3447 | (define_insn "*adddi3_64" |
ec24698e UW |
3448 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d") |
3449 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
3450 | (match_operand:DI 2 "general_operand" "d,K,Op,On,m") ) ) | |
ae156f85 | 3451 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3452 | "TARGET_64BIT" |
3453 | "@ | |
d40c829f UW |
3454 | agr\t%0,%2 |
3455 | aghi\t%0,%h2 | |
ec24698e UW |
3456 | algfi\t%0,%2 |
3457 | slgfi\t%0,%n2 | |
d40c829f | 3458 | ag\t%0,%2" |
ec24698e | 3459 | [(set_attr "op_type" "RRE,RI,RIL,RIL,RXY")]) |
9db1d521 | 3460 | |
e69166de UW |
3461 | (define_insn_and_split "*adddi3_31z" |
3462 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3463 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") | |
3464 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 3465 | (clobber (reg:CC CC_REGNUM))] |
e69166de UW |
3466 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
3467 | "#" | |
3468 | "&& reload_completed" | |
3469 | [(parallel | |
ae156f85 | 3470 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
3471 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
3472 | (match_dup 7))) | |
3473 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3474 | (parallel | |
3475 | [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
3476 | (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)))) |
3477 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
3478 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3479 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3480 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3481 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3482 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 3483 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 3484 | |
07893d4f UW |
3485 | (define_insn_and_split "*adddi3_31" |
3486 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
96fd3851 | 3487 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 3488 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 3489 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 3490 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
3491 | "#" |
3492 | "&& reload_completed" | |
3493 | [(parallel | |
3494 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 3495 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 3496 | (parallel |
ae156f85 | 3497 | [(set (reg:CCL1 CC_REGNUM) |
07893d4f UW |
3498 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
3499 | (match_dup 7))) | |
3500 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
3501 | (set (pc) | |
ae156f85 | 3502 | (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) |
07893d4f UW |
3503 | (pc) |
3504 | (label_ref (match_dup 9)))) | |
3505 | (parallel | |
3506 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
ae156f85 | 3507 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 3508 | (match_dup 9)] |
97c6f7ad UW |
3509 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3510 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3511 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3512 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3513 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3514 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 3515 | operands[9] = gen_label_rtx ();") |
9db1d521 HP |
3516 | |
3517 | (define_expand "adddi3" | |
07893d4f UW |
3518 | [(parallel |
3519 | [(set (match_operand:DI 0 "register_operand" "") | |
96fd3851 | 3520 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
07893d4f | 3521 | (match_operand:DI 2 "general_operand" ""))) |
ae156f85 | 3522 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 3523 | "" |
07893d4f | 3524 | "") |
9db1d521 | 3525 | |
9db1d521 HP |
3526 | ; |
3527 | ; addsi3 instruction pattern(s). | |
3528 | ; | |
9db1d521 | 3529 | |
0a3bdf9d | 3530 | (define_insn "*addsi3_imm_cc" |
ae156f85 | 3531 | [(set (reg CC_REGNUM) |
ec24698e UW |
3532 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0") |
3533 | (match_operand:SI 2 "const_int_operand" "K,Os")) | |
0a3bdf9d | 3534 | (const_int 0))) |
ec24698e | 3535 | (set (match_operand:SI 0 "register_operand" "=d,d") |
0a3bdf9d UW |
3536 | (plus:SI (match_dup 1) (match_dup 2)))] |
3537 | "s390_match_ccmode (insn, CCAmode) | |
ec24698e UW |
3538 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") |
3539 | || CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\")) | |
3540 | && INTVAL (operands[2]) != -((HOST_WIDE_INT)1 << 31)" | |
3541 | "@ | |
3542 | ahi\t%0,%h2 | |
3543 | afi\t%0,%2" | |
3544 | [(set_attr "op_type" "RI,RIL")]) | |
0a3bdf9d | 3545 | |
07893d4f | 3546 | (define_insn "*addsi3_carry1_cc" |
ae156f85 | 3547 | [(set (reg CC_REGNUM) |
ec24698e UW |
3548 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
3549 | (match_operand:SI 2 "general_operand" "d,Os,R,T")) | |
07893d4f | 3550 | (match_dup 1))) |
ec24698e | 3551 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
07893d4f | 3552 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3553 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3554 | "@ |
d40c829f | 3555 | alr\t%0,%2 |
ec24698e | 3556 | alfi\t%0,%o2 |
d40c829f UW |
3557 | al\t%0,%2 |
3558 | aly\t%0,%2" | |
ec24698e | 3559 | [(set_attr "op_type" "RR,RIL,RX,RXY")]) |
07893d4f UW |
3560 | |
3561 | (define_insn "*addsi3_carry1_cconly" | |
ae156f85 | 3562 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3563 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3564 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3565 | (match_dup 1))) |
d3632d41 | 3566 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3567 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3568 | "@ |
d40c829f UW |
3569 | alr\t%0,%2 |
3570 | al\t%0,%2 | |
3571 | aly\t%0,%2" | |
d3632d41 | 3572 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3573 | |
3574 | (define_insn "*addsi3_carry2_cc" | |
ae156f85 | 3575 | [(set (reg CC_REGNUM) |
ec24698e UW |
3576 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
3577 | (match_operand:SI 2 "general_operand" "d,Os,R,T")) | |
07893d4f | 3578 | (match_dup 2))) |
ec24698e | 3579 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
07893d4f | 3580 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3581 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3582 | "@ |
d40c829f | 3583 | alr\t%0,%2 |
ec24698e | 3584 | alfi\t%0,%o2 |
d40c829f UW |
3585 | al\t%0,%2 |
3586 | aly\t%0,%2" | |
ec24698e | 3587 | [(set_attr "op_type" "RR,RIL,RX,RXY")]) |
07893d4f UW |
3588 | |
3589 | (define_insn "*addsi3_carry2_cconly" | |
ae156f85 | 3590 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3591 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3592 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3593 | (match_dup 2))) |
d3632d41 | 3594 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3595 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 3596 | "@ |
d40c829f UW |
3597 | alr\t%0,%2 |
3598 | al\t%0,%2 | |
3599 | aly\t%0,%2" | |
d3632d41 | 3600 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f | 3601 | |
9db1d521 | 3602 | (define_insn "*addsi3_cc" |
ae156f85 | 3603 | [(set (reg CC_REGNUM) |
ec24698e UW |
3604 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
3605 | (match_operand:SI 2 "general_operand" "d,Os,R,T")) | |
9db1d521 | 3606 | (const_int 0))) |
ec24698e | 3607 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
9db1d521 | 3608 | (plus:SI (match_dup 1) (match_dup 2)))] |
c7453384 | 3609 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3610 | "@ |
d40c829f | 3611 | alr\t%0,%2 |
ec24698e | 3612 | alfi\t%0,%o2 |
d40c829f UW |
3613 | al\t%0,%2 |
3614 | aly\t%0,%2" | |
ec24698e | 3615 | [(set_attr "op_type" "RR,RIL,RX,RXY")]) |
9db1d521 HP |
3616 | |
3617 | (define_insn "*addsi3_cconly" | |
ae156f85 | 3618 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3619 | (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3620 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3621 | (const_int 0))) |
d3632d41 | 3622 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
c7453384 | 3623 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3624 | "@ |
d40c829f UW |
3625 | alr\t%0,%2 |
3626 | al\t%0,%2 | |
3627 | aly\t%0,%2" | |
d3632d41 | 3628 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 HP |
3629 | |
3630 | (define_insn "*addsi3_cconly2" | |
ae156f85 | 3631 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3632 | (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0") |
3633 | (neg:SI (match_operand:SI 2 "general_operand" "d,R,T")))) | |
3634 | (clobber (match_scratch:SI 0 "=d,d,d"))] | |
b2ba71ca | 3635 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 3636 | "@ |
d40c829f UW |
3637 | alr\t%0,%2 |
3638 | al\t%0,%2 | |
3639 | aly\t%0,%2" | |
d3632d41 | 3640 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 3641 | |
07893d4f | 3642 | (define_insn "*addsi3_sign" |
d3632d41 | 3643 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
f0ad121f UW |
3644 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) |
3645 | (match_operand:SI 1 "register_operand" "0,0"))) | |
ae156f85 | 3646 | (clobber (reg:CC CC_REGNUM))] |
07893d4f | 3647 | "" |
d3632d41 | 3648 | "@ |
d40c829f UW |
3649 | ah\t%0,%2 |
3650 | ahy\t%0,%2" | |
d3632d41 | 3651 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f | 3652 | |
9db1d521 | 3653 | (define_insn "addsi3" |
ec24698e UW |
3654 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
3655 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
3656 | (match_operand:SI 2 "general_operand" "d,K,Os,R,T"))) | |
ae156f85 | 3657 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3658 | "" |
3659 | "@ | |
d40c829f UW |
3660 | ar\t%0,%2 |
3661 | ahi\t%0,%h2 | |
ec24698e | 3662 | afi\t%0,%2 |
d40c829f UW |
3663 | a\t%0,%2 |
3664 | ay\t%0,%2" | |
ec24698e | 3665 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY")]) |
9db1d521 | 3666 | |
9db1d521 | 3667 | ; |
f5905b37 | 3668 | ; add(df|sf)3 instruction pattern(s). |
9db1d521 HP |
3669 | ; |
3670 | ||
f5905b37 | 3671 | (define_expand "add<mode>3" |
9db1d521 | 3672 | [(parallel |
f5905b37 AS |
3673 | [(set (match_operand:FPR 0 "register_operand" "=f,f") |
3674 | (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
3675 | (match_operand:FPR 2 "general_operand" "f,R"))) | |
ae156f85 | 3676 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
3677 | "TARGET_HARD_FLOAT" |
3678 | "") | |
3679 | ||
f5905b37 AS |
3680 | (define_insn "*add<mode>3" |
3681 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
3682 | (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
3683 | (match_operand:FPR 2 "general_operand" "f,R"))) | |
ae156f85 | 3684 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3685 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3686 | "@ | |
f5905b37 AS |
3687 | a<de>br\t%0,%2 |
3688 | a<de>b\t%0,%2" | |
ce50cae8 | 3689 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 3690 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 3691 | |
f5905b37 | 3692 | (define_insn "*add<mode>3_cc" |
ae156f85 | 3693 | [(set (reg CC_REGNUM) |
f5905b37 AS |
3694 | (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") |
3695 | (match_operand:FPR 2 "general_operand" "f,R")) | |
3696 | (match_operand:FPR 3 "const0_operand" ""))) | |
3697 | (set (match_operand:FPR 0 "register_operand" "=f,f") | |
3698 | (plus:FPR (match_dup 1) (match_dup 2)))] | |
3ef093a8 AK |
3699 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3700 | "@ | |
f5905b37 AS |
3701 | a<de>br\t%0,%2 |
3702 | a<de>b\t%0,%2" | |
3ef093a8 | 3703 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 3704 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 3705 | |
f5905b37 | 3706 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 3707 | [(set (reg CC_REGNUM) |
f5905b37 AS |
3708 | (compare (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") |
3709 | (match_operand:FPR 2 "general_operand" "f,R")) | |
3710 | (match_operand:FPR 3 "const0_operand" ""))) | |
3711 | (clobber (match_scratch:FPR 0 "=f,f"))] | |
3ef093a8 AK |
3712 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
3713 | "@ | |
f5905b37 AS |
3714 | a<de>br\t%0,%2 |
3715 | a<de>b\t%0,%2" | |
3ef093a8 | 3716 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 3717 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 3718 | |
f5905b37 AS |
3719 | (define_insn "*add<mode>3_ibm" |
3720 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
3721 | (plus:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
3722 | (match_operand:FPR 2 "general_operand" "f,R"))) | |
ae156f85 | 3723 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3724 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
3725 | "@ | |
f5905b37 AS |
3726 | a<de>r\t%0,%2 |
3727 | a<de>\t%0,%2" | |
9db1d521 | 3728 | [(set_attr "op_type" "RR,RX") |
f5905b37 | 3729 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 HP |
3730 | |
3731 | ||
3732 | ;; | |
3733 | ;;- Subtract instructions. | |
3734 | ;; | |
3735 | ||
1c7b1b7e UW |
3736 | ; |
3737 | ; subti3 instruction pattern(s). | |
3738 | ; | |
3739 | ||
3740 | (define_insn_and_split "subti3" | |
3741 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
3742 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
3743 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 3744 | (clobber (reg:CC CC_REGNUM))] |
1c7b1b7e UW |
3745 | "TARGET_64BIT" |
3746 | "#" | |
3747 | "&& reload_completed" | |
3748 | [(parallel | |
ae156f85 | 3749 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
3750 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
3751 | (match_dup 7))) | |
3752 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
3753 | (parallel | |
3754 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
3755 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
3756 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
3757 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
3758 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
3759 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
3760 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
3761 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
b628bd8e | 3762 | operands[8] = operand_subword (operands[2], 1, 0, TImode);") |
1c7b1b7e | 3763 | |
9db1d521 HP |
3764 | ; |
3765 | ; subdi3 instruction pattern(s). | |
3766 | ; | |
3767 | ||
07893d4f UW |
3768 | (define_insn "*subdi3_sign" |
3769 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3770 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3771 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
ae156f85 | 3772 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
3773 | "TARGET_64BIT" |
3774 | "@ | |
d40c829f UW |
3775 | sgfr\t%0,%2 |
3776 | sgf\t%0,%2" | |
d3632d41 | 3777 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3778 | |
3779 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 3780 | [(set (reg CC_REGNUM) |
07893d4f UW |
3781 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3782 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3783 | (const_int 0))) | |
3784 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3785 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
3786 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3787 | "@ | |
d40c829f UW |
3788 | slgfr\t%0,%2 |
3789 | slgf\t%0,%2" | |
d3632d41 | 3790 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3791 | |
3792 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 3793 | [(set (reg CC_REGNUM) |
07893d4f UW |
3794 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3795 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))) | |
3796 | (const_int 0))) | |
3797 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3798 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" | |
3799 | "@ | |
d40c829f UW |
3800 | slgfr\t%0,%2 |
3801 | slgf\t%0,%2" | |
d3632d41 | 3802 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f UW |
3803 | |
3804 | (define_insn "*subdi3_zero" | |
3805 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3806 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3807 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) | |
ae156f85 | 3808 | (clobber (reg:CC CC_REGNUM))] |
07893d4f UW |
3809 | "TARGET_64BIT" |
3810 | "@ | |
d40c829f UW |
3811 | slgfr\t%0,%2 |
3812 | slgf\t%0,%2" | |
d3632d41 | 3813 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3814 | |
b2ba71ca | 3815 | (define_insn "*subdi3_borrow_cc" |
ae156f85 | 3816 | [(set (reg CC_REGNUM) |
b2ba71ca UW |
3817 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3818 | (match_operand:DI 2 "general_operand" "d,m")) | |
3819 | (match_dup 1))) | |
3820 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3821 | (minus:DI (match_dup 1) (match_dup 2)))] | |
3822 | "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" | |
3823 | "@ | |
3824 | slgr\t%0,%2 | |
3825 | slg\t%0,%2" | |
3826 | [(set_attr "op_type" "RRE,RXY")]) | |
3827 | ||
3828 | (define_insn "*subdi3_borrow_cconly" | |
ae156f85 | 3829 | [(set (reg CC_REGNUM) |
b2ba71ca UW |
3830 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3831 | (match_operand:DI 2 "general_operand" "d,m")) | |
3832 | (match_dup 1))) | |
3833 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3834 | "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT" | |
3835 | "@ | |
3836 | slgr\t%0,%2 | |
3837 | slg\t%0,%2" | |
3838 | [(set_attr "op_type" "RRE,RXY")]) | |
3839 | ||
07893d4f | 3840 | (define_insn "*subdi3_cc" |
ae156f85 | 3841 | [(set (reg CC_REGNUM) |
07893d4f UW |
3842 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3843 | (match_operand:DI 2 "general_operand" "d,m")) | |
3844 | (const_int 0))) | |
3845 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3846 | (minus:DI (match_dup 1) (match_dup 2)))] | |
b2ba71ca | 3847 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
07893d4f | 3848 | "@ |
d40c829f UW |
3849 | slgr\t%0,%2 |
3850 | slg\t%0,%2" | |
d3632d41 | 3851 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3852 | |
5d880bd2 | 3853 | (define_insn "*subdi3_cc2" |
ae156f85 | 3854 | [(set (reg CC_REGNUM) |
5d880bd2 UW |
3855 | (compare (match_operand:DI 1 "register_operand" "0,0") |
3856 | (match_operand:DI 2 "general_operand" "d,m"))) | |
3857 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
3858 | (minus:DI (match_dup 1) (match_dup 2)))] | |
3859 | "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT" | |
3860 | "@ | |
3861 | slgr\t%0,%2 | |
3862 | slg\t%0,%2" | |
3863 | [(set_attr "op_type" "RRE,RXY")]) | |
3864 | ||
07893d4f | 3865 | (define_insn "*subdi3_cconly" |
ae156f85 | 3866 | [(set (reg CC_REGNUM) |
07893d4f UW |
3867 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3868 | (match_operand:DI 2 "general_operand" "d,m")) | |
3869 | (const_int 0))) | |
3870 | (clobber (match_scratch:DI 0 "=d,d"))] | |
b2ba71ca | 3871 | "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT" |
07893d4f | 3872 | "@ |
d40c829f UW |
3873 | slgr\t%0,%2 |
3874 | slg\t%0,%2" | |
d3632d41 | 3875 | [(set_attr "op_type" "RRE,RXY")]) |
07893d4f | 3876 | |
5d880bd2 | 3877 | (define_insn "*subdi3_cconly2" |
ae156f85 | 3878 | [(set (reg CC_REGNUM) |
5d880bd2 UW |
3879 | (compare (match_operand:DI 1 "register_operand" "0,0") |
3880 | (match_operand:DI 2 "general_operand" "d,m"))) | |
3881 | (clobber (match_scratch:DI 0 "=d,d"))] | |
3882 | "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT" | |
3883 | "@ | |
3884 | slgr\t%0,%2 | |
3885 | slg\t%0,%2" | |
3886 | [(set_attr "op_type" "RRE,RXY")]) | |
3887 | ||
9db1d521 HP |
3888 | (define_insn "*subdi3_64" |
3889 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3890 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3891 | (match_operand:DI 2 "general_operand" "d,m") ) ) | |
ae156f85 | 3892 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
3893 | "TARGET_64BIT" |
3894 | "@ | |
d40c829f UW |
3895 | sgr\t%0,%2 |
3896 | sg\t%0,%2" | |
077dab3b | 3897 | [(set_attr "op_type" "RRE,RRE")]) |
9db1d521 | 3898 | |
e69166de UW |
3899 | (define_insn_and_split "*subdi3_31z" |
3900 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3901 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
3902 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 3903 | (clobber (reg:CC CC_REGNUM))] |
e69166de UW |
3904 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
3905 | "#" | |
3906 | "&& reload_completed" | |
3907 | [(parallel | |
ae156f85 | 3908 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
3909 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
3910 | (match_dup 7))) | |
3911 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
3912 | (parallel | |
3913 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
3914 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
3915 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
3916 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3917 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3918 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3919 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3920 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 3921 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 3922 | |
07893d4f UW |
3923 | (define_insn_and_split "*subdi3_31" |
3924 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
3925 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 3926 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 3927 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 3928 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
3929 | "#" |
3930 | "&& reload_completed" | |
3931 | [(parallel | |
3932 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 3933 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 3934 | (parallel |
ae156f85 | 3935 | [(set (reg:CCL2 CC_REGNUM) |
07893d4f UW |
3936 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
3937 | (match_dup 7))) | |
3938 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
3939 | (set (pc) | |
ae156f85 | 3940 | (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) |
07893d4f UW |
3941 | (pc) |
3942 | (label_ref (match_dup 9)))) | |
3943 | (parallel | |
3944 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
ae156f85 | 3945 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 3946 | (match_dup 9)] |
97c6f7ad UW |
3947 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
3948 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
3949 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
3950 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
3951 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
3952 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 3953 | operands[9] = gen_label_rtx ();") |
07893d4f UW |
3954 | |
3955 | (define_expand "subdi3" | |
3956 | [(parallel | |
3957 | [(set (match_operand:DI 0 "register_operand" "") | |
3958 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
3959 | (match_operand:DI 2 "general_operand" ""))) | |
ae156f85 | 3960 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 3961 | "" |
07893d4f | 3962 | "") |
9db1d521 HP |
3963 | |
3964 | ; | |
3965 | ; subsi3 instruction pattern(s). | |
3966 | ; | |
3967 | ||
07893d4f | 3968 | (define_insn "*subsi3_borrow_cc" |
ae156f85 | 3969 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3970 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3971 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3972 | (match_dup 1))) |
d3632d41 | 3973 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
07893d4f | 3974 | (minus:SI (match_dup 1) (match_dup 2)))] |
b2ba71ca | 3975 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 3976 | "@ |
d40c829f UW |
3977 | slr\t%0,%2 |
3978 | sl\t%0,%2 | |
3979 | sly\t%0,%2" | |
d3632d41 | 3980 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f UW |
3981 | |
3982 | (define_insn "*subsi3_borrow_cconly" | |
ae156f85 | 3983 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3984 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3985 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
07893d4f | 3986 | (match_dup 1))) |
d3632d41 | 3987 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
b2ba71ca | 3988 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 3989 | "@ |
d40c829f UW |
3990 | slr\t%0,%2 |
3991 | sl\t%0,%2 | |
3992 | sly\t%0,%2" | |
b2ba71ca | 3993 | [(set_attr "op_type" "RR,RX,RXY")]) |
07893d4f | 3994 | |
9db1d521 | 3995 | (define_insn "*subsi3_cc" |
ae156f85 | 3996 | [(set (reg CC_REGNUM) |
d3632d41 UW |
3997 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
3998 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 3999 | (const_int 0))) |
d3632d41 | 4000 | (set (match_operand:SI 0 "register_operand" "=d,d,d") |
9db1d521 | 4001 | (minus:SI (match_dup 1) (match_dup 2)))] |
b2ba71ca | 4002 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4003 | "@ |
d40c829f UW |
4004 | slr\t%0,%2 |
4005 | sl\t%0,%2 | |
4006 | sly\t%0,%2" | |
d3632d41 | 4007 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 4008 | |
5d880bd2 | 4009 | (define_insn "*subsi3_cc2" |
ae156f85 | 4010 | [(set (reg CC_REGNUM) |
5d880bd2 UW |
4011 | (compare (match_operand:SI 1 "register_operand" "0,0,0") |
4012 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
4013 | (set (match_operand:SI 0 "register_operand" "=d,d,d") | |
4014 | (minus:SI (match_dup 1) (match_dup 2)))] | |
4015 | "s390_match_ccmode (insn, CCL3mode)" | |
4016 | "@ | |
4017 | slr\t%0,%2 | |
4018 | sl\t%0,%2 | |
4019 | sly\t%0,%2" | |
4020 | [(set_attr "op_type" "RR,RX,RXY")]) | |
4021 | ||
9db1d521 | 4022 | (define_insn "*subsi3_cconly" |
ae156f85 | 4023 | [(set (reg CC_REGNUM) |
d3632d41 UW |
4024 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") |
4025 | (match_operand:SI 2 "general_operand" "d,R,T")) | |
9db1d521 | 4026 | (const_int 0))) |
d3632d41 | 4027 | (clobber (match_scratch:SI 0 "=d,d,d"))] |
b2ba71ca | 4028 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 4029 | "@ |
d40c829f UW |
4030 | slr\t%0,%2 |
4031 | sl\t%0,%2 | |
4032 | sly\t%0,%2" | |
d3632d41 | 4033 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 4034 | |
5d880bd2 | 4035 | (define_insn "*subsi3_cconly2" |
ae156f85 | 4036 | [(set (reg CC_REGNUM) |
5d880bd2 UW |
4037 | (compare (match_operand:SI 1 "register_operand" "0,0,0") |
4038 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
4039 | (clobber (match_scratch:SI 0 "=d,d,d"))] | |
4040 | "s390_match_ccmode (insn, CCL3mode)" | |
4041 | "@ | |
4042 | slr\t%0,%2 | |
4043 | sl\t%0,%2 | |
4044 | sly\t%0,%2" | |
4045 | [(set_attr "op_type" "RR,RX,RXY")]) | |
4046 | ||
07893d4f | 4047 | (define_insn "*subsi3_sign" |
d3632d41 UW |
4048 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4049 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
4050 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
ae156f85 | 4051 | (clobber (reg:CC CC_REGNUM))] |
07893d4f | 4052 | "" |
d3632d41 | 4053 | "@ |
d40c829f UW |
4054 | sh\t%0,%2 |
4055 | shy\t%0,%2" | |
d3632d41 | 4056 | [(set_attr "op_type" "RX,RXY")]) |
07893d4f | 4057 | |
9db1d521 | 4058 | (define_insn "subsi3" |
d3632d41 UW |
4059 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") |
4060 | (minus:SI (match_operand:SI 1 "register_operand" "0,0,0") | |
4061 | (match_operand:SI 2 "general_operand" "d,R,T"))) | |
ae156f85 | 4062 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
4063 | "" |
4064 | "@ | |
d40c829f UW |
4065 | sr\t%0,%2 |
4066 | s\t%0,%2 | |
4067 | sy\t%0,%2" | |
d3632d41 | 4068 | [(set_attr "op_type" "RR,RX,RXY")]) |
9db1d521 | 4069 | |
9db1d521 HP |
4070 | |
4071 | ; | |
f5905b37 | 4072 | ; sub(df|sf)3 instruction pattern(s). |
9db1d521 HP |
4073 | ; |
4074 | ||
f5905b37 | 4075 | (define_expand "sub<mode>3" |
9db1d521 | 4076 | [(parallel |
f5905b37 AS |
4077 | [(set (match_operand:FPR 0 "register_operand" "=f,f") |
4078 | (minus:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
4079 | (match_operand:FPR 2 "general_operand" "f,R"))) | |
ae156f85 | 4080 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
4081 | "TARGET_HARD_FLOAT" |
4082 | "") | |
4083 | ||
f5905b37 AS |
4084 | (define_insn "*sub<mode>3" |
4085 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4086 | (minus:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
4087 | (match_operand:FPR 2 "general_operand" "f,R"))) | |
ae156f85 | 4088 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
4089 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4090 | "@ | |
f5905b37 AS |
4091 | s<de>br\t%0,%2 |
4092 | s<de>b\t%0,%2" | |
ce50cae8 | 4093 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4094 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 4095 | |
f5905b37 | 4096 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 4097 | [(set (reg CC_REGNUM) |
f5905b37 AS |
4098 | (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0") |
4099 | (match_operand:FPR 2 "general_operand" "f,R")) | |
4100 | (match_operand:FPR 3 "const0_operand" ""))) | |
4101 | (set (match_operand:FPR 0 "register_operand" "=f,f") | |
4102 | (minus:FPR (match_dup 1) (match_dup 2)))] | |
3ef093a8 AK |
4103 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4104 | "@ | |
f5905b37 AS |
4105 | s<de>br\t%0,%2 |
4106 | s<de>b\t%0,%2" | |
3ef093a8 | 4107 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4108 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4109 | |
f5905b37 | 4110 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 4111 | [(set (reg CC_REGNUM) |
f5905b37 AS |
4112 | (compare (minus:FPR (match_operand:FPR 1 "nonimmediate_operand" "0,0") |
4113 | (match_operand:FPR 2 "general_operand" "f,R")) | |
4114 | (match_operand:FPR 3 "const0_operand" ""))) | |
4115 | (clobber (match_scratch:FPR 0 "=f,f"))] | |
3ef093a8 AK |
4116 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4117 | "@ | |
f5905b37 AS |
4118 | s<de>br\t%0,%2 |
4119 | s<de>b\t%0,%2" | |
3ef093a8 | 4120 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4121 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 4122 | |
f5905b37 AS |
4123 | (define_insn "*sub<mode>3_ibm" |
4124 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4125 | (minus:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
4126 | (match_operand:FPR 2 "general_operand" "f,R"))) | |
ae156f85 | 4127 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 HP |
4128 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4129 | "@ | |
f5905b37 AS |
4130 | s<de>r\t%0,%2 |
4131 | s<de>\t%0,%2" | |
9db1d521 | 4132 | [(set_attr "op_type" "RR,RX") |
f5905b37 | 4133 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 HP |
4134 | |
4135 | ||
e69166de UW |
4136 | ;; |
4137 | ;;- Conditional add/subtract instructions. | |
4138 | ;; | |
4139 | ||
4140 | ; | |
9a91a21f | 4141 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
4142 | ; |
4143 | ||
9a91a21f | 4144 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 4145 | [(set (reg CC_REGNUM) |
e69166de | 4146 | (compare |
9a91a21f AS |
4147 | (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0") |
4148 | (match_operand:GPR 2 "general_operand" "d,m")) | |
4149 | (match_operand:GPR 3 "s390_alc_comparison" "")) | |
e69166de | 4150 | (const_int 0))) |
9a91a21f AS |
4151 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
4152 | (plus:GPR (plus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 4153 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 4154 | "@ |
9a91a21f AS |
4155 | alc<g>r\t%0,%2 |
4156 | alc<g>\t%0,%2" | |
e69166de UW |
4157 | [(set_attr "op_type" "RRE,RXY")]) |
4158 | ||
9a91a21f AS |
4159 | (define_insn "*add<mode>3_alc" |
4160 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
4161 | (plus:GPR (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,0") | |
4162 | (match_operand:GPR 2 "general_operand" "d,m")) | |
4163 | (match_operand:GPR 3 "s390_alc_comparison" ""))) | |
ae156f85 | 4164 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 4165 | "TARGET_CPU_ZARCH" |
e69166de | 4166 | "@ |
9a91a21f AS |
4167 | alc<g>r\t%0,%2 |
4168 | alc<g>\t%0,%2" | |
e69166de UW |
4169 | [(set_attr "op_type" "RRE,RXY")]) |
4170 | ||
9a91a21f | 4171 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 4172 | [(set (reg CC_REGNUM) |
e69166de | 4173 | (compare |
9a91a21f AS |
4174 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
4175 | (match_operand:GPR 2 "general_operand" "d,m")) | |
4176 | (match_operand:GPR 3 "s390_slb_comparison" "")) | |
e69166de | 4177 | (const_int 0))) |
9a91a21f AS |
4178 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
4179 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 4180 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 4181 | "@ |
9a91a21f AS |
4182 | slb<g>r\t%0,%2 |
4183 | slb<g>\t%0,%2" | |
e69166de UW |
4184 | [(set_attr "op_type" "RRE,RXY")]) |
4185 | ||
9a91a21f AS |
4186 | (define_insn "*sub<mode>3_slb" |
4187 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
4188 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
4189 | (match_operand:GPR 2 "general_operand" "d,m")) | |
4190 | (match_operand:GPR 3 "s390_slb_comparison" ""))) | |
ae156f85 | 4191 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 4192 | "TARGET_CPU_ZARCH" |
e69166de | 4193 | "@ |
9a91a21f AS |
4194 | slb<g>r\t%0,%2 |
4195 | slb<g>\t%0,%2" | |
e69166de UW |
4196 | [(set_attr "op_type" "RRE,RXY")]) |
4197 | ||
9a91a21f AS |
4198 | (define_expand "add<mode>cc" |
4199 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 4200 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
4201 | (match_operand:GPR 2 "register_operand" "") |
4202 | (match_operand:GPR 3 "const_int_operand" "")] | |
5d880bd2 UW |
4203 | "TARGET_CPU_ZARCH" |
4204 | "if (!s390_expand_addcc (GET_CODE (operands[1]), | |
4205 | s390_compare_op0, s390_compare_op1, | |
4206 | operands[0], operands[2], | |
4207 | operands[3])) FAIL; DONE;") | |
4208 | ||
4209 | ; | |
4210 | ; scond instruction pattern(s). | |
4211 | ; | |
4212 | ||
9a91a21f AS |
4213 | (define_insn_and_split "*scond<mode>" |
4214 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
4215 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 4216 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
4217 | "TARGET_CPU_ZARCH" |
4218 | "#" | |
4219 | "&& reload_completed" | |
4220 | [(set (match_dup 0) (const_int 0)) | |
4221 | (parallel | |
9a91a21f | 4222 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 0) (match_dup 0)) |
5d880bd2 | 4223 | (match_dup 1))) |
ae156f85 | 4224 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4225 | "") |
5d880bd2 | 4226 | |
9a91a21f AS |
4227 | (define_insn_and_split "*scond<mode>_neg" |
4228 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
4229 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 4230 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
4231 | "TARGET_CPU_ZARCH" |
4232 | "#" | |
4233 | "&& reload_completed" | |
4234 | [(set (match_dup 0) (const_int 0)) | |
4235 | (parallel | |
9a91a21f AS |
4236 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
4237 | (match_dup 1))) | |
ae156f85 | 4238 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 4239 | (parallel |
9a91a21f | 4240 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 4241 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4242 | "") |
5d880bd2 | 4243 | |
5d880bd2 | 4244 | |
9a91a21f AS |
4245 | (define_expand "s<code>" |
4246 | [(set (match_operand:SI 0 "register_operand" "") | |
4247 | (SCOND (match_dup 0) | |
4248 | (match_dup 0)))] | |
5d880bd2 | 4249 | "TARGET_CPU_ZARCH" |
9a91a21f | 4250 | "if (!s390_expand_addcc (<CODE>, s390_compare_op0, s390_compare_op1, |
5d880bd2 UW |
4251 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
4252 | ||
69950452 AS |
4253 | (define_expand "seq" |
4254 | [(parallel | |
4255 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4256 | (match_dup 1)) | |
4257 | (clobber (reg:CC CC_REGNUM))]) | |
4258 | (parallel | |
4259 | [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 1))) | |
4260 | (clobber (reg:CC CC_REGNUM))])] | |
4261 | "" | |
4262 | { | |
4263 | if (!s390_compare_emitted || GET_MODE (s390_compare_emitted) != CCZ1mode) | |
4264 | FAIL; | |
4265 | operands[1] = s390_emit_compare (NE, s390_compare_op0, s390_compare_op1); | |
4266 | PUT_MODE (operands[1], SImode); | |
4267 | }) | |
4268 | ||
4269 | (define_insn_and_split "*sne" | |
4270 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4271 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") | |
4272 | (const_int 0))) | |
4273 | (clobber (reg:CC CC_REGNUM))] | |
4274 | "" | |
4275 | "#" | |
4276 | "reload_completed" | |
4277 | [(parallel | |
4278 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
4279 | (clobber (reg:CC CC_REGNUM))])]) | |
4280 | ||
e69166de | 4281 | |
9db1d521 HP |
4282 | ;; |
4283 | ;;- Multiply instructions. | |
4284 | ;; | |
4285 | ||
4023fb28 UW |
4286 | ; |
4287 | ; muldi3 instruction pattern(s). | |
4288 | ; | |
9db1d521 | 4289 | |
07893d4f UW |
4290 | (define_insn "*muldi3_sign" |
4291 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4292 | (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")) | |
4293 | (match_operand:DI 1 "register_operand" "0,0")))] | |
4294 | "TARGET_64BIT" | |
4295 | "@ | |
d40c829f UW |
4296 | msgfr\t%0,%2 |
4297 | msgf\t%0,%2" | |
d3632d41 | 4298 | [(set_attr "op_type" "RRE,RXY") |
ed0e512a | 4299 | (set_attr "type" "imuldi")]) |
07893d4f | 4300 | |
4023fb28 | 4301 | (define_insn "muldi3" |
9db1d521 | 4302 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
96fd3851 | 4303 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0") |
07893d4f | 4304 | (match_operand:DI 2 "general_operand" "d,K,m")))] |
9db1d521 HP |
4305 | "TARGET_64BIT" |
4306 | "@ | |
d40c829f UW |
4307 | msgr\t%0,%2 |
4308 | mghi\t%0,%h2 | |
4309 | msg\t%0,%2" | |
d3632d41 | 4310 | [(set_attr "op_type" "RRE,RI,RXY") |
ed0e512a | 4311 | (set_attr "type" "imuldi")]) |
f2d3c02a | 4312 | |
9db1d521 HP |
4313 | ; |
4314 | ; mulsi3 instruction pattern(s). | |
4315 | ; | |
4316 | ||
f1e77d83 UW |
4317 | (define_insn "*mulsi3_sign" |
4318 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4319 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R")) | |
4320 | (match_operand:SI 1 "register_operand" "0")))] | |
4321 | "" | |
4322 | "mh\t%0,%2" | |
4323 | [(set_attr "op_type" "RX") | |
ed0e512a | 4324 | (set_attr "type" "imulhi")]) |
f1e77d83 | 4325 | |
9db1d521 | 4326 | (define_insn "mulsi3" |
d3632d41 UW |
4327 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4328 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
4329 | (match_operand:SI 2 "general_operand" "d,K,R,T")))] | |
9db1d521 HP |
4330 | "" |
4331 | "@ | |
d40c829f UW |
4332 | msr\t%0,%2 |
4333 | mhi\t%0,%h2 | |
4334 | ms\t%0,%2 | |
4335 | msy\t%0,%2" | |
d3632d41 | 4336 | [(set_attr "op_type" "RRE,RI,RX,RXY") |
ed0e512a | 4337 | (set_attr "type" "imulsi,imulhi,imulsi,imulsi")]) |
9db1d521 | 4338 | |
4023fb28 UW |
4339 | ; |
4340 | ; mulsidi3 instruction pattern(s). | |
4341 | ; | |
4342 | ||
f1e77d83 UW |
4343 | (define_insn "mulsidi3" |
4344 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4345 | (mult:DI (sign_extend:DI | |
4346 | (match_operand:SI 1 "register_operand" "%0,0")) | |
4347 | (sign_extend:DI | |
4348 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))] | |
4023fb28 | 4349 | "!TARGET_64BIT" |
f1e77d83 UW |
4350 | "@ |
4351 | mr\t%0,%2 | |
4352 | m\t%0,%2" | |
4353 | [(set_attr "op_type" "RR,RX") | |
ed0e512a | 4354 | (set_attr "type" "imulsi")]) |
4023fb28 | 4355 | |
f1e77d83 UW |
4356 | ; |
4357 | ; umulsidi3 instruction pattern(s). | |
4358 | ; | |
c7453384 | 4359 | |
f1e77d83 UW |
4360 | (define_insn "umulsidi3" |
4361 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4362 | (mult:DI (zero_extend:DI | |
4363 | (match_operand:SI 1 "register_operand" "%0,0")) | |
4364 | (zero_extend:DI | |
4365 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))] | |
4366 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4367 | "@ | |
4368 | mlr\t%0,%2 | |
4369 | ml\t%0,%2" | |
4370 | [(set_attr "op_type" "RRE,RXY") | |
ed0e512a | 4371 | (set_attr "type" "imulsi")]) |
c7453384 | 4372 | |
9db1d521 | 4373 | ; |
f5905b37 | 4374 | ; mul(df|sf)3 instruction pattern(s). |
9db1d521 HP |
4375 | ; |
4376 | ||
f5905b37 AS |
4377 | (define_expand "mul<mode>3" |
4378 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4379 | (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
4380 | (match_operand:FPR 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4381 | "TARGET_HARD_FLOAT" |
4382 | "") | |
4383 | ||
f5905b37 AS |
4384 | (define_insn "*mul<mode>3" |
4385 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4386 | (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
4387 | (match_operand:FPR 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4388 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4389 | "@ | |
f5905b37 AS |
4390 | m<dee>br\t%0,%2 |
4391 | m<dee>b\t%0,%2" | |
ce50cae8 | 4392 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4393 | (set_attr "type" "fmul<mode>")]) |
9db1d521 | 4394 | |
f5905b37 AS |
4395 | (define_insn "*mul<mode>3_ibm" |
4396 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4397 | (mult:FPR (match_operand:FPR 1 "nonimmediate_operand" "%0,0") | |
4398 | (match_operand:FPR 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4399 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4400 | "@ | |
f5905b37 AS |
4401 | m<de>r\t%0,%2 |
4402 | m<de>\t%0,%2" | |
9db1d521 | 4403 | [(set_attr "op_type" "RR,RX") |
f5905b37 | 4404 | (set_attr "type" "fmul<mode>")]) |
9db1d521 | 4405 | |
f5905b37 AS |
4406 | (define_insn "*fmadd<mode>" |
4407 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4408 | (plus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "%f,f") | |
4409 | (match_operand:FPR 2 "nonimmediate_operand" "f,R")) | |
4410 | (match_operand:FPR 3 "register_operand" "0,0")))] | |
f2d226e1 | 4411 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 | 4412 | "@ |
f5905b37 AS |
4413 | ma<de>br\t%0,%1,%2 |
4414 | ma<de>b\t%0,%1,%2" | |
a1b892b5 | 4415 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4416 | (set_attr "type" "fmul<mode>")]) |
a1b892b5 | 4417 | |
f5905b37 AS |
4418 | (define_insn "*fmsub<mode>" |
4419 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4420 | (minus:FPR (mult:FPR (match_operand:FPR 1 "register_operand" "f,f") | |
4421 | (match_operand:FPR 2 "nonimmediate_operand" "f,R")) | |
4422 | (match_operand:FPR 3 "register_operand" "0,0")))] | |
f2d226e1 | 4423 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD" |
a1b892b5 | 4424 | "@ |
f5905b37 AS |
4425 | ms<de>br\t%0,%1,%2 |
4426 | ms<de>b\t%0,%1,%2" | |
ce50cae8 | 4427 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4428 | (set_attr "type" "fmul<mode>")]) |
9db1d521 HP |
4429 | |
4430 | ;; | |
4431 | ;;- Divide and modulo instructions. | |
4432 | ;; | |
4433 | ||
4434 | ; | |
4023fb28 | 4435 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
4436 | ; |
4437 | ||
4023fb28 UW |
4438 | (define_expand "divmoddi4" |
4439 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 4440 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
4441 | (match_operand:DI 2 "general_operand" ""))) |
4442 | (set (match_operand:DI 3 "general_operand" "") | |
4443 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
4444 | (clobber (match_dup 4))] | |
9db1d521 | 4445 | "TARGET_64BIT" |
9db1d521 | 4446 | { |
f1e77d83 | 4447 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
4448 | |
4449 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
4450 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
4451 | |
4452 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 4453 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
4454 | |
4455 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4456 | REG_NOTES (insn) = | |
4457 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4458 | ||
4459 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4460 | REG_NOTES (insn) = | |
4461 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4462 | |
9db1d521 | 4463 | DONE; |
10bbf137 | 4464 | }) |
9db1d521 HP |
4465 | |
4466 | (define_insn "divmodtidi3" | |
4023fb28 UW |
4467 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
4468 | (ior:TI | |
4023fb28 UW |
4469 | (ashift:TI |
4470 | (zero_extend:TI | |
5665e398 UW |
4471 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
4472 | (match_operand:DI 2 "general_operand" "d,m"))) | |
4473 | (const_int 64)) | |
4474 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9db1d521 HP |
4475 | "TARGET_64BIT" |
4476 | "@ | |
d40c829f UW |
4477 | dsgr\t%0,%2 |
4478 | dsg\t%0,%2" | |
d3632d41 | 4479 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4480 | (set_attr "type" "idiv")]) |
9db1d521 | 4481 | |
4023fb28 UW |
4482 | (define_insn "divmodtisi3" |
4483 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
4484 | (ior:TI | |
4023fb28 UW |
4485 | (ashift:TI |
4486 | (zero_extend:TI | |
5665e398 | 4487 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 4488 | (sign_extend:DI |
5665e398 UW |
4489 | (match_operand:SI 2 "nonimmediate_operand" "d,m")))) |
4490 | (const_int 64)) | |
4491 | (zero_extend:TI | |
4492 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9db1d521 | 4493 | "TARGET_64BIT" |
4023fb28 | 4494 | "@ |
d40c829f UW |
4495 | dsgfr\t%0,%2 |
4496 | dsgf\t%0,%2" | |
d3632d41 | 4497 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4498 | (set_attr "type" "idiv")]) |
9db1d521 | 4499 | |
4023fb28 UW |
4500 | ; |
4501 | ; udivmoddi4 instruction pattern(s). | |
4502 | ; | |
9db1d521 | 4503 | |
4023fb28 UW |
4504 | (define_expand "udivmoddi4" |
4505 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
4506 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
4507 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
4508 | (set (match_operand:DI 3 "general_operand" "") | |
4509 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
4510 | (clobber (match_dup 4))] | |
9db1d521 | 4511 | "TARGET_64BIT" |
9db1d521 | 4512 | { |
4023fb28 UW |
4513 | rtx insn, div_equal, mod_equal, equal; |
4514 | ||
4515 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
4516 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
4517 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
4518 | gen_rtx_ASHIFT (TImode, |
4519 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
4520 | GEN_INT (64)), |
4521 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
4522 | |
4523 | operands[4] = gen_reg_rtx(TImode); | |
4524 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4525 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); | |
4526 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
4527 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); | |
4528 | REG_NOTES (insn) = | |
4529 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4530 | ||
4531 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
4532 | REG_NOTES (insn) = | |
4533 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4534 | ||
4535 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
4536 | REG_NOTES (insn) = | |
4537 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4538 | |
9db1d521 | 4539 | DONE; |
10bbf137 | 4540 | }) |
9db1d521 HP |
4541 | |
4542 | (define_insn "udivmodtidi3" | |
4023fb28 | 4543 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 4544 | (ior:TI |
5665e398 UW |
4545 | (ashift:TI |
4546 | (zero_extend:TI | |
4547 | (truncate:DI | |
2f7e5a0d EC |
4548 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
4549 | (zero_extend:TI | |
5665e398 UW |
4550 | (match_operand:DI 2 "nonimmediate_operand" "d,m"))))) |
4551 | (const_int 64)) | |
4552 | (zero_extend:TI | |
4553 | (truncate:DI | |
4554 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9db1d521 HP |
4555 | "TARGET_64BIT" |
4556 | "@ | |
d40c829f UW |
4557 | dlgr\t%0,%2 |
4558 | dlg\t%0,%2" | |
d3632d41 | 4559 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 4560 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4561 | |
4562 | ; | |
4023fb28 | 4563 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
4564 | ; |
4565 | ||
4023fb28 UW |
4566 | (define_expand "divmodsi4" |
4567 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4568 | (div:SI (match_operand:SI 1 "general_operand" "") | |
4569 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4570 | (set (match_operand:SI 3 "general_operand" "") | |
4571 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
4572 | (clobber (match_dup 4))] | |
9db1d521 | 4573 | "!TARGET_64BIT" |
9db1d521 | 4574 | { |
4023fb28 UW |
4575 | rtx insn, div_equal, mod_equal, equal; |
4576 | ||
4577 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
4578 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
4579 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4580 | gen_rtx_ASHIFT (DImode, |
4581 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
4582 | GEN_INT (32)), |
4583 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
4584 | |
4585 | operands[4] = gen_reg_rtx(DImode); | |
4586 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
4587 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); | |
4588 | REG_NOTES (insn) = | |
4589 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4590 | ||
4591 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4592 | REG_NOTES (insn) = | |
4593 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4594 | ||
4595 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4596 | REG_NOTES (insn) = | |
4597 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
9db1d521 | 4598 | |
9db1d521 | 4599 | DONE; |
10bbf137 | 4600 | }) |
9db1d521 HP |
4601 | |
4602 | (define_insn "divmoddisi3" | |
4023fb28 | 4603 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 4604 | (ior:DI |
5665e398 UW |
4605 | (ashift:DI |
4606 | (zero_extend:DI | |
4607 | (truncate:SI | |
2f7e5a0d EC |
4608 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
4609 | (sign_extend:DI | |
5665e398 UW |
4610 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
4611 | (const_int 32)) | |
4612 | (zero_extend:DI | |
4613 | (truncate:SI | |
4614 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9db1d521 HP |
4615 | "!TARGET_64BIT" |
4616 | "@ | |
d40c829f UW |
4617 | dr\t%0,%2 |
4618 | d\t%0,%2" | |
9db1d521 | 4619 | [(set_attr "op_type" "RR,RX") |
077dab3b | 4620 | (set_attr "type" "idiv")]) |
9db1d521 HP |
4621 | |
4622 | ; | |
4623 | ; udivsi3 and umodsi3 instruction pattern(s). | |
4624 | ; | |
4625 | ||
f1e77d83 UW |
4626 | (define_expand "udivmodsi4" |
4627 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
4628 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4629 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
4630 | (set (match_operand:SI 3 "general_operand" "") | |
4631 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
4632 | (clobber (match_dup 4))] | |
4633 | "!TARGET_64BIT && TARGET_CPU_ZARCH" | |
4634 | { | |
4635 | rtx insn, div_equal, mod_equal, equal; | |
4636 | ||
4637 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4638 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4639 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
4640 | gen_rtx_ASHIFT (DImode, |
4641 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
4642 | GEN_INT (32)), |
4643 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
4644 | |
4645 | operands[4] = gen_reg_rtx(DImode); | |
4646 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
4647 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); | |
4648 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
4649 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); | |
4650 | REG_NOTES (insn) = | |
4651 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
4652 | ||
4653 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
4654 | REG_NOTES (insn) = | |
4655 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
4656 | ||
4657 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
4658 | REG_NOTES (insn) = | |
4659 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
4660 | ||
4661 | DONE; | |
4662 | }) | |
4663 | ||
4664 | (define_insn "udivmoddisi3" | |
4665 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 4666 | (ior:DI |
5665e398 UW |
4667 | (ashift:DI |
4668 | (zero_extend:DI | |
4669 | (truncate:SI | |
2f7e5a0d EC |
4670 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
4671 | (zero_extend:DI | |
5665e398 UW |
4672 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))) |
4673 | (const_int 32)) | |
4674 | (zero_extend:DI | |
4675 | (truncate:SI | |
4676 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
f1e77d83 UW |
4677 | "!TARGET_64BIT && TARGET_CPU_ZARCH" |
4678 | "@ | |
4679 | dlr\t%0,%2 | |
4680 | dl\t%0,%2" | |
4681 | [(set_attr "op_type" "RRE,RXY") | |
4682 | (set_attr "type" "idiv")]) | |
4023fb28 | 4683 | |
9db1d521 HP |
4684 | (define_expand "udivsi3" |
4685 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4686 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
4687 | (match_operand:SI 2 "general_operand" ""))) |
4688 | (clobber (match_dup 3))] | |
f1e77d83 | 4689 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 4690 | { |
4023fb28 UW |
4691 | rtx insn, udiv_equal, umod_equal, equal; |
4692 | ||
4693 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4694 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4695 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4696 | gen_rtx_ASHIFT (DImode, |
4697 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
4698 | GEN_INT (32)), |
4699 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 4700 | |
4023fb28 | 4701 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
4702 | |
4703 | if (CONSTANT_P (operands[2])) | |
4704 | { | |
4705 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
4706 | { | |
4707 | rtx label1 = gen_label_rtx (); | |
4708 | ||
4023fb28 UW |
4709 | operands[1] = make_safe_from (operands[1], operands[0]); |
4710 | emit_move_insn (operands[0], const0_rtx); | |
4711 | emit_insn (gen_cmpsi (operands[1], operands[2])); | |
9db1d521 | 4712 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 | 4713 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
4714 | emit_label (label1); |
4715 | } | |
4716 | else | |
4717 | { | |
c7453384 EC |
4718 | operands[2] = force_reg (SImode, operands[2]); |
4719 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4720 | |
4721 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4722 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4723 | operands[2])); | |
4724 | REG_NOTES (insn) = | |
4725 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4726 | |
4727 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4728 | gen_lowpart (SImode, operands[3])); |
4729 | REG_NOTES (insn) = | |
c7453384 | 4730 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4731 | udiv_equal, REG_NOTES (insn)); |
9db1d521 HP |
4732 | } |
4733 | } | |
4734 | else | |
c7453384 | 4735 | { |
9db1d521 HP |
4736 | rtx label1 = gen_label_rtx (); |
4737 | rtx label2 = gen_label_rtx (); | |
4738 | rtx label3 = gen_label_rtx (); | |
4739 | ||
c7453384 EC |
4740 | operands[1] = force_reg (SImode, operands[1]); |
4741 | operands[1] = make_safe_from (operands[1], operands[0]); | |
4742 | operands[2] = force_reg (SImode, operands[2]); | |
4743 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4744 | |
4745 | emit_move_insn (operands[0], const0_rtx); | |
9db1d521 HP |
4746 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
4747 | emit_jump_insn (gen_bgtu (label3)); | |
220a826e | 4748 | emit_insn (gen_cmpsi (operands[2], const0_rtx)); |
9db1d521 HP |
4749 | emit_jump_insn (gen_blt (label2)); |
4750 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4751 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
4752 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
4753 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4754 | operands[2])); | |
4755 | REG_NOTES (insn) = | |
4756 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4757 | |
4758 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4759 | gen_lowpart (SImode, operands[3])); |
4760 | REG_NOTES (insn) = | |
c7453384 | 4761 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4762 | udiv_equal, REG_NOTES (insn)); |
f314b9b1 | 4763 | emit_jump (label3); |
9db1d521 | 4764 | emit_label (label1); |
4023fb28 | 4765 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 4766 | emit_jump (label3); |
9db1d521 | 4767 | emit_label (label2); |
4023fb28 | 4768 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
4769 | emit_label (label3); |
4770 | } | |
c7453384 | 4771 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 4772 | DONE; |
10bbf137 | 4773 | }) |
9db1d521 HP |
4774 | |
4775 | (define_expand "umodsi3" | |
4776 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4777 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
4778 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
4779 | (clobber (match_dup 3))] | |
f1e77d83 | 4780 | "!TARGET_64BIT && !TARGET_CPU_ZARCH" |
9db1d521 | 4781 | { |
4023fb28 UW |
4782 | rtx insn, udiv_equal, umod_equal, equal; |
4783 | ||
4784 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
4785 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
4786 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
4787 | gen_rtx_ASHIFT (DImode, |
4788 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
4789 | GEN_INT (32)), |
4790 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 4791 | |
4023fb28 | 4792 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
4793 | |
4794 | if (CONSTANT_P (operands[2])) | |
4795 | { | |
4796 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
4797 | { | |
4798 | rtx label1 = gen_label_rtx (); | |
4799 | ||
4023fb28 UW |
4800 | operands[1] = make_safe_from (operands[1], operands[0]); |
4801 | emit_move_insn (operands[0], operands[1]); | |
4802 | emit_insn (gen_cmpsi (operands[0], operands[2])); | |
9db1d521 | 4803 | emit_jump_insn (gen_bltu (label1)); |
4023fb28 UW |
4804 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
4805 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
4806 | emit_label (label1); |
4807 | } | |
4808 | else | |
4809 | { | |
c7453384 EC |
4810 | operands[2] = force_reg (SImode, operands[2]); |
4811 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
4812 | |
4813 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
4814 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4815 | operands[2])); | |
4816 | REG_NOTES (insn) = | |
4817 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4818 | |
4819 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4820 | gen_highpart (SImode, operands[3])); |
4821 | REG_NOTES (insn) = | |
c7453384 | 4822 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4823 | umod_equal, REG_NOTES (insn)); |
9db1d521 HP |
4824 | } |
4825 | } | |
4826 | else | |
4827 | { | |
4828 | rtx label1 = gen_label_rtx (); | |
4829 | rtx label2 = gen_label_rtx (); | |
4830 | rtx label3 = gen_label_rtx (); | |
4831 | ||
c7453384 EC |
4832 | operands[1] = force_reg (SImode, operands[1]); |
4833 | operands[1] = make_safe_from (operands[1], operands[0]); | |
4834 | operands[2] = force_reg (SImode, operands[2]); | |
4835 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 4836 | |
c7453384 | 4837 | emit_move_insn(operands[0], operands[1]); |
4023fb28 | 4838 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
9db1d521 | 4839 | emit_jump_insn (gen_bgtu (label3)); |
220a826e | 4840 | emit_insn (gen_cmpsi (operands[2], const0_rtx)); |
9db1d521 HP |
4841 | emit_jump_insn (gen_blt (label2)); |
4842 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
4843 | emit_jump_insn (gen_beq (label1)); | |
4023fb28 UW |
4844 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
4845 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
4846 | operands[2])); | |
4847 | REG_NOTES (insn) = | |
4848 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
c7453384 EC |
4849 | |
4850 | insn = emit_move_insn (operands[0], | |
4023fb28 UW |
4851 | gen_highpart (SImode, operands[3])); |
4852 | REG_NOTES (insn) = | |
c7453384 | 4853 | gen_rtx_EXPR_LIST (REG_EQUAL, |
4023fb28 | 4854 | umod_equal, REG_NOTES (insn)); |
f314b9b1 | 4855 | emit_jump (label3); |
9db1d521 | 4856 | emit_label (label1); |
4023fb28 | 4857 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 4858 | emit_jump (label3); |
9db1d521 | 4859 | emit_label (label2); |
4023fb28 | 4860 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
4861 | emit_label (label3); |
4862 | } | |
9db1d521 | 4863 | DONE; |
10bbf137 | 4864 | }) |
9db1d521 HP |
4865 | |
4866 | ; | |
f5905b37 | 4867 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
4868 | ; |
4869 | ||
f5905b37 AS |
4870 | (define_expand "div<mode>3" |
4871 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4872 | (div:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
4873 | (match_operand:FPR 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4874 | "TARGET_HARD_FLOAT" |
4875 | "") | |
4876 | ||
f5905b37 AS |
4877 | (define_insn "*div<mode>3" |
4878 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4879 | (div:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
4880 | (match_operand:FPR 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4881 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
4882 | "@ | |
f5905b37 AS |
4883 | d<de>br\t%0,%2 |
4884 | d<de>b\t%0,%2" | |
ce50cae8 | 4885 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 4886 | (set_attr "type" "fdiv<mode>")]) |
9db1d521 | 4887 | |
f5905b37 AS |
4888 | (define_insn "*div<mode>3_ibm" |
4889 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
4890 | (div:FPR (match_operand:FPR 1 "register_operand" "0,0") | |
4891 | (match_operand:FPR 2 "general_operand" "f,R")))] | |
9db1d521 HP |
4892 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
4893 | "@ | |
f5905b37 AS |
4894 | d<de>r\t%0,%2 |
4895 | d<de>\t%0,%2" | |
9db1d521 | 4896 | [(set_attr "op_type" "RR,RX") |
f5905b37 | 4897 | (set_attr "type" "fdiv<mode>")]) |
9db1d521 HP |
4898 | |
4899 | ||
4900 | ;; | |
4901 | ;;- And instructions. | |
4902 | ;; | |
4903 | ||
047d35ed AS |
4904 | (define_expand "and<mode>3" |
4905 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
4906 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
4907 | (match_operand:INT 2 "general_operand" ""))) | |
4908 | (clobber (reg:CC CC_REGNUM))] | |
4909 | "" | |
4910 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
4911 | ||
9db1d521 HP |
4912 | ; |
4913 | ; anddi3 instruction pattern(s). | |
4914 | ; | |
4915 | ||
4916 | (define_insn "*anddi3_cc" | |
ae156f85 | 4917 | [(set (reg CC_REGNUM) |
96fd3851 | 4918 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 4919 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 | 4920 | (const_int 0))) |
4023fb28 | 4921 | (set (match_operand:DI 0 "register_operand" "=d,d") |
9db1d521 HP |
4922 | (and:DI (match_dup 1) (match_dup 2)))] |
4923 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
4924 | "@ | |
d40c829f UW |
4925 | ngr\t%0,%2 |
4926 | ng\t%0,%2" | |
d3632d41 | 4927 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 HP |
4928 | |
4929 | (define_insn "*anddi3_cconly" | |
ae156f85 | 4930 | [(set (reg CC_REGNUM) |
96fd3851 | 4931 | (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 | 4932 | (match_operand:DI 2 "general_operand" "d,m")) |
9db1d521 HP |
4933 | (const_int 0))) |
4934 | (clobber (match_scratch:DI 0 "=d,d"))] | |
68f9c5e2 UW |
4935 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT |
4936 | /* Do not steal TM patterns. */ | |
4937 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 4938 | "@ |
d40c829f UW |
4939 | ngr\t%0,%2 |
4940 | ng\t%0,%2" | |
d3632d41 | 4941 | [(set_attr "op_type" "RRE,RXY")]) |
9db1d521 | 4942 | |
ec24698e UW |
4943 | (define_insn "*anddi3_extimm" |
4944 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,d,d,AQ,Q") | |
4945 | (and:DI (match_operand:DI 1 "nonimmediate_operand" | |
4946 | "%d,o,0,0,0,0,0,0,0,0,0,0") | |
4947 | (match_operand:DI 2 "general_operand" | |
4948 | "M,M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,m,NxQDF,Q"))) | |
4949 | (clobber (reg:CC CC_REGNUM))] | |
4950 | "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)" | |
4951 | "@ | |
4952 | # | |
4953 | # | |
4954 | nihh\t%0,%j2 | |
4955 | nihl\t%0,%j2 | |
4956 | nilh\t%0,%j2 | |
4957 | nill\t%0,%j2 | |
4958 | nihf\t%0,%m2 | |
4959 | nilf\t%0,%m2 | |
4960 | ngr\t%0,%2 | |
4961 | ng\t%0,%2 | |
4962 | # | |
4963 | #" | |
4964 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")]) | |
4965 | ||
8cb66696 | 4966 | (define_insn "*anddi3" |
0dfa6c5e | 4967 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") |
8cb66696 | 4968 | (and:DI (match_operand:DI 1 "nonimmediate_operand" |
0dfa6c5e | 4969 | "%d,o,0,0,0,0,0,0,0,0") |
8cb66696 | 4970 | (match_operand:DI 2 "general_operand" |
0dfa6c5e | 4971 | "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q"))) |
ae156f85 | 4972 | (clobber (reg:CC CC_REGNUM))] |
ec24698e | 4973 | "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)" |
8cb66696 UW |
4974 | "@ |
4975 | # | |
4976 | # | |
4977 | nihh\t%0,%j2 | |
4978 | nihl\t%0,%j2 | |
4979 | nilh\t%0,%j2 | |
4980 | nill\t%0,%j2 | |
4981 | ngr\t%0,%2 | |
4982 | ng\t%0,%2 | |
0dfa6c5e | 4983 | # |
19b63d8e | 4984 | #" |
0dfa6c5e UW |
4985 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")]) |
4986 | ||
4987 | (define_split | |
4988 | [(set (match_operand:DI 0 "s_operand" "") | |
4989 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 4990 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
4991 | "reload_completed" |
4992 | [(parallel | |
4993 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 4994 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 4995 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 4996 | |
9db1d521 HP |
4997 | |
4998 | ; | |
4999 | ; andsi3 instruction pattern(s). | |
5000 | ; | |
5001 | ||
5002 | (define_insn "*andsi3_cc" | |
ae156f85 | 5003 | [(set (reg CC_REGNUM) |
ec24698e UW |
5004 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5005 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
9db1d521 | 5006 | (const_int 0))) |
ec24698e | 5007 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
9db1d521 HP |
5008 | (and:SI (match_dup 1) (match_dup 2)))] |
5009 | "s390_match_ccmode(insn, CCTmode)" | |
5010 | "@ | |
ec24698e | 5011 | nilf\t%0,%o2 |
d40c829f UW |
5012 | nr\t%0,%2 |
5013 | n\t%0,%2 | |
5014 | ny\t%0,%2" | |
ec24698e | 5015 | [(set_attr "op_type" "RIL,RR,RX,RXY")]) |
9db1d521 HP |
5016 | |
5017 | (define_insn "*andsi3_cconly" | |
ae156f85 | 5018 | [(set (reg CC_REGNUM) |
ec24698e UW |
5019 | (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5020 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
9db1d521 | 5021 | (const_int 0))) |
ec24698e | 5022 | (clobber (match_scratch:SI 0 "=d,d,d,d"))] |
68f9c5e2 UW |
5023 | "s390_match_ccmode(insn, CCTmode) |
5024 | /* Do not steal TM patterns. */ | |
5025 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 5026 | "@ |
ec24698e | 5027 | nilf\t%0,%o2 |
d40c829f UW |
5028 | nr\t%0,%2 |
5029 | n\t%0,%2 | |
5030 | ny\t%0,%2" | |
ec24698e | 5031 | [(set_attr "op_type" "RIL,RR,RX,RXY")]) |
9db1d521 | 5032 | |
f19a9af7 | 5033 | (define_insn "*andsi3_zarch" |
ec24698e | 5034 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") |
0dfa6c5e | 5035 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
ec24698e | 5036 | "%d,o,0,0,0,0,0,0,0,0") |
0dfa6c5e | 5037 | (match_operand:SI 2 "general_operand" |
ec24698e | 5038 | "M,M,N0HSF,N1HSF,Os,d,R,T,NxQSF,Q"))) |
ae156f85 | 5039 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5040 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5041 | "@ |
f19a9af7 AK |
5042 | # |
5043 | # | |
5044 | nilh\t%0,%j2 | |
2f7e5a0d | 5045 | nill\t%0,%j2 |
ec24698e | 5046 | nilf\t%0,%o2 |
d40c829f UW |
5047 | nr\t%0,%2 |
5048 | n\t%0,%2 | |
8cb66696 | 5049 | ny\t%0,%2 |
0dfa6c5e | 5050 | # |
19b63d8e | 5051 | #" |
ec24698e | 5052 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RX,RXY,SI,SS")]) |
f19a9af7 AK |
5053 | |
5054 | (define_insn "*andsi3_esa" | |
0dfa6c5e UW |
5055 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5056 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") | |
5057 | (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q"))) | |
ae156f85 | 5058 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5059 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
5060 | "@ |
5061 | nr\t%0,%2 | |
8cb66696 | 5062 | n\t%0,%2 |
0dfa6c5e | 5063 | # |
19b63d8e | 5064 | #" |
0dfa6c5e UW |
5065 | [(set_attr "op_type" "RR,RX,SI,SS")]) |
5066 | ||
5067 | (define_split | |
5068 | [(set (match_operand:SI 0 "s_operand" "") | |
5069 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 5070 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5071 | "reload_completed" |
5072 | [(parallel | |
5073 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5074 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5075 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 5076 | |
9db1d521 HP |
5077 | ; |
5078 | ; andhi3 instruction pattern(s). | |
5079 | ; | |
5080 | ||
8cb66696 | 5081 | (define_insn "*andhi3_zarch" |
0dfa6c5e UW |
5082 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5083 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
5084 | (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q"))) | |
ae156f85 | 5085 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5086 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5087 | "@ |
d40c829f | 5088 | nr\t%0,%2 |
8cb66696 | 5089 | nill\t%0,%x2 |
0dfa6c5e | 5090 | # |
19b63d8e | 5091 | #" |
0dfa6c5e | 5092 | [(set_attr "op_type" "RR,RI,SI,SS")]) |
8cb66696 UW |
5093 | |
5094 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
5095 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
5096 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
5097 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 5098 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
5099 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
5100 | "@ | |
5101 | nr\t%0,%2 | |
0dfa6c5e | 5102 | # |
19b63d8e | 5103 | #" |
0dfa6c5e UW |
5104 | [(set_attr "op_type" "RR,SI,SS")]) |
5105 | ||
5106 | (define_split | |
5107 | [(set (match_operand:HI 0 "s_operand" "") | |
5108 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 5109 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5110 | "reload_completed" |
5111 | [(parallel | |
5112 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5113 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5114 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 5115 | |
9db1d521 HP |
5116 | ; |
5117 | ; andqi3 instruction pattern(s). | |
5118 | ; | |
5119 | ||
8cb66696 UW |
5120 | (define_insn "*andqi3_zarch" |
5121 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
5122 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5123 | (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
ae156f85 | 5124 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5125 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5126 | "@ |
d40c829f | 5127 | nr\t%0,%2 |
8cb66696 | 5128 | nill\t%0,%b2 |
fc0ea003 UW |
5129 | ni\t%S0,%b2 |
5130 | niy\t%S0,%b2 | |
19b63d8e | 5131 | #" |
8cb66696 UW |
5132 | [(set_attr "op_type" "RR,RI,SI,SIY,SS")]) |
5133 | ||
5134 | (define_insn "*andqi3_esa" | |
5135 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
5136 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
5137 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 5138 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5139 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5140 | "@ |
8cb66696 | 5141 | nr\t%0,%2 |
fc0ea003 | 5142 | ni\t%S0,%b2 |
19b63d8e | 5143 | #" |
8cb66696 | 5144 | [(set_attr "op_type" "RR,SI,SS")]) |
4023fb28 | 5145 | |
19b63d8e UW |
5146 | ; |
5147 | ; Block and (NC) patterns. | |
5148 | ; | |
5149 | ||
5150 | (define_insn "*nc" | |
5151 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5152 | (and:BLK (match_dup 0) | |
5153 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5154 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 5155 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 5156 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 5157 | "nc\t%O0(%2,%R0),%S1" |
b628bd8e | 5158 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5159 | |
5160 | (define_split | |
5161 | [(set (match_operand 0 "memory_operand" "") | |
5162 | (and (match_dup 0) | |
5163 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 5164 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
5165 | "reload_completed |
5166 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5167 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
5168 | [(parallel | |
5169 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
5170 | (use (match_dup 2)) | |
ae156f85 | 5171 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5172 | { |
5173 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
5174 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
5175 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
5176 | }) | |
5177 | ||
5178 | (define_peephole2 | |
5179 | [(parallel | |
5180 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5181 | (and:BLK (match_dup 0) | |
5182 | (match_operand:BLK 1 "memory_operand" ""))) | |
5183 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 5184 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
5185 | (parallel |
5186 | [(set (match_operand:BLK 3 "memory_operand" "") | |
5187 | (and:BLK (match_dup 3) | |
5188 | (match_operand:BLK 4 "memory_operand" ""))) | |
5189 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 5190 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5191 | "s390_offset_p (operands[0], operands[3], operands[2]) |
5192 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
bcf8c1cc AK |
5193 | && !s390_overlap_p (operands[0], operands[1], |
5194 | INTVAL (operands[2]) + INTVAL (operands[5])) | |
19b63d8e UW |
5195 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
5196 | [(parallel | |
5197 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
5198 | (use (match_dup 8)) | |
ae156f85 | 5199 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5200 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
5201 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
5202 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
5203 | ||
9db1d521 HP |
5204 | |
5205 | ;; | |
5206 | ;;- Bit set (inclusive or) instructions. | |
5207 | ;; | |
5208 | ||
047d35ed AS |
5209 | (define_expand "ior<mode>3" |
5210 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
5211 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
5212 | (match_operand:INT 2 "general_operand" ""))) | |
5213 | (clobber (reg:CC CC_REGNUM))] | |
5214 | "" | |
5215 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
5216 | ||
9db1d521 HP |
5217 | ; |
5218 | ; iordi3 instruction pattern(s). | |
5219 | ; | |
5220 | ||
4023fb28 | 5221 | (define_insn "*iordi3_cc" |
ae156f85 | 5222 | [(set (reg CC_REGNUM) |
96fd3851 | 5223 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5224 | (match_operand:DI 2 "general_operand" "d,m")) |
5225 | (const_int 0))) | |
5226 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5227 | (ior:DI (match_dup 1) (match_dup 2)))] | |
5228 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5229 | "@ | |
d40c829f UW |
5230 | ogr\t%0,%2 |
5231 | og\t%0,%2" | |
d3632d41 | 5232 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5233 | |
5234 | (define_insn "*iordi3_cconly" | |
ae156f85 | 5235 | [(set (reg CC_REGNUM) |
96fd3851 | 5236 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5237 | (match_operand:DI 2 "general_operand" "d,m")) |
5238 | (const_int 0))) | |
5239 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5240 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5241 | "@ | |
d40c829f UW |
5242 | ogr\t%0,%2 |
5243 | og\t%0,%2" | |
d3632d41 | 5244 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 5245 | |
ec24698e UW |
5246 | (define_insn "*iordi3_extimm" |
5247 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q") | |
5248 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0,0,0") | |
5249 | (match_operand:DI 2 "general_operand" | |
5250 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,m,NxQD0,Q"))) | |
5251 | (clobber (reg:CC CC_REGNUM))] | |
5252 | "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)" | |
5253 | "@ | |
5254 | oihh\t%0,%i2 | |
5255 | oihl\t%0,%i2 | |
5256 | oilh\t%0,%i2 | |
5257 | oill\t%0,%i2 | |
5258 | oihf\t%0,%k2 | |
5259 | oilf\t%0,%k2 | |
5260 | ogr\t%0,%2 | |
5261 | og\t%0,%2 | |
5262 | # | |
5263 | #" | |
5264 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RXY,SI,SS")]) | |
5265 | ||
8cb66696 | 5266 | (define_insn "*iordi3" |
0dfa6c5e | 5267 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q") |
bad82153 | 5268 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0") |
8cb66696 | 5269 | (match_operand:DI 2 "general_operand" |
0dfa6c5e | 5270 | "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q"))) |
ae156f85 | 5271 | (clobber (reg:CC CC_REGNUM))] |
ec24698e | 5272 | "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5273 | "@ |
f19a9af7 AK |
5274 | oihh\t%0,%i2 |
5275 | oihl\t%0,%i2 | |
5276 | oilh\t%0,%i2 | |
5277 | oill\t%0,%i2 | |
d40c829f | 5278 | ogr\t%0,%2 |
8cb66696 | 5279 | og\t%0,%2 |
0dfa6c5e | 5280 | # |
19b63d8e | 5281 | #" |
0dfa6c5e UW |
5282 | [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")]) |
5283 | ||
5284 | (define_split | |
5285 | [(set (match_operand:DI 0 "s_operand" "") | |
5286 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 5287 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5288 | "reload_completed" |
5289 | [(parallel | |
5290 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5291 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5292 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 5293 | |
9db1d521 HP |
5294 | ; |
5295 | ; iorsi3 instruction pattern(s). | |
5296 | ; | |
5297 | ||
4023fb28 | 5298 | (define_insn "*iorsi3_cc" |
ae156f85 | 5299 | [(set (reg CC_REGNUM) |
ec24698e UW |
5300 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5301 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
4023fb28 | 5302 | (const_int 0))) |
ec24698e | 5303 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4023fb28 UW |
5304 | (ior:SI (match_dup 1) (match_dup 2)))] |
5305 | "s390_match_ccmode(insn, CCTmode)" | |
5306 | "@ | |
ec24698e | 5307 | oilf\t%0,%o2 |
d40c829f UW |
5308 | or\t%0,%2 |
5309 | o\t%0,%2 | |
5310 | oy\t%0,%2" | |
ec24698e | 5311 | [(set_attr "op_type" "RIL,RR,RX,RXY")]) |
4023fb28 UW |
5312 | |
5313 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 5314 | [(set (reg CC_REGNUM) |
ec24698e UW |
5315 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5316 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
4023fb28 | 5317 | (const_int 0))) |
ec24698e | 5318 | (clobber (match_scratch:SI 0 "=d,d,d,d"))] |
4023fb28 UW |
5319 | "s390_match_ccmode(insn, CCTmode)" |
5320 | "@ | |
ec24698e | 5321 | oilf\t%0,%o2 |
d40c829f UW |
5322 | or\t%0,%2 |
5323 | o\t%0,%2 | |
5324 | oy\t%0,%2" | |
ec24698e | 5325 | [(set_attr "op_type" "RIL,RR,RX,RXY")]) |
4023fb28 | 5326 | |
8cb66696 | 5327 | (define_insn "*iorsi3_zarch" |
ec24698e UW |
5328 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q") |
5329 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0") | |
5330 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,R,T,NxQS0,Q"))) | |
ae156f85 | 5331 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5332 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5333 | "@ |
f19a9af7 AK |
5334 | oilh\t%0,%i2 |
5335 | oill\t%0,%i2 | |
ec24698e | 5336 | oilf\t%0,%o2 |
d40c829f UW |
5337 | or\t%0,%2 |
5338 | o\t%0,%2 | |
8cb66696 | 5339 | oy\t%0,%2 |
0dfa6c5e | 5340 | # |
19b63d8e | 5341 | #" |
ec24698e | 5342 | [(set_attr "op_type" "RI,RI,RIL,RR,RX,RXY,SI,SS")]) |
8cb66696 UW |
5343 | |
5344 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 5345 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 5346 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 5347 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 5348 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5349 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
5350 | "@ |
5351 | or\t%0,%2 | |
8cb66696 | 5352 | o\t%0,%2 |
0dfa6c5e | 5353 | # |
19b63d8e | 5354 | #" |
0dfa6c5e UW |
5355 | [(set_attr "op_type" "RR,RX,SI,SS")]) |
5356 | ||
5357 | (define_split | |
5358 | [(set (match_operand:SI 0 "s_operand" "") | |
5359 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 5360 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5361 | "reload_completed" |
5362 | [(parallel | |
5363 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5364 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5365 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 5366 | |
4023fb28 UW |
5367 | ; |
5368 | ; iorhi3 instruction pattern(s). | |
5369 | ; | |
5370 | ||
8cb66696 | 5371 | (define_insn "*iorhi3_zarch" |
0dfa6c5e UW |
5372 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5373 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
5374 | (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q"))) | |
ae156f85 | 5375 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5376 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5377 | "@ |
d40c829f | 5378 | or\t%0,%2 |
8cb66696 | 5379 | oill\t%0,%x2 |
0dfa6c5e | 5380 | # |
19b63d8e | 5381 | #" |
0dfa6c5e | 5382 | [(set_attr "op_type" "RR,RI,SI,SS")]) |
8cb66696 UW |
5383 | |
5384 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
5385 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
5386 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
5387 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 5388 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
5389 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
5390 | "@ | |
5391 | or\t%0,%2 | |
0dfa6c5e | 5392 | # |
19b63d8e | 5393 | #" |
0dfa6c5e UW |
5394 | [(set_attr "op_type" "RR,SI,SS")]) |
5395 | ||
5396 | (define_split | |
5397 | [(set (match_operand:HI 0 "s_operand" "") | |
5398 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 5399 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5400 | "reload_completed" |
5401 | [(parallel | |
5402 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5403 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5404 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 5405 | |
9db1d521 | 5406 | ; |
4023fb28 | 5407 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
5408 | ; |
5409 | ||
8cb66696 UW |
5410 | (define_insn "*iorqi3_zarch" |
5411 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") | |
5412 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5413 | (match_operand:QI 2 "general_operand" "d,n,n,n,Q"))) | |
ae156f85 | 5414 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5415 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 5416 | "@ |
d40c829f | 5417 | or\t%0,%2 |
8cb66696 | 5418 | oill\t%0,%b2 |
fc0ea003 UW |
5419 | oi\t%S0,%b2 |
5420 | oiy\t%S0,%b2 | |
19b63d8e | 5421 | #" |
8cb66696 UW |
5422 | [(set_attr "op_type" "RR,RI,SI,SIY,SS")]) |
5423 | ||
5424 | (define_insn "*iorqi3_esa" | |
5425 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
5426 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
5427 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 5428 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5429 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5430 | "@ |
8cb66696 | 5431 | or\t%0,%2 |
fc0ea003 | 5432 | oi\t%S0,%b2 |
19b63d8e | 5433 | #" |
8cb66696 | 5434 | [(set_attr "op_type" "RR,SI,SS")]) |
9db1d521 | 5435 | |
19b63d8e UW |
5436 | ; |
5437 | ; Block inclusive or (OC) patterns. | |
5438 | ; | |
5439 | ||
5440 | (define_insn "*oc" | |
5441 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5442 | (ior:BLK (match_dup 0) | |
5443 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5444 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 5445 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 5446 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 5447 | "oc\t%O0(%2,%R0),%S1" |
b628bd8e | 5448 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5449 | |
5450 | (define_split | |
5451 | [(set (match_operand 0 "memory_operand" "") | |
5452 | (ior (match_dup 0) | |
5453 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 5454 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
5455 | "reload_completed |
5456 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5457 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
5458 | [(parallel | |
5459 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
5460 | (use (match_dup 2)) | |
ae156f85 | 5461 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5462 | { |
5463 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
5464 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
5465 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
5466 | }) | |
5467 | ||
5468 | (define_peephole2 | |
5469 | [(parallel | |
5470 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5471 | (ior:BLK (match_dup 0) | |
5472 | (match_operand:BLK 1 "memory_operand" ""))) | |
5473 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 5474 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
5475 | (parallel |
5476 | [(set (match_operand:BLK 3 "memory_operand" "") | |
5477 | (ior:BLK (match_dup 3) | |
5478 | (match_operand:BLK 4 "memory_operand" ""))) | |
5479 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 5480 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5481 | "s390_offset_p (operands[0], operands[3], operands[2]) |
5482 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
bcf8c1cc AK |
5483 | && !s390_overlap_p (operands[0], operands[1], |
5484 | INTVAL (operands[2]) + INTVAL (operands[5])) | |
19b63d8e UW |
5485 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
5486 | [(parallel | |
5487 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
5488 | (use (match_dup 8)) | |
ae156f85 | 5489 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5490 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
5491 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
5492 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
5493 | ||
9db1d521 HP |
5494 | |
5495 | ;; | |
5496 | ;;- Xor instructions. | |
5497 | ;; | |
5498 | ||
047d35ed AS |
5499 | (define_expand "xor<mode>3" |
5500 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
5501 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
5502 | (match_operand:INT 2 "general_operand" ""))) | |
5503 | (clobber (reg:CC CC_REGNUM))] | |
5504 | "" | |
5505 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
5506 | ||
9db1d521 HP |
5507 | ; |
5508 | ; xordi3 instruction pattern(s). | |
5509 | ; | |
5510 | ||
4023fb28 | 5511 | (define_insn "*xordi3_cc" |
ae156f85 | 5512 | [(set (reg CC_REGNUM) |
96fd3851 | 5513 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5514 | (match_operand:DI 2 "general_operand" "d,m")) |
5515 | (const_int 0))) | |
5516 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5517 | (xor:DI (match_dup 1) (match_dup 2)))] | |
5518 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5519 | "@ | |
d40c829f UW |
5520 | xgr\t%0,%2 |
5521 | xg\t%0,%2" | |
d3632d41 | 5522 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 UW |
5523 | |
5524 | (define_insn "*xordi3_cconly" | |
ae156f85 | 5525 | [(set (reg CC_REGNUM) |
96fd3851 | 5526 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0") |
4023fb28 UW |
5527 | (match_operand:DI 2 "general_operand" "d,m")) |
5528 | (const_int 0))) | |
5529 | (clobber (match_scratch:DI 0 "=d,d"))] | |
5530 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
5531 | "@ | |
d40c829f UW |
5532 | xgr\t%0,%2 |
5533 | xr\t%0,%2" | |
d3632d41 | 5534 | [(set_attr "op_type" "RRE,RXY")]) |
4023fb28 | 5535 | |
ec24698e UW |
5536 | (define_insn "*xordi3_extimm" |
5537 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") | |
5538 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0") | |
5539 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,m,NxQD0,Q"))) | |
5540 | (clobber (reg:CC CC_REGNUM))] | |
5541 | "TARGET_64BIT && TARGET_EXTIMM && s390_logical_operator_ok_p (operands)" | |
5542 | "@ | |
5543 | xihf\t%0,%k2 | |
5544 | xilf\t%0,%k2 | |
5545 | xgr\t%0,%2 | |
5546 | xg\t%0,%2 | |
5547 | # | |
5548 | #" | |
5549 | [(set_attr "op_type" "RIL,RIL,RRE,RXY,SI,SS")]) | |
5550 | ||
8cb66696 | 5551 | (define_insn "*xordi3" |
0dfa6c5e UW |
5552 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5553 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
5554 | (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q"))) | |
ae156f85 | 5555 | (clobber (reg:CC CC_REGNUM))] |
ec24698e | 5556 | "TARGET_64BIT && !TARGET_EXTIMM && s390_logical_operator_ok_p (operands)" |
9db1d521 | 5557 | "@ |
d40c829f | 5558 | xgr\t%0,%2 |
8cb66696 | 5559 | xg\t%0,%2 |
0dfa6c5e | 5560 | # |
19b63d8e | 5561 | #" |
0dfa6c5e UW |
5562 | [(set_attr "op_type" "RRE,RXY,SI,SS")]) |
5563 | ||
5564 | (define_split | |
5565 | [(set (match_operand:DI 0 "s_operand" "") | |
5566 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 5567 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5568 | "reload_completed" |
5569 | [(parallel | |
5570 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5571 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5572 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 5573 | |
9db1d521 HP |
5574 | ; |
5575 | ; xorsi3 instruction pattern(s). | |
5576 | ; | |
5577 | ||
4023fb28 | 5578 | (define_insn "*xorsi3_cc" |
ae156f85 | 5579 | [(set (reg CC_REGNUM) |
ec24698e UW |
5580 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5581 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
4023fb28 | 5582 | (const_int 0))) |
ec24698e | 5583 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4023fb28 UW |
5584 | (xor:SI (match_dup 1) (match_dup 2)))] |
5585 | "s390_match_ccmode(insn, CCTmode)" | |
5586 | "@ | |
ec24698e | 5587 | xilf\t%0,%o2 |
d40c829f UW |
5588 | xr\t%0,%2 |
5589 | x\t%0,%2 | |
5590 | xy\t%0,%2" | |
ec24698e | 5591 | [(set_attr "op_type" "RIL,RR,RX,RXY")]) |
4023fb28 UW |
5592 | |
5593 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 5594 | [(set (reg CC_REGNUM) |
ec24698e UW |
5595 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
5596 | (match_operand:SI 2 "general_operand" "Os,d,R,T")) | |
4023fb28 | 5597 | (const_int 0))) |
ec24698e | 5598 | (clobber (match_scratch:SI 0 "=d,d,d,d"))] |
4023fb28 UW |
5599 | "s390_match_ccmode(insn, CCTmode)" |
5600 | "@ | |
ec24698e | 5601 | xilf\t%0,%o2 |
d40c829f UW |
5602 | xr\t%0,%2 |
5603 | x\t%0,%2 | |
5604 | xy\t%0,%2" | |
ec24698e | 5605 | [(set_attr "op_type" "RIL,RR,RX,RXY")]) |
9db1d521 | 5606 | |
8cb66696 | 5607 | (define_insn "*xorsi3" |
ec24698e UW |
5608 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,AQ,Q") |
5609 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0") | |
5610 | (match_operand:SI 2 "general_operand" "Os,d,R,T,NxQS0,Q"))) | |
ae156f85 | 5611 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5612 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 5613 | "@ |
ec24698e | 5614 | xilf\t%0,%o2 |
d40c829f UW |
5615 | xr\t%0,%2 |
5616 | x\t%0,%2 | |
8cb66696 | 5617 | xy\t%0,%2 |
0dfa6c5e | 5618 | # |
19b63d8e | 5619 | #" |
ec24698e | 5620 | [(set_attr "op_type" "RIL,RR,RX,RXY,SI,SS")]) |
0dfa6c5e UW |
5621 | |
5622 | (define_split | |
5623 | [(set (match_operand:SI 0 "s_operand" "") | |
5624 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 5625 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5626 | "reload_completed" |
5627 | [(parallel | |
5628 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5629 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5630 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 5631 | |
9db1d521 HP |
5632 | ; |
5633 | ; xorhi3 instruction pattern(s). | |
5634 | ; | |
5635 | ||
8cb66696 | 5636 | (define_insn "*xorhi3" |
ec24698e UW |
5637 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
5638 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0") | |
5639 | (match_operand:HI 2 "general_operand" "Os,d,NxQH0,Q"))) | |
ae156f85 | 5640 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
5641 | "s390_logical_operator_ok_p (operands)" |
5642 | "@ | |
ec24698e | 5643 | xilf\t%0,%x2 |
8cb66696 | 5644 | xr\t%0,%2 |
0dfa6c5e | 5645 | # |
19b63d8e | 5646 | #" |
ec24698e | 5647 | [(set_attr "op_type" "RIL,RR,SI,SS")]) |
0dfa6c5e UW |
5648 | |
5649 | (define_split | |
5650 | [(set (match_operand:HI 0 "s_operand" "") | |
5651 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 5652 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
5653 | "reload_completed" |
5654 | [(parallel | |
5655 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 5656 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 5657 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 5658 | |
9db1d521 HP |
5659 | ; |
5660 | ; xorqi3 instruction pattern(s). | |
5661 | ; | |
5662 | ||
8cb66696 | 5663 | (define_insn "*xorqi3" |
ec24698e UW |
5664 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q") |
5665 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
5666 | (match_operand:QI 2 "general_operand" "Os,d,n,n,Q"))) | |
ae156f85 | 5667 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 5668 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 5669 | "@ |
ec24698e | 5670 | xilf\t%0,%b2 |
8cb66696 | 5671 | xr\t%0,%2 |
fc0ea003 UW |
5672 | xi\t%S0,%b2 |
5673 | xiy\t%S0,%b2 | |
19b63d8e | 5674 | #" |
ec24698e | 5675 | [(set_attr "op_type" "RIL,RR,SI,SIY,SS")]) |
4023fb28 | 5676 | |
19b63d8e UW |
5677 | ; |
5678 | ; Block exclusive or (XC) patterns. | |
5679 | ; | |
5680 | ||
5681 | (define_insn "*xc" | |
5682 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5683 | (xor:BLK (match_dup 0) | |
5684 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
5685 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 5686 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 5687 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 5688 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 5689 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5690 | |
5691 | (define_split | |
5692 | [(set (match_operand 0 "memory_operand" "") | |
5693 | (xor (match_dup 0) | |
5694 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 5695 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
5696 | "reload_completed |
5697 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
5698 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
5699 | [(parallel | |
5700 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
5701 | (use (match_dup 2)) | |
ae156f85 | 5702 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5703 | { |
5704 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
5705 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
5706 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
5707 | }) | |
5708 | ||
5709 | (define_peephole2 | |
5710 | [(parallel | |
5711 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5712 | (xor:BLK (match_dup 0) | |
5713 | (match_operand:BLK 1 "memory_operand" ""))) | |
5714 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 5715 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
5716 | (parallel |
5717 | [(set (match_operand:BLK 3 "memory_operand" "") | |
5718 | (xor:BLK (match_dup 3) | |
5719 | (match_operand:BLK 4 "memory_operand" ""))) | |
5720 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 5721 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5722 | "s390_offset_p (operands[0], operands[3], operands[2]) |
5723 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
bcf8c1cc AK |
5724 | && !s390_overlap_p (operands[0], operands[1], |
5725 | INTVAL (operands[2]) + INTVAL (operands[5])) | |
19b63d8e UW |
5726 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
5727 | [(parallel | |
5728 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
5729 | (use (match_dup 8)) | |
ae156f85 | 5730 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5731 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
5732 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
5733 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
5734 | ||
5735 | ; | |
5736 | ; Block xor (XC) patterns with src == dest. | |
5737 | ; | |
5738 | ||
5739 | (define_insn "*xc_zero" | |
5740 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
5741 | (const_int 0)) | |
5742 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 5743 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 5744 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 5745 | "xc\t%O0(%1,%R0),%S0" |
b628bd8e | 5746 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
5747 | |
5748 | (define_peephole2 | |
5749 | [(parallel | |
5750 | [(set (match_operand:BLK 0 "memory_operand" "") | |
5751 | (const_int 0)) | |
5752 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 5753 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
5754 | (parallel |
5755 | [(set (match_operand:BLK 2 "memory_operand" "") | |
5756 | (const_int 0)) | |
5757 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 5758 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5759 | "s390_offset_p (operands[0], operands[2], operands[1]) |
5760 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
5761 | [(parallel | |
5762 | [(set (match_dup 4) (const_int 0)) | |
5763 | (use (match_dup 5)) | |
ae156f85 | 5764 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
5765 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
5766 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
5767 | ||
9db1d521 HP |
5768 | |
5769 | ;; | |
5770 | ;;- Negate instructions. | |
5771 | ;; | |
5772 | ||
5773 | ; | |
9a91a21f | 5774 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
5775 | ; |
5776 | ||
9a91a21f | 5777 | (define_expand "neg<mode>2" |
9db1d521 | 5778 | [(parallel |
9a91a21f AS |
5779 | [(set (match_operand:DSI 0 "register_operand" "=d") |
5780 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 5781 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
5782 | "" |
5783 | "") | |
5784 | ||
26a89301 | 5785 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 5786 | [(set (reg CC_REGNUM) |
26a89301 UW |
5787 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
5788 | (match_operand:SI 1 "register_operand" "d") 0) | |
5789 | (const_int 32)) (const_int 32))) | |
5790 | (const_int 0))) | |
5791 | (set (match_operand:DI 0 "register_operand" "=d") | |
5792 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
5793 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
5794 | "lcgfr\t%0,%1" | |
5795 | [(set_attr "op_type" "RRE")]) | |
5796 | ||
5797 | (define_insn "*negdi2_sign" | |
5798 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5799 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 5800 | (clobber (reg:CC CC_REGNUM))] |
26a89301 UW |
5801 | "TARGET_64BIT" |
5802 | "lcgfr\t%0,%1" | |
5803 | [(set_attr "op_type" "RRE")]) | |
5804 | ||
9a91a21f | 5805 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 5806 | [(set (reg CC_REGNUM) |
9a91a21f | 5807 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 5808 | (const_int 0))) |
9a91a21f AS |
5809 | (set (match_operand:GPR 0 "register_operand" "=d") |
5810 | (neg:GPR (match_dup 1)))] | |
5811 | "s390_match_ccmode (insn, CCAmode)" | |
5812 | "lc<g>r\t%0,%1" | |
5813 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 5814 | |
9a91a21f | 5815 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 5816 | [(set (reg CC_REGNUM) |
9a91a21f | 5817 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 5818 | (const_int 0))) |
9a91a21f AS |
5819 | (clobber (match_scratch:GPR 0 "=d"))] |
5820 | "s390_match_ccmode (insn, CCAmode)" | |
5821 | "lc<g>r\t%0,%1" | |
5822 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 5823 | |
9a91a21f AS |
5824 | (define_insn "*neg<mode>2" |
5825 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5826 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 5827 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
5828 | "" |
5829 | "lc<g>r\t%0,%1" | |
5830 | [(set_attr "op_type" "RR<E>")]) | |
9db1d521 | 5831 | |
26a89301 | 5832 | (define_insn_and_split "*negdi2_31" |
9db1d521 HP |
5833 | [(set (match_operand:DI 0 "register_operand" "=d") |
5834 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 5835 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 5836 | "!TARGET_64BIT" |
26a89301 UW |
5837 | "#" |
5838 | "&& reload_completed" | |
5839 | [(parallel | |
5840 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 5841 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 5842 | (parallel |
ae156f85 | 5843 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
5844 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
5845 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
5846 | (set (pc) | |
ae156f85 | 5847 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
5848 | (pc) |
5849 | (label_ref (match_dup 6)))) | |
5850 | (parallel | |
5851 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 5852 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
5853 | (match_dup 6)] |
5854 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
5855 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
5856 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
5857 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
5858 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 5859 | |
9db1d521 | 5860 | ; |
f5905b37 | 5861 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
5862 | ; |
5863 | ||
f5905b37 | 5864 | (define_expand "neg<mode>2" |
9db1d521 | 5865 | [(parallel |
f5905b37 AS |
5866 | [(set (match_operand:FPR 0 "register_operand" "=f") |
5867 | (neg:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 5868 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
5869 | "TARGET_HARD_FLOAT" |
5870 | "") | |
5871 | ||
f5905b37 | 5872 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 5873 | [(set (reg CC_REGNUM) |
f5905b37 AS |
5874 | (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f")) |
5875 | (match_operand:FPR 2 "const0_operand" ""))) | |
5876 | (set (match_operand:FPR 0 "register_operand" "=f") | |
5877 | (neg:FPR (match_dup 1)))] | |
26a89301 | 5878 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 5879 | "lc<de>br\t%0,%1" |
26a89301 | 5880 | [(set_attr "op_type" "RRE") |
f5905b37 | 5881 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 5882 | |
f5905b37 | 5883 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 5884 | [(set (reg CC_REGNUM) |
f5905b37 AS |
5885 | (compare (neg:FPR (match_operand:FPR 1 "register_operand" "f")) |
5886 | (match_operand:FPR 2 "const0_operand" ""))) | |
5887 | (clobber (match_scratch:FPR 0 "=f"))] | |
26a89301 | 5888 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 5889 | "lc<de>br\t%0,%1" |
26a89301 | 5890 | [(set_attr "op_type" "RRE") |
f5905b37 | 5891 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 5892 | |
f5905b37 AS |
5893 | (define_insn "*neg<mode>2" |
5894 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
5895 | (neg:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 5896 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 5897 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 5898 | "lc<de>br\t%0,%1" |
077dab3b | 5899 | [(set_attr "op_type" "RRE") |
f5905b37 | 5900 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 5901 | |
f5905b37 AS |
5902 | (define_insn "*neg<mode>2_ibm" |
5903 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
5904 | (neg:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 5905 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 5906 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
f5905b37 | 5907 | "lc<de>r\t%0,%1" |
077dab3b | 5908 | [(set_attr "op_type" "RR") |
f5905b37 | 5909 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 HP |
5910 | |
5911 | ||
5912 | ;; | |
5913 | ;;- Absolute value instructions. | |
5914 | ;; | |
5915 | ||
5916 | ; | |
9a91a21f | 5917 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
5918 | ; |
5919 | ||
26a89301 | 5920 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 5921 | [(set (reg CC_REGNUM) |
26a89301 UW |
5922 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
5923 | (match_operand:SI 1 "register_operand" "d") 0) | |
5924 | (const_int 32)) (const_int 32))) | |
5925 | (const_int 0))) | |
5926 | (set (match_operand:DI 0 "register_operand" "=d") | |
5927 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
5928 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
5929 | "lpgfr\t%0,%1" | |
5930 | [(set_attr "op_type" "RRE")]) | |
5931 | ||
5932 | (define_insn "*absdi2_sign" | |
5933 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5934 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 5935 | (clobber (reg:CC CC_REGNUM))] |
26a89301 UW |
5936 | "TARGET_64BIT" |
5937 | "lpgfr\t%0,%1" | |
5938 | [(set_attr "op_type" "RRE")]) | |
5939 | ||
9a91a21f | 5940 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 5941 | [(set (reg CC_REGNUM) |
9a91a21f | 5942 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 5943 | (const_int 0))) |
9a91a21f AS |
5944 | (set (match_operand:GPR 0 "register_operand" "=d") |
5945 | (abs:GPR (match_dup 1)))] | |
26a89301 | 5946 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f AS |
5947 | "lp<g>r\t%0,%1" |
5948 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 5949 | |
9a91a21f | 5950 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 5951 | [(set (reg CC_REGNUM) |
9a91a21f | 5952 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 5953 | (const_int 0))) |
9a91a21f | 5954 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 5955 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f AS |
5956 | "lp<g>r\t%0,%1" |
5957 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 5958 | |
9a91a21f AS |
5959 | (define_insn "abs<mode>2" |
5960 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5961 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 5962 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 5963 | "" |
9a91a21f AS |
5964 | "lp<g>r\t%0,%1" |
5965 | [(set_attr "op_type" "RR<E>")]) | |
9db1d521 | 5966 | |
9db1d521 | 5967 | ; |
f5905b37 | 5968 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
5969 | ; |
5970 | ||
f5905b37 | 5971 | (define_expand "abs<mode>2" |
9db1d521 | 5972 | [(parallel |
f5905b37 AS |
5973 | [(set (match_operand:FPR 0 "register_operand" "=f") |
5974 | (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 5975 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
5976 | "TARGET_HARD_FLOAT" |
5977 | "") | |
5978 | ||
f5905b37 | 5979 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 5980 | [(set (reg CC_REGNUM) |
f5905b37 AS |
5981 | (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f")) |
5982 | (match_operand:FPR 2 "const0_operand" ""))) | |
5983 | (set (match_operand:FPR 0 "register_operand" "=f") | |
5984 | (abs:FPR (match_dup 1)))] | |
26a89301 | 5985 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 5986 | "lp<de>br\t%0,%1" |
26a89301 | 5987 | [(set_attr "op_type" "RRE") |
f5905b37 | 5988 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 5989 | |
f5905b37 | 5990 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 5991 | [(set (reg CC_REGNUM) |
f5905b37 AS |
5992 | (compare (abs:FPR (match_operand:FPR 1 "register_operand" "f")) |
5993 | (match_operand:FPR 2 "const0_operand" ""))) | |
5994 | (clobber (match_scratch:FPR 0 "=f"))] | |
26a89301 | 5995 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 5996 | "lp<de>br\t%0,%1" |
26a89301 | 5997 | [(set_attr "op_type" "RRE") |
f5905b37 | 5998 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 5999 | |
f5905b37 AS |
6000 | (define_insn "*abs<mode>2" |
6001 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
6002 | (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 6003 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 6004 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 6005 | "lp<de>br\t%0,%1" |
077dab3b | 6006 | [(set_attr "op_type" "RRE") |
f5905b37 | 6007 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 6008 | |
f5905b37 AS |
6009 | (define_insn "*abs<mode>2_ibm" |
6010 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
6011 | (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) | |
ae156f85 | 6012 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 6013 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
f5905b37 | 6014 | "lp<de>r\t%0,%1" |
077dab3b | 6015 | [(set_attr "op_type" "RR") |
f5905b37 | 6016 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 6017 | |
3ef093a8 AK |
6018 | ;; |
6019 | ;;- Negated absolute value instructions | |
6020 | ;; | |
6021 | ||
6022 | ; | |
6023 | ; Integer | |
6024 | ; | |
6025 | ||
26a89301 | 6026 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 6027 | [(set (reg CC_REGNUM) |
26a89301 UW |
6028 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
6029 | (match_operand:SI 1 "register_operand" "d") 0) | |
6030 | (const_int 32)) (const_int 32)))) | |
6031 | (const_int 0))) | |
6032 | (set (match_operand:DI 0 "register_operand" "=d") | |
6033 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
6034 | "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)" | |
6035 | "lngfr\t%0,%1" | |
6036 | [(set_attr "op_type" "RRE")]) | |
6037 | ||
6038 | (define_insn "*negabsdi2_sign" | |
6039 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6040 | (neg:DI (abs:DI (sign_extend:DI | |
6041 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 6042 | (clobber (reg:CC CC_REGNUM))] |
26a89301 UW |
6043 | "TARGET_64BIT" |
6044 | "lngfr\t%0,%1" | |
6045 | [(set_attr "op_type" "RRE")]) | |
3ef093a8 | 6046 | |
9a91a21f | 6047 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 6048 | [(set (reg CC_REGNUM) |
9a91a21f | 6049 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 6050 | (const_int 0))) |
9a91a21f AS |
6051 | (set (match_operand:GPR 0 "register_operand" "=d") |
6052 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 6053 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f AS |
6054 | "ln<g>r\t%0,%1" |
6055 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 6056 | |
9a91a21f | 6057 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 6058 | [(set (reg CC_REGNUM) |
9a91a21f | 6059 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 6060 | (const_int 0))) |
9a91a21f | 6061 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 6062 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f AS |
6063 | "ln<g>r\t%0,%1" |
6064 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 6065 | |
9a91a21f AS |
6066 | (define_insn "*negabs<mode>2" |
6067 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6068 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 6069 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 6070 | "" |
9a91a21f AS |
6071 | "ln<g>r\t%0,%1" |
6072 | [(set_attr "op_type" "RR<E>")]) | |
26a89301 | 6073 | |
3ef093a8 AK |
6074 | ; |
6075 | ; Floating point | |
6076 | ; | |
6077 | ||
f5905b37 | 6078 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 6079 | [(set (reg CC_REGNUM) |
f5905b37 AS |
6080 | (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) |
6081 | (match_operand:FPR 2 "const0_operand" ""))) | |
6082 | (set (match_operand:FPR 0 "register_operand" "=f") | |
6083 | (neg:FPR (abs:FPR (match_dup 1))))] | |
26a89301 | 6084 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 6085 | "ln<de>br\t%0,%1" |
26a89301 | 6086 | [(set_attr "op_type" "RRE") |
f5905b37 | 6087 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 6088 | |
f5905b37 | 6089 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 6090 | [(set (reg CC_REGNUM) |
f5905b37 AS |
6091 | (compare (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f"))) |
6092 | (match_operand:FPR 2 "const0_operand" ""))) | |
6093 | (clobber (match_scratch:FPR 0 "=f"))] | |
26a89301 | 6094 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 6095 | "ln<de>br\t%0,%1" |
26a89301 | 6096 | [(set_attr "op_type" "RRE") |
f5905b37 | 6097 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 6098 | |
f5905b37 AS |
6099 | (define_insn "*negabs<mode>2" |
6100 | [(set (match_operand:FPR 0 "register_operand" "=f") | |
6101 | (neg:FPR (abs:FPR (match_operand:FPR 1 "register_operand" "f")))) | |
ae156f85 | 6102 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 6103 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
f5905b37 | 6104 | "ln<de>br\t%0,%1" |
26a89301 | 6105 | [(set_attr "op_type" "RRE") |
f5905b37 | 6106 | (set_attr "type" "fsimp<mode>")]) |
26a89301 | 6107 | |
4023fb28 UW |
6108 | ;; |
6109 | ;;- Square root instructions. | |
6110 | ;; | |
6111 | ||
6112 | ; | |
f5905b37 | 6113 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
6114 | ; |
6115 | ||
f5905b37 AS |
6116 | (define_insn "sqrt<mode>2" |
6117 | [(set (match_operand:FPR 0 "register_operand" "=f,f") | |
6118 | (sqrt:FPR (match_operand:FPR 1 "general_operand" "f,R")))] | |
4023fb28 UW |
6119 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
6120 | "@ | |
f5905b37 AS |
6121 | sq<de>br\t%0,%1 |
6122 | sq<de>b\t%0,%1" | |
a036c6f7 | 6123 | [(set_attr "op_type" "RRE,RXE") |
f5905b37 | 6124 | (set_attr "type" "fsqrt<mode>")]) |
4023fb28 | 6125 | |
9db1d521 HP |
6126 | |
6127 | ;; | |
6128 | ;;- One complement instructions. | |
6129 | ;; | |
6130 | ||
6131 | ; | |
342cf42b | 6132 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 6133 | ; |
c7453384 | 6134 | |
342cf42b | 6135 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 6136 | [(parallel |
342cf42b AS |
6137 | [(set (match_operand:INT 0 "register_operand" "") |
6138 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
6139 | (const_int -1))) | |
ae156f85 | 6140 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 6141 | "" |
4023fb28 | 6142 | "") |
9db1d521 HP |
6143 | |
6144 | ||
ec24698e UW |
6145 | ;; |
6146 | ;; Find leftmost bit instructions. | |
6147 | ;; | |
6148 | ||
6149 | (define_expand "clzdi2" | |
6150 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6151 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
6152 | "TARGET_EXTIMM && TARGET_64BIT" | |
6153 | { | |
6154 | rtx insn, clz_equal; | |
6155 | rtx wide_reg = gen_reg_rtx (TImode); | |
6156 | rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63); | |
6157 | ||
6158 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
6159 | ||
6160 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
6161 | ||
6162 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); | |
6163 | REG_NOTES (insn) = | |
6164 | gen_rtx_EXPR_LIST (REG_EQUAL, clz_equal, REG_NOTES (insn)); | |
6165 | ||
6166 | DONE; | |
6167 | }) | |
6168 | ||
6169 | (define_insn "clztidi2" | |
6170 | [(set (match_operand:TI 0 "register_operand" "=d") | |
6171 | (ior:TI | |
6172 | (ashift:TI | |
6173 | (zero_extend:TI | |
6174 | (xor:DI (match_operand:DI 1 "register_operand" "d") | |
6175 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
6176 | (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
6177 | ||
6178 | (const_int 64)) | |
6179 | (zero_extend:TI (clz:DI (match_dup 1))))) | |
6180 | (clobber (reg:CC CC_REGNUM))] | |
6181 | "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) | |
6182 | == (unsigned HOST_WIDE_INT) 1 << 63 | |
6183 | && TARGET_EXTIMM && TARGET_64BIT" | |
6184 | "flogr\t%0,%1" | |
6185 | [(set_attr "op_type" "RRE")]) | |
6186 | ||
6187 | ||
9db1d521 HP |
6188 | ;; |
6189 | ;;- Rotate instructions. | |
6190 | ;; | |
6191 | ||
6192 | ; | |
9a91a21f | 6193 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
6194 | ; |
6195 | ||
9a91a21f AS |
6196 | (define_insn "rotl<mode>3" |
6197 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6198 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
4989e88a | 6199 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9e8327e3 | 6200 | "TARGET_CPU_ZARCH" |
9a91a21f | 6201 | "rll<g>\t%0,%1,%Y2" |
077dab3b HP |
6202 | [(set_attr "op_type" "RSE") |
6203 | (set_attr "atype" "reg")]) | |
9db1d521 | 6204 | |
4989e88a AK |
6205 | (define_insn "*rotl<mode>3_and" |
6206 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6207 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
6208 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
6209 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
6210 | "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63" | |
6211 | "rll<g>\t%0,%1,%Y2" | |
6212 | [(set_attr "op_type" "RSE") | |
6213 | (set_attr "atype" "reg")]) | |
6214 | ||
9db1d521 HP |
6215 | |
6216 | ;; | |
f337b930 | 6217 | ;;- Shift instructions. |
9db1d521 | 6218 | ;; |
9db1d521 HP |
6219 | |
6220 | ; | |
1b48c8cc | 6221 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
9db1d521 HP |
6222 | ; |
6223 | ||
1b48c8cc AS |
6224 | (define_expand "<shift><mode>3" |
6225 | [(set (match_operand:DSI 0 "register_operand" "") | |
6226 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
6227 | (match_operand:SI 2 "shift_count_or_setmem_operand" "")))] | |
9db1d521 HP |
6228 | "" |
6229 | "") | |
6230 | ||
f337b930 | 6231 | (define_insn "*<shift>di3_31" |
ac32b25e | 6232 | [(set (match_operand:DI 0 "register_operand" "=d") |
f337b930 | 6233 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 6234 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9db1d521 | 6235 | "!TARGET_64BIT" |
f337b930 | 6236 | "s<lr>dl\t%0,%Y2" |
077dab3b HP |
6237 | [(set_attr "op_type" "RS") |
6238 | (set_attr "atype" "reg")]) | |
9db1d521 | 6239 | |
1b48c8cc AS |
6240 | (define_insn "*<shift><mode>3" |
6241 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6242 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
6243 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] | |
6244 | "" | |
6245 | "s<lr>l<g>\t%0,<1>%Y2" | |
6246 | [(set_attr "op_type" "RS<E>") | |
077dab3b | 6247 | (set_attr "atype" "reg")]) |
9db1d521 | 6248 | |
4989e88a AK |
6249 | (define_insn "*<shift>di3_31_and" |
6250 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6251 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
6252 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
6253 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
6254 | "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63" | |
6255 | "s<lr>dl\t%0,%Y2" | |
6256 | [(set_attr "op_type" "RS") | |
6257 | (set_attr "atype" "reg")]) | |
6258 | ||
1b48c8cc AS |
6259 | (define_insn "*<shift><mode>3_and" |
6260 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6261 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
6262 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
6263 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
6264 | "(INTVAL (operands[3]) & 63) == 63" | |
6265 | "s<lr>l<g>\t%0,<1>%Y2" | |
6266 | [(set_attr "op_type" "RS<E>") | |
4989e88a AK |
6267 | (set_attr "atype" "reg")]) |
6268 | ||
9db1d521 | 6269 | ; |
1b48c8cc | 6270 | ; ashr(di|si)3 instruction pattern(s). |
9db1d521 HP |
6271 | ; |
6272 | ||
1b48c8cc | 6273 | (define_expand "ashr<mode>3" |
9db1d521 | 6274 | [(parallel |
1b48c8cc AS |
6275 | [(set (match_operand:DSI 0 "register_operand" "") |
6276 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
6277 | (match_operand:SI 2 "shift_count_or_setmem_operand" ""))) | |
ae156f85 | 6278 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
6279 | "" |
6280 | "") | |
6281 | ||
ecbe845e | 6282 | (define_insn "*ashrdi3_cc_31" |
ae156f85 | 6283 | [(set (reg CC_REGNUM) |
ac32b25e | 6284 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 6285 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 6286 | (const_int 0))) |
ac32b25e | 6287 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e UW |
6288 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
6289 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" | |
ac32b25e | 6290 | "srda\t%0,%Y2" |
077dab3b HP |
6291 | [(set_attr "op_type" "RS") |
6292 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
6293 | |
6294 | (define_insn "*ashrdi3_cconly_31" | |
ae156f85 | 6295 | [(set (reg CC_REGNUM) |
ac32b25e | 6296 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 6297 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 6298 | (const_int 0))) |
ac32b25e | 6299 | (clobber (match_scratch:DI 0 "=d"))] |
ecbe845e | 6300 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 6301 | "srda\t%0,%Y2" |
077dab3b HP |
6302 | [(set_attr "op_type" "RS") |
6303 | (set_attr "atype" "reg")]) | |
ecbe845e | 6304 | |
9db1d521 | 6305 | (define_insn "*ashrdi3_31" |
ac32b25e UW |
6306 | [(set (match_operand:DI 0 "register_operand" "=d") |
6307 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
4989e88a | 6308 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) |
ae156f85 | 6309 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 6310 | "!TARGET_64BIT" |
ac32b25e | 6311 | "srda\t%0,%Y2" |
077dab3b HP |
6312 | [(set_attr "op_type" "RS") |
6313 | (set_attr "atype" "reg")]) | |
c7453384 | 6314 | |
1b48c8cc | 6315 | (define_insn "*ashr<mode>3_cc" |
ae156f85 | 6316 | [(set (reg CC_REGNUM) |
1b48c8cc AS |
6317 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") |
6318 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) | |
ecbe845e | 6319 | (const_int 0))) |
1b48c8cc AS |
6320 | (set (match_operand:GPR 0 "register_operand" "=d") |
6321 | (ashiftrt:GPR (match_dup 1) (match_dup 2)))] | |
6322 | "s390_match_ccmode(insn, CCSmode)" | |
6323 | "sra<g>\t%0,<1>%Y2" | |
6324 | [(set_attr "op_type" "RS<E>") | |
077dab3b | 6325 | (set_attr "atype" "reg")]) |
ecbe845e | 6326 | |
1b48c8cc | 6327 | (define_insn "*ashr<mode>3_cconly" |
ae156f85 | 6328 | [(set (reg CC_REGNUM) |
1b48c8cc AS |
6329 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") |
6330 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) | |
ecbe845e | 6331 | (const_int 0))) |
1b48c8cc AS |
6332 | (clobber (match_scratch:GPR 0 "=d"))] |
6333 | "s390_match_ccmode(insn, CCSmode)" | |
6334 | "sra<g>\t%0,<1>%Y2" | |
6335 | [(set_attr "op_type" "RS<E>") | |
077dab3b | 6336 | (set_attr "atype" "reg")]) |
ecbe845e | 6337 | |
1b48c8cc AS |
6338 | (define_insn "*ashr<mode>3" |
6339 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6340 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
6341 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) | |
ae156f85 | 6342 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc AS |
6343 | "" |
6344 | "sra<g>\t%0,<1>%Y2" | |
6345 | [(set_attr "op_type" "RS<E>") | |
077dab3b HP |
6346 | (set_attr "atype" "reg")]) |
6347 | ||
9db1d521 | 6348 | |
4989e88a AK |
6349 | ; shift pattern with implicit ANDs |
6350 | ||
6351 | (define_insn "*ashrdi3_cc_31_and" | |
6352 | [(set (reg CC_REGNUM) | |
6353 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
6354 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
6355 | (match_operand:SI 3 "const_int_operand" "n"))) | |
6356 | (const_int 0))) | |
6357 | (set (match_operand:DI 0 "register_operand" "=d") | |
6358 | (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] | |
6359 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode) | |
6360 | && (INTVAL (operands[3]) & 63) == 63" | |
6361 | "srda\t%0,%Y2" | |
6362 | [(set_attr "op_type" "RS") | |
6363 | (set_attr "atype" "reg")]) | |
6364 | ||
6365 | (define_insn "*ashrdi3_cconly_31_and" | |
6366 | [(set (reg CC_REGNUM) | |
6367 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
6368 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
6369 | (match_operand:SI 3 "const_int_operand" "n"))) | |
6370 | (const_int 0))) | |
6371 | (clobber (match_scratch:DI 0 "=d"))] | |
6372 | "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode) | |
6373 | && (INTVAL (operands[3]) & 63) == 63" | |
6374 | "srda\t%0,%Y2" | |
6375 | [(set_attr "op_type" "RS") | |
6376 | (set_attr "atype" "reg")]) | |
6377 | ||
6378 | (define_insn "*ashrdi3_31_and" | |
6379 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6380 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
6381 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
6382 | (match_operand:SI 3 "const_int_operand" "n")))) | |
6383 | (clobber (reg:CC CC_REGNUM))] | |
6384 | "!TARGET_64BIT && (INTVAL (operands[3]) & 63) == 63" | |
6385 | "srda\t%0,%Y2" | |
6386 | [(set_attr "op_type" "RS") | |
6387 | (set_attr "atype" "reg")]) | |
6388 | ||
1b48c8cc | 6389 | (define_insn "*ashr<mode>3_cc_and" |
4989e88a | 6390 | [(set (reg CC_REGNUM) |
1b48c8cc AS |
6391 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") |
6392 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
6393 | (match_operand:SI 3 "const_int_operand" "n"))) | |
4989e88a | 6394 | (const_int 0))) |
1b48c8cc AS |
6395 | (set (match_operand:GPR 0 "register_operand" "=d") |
6396 | (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] | |
4989e88a | 6397 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
1b48c8cc AS |
6398 | "sra<g>\t%0,<1>%Y2" |
6399 | [(set_attr "op_type" "RS<E>") | |
4989e88a AK |
6400 | (set_attr "atype" "reg")]) |
6401 | ||
1b48c8cc | 6402 | (define_insn "*ashr<mode>3_cconly_and" |
4989e88a | 6403 | [(set (reg CC_REGNUM) |
1b48c8cc AS |
6404 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") |
6405 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
6406 | (match_operand:SI 3 "const_int_operand" "n"))) | |
4989e88a | 6407 | (const_int 0))) |
1b48c8cc | 6408 | (clobber (match_scratch:GPR 0 "=d"))] |
4989e88a | 6409 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
1b48c8cc AS |
6410 | "sra<g>\t%0,<1>%Y2" |
6411 | [(set_attr "op_type" "RS<E>") | |
4989e88a AK |
6412 | (set_attr "atype" "reg")]) |
6413 | ||
1b48c8cc AS |
6414 | (define_insn "*ashr<mode>3_and" |
6415 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6416 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>") | |
6417 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
6418 | (match_operand:SI 3 "const_int_operand" "n")))) | |
4989e88a AK |
6419 | (clobber (reg:CC CC_REGNUM))] |
6420 | "(INTVAL (operands[3]) & 63) == 63" | |
1b48c8cc AS |
6421 | "sra<g>\t%0,<1>%Y2" |
6422 | [(set_attr "op_type" "RS<E>") | |
4989e88a AK |
6423 | (set_attr "atype" "reg")]) |
6424 | ||
9db1d521 | 6425 | |
9db1d521 HP |
6426 | ;; |
6427 | ;; Branch instruction patterns. | |
6428 | ;; | |
6429 | ||
fa77b251 AS |
6430 | (define_expand "b<code>" |
6431 | [(set (pc) | |
6432 | (if_then_else (COMPARE (match_operand 0 "" "") | |
6433 | (const_int 0)) | |
6434 | (match_dup 0) | |
6435 | (pc)))] | |
ba956982 | 6436 | "" |
6590e19a | 6437 | "s390_emit_jump (operands[0], |
fa77b251 | 6438 | s390_emit_compare (<CODE>, s390_compare_op0, s390_compare_op1)); DONE;") |
ba956982 | 6439 | |
9db1d521 HP |
6440 | |
6441 | ;; | |
6442 | ;;- Conditional jump instructions. | |
6443 | ;; | |
6444 | ||
6590e19a UW |
6445 | (define_insn "*cjump_64" |
6446 | [(set (pc) | |
6447 | (if_then_else | |
ae156f85 | 6448 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
6449 | (label_ref (match_operand 0 "" "")) |
6450 | (pc)))] | |
6451 | "TARGET_CPU_ZARCH" | |
9db1d521 | 6452 | { |
13e58269 | 6453 | if (get_attr_length (insn) == 4) |
d40c829f | 6454 | return "j%C1\t%l0"; |
6590e19a | 6455 | else |
d40c829f | 6456 | return "jg%C1\t%l0"; |
6590e19a UW |
6457 | } |
6458 | [(set_attr "op_type" "RI") | |
6459 | (set_attr "type" "branch") | |
6460 | (set (attr "length") | |
6461 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6462 | (const_int 4) (const_int 6)))]) | |
6463 | ||
6464 | (define_insn "*cjump_31" | |
6465 | [(set (pc) | |
6466 | (if_then_else | |
ae156f85 | 6467 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
6468 | (label_ref (match_operand 0 "" "")) |
6469 | (pc)))] | |
6470 | "!TARGET_CPU_ZARCH" | |
6471 | { | |
8d933e31 AS |
6472 | gcc_assert (get_attr_length (insn) == 4); |
6473 | return "j%C1\t%l0"; | |
10bbf137 | 6474 | } |
9db1d521 | 6475 | [(set_attr "op_type" "RI") |
077dab3b | 6476 | (set_attr "type" "branch") |
13e58269 | 6477 | (set (attr "length") |
6590e19a UW |
6478 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6479 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6480 | (const_int 4) (const_int 6)) | |
6481 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6482 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 6483 | |
f314b9b1 | 6484 | (define_insn "*cjump_long" |
6590e19a UW |
6485 | [(set (pc) |
6486 | (if_then_else | |
ae156f85 | 6487 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
6488 | (match_operand 0 "address_operand" "U") |
6489 | (pc)))] | |
9db1d521 | 6490 | "" |
f314b9b1 UW |
6491 | { |
6492 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6493 | return "b%C1r\t%0"; |
f314b9b1 | 6494 | else |
d40c829f | 6495 | return "b%C1\t%a0"; |
10bbf137 | 6496 | } |
c7453384 | 6497 | [(set (attr "op_type") |
f314b9b1 UW |
6498 | (if_then_else (match_operand 0 "register_operand" "") |
6499 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 6500 | (set_attr "type" "branch") |
077dab3b | 6501 | (set_attr "atype" "agen")]) |
9db1d521 HP |
6502 | |
6503 | ||
6504 | ;; | |
6505 | ;;- Negated conditional jump instructions. | |
6506 | ;; | |
6507 | ||
6590e19a UW |
6508 | (define_insn "*icjump_64" |
6509 | [(set (pc) | |
6510 | (if_then_else | |
ae156f85 | 6511 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
6512 | (pc) |
6513 | (label_ref (match_operand 0 "" ""))))] | |
6514 | "TARGET_CPU_ZARCH" | |
c7453384 | 6515 | { |
13e58269 | 6516 | if (get_attr_length (insn) == 4) |
d40c829f | 6517 | return "j%D1\t%l0"; |
6590e19a | 6518 | else |
d40c829f | 6519 | return "jg%D1\t%l0"; |
6590e19a UW |
6520 | } |
6521 | [(set_attr "op_type" "RI") | |
6522 | (set_attr "type" "branch") | |
6523 | (set (attr "length") | |
6524 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6525 | (const_int 4) (const_int 6)))]) | |
6526 | ||
6527 | (define_insn "*icjump_31" | |
6528 | [(set (pc) | |
6529 | (if_then_else | |
ae156f85 | 6530 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
6531 | (pc) |
6532 | (label_ref (match_operand 0 "" ""))))] | |
6533 | "!TARGET_CPU_ZARCH" | |
6534 | { | |
8d933e31 AS |
6535 | gcc_assert (get_attr_length (insn) == 4); |
6536 | return "j%D1\t%l0"; | |
10bbf137 | 6537 | } |
9db1d521 | 6538 | [(set_attr "op_type" "RI") |
077dab3b | 6539 | (set_attr "type" "branch") |
13e58269 | 6540 | (set (attr "length") |
6590e19a UW |
6541 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6542 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6543 | (const_int 4) (const_int 6)) | |
6544 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6545 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 6546 | |
f314b9b1 | 6547 | (define_insn "*icjump_long" |
6590e19a UW |
6548 | [(set (pc) |
6549 | (if_then_else | |
ae156f85 | 6550 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
6551 | (pc) |
6552 | (match_operand 0 "address_operand" "U")))] | |
9db1d521 | 6553 | "" |
f314b9b1 UW |
6554 | { |
6555 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6556 | return "b%D1r\t%0"; |
f314b9b1 | 6557 | else |
d40c829f | 6558 | return "b%D1\t%a0"; |
10bbf137 | 6559 | } |
c7453384 | 6560 | [(set (attr "op_type") |
f314b9b1 UW |
6561 | (if_then_else (match_operand 0 "register_operand" "") |
6562 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6563 | (set_attr "type" "branch") |
6564 | (set_attr "atype" "agen")]) | |
9db1d521 | 6565 | |
4456530d HP |
6566 | ;; |
6567 | ;;- Trap instructions. | |
6568 | ;; | |
6569 | ||
6570 | (define_insn "trap" | |
6571 | [(trap_if (const_int 1) (const_int 0))] | |
6572 | "" | |
d40c829f | 6573 | "j\t.+2" |
6590e19a | 6574 | [(set_attr "op_type" "RI") |
077dab3b | 6575 | (set_attr "type" "branch")]) |
4456530d HP |
6576 | |
6577 | (define_expand "conditional_trap" | |
6590e19a UW |
6578 | [(trap_if (match_operand 0 "comparison_operator" "") |
6579 | (match_operand 1 "general_operand" ""))] | |
4456530d | 6580 | "" |
4456530d | 6581 | { |
6590e19a UW |
6582 | if (operands[1] != const0_rtx) FAIL; |
6583 | operands[0] = s390_emit_compare (GET_CODE (operands[0]), | |
6584 | s390_compare_op0, s390_compare_op1); | |
10bbf137 | 6585 | }) |
4456530d HP |
6586 | |
6587 | (define_insn "*trap" | |
ae156f85 | 6588 | [(trap_if (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4456530d HP |
6589 | (const_int 0))] |
6590 | "" | |
d40c829f | 6591 | "j%C0\t.+2"; |
077dab3b HP |
6592 | [(set_attr "op_type" "RI") |
6593 | (set_attr "type" "branch")]) | |
9db1d521 HP |
6594 | |
6595 | ;; | |
0a3bdf9d | 6596 | ;;- Loop instructions. |
9db1d521 | 6597 | ;; |
0a3bdf9d UW |
6598 | ;; This is all complicated by the fact that since this is a jump insn |
6599 | ;; we must handle our own output reloads. | |
c7453384 | 6600 | |
0a3bdf9d UW |
6601 | (define_expand "doloop_end" |
6602 | [(use (match_operand 0 "" "")) ; loop pseudo | |
6603 | (use (match_operand 1 "" "")) ; iterations; zero if unknown | |
6604 | (use (match_operand 2 "" "")) ; max iterations | |
6605 | (use (match_operand 3 "" "")) ; loop level | |
6606 | (use (match_operand 4 "" ""))] ; label | |
6607 | "" | |
0a3bdf9d | 6608 | { |
6590e19a UW |
6609 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
6610 | emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0])); | |
6611 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) | |
6612 | emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0])); | |
0a3bdf9d UW |
6613 | else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT) |
6614 | emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0])); | |
6615 | else | |
6616 | FAIL; | |
6617 | ||
6618 | DONE; | |
10bbf137 | 6619 | }) |
0a3bdf9d | 6620 | |
6590e19a | 6621 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
6622 | [(set (pc) |
6623 | (if_then_else | |
6624 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6625 | (const_int 1)) | |
6626 | (label_ref (match_operand 0 "" "")) | |
6627 | (pc))) | |
bd446804 | 6628 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") |
0a3bdf9d | 6629 | (plus:SI (match_dup 1) (const_int -1))) |
eb862a88 | 6630 | (clobber (match_scratch:SI 3 "=X,&1")) |
ae156f85 | 6631 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 6632 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
6633 | { |
6634 | if (which_alternative != 0) | |
10bbf137 | 6635 | return "#"; |
0a3bdf9d | 6636 | else if (get_attr_length (insn) == 4) |
d40c829f | 6637 | return "brct\t%1,%l0"; |
6590e19a | 6638 | else |
545d16ff | 6639 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
6640 | } |
6641 | "&& reload_completed | |
6642 | && (! REG_P (operands[2]) | |
6643 | || ! rtx_equal_p (operands[1], operands[2]))" | |
ae156f85 | 6644 | [(parallel [(set (reg:CCAN CC_REGNUM) |
6590e19a UW |
6645 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
6646 | (const_int 0))) | |
6647 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
6648 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 6649 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
6650 | (label_ref (match_dup 0)) |
6651 | (pc)))] | |
6652 | "" | |
6653 | [(set_attr "op_type" "RI") | |
6654 | (set_attr "type" "branch") | |
6655 | (set (attr "length") | |
6656 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6657 | (const_int 4) (const_int 10)))]) | |
6658 | ||
6659 | (define_insn_and_split "doloop_si31" | |
6660 | [(set (pc) | |
6661 | (if_then_else | |
6662 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6663 | (const_int 1)) | |
6664 | (label_ref (match_operand 0 "" "")) | |
6665 | (pc))) | |
6666 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d") | |
6667 | (plus:SI (match_dup 1) (const_int -1))) | |
eb862a88 | 6668 | (clobber (match_scratch:SI 3 "=X,&1")) |
ae156f85 | 6669 | (clobber (reg:CC CC_REGNUM))] |
6590e19a UW |
6670 | "!TARGET_CPU_ZARCH" |
6671 | { | |
6672 | if (which_alternative != 0) | |
6673 | return "#"; | |
6674 | else if (get_attr_length (insn) == 4) | |
6675 | return "brct\t%1,%l0"; | |
0a3bdf9d | 6676 | else |
8d933e31 | 6677 | gcc_unreachable (); |
10bbf137 | 6678 | } |
6590e19a UW |
6679 | "&& reload_completed |
6680 | && (! REG_P (operands[2]) | |
6681 | || ! rtx_equal_p (operands[1], operands[2]))" | |
ae156f85 | 6682 | [(parallel [(set (reg:CCAN CC_REGNUM) |
6590e19a UW |
6683 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
6684 | (const_int 0))) | |
6685 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
6686 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 6687 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
6688 | (label_ref (match_dup 0)) |
6689 | (pc)))] | |
6690 | "" | |
0a3bdf9d | 6691 | [(set_attr "op_type" "RI") |
077dab3b | 6692 | (set_attr "type" "branch") |
0a3bdf9d | 6693 | (set (attr "length") |
6590e19a UW |
6694 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6695 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6696 | (const_int 4) (const_int 6)) | |
6697 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6698 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 6699 | |
0a3bdf9d UW |
6700 | (define_insn "*doloop_si_long" |
6701 | [(set (pc) | |
6702 | (if_then_else | |
6703 | (ne (match_operand:SI 1 "register_operand" "d,d") | |
6704 | (const_int 1)) | |
d3632d41 | 6705 | (match_operand 0 "address_operand" "U,U") |
0a3bdf9d UW |
6706 | (pc))) |
6707 | (set (match_operand:SI 2 "register_operand" "=1,?*m*d") | |
6708 | (plus:SI (match_dup 1) (const_int -1))) | |
eb862a88 | 6709 | (clobber (match_scratch:SI 3 "=X,&1")) |
ae156f85 | 6710 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 6711 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
6712 | { |
6713 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6714 | return "bctr\t%1,%0"; |
0a3bdf9d | 6715 | else |
d40c829f | 6716 | return "bct\t%1,%a0"; |
10bbf137 | 6717 | } |
c7453384 | 6718 | [(set (attr "op_type") |
0a3bdf9d UW |
6719 | (if_then_else (match_operand 0 "register_operand" "") |
6720 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6721 | (set_attr "type" "branch") |
6722 | (set_attr "atype" "agen")]) | |
0a3bdf9d | 6723 | |
6590e19a | 6724 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
6725 | [(set (pc) |
6726 | (if_then_else | |
6727 | (ne (match_operand:DI 1 "register_operand" "d,d") | |
6728 | (const_int 1)) | |
6729 | (label_ref (match_operand 0 "" "")) | |
6730 | (pc))) | |
eb862a88 | 6731 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d") |
0a3bdf9d | 6732 | (plus:DI (match_dup 1) (const_int -1))) |
eb862a88 | 6733 | (clobber (match_scratch:DI 3 "=X,&1")) |
ae156f85 | 6734 | (clobber (reg:CC CC_REGNUM))] |
0a3bdf9d | 6735 | "TARGET_64BIT" |
0a3bdf9d UW |
6736 | { |
6737 | if (which_alternative != 0) | |
10bbf137 | 6738 | return "#"; |
0a3bdf9d | 6739 | else if (get_attr_length (insn) == 4) |
d40c829f | 6740 | return "brctg\t%1,%l0"; |
0a3bdf9d | 6741 | else |
545d16ff | 6742 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 6743 | } |
6590e19a | 6744 | "&& reload_completed |
0a3bdf9d UW |
6745 | && (! REG_P (operands[2]) |
6746 | || ! rtx_equal_p (operands[1], operands[2]))" | |
ae156f85 | 6747 | [(parallel [(set (reg:CCAN CC_REGNUM) |
0a3bdf9d UW |
6748 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
6749 | (const_int 0))) | |
6750 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
6751 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 6752 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 6753 | (label_ref (match_dup 0)) |
0a3bdf9d | 6754 | (pc)))] |
6590e19a UW |
6755 | "" |
6756 | [(set_attr "op_type" "RI") | |
6757 | (set_attr "type" "branch") | |
6758 | (set (attr "length") | |
6759 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6760 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
6761 | |
6762 | ;; | |
6763 | ;;- Unconditional jump instructions. | |
6764 | ;; | |
6765 | ||
6766 | ; | |
6767 | ; jump instruction pattern(s). | |
6768 | ; | |
6769 | ||
6590e19a UW |
6770 | (define_expand "jump" |
6771 | [(match_operand 0 "" "")] | |
9db1d521 | 6772 | "" |
6590e19a UW |
6773 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
6774 | ||
6775 | (define_insn "*jump64" | |
6776 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
6777 | "TARGET_CPU_ZARCH" | |
9db1d521 | 6778 | { |
13e58269 | 6779 | if (get_attr_length (insn) == 4) |
d40c829f | 6780 | return "j\t%l0"; |
6590e19a | 6781 | else |
d40c829f | 6782 | return "jg\t%l0"; |
6590e19a UW |
6783 | } |
6784 | [(set_attr "op_type" "RI") | |
6785 | (set_attr "type" "branch") | |
6786 | (set (attr "length") | |
6787 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6788 | (const_int 4) (const_int 6)))]) | |
6789 | ||
6790 | (define_insn "*jump31" | |
6791 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
6792 | "!TARGET_CPU_ZARCH" | |
6793 | { | |
8d933e31 AS |
6794 | gcc_assert (get_attr_length (insn) == 4); |
6795 | return "j\t%l0"; | |
10bbf137 | 6796 | } |
9db1d521 | 6797 | [(set_attr "op_type" "RI") |
077dab3b | 6798 | (set_attr "type" "branch") |
13e58269 | 6799 | (set (attr "length") |
6590e19a UW |
6800 | (if_then_else (eq (symbol_ref "flag_pic") (const_int 0)) |
6801 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6802 | (const_int 4) (const_int 6)) | |
6803 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
6804 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
6805 | |
6806 | ; | |
6807 | ; indirect-jump instruction pattern(s). | |
6808 | ; | |
6809 | ||
6810 | (define_insn "indirect_jump" | |
d3632d41 | 6811 | [(set (pc) (match_operand 0 "address_operand" "U"))] |
9db1d521 | 6812 | "" |
f314b9b1 UW |
6813 | { |
6814 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 6815 | return "br\t%0"; |
f314b9b1 | 6816 | else |
d40c829f | 6817 | return "b\t%a0"; |
10bbf137 | 6818 | } |
c7453384 | 6819 | [(set (attr "op_type") |
f314b9b1 UW |
6820 | (if_then_else (match_operand 0 "register_operand" "") |
6821 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6822 | (set_attr "type" "branch") |
6823 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
6824 | |
6825 | ; | |
f314b9b1 | 6826 | ; casesi instruction pattern(s). |
9db1d521 HP |
6827 | ; |
6828 | ||
f314b9b1 | 6829 | (define_insn "casesi_jump" |
d3632d41 | 6830 | [(set (pc) (match_operand 0 "address_operand" "U")) |
f314b9b1 | 6831 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 6832 | "" |
9db1d521 | 6833 | { |
f314b9b1 | 6834 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 6835 | return "br\t%0"; |
f314b9b1 | 6836 | else |
d40c829f | 6837 | return "b\t%a0"; |
10bbf137 | 6838 | } |
c7453384 | 6839 | [(set (attr "op_type") |
f314b9b1 UW |
6840 | (if_then_else (match_operand 0 "register_operand" "") |
6841 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
6842 | (set_attr "type" "branch") |
6843 | (set_attr "atype" "agen")]) | |
9db1d521 | 6844 | |
f314b9b1 UW |
6845 | (define_expand "casesi" |
6846 | [(match_operand:SI 0 "general_operand" "") | |
6847 | (match_operand:SI 1 "general_operand" "") | |
6848 | (match_operand:SI 2 "general_operand" "") | |
6849 | (label_ref (match_operand 3 "" "")) | |
6850 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 6851 | "" |
f314b9b1 UW |
6852 | { |
6853 | rtx index = gen_reg_rtx (SImode); | |
6854 | rtx base = gen_reg_rtx (Pmode); | |
6855 | rtx target = gen_reg_rtx (Pmode); | |
6856 | ||
6857 | emit_move_insn (index, operands[0]); | |
6858 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
6859 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 6860 | operands[4]); |
f314b9b1 UW |
6861 | |
6862 | if (Pmode != SImode) | |
6863 | index = convert_to_mode (Pmode, index, 1); | |
6864 | if (GET_CODE (index) != REG) | |
6865 | index = copy_to_mode_reg (Pmode, index); | |
6866 | ||
6867 | if (TARGET_64BIT) | |
6868 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
6869 | else | |
a556fd39 | 6870 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 6871 | |
f314b9b1 UW |
6872 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
6873 | ||
542a8afa | 6874 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
6875 | emit_move_insn (target, index); |
6876 | ||
6877 | if (flag_pic) | |
6878 | target = gen_rtx_PLUS (Pmode, base, target); | |
6879 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
6880 | ||
6881 | DONE; | |
10bbf137 | 6882 | }) |
9db1d521 HP |
6883 | |
6884 | ||
6885 | ;; | |
6886 | ;;- Jump to subroutine. | |
6887 | ;; | |
6888 | ;; | |
6889 | ||
6890 | ; | |
6891 | ; untyped call instruction pattern(s). | |
6892 | ; | |
6893 | ||
6894 | ;; Call subroutine returning any type. | |
6895 | (define_expand "untyped_call" | |
6896 | [(parallel [(call (match_operand 0 "" "") | |
6897 | (const_int 0)) | |
6898 | (match_operand 1 "" "") | |
6899 | (match_operand 2 "" "")])] | |
6900 | "" | |
9db1d521 HP |
6901 | { |
6902 | int i; | |
6903 | ||
6904 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
6905 | ||
6906 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
6907 | { | |
6908 | rtx set = XVECEXP (operands[2], 0, i); | |
6909 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
6910 | } | |
6911 | ||
6912 | /* The optimizer does not know that the call sets the function value | |
6913 | registers we stored in the result block. We avoid problems by | |
6914 | claiming that all hard registers are used and clobbered at this | |
6915 | point. */ | |
6916 | emit_insn (gen_blockage ()); | |
6917 | ||
6918 | DONE; | |
10bbf137 | 6919 | }) |
9db1d521 HP |
6920 | |
6921 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
6922 | ;; all of memory. This blocks insns from being moved across this point. | |
6923 | ||
6924 | (define_insn "blockage" | |
10bbf137 | 6925 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 6926 | "" |
4023fb28 | 6927 | "" |
d5869ca0 UW |
6928 | [(set_attr "type" "none") |
6929 | (set_attr "length" "0")]) | |
4023fb28 | 6930 | |
9db1d521 | 6931 | ; |
ed9676cf | 6932 | ; sibcall patterns |
9db1d521 HP |
6933 | ; |
6934 | ||
ed9676cf | 6935 | (define_expand "sibcall" |
44b8152b | 6936 | [(call (match_operand 0 "" "") |
ed9676cf | 6937 | (match_operand 1 "" ""))] |
9db1d521 | 6938 | "" |
9db1d521 | 6939 | { |
ed9676cf AK |
6940 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
6941 | DONE; | |
6942 | }) | |
9db1d521 | 6943 | |
ed9676cf | 6944 | (define_insn "*sibcall_br" |
ae156f85 | 6945 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 6946 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 6947 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
6948 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
6949 | "br\t%%r1" | |
6950 | [(set_attr "op_type" "RR") | |
6951 | (set_attr "type" "branch") | |
6952 | (set_attr "atype" "agen")]) | |
9db1d521 | 6953 | |
ed9676cf AK |
6954 | (define_insn "*sibcall_brc" |
6955 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
6956 | (match_operand 1 "const_int_operand" "n"))] | |
6957 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
6958 | "j\t%0" | |
6959 | [(set_attr "op_type" "RI") | |
6960 | (set_attr "type" "branch")]) | |
9db1d521 | 6961 | |
ed9676cf AK |
6962 | (define_insn "*sibcall_brcl" |
6963 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
6964 | (match_operand 1 "const_int_operand" "n"))] | |
6965 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
6966 | "jg\t%0" | |
6967 | [(set_attr "op_type" "RIL") | |
6968 | (set_attr "type" "branch")]) | |
44b8152b | 6969 | |
ed9676cf AK |
6970 | ; |
6971 | ; sibcall_value patterns | |
6972 | ; | |
9e8327e3 | 6973 | |
ed9676cf AK |
6974 | (define_expand "sibcall_value" |
6975 | [(set (match_operand 0 "" "") | |
6976 | (call (match_operand 1 "" "") | |
6977 | (match_operand 2 "" "")))] | |
6978 | "" | |
6979 | { | |
6980 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 6981 | DONE; |
10bbf137 | 6982 | }) |
9db1d521 | 6983 | |
ed9676cf AK |
6984 | (define_insn "*sibcall_value_br" |
6985 | [(set (match_operand 0 "" "") | |
ae156f85 | 6986 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 6987 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 6988 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
6989 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
6990 | "br\t%%r1" | |
6991 | [(set_attr "op_type" "RR") | |
6992 | (set_attr "type" "branch") | |
6993 | (set_attr "atype" "agen")]) | |
6994 | ||
6995 | (define_insn "*sibcall_value_brc" | |
6996 | [(set (match_operand 0 "" "") | |
6997 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
6998 | (match_operand 2 "const_int_operand" "n")))] | |
6999 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
7000 | "j\t%1" | |
7001 | [(set_attr "op_type" "RI") | |
7002 | (set_attr "type" "branch")]) | |
7003 | ||
7004 | (define_insn "*sibcall_value_brcl" | |
7005 | [(set (match_operand 0 "" "") | |
7006 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
7007 | (match_operand 2 "const_int_operand" "n")))] | |
7008 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
7009 | "jg\t%1" | |
7010 | [(set_attr "op_type" "RIL") | |
7011 | (set_attr "type" "branch")]) | |
7012 | ||
7013 | ||
7014 | ; | |
7015 | ; call instruction pattern(s). | |
7016 | ; | |
7017 | ||
7018 | (define_expand "call" | |
7019 | [(call (match_operand 0 "" "") | |
7020 | (match_operand 1 "" "")) | |
7021 | (use (match_operand 2 "" ""))] | |
44b8152b | 7022 | "" |
ed9676cf | 7023 | { |
2f7e5a0d | 7024 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
7025 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
7026 | DONE; | |
7027 | }) | |
44b8152b | 7028 | |
9e8327e3 UW |
7029 | (define_insn "*bras" |
7030 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7031 | (match_operand 1 "const_int_operand" "n")) | |
7032 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
7033 | "!SIBLING_CALL_P (insn) |
7034 | && TARGET_SMALL_EXEC | |
ed9676cf | 7035 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 7036 | "bras\t%2,%0" |
9db1d521 | 7037 | [(set_attr "op_type" "RI") |
4023fb28 | 7038 | (set_attr "type" "jsr")]) |
9db1d521 | 7039 | |
9e8327e3 UW |
7040 | (define_insn "*brasl" |
7041 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
7042 | (match_operand 1 "const_int_operand" "n")) | |
7043 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
7044 | "!SIBLING_CALL_P (insn) |
7045 | && TARGET_CPU_ZARCH | |
ed9676cf | 7046 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
7047 | "brasl\t%2,%0" |
7048 | [(set_attr "op_type" "RIL") | |
077dab3b | 7049 | (set_attr "type" "jsr")]) |
9db1d521 | 7050 | |
9e8327e3 UW |
7051 | (define_insn "*basr" |
7052 | [(call (mem:QI (match_operand 0 "address_operand" "U")) | |
7053 | (match_operand 1 "const_int_operand" "n")) | |
7054 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 7055 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
7056 | { |
7057 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7058 | return "basr\t%2,%0"; | |
7059 | else | |
7060 | return "bas\t%2,%a0"; | |
7061 | } | |
7062 | [(set (attr "op_type") | |
7063 | (if_then_else (match_operand 0 "register_operand" "") | |
7064 | (const_string "RR") (const_string "RX"))) | |
7065 | (set_attr "type" "jsr") | |
7066 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
7067 | |
7068 | ; | |
7069 | ; call_value instruction pattern(s). | |
7070 | ; | |
7071 | ||
7072 | (define_expand "call_value" | |
44b8152b UW |
7073 | [(set (match_operand 0 "" "") |
7074 | (call (match_operand 1 "" "") | |
7075 | (match_operand 2 "" ""))) | |
7076 | (use (match_operand 3 "" ""))] | |
9db1d521 | 7077 | "" |
9db1d521 | 7078 | { |
2f7e5a0d | 7079 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 7080 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 7081 | DONE; |
10bbf137 | 7082 | }) |
9db1d521 | 7083 | |
9e8327e3 | 7084 | (define_insn "*bras_r" |
c19ec8f9 | 7085 | [(set (match_operand 0 "" "") |
9e8327e3 | 7086 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 7087 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 7088 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
7089 | "!SIBLING_CALL_P (insn) |
7090 | && TARGET_SMALL_EXEC | |
ed9676cf | 7091 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 7092 | "bras\t%3,%1" |
9db1d521 | 7093 | [(set_attr "op_type" "RI") |
f2d3c02a | 7094 | (set_attr "type" "jsr")]) |
9db1d521 | 7095 | |
9e8327e3 | 7096 | (define_insn "*brasl_r" |
c19ec8f9 | 7097 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7098 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7099 | (match_operand 2 "const_int_operand" "n"))) | |
7100 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
7101 | "!SIBLING_CALL_P (insn) |
7102 | && TARGET_CPU_ZARCH | |
ed9676cf | 7103 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7104 | "brasl\t%3,%1" |
7105 | [(set_attr "op_type" "RIL") | |
077dab3b | 7106 | (set_attr "type" "jsr")]) |
9db1d521 | 7107 | |
9e8327e3 | 7108 | (define_insn "*basr_r" |
c19ec8f9 | 7109 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7110 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
7111 | (match_operand 2 "const_int_operand" "n"))) | |
7112 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 7113 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7114 | { |
7115 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7116 | return "basr\t%3,%1"; | |
7117 | else | |
7118 | return "bas\t%3,%a1"; | |
7119 | } | |
7120 | [(set (attr "op_type") | |
7121 | (if_then_else (match_operand 1 "register_operand" "") | |
7122 | (const_string "RR") (const_string "RX"))) | |
7123 | (set_attr "type" "jsr") | |
7124 | (set_attr "atype" "agen")]) | |
9db1d521 | 7125 | |
fd3cd001 UW |
7126 | ;; |
7127 | ;;- Thread-local storage support. | |
7128 | ;; | |
7129 | ||
c5aa1d12 | 7130 | (define_expand "get_tp_64" |
ae156f85 | 7131 | [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI TP_REGNUM))] |
fd3cd001 | 7132 | "TARGET_64BIT" |
c5aa1d12 | 7133 | "") |
fd3cd001 | 7134 | |
c5aa1d12 | 7135 | (define_expand "get_tp_31" |
ae156f85 | 7136 | [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI TP_REGNUM))] |
fd3cd001 | 7137 | "!TARGET_64BIT" |
c5aa1d12 | 7138 | "") |
fd3cd001 | 7139 | |
c5aa1d12 | 7140 | (define_expand "set_tp_64" |
ae156f85 AS |
7141 | [(set (reg:DI TP_REGNUM) (match_operand:DI 0 "nonimmediate_operand" "")) |
7142 | (set (reg:DI TP_REGNUM) (unspec_volatile:DI [(reg:DI TP_REGNUM)] UNSPECV_SET_TP))] | |
fd3cd001 | 7143 | "TARGET_64BIT" |
c5aa1d12 | 7144 | "") |
fd3cd001 | 7145 | |
c5aa1d12 | 7146 | (define_expand "set_tp_31" |
ae156f85 AS |
7147 | [(set (reg:SI TP_REGNUM) (match_operand:SI 0 "nonimmediate_operand" "")) |
7148 | (set (reg:SI TP_REGNUM) (unspec_volatile:SI [(reg:SI TP_REGNUM)] UNSPECV_SET_TP))] | |
fd3cd001 | 7149 | "!TARGET_64BIT" |
c5aa1d12 UW |
7150 | "") |
7151 | ||
7152 | (define_insn "*set_tp" | |
ae156f85 | 7153 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
7154 | "" |
7155 | "" | |
7156 | [(set_attr "type" "none") | |
7157 | (set_attr "length" "0")]) | |
c7453384 | 7158 | |
fd3cd001 UW |
7159 | (define_insn "*tls_load_64" |
7160 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7161 | (unspec:DI [(match_operand:DI 1 "memory_operand" "m") | |
7162 | (match_operand:DI 2 "" "")] | |
7163 | UNSPEC_TLS_LOAD))] | |
7164 | "TARGET_64BIT" | |
d40c829f | 7165 | "lg\t%0,%1%J2" |
fd3cd001 UW |
7166 | [(set_attr "op_type" "RXE")]) |
7167 | ||
7168 | (define_insn "*tls_load_31" | |
d3632d41 UW |
7169 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
7170 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
7171 | (match_operand:SI 2 "" "")] |
7172 | UNSPEC_TLS_LOAD))] | |
7173 | "!TARGET_64BIT" | |
d3632d41 | 7174 | "@ |
d40c829f UW |
7175 | l\t%0,%1%J2 |
7176 | ly\t%0,%1%J2" | |
d3632d41 | 7177 | [(set_attr "op_type" "RX,RXY")]) |
fd3cd001 | 7178 | |
9e8327e3 | 7179 | (define_insn "*bras_tls" |
c19ec8f9 | 7180 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7181 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7182 | (match_operand 2 "const_int_operand" "n"))) | |
7183 | (clobber (match_operand 3 "register_operand" "=r")) | |
7184 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
7185 | "!SIBLING_CALL_P (insn) |
7186 | && TARGET_SMALL_EXEC | |
ed9676cf | 7187 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 7188 | "bras\t%3,%1%J4" |
fd3cd001 UW |
7189 | [(set_attr "op_type" "RI") |
7190 | (set_attr "type" "jsr")]) | |
7191 | ||
9e8327e3 | 7192 | (define_insn "*brasl_tls" |
c19ec8f9 | 7193 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7194 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
7195 | (match_operand 2 "const_int_operand" "n"))) | |
7196 | (clobber (match_operand 3 "register_operand" "=r")) | |
7197 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
7198 | "!SIBLING_CALL_P (insn) |
7199 | && TARGET_CPU_ZARCH | |
ed9676cf | 7200 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7201 | "brasl\t%3,%1%J4" |
7202 | [(set_attr "op_type" "RIL") | |
fd3cd001 UW |
7203 | (set_attr "type" "jsr")]) |
7204 | ||
9e8327e3 | 7205 | (define_insn "*basr_tls" |
c19ec8f9 | 7206 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
7207 | (call (mem:QI (match_operand 1 "address_operand" "U")) |
7208 | (match_operand 2 "const_int_operand" "n"))) | |
7209 | (clobber (match_operand 3 "register_operand" "=r")) | |
7210 | (use (match_operand 4 "" ""))] | |
ed9676cf | 7211 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
7212 | { |
7213 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
7214 | return "basr\t%3,%1%J4"; | |
7215 | else | |
7216 | return "bas\t%3,%a1%J4"; | |
7217 | } | |
7218 | [(set (attr "op_type") | |
7219 | (if_then_else (match_operand 1 "register_operand" "") | |
7220 | (const_string "RR") (const_string "RX"))) | |
7221 | (set_attr "type" "jsr") | |
7222 | (set_attr "atype" "agen")]) | |
fd3cd001 | 7223 | |
e0374221 AS |
7224 | ;; |
7225 | ;;- Atomic operations | |
7226 | ;; | |
7227 | ||
7228 | ; | |
7229 | ; memory barrier pattern. | |
7230 | ; | |
7231 | ||
7232 | (define_expand "memory_barrier" | |
7233 | [(set (mem:BLK (match_dup 0)) | |
7234 | (unspec_volatile:BLK [(mem:BLK (match_dup 0))] UNSPECV_MB))] | |
7235 | "" | |
7236 | { | |
7237 | operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (DImode)); | |
7238 | MEM_VOLATILE_P (operands[0]) = 1; | |
7239 | }) | |
7240 | ||
7241 | (define_insn "*memory_barrier" | |
7242 | [(set (match_operand:BLK 0 "" "") | |
7243 | (unspec_volatile:BLK [(match_operand:BLK 1 "" "")] UNSPECV_MB))] | |
7244 | "" | |
7245 | "bcr\t15,0" | |
7246 | [(set_attr "op_type" "RR")]) | |
7247 | ||
7248 | ; | |
7249 | ; compare and swap patterns. | |
7250 | ; | |
7251 | ||
8006eaa6 AS |
7252 | (define_expand "sync_compare_and_swap<mode>" |
7253 | [(parallel | |
7254 | [(set (match_operand:TDSI 0 "register_operand" "") | |
7255 | (match_operand:TDSI 1 "memory_operand" "")) | |
7256 | (set (match_dup 1) | |
7257 | (unspec_volatile:TDSI | |
7258 | [(match_dup 1) | |
7259 | (match_operand:TDSI 2 "register_operand" "") | |
7260 | (match_operand:TDSI 3 "register_operand" "")] | |
7261 | UNSPECV_CAS)) | |
7262 | (set (reg:CCZ1 CC_REGNUM) | |
7263 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
7264 | "") | |
e0374221 | 7265 | |
3093f076 AS |
7266 | (define_expand "sync_compare_and_swap<mode>" |
7267 | [(parallel | |
7268 | [(set (match_operand:HQI 0 "register_operand" "") | |
7269 | (match_operand:HQI 1 "memory_operand" "")) | |
7270 | (set (match_dup 1) | |
7271 | (unspec_volatile:HQI | |
7272 | [(match_dup 1) | |
7273 | (match_operand:HQI 2 "general_operand" "") | |
7274 | (match_operand:HQI 3 "general_operand" "")] | |
7275 | UNSPECV_CAS)) | |
7276 | (set (reg:CCZ1 CC_REGNUM) | |
7277 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
7278 | "" | |
7279 | "s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], | |
7280 | operands[2], operands[3]); DONE;") | |
7281 | ||
e0374221 AS |
7282 | (define_expand "sync_compare_and_swap_cc<mode>" |
7283 | [(parallel | |
8006eaa6 AS |
7284 | [(set (match_operand:TDSI 0 "register_operand" "") |
7285 | (match_operand:TDSI 1 "memory_operand" "")) | |
e0374221 | 7286 | (set (match_dup 1) |
8006eaa6 | 7287 | (unspec_volatile:TDSI |
e0374221 | 7288 | [(match_dup 1) |
8006eaa6 AS |
7289 | (match_operand:TDSI 2 "register_operand" "") |
7290 | (match_operand:TDSI 3 "register_operand" "")] | |
e0374221 AS |
7291 | UNSPECV_CAS)) |
7292 | (set (match_dup 4) | |
69950452 | 7293 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] |
e0374221 AS |
7294 | "" |
7295 | { | |
8006eaa6 | 7296 | /* Emulate compare. */ |
69950452 | 7297 | operands[4] = gen_rtx_REG (CCZ1mode, CC_REGNUM); |
e0374221 AS |
7298 | s390_compare_op0 = operands[1]; |
7299 | s390_compare_op1 = operands[2]; | |
7300 | s390_compare_emitted = operands[4]; | |
7301 | }) | |
7302 | ||
8006eaa6 AS |
7303 | (define_insn "*sync_compare_and_swap<mode>" |
7304 | [(set (match_operand:DP 0 "register_operand" "=r") | |
7305 | (match_operand:DP 1 "memory_operand" "+Q")) | |
7306 | (set (match_dup 1) | |
7307 | (unspec_volatile:DP | |
7308 | [(match_dup 1) | |
7309 | (match_operand:DP 2 "register_operand" "0") | |
7310 | (match_operand:DP 3 "register_operand" "r")] | |
7311 | UNSPECV_CAS)) | |
7312 | (set (reg:CCZ1 CC_REGNUM) | |
7313 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
7314 | "" | |
7315 | "cds<tg>\t%0,%3,%S1" | |
7316 | [(set_attr "op_type" "RS<TE>") | |
7317 | (set_attr "type" "sem")]) | |
7318 | ||
7319 | (define_insn "*sync_compare_and_swap<mode>" | |
e0374221 AS |
7320 | [(set (match_operand:GPR 0 "register_operand" "=r") |
7321 | (match_operand:GPR 1 "memory_operand" "+Q")) | |
7322 | (set (match_dup 1) | |
7323 | (unspec_volatile:GPR | |
7324 | [(match_dup 1) | |
7325 | (match_operand:GPR 2 "register_operand" "0") | |
7326 | (match_operand:GPR 3 "register_operand" "r")] | |
7327 | UNSPECV_CAS)) | |
69950452 AS |
7328 | (set (reg:CCZ1 CC_REGNUM) |
7329 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
e0374221 AS |
7330 | "" |
7331 | "cs<g>\t%0,%3,%S1" | |
7332 | [(set_attr "op_type" "RS<E>") | |
7333 | (set_attr "type" "sem")]) | |
7334 | ||
7335 | ||
45d18331 AS |
7336 | ; |
7337 | ; Other atomic instruction patterns. | |
7338 | ; | |
7339 | ||
7340 | (define_expand "sync_lock_test_and_set<mode>" | |
7341 | [(match_operand:HQI 0 "register_operand") | |
7342 | (match_operand:HQI 1 "memory_operand") | |
7343 | (match_operand:HQI 2 "general_operand")] | |
7344 | "" | |
7345 | "s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], | |
7346 | operands[2], false); DONE;") | |
7347 | ||
7348 | (define_expand "sync_<atomic><mode>" | |
7349 | [(set (match_operand:HQI 0 "memory_operand") | |
7350 | (ATOMIC:HQI (match_dup 0) | |
7351 | (match_operand:HQI 1 "general_operand")))] | |
7352 | "" | |
7353 | "s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], | |
7354 | operands[1], false); DONE;") | |
7355 | ||
7356 | (define_expand "sync_old_<atomic><mode>" | |
7357 | [(set (match_operand:HQI 0 "register_operand") | |
7358 | (match_operand:HQI 1 "memory_operand")) | |
7359 | (set (match_dup 1) | |
7360 | (ATOMIC:HQI (match_dup 1) | |
7361 | (match_operand:HQI 2 "general_operand")))] | |
7362 | "" | |
7363 | "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
7364 | operands[2], false); DONE;") | |
7365 | ||
7366 | (define_expand "sync_new_<atomic><mode>" | |
7367 | [(set (match_operand:HQI 0 "register_operand") | |
7368 | (ATOMIC:HQI (match_operand:HQI 1 "memory_operand") | |
7369 | (match_operand:HQI 2 "general_operand"))) | |
7370 | (set (match_dup 1) (ATOMIC:HQI (match_dup 1) (match_dup 2)))] | |
7371 | "" | |
7372 | "s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
7373 | operands[2], true); DONE;") | |
7374 | ||
9db1d521 HP |
7375 | ;; |
7376 | ;;- Miscellaneous instructions. | |
7377 | ;; | |
7378 | ||
7379 | ; | |
7380 | ; allocate stack instruction pattern(s). | |
7381 | ; | |
7382 | ||
7383 | (define_expand "allocate_stack" | |
ef44a6ff UW |
7384 | [(match_operand 0 "general_operand" "") |
7385 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 7386 | "TARGET_BACKCHAIN" |
9db1d521 | 7387 | { |
ef44a6ff | 7388 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 7389 | |
ef44a6ff UW |
7390 | emit_move_insn (temp, s390_back_chain_rtx ()); |
7391 | anti_adjust_stack (operands[1]); | |
7392 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 7393 | |
ef44a6ff UW |
7394 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
7395 | DONE; | |
10bbf137 | 7396 | }) |
9db1d521 HP |
7397 | |
7398 | ||
7399 | ; | |
43ab026f | 7400 | ; setjmp instruction pattern. |
9db1d521 HP |
7401 | ; |
7402 | ||
9db1d521 | 7403 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 7404 | [(match_operand 0 "" "")] |
f314b9b1 | 7405 | "flag_pic" |
9db1d521 | 7406 | { |
585539a1 | 7407 | emit_insn (s390_load_got ()); |
fd7643fb | 7408 | emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); |
9db1d521 | 7409 | DONE; |
fd7643fb | 7410 | }) |
9db1d521 | 7411 | |
9db1d521 HP |
7412 | ;; These patterns say how to save and restore the stack pointer. We need not |
7413 | ;; save the stack pointer at function level since we are careful to | |
7414 | ;; preserve the backchain. At block level, we have to restore the backchain | |
7415 | ;; when we restore the stack pointer. | |
7416 | ;; | |
7417 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
7418 | ;; backchain and restore both. Note that in the nonlocal case, the | |
7419 | ;; save area is a memory location. | |
7420 | ||
7421 | (define_expand "save_stack_function" | |
7422 | [(match_operand 0 "general_operand" "") | |
7423 | (match_operand 1 "general_operand" "")] | |
7424 | "" | |
7425 | "DONE;") | |
7426 | ||
7427 | (define_expand "restore_stack_function" | |
7428 | [(match_operand 0 "general_operand" "") | |
7429 | (match_operand 1 "general_operand" "")] | |
7430 | "" | |
7431 | "DONE;") | |
7432 | ||
7433 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
7434 | [(match_operand 0 "register_operand" "") |
7435 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 7436 | "TARGET_BACKCHAIN" |
9db1d521 | 7437 | { |
ef44a6ff UW |
7438 | rtx temp = gen_reg_rtx (Pmode); |
7439 | ||
7440 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
7441 | emit_move_insn (operands[0], operands[1]); | |
7442 | emit_move_insn (s390_back_chain_rtx (), temp); | |
7443 | ||
7444 | DONE; | |
10bbf137 | 7445 | }) |
9db1d521 HP |
7446 | |
7447 | (define_expand "save_stack_nonlocal" | |
7448 | [(match_operand 0 "memory_operand" "") | |
7449 | (match_operand 1 "register_operand" "")] | |
7450 | "" | |
9db1d521 | 7451 | { |
ef44a6ff UW |
7452 | enum machine_mode mode = TARGET_64BIT ? OImode : TImode; |
7453 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); | |
7454 | ||
7455 | /* Copy the backchain to the first word, sp to the second and the | |
7456 | literal pool base to the third. */ | |
7457 | ||
b3d31392 | 7458 | if (TARGET_BACKCHAIN) |
ef44a6ff UW |
7459 | { |
7460 | rtx temp = force_reg (Pmode, s390_back_chain_rtx ()); | |
7461 | emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp); | |
7462 | } | |
7463 | ||
7464 | emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]); | |
7465 | emit_move_insn (operand_subword (operands[0], 2, 0, mode), base); | |
9db1d521 | 7466 | |
9db1d521 | 7467 | DONE; |
10bbf137 | 7468 | }) |
9db1d521 HP |
7469 | |
7470 | (define_expand "restore_stack_nonlocal" | |
7471 | [(match_operand 0 "register_operand" "") | |
7472 | (match_operand 1 "memory_operand" "")] | |
7473 | "" | |
9db1d521 | 7474 | { |
ef44a6ff | 7475 | enum machine_mode mode = TARGET_64BIT ? OImode : TImode; |
490ceeb4 | 7476 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 7477 | rtx temp = NULL_RTX; |
9db1d521 | 7478 | |
43ab026f | 7479 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 7480 | literal pool base from the third. */ |
43ab026f | 7481 | |
b3d31392 | 7482 | if (TARGET_BACKCHAIN) |
ef44a6ff UW |
7483 | temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode)); |
7484 | ||
7485 | emit_move_insn (base, operand_subword (operands[1], 2, 0, mode)); | |
7486 | emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode)); | |
7487 | ||
7488 | if (temp) | |
7489 | emit_move_insn (s390_back_chain_rtx (), temp); | |
7490 | ||
7491 | emit_insn (gen_rtx_USE (VOIDmode, base)); | |
9db1d521 | 7492 | DONE; |
10bbf137 | 7493 | }) |
9db1d521 | 7494 | |
7bcebb25 AK |
7495 | (define_expand "exception_receiver" |
7496 | [(const_int 0)] | |
7497 | "" | |
7498 | { | |
7499 | s390_set_has_landing_pad_p (true); | |
7500 | DONE; | |
7501 | }) | |
9db1d521 HP |
7502 | |
7503 | ; | |
7504 | ; nop instruction pattern(s). | |
7505 | ; | |
7506 | ||
7507 | (define_insn "nop" | |
7508 | [(const_int 0)] | |
7509 | "" | |
d40c829f | 7510 | "lr\t0,0" |
9db1d521 HP |
7511 | [(set_attr "op_type" "RR")]) |
7512 | ||
7513 | ||
7514 | ; | |
7515 | ; Special literal pool access instruction pattern(s). | |
7516 | ; | |
7517 | ||
416cf582 UW |
7518 | (define_insn "*pool_entry" |
7519 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
7520 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 7521 | "" |
9db1d521 | 7522 | { |
416cf582 UW |
7523 | enum machine_mode mode = GET_MODE (PATTERN (insn)); |
7524 | unsigned int align = GET_MODE_BITSIZE (mode); | |
faeb9bb6 | 7525 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
7526 | return ""; |
7527 | } | |
b628bd8e | 7528 | [(set (attr "length") |
416cf582 | 7529 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 7530 | |
9bb86f41 UW |
7531 | (define_insn "pool_align" |
7532 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
7533 | UNSPECV_POOL_ALIGN)] | |
7534 | "" | |
7535 | ".align\t%0" | |
b628bd8e | 7536 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 7537 | |
9bb86f41 UW |
7538 | (define_insn "pool_section_start" |
7539 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
7540 | "" | |
7541 | ".section\t.rodata" | |
b628bd8e | 7542 | [(set_attr "length" "0")]) |
b2ccb744 | 7543 | |
9bb86f41 UW |
7544 | (define_insn "pool_section_end" |
7545 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
7546 | "" | |
b2ccb744 | 7547 | ".previous" |
b628bd8e | 7548 | [(set_attr "length" "0")]) |
b2ccb744 | 7549 | |
5af2f3d3 | 7550 | (define_insn "main_base_31_small" |
9e8327e3 UW |
7551 | [(set (match_operand 0 "register_operand" "=a") |
7552 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
7553 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
7554 | "basr\t%0,0" |
7555 | [(set_attr "op_type" "RR") | |
7556 | (set_attr "type" "la")]) | |
7557 | ||
7558 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
7559 | [(set (match_operand 0 "register_operand" "=a") |
7560 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 7561 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 7562 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 UW |
7563 | "bras\t%0,%2" |
7564 | [(set_attr "op_type" "RI")]) | |
7565 | ||
7566 | (define_insn "main_base_64" | |
9e8327e3 UW |
7567 | [(set (match_operand 0 "register_operand" "=a") |
7568 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
7569 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
7570 | "larl\t%0,%1" |
7571 | [(set_attr "op_type" "RIL") | |
7572 | (set_attr "type" "larl")]) | |
7573 | ||
7574 | (define_insn "main_pool" | |
585539a1 UW |
7575 | [(set (match_operand 0 "register_operand" "=a") |
7576 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
7577 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
7578 | { |
7579 | gcc_unreachable (); | |
7580 | } | |
b628bd8e | 7581 | [(set (attr "type") |
ea77e738 UW |
7582 | (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0)) |
7583 | (const_string "larl") (const_string "la")))]) | |
5af2f3d3 | 7584 | |
aee4e0db | 7585 | (define_insn "reload_base_31" |
9e8327e3 UW |
7586 | [(set (match_operand 0 "register_operand" "=a") |
7587 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
7588 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7589 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e UW |
7590 | [(set_attr "length" "6") |
7591 | (set_attr "type" "la")]) | |
b2ccb744 | 7592 | |
aee4e0db | 7593 | (define_insn "reload_base_64" |
9e8327e3 UW |
7594 | [(set (match_operand 0 "register_operand" "=a") |
7595 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
7596 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7597 | "larl\t%0,%1" |
aee4e0db | 7598 | [(set_attr "op_type" "RIL") |
077dab3b | 7599 | (set_attr "type" "larl")]) |
aee4e0db | 7600 | |
aee4e0db | 7601 | (define_insn "pool" |
fd7643fb | 7602 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 7603 | "" |
8d933e31 AS |
7604 | { |
7605 | gcc_unreachable (); | |
7606 | } | |
b628bd8e | 7607 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 7608 | |
4023fb28 UW |
7609 | ;; |
7610 | ;; Insns related to generating the function prologue and epilogue. | |
7611 | ;; | |
7612 | ||
7613 | ||
7614 | (define_expand "prologue" | |
7615 | [(use (const_int 0))] | |
7616 | "" | |
10bbf137 | 7617 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
7618 | |
7619 | (define_expand "epilogue" | |
7620 | [(use (const_int 1))] | |
7621 | "" | |
ed9676cf AK |
7622 | "s390_emit_epilogue (false); DONE;") |
7623 | ||
7624 | (define_expand "sibcall_epilogue" | |
7625 | [(use (const_int 0))] | |
7626 | "" | |
7627 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 7628 | |
9e8327e3 | 7629 | (define_insn "*return" |
4023fb28 | 7630 | [(return) |
9e8327e3 UW |
7631 | (use (match_operand 0 "register_operand" "a"))] |
7632 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 7633 | "br\t%0" |
4023fb28 | 7634 | [(set_attr "op_type" "RR") |
c7453384 | 7635 | (set_attr "type" "jsr") |
077dab3b | 7636 | (set_attr "atype" "agen")]) |
4023fb28 | 7637 | |
4023fb28 | 7638 | |
c7453384 | 7639 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 7640 | ;; pointer. This is used for compatibility. |
c7453384 EC |
7641 | |
7642 | (define_expand "ptr_extend" | |
7643 | [(set (match_operand:DI 0 "register_operand" "=r") | |
7644 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 7645 | "TARGET_64BIT" |
c7453384 | 7646 | { |
c7453384 EC |
7647 | emit_insn (gen_anddi3 (operands[0], |
7648 | gen_lowpart (DImode, operands[1]), | |
7649 | GEN_INT (0x7fffffff))); | |
c7453384 | 7650 | DONE; |
10bbf137 | 7651 | }) |
4798630c D |
7652 | |
7653 | ;; Instruction definition to expand eh_return macro to support | |
7654 | ;; swapping in special linkage return addresses. | |
7655 | ||
7656 | (define_expand "eh_return" | |
7657 | [(use (match_operand 0 "register_operand" ""))] | |
7658 | "TARGET_TPF" | |
7659 | { | |
7660 | s390_emit_tpf_eh_return (operands[0]); | |
7661 | DONE; | |
7662 | }) | |
7663 | ||
7b8acc34 AK |
7664 | ; |
7665 | ; Stack Protector Patterns | |
7666 | ; | |
7667 | ||
7668 | (define_expand "stack_protect_set" | |
7669 | [(set (match_operand 0 "memory_operand" "") | |
7670 | (match_operand 1 "memory_operand" ""))] | |
7671 | "" | |
7672 | { | |
7673 | #ifdef TARGET_THREAD_SSP_OFFSET | |
7674 | operands[1] | |
7675 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
7676 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
7677 | #endif | |
7678 | if (TARGET_64BIT) | |
7679 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
7680 | else | |
7681 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
7682 | ||
7683 | DONE; | |
7684 | }) | |
7685 | ||
7686 | (define_insn "stack_protect_set<mode>" | |
7687 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
7688 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
7689 | "" | |
7690 | "mvc\t%O0(%G0,%R0),%S1" | |
7691 | [(set_attr "op_type" "SS")]) | |
7692 | ||
7693 | (define_expand "stack_protect_test" | |
7694 | [(set (reg:CC CC_REGNUM) | |
7695 | (compare (match_operand 0 "memory_operand" "") | |
7696 | (match_operand 1 "memory_operand" ""))) | |
7697 | (match_operand 2 "" "")] | |
7698 | "" | |
7699 | { | |
7700 | #ifdef TARGET_THREAD_SSP_OFFSET | |
7701 | operands[1] | |
7702 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
7703 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
7704 | #endif | |
7705 | s390_compare_op0 = operands[0]; | |
7706 | s390_compare_op1 = operands[1]; | |
7707 | s390_compare_emitted = gen_rtx_REG (CCZmode, CC_REGNUM); | |
7708 | ||
7709 | if (TARGET_64BIT) | |
7710 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
7711 | else | |
7712 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
7713 | ||
7714 | emit_jump_insn (gen_beq (operands[2])); | |
7715 | ||
7716 | DONE; | |
7717 | }) | |
7718 | ||
7719 | (define_insn "stack_protect_test<mode>" | |
7720 | [(set (reg:CCZ CC_REGNUM) | |
7721 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
7722 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
7723 | "" | |
7724 | "clc\t%O0(%G0,%R0),%S1" | |
7725 | [(set_attr "op_type" "SS")]) |