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Commit | Line | Data |
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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
a5544970 | 2 | ;; Copyright (C) 1999-2019 Free Software Foundation, Inc. |
9db1d521 | 3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
4 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
5 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | ;; version. |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
22 | |
23 | ;; | |
cd8dc1f9 | 24 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 25 | ;; |
cd8dc1f9 | 26 | |
9db1d521 HP |
27 | ;; Special formats used for outputting 390 instructions. |
28 | ;; | |
f19a9af7 AK |
29 | ;; %C: print opcode suffix for branch condition. |
30 | ;; %D: print opcode suffix for inverse branch condition. | |
31 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 32 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
33 | ;; %O: print only the displacement of a memory reference. |
34 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 35 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
36 | ;; %N: print the second word of a DImode operand. |
37 | ;; %M: print the second word of a TImode operand. | |
da48f5ec | 38 | ;; %Y: print shift count operand. |
f4aa3848 | 39 | ;; |
f19a9af7 | 40 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 41 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
42 | ;; %x: print integer X as if it's an unsigned halfword. |
43 | ;; %h: print integer X as if it's a signed halfword. | |
44 | ;; %i: print the first nonzero HImode part of X. | |
45 | ;; %j: print the first HImode part unequal to -1 of X. | |
46 | ;; %k: print the first nonzero SImode part of X. | |
47 | ;; %m: print the first SImode part unequal to -1 of X. | |
48 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
49 | ;; |
50 | ;; We have a special constraint for pattern matching. | |
51 | ;; | |
52 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
53 | ;; | |
9db1d521 | 54 | |
fd3cd001 UW |
55 | ;; |
56 | ;; UNSPEC usage | |
57 | ;; | |
58 | ||
30a49b23 AK |
59 | (define_c_enum "unspec" [ |
60 | ; Miscellaneous | |
61 | UNSPEC_ROUND | |
30a49b23 AK |
62 | UNSPEC_ICM |
63 | UNSPEC_TIE | |
10bbf137 | 64 | |
5a3fe9b6 AK |
65 | ; Convert CC into a str comparison result and copy it into an |
66 | ; integer register | |
67 | ; cc0->0, cc1->1, cc2->-1, (cc3->-1) | |
68 | UNSPEC_STRCMPCC_TO_INT | |
69 | ||
70 | ; Copy CC as is into the lower 2 bits of an integer register | |
71 | UNSPEC_CC_TO_INT | |
72 | ||
da0dcab1 DV |
73 | ; The right hand side of an setmem |
74 | UNSPEC_REPLICATE_BYTE | |
75 | ||
10bbf137 | 76 | ; GOT/PLT and lt-relative accesses |
30a49b23 | 77 | UNSPEC_LTREL_OFFSET |
30a49b23 AK |
78 | UNSPEC_POOL_OFFSET |
79 | UNSPEC_GOTENT | |
80 | UNSPEC_GOT | |
81 | UNSPEC_GOTOFF | |
82 | UNSPEC_PLT | |
83 | UNSPEC_PLTOFF | |
fd7643fb UW |
84 | |
85 | ; Literal pool | |
30a49b23 AK |
86 | UNSPEC_RELOAD_BASE |
87 | UNSPEC_MAIN_BASE | |
88 | UNSPEC_LTREF | |
89 | UNSPEC_INSN | |
90 | UNSPEC_EXECUTE | |
84b4c7b5 | 91 | UNSPEC_EXECUTE_JUMP |
fd7643fb | 92 | |
1a8c13b3 | 93 | ; Atomic Support |
30a49b23 | 94 | UNSPEC_MB |
78ce265b | 95 | UNSPEC_MOVA |
1a8c13b3 | 96 | |
fd7643fb | 97 | ; TLS relocation specifiers |
30a49b23 AK |
98 | UNSPEC_TLSGD |
99 | UNSPEC_TLSLDM | |
100 | UNSPEC_NTPOFF | |
101 | UNSPEC_DTPOFF | |
102 | UNSPEC_GOTNTPOFF | |
103 | UNSPEC_INDNTPOFF | |
fd3cd001 UW |
104 | |
105 | ; TLS support | |
30a49b23 AK |
106 | UNSPEC_TLSLDM_NTPOFF |
107 | UNSPEC_TLS_LOAD | |
91d39d71 UW |
108 | |
109 | ; String Functions | |
30a49b23 AK |
110 | UNSPEC_SRST |
111 | UNSPEC_MVST | |
638e37c2 | 112 | |
7b8acc34 | 113 | ; Stack Smashing Protector |
30a49b23 AK |
114 | UNSPEC_SP_SET |
115 | UNSPEC_SP_TEST | |
85dae55a | 116 | |
4cb4721f MK |
117 | ; Split stack support |
118 | UNSPEC_STACK_CHECK | |
119 | ||
638e37c2 | 120 | ; Test Data Class (TDC) |
30a49b23 | 121 | UNSPEC_TDC_INSN |
65b1d8ea AK |
122 | |
123 | ; Population Count | |
30a49b23 AK |
124 | UNSPEC_POPCNT |
125 | UNSPEC_COPYSIGN | |
d12a76f3 AK |
126 | |
127 | ; Load FP Integer | |
128 | UNSPEC_FPINT_FLOOR | |
129 | UNSPEC_FPINT_BTRUNC | |
130 | UNSPEC_FPINT_ROUND | |
131 | UNSPEC_FPINT_CEIL | |
132 | UNSPEC_FPINT_NEARBYINT | |
133 | UNSPEC_FPINT_RINT | |
085261c8 | 134 | |
3af82a61 AK |
135 | UNSPEC_LCBB |
136 | ||
085261c8 | 137 | ; Vector |
3af82a61 AK |
138 | UNSPEC_VEC_SMULT_HI |
139 | UNSPEC_VEC_UMULT_HI | |
140 | UNSPEC_VEC_SMULT_LO | |
085261c8 AK |
141 | UNSPEC_VEC_SMULT_EVEN |
142 | UNSPEC_VEC_UMULT_EVEN | |
143 | UNSPEC_VEC_SMULT_ODD | |
144 | UNSPEC_VEC_UMULT_ODD | |
3af82a61 AK |
145 | |
146 | UNSPEC_VEC_VMAL | |
147 | UNSPEC_VEC_VMAH | |
148 | UNSPEC_VEC_VMALH | |
149 | UNSPEC_VEC_VMAE | |
150 | UNSPEC_VEC_VMALE | |
151 | UNSPEC_VEC_VMAO | |
152 | UNSPEC_VEC_VMALO | |
153 | ||
154 | UNSPEC_VEC_GATHER | |
155 | UNSPEC_VEC_EXTRACT | |
156 | UNSPEC_VEC_INSERT_AND_ZERO | |
157 | UNSPEC_VEC_LOAD_BNDRY | |
085261c8 | 158 | UNSPEC_VEC_LOAD_LEN |
76794c52 | 159 | UNSPEC_VEC_LOAD_LEN_R |
3af82a61 AK |
160 | UNSPEC_VEC_MERGEH |
161 | UNSPEC_VEC_MERGEL | |
162 | UNSPEC_VEC_PACK | |
163 | UNSPEC_VEC_PACK_SATURATE | |
164 | UNSPEC_VEC_PACK_SATURATE_CC | |
165 | UNSPEC_VEC_PACK_SATURATE_GENCC | |
166 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE | |
167 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC | |
168 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC | |
169 | UNSPEC_VEC_PERM | |
170 | UNSPEC_VEC_PERMI | |
171 | UNSPEC_VEC_EXTEND | |
172 | UNSPEC_VEC_STORE_LEN | |
76794c52 AK |
173 | UNSPEC_VEC_STORE_LEN_R |
174 | UNSPEC_VEC_VBPERM | |
3af82a61 AK |
175 | UNSPEC_VEC_UNPACKH |
176 | UNSPEC_VEC_UNPACKH_L | |
177 | UNSPEC_VEC_UNPACKL | |
178 | UNSPEC_VEC_UNPACKL_L | |
179 | UNSPEC_VEC_ADDC | |
3af82a61 AK |
180 | UNSPEC_VEC_ADDE_U128 |
181 | UNSPEC_VEC_ADDEC_U128 | |
182 | UNSPEC_VEC_AVG | |
183 | UNSPEC_VEC_AVGU | |
184 | UNSPEC_VEC_CHECKSUM | |
185 | UNSPEC_VEC_GFMSUM | |
186 | UNSPEC_VEC_GFMSUM_128 | |
187 | UNSPEC_VEC_GFMSUM_ACCUM | |
188 | UNSPEC_VEC_GFMSUM_ACCUM_128 | |
189 | UNSPEC_VEC_SET | |
190 | ||
191 | UNSPEC_VEC_VSUMG | |
192 | UNSPEC_VEC_VSUMQ | |
193 | UNSPEC_VEC_VSUM | |
194 | UNSPEC_VEC_RL_MASK | |
195 | UNSPEC_VEC_SLL | |
196 | UNSPEC_VEC_SLB | |
197 | UNSPEC_VEC_SLDB | |
198 | UNSPEC_VEC_SRAL | |
199 | UNSPEC_VEC_SRAB | |
200 | UNSPEC_VEC_SRL | |
201 | UNSPEC_VEC_SRLB | |
202 | ||
3af82a61 | 203 | UNSPEC_VEC_SUBC |
3af82a61 AK |
204 | UNSPEC_VEC_SUBE_U128 |
205 | UNSPEC_VEC_SUBEC_U128 | |
206 | ||
207 | UNSPEC_VEC_TEST_MASK | |
208 | ||
209 | UNSPEC_VEC_VFAE | |
210 | UNSPEC_VEC_VFAECC | |
211 | ||
212 | UNSPEC_VEC_VFEE | |
213 | UNSPEC_VEC_VFEECC | |
085261c8 AK |
214 | UNSPEC_VEC_VFENE |
215 | UNSPEC_VEC_VFENECC | |
3af82a61 AK |
216 | |
217 | UNSPEC_VEC_VISTR | |
218 | UNSPEC_VEC_VISTRCC | |
219 | ||
220 | UNSPEC_VEC_VSTRC | |
221 | UNSPEC_VEC_VSTRCCC | |
222 | ||
223 | UNSPEC_VEC_VCDGB | |
224 | UNSPEC_VEC_VCDLGB | |
225 | ||
226 | UNSPEC_VEC_VCGDB | |
227 | UNSPEC_VEC_VCLGDB | |
228 | ||
76794c52 | 229 | UNSPEC_VEC_VFI |
3af82a61 | 230 | |
76794c52 AK |
231 | UNSPEC_VEC_VFLL ; vector fp load lengthened |
232 | UNSPEC_VEC_VFLR ; vector fp load rounded | |
3af82a61 | 233 | |
76794c52 AK |
234 | UNSPEC_VEC_VFTCI |
235 | UNSPEC_VEC_VFTCICC | |
236 | ||
237 | UNSPEC_VEC_MSUM | |
238 | ||
239 | UNSPEC_VEC_VFMIN | |
240 | UNSPEC_VEC_VFMAX | |
085261c8 | 241 | ]) |
fd3cd001 UW |
242 | |
243 | ;; | |
244 | ;; UNSPEC_VOLATILE usage | |
245 | ;; | |
246 | ||
30a49b23 AK |
247 | (define_c_enum "unspecv" [ |
248 | ; Blockage | |
249 | UNSPECV_BLOCKAGE | |
10bbf137 | 250 | |
2f7e5a0d | 251 | ; TPF Support |
30a49b23 AK |
252 | UNSPECV_TPF_PROLOGUE |
253 | UNSPECV_TPF_EPILOGUE | |
2f7e5a0d | 254 | |
10bbf137 | 255 | ; Literal pool |
30a49b23 AK |
256 | UNSPECV_POOL |
257 | UNSPECV_POOL_SECTION | |
258 | UNSPECV_POOL_ALIGN | |
259 | UNSPECV_POOL_ENTRY | |
260 | UNSPECV_MAIN_POOL | |
fd7643fb UW |
261 | |
262 | ; TLS support | |
30a49b23 | 263 | UNSPECV_SET_TP |
e0374221 AS |
264 | |
265 | ; Atomic Support | |
30a49b23 AK |
266 | UNSPECV_CAS |
267 | UNSPECV_ATOMIC_OP | |
5a3fe9b6 | 268 | |
aad98a61 AK |
269 | ; Non-branch nops used for compare-and-branch adjustments on z10 |
270 | UNSPECV_NOP_LR_0 | |
271 | UNSPECV_NOP_LR_1 | |
272 | ||
f8af0e30 DV |
273 | ; Hotpatching (unremovable NOPs) |
274 | UNSPECV_NOP_2_BYTE | |
275 | UNSPECV_NOP_4_BYTE | |
276 | UNSPECV_NOP_6_BYTE | |
277 | ||
5a3fe9b6 AK |
278 | ; Transactional Execution support |
279 | UNSPECV_TBEGIN | |
2561451d | 280 | UNSPECV_TBEGIN_TDB |
5a3fe9b6 AK |
281 | UNSPECV_TBEGINC |
282 | UNSPECV_TEND | |
283 | UNSPECV_TABORT | |
284 | UNSPECV_ETND | |
285 | UNSPECV_NTSTG | |
286 | UNSPECV_PPA | |
004f64e1 AK |
287 | |
288 | ; Set and get floating point control register | |
289 | UNSPECV_SFPC | |
290 | UNSPECV_EFPC | |
4cb4721f MK |
291 | |
292 | ; Split stack support | |
293 | UNSPECV_SPLIT_STACK_CALL | |
294 | UNSPECV_SPLIT_STACK_DATA | |
539405d5 AK |
295 | |
296 | UNSPECV_OSC_BREAK | |
fd3cd001 UW |
297 | ]) |
298 | ||
ae156f85 AS |
299 | ;; |
300 | ;; Registers | |
301 | ;; | |
302 | ||
35dd9a0e AK |
303 | ; Registers with special meaning |
304 | ||
ae156f85 AS |
305 | (define_constants |
306 | [ | |
307 | ; Sibling call register. | |
308 | (SIBCALL_REGNUM 1) | |
84b4c7b5 AK |
309 | ; A call-clobbered reg which can be used in indirect branch thunks |
310 | (INDIRECT_BRANCH_THUNK_REGNUM 1) | |
ae156f85 AS |
311 | ; Literal pool base register. |
312 | (BASE_REGNUM 13) | |
313 | ; Return address register. | |
314 | (RETURN_REGNUM 14) | |
82c6f58a AK |
315 | ; Stack pointer register. |
316 | (STACK_REGNUM 15) | |
ae156f85 AS |
317 | ; Condition code register. |
318 | (CC_REGNUM 33) | |
f4aa3848 | 319 | ; Thread local storage pointer register. |
ae156f85 AS |
320 | (TP_REGNUM 36) |
321 | ]) | |
322 | ||
35dd9a0e AK |
323 | ; Hardware register names |
324 | ||
325 | (define_constants | |
326 | [ | |
327 | ; General purpose registers | |
328 | (GPR0_REGNUM 0) | |
af344a30 | 329 | (GPR1_REGNUM 1) |
82379bdf AK |
330 | (GPR2_REGNUM 2) |
331 | (GPR6_REGNUM 6) | |
35dd9a0e AK |
332 | ; Floating point registers. |
333 | (FPR0_REGNUM 16) | |
2cf4c39e AK |
334 | (FPR1_REGNUM 20) |
335 | (FPR2_REGNUM 17) | |
336 | (FPR3_REGNUM 21) | |
337 | (FPR4_REGNUM 18) | |
338 | (FPR5_REGNUM 22) | |
339 | (FPR6_REGNUM 19) | |
340 | (FPR7_REGNUM 23) | |
341 | (FPR8_REGNUM 24) | |
342 | (FPR9_REGNUM 28) | |
343 | (FPR10_REGNUM 25) | |
344 | (FPR11_REGNUM 29) | |
345 | (FPR12_REGNUM 26) | |
346 | (FPR13_REGNUM 30) | |
347 | (FPR14_REGNUM 27) | |
348 | (FPR15_REGNUM 31) | |
085261c8 AK |
349 | (VR0_REGNUM 16) |
350 | (VR16_REGNUM 38) | |
351 | (VR23_REGNUM 45) | |
352 | (VR24_REGNUM 46) | |
353 | (VR31_REGNUM 53) | |
35dd9a0e AK |
354 | ]) |
355 | ||
ae8e301e AK |
356 | ; Rounding modes for binary floating point numbers |
357 | (define_constants | |
358 | [(BFP_RND_CURRENT 0) | |
359 | (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1) | |
360 | (BFP_RND_PREP_FOR_SHORT_PREC 3) | |
361 | (BFP_RND_NEAREST_TIE_TO_EVEN 4) | |
362 | (BFP_RND_TOWARD_0 5) | |
363 | (BFP_RND_TOWARD_INF 6) | |
364 | (BFP_RND_TOWARD_MINF 7)]) | |
365 | ||
366 | ; Rounding modes for decimal floating point numbers | |
367 | ; 1-7 were introduced with the floating point extension facility | |
368 | ; available with z196 | |
369 | ; With these rounding modes (1-7) a quantum exception might occur | |
370 | ; which is suppressed for the other modes. | |
371 | (define_constants | |
372 | [(DFP_RND_CURRENT 0) | |
373 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1) | |
374 | (DFP_RND_CURRENT_QUANTEXC 2) | |
375 | (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC 3) | |
376 | (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC 4) | |
377 | (DFP_RND_TOWARD_0_QUANTEXC 5) | |
378 | (DFP_RND_TOWARD_INF_QUANTEXC 6) | |
379 | (DFP_RND_TOWARD_MINF_QUANTEXC 7) | |
380 | (DFP_RND_NEAREST_TIE_TO_EVEN 8) | |
381 | (DFP_RND_TOWARD_0 9) | |
382 | (DFP_RND_TOWARD_INF 10) | |
383 | (DFP_RND_TOWARD_MINF 11) | |
384 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0 12) | |
385 | (DFP_RND_NEAREST_TIE_TO_0 13) | |
386 | (DFP_RND_AWAY_FROM_0 14) | |
387 | (DFP_RND_PREP_FOR_SHORT_PREC 15)]) | |
388 | ||
35dd9a0e AK |
389 | ;; |
390 | ;; PFPO GPR0 argument format | |
391 | ;; | |
392 | ||
393 | (define_constants | |
394 | [ | |
395 | ; PFPO operation type | |
396 | (PFPO_CONVERT 0x1000000) | |
397 | ; PFPO operand types | |
398 | (PFPO_OP_TYPE_SF 0x5) | |
399 | (PFPO_OP_TYPE_DF 0x6) | |
400 | (PFPO_OP_TYPE_TF 0x7) | |
401 | (PFPO_OP_TYPE_SD 0x8) | |
402 | (PFPO_OP_TYPE_DD 0x9) | |
403 | (PFPO_OP_TYPE_TD 0xa) | |
404 | ; Bitposition of operand types | |
405 | (PFPO_OP0_TYPE_SHIFT 16) | |
406 | (PFPO_OP1_TYPE_SHIFT 8) | |
ced8d882 AK |
407 | ; Decide whether current DFP or BFD rounding mode should be used |
408 | ; for the conversion. | |
409 | (PFPO_RND_MODE_DFP 0) | |
410 | (PFPO_RND_MODE_BFP 1) | |
35dd9a0e AK |
411 | ]) |
412 | ||
291a9e98 AK |
413 | ;; PPA constants |
414 | ||
415 | ; Immediate values which can be used as the third operand to the | |
416 | ; perform processor assist instruction | |
417 | ||
418 | (define_constants | |
419 | [(PPA_TX_ABORT 1) | |
420 | (PPA_OOO_BARRIER 15)]) | |
421 | ||
5a3fe9b6 AK |
422 | ; Immediate operands for tbegin and tbeginc |
423 | (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c | |
424 | (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08 | |
fd3cd001 | 425 | |
29a74354 UW |
426 | ;; Instruction operand type as used in the Principles of Operation. |
427 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 428 | |
29a74354 | 429 | (define_attr "op_type" |
76794c52 | 430 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX,VSI" |
b628bd8e | 431 | (const_string "NN")) |
9db1d521 | 432 | |
29a74354 | 433 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 434 | |
077dab3b | 435 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 436 | cs,vs,store,sem,idiv, |
ed0e512a | 437 | imulhi,imulsi,imuldi, |
2cdece44 | 438 | branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, |
f61a2c7d AK |
439 | floadtf,floaddf,floadsf,fstoredf,fstoresf, |
440 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 | 441 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
65b1d8ea | 442 | fmadddf,fmaddsf, |
9381e3f1 WG |
443 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, |
444 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
445 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
446 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
447 | ftoidfp, other" | |
29a74354 UW |
448 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
449 | (eq_attr "op_type" "SS") (const_string "cs")] | |
450 | (const_string "integer"))) | |
9db1d521 | 451 | |
29a74354 UW |
452 | ;; Another attribute used for scheduling purposes: |
453 | ;; agen: Instruction uses the address generation unit | |
454 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
455 | |
456 | (define_attr "atype" "agen,reg" | |
62d3f261 | 457 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF") |
0101708c AS |
458 | (const_string "reg") |
459 | (const_string "agen"))) | |
9db1d521 | 460 | |
9381e3f1 WG |
461 | ;; Properties concerning Z10 execution grouping and value forwarding. |
462 | ;; z10_super: instruction is superscalar. | |
463 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
464 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
465 | ;; target register. It can forward this value to a second instruction that reads | |
466 | ;; the same register if that second instruction is issued in the same group. | |
467 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
468 | ;; instruction in the S pipe writes to the register, then the T instruction | |
469 | ;; can immediately read the new value. | |
470 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
471 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
9381e3f1 WG |
472 | ;; |
473 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
474 | ||
475 | ||
476 | (define_attr "z10prop" "none, | |
477 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
478 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
479 | z10_rec, | |
480 | z10_fr, z10_fr_A3, z10_fr_E1, | |
e3cba5e5 | 481 | z10_c" |
9381e3f1 WG |
482 | (const_string "none")) |
483 | ||
65b1d8ea AK |
484 | ;; Properties concerning Z196 decoding |
485 | ;; z196_alone: must group alone | |
486 | ;; z196_end: ends a group | |
487 | ;; z196_cracked: instruction is cracked or expanded | |
488 | (define_attr "z196prop" "none, | |
489 | z196_alone, z196_ends, | |
490 | z196_cracked" | |
491 | (const_string "none")) | |
9381e3f1 | 492 | |
84b4c7b5 AK |
493 | ; mnemonics which only get defined through if_then_else currently |
494 | ; don't get added to the list values automatically and hence need to | |
495 | ; be listed here. | |
8cc6307c | 496 | (define_attr "mnemonic" "b,bas,basr,bc,bcr_flush,unknown" (const_string "unknown")) |
22ac2c2f | 497 | |
9db1d521 HP |
498 | ;; Length in bytes. |
499 | ||
500 | (define_attr "length" "" | |
62d3f261 AK |
501 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
502 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)] | |
b628bd8e | 503 | (const_int 6))) |
9db1d521 | 504 | |
29a74354 UW |
505 | |
506 | ;; Processor type. This attribute must exactly match the processor_type | |
52d4aa4f | 507 | ;; enumeration in s390.h. |
29a74354 | 508 | |
e9e8efc9 | 509 | (define_attr "cpu" "z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,z14" |
90c6fd8a | 510 | (const (symbol_ref "s390_tune_attr"))) |
29a74354 | 511 | |
b5e0425c | 512 | (define_attr "cpu_facility" |
e9e8efc9 | 513 | "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,z14,vxe" |
3af8e996 AK |
514 | (const_string "standard")) |
515 | ||
516 | (define_attr "enabled" "" | |
517 | (cond [(eq_attr "cpu_facility" "standard") | |
518 | (const_int 1) | |
519 | ||
520 | (and (eq_attr "cpu_facility" "ieee") | |
d7f99b2c | 521 | (match_test "TARGET_CPU_IEEE_FLOAT")) |
3af8e996 AK |
522 | (const_int 1) |
523 | ||
524 | (and (eq_attr "cpu_facility" "zarch") | |
d7f99b2c | 525 | (match_test "TARGET_ZARCH")) |
3af8e996 AK |
526 | (const_int 1) |
527 | ||
528 | (and (eq_attr "cpu_facility" "longdisp") | |
d7f99b2c | 529 | (match_test "TARGET_LONG_DISPLACEMENT")) |
3af8e996 AK |
530 | (const_int 1) |
531 | ||
532 | (and (eq_attr "cpu_facility" "extimm") | |
d7f99b2c | 533 | (match_test "TARGET_EXTIMM")) |
3af8e996 AK |
534 | (const_int 1) |
535 | ||
536 | (and (eq_attr "cpu_facility" "dfp") | |
d7f99b2c | 537 | (match_test "TARGET_DFP")) |
93538e8e AK |
538 | (const_int 1) |
539 | ||
8cc6307c | 540 | (eq_attr "cpu_facility" "cpu_zarch") |
b5e0425c AK |
541 | (const_int 1) |
542 | ||
93538e8e | 543 | (and (eq_attr "cpu_facility" "z10") |
d7f99b2c | 544 | (match_test "TARGET_Z10")) |
65b1d8ea AK |
545 | (const_int 1) |
546 | ||
547 | (and (eq_attr "cpu_facility" "z196") | |
d7f99b2c | 548 | (match_test "TARGET_Z196")) |
22ac2c2f AK |
549 | (const_int 1) |
550 | ||
551 | (and (eq_attr "cpu_facility" "zEC12") | |
552 | (match_test "TARGET_ZEC12")) | |
55ac540c AK |
553 | (const_int 1) |
554 | ||
285363a1 | 555 | (and (eq_attr "cpu_facility" "vx") |
55ac540c | 556 | (match_test "TARGET_VX")) |
bf749919 DV |
557 | (const_int 1) |
558 | ||
559 | (and (eq_attr "cpu_facility" "z13") | |
560 | (match_test "TARGET_Z13")) | |
561 | (const_int 1) | |
6654e96f | 562 | |
e9e8efc9 AK |
563 | (and (eq_attr "cpu_facility" "z14") |
564 | (match_test "TARGET_Z14")) | |
6654e96f AK |
565 | (const_int 1) |
566 | ||
567 | (and (eq_attr "cpu_facility" "vxe") | |
568 | (match_test "TARGET_VXE")) | |
569 | (const_int 1) | |
bf749919 | 570 | ] |
3af8e996 AK |
571 | (const_int 0))) |
572 | ||
14cfceb7 IL |
573 | ;; Whether an instruction supports relative long addressing. |
574 | ;; Currently this corresponds to RIL-b and RIL-c instruction formats, | |
575 | ;; but having a separate attribute, as opposed to reusing op_type, | |
576 | ;; provides additional flexibility. | |
577 | ||
578 | (define_attr "relative_long" "no,yes" (const_string "no")) | |
579 | ||
52d4aa4f | 580 | ;; Pipeline description for z900. |
29a74354 UW |
581 | (include "2064.md") |
582 | ||
3443392a | 583 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
584 | (include "2084.md") |
585 | ||
9381e3f1 WG |
586 | ;; Pipeline description for z10 |
587 | (include "2097.md") | |
588 | ||
65b1d8ea AK |
589 | ;; Pipeline description for z196 |
590 | (include "2817.md") | |
591 | ||
22ac2c2f AK |
592 | ;; Pipeline description for zEC12 |
593 | (include "2827.md") | |
594 | ||
23902021 AK |
595 | ;; Pipeline description for z13 |
596 | (include "2964.md") | |
597 | ||
0bfc3f69 AS |
598 | ;; Predicates |
599 | (include "predicates.md") | |
600 | ||
cd8dc1f9 WG |
601 | ;; Constraint definitions |
602 | (include "constraints.md") | |
603 | ||
a8ba31f2 EC |
604 | ;; Other includes |
605 | (include "tpf.md") | |
f52c81dd | 606 | |
3abcb3a7 | 607 | ;; Iterators |
f52c81dd | 608 | |
085261c8 AK |
609 | (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF]) |
610 | ||
3abcb3a7 | 611 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 612 | ;; same template. |
f4aa3848 | 613 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
0387c142 | 614 | (SD "TARGET_HARD_DFP")]) |
3abcb3a7 HPN |
615 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
616 | (define_mode_iterator BFP [TF DF SF]) | |
617 | (define_mode_iterator DFP [TD DD]) | |
618 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
619 | (define_mode_iterator DSF [DF SF]) | |
620 | (define_mode_iterator SD_SF [SF SD]) | |
621 | (define_mode_iterator DD_DF [DF DD]) | |
622 | (define_mode_iterator TD_TF [TF TD]) | |
623 | ||
3abcb3a7 | 624 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 625 | ;; from the same template. |
9602b6a1 | 626 | (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) |
78ce265b | 627 | (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) |
3abcb3a7 | 628 | (define_mode_iterator DSI [DI SI]) |
78ce265b | 629 | (define_mode_iterator TDI [TI DI]) |
9db2f16d | 630 | |
3abcb3a7 | 631 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 632 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 | 633 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
9db2f16d | 634 | |
78ce265b RH |
635 | ;; These macros refer to the actual word_mode of the configuration. |
636 | ;; This is equal to Pmode except on 31-bit machines in zarch mode. | |
9602b6a1 AK |
637 | (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) |
638 | (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) | |
639 | ||
6e0d70c9 AK |
640 | ;; Used by the umul pattern to express modes having half the size. |
641 | (define_mode_attr DWH [(TI "DI") (DI "SI")]) | |
642 | (define_mode_attr dwh [(TI "di") (DI "si")]) | |
643 | ||
3abcb3a7 | 644 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 645 | ;; the same template. |
3abcb3a7 | 646 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 647 | |
3abcb3a7 | 648 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 649 | ;; same template. |
9602b6a1 | 650 | (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) |
78ce265b | 651 | (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) |
64c744b9 | 652 | (define_mode_iterator SINT [SI HI QI]) |
342cf42b | 653 | |
3abcb3a7 | 654 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 655 | ;; the same template. |
3abcb3a7 | 656 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 657 | |
d12a76f3 | 658 | ;; This iterator allows r[ox]sbg to be defined with the same template |
571e408a RH |
659 | (define_code_iterator IXOR [ior xor]) |
660 | ||
d12a76f3 AK |
661 | ;; This iterator is used to expand the patterns for the nearest |
662 | ;; integer functions. | |
663 | (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC | |
664 | UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL | |
665 | UNSPEC_FPINT_NEARBYINT]) | |
666 | (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor") | |
667 | (UNSPEC_FPINT_BTRUNC "btrunc") | |
668 | (UNSPEC_FPINT_ROUND "round") | |
669 | (UNSPEC_FPINT_CEIL "ceil") | |
670 | (UNSPEC_FPINT_NEARBYINT "nearbyint")]) | |
671 | (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7") | |
672 | (UNSPEC_FPINT_BTRUNC "5") | |
673 | (UNSPEC_FPINT_ROUND "1") | |
674 | (UNSPEC_FPINT_CEIL "6") | |
675 | (UNSPEC_FPINT_NEARBYINT "0")]) | |
676 | ||
3abcb3a7 HPN |
677 | ;; This iterator and attribute allow to combine most atomic operations. |
678 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
65b1d8ea | 679 | (define_code_iterator ATOMIC_Z196 [and ior xor plus]) |
cf5b43b0 | 680 | (define_code_attr atomic [(and "and") (ior "or") (xor "xor") |
45d18331 | 681 | (plus "add") (minus "sub") (mult "nand")]) |
65b1d8ea | 682 | (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) |
45d18331 | 683 | |
f4aa3848 | 684 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
609e7e80 AK |
685 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. |
686 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) | |
f337b930 | 687 | |
f4aa3848 AK |
688 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
689 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
609e7e80 AK |
690 | ;; SDmode. |
691 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 692 | |
609e7e80 | 693 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
694 | ;; Likewise for "<RXe>". |
695 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
696 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
697 | ||
609e7e80 | 698 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 699 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
700 | ;; dfp variants in a single insn definition. |
701 | ||
62d3f261 AK |
702 | ;; These mode attributes are supposed to be used in the `enabled' insn |
703 | ;; attribute to disable certain alternatives for certain modes. | |
704 | (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")]) | |
705 | (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")]) | |
706 | (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")]) | |
707 | (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0") | |
708 | (TD "0") (DD "0") (DD "0") | |
709 | (TI "0") (DI "*") (SI "0")]) | |
2de2b3f9 AK |
710 | (define_mode_attr DF [(TF "0") (DF "*") (SF "0") |
711 | (TD "0") (DD "0") (DD "0") | |
712 | (TI "0") (DI "0") (SI "0")]) | |
713 | (define_mode_attr SF [(TF "0") (DF "0") (SF "*") | |
714 | (TD "0") (DD "0") (DD "0") | |
715 | (TI "0") (DI "0") (SI "0")]) | |
f5905b37 | 716 | |
85dae55a AK |
717 | ;; This attribute is used in the operand constraint list |
718 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
719 | ;; TFmode values are represented by a fp register pair. Since the | |
720 | ;; sign bit instructions only handle single source and target fp registers | |
721 | ;; these instructions can only be used for TFmode values if the source and | |
722 | ;; target operand uses the same fp register. | |
723 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
724 | ||
3abcb3a7 | 725 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
726 | ;; within instruction mnemonics. |
727 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
728 | ||
0387c142 WG |
729 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
730 | ;; modes and to an empty string for bfp modes. | |
731 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
732 | ||
1b48c8cc AS |
733 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
734 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
735 | ;; version only operates on one register. | |
736 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
737 | ||
738 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
739 | ;; version only operates on one register. The DImode version needs an additional | |
740 | ;; register for the assembler output. | |
741 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
742 | |
743 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
744 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
745 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
746 | ||
747 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 748 | ;; pattern itself and the corresponding function calls. |
f337b930 | 749 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
750 | |
751 | ;; This attribute handles differences in the instruction 'type' and will result | |
752 | ;; in "RRE" for DImode and "RR" for SImode. | |
753 | (define_mode_attr E [(DI "E") (SI "")]) | |
754 | ||
3298c037 AK |
755 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
756 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
757 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
758 | ||
8006eaa6 AS |
759 | ;; This attribute handles differences in the instruction 'type' and will result |
760 | ;; in "RSE" for TImode and "RS" for DImode. | |
761 | (define_mode_attr TE [(TI "E") (DI "")]) | |
762 | ||
9a91a21f AS |
763 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
764 | ;; and "lcr" in SImode. | |
765 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 766 | |
3298c037 AK |
767 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
768 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
769 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
770 | ;; variant for long displacements. | |
771 | (define_mode_attr y [(DI "g") (SI "y")]) | |
772 | ||
9602b6a1 | 773 | ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode |
8006eaa6 AS |
774 | ;; and "cds" in DImode. |
775 | (define_mode_attr tg [(TI "g") (DI "")]) | |
776 | ||
78ce265b RH |
777 | ;; In TDI templates, a string like "c<d>sg". |
778 | (define_mode_attr td [(TI "d") (DI "")]) | |
779 | ||
2f8f8434 AS |
780 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
781 | ;; and "cfdbr" in SImode. | |
782 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
783 | ||
65b1d8ea AK |
784 | ;; In GPR templates, a string like sll<gk> will expand to sllg for DI |
785 | ;; and sllk for SI. This way it is possible to merge the new z196 SI | |
786 | ;; 3 operands shift instructions into the existing patterns. | |
787 | (define_mode_attr gk [(DI "g") (SI "k")]) | |
788 | ||
f52c81dd AS |
789 | ;; ICM mask required to load MODE value into the lowest subreg |
790 | ;; of a SImode register. | |
791 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
792 | ||
f6ee577c AS |
793 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
794 | ;; HImode and "llgc" in QImode. | |
795 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
796 | ||
a1aed706 AS |
797 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
798 | ;; in SImode. | |
799 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
800 | ||
609e7e80 AK |
801 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
802 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
803 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
804 | ||
f52c81dd AS |
805 | ;; Maximum unsigned integer that fits in MODE. |
806 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
807 | ||
75ca1b39 RH |
808 | ;; Start and end field computations for RISBG et al. |
809 | (define_mode_attr bfstart [(DI "s") (SI "t")]) | |
810 | (define_mode_attr bfend [(DI "e") (SI "f")]) | |
811 | ||
2542ef05 RH |
812 | ;; In place of GET_MODE_BITSIZE (<MODE>mode) |
813 | (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) | |
576987fc DV |
814 | ;; 64 - bitsize |
815 | (define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")]) | |
816 | (define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")]) | |
2542ef05 | 817 | |
da0dcab1 DV |
818 | ;; In place of GET_MODE_SIZE (<MODE>mode) |
819 | (define_mode_attr modesize [(DI "8") (SI "4")]) | |
820 | ||
177bc204 RS |
821 | ;; Allow return and simple_return to be defined from a single template. |
822 | (define_code_iterator ANY_RETURN [return simple_return]) | |
823 | ||
6e5b5de8 AK |
824 | |
825 | ||
826 | ; Condition code modes generated by vector fp comparisons. These will | |
827 | ; be used also in single element mode. | |
828 | (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE]) | |
829 | ; Used with VFCMP to expand part of the mnemonic | |
830 | ; For fp we have a mismatch: eq in the insn name - e in asm | |
831 | (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) | |
a6a2b532 | 832 | (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVIH "h") (CCVIHU "hl") (CCVFH "h") (CCVFHE "he")]) |
6e5b5de8 | 833 | |
191eb16d AK |
834 | ;; Subst pattern definitions |
835 | (include "subst.md") | |
6e5b5de8 | 836 | |
085261c8 AK |
837 | (include "vector.md") |
838 | ||
9db1d521 HP |
839 | ;; |
840 | ;;- Compare instructions. | |
841 | ;; | |
842 | ||
07893d4f | 843 | ; Test-under-Mask instructions |
9db1d521 | 844 | |
07893d4f | 845 | (define_insn "*tmqi_mem" |
ae156f85 | 846 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
847 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
848 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
849 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 850 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 851 | "@ |
fc0ea003 UW |
852 | tm\t%S0,%b1 |
853 | tmy\t%S0,%b1" | |
9381e3f1 | 854 | [(set_attr "op_type" "SI,SIY") |
3e4be43f | 855 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 856 | (set_attr "z10prop" "z10_super,z10_super")]) |
9db1d521 | 857 | |
05b9aaaa | 858 | (define_insn "*tmdi_reg" |
ae156f85 | 859 | [(set (reg CC_REGNUM) |
f19a9af7 | 860 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 861 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
862 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
863 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
9602b6a1 | 864 | "TARGET_ZARCH |
3ed99cc9 | 865 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
866 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
867 | "@ | |
868 | tmhh\t%0,%i1 | |
869 | tmhl\t%0,%i1 | |
870 | tmlh\t%0,%i1 | |
871 | tmll\t%0,%i1" | |
9381e3f1 WG |
872 | [(set_attr "op_type" "RI") |
873 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
874 | |
875 | (define_insn "*tmsi_reg" | |
ae156f85 | 876 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
877 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
878 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
879 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 880 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
881 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
882 | "@ | |
883 | tmh\t%0,%i1 | |
884 | tml\t%0,%i1" | |
729e750f WG |
885 | [(set_attr "op_type" "RI") |
886 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 887 | |
f52c81dd | 888 | (define_insn "*tm<mode>_full" |
ae156f85 | 889 | [(set (reg CC_REGNUM) |
f52c81dd AS |
890 | (compare (match_operand:HQI 0 "register_operand" "d") |
891 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 892 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 893 | "tml\t%0,<max_uint>" |
729e750f WG |
894 | [(set_attr "op_type" "RI") |
895 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 896 | |
07893d4f | 897 | |
08a5aaa2 | 898 | ; |
07893d4f | 899 | ; Load-and-Test instructions |
08a5aaa2 AS |
900 | ; |
901 | ||
c0220ea4 | 902 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
903 | |
904 | (define_insn "*tstdi_sign" | |
ae156f85 | 905 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
906 | (compare |
907 | (ashiftrt:DI | |
908 | (ashift:DI | |
3e4be43f | 909 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0) |
963fc8d0 AK |
910 | (const_int 32)) (const_int 32)) |
911 | (match_operand:DI 1 "const0_operand" ""))) | |
912 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f | 913 | (sign_extend:DI (match_dup 0)))] |
9602b6a1 | 914 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" |
963fc8d0 AK |
915 | "ltgfr\t%2,%0 |
916 | ltgf\t%2,%0" | |
917 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
918 | (set_attr "cpu_facility" "*,z10") |
919 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 920 | |
43a09b63 | 921 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 922 | (define_insn "*tst<mode>_extimm" |
ec24698e | 923 | [(set (reg CC_REGNUM) |
3e4be43f | 924 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") |
08a5aaa2 AS |
925 | (match_operand:GPR 1 "const0_operand" ""))) |
926 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 927 | (match_dup 0))] |
08a5aaa2 | 928 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 929 | "@ |
08a5aaa2 AS |
930 | lt<g>r\t%2,%0 |
931 | lt<g>\t%2,%0" | |
9381e3f1 | 932 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 933 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 934 | |
97160c9b DV |
935 | ; Peephole to combine a load-and-test from volatile memory which combine does |
936 | ; not do. | |
937 | (define_peephole2 | |
938 | [(set (match_operand:GPR 0 "register_operand") | |
939 | (match_operand:GPR 2 "memory_operand")) | |
940 | (set (reg CC_REGNUM) | |
941 | (compare (match_dup 0) (match_operand:GPR 1 "const0_operand")))] | |
942 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM | |
943 | && GENERAL_REG_P (operands[0]) | |
34a249bc IL |
944 | && satisfies_constraint_T (operands[2]) |
945 | && !contains_constant_pool_address_p (operands[2])" | |
97160c9b DV |
946 | [(parallel |
947 | [(set (reg:CCS CC_REGNUM) | |
948 | (compare:CCS (match_dup 2) (match_dup 1))) | |
949 | (set (match_dup 0) (match_dup 2))])]) | |
950 | ||
43a09b63 | 951 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 952 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 953 | [(set (reg CC_REGNUM) |
3e4be43f | 954 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") |
08a5aaa2 AS |
955 | (match_operand:GPR 1 "const0_operand" ""))) |
956 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
957 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 958 | "@ |
08a5aaa2 AS |
959 | lt<g>r\t%0,%0 |
960 | lt<g>\t%2,%0" | |
9381e3f1 | 961 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 962 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 963 | |
07893d4f | 964 | (define_insn "*tstdi" |
ae156f85 | 965 | [(set (reg CC_REGNUM) |
07893d4f UW |
966 | (compare (match_operand:DI 0 "register_operand" "d") |
967 | (match_operand:DI 1 "const0_operand" ""))) | |
968 | (set (match_operand:DI 2 "register_operand" "=d") | |
969 | (match_dup 0))] | |
9602b6a1 | 970 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 971 | "ltgr\t%2,%0" |
9381e3f1 WG |
972 | [(set_attr "op_type" "RRE") |
973 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 974 | |
07893d4f | 975 | (define_insn "*tstsi" |
ae156f85 | 976 | [(set (reg CC_REGNUM) |
d3632d41 | 977 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 978 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 979 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 980 | (match_dup 0))] |
ec24698e | 981 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 982 | "@ |
d40c829f | 983 | ltr\t%2,%0 |
fc0ea003 UW |
984 | icm\t%2,15,%S0 |
985 | icmy\t%2,15,%S0" | |
9381e3f1 | 986 | [(set_attr "op_type" "RR,RS,RSY") |
3e4be43f | 987 | (set_attr "cpu_facility" "*,*,longdisp") |
9381e3f1 | 988 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 989 | |
07893d4f | 990 | (define_insn "*tstsi_cconly" |
ae156f85 | 991 | [(set (reg CC_REGNUM) |
d3632d41 | 992 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 993 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 994 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
995 | "s390_match_ccmode(insn, CCSmode)" |
996 | "@ | |
d40c829f | 997 | ltr\t%0,%0 |
fc0ea003 UW |
998 | icm\t%2,15,%S0 |
999 | icmy\t%2,15,%S0" | |
9381e3f1 | 1000 | [(set_attr "op_type" "RR,RS,RSY") |
3e4be43f | 1001 | (set_attr "cpu_facility" "*,*,longdisp") |
9381e3f1 | 1002 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) |
4023fb28 | 1003 | |
08a5aaa2 AS |
1004 | (define_insn "*tstdi_cconly_31" |
1005 | [(set (reg CC_REGNUM) | |
1006 | (compare (match_operand:DI 0 "register_operand" "d") | |
1007 | (match_operand:DI 1 "const0_operand" "")))] | |
9602b6a1 | 1008 | "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" |
08a5aaa2 AS |
1009 | "srda\t%0,0" |
1010 | [(set_attr "op_type" "RS") | |
1011 | (set_attr "atype" "reg")]) | |
1012 | ||
43a09b63 | 1013 | ; ltr, ltgr |
08a5aaa2 | 1014 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 1015 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
1016 | (compare (match_operand:GPR 0 "register_operand" "d") |
1017 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 1018 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 1019 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
1020 | [(set_attr "op_type" "RR<E>") |
1021 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 1022 | |
c0220ea4 | 1023 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 1024 | |
f52c81dd | 1025 | (define_insn "*tst<mode>CCT" |
ae156f85 | 1026 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1027 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
1028 | (match_operand:HQI 1 "const0_operand" ""))) | |
1029 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
1030 | (match_dup 0))] |
1031 | "s390_match_ccmode(insn, CCTmode)" | |
1032 | "@ | |
f52c81dd AS |
1033 | icm\t%2,<icm_lo>,%S0 |
1034 | icmy\t%2,<icm_lo>,%S0 | |
1035 | tml\t%0,<max_uint>" | |
9381e3f1 | 1036 | [(set_attr "op_type" "RS,RSY,RI") |
3e4be43f | 1037 | (set_attr "cpu_facility" "*,longdisp,*") |
9381e3f1 | 1038 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) |
3af97654 UW |
1039 | |
1040 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 1041 | [(set (reg CC_REGNUM) |
d3632d41 | 1042 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 1043 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 1044 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
1045 | "s390_match_ccmode(insn, CCTmode)" |
1046 | "@ | |
fc0ea003 UW |
1047 | icm\t%2,3,%S0 |
1048 | icmy\t%2,3,%S0 | |
d40c829f | 1049 | tml\t%0,65535" |
9381e3f1 | 1050 | [(set_attr "op_type" "RS,RSY,RI") |
3e4be43f | 1051 | (set_attr "cpu_facility" "*,longdisp,*") |
9381e3f1 | 1052 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) |
3af97654 | 1053 | |
3af97654 | 1054 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 1055 | [(set (reg CC_REGNUM) |
d3632d41 | 1056 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
1057 | (match_operand:QI 1 "const0_operand" "")))] |
1058 | "s390_match_ccmode(insn, CCTmode)" | |
1059 | "@ | |
fc0ea003 UW |
1060 | cli\t%S0,0 |
1061 | cliy\t%S0,0 | |
d40c829f | 1062 | tml\t%0,255" |
9381e3f1 | 1063 | [(set_attr "op_type" "SI,SIY,RI") |
3e4be43f | 1064 | (set_attr "cpu_facility" "*,longdisp,*") |
729e750f | 1065 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 1066 | |
f52c81dd | 1067 | (define_insn "*tst<mode>" |
ae156f85 | 1068 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1069 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1070 | (match_operand:HQI 1 "const0_operand" ""))) | |
1071 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
1072 | (match_dup 0))] |
1073 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 1074 | "@ |
f52c81dd AS |
1075 | icm\t%2,<icm_lo>,%S0 |
1076 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 | 1077 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 1078 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1079 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 | 1080 | |
f52c81dd | 1081 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 1082 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1083 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1084 | (match_operand:HQI 1 "const0_operand" ""))) | |
1085 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 1086 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 1087 | "@ |
f52c81dd AS |
1088 | icm\t%2,<icm_lo>,%S0 |
1089 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 | 1090 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 1091 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1092 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
d3632d41 | 1093 | |
9db1d521 | 1094 | |
575f7c2b UW |
1095 | ; Compare (equality) instructions |
1096 | ||
1097 | (define_insn "*cmpdi_cct" | |
ae156f85 | 1098 | [(set (reg CC_REGNUM) |
ec24698e | 1099 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
3e4be43f | 1100 | (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))] |
9602b6a1 | 1101 | "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" |
575f7c2b UW |
1102 | "@ |
1103 | cgr\t%0,%1 | |
f4f41b4e | 1104 | cghi\t%0,%h1 |
ec24698e | 1105 | cgfi\t%0,%1 |
575f7c2b | 1106 | cg\t%0,%1 |
19b63d8e | 1107 | #" |
9381e3f1 WG |
1108 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
1109 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
1110 | |
1111 | (define_insn "*cmpsi_cct" | |
ae156f85 | 1112 | [(set (reg CC_REGNUM) |
ec24698e UW |
1113 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
1114 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 1115 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
1116 | "@ |
1117 | cr\t%0,%1 | |
f4f41b4e | 1118 | chi\t%0,%h1 |
ec24698e | 1119 | cfi\t%0,%1 |
575f7c2b UW |
1120 | c\t%0,%1 |
1121 | cy\t%0,%1 | |
19b63d8e | 1122 | #" |
9381e3f1 | 1123 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
3e4be43f | 1124 | (set_attr "cpu_facility" "*,*,*,*,longdisp,*") |
e3cba5e5 | 1125 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) |
575f7c2b | 1126 | |
07893d4f | 1127 | ; Compare (signed) instructions |
4023fb28 | 1128 | |
07893d4f | 1129 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 1130 | [(set (reg CC_REGNUM) |
963fc8d0 | 1131 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
3e4be43f | 1132 | "d,T,b")) |
963fc8d0 | 1133 | (match_operand:DI 0 "register_operand" "d, d,d")))] |
9602b6a1 | 1134 | "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" |
4023fb28 | 1135 | "@ |
d40c829f | 1136 | cgfr\t%0,%1 |
963fc8d0 AK |
1137 | cgf\t%0,%1 |
1138 | cgfrl\t%0,%1" | |
1139 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 1140 | (set_attr "z10prop" "z10_c,*,*") |
14cfceb7 IL |
1141 | (set_attr "type" "*,*,larl") |
1142 | (set_attr "relative_long" "*,*,yes")]) | |
4023fb28 | 1143 | |
9381e3f1 WG |
1144 | |
1145 | ||
07893d4f | 1146 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 1147 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1148 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
1149 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 1150 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 1151 | "@ |
d40c829f | 1152 | ch\t%0,%1 |
963fc8d0 AK |
1153 | chy\t%0,%1 |
1154 | chrl\t%0,%1" | |
1155 | [(set_attr "op_type" "RX,RXY,RIL") | |
3e4be43f | 1156 | (set_attr "cpu_facility" "*,longdisp,z10") |
65b1d8ea | 1157 | (set_attr "type" "*,*,larl") |
14cfceb7 IL |
1158 | (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked") |
1159 | (set_attr "relative_long" "*,*,yes")]) | |
963fc8d0 AK |
1160 | |
1161 | (define_insn "*cmphi_ccs_z10" | |
1162 | [(set (reg CC_REGNUM) | |
1163 | (compare (match_operand:HI 0 "s_operand" "Q") | |
1164 | (match_operand:HI 1 "immediate_operand" "K")))] | |
1165 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
1166 | "chhsi\t%0,%1" | |
65b1d8ea AK |
1167 | [(set_attr "op_type" "SIL") |
1168 | (set_attr "z196prop" "z196_cracked")]) | |
963fc8d0 AK |
1169 | |
1170 | (define_insn "*cmpdi_ccs_signhi_rl" | |
1171 | [(set (reg CC_REGNUM) | |
3e4be43f | 1172 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b")) |
963fc8d0 AK |
1173 | (match_operand:GPR 0 "register_operand" "d,d")))] |
1174 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
1175 | "@ | |
1176 | cgh\t%0,%1 | |
1177 | cghrl\t%0,%1" | |
1178 | [(set_attr "op_type" "RXY,RIL") | |
14cfceb7 IL |
1179 | (set_attr "type" "*,larl") |
1180 | (set_attr "relative_long" "*,yes")]) | |
4023fb28 | 1181 | |
963fc8d0 | 1182 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 1183 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1184 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1185 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
1186 | "d,d,Q, d,d,d,d") | |
1187 | (match_operand:GPR 1 "general_operand" | |
1188 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 1189 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 1190 | "@ |
3298c037 AK |
1191 | c<g>r\t%0,%1 |
1192 | c<g>hi\t%0,%h1 | |
963fc8d0 | 1193 | c<g>hsi\t%0,%h1 |
3298c037 AK |
1194 | c<g>fi\t%0,%1 |
1195 | c<g>\t%0,%1 | |
963fc8d0 AK |
1196 | c<y>\t%0,%1 |
1197 | c<g>rl\t%0,%1" | |
1198 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
3e4be43f | 1199 | (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10") |
9381e3f1 | 1200 | (set_attr "type" "*,*,*,*,*,*,larl") |
14cfceb7 IL |
1201 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super") |
1202 | (set_attr "relative_long" "*,*,*,*,*,*,yes")]) | |
c7453384 | 1203 | |
07893d4f UW |
1204 | |
1205 | ; Compare (unsigned) instructions | |
9db1d521 | 1206 | |
963fc8d0 AK |
1207 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
1208 | [(set (reg CC_REGNUM) | |
1209 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
1210 | "larl_operand" "X"))) | |
1211 | (match_operand:SI 0 "register_operand" "d")))] | |
1212 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1213 | "clhrl\t%0,%1" | |
1214 | [(set_attr "op_type" "RIL") | |
729e750f | 1215 | (set_attr "type" "larl") |
14cfceb7 IL |
1216 | (set_attr "z10prop" "z10_super") |
1217 | (set_attr "relative_long" "yes")]) | |
963fc8d0 AK |
1218 | |
1219 | ; clhrl, clghrl | |
1220 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
1221 | [(set (reg CC_REGNUM) | |
1222 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
1223 | "larl_operand" "X"))) | |
1224 | (match_operand:GPR 0 "register_operand" "d")))] | |
1225 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1226 | "cl<g>hrl\t%0,%1" | |
1227 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1228 | (set_attr "type" "larl") |
14cfceb7 IL |
1229 | (set_attr "z10prop" "z10_super") |
1230 | (set_attr "relative_long" "yes")]) | |
963fc8d0 | 1231 | |
07893d4f | 1232 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 1233 | [(set (reg CC_REGNUM) |
963fc8d0 | 1234 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
3e4be43f UW |
1235 | "d,T,b")) |
1236 | (match_operand:DI 0 "register_operand" "d,d,d")))] | |
9602b6a1 | 1237 | "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" |
07893d4f | 1238 | "@ |
d40c829f | 1239 | clgfr\t%0,%1 |
963fc8d0 AK |
1240 | clgf\t%0,%1 |
1241 | clgfrl\t%0,%1" | |
1242 | [(set_attr "op_type" "RRE,RXY,RIL") | |
1243 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 | 1244 | (set_attr "type" "*,*,larl") |
14cfceb7 IL |
1245 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super") |
1246 | (set_attr "relative_long" "*,*,yes")]) | |
9db1d521 | 1247 | |
07893d4f | 1248 | (define_insn "*cmpdi_ccu" |
ae156f85 | 1249 | [(set (reg CC_REGNUM) |
963fc8d0 | 1250 | (compare (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1251 | "d, d,d,Q,d, Q,BQ") |
963fc8d0 | 1252 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1253 | "d,Op,b,D,T,BQ,Q")))] |
9602b6a1 | 1254 | "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" |
07893d4f | 1255 | "@ |
d40c829f | 1256 | clgr\t%0,%1 |
ec24698e | 1257 | clgfi\t%0,%1 |
963fc8d0 AK |
1258 | clgrl\t%0,%1 |
1259 | clghsi\t%0,%x1 | |
575f7c2b | 1260 | clg\t%0,%1 |
e221ef54 | 1261 | # |
19b63d8e | 1262 | #" |
963fc8d0 AK |
1263 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
1264 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 | 1265 | (set_attr "type" "*,*,larl,*,*,*,*") |
14cfceb7 IL |
1266 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*") |
1267 | (set_attr "relative_long" "*,*,yes,*,*,*,*")]) | |
9db1d521 | 1268 | |
07893d4f | 1269 | (define_insn "*cmpsi_ccu" |
ae156f85 | 1270 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1271 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
1272 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 1273 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 1274 | "@ |
d40c829f | 1275 | clr\t%0,%1 |
ec24698e | 1276 | clfi\t%0,%o1 |
963fc8d0 AK |
1277 | clrl\t%0,%1 |
1278 | clfhsi\t%0,%x1 | |
d40c829f | 1279 | cl\t%0,%1 |
575f7c2b | 1280 | cly\t%0,%1 |
e221ef54 | 1281 | # |
19b63d8e | 1282 | #" |
963fc8d0 | 1283 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
3e4be43f | 1284 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*") |
9381e3f1 | 1285 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
14cfceb7 IL |
1286 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*") |
1287 | (set_attr "relative_long" "*,*,yes,*,*,*,*,*")]) | |
9db1d521 | 1288 | |
07893d4f | 1289 | (define_insn "*cmphi_ccu" |
ae156f85 | 1290 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1291 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
1292 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 1293 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1294 | && !register_operand (operands[1], HImode)" |
d3632d41 | 1295 | "@ |
fc0ea003 UW |
1296 | clm\t%0,3,%S1 |
1297 | clmy\t%0,3,%S1 | |
963fc8d0 | 1298 | clhhsi\t%0,%1 |
e221ef54 | 1299 | # |
19b63d8e | 1300 | #" |
963fc8d0 | 1301 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
3e4be43f | 1302 | (set_attr "cpu_facility" "*,longdisp,z10,*,*") |
9381e3f1 | 1303 | (set_attr "z10prop" "*,*,z10_super,*,*")]) |
9db1d521 HP |
1304 | |
1305 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 1306 | [(set (reg CC_REGNUM) |
e221ef54 UW |
1307 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
1308 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 1309 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1310 | && !register_operand (operands[1], QImode)" |
d3632d41 | 1311 | "@ |
fc0ea003 UW |
1312 | clm\t%0,1,%S1 |
1313 | clmy\t%0,1,%S1 | |
1314 | cli\t%S0,%b1 | |
1315 | cliy\t%S0,%b1 | |
e221ef54 | 1316 | # |
19b63d8e | 1317 | #" |
9381e3f1 | 1318 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
3e4be43f | 1319 | (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*") |
9381e3f1 | 1320 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) |
9db1d521 HP |
1321 | |
1322 | ||
19b63d8e UW |
1323 | ; Block compare (CLC) instruction patterns. |
1324 | ||
1325 | (define_insn "*clc" | |
ae156f85 | 1326 | [(set (reg CC_REGNUM) |
d4f52f0e | 1327 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
1328 | (match_operand:BLK 1 "memory_operand" "Q"))) |
1329 | (use (match_operand 2 "const_int_operand" "n"))] | |
1330 | "s390_match_ccmode (insn, CCUmode) | |
1331 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1332 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 1333 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1334 | |
1335 | (define_split | |
ae156f85 | 1336 | [(set (reg CC_REGNUM) |
19b63d8e UW |
1337 | (compare (match_operand 0 "memory_operand" "") |
1338 | (match_operand 1 "memory_operand" "")))] | |
1339 | "reload_completed | |
1340 | && s390_match_ccmode (insn, CCUmode) | |
1341 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1342 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1343 | [(parallel | |
1344 | [(set (match_dup 0) (match_dup 1)) | |
1345 | (use (match_dup 2))])] | |
1346 | { | |
1347 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1348 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1349 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1350 | ||
1351 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
1352 | operands[0], operands[1]); | |
1353 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
1354 | }) | |
1355 | ||
1356 | ||
609e7e80 | 1357 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 1358 | |
e325aba2 | 1359 | |
64c8e85a | 1360 | ; FIXME: load and test instructions turn SNaN into QNaN what is not |
e325aba2 AK |
1361 | ; acceptable if the target will be used afterwards. On the other hand |
1362 | ; they are quite convenient for implementing comparisons with 0.0. So | |
64c8e85a AK |
1363 | ; try to enable them via splitter/peephole if the value isn't needed anymore. |
1364 | ; See testcases: load-and-test-fp-1.c and load-and-test-fp-2.c | |
e325aba2 | 1365 | |
609e7e80 | 1366 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 1367 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 1368 | [(set (reg CC_REGNUM) |
e325aba2 AK |
1369 | (compare (match_operand:FP 0 "register_operand" "f") |
1370 | (match_operand:FP 1 "const0_operand" ""))) | |
1371 | (clobber (match_operand:FP 2 "register_operand" "=0"))] | |
142cd70f | 1372 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 1373 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 1374 | [(set_attr "op_type" "RRE") |
9381e3f1 | 1375 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1376 | |
2de2b3f9 AK |
1377 | ; VX: TFmode in FPR pairs: use cxbr instead of wfcxb |
1378 | ; cxtr, cdtr, cxbr, cdbr, cebr, cdb, ceb, wfcsb, wfcdb | |
f5905b37 | 1379 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1380 | [(set (reg CC_REGNUM) |
2de2b3f9 AK |
1381 | (compare (match_operand:FP 0 "register_operand" "f,f,v,v") |
1382 | (match_operand:FP 1 "general_operand" "f,R,v,v")))] | |
142cd70f | 1383 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 1384 | "@ |
609e7e80 | 1385 | c<xde><bt>r\t%0,%1 |
77c585ca | 1386 | c<xde>b\t%0,%1 |
2de2b3f9 AK |
1387 | wfcdb\t%0,%1 |
1388 | wfcsb\t%0,%1" | |
1389 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
1390 | (set_attr "cpu_facility" "*,*,vx,vxe") | |
1391 | (set_attr "enabled" "*,<DSF>,<DF>,<SF>")]) | |
963fc8d0 AK |
1392 | |
1393 | ; Compare and Branch instructions | |
1394 | ||
1395 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
1396 | ; The following instructions do a complementary access of their second |
1397 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
1398 | (define_insn "*cmp_and_br_signed_<mode>" |
1399 | [(set (pc) | |
1400 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1401 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1402 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1403 | (label_ref (match_operand 3 "" "")) | |
1404 | (pc))) | |
1405 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1406 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1407 | { |
1408 | if (get_attr_length (insn) == 6) | |
1409 | return which_alternative ? | |
1410 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1411 | else | |
1412 | return which_alternative ? | |
1413 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1414 | } | |
1415 | [(set_attr "op_type" "RIE") | |
1416 | (set_attr "type" "branch") | |
e3cba5e5 | 1417 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1418 | (set (attr "length") |
1419 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1420 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1421 | ; 10 byte for cgr/jg | |
1422 | ||
1423 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1424 | ; The following instructions do a complementary access of their second |
1425 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1426 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1427 | [(set (pc) | |
1428 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1429 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1430 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1431 | (label_ref (match_operand 3 "" "")) | |
1432 | (pc))) | |
1433 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1434 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1435 | { |
1436 | if (get_attr_length (insn) == 6) | |
1437 | return which_alternative ? | |
1438 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1439 | else | |
1440 | return which_alternative ? | |
1441 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1442 | } | |
1443 | [(set_attr "op_type" "RIE") | |
1444 | (set_attr "type" "branch") | |
e3cba5e5 | 1445 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1446 | (set (attr "length") |
1447 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1448 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1449 | ; 10 byte for clgr/jg | |
1450 | ||
b0f86a7e AK |
1451 | ; And now the same two patterns as above but with a negated CC mask. |
1452 | ||
1453 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1454 | ; The following instructions do a complementary access of their second | |
1455 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1456 | (define_insn "*icmp_and_br_signed_<mode>" | |
1457 | [(set (pc) | |
1458 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1459 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1460 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1461 | (pc) | |
1462 | (label_ref (match_operand 3 "" "")))) | |
1463 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1464 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1465 | { |
1466 | if (get_attr_length (insn) == 6) | |
1467 | return which_alternative ? | |
1468 | "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; | |
1469 | else | |
1470 | return which_alternative ? | |
1471 | "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; | |
1472 | } | |
1473 | [(set_attr "op_type" "RIE") | |
1474 | (set_attr "type" "branch") | |
1475 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1476 | (set (attr "length") | |
1477 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1478 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1479 | ; 10 byte for cgr/jg | |
1480 | ||
1481 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1482 | ; The following instructions do a complementary access of their second | |
1483 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
1484 | (define_insn "*icmp_and_br_unsigned_<mode>" | |
1485 | [(set (pc) | |
1486 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1487 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1488 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1489 | (pc) | |
1490 | (label_ref (match_operand 3 "" "")))) | |
1491 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1492 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1493 | { |
1494 | if (get_attr_length (insn) == 6) | |
1495 | return which_alternative ? | |
1496 | "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; | |
1497 | else | |
1498 | return which_alternative ? | |
1499 | "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; | |
1500 | } | |
1501 | [(set_attr "op_type" "RIE") | |
1502 | (set_attr "type" "branch") | |
1503 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1504 | (set (attr "length") | |
1505 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1506 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1507 | ; 10 byte for clgr/jg | |
1508 | ||
9db1d521 HP |
1509 | ;; |
1510 | ;;- Move instructions. | |
1511 | ;; | |
1512 | ||
1513 | ; | |
1514 | ; movti instruction pattern(s). | |
1515 | ; | |
1516 | ||
3cb9ee2f AK |
1517 | |
1518 | ; Separate out the register pair alternative since constraints (P) are | |
1519 | ; not able to deal with const_wide_int's. But predicates do. | |
1520 | (define_insn "*movti_bigconst" | |
1521 | [(set (match_operand:TI 0 "register_operand" "=d") | |
1522 | (match_operand:TI 1 "reload_const_wide_int_operand" ""))] | |
1523 | "TARGET_ZARCH" | |
1524 | "#") | |
1525 | ||
085261c8 AK |
1526 | ; FIXME: More constants are possible by enabling jxx, jyy constraints |
1527 | ; for TImode (use double-int for the calculations) | |
9db1d521 | 1528 | (define_insn "movti" |
9f3c21d6 AK |
1529 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R,d, d, d, d, d,o") |
1530 | (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,K,NxHD0,Os,NxSD0,dT,d"))] | |
9602b6a1 | 1531 | "TARGET_ZARCH" |
4023fb28 | 1532 | "@ |
fc0ea003 UW |
1533 | lmg\t%0,%N0,%S1 |
1534 | stmg\t%1,%N1,%S0 | |
085261c8 AK |
1535 | vlr\t%v0,%v1 |
1536 | vzero\t%v0 | |
1537 | vone\t%v0 | |
1538 | vlvgp\t%v0,%1,%N1 | |
1539 | # | |
b8923037 AK |
1540 | vl\t%v0,%1%A1 |
1541 | vst\t%v1,%0%A0 | |
4023fb28 | 1542 | # |
9f3c21d6 AK |
1543 | # |
1544 | # | |
1545 | # | |
1546 | # | |
19b63d8e | 1547 | #" |
9f3c21d6 AK |
1548 | [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*,*,*,*,*") |
1549 | (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*,*,*,*,*") | |
1550 | (set_attr "cpu_facility" "*,*,vx,vx,vx,vx,vx,vx,vx,*,*,*,extimm,*,*")]) | |
4023fb28 UW |
1551 | |
1552 | (define_split | |
1553 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1554 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1555 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
1556 | && !s_operand (operands[0], TImode) |
1557 | && !s_operand (operands[1], TImode) | |
dc65c307 | 1558 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1559 | [(set (match_dup 2) (match_dup 4)) |
1560 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1561 | { |
dc65c307 UW |
1562 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1563 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1564 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1565 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1566 | }) | |
1567 | ||
1568 | (define_split | |
1569 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1570 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1571 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
1572 | && !s_operand (operands[0], TImode) |
1573 | && !s_operand (operands[1], TImode) | |
dc65c307 UW |
1574 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" |
1575 | [(set (match_dup 2) (match_dup 4)) | |
1576 | (set (match_dup 3) (match_dup 5))] | |
1577 | { | |
1578 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1579 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1580 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1581 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1582 | }) | |
4023fb28 | 1583 | |
085261c8 AK |
1584 | ; Use part of the TImode target reg to perform the address |
1585 | ; calculation. If the TImode value is supposed to be copied into a VR | |
1586 | ; this splitter is not necessary. | |
4023fb28 UW |
1587 | (define_split |
1588 | [(set (match_operand:TI 0 "register_operand" "") | |
1589 | (match_operand:TI 1 "memory_operand" ""))] | |
9602b6a1 | 1590 | "TARGET_ZARCH && reload_completed |
085261c8 | 1591 | && !VECTOR_REG_P (operands[0]) |
4023fb28 | 1592 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1593 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1594 | { |
1595 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
9602b6a1 | 1596 | addr = gen_lowpart (Pmode, addr); |
a41c6c53 UW |
1597 | s390_load_address (addr, XEXP (operands[1], 0)); |
1598 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1599 | }) |
1600 | ||
833cd70a | 1601 | |
085261c8 AK |
1602 | ; Split a VR -> GPR TImode move into 2 vector load GR from VR element. |
1603 | ; For the higher order bits we do simply a DImode move while the | |
1604 | ; second part is done via vec extract. Both will end up as vlgvg. | |
1605 | (define_split | |
1606 | [(set (match_operand:TI 0 "register_operand" "") | |
1607 | (match_operand:TI 1 "register_operand" ""))] | |
1608 | "TARGET_VX && reload_completed | |
1609 | && GENERAL_REG_P (operands[0]) | |
1610 | && VECTOR_REG_P (operands[1])" | |
1611 | [(set (match_dup 2) (match_dup 4)) | |
1612 | (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)] | |
1613 | UNSPEC_VEC_EXTRACT))] | |
1614 | { | |
1615 | operands[2] = operand_subword (operands[0], 0, 0, TImode); | |
1616 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1617 | operands[4] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
1618 | operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1])); | |
1619 | }) | |
1620 | ||
833cd70a AK |
1621 | ; |
1622 | ; Patterns used for secondary reloads | |
1623 | ; | |
1624 | ||
963fc8d0 AK |
1625 | ; z10 provides move instructions accepting larl memory operands. |
1626 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1627 | ; These patterns are also used for unaligned SI and DI accesses. | |
1628 | ||
085261c8 AK |
1629 | (define_expand "reload<ALL:mode><P:mode>_tomem_z10" |
1630 | [(parallel [(match_operand:ALL 0 "memory_operand" "") | |
1631 | (match_operand:ALL 1 "register_operand" "=d") | |
1632 | (match_operand:P 2 "register_operand" "=&a")])] | |
963fc8d0 AK |
1633 | "TARGET_Z10" |
1634 | { | |
1635 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1636 | DONE; | |
1637 | }) | |
1638 | ||
085261c8 AK |
1639 | (define_expand "reload<ALL:mode><P:mode>_toreg_z10" |
1640 | [(parallel [(match_operand:ALL 0 "register_operand" "=d") | |
1641 | (match_operand:ALL 1 "memory_operand" "") | |
1642 | (match_operand:P 2 "register_operand" "=a")])] | |
963fc8d0 AK |
1643 | "TARGET_Z10" |
1644 | { | |
1645 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1646 | DONE; | |
1647 | }) | |
1648 | ||
1649 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1650 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1651 | (match_operand:P 1 "larl_operand" "") | |
1652 | (match_operand:P 2 "register_operand" "=a")])] | |
1653 | "TARGET_Z10" | |
1654 | { | |
1655 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1656 | DONE; | |
1657 | }) | |
1658 | ||
833cd70a AK |
1659 | ; Handles loading a PLUS (load address) expression |
1660 | ||
1661 | (define_expand "reload<mode>_plus" | |
1662 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1663 | (match_operand:P 1 "s390_plus_operand" "") | |
1664 | (match_operand:P 2 "register_operand" "=&a")])] | |
1665 | "" | |
1666 | { | |
1667 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1668 | DONE; | |
1669 | }) | |
1670 | ||
085261c8 AK |
1671 | ; Not all the indirect memory access instructions support the full |
1672 | ; format (long disp + index + base). So whenever a move from/to such | |
1673 | ; an address is required and the instruction cannot deal with it we do | |
1674 | ; a load address into a scratch register first and use this as the new | |
1675 | ; base register. | |
1676 | ; This in particular is used for: | |
1677 | ; - non-offsetable memory accesses for multiword moves | |
1678 | ; - full vector reg moves with long displacements | |
833cd70a | 1679 | |
085261c8 | 1680 | (define_expand "reload<mode>_la_in" |
833cd70a AK |
1681 | [(parallel [(match_operand 0 "register_operand" "") |
1682 | (match_operand 1 "" "") | |
1683 | (match_operand:P 2 "register_operand" "=&a")])] | |
1684 | "" | |
1685 | { | |
1686 | gcc_assert (MEM_P (operands[1])); | |
1687 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1688 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1689 | emit_move_insn (operands[0], operands[1]); | |
1690 | DONE; | |
1691 | }) | |
1692 | ||
085261c8 | 1693 | (define_expand "reload<mode>_la_out" |
833cd70a AK |
1694 | [(parallel [(match_operand 0 "" "") |
1695 | (match_operand 1 "register_operand" "") | |
1696 | (match_operand:P 2 "register_operand" "=&a")])] | |
1697 | "" | |
dc65c307 | 1698 | { |
9c3c3dcc | 1699 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1700 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1701 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1702 | emit_move_insn (operands[0], operands[1]); | |
1703 | DONE; | |
1704 | }) | |
9db1d521 | 1705 | |
1f9e1fc6 AK |
1706 | (define_expand "reload<mode>_PIC_addr" |
1707 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1708 | (match_operand 1 "larl_operand" "") | |
1709 | (match_operand:P 2 "register_operand" "=a")])] | |
1710 | "" | |
1711 | { | |
0a2aaacc KG |
1712 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1713 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1714 | }) |
1715 | ||
9db1d521 HP |
1716 | ; |
1717 | ; movdi instruction pattern(s). | |
1718 | ; | |
1719 | ||
9db1d521 HP |
1720 | (define_expand "movdi" |
1721 | [(set (match_operand:DI 0 "general_operand" "") | |
1722 | (match_operand:DI 1 "general_operand" ""))] | |
1723 | "" | |
9db1d521 | 1724 | { |
fd3cd001 | 1725 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1726 | if (TARGET_64BIT |
1727 | && (SYMBOLIC_CONST (operands[1]) | |
1728 | || (GET_CODE (operands[1]) == PLUS | |
1729 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1730 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1731 | emit_symbolic_move (operands); |
10bbf137 | 1732 | }) |
9db1d521 | 1733 | |
3af8e996 | 1734 | (define_insn "*movdi_64" |
85dae55a | 1735 | [(set (match_operand:DI 0 "nonimmediate_operand" |
b6f51755 | 1736 | "=d, d, d, d, d, d, d, d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R,d") |
85dae55a | 1737 | (match_operand:DI 1 "general_operand" |
b6f51755 | 1738 | " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v,ZL"))] |
9602b6a1 | 1739 | "TARGET_ZARCH" |
85dae55a AK |
1740 | "@ |
1741 | lghi\t%0,%h1 | |
1742 | llihh\t%0,%i1 | |
1743 | llihl\t%0,%i1 | |
1744 | llilh\t%0,%i1 | |
1745 | llill\t%0,%i1 | |
1746 | lgfi\t%0,%1 | |
1747 | llihf\t%0,%k1 | |
1748 | llilf\t%0,%k1 | |
1749 | ldgr\t%0,%1 | |
1750 | lgdr\t%0,%1 | |
1751 | lay\t%0,%a1 | |
963fc8d0 | 1752 | lgrl\t%0,%1 |
85dae55a AK |
1753 | lgr\t%0,%1 |
1754 | lg\t%0,%1 | |
1755 | stg\t%1,%0 | |
1756 | ldr\t%0,%1 | |
1757 | ld\t%0,%1 | |
1758 | ldy\t%0,%1 | |
1759 | std\t%1,%0 | |
1760 | stdy\t%1,%0 | |
963fc8d0 AK |
1761 | stgrl\t%1,%0 |
1762 | mvghi\t%0,%1 | |
85dae55a AK |
1763 | # |
1764 | # | |
1765 | stam\t%1,%N1,%S0 | |
085261c8 AK |
1766 | lam\t%0,%N0,%S1 |
1767 | vleig\t%v0,%h1,0 | |
1768 | vlr\t%v0,%v1 | |
1769 | vlvgg\t%v0,%1,0 | |
1770 | vlgvg\t%0,%v1,0 | |
1771 | vleg\t%v0,%1,0 | |
b6f51755 IL |
1772 | vsteg\t%v1,%0,0 |
1773 | larl\t%0,%1" | |
963fc8d0 | 1774 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
b6f51755 IL |
1775 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS, |
1776 | VRX,VRX,RIL") | |
963fc8d0 | 1777 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
085261c8 | 1778 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*, |
b6f51755 | 1779 | *,*,*,*,*,*,*,larl") |
3af8e996 | 1780 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1781 | z10,*,*,*,*,*,longdisp,*,longdisp, |
b6f51755 | 1782 | z10,z10,*,*,*,*,vx,vx,vx,vx,vx,vx,*") |
9381e3f1 WG |
1783 | (set_attr "z10prop" "z10_fwd_A1, |
1784 | z10_fwd_E1, | |
1785 | z10_fwd_E1, | |
1786 | z10_fwd_E1, | |
1787 | z10_fwd_E1, | |
1788 | z10_fwd_A1, | |
1789 | z10_fwd_E1, | |
1790 | z10_fwd_E1, | |
1791 | *, | |
1792 | *, | |
1793 | z10_fwd_A1, | |
1794 | z10_fwd_A3, | |
1795 | z10_fr_E1, | |
1796 | z10_fwd_A3, | |
1797 | z10_rec, | |
1798 | *, | |
1799 | *, | |
1800 | *, | |
1801 | *, | |
1802 | *, | |
1803 | z10_rec, | |
1804 | z10_super, | |
1805 | *, | |
1806 | *, | |
1807 | *, | |
b6f51755 IL |
1808 | *,*,*,*,*,*,*, |
1809 | z10_super_A1") | |
14cfceb7 IL |
1810 | (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*, |
1811 | *,yes,*,*,*,*,*,*,*,*, | |
1812 | yes,*,*,*,*,*,*,*,*,*, | |
1813 | *,*,yes") | |
9381e3f1 | 1814 | ]) |
c5aa1d12 UW |
1815 | |
1816 | (define_split | |
1817 | [(set (match_operand:DI 0 "register_operand" "") | |
1818 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1819 | "TARGET_ZARCH && ACCESS_REG_P (operands[1])" |
c5aa1d12 UW |
1820 | [(set (match_dup 2) (match_dup 3)) |
1821 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1822 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1823 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1824 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1825 | ||
1826 | (define_split | |
1827 | [(set (match_operand:DI 0 "register_operand" "") | |
1828 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1829 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1830 | && dead_or_set_p (insn, operands[1])" |
1831 | [(set (match_dup 3) (match_dup 2)) | |
1832 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1833 | (set (match_dup 4) (match_dup 2))] | |
1834 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1835 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1836 | ||
1837 | (define_split | |
1838 | [(set (match_operand:DI 0 "register_operand" "") | |
1839 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1840 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1841 | && !dead_or_set_p (insn, operands[1])" |
1842 | [(set (match_dup 3) (match_dup 2)) | |
1843 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1844 | (set (match_dup 4) (match_dup 2)) | |
1845 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1846 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1847 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1848 | |
1849 | (define_insn "*movdi_31" | |
963fc8d0 | 1850 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1851 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1852 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1853 | " Q,S,d,d,dPT,d, *f, R, T,*f,*f,b"))] |
9602b6a1 | 1854 | "!TARGET_ZARCH" |
4023fb28 | 1855 | "@ |
fc0ea003 | 1856 | lm\t%0,%N0,%S1 |
c4d50129 | 1857 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1858 | stm\t%1,%N1,%S0 |
c4d50129 | 1859 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1860 | # |
1861 | # | |
d40c829f UW |
1862 | ldr\t%0,%1 |
1863 | ld\t%0,%1 | |
1864 | ldy\t%0,%1 | |
1865 | std\t%1,%0 | |
1866 | stdy\t%1,%0 | |
19b63d8e | 1867 | #" |
f2dc2f86 AK |
1868 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1869 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
3e4be43f | 1870 | (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")]) |
963fc8d0 AK |
1871 | |
1872 | ; For a load from a symbol ref we can use one of the target registers | |
1873 | ; together with larl to load the address. | |
1874 | (define_split | |
1875 | [(set (match_operand:DI 0 "register_operand" "") | |
1876 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1877 | "!TARGET_ZARCH && reload_completed && TARGET_Z10 |
963fc8d0 AK |
1878 | && larl_operand (XEXP (operands[1], 0), SImode)" |
1879 | [(set (match_dup 2) (match_dup 3)) | |
1880 | (set (match_dup 0) (match_dup 1))] | |
1881 | { | |
1882 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1883 | operands[3] = XEXP (operands[1], 0); | |
1884 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1885 | }) | |
4023fb28 UW |
1886 | |
1887 | (define_split | |
1888 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1889 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1890 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
1891 | && !s_operand (operands[0], DImode) |
1892 | && !s_operand (operands[1], DImode) | |
dc65c307 | 1893 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1894 | [(set (match_dup 2) (match_dup 4)) |
1895 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1896 | { |
dc65c307 UW |
1897 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1898 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1899 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1900 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1901 | }) | |
1902 | ||
1903 | (define_split | |
1904 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1905 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1906 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
1907 | && !s_operand (operands[0], DImode) |
1908 | && !s_operand (operands[1], DImode) | |
dc65c307 UW |
1909 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" |
1910 | [(set (match_dup 2) (match_dup 4)) | |
1911 | (set (match_dup 3) (match_dup 5))] | |
1912 | { | |
1913 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1914 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1915 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1916 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1917 | }) | |
9db1d521 | 1918 | |
4023fb28 UW |
1919 | (define_split |
1920 | [(set (match_operand:DI 0 "register_operand" "") | |
1921 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1922 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 1923 | && !FP_REG_P (operands[0]) |
4023fb28 | 1924 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1925 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1926 | { |
1927 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1928 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1929 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1930 | }) |
1931 | ||
84817c5d UW |
1932 | (define_peephole2 |
1933 | [(set (match_operand:DI 0 "register_operand" "") | |
1934 | (mem:DI (match_operand 1 "address_operand" "")))] | |
9602b6a1 | 1935 | "TARGET_ZARCH |
84817c5d UW |
1936 | && !FP_REG_P (operands[0]) |
1937 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1938 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1939 | && get_pool_mode (operands[1]) == DImode | |
1940 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1941 | [(set (match_dup 0) (match_dup 2))] | |
1942 | "operands[2] = get_pool_constant (operands[1]);") | |
1943 | ||
7bdff56f UW |
1944 | (define_insn "*la_64" |
1945 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 1946 | (match_operand:QI 1 "address_operand" "ZR,ZT"))] |
7bdff56f UW |
1947 | "TARGET_64BIT" |
1948 | "@ | |
1949 | la\t%0,%a1 | |
1950 | lay\t%0,%a1" | |
1951 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 1952 | (set_attr "type" "la") |
3e4be43f | 1953 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1954 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
1955 | |
1956 | (define_peephole2 | |
1957 | [(parallel | |
1958 | [(set (match_operand:DI 0 "register_operand" "") | |
1959 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1960 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1961 | "TARGET_64BIT |
e1d5ee28 | 1962 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1963 | [(set (match_dup 0) (match_dup 1))] |
1964 | "") | |
1965 | ||
1966 | (define_peephole2 | |
1967 | [(set (match_operand:DI 0 "register_operand" "") | |
1968 | (match_operand:DI 1 "register_operand" "")) | |
1969 | (parallel | |
1970 | [(set (match_dup 0) | |
1971 | (plus:DI (match_dup 0) | |
1972 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1973 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1974 | "TARGET_64BIT |
1975 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1976 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1977 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1978 | "") | |
1979 | ||
9db1d521 HP |
1980 | ; |
1981 | ; movsi instruction pattern(s). | |
1982 | ; | |
1983 | ||
9db1d521 HP |
1984 | (define_expand "movsi" |
1985 | [(set (match_operand:SI 0 "general_operand" "") | |
1986 | (match_operand:SI 1 "general_operand" ""))] | |
1987 | "" | |
9db1d521 | 1988 | { |
fd3cd001 | 1989 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1990 | if (!TARGET_64BIT |
1991 | && (SYMBOLIC_CONST (operands[1]) | |
1992 | || (GET_CODE (operands[1]) == PLUS | |
1993 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1994 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 1995 | emit_symbolic_move (operands); |
10bbf137 | 1996 | }) |
9db1d521 | 1997 | |
9e8327e3 UW |
1998 | (define_insn "*movsi_larl" |
1999 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2000 | (match_operand:SI 1 "larl_operand" "X"))] | |
8cc6307c | 2001 | "!TARGET_64BIT |
9e8327e3 UW |
2002 | && !FP_REG_P (operands[0])" |
2003 | "larl\t%0,%1" | |
2004 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 2005 | (set_attr "type" "larl") |
14cfceb7 IL |
2006 | (set_attr "z10prop" "z10_fwd_A1") |
2007 | (set_attr "relative_long" "yes")]) | |
9e8327e3 | 2008 | |
f19a9af7 | 2009 | (define_insn "*movsi_zarch" |
2f7e5a0d | 2010 | [(set (match_operand:SI 0 "nonimmediate_operand" |
3e4be43f | 2011 | "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R") |
2f7e5a0d | 2012 | (match_operand:SI 1 "general_operand" |
3e4be43f | 2013 | " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))] |
f19a9af7 | 2014 | "TARGET_ZARCH" |
9db1d521 | 2015 | "@ |
f19a9af7 AK |
2016 | lhi\t%0,%h1 |
2017 | llilh\t%0,%i1 | |
2018 | llill\t%0,%i1 | |
ec24698e | 2019 | iilf\t%0,%o1 |
f19a9af7 | 2020 | lay\t%0,%a1 |
963fc8d0 | 2021 | lrl\t%0,%1 |
d40c829f UW |
2022 | lr\t%0,%1 |
2023 | l\t%0,%1 | |
2024 | ly\t%0,%1 | |
2025 | st\t%1,%0 | |
2026 | sty\t%1,%0 | |
ae1c6198 | 2027 | ldr\t%0,%1 |
d40c829f | 2028 | ler\t%0,%1 |
085261c8 | 2029 | lde\t%0,%1 |
d40c829f UW |
2030 | le\t%0,%1 |
2031 | ley\t%0,%1 | |
2032 | ste\t%1,%0 | |
2033 | stey\t%1,%0 | |
c5aa1d12 UW |
2034 | ear\t%0,%1 |
2035 | sar\t%0,%1 | |
2036 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
2037 | strl\t%1,%0 |
2038 | mvhi\t%0,%1 | |
085261c8 AK |
2039 | lam\t%0,%0,%S1 |
2040 | vleif\t%v0,%h1,0 | |
2041 | vlr\t%v0,%v1 | |
2042 | vlvgf\t%v0,%1,0 | |
2043 | vlgvf\t%0,%v1,0 | |
2044 | vlef\t%v0,%1,0 | |
2045 | vstef\t%v1,%0,0" | |
963fc8d0 | 2046 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
ae1c6198 | 2047 | RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
9381e3f1 WG |
2048 | (set_attr "type" "*, |
2049 | *, | |
2050 | *, | |
2051 | *, | |
2052 | la, | |
2053 | larl, | |
2054 | lr, | |
2055 | load, | |
2056 | load, | |
2057 | store, | |
2058 | store, | |
2059 | floadsf, | |
2060 | floadsf, | |
2061 | floadsf, | |
085261c8 AK |
2062 | floadsf, |
2063 | floadsf, | |
9381e3f1 WG |
2064 | fstoresf, |
2065 | fstoresf, | |
2066 | *, | |
2067 | *, | |
2068 | *, | |
2069 | larl, | |
2070 | *, | |
085261c8 | 2071 | *,*,*,*,*,*,*") |
963fc8d0 | 2072 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
285363a1 | 2073 | vx,*,vx,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2074 | (set_attr "z10prop" "z10_fwd_A1, |
2075 | z10_fwd_E1, | |
2076 | z10_fwd_E1, | |
2077 | z10_fwd_A1, | |
2078 | z10_fwd_A1, | |
2079 | z10_fwd_A3, | |
2080 | z10_fr_E1, | |
2081 | z10_fwd_A3, | |
2082 | z10_fwd_A3, | |
729e750f | 2083 | z10_rec, |
9381e3f1 WG |
2084 | z10_rec, |
2085 | *, | |
2086 | *, | |
2087 | *, | |
2088 | *, | |
2089 | *, | |
085261c8 AK |
2090 | *, |
2091 | *, | |
9381e3f1 WG |
2092 | z10_super_E1, |
2093 | z10_super, | |
2094 | *, | |
2095 | z10_rec, | |
2096 | z10_super, | |
14cfceb7 IL |
2097 | *,*,*,*,*,*,*") |
2098 | (set_attr "relative_long" "*,*,*,*,*,yes,*,*,*,*, | |
2099 | *,*,*,*,*,*,*,*,*,*, | |
2100 | *,yes,*,*,*,*,*,*,*,*")]) | |
f19a9af7 AK |
2101 | |
2102 | (define_insn "*movsi_esa" | |
085261c8 AK |
2103 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t") |
2104 | (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
2105 | "!TARGET_ZARCH" |
2106 | "@ | |
2107 | lhi\t%0,%h1 | |
2108 | lr\t%0,%1 | |
2109 | l\t%0,%1 | |
2110 | st\t%1,%0 | |
ae1c6198 | 2111 | ldr\t%0,%1 |
f19a9af7 | 2112 | ler\t%0,%1 |
085261c8 | 2113 | lde\t%0,%1 |
f19a9af7 AK |
2114 | le\t%0,%1 |
2115 | ste\t%1,%0 | |
c5aa1d12 UW |
2116 | ear\t%0,%1 |
2117 | sar\t%0,%1 | |
2118 | stam\t%1,%1,%S0 | |
f2dc2f86 | 2119 | lam\t%0,%0,%S1" |
ae1c6198 | 2120 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS") |
085261c8 AK |
2121 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*") |
2122 | (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1, | |
2123 | z10_super,*,*") | |
285363a1 | 2124 | (set_attr "cpu_facility" "*,*,*,*,vx,*,vx,*,*,*,*,*,*") |
9381e3f1 | 2125 | ]) |
9db1d521 | 2126 | |
84817c5d UW |
2127 | (define_peephole2 |
2128 | [(set (match_operand:SI 0 "register_operand" "") | |
2129 | (mem:SI (match_operand 1 "address_operand" "")))] | |
2130 | "!FP_REG_P (operands[0]) | |
2131 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2132 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2133 | && get_pool_mode (operands[1]) == SImode | |
2134 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
2135 | [(set (match_dup 0) (match_dup 2))] | |
2136 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 2137 | |
7bdff56f UW |
2138 | (define_insn "*la_31" |
2139 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2140 | (match_operand:QI 1 "address_operand" "ZR,ZT"))] |
7bdff56f UW |
2141 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
2142 | "@ | |
2143 | la\t%0,%a1 | |
2144 | lay\t%0,%a1" | |
2145 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2146 | (set_attr "type" "la") |
3e4be43f | 2147 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2148 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2149 | |
2150 | (define_peephole2 | |
2151 | [(parallel | |
2152 | [(set (match_operand:SI 0 "register_operand" "") | |
2153 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 2154 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 2155 | "!TARGET_64BIT |
e1d5ee28 | 2156 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
2157 | [(set (match_dup 0) (match_dup 1))] |
2158 | "") | |
2159 | ||
2160 | (define_peephole2 | |
2161 | [(set (match_operand:SI 0 "register_operand" "") | |
2162 | (match_operand:SI 1 "register_operand" "")) | |
2163 | (parallel | |
2164 | [(set (match_dup 0) | |
2165 | (plus:SI (match_dup 0) | |
2166 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 2167 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
2168 | "!TARGET_64BIT |
2169 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 2170 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
2171 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
2172 | "") | |
2173 | ||
2174 | (define_insn "*la_31_and" | |
2175 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2176 | (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT") |
7bdff56f UW |
2177 | (const_int 2147483647)))] |
2178 | "!TARGET_64BIT" | |
2179 | "@ | |
2180 | la\t%0,%a1 | |
2181 | lay\t%0,%a1" | |
2182 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2183 | (set_attr "type" "la") |
3e4be43f | 2184 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2185 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2186 | |
2187 | (define_insn_and_split "*la_31_and_cc" | |
2188 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2189 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
2190 | (const_int 2147483647))) | |
ae156f85 | 2191 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
2192 | "!TARGET_64BIT" |
2193 | "#" | |
2194 | "&& reload_completed" | |
2195 | [(set (match_dup 0) | |
2196 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
2197 | "" | |
2198 | [(set_attr "op_type" "RX") | |
2199 | (set_attr "type" "la")]) | |
2200 | ||
2201 | (define_insn "force_la_31" | |
2202 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2203 | (match_operand:QI 1 "address_operand" "ZR,ZT")) |
7bdff56f UW |
2204 | (use (const_int 0))] |
2205 | "!TARGET_64BIT" | |
2206 | "@ | |
2207 | la\t%0,%a1 | |
2208 | lay\t%0,%a1" | |
2209 | [(set_attr "op_type" "RX") | |
9381e3f1 | 2210 | (set_attr "type" "la") |
3e4be43f | 2211 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2212 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f | 2213 | |
9db1d521 HP |
2214 | ; |
2215 | ; movhi instruction pattern(s). | |
2216 | ; | |
2217 | ||
02ed3c5e UW |
2218 | (define_expand "movhi" |
2219 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
2220 | (match_operand:HI 1 "general_operand" ""))] | |
2221 | "" | |
2222 | { | |
2f7e5a0d | 2223 | /* Make it explicit that loading a register from memory |
02ed3c5e | 2224 | always sign-extends (at least) to SImode. */ |
b3a13419 | 2225 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 2226 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2227 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
2228 | { |
2229 | rtx tmp = gen_reg_rtx (SImode); | |
2230 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
f7df4a84 | 2231 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2232 | operands[1] = gen_lowpart (HImode, tmp); |
2233 | } | |
2234 | }) | |
2235 | ||
2236 | (define_insn "*movhi" | |
3e4be43f UW |
2237 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R") |
2238 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))] | |
9db1d521 HP |
2239 | "" |
2240 | "@ | |
d40c829f UW |
2241 | lr\t%0,%1 |
2242 | lhi\t%0,%h1 | |
2243 | lh\t%0,%1 | |
2244 | lhy\t%0,%1 | |
963fc8d0 | 2245 | lhrl\t%0,%1 |
d40c829f UW |
2246 | sth\t%1,%0 |
2247 | sthy\t%1,%0 | |
963fc8d0 | 2248 | sthrl\t%1,%0 |
085261c8 AK |
2249 | mvhhi\t%0,%1 |
2250 | vleih\t%v0,%h1,0 | |
2251 | vlr\t%v0,%v1 | |
2252 | vlvgh\t%v0,%1,0 | |
2253 | vlgvh\t%0,%v1,0 | |
2254 | vleh\t%v0,%1,0 | |
2255 | vsteh\t%v1,%0,0" | |
2256 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX") | |
2257 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*") | |
285363a1 | 2258 | (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2259 | (set_attr "z10prop" "z10_fr_E1, |
2260 | z10_fwd_A1, | |
2261 | z10_super_E1, | |
2262 | z10_super_E1, | |
2263 | z10_super_E1, | |
729e750f | 2264 | z10_rec, |
9381e3f1 WG |
2265 | z10_rec, |
2266 | z10_rec, | |
14cfceb7 IL |
2267 | z10_super,*,*,*,*,*,*") |
2268 | (set_attr "relative_long" "*,*,*,*,yes,*,*,yes,*,*,*,*,*,*,*")]) | |
9db1d521 | 2269 | |
84817c5d UW |
2270 | (define_peephole2 |
2271 | [(set (match_operand:HI 0 "register_operand" "") | |
2272 | (mem:HI (match_operand 1 "address_operand" "")))] | |
2273 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2274 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2275 | && get_pool_mode (operands[1]) == HImode | |
2276 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2277 | [(set (match_dup 0) (match_dup 2))] | |
2278 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2279 | |
9db1d521 HP |
2280 | ; |
2281 | ; movqi instruction pattern(s). | |
2282 | ; | |
2283 | ||
02ed3c5e UW |
2284 | (define_expand "movqi" |
2285 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2286 | (match_operand:QI 1 "general_operand" ""))] | |
2287 | "" | |
2288 | { | |
c19ec8f9 | 2289 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 2290 | is just as fast as a QImode load. */ |
b3a13419 | 2291 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 2292 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2293 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 2294 | { |
9602b6a1 AK |
2295 | rtx tmp = gen_reg_rtx (DImode); |
2296 | rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
f7df4a84 | 2297 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2298 | operands[1] = gen_lowpart (QImode, tmp); |
2299 | } | |
2300 | }) | |
4023fb28 | 2301 | |
02ed3c5e | 2302 | (define_insn "*movqi" |
3e4be43f UW |
2303 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R") |
2304 | (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))] | |
9db1d521 HP |
2305 | "" |
2306 | "@ | |
d40c829f UW |
2307 | lr\t%0,%1 |
2308 | lhi\t%0,%b1 | |
2309 | ic\t%0,%1 | |
2310 | icy\t%0,%1 | |
2311 | stc\t%1,%0 | |
2312 | stcy\t%1,%0 | |
fc0ea003 | 2313 | mvi\t%S0,%b1 |
0a88561f | 2314 | mviy\t%S0,%b1 |
085261c8 AK |
2315 | # |
2316 | vleib\t%v0,%b1,0 | |
2317 | vlr\t%v0,%v1 | |
2318 | vlvgb\t%v0,%1,0 | |
2319 | vlgvb\t%0,%v1,0 | |
2320 | vleb\t%v0,%1,0 | |
2321 | vsteb\t%v1,%0,0" | |
2322 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX") | |
2323 | (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*") | |
285363a1 | 2324 | (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2325 | (set_attr "z10prop" "z10_fr_E1, |
2326 | z10_fwd_A1, | |
2327 | z10_super_E1, | |
2328 | z10_super_E1, | |
729e750f | 2329 | z10_rec, |
9381e3f1 WG |
2330 | z10_rec, |
2331 | z10_super, | |
0a88561f | 2332 | z10_super, |
085261c8 | 2333 | *,*,*,*,*,*,*")]) |
9db1d521 | 2334 | |
84817c5d UW |
2335 | (define_peephole2 |
2336 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2337 | (mem:QI (match_operand 1 "address_operand" "")))] | |
2338 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2339 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2340 | && get_pool_mode (operands[1]) == QImode | |
2341 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2342 | [(set (match_dup 0) (match_dup 2))] | |
2343 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2344 | |
9db1d521 | 2345 | ; |
05b9aaaa | 2346 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
2347 | ; |
2348 | ||
2349 | (define_insn "*movstrictqi" | |
d3632d41 UW |
2350 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
2351 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 2352 | "" |
d3632d41 | 2353 | "@ |
d40c829f UW |
2354 | ic\t%0,%1 |
2355 | icy\t%0,%1" | |
9381e3f1 | 2356 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 2357 | (set_attr "cpu_facility" "*,longdisp") |
729e750f | 2358 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2359 | |
2360 | ; | |
2361 | ; movstricthi instruction pattern(s). | |
2362 | ; | |
2363 | ||
2364 | (define_insn "*movstricthi" | |
d3632d41 | 2365 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 2366 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 2367 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2368 | "" |
d3632d41 | 2369 | "@ |
fc0ea003 UW |
2370 | icm\t%0,3,%S1 |
2371 | icmy\t%0,3,%S1" | |
9381e3f1 | 2372 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2373 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2374 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2375 | |
2376 | ; | |
2377 | ; movstrictsi instruction pattern(s). | |
2378 | ; | |
2379 | ||
05b9aaaa | 2380 | (define_insn "movstrictsi" |
c5aa1d12 UW |
2381 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
2382 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9602b6a1 | 2383 | "TARGET_ZARCH" |
9db1d521 | 2384 | "@ |
d40c829f UW |
2385 | lr\t%0,%1 |
2386 | l\t%0,%1 | |
c5aa1d12 UW |
2387 | ly\t%0,%1 |
2388 | ear\t%0,%1" | |
2389 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 | 2390 | (set_attr "type" "lr,load,load,*") |
3e4be43f | 2391 | (set_attr "cpu_facility" "*,*,longdisp,*") |
9381e3f1 | 2392 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) |
9db1d521 | 2393 | |
f61a2c7d | 2394 | ; |
609e7e80 | 2395 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
2396 | ; |
2397 | ||
609e7e80 AK |
2398 | (define_expand "mov<mode>" |
2399 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
2400 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
2401 | "" |
2402 | "") | |
2403 | ||
609e7e80 | 2404 | (define_insn "*mov<mode>_64" |
3e4be43f UW |
2405 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o") |
2406 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))] | |
9602b6a1 | 2407 | "TARGET_ZARCH" |
f61a2c7d | 2408 | "@ |
65b1d8ea | 2409 | lzxr\t%0 |
f61a2c7d AK |
2410 | lxr\t%0,%1 |
2411 | # | |
2412 | # | |
2413 | lmg\t%0,%N0,%S1 | |
2414 | stmg\t%1,%N1,%S0 | |
2415 | # | |
f61a2c7d | 2416 | #" |
65b1d8ea AK |
2417 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
2418 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") | |
2419 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) | |
f61a2c7d | 2420 | |
609e7e80 | 2421 | (define_insn "*mov<mode>_31" |
65b1d8ea AK |
2422 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
2423 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
9602b6a1 | 2424 | "!TARGET_ZARCH" |
f61a2c7d | 2425 | "@ |
65b1d8ea | 2426 | lzxr\t%0 |
f61a2c7d AK |
2427 | lxr\t%0,%1 |
2428 | # | |
f61a2c7d | 2429 | #" |
65b1d8ea AK |
2430 | [(set_attr "op_type" "RRE,RRE,*,*") |
2431 | (set_attr "type" "fsimptf,fsimptf,*,*") | |
2432 | (set_attr "cpu_facility" "z196,*,*,*")]) | |
f61a2c7d AK |
2433 | |
2434 | ; TFmode in GPRs splitters | |
2435 | ||
2436 | (define_split | |
609e7e80 AK |
2437 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2438 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2439 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
2440 | && !s_operand (operands[0], <MODE>mode) |
2441 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2442 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
2443 | [(set (match_dup 2) (match_dup 4)) |
2444 | (set (match_dup 3) (match_dup 5))] | |
2445 | { | |
609e7e80 AK |
2446 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2447 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2448 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2449 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
2450 | }) |
2451 | ||
2452 | (define_split | |
609e7e80 AK |
2453 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2454 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2455 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
2456 | && !s_operand (operands[0], <MODE>mode) |
2457 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2458 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
2459 | [(set (match_dup 2) (match_dup 4)) |
2460 | (set (match_dup 3) (match_dup 5))] | |
2461 | { | |
609e7e80 AK |
2462 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2463 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2464 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2465 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
2466 | }) |
2467 | ||
2468 | (define_split | |
609e7e80 AK |
2469 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2470 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9602b6a1 | 2471 | "TARGET_ZARCH && reload_completed |
085261c8 | 2472 | && GENERAL_REG_P (operands[0]) |
f61a2c7d AK |
2473 | && !s_operand (operands[1], VOIDmode)" |
2474 | [(set (match_dup 0) (match_dup 1))] | |
2475 | { | |
609e7e80 | 2476 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a9e6994a | 2477 | addr = gen_lowpart (Pmode, addr); |
f61a2c7d AK |
2478 | s390_load_address (addr, XEXP (operands[1], 0)); |
2479 | operands[1] = replace_equiv_address (operands[1], addr); | |
2480 | }) | |
2481 | ||
7b6baae1 | 2482 | ; TFmode in BFPs splitters |
f61a2c7d AK |
2483 | |
2484 | (define_split | |
609e7e80 AK |
2485 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2486 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 2487 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
2488 | && FP_REG_P (operands[0])" |
2489 | [(set (match_dup 2) (match_dup 4)) | |
2490 | (set (match_dup 3) (match_dup 5))] | |
2491 | { | |
609e7e80 AK |
2492 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
2493 | <MODE>mode, 0); | |
2494 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
2495 | <MODE>mode, 8); | |
2496 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
2497 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
2498 | }) |
2499 | ||
2500 | (define_split | |
609e7e80 AK |
2501 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
2502 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
2503 | "reload_completed && offsettable_memref_p (operands[0]) |
2504 | && FP_REG_P (operands[1])" | |
2505 | [(set (match_dup 2) (match_dup 4)) | |
2506 | (set (match_dup 3) (match_dup 5))] | |
2507 | { | |
609e7e80 AK |
2508 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
2509 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
2510 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2511 | <MODE>mode, 0); | |
2512 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2513 | <MODE>mode, 8); | |
f61a2c7d AK |
2514 | }) |
2515 | ||
9db1d521 | 2516 | ; |
609e7e80 | 2517 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
2518 | ; |
2519 | ||
609e7e80 AK |
2520 | (define_expand "mov<mode>" |
2521 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2522 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 2523 | "" |
13c025c1 | 2524 | "") |
9db1d521 | 2525 | |
609e7e80 AK |
2526 | (define_insn "*mov<mode>_64dfp" |
2527 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
590961cf | 2528 | "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,v,d,v,R") |
609e7e80 | 2529 | (match_operand:DD_DF 1 "general_operand" |
590961cf | 2530 | " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,G,d,v,R,v"))] |
9602b6a1 | 2531 | "TARGET_DFP" |
85dae55a | 2532 | "@ |
65b1d8ea | 2533 | lzdr\t%0 |
85dae55a AK |
2534 | ldr\t%0,%1 |
2535 | ldgr\t%0,%1 | |
2536 | lgdr\t%0,%1 | |
2537 | ld\t%0,%1 | |
2538 | ldy\t%0,%1 | |
2539 | std\t%1,%0 | |
2540 | stdy\t%1,%0 | |
45e5214c | 2541 | lghi\t%0,0 |
85dae55a | 2542 | lgr\t%0,%1 |
085261c8 | 2543 | lgrl\t%0,%1 |
85dae55a | 2544 | lg\t%0,%1 |
085261c8 AK |
2545 | stgrl\t%1,%0 |
2546 | stg\t%1,%0 | |
2547 | vlr\t%v0,%v1 | |
590961cf | 2548 | vleig\t%v0,0,0 |
085261c8 AK |
2549 | vlvgg\t%v0,%1,0 |
2550 | vlgvg\t%0,%v1,0 | |
2551 | vleg\t%0,%1,0 | |
2552 | vsteg\t%1,%0,0" | |
590961cf | 2553 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRI,VRS,VRS,VRX,VRX") |
65b1d8ea | 2554 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, |
590961cf AK |
2555 | fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,*,load,store") |
2556 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*,*") | |
14cfceb7 IL |
2557 | (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx,vx") |
2558 | (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*,yes,*,yes,*,*,*,*,*,*,*")]) | |
85dae55a | 2559 | |
609e7e80 | 2560 | (define_insn "*mov<mode>_64" |
590961cf AK |
2561 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T") |
2562 | (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d"))] | |
9602b6a1 | 2563 | "TARGET_ZARCH" |
9db1d521 | 2564 | "@ |
65b1d8ea | 2565 | lzdr\t%0 |
d40c829f UW |
2566 | ldr\t%0,%1 |
2567 | ld\t%0,%1 | |
2568 | ldy\t%0,%1 | |
2569 | std\t%1,%0 | |
2570 | stdy\t%1,%0 | |
45e5214c | 2571 | lghi\t%0,0 |
d40c829f | 2572 | lgr\t%0,%1 |
085261c8 | 2573 | lgrl\t%0,%1 |
d40c829f | 2574 | lg\t%0,%1 |
085261c8 | 2575 | stgrl\t%1,%0 |
590961cf AK |
2576 | stg\t%1,%0" |
2577 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY") | |
65b1d8ea | 2578 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, |
590961cf AK |
2579 | fstore<mode>,fstore<mode>,*,lr,load,load,store,store") |
2580 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") | |
14cfceb7 IL |
2581 | (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*") |
2582 | (set_attr "relative_long" "*,*,*,*,*,*,*,*,yes,*,*,*")]) | |
609e7e80 AK |
2583 | |
2584 | (define_insn "*mov<mode>_31" | |
2585 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
3e4be43f | 2586 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2587 | (match_operand:DD_DF 1 "general_operand" |
3e4be43f | 2588 | " G,f,R,T,f,f,Q,S,d,d,dPT,d"))] |
9602b6a1 | 2589 | "!TARGET_ZARCH" |
9db1d521 | 2590 | "@ |
65b1d8ea | 2591 | lzdr\t%0 |
d40c829f UW |
2592 | ldr\t%0,%1 |
2593 | ld\t%0,%1 | |
2594 | ldy\t%0,%1 | |
2595 | std\t%1,%0 | |
2596 | stdy\t%1,%0 | |
fc0ea003 | 2597 | lm\t%0,%N0,%S1 |
c4d50129 | 2598 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2599 | stm\t%1,%N1,%S0 |
c4d50129 | 2600 | stmy\t%1,%N1,%S0 |
4023fb28 | 2601 | # |
19b63d8e | 2602 | #" |
65b1d8ea AK |
2603 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
2604 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2605 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") | |
3e4be43f | 2606 | (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")]) |
4023fb28 UW |
2607 | |
2608 | (define_split | |
609e7e80 AK |
2609 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2610 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2611 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
2612 | && !s_operand (operands[0], <MODE>mode) |
2613 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2614 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2615 | [(set (match_dup 2) (match_dup 4)) |
2616 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2617 | { |
609e7e80 AK |
2618 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2619 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2620 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2621 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2622 | }) |
2623 | ||
2624 | (define_split | |
609e7e80 AK |
2625 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2626 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2627 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
2628 | && !s_operand (operands[0], <MODE>mode) |
2629 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2630 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2631 | [(set (match_dup 2) (match_dup 4)) |
2632 | (set (match_dup 3) (match_dup 5))] | |
2633 | { | |
609e7e80 AK |
2634 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2635 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2636 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2637 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2638 | }) |
9db1d521 | 2639 | |
4023fb28 | 2640 | (define_split |
609e7e80 AK |
2641 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2642 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
9602b6a1 | 2643 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 2644 | && !FP_REG_P (operands[0]) |
4023fb28 | 2645 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2646 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2647 | { |
609e7e80 | 2648 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2649 | s390_load_address (addr, XEXP (operands[1], 0)); |
2650 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2651 | }) |
2652 | ||
9db1d521 | 2653 | ; |
609e7e80 | 2654 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2655 | ; |
2656 | ||
609e7e80 AK |
2657 | (define_insn "mov<mode>" |
2658 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
3e4be43f | 2659 | "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R") |
609e7e80 | 2660 | (match_operand:SD_SF 1 "general_operand" |
3e4be43f | 2661 | " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))] |
4023fb28 | 2662 | "" |
9db1d521 | 2663 | "@ |
65b1d8ea | 2664 | lzer\t%0 |
ae1c6198 | 2665 | ldr\t%0,%1 |
d40c829f | 2666 | ler\t%0,%1 |
085261c8 | 2667 | lde\t%0,%1 |
d40c829f UW |
2668 | le\t%0,%1 |
2669 | ley\t%0,%1 | |
2670 | ste\t%1,%0 | |
2671 | stey\t%1,%0 | |
45e5214c | 2672 | lhi\t%0,0 |
d40c829f | 2673 | lr\t%0,%1 |
085261c8 | 2674 | lrl\t%0,%1 |
d40c829f UW |
2675 | l\t%0,%1 |
2676 | ly\t%0,%1 | |
085261c8 | 2677 | strl\t%1,%0 |
d40c829f | 2678 | st\t%1,%0 |
085261c8 AK |
2679 | sty\t%1,%0 |
2680 | vlr\t%v0,%v1 | |
298f4647 | 2681 | vleif\t%v0,0,0 |
085261c8 AK |
2682 | vlvgf\t%v0,%1,0 |
2683 | vlgvf\t%0,%v1,0 | |
298f4647 AK |
2684 | vlef\t%0,%1,0 |
2685 | vstef\t%1,%0,0" | |
ae1c6198 | 2686 | [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX") |
085261c8 AK |
2687 | (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>, |
2688 | fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store") | |
2689 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*") | |
14cfceb7 IL |
2690 | (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx") |
2691 | (set_attr "relative_long" "*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*,*,*,*,*")]) | |
4023fb28 | 2692 | |
9dc62c00 AK |
2693 | ; |
2694 | ; movcc instruction pattern | |
2695 | ; | |
2696 | ||
2697 | (define_insn "movcc" | |
2698 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
5a3fe9b6 | 2699 | (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))] |
9dc62c00 AK |
2700 | "" |
2701 | "@ | |
2702 | lr\t%0,%1 | |
2703 | tmh\t%1,12288 | |
2704 | ipm\t%0 | |
a71f0749 DV |
2705 | l\t%0,%1 |
2706 | ly\t%0,%1 | |
2707 | st\t%1,%0 | |
2708 | sty\t%1,%0" | |
8dd3b235 | 2709 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
a71f0749 | 2710 | (set_attr "type" "lr,*,*,load,load,store,store") |
3e4be43f | 2711 | (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp") |
a71f0749 | 2712 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") |
65b1d8ea | 2713 | (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) |
9dc62c00 | 2714 | |
19b63d8e UW |
2715 | ; |
2716 | ; Block move (MVC) patterns. | |
2717 | ; | |
2718 | ||
2719 | (define_insn "*mvc" | |
2720 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2721 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2722 | (use (match_operand 2 "const_int_operand" "n"))] | |
2723 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2724 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2725 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2726 | |
0a88561f AK |
2727 | ; This splitter converts a QI to QI mode copy into a BLK mode copy in |
2728 | ; order to have it implemented with mvc. | |
2729 | ||
2730 | (define_split | |
2731 | [(set (match_operand:QI 0 "memory_operand" "") | |
2732 | (match_operand:QI 1 "memory_operand" ""))] | |
2733 | "reload_completed" | |
2734 | [(parallel | |
2735 | [(set (match_dup 0) (match_dup 1)) | |
2736 | (use (const_int 1))])] | |
2737 | { | |
2738 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
2739 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2740 | }) | |
2741 | ||
2742 | ||
19b63d8e UW |
2743 | (define_peephole2 |
2744 | [(parallel | |
2745 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2746 | (match_operand:BLK 1 "memory_operand" "")) | |
2747 | (use (match_operand 2 "const_int_operand" ""))]) | |
2748 | (parallel | |
2749 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2750 | (match_operand:BLK 4 "memory_operand" "")) | |
2751 | (use (match_operand 5 "const_int_operand" ""))])] | |
f9dcf14a AK |
2752 | "((INTVAL (operands[2]) > 16 && INTVAL (operands[5]) > 16) |
2753 | || (INTVAL (operands[2]) + INTVAL (operands[5]) <= 16)) | |
2754 | && s390_offset_p (operands[0], operands[3], operands[2]) | |
19b63d8e | 2755 | && s390_offset_p (operands[1], operands[4], operands[2]) |
9381e3f1 | 2756 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2757 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2758 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2759 | [(parallel | |
2760 | [(set (match_dup 6) (match_dup 7)) | |
2761 | (use (match_dup 8))])] | |
2762 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2763 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2764 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2765 | ||
f9dcf14a AK |
2766 | (define_peephole2 |
2767 | [(parallel | |
2768 | [(set (match_operand:BLK 0 "plus16_Q_operand" "") | |
2769 | (match_operand:BLK 1 "plus16_Q_operand" "")) | |
2770 | (use (match_operand 2 "const_int_operand" ""))])] | |
2771 | "INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32" | |
2772 | [(parallel | |
2773 | [(set (match_dup 0) (match_dup 1)) | |
2774 | (use (const_int 16))]) | |
2775 | (parallel | |
2776 | [(set (match_dup 3) (match_dup 4)) | |
2777 | (use (match_dup 5))])] | |
2778 | "operands[3] = change_address (operands[0], VOIDmode, | |
2779 | plus_constant (Pmode, XEXP (operands[0], 0), 16)); | |
2780 | operands[4] = change_address (operands[1], VOIDmode, | |
2781 | plus_constant (Pmode, XEXP (operands[1], 0), 16)); | |
2782 | operands[5] = GEN_INT (INTVAL (operands[2]) - 16);") | |
2783 | ||
19b63d8e | 2784 | |
9db1d521 HP |
2785 | ; |
2786 | ; load_multiple pattern(s). | |
2787 | ; | |
22ea6b4f UW |
2788 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2789 | ; we currently support load_multiple/store_multiple only after reload. | |
2790 | ; | |
9db1d521 HP |
2791 | |
2792 | (define_expand "load_multiple" | |
2793 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2794 | (match_operand 1 "" "")) | |
2795 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2796 | "reload_completed" |
9db1d521 | 2797 | { |
ef4bddc2 | 2798 | machine_mode mode; |
9db1d521 HP |
2799 | int regno; |
2800 | int count; | |
2801 | rtx from; | |
4023fb28 | 2802 | int i, off; |
9db1d521 HP |
2803 | |
2804 | /* Support only loading a constant number of fixed-point registers from | |
2805 | memory and only bother with this if more than two */ | |
2806 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2807 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2808 | || INTVAL (operands[2]) > 16 |
2809 | || GET_CODE (operands[1]) != MEM | |
2810 | || GET_CODE (operands[0]) != REG | |
2811 | || REGNO (operands[0]) >= 16) | |
2812 | FAIL; | |
2813 | ||
2814 | count = INTVAL (operands[2]); | |
2815 | regno = REGNO (operands[0]); | |
c19ec8f9 | 2816 | mode = GET_MODE (operands[0]); |
9602b6a1 | 2817 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2818 | FAIL; |
9db1d521 HP |
2819 | |
2820 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2821 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2822 | { |
2823 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2824 | { | |
2825 | from = XEXP (operands[1], 0); | |
2826 | off = 0; | |
2827 | } | |
2828 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2829 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2830 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2831 | { | |
2832 | from = XEXP (XEXP (operands[1], 0), 0); | |
2833 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2834 | } | |
2835 | else | |
2836 | FAIL; | |
4023fb28 UW |
2837 | } |
2838 | else | |
2839 | { | |
2840 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2841 | off = 0; | |
2842 | } | |
9db1d521 HP |
2843 | |
2844 | for (i = 0; i < count; i++) | |
2845 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2846 | = gen_rtx_SET (gen_rtx_REG (mode, regno + i), |
c19ec8f9 | 2847 | change_address (operands[1], mode, |
0a81f074 RS |
2848 | plus_constant (Pmode, from, |
2849 | off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2850 | }) |
9db1d521 HP |
2851 | |
2852 | (define_insn "*load_multiple_di" | |
2853 | [(match_parallel 0 "load_multiple_operation" | |
2854 | [(set (match_operand:DI 1 "register_operand" "=r") | |
3e4be43f | 2855 | (match_operand:DI 2 "s_operand" "S"))])] |
9602b6a1 | 2856 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2857 | { |
2858 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2859 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2860 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2861 | } |
d3632d41 | 2862 | [(set_attr "op_type" "RSY") |
4023fb28 | 2863 | (set_attr "type" "lm")]) |
9db1d521 HP |
2864 | |
2865 | (define_insn "*load_multiple_si" | |
2866 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2867 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2868 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2869 | "reload_completed" |
9db1d521 HP |
2870 | { |
2871 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2872 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2873 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2874 | } |
d3632d41 | 2875 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2876 | (set_attr "cpu_facility" "*,longdisp") |
4023fb28 | 2877 | (set_attr "type" "lm")]) |
9db1d521 HP |
2878 | |
2879 | ; | |
c7453384 | 2880 | ; store multiple pattern(s). |
9db1d521 HP |
2881 | ; |
2882 | ||
2883 | (define_expand "store_multiple" | |
2884 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2885 | (match_operand 1 "" "")) | |
2886 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2887 | "reload_completed" |
9db1d521 | 2888 | { |
ef4bddc2 | 2889 | machine_mode mode; |
9db1d521 HP |
2890 | int regno; |
2891 | int count; | |
2892 | rtx to; | |
4023fb28 | 2893 | int i, off; |
9db1d521 HP |
2894 | |
2895 | /* Support only storing a constant number of fixed-point registers to | |
2896 | memory and only bother with this if more than two. */ | |
2897 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2898 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2899 | || INTVAL (operands[2]) > 16 |
2900 | || GET_CODE (operands[0]) != MEM | |
2901 | || GET_CODE (operands[1]) != REG | |
2902 | || REGNO (operands[1]) >= 16) | |
2903 | FAIL; | |
2904 | ||
2905 | count = INTVAL (operands[2]); | |
2906 | regno = REGNO (operands[1]); | |
c19ec8f9 | 2907 | mode = GET_MODE (operands[1]); |
9602b6a1 | 2908 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2909 | FAIL; |
9db1d521 HP |
2910 | |
2911 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2912 | |
b3a13419 | 2913 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2914 | { |
2915 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2916 | { | |
2917 | to = XEXP (operands[0], 0); | |
2918 | off = 0; | |
2919 | } | |
2920 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2921 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2922 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2923 | { | |
2924 | to = XEXP (XEXP (operands[0], 0), 0); | |
2925 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2926 | } | |
2927 | else | |
2928 | FAIL; | |
4023fb28 | 2929 | } |
c7453384 | 2930 | else |
4023fb28 UW |
2931 | { |
2932 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2933 | off = 0; | |
2934 | } | |
9db1d521 HP |
2935 | |
2936 | for (i = 0; i < count; i++) | |
2937 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2938 | = gen_rtx_SET (change_address (operands[0], mode, |
0a81f074 RS |
2939 | plus_constant (Pmode, to, |
2940 | off + i * GET_MODE_SIZE (mode))), | |
c19ec8f9 | 2941 | gen_rtx_REG (mode, regno + i)); |
10bbf137 | 2942 | }) |
9db1d521 HP |
2943 | |
2944 | (define_insn "*store_multiple_di" | |
2945 | [(match_parallel 0 "store_multiple_operation" | |
3e4be43f | 2946 | [(set (match_operand:DI 1 "s_operand" "=S") |
9db1d521 | 2947 | (match_operand:DI 2 "register_operand" "r"))])] |
9602b6a1 | 2948 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2949 | { |
2950 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2951 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2952 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 2953 | } |
d3632d41 | 2954 | [(set_attr "op_type" "RSY") |
4023fb28 | 2955 | (set_attr "type" "stm")]) |
9db1d521 HP |
2956 | |
2957 | ||
2958 | (define_insn "*store_multiple_si" | |
2959 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
2960 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
2961 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 2962 | "reload_completed" |
9db1d521 HP |
2963 | { |
2964 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2965 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2966 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 2967 | } |
d3632d41 | 2968 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2969 | (set_attr "cpu_facility" "*,longdisp") |
4023fb28 | 2970 | (set_attr "type" "stm")]) |
9db1d521 HP |
2971 | |
2972 | ;; | |
2973 | ;; String instructions. | |
2974 | ;; | |
2975 | ||
963fc8d0 | 2976 | (define_insn "*execute_rl" |
2771c2f9 | 2977 | [(match_parallel 0 "execute_operation" |
963fc8d0 AK |
2978 | [(unspec [(match_operand 1 "register_operand" "a") |
2979 | (match_operand 2 "" "") | |
2980 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
2981 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2982 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2983 | "exrl\t%1,%3" | |
2984 | [(set_attr "op_type" "RIL") | |
14cfceb7 IL |
2985 | (set_attr "type" "cs") |
2986 | (set_attr "relative_long" "yes")]) | |
963fc8d0 | 2987 | |
9bb86f41 | 2988 | (define_insn "*execute" |
2771c2f9 | 2989 | [(match_parallel 0 "execute_operation" |
9bb86f41 UW |
2990 | [(unspec [(match_operand 1 "register_operand" "a") |
2991 | (match_operand:BLK 2 "memory_operand" "R") | |
2992 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
2993 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2994 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2995 | "ex\t%1,%2" | |
29a74354 UW |
2996 | [(set_attr "op_type" "RX") |
2997 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
2998 | |
2999 | ||
91d39d71 UW |
3000 | ; |
3001 | ; strlenM instruction pattern(s). | |
3002 | ; | |
3003 | ||
9db2f16d | 3004 | (define_expand "strlen<mode>" |
085261c8 AK |
3005 | [(match_operand:P 0 "register_operand" "") ; result |
3006 | (match_operand:BLK 1 "memory_operand" "") ; input string | |
3007 | (match_operand:SI 2 "immediate_operand" "") ; search character | |
3008 | (match_operand:SI 3 "immediate_operand" "")] ; known alignment | |
3009 | "" | |
3010 | { | |
3011 | if (!TARGET_VX || operands[2] != const0_rtx) | |
3012 | emit_insn (gen_strlen_srst<mode> (operands[0], operands[1], | |
3013 | operands[2], operands[3])); | |
3014 | else | |
3015 | s390_expand_vec_strlen (operands[0], operands[1], operands[3]); | |
3016 | ||
3017 | DONE; | |
3018 | }) | |
3019 | ||
3020 | (define_expand "strlen_srst<mode>" | |
ccbdc0d4 | 3021 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 3022 | (parallel |
91d39d71 | 3023 | [(set (match_dup 4) |
9db2f16d | 3024 | (unspec:P [(const_int 0) |
91d39d71 | 3025 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 3026 | (reg:SI 0) |
91d39d71 | 3027 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 3028 | (clobber (scratch:P)) |
ae156f85 | 3029 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 3030 | (parallel |
9db2f16d AS |
3031 | [(set (match_operand:P 0 "register_operand" "") |
3032 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 3033 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 3034 | "" |
91d39d71 | 3035 | { |
9db2f16d AS |
3036 | operands[4] = gen_reg_rtx (Pmode); |
3037 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
3038 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3039 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
3040 | }) | |
3041 | ||
9db2f16d AS |
3042 | (define_insn "*strlen<mode>" |
3043 | [(set (match_operand:P 0 "register_operand" "=a") | |
3044 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
3045 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 3046 | (reg:SI 0) |
91d39d71 | 3047 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 3048 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 3049 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 3050 | "" |
91d39d71 | 3051 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
3052 | [(set_attr "length" "8") |
3053 | (set_attr "type" "vs")]) | |
91d39d71 | 3054 | |
ccbdc0d4 AS |
3055 | ; |
3056 | ; cmpstrM instruction pattern(s). | |
3057 | ; | |
3058 | ||
3059 | (define_expand "cmpstrsi" | |
3060 | [(set (reg:SI 0) (const_int 0)) | |
3061 | (parallel | |
3062 | [(clobber (match_operand 3 "" "")) | |
3063 | (clobber (match_dup 4)) | |
3064 | (set (reg:CCU CC_REGNUM) | |
3065 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
3066 | (match_operand:BLK 2 "memory_operand" ""))) | |
3067 | (use (reg:SI 0))]) | |
3068 | (parallel | |
3069 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3070 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT)) |
ccbdc0d4 AS |
3071 | (clobber (reg:CC CC_REGNUM))])] |
3072 | "" | |
3073 | { | |
3074 | /* As the result of CMPINT is inverted compared to what we need, | |
3075 | we have to swap the operands. */ | |
3076 | rtx op1 = operands[2]; | |
3077 | rtx op2 = operands[1]; | |
3078 | rtx addr1 = gen_reg_rtx (Pmode); | |
3079 | rtx addr2 = gen_reg_rtx (Pmode); | |
3080 | ||
3081 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
3082 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
3083 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
3084 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
3085 | operands[3] = addr1; | |
3086 | operands[4] = addr2; | |
3087 | }) | |
3088 | ||
3089 | (define_insn "*cmpstr<mode>" | |
3090 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
3091 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
3092 | (set (reg:CCU CC_REGNUM) | |
3093 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
3094 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
3095 | (use (reg:SI 0))] | |
3096 | "" | |
3097 | "clst\t%0,%1\;jo\t.-4" | |
3098 | [(set_attr "length" "8") | |
3099 | (set_attr "type" "vs")]) | |
9381e3f1 | 3100 | |
742090fc AS |
3101 | ; |
3102 | ; movstr instruction pattern. | |
3103 | ; | |
3104 | ||
3105 | (define_expand "movstr" | |
4a7dec25 DV |
3106 | [(match_operand 0 "register_operand" "") |
3107 | (match_operand 1 "memory_operand" "") | |
3108 | (match_operand 2 "memory_operand" "")] | |
3109 | "" | |
3110 | { | |
3111 | if (TARGET_64BIT) | |
3112 | emit_insn (gen_movstrdi (operands[0], operands[1], operands[2])); | |
3113 | else | |
3114 | emit_insn (gen_movstrsi (operands[0], operands[1], operands[2])); | |
3115 | DONE; | |
3116 | }) | |
3117 | ||
3118 | (define_expand "movstr<P:mode>" | |
742090fc | 3119 | [(set (reg:SI 0) (const_int 0)) |
9381e3f1 | 3120 | (parallel |
742090fc AS |
3121 | [(clobber (match_dup 3)) |
3122 | (set (match_operand:BLK 1 "memory_operand" "") | |
3123 | (match_operand:BLK 2 "memory_operand" "")) | |
4a7dec25 DV |
3124 | (set (match_operand:P 0 "register_operand" "") |
3125 | (unspec:P [(match_dup 1) | |
742090fc AS |
3126 | (match_dup 2) |
3127 | (reg:SI 0)] UNSPEC_MVST)) | |
3128 | (clobber (reg:CC CC_REGNUM))])] | |
3129 | "" | |
3130 | { | |
859a4c0e AK |
3131 | rtx addr1, addr2; |
3132 | ||
3133 | if (TARGET_VX && optimize_function_for_speed_p (cfun)) | |
3134 | { | |
3135 | s390_expand_vec_movstr (operands[0], operands[1], operands[2]); | |
3136 | DONE; | |
3137 | } | |
3138 | ||
3139 | addr1 = gen_reg_rtx (Pmode); | |
3140 | addr2 = gen_reg_rtx (Pmode); | |
742090fc AS |
3141 | |
3142 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
3143 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
3144 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3145 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
3146 | operands[3] = addr2; | |
3147 | }) | |
3148 | ||
3149 | (define_insn "*movstr" | |
3150 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
3151 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
3152 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
3153 | (set (match_operand:P 0 "register_operand" "=d") | |
4a7dec25 | 3154 | (unspec:P [(mem:BLK (match_dup 1)) |
742090fc AS |
3155 | (mem:BLK (match_dup 3)) |
3156 | (reg:SI 0)] UNSPEC_MVST)) | |
3157 | (clobber (reg:CC CC_REGNUM))] | |
3158 | "" | |
3159 | "mvst\t%1,%2\;jo\t.-4" | |
3160 | [(set_attr "length" "8") | |
3161 | (set_attr "type" "vs")]) | |
9381e3f1 | 3162 | |
742090fc | 3163 | |
9db1d521 | 3164 | ; |
70128ad9 | 3165 | ; movmemM instruction pattern(s). |
9db1d521 HP |
3166 | ; |
3167 | ||
9db2f16d | 3168 | (define_expand "movmem<mode>" |
963fc8d0 AK |
3169 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
3170 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
3171 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
3172 | (match_operand 3 "" "")] |
3173 | "" | |
367d32f3 AK |
3174 | { |
3175 | if (s390_expand_movmem (operands[0], operands[1], operands[2])) | |
3176 | DONE; | |
3177 | else | |
3178 | FAIL; | |
3179 | }) | |
9db1d521 | 3180 | |
ecbe845e UW |
3181 | ; Move a block that is up to 256 bytes in length. |
3182 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3183 | |
70128ad9 | 3184 | (define_expand "movmem_short" |
b9404c99 UW |
3185 | [(parallel |
3186 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3187 | (match_operand:BLK 1 "memory_operand" "")) | |
3188 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3189 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3190 | (clobber (match_dup 3))])] |
3191 | "" | |
3192 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 3193 | |
70128ad9 | 3194 | (define_insn "*movmem_short" |
963fc8d0 AK |
3195 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
3196 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
3197 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3198 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3199 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3200 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3201 | "#" |
963fc8d0 | 3202 | [(set_attr "type" "cs") |
b5e0425c | 3203 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
ecbe845e | 3204 | |
9bb86f41 UW |
3205 | (define_split |
3206 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3207 | (match_operand:BLK 1 "memory_operand" "")) | |
3208 | (use (match_operand 2 "const_int_operand" "")) | |
3209 | (use (match_operand 3 "immediate_operand" "")) | |
3210 | (clobber (scratch))] | |
3211 | "reload_completed" | |
3212 | [(parallel | |
3213 | [(set (match_dup 0) (match_dup 1)) | |
3214 | (use (match_dup 2))])] | |
3215 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3216 | |
9bb86f41 UW |
3217 | (define_split |
3218 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3219 | (match_operand:BLK 1 "memory_operand" "")) | |
3220 | (use (match_operand 2 "register_operand" "")) | |
3221 | (use (match_operand 3 "memory_operand" "")) | |
3222 | (clobber (scratch))] | |
3223 | "reload_completed" | |
3224 | [(parallel | |
3225 | [(unspec [(match_dup 2) (match_dup 3) | |
3226 | (const_int 0)] UNSPEC_EXECUTE) | |
3227 | (set (match_dup 0) (match_dup 1)) | |
3228 | (use (const_int 1))])] | |
3229 | "") | |
3230 | ||
963fc8d0 AK |
3231 | (define_split |
3232 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3233 | (match_operand:BLK 1 "memory_operand" "")) | |
3234 | (use (match_operand 2 "register_operand" "")) | |
3235 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3236 | (clobber (scratch))] | |
3237 | "TARGET_Z10 && reload_completed" | |
3238 | [(parallel | |
3239 | [(unspec [(match_dup 2) (const_int 0) | |
3240 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3241 | (set (match_dup 0) (match_dup 1)) | |
3242 | (use (const_int 1))])] | |
3243 | "operands[3] = gen_label_rtx ();") | |
3244 | ||
9bb86f41 UW |
3245 | (define_split |
3246 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3247 | (match_operand:BLK 1 "memory_operand" "")) | |
3248 | (use (match_operand 2 "register_operand" "")) | |
3249 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3250 | (clobber (match_operand 3 "register_operand" ""))] | |
8cc6307c | 3251 | "reload_completed" |
9bb86f41 UW |
3252 | [(set (match_dup 3) (label_ref (match_dup 4))) |
3253 | (parallel | |
9381e3f1 | 3254 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
3255 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
3256 | (set (match_dup 0) (match_dup 1)) | |
3257 | (use (const_int 1))])] | |
3258 | "operands[4] = gen_label_rtx ();") | |
3259 | ||
a41c6c53 | 3260 | ; Move a block of arbitrary length. |
9db1d521 | 3261 | |
70128ad9 | 3262 | (define_expand "movmem_long" |
b9404c99 UW |
3263 | [(parallel |
3264 | [(clobber (match_dup 2)) | |
3265 | (clobber (match_dup 3)) | |
3266 | (set (match_operand:BLK 0 "memory_operand" "") | |
3267 | (match_operand:BLK 1 "memory_operand" "")) | |
3268 | (use (match_operand 2 "general_operand" "")) | |
3269 | (use (match_dup 3)) | |
ae156f85 | 3270 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3271 | "" |
3272 | { | |
ef4bddc2 RS |
3273 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3274 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3275 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3276 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3277 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3278 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3279 | rtx len0 = gen_lowpart (Pmode, reg0); |
3280 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3281 | ||
c41c1387 | 3282 | emit_clobber (reg0); |
b9404c99 UW |
3283 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3284 | emit_move_insn (len0, operands[2]); | |
3285 | ||
c41c1387 | 3286 | emit_clobber (reg1); |
b9404c99 UW |
3287 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3288 | emit_move_insn (len1, operands[2]); | |
3289 | ||
3290 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3291 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3292 | operands[2] = reg0; | |
3293 | operands[3] = reg1; | |
3294 | }) | |
3295 | ||
a1aed706 AS |
3296 | (define_insn "*movmem_long" |
3297 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3298 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
3299 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
3300 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
3301 | (use (match_dup 2)) |
3302 | (use (match_dup 3)) | |
ae156f85 | 3303 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 AK |
3304 | "TARGET_64BIT || !TARGET_ZARCH" |
3305 | "mvcle\t%0,%1,0\;jo\t.-4" | |
3306 | [(set_attr "length" "8") | |
3307 | (set_attr "type" "vs")]) | |
3308 | ||
3309 | (define_insn "*movmem_long_31z" | |
3310 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3311 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3312 | (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3313 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) | |
3314 | (use (match_dup 2)) | |
3315 | (use (match_dup 3)) | |
3316 | (clobber (reg:CC CC_REGNUM))] | |
3317 | "!TARGET_64BIT && TARGET_ZARCH" | |
d40c829f | 3318 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3319 | [(set_attr "length" "8") |
3320 | (set_attr "type" "vs")]) | |
9db1d521 | 3321 | |
638e37c2 WG |
3322 | |
3323 | ; | |
3324 | ; Test data class. | |
3325 | ; | |
3326 | ||
0f67fa83 WG |
3327 | (define_expand "signbit<mode>2" |
3328 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3329 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3330 | (match_dup 2)] | |
0f67fa83 WG |
3331 | UNSPEC_TDC_INSN)) |
3332 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3333 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
0f67fa83 WG |
3334 | "TARGET_HARD_FLOAT" |
3335 | { | |
3336 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
3337 | }) | |
3338 | ||
638e37c2 WG |
3339 | (define_expand "isinf<mode>2" |
3340 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3341 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3342 | (match_dup 2)] | |
638e37c2 WG |
3343 | UNSPEC_TDC_INSN)) |
3344 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3345 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
142cd70f | 3346 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
3347 | { |
3348 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
3349 | }) | |
3350 | ||
085261c8 AK |
3351 | ; This extracts CC into a GPR properly shifted. The actual IPM |
3352 | ; instruction will be issued by reload. The constraint of operand 1 | |
3353 | ; forces reload to use a GPR. So reload will issue a movcc insn for | |
3354 | ; copying CC into a GPR first. | |
5a3fe9b6 | 3355 | (define_insn_and_split "*cc_to_int" |
085261c8 | 3356 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
5a3fe9b6 AK |
3357 | (unspec:SI [(match_operand 1 "register_operand" "0")] |
3358 | UNSPEC_CC_TO_INT))] | |
3359 | "operands != NULL" | |
3360 | "#" | |
3361 | "reload_completed" | |
3362 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
3363 | ||
638e37c2 WG |
3364 | ; This insn is used to generate all variants of the Test Data Class |
3365 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
3366 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 3367 | ; specifying the required test(s). |
638e37c2 | 3368 | ; |
be5de7a1 | 3369 | ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet |
638e37c2 WG |
3370 | (define_insn "*TDC_insn_<mode>" |
3371 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 3372 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 3373 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 3374 | "TARGET_HARD_FLOAT" |
0387c142 | 3375 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 3376 | [(set_attr "op_type" "RXE") |
9381e3f1 | 3377 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 | 3378 | |
638e37c2 WG |
3379 | |
3380 | ||
9db1d521 | 3381 | ; |
57e84f18 | 3382 | ; setmemM instruction pattern(s). |
9db1d521 HP |
3383 | ; |
3384 | ||
57e84f18 | 3385 | (define_expand "setmem<mode>" |
a41c6c53 | 3386 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 3387 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 3388 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 3389 | (match_operand 3 "" "")] |
a41c6c53 | 3390 | "" |
6d057022 | 3391 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 3392 | |
a41c6c53 | 3393 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
3394 | ; The block length is taken as (operands[1] % 256) + 1. |
3395 | ||
70128ad9 | 3396 | (define_expand "clrmem_short" |
b9404c99 UW |
3397 | [(parallel |
3398 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3399 | (const_int 0)) | |
3400 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 3401 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 3402 | (clobber (match_dup 2)) |
ae156f85 | 3403 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3404 | "" |
3405 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3406 | |
70128ad9 | 3407 | (define_insn "*clrmem_short" |
963fc8d0 | 3408 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 3409 | (const_int 0)) |
963fc8d0 AK |
3410 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
3411 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
1eae36f0 | 3412 | (clobber (match_scratch:P 3 "=X,X,X,&a")) |
ae156f85 | 3413 | (clobber (reg:CC CC_REGNUM))] |
1eae36f0 | 3414 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" |
9bb86f41 | 3415 | "#" |
963fc8d0 | 3416 | [(set_attr "type" "cs") |
b5e0425c | 3417 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9bb86f41 UW |
3418 | |
3419 | (define_split | |
3420 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3421 | (const_int 0)) | |
3422 | (use (match_operand 1 "const_int_operand" "")) | |
3423 | (use (match_operand 2 "immediate_operand" "")) | |
3424 | (clobber (scratch)) | |
ae156f85 | 3425 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3426 | "reload_completed" |
3427 | [(parallel | |
3428 | [(set (match_dup 0) (const_int 0)) | |
3429 | (use (match_dup 1)) | |
ae156f85 | 3430 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3431 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 3432 | |
9bb86f41 UW |
3433 | (define_split |
3434 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3435 | (const_int 0)) | |
3436 | (use (match_operand 1 "register_operand" "")) | |
3437 | (use (match_operand 2 "memory_operand" "")) | |
3438 | (clobber (scratch)) | |
ae156f85 | 3439 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3440 | "reload_completed" |
3441 | [(parallel | |
3442 | [(unspec [(match_dup 1) (match_dup 2) | |
3443 | (const_int 0)] UNSPEC_EXECUTE) | |
3444 | (set (match_dup 0) (const_int 0)) | |
3445 | (use (const_int 1)) | |
ae156f85 | 3446 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3447 | "") |
9db1d521 | 3448 | |
963fc8d0 AK |
3449 | (define_split |
3450 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3451 | (const_int 0)) | |
3452 | (use (match_operand 1 "register_operand" "")) | |
3453 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3454 | (clobber (scratch)) | |
3455 | (clobber (reg:CC CC_REGNUM))] | |
3456 | "TARGET_Z10 && reload_completed" | |
3457 | [(parallel | |
3458 | [(unspec [(match_dup 1) (const_int 0) | |
3459 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3460 | (set (match_dup 0) (const_int 0)) | |
3461 | (use (const_int 1)) | |
3462 | (clobber (reg:CC CC_REGNUM))])] | |
3463 | "operands[3] = gen_label_rtx ();") | |
3464 | ||
9bb86f41 UW |
3465 | (define_split |
3466 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3467 | (const_int 0)) | |
3468 | (use (match_operand 1 "register_operand" "")) | |
3469 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3470 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 3471 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 3472 | "reload_completed" |
9bb86f41 UW |
3473 | [(set (match_dup 2) (label_ref (match_dup 3))) |
3474 | (parallel | |
9381e3f1 | 3475 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
3476 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
3477 | (set (match_dup 0) (const_int 0)) | |
3478 | (use (const_int 1)) | |
ae156f85 | 3479 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
3480 | "operands[3] = gen_label_rtx ();") |
3481 | ||
9381e3f1 | 3482 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 3483 | |
da0dcab1 | 3484 | (define_expand "setmem_long_<P:mode>" |
b9404c99 UW |
3485 | [(parallel |
3486 | [(clobber (match_dup 1)) | |
3487 | (set (match_operand:BLK 0 "memory_operand" "") | |
dd95128b | 3488 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "") |
da0dcab1 | 3489 | (match_dup 4)] UNSPEC_REPLICATE_BYTE)) |
6d057022 | 3490 | (use (match_dup 3)) |
ae156f85 | 3491 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 3492 | "" |
a41c6c53 | 3493 | { |
ef4bddc2 RS |
3494 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3495 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3496 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3497 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3498 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
b9404c99 | 3499 | rtx len0 = gen_lowpart (Pmode, reg0); |
9db1d521 | 3500 | |
c41c1387 | 3501 | emit_clobber (reg0); |
b9404c99 UW |
3502 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3503 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 3504 | |
b9404c99 | 3505 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 3506 | |
b9404c99 UW |
3507 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
3508 | operands[1] = reg0; | |
6d057022 | 3509 | operands[3] = reg1; |
da0dcab1 | 3510 | operands[4] = gen_lowpart (Pmode, operands[1]); |
b9404c99 | 3511 | }) |
a41c6c53 | 3512 | |
da0dcab1 DV |
3513 | ; Patterns for 31 bit + Esa and 64 bit + Zarch. |
3514 | ||
db340c73 | 3515 | (define_insn "*setmem_long" |
a1aed706 | 3516 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 3517 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
dd95128b | 3518 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y") |
da0dcab1 DV |
3519 | (subreg:P (match_dup 3) <modesize>)] |
3520 | UNSPEC_REPLICATE_BYTE)) | |
a1aed706 | 3521 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 3522 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3523 | "TARGET_64BIT || !TARGET_ZARCH" |
6d057022 | 3524 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
3525 | [(set_attr "length" "8") |
3526 | (set_attr "type" "vs")]) | |
9db1d521 | 3527 | |
db340c73 AK |
3528 | (define_insn "*setmem_long_and" |
3529 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3530 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
d876f5cd | 3531 | (unspec:BLK [(zero_extend:P (match_operand:QI 2 "setmem_operand" "Y")) |
db340c73 AK |
3532 | (subreg:P (match_dup 3) <modesize>)] |
3533 | UNSPEC_REPLICATE_BYTE)) | |
3534 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
3535 | (clobber (reg:CC CC_REGNUM))] | |
d876f5cd | 3536 | "(TARGET_64BIT || !TARGET_ZARCH)" |
db340c73 AK |
3537 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3538 | [(set_attr "length" "8") | |
3539 | (set_attr "type" "vs")]) | |
3540 | ||
da0dcab1 DV |
3541 | ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets |
3542 | ; of the SImode subregs. | |
3543 | ||
db340c73 | 3544 | (define_insn "*setmem_long_31z" |
9602b6a1 AK |
3545 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
3546 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
dd95128b | 3547 | (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y") |
da0dcab1 | 3548 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
9602b6a1 AK |
3549 | (use (match_operand:TI 1 "register_operand" "d")) |
3550 | (clobber (reg:CC CC_REGNUM))] | |
3551 | "!TARGET_64BIT && TARGET_ZARCH" | |
4989e88a AK |
3552 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3553 | [(set_attr "length" "8") | |
3554 | (set_attr "type" "vs")]) | |
9602b6a1 | 3555 | |
db340c73 AK |
3556 | (define_insn "*setmem_long_and_31z" |
3557 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3558 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
d876f5cd | 3559 | (unspec:BLK [(zero_extend:SI (match_operand:QI 2 "setmem_operand" "Y")) |
db340c73 AK |
3560 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
3561 | (use (match_operand:TI 1 "register_operand" "d")) | |
3562 | (clobber (reg:CC CC_REGNUM))] | |
d876f5cd | 3563 | "(!TARGET_64BIT && TARGET_ZARCH)" |
db340c73 AK |
3564 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3565 | [(set_attr "length" "8") | |
3566 | (set_attr "type" "vs")]) | |
3567 | ||
9db1d521 | 3568 | ; |
358b8f01 | 3569 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
3570 | ; |
3571 | ||
358b8f01 | 3572 | (define_expand "cmpmemsi" |
a41c6c53 UW |
3573 | [(set (match_operand:SI 0 "register_operand" "") |
3574 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
3575 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
3576 | (use (match_operand:SI 3 "general_operand" "")) | |
3577 | (use (match_operand:SI 4 "" ""))] | |
3578 | "" | |
367d32f3 AK |
3579 | { |
3580 | if (s390_expand_cmpmem (operands[0], operands[1], | |
3581 | operands[2], operands[3])) | |
3582 | DONE; | |
3583 | else | |
3584 | FAIL; | |
3585 | }) | |
9db1d521 | 3586 | |
a41c6c53 UW |
3587 | ; Compare a block that is up to 256 bytes in length. |
3588 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3589 | |
b9404c99 UW |
3590 | (define_expand "cmpmem_short" |
3591 | [(parallel | |
ae156f85 | 3592 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 3593 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3594 | (match_operand:BLK 1 "memory_operand" ""))) |
3595 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3596 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3597 | (clobber (match_dup 3))])] |
3598 | "" | |
3599 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3600 | |
b9404c99 | 3601 | (define_insn "*cmpmem_short" |
ae156f85 | 3602 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
3603 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
3604 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
3605 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3606 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3607 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3608 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3609 | "#" |
963fc8d0 | 3610 | [(set_attr "type" "cs") |
b5e0425c | 3611 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9db1d521 | 3612 | |
9bb86f41 | 3613 | (define_split |
ae156f85 | 3614 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3615 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3616 | (match_operand:BLK 1 "memory_operand" ""))) | |
3617 | (use (match_operand 2 "const_int_operand" "")) | |
3618 | (use (match_operand 3 "immediate_operand" "")) | |
3619 | (clobber (scratch))] | |
3620 | "reload_completed" | |
3621 | [(parallel | |
ae156f85 | 3622 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3623 | (use (match_dup 2))])] |
3624 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3625 | |
9bb86f41 | 3626 | (define_split |
ae156f85 | 3627 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3628 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3629 | (match_operand:BLK 1 "memory_operand" ""))) | |
3630 | (use (match_operand 2 "register_operand" "")) | |
3631 | (use (match_operand 3 "memory_operand" "")) | |
3632 | (clobber (scratch))] | |
3633 | "reload_completed" | |
3634 | [(parallel | |
3635 | [(unspec [(match_dup 2) (match_dup 3) | |
3636 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 3637 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3638 | (use (const_int 1))])] |
3639 | "") | |
3640 | ||
963fc8d0 AK |
3641 | (define_split |
3642 | [(set (reg:CCU CC_REGNUM) | |
3643 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3644 | (match_operand:BLK 1 "memory_operand" ""))) | |
3645 | (use (match_operand 2 "register_operand" "")) | |
3646 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3647 | (clobber (scratch))] | |
3648 | "TARGET_Z10 && reload_completed" | |
3649 | [(parallel | |
3650 | [(unspec [(match_dup 2) (const_int 0) | |
3651 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
3652 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
3653 | (use (const_int 1))])] | |
3654 | "operands[4] = gen_label_rtx ();") | |
3655 | ||
9bb86f41 | 3656 | (define_split |
ae156f85 | 3657 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3658 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3659 | (match_operand:BLK 1 "memory_operand" ""))) | |
3660 | (use (match_operand 2 "register_operand" "")) | |
3661 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3662 | (clobber (match_operand 3 "register_operand" ""))] | |
8cc6307c | 3663 | "reload_completed" |
9bb86f41 UW |
3664 | [(set (match_dup 3) (label_ref (match_dup 4))) |
3665 | (parallel | |
9381e3f1 | 3666 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 3667 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 3668 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3669 | (use (const_int 1))])] |
3670 | "operands[4] = gen_label_rtx ();") | |
3671 | ||
a41c6c53 | 3672 | ; Compare a block of arbitrary length. |
9db1d521 | 3673 | |
b9404c99 UW |
3674 | (define_expand "cmpmem_long" |
3675 | [(parallel | |
3676 | [(clobber (match_dup 2)) | |
3677 | (clobber (match_dup 3)) | |
ae156f85 | 3678 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 3679 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3680 | (match_operand:BLK 1 "memory_operand" ""))) |
3681 | (use (match_operand 2 "general_operand" "")) | |
3682 | (use (match_dup 3))])] | |
3683 | "" | |
3684 | { | |
ef4bddc2 RS |
3685 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3686 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3687 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3688 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3689 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3690 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3691 | rtx len0 = gen_lowpart (Pmode, reg0); |
3692 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3693 | ||
c41c1387 | 3694 | emit_clobber (reg0); |
b9404c99 UW |
3695 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3696 | emit_move_insn (len0, operands[2]); | |
3697 | ||
c41c1387 | 3698 | emit_clobber (reg1); |
b9404c99 UW |
3699 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3700 | emit_move_insn (len1, operands[2]); | |
3701 | ||
3702 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3703 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3704 | operands[2] = reg0; | |
3705 | operands[3] = reg1; | |
3706 | }) | |
3707 | ||
a1aed706 AS |
3708 | (define_insn "*cmpmem_long" |
3709 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3710 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3711 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3712 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3713 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3714 | (use (match_dup 2)) |
3715 | (use (match_dup 3))] | |
9602b6a1 | 3716 | "TARGET_64BIT || !TARGET_ZARCH" |
287ff198 | 3717 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3718 | [(set_attr "length" "8") |
3719 | (set_attr "type" "vs")]) | |
9db1d521 | 3720 | |
9602b6a1 AK |
3721 | (define_insn "*cmpmem_long_31z" |
3722 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3723 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3724 | (set (reg:CCU CC_REGNUM) | |
3725 | (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3726 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) | |
3727 | (use (match_dup 2)) | |
3728 | (use (match_dup 3))] | |
3729 | "!TARGET_64BIT && TARGET_ZARCH" | |
3730 | "clcle\t%0,%1,0\;jo\t.-4" | |
3731 | [(set_attr "op_type" "NN") | |
3732 | (set_attr "type" "vs") | |
3733 | (set_attr "length" "8")]) | |
3734 | ||
02887425 UW |
3735 | ; Convert CCUmode condition code to integer. |
3736 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3737 | |
02887425 | 3738 | (define_insn_and_split "cmpint" |
9db1d521 | 3739 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3740 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3741 | UNSPEC_STRCMPCC_TO_INT)) |
ae156f85 | 3742 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3743 | "" |
02887425 UW |
3744 | "#" |
3745 | "reload_completed" | |
3746 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3747 | (parallel | |
3748 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3749 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3750 | |
3751 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3752 | [(set (reg CC_REGNUM) |
02887425 | 3753 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3754 | UNSPEC_STRCMPCC_TO_INT) |
02887425 UW |
3755 | (const_int 0))) |
3756 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3757 | (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))] |
02887425 UW |
3758 | "s390_match_ccmode (insn, CCSmode)" |
3759 | "#" | |
3760 | "&& reload_completed" | |
3761 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3762 | (parallel | |
3763 | [(set (match_dup 2) (match_dup 3)) | |
3764 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3765 | { |
02887425 UW |
3766 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3767 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3768 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3769 | }) | |
9db1d521 | 3770 | |
02887425 | 3771 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3772 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3773 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3774 | UNSPEC_STRCMPCC_TO_INT))) |
ae156f85 | 3775 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3776 | "TARGET_ZARCH" |
02887425 UW |
3777 | "#" |
3778 | "&& reload_completed" | |
3779 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3780 | (parallel | |
3781 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3782 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3783 | |
3784 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3785 | [(set (reg CC_REGNUM) |
9381e3f1 | 3786 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3787 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3788 | UNSPEC_STRCMPCC_TO_INT) 0) |
02887425 UW |
3789 | (const_int 32)) (const_int 32)) |
3790 | (const_int 0))) | |
3791 | (set (match_operand:DI 0 "register_operand" "=d") | |
5a3fe9b6 | 3792 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))] |
9602b6a1 | 3793 | "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" |
02887425 UW |
3794 | "#" |
3795 | "&& reload_completed" | |
3796 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3797 | (parallel | |
3798 | [(set (match_dup 2) (match_dup 3)) | |
3799 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3800 | { |
02887425 UW |
3801 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3802 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3803 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3804 | }) | |
9db1d521 | 3805 | |
4023fb28 | 3806 | |
9db1d521 HP |
3807 | ;; |
3808 | ;;- Conversion instructions. | |
3809 | ;; | |
3810 | ||
6fa05db6 | 3811 | (define_insn "*sethighpartsi" |
d3632d41 | 3812 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3813 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3814 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3815 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3816 | "" |
d3632d41 | 3817 | "@ |
6fa05db6 AS |
3818 | icm\t%0,%2,%S1 |
3819 | icmy\t%0,%2,%S1" | |
9381e3f1 | 3820 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3821 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 3822 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
4023fb28 | 3823 | |
6fa05db6 | 3824 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3825 | [(set (match_operand:DI 0 "register_operand" "=d") |
3e4be43f | 3826 | (unspec:DI [(match_operand:BLK 1 "s_operand" "S") |
6fa05db6 | 3827 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) |
ae156f85 | 3828 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3829 | "TARGET_ZARCH" |
6fa05db6 | 3830 | "icmh\t%0,%2,%S1" |
729e750f WG |
3831 | [(set_attr "op_type" "RSY") |
3832 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3833 | |
6fa05db6 | 3834 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3835 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3836 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3837 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3838 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3839 | "!TARGET_ZARCH" |
d3632d41 | 3840 | "@ |
6fa05db6 AS |
3841 | icm\t%0,%2,%S1 |
3842 | icmy\t%0,%2,%S1" | |
9381e3f1 | 3843 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3844 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 WG |
3845 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
3846 | ||
1a2e356e RH |
3847 | ; |
3848 | ; extv instruction patterns | |
3849 | ; | |
3850 | ||
3851 | ; FIXME: This expander needs to be converted from DI to GPR as well | |
3852 | ; after resolving some issues with it. | |
3853 | ||
3854 | (define_expand "extzv" | |
3855 | [(parallel | |
3856 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3857 | (zero_extract:DI | |
3858 | (match_operand:DI 1 "register_operand" "d") | |
3859 | (match_operand 2 "const_int_operand" "") ; size | |
3860 | (match_operand 3 "const_int_operand" ""))) ; start | |
3861 | (clobber (reg:CC CC_REGNUM))])] | |
3862 | "TARGET_Z10" | |
3863 | { | |
0f6f72e8 DV |
3864 | if (! EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64)) |
3865 | FAIL; | |
1a2e356e RH |
3866 | /* Starting with zEC12 there is risbgn not clobbering CC. */ |
3867 | if (TARGET_ZEC12) | |
3868 | { | |
3869 | emit_move_insn (operands[0], | |
3870 | gen_rtx_ZERO_EXTRACT (DImode, | |
3871 | operands[1], | |
3872 | operands[2], | |
3873 | operands[3])); | |
3874 | DONE; | |
3875 | } | |
3876 | }) | |
3877 | ||
64c744b9 | 3878 | (define_insn "*extzv<mode><clobbercc_or_nocc>" |
1a2e356e RH |
3879 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3880 | (zero_extract:GPR | |
3881 | (match_operand:GPR 1 "register_operand" "d") | |
3882 | (match_operand 2 "const_int_operand" "") ; size | |
64c744b9 DV |
3883 | (match_operand 3 "const_int_operand" ""))) ; start |
3884 | ] | |
0f6f72e8 DV |
3885 | "<z10_or_zEC12_cond> |
3886 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), | |
3887 | GET_MODE_BITSIZE (<MODE>mode))" | |
64c744b9 DV |
3888 | "<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift |
3889 | [(set_attr "op_type" "RIE") | |
3890 | (set_attr "z10prop" "z10_super_E1")]) | |
1a2e356e | 3891 | |
64c744b9 DV |
3892 | ; 64 bit: (a & -16) | ((b >> 8) & 15) |
3893 | (define_insn "*extzvdi<clobbercc_or_nocc>_lshiftrt" | |
3894 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3895 | (match_operand 1 "const_int_operand" "") ; size | |
3896 | (match_operand 2 "const_int_operand" "")) ; start | |
3897 | (lshiftrt:DI (match_operand:DI 3 "register_operand" "d") | |
3898 | (match_operand:DI 4 "nonzero_shift_count_operand" "")))] | |
3899 | "<z10_or_zEC12_cond> | |
0f6f72e8 | 3900 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
64c744b9 DV |
3901 | && 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])" |
3902 | "<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4" | |
3903 | [(set_attr "op_type" "RIE") | |
3904 | (set_attr "z10prop" "z10_super_E1")]) | |
3905 | ||
3906 | ; 32 bit: (a & -16) | ((b >> 8) & 15) | |
3907 | (define_insn "*<risbg_n>_ior_and_sr_ze" | |
3908 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3909 | (ior:SI (and:SI | |
3910 | (match_operand:SI 1 "register_operand" "0") | |
3911 | (match_operand:SI 2 "const_int_operand" "")) | |
3912 | (subreg:SI | |
3913 | (zero_extract:DI | |
3914 | (match_operand:DI 3 "register_operand" "d") | |
3915 | (match_operand 4 "const_int_operand" "") ; size | |
3916 | (match_operand 5 "const_int_operand" "")) ; start | |
3917 | 4)))] | |
3918 | "<z10_or_zEC12_cond> | |
0f6f72e8 | 3919 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64) |
14653c37 | 3920 | && UINTVAL (operands[2]) == (HOST_WIDE_INT_M1U << UINTVAL (operands[4]))" |
64c744b9 DV |
3921 | "<risbg_n>\t%0,%3,64-%4,63,%4+%5" |
3922 | [(set_attr "op_type" "RIE") | |
3923 | (set_attr "z10prop" "z10_super_E1")]) | |
3924 | ||
3925 | ; ((int)foo >> 10) & 1; | |
3926 | (define_insn "*extract1bitdi<clobbercc_or_nocc>" | |
3927 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3928 | (ne:DI (zero_extract:DI | |
3929 | (match_operand:DI 1 "register_operand" "d") | |
3930 | (const_int 1) ; size | |
3931 | (match_operand 2 "const_int_operand" "")) ; start | |
3932 | (const_int 0)))] | |
0f6f72e8 DV |
3933 | "<z10_or_zEC12_cond> |
3934 | && EXTRACT_ARGS_IN_RANGE (1, INTVAL (operands[2]), 64)" | |
64c744b9 DV |
3935 | "<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift |
3936 | [(set_attr "op_type" "RIE") | |
3937 | (set_attr "z10prop" "z10_super_E1")]) | |
3938 | ||
3939 | (define_insn "*<risbg_n>_and_subregdi_rotr" | |
3940 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3941 | (and:DI (subreg:DI | |
3942 | (rotate:SINT (match_operand:SINT 1 "register_operand" "d") | |
3943 | (match_operand:SINT 2 "const_int_operand" "")) 0) | |
3944 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3945 | "<z10_or_zEC12_cond> | |
14653c37 JJ |
3946 | && (UINTVAL (operands[3]) |
3947 | < (HOST_WIDE_INT_1U << (UINTVAL (operands[2]) & 0x3f)))" | |
64c744b9 DV |
3948 | "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift |
3949 | [(set_attr "op_type" "RIE") | |
3950 | (set_attr "z10prop" "z10_super_E1")]) | |
3951 | ||
3952 | (define_insn "*<risbg_n>_and_subregdi_rotl" | |
3953 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3954 | (and:DI (subreg:DI | |
3955 | (rotate:SINT (match_operand:SINT 1 "register_operand" "d") | |
3956 | (match_operand:SINT 2 "const_int_operand" "")) 0) | |
3957 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3958 | "<z10_or_zEC12_cond> | |
14653c37 JJ |
3959 | && !(UINTVAL (operands[3]) |
3960 | & ((HOST_WIDE_INT_1U << (UINTVAL (operands[2]) & 0x3f)) - 1))" | |
64c744b9 DV |
3961 | "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift |
3962 | [(set_attr "op_type" "RIE") | |
3963 | (set_attr "z10prop" "z10_super_E1")]) | |
3964 | ||
3965 | (define_insn "*<risbg_n>_di_and_rot" | |
3966 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3967 | (and:DI (rotate:DI (match_operand:DI 1 "register_operand" "d") | |
3968 | (match_operand:DI 2 "const_int_operand" "")) | |
3969 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3970 | "<z10_or_zEC12_cond>" | |
3971 | "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift | |
1a2e356e RH |
3972 | [(set_attr "op_type" "RIE") |
3973 | (set_attr "z10prop" "z10_super_E1")]) | |
4023fb28 | 3974 | |
1a2e356e | 3975 | (define_insn_and_split "*pre_z10_extzv<mode>" |
6fa05db6 | 3976 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3e4be43f | 3977 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "S") |
1a2e356e | 3978 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3979 | (const_int 0))) |
ae156f85 | 3980 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3981 | "!TARGET_Z10" |
cc7ab9b7 UW |
3982 | "#" |
3983 | "&& reload_completed" | |
4023fb28 | 3984 | [(parallel |
6fa05db6 | 3985 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3986 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 3987 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 3988 | { |
6fa05db6 AS |
3989 | int bitsize = INTVAL (operands[2]); |
3990 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
14653c37 JJ |
3991 | unsigned HOST_WIDE_INT mask |
3992 | = ((HOST_WIDE_INT_1U << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
6fa05db6 AS |
3993 | |
3994 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3995 | set_mem_size (operands[1], size); |
2542ef05 | 3996 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 | 3997 | operands[3] = GEN_INT (mask); |
b628bd8e | 3998 | }) |
4023fb28 | 3999 | |
1a2e356e | 4000 | (define_insn_and_split "*pre_z10_extv<mode>" |
6fa05db6 | 4001 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3e4be43f | 4002 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "S") |
1a2e356e | 4003 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 4004 | (const_int 0))) |
ae156f85 | 4005 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 4006 | "" |
cc7ab9b7 UW |
4007 | "#" |
4008 | "&& reload_completed" | |
4023fb28 | 4009 | [(parallel |
6fa05db6 | 4010 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 4011 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
4012 | (parallel |
4013 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
4014 | (clobber (reg:CC CC_REGNUM))])] | |
4015 | { | |
4016 | int bitsize = INTVAL (operands[2]); | |
4017 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
14653c37 JJ |
4018 | unsigned HOST_WIDE_INT mask |
4019 | = ((HOST_WIDE_INT_1U << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
6fa05db6 AS |
4020 | |
4021 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4022 | set_mem_size (operands[1], size); |
2542ef05 | 4023 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 AS |
4024 | operands[3] = GEN_INT (mask); |
4025 | }) | |
4026 | ||
4027 | ; | |
4028 | ; insv instruction patterns | |
4029 | ; | |
4030 | ||
4031 | (define_expand "insv" | |
4032 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
4033 | (match_operand 1 "const_int_operand" "") | |
4034 | (match_operand 2 "const_int_operand" "")) | |
4035 | (match_operand 3 "general_operand" ""))] | |
4036 | "" | |
4023fb28 | 4037 | { |
6fa05db6 AS |
4038 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
4039 | DONE; | |
4040 | FAIL; | |
b628bd8e | 4041 | }) |
4023fb28 | 4042 | |
2542ef05 RH |
4043 | |
4044 | ; The normal RTL expansion will never generate a zero_extract where | |
4045 | ; the location operand isn't word mode. However, we do this in the | |
4046 | ; back-end when generating atomic operations. See s390_two_part_insv. | |
64c744b9 | 4047 | (define_insn "*insv<mode><clobbercc_or_nocc>" |
22ac2c2f | 4048 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") |
2542ef05 RH |
4049 | (match_operand 1 "const_int_operand" "I") ; size |
4050 | (match_operand 2 "const_int_operand" "I")) ; pos | |
22ac2c2f | 4051 | (match_operand:GPR 3 "nonimmediate_operand" "d"))] |
64c744b9 | 4052 | "<z10_or_zEC12_cond> |
0f6f72e8 DV |
4053 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), |
4054 | GET_MODE_BITSIZE (<MODE>mode)) | |
2542ef05 | 4055 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
64c744b9 | 4056 | "<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1" |
9381e3f1 WG |
4057 | [(set_attr "op_type" "RIE") |
4058 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 4059 | |
22ac2c2f AK |
4060 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest |
4061 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
64c744b9 DV |
4062 | (define_insn "*insv<mode><clobbercc_or_nocc>_noshift" |
4063 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d") | |
4064 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d,0") | |
75ca1b39 | 4065 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
64c744b9 | 4066 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0,d") |
75ca1b39 | 4067 | (match_operand:GPR 4 "const_int_operand" ""))))] |
64c744b9 DV |
4068 | "<z10_or_zEC12_cond> && INTVAL (operands[2]) == ~INTVAL (operands[4])" |
4069 | "@ | |
4070 | <risbg_n>\t%0,%1,%<bfstart>2,%<bfend>2,0 | |
4071 | <risbg_n>\t%0,%3,%<bfstart>4,%<bfend>4,0" | |
4072 | [(set_attr "op_type" "RIE") | |
4073 | (set_attr "z10prop" "z10_super_E1")]) | |
22ac2c2f | 4074 | |
64c744b9 DV |
4075 | (define_insn "*insv_z10_noshift_cc" |
4076 | [(set (reg CC_REGNUM) | |
4077 | (compare | |
4078 | (ior:DI | |
4079 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") | |
4080 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4081 | (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") | |
4082 | (match_operand:DI 4 "const_int_operand" ""))) | |
4083 | (const_int 0))) | |
4084 | (set (match_operand:DI 0 "nonimmediate_operand" "=d,d") | |
4085 | (ior:DI (and:DI (match_dup 1) (match_dup 2)) | |
4086 | (and:DI (match_dup 3) (match_dup 4))))] | |
4087 | "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) | |
4088 | && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
4089 | "@ | |
4090 | risbg\t%0,%1,%s2,%e2,0 | |
4091 | risbg\t%0,%3,%s4,%e4,0" | |
4092 | [(set_attr "op_type" "RIE") | |
4093 | (set_attr "z10prop" "z10_super_E1")]) | |
4094 | ||
4095 | (define_insn "*insv_z10_noshift_cconly" | |
4096 | [(set | |
4097 | (reg CC_REGNUM) | |
4098 | (compare | |
4099 | (ior:DI | |
4100 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") | |
4101 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4102 | (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") | |
4103 | (match_operand:DI 4 "const_int_operand" ""))) | |
4104 | (const_int 0))) | |
4105 | (clobber (match_scratch:DI 0 "=d,d"))] | |
4106 | "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) | |
4107 | && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
4108 | "@ | |
4109 | risbg\t%0,%1,%s2,%e2,0 | |
4110 | risbg\t%0,%3,%s4,%e4,0" | |
9381e3f1 WG |
4111 | [(set_attr "op_type" "RIE") |
4112 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 4113 | |
3d44ff99 AK |
4114 | ; Implement appending Y on the left of S bits of X |
4115 | ; x = (y << s) | (x & ((1 << s) - 1)) | |
64c744b9 | 4116 | (define_insn "*insv<mode><clobbercc_or_nocc>_appendbitsleft" |
3d44ff99 AK |
4117 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4118 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") | |
4119 | (match_operand:GPR 2 "immediate_operand" "")) | |
4120 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") | |
4121 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
64c744b9 | 4122 | "<z10_or_zEC12_cond> |
14653c37 | 4123 | && UINTVAL (operands[2]) == (HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1" |
64c744b9 | 4124 | "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4" |
3d44ff99 AK |
4125 | [(set_attr "op_type" "RIE") |
4126 | (set_attr "z10prop" "z10_super_E1")]) | |
4127 | ||
64c744b9 DV |
4128 | ; a = ((i32)a & -16777216) | (((ui32)b) >> 8) |
4129 | (define_insn "*<risbg_n>_<mode>_ior_and_lshiftrt" | |
4130 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4131 | (ior:GPR (and:GPR | |
4132 | (match_operand:GPR 1 "register_operand" "0") | |
4133 | (match_operand:GPR 2 "const_int_operand" "")) | |
4134 | (lshiftrt:GPR | |
4135 | (match_operand:GPR 3 "register_operand" "d") | |
4136 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
4137 | "<z10_or_zEC12_cond> && UINTVAL (operands[2]) | |
14653c37 JJ |
4138 | == (HOST_WIDE_INT_M1U |
4139 | << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))" | |
64c744b9 DV |
4140 | "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4" |
4141 | [(set_attr "op_type" "RIE") | |
4142 | (set_attr "z10prop" "z10_super_E1")]) | |
4143 | ||
4144 | ; (ui32)(((ui64)x) >> 48) | ((i32)y & -65536); | |
4145 | (define_insn "*<risbg_n>_sidi_ior_and_lshiftrt" | |
4146 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4147 | (ior:SI (and:SI | |
4148 | (match_operand:SI 1 "register_operand" "0") | |
4149 | (match_operand:SI 2 "const_int_operand" "")) | |
4150 | (subreg:SI | |
4151 | (lshiftrt:DI | |
4152 | (match_operand:DI 3 "register_operand" "d") | |
4153 | (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))] | |
4154 | "<z10_or_zEC12_cond> | |
14653c37 | 4155 | && UINTVAL (operands[2]) == ~(HOST_WIDE_INT_M1U >> UINTVAL (operands[4]))" |
64c744b9 DV |
4156 | "<risbg_n>\t%0,%3,%4,63,64-%4" |
4157 | [(set_attr "op_type" "RIE") | |
4158 | (set_attr "z10prop" "z10_super_E1")]) | |
4159 | ||
4160 | ; (ui32)(((ui64)x) >> 12) & -4 | |
4161 | (define_insn "*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>" | |
4162 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4163 | (and:SI | |
4164 | (subreg:SI (lshiftrt:DI | |
4165 | (match_operand:DI 1 "register_operand" "d") | |
4166 | (match_operand:DI 2 "nonzero_shift_count_operand" "")) 4) | |
4167 | (match_operand:SI 3 "contiguous_bitmask_nowrap_operand" "")))] | |
4168 | "<z10_or_zEC12_cond>" | |
4169 | "<risbg_n>\t%0,%1,%t3,128+%f3,64-%2" | |
3d44ff99 AK |
4170 | [(set_attr "op_type" "RIE") |
4171 | (set_attr "z10prop" "z10_super_E1")]) | |
4172 | ||
4173 | ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting | |
4174 | ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1)) | |
4175 | ; -> z = y >> d; z = risbg; | |
4176 | ||
4177 | (define_split | |
4178 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
4179 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
4180 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4181 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
4182 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
4183 | "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 4184 | [(set (match_dup 6) |
3d44ff99 AK |
4185 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
4186 | (set (match_dup 0) | |
1d11f7ce | 4187 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
4188 | (ashift:GPR (match_dup 3) (match_dup 4))))] |
4189 | { | |
14653c37 | 4190 | operands[5] = GEN_INT ((HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1); |
3168e073 | 4191 | if (reg_overlap_mentioned_p (operands[0], operands[3])) |
1d11f7ce AK |
4192 | { |
4193 | if (!can_create_pseudo_p ()) | |
4194 | FAIL; | |
4195 | operands[6] = gen_reg_rtx (<MODE>mode); | |
4196 | } | |
4197 | else | |
4198 | operands[6] = operands[0]; | |
3d44ff99 AK |
4199 | }) |
4200 | ||
4201 | (define_split | |
4202 | [(parallel | |
4203 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
4204 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
4205 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4206 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
4207 | (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) | |
4208 | (clobber (reg:CC CC_REGNUM))])] | |
4209 | "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 4210 | [(set (match_dup 6) |
3d44ff99 AK |
4211 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
4212 | (parallel | |
4213 | [(set (match_dup 0) | |
1d11f7ce | 4214 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
4215 | (ashift:GPR (match_dup 3) (match_dup 4)))) |
4216 | (clobber (reg:CC CC_REGNUM))])] | |
4217 | { | |
14653c37 | 4218 | operands[5] = GEN_INT ((HOST_WIDE_INT_1U << UINTVAL (operands[4])) - 1); |
3168e073 | 4219 | if (reg_overlap_mentioned_p (operands[0], operands[3])) |
1d11f7ce AK |
4220 | { |
4221 | if (!can_create_pseudo_p ()) | |
4222 | FAIL; | |
4223 | operands[6] = gen_reg_rtx (<MODE>mode); | |
4224 | } | |
4225 | else | |
4226 | operands[6] = operands[0]; | |
3d44ff99 AK |
4227 | }) |
4228 | ||
50dc4eed | 4229 | ; rosbg, rxsbg |
571e408a | 4230 | (define_insn "*r<noxa>sbg_<mode>_noshift" |
963fc8d0 | 4231 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
571e408a RH |
4232 | (IXOR:GPR |
4233 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4234 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
4235 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
963fc8d0 | 4236 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 | 4237 | "TARGET_Z10" |
571e408a RH |
4238 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0" |
4239 | [(set_attr "op_type" "RIE")]) | |
4240 | ||
50dc4eed | 4241 | ; rosbg, rxsbg |
571e408a RH |
4242 | (define_insn "*r<noxa>sbg_di_rotl" |
4243 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") | |
4244 | (IXOR:DI | |
4245 | (and:DI | |
4246 | (rotate:DI | |
4247 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
4248 | (match_operand:DI 3 "const_int_operand" "")) | |
4249 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4250 | (match_operand:DI 4 "nonimmediate_operand" "0"))) | |
4251 | (clobber (reg:CC CC_REGNUM))] | |
4252 | "TARGET_Z10" | |
8c21b0d1 | 4253 | "r<noxa>sbg\t%0,%1,%s2,%e2,%b3" |
571e408a RH |
4254 | [(set_attr "op_type" "RIE")]) |
4255 | ||
50dc4eed | 4256 | ; rosbg, rxsbg |
f3d90045 | 4257 | (define_insn "*r<noxa>sbg_<mode>_srl_bitmask" |
571e408a RH |
4258 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4259 | (IXOR:GPR | |
4260 | (and:GPR | |
4261 | (lshiftrt:GPR | |
4262 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4263 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 4264 | (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) |
571e408a RH |
4265 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) |
4266 | (clobber (reg:CC CC_REGNUM))] | |
4267 | "TARGET_Z10 | |
4268 | && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), | |
4269 | INTVAL (operands[2]))" | |
b9789752 | 4270 | { |
290dfd9b JJ |
4271 | operands[3] = GEN_INT (64 - INTVAL (operands[3])); |
4272 | return "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3"; | |
b9789752 | 4273 | } |
571e408a RH |
4274 | [(set_attr "op_type" "RIE")]) |
4275 | ||
50dc4eed | 4276 | ; rosbg, rxsbg |
f3d90045 | 4277 | (define_insn "*r<noxa>sbg_<mode>_sll_bitmask" |
571e408a RH |
4278 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4279 | (IXOR:GPR | |
4280 | (and:GPR | |
4281 | (ashift:GPR | |
4282 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4283 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 4284 | (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) |
571e408a RH |
4285 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) |
4286 | (clobber (reg:CC CC_REGNUM))] | |
4287 | "TARGET_Z10 | |
4288 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]), | |
4289 | INTVAL (operands[2]))" | |
4290 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3" | |
963fc8d0 AK |
4291 | [(set_attr "op_type" "RIE")]) |
4292 | ||
f3d90045 DV |
4293 | ;; unsigned {int,long} a, b |
4294 | ;; a = a | (b << const_int) | |
4295 | ;; a = a ^ (b << const_int) | |
50dc4eed | 4296 | ; rosbg, rxsbg |
f3d90045 DV |
4297 | (define_insn "*r<noxa>sbg_<mode>_sll" |
4298 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
4299 | (IXOR:GPR | |
4300 | (ashift:GPR | |
4301 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4302 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4303 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
4304 | (clobber (reg:CC CC_REGNUM))] | |
4305 | "TARGET_Z10" | |
b9789752 | 4306 | { |
290dfd9b JJ |
4307 | operands[3] = GEN_INT (63 - INTVAL (operands[2])); |
4308 | return "r<noxa>sbg\t%0,%1,<bitoff>,%3,%2"; | |
b9789752 | 4309 | } |
f3d90045 DV |
4310 | [(set_attr "op_type" "RIE")]) |
4311 | ||
4312 | ;; unsigned {int,long} a, b | |
4313 | ;; a = a | (b >> const_int) | |
4314 | ;; a = a ^ (b >> const_int) | |
50dc4eed | 4315 | ; rosbg, rxsbg |
f3d90045 DV |
4316 | (define_insn "*r<noxa>sbg_<mode>_srl" |
4317 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
4318 | (IXOR:GPR | |
4319 | (lshiftrt:GPR | |
4320 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4321 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4322 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
4323 | (clobber (reg:CC CC_REGNUM))] | |
4324 | "TARGET_Z10" | |
b9789752 | 4325 | { |
290dfd9b JJ |
4326 | operands[3] = GEN_INT (64 - INTVAL (operands[2])); |
4327 | operands[2] = GEN_INT (<bitoff_plus> INTVAL (operands[2])); | |
4328 | return "r<noxa>sbg\t%0,%1,%2,63,%3"; | |
b9789752 IL |
4329 | } |
4330 | [(set_attr "op_type" "RIE")]) | |
4331 | ||
4332 | ; rosbg, rxsbg | |
4333 | (define_insn "*r<noxa>sbg_sidi_srl" | |
4334 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") | |
4335 | (IXOR:SI | |
4336 | (subreg:SI | |
4337 | (zero_extract:DI | |
4338 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
4339 | (const_int 32) | |
4340 | (match_operand:DI 2 "immediate_operand" "")) | |
4341 | 4) | |
4342 | (match_operand:SI 3 "nonimmediate_operand" "0"))) | |
4343 | (clobber (reg:CC CC_REGNUM))] | |
4344 | "TARGET_Z10" | |
4345 | { | |
290dfd9b JJ |
4346 | operands[2] = GEN_INT (32 + INTVAL (operands[2])); |
4347 | return "r<noxa>sbg\t%0,%1,32,63,%2"; | |
b9789752 | 4348 | } |
f3d90045 DV |
4349 | [(set_attr "op_type" "RIE")]) |
4350 | ||
5bb33936 RH |
4351 | ;; These two are generated by combine for s.bf &= val. |
4352 | ;; ??? For bitfields smaller than 32-bits, we wind up with SImode | |
4353 | ;; shifts and ands, which results in some truly awful patterns | |
4354 | ;; including subregs of operations. Rather unnecessisarily, IMO. | |
4355 | ;; Instead of | |
4356 | ;; | |
4357 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4358 | ;; (const_int 24 [0x18]) | |
4359 | ;; (const_int 0 [0])) | |
4360 | ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4361 | ;; (const_int 40 [0x28])) 4) | |
4362 | ;; (reg:SI 4 %r4 [ y+4 ])) 0)) | |
4363 | ;; | |
4364 | ;; we should instead generate | |
4365 | ;; | |
4366 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4367 | ;; (const_int 24 [0x18]) | |
4368 | ;; (const_int 0 [0])) | |
4369 | ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4370 | ;; (const_int 40 [0x28])) | |
4371 | ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0))) | |
4372 | ;; | |
4373 | ;; by noticing that we can push down the outer paradoxical subreg | |
4374 | ;; into the operation. | |
4375 | ||
4376 | (define_insn "*insv_rnsbg_noshift" | |
4377 | [(set (zero_extract:DI | |
4378 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4379 | (match_operand 1 "const_int_operand" "") | |
4380 | (match_operand 2 "const_int_operand" "")) | |
4381 | (and:DI | |
4382 | (match_dup 0) | |
4383 | (match_operand:DI 3 "nonimmediate_operand" "d"))) | |
4384 | (clobber (reg:CC CC_REGNUM))] | |
4385 | "TARGET_Z10 | |
0f6f72e8 | 4386 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
5bb33936 RH |
4387 | && INTVAL (operands[1]) + INTVAL (operands[2]) == 64" |
4388 | "rnsbg\t%0,%3,%2,63,0" | |
4389 | [(set_attr "op_type" "RIE")]) | |
4390 | ||
4391 | (define_insn "*insv_rnsbg_srl" | |
4392 | [(set (zero_extract:DI | |
4393 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4394 | (match_operand 1 "const_int_operand" "") | |
4395 | (match_operand 2 "const_int_operand" "")) | |
4396 | (and:DI | |
4397 | (lshiftrt:DI | |
4398 | (match_dup 0) | |
4399 | (match_operand 3 "const_int_operand" "")) | |
4400 | (match_operand:DI 4 "nonimmediate_operand" "d"))) | |
4401 | (clobber (reg:CC CC_REGNUM))] | |
4402 | "TARGET_Z10 | |
0f6f72e8 | 4403 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
5bb33936 RH |
4404 | && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])" |
4405 | "rnsbg\t%0,%4,%2,%2+%1-1,%3" | |
4406 | [(set_attr "op_type" "RIE")]) | |
4407 | ||
6fa05db6 | 4408 | (define_insn "*insv<mode>_mem_reg" |
9602b6a1 | 4409 | [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") |
6fa05db6 AS |
4410 | (match_operand 1 "const_int_operand" "n,n") |
4411 | (const_int 0)) | |
9602b6a1 | 4412 | (match_operand:W 2 "register_operand" "d,d"))] |
0f6f72e8 DV |
4413 | "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) |
4414 | && INTVAL (operands[1]) > 0 | |
6fa05db6 AS |
4415 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) |
4416 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4417 | { | |
4418 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4419 | ||
14653c37 | 4420 | operands[1] = GEN_INT ((HOST_WIDE_INT_1U << size) - 1); |
9381e3f1 | 4421 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
4422 | : "stcmy\t%2,%1,%S0"; |
4423 | } | |
9381e3f1 | 4424 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 4425 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 4426 | (set_attr "z10prop" "z10_super,z10_super")]) |
6fa05db6 AS |
4427 | |
4428 | (define_insn "*insvdi_mem_reghigh" | |
3e4be43f | 4429 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S") |
6fa05db6 AS |
4430 | (match_operand 1 "const_int_operand" "n") |
4431 | (const_int 0)) | |
4432 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
4433 | (const_int 32)))] | |
9602b6a1 | 4434 | "TARGET_ZARCH |
0f6f72e8 | 4435 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) |
6fa05db6 AS |
4436 | && INTVAL (operands[1]) > 0 |
4437 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
4438 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4439 | { | |
4440 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4441 | ||
14653c37 | 4442 | operands[1] = GEN_INT ((HOST_WIDE_INT_1U << size) - 1); |
6fa05db6 AS |
4443 | return "stcmh\t%2,%1,%S0"; |
4444 | } | |
9381e3f1 WG |
4445 | [(set_attr "op_type" "RSY") |
4446 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 | 4447 | |
9602b6a1 AK |
4448 | (define_insn "*insvdi_reg_imm" |
4449 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4450 | (const_int 16) | |
4451 | (match_operand 1 "const_int_operand" "n")) | |
4452 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6fa05db6 | 4453 | "TARGET_ZARCH |
0f6f72e8 | 4454 | && EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64) |
6fa05db6 AS |
4455 | && INTVAL (operands[1]) >= 0 |
4456 | && INTVAL (operands[1]) < BITS_PER_WORD | |
4457 | && INTVAL (operands[1]) % 16 == 0" | |
4458 | { | |
4459 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
4460 | { | |
4461 | case 64: return "iihh\t%0,%x2"; break; | |
4462 | case 48: return "iihl\t%0,%x2"; break; | |
4463 | case 32: return "iilh\t%0,%x2"; break; | |
4464 | case 16: return "iill\t%0,%x2"; break; | |
4465 | default: gcc_unreachable(); | |
4466 | } | |
4467 | } | |
9381e3f1 WG |
4468 | [(set_attr "op_type" "RI") |
4469 | (set_attr "z10prop" "z10_super_E1")]) | |
4470 | ||
9fec758d WG |
4471 | ; Update the left-most 32 bit of a DI. |
4472 | (define_insn "*insv_h_di_reg_extimm" | |
4473 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4474 | (const_int 32) | |
4475 | (const_int 0)) | |
4476 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4477 | "TARGET_EXTIMM" | |
4478 | "iihf\t%0,%o1" | |
4479 | [(set_attr "op_type" "RIL") | |
4480 | (set_attr "z10prop" "z10_fwd_E1")]) | |
6fa05db6 | 4481 | |
d378b983 RH |
4482 | ; Update the right-most 32 bit of a DI. |
4483 | (define_insn "*insv_l_di_reg_extimm" | |
4484 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4485 | (const_int 32) | |
4486 | (const_int 32)) | |
4487 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4488 | "TARGET_EXTIMM" | |
4489 | "iilf\t%0,%o1" | |
9381e3f1 | 4490 | [(set_attr "op_type" "RIL") |
9fec758d | 4491 | (set_attr "z10prop" "z10_fwd_A1")]) |
6fa05db6 | 4492 | |
9db1d521 HP |
4493 | ; |
4494 | ; extendsidi2 instruction pattern(s). | |
4495 | ; | |
4496 | ||
4023fb28 UW |
4497 | (define_expand "extendsidi2" |
4498 | [(set (match_operand:DI 0 "register_operand" "") | |
4499 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4500 | "" | |
4023fb28 | 4501 | { |
9602b6a1 | 4502 | if (!TARGET_ZARCH) |
4023fb28 | 4503 | { |
c41c1387 | 4504 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4505 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
4506 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
4507 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
4508 | DONE; |
4509 | } | |
ec24698e | 4510 | }) |
4023fb28 UW |
4511 | |
4512 | (define_insn "*extendsidi2" | |
963fc8d0 | 4513 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4514 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] |
9602b6a1 | 4515 | "TARGET_ZARCH" |
9db1d521 | 4516 | "@ |
d40c829f | 4517 | lgfr\t%0,%1 |
963fc8d0 AK |
4518 | lgf\t%0,%1 |
4519 | lgfrl\t%0,%1" | |
4520 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4521 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4522 | (set_attr "cpu_facility" "*,*,z10") |
14cfceb7 IL |
4523 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1") |
4524 | (set_attr "relative_long" "*,*,yes")]) | |
9db1d521 | 4525 | |
9db1d521 | 4526 | ; |
56477c21 | 4527 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4528 | ; |
4529 | ||
56477c21 AS |
4530 | (define_expand "extend<HQI:mode><DSI:mode>2" |
4531 | [(set (match_operand:DSI 0 "register_operand" "") | |
4532 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 4533 | "" |
4023fb28 | 4534 | { |
9602b6a1 | 4535 | if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) |
4023fb28 UW |
4536 | { |
4537 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 4538 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
4539 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
4540 | DONE; | |
4541 | } | |
ec24698e | 4542 | else if (!TARGET_EXTIMM) |
4023fb28 | 4543 | { |
2542ef05 | 4544 | rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>); |
56477c21 AS |
4545 | |
4546 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
4547 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
4548 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
4549 | DONE; |
4550 | } | |
ec24698e UW |
4551 | }) |
4552 | ||
56477c21 AS |
4553 | ; |
4554 | ; extendhidi2 instruction pattern(s). | |
4555 | ; | |
4556 | ||
ec24698e | 4557 | (define_insn "*extendhidi2_extimm" |
963fc8d0 | 4558 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4559 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))] |
9602b6a1 | 4560 | "TARGET_ZARCH && TARGET_EXTIMM" |
ec24698e UW |
4561 | "@ |
4562 | lghr\t%0,%1 | |
963fc8d0 AK |
4563 | lgh\t%0,%1 |
4564 | lghrl\t%0,%1" | |
4565 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4566 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4567 | (set_attr "cpu_facility" "extimm,extimm,z10") |
14cfceb7 IL |
4568 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1") |
4569 | (set_attr "relative_long" "*,*,yes")]) | |
4023fb28 UW |
4570 | |
4571 | (define_insn "*extendhidi2" | |
9db1d521 | 4572 | [(set (match_operand:DI 0 "register_operand" "=d") |
3e4be43f | 4573 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))] |
9602b6a1 | 4574 | "TARGET_ZARCH" |
d40c829f | 4575 | "lgh\t%0,%1" |
9381e3f1 WG |
4576 | [(set_attr "op_type" "RXY") |
4577 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 4578 | |
9db1d521 | 4579 | ; |
56477c21 | 4580 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
4581 | ; |
4582 | ||
ec24698e | 4583 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
4584 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4585 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
4586 | "TARGET_EXTIMM" |
4587 | "@ | |
4588 | lhr\t%0,%1 | |
4589 | lh\t%0,%1 | |
963fc8d0 AK |
4590 | lhy\t%0,%1 |
4591 | lhrl\t%0,%1" | |
4592 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
4593 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 | 4594 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
14cfceb7 IL |
4595 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1") |
4596 | (set_attr "relative_long" "*,*,*,yes")]) | |
9db1d521 | 4597 | |
4023fb28 | 4598 | (define_insn "*extendhisi2" |
d3632d41 UW |
4599 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4600 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 4601 | "!TARGET_EXTIMM" |
d3632d41 | 4602 | "@ |
d40c829f UW |
4603 | lh\t%0,%1 |
4604 | lhy\t%0,%1" | |
9381e3f1 | 4605 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 4606 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 4607 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 | 4608 | |
56477c21 AS |
4609 | ; |
4610 | ; extendqi(si|di)2 instruction pattern(s). | |
4611 | ; | |
4612 | ||
43a09b63 | 4613 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
4614 | (define_insn "*extendqi<mode>2_extimm" |
4615 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3e4be43f | 4616 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))] |
ec24698e UW |
4617 | "TARGET_EXTIMM" |
4618 | "@ | |
56477c21 AS |
4619 | l<g>br\t%0,%1 |
4620 | l<g>b\t%0,%1" | |
9381e3f1 WG |
4621 | [(set_attr "op_type" "RRE,RXY") |
4622 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 4623 | |
43a09b63 | 4624 | ; lb, lgb |
56477c21 AS |
4625 | (define_insn "*extendqi<mode>2" |
4626 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 4627 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))] |
56477c21 AS |
4628 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
4629 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
4630 | [(set_attr "op_type" "RXY") |
4631 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 4632 | |
56477c21 AS |
4633 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
4634 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4635 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 4636 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 4637 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
4638 | "#" |
4639 | "&& reload_completed" | |
4023fb28 | 4640 | [(parallel |
56477c21 | 4641 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 4642 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 4643 | (parallel |
56477c21 | 4644 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 4645 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
4646 | { |
4647 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4648 | set_mem_size (operands[1], GET_MODE_SIZE (QImode)); |
2542ef05 | 4649 | operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT); |
6fa05db6 | 4650 | }) |
9db1d521 | 4651 | |
9db1d521 HP |
4652 | ; |
4653 | ; zero_extendsidi2 instruction pattern(s). | |
4654 | ; | |
4655 | ||
4023fb28 UW |
4656 | (define_expand "zero_extendsidi2" |
4657 | [(set (match_operand:DI 0 "register_operand" "") | |
4658 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4659 | "" | |
4023fb28 | 4660 | { |
9602b6a1 | 4661 | if (!TARGET_ZARCH) |
4023fb28 | 4662 | { |
c41c1387 | 4663 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4664 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
4665 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
4666 | DONE; |
4667 | } | |
ec24698e | 4668 | }) |
4023fb28 UW |
4669 | |
4670 | (define_insn "*zero_extendsidi2" | |
963fc8d0 | 4671 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4672 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] |
9602b6a1 | 4673 | "TARGET_ZARCH" |
9db1d521 | 4674 | "@ |
d40c829f | 4675 | llgfr\t%0,%1 |
963fc8d0 AK |
4676 | llgf\t%0,%1 |
4677 | llgfrl\t%0,%1" | |
4678 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4679 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4680 | (set_attr "cpu_facility" "*,*,z10") |
14cfceb7 IL |
4681 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3") |
4682 | (set_attr "relative_long" "*,*,yes")]) | |
9db1d521 | 4683 | |
288e517f AK |
4684 | ; |
4685 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
4686 | ; | |
4687 | ||
d6083c7d UW |
4688 | (define_insn "*llgt_sidi" |
4689 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 4690 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) |
d6083c7d | 4691 | (const_int 2147483647)))] |
9602b6a1 | 4692 | "TARGET_ZARCH" |
d6083c7d | 4693 | "llgt\t%0,%1" |
9381e3f1 WG |
4694 | [(set_attr "op_type" "RXE") |
4695 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
4696 | |
4697 | (define_insn_and_split "*llgt_sidi_split" | |
4698 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 4699 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) |
d6083c7d | 4700 | (const_int 2147483647))) |
ae156f85 | 4701 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4702 | "TARGET_ZARCH" |
d6083c7d UW |
4703 | "#" |
4704 | "&& reload_completed" | |
4705 | [(set (match_dup 0) | |
4706 | (and:DI (subreg:DI (match_dup 1) 0) | |
4707 | (const_int 2147483647)))] | |
4708 | "") | |
4709 | ||
288e517f AK |
4710 | (define_insn "*llgt_sisi" |
4711 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 4712 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T") |
288e517f | 4713 | (const_int 2147483647)))] |
c4d50129 | 4714 | "TARGET_ZARCH" |
288e517f AK |
4715 | "@ |
4716 | llgtr\t%0,%1 | |
4717 | llgt\t%0,%1" | |
9381e3f1 WG |
4718 | [(set_attr "op_type" "RRE,RXE") |
4719 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4720 | |
288e517f AK |
4721 | (define_insn "*llgt_didi" |
4722 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4723 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
4724 | (const_int 2147483647)))] | |
9602b6a1 | 4725 | "TARGET_ZARCH" |
288e517f AK |
4726 | "@ |
4727 | llgtr\t%0,%1 | |
4728 | llgt\t%0,%N1" | |
9381e3f1 WG |
4729 | [(set_attr "op_type" "RRE,RXE") |
4730 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4731 | |
f19a9af7 | 4732 | (define_split |
9602b6a1 AK |
4733 | [(set (match_operand:DSI 0 "register_operand" "") |
4734 | (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") | |
f6ee577c | 4735 | (const_int 2147483647))) |
ae156f85 | 4736 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 4737 | "TARGET_ZARCH && reload_completed" |
288e517f | 4738 | [(set (match_dup 0) |
9602b6a1 | 4739 | (and:DSI (match_dup 1) |
f6ee577c | 4740 | (const_int 2147483647)))] |
288e517f AK |
4741 | "") |
4742 | ||
9db1d521 | 4743 | ; |
56477c21 | 4744 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4745 | ; |
4746 | ||
56477c21 AS |
4747 | (define_expand "zero_extend<mode>di2" |
4748 | [(set (match_operand:DI 0 "register_operand" "") | |
4749 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4750 | "" | |
4751 | { | |
9602b6a1 | 4752 | if (!TARGET_ZARCH) |
56477c21 AS |
4753 | { |
4754 | rtx tmp = gen_reg_rtx (SImode); | |
4755 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
4756 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
4757 | DONE; | |
4758 | } | |
4759 | else if (!TARGET_EXTIMM) | |
4760 | { | |
2542ef05 | 4761 | rtx bitcount = GEN_INT (64 - <HQI:bitsize>); |
56477c21 AS |
4762 | operands[1] = gen_lowpart (DImode, operands[1]); |
4763 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
4764 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
4765 | DONE; | |
4766 | } | |
4767 | }) | |
4768 | ||
f6ee577c | 4769 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 4770 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 4771 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 4772 | "" |
4023fb28 | 4773 | { |
ec24698e UW |
4774 | if (!TARGET_EXTIMM) |
4775 | { | |
4776 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 4777 | emit_insn (gen_andsi3 (operands[0], operands[1], |
2542ef05 | 4778 | GEN_INT ((1 << <HQI:bitsize>) - 1))); |
ec24698e | 4779 | DONE; |
56477c21 | 4780 | } |
ec24698e UW |
4781 | }) |
4782 | ||
963fc8d0 AK |
4783 | ; llhrl, llghrl |
4784 | (define_insn "*zero_extendhi<mode>2_z10" | |
4785 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
3e4be43f | 4786 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))] |
963fc8d0 AK |
4787 | "TARGET_Z10" |
4788 | "@ | |
4789 | ll<g>hr\t%0,%1 | |
4790 | ll<g>h\t%0,%1 | |
4791 | ll<g>hrl\t%0,%1" | |
4792 | [(set_attr "op_type" "RXY,RRE,RIL") | |
4793 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4794 | (set_attr "cpu_facility" "*,*,z10") |
14cfceb7 IL |
4795 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3") |
4796 | (set_attr "relative_long" "*,*,yes")]) | |
963fc8d0 | 4797 | |
43a09b63 | 4798 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
4799 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
4800 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3e4be43f | 4801 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))] |
ec24698e UW |
4802 | "TARGET_EXTIMM" |
4803 | "@ | |
56477c21 AS |
4804 | ll<g><hc>r\t%0,%1 |
4805 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
4806 | [(set_attr "op_type" "RRE,RXY") |
4807 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 4808 | |
43a09b63 | 4809 | ; llgh, llgc |
56477c21 AS |
4810 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
4811 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 4812 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))] |
ec24698e | 4813 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 4814 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
4815 | [(set_attr "op_type" "RXY") |
4816 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
4817 | |
4818 | (define_insn_and_split "*zero_extendhisi2_31" | |
4819 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3e4be43f | 4820 | (zero_extend:SI (match_operand:HI 1 "s_operand" "S"))) |
ae156f85 | 4821 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 4822 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4823 | "#" |
4824 | "&& reload_completed" | |
4825 | [(set (match_dup 0) (const_int 0)) | |
4826 | (parallel | |
4827 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 4828 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4829 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 4830 | |
cc7ab9b7 UW |
4831 | (define_insn_and_split "*zero_extendqisi2_31" |
4832 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3e4be43f | 4833 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))] |
9e8327e3 | 4834 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4835 | "#" |
4836 | "&& reload_completed" | |
4837 | [(set (match_dup 0) (const_int 0)) | |
4838 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4839 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 4840 | |
9db1d521 HP |
4841 | ; |
4842 | ; zero_extendqihi2 instruction pattern(s). | |
4843 | ; | |
4844 | ||
9db1d521 HP |
4845 | (define_expand "zero_extendqihi2" |
4846 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 4847 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 4848 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 4849 | { |
4023fb28 UW |
4850 | operands[1] = gen_lowpart (HImode, operands[1]); |
4851 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
4852 | DONE; | |
ec24698e | 4853 | }) |
9db1d521 | 4854 | |
4023fb28 | 4855 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 4856 | [(set (match_operand:HI 0 "register_operand" "=d") |
3e4be43f | 4857 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] |
ec24698e | 4858 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 4859 | "llgc\t%0,%1" |
9381e3f1 WG |
4860 | [(set_attr "op_type" "RXY") |
4861 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 4862 | |
cc7ab9b7 UW |
4863 | (define_insn_and_split "*zero_extendqihi2_31" |
4864 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
3e4be43f | 4865 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] |
9e8327e3 | 4866 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4867 | "#" |
4868 | "&& reload_completed" | |
4869 | [(set (match_dup 0) (const_int 0)) | |
4870 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4871 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 4872 | |
609e7e80 | 4873 | ; |
9751ad6e | 4874 | ; fixuns_trunc(dd|td|sf|df|tf)(si|di)2 expander |
609e7e80 AK |
4875 | ; |
4876 | ||
9751ad6e AK |
4877 | ; This is the only entry point for fixuns_trunc. It multiplexes the |
4878 | ; expansion to either the *_emu expanders below for pre z196 machines | |
4879 | ; or emits the default pattern otherwise. | |
4880 | (define_expand "fixuns_trunc<FP:mode><GPR:mode>2" | |
609e7e80 | 4881 | [(parallel |
9751ad6e AK |
4882 | [(set (match_operand:GPR 0 "register_operand" "") |
4883 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" ""))) | |
4884 | (unspec:GPR [(match_dup 2)] UNSPEC_ROUND) | |
65b1d8ea | 4885 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e | 4886 | "TARGET_HARD_FLOAT" |
609e7e80 | 4887 | { |
65b1d8ea AK |
4888 | if (!TARGET_Z196) |
4889 | { | |
9751ad6e AK |
4890 | /* We don't provide emulation for TD|DD->SI. */ |
4891 | if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT | |
4892 | && <GPR:MODE>mode == SImode) | |
4893 | FAIL; | |
4894 | emit_insn (gen_fixuns_trunc<FP:mode><GPR:mode>2_emu (operands[0], | |
4895 | operands[1])); | |
65b1d8ea AK |
4896 | DONE; |
4897 | } | |
9751ad6e AK |
4898 | |
4899 | if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT) | |
4900 | operands[2] = GEN_INT (DFP_RND_TOWARD_0); | |
4901 | else | |
4902 | operands[2] = GEN_INT (BFP_RND_TOWARD_0); | |
609e7e80 AK |
4903 | }) |
4904 | ||
9751ad6e AK |
4905 | ; (sf|df|tf)->unsigned (si|di) |
4906 | ||
4907 | ; Emulate the unsigned conversion with the signed version for pre z196 | |
4908 | ; machines. | |
4909 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2_emu" | |
4910 | [(parallel | |
4911 | [(set (match_operand:GPR 0 "register_operand" "") | |
4912 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) | |
4913 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) | |
4914 | (clobber (reg:CC CC_REGNUM))])] | |
4915 | "!TARGET_Z196 && TARGET_HARD_FLOAT" | |
4916 | { | |
4917 | rtx_code_label *label1 = gen_label_rtx (); | |
4918 | rtx_code_label *label2 = gen_label_rtx (); | |
4919 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); | |
4920 | REAL_VALUE_TYPE cmp, sub; | |
4921 | ||
4922 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); | |
4923 | real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode); | |
4924 | real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode); | |
4925 | ||
4926 | emit_cmp_and_jump_insns (operands[1], | |
4927 | const_double_from_real_value (cmp, <BFP:MODE>mode), | |
4928 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4929 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], | |
4930 | const_double_from_real_value (sub, <BFP:MODE>mode))); | |
4931 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, | |
4932 | GEN_INT (BFP_RND_TOWARD_MINF))); | |
4933 | emit_jump (label2); | |
4934 | ||
4935 | emit_label (label1); | |
4936 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], | |
4937 | operands[1], | |
4938 | GEN_INT (BFP_RND_TOWARD_0))); | |
4939 | emit_label (label2); | |
4940 | DONE; | |
4941 | }) | |
4942 | ||
4943 | ; dd->unsigned di | |
4944 | ||
4945 | ; Emulate the unsigned conversion with the signed version for pre z196 | |
4946 | ; machines. | |
4947 | (define_expand "fixuns_truncdddi2_emu" | |
65b1d8ea AK |
4948 | [(parallel |
4949 | [(set (match_operand:DI 0 "register_operand" "") | |
9751ad6e | 4950 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) |
ae8e301e | 4951 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea AK |
4952 | (clobber (reg:CC CC_REGNUM))])] |
4953 | ||
9751ad6e | 4954 | "!TARGET_Z196 && TARGET_HARD_DFP" |
609e7e80 | 4955 | { |
9751ad6e AK |
4956 | rtx_code_label *label1 = gen_label_rtx (); |
4957 | rtx_code_label *label2 = gen_label_rtx (); | |
4958 | rtx temp = gen_reg_rtx (TDmode); | |
4959 | REAL_VALUE_TYPE cmp, sub; | |
4960 | ||
4961 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4962 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4963 | ||
4964 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
4965 | solution is doing the check and the subtraction in TD mode and using a | |
4966 | TD -> DI convert afterwards. */ | |
4967 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
4968 | temp = force_reg (TDmode, temp); | |
4969 | emit_cmp_and_jump_insns (temp, | |
4970 | const_double_from_real_value (cmp, TDmode), | |
4971 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4972 | emit_insn (gen_subtd3 (temp, temp, | |
4973 | const_double_from_real_value (sub, TDmode))); | |
4974 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, | |
4975 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
4976 | emit_jump (label2); | |
4977 | ||
4978 | emit_label (label1); | |
4979 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], | |
4980 | GEN_INT (DFP_RND_TOWARD_0))); | |
4981 | emit_label (label2); | |
4982 | DONE; | |
609e7e80 | 4983 | }) |
cc7ab9b7 | 4984 | |
9751ad6e | 4985 | ; td->unsigned di |
9db1d521 | 4986 | |
9751ad6e AK |
4987 | ; Emulate the unsigned conversion with the signed version for pre z196 |
4988 | ; machines. | |
4989 | (define_expand "fixuns_trunctddi2_emu" | |
65b1d8ea | 4990 | [(parallel |
9751ad6e AK |
4991 | [(set (match_operand:DI 0 "register_operand" "") |
4992 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) | |
4993 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) | |
65b1d8ea | 4994 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e AK |
4995 | |
4996 | "!TARGET_Z196 && TARGET_HARD_DFP" | |
9db1d521 | 4997 | { |
9751ad6e AK |
4998 | rtx_code_label *label1 = gen_label_rtx (); |
4999 | rtx_code_label *label2 = gen_label_rtx (); | |
5000 | rtx temp = gen_reg_rtx (TDmode); | |
5001 | REAL_VALUE_TYPE cmp, sub; | |
5002 | ||
5003 | operands[1] = force_reg (TDmode, operands[1]); | |
5004 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
5005 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
5006 | ||
5007 | emit_cmp_and_jump_insns (operands[1], | |
5008 | const_double_from_real_value (cmp, TDmode), | |
5009 | LT, NULL_RTX, VOIDmode, 0, label1); | |
5010 | emit_insn (gen_subtd3 (temp, operands[1], | |
5011 | const_double_from_real_value (sub, TDmode))); | |
5012 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, | |
5013 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
5014 | emit_jump (label2); | |
5015 | ||
5016 | emit_label (label1); | |
5017 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], | |
5018 | GEN_INT (DFP_RND_TOWARD_0))); | |
5019 | emit_label (label2); | |
5020 | DONE; | |
10bbf137 | 5021 | }) |
9db1d521 | 5022 | |
9751ad6e AK |
5023 | ; Just a dummy to make the code in the first expander a bit easier. |
5024 | (define_expand "fixuns_trunc<mode>si2_emu" | |
65b1d8ea AK |
5025 | [(parallel |
5026 | [(set (match_operand:SI 0 "register_operand" "") | |
5027 | (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) | |
9751ad6e | 5028 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea | 5029 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e AK |
5030 | |
5031 | "!TARGET_Z196 && TARGET_HARD_DFP" | |
5032 | { | |
5033 | FAIL; | |
5034 | }) | |
5035 | ||
65b1d8ea AK |
5036 | |
5037 | ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. | |
5038 | ||
9751ad6e AK |
5039 | ; df -> unsigned di |
5040 | (define_insn "*fixuns_truncdfdi2_vx" | |
6e5b5de8 AK |
5041 | [(set (match_operand:DI 0 "register_operand" "=d,v") |
5042 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
5043 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
5044 | (clobber (reg:CC CC_REGNUM))] | |
9751ad6e AK |
5045 | "TARGET_VX && TARGET_HARD_FLOAT" |
5046 | "@ | |
5047 | clgdbr\t%0,%h2,%1,0 | |
5048 | wclgdb\t%v0,%v1,0,%h2" | |
5049 | [(set_attr "op_type" "RRF,VRR") | |
5050 | (set_attr "type" "ftoi")]) | |
6e5b5de8 | 5051 | |
9751ad6e | 5052 | ; (dd|td|sf|df|tf)->unsigned (di|si) |
65b1d8ea AK |
5053 | ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr |
5054 | ; clfdtr, clfxtr, clgdtr, clgxtr | |
5055 | (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" | |
6e5b5de8 AK |
5056 | [(set (match_operand:GPR 0 "register_operand" "=d") |
5057 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) | |
5058 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
65b1d8ea | 5059 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 | 5060 | "TARGET_Z196 && TARGET_HARD_FLOAT |
a579871b | 5061 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)" |
65b1d8ea AK |
5062 | "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" |
5063 | [(set_attr "op_type" "RRF") | |
5064 | (set_attr "type" "ftoi")]) | |
5065 | ||
b60cb710 AK |
5066 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
5067 | [(set (match_operand:GPR 0 "register_operand" "") | |
5068 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
5069 | "TARGET_HARD_FLOAT" | |
9db1d521 | 5070 | { |
b60cb710 | 5071 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
ae8e301e | 5072 | GEN_INT (BFP_RND_TOWARD_0))); |
9db1d521 | 5073 | DONE; |
10bbf137 | 5074 | }) |
9db1d521 | 5075 | |
6e5b5de8 AK |
5076 | (define_insn "*fix_truncdfdi2_bfp_z13" |
5077 | [(set (match_operand:DI 0 "register_operand" "=d,v") | |
5078 | (fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
5079 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
5080 | (clobber (reg:CC CC_REGNUM))] | |
a579871b | 5081 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5082 | "@ |
5083 | cgdbr\t%0,%h2,%1 | |
5084 | wcgdb\t%v0,%v1,0,%h2" | |
5085 | [(set_attr "op_type" "RRE,VRR") | |
5086 | (set_attr "type" "ftoi")]) | |
5087 | ||
43a09b63 | 5088 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
6e5b5de8 AK |
5089 | (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp" |
5090 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5091 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
5092 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
ae156f85 | 5093 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 AK |
5094 | "TARGET_HARD_FLOAT |
5095 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)" | |
7b6baae1 | 5096 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 5097 | [(set_attr "op_type" "RRE") |
077dab3b | 5098 | (set_attr "type" "ftoi")]) |
9db1d521 | 5099 | |
6e5b5de8 AK |
5100 | (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
5101 | [(parallel | |
5102 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
5103 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
5104 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
5105 | (clobber (reg:CC CC_REGNUM))])] | |
5106 | "TARGET_HARD_FLOAT") | |
609e7e80 AK |
5107 | ; |
5108 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
5109 | ; | |
5110 | ||
99cd7dd0 AK |
5111 | (define_expand "fix_trunc<mode>di2" |
5112 | [(set (match_operand:DI 0 "register_operand" "") | |
5113 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
9602b6a1 | 5114 | "TARGET_ZARCH && TARGET_HARD_DFP" |
99cd7dd0 AK |
5115 | { |
5116 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
5117 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
ae8e301e | 5118 | GEN_INT (DFP_RND_TOWARD_0))); |
99cd7dd0 AK |
5119 | DONE; |
5120 | }) | |
5121 | ||
609e7e80 | 5122 | ; cgxtr, cgdtr |
99cd7dd0 | 5123 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
5124 | [(set (match_operand:DI 0 "register_operand" "=d") |
5125 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
5126 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
5127 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 5128 | "TARGET_ZARCH && TARGET_HARD_DFP" |
609e7e80 AK |
5129 | "cg<DFP:xde>tr\t%0,%h2,%1" |
5130 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 5131 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
5132 | |
5133 | ||
f61a2c7d AK |
5134 | ; |
5135 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
5136 | ; | |
5137 | ||
5138 | (define_expand "fix_trunctf<mode>2" | |
5139 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
5140 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
ae8e301e | 5141 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) |
f61a2c7d | 5142 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5143 | "TARGET_HARD_FLOAT" |
142cd70f | 5144 | "") |
9db1d521 | 5145 | |
9db1d521 | 5146 | |
9db1d521 | 5147 | ; |
142cd70f | 5148 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
5149 | ; |
5150 | ||
609e7e80 | 5151 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 5152 | (define_insn "floatdi<mode>2" |
62d3f261 AK |
5153 | [(set (match_operand:FP 0 "register_operand" "=f,v") |
5154 | (float:FP (match_operand:DI 1 "register_operand" "d,v")))] | |
9602b6a1 | 5155 | "TARGET_ZARCH && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5156 | "@ |
5157 | c<xde>g<bt>r\t%0,%1 | |
5158 | wcdgb\t%v0,%v1,0,0" | |
5159 | [(set_attr "op_type" "RRE,VRR") | |
5160 | (set_attr "type" "itof<mode>" ) | |
285363a1 | 5161 | (set_attr "cpu_facility" "*,vx") |
62d3f261 | 5162 | (set_attr "enabled" "*,<DFDI>")]) |
9db1d521 | 5163 | |
43a09b63 | 5164 | ; cxfbr, cdfbr, cefbr |
142cd70f | 5165 | (define_insn "floatsi<mode>2" |
7b6baae1 AK |
5166 | [(set (match_operand:BFP 0 "register_operand" "=f") |
5167 | (float:BFP (match_operand:SI 1 "register_operand" "d")))] | |
142cd70f | 5168 | "TARGET_HARD_FLOAT" |
f61a2c7d AK |
5169 | "c<xde>fbr\t%0,%1" |
5170 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 5171 | (set_attr "type" "itof<mode>" )]) |
f61a2c7d | 5172 | |
65b1d8ea AK |
5173 | ; cxftr, cdftr |
5174 | (define_insn "floatsi<mode>2" | |
5175 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5176 | (float:DFP (match_operand:SI 1 "register_operand" "d")))] | |
5177 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
5178 | "c<xde>ftr\t%0,0,%1,0" | |
5179 | [(set_attr "op_type" "RRE") | |
5180 | (set_attr "type" "itof<mode>" )]) | |
5181 | ||
5182 | ; | |
5183 | ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). | |
5184 | ; | |
5185 | ||
6e5b5de8 AK |
5186 | (define_insn "*floatunsdidf2_z13" |
5187 | [(set (match_operand:DF 0 "register_operand" "=f,v") | |
5188 | (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))] | |
a579871b | 5189 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5190 | "@ |
5191 | cdlgbr\t%0,0,%1,0 | |
5192 | wcdlgb\t%v0,%v1,0,0" | |
5193 | [(set_attr "op_type" "RRE,VRR") | |
5194 | (set_attr "type" "itofdf")]) | |
5195 | ||
65b1d8ea AK |
5196 | ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr |
5197 | ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr | |
6e5b5de8 AK |
5198 | (define_insn "*floatuns<GPR:mode><FP:mode>2" |
5199 | [(set (match_operand:FP 0 "register_operand" "=f") | |
5200 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] | |
5201 | "TARGET_Z196 && TARGET_HARD_FLOAT | |
5202 | && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)" | |
65b1d8ea AK |
5203 | "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" |
5204 | [(set_attr "op_type" "RRE") | |
6e5b5de8 AK |
5205 | (set_attr "type" "itof<FP:mode>")]) |
5206 | ||
5207 | (define_expand "floatuns<GPR:mode><FP:mode>2" | |
5208 | [(set (match_operand:FP 0 "register_operand" "") | |
5209 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))] | |
5210 | "TARGET_Z196 && TARGET_HARD_FLOAT") | |
f61a2c7d | 5211 | |
9db1d521 HP |
5212 | ; |
5213 | ; truncdfsf2 instruction pattern(s). | |
5214 | ; | |
5215 | ||
142cd70f | 5216 | (define_insn "truncdfsf2" |
6e5b5de8 AK |
5217 | [(set (match_operand:SF 0 "register_operand" "=f,v") |
5218 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))] | |
142cd70f | 5219 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5220 | "@ |
5221 | ledbr\t%0,%1 | |
5222 | wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed | |
5223 | ; According to BFP rounding mode | |
5224 | [(set_attr "op_type" "RRE,VRR") | |
5225 | (set_attr "type" "ftruncdf") | |
285363a1 | 5226 | (set_attr "cpu_facility" "*,vx")]) |
9db1d521 | 5227 | |
f61a2c7d | 5228 | ; |
142cd70f | 5229 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
5230 | ; |
5231 | ||
142cd70f AK |
5232 | ; ldxbr, lexbr |
5233 | (define_insn "trunctf<mode>2" | |
5234 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
5235 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 5236 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
5237 | "TARGET_HARD_FLOAT" |
5238 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 5239 | [(set_attr "length" "6") |
9381e3f1 | 5240 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 5241 | |
609e7e80 AK |
5242 | ; |
5243 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
5244 | ; | |
5245 | ||
432d4670 AK |
5246 | |
5247 | (define_expand "trunctddd2" | |
5248 | [(parallel | |
5249 | [(set (match_operand:DD 0 "register_operand" "") | |
5250 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) | |
5251 | (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND) | |
5252 | (clobber (scratch:TD))])] | |
5253 | "TARGET_HARD_DFP") | |
5254 | ||
5255 | (define_insn "*trunctddd2" | |
609e7e80 | 5256 | [(set (match_operand:DD 0 "register_operand" "=f") |
bf259a77 | 5257 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
432d4670 AK |
5258 | (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND) |
5259 | (clobber (match_scratch:TD 3 "=f"))] | |
fb068247 | 5260 | "TARGET_HARD_DFP" |
432d4670 | 5261 | "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3" |
bf259a77 | 5262 | [(set_attr "length" "6") |
9381e3f1 | 5263 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
5264 | |
5265 | (define_insn "truncddsd2" | |
5266 | [(set (match_operand:SD 0 "register_operand" "=f") | |
5267 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 5268 | "TARGET_HARD_DFP" |
609e7e80 AK |
5269 | "ledtr\t%0,0,%1,0" |
5270 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 5271 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 5272 | |
feade5a8 AK |
5273 | (define_expand "trunctdsd2" |
5274 | [(parallel | |
d5a216fa | 5275 | [(set (match_dup 2) |
feade5a8 | 5276 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) |
432d4670 | 5277 | (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND) |
d5a216fa | 5278 | (clobber (match_scratch:TD 3 ""))]) |
feade5a8 | 5279 | (set (match_operand:SD 0 "register_operand" "") |
d5a216fa | 5280 | (float_truncate:SD (match_dup 2)))] |
feade5a8 AK |
5281 | "TARGET_HARD_DFP" |
5282 | { | |
d5a216fa | 5283 | operands[2] = gen_reg_rtx (DDmode); |
feade5a8 AK |
5284 | }) |
5285 | ||
9db1d521 | 5286 | ; |
142cd70f | 5287 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
5288 | ; |
5289 | ||
2de2b3f9 | 5290 | ; wflls |
6e5b5de8 AK |
5291 | (define_insn "*extendsfdf2_z13" |
5292 | [(set (match_operand:DF 0 "register_operand" "=f,f,v") | |
5293 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))] | |
a579871b | 5294 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5295 | "@ |
5296 | ldebr\t%0,%1 | |
5297 | ldeb\t%0,%1 | |
5298 | wldeb\t%v0,%v1" | |
5299 | [(set_attr "op_type" "RRE,RXE,VRR") | |
5300 | (set_attr "type" "fsimpdf, floaddf,fsimpdf")]) | |
5301 | ||
142cd70f | 5302 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
6e5b5de8 AK |
5303 | (define_insn "*extend<DSF:mode><BFP:mode>2" |
5304 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
142cd70f AK |
5305 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] |
5306 | "TARGET_HARD_FLOAT | |
6e5b5de8 AK |
5307 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode) |
5308 | && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)" | |
f61a2c7d | 5309 | "@ |
142cd70f AK |
5310 | l<BFP:xde><DSF:xde>br\t%0,%1 |
5311 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
6e5b5de8 AK |
5312 | [(set_attr "op_type" "RRE,RXE") |
5313 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) | |
5314 | ||
5315 | (define_expand "extend<DSF:mode><BFP:mode>2" | |
5316 | [(set (match_operand:BFP 0 "register_operand" "") | |
5317 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))] | |
5318 | "TARGET_HARD_FLOAT | |
5319 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)") | |
f61a2c7d | 5320 | |
609e7e80 AK |
5321 | ; |
5322 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
5323 | ; | |
5324 | ||
5325 | (define_insn "extendddtd2" | |
5326 | [(set (match_operand:TD 0 "register_operand" "=f") | |
5327 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 5328 | "TARGET_HARD_DFP" |
609e7e80 AK |
5329 | "lxdtr\t%0,%1,0" |
5330 | [(set_attr "op_type" "RRF") | |
5331 | (set_attr "type" "fsimptf")]) | |
5332 | ||
5333 | (define_insn "extendsddd2" | |
5334 | [(set (match_operand:DD 0 "register_operand" "=f") | |
5335 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 5336 | "TARGET_HARD_DFP" |
609e7e80 AK |
5337 | "ldetr\t%0,%1,0" |
5338 | [(set_attr "op_type" "RRF") | |
5339 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 5340 | |
feade5a8 AK |
5341 | (define_expand "extendsdtd2" |
5342 | [(set (match_dup 2) | |
5343 | (float_extend:DD (match_operand:SD 1 "register_operand" ""))) | |
5344 | (set (match_operand:TD 0 "register_operand" "") | |
5345 | (float_extend:TD (match_dup 2)))] | |
5346 | "TARGET_HARD_DFP" | |
5347 | { | |
5348 | operands[2] = gen_reg_rtx (DDmode); | |
5349 | }) | |
5350 | ||
d12a76f3 AK |
5351 | ; Binary Floating Point - load fp integer |
5352 | ||
5353 | ; Expanders for: floor, btrunc, round, ceil, and nearbyint | |
5354 | ; For all of them the inexact exceptions are suppressed. | |
5355 | ||
5356 | ; fiebra, fidbra, fixbra | |
5357 | (define_insn "<FPINT:fpint_name><BFP:mode>2" | |
5358 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
5359 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
5360 | FPINT))] | |
5361 | "TARGET_Z196" | |
5362 | "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
5363 | [(set_attr "op_type" "RRF") | |
5364 | (set_attr "type" "fsimp<BFP:mode>")]) | |
5365 | ||
5366 | ; rint is supposed to raise an inexact exception so we can use the | |
5367 | ; older instructions. | |
5368 | ||
5369 | ; fiebr, fidbr, fixbr | |
5370 | (define_insn "rint<BFP:mode>2" | |
5371 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
5372 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
5373 | UNSPEC_FPINT_RINT))] | |
5374 | "" | |
5375 | "fi<BFP:xde>br\t%0,0,%1" | |
5376 | [(set_attr "op_type" "RRF") | |
5377 | (set_attr "type" "fsimp<BFP:mode>")]) | |
5378 | ||
5379 | ||
5380 | ; Decimal Floating Point - load fp integer | |
5381 | ||
5382 | ; fidtr, fixtr | |
5383 | (define_insn "<FPINT:fpint_name><DFP:mode>2" | |
5384 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5385 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5386 | FPINT))] | |
5387 | "TARGET_HARD_DFP" | |
5388 | "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
5389 | [(set_attr "op_type" "RRF") | |
5390 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5391 | ||
5392 | ; fidtr, fixtr | |
5393 | (define_insn "rint<DFP:mode>2" | |
5394 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5395 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5396 | UNSPEC_FPINT_RINT))] | |
5397 | "TARGET_HARD_DFP" | |
5398 | "fi<DFP:xde>tr\t%0,0,%1,0" | |
5399 | [(set_attr "op_type" "RRF") | |
5400 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5401 | ||
5402 | ; | |
35dd9a0e AK |
5403 | ; Binary <-> Decimal floating point trunc patterns |
5404 | ; | |
5405 | ||
5406 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
5407 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5408 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5409 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5410 | (clobber (reg:CC CC_REGNUM)) |
5411 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5412 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5413 | "pfpo") |
5414 | ||
5415 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
5416 | [(set (reg:BFP FPR0_REGNUM) | |
2cf4c39e | 5417 | (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5418 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5419 | (clobber (reg:CC CC_REGNUM)) |
5420 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5421 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5422 | "pfpo") |
5423 | ||
5424 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5425 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5426 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5427 | (parallel | |
5428 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5429 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5430 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5431 | (clobber (reg:CC CC_REGNUM)) |
5432 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5433 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5434 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5435 | "TARGET_HARD_DFP |
35dd9a0e AK |
5436 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5437 | { | |
5438 | HOST_WIDE_INT flags; | |
5439 | ||
ced8d882 AK |
5440 | /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the |
5441 | rounding mode of the target format needs to be used. */ | |
5442 | ||
35dd9a0e AK |
5443 | flags = (PFPO_CONVERT | |
5444 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
ced8d882 AK |
5445 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT | |
5446 | PFPO_RND_MODE_DFP); | |
35dd9a0e AK |
5447 | |
5448 | operands[2] = GEN_INT (flags); | |
5449 | }) | |
5450 | ||
5451 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5452 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5453 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5454 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5455 | (parallel | |
2cf4c39e | 5456 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5457 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5458 | (clobber (reg:CC CC_REGNUM)) |
5459 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5460 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5461 | "TARGET_HARD_DFP |
35dd9a0e AK |
5462 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
5463 | { | |
5464 | HOST_WIDE_INT flags; | |
5465 | ||
ced8d882 AK |
5466 | /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the |
5467 | rounding mode of the target format needs to be used. */ | |
5468 | ||
35dd9a0e AK |
5469 | flags = (PFPO_CONVERT | |
5470 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
ced8d882 AK |
5471 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT | |
5472 | PFPO_RND_MODE_BFP); | |
35dd9a0e AK |
5473 | |
5474 | operands[2] = GEN_INT (flags); | |
5475 | }) | |
5476 | ||
5477 | ; | |
5478 | ; Binary <-> Decimal floating point extend patterns | |
5479 | ; | |
5480 | ||
5481 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5482 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5483 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5484 | (clobber (reg:CC CC_REGNUM)) |
5485 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5486 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5487 | "pfpo") |
5488 | ||
5489 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5490 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5491 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5492 | (clobber (reg:CC CC_REGNUM)) |
5493 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5494 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5495 | "pfpo") |
5496 | ||
5497 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5498 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5499 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5500 | (parallel | |
5501 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5502 | (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5503 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5504 | (clobber (reg:CC CC_REGNUM)) |
5505 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5506 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5507 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5508 | "TARGET_HARD_DFP |
35dd9a0e AK |
5509 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5510 | { | |
5511 | HOST_WIDE_INT flags; | |
5512 | ||
ced8d882 AK |
5513 | /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the |
5514 | rounding mode of the target format needs to be used. */ | |
5515 | ||
35dd9a0e AK |
5516 | flags = (PFPO_CONVERT | |
5517 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
ced8d882 AK |
5518 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT | |
5519 | PFPO_RND_MODE_DFP); | |
35dd9a0e AK |
5520 | |
5521 | operands[2] = GEN_INT (flags); | |
5522 | }) | |
5523 | ||
5524 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5525 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5526 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5527 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5528 | (parallel | |
2cf4c39e | 5529 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5530 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5531 | (clobber (reg:CC CC_REGNUM)) |
5532 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5533 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5534 | "TARGET_HARD_DFP |
35dd9a0e AK |
5535 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
5536 | { | |
5537 | HOST_WIDE_INT flags; | |
5538 | ||
ced8d882 AK |
5539 | /* According to IEEE 754 2008 4.3 'Rounding-direction attributes' the |
5540 | rounding mode of the target format needs to be used. */ | |
5541 | ||
35dd9a0e AK |
5542 | flags = (PFPO_CONVERT | |
5543 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
ced8d882 AK |
5544 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT | |
5545 | PFPO_RND_MODE_BFP); | |
35dd9a0e AK |
5546 | |
5547 | operands[2] = GEN_INT (flags); | |
5548 | }) | |
5549 | ||
5550 | ||
9db1d521 | 5551 | ;; |
fae778eb | 5552 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 5553 | ;; |
fae778eb | 5554 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
5555 | ; because of unpredictable Bits in Register for Halfword and Byte |
5556 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
5557 | ||
07893d4f UW |
5558 | ;; |
5559 | ;;- Add instructions. | |
5560 | ;; | |
5561 | ||
1c7b1b7e UW |
5562 | ; |
5563 | ; addti3 instruction pattern(s). | |
5564 | ; | |
5565 | ||
085261c8 AK |
5566 | (define_expand "addti3" |
5567 | [(parallel | |
5568 | [(set (match_operand:TI 0 "register_operand" "") | |
5569 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "") | |
5570 | (match_operand:TI 2 "general_operand" "") ) ) | |
5571 | (clobber (reg:CC CC_REGNUM))])] | |
5572 | "TARGET_ZARCH" | |
5573 | { | |
5574 | /* For z13 we have vaq which doesn't set CC. */ | |
5575 | if (TARGET_VX) | |
5576 | { | |
5577 | emit_insn (gen_rtx_SET (operands[0], | |
5578 | gen_rtx_PLUS (TImode, | |
5579 | copy_to_mode_reg (TImode, operands[1]), | |
5580 | copy_to_mode_reg (TImode, operands[2])))); | |
5581 | DONE; | |
5582 | } | |
5583 | }) | |
5584 | ||
5585 | (define_insn_and_split "*addti3" | |
5586 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
1c7b1b7e | 5587 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
085261c8 | 5588 | (match_operand:TI 2 "general_operand" "do") ) ) |
ae156f85 | 5589 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5590 | "TARGET_ZARCH" |
1c7b1b7e UW |
5591 | "#" |
5592 | "&& reload_completed" | |
5593 | [(parallel | |
ae156f85 | 5594 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
5595 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
5596 | (match_dup 7))) | |
5597 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
5598 | (parallel | |
a94a76a7 UW |
5599 | [(set (match_dup 3) (plus:DI |
5600 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5601 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5602 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
5603 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5604 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5605 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5606 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5607 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5608 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5609 | [(set_attr "op_type" "*") | |
5610 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 5611 | |
07893d4f UW |
5612 | ; |
5613 | ; adddi3 instruction pattern(s). | |
5614 | ; | |
5615 | ||
3298c037 AK |
5616 | (define_expand "adddi3" |
5617 | [(parallel | |
963fc8d0 | 5618 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
5619 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
5620 | (match_operand:DI 2 "general_operand" ""))) | |
5621 | (clobber (reg:CC CC_REGNUM))])] | |
5622 | "" | |
5623 | "") | |
5624 | ||
07893d4f UW |
5625 | (define_insn "*adddi3_sign" |
5626 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 5627 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 5628 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5629 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5630 | "TARGET_ZARCH" |
07893d4f | 5631 | "@ |
d40c829f UW |
5632 | agfr\t%0,%2 |
5633 | agf\t%0,%2" | |
65b1d8ea AK |
5634 | [(set_attr "op_type" "RRE,RXY") |
5635 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
07893d4f UW |
5636 | |
5637 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 5638 | [(set (reg CC_REGNUM) |
3e4be43f | 5639 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f UW |
5640 | (match_operand:DI 1 "register_operand" "0,0")) |
5641 | (const_int 0))) | |
5642 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5643 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
9602b6a1 | 5644 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5645 | "@ |
d40c829f UW |
5646 | algfr\t%0,%2 |
5647 | algf\t%0,%2" | |
9381e3f1 WG |
5648 | [(set_attr "op_type" "RRE,RXY") |
5649 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5650 | |
5651 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 5652 | [(set (reg CC_REGNUM) |
3e4be43f | 5653 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f UW |
5654 | (match_operand:DI 1 "register_operand" "0,0")) |
5655 | (const_int 0))) | |
5656 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5657 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5658 | "@ |
d40c829f UW |
5659 | algfr\t%0,%2 |
5660 | algf\t%0,%2" | |
9381e3f1 WG |
5661 | [(set_attr "op_type" "RRE,RXY") |
5662 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5663 | |
5664 | (define_insn "*adddi3_zero" | |
5665 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 5666 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 5667 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5668 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5669 | "TARGET_ZARCH" |
07893d4f | 5670 | "@ |
d40c829f UW |
5671 | algfr\t%0,%2 |
5672 | algf\t%0,%2" | |
9381e3f1 WG |
5673 | [(set_attr "op_type" "RRE,RXY") |
5674 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 5675 | |
e69166de | 5676 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 5677 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
5678 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
5679 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5680 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 5681 | "!TARGET_ZARCH" |
e69166de UW |
5682 | "#" |
5683 | "&& reload_completed" | |
5684 | [(parallel | |
ae156f85 | 5685 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
5686 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5687 | (match_dup 7))) | |
5688 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5689 | (parallel | |
a94a76a7 UW |
5690 | [(set (match_dup 3) (plus:SI |
5691 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5692 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5693 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
5694 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5695 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5696 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5697 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5698 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 5699 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 5700 | |
3298c037 AK |
5701 | ; |
5702 | ; addsi3 instruction pattern(s). | |
5703 | ; | |
5704 | ||
5705 | (define_expand "addsi3" | |
07893d4f | 5706 | [(parallel |
963fc8d0 | 5707 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
5708 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
5709 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 5710 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5711 | "" |
07893d4f | 5712 | "") |
9db1d521 | 5713 | |
3298c037 AK |
5714 | (define_insn "*addsi3_sign" |
5715 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5716 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5717 | (match_operand:SI 1 "register_operand" "0,0"))) | |
5718 | (clobber (reg:CC CC_REGNUM))] | |
5719 | "" | |
5720 | "@ | |
5721 | ah\t%0,%2 | |
5722 | ahy\t%0,%2" | |
65b1d8ea | 5723 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 5724 | (set_attr "cpu_facility" "*,longdisp") |
65b1d8ea | 5725 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) |
3298c037 | 5726 | |
9db1d521 | 5727 | ; |
3298c037 | 5728 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 5729 | ; |
9db1d521 | 5730 | |
65b1d8ea | 5731 | ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 5732 | (define_insn "*add<mode>3" |
3e4be43f UW |
5733 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S") |
5734 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0") | |
5735 | (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) ) | |
3298c037 AK |
5736 | (clobber (reg:CC CC_REGNUM))] |
5737 | "" | |
ec24698e | 5738 | "@ |
3298c037 | 5739 | a<g>r\t%0,%2 |
65b1d8ea | 5740 | a<g>rk\t%0,%1,%2 |
3298c037 | 5741 | a<g>hi\t%0,%h2 |
65b1d8ea | 5742 | a<g>hik\t%0,%1,%h2 |
3298c037 AK |
5743 | al<g>fi\t%0,%2 |
5744 | sl<g>fi\t%0,%n2 | |
5745 | a<g>\t%0,%2 | |
963fc8d0 AK |
5746 | a<y>\t%0,%2 |
5747 | a<g>si\t%0,%c2" | |
65b1d8ea | 5748 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") |
3e4be43f | 5749 | (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10") |
65b1d8ea AK |
5750 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, |
5751 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
0a3bdf9d | 5752 | |
65b1d8ea | 5753 | ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik |
3298c037 | 5754 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 5755 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5756 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5757 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5758 | (match_dup 1))) |
65b1d8ea | 5759 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") |
3298c037 | 5760 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5761 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5762 | "@ |
3298c037 | 5763 | al<g>r\t%0,%2 |
65b1d8ea | 5764 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5765 | al<g>fi\t%0,%2 |
5766 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5767 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5768 | al<g>\t%0,%2 |
963fc8d0 AK |
5769 | al<y>\t%0,%2 |
5770 | al<g>si\t%0,%c2" | |
65b1d8ea | 5771 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5772 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5773 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, |
5774 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5775 | |
65b1d8ea | 5776 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5777 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 5778 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5779 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5780 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5781 | (match_dup 1))) |
65b1d8ea | 5782 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5783 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5784 | "@ |
3298c037 | 5785 | al<g>r\t%0,%2 |
65b1d8ea | 5786 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5787 | al<g>\t%0,%2 |
5788 | al<y>\t%0,%2" | |
65b1d8ea | 5789 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5790 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5791 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5792 | |
65b1d8ea | 5793 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5794 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 5795 | [(set (reg CC_REGNUM) |
3e4be43f UW |
5796 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5797 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5798 | (match_dup 2))) |
3e4be43f | 5799 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") |
3298c037 | 5800 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5801 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5802 | "@ |
3298c037 | 5803 | al<g>r\t%0,%2 |
65b1d8ea | 5804 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5805 | al<g>fi\t%0,%2 |
5806 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5807 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5808 | al<g>\t%0,%2 |
963fc8d0 AK |
5809 | al<y>\t%0,%2 |
5810 | al<g>si\t%0,%c2" | |
65b1d8ea | 5811 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5812 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5813 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, |
5814 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5815 | |
65b1d8ea | 5816 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5817 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 5818 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5819 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5820 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5821 | (match_dup 2))) |
65b1d8ea | 5822 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5823 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5824 | "@ |
3298c037 | 5825 | al<g>r\t%0,%2 |
65b1d8ea | 5826 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5827 | al<g>\t%0,%2 |
5828 | al<y>\t%0,%2" | |
65b1d8ea | 5829 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5830 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5831 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5832 | |
65b1d8ea | 5833 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5834 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5835 | [(set (reg CC_REGNUM) |
3e4be43f UW |
5836 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5837 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
9db1d521 | 5838 | (const_int 0))) |
3e4be43f | 5839 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") |
3298c037 | 5840 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5841 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5842 | "@ |
3298c037 | 5843 | al<g>r\t%0,%2 |
65b1d8ea | 5844 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5845 | al<g>fi\t%0,%2 |
5846 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5847 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5848 | al<g>\t%0,%2 |
963fc8d0 AK |
5849 | al<y>\t%0,%2 |
5850 | al<g>si\t%0,%c2" | |
65b1d8ea | 5851 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5852 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5853 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, |
5854 | *,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5855 | |
65b1d8ea | 5856 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5857 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5858 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5859 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5860 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5861 | (const_int 0))) |
65b1d8ea | 5862 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5863 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5864 | "@ |
3298c037 | 5865 | al<g>r\t%0,%2 |
65b1d8ea | 5866 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5867 | al<g>\t%0,%2 |
5868 | al<y>\t%0,%2" | |
65b1d8ea | 5869 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5870 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5871 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
9db1d521 | 5872 | |
65b1d8ea | 5873 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5874 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 5875 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5876 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5877 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) | |
5878 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
3298c037 | 5879 | "s390_match_ccmode(insn, CCLmode)" |
d3632d41 | 5880 | "@ |
3298c037 | 5881 | al<g>r\t%0,%2 |
65b1d8ea | 5882 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5883 | al<g>\t%0,%2 |
5884 | al<y>\t%0,%2" | |
65b1d8ea | 5885 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5886 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5887 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5888 | |
963fc8d0 | 5889 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
5890 | (define_insn "*add<mode>3_imm_cc" |
5891 | [(set (reg CC_REGNUM) | |
65b1d8ea | 5892 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") |
3e4be43f | 5893 | (match_operand:GPR 2 "const_int_operand" " K, K,Os,C")) |
3298c037 | 5894 | (const_int 0))) |
3e4be43f | 5895 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S") |
3298c037 AK |
5896 | (plus:GPR (match_dup 1) (match_dup 2)))] |
5897 | "s390_match_ccmode (insn, CCAmode) | |
5898 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
2542ef05 RH |
5899 | || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
5900 | /* Avoid INT32_MIN on 32 bit. */ | |
5901 | && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" | |
9db1d521 | 5902 | "@ |
3298c037 | 5903 | a<g>hi\t%0,%h2 |
65b1d8ea | 5904 | a<g>hik\t%0,%1,%h2 |
963fc8d0 AK |
5905 | a<g>fi\t%0,%2 |
5906 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
5907 | [(set_attr "op_type" "RI,RIE,RIL,SIY") |
5908 | (set_attr "cpu_facility" "*,z196,extimm,z10") | |
5909 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5910 | |
7d2fd075 AK |
5911 | (define_insn "*adddi3_sign" |
5912 | [(set (match_operand:DI 0 "register_operand" "=d") | |
5913 | (plus:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) | |
5914 | (match_operand:DI 1 "register_operand" "0"))) | |
5915 | (clobber (reg:CC CC_REGNUM))] | |
e9e8efc9 | 5916 | "TARGET_Z14" |
7d2fd075 AK |
5917 | "agh\t%0,%2" |
5918 | [(set_attr "op_type" "RXY")]) | |
5919 | ||
9db1d521 | 5920 | ; |
609e7e80 | 5921 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5922 | ; |
5923 | ||
609e7e80 | 5924 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
6e5b5de8 | 5925 | ; FIXME: wfadb does not clobber cc |
142cd70f | 5926 | (define_insn "add<mode>3" |
2de2b3f9 AK |
5927 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
5928 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v") | |
5929 | (match_operand:FP 2 "general_operand" "f,f,R,v,v"))) | |
ae156f85 | 5930 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5931 | "TARGET_HARD_FLOAT" |
9db1d521 | 5932 | "@ |
62d3f261 AK |
5933 | a<xde>tr\t%0,%1,%2 |
5934 | a<xde>br\t%0,%2 | |
6e5b5de8 | 5935 | a<xde>b\t%0,%2 |
2de2b3f9 AK |
5936 | wfadb\t%v0,%v1,%v2 |
5937 | wfasb\t%v0,%v1,%v2" | |
5938 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 5939 | (set_attr "type" "fsimp<mode>") |
2de2b3f9 AK |
5940 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
5941 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 5942 | |
609e7e80 | 5943 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5944 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5945 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5946 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
5947 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5948 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5949 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 5950 | (plus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 5951 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5952 | "@ |
62d3f261 AK |
5953 | a<xde>tr\t%0,%1,%2 |
5954 | a<xde>br\t%0,%2 | |
f61a2c7d | 5955 | a<xde>b\t%0,%2" |
62d3f261 AK |
5956 | [(set_attr "op_type" "RRF,RRE,RXE") |
5957 | (set_attr "type" "fsimp<mode>") | |
5958 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5959 | |
609e7e80 | 5960 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5961 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5962 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5963 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
5964 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5965 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5966 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 5967 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5968 | "@ |
62d3f261 AK |
5969 | a<xde>tr\t%0,%1,%2 |
5970 | a<xde>br\t%0,%2 | |
f61a2c7d | 5971 | a<xde>b\t%0,%2" |
62d3f261 AK |
5972 | [(set_attr "op_type" "RRF,RRE,RXE") |
5973 | (set_attr "type" "fsimp<mode>") | |
5974 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5975 | |
72a4ddf2 AK |
5976 | ; |
5977 | ; Pointer add instruction patterns | |
5978 | ; | |
5979 | ||
5980 | ; This will match "*la_64" | |
5981 | (define_expand "addptrdi3" | |
5982 | [(set (match_operand:DI 0 "register_operand" "") | |
5983 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
5984 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
5985 | "TARGET_64BIT" | |
5986 | { | |
72a4ddf2 AK |
5987 | if (GET_CODE (operands[2]) == CONST_INT) |
5988 | { | |
357ddc7d TV |
5989 | HOST_WIDE_INT c = INTVAL (operands[2]); |
5990 | ||
72a4ddf2 AK |
5991 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
5992 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
5993 | { | |
5994 | operands[2] = force_const_mem (DImode, operands[2]); | |
5995 | operands[2] = force_reg (DImode, operands[2]); | |
5996 | } | |
5997 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
5998 | operands[2] = force_reg (DImode, operands[2]); | |
5999 | } | |
6000 | }) | |
6001 | ||
6002 | ; For 31 bit we have to prevent the generated pattern from matching | |
6003 | ; normal ADDs since la only does a 31 bit add. This is supposed to | |
6004 | ; match "force_la_31". | |
6005 | (define_expand "addptrsi3" | |
6006 | [(parallel | |
6007 | [(set (match_operand:SI 0 "register_operand" "") | |
6008 | (plus:SI (match_operand:SI 1 "register_operand" "") | |
6009 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
6010 | (use (const_int 0))])] | |
6011 | "!TARGET_64BIT" | |
6012 | { | |
72a4ddf2 AK |
6013 | if (GET_CODE (operands[2]) == CONST_INT) |
6014 | { | |
357ddc7d TV |
6015 | HOST_WIDE_INT c = INTVAL (operands[2]); |
6016 | ||
72a4ddf2 AK |
6017 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
6018 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
6019 | { | |
6020 | operands[2] = force_const_mem (SImode, operands[2]); | |
6021 | operands[2] = force_reg (SImode, operands[2]); | |
6022 | } | |
6023 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
6024 | operands[2] = force_reg (SImode, operands[2]); | |
6025 | } | |
6026 | }) | |
9db1d521 HP |
6027 | |
6028 | ;; | |
6029 | ;;- Subtract instructions. | |
6030 | ;; | |
6031 | ||
1c7b1b7e UW |
6032 | ; |
6033 | ; subti3 instruction pattern(s). | |
6034 | ; | |
6035 | ||
085261c8 AK |
6036 | (define_expand "subti3" |
6037 | [(parallel | |
6038 | [(set (match_operand:TI 0 "register_operand" "") | |
6039 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
6040 | (match_operand:TI 2 "general_operand" "") ) ) | |
6041 | (clobber (reg:CC CC_REGNUM))])] | |
6042 | "TARGET_ZARCH" | |
6043 | { | |
2d71f118 | 6044 | /* For z13 we have vsq which doesn't set CC. */ |
085261c8 AK |
6045 | if (TARGET_VX) |
6046 | { | |
6047 | emit_insn (gen_rtx_SET (operands[0], | |
6048 | gen_rtx_MINUS (TImode, | |
6049 | operands[1], | |
6050 | copy_to_mode_reg (TImode, operands[2])))); | |
6051 | DONE; | |
6052 | } | |
6053 | }) | |
6054 | ||
6055 | (define_insn_and_split "*subti3" | |
6056 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
6057 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
6058 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 6059 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6060 | "TARGET_ZARCH" |
1c7b1b7e UW |
6061 | "#" |
6062 | "&& reload_completed" | |
6063 | [(parallel | |
ae156f85 | 6064 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
6065 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
6066 | (match_dup 7))) | |
6067 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
6068 | (parallel | |
6069 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
6070 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
6071 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
6072 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
6073 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
6074 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
6075 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
6076 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
6077 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
6078 | [(set_attr "op_type" "*") | |
6079 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 6080 | |
9db1d521 HP |
6081 | ; |
6082 | ; subdi3 instruction pattern(s). | |
6083 | ; | |
6084 | ||
3298c037 AK |
6085 | (define_expand "subdi3" |
6086 | [(parallel | |
6087 | [(set (match_operand:DI 0 "register_operand" "") | |
6088 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
6089 | (match_operand:DI 2 "general_operand" ""))) | |
6090 | (clobber (reg:CC CC_REGNUM))])] | |
6091 | "" | |
6092 | "") | |
6093 | ||
07893d4f UW |
6094 | (define_insn "*subdi3_sign" |
6095 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
6096 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3e4be43f | 6097 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) |
ae156f85 | 6098 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6099 | "TARGET_ZARCH" |
07893d4f | 6100 | "@ |
d40c829f UW |
6101 | sgfr\t%0,%2 |
6102 | sgf\t%0,%2" | |
9381e3f1 | 6103 | [(set_attr "op_type" "RRE,RXY") |
65b1d8ea AK |
6104 | (set_attr "z10prop" "z10_c,*") |
6105 | (set_attr "z196prop" "z196_cracked")]) | |
07893d4f UW |
6106 | |
6107 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 6108 | [(set (reg CC_REGNUM) |
07893d4f | 6109 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6110 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) |
07893d4f UW |
6111 | (const_int 0))) |
6112 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
6113 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
9602b6a1 | 6114 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 6115 | "@ |
d40c829f UW |
6116 | slgfr\t%0,%2 |
6117 | slgf\t%0,%2" | |
9381e3f1 WG |
6118 | [(set_attr "op_type" "RRE,RXY") |
6119 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
6120 | |
6121 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 6122 | [(set (reg CC_REGNUM) |
07893d4f | 6123 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6124 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) |
07893d4f UW |
6125 | (const_int 0))) |
6126 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 6127 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 6128 | "@ |
d40c829f UW |
6129 | slgfr\t%0,%2 |
6130 | slgf\t%0,%2" | |
9381e3f1 WG |
6131 | [(set_attr "op_type" "RRE,RXY") |
6132 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
6133 | |
6134 | (define_insn "*subdi3_zero" | |
6135 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
6136 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3e4be43f | 6137 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) |
ae156f85 | 6138 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6139 | "TARGET_ZARCH" |
07893d4f | 6140 | "@ |
d40c829f UW |
6141 | slgfr\t%0,%2 |
6142 | slgf\t%0,%2" | |
9381e3f1 WG |
6143 | [(set_attr "op_type" "RRE,RXY") |
6144 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 6145 | |
e69166de UW |
6146 | (define_insn_and_split "*subdi3_31z" |
6147 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
6148 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
6149 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 6150 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6151 | "!TARGET_ZARCH" |
e69166de UW |
6152 | "#" |
6153 | "&& reload_completed" | |
6154 | [(parallel | |
ae156f85 | 6155 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
6156 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
6157 | (match_dup 7))) | |
6158 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
6159 | (parallel | |
6160 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
6161 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
6162 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
6163 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
6164 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
6165 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
6166 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
6167 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 6168 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 6169 | |
3298c037 AK |
6170 | ; |
6171 | ; subsi3 instruction pattern(s). | |
6172 | ; | |
6173 | ||
6174 | (define_expand "subsi3" | |
07893d4f | 6175 | [(parallel |
3298c037 AK |
6176 | [(set (match_operand:SI 0 "register_operand" "") |
6177 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
6178 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 6179 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 6180 | "" |
07893d4f | 6181 | "") |
9db1d521 | 6182 | |
3298c037 AK |
6183 | (define_insn "*subsi3_sign" |
6184 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
6185 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
6186 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
6187 | (clobber (reg:CC CC_REGNUM))] | |
6188 | "" | |
6189 | "@ | |
6190 | sh\t%0,%2 | |
6191 | shy\t%0,%2" | |
65b1d8ea | 6192 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 6193 | (set_attr "cpu_facility" "*,longdisp") |
65b1d8ea | 6194 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) |
3298c037 | 6195 | |
9db1d521 | 6196 | ; |
3298c037 | 6197 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
6198 | ; |
6199 | ||
65b1d8ea | 6200 | ; sr, s, sy, sgr, sg, srk, sgrk |
3298c037 | 6201 | (define_insn "*sub<mode>3" |
65b1d8ea AK |
6202 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
6203 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") | |
6204 | (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) | |
3298c037 AK |
6205 | (clobber (reg:CC CC_REGNUM))] |
6206 | "" | |
6207 | "@ | |
6208 | s<g>r\t%0,%2 | |
65b1d8ea | 6209 | s<g>rk\t%0,%1,%2 |
3298c037 AK |
6210 | s<g>\t%0,%2 |
6211 | s<y>\t%0,%2" | |
65b1d8ea | 6212 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6213 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6214 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
3298c037 | 6215 | |
65b1d8ea | 6216 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6217 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 6218 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6219 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6220 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 6221 | (match_dup 1))) |
65b1d8ea | 6222 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 6223 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 6224 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 6225 | "@ |
3298c037 | 6226 | sl<g>r\t%0,%2 |
65b1d8ea | 6227 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6228 | sl<g>\t%0,%2 |
6229 | sl<y>\t%0,%2" | |
65b1d8ea | 6230 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6231 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6232 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 6233 | |
65b1d8ea | 6234 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6235 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 6236 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6237 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6238 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 6239 | (match_dup 1))) |
65b1d8ea | 6240 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 6241 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 6242 | "@ |
3298c037 | 6243 | sl<g>r\t%0,%2 |
65b1d8ea | 6244 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6245 | sl<g>\t%0,%2 |
6246 | sl<y>\t%0,%2" | |
65b1d8ea | 6247 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6248 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6249 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 6250 | |
65b1d8ea | 6251 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6252 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 6253 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6254 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6255 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 6256 | (const_int 0))) |
65b1d8ea | 6257 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 6258 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 6259 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 6260 | "@ |
3298c037 | 6261 | sl<g>r\t%0,%2 |
65b1d8ea | 6262 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6263 | sl<g>\t%0,%2 |
6264 | sl<y>\t%0,%2" | |
65b1d8ea | 6265 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6266 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6267 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9db1d521 | 6268 | |
65b1d8ea | 6269 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6270 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 6271 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6272 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6273 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
6274 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
3298c037 | 6275 | (minus:GPR (match_dup 1) (match_dup 2)))] |
5d880bd2 UW |
6276 | "s390_match_ccmode (insn, CCL3mode)" |
6277 | "@ | |
3298c037 | 6278 | sl<g>r\t%0,%2 |
65b1d8ea | 6279 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6280 | sl<g>\t%0,%2 |
6281 | sl<y>\t%0,%2" | |
65b1d8ea | 6282 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6283 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6284 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
5d880bd2 | 6285 | |
65b1d8ea | 6286 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6287 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6288 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6289 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6290 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 6291 | (const_int 0))) |
65b1d8ea | 6292 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 6293 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 6294 | "@ |
3298c037 | 6295 | sl<g>r\t%0,%2 |
65b1d8ea | 6296 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6297 | sl<g>\t%0,%2 |
6298 | sl<y>\t%0,%2" | |
65b1d8ea | 6299 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6300 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6301 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9381e3f1 | 6302 | |
9db1d521 | 6303 | |
65b1d8ea | 6304 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6305 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 6306 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6307 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6308 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
6309 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
5d880bd2 UW |
6310 | "s390_match_ccmode (insn, CCL3mode)" |
6311 | "@ | |
3298c037 | 6312 | sl<g>r\t%0,%2 |
65b1d8ea | 6313 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6314 | sl<g>\t%0,%2 |
6315 | sl<y>\t%0,%2" | |
65b1d8ea | 6316 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6317 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6318 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9381e3f1 | 6319 | |
7d2fd075 AK |
6320 | (define_insn "*subdi3_sign" |
6321 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6322 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
6323 | (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")))) | |
6324 | (clobber (reg:CC CC_REGNUM))] | |
e9e8efc9 | 6325 | "TARGET_Z14" |
7d2fd075 AK |
6326 | "sgh\t%0,%2" |
6327 | [(set_attr "op_type" "RXY")]) | |
6328 | ||
9db1d521 HP |
6329 | |
6330 | ; | |
609e7e80 | 6331 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6332 | ; |
6333 | ||
2de2b3f9 | 6334 | ; FIXME: (clobber (match_scratch:CC 3 "=c,c,c,X,X")) does not work - why? |
d46f24b6 | 6335 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 6336 | (define_insn "sub<mode>3" |
2de2b3f9 AK |
6337 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
6338 | (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v") | |
6339 | (match_operand:FP 2 "general_operand" "f,f,R,v,v"))) | |
ae156f85 | 6340 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 6341 | "TARGET_HARD_FLOAT" |
9db1d521 | 6342 | "@ |
62d3f261 AK |
6343 | s<xde>tr\t%0,%1,%2 |
6344 | s<xde>br\t%0,%2 | |
6e5b5de8 | 6345 | s<xde>b\t%0,%2 |
2de2b3f9 AK |
6346 | wfsdb\t%v0,%v1,%v2 |
6347 | wfssb\t%v0,%v1,%v2" | |
6348 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6349 | (set_attr "type" "fsimp<mode>") |
2de2b3f9 AK |
6350 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
6351 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 6352 | |
d46f24b6 | 6353 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6354 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 6355 | [(set (reg CC_REGNUM) |
62d3f261 | 6356 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
2de2b3f9 | 6357 | (match_operand:FP 2 "general_operand" "f,f,R")) |
609e7e80 | 6358 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6359 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 6360 | (minus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 6361 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6362 | "@ |
62d3f261 AK |
6363 | s<xde>tr\t%0,%1,%2 |
6364 | s<xde>br\t%0,%2 | |
f61a2c7d | 6365 | s<xde>b\t%0,%2" |
62d3f261 AK |
6366 | [(set_attr "op_type" "RRF,RRE,RXE") |
6367 | (set_attr "type" "fsimp<mode>") | |
6368 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6369 | |
d46f24b6 | 6370 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6371 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6372 | [(set (reg CC_REGNUM) |
62d3f261 AK |
6373 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
6374 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 6375 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6376 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 6377 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6378 | "@ |
62d3f261 AK |
6379 | s<xde>tr\t%0,%1,%2 |
6380 | s<xde>br\t%0,%2 | |
f61a2c7d | 6381 | s<xde>b\t%0,%2" |
62d3f261 AK |
6382 | [(set_attr "op_type" "RRF,RRE,RXE") |
6383 | (set_attr "type" "fsimp<mode>") | |
6384 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6385 | |
9db1d521 | 6386 | |
e69166de UW |
6387 | ;; |
6388 | ;;- Conditional add/subtract instructions. | |
6389 | ;; | |
6390 | ||
6391 | ; | |
9a91a21f | 6392 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
6393 | ; |
6394 | ||
a996720c UW |
6395 | ; the following 4 patterns are used when the result of an add with |
6396 | ; carry is checked for an overflow condition | |
6397 | ||
6398 | ; op1 + op2 + c < op1 | |
6399 | ||
6400 | ; alcr, alc, alcgr, alcg | |
6401 | (define_insn "*add<mode>3_alc_carry1_cc" | |
6402 | [(set (reg CC_REGNUM) | |
6403 | (compare | |
6404 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6405 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6406 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6407 | (match_dup 1))) |
6408 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6409 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
8cc6307c | 6410 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6411 | "@ |
6412 | alc<g>r\t%0,%2 | |
6413 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6414 | [(set_attr "op_type" "RRE,RXY") |
6415 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6416 | |
6417 | ; alcr, alc, alcgr, alcg | |
6418 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
6419 | [(set (reg CC_REGNUM) | |
6420 | (compare | |
6421 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6422 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6423 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6424 | (match_dup 1))) |
6425 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
8cc6307c | 6426 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6427 | "@ |
6428 | alc<g>r\t%0,%2 | |
6429 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6430 | [(set_attr "op_type" "RRE,RXY") |
6431 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6432 | |
6433 | ; op1 + op2 + c < op2 | |
6434 | ||
6435 | ; alcr, alc, alcgr, alcg | |
6436 | (define_insn "*add<mode>3_alc_carry2_cc" | |
6437 | [(set (reg CC_REGNUM) | |
6438 | (compare | |
6439 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6440 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6441 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6442 | (match_dup 2))) |
6443 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6444 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
8cc6307c | 6445 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6446 | "@ |
6447 | alc<g>r\t%0,%2 | |
6448 | alc<g>\t%0,%2" | |
6449 | [(set_attr "op_type" "RRE,RXY")]) | |
6450 | ||
6451 | ; alcr, alc, alcgr, alcg | |
6452 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
6453 | [(set (reg CC_REGNUM) | |
6454 | (compare | |
6455 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6456 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6457 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6458 | (match_dup 2))) |
6459 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
8cc6307c | 6460 | "s390_match_ccmode (insn, CCL1mode)" |
a996720c UW |
6461 | "@ |
6462 | alc<g>r\t%0,%2 | |
6463 | alc<g>\t%0,%2" | |
6464 | [(set_attr "op_type" "RRE,RXY")]) | |
6465 | ||
43a09b63 | 6466 | ; alcr, alc, alcgr, alcg |
9a91a21f | 6467 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 6468 | [(set (reg CC_REGNUM) |
e69166de | 6469 | (compare |
a94a76a7 UW |
6470 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6471 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6472 | (match_operand:GPR 2 "general_operand" "d,T")) |
e69166de | 6473 | (const_int 0))) |
9a91a21f | 6474 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 6475 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
8cc6307c | 6476 | "s390_match_ccmode (insn, CCLmode)" |
e69166de | 6477 | "@ |
9a91a21f AS |
6478 | alc<g>r\t%0,%2 |
6479 | alc<g>\t%0,%2" | |
e69166de UW |
6480 | [(set_attr "op_type" "RRE,RXY")]) |
6481 | ||
43a09b63 | 6482 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
6483 | (define_insn "*add<mode>3_alc" |
6484 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
6485 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6486 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6487 | (match_operand:GPR 2 "general_operand" "d,T"))) |
ae156f85 | 6488 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6489 | "" |
e69166de | 6490 | "@ |
9a91a21f AS |
6491 | alc<g>r\t%0,%2 |
6492 | alc<g>\t%0,%2" | |
e69166de UW |
6493 | [(set_attr "op_type" "RRE,RXY")]) |
6494 | ||
43a09b63 | 6495 | ; slbr, slb, slbgr, slbg |
9a91a21f | 6496 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 6497 | [(set (reg CC_REGNUM) |
e69166de | 6498 | (compare |
9a91a21f | 6499 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
3e4be43f | 6500 | (match_operand:GPR 2 "general_operand" "d,T")) |
9a91a21f | 6501 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 6502 | (const_int 0))) |
9a91a21f AS |
6503 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
6504 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
8cc6307c | 6505 | "s390_match_ccmode (insn, CCLmode)" |
e69166de | 6506 | "@ |
9a91a21f AS |
6507 | slb<g>r\t%0,%2 |
6508 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6509 | [(set_attr "op_type" "RRE,RXY") |
6510 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6511 | |
43a09b63 | 6512 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
6513 | (define_insn "*sub<mode>3_slb" |
6514 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
6515 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
3e4be43f | 6516 | (match_operand:GPR 2 "general_operand" "d,T")) |
9a91a21f | 6517 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 6518 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6519 | "" |
e69166de | 6520 | "@ |
9a91a21f AS |
6521 | slb<g>r\t%0,%2 |
6522 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6523 | [(set_attr "op_type" "RRE,RXY") |
6524 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6525 | |
9a91a21f AS |
6526 | (define_expand "add<mode>cc" |
6527 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 6528 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
6529 | (match_operand:GPR 2 "register_operand" "") |
6530 | (match_operand:GPR 3 "const_int_operand" "")] | |
8cc6307c | 6531 | "" |
9381e3f1 | 6532 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
f90b7a5a | 6533 | XEXP (operands[1], 0), XEXP (operands[1], 1), |
9381e3f1 | 6534 | operands[0], operands[2], |
5d880bd2 UW |
6535 | operands[3])) FAIL; DONE;") |
6536 | ||
6537 | ; | |
6538 | ; scond instruction pattern(s). | |
6539 | ; | |
6540 | ||
9a91a21f AS |
6541 | (define_insn_and_split "*scond<mode>" |
6542 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6543 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 6544 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6545 | "" |
5d880bd2 UW |
6546 | "#" |
6547 | "&& reload_completed" | |
6548 | [(set (match_dup 0) (const_int 0)) | |
6549 | (parallel | |
a94a76a7 UW |
6550 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
6551 | (match_dup 0))) | |
ae156f85 | 6552 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6553 | "") |
5d880bd2 | 6554 | |
9a91a21f AS |
6555 | (define_insn_and_split "*scond<mode>_neg" |
6556 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6557 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 6558 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 6559 | "" |
5d880bd2 UW |
6560 | "#" |
6561 | "&& reload_completed" | |
6562 | [(set (match_dup 0) (const_int 0)) | |
6563 | (parallel | |
9a91a21f AS |
6564 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
6565 | (match_dup 1))) | |
ae156f85 | 6566 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 6567 | (parallel |
9a91a21f | 6568 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 6569 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6570 | "") |
5d880bd2 | 6571 | |
5d880bd2 | 6572 | |
f90b7a5a | 6573 | (define_expand "cstore<mode>4" |
9a91a21f | 6574 | [(set (match_operand:SI 0 "register_operand" "") |
f90b7a5a PB |
6575 | (match_operator:SI 1 "s390_scond_operator" |
6576 | [(match_operand:GPR 2 "register_operand" "") | |
6577 | (match_operand:GPR 3 "general_operand" "")]))] | |
8cc6307c | 6578 | "" |
f90b7a5a | 6579 | "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], |
5d880bd2 UW |
6580 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
6581 | ||
f90b7a5a | 6582 | (define_expand "cstorecc4" |
69950452 | 6583 | [(parallel |
f90b7a5a PB |
6584 | [(set (match_operand:SI 0 "register_operand" "") |
6585 | (match_operator:SI 1 "s390_eqne_operator" | |
3ea685e7 | 6586 | [(match_operand 2 "cc_reg_operand") |
f90b7a5a | 6587 | (match_operand 3 "const0_operand")])) |
69950452 AS |
6588 | (clobber (reg:CC CC_REGNUM))])] |
6589 | "" | |
3ea685e7 DV |
6590 | "machine_mode mode = GET_MODE (operands[2]); |
6591 | if (TARGET_Z196) | |
6592 | { | |
6593 | rtx cond, ite; | |
6594 | ||
6595 | if (GET_CODE (operands[1]) == NE) | |
6596 | cond = gen_rtx_NE (VOIDmode, operands[2], const0_rtx); | |
6597 | else | |
6598 | cond = gen_rtx_EQ (VOIDmode, operands[2], const0_rtx); | |
6599 | ite = gen_rtx_IF_THEN_ELSE (SImode, cond, const1_rtx, const0_rtx); | |
6600 | emit_insn (gen_rtx_SET (operands[0], ite)); | |
6601 | } | |
6602 | else | |
6603 | { | |
6604 | if (mode != CCZ1mode) | |
6605 | FAIL; | |
6606 | emit_insn (gen_sne (operands[0], operands[2])); | |
6607 | if (GET_CODE (operands[1]) == EQ) | |
6608 | emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); | |
6609 | } | |
f90b7a5a | 6610 | DONE;") |
69950452 | 6611 | |
f90b7a5a | 6612 | (define_insn_and_split "sne" |
69950452 | 6613 | [(set (match_operand:SI 0 "register_operand" "=d") |
9381e3f1 | 6614 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
6615 | (const_int 0))) |
6616 | (clobber (reg:CC CC_REGNUM))] | |
6617 | "" | |
6618 | "#" | |
6619 | "reload_completed" | |
6620 | [(parallel | |
6621 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
6622 | (clobber (reg:CC CC_REGNUM))])]) | |
6623 | ||
e69166de | 6624 | |
65b1d8ea AK |
6625 | ;; |
6626 | ;; - Conditional move instructions (introduced with z196) | |
6627 | ;; | |
6628 | ||
6629 | (define_expand "mov<mode>cc" | |
6630 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
6631 | (if_then_else:GPR (match_operand 1 "comparison_operator" "") | |
88e845c0 RD |
6632 | (match_operand:GPR 2 "loc_operand" "") |
6633 | (match_operand:GPR 3 "loc_operand" "")))] | |
65b1d8ea | 6634 | "TARGET_Z196" |
7477de01 | 6635 | { |
88e845c0 RD |
6636 | if (!TARGET_Z13 && CONSTANT_P (operands[2])) |
6637 | operands[2] = force_reg (<MODE>mode, operands[2]); | |
6638 | ||
6639 | if (!TARGET_Z13 && CONSTANT_P (operands[3])) | |
6640 | operands[3] = force_reg (<MODE>mode, operands[3]); | |
6641 | ||
7477de01 AK |
6642 | /* Emit the comparison insn in case we do not already have a comparison result. */ |
6643 | if (!s390_comparison (operands[1], VOIDmode)) | |
6644 | operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
6645 | XEXP (operands[1], 0), | |
6646 | XEXP (operands[1], 1)); | |
6647 | }) | |
65b1d8ea | 6648 | |
d8928886 RD |
6649 | ;; |
6650 | ;; - We do not have instructions for QImode or HImode but still | |
6651 | ;; enable load on condition/if conversion for them. | |
6652 | (define_expand "mov<mode>cc" | |
6653 | [(set (match_operand:HQI 0 "nonimmediate_operand" "") | |
6654 | (if_then_else:HQI (match_operand 1 "comparison_operator" "") | |
6655 | (match_operand:HQI 2 "loc_operand" "") | |
6656 | (match_operand:HQI 3 "loc_operand" "")))] | |
6657 | "TARGET_Z196" | |
6658 | { | |
6659 | /* Emit the comparison insn in case we do not already have a comparison | |
6660 | result. */ | |
6661 | if (!s390_comparison (operands[1], VOIDmode)) | |
6662 | operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
6663 | XEXP (operands[1], 0), | |
6664 | XEXP (operands[1], 1)); | |
6665 | ||
6666 | rtx then = operands[2]; | |
6667 | rtx els = operands[3]; | |
6668 | ||
6669 | if ((!TARGET_Z13 && CONSTANT_P (then)) || MEM_P (then)) | |
6670 | then = force_reg (<MODE>mode, then); | |
6671 | if ((!TARGET_Z13 && CONSTANT_P (els)) || MEM_P (els)) | |
6672 | els = force_reg (<MODE>mode, els); | |
6673 | ||
6674 | if (!CONSTANT_P (then)) | |
6675 | then = simplify_gen_subreg (E_SImode, then, <MODE>mode, 0); | |
6676 | if (!CONSTANT_P (els)) | |
6677 | els = simplify_gen_subreg (E_SImode, els, <MODE>mode, 0); | |
6678 | ||
6679 | rtx tmp_target = gen_reg_rtx (E_SImode); | |
6680 | emit_insn (gen_movsicc (tmp_target, operands[1], then, els)); | |
6681 | emit_move_insn (operands[0], gen_lowpart (<MODE>mode, tmp_target)); | |
6682 | DONE; | |
6683 | }) | |
6684 | ||
6685 | ||
6686 | ||
bf749919 | 6687 | ; locr, loc, stoc, locgr, locg, stocg, lochi, locghi |
561f6312 AK |
6688 | (define_insn "*mov<mode>cc" |
6689 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S,S") | |
65b1d8ea AK |
6690 | (if_then_else:GPR |
6691 | (match_operator 1 "s390_comparison" | |
561f6312 | 6692 | [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c") |
5a3fe9b6 | 6693 | (match_operand 5 "const_int_operand" "")]) |
561f6312 AK |
6694 | (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0") |
6695 | (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d")))] | |
65b1d8ea AK |
6696 | "TARGET_Z196" |
6697 | "@ | |
6698 | loc<g>r%C1\t%0,%3 | |
6699 | loc<g>r%D1\t%0,%4 | |
a6510374 AK |
6700 | loc<g>%C1\t%0,%3 |
6701 | loc<g>%D1\t%0,%4 | |
bf749919 DV |
6702 | loc<g>hi%C1\t%0,%h3 |
6703 | loc<g>hi%D1\t%0,%h4 | |
a6510374 | 6704 | stoc<g>%C1\t%3,%0 |
561f6312 AK |
6705 | stoc<g>%D1\t%4,%0" |
6706 | [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY") | |
6707 | (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*")]) | |
65b1d8ea | 6708 | |
9db1d521 HP |
6709 | ;; |
6710 | ;;- Multiply instructions. | |
6711 | ;; | |
6712 | ||
4023fb28 UW |
6713 | ; |
6714 | ; muldi3 instruction pattern(s). | |
6715 | ; | |
9db1d521 | 6716 | |
7d2fd075 AK |
6717 | (define_expand "muldi3" |
6718 | [(parallel | |
6719 | [(set (match_operand:DI 0 "register_operand") | |
6720 | (mult:DI (match_operand:DI 1 "nonimmediate_operand") | |
6721 | (match_operand:DI 2 "general_operand"))) | |
6722 | (clobber (reg:CC CC_REGNUM))])] | |
6723 | "TARGET_ZARCH") | |
6724 | ||
07893d4f UW |
6725 | (define_insn "*muldi3_sign" |
6726 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 6727 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 6728 | (match_operand:DI 1 "register_operand" "0,0")))] |
9602b6a1 | 6729 | "TARGET_ZARCH" |
07893d4f | 6730 | "@ |
d40c829f UW |
6731 | msgfr\t%0,%2 |
6732 | msgf\t%0,%2" | |
963fc8d0 AK |
6733 | [(set_attr "op_type" "RRE,RXY") |
6734 | (set_attr "type" "imuldi")]) | |
07893d4f | 6735 | |
7d2fd075 AK |
6736 | (define_insn "*muldi3" |
6737 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d,d") | |
6738 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0,0,0") | |
6739 | (match_operand:DI 2 "general_operand" "d,d,K,T,Os"))) | |
6740 | (clobber (match_scratch:CC 3 "=X,c,X,X,X"))] | |
9602b6a1 | 6741 | "TARGET_ZARCH" |
9db1d521 | 6742 | "@ |
d40c829f | 6743 | msgr\t%0,%2 |
7d2fd075 | 6744 | msgrkc\t%0,%1,%2 |
d40c829f | 6745 | mghi\t%0,%h2 |
963fc8d0 AK |
6746 | msg\t%0,%2 |
6747 | msgfi\t%0,%2" | |
7d2fd075 | 6748 | [(set_attr "op_type" "RRE,RRF,RI,RXY,RIL") |
963fc8d0 | 6749 | (set_attr "type" "imuldi") |
e9e8efc9 | 6750 | (set_attr "cpu_facility" "*,z14,*,*,z10")]) |
7d2fd075 AK |
6751 | |
6752 | (define_insn "mulditi3" | |
6753 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6754 | (mult:TI (sign_extend:TI | |
6755 | (match_operand:DI 1 "register_operand" "%d,0")) | |
6756 | (sign_extend:TI | |
6757 | (match_operand:DI 2 "nonimmediate_operand" " d,T"))))] | |
e9e8efc9 | 6758 | "TARGET_Z14" |
7d2fd075 AK |
6759 | "@ |
6760 | mgrk\t%0,%1,%2 | |
6761 | mg\t%0,%2" | |
6762 | [(set_attr "op_type" "RRF,RXY")]) | |
6763 | ||
6764 | ; Combine likes op1 and op2 to be swapped sometimes. | |
6765 | (define_insn "mulditi3_2" | |
6766 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6767 | (mult:TI (sign_extend:TI | |
6768 | (match_operand:DI 1 "nonimmediate_operand" "%d,T")) | |
6769 | (sign_extend:TI | |
6770 | (match_operand:DI 2 "register_operand" " d,0"))))] | |
e9e8efc9 | 6771 | "TARGET_Z14" |
7d2fd075 AK |
6772 | "@ |
6773 | mgrk\t%0,%1,%2 | |
6774 | mg\t%0,%1" | |
6775 | [(set_attr "op_type" "RRF,RXY")]) | |
6776 | ||
6777 | (define_insn "*muldi3_sign" | |
6778 | [(set (match_operand:DI 0 "register_operand" "=d") | |
6779 | (mult:DI (sign_extend:DI (match_operand:HI 2 "memory_operand" "T")) | |
6780 | (match_operand:DI 1 "register_operand" "0")))] | |
e9e8efc9 | 6781 | "TARGET_Z14" |
7d2fd075 AK |
6782 | "mgh\t%0,%2" |
6783 | [(set_attr "op_type" "RXY")]) | |
6784 | ||
f2d3c02a | 6785 | |
9db1d521 HP |
6786 | ; |
6787 | ; mulsi3 instruction pattern(s). | |
6788 | ; | |
6789 | ||
7d2fd075 AK |
6790 | (define_expand "mulsi3" |
6791 | [(parallel | |
6792 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") | |
6793 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6794 | (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) | |
6795 | (clobber (reg:CC CC_REGNUM))])] | |
6796 | "") | |
6797 | ||
f1e77d83 | 6798 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
6799 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6800 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
6801 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 6802 | "" |
963fc8d0 AK |
6803 | "@ |
6804 | mh\t%0,%2 | |
6805 | mhy\t%0,%2" | |
6806 | [(set_attr "op_type" "RX,RXY") | |
6807 | (set_attr "type" "imulhi") | |
6808 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 6809 | |
7d2fd075 AK |
6810 | (define_insn "*mulsi3" |
6811 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d,d") | |
6812 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
6813 | (match_operand:SI 2 "general_operand" "d,d,K,R,T,Os"))) | |
6814 | (clobber (match_scratch:CC 3 "=X,c,X,X,X,X"))] | |
9db1d521 HP |
6815 | "" |
6816 | "@ | |
d40c829f | 6817 | msr\t%0,%2 |
7d2fd075 | 6818 | msrkc\t%0,%1,%2 |
d40c829f UW |
6819 | mhi\t%0,%h2 |
6820 | ms\t%0,%2 | |
963fc8d0 AK |
6821 | msy\t%0,%2 |
6822 | msfi\t%0,%2" | |
7d2fd075 AK |
6823 | [(set_attr "op_type" "RRE,RRF,RI,RX,RXY,RIL") |
6824 | (set_attr "type" "imulsi,*,imulhi,imulsi,imulsi,imulsi") | |
e9e8efc9 | 6825 | (set_attr "cpu_facility" "*,z14,*,*,longdisp,z10")]) |
9db1d521 | 6826 | |
4023fb28 UW |
6827 | ; |
6828 | ; mulsidi3 instruction pattern(s). | |
6829 | ; | |
6830 | ||
f1e77d83 | 6831 | (define_insn "mulsidi3" |
963fc8d0 | 6832 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 6833 | (mult:DI (sign_extend:DI |
963fc8d0 | 6834 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 6835 | (sign_extend:DI |
963fc8d0 | 6836 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
9602b6a1 | 6837 | "!TARGET_ZARCH" |
f1e77d83 UW |
6838 | "@ |
6839 | mr\t%0,%2 | |
963fc8d0 AK |
6840 | m\t%0,%2 |
6841 | mfy\t%0,%2" | |
6842 | [(set_attr "op_type" "RR,RX,RXY") | |
6843 | (set_attr "type" "imulsi") | |
6844 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 6845 | |
f1e77d83 | 6846 | ; |
6e0d70c9 | 6847 | ; umul instruction pattern(s). |
f1e77d83 | 6848 | ; |
c7453384 | 6849 | |
6e0d70c9 AK |
6850 | ; mlr, ml, mlgr, mlg |
6851 | (define_insn "umul<dwh><mode>3" | |
3e4be43f | 6852 | [(set (match_operand:DW 0 "register_operand" "=d,d") |
6e0d70c9 | 6853 | (mult:DW (zero_extend:DW |
3e4be43f | 6854 | (match_operand:<DWH> 1 "register_operand" "%0,0")) |
6e0d70c9 | 6855 | (zero_extend:DW |
3e4be43f | 6856 | (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))] |
8cc6307c | 6857 | "" |
f1e77d83 | 6858 | "@ |
6e0d70c9 AK |
6859 | ml<tg>r\t%0,%2 |
6860 | ml<tg>\t%0,%2" | |
f1e77d83 | 6861 | [(set_attr "op_type" "RRE,RXY") |
6e0d70c9 | 6862 | (set_attr "type" "imul<dwh>")]) |
c7453384 | 6863 | |
9db1d521 | 6864 | ; |
609e7e80 | 6865 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6866 | ; |
6867 | ||
9381e3f1 | 6868 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 6869 | (define_insn "mul<mode>3" |
2de2b3f9 AK |
6870 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
6871 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v,v") | |
6872 | (match_operand:FP 2 "general_operand" "f,f,R,v,v")))] | |
142cd70f | 6873 | "TARGET_HARD_FLOAT" |
9db1d521 | 6874 | "@ |
62d3f261 AK |
6875 | m<xdee>tr\t%0,%1,%2 |
6876 | m<xdee>br\t%0,%2 | |
6e5b5de8 | 6877 | m<xdee>b\t%0,%2 |
2de2b3f9 AK |
6878 | wfmdb\t%v0,%v1,%v2 |
6879 | wfmsb\t%v0,%v1,%v2" | |
6880 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6881 | (set_attr "type" "fmul<mode>") |
2de2b3f9 AK |
6882 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
6883 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 6884 | |
9381e3f1 | 6885 | ; madbr, maebr, maxb, madb, maeb |
d7ecb504 | 6886 | (define_insn "fma<mode>4" |
2de2b3f9 AK |
6887 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v") |
6888 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v") | |
6889 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v") | |
6890 | (match_operand:DSF 3 "register_operand" "0,0,v,v")))] | |
d7ecb504 | 6891 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6892 | "@ |
f61a2c7d | 6893 | ma<xde>br\t%0,%1,%2 |
6e5b5de8 | 6894 | ma<xde>b\t%0,%1,%2 |
2de2b3f9 AK |
6895 | wfmadb\t%v0,%v1,%v2,%v3 |
6896 | wfmasb\t%v0,%v1,%v2,%v3" | |
6897 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6898 | (set_attr "type" "fmadd<mode>") |
2de2b3f9 AK |
6899 | (set_attr "cpu_facility" "*,*,vx,vxe") |
6900 | (set_attr "enabled" "*,*,<DF>,<SF>")]) | |
a1b892b5 | 6901 | |
43a09b63 | 6902 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
d7ecb504 | 6903 | (define_insn "fms<mode>4" |
2de2b3f9 AK |
6904 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v,v") |
6905 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v,v") | |
6906 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v,v") | |
6907 | (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v,v"))))] | |
d7ecb504 | 6908 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6909 | "@ |
f61a2c7d | 6910 | ms<xde>br\t%0,%1,%2 |
6e5b5de8 | 6911 | ms<xde>b\t%0,%1,%2 |
2de2b3f9 AK |
6912 | wfmsdb\t%v0,%v1,%v2,%v3 |
6913 | wfmssb\t%v0,%v1,%v2,%v3" | |
6914 | [(set_attr "op_type" "RRE,RXE,VRR,VRR") | |
6e5b5de8 | 6915 | (set_attr "type" "fmadd<mode>") |
2de2b3f9 AK |
6916 | (set_attr "cpu_facility" "*,*,vx,vxe") |
6917 | (set_attr "enabled" "*,*,<DF>,<SF>")]) | |
9db1d521 HP |
6918 | |
6919 | ;; | |
6920 | ;;- Divide and modulo instructions. | |
6921 | ;; | |
6922 | ||
6923 | ; | |
4023fb28 | 6924 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
6925 | ; |
6926 | ||
4023fb28 UW |
6927 | (define_expand "divmoddi4" |
6928 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 6929 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
6930 | (match_operand:DI 2 "general_operand" ""))) |
6931 | (set (match_operand:DI 3 "general_operand" "") | |
6932 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
6933 | (clobber (match_dup 4))] | |
9602b6a1 | 6934 | "TARGET_ZARCH" |
9db1d521 | 6935 | { |
d8485bdb TS |
6936 | rtx div_equal, mod_equal; |
6937 | rtx_insn *insn; | |
4023fb28 UW |
6938 | |
6939 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
6940 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
6941 | |
6942 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 6943 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
6944 | |
6945 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6946 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6947 | |
6948 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6949 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6950 | |
9db1d521 | 6951 | DONE; |
10bbf137 | 6952 | }) |
9db1d521 HP |
6953 | |
6954 | (define_insn "divmodtidi3" | |
4023fb28 UW |
6955 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
6956 | (ior:TI | |
4023fb28 UW |
6957 | (ashift:TI |
6958 | (zero_extend:TI | |
5665e398 | 6959 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6960 | (match_operand:DI 2 "general_operand" "d,T"))) |
5665e398 UW |
6961 | (const_int 64)) |
6962 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9602b6a1 | 6963 | "TARGET_ZARCH" |
9db1d521 | 6964 | "@ |
d40c829f UW |
6965 | dsgr\t%0,%2 |
6966 | dsg\t%0,%2" | |
d3632d41 | 6967 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6968 | (set_attr "type" "idiv")]) |
9db1d521 | 6969 | |
4023fb28 UW |
6970 | (define_insn "divmodtisi3" |
6971 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6972 | (ior:TI | |
4023fb28 UW |
6973 | (ashift:TI |
6974 | (zero_extend:TI | |
5665e398 | 6975 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 6976 | (sign_extend:DI |
3e4be43f | 6977 | (match_operand:SI 2 "nonimmediate_operand" "d,T")))) |
5665e398 UW |
6978 | (const_int 64)) |
6979 | (zero_extend:TI | |
6980 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9602b6a1 | 6981 | "TARGET_ZARCH" |
4023fb28 | 6982 | "@ |
d40c829f UW |
6983 | dsgfr\t%0,%2 |
6984 | dsgf\t%0,%2" | |
d3632d41 | 6985 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6986 | (set_attr "type" "idiv")]) |
9db1d521 | 6987 | |
4023fb28 UW |
6988 | ; |
6989 | ; udivmoddi4 instruction pattern(s). | |
6990 | ; | |
9db1d521 | 6991 | |
4023fb28 UW |
6992 | (define_expand "udivmoddi4" |
6993 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
6994 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
6995 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
6996 | (set (match_operand:DI 3 "general_operand" "") | |
6997 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
6998 | (clobber (match_dup 4))] | |
9602b6a1 | 6999 | "TARGET_ZARCH" |
9db1d521 | 7000 | { |
d8485bdb TS |
7001 | rtx div_equal, mod_equal, equal; |
7002 | rtx_insn *insn; | |
4023fb28 UW |
7003 | |
7004 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
7005 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
7006 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
7007 | gen_rtx_ASHIFT (TImode, |
7008 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
7009 | GEN_INT (64)), |
7010 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
7011 | |
7012 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 7013 | emit_clobber (operands[4]); |
4023fb28 UW |
7014 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
7015 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 7016 | |
4023fb28 | 7017 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 7018 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
7019 | |
7020 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 7021 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
7022 | |
7023 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 7024 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 7025 | |
9db1d521 | 7026 | DONE; |
10bbf137 | 7027 | }) |
9db1d521 HP |
7028 | |
7029 | (define_insn "udivmodtidi3" | |
4023fb28 | 7030 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 7031 | (ior:TI |
5665e398 UW |
7032 | (ashift:TI |
7033 | (zero_extend:TI | |
7034 | (truncate:DI | |
2f7e5a0d EC |
7035 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
7036 | (zero_extend:TI | |
3e4be43f | 7037 | (match_operand:DI 2 "nonimmediate_operand" "d,T"))))) |
5665e398 UW |
7038 | (const_int 64)) |
7039 | (zero_extend:TI | |
7040 | (truncate:DI | |
7041 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9602b6a1 | 7042 | "TARGET_ZARCH" |
9db1d521 | 7043 | "@ |
d40c829f UW |
7044 | dlgr\t%0,%2 |
7045 | dlg\t%0,%2" | |
d3632d41 | 7046 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 7047 | (set_attr "type" "idiv")]) |
9db1d521 HP |
7048 | |
7049 | ; | |
4023fb28 | 7050 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
7051 | ; |
7052 | ||
4023fb28 UW |
7053 | (define_expand "divmodsi4" |
7054 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
7055 | (div:SI (match_operand:SI 1 "general_operand" "") | |
7056 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
7057 | (set (match_operand:SI 3 "general_operand" "") | |
7058 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
7059 | (clobber (match_dup 4))] | |
9602b6a1 | 7060 | "!TARGET_ZARCH" |
9db1d521 | 7061 | { |
d8485bdb TS |
7062 | rtx div_equal, mod_equal, equal; |
7063 | rtx_insn *insn; | |
4023fb28 UW |
7064 | |
7065 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
7066 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
7067 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
7068 | gen_rtx_ASHIFT (DImode, |
7069 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
7070 | GEN_INT (32)), |
7071 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
7072 | |
7073 | operands[4] = gen_reg_rtx(DImode); | |
7074 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 7075 | |
4023fb28 | 7076 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 7077 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
7078 | |
7079 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 7080 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
7081 | |
7082 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 7083 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 7084 | |
9db1d521 | 7085 | DONE; |
10bbf137 | 7086 | }) |
9db1d521 HP |
7087 | |
7088 | (define_insn "divmoddisi3" | |
4023fb28 | 7089 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 7090 | (ior:DI |
5665e398 UW |
7091 | (ashift:DI |
7092 | (zero_extend:DI | |
7093 | (truncate:SI | |
2f7e5a0d EC |
7094 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
7095 | (sign_extend:DI | |
5665e398 UW |
7096 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
7097 | (const_int 32)) | |
7098 | (zero_extend:DI | |
7099 | (truncate:SI | |
7100 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 7101 | "!TARGET_ZARCH" |
9db1d521 | 7102 | "@ |
d40c829f UW |
7103 | dr\t%0,%2 |
7104 | d\t%0,%2" | |
9db1d521 | 7105 | [(set_attr "op_type" "RR,RX") |
077dab3b | 7106 | (set_attr "type" "idiv")]) |
9db1d521 HP |
7107 | |
7108 | ; | |
7109 | ; udivsi3 and umodsi3 instruction pattern(s). | |
7110 | ; | |
7111 | ||
f1e77d83 UW |
7112 | (define_expand "udivmodsi4" |
7113 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
7114 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
7115 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
7116 | (set (match_operand:SI 3 "general_operand" "") | |
7117 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
7118 | (clobber (match_dup 4))] | |
8cc6307c | 7119 | "!TARGET_ZARCH" |
f1e77d83 | 7120 | { |
d8485bdb TS |
7121 | rtx div_equal, mod_equal, equal; |
7122 | rtx_insn *insn; | |
f1e77d83 UW |
7123 | |
7124 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
7125 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
7126 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
7127 | gen_rtx_ASHIFT (DImode, |
7128 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
7129 | GEN_INT (32)), |
7130 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
7131 | |
7132 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 7133 | emit_clobber (operands[4]); |
f1e77d83 UW |
7134 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
7135 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 7136 | |
f1e77d83 | 7137 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 7138 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
7139 | |
7140 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 7141 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
7142 | |
7143 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 7144 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
7145 | |
7146 | DONE; | |
7147 | }) | |
7148 | ||
7149 | (define_insn "udivmoddisi3" | |
7150 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 7151 | (ior:DI |
5665e398 UW |
7152 | (ashift:DI |
7153 | (zero_extend:DI | |
7154 | (truncate:SI | |
2f7e5a0d EC |
7155 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
7156 | (zero_extend:DI | |
3e4be43f | 7157 | (match_operand:SI 2 "nonimmediate_operand" "d,T"))))) |
5665e398 UW |
7158 | (const_int 32)) |
7159 | (zero_extend:DI | |
7160 | (truncate:SI | |
7161 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
8cc6307c | 7162 | "!TARGET_ZARCH" |
f1e77d83 UW |
7163 | "@ |
7164 | dlr\t%0,%2 | |
7165 | dl\t%0,%2" | |
7166 | [(set_attr "op_type" "RRE,RXY") | |
7167 | (set_attr "type" "idiv")]) | |
4023fb28 | 7168 | |
9db1d521 | 7169 | ; |
f5905b37 | 7170 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
7171 | ; |
7172 | ||
609e7e80 | 7173 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 7174 | (define_insn "div<mode>3" |
2de2b3f9 AK |
7175 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v,v") |
7176 | (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v,v") | |
7177 | (match_operand:FP 2 "general_operand" "f,f,R,v,v")))] | |
142cd70f | 7178 | "TARGET_HARD_FLOAT" |
9db1d521 | 7179 | "@ |
62d3f261 AK |
7180 | d<xde>tr\t%0,%1,%2 |
7181 | d<xde>br\t%0,%2 | |
6e5b5de8 | 7182 | d<xde>b\t%0,%2 |
2de2b3f9 AK |
7183 | wfddb\t%v0,%v1,%v2 |
7184 | wfdsb\t%v0,%v1,%v2" | |
7185 | [(set_attr "op_type" "RRF,RRE,RXE,VRR,VRR") | |
6e5b5de8 | 7186 | (set_attr "type" "fdiv<mode>") |
2de2b3f9 AK |
7187 | (set_attr "cpu_facility" "*,*,*,vx,vxe") |
7188 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DF>,<SF>")]) | |
9db1d521 | 7189 | |
9db1d521 HP |
7190 | |
7191 | ;; | |
7192 | ;;- And instructions. | |
7193 | ;; | |
7194 | ||
047d35ed AS |
7195 | (define_expand "and<mode>3" |
7196 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7197 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7198 | (match_operand:INT 2 "general_operand" ""))) | |
7199 | (clobber (reg:CC CC_REGNUM))] | |
7200 | "" | |
7201 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
7202 | ||
9db1d521 HP |
7203 | ; |
7204 | ; anddi3 instruction pattern(s). | |
7205 | ; | |
7206 | ||
7207 | (define_insn "*anddi3_cc" | |
ae156f85 | 7208 | [(set (reg CC_REGNUM) |
e3140518 | 7209 | (compare |
3e4be43f | 7210 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") |
c2586c82 | 7211 | (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) |
e3140518 | 7212 | (const_int 0))) |
3e4be43f | 7213 | (set (match_operand:DI 0 "register_operand" "=d,d,d, d") |
9db1d521 | 7214 | (and:DI (match_dup 1) (match_dup 2)))] |
e3140518 | 7215 | "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" |
9db1d521 | 7216 | "@ |
d40c829f | 7217 | ngr\t%0,%2 |
65b1d8ea | 7218 | ngrk\t%0,%1,%2 |
e3140518 RH |
7219 | ng\t%0,%2 |
7220 | risbg\t%0,%1,%s2,128+%e2,0" | |
7221 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
7222 | (set_attr "cpu_facility" "*,z196,*,z10") | |
7223 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7224 | |
7225 | (define_insn "*anddi3_cconly" | |
ae156f85 | 7226 | [(set (reg CC_REGNUM) |
e3140518 | 7227 | (compare |
3e4be43f | 7228 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") |
c2586c82 | 7229 | (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) |
9db1d521 | 7230 | (const_int 0))) |
3e4be43f | 7231 | (clobber (match_scratch:DI 0 "=d,d,d, d"))] |
e3140518 RH |
7232 | "TARGET_ZARCH |
7233 | && s390_match_ccmode(insn, CCTmode) | |
68f9c5e2 UW |
7234 | /* Do not steal TM patterns. */ |
7235 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 7236 | "@ |
d40c829f | 7237 | ngr\t%0,%2 |
65b1d8ea | 7238 | ngrk\t%0,%1,%2 |
e3140518 RH |
7239 | ng\t%0,%2 |
7240 | risbg\t%0,%1,%s2,128+%e2,0" | |
7241 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
7242 | (set_attr "cpu_facility" "*,z196,*,z10") | |
7243 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 7244 | |
3af8e996 | 7245 | (define_insn "*anddi3" |
65b1d8ea | 7246 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 7247 | "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q") |
e3140518 RH |
7248 | (and:DI |
7249 | (match_operand:DI 1 "nonimmediate_operand" | |
3e4be43f | 7250 | "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0") |
e3140518 | 7251 | (match_operand:DI 2 "general_operand" |
c2586c82 | 7252 | "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDw,NxQDF,Q"))) |
ec24698e | 7253 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7254 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7255 | "@ |
7256 | # | |
7257 | # | |
7258 | nihh\t%0,%j2 | |
7259 | nihl\t%0,%j2 | |
7260 | nilh\t%0,%j2 | |
7261 | nill\t%0,%j2 | |
7262 | nihf\t%0,%m2 | |
7263 | nilf\t%0,%m2 | |
7264 | ngr\t%0,%2 | |
65b1d8ea | 7265 | ngrk\t%0,%1,%2 |
ec24698e | 7266 | ng\t%0,%2 |
e3140518 | 7267 | risbg\t%0,%1,%s2,128+%e2,0 |
ec24698e UW |
7268 | # |
7269 | #" | |
e3140518 RH |
7270 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS") |
7271 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*") | |
9381e3f1 WG |
7272 | (set_attr "z10prop" "*, |
7273 | *, | |
7274 | z10_super_E1, | |
7275 | z10_super_E1, | |
7276 | z10_super_E1, | |
7277 | z10_super_E1, | |
7278 | z10_super_E1, | |
7279 | z10_super_E1, | |
7280 | z10_super_E1, | |
65b1d8ea | 7281 | *, |
9381e3f1 | 7282 | z10_super_E1, |
e3140518 | 7283 | z10_super_E1, |
9381e3f1 WG |
7284 | *, |
7285 | *")]) | |
0dfa6c5e UW |
7286 | |
7287 | (define_split | |
7288 | [(set (match_operand:DI 0 "s_operand" "") | |
7289 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7290 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7291 | "reload_completed" |
7292 | [(parallel | |
7293 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7294 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7295 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7296 | |
1a2e356e | 7297 | ;; These two are what combine generates for (ashift (zero_extract)). |
64c744b9 | 7298 | (define_insn "*extzv_<mode>_srl<clobbercc_or_nocc>" |
1a2e356e RH |
7299 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7300 | (and:GPR (lshiftrt:GPR | |
7301 | (match_operand:GPR 1 "register_operand" "d") | |
7302 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 7303 | (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] |
64c744b9 | 7304 | "<z10_or_zEC12_cond> |
1a2e356e RH |
7305 | /* Note that even for the SImode pattern, the rotate is always DImode. */ |
7306 | && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]), | |
7307 | INTVAL (operands[3]))" | |
64c744b9 | 7308 | "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2" |
1a2e356e RH |
7309 | [(set_attr "op_type" "RIE") |
7310 | (set_attr "z10prop" "z10_super_E1")]) | |
7311 | ||
64c744b9 | 7312 | (define_insn "*extzv_<mode>_sll<clobbercc_or_nocc>" |
1a2e356e RH |
7313 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7314 | (and:GPR (ashift:GPR | |
7315 | (match_operand:GPR 1 "register_operand" "d") | |
7316 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 7317 | (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] |
64c744b9 | 7318 | "<z10_or_zEC12_cond> |
1a2e356e RH |
7319 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]), |
7320 | INTVAL (operands[3]))" | |
64c744b9 | 7321 | "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,%2" |
1a2e356e RH |
7322 | [(set_attr "op_type" "RIE") |
7323 | (set_attr "z10prop" "z10_super_E1")]) | |
7324 | ||
9db1d521 HP |
7325 | |
7326 | ; | |
7327 | ; andsi3 instruction pattern(s). | |
7328 | ; | |
7329 | ||
7330 | (define_insn "*andsi3_cc" | |
ae156f85 | 7331 | [(set (reg CC_REGNUM) |
e3140518 RH |
7332 | (compare |
7333 | (and:SI | |
7334 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7335 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7336 | (const_int 0))) | |
7337 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d") | |
9db1d521 HP |
7338 | (and:SI (match_dup 1) (match_dup 2)))] |
7339 | "s390_match_ccmode(insn, CCTmode)" | |
7340 | "@ | |
ec24698e | 7341 | nilf\t%0,%o2 |
d40c829f | 7342 | nr\t%0,%2 |
65b1d8ea | 7343 | nrk\t%0,%1,%2 |
d40c829f | 7344 | n\t%0,%2 |
e3140518 RH |
7345 | ny\t%0,%2 |
7346 | risbg\t%0,%1,%t2,128+%f2,0" | |
7347 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
3e4be43f | 7348 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") |
e3140518 RH |
7349 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
7350 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7351 | |
7352 | (define_insn "*andsi3_cconly" | |
ae156f85 | 7353 | [(set (reg CC_REGNUM) |
e3140518 RH |
7354 | (compare |
7355 | (and:SI | |
7356 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7357 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7358 | (const_int 0))) | |
7359 | (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))] | |
68f9c5e2 UW |
7360 | "s390_match_ccmode(insn, CCTmode) |
7361 | /* Do not steal TM patterns. */ | |
7362 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 7363 | "@ |
ec24698e | 7364 | nilf\t%0,%o2 |
d40c829f | 7365 | nr\t%0,%2 |
65b1d8ea | 7366 | nrk\t%0,%1,%2 |
d40c829f | 7367 | n\t%0,%2 |
e3140518 RH |
7368 | ny\t%0,%2 |
7369 | risbg\t%0,%1,%t2,128+%f2,0" | |
7370 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
3e4be43f | 7371 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") |
65b1d8ea | 7372 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
e3140518 | 7373 | z10_super_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 7374 | |
f19a9af7 | 7375 | (define_insn "*andsi3_zarch" |
65b1d8ea | 7376 | [(set (match_operand:SI 0 "nonimmediate_operand" |
e3140518 | 7377 | "=d,d, d, d, d,d,d,d,d, d, AQ,Q") |
0dfa6c5e | 7378 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
e3140518 | 7379 | "%d,o, 0, 0, 0,0,d,0,0, d, 0,0") |
0dfa6c5e | 7380 | (match_operand:SI 2 "general_operand" |
c2586c82 | 7381 | " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSw,NxQSF,Q"))) |
ae156f85 | 7382 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7383 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7384 | "@ |
f19a9af7 AK |
7385 | # |
7386 | # | |
7387 | nilh\t%0,%j2 | |
2f7e5a0d | 7388 | nill\t%0,%j2 |
ec24698e | 7389 | nilf\t%0,%o2 |
d40c829f | 7390 | nr\t%0,%2 |
65b1d8ea | 7391 | nrk\t%0,%1,%2 |
d40c829f | 7392 | n\t%0,%2 |
8cb66696 | 7393 | ny\t%0,%2 |
e3140518 | 7394 | risbg\t%0,%1,%t2,128+%f2,0 |
0dfa6c5e | 7395 | # |
19b63d8e | 7396 | #" |
e3140518 | 7397 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") |
3e4be43f | 7398 | (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*") |
9381e3f1 WG |
7399 | (set_attr "z10prop" "*, |
7400 | *, | |
7401 | z10_super_E1, | |
7402 | z10_super_E1, | |
7403 | z10_super_E1, | |
7404 | z10_super_E1, | |
65b1d8ea | 7405 | *, |
9381e3f1 WG |
7406 | z10_super_E1, |
7407 | z10_super_E1, | |
e3140518 | 7408 | z10_super_E1, |
9381e3f1 WG |
7409 | *, |
7410 | *")]) | |
f19a9af7 AK |
7411 | |
7412 | (define_insn "*andsi3_esa" | |
65b1d8ea AK |
7413 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") |
7414 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") | |
7415 | (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) | |
ae156f85 | 7416 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7417 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7418 | "@ |
7419 | nr\t%0,%2 | |
8cb66696 | 7420 | n\t%0,%2 |
0dfa6c5e | 7421 | # |
19b63d8e | 7422 | #" |
9381e3f1 WG |
7423 | [(set_attr "op_type" "RR,RX,SI,SS") |
7424 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
7425 | ||
0dfa6c5e UW |
7426 | |
7427 | (define_split | |
7428 | [(set (match_operand:SI 0 "s_operand" "") | |
7429 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7430 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7431 | "reload_completed" |
7432 | [(parallel | |
7433 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7434 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7435 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7436 | |
9db1d521 HP |
7437 | ; |
7438 | ; andhi3 instruction pattern(s). | |
7439 | ; | |
7440 | ||
8cb66696 | 7441 | (define_insn "*andhi3_zarch" |
65b1d8ea AK |
7442 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7443 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7444 | (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) | |
ae156f85 | 7445 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7446 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7447 | "@ |
d40c829f | 7448 | nr\t%0,%2 |
65b1d8ea | 7449 | nrk\t%0,%1,%2 |
8cb66696 | 7450 | nill\t%0,%x2 |
0dfa6c5e | 7451 | # |
19b63d8e | 7452 | #" |
65b1d8ea AK |
7453 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7454 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7455 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") | |
9381e3f1 | 7456 | ]) |
8cb66696 UW |
7457 | |
7458 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
7459 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7460 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7461 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 7462 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7463 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7464 | "@ | |
7465 | nr\t%0,%2 | |
0dfa6c5e | 7466 | # |
19b63d8e | 7467 | #" |
9381e3f1 WG |
7468 | [(set_attr "op_type" "RR,SI,SS") |
7469 | (set_attr "z10prop" "z10_super_E1,*,*") | |
7470 | ]) | |
0dfa6c5e UW |
7471 | |
7472 | (define_split | |
7473 | [(set (match_operand:HI 0 "s_operand" "") | |
7474 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7475 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7476 | "reload_completed" |
7477 | [(parallel | |
7478 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7479 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7480 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 7481 | |
9db1d521 HP |
7482 | ; |
7483 | ; andqi3 instruction pattern(s). | |
7484 | ; | |
7485 | ||
8cb66696 | 7486 | (define_insn "*andqi3_zarch" |
65b1d8ea AK |
7487 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7488 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7489 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7490 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7491 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7492 | "@ |
d40c829f | 7493 | nr\t%0,%2 |
65b1d8ea | 7494 | nrk\t%0,%1,%2 |
8cb66696 | 7495 | nill\t%0,%b2 |
fc0ea003 UW |
7496 | ni\t%S0,%b2 |
7497 | niy\t%S0,%b2 | |
19b63d8e | 7498 | #" |
65b1d8ea | 7499 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
3e4be43f | 7500 | (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") |
65b1d8ea | 7501 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) |
8cb66696 UW |
7502 | |
7503 | (define_insn "*andqi3_esa" | |
7504 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7505 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7506 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7507 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7508 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7509 | "@ |
8cb66696 | 7510 | nr\t%0,%2 |
fc0ea003 | 7511 | ni\t%S0,%b2 |
19b63d8e | 7512 | #" |
9381e3f1 WG |
7513 | [(set_attr "op_type" "RR,SI,SS") |
7514 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 7515 | |
deb9351f DV |
7516 | ; |
7517 | ; And with complement | |
7518 | ; | |
7519 | ; c = ~b & a = (b & a) ^ a | |
7520 | ||
7521 | (define_insn_and_split "*andc_split_<mode>" | |
7522 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
7523 | (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" "")) | |
7524 | (match_operand:GPR 2 "general_operand" ""))) | |
7525 | (clobber (reg:CC CC_REGNUM))] | |
ad7ab32e DV |
7526 | "! reload_completed |
7527 | && (GET_CODE (operands[0]) != MEM | |
7528 | /* Ensure that s390_logical_operator_ok_p will succeed even | |
7529 | on the split xor if (b & a) is stored into a pseudo. */ | |
7530 | || rtx_equal_p (operands[0], operands[2]))" | |
deb9351f DV |
7531 | "#" |
7532 | "&& 1" | |
7533 | [ | |
7534 | (parallel | |
7535 | [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2))) | |
7536 | (clobber (reg:CC CC_REGNUM))]) | |
7537 | (parallel | |
7538 | [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2))) | |
7539 | (clobber (reg:CC CC_REGNUM))])] | |
7540 | { | |
7541 | if (reg_overlap_mentioned_p (operands[0], operands[2])) | |
7542 | operands[3] = gen_reg_rtx (<MODE>mode); | |
7543 | else | |
7544 | operands[3] = operands[0]; | |
7545 | }) | |
7546 | ||
19b63d8e UW |
7547 | ; |
7548 | ; Block and (NC) patterns. | |
7549 | ; | |
7550 | ||
7551 | (define_insn "*nc" | |
7552 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7553 | (and:BLK (match_dup 0) | |
7554 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7555 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7556 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7557 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7558 | "nc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7559 | [(set_attr "op_type" "SS") |
7560 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7561 | |
7562 | (define_split | |
7563 | [(set (match_operand 0 "memory_operand" "") | |
7564 | (and (match_dup 0) | |
7565 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7566 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7567 | "reload_completed |
7568 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7569 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7570 | [(parallel | |
7571 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
7572 | (use (match_dup 2)) | |
ae156f85 | 7573 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7574 | { |
7575 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7576 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7577 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7578 | }) | |
7579 | ||
7580 | (define_peephole2 | |
7581 | [(parallel | |
7582 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7583 | (and:BLK (match_dup 0) | |
7584 | (match_operand:BLK 1 "memory_operand" ""))) | |
7585 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7586 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7587 | (parallel |
7588 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7589 | (and:BLK (match_dup 3) | |
7590 | (match_operand:BLK 4 "memory_operand" ""))) | |
7591 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7592 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7593 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7594 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7595 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7596 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7597 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7598 | [(parallel | |
7599 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
7600 | (use (match_dup 8)) | |
ae156f85 | 7601 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7602 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7603 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7604 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7605 | ||
9db1d521 HP |
7606 | |
7607 | ;; | |
7608 | ;;- Bit set (inclusive or) instructions. | |
7609 | ;; | |
7610 | ||
047d35ed AS |
7611 | (define_expand "ior<mode>3" |
7612 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7613 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7614 | (match_operand:INT 2 "general_operand" ""))) | |
7615 | (clobber (reg:CC CC_REGNUM))] | |
7616 | "" | |
7617 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
7618 | ||
9db1d521 HP |
7619 | ; |
7620 | ; iordi3 instruction pattern(s). | |
7621 | ; | |
7622 | ||
4023fb28 | 7623 | (define_insn "*iordi3_cc" |
ae156f85 | 7624 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7625 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7626 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7627 | (const_int 0))) |
3e4be43f | 7628 | (set (match_operand:DI 0 "register_operand" "=d,d,d") |
4023fb28 | 7629 | (ior:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7630 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7631 | "@ |
d40c829f | 7632 | ogr\t%0,%2 |
65b1d8ea | 7633 | ogrk\t%0,%1,%2 |
d40c829f | 7634 | og\t%0,%2" |
65b1d8ea AK |
7635 | [(set_attr "op_type" "RRE,RRF,RXY") |
7636 | (set_attr "cpu_facility" "*,z196,*") | |
7637 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 UW |
7638 | |
7639 | (define_insn "*iordi3_cconly" | |
ae156f85 | 7640 | [(set (reg CC_REGNUM) |
65b1d8ea | 7641 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
3e4be43f | 7642 | (match_operand:DI 2 "general_operand" " d,d,T")) |
4023fb28 | 7643 | (const_int 0))) |
65b1d8ea | 7644 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 7645 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7646 | "@ |
d40c829f | 7647 | ogr\t%0,%2 |
65b1d8ea | 7648 | ogrk\t%0,%1,%2 |
d40c829f | 7649 | og\t%0,%2" |
65b1d8ea AK |
7650 | [(set_attr "op_type" "RRE,RRF,RXY") |
7651 | (set_attr "cpu_facility" "*,z196,*") | |
7652 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7653 | |
3af8e996 | 7654 | (define_insn "*iordi3" |
65b1d8ea | 7655 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 7656 | "=d, d, d, d, d, d,d,d,d, AQ,Q") |
65b1d8ea | 7657 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" |
3e4be43f | 7658 | " %0, 0, 0, 0, 0, 0,0,d,0, 0,0") |
ec24698e | 7659 | (match_operand:DI 2 "general_operand" |
3e4be43f | 7660 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q"))) |
ec24698e | 7661 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7662 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7663 | "@ |
7664 | oihh\t%0,%i2 | |
7665 | oihl\t%0,%i2 | |
7666 | oilh\t%0,%i2 | |
7667 | oill\t%0,%i2 | |
7668 | oihf\t%0,%k2 | |
7669 | oilf\t%0,%k2 | |
7670 | ogr\t%0,%2 | |
65b1d8ea | 7671 | ogrk\t%0,%1,%2 |
ec24698e UW |
7672 | og\t%0,%2 |
7673 | # | |
7674 | #" | |
65b1d8ea AK |
7675 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
7676 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
7677 | (set_attr "z10prop" "z10_super_E1, |
7678 | z10_super_E1, | |
7679 | z10_super_E1, | |
7680 | z10_super_E1, | |
7681 | z10_super_E1, | |
7682 | z10_super_E1, | |
7683 | z10_super_E1, | |
65b1d8ea | 7684 | *, |
9381e3f1 WG |
7685 | z10_super_E1, |
7686 | *, | |
7687 | *")]) | |
0dfa6c5e UW |
7688 | |
7689 | (define_split | |
7690 | [(set (match_operand:DI 0 "s_operand" "") | |
7691 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7692 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7693 | "reload_completed" |
7694 | [(parallel | |
7695 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7696 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7697 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7698 | |
9db1d521 HP |
7699 | ; |
7700 | ; iorsi3 instruction pattern(s). | |
7701 | ; | |
7702 | ||
4023fb28 | 7703 | (define_insn "*iorsi3_cc" |
ae156f85 | 7704 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7705 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7706 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7707 | (const_int 0))) |
65b1d8ea | 7708 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7709 | (ior:SI (match_dup 1) (match_dup 2)))] |
7710 | "s390_match_ccmode(insn, CCTmode)" | |
7711 | "@ | |
ec24698e | 7712 | oilf\t%0,%o2 |
d40c829f | 7713 | or\t%0,%2 |
65b1d8ea | 7714 | ork\t%0,%1,%2 |
d40c829f UW |
7715 | o\t%0,%2 |
7716 | oy\t%0,%2" | |
65b1d8ea | 7717 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7718 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea | 7719 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
4023fb28 UW |
7720 | |
7721 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 7722 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7723 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7724 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7725 | (const_int 0))) |
65b1d8ea | 7726 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7727 | "s390_match_ccmode(insn, CCTmode)" |
7728 | "@ | |
ec24698e | 7729 | oilf\t%0,%o2 |
d40c829f | 7730 | or\t%0,%2 |
65b1d8ea | 7731 | ork\t%0,%1,%2 |
d40c829f UW |
7732 | o\t%0,%2 |
7733 | oy\t%0,%2" | |
65b1d8ea | 7734 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7735 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea | 7736 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
4023fb28 | 7737 | |
8cb66696 | 7738 | (define_insn "*iorsi3_zarch" |
65b1d8ea AK |
7739 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") |
7740 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") | |
7741 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7742 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7743 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7744 | "@ |
f19a9af7 AK |
7745 | oilh\t%0,%i2 |
7746 | oill\t%0,%i2 | |
ec24698e | 7747 | oilf\t%0,%o2 |
d40c829f | 7748 | or\t%0,%2 |
65b1d8ea | 7749 | ork\t%0,%1,%2 |
d40c829f | 7750 | o\t%0,%2 |
8cb66696 | 7751 | oy\t%0,%2 |
0dfa6c5e | 7752 | # |
19b63d8e | 7753 | #" |
65b1d8ea | 7754 | [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
3e4be43f | 7755 | (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*") |
9381e3f1 WG |
7756 | (set_attr "z10prop" "z10_super_E1, |
7757 | z10_super_E1, | |
7758 | z10_super_E1, | |
7759 | z10_super_E1, | |
65b1d8ea | 7760 | *, |
9381e3f1 WG |
7761 | z10_super_E1, |
7762 | z10_super_E1, | |
7763 | *, | |
7764 | *")]) | |
8cb66696 UW |
7765 | |
7766 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 7767 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 7768 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 7769 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 7770 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7771 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7772 | "@ |
7773 | or\t%0,%2 | |
8cb66696 | 7774 | o\t%0,%2 |
0dfa6c5e | 7775 | # |
19b63d8e | 7776 | #" |
9381e3f1 WG |
7777 | [(set_attr "op_type" "RR,RX,SI,SS") |
7778 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7779 | |
7780 | (define_split | |
7781 | [(set (match_operand:SI 0 "s_operand" "") | |
7782 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7783 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7784 | "reload_completed" |
7785 | [(parallel | |
7786 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7787 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7788 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7789 | |
4023fb28 UW |
7790 | ; |
7791 | ; iorhi3 instruction pattern(s). | |
7792 | ; | |
7793 | ||
8cb66696 | 7794 | (define_insn "*iorhi3_zarch" |
65b1d8ea AK |
7795 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7796 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7797 | (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) | |
ae156f85 | 7798 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7799 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7800 | "@ |
d40c829f | 7801 | or\t%0,%2 |
65b1d8ea | 7802 | ork\t%0,%1,%2 |
8cb66696 | 7803 | oill\t%0,%x2 |
0dfa6c5e | 7804 | # |
19b63d8e | 7805 | #" |
65b1d8ea AK |
7806 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7807 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7808 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) | |
8cb66696 UW |
7809 | |
7810 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
7811 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7812 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7813 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 7814 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7815 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7816 | "@ | |
7817 | or\t%0,%2 | |
0dfa6c5e | 7818 | # |
19b63d8e | 7819 | #" |
9381e3f1 WG |
7820 | [(set_attr "op_type" "RR,SI,SS") |
7821 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7822 | |
7823 | (define_split | |
7824 | [(set (match_operand:HI 0 "s_operand" "") | |
7825 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7826 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7827 | "reload_completed" |
7828 | [(parallel | |
7829 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7830 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7831 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 7832 | |
9db1d521 | 7833 | ; |
4023fb28 | 7834 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
7835 | ; |
7836 | ||
8cb66696 | 7837 | (define_insn "*iorqi3_zarch" |
65b1d8ea AK |
7838 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7839 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7840 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7841 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7842 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7843 | "@ |
d40c829f | 7844 | or\t%0,%2 |
65b1d8ea | 7845 | ork\t%0,%1,%2 |
8cb66696 | 7846 | oill\t%0,%b2 |
fc0ea003 UW |
7847 | oi\t%S0,%b2 |
7848 | oiy\t%S0,%b2 | |
19b63d8e | 7849 | #" |
65b1d8ea | 7850 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
3e4be43f | 7851 | (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") |
65b1d8ea AK |
7852 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, |
7853 | z10_super,z10_super,*")]) | |
8cb66696 UW |
7854 | |
7855 | (define_insn "*iorqi3_esa" | |
7856 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7857 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7858 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7859 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7860 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7861 | "@ |
8cb66696 | 7862 | or\t%0,%2 |
fc0ea003 | 7863 | oi\t%S0,%b2 |
19b63d8e | 7864 | #" |
9381e3f1 WG |
7865 | [(set_attr "op_type" "RR,SI,SS") |
7866 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 7867 | |
19b63d8e UW |
7868 | ; |
7869 | ; Block inclusive or (OC) patterns. | |
7870 | ; | |
7871 | ||
7872 | (define_insn "*oc" | |
7873 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7874 | (ior:BLK (match_dup 0) | |
7875 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7876 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7877 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7878 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7879 | "oc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7880 | [(set_attr "op_type" "SS") |
7881 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7882 | |
7883 | (define_split | |
7884 | [(set (match_operand 0 "memory_operand" "") | |
7885 | (ior (match_dup 0) | |
7886 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7887 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7888 | "reload_completed |
7889 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7890 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7891 | [(parallel | |
7892 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
7893 | (use (match_dup 2)) | |
ae156f85 | 7894 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7895 | { |
7896 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7897 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7898 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7899 | }) | |
7900 | ||
7901 | (define_peephole2 | |
7902 | [(parallel | |
7903 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7904 | (ior:BLK (match_dup 0) | |
7905 | (match_operand:BLK 1 "memory_operand" ""))) | |
7906 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7907 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7908 | (parallel |
7909 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7910 | (ior:BLK (match_dup 3) | |
7911 | (match_operand:BLK 4 "memory_operand" ""))) | |
7912 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7913 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7914 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7915 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7916 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7917 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7918 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7919 | [(parallel | |
7920 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
7921 | (use (match_dup 8)) | |
ae156f85 | 7922 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7923 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7924 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7925 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7926 | ||
9db1d521 HP |
7927 | |
7928 | ;; | |
7929 | ;;- Xor instructions. | |
7930 | ;; | |
7931 | ||
047d35ed AS |
7932 | (define_expand "xor<mode>3" |
7933 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7934 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7935 | (match_operand:INT 2 "general_operand" ""))) | |
7936 | (clobber (reg:CC CC_REGNUM))] | |
7937 | "" | |
7938 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
7939 | ||
3c91f126 AK |
7940 | ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing |
7941 | ; simplifications. So its better to have something matching. | |
7942 | (define_split | |
7943 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7944 | (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))] | |
7945 | "" | |
7946 | [(parallel | |
7947 | [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2))) | |
7948 | (clobber (reg:CC CC_REGNUM))])] | |
7949 | { | |
7950 | operands[2] = constm1_rtx; | |
7951 | if (!s390_logical_operator_ok_p (operands)) | |
7952 | FAIL; | |
7953 | }) | |
7954 | ||
9db1d521 HP |
7955 | ; |
7956 | ; xordi3 instruction pattern(s). | |
7957 | ; | |
7958 | ||
4023fb28 | 7959 | (define_insn "*xordi3_cc" |
ae156f85 | 7960 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7961 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7962 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7963 | (const_int 0))) |
3e4be43f | 7964 | (set (match_operand:DI 0 "register_operand" "=d,d,d") |
4023fb28 | 7965 | (xor:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7966 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7967 | "@ |
d40c829f | 7968 | xgr\t%0,%2 |
65b1d8ea | 7969 | xgrk\t%0,%1,%2 |
d40c829f | 7970 | xg\t%0,%2" |
65b1d8ea | 7971 | [(set_attr "op_type" "RRE,RRF,RXY") |
5490de28 | 7972 | (set_attr "cpu_facility" "*,z196,*") |
65b1d8ea | 7973 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) |
4023fb28 UW |
7974 | |
7975 | (define_insn "*xordi3_cconly" | |
ae156f85 | 7976 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7977 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7978 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7979 | (const_int 0))) |
3e4be43f | 7980 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 7981 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7982 | "@ |
d40c829f | 7983 | xgr\t%0,%2 |
65b1d8ea | 7984 | xgrk\t%0,%1,%2 |
c7fd8cd8 | 7985 | xg\t%0,%2" |
65b1d8ea AK |
7986 | [(set_attr "op_type" "RRE,RRF,RXY") |
7987 | (set_attr "cpu_facility" "*,z196,*") | |
7988 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7989 | |
3af8e996 | 7990 | (define_insn "*xordi3" |
3e4be43f UW |
7991 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q") |
7992 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0") | |
7993 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q"))) | |
ec24698e | 7994 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7995 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7996 | "@ |
7997 | xihf\t%0,%k2 | |
7998 | xilf\t%0,%k2 | |
7999 | xgr\t%0,%2 | |
65b1d8ea | 8000 | xgrk\t%0,%1,%2 |
ec24698e UW |
8001 | xg\t%0,%2 |
8002 | # | |
8003 | #" | |
65b1d8ea AK |
8004 | [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") |
8005 | (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") | |
8006 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, | |
8007 | *,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
8008 | |
8009 | (define_split | |
8010 | [(set (match_operand:DI 0 "s_operand" "") | |
8011 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 8012 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8013 | "reload_completed" |
8014 | [(parallel | |
8015 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8016 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8017 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 8018 | |
9db1d521 HP |
8019 | ; |
8020 | ; xorsi3 instruction pattern(s). | |
8021 | ; | |
8022 | ||
4023fb28 | 8023 | (define_insn "*xorsi3_cc" |
ae156f85 | 8024 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8025 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
8026 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 8027 | (const_int 0))) |
65b1d8ea | 8028 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
8029 | (xor:SI (match_dup 1) (match_dup 2)))] |
8030 | "s390_match_ccmode(insn, CCTmode)" | |
8031 | "@ | |
ec24698e | 8032 | xilf\t%0,%o2 |
d40c829f | 8033 | xr\t%0,%2 |
65b1d8ea | 8034 | xrk\t%0,%1,%2 |
d40c829f UW |
8035 | x\t%0,%2 |
8036 | xy\t%0,%2" | |
65b1d8ea | 8037 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 8038 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea AK |
8039 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8040 | z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
8041 | |
8042 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 8043 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8044 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
8045 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 8046 | (const_int 0))) |
65b1d8ea | 8047 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
8048 | "s390_match_ccmode(insn, CCTmode)" |
8049 | "@ | |
ec24698e | 8050 | xilf\t%0,%o2 |
d40c829f | 8051 | xr\t%0,%2 |
65b1d8ea | 8052 | xrk\t%0,%1,%2 |
d40c829f UW |
8053 | x\t%0,%2 |
8054 | xy\t%0,%2" | |
65b1d8ea | 8055 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 8056 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea AK |
8057 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8058 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 8059 | |
8cb66696 | 8060 | (define_insn "*xorsi3" |
65b1d8ea AK |
8061 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") |
8062 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") | |
8063 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 8064 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8065 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 8066 | "@ |
ec24698e | 8067 | xilf\t%0,%o2 |
d40c829f | 8068 | xr\t%0,%2 |
65b1d8ea | 8069 | xrk\t%0,%1,%2 |
d40c829f | 8070 | x\t%0,%2 |
8cb66696 | 8071 | xy\t%0,%2 |
0dfa6c5e | 8072 | # |
19b63d8e | 8073 | #" |
65b1d8ea | 8074 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") |
3e4be43f | 8075 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*") |
65b1d8ea AK |
8076 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8077 | z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
8078 | |
8079 | (define_split | |
8080 | [(set (match_operand:SI 0 "s_operand" "") | |
8081 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 8082 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8083 | "reload_completed" |
8084 | [(parallel | |
8085 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8086 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8087 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 8088 | |
9db1d521 HP |
8089 | ; |
8090 | ; xorhi3 instruction pattern(s). | |
8091 | ; | |
8092 | ||
8cb66696 | 8093 | (define_insn "*xorhi3" |
65b1d8ea AK |
8094 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
8095 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") | |
8096 | (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) | |
ae156f85 | 8097 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
8098 | "s390_logical_operator_ok_p (operands)" |
8099 | "@ | |
ec24698e | 8100 | xilf\t%0,%x2 |
8cb66696 | 8101 | xr\t%0,%2 |
65b1d8ea | 8102 | xrk\t%0,%1,%2 |
0dfa6c5e | 8103 | # |
19b63d8e | 8104 | #" |
65b1d8ea AK |
8105 | [(set_attr "op_type" "RIL,RR,RRF,SI,SS") |
8106 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
8107 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) | |
0dfa6c5e UW |
8108 | |
8109 | (define_split | |
8110 | [(set (match_operand:HI 0 "s_operand" "") | |
8111 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 8112 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8113 | "reload_completed" |
8114 | [(parallel | |
8115 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8116 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8117 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 8118 | |
9db1d521 HP |
8119 | ; |
8120 | ; xorqi3 instruction pattern(s). | |
8121 | ; | |
8122 | ||
8cb66696 | 8123 | (define_insn "*xorqi3" |
65b1d8ea AK |
8124 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
8125 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") | |
8126 | (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) | |
ae156f85 | 8127 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8128 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 8129 | "@ |
ec24698e | 8130 | xilf\t%0,%b2 |
8cb66696 | 8131 | xr\t%0,%2 |
65b1d8ea | 8132 | xrk\t%0,%1,%2 |
fc0ea003 UW |
8133 | xi\t%S0,%b2 |
8134 | xiy\t%S0,%b2 | |
19b63d8e | 8135 | #" |
65b1d8ea | 8136 | [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") |
3e4be43f | 8137 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,*") |
65b1d8ea | 8138 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) |
9381e3f1 | 8139 | |
4023fb28 | 8140 | |
19b63d8e UW |
8141 | ; |
8142 | ; Block exclusive or (XC) patterns. | |
8143 | ; | |
8144 | ||
8145 | (define_insn "*xc" | |
8146 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8147 | (xor:BLK (match_dup 0) | |
8148 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
8149 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 8150 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8151 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 8152 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 8153 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
8154 | |
8155 | (define_split | |
8156 | [(set (match_operand 0 "memory_operand" "") | |
8157 | (xor (match_dup 0) | |
8158 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 8159 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
8160 | "reload_completed |
8161 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
8162 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
8163 | [(parallel | |
8164 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
8165 | (use (match_dup 2)) | |
ae156f85 | 8166 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8167 | { |
8168 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
8169 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
8170 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
8171 | }) | |
8172 | ||
8173 | (define_peephole2 | |
8174 | [(parallel | |
8175 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8176 | (xor:BLK (match_dup 0) | |
8177 | (match_operand:BLK 1 "memory_operand" ""))) | |
8178 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 8179 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8180 | (parallel |
8181 | [(set (match_operand:BLK 3 "memory_operand" "") | |
8182 | (xor:BLK (match_dup 3) | |
8183 | (match_operand:BLK 4 "memory_operand" ""))) | |
8184 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 8185 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8186 | "s390_offset_p (operands[0], operands[3], operands[2]) |
8187 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 8188 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 8189 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
8190 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
8191 | [(parallel | |
8192 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
8193 | (use (match_dup 8)) | |
ae156f85 | 8194 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8195 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8196 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
8197 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
8198 | ||
8199 | ; | |
8200 | ; Block xor (XC) patterns with src == dest. | |
8201 | ; | |
8202 | ||
8203 | (define_insn "*xc_zero" | |
8204 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8205 | (const_int 0)) | |
8206 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 8207 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8208 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 8209 | "xc\t%O0(%1,%R0),%S0" |
65b1d8ea AK |
8210 | [(set_attr "op_type" "SS") |
8211 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
8212 | |
8213 | (define_peephole2 | |
8214 | [(parallel | |
8215 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8216 | (const_int 0)) | |
8217 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 8218 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8219 | (parallel |
8220 | [(set (match_operand:BLK 2 "memory_operand" "") | |
8221 | (const_int 0)) | |
8222 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 8223 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8224 | "s390_offset_p (operands[0], operands[2], operands[1]) |
8225 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
8226 | [(parallel | |
8227 | [(set (match_dup 4) (const_int 0)) | |
8228 | (use (match_dup 5)) | |
ae156f85 | 8229 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8230 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8231 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
8232 | ||
9db1d521 HP |
8233 | |
8234 | ;; | |
8235 | ;;- Negate instructions. | |
8236 | ;; | |
8237 | ||
8238 | ; | |
9a91a21f | 8239 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
8240 | ; |
8241 | ||
9a91a21f | 8242 | (define_expand "neg<mode>2" |
9db1d521 | 8243 | [(parallel |
9a91a21f AS |
8244 | [(set (match_operand:DSI 0 "register_operand" "=d") |
8245 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 8246 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8247 | "" |
8248 | "") | |
8249 | ||
26a89301 | 8250 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 8251 | [(set (reg CC_REGNUM) |
26a89301 UW |
8252 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8253 | (match_operand:SI 1 "register_operand" "d") 0) | |
8254 | (const_int 32)) (const_int 32))) | |
8255 | (const_int 0))) | |
8256 | (set (match_operand:DI 0 "register_operand" "=d") | |
8257 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8258 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8259 | "lcgfr\t%0,%1" |
729e750f WG |
8260 | [(set_attr "op_type" "RRE") |
8261 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8262 | |
26a89301 UW |
8263 | (define_insn "*negdi2_sign" |
8264 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8265 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8266 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8267 | "TARGET_ZARCH" |
26a89301 | 8268 | "lcgfr\t%0,%1" |
729e750f WG |
8269 | [(set_attr "op_type" "RRE") |
8270 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8271 | |
43a09b63 | 8272 | ; lcr, lcgr |
9a91a21f | 8273 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8274 | [(set (reg CC_REGNUM) |
9a91a21f | 8275 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8276 | (const_int 0))) |
9a91a21f AS |
8277 | (set (match_operand:GPR 0 "register_operand" "=d") |
8278 | (neg:GPR (match_dup 1)))] | |
8279 | "s390_match_ccmode (insn, CCAmode)" | |
8280 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8281 | [(set_attr "op_type" "RR<E>") |
8282 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
8283 | |
8284 | ; lcr, lcgr | |
9a91a21f | 8285 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8286 | [(set (reg CC_REGNUM) |
9a91a21f | 8287 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8288 | (const_int 0))) |
9a91a21f AS |
8289 | (clobber (match_scratch:GPR 0 "=d"))] |
8290 | "s390_match_ccmode (insn, CCAmode)" | |
8291 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8292 | [(set_attr "op_type" "RR<E>") |
8293 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
8294 | |
8295 | ; lcr, lcgr | |
9a91a21f AS |
8296 | (define_insn "*neg<mode>2" |
8297 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8298 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8299 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
8300 | "" |
8301 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8302 | [(set_attr "op_type" "RR<E>") |
8303 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 8304 | |
b7d19263 | 8305 | (define_insn "*negdi2_31" |
9db1d521 HP |
8306 | [(set (match_operand:DI 0 "register_operand" "=d") |
8307 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 8308 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8309 | "!TARGET_ZARCH" |
b7d19263 AK |
8310 | "#") |
8311 | ||
8312 | ; Split a DImode NEG on 31bit into 2 SImode NEGs | |
8313 | ||
8314 | ; Doing the twos complement separately on the SImode parts does an | |
8315 | ; unwanted +1 on the high part which needs to be subtracted afterwards | |
8316 | ; ... unless the +1 on the low part created an overflow. | |
8317 | ||
8318 | (define_split | |
8319 | [(set (match_operand:DI 0 "register_operand" "") | |
8320 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8321 | (clobber (reg:CC CC_REGNUM))] | |
8322 | "!TARGET_ZARCH | |
8323 | && (REGNO (operands[0]) == REGNO (operands[1]) | |
8324 | || s390_split_ok_p (operands[0], operands[1], DImode, 0)) | |
8325 | && reload_completed" | |
26a89301 UW |
8326 | [(parallel |
8327 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 8328 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 8329 | (parallel |
ae156f85 | 8330 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
8331 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
8332 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
8333 | (set (pc) | |
ae156f85 | 8334 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
8335 | (pc) |
8336 | (label_ref (match_dup 6)))) | |
8337 | (parallel | |
8338 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 8339 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
8340 | (match_dup 6)] |
8341 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8342 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8343 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8344 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8345 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 8346 | |
b7d19263 AK |
8347 | ; Like above but first make a copy of the low part of the src operand |
8348 | ; since it might overlap with the high part of the destination. | |
8349 | ||
8350 | (define_split | |
8351 | [(set (match_operand:DI 0 "register_operand" "") | |
8352 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8353 | (clobber (reg:CC CC_REGNUM))] | |
8354 | "!TARGET_ZARCH | |
8355 | && s390_split_ok_p (operands[0], operands[1], DImode, 1) | |
8356 | && reload_completed" | |
8357 | [; Make a backup of op5 first | |
8358 | (set (match_dup 4) (match_dup 5)) | |
8359 | ; Setting op2 here might clobber op5 | |
8360 | (parallel | |
8361 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
8362 | (clobber (reg:CC CC_REGNUM))]) | |
8363 | (parallel | |
8364 | [(set (reg:CCAP CC_REGNUM) | |
8365 | (compare:CCAP (neg:SI (match_dup 4)) (const_int 0))) | |
8366 | (set (match_dup 4) (neg:SI (match_dup 4)))]) | |
8367 | (set (pc) | |
8368 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) | |
8369 | (pc) | |
8370 | (label_ref (match_dup 6)))) | |
8371 | (parallel | |
8372 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
8373 | (clobber (reg:CC CC_REGNUM))]) | |
8374 | (match_dup 6)] | |
8375 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8376 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8377 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8378 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8379 | operands[6] = gen_label_rtx ();") | |
8380 | ||
9db1d521 | 8381 | ; |
f5905b37 | 8382 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8383 | ; |
8384 | ||
f5905b37 | 8385 | (define_expand "neg<mode>2" |
9db1d521 | 8386 | [(parallel |
2de2b3f9 AK |
8387 | [(set (match_operand:BFP 0 "register_operand") |
8388 | (neg:BFP (match_operand:BFP 1 "register_operand"))) | |
ae156f85 | 8389 | (clobber (reg:CC CC_REGNUM))])] |
2de2b3f9 | 8390 | "TARGET_HARD_FLOAT") |
9db1d521 | 8391 | |
43a09b63 | 8392 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 8393 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8394 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8395 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8396 | (match_operand:BFP 2 "const0_operand" ""))) | |
8397 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8398 | (neg:BFP (match_dup 1)))] | |
142cd70f | 8399 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8400 | "lc<xde>br\t%0,%1" |
26a89301 | 8401 | [(set_attr "op_type" "RRE") |
f5905b37 | 8402 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8403 | |
8404 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 8405 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8406 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8407 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8408 | (match_operand:BFP 2 "const0_operand" ""))) | |
8409 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8410 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8411 | "lc<xde>br\t%0,%1" |
26a89301 | 8412 | [(set_attr "op_type" "RRE") |
f5905b37 | 8413 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8414 | |
85dae55a AK |
8415 | ; lcdfr |
8416 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
8417 | [(set (match_operand:FP 0 "register_operand" "=f") |
8418 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8419 | "TARGET_DFP" |
85dae55a AK |
8420 | "lcdfr\t%0,%1" |
8421 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8422 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8423 | |
43a09b63 | 8424 | ; lcxbr, lcdbr, lcebr |
6e5b5de8 | 8425 | ; FIXME: wflcdb does not clobber cc |
2de2b3f9 | 8426 | ; FIXME: Does wflcdb ever match here? |
f5905b37 | 8427 | (define_insn "*neg<mode>2" |
2de2b3f9 AK |
8428 | [(set (match_operand:BFP 0 "register_operand" "=f,v,v") |
8429 | (neg:BFP (match_operand:BFP 1 "register_operand" "f,v,v"))) | |
ae156f85 | 8430 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8431 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8432 | "@ |
8433 | lc<xde>br\t%0,%1 | |
2de2b3f9 AK |
8434 | wflcdb\t%0,%1 |
8435 | wflcsb\t%0,%1" | |
8436 | [(set_attr "op_type" "RRE,VRR,VRR") | |
8437 | (set_attr "cpu_facility" "*,vx,vxe") | |
8438 | (set_attr "type" "fsimp<mode>,*,*") | |
8439 | (set_attr "enabled" "*,<DF>,<SF>")]) | |
9db1d521 | 8440 | |
9db1d521 HP |
8441 | |
8442 | ;; | |
8443 | ;;- Absolute value instructions. | |
8444 | ;; | |
8445 | ||
8446 | ; | |
9a91a21f | 8447 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
8448 | ; |
8449 | ||
26a89301 | 8450 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 8451 | [(set (reg CC_REGNUM) |
26a89301 UW |
8452 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8453 | (match_operand:SI 1 "register_operand" "d") 0) | |
8454 | (const_int 32)) (const_int 32))) | |
8455 | (const_int 0))) | |
8456 | (set (match_operand:DI 0 "register_operand" "=d") | |
8457 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8458 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8459 | "lpgfr\t%0,%1" |
729e750f WG |
8460 | [(set_attr "op_type" "RRE") |
8461 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
8462 | |
8463 | (define_insn "*absdi2_sign" | |
8464 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8465 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8466 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8467 | "TARGET_ZARCH" |
26a89301 | 8468 | "lpgfr\t%0,%1" |
729e750f WG |
8469 | [(set_attr "op_type" "RRE") |
8470 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8471 | |
43a09b63 | 8472 | ; lpr, lpgr |
9a91a21f | 8473 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8474 | [(set (reg CC_REGNUM) |
9a91a21f | 8475 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 8476 | (const_int 0))) |
9a91a21f AS |
8477 | (set (match_operand:GPR 0 "register_operand" "=d") |
8478 | (abs:GPR (match_dup 1)))] | |
26a89301 | 8479 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8480 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8481 | [(set_attr "op_type" "RR<E>") |
8482 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 8483 | |
9381e3f1 | 8484 | ; lpr, lpgr |
9a91a21f | 8485 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8486 | [(set (reg CC_REGNUM) |
9a91a21f | 8487 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8488 | (const_int 0))) |
9a91a21f | 8489 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8490 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8491 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8492 | [(set_attr "op_type" "RR<E>") |
8493 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8494 | |
8495 | ; lpr, lpgr | |
9a91a21f AS |
8496 | (define_insn "abs<mode>2" |
8497 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8498 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8499 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 8500 | "" |
9a91a21f | 8501 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8502 | [(set_attr "op_type" "RR<E>") |
8503 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 8504 | |
9db1d521 | 8505 | ; |
f5905b37 | 8506 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8507 | ; |
8508 | ||
f5905b37 | 8509 | (define_expand "abs<mode>2" |
9db1d521 | 8510 | [(parallel |
7b6baae1 AK |
8511 | [(set (match_operand:BFP 0 "register_operand" "=f") |
8512 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 8513 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8514 | "TARGET_HARD_FLOAT" |
8515 | "") | |
8516 | ||
43a09b63 | 8517 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 8518 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8519 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8520 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8521 | (match_operand:BFP 2 "const0_operand" ""))) | |
8522 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8523 | (abs:BFP (match_dup 1)))] | |
142cd70f | 8524 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8525 | "lp<xde>br\t%0,%1" |
26a89301 | 8526 | [(set_attr "op_type" "RRE") |
f5905b37 | 8527 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8528 | |
8529 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 8530 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8531 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8532 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8533 | (match_operand:BFP 2 "const0_operand" ""))) | |
8534 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8535 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8536 | "lp<xde>br\t%0,%1" |
26a89301 | 8537 | [(set_attr "op_type" "RRE") |
f5905b37 | 8538 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8539 | |
85dae55a AK |
8540 | ; lpdfr |
8541 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
8542 | [(set (match_operand:FP 0 "register_operand" "=f") |
8543 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8544 | "TARGET_DFP" |
85dae55a AK |
8545 | "lpdfr\t%0,%1" |
8546 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8547 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8548 | |
43a09b63 | 8549 | ; lpxbr, lpdbr, lpebr |
6e5b5de8 | 8550 | ; FIXME: wflpdb does not clobber cc |
f5905b37 | 8551 | (define_insn "*abs<mode>2" |
62d3f261 AK |
8552 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8553 | (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))) | |
ae156f85 | 8554 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8555 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8556 | "@ |
8557 | lp<xde>br\t%0,%1 | |
8558 | wflpdb\t%0,%1" | |
8559 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8560 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8561 | (set_attr "type" "fsimp<mode>,*") |
8562 | (set_attr "enabled" "*,<DFDI>")]) | |
9db1d521 | 8563 | |
9db1d521 | 8564 | |
3ef093a8 AK |
8565 | ;; |
8566 | ;;- Negated absolute value instructions | |
8567 | ;; | |
8568 | ||
8569 | ; | |
8570 | ; Integer | |
8571 | ; | |
8572 | ||
26a89301 | 8573 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 8574 | [(set (reg CC_REGNUM) |
26a89301 UW |
8575 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8576 | (match_operand:SI 1 "register_operand" "d") 0) | |
8577 | (const_int 32)) (const_int 32)))) | |
8578 | (const_int 0))) | |
8579 | (set (match_operand:DI 0 "register_operand" "=d") | |
8580 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
9602b6a1 | 8581 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8582 | "lngfr\t%0,%1" |
729e750f WG |
8583 | [(set_attr "op_type" "RRE") |
8584 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8585 | |
26a89301 UW |
8586 | (define_insn "*negabsdi2_sign" |
8587 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8588 | (neg:DI (abs:DI (sign_extend:DI | |
8589 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 8590 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8591 | "TARGET_ZARCH" |
26a89301 | 8592 | "lngfr\t%0,%1" |
729e750f WG |
8593 | [(set_attr "op_type" "RRE") |
8594 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 8595 | |
43a09b63 | 8596 | ; lnr, lngr |
9a91a21f | 8597 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8598 | [(set (reg CC_REGNUM) |
9a91a21f | 8599 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8600 | (const_int 0))) |
9a91a21f AS |
8601 | (set (match_operand:GPR 0 "register_operand" "=d") |
8602 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 8603 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8604 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8605 | [(set_attr "op_type" "RR<E>") |
8606 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8607 | |
8608 | ; lnr, lngr | |
9a91a21f | 8609 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8610 | [(set (reg CC_REGNUM) |
9a91a21f | 8611 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8612 | (const_int 0))) |
9a91a21f | 8613 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8614 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8615 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8616 | [(set_attr "op_type" "RR<E>") |
8617 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8618 | |
8619 | ; lnr, lngr | |
9a91a21f AS |
8620 | (define_insn "*negabs<mode>2" |
8621 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8622 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 8623 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 8624 | "" |
9a91a21f | 8625 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8626 | [(set_attr "op_type" "RR<E>") |
8627 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8628 | |
3ef093a8 AK |
8629 | ; |
8630 | ; Floating point | |
8631 | ; | |
8632 | ||
43a09b63 | 8633 | ; lnxbr, lndbr, lnebr |
f5905b37 | 8634 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8635 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8636 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8637 | (match_operand:BFP 2 "const0_operand" ""))) | |
8638 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8639 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 8640 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8641 | "ln<xde>br\t%0,%1" |
26a89301 | 8642 | [(set_attr "op_type" "RRE") |
f5905b37 | 8643 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8644 | |
8645 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 8646 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8647 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8648 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8649 | (match_operand:BFP 2 "const0_operand" ""))) | |
8650 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8651 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8652 | "ln<xde>br\t%0,%1" |
26a89301 | 8653 | [(set_attr "op_type" "RRE") |
f5905b37 | 8654 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8655 | |
85dae55a AK |
8656 | ; lndfr |
8657 | (define_insn "*negabs<mode>2_nocc" | |
609e7e80 AK |
8658 | [(set (match_operand:FP 0 "register_operand" "=f") |
8659 | (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 8660 | "TARGET_DFP" |
85dae55a AK |
8661 | "lndfr\t%0,%1" |
8662 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8663 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8664 | |
43a09b63 | 8665 | ; lnxbr, lndbr, lnebr |
6e5b5de8 | 8666 | ; FIXME: wflndb does not clobber cc |
f5905b37 | 8667 | (define_insn "*negabs<mode>2" |
62d3f261 AK |
8668 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8669 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))) | |
ae156f85 | 8670 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8671 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8672 | "@ |
8673 | ln<xde>br\t%0,%1 | |
8674 | wflndb\t%0,%1" | |
8675 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8676 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8677 | (set_attr "type" "fsimp<mode>,*") |
8678 | (set_attr "enabled" "*,<DFDI>")]) | |
26a89301 | 8679 | |
4023fb28 UW |
8680 | ;; |
8681 | ;;- Square root instructions. | |
8682 | ;; | |
8683 | ||
8684 | ; | |
f5905b37 | 8685 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
8686 | ; |
8687 | ||
9381e3f1 | 8688 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 8689 | (define_insn "sqrt<mode>2" |
62d3f261 AK |
8690 | [(set (match_operand:BFP 0 "register_operand" "=f,f,v") |
8691 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))] | |
142cd70f | 8692 | "TARGET_HARD_FLOAT" |
4023fb28 | 8693 | "@ |
f61a2c7d | 8694 | sq<xde>br\t%0,%1 |
6e5b5de8 AK |
8695 | sq<xde>b\t%0,%1 |
8696 | wfsqdb\t%v0,%v1" | |
8697 | [(set_attr "op_type" "RRE,RXE,VRR") | |
8698 | (set_attr "type" "fsqrt<mode>") | |
285363a1 | 8699 | (set_attr "cpu_facility" "*,*,vx") |
62d3f261 | 8700 | (set_attr "enabled" "*,<DSF>,<DFDI>")]) |
4023fb28 | 8701 | |
9db1d521 HP |
8702 | |
8703 | ;; | |
8704 | ;;- One complement instructions. | |
8705 | ;; | |
8706 | ||
8707 | ; | |
342cf42b | 8708 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 8709 | ; |
c7453384 | 8710 | |
342cf42b | 8711 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 8712 | [(parallel |
342cf42b AS |
8713 | [(set (match_operand:INT 0 "register_operand" "") |
8714 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
8715 | (const_int -1))) | |
ae156f85 | 8716 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 8717 | "" |
4023fb28 | 8718 | "") |
9db1d521 HP |
8719 | |
8720 | ||
ec24698e UW |
8721 | ;; |
8722 | ;; Find leftmost bit instructions. | |
8723 | ;; | |
8724 | ||
8725 | (define_expand "clzdi2" | |
8726 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8727 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 8728 | "TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e | 8729 | { |
d8485bdb TS |
8730 | rtx_insn *insn; |
8731 | rtx clz_equal; | |
ec24698e | 8732 | rtx wide_reg = gen_reg_rtx (TImode); |
406fde6e | 8733 | rtx msb = gen_rtx_CONST_INT (DImode, HOST_WIDE_INT_1U << 63); |
ec24698e UW |
8734 | |
8735 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
8736 | ||
8737 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
8738 | ||
9381e3f1 | 8739 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 8740 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
8741 | |
8742 | DONE; | |
8743 | }) | |
8744 | ||
33f3393a AK |
8745 | ; CLZ result is in hard reg op0 - this is the high part of the target operand |
8746 | ; The source with the left-most one bit cleared is in hard reg op0 + 1 - the low part | |
ec24698e UW |
8747 | (define_insn "clztidi2" |
8748 | [(set (match_operand:TI 0 "register_operand" "=d") | |
8749 | (ior:TI | |
33f3393a AK |
8750 | (ashift:TI (zero_extend:TI (clz:DI (match_operand:DI 1 "register_operand" "d"))) |
8751 | (const_int 64)) | |
8752 | (zero_extend:TI | |
8753 | (xor:DI (match_dup 1) | |
8754 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
8755 | (subreg:SI (clz:DI (match_dup 1)) 4)))))) | |
ec24698e | 8756 | (clobber (reg:CC CC_REGNUM))] |
406fde6e | 8757 | "UINTVAL (operands[2]) == HOST_WIDE_INT_1U << 63 |
9602b6a1 | 8758 | && TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
8759 | "flogr\t%0,%1" |
8760 | [(set_attr "op_type" "RRE")]) | |
8761 | ||
8762 | ||
9db1d521 HP |
8763 | ;; |
8764 | ;;- Rotate instructions. | |
8765 | ;; | |
8766 | ||
8767 | ; | |
9a91a21f | 8768 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
8769 | ; |
8770 | ||
191eb16d AK |
8771 | (define_expand "rotl<mode>3" |
8772 | [(set (match_operand:GPR 0 "register_operand" "") | |
8773 | (rotate:GPR (match_operand:GPR 1 "register_operand" "") | |
8774 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
8cc6307c | 8775 | "" |
191eb16d | 8776 | "") |
9db1d521 | 8777 | |
43a09b63 | 8778 | ; rll, rllg |
191eb16d AK |
8779 | (define_insn "*rotl<mode>3<addr_style_op><masked_op>" |
8780 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8781 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
8782 | (match_operand:SI 2 "nonmemory_operand" "an")))] | |
8cc6307c | 8783 | "" |
191eb16d | 8784 | "rll<g>\t%0,%1,<addr_style_op_ops>" |
4989e88a | 8785 | [(set_attr "op_type" "RSE") |
9381e3f1 | 8786 | (set_attr "atype" "reg") |
191eb16d | 8787 | (set_attr "z10prop" "z10_super_E1")]) |
4989e88a | 8788 | |
9db1d521 HP |
8789 | |
8790 | ;; | |
f337b930 | 8791 | ;;- Shift instructions. |
9db1d521 | 8792 | ;; |
9db1d521 HP |
8793 | |
8794 | ; | |
1b48c8cc | 8795 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
65b1d8ea | 8796 | ; Left shifts and logical right shifts |
9db1d521 | 8797 | |
1b48c8cc AS |
8798 | (define_expand "<shift><mode>3" |
8799 | [(set (match_operand:DSI 0 "register_operand" "") | |
8800 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
adf22b3f | 8801 | (match_operand:SI 2 "nonmemory_operand" "")))] |
9db1d521 HP |
8802 | "" |
8803 | "") | |
8804 | ||
adf22b3f | 8805 | ; ESA 64 bit register pair shift with reg or imm shift count |
43a09b63 | 8806 | ; sldl, srdl |
adf22b3f AK |
8807 | (define_insn "*<shift>di3_31<addr_style_op><masked_op>" |
8808 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8809 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
8810 | (match_operand:SI 2 "nonmemory_operand" "an")))] | |
9602b6a1 | 8811 | "!TARGET_ZARCH" |
adf22b3f | 8812 | "s<lr>dl\t%0,<addr_style_op_ops>" |
077dab3b | 8813 | [(set_attr "op_type" "RS") |
65b1d8ea AK |
8814 | (set_attr "atype" "reg") |
8815 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8816 | |
adf22b3f AK |
8817 | |
8818 | ; 64 bit register shift with reg or imm shift count | |
65b1d8ea | 8819 | ; sll, srl, sllg, srlg, sllk, srlk |
adf22b3f AK |
8820 | (define_insn "*<shift><mode>3<addr_style_op><masked_op>" |
8821 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
8822 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
8823 | (match_operand:SI 2 "nonmemory_operand" "an,an")))] | |
1b48c8cc | 8824 | "" |
65b1d8ea | 8825 | "@ |
adf22b3f AK |
8826 | s<lr>l<g>\t%0,<1><addr_style_op_ops> |
8827 | s<lr>l<gk>\t%0,%1,<addr_style_op_ops>" | |
65b1d8ea AK |
8828 | [(set_attr "op_type" "RS<E>,RSY") |
8829 | (set_attr "atype" "reg,reg") | |
8830 | (set_attr "cpu_facility" "*,z196") | |
adf22b3f | 8831 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8832 | |
9db1d521 | 8833 | ; |
1b48c8cc | 8834 | ; ashr(di|si)3 instruction pattern(s). |
65b1d8ea | 8835 | ; Arithmetic right shifts |
9db1d521 | 8836 | |
1b48c8cc | 8837 | (define_expand "ashr<mode>3" |
9db1d521 | 8838 | [(parallel |
1b48c8cc AS |
8839 | [(set (match_operand:DSI 0 "register_operand" "") |
8840 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
a9fcf821 | 8841 | (match_operand:SI 2 "nonmemory_operand" ""))) |
ae156f85 | 8842 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8843 | "" |
8844 | "") | |
8845 | ||
a9fcf821 AK |
8846 | ; FIXME: The number of alternatives is doubled here to match the fix |
8847 | ; number of 2 in the subst pattern for the (clobber (match_scratch... | |
8848 | ; The right fix should be to support match_scratch in the output | |
8849 | ; pattern of a define_subst. | |
8850 | (define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>" | |
8851 | [(set (match_operand:DI 0 "register_operand" "=d, d") | |
8852 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0, 0") | |
8853 | (match_operand:SI 2 "nonmemory_operand" "an,an"))) | |
ae156f85 | 8854 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8855 | "!TARGET_ZARCH" |
65b1d8ea | 8856 | "@ |
a9fcf821 AK |
8857 | srda\t%0,<addr_style_op_cc_ops> |
8858 | srda\t%0,<addr_style_op_cc_ops>" | |
8859 | [(set_attr "op_type" "RS") | |
8860 | (set_attr "atype" "reg")]) | |
ecbe845e | 8861 | |
ecbe845e | 8862 | |
43a09b63 | 8863 | ; sra, srag |
a9fcf821 AK |
8864 | (define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>" |
8865 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
8866 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
8867 | (match_operand:SI 2 "nonmemory_operand" "an,an"))) | |
ae156f85 | 8868 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc | 8869 | "" |
65b1d8ea | 8870 | "@ |
a9fcf821 AK |
8871 | sra<g>\t%0,<1><addr_style_op_cc_ops> |
8872 | sra<gk>\t%0,%1,<addr_style_op_cc_ops>" | |
65b1d8ea | 8873 | [(set_attr "op_type" "RS<E>,RSY") |
a9fcf821 | 8874 | (set_attr "atype" "reg") |
01496eca | 8875 | (set_attr "cpu_facility" "*,z196") |
65b1d8ea | 8876 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8877 | |
9db1d521 | 8878 | |
9db1d521 HP |
8879 | ;; |
8880 | ;; Branch instruction patterns. | |
8881 | ;; | |
8882 | ||
f90b7a5a | 8883 | (define_expand "cbranch<mode>4" |
fa77b251 | 8884 | [(set (pc) |
f90b7a5a PB |
8885 | (if_then_else (match_operator 0 "comparison_operator" |
8886 | [(match_operand:GPR 1 "register_operand" "") | |
8887 | (match_operand:GPR 2 "general_operand" "")]) | |
8888 | (label_ref (match_operand 3 "" "")) | |
fa77b251 | 8889 | (pc)))] |
ba956982 | 8890 | "" |
f90b7a5a PB |
8891 | "s390_emit_jump (operands[3], |
8892 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8893 | DONE;") | |
8894 | ||
8895 | (define_expand "cbranch<mode>4" | |
8896 | [(set (pc) | |
8897 | (if_then_else (match_operator 0 "comparison_operator" | |
8898 | [(match_operand:FP 1 "register_operand" "") | |
8899 | (match_operand:FP 2 "general_operand" "")]) | |
8900 | (label_ref (match_operand 3 "" "")) | |
8901 | (pc)))] | |
8902 | "TARGET_HARD_FLOAT" | |
8903 | "s390_emit_jump (operands[3], | |
8904 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8905 | DONE;") | |
8906 | ||
8907 | (define_expand "cbranchcc4" | |
8908 | [(set (pc) | |
de6fba39 | 8909 | (if_then_else (match_operator 0 "s390_comparison" |
f90b7a5a | 8910 | [(match_operand 1 "cc_reg_operand" "") |
de6fba39 | 8911 | (match_operand 2 "const_int_operand" "")]) |
f90b7a5a PB |
8912 | (label_ref (match_operand 3 "" "")) |
8913 | (pc)))] | |
de6fba39 UW |
8914 | "" |
8915 | "") | |
ba956982 | 8916 | |
9db1d521 HP |
8917 | |
8918 | ;; | |
8919 | ;;- Conditional jump instructions. | |
8920 | ;; | |
8921 | ||
6590e19a UW |
8922 | (define_insn "*cjump_64" |
8923 | [(set (pc) | |
8924 | (if_then_else | |
5a3fe9b6 AK |
8925 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
8926 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
8927 | (label_ref (match_operand 0 "" "")) |
8928 | (pc)))] | |
8cc6307c | 8929 | "" |
9db1d521 | 8930 | { |
13e58269 | 8931 | if (get_attr_length (insn) == 4) |
d40c829f | 8932 | return "j%C1\t%l0"; |
6590e19a | 8933 | else |
d40c829f | 8934 | return "jg%C1\t%l0"; |
6590e19a UW |
8935 | } |
8936 | [(set_attr "op_type" "RI") | |
8937 | (set_attr "type" "branch") | |
8938 | (set (attr "length") | |
8939 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8940 | (const_int 4) (const_int 6)))]) | |
8941 | ||
f314b9b1 | 8942 | (define_insn "*cjump_long" |
6590e19a UW |
8943 | [(set (pc) |
8944 | (if_then_else | |
ae156f85 | 8945 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4fe6dea8 | 8946 | (match_operand 0 "address_operand" "ZQZR") |
6590e19a | 8947 | (pc)))] |
84b4c7b5 | 8948 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
f314b9b1 UW |
8949 | { |
8950 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8951 | return "b%C1r\t%0"; |
f314b9b1 | 8952 | else |
d40c829f | 8953 | return "b%C1\t%a0"; |
10bbf137 | 8954 | } |
c7453384 | 8955 | [(set (attr "op_type") |
f314b9b1 UW |
8956 | (if_then_else (match_operand 0 "register_operand" "") |
8957 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
8958 | (set (attr "mnemonic") |
8959 | (if_then_else (match_operand 0 "register_operand" "") | |
8960 | (const_string "bcr") (const_string "bc"))) | |
6590e19a | 8961 | (set_attr "type" "branch") |
077dab3b | 8962 | (set_attr "atype" "agen")]) |
9db1d521 | 8963 | |
177bc204 RS |
8964 | ;; A conditional return instruction. |
8965 | (define_insn "*c<code>" | |
8966 | [(set (pc) | |
8967 | (if_then_else | |
8968 | (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
8969 | (ANY_RETURN) | |
8970 | (pc)))] | |
8971 | "s390_can_use_<code>_insn ()" | |
84b4c7b5 AK |
8972 | { |
8973 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
8974 | { | |
8975 | s390_indirect_branch_via_thunk (RETURN_REGNUM, | |
8976 | INVALID_REGNUM, | |
8977 | operands[0], | |
8978 | s390_indirect_branch_type_return); | |
8979 | return ""; | |
8980 | } | |
8981 | else | |
8982 | return "b%C0r\t%%r14"; | |
8983 | } | |
8984 | [(set (attr "op_type") | |
8985 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
8986 | (const_string "RIL") | |
8987 | (const_string "RR"))) | |
8988 | (set (attr "mnemonic") | |
8989 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
8990 | (const_string "brcl") | |
8991 | (const_string "bcr"))) | |
177bc204 RS |
8992 | (set_attr "type" "jsr") |
8993 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
8994 | |
8995 | ;; | |
8996 | ;;- Negated conditional jump instructions. | |
8997 | ;; | |
8998 | ||
6590e19a UW |
8999 | (define_insn "*icjump_64" |
9000 | [(set (pc) | |
9001 | (if_then_else | |
ae156f85 | 9002 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
9003 | (pc) |
9004 | (label_ref (match_operand 0 "" ""))))] | |
8cc6307c | 9005 | "" |
c7453384 | 9006 | { |
13e58269 | 9007 | if (get_attr_length (insn) == 4) |
d40c829f | 9008 | return "j%D1\t%l0"; |
6590e19a | 9009 | else |
d40c829f | 9010 | return "jg%D1\t%l0"; |
6590e19a UW |
9011 | } |
9012 | [(set_attr "op_type" "RI") | |
9013 | (set_attr "type" "branch") | |
9014 | (set (attr "length") | |
9015 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9016 | (const_int 4) (const_int 6)))]) | |
9017 | ||
f314b9b1 | 9018 | (define_insn "*icjump_long" |
6590e19a UW |
9019 | [(set (pc) |
9020 | (if_then_else | |
ae156f85 | 9021 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a | 9022 | (pc) |
4fe6dea8 | 9023 | (match_operand 0 "address_operand" "ZQZR")))] |
84b4c7b5 | 9024 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
f314b9b1 UW |
9025 | { |
9026 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9027 | return "b%D1r\t%0"; |
f314b9b1 | 9028 | else |
d40c829f | 9029 | return "b%D1\t%a0"; |
10bbf137 | 9030 | } |
c7453384 | 9031 | [(set (attr "op_type") |
f314b9b1 UW |
9032 | (if_then_else (match_operand 0 "register_operand" "") |
9033 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
9034 | (set (attr "mnemonic") |
9035 | (if_then_else (match_operand 0 "register_operand" "") | |
9036 | (const_string "bcr") (const_string "bc"))) | |
077dab3b HP |
9037 | (set_attr "type" "branch") |
9038 | (set_attr "atype" "agen")]) | |
9db1d521 | 9039 | |
4456530d HP |
9040 | ;; |
9041 | ;;- Trap instructions. | |
9042 | ;; | |
9043 | ||
9044 | (define_insn "trap" | |
9045 | [(trap_if (const_int 1) (const_int 0))] | |
9046 | "" | |
d40c829f | 9047 | "j\t.+2" |
6590e19a | 9048 | [(set_attr "op_type" "RI") |
077dab3b | 9049 | (set_attr "type" "branch")]) |
4456530d | 9050 | |
f90b7a5a PB |
9051 | (define_expand "ctrap<mode>4" |
9052 | [(trap_if (match_operator 0 "comparison_operator" | |
9053 | [(match_operand:GPR 1 "register_operand" "") | |
9054 | (match_operand:GPR 2 "general_operand" "")]) | |
9055 | (match_operand 3 "const0_operand" ""))] | |
4456530d | 9056 | "" |
f90b7a5a PB |
9057 | { |
9058 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
9059 | operands[1], operands[2]); | |
9060 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
9061 | DONE; | |
9062 | }) | |
9063 | ||
9064 | (define_expand "ctrap<mode>4" | |
9065 | [(trap_if (match_operator 0 "comparison_operator" | |
9066 | [(match_operand:FP 1 "register_operand" "") | |
9067 | (match_operand:FP 2 "general_operand" "")]) | |
9068 | (match_operand 3 "const0_operand" ""))] | |
9069 | "" | |
9070 | { | |
9071 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
9072 | operands[1], operands[2]); | |
9073 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
9074 | DONE; | |
9075 | }) | |
4456530d | 9076 | |
f90b7a5a PB |
9077 | (define_insn "condtrap" |
9078 | [(trap_if (match_operator 0 "s390_comparison" | |
9079 | [(match_operand 1 "cc_reg_operand" "c") | |
9080 | (const_int 0)]) | |
4456530d HP |
9081 | (const_int 0))] |
9082 | "" | |
d40c829f | 9083 | "j%C0\t.+2"; |
077dab3b HP |
9084 | [(set_attr "op_type" "RI") |
9085 | (set_attr "type" "branch")]) | |
9db1d521 | 9086 | |
963fc8d0 AK |
9087 | ; crt, cgrt, cit, cgit |
9088 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
9089 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
9090 | [(match_operand:GPR 1 "register_operand" "d,d") | |
9091 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
9092 | (const_int 0))] | |
9093 | "TARGET_Z10" | |
9094 | "@ | |
9095 | c<g>rt%C0\t%1,%2 | |
9096 | c<g>it%C0\t%1,%h2" | |
9097 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 9098 | (set_attr "type" "branch") |
729e750f | 9099 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 9100 | |
22ac2c2f | 9101 | ; clrt, clgrt, clfit, clgit, clt, clgt |
963fc8d0 AK |
9102 | (define_insn "*cmp_and_trap_unsigned_int<mode>" |
9103 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
3e4be43f UW |
9104 | [(match_operand:GPR 1 "register_operand" "d,d,d") |
9105 | (match_operand:GPR 2 "general_operand" "d,D,T")]) | |
963fc8d0 AK |
9106 | (const_int 0))] |
9107 | "TARGET_Z10" | |
9108 | "@ | |
9109 | cl<g>rt%C0\t%1,%2 | |
22ac2c2f AK |
9110 | cl<gf>it%C0\t%1,%x2 |
9111 | cl<g>t%C0\t%1,%2" | |
9112 | [(set_attr "op_type" "RRF,RIE,RSY") | |
9113 | (set_attr "type" "branch") | |
9114 | (set_attr "z10prop" "z10_super_c,z10_super,*") | |
9115 | (set_attr "cpu_facility" "z10,z10,zEC12")]) | |
9116 | ||
9117 | ; lat, lgat | |
9118 | (define_insn "*load_and_trap<mode>" | |
3e4be43f | 9119 | [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T") |
22ac2c2f AK |
9120 | (const_int 0)) |
9121 | (const_int 0)) | |
9122 | (set (match_operand:GPR 1 "register_operand" "=d") | |
9123 | (match_dup 0))] | |
9124 | "TARGET_ZEC12" | |
9125 | "l<g>at\t%1,%0" | |
9126 | [(set_attr "op_type" "RXY")]) | |
9127 | ||
963fc8d0 | 9128 | |
9db1d521 | 9129 | ;; |
0a3bdf9d | 9130 | ;;- Loop instructions. |
9db1d521 | 9131 | ;; |
0a3bdf9d UW |
9132 | ;; This is all complicated by the fact that since this is a jump insn |
9133 | ;; we must handle our own output reloads. | |
c7453384 | 9134 | |
f1149235 AK |
9135 | ;; branch on index |
9136 | ||
9137 | ; This splitter will be matched by combine and has to add the 2 moves | |
9138 | ; necessary to load the compare and the increment values into a | |
9139 | ; register pair as needed by brxle. | |
9140 | ||
9141 | (define_insn_and_split "*brx_stage1_<GPR:mode>" | |
9142 | [(set (pc) | |
9143 | (if_then_else | |
9144 | (match_operator 6 "s390_brx_operator" | |
9145 | [(plus:GPR (match_operand:GPR 1 "register_operand" "") | |
9146 | (match_operand:GPR 2 "general_operand" "")) | |
9147 | (match_operand:GPR 3 "register_operand" "")]) | |
9148 | (label_ref (match_operand 0 "" "")) | |
9149 | (pc))) | |
9150 | (set (match_operand:GPR 4 "nonimmediate_operand" "") | |
9151 | (plus:GPR (match_dup 1) (match_dup 2))) | |
9152 | (clobber (match_scratch:GPR 5 ""))] | |
8cc6307c | 9153 | "" |
f1149235 AK |
9154 | "#" |
9155 | "!reload_completed && !reload_in_progress" | |
9156 | [(set (match_dup 7) (match_dup 2)) ; the increment | |
9157 | (set (match_dup 8) (match_dup 3)) ; the comparison value | |
9158 | (parallel [(set (pc) | |
9159 | (if_then_else | |
9160 | (match_op_dup 6 | |
9161 | [(plus:GPR (match_dup 1) (match_dup 7)) | |
9162 | (match_dup 8)]) | |
9163 | (label_ref (match_dup 0)) | |
9164 | (pc))) | |
9165 | (set (match_dup 4) | |
9166 | (plus:GPR (match_dup 1) (match_dup 7))) | |
9167 | (clobber (match_dup 5)) | |
9168 | (clobber (reg:CC CC_REGNUM))])] | |
9169 | { | |
9170 | rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); | |
9171 | operands[7] = gen_lowpart (<GPR:MODE>mode, | |
9172 | gen_highpart (word_mode, dreg)); | |
9173 | operands[8] = gen_lowpart (<GPR:MODE>mode, | |
9174 | gen_lowpart (word_mode, dreg)); | |
9175 | }) | |
9176 | ||
9177 | ; brxlg, brxhg | |
9178 | ||
9179 | (define_insn_and_split "*brxg_64bit" | |
9180 | [(set (pc) | |
9181 | (if_then_else | |
9182 | (match_operator 5 "s390_brx_operator" | |
9183 | [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") | |
9184 | (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) | |
9185 | (subreg:DI (match_dup 2) 8)]) | |
9186 | (label_ref (match_operand 0 "" "")) | |
9187 | (pc))) | |
9188 | (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") | |
9189 | (plus:DI (match_dup 1) | |
9190 | (subreg:DI (match_dup 2) 0))) | |
9191 | (clobber (match_scratch:DI 4 "=X,&1,&?d")) | |
9192 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9193 | "TARGET_ZARCH" |
f1149235 AK |
9194 | { |
9195 | if (which_alternative != 0) | |
9196 | return "#"; | |
9197 | else if (get_attr_length (insn) == 6) | |
9198 | return "brx%E5g\t%1,%2,%l0"; | |
9199 | else | |
9200 | return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; | |
9201 | } | |
9202 | "&& reload_completed | |
9203 | && (!REG_P (operands[3]) | |
9204 | || !rtx_equal_p (operands[1], operands[3]))" | |
9205 | [(set (match_dup 4) (match_dup 1)) | |
9206 | (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) | |
9207 | (clobber (reg:CC CC_REGNUM))]) | |
9208 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) | |
9209 | (set (match_dup 3) (match_dup 4)) | |
9210 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9211 | (label_ref (match_dup 0)) | |
9212 | (pc)))] | |
9213 | "" | |
9214 | [(set_attr "op_type" "RIE") | |
9215 | (set_attr "type" "branch") | |
9216 | (set (attr "length") | |
9217 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9218 | (const_int 6) (const_int 16)))]) | |
9219 | ||
9220 | ; brxle, brxh | |
9221 | ||
9222 | (define_insn_and_split "*brx_64bit" | |
9223 | [(set (pc) | |
9224 | (if_then_else | |
9225 | (match_operator 5 "s390_brx_operator" | |
9226 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9227 | (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) | |
9228 | (subreg:SI (match_dup 2) 12)]) | |
9229 | (label_ref (match_operand 0 "" "")) | |
9230 | (pc))) | |
9231 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9232 | (plus:SI (match_dup 1) | |
9233 | (subreg:SI (match_dup 2) 4))) | |
9234 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9235 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9236 | "TARGET_ZARCH" |
f1149235 AK |
9237 | { |
9238 | if (which_alternative != 0) | |
9239 | return "#"; | |
9240 | else if (get_attr_length (insn) == 6) | |
9241 | return "brx%C5\t%1,%2,%l0"; | |
9242 | else | |
9243 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9244 | } | |
9245 | "&& reload_completed | |
9246 | && (!REG_P (operands[3]) | |
9247 | || !rtx_equal_p (operands[1], operands[3]))" | |
9248 | [(set (match_dup 4) (match_dup 1)) | |
9249 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9250 | (clobber (reg:CC CC_REGNUM))]) | |
9251 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) | |
9252 | (set (match_dup 3) (match_dup 4)) | |
9253 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9254 | (label_ref (match_dup 0)) | |
9255 | (pc)))] | |
9256 | "" | |
9257 | [(set_attr "op_type" "RSI") | |
9258 | (set_attr "type" "branch") | |
9259 | (set (attr "length") | |
9260 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9261 | (const_int 6) (const_int 14)))]) | |
9262 | ||
9263 | ; brxle, brxh | |
9264 | ||
9265 | (define_insn_and_split "*brx_31bit" | |
9266 | [(set (pc) | |
9267 | (if_then_else | |
9268 | (match_operator 5 "s390_brx_operator" | |
9269 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9270 | (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) | |
9271 | (subreg:SI (match_dup 2) 4)]) | |
9272 | (label_ref (match_operand 0 "" "")) | |
9273 | (pc))) | |
9274 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9275 | (plus:SI (match_dup 1) | |
9276 | (subreg:SI (match_dup 2) 0))) | |
9277 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9278 | (clobber (reg:CC CC_REGNUM))] | |
8cc6307c | 9279 | "!TARGET_ZARCH" |
f1149235 AK |
9280 | { |
9281 | if (which_alternative != 0) | |
9282 | return "#"; | |
9283 | else if (get_attr_length (insn) == 6) | |
9284 | return "brx%C5\t%1,%2,%l0"; | |
9285 | else | |
9286 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9287 | } | |
9288 | "&& reload_completed | |
9289 | && (!REG_P (operands[3]) | |
9290 | || !rtx_equal_p (operands[1], operands[3]))" | |
9291 | [(set (match_dup 4) (match_dup 1)) | |
9292 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) | |
9293 | (clobber (reg:CC CC_REGNUM))]) | |
9294 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9295 | (set (match_dup 3) (match_dup 4)) | |
9296 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9297 | (label_ref (match_dup 0)) | |
9298 | (pc)))] | |
9299 | "" | |
9300 | [(set_attr "op_type" "RSI") | |
9301 | (set_attr "type" "branch") | |
9302 | (set (attr "length") | |
9303 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9304 | (const_int 6) (const_int 14)))]) | |
9305 | ||
9306 | ||
9307 | ;; branch on count | |
9308 | ||
0a3bdf9d UW |
9309 | (define_expand "doloop_end" |
9310 | [(use (match_operand 0 "" "")) ; loop pseudo | |
1d0216c8 | 9311 | (use (match_operand 1 "" ""))] ; label |
0a3bdf9d | 9312 | "" |
0a3bdf9d | 9313 | { |
8cc6307c | 9314 | if (GET_MODE (operands[0]) == SImode) |
1d0216c8 | 9315 | emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0])); |
9602b6a1 | 9316 | else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) |
1d0216c8 | 9317 | emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0])); |
0a3bdf9d UW |
9318 | else |
9319 | FAIL; | |
9320 | ||
9321 | DONE; | |
10bbf137 | 9322 | }) |
0a3bdf9d | 9323 | |
6590e19a | 9324 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
9325 | [(set (pc) |
9326 | (if_then_else | |
7e665d18 | 9327 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9328 | (const_int 1)) |
9329 | (label_ref (match_operand 0 "" "")) | |
9330 | (pc))) | |
7e665d18 | 9331 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9332 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9333 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9334 | (clobber (reg:CC CC_REGNUM))] |
8cc6307c | 9335 | "" |
0a3bdf9d UW |
9336 | { |
9337 | if (which_alternative != 0) | |
10bbf137 | 9338 | return "#"; |
0a3bdf9d | 9339 | else if (get_attr_length (insn) == 4) |
d40c829f | 9340 | return "brct\t%1,%l0"; |
6590e19a | 9341 | else |
545d16ff | 9342 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
9343 | } |
9344 | "&& reload_completed | |
9345 | && (! REG_P (operands[2]) | |
9346 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9347 | [(set (match_dup 3) (match_dup 1)) |
9348 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9349 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9350 | (const_int 0))) | |
9351 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9352 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9353 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9354 | (label_ref (match_dup 0)) |
9355 | (pc)))] | |
9356 | "" | |
9357 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9358 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9359 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9360 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9361 | (set_attr "type" "branch") |
9362 | (set (attr "length") | |
9363 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9364 | (const_int 4) (const_int 10)))]) | |
9365 | ||
6590e19a | 9366 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
9367 | [(set (pc) |
9368 | (if_then_else | |
7e665d18 | 9369 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9370 | (const_int 1)) |
9371 | (label_ref (match_operand 0 "" "")) | |
9372 | (pc))) | |
7e665d18 | 9373 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9374 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 9375 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 9376 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 9377 | "TARGET_ZARCH" |
0a3bdf9d UW |
9378 | { |
9379 | if (which_alternative != 0) | |
10bbf137 | 9380 | return "#"; |
0a3bdf9d | 9381 | else if (get_attr_length (insn) == 4) |
d40c829f | 9382 | return "brctg\t%1,%l0"; |
0a3bdf9d | 9383 | else |
545d16ff | 9384 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 9385 | } |
6590e19a | 9386 | "&& reload_completed |
0a3bdf9d UW |
9387 | && (! REG_P (operands[2]) |
9388 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9389 | [(set (match_dup 3) (match_dup 1)) |
9390 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
9391 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
9392 | (const_int 0))) | |
9393 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
9394 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9395 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 9396 | (label_ref (match_dup 0)) |
0a3bdf9d | 9397 | (pc)))] |
6590e19a UW |
9398 | "" |
9399 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9400 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9401 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9402 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9403 | (set_attr "type" "branch") |
9404 | (set (attr "length") | |
9405 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9406 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
9407 | |
9408 | ;; | |
9409 | ;;- Unconditional jump instructions. | |
9410 | ;; | |
9411 | ||
9412 | ; | |
9413 | ; jump instruction pattern(s). | |
9414 | ; | |
9415 | ||
6590e19a UW |
9416 | (define_expand "jump" |
9417 | [(match_operand 0 "" "")] | |
9db1d521 | 9418 | "" |
6590e19a UW |
9419 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
9420 | ||
9421 | (define_insn "*jump64" | |
9422 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
8cc6307c | 9423 | "" |
9db1d521 | 9424 | { |
13e58269 | 9425 | if (get_attr_length (insn) == 4) |
d40c829f | 9426 | return "j\t%l0"; |
6590e19a | 9427 | else |
d40c829f | 9428 | return "jg\t%l0"; |
6590e19a UW |
9429 | } |
9430 | [(set_attr "op_type" "RI") | |
9431 | (set_attr "type" "branch") | |
9432 | (set (attr "length") | |
9433 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9434 | (const_int 4) (const_int 6)))]) | |
9435 | ||
9db1d521 HP |
9436 | ; |
9437 | ; indirect-jump instruction pattern(s). | |
9438 | ; | |
9439 | ||
2841f550 AK |
9440 | (define_expand "indirect_jump" |
9441 | [(set (pc) (match_operand 0 "nonimmediate_operand" ""))] | |
9db1d521 | 9442 | "" |
f314b9b1 | 9443 | { |
2841f550 AK |
9444 | if (address_operand (operands[0], GET_MODE (operands[0]))) |
9445 | ; | |
e9e8efc9 | 9446 | else if (TARGET_Z14 |
2841f550 AK |
9447 | && GET_MODE (operands[0]) == Pmode |
9448 | && memory_operand (operands[0], Pmode)) | |
9449 | ; | |
f314b9b1 | 9450 | else |
2841f550 | 9451 | operands[0] = force_reg (Pmode, operands[0]); |
84b4c7b5 AK |
9452 | |
9453 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK) | |
9454 | { | |
9455 | operands[0] = force_reg (Pmode, operands[0]); | |
9456 | if (TARGET_CPU_Z10) | |
9457 | { | |
9458 | if (TARGET_64BIT) | |
9459 | emit_jump_insn (gen_indirect_jump_via_thunkdi_z10 (operands[0])); | |
9460 | else | |
9461 | emit_jump_insn (gen_indirect_jump_via_thunksi_z10 (operands[0])); | |
9462 | } | |
9463 | else | |
9464 | { | |
9465 | if (TARGET_64BIT) | |
9466 | emit_jump_insn (gen_indirect_jump_via_thunkdi (operands[0])); | |
9467 | else | |
9468 | emit_jump_insn (gen_indirect_jump_via_thunksi (operands[0])); | |
9469 | } | |
9470 | DONE; | |
9471 | } | |
9472 | ||
9473 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK) | |
9474 | { | |
9475 | operands[0] = force_reg (Pmode, operands[0]); | |
9476 | rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
9477 | if (TARGET_CPU_Z10) | |
9478 | { | |
9479 | if (TARGET_64BIT) | |
9480 | emit_jump_insn (gen_indirect_jump_via_inlinethunkdi_z10 (operands[0], | |
9481 | label_ref)); | |
9482 | else | |
9483 | emit_jump_insn (gen_indirect_jump_via_inlinethunksi_z10 (operands[0], | |
9484 | label_ref)); | |
9485 | } | |
9486 | else | |
9487 | { | |
9488 | if (TARGET_64BIT) | |
9489 | emit_jump_insn (gen_indirect_jump_via_inlinethunkdi (operands[0], | |
9490 | label_ref, | |
9491 | force_reg (Pmode, label_ref))); | |
9492 | else | |
9493 | emit_jump_insn (gen_indirect_jump_via_inlinethunksi (operands[0], | |
9494 | label_ref, | |
9495 | force_reg (Pmode, label_ref))); | |
9496 | } | |
9497 | DONE; | |
9498 | } | |
2841f550 AK |
9499 | }) |
9500 | ||
9501 | (define_insn "*indirect_jump" | |
9502 | [(set (pc) | |
84b4c7b5 AK |
9503 | (match_operand 0 "address_operand" "ZR"))] |
9504 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK" | |
9505 | { | |
9506 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9507 | return "br\t%0"; | |
9508 | else | |
9509 | return "b\t%a0"; | |
9510 | } | |
9511 | [(set (attr "op_type") | |
9512 | (if_then_else (match_operand 0 "register_operand" "") | |
9513 | (const_string "RR") (const_string "RX"))) | |
9514 | (set (attr "mnemonic") | |
9515 | (if_then_else (match_operand 0 "register_operand" "") | |
9516 | (const_string "br") (const_string "b"))) | |
2841f550 | 9517 | (set_attr "type" "branch") |
84b4c7b5 AK |
9518 | (set_attr "atype" "agen")]) |
9519 | ||
9520 | (define_insn "indirect_jump_via_thunk<mode>_z10" | |
9521 | [(set (pc) | |
9522 | (match_operand:P 0 "register_operand" "a"))] | |
9523 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9524 | && TARGET_CPU_Z10" | |
9525 | { | |
9526 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9527 | INVALID_REGNUM, | |
9528 | NULL_RTX, | |
9529 | s390_indirect_branch_type_jump); | |
9530 | return ""; | |
9531 | } | |
9532 | [(set_attr "op_type" "RIL") | |
9533 | (set_attr "mnemonic" "jg") | |
9534 | (set_attr "type" "branch") | |
9535 | (set_attr "atype" "agen")]) | |
9536 | ||
9537 | (define_insn "indirect_jump_via_thunk<mode>" | |
9538 | [(set (pc) | |
9539 | (match_operand:P 0 "register_operand" " a")) | |
9540 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
9541 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9542 | && !TARGET_CPU_Z10" | |
9543 | { | |
9544 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9545 | INVALID_REGNUM, | |
9546 | NULL_RTX, | |
9547 | s390_indirect_branch_type_jump); | |
9548 | return ""; | |
9549 | } | |
9550 | [(set_attr "op_type" "RIL") | |
9551 | (set_attr "mnemonic" "jg") | |
9552 | (set_attr "type" "branch") | |
9553 | (set_attr "atype" "agen")]) | |
9554 | ||
9555 | ||
9556 | ; The label_ref is wrapped into an if_then_else in order to hide it | |
9557 | ; from mark_jump_label. Without this the label_ref would become the | |
9558 | ; ONLY jump target of that jump breaking the control flow graph. | |
9559 | (define_insn "indirect_jump_via_inlinethunk<mode>_z10" | |
9560 | [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X") | |
9561 | (const_int 0) | |
9562 | (const_int 0)) | |
9563 | (const_int 0)] UNSPEC_EXECUTE_JUMP) | |
9564 | (set (pc) (match_operand:P 0 "register_operand" "a"))] | |
9565 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9566 | && TARGET_CPU_Z10" | |
9567 | { | |
9568 | s390_indirect_branch_via_inline_thunk (operands[1]); | |
9569 | return ""; | |
9570 | } | |
9571 | [(set_attr "op_type" "RIL") | |
9572 | (set_attr "type" "branch") | |
9573 | (set_attr "length" "10")]) | |
9574 | ||
9575 | (define_insn "indirect_jump_via_inlinethunk<mode>" | |
9576 | [(unspec [(if_then_else (match_operand:P 1 "larl_operand" "X") | |
9577 | (const_int 0) | |
9578 | (const_int 0)) | |
9579 | (match_operand:P 2 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) | |
9580 | (set (pc) (match_operand:P 0 "register_operand" "a"))] | |
9581 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9582 | && !TARGET_CPU_Z10" | |
9583 | { | |
9584 | s390_indirect_branch_via_inline_thunk (operands[2]); | |
9585 | return ""; | |
9586 | } | |
9587 | [(set_attr "op_type" "RX") | |
9588 | (set_attr "type" "branch") | |
9589 | (set_attr "length" "8")]) | |
2841f550 AK |
9590 | |
9591 | ; FIXME: LRA does not appear to be able to deal with MEMs being | |
9592 | ; checked against address constraints like ZR above. So make this a | |
9593 | ; separate pattern for now. | |
9594 | (define_insn "*indirect2_jump" | |
9595 | [(set (pc) | |
9596 | (match_operand 0 "nonimmediate_operand" "a,T"))] | |
84b4c7b5 | 9597 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP" |
2841f550 AK |
9598 | "@ |
9599 | br\t%0 | |
9600 | bi\t%0" | |
9601 | [(set_attr "op_type" "RR,RXY") | |
9602 | (set_attr "type" "branch") | |
9603 | (set_attr "atype" "agen") | |
e9e8efc9 | 9604 | (set_attr "cpu_facility" "*,z14")]) |
9db1d521 HP |
9605 | |
9606 | ; | |
f314b9b1 | 9607 | ; casesi instruction pattern(s). |
9db1d521 HP |
9608 | ; |
9609 | ||
84b4c7b5 AK |
9610 | (define_expand "casesi_jump" |
9611 | [(parallel | |
9612 | [(set (pc) (match_operand 0 "address_operand")) | |
9613 | (use (label_ref (match_operand 1 "")))])] | |
9db1d521 | 9614 | "" |
84b4c7b5 AK |
9615 | { |
9616 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK) | |
9617 | { | |
9618 | operands[0] = force_reg (GET_MODE (operands[0]), operands[0]); | |
9619 | ||
9620 | if (TARGET_CPU_Z10) | |
9621 | { | |
9622 | if (TARGET_64BIT) | |
9623 | emit_jump_insn (gen_casesi_jump_via_thunkdi_z10 (operands[0], | |
9624 | operands[1])); | |
9625 | else | |
9626 | emit_jump_insn (gen_casesi_jump_via_thunksi_z10 (operands[0], | |
9627 | operands[1])); | |
9628 | } | |
9629 | else | |
9630 | { | |
9631 | if (TARGET_64BIT) | |
9632 | emit_jump_insn (gen_casesi_jump_via_thunkdi (operands[0], | |
9633 | operands[1])); | |
9634 | else | |
9635 | emit_jump_insn (gen_casesi_jump_via_thunksi (operands[0], | |
9636 | operands[1])); | |
9637 | } | |
9638 | DONE; | |
9639 | } | |
9640 | ||
9641 | if (TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK) | |
9642 | { | |
9643 | operands[0] = force_reg (Pmode, operands[0]); | |
9644 | rtx label_ref = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ()); | |
9645 | if (TARGET_CPU_Z10) | |
9646 | { | |
9647 | if (TARGET_64BIT) | |
9648 | emit_jump_insn (gen_casesi_jump_via_inlinethunkdi_z10 (operands[0], | |
9649 | operands[1], | |
9650 | label_ref)); | |
9651 | else | |
9652 | emit_jump_insn (gen_casesi_jump_via_inlinethunksi_z10 (operands[0], | |
9653 | operands[1], | |
9654 | label_ref)); | |
9655 | } | |
9656 | else | |
9657 | { | |
9658 | if (TARGET_64BIT) | |
9659 | emit_jump_insn (gen_casesi_jump_via_inlinethunkdi (operands[0], | |
9660 | operands[1], | |
9661 | label_ref, | |
9662 | force_reg (Pmode, label_ref))); | |
9663 | else | |
9664 | emit_jump_insn (gen_casesi_jump_via_inlinethunksi (operands[0], | |
9665 | operands[1], | |
9666 | label_ref, | |
9667 | force_reg (Pmode, label_ref))); | |
9668 | } | |
9669 | DONE; | |
9670 | } | |
9671 | }) | |
9672 | ||
9673 | (define_insn "*casesi_jump" | |
9674 | [(set (pc) (match_operand 0 "address_operand" "ZR")) | |
9675 | (use (label_ref (match_operand 1 "" "")))] | |
9676 | "!TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK" | |
9db1d521 | 9677 | { |
f314b9b1 | 9678 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 9679 | return "br\t%0"; |
f314b9b1 | 9680 | else |
d40c829f | 9681 | return "b\t%a0"; |
10bbf137 | 9682 | } |
c7453384 | 9683 | [(set (attr "op_type") |
f314b9b1 UW |
9684 | (if_then_else (match_operand 0 "register_operand" "") |
9685 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
9686 | (set (attr "mnemonic") |
9687 | (if_then_else (match_operand 0 "register_operand" "") | |
9688 | (const_string "br") (const_string "b"))) | |
9689 | (set_attr "type" "branch") | |
9690 | (set_attr "atype" "agen")]) | |
9691 | ||
9692 | (define_insn "casesi_jump_via_thunk<mode>_z10" | |
9693 | [(set (pc) (match_operand:P 0 "register_operand" "a")) | |
9694 | (use (label_ref (match_operand 1 "" "")))] | |
9695 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9696 | && TARGET_CPU_Z10" | |
9697 | { | |
9698 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9699 | INVALID_REGNUM, | |
9700 | NULL_RTX, | |
9701 | s390_indirect_branch_type_jump); | |
9702 | return ""; | |
9703 | } | |
9704 | [(set_attr "op_type" "RIL") | |
9705 | (set_attr "mnemonic" "jg") | |
9706 | (set_attr "type" "branch") | |
9707 | (set_attr "atype" "agen")]) | |
9708 | ||
9709 | (define_insn "casesi_jump_via_thunk<mode>" | |
9710 | [(set (pc) (match_operand:P 0 "register_operand" "a")) | |
9711 | (use (label_ref (match_operand 1 "" ""))) | |
9712 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
9713 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_THUNK | |
9714 | && !TARGET_CPU_Z10" | |
9715 | { | |
9716 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
9717 | INVALID_REGNUM, | |
9718 | NULL_RTX, | |
9719 | s390_indirect_branch_type_jump); | |
9720 | return ""; | |
9721 | } | |
9722 | [(set_attr "op_type" "RIL") | |
9723 | (set_attr "mnemonic" "jg") | |
077dab3b HP |
9724 | (set_attr "type" "branch") |
9725 | (set_attr "atype" "agen")]) | |
9db1d521 | 9726 | |
84b4c7b5 AK |
9727 | |
9728 | ; The label_ref is wrapped into an if_then_else in order to hide it | |
9729 | ; from mark_jump_label. Without this the label_ref would become the | |
9730 | ; ONLY jump target of that jump breaking the control flow graph. | |
9731 | (define_insn "casesi_jump_via_inlinethunk<mode>_z10" | |
9732 | [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X") | |
9733 | (const_int 0) | |
9734 | (const_int 0)) | |
9735 | (const_int 0)] UNSPEC_EXECUTE_JUMP) | |
9736 | (set (pc) (match_operand:P 0 "register_operand" "a")) | |
9737 | (use (label_ref (match_operand 1 "" "")))] | |
9738 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9739 | && TARGET_CPU_Z10" | |
9740 | { | |
9741 | s390_indirect_branch_via_inline_thunk (operands[2]); | |
9742 | return ""; | |
9743 | } | |
9744 | [(set_attr "op_type" "RIL") | |
9745 | (set_attr "type" "cs") | |
9746 | (set_attr "length" "10")]) | |
9747 | ||
9748 | (define_insn "casesi_jump_via_inlinethunk<mode>" | |
9749 | [(unspec [(if_then_else (match_operand:P 2 "larl_operand" "X") | |
9750 | (const_int 0) | |
9751 | (const_int 0)) | |
9752 | (match_operand:P 3 "register_operand" "a")] UNSPEC_EXECUTE_JUMP) | |
9753 | (set (pc) (match_operand:P 0 "register_operand" "a")) | |
9754 | (use (label_ref (match_operand 1 "" "")))] | |
9755 | "TARGET_INDIRECT_BRANCH_NOBP_JUMP_INLINE_THUNK | |
9756 | && !TARGET_CPU_Z10" | |
9757 | { | |
9758 | s390_indirect_branch_via_inline_thunk (operands[3]); | |
9759 | return ""; | |
9760 | } | |
9761 | [(set_attr "op_type" "RX") | |
9762 | (set_attr "type" "cs") | |
9763 | (set_attr "length" "8")]) | |
9764 | ||
f314b9b1 UW |
9765 | (define_expand "casesi" |
9766 | [(match_operand:SI 0 "general_operand" "") | |
9767 | (match_operand:SI 1 "general_operand" "") | |
9768 | (match_operand:SI 2 "general_operand" "") | |
9769 | (label_ref (match_operand 3 "" "")) | |
9770 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 9771 | "" |
f314b9b1 UW |
9772 | { |
9773 | rtx index = gen_reg_rtx (SImode); | |
9774 | rtx base = gen_reg_rtx (Pmode); | |
9775 | rtx target = gen_reg_rtx (Pmode); | |
9776 | ||
9777 | emit_move_insn (index, operands[0]); | |
9778 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
9779 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 9780 | operands[4]); |
f314b9b1 UW |
9781 | |
9782 | if (Pmode != SImode) | |
9783 | index = convert_to_mode (Pmode, index, 1); | |
9784 | if (GET_CODE (index) != REG) | |
9785 | index = copy_to_mode_reg (Pmode, index); | |
9786 | ||
9787 | if (TARGET_64BIT) | |
9788 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
9789 | else | |
a556fd39 | 9790 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 9791 | |
f314b9b1 UW |
9792 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
9793 | ||
542a8afa | 9794 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
9795 | emit_move_insn (target, index); |
9796 | ||
9797 | if (flag_pic) | |
9798 | target = gen_rtx_PLUS (Pmode, base, target); | |
9799 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
9800 | ||
9801 | DONE; | |
10bbf137 | 9802 | }) |
9db1d521 HP |
9803 | |
9804 | ||
9805 | ;; | |
9806 | ;;- Jump to subroutine. | |
9807 | ;; | |
9808 | ;; | |
9809 | ||
9810 | ; | |
9811 | ; untyped call instruction pattern(s). | |
9812 | ; | |
9813 | ||
9814 | ;; Call subroutine returning any type. | |
9815 | (define_expand "untyped_call" | |
9816 | [(parallel [(call (match_operand 0 "" "") | |
9817 | (const_int 0)) | |
9818 | (match_operand 1 "" "") | |
9819 | (match_operand 2 "" "")])] | |
9820 | "" | |
9db1d521 HP |
9821 | { |
9822 | int i; | |
9823 | ||
9824 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
9825 | ||
9826 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
9827 | { | |
9828 | rtx set = XVECEXP (operands[2], 0, i); | |
9829 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
9830 | } | |
9831 | ||
9832 | /* The optimizer does not know that the call sets the function value | |
9833 | registers we stored in the result block. We avoid problems by | |
9834 | claiming that all hard registers are used and clobbered at this | |
9835 | point. */ | |
9836 | emit_insn (gen_blockage ()); | |
9837 | ||
9838 | DONE; | |
10bbf137 | 9839 | }) |
9db1d521 HP |
9840 | |
9841 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
9842 | ;; all of memory. This blocks insns from being moved across this point. | |
9843 | ||
9844 | (define_insn "blockage" | |
10bbf137 | 9845 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 9846 | "" |
4023fb28 | 9847 | "" |
d5869ca0 UW |
9848 | [(set_attr "type" "none") |
9849 | (set_attr "length" "0")]) | |
4023fb28 | 9850 | |
9db1d521 | 9851 | ; |
ed9676cf | 9852 | ; sibcall patterns |
9db1d521 HP |
9853 | ; |
9854 | ||
ed9676cf | 9855 | (define_expand "sibcall" |
44b8152b | 9856 | [(call (match_operand 0 "" "") |
ed9676cf | 9857 | (match_operand 1 "" ""))] |
9db1d521 | 9858 | "" |
9db1d521 | 9859 | { |
ed9676cf AK |
9860 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
9861 | DONE; | |
9862 | }) | |
9db1d521 | 9863 | |
ed9676cf | 9864 | (define_insn "*sibcall_br" |
ae156f85 | 9865 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9866 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 9867 | "SIBLING_CALL_P (insn) |
ed9676cf | 9868 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
84b4c7b5 AK |
9869 | { |
9870 | if (TARGET_INDIRECT_BRANCH_NOBP_CALL) | |
9871 | { | |
9872 | gcc_assert (TARGET_CPU_Z10); | |
9873 | s390_indirect_branch_via_thunk (SIBCALL_REGNUM, | |
9874 | INVALID_REGNUM, | |
9875 | NULL_RTX, | |
9876 | s390_indirect_branch_type_call); | |
9877 | return ""; | |
9878 | } | |
9879 | else | |
9880 | return "br\t%%r1"; | |
9881 | } | |
9882 | [(set (attr "op_type") | |
9883 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
9884 | (const_string "RIL") | |
9885 | (const_string "RR"))) | |
9886 | (set (attr "mnemonic") | |
9887 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
9888 | (const_string "jg") | |
9889 | (const_string "br"))) | |
ed9676cf AK |
9890 | (set_attr "type" "branch") |
9891 | (set_attr "atype" "agen")]) | |
9db1d521 | 9892 | |
ed9676cf AK |
9893 | (define_insn "*sibcall_brc" |
9894 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9895 | (match_operand 1 "const_int_operand" "n"))] | |
9896 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9897 | "j\t%0" | |
9898 | [(set_attr "op_type" "RI") | |
9899 | (set_attr "type" "branch")]) | |
9db1d521 | 9900 | |
ed9676cf AK |
9901 | (define_insn "*sibcall_brcl" |
9902 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9903 | (match_operand 1 "const_int_operand" "n"))] | |
8cc6307c | 9904 | "SIBLING_CALL_P (insn)" |
ed9676cf AK |
9905 | "jg\t%0" |
9906 | [(set_attr "op_type" "RIL") | |
9907 | (set_attr "type" "branch")]) | |
44b8152b | 9908 | |
ed9676cf AK |
9909 | ; |
9910 | ; sibcall_value patterns | |
9911 | ; | |
9e8327e3 | 9912 | |
ed9676cf AK |
9913 | (define_expand "sibcall_value" |
9914 | [(set (match_operand 0 "" "") | |
9915 | (call (match_operand 1 "" "") | |
9916 | (match_operand 2 "" "")))] | |
9917 | "" | |
9918 | { | |
9919 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 9920 | DONE; |
10bbf137 | 9921 | }) |
9db1d521 | 9922 | |
ed9676cf AK |
9923 | (define_insn "*sibcall_value_br" |
9924 | [(set (match_operand 0 "" "") | |
ae156f85 | 9925 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9926 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 9927 | "SIBLING_CALL_P (insn) |
ed9676cf | 9928 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
84b4c7b5 AK |
9929 | { |
9930 | if (TARGET_INDIRECT_BRANCH_NOBP_CALL) | |
9931 | { | |
9932 | gcc_assert (TARGET_CPU_Z10); | |
9933 | s390_indirect_branch_via_thunk (SIBCALL_REGNUM, | |
9934 | INVALID_REGNUM, | |
9935 | NULL_RTX, | |
9936 | s390_indirect_branch_type_call); | |
9937 | return ""; | |
9938 | } | |
9939 | else | |
9940 | return "br\t%%r1"; | |
9941 | } | |
9942 | [(set (attr "op_type") | |
9943 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
9944 | (const_string "RIL") | |
9945 | (const_string "RR"))) | |
9946 | (set (attr "mnemonic") | |
9947 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_CALL") | |
9948 | (const_string "jg") | |
9949 | (const_string "br"))) | |
ed9676cf AK |
9950 | (set_attr "type" "branch") |
9951 | (set_attr "atype" "agen")]) | |
9952 | ||
9953 | (define_insn "*sibcall_value_brc" | |
9954 | [(set (match_operand 0 "" "") | |
9955 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9956 | (match_operand 2 "const_int_operand" "n")))] | |
9957 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9958 | "j\t%1" | |
9959 | [(set_attr "op_type" "RI") | |
9960 | (set_attr "type" "branch")]) | |
9961 | ||
9962 | (define_insn "*sibcall_value_brcl" | |
9963 | [(set (match_operand 0 "" "") | |
9964 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9965 | (match_operand 2 "const_int_operand" "n")))] | |
8cc6307c | 9966 | "SIBLING_CALL_P (insn)" |
ed9676cf AK |
9967 | "jg\t%1" |
9968 | [(set_attr "op_type" "RIL") | |
9969 | (set_attr "type" "branch")]) | |
9970 | ||
9971 | ||
9972 | ; | |
9973 | ; call instruction pattern(s). | |
9974 | ; | |
9975 | ||
9976 | (define_expand "call" | |
9977 | [(call (match_operand 0 "" "") | |
9978 | (match_operand 1 "" "")) | |
9979 | (use (match_operand 2 "" ""))] | |
44b8152b | 9980 | "" |
ed9676cf | 9981 | { |
2f7e5a0d | 9982 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
9983 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
9984 | DONE; | |
9985 | }) | |
44b8152b | 9986 | |
9e8327e3 UW |
9987 | (define_insn "*bras" |
9988 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9989 | (match_operand 1 "const_int_operand" "n")) | |
9990 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
9991 | "!SIBLING_CALL_P (insn) |
9992 | && TARGET_SMALL_EXEC | |
ed9676cf | 9993 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 9994 | "bras\t%2,%0" |
9db1d521 | 9995 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9996 | (set_attr "type" "jsr") |
9997 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9998 | |
9e8327e3 UW |
9999 | (define_insn "*brasl" |
10000 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
10001 | (match_operand 1 "const_int_operand" "n")) | |
10002 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d | 10003 | "!SIBLING_CALL_P (insn) |
8cc6307c | 10004 | |
ed9676cf | 10005 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
10006 | "brasl\t%2,%0" |
10007 | [(set_attr "op_type" "RIL") | |
65b1d8ea | 10008 | (set_attr "type" "jsr") |
14cfceb7 IL |
10009 | (set_attr "z196prop" "z196_cracked") |
10010 | (set_attr "relative_long" "yes")]) | |
9db1d521 | 10011 | |
9e8327e3 | 10012 | (define_insn "*basr" |
3e4be43f | 10013 | [(call (mem:QI (match_operand 0 "address_operand" "ZR")) |
9e8327e3 UW |
10014 | (match_operand 1 "const_int_operand" "n")) |
10015 | (clobber (match_operand 2 "register_operand" "=r"))] | |
84b4c7b5 AK |
10016 | "!TARGET_INDIRECT_BRANCH_NOBP_CALL |
10017 | && !SIBLING_CALL_P (insn) | |
10018 | && GET_MODE (operands[2]) == Pmode" | |
9e8327e3 UW |
10019 | { |
10020 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10021 | return "basr\t%2,%0"; | |
10022 | else | |
10023 | return "bas\t%2,%a0"; | |
10024 | } | |
10025 | [(set (attr "op_type") | |
10026 | (if_then_else (match_operand 0 "register_operand" "") | |
10027 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
10028 | (set (attr "mnemonic") |
10029 | (if_then_else (match_operand 0 "register_operand" "") | |
10030 | (const_string "basr") (const_string "bas"))) | |
10031 | (set_attr "type" "jsr") | |
10032 | (set_attr "atype" "agen") | |
10033 | (set_attr "z196prop" "z196_cracked")]) | |
10034 | ||
10035 | (define_insn "*basr_via_thunk<mode>_z10" | |
10036 | [(call (mem:QI (match_operand:P 0 "register_operand" "a")) | |
10037 | (match_operand 1 "const_int_operand" "n")) | |
10038 | (clobber (match_operand:P 2 "register_operand" "=&r"))] | |
10039 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10040 | && TARGET_CPU_Z10 | |
10041 | && !SIBLING_CALL_P (insn)" | |
10042 | { | |
10043 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10044 | REGNO (operands[2]), | |
10045 | NULL_RTX, | |
10046 | s390_indirect_branch_type_call); | |
10047 | return ""; | |
10048 | } | |
10049 | [(set_attr "op_type" "RIL") | |
10050 | (set_attr "mnemonic" "brasl") | |
10051 | (set_attr "type" "jsr") | |
10052 | (set_attr "atype" "agen") | |
10053 | (set_attr "z196prop" "z196_cracked")]) | |
10054 | ||
10055 | (define_insn "*basr_via_thunk<mode>" | |
10056 | [(call (mem:QI (match_operand:P 0 "register_operand" "a")) | |
10057 | (match_operand 1 "const_int_operand" "n")) | |
10058 | (clobber (match_operand:P 2 "register_operand" "=&r")) | |
10059 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
10060 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10061 | && !TARGET_CPU_Z10 | |
10062 | && !SIBLING_CALL_P (insn)" | |
10063 | { | |
10064 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10065 | REGNO (operands[2]), | |
10066 | NULL_RTX, | |
10067 | s390_indirect_branch_type_call); | |
10068 | return ""; | |
10069 | } | |
10070 | [(set_attr "op_type" "RIL") | |
10071 | (set_attr "mnemonic" "brasl") | |
9e8327e3 | 10072 | (set_attr "type" "jsr") |
65b1d8ea AK |
10073 | (set_attr "atype" "agen") |
10074 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 HP |
10075 | |
10076 | ; | |
10077 | ; call_value instruction pattern(s). | |
10078 | ; | |
10079 | ||
10080 | (define_expand "call_value" | |
44b8152b UW |
10081 | [(set (match_operand 0 "" "") |
10082 | (call (match_operand 1 "" "") | |
10083 | (match_operand 2 "" ""))) | |
10084 | (use (match_operand 3 "" ""))] | |
9db1d521 | 10085 | "" |
9db1d521 | 10086 | { |
2f7e5a0d | 10087 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 10088 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 10089 | DONE; |
10bbf137 | 10090 | }) |
9db1d521 | 10091 | |
9e8327e3 | 10092 | (define_insn "*bras_r" |
c19ec8f9 | 10093 | [(set (match_operand 0 "" "") |
9e8327e3 | 10094 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 10095 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 10096 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
10097 | "!SIBLING_CALL_P (insn) |
10098 | && TARGET_SMALL_EXEC | |
ed9676cf | 10099 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 10100 | "bras\t%3,%1" |
9db1d521 | 10101 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
10102 | (set_attr "type" "jsr") |
10103 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10104 | |
9e8327e3 | 10105 | (define_insn "*brasl_r" |
c19ec8f9 | 10106 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10107 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10108 | (match_operand 2 "const_int_operand" "n"))) | |
10109 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d | 10110 | "!SIBLING_CALL_P (insn) |
8cc6307c | 10111 | |
ed9676cf | 10112 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10113 | "brasl\t%3,%1" |
10114 | [(set_attr "op_type" "RIL") | |
65b1d8ea | 10115 | (set_attr "type" "jsr") |
14cfceb7 IL |
10116 | (set_attr "z196prop" "z196_cracked") |
10117 | (set_attr "relative_long" "yes")]) | |
9db1d521 | 10118 | |
9e8327e3 | 10119 | (define_insn "*basr_r" |
c19ec8f9 | 10120 | [(set (match_operand 0 "" "") |
3e4be43f | 10121 | (call (mem:QI (match_operand 1 "address_operand" "ZR")) |
9e8327e3 UW |
10122 | (match_operand 2 "const_int_operand" "n"))) |
10123 | (clobber (match_operand 3 "register_operand" "=r"))] | |
84b4c7b5 AK |
10124 | "!TARGET_INDIRECT_BRANCH_NOBP_CALL |
10125 | && !SIBLING_CALL_P (insn) | |
10126 | && GET_MODE (operands[3]) == Pmode" | |
9e8327e3 UW |
10127 | { |
10128 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10129 | return "basr\t%3,%1"; | |
10130 | else | |
10131 | return "bas\t%3,%a1"; | |
10132 | } | |
10133 | [(set (attr "op_type") | |
10134 | (if_then_else (match_operand 1 "register_operand" "") | |
10135 | (const_string "RR") (const_string "RX"))) | |
84b4c7b5 AK |
10136 | (set (attr "mnemonic") |
10137 | (if_then_else (match_operand 1 "register_operand" "") | |
10138 | (const_string "basr") (const_string "bas"))) | |
10139 | (set_attr "type" "jsr") | |
10140 | (set_attr "atype" "agen") | |
10141 | (set_attr "z196prop" "z196_cracked")]) | |
10142 | ||
10143 | (define_insn "*basr_r_via_thunk_z10" | |
10144 | [(set (match_operand 0 "" "") | |
10145 | (call (mem:QI (match_operand 1 "register_operand" "a")) | |
10146 | (match_operand 2 "const_int_operand" "n"))) | |
10147 | (clobber (match_operand 3 "register_operand" "=&r"))] | |
10148 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10149 | && TARGET_CPU_Z10 | |
10150 | && !SIBLING_CALL_P (insn) | |
10151 | && GET_MODE (operands[3]) == Pmode" | |
10152 | { | |
10153 | s390_indirect_branch_via_thunk (REGNO (operands[1]), | |
10154 | REGNO (operands[3]), | |
10155 | NULL_RTX, | |
10156 | s390_indirect_branch_type_call); | |
10157 | return ""; | |
10158 | } | |
10159 | [(set_attr "op_type" "RIL") | |
10160 | (set_attr "mnemonic" "brasl") | |
10161 | (set_attr "type" "jsr") | |
10162 | (set_attr "atype" "agen") | |
10163 | (set_attr "z196prop" "z196_cracked")]) | |
10164 | ||
10165 | (define_insn "*basr_r_via_thunk" | |
10166 | [(set (match_operand 0 "" "") | |
10167 | (call (mem:QI (match_operand 1 "register_operand" "a")) | |
10168 | (match_operand 2 "const_int_operand" "n"))) | |
10169 | (clobber (match_operand 3 "register_operand" "=&r")) | |
10170 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
10171 | "TARGET_INDIRECT_BRANCH_NOBP_CALL | |
10172 | && !TARGET_CPU_Z10 | |
10173 | && !SIBLING_CALL_P (insn) | |
10174 | && GET_MODE (operands[3]) == Pmode" | |
10175 | { | |
10176 | s390_indirect_branch_via_thunk (REGNO (operands[1]), | |
10177 | REGNO (operands[3]), | |
10178 | NULL_RTX, | |
10179 | s390_indirect_branch_type_call); | |
10180 | return ""; | |
10181 | } | |
10182 | [(set_attr "op_type" "RIL") | |
10183 | (set_attr "mnemonic" "brasl") | |
9e8327e3 | 10184 | (set_attr "type" "jsr") |
65b1d8ea AK |
10185 | (set_attr "atype" "agen") |
10186 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 10187 | |
fd3cd001 UW |
10188 | ;; |
10189 | ;;- Thread-local storage support. | |
10190 | ;; | |
10191 | ||
f959607b CLT |
10192 | (define_expand "get_thread_pointer<mode>" |
10193 | [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))] | |
10194 | "" | |
c5aa1d12 | 10195 | "") |
fd3cd001 | 10196 | |
f959607b CLT |
10197 | (define_expand "set_thread_pointer<mode>" |
10198 | [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) | |
10199 | (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] | |
10200 | "" | |
c5aa1d12 UW |
10201 | "") |
10202 | ||
10203 | (define_insn "*set_tp" | |
ae156f85 | 10204 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
10205 | "" |
10206 | "" | |
10207 | [(set_attr "type" "none") | |
10208 | (set_attr "length" "0")]) | |
c7453384 | 10209 | |
fd3cd001 UW |
10210 | (define_insn "*tls_load_64" |
10211 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 10212 | (unspec:DI [(match_operand:DI 1 "memory_operand" "T") |
fd3cd001 UW |
10213 | (match_operand:DI 2 "" "")] |
10214 | UNSPEC_TLS_LOAD))] | |
10215 | "TARGET_64BIT" | |
d40c829f | 10216 | "lg\t%0,%1%J2" |
9381e3f1 WG |
10217 | [(set_attr "op_type" "RXE") |
10218 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
10219 | |
10220 | (define_insn "*tls_load_31" | |
d3632d41 UW |
10221 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
10222 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
10223 | (match_operand:SI 2 "" "")] |
10224 | UNSPEC_TLS_LOAD))] | |
10225 | "!TARGET_64BIT" | |
d3632d41 | 10226 | "@ |
d40c829f UW |
10227 | l\t%0,%1%J2 |
10228 | ly\t%0,%1%J2" | |
9381e3f1 | 10229 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 10230 | (set_attr "type" "load") |
3e4be43f | 10231 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 10232 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 10233 | |
9e8327e3 | 10234 | (define_insn "*bras_tls" |
c19ec8f9 | 10235 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10236 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10237 | (match_operand 2 "const_int_operand" "n"))) | |
10238 | (clobber (match_operand 3 "register_operand" "=r")) | |
10239 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
10240 | "!SIBLING_CALL_P (insn) |
10241 | && TARGET_SMALL_EXEC | |
ed9676cf | 10242 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 10243 | "bras\t%3,%1%J4" |
fd3cd001 | 10244 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
10245 | (set_attr "type" "jsr") |
10246 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 10247 | |
9e8327e3 | 10248 | (define_insn "*brasl_tls" |
c19ec8f9 | 10249 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
10250 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
10251 | (match_operand 2 "const_int_operand" "n"))) | |
10252 | (clobber (match_operand 3 "register_operand" "=r")) | |
10253 | (use (match_operand 4 "" ""))] | |
2f7e5a0d | 10254 | "!SIBLING_CALL_P (insn) |
8cc6307c | 10255 | |
ed9676cf | 10256 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10257 | "brasl\t%3,%1%J4" |
10258 | [(set_attr "op_type" "RIL") | |
65b1d8ea | 10259 | (set_attr "type" "jsr") |
14cfceb7 IL |
10260 | (set_attr "z196prop" "z196_cracked") |
10261 | (set_attr "relative_long" "yes")]) | |
fd3cd001 | 10262 | |
9e8327e3 | 10263 | (define_insn "*basr_tls" |
c19ec8f9 | 10264 | [(set (match_operand 0 "" "") |
3e4be43f | 10265 | (call (mem:QI (match_operand 1 "address_operand" "ZR")) |
9e8327e3 UW |
10266 | (match_operand 2 "const_int_operand" "n"))) |
10267 | (clobber (match_operand 3 "register_operand" "=r")) | |
10268 | (use (match_operand 4 "" ""))] | |
ed9676cf | 10269 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
10270 | { |
10271 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
10272 | return "basr\t%3,%1%J4"; | |
10273 | else | |
10274 | return "bas\t%3,%a1%J4"; | |
10275 | } | |
10276 | [(set (attr "op_type") | |
10277 | (if_then_else (match_operand 1 "register_operand" "") | |
10278 | (const_string "RR") (const_string "RX"))) | |
10279 | (set_attr "type" "jsr") | |
65b1d8ea AK |
10280 | (set_attr "atype" "agen") |
10281 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 10282 | |
e0374221 AS |
10283 | ;; |
10284 | ;;- Atomic operations | |
10285 | ;; | |
10286 | ||
10287 | ; | |
78ce265b | 10288 | ; memory barrier patterns. |
e0374221 AS |
10289 | ; |
10290 | ||
78ce265b RH |
10291 | (define_expand "mem_thread_fence" |
10292 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
10293 | "" | |
10294 | { | |
10295 | /* Unless this is a SEQ_CST fence, the s390 memory model is strong | |
10296 | enough not to require barriers of any kind. */ | |
46b35980 | 10297 | if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0])))) |
78ce265b RH |
10298 | { |
10299 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
10300 | MEM_VOLATILE_P (mem) = 1; | |
10301 | emit_insn (gen_mem_thread_fence_1 (mem)); | |
10302 | } | |
10303 | DONE; | |
e0374221 AS |
10304 | }) |
10305 | ||
78ce265b RH |
10306 | ; Although bcr is superscalar on Z10, this variant will never |
10307 | ; become part of an execution group. | |
a9cc3f58 AK |
10308 | ; With z196 we can make use of the fast-BCR-serialization facility. |
10309 | ; This allows for a slightly faster sync which is sufficient for our | |
10310 | ; purposes. | |
78ce265b | 10311 | (define_insn "mem_thread_fence_1" |
e0374221 | 10312 | [(set (match_operand:BLK 0 "" "") |
1a8c13b3 | 10313 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 | 10314 | "" |
a9cc3f58 AK |
10315 | { |
10316 | if (TARGET_Z196) | |
10317 | return "bcr\t14,0"; | |
10318 | else | |
10319 | return "bcr\t15,0"; | |
10320 | } | |
10321 | [(set_attr "op_type" "RR") | |
10322 | (set_attr "mnemonic" "bcr_flush") | |
10323 | (set_attr "z196prop" "z196_alone")]) | |
1a8c13b3 | 10324 | |
78ce265b RH |
10325 | ; |
10326 | ; atomic load/store operations | |
10327 | ; | |
10328 | ||
10329 | ; Atomic loads need not examine the memory model at all. | |
10330 | (define_expand "atomic_load<mode>" | |
10331 | [(match_operand:DINT 0 "register_operand") ;; output | |
10332 | (match_operand:DINT 1 "memory_operand") ;; memory | |
10333 | (match_operand:SI 2 "const_int_operand")] ;; model | |
10334 | "" | |
10335 | { | |
75cc21e2 AK |
10336 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
10337 | FAIL; | |
10338 | ||
78ce265b RH |
10339 | if (<MODE>mode == TImode) |
10340 | emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); | |
10341 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
10342 | emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); | |
10343 | else | |
10344 | emit_move_insn (operands[0], operands[1]); | |
10345 | DONE; | |
10346 | }) | |
10347 | ||
10348 | ; Different from movdi_31 in that we want no splitters. | |
10349 | (define_insn "atomic_loaddi_1" | |
10350 | [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") | |
10351 | (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] | |
10352 | UNSPEC_MOVA))] | |
10353 | "!TARGET_ZARCH" | |
10354 | "@ | |
10355 | lm\t%0,%M0,%S1 | |
10356 | lmy\t%0,%M0,%S1 | |
10357 | ld\t%0,%1 | |
10358 | ldy\t%0,%1" | |
10359 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
3e4be43f | 10360 | (set_attr "cpu_facility" "*,longdisp,*,longdisp") |
78ce265b RH |
10361 | (set_attr "type" "lm,lm,floaddf,floaddf")]) |
10362 | ||
10363 | (define_insn "atomic_loadti_1" | |
10364 | [(set (match_operand:TI 0 "register_operand" "=r") | |
3e4be43f | 10365 | (unspec:TI [(match_operand:TI 1 "memory_operand" "T")] |
78ce265b RH |
10366 | UNSPEC_MOVA))] |
10367 | "TARGET_ZARCH" | |
10368 | "lpq\t%0,%1" | |
10369 | [(set_attr "op_type" "RXY") | |
10370 | (set_attr "type" "other")]) | |
10371 | ||
10372 | ; Atomic stores must(?) enforce sequential consistency. | |
10373 | (define_expand "atomic_store<mode>" | |
10374 | [(match_operand:DINT 0 "memory_operand") ;; memory | |
10375 | (match_operand:DINT 1 "register_operand") ;; input | |
10376 | (match_operand:SI 2 "const_int_operand")] ;; model | |
10377 | "" | |
10378 | { | |
46b35980 | 10379 | enum memmodel model = memmodel_from_int (INTVAL (operands[2])); |
78ce265b | 10380 | |
75cc21e2 AK |
10381 | if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0]))) |
10382 | FAIL; | |
10383 | ||
78ce265b RH |
10384 | if (<MODE>mode == TImode) |
10385 | emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); | |
10386 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
10387 | emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); | |
10388 | else | |
10389 | emit_move_insn (operands[0], operands[1]); | |
46b35980 | 10390 | if (is_mm_seq_cst (model)) |
78ce265b RH |
10391 | emit_insn (gen_mem_thread_fence (operands[2])); |
10392 | DONE; | |
10393 | }) | |
10394 | ||
10395 | ; Different from movdi_31 in that we want no splitters. | |
10396 | (define_insn "atomic_storedi_1" | |
10397 | [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") | |
10398 | (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] | |
10399 | UNSPEC_MOVA))] | |
10400 | "!TARGET_ZARCH" | |
10401 | "@ | |
10402 | stm\t%1,%N1,%S0 | |
10403 | stmy\t%1,%N1,%S0 | |
10404 | std %1,%0 | |
10405 | stdy %1,%0" | |
10406 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
3e4be43f | 10407 | (set_attr "cpu_facility" "*,longdisp,*,longdisp") |
78ce265b RH |
10408 | (set_attr "type" "stm,stm,fstoredf,fstoredf")]) |
10409 | ||
10410 | (define_insn "atomic_storeti_1" | |
3e4be43f | 10411 | [(set (match_operand:TI 0 "memory_operand" "=T") |
78ce265b RH |
10412 | (unspec:TI [(match_operand:TI 1 "register_operand" "r")] |
10413 | UNSPEC_MOVA))] | |
10414 | "TARGET_ZARCH" | |
10415 | "stpq\t%1,%0" | |
10416 | [(set_attr "op_type" "RXY") | |
10417 | (set_attr "type" "other")]) | |
e0374221 AS |
10418 | |
10419 | ; | |
10420 | ; compare and swap patterns. | |
10421 | ; | |
10422 | ||
78ce265b RH |
10423 | (define_expand "atomic_compare_and_swap<mode>" |
10424 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
03db9ab5 DV |
10425 | (match_operand:DINT 1 "nonimmediate_operand");; oldval output |
10426 | (match_operand:DINT 2 "s_operand") ;; memory | |
10427 | (match_operand:DINT 3 "general_operand") ;; expected intput | |
10428 | (match_operand:DINT 4 "general_operand") ;; newval intput | |
78ce265b RH |
10429 | (match_operand:SI 5 "const_int_operand") ;; is_weak |
10430 | (match_operand:SI 6 "const_int_operand") ;; success model | |
10431 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
10432 | "" | |
10433 | { | |
03db9ab5 DV |
10434 | if (GET_MODE_BITSIZE (<MODE>mode) >= 16 |
10435 | && GET_MODE_BITSIZE (<MODE>mode) > MEM_ALIGN (operands[2])) | |
75cc21e2 AK |
10436 | FAIL; |
10437 | ||
03db9ab5 DV |
10438 | s390_expand_cs (<MODE>mode, operands[0], operands[1], operands[2], |
10439 | operands[3], operands[4], INTVAL (operands[5])); | |
10440 | DONE;}) | |
3093f076 | 10441 | |
78ce265b RH |
10442 | (define_expand "atomic_compare_and_swap<mode>_internal" |
10443 | [(parallel | |
10444 | [(set (match_operand:DGPR 0 "register_operand") | |
03db9ab5 | 10445 | (match_operand:DGPR 1 "s_operand")) |
78ce265b RH |
10446 | (set (match_dup 1) |
10447 | (unspec_volatile:DGPR | |
10448 | [(match_dup 1) | |
10449 | (match_operand:DGPR 2 "register_operand") | |
10450 | (match_operand:DGPR 3 "register_operand")] | |
10451 | UNSPECV_CAS)) | |
03db9ab5 DV |
10452 | (set (match_operand 4 "cc_reg_operand") |
10453 | (match_dup 5))])] | |
10454 | "GET_MODE (operands[4]) == CCZmode | |
10455 | || GET_MODE (operands[4]) == CCZ1mode" | |
10456 | { | |
10457 | operands[5] | |
10458 | = gen_rtx_COMPARE (GET_MODE (operands[4]), operands[1], operands[2]); | |
10459 | }) | |
78ce265b RH |
10460 | |
10461 | ; cdsg, csg | |
10462 | (define_insn "*atomic_compare_and_swap<mode>_1" | |
10463 | [(set (match_operand:TDI 0 "register_operand" "=r") | |
bdb57bcb | 10464 | (match_operand:TDI 1 "nonsym_memory_operand" "+S")) |
8006eaa6 | 10465 | (set (match_dup 1) |
78ce265b | 10466 | (unspec_volatile:TDI |
8006eaa6 | 10467 | [(match_dup 1) |
78ce265b RH |
10468 | (match_operand:TDI 2 "register_operand" "0") |
10469 | (match_operand:TDI 3 "register_operand" "r")] | |
8006eaa6 | 10470 | UNSPECV_CAS)) |
03db9ab5 DV |
10471 | (set (reg CC_REGNUM) |
10472 | (compare (match_dup 1) (match_dup 2)))] | |
10473 | "TARGET_ZARCH | |
10474 | && s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10475 | "c<td>sg\t%0,%3,%S1" |
10476 | [(set_attr "op_type" "RSY") | |
8006eaa6 AS |
10477 | (set_attr "type" "sem")]) |
10478 | ||
78ce265b RH |
10479 | ; cds, cdsy |
10480 | (define_insn "*atomic_compare_and_swapdi_2" | |
10481 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
bdb57bcb | 10482 | (match_operand:DI 1 "nonsym_memory_operand" "+Q,S")) |
e0374221 | 10483 | (set (match_dup 1) |
78ce265b RH |
10484 | (unspec_volatile:DI |
10485 | [(match_dup 1) | |
10486 | (match_operand:DI 2 "register_operand" "0,0") | |
10487 | (match_operand:DI 3 "register_operand" "r,r")] | |
10488 | UNSPECV_CAS)) | |
03db9ab5 DV |
10489 | (set (reg CC_REGNUM) |
10490 | (compare (match_dup 1) (match_dup 2)))] | |
10491 | "!TARGET_ZARCH | |
10492 | && s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10493 | "@ |
10494 | cds\t%0,%3,%S1 | |
10495 | cdsy\t%0,%3,%S1" | |
10496 | [(set_attr "op_type" "RS,RSY") | |
3e4be43f | 10497 | (set_attr "cpu_facility" "*,longdisp") |
78ce265b RH |
10498 | (set_attr "type" "sem")]) |
10499 | ||
10500 | ; cs, csy | |
10501 | (define_insn "*atomic_compare_and_swapsi_3" | |
10502 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
bdb57bcb | 10503 | (match_operand:SI 1 "nonsym_memory_operand" "+Q,S")) |
78ce265b RH |
10504 | (set (match_dup 1) |
10505 | (unspec_volatile:SI | |
e0374221 | 10506 | [(match_dup 1) |
78ce265b RH |
10507 | (match_operand:SI 2 "register_operand" "0,0") |
10508 | (match_operand:SI 3 "register_operand" "r,r")] | |
e0374221 | 10509 | UNSPECV_CAS)) |
03db9ab5 DV |
10510 | (set (reg CC_REGNUM) |
10511 | (compare (match_dup 1) (match_dup 2)))] | |
10512 | "s390_match_ccmode (insn, CCZ1mode)" | |
78ce265b RH |
10513 | "@ |
10514 | cs\t%0,%3,%S1 | |
10515 | csy\t%0,%3,%S1" | |
10516 | [(set_attr "op_type" "RS,RSY") | |
3e4be43f | 10517 | (set_attr "cpu_facility" "*,longdisp") |
e0374221 AS |
10518 | (set_attr "type" "sem")]) |
10519 | ||
45d18331 AS |
10520 | ; |
10521 | ; Other atomic instruction patterns. | |
10522 | ; | |
10523 | ||
65b1d8ea AK |
10524 | ; z196 load and add, xor, or and and instructions |
10525 | ||
78ce265b RH |
10526 | (define_expand "atomic_fetch_<atomic><mode>" |
10527 | [(match_operand:GPR 0 "register_operand") ;; val out | |
10528 | (ATOMIC_Z196:GPR | |
10529 | (match_operand:GPR 1 "memory_operand") ;; memory | |
10530 | (match_operand:GPR 2 "register_operand")) ;; val in | |
10531 | (match_operand:SI 3 "const_int_operand")] ;; model | |
65b1d8ea | 10532 | "TARGET_Z196" |
78ce265b | 10533 | { |
75cc21e2 AK |
10534 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
10535 | FAIL; | |
10536 | ||
78ce265b RH |
10537 | emit_insn (gen_atomic_fetch_<atomic><mode>_iaf |
10538 | (operands[0], operands[1], operands[2])); | |
10539 | DONE; | |
10540 | }) | |
65b1d8ea AK |
10541 | |
10542 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
78ce265b RH |
10543 | (define_insn "atomic_fetch_<atomic><mode>_iaf" |
10544 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 10545 | (match_operand:GPR 1 "memory_operand" "+S")) |
78ce265b RH |
10546 | (set (match_dup 1) |
10547 | (unspec_volatile:GPR | |
10548 | [(ATOMIC_Z196:GPR (match_dup 1) | |
10549 | (match_operand:GPR 2 "general_operand" "d"))] | |
10550 | UNSPECV_ATOMIC_OP)) | |
10551 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 10552 | "TARGET_Z196" |
78ce265b RH |
10553 | "la<noxa><g>\t%0,%2,%1" |
10554 | [(set_attr "op_type" "RSY") | |
10555 | (set_attr "type" "sem")]) | |
65b1d8ea | 10556 | |
78ce265b RH |
10557 | ;; For SImode and larger, the optabs.c code will do just fine in |
10558 | ;; expanding a compare-and-swap loop. For QI/HImode, we can do | |
10559 | ;; better by expanding our own loop. | |
65b1d8ea | 10560 | |
78ce265b RH |
10561 | (define_expand "atomic_<atomic><mode>" |
10562 | [(ATOMIC:HQI | |
10563 | (match_operand:HQI 0 "memory_operand") ;; memory | |
10564 | (match_operand:HQI 1 "general_operand")) ;; val in | |
10565 | (match_operand:SI 2 "const_int_operand")] ;; model | |
45d18331 | 10566 | "" |
78ce265b RH |
10567 | { |
10568 | s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], | |
10569 | operands[1], false); | |
10570 | DONE; | |
10571 | }) | |
45d18331 | 10572 | |
78ce265b RH |
10573 | (define_expand "atomic_fetch_<atomic><mode>" |
10574 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10575 | (ATOMIC:HQI | |
10576 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10577 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10578 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 10579 | "" |
78ce265b RH |
10580 | { |
10581 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10582 | operands[2], false); | |
10583 | DONE; | |
10584 | }) | |
10585 | ||
10586 | (define_expand "atomic_<atomic>_fetch<mode>" | |
10587 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10588 | (ATOMIC:HQI | |
10589 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10590 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10591 | (match_operand:SI 3 "const_int_operand")] ;; model | |
10592 | "" | |
10593 | { | |
10594 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10595 | operands[2], true); | |
10596 | DONE; | |
10597 | }) | |
10598 | ||
03db9ab5 DV |
10599 | ;; Pattern to implement atomic_exchange with a compare-and-swap loop. The code |
10600 | ;; generated by the middleend is not good. | |
78ce265b | 10601 | (define_expand "atomic_exchange<mode>" |
03db9ab5 DV |
10602 | [(match_operand:DINT 0 "register_operand") ;; val out |
10603 | (match_operand:DINT 1 "s_operand") ;; memory | |
10604 | (match_operand:DINT 2 "general_operand") ;; val in | |
78ce265b | 10605 | (match_operand:SI 3 "const_int_operand")] ;; model |
45d18331 | 10606 | "" |
78ce265b | 10607 | { |
03db9ab5 DV |
10608 | if (<MODE>mode != QImode |
10609 | && MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (<MODE>mode)) | |
10610 | FAIL; | |
10611 | if (<MODE>mode == HImode || <MODE>mode == QImode) | |
10612 | s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], operands[2], | |
10613 | false); | |
10614 | else if (<MODE>mode == SImode || TARGET_ZARCH) | |
10615 | s390_expand_atomic_exchange_tdsi (operands[0], operands[1], operands[2]); | |
10616 | else | |
10617 | FAIL; | |
78ce265b RH |
10618 | DONE; |
10619 | }) | |
45d18331 | 10620 | |
9db1d521 HP |
10621 | ;; |
10622 | ;;- Miscellaneous instructions. | |
10623 | ;; | |
10624 | ||
10625 | ; | |
10626 | ; allocate stack instruction pattern(s). | |
10627 | ; | |
10628 | ||
10629 | (define_expand "allocate_stack" | |
ef44a6ff UW |
10630 | [(match_operand 0 "general_operand" "") |
10631 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 10632 | "TARGET_BACKCHAIN" |
9db1d521 | 10633 | { |
ef44a6ff | 10634 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 10635 | |
ef44a6ff UW |
10636 | emit_move_insn (temp, s390_back_chain_rtx ()); |
10637 | anti_adjust_stack (operands[1]); | |
10638 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 10639 | |
ef44a6ff UW |
10640 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
10641 | DONE; | |
10bbf137 | 10642 | }) |
9db1d521 HP |
10643 | |
10644 | ||
10645 | ; | |
43ab026f | 10646 | ; setjmp instruction pattern. |
9db1d521 HP |
10647 | ; |
10648 | ||
9db1d521 | 10649 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 10650 | [(match_operand 0 "" "")] |
f314b9b1 | 10651 | "flag_pic" |
9db1d521 | 10652 | { |
585539a1 | 10653 | emit_insn (s390_load_got ()); |
c41c1387 | 10654 | emit_use (pic_offset_table_rtx); |
9db1d521 | 10655 | DONE; |
fd7643fb | 10656 | }) |
9db1d521 | 10657 | |
9db1d521 HP |
10658 | ;; These patterns say how to save and restore the stack pointer. We need not |
10659 | ;; save the stack pointer at function level since we are careful to | |
10660 | ;; preserve the backchain. At block level, we have to restore the backchain | |
10661 | ;; when we restore the stack pointer. | |
10662 | ;; | |
10663 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
10664 | ;; backchain and restore both. Note that in the nonlocal case, the | |
10665 | ;; save area is a memory location. | |
10666 | ||
10667 | (define_expand "save_stack_function" | |
10668 | [(match_operand 0 "general_operand" "") | |
10669 | (match_operand 1 "general_operand" "")] | |
10670 | "" | |
10671 | "DONE;") | |
10672 | ||
10673 | (define_expand "restore_stack_function" | |
10674 | [(match_operand 0 "general_operand" "") | |
10675 | (match_operand 1 "general_operand" "")] | |
10676 | "" | |
10677 | "DONE;") | |
10678 | ||
10679 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
10680 | [(match_operand 0 "register_operand" "") |
10681 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 10682 | "TARGET_BACKCHAIN" |
9db1d521 | 10683 | { |
ef44a6ff UW |
10684 | rtx temp = gen_reg_rtx (Pmode); |
10685 | ||
10686 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
10687 | emit_move_insn (operands[0], operands[1]); | |
10688 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10689 | ||
10690 | DONE; | |
10bbf137 | 10691 | }) |
9db1d521 HP |
10692 | |
10693 | (define_expand "save_stack_nonlocal" | |
10694 | [(match_operand 0 "memory_operand" "") | |
10695 | (match_operand 1 "register_operand" "")] | |
10696 | "" | |
9db1d521 | 10697 | { |
ef44a6ff UW |
10698 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
10699 | ||
10700 | /* Copy the backchain to the first word, sp to the second and the | |
10701 | literal pool base to the third. */ | |
10702 | ||
9602b6a1 AK |
10703 | rtx save_bc = adjust_address (operands[0], Pmode, 0); |
10704 | rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); | |
10705 | rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10706 | ||
b3d31392 | 10707 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10708 | emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); |
ef44a6ff | 10709 | |
9602b6a1 AK |
10710 | emit_move_insn (save_sp, operands[1]); |
10711 | emit_move_insn (save_bp, base); | |
9db1d521 | 10712 | |
9db1d521 | 10713 | DONE; |
10bbf137 | 10714 | }) |
9db1d521 HP |
10715 | |
10716 | (define_expand "restore_stack_nonlocal" | |
10717 | [(match_operand 0 "register_operand" "") | |
10718 | (match_operand 1 "memory_operand" "")] | |
10719 | "" | |
9db1d521 | 10720 | { |
490ceeb4 | 10721 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 10722 | rtx temp = NULL_RTX; |
9db1d521 | 10723 | |
43ab026f | 10724 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 10725 | literal pool base from the third. */ |
43ab026f | 10726 | |
9602b6a1 AK |
10727 | rtx save_bc = adjust_address (operands[1], Pmode, 0); |
10728 | rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); | |
10729 | rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10730 | ||
b3d31392 | 10731 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10732 | temp = force_reg (Pmode, save_bc); |
9381e3f1 | 10733 | |
9602b6a1 AK |
10734 | emit_move_insn (base, save_bp); |
10735 | emit_move_insn (operands[0], save_sp); | |
ef44a6ff UW |
10736 | |
10737 | if (temp) | |
10738 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10739 | ||
c41c1387 | 10740 | emit_use (base); |
9db1d521 | 10741 | DONE; |
10bbf137 | 10742 | }) |
9db1d521 | 10743 | |
7bcebb25 AK |
10744 | (define_expand "exception_receiver" |
10745 | [(const_int 0)] | |
10746 | "" | |
10747 | { | |
10748 | s390_set_has_landing_pad_p (true); | |
10749 | DONE; | |
10750 | }) | |
9db1d521 HP |
10751 | |
10752 | ; | |
10753 | ; nop instruction pattern(s). | |
10754 | ; | |
10755 | ||
10756 | (define_insn "nop" | |
10757 | [(const_int 0)] | |
10758 | "" | |
aad98a61 AK |
10759 | "nopr\t%%r0" |
10760 | [(set_attr "op_type" "RR")]) | |
10761 | ||
10762 | ; non-branch NOPs required for optimizing compare-and-branch patterns | |
10763 | ; on z10 | |
10764 | ||
10765 | (define_insn "nop_lr0" | |
10766 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_0)] | |
10767 | "" | |
d40c829f | 10768 | "lr\t0,0" |
729e750f WG |
10769 | [(set_attr "op_type" "RR") |
10770 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 10771 | |
aad98a61 AK |
10772 | (define_insn "nop_lr1" |
10773 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_LR_1)] | |
d277db6b WG |
10774 | "" |
10775 | "lr\t1,1" | |
10776 | [(set_attr "op_type" "RR")]) | |
10777 | ||
f8af0e30 DV |
10778 | ;;- Undeletable nops (used for hotpatching) |
10779 | ||
10780 | (define_insn "nop_2_byte" | |
10781 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)] | |
10782 | "" | |
4bbc8970 | 10783 | "nopr\t%%r0" |
f8af0e30 DV |
10784 | [(set_attr "op_type" "RR")]) |
10785 | ||
10786 | (define_insn "nop_4_byte" | |
10787 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)] | |
10788 | "" | |
10789 | "nop\t0" | |
10790 | [(set_attr "op_type" "RX")]) | |
10791 | ||
10792 | (define_insn "nop_6_byte" | |
10793 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)] | |
8cc6307c | 10794 | "" |
f8af0e30 | 10795 | "brcl\t0, 0" |
14cfceb7 IL |
10796 | [(set_attr "op_type" "RIL") |
10797 | (set_attr "relative_long" "yes")]) | |
f8af0e30 | 10798 | |
9db1d521 HP |
10799 | |
10800 | ; | |
10801 | ; Special literal pool access instruction pattern(s). | |
10802 | ; | |
10803 | ||
416cf582 UW |
10804 | (define_insn "*pool_entry" |
10805 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
10806 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 10807 | "" |
9db1d521 | 10808 | { |
ef4bddc2 | 10809 | machine_mode mode = GET_MODE (PATTERN (insn)); |
416cf582 | 10810 | unsigned int align = GET_MODE_BITSIZE (mode); |
faeb9bb6 | 10811 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
10812 | return ""; |
10813 | } | |
b628bd8e | 10814 | [(set (attr "length") |
416cf582 | 10815 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 10816 | |
9bb86f41 UW |
10817 | (define_insn "pool_align" |
10818 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
10819 | UNSPECV_POOL_ALIGN)] | |
10820 | "" | |
10821 | ".align\t%0" | |
b628bd8e | 10822 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 10823 | |
9bb86f41 UW |
10824 | (define_insn "pool_section_start" |
10825 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
10826 | "" | |
b929b470 MK |
10827 | { |
10828 | switch_to_section (targetm.asm_out.function_rodata_section | |
10829 | (current_function_decl)); | |
10830 | return ""; | |
10831 | } | |
b628bd8e | 10832 | [(set_attr "length" "0")]) |
b2ccb744 | 10833 | |
9bb86f41 UW |
10834 | (define_insn "pool_section_end" |
10835 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
10836 | "" | |
b929b470 MK |
10837 | { |
10838 | switch_to_section (current_function_section ()); | |
10839 | return ""; | |
10840 | } | |
b628bd8e | 10841 | [(set_attr "length" "0")]) |
b2ccb744 | 10842 | |
5af2f3d3 | 10843 | (define_insn "main_base_64" |
9e8327e3 UW |
10844 | [(set (match_operand 0 "register_operand" "=a") |
10845 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
8cc6307c | 10846 | "GET_MODE (operands[0]) == Pmode" |
5af2f3d3 UW |
10847 | "larl\t%0,%1" |
10848 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 10849 | (set_attr "type" "larl") |
14cfceb7 IL |
10850 | (set_attr "z10prop" "z10_fwd_A1") |
10851 | (set_attr "relative_long" "yes")]) | |
5af2f3d3 UW |
10852 | |
10853 | (define_insn "main_pool" | |
585539a1 UW |
10854 | [(set (match_operand 0 "register_operand" "=a") |
10855 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
10856 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
10857 | { |
10858 | gcc_unreachable (); | |
10859 | } | |
9381e3f1 | 10860 | [(set (attr "type") |
8cc6307c | 10861 | (const_string "larl"))]) |
b2ccb744 | 10862 | |
aee4e0db | 10863 | (define_insn "reload_base_64" |
9e8327e3 UW |
10864 | [(set (match_operand 0 "register_operand" "=a") |
10865 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
8cc6307c | 10866 | "GET_MODE (operands[0]) == Pmode" |
d40c829f | 10867 | "larl\t%0,%1" |
aee4e0db | 10868 | [(set_attr "op_type" "RIL") |
9381e3f1 | 10869 | (set_attr "type" "larl") |
729e750f | 10870 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 10871 | |
aee4e0db | 10872 | (define_insn "pool" |
fd7643fb | 10873 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 10874 | "" |
8d933e31 AS |
10875 | { |
10876 | gcc_unreachable (); | |
10877 | } | |
b628bd8e | 10878 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 10879 | |
4023fb28 UW |
10880 | ;; |
10881 | ;; Insns related to generating the function prologue and epilogue. | |
10882 | ;; | |
10883 | ||
10884 | ||
10885 | (define_expand "prologue" | |
10886 | [(use (const_int 0))] | |
10887 | "" | |
10bbf137 | 10888 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
10889 | |
10890 | (define_expand "epilogue" | |
10891 | [(use (const_int 1))] | |
10892 | "" | |
ed9676cf AK |
10893 | "s390_emit_epilogue (false); DONE;") |
10894 | ||
10895 | (define_expand "sibcall_epilogue" | |
10896 | [(use (const_int 0))] | |
10897 | "" | |
10898 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 10899 | |
177bc204 RS |
10900 | ;; A direct return instruction, without using an epilogue. |
10901 | (define_insn "<code>" | |
10902 | [(ANY_RETURN)] | |
10903 | "s390_can_use_<code>_insn ()" | |
84b4c7b5 AK |
10904 | { |
10905 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
10906 | { | |
10907 | /* The target is always r14 so there is no clobber | |
10908 | of r1 needed for pre z10 targets. */ | |
10909 | s390_indirect_branch_via_thunk (RETURN_REGNUM, | |
10910 | INVALID_REGNUM, | |
10911 | NULL_RTX, | |
10912 | s390_indirect_branch_type_return); | |
10913 | return ""; | |
10914 | } | |
10915 | else | |
10916 | return "br\t%%r14"; | |
10917 | } | |
10918 | [(set (attr "op_type") | |
10919 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
10920 | (const_string "RIL") | |
10921 | (const_string "RR"))) | |
10922 | (set (attr "mnemonic") | |
10923 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
10924 | (const_string "jg") | |
10925 | (const_string "br"))) | |
177bc204 RS |
10926 | (set_attr "type" "jsr") |
10927 | (set_attr "atype" "agen")]) | |
10928 | ||
84b4c7b5 AK |
10929 | |
10930 | (define_expand "return_use" | |
10931 | [(parallel | |
10932 | [(return) | |
10933 | (use (match_operand 0 "register_operand" "a"))])] | |
10934 | "" | |
10935 | { | |
10936 | if (!TARGET_CPU_Z10 | |
10937 | && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION) | |
10938 | { | |
10939 | if (TARGET_64BIT) | |
10940 | emit_jump_insn (gen_returndi_prez10 (operands[0])); | |
10941 | else | |
10942 | emit_jump_insn (gen_returnsi_prez10 (operands[0])); | |
10943 | DONE; | |
10944 | } | |
10945 | }) | |
10946 | ||
10947 | (define_insn "*return<mode>" | |
4023fb28 | 10948 | [(return) |
84b4c7b5 AK |
10949 | (use (match_operand:P 0 "register_operand" "a"))] |
10950 | "TARGET_CPU_Z10 || !TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION" | |
10951 | { | |
10952 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
10953 | { | |
10954 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10955 | INVALID_REGNUM, | |
10956 | NULL_RTX, | |
10957 | s390_indirect_branch_type_return); | |
10958 | return ""; | |
10959 | } | |
10960 | else | |
10961 | return "br\t%0"; | |
10962 | } | |
10963 | [(set (attr "op_type") | |
10964 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
10965 | (const_string "RIL") | |
10966 | (const_string "RR"))) | |
10967 | (set (attr "mnemonic") | |
10968 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
10969 | (const_string "jg") | |
10970 | (const_string "br"))) | |
10971 | (set_attr "type" "jsr") | |
10972 | (set_attr "atype" "agen")]) | |
10973 | ||
10974 | (define_insn "return<mode>_prez10" | |
10975 | [(return) | |
10976 | (use (match_operand:P 0 "register_operand" "a")) | |
10977 | (clobber (reg:P INDIRECT_BRANCH_THUNK_REGNUM))] | |
10978 | "!TARGET_CPU_Z10 && TARGET_INDIRECT_BRANCH_NOBP_RET_OPTION" | |
10979 | { | |
10980 | if (TARGET_INDIRECT_BRANCH_NOBP_RET) | |
10981 | { | |
10982 | s390_indirect_branch_via_thunk (REGNO (operands[0]), | |
10983 | INVALID_REGNUM, | |
10984 | NULL_RTX, | |
10985 | s390_indirect_branch_type_return); | |
10986 | return ""; | |
10987 | } | |
10988 | else | |
10989 | return "br\t%0"; | |
10990 | } | |
10991 | [(set (attr "op_type") | |
10992 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
10993 | (const_string "RIL") | |
10994 | (const_string "RR"))) | |
10995 | (set (attr "mnemonic") | |
10996 | (if_then_else (match_test "TARGET_INDIRECT_BRANCH_NOBP_RET") | |
10997 | (const_string "jg") | |
10998 | (const_string "br"))) | |
c7453384 | 10999 | (set_attr "type" "jsr") |
077dab3b | 11000 | (set_attr "atype" "agen")]) |
4023fb28 | 11001 | |
4023fb28 | 11002 | |
c7453384 | 11003 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 11004 | ;; pointer. This is used for compatibility. |
c7453384 EC |
11005 | |
11006 | (define_expand "ptr_extend" | |
11007 | [(set (match_operand:DI 0 "register_operand" "=r") | |
11008 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 11009 | "TARGET_64BIT" |
c7453384 | 11010 | { |
c7453384 EC |
11011 | emit_insn (gen_anddi3 (operands[0], |
11012 | gen_lowpart (DImode, operands[1]), | |
11013 | GEN_INT (0x7fffffff))); | |
c7453384 | 11014 | DONE; |
10bbf137 | 11015 | }) |
4798630c D |
11016 | |
11017 | ;; Instruction definition to expand eh_return macro to support | |
11018 | ;; swapping in special linkage return addresses. | |
11019 | ||
11020 | (define_expand "eh_return" | |
11021 | [(use (match_operand 0 "register_operand" ""))] | |
11022 | "TARGET_TPF" | |
11023 | { | |
11024 | s390_emit_tpf_eh_return (operands[0]); | |
11025 | DONE; | |
11026 | }) | |
11027 | ||
7b8acc34 AK |
11028 | ; |
11029 | ; Stack Protector Patterns | |
11030 | ; | |
11031 | ||
11032 | (define_expand "stack_protect_set" | |
11033 | [(set (match_operand 0 "memory_operand" "") | |
11034 | (match_operand 1 "memory_operand" ""))] | |
11035 | "" | |
11036 | { | |
11037 | #ifdef TARGET_THREAD_SSP_OFFSET | |
11038 | operands[1] | |
11039 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
11040 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
11041 | #endif | |
11042 | if (TARGET_64BIT) | |
11043 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
11044 | else | |
11045 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
11046 | ||
11047 | DONE; | |
11048 | }) | |
11049 | ||
11050 | (define_insn "stack_protect_set<mode>" | |
11051 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
11052 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
11053 | "" | |
11054 | "mvc\t%O0(%G0,%R0),%S1" | |
11055 | [(set_attr "op_type" "SS")]) | |
11056 | ||
11057 | (define_expand "stack_protect_test" | |
11058 | [(set (reg:CC CC_REGNUM) | |
11059 | (compare (match_operand 0 "memory_operand" "") | |
11060 | (match_operand 1 "memory_operand" ""))) | |
11061 | (match_operand 2 "" "")] | |
11062 | "" | |
11063 | { | |
f90b7a5a | 11064 | rtx cc_reg, test; |
7b8acc34 AK |
11065 | #ifdef TARGET_THREAD_SSP_OFFSET |
11066 | operands[1] | |
11067 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
11068 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
11069 | #endif | |
7b8acc34 AK |
11070 | if (TARGET_64BIT) |
11071 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
11072 | else | |
11073 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
11074 | ||
f90b7a5a PB |
11075 | cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); |
11076 | test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); | |
11077 | emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); | |
7b8acc34 AK |
11078 | DONE; |
11079 | }) | |
11080 | ||
11081 | (define_insn "stack_protect_test<mode>" | |
11082 | [(set (reg:CCZ CC_REGNUM) | |
11083 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
11084 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
11085 | "" | |
11086 | "clc\t%O0(%G0,%R0),%S1" | |
11087 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
11088 | |
11089 | ; This is used in s390_emit_prologue in order to prevent insns | |
11090 | ; adjusting the stack pointer to be moved over insns writing stack | |
11091 | ; slots using a copy of the stack pointer in a different register. | |
11092 | (define_insn "stack_tie" | |
11093 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
11094 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
11095 | "" | |
11096 | "" | |
11097 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
11098 | |
11099 | ||
82c6f58a AK |
11100 | (define_insn "stack_restore_from_fpr" |
11101 | [(set (reg:DI STACK_REGNUM) | |
11102 | (match_operand:DI 0 "register_operand" "f")) | |
11103 | (clobber (mem:BLK (scratch)))] | |
11104 | "TARGET_Z10" | |
11105 | "lgdr\t%%r15,%0" | |
11106 | [(set_attr "op_type" "RRE")]) | |
11107 | ||
963fc8d0 AK |
11108 | ; |
11109 | ; Data prefetch patterns | |
11110 | ; | |
11111 | ||
11112 | (define_insn "prefetch" | |
3e4be43f UW |
11113 | [(prefetch (match_operand 0 "address_operand" "ZT,X") |
11114 | (match_operand:SI 1 "const_int_operand" " n,n") | |
11115 | (match_operand:SI 2 "const_int_operand" " n,n"))] | |
22d72dbc | 11116 | "TARGET_Z10" |
963fc8d0 | 11117 | { |
4fe6dea8 AK |
11118 | switch (which_alternative) |
11119 | { | |
11120 | case 0: | |
4fe6dea8 | 11121 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; |
22d72dbc | 11122 | case 1: |
4fe6dea8 AK |
11123 | if (larl_operand (operands[0], Pmode)) |
11124 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
a65593a4 | 11125 | /* fallthrough */ |
4fe6dea8 AK |
11126 | default: |
11127 | ||
11128 | /* This might be reached for symbolic operands with an odd | |
11129 | addend. We simply omit the prefetch for such rare cases. */ | |
11130 | ||
11131 | return ""; | |
11132 | } | |
9381e3f1 | 11133 | } |
22d72dbc AK |
11134 | [(set_attr "type" "load,larl") |
11135 | (set_attr "op_type" "RXY,RIL") | |
65b1d8ea | 11136 | (set_attr "z10prop" "z10_super") |
14cfceb7 IL |
11137 | (set_attr "z196prop" "z196_alone") |
11138 | (set_attr "relative_long" "yes")]) | |
07da44ab AK |
11139 | |
11140 | ||
11141 | ; | |
11142 | ; Byte swap instructions | |
11143 | ; | |
11144 | ||
511f5bb1 AK |
11145 | ; FIXME: There is also mvcin but we cannot use it since src and target |
11146 | ; may overlap. | |
50dc4eed | 11147 | ; lrvr, lrv, strv, lrvgr, lrvg, strvg |
07da44ab | 11148 | (define_insn "bswap<mode>2" |
3e4be43f UW |
11149 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T") |
11150 | (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))] | |
8cc6307c | 11151 | "" |
07da44ab AK |
11152 | "@ |
11153 | lrv<g>r\t%0,%1 | |
6f5a59d1 AK |
11154 | lrv<g>\t%0,%1 |
11155 | strv<g>\t%1,%0" | |
11156 | [(set_attr "type" "*,load,store") | |
11157 | (set_attr "op_type" "RRE,RXY,RXY") | |
07da44ab | 11158 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 11159 | |
511f5bb1 | 11160 | (define_insn "bswaphi2" |
3e4be43f UW |
11161 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T") |
11162 | (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))] | |
8cc6307c | 11163 | "" |
6f5a59d1 AK |
11164 | "@ |
11165 | # | |
11166 | lrvh\t%0,%1 | |
11167 | strvh\t%1,%0" | |
11168 | [(set_attr "type" "*,load,store") | |
11169 | (set_attr "op_type" "RRE,RXY,RXY") | |
511f5bb1 | 11170 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 11171 | |
6f5a59d1 AK |
11172 | (define_split |
11173 | [(set (match_operand:HI 0 "register_operand" "") | |
11174 | (bswap:HI (match_operand:HI 1 "register_operand" "")))] | |
8cc6307c | 11175 | "" |
6f5a59d1 | 11176 | [(set (match_dup 2) (bswap:SI (match_dup 3))) |
9060e335 | 11177 | (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))] |
6f5a59d1 | 11178 | { |
9060e335 | 11179 | operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0); |
6f5a59d1 AK |
11180 | operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0); |
11181 | }) | |
11182 | ||
11183 | ||
65b1d8ea AK |
11184 | ; |
11185 | ; Population count instruction | |
11186 | ; | |
11187 | ||
11188 | ; The S/390 popcount instruction counts the bits of op1 in 8 byte | |
11189 | ; portions and stores the result in the corresponding bytes in op0. | |
11190 | (define_insn "*popcount<mode>" | |
11191 | [(set (match_operand:INT 0 "register_operand" "=d") | |
11192 | (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) | |
11193 | (clobber (reg:CC CC_REGNUM))] | |
11194 | "TARGET_Z196" | |
11195 | "popcnt\t%0,%1" | |
11196 | [(set_attr "op_type" "RRE")]) | |
11197 | ||
11198 | (define_expand "popcountdi2" | |
11199 | [; popcnt op0, op1 | |
11200 | (parallel [(set (match_operand:DI 0 "register_operand" "") | |
11201 | (unspec:DI [(match_operand:DI 1 "register_operand")] | |
11202 | UNSPEC_POPCNT)) | |
11203 | (clobber (reg:CC CC_REGNUM))]) | |
11204 | ; sllg op2, op0, 32 | |
11205 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) | |
11206 | ; agr op0, op2 | |
11207 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11208 | (clobber (reg:CC CC_REGNUM))]) | |
11209 | ; sllg op2, op0, 16 | |
17465c6e | 11210 | (set (match_dup 2) |
65b1d8ea AK |
11211 | (ashift:DI (match_dup 0) (const_int 16))) |
11212 | ; agr op0, op2 | |
11213 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11214 | (clobber (reg:CC CC_REGNUM))]) | |
11215 | ; sllg op2, op0, 8 | |
11216 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) | |
11217 | ; agr op0, op2 | |
11218 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
11219 | (clobber (reg:CC CC_REGNUM))]) | |
11220 | ; srlg op0, op0, 56 | |
11221 | (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] | |
11222 | "TARGET_Z196 && TARGET_64BIT" | |
11223 | "operands[2] = gen_reg_rtx (DImode);") | |
11224 | ||
11225 | (define_expand "popcountsi2" | |
11226 | [; popcnt op0, op1 | |
11227 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
11228 | (unspec:SI [(match_operand:SI 1 "register_operand")] | |
11229 | UNSPEC_POPCNT)) | |
11230 | (clobber (reg:CC CC_REGNUM))]) | |
11231 | ; sllk op2, op0, 16 | |
17465c6e | 11232 | (set (match_dup 2) |
65b1d8ea AK |
11233 | (ashift:SI (match_dup 0) (const_int 16))) |
11234 | ; ar op0, op2 | |
11235 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11236 | (clobber (reg:CC CC_REGNUM))]) | |
11237 | ; sllk op2, op0, 8 | |
11238 | (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) | |
11239 | ; ar op0, op2 | |
11240 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11241 | (clobber (reg:CC CC_REGNUM))]) | |
11242 | ; srl op0, op0, 24 | |
11243 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | |
11244 | "TARGET_Z196" | |
11245 | "operands[2] = gen_reg_rtx (SImode);") | |
11246 | ||
11247 | (define_expand "popcounthi2" | |
11248 | [; popcnt op0, op1 | |
11249 | (parallel [(set (match_operand:HI 0 "register_operand" "") | |
11250 | (unspec:HI [(match_operand:HI 1 "register_operand")] | |
11251 | UNSPEC_POPCNT)) | |
11252 | (clobber (reg:CC CC_REGNUM))]) | |
11253 | ; sllk op2, op0, 8 | |
17465c6e | 11254 | (set (match_dup 2) |
65b1d8ea AK |
11255 | (ashift:SI (match_dup 0) (const_int 8))) |
11256 | ; ar op0, op2 | |
11257 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
11258 | (clobber (reg:CC CC_REGNUM))]) | |
11259 | ; srl op0, op0, 8 | |
11260 | (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] | |
11261 | "TARGET_Z196" | |
11262 | "operands[2] = gen_reg_rtx (SImode);") | |
11263 | ||
11264 | (define_expand "popcountqi2" | |
11265 | [; popcnt op0, op1 | |
11266 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
11267 | (unspec:QI [(match_operand:QI 1 "register_operand")] | |
11268 | UNSPEC_POPCNT)) | |
11269 | (clobber (reg:CC CC_REGNUM))])] | |
11270 | "TARGET_Z196" | |
11271 | "") | |
11272 | ||
11273 | ;; | |
11274 | ;;- Copy sign instructions | |
11275 | ;; | |
11276 | ||
11277 | (define_insn "copysign<mode>3" | |
11278 | [(set (match_operand:FP 0 "register_operand" "=f") | |
11279 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
11280 | (match_operand:FP 2 "register_operand" "f")] | |
11281 | UNSPEC_COPYSIGN))] | |
11282 | "TARGET_Z196" | |
11283 | "cpsdr\t%0,%2,%1" | |
11284 | [(set_attr "op_type" "RRF") | |
11285 | (set_attr "type" "fsimp<mode>")]) | |
5a3fe9b6 AK |
11286 | |
11287 | ||
11288 | ;; | |
11289 | ;;- Transactional execution instructions | |
11290 | ;; | |
11291 | ||
11292 | ; This splitter helps combine to make use of CC directly when | |
11293 | ; comparing the integer result of a tbegin builtin with a constant. | |
11294 | ; The unspec is already removed by canonicalize_comparison. So this | |
11295 | ; splitters only job is to turn the PARALLEL into separate insns | |
11296 | ; again. Unfortunately this only works with the very first cc/int | |
11297 | ; compare since combine is not able to deal with data flow across | |
11298 | ; basic block boundaries. | |
11299 | ||
11300 | ; It needs to be an insn pattern as well since combine does not apply | |
11301 | ; the splitter directly. Combine would only use it if it actually | |
11302 | ; would reduce the number of instructions. | |
11303 | (define_insn_and_split "*ccraw_to_int" | |
11304 | [(set (pc) | |
11305 | (if_then_else | |
11306 | (match_operator 0 "s390_eqne_operator" | |
11307 | [(reg:CCRAW CC_REGNUM) | |
11308 | (match_operand 1 "const_int_operand" "")]) | |
11309 | (label_ref (match_operand 2 "" "")) | |
11310 | (pc))) | |
11311 | (set (match_operand:SI 3 "register_operand" "=d") | |
11312 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] | |
11313 | "" | |
11314 | "#" | |
11315 | "" | |
11316 | [(set (match_dup 3) | |
11317 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) | |
11318 | (set (pc) | |
11319 | (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)]) | |
11320 | (label_ref (match_dup 2)) | |
11321 | (pc)))] | |
11322 | "") | |
11323 | ||
11324 | ; Non-constrained transaction begin | |
11325 | ||
11326 | (define_expand "tbegin" | |
ee163e72 AK |
11327 | [(match_operand:SI 0 "register_operand" "") |
11328 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
11329 | "TARGET_HTM" |
11330 | { | |
11331 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true); | |
11332 | DONE; | |
11333 | }) | |
11334 | ||
11335 | (define_expand "tbegin_nofloat" | |
ee163e72 AK |
11336 | [(match_operand:SI 0 "register_operand" "") |
11337 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
11338 | "TARGET_HTM" |
11339 | { | |
11340 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false); | |
11341 | DONE; | |
11342 | }) | |
11343 | ||
11344 | (define_expand "tbegin_retry" | |
ee163e72 AK |
11345 | [(match_operand:SI 0 "register_operand" "") |
11346 | (match_operand:BLK 1 "memory_operand" "") | |
11347 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
11348 | "TARGET_HTM" |
11349 | { | |
11350 | s390_expand_tbegin (operands[0], operands[1], operands[2], true); | |
11351 | DONE; | |
11352 | }) | |
11353 | ||
11354 | (define_expand "tbegin_retry_nofloat" | |
ee163e72 AK |
11355 | [(match_operand:SI 0 "register_operand" "") |
11356 | (match_operand:BLK 1 "memory_operand" "") | |
11357 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
11358 | "TARGET_HTM" |
11359 | { | |
11360 | s390_expand_tbegin (operands[0], operands[1], operands[2], false); | |
11361 | DONE; | |
11362 | }) | |
11363 | ||
c914ac45 AK |
11364 | ; Clobber VRs since they don't get restored |
11365 | (define_insn "tbegin_1_z13" | |
11366 | [(set (reg:CCRAW CC_REGNUM) | |
11367 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] | |
11368 | UNSPECV_TBEGIN)) | |
11369 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
11370 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
11371 | (clobber (reg:TI 16)) (clobber (reg:TI 38)) | |
11372 | (clobber (reg:TI 17)) (clobber (reg:TI 39)) | |
11373 | (clobber (reg:TI 18)) (clobber (reg:TI 40)) | |
11374 | (clobber (reg:TI 19)) (clobber (reg:TI 41)) | |
11375 | (clobber (reg:TI 20)) (clobber (reg:TI 42)) | |
11376 | (clobber (reg:TI 21)) (clobber (reg:TI 43)) | |
11377 | (clobber (reg:TI 22)) (clobber (reg:TI 44)) | |
11378 | (clobber (reg:TI 23)) (clobber (reg:TI 45)) | |
11379 | (clobber (reg:TI 24)) (clobber (reg:TI 46)) | |
11380 | (clobber (reg:TI 25)) (clobber (reg:TI 47)) | |
11381 | (clobber (reg:TI 26)) (clobber (reg:TI 48)) | |
11382 | (clobber (reg:TI 27)) (clobber (reg:TI 49)) | |
11383 | (clobber (reg:TI 28)) (clobber (reg:TI 50)) | |
11384 | (clobber (reg:TI 29)) (clobber (reg:TI 51)) | |
11385 | (clobber (reg:TI 30)) (clobber (reg:TI 52)) | |
11386 | (clobber (reg:TI 31)) (clobber (reg:TI 53))] | |
11387 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
11388 | ; not supposed to be used for immediates (see genpreds.c). | |
11389 | "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11390 | "tbegin\t%1,%x0" | |
11391 | [(set_attr "op_type" "SIL")]) | |
11392 | ||
5a3fe9b6 AK |
11393 | (define_insn "tbegin_1" |
11394 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d | 11395 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
5a3fe9b6 | 11396 | UNSPECV_TBEGIN)) |
2561451d AK |
11397 | (set (match_operand:BLK 1 "memory_operand" "=Q") |
11398 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
5a3fe9b6 AK |
11399 | (clobber (reg:DF 16)) |
11400 | (clobber (reg:DF 17)) | |
11401 | (clobber (reg:DF 18)) | |
11402 | (clobber (reg:DF 19)) | |
11403 | (clobber (reg:DF 20)) | |
11404 | (clobber (reg:DF 21)) | |
11405 | (clobber (reg:DF 22)) | |
11406 | (clobber (reg:DF 23)) | |
11407 | (clobber (reg:DF 24)) | |
11408 | (clobber (reg:DF 25)) | |
11409 | (clobber (reg:DF 26)) | |
11410 | (clobber (reg:DF 27)) | |
11411 | (clobber (reg:DF 28)) | |
11412 | (clobber (reg:DF 29)) | |
11413 | (clobber (reg:DF 30)) | |
11414 | (clobber (reg:DF 31))] | |
11415 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
11416 | ; not supposed to be used for immediates (see genpreds.c). | |
2561451d AK |
11417 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" |
11418 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
11419 | [(set_attr "op_type" "SIL")]) |
11420 | ||
11421 | ; Same as above but without the FPR clobbers | |
11422 | (define_insn "tbegin_nofloat_1" | |
11423 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d AK |
11424 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
11425 | UNSPECV_TBEGIN)) | |
11426 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
11427 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))] | |
11428 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11429 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
11430 | [(set_attr "op_type" "SIL")]) |
11431 | ||
11432 | ||
11433 | ; Constrained transaction begin | |
11434 | ||
11435 | (define_expand "tbeginc" | |
11436 | [(set (reg:CCRAW CC_REGNUM) | |
11437 | (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)] | |
11438 | UNSPECV_TBEGINC))] | |
11439 | "TARGET_HTM" | |
11440 | "") | |
11441 | ||
11442 | (define_insn "*tbeginc_1" | |
11443 | [(set (reg:CCRAW CC_REGNUM) | |
11444 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")] | |
11445 | UNSPECV_TBEGINC))] | |
11446 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11447 | "tbeginc\t0,%x0" | |
11448 | [(set_attr "op_type" "SIL")]) | |
11449 | ||
11450 | ; Transaction end | |
11451 | ||
11452 | (define_expand "tend" | |
11453 | [(set (reg:CCRAW CC_REGNUM) | |
11454 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND)) | |
ee163e72 | 11455 | (set (match_operand:SI 0 "register_operand" "") |
5a3fe9b6 AK |
11456 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] |
11457 | "TARGET_HTM" | |
11458 | "") | |
11459 | ||
11460 | (define_insn "*tend_1" | |
11461 | [(set (reg:CCRAW CC_REGNUM) | |
11462 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))] | |
11463 | "TARGET_HTM" | |
11464 | "tend" | |
11465 | [(set_attr "op_type" "S")]) | |
11466 | ||
11467 | ; Transaction abort | |
11468 | ||
11469 | (define_expand "tabort" | |
eae48192 | 11470 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")] |
5a3fe9b6 AK |
11471 | UNSPECV_TABORT)] |
11472 | "TARGET_HTM && operands != NULL" | |
11473 | { | |
11474 | if (CONST_INT_P (operands[0]) | |
11475 | && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255) | |
11476 | { | |
f3981e7e | 11477 | error ("invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC |
5a3fe9b6 AK |
11478 | ". Values in range 0 through 255 are reserved.", |
11479 | INTVAL (operands[0])); | |
11480 | FAIL; | |
11481 | } | |
11482 | }) | |
11483 | ||
11484 | (define_insn "*tabort_1" | |
eae48192 | 11485 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")] |
5a3fe9b6 AK |
11486 | UNSPECV_TABORT)] |
11487 | "TARGET_HTM && operands != NULL" | |
11488 | "tabort\t%Y0" | |
11489 | [(set_attr "op_type" "S")]) | |
11490 | ||
eae48192 AK |
11491 | (define_insn "*tabort_1_plus" |
11492 | [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand" "a") | |
11493 | (match_operand:SI 1 "const_int_operand" "J"))] | |
11494 | UNSPECV_TABORT)] | |
11495 | "TARGET_HTM && operands != NULL | |
11496 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")" | |
11497 | "tabort\t%1(%0)" | |
11498 | [(set_attr "op_type" "S")]) | |
11499 | ||
5a3fe9b6 AK |
11500 | ; Transaction extract nesting depth |
11501 | ||
11502 | (define_insn "etnd" | |
11503 | [(set (match_operand:SI 0 "register_operand" "=d") | |
11504 | (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))] | |
11505 | "TARGET_HTM" | |
11506 | "etnd\t%0" | |
11507 | [(set_attr "op_type" "RRE")]) | |
11508 | ||
11509 | ; Non-transactional store | |
11510 | ||
11511 | (define_insn "ntstg" | |
3e4be43f | 11512 | [(set (match_operand:DI 0 "memory_operand" "=T") |
5a3fe9b6 AK |
11513 | (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] |
11514 | UNSPECV_NTSTG))] | |
11515 | "TARGET_HTM" | |
11516 | "ntstg\t%1,%0" | |
11517 | [(set_attr "op_type" "RXY")]) | |
11518 | ||
11519 | ; Transaction perform processor assist | |
11520 | ||
11521 | (define_expand "tx_assist" | |
2561451d AK |
11522 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "") |
11523 | (reg:SI GPR0_REGNUM) | |
291a9e98 | 11524 | (const_int PPA_TX_ABORT)] |
5a3fe9b6 AK |
11525 | UNSPECV_PPA)] |
11526 | "TARGET_HTM" | |
2561451d | 11527 | "") |
5a3fe9b6 AK |
11528 | |
11529 | (define_insn "*ppa" | |
11530 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") | |
11531 | (match_operand:SI 1 "register_operand" "d") | |
11532 | (match_operand 2 "const_int_operand" "I")] | |
11533 | UNSPECV_PPA)] | |
291a9e98 | 11534 | "(TARGET_ZEC12 || TARGET_HTM) && INTVAL (operands[2]) < 16" |
2561451d | 11535 | "ppa\t%0,%1,%2" |
5a3fe9b6 | 11536 | [(set_attr "op_type" "RRF")]) |
004f64e1 AK |
11537 | |
11538 | ||
11539 | ; Set and get floating point control register | |
11540 | ||
3af82a61 | 11541 | (define_insn "sfpc" |
004f64e1 AK |
11542 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] |
11543 | UNSPECV_SFPC)] | |
11544 | "TARGET_HARD_FLOAT" | |
11545 | "sfpc\t%0") | |
11546 | ||
3af82a61 | 11547 | (define_insn "efpc" |
004f64e1 AK |
11548 | [(set (match_operand:SI 0 "register_operand" "=d") |
11549 | (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))] | |
11550 | "TARGET_HARD_FLOAT" | |
11551 | "efpc\t%0") | |
3af82a61 AK |
11552 | |
11553 | ||
11554 | ; Load count to block boundary | |
11555 | ||
11556 | (define_insn "lcbb" | |
11557 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3e4be43f | 11558 | (unspec:SI [(match_operand 1 "address_operand" "ZR") |
3af82a61 AK |
11559 | (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB)) |
11560 | (clobber (reg:CC CC_REGNUM))] | |
11561 | "TARGET_Z13" | |
9a36359e | 11562 | "lcbb\t%0,%a1,%b2" |
3af82a61 | 11563 | [(set_attr "op_type" "VRX")]) |
4cb4721f MK |
11564 | |
11565 | ; Handle -fsplit-stack. | |
11566 | ||
11567 | (define_expand "split_stack_prologue" | |
11568 | [(const_int 0)] | |
11569 | "" | |
11570 | { | |
11571 | s390_expand_split_stack_prologue (); | |
11572 | DONE; | |
11573 | }) | |
11574 | ||
11575 | ;; If there are operand 0 bytes available on the stack, jump to | |
11576 | ;; operand 1. | |
11577 | ||
11578 | (define_expand "split_stack_space_check" | |
11579 | [(set (pc) (if_then_else | |
11580 | (ltu (minus (reg 15) | |
11581 | (match_operand 0 "register_operand")) | |
11582 | (unspec [(const_int 0)] UNSPEC_STACK_CHECK)) | |
11583 | (label_ref (match_operand 1)) | |
11584 | (pc)))] | |
11585 | "" | |
11586 | { | |
11587 | /* Offset from thread pointer to __private_ss. */ | |
11588 | int psso = TARGET_64BIT ? 0x38 : 0x20; | |
11589 | rtx tp = s390_get_thread_pointer (); | |
11590 | rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso)); | |
11591 | rtx reg = gen_reg_rtx (Pmode); | |
11592 | rtx cc; | |
11593 | if (TARGET_64BIT) | |
11594 | emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0])); | |
11595 | else | |
11596 | emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0])); | |
11597 | cc = s390_emit_compare (GT, reg, guard); | |
11598 | s390_emit_jump (operands[1], cc); | |
11599 | ||
11600 | DONE; | |
11601 | }) | |
11602 | ||
11603 | ;; __morestack parameter block for split stack prologue. Parameters are: | |
11604 | ;; parameter block label, label to be called by __morestack, frame size, | |
11605 | ;; stack parameter size. | |
11606 | ||
11607 | (define_insn "split_stack_data" | |
11608 | [(unspec_volatile [(match_operand 0 "" "X") | |
11609 | (match_operand 1 "" "X") | |
11610 | (match_operand 2 "const_int_operand" "X") | |
11611 | (match_operand 3 "const_int_operand" "X")] | |
11612 | UNSPECV_SPLIT_STACK_DATA)] | |
8cc6307c | 11613 | "" |
4cb4721f MK |
11614 | { |
11615 | switch_to_section (targetm.asm_out.function_rodata_section | |
11616 | (current_function_decl)); | |
11617 | ||
11618 | if (TARGET_64BIT) | |
11619 | output_asm_insn (".align\t8", operands); | |
11620 | else | |
11621 | output_asm_insn (".align\t4", operands); | |
11622 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
11623 | CODE_LABEL_NUMBER (operands[0])); | |
11624 | if (TARGET_64BIT) | |
11625 | { | |
11626 | output_asm_insn (".quad\t%2", operands); | |
11627 | output_asm_insn (".quad\t%3", operands); | |
11628 | output_asm_insn (".quad\t%1-%0", operands); | |
11629 | } | |
11630 | else | |
11631 | { | |
11632 | output_asm_insn (".long\t%2", operands); | |
11633 | output_asm_insn (".long\t%3", operands); | |
11634 | output_asm_insn (".long\t%1-%0", operands); | |
11635 | } | |
11636 | ||
11637 | switch_to_section (current_function_section ()); | |
11638 | return ""; | |
11639 | } | |
11640 | [(set_attr "length" "0")]) | |
11641 | ||
11642 | ||
11643 | ;; A jg with minimal fuss for use in split stack prologue. | |
11644 | ||
11645 | (define_expand "split_stack_call" | |
11646 | [(match_operand 0 "bras_sym_operand" "X") | |
11647 | (match_operand 1 "" "")] | |
8cc6307c | 11648 | "" |
4cb4721f MK |
11649 | { |
11650 | if (TARGET_64BIT) | |
11651 | emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1])); | |
11652 | else | |
11653 | emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1])); | |
11654 | DONE; | |
11655 | }) | |
11656 | ||
11657 | (define_insn "split_stack_call_<mode>" | |
11658 | [(set (pc) (label_ref (match_operand 1 "" ""))) | |
11659 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
11660 | (reg:P 1)] | |
11661 | UNSPECV_SPLIT_STACK_CALL))] | |
8cc6307c | 11662 | "" |
4cb4721f MK |
11663 | "jg\t%0" |
11664 | [(set_attr "op_type" "RIL") | |
11665 | (set_attr "type" "branch")]) | |
11666 | ||
11667 | ;; Also a conditional one. | |
11668 | ||
11669 | (define_expand "split_stack_cond_call" | |
11670 | [(match_operand 0 "bras_sym_operand" "X") | |
11671 | (match_operand 1 "" "") | |
11672 | (match_operand 2 "" "")] | |
8cc6307c | 11673 | "" |
4cb4721f MK |
11674 | { |
11675 | if (TARGET_64BIT) | |
11676 | emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2])); | |
11677 | else | |
11678 | emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2])); | |
11679 | DONE; | |
11680 | }) | |
11681 | ||
11682 | (define_insn "split_stack_cond_call_<mode>" | |
11683 | [(set (pc) | |
11684 | (if_then_else | |
11685 | (match_operand 1 "" "") | |
11686 | (label_ref (match_operand 2 "" "")) | |
11687 | (pc))) | |
11688 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
11689 | (reg:P 1)] | |
11690 | UNSPECV_SPLIT_STACK_CALL))] | |
8cc6307c | 11691 | "" |
4cb4721f MK |
11692 | "jg%C1\t%0" |
11693 | [(set_attr "op_type" "RIL") | |
11694 | (set_attr "type" "branch")]) | |
539405d5 AK |
11695 | |
11696 | (define_insn "osc_break" | |
11697 | [(unspec_volatile [(const_int 0)] UNSPECV_OSC_BREAK)] | |
11698 | "" | |
11699 | "bcr\t7,%%r0" | |
11700 | [(set_attr "op_type" "RR")]) | |
291a9e98 AK |
11701 | |
11702 | (define_expand "speculation_barrier" | |
11703 | [(unspec_volatile [(reg:SI GPR0_REGNUM) | |
11704 | (reg:SI GPR0_REGNUM) | |
11705 | (const_int PPA_OOO_BARRIER)] | |
11706 | UNSPECV_PPA)] | |
11707 | "TARGET_ZEC12" | |
11708 | "") |