projects / thirdparty / gcc.git / blame
| Commit | Line | Data |
|---|---|---|
| 9db1d521 HP |
1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
| 2 | ;; Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc. | |
| 3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and | |
| f314b9b1 | 4 | ;; Ulrich Weigand (uweigand@de.ibm.com). |
| 9db1d521 HP |
5 | ;; This file is part of GNU CC. |
| 6 | ||
| 7 | ;; GNU CC is free software; you can redistribute it and/or modify | |
| 8 | ;; it under the terms of the GNU General Public License as published by | |
| 9 | ;; the Free Software Foundation; either version 2, or (at your option) | |
| 10 | ;; any later version. | |
| 11 | ||
| 12 | ;; GNU CC is distributed in the hope that it will be useful, | |
| 13 | ;; but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | ;; GNU General Public License for more details. | |
| 16 | ||
| 17 | ;; You should have received a copy of the GNU General Public License | |
| 18 | ;; along with GNU CC; see the file COPYING. If not, write to | |
| 19 | ;; the Free Software Foundation, 59 Temple Place - Suite 330, | |
| 20 | ;; Boston, MA 02111-1307, USA. | |
| 21 | ||
| 22 | ;; | |
| 23 | ;; Special constraints for s/390 machine description: | |
| 24 | ;; | |
| 25 | ;; a -- Any address register from 1 to 15. | |
| 26 | ;; d -- Any register from 0 to 15. | |
| 27 | ;; I -- An 8-bit constant (0..255). | |
| 28 | ;; J -- A 12-bit constant (0..4095). | |
| 29 | ;; K -- A 16-bit constant (-32768..32767). | |
| 30 | ;; Q -- A memory reference without index-register. | |
| 31 | ;; S -- Valid operand for the LARL instruction. | |
| 32 | ;; | |
| 33 | ;; Special formats used for outputting 390 instructions. | |
| 34 | ;; | |
| 35 | ;; %b -- Print a constant byte integer. xy | |
| 36 | ;; %h -- Print a signed 16-bit. wxyz | |
| 37 | ;; %N -- Print next register (second word of a DImode reg) or next word. | |
| 38 | ;; %M -- Print next register (second word of a TImode reg) or next word. | |
| 39 | ;; %O -- Print the offset of a memory reference (PLUS (REG) (CONST_INT)). | |
| 40 | ;; %R -- Print the register of a memory reference (PLUS (REG) (CONST_INT)). | |
| 41 | ;; | |
| 42 | ;; We have a special constraint for pattern matching. | |
| 43 | ;; | |
| 44 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
| 45 | ;; | |
| 9db1d521 | 46 | |
| 9db1d521 | 47 | |
| f2d3c02a HP |
48 | ;; Define an insn type attribute. This is used in function unit delay |
| 49 | ;; computations. | |
| 9db1d521 | 50 | |
| 4023fb28 | 51 | (define_attr "type" "none,integer,load,lr,la,lm,stm,cs,vs,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3" |
| f2d3c02a | 52 | (const_string "integer")) |
| 9db1d521 | 53 | |
| f2d3c02a | 54 | ;; Insn are devide in two classes: |
| d6a7951f | 55 | ;; mem: Insn accessing memory |
| f2d3c02a | 56 | ;; reg: Insn operands all in registers |
| 9db1d521 | 57 | |
| f2d3c02a HP |
58 | (define_attr "atype" "reg,mem" |
| 59 | (const_string "reg")) | |
| 9db1d521 | 60 | |
| f2d3c02a | 61 | ;; Generic pipeline function unit. |
| 9db1d521 | 62 | |
| 4023fb28 UW |
63 | (define_function_unit "integer" 1 0 |
| 64 | (eq_attr "type" "none") 0 0) | |
| 65 | ||
| f2d3c02a HP |
66 | (define_function_unit "integer" 1 0 |
| 67 | (eq_attr "type" "integer") 1 1) | |
| 9db1d521 | 68 | |
| f2d3c02a HP |
69 | (define_function_unit "integer" 1 0 |
| 70 | (eq_attr "type" "load") 1 1) | |
| 9db1d521 | 71 | |
| f2d3c02a HP |
72 | (define_function_unit "integer" 1 0 |
| 73 | (eq_attr "type" "la") 1 1) | |
| 9db1d521 | 74 | |
| f2d3c02a HP |
75 | (define_function_unit "integer" 1 0 |
| 76 | (eq_attr "type" "lr") 1 1) | |
| 9db1d521 | 77 | |
| f2d3c02a HP |
78 | (define_function_unit "integer" 1 0 |
| 79 | (eq_attr "type" "store") 1 1) | |
| 9db1d521 | 80 | |
| 4023fb28 UW |
81 | (define_function_unit "integer" 1 0 |
| 82 | (eq_attr "type" "lm") 2 2) | |
| 83 | ||
| 84 | (define_function_unit "integer" 1 0 | |
| 85 | (eq_attr "type" "stm") 2 2) | |
| 86 | ||
| 87 | (define_function_unit "integer" 1 0 | |
| 88 | (eq_attr "type" "cs") 5 5) | |
| 89 | ||
| 90 | (define_function_unit "integer" 1 0 | |
| 91 | (eq_attr "type" "vs") 30 30) | |
| 92 | ||
| f2d3c02a HP |
93 | (define_function_unit "integer" 1 0 |
| 94 | (eq_attr "type" "jsr") 5 5) | |
| 9db1d521 | 95 | |
| f2d3c02a HP |
96 | (define_function_unit "integer" 1 0 |
| 97 | (eq_attr "type" "imul") 7 7) | |
| 98 | ||
| 99 | (define_function_unit "integer" 1 0 | |
| 100 | (eq_attr "type" "fmul") 6 6) | |
| 9db1d521 | 101 | |
| f2d3c02a HP |
102 | (define_function_unit "integer" 1 0 |
| 103 | (eq_attr "type" "idiv") 33 33) | |
| 9db1d521 | 104 | |
| f2d3c02a HP |
105 | (define_function_unit "integer" 1 0 |
| 106 | (eq_attr "type" "fdiv") 33 33) | |
| 9db1d521 | 107 | |
| f2d3c02a HP |
108 | (define_function_unit "integer" 1 0 |
| 109 | (eq_attr "type" "o2") 2 2) | |
| 9db1d521 | 110 | |
| f2d3c02a HP |
111 | (define_function_unit "integer" 1 0 |
| 112 | (eq_attr "type" "o3") 3 3) | |
| 9db1d521 | 113 | |
| f2d3c02a HP |
114 | (define_function_unit "integer" 1 0 |
| 115 | (eq_attr "type" "other") 5 5) | |
| 116 | ||
| 117 | ;; Operand type. Used to default length attribute values | |
| 9db1d521 HP |
118 | |
| 119 | (define_attr "op_type" | |
| 120 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE" | |
| 121 | (const_string "RX")) | |
| 122 | ||
| 123 | ;; Length in bytes. | |
| 124 | ||
| 125 | (define_attr "length" "" | |
| 126 | (cond [ (eq_attr "op_type" "E") (const_int 2) | |
| 127 | (eq_attr "op_type" "RR") (const_int 2) | |
| 128 | (eq_attr "op_type" "RX") (const_int 4) | |
| 129 | (eq_attr "op_type" "RI") (const_int 4) | |
| 130 | (eq_attr "op_type" "RRE") (const_int 4) | |
| 131 | (eq_attr "op_type" "RS") (const_int 4) | |
| 132 | (eq_attr "op_type" "RSI") (const_int 4) | |
| 133 | (eq_attr "op_type" "RX") (const_int 4) | |
| 134 | (eq_attr "op_type" "S") (const_int 4) | |
| 135 | (eq_attr "op_type" "SI") (const_int 4) | |
| 136 | (eq_attr "op_type" "SS") (const_int 6) | |
| 137 | (eq_attr "op_type" "SSE") (const_int 6) | |
| 138 | (eq_attr "op_type" "RXE") (const_int 6) | |
| 139 | (eq_attr "op_type" "RSE") (const_int 6) | |
| 140 | (eq_attr "op_type" "RIL") (const_int 6)] | |
| 141 | (const_int 4))) | |
| 142 | ||
| 143 | ;; Define attributes for `asm' insns. | |
| 144 | ||
| f2d3c02a | 145 | (define_asm_attributes [(set_attr "type" "other") |
| 9db1d521 HP |
146 | (set_attr "op_type" "NN")]) |
| 147 | ||
| 148 | ;; | |
| 149 | ;; Condition Codes | |
| 150 | ;; | |
| 151 | ; | |
| 152 | ; CCL: Zero Nonzero Zero Nonzero (AL, ALR, SL, SLR, N, NC, NI, NR, O, OC, OI, OR, X, XC, XI, XR) | |
| 153 | ; CCA: Zero <Zero >Zero Overflow (A, AR, AH, AHI, S, SR, SH, SHI, LTR, LCR, LNR, LPR, SLA, SLDA, SLA, SRDA) | |
| 154 | ; CCU: Equal ULess UGreater -- (CL, CLR, CLI, CLM) | |
| 155 | ; CCS: Equal SLess SGreater -- (C, CR, CH, CHI, ICM) | |
| 156 | ; CCT: Zero Mixed Mixed Ones (TM, TMH, TML) | |
| 157 | ||
| 158 | ; CCZ -> CCL / CCZ1 | |
| 159 | ; CCZ1 -> CCA/CCU/CCS/CCT | |
| 160 | ; CCS -> CCA | |
| 161 | ||
| 162 | ; String: CLC, CLCL, CLCLE, CLST, CUSE, MVCL, MVCLE, MVPG, MVST, SRST | |
| 163 | ; Clobber: CKSM, CFC, CS, CDS, CUUTF, CUTFU, PLO, SPM, STCK, STCKE, TS, TRT, TRE, UPT | |
| 164 | ||
| 165 | ||
| 166 | ;; | |
| 167 | ;;- Compare instructions. | |
| 168 | ;; | |
| 169 | ||
| 170 | (define_expand "cmpdi" | |
| 171 | [(set (reg:CC 33) | |
| 172 | (compare:CC (match_operand:DI 0 "register_operand" "") | |
| 173 | (match_operand:DI 1 "general_operand" "")))] | |
| 174 | "TARGET_64BIT" | |
| 175 | " | |
| 176 | { | |
| 177 | s390_compare_op0 = operands[0]; | |
| 178 | s390_compare_op1 = operands[1]; | |
| 179 | DONE; | |
| 180 | }") | |
| 181 | ||
| 182 | (define_expand "cmpsi" | |
| 183 | [(set (reg:CC 33) | |
| 184 | (compare:CC (match_operand:SI 0 "register_operand" "") | |
| 185 | (match_operand:SI 1 "general_operand" "")))] | |
| 186 | "" | |
| 187 | " | |
| 188 | { | |
| 189 | s390_compare_op0 = operands[0]; | |
| 190 | s390_compare_op1 = operands[1]; | |
| 191 | DONE; | |
| 192 | }") | |
| 193 | ||
| 194 | ;(define_expand "cmphi" | |
| 195 | ; [(set (reg:CC 33) | |
| 196 | ; (compare:CC (match_operand:HI 0 "register_operand" "") | |
| 197 | ; (match_operand:HI 1 "general_operand" "")))] | |
| 198 | ; "" | |
| 199 | ; " | |
| 200 | ;{ | |
| 201 | ; s390_compare_op0 = operands[0]; | |
| 202 | ; s390_compare_op1 = operands[1]; | |
| 203 | ; DONE; | |
| 204 | ;}") | |
| 205 | ||
| 206 | ;(define_expand "cmpqi" | |
| 207 | ; [(set (reg:CC 33) | |
| 208 | ; (compare:CC (match_operand:QI 0 "register_operand" "") | |
| 209 | ; (match_operand:QI 1 "general_operand" "")))] | |
| 210 | ; "" | |
| 211 | ; " | |
| 212 | ;{ | |
| 213 | ; s390_compare_op0 = operands[0]; | |
| 214 | ; s390_compare_op1 = operands[1]; | |
| 215 | ; DONE; | |
| 216 | ;}") | |
| 217 | ||
| 218 | (define_expand "cmpdf" | |
| 219 | [(set (reg:CC 33) | |
| 220 | (compare:CC (match_operand:DF 0 "register_operand" "") | |
| 221 | (match_operand:DF 1 "general_operand" "")))] | |
| 222 | "TARGET_HARD_FLOAT" | |
| 223 | " | |
| 224 | { | |
| 225 | s390_compare_op0 = operands[0]; | |
| 226 | s390_compare_op1 = operands[1]; | |
| 227 | DONE; | |
| 228 | }") | |
| 229 | ||
| 230 | (define_expand "cmpsf" | |
| 231 | [(set (reg:CC 33) | |
| 232 | (compare:CC (match_operand:SF 0 "register_operand" "") | |
| 233 | (match_operand:SF 1 "general_operand" "")))] | |
| 234 | "TARGET_HARD_FLOAT" | |
| 235 | " | |
| 236 | { | |
| 237 | s390_compare_op0 = operands[0]; | |
| 238 | s390_compare_op1 = operands[1]; | |
| 239 | DONE; | |
| 240 | }") | |
| 241 | ||
| 242 | ||
| 243 | ; DI instructions | |
| 244 | ||
| 245 | (define_insn "*cmpdi_tm2" | |
| 246 | [(set (reg 33) | |
| 247 | (compare (zero_extract:DI (match_operand:DI 0 "register_operand" "d") | |
| 4023fb28 UW |
248 | (match_operand:DI 1 "const_int_operand" "n") |
| 249 | (match_operand:DI 2 "const_int_operand" "n")) | |
| 9db1d521 | 250 | (const_int 0)))] |
| 4023fb28 UW |
251 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT |
| 252 | && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 | |
| 253 | && INTVAL (operands[1]) + INTVAL (operands[2]) <= 64 | |
| 254 | && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4 | |
| 255 | == INTVAL (operands[2]) >> 4" | |
| 9db1d521 HP |
256 | "* |
| 257 | { | |
| 4023fb28 UW |
258 | int part = INTVAL (operands[2]) >> 4; |
| 259 | int block = (1 << INTVAL (operands[1])) - 1; | |
| 260 | int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15); | |
| 9db1d521 | 261 | |
| 4023fb28 | 262 | operands[2] = GEN_INT (block << shift); |
| 9db1d521 | 263 | |
| 4023fb28 UW |
264 | switch (part) |
| 265 | { | |
| 266 | case 0: return \"tmhh\\t%0,%x2\"; | |
| 267 | case 1: return \"tmhl\\t%0,%x2\"; | |
| 268 | case 2: return \"tmlh\\t%0,%x2\"; | |
| 269 | case 3: return \"tmll\\t%0,%x2\"; | |
| 270 | default: abort (); | |
| 271 | } | |
| 272 | }" | |
| 273 | [(set_attr "op_type" "RI")]) | |
| 274 | ||
| 275 | (define_insn "*cmpdi_tm_reg" | |
| 9db1d521 HP |
276 | [(set (reg 33) |
| 277 | (compare (and:DI (match_operand:DI 0 "register_operand" "%d") | |
| 4023fb28 | 278 | (match_operand:DI 1 "immediate_operand" "n")) |
| 9db1d521 | 279 | (const_int 0)))] |
| 4023fb28 UW |
280 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT |
| 281 | && s390_single_hi (operands[1], DImode, 0) >= 0" | |
| 9db1d521 HP |
282 | "* |
| 283 | { | |
| 4023fb28 UW |
284 | int part = s390_single_hi (operands[1], DImode, 0); |
| 285 | operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part)); | |
| 9db1d521 | 286 | |
| 4023fb28 | 287 | switch (part) |
| 9db1d521 | 288 | { |
| 4023fb28 UW |
289 | case 0: return \"tmhh\\t%0,%x1\"; |
| 290 | case 1: return \"tmhl\\t%0,%x1\"; | |
| 291 | case 2: return \"tmlh\\t%0,%x1\"; | |
| 292 | case 3: return \"tmll\\t%0,%x1\"; | |
| 293 | default: abort (); | |
| 9db1d521 | 294 | } |
| 9db1d521 | 295 | }" |
| 4023fb28 UW |
296 | [(set_attr "op_type" "RI")]) |
| 297 | ||
| 298 | (define_insn "*cmpdi_tm_mem" | |
| 299 | [(set (reg 33) | |
| 300 | (compare (and:DI (match_operand:DI 0 "s_operand" "%Qo") | |
| 301 | (match_operand:DI 1 "immediate_operand" "n")) | |
| 302 | (const_int 0)))] | |
| 303 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT | |
| 304 | && s390_single_qi (operands[1], DImode, 0) >= 0" | |
| 305 | "* | |
| 306 | { | |
| 307 | int part = s390_single_qi (operands[1], DImode, 0); | |
| 308 | operands[1] = GEN_INT (s390_extract_qi (operands[1], DImode, part)); | |
| 9db1d521 | 309 | |
| 4023fb28 UW |
310 | operands[0] = gen_rtx_MEM (QImode, |
| 311 | plus_constant (XEXP (operands[0], 0), part)); | |
| 312 | return \"tm\\t%0,%b1\"; | |
| 313 | }" | |
| 314 | [(set_attr "op_type" "SI") | |
| 315 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
316 | |
| 317 | (define_insn "*ltgr" | |
| 318 | [(set (reg 33) | |
| 319 | (compare (match_operand:DI 0 "register_operand" "d") | |
| 320 | (match_operand:DI 1 "const0_operand" ""))) | |
| 321 | (set (match_operand:DI 2 "register_operand" "=d") | |
| 322 | (match_dup 0))] | |
| 323 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
| 324 | "ltgr\\t%2,%0" | |
| 4023fb28 | 325 | [(set_attr "op_type" "RRE")]) |
| 9db1d521 HP |
326 | |
| 327 | (define_insn "*cmpdi_ccs_0_64" | |
| 328 | [(set (reg 33) | |
| 329 | (compare (match_operand:DI 0 "register_operand" "d") | |
| 330 | (match_operand:DI 1 "const0_operand" "")))] | |
| 331 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
| 332 | "ltgr\\t%0,%0" | |
| 4023fb28 | 333 | [(set_attr "op_type" "RRE")]) |
| 9db1d521 HP |
334 | |
| 335 | (define_insn "*cmpdi_ccs_0_31" | |
| 336 | [(set (reg 33) | |
| 337 | (compare (match_operand:DI 0 "register_operand" "d") | |
| 338 | (match_operand:DI 1 "const0_operand" "")))] | |
| 339 | "s390_match_ccmode(insn, CCSmode)" | |
| 340 | "srda\\t%0,0" | |
| 4023fb28 | 341 | [(set_attr "op_type" "RS")]) |
| 9db1d521 HP |
342 | |
| 343 | (define_insn "*cmpdi_ccs" | |
| 344 | [(set (reg 33) | |
| 345 | (compare (match_operand:DI 0 "register_operand" "d,d,d") | |
| 346 | (match_operand:DI 1 "general_operand" "d,K,m")))] | |
| 347 | "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" | |
| 348 | "@ | |
| 349 | cgr\\t%0,%1 | |
| 350 | cghi\\t%0,%c1 | |
| 351 | cg\\t%0,%1" | |
| 352 | [(set_attr "op_type" "RRE,RI,RXE") | |
| 353 | (set_attr "atype" "reg,reg,mem")]) | |
| 354 | ||
| 355 | (define_insn "*cmpdi_ccu" | |
| 356 | [(set (reg 33) | |
| 357 | (compare (match_operand:DI 0 "register_operand" "d,d") | |
| 358 | (match_operand:DI 1 "general_operand" "d,m")))] | |
| 359 | "s390_match_ccmode(insn, CCUmode) && TARGET_64BIT" | |
| 360 | "@ | |
| 361 | clgr\\t%0,%1 | |
| 362 | clg\\t%0,%1" | |
| 363 | [(set_attr "op_type" "RRE,RXE") | |
| 364 | (set_attr "atype" "reg,mem")]) | |
| 365 | ||
| 366 | (define_insn "*cmpdi_ccu_mem" | |
| 367 | [(set (reg 33) | |
| 14b3e8ef | 368 | (compare (match_operand:DI 0 "s_operand" "oQ") |
| 4023fb28 | 369 | (match_operand:DI 1 "s_imm_operand" "oQ")))] |
| 9db1d521 HP |
370 | "s390_match_ccmode(insn, CCUmode)" |
| 371 | "clc\\t%O0(8,%R0),%1" | |
| 372 | [(set_attr "op_type" "SS") | |
| 373 | (set_attr "atype" "mem")]) | |
| 374 | ||
| 375 | ; SI instructions | |
| 376 | ||
| 4023fb28 | 377 | (define_insn "*cmpsi_tm2" |
| 9db1d521 | 378 | [(set (reg 33) |
| ba956982 | 379 | (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d") |
| 4023fb28 UW |
380 | (match_operand:SI 1 "const_int_operand" "n") |
| 381 | (match_operand:SI 2 "const_int_operand" "n")) | |
| 9db1d521 | 382 | (const_int 0)))] |
| 4023fb28 UW |
383 | "s390_match_ccmode(insn, CCTmode) |
| 384 | && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 | |
| 385 | && INTVAL (operands[1]) + INTVAL (operands[2]) <= 32 | |
| 386 | && (INTVAL (operands[1]) + INTVAL (operands[2]) - 1) >> 4 | |
| 387 | == INTVAL (operands[2]) >> 4" | |
| 9db1d521 HP |
388 | "* |
| 389 | { | |
| 4023fb28 UW |
390 | int part = INTVAL (operands[2]) >> 4; |
| 391 | int block = (1 << INTVAL (operands[1])) - 1; | |
| 392 | int shift = 16 - INTVAL (operands[1]) - (INTVAL (operands[2]) & 15); | |
| 393 | ||
| 394 | operands[2] = GEN_INT (block << shift); | |
| 395 | ||
| 396 | switch (part) | |
| 9db1d521 | 397 | { |
| 4023fb28 UW |
398 | case 0: return \"tmh\\t%0,%x2\"; |
| 399 | case 1: return \"tml\\t%0,%x2\"; | |
| 400 | default: abort (); | |
| 9db1d521 | 401 | } |
| 9db1d521 | 402 | }" |
| f2d3c02a | 403 | [(set_attr "op_type" "RI")]) |
| 9db1d521 | 404 | |
| 4023fb28 | 405 | (define_insn "*cmpsi_tm_reg" |
| 9db1d521 HP |
406 | [(set (reg 33) |
| 407 | (compare (and:SI (match_operand:SI 0 "register_operand" "%d") | |
| 4023fb28 | 408 | (match_operand:SI 1 "immediate_operand" "n")) |
| 9db1d521 | 409 | (const_int 0)))] |
| 4023fb28 UW |
410 | "s390_match_ccmode(insn, CCTmode) |
| 411 | && s390_single_hi (operands[1], SImode, 0) >= 0" | |
| 9db1d521 HP |
412 | "* |
| 413 | { | |
| 4023fb28 UW |
414 | int part = s390_single_hi (operands[1], SImode, 0); |
| 415 | operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part)); | |
| 9db1d521 | 416 | |
| 4023fb28 | 417 | switch (part) |
| 9db1d521 | 418 | { |
| 4023fb28 UW |
419 | case 0: return \"tmh\\t%0,%x1\"; |
| 420 | case 1: return \"tml\\t%0,%x1\"; | |
| 421 | default: abort (); | |
| 9db1d521 | 422 | } |
| 9db1d521 | 423 | }" |
| 4023fb28 UW |
424 | [(set_attr "op_type" "RI")]) |
| 425 | ||
| 426 | (define_insn "*cmpsi_tm_mem" | |
| 427 | [(set (reg 33) | |
| 428 | (compare (and:SI (match_operand:SI 0 "s_operand" "%Qo") | |
| 429 | (match_operand:SI 1 "immediate_operand" "n")) | |
| 430 | (const_int 0)))] | |
| 431 | "s390_match_ccmode(insn, CCTmode) | |
| 432 | && s390_single_qi (operands[1], SImode, 0) >= 0" | |
| 433 | "* | |
| 434 | { | |
| 435 | int part = s390_single_qi (operands[1], SImode, 0); | |
| 436 | operands[1] = GEN_INT (s390_extract_qi (operands[1], SImode, part)); | |
| 437 | ||
| 438 | operands[0] = gen_rtx_MEM (QImode, | |
| 439 | plus_constant (XEXP (operands[0], 0), part)); | |
| 440 | return \"tm\\t%0,%b1\"; | |
| 441 | }" | |
| 442 | [(set_attr "op_type" "SI") | |
| 443 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
444 | |
| 445 | (define_insn "*ltr" | |
| 446 | [(set (reg 33) | |
| 447 | (compare (match_operand:SI 0 "register_operand" "d") | |
| 448 | (match_operand:SI 1 "const0_operand" ""))) | |
| 449 | (set (match_operand:SI 2 "register_operand" "=d") | |
| 450 | (match_dup 0))] | |
| 451 | "s390_match_ccmode(insn, CCSmode)" | |
| 452 | "ltr\\t%2,%0" | |
| f2d3c02a | 453 | [(set_attr "op_type" "RR")]) |
| 9db1d521 HP |
454 | |
| 455 | (define_insn "*icm15" | |
| 456 | [(set (reg 33) | |
| 457 | (compare (match_operand:SI 0 "s_operand" "Qo") | |
| 458 | (match_operand:SI 1 "const0_operand" ""))) | |
| 459 | (set (match_operand:SI 2 "register_operand" "=d") | |
| 460 | (match_dup 0))] | |
| 461 | "s390_match_ccmode(insn, CCSmode)" | |
| 462 | "icm\\t%2,15,%0" | |
| 463 | [(set_attr "op_type" "RS") | |
| f2d3c02a | 464 | (set_attr "atype" "mem")]) |
| 9db1d521 HP |
465 | |
| 466 | (define_insn "*icm15_cconly" | |
| 467 | [(set (reg 33) | |
| 468 | (compare (match_operand:SI 0 "s_operand" "Qo") | |
| 469 | (match_operand:SI 1 "const0_operand" ""))) | |
| 470 | (clobber (match_scratch:SI 2 "=d"))] | |
| 471 | "s390_match_ccmode(insn, CCSmode)" | |
| 472 | "icm\\t%2,15,%0" | |
| 473 | [(set_attr "op_type" "RS") | |
| f2d3c02a | 474 | (set_attr "atype" "mem")]) |
| 9db1d521 HP |
475 | |
| 476 | (define_insn "*cmpsi_ccs_0" | |
| 477 | [(set (reg 33) | |
| 478 | (compare (match_operand:SI 0 "register_operand" "d") | |
| 479 | (match_operand:SI 1 "const0_operand" "")))] | |
| 480 | "s390_match_ccmode(insn, CCSmode)" | |
| 481 | "ltr\\t%0,%0" | |
| f2d3c02a | 482 | [(set_attr "op_type" "RR")]) |
| 9db1d521 HP |
483 | |
| 484 | (define_insn "*cmpsidi_ccs" | |
| 485 | [(set (reg 33) | |
| 486 | (compare (match_operand:SI 0 "register_operand" "d") | |
| 487 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "m"))))] | |
| 488 | "s390_match_ccmode(insn, CCSmode)" | |
| 489 | "ch\\t%0,%1" | |
| 490 | [(set_attr "op_type" "RR") | |
| f2d3c02a | 491 | (set_attr "atype" "mem")]) |
| 9db1d521 HP |
492 | |
| 493 | (define_insn "*cmpsi_ccs" | |
| 494 | [(set (reg 33) | |
| 495 | (compare (match_operand:SI 0 "register_operand" "d,d,d") | |
| 496 | (match_operand:SI 1 "general_operand" "d,K,m")))] | |
| 497 | "s390_match_ccmode(insn, CCSmode)" | |
| 498 | "@ | |
| 499 | cr\\t%0,%1 | |
| 500 | chi\\t%0,%c1 | |
| 501 | c\\t%0,%1" | |
| 502 | [(set_attr "op_type" "RR,RI,RX") | |
| f2d3c02a | 503 | (set_attr "atype" "reg,reg,mem")]) |
| 9db1d521 HP |
504 | |
| 505 | (define_insn "*cmpsi_ccu" | |
| 506 | [(set (reg 33) | |
| 507 | (compare (match_operand:SI 0 "register_operand" "d,d") | |
| 508 | (match_operand:SI 1 "general_operand" "d,m")))] | |
| 509 | "s390_match_ccmode(insn, CCUmode)" | |
| 510 | "@ | |
| 511 | clr\\t%0,%1 | |
| 512 | cl\\t%0,%1" | |
| 513 | [(set_attr "op_type" "RR,RX") | |
| 514 | (set_attr "atype" "reg,mem")]) | |
| 515 | ||
| 516 | (define_insn "*cmpsi_ccu_mem" | |
| 517 | [(set (reg 33) | |
| 14b3e8ef | 518 | (compare (match_operand:SI 0 "s_operand" "oQ") |
| 4023fb28 | 519 | (match_operand:SI 1 "s_imm_operand" "oQ")))] |
| 9db1d521 HP |
520 | "s390_match_ccmode(insn, CCUmode)" |
| 521 | "clc\\t%O0(4,%R0),%1" | |
| 522 | [(set_attr "op_type" "SS") | |
| f2d3c02a | 523 | (set_attr "atype" "mem")]) |
| 9db1d521 | 524 | |
| 4023fb28 | 525 | |
| 9db1d521 HP |
526 | ; HI instructions |
| 527 | ||
| 4023fb28 UW |
528 | (define_insn "*cmphi_tm_sub" |
| 529 | [(set (reg 33) | |
| 530 | (compare (and:SI (subreg:SI (match_operand:HI 0 "s_operand" "%Qo") 0) | |
| 531 | (match_operand:SI 1 "immediate_operand" "n")) | |
| 532 | (const_int 0)))] | |
| 533 | "s390_match_ccmode(insn, CCTmode) | |
| 534 | && s390_single_qi (operands[1], HImode, 0) >= 0" | |
| 535 | "* | |
| 536 | { | |
| 537 | int part = s390_single_qi (operands[1], HImode, 0); | |
| 538 | operands[1] = GEN_INT (s390_extract_qi (operands[1], HImode, part)); | |
| 539 | ||
| 540 | operands[0] = gen_rtx_MEM (QImode, | |
| 541 | plus_constant (XEXP (operands[0], 0), part)); | |
| 542 | return \"tm\\t%0,%b1\"; | |
| 543 | }" | |
| 544 | [(set_attr "op_type" "SI") | |
| 545 | (set_attr "atype" "mem")]) | |
| 546 | ||
| 9db1d521 HP |
547 | (define_insn "*icm3" |
| 548 | [(set (reg 33) | |
| 549 | (compare (match_operand:HI 0 "s_operand" "Qo") | |
| 550 | (match_operand:HI 1 "const0_operand" ""))) | |
| 551 | (set (match_operand:HI 2 "register_operand" "=d") | |
| 552 | (match_dup 0))] | |
| 553 | "s390_match_ccmode(insn, CCSmode)" | |
| 554 | "icm\\t%2,3,%0" | |
| 555 | [(set_attr "op_type" "RS") | |
| f2d3c02a | 556 | (set_attr "atype" "mem")]) |
| 9db1d521 HP |
557 | |
| 558 | (define_insn "*cmphi_cct_0" | |
| 559 | [(set (reg 33) | |
| 560 | (compare (match_operand:HI 0 "register_operand" "d") | |
| 561 | (match_operand:HI 1 "const0_operand" "")))] | |
| 562 | "s390_match_ccmode(insn, CCTmode)" | |
| 563 | "tml\\t%0,65535" | |
| f2d3c02a | 564 | [(set_attr "op_type" "RX")]) |
| 9db1d521 HP |
565 | |
| 566 | (define_insn "*cmphi_ccs_0" | |
| 567 | [(set (reg 33) | |
| 568 | (compare (match_operand:HI 0 "s_operand" "Qo") | |
| 569 | (match_operand:HI 1 "const0_operand" ""))) | |
| 570 | (clobber (match_scratch:HI 2 "=d"))] | |
| 571 | "s390_match_ccmode(insn, CCSmode)" | |
| 572 | "icm\\t%2,3,%0" | |
| 573 | [(set_attr "op_type" "RS") | |
| f2d3c02a | 574 | (set_attr "atype" "mem")]) |
| 9db1d521 HP |
575 | |
| 576 | (define_insn "*cmphi_ccu" | |
| 577 | [(set (reg 33) | |
| 578 | (compare (match_operand:HI 0 "register_operand" "d") | |
| 4023fb28 | 579 | (match_operand:HI 1 "s_imm_operand" "Qo")))] |
| 9db1d521 HP |
580 | "s390_match_ccmode(insn, CCUmode)" |
| 581 | "clm\\t%0,3,%1" | |
| 582 | [(set_attr "op_type" "RS") | |
| f2d3c02a | 583 | (set_attr "atype" "mem")]) |
| 9db1d521 HP |
584 | |
| 585 | (define_insn "*cmphi_ccu_mem" | |
| 586 | [(set (reg 33) | |
| 14b3e8ef | 587 | (compare (match_operand:HI 0 "s_operand" "oQ") |
| 4023fb28 | 588 | (match_operand:HI 1 "s_imm_operand" "oQ")))] |
| 9db1d521 HP |
589 | "s390_match_ccmode(insn, CCUmode)" |
| 590 | "clc\\t%O0(2,%R0),%1" | |
| 591 | [(set_attr "op_type" "SS") | |
| f2d3c02a | 592 | (set_attr "atype" "mem")]) |
| 9db1d521 HP |
593 | |
| 594 | ||
| 595 | ; QI instructions | |
| 596 | ||
| 4023fb28 UW |
597 | (define_insn "*cmpqi_tm2" |
| 598 | [(set (reg 33) | |
| 599 | (compare (zero_extract:SI (match_operand:QI 0 "s_operand" "Qo") | |
| 600 | (match_operand:SI 1 "const_int_operand" "n") | |
| 601 | (match_operand:SI 2 "const_int_operand" "n")) | |
| 602 | (const_int 0)))] | |
| 603 | "s390_match_ccmode(insn, CCTmode) | |
| 604 | && INTVAL (operands[1]) >= 1 && INTVAL (operands[2]) >= 0 | |
| 605 | && INTVAL (operands[1]) + INTVAL (operands[2]) <= 8" | |
| 606 | "* | |
| 607 | { | |
| 608 | int block = (1 << INTVAL (operands[1])) - 1; | |
| 609 | int shift = 8 - INTVAL (operands[1]) - INTVAL (operands[2]); | |
| 610 | ||
| 611 | operands[2] = GEN_INT (block << shift); | |
| 612 | return \"tm\\t%0,%b2\"; | |
| 613 | }" | |
| 614 | [(set_attr "op_type" "SI") | |
| 615 | (set_attr "atype" "mem")]) | |
| 616 | ||
| 617 | (define_insn "*cmpqi_tm" | |
| 618 | [(set (reg 33) | |
| 619 | (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%d,Q") | |
| 620 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
| 621 | (const_int 0)))] | |
| 622 | "s390_match_ccmode(insn, CCTmode)" | |
| 623 | "@ | |
| 624 | tml\\t%0,%b1 | |
| 625 | tm\\t%0,%b1" | |
| 626 | [(set_attr "op_type" "RI,SI") | |
| 627 | (set_attr "atype" "reg,mem")]) | |
| 628 | ||
| 629 | (define_insn "*cmpqi_tm_sub" | |
| 630 | [(set (reg 33) | |
| 631 | (compare (and:SI (subreg:SI (match_operand:QI 0 "s_operand" "%Qo") 0) | |
| 632 | (match_operand:SI 1 "immediate_operand" "n")) | |
| 633 | (const_int 0)))] | |
| 634 | "s390_match_ccmode(insn, CCTmode)" | |
| 635 | "tm\\t%0,%b1" | |
| 636 | [(set_attr "op_type" "SI") | |
| 637 | (set_attr "atype" "mem")]) | |
| 638 | ||
| 9db1d521 HP |
639 | (define_insn "*icm1" |
| 640 | [(set (reg 33) | |
| 641 | (compare (match_operand:QI 0 "s_operand" "Qo") | |
| 642 | (match_operand:QI 1 "const0_operand" ""))) | |
| 643 | (set (match_operand:QI 2 "register_operand" "=d") | |
| 644 | (match_dup 0))] | |
| 645 | "s390_match_ccmode(insn, CCSmode)" | |
| 646 | "icm\\t%2,1,%0" | |
| 647 | [(set_attr "op_type" "RS") | |
| f2d3c02a | 648 | (set_attr "atype" "mem")]) |
| 9db1d521 HP |
649 | |
| 650 | (define_insn "*tm_0" | |
| 651 | [(set (reg 33) | |
| 652 | (compare (zero_extend:SI (and:QI (match_operand:QI 0 "s_operand" "Qo") | |
| 653 | (match_operand:QI 1 "immediate_operand" ""))) | |
| 654 | (const_int 0)))] | |
| 655 | "s390_match_ccmode(insn, CCTmode) && | |
| 656 | INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256" | |
| 657 | "tm\\t%0,%1" | |
| 658 | [(set_attr "op_type" "RI") | |
| f2d3c02a | 659 | (set_attr "atype" "mem")]) |
| 9db1d521 HP |
660 | |
| 661 | (define_insn "*cmpqi_cct_0" | |
| 662 | [(set (reg 33) | |
| 663 | (compare (match_operand:QI 0 "register_operand" "d") | |
| 664 | (match_operand:QI 1 "const0_operand" "")))] | |
| 665 | "s390_match_ccmode(insn, CCTmode)" | |
| 666 | "tml\\t%0,255" | |
| f2d3c02a | 667 | [(set_attr "op_type" "RI")]) |
| 9db1d521 HP |
668 | |
| 669 | (define_insn "*cmpqi_ccs_0" | |
| 670 | [(set (reg 33) | |
| 671 | (compare (match_operand:QI 0 "s_operand" "Qo") | |
| 672 | (match_operand:QI 1 "const0_operand" ""))) | |
| 673 | (clobber (match_scratch:QI 2 "=d"))] | |
| 674 | "s390_match_ccmode(insn, CCSmode)" | |
| 675 | "icm\\t%2,1,%0" | |
| 4023fb28 UW |
676 | [(set_attr "op_type" "RS") |
| 677 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
678 | |
| 679 | (define_insn "*cmpqi_ccu_0" | |
| 680 | [(set (reg 33) | |
| 681 | (compare (match_operand:QI 0 "s_operand" "Qo") | |
| 682 | (match_operand:QI 1 "const0_operand" "")))] | |
| 683 | "s390_match_ccmode(insn, CCUmode)" | |
| 684 | "cli\\t%0,0" | |
| 685 | [(set_attr "op_type" "SI") | |
| f2d3c02a | 686 | (set_attr "atype" "mem")]) |
| 9db1d521 HP |
687 | |
| 688 | (define_insn "*cmpqi_ccu" | |
| 689 | [(set (reg 33) | |
| 690 | (compare (match_operand:QI 0 "register_operand" "d") | |
| 4023fb28 | 691 | (match_operand:QI 1 "s_imm_operand" "Qo")))] |
| 9db1d521 HP |
692 | "s390_match_ccmode(insn, CCUmode)" |
| 693 | "clm\\t%0,1,%1" | |
| 694 | [(set_attr "op_type" "RS") | |
| f2d3c02a | 695 | (set_attr "atype" "mem")]) |
| 9db1d521 HP |
696 | |
| 697 | (define_insn "*cmpqi_ccu_immed" | |
| 698 | [(set (reg 33) | |
| 4023fb28 UW |
699 | (compare (match_operand:QI 0 "s_operand" "Qo") |
| 700 | (match_operand:QI 1 "const_int_operand" "n")))] | |
| 9db1d521 HP |
701 | "s390_match_ccmode(insn, CCUmode) && |
| 702 | INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256" | |
| 703 | "cli\\t%0,%1" | |
| 704 | [(set_attr "op_type" "SI") | |
| f2d3c02a | 705 | (set_attr "atype" "mem")]) |
| 9db1d521 HP |
706 | |
| 707 | (define_insn "*cmpqi_ccu_mem" | |
| 708 | [(set (reg 33) | |
| 14b3e8ef | 709 | (compare (match_operand:QI 0 "s_operand" "oQ") |
| 4023fb28 | 710 | (match_operand:QI 1 "s_imm_operand" "oQ")))] |
| 9db1d521 HP |
711 | "s390_match_ccmode(insn, CCUmode)" |
| 712 | "clc\\t%O0(1,%R0),%1" | |
| 713 | [(set_attr "op_type" "SS") | |
| f2d3c02a | 714 | (set_attr "atype" "mem")]) |
| 9db1d521 HP |
715 | |
| 716 | ||
| 717 | ; DF instructions | |
| 718 | ||
| 719 | (define_insn "*cmpdf_ccs_0" | |
| 720 | [(set (reg 33) | |
| 721 | (compare (match_operand:DF 0 "register_operand" "f") | |
| 722 | (match_operand:DF 1 "const0_operand" "")))] | |
| 723 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 724 | "ltdbr\\t%0,%0" | |
| f2d3c02a | 725 | [(set_attr "op_type" "RR")]) |
| 9db1d521 HP |
726 | |
| 727 | (define_insn "*cmpdf_ccs_0_ibm" | |
| 728 | [(set (reg 33) | |
| 729 | (compare (match_operand:DF 0 "register_operand" "f") | |
| 730 | (match_operand:DF 1 "const0_operand" "")))] | |
| 731 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 732 | "ltdr\\t%0,%0" | |
| f2d3c02a | 733 | [(set_attr "op_type" "RR")]) |
| 9db1d521 HP |
734 | |
| 735 | (define_insn "*cmpdf_ccs" | |
| 736 | [(set (reg 33) | |
| 737 | (compare (match_operand:DF 0 "register_operand" "f,f") | |
| 4023fb28 | 738 | (match_operand:DF 1 "general_operand" "f,m")))] |
| 9db1d521 HP |
739 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| 740 | "@ | |
| 741 | cdbr\\t%0,%1 | |
| 742 | cdb\\t%0,%1" | |
| 743 | [(set_attr "op_type" "RR,RX") | |
| f2d3c02a | 744 | (set_attr "atype" "reg,mem")]) |
| 9db1d521 HP |
745 | |
| 746 | (define_insn "*cmpdf_ccs_ibm" | |
| 747 | [(set (reg 33) | |
| 748 | (compare (match_operand:DF 0 "register_operand" "f,f") | |
| 4023fb28 | 749 | (match_operand:DF 1 "general_operand" "f,m")))] |
| 9db1d521 HP |
750 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
| 751 | "@ | |
| 752 | cdr\\t%0,%1 | |
| 753 | cd\\t%0,%1" | |
| 754 | [(set_attr "op_type" "RR,RX") | |
| f2d3c02a | 755 | (set_attr "atype" "reg,mem")]) |
| 9db1d521 HP |
756 | |
| 757 | ||
| 758 | ; SF instructions | |
| 759 | ||
| 760 | (define_insn "*cmpsf_ccs_0" | |
| 761 | [(set (reg 33) | |
| 762 | (compare (match_operand:SF 0 "register_operand" "f") | |
| 763 | (match_operand:SF 1 "const0_operand" "")))] | |
| 764 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 765 | "ltebr\\t%0,%0" | |
| f2d3c02a | 766 | [(set_attr "op_type" "RR")]) |
| 9db1d521 HP |
767 | |
| 768 | (define_insn "*cmpsf_ccs_0_ibm" | |
| 769 | [(set (reg 33) | |
| 770 | (compare (match_operand:SF 0 "register_operand" "f") | |
| 771 | (match_operand:SF 1 "const0_operand" "")))] | |
| 772 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 773 | "lter\\t%0,%0" | |
| f2d3c02a | 774 | [(set_attr "op_type" "RR")]) |
| 9db1d521 HP |
775 | |
| 776 | (define_insn "*cmpsf_ccs" | |
| 777 | [(set (reg 33) | |
| 778 | (compare (match_operand:SF 0 "register_operand" "f,f") | |
| 4023fb28 | 779 | (match_operand:SF 1 "general_operand" "f,m")))] |
| 9db1d521 HP |
780 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| 781 | "@ | |
| 782 | cebr\\t%0,%1 | |
| 783 | ceb\\t%0,%1" | |
| 784 | [(set_attr "op_type" "RR,RX") | |
| f2d3c02a | 785 | (set_attr "atype" "reg,mem")]) |
| 9db1d521 HP |
786 | |
| 787 | (define_insn "*cmpsf_ccs" | |
| 788 | [(set (reg 33) | |
| 789 | (compare (match_operand:SF 0 "register_operand" "f,f") | |
| 4023fb28 | 790 | (match_operand:SF 1 "general_operand" "f,m")))] |
| 9db1d521 HP |
791 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
| 792 | "@ | |
| 793 | cer\\t%0,%1 | |
| 794 | ce\\t%0,%1" | |
| 795 | [(set_attr "op_type" "RR,RX") | |
| f2d3c02a | 796 | (set_attr "atype" "reg,mem")]) |
| 9db1d521 HP |
797 | |
| 798 | ||
| 799 | ;; | |
| 800 | ;;- Move instructions. | |
| 801 | ;; | |
| 802 | ||
| 803 | ; | |
| 804 | ; movti instruction pattern(s). | |
| 805 | ; | |
| 806 | ||
| 4023fb28 UW |
807 | (define_insn "*movti_ss" |
| 808 | [(set (match_operand:TI 0 "s_operand" "=Qo") | |
| 809 | (match_operand:TI 1 "s_imm_operand" "Qo"))] | |
| 810 | "" | |
| 811 | "mvc\\t%O0(16,%R0),%1" | |
| 812 | [(set_attr "op_type" "SS") | |
| 813 | (set_attr "atype" "mem")]) | |
| 814 | ||
| 9db1d521 | 815 | (define_insn "movti" |
| 4023fb28 UW |
816 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,Q,d,m") |
| 817 | (match_operand:TI 1 "general_operand" "Q,d,dKm,d"))] | |
| 9db1d521 | 818 | "TARGET_64BIT" |
| 4023fb28 UW |
819 | "@ |
| 820 | lmg\\t%0,%N0,%1 | |
| 821 | stmg\\t%1,%N1,%0 | |
| 822 | # | |
| 823 | #" | |
| 824 | [(set_attr "op_type" "RSE,RSE,NN,NN") | |
| 825 | (set_attr "atype" "mem")]) | |
| 826 | ||
| 827 | (define_split | |
| 828 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
| 829 | (match_operand:TI 1 "general_operand" ""))] | |
| 830 | "TARGET_64BIT && reload_completed | |
| 831 | && !s_operand (operands[0], VOIDmode) | |
| 832 | && !s_operand (operands[1], VOIDmode) | |
| 833 | && (register_operand (operands[0], VOIDmode) | |
| 834 | || register_operand (operands[1], VOIDmode)) | |
| 835 | && (!register_operand (operands[0], VOIDmode) | |
| 836 | || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode), | |
| 837 | operands[1]) | |
| 838 | || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, TImode), | |
| 839 | operands[1]))" | |
| 840 | [(set (match_dup 2) (match_dup 4)) | |
| 841 | (set (match_dup 3) (match_dup 5))] | |
| 842 | " | |
| 9db1d521 | 843 | { |
| 4023fb28 UW |
844 | if (!register_operand (operands[0], VOIDmode) |
| 845 | || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, TImode), | |
| 846 | operands[1])) | |
| 9db1d521 | 847 | { |
| 4023fb28 UW |
848 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
| 849 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
| 850 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
| 851 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
| 9db1d521 | 852 | } |
| 4023fb28 UW |
853 | else |
| 854 | { | |
| 855 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
| 856 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
| 857 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
| 858 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
| 859 | } | |
| 860 | }") | |
| 861 | ||
| 862 | (define_split | |
| 863 | [(set (match_operand:TI 0 "register_operand" "") | |
| 864 | (match_operand:TI 1 "memory_operand" ""))] | |
| 865 | "TARGET_64BIT && reload_completed | |
| 866 | && !s_operand (operands[1], VOIDmode)" | |
| 867 | [(set (match_dup 2) (match_dup 3)) | |
| 868 | (set (match_dup 0) (mem:TI (match_dup 2)))] | |
| 9f37ccb1 | 869 | "operands[2] = operand_subword (operands[0], 1, 0, TImode); |
| 4023fb28 | 870 | operands[3] = XEXP (operands[1], 0);") |
| 9db1d521 HP |
871 | |
| 872 | ; | |
| 873 | ; movdi instruction pattern(s). | |
| 874 | ; | |
| 875 | ||
| 876 | ;; If generating PIC code and operands[1] is a symbolic CONST, emit a | |
| 877 | ;; move to get the address of the symbolic object from the GOT. | |
| 878 | ||
| 879 | (define_expand "movdi" | |
| 880 | [(set (match_operand:DI 0 "general_operand" "") | |
| 881 | (match_operand:DI 1 "general_operand" ""))] | |
| 882 | "" | |
| 883 | " | |
| 884 | { | |
| 4023fb28 | 885 | /* Handle PIC symbolic constants. */ |
| 9db1d521 HP |
886 | if (TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1])) |
| 887 | emit_pic_move (operands, DImode); | |
| 4023fb28 UW |
888 | |
| 889 | /* During and after reload, we need to force constants | |
| 890 | to the literal pool ourselves, if necessary. */ | |
| 891 | if ((reload_in_progress || reload_completed) | |
| 892 | && CONSTANT_P (operands[1]) | |
| 893 | && (!legitimate_reload_constant_p (operands[1]) | |
| 894 | || fp_operand (operands[0], VOIDmode))) | |
| 895 | operands[1] = force_const_mem (DImode, operands[1]); | |
| 9db1d521 HP |
896 | }") |
| 897 | ||
| 4023fb28 UW |
898 | (define_insn "*movdi_lhi" |
| 899 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 900 | (match_operand:DI 1 "immediate_operand" "K"))] | |
| 901 | "TARGET_64BIT | |
| 902 | && GET_CODE (operands[1]) == CONST_INT | |
| 903 | && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K') | |
| 904 | && !fp_operand (operands[0], VOIDmode)" | |
| 905 | "lghi\\t%0,%h1" | |
| 906 | [(set_attr "op_type" "RI") | |
| 907 | (set_attr "atype" "reg")]) | |
| 908 | ||
| 909 | (define_insn "*movdi_lli" | |
| 910 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 911 | (match_operand:DI 1 "immediate_operand" "n"))] | |
| 912 | "TARGET_64BIT && s390_single_hi (operands[1], DImode, 0) >= 0 | |
| 913 | && !fp_operand (operands[0], VOIDmode)" | |
| 914 | "* | |
| 915 | { | |
| 916 | int part = s390_single_hi (operands[1], DImode, 0); | |
| 917 | operands[1] = GEN_INT (s390_extract_hi (operands[1], DImode, part)); | |
| 918 | ||
| 919 | switch (part) | |
| 920 | { | |
| 921 | case 0: return \"llihh\\t%0,%x1\"; | |
| 922 | case 1: return \"llihl\\t%0,%x1\"; | |
| 923 | case 2: return \"llilh\\t%0,%x1\"; | |
| 924 | case 3: return \"llill\\t%0,%x1\"; | |
| 925 | default: abort (); | |
| 926 | } | |
| 927 | }" | |
| 928 | [(set_attr "op_type" "RI") | |
| 929 | (set_attr "atype" "reg")]) | |
| 930 | ||
| 931 | (define_insn "*movdi_larl" | |
| 932 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 933 | (match_operand:DI 1 "larl_operand" "X"))] | |
| 934 | "TARGET_64BIT | |
| 935 | && !fp_operand (operands[0], VOIDmode)" | |
| 936 | "larl\\t%0,%1" | |
| 937 | [(set_attr "op_type" "RIL") | |
| 938 | (set_attr "atype" "reg") | |
| 939 | (set_attr "type" "la")]) | |
| 940 | ||
| 941 | (define_insn "*movdi_ss" | |
| 942 | [(set (match_operand:DI 0 "s_operand" "=Qo") | |
| 943 | (match_operand:DI 1 "s_imm_operand" "Qo"))] | |
| 944 | "" | |
| 945 | "mvc\\t%O0(8,%R0),%1" | |
| 946 | [(set_attr "op_type" "SS") | |
| 947 | (set_attr "atype" "mem")]) | |
| 948 | ||
| 9db1d521 | 949 | (define_insn "*movdi_64" |
| 4023fb28 UW |
950 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,m,f,f,m") |
| 951 | (match_operand:DI 1 "general_operand" "d,m,d,f,m,f"))] | |
| 9db1d521 HP |
952 | "TARGET_64BIT" |
| 953 | "@ | |
| 954 | lgr\\t%0,%1 | |
| 9db1d521 HP |
955 | lg\\t%0,%1 |
| 956 | stg\\t%1,%0 | |
| 4023fb28 UW |
957 | ldr\\t%0,%1 |
| 958 | ld\\t%0,%1 | |
| 959 | std\\t%1,%0" | |
| 960 | [(set_attr "op_type" "RR,RXE,RXE,RR,RX,RX") | |
| 961 | (set_attr "atype" "reg,mem,mem,reg,mem,mem")]) | |
| 9db1d521 HP |
962 | |
| 963 | (define_insn "*movdi_31" | |
| 4023fb28 UW |
964 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,m,f,f,m") |
| 965 | (match_operand:DI 1 "general_operand" "Q,d,dKm,d,f,m,f"))] | |
| 9db1d521 | 966 | "!TARGET_64BIT" |
| 4023fb28 UW |
967 | "@ |
| 968 | lm\\t%0,%N0,%1 | |
| 969 | stm\\t%1,%N1,%0 | |
| 970 | # | |
| 971 | # | |
| 972 | ldr\\t%0,%1 | |
| 973 | ld\\t%0,%1 | |
| 974 | std\\t%1,%0" | |
| 975 | [(set_attr "op_type" "RS,RS,NN,NN,RR,RX,RX") | |
| 976 | (set_attr "atype" "mem,mem,*,*,reg,mem,mem")]) | |
| 977 | ||
| 978 | (define_split | |
| 979 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
| 980 | (match_operand:DI 1 "general_operand" ""))] | |
| 981 | "!TARGET_64BIT && reload_completed | |
| 982 | && !fp_operand (operands[0], VOIDmode) | |
| 983 | && !fp_operand (operands[1], VOIDmode) | |
| 984 | && !s_operand (operands[0], VOIDmode) | |
| 985 | && !s_operand (operands[1], VOIDmode) | |
| 986 | && (register_operand (operands[0], VOIDmode) | |
| 987 | || register_operand (operands[1], VOIDmode)) | |
| 988 | && (!register_operand (operands[0], VOIDmode) | |
| 989 | || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode), | |
| 990 | operands[1]) | |
| 991 | || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DImode), | |
| 992 | operands[1]))" | |
| 993 | [(set (match_dup 2) (match_dup 4)) | |
| 994 | (set (match_dup 3) (match_dup 5))] | |
| 995 | " | |
| 9db1d521 | 996 | { |
| 4023fb28 UW |
997 | if (!register_operand (operands[0], VOIDmode) |
| 998 | || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DImode), | |
| 999 | operands[1])) | |
| 9db1d521 | 1000 | { |
| 4023fb28 UW |
1001 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
| 1002 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
| 1003 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
| 1004 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
| 1005 | } | |
| 1006 | else | |
| 1007 | { | |
| 1008 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
| 1009 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
| 1010 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
| 1011 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
| 1012 | } | |
| 1013 | }") | |
| 9db1d521 | 1014 | |
| 4023fb28 UW |
1015 | (define_split |
| 1016 | [(set (match_operand:DI 0 "register_operand" "") | |
| 1017 | (match_operand:DI 1 "memory_operand" ""))] | |
| 1018 | "!TARGET_64BIT && reload_completed | |
| 1019 | && !fp_operand (operands[0], VOIDmode) | |
| 1020 | && !fp_operand (operands[1], VOIDmode) | |
| 1021 | && !s_operand (operands[1], VOIDmode)" | |
| 1022 | [(set (match_dup 2) (match_dup 3)) | |
| 1023 | (set (match_dup 0) (mem:DI (match_dup 2)))] | |
| 1024 | "operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
| 1025 | operands[3] = XEXP (operands[1], 0);") | |
| 9db1d521 HP |
1026 | |
| 1027 | ; | |
| 1028 | ; movsi instruction pattern(s). | |
| 1029 | ; | |
| 1030 | ||
| 1031 | ;; If generating PIC code and operands[1] is a symbolic CONST, emit a | |
| 1032 | ;; move to get the address of the symbolic object from the GOT. | |
| 1033 | ||
| 1034 | (define_expand "movsi" | |
| 1035 | [(set (match_operand:SI 0 "general_operand" "") | |
| 1036 | (match_operand:SI 1 "general_operand" ""))] | |
| 1037 | "" | |
| 1038 | " | |
| 1039 | { | |
| 4023fb28 UW |
1040 | /* Handle PIC symbolic constants. */ |
| 1041 | if (!TARGET_64BIT && flag_pic && SYMBOLIC_CONST (operands[1])) | |
| 9db1d521 | 1042 | emit_pic_move (operands, SImode); |
| ba956982 UW |
1043 | |
| 1044 | /* expr.c tries to load an effective address using | |
| 1045 | force_reg. This fails because we don't have a | |
| 1046 | generic load_address pattern. Convert the move | |
| 1047 | to a proper arithmetic operation instead, unless | |
| 1048 | it is guaranteed to be OK. */ | |
| 1049 | if (GET_CODE (operands[1]) == PLUS | |
| 1050 | && !legitimate_la_operand_p (operands[1])) | |
| 1051 | { | |
| 1052 | operands[1] = force_operand (operands[1], operands[0]); | |
| 1053 | if (operands[1] == operands[0]) | |
| 1054 | DONE; | |
| 1055 | } | |
| 4023fb28 UW |
1056 | |
| 1057 | /* During and after reload, we need to force constants | |
| 1058 | to the literal pool ourselves, if necessary. */ | |
| 1059 | if ((reload_in_progress || reload_completed) | |
| 1060 | && CONSTANT_P (operands[1]) | |
| 1061 | && (!legitimate_reload_constant_p (operands[1]) | |
| 1062 | || fp_operand (operands[0], VOIDmode))) | |
| 1063 | operands[1] = force_const_mem (SImode, operands[1]); | |
| 9db1d521 HP |
1064 | }") |
| 1065 | ||
| 4023fb28 UW |
1066 | (define_insn "*movsi_lhi" |
| 1067 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1068 | (match_operand:SI 1 "immediate_operand" "K"))] | |
| 1069 | "GET_CODE (operands[1]) == CONST_INT | |
| 1070 | && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K') | |
| 1071 | && !fp_operand (operands[0], VOIDmode)" | |
| 1072 | "lhi\\t%0,%h1" | |
| 1073 | [(set_attr "op_type" "RI")]) | |
| 1074 | ||
| 1075 | (define_insn "*movsi_lli" | |
| 1076 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 1077 | (match_operand:SI 1 "immediate_operand" "n"))] | |
| 1078 | "TARGET_64BIT && s390_single_hi (operands[1], SImode, 0) >= 0 | |
| 1079 | && !fp_operand (operands[0], VOIDmode)" | |
| 1080 | "* | |
| 1081 | { | |
| 1082 | int part = s390_single_hi (operands[1], SImode, 0); | |
| 1083 | operands[1] = GEN_INT (s390_extract_hi (operands[1], SImode, part)); | |
| 1084 | ||
| 1085 | switch (part) | |
| 1086 | { | |
| 1087 | case 0: return \"llilh\\t%0,%x1\"; | |
| 1088 | case 1: return \"llill\\t%0,%x1\"; | |
| 1089 | default: abort (); | |
| 1090 | } | |
| 1091 | }" | |
| 1092 | [(set_attr "op_type" "RI")]) | |
| 1093 | ||
| 1094 | (define_insn "*movsi_ss" | |
| 1095 | [(set (match_operand:SI 0 "s_operand" "=Qo") | |
| 1096 | (match_operand:SI 1 "s_imm_operand" "Qo"))] | |
| 1097 | "" | |
| 1098 | "mvc\\t%O0(4,%R0),%1" | |
| 1099 | [(set_attr "op_type" "SS") | |
| 1100 | (set_attr "atype" "mem")]) | |
| 1101 | ||
| 9db1d521 | 1102 | (define_insn "*movsi" |
| 4023fb28 UW |
1103 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,m,f,f,m") |
| 1104 | (match_operand:SI 1 "general_operand" "d,m,d,f,m,f"))] | |
| 9db1d521 HP |
1105 | "" |
| 1106 | "@ | |
| 1107 | lr\\t%0,%1 | |
| 9db1d521 HP |
1108 | l\\t%0,%1 |
| 1109 | st\\t%1,%0 | |
| 4023fb28 UW |
1110 | ler\\t%0,%1 |
| 1111 | le\\t%0,%1 | |
| 1112 | ste\\t%1,%0" | |
| 1113 | [(set_attr "op_type" "RR,RX,RX,RR,RX,RX") | |
| 1114 | (set_attr "atype" "reg,mem,mem,reg,mem,mem")]) | |
| 9db1d521 HP |
1115 | |
| 1116 | ||
| 1117 | ; | |
| 1118 | ; movhi instruction pattern(s). | |
| 1119 | ; | |
| 1120 | ||
| 1121 | (define_insn "movhi" | |
| 1122 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m") | |
| 4023fb28 | 1123 | (match_operand:HI 1 "general_operand" "d,n,m,d"))] |
| 9db1d521 HP |
1124 | "" |
| 1125 | "@ | |
| 1126 | lr\\t%0,%1 | |
| 1127 | lhi\\t%0,%h1 | |
| 1128 | lh\\t%0,%1 | |
| 1129 | sth\\t%1,%0" | |
| 1130 | [(set_attr "op_type" "RR,RI,RX,RX") | |
| f2d3c02a | 1131 | (set_attr "atype" "reg,reg,mem,mem")]) |
| 9db1d521 | 1132 | |
| 4023fb28 | 1133 | |
| 9db1d521 HP |
1134 | ; |
| 1135 | ; movqi instruction pattern(s). | |
| 1136 | ; | |
| 1137 | ||
| 1138 | (define_insn "movqi_64" | |
| 1139 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q") | |
| 4023fb28 | 1140 | (match_operand:QI 1 "general_operand" "d,n,m,d,n"))] |
| 9db1d521 HP |
1141 | "TARGET_64BIT" |
| 1142 | "@ | |
| 1143 | lr\\t%0,%1 | |
| 4023fb28 | 1144 | lhi\\t%0,%b1 |
| 9db1d521 HP |
1145 | llgc\\t%0,%1 |
| 1146 | stc\\t%1,%0 | |
| 1147 | mvi\\t%0,%b1" | |
| 1148 | [(set_attr "op_type" "RR,RI,RXE,RX,SI") | |
| f2d3c02a | 1149 | (set_attr "atype" "reg,reg,mem,mem,mem")]) |
| 9db1d521 | 1150 | |
| 4023fb28 | 1151 | |
| 9db1d521 HP |
1152 | (define_insn "movqi" |
| 1153 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q") | |
| 4023fb28 | 1154 | (match_operand:QI 1 "general_operand" "d,n,m,d,n"))] |
| 9db1d521 HP |
1155 | "" |
| 1156 | "@ | |
| 1157 | lr\\t%0,%1 | |
| 4023fb28 | 1158 | lhi\\t%0,%b1 |
| 9db1d521 HP |
1159 | ic\\t%0,%1 |
| 1160 | stc\\t%1,%0 | |
| 1161 | mvi\\t%0,%b1" | |
| 4023fb28 | 1162 | [(set_attr "op_type" "RR,RI,RX,RX,SI") |
| f2d3c02a | 1163 | (set_attr "atype" "reg,reg,mem,mem,mem")]) |
| 9db1d521 | 1164 | |
| 4023fb28 | 1165 | |
| 9db1d521 HP |
1166 | ; |
| 1167 | ; moveqstrictqi instruction pattern(s). | |
| 1168 | ; | |
| 1169 | ||
| 1170 | (define_insn "*movstrictqi" | |
| 4023fb28 UW |
1171 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) |
| 1172 | (match_operand:QI 1 "memory_operand" "m"))] | |
| 9db1d521 | 1173 | "" |
| 4023fb28 UW |
1174 | "ic\\t%0,%1" |
| 1175 | [(set_attr "op_type" "RX") | |
| 1176 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
1177 | |
| 1178 | ; | |
| 1179 | ; movstricthi instruction pattern(s). | |
| 1180 | ; | |
| 1181 | ||
| 1182 | (define_insn "*movstricthi" | |
| 4023fb28 UW |
1183 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) |
| 1184 | (match_operand:HI 1 "s_imm_operand" "Qo")) | |
| 9db1d521 HP |
1185 | (clobber (reg:CC 33))] |
| 1186 | "" | |
| 4023fb28 UW |
1187 | "icm\\t%0,3,%1" |
| 1188 | [(set_attr "op_type" "RS") | |
| f2d3c02a | 1189 | (set_attr "atype" "mem")]) |
| 9db1d521 HP |
1190 | |
| 1191 | ||
| 1192 | ; | |
| 1193 | ; movstrictsi instruction pattern(s). | |
| 1194 | ; | |
| 1195 | ||
| 1196 | (define_insn "movestrictsi" | |
| 4023fb28 UW |
1197 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d")) |
| 1198 | (match_operand:SI 1 "general_operand" "d,m"))] | |
| 9db1d521 HP |
1199 | "TARGET_64BIT" |
| 1200 | "@ | |
| 1201 | lr\\t%0,%1 | |
| 4023fb28 UW |
1202 | l\\t%0,%1" |
| 1203 | [(set_attr "op_type" "RR,RS") | |
| 1204 | (set_attr "atype" "reg,mem")]) | |
| 9db1d521 HP |
1205 | |
| 1206 | ||
| 1207 | ; | |
| 1208 | ; movdf instruction pattern(s). | |
| 1209 | ; | |
| 1210 | ||
| 1211 | (define_expand "movdf" | |
| 1212 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
| 1213 | (match_operand:DF 1 "general_operand" ""))] | |
| 1214 | "" | |
| 1215 | " | |
| 1216 | { | |
| 4023fb28 UW |
1217 | /* During and after reload, we need to force constants |
| 1218 | to the literal pool ourselves, if necessary. */ | |
| 1219 | if ((reload_in_progress || reload_completed) | |
| 1220 | && CONSTANT_P (operands[1])) | |
| 1221 | operands[1] = force_const_mem (DFmode, operands[1]); | |
| 9db1d521 HP |
1222 | }") |
| 1223 | ||
| 4023fb28 UW |
1224 | (define_insn "*movdf_ss" |
| 1225 | [(set (match_operand:DF 0 "s_operand" "=Qo") | |
| 1226 | (match_operand:DF 1 "s_imm_operand" "Qo"))] | |
| 1227 | "" | |
| 1228 | "mvc\\t%O0(8,%R0),%1" | |
| 1229 | [(set_attr "op_type" "SS") | |
| 1230 | (set_attr "atype" "mem")]) | |
| 1231 | ||
| 9db1d521 | 1232 | (define_insn "*movdf_64" |
| 4023fb28 UW |
1233 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,d,m") |
| 1234 | (match_operand:DF 1 "general_operand" "f,m,f,d,m,d"))] | |
| 1235 | "TARGET_64BIT" | |
| 9db1d521 HP |
1236 | "@ |
| 1237 | ldr\\t%0,%1 | |
| 1238 | ld\\t%0,%1 | |
| 1239 | std\\t%1,%0 | |
| 9db1d521 | 1240 | lgr\\t%0,%1 |
| 4023fb28 UW |
1241 | lg\\t%0,%1 |
| 1242 | stg\\t%1,%0" | |
| 1243 | [(set_attr "op_type" "RR,RX,RX,RR,RXE,RXE") | |
| 1244 | (set_attr "atype" "reg,mem,mem,reg,mem,mem")]) | |
| 9db1d521 HP |
1245 | |
| 1246 | (define_insn "*movdf_31" | |
| 4023fb28 UW |
1247 | [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,Q,d,m") |
| 1248 | (match_operand:DF 1 "general_operand" "f,m,f,Q,d,dKm,d"))] | |
| 1249 | "!TARGET_64BIT" | |
| 9db1d521 | 1250 | "@ |
| 4023fb28 UW |
1251 | ldr\\t%0,%1 |
| 1252 | ld\\t%0,%1 | |
| 1253 | std\\t%1,%0 | |
| 1254 | lm\\t%0,%N0,%1 | |
| 1255 | stm\\t%1,%N1,%0 | |
| 1256 | # | |
| 1257 | #" | |
| 1258 | [(set_attr "op_type" "RR,RX,RX,RS,RS,NN,NN") | |
| 1259 | (set_attr "atype" "reg,mem,mem,mem,mem,*,*")]) | |
| 1260 | ||
| 1261 | (define_split | |
| 1262 | [(set (match_operand:DF 0 "nonimmediate_operand" "") | |
| 1263 | (match_operand:DF 1 "general_operand" ""))] | |
| 1264 | "!TARGET_64BIT && reload_completed | |
| 1265 | && !fp_operand (operands[0], VOIDmode) | |
| 1266 | && !fp_operand (operands[1], VOIDmode) | |
| 1267 | && !s_operand (operands[0], VOIDmode) | |
| 1268 | && !s_operand (operands[1], VOIDmode) | |
| 1269 | && (register_operand (operands[0], VOIDmode) | |
| 1270 | || register_operand (operands[1], VOIDmode)) | |
| 1271 | && (!register_operand (operands[0], VOIDmode) | |
| 1272 | || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode), | |
| 1273 | operands[1]) | |
| 1274 | || !reg_overlap_mentioned_p (operand_subword (operands[0], 1, 0, DFmode), | |
| 1275 | operands[1]))" | |
| 1276 | [(set (match_dup 2) (match_dup 4)) | |
| 1277 | (set (match_dup 3) (match_dup 5))] | |
| 1278 | " | |
| 9db1d521 | 1279 | { |
| 4023fb28 UW |
1280 | if (!register_operand (operands[0], VOIDmode) |
| 1281 | || !reg_overlap_mentioned_p (operand_subword (operands[0], 0, 0, DFmode), | |
| 1282 | operands[1])) | |
| 9db1d521 | 1283 | { |
| 4023fb28 UW |
1284 | operands[2] = operand_subword (operands[0], 0, 0, DFmode); |
| 1285 | operands[3] = operand_subword (operands[0], 1, 0, DFmode); | |
| 1286 | operands[4] = operand_subword (operands[1], 0, 0, DFmode); | |
| 1287 | operands[5] = operand_subword (operands[1], 1, 0, DFmode); | |
| 9db1d521 | 1288 | } |
| 4023fb28 UW |
1289 | else |
| 1290 | { | |
| 1291 | operands[2] = operand_subword (operands[0], 1, 0, DFmode); | |
| 1292 | operands[3] = operand_subword (operands[0], 0, 0, DFmode); | |
| 1293 | operands[4] = operand_subword (operands[1], 1, 0, DFmode); | |
| 1294 | operands[5] = operand_subword (operands[1], 0, 0, DFmode); | |
| 1295 | } | |
| 1296 | }") | |
| 9db1d521 | 1297 | |
| 4023fb28 UW |
1298 | (define_split |
| 1299 | [(set (match_operand:DF 0 "register_operand" "") | |
| 1300 | (match_operand:DF 1 "memory_operand" ""))] | |
| 1301 | "!TARGET_64BIT && reload_completed | |
| 1302 | && !fp_operand (operands[0], VOIDmode) | |
| 1303 | && !fp_operand (operands[1], VOIDmode) | |
| 1304 | && !s_operand (operands[1], VOIDmode)" | |
| 1305 | [(set (match_dup 2) (match_dup 3)) | |
| 1306 | (set (match_dup 0) (mem:DI (match_dup 2)))] | |
| 1307 | "operands[2] = operand_subword (operands[0], 1, 0, DFmode); | |
| 1308 | operands[3] = XEXP (operands[1], 0);") | |
| 9db1d521 HP |
1309 | |
| 1310 | ; | |
| 1311 | ; movsf instruction pattern(s). | |
| 1312 | ; | |
| 1313 | ||
| 1314 | (define_expand "movsf" | |
| 1315 | [(set (match_operand:SF 0 "nonimmediate_operand" "") | |
| 1316 | (match_operand:SF 1 "general_operand" ""))] | |
| 1317 | "" | |
| 1318 | " | |
| 1319 | { | |
| 4023fb28 UW |
1320 | /* During and after reload, we need to force constants |
| 1321 | to the literal pool ourselves, if necessary. */ | |
| 1322 | if ((reload_in_progress || reload_completed) | |
| 1323 | && CONSTANT_P (operands[1])) | |
| 1324 | operands[1] = force_const_mem (SFmode, operands[1]); | |
| 9db1d521 HP |
1325 | }") |
| 1326 | ||
| 4023fb28 UW |
1327 | (define_insn "*movsf_ss" |
| 1328 | [(set (match_operand:SF 0 "s_operand" "=Qo") | |
| 1329 | (match_operand:SF 1 "s_imm_operand" "Qo"))] | |
| 1330 | "" | |
| 1331 | "mvc\\t%O0(4,%R0),%1" | |
| 1332 | [(set_attr "op_type" "SS") | |
| 1333 | (set_attr "atype" "mem")]) | |
| 9db1d521 | 1334 | |
| 4023fb28 UW |
1335 | (define_insn "*movsf" |
| 1336 | [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,m,d,d,m") | |
| 1337 | (match_operand:SF 1 "general_operand" "f,m,f,d,m,d"))] | |
| 1338 | "" | |
| 9db1d521 HP |
1339 | "@ |
| 1340 | ler\\t%0,%1 | |
| 1341 | le\\t%0,%1 | |
| 1342 | ste\\t%1,%0 | |
| 9db1d521 HP |
1343 | lr\\t%0,%1 |
| 1344 | l\\t%0,%1 | |
| 4023fb28 UW |
1345 | st\\t%1,%0" |
| 1346 | [(set_attr "op_type" "RR,RX,RX,RR,RX,RX") | |
| 1347 | (set_attr "atype" "reg,mem,mem,reg,mem,mem")]) | |
| 1348 | ||
| 9db1d521 HP |
1349 | ; |
| 1350 | ; load_multiple pattern(s). | |
| 1351 | ; | |
| 1352 | ||
| 1353 | (define_expand "load_multiple" | |
| 1354 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
| 1355 | (match_operand 1 "" "")) | |
| 1356 | (use (match_operand 2 "" ""))])] | |
| 1357 | "" | |
| 1358 | " | |
| 1359 | { | |
| 1360 | int regno; | |
| 1361 | int count; | |
| 1362 | rtx from; | |
| 4023fb28 | 1363 | int i, off; |
| 9db1d521 HP |
1364 | |
| 1365 | /* Support only loading a constant number of fixed-point registers from | |
| 1366 | memory and only bother with this if more than two */ | |
| 1367 | if (GET_CODE (operands[2]) != CONST_INT | |
| 4023fb28 | 1368 | || INTVAL (operands[2]) < 2 |
| 9db1d521 HP |
1369 | || INTVAL (operands[2]) > 16 |
| 1370 | || GET_CODE (operands[1]) != MEM | |
| 1371 | || GET_CODE (operands[0]) != REG | |
| 1372 | || REGNO (operands[0]) >= 16) | |
| 1373 | FAIL; | |
| 1374 | ||
| 1375 | count = INTVAL (operands[2]); | |
| 1376 | regno = REGNO (operands[0]); | |
| 1377 | ||
| 1378 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
| 4023fb28 UW |
1379 | if (no_new_pseudos) |
| 1380 | { | |
| 1381 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
| 1382 | { | |
| 1383 | from = XEXP (operands[1], 0); | |
| 1384 | off = 0; | |
| 1385 | } | |
| 1386 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
| 1387 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
| 1388 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
| 1389 | { | |
| 1390 | from = XEXP (XEXP (operands[1], 0), 0); | |
| 1391 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
| 1392 | } | |
| 1393 | else | |
| 1394 | FAIL; | |
| 1395 | ||
| 1396 | if (from == frame_pointer_rtx || from == arg_pointer_rtx) | |
| 1397 | FAIL; | |
| 1398 | } | |
| 1399 | else | |
| 1400 | { | |
| 1401 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
| 1402 | off = 0; | |
| 1403 | } | |
| 9db1d521 HP |
1404 | |
| 1405 | for (i = 0; i < count; i++) | |
| 1406 | XVECEXP (operands[3], 0, i) | |
| 1407 | = gen_rtx_SET (VOIDmode, gen_rtx_REG (Pmode, regno + i), | |
| 1408 | change_address (operands[1], Pmode, | |
| 4023fb28 UW |
1409 | plus_constant (from, |
| 1410 | off + i * UNITS_PER_WORD))); | |
| 9db1d521 HP |
1411 | }") |
| 1412 | ||
| 1413 | (define_insn "*load_multiple_di" | |
| 1414 | [(match_parallel 0 "load_multiple_operation" | |
| 1415 | [(set (match_operand:DI 1 "register_operand" "=r") | |
| 1416 | (match_operand:DI 2 "s_operand" "oQ"))])] | |
| 1417 | "" | |
| 1418 | "* | |
| 1419 | { | |
| 1420 | int words = XVECLEN (operands[0], 0); | |
| 1421 | ||
| 1422 | if (XVECLEN (operands[0], 0) == 1) | |
| 1423 | return \"lg\\t%1,0(%2)\"; | |
| 1424 | ||
| 1425 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); | |
| 1426 | return \"lmg\\t%1,%0,%2\"; | |
| 1427 | }" | |
| 1428 | [(set_attr "op_type" "RXE") | |
| 4023fb28 UW |
1429 | (set_attr "atype" "mem") |
| 1430 | (set_attr "type" "lm")]) | |
| 9db1d521 HP |
1431 | |
| 1432 | (define_insn "*load_multiple_si" | |
| 1433 | [(match_parallel 0 "load_multiple_operation" | |
| 1434 | [(set (match_operand:SI 1 "register_operand" "=r") | |
| 1435 | (match_operand:SI 2 "s_operand" "oQ"))])] | |
| 1436 | "" | |
| 1437 | "* | |
| 1438 | { | |
| 1439 | int words = XVECLEN (operands[0], 0); | |
| 1440 | ||
| 1441 | if (XVECLEN (operands[0], 0) == 1) | |
| 1442 | return \"l\\t%1,0(%2)\"; | |
| 1443 | ||
| 1444 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); | |
| 1445 | return \"lm\\t%1,%0,%2\"; | |
| 1446 | }" | |
| 1447 | [(set_attr "op_type" "RXE") | |
| 4023fb28 UW |
1448 | (set_attr "atype" "mem") |
| 1449 | (set_attr "type" "lm")]) | |
| 9db1d521 HP |
1450 | |
| 1451 | ; | |
| 1452 | ; store multiple pattern(s). | |
| 1453 | ; | |
| 1454 | ||
| 1455 | (define_expand "store_multiple" | |
| 1456 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
| 1457 | (match_operand 1 "" "")) | |
| 1458 | (use (match_operand 2 "" ""))])] | |
| 1459 | "" | |
| 1460 | " | |
| 1461 | { | |
| 1462 | int regno; | |
| 1463 | int count; | |
| 1464 | rtx to; | |
| 4023fb28 | 1465 | int i, off; |
| 9db1d521 HP |
1466 | |
| 1467 | /* Support only storing a constant number of fixed-point registers to | |
| 1468 | memory and only bother with this if more than two. */ | |
| 1469 | if (GET_CODE (operands[2]) != CONST_INT | |
| 4023fb28 | 1470 | || INTVAL (operands[2]) < 2 |
| 9db1d521 HP |
1471 | || INTVAL (operands[2]) > 16 |
| 1472 | || GET_CODE (operands[0]) != MEM | |
| 1473 | || GET_CODE (operands[1]) != REG | |
| 1474 | || REGNO (operands[1]) >= 16) | |
| 1475 | FAIL; | |
| 1476 | ||
| 1477 | count = INTVAL (operands[2]); | |
| 1478 | regno = REGNO (operands[1]); | |
| 1479 | ||
| 1480 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
| 4023fb28 UW |
1481 | |
| 1482 | if (no_new_pseudos) | |
| 1483 | { | |
| 1484 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
| 1485 | { | |
| 1486 | to = XEXP (operands[0], 0); | |
| 1487 | off = 0; | |
| 1488 | } | |
| 1489 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
| 1490 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
| 1491 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
| 1492 | { | |
| 1493 | to = XEXP (XEXP (operands[0], 0), 0); | |
| 1494 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
| 1495 | } | |
| 1496 | else | |
| 1497 | FAIL; | |
| 1498 | ||
| 1499 | if (to == frame_pointer_rtx || to == arg_pointer_rtx) | |
| 1500 | FAIL; | |
| 1501 | } | |
| 1502 | else | |
| 1503 | { | |
| 1504 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
| 1505 | off = 0; | |
| 1506 | } | |
| 9db1d521 HP |
1507 | |
| 1508 | for (i = 0; i < count; i++) | |
| 1509 | XVECEXP (operands[3], 0, i) | |
| 1510 | = gen_rtx_SET (VOIDmode, | |
| 1511 | change_address (operands[0], Pmode, | |
| 4023fb28 UW |
1512 | plus_constant (to, |
| 1513 | off + i * UNITS_PER_WORD)), | |
| 9db1d521 HP |
1514 | gen_rtx_REG (Pmode, regno + i)); |
| 1515 | }") | |
| 1516 | ||
| 1517 | (define_insn "*store_multiple_di" | |
| 1518 | [(match_parallel 0 "store_multiple_operation" | |
| 1519 | [(set (match_operand:DI 1 "s_operand" "=oQ") | |
| 1520 | (match_operand:DI 2 "register_operand" "r"))])] | |
| 1521 | "" | |
| 1522 | "* | |
| 1523 | { | |
| 1524 | int words = XVECLEN (operands[0], 0); | |
| 1525 | ||
| 1526 | if (XVECLEN (operands[0], 0) == 1) | |
| 1527 | return \"stg\\t%1,0(%2)\"; | |
| 1528 | ||
| 1529 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); | |
| 1530 | return \"stmg\\t%2,%0,%1\"; | |
| 1531 | }" | |
| 1532 | [(set_attr "op_type" "RXE") | |
| 1533 | (set_attr "atype" "mem") | |
| 4023fb28 | 1534 | (set_attr "type" "stm")]) |
| 9db1d521 HP |
1535 | |
| 1536 | ||
| 1537 | (define_insn "*store_multiple_si" | |
| 1538 | [(match_parallel 0 "store_multiple_operation" | |
| 1539 | [(set (match_operand:SI 1 "s_operand" "=oQ") | |
| 1540 | (match_operand:SI 2 "register_operand" "r"))])] | |
| 1541 | "" | |
| 1542 | "* | |
| 1543 | { | |
| 1544 | int words = XVECLEN (operands[0], 0); | |
| 1545 | ||
| 1546 | if (XVECLEN (operands[0], 0) == 1) | |
| 1547 | return \"st\\t%1,0(%2)\"; | |
| 1548 | ||
| 1549 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); | |
| 1550 | return \"stm\\t%2,%0,%1\"; | |
| 1551 | }" | |
| 1552 | [(set_attr "op_type" "RXE") | |
| 1553 | (set_attr "atype" "mem") | |
| 4023fb28 | 1554 | (set_attr "type" "stm")]) |
| 9db1d521 HP |
1555 | |
| 1556 | ;; | |
| 1557 | ;; String instructions. | |
| 1558 | ;; | |
| 1559 | ||
| 1560 | ; | |
| 1561 | ; movstrdi instruction pattern(s). | |
| 1562 | ; | |
| 1563 | ||
| 1564 | (define_expand "movstrdi" | |
| 1565 | [(set (match_operand:BLK 0 "general_operand" "") | |
| 1566 | (match_operand:BLK 1 "general_operand" "")) | |
| 1567 | (use (match_operand:DI 2 "general_operand" "")) | |
| 1568 | (match_operand 3 "" "")] | |
| 1569 | "TARGET_64BIT" | |
| 1570 | " | |
| 1571 | { | |
| 1572 | rtx addr0, addr1; | |
| 1573 | ||
| 1574 | addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX); | |
| 1575 | addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX); | |
| 1576 | ||
| 1577 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256) | |
| 1578 | { | |
| 1579 | operands[0] = change_address (operands[0], VOIDmode, addr0); | |
| 1580 | operands[1] = change_address (operands[1], VOIDmode, addr1); | |
| 1581 | operands[2] = GEN_INT (INTVAL (operands[2]) - 1); | |
| 1582 | ||
| 1583 | emit_insn (gen_movstrsico (operands[0], operands[1], operands[2])); | |
| 1584 | DONE; | |
| 1585 | } | |
| 1586 | else | |
| 1587 | { | |
| 1588 | if (TARGET_MVCLE) | |
| 1589 | { | |
| 1590 | /* implementation suggested by Richard Henderson <rth@cygnus.com> */ | |
| 1591 | rtx reg0 = gen_reg_rtx (TImode); | |
| 1592 | rtx reg1 = gen_reg_rtx (TImode); | |
| 1593 | rtx len = operands[2]; | |
| 1594 | ||
| 1595 | if (! CONSTANT_P (len)) | |
| 1596 | len = force_reg (DImode, len); | |
| 1597 | ||
| 1598 | /* Load up the address+length pairs. */ | |
| 1599 | ||
| 4023fb28 UW |
1600 | emit_move_insn (gen_highpart (DImode, reg0), addr0); |
| 1601 | emit_move_insn (gen_lowpart (DImode, reg0), len); | |
| 9db1d521 | 1602 | |
| 4023fb28 UW |
1603 | emit_move_insn (gen_highpart (DImode, reg1), addr1); |
| 1604 | emit_move_insn (gen_lowpart (DImode, reg1), len); | |
| 9db1d521 HP |
1605 | |
| 1606 | /* MOVE */ | |
| 4023fb28 | 1607 | emit_insn (gen_movstrdi_64 (reg0, reg1, reg0, reg1)); |
| 9db1d521 HP |
1608 | DONE; |
| 1609 | } | |
| 1610 | else | |
| 1611 | { | |
| 1612 | rtx label = gen_label_rtx (); | |
| 1613 | rtx reg0, reg1, len; | |
| 1614 | ||
| 1615 | reg0 = gen_reg_rtx (DImode); | |
| 1616 | reg1 = gen_reg_rtx (DImode); | |
| 1617 | len = gen_reg_rtx (DImode); | |
| 1618 | ||
| 1619 | emit_move_insn (len, operands[2]); | |
| 1620 | emit_insn (gen_cmpdi (len, const0_rtx)); | |
| 1621 | emit_jump_insn (gen_beq (label)); | |
| 1622 | emit_move_insn (reg0, addr0); | |
| 1623 | emit_move_insn (reg1, addr1); | |
| 1624 | emit_insn (gen_adddi3 (len, len, constm1_rtx)); | |
| 4023fb28 | 1625 | emit_insn (gen_movstrdix_64 (reg0, reg1, reg0, reg1, len)); |
| 9db1d521 HP |
1626 | emit_label (label); |
| 1627 | DONE; | |
| 1628 | } | |
| 1629 | } | |
| 1630 | }") | |
| 1631 | ||
| 1632 | ; | |
| 1633 | ; movstrsi instruction pattern(s). | |
| 1634 | ; | |
| 1635 | ||
| 1636 | (define_expand "movstrsi" | |
| 1637 | [(set (match_operand:BLK 0 "general_operand" "") | |
| 1638 | (match_operand:BLK 1 "general_operand" "")) | |
| 1639 | (use (match_operand:SI 2 "general_operand" "")) | |
| 1640 | (match_operand 3 "" "")] | |
| 1641 | "" | |
| 1642 | " | |
| 1643 | { | |
| 1644 | rtx addr0 = force_operand (XEXP (operands[0], 0), NULL_RTX); | |
| 1645 | rtx addr1 = force_operand (XEXP (operands[1], 0), NULL_RTX); | |
| 1646 | ||
| 1647 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 256) | |
| 1648 | { | |
| 1649 | operands[0] = change_address (operands[0], VOIDmode, addr0); | |
| 1650 | operands[1] = change_address (operands[1], VOIDmode, addr1); | |
| 1651 | operands[2] = GEN_INT (INTVAL (operands[2]) - 1); | |
| 1652 | ||
| 1653 | emit_insn (gen_movstrsico (operands[0], operands[1], operands[2])); | |
| 1654 | DONE; | |
| 1655 | } | |
| 1656 | else | |
| 1657 | { | |
| 1658 | if (TARGET_64BIT) | |
| 1659 | FAIL; | |
| 1660 | ||
| 1661 | if (TARGET_MVCLE) | |
| 1662 | { | |
| 1663 | /* implementation suggested by Richard Henderson <rth@cygnus.com> */ | |
| 1664 | rtx reg0 = gen_reg_rtx (DImode); | |
| 1665 | rtx reg1 = gen_reg_rtx (DImode); | |
| 1666 | rtx len = operands[2]; | |
| 1667 | ||
| 1668 | ||
| 1669 | if (! CONSTANT_P (len)) | |
| 1670 | len = force_reg (SImode, len); | |
| 1671 | ||
| 1672 | /* Load up the address+length pairs. */ | |
| 1673 | ||
| 4023fb28 UW |
1674 | emit_move_insn (gen_highpart (SImode, reg0), addr0); |
| 1675 | emit_move_insn (gen_lowpart (SImode, reg0), len); | |
| 9db1d521 | 1676 | |
| 4023fb28 UW |
1677 | emit_move_insn (gen_highpart (SImode, reg1), addr1); |
| 1678 | emit_move_insn (gen_lowpart (SImode, reg1), len); | |
| 9db1d521 HP |
1679 | |
| 1680 | /* MOVE */ | |
| 4023fb28 | 1681 | emit_insn (gen_movstrsi_31 (reg0, reg1, reg0, reg1)); |
| 9db1d521 HP |
1682 | DONE; |
| 1683 | } | |
| 1684 | else | |
| 1685 | { | |
| 1686 | rtx label = gen_label_rtx (); | |
| 1687 | rtx reg0, reg1, len; | |
| 1688 | ||
| 1689 | reg0 = gen_reg_rtx (SImode); | |
| 1690 | reg1 = gen_reg_rtx (SImode); | |
| 1691 | len = gen_reg_rtx (SImode); | |
| 1692 | ||
| 1693 | emit_move_insn (len, operands[2]); | |
| 1694 | emit_insn (gen_cmpsi (len, const0_rtx)); | |
| 1695 | emit_jump_insn (gen_beq (label)); | |
| 1696 | emit_move_insn (reg0, addr0); | |
| 1697 | emit_move_insn (reg1, addr1); | |
| 1698 | emit_insn (gen_addsi3 (len, len, constm1_rtx)); | |
| 4023fb28 | 1699 | emit_insn (gen_movstrsix_31 (reg0, reg1, reg0, reg1, len)); |
| 9db1d521 HP |
1700 | emit_label (label); |
| 1701 | DONE; | |
| 1702 | } | |
| 1703 | } | |
| 1704 | }") | |
| 1705 | ||
| 1706 | ; Move a block that is less than 256 bytes in length. | |
| 1707 | ||
| 1708 | (define_insn "movstrsico" | |
| 1709 | [(set (match_operand:BLK 0 "s_operand" "=oQ") | |
| 1710 | (match_operand:BLK 1 "s_operand" "oQ")) | |
| 1711 | (use (match_operand 2 "const_int_operand" "I"))] | |
| 1712 | "((unsigned) INTVAL (operands[2]) < 256)" | |
| 1713 | "mvc\\t%O0(%c2+1,%R0),%1" | |
| 1714 | [(set_attr "op_type" "SS") | |
| 1715 | (set_attr "atype" "mem")]) | |
| 1716 | ||
| 1717 | ; Move a block that is more than 256 bytes in lenght or length in register | |
| 1718 | ||
| 1719 | (define_insn "movstrdix_64" | |
| 9f37ccb1 UW |
1720 | [(use (match_operand:DI 4 "register_operand" "a")) |
| 1721 | (set (match_operand:DI 0 "register_operand" "=a") | |
| 1722 | (plus:DI (match_operand:DI 2 "register_operand" "0") | |
| 1723 | (and:DI (match_dup 4) (const_int -256)))) | |
| 1724 | (set (match_operand:DI 1 "register_operand" "=a") | |
| 1725 | (plus:DI (match_operand:DI 3 "register_operand" "1") | |
| 1726 | (and:DI (match_dup 4) (const_int -256)))) | |
| 1727 | (set (mem:BLK (match_dup 2)) | |
| 1728 | (mem:BLK (match_dup 3))) | |
| 4023fb28 | 1729 | (clobber (match_scratch:DI 5 "=&a")) |
| 9db1d521 HP |
1730 | (clobber (reg:CC 33))] |
| 1731 | "" | |
| 1732 | "* | |
| 1733 | { | |
| 1734 | rtx xop[4]; | |
| 1735 | xop[0] = gen_label_rtx (); | |
| 1736 | xop[1] = gen_label_rtx (); | |
| 1737 | xop[2] = gen_label_rtx (); | |
| 4023fb28 UW |
1738 | xop[3] = operands[5]; |
| 1739 | output_asm_insn (\"srag\\t%5,%4,8\", operands); | |
| 1740 | output_asm_insn (\"jz\\t%l1\", xop); | |
| 9db1d521 HP |
1741 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", |
| 1742 | CODE_LABEL_NUMBER (xop[0])); | |
| 4023fb28 UW |
1743 | output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands); |
| 1744 | output_asm_insn (\"la\\t%0,256(%0)\", operands); | |
| 1745 | output_asm_insn (\"la\\t%1,256(%1)\", operands); | |
| 1746 | output_asm_insn (\"brct\\t%3,%l0\", xop); | |
| 9db1d521 HP |
1747 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", |
| 1748 | CODE_LABEL_NUMBER (xop[1])); | |
| 4023fb28 UW |
1749 | output_asm_insn (\"bras\\t%3,%l2\", xop); |
| 1750 | output_asm_insn (\"mvc\\t0(1,%0),0(%1)\", operands); | |
| 9db1d521 HP |
1751 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", |
| 1752 | CODE_LABEL_NUMBER (xop[2])); | |
| 4023fb28 | 1753 | return \"ex\\t%4,0(%5)\"; |
| 9db1d521 HP |
1754 | }" |
| 1755 | [(set_attr "op_type" "NN") | |
| 1756 | (set_attr "atype" "mem") | |
| 1757 | (set_attr "length" "44")]) | |
| 1758 | ||
| 1759 | (define_insn "movstrsix_31" | |
| 9f37ccb1 UW |
1760 | [(use (match_operand:SI 4 "register_operand" "a")) |
| 1761 | (set (match_operand:SI 0 "register_operand" "=a") | |
| 1762 | (plus:SI (match_operand:SI 2 "register_operand" "0") | |
| 1763 | (and:SI (match_dup 4) (const_int -256)))) | |
| 1764 | (set (match_operand:SI 1 "register_operand" "=a") | |
| 1765 | (plus:SI (match_operand:SI 3 "register_operand" "1") | |
| 1766 | (and:SI (match_dup 4) (const_int -256)))) | |
| 1767 | (set (mem:BLK (match_dup 2)) | |
| 1768 | (mem:BLK (match_dup 3))) | |
| 4023fb28 | 1769 | (clobber (match_scratch:SI 5 "=&a")) |
| 9db1d521 HP |
1770 | (clobber (reg:CC 33))] |
| 1771 | "" | |
| 1772 | "* | |
| 1773 | { | |
| 1774 | rtx xop[4]; | |
| 1775 | xop[0] = gen_label_rtx (); | |
| 1776 | xop[1] = gen_label_rtx (); | |
| 1777 | xop[2] = gen_label_rtx (); | |
| 4023fb28 UW |
1778 | xop[3] = operands[5]; |
| 1779 | output_asm_insn (\"lr\\t%5,%4\", operands); | |
| 1780 | output_asm_insn (\"sra\\t%5,8\", operands); | |
| 1781 | output_asm_insn (\"jz\\t%l1\", xop); | |
| 9db1d521 HP |
1782 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", |
| 1783 | CODE_LABEL_NUMBER (xop[0])); | |
| 4023fb28 UW |
1784 | output_asm_insn (\"mvc\\t0(256,%0),0(%1)\", operands); |
| 1785 | output_asm_insn (\"la\\t%0,256(%0)\", operands); | |
| 1786 | output_asm_insn (\"la\\t%1,256(%1)\", operands); | |
| 1787 | output_asm_insn (\"brct\\t%3,%l0\", xop); | |
| 9db1d521 HP |
1788 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", |
| 1789 | CODE_LABEL_NUMBER (xop[1])); | |
| 4023fb28 UW |
1790 | output_asm_insn (\"bras\\t%3,%l2\", xop); |
| 1791 | output_asm_insn (\"mvc\\t0(1,%0),0(%1)\", operands); | |
| 9db1d521 HP |
1792 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", |
| 1793 | CODE_LABEL_NUMBER (xop[2])); | |
| 4023fb28 | 1794 | return \"ex\\t%4,0(%5)\"; |
| 9db1d521 HP |
1795 | }" |
| 1796 | [(set_attr "op_type" "NN") | |
| 1797 | (set_attr "length" "42") | |
| 1798 | (set_attr "atype" "mem")]) | |
| 1799 | ||
| 1800 | ; Move a block that is larger than 255 bytes in length. | |
| 1801 | ||
| 1802 | (define_insn "movstrdi_64" | |
| 9f37ccb1 UW |
1803 | [(set (match_operand:TI 0 "register_operand" "=d") |
| 1804 | (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0") | |
| 1805 | (lshiftrt:TI (match_dup 2) (const_int 64))) | |
| 1806 | (const_int 64))) | |
| 1807 | (set (match_operand:TI 1 "register_operand" "=d") | |
| 1808 | (ashift:TI (plus:TI (match_operand:TI 3 "register_operand" "1") | |
| 1809 | (lshiftrt:TI (match_dup 3) (const_int 64))) | |
| 1810 | (const_int 64))) | |
| 1811 | (set (mem:BLK (subreg:DI (match_dup 2) 0)) | |
| 1812 | (mem:BLK (subreg:DI (match_dup 3) 0))) | |
| 9db1d521 | 1813 | (clobber (reg:CC 33))] |
| 9f37ccb1 | 1814 | "TARGET_64BIT" |
| 9db1d521 HP |
1815 | "mvcle\\t%0,%1,0\;jo\\t.-4" |
| 1816 | [(set_attr "op_type" "NN") | |
| 1817 | (set_attr "atype" "mem") | |
| 1818 | (set_attr "length" "8")]) | |
| 1819 | ||
| 1820 | (define_insn "movstrsi_31" | |
| 9f37ccb1 UW |
1821 | [(set (match_operand:DI 0 "register_operand" "=d") |
| 1822 | (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0") | |
| 1823 | (lshiftrt:DI (match_dup 2) (const_int 32))) | |
| 1824 | (const_int 32))) | |
| 1825 | (set (match_operand:DI 1 "register_operand" "=d") | |
| 1826 | (ashift:DI (plus:DI (match_operand:DI 3 "register_operand" "1") | |
| 1827 | (lshiftrt:DI (match_dup 3) (const_int 32))) | |
| 1828 | (const_int 32))) | |
| 1829 | (set (mem:BLK (subreg:SI (match_dup 2) 0)) | |
| 1830 | (mem:BLK (subreg:SI (match_dup 3) 0))) | |
| 9db1d521 | 1831 | (clobber (reg:CC 33))] |
| 9f37ccb1 | 1832 | "!TARGET_64BIT" |
| 9db1d521 HP |
1833 | "mvcle\\t%0,%1,0\;jo\\t.-4" |
| 1834 | [(set_attr "op_type" "NN") | |
| 1835 | (set_attr "atype" "mem") | |
| 1836 | (set_attr "length" "8")]) | |
| 1837 | ||
| 1838 | ; | |
| 1839 | ; clrstrdi instruction pattern(s). | |
| 1840 | ; | |
| 1841 | ||
| 1842 | (define_expand "clrstrdi" | |
| 1843 | [(set (match_operand:BLK 0 "general_operand" "") | |
| 1844 | (const_int 0)) | |
| 1845 | (use (match_operand:DI 1 "general_operand" "")) | |
| 1846 | (match_operand 2 "" "")] | |
| 1847 | "TARGET_64BIT" | |
| 1848 | " | |
| 1849 | { | |
| 1850 | rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX); | |
| 1851 | ||
| 1852 | operands[0] = change_address (operands[0], VOIDmode, addr); | |
| 1853 | ||
| 1854 | if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256) | |
| 1855 | { | |
| 1856 | emit_insn (gen_clrstrsico (operands[0], operands[1])); | |
| 1857 | DONE; | |
| 1858 | } | |
| 1859 | else | |
| 1860 | { | |
| 1861 | rtx reg0 = gen_reg_rtx (TImode); | |
| 1862 | rtx reg1 = gen_reg_rtx (TImode); | |
| 1863 | rtx len = operands[1]; | |
| 1864 | ||
| 1865 | if (! CONSTANT_P (len)) | |
| 1866 | len = force_reg (DImode, len); | |
| 1867 | ||
| 1868 | /* Load up the address+length pairs. */ | |
| 1869 | ||
| 4023fb28 UW |
1870 | emit_move_insn (gen_highpart (DImode, reg0), addr); |
| 1871 | emit_move_insn (gen_lowpart (DImode, reg0), len); | |
| 9db1d521 | 1872 | |
| 4023fb28 | 1873 | emit_move_insn (gen_lowpart (DImode, reg1), const0_rtx); |
| 9db1d521 HP |
1874 | |
| 1875 | /* Clear! */ | |
| 9f37ccb1 | 1876 | emit_insn (gen_clrstrsi_64 (reg0, reg1, reg0)); |
| 9db1d521 HP |
1877 | DONE; |
| 1878 | } | |
| 1879 | }") | |
| 1880 | ||
| 1881 | ; | |
| 1882 | ; clrstrsi instruction pattern(s). | |
| 1883 | ; | |
| 1884 | ||
| 1885 | (define_expand "clrstrsi" | |
| 1886 | [(set (match_operand:BLK 0 "general_operand" "") | |
| 1887 | (const_int 0)) | |
| 1888 | (use (match_operand:SI 1 "general_operand" "")) | |
| 1889 | (match_operand 2 "" "")] | |
| 1890 | "!TARGET_64BIT" | |
| 1891 | " | |
| 1892 | { | |
| 1893 | rtx addr = force_operand (XEXP (operands[0], 0), NULL_RTX); | |
| 1894 | ||
| 1895 | operands[0] = change_address (operands[0], VOIDmode, addr); | |
| 1896 | ||
| 1897 | if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 256) | |
| 1898 | { | |
| 1899 | emit_insn (gen_clrstrsico (operands[0], operands[1])); | |
| 1900 | DONE; | |
| 1901 | } | |
| 1902 | else | |
| 1903 | { | |
| 1904 | rtx reg0 = gen_reg_rtx (DImode); | |
| 1905 | rtx reg1 = gen_reg_rtx (DImode); | |
| 1906 | rtx len = operands[1]; | |
| 1907 | ||
| 1908 | if (! CONSTANT_P (len)) | |
| 1909 | len = force_reg (SImode, len); | |
| 1910 | ||
| 1911 | /* Load up the address+length pairs. */ | |
| 1912 | ||
| 4023fb28 UW |
1913 | emit_move_insn (gen_highpart (SImode, reg0), addr); |
| 1914 | emit_move_insn (gen_lowpart (SImode, reg0), len); | |
| 9db1d521 | 1915 | |
| 4023fb28 | 1916 | emit_move_insn (gen_lowpart (SImode, reg1), const0_rtx); |
| 9db1d521 HP |
1917 | |
| 1918 | /* CLear! */ | |
| 9f37ccb1 | 1919 | emit_insn (gen_clrstrsi_31 (reg0, reg1, reg0)); |
| 9db1d521 HP |
1920 | DONE; |
| 1921 | } | |
| 1922 | }") | |
| 1923 | ||
| 1924 | ; Clear memory with length less than 256 bytes | |
| 1925 | ||
| 1926 | (define_insn "clrstrsico" | |
| 1927 | [(set (match_operand:BLK 0 "s_operand" "=Qo") | |
| 1928 | (const_int 0)) | |
| 1929 | (use (match_operand 1 "immediate_operand" "I")) | |
| 1930 | (clobber (reg:CC 33))] | |
| 1931 | "" | |
| 1932 | "xc\\t%O0(%1,%R0),%0" | |
| 1933 | [(set_attr "op_type" "RS") | |
| 4023fb28 | 1934 | (set_attr "type" "cs") |
| 9db1d521 HP |
1935 | (set_attr "atype" "mem")]) |
| 1936 | ||
| 1937 | ; Clear memory with length greater 256 bytes or lenght not constant | |
| 1938 | ||
| 1939 | (define_insn "clrstrsi_64" | |
| 9f37ccb1 UW |
1940 | [(set (match_operand:TI 0 "register_operand" "=d") |
| 1941 | (ashift:TI (plus:TI (match_operand:TI 2 "register_operand" "0") | |
| 1942 | (lshiftrt:TI (match_dup 2) (const_int 64))) | |
| 1943 | (const_int 64))) | |
| 1944 | (set (mem:BLK (subreg:DI (match_dup 2) 0)) | |
| 9db1d521 | 1945 | (const_int 0)) |
| 9f37ccb1 | 1946 | (use (match_operand:TI 1 "register_operand" "d")) |
| 9db1d521 HP |
1947 | (clobber (reg:CC 33))] |
| 1948 | "TARGET_64BIT" | |
| 1949 | "mvcle\\t%0,%1,0\;jo\\t.-4" | |
| 1950 | [(set_attr "op_type" "NN") | |
| 1951 | (set_attr "atype" "mem") | |
| 4023fb28 | 1952 | (set_attr "type" "vs") |
| 9db1d521 HP |
1953 | (set_attr "length" "8")]) |
| 1954 | ||
| 1955 | (define_insn "clrstrsi_31" | |
| 9f37ccb1 UW |
1956 | [(set (match_operand:DI 0 "register_operand" "=d") |
| 1957 | (ashift:DI (plus:DI (match_operand:DI 2 "register_operand" "0") | |
| 1958 | (lshiftrt:DI (match_dup 2) (const_int 32))) | |
| 1959 | (const_int 32))) | |
| 1960 | (set (mem:BLK (subreg:SI (match_dup 2) 0)) | |
| 9db1d521 | 1961 | (const_int 0)) |
| 9f37ccb1 | 1962 | (use (match_operand:DI 1 "register_operand" "d")) |
| 9db1d521 HP |
1963 | (clobber (reg:CC 33))] |
| 1964 | "!TARGET_64BIT" | |
| 1965 | "mvcle\\t%0,%1,0\;jo\\t.-4" | |
| 1966 | [(set_attr "op_type" "NN") | |
| 1967 | (set_attr "atype" "mem") | |
| 4023fb28 | 1968 | (set_attr "type" "vs") |
| 9db1d521 HP |
1969 | (set_attr "length" "8")]) |
| 1970 | ||
| 1971 | ; | |
| 1972 | ; cmpstrdi instruction pattern(s). | |
| 1973 | ; | |
| 1974 | ||
| 1975 | (define_expand "cmpstrdi" | |
| 1976 | [(set (match_operand:DI 0 "register_operand" "") | |
| 1977 | (compare:DI (match_operand:BLK 1 "s_operand" "") | |
| 1978 | (match_operand:BLK 2 "s_operand" "") ) ) | |
| 1979 | (use (match_operand:DI 3 "general_operand" "")) | |
| 1980 | (use (match_operand:DI 4 "" ""))] | |
| 1981 | "TARGET_64BIT" | |
| 1982 | " | |
| 1983 | { | |
| 1984 | rtx addr0, addr1; | |
| 1985 | ||
| 1986 | /* for pre/post increment */ | |
| 1987 | operands[1] = protect_from_queue (operands[1], 0); | |
| 1988 | operands[2] = protect_from_queue (operands[2], 0); | |
| 1989 | operands[3] = protect_from_queue (operands[3], 0); | |
| 1990 | ||
| 1991 | addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX); | |
| 1992 | addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX); | |
| 1993 | ||
| 1994 | if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256) | |
| 1995 | { | |
| 1996 | if (INTVAL (operands[3]) == 0) { | |
| 1997 | emit_move_insn (operands[0], operands[3]); | |
| 1998 | DONE; | |
| 1999 | } | |
| 2000 | ||
| 2001 | operands[1] = change_address (operands[1], VOIDmode, addr0); | |
| 2002 | operands[2] = change_address (operands[2], VOIDmode, addr1); | |
| 2003 | ||
| 2004 | emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3])); | |
| 2005 | emit_insn (gen_cmpint_di (operands[0])); | |
| 2006 | DONE; | |
| 2007 | } | |
| 2008 | else | |
| 2009 | { | |
| 2010 | /* implementation suggested by Richard Henderson <rth@cygnus.com> */ | |
| 2011 | rtx reg0 = gen_reg_rtx (TImode); | |
| 2012 | rtx reg1 = gen_reg_rtx (TImode); | |
| 2013 | rtx len = operands[3]; | |
| 2014 | ||
| 2015 | if (! CONSTANT_P (len)) | |
| 2016 | len = force_reg (DImode, len); | |
| 2017 | ||
| 2018 | /* Load up the address+length pairs. */ | |
| 4023fb28 UW |
2019 | emit_move_insn (gen_highpart (DImode, reg0), addr0); |
| 2020 | emit_move_insn (gen_lowpart (DImode, reg0), len); | |
| 9db1d521 | 2021 | |
| 4023fb28 UW |
2022 | emit_move_insn (gen_highpart (DImode, reg1), addr1); |
| 2023 | emit_move_insn (gen_lowpart (DImode, reg1), len); | |
| 9db1d521 HP |
2024 | |
| 2025 | /* Compare! */ | |
| 4023fb28 | 2026 | emit_insn (gen_cmpstr_64 (reg0, reg1, reg0, reg1)); |
| 9db1d521 HP |
2027 | emit_insn (gen_cmpint_di (operands[0])); |
| 2028 | DONE; | |
| 2029 | } | |
| 2030 | }") | |
| 2031 | ||
| 2032 | ; | |
| 2033 | ; cmpstrsi instruction pattern(s). | |
| 2034 | ; | |
| 2035 | ||
| 2036 | (define_expand "cmpstrsi" | |
| 2037 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2038 | (compare:SI (match_operand:BLK 1 "s_operand" "") | |
| 2039 | (match_operand:BLK 2 "s_operand" "") ) ) | |
| 2040 | (use (match_operand:SI 3 "general_operand" "")) | |
| 2041 | (use (match_operand:SI 4 "" ""))] | |
| 2042 | "" | |
| 2043 | " | |
| 2044 | { | |
| 2045 | rtx addr0, addr1; | |
| 2046 | ||
| 2047 | /* for pre/post increment */ | |
| 2048 | operands[1] = protect_from_queue (operands[1], 0); | |
| 2049 | operands[2] = protect_from_queue (operands[2], 0); | |
| 2050 | operands[3] = protect_from_queue (operands[3], 0); | |
| 2051 | ||
| 2052 | addr0 = force_operand (XEXP (operands[1], 0), NULL_RTX); | |
| 2053 | addr1 = force_operand (XEXP (operands[2], 0), NULL_RTX); | |
| 2054 | ||
| 2055 | if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) < 256) | |
| 2056 | { | |
| 2057 | if (INTVAL (operands[3]) == 0) { | |
| 2058 | emit_move_insn (operands[0], operands[3]); | |
| 2059 | DONE; | |
| 2060 | } | |
| 2061 | ||
| 2062 | operands[1] = change_address (operands[1], VOIDmode, addr0); | |
| 2063 | operands[2] = change_address (operands[2], VOIDmode, addr1); | |
| 2064 | ||
| 2065 | emit_insn (gen_cmpstr_const (operands[1], operands[2], operands[3])); | |
| 2066 | emit_insn (gen_cmpint_si (operands[0])); | |
| 2067 | DONE; | |
| 2068 | } | |
| 2069 | else | |
| 2070 | { | |
| 2071 | /* implementation suggested by Richard Henderson <rth@cygnus.com> */ | |
| 2072 | rtx reg0, reg1; | |
| 2073 | rtx len = operands[3]; | |
| 2074 | ||
| 2075 | if (TARGET_64BIT) | |
| 2076 | { | |
| 2077 | reg0 = gen_reg_rtx (TImode); | |
| 2078 | reg1 = gen_reg_rtx (TImode); | |
| 2079 | } | |
| 2080 | else | |
| 2081 | { | |
| 2082 | reg0 = gen_reg_rtx (DImode); | |
| 2083 | reg1 = gen_reg_rtx (DImode); | |
| 2084 | } | |
| 2085 | ||
| 2086 | if (! CONSTANT_P (len)) | |
| 2087 | len = force_reg (Pmode, len); | |
| 2088 | ||
| 2089 | /* Load up the address+length pairs. */ | |
| 4023fb28 UW |
2090 | emit_move_insn (gen_highpart (Pmode, reg0), addr0); |
| 2091 | emit_move_insn (gen_lowpart (Pmode, reg0), len); | |
| 9db1d521 | 2092 | |
| 4023fb28 UW |
2093 | emit_move_insn (gen_highpart (Pmode, reg1), addr1); |
| 2094 | emit_move_insn (gen_lowpart (Pmode, reg1), len); | |
| 9db1d521 HP |
2095 | |
| 2096 | /* Compare! */ | |
| 2097 | if (TARGET_64BIT) | |
| 4023fb28 | 2098 | emit_insn (gen_cmpstr_64 (reg0, reg1, reg0, reg1)); |
| 9db1d521 | 2099 | else |
| 4023fb28 | 2100 | emit_insn (gen_cmpstr_31 (reg0, reg1, reg0, reg1)); |
| 9db1d521 HP |
2101 | |
| 2102 | emit_insn (gen_cmpint_si (operands[0])); | |
| 2103 | DONE; | |
| 2104 | } | |
| 2105 | }") | |
| 2106 | ||
| 2107 | ; Compare a block that is less than 256 bytes in length. | |
| 2108 | ||
| 2109 | (define_insn "cmpstr_const" | |
| ba956982 UW |
2110 | [(set (reg:CCS 33) |
| 2111 | (compare:CCS (match_operand:BLK 0 "s_operand" "oQ") | |
| 9db1d521 HP |
2112 | (match_operand:BLK 1 "s_operand" "oQ"))) |
| 2113 | (use (match_operand 2 "immediate_operand" "I"))] | |
| 2114 | "(unsigned) INTVAL (operands[2]) < 256" | |
| 2115 | "clc\\t%O0(%c2,%R0),%1" | |
| 2116 | [(set_attr "op_type" "SS") | |
| 2117 | (set_attr "atype" "mem") | |
| 4023fb28 | 2118 | (set_attr "type" "cs")]) |
| 9db1d521 HP |
2119 | |
| 2120 | ; Compare a block that is larger than 255 bytes in length. | |
| 2121 | ||
| 2122 | (define_insn "cmpstr_64" | |
| 4023fb28 UW |
2123 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
| 2124 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
| 2125 | (set (reg:CCS 33) | |
| 2126 | (compare:CCS (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0)) | |
| 2127 | (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))] | |
| 9db1d521 HP |
2128 | "TARGET_64BIT" |
| 2129 | "clcl\\t%0,%1" | |
| 2130 | [(set_attr "op_type" "RR") | |
| 2131 | (set_attr "atype" "mem") | |
| 4023fb28 | 2132 | (set_attr "type" "vs")]) |
| 9db1d521 HP |
2133 | |
| 2134 | (define_insn "cmpstr_31" | |
| 4023fb28 UW |
2135 | [(clobber (match_operand:DI 0 "register_operand" "=d")) |
| 2136 | (clobber (match_operand:DI 1 "register_operand" "=d")) | |
| 2137 | (set (reg:CCS 33) | |
| 2138 | (compare:CCS (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0)) | |
| 2139 | (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))] | |
| 9db1d521 HP |
2140 | "!TARGET_64BIT" |
| 2141 | "clcl\\t%0,%1" | |
| 2142 | [(set_attr "op_type" "RR") | |
| 2143 | (set_attr "atype" "mem") | |
| 4023fb28 | 2144 | (set_attr "type" "vs")]) |
| 9db1d521 HP |
2145 | |
| 2146 | ; Convert condition code to integer in range (-1, 0, 1) | |
| 2147 | ||
| 2148 | (define_insn "cmpint_si" | |
| 2149 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| ba956982 | 2150 | (compare:SI (reg:CCS 33) (const_int 0)))] |
| 9db1d521 HP |
2151 | "" |
| 2152 | "* | |
| 2153 | { | |
| 2154 | output_asm_insn (\"lhi\\t%0,1\", operands); | |
| 2155 | output_asm_insn (\"jh\\t.+12\", operands); | |
| 2156 | output_asm_insn (\"jl\\t.+6\", operands); | |
| 2157 | output_asm_insn (\"sr\\t%0,%0\", operands); | |
| 2158 | return \"lcr\\t%0,%0\"; | |
| 2159 | }" | |
| 2160 | [(set_attr "op_type" "NN") | |
| 2161 | (set_attr "length" "16") | |
| 2162 | (set_attr "atype" "reg") | |
| f2d3c02a | 2163 | (set_attr "type" "other")]) |
| 9db1d521 HP |
2164 | |
| 2165 | (define_insn "cmpint_di" | |
| 2166 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| ba956982 | 2167 | (compare:DI (reg:CCS 33) (const_int 0)))] |
| 9db1d521 HP |
2168 | "TARGET_64BIT" |
| 2169 | "* | |
| 2170 | { | |
| 2171 | output_asm_insn (\"lghi\\t%0,1\", operands); | |
| 2172 | output_asm_insn (\"jh\\t.+12\", operands); | |
| 2173 | output_asm_insn (\"jl\\t.+6\", operands); | |
| 2174 | output_asm_insn (\"sgr\\t%0,%0\", operands); | |
| 2175 | return \"lcgr\\t%0,%0\"; | |
| 2176 | }" | |
| 2177 | [(set_attr "op_type" "NN") | |
| 2178 | (set_attr "length" "22") | |
| 2179 | (set_attr "atype" "reg") | |
| f2d3c02a | 2180 | (set_attr "type" "other")]) |
| 9db1d521 | 2181 | |
| 4023fb28 | 2182 | |
| 9db1d521 HP |
2183 | ;; |
| 2184 | ;;- Conversion instructions. | |
| 2185 | ;; | |
| 2186 | ||
| 4023fb28 UW |
2187 | (define_insn "*sethighqisi" |
| 2188 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2189 | (unspec:SI [(match_operand:QI 1 "s_operand" "Qo")] 10)) | |
| 2190 | (clobber (reg:CC 33))] | |
| 2191 | "" | |
| 2192 | "icm\\t%0,8,%1" | |
| 2193 | [(set_attr "op_type" "RS") | |
| 2194 | (set_attr "atype" "mem")]) | |
| 2195 | ||
| 2196 | (define_insn "*sethighhisi" | |
| 2197 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2198 | (unspec:SI [(match_operand:HI 1 "s_operand" "Qo")] 10)) | |
| 2199 | (clobber (reg:CC 33))] | |
| 2200 | "" | |
| 2201 | "icm\\t%0,12,%1" | |
| 2202 | [(set_attr "op_type" "RS") | |
| 2203 | (set_attr "atype" "mem")]) | |
| 2204 | ||
| 2205 | (define_insn "*sethighqidi_64" | |
| 2206 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 2207 | (unspec:DI [(match_operand:QI 1 "s_operand" "Qo")] 10)) | |
| 2208 | (clobber (reg:CC 33))] | |
| 2209 | "TARGET_64BIT" | |
| 2210 | "icmh\\t%0,8,%1" | |
| 2211 | [(set_attr "op_type" "RSE") | |
| 2212 | (set_attr "atype" "mem")]) | |
| 2213 | ||
| 2214 | (define_insn "*sethighqidi_31" | |
| 2215 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 2216 | (unspec:DI [(match_operand:QI 1 "s_operand" "Qo")] 10)) | |
| 2217 | (clobber (reg:CC 33))] | |
| 2218 | "!TARGET_64BIT" | |
| 2219 | "icm\\t%0,8,%1" | |
| 2220 | [(set_attr "op_type" "RS") | |
| 2221 | (set_attr "atype" "mem")]) | |
| 2222 | ||
| 2223 | (define_split | |
| 2224 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2225 | (zero_extract:SI (match_operand:QI 1 "s_operand" "") | |
| 2226 | (match_operand 2 "const_int_operand" "") | |
| 2227 | (const_int 0)))] | |
| 2228 | "!TARGET_64BIT && !reload_completed | |
| 2229 | && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8" | |
| 2230 | [(parallel | |
| 2231 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10)) | |
| 2232 | (clobber (reg:CC 33))]) | |
| 2233 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] | |
| 2234 | " | |
| 2235 | { | |
| 2236 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
| 2237 | operands[1] = change_address (operands[1], QImode, 0); | |
| 2238 | }") | |
| 2239 | ||
| 2240 | (define_split | |
| 2241 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2242 | (zero_extract:SI (match_operand:QI 1 "s_operand" "") | |
| 2243 | (match_operand 2 "const_int_operand" "") | |
| 2244 | (const_int 0)))] | |
| 2245 | "!TARGET_64BIT && !reload_completed | |
| 2246 | && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16" | |
| 2247 | [(parallel | |
| 2248 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10)) | |
| 2249 | (clobber (reg:CC 33))]) | |
| 2250 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))] | |
| 2251 | " | |
| 2252 | { | |
| 2253 | operands[2] = GEN_INT (32 - INTVAL (operands[2])); | |
| 2254 | operands[1] = change_address (operands[1], HImode, 0); | |
| 2255 | }") | |
| 2256 | ||
| 9db1d521 HP |
2257 | ; |
| 2258 | ; extendsidi2 instruction pattern(s). | |
| 2259 | ; | |
| 2260 | ||
| 4023fb28 UW |
2261 | (define_expand "extendsidi2" |
| 2262 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2263 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
| 2264 | "" | |
| 2265 | " | |
| 2266 | { | |
| 2267 | if (!TARGET_64BIT) | |
| 2268 | { | |
| 9f37ccb1 UW |
2269 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
| 2270 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); | |
| 2271 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
| 2272 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
| 4023fb28 UW |
2273 | DONE; |
| 2274 | } | |
| 2275 | } | |
| 2276 | ") | |
| 2277 | ||
| 2278 | (define_insn "*extendsidi2" | |
| 9db1d521 HP |
2279 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
| 2280 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
| 2281 | "TARGET_64BIT" | |
| 2282 | "@ | |
| 2283 | lgfr\\t%0,%1 | |
| 2284 | lgf\\t%0,%1" | |
| 2285 | [(set_attr "op_type" "RRE,RXE") | |
| f2d3c02a | 2286 | (set_attr "atype" "reg,mem")]) |
| 9db1d521 | 2287 | |
| 9db1d521 HP |
2288 | ; |
| 2289 | ; extendhidi2 instruction pattern(s). | |
| 2290 | ; | |
| 2291 | ||
| 4023fb28 UW |
2292 | (define_expand "extendhidi2" |
| 2293 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2294 | (sign_extend:DI (match_operand:HI 1 "register_operand" "")))] | |
| 2295 | "" | |
| 2296 | " | |
| 2297 | { | |
| 2298 | if (!TARGET_64BIT) | |
| 2299 | { | |
| 2300 | rtx tmp = gen_reg_rtx (SImode); | |
| 2301 | emit_insn (gen_extendhisi2 (tmp, operands[1])); | |
| 2302 | emit_insn (gen_extendsidi2 (operands[0], tmp)); | |
| 2303 | DONE; | |
| 2304 | } | |
| 2305 | else | |
| 2306 | { | |
| 2307 | operands[1] = gen_lowpart (DImode, operands[1]); | |
| 2308 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); | |
| 2309 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48))); | |
| 2310 | DONE; | |
| 2311 | } | |
| 2312 | } | |
| 2313 | ") | |
| 2314 | ||
| 2315 | (define_insn "*extendhidi2" | |
| 9db1d521 | 2316 | [(set (match_operand:DI 0 "register_operand" "=d") |
| 4023fb28 | 2317 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))] |
| 9db1d521 | 2318 | "TARGET_64BIT" |
| 4023fb28 UW |
2319 | "lgh\\t%0,%1" |
| 2320 | [(set_attr "op_type" "RXE") | |
| 2321 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
2322 | |
| 2323 | ; | |
| 2324 | ; extendqidi2 instruction pattern(s). | |
| 2325 | ; | |
| 2326 | ||
| 4023fb28 UW |
2327 | (define_expand "extendqidi2" |
| 2328 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2329 | (sign_extend:DI (match_operand:QI 1 "register_operand" "")))] | |
| 2330 | "" | |
| 2331 | " | |
| 2332 | { | |
| 2333 | if (!TARGET_64BIT) | |
| 2334 | { | |
| 2335 | rtx tmp = gen_reg_rtx (SImode); | |
| 2336 | emit_insn (gen_extendqisi2 (tmp, operands[1])); | |
| 2337 | emit_insn (gen_extendsidi2 (operands[0], tmp)); | |
| 2338 | DONE; | |
| 2339 | } | |
| 2340 | else | |
| 2341 | { | |
| 2342 | operands[1] = gen_lowpart (DImode, operands[1]); | |
| 2343 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); | |
| 2344 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56))); | |
| 2345 | DONE; | |
| 2346 | } | |
| 2347 | } | |
| 2348 | ") | |
| 2349 | ||
| 2350 | (define_split | |
| 2351 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2352 | (sign_extend:DI (match_operand:QI 1 "s_operand" "")))] | |
| 2353 | "TARGET_64BIT && !reload_completed" | |
| 2354 | [(parallel | |
| 2355 | [(set (match_dup 0) (unspec:DI [(match_dup 1)] 10)) | |
| 2356 | (clobber (reg:CC 33))]) | |
| 2357 | (parallel | |
| 2358 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56))) | |
| 2359 | (clobber (reg:CC 33))])] | |
| 2360 | "") | |
| 9db1d521 HP |
2361 | |
| 2362 | ; | |
| 2363 | ; extendhisi2 instruction pattern(s). | |
| 2364 | ; | |
| 2365 | ||
| 4023fb28 UW |
2366 | (define_expand "extendhisi2" |
| 2367 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2368 | (sign_extend:SI (match_operand:HI 1 "register_operand" "")))] | |
| 9db1d521 | 2369 | "" |
| 4023fb28 UW |
2370 | " |
| 2371 | { | |
| 2372 | operands[1] = gen_lowpart (SImode, operands[1]); | |
| 2373 | emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16))); | |
| 2374 | emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16))); | |
| 2375 | DONE; | |
| 2376 | } | |
| 2377 | ") | |
| 9db1d521 | 2378 | |
| 4023fb28 UW |
2379 | (define_insn "*extendhisi2" |
| 2380 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2381 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))] | |
| 2382 | "" | |
| 2383 | "lh\\t%0,%1" | |
| 2384 | [(set_attr "op_type" "RX") | |
| 2385 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
2386 | |
| 2387 | ; | |
| 2388 | ; extendqisi2 instruction pattern(s). | |
| 2389 | ; | |
| 2390 | ||
| 4023fb28 UW |
2391 | (define_expand "extendqisi2" |
| 2392 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2393 | (sign_extend:SI (match_operand:QI 1 "register_operand" "")))] | |
| 9db1d521 | 2394 | "" |
| 4023fb28 UW |
2395 | " |
| 2396 | { | |
| 2397 | operands[1] = gen_lowpart (SImode, operands[1]); | |
| 2398 | emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24))); | |
| 2399 | emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24))); | |
| 2400 | DONE; | |
| 2401 | } | |
| 2402 | ") | |
| 9db1d521 | 2403 | |
| 4023fb28 UW |
2404 | (define_split |
| 2405 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2406 | (sign_extend:SI (match_operand:QI 1 "s_operand" "")))] | |
| 2407 | "!reload_completed" | |
| 2408 | [(parallel | |
| 2409 | [(set (match_dup 0) (unspec:SI [(match_dup 1)] 10)) | |
| 2410 | (clobber (reg:CC 33))]) | |
| 2411 | (parallel | |
| 2412 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24))) | |
| 2413 | (clobber (reg:CC 33))])] | |
| 2414 | "") | |
| 9db1d521 HP |
2415 | |
| 2416 | ; | |
| 2417 | ; extendqihi2 instruction pattern(s). | |
| 2418 | ; | |
| 2419 | ||
| 9db1d521 HP |
2420 | |
| 2421 | ; | |
| 2422 | ; zero_extendsidi2 instruction pattern(s). | |
| 2423 | ; | |
| 2424 | ||
| 4023fb28 UW |
2425 | (define_expand "zero_extendsidi2" |
| 2426 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2427 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
| 2428 | "" | |
| 2429 | " | |
| 2430 | { | |
| 2431 | if (!TARGET_64BIT) | |
| 2432 | { | |
| 9f37ccb1 UW |
2433 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); |
| 2434 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); | |
| 2435 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
| 4023fb28 UW |
2436 | DONE; |
| 2437 | } | |
| 2438 | } | |
| 2439 | ") | |
| 2440 | ||
| 2441 | (define_insn "*zero_extendsidi2" | |
| 9db1d521 HP |
2442 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
| 2443 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))] | |
| 2444 | "TARGET_64BIT" | |
| 2445 | "@ | |
| 2446 | llgfr\\t%0,%1 | |
| 2447 | llgf\\t%0,%1" | |
| 2448 | [(set_attr "op_type" "RRE,RXE") | |
| f2d3c02a | 2449 | (set_attr "atype" "reg,mem")]) |
| 9db1d521 | 2450 | |
| 9db1d521 HP |
2451 | ; |
| 2452 | ; zero_extendhidi2 instruction pattern(s). | |
| 2453 | ; | |
| 2454 | ||
| 4023fb28 UW |
2455 | (define_expand "zero_extendhidi2" |
| 2456 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2457 | (zero_extend:DI (match_operand:HI 1 "register_operand" "")))] | |
| 2458 | "" | |
| 2459 | " | |
| 2460 | { | |
| 2461 | if (!TARGET_64BIT) | |
| 2462 | { | |
| 2463 | rtx tmp = gen_reg_rtx (SImode); | |
| 2464 | emit_insn (gen_zero_extendhisi2 (tmp, operands[1])); | |
| 2465 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
| 2466 | DONE; | |
| 2467 | } | |
| 2468 | else | |
| 2469 | { | |
| 2470 | operands[1] = gen_lowpart (DImode, operands[1]); | |
| 2471 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48))); | |
| 2472 | emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48))); | |
| 2473 | DONE; | |
| 2474 | } | |
| 2475 | } | |
| 2476 | ") | |
| 9db1d521 | 2477 | |
| 4023fb28 UW |
2478 | (define_insn "*zero_extendhidi2" |
| 2479 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 2480 | (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))] | |
| 9db1d521 | 2481 | "TARGET_64BIT" |
| 4023fb28 UW |
2482 | "llgh\\t%0,%1" |
| 2483 | [(set_attr "op_type" "RXE") | |
| 2484 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
2485 | |
| 2486 | ; | |
| 4023fb28 | 2487 | ; zero_extendqidi2 instruction pattern(s) |
| 9db1d521 HP |
2488 | ; |
| 2489 | ||
| 4023fb28 UW |
2490 | (define_expand "zero_extendqidi2" |
| 2491 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2492 | (zero_extend:DI (match_operand:QI 1 "register_operand" "")))] | |
| 9db1d521 HP |
2493 | "" |
| 2494 | " | |
| 2495 | { | |
| 2496 | if (!TARGET_64BIT) | |
| 2497 | { | |
| 4023fb28 UW |
2498 | rtx tmp = gen_reg_rtx (SImode); |
| 2499 | emit_insn (gen_zero_extendqisi2 (tmp, operands[1])); | |
| 2500 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
| 9db1d521 HP |
2501 | DONE; |
| 2502 | } | |
| 4023fb28 UW |
2503 | else |
| 2504 | { | |
| 2505 | operands[1] = gen_lowpart (DImode, operands[1]); | |
| 2506 | emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56))); | |
| 2507 | emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56))); | |
| 2508 | DONE; | |
| 2509 | } | |
| 2510 | } | |
| 2511 | ") | |
| 9db1d521 | 2512 | |
| 4023fb28 UW |
2513 | (define_insn "*zero_extendqidi2" |
| 2514 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 2515 | (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))] | |
| 9db1d521 | 2516 | "TARGET_64BIT" |
| 4023fb28 UW |
2517 | "llgc\\t%0,%1" |
| 2518 | [(set_attr "op_type" "RXE") | |
| 2519 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
2520 | |
| 2521 | ; | |
| 4023fb28 | 2522 | ; zero_extendhisi2 instruction pattern(s). |
| 9db1d521 HP |
2523 | ; |
| 2524 | ||
| 4023fb28 UW |
2525 | (define_expand "zero_extendhisi2" |
| 2526 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2527 | (zero_extend:SI (match_operand:HI 1 "register_operand" "")))] | |
| 9db1d521 | 2528 | "" |
| 4023fb28 UW |
2529 | " |
| 2530 | { | |
| 2531 | operands[1] = gen_lowpart (SImode, operands[1]); | |
| 2532 | emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff))); | |
| 2533 | DONE; | |
| 2534 | } | |
| 2535 | ") | |
| 9db1d521 | 2536 | |
| 4023fb28 | 2537 | (define_insn "*zero_extendhisi2_64" |
| 9db1d521 | 2538 | [(set (match_operand:SI 0 "register_operand" "=d") |
| 4023fb28 | 2539 | (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] |
| 9db1d521 | 2540 | "TARGET_64BIT" |
| 4023fb28 UW |
2541 | "llgh\\t%0,%1" |
| 2542 | [(set_attr "op_type" "RXE") | |
| 2543 | (set_attr "atype" "mem")]) | |
| 2544 | ||
| 2545 | ; | |
| 2546 | ; zero_extendqisi2 instruction pattern(s). | |
| 2547 | ; | |
| 9db1d521 HP |
2548 | |
| 2549 | (define_expand "zero_extendqisi2" | |
| 2550 | [(set (match_operand:SI 0 "register_operand" "") | |
| 4023fb28 | 2551 | (zero_extend:SI (match_operand:QI 1 "register_operand" "")))] |
| 9db1d521 HP |
2552 | "" |
| 2553 | " | |
| 2554 | { | |
| 4023fb28 UW |
2555 | operands[1] = gen_lowpart (SImode, operands[1]); |
| 2556 | emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff))); | |
| 2557 | DONE; | |
| 2558 | } | |
| 2559 | ") | |
| 9db1d521 | 2560 | |
| 4023fb28 UW |
2561 | (define_insn "*zero_extendqisi2_64" |
| 2562 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2563 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] | |
| 2564 | "TARGET_64BIT" | |
| 2565 | "llgc\\t%0,%1" | |
| 2566 | [(set_attr "op_type" "RXE") | |
| 2567 | (set_attr "atype" "mem")]) | |
| 2568 | ||
| 9db1d521 HP |
2569 | ; |
| 2570 | ; zero_extendqihi2 instruction pattern(s). | |
| 2571 | ; | |
| 2572 | ||
| 9db1d521 HP |
2573 | (define_expand "zero_extendqihi2" |
| 2574 | [(set (match_operand:HI 0 "register_operand" "") | |
| 4023fb28 | 2575 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
| 9db1d521 | 2576 | "TARGET_64BIT" |
| 9db1d521 HP |
2577 | " |
| 2578 | { | |
| 4023fb28 UW |
2579 | operands[1] = gen_lowpart (HImode, operands[1]); |
| 2580 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
| 2581 | DONE; | |
| 2582 | } | |
| 2583 | ") | |
| 9db1d521 | 2584 | |
| 4023fb28 | 2585 | (define_insn "*zero_extendqihi2_64" |
| 9db1d521 | 2586 | [(set (match_operand:HI 0 "register_operand" "=d") |
| 4023fb28 | 2587 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "m"))) |
| 9db1d521 | 2588 | (clobber (reg:CC 33))] |
| 9db1d521 | 2589 | "TARGET_64BIT" |
| 4023fb28 UW |
2590 | "llgc\\t%0,%1" |
| 2591 | [(set_attr "op_type" "RXE") | |
| 2592 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
2593 | |
| 2594 | ; | |
| 2595 | ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s). | |
| 2596 | ; | |
| 2597 | ||
| 2598 | (define_expand "fixuns_truncdfdi2" | |
| 2599 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2600 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))] | |
| 2601 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 2602 | " | |
| 2603 | { | |
| 2604 | rtx label1 = gen_label_rtx (); | |
| 2605 | rtx label2 = gen_label_rtx (); | |
| 2606 | rtx temp = gen_reg_rtx (DFmode); | |
| 2607 | operands[1] = force_reg (DFmode, operands[1]); | |
| 2608 | ||
| 4023fb28 UW |
2609 | emit_insn (gen_cmpdf (operands[1], |
| 2610 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
| 2611 | REAL_VALUE_ATOF (\"9223372036854775808.0\", DFmode), DFmode))); | |
| 9db1d521 | 2612 | emit_jump_insn (gen_blt (label1)); |
| 4023fb28 UW |
2613 | emit_insn (gen_subdf3 (temp, operands[1], |
| 2614 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
| 2615 | REAL_VALUE_ATOF (\"18446744073709551616.0\", DFmode), DFmode))); | |
| 9db1d521 | 2616 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7))); |
| f314b9b1 | 2617 | emit_jump (label2); |
| 9db1d521 HP |
2618 | |
| 2619 | emit_label (label1); | |
| 2620 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
| 2621 | emit_label (label2); | |
| 2622 | DONE; | |
| 2623 | }") | |
| 2624 | ||
| 2625 | (define_expand "fix_truncdfdi2" | |
| 2626 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2627 | (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
| 2628 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 2629 | " | |
| 2630 | { | |
| 2631 | operands[1] = force_reg (DFmode, operands[1]); | |
| 2632 | emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
| 2633 | DONE; | |
| 2634 | }") | |
| 2635 | ||
| 2636 | (define_insn "fix_truncdfdi2_ieee" | |
| 2637 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 2638 | (fix:DI (match_operand:DF 1 "register_operand" "f"))) | |
| 2639 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1) | |
| 2640 | (clobber (reg:CC 33))] | |
| 2641 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 2642 | "cgdbr\\t%0,%h2,%1" | |
| 2643 | [(set_attr "op_type" "RRE") | |
| 4023fb28 | 2644 | (set_attr "type" "other")]) |
| 9db1d521 HP |
2645 | |
| 2646 | ; | |
| 2647 | ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s). | |
| 2648 | ; | |
| 2649 | ||
| 2650 | (define_expand "fixuns_truncdfsi2" | |
| 2651 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2652 | (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))] | |
| 2653 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 2654 | " | |
| 2655 | { | |
| 2656 | rtx label1 = gen_label_rtx (); | |
| 2657 | rtx label2 = gen_label_rtx (); | |
| 2658 | rtx temp = gen_reg_rtx (DFmode); | |
| 2659 | ||
| 2660 | operands[1] = force_reg (DFmode,operands[1]); | |
| 4023fb28 UW |
2661 | emit_insn (gen_cmpdf (operands[1], |
| 2662 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
| 2663 | REAL_VALUE_ATOF (\"2147483648.0\", DFmode), DFmode))); | |
| 9db1d521 | 2664 | emit_jump_insn (gen_blt (label1)); |
| 4023fb28 UW |
2665 | emit_insn (gen_subdf3 (temp, operands[1], |
| 2666 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
| 2667 | REAL_VALUE_ATOF (\"4294967296.0\", DFmode), DFmode))); | |
| 9db1d521 | 2668 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7))); |
| f314b9b1 | 2669 | emit_jump (label2); |
| 9db1d521 HP |
2670 | |
| 2671 | emit_label (label1); | |
| 2672 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
| 2673 | emit_label (label2); | |
| 2674 | DONE; | |
| 2675 | }") | |
| 2676 | ||
| 2677 | (define_expand "fix_truncdfsi2" | |
| 2678 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2679 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))] | |
| 2680 | "TARGET_HARD_FLOAT" | |
| 2681 | " | |
| 2682 | { | |
| 2683 | if (TARGET_IBM_FLOAT) | |
| 2684 | { | |
| 2685 | /* This is the algorithm from POP chapter A.5.7.2. */ | |
| 2686 | ||
| 2687 | rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD); | |
| 4023fb28 UW |
2688 | rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000); |
| 2689 | rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000); | |
| 9db1d521 HP |
2690 | |
| 2691 | operands[1] = force_reg (DFmode, operands[1]); | |
| 2692 | emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1], | |
| 2693 | two31r, two32, temp)); | |
| 2694 | } | |
| 2695 | else | |
| 2696 | { | |
| 2697 | operands[1] = force_reg (DFmode, operands[1]); | |
| 2698 | emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
| 2699 | } | |
| 2700 | ||
| 2701 | DONE; | |
| 2702 | }") | |
| 2703 | ||
| 2704 | (define_insn "fix_truncdfsi2_ieee" | |
| 2705 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2706 | (fix:SI (match_operand:DF 1 "register_operand" "f"))) | |
| 2707 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1) | |
| 2708 | (clobber (reg:CC 33))] | |
| 2709 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 2710 | "cfdbr\\t%0,%h2,%1" | |
| 2711 | [(set_attr "op_type" "RRE") | |
| 4023fb28 | 2712 | (set_attr "type" "other" )]) |
| 9db1d521 HP |
2713 | |
| 2714 | (define_insn "fix_truncdfsi2_ibm" | |
| 2715 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2716 | (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f"))) | |
| 4023fb28 UW |
2717 | (use (match_operand:DI 2 "immediate_operand" "m")) |
| 2718 | (use (match_operand:DI 3 "immediate_operand" "m")) | |
| 9db1d521 HP |
2719 | (use (match_operand:BLK 4 "memory_operand" "m")) |
| 2720 | (clobber (reg:CC 33))] | |
| 2721 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 2722 | "* | |
| 2723 | { | |
| 2724 | output_asm_insn (\"sd\\t%1,%2\", operands); | |
| 2725 | output_asm_insn (\"aw\\t%1,%3\", operands); | |
| 2726 | output_asm_insn (\"std\\t%1,%4\", operands); | |
| 2727 | output_asm_insn (\"xi\\t%N4,128\", operands); | |
| 2728 | return \"l\\t%0,%N4\"; | |
| 2729 | }" | |
| 2730 | [(set_attr "op_type" "NN") | |
| 4023fb28 | 2731 | (set_attr "type" "other") |
| 9db1d521 HP |
2732 | (set_attr "length" "20")]) |
| 2733 | ||
| 2734 | ; | |
| 2735 | ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s). | |
| 2736 | ; | |
| 2737 | ||
| 2738 | (define_expand "fixuns_truncsfdi2" | |
| 2739 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2740 | (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))] | |
| 2741 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 2742 | " | |
| 2743 | { | |
| 2744 | rtx label1 = gen_label_rtx (); | |
| 2745 | rtx label2 = gen_label_rtx (); | |
| 2746 | rtx temp = gen_reg_rtx (SFmode); | |
| 2747 | ||
| 2748 | operands[1] = force_reg (SFmode, operands[1]); | |
| 4023fb28 UW |
2749 | emit_insn (gen_cmpsf (operands[1], |
| 2750 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
| 2751 | REAL_VALUE_ATOF (\"9223372036854775808.0\", SFmode), SFmode))); | |
| 9db1d521 HP |
2752 | emit_jump_insn (gen_blt (label1)); |
| 2753 | ||
| 4023fb28 UW |
2754 | emit_insn (gen_subsf3 (temp, operands[1], |
| 2755 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
| 2756 | REAL_VALUE_ATOF (\"18446744073709551616.0\", SFmode), SFmode))); | |
| 9db1d521 | 2757 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7))); |
| f314b9b1 | 2758 | emit_jump (label2); |
| 9db1d521 HP |
2759 | |
| 2760 | emit_label (label1); | |
| 2761 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
| 2762 | emit_label (label2); | |
| 2763 | DONE; | |
| 2764 | }") | |
| 2765 | ||
| 2766 | (define_expand "fix_truncsfdi2" | |
| 2767 | [(set (match_operand:DI 0 "register_operand" "") | |
| 2768 | (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
| 2769 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 2770 | " | |
| 2771 | { | |
| 2772 | operands[1] = force_reg (SFmode, operands[1]); | |
| 2773 | emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5))); | |
| 2774 | DONE; | |
| 2775 | }") | |
| 2776 | ||
| 2777 | (define_insn "fix_truncsfdi2_ieee" | |
| 2778 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 2779 | (fix:DI (match_operand:SF 1 "register_operand" "f"))) | |
| 2780 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] 1) | |
| 2781 | (clobber (reg:CC 33))] | |
| 2782 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 2783 | "cgebr\\t%0,%h2,%1" | |
| 2784 | [(set_attr "op_type" "RRE") | |
| 4023fb28 | 2785 | (set_attr "type" "other")]) |
| 9db1d521 HP |
2786 | |
| 2787 | ; | |
| 2788 | ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s). | |
| 2789 | ; | |
| 2790 | ||
| 2791 | (define_expand "fixuns_truncsfsi2" | |
| 2792 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2793 | (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))] | |
| 2794 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 2795 | " | |
| 2796 | { | |
| 2797 | rtx label1 = gen_label_rtx (); | |
| 2798 | rtx label2 = gen_label_rtx (); | |
| 2799 | rtx temp = gen_reg_rtx (SFmode); | |
| 2800 | ||
| 2801 | operands[1] = force_reg (SFmode, operands[1]); | |
| 4023fb28 UW |
2802 | emit_insn (gen_cmpsf (operands[1], |
| 2803 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
| 2804 | REAL_VALUE_ATOF (\"2147483648.0\", SFmode), SFmode))); | |
| 9db1d521 | 2805 | emit_jump_insn (gen_blt (label1)); |
| 4023fb28 UW |
2806 | emit_insn (gen_subsf3 (temp, operands[1], |
| 2807 | CONST_DOUBLE_FROM_REAL_VALUE ( | |
| 2808 | REAL_VALUE_ATOF (\"4294967296.0\", SFmode), SFmode))); | |
| 9db1d521 | 2809 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7))); |
| f314b9b1 | 2810 | emit_jump (label2); |
| 9db1d521 HP |
2811 | |
| 2812 | emit_label (label1); | |
| 2813 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
| 2814 | emit_label (label2); | |
| 2815 | DONE; | |
| 2816 | }") | |
| 2817 | ||
| 2818 | (define_expand "fix_truncsfsi2" | |
| 2819 | [(set (match_operand:SI 0 "register_operand" "") | |
| 2820 | (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))] | |
| 2821 | "TARGET_HARD_FLOAT" | |
| 2822 | " | |
| 2823 | { | |
| 2824 | if (TARGET_IBM_FLOAT) | |
| 2825 | { | |
| 2826 | /* Convert to DFmode and then use the POP algorithm. */ | |
| 2827 | rtx temp = gen_reg_rtx (DFmode); | |
| 2828 | emit_insn (gen_extendsfdf2 (temp, operands[1])); | |
| 2829 | emit_insn (gen_fix_truncdfsi2 (operands[0], temp)); | |
| 2830 | } | |
| 2831 | else | |
| 2832 | { | |
| 2833 | operands[1] = force_reg (SFmode, operands[1]); | |
| 2834 | emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5))); | |
| 2835 | } | |
| 2836 | ||
| 2837 | DONE; | |
| 2838 | }") | |
| 2839 | ||
| 2840 | (define_insn "fix_truncsfsi2_ieee" | |
| 2841 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 2842 | (fix:SI (match_operand:SF 1 "register_operand" "f"))) | |
| 2843 | (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] 1) | |
| 2844 | (clobber (reg:CC 33))] | |
| 2845 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 2846 | "cfebr\\t%0,%h2,%1" | |
| 2847 | [(set_attr "op_type" "RRE") | |
| 4023fb28 | 2848 | (set_attr "type" "other")]) |
| 9db1d521 HP |
2849 | |
| 2850 | ; | |
| 2851 | ; floatdidf2 instruction pattern(s). | |
| 2852 | ; | |
| 2853 | ||
| 2854 | (define_insn "floatdidf2" | |
| 2855 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 4023fb28 UW |
2856 | (float:DF (match_operand:DI 1 "register_operand" "d"))) |
| 2857 | (clobber (reg:CC 33))] | |
| 9db1d521 HP |
2858 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| 2859 | "cdgbr\\t%0,%1" | |
| 2860 | [(set_attr "op_type" "RRE") | |
| 4023fb28 | 2861 | (set_attr "type" "other" )]) |
| 9db1d521 HP |
2862 | |
| 2863 | ; | |
| 2864 | ; floatdisf2 instruction pattern(s). | |
| 2865 | ; | |
| 2866 | ||
| 2867 | (define_insn "floatdisf2" | |
| 2868 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 4023fb28 UW |
2869 | (float:SF (match_operand:DI 1 "register_operand" "d"))) |
| 2870 | (clobber (reg:CC 33))] | |
| 9db1d521 HP |
2871 | "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| 2872 | "cegbr\\t%0,%1" | |
| 2873 | [(set_attr "op_type" "RRE") | |
| 4023fb28 | 2874 | (set_attr "type" "other" )]) |
| 9db1d521 HP |
2875 | |
| 2876 | ; | |
| 2877 | ; floatsidf2 instruction pattern(s). | |
| 2878 | ; | |
| 2879 | ||
| 2880 | (define_expand "floatsidf2" | |
| 4023fb28 UW |
2881 | [(parallel |
| 2882 | [(set (match_operand:DF 0 "register_operand" "") | |
| 2883 | (float:DF (match_operand:SI 1 "register_operand" ""))) | |
| 2884 | (clobber (reg:CC 33))])] | |
| 9db1d521 HP |
2885 | "TARGET_HARD_FLOAT" |
| 2886 | " | |
| 2887 | { | |
| 2888 | if (TARGET_IBM_FLOAT) | |
| 2889 | { | |
| 2890 | /* This is the algorithm from POP chapter A.5.7.1. */ | |
| 2891 | ||
| 2892 | rtx temp = assign_stack_local (BLKmode, 2 * UNITS_PER_WORD, BITS_PER_WORD); | |
| 4023fb28 | 2893 | rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000); |
| 9db1d521 HP |
2894 | |
| 2895 | emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp)); | |
| 2896 | DONE; | |
| 2897 | } | |
| 2898 | }") | |
| 2899 | ||
| 2900 | (define_insn "floatsidf2_ieee" | |
| 2901 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 4023fb28 UW |
2902 | (float:DF (match_operand:SI 1 "register_operand" "d"))) |
| 2903 | (clobber (reg:CC 33))] | |
| 9db1d521 HP |
2904 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| 2905 | "cdfbr\\t%0,%1" | |
| 2906 | [(set_attr "op_type" "RRE") | |
| f2d3c02a | 2907 | (set_attr "type" "other" )]) |
| 9db1d521 HP |
2908 | |
| 2909 | (define_insn "floatsidf2_ibm" | |
| 2910 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 2911 | (float:DF (match_operand:SI 1 "register_operand" "d"))) | |
| 4023fb28 | 2912 | (use (match_operand:DI 2 "immediate_operand" "m")) |
| 9db1d521 HP |
2913 | (use (match_operand:BLK 3 "memory_operand" "m")) |
| 2914 | (clobber (reg:CC 33))] | |
| 2915 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 2916 | "* | |
| 2917 | { | |
| 4023fb28 | 2918 | output_asm_insn (\"st\\t%1,%N3\", operands); |
| 9db1d521 HP |
2919 | output_asm_insn (\"xi\\t%N3,128\", operands); |
| 2920 | output_asm_insn (\"mvc\\t%O3(4,%R3),%2\", operands); | |
| 2921 | output_asm_insn (\"ld\\t%0,%3\", operands); | |
| 2922 | return \"sd\\t%0,%2\"; | |
| 2923 | }" | |
| 2924 | [(set_attr "op_type" "NN") | |
| 4023fb28 | 2925 | (set_attr "type" "other" ) |
| 9db1d521 HP |
2926 | (set_attr "length" "20")]) |
| 2927 | ||
| 2928 | ; | |
| 2929 | ; floatsisf2 instruction pattern(s). | |
| 2930 | ; | |
| 2931 | ||
| 2932 | (define_expand "floatsisf2" | |
| 4023fb28 UW |
2933 | [(parallel |
| 2934 | [(set (match_operand:SF 0 "register_operand" "") | |
| 2935 | (float:SF (match_operand:SI 1 "register_operand" ""))) | |
| 2936 | (clobber (reg:CC 33))])] | |
| 9db1d521 HP |
2937 | "TARGET_HARD_FLOAT" |
| 2938 | " | |
| 2939 | { | |
| 2940 | if (TARGET_IBM_FLOAT) | |
| 2941 | { | |
| 2942 | /* Use the POP algorithm to convert to DFmode and then truncate. */ | |
| 2943 | rtx temp = gen_reg_rtx (DFmode); | |
| 2944 | emit_insn (gen_floatsidf2 (temp, operands[1])); | |
| 2945 | emit_insn (gen_truncdfsf2 (operands[0], temp)); | |
| 2946 | DONE; | |
| 2947 | } | |
| 2948 | }") | |
| 2949 | ||
| 2950 | (define_insn "floatsisf2_ieee" | |
| 2951 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 4023fb28 UW |
2952 | (float:SF (match_operand:SI 1 "register_operand" "d"))) |
| 2953 | (clobber (reg:CC 33))] | |
| 9db1d521 HP |
2954 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| 2955 | "cefbr\\t%0,%1" | |
| 2956 | [(set_attr "op_type" "RRE") | |
| 4023fb28 | 2957 | (set_attr "type" "other" )]) |
| 9db1d521 HP |
2958 | |
| 2959 | ; | |
| 2960 | ; truncdfsf2 instruction pattern(s). | |
| 2961 | ; | |
| 2962 | ||
| 2963 | (define_expand "truncdfsf2" | |
| 2964 | [(set (match_operand:SF 0 "register_operand" "") | |
| 2965 | (float_truncate:SF (match_operand:DF 1 "general_operand" "")))] | |
| 2966 | "TARGET_HARD_FLOAT" | |
| 4023fb28 | 2967 | "") |
| 9db1d521 HP |
2968 | |
| 2969 | (define_insn "truncdfsf2_ieee" | |
| 2970 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 4023fb28 | 2971 | (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))] |
| 9db1d521 HP |
2972 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" |
| 2973 | "ledbr\\t%0,%1" | |
| 2974 | [(set_attr "op_type" "RR")]) | |
| 2975 | ||
| 2976 | (define_insn "truncdfsf2_ibm" | |
| 2977 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 4023fb28 | 2978 | (float_truncate:SF (match_operand:DF 1 "general_operand" "f,m")))] |
| 9db1d521 HP |
2979 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" |
| 2980 | "@ | |
| 2981 | lrer\\t%0,%1 | |
| 2982 | le\\t%0,%1" | |
| 4023fb28 UW |
2983 | [(set_attr "op_type" "RR,RX") |
| 2984 | (set_attr "atype" "reg,mem")]) | |
| 9db1d521 HP |
2985 | |
| 2986 | ; | |
| 2987 | ; extendsfdf2 instruction pattern(s). | |
| 2988 | ; | |
| 2989 | ||
| 2990 | (define_expand "extendsfdf2" | |
| 2991 | [(set (match_operand:DF 0 "register_operand" "") | |
| 2992 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))] | |
| 2993 | "TARGET_HARD_FLOAT" | |
| 2994 | " | |
| 2995 | { | |
| 2996 | if (TARGET_IBM_FLOAT) | |
| 2997 | { | |
| 2998 | emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1])); | |
| 2999 | DONE; | |
| 3000 | } | |
| 3001 | }") | |
| 3002 | ||
| 3003 | (define_insn "extendsfdf2_ieee" | |
| 3004 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 3005 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m")))] | |
| 3006 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 3007 | "@ | |
| 3008 | ldebr\\t%0,%1 | |
| 3009 | ldeb\\t%0,%1" | |
| 3010 | [(set_attr "op_type" "RRE,RXE")]) | |
| 3011 | ||
| 3012 | (define_insn "extendsfdf2_ibm" | |
| 3013 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 3014 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m"))) | |
| 3015 | (clobber (reg:CC 33))] | |
| 3016 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 3017 | "@ | |
| 3018 | sdr\\t%0,%0\;ler\\t%0,%1 | |
| 3019 | sdr\\t%0,%0\;le\\t%0,%1" | |
| 4023fb28 UW |
3020 | [(set_attr "op_type" "RRE,RXE") |
| 3021 | (set_attr "atype" "reg,mem") | |
| 3022 | (set_attr "type" "o2,o2")]) | |
| 9db1d521 HP |
3023 | |
| 3024 | ||
| 3025 | ;; | |
| 3026 | ;; ARITHMETRIC OPERATIONS | |
| 3027 | ;; | |
| 3028 | ; arithmetric operations set the ConditionCode, | |
| 3029 | ; because of unpredictable Bits in Register for Halfword and Byte | |
| 3030 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
| 3031 | ||
| 3032 | ;; | |
| 3033 | ;;- Add instructions. | |
| 3034 | ;; | |
| 3035 | ||
| 3036 | ; | |
| 3037 | ; adddi3 instruction pattern(s). | |
| 3038 | ; | |
| 3039 | ||
| 3040 | (define_insn "addaddr_esame" | |
| 3041 | [(set (match_operand:DI 0 "register_operand" "=a,a") | |
| 3042 | (plus:DI (match_operand:DI 1 "register_operand" "%a,a") | |
| 3043 | (match_operand:DI 2 "nonmemory_operand" "J,a")))] | |
| 3044 | "TARGET_64BIT && (((REGNO (operands[1]) == STACK_POINTER_REGNUM ) || | |
| 3045 | (REGNO (operands[1]) == BASE_REGISTER)) && | |
| 3046 | (GET_CODE (operands[2]) == REG || | |
| 3047 | CONST_OK_FOR_LETTER_P (INTVAL (operands[2]),'J')))" | |
| 3048 | "@ | |
| 3049 | la\\t%0,%c2(,%1) | |
| 3050 | la\\t%0,0(%1,%2)" | |
| 3051 | [(set_attr "op_type" "RX") | |
| 3052 | (set_attr "atype" "mem") | |
| 3053 | (set_attr "type" "la")]) | |
| 3054 | ||
| 3055 | (define_insn "adddi3_64" | |
| 3056 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") | |
| 3057 | (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0") | |
| 3058 | (match_operand:DI 2 "general_operand" "d,K,m") ) ) | |
| 3059 | (clobber (reg:CC 33))] | |
| 3060 | "TARGET_64BIT" | |
| 3061 | "@ | |
| 3062 | agr\\t%0,%2 | |
| 3063 | aghi\\t%0,%h2 | |
| 3064 | ag\\t%0,%2" | |
| 3065 | [(set_attr "op_type" "RRE,RI,RXE") | |
| f2d3c02a | 3066 | (set_attr "atype" "reg,reg,mem")]) |
| 9db1d521 HP |
3067 | |
| 3068 | ; | |
| 3069 | ; For weakness of reload, need (set (reg x) (plus (reg y) (reg x))) | |
| 3070 | ; | |
| 3071 | ||
| 3072 | (define_insn "adddi3_inv_64" | |
| 3073 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") | |
| 3074 | (plus:DI (match_operand:DI 1 "general_operand" "%d,K,m") | |
| 3075 | (match_operand:DI 2 "register_operand" "0,0,0") ) ) | |
| 3076 | (clobber (reg:CC 33))] | |
| 3077 | "TARGET_64BIT" | |
| 3078 | "@ | |
| 3079 | agr\\t%0,%1 | |
| 3080 | aghi\\t%0,%h1 | |
| 3081 | ag\\t%0,%1" | |
| 3082 | [(set_attr "op_type" "RRE,RI,RXE") | |
| f2d3c02a | 3083 | (set_attr "atype" "reg,reg,mem")]) |
| 9db1d521 HP |
3084 | |
| 3085 | (define_insn "adddi3_31" | |
| 3086 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 3087 | (plus:DI (match_operand:DI 1 "register_operand" "0,0") | |
| 3088 | (match_operand:DI 2 "general_operand" "d,m") ) ) | |
| 3089 | (clobber (reg:CC 33))] | |
| 3090 | "!TARGET_64BIT" | |
| 3091 | "* | |
| 3092 | { | |
| 4023fb28 | 3093 | switch (which_alternative) |
| 9db1d521 HP |
3094 | { |
| 3095 | case 0: /* d <- d */ | |
| 3096 | output_asm_insn (\"ar\\t%0,%2\", operands); | |
| 3097 | output_asm_insn (\"alr\\t%N0,%N2\", operands); | |
| 3098 | break; | |
| 3099 | ||
| 3100 | case 1: /* d <- m */ | |
| 3101 | output_asm_insn (\"a\\t%0,%2\", operands); | |
| 3102 | output_asm_insn (\"al\\t%N0,%N2\", operands); | |
| 3103 | break; | |
| 4023fb28 UW |
3104 | |
| 3105 | default: | |
| 3106 | abort (); | |
| 9db1d521 HP |
3107 | } |
| 3108 | ||
| 3109 | output_asm_insn (\"brc\\t12,.+8\", operands); | |
| 3110 | return \"ahi\\t%0,1\"; | |
| 3111 | }" | |
| 3112 | [(set_attr "op_type" "NN,NN") | |
| 3113 | (set_attr "atype" "reg,mem") | |
| 4023fb28 | 3114 | (set_attr "type" "o2,o2") |
| 9db1d521 HP |
3115 | (set_attr "length" "12,16")]) |
| 3116 | ||
| 3117 | (define_expand "adddi3" | |
| 3118 | [(set (match_operand:DI 0 "register_operand" "") | |
| 3119 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
| 3120 | (match_operand:DI 2 "general_operand" "")))] | |
| 3121 | "" | |
| 3122 | " | |
| 3123 | { | |
| 3124 | if (TARGET_64BIT) | |
| 3125 | emit_insn(gen_adddi3_64 (operands[0],operands[1],operands[2])); | |
| 3126 | else | |
| 3127 | emit_insn(gen_adddi3_31 (operands[0],operands[1],operands[2])); | |
| 3128 | DONE; | |
| 3129 | }") | |
| 3130 | ||
| 3131 | (define_insn "reload_load_address" | |
| 3132 | [(set (match_operand:DI 0 "register_operand" "=a") | |
| 3133 | (match_operand:QI 1 "address_operand" "p"))] | |
| 3134 | "TARGET_64BIT" | |
| 3135 | "la\\t%0,%a1" | |
| 3136 | [(set_attr "op_type" "RX") | |
| 3137 | (set_attr "atype" "mem") | |
| 3138 | (set_attr "type" "la")]) | |
| 3139 | ||
| 3140 | (define_insn "*reload_load_address_reg_0" | |
| 3141 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 3142 | (plus:DI (match_operand:DI 1 "register_operand" "%0") | |
| 3143 | (match_operand:DI 2 "register_operand" "d")))] | |
| 3144 | "TARGET_64BIT" | |
| 3145 | "brxlg\\t%0,%2,.+6" | |
| 3146 | [(set_attr "op_type" "RIE") | |
| f2d3c02a | 3147 | (set_attr "atype" "reg")]) |
| 9db1d521 HP |
3148 | |
| 3149 | (define_insn "*reload_la_64" | |
| 3150 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 3151 | (plus:DI (match_operand:DI 1 "general_operand" "g") | |
| 3152 | (match_operand:DI 2 "general_operand" "g")))] | |
| bc1fa59c UW |
3153 | "TARGET_64BIT && reload_in_progress |
| 3154 | && !address_operand (gen_rtx_PLUS (DImode, operands[1], operands[2]), QImode) | |
| 3155 | && !rtx_equal_p (operands[0], operands[1]) | |
| 3156 | && !rtx_equal_p (operands[0], operands[2])" | |
| 9db1d521 HP |
3157 | "#") |
| 3158 | ||
| 3159 | (define_split | |
| 3160 | [(set (match_operand:DI 0 "register_operand" "") | |
| 3161 | (plus:DI (match_operand:DI 1 "general_operand" "") | |
| 3162 | (match_operand:DI 2 "register_operand" "")))] | |
| 3163 | "TARGET_64BIT && reload_completed | |
| 3164 | && !address_operand (gen_rtx_PLUS (DImode, operands[1], operands[2]), QImode) | |
| 3165 | && !rtx_equal_p (operands[0], operands[1]) | |
| 3166 | && !rtx_equal_p (operands[0], operands[2])" | |
| 3167 | [(set (match_dup 0) (match_dup 1)) | |
| 3168 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))] | |
| 4023fb28 UW |
3169 | " |
| 3170 | { | |
| 3171 | if (CONSTANT_P (operands[1]) | |
| 3172 | && !legitimate_reload_constant_p (operands[1])) | |
| 3173 | operands[1] = force_const_mem (DImode, operands[1]); | |
| 3174 | }") | |
| 3175 | ||
| 9db1d521 HP |
3176 | (define_split |
| 3177 | [(set (match_operand:DI 0 "register_operand" "") | |
| 3178 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
| 3179 | (match_operand:DI 2 "general_operand" "")))] | |
| 3180 | "TARGET_64BIT && reload_completed | |
| 3181 | && !address_operand (gen_rtx_PLUS (DImode, operands[1], operands[2]), QImode) | |
| 3182 | && !rtx_equal_p (operands[0], operands[1]) | |
| 3183 | && !rtx_equal_p (operands[0], operands[2])" | |
| 3184 | [(set (match_dup 0) (match_dup 2)) | |
| 3185 | (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))] | |
| 4023fb28 UW |
3186 | " |
| 3187 | { | |
| 3188 | if (CONSTANT_P (operands[2]) | |
| 3189 | && !legitimate_reload_constant_p (operands[2])) | |
| 3190 | operands[2] = force_const_mem (DImode, operands[2]); | |
| 3191 | }") | |
| 9db1d521 HP |
3192 | |
| 3193 | ; | |
| 3194 | ; addsi3 instruction pattern(s). | |
| 3195 | ; | |
| 9db1d521 | 3196 | |
| 4023fb28 UW |
3197 | (define_insn "*la_ccclobber" |
| 3198 | [(set (match_operand:SI 0 "register_operand" "=a") | |
| 3199 | (match_operand:QI 1 "address_operand" "p")) | |
| 3200 | (clobber (reg:CC 33))] | |
| 3201 | "legitimate_la_operand_p (operands[1])" | |
| 3202 | "la\\t%0,%a1" | |
| 3203 | [(set_attr "op_type" "RX") | |
| 3204 | (set_attr "atype" "mem") | |
| 3205 | (set_attr "type" "la")]) | |
| 3206 | ||
| 3207 | (define_insn "*addaddr_ccclobber" | |
| 9db1d521 HP |
3208 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
| 3209 | (plus:SI (match_operand:SI 1 "register_operand" "%a,a") | |
| 4023fb28 UW |
3210 | (match_operand:SI 2 "nonmemory_operand" "J,a"))) |
| 3211 | (clobber (reg:CC 33))] | |
| 9db1d521 | 3212 | "(((REGNO (operands[1]) == STACK_POINTER_REGNUM ) || |
| 4023fb28 | 3213 | (REGNO (operands[1]) == FRAME_POINTER_REGNUM ) || |
| 9db1d521 | 3214 | (REGNO (operands[1]) == BASE_REGISTER)) && |
| 4023fb28 | 3215 | (GET_CODE (operands[2]) == REG || |
| 9db1d521 HP |
3216 | CONST_OK_FOR_LETTER_P (INTVAL (operands[2]),'J')))" |
| 3217 | "@ | |
| 3218 | la\\t%0,%c2(,%1) | |
| 3219 | la\\t%0,0(%1,%2)" | |
| 3220 | [(set_attr "op_type" "RX") | |
| 3221 | (set_attr "atype" "mem") | |
| 3222 | (set_attr "type" "la")]) | |
| 3223 | ||
| 9db1d521 HP |
3224 | (define_insn "*addsi3_cc" |
| 3225 | [(set (reg 33) | |
| ba956982 UW |
3226 | (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0") |
| 3227 | (match_operand:SI 2 "nonimmediate_operand" "d,m")) | |
| 9db1d521 | 3228 | (const_int 0))) |
| ba956982 | 3229 | (set (match_operand:SI 0 "register_operand" "=d,d") |
| 9db1d521 | 3230 | (plus:SI (match_dup 1) (match_dup 2)))] |
| ba956982 | 3231 | "s390_match_ccmode(insn, CCLmode)" |
| 9db1d521 | 3232 | "@ |
| ba956982 UW |
3233 | alr\\t%0,%2 |
| 3234 | al\\t%0,%2" | |
| 3235 | [(set_attr "op_type" "RR,RX") | |
| 3236 | (set_attr "atype" "reg,mem")]) | |
| 9db1d521 HP |
3237 | |
| 3238 | (define_insn "*addsi3_cconly" | |
| 3239 | [(set (reg 33) | |
| ba956982 UW |
3240 | (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0") |
| 3241 | (match_operand:SI 2 "general_operand" "d,m")) | |
| 9db1d521 | 3242 | (const_int 0))) |
| ba956982 UW |
3243 | (clobber (match_scratch:SI 0 "=d,d"))] |
| 3244 | "s390_match_ccmode(insn, CCLmode)" | |
| 9db1d521 | 3245 | "@ |
| ba956982 UW |
3246 | alr\\t%0,%2 |
| 3247 | al\\t%0,%2" | |
| 3248 | [(set_attr "op_type" "RR,RX") | |
| 3249 | (set_attr "atype" "reg,mem")]) | |
| 9db1d521 HP |
3250 | |
| 3251 | (define_insn "*addsi3_cconly2" | |
| 3252 | [(set (reg 33) | |
| ba956982 UW |
3253 | (compare (match_operand:SI 1 "register_operand" "%0,0") |
| 3254 | (neg:SI (match_operand:SI 2 "general_operand" "d,m")))) | |
| 3255 | (clobber (match_scratch:SI 0 "=d,d"))] | |
| 3256 | "s390_match_ccmode(insn, CCLmode)" | |
| 9db1d521 | 3257 | "@ |
| ba956982 UW |
3258 | alr\\t%0,%2 |
| 3259 | al\\t%0,%2" | |
| 3260 | [(set_attr "op_type" "RR,RX") | |
| 3261 | (set_attr "atype" "reg,mem")]) | |
| 9db1d521 HP |
3262 | |
| 3263 | (define_insn "addsi3" | |
| 3264 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
| 3265 | (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0") | |
| 3266 | (match_operand:SI 2 "general_operand" "d,K,m"))) | |
| 3267 | (clobber (reg:CC 33))] | |
| 3268 | "" | |
| 3269 | "@ | |
| 3270 | ar\\t%0,%2 | |
| 3271 | ahi\\t%0,%h2 | |
| 3272 | a\\t%0,%2" | |
| 3273 | [(set_attr "op_type" "RR,RI,RX") | |
| f2d3c02a | 3274 | (set_attr "atype" "reg,reg,mem")]) |
| 9db1d521 | 3275 | |
| 4023fb28 | 3276 | (define_insn "*la" |
| 9db1d521 HP |
3277 | [(set (match_operand:SI 0 "register_operand" "=a") |
| 3278 | (match_operand:QI 1 "address_operand" "p"))] | |
| ba956982 UW |
3279 | "reload_in_progress || reload_completed |
| 3280 | || legitimate_la_operand_p (operands[1])" | |
| 9db1d521 HP |
3281 | "la\\t%0,%a1" |
| 3282 | [(set_attr "op_type" "RX") | |
| 3283 | (set_attr "atype" "mem") | |
| 3284 | (set_attr "type" "la")]) | |
| 3285 | ||
| 3286 | (define_insn "*do_la_reg_0" | |
| 3287 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 3288 | (plus:SI (match_operand:SI 1 "register_operand" "%0") | |
| 3289 | (match_operand:SI 2 "register_operand" "d")))] | |
| ba956982 | 3290 | "reload_in_progress || reload_completed" |
| 9db1d521 HP |
3291 | "brxle\\t%0,%2,.+4" |
| 3292 | [(set_attr "op_type" "RSI") | |
| f2d3c02a | 3293 | (set_attr "atype" "reg")]) |
| 9db1d521 HP |
3294 | |
| 3295 | (define_insn "*reload_la_31" | |
| 3296 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 3297 | (plus:SI (match_operand:SI 1 "general_operand" "g") | |
| 3298 | (match_operand:SI 2 "general_operand" "g")))] | |
| bc1fa59c UW |
3299 | "reload_in_progress |
| 3300 | && !address_operand (gen_rtx_PLUS (SImode, operands[1], operands[2]), QImode) | |
| 3301 | && !rtx_equal_p (operands[0], operands[1]) | |
| 3302 | && !rtx_equal_p (operands[0], operands[2])" | |
| 9db1d521 HP |
3303 | "#") |
| 3304 | ||
| 3305 | (define_split | |
| 3306 | [(set (match_operand:SI 0 "register_operand" "") | |
| 3307 | (plus:SI (match_operand:SI 1 "general_operand" "") | |
| 3308 | (match_operand:SI 2 "register_operand" "")))] | |
| 3309 | "reload_completed | |
| 3310 | && !address_operand (gen_rtx_PLUS (SImode, operands[1], operands[2]), QImode) | |
| 3311 | && !rtx_equal_p (operands[0], operands[1]) | |
| 3312 | && !rtx_equal_p (operands[0], operands[2])" | |
| 3313 | [(set (match_dup 0) (match_dup 1)) | |
| 3314 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))] | |
| 4023fb28 UW |
3315 | " |
| 3316 | { | |
| 3317 | if (CONSTANT_P (operands[1]) | |
| 3318 | && !legitimate_reload_constant_p (operands[1])) | |
| 3319 | operands[1] = force_const_mem (SImode, operands[1]); | |
| 3320 | }") | |
| 9db1d521 HP |
3321 | |
| 3322 | (define_split | |
| 3323 | [(set (match_operand:SI 0 "register_operand" "") | |
| 3324 | (plus:SI (match_operand:SI 1 "register_operand" "") | |
| 3325 | (match_operand:SI 2 "general_operand" "")))] | |
| 3326 | "reload_completed | |
| 3327 | && !address_operand (gen_rtx_PLUS (SImode, operands[1], operands[2]), QImode) | |
| 3328 | && !rtx_equal_p (operands[0], operands[1]) | |
| 3329 | && !rtx_equal_p (operands[0], operands[2])" | |
| 3330 | [(set (match_dup 0) (match_dup 2)) | |
| 3331 | (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))] | |
| 4023fb28 UW |
3332 | " |
| 3333 | { | |
| 3334 | if (CONSTANT_P (operands[2]) | |
| 3335 | && !legitimate_reload_constant_p (operands[2])) | |
| 3336 | operands[2] = force_const_mem (SImode, operands[2]); | |
| 3337 | }") | |
| bc1fa59c | 3338 | |
| 9db1d521 HP |
3339 | |
| 3340 | ; | |
| 3341 | ; addhi3 instruction pattern(s). | |
| 3342 | ; | |
| 3343 | ||
| 3344 | (define_insn "addhi3" | |
| 3345 | [(set (match_operand:HI 0 "register_operand" "=d,d,d") | |
| 3346 | (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0") | |
| 3347 | (match_operand:HI 2 "general_operand" "d,K,m"))) | |
| 3348 | (clobber (reg:CC 33))] | |
| 3349 | "" | |
| 3350 | "@ | |
| 3351 | ar\\t%0,%2 | |
| 3352 | ahi\\t%0,%h2 | |
| 3353 | ah\\t%0,%2" | |
| 3354 | [(set_attr "op_type" "RR,RI,RX") | |
| 3355 | (set_attr "atype" "reg,reg,mem")]) | |
| 3356 | ||
| 3357 | ||
| 3358 | ; | |
| 3359 | ; addqi3 instruction pattern(s). | |
| 3360 | ; | |
| 3361 | ||
| 3362 | (define_insn "addqi3" | |
| 3363 | [(set (match_operand:QI 0 "register_operand" "=d,d") | |
| 3364 | (plus:QI (match_operand:QI 1 "register_operand" "%0,0") | |
| 3365 | (match_operand:QI 2 "general_operand" "a,n"))) | |
| 3366 | (clobber (reg:CC 33))] | |
| 3367 | "" | |
| 3368 | "@ | |
| 3369 | ar\\t%0,%2 | |
| 3370 | ahi\\t%0,%h2" | |
| 3371 | [(set_attr "op_type" "RX,RX") | |
| 3372 | (set_attr "atype" "reg,mem")]) | |
| 3373 | ||
| 3374 | ||
| 3375 | ; | |
| 3376 | ; adddf3 instruction pattern(s). | |
| 3377 | ; | |
| 3378 | ||
| 3379 | (define_expand "adddf3" | |
| 3380 | [(parallel | |
| 3381 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 3382 | (plus:DF (match_operand:DF 1 "register_operand" "%0,0") | |
| 4023fb28 | 3383 | (match_operand:DF 2 "general_operand" "f,m"))) |
| 9db1d521 HP |
3384 | (clobber (reg:CC 33))])] |
| 3385 | "TARGET_HARD_FLOAT" | |
| 3386 | "") | |
| 3387 | ||
| 3388 | (define_insn "*adddf3" | |
| 3389 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 3390 | (plus:DF (match_operand:DF 1 "register_operand" "%0,0") | |
| 4023fb28 | 3391 | (match_operand:DF 2 "general_operand" "f,m"))) |
| 9db1d521 HP |
3392 | (clobber (reg:CC 33))] |
| 3393 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 3394 | "@ | |
| 3395 | adbr\\t%0,%2 | |
| 3396 | adb\\t%0,%2" | |
| 3397 | [(set_attr "op_type" "RR,RX") | |
| 3398 | (set_attr "atype" "reg,mem")]) | |
| 3399 | ||
| 3400 | (define_insn "*adddf3_ibm" | |
| 3401 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 3402 | (plus:DF (match_operand:DF 1 "register_operand" "%0,0") | |
| 4023fb28 | 3403 | (match_operand:DF 2 "general_operand" "f,m"))) |
| 9db1d521 HP |
3404 | (clobber (reg:CC 33))] |
| 3405 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 3406 | "@ | |
| 3407 | adr\\t%0,%2 | |
| 3408 | ad\\t%0,%2" | |
| 3409 | [(set_attr "op_type" "RR,RX") | |
| 3410 | (set_attr "atype" "reg,mem")]) | |
| 3411 | ||
| 3412 | ; | |
| 3413 | ; addsf3 instruction pattern(s). | |
| 3414 | ; | |
| 3415 | ||
| 3416 | (define_expand "addsf3" | |
| 3417 | [(parallel | |
| 3418 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 3419 | (plus:SF (match_operand:SF 1 "register_operand" "%0,0") | |
| 4023fb28 | 3420 | (match_operand:SF 2 "general_operand" "f,m"))) |
| 9db1d521 HP |
3421 | (clobber (reg:CC 33))])] |
| 3422 | "TARGET_HARD_FLOAT" | |
| 3423 | "") | |
| 3424 | ||
| 3425 | (define_insn "*addsf3" | |
| 3426 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 3427 | (plus:SF (match_operand:SF 1 "register_operand" "%0,0") | |
| 4023fb28 | 3428 | (match_operand:SF 2 "general_operand" "f,m"))) |
| 9db1d521 HP |
3429 | (clobber (reg:CC 33))] |
| 3430 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 3431 | "@ | |
| 3432 | aebr\\t%0,%2 | |
| 3433 | aeb\\t%0,%2" | |
| 3434 | [(set_attr "op_type" "RR,RX") | |
| 3435 | (set_attr "atype" "reg,mem")]) | |
| 3436 | ||
| 3437 | (define_insn "*addsf3" | |
| 3438 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 3439 | (plus:SF (match_operand:SF 1 "register_operand" "%0,0") | |
| 4023fb28 | 3440 | (match_operand:SF 2 "general_operand" "f,m"))) |
| 9db1d521 HP |
3441 | (clobber (reg:CC 33))] |
| 3442 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 3443 | "@ | |
| 3444 | aer\\t%0,%2 | |
| 3445 | ae\\t%0,%2" | |
| 3446 | [(set_attr "op_type" "RR,RX") | |
| 3447 | (set_attr "atype" "reg,mem")]) | |
| 3448 | ||
| 3449 | ||
| 3450 | ;; | |
| 3451 | ;;- Subtract instructions. | |
| 3452 | ;; | |
| 3453 | ||
| 3454 | ; | |
| 3455 | ; subdi3 instruction pattern(s). | |
| 3456 | ; | |
| 3457 | ||
| 3458 | (define_insn "*subdi3_64" | |
| 3459 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 3460 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
| 3461 | (match_operand:DI 2 "general_operand" "d,m") ) ) | |
| 3462 | (clobber (reg:CC 33))] | |
| 3463 | "TARGET_64BIT" | |
| 3464 | "@ | |
| 3465 | sgr\\t%0,%2 | |
| 3466 | sg\\t%0,%2" | |
| 3467 | [(set_attr "op_type" "RRE,RRE") | |
| f2d3c02a | 3468 | (set_attr "atype" "reg,mem")]) |
| 9db1d521 HP |
3469 | |
| 3470 | (define_insn "subdi3" | |
| 3471 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 3472 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
| 4023fb28 | 3473 | (match_operand:DI 2 "general_operand" "d,m"))) |
| 9db1d521 HP |
3474 | (clobber (reg:CC 33))] |
| 3475 | "" | |
| 3476 | "* | |
| 3477 | { | |
| 3478 | switch (which_alternative) | |
| 3479 | { | |
| 3480 | case 0: /* d <- d */ | |
| 3481 | output_asm_insn (\"sr\\t%0,%2\", operands); | |
| 3482 | output_asm_insn (\"slr\\t%N0,%N2\", operands); | |
| 3483 | break; | |
| 3484 | case 1: /* d <- m */ | |
| 3485 | output_asm_insn (\"s\\t%0,%2\", operands); | |
| 3486 | output_asm_insn (\"sl\\t%N0,%N2\", operands); | |
| 3487 | break; | |
| 4023fb28 UW |
3488 | |
| 3489 | default: | |
| 3490 | abort (); | |
| 9db1d521 HP |
3491 | } |
| 3492 | ||
| 3493 | output_asm_insn (\"brc\\t11,.+8\", operands); | |
| 3494 | return \"ahi\\t%0,-1\"; | |
| 3495 | }" | |
| 3496 | [(set_attr "op_type" "NN,NN") | |
| 3497 | (set_attr "atype" "reg,mem") | |
| 4023fb28 | 3498 | (set_attr "type" "other,other") |
| 9db1d521 HP |
3499 | (set_attr "length" "12,16")]) |
| 3500 | ||
| 3501 | ; | |
| 3502 | ; subsi3 instruction pattern(s). | |
| 3503 | ; | |
| 3504 | ||
| 3505 | (define_insn "*subsi3_cc" | |
| 3506 | [(set (reg 33) | |
| 3507 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
| 3508 | (match_operand:SI 2 "general_operand" "d,m")) | |
| 3509 | (const_int 0))) | |
| 3510 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
| 3511 | (minus:SI (match_dup 1) (match_dup 2)))] | |
| ba956982 | 3512 | "s390_match_ccmode(insn, CCLmode)" |
| 9db1d521 | 3513 | "@ |
| ba956982 UW |
3514 | slr\\t%0,%2 |
| 3515 | sl\\t%0,%2" | |
| 9db1d521 | 3516 | [(set_attr "op_type" "RR,RX") |
| f2d3c02a | 3517 | (set_attr "atype" "reg,mem")]) |
| 9db1d521 HP |
3518 | |
| 3519 | (define_insn "*subsi3_cconly" | |
| 3520 | [(set (reg 33) | |
| 3521 | (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
| 3522 | (match_operand:SI 2 "general_operand" "d,m")) | |
| 3523 | (const_int 0))) | |
| 3524 | (clobber (match_scratch:SI 0 "=d,d"))] | |
| ba956982 | 3525 | "s390_match_ccmode(insn, CCLmode)" |
| 9db1d521 | 3526 | "@ |
| ba956982 UW |
3527 | slr\\t%0,%2 |
| 3528 | sl\\t%0,%2" | |
| 9db1d521 | 3529 | [(set_attr "op_type" "RR,RX") |
| f2d3c02a | 3530 | (set_attr "atype" "reg,mem")]) |
| 9db1d521 HP |
3531 | |
| 3532 | (define_insn "subsi3" | |
| 3533 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 3534 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
| 3535 | (match_operand:SI 2 "general_operand" "d,m"))) | |
| 3536 | (clobber (reg:CC 33))] | |
| 3537 | "" | |
| 3538 | "@ | |
| 3539 | sr\\t%0,%2 | |
| 3540 | s\\t%0,%2" | |
| 3541 | [(set_attr "op_type" "RR,RX") | |
| f2d3c02a | 3542 | (set_attr "atype" "reg,mem")]) |
| 9db1d521 HP |
3543 | |
| 3544 | ; | |
| 3545 | ; subhi3 instruction pattern(s). | |
| 3546 | ; | |
| 3547 | ||
| 3548 | (define_insn "subhi3" | |
| 4023fb28 UW |
3549 | [(set (match_operand:HI 0 "register_operand" "=d,d") |
| 3550 | (minus:HI (match_operand:HI 1 "register_operand" "0,0") | |
| 3551 | (match_operand:HI 2 "general_operand" "d,m"))) | |
| 9db1d521 HP |
3552 | (clobber (reg:CC 33))] |
| 3553 | "" | |
| 3554 | "@ | |
| 3555 | sr\\t%0,%2 | |
| 9db1d521 | 3556 | sh\\t%0,%2" |
| 4023fb28 UW |
3557 | [(set_attr "op_type" "RR,RX") |
| 3558 | (set_attr "atype" "reg,mem")]) | |
| 9db1d521 HP |
3559 | |
| 3560 | ; | |
| 3561 | ; subqi3 instruction pattern(s). | |
| 3562 | ; | |
| 3563 | ||
| 3564 | (define_insn "subqi3" | |
| 3565 | [(set (match_operand:QI 0 "register_operand" "=d") | |
| 3566 | (minus:QI (match_operand:QI 1 "register_operand" "0") | |
| 3567 | (match_operand:QI 2 "register_operand" "d"))) | |
| 3568 | (clobber (reg:CC 33))] | |
| 3569 | "" | |
| 3570 | "sr\\t%0,%2" | |
| 3571 | [(set_attr "op_type" "RR")]) | |
| 3572 | ||
| 3573 | ; | |
| 3574 | ; subdf3 instruction pattern(s). | |
| 3575 | ; | |
| 3576 | ||
| 3577 | (define_expand "subdf3" | |
| 3578 | [(parallel | |
| 3579 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 3580 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
| 4023fb28 | 3581 | (match_operand:DF 2 "general_operand" "f,m"))) |
| 9db1d521 HP |
3582 | (clobber (reg:CC 33))])] |
| 3583 | "TARGET_HARD_FLOAT" | |
| 3584 | "") | |
| 3585 | ||
| 3586 | (define_insn "*subdf3" | |
| 3587 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 3588 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
| 4023fb28 | 3589 | (match_operand:DF 2 "general_operand" "f,m"))) |
| 9db1d521 HP |
3590 | (clobber (reg:CC 33))] |
| 3591 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 3592 | "@ | |
| 3593 | sdbr\\t%0,%2 | |
| 3594 | sdb\\t%0,%2" | |
| 3595 | [(set_attr "op_type" "RR,RX") | |
| 3596 | (set_attr "atype" "reg,mem")]) | |
| 3597 | ||
| 3598 | (define_insn "*subdf3_ibm" | |
| 3599 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 3600 | (minus:DF (match_operand:DF 1 "register_operand" "0,0") | |
| 4023fb28 | 3601 | (match_operand:DF 2 "general_operand" "f,m"))) |
| 9db1d521 HP |
3602 | (clobber (reg:CC 33))] |
| 3603 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 3604 | "@ | |
| 3605 | sdr\\t%0,%2 | |
| 3606 | sd\\t%0,%2" | |
| 3607 | [(set_attr "op_type" "RR,RX") | |
| 3608 | (set_attr "atype" "reg,mem")]) | |
| 3609 | ||
| 3610 | ; | |
| 3611 | ; subsf3 instruction pattern(s). | |
| 3612 | ; | |
| 3613 | ||
| 3614 | (define_expand "subsf3" | |
| 3615 | [(parallel | |
| 3616 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 3617 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
| 4023fb28 | 3618 | (match_operand:SF 2 "general_operand" "f,m"))) |
| 9db1d521 HP |
3619 | (clobber (reg:CC 33))])] |
| 3620 | "TARGET_HARD_FLOAT" | |
| 3621 | "") | |
| 3622 | ||
| 3623 | (define_insn "*subsf3" | |
| 3624 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 3625 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
| 4023fb28 | 3626 | (match_operand:SF 2 "general_operand" "f,m"))) |
| 9db1d521 HP |
3627 | (clobber (reg:CC 33))] |
| 3628 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 3629 | "@ | |
| 3630 | sebr\\t%0,%2 | |
| 3631 | seb\\t%0,%2" | |
| 3632 | [(set_attr "op_type" "RR,RX") | |
| 3633 | (set_attr "atype" "reg,mem")]) | |
| 3634 | ||
| 3635 | (define_insn "*subsf3_ibm" | |
| 3636 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 3637 | (minus:SF (match_operand:SF 1 "register_operand" "0,0") | |
| 4023fb28 | 3638 | (match_operand:SF 2 "general_operand" "f,m"))) |
| 9db1d521 HP |
3639 | (clobber (reg:CC 33))] |
| 3640 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 3641 | "@ | |
| 3642 | ser\\t%0,%2 | |
| 3643 | se\\t%0,%2" | |
| 3644 | [(set_attr "op_type" "RR,RX") | |
| 3645 | (set_attr "atype" "reg,mem")]) | |
| 3646 | ||
| 3647 | ||
| 3648 | ;; | |
| 3649 | ;;- Multiply instructions. | |
| 3650 | ;; | |
| 3651 | ||
| 4023fb28 UW |
3652 | ; |
| 3653 | ; muldi3 instruction pattern(s). | |
| 3654 | ; | |
| 9db1d521 | 3655 | |
| 4023fb28 | 3656 | (define_insn "muldi3" |
| 9db1d521 HP |
3657 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
| 3658 | (mult:DI (match_operand:DI 1 "register_operand" "%0,0,0") | |
| 3659 | (match_operand:DI 2 "general_operand" "d,K,m"))) | |
| 3660 | (clobber (reg:CC 33))] | |
| 3661 | "TARGET_64BIT" | |
| 3662 | "@ | |
| 3663 | msgr\\t%0,%2 | |
| 3664 | mghi\\t%0,%h2 | |
| 3665 | msg\\t%0,%2" | |
| 3666 | [(set_attr "op_type" "RRE,RI,RX") | |
| 9db1d521 | 3667 | (set_attr "atype" "reg,reg,mem") |
| f2d3c02a HP |
3668 | (set_attr "type" "imul")]) |
| 3669 | ||
| 9db1d521 HP |
3670 | ; |
| 3671 | ; mulsi3 instruction pattern(s). | |
| 3672 | ; | |
| 3673 | ||
| 3674 | (define_insn "mulsi3" | |
| 3675 | [(set (match_operand:SI 0 "register_operand" "=d,d,d") | |
| 3676 | (mult:SI (match_operand:SI 1 "register_operand" "%0,0,0") | |
| 3677 | (match_operand:SI 2 "general_operand" "d,K,m"))) | |
| 3678 | (clobber (reg:CC 33))] | |
| 3679 | "" | |
| 3680 | "@ | |
| 3681 | msr\\t%0,%2 | |
| 3682 | mhi\\t%0,%h2 | |
| 3683 | ms\\t%0,%2" | |
| 3684 | [(set_attr "op_type" "RRE,RI,RX") | |
| 9db1d521 | 3685 | (set_attr "atype" "reg,reg,mem") |
| f2d3c02a | 3686 | (set_attr "type" "imul")]) |
| 9db1d521 | 3687 | |
| 4023fb28 UW |
3688 | ; |
| 3689 | ; mulsidi3 instruction pattern(s). | |
| 3690 | ; | |
| 3691 | ||
| 3692 | (define_expand "mulsidi3" | |
| 3693 | [(set (match_operand:DI 0 "register_operand" "") | |
| 3694 | (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "")) | |
| 3695 | (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))] | |
| 3696 | "!TARGET_64BIT" | |
| 3697 | " | |
| 3698 | { | |
| 3699 | rtx insn; | |
| 3700 | ||
| 3701 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0])); | |
| 3702 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); | |
| 3703 | insn = emit_insn (gen_mulsi_6432 (operands[0], operands[0], operands[2])); | |
| 3704 | ||
| 3705 | REG_NOTES (insn) = | |
| 3706 | gen_rtx_EXPR_LIST (REG_EQUAL, | |
| 3707 | gen_rtx_MULT (DImode, | |
| 3708 | gen_rtx_SIGN_EXTEND (DImode, operands[1]), | |
| 3709 | gen_rtx_SIGN_EXTEND (DImode, operands[2])), | |
| 3710 | REG_NOTES (insn)); | |
| 3711 | DONE; | |
| 3712 | }") | |
| 3713 | ||
| 9db1d521 HP |
3714 | (define_insn "mulsi_6432" |
| 3715 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 3716 | (mult:DI (sign_extend:DI | |
| 4023fb28 | 3717 | (truncate:SI (match_operand:DI 1 "register_operand" "0,0"))) |
| 9db1d521 | 3718 | (sign_extend:DI |
| 4023fb28 | 3719 | (match_operand:SI 2 "nonimmediate_operand" "d,m")))) |
| 9db1d521 HP |
3720 | (clobber (reg:CC 33))] |
| 3721 | "!TARGET_64BIT" | |
| 3722 | "@ | |
| 3723 | mr\\t%0,%2 | |
| 3724 | m\\t%0,%2" | |
| 3725 | [(set_attr "op_type" "RR,RX") | |
| 9db1d521 | 3726 | (set_attr "atype" "reg,mem") |
| f2d3c02a | 3727 | (set_attr "type" "imul")]) |
| 9db1d521 | 3728 | |
| 9db1d521 HP |
3729 | ; |
| 3730 | ; muldf3 instruction pattern(s). | |
| 3731 | ; | |
| 3732 | ||
| 3733 | (define_expand "muldf3" | |
| 3734 | [(parallel | |
| 3735 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 3736 | (mult:DF (match_operand:DF 1 "register_operand" "%0,0") | |
| 4023fb28 | 3737 | (match_operand:DF 2 "general_operand" "f,m"))) |
| 9db1d521 HP |
3738 | (clobber (reg:CC 33))])] |
| 3739 | "TARGET_HARD_FLOAT" | |
| 3740 | "") | |
| 3741 | ||
| 3742 | (define_insn "*muldf3" | |
| 3743 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 3744 | (mult:DF (match_operand:DF 1 "register_operand" "%0,0") | |
| 4023fb28 | 3745 | (match_operand:DF 2 "general_operand" "f,m"))) |
| 9db1d521 HP |
3746 | (clobber (reg:CC 33))] |
| 3747 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 3748 | "@ | |
| 3749 | mdbr\\t%0,%2 | |
| 3750 | mdb\\t%0,%2" | |
| 3751 | [(set_attr "op_type" "RR,RX") | |
| 4023fb28 | 3752 | (set_attr "type" "fmul") |
| 9db1d521 HP |
3753 | (set_attr "atype" "reg,mem")]) |
| 3754 | ||
| 3755 | (define_insn "*muldf3_ibm" | |
| 3756 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 3757 | (mult:DF (match_operand:DF 1 "register_operand" "%0,0") | |
| 4023fb28 | 3758 | (match_operand:DF 2 "general_operand" "f,m"))) |
| 9db1d521 HP |
3759 | (clobber (reg:CC 33))] |
| 3760 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 3761 | "@ | |
| 3762 | mdr\\t%0,%2 | |
| 3763 | md\\t%0,%2" | |
| 3764 | [(set_attr "op_type" "RR,RX") | |
| f2d3c02a | 3765 | (set_attr "type" "fmul") |
| 9db1d521 HP |
3766 | (set_attr "atype" "reg,mem")]) |
| 3767 | ||
| 3768 | ; | |
| 3769 | ; mulsf3 instruction pattern(s). | |
| 3770 | ; | |
| 3771 | ||
| 3772 | (define_expand "mulsf3" | |
| 3773 | [(parallel | |
| 3774 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 3775 | (mult:SF (match_operand:SF 1 "register_operand" "%0,0") | |
| 4023fb28 | 3776 | (match_operand:SF 2 "general_operand" "f,m"))) |
| 9db1d521 HP |
3777 | (clobber (reg:CC 33))])] |
| 3778 | "TARGET_HARD_FLOAT" | |
| 3779 | "") | |
| 3780 | ||
| 3781 | (define_insn "*mulsf3" | |
| 3782 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 3783 | (mult:SF (match_operand:SF 1 "register_operand" "%0,0") | |
| 4023fb28 | 3784 | (match_operand:SF 2 "general_operand" "f,m"))) |
| 9db1d521 HP |
3785 | (clobber (reg:CC 33))] |
| 3786 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 3787 | "@ | |
| 3788 | meebr\\t%0,%2 | |
| 3789 | meeb\\t%0,%2" | |
| 3790 | [(set_attr "op_type" "RR,RX") | |
| f2d3c02a | 3791 | (set_attr "type" "fmul") |
| 9db1d521 HP |
3792 | (set_attr "atype" "reg,mem")]) |
| 3793 | ||
| 3794 | (define_insn "*mulsf3_ibm" | |
| 3795 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 3796 | (mult:SF (match_operand:SF 1 "register_operand" "%0,0") | |
| 4023fb28 | 3797 | (match_operand:SF 2 "general_operand" "f,m"))) |
| 9db1d521 HP |
3798 | (clobber (reg:CC 33))] |
| 3799 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 3800 | "@ | |
| 3801 | mer\\t%0,%2 | |
| 3802 | me\\t%0,%2" | |
| 3803 | [(set_attr "op_type" "RR,RX") | |
| f2d3c02a | 3804 | (set_attr "type" "fmul") |
| 9db1d521 HP |
3805 | (set_attr "atype" "reg,mem")]) |
| 3806 | ||
| 3807 | ||
| 3808 | ;; | |
| 3809 | ;;- Divide and modulo instructions. | |
| 3810 | ;; | |
| 3811 | ||
| 3812 | ; | |
| 4023fb28 | 3813 | ; divmoddi4 instruction pattern(s). |
| 9db1d521 HP |
3814 | ; |
| 3815 | ||
| 4023fb28 UW |
3816 | (define_expand "divmoddi4" |
| 3817 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
| 3818 | (div:DI (match_operand:DI 1 "general_operand" "") | |
| 3819 | (match_operand:DI 2 "general_operand" ""))) | |
| 3820 | (set (match_operand:DI 3 "general_operand" "") | |
| 3821 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
| 3822 | (clobber (match_dup 4))] | |
| 9db1d521 HP |
3823 | "TARGET_64BIT" |
| 3824 | " | |
| 3825 | { | |
| 4023fb28 UW |
3826 | rtx insn, div_equal, mod_equal, equal; |
| 3827 | ||
| 3828 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
| 3829 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
| 3830 | equal = gen_rtx_IOR (TImode, | |
| 3831 | gen_rtx_ZERO_EXTEND (TImode, div_equal), | |
| 3832 | gen_rtx_ASHIFT (TImode, | |
| 3833 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
| 3834 | GEN_INT (64))); | |
| 3835 | ||
| 3836 | operands[4] = gen_reg_rtx(TImode); | |
| 3837 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
| 3838 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); | |
| 3839 | insn = emit_insn (gen_divmodtidi3 (operands[4], operands[4], operands[2])); | |
| 3840 | REG_NOTES (insn) = | |
| 3841 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
| 3842 | ||
| 3843 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
| 3844 | REG_NOTES (insn) = | |
| 3845 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
| 3846 | ||
| 3847 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
| 3848 | REG_NOTES (insn) = | |
| 3849 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
| 9db1d521 | 3850 | |
| 9db1d521 HP |
3851 | DONE; |
| 3852 | }") | |
| 3853 | ||
| 3854 | (define_insn "divmodtidi3" | |
| 4023fb28 UW |
3855 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
| 3856 | (ior:TI | |
| 3857 | (zero_extend:TI | |
| 3858 | (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0")) | |
| 3859 | (match_operand:DI 2 "general_operand" "d,m"))) | |
| 3860 | (ashift:TI | |
| 3861 | (zero_extend:TI | |
| 3862 | (mod:DI (truncate:DI (match_dup 1)) | |
| 3863 | (match_dup 2))) | |
| 3864 | (const_int 64))))] | |
| 9db1d521 HP |
3865 | "TARGET_64BIT" |
| 3866 | "@ | |
| 3867 | dsgr\\t%0,%2 | |
| 3868 | dsg\\t%0,%2" | |
| 3869 | [(set_attr "op_type" "RRE,RXE") | |
| f2d3c02a | 3870 | (set_attr "type" "idiv") |
| 9db1d521 HP |
3871 | (set_attr "atype" "reg,mem")]) |
| 3872 | ||
| 4023fb28 UW |
3873 | (define_insn "divmodtisi3" |
| 3874 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
| 3875 | (ior:TI | |
| 3876 | (zero_extend:TI | |
| 3877 | (div:DI (truncate:DI (match_operand:TI 1 "register_operand" "0,0")) | |
| 3878 | (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m")))) | |
| 3879 | (ashift:TI | |
| 3880 | (zero_extend:TI | |
| 3881 | (mod:DI (truncate:DI (match_dup 1)) | |
| 3882 | (sign_extend:DI (match_dup 2)))) | |
| 3883 | (const_int 64))))] | |
| 9db1d521 | 3884 | "TARGET_64BIT" |
| 4023fb28 UW |
3885 | "@ |
| 3886 | dsgfr\\t%0,%2 | |
| 3887 | dsgf\\t%0,%2" | |
| 3888 | [(set_attr "op_type" "RRE,RXE") | |
| 3889 | (set_attr "type" "idiv") | |
| 3890 | (set_attr "atype" "reg,mem")]) | |
| 9db1d521 | 3891 | |
| 4023fb28 UW |
3892 | ; |
| 3893 | ; udivmoddi4 instruction pattern(s). | |
| 3894 | ; | |
| 9db1d521 | 3895 | |
| 4023fb28 UW |
3896 | (define_expand "udivmoddi4" |
| 3897 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
| 3898 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
| 3899 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
| 3900 | (set (match_operand:DI 3 "general_operand" "") | |
| 3901 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
| 3902 | (clobber (match_dup 4))] | |
| 9db1d521 HP |
3903 | "TARGET_64BIT" |
| 3904 | " | |
| 3905 | { | |
| 4023fb28 UW |
3906 | rtx insn, div_equal, mod_equal, equal; |
| 3907 | ||
| 3908 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
| 3909 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
| 3910 | equal = gen_rtx_IOR (TImode, | |
| 3911 | gen_rtx_ZERO_EXTEND (TImode, div_equal), | |
| 3912 | gen_rtx_ASHIFT (TImode, | |
| 3913 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
| 3914 | GEN_INT (64))); | |
| 3915 | ||
| 3916 | operands[4] = gen_reg_rtx(TImode); | |
| 3917 | emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4])); | |
| 3918 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); | |
| 3919 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
| 3920 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); | |
| 3921 | REG_NOTES (insn) = | |
| 3922 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
| 3923 | ||
| 3924 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
| 3925 | REG_NOTES (insn) = | |
| 3926 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
| 3927 | ||
| 3928 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
| 3929 | REG_NOTES (insn) = | |
| 3930 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
| 9db1d521 | 3931 | |
| 9db1d521 HP |
3932 | DONE; |
| 3933 | }") | |
| 3934 | ||
| 3935 | (define_insn "udivmodtidi3" | |
| 4023fb28 UW |
3936 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
| 3937 | (ior:TI (zero_extend:TI | |
| 3938 | (truncate:DI | |
| 3939 | (udiv:TI (match_operand:TI 1 "register_operand" "0,0") | |
| 3940 | (zero_extend:TI | |
| 3941 | (match_operand:DI 2 "nonimmediate_operand" "d,m"))))) | |
| 3942 | (ashift:TI | |
| 3943 | (zero_extend:TI | |
| 3944 | (truncate:DI | |
| 3945 | (umod:TI (match_dup 1) (zero_extend:TI (match_dup 2))))) | |
| 3946 | (const_int 64))))] | |
| 9db1d521 HP |
3947 | "TARGET_64BIT" |
| 3948 | "@ | |
| 3949 | dlgr\\t%0,%2 | |
| 3950 | dlg\\t%0,%2" | |
| 3951 | [(set_attr "op_type" "RRE,RXE") | |
| f2d3c02a | 3952 | (set_attr "type" "idiv") |
| 9db1d521 HP |
3953 | (set_attr "atype" "reg,mem")]) |
| 3954 | ||
| 3955 | ; | |
| 4023fb28 | 3956 | ; divmodsi4 instruction pattern(s). |
| 9db1d521 HP |
3957 | ; |
| 3958 | ||
| 4023fb28 UW |
3959 | (define_expand "divmodsi4" |
| 3960 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
| 3961 | (div:SI (match_operand:SI 1 "general_operand" "") | |
| 3962 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
| 3963 | (set (match_operand:SI 3 "general_operand" "") | |
| 3964 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
| 3965 | (clobber (match_dup 4))] | |
| 9db1d521 HP |
3966 | "!TARGET_64BIT" |
| 3967 | " | |
| 3968 | { | |
| 4023fb28 UW |
3969 | rtx insn, div_equal, mod_equal, equal; |
| 3970 | ||
| 3971 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
| 3972 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
| 3973 | equal = gen_rtx_IOR (DImode, | |
| 3974 | gen_rtx_ZERO_EXTEND (DImode, div_equal), | |
| 3975 | gen_rtx_ASHIFT (DImode, | |
| 3976 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
| 3977 | GEN_INT (32))); | |
| 3978 | ||
| 3979 | operands[4] = gen_reg_rtx(DImode); | |
| 3980 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
| 3981 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); | |
| 3982 | REG_NOTES (insn) = | |
| 3983 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
| 3984 | ||
| 3985 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
| 3986 | REG_NOTES (insn) = | |
| 3987 | gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn)); | |
| 3988 | ||
| 3989 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
| 3990 | REG_NOTES (insn) = | |
| 3991 | gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn)); | |
| 9db1d521 | 3992 | |
| 9db1d521 HP |
3993 | DONE; |
| 3994 | }") | |
| 3995 | ||
| 3996 | (define_insn "divmoddisi3" | |
| 4023fb28 UW |
3997 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
| 3998 | (ior:DI (zero_extend:DI | |
| 3999 | (truncate:SI | |
| 4000 | (div:DI (match_operand:DI 1 "register_operand" "0,0") | |
| 4001 | (sign_extend:DI | |
| 4002 | (match_operand:SI 2 "nonimmediate_operand" "d,m"))))) | |
| 4003 | (ashift:DI | |
| 4004 | (zero_extend:DI | |
| 4005 | (truncate:SI | |
| 4006 | (mod:DI (match_dup 1) (sign_extend:SI (match_dup 2))))) | |
| 4007 | (const_int 32))))] | |
| 9db1d521 HP |
4008 | "!TARGET_64BIT" |
| 4009 | "@ | |
| 4010 | dr\\t%0,%2 | |
| 4011 | d\\t%0,%2" | |
| 4012 | [(set_attr "op_type" "RR,RX") | |
| f2d3c02a | 4013 | (set_attr "type" "idiv") |
| 9db1d521 HP |
4014 | (set_attr "atype" "reg,mem")]) |
| 4015 | ||
| 4016 | ; | |
| 4017 | ; udivsi3 and umodsi3 instruction pattern(s). | |
| 4018 | ; | |
| 4019 | ||
| 4023fb28 | 4020 | |
| 9db1d521 HP |
4021 | (define_expand "udivsi3" |
| 4022 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 4023 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
| 4023fb28 UW |
4024 | (match_operand:SI 2 "general_operand" ""))) |
| 4025 | (clobber (match_dup 3))] | |
| 9db1d521 HP |
4026 | "!TARGET_64BIT" |
| 4027 | " | |
| 4028 | { | |
| 4023fb28 UW |
4029 | rtx insn, udiv_equal, umod_equal, equal; |
| 4030 | ||
| 4031 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
| 4032 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
| 4033 | equal = gen_rtx_IOR (DImode, | |
| 4034 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal), | |
| 4035 | gen_rtx_ASHIFT (DImode, | |
| 4036 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
| 4037 | GEN_INT (32))); | |
| 9db1d521 | 4038 | |
| 4023fb28 | 4039 | operands[3] = gen_reg_rtx (DImode); |
| 9db1d521 HP |
4040 | |
| 4041 | if (CONSTANT_P (operands[2])) | |
| 4042 | { | |
| 4043 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
| 4044 | { | |
| 4045 | rtx label1 = gen_label_rtx (); | |
| 4046 | ||
| 4023fb28 UW |
4047 | operands[1] = make_safe_from (operands[1], operands[0]); |
| 4048 | emit_move_insn (operands[0], const0_rtx); | |
| 4049 | emit_insn (gen_cmpsi (operands[1], operands[2])); | |
| 9db1d521 | 4050 | emit_jump_insn (gen_bltu (label1)); |
| 4023fb28 | 4051 | emit_move_insn (operands[0], const1_rtx); |
| 9db1d521 HP |
4052 | emit_label (label1); |
| 4053 | } | |
| 4054 | else | |
| 4055 | { | |
| 4023fb28 UW |
4056 | operands[2] = force_reg (SImode, operands[2]); |
| 4057 | operands[2] = make_safe_from (operands[2], operands[0]); | |
| 4058 | ||
| 4059 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
| 4060 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
| 4061 | operands[2])); | |
| 4062 | REG_NOTES (insn) = | |
| 4063 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
| 4064 | ||
| 4065 | insn = emit_move_insn (operands[0], | |
| 4066 | gen_lowpart (SImode, operands[3])); | |
| 4067 | REG_NOTES (insn) = | |
| 4068 | gen_rtx_EXPR_LIST (REG_EQUAL, | |
| 4069 | udiv_equal, REG_NOTES (insn)); | |
| 9db1d521 HP |
4070 | } |
| 4071 | } | |
| 4072 | else | |
| 4073 | { | |
| 4074 | rtx label1 = gen_label_rtx (); | |
| 4075 | rtx label2 = gen_label_rtx (); | |
| 4076 | rtx label3 = gen_label_rtx (); | |
| 4077 | ||
| 4078 | operands[1] = force_reg (SImode, operands[1]); | |
| 4023fb28 | 4079 | operands[1] = make_safe_from (operands[1], operands[0]); |
| 9db1d521 | 4080 | operands[2] = force_reg (SImode, operands[2]); |
| 4023fb28 UW |
4081 | operands[2] = make_safe_from (operands[2], operands[0]); |
| 4082 | ||
| 4083 | emit_move_insn (operands[0], const0_rtx); | |
| 9db1d521 HP |
4084 | emit_insn (gen_cmpsi (operands[2], operands[1])); |
| 4085 | emit_jump_insn (gen_bgtu (label3)); | |
| 4086 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
| 4087 | emit_jump_insn (gen_blt (label2)); | |
| 4088 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
| 4089 | emit_jump_insn (gen_beq (label1)); | |
| 4023fb28 UW |
4090 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
| 4091 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
| 4092 | operands[2])); | |
| 4093 | REG_NOTES (insn) = | |
| 4094 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
| 4095 | ||
| 4096 | insn = emit_move_insn (operands[0], | |
| 4097 | gen_lowpart (SImode, operands[3])); | |
| 4098 | REG_NOTES (insn) = | |
| 4099 | gen_rtx_EXPR_LIST (REG_EQUAL, | |
| 4100 | udiv_equal, REG_NOTES (insn)); | |
| f314b9b1 | 4101 | emit_jump (label3); |
| 9db1d521 | 4102 | emit_label (label1); |
| 4023fb28 | 4103 | emit_move_insn (operands[0], operands[1]); |
| f314b9b1 | 4104 | emit_jump (label3); |
| 9db1d521 | 4105 | emit_label (label2); |
| 4023fb28 | 4106 | emit_move_insn (operands[0], const1_rtx); |
| 9db1d521 HP |
4107 | emit_label (label3); |
| 4108 | } | |
| 4023fb28 | 4109 | emit_move_insn (operands[0], operands[0]); |
| 9db1d521 HP |
4110 | DONE; |
| 4111 | }") | |
| 4112 | ||
| 4113 | (define_expand "umodsi3" | |
| 4114 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 4115 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
| 4023fb28 UW |
4116 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
| 4117 | (clobber (match_dup 3))] | |
| 9db1d521 HP |
4118 | "!TARGET_64BIT" |
| 4119 | " | |
| 4120 | { | |
| 4023fb28 UW |
4121 | rtx insn, udiv_equal, umod_equal, equal; |
| 4122 | ||
| 4123 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
| 4124 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
| 4125 | equal = gen_rtx_IOR (DImode, | |
| 4126 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal), | |
| 4127 | gen_rtx_ASHIFT (DImode, | |
| 4128 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
| 4129 | GEN_INT (32))); | |
| 9db1d521 | 4130 | |
| 4023fb28 | 4131 | operands[3] = gen_reg_rtx (DImode); |
| 9db1d521 HP |
4132 | |
| 4133 | if (CONSTANT_P (operands[2])) | |
| 4134 | { | |
| 4135 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
| 4136 | { | |
| 4137 | rtx label1 = gen_label_rtx (); | |
| 4138 | ||
| 4023fb28 UW |
4139 | operands[1] = make_safe_from (operands[1], operands[0]); |
| 4140 | emit_move_insn (operands[0], operands[1]); | |
| 4141 | emit_insn (gen_cmpsi (operands[0], operands[2])); | |
| 9db1d521 | 4142 | emit_jump_insn (gen_bltu (label1)); |
| 4023fb28 UW |
4143 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
| 4144 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
| 9db1d521 HP |
4145 | emit_label (label1); |
| 4146 | } | |
| 4147 | else | |
| 4148 | { | |
| 4023fb28 UW |
4149 | operands[2] = force_reg (SImode, operands[2]); |
| 4150 | operands[2] = make_safe_from (operands[2], operands[0]); | |
| 4151 | ||
| 4152 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
| 4153 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
| 4154 | operands[2])); | |
| 4155 | REG_NOTES (insn) = | |
| 4156 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
| 4157 | ||
| 4158 | insn = emit_move_insn (operands[0], | |
| 4159 | gen_highpart (SImode, operands[3])); | |
| 4160 | REG_NOTES (insn) = | |
| 4161 | gen_rtx_EXPR_LIST (REG_EQUAL, | |
| 4162 | umod_equal, REG_NOTES (insn)); | |
| 9db1d521 HP |
4163 | } |
| 4164 | } | |
| 4165 | else | |
| 4166 | { | |
| 4167 | rtx label1 = gen_label_rtx (); | |
| 4168 | rtx label2 = gen_label_rtx (); | |
| 4169 | rtx label3 = gen_label_rtx (); | |
| 4170 | ||
| 4171 | operands[1] = force_reg (SImode, operands[1]); | |
| 4023fb28 | 4172 | operands[1] = make_safe_from (operands[1], operands[0]); |
| 9db1d521 | 4173 | operands[2] = force_reg (SImode, operands[2]); |
| 4023fb28 | 4174 | operands[2] = make_safe_from (operands[2], operands[0]); |
| 9db1d521 | 4175 | |
| 4023fb28 UW |
4176 | emit_move_insn(operands[0], operands[1]); |
| 4177 | emit_insn (gen_cmpsi (operands[2], operands[1])); | |
| 9db1d521 HP |
4178 | emit_jump_insn (gen_bgtu (label3)); |
| 4179 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
| 4180 | emit_jump_insn (gen_blt (label2)); | |
| 4181 | emit_insn (gen_cmpsi (operands[2], const1_rtx)); | |
| 4182 | emit_jump_insn (gen_beq (label1)); | |
| 4023fb28 UW |
4183 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
| 4184 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
| 4185 | operands[2])); | |
| 4186 | REG_NOTES (insn) = | |
| 4187 | gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn)); | |
| 4188 | ||
| 4189 | insn = emit_move_insn (operands[0], | |
| 4190 | gen_highpart (SImode, operands[3])); | |
| 4191 | REG_NOTES (insn) = | |
| 4192 | gen_rtx_EXPR_LIST (REG_EQUAL, | |
| 4193 | umod_equal, REG_NOTES (insn)); | |
| f314b9b1 | 4194 | emit_jump (label3); |
| 9db1d521 | 4195 | emit_label (label1); |
| 4023fb28 | 4196 | emit_move_insn (operands[0], const0_rtx); |
| f314b9b1 | 4197 | emit_jump (label3); |
| 9db1d521 | 4198 | emit_label (label2); |
| 4023fb28 | 4199 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
| 9db1d521 HP |
4200 | emit_label (label3); |
| 4201 | } | |
| 9db1d521 HP |
4202 | DONE; |
| 4203 | }") | |
| 4204 | ||
| 4205 | ; | |
| 4206 | ; divdf3 instruction pattern(s). | |
| 4207 | ; | |
| 4208 | ||
| 4209 | (define_expand "divdf3" | |
| 4210 | [(parallel | |
| 4023fb28 UW |
4211 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
| 4212 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
| 4213 | (match_operand:DF 2 "general_operand" "f,m"))) | |
| 9db1d521 HP |
4214 | (clobber (reg:CC 33))])] |
| 4215 | "TARGET_HARD_FLOAT" | |
| 4216 | "") | |
| 4217 | ||
| 4218 | (define_insn "*divdf3" | |
| 4023fb28 UW |
4219 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
| 4220 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
| 4221 | (match_operand:DF 2 "general_operand" "f,m"))) | |
| 9db1d521 HP |
4222 | (clobber (reg:CC 33))] |
| 4223 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 4224 | "@ | |
| 4225 | ddbr\\t%0,%2 | |
| 4226 | ddb\\t%0,%2" | |
| 4227 | [(set_attr "op_type" "RR,RX") | |
| 4023fb28 | 4228 | (set_attr "type" "fdiv") |
| 9db1d521 HP |
4229 | (set_attr "atype" "reg,mem")]) |
| 4230 | ||
| 4231 | (define_insn "*divdf3_ibm" | |
| 4023fb28 UW |
4232 | [(set (match_operand:DF 0 "register_operand" "=f,f") |
| 4233 | (div:DF (match_operand:DF 1 "register_operand" "0,0") | |
| 4234 | (match_operand:DF 2 "general_operand" "f,m"))) | |
| 9db1d521 HP |
4235 | (clobber (reg:CC 33))] |
| 4236 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 4237 | "@ | |
| 4238 | ddr\\t%0,%2 | |
| 4239 | dd\\t%0,%2" | |
| 4240 | [(set_attr "op_type" "RR,RX") | |
| 4023fb28 | 4241 | (set_attr "type" "fdiv") |
| 9db1d521 HP |
4242 | (set_attr "atype" "reg,mem")]) |
| 4243 | ||
| 4244 | ; | |
| 4245 | ; divsf3 instruction pattern(s). | |
| 4246 | ; | |
| 4247 | ||
| 4248 | (define_expand "divsf3" | |
| 4249 | [(parallel | |
| 4023fb28 UW |
4250 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
| 4251 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
| 4252 | (match_operand:SF 2 "general_operand" "f,m"))) | |
| 9db1d521 HP |
4253 | (clobber (reg:CC 33))])] |
| 4254 | "TARGET_HARD_FLOAT" | |
| 4255 | "") | |
| 4256 | ||
| 4257 | (define_insn "*divsf3" | |
| 4023fb28 UW |
4258 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
| 4259 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
| 4260 | (match_operand:SF 2 "general_operand" "f,m"))) | |
| 9db1d521 HP |
4261 | (clobber (reg:CC 33))] |
| 4262 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 4263 | "@ | |
| 4264 | debr\\t%0,%2 | |
| 4265 | deb\\t%0,%2" | |
| 4266 | [(set_attr "op_type" "RR,RX") | |
| f2d3c02a | 4267 | (set_attr "type" "fdiv") |
| 9db1d521 HP |
4268 | (set_attr "atype" "reg,mem")]) |
| 4269 | ||
| 4270 | (define_insn "*divsf3" | |
| 4023fb28 UW |
4271 | [(set (match_operand:SF 0 "register_operand" "=f,f") |
| 4272 | (div:SF (match_operand:SF 1 "register_operand" "0,0") | |
| 4273 | (match_operand:SF 2 "general_operand" "f,m"))) | |
| 9db1d521 HP |
4274 | (clobber (reg:CC 33))] |
| 4275 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 4276 | "@ | |
| 4277 | der\\t%0,%2 | |
| 4278 | de\\t%0,%2" | |
| 4279 | [(set_attr "op_type" "RR,RX") | |
| f2d3c02a | 4280 | (set_attr "type" "fdiv") |
| 9db1d521 HP |
4281 | (set_attr "atype" "reg,mem")]) |
| 4282 | ||
| 4283 | ||
| 4284 | ;; | |
| 4285 | ;;- And instructions. | |
| 4286 | ;; | |
| 4287 | ||
| 4288 | ; | |
| 4289 | ; anddi3 instruction pattern(s). | |
| 4290 | ; | |
| 4291 | ||
| 4292 | (define_insn "*anddi3_cc" | |
| 4293 | [(set (reg 33) | |
| 4023fb28 UW |
4294 | (compare (and:DI (match_operand:DI 1 "register_operand" "%0,0") |
| 4295 | (match_operand:DI 2 "general_operand" "d,m")) | |
| 9db1d521 | 4296 | (const_int 0))) |
| 4023fb28 | 4297 | (set (match_operand:DI 0 "register_operand" "=d,d") |
| 9db1d521 HP |
4298 | (and:DI (match_dup 1) (match_dup 2)))] |
| 4299 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
| 4300 | "@ | |
| 4301 | ngr\\t%0,%2 | |
| 4023fb28 UW |
4302 | ng\\t%0,%2" |
| 4303 | [(set_attr "op_type" "RRE,RXE") | |
| 4304 | (set_attr "atype" "reg,mem")]) | |
| 9db1d521 HP |
4305 | |
| 4306 | (define_insn "*anddi3_cconly" | |
| 4307 | [(set (reg 33) | |
| 4308 | (compare (and:DI (match_operand:DI 1 "register_operand" "%0,0") | |
| 4023fb28 | 4309 | (match_operand:DI 2 "general_operand" "d,m")) |
| 9db1d521 HP |
4310 | (const_int 0))) |
| 4311 | (clobber (match_scratch:DI 0 "=d,d"))] | |
| 4312 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
| 4313 | "@ | |
| 4314 | ngr\\t%0,%2 | |
| 4315 | ng\\t%0,%2" | |
| 4023fb28 | 4316 | [(set_attr "op_type" "RRE,RXE") |
| f2d3c02a | 4317 | (set_attr "atype" "reg,mem")]) |
| 9db1d521 | 4318 | |
| 4023fb28 UW |
4319 | (define_insn "*anddi3_ni" |
| 4320 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 4321 | (and:DI (match_operand:DI 1 "register_operand" "%0") | |
| 4322 | (match_operand:DI 2 "immediate_operand" "n"))) | |
| 4323 | (clobber (reg:CC 33))] | |
| 4324 | "TARGET_64BIT && s390_single_hi (operands[2], DImode, -1) >= 0" | |
| 4325 | "* | |
| 4326 | { | |
| 4327 | int part = s390_single_hi (operands[2], DImode, -1); | |
| 4328 | operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part)); | |
| 4329 | ||
| 4330 | switch (part) | |
| 4331 | { | |
| 4332 | case 0: return \"nihh\\t%0,%x2\"; | |
| 4333 | case 1: return \"nihl\\t%0,%x2\"; | |
| 4334 | case 2: return \"nilh\\t%0,%x2\"; | |
| 4335 | case 3: return \"nill\\t%0,%x2\"; | |
| 4336 | default: abort (); | |
| 4337 | } | |
| 4338 | }" | |
| 4339 | [(set_attr "op_type" "RI") | |
| 4340 | (set_attr "atype" "reg")]) | |
| 4341 | ||
| 9db1d521 | 4342 | (define_insn "anddi3" |
| 4023fb28 UW |
4343 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
| 4344 | (and:DI (match_operand:DI 1 "register_operand" "%0,0") | |
| 4345 | (match_operand:DI 2 "general_operand" "d,m"))) | |
| 9db1d521 HP |
4346 | (clobber (reg:CC 33))] |
| 4347 | "TARGET_64BIT" | |
| 4348 | "@ | |
| 4349 | ngr\\t%0,%2 | |
| 4023fb28 UW |
4350 | ng\\t%0,%2" |
| 4351 | [(set_attr "op_type" "RRE,RXE") | |
| 4352 | (set_attr "atype" "reg,mem")]) | |
| 4353 | ||
| 4354 | (define_insn "*anddi3_ss" | |
| 4355 | [(set (match_operand:DI 0 "s_operand" "=Qo") | |
| 4356 | (and:DI (match_dup 0) | |
| 4357 | (match_operand:DI 1 "s_imm_operand" "Qo"))) | |
| 4358 | (clobber (reg:CC 33))] | |
| 4359 | "" | |
| 4360 | "nc\\t%O0(8,%R0),%1" | |
| 4361 | [(set_attr "op_type" "SS") | |
| 4362 | (set_attr "atype" "mem")]) | |
| 4363 | ||
| 4364 | (define_insn "*anddi3_ss_inv" | |
| 4365 | [(set (match_operand:DI 0 "s_operand" "=Qo") | |
| 4366 | (and:DI (match_operand:DI 1 "s_imm_operand" "Qo") | |
| 4367 | (match_dup 0))) | |
| 4368 | (clobber (reg:CC 33))] | |
| 4369 | "" | |
| 4370 | "nc\\t%O0(8,%R0),%1" | |
| 4371 | [(set_attr "op_type" "SS") | |
| 4372 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
4373 | |
| 4374 | ; | |
| 4375 | ; andsi3 instruction pattern(s). | |
| 4376 | ; | |
| 4377 | ||
| 4378 | (define_insn "*andsi3_cc" | |
| 4379 | [(set (reg 33) | |
| 4023fb28 UW |
4380 | (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0") |
| 4381 | (match_operand:SI 2 "general_operand" "d,m")) | |
| 9db1d521 | 4382 | (const_int 0))) |
| 4023fb28 | 4383 | (set (match_operand:SI 0 "register_operand" "=d,d") |
| 9db1d521 HP |
4384 | (and:SI (match_dup 1) (match_dup 2)))] |
| 4385 | "s390_match_ccmode(insn, CCTmode)" | |
| 4386 | "@ | |
| 4387 | nr\\t%0,%2 | |
| 4023fb28 UW |
4388 | n\\t%0,%2" |
| 4389 | [(set_attr "op_type" "RR,RX") | |
| 4390 | (set_attr "atype" "reg,mem")]) | |
| 9db1d521 HP |
4391 | |
| 4392 | (define_insn "*andsi3_cconly" | |
| 4393 | [(set (reg 33) | |
| 4394 | (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0") | |
| 4023fb28 | 4395 | (match_operand:SI 2 "general_operand" "d,m")) |
| 9db1d521 HP |
4396 | (const_int 0))) |
| 4397 | (clobber (match_scratch:SI 0 "=d,d"))] | |
| 4398 | "s390_match_ccmode(insn, CCTmode)" | |
| 4399 | "@ | |
| 4400 | nr\\t%0,%2 | |
| 4401 | n\\t%0,%2" | |
| 4402 | [(set_attr "op_type" "RR,RX") | |
| f2d3c02a | 4403 | (set_attr "atype" "reg,mem")]) |
| 9db1d521 | 4404 | |
| 4023fb28 UW |
4405 | (define_insn "*andsi3_ni" |
| 4406 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 4407 | (and:SI (match_operand:SI 1 "register_operand" "%0") | |
| 4408 | (match_operand:SI 2 "immediate_operand" "n"))) | |
| 4409 | (clobber (reg:CC 33))] | |
| 4410 | "TARGET_64BIT && s390_single_hi (operands[2], SImode, -1) >= 0" | |
| 4411 | "* | |
| 4412 | { | |
| 4413 | int part = s390_single_hi (operands[2], SImode, -1); | |
| 4414 | operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part)); | |
| 4415 | ||
| 4416 | switch (part) | |
| 4417 | { | |
| 4418 | case 0: return \"nilh\\t%0,%x2\"; | |
| 4419 | case 1: return \"nill\\t%0,%x2\"; | |
| 4420 | default: abort (); | |
| 4421 | } | |
| 4422 | }" | |
| 4423 | [(set_attr "op_type" "RI") | |
| 4424 | (set_attr "atype" "reg")]) | |
| 4425 | ||
| 9db1d521 | 4426 | (define_insn "andsi3" |
| 4023fb28 UW |
4427 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
| 4428 | (and:SI (match_operand:SI 1 "register_operand" "%0,0") | |
| 4429 | (match_operand:SI 2 "general_operand" "d,m"))) | |
| 9db1d521 HP |
4430 | (clobber (reg:CC 33))] |
| 4431 | "" | |
| 4432 | "@ | |
| 4433 | nr\\t%0,%2 | |
| 4023fb28 UW |
4434 | n\\t%0,%2" |
| 4435 | [(set_attr "op_type" "RR,RX") | |
| 4436 | (set_attr "atype" "reg,mem")]) | |
| 4437 | ||
| 4438 | (define_insn "*andsi3_ss" | |
| 4439 | [(set (match_operand:SI 0 "s_operand" "=Qo") | |
| 4440 | (and:SI (match_dup 0) | |
| 4441 | (match_operand:SI 1 "s_imm_operand" "Qo"))) | |
| 4442 | (clobber (reg:CC 33))] | |
| 4443 | "" | |
| 4444 | "nc\\t%O0(4,%R0),%1" | |
| 4445 | [(set_attr "op_type" "SS") | |
| 4446 | (set_attr "atype" "mem")]) | |
| 4447 | ||
| 4448 | (define_insn "*andsi3_ss_inv" | |
| 4449 | [(set (match_operand:SI 0 "s_operand" "=Qo") | |
| 4450 | (and:SI (match_operand:SI 1 "s_imm_operand" "Qo") | |
| 4451 | (match_dup 0))) | |
| 4452 | (clobber (reg:CC 33))] | |
| 4453 | "" | |
| 4454 | "nc\\t%O0(4,%R0),%1" | |
| 4455 | [(set_attr "op_type" "SS") | |
| 4456 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
4457 | |
| 4458 | ; | |
| 4459 | ; andhi3 instruction pattern(s). | |
| 4460 | ; | |
| 4461 | ||
| 4023fb28 UW |
4462 | (define_insn "*andhi3_ni" |
| 4463 | [(set (match_operand:HI 0 "register_operand" "=d,d") | |
| 4464 | (and:HI (match_operand:HI 1 "register_operand" "%0,0") | |
| 4465 | (match_operand:HI 2 "nonmemory_operand" "d,n"))) | |
| 4466 | (clobber (reg:CC 33))] | |
| 4467 | "TARGET_64BIT" | |
| 4468 | "@ | |
| 4469 | nr\\t%0,%2 | |
| 4470 | nill\\t%0,%x2" | |
| 4471 | [(set_attr "op_type" "RR,RI") | |
| 4472 | (set_attr "atype" "reg")]) | |
| 4473 | ||
| 4474 | (define_insn "andhi3" | |
| 4475 | [(set (match_operand:HI 0 "register_operand" "=d") | |
| 4476 | (and:HI (match_operand:HI 1 "register_operand" "%0") | |
| 4477 | (match_operand:HI 2 "nonmemory_operand" "d"))) | |
| 4478 | (clobber (reg:CC 33))] | |
| 9db1d521 | 4479 | "" |
| 4023fb28 UW |
4480 | "nr\\t%0,%2" |
| 4481 | [(set_attr "op_type" "RR") | |
| 4482 | (set_attr "atype" "reg")]) | |
| 4483 | ||
| 4484 | (define_insn "*andhi3_ss" | |
| 4485 | [(set (match_operand:HI 0 "s_operand" "=Qo") | |
| 4486 | (and:HI (match_dup 0) | |
| 4487 | (match_operand:HI 1 "s_imm_operand" "Qo"))) | |
| 4488 | (clobber (reg:CC 33))] | |
| 4489 | "" | |
| 4490 | "nc\\t%O0(2,%R0),%1" | |
| 4491 | [(set_attr "op_type" "SS") | |
| 4492 | (set_attr "atype" "mem")]) | |
| 9db1d521 | 4493 | |
| 4023fb28 UW |
4494 | (define_insn "*andhi3_ss_inv" |
| 4495 | [(set (match_operand:HI 0 "s_operand" "=Qo") | |
| 4496 | (and:HI (match_operand:HI 1 "s_imm_operand" "Qo") | |
| 4497 | (match_dup 0))) | |
| 9db1d521 HP |
4498 | (clobber (reg:CC 33))] |
| 4499 | "" | |
| 4023fb28 UW |
4500 | "nc\\t%O0(2,%R0),%1" |
| 4501 | [(set_attr "op_type" "SS") | |
| 4502 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
4503 | |
| 4504 | ; | |
| 4505 | ; andqi3 instruction pattern(s). | |
| 4506 | ; | |
| 4507 | ||
| 4023fb28 UW |
4508 | (define_insn "*andqi3_ni" |
| 4509 | [(set (match_operand:QI 0 "register_operand" "=d,d") | |
| 4510 | (and:QI (match_operand:QI 1 "register_operand" "%0,0") | |
| 4511 | (match_operand:QI 2 "nonmemory_operand" "d,n"))) | |
| 4512 | (clobber (reg:CC 33))] | |
| 4513 | "TARGET_64BIT" | |
| 4514 | "@ | |
| 4515 | nr\\t%0,%2 | |
| 4516 | nill\\t%0,%b2" | |
| 4517 | [(set_attr "op_type" "RR,RI") | |
| 4518 | (set_attr "atype" "reg")]) | |
| 4519 | ||
| 9db1d521 | 4520 | (define_insn "andqi3" |
| 4023fb28 UW |
4521 | [(set (match_operand:QI 0 "register_operand" "=d") |
| 4522 | (and:QI (match_operand:QI 1 "register_operand" "%0") | |
| 4523 | (match_operand:QI 2 "nonmemory_operand" "d"))) | |
| 4524 | (clobber (reg:CC 33))] | |
| 4525 | "" | |
| 4526 | "nr\\t%0,%2" | |
| 4527 | [(set_attr "op_type" "RR") | |
| 4528 | (set_attr "atype" "reg")]) | |
| 4529 | ||
| 4530 | (define_insn "*andqi3_ss" | |
| 4531 | [(set (match_operand:QI 0 "s_operand" "=Qo,Qo") | |
| 4532 | (and:QI (match_dup 0) | |
| 4533 | (match_operand:QI 1 "s_imm_operand" "n,Qo"))) | |
| 9db1d521 HP |
4534 | (clobber (reg:CC 33))] |
| 4535 | "" | |
| 4536 | "@ | |
| 4023fb28 UW |
4537 | ni\\t%0,%b1 |
| 4538 | nc\\t%O0(1,%R0),%1" | |
| 4539 | [(set_attr "op_type" "SI,SS") | |
| 4540 | (set_attr "atype" "mem")]) | |
| 4541 | ||
| 4542 | (define_insn "*andqi3_ss_inv" | |
| 4543 | [(set (match_operand:QI 0 "s_operand" "=Qo,Qo") | |
| 4544 | (and:QI (match_operand:QI 1 "s_imm_operand" "n,Qo") | |
| 4545 | (match_dup 0))) | |
| 4546 | (clobber (reg:CC 33))] | |
| 4547 | "" | |
| 4548 | "@ | |
| 4549 | ni\\t%0,%b1 | |
| 4550 | nc\\t%O0(1,%R0),%1" | |
| 4551 | [(set_attr "op_type" "SI,SS") | |
| 4552 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
4553 | |
| 4554 | ||
| 4555 | ;; | |
| 4556 | ;;- Bit set (inclusive or) instructions. | |
| 4557 | ;; | |
| 4558 | ||
| 4559 | ; | |
| 4560 | ; iordi3 instruction pattern(s). | |
| 4561 | ; | |
| 4562 | ||
| 4023fb28 UW |
4563 | (define_insn "*iordi3_cc" |
| 4564 | [(set (reg 33) | |
| 4565 | (compare (ior:DI (match_operand:DI 1 "register_operand" "%0,0") | |
| 4566 | (match_operand:DI 2 "general_operand" "d,m")) | |
| 4567 | (const_int 0))) | |
| 4568 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
| 4569 | (ior:DI (match_dup 1) (match_dup 2)))] | |
| 4570 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
| 4571 | "@ | |
| 4572 | ogr\\t%0,%2 | |
| 4573 | og\\t%0,%2" | |
| 4574 | [(set_attr "op_type" "RRE,RXE") | |
| 4575 | (set_attr "atype" "reg,mem")]) | |
| 4576 | ||
| 4577 | (define_insn "*iordi3_cconly" | |
| 4578 | [(set (reg 33) | |
| 4579 | (compare (ior:DI (match_operand:DI 1 "register_operand" "%0,0") | |
| 4580 | (match_operand:DI 2 "general_operand" "d,m")) | |
| 4581 | (const_int 0))) | |
| 4582 | (clobber (match_scratch:DI 0 "=d,d"))] | |
| 4583 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
| 4584 | "@ | |
| 4585 | ogr\\t%0,%2 | |
| 4586 | og\\t%0,%2" | |
| 4587 | [(set_attr "op_type" "RRE,RXE") | |
| 4588 | (set_attr "atype" "reg,mem")]) | |
| 4589 | ||
| 4590 | (define_insn "*iordi3_oi" | |
| 4591 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 4592 | (ior:DI (match_operand:DI 1 "register_operand" "%0") | |
| 4593 | (match_operand:DI 2 "immediate_operand" "n"))) | |
| 4594 | (clobber (reg:CC 33))] | |
| 4595 | "TARGET_64BIT && s390_single_hi (operands[2], DImode, 0) >= 0" | |
| 4596 | "* | |
| 4597 | { | |
| 4598 | int part = s390_single_hi (operands[2], DImode, 0); | |
| 4599 | operands[2] = GEN_INT (s390_extract_hi (operands[2], DImode, part)); | |
| 4600 | ||
| 4601 | switch (part) | |
| 4602 | { | |
| 4603 | case 0: return \"oihh\\t%0,%x2\"; | |
| 4604 | case 1: return \"oihl\\t%0,%x2\"; | |
| 4605 | case 2: return \"oilh\\t%0,%x2\"; | |
| 4606 | case 3: return \"oill\\t%0,%x2\"; | |
| 4607 | default: abort (); | |
| 4608 | } | |
| 4609 | }" | |
| 4610 | [(set_attr "op_type" "RI") | |
| 4611 | (set_attr "atype" "reg")]) | |
| 4612 | ||
| 9db1d521 | 4613 | (define_insn "iordi3" |
| 4023fb28 UW |
4614 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
| 4615 | (ior:DI (match_operand:DI 1 "register_operand" "%0,0") | |
| 4616 | (match_operand:DI 2 "general_operand" "d,m"))) | |
| 9db1d521 HP |
4617 | (clobber (reg:CC 33))] |
| 4618 | "TARGET_64BIT" | |
| 4619 | "@ | |
| 4620 | ogr\\t%0,%2 | |
| 4023fb28 UW |
4621 | og\\t%0,%2" |
| 4622 | [(set_attr "op_type" "RRE,RXE") | |
| 4623 | (set_attr "atype" "reg,mem")]) | |
| 4624 | ||
| 4625 | (define_insn "*iordi3_ss" | |
| 4626 | [(set (match_operand:DI 0 "s_operand" "=Qo") | |
| 4627 | (ior:DI (match_dup 0) | |
| 4628 | (match_operand:DI 1 "s_imm_operand" "Qo"))) | |
| 4629 | (clobber (reg:CC 33))] | |
| 4630 | "" | |
| 4631 | "oc\\t%O0(8,%R0),%1" | |
| 4632 | [(set_attr "op_type" "SS") | |
| 4633 | (set_attr "atype" "mem")]) | |
| 4634 | ||
| 4635 | (define_insn "*iordi3_ss_inv" | |
| 4636 | [(set (match_operand:DI 0 "s_operand" "=Qo") | |
| 4637 | (ior:DI (match_operand:DI 1 "s_imm_operand" "Qo") | |
| 4638 | (match_dup 0))) | |
| 4639 | (clobber (reg:CC 33))] | |
| 4640 | "" | |
| 4641 | "oc\\t%O0(8,%R0),%1" | |
| 4642 | [(set_attr "op_type" "SS") | |
| 4643 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
4644 | |
| 4645 | ; | |
| 4646 | ; iorsi3 instruction pattern(s). | |
| 4647 | ; | |
| 4648 | ||
| 4023fb28 UW |
4649 | (define_insn "*iorsi3_cc" |
| 4650 | [(set (reg 33) | |
| 4651 | (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0") | |
| 4652 | (match_operand:SI 2 "general_operand" "d,m")) | |
| 4653 | (const_int 0))) | |
| 4654 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
| 4655 | (ior:SI (match_dup 1) (match_dup 2)))] | |
| 4656 | "s390_match_ccmode(insn, CCTmode)" | |
| 4657 | "@ | |
| 4658 | or\\t%0,%2 | |
| 4659 | o\\t%0,%2" | |
| 4660 | [(set_attr "op_type" "RR,RX") | |
| 4661 | (set_attr "atype" "reg,mem")]) | |
| 4662 | ||
| 4663 | (define_insn "*iorsi3_cconly" | |
| 4664 | [(set (reg 33) | |
| 4665 | (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0") | |
| 4666 | (match_operand:SI 2 "general_operand" "d,m")) | |
| 4667 | (const_int 0))) | |
| 4668 | (clobber (match_scratch:SI 0 "=d,d"))] | |
| 4669 | "s390_match_ccmode(insn, CCTmode)" | |
| 4670 | "@ | |
| 4671 | or\\t%0,%2 | |
| 4672 | o\\t%0,%2" | |
| 4673 | [(set_attr "op_type" "RR,RX") | |
| 4674 | (set_attr "atype" "reg,mem")]) | |
| 4675 | ||
| 4676 | (define_insn "*iorsi3_oi" | |
| 4677 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 4678 | (ior:SI (match_operand:SI 1 "register_operand" "%0") | |
| 4679 | (match_operand:SI 2 "immediate_operand" "n"))) | |
| 4680 | (clobber (reg:CC 33))] | |
| 4681 | "TARGET_64BIT && s390_single_hi (operands[2], SImode, 0) >= 0" | |
| 4682 | "* | |
| 4683 | { | |
| 4684 | int part = s390_single_hi (operands[2], SImode, 0); | |
| 4685 | operands[2] = GEN_INT (s390_extract_hi (operands[2], SImode, part)); | |
| 4686 | ||
| 4687 | switch (part) | |
| 4688 | { | |
| 4689 | case 0: return \"oilh\\t%0,%x2\"; | |
| 4690 | case 1: return \"oill\\t%0,%x2\"; | |
| 4691 | default: abort (); | |
| 4692 | } | |
| 4693 | }" | |
| 4694 | [(set_attr "op_type" "RI") | |
| 4695 | (set_attr "atype" "reg")]) | |
| 4696 | ||
| 4697 | (define_insn "iorsi3" | |
| 4698 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 4699 | (ior:SI (match_operand:SI 1 "register_operand" "%0,0") | |
| 4700 | (match_operand:SI 2 "general_operand" "d,m"))) | |
| 4701 | (clobber (reg:CC 33))] | |
| 4702 | "" | |
| 4703 | "@ | |
| 4704 | or\\t%0,%2 | |
| 4705 | o\\t%0,%2" | |
| 4706 | [(set_attr "op_type" "RR,RX") | |
| 4707 | (set_attr "atype" "reg,mem")]) | |
| 4708 | ||
| 4709 | (define_insn "*iorsi3_ss" | |
| 4710 | [(set (match_operand:SI 0 "s_operand" "=Qo") | |
| 4711 | (ior:SI (match_dup 0) | |
| 4712 | (match_operand:SI 1 "s_imm_operand" "Qo"))) | |
| 4713 | (clobber (reg:CC 33))] | |
| 4714 | "" | |
| 4715 | "oc\\t%O0(4,%R0),%1" | |
| 4716 | [(set_attr "op_type" "SS") | |
| 4717 | (set_attr "atype" "mem")]) | |
| 4718 | ||
| 4719 | (define_insn "*iorsi3_ss_inv" | |
| 4720 | [(set (match_operand:SI 0 "s_operand" "=Qo") | |
| 4721 | (ior:SI (match_operand:SI 1 "s_imm_operand" "Qo") | |
| 4722 | (match_dup 0))) | |
| 4723 | (clobber (reg:CC 33))] | |
| 4724 | "" | |
| 4725 | "oc\\t%O0(4,%R0),%1" | |
| 4726 | [(set_attr "op_type" "SS") | |
| 4727 | (set_attr "atype" "mem")]) | |
| 4728 | ||
| 4729 | ; | |
| 4730 | ; iorhi3 instruction pattern(s). | |
| 4731 | ; | |
| 4732 | ||
| 4733 | (define_insn "*iorhi3_oi" | |
| 4734 | [(set (match_operand:HI 0 "register_operand" "=d,d") | |
| 4735 | (ior:HI (match_operand:HI 1 "register_operand" "%0,0") | |
| 4736 | (match_operand:HI 2 "nonmemory_operand" "d,n"))) | |
| 4737 | (clobber (reg:CC 33))] | |
| 4738 | "TARGET_64BIT" | |
| 4739 | "@ | |
| 4740 | or\\t%0,%2 | |
| 4741 | oill\\t%0,%x2" | |
| 4742 | [(set_attr "op_type" "RR,RI") | |
| 4743 | (set_attr "atype" "reg")]) | |
| 4744 | ||
| 4745 | (define_insn "iorhi3" | |
| 4746 | [(set (match_operand:HI 0 "register_operand" "=d") | |
| 4747 | (ior:HI (match_operand:HI 1 "register_operand" "%0") | |
| 4748 | (match_operand:HI 2 "nonmemory_operand" "d"))) | |
| 4749 | (clobber (reg:CC 33))] | |
| 9db1d521 | 4750 | "" |
| 4023fb28 UW |
4751 | "or\\t%0,%2" |
| 4752 | [(set_attr "op_type" "RR") | |
| 4753 | (set_attr "atype" "reg")]) | |
| 4754 | ||
| 4755 | (define_insn "*iorhi3_ss" | |
| 4756 | [(set (match_operand:HI 0 "s_operand" "=Qo") | |
| 4757 | (ior:HI (match_dup 0) | |
| 4758 | (match_operand:HI 1 "s_imm_operand" "Qo"))) | |
| 4759 | (clobber (reg:CC 33))] | |
| 4760 | "" | |
| 4761 | "oc\\t%O0(2,%R0),%1" | |
| 4762 | [(set_attr "op_type" "SS") | |
| 4763 | (set_attr "atype" "mem")]) | |
| 9db1d521 | 4764 | |
| 4023fb28 UW |
4765 | (define_insn "*iorhi3_ss_inv" |
| 4766 | [(set (match_operand:HI 0 "s_operand" "=Qo") | |
| 4767 | (ior:HI (match_operand:HI 1 "s_imm_operand" "Qo") | |
| 4768 | (match_dup 0))) | |
| 9db1d521 HP |
4769 | (clobber (reg:CC 33))] |
| 4770 | "" | |
| 4023fb28 UW |
4771 | "oc\\t%O0(2,%R0),%1" |
| 4772 | [(set_attr "op_type" "SS") | |
| 4773 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
4774 | |
| 4775 | ; | |
| 4023fb28 | 4776 | ; iorqi3 instruction pattern(s). |
| 9db1d521 HP |
4777 | ; |
| 4778 | ||
| 4023fb28 UW |
4779 | (define_insn "*iorqi3_oi" |
| 4780 | [(set (match_operand:QI 0 "register_operand" "=d,d") | |
| 4781 | (ior:QI (match_operand:QI 1 "register_operand" "%0,0") | |
| 4782 | (match_operand:QI 2 "nonmemory_operand" "d,n"))) | |
| 4783 | (clobber (reg:CC 33))] | |
| 4784 | "TARGET_64BIT" | |
| 4785 | "@ | |
| 4786 | or\\t%0,%2 | |
| 4787 | oill\\t%0,%b2" | |
| 4788 | [(set_attr "op_type" "RR,RI") | |
| 4789 | (set_attr "atype" "reg")]) | |
| 9db1d521 | 4790 | |
| 4023fb28 UW |
4791 | (define_insn "iorqi3" |
| 4792 | [(set (match_operand:QI 0 "register_operand" "=d") | |
| 4793 | (ior:QI (match_operand:QI 1 "register_operand" "%0") | |
| 4794 | (match_operand:QI 2 "nonmemory_operand" "d"))) | |
| 4795 | (clobber (reg:CC 33))] | |
| 4796 | "" | |
| 4797 | "or\\t%0,%2" | |
| 4798 | [(set_attr "op_type" "RR") | |
| 4799 | (set_attr "atype" "reg")]) | |
| 4800 | ||
| 4801 | (define_insn "*iorqi3_ss" | |
| 4802 | [(set (match_operand:QI 0 "s_operand" "=Qo,Qo") | |
| 4803 | (ior:QI (match_dup 0) | |
| 4804 | (match_operand:QI 1 "s_imm_operand" "n,Qo"))) | |
| 9db1d521 HP |
4805 | (clobber (reg:CC 33))] |
| 4806 | "" | |
| 4807 | "@ | |
| 4023fb28 UW |
4808 | oi\\t%0,%b1 |
| 4809 | oc\\t%O0(1,%R0),%1" | |
| 4810 | [(set_attr "op_type" "SI,SS") | |
| 9db1d521 HP |
4811 | (set_attr "atype" "reg,mem")]) |
| 4812 | ||
| 4023fb28 UW |
4813 | (define_insn "*iorqi3_ss_inv" |
| 4814 | [(set (match_operand:QI 0 "s_operand" "=Qo,Qo") | |
| 4815 | (ior:QI (match_operand:QI 1 "s_imm_operand" "n,Qo") | |
| 4816 | (match_dup 0))) | |
| 9db1d521 HP |
4817 | (clobber (reg:CC 33))] |
| 4818 | "" | |
| 4819 | "@ | |
| 4023fb28 UW |
4820 | oi\\t%0,%b1 |
| 4821 | oc\\t%O0(1,%R0),%1" | |
| 4822 | [(set_attr "op_type" "SI,SS") | |
| 4823 | (set_attr "atype" "reg,mem")]) | |
| 9db1d521 HP |
4824 | |
| 4825 | ||
| 4826 | ;; | |
| 4827 | ;;- Xor instructions. | |
| 4828 | ;; | |
| 4829 | ||
| 4830 | ; | |
| 4831 | ; xordi3 instruction pattern(s). | |
| 4832 | ; | |
| 4833 | ||
| 4023fb28 UW |
4834 | (define_insn "*xordi3_cc" |
| 4835 | [(set (reg 33) | |
| 4836 | (compare (xor:DI (match_operand:DI 1 "register_operand" "%0,0") | |
| 4837 | (match_operand:DI 2 "general_operand" "d,m")) | |
| 4838 | (const_int 0))) | |
| 4839 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
| 4840 | (xor:DI (match_dup 1) (match_dup 2)))] | |
| 4841 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
| 4842 | "@ | |
| 4843 | xgr\\t%0,%2 | |
| 4844 | xg\\t%0,%2" | |
| 4845 | [(set_attr "op_type" "RRE,RXE") | |
| 4846 | (set_attr "atype" "reg,mem")]) | |
| 4847 | ||
| 4848 | (define_insn "*xordi3_cconly" | |
| 4849 | [(set (reg 33) | |
| 4850 | (compare (xor:DI (match_operand:DI 1 "register_operand" "%0,0") | |
| 4851 | (match_operand:DI 2 "general_operand" "d,m")) | |
| 4852 | (const_int 0))) | |
| 4853 | (clobber (match_scratch:DI 0 "=d,d"))] | |
| 4854 | "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT" | |
| 4855 | "@ | |
| 4856 | xgr\\t%0,%2 | |
| 4857 | xr\\t%0,%2" | |
| 4858 | [(set_attr "op_type" "RRE,RXE") | |
| 4859 | (set_attr "atype" "reg,mem")]) | |
| 4860 | ||
| 9db1d521 | 4861 | (define_insn "xordi3" |
| 4023fb28 UW |
4862 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
| 4863 | (xor:DI (match_operand:DI 1 "register_operand" "%0,0") | |
| 4864 | (match_operand:DI 2 "general_operand" "d,m"))) | |
| 9db1d521 HP |
4865 | (clobber (reg:CC 33))] |
| 4866 | "TARGET_64BIT" | |
| 4867 | "@ | |
| 4868 | xgr\\t%0,%2 | |
| 4023fb28 UW |
4869 | xg\\t%0,%2" |
| 4870 | [(set_attr "op_type" "RRE,RXE") | |
| 4871 | (set_attr "atype" "reg,mem")]) | |
| 4872 | ||
| 4873 | (define_insn "*xordi3_ss" | |
| 4874 | [(set (match_operand:DI 0 "s_operand" "=Qo") | |
| 4875 | (xor:DI (match_dup 0) | |
| 4876 | (match_operand:DI 1 "s_imm_operand" "Qo"))) | |
| 4877 | (clobber (reg:CC 33))] | |
| 4878 | "" | |
| 4879 | "xc\\t%O0(8,%R0),%1" | |
| 4880 | [(set_attr "op_type" "SS") | |
| 4881 | (set_attr "atype" "mem")]) | |
| 4882 | ||
| 4883 | (define_insn "*xordi3_ss_inv" | |
| 4884 | [(set (match_operand:DI 0 "s_operand" "=Qo") | |
| 4885 | (xor:DI (match_operand:DI 1 "s_imm_operand" "Qo") | |
| 4886 | (match_dup 0))) | |
| 4887 | (clobber (reg:CC 33))] | |
| 4888 | "" | |
| 4889 | "xc\\t%O0(8,%R0),%1" | |
| 4890 | [(set_attr "op_type" "SS") | |
| 4891 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
4892 | |
| 4893 | ; | |
| 4894 | ; xorsi3 instruction pattern(s). | |
| 4895 | ; | |
| 4896 | ||
| 4023fb28 UW |
4897 | (define_insn "*xorsi3_cc" |
| 4898 | [(set (reg 33) | |
| 4899 | (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0") | |
| 4900 | (match_operand:SI 2 "general_operand" "d,m")) | |
| 4901 | (const_int 0))) | |
| 4902 | (set (match_operand:SI 0 "register_operand" "=d,d") | |
| 4903 | (xor:SI (match_dup 1) (match_dup 2)))] | |
| 4904 | "s390_match_ccmode(insn, CCTmode)" | |
| 4905 | "@ | |
| 4906 | xr\\t%0,%2 | |
| 4907 | x\\t%0,%2" | |
| 4908 | [(set_attr "op_type" "RR,RX") | |
| 4909 | (set_attr "atype" "reg,mem")]) | |
| 4910 | ||
| 4911 | (define_insn "*xorsi3_cconly" | |
| 4912 | [(set (reg 33) | |
| 4913 | (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0") | |
| 4914 | (match_operand:SI 2 "general_operand" "d,m")) | |
| 4915 | (const_int 0))) | |
| 4916 | (clobber (match_scratch:SI 0 "=d,d"))] | |
| 4917 | "s390_match_ccmode(insn, CCTmode)" | |
| 4918 | "@ | |
| 4919 | xr\\t%0,%2 | |
| 4920 | x\\t%0,%2" | |
| 4921 | [(set_attr "op_type" "RR,RX") | |
| 4922 | (set_attr "atype" "reg,mem")]) | |
| 9db1d521 | 4923 | |
| 4023fb28 UW |
4924 | (define_insn "xorsi3" |
| 4925 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 4926 | (xor:SI (match_operand:SI 1 "register_operand" "%0,0") | |
| 4927 | (match_operand:SI 2 "general_operand" "d,m"))) | |
| 9db1d521 HP |
4928 | (clobber (reg:CC 33))] |
| 4929 | "" | |
| 4930 | "@ | |
| 4931 | xr\\t%0,%2 | |
| 4023fb28 UW |
4932 | x\\t%0,%2" |
| 4933 | [(set_attr "op_type" "RR,RX") | |
| 4934 | (set_attr "atype" "reg,mem")]) | |
| 4935 | ||
| 4936 | (define_insn "*xorsi3_ss" | |
| 4937 | [(set (match_operand:SI 0 "s_operand" "=Qo") | |
| 4938 | (xor:SI (match_dup 0) | |
| 4939 | (match_operand:SI 1 "s_imm_operand" "Qo"))) | |
| 4940 | (clobber (reg:CC 33))] | |
| 4941 | "" | |
| 4942 | "xc\\t%O0(4,%R0),%1" | |
| 4943 | [(set_attr "op_type" "SS") | |
| 4944 | (set_attr "atype" "mem")]) | |
| 4945 | ||
| 4946 | (define_insn "*xorsi3_ss_inv" | |
| 4947 | [(set (match_operand:SI 0 "s_operand" "=Qo") | |
| 4948 | (xor:SI (match_operand:SI 1 "s_imm_operand" "Qo") | |
| 4949 | (match_dup 0))) | |
| 4950 | (clobber (reg:CC 33))] | |
| 4951 | "" | |
| 4952 | "xc\\t%O0(4,%R0),%1" | |
| 4953 | [(set_attr "op_type" "SS") | |
| 4954 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
4955 | |
| 4956 | ; | |
| 4957 | ; xorhi3 instruction pattern(s). | |
| 4958 | ; | |
| 4959 | ||
| 4023fb28 UW |
4960 | (define_insn "xorhi3" |
| 4961 | [(set (match_operand:HI 0 "register_operand" "=d") | |
| 4962 | (xor:HI (match_operand:HI 1 "register_operand" "%0") | |
| 4963 | (match_operand:HI 2 "nonmemory_operand" "d"))) | |
| 4964 | (clobber (reg:CC 33))] | |
| 9db1d521 | 4965 | "" |
| 4023fb28 UW |
4966 | "xr\\t%0,%2" |
| 4967 | [(set_attr "op_type" "RR") | |
| 4968 | (set_attr "atype" "reg")]) | |
| 4969 | ||
| 4970 | (define_insn "*xorhi3_ss" | |
| 4971 | [(set (match_operand:HI 0 "s_operand" "=Qo") | |
| 4972 | (xor:HI (match_dup 0) | |
| 4973 | (match_operand:HI 1 "s_imm_operand" "Qo"))) | |
| 4974 | (clobber (reg:CC 33))] | |
| 4975 | "" | |
| 4976 | "xc\\t%O0(2,%R0),%1" | |
| 4977 | [(set_attr "op_type" "SS") | |
| 4978 | (set_attr "atype" "mem")]) | |
| 9db1d521 | 4979 | |
| 4023fb28 UW |
4980 | (define_insn "*xorhi3_ss_inv" |
| 4981 | [(set (match_operand:HI 0 "s_operand" "=Qo") | |
| 4982 | (xor:HI (match_operand:HI 1 "s_imm_operand" "Qo") | |
| 4983 | (match_dup 0))) | |
| 9db1d521 HP |
4984 | (clobber (reg:CC 33))] |
| 4985 | "" | |
| 4023fb28 UW |
4986 | "xc\\t%O0(2,%R0),%1" |
| 4987 | [(set_attr "op_type" "SS") | |
| 4988 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
4989 | |
| 4990 | ; | |
| 4991 | ; xorqi3 instruction pattern(s). | |
| 4992 | ; | |
| 4993 | ||
| 4994 | (define_insn "xorqi3" | |
| 4023fb28 UW |
4995 | [(set (match_operand:QI 0 "register_operand" "=d") |
| 4996 | (xor:QI (match_operand:QI 1 "register_operand" "%0") | |
| 4997 | (match_operand:QI 2 "nonmemory_operand" "d"))) | |
| 4998 | (clobber (reg:CC 33))] | |
| 4999 | "" | |
| 5000 | "xr\\t%0,%2" | |
| 5001 | [(set_attr "op_type" "RR") | |
| 5002 | (set_attr "atype" "reg")]) | |
| 5003 | ||
| 5004 | (define_insn "*xorqi3_ss" | |
| 5005 | [(set (match_operand:QI 0 "s_operand" "=Qo,Qo") | |
| 5006 | (xor:QI (match_dup 0) | |
| 5007 | (match_operand:QI 1 "s_imm_operand" "n,Qo"))) | |
| 9db1d521 HP |
5008 | (clobber (reg:CC 33))] |
| 5009 | "" | |
| 5010 | "@ | |
| 4023fb28 UW |
5011 | xi\\t%0,%b1 |
| 5012 | xc\\t%O0(1,%R0),%1" | |
| 5013 | [(set_attr "op_type" "SI,SS") | |
| 5014 | (set_attr "atype" "mem")]) | |
| 5015 | ||
| 5016 | (define_insn "*xorqi3_ss_inv" | |
| 5017 | [(set (match_operand:QI 0 "s_operand" "=Qo,Qo") | |
| 5018 | (xor:QI (match_operand:QI 1 "s_imm_operand" "n,Qo") | |
| 5019 | (match_dup 0))) | |
| 5020 | (clobber (reg:CC 33))] | |
| 5021 | "" | |
| 5022 | "@ | |
| 5023 | xi\\t%0,%b1 | |
| 5024 | xc\\t%O0(1,%R0),%1" | |
| 5025 | [(set_attr "op_type" "SI,SS") | |
| 5026 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
5027 | |
| 5028 | ||
| 5029 | ;; | |
| 5030 | ;;- Negate instructions. | |
| 5031 | ;; | |
| 5032 | ||
| 5033 | ; | |
| 5034 | ; negdi2 instruction pattern(s). | |
| 5035 | ; | |
| 5036 | ||
| 5037 | (define_expand "negdi2" | |
| 5038 | [(parallel | |
| 5039 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5040 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
| 5041 | (clobber (reg:CC 33))])] | |
| 5042 | "" | |
| 5043 | "") | |
| 5044 | ||
| 5045 | (define_insn "*negdi2_64" | |
| 5046 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5047 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
| 5048 | (clobber (reg:CC 33))] | |
| 5049 | "TARGET_64BIT" | |
| 5050 | "lcgr\\t%0,%1" | |
| f2d3c02a | 5051 | [(set_attr "op_type" "RR")]) |
| 9db1d521 HP |
5052 | |
| 5053 | (define_insn "*negdi2_31" | |
| 5054 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5055 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
| 5056 | (clobber (reg:CC 33))] | |
| 5057 | "!TARGET_64BIT" | |
| 5058 | "* | |
| 5059 | { | |
| 5060 | rtx xop[1]; | |
| 5061 | xop[0] = gen_label_rtx (); | |
| 5062 | output_asm_insn (\"lcr\\t%0,%1\", operands); | |
| 5063 | output_asm_insn (\"lcr\\t%N0,%N1\", operands); | |
| 5064 | output_asm_insn (\"je\\t%l0\", xop); | |
| 5065 | output_asm_insn (\"bctr\\t%0,0\", operands); | |
| 5066 | ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", | |
| 5067 | CODE_LABEL_NUMBER (xop[0])); | |
| 5068 | return \"\"; | |
| 5069 | }" | |
| 5070 | [(set_attr "op_type" "NN") | |
| 4023fb28 UW |
5071 | (set_attr "type" "other") |
| 5072 | (set_attr "length" "10")]) | |
| 9db1d521 HP |
5073 | |
| 5074 | ; | |
| 5075 | ; negsi2 instruction pattern(s). | |
| 5076 | ; | |
| 5077 | ||
| 5078 | (define_insn "negsi2" | |
| 5079 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 5080 | (neg:SI (match_operand:SI 1 "register_operand" "d"))) | |
| 5081 | (clobber (reg:CC 33))] | |
| 5082 | "" | |
| 5083 | "lcr\\t%0,%1" | |
| f2d3c02a | 5084 | [(set_attr "op_type" "RR")]) |
| 9db1d521 HP |
5085 | |
| 5086 | ; | |
| 5087 | ; negdf2 instruction pattern(s). | |
| 5088 | ; | |
| 5089 | ||
| 5090 | (define_expand "negdf2" | |
| 5091 | [(parallel | |
| 5092 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 5093 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
| 5094 | (clobber (reg:CC 33))])] | |
| 5095 | "TARGET_HARD_FLOAT" | |
| 5096 | "") | |
| 5097 | ||
| 5098 | (define_insn "*negdf2" | |
| 5099 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 5100 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
| 5101 | (clobber (reg:CC 33))] | |
| 5102 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 5103 | "lcdbr\\t%0,%1" | |
| 5104 | [(set_attr "op_type" "RR")]) | |
| 5105 | ||
| 5106 | (define_insn "*negdf2_ibm" | |
| 5107 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 5108 | (neg:DF (match_operand:DF 1 "register_operand" "f"))) | |
| 5109 | (clobber (reg:CC 33))] | |
| 5110 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 5111 | "lcdr\\t%0,%1" | |
| 5112 | [(set_attr "op_type" "RR")]) | |
| 5113 | ||
| 5114 | ; | |
| 5115 | ; negsf2 instruction pattern(s). | |
| 5116 | ; | |
| 5117 | ||
| 5118 | (define_expand "negsf2" | |
| 5119 | [(parallel | |
| 5120 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 5121 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
| 5122 | (clobber (reg:CC 33))])] | |
| 5123 | "TARGET_HARD_FLOAT" | |
| 5124 | "") | |
| 5125 | ||
| 5126 | (define_insn "*negsf2" | |
| 5127 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 5128 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
| 5129 | (clobber (reg:CC 33))] | |
| 5130 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 5131 | "lcebr\\t%0,%1" | |
| 5132 | [(set_attr "op_type" "RR")]) | |
| 5133 | ||
| 5134 | (define_insn "*negsf2" | |
| 5135 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 5136 | (neg:SF (match_operand:SF 1 "register_operand" "f"))) | |
| 5137 | (clobber (reg:CC 33))] | |
| 5138 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 5139 | "lcer\\t%0,%1" | |
| 5140 | [(set_attr "op_type" "RR")]) | |
| 5141 | ||
| 5142 | ||
| 5143 | ;; | |
| 5144 | ;;- Absolute value instructions. | |
| 5145 | ;; | |
| 5146 | ||
| 5147 | ; | |
| 5148 | ; absdi2 instruction pattern(s). | |
| 5149 | ; | |
| 5150 | ||
| 5151 | (define_insn "absdi2" | |
| 5152 | [(set (match_operand:DI 0 "register_operand" "=d") | |
| 5153 | (abs:DI (match_operand:DI 1 "register_operand" "d"))) | |
| 5154 | (clobber (reg:CC 33))] | |
| 5155 | "TARGET_64BIT" | |
| 5156 | "lpgr\\t%0,%1" | |
| f2d3c02a | 5157 | [(set_attr "op_type" "RRE")]) |
| 9db1d521 HP |
5158 | |
| 5159 | ; | |
| 5160 | ; abssi2 instruction pattern(s). | |
| 5161 | ; | |
| 5162 | ||
| 5163 | (define_insn "abssi2" | |
| 5164 | [(set (match_operand:SI 0 "register_operand" "=d") | |
| 5165 | (abs:SI (match_operand:SI 1 "register_operand" "d"))) | |
| 5166 | (clobber (reg:CC 33))] | |
| 5167 | "" | |
| 5168 | "lpr\\t%0,%1" | |
| f2d3c02a | 5169 | [(set_attr "op_type" "RR")]) |
| 9db1d521 | 5170 | |
| 9db1d521 HP |
5171 | ; |
| 5172 | ; absdf2 instruction pattern(s). | |
| 5173 | ; | |
| 5174 | ||
| 5175 | (define_expand "absdf2" | |
| 5176 | [(parallel | |
| 5177 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 5178 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
| 5179 | (clobber (reg:CC 33))])] | |
| 5180 | "TARGET_HARD_FLOAT" | |
| 5181 | "") | |
| 5182 | ||
| 5183 | (define_insn "*absdf2" | |
| 5184 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 5185 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
| 5186 | (clobber (reg:CC 33))] | |
| 5187 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 5188 | "lpdbr\\t%0,%1" | |
| 5189 | [(set_attr "op_type" "RR")]) | |
| 5190 | ||
| 5191 | (define_insn "*absdf2_ibm" | |
| 5192 | [(set (match_operand:DF 0 "register_operand" "=f") | |
| 5193 | (abs:DF (match_operand:DF 1 "register_operand" "f"))) | |
| 5194 | (clobber (reg:CC 33))] | |
| 5195 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 5196 | "lpdr\\t%0,%1" | |
| 5197 | [(set_attr "op_type" "RR")]) | |
| 5198 | ||
| 5199 | ; | |
| 5200 | ; abssf2 instruction pattern(s). | |
| 5201 | ; | |
| 5202 | ||
| 5203 | (define_expand "abssf2" | |
| 5204 | [(parallel | |
| 5205 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 5206 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
| 5207 | (clobber (reg:CC 33))])] | |
| 5208 | "TARGET_HARD_FLOAT" | |
| 5209 | "") | |
| 5210 | ||
| 5211 | (define_insn "*abssf2" | |
| 5212 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 5213 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
| 5214 | (clobber (reg:CC 33))] | |
| 5215 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 5216 | "lpebr\\t%0,%1" | |
| 5217 | [(set_attr "op_type" "RR")]) | |
| 5218 | ||
| 5219 | (define_insn "*abssf2_ibm" | |
| 5220 | [(set (match_operand:SF 0 "register_operand" "=f") | |
| 5221 | (abs:SF (match_operand:SF 1 "register_operand" "f"))) | |
| 5222 | (clobber (reg:CC 33))] | |
| 5223 | "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" | |
| 5224 | "lper\\t%0,%1" | |
| 5225 | [(set_attr "op_type" "RR")]) | |
| 5226 | ||
| 4023fb28 UW |
5227 | ;; |
| 5228 | ;;- Square root instructions. | |
| 5229 | ;; | |
| 5230 | ||
| 5231 | ; | |
| 5232 | ; sqrtdf2 instruction pattern(s). | |
| 5233 | ; | |
| 5234 | ||
| 5235 | (define_insn "sqrtdf2" | |
| 5236 | [(set (match_operand:DF 0 "register_operand" "=f,f") | |
| 5237 | (sqrt:DF (match_operand:DF 1 "general_operand" "f,m")))] | |
| 5238 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 5239 | "@ | |
| 5240 | sqdbr\\t%0,%1 | |
| 5241 | sqdb\\t%0,%1" | |
| 5242 | [(set_attr "op_type" "RRE,RSE")]) | |
| 5243 | ||
| 5244 | ; | |
| 5245 | ; sqrtsf2 instruction pattern(s). | |
| 5246 | ; | |
| 5247 | ||
| 5248 | (define_insn "sqrtsf2" | |
| 5249 | [(set (match_operand:SF 0 "register_operand" "=f,f") | |
| 5250 | (sqrt:SF (match_operand:SF 1 "general_operand" "f,m")))] | |
| 5251 | "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" | |
| 5252 | "@ | |
| 5253 | sqebr\\t%0,%1 | |
| 5254 | sqeb\\t%0,%1" | |
| 5255 | [(set_attr "op_type" "RRE,RSE")]) | |
| 9db1d521 HP |
5256 | |
| 5257 | ;; | |
| 5258 | ;;- One complement instructions. | |
| 5259 | ;; | |
| 5260 | ||
| 5261 | ; | |
| 5262 | ; one_cmpldi2 instruction pattern(s). | |
| 5263 | ; | |
| 4023fb28 | 5264 | |
| 9db1d521 HP |
5265 | (define_expand "one_cmpldi2" |
| 5266 | [(parallel | |
| 4023fb28 UW |
5267 | [(set (match_operand:DI 0 "register_operand" "") |
| 5268 | (xor:DI (match_operand:DI 1 "register_operand" "") | |
| 5269 | (const_int -1))) | |
| 9db1d521 HP |
5270 | (clobber (reg:CC 33))])] |
| 5271 | "TARGET_64BIT" | |
| 4023fb28 UW |
5272 | "") |
| 5273 | ||
| 9db1d521 HP |
5274 | ; |
| 5275 | ; one_cmplsi2 instruction pattern(s). | |
| 5276 | ; | |
| 4023fb28 | 5277 | |
| 9db1d521 HP |
5278 | (define_expand "one_cmplsi2" |
| 5279 | [(parallel | |
| 4023fb28 UW |
5280 | [(set (match_operand:SI 0 "register_operand" "") |
| 5281 | (xor:SI (match_operand:SI 1 "register_operand" "") | |
| 5282 | (const_int -1))) | |
| 9db1d521 HP |
5283 | (clobber (reg:CC 33))])] |
| 5284 | "" | |
| 4023fb28 UW |
5285 | "") |
| 5286 | ||
| 9db1d521 HP |
5287 | ; |
| 5288 | ; one_cmplhi2 instruction pattern(s). | |
| 5289 | ; | |
| 4023fb28 | 5290 | |
| 9db1d521 HP |
5291 | (define_expand "one_cmplhi2" |
| 5292 | [(parallel | |
| 4023fb28 UW |
5293 | [(set (match_operand:HI 0 "register_operand" "") |
| 5294 | (xor:HI (match_operand:HI 1 "register_operand" "") | |
| 5295 | (const_int -1))) | |
| 9db1d521 HP |
5296 | (clobber (reg:CC 33))])] |
| 5297 | "" | |
| 4023fb28 UW |
5298 | "") |
| 5299 | ||
| 9db1d521 HP |
5300 | ; |
| 5301 | ; one_cmplqi2 instruction pattern(s). | |
| 5302 | ; | |
| 4023fb28 UW |
5303 | |
| 5304 | (define_expand "one_cmplqi2" | |
| 5305 | [(parallel | |
| 5306 | [(set (match_operand:QI 0 "register_operand" "") | |
| 5307 | (xor:QI (match_operand:QI 1 "register_operand" "") | |
| 5308 | (const_int -1))) | |
| 5309 | (clobber (reg:CC 33))])] | |
| 9db1d521 | 5310 | "" |
| 4023fb28 | 5311 | "") |
| 9db1d521 HP |
5312 | |
| 5313 | ||
| 5314 | ;; | |
| 5315 | ;;- Rotate instructions. | |
| 5316 | ;; | |
| 5317 | ||
| 5318 | ; | |
| 5319 | ; rotldi3 instruction pattern(s). | |
| 5320 | ; | |
| 5321 | ||
| 5322 | (define_insn "rotldi3" | |
| 5323 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 5324 | (rotate:DI (match_operand:DI 1 "register_operand" "d,d") | |
| 5325 | (match_operand:DI 2 "nonmemory_operand" "J,a"))) | |
| 5326 | (clobber (reg:CC 33))] | |
| 5327 | "TARGET_64BIT" | |
| 5328 | "@ | |
| 5329 | rllg\\t%0,%1,%c2 | |
| 5330 | rllg\\t%0,%1,0(%2)" | |
| f2d3c02a | 5331 | [(set_attr "op_type" "RSE")]) |
| 9db1d521 HP |
5332 | |
| 5333 | ; | |
| 5334 | ; rotlsi3 instruction pattern(s). | |
| 5335 | ; | |
| 5336 | ||
| 5337 | (define_insn "rotlsi3" | |
| 5338 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 5339 | (rotate:SI (match_operand:SI 1 "register_operand" "d,d") | |
| 5340 | (match_operand:SI 2 "nonmemory_operand" "J,a"))) | |
| 5341 | (clobber (reg:CC 33))] | |
| 5342 | "TARGET_64BIT" | |
| 5343 | "@ | |
| 5344 | rll\\t%0,%1,%c2 | |
| 5345 | rll\\t%0,%1,0(%2)" | |
| f2d3c02a | 5346 | [(set_attr "op_type" "RSE")]) |
| 9db1d521 HP |
5347 | |
| 5348 | ||
| 5349 | ;; | |
| 5350 | ;;- Arithmetic shift instructions. | |
| 5351 | ;; | |
| 5352 | ;; for left shifts always setal shifts are used (ANSI-C) | |
| 5353 | ||
| 5354 | ; | |
| 5355 | ; ashldi3 instruction pattern(s). | |
| 5356 | ; | |
| 5357 | ||
| 5358 | (define_expand "ashldi3" | |
| 5359 | [(parallel | |
| 5360 | [(set (match_operand:DI 0 "register_operand" "") | |
| 5361 | (ashift:DI (match_operand:DI 1 "register_operand" "") | |
| 5362 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
| 5363 | (clobber (reg:CC 33))])] | |
| 5364 | "" | |
| 5365 | "") | |
| 5366 | ||
| 5367 | (define_insn "*ashldi3_31" | |
| 5368 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 5369 | (ashift:DI (match_operand:DI 1 "register_operand" "0,0") | |
| 5370 | (match_operand:SI 2 "nonmemory_operand" "J,a"))) | |
| 5371 | (clobber (reg:CC 33))] | |
| 5372 | "!TARGET_64BIT" | |
| 5373 | "@ | |
| 5374 | sldl\\t%0,%c2 | |
| 5375 | sldl\\t%0,0(%2)" | |
| f2d3c02a | 5376 | [(set_attr "op_type" "RS")]) |
| 9db1d521 HP |
5377 | |
| 5378 | (define_insn "*ashldi3_64" | |
| 5379 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 5380 | (ashift:DI (match_operand:DI 1 "register_operand" "d,d") | |
| 5381 | (match_operand:SI 2 "nonmemory_operand" "J,a"))) | |
| 5382 | (clobber (reg:CC 33))] | |
| 5383 | "TARGET_64BIT" | |
| 5384 | "@ | |
| 5385 | sllg\\t%0,%1,%2 | |
| 5386 | sllg\\t%0,%1,0(%2)" | |
| f2d3c02a | 5387 | [(set_attr "op_type" "RSE")]) |
| 9db1d521 HP |
5388 | |
| 5389 | ; | |
| 5390 | ; ashrdi3 instruction pattern(s). | |
| 5391 | ; | |
| 5392 | ||
| 5393 | (define_expand "ashrdi3" | |
| 5394 | [(parallel | |
| 5395 | [(set (match_operand:DI 0 "register_operand" "") | |
| 5396 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "") | |
| 5397 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
| 5398 | (clobber (reg:CC 33))])] | |
| 5399 | "" | |
| 5400 | "") | |
| 5401 | ||
| 5402 | (define_insn "*ashrdi3_31" | |
| 5403 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 5404 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0") | |
| 5405 | (match_operand:SI 2 "nonmemory_operand" "J,a"))) | |
| 5406 | (clobber (reg:CC 33))] | |
| 5407 | "!TARGET_64BIT" | |
| 5408 | "@ | |
| 5409 | srda\\t%0,%c2 | |
| 5410 | srda\\t%0,0(%2)" | |
| 5411 | [(set_attr "op_type" "RS")]) | |
| 5412 | ||
| 5413 | (define_insn "*ashrdi3_64" | |
| 5414 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 5415 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "d,d") | |
| 5416 | (match_operand:SI 2 "nonmemory_operand" "J,a"))) | |
| 5417 | (clobber (reg:CC 33))] | |
| 5418 | "TARGET_64BIT" | |
| 5419 | "@ | |
| 5420 | srag\\t%0,%1,%c2 | |
| 5421 | srag\\t%0,%1,0(%2)" | |
| f2d3c02a | 5422 | [(set_attr "op_type" "RSE")]) |
| 9db1d521 HP |
5423 | |
| 5424 | ; | |
| 5425 | ; ashlsi3 instruction pattern(s). | |
| 5426 | ; | |
| 5427 | ; all 32 bits has to be shifted (testcase co750c) | |
| 5428 | ||
| 5429 | (define_insn "ashlsi3" | |
| 5430 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 5431 | (ashift:SI (match_operand:SI 1 "register_operand" "0,0") | |
| 4023fb28 | 5432 | (match_operand:SI 2 "nonmemory_operand" "J,a"))) |
| 9db1d521 HP |
5433 | (clobber (reg:CC 33))] |
| 5434 | "" | |
| 5435 | "@ | |
| 5436 | sll\\t%0,%c2 | |
| 5437 | sll\\t%0,0(%2)" | |
| f2d3c02a | 5438 | [(set_attr "op_type" "RS")]) |
| 9db1d521 HP |
5439 | |
| 5440 | ; | |
| 5441 | ; ashrsi3 instruction pattern(s). | |
| 5442 | ; | |
| 5443 | ||
| 5444 | (define_insn "ashrsi3" | |
| 5445 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 5446 | (ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0") | |
| 4023fb28 | 5447 | (match_operand:SI 2 "nonmemory_operand" "J,a"))) |
| 9db1d521 HP |
5448 | (clobber (reg:CC 33))] |
| 5449 | "" | |
| 5450 | "@ | |
| 5451 | sra\\t%0,%c2 | |
| 5452 | sra\\t%0,0(%2)" | |
| f2d3c02a | 5453 | [(set_attr "op_type" "RS")]) |
| 9db1d521 | 5454 | |
| 9db1d521 HP |
5455 | |
| 5456 | ;; | |
| 5457 | ;;- logical shift instructions. | |
| 5458 | ;; | |
| 5459 | ||
| 5460 | ; | |
| 5461 | ; lshrdi3 instruction pattern(s). | |
| 5462 | ; | |
| 5463 | ||
| 5464 | (define_expand "lshrdi3" | |
| 5465 | [(parallel | |
| 5466 | [(set (match_operand:DI 0 "register_operand" "") | |
| 5467 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "") | |
| 5468 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
| 5469 | (clobber (reg:CC 33))])] | |
| 5470 | "" | |
| 5471 | "") | |
| 5472 | ||
| 5473 | (define_insn "*lshrdi3_31" | |
| 5474 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 5475 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0") | |
| 5476 | (match_operand:SI 2 "nonmemory_operand" "J,a"))) | |
| 5477 | (clobber (reg:CC 33))] | |
| 5478 | "!TARGET_64BIT" | |
| 5479 | "@ | |
| 5480 | srdl\\t%0,%c2 | |
| 5481 | srdl\\t%0,0(%2)" | |
| 5482 | [(set_attr "op_type" "RS,RS")]) | |
| 5483 | ||
| 5484 | (define_insn "*lshrdi3_64" | |
| 5485 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
| 5486 | (lshiftrt:DI (match_operand:DI 1 "register_operand" "d,d") | |
| 5487 | (match_operand:SI 2 "nonmemory_operand" "J,a"))) | |
| 5488 | (clobber (reg:CC 33))] | |
| 5489 | "TARGET_64BIT" | |
| 5490 | "@ | |
| 5491 | srlg\\t%0,%1,%c2 | |
| 5492 | srlg\\t%0,%1,0(%2)" | |
| f2d3c02a | 5493 | [(set_attr "op_type" "RS,RS")]) |
| 9db1d521 HP |
5494 | |
| 5495 | ; | |
| 5496 | ; lshrsi3 instruction pattern(s). | |
| 5497 | ; | |
| 5498 | ||
| 5499 | (define_insn "lshrsi3" | |
| 5500 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
| 5501 | (lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0") | |
| 4023fb28 | 5502 | (match_operand:SI 2 "nonmemory_operand" "J,a"))) |
| 9db1d521 HP |
5503 | (clobber (reg:CC 33))] |
| 5504 | "" | |
| 5505 | "@ | |
| 5506 | srl\\t%0,%c2 | |
| 5507 | srl\\t%0,0(%2)" | |
| f2d3c02a | 5508 | [(set_attr "op_type" "RS")]) |
| 9db1d521 | 5509 | |
| 9db1d521 HP |
5510 | |
| 5511 | ;; | |
| 5512 | ;; Branch instruction patterns. | |
| 5513 | ;; | |
| 5514 | ||
| 5515 | (define_expand "beq" | |
| 5516 | [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2))) | |
| 5517 | (set (pc) | |
| 5518 | (if_then_else (eq (reg:CCZ 33) (const_int 0)) | |
| 5519 | (label_ref (match_operand 0 "" "")) | |
| 5520 | (pc)))] | |
| 5521 | "" | |
| 5522 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
| 5523 | ||
| 5524 | (define_expand "bne" | |
| 5525 | [(set (reg:CCZ 33) (compare:CCZ (match_dup 1) (match_dup 2))) | |
| 5526 | (set (pc) | |
| 5527 | (if_then_else (ne (reg:CCZ 33) (const_int 0)) | |
| 5528 | (label_ref (match_operand 0 "" "")) | |
| 5529 | (pc)))] | |
| 5530 | "" | |
| 5531 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
| 5532 | ||
| 5533 | (define_expand "bgt" | |
| 5534 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
| 5535 | (set (pc) | |
| 5536 | (if_then_else (gt (reg:CCS 33) (const_int 0)) | |
| 5537 | (label_ref (match_operand 0 "" "")) | |
| 5538 | (pc)))] | |
| 5539 | "" | |
| 5540 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
| 5541 | ||
| 5542 | (define_expand "bgtu" | |
| 5543 | [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) | |
| 5544 | (set (pc) | |
| 5545 | (if_then_else (gtu (reg:CCU 33) (const_int 0)) | |
| 5546 | (label_ref (match_operand 0 "" "")) | |
| 5547 | (pc)))] | |
| 5548 | "" | |
| 5549 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
| 5550 | ||
| 5551 | (define_expand "blt" | |
| 5552 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
| 5553 | (set (pc) | |
| 5554 | (if_then_else (lt (reg:CCS 33) (const_int 0)) | |
| 5555 | (label_ref (match_operand 0 "" "")) | |
| 5556 | (pc)))] | |
| 5557 | "" | |
| 5558 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
| 5559 | ||
| 5560 | (define_expand "bltu" | |
| 5561 | [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) | |
| 5562 | (set (pc) | |
| 5563 | (if_then_else (ltu (reg:CCU 33) (const_int 0)) | |
| 5564 | (label_ref (match_operand 0 "" "")) | |
| 5565 | (pc)))] | |
| 5566 | "" | |
| 5567 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
| 5568 | ||
| 5569 | (define_expand "bge" | |
| 5570 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
| 5571 | (set (pc) | |
| 5572 | (if_then_else (ge (reg:CCS 33) (const_int 0)) | |
| 5573 | (label_ref (match_operand 0 "" "")) | |
| 5574 | (pc)))] | |
| 5575 | "" | |
| 5576 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
| 5577 | ||
| 5578 | (define_expand "bgeu" | |
| 5579 | [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) | |
| 5580 | (set (pc) | |
| 5581 | (if_then_else (geu (reg:CCU 33) (const_int 0)) | |
| 5582 | (label_ref (match_operand 0 "" "")) | |
| 5583 | (pc)))] | |
| 5584 | "" | |
| 5585 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
| 5586 | ||
| 5587 | (define_expand "ble" | |
| 5588 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
| 5589 | (set (pc) | |
| 5590 | (if_then_else (le (reg:CCS 33) (const_int 0)) | |
| 5591 | (label_ref (match_operand 0 "" "")) | |
| 5592 | (pc)))] | |
| 5593 | "" | |
| 5594 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
| 5595 | ||
| 5596 | (define_expand "bleu" | |
| 5597 | [(set (reg:CCU 33) (compare:CCU (match_dup 1) (match_dup 2))) | |
| 5598 | (set (pc) | |
| 5599 | (if_then_else (leu (reg:CCU 33) (const_int 0)) | |
| 5600 | (label_ref (match_operand 0 "" "")) | |
| 5601 | (pc)))] | |
| 5602 | "" | |
| 5603 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
| 5604 | ||
| ba956982 UW |
5605 | (define_expand "bunordered" |
| 5606 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
| 5607 | (set (pc) | |
| 5608 | (if_then_else (unordered (reg:CCS 33) (const_int 0)) | |
| 5609 | (label_ref (match_operand 0 "" "")) | |
| 5610 | (pc)))] | |
| 5611 | "" | |
| 5612 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
| 5613 | ||
| 5614 | (define_expand "bordered" | |
| 5615 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
| 5616 | (set (pc) | |
| 5617 | (if_then_else (ordered (reg:CCS 33) (const_int 0)) | |
| 5618 | (label_ref (match_operand 0 "" "")) | |
| 5619 | (pc)))] | |
| 5620 | "" | |
| 5621 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
| 5622 | ||
| 5623 | (define_expand "buneq" | |
| 5624 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
| 5625 | (set (pc) | |
| 5626 | (if_then_else (uneq (reg:CCS 33) (const_int 0)) | |
| 5627 | (label_ref (match_operand 0 "" "")) | |
| 5628 | (pc)))] | |
| 5629 | "" | |
| 5630 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
| 5631 | ||
| 5632 | (define_expand "bungt" | |
| 5633 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
| 5634 | (set (pc) | |
| 5635 | (if_then_else (ungt (reg:CCS 33) (const_int 0)) | |
| 5636 | (label_ref (match_operand 0 "" "")) | |
| 5637 | (pc)))] | |
| 5638 | "" | |
| 5639 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
| 5640 | ||
| 5641 | (define_expand "bunlt" | |
| 5642 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
| 5643 | (set (pc) | |
| 5644 | (if_then_else (unlt (reg:CCS 33) (const_int 0)) | |
| 5645 | (label_ref (match_operand 0 "" "")) | |
| 5646 | (pc)))] | |
| 5647 | "" | |
| 5648 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
| 5649 | ||
| 5650 | (define_expand "bunge" | |
| 5651 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
| 5652 | (set (pc) | |
| 5653 | (if_then_else (unge (reg:CCS 33) (const_int 0)) | |
| 5654 | (label_ref (match_operand 0 "" "")) | |
| 5655 | (pc)))] | |
| 5656 | "" | |
| 5657 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
| 5658 | ||
| 5659 | (define_expand "bunle" | |
| 5660 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
| 5661 | (set (pc) | |
| 5662 | (if_then_else (unle (reg:CCS 33) (const_int 0)) | |
| 5663 | (label_ref (match_operand 0 "" "")) | |
| 5664 | (pc)))] | |
| 5665 | "" | |
| 5666 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
| 5667 | ||
| 5668 | (define_expand "bltgt" | |
| 5669 | [(set (reg:CCS 33) (compare:CCS (match_dup 1) (match_dup 2))) | |
| 5670 | (set (pc) | |
| 5671 | (if_then_else (ltgt (reg:CCS 33) (const_int 0)) | |
| 5672 | (label_ref (match_operand 0 "" "")) | |
| 5673 | (pc)))] | |
| 5674 | "" | |
| 5675 | "{ operands[1] = s390_compare_op0; operands[2] = s390_compare_op1; }") | |
| 5676 | ||
| 9db1d521 HP |
5677 | |
| 5678 | ;; | |
| 5679 | ;;- Conditional jump instructions. | |
| 5680 | ;; | |
| 5681 | ||
| 5682 | (define_insn "cjump" | |
| 5683 | [(set (pc) | |
| 5684 | (if_then_else | |
| 5685 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
| 5686 | (label_ref (match_operand 0 "" "")) | |
| 5687 | (pc)))] | |
| 5688 | "" | |
| 5689 | "* | |
| 5690 | { | |
| 5691 | if (get_attr_length (insn) == 4 || !TARGET_64BIT) | |
| 5692 | return \"j%C1\\t%l0\"; | |
| 5693 | else | |
| 5694 | return \"jg%C1\\t%l0\"; | |
| 5695 | }" | |
| 5696 | [(set_attr "op_type" "RI") | |
| 5697 | (set (attr "length") (if_then_else | |
| 5698 | (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
| 5699 | (const_int 4) (const_int 6)))]) | |
| 5700 | ||
| f314b9b1 | 5701 | (define_insn "*cjump_long" |
| 9db1d521 HP |
5702 | [(set (pc) |
| 5703 | (if_then_else | |
| 5704 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
| f314b9b1 | 5705 | (match_operand 0 "address_operand" "p") |
| 9db1d521 HP |
5706 | (pc)))] |
| 5707 | "" | |
| f314b9b1 UW |
5708 | "* |
| 5709 | { | |
| 5710 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
| 5711 | return \"b%C1r\\t%0\"; | |
| 5712 | else | |
| 5713 | return \"b%C1\\t%a0\"; | |
| 5714 | }" | |
| 5715 | [(set (attr "op_type") | |
| 5716 | (if_then_else (match_operand 0 "register_operand" "") | |
| 5717 | (const_string "RR") (const_string "RX"))) | |
| 5718 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
5719 | |
| 5720 | ||
| 5721 | ;; | |
| 5722 | ;;- Negated conditional jump instructions. | |
| 5723 | ;; | |
| 5724 | ||
| 5725 | (define_insn "icjump" | |
| 5726 | [(set (pc) | |
| 5727 | (if_then_else | |
| 5728 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
| 5729 | (pc) | |
| 5730 | (label_ref (match_operand 0 "" ""))))] | |
| 5731 | "" | |
| 5732 | "* | |
| 5733 | { | |
| 5734 | if (get_attr_length (insn) == 4 || !TARGET_64BIT) | |
| 5735 | return \"j%D1\\t%l0\"; | |
| 5736 | else | |
| 5737 | return \"jg%D1\\t%l0\"; | |
| 5738 | }" | |
| 5739 | [(set_attr "op_type" "RI") | |
| 5740 | (set (attr "length") (if_then_else | |
| 5741 | (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
| 5742 | (const_int 4) (const_int 6)))]) | |
| 5743 | ||
| f314b9b1 | 5744 | (define_insn "*icjump_long" |
| 9db1d521 HP |
5745 | [(set (pc) |
| 5746 | (if_then_else | |
| 5747 | (match_operator 1 "comparison_operator" [(reg 33) (const_int 0)]) | |
| f314b9b1 UW |
5748 | (pc) |
| 5749 | (match_operand 0 "address_operand" "p")))] | |
| 9db1d521 | 5750 | "" |
| f314b9b1 UW |
5751 | "* |
| 5752 | { | |
| 5753 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
| 5754 | return \"b%D1r\\t%0\"; | |
| 5755 | else | |
| 5756 | return \"b%D1\\t%a0\"; | |
| 5757 | }" | |
| 5758 | [(set (attr "op_type") | |
| 5759 | (if_then_else (match_operand 0 "register_operand" "") | |
| 5760 | (const_string "RR") (const_string "RX"))) | |
| 5761 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
5762 | |
| 5763 | ||
| 5764 | ;; | |
| 5765 | ;;- Subtract one and jump if not zero. | |
| 5766 | ;; | |
| 5767 | ||
| 5768 | ;(define_expand "decrement_and_branch_on_count" | |
| 5769 | ; [(use (match_operand 0 "register_operand" "")) | |
| 5770 | ; (use (label_ref (match_operand 1 "" "")))] | |
| 5771 | ; "" | |
| 5772 | ; " | |
| 5773 | ;{ | |
| 5774 | ;/* if (TARGET_64BIT) | |
| 5775 | ; emit_jump_insn (gen_brctdi (operands[0], operands[1])); | |
| 5776 | ; else */ | |
| 5777 | ; emit_jump_insn (gen_brctsi (operands[0], operands[1])); | |
| 5778 | ; DONE; | |
| 5779 | ;}") | |
| 5780 | ; | |
| 5781 | ;(define_insn "brctsi" | |
| 5782 | ; [(set (pc) | |
| 5783 | ; (if_then_else | |
| 5784 | ; (ne (match_operand:SI 0 "register_operand" "+a") | |
| 5785 | ; (const_int 1)) | |
| 5786 | ; (label_ref (match_operand 1 "" "")) | |
| 5787 | ; (pc))) | |
| 5788 | ; (set (match_dup 0) | |
| 5789 | ; (plus:SI (match_dup 0) (const_int -1)))] | |
| 5790 | ; "" | |
| 5791 | ; "brct\\t%0,%l1" | |
| 5792 | ; [(set_attr "op_type" "RI") | |
| 5793 | ; (set_attr "type" "branch")] | |
| 5794 | ;) | |
| 5795 | ; | |
| 5796 | ;(define_insn "ibrctsi" | |
| 5797 | ; [(set (pc) | |
| 5798 | ; (if_then_else | |
| 5799 | ; (eq (match_operand:SI 0 "register_operand" "+a") | |
| 5800 | ; (const_int 1)) | |
| 5801 | ; (pc) | |
| 5802 | ; (label_ref (match_operand 1 "" "")))) | |
| 5803 | ; (set (match_dup 0) | |
| 5804 | ; (plus:SI (match_dup 0) (const_int -1)))] | |
| 5805 | ; "" | |
| 5806 | ; "brct\\t%0,%l1" | |
| 5807 | ; [(set_attr "op_type" "RI") | |
| 5808 | ; (set_attr "type" "branch")] | |
| 5809 | ;) | |
| 5810 | ||
| 5811 | ||
| 5812 | ;; | |
| 5813 | ;;- Unconditional jump instructions. | |
| 5814 | ;; | |
| 5815 | ||
| 5816 | ; | |
| 5817 | ; jump instruction pattern(s). | |
| 5818 | ; | |
| 5819 | ||
| 5820 | (define_insn "jump" | |
| 5821 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
| 5822 | "" | |
| 5823 | "* | |
| 5824 | { | |
| 5825 | if (get_attr_length (insn) == 4 || !TARGET_64BIT) | |
| 5826 | return \"j\\t%l0\"; | |
| 5827 | else | |
| 5828 | return \"jg\\t%l0\"; | |
| 5829 | }" | |
| 5830 | [(set_attr "op_type" "RI") | |
| 5831 | (set (attr "length") (if_then_else | |
| 5832 | (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
| 5833 | (const_int 4) (const_int 6)))]) | |
| 5834 | ||
| 5835 | ; | |
| 5836 | ; indirect-jump instruction pattern(s). | |
| 5837 | ; | |
| 5838 | ||
| 5839 | (define_insn "indirect_jump" | |
| f314b9b1 | 5840 | [(set (pc) (match_operand 0 "address_operand" "p"))] |
| 9db1d521 | 5841 | "" |
| f314b9b1 UW |
5842 | "* |
| 5843 | { | |
| 5844 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
| 5845 | return \"br\\t%0\"; | |
| 5846 | else | |
| 5847 | return \"b\\t%a0\"; | |
| 5848 | }" | |
| 5849 | [(set (attr "op_type") | |
| 5850 | (if_then_else (match_operand 0 "register_operand" "") | |
| 5851 | (const_string "RR") (const_string "RX"))) | |
| 5852 | (set_attr "atype" "mem")]) | |
| 9db1d521 HP |
5853 | |
| 5854 | ; | |
| f314b9b1 | 5855 | ; casesi instruction pattern(s). |
| 9db1d521 HP |
5856 | ; |
| 5857 | ||
| f314b9b1 UW |
5858 | (define_insn "casesi_jump" |
| 5859 | [(set (pc) (match_operand 0 "address_operand" "p")) | |
| 5860 | (use (label_ref (match_operand 1 "" "")))] | |
| 9db1d521 | 5861 | "" |
| f314b9b1 | 5862 | "* |
| 9db1d521 | 5863 | { |
| f314b9b1 UW |
5864 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
| 5865 | return \"br\\t%0\"; | |
| 5866 | else | |
| 5867 | return \"b\\t%a0\"; | |
| 5868 | }" | |
| 5869 | [(set (attr "op_type") | |
| 5870 | (if_then_else (match_operand 0 "register_operand" "") | |
| 5871 | (const_string "RR") (const_string "RX"))) | |
| 5872 | (set_attr "atype" "mem")]) | |
| 9db1d521 | 5873 | |
| f314b9b1 UW |
5874 | (define_expand "casesi" |
| 5875 | [(match_operand:SI 0 "general_operand" "") | |
| 5876 | (match_operand:SI 1 "general_operand" "") | |
| 5877 | (match_operand:SI 2 "general_operand" "") | |
| 5878 | (label_ref (match_operand 3 "" "")) | |
| 5879 | (label_ref (match_operand 4 "" ""))] | |
| 9db1d521 | 5880 | "" |
| f314b9b1 UW |
5881 | " |
| 5882 | { | |
| 5883 | rtx index = gen_reg_rtx (SImode); | |
| 5884 | rtx base = gen_reg_rtx (Pmode); | |
| 5885 | rtx target = gen_reg_rtx (Pmode); | |
| 5886 | ||
| 5887 | emit_move_insn (index, operands[0]); | |
| 5888 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
| 5889 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
| e790b36a | 5890 | operands[4]); |
| f314b9b1 UW |
5891 | |
| 5892 | if (Pmode != SImode) | |
| 5893 | index = convert_to_mode (Pmode, index, 1); | |
| 5894 | if (GET_CODE (index) != REG) | |
| 5895 | index = copy_to_mode_reg (Pmode, index); | |
| 5896 | ||
| 5897 | if (TARGET_64BIT) | |
| 5898 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
| 5899 | else | |
| 5900 | emit_insn (gen_ashlsi3 (index, index, GEN_INT (2))); | |
| 9db1d521 | 5901 | |
| f314b9b1 UW |
5902 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
| 5903 | ||
| 5904 | index = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, base, index)); | |
| 5905 | emit_move_insn (target, index); | |
| 5906 | ||
| 5907 | if (flag_pic) | |
| 5908 | target = gen_rtx_PLUS (Pmode, base, target); | |
| 5909 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
| 5910 | ||
| 5911 | DONE; | |
| 5912 | }") | |
| 9db1d521 HP |
5913 | |
| 5914 | ||
| 5915 | ;; | |
| 5916 | ;;- Jump to subroutine. | |
| 5917 | ;; | |
| 5918 | ;; | |
| 5919 | ||
| 5920 | ; | |
| 5921 | ; untyped call instruction pattern(s). | |
| 5922 | ; | |
| 5923 | ||
| 5924 | ;; Call subroutine returning any type. | |
| 5925 | (define_expand "untyped_call" | |
| 5926 | [(parallel [(call (match_operand 0 "" "") | |
| 5927 | (const_int 0)) | |
| 5928 | (match_operand 1 "" "") | |
| 5929 | (match_operand 2 "" "")])] | |
| 5930 | "" | |
| 5931 | " | |
| 5932 | { | |
| 5933 | int i; | |
| 5934 | ||
| 5935 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
| 5936 | ||
| 5937 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
| 5938 | { | |
| 5939 | rtx set = XVECEXP (operands[2], 0, i); | |
| 5940 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
| 5941 | } | |
| 5942 | ||
| 5943 | /* The optimizer does not know that the call sets the function value | |
| 5944 | registers we stored in the result block. We avoid problems by | |
| 5945 | claiming that all hard registers are used and clobbered at this | |
| 5946 | point. */ | |
| 5947 | emit_insn (gen_blockage ()); | |
| 5948 | ||
| 5949 | DONE; | |
| 5950 | }") | |
| 5951 | ||
| 5952 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
| 5953 | ;; all of memory. This blocks insns from being moved across this point. | |
| 5954 | ||
| 5955 | (define_insn "blockage" | |
| 5956 | [(unspec_volatile [(const_int 0)] 0)] | |
| 5957 | "" | |
| 4023fb28 UW |
5958 | "" |
| 5959 | [(set_attr "type" "none")]) | |
| 5960 | ||
| 9db1d521 HP |
5961 | |
| 5962 | ||
| 5963 | ; | |
| 5964 | ; call instruction pattern(s). | |
| 5965 | ; | |
| 5966 | ||
| 5967 | (define_expand "call" | |
| 5968 | [(parallel [(call (match_operand 0 "" "") | |
| 5969 | (match_operand 1 "" "")) | |
| 5970 | (clobber (match_operand 2 "" ""))])] | |
| 5971 | "" | |
| 5972 | " | |
| 5973 | { | |
| 5974 | /* Abuse operand 2 to hold the return register. */ | |
| 5975 | operands[2] = gen_rtx_REG (Pmode, RETURN_REGNUM); | |
| 5976 | ||
| 5977 | /* In 31-bit, we must load the GOT register even if the | |
| 5978 | compiler doesn't know about it, because the PLT glue | |
| 5979 | code uses it. In 64-bit, this is not necessary. */ | |
| 5980 | if (flag_pic && !TARGET_64BIT) | |
| 5981 | current_function_uses_pic_offset_table = 1; | |
| 5982 | ||
| 5983 | /* Direct function calls need special treatment. */ | |
| 5984 | if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) | |
| 5985 | { | |
| 5986 | rtx sym = XEXP (operands[0], 0); | |
| 5987 | ||
| 5988 | /* When calling a global routine in PIC mode, we must | |
| 5989 | replace the symbol itself with the PLT stub. */ | |
| 5990 | if (flag_pic && !SYMBOL_REF_FLAG(sym)) | |
| 5991 | { | |
| 5992 | sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113); | |
| 5993 | sym = gen_rtx_CONST (Pmode, sym); | |
| 5994 | } | |
| 5995 | ||
| 5996 | /* Unless we can use the bras(l) insn, force the | |
| 5997 | routine address into a register. */ | |
| 5998 | if (!TARGET_SMALL_EXEC && !TARGET_64BIT) | |
| 5999 | { | |
| 6000 | rtx target = gen_reg_rtx (Pmode); | |
| 6001 | emit_move_insn (target, sym); | |
| 6002 | sym = target; | |
| 6003 | } | |
| 6004 | ||
| 6005 | operands[0] = gen_rtx_MEM (QImode, sym); | |
| 6006 | } | |
| 6007 | }") | |
| 6008 | ||
| 6009 | (define_insn "brasl" | |
| 6010 | [(call (mem:QI (match_operand:DI 0 "bras_sym_operand" "X")) | |
| 6011 | (match_operand:SI 1 "const_int_operand" "n")) | |
| 6012 | (clobber (match_operand:DI 2 "register_operand" "=r"))] | |
| 6013 | "TARGET_64BIT" | |
| 6014 | "brasl\\t%2,%0" | |
| 6015 | [(set_attr "op_type" "RIL") | |
| 4023fb28 | 6016 | (set_attr "type" "jsr")]) |
| 9db1d521 HP |
6017 | |
| 6018 | (define_insn "bras" | |
| 6019 | [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X")) | |
| 6020 | (match_operand:SI 1 "const_int_operand" "n")) | |
| 6021 | (clobber (match_operand:SI 2 "register_operand" "=r"))] | |
| 6022 | "TARGET_SMALL_EXEC" | |
| 6023 | "bras\\t%2,%0" | |
| 6024 | [(set_attr "op_type" "RI") | |
| 4023fb28 | 6025 | (set_attr "type" "jsr")]) |
| 9db1d521 HP |
6026 | |
| 6027 | (define_insn "basr_64" | |
| 6028 | [(call (mem:QI (match_operand:DI 0 "register_operand" "a")) | |
| 6029 | (match_operand:SI 1 "const_int_operand" "n")) | |
| 6030 | (clobber (match_operand:DI 2 "register_operand" "=r"))] | |
| 6031 | "TARGET_64BIT" | |
| 6032 | "basr\\t%2,%0" | |
| 6033 | [(set_attr "op_type" "RR") | |
| f2d3c02a | 6034 | (set_attr "type" "jsr") |
| 9db1d521 HP |
6035 | (set_attr "atype" "mem")]) |
| 6036 | ||
| 6037 | (define_insn "basr_31" | |
| 6038 | [(call (mem:QI (match_operand:SI 0 "register_operand" "a")) | |
| 6039 | (match_operand:SI 1 "const_int_operand" "n")) | |
| 6040 | (clobber (match_operand:SI 2 "register_operand" "=r"))] | |
| 6041 | "!TARGET_64BIT" | |
| 6042 | "basr\\t%2,%0" | |
| 6043 | [(set_attr "op_type" "RR") | |
| f2d3c02a | 6044 | (set_attr "type" "jsr") |
| 9db1d521 HP |
6045 | (set_attr "atype" "mem")]) |
| 6046 | ||
| 6047 | (define_insn "bas_64" | |
| 6048 | [(call (mem:QI (match_operand:QI 0 "address_operand" "p")) | |
| 6049 | (match_operand:SI 1 "const_int_operand" "n")) | |
| 6050 | (clobber (match_operand:DI 2 "register_operand" "=r"))] | |
| 6051 | "TARGET_64BIT" | |
| 6052 | "bas\\t%2,%a0" | |
| 6053 | [(set_attr "op_type" "RX") | |
| f2d3c02a | 6054 | (set_attr "type" "jsr") |
| 9db1d521 HP |
6055 | (set_attr "atype" "mem")]) |
| 6056 | ||
| 6057 | (define_insn "bas_31" | |
| 6058 | [(call (mem:QI (match_operand:QI 0 "address_operand" "p")) | |
| 6059 | (match_operand:SI 1 "const_int_operand" "n")) | |
| 6060 | (clobber (match_operand:SI 2 "register_operand" "=r"))] | |
| 6061 | "!TARGET_64BIT" | |
| 6062 | "bas\\t%2,%a0" | |
| 6063 | [(set_attr "op_type" "RX") | |
| f2d3c02a | 6064 | (set_attr "type" "jsr") |
| 9db1d521 HP |
6065 | (set_attr "atype" "mem")]) |
| 6066 | ||
| 6067 | ||
| 6068 | ; | |
| 6069 | ; call_value instruction pattern(s). | |
| 6070 | ; | |
| 6071 | ||
| 6072 | (define_expand "call_value" | |
| 6073 | [(parallel [(set (match_operand 0 "" "") | |
| 6074 | (call (match_operand 1 "" "") | |
| 6075 | (match_operand 2 "" ""))) | |
| 6076 | (clobber (match_operand 3 "" ""))])] | |
| 6077 | "" | |
| 6078 | " | |
| 6079 | { | |
| 6080 | /* Abuse operand 3 to hold the return register. */ | |
| 6081 | operands[3] = gen_rtx_REG (Pmode, RETURN_REGNUM); | |
| 6082 | ||
| 6083 | /* In 31-bit, we must load the GOT register even if the | |
| 6084 | compiler doesn't know about it, because the PLT glue | |
| 6085 | code uses it. In 64-bit, this is not necessary. */ | |
| 6086 | if (flag_pic && !TARGET_64BIT) | |
| 6087 | current_function_uses_pic_offset_table = 1; | |
| 6088 | ||
| 6089 | /* Direct function calls need special treatment. */ | |
| 6090 | if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) | |
| 6091 | { | |
| 6092 | rtx sym = XEXP (operands[1], 0); | |
| 6093 | ||
| 6094 | /* When calling a global routine in PIC mode, we must | |
| 6095 | replace the symbol itself with the PLT stub. */ | |
| 6096 | if (flag_pic && !SYMBOL_REF_FLAG(sym)) | |
| 6097 | { | |
| 6098 | sym = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, sym), 113); | |
| 6099 | sym = gen_rtx_CONST (Pmode, sym); | |
| 6100 | } | |
| 6101 | ||
| 6102 | /* Unless we can use the bras(l) insn, force the | |
| 6103 | routine address into a register. */ | |
| 6104 | if (!TARGET_SMALL_EXEC && !TARGET_64BIT) | |
| 6105 | { | |
| 6106 | rtx target = gen_reg_rtx (Pmode); | |
| 6107 | emit_move_insn (target, sym); | |
| 6108 | sym = target; | |
| 6109 | } | |
| 6110 | ||
| 6111 | operands[1] = gen_rtx_MEM (QImode, sym); | |
| 6112 | } | |
| 6113 | }") | |
| 6114 | ||
| 6115 | (define_insn "brasl_r" | |
| 6116 | [(set (match_operand 0 "register_operand" "=df") | |
| 6117 | (call (mem:QI (match_operand:DI 1 "bras_sym_operand" "X")) | |
| 6118 | (match_operand:SI 2 "const_int_operand" "n"))) | |
| 6119 | (clobber (match_operand:DI 3 "register_operand" "=r"))] | |
| 6120 | "TARGET_64BIT" | |
| 6121 | "brasl\\t%3,%1" | |
| 6122 | [(set_attr "op_type" "RIL") | |
| f2d3c02a | 6123 | (set_attr "type" "jsr")]) |
| 9db1d521 HP |
6124 | |
| 6125 | (define_insn "bras_r" | |
| 6126 | [(set (match_operand 0 "register_operand" "=df") | |
| 6127 | (call (mem:QI (match_operand:SI 1 "bras_sym_operand" "X")) | |
| 6128 | (match_operand:SI 2 "const_int_operand" "n"))) | |
| 6129 | (clobber (match_operand:SI 3 "register_operand" "=r"))] | |
| 6130 | "TARGET_SMALL_EXEC" | |
| 6131 | "bras\\t%3,%1" | |
| 6132 | [(set_attr "op_type" "RI") | |
| f2d3c02a | 6133 | (set_attr "type" "jsr")]) |
| 9db1d521 HP |
6134 | |
| 6135 | (define_insn "basr_r_64" | |
| 6136 | [(set (match_operand 0 "register_operand" "=df") | |
| 6137 | (call (mem:QI (match_operand:DI 1 "register_operand" "a")) | |
| 6138 | (match_operand:SI 2 "const_int_operand" "n"))) | |
| 6139 | (clobber (match_operand:DI 3 "register_operand" "=r"))] | |
| 6140 | "TARGET_64BIT" | |
| 6141 | "basr\\t%3,%1" | |
| 6142 | [(set_attr "op_type" "RR") | |
| f2d3c02a | 6143 | (set_attr "type" "jsr")]) |
| 9db1d521 HP |
6144 | |
| 6145 | (define_insn "basr_r_31" | |
| 6146 | [(set (match_operand 0 "register_operand" "=df") | |
| 6147 | (call (mem:QI (match_operand:SI 1 "register_operand" "a")) | |
| 6148 | (match_operand:SI 2 "const_int_operand" "n"))) | |
| 6149 | (clobber (match_operand:SI 3 "register_operand" "=r"))] | |
| 6150 | "!TARGET_64BIT" | |
| 6151 | "basr\\t%3,%1" | |
| 6152 | [(set_attr "op_type" "RR") | |
| f2d3c02a | 6153 | (set_attr "type" "jsr") |
| 9db1d521 HP |
6154 | (set_attr "atype" "mem")]) |
| 6155 | ||
| 6156 | (define_insn "bas_r_64" | |
| 6157 | [(set (match_operand 0 "register_operand" "=df") | |
| 6158 | (call (mem:QI (match_operand:QI 1 "address_operand" "p")) | |
| 6159 | (match_operand:SI 2 "const_int_operand" "n"))) | |
| 6160 | (clobber (match_operand:DI 3 "register_operand" "=r"))] | |
| 6161 | "TARGET_64BIT" | |
| 6162 | "bas\\t%3,%a1" | |
| 6163 | [(set_attr "op_type" "RX") | |
| f2d3c02a | 6164 | (set_attr "type" "jsr") |
| 9db1d521 HP |
6165 | (set_attr "atype" "mem")]) |
| 6166 | ||
| 6167 | (define_insn "bas_r_31" | |
| 6168 | [(set (match_operand 0 "register_operand" "=df") | |
| 6169 | (call (mem:QI (match_operand:QI 1 "address_operand" "p")) | |
| 6170 | (match_operand:SI 2 "const_int_operand" "n"))) | |
| 6171 | (clobber (match_operand:SI 3 "register_operand" "=r"))] | |
| 6172 | "!TARGET_64BIT" | |
| 6173 | "bas\\t%3,%a1" | |
| 6174 | [(set_attr "op_type" "RX") | |
| f2d3c02a | 6175 | (set_attr "type" "jsr") |
| 9db1d521 HP |
6176 | (set_attr "atype" "mem")]) |
| 6177 | ||
| 6178 | ||
| 6179 | ;; | |
| 6180 | ;;- Miscellaneous instructions. | |
| 6181 | ;; | |
| 6182 | ||
| 6183 | ; | |
| 6184 | ; allocate stack instruction pattern(s). | |
| 6185 | ; | |
| 6186 | ||
| 6187 | (define_expand "allocate_stack" | |
| 6188 | [(set (reg 15) | |
| 6189 | (plus (reg 15) (match_operand 1 "general_operand" ""))) | |
| 6190 | (set (match_operand 0 "general_operand" "") | |
| 6191 | (reg 15))] | |
| 6192 | "" | |
| 6193 | " | |
| 6194 | { | |
| 6195 | rtx stack = gen_rtx (REG, Pmode, STACK_POINTER_REGNUM); | |
| 6196 | rtx chain = gen_rtx (MEM, Pmode, stack); | |
| 6197 | rtx temp = gen_reg_rtx (Pmode); | |
| 6198 | ||
| 6199 | emit_move_insn (temp, chain); | |
| 6200 | ||
| 6201 | if (TARGET_64BIT) | |
| 6202 | emit_insn (gen_adddi3 (stack, stack, negate_rtx (Pmode, operands[1]))); | |
| 6203 | else | |
| 6204 | emit_insn (gen_addsi3 (stack, stack, negate_rtx (Pmode, operands[1]))); | |
| 6205 | ||
| 6206 | emit_move_insn (chain, temp); | |
| 6207 | ||
| 6208 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); | |
| 6209 | DONE; | |
| 6210 | }") | |
| 6211 | ||
| 6212 | ||
| 6213 | ; | |
| 6214 | ; setjmp/longjmp instruction pattern(s). | |
| 6215 | ; | |
| 6216 | ||
| 6217 | (define_expand "builtin_setjmp_setup" | |
| 6218 | [(unspec [(match_operand 0 "register_operand" "a")] 1)] | |
| 6219 | "" | |
| 6220 | " | |
| 6221 | { | |
| f314b9b1 UW |
6222 | rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode))); |
| 6223 | rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER); | |
| 6224 | ||
| 6225 | emit_move_insn (base, basereg); | |
| 9db1d521 HP |
6226 | DONE; |
| 6227 | }") | |
| 6228 | ||
| 6229 | (define_expand "builtin_setjmp_receiver" | |
| 6230 | [(unspec_volatile [(label_ref (match_operand 0 "" ""))] 2)] | |
| f314b9b1 | 6231 | "flag_pic" |
| 9db1d521 HP |
6232 | " |
| 6233 | { | |
| f314b9b1 UW |
6234 | rtx gotreg = gen_rtx_REG (Pmode, PIC_OFFSET_TABLE_REGNUM); |
| 6235 | rtx got = gen_rtx_SYMBOL_REF (Pmode, \"_GLOBAL_OFFSET_TABLE_\"); | |
| 6236 | SYMBOL_REF_FLAG (got) = 1; | |
| 6237 | ||
| 6238 | emit_move_insn (gotreg, got); | |
| 6239 | emit_insn (gen_rtx_USE (VOIDmode, gotreg)); | |
| 9db1d521 HP |
6240 | DONE; |
| 6241 | }") | |
| 6242 | ||
| 9db1d521 HP |
6243 | (define_expand "builtin_longjmp" |
| 6244 | [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)] | |
| 6245 | "" | |
| 6246 | " | |
| 6247 | { | |
| 6248 | /* The elements of the buffer are, in order: */ | |
| 6249 | rtx fp = gen_rtx_MEM (Pmode, operands[0]); | |
| f314b9b1 UW |
6250 | rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], GET_MODE_SIZE (Pmode))); |
| 6251 | rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2 * GET_MODE_SIZE (Pmode))); | |
| 6252 | rtx base = gen_rtx_MEM (Pmode, plus_constant (operands[0], 4 * GET_MODE_SIZE (Pmode))); | |
| 6253 | rtx basereg = gen_rtx_REG (Pmode, BASE_REGISTER); | |
| 9db1d521 HP |
6254 | rtx jmp = gen_rtx_REG (Pmode, 14); |
| 6255 | ||
| 6256 | emit_move_insn (jmp, lab); | |
| f314b9b1 | 6257 | emit_move_insn (basereg, base); |
| 9db1d521 HP |
6258 | emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX); |
| 6259 | emit_move_insn (hard_frame_pointer_rtx, fp); | |
| 6260 | ||
| 6261 | emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx)); | |
| 6262 | emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx)); | |
| f314b9b1 | 6263 | emit_insn (gen_rtx_USE (VOIDmode, basereg)); |
| 9db1d521 HP |
6264 | emit_indirect_jump (jmp); |
| 6265 | DONE; | |
| 6266 | }") | |
| 6267 | ||
| 6268 | ||
| 6269 | ;; These patterns say how to save and restore the stack pointer. We need not | |
| 6270 | ;; save the stack pointer at function level since we are careful to | |
| 6271 | ;; preserve the backchain. At block level, we have to restore the backchain | |
| 6272 | ;; when we restore the stack pointer. | |
| 6273 | ;; | |
| 6274 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
| 6275 | ;; backchain and restore both. Note that in the nonlocal case, the | |
| 6276 | ;; save area is a memory location. | |
| 6277 | ||
| 6278 | (define_expand "save_stack_function" | |
| 6279 | [(match_operand 0 "general_operand" "") | |
| 6280 | (match_operand 1 "general_operand" "")] | |
| 6281 | "" | |
| 6282 | "DONE;") | |
| 6283 | ||
| 6284 | (define_expand "restore_stack_function" | |
| 6285 | [(match_operand 0 "general_operand" "") | |
| 6286 | (match_operand 1 "general_operand" "")] | |
| 6287 | "" | |
| 6288 | "DONE;") | |
| 6289 | ||
| 6290 | (define_expand "restore_stack_block" | |
| 6291 | [(use (match_operand 0 "register_operand" "")) | |
| 6292 | (set (match_dup 2) (match_dup 3)) | |
| 6293 | (set (match_dup 0) (match_operand 1 "register_operand" "")) | |
| 6294 | (set (match_dup 3) (match_dup 2))] | |
| 6295 | "" | |
| 6296 | " | |
| 6297 | { | |
| 6298 | operands[2] = gen_reg_rtx (Pmode); | |
| 6299 | operands[3] = gen_rtx_MEM (Pmode, operands[0]); | |
| 6300 | }") | |
| 6301 | ||
| 6302 | (define_expand "save_stack_nonlocal" | |
| 6303 | [(match_operand 0 "memory_operand" "") | |
| 6304 | (match_operand 1 "register_operand" "")] | |
| 6305 | "" | |
| 6306 | " | |
| 6307 | { | |
| 6308 | rtx temp = gen_reg_rtx (Pmode); | |
| 6309 | ||
| 6310 | /* Copy the backchain to the first word, sp to the second. */ | |
| 6311 | emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1])); | |
| 6312 | emit_move_insn (operand_subword (operands[0], 0, 0, | |
| 6313 | TARGET_64BIT ? TImode : DImode), | |
| 6314 | temp); | |
| 6315 | emit_move_insn (operand_subword (operands[0], 1, 0, | |
| 6316 | TARGET_64BIT ? TImode : DImode), | |
| 6317 | operands[1]); | |
| 6318 | DONE; | |
| 6319 | }") | |
| 6320 | ||
| 6321 | (define_expand "restore_stack_nonlocal" | |
| 6322 | [(match_operand 0 "register_operand" "") | |
| 6323 | (match_operand 1 "memory_operand" "")] | |
| 6324 | "" | |
| 6325 | " | |
| 6326 | { | |
| 6327 | rtx temp = gen_reg_rtx (Pmode); | |
| 6328 | ||
| 6329 | /* Restore the backchain from the first word, sp from the second. */ | |
| 6330 | emit_move_insn (temp, | |
| 6331 | operand_subword (operands[1], 0, 0, | |
| 6332 | TARGET_64BIT ? TImode : DImode)); | |
| 6333 | emit_move_insn (operands[0], | |
| 6334 | operand_subword (operands[1], 1, 0, | |
| 6335 | TARGET_64BIT ? TImode : DImode)); | |
| 6336 | emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp); | |
| 6337 | DONE; | |
| 6338 | }") | |
| 6339 | ||
| 6340 | ||
| 6341 | ; | |
| 6342 | ; nop instruction pattern(s). | |
| 6343 | ; | |
| 6344 | ||
| 6345 | (define_insn "nop" | |
| 6346 | [(const_int 0)] | |
| 6347 | "" | |
| 6348 | "lr\\t0,0" | |
| 6349 | [(set_attr "op_type" "RR")]) | |
| 6350 | ||
| 6351 | ||
| 6352 | ; | |
| 6353 | ; Special literal pool access instruction pattern(s). | |
| 6354 | ; | |
| 6355 | ||
| 6356 | (define_insn "reload_base" | |
| 6357 | [(parallel [(set (reg 13) (pc)) | |
| 6358 | (use (label_ref (match_operand 0 "" "")))])] | |
| 6359 | "" | |
| 6360 | "* | |
| 6361 | { | |
| 6362 | if (TARGET_64BIT) | |
| 6363 | return \"larl\\t13,%y0\"; | |
| 6364 | else | |
| 6365 | return \"basr\\t13,0\;ahi\\t13,%Y0\"; | |
| 6366 | }" | |
| 6367 | [(set_attr "op_type" "NN") | |
| 4023fb28 | 6368 | (set_attr "type" "la") |
| 9db1d521 HP |
6369 | (set_attr "length" "8")]) |
| 6370 | ||
| 6371 | (define_insn "ltorg" | |
| 6372 | [(parallel [(set (reg 13) (pc)) | |
| 6373 | (use (match_operand:SI 0 "const_int_operand" ""))])] | |
| 6374 | "" | |
| 6375 | "* | |
| 6376 | { | |
| 6377 | s390_dump_literal_pool (insn, operands[0]); | |
| 6378 | return \"0:\"; | |
| 6379 | }" | |
| 6380 | [(set_attr "op_type" "NN") | |
| 4023fb28 | 6381 | (set_attr "type" "other") |
| 9db1d521 HP |
6382 | (set_attr "length" "4096")]) |
| 6383 | ||
| 4023fb28 UW |
6384 | ;; |
| 6385 | ;; Insns related to generating the function prologue and epilogue. | |
| 6386 | ;; | |
| 6387 | ||
| 6388 | ||
| 6389 | (define_expand "prologue" | |
| 6390 | [(use (const_int 0))] | |
| 6391 | "" | |
| 6392 | " | |
| 6393 | { | |
| 6394 | s390_emit_prologue (); | |
| 6395 | DONE; | |
| 6396 | }") | |
| 6397 | ||
| 6398 | (define_expand "epilogue" | |
| 6399 | [(use (const_int 1))] | |
| 6400 | "" | |
| 6401 | " | |
| 6402 | { | |
| 6403 | s390_emit_epilogue (); | |
| 6404 | DONE; | |
| 6405 | }") | |
| 6406 | ||
| 6407 | ||
| 6408 | (define_insn "*return_si" | |
| 6409 | [(return) | |
| 6410 | (use (match_operand:SI 0 "register_operand" "a"))] | |
| 6411 | "!TARGET_64BIT" | |
| 6412 | "br\\t%0" | |
| 6413 | [(set_attr "op_type" "RR") | |
| 6414 | (set_attr "type" "jsr") | |
| 6415 | (set_attr "atype" "mem")]) | |
| 6416 | ||
| 6417 | (define_insn "*return_di" | |
| 6418 | [(return) | |
| 6419 | (use (match_operand:DI 0 "register_operand" "a"))] | |
| 6420 | "TARGET_64BIT" | |
| 6421 | "br\\t%0" | |
| 6422 | [(set_attr "op_type" "RR") | |
| 6423 | (set_attr "type" "jsr") | |
| 6424 | (set_attr "atype" "mem")]) | |
| 6425 | ||
| 6426 | ||
| 6427 | (define_insn "lit" | |
| 6428 | [(set (reg 13) (pc)) | |
| 6429 | (unspec_volatile [(const_int 0)] 200)] | |
| 6430 | "" | |
| 6431 | "* | |
| 6432 | { | |
| 6433 | s390_output_constant_pool (asm_out_file); | |
| 6434 | return \"\"; | |
| 6435 | }" | |
| 6436 | [(set_attr "op_type" "NN") | |
| 6437 | (set_attr "type" "integer")]) | |
| 6438 | ||
| 9db1d521 HP |
6439 | |
| 6440 | ;; | |
| 6441 | ;; Peephole optimization patterns. | |
| 6442 | ;; | |
| 6443 | ||
| 6444 | (define_peephole | |
| 6445 | [(set (match_operand:SI 0 "memory_operand" "m") | |
| 6446 | (match_operand:SI 1 "register_operand" "d")) | |
| 6447 | (set (match_dup 1) | |
| 6448 | (match_dup 0))] | |
| 6449 | "" | |
| 6450 | "st\\t%1,%0") | |
| 6451 | ||
| 6452 | (define_peephole | |
| 6453 | [(set (match_operand:SI 0 "memory_operand" "m") | |
| 6454 | (match_operand:SI 1 "register_operand" "d")) | |
| 6455 | (set (match_dup 0) | |
| 6456 | (match_dup 1))] | |
| 6457 | "" | |
| 6458 | "st\\t%1,%0") | |
| 6459 | ||
| 6460 | (define_peephole | |
| 6461 | [(set (match_operand:SI 0 "register_operand" "") | |
| 6462 | (match_operand:SI 1 "register_operand" "")) | |
| 6463 | (parallel | |
| 6464 | [(set (match_dup 0) | |
| 6465 | (plus:SI (match_dup 0) | |
| 6466 | (match_operand:SI 2 "immediate_operand" ""))) | |
| 6467 | (clobber (reg:CC 33))])] | |
| 6468 | "(REGNO (operands[0]) == STACK_POINTER_REGNUM || | |
| 6469 | REGNO (operands[1]) == STACK_POINTER_REGNUM || | |
| 6470 | REGNO (operands[0]) == BASE_REGISTER || | |
| 6471 | REGNO (operands[1]) == BASE_REGISTER) && | |
| 6472 | INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 4096" | |
| 6473 | "la\\t%0,%c2(%1)") | |
| 6474 | ||
| 6475 | ; | |
| 6476 | ; peepholes for fast char instructions | |
| 6477 | ; | |
| 6478 | ||
| 6479 | ;(define_peephole | |
| 6480 | ; [(set (match_operand:QI 0 "register_operand" "d") | |
| 6481 | ; (match_operand:QI 1 "s_operand" "Q")) | |
| 6482 | ; (set (match_operand:SI 2 "register_operand" "0") | |
| 6483 | ; (zero_extend:SI (match_dup 0)))] | |
| 6484 | ; "REGNO(operands[0]) == REGNO(operands[2])" | |
| 6485 | ; "icm\\t%0,8,%1\;srl\\t%0,24") | |
| 6486 | ||
| 6487 | ;(define_peephole | |
| 6488 | ; [(set (match_operand:QI 0 "register_operand" "d") | |
| 6489 | ; (match_operand:QI 1 "s_operand" "Q")) | |
| 6490 | ; (set (match_operand:SI 2 "register_operand" "0") | |
| 6491 | ; (sign_extend:SI (match_dup 0)))] | |
| 6492 | ; "REGNO(operands[0]) == REGNO(operands[2])" | |
| 6493 | ; "icm\\t%0,8,%1\;sra\\t%0,24") | |
| 6494 | ||
| 6495 | (define_peephole | |
| 6496 | [(set (match_operand:QI 0 "register_operand" "d") | |
| 6497 | (match_operand:QI 1 "immediate_operand" "J")) | |
| 6498 | (set (match_operand:SI 2 "register_operand" "0" ) | |
| 6499 | (sign_extend:SI (match_dup 0) ) )] | |
| 6500 | "REGNO(operands[0]) == REGNO(operands[2])" | |
| 6501 | "lhi\\t%0,%h1") | |
| 6502 | ||
| 6503 | ; | |
| 6504 | ; peepholes for fast short instructions | |
| 6505 | ; | |
| 6506 | ||
| 6507 | ;(define_peephole | |
| 6508 | ; [(set (match_operand:HI 0 "register_operand" "d") | |
| 6509 | ; (match_operand:HI 1 "s_operand" "Q")) | |
| 6510 | ; (set (match_operand:SI 2 "register_operand" "0" ) | |
| 6511 | ; (zero_extend:SI (match_dup 0)))] | |
| 6512 | ; "REGNO(operands[0]) == REGNO(operands[2])" | |
| 6513 | ; "icm\\t%0,12,%1\;srl\\t%0,16") | |
| 6514 | ||
| 6515 | (define_peephole | |
| 6516 | [(set (match_operand:HI 0 "register_operand" "d") | |
| 6517 | (match_operand:HI 1 "memory_operand" "m")) | |
| 6518 | (set (match_operand:SI 2 "register_operand" "0" ) | |
| 6519 | (sign_extend:SI (match_dup 0)))] | |
| 6520 | "REGNO(operands[0]) == REGNO(operands[2])" | |
| 6521 | "lh\\t%0,%1") | |
| 6522 | ||
| 6523 | (define_peephole | |
| 6524 | [(set (match_operand:HI 0 "register_operand" "d") | |
| 6525 | (match_operand:HI 1 "immediate_operand" "K")) | |
| 6526 | (set (match_operand:SI 2 "register_operand" "0" ) | |
| 6527 | (sign_extend:SI (match_dup 0) ) )] | |
| 6528 | "REGNO(operands[0]) == REGNO(operands[2])" | |
| 6529 | "lhi\\t%0,%h1") | |
| 6530 | ||
| 6531 | ; | |
| 6532 | ; peepholes for divide instructions | |
| 6533 | ; | |
| 6534 | ||
| 6535 | (define_peephole | |
| 6536 | [(set (match_operand:DI 0 "register_operand" "d") | |
| 6537 | (match_operand:DI 1 "memory_operand" "m")) | |
| 6538 | (set (match_dup 0) | |
| 6539 | (lshiftrt:DI (match_dup 0) | |
| 6540 | (match_operand:SI 2 "immediate_operand" "J"))) | |
| 6541 | (set (match_dup 0) | |
| 6542 | (div:SI (match_dup 0) | |
| 6543 | (match_operand:SI 3 "nonimmediate_operand" "g"))) | |
| 6544 | (set (match_dup 1) | |
| 6545 | (match_dup 0))] | |
| 6546 | "" | |
| 6547 | "* | |
| 6548 | { | |
| 6549 | output_asm_insn (\"l\\t%0,%1\", operands); | |
| 6550 | output_asm_insn (\"srdl\\t%0,%b2\", operands); | |
| 6551 | ||
| 6552 | if (REG_P (operands[3])) | |
| 6553 | output_asm_insn (\"dr\\t%0,%3\", operands); | |
| 6554 | else | |
| 6555 | output_asm_insn (\"d\\t%0,%3\", operands); | |
| 6556 | ||
| 6557 | return \"st\\t%N0,%N1\"; | |
| 6558 | }") | |
| 6559 | ||
| 6560 | (define_peephole | |
| 6561 | [(set (match_operand:DI 0 "register_operand" "d") | |
| 6562 | (match_operand:DI 1 "memory_operand" "m")) | |
| 6563 | (set (match_dup 0) | |
| 6564 | (lshiftrt:DI (match_dup 0) | |
| 6565 | (match_operand:SI 2 "immediate_operand" "J"))) | |
| 6566 | (set (match_dup 0) | |
| 6567 | (mod:SI (match_dup 0) | |
| 6568 | (match_operand:SI 3 "nonimmediate_operand" "g"))) | |
| 6569 | (set (match_dup 1) | |
| 6570 | (match_dup 0))] | |
| 6571 | "" | |
| 6572 | "* | |
| 6573 | { | |
| 6574 | output_asm_insn (\"l\\t%0,%1\", operands); | |
| 6575 | output_asm_insn (\"srdl\\t%0,%b2\", operands); | |
| 6576 | ||
| 6577 | if (REG_P (operands[3])) | |
| 6578 | output_asm_insn (\"dr\\t%0,%3\", operands); | |
| 6579 | else | |
| 6580 | output_asm_insn (\"d\\t%0,%3\", operands); | |
| 6581 | ||
| 6582 | return \"st\\t%0,%1\"; | |
| 6583 | }") | |
| 6584 |