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Commit | Line | Data |
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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
818ab71a | 2 | ;; Copyright (C) 1999-2016 Free Software Foundation, Inc. |
9db1d521 | 3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
4 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
5 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | ;; version. |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
22 | |
23 | ;; | |
cd8dc1f9 | 24 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 25 | ;; |
cd8dc1f9 | 26 | |
9db1d521 HP |
27 | ;; Special formats used for outputting 390 instructions. |
28 | ;; | |
f19a9af7 AK |
29 | ;; %C: print opcode suffix for branch condition. |
30 | ;; %D: print opcode suffix for inverse branch condition. | |
31 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 32 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
33 | ;; %O: print only the displacement of a memory reference. |
34 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 35 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
36 | ;; %N: print the second word of a DImode operand. |
37 | ;; %M: print the second word of a TImode operand. | |
da48f5ec | 38 | ;; %Y: print shift count operand. |
f4aa3848 | 39 | ;; |
f19a9af7 | 40 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 41 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
42 | ;; %x: print integer X as if it's an unsigned halfword. |
43 | ;; %h: print integer X as if it's a signed halfword. | |
44 | ;; %i: print the first nonzero HImode part of X. | |
45 | ;; %j: print the first HImode part unequal to -1 of X. | |
46 | ;; %k: print the first nonzero SImode part of X. | |
47 | ;; %m: print the first SImode part unequal to -1 of X. | |
48 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
49 | ;; |
50 | ;; We have a special constraint for pattern matching. | |
51 | ;; | |
52 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
53 | ;; | |
9db1d521 | 54 | |
fd3cd001 UW |
55 | ;; |
56 | ;; UNSPEC usage | |
57 | ;; | |
58 | ||
30a49b23 AK |
59 | (define_c_enum "unspec" [ |
60 | ; Miscellaneous | |
61 | UNSPEC_ROUND | |
30a49b23 AK |
62 | UNSPEC_ICM |
63 | UNSPEC_TIE | |
10bbf137 | 64 | |
5a3fe9b6 AK |
65 | ; Convert CC into a str comparison result and copy it into an |
66 | ; integer register | |
67 | ; cc0->0, cc1->1, cc2->-1, (cc3->-1) | |
68 | UNSPEC_STRCMPCC_TO_INT | |
69 | ||
70 | ; Copy CC as is into the lower 2 bits of an integer register | |
71 | UNSPEC_CC_TO_INT | |
72 | ||
da0dcab1 DV |
73 | ; The right hand side of an setmem |
74 | UNSPEC_REPLICATE_BYTE | |
75 | ||
10bbf137 | 76 | ; GOT/PLT and lt-relative accesses |
30a49b23 AK |
77 | UNSPEC_LTREL_OFFSET |
78 | UNSPEC_LTREL_BASE | |
79 | UNSPEC_POOL_OFFSET | |
80 | UNSPEC_GOTENT | |
81 | UNSPEC_GOT | |
82 | UNSPEC_GOTOFF | |
83 | UNSPEC_PLT | |
84 | UNSPEC_PLTOFF | |
fd7643fb UW |
85 | |
86 | ; Literal pool | |
30a49b23 AK |
87 | UNSPEC_RELOAD_BASE |
88 | UNSPEC_MAIN_BASE | |
89 | UNSPEC_LTREF | |
90 | UNSPEC_INSN | |
91 | UNSPEC_EXECUTE | |
fd7643fb | 92 | |
1a8c13b3 | 93 | ; Atomic Support |
30a49b23 | 94 | UNSPEC_MB |
78ce265b | 95 | UNSPEC_MOVA |
1a8c13b3 | 96 | |
fd7643fb | 97 | ; TLS relocation specifiers |
30a49b23 AK |
98 | UNSPEC_TLSGD |
99 | UNSPEC_TLSLDM | |
100 | UNSPEC_NTPOFF | |
101 | UNSPEC_DTPOFF | |
102 | UNSPEC_GOTNTPOFF | |
103 | UNSPEC_INDNTPOFF | |
fd3cd001 UW |
104 | |
105 | ; TLS support | |
30a49b23 AK |
106 | UNSPEC_TLSLDM_NTPOFF |
107 | UNSPEC_TLS_LOAD | |
91d39d71 UW |
108 | |
109 | ; String Functions | |
30a49b23 AK |
110 | UNSPEC_SRST |
111 | UNSPEC_MVST | |
638e37c2 | 112 | |
7b8acc34 | 113 | ; Stack Smashing Protector |
30a49b23 AK |
114 | UNSPEC_SP_SET |
115 | UNSPEC_SP_TEST | |
85dae55a | 116 | |
4cb4721f MK |
117 | ; Split stack support |
118 | UNSPEC_STACK_CHECK | |
119 | ||
638e37c2 | 120 | ; Test Data Class (TDC) |
30a49b23 | 121 | UNSPEC_TDC_INSN |
65b1d8ea AK |
122 | |
123 | ; Population Count | |
30a49b23 AK |
124 | UNSPEC_POPCNT |
125 | UNSPEC_COPYSIGN | |
d12a76f3 AK |
126 | |
127 | ; Load FP Integer | |
128 | UNSPEC_FPINT_FLOOR | |
129 | UNSPEC_FPINT_BTRUNC | |
130 | UNSPEC_FPINT_ROUND | |
131 | UNSPEC_FPINT_CEIL | |
132 | UNSPEC_FPINT_NEARBYINT | |
133 | UNSPEC_FPINT_RINT | |
085261c8 | 134 | |
3af82a61 AK |
135 | UNSPEC_LCBB |
136 | ||
085261c8 | 137 | ; Vector |
3af82a61 AK |
138 | UNSPEC_VEC_SMULT_HI |
139 | UNSPEC_VEC_UMULT_HI | |
140 | UNSPEC_VEC_SMULT_LO | |
085261c8 AK |
141 | UNSPEC_VEC_SMULT_EVEN |
142 | UNSPEC_VEC_UMULT_EVEN | |
143 | UNSPEC_VEC_SMULT_ODD | |
144 | UNSPEC_VEC_UMULT_ODD | |
3af82a61 AK |
145 | |
146 | UNSPEC_VEC_VMAL | |
147 | UNSPEC_VEC_VMAH | |
148 | UNSPEC_VEC_VMALH | |
149 | UNSPEC_VEC_VMAE | |
150 | UNSPEC_VEC_VMALE | |
151 | UNSPEC_VEC_VMAO | |
152 | UNSPEC_VEC_VMALO | |
153 | ||
154 | UNSPEC_VEC_GATHER | |
155 | UNSPEC_VEC_EXTRACT | |
156 | UNSPEC_VEC_INSERT_AND_ZERO | |
157 | UNSPEC_VEC_LOAD_BNDRY | |
085261c8 | 158 | UNSPEC_VEC_LOAD_LEN |
3af82a61 AK |
159 | UNSPEC_VEC_MERGEH |
160 | UNSPEC_VEC_MERGEL | |
161 | UNSPEC_VEC_PACK | |
162 | UNSPEC_VEC_PACK_SATURATE | |
163 | UNSPEC_VEC_PACK_SATURATE_CC | |
164 | UNSPEC_VEC_PACK_SATURATE_GENCC | |
165 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE | |
166 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC | |
167 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC | |
168 | UNSPEC_VEC_PERM | |
169 | UNSPEC_VEC_PERMI | |
170 | UNSPEC_VEC_EXTEND | |
171 | UNSPEC_VEC_STORE_LEN | |
172 | UNSPEC_VEC_UNPACKH | |
173 | UNSPEC_VEC_UNPACKH_L | |
174 | UNSPEC_VEC_UNPACKL | |
175 | UNSPEC_VEC_UNPACKL_L | |
176 | UNSPEC_VEC_ADDC | |
177 | UNSPEC_VEC_ADDC_U128 | |
178 | UNSPEC_VEC_ADDE_U128 | |
179 | UNSPEC_VEC_ADDEC_U128 | |
180 | UNSPEC_VEC_AVG | |
181 | UNSPEC_VEC_AVGU | |
182 | UNSPEC_VEC_CHECKSUM | |
183 | UNSPEC_VEC_GFMSUM | |
184 | UNSPEC_VEC_GFMSUM_128 | |
185 | UNSPEC_VEC_GFMSUM_ACCUM | |
186 | UNSPEC_VEC_GFMSUM_ACCUM_128 | |
187 | UNSPEC_VEC_SET | |
188 | ||
189 | UNSPEC_VEC_VSUMG | |
190 | UNSPEC_VEC_VSUMQ | |
191 | UNSPEC_VEC_VSUM | |
192 | UNSPEC_VEC_RL_MASK | |
193 | UNSPEC_VEC_SLL | |
194 | UNSPEC_VEC_SLB | |
195 | UNSPEC_VEC_SLDB | |
196 | UNSPEC_VEC_SRAL | |
197 | UNSPEC_VEC_SRAB | |
198 | UNSPEC_VEC_SRL | |
199 | UNSPEC_VEC_SRLB | |
200 | ||
201 | UNSPEC_VEC_SUB_U128 | |
202 | UNSPEC_VEC_SUBC | |
203 | UNSPEC_VEC_SUBC_U128 | |
204 | UNSPEC_VEC_SUBE_U128 | |
205 | UNSPEC_VEC_SUBEC_U128 | |
206 | ||
207 | UNSPEC_VEC_TEST_MASK | |
208 | ||
209 | UNSPEC_VEC_VFAE | |
210 | UNSPEC_VEC_VFAECC | |
211 | ||
212 | UNSPEC_VEC_VFEE | |
213 | UNSPEC_VEC_VFEECC | |
085261c8 AK |
214 | UNSPEC_VEC_VFENE |
215 | UNSPEC_VEC_VFENECC | |
3af82a61 AK |
216 | |
217 | UNSPEC_VEC_VISTR | |
218 | UNSPEC_VEC_VISTRCC | |
219 | ||
220 | UNSPEC_VEC_VSTRC | |
221 | UNSPEC_VEC_VSTRCCC | |
222 | ||
223 | UNSPEC_VEC_VCDGB | |
224 | UNSPEC_VEC_VCDLGB | |
225 | ||
226 | UNSPEC_VEC_VCGDB | |
227 | UNSPEC_VEC_VCLGDB | |
228 | ||
229 | UNSPEC_VEC_VFIDB | |
230 | ||
231 | UNSPEC_VEC_VLDEB | |
232 | UNSPEC_VEC_VLEDB | |
233 | ||
234 | UNSPEC_VEC_VFTCIDB | |
235 | UNSPEC_VEC_VFTCIDBCC | |
085261c8 | 236 | ]) |
fd3cd001 UW |
237 | |
238 | ;; | |
239 | ;; UNSPEC_VOLATILE usage | |
240 | ;; | |
241 | ||
30a49b23 AK |
242 | (define_c_enum "unspecv" [ |
243 | ; Blockage | |
244 | UNSPECV_BLOCKAGE | |
10bbf137 | 245 | |
2f7e5a0d | 246 | ; TPF Support |
30a49b23 AK |
247 | UNSPECV_TPF_PROLOGUE |
248 | UNSPECV_TPF_EPILOGUE | |
2f7e5a0d | 249 | |
10bbf137 | 250 | ; Literal pool |
30a49b23 AK |
251 | UNSPECV_POOL |
252 | UNSPECV_POOL_SECTION | |
253 | UNSPECV_POOL_ALIGN | |
254 | UNSPECV_POOL_ENTRY | |
255 | UNSPECV_MAIN_POOL | |
fd7643fb UW |
256 | |
257 | ; TLS support | |
30a49b23 | 258 | UNSPECV_SET_TP |
e0374221 AS |
259 | |
260 | ; Atomic Support | |
30a49b23 AK |
261 | UNSPECV_CAS |
262 | UNSPECV_ATOMIC_OP | |
5a3fe9b6 | 263 | |
f8af0e30 DV |
264 | ; Hotpatching (unremovable NOPs) |
265 | UNSPECV_NOP_2_BYTE | |
266 | UNSPECV_NOP_4_BYTE | |
267 | UNSPECV_NOP_6_BYTE | |
268 | ||
5a3fe9b6 AK |
269 | ; Transactional Execution support |
270 | UNSPECV_TBEGIN | |
2561451d | 271 | UNSPECV_TBEGIN_TDB |
5a3fe9b6 AK |
272 | UNSPECV_TBEGINC |
273 | UNSPECV_TEND | |
274 | UNSPECV_TABORT | |
275 | UNSPECV_ETND | |
276 | UNSPECV_NTSTG | |
277 | UNSPECV_PPA | |
004f64e1 AK |
278 | |
279 | ; Set and get floating point control register | |
280 | UNSPECV_SFPC | |
281 | UNSPECV_EFPC | |
4cb4721f MK |
282 | |
283 | ; Split stack support | |
284 | UNSPECV_SPLIT_STACK_CALL | |
285 | UNSPECV_SPLIT_STACK_DATA | |
fd3cd001 UW |
286 | ]) |
287 | ||
ae156f85 AS |
288 | ;; |
289 | ;; Registers | |
290 | ;; | |
291 | ||
35dd9a0e AK |
292 | ; Registers with special meaning |
293 | ||
ae156f85 AS |
294 | (define_constants |
295 | [ | |
296 | ; Sibling call register. | |
297 | (SIBCALL_REGNUM 1) | |
298 | ; Literal pool base register. | |
299 | (BASE_REGNUM 13) | |
300 | ; Return address register. | |
301 | (RETURN_REGNUM 14) | |
302 | ; Condition code register. | |
303 | (CC_REGNUM 33) | |
f4aa3848 | 304 | ; Thread local storage pointer register. |
ae156f85 AS |
305 | (TP_REGNUM 36) |
306 | ]) | |
307 | ||
35dd9a0e AK |
308 | ; Hardware register names |
309 | ||
310 | (define_constants | |
311 | [ | |
312 | ; General purpose registers | |
313 | (GPR0_REGNUM 0) | |
af344a30 | 314 | (GPR1_REGNUM 1) |
82379bdf AK |
315 | (GPR2_REGNUM 2) |
316 | (GPR6_REGNUM 6) | |
35dd9a0e AK |
317 | ; Floating point registers. |
318 | (FPR0_REGNUM 16) | |
2cf4c39e AK |
319 | (FPR1_REGNUM 20) |
320 | (FPR2_REGNUM 17) | |
321 | (FPR3_REGNUM 21) | |
322 | (FPR4_REGNUM 18) | |
323 | (FPR5_REGNUM 22) | |
324 | (FPR6_REGNUM 19) | |
325 | (FPR7_REGNUM 23) | |
326 | (FPR8_REGNUM 24) | |
327 | (FPR9_REGNUM 28) | |
328 | (FPR10_REGNUM 25) | |
329 | (FPR11_REGNUM 29) | |
330 | (FPR12_REGNUM 26) | |
331 | (FPR13_REGNUM 30) | |
332 | (FPR14_REGNUM 27) | |
333 | (FPR15_REGNUM 31) | |
085261c8 AK |
334 | (VR0_REGNUM 16) |
335 | (VR16_REGNUM 38) | |
336 | (VR23_REGNUM 45) | |
337 | (VR24_REGNUM 46) | |
338 | (VR31_REGNUM 53) | |
35dd9a0e AK |
339 | ]) |
340 | ||
341 | ;; | |
342 | ;; PFPO GPR0 argument format | |
343 | ;; | |
344 | ||
345 | (define_constants | |
346 | [ | |
347 | ; PFPO operation type | |
348 | (PFPO_CONVERT 0x1000000) | |
349 | ; PFPO operand types | |
350 | (PFPO_OP_TYPE_SF 0x5) | |
351 | (PFPO_OP_TYPE_DF 0x6) | |
352 | (PFPO_OP_TYPE_TF 0x7) | |
353 | (PFPO_OP_TYPE_SD 0x8) | |
354 | (PFPO_OP_TYPE_DD 0x9) | |
355 | (PFPO_OP_TYPE_TD 0xa) | |
356 | ; Bitposition of operand types | |
357 | (PFPO_OP0_TYPE_SHIFT 16) | |
358 | (PFPO_OP1_TYPE_SHIFT 8) | |
359 | ]) | |
360 | ||
5a3fe9b6 AK |
361 | ; Immediate operands for tbegin and tbeginc |
362 | (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c | |
363 | (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08 | |
fd3cd001 | 364 | |
29a74354 UW |
365 | ;; Instruction operand type as used in the Principles of Operation. |
366 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 367 | |
29a74354 | 368 | (define_attr "op_type" |
085261c8 | 369 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX" |
b628bd8e | 370 | (const_string "NN")) |
9db1d521 | 371 | |
29a74354 | 372 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 373 | |
077dab3b | 374 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 375 | cs,vs,store,sem,idiv, |
ed0e512a | 376 | imulhi,imulsi,imuldi, |
2cdece44 | 377 | branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, |
f61a2c7d AK |
378 | floadtf,floaddf,floadsf,fstoredf,fstoresf, |
379 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 | 380 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
65b1d8ea | 381 | fmadddf,fmaddsf, |
9381e3f1 WG |
382 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, |
383 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
384 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
385 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
386 | ftoidfp, other" | |
29a74354 UW |
387 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
388 | (eq_attr "op_type" "SS") (const_string "cs")] | |
389 | (const_string "integer"))) | |
9db1d521 | 390 | |
29a74354 UW |
391 | ;; Another attribute used for scheduling purposes: |
392 | ;; agen: Instruction uses the address generation unit | |
393 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
394 | |
395 | (define_attr "atype" "agen,reg" | |
c68e7b86 | 396 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR") |
0101708c AS |
397 | (const_string "reg") |
398 | (const_string "agen"))) | |
9db1d521 | 399 | |
9381e3f1 WG |
400 | ;; Properties concerning Z10 execution grouping and value forwarding. |
401 | ;; z10_super: instruction is superscalar. | |
402 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
403 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
404 | ;; target register. It can forward this value to a second instruction that reads | |
405 | ;; the same register if that second instruction is issued in the same group. | |
406 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
407 | ;; instruction in the S pipe writes to the register, then the T instruction | |
408 | ;; can immediately read the new value. | |
409 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
410 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
9381e3f1 WG |
411 | ;; |
412 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
413 | ||
414 | ||
415 | (define_attr "z10prop" "none, | |
416 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
417 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
418 | z10_rec, | |
419 | z10_fr, z10_fr_A3, z10_fr_E1, | |
e3cba5e5 | 420 | z10_c" |
9381e3f1 WG |
421 | (const_string "none")) |
422 | ||
65b1d8ea AK |
423 | ;; Properties concerning Z196 decoding |
424 | ;; z196_alone: must group alone | |
425 | ;; z196_end: ends a group | |
426 | ;; z196_cracked: instruction is cracked or expanded | |
427 | (define_attr "z196prop" "none, | |
428 | z196_alone, z196_ends, | |
429 | z196_cracked" | |
430 | (const_string "none")) | |
9381e3f1 | 431 | |
a9cc3f58 | 432 | (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown")) |
22ac2c2f | 433 | |
9db1d521 HP |
434 | ;; Length in bytes. |
435 | ||
436 | (define_attr "length" "" | |
963fc8d0 AK |
437 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
438 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)] | |
b628bd8e | 439 | (const_int 6))) |
9db1d521 | 440 | |
29a74354 UW |
441 | |
442 | ;; Processor type. This attribute must exactly match the processor_type | |
443 | ;; enumeration in s390.h. The current machine description does not | |
444 | ;; distinguish between g5 and g6, but there are differences between the two | |
445 | ;; CPUs could in theory be modeled. | |
446 | ||
55ac540c | 447 | (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13" |
90c6fd8a | 448 | (const (symbol_ref "s390_tune_attr"))) |
29a74354 | 449 | |
b5e0425c | 450 | (define_attr "cpu_facility" |
55ac540c | 451 | "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec" |
3af8e996 AK |
452 | (const_string "standard")) |
453 | ||
454 | (define_attr "enabled" "" | |
455 | (cond [(eq_attr "cpu_facility" "standard") | |
456 | (const_int 1) | |
457 | ||
458 | (and (eq_attr "cpu_facility" "ieee") | |
d7f99b2c | 459 | (match_test "TARGET_CPU_IEEE_FLOAT")) |
3af8e996 AK |
460 | (const_int 1) |
461 | ||
462 | (and (eq_attr "cpu_facility" "zarch") | |
d7f99b2c | 463 | (match_test "TARGET_ZARCH")) |
3af8e996 AK |
464 | (const_int 1) |
465 | ||
466 | (and (eq_attr "cpu_facility" "longdisp") | |
d7f99b2c | 467 | (match_test "TARGET_LONG_DISPLACEMENT")) |
3af8e996 AK |
468 | (const_int 1) |
469 | ||
470 | (and (eq_attr "cpu_facility" "extimm") | |
d7f99b2c | 471 | (match_test "TARGET_EXTIMM")) |
3af8e996 AK |
472 | (const_int 1) |
473 | ||
474 | (and (eq_attr "cpu_facility" "dfp") | |
d7f99b2c | 475 | (match_test "TARGET_DFP")) |
93538e8e AK |
476 | (const_int 1) |
477 | ||
b5e0425c AK |
478 | (and (eq_attr "cpu_facility" "cpu_zarch") |
479 | (match_test "TARGET_CPU_ZARCH")) | |
480 | (const_int 1) | |
481 | ||
93538e8e | 482 | (and (eq_attr "cpu_facility" "z10") |
d7f99b2c | 483 | (match_test "TARGET_Z10")) |
65b1d8ea AK |
484 | (const_int 1) |
485 | ||
486 | (and (eq_attr "cpu_facility" "z196") | |
d7f99b2c | 487 | (match_test "TARGET_Z196")) |
22ac2c2f AK |
488 | (const_int 1) |
489 | ||
490 | (and (eq_attr "cpu_facility" "zEC12") | |
491 | (match_test "TARGET_ZEC12")) | |
55ac540c AK |
492 | (const_int 1) |
493 | ||
494 | (and (eq_attr "cpu_facility" "vec") | |
495 | (match_test "TARGET_VX")) | |
3af8e996 AK |
496 | (const_int 1)] |
497 | (const_int 0))) | |
498 | ||
29a74354 UW |
499 | ;; Pipeline description for z900. For lack of anything better, |
500 | ;; this description is also used for the g5 and g6. | |
501 | (include "2064.md") | |
502 | ||
3443392a | 503 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
504 | (include "2084.md") |
505 | ||
9381e3f1 WG |
506 | ;; Pipeline description for z10 |
507 | (include "2097.md") | |
508 | ||
65b1d8ea AK |
509 | ;; Pipeline description for z196 |
510 | (include "2817.md") | |
511 | ||
22ac2c2f AK |
512 | ;; Pipeline description for zEC12 |
513 | (include "2827.md") | |
514 | ||
23902021 AK |
515 | ;; Pipeline description for z13 |
516 | (include "2964.md") | |
517 | ||
0bfc3f69 AS |
518 | ;; Predicates |
519 | (include "predicates.md") | |
520 | ||
cd8dc1f9 WG |
521 | ;; Constraint definitions |
522 | (include "constraints.md") | |
523 | ||
a8ba31f2 EC |
524 | ;; Other includes |
525 | (include "tpf.md") | |
f52c81dd | 526 | |
3abcb3a7 | 527 | ;; Iterators |
f52c81dd | 528 | |
085261c8 AK |
529 | (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF]) |
530 | ||
3abcb3a7 | 531 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 532 | ;; same template. |
f4aa3848 | 533 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
0387c142 | 534 | (SD "TARGET_HARD_DFP")]) |
3abcb3a7 HPN |
535 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
536 | (define_mode_iterator BFP [TF DF SF]) | |
537 | (define_mode_iterator DFP [TD DD]) | |
538 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
539 | (define_mode_iterator DSF [DF SF]) | |
540 | (define_mode_iterator SD_SF [SF SD]) | |
541 | (define_mode_iterator DD_DF [DF DD]) | |
542 | (define_mode_iterator TD_TF [TF TD]) | |
543 | ||
3abcb3a7 | 544 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 545 | ;; from the same template. |
9602b6a1 | 546 | (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) |
78ce265b | 547 | (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) |
3abcb3a7 | 548 | (define_mode_iterator DSI [DI SI]) |
78ce265b | 549 | (define_mode_iterator TDI [TI DI]) |
9db2f16d | 550 | |
3abcb3a7 | 551 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 552 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 | 553 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
9db2f16d | 554 | |
78ce265b RH |
555 | ;; These macros refer to the actual word_mode of the configuration. |
556 | ;; This is equal to Pmode except on 31-bit machines in zarch mode. | |
9602b6a1 AK |
557 | (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) |
558 | (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) | |
559 | ||
6e0d70c9 AK |
560 | ;; Used by the umul pattern to express modes having half the size. |
561 | (define_mode_attr DWH [(TI "DI") (DI "SI")]) | |
562 | (define_mode_attr dwh [(TI "di") (DI "si")]) | |
563 | ||
3abcb3a7 | 564 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 565 | ;; the same template. |
3abcb3a7 | 566 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 567 | |
3abcb3a7 | 568 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 569 | ;; same template. |
9602b6a1 | 570 | (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) |
78ce265b | 571 | (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) |
342cf42b | 572 | |
3abcb3a7 | 573 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 574 | ;; the same template. |
3abcb3a7 | 575 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 576 | |
d12a76f3 | 577 | ;; This iterator allows r[ox]sbg to be defined with the same template |
571e408a RH |
578 | (define_code_iterator IXOR [ior xor]) |
579 | ||
d12a76f3 AK |
580 | ;; This iterator is used to expand the patterns for the nearest |
581 | ;; integer functions. | |
582 | (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC | |
583 | UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL | |
584 | UNSPEC_FPINT_NEARBYINT]) | |
585 | (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor") | |
586 | (UNSPEC_FPINT_BTRUNC "btrunc") | |
587 | (UNSPEC_FPINT_ROUND "round") | |
588 | (UNSPEC_FPINT_CEIL "ceil") | |
589 | (UNSPEC_FPINT_NEARBYINT "nearbyint")]) | |
590 | (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7") | |
591 | (UNSPEC_FPINT_BTRUNC "5") | |
592 | (UNSPEC_FPINT_ROUND "1") | |
593 | (UNSPEC_FPINT_CEIL "6") | |
594 | (UNSPEC_FPINT_NEARBYINT "0")]) | |
595 | ||
3abcb3a7 HPN |
596 | ;; This iterator and attribute allow to combine most atomic operations. |
597 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
65b1d8ea | 598 | (define_code_iterator ATOMIC_Z196 [and ior xor plus]) |
cf5b43b0 | 599 | (define_code_attr atomic [(and "and") (ior "or") (xor "xor") |
45d18331 | 600 | (plus "add") (minus "sub") (mult "nand")]) |
65b1d8ea | 601 | (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) |
45d18331 | 602 | |
f4aa3848 | 603 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
609e7e80 AK |
604 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. |
605 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) | |
f337b930 | 606 | |
f4aa3848 AK |
607 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
608 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
609e7e80 AK |
609 | ;; SDmode. |
610 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 611 | |
609e7e80 | 612 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
613 | ;; Likewise for "<RXe>". |
614 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
615 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
616 | ||
609e7e80 | 617 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 618 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
619 | ;; dfp variants in a single insn definition. |
620 | ||
3abcb3a7 | 621 | ;; This attribute is used to set op_type accordingly. |
f4aa3848 | 622 | (define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR") |
609e7e80 AK |
623 | (DD "RRR") (SD "RRR")]) |
624 | ||
f4aa3848 | 625 | ;; This attribute is used in the operand constraint list in order to have the |
609e7e80 AK |
626 | ;; first and the second operand match for bfp modes. |
627 | (define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")]) | |
628 | ||
6e5b5de8 AK |
629 | ;; This attribute is used to merge the scalar vector instructions into |
630 | ;; the FP patterns. For non-supported modes (all but DF) it expands | |
631 | ;; to constraints which are supposed to be matched by an earlier | |
632 | ;; variant. | |
633 | (define_mode_attr v0 [(TF "0") (DF "v") (SF "0") (TD "0") (DD "0") (DD "0") (TI "0") (DI "v") (SI "0")]) | |
634 | (define_mode_attr vf [(TF "f") (DF "v") (SF "f") (TD "f") (DD "f") (DD "f") (TI "f") (DI "v") (SI "f")]) | |
635 | (define_mode_attr vd [(TF "d") (DF "v") (SF "d") (TD "d") (DD "d") (DD "d") (TI "d") (DI "v") (SI "d")]) | |
636 | ||
f4aa3848 | 637 | ;; This attribute is used in the operand list of the instruction to have an |
609e7e80 AK |
638 | ;; additional operand for the dfp instructions. |
639 | (define_mode_attr op1 [(TF "") (DF "") (SF "") | |
640 | (TD "%1,") (DD "%1,") (SD "%1,")]) | |
641 | ||
f5905b37 | 642 | |
85dae55a AK |
643 | ;; This attribute is used in the operand constraint list |
644 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
645 | ;; TFmode values are represented by a fp register pair. Since the | |
646 | ;; sign bit instructions only handle single source and target fp registers | |
647 | ;; these instructions can only be used for TFmode values if the source and | |
648 | ;; target operand uses the same fp register. | |
649 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
650 | ||
609e7e80 AK |
651 | ;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise. |
652 | ;; This is used to disable the memory alternative in TFmode patterns. | |
653 | (define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")]) | |
654 | ||
3abcb3a7 | 655 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
656 | ;; within instruction mnemonics. |
657 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
658 | ||
0387c142 WG |
659 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
660 | ;; modes and to an empty string for bfp modes. | |
661 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
662 | ||
1b48c8cc AS |
663 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
664 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
665 | ;; version only operates on one register. | |
666 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
667 | ||
668 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
669 | ;; version only operates on one register. The DImode version needs an additional | |
670 | ;; register for the assembler output. | |
671 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
672 | |
673 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
674 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
675 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
676 | ||
677 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 678 | ;; pattern itself and the corresponding function calls. |
f337b930 | 679 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
680 | |
681 | ;; This attribute handles differences in the instruction 'type' and will result | |
682 | ;; in "RRE" for DImode and "RR" for SImode. | |
683 | (define_mode_attr E [(DI "E") (SI "")]) | |
684 | ||
3298c037 AK |
685 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
686 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
687 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
688 | ||
8006eaa6 AS |
689 | ;; This attribute handles differences in the instruction 'type' and will result |
690 | ;; in "RSE" for TImode and "RS" for DImode. | |
691 | (define_mode_attr TE [(TI "E") (DI "")]) | |
692 | ||
9a91a21f AS |
693 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
694 | ;; and "lcr" in SImode. | |
695 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 696 | |
3298c037 AK |
697 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
698 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
699 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
700 | ;; variant for long displacements. | |
701 | (define_mode_attr y [(DI "g") (SI "y")]) | |
702 | ||
9602b6a1 | 703 | ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode |
8006eaa6 AS |
704 | ;; and "cds" in DImode. |
705 | (define_mode_attr tg [(TI "g") (DI "")]) | |
706 | ||
78ce265b RH |
707 | ;; In TDI templates, a string like "c<d>sg". |
708 | (define_mode_attr td [(TI "d") (DI "")]) | |
709 | ||
2f8f8434 AS |
710 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
711 | ;; and "cfdbr" in SImode. | |
712 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
713 | ||
65b1d8ea AK |
714 | ;; In GPR templates, a string like sll<gk> will expand to sllg for DI |
715 | ;; and sllk for SI. This way it is possible to merge the new z196 SI | |
716 | ;; 3 operands shift instructions into the existing patterns. | |
717 | (define_mode_attr gk [(DI "g") (SI "k")]) | |
718 | ||
f52c81dd AS |
719 | ;; ICM mask required to load MODE value into the lowest subreg |
720 | ;; of a SImode register. | |
721 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
722 | ||
f6ee577c AS |
723 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
724 | ;; HImode and "llgc" in QImode. | |
725 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
726 | ||
a1aed706 AS |
727 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
728 | ;; in SImode. | |
729 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
730 | ||
609e7e80 AK |
731 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
732 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
733 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
734 | ||
f52c81dd AS |
735 | ;; Maximum unsigned integer that fits in MODE. |
736 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
737 | ||
75ca1b39 RH |
738 | ;; Start and end field computations for RISBG et al. |
739 | (define_mode_attr bfstart [(DI "s") (SI "t")]) | |
740 | (define_mode_attr bfend [(DI "e") (SI "f")]) | |
741 | ||
2542ef05 RH |
742 | ;; In place of GET_MODE_BITSIZE (<MODE>mode) |
743 | (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) | |
744 | ||
da0dcab1 DV |
745 | ;; In place of GET_MODE_SIZE (<MODE>mode) |
746 | (define_mode_attr modesize [(DI "8") (SI "4")]) | |
747 | ||
177bc204 RS |
748 | ;; Allow return and simple_return to be defined from a single template. |
749 | (define_code_iterator ANY_RETURN [return simple_return]) | |
750 | ||
6e5b5de8 AK |
751 | |
752 | ||
753 | ; Condition code modes generated by vector fp comparisons. These will | |
754 | ; be used also in single element mode. | |
755 | (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE]) | |
756 | ; Used with VFCMP to expand part of the mnemonic | |
757 | ; For fp we have a mismatch: eq in the insn name - e in asm | |
758 | (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) | |
3af82a61 | 759 | (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")]) |
6e5b5de8 AK |
760 | |
761 | ||
085261c8 AK |
762 | (include "vector.md") |
763 | ||
9db1d521 HP |
764 | ;; |
765 | ;;- Compare instructions. | |
766 | ;; | |
767 | ||
07893d4f | 768 | ; Test-under-Mask instructions |
9db1d521 | 769 | |
07893d4f | 770 | (define_insn "*tmqi_mem" |
ae156f85 | 771 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
772 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
773 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
774 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 775 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 776 | "@ |
fc0ea003 UW |
777 | tm\t%S0,%b1 |
778 | tmy\t%S0,%b1" | |
9381e3f1 WG |
779 | [(set_attr "op_type" "SI,SIY") |
780 | (set_attr "z10prop" "z10_super,z10_super")]) | |
9db1d521 | 781 | |
05b9aaaa | 782 | (define_insn "*tmdi_reg" |
ae156f85 | 783 | [(set (reg CC_REGNUM) |
f19a9af7 | 784 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 785 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
786 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
787 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
9602b6a1 | 788 | "TARGET_ZARCH |
3ed99cc9 | 789 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
790 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
791 | "@ | |
792 | tmhh\t%0,%i1 | |
793 | tmhl\t%0,%i1 | |
794 | tmlh\t%0,%i1 | |
795 | tmll\t%0,%i1" | |
9381e3f1 WG |
796 | [(set_attr "op_type" "RI") |
797 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
798 | |
799 | (define_insn "*tmsi_reg" | |
ae156f85 | 800 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
801 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
802 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
803 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 804 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
805 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
806 | "@ | |
807 | tmh\t%0,%i1 | |
808 | tml\t%0,%i1" | |
729e750f WG |
809 | [(set_attr "op_type" "RI") |
810 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 811 | |
f52c81dd | 812 | (define_insn "*tm<mode>_full" |
ae156f85 | 813 | [(set (reg CC_REGNUM) |
f52c81dd AS |
814 | (compare (match_operand:HQI 0 "register_operand" "d") |
815 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 816 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 817 | "tml\t%0,<max_uint>" |
729e750f WG |
818 | [(set_attr "op_type" "RI") |
819 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 820 | |
07893d4f | 821 | |
08a5aaa2 | 822 | ; |
07893d4f | 823 | ; Load-and-Test instructions |
08a5aaa2 AS |
824 | ; |
825 | ||
c0220ea4 | 826 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
827 | |
828 | (define_insn "*tstdi_sign" | |
ae156f85 | 829 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
830 | (compare |
831 | (ashiftrt:DI | |
832 | (ashift:DI | |
833 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0) | |
834 | (const_int 32)) (const_int 32)) | |
835 | (match_operand:DI 1 "const0_operand" ""))) | |
836 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f | 837 | (sign_extend:DI (match_dup 0)))] |
9602b6a1 | 838 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" |
963fc8d0 AK |
839 | "ltgfr\t%2,%0 |
840 | ltgf\t%2,%0" | |
841 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
842 | (set_attr "cpu_facility" "*,z10") |
843 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 844 | |
43a09b63 | 845 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 846 | (define_insn "*tst<mode>_extimm" |
ec24698e | 847 | [(set (reg CC_REGNUM) |
fb492564 | 848 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
849 | (match_operand:GPR 1 "const0_operand" ""))) |
850 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 851 | (match_dup 0))] |
08a5aaa2 | 852 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 853 | "@ |
08a5aaa2 AS |
854 | lt<g>r\t%2,%0 |
855 | lt<g>\t%2,%0" | |
9381e3f1 | 856 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 857 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 858 | |
43a09b63 | 859 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 860 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 861 | [(set (reg CC_REGNUM) |
fb492564 | 862 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") |
08a5aaa2 AS |
863 | (match_operand:GPR 1 "const0_operand" ""))) |
864 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
865 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 866 | "@ |
08a5aaa2 AS |
867 | lt<g>r\t%0,%0 |
868 | lt<g>\t%2,%0" | |
9381e3f1 | 869 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 870 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 871 | |
07893d4f | 872 | (define_insn "*tstdi" |
ae156f85 | 873 | [(set (reg CC_REGNUM) |
07893d4f UW |
874 | (compare (match_operand:DI 0 "register_operand" "d") |
875 | (match_operand:DI 1 "const0_operand" ""))) | |
876 | (set (match_operand:DI 2 "register_operand" "=d") | |
877 | (match_dup 0))] | |
9602b6a1 | 878 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 879 | "ltgr\t%2,%0" |
9381e3f1 WG |
880 | [(set_attr "op_type" "RRE") |
881 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 882 | |
07893d4f | 883 | (define_insn "*tstsi" |
ae156f85 | 884 | [(set (reg CC_REGNUM) |
d3632d41 | 885 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 886 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 887 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 888 | (match_dup 0))] |
ec24698e | 889 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 890 | "@ |
d40c829f | 891 | ltr\t%2,%0 |
fc0ea003 UW |
892 | icm\t%2,15,%S0 |
893 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
894 | [(set_attr "op_type" "RR,RS,RSY") |
895 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 896 | |
07893d4f | 897 | (define_insn "*tstsi_cconly" |
ae156f85 | 898 | [(set (reg CC_REGNUM) |
d3632d41 | 899 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 900 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 901 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
902 | "s390_match_ccmode(insn, CCSmode)" |
903 | "@ | |
d40c829f | 904 | ltr\t%0,%0 |
fc0ea003 UW |
905 | icm\t%2,15,%S0 |
906 | icmy\t%2,15,%S0" | |
9381e3f1 WG |
907 | [(set_attr "op_type" "RR,RS,RSY") |
908 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 909 | |
08a5aaa2 AS |
910 | (define_insn "*tstdi_cconly_31" |
911 | [(set (reg CC_REGNUM) | |
912 | (compare (match_operand:DI 0 "register_operand" "d") | |
913 | (match_operand:DI 1 "const0_operand" "")))] | |
9602b6a1 | 914 | "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" |
08a5aaa2 AS |
915 | "srda\t%0,0" |
916 | [(set_attr "op_type" "RS") | |
917 | (set_attr "atype" "reg")]) | |
918 | ||
43a09b63 | 919 | ; ltr, ltgr |
08a5aaa2 | 920 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 921 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
922 | (compare (match_operand:GPR 0 "register_operand" "d") |
923 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 924 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 925 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
926 | [(set_attr "op_type" "RR<E>") |
927 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 928 | |
c0220ea4 | 929 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 930 | |
f52c81dd | 931 | (define_insn "*tst<mode>CCT" |
ae156f85 | 932 | [(set (reg CC_REGNUM) |
f52c81dd AS |
933 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
934 | (match_operand:HQI 1 "const0_operand" ""))) | |
935 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
936 | (match_dup 0))] |
937 | "s390_match_ccmode(insn, CCTmode)" | |
938 | "@ | |
f52c81dd AS |
939 | icm\t%2,<icm_lo>,%S0 |
940 | icmy\t%2,<icm_lo>,%S0 | |
941 | tml\t%0,<max_uint>" | |
9381e3f1 WG |
942 | [(set_attr "op_type" "RS,RSY,RI") |
943 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 UW |
944 | |
945 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 946 | [(set (reg CC_REGNUM) |
d3632d41 | 947 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 948 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 949 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
950 | "s390_match_ccmode(insn, CCTmode)" |
951 | "@ | |
fc0ea003 UW |
952 | icm\t%2,3,%S0 |
953 | icmy\t%2,3,%S0 | |
d40c829f | 954 | tml\t%0,65535" |
9381e3f1 WG |
955 | [(set_attr "op_type" "RS,RSY,RI") |
956 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) | |
3af97654 | 957 | |
3af97654 | 958 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 959 | [(set (reg CC_REGNUM) |
d3632d41 | 960 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
961 | (match_operand:QI 1 "const0_operand" "")))] |
962 | "s390_match_ccmode(insn, CCTmode)" | |
963 | "@ | |
fc0ea003 UW |
964 | cli\t%S0,0 |
965 | cliy\t%S0,0 | |
d40c829f | 966 | tml\t%0,255" |
9381e3f1 | 967 | [(set_attr "op_type" "SI,SIY,RI") |
729e750f | 968 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 969 | |
f52c81dd | 970 | (define_insn "*tst<mode>" |
ae156f85 | 971 | [(set (reg CC_REGNUM) |
f52c81dd AS |
972 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
973 | (match_operand:HQI 1 "const0_operand" ""))) | |
974 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
975 | (match_dup 0))] |
976 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 977 | "@ |
f52c81dd AS |
978 | icm\t%2,<icm_lo>,%S0 |
979 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
980 | [(set_attr "op_type" "RS,RSY") |
981 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 982 | |
f52c81dd | 983 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 984 | [(set (reg CC_REGNUM) |
f52c81dd AS |
985 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
986 | (match_operand:HQI 1 "const0_operand" ""))) | |
987 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 988 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 989 | "@ |
f52c81dd AS |
990 | icm\t%2,<icm_lo>,%S0 |
991 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 WG |
992 | [(set_attr "op_type" "RS,RSY") |
993 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
d3632d41 | 994 | |
9db1d521 | 995 | |
575f7c2b UW |
996 | ; Compare (equality) instructions |
997 | ||
998 | (define_insn "*cmpdi_cct" | |
ae156f85 | 999 | [(set (reg CC_REGNUM) |
ec24698e | 1000 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
fb492564 | 1001 | (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))] |
9602b6a1 | 1002 | "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" |
575f7c2b UW |
1003 | "@ |
1004 | cgr\t%0,%1 | |
f4f41b4e | 1005 | cghi\t%0,%h1 |
ec24698e | 1006 | cgfi\t%0,%1 |
575f7c2b | 1007 | cg\t%0,%1 |
19b63d8e | 1008 | #" |
9381e3f1 WG |
1009 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
1010 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
1011 | |
1012 | (define_insn "*cmpsi_cct" | |
ae156f85 | 1013 | [(set (reg CC_REGNUM) |
ec24698e UW |
1014 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
1015 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 1016 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
1017 | "@ |
1018 | cr\t%0,%1 | |
f4f41b4e | 1019 | chi\t%0,%h1 |
ec24698e | 1020 | cfi\t%0,%1 |
575f7c2b UW |
1021 | c\t%0,%1 |
1022 | cy\t%0,%1 | |
19b63d8e | 1023 | #" |
9381e3f1 | 1024 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
e3cba5e5 | 1025 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) |
575f7c2b | 1026 | |
07893d4f | 1027 | ; Compare (signed) instructions |
4023fb28 | 1028 | |
07893d4f | 1029 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 1030 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1031 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
1032 | "d,RT,b")) | |
1033 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
9602b6a1 | 1034 | "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" |
4023fb28 | 1035 | "@ |
d40c829f | 1036 | cgfr\t%0,%1 |
963fc8d0 AK |
1037 | cgf\t%0,%1 |
1038 | cgfrl\t%0,%1" | |
1039 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 1040 | (set_attr "z10prop" "z10_c,*,*") |
963fc8d0 | 1041 | (set_attr "type" "*,*,larl")]) |
4023fb28 | 1042 | |
9381e3f1 WG |
1043 | |
1044 | ||
07893d4f | 1045 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 1046 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1047 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
1048 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 1049 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 1050 | "@ |
d40c829f | 1051 | ch\t%0,%1 |
963fc8d0 AK |
1052 | chy\t%0,%1 |
1053 | chrl\t%0,%1" | |
1054 | [(set_attr "op_type" "RX,RXY,RIL") | |
1055 | (set_attr "cpu_facility" "*,*,z10") | |
65b1d8ea AK |
1056 | (set_attr "type" "*,*,larl") |
1057 | (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")]) | |
963fc8d0 AK |
1058 | |
1059 | (define_insn "*cmphi_ccs_z10" | |
1060 | [(set (reg CC_REGNUM) | |
1061 | (compare (match_operand:HI 0 "s_operand" "Q") | |
1062 | (match_operand:HI 1 "immediate_operand" "K")))] | |
1063 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
1064 | "chhsi\t%0,%1" | |
65b1d8ea AK |
1065 | [(set_attr "op_type" "SIL") |
1066 | (set_attr "z196prop" "z196_cracked")]) | |
963fc8d0 AK |
1067 | |
1068 | (define_insn "*cmpdi_ccs_signhi_rl" | |
1069 | [(set (reg CC_REGNUM) | |
1070 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b")) | |
1071 | (match_operand:GPR 0 "register_operand" "d,d")))] | |
1072 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
1073 | "@ | |
1074 | cgh\t%0,%1 | |
1075 | cghrl\t%0,%1" | |
1076 | [(set_attr "op_type" "RXY,RIL") | |
1077 | (set_attr "type" "*,larl")]) | |
4023fb28 | 1078 | |
963fc8d0 | 1079 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 1080 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1081 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1082 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
1083 | "d,d,Q, d,d,d,d") | |
1084 | (match_operand:GPR 1 "general_operand" | |
1085 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 1086 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 1087 | "@ |
3298c037 AK |
1088 | c<g>r\t%0,%1 |
1089 | c<g>hi\t%0,%h1 | |
963fc8d0 | 1090 | c<g>hsi\t%0,%h1 |
3298c037 AK |
1091 | c<g>fi\t%0,%1 |
1092 | c<g>\t%0,%1 | |
963fc8d0 AK |
1093 | c<y>\t%0,%1 |
1094 | c<g>rl\t%0,%1" | |
1095 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
1096 | (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10") | |
9381e3f1 WG |
1097 | (set_attr "type" "*,*,*,*,*,*,larl") |
1098 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) | |
c7453384 | 1099 | |
07893d4f UW |
1100 | |
1101 | ; Compare (unsigned) instructions | |
9db1d521 | 1102 | |
963fc8d0 AK |
1103 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
1104 | [(set (reg CC_REGNUM) | |
1105 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
1106 | "larl_operand" "X"))) | |
1107 | (match_operand:SI 0 "register_operand" "d")))] | |
1108 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1109 | "clhrl\t%0,%1" | |
1110 | [(set_attr "op_type" "RIL") | |
729e750f WG |
1111 | (set_attr "type" "larl") |
1112 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 AK |
1113 | |
1114 | ; clhrl, clghrl | |
1115 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
1116 | [(set (reg CC_REGNUM) | |
1117 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
1118 | "larl_operand" "X"))) | |
1119 | (match_operand:GPR 0 "register_operand" "d")))] | |
1120 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1121 | "cl<g>hrl\t%0,%1" | |
1122 | [(set_attr "op_type" "RIL") | |
9381e3f1 WG |
1123 | (set_attr "type" "larl") |
1124 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 | 1125 | |
07893d4f | 1126 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 1127 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1128 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
1129 | "d,RT,b")) | |
1130 | (match_operand:DI 0 "register_operand" "d, d,d")))] | |
9602b6a1 | 1131 | "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" |
07893d4f | 1132 | "@ |
d40c829f | 1133 | clgfr\t%0,%1 |
963fc8d0 AK |
1134 | clgf\t%0,%1 |
1135 | clgfrl\t%0,%1" | |
1136 | [(set_attr "op_type" "RRE,RXY,RIL") | |
1137 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 WG |
1138 | (set_attr "type" "*,*,larl") |
1139 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) | |
9db1d521 | 1140 | |
07893d4f | 1141 | (define_insn "*cmpdi_ccu" |
ae156f85 | 1142 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1143 | (compare (match_operand:DI 0 "nonimmediate_operand" |
1144 | "d, d,d,Q, d, Q,BQ") | |
1145 | (match_operand:DI 1 "general_operand" | |
1146 | "d,Op,b,D,RT,BQ,Q")))] | |
9602b6a1 | 1147 | "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" |
07893d4f | 1148 | "@ |
d40c829f | 1149 | clgr\t%0,%1 |
ec24698e | 1150 | clgfi\t%0,%1 |
963fc8d0 AK |
1151 | clgrl\t%0,%1 |
1152 | clghsi\t%0,%x1 | |
575f7c2b | 1153 | clg\t%0,%1 |
e221ef54 | 1154 | # |
19b63d8e | 1155 | #" |
963fc8d0 AK |
1156 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
1157 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 WG |
1158 | (set_attr "type" "*,*,larl,*,*,*,*") |
1159 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 1160 | |
07893d4f | 1161 | (define_insn "*cmpsi_ccu" |
ae156f85 | 1162 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1163 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
1164 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 1165 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 1166 | "@ |
d40c829f | 1167 | clr\t%0,%1 |
ec24698e | 1168 | clfi\t%0,%o1 |
963fc8d0 AK |
1169 | clrl\t%0,%1 |
1170 | clfhsi\t%0,%x1 | |
d40c829f | 1171 | cl\t%0,%1 |
575f7c2b | 1172 | cly\t%0,%1 |
e221ef54 | 1173 | # |
19b63d8e | 1174 | #" |
963fc8d0 AK |
1175 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
1176 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*") | |
9381e3f1 WG |
1177 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
1178 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 1179 | |
07893d4f | 1180 | (define_insn "*cmphi_ccu" |
ae156f85 | 1181 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1182 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
1183 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 1184 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1185 | && !register_operand (operands[1], HImode)" |
d3632d41 | 1186 | "@ |
fc0ea003 UW |
1187 | clm\t%0,3,%S1 |
1188 | clmy\t%0,3,%S1 | |
963fc8d0 | 1189 | clhhsi\t%0,%1 |
e221ef54 | 1190 | # |
19b63d8e | 1191 | #" |
963fc8d0 | 1192 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
9381e3f1 WG |
1193 | (set_attr "cpu_facility" "*,*,z10,*,*") |
1194 | (set_attr "z10prop" "*,*,z10_super,*,*")]) | |
9db1d521 HP |
1195 | |
1196 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 1197 | [(set (reg CC_REGNUM) |
e221ef54 UW |
1198 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
1199 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 1200 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1201 | && !register_operand (operands[1], QImode)" |
d3632d41 | 1202 | "@ |
fc0ea003 UW |
1203 | clm\t%0,1,%S1 |
1204 | clmy\t%0,1,%S1 | |
1205 | cli\t%S0,%b1 | |
1206 | cliy\t%S0,%b1 | |
e221ef54 | 1207 | # |
19b63d8e | 1208 | #" |
9381e3f1 WG |
1209 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
1210 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) | |
9db1d521 HP |
1211 | |
1212 | ||
19b63d8e UW |
1213 | ; Block compare (CLC) instruction patterns. |
1214 | ||
1215 | (define_insn "*clc" | |
ae156f85 | 1216 | [(set (reg CC_REGNUM) |
d4f52f0e | 1217 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
1218 | (match_operand:BLK 1 "memory_operand" "Q"))) |
1219 | (use (match_operand 2 "const_int_operand" "n"))] | |
1220 | "s390_match_ccmode (insn, CCUmode) | |
1221 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1222 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 1223 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1224 | |
1225 | (define_split | |
ae156f85 | 1226 | [(set (reg CC_REGNUM) |
19b63d8e UW |
1227 | (compare (match_operand 0 "memory_operand" "") |
1228 | (match_operand 1 "memory_operand" "")))] | |
1229 | "reload_completed | |
1230 | && s390_match_ccmode (insn, CCUmode) | |
1231 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1232 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1233 | [(parallel | |
1234 | [(set (match_dup 0) (match_dup 1)) | |
1235 | (use (match_dup 2))])] | |
1236 | { | |
1237 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1238 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1239 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1240 | ||
1241 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
1242 | operands[0], operands[1]); | |
1243 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
1244 | }) | |
1245 | ||
1246 | ||
609e7e80 | 1247 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 1248 | |
609e7e80 | 1249 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 1250 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 1251 | [(set (reg CC_REGNUM) |
609e7e80 AK |
1252 | (compare (match_operand:FP 0 "register_operand" "f") |
1253 | (match_operand:FP 1 "const0_operand" "")))] | |
142cd70f | 1254 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 1255 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 1256 | [(set_attr "op_type" "RRE") |
9381e3f1 | 1257 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1258 | |
be5de7a1 | 1259 | ; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb |
f5905b37 | 1260 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1261 | [(set (reg CC_REGNUM) |
609e7e80 AK |
1262 | (compare (match_operand:FP 0 "register_operand" "f,f") |
1263 | (match_operand:FP 1 "general_operand" "f,<Rf>")))] | |
142cd70f | 1264 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 1265 | "@ |
609e7e80 | 1266 | c<xde><bt>r\t%0,%1 |
f61a2c7d | 1267 | c<xde>b\t%0,%1" |
077dab3b | 1268 | [(set_attr "op_type" "RRE,RXE") |
9381e3f1 | 1269 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1270 | |
6e5b5de8 AK |
1271 | ; wfcedbs, wfchdbs, wfchedbs |
1272 | (define_insn "*vec_cmp<insn_cmp>df_cconly" | |
1273 | [(set (reg:VFCMP CC_REGNUM) | |
1274 | (compare:VFCMP (match_operand:DF 0 "register_operand" "v") | |
1275 | (match_operand:DF 1 "register_operand" "v"))) | |
1276 | (clobber (match_scratch:V2DI 2 "=v"))] | |
1277 | "TARGET_Z13 && TARGET_HARD_FLOAT" | |
1278 | "wfc<asm_fcmp>dbs\t%v2,%v0,%v1" | |
1279 | [(set_attr "op_type" "VRR")]) | |
963fc8d0 AK |
1280 | |
1281 | ; Compare and Branch instructions | |
1282 | ||
1283 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
1284 | ; The following instructions do a complementary access of their second |
1285 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
1286 | (define_insn "*cmp_and_br_signed_<mode>" |
1287 | [(set (pc) | |
1288 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1289 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1290 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1291 | (label_ref (match_operand 3 "" "")) | |
1292 | (pc))) | |
1293 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1294 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1295 | { |
1296 | if (get_attr_length (insn) == 6) | |
1297 | return which_alternative ? | |
1298 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1299 | else | |
1300 | return which_alternative ? | |
1301 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1302 | } | |
1303 | [(set_attr "op_type" "RIE") | |
1304 | (set_attr "type" "branch") | |
e3cba5e5 | 1305 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1306 | (set (attr "length") |
1307 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1308 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1309 | ; 10 byte for cgr/jg | |
1310 | ||
1311 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1312 | ; The following instructions do a complementary access of their second |
1313 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1314 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1315 | [(set (pc) | |
1316 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1317 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1318 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1319 | (label_ref (match_operand 3 "" "")) | |
1320 | (pc))) | |
1321 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1322 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1323 | { |
1324 | if (get_attr_length (insn) == 6) | |
1325 | return which_alternative ? | |
1326 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1327 | else | |
1328 | return which_alternative ? | |
1329 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1330 | } | |
1331 | [(set_attr "op_type" "RIE") | |
1332 | (set_attr "type" "branch") | |
e3cba5e5 | 1333 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1334 | (set (attr "length") |
1335 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1336 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1337 | ; 10 byte for clgr/jg | |
1338 | ||
b0f86a7e AK |
1339 | ; And now the same two patterns as above but with a negated CC mask. |
1340 | ||
1341 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1342 | ; The following instructions do a complementary access of their second | |
1343 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1344 | (define_insn "*icmp_and_br_signed_<mode>" | |
1345 | [(set (pc) | |
1346 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1347 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1348 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1349 | (pc) | |
1350 | (label_ref (match_operand 3 "" "")))) | |
1351 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1352 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1353 | { |
1354 | if (get_attr_length (insn) == 6) | |
1355 | return which_alternative ? | |
1356 | "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; | |
1357 | else | |
1358 | return which_alternative ? | |
1359 | "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; | |
1360 | } | |
1361 | [(set_attr "op_type" "RIE") | |
1362 | (set_attr "type" "branch") | |
1363 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1364 | (set (attr "length") | |
1365 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1366 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1367 | ; 10 byte for cgr/jg | |
1368 | ||
1369 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1370 | ; The following instructions do a complementary access of their second | |
1371 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
1372 | (define_insn "*icmp_and_br_unsigned_<mode>" | |
1373 | [(set (pc) | |
1374 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1375 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1376 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1377 | (pc) | |
1378 | (label_ref (match_operand 3 "" "")))) | |
1379 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1380 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1381 | { |
1382 | if (get_attr_length (insn) == 6) | |
1383 | return which_alternative ? | |
1384 | "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; | |
1385 | else | |
1386 | return which_alternative ? | |
1387 | "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; | |
1388 | } | |
1389 | [(set_attr "op_type" "RIE") | |
1390 | (set_attr "type" "branch") | |
1391 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1392 | (set (attr "length") | |
1393 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1394 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1395 | ; 10 byte for clgr/jg | |
1396 | ||
9db1d521 HP |
1397 | ;; |
1398 | ;;- Move instructions. | |
1399 | ;; | |
1400 | ||
1401 | ; | |
1402 | ; movti instruction pattern(s). | |
1403 | ; | |
1404 | ||
085261c8 AK |
1405 | ; FIXME: More constants are possible by enabling jxx, jyy constraints |
1406 | ; for TImode (use double-int for the calculations) | |
9db1d521 | 1407 | (define_insn "movti" |
085261c8 AK |
1408 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,v, v, v,v,d, v,QR, d,o") |
1409 | (match_operand:TI 1 "general_operand" "QS, d,v,j00,jm1,d,v,QR, v,dPRT,d"))] | |
9602b6a1 | 1410 | "TARGET_ZARCH" |
4023fb28 | 1411 | "@ |
fc0ea003 UW |
1412 | lmg\t%0,%N0,%S1 |
1413 | stmg\t%1,%N1,%S0 | |
085261c8 AK |
1414 | vlr\t%v0,%v1 |
1415 | vzero\t%v0 | |
1416 | vone\t%v0 | |
1417 | vlvgp\t%v0,%1,%N1 | |
1418 | # | |
1419 | vl\t%v0,%1 | |
1420 | vst\t%v1,%0 | |
4023fb28 | 1421 | # |
19b63d8e | 1422 | #" |
085261c8 AK |
1423 | [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*") |
1424 | (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*") | |
1425 | (set_attr "cpu_facility" "*,*,vec,vec,vec,vec,vec,vec,vec,*,*")]) | |
4023fb28 UW |
1426 | |
1427 | (define_split | |
1428 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1429 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1430 | "TARGET_ZARCH && reload_completed |
dc65c307 | 1431 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1432 | [(set (match_dup 2) (match_dup 4)) |
1433 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1434 | { |
dc65c307 UW |
1435 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1436 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1437 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1438 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1439 | }) | |
1440 | ||
1441 | (define_split | |
1442 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1443 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1444 | "TARGET_ZARCH && reload_completed |
dc65c307 UW |
1445 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" |
1446 | [(set (match_dup 2) (match_dup 4)) | |
1447 | (set (match_dup 3) (match_dup 5))] | |
1448 | { | |
1449 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1450 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1451 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1452 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1453 | }) | |
4023fb28 | 1454 | |
085261c8 AK |
1455 | ; Use part of the TImode target reg to perform the address |
1456 | ; calculation. If the TImode value is supposed to be copied into a VR | |
1457 | ; this splitter is not necessary. | |
4023fb28 UW |
1458 | (define_split |
1459 | [(set (match_operand:TI 0 "register_operand" "") | |
1460 | (match_operand:TI 1 "memory_operand" ""))] | |
9602b6a1 | 1461 | "TARGET_ZARCH && reload_completed |
085261c8 | 1462 | && !VECTOR_REG_P (operands[0]) |
4023fb28 | 1463 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1464 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1465 | { |
1466 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
9602b6a1 | 1467 | addr = gen_lowpart (Pmode, addr); |
a41c6c53 UW |
1468 | s390_load_address (addr, XEXP (operands[1], 0)); |
1469 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1470 | }) |
1471 | ||
833cd70a | 1472 | |
085261c8 AK |
1473 | ; Split a VR -> GPR TImode move into 2 vector load GR from VR element. |
1474 | ; For the higher order bits we do simply a DImode move while the | |
1475 | ; second part is done via vec extract. Both will end up as vlgvg. | |
1476 | (define_split | |
1477 | [(set (match_operand:TI 0 "register_operand" "") | |
1478 | (match_operand:TI 1 "register_operand" ""))] | |
1479 | "TARGET_VX && reload_completed | |
1480 | && GENERAL_REG_P (operands[0]) | |
1481 | && VECTOR_REG_P (operands[1])" | |
1482 | [(set (match_dup 2) (match_dup 4)) | |
1483 | (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)] | |
1484 | UNSPEC_VEC_EXTRACT))] | |
1485 | { | |
1486 | operands[2] = operand_subword (operands[0], 0, 0, TImode); | |
1487 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1488 | operands[4] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
1489 | operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1])); | |
1490 | }) | |
1491 | ||
833cd70a AK |
1492 | ; |
1493 | ; Patterns used for secondary reloads | |
1494 | ; | |
1495 | ||
963fc8d0 AK |
1496 | ; z10 provides move instructions accepting larl memory operands. |
1497 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1498 | ; These patterns are also used for unaligned SI and DI accesses. | |
1499 | ||
085261c8 AK |
1500 | (define_expand "reload<ALL:mode><P:mode>_tomem_z10" |
1501 | [(parallel [(match_operand:ALL 0 "memory_operand" "") | |
1502 | (match_operand:ALL 1 "register_operand" "=d") | |
1503 | (match_operand:P 2 "register_operand" "=&a")])] | |
963fc8d0 AK |
1504 | "TARGET_Z10" |
1505 | { | |
1506 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1507 | DONE; | |
1508 | }) | |
1509 | ||
085261c8 AK |
1510 | (define_expand "reload<ALL:mode><P:mode>_toreg_z10" |
1511 | [(parallel [(match_operand:ALL 0 "register_operand" "=d") | |
1512 | (match_operand:ALL 1 "memory_operand" "") | |
1513 | (match_operand:P 2 "register_operand" "=a")])] | |
963fc8d0 AK |
1514 | "TARGET_Z10" |
1515 | { | |
1516 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1517 | DONE; | |
1518 | }) | |
1519 | ||
1520 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1521 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1522 | (match_operand:P 1 "larl_operand" "") | |
1523 | (match_operand:P 2 "register_operand" "=a")])] | |
1524 | "TARGET_Z10" | |
1525 | { | |
1526 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1527 | DONE; | |
1528 | }) | |
1529 | ||
833cd70a AK |
1530 | ; Handles loading a PLUS (load address) expression |
1531 | ||
1532 | (define_expand "reload<mode>_plus" | |
1533 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1534 | (match_operand:P 1 "s390_plus_operand" "") | |
1535 | (match_operand:P 2 "register_operand" "=&a")])] | |
1536 | "" | |
1537 | { | |
1538 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1539 | DONE; | |
1540 | }) | |
1541 | ||
085261c8 AK |
1542 | ; Not all the indirect memory access instructions support the full |
1543 | ; format (long disp + index + base). So whenever a move from/to such | |
1544 | ; an address is required and the instruction cannot deal with it we do | |
1545 | ; a load address into a scratch register first and use this as the new | |
1546 | ; base register. | |
1547 | ; This in particular is used for: | |
1548 | ; - non-offsetable memory accesses for multiword moves | |
1549 | ; - full vector reg moves with long displacements | |
833cd70a | 1550 | |
085261c8 | 1551 | (define_expand "reload<mode>_la_in" |
833cd70a AK |
1552 | [(parallel [(match_operand 0 "register_operand" "") |
1553 | (match_operand 1 "" "") | |
1554 | (match_operand:P 2 "register_operand" "=&a")])] | |
1555 | "" | |
1556 | { | |
1557 | gcc_assert (MEM_P (operands[1])); | |
1558 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1559 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1560 | emit_move_insn (operands[0], operands[1]); | |
1561 | DONE; | |
1562 | }) | |
1563 | ||
085261c8 | 1564 | (define_expand "reload<mode>_la_out" |
833cd70a AK |
1565 | [(parallel [(match_operand 0 "" "") |
1566 | (match_operand 1 "register_operand" "") | |
1567 | (match_operand:P 2 "register_operand" "=&a")])] | |
1568 | "" | |
dc65c307 | 1569 | { |
9c3c3dcc | 1570 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1571 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1572 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1573 | emit_move_insn (operands[0], operands[1]); | |
1574 | DONE; | |
1575 | }) | |
9db1d521 | 1576 | |
1f9e1fc6 AK |
1577 | (define_expand "reload<mode>_PIC_addr" |
1578 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1579 | (match_operand 1 "larl_operand" "") | |
1580 | (match_operand:P 2 "register_operand" "=a")])] | |
1581 | "" | |
1582 | { | |
0a2aaacc KG |
1583 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1584 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1585 | }) |
1586 | ||
9db1d521 HP |
1587 | ; |
1588 | ; movdi instruction pattern(s). | |
1589 | ; | |
1590 | ||
9db1d521 HP |
1591 | (define_expand "movdi" |
1592 | [(set (match_operand:DI 0 "general_operand" "") | |
1593 | (match_operand:DI 1 "general_operand" ""))] | |
1594 | "" | |
9db1d521 | 1595 | { |
fd3cd001 | 1596 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1597 | if (TARGET_64BIT |
1598 | && (SYMBOLIC_CONST (operands[1]) | |
1599 | || (GET_CODE (operands[1]) == PLUS | |
1600 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1601 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1602 | emit_symbolic_move (operands); |
10bbf137 | 1603 | }) |
9db1d521 | 1604 | |
4023fb28 UW |
1605 | (define_insn "*movdi_larl" |
1606 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1607 | (match_operand:DI 1 "larl_operand" "X"))] | |
1608 | "TARGET_64BIT | |
8e509cf9 | 1609 | && !FP_REG_P (operands[0])" |
d40c829f | 1610 | "larl\t%0,%1" |
4023fb28 | 1611 | [(set_attr "op_type" "RIL") |
9381e3f1 WG |
1612 | (set_attr "type" "larl") |
1613 | (set_attr "z10prop" "z10_super_A1")]) | |
4023fb28 | 1614 | |
3af8e996 | 1615 | (define_insn "*movdi_64" |
85dae55a | 1616 | [(set (match_operand:DI 0 "nonimmediate_operand" |
085261c8 | 1617 | "=d, d, d, d, d, d, d, d,f,d,d,d,d, d,RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d, v,QR") |
85dae55a | 1618 | (match_operand:DI 1 "general_operand" |
085261c8 | 1619 | " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,QR, v"))] |
9602b6a1 | 1620 | "TARGET_ZARCH" |
85dae55a AK |
1621 | "@ |
1622 | lghi\t%0,%h1 | |
1623 | llihh\t%0,%i1 | |
1624 | llihl\t%0,%i1 | |
1625 | llilh\t%0,%i1 | |
1626 | llill\t%0,%i1 | |
1627 | lgfi\t%0,%1 | |
1628 | llihf\t%0,%k1 | |
1629 | llilf\t%0,%k1 | |
1630 | ldgr\t%0,%1 | |
1631 | lgdr\t%0,%1 | |
1632 | lay\t%0,%a1 | |
963fc8d0 | 1633 | lgrl\t%0,%1 |
85dae55a AK |
1634 | lgr\t%0,%1 |
1635 | lg\t%0,%1 | |
1636 | stg\t%1,%0 | |
1637 | ldr\t%0,%1 | |
1638 | ld\t%0,%1 | |
1639 | ldy\t%0,%1 | |
1640 | std\t%1,%0 | |
1641 | stdy\t%1,%0 | |
963fc8d0 AK |
1642 | stgrl\t%1,%0 |
1643 | mvghi\t%0,%1 | |
85dae55a AK |
1644 | # |
1645 | # | |
1646 | stam\t%1,%N1,%S0 | |
085261c8 AK |
1647 | lam\t%0,%N0,%S1 |
1648 | vleig\t%v0,%h1,0 | |
1649 | vlr\t%v0,%v1 | |
1650 | vlvgg\t%v0,%1,0 | |
1651 | vlgvg\t%0,%v1,0 | |
1652 | vleg\t%v0,%1,0 | |
1653 | vsteg\t%v1,%0,0" | |
963fc8d0 | 1654 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
085261c8 | 1655 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
963fc8d0 | 1656 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
085261c8 AK |
1657 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*, |
1658 | *,*,*,*,*,*,*") | |
3af8e996 | 1659 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1660 | z10,*,*,*,*,*,longdisp,*,longdisp, |
085261c8 | 1661 | z10,z10,*,*,*,*,vec,vec,vec,vec,vec,vec") |
9381e3f1 WG |
1662 | (set_attr "z10prop" "z10_fwd_A1, |
1663 | z10_fwd_E1, | |
1664 | z10_fwd_E1, | |
1665 | z10_fwd_E1, | |
1666 | z10_fwd_E1, | |
1667 | z10_fwd_A1, | |
1668 | z10_fwd_E1, | |
1669 | z10_fwd_E1, | |
1670 | *, | |
1671 | *, | |
1672 | z10_fwd_A1, | |
1673 | z10_fwd_A3, | |
1674 | z10_fr_E1, | |
1675 | z10_fwd_A3, | |
1676 | z10_rec, | |
1677 | *, | |
1678 | *, | |
1679 | *, | |
1680 | *, | |
1681 | *, | |
1682 | z10_rec, | |
1683 | z10_super, | |
1684 | *, | |
1685 | *, | |
1686 | *, | |
085261c8 | 1687 | *,*,*,*,*,*,*") |
9381e3f1 | 1688 | ]) |
c5aa1d12 UW |
1689 | |
1690 | (define_split | |
1691 | [(set (match_operand:DI 0 "register_operand" "") | |
1692 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1693 | "TARGET_ZARCH && ACCESS_REG_P (operands[1])" |
c5aa1d12 UW |
1694 | [(set (match_dup 2) (match_dup 3)) |
1695 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1696 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1697 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1698 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1699 | ||
1700 | (define_split | |
1701 | [(set (match_operand:DI 0 "register_operand" "") | |
1702 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1703 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1704 | && dead_or_set_p (insn, operands[1])" |
1705 | [(set (match_dup 3) (match_dup 2)) | |
1706 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1707 | (set (match_dup 4) (match_dup 2))] | |
1708 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1709 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1710 | ||
1711 | (define_split | |
1712 | [(set (match_operand:DI 0 "register_operand" "") | |
1713 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1714 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1715 | && !dead_or_set_p (insn, operands[1])" |
1716 | [(set (match_dup 3) (match_dup 2)) | |
1717 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1718 | (set (match_dup 4) (match_dup 2)) | |
1719 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1720 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1721 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1722 | |
1723 | (define_insn "*movdi_31" | |
963fc8d0 | 1724 | [(set (match_operand:DI 0 "nonimmediate_operand" |
f2dc2f86 | 1725 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1726 | (match_operand:DI 1 "general_operand" |
f2dc2f86 | 1727 | " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))] |
9602b6a1 | 1728 | "!TARGET_ZARCH" |
4023fb28 | 1729 | "@ |
fc0ea003 | 1730 | lm\t%0,%N0,%S1 |
c4d50129 | 1731 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1732 | stm\t%1,%N1,%S0 |
c4d50129 | 1733 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1734 | # |
1735 | # | |
d40c829f UW |
1736 | ldr\t%0,%1 |
1737 | ld\t%0,%1 | |
1738 | ldy\t%0,%1 | |
1739 | std\t%1,%0 | |
1740 | stdy\t%1,%0 | |
19b63d8e | 1741 | #" |
f2dc2f86 AK |
1742 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1743 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
1744 | (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")]) | |
963fc8d0 AK |
1745 | |
1746 | ; For a load from a symbol ref we can use one of the target registers | |
1747 | ; together with larl to load the address. | |
1748 | (define_split | |
1749 | [(set (match_operand:DI 0 "register_operand" "") | |
1750 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1751 | "!TARGET_ZARCH && reload_completed && TARGET_Z10 |
963fc8d0 AK |
1752 | && larl_operand (XEXP (operands[1], 0), SImode)" |
1753 | [(set (match_dup 2) (match_dup 3)) | |
1754 | (set (match_dup 0) (match_dup 1))] | |
1755 | { | |
1756 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1757 | operands[3] = XEXP (operands[1], 0); | |
1758 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1759 | }) | |
4023fb28 UW |
1760 | |
1761 | (define_split | |
1762 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1763 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1764 | "!TARGET_ZARCH && reload_completed |
dc65c307 | 1765 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1766 | [(set (match_dup 2) (match_dup 4)) |
1767 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1768 | { |
dc65c307 UW |
1769 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1770 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1771 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1772 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1773 | }) | |
1774 | ||
1775 | (define_split | |
1776 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1777 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1778 | "!TARGET_ZARCH && reload_completed |
dc65c307 UW |
1779 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" |
1780 | [(set (match_dup 2) (match_dup 4)) | |
1781 | (set (match_dup 3) (match_dup 5))] | |
1782 | { | |
1783 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1784 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1785 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1786 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1787 | }) | |
9db1d521 | 1788 | |
4023fb28 UW |
1789 | (define_split |
1790 | [(set (match_operand:DI 0 "register_operand" "") | |
1791 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1792 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 1793 | && !FP_REG_P (operands[0]) |
4023fb28 | 1794 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1795 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1796 | { |
1797 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1798 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1799 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1800 | }) |
1801 | ||
84817c5d UW |
1802 | (define_peephole2 |
1803 | [(set (match_operand:DI 0 "register_operand" "") | |
1804 | (mem:DI (match_operand 1 "address_operand" "")))] | |
9602b6a1 | 1805 | "TARGET_ZARCH |
84817c5d UW |
1806 | && !FP_REG_P (operands[0]) |
1807 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1808 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1809 | && get_pool_mode (operands[1]) == DImode | |
1810 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1811 | [(set (match_dup 0) (match_dup 2))] | |
1812 | "operands[2] = get_pool_constant (operands[1]);") | |
1813 | ||
7bdff56f UW |
1814 | (define_insn "*la_64" |
1815 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4fe6dea8 | 1816 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
7bdff56f UW |
1817 | "TARGET_64BIT" |
1818 | "@ | |
1819 | la\t%0,%a1 | |
1820 | lay\t%0,%a1" | |
1821 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
1822 | (set_attr "type" "la") |
1823 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
1824 | |
1825 | (define_peephole2 | |
1826 | [(parallel | |
1827 | [(set (match_operand:DI 0 "register_operand" "") | |
1828 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1829 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1830 | "TARGET_64BIT |
e1d5ee28 | 1831 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1832 | [(set (match_dup 0) (match_dup 1))] |
1833 | "") | |
1834 | ||
1835 | (define_peephole2 | |
1836 | [(set (match_operand:DI 0 "register_operand" "") | |
1837 | (match_operand:DI 1 "register_operand" "")) | |
1838 | (parallel | |
1839 | [(set (match_dup 0) | |
1840 | (plus:DI (match_dup 0) | |
1841 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1842 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1843 | "TARGET_64BIT |
1844 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1845 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1846 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1847 | "") | |
1848 | ||
9db1d521 HP |
1849 | ; |
1850 | ; movsi instruction pattern(s). | |
1851 | ; | |
1852 | ||
9db1d521 HP |
1853 | (define_expand "movsi" |
1854 | [(set (match_operand:SI 0 "general_operand" "") | |
1855 | (match_operand:SI 1 "general_operand" ""))] | |
1856 | "" | |
9db1d521 | 1857 | { |
fd3cd001 | 1858 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1859 | if (!TARGET_64BIT |
1860 | && (SYMBOLIC_CONST (operands[1]) | |
1861 | || (GET_CODE (operands[1]) == PLUS | |
1862 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1863 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 1864 | emit_symbolic_move (operands); |
10bbf137 | 1865 | }) |
9db1d521 | 1866 | |
9e8327e3 UW |
1867 | (define_insn "*movsi_larl" |
1868 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1869 | (match_operand:SI 1 "larl_operand" "X"))] | |
1870 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1871 | && !FP_REG_P (operands[0])" | |
1872 | "larl\t%0,%1" | |
1873 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1874 | (set_attr "type" "larl") |
729e750f | 1875 | (set_attr "z10prop" "z10_fwd_A1")]) |
9e8327e3 | 1876 | |
f19a9af7 | 1877 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1878 | [(set (match_operand:SI 0 "nonimmediate_operand" |
085261c8 | 1879 | "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d, v,QR") |
2f7e5a0d | 1880 | (match_operand:SI 1 "general_operand" |
085261c8 | 1881 | " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,QR, v"))] |
f19a9af7 | 1882 | "TARGET_ZARCH" |
9db1d521 | 1883 | "@ |
f19a9af7 AK |
1884 | lhi\t%0,%h1 |
1885 | llilh\t%0,%i1 | |
1886 | llill\t%0,%i1 | |
ec24698e | 1887 | iilf\t%0,%o1 |
f19a9af7 | 1888 | lay\t%0,%a1 |
963fc8d0 | 1889 | lrl\t%0,%1 |
d40c829f UW |
1890 | lr\t%0,%1 |
1891 | l\t%0,%1 | |
1892 | ly\t%0,%1 | |
1893 | st\t%1,%0 | |
1894 | sty\t%1,%0 | |
085261c8 | 1895 | lder\t%0,%1 |
d40c829f | 1896 | ler\t%0,%1 |
085261c8 | 1897 | lde\t%0,%1 |
d40c829f UW |
1898 | le\t%0,%1 |
1899 | ley\t%0,%1 | |
1900 | ste\t%1,%0 | |
1901 | stey\t%1,%0 | |
c5aa1d12 UW |
1902 | ear\t%0,%1 |
1903 | sar\t%0,%1 | |
1904 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
1905 | strl\t%1,%0 |
1906 | mvhi\t%0,%1 | |
085261c8 AK |
1907 | lam\t%0,%0,%S1 |
1908 | vleif\t%v0,%h1,0 | |
1909 | vlr\t%v0,%v1 | |
1910 | vlvgf\t%v0,%1,0 | |
1911 | vlgvf\t%0,%v1,0 | |
1912 | vlef\t%v0,%1,0 | |
1913 | vstef\t%v1,%0,0" | |
963fc8d0 | 1914 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
085261c8 | 1915 | RRE,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
9381e3f1 WG |
1916 | (set_attr "type" "*, |
1917 | *, | |
1918 | *, | |
1919 | *, | |
1920 | la, | |
1921 | larl, | |
1922 | lr, | |
1923 | load, | |
1924 | load, | |
1925 | store, | |
1926 | store, | |
1927 | floadsf, | |
1928 | floadsf, | |
1929 | floadsf, | |
085261c8 AK |
1930 | floadsf, |
1931 | floadsf, | |
9381e3f1 WG |
1932 | fstoresf, |
1933 | fstoresf, | |
1934 | *, | |
1935 | *, | |
1936 | *, | |
1937 | larl, | |
1938 | *, | |
085261c8 | 1939 | *,*,*,*,*,*,*") |
963fc8d0 | 1940 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
085261c8 | 1941 | vec,*,vec,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vec,vec,vec,vec,vec,vec") |
9381e3f1 WG |
1942 | (set_attr "z10prop" "z10_fwd_A1, |
1943 | z10_fwd_E1, | |
1944 | z10_fwd_E1, | |
1945 | z10_fwd_A1, | |
1946 | z10_fwd_A1, | |
1947 | z10_fwd_A3, | |
1948 | z10_fr_E1, | |
1949 | z10_fwd_A3, | |
1950 | z10_fwd_A3, | |
729e750f | 1951 | z10_rec, |
9381e3f1 WG |
1952 | z10_rec, |
1953 | *, | |
1954 | *, | |
1955 | *, | |
1956 | *, | |
1957 | *, | |
085261c8 AK |
1958 | *, |
1959 | *, | |
9381e3f1 WG |
1960 | z10_super_E1, |
1961 | z10_super, | |
1962 | *, | |
1963 | z10_rec, | |
1964 | z10_super, | |
085261c8 | 1965 | *,*,*,*,*,*,*")]) |
f19a9af7 AK |
1966 | |
1967 | (define_insn "*movsi_esa" | |
085261c8 AK |
1968 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t") |
1969 | (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
1970 | "!TARGET_ZARCH" |
1971 | "@ | |
1972 | lhi\t%0,%h1 | |
1973 | lr\t%0,%1 | |
1974 | l\t%0,%1 | |
1975 | st\t%1,%0 | |
085261c8 | 1976 | lder\t%0,%1 |
f19a9af7 | 1977 | ler\t%0,%1 |
085261c8 | 1978 | lde\t%0,%1 |
f19a9af7 AK |
1979 | le\t%0,%1 |
1980 | ste\t%1,%0 | |
c5aa1d12 UW |
1981 | ear\t%0,%1 |
1982 | sar\t%0,%1 | |
1983 | stam\t%1,%1,%S0 | |
f2dc2f86 | 1984 | lam\t%0,%0,%S1" |
085261c8 AK |
1985 | [(set_attr "op_type" "RI,RR,RX,RX,RRE,RR,RXE,RX,RX,RRE,RRE,RS,RS") |
1986 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*") | |
1987 | (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1, | |
1988 | z10_super,*,*") | |
1989 | (set_attr "cpu_facility" "*,*,*,*,vec,*,vec,*,*,*,*,*,*") | |
9381e3f1 | 1990 | ]) |
9db1d521 | 1991 | |
84817c5d UW |
1992 | (define_peephole2 |
1993 | [(set (match_operand:SI 0 "register_operand" "") | |
1994 | (mem:SI (match_operand 1 "address_operand" "")))] | |
1995 | "!FP_REG_P (operands[0]) | |
1996 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1997 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1998 | && get_pool_mode (operands[1]) == SImode | |
1999 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
2000 | [(set (match_dup 0) (match_dup 2))] | |
2001 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 2002 | |
7bdff56f UW |
2003 | (define_insn "*la_31" |
2004 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 2005 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] |
7bdff56f UW |
2006 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
2007 | "@ | |
2008 | la\t%0,%a1 | |
2009 | lay\t%0,%a1" | |
2010 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
2011 | (set_attr "type" "la") |
2012 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
2013 | |
2014 | (define_peephole2 | |
2015 | [(parallel | |
2016 | [(set (match_operand:SI 0 "register_operand" "") | |
2017 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 2018 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 2019 | "!TARGET_64BIT |
e1d5ee28 | 2020 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
2021 | [(set (match_dup 0) (match_dup 1))] |
2022 | "") | |
2023 | ||
2024 | (define_peephole2 | |
2025 | [(set (match_operand:SI 0 "register_operand" "") | |
2026 | (match_operand:SI 1 "register_operand" "")) | |
2027 | (parallel | |
2028 | [(set (match_dup 0) | |
2029 | (plus:SI (match_dup 0) | |
2030 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 2031 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
2032 | "!TARGET_64BIT |
2033 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 2034 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
2035 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
2036 | "") | |
2037 | ||
2038 | (define_insn "*la_31_and" | |
2039 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 2040 | (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT") |
7bdff56f UW |
2041 | (const_int 2147483647)))] |
2042 | "!TARGET_64BIT" | |
2043 | "@ | |
2044 | la\t%0,%a1 | |
2045 | lay\t%0,%a1" | |
2046 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 WG |
2047 | (set_attr "type" "la") |
2048 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f UW |
2049 | |
2050 | (define_insn_and_split "*la_31_and_cc" | |
2051 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2052 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
2053 | (const_int 2147483647))) | |
ae156f85 | 2054 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
2055 | "!TARGET_64BIT" |
2056 | "#" | |
2057 | "&& reload_completed" | |
2058 | [(set (match_dup 0) | |
2059 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
2060 | "" | |
2061 | [(set_attr "op_type" "RX") | |
2062 | (set_attr "type" "la")]) | |
2063 | ||
2064 | (define_insn "force_la_31" | |
2065 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
4fe6dea8 | 2066 | (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")) |
7bdff56f UW |
2067 | (use (const_int 0))] |
2068 | "!TARGET_64BIT" | |
2069 | "@ | |
2070 | la\t%0,%a1 | |
2071 | lay\t%0,%a1" | |
2072 | [(set_attr "op_type" "RX") | |
9381e3f1 WG |
2073 | (set_attr "type" "la") |
2074 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) | |
7bdff56f | 2075 | |
9db1d521 HP |
2076 | ; |
2077 | ; movhi instruction pattern(s). | |
2078 | ; | |
2079 | ||
02ed3c5e UW |
2080 | (define_expand "movhi" |
2081 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
2082 | (match_operand:HI 1 "general_operand" ""))] | |
2083 | "" | |
2084 | { | |
2f7e5a0d | 2085 | /* Make it explicit that loading a register from memory |
02ed3c5e | 2086 | always sign-extends (at least) to SImode. */ |
b3a13419 | 2087 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 2088 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2089 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
2090 | { |
2091 | rtx tmp = gen_reg_rtx (SImode); | |
2092 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
f7df4a84 | 2093 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2094 | operands[1] = gen_lowpart (HImode, tmp); |
2095 | } | |
2096 | }) | |
2097 | ||
2098 | (define_insn "*movhi" | |
085261c8 AK |
2099 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d, v,QR") |
2100 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,QR, v"))] | |
9db1d521 HP |
2101 | "" |
2102 | "@ | |
d40c829f UW |
2103 | lr\t%0,%1 |
2104 | lhi\t%0,%h1 | |
2105 | lh\t%0,%1 | |
2106 | lhy\t%0,%1 | |
963fc8d0 | 2107 | lhrl\t%0,%1 |
d40c829f UW |
2108 | sth\t%1,%0 |
2109 | sthy\t%1,%0 | |
963fc8d0 | 2110 | sthrl\t%1,%0 |
085261c8 AK |
2111 | mvhhi\t%0,%1 |
2112 | vleih\t%v0,%h1,0 | |
2113 | vlr\t%v0,%v1 | |
2114 | vlvgh\t%v0,%1,0 | |
2115 | vlgvh\t%0,%v1,0 | |
2116 | vleh\t%v0,%1,0 | |
2117 | vsteh\t%v1,%0,0" | |
2118 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX") | |
2119 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*") | |
2120 | (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,vec,vec,vec,vec,vec,vec") | |
9381e3f1 WG |
2121 | (set_attr "z10prop" "z10_fr_E1, |
2122 | z10_fwd_A1, | |
2123 | z10_super_E1, | |
2124 | z10_super_E1, | |
2125 | z10_super_E1, | |
729e750f | 2126 | z10_rec, |
9381e3f1 WG |
2127 | z10_rec, |
2128 | z10_rec, | |
085261c8 | 2129 | z10_super,*,*,*,*,*,*")]) |
9db1d521 | 2130 | |
84817c5d UW |
2131 | (define_peephole2 |
2132 | [(set (match_operand:HI 0 "register_operand" "") | |
2133 | (mem:HI (match_operand 1 "address_operand" "")))] | |
2134 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2135 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2136 | && get_pool_mode (operands[1]) == HImode | |
2137 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2138 | [(set (match_dup 0) (match_dup 2))] | |
2139 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2140 | |
9db1d521 HP |
2141 | ; |
2142 | ; movqi instruction pattern(s). | |
2143 | ; | |
2144 | ||
02ed3c5e UW |
2145 | (define_expand "movqi" |
2146 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2147 | (match_operand:QI 1 "general_operand" ""))] | |
2148 | "" | |
2149 | { | |
c19ec8f9 | 2150 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 2151 | is just as fast as a QImode load. */ |
b3a13419 | 2152 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 2153 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2154 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 2155 | { |
9602b6a1 AK |
2156 | rtx tmp = gen_reg_rtx (DImode); |
2157 | rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
f7df4a84 | 2158 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2159 | operands[1] = gen_lowpart (QImode, tmp); |
2160 | } | |
2161 | }) | |
4023fb28 | 2162 | |
02ed3c5e | 2163 | (define_insn "*movqi" |
085261c8 AK |
2164 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d, v,QR") |
2165 | (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,QR, v"))] | |
9db1d521 HP |
2166 | "" |
2167 | "@ | |
d40c829f UW |
2168 | lr\t%0,%1 |
2169 | lhi\t%0,%b1 | |
2170 | ic\t%0,%1 | |
2171 | icy\t%0,%1 | |
2172 | stc\t%1,%0 | |
2173 | stcy\t%1,%0 | |
fc0ea003 | 2174 | mvi\t%S0,%b1 |
0a88561f | 2175 | mviy\t%S0,%b1 |
085261c8 AK |
2176 | # |
2177 | vleib\t%v0,%b1,0 | |
2178 | vlr\t%v0,%v1 | |
2179 | vlvgb\t%v0,%1,0 | |
2180 | vlgvb\t%0,%v1,0 | |
2181 | vleb\t%v0,%1,0 | |
2182 | vsteb\t%v1,%0,0" | |
2183 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX") | |
2184 | (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*") | |
2185 | (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,vec,vec,vec,vec,vec,vec") | |
9381e3f1 WG |
2186 | (set_attr "z10prop" "z10_fr_E1, |
2187 | z10_fwd_A1, | |
2188 | z10_super_E1, | |
2189 | z10_super_E1, | |
729e750f | 2190 | z10_rec, |
9381e3f1 WG |
2191 | z10_rec, |
2192 | z10_super, | |
0a88561f | 2193 | z10_super, |
085261c8 | 2194 | *,*,*,*,*,*,*")]) |
9db1d521 | 2195 | |
84817c5d UW |
2196 | (define_peephole2 |
2197 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2198 | (mem:QI (match_operand 1 "address_operand" "")))] | |
2199 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2200 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2201 | && get_pool_mode (operands[1]) == QImode | |
2202 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2203 | [(set (match_dup 0) (match_dup 2))] | |
2204 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2205 | |
9db1d521 | 2206 | ; |
05b9aaaa | 2207 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
2208 | ; |
2209 | ||
2210 | (define_insn "*movstrictqi" | |
d3632d41 UW |
2211 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
2212 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 2213 | "" |
d3632d41 | 2214 | "@ |
d40c829f UW |
2215 | ic\t%0,%1 |
2216 | icy\t%0,%1" | |
9381e3f1 | 2217 | [(set_attr "op_type" "RX,RXY") |
729e750f | 2218 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2219 | |
2220 | ; | |
2221 | ; movstricthi instruction pattern(s). | |
2222 | ; | |
2223 | ||
2224 | (define_insn "*movstricthi" | |
d3632d41 | 2225 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 2226 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 2227 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2228 | "" |
d3632d41 | 2229 | "@ |
fc0ea003 UW |
2230 | icm\t%0,3,%S1 |
2231 | icmy\t%0,3,%S1" | |
9381e3f1 WG |
2232 | [(set_attr "op_type" "RS,RSY") |
2233 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
2234 | |
2235 | ; | |
2236 | ; movstrictsi instruction pattern(s). | |
2237 | ; | |
2238 | ||
05b9aaaa | 2239 | (define_insn "movstrictsi" |
c5aa1d12 UW |
2240 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
2241 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9602b6a1 | 2242 | "TARGET_ZARCH" |
9db1d521 | 2243 | "@ |
d40c829f UW |
2244 | lr\t%0,%1 |
2245 | l\t%0,%1 | |
c5aa1d12 UW |
2246 | ly\t%0,%1 |
2247 | ear\t%0,%1" | |
2248 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 WG |
2249 | (set_attr "type" "lr,load,load,*") |
2250 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) | |
9db1d521 | 2251 | |
f61a2c7d | 2252 | ; |
609e7e80 | 2253 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
2254 | ; |
2255 | ||
609e7e80 AK |
2256 | (define_expand "mov<mode>" |
2257 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
2258 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
2259 | "" |
2260 | "") | |
2261 | ||
609e7e80 | 2262 | (define_insn "*mov<mode>_64" |
65b1d8ea AK |
2263 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o") |
2264 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))] | |
9602b6a1 | 2265 | "TARGET_ZARCH" |
f61a2c7d | 2266 | "@ |
65b1d8ea | 2267 | lzxr\t%0 |
f61a2c7d AK |
2268 | lxr\t%0,%1 |
2269 | # | |
2270 | # | |
2271 | lmg\t%0,%N0,%S1 | |
2272 | stmg\t%1,%N1,%S0 | |
2273 | # | |
f61a2c7d | 2274 | #" |
65b1d8ea AK |
2275 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
2276 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") | |
2277 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) | |
f61a2c7d | 2278 | |
609e7e80 | 2279 | (define_insn "*mov<mode>_31" |
65b1d8ea AK |
2280 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
2281 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
9602b6a1 | 2282 | "!TARGET_ZARCH" |
f61a2c7d | 2283 | "@ |
65b1d8ea | 2284 | lzxr\t%0 |
f61a2c7d AK |
2285 | lxr\t%0,%1 |
2286 | # | |
f61a2c7d | 2287 | #" |
65b1d8ea AK |
2288 | [(set_attr "op_type" "RRE,RRE,*,*") |
2289 | (set_attr "type" "fsimptf,fsimptf,*,*") | |
2290 | (set_attr "cpu_facility" "z196,*,*,*")]) | |
f61a2c7d AK |
2291 | |
2292 | ; TFmode in GPRs splitters | |
2293 | ||
2294 | (define_split | |
609e7e80 AK |
2295 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2296 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2297 | "TARGET_ZARCH && reload_completed |
609e7e80 | 2298 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
2299 | [(set (match_dup 2) (match_dup 4)) |
2300 | (set (match_dup 3) (match_dup 5))] | |
2301 | { | |
609e7e80 AK |
2302 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2303 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2304 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2305 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
2306 | }) |
2307 | ||
2308 | (define_split | |
609e7e80 AK |
2309 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2310 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2311 | "TARGET_ZARCH && reload_completed |
609e7e80 | 2312 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
2313 | [(set (match_dup 2) (match_dup 4)) |
2314 | (set (match_dup 3) (match_dup 5))] | |
2315 | { | |
609e7e80 AK |
2316 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2317 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2318 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2319 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
2320 | }) |
2321 | ||
2322 | (define_split | |
609e7e80 AK |
2323 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2324 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9602b6a1 | 2325 | "TARGET_ZARCH && reload_completed |
085261c8 | 2326 | && GENERAL_REG_P (operands[0]) |
f61a2c7d AK |
2327 | && !s_operand (operands[1], VOIDmode)" |
2328 | [(set (match_dup 0) (match_dup 1))] | |
2329 | { | |
609e7e80 | 2330 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a9e6994a | 2331 | addr = gen_lowpart (Pmode, addr); |
f61a2c7d AK |
2332 | s390_load_address (addr, XEXP (operands[1], 0)); |
2333 | operands[1] = replace_equiv_address (operands[1], addr); | |
2334 | }) | |
2335 | ||
7b6baae1 | 2336 | ; TFmode in BFPs splitters |
f61a2c7d AK |
2337 | |
2338 | (define_split | |
609e7e80 AK |
2339 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2340 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 2341 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
2342 | && FP_REG_P (operands[0])" |
2343 | [(set (match_dup 2) (match_dup 4)) | |
2344 | (set (match_dup 3) (match_dup 5))] | |
2345 | { | |
609e7e80 AK |
2346 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
2347 | <MODE>mode, 0); | |
2348 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
2349 | <MODE>mode, 8); | |
2350 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
2351 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
2352 | }) |
2353 | ||
2354 | (define_split | |
609e7e80 AK |
2355 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
2356 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
2357 | "reload_completed && offsettable_memref_p (operands[0]) |
2358 | && FP_REG_P (operands[1])" | |
2359 | [(set (match_dup 2) (match_dup 4)) | |
2360 | (set (match_dup 3) (match_dup 5))] | |
2361 | { | |
609e7e80 AK |
2362 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
2363 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
2364 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2365 | <MODE>mode, 0); | |
2366 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2367 | <MODE>mode, 8); | |
f61a2c7d AK |
2368 | }) |
2369 | ||
9db1d521 | 2370 | ; |
609e7e80 | 2371 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
2372 | ; |
2373 | ||
609e7e80 AK |
2374 | (define_expand "mov<mode>" |
2375 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2376 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 2377 | "" |
13c025c1 | 2378 | "") |
9db1d521 | 2379 | |
609e7e80 AK |
2380 | (define_insn "*mov<mode>_64dfp" |
2381 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
085261c8 | 2382 | "=f,f,f,d,f,f,R,T,d,d,d, d,b,RT,v,v,d,v,QR") |
609e7e80 | 2383 | (match_operand:DD_DF 1 "general_operand" |
085261c8 | 2384 | " G,f,d,f,R,T,f,f,G,d,b,RT,d, d,v,d,v,QR,v"))] |
9602b6a1 | 2385 | "TARGET_DFP" |
85dae55a | 2386 | "@ |
65b1d8ea | 2387 | lzdr\t%0 |
85dae55a AK |
2388 | ldr\t%0,%1 |
2389 | ldgr\t%0,%1 | |
2390 | lgdr\t%0,%1 | |
2391 | ld\t%0,%1 | |
2392 | ldy\t%0,%1 | |
2393 | std\t%1,%0 | |
2394 | stdy\t%1,%0 | |
45e5214c | 2395 | lghi\t%0,0 |
85dae55a | 2396 | lgr\t%0,%1 |
085261c8 | 2397 | lgrl\t%0,%1 |
85dae55a | 2398 | lg\t%0,%1 |
085261c8 AK |
2399 | stgrl\t%1,%0 |
2400 | stg\t%1,%0 | |
2401 | vlr\t%v0,%v1 | |
2402 | vlvgg\t%v0,%1,0 | |
2403 | vlgvg\t%0,%v1,0 | |
2404 | vleg\t%0,%1,0 | |
2405 | vsteg\t%1,%0,0" | |
2406 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRS,VRS,VRX,VRX") | |
65b1d8ea | 2407 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, |
085261c8 AK |
2408 | fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store") |
2409 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*") | |
2410 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")]) | |
85dae55a | 2411 | |
609e7e80 | 2412 | (define_insn "*mov<mode>_64" |
085261c8 AK |
2413 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d, d,b,RT,v,v,QR") |
2414 | (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,RT,d, d,v,QR,v"))] | |
9602b6a1 | 2415 | "TARGET_ZARCH" |
9db1d521 | 2416 | "@ |
65b1d8ea | 2417 | lzdr\t%0 |
d40c829f UW |
2418 | ldr\t%0,%1 |
2419 | ld\t%0,%1 | |
2420 | ldy\t%0,%1 | |
2421 | std\t%1,%0 | |
2422 | stdy\t%1,%0 | |
45e5214c | 2423 | lghi\t%0,0 |
d40c829f | 2424 | lgr\t%0,%1 |
085261c8 | 2425 | lgrl\t%0,%1 |
d40c829f | 2426 | lg\t%0,%1 |
085261c8 AK |
2427 | stgrl\t%1,%0 |
2428 | stg\t%1,%0 | |
2429 | vlr\t%v0,%v1 | |
2430 | vleg\t%v0,%1,0 | |
2431 | vsteg\t%v1,%0,0" | |
2432 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRX,VRX") | |
65b1d8ea | 2433 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, |
085261c8 AK |
2434 | fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store") |
2435 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*") | |
2436 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec")]) | |
609e7e80 AK |
2437 | |
2438 | (define_insn "*mov<mode>_31" | |
2439 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
65b1d8ea | 2440 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2441 | (match_operand:DD_DF 1 "general_operand" |
65b1d8ea | 2442 | " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))] |
9602b6a1 | 2443 | "!TARGET_ZARCH" |
9db1d521 | 2444 | "@ |
65b1d8ea | 2445 | lzdr\t%0 |
d40c829f UW |
2446 | ldr\t%0,%1 |
2447 | ld\t%0,%1 | |
2448 | ldy\t%0,%1 | |
2449 | std\t%1,%0 | |
2450 | stdy\t%1,%0 | |
fc0ea003 | 2451 | lm\t%0,%N0,%S1 |
c4d50129 | 2452 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2453 | stm\t%1,%N1,%S0 |
c4d50129 | 2454 | stmy\t%1,%N1,%S0 |
4023fb28 | 2455 | # |
19b63d8e | 2456 | #" |
65b1d8ea AK |
2457 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
2458 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2459 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") | |
2460 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) | |
4023fb28 UW |
2461 | |
2462 | (define_split | |
609e7e80 AK |
2463 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2464 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2465 | "!TARGET_ZARCH && reload_completed |
609e7e80 | 2466 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2467 | [(set (match_dup 2) (match_dup 4)) |
2468 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2469 | { |
609e7e80 AK |
2470 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2471 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2472 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2473 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2474 | }) |
2475 | ||
2476 | (define_split | |
609e7e80 AK |
2477 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2478 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2479 | "!TARGET_ZARCH && reload_completed |
609e7e80 | 2480 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2481 | [(set (match_dup 2) (match_dup 4)) |
2482 | (set (match_dup 3) (match_dup 5))] | |
2483 | { | |
609e7e80 AK |
2484 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2485 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2486 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2487 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2488 | }) |
9db1d521 | 2489 | |
4023fb28 | 2490 | (define_split |
609e7e80 AK |
2491 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2492 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
9602b6a1 | 2493 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 2494 | && !FP_REG_P (operands[0]) |
4023fb28 | 2495 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2496 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2497 | { |
609e7e80 | 2498 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2499 | s390_load_address (addr, XEXP (operands[1], 0)); |
2500 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2501 | }) |
2502 | ||
9db1d521 | 2503 | ; |
609e7e80 | 2504 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2505 | ; |
2506 | ||
609e7e80 AK |
2507 | (define_insn "mov<mode>" |
2508 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
085261c8 | 2509 | "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,QR") |
609e7e80 | 2510 | (match_operand:SD_SF 1 "general_operand" |
085261c8 | 2511 | " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,QR,v"))] |
4023fb28 | 2512 | "" |
9db1d521 | 2513 | "@ |
65b1d8ea | 2514 | lzer\t%0 |
085261c8 | 2515 | lder\t%0,%1 |
d40c829f | 2516 | ler\t%0,%1 |
085261c8 | 2517 | lde\t%0,%1 |
d40c829f UW |
2518 | le\t%0,%1 |
2519 | ley\t%0,%1 | |
2520 | ste\t%1,%0 | |
2521 | stey\t%1,%0 | |
45e5214c | 2522 | lhi\t%0,0 |
d40c829f | 2523 | lr\t%0,%1 |
085261c8 | 2524 | lrl\t%0,%1 |
d40c829f UW |
2525 | l\t%0,%1 |
2526 | ly\t%0,%1 | |
085261c8 | 2527 | strl\t%1,%0 |
d40c829f | 2528 | st\t%1,%0 |
085261c8 AK |
2529 | sty\t%1,%0 |
2530 | vlr\t%v0,%v1 | |
2531 | vleif\t%v0,0 | |
2532 | vlvgf\t%v0,%1,0 | |
2533 | vlgvf\t%0,%v1,0 | |
2534 | vleg\t%0,%1,0 | |
2535 | vsteg\t%1,%0,0" | |
2536 | [(set_attr "op_type" "RRE,RRE,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX") | |
2537 | (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>, | |
2538 | fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store") | |
2539 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*") | |
2540 | (set_attr "cpu_facility" "z196,vec,*,vec,*,*,*,*,*,*,z10,*,*,z10,*,*,vec,vec,vec,vec,vec,vec")]) | |
4023fb28 | 2541 | |
9dc62c00 AK |
2542 | ; |
2543 | ; movcc instruction pattern | |
2544 | ; | |
2545 | ||
2546 | (define_insn "movcc" | |
2547 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
5a3fe9b6 | 2548 | (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))] |
9dc62c00 AK |
2549 | "" |
2550 | "@ | |
2551 | lr\t%0,%1 | |
2552 | tmh\t%1,12288 | |
2553 | ipm\t%0 | |
a71f0749 DV |
2554 | l\t%0,%1 |
2555 | ly\t%0,%1 | |
2556 | st\t%1,%0 | |
2557 | sty\t%1,%0" | |
8dd3b235 | 2558 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
a71f0749 DV |
2559 | (set_attr "type" "lr,*,*,load,load,store,store") |
2560 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") | |
65b1d8ea | 2561 | (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) |
9dc62c00 | 2562 | |
19b63d8e UW |
2563 | ; |
2564 | ; Block move (MVC) patterns. | |
2565 | ; | |
2566 | ||
2567 | (define_insn "*mvc" | |
2568 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2569 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2570 | (use (match_operand 2 "const_int_operand" "n"))] | |
2571 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2572 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2573 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2574 | |
0a88561f AK |
2575 | ; This splitter converts a QI to QI mode copy into a BLK mode copy in |
2576 | ; order to have it implemented with mvc. | |
2577 | ||
2578 | (define_split | |
2579 | [(set (match_operand:QI 0 "memory_operand" "") | |
2580 | (match_operand:QI 1 "memory_operand" ""))] | |
2581 | "reload_completed" | |
2582 | [(parallel | |
2583 | [(set (match_dup 0) (match_dup 1)) | |
2584 | (use (const_int 1))])] | |
2585 | { | |
2586 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
2587 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2588 | }) | |
2589 | ||
2590 | ||
19b63d8e UW |
2591 | (define_peephole2 |
2592 | [(parallel | |
2593 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2594 | (match_operand:BLK 1 "memory_operand" "")) | |
2595 | (use (match_operand 2 "const_int_operand" ""))]) | |
2596 | (parallel | |
2597 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2598 | (match_operand:BLK 4 "memory_operand" "")) | |
2599 | (use (match_operand 5 "const_int_operand" ""))])] | |
2600 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
2601 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 2602 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2603 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2604 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2605 | [(parallel | |
2606 | [(set (match_dup 6) (match_dup 7)) | |
2607 | (use (match_dup 8))])] | |
2608 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2609 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2610 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2611 | ||
2612 | ||
9db1d521 HP |
2613 | ; |
2614 | ; load_multiple pattern(s). | |
2615 | ; | |
22ea6b4f UW |
2616 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2617 | ; we currently support load_multiple/store_multiple only after reload. | |
2618 | ; | |
9db1d521 HP |
2619 | |
2620 | (define_expand "load_multiple" | |
2621 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2622 | (match_operand 1 "" "")) | |
2623 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2624 | "reload_completed" |
9db1d521 | 2625 | { |
ef4bddc2 | 2626 | machine_mode mode; |
9db1d521 HP |
2627 | int regno; |
2628 | int count; | |
2629 | rtx from; | |
4023fb28 | 2630 | int i, off; |
9db1d521 HP |
2631 | |
2632 | /* Support only loading a constant number of fixed-point registers from | |
2633 | memory and only bother with this if more than two */ | |
2634 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2635 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2636 | || INTVAL (operands[2]) > 16 |
2637 | || GET_CODE (operands[1]) != MEM | |
2638 | || GET_CODE (operands[0]) != REG | |
2639 | || REGNO (operands[0]) >= 16) | |
2640 | FAIL; | |
2641 | ||
2642 | count = INTVAL (operands[2]); | |
2643 | regno = REGNO (operands[0]); | |
c19ec8f9 | 2644 | mode = GET_MODE (operands[0]); |
9602b6a1 | 2645 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2646 | FAIL; |
9db1d521 HP |
2647 | |
2648 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2649 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2650 | { |
2651 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2652 | { | |
2653 | from = XEXP (operands[1], 0); | |
2654 | off = 0; | |
2655 | } | |
2656 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2657 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2658 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2659 | { | |
2660 | from = XEXP (XEXP (operands[1], 0), 0); | |
2661 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2662 | } | |
2663 | else | |
2664 | FAIL; | |
4023fb28 UW |
2665 | } |
2666 | else | |
2667 | { | |
2668 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2669 | off = 0; | |
2670 | } | |
9db1d521 HP |
2671 | |
2672 | for (i = 0; i < count; i++) | |
2673 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2674 | = gen_rtx_SET (gen_rtx_REG (mode, regno + i), |
c19ec8f9 | 2675 | change_address (operands[1], mode, |
0a81f074 RS |
2676 | plus_constant (Pmode, from, |
2677 | off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2678 | }) |
9db1d521 HP |
2679 | |
2680 | (define_insn "*load_multiple_di" | |
2681 | [(match_parallel 0 "load_multiple_operation" | |
2682 | [(set (match_operand:DI 1 "register_operand" "=r") | |
d3632d41 | 2683 | (match_operand:DI 2 "s_operand" "QS"))])] |
9602b6a1 | 2684 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2685 | { |
2686 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2687 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2688 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2689 | } |
d3632d41 | 2690 | [(set_attr "op_type" "RSY") |
4023fb28 | 2691 | (set_attr "type" "lm")]) |
9db1d521 HP |
2692 | |
2693 | (define_insn "*load_multiple_si" | |
2694 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2695 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2696 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2697 | "reload_completed" |
9db1d521 HP |
2698 | { |
2699 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2700 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2701 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2702 | } |
d3632d41 | 2703 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2704 | (set_attr "type" "lm")]) |
9db1d521 HP |
2705 | |
2706 | ; | |
c7453384 | 2707 | ; store multiple pattern(s). |
9db1d521 HP |
2708 | ; |
2709 | ||
2710 | (define_expand "store_multiple" | |
2711 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2712 | (match_operand 1 "" "")) | |
2713 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2714 | "reload_completed" |
9db1d521 | 2715 | { |
ef4bddc2 | 2716 | machine_mode mode; |
9db1d521 HP |
2717 | int regno; |
2718 | int count; | |
2719 | rtx to; | |
4023fb28 | 2720 | int i, off; |
9db1d521 HP |
2721 | |
2722 | /* Support only storing a constant number of fixed-point registers to | |
2723 | memory and only bother with this if more than two. */ | |
2724 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2725 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2726 | || INTVAL (operands[2]) > 16 |
2727 | || GET_CODE (operands[0]) != MEM | |
2728 | || GET_CODE (operands[1]) != REG | |
2729 | || REGNO (operands[1]) >= 16) | |
2730 | FAIL; | |
2731 | ||
2732 | count = INTVAL (operands[2]); | |
2733 | regno = REGNO (operands[1]); | |
c19ec8f9 | 2734 | mode = GET_MODE (operands[1]); |
9602b6a1 | 2735 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2736 | FAIL; |
9db1d521 HP |
2737 | |
2738 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2739 | |
b3a13419 | 2740 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2741 | { |
2742 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2743 | { | |
2744 | to = XEXP (operands[0], 0); | |
2745 | off = 0; | |
2746 | } | |
2747 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2748 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2749 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2750 | { | |
2751 | to = XEXP (XEXP (operands[0], 0), 0); | |
2752 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2753 | } | |
2754 | else | |
2755 | FAIL; | |
4023fb28 | 2756 | } |
c7453384 | 2757 | else |
4023fb28 UW |
2758 | { |
2759 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2760 | off = 0; | |
2761 | } | |
9db1d521 HP |
2762 | |
2763 | for (i = 0; i < count; i++) | |
2764 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2765 | = gen_rtx_SET (change_address (operands[0], mode, |
0a81f074 RS |
2766 | plus_constant (Pmode, to, |
2767 | off + i * GET_MODE_SIZE (mode))), | |
c19ec8f9 | 2768 | gen_rtx_REG (mode, regno + i)); |
10bbf137 | 2769 | }) |
9db1d521 HP |
2770 | |
2771 | (define_insn "*store_multiple_di" | |
2772 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 | 2773 | [(set (match_operand:DI 1 "s_operand" "=QS") |
9db1d521 | 2774 | (match_operand:DI 2 "register_operand" "r"))])] |
9602b6a1 | 2775 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2776 | { |
2777 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2778 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2779 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 2780 | } |
d3632d41 | 2781 | [(set_attr "op_type" "RSY") |
4023fb28 | 2782 | (set_attr "type" "stm")]) |
9db1d521 HP |
2783 | |
2784 | ||
2785 | (define_insn "*store_multiple_si" | |
2786 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
2787 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
2788 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 2789 | "reload_completed" |
9db1d521 HP |
2790 | { |
2791 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2792 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2793 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 2794 | } |
d3632d41 | 2795 | [(set_attr "op_type" "RS,RSY") |
4023fb28 | 2796 | (set_attr "type" "stm")]) |
9db1d521 HP |
2797 | |
2798 | ;; | |
2799 | ;; String instructions. | |
2800 | ;; | |
2801 | ||
963fc8d0 | 2802 | (define_insn "*execute_rl" |
2771c2f9 | 2803 | [(match_parallel 0 "execute_operation" |
963fc8d0 AK |
2804 | [(unspec [(match_operand 1 "register_operand" "a") |
2805 | (match_operand 2 "" "") | |
2806 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
2807 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2808 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2809 | "exrl\t%1,%3" | |
2810 | [(set_attr "op_type" "RIL") | |
2811 | (set_attr "type" "cs")]) | |
2812 | ||
9bb86f41 | 2813 | (define_insn "*execute" |
2771c2f9 | 2814 | [(match_parallel 0 "execute_operation" |
9bb86f41 UW |
2815 | [(unspec [(match_operand 1 "register_operand" "a") |
2816 | (match_operand:BLK 2 "memory_operand" "R") | |
2817 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
2818 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2819 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2820 | "ex\t%1,%2" | |
29a74354 UW |
2821 | [(set_attr "op_type" "RX") |
2822 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
2823 | |
2824 | ||
91d39d71 UW |
2825 | ; |
2826 | ; strlenM instruction pattern(s). | |
2827 | ; | |
2828 | ||
9db2f16d | 2829 | (define_expand "strlen<mode>" |
085261c8 AK |
2830 | [(match_operand:P 0 "register_operand" "") ; result |
2831 | (match_operand:BLK 1 "memory_operand" "") ; input string | |
2832 | (match_operand:SI 2 "immediate_operand" "") ; search character | |
2833 | (match_operand:SI 3 "immediate_operand" "")] ; known alignment | |
2834 | "" | |
2835 | { | |
2836 | if (!TARGET_VX || operands[2] != const0_rtx) | |
2837 | emit_insn (gen_strlen_srst<mode> (operands[0], operands[1], | |
2838 | operands[2], operands[3])); | |
2839 | else | |
2840 | s390_expand_vec_strlen (operands[0], operands[1], operands[3]); | |
2841 | ||
2842 | DONE; | |
2843 | }) | |
2844 | ||
2845 | (define_expand "strlen_srst<mode>" | |
ccbdc0d4 | 2846 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 2847 | (parallel |
91d39d71 | 2848 | [(set (match_dup 4) |
9db2f16d | 2849 | (unspec:P [(const_int 0) |
91d39d71 | 2850 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 2851 | (reg:SI 0) |
91d39d71 | 2852 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2853 | (clobber (scratch:P)) |
ae156f85 | 2854 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 2855 | (parallel |
9db2f16d AS |
2856 | [(set (match_operand:P 0 "register_operand" "") |
2857 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 2858 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 2859 | "" |
91d39d71 | 2860 | { |
9db2f16d AS |
2861 | operands[4] = gen_reg_rtx (Pmode); |
2862 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
2863 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2864 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
2865 | }) | |
2866 | ||
9db2f16d AS |
2867 | (define_insn "*strlen<mode>" |
2868 | [(set (match_operand:P 0 "register_operand" "=a") | |
2869 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
2870 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 2871 | (reg:SI 0) |
91d39d71 | 2872 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2873 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 2874 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 2875 | "" |
91d39d71 | 2876 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
2877 | [(set_attr "length" "8") |
2878 | (set_attr "type" "vs")]) | |
91d39d71 | 2879 | |
ccbdc0d4 AS |
2880 | ; |
2881 | ; cmpstrM instruction pattern(s). | |
2882 | ; | |
2883 | ||
2884 | (define_expand "cmpstrsi" | |
2885 | [(set (reg:SI 0) (const_int 0)) | |
2886 | (parallel | |
2887 | [(clobber (match_operand 3 "" "")) | |
2888 | (clobber (match_dup 4)) | |
2889 | (set (reg:CCU CC_REGNUM) | |
2890 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
2891 | (match_operand:BLK 2 "memory_operand" ""))) | |
2892 | (use (reg:SI 0))]) | |
2893 | (parallel | |
2894 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 2895 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT)) |
ccbdc0d4 AS |
2896 | (clobber (reg:CC CC_REGNUM))])] |
2897 | "" | |
2898 | { | |
2899 | /* As the result of CMPINT is inverted compared to what we need, | |
2900 | we have to swap the operands. */ | |
2901 | rtx op1 = operands[2]; | |
2902 | rtx op2 = operands[1]; | |
2903 | rtx addr1 = gen_reg_rtx (Pmode); | |
2904 | rtx addr2 = gen_reg_rtx (Pmode); | |
2905 | ||
2906 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
2907 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
2908 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
2909 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
2910 | operands[3] = addr1; | |
2911 | operands[4] = addr2; | |
2912 | }) | |
2913 | ||
2914 | (define_insn "*cmpstr<mode>" | |
2915 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
2916 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
2917 | (set (reg:CCU CC_REGNUM) | |
2918 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
2919 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
2920 | (use (reg:SI 0))] | |
2921 | "" | |
2922 | "clst\t%0,%1\;jo\t.-4" | |
2923 | [(set_attr "length" "8") | |
2924 | (set_attr "type" "vs")]) | |
9381e3f1 | 2925 | |
742090fc AS |
2926 | ; |
2927 | ; movstr instruction pattern. | |
2928 | ; | |
2929 | ||
2930 | (define_expand "movstr" | |
4a7dec25 DV |
2931 | [(match_operand 0 "register_operand" "") |
2932 | (match_operand 1 "memory_operand" "") | |
2933 | (match_operand 2 "memory_operand" "")] | |
2934 | "" | |
2935 | { | |
2936 | if (TARGET_64BIT) | |
2937 | emit_insn (gen_movstrdi (operands[0], operands[1], operands[2])); | |
2938 | else | |
2939 | emit_insn (gen_movstrsi (operands[0], operands[1], operands[2])); | |
2940 | DONE; | |
2941 | }) | |
2942 | ||
2943 | (define_expand "movstr<P:mode>" | |
742090fc | 2944 | [(set (reg:SI 0) (const_int 0)) |
9381e3f1 | 2945 | (parallel |
742090fc AS |
2946 | [(clobber (match_dup 3)) |
2947 | (set (match_operand:BLK 1 "memory_operand" "") | |
2948 | (match_operand:BLK 2 "memory_operand" "")) | |
4a7dec25 DV |
2949 | (set (match_operand:P 0 "register_operand" "") |
2950 | (unspec:P [(match_dup 1) | |
742090fc AS |
2951 | (match_dup 2) |
2952 | (reg:SI 0)] UNSPEC_MVST)) | |
2953 | (clobber (reg:CC CC_REGNUM))])] | |
2954 | "" | |
2955 | { | |
2956 | rtx addr1 = gen_reg_rtx (Pmode); | |
2957 | rtx addr2 = gen_reg_rtx (Pmode); | |
2958 | ||
2959 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
2960 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
2961 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
2962 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
2963 | operands[3] = addr2; | |
2964 | }) | |
2965 | ||
2966 | (define_insn "*movstr" | |
2967 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
2968 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
2969 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
2970 | (set (match_operand:P 0 "register_operand" "=d") | |
4a7dec25 | 2971 | (unspec:P [(mem:BLK (match_dup 1)) |
742090fc AS |
2972 | (mem:BLK (match_dup 3)) |
2973 | (reg:SI 0)] UNSPEC_MVST)) | |
2974 | (clobber (reg:CC CC_REGNUM))] | |
2975 | "" | |
2976 | "mvst\t%1,%2\;jo\t.-4" | |
2977 | [(set_attr "length" "8") | |
2978 | (set_attr "type" "vs")]) | |
9381e3f1 | 2979 | |
742090fc | 2980 | |
9db1d521 | 2981 | ; |
70128ad9 | 2982 | ; movmemM instruction pattern(s). |
9db1d521 HP |
2983 | ; |
2984 | ||
9db2f16d | 2985 | (define_expand "movmem<mode>" |
963fc8d0 AK |
2986 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
2987 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
2988 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
2989 | (match_operand 3 "" "")] |
2990 | "" | |
367d32f3 AK |
2991 | { |
2992 | if (s390_expand_movmem (operands[0], operands[1], operands[2])) | |
2993 | DONE; | |
2994 | else | |
2995 | FAIL; | |
2996 | }) | |
9db1d521 | 2997 | |
ecbe845e UW |
2998 | ; Move a block that is up to 256 bytes in length. |
2999 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3000 | |
70128ad9 | 3001 | (define_expand "movmem_short" |
b9404c99 UW |
3002 | [(parallel |
3003 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3004 | (match_operand:BLK 1 "memory_operand" "")) | |
3005 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3006 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3007 | (clobber (match_dup 3))])] |
3008 | "" | |
3009 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 3010 | |
70128ad9 | 3011 | (define_insn "*movmem_short" |
963fc8d0 AK |
3012 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
3013 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
3014 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3015 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3016 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3017 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3018 | "#" |
963fc8d0 | 3019 | [(set_attr "type" "cs") |
b5e0425c | 3020 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
ecbe845e | 3021 | |
9bb86f41 UW |
3022 | (define_split |
3023 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3024 | (match_operand:BLK 1 "memory_operand" "")) | |
3025 | (use (match_operand 2 "const_int_operand" "")) | |
3026 | (use (match_operand 3 "immediate_operand" "")) | |
3027 | (clobber (scratch))] | |
3028 | "reload_completed" | |
3029 | [(parallel | |
3030 | [(set (match_dup 0) (match_dup 1)) | |
3031 | (use (match_dup 2))])] | |
3032 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3033 | |
9bb86f41 UW |
3034 | (define_split |
3035 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3036 | (match_operand:BLK 1 "memory_operand" "")) | |
3037 | (use (match_operand 2 "register_operand" "")) | |
3038 | (use (match_operand 3 "memory_operand" "")) | |
3039 | (clobber (scratch))] | |
3040 | "reload_completed" | |
3041 | [(parallel | |
3042 | [(unspec [(match_dup 2) (match_dup 3) | |
3043 | (const_int 0)] UNSPEC_EXECUTE) | |
3044 | (set (match_dup 0) (match_dup 1)) | |
3045 | (use (const_int 1))])] | |
3046 | "") | |
3047 | ||
963fc8d0 AK |
3048 | (define_split |
3049 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3050 | (match_operand:BLK 1 "memory_operand" "")) | |
3051 | (use (match_operand 2 "register_operand" "")) | |
3052 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3053 | (clobber (scratch))] | |
3054 | "TARGET_Z10 && reload_completed" | |
3055 | [(parallel | |
3056 | [(unspec [(match_dup 2) (const_int 0) | |
3057 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3058 | (set (match_dup 0) (match_dup 1)) | |
3059 | (use (const_int 1))])] | |
3060 | "operands[3] = gen_label_rtx ();") | |
3061 | ||
9bb86f41 UW |
3062 | (define_split |
3063 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3064 | (match_operand:BLK 1 "memory_operand" "")) | |
3065 | (use (match_operand 2 "register_operand" "")) | |
3066 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3067 | (clobber (match_operand 3 "register_operand" ""))] | |
3068 | "reload_completed && TARGET_CPU_ZARCH" | |
3069 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3070 | (parallel | |
9381e3f1 | 3071 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
3072 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
3073 | (set (match_dup 0) (match_dup 1)) | |
3074 | (use (const_int 1))])] | |
3075 | "operands[4] = gen_label_rtx ();") | |
3076 | ||
a41c6c53 | 3077 | ; Move a block of arbitrary length. |
9db1d521 | 3078 | |
70128ad9 | 3079 | (define_expand "movmem_long" |
b9404c99 UW |
3080 | [(parallel |
3081 | [(clobber (match_dup 2)) | |
3082 | (clobber (match_dup 3)) | |
3083 | (set (match_operand:BLK 0 "memory_operand" "") | |
3084 | (match_operand:BLK 1 "memory_operand" "")) | |
3085 | (use (match_operand 2 "general_operand" "")) | |
3086 | (use (match_dup 3)) | |
ae156f85 | 3087 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3088 | "" |
3089 | { | |
ef4bddc2 RS |
3090 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3091 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3092 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3093 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3094 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3095 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3096 | rtx len0 = gen_lowpart (Pmode, reg0); |
3097 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3098 | ||
c41c1387 | 3099 | emit_clobber (reg0); |
b9404c99 UW |
3100 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3101 | emit_move_insn (len0, operands[2]); | |
3102 | ||
c41c1387 | 3103 | emit_clobber (reg1); |
b9404c99 UW |
3104 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3105 | emit_move_insn (len1, operands[2]); | |
3106 | ||
3107 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3108 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3109 | operands[2] = reg0; | |
3110 | operands[3] = reg1; | |
3111 | }) | |
3112 | ||
a1aed706 AS |
3113 | (define_insn "*movmem_long" |
3114 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3115 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
3116 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
3117 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
3118 | (use (match_dup 2)) |
3119 | (use (match_dup 3)) | |
ae156f85 | 3120 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 AK |
3121 | "TARGET_64BIT || !TARGET_ZARCH" |
3122 | "mvcle\t%0,%1,0\;jo\t.-4" | |
3123 | [(set_attr "length" "8") | |
3124 | (set_attr "type" "vs")]) | |
3125 | ||
3126 | (define_insn "*movmem_long_31z" | |
3127 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3128 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3129 | (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3130 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) | |
3131 | (use (match_dup 2)) | |
3132 | (use (match_dup 3)) | |
3133 | (clobber (reg:CC CC_REGNUM))] | |
3134 | "!TARGET_64BIT && TARGET_ZARCH" | |
d40c829f | 3135 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3136 | [(set_attr "length" "8") |
3137 | (set_attr "type" "vs")]) | |
9db1d521 | 3138 | |
638e37c2 WG |
3139 | |
3140 | ; | |
3141 | ; Test data class. | |
3142 | ; | |
3143 | ||
0f67fa83 WG |
3144 | (define_expand "signbit<mode>2" |
3145 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3146 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3147 | (match_dup 2)] | |
0f67fa83 WG |
3148 | UNSPEC_TDC_INSN)) |
3149 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3150 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
0f67fa83 WG |
3151 | "TARGET_HARD_FLOAT" |
3152 | { | |
3153 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
3154 | }) | |
3155 | ||
638e37c2 WG |
3156 | (define_expand "isinf<mode>2" |
3157 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3158 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3159 | (match_dup 2)] | |
638e37c2 WG |
3160 | UNSPEC_TDC_INSN)) |
3161 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3162 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
142cd70f | 3163 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
3164 | { |
3165 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
3166 | }) | |
3167 | ||
085261c8 AK |
3168 | ; This extracts CC into a GPR properly shifted. The actual IPM |
3169 | ; instruction will be issued by reload. The constraint of operand 1 | |
3170 | ; forces reload to use a GPR. So reload will issue a movcc insn for | |
3171 | ; copying CC into a GPR first. | |
5a3fe9b6 | 3172 | (define_insn_and_split "*cc_to_int" |
085261c8 | 3173 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
5a3fe9b6 AK |
3174 | (unspec:SI [(match_operand 1 "register_operand" "0")] |
3175 | UNSPEC_CC_TO_INT))] | |
3176 | "operands != NULL" | |
3177 | "#" | |
3178 | "reload_completed" | |
3179 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
3180 | ||
638e37c2 WG |
3181 | ; This insn is used to generate all variants of the Test Data Class |
3182 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
3183 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 3184 | ; specifying the required test(s). |
638e37c2 | 3185 | ; |
be5de7a1 | 3186 | ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet |
638e37c2 WG |
3187 | (define_insn "*TDC_insn_<mode>" |
3188 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 3189 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 3190 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 3191 | "TARGET_HARD_FLOAT" |
0387c142 | 3192 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 3193 | [(set_attr "op_type" "RXE") |
9381e3f1 | 3194 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 | 3195 | |
638e37c2 WG |
3196 | |
3197 | ||
9db1d521 | 3198 | ; |
57e84f18 | 3199 | ; setmemM instruction pattern(s). |
9db1d521 HP |
3200 | ; |
3201 | ||
57e84f18 | 3202 | (define_expand "setmem<mode>" |
a41c6c53 | 3203 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 3204 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 3205 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 3206 | (match_operand 3 "" "")] |
a41c6c53 | 3207 | "" |
6d057022 | 3208 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 3209 | |
a41c6c53 | 3210 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
3211 | ; The block length is taken as (operands[1] % 256) + 1. |
3212 | ||
70128ad9 | 3213 | (define_expand "clrmem_short" |
b9404c99 UW |
3214 | [(parallel |
3215 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3216 | (const_int 0)) | |
3217 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 3218 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 3219 | (clobber (match_dup 2)) |
ae156f85 | 3220 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3221 | "" |
3222 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3223 | |
70128ad9 | 3224 | (define_insn "*clrmem_short" |
963fc8d0 | 3225 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 3226 | (const_int 0)) |
963fc8d0 AK |
3227 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
3228 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
1eae36f0 | 3229 | (clobber (match_scratch:P 3 "=X,X,X,&a")) |
ae156f85 | 3230 | (clobber (reg:CC CC_REGNUM))] |
1eae36f0 | 3231 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" |
9bb86f41 | 3232 | "#" |
963fc8d0 | 3233 | [(set_attr "type" "cs") |
b5e0425c | 3234 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9bb86f41 UW |
3235 | |
3236 | (define_split | |
3237 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3238 | (const_int 0)) | |
3239 | (use (match_operand 1 "const_int_operand" "")) | |
3240 | (use (match_operand 2 "immediate_operand" "")) | |
3241 | (clobber (scratch)) | |
ae156f85 | 3242 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3243 | "reload_completed" |
3244 | [(parallel | |
3245 | [(set (match_dup 0) (const_int 0)) | |
3246 | (use (match_dup 1)) | |
ae156f85 | 3247 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3248 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 3249 | |
9bb86f41 UW |
3250 | (define_split |
3251 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3252 | (const_int 0)) | |
3253 | (use (match_operand 1 "register_operand" "")) | |
3254 | (use (match_operand 2 "memory_operand" "")) | |
3255 | (clobber (scratch)) | |
ae156f85 | 3256 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3257 | "reload_completed" |
3258 | [(parallel | |
3259 | [(unspec [(match_dup 1) (match_dup 2) | |
3260 | (const_int 0)] UNSPEC_EXECUTE) | |
3261 | (set (match_dup 0) (const_int 0)) | |
3262 | (use (const_int 1)) | |
ae156f85 | 3263 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3264 | "") |
9db1d521 | 3265 | |
963fc8d0 AK |
3266 | (define_split |
3267 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3268 | (const_int 0)) | |
3269 | (use (match_operand 1 "register_operand" "")) | |
3270 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3271 | (clobber (scratch)) | |
3272 | (clobber (reg:CC CC_REGNUM))] | |
3273 | "TARGET_Z10 && reload_completed" | |
3274 | [(parallel | |
3275 | [(unspec [(match_dup 1) (const_int 0) | |
3276 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3277 | (set (match_dup 0) (const_int 0)) | |
3278 | (use (const_int 1)) | |
3279 | (clobber (reg:CC CC_REGNUM))])] | |
3280 | "operands[3] = gen_label_rtx ();") | |
3281 | ||
9bb86f41 UW |
3282 | (define_split |
3283 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3284 | (const_int 0)) | |
3285 | (use (match_operand 1 "register_operand" "")) | |
3286 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3287 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 3288 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3289 | "reload_completed && TARGET_CPU_ZARCH" |
3290 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
3291 | (parallel | |
9381e3f1 | 3292 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
3293 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
3294 | (set (match_dup 0) (const_int 0)) | |
3295 | (use (const_int 1)) | |
ae156f85 | 3296 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
3297 | "operands[3] = gen_label_rtx ();") |
3298 | ||
9381e3f1 | 3299 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 3300 | |
da0dcab1 | 3301 | (define_expand "setmem_long_<P:mode>" |
b9404c99 UW |
3302 | [(parallel |
3303 | [(clobber (match_dup 1)) | |
3304 | (set (match_operand:BLK 0 "memory_operand" "") | |
da0dcab1 DV |
3305 | (unspec:BLK [(match_operand:P 2 "shift_count_or_setmem_operand" "") |
3306 | (match_dup 4)] UNSPEC_REPLICATE_BYTE)) | |
6d057022 | 3307 | (use (match_dup 3)) |
ae156f85 | 3308 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 3309 | "" |
a41c6c53 | 3310 | { |
ef4bddc2 RS |
3311 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3312 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3313 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3314 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3315 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
b9404c99 | 3316 | rtx len0 = gen_lowpart (Pmode, reg0); |
9db1d521 | 3317 | |
c41c1387 | 3318 | emit_clobber (reg0); |
b9404c99 UW |
3319 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3320 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 3321 | |
b9404c99 | 3322 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 3323 | |
b9404c99 UW |
3324 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
3325 | operands[1] = reg0; | |
6d057022 | 3326 | operands[3] = reg1; |
da0dcab1 | 3327 | operands[4] = gen_lowpart (Pmode, operands[1]); |
b9404c99 | 3328 | }) |
a41c6c53 | 3329 | |
da0dcab1 DV |
3330 | ; Patterns for 31 bit + Esa and 64 bit + Zarch. |
3331 | ||
6d057022 | 3332 | (define_insn "*setmem_long" |
a1aed706 | 3333 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 3334 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
da0dcab1 DV |
3335 | (unspec:BLK [(match_operand:P 2 "shift_count_or_setmem_operand" "Y") |
3336 | (subreg:P (match_dup 3) <modesize>)] | |
3337 | UNSPEC_REPLICATE_BYTE)) | |
a1aed706 | 3338 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 3339 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3340 | "TARGET_64BIT || !TARGET_ZARCH" |
6d057022 | 3341 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
3342 | [(set_attr "length" "8") |
3343 | (set_attr "type" "vs")]) | |
9db1d521 | 3344 | |
4989e88a AK |
3345 | (define_insn "*setmem_long_and" |
3346 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3347 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
da0dcab1 DV |
3348 | (unspec:BLK [(and:P |
3349 | (match_operand:P 2 "shift_count_or_setmem_operand" "Y") | |
3350 | (match_operand:P 4 "const_int_operand" "n")) | |
3351 | (subreg:P (match_dup 3) <modesize>)] | |
3352 | UNSPEC_REPLICATE_BYTE)) | |
4989e88a AK |
3353 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
3354 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 AK |
3355 | "(TARGET_64BIT || !TARGET_ZARCH) && |
3356 | (INTVAL (operands[4]) & 255) == 255" | |
3357 | "mvcle\t%0,%1,%Y2\;jo\t.-4" | |
3358 | [(set_attr "length" "8") | |
3359 | (set_attr "type" "vs")]) | |
3360 | ||
da0dcab1 DV |
3361 | ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets |
3362 | ; of the SImode subregs. | |
3363 | ||
9602b6a1 AK |
3364 | (define_insn "*setmem_long_31z" |
3365 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3366 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
da0dcab1 DV |
3367 | (unspec:BLK [(match_operand:SI 2 "shift_count_or_setmem_operand" "Y") |
3368 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) | |
9602b6a1 AK |
3369 | (use (match_operand:TI 1 "register_operand" "d")) |
3370 | (clobber (reg:CC CC_REGNUM))] | |
3371 | "!TARGET_64BIT && TARGET_ZARCH" | |
4989e88a AK |
3372 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3373 | [(set_attr "length" "8") | |
3374 | (set_attr "type" "vs")]) | |
9602b6a1 | 3375 | |
da0dcab1 DV |
3376 | (define_insn "*setmem_long_and_31z" |
3377 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3378 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
3379 | (unspec:BLK [(and:SI | |
3380 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
3381 | (match_operand:SI 4 "const_int_operand" "n")) | |
3382 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) | |
3383 | (use (match_operand:TI 1 "register_operand" "d")) | |
3384 | (clobber (reg:CC CC_REGNUM))] | |
3385 | "(!TARGET_64BIT && TARGET_ZARCH) && | |
3386 | (INTVAL (operands[4]) & 255) == 255" | |
3387 | "mvcle\t%0,%1,%Y2\;jo\t.-4" | |
3388 | [(set_attr "length" "8") | |
3389 | (set_attr "type" "vs")]) | |
3390 | ||
9db1d521 | 3391 | ; |
358b8f01 | 3392 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
3393 | ; |
3394 | ||
358b8f01 | 3395 | (define_expand "cmpmemsi" |
a41c6c53 UW |
3396 | [(set (match_operand:SI 0 "register_operand" "") |
3397 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
3398 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
3399 | (use (match_operand:SI 3 "general_operand" "")) | |
3400 | (use (match_operand:SI 4 "" ""))] | |
3401 | "" | |
367d32f3 AK |
3402 | { |
3403 | if (s390_expand_cmpmem (operands[0], operands[1], | |
3404 | operands[2], operands[3])) | |
3405 | DONE; | |
3406 | else | |
3407 | FAIL; | |
3408 | }) | |
9db1d521 | 3409 | |
a41c6c53 UW |
3410 | ; Compare a block that is up to 256 bytes in length. |
3411 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3412 | |
b9404c99 UW |
3413 | (define_expand "cmpmem_short" |
3414 | [(parallel | |
ae156f85 | 3415 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 3416 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3417 | (match_operand:BLK 1 "memory_operand" ""))) |
3418 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3419 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3420 | (clobber (match_dup 3))])] |
3421 | "" | |
3422 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3423 | |
b9404c99 | 3424 | (define_insn "*cmpmem_short" |
ae156f85 | 3425 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
3426 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
3427 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
3428 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3429 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3430 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3431 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3432 | "#" |
963fc8d0 | 3433 | [(set_attr "type" "cs") |
b5e0425c | 3434 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9db1d521 | 3435 | |
9bb86f41 | 3436 | (define_split |
ae156f85 | 3437 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3438 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3439 | (match_operand:BLK 1 "memory_operand" ""))) | |
3440 | (use (match_operand 2 "const_int_operand" "")) | |
3441 | (use (match_operand 3 "immediate_operand" "")) | |
3442 | (clobber (scratch))] | |
3443 | "reload_completed" | |
3444 | [(parallel | |
ae156f85 | 3445 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3446 | (use (match_dup 2))])] |
3447 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3448 | |
9bb86f41 | 3449 | (define_split |
ae156f85 | 3450 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3451 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3452 | (match_operand:BLK 1 "memory_operand" ""))) | |
3453 | (use (match_operand 2 "register_operand" "")) | |
3454 | (use (match_operand 3 "memory_operand" "")) | |
3455 | (clobber (scratch))] | |
3456 | "reload_completed" | |
3457 | [(parallel | |
3458 | [(unspec [(match_dup 2) (match_dup 3) | |
3459 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 3460 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3461 | (use (const_int 1))])] |
3462 | "") | |
3463 | ||
963fc8d0 AK |
3464 | (define_split |
3465 | [(set (reg:CCU CC_REGNUM) | |
3466 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3467 | (match_operand:BLK 1 "memory_operand" ""))) | |
3468 | (use (match_operand 2 "register_operand" "")) | |
3469 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3470 | (clobber (scratch))] | |
3471 | "TARGET_Z10 && reload_completed" | |
3472 | [(parallel | |
3473 | [(unspec [(match_dup 2) (const_int 0) | |
3474 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
3475 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
3476 | (use (const_int 1))])] | |
3477 | "operands[4] = gen_label_rtx ();") | |
3478 | ||
9bb86f41 | 3479 | (define_split |
ae156f85 | 3480 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3481 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3482 | (match_operand:BLK 1 "memory_operand" ""))) | |
3483 | (use (match_operand 2 "register_operand" "")) | |
3484 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3485 | (clobber (match_operand 3 "register_operand" ""))] | |
3486 | "reload_completed && TARGET_CPU_ZARCH" | |
3487 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3488 | (parallel | |
9381e3f1 | 3489 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 3490 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 3491 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3492 | (use (const_int 1))])] |
3493 | "operands[4] = gen_label_rtx ();") | |
3494 | ||
a41c6c53 | 3495 | ; Compare a block of arbitrary length. |
9db1d521 | 3496 | |
b9404c99 UW |
3497 | (define_expand "cmpmem_long" |
3498 | [(parallel | |
3499 | [(clobber (match_dup 2)) | |
3500 | (clobber (match_dup 3)) | |
ae156f85 | 3501 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 3502 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3503 | (match_operand:BLK 1 "memory_operand" ""))) |
3504 | (use (match_operand 2 "general_operand" "")) | |
3505 | (use (match_dup 3))])] | |
3506 | "" | |
3507 | { | |
ef4bddc2 RS |
3508 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3509 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3510 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3511 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3512 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3513 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3514 | rtx len0 = gen_lowpart (Pmode, reg0); |
3515 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3516 | ||
c41c1387 | 3517 | emit_clobber (reg0); |
b9404c99 UW |
3518 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3519 | emit_move_insn (len0, operands[2]); | |
3520 | ||
c41c1387 | 3521 | emit_clobber (reg1); |
b9404c99 UW |
3522 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3523 | emit_move_insn (len1, operands[2]); | |
3524 | ||
3525 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3526 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3527 | operands[2] = reg0; | |
3528 | operands[3] = reg1; | |
3529 | }) | |
3530 | ||
a1aed706 AS |
3531 | (define_insn "*cmpmem_long" |
3532 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3533 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3534 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3535 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3536 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3537 | (use (match_dup 2)) |
3538 | (use (match_dup 3))] | |
9602b6a1 | 3539 | "TARGET_64BIT || !TARGET_ZARCH" |
287ff198 | 3540 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3541 | [(set_attr "length" "8") |
3542 | (set_attr "type" "vs")]) | |
9db1d521 | 3543 | |
9602b6a1 AK |
3544 | (define_insn "*cmpmem_long_31z" |
3545 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3546 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3547 | (set (reg:CCU CC_REGNUM) | |
3548 | (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3549 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) | |
3550 | (use (match_dup 2)) | |
3551 | (use (match_dup 3))] | |
3552 | "!TARGET_64BIT && TARGET_ZARCH" | |
3553 | "clcle\t%0,%1,0\;jo\t.-4" | |
3554 | [(set_attr "op_type" "NN") | |
3555 | (set_attr "type" "vs") | |
3556 | (set_attr "length" "8")]) | |
3557 | ||
02887425 UW |
3558 | ; Convert CCUmode condition code to integer. |
3559 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3560 | |
02887425 | 3561 | (define_insn_and_split "cmpint" |
9db1d521 | 3562 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3563 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3564 | UNSPEC_STRCMPCC_TO_INT)) |
ae156f85 | 3565 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3566 | "" |
02887425 UW |
3567 | "#" |
3568 | "reload_completed" | |
3569 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3570 | (parallel | |
3571 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3572 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3573 | |
3574 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3575 | [(set (reg CC_REGNUM) |
02887425 | 3576 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3577 | UNSPEC_STRCMPCC_TO_INT) |
02887425 UW |
3578 | (const_int 0))) |
3579 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3580 | (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))] |
02887425 UW |
3581 | "s390_match_ccmode (insn, CCSmode)" |
3582 | "#" | |
3583 | "&& reload_completed" | |
3584 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3585 | (parallel | |
3586 | [(set (match_dup 2) (match_dup 3)) | |
3587 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3588 | { |
02887425 UW |
3589 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3590 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3591 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3592 | }) | |
9db1d521 | 3593 | |
02887425 | 3594 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3595 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3596 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3597 | UNSPEC_STRCMPCC_TO_INT))) |
ae156f85 | 3598 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3599 | "TARGET_ZARCH" |
02887425 UW |
3600 | "#" |
3601 | "&& reload_completed" | |
3602 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3603 | (parallel | |
3604 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3605 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3606 | |
3607 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3608 | [(set (reg CC_REGNUM) |
9381e3f1 | 3609 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3610 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3611 | UNSPEC_STRCMPCC_TO_INT) 0) |
02887425 UW |
3612 | (const_int 32)) (const_int 32)) |
3613 | (const_int 0))) | |
3614 | (set (match_operand:DI 0 "register_operand" "=d") | |
5a3fe9b6 | 3615 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))] |
9602b6a1 | 3616 | "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" |
02887425 UW |
3617 | "#" |
3618 | "&& reload_completed" | |
3619 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3620 | (parallel | |
3621 | [(set (match_dup 2) (match_dup 3)) | |
3622 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3623 | { |
02887425 UW |
3624 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3625 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3626 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3627 | }) | |
9db1d521 | 3628 | |
4023fb28 | 3629 | |
9db1d521 HP |
3630 | ;; |
3631 | ;;- Conversion instructions. | |
3632 | ;; | |
3633 | ||
6fa05db6 | 3634 | (define_insn "*sethighpartsi" |
d3632d41 | 3635 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3636 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3637 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3638 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3639 | "" |
d3632d41 | 3640 | "@ |
6fa05db6 AS |
3641 | icm\t%0,%2,%S1 |
3642 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3643 | [(set_attr "op_type" "RS,RSY") |
3644 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
4023fb28 | 3645 | |
6fa05db6 | 3646 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3647 | [(set (match_operand:DI 0 "register_operand" "=d") |
6fa05db6 AS |
3648 | (unspec:DI [(match_operand:BLK 1 "s_operand" "QS") |
3649 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) | |
ae156f85 | 3650 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3651 | "TARGET_ZARCH" |
6fa05db6 | 3652 | "icmh\t%0,%2,%S1" |
729e750f WG |
3653 | [(set_attr "op_type" "RSY") |
3654 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3655 | |
6fa05db6 | 3656 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3657 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3658 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3659 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3660 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3661 | "!TARGET_ZARCH" |
d3632d41 | 3662 | "@ |
6fa05db6 AS |
3663 | icm\t%0,%2,%S1 |
3664 | icmy\t%0,%2,%S1" | |
9381e3f1 WG |
3665 | [(set_attr "op_type" "RS,RSY") |
3666 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
3667 | ||
1a2e356e RH |
3668 | ; |
3669 | ; extv instruction patterns | |
3670 | ; | |
3671 | ||
3672 | ; FIXME: This expander needs to be converted from DI to GPR as well | |
3673 | ; after resolving some issues with it. | |
3674 | ||
3675 | (define_expand "extzv" | |
3676 | [(parallel | |
3677 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3678 | (zero_extract:DI | |
3679 | (match_operand:DI 1 "register_operand" "d") | |
3680 | (match_operand 2 "const_int_operand" "") ; size | |
3681 | (match_operand 3 "const_int_operand" ""))) ; start | |
3682 | (clobber (reg:CC CC_REGNUM))])] | |
3683 | "TARGET_Z10" | |
3684 | { | |
3685 | /* Starting with zEC12 there is risbgn not clobbering CC. */ | |
3686 | if (TARGET_ZEC12) | |
3687 | { | |
3688 | emit_move_insn (operands[0], | |
3689 | gen_rtx_ZERO_EXTRACT (DImode, | |
3690 | operands[1], | |
3691 | operands[2], | |
3692 | operands[3])); | |
3693 | DONE; | |
3694 | } | |
3695 | }) | |
3696 | ||
3697 | (define_insn "*extzv<mode>_zEC12" | |
3698 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3699 | (zero_extract:GPR | |
3700 | (match_operand:GPR 1 "register_operand" "d") | |
3701 | (match_operand 2 "const_int_operand" "") ; size | |
3702 | (match_operand 3 "const_int_operand" "")))] ; start] | |
3703 | "TARGET_ZEC12" | |
3704 | "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift | |
3705 | [(set_attr "op_type" "RIE")]) | |
3706 | ||
3707 | (define_insn "*extzv<mode>_z10" | |
3708 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3709 | (zero_extract:GPR | |
3710 | (match_operand:GPR 1 "register_operand" "d") | |
3711 | (match_operand 2 "const_int_operand" "") ; size | |
3712 | (match_operand 3 "const_int_operand" ""))) ; start | |
3713 | (clobber (reg:CC CC_REGNUM))] | |
3714 | "TARGET_Z10" | |
3715 | "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift | |
3716 | [(set_attr "op_type" "RIE") | |
3717 | (set_attr "z10prop" "z10_super_E1")]) | |
4023fb28 | 3718 | |
1a2e356e | 3719 | (define_insn_and_split "*pre_z10_extzv<mode>" |
6fa05db6 AS |
3720 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3721 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
1a2e356e | 3722 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3723 | (const_int 0))) |
ae156f85 | 3724 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3725 | "!TARGET_Z10" |
cc7ab9b7 UW |
3726 | "#" |
3727 | "&& reload_completed" | |
4023fb28 | 3728 | [(parallel |
6fa05db6 | 3729 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3730 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 3731 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 3732 | { |
6fa05db6 AS |
3733 | int bitsize = INTVAL (operands[2]); |
3734 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3735 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3736 | ||
3737 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3738 | set_mem_size (operands[1], size); |
2542ef05 | 3739 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 | 3740 | operands[3] = GEN_INT (mask); |
b628bd8e | 3741 | }) |
4023fb28 | 3742 | |
1a2e356e | 3743 | (define_insn_and_split "*pre_z10_extv<mode>" |
6fa05db6 AS |
3744 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3745 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS") | |
1a2e356e | 3746 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3747 | (const_int 0))) |
ae156f85 | 3748 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3749 | "" |
cc7ab9b7 UW |
3750 | "#" |
3751 | "&& reload_completed" | |
4023fb28 | 3752 | [(parallel |
6fa05db6 | 3753 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3754 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
3755 | (parallel |
3756 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
3757 | (clobber (reg:CC CC_REGNUM))])] | |
3758 | { | |
3759 | int bitsize = INTVAL (operands[2]); | |
3760 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3761 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3762 | ||
3763 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3764 | set_mem_size (operands[1], size); |
2542ef05 | 3765 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 AS |
3766 | operands[3] = GEN_INT (mask); |
3767 | }) | |
3768 | ||
3769 | ; | |
3770 | ; insv instruction patterns | |
3771 | ; | |
3772 | ||
3773 | (define_expand "insv" | |
3774 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
3775 | (match_operand 1 "const_int_operand" "") | |
3776 | (match_operand 2 "const_int_operand" "")) | |
3777 | (match_operand 3 "general_operand" ""))] | |
3778 | "" | |
4023fb28 | 3779 | { |
6fa05db6 AS |
3780 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
3781 | DONE; | |
3782 | FAIL; | |
b628bd8e | 3783 | }) |
4023fb28 | 3784 | |
2542ef05 RH |
3785 | |
3786 | ; The normal RTL expansion will never generate a zero_extract where | |
3787 | ; the location operand isn't word mode. However, we do this in the | |
3788 | ; back-end when generating atomic operations. See s390_two_part_insv. | |
22ac2c2f AK |
3789 | (define_insn "*insv<mode>_zEC12" |
3790 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") | |
2542ef05 RH |
3791 | (match_operand 1 "const_int_operand" "I") ; size |
3792 | (match_operand 2 "const_int_operand" "I")) ; pos | |
22ac2c2f AK |
3793 | (match_operand:GPR 3 "nonimmediate_operand" "d"))] |
3794 | "TARGET_ZEC12 | |
2542ef05 RH |
3795 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
3796 | "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1" | |
22ac2c2f AK |
3797 | [(set_attr "op_type" "RIE")]) |
3798 | ||
963fc8d0 AK |
3799 | (define_insn "*insv<mode>_z10" |
3800 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") | |
2542ef05 RH |
3801 | (match_operand 1 "const_int_operand" "I") ; size |
3802 | (match_operand 2 "const_int_operand" "I")) ; pos | |
963fc8d0 AK |
3803 | (match_operand:GPR 3 "nonimmediate_operand" "d")) |
3804 | (clobber (reg:CC CC_REGNUM))] | |
3805 | "TARGET_Z10 | |
2542ef05 RH |
3806 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
3807 | "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1" | |
9381e3f1 WG |
3808 | [(set_attr "op_type" "RIE") |
3809 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 3810 | |
22ac2c2f AK |
3811 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest |
3812 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
3813 | (define_insn "*insv<mode>_zEC12_noshift" | |
3814 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3815 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
75ca1b39 | 3816 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
22ac2c2f | 3817 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") |
75ca1b39 RH |
3818 | (match_operand:GPR 4 "const_int_operand" ""))))] |
3819 | "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
3820 | "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0" | |
22ac2c2f AK |
3821 | [(set_attr "op_type" "RIE")]) |
3822 | ||
963fc8d0 AK |
3823 | (define_insn "*insv<mode>_z10_noshift" |
3824 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3825 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
75ca1b39 | 3826 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
963fc8d0 | 3827 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") |
75ca1b39 | 3828 | (match_operand:GPR 4 "const_int_operand" "")))) |
963fc8d0 | 3829 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 RH |
3830 | "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])" |
3831 | "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0" | |
9381e3f1 WG |
3832 | [(set_attr "op_type" "RIE") |
3833 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 3834 | |
3d44ff99 AK |
3835 | ; Implement appending Y on the left of S bits of X |
3836 | ; x = (y << s) | (x & ((1 << s) - 1)) | |
3837 | (define_insn "*insv<mode>_zEC12_appendbitsleft" | |
3838 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3839 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") | |
3840 | (match_operand:GPR 2 "immediate_operand" "")) | |
3841 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") | |
3842 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
3843 | "TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1" | |
3844 | "risbgn\t%0,%3,64-<bitsize>,64-%4-1,%4" | |
3845 | [(set_attr "op_type" "RIE") | |
3846 | (set_attr "z10prop" "z10_super_E1")]) | |
3847 | ||
3848 | (define_insn "*insv<mode>_z10_appendbitsleft" | |
3849 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3850 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") | |
3851 | (match_operand:GPR 2 "immediate_operand" "")) | |
3852 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") | |
3853 | (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) | |
3854 | (clobber (reg:CC CC_REGNUM))] | |
3855 | "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1" | |
3856 | "risbg\t%0,%3,64-<bitsize>,64-%4-1,%4" | |
3857 | [(set_attr "op_type" "RIE") | |
3858 | (set_attr "z10prop" "z10_super_E1")]) | |
3859 | ||
3860 | ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting | |
3861 | ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1)) | |
3862 | ; -> z = y >> d; z = risbg; | |
3863 | ||
3864 | (define_split | |
3865 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
3866 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
3867 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
3868 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
3869 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
3870 | "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
3871 | [(set (match_dup 0) | |
3872 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) | |
3873 | (set (match_dup 0) | |
3874 | (ior:GPR (and:GPR (match_dup 0) (match_dup 5)) | |
3875 | (ashift:GPR (match_dup 3) (match_dup 4))))] | |
3876 | { | |
3877 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
3878 | }) | |
3879 | ||
3880 | (define_split | |
3881 | [(parallel | |
3882 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
3883 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
3884 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
3885 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
3886 | (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) | |
3887 | (clobber (reg:CC CC_REGNUM))])] | |
3888 | "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
3889 | [(set (match_dup 0) | |
3890 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) | |
3891 | (parallel | |
3892 | [(set (match_dup 0) | |
3893 | (ior:GPR (and:GPR (match_dup 0) (match_dup 5)) | |
3894 | (ashift:GPR (match_dup 3) (match_dup 4)))) | |
3895 | (clobber (reg:CC CC_REGNUM))])] | |
3896 | { | |
3897 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
3898 | }) | |
3899 | ||
571e408a | 3900 | (define_insn "*r<noxa>sbg_<mode>_noshift" |
963fc8d0 | 3901 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
571e408a RH |
3902 | (IXOR:GPR |
3903 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3904 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
3905 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
963fc8d0 | 3906 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 | 3907 | "TARGET_Z10" |
571e408a RH |
3908 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0" |
3909 | [(set_attr "op_type" "RIE")]) | |
3910 | ||
3911 | (define_insn "*r<noxa>sbg_di_rotl" | |
3912 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") | |
3913 | (IXOR:DI | |
3914 | (and:DI | |
3915 | (rotate:DI | |
3916 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
3917 | (match_operand:DI 3 "const_int_operand" "")) | |
3918 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
3919 | (match_operand:DI 4 "nonimmediate_operand" "0"))) | |
3920 | (clobber (reg:CC CC_REGNUM))] | |
3921 | "TARGET_Z10" | |
3922 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3" | |
3923 | [(set_attr "op_type" "RIE")]) | |
3924 | ||
3925 | (define_insn "*r<noxa>sbg_<mode>_srl" | |
3926 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3927 | (IXOR:GPR | |
3928 | (and:GPR | |
3929 | (lshiftrt:GPR | |
3930 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3931 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
3932 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
3933 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) | |
3934 | (clobber (reg:CC CC_REGNUM))] | |
3935 | "TARGET_Z10 | |
3936 | && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), | |
3937 | INTVAL (operands[2]))" | |
3938 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3" | |
3939 | [(set_attr "op_type" "RIE")]) | |
3940 | ||
3941 | (define_insn "*r<noxa>sbg_<mode>_sll" | |
3942 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
3943 | (IXOR:GPR | |
3944 | (and:GPR | |
3945 | (ashift:GPR | |
3946 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
3947 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
3948 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
3949 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) | |
3950 | (clobber (reg:CC CC_REGNUM))] | |
3951 | "TARGET_Z10 | |
3952 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]), | |
3953 | INTVAL (operands[2]))" | |
3954 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3" | |
963fc8d0 AK |
3955 | [(set_attr "op_type" "RIE")]) |
3956 | ||
5bb33936 RH |
3957 | ;; These two are generated by combine for s.bf &= val. |
3958 | ;; ??? For bitfields smaller than 32-bits, we wind up with SImode | |
3959 | ;; shifts and ands, which results in some truly awful patterns | |
3960 | ;; including subregs of operations. Rather unnecessisarily, IMO. | |
3961 | ;; Instead of | |
3962 | ;; | |
3963 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
3964 | ;; (const_int 24 [0x18]) | |
3965 | ;; (const_int 0 [0])) | |
3966 | ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
3967 | ;; (const_int 40 [0x28])) 4) | |
3968 | ;; (reg:SI 4 %r4 [ y+4 ])) 0)) | |
3969 | ;; | |
3970 | ;; we should instead generate | |
3971 | ;; | |
3972 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
3973 | ;; (const_int 24 [0x18]) | |
3974 | ;; (const_int 0 [0])) | |
3975 | ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
3976 | ;; (const_int 40 [0x28])) | |
3977 | ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0))) | |
3978 | ;; | |
3979 | ;; by noticing that we can push down the outer paradoxical subreg | |
3980 | ;; into the operation. | |
3981 | ||
3982 | (define_insn "*insv_rnsbg_noshift" | |
3983 | [(set (zero_extract:DI | |
3984 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
3985 | (match_operand 1 "const_int_operand" "") | |
3986 | (match_operand 2 "const_int_operand" "")) | |
3987 | (and:DI | |
3988 | (match_dup 0) | |
3989 | (match_operand:DI 3 "nonimmediate_operand" "d"))) | |
3990 | (clobber (reg:CC CC_REGNUM))] | |
3991 | "TARGET_Z10 | |
3992 | && INTVAL (operands[1]) + INTVAL (operands[2]) == 64" | |
3993 | "rnsbg\t%0,%3,%2,63,0" | |
3994 | [(set_attr "op_type" "RIE")]) | |
3995 | ||
3996 | (define_insn "*insv_rnsbg_srl" | |
3997 | [(set (zero_extract:DI | |
3998 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
3999 | (match_operand 1 "const_int_operand" "") | |
4000 | (match_operand 2 "const_int_operand" "")) | |
4001 | (and:DI | |
4002 | (lshiftrt:DI | |
4003 | (match_dup 0) | |
4004 | (match_operand 3 "const_int_operand" "")) | |
4005 | (match_operand:DI 4 "nonimmediate_operand" "d"))) | |
4006 | (clobber (reg:CC CC_REGNUM))] | |
4007 | "TARGET_Z10 | |
4008 | && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])" | |
4009 | "rnsbg\t%0,%4,%2,%2+%1-1,%3" | |
4010 | [(set_attr "op_type" "RIE")]) | |
4011 | ||
6fa05db6 | 4012 | (define_insn "*insv<mode>_mem_reg" |
9602b6a1 | 4013 | [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") |
6fa05db6 AS |
4014 | (match_operand 1 "const_int_operand" "n,n") |
4015 | (const_int 0)) | |
9602b6a1 | 4016 | (match_operand:W 2 "register_operand" "d,d"))] |
6fa05db6 AS |
4017 | "INTVAL (operands[1]) > 0 |
4018 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
4019 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4020 | { | |
4021 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4022 | ||
4023 | operands[1] = GEN_INT ((1ul << size) - 1); | |
9381e3f1 | 4024 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
4025 | : "stcmy\t%2,%1,%S0"; |
4026 | } | |
9381e3f1 WG |
4027 | [(set_attr "op_type" "RS,RSY") |
4028 | (set_attr "z10prop" "z10_super,z10_super")]) | |
6fa05db6 AS |
4029 | |
4030 | (define_insn "*insvdi_mem_reghigh" | |
4031 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") | |
4032 | (match_operand 1 "const_int_operand" "n") | |
4033 | (const_int 0)) | |
4034 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
4035 | (const_int 32)))] | |
9602b6a1 | 4036 | "TARGET_ZARCH |
6fa05db6 AS |
4037 | && INTVAL (operands[1]) > 0 |
4038 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
4039 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4040 | { | |
4041 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4042 | ||
4043 | operands[1] = GEN_INT ((1ul << size) - 1); | |
4044 | return "stcmh\t%2,%1,%S0"; | |
4045 | } | |
9381e3f1 WG |
4046 | [(set_attr "op_type" "RSY") |
4047 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 | 4048 | |
9602b6a1 AK |
4049 | (define_insn "*insvdi_reg_imm" |
4050 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4051 | (const_int 16) | |
4052 | (match_operand 1 "const_int_operand" "n")) | |
4053 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6fa05db6 AS |
4054 | "TARGET_ZARCH |
4055 | && INTVAL (operands[1]) >= 0 | |
4056 | && INTVAL (operands[1]) < BITS_PER_WORD | |
4057 | && INTVAL (operands[1]) % 16 == 0" | |
4058 | { | |
4059 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
4060 | { | |
4061 | case 64: return "iihh\t%0,%x2"; break; | |
4062 | case 48: return "iihl\t%0,%x2"; break; | |
4063 | case 32: return "iilh\t%0,%x2"; break; | |
4064 | case 16: return "iill\t%0,%x2"; break; | |
4065 | default: gcc_unreachable(); | |
4066 | } | |
4067 | } | |
9381e3f1 WG |
4068 | [(set_attr "op_type" "RI") |
4069 | (set_attr "z10prop" "z10_super_E1")]) | |
4070 | ||
9fec758d WG |
4071 | ; Update the left-most 32 bit of a DI. |
4072 | (define_insn "*insv_h_di_reg_extimm" | |
4073 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4074 | (const_int 32) | |
4075 | (const_int 0)) | |
4076 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4077 | "TARGET_EXTIMM" | |
4078 | "iihf\t%0,%o1" | |
4079 | [(set_attr "op_type" "RIL") | |
4080 | (set_attr "z10prop" "z10_fwd_E1")]) | |
6fa05db6 | 4081 | |
d378b983 RH |
4082 | ; Update the right-most 32 bit of a DI. |
4083 | (define_insn "*insv_l_di_reg_extimm" | |
4084 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4085 | (const_int 32) | |
4086 | (const_int 32)) | |
4087 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4088 | "TARGET_EXTIMM" | |
4089 | "iilf\t%0,%o1" | |
9381e3f1 | 4090 | [(set_attr "op_type" "RIL") |
9fec758d | 4091 | (set_attr "z10prop" "z10_fwd_A1")]) |
6fa05db6 | 4092 | |
9db1d521 HP |
4093 | ; |
4094 | ; extendsidi2 instruction pattern(s). | |
4095 | ; | |
4096 | ||
4023fb28 UW |
4097 | (define_expand "extendsidi2" |
4098 | [(set (match_operand:DI 0 "register_operand" "") | |
4099 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4100 | "" | |
4023fb28 | 4101 | { |
9602b6a1 | 4102 | if (!TARGET_ZARCH) |
4023fb28 | 4103 | { |
c41c1387 | 4104 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4105 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
4106 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
4107 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
4108 | DONE; |
4109 | } | |
ec24698e | 4110 | }) |
4023fb28 UW |
4111 | |
4112 | (define_insn "*extendsidi2" | |
963fc8d0 AK |
4113 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
4114 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9602b6a1 | 4115 | "TARGET_ZARCH" |
9db1d521 | 4116 | "@ |
d40c829f | 4117 | lgfr\t%0,%1 |
963fc8d0 AK |
4118 | lgf\t%0,%1 |
4119 | lgfrl\t%0,%1" | |
4120 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4121 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4122 | (set_attr "cpu_facility" "*,*,z10") |
4123 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4124 | |
9db1d521 | 4125 | ; |
56477c21 | 4126 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4127 | ; |
4128 | ||
56477c21 AS |
4129 | (define_expand "extend<HQI:mode><DSI:mode>2" |
4130 | [(set (match_operand:DSI 0 "register_operand" "") | |
4131 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 4132 | "" |
4023fb28 | 4133 | { |
9602b6a1 | 4134 | if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) |
4023fb28 UW |
4135 | { |
4136 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 4137 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
4138 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
4139 | DONE; | |
4140 | } | |
ec24698e | 4141 | else if (!TARGET_EXTIMM) |
4023fb28 | 4142 | { |
2542ef05 | 4143 | rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>); |
56477c21 AS |
4144 | |
4145 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
4146 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
4147 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
4148 | DONE; |
4149 | } | |
ec24698e UW |
4150 | }) |
4151 | ||
56477c21 AS |
4152 | ; |
4153 | ; extendhidi2 instruction pattern(s). | |
4154 | ; | |
4155 | ||
ec24698e | 4156 | (define_insn "*extendhidi2_extimm" |
963fc8d0 AK |
4157 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
4158 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))] | |
9602b6a1 | 4159 | "TARGET_ZARCH && TARGET_EXTIMM" |
ec24698e UW |
4160 | "@ |
4161 | lghr\t%0,%1 | |
963fc8d0 AK |
4162 | lgh\t%0,%1 |
4163 | lghrl\t%0,%1" | |
4164 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4165 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4166 | (set_attr "cpu_facility" "extimm,extimm,z10") |
4167 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
4168 | |
4169 | (define_insn "*extendhidi2" | |
9db1d521 | 4170 | [(set (match_operand:DI 0 "register_operand" "=d") |
fb492564 | 4171 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] |
9602b6a1 | 4172 | "TARGET_ZARCH" |
d40c829f | 4173 | "lgh\t%0,%1" |
9381e3f1 WG |
4174 | [(set_attr "op_type" "RXY") |
4175 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 4176 | |
9db1d521 | 4177 | ; |
56477c21 | 4178 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
4179 | ; |
4180 | ||
ec24698e | 4181 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
4182 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4183 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
4184 | "TARGET_EXTIMM" |
4185 | "@ | |
4186 | lhr\t%0,%1 | |
4187 | lh\t%0,%1 | |
963fc8d0 AK |
4188 | lhy\t%0,%1 |
4189 | lhrl\t%0,%1" | |
4190 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
4191 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 WG |
4192 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
4193 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4194 | |
4023fb28 | 4195 | (define_insn "*extendhisi2" |
d3632d41 UW |
4196 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4197 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 4198 | "!TARGET_EXTIMM" |
d3632d41 | 4199 | "@ |
d40c829f UW |
4200 | lh\t%0,%1 |
4201 | lhy\t%0,%1" | |
9381e3f1 WG |
4202 | [(set_attr "op_type" "RX,RXY") |
4203 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4204 | |
56477c21 AS |
4205 | ; |
4206 | ; extendqi(si|di)2 instruction pattern(s). | |
4207 | ; | |
4208 | ||
43a09b63 | 4209 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
4210 | (define_insn "*extendqi<mode>2_extimm" |
4211 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 4212 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
4213 | "TARGET_EXTIMM" |
4214 | "@ | |
56477c21 AS |
4215 | l<g>br\t%0,%1 |
4216 | l<g>b\t%0,%1" | |
9381e3f1 WG |
4217 | [(set_attr "op_type" "RRE,RXY") |
4218 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 4219 | |
43a09b63 | 4220 | ; lb, lgb |
56477c21 AS |
4221 | (define_insn "*extendqi<mode>2" |
4222 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 4223 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))] |
56477c21 AS |
4224 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
4225 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
4226 | [(set_attr "op_type" "RXY") |
4227 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 4228 | |
56477c21 AS |
4229 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
4230 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4231 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 4232 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 4233 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
4234 | "#" |
4235 | "&& reload_completed" | |
4023fb28 | 4236 | [(parallel |
56477c21 | 4237 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 4238 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 4239 | (parallel |
56477c21 | 4240 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 4241 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
4242 | { |
4243 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4244 | set_mem_size (operands[1], GET_MODE_SIZE (QImode)); |
2542ef05 | 4245 | operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT); |
6fa05db6 | 4246 | }) |
9db1d521 | 4247 | |
9db1d521 HP |
4248 | ; |
4249 | ; zero_extendsidi2 instruction pattern(s). | |
4250 | ; | |
4251 | ||
4023fb28 UW |
4252 | (define_expand "zero_extendsidi2" |
4253 | [(set (match_operand:DI 0 "register_operand" "") | |
4254 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4255 | "" | |
4023fb28 | 4256 | { |
9602b6a1 | 4257 | if (!TARGET_ZARCH) |
4023fb28 | 4258 | { |
c41c1387 | 4259 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4260 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
4261 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
4262 | DONE; |
4263 | } | |
ec24698e | 4264 | }) |
4023fb28 UW |
4265 | |
4266 | (define_insn "*zero_extendsidi2" | |
963fc8d0 AK |
4267 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
4268 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] | |
9602b6a1 | 4269 | "TARGET_ZARCH" |
9db1d521 | 4270 | "@ |
d40c829f | 4271 | llgfr\t%0,%1 |
963fc8d0 AK |
4272 | llgf\t%0,%1 |
4273 | llgfrl\t%0,%1" | |
4274 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4275 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4276 | (set_attr "cpu_facility" "*,*,z10") |
4277 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) | |
9db1d521 | 4278 | |
288e517f AK |
4279 | ; |
4280 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
4281 | ; | |
4282 | ||
d6083c7d UW |
4283 | (define_insn "*llgt_sidi" |
4284 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 4285 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d | 4286 | (const_int 2147483647)))] |
9602b6a1 | 4287 | "TARGET_ZARCH" |
d6083c7d | 4288 | "llgt\t%0,%1" |
9381e3f1 WG |
4289 | [(set_attr "op_type" "RXE") |
4290 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
4291 | |
4292 | (define_insn_and_split "*llgt_sidi_split" | |
4293 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 4294 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) |
d6083c7d | 4295 | (const_int 2147483647))) |
ae156f85 | 4296 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4297 | "TARGET_ZARCH" |
d6083c7d UW |
4298 | "#" |
4299 | "&& reload_completed" | |
4300 | [(set (match_dup 0) | |
4301 | (and:DI (subreg:DI (match_dup 1) 0) | |
4302 | (const_int 2147483647)))] | |
4303 | "") | |
4304 | ||
288e517f AK |
4305 | (define_insn "*llgt_sisi" |
4306 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
fb492564 | 4307 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT") |
288e517f | 4308 | (const_int 2147483647)))] |
c4d50129 | 4309 | "TARGET_ZARCH" |
288e517f AK |
4310 | "@ |
4311 | llgtr\t%0,%1 | |
4312 | llgt\t%0,%1" | |
9381e3f1 WG |
4313 | [(set_attr "op_type" "RRE,RXE") |
4314 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4315 | |
288e517f AK |
4316 | (define_insn "*llgt_didi" |
4317 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4318 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
4319 | (const_int 2147483647)))] | |
9602b6a1 | 4320 | "TARGET_ZARCH" |
288e517f AK |
4321 | "@ |
4322 | llgtr\t%0,%1 | |
4323 | llgt\t%0,%N1" | |
9381e3f1 WG |
4324 | [(set_attr "op_type" "RRE,RXE") |
4325 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4326 | |
f19a9af7 | 4327 | (define_split |
9602b6a1 AK |
4328 | [(set (match_operand:DSI 0 "register_operand" "") |
4329 | (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") | |
f6ee577c | 4330 | (const_int 2147483647))) |
ae156f85 | 4331 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 4332 | "TARGET_ZARCH && reload_completed" |
288e517f | 4333 | [(set (match_dup 0) |
9602b6a1 | 4334 | (and:DSI (match_dup 1) |
f6ee577c | 4335 | (const_int 2147483647)))] |
288e517f AK |
4336 | "") |
4337 | ||
9db1d521 | 4338 | ; |
56477c21 | 4339 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4340 | ; |
4341 | ||
56477c21 AS |
4342 | (define_expand "zero_extend<mode>di2" |
4343 | [(set (match_operand:DI 0 "register_operand" "") | |
4344 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4345 | "" | |
4346 | { | |
9602b6a1 | 4347 | if (!TARGET_ZARCH) |
56477c21 AS |
4348 | { |
4349 | rtx tmp = gen_reg_rtx (SImode); | |
4350 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
4351 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
4352 | DONE; | |
4353 | } | |
4354 | else if (!TARGET_EXTIMM) | |
4355 | { | |
2542ef05 | 4356 | rtx bitcount = GEN_INT (64 - <HQI:bitsize>); |
56477c21 AS |
4357 | operands[1] = gen_lowpart (DImode, operands[1]); |
4358 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
4359 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
4360 | DONE; | |
4361 | } | |
4362 | }) | |
4363 | ||
f6ee577c | 4364 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 4365 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 4366 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 4367 | "" |
4023fb28 | 4368 | { |
ec24698e UW |
4369 | if (!TARGET_EXTIMM) |
4370 | { | |
4371 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 4372 | emit_insn (gen_andsi3 (operands[0], operands[1], |
2542ef05 | 4373 | GEN_INT ((1 << <HQI:bitsize>) - 1))); |
ec24698e | 4374 | DONE; |
56477c21 | 4375 | } |
ec24698e UW |
4376 | }) |
4377 | ||
963fc8d0 AK |
4378 | ; llhrl, llghrl |
4379 | (define_insn "*zero_extendhi<mode>2_z10" | |
4380 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
4381 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))] | |
4382 | "TARGET_Z10" | |
4383 | "@ | |
4384 | ll<g>hr\t%0,%1 | |
4385 | ll<g>h\t%0,%1 | |
4386 | ll<g>hrl\t%0,%1" | |
4387 | [(set_attr "op_type" "RXY,RRE,RIL") | |
4388 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4389 | (set_attr "cpu_facility" "*,*,z10") |
729e750f | 4390 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) |
963fc8d0 | 4391 | |
43a09b63 | 4392 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
4393 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
4394 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
fb492564 | 4395 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))] |
ec24698e UW |
4396 | "TARGET_EXTIMM" |
4397 | "@ | |
56477c21 AS |
4398 | ll<g><hc>r\t%0,%1 |
4399 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
4400 | [(set_attr "op_type" "RRE,RXY") |
4401 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 4402 | |
43a09b63 | 4403 | ; llgh, llgc |
56477c21 AS |
4404 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
4405 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
fb492564 | 4406 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))] |
ec24698e | 4407 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 4408 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
4409 | [(set_attr "op_type" "RXY") |
4410 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
4411 | |
4412 | (define_insn_and_split "*zero_extendhisi2_31" | |
4413 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
02ed3c5e | 4414 | (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) |
ae156f85 | 4415 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 4416 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4417 | "#" |
4418 | "&& reload_completed" | |
4419 | [(set (match_dup 0) (const_int 0)) | |
4420 | (parallel | |
4421 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 4422 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4423 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 4424 | |
cc7ab9b7 UW |
4425 | (define_insn_and_split "*zero_extendqisi2_31" |
4426 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
fb492564 | 4427 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 4428 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4429 | "#" |
4430 | "&& reload_completed" | |
4431 | [(set (match_dup 0) (const_int 0)) | |
4432 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4433 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 4434 | |
9db1d521 HP |
4435 | ; |
4436 | ; zero_extendqihi2 instruction pattern(s). | |
4437 | ; | |
4438 | ||
9db1d521 HP |
4439 | (define_expand "zero_extendqihi2" |
4440 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 4441 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 4442 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 4443 | { |
4023fb28 UW |
4444 | operands[1] = gen_lowpart (HImode, operands[1]); |
4445 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
4446 | DONE; | |
ec24698e | 4447 | }) |
9db1d521 | 4448 | |
4023fb28 | 4449 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 4450 | [(set (match_operand:HI 0 "register_operand" "=d") |
fb492564 | 4451 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
ec24698e | 4452 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 4453 | "llgc\t%0,%1" |
9381e3f1 WG |
4454 | [(set_attr "op_type" "RXY") |
4455 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 4456 | |
cc7ab9b7 UW |
4457 | (define_insn_and_split "*zero_extendqihi2_31" |
4458 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
fb492564 | 4459 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] |
9e8327e3 | 4460 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4461 | "#" |
4462 | "&& reload_completed" | |
4463 | [(set (match_dup 0) (const_int 0)) | |
4464 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4465 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 4466 | |
609e7e80 AK |
4467 | ; |
4468 | ; fixuns_trunc(dd|td)di2 instruction pattern(s). | |
4469 | ; | |
4470 | ||
4471 | (define_expand "fixuns_truncdddi2" | |
4472 | [(parallel | |
4473 | [(set (match_operand:DI 0 "register_operand" "") | |
4474 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) | |
65b1d8ea AK |
4475 | (unspec:DI [(const_int 5)] UNSPEC_ROUND) |
4476 | (clobber (reg:CC CC_REGNUM))])] | |
9381e3f1 | 4477 | |
fb068247 | 4478 | "TARGET_HARD_DFP" |
609e7e80 | 4479 | { |
65b1d8ea AK |
4480 | if (!TARGET_Z196) |
4481 | { | |
19f8b229 TS |
4482 | rtx_code_label *label1 = gen_label_rtx (); |
4483 | rtx_code_label *label2 = gen_label_rtx (); | |
65b1d8ea AK |
4484 | rtx temp = gen_reg_rtx (TDmode); |
4485 | REAL_VALUE_TYPE cmp, sub; | |
4486 | ||
4487 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4488 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4489 | ||
4490 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
4491 | solution is doing the check and the subtraction in TD mode and using a | |
4492 | TD -> DI convert afterwards. */ | |
4493 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
4494 | temp = force_reg (TDmode, temp); | |
4495 | emit_cmp_and_jump_insns (temp, | |
555affd7 | 4496 | const_double_from_real_value (cmp, TDmode), |
65b1d8ea AK |
4497 | LT, NULL_RTX, VOIDmode, 0, label1); |
4498 | emit_insn (gen_subtd3 (temp, temp, | |
555affd7 | 4499 | const_double_from_real_value (sub, TDmode))); |
65b1d8ea AK |
4500 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); |
4501 | emit_jump (label2); | |
4502 | ||
4503 | emit_label (label1); | |
4504 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9))); | |
4505 | emit_label (label2); | |
4506 | DONE; | |
4507 | } | |
609e7e80 AK |
4508 | }) |
4509 | ||
4510 | (define_expand "fixuns_trunctddi2" | |
65b1d8ea AK |
4511 | [(parallel |
4512 | [(set (match_operand:DI 0 "register_operand" "") | |
4513 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) | |
4514 | (unspec:DI [(const_int 5)] UNSPEC_ROUND) | |
4515 | (clobber (reg:CC CC_REGNUM))])] | |
4516 | ||
fb068247 | 4517 | "TARGET_HARD_DFP" |
609e7e80 | 4518 | { |
65b1d8ea AK |
4519 | if (!TARGET_Z196) |
4520 | { | |
19f8b229 TS |
4521 | rtx_code_label *label1 = gen_label_rtx (); |
4522 | rtx_code_label *label2 = gen_label_rtx (); | |
65b1d8ea AK |
4523 | rtx temp = gen_reg_rtx (TDmode); |
4524 | REAL_VALUE_TYPE cmp, sub; | |
4525 | ||
4526 | operands[1] = force_reg (TDmode, operands[1]); | |
4527 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4528 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4529 | ||
4530 | emit_cmp_and_jump_insns (operands[1], | |
555affd7 | 4531 | const_double_from_real_value (cmp, TDmode), |
65b1d8ea AK |
4532 | LT, NULL_RTX, VOIDmode, 0, label1); |
4533 | emit_insn (gen_subtd3 (temp, operands[1], | |
555affd7 | 4534 | const_double_from_real_value (sub, TDmode))); |
65b1d8ea AK |
4535 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); |
4536 | emit_jump (label2); | |
4537 | ||
4538 | emit_label (label1); | |
4539 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9))); | |
4540 | emit_label (label2); | |
4541 | DONE; | |
4542 | } | |
609e7e80 | 4543 | }) |
cc7ab9b7 | 4544 | |
9db1d521 | 4545 | ; |
65b1d8ea | 4546 | ; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2 |
609e7e80 | 4547 | ; instruction pattern(s). |
9db1d521 HP |
4548 | ; |
4549 | ||
7b6baae1 | 4550 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2" |
65b1d8ea AK |
4551 | [(parallel |
4552 | [(set (match_operand:GPR 0 "register_operand" "") | |
4553 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) | |
4554 | (unspec:GPR [(const_int 5)] UNSPEC_ROUND) | |
4555 | (clobber (reg:CC CC_REGNUM))])] | |
142cd70f | 4556 | "TARGET_HARD_FLOAT" |
9db1d521 | 4557 | { |
65b1d8ea AK |
4558 | if (!TARGET_Z196) |
4559 | { | |
19f8b229 TS |
4560 | rtx_code_label *label1 = gen_label_rtx (); |
4561 | rtx_code_label *label2 = gen_label_rtx (); | |
65b1d8ea AK |
4562 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); |
4563 | REAL_VALUE_TYPE cmp, sub; | |
4564 | ||
4565 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); | |
2542ef05 RH |
4566 | real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode); |
4567 | real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode); | |
65b1d8ea AK |
4568 | |
4569 | emit_cmp_and_jump_insns (operands[1], | |
555affd7 | 4570 | const_double_from_real_value (cmp, <BFP:MODE>mode), |
65b1d8ea AK |
4571 | LT, NULL_RTX, VOIDmode, 0, label1); |
4572 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], | |
555affd7 | 4573 | const_double_from_real_value (sub, <BFP:MODE>mode))); |
65b1d8ea AK |
4574 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, |
4575 | GEN_INT (7))); | |
4576 | emit_jump (label2); | |
4577 | ||
4578 | emit_label (label1); | |
4579 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], | |
4580 | operands[1], GEN_INT (5))); | |
4581 | emit_label (label2); | |
4582 | DONE; | |
4583 | } | |
10bbf137 | 4584 | }) |
9db1d521 | 4585 | |
65b1d8ea AK |
4586 | ; fixuns_trunc(td|dd)si2 expander |
4587 | (define_expand "fixuns_trunc<mode>si2" | |
4588 | [(parallel | |
4589 | [(set (match_operand:SI 0 "register_operand" "") | |
4590 | (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) | |
4591 | (unspec:SI [(const_int 5)] UNSPEC_ROUND) | |
4592 | (clobber (reg:CC CC_REGNUM))])] | |
8540e6e8 | 4593 | "TARGET_Z196 && TARGET_HARD_DFP" |
65b1d8ea AK |
4594 | "") |
4595 | ||
4596 | ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. | |
4597 | ||
6e5b5de8 AK |
4598 | (define_insn "*fixuns_truncdfdi2_z13" |
4599 | [(set (match_operand:DI 0 "register_operand" "=d,v") | |
4600 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
4601 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
4602 | (clobber (reg:CC CC_REGNUM))] | |
4603 | "TARGET_Z13 && TARGET_HARD_FLOAT" | |
4604 | "@ | |
4605 | clgdbr\t%0,%h2,%1,0 | |
4606 | wclgdb\t%v0,%v1,0,%h2" | |
4607 | [(set_attr "op_type" "RRF,VRR") | |
4608 | (set_attr "type" "ftoi")]) | |
4609 | ||
65b1d8ea AK |
4610 | ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr |
4611 | ; clfdtr, clfxtr, clgdtr, clgxtr | |
4612 | (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" | |
6e5b5de8 AK |
4613 | [(set (match_operand:GPR 0 "register_operand" "=d") |
4614 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) | |
4615 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
65b1d8ea | 4616 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 AK |
4617 | "TARGET_Z196 && TARGET_HARD_FLOAT |
4618 | && (!TARGET_Z13 || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)" | |
65b1d8ea AK |
4619 | "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" |
4620 | [(set_attr "op_type" "RRF") | |
4621 | (set_attr "type" "ftoi")]) | |
4622 | ||
b60cb710 AK |
4623 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
4624 | [(set (match_operand:GPR 0 "register_operand" "") | |
4625 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
4626 | "TARGET_HARD_FLOAT" | |
9db1d521 | 4627 | { |
b60cb710 AK |
4628 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
4629 | GEN_INT (5))); | |
9db1d521 | 4630 | DONE; |
10bbf137 | 4631 | }) |
9db1d521 | 4632 | |
6e5b5de8 AK |
4633 | (define_insn "*fix_truncdfdi2_bfp_z13" |
4634 | [(set (match_operand:DI 0 "register_operand" "=d,v") | |
4635 | (fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
4636 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
4637 | (clobber (reg:CC CC_REGNUM))] | |
4638 | "TARGET_Z13 && TARGET_HARD_FLOAT" | |
4639 | "@ | |
4640 | cgdbr\t%0,%h2,%1 | |
4641 | wcgdb\t%v0,%v1,0,%h2" | |
4642 | [(set_attr "op_type" "RRE,VRR") | |
4643 | (set_attr "type" "ftoi")]) | |
4644 | ||
43a09b63 | 4645 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
6e5b5de8 AK |
4646 | (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp" |
4647 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4648 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
4649 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
ae156f85 | 4650 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 AK |
4651 | "TARGET_HARD_FLOAT |
4652 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)" | |
7b6baae1 | 4653 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 4654 | [(set_attr "op_type" "RRE") |
077dab3b | 4655 | (set_attr "type" "ftoi")]) |
9db1d521 | 4656 | |
6e5b5de8 AK |
4657 | (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
4658 | [(parallel | |
4659 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4660 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
4661 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4662 | (clobber (reg:CC CC_REGNUM))])] | |
4663 | "TARGET_HARD_FLOAT") | |
609e7e80 AK |
4664 | ; |
4665 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
4666 | ; | |
4667 | ||
99cd7dd0 AK |
4668 | (define_expand "fix_trunc<mode>di2" |
4669 | [(set (match_operand:DI 0 "register_operand" "") | |
4670 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
9602b6a1 | 4671 | "TARGET_ZARCH && TARGET_HARD_DFP" |
99cd7dd0 AK |
4672 | { |
4673 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
4674 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
4675 | GEN_INT (9))); | |
4676 | DONE; | |
4677 | }) | |
4678 | ||
609e7e80 | 4679 | ; cgxtr, cgdtr |
99cd7dd0 | 4680 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
4681 | [(set (match_operand:DI 0 "register_operand" "=d") |
4682 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
4683 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4684 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 4685 | "TARGET_ZARCH && TARGET_HARD_DFP" |
609e7e80 AK |
4686 | "cg<DFP:xde>tr\t%0,%h2,%1" |
4687 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 4688 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
4689 | |
4690 | ||
f61a2c7d AK |
4691 | ; |
4692 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
4693 | ; | |
4694 | ||
4695 | (define_expand "fix_trunctf<mode>2" | |
4696 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
4697 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
4698 | (unspec:GPR [(const_int 5)] UNSPEC_ROUND) | |
4699 | (clobber (reg:CC CC_REGNUM))])] | |
9db1d521 | 4700 | "TARGET_HARD_FLOAT" |
142cd70f | 4701 | "") |
9db1d521 | 4702 | |
9db1d521 | 4703 | |
9db1d521 | 4704 | ; |
142cd70f | 4705 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
4706 | ; |
4707 | ||
609e7e80 | 4708 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 4709 | (define_insn "floatdi<mode>2" |
6e5b5de8 AK |
4710 | [(set (match_operand:FP 0 "register_operand" "=f,<vf>") |
4711 | (float:FP (match_operand:DI 1 "register_operand" "d,<vd>")))] | |
9602b6a1 | 4712 | "TARGET_ZARCH && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
4713 | "@ |
4714 | c<xde>g<bt>r\t%0,%1 | |
4715 | wcdgb\t%v0,%v1,0,0" | |
4716 | [(set_attr "op_type" "RRE,VRR") | |
4717 | (set_attr "type" "itof<mode>" ) | |
4718 | (set_attr "cpu_facility" "*,vec")]) | |
9db1d521 | 4719 | |
43a09b63 | 4720 | ; cxfbr, cdfbr, cefbr |
142cd70f | 4721 | (define_insn "floatsi<mode>2" |
7b6baae1 AK |
4722 | [(set (match_operand:BFP 0 "register_operand" "=f") |
4723 | (float:BFP (match_operand:SI 1 "register_operand" "d")))] | |
142cd70f | 4724 | "TARGET_HARD_FLOAT" |
f61a2c7d AK |
4725 | "c<xde>fbr\t%0,%1" |
4726 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 4727 | (set_attr "type" "itof<mode>" )]) |
f61a2c7d | 4728 | |
65b1d8ea AK |
4729 | ; cxftr, cdftr |
4730 | (define_insn "floatsi<mode>2" | |
4731 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
4732 | (float:DFP (match_operand:SI 1 "register_operand" "d")))] | |
4733 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
4734 | "c<xde>ftr\t%0,0,%1,0" | |
4735 | [(set_attr "op_type" "RRE") | |
4736 | (set_attr "type" "itof<mode>" )]) | |
4737 | ||
4738 | ; | |
4739 | ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). | |
4740 | ; | |
4741 | ||
6e5b5de8 AK |
4742 | (define_insn "*floatunsdidf2_z13" |
4743 | [(set (match_operand:DF 0 "register_operand" "=f,v") | |
4744 | (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))] | |
4745 | "TARGET_Z13 && TARGET_HARD_FLOAT" | |
4746 | "@ | |
4747 | cdlgbr\t%0,0,%1,0 | |
4748 | wcdlgb\t%v0,%v1,0,0" | |
4749 | [(set_attr "op_type" "RRE,VRR") | |
4750 | (set_attr "type" "itofdf")]) | |
4751 | ||
65b1d8ea AK |
4752 | ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr |
4753 | ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr | |
6e5b5de8 AK |
4754 | (define_insn "*floatuns<GPR:mode><FP:mode>2" |
4755 | [(set (match_operand:FP 0 "register_operand" "=f") | |
4756 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] | |
4757 | "TARGET_Z196 && TARGET_HARD_FLOAT | |
4758 | && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)" | |
65b1d8ea AK |
4759 | "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" |
4760 | [(set_attr "op_type" "RRE") | |
6e5b5de8 AK |
4761 | (set_attr "type" "itof<FP:mode>")]) |
4762 | ||
4763 | (define_expand "floatuns<GPR:mode><FP:mode>2" | |
4764 | [(set (match_operand:FP 0 "register_operand" "") | |
4765 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))] | |
4766 | "TARGET_Z196 && TARGET_HARD_FLOAT") | |
f61a2c7d | 4767 | |
9db1d521 HP |
4768 | ; |
4769 | ; truncdfsf2 instruction pattern(s). | |
4770 | ; | |
4771 | ||
142cd70f | 4772 | (define_insn "truncdfsf2" |
6e5b5de8 AK |
4773 | [(set (match_operand:SF 0 "register_operand" "=f,v") |
4774 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))] | |
142cd70f | 4775 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
4776 | "@ |
4777 | ledbr\t%0,%1 | |
4778 | wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed | |
4779 | ; According to BFP rounding mode | |
4780 | [(set_attr "op_type" "RRE,VRR") | |
4781 | (set_attr "type" "ftruncdf") | |
4782 | (set_attr "cpu_facility" "*,vec")]) | |
9db1d521 | 4783 | |
f61a2c7d | 4784 | ; |
142cd70f | 4785 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
4786 | ; |
4787 | ||
142cd70f AK |
4788 | ; ldxbr, lexbr |
4789 | (define_insn "trunctf<mode>2" | |
4790 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
4791 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 4792 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
4793 | "TARGET_HARD_FLOAT" |
4794 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 4795 | [(set_attr "length" "6") |
9381e3f1 | 4796 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 4797 | |
609e7e80 AK |
4798 | ; |
4799 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
4800 | ; | |
4801 | ||
4802 | (define_insn "trunctddd2" | |
4803 | [(set (match_operand:DD 0 "register_operand" "=f") | |
bf259a77 AK |
4804 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
4805 | (clobber (match_scratch:TD 2 "=f"))] | |
fb068247 | 4806 | "TARGET_HARD_DFP" |
bf259a77 AK |
4807 | "ldxtr\t%2,0,%1,0\;ldr\t%0,%2" |
4808 | [(set_attr "length" "6") | |
9381e3f1 | 4809 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
4810 | |
4811 | (define_insn "truncddsd2" | |
4812 | [(set (match_operand:SD 0 "register_operand" "=f") | |
4813 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4814 | "TARGET_HARD_DFP" |
609e7e80 AK |
4815 | "ledtr\t%0,0,%1,0" |
4816 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 4817 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 4818 | |
feade5a8 AK |
4819 | (define_expand "trunctdsd2" |
4820 | [(parallel | |
4821 | [(set (match_dup 3) | |
4822 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) | |
4823 | (clobber (match_scratch:TD 2 ""))]) | |
4824 | (set (match_operand:SD 0 "register_operand" "") | |
4825 | (float_truncate:SD (match_dup 3)))] | |
4826 | "TARGET_HARD_DFP" | |
4827 | { | |
4828 | operands[3] = gen_reg_rtx (DDmode); | |
4829 | }) | |
4830 | ||
9db1d521 | 4831 | ; |
142cd70f | 4832 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
4833 | ; |
4834 | ||
6e5b5de8 AK |
4835 | (define_insn "*extendsfdf2_z13" |
4836 | [(set (match_operand:DF 0 "register_operand" "=f,f,v") | |
4837 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))] | |
4838 | "TARGET_Z13 && TARGET_HARD_FLOAT" | |
4839 | "@ | |
4840 | ldebr\t%0,%1 | |
4841 | ldeb\t%0,%1 | |
4842 | wldeb\t%v0,%v1" | |
4843 | [(set_attr "op_type" "RRE,RXE,VRR") | |
4844 | (set_attr "type" "fsimpdf, floaddf,fsimpdf")]) | |
4845 | ||
142cd70f | 4846 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
6e5b5de8 AK |
4847 | (define_insn "*extend<DSF:mode><BFP:mode>2" |
4848 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
142cd70f AK |
4849 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] |
4850 | "TARGET_HARD_FLOAT | |
6e5b5de8 AK |
4851 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode) |
4852 | && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)" | |
f61a2c7d | 4853 | "@ |
142cd70f AK |
4854 | l<BFP:xde><DSF:xde>br\t%0,%1 |
4855 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
6e5b5de8 AK |
4856 | [(set_attr "op_type" "RRE,RXE") |
4857 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) | |
4858 | ||
4859 | (define_expand "extend<DSF:mode><BFP:mode>2" | |
4860 | [(set (match_operand:BFP 0 "register_operand" "") | |
4861 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))] | |
4862 | "TARGET_HARD_FLOAT | |
4863 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)") | |
f61a2c7d | 4864 | |
609e7e80 AK |
4865 | ; |
4866 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
4867 | ; | |
4868 | ||
4869 | (define_insn "extendddtd2" | |
4870 | [(set (match_operand:TD 0 "register_operand" "=f") | |
4871 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 4872 | "TARGET_HARD_DFP" |
609e7e80 AK |
4873 | "lxdtr\t%0,%1,0" |
4874 | [(set_attr "op_type" "RRF") | |
4875 | (set_attr "type" "fsimptf")]) | |
4876 | ||
4877 | (define_insn "extendsddd2" | |
4878 | [(set (match_operand:DD 0 "register_operand" "=f") | |
4879 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 4880 | "TARGET_HARD_DFP" |
609e7e80 AK |
4881 | "ldetr\t%0,%1,0" |
4882 | [(set_attr "op_type" "RRF") | |
4883 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 4884 | |
feade5a8 AK |
4885 | (define_expand "extendsdtd2" |
4886 | [(set (match_dup 2) | |
4887 | (float_extend:DD (match_operand:SD 1 "register_operand" ""))) | |
4888 | (set (match_operand:TD 0 "register_operand" "") | |
4889 | (float_extend:TD (match_dup 2)))] | |
4890 | "TARGET_HARD_DFP" | |
4891 | { | |
4892 | operands[2] = gen_reg_rtx (DDmode); | |
4893 | }) | |
4894 | ||
d12a76f3 AK |
4895 | ; Binary Floating Point - load fp integer |
4896 | ||
4897 | ; Expanders for: floor, btrunc, round, ceil, and nearbyint | |
4898 | ; For all of them the inexact exceptions are suppressed. | |
4899 | ||
4900 | ; fiebra, fidbra, fixbra | |
4901 | (define_insn "<FPINT:fpint_name><BFP:mode>2" | |
4902 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
4903 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
4904 | FPINT))] | |
4905 | "TARGET_Z196" | |
4906 | "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
4907 | [(set_attr "op_type" "RRF") | |
4908 | (set_attr "type" "fsimp<BFP:mode>")]) | |
4909 | ||
4910 | ; rint is supposed to raise an inexact exception so we can use the | |
4911 | ; older instructions. | |
4912 | ||
4913 | ; fiebr, fidbr, fixbr | |
4914 | (define_insn "rint<BFP:mode>2" | |
4915 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
4916 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
4917 | UNSPEC_FPINT_RINT))] | |
4918 | "" | |
4919 | "fi<BFP:xde>br\t%0,0,%1" | |
4920 | [(set_attr "op_type" "RRF") | |
4921 | (set_attr "type" "fsimp<BFP:mode>")]) | |
4922 | ||
4923 | ||
4924 | ; Decimal Floating Point - load fp integer | |
4925 | ||
4926 | ; fidtr, fixtr | |
4927 | (define_insn "<FPINT:fpint_name><DFP:mode>2" | |
4928 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
4929 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
4930 | FPINT))] | |
4931 | "TARGET_HARD_DFP" | |
4932 | "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
4933 | [(set_attr "op_type" "RRF") | |
4934 | (set_attr "type" "fsimp<DFP:mode>")]) | |
4935 | ||
4936 | ; fidtr, fixtr | |
4937 | (define_insn "rint<DFP:mode>2" | |
4938 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
4939 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
4940 | UNSPEC_FPINT_RINT))] | |
4941 | "TARGET_HARD_DFP" | |
4942 | "fi<DFP:xde>tr\t%0,0,%1,0" | |
4943 | [(set_attr "op_type" "RRF") | |
4944 | (set_attr "type" "fsimp<DFP:mode>")]) | |
4945 | ||
4946 | ; | |
35dd9a0e AK |
4947 | ; Binary <-> Decimal floating point trunc patterns |
4948 | ; | |
4949 | ||
4950 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
4951 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 4952 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 4953 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
4954 | (clobber (reg:CC CC_REGNUM)) |
4955 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 4956 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4957 | "pfpo") |
4958 | ||
4959 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
4960 | [(set (reg:BFP FPR0_REGNUM) | |
2cf4c39e | 4961 | (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 4962 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
4963 | (clobber (reg:CC CC_REGNUM)) |
4964 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 4965 | "TARGET_HARD_DFP" |
35dd9a0e AK |
4966 | "pfpo") |
4967 | ||
4968 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 4969 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
4970 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
4971 | (parallel | |
4972 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 4973 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 4974 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
4975 | (clobber (reg:CC CC_REGNUM)) |
4976 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
4977 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
4978 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 4979 | "TARGET_HARD_DFP |
35dd9a0e AK |
4980 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
4981 | { | |
4982 | HOST_WIDE_INT flags; | |
4983 | ||
4984 | flags = (PFPO_CONVERT | | |
4985 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
4986 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
4987 | ||
4988 | operands[2] = GEN_INT (flags); | |
4989 | }) | |
4990 | ||
4991 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 4992 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
4993 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
4994 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
4995 | (parallel | |
2cf4c39e | 4996 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 4997 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
4998 | (clobber (reg:CC CC_REGNUM)) |
4999 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5000 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5001 | "TARGET_HARD_DFP |
35dd9a0e AK |
5002 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
5003 | { | |
5004 | HOST_WIDE_INT flags; | |
5005 | ||
5006 | flags = (PFPO_CONVERT | | |
5007 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5008 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5009 | ||
5010 | operands[2] = GEN_INT (flags); | |
5011 | }) | |
5012 | ||
5013 | ; | |
5014 | ; Binary <-> Decimal floating point extend patterns | |
5015 | ; | |
5016 | ||
5017 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5018 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5019 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5020 | (clobber (reg:CC CC_REGNUM)) |
5021 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5022 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5023 | "pfpo") |
5024 | ||
5025 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5026 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5027 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5028 | (clobber (reg:CC CC_REGNUM)) |
5029 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5030 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5031 | "pfpo") |
5032 | ||
5033 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5034 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5035 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5036 | (parallel | |
5037 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5038 | (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5039 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5040 | (clobber (reg:CC CC_REGNUM)) |
5041 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5042 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5043 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5044 | "TARGET_HARD_DFP |
35dd9a0e AK |
5045 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5046 | { | |
5047 | HOST_WIDE_INT flags; | |
5048 | ||
5049 | flags = (PFPO_CONVERT | | |
5050 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5051 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5052 | ||
5053 | operands[2] = GEN_INT (flags); | |
5054 | }) | |
5055 | ||
5056 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5057 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5058 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5059 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5060 | (parallel | |
2cf4c39e | 5061 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5062 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5063 | (clobber (reg:CC CC_REGNUM)) |
5064 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5065 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5066 | "TARGET_HARD_DFP |
35dd9a0e AK |
5067 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
5068 | { | |
5069 | HOST_WIDE_INT flags; | |
5070 | ||
5071 | flags = (PFPO_CONVERT | | |
5072 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5073 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5074 | ||
5075 | operands[2] = GEN_INT (flags); | |
5076 | }) | |
5077 | ||
5078 | ||
9db1d521 | 5079 | ;; |
fae778eb | 5080 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 5081 | ;; |
fae778eb | 5082 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
5083 | ; because of unpredictable Bits in Register for Halfword and Byte |
5084 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
5085 | ||
07893d4f UW |
5086 | ;; |
5087 | ;;- Add instructions. | |
5088 | ;; | |
5089 | ||
1c7b1b7e UW |
5090 | ; |
5091 | ; addti3 instruction pattern(s). | |
5092 | ; | |
5093 | ||
085261c8 AK |
5094 | (define_expand "addti3" |
5095 | [(parallel | |
5096 | [(set (match_operand:TI 0 "register_operand" "") | |
5097 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "") | |
5098 | (match_operand:TI 2 "general_operand" "") ) ) | |
5099 | (clobber (reg:CC CC_REGNUM))])] | |
5100 | "TARGET_ZARCH" | |
5101 | { | |
5102 | /* For z13 we have vaq which doesn't set CC. */ | |
5103 | if (TARGET_VX) | |
5104 | { | |
5105 | emit_insn (gen_rtx_SET (operands[0], | |
5106 | gen_rtx_PLUS (TImode, | |
5107 | copy_to_mode_reg (TImode, operands[1]), | |
5108 | copy_to_mode_reg (TImode, operands[2])))); | |
5109 | DONE; | |
5110 | } | |
5111 | }) | |
5112 | ||
5113 | (define_insn_and_split "*addti3" | |
5114 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
1c7b1b7e | 5115 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
085261c8 | 5116 | (match_operand:TI 2 "general_operand" "do") ) ) |
ae156f85 | 5117 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5118 | "TARGET_ZARCH" |
1c7b1b7e UW |
5119 | "#" |
5120 | "&& reload_completed" | |
5121 | [(parallel | |
ae156f85 | 5122 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
5123 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
5124 | (match_dup 7))) | |
5125 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
5126 | (parallel | |
a94a76a7 UW |
5127 | [(set (match_dup 3) (plus:DI |
5128 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5129 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5130 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
5131 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5132 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5133 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5134 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5135 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5136 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5137 | [(set_attr "op_type" "*") | |
5138 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 5139 | |
07893d4f UW |
5140 | ; |
5141 | ; adddi3 instruction pattern(s). | |
5142 | ; | |
5143 | ||
3298c037 AK |
5144 | (define_expand "adddi3" |
5145 | [(parallel | |
963fc8d0 | 5146 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
5147 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
5148 | (match_operand:DI 2 "general_operand" ""))) | |
5149 | (clobber (reg:CC CC_REGNUM))])] | |
5150 | "" | |
5151 | "") | |
5152 | ||
07893d4f UW |
5153 | (define_insn "*adddi3_sign" |
5154 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 5155 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 5156 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5157 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5158 | "TARGET_ZARCH" |
07893d4f | 5159 | "@ |
d40c829f UW |
5160 | agfr\t%0,%2 |
5161 | agf\t%0,%2" | |
65b1d8ea AK |
5162 | [(set_attr "op_type" "RRE,RXY") |
5163 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
07893d4f UW |
5164 | |
5165 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 5166 | [(set (reg CC_REGNUM) |
fb492564 | 5167 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
5168 | (match_operand:DI 1 "register_operand" "0,0")) |
5169 | (const_int 0))) | |
5170 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5171 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
9602b6a1 | 5172 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5173 | "@ |
d40c829f UW |
5174 | algfr\t%0,%2 |
5175 | algf\t%0,%2" | |
9381e3f1 WG |
5176 | [(set_attr "op_type" "RRE,RXY") |
5177 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5178 | |
5179 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 5180 | [(set (reg CC_REGNUM) |
fb492564 | 5181 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f UW |
5182 | (match_operand:DI 1 "register_operand" "0,0")) |
5183 | (const_int 0))) | |
5184 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5185 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5186 | "@ |
d40c829f UW |
5187 | algfr\t%0,%2 |
5188 | algf\t%0,%2" | |
9381e3f1 WG |
5189 | [(set_attr "op_type" "RRE,RXY") |
5190 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5191 | |
5192 | (define_insn "*adddi3_zero" | |
5193 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
fb492564 | 5194 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 5195 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5196 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5197 | "TARGET_ZARCH" |
07893d4f | 5198 | "@ |
d40c829f UW |
5199 | algfr\t%0,%2 |
5200 | algf\t%0,%2" | |
9381e3f1 WG |
5201 | [(set_attr "op_type" "RRE,RXY") |
5202 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 5203 | |
e69166de | 5204 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 5205 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
5206 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
5207 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5208 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5209 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
5210 | "#" |
5211 | "&& reload_completed" | |
5212 | [(parallel | |
ae156f85 | 5213 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
5214 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5215 | (match_dup 7))) | |
5216 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5217 | (parallel | |
a94a76a7 UW |
5218 | [(set (match_dup 3) (plus:SI |
5219 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5220 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5221 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
5222 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5223 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5224 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5225 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5226 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 5227 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 5228 | |
07893d4f | 5229 | (define_insn_and_split "*adddi3_31" |
963fc8d0 | 5230 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
96fd3851 | 5231 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 5232 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 5233 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 5234 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
5235 | "#" |
5236 | "&& reload_completed" | |
5237 | [(parallel | |
5238 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 5239 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5240 | (parallel |
ae156f85 | 5241 | [(set (reg:CCL1 CC_REGNUM) |
07893d4f UW |
5242 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5243 | (match_dup 7))) | |
5244 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5245 | (set (pc) | |
ae156f85 | 5246 | (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) |
07893d4f UW |
5247 | (pc) |
5248 | (label_ref (match_dup 9)))) | |
5249 | (parallel | |
5250 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
ae156f85 | 5251 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5252 | (match_dup 9)] |
97c6f7ad UW |
5253 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5254 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5255 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5256 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5257 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
5258 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 5259 | operands[9] = gen_label_rtx ();") |
9db1d521 | 5260 | |
3298c037 AK |
5261 | ; |
5262 | ; addsi3 instruction pattern(s). | |
5263 | ; | |
5264 | ||
5265 | (define_expand "addsi3" | |
07893d4f | 5266 | [(parallel |
963fc8d0 | 5267 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
5268 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
5269 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 5270 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5271 | "" |
07893d4f | 5272 | "") |
9db1d521 | 5273 | |
3298c037 AK |
5274 | (define_insn "*addsi3_sign" |
5275 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5276 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5277 | (match_operand:SI 1 "register_operand" "0,0"))) | |
5278 | (clobber (reg:CC CC_REGNUM))] | |
5279 | "" | |
5280 | "@ | |
5281 | ah\t%0,%2 | |
5282 | ahy\t%0,%2" | |
65b1d8ea AK |
5283 | [(set_attr "op_type" "RX,RXY") |
5284 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
3298c037 | 5285 | |
9db1d521 | 5286 | ; |
3298c037 | 5287 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 5288 | ; |
9db1d521 | 5289 | |
65b1d8ea | 5290 | ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 5291 | (define_insn "*add<mode>3" |
65b1d8ea AK |
5292 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS") |
5293 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0") | |
5294 | (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) ) | |
3298c037 AK |
5295 | (clobber (reg:CC CC_REGNUM))] |
5296 | "" | |
ec24698e | 5297 | "@ |
3298c037 | 5298 | a<g>r\t%0,%2 |
65b1d8ea | 5299 | a<g>rk\t%0,%1,%2 |
3298c037 | 5300 | a<g>hi\t%0,%h2 |
65b1d8ea | 5301 | a<g>hik\t%0,%1,%h2 |
3298c037 AK |
5302 | al<g>fi\t%0,%2 |
5303 | sl<g>fi\t%0,%n2 | |
5304 | a<g>\t%0,%2 | |
963fc8d0 AK |
5305 | a<y>\t%0,%2 |
5306 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
5307 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") |
5308 | (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10") | |
5309 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, | |
5310 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
0a3bdf9d | 5311 | |
65b1d8ea | 5312 | ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik |
3298c037 | 5313 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 5314 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5315 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5316 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5317 | (match_dup 1))) |
65b1d8ea | 5318 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") |
3298c037 | 5319 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5320 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5321 | "@ |
3298c037 | 5322 | al<g>r\t%0,%2 |
65b1d8ea | 5323 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5324 | al<g>fi\t%0,%2 |
5325 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5326 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5327 | al<g>\t%0,%2 |
963fc8d0 AK |
5328 | al<y>\t%0,%2 |
5329 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
5330 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
5331 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
5332 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, | |
5333 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5334 | |
65b1d8ea | 5335 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5336 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 5337 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5338 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5339 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5340 | (match_dup 1))) |
65b1d8ea | 5341 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5342 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5343 | "@ |
3298c037 | 5344 | al<g>r\t%0,%2 |
65b1d8ea | 5345 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5346 | al<g>\t%0,%2 |
5347 | al<y>\t%0,%2" | |
65b1d8ea AK |
5348 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5349 | (set_attr "cpu_facility" "*,z196,*,*") | |
5350 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5351 | |
65b1d8ea | 5352 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5353 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 5354 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5355 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") |
5356 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) | |
07893d4f | 5357 | (match_dup 2))) |
65b1d8ea | 5358 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") |
3298c037 | 5359 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5360 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5361 | "@ |
3298c037 | 5362 | al<g>r\t%0,%2 |
65b1d8ea | 5363 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5364 | al<g>fi\t%0,%2 |
5365 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5366 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5367 | al<g>\t%0,%2 |
963fc8d0 AK |
5368 | al<y>\t%0,%2 |
5369 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
5370 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
5371 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
5372 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, | |
5373 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5374 | |
65b1d8ea | 5375 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5376 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 5377 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5378 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5379 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5380 | (match_dup 2))) |
65b1d8ea | 5381 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5382 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5383 | "@ |
3298c037 | 5384 | al<g>r\t%0,%2 |
65b1d8ea | 5385 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5386 | al<g>\t%0,%2 |
5387 | al<y>\t%0,%2" | |
65b1d8ea AK |
5388 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5389 | (set_attr "cpu_facility" "*,z196,*,*") | |
5390 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5391 | |
65b1d8ea | 5392 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5393 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5394 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5395 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") |
5396 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) | |
9db1d521 | 5397 | (const_int 0))) |
65b1d8ea | 5398 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") |
3298c037 | 5399 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5400 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5401 | "@ |
3298c037 | 5402 | al<g>r\t%0,%2 |
65b1d8ea | 5403 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5404 | al<g>fi\t%0,%2 |
5405 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5406 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5407 | al<g>\t%0,%2 |
963fc8d0 AK |
5408 | al<y>\t%0,%2 |
5409 | al<g>si\t%0,%c2" | |
65b1d8ea AK |
5410 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
5411 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") | |
5412 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, | |
5413 | *,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5414 | |
65b1d8ea | 5415 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5416 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5417 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5418 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5419 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5420 | (const_int 0))) |
65b1d8ea | 5421 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5422 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5423 | "@ |
3298c037 | 5424 | al<g>r\t%0,%2 |
65b1d8ea | 5425 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5426 | al<g>\t%0,%2 |
5427 | al<y>\t%0,%2" | |
65b1d8ea AK |
5428 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5429 | (set_attr "cpu_facility" "*,z196,*,*") | |
5430 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5431 | |
65b1d8ea | 5432 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5433 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 5434 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5435 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5436 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) | |
5437 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
3298c037 | 5438 | "s390_match_ccmode(insn, CCLmode)" |
d3632d41 | 5439 | "@ |
3298c037 | 5440 | al<g>r\t%0,%2 |
65b1d8ea | 5441 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5442 | al<g>\t%0,%2 |
5443 | al<y>\t%0,%2" | |
65b1d8ea AK |
5444 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5445 | (set_attr "cpu_facility" "*,z196,*,*") | |
5446 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5447 | |
963fc8d0 | 5448 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
5449 | (define_insn "*add<mode>3_imm_cc" |
5450 | [(set (reg CC_REGNUM) | |
65b1d8ea AK |
5451 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") |
5452 | (match_operand:GPR 2 "const_int_operand" " K, K,Os, C")) | |
3298c037 | 5453 | (const_int 0))) |
65b1d8ea | 5454 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS") |
3298c037 AK |
5455 | (plus:GPR (match_dup 1) (match_dup 2)))] |
5456 | "s390_match_ccmode (insn, CCAmode) | |
5457 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
2542ef05 RH |
5458 | || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
5459 | /* Avoid INT32_MIN on 32 bit. */ | |
5460 | && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" | |
9db1d521 | 5461 | "@ |
3298c037 | 5462 | a<g>hi\t%0,%h2 |
65b1d8ea | 5463 | a<g>hik\t%0,%1,%h2 |
963fc8d0 AK |
5464 | a<g>fi\t%0,%2 |
5465 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
5466 | [(set_attr "op_type" "RI,RIE,RIL,SIY") |
5467 | (set_attr "cpu_facility" "*,z196,extimm,z10") | |
5468 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5469 | |
9db1d521 | 5470 | ; |
609e7e80 | 5471 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5472 | ; |
5473 | ||
609e7e80 | 5474 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
6e5b5de8 | 5475 | ; FIXME: wfadb does not clobber cc |
142cd70f | 5476 | (define_insn "add<mode>3" |
6e5b5de8 AK |
5477 | [(set (match_operand:FP 0 "register_operand" "=f, f,<vf>") |
5478 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>, 0,<v0>") | |
5479 | (match_operand:FP 2 "general_operand" "f,<Rf>,<vf>"))) | |
ae156f85 | 5480 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5481 | "TARGET_HARD_FLOAT" |
9db1d521 | 5482 | "@ |
609e7e80 | 5483 | a<xde><bt>r\t%0,<op1>%2 |
6e5b5de8 AK |
5484 | a<xde>b\t%0,%2 |
5485 | wfadb\t%v0,%v1,%v2" | |
5486 | [(set_attr "op_type" "<RRer>,RXE,VRR") | |
5487 | (set_attr "type" "fsimp<mode>") | |
5488 | (set_attr "cpu_facility" "*,*,vec")]) | |
9db1d521 | 5489 | |
609e7e80 | 5490 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5491 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5492 | [(set (reg CC_REGNUM) |
609e7e80 AK |
5493 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") |
5494 | (match_operand:FP 2 "general_operand" " f,<Rf>")) | |
5495 | (match_operand:FP 3 "const0_operand" ""))) | |
5496 | (set (match_operand:FP 0 "register_operand" "=f,f") | |
5497 | (plus:FP (match_dup 1) (match_dup 2)))] | |
142cd70f | 5498 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5499 | "@ |
609e7e80 | 5500 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5501 | a<xde>b\t%0,%2" |
609e7e80 | 5502 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5503 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 5504 | |
609e7e80 | 5505 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5506 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5507 | [(set (reg CC_REGNUM) |
609e7e80 AK |
5508 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") |
5509 | (match_operand:FP 2 "general_operand" " f,<Rf>")) | |
5510 | (match_operand:FP 3 "const0_operand" ""))) | |
5511 | (clobber (match_scratch:FP 0 "=f,f"))] | |
142cd70f | 5512 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5513 | "@ |
609e7e80 | 5514 | a<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5515 | a<xde>b\t%0,%2" |
609e7e80 | 5516 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5517 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 5518 | |
72a4ddf2 AK |
5519 | ; |
5520 | ; Pointer add instruction patterns | |
5521 | ; | |
5522 | ||
5523 | ; This will match "*la_64" | |
5524 | (define_expand "addptrdi3" | |
5525 | [(set (match_operand:DI 0 "register_operand" "") | |
5526 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
5527 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
5528 | "TARGET_64BIT" | |
5529 | { | |
72a4ddf2 AK |
5530 | if (GET_CODE (operands[2]) == CONST_INT) |
5531 | { | |
357ddc7d TV |
5532 | HOST_WIDE_INT c = INTVAL (operands[2]); |
5533 | ||
72a4ddf2 AK |
5534 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
5535 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
5536 | { | |
5537 | operands[2] = force_const_mem (DImode, operands[2]); | |
5538 | operands[2] = force_reg (DImode, operands[2]); | |
5539 | } | |
5540 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
5541 | operands[2] = force_reg (DImode, operands[2]); | |
5542 | } | |
5543 | }) | |
5544 | ||
5545 | ; For 31 bit we have to prevent the generated pattern from matching | |
5546 | ; normal ADDs since la only does a 31 bit add. This is supposed to | |
5547 | ; match "force_la_31". | |
5548 | (define_expand "addptrsi3" | |
5549 | [(parallel | |
5550 | [(set (match_operand:SI 0 "register_operand" "") | |
5551 | (plus:SI (match_operand:SI 1 "register_operand" "") | |
5552 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
5553 | (use (const_int 0))])] | |
5554 | "!TARGET_64BIT" | |
5555 | { | |
72a4ddf2 AK |
5556 | if (GET_CODE (operands[2]) == CONST_INT) |
5557 | { | |
357ddc7d TV |
5558 | HOST_WIDE_INT c = INTVAL (operands[2]); |
5559 | ||
72a4ddf2 AK |
5560 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
5561 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
5562 | { | |
5563 | operands[2] = force_const_mem (SImode, operands[2]); | |
5564 | operands[2] = force_reg (SImode, operands[2]); | |
5565 | } | |
5566 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
5567 | operands[2] = force_reg (SImode, operands[2]); | |
5568 | } | |
5569 | }) | |
9db1d521 HP |
5570 | |
5571 | ;; | |
5572 | ;;- Subtract instructions. | |
5573 | ;; | |
5574 | ||
1c7b1b7e UW |
5575 | ; |
5576 | ; subti3 instruction pattern(s). | |
5577 | ; | |
5578 | ||
085261c8 AK |
5579 | (define_expand "subti3" |
5580 | [(parallel | |
5581 | [(set (match_operand:TI 0 "register_operand" "") | |
5582 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
5583 | (match_operand:TI 2 "general_operand" "") ) ) | |
5584 | (clobber (reg:CC CC_REGNUM))])] | |
5585 | "TARGET_ZARCH" | |
5586 | { | |
5587 | /* For z13 we have vaq which doesn't set CC. */ | |
5588 | if (TARGET_VX) | |
5589 | { | |
5590 | emit_insn (gen_rtx_SET (operands[0], | |
5591 | gen_rtx_MINUS (TImode, | |
5592 | operands[1], | |
5593 | copy_to_mode_reg (TImode, operands[2])))); | |
5594 | DONE; | |
5595 | } | |
5596 | }) | |
5597 | ||
5598 | (define_insn_and_split "*subti3" | |
5599 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
5600 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
5601 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 5602 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5603 | "TARGET_ZARCH" |
1c7b1b7e UW |
5604 | "#" |
5605 | "&& reload_completed" | |
5606 | [(parallel | |
ae156f85 | 5607 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
5608 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
5609 | (match_dup 7))) | |
5610 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
5611 | (parallel | |
5612 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
5613 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
5614 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
5615 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5616 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5617 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5618 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5619 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5620 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5621 | [(set_attr "op_type" "*") | |
5622 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 5623 | |
9db1d521 HP |
5624 | ; |
5625 | ; subdi3 instruction pattern(s). | |
5626 | ; | |
5627 | ||
3298c037 AK |
5628 | (define_expand "subdi3" |
5629 | [(parallel | |
5630 | [(set (match_operand:DI 0 "register_operand" "") | |
5631 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
5632 | (match_operand:DI 2 "general_operand" ""))) | |
5633 | (clobber (reg:CC CC_REGNUM))])] | |
5634 | "" | |
5635 | "") | |
5636 | ||
07893d4f UW |
5637 | (define_insn "*subdi3_sign" |
5638 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5639 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 5640 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 5641 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5642 | "TARGET_ZARCH" |
07893d4f | 5643 | "@ |
d40c829f UW |
5644 | sgfr\t%0,%2 |
5645 | sgf\t%0,%2" | |
9381e3f1 | 5646 | [(set_attr "op_type" "RRE,RXY") |
65b1d8ea AK |
5647 | (set_attr "z10prop" "z10_c,*") |
5648 | (set_attr "z196prop" "z196_cracked")]) | |
07893d4f UW |
5649 | |
5650 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 5651 | [(set (reg CC_REGNUM) |
07893d4f | 5652 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 5653 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
5654 | (const_int 0))) |
5655 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5656 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
9602b6a1 | 5657 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5658 | "@ |
d40c829f UW |
5659 | slgfr\t%0,%2 |
5660 | slgf\t%0,%2" | |
9381e3f1 WG |
5661 | [(set_attr "op_type" "RRE,RXY") |
5662 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
5663 | |
5664 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 5665 | [(set (reg CC_REGNUM) |
07893d4f | 5666 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 5667 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) |
07893d4f UW |
5668 | (const_int 0))) |
5669 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5670 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5671 | "@ |
d40c829f UW |
5672 | slgfr\t%0,%2 |
5673 | slgf\t%0,%2" | |
9381e3f1 WG |
5674 | [(set_attr "op_type" "RRE,RXY") |
5675 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
5676 | |
5677 | (define_insn "*subdi3_zero" | |
5678 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5679 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
fb492564 | 5680 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) |
ae156f85 | 5681 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5682 | "TARGET_ZARCH" |
07893d4f | 5683 | "@ |
d40c829f UW |
5684 | slgfr\t%0,%2 |
5685 | slgf\t%0,%2" | |
9381e3f1 WG |
5686 | [(set_attr "op_type" "RRE,RXY") |
5687 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 5688 | |
e69166de UW |
5689 | (define_insn_and_split "*subdi3_31z" |
5690 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
5691 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
5692 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5693 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5694 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
5695 | "#" |
5696 | "&& reload_completed" | |
5697 | [(parallel | |
ae156f85 | 5698 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
5699 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
5700 | (match_dup 7))) | |
5701 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
5702 | (parallel | |
5703 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
5704 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
5705 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
5706 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5707 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5708 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5709 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5710 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 5711 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 5712 | |
07893d4f UW |
5713 | (define_insn_and_split "*subdi3_31" |
5714 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
5715 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 5716 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 5717 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 5718 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
5719 | "#" |
5720 | "&& reload_completed" | |
5721 | [(parallel | |
5722 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 5723 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5724 | (parallel |
ae156f85 | 5725 | [(set (reg:CCL2 CC_REGNUM) |
07893d4f UW |
5726 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
5727 | (match_dup 7))) | |
5728 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
5729 | (set (pc) | |
ae156f85 | 5730 | (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) |
07893d4f UW |
5731 | (pc) |
5732 | (label_ref (match_dup 9)))) | |
5733 | (parallel | |
5734 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
ae156f85 | 5735 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5736 | (match_dup 9)] |
97c6f7ad UW |
5737 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5738 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5739 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5740 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5741 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
5742 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 5743 | operands[9] = gen_label_rtx ();") |
07893d4f | 5744 | |
3298c037 AK |
5745 | ; |
5746 | ; subsi3 instruction pattern(s). | |
5747 | ; | |
5748 | ||
5749 | (define_expand "subsi3" | |
07893d4f | 5750 | [(parallel |
3298c037 AK |
5751 | [(set (match_operand:SI 0 "register_operand" "") |
5752 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
5753 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 5754 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5755 | "" |
07893d4f | 5756 | "") |
9db1d521 | 5757 | |
3298c037 AK |
5758 | (define_insn "*subsi3_sign" |
5759 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5760 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
5761 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
5762 | (clobber (reg:CC CC_REGNUM))] | |
5763 | "" | |
5764 | "@ | |
5765 | sh\t%0,%2 | |
5766 | shy\t%0,%2" | |
65b1d8ea AK |
5767 | [(set_attr "op_type" "RX,RXY") |
5768 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
3298c037 | 5769 | |
9db1d521 | 5770 | ; |
3298c037 | 5771 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
5772 | ; |
5773 | ||
65b1d8ea | 5774 | ; sr, s, sy, sgr, sg, srk, sgrk |
3298c037 | 5775 | (define_insn "*sub<mode>3" |
65b1d8ea AK |
5776 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
5777 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") | |
5778 | (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) | |
3298c037 AK |
5779 | (clobber (reg:CC CC_REGNUM))] |
5780 | "" | |
5781 | "@ | |
5782 | s<g>r\t%0,%2 | |
65b1d8ea | 5783 | s<g>rk\t%0,%1,%2 |
3298c037 AK |
5784 | s<g>\t%0,%2 |
5785 | s<y>\t%0,%2" | |
65b1d8ea AK |
5786 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5787 | (set_attr "cpu_facility" "*,z196,*,*") | |
5788 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
3298c037 | 5789 | |
65b1d8ea | 5790 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5791 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 5792 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5793 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5794 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5795 | (match_dup 1))) |
65b1d8ea | 5796 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 5797 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 5798 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 5799 | "@ |
3298c037 | 5800 | sl<g>r\t%0,%2 |
65b1d8ea | 5801 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5802 | sl<g>\t%0,%2 |
5803 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5804 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5805 | (set_attr "cpu_facility" "*,z196,*,*") | |
5806 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5807 | |
65b1d8ea | 5808 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5809 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 5810 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5811 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5812 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5813 | (match_dup 1))) |
65b1d8ea | 5814 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 5815 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 5816 | "@ |
3298c037 | 5817 | sl<g>r\t%0,%2 |
65b1d8ea | 5818 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5819 | sl<g>\t%0,%2 |
5820 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5821 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5822 | (set_attr "cpu_facility" "*,z196,*,*") | |
5823 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5824 | |
65b1d8ea | 5825 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5826 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 5827 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5828 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5829 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5830 | (const_int 0))) |
65b1d8ea | 5831 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 5832 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 5833 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5834 | "@ |
3298c037 | 5835 | sl<g>r\t%0,%2 |
65b1d8ea | 5836 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5837 | sl<g>\t%0,%2 |
5838 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5839 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5840 | (set_attr "cpu_facility" "*,z196,*,*") | |
5841 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5842 | |
65b1d8ea | 5843 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5844 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 5845 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5846 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5847 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
5848 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
3298c037 | 5849 | (minus:GPR (match_dup 1) (match_dup 2)))] |
5d880bd2 UW |
5850 | "s390_match_ccmode (insn, CCL3mode)" |
5851 | "@ | |
3298c037 | 5852 | sl<g>r\t%0,%2 |
65b1d8ea | 5853 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5854 | sl<g>\t%0,%2 |
5855 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5856 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5857 | (set_attr "cpu_facility" "*,z196,*,*") | |
5858 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
5d880bd2 | 5859 | |
65b1d8ea | 5860 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5861 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 5862 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5863 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5864 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5865 | (const_int 0))) |
65b1d8ea | 5866 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 5867 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5868 | "@ |
3298c037 | 5869 | sl<g>r\t%0,%2 |
65b1d8ea | 5870 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5871 | sl<g>\t%0,%2 |
5872 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5873 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5874 | (set_attr "cpu_facility" "*,z196,*,*") | |
5875 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9381e3f1 | 5876 | |
9db1d521 | 5877 | |
65b1d8ea | 5878 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 5879 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 5880 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5881 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
5882 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
5883 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
5d880bd2 UW |
5884 | "s390_match_ccmode (insn, CCL3mode)" |
5885 | "@ | |
3298c037 | 5886 | sl<g>r\t%0,%2 |
65b1d8ea | 5887 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
5888 | sl<g>\t%0,%2 |
5889 | sl<y>\t%0,%2" | |
65b1d8ea AK |
5890 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
5891 | (set_attr "cpu_facility" "*,z196,*,*") | |
5892 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) | |
9381e3f1 | 5893 | |
9db1d521 HP |
5894 | |
5895 | ; | |
609e7e80 | 5896 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5897 | ; |
5898 | ||
d46f24b6 | 5899 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 5900 | (define_insn "sub<mode>3" |
6e5b5de8 AK |
5901 | [(set (match_operand:FP 0 "register_operand" "=f, f,<vf>") |
5902 | (minus:FP (match_operand:FP 1 "register_operand" "<f0>, 0,<v0>") | |
5903 | (match_operand:FP 2 "general_operand" "f,<Rf>,<vf>"))) | |
ae156f85 | 5904 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5905 | "TARGET_HARD_FLOAT" |
9db1d521 | 5906 | "@ |
609e7e80 | 5907 | s<xde><bt>r\t%0,<op1>%2 |
6e5b5de8 AK |
5908 | s<xde>b\t%0,%2 |
5909 | wfsdb\t%v0,%v1,%v2" | |
5910 | [(set_attr "op_type" "<RRer>,RXE,VRR") | |
5911 | (set_attr "type" "fsimp<mode>") | |
5912 | (set_attr "cpu_facility" "*,*,vec")]) | |
9db1d521 | 5913 | |
d46f24b6 | 5914 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 5915 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 5916 | [(set (reg CC_REGNUM) |
609e7e80 | 5917 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") |
142cd70f | 5918 | (match_operand:FP 2 "general_operand" "f,<Rf>")) |
609e7e80 AK |
5919 | (match_operand:FP 3 "const0_operand" ""))) |
5920 | (set (match_operand:FP 0 "register_operand" "=f,f") | |
5921 | (minus:FP (match_dup 1) (match_dup 2)))] | |
142cd70f | 5922 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5923 | "@ |
609e7e80 | 5924 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5925 | s<xde>b\t%0,%2" |
609e7e80 | 5926 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5927 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 5928 | |
d46f24b6 | 5929 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 5930 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 5931 | [(set (reg CC_REGNUM) |
609e7e80 AK |
5932 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") |
5933 | (match_operand:FP 2 "general_operand" "f,<Rf>")) | |
5934 | (match_operand:FP 3 "const0_operand" ""))) | |
5935 | (clobber (match_scratch:FP 0 "=f,f"))] | |
142cd70f | 5936 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5937 | "@ |
609e7e80 | 5938 | s<xde><bt>r\t%0,<op1>%2 |
f61a2c7d | 5939 | s<xde>b\t%0,%2" |
609e7e80 | 5940 | [(set_attr "op_type" "<RRer>,RXE") |
9381e3f1 | 5941 | (set_attr "type" "fsimp<mode>")]) |
3ef093a8 | 5942 | |
9db1d521 | 5943 | |
e69166de UW |
5944 | ;; |
5945 | ;;- Conditional add/subtract instructions. | |
5946 | ;; | |
5947 | ||
5948 | ; | |
9a91a21f | 5949 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
5950 | ; |
5951 | ||
a996720c UW |
5952 | ; the following 4 patterns are used when the result of an add with |
5953 | ; carry is checked for an overflow condition | |
5954 | ||
5955 | ; op1 + op2 + c < op1 | |
5956 | ||
5957 | ; alcr, alc, alcgr, alcg | |
5958 | (define_insn "*add<mode>3_alc_carry1_cc" | |
5959 | [(set (reg CC_REGNUM) | |
5960 | (compare | |
5961 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5962 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5963 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5964 | (match_dup 1))) |
5965 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
5966 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
5967 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5968 | "@ | |
5969 | alc<g>r\t%0,%2 | |
5970 | alc<g>\t%0,%2" | |
65b1d8ea AK |
5971 | [(set_attr "op_type" "RRE,RXY") |
5972 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
5973 | |
5974 | ; alcr, alc, alcgr, alcg | |
5975 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
5976 | [(set (reg CC_REGNUM) | |
5977 | (compare | |
5978 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5979 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5980 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5981 | (match_dup 1))) |
5982 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
5983 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
5984 | "@ | |
5985 | alc<g>r\t%0,%2 | |
5986 | alc<g>\t%0,%2" | |
65b1d8ea AK |
5987 | [(set_attr "op_type" "RRE,RXY") |
5988 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
5989 | |
5990 | ; op1 + op2 + c < op2 | |
5991 | ||
5992 | ; alcr, alc, alcgr, alcg | |
5993 | (define_insn "*add<mode>3_alc_carry2_cc" | |
5994 | [(set (reg CC_REGNUM) | |
5995 | (compare | |
5996 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
5997 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 5998 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
5999 | (match_dup 2))) |
6000 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6001 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
6002 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6003 | "@ | |
6004 | alc<g>r\t%0,%2 | |
6005 | alc<g>\t%0,%2" | |
6006 | [(set_attr "op_type" "RRE,RXY")]) | |
6007 | ||
6008 | ; alcr, alc, alcgr, alcg | |
6009 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
6010 | [(set (reg CC_REGNUM) | |
6011 | (compare | |
6012 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6013 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 6014 | (match_operand:GPR 2 "general_operand" "d,RT")) |
a996720c UW |
6015 | (match_dup 2))) |
6016 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
6017 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6018 | "@ | |
6019 | alc<g>r\t%0,%2 | |
6020 | alc<g>\t%0,%2" | |
6021 | [(set_attr "op_type" "RRE,RXY")]) | |
6022 | ||
43a09b63 | 6023 | ; alcr, alc, alcgr, alcg |
9a91a21f | 6024 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 6025 | [(set (reg CC_REGNUM) |
e69166de | 6026 | (compare |
a94a76a7 UW |
6027 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6028 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 6029 | (match_operand:GPR 2 "general_operand" "d,RT")) |
e69166de | 6030 | (const_int 0))) |
9a91a21f | 6031 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 6032 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
2f7e5a0d | 6033 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 6034 | "@ |
9a91a21f AS |
6035 | alc<g>r\t%0,%2 |
6036 | alc<g>\t%0,%2" | |
e69166de UW |
6037 | [(set_attr "op_type" "RRE,RXY")]) |
6038 | ||
43a09b63 | 6039 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
6040 | (define_insn "*add<mode>3_alc" |
6041 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
6042 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6043 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
fb492564 | 6044 | (match_operand:GPR 2 "general_operand" "d,RT"))) |
ae156f85 | 6045 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 6046 | "TARGET_CPU_ZARCH" |
e69166de | 6047 | "@ |
9a91a21f AS |
6048 | alc<g>r\t%0,%2 |
6049 | alc<g>\t%0,%2" | |
e69166de UW |
6050 | [(set_attr "op_type" "RRE,RXY")]) |
6051 | ||
43a09b63 | 6052 | ; slbr, slb, slbgr, slbg |
9a91a21f | 6053 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 6054 | [(set (reg CC_REGNUM) |
e69166de | 6055 | (compare |
9a91a21f | 6056 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
fb492564 | 6057 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 6058 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 6059 | (const_int 0))) |
9a91a21f AS |
6060 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
6061 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 6062 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 6063 | "@ |
9a91a21f AS |
6064 | slb<g>r\t%0,%2 |
6065 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6066 | [(set_attr "op_type" "RRE,RXY") |
6067 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6068 | |
43a09b63 | 6069 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
6070 | (define_insn "*sub<mode>3_slb" |
6071 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
6072 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
fb492564 | 6073 | (match_operand:GPR 2 "general_operand" "d,RT")) |
9a91a21f | 6074 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 6075 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 6076 | "TARGET_CPU_ZARCH" |
e69166de | 6077 | "@ |
9a91a21f AS |
6078 | slb<g>r\t%0,%2 |
6079 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6080 | [(set_attr "op_type" "RRE,RXY") |
6081 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6082 | |
9a91a21f AS |
6083 | (define_expand "add<mode>cc" |
6084 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 6085 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
6086 | (match_operand:GPR 2 "register_operand" "") |
6087 | (match_operand:GPR 3 "const_int_operand" "")] | |
5d880bd2 | 6088 | "TARGET_CPU_ZARCH" |
9381e3f1 | 6089 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
f90b7a5a | 6090 | XEXP (operands[1], 0), XEXP (operands[1], 1), |
9381e3f1 | 6091 | operands[0], operands[2], |
5d880bd2 UW |
6092 | operands[3])) FAIL; DONE;") |
6093 | ||
6094 | ; | |
6095 | ; scond instruction pattern(s). | |
6096 | ; | |
6097 | ||
9a91a21f AS |
6098 | (define_insn_and_split "*scond<mode>" |
6099 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6100 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 6101 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
6102 | "TARGET_CPU_ZARCH" |
6103 | "#" | |
6104 | "&& reload_completed" | |
6105 | [(set (match_dup 0) (const_int 0)) | |
6106 | (parallel | |
a94a76a7 UW |
6107 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
6108 | (match_dup 0))) | |
ae156f85 | 6109 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6110 | "") |
5d880bd2 | 6111 | |
9a91a21f AS |
6112 | (define_insn_and_split "*scond<mode>_neg" |
6113 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6114 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 6115 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
6116 | "TARGET_CPU_ZARCH" |
6117 | "#" | |
6118 | "&& reload_completed" | |
6119 | [(set (match_dup 0) (const_int 0)) | |
6120 | (parallel | |
9a91a21f AS |
6121 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
6122 | (match_dup 1))) | |
ae156f85 | 6123 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 6124 | (parallel |
9a91a21f | 6125 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 6126 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6127 | "") |
5d880bd2 | 6128 | |
5d880bd2 | 6129 | |
f90b7a5a | 6130 | (define_expand "cstore<mode>4" |
9a91a21f | 6131 | [(set (match_operand:SI 0 "register_operand" "") |
f90b7a5a PB |
6132 | (match_operator:SI 1 "s390_scond_operator" |
6133 | [(match_operand:GPR 2 "register_operand" "") | |
6134 | (match_operand:GPR 3 "general_operand" "")]))] | |
5d880bd2 | 6135 | "TARGET_CPU_ZARCH" |
f90b7a5a | 6136 | "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], |
5d880bd2 UW |
6137 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
6138 | ||
f90b7a5a | 6139 | (define_expand "cstorecc4" |
69950452 | 6140 | [(parallel |
f90b7a5a PB |
6141 | [(set (match_operand:SI 0 "register_operand" "") |
6142 | (match_operator:SI 1 "s390_eqne_operator" | |
6143 | [(match_operand:CCZ1 2 "register_operand") | |
6144 | (match_operand 3 "const0_operand")])) | |
69950452 AS |
6145 | (clobber (reg:CC CC_REGNUM))])] |
6146 | "" | |
f90b7a5a PB |
6147 | "emit_insn (gen_sne (operands[0], operands[2])); |
6148 | if (GET_CODE (operands[1]) == EQ) | |
6149 | emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); | |
6150 | DONE;") | |
69950452 | 6151 | |
f90b7a5a | 6152 | (define_insn_and_split "sne" |
69950452 | 6153 | [(set (match_operand:SI 0 "register_operand" "=d") |
9381e3f1 | 6154 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
6155 | (const_int 0))) |
6156 | (clobber (reg:CC CC_REGNUM))] | |
6157 | "" | |
6158 | "#" | |
6159 | "reload_completed" | |
6160 | [(parallel | |
6161 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
6162 | (clobber (reg:CC CC_REGNUM))])]) | |
6163 | ||
e69166de | 6164 | |
65b1d8ea AK |
6165 | ;; |
6166 | ;; - Conditional move instructions (introduced with z196) | |
6167 | ;; | |
6168 | ||
6169 | (define_expand "mov<mode>cc" | |
6170 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
6171 | (if_then_else:GPR (match_operand 1 "comparison_operator" "") | |
6172 | (match_operand:GPR 2 "nonimmediate_operand" "") | |
6173 | (match_operand:GPR 3 "nonimmediate_operand" "")))] | |
6174 | "TARGET_Z196" | |
7477de01 AK |
6175 | { |
6176 | /* Emit the comparison insn in case we do not already have a comparison result. */ | |
6177 | if (!s390_comparison (operands[1], VOIDmode)) | |
6178 | operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
6179 | XEXP (operands[1], 0), | |
6180 | XEXP (operands[1], 1)); | |
6181 | }) | |
65b1d8ea | 6182 | |
27037b5f | 6183 | ; locr, loc, stoc, locgr, locg, stocg |
65b1d8ea AK |
6184 | (define_insn_and_split "*mov<mode>cc" |
6185 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d") | |
6186 | (if_then_else:GPR | |
6187 | (match_operator 1 "s390_comparison" | |
6188 | [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c") | |
5a3fe9b6 | 6189 | (match_operand 5 "const_int_operand" "")]) |
65b1d8ea AK |
6190 | (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS") |
6191 | (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))] | |
6192 | "TARGET_Z196" | |
6193 | "@ | |
6194 | loc<g>r%C1\t%0,%3 | |
6195 | loc<g>r%D1\t%0,%4 | |
a6510374 AK |
6196 | loc<g>%C1\t%0,%3 |
6197 | loc<g>%D1\t%0,%4 | |
6198 | stoc<g>%C1\t%3,%0 | |
6199 | stoc<g>%D1\t%4,%0 | |
65b1d8ea AK |
6200 | #" |
6201 | "&& reload_completed | |
6202 | && MEM_P (operands[3]) && MEM_P (operands[4])" | |
6203 | [(set (match_dup 0) | |
6204 | (if_then_else:GPR | |
6205 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
6206 | (match_dup 3) | |
6207 | (match_dup 0))) | |
6208 | (set (match_dup 0) | |
6209 | (if_then_else:GPR | |
6210 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
6211 | (match_dup 0) | |
6212 | (match_dup 4)))] | |
6213 | "" | |
6214 | [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")]) | |
6215 | ||
9db1d521 HP |
6216 | ;; |
6217 | ;;- Multiply instructions. | |
6218 | ;; | |
6219 | ||
4023fb28 UW |
6220 | ; |
6221 | ; muldi3 instruction pattern(s). | |
6222 | ; | |
9db1d521 | 6223 | |
07893d4f UW |
6224 | (define_insn "*muldi3_sign" |
6225 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
963fc8d0 | 6226 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) |
07893d4f | 6227 | (match_operand:DI 1 "register_operand" "0,0")))] |
9602b6a1 | 6228 | "TARGET_ZARCH" |
07893d4f | 6229 | "@ |
d40c829f UW |
6230 | msgfr\t%0,%2 |
6231 | msgf\t%0,%2" | |
963fc8d0 AK |
6232 | [(set_attr "op_type" "RRE,RXY") |
6233 | (set_attr "type" "imuldi")]) | |
07893d4f | 6234 | |
4023fb28 | 6235 | (define_insn "muldi3" |
963fc8d0 AK |
6236 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") |
6237 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
6238 | (match_operand:DI 2 "general_operand" "d,K,RT,Os")))] | |
9602b6a1 | 6239 | "TARGET_ZARCH" |
9db1d521 | 6240 | "@ |
d40c829f UW |
6241 | msgr\t%0,%2 |
6242 | mghi\t%0,%h2 | |
963fc8d0 AK |
6243 | msg\t%0,%2 |
6244 | msgfi\t%0,%2" | |
6245 | [(set_attr "op_type" "RRE,RI,RXY,RIL") | |
6246 | (set_attr "type" "imuldi") | |
6247 | (set_attr "cpu_facility" "*,*,*,z10")]) | |
f2d3c02a | 6248 | |
9db1d521 HP |
6249 | ; |
6250 | ; mulsi3 instruction pattern(s). | |
6251 | ; | |
6252 | ||
f1e77d83 | 6253 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
6254 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6255 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
6256 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 6257 | "" |
963fc8d0 AK |
6258 | "@ |
6259 | mh\t%0,%2 | |
6260 | mhy\t%0,%2" | |
6261 | [(set_attr "op_type" "RX,RXY") | |
6262 | (set_attr "type" "imulhi") | |
6263 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 6264 | |
9db1d521 | 6265 | (define_insn "mulsi3" |
963fc8d0 AK |
6266 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
6267 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
6268 | (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))] | |
9db1d521 HP |
6269 | "" |
6270 | "@ | |
d40c829f UW |
6271 | msr\t%0,%2 |
6272 | mhi\t%0,%h2 | |
6273 | ms\t%0,%2 | |
963fc8d0 AK |
6274 | msy\t%0,%2 |
6275 | msfi\t%0,%2" | |
6276 | [(set_attr "op_type" "RRE,RI,RX,RXY,RIL") | |
6277 | (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi") | |
6278 | (set_attr "cpu_facility" "*,*,*,*,z10")]) | |
9db1d521 | 6279 | |
4023fb28 UW |
6280 | ; |
6281 | ; mulsidi3 instruction pattern(s). | |
6282 | ; | |
6283 | ||
f1e77d83 | 6284 | (define_insn "mulsidi3" |
963fc8d0 | 6285 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 6286 | (mult:DI (sign_extend:DI |
963fc8d0 | 6287 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 6288 | (sign_extend:DI |
963fc8d0 | 6289 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
9602b6a1 | 6290 | "!TARGET_ZARCH" |
f1e77d83 UW |
6291 | "@ |
6292 | mr\t%0,%2 | |
963fc8d0 AK |
6293 | m\t%0,%2 |
6294 | mfy\t%0,%2" | |
6295 | [(set_attr "op_type" "RR,RX,RXY") | |
6296 | (set_attr "type" "imulsi") | |
6297 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 6298 | |
f1e77d83 | 6299 | ; |
6e0d70c9 | 6300 | ; umul instruction pattern(s). |
f1e77d83 | 6301 | ; |
c7453384 | 6302 | |
6e0d70c9 AK |
6303 | ; mlr, ml, mlgr, mlg |
6304 | (define_insn "umul<dwh><mode>3" | |
6305 | [(set (match_operand:DW 0 "register_operand" "=d, d") | |
6306 | (mult:DW (zero_extend:DW | |
6307 | (match_operand:<DWH> 1 "register_operand" "%0, 0")) | |
6308 | (zero_extend:DW | |
6309 | (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))] | |
6310 | "TARGET_CPU_ZARCH" | |
f1e77d83 | 6311 | "@ |
6e0d70c9 AK |
6312 | ml<tg>r\t%0,%2 |
6313 | ml<tg>\t%0,%2" | |
f1e77d83 | 6314 | [(set_attr "op_type" "RRE,RXY") |
6e0d70c9 | 6315 | (set_attr "type" "imul<dwh>")]) |
c7453384 | 6316 | |
9db1d521 | 6317 | ; |
609e7e80 | 6318 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6319 | ; |
6320 | ||
9381e3f1 | 6321 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 6322 | (define_insn "mul<mode>3" |
6e5b5de8 AK |
6323 | [(set (match_operand:FP 0 "register_operand" "=f, f,<vf>") |
6324 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>, 0,<v0>") | |
6325 | (match_operand:FP 2 "general_operand" "f,<Rf>,<vf>")))] | |
142cd70f | 6326 | "TARGET_HARD_FLOAT" |
9db1d521 | 6327 | "@ |
609e7e80 | 6328 | m<xdee><bt>r\t%0,<op1>%2 |
6e5b5de8 AK |
6329 | m<xdee>b\t%0,%2 |
6330 | wfmdb\t%v0,%v1,%v2" | |
6331 | [(set_attr "op_type" "<RRer>,RXE,VRR") | |
6332 | (set_attr "type" "fmul<mode>") | |
6333 | (set_attr "cpu_facility" "*,*,vec")]) | |
9db1d521 | 6334 | |
9381e3f1 | 6335 | ; madbr, maebr, maxb, madb, maeb |
d7ecb504 | 6336 | (define_insn "fma<mode>4" |
6e5b5de8 AK |
6337 | [(set (match_operand:DSF 0 "register_operand" "=f,f,<vf>") |
6338 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,<vf>") | |
6339 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,<vf>") | |
6340 | (match_operand:DSF 3 "register_operand" "0,0,<v0>")))] | |
d7ecb504 | 6341 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6342 | "@ |
f61a2c7d | 6343 | ma<xde>br\t%0,%1,%2 |
6e5b5de8 AK |
6344 | ma<xde>b\t%0,%1,%2 |
6345 | wfmadb\t%v0,%v1,%v2,%v3" | |
6346 | [(set_attr "op_type" "RRE,RXE,VRR") | |
6347 | (set_attr "type" "fmadd<mode>") | |
6348 | (set_attr "cpu_facility" "*,*,vec")]) | |
a1b892b5 | 6349 | |
43a09b63 | 6350 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
d7ecb504 | 6351 | (define_insn "fms<mode>4" |
6e5b5de8 AK |
6352 | [(set (match_operand:DSF 0 "register_operand" "=f,f,<vf>") |
6353 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,<vf>") | |
6354 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,<vf>") | |
6355 | (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,<v0>"))))] | |
d7ecb504 | 6356 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6357 | "@ |
f61a2c7d | 6358 | ms<xde>br\t%0,%1,%2 |
6e5b5de8 AK |
6359 | ms<xde>b\t%0,%1,%2 |
6360 | wfmsdb\t%v0,%v1,%v2,%v3" | |
6361 | [(set_attr "op_type" "RRE,RXE,VRR") | |
6362 | (set_attr "type" "fmadd<mode>") | |
6363 | (set_attr "cpu_facility" "*,*,vec")]) | |
9db1d521 HP |
6364 | |
6365 | ;; | |
6366 | ;;- Divide and modulo instructions. | |
6367 | ;; | |
6368 | ||
6369 | ; | |
4023fb28 | 6370 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
6371 | ; |
6372 | ||
4023fb28 UW |
6373 | (define_expand "divmoddi4" |
6374 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 6375 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
6376 | (match_operand:DI 2 "general_operand" ""))) |
6377 | (set (match_operand:DI 3 "general_operand" "") | |
6378 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
6379 | (clobber (match_dup 4))] | |
9602b6a1 | 6380 | "TARGET_ZARCH" |
9db1d521 | 6381 | { |
f1e77d83 | 6382 | rtx insn, div_equal, mod_equal; |
4023fb28 UW |
6383 | |
6384 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
6385 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
6386 | |
6387 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 6388 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
6389 | |
6390 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6391 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6392 | |
6393 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6394 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6395 | |
9db1d521 | 6396 | DONE; |
10bbf137 | 6397 | }) |
9db1d521 HP |
6398 | |
6399 | (define_insn "divmodtidi3" | |
4023fb28 UW |
6400 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
6401 | (ior:TI | |
4023fb28 UW |
6402 | (ashift:TI |
6403 | (zero_extend:TI | |
5665e398 | 6404 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
fb492564 | 6405 | (match_operand:DI 2 "general_operand" "d,RT"))) |
5665e398 UW |
6406 | (const_int 64)) |
6407 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9602b6a1 | 6408 | "TARGET_ZARCH" |
9db1d521 | 6409 | "@ |
d40c829f UW |
6410 | dsgr\t%0,%2 |
6411 | dsg\t%0,%2" | |
d3632d41 | 6412 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6413 | (set_attr "type" "idiv")]) |
9db1d521 | 6414 | |
4023fb28 UW |
6415 | (define_insn "divmodtisi3" |
6416 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6417 | (ior:TI | |
4023fb28 UW |
6418 | (ashift:TI |
6419 | (zero_extend:TI | |
5665e398 | 6420 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 6421 | (sign_extend:DI |
fb492564 | 6422 | (match_operand:SI 2 "nonimmediate_operand" "d,RT")))) |
5665e398 UW |
6423 | (const_int 64)) |
6424 | (zero_extend:TI | |
6425 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9602b6a1 | 6426 | "TARGET_ZARCH" |
4023fb28 | 6427 | "@ |
d40c829f UW |
6428 | dsgfr\t%0,%2 |
6429 | dsgf\t%0,%2" | |
d3632d41 | 6430 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6431 | (set_attr "type" "idiv")]) |
9db1d521 | 6432 | |
4023fb28 UW |
6433 | ; |
6434 | ; udivmoddi4 instruction pattern(s). | |
6435 | ; | |
9db1d521 | 6436 | |
4023fb28 UW |
6437 | (define_expand "udivmoddi4" |
6438 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
6439 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
6440 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
6441 | (set (match_operand:DI 3 "general_operand" "") | |
6442 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
6443 | (clobber (match_dup 4))] | |
9602b6a1 | 6444 | "TARGET_ZARCH" |
9db1d521 | 6445 | { |
4023fb28 UW |
6446 | rtx insn, div_equal, mod_equal, equal; |
6447 | ||
6448 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
6449 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
6450 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
6451 | gen_rtx_ASHIFT (TImode, |
6452 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
6453 | GEN_INT (64)), |
6454 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
6455 | |
6456 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 6457 | emit_clobber (operands[4]); |
4023fb28 UW |
6458 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
6459 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 6460 | |
4023fb28 | 6461 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6462 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
6463 | |
6464 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6465 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6466 | |
6467 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6468 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6469 | |
9db1d521 | 6470 | DONE; |
10bbf137 | 6471 | }) |
9db1d521 HP |
6472 | |
6473 | (define_insn "udivmodtidi3" | |
4023fb28 | 6474 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 6475 | (ior:TI |
5665e398 UW |
6476 | (ashift:TI |
6477 | (zero_extend:TI | |
6478 | (truncate:DI | |
2f7e5a0d EC |
6479 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
6480 | (zero_extend:TI | |
fb492564 | 6481 | (match_operand:DI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
6482 | (const_int 64)) |
6483 | (zero_extend:TI | |
6484 | (truncate:DI | |
6485 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9602b6a1 | 6486 | "TARGET_ZARCH" |
9db1d521 | 6487 | "@ |
d40c829f UW |
6488 | dlgr\t%0,%2 |
6489 | dlg\t%0,%2" | |
d3632d41 | 6490 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6491 | (set_attr "type" "idiv")]) |
9db1d521 HP |
6492 | |
6493 | ; | |
4023fb28 | 6494 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
6495 | ; |
6496 | ||
4023fb28 UW |
6497 | (define_expand "divmodsi4" |
6498 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
6499 | (div:SI (match_operand:SI 1 "general_operand" "") | |
6500 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
6501 | (set (match_operand:SI 3 "general_operand" "") | |
6502 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
6503 | (clobber (match_dup 4))] | |
9602b6a1 | 6504 | "!TARGET_ZARCH" |
9db1d521 | 6505 | { |
4023fb28 UW |
6506 | rtx insn, div_equal, mod_equal, equal; |
6507 | ||
6508 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
6509 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
6510 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
6511 | gen_rtx_ASHIFT (DImode, |
6512 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
6513 | GEN_INT (32)), |
6514 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
6515 | |
6516 | operands[4] = gen_reg_rtx(DImode); | |
6517 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 6518 | |
4023fb28 | 6519 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6520 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
6521 | |
6522 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 6523 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6524 | |
6525 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 6526 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6527 | |
9db1d521 | 6528 | DONE; |
10bbf137 | 6529 | }) |
9db1d521 HP |
6530 | |
6531 | (define_insn "divmoddisi3" | |
4023fb28 | 6532 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 6533 | (ior:DI |
5665e398 UW |
6534 | (ashift:DI |
6535 | (zero_extend:DI | |
6536 | (truncate:SI | |
2f7e5a0d EC |
6537 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
6538 | (sign_extend:DI | |
5665e398 UW |
6539 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
6540 | (const_int 32)) | |
6541 | (zero_extend:DI | |
6542 | (truncate:SI | |
6543 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 6544 | "!TARGET_ZARCH" |
9db1d521 | 6545 | "@ |
d40c829f UW |
6546 | dr\t%0,%2 |
6547 | d\t%0,%2" | |
9db1d521 | 6548 | [(set_attr "op_type" "RR,RX") |
077dab3b | 6549 | (set_attr "type" "idiv")]) |
9db1d521 HP |
6550 | |
6551 | ; | |
6552 | ; udivsi3 and umodsi3 instruction pattern(s). | |
6553 | ; | |
6554 | ||
f1e77d83 UW |
6555 | (define_expand "udivmodsi4" |
6556 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
6557 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
6558 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
6559 | (set (match_operand:SI 3 "general_operand" "") | |
6560 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
6561 | (clobber (match_dup 4))] | |
9602b6a1 | 6562 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
6563 | { |
6564 | rtx insn, div_equal, mod_equal, equal; | |
6565 | ||
6566 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
6567 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
6568 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
6569 | gen_rtx_ASHIFT (DImode, |
6570 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
6571 | GEN_INT (32)), |
6572 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
6573 | |
6574 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 6575 | emit_clobber (operands[4]); |
f1e77d83 UW |
6576 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
6577 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 6578 | |
f1e77d83 | 6579 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6580 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
6581 | |
6582 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 6583 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
6584 | |
6585 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 6586 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
6587 | |
6588 | DONE; | |
6589 | }) | |
6590 | ||
6591 | (define_insn "udivmoddisi3" | |
6592 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 6593 | (ior:DI |
5665e398 UW |
6594 | (ashift:DI |
6595 | (zero_extend:DI | |
6596 | (truncate:SI | |
2f7e5a0d EC |
6597 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
6598 | (zero_extend:DI | |
fb492564 | 6599 | (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))) |
5665e398 UW |
6600 | (const_int 32)) |
6601 | (zero_extend:DI | |
6602 | (truncate:SI | |
6603 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 6604 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
6605 | "@ |
6606 | dlr\t%0,%2 | |
6607 | dl\t%0,%2" | |
6608 | [(set_attr "op_type" "RRE,RXY") | |
6609 | (set_attr "type" "idiv")]) | |
4023fb28 | 6610 | |
9db1d521 HP |
6611 | (define_expand "udivsi3" |
6612 | [(set (match_operand:SI 0 "register_operand" "=d") | |
6613 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
6614 | (match_operand:SI 2 "general_operand" ""))) |
6615 | (clobber (match_dup 3))] | |
9602b6a1 | 6616 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 6617 | { |
4023fb28 UW |
6618 | rtx insn, udiv_equal, umod_equal, equal; |
6619 | ||
6620 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
6621 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
6622 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
6623 | gen_rtx_ASHIFT (DImode, |
6624 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
6625 | GEN_INT (32)), |
6626 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 6627 | |
4023fb28 | 6628 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
6629 | |
6630 | if (CONSTANT_P (operands[2])) | |
6631 | { | |
6632 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
6633 | { | |
19f8b229 | 6634 | rtx_code_label *label1 = gen_label_rtx (); |
9db1d521 | 6635 | |
4023fb28 UW |
6636 | operands[1] = make_safe_from (operands[1], operands[0]); |
6637 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
6638 | emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX, |
6639 | SImode, 1, label1); | |
4023fb28 | 6640 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
6641 | emit_label (label1); |
6642 | } | |
6643 | else | |
6644 | { | |
c7453384 EC |
6645 | operands[2] = force_reg (SImode, operands[2]); |
6646 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
6647 | |
6648 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
6649 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6650 | operands[2])); | |
bd94cb6e | 6651 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6652 | |
6653 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6654 | gen_lowpart (SImode, operands[3])); |
bd94cb6e | 6655 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
9db1d521 HP |
6656 | } |
6657 | } | |
6658 | else | |
c7453384 | 6659 | { |
19f8b229 TS |
6660 | rtx_code_label *label1 = gen_label_rtx (); |
6661 | rtx_code_label *label2 = gen_label_rtx (); | |
6662 | rtx_code_label *label3 = gen_label_rtx (); | |
9db1d521 | 6663 | |
c7453384 EC |
6664 | operands[1] = force_reg (SImode, operands[1]); |
6665 | operands[1] = make_safe_from (operands[1], operands[0]); | |
6666 | operands[2] = force_reg (SImode, operands[2]); | |
6667 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
6668 | |
6669 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
6670 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
6671 | SImode, 1, label3); | |
6672 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
6673 | SImode, 0, label2); | |
6674 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
6675 | SImode, 0, label1); | |
4023fb28 UW |
6676 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
6677 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6678 | operands[2])); | |
bd94cb6e | 6679 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6680 | |
6681 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6682 | gen_lowpart (SImode, operands[3])); |
bd94cb6e SB |
6683 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
6684 | ||
f314b9b1 | 6685 | emit_jump (label3); |
9db1d521 | 6686 | emit_label (label1); |
4023fb28 | 6687 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 6688 | emit_jump (label3); |
9db1d521 | 6689 | emit_label (label2); |
4023fb28 | 6690 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
6691 | emit_label (label3); |
6692 | } | |
c7453384 | 6693 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 6694 | DONE; |
10bbf137 | 6695 | }) |
9db1d521 HP |
6696 | |
6697 | (define_expand "umodsi3" | |
6698 | [(set (match_operand:SI 0 "register_operand" "=d") | |
6699 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
6700 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
6701 | (clobber (match_dup 3))] | |
9602b6a1 | 6702 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 6703 | { |
4023fb28 UW |
6704 | rtx insn, udiv_equal, umod_equal, equal; |
6705 | ||
6706 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
6707 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
6708 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
6709 | gen_rtx_ASHIFT (DImode, |
6710 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
6711 | GEN_INT (32)), |
6712 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 6713 | |
4023fb28 | 6714 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
6715 | |
6716 | if (CONSTANT_P (operands[2])) | |
6717 | { | |
6718 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
6719 | { | |
19f8b229 | 6720 | rtx_code_label *label1 = gen_label_rtx (); |
9db1d521 | 6721 | |
4023fb28 UW |
6722 | operands[1] = make_safe_from (operands[1], operands[0]); |
6723 | emit_move_insn (operands[0], operands[1]); | |
f90b7a5a PB |
6724 | emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX, |
6725 | SImode, 1, label1); | |
4023fb28 UW |
6726 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
6727 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
6728 | emit_label (label1); |
6729 | } | |
6730 | else | |
6731 | { | |
c7453384 EC |
6732 | operands[2] = force_reg (SImode, operands[2]); |
6733 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
6734 | |
6735 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
6736 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6737 | operands[2])); | |
bd94cb6e | 6738 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6739 | |
6740 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6741 | gen_highpart (SImode, operands[3])); |
bd94cb6e | 6742 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
9db1d521 HP |
6743 | } |
6744 | } | |
6745 | else | |
6746 | { | |
19f8b229 TS |
6747 | rtx_code_label *label1 = gen_label_rtx (); |
6748 | rtx_code_label *label2 = gen_label_rtx (); | |
6749 | rtx_code_label *label3 = gen_label_rtx (); | |
9db1d521 | 6750 | |
c7453384 EC |
6751 | operands[1] = force_reg (SImode, operands[1]); |
6752 | operands[1] = make_safe_from (operands[1], operands[0]); | |
6753 | operands[2] = force_reg (SImode, operands[2]); | |
6754 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 6755 | |
c7453384 | 6756 | emit_move_insn(operands[0], operands[1]); |
f90b7a5a PB |
6757 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
6758 | SImode, 1, label3); | |
6759 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
6760 | SImode, 0, label2); | |
6761 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
6762 | SImode, 0, label1); | |
4023fb28 UW |
6763 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
6764 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
6765 | operands[2])); | |
bd94cb6e | 6766 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
6767 | |
6768 | insn = emit_move_insn (operands[0], | |
4023fb28 | 6769 | gen_highpart (SImode, operands[3])); |
bd94cb6e SB |
6770 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
6771 | ||
f314b9b1 | 6772 | emit_jump (label3); |
9db1d521 | 6773 | emit_label (label1); |
4023fb28 | 6774 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 6775 | emit_jump (label3); |
9db1d521 | 6776 | emit_label (label2); |
4023fb28 | 6777 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
6778 | emit_label (label3); |
6779 | } | |
9db1d521 | 6780 | DONE; |
10bbf137 | 6781 | }) |
9db1d521 HP |
6782 | |
6783 | ; | |
f5905b37 | 6784 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
6785 | ; |
6786 | ||
609e7e80 | 6787 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 6788 | (define_insn "div<mode>3" |
6e5b5de8 AK |
6789 | [(set (match_operand:FP 0 "register_operand" "=f, f,<vf>") |
6790 | (div:FP (match_operand:FP 1 "register_operand" "<f0>, 0,<v0>") | |
6791 | (match_operand:FP 2 "general_operand" "f,<Rf>,<vf>")))] | |
142cd70f | 6792 | "TARGET_HARD_FLOAT" |
9db1d521 | 6793 | "@ |
609e7e80 | 6794 | d<xde><bt>r\t%0,<op1>%2 |
6e5b5de8 AK |
6795 | d<xde>b\t%0,%2 |
6796 | wfddb\t%v0,%v1,%v2" | |
6797 | [(set_attr "op_type" "<RRer>,RXE,VRR") | |
6798 | (set_attr "type" "fdiv<mode>") | |
6799 | (set_attr "cpu_facility" "*,*,vec")]) | |
9db1d521 | 6800 | |
9db1d521 HP |
6801 | |
6802 | ;; | |
6803 | ;;- And instructions. | |
6804 | ;; | |
6805 | ||
047d35ed AS |
6806 | (define_expand "and<mode>3" |
6807 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
6808 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
6809 | (match_operand:INT 2 "general_operand" ""))) | |
6810 | (clobber (reg:CC CC_REGNUM))] | |
6811 | "" | |
6812 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
6813 | ||
9db1d521 HP |
6814 | ; |
6815 | ; anddi3 instruction pattern(s). | |
6816 | ; | |
6817 | ||
6818 | (define_insn "*anddi3_cc" | |
ae156f85 | 6819 | [(set (reg CC_REGNUM) |
e3140518 RH |
6820 | (compare |
6821 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d") | |
6822 | (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq")) | |
6823 | (const_int 0))) | |
6824 | (set (match_operand:DI 0 "register_operand" "=d,d, d, d") | |
9db1d521 | 6825 | (and:DI (match_dup 1) (match_dup 2)))] |
e3140518 | 6826 | "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" |
9db1d521 | 6827 | "@ |
d40c829f | 6828 | ngr\t%0,%2 |
65b1d8ea | 6829 | ngrk\t%0,%1,%2 |
e3140518 RH |
6830 | ng\t%0,%2 |
6831 | risbg\t%0,%1,%s2,128+%e2,0" | |
6832 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
6833 | (set_attr "cpu_facility" "*,z196,*,z10") | |
6834 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
6835 | |
6836 | (define_insn "*anddi3_cconly" | |
ae156f85 | 6837 | [(set (reg CC_REGNUM) |
e3140518 RH |
6838 | (compare |
6839 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d") | |
6840 | (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq")) | |
9db1d521 | 6841 | (const_int 0))) |
e3140518 RH |
6842 | (clobber (match_scratch:DI 0 "=d,d, d, d"))] |
6843 | "TARGET_ZARCH | |
6844 | && s390_match_ccmode(insn, CCTmode) | |
68f9c5e2 UW |
6845 | /* Do not steal TM patterns. */ |
6846 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 6847 | "@ |
d40c829f | 6848 | ngr\t%0,%2 |
65b1d8ea | 6849 | ngrk\t%0,%1,%2 |
e3140518 RH |
6850 | ng\t%0,%2 |
6851 | risbg\t%0,%1,%s2,128+%e2,0" | |
6852 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
6853 | (set_attr "cpu_facility" "*,z196,*,z10") | |
6854 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 6855 | |
3af8e996 | 6856 | (define_insn "*anddi3" |
65b1d8ea | 6857 | [(set (match_operand:DI 0 "nonimmediate_operand" |
e3140518 RH |
6858 | "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q") |
6859 | (and:DI | |
6860 | (match_operand:DI 1 "nonimmediate_operand" | |
6861 | "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0") | |
6862 | (match_operand:DI 2 "general_operand" | |
6863 | "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q"))) | |
ec24698e | 6864 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6865 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
6866 | "@ |
6867 | # | |
6868 | # | |
6869 | nihh\t%0,%j2 | |
6870 | nihl\t%0,%j2 | |
6871 | nilh\t%0,%j2 | |
6872 | nill\t%0,%j2 | |
6873 | nihf\t%0,%m2 | |
6874 | nilf\t%0,%m2 | |
6875 | ngr\t%0,%2 | |
65b1d8ea | 6876 | ngrk\t%0,%1,%2 |
ec24698e | 6877 | ng\t%0,%2 |
e3140518 | 6878 | risbg\t%0,%1,%s2,128+%e2,0 |
ec24698e UW |
6879 | # |
6880 | #" | |
e3140518 RH |
6881 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS") |
6882 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*") | |
9381e3f1 WG |
6883 | (set_attr "z10prop" "*, |
6884 | *, | |
6885 | z10_super_E1, | |
6886 | z10_super_E1, | |
6887 | z10_super_E1, | |
6888 | z10_super_E1, | |
6889 | z10_super_E1, | |
6890 | z10_super_E1, | |
6891 | z10_super_E1, | |
65b1d8ea | 6892 | *, |
9381e3f1 | 6893 | z10_super_E1, |
e3140518 | 6894 | z10_super_E1, |
9381e3f1 WG |
6895 | *, |
6896 | *")]) | |
0dfa6c5e UW |
6897 | |
6898 | (define_split | |
6899 | [(set (match_operand:DI 0 "s_operand" "") | |
6900 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 6901 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
6902 | "reload_completed" |
6903 | [(parallel | |
6904 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 6905 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 6906 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 6907 | |
1a2e356e RH |
6908 | ;; These two are what combine generates for (ashift (zero_extract)). |
6909 | (define_insn "*extzv_<mode>_srl" | |
6910 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6911 | (and:GPR (lshiftrt:GPR | |
6912 | (match_operand:GPR 1 "register_operand" "d") | |
6913 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
6914 | (match_operand:GPR 3 "contiguous_bitmask_operand" ""))) | |
6915 | (clobber (reg:CC CC_REGNUM))] | |
6916 | "TARGET_Z10 | |
6917 | /* Note that even for the SImode pattern, the rotate is always DImode. */ | |
6918 | && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]), | |
6919 | INTVAL (operands[3]))" | |
6920 | "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2" | |
6921 | [(set_attr "op_type" "RIE") | |
6922 | (set_attr "z10prop" "z10_super_E1")]) | |
6923 | ||
6924 | (define_insn "*extzv_<mode>_sll" | |
6925 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
6926 | (and:GPR (ashift:GPR | |
6927 | (match_operand:GPR 1 "register_operand" "d") | |
6928 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
6929 | (match_operand:GPR 3 "contiguous_bitmask_operand" ""))) | |
6930 | (clobber (reg:CC CC_REGNUM))] | |
6931 | "TARGET_Z10 | |
6932 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]), | |
6933 | INTVAL (operands[3]))" | |
6934 | "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2" | |
6935 | [(set_attr "op_type" "RIE") | |
6936 | (set_attr "z10prop" "z10_super_E1")]) | |
6937 | ||
9db1d521 HP |
6938 | |
6939 | ; | |
6940 | ; andsi3 instruction pattern(s). | |
6941 | ; | |
6942 | ||
6943 | (define_insn "*andsi3_cc" | |
ae156f85 | 6944 | [(set (reg CC_REGNUM) |
e3140518 RH |
6945 | (compare |
6946 | (and:SI | |
6947 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
6948 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
6949 | (const_int 0))) | |
6950 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d") | |
9db1d521 HP |
6951 | (and:SI (match_dup 1) (match_dup 2)))] |
6952 | "s390_match_ccmode(insn, CCTmode)" | |
6953 | "@ | |
ec24698e | 6954 | nilf\t%0,%o2 |
d40c829f | 6955 | nr\t%0,%2 |
65b1d8ea | 6956 | nrk\t%0,%1,%2 |
d40c829f | 6957 | n\t%0,%2 |
e3140518 RH |
6958 | ny\t%0,%2 |
6959 | risbg\t%0,%1,%t2,128+%f2,0" | |
6960 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
6961 | (set_attr "cpu_facility" "*,*,z196,*,*,z10") | |
6962 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
6963 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
6964 | |
6965 | (define_insn "*andsi3_cconly" | |
ae156f85 | 6966 | [(set (reg CC_REGNUM) |
e3140518 RH |
6967 | (compare |
6968 | (and:SI | |
6969 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
6970 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
6971 | (const_int 0))) | |
6972 | (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))] | |
68f9c5e2 UW |
6973 | "s390_match_ccmode(insn, CCTmode) |
6974 | /* Do not steal TM patterns. */ | |
6975 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 6976 | "@ |
ec24698e | 6977 | nilf\t%0,%o2 |
d40c829f | 6978 | nr\t%0,%2 |
65b1d8ea | 6979 | nrk\t%0,%1,%2 |
d40c829f | 6980 | n\t%0,%2 |
e3140518 RH |
6981 | ny\t%0,%2 |
6982 | risbg\t%0,%1,%t2,128+%f2,0" | |
6983 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
6984 | (set_attr "cpu_facility" "*,*,z196,*,*,z10") | |
65b1d8ea | 6985 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
e3140518 | 6986 | z10_super_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 6987 | |
f19a9af7 | 6988 | (define_insn "*andsi3_zarch" |
65b1d8ea | 6989 | [(set (match_operand:SI 0 "nonimmediate_operand" |
e3140518 | 6990 | "=d,d, d, d, d,d,d,d,d, d, AQ,Q") |
0dfa6c5e | 6991 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
e3140518 | 6992 | "%d,o, 0, 0, 0,0,d,0,0, d, 0,0") |
0dfa6c5e | 6993 | (match_operand:SI 2 "general_operand" |
e3140518 | 6994 | " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q"))) |
ae156f85 | 6995 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 6996 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 6997 | "@ |
f19a9af7 AK |
6998 | # |
6999 | # | |
7000 | nilh\t%0,%j2 | |
2f7e5a0d | 7001 | nill\t%0,%j2 |
ec24698e | 7002 | nilf\t%0,%o2 |
d40c829f | 7003 | nr\t%0,%2 |
65b1d8ea | 7004 | nrk\t%0,%1,%2 |
d40c829f | 7005 | n\t%0,%2 |
8cb66696 | 7006 | ny\t%0,%2 |
e3140518 | 7007 | risbg\t%0,%1,%t2,128+%f2,0 |
0dfa6c5e | 7008 | # |
19b63d8e | 7009 | #" |
e3140518 RH |
7010 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") |
7011 | (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*") | |
9381e3f1 WG |
7012 | (set_attr "z10prop" "*, |
7013 | *, | |
7014 | z10_super_E1, | |
7015 | z10_super_E1, | |
7016 | z10_super_E1, | |
7017 | z10_super_E1, | |
65b1d8ea | 7018 | *, |
9381e3f1 WG |
7019 | z10_super_E1, |
7020 | z10_super_E1, | |
e3140518 | 7021 | z10_super_E1, |
9381e3f1 WG |
7022 | *, |
7023 | *")]) | |
f19a9af7 AK |
7024 | |
7025 | (define_insn "*andsi3_esa" | |
65b1d8ea AK |
7026 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") |
7027 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") | |
7028 | (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) | |
ae156f85 | 7029 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7030 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7031 | "@ |
7032 | nr\t%0,%2 | |
8cb66696 | 7033 | n\t%0,%2 |
0dfa6c5e | 7034 | # |
19b63d8e | 7035 | #" |
9381e3f1 WG |
7036 | [(set_attr "op_type" "RR,RX,SI,SS") |
7037 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
7038 | ||
0dfa6c5e UW |
7039 | |
7040 | (define_split | |
7041 | [(set (match_operand:SI 0 "s_operand" "") | |
7042 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7043 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7044 | "reload_completed" |
7045 | [(parallel | |
7046 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7047 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7048 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7049 | |
9db1d521 HP |
7050 | ; |
7051 | ; andhi3 instruction pattern(s). | |
7052 | ; | |
7053 | ||
8cb66696 | 7054 | (define_insn "*andhi3_zarch" |
65b1d8ea AK |
7055 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7056 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7057 | (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) | |
ae156f85 | 7058 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7059 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7060 | "@ |
d40c829f | 7061 | nr\t%0,%2 |
65b1d8ea | 7062 | nrk\t%0,%1,%2 |
8cb66696 | 7063 | nill\t%0,%x2 |
0dfa6c5e | 7064 | # |
19b63d8e | 7065 | #" |
65b1d8ea AK |
7066 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7067 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7068 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") | |
9381e3f1 | 7069 | ]) |
8cb66696 UW |
7070 | |
7071 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
7072 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7073 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7074 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 7075 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7076 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7077 | "@ | |
7078 | nr\t%0,%2 | |
0dfa6c5e | 7079 | # |
19b63d8e | 7080 | #" |
9381e3f1 WG |
7081 | [(set_attr "op_type" "RR,SI,SS") |
7082 | (set_attr "z10prop" "z10_super_E1,*,*") | |
7083 | ]) | |
0dfa6c5e UW |
7084 | |
7085 | (define_split | |
7086 | [(set (match_operand:HI 0 "s_operand" "") | |
7087 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7088 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7089 | "reload_completed" |
7090 | [(parallel | |
7091 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7092 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7093 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 7094 | |
9db1d521 HP |
7095 | ; |
7096 | ; andqi3 instruction pattern(s). | |
7097 | ; | |
7098 | ||
8cb66696 | 7099 | (define_insn "*andqi3_zarch" |
65b1d8ea AK |
7100 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7101 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7102 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7103 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7104 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7105 | "@ |
d40c829f | 7106 | nr\t%0,%2 |
65b1d8ea | 7107 | nrk\t%0,%1,%2 |
8cb66696 | 7108 | nill\t%0,%b2 |
fc0ea003 UW |
7109 | ni\t%S0,%b2 |
7110 | niy\t%S0,%b2 | |
19b63d8e | 7111 | #" |
65b1d8ea AK |
7112 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
7113 | (set_attr "cpu_facility" "*,z196,*,*,*,*") | |
7114 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) | |
8cb66696 UW |
7115 | |
7116 | (define_insn "*andqi3_esa" | |
7117 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7118 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7119 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7120 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7121 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7122 | "@ |
8cb66696 | 7123 | nr\t%0,%2 |
fc0ea003 | 7124 | ni\t%S0,%b2 |
19b63d8e | 7125 | #" |
9381e3f1 WG |
7126 | [(set_attr "op_type" "RR,SI,SS") |
7127 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 7128 | |
19b63d8e UW |
7129 | ; |
7130 | ; Block and (NC) patterns. | |
7131 | ; | |
7132 | ||
7133 | (define_insn "*nc" | |
7134 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7135 | (and:BLK (match_dup 0) | |
7136 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7137 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7138 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7139 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7140 | "nc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7141 | [(set_attr "op_type" "SS") |
7142 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7143 | |
7144 | (define_split | |
7145 | [(set (match_operand 0 "memory_operand" "") | |
7146 | (and (match_dup 0) | |
7147 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7148 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7149 | "reload_completed |
7150 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7151 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7152 | [(parallel | |
7153 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
7154 | (use (match_dup 2)) | |
ae156f85 | 7155 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7156 | { |
7157 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7158 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7159 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7160 | }) | |
7161 | ||
7162 | (define_peephole2 | |
7163 | [(parallel | |
7164 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7165 | (and:BLK (match_dup 0) | |
7166 | (match_operand:BLK 1 "memory_operand" ""))) | |
7167 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7168 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7169 | (parallel |
7170 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7171 | (and:BLK (match_dup 3) | |
7172 | (match_operand:BLK 4 "memory_operand" ""))) | |
7173 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7174 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7175 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7176 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7177 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7178 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7179 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7180 | [(parallel | |
7181 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
7182 | (use (match_dup 8)) | |
ae156f85 | 7183 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7184 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7185 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7186 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7187 | ||
9db1d521 HP |
7188 | |
7189 | ;; | |
7190 | ;;- Bit set (inclusive or) instructions. | |
7191 | ;; | |
7192 | ||
047d35ed AS |
7193 | (define_expand "ior<mode>3" |
7194 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7195 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7196 | (match_operand:INT 2 "general_operand" ""))) | |
7197 | (clobber (reg:CC CC_REGNUM))] | |
7198 | "" | |
7199 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
7200 | ||
9db1d521 HP |
7201 | ; |
7202 | ; iordi3 instruction pattern(s). | |
7203 | ; | |
7204 | ||
4023fb28 | 7205 | (define_insn "*iordi3_cc" |
ae156f85 | 7206 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7207 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
7208 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 7209 | (const_int 0))) |
65b1d8ea | 7210 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
4023fb28 | 7211 | (ior:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7212 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7213 | "@ |
d40c829f | 7214 | ogr\t%0,%2 |
65b1d8ea | 7215 | ogrk\t%0,%1,%2 |
d40c829f | 7216 | og\t%0,%2" |
65b1d8ea AK |
7217 | [(set_attr "op_type" "RRE,RRF,RXY") |
7218 | (set_attr "cpu_facility" "*,z196,*") | |
7219 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 UW |
7220 | |
7221 | (define_insn "*iordi3_cconly" | |
ae156f85 | 7222 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7223 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7224 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 7225 | (const_int 0))) |
65b1d8ea | 7226 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 7227 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7228 | "@ |
d40c829f | 7229 | ogr\t%0,%2 |
65b1d8ea | 7230 | ogrk\t%0,%1,%2 |
d40c829f | 7231 | og\t%0,%2" |
65b1d8ea AK |
7232 | [(set_attr "op_type" "RRE,RRF,RXY") |
7233 | (set_attr "cpu_facility" "*,z196,*") | |
7234 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7235 | |
3af8e996 | 7236 | (define_insn "*iordi3" |
65b1d8ea AK |
7237 | [(set (match_operand:DI 0 "nonimmediate_operand" |
7238 | "=d, d, d, d, d, d,d,d, d, AQ,Q") | |
7239 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" | |
7240 | " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0") | |
ec24698e | 7241 | (match_operand:DI 2 "general_operand" |
65b1d8ea | 7242 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) |
ec24698e | 7243 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7244 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7245 | "@ |
7246 | oihh\t%0,%i2 | |
7247 | oihl\t%0,%i2 | |
7248 | oilh\t%0,%i2 | |
7249 | oill\t%0,%i2 | |
7250 | oihf\t%0,%k2 | |
7251 | oilf\t%0,%k2 | |
7252 | ogr\t%0,%2 | |
65b1d8ea | 7253 | ogrk\t%0,%1,%2 |
ec24698e UW |
7254 | og\t%0,%2 |
7255 | # | |
7256 | #" | |
65b1d8ea AK |
7257 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
7258 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
7259 | (set_attr "z10prop" "z10_super_E1, |
7260 | z10_super_E1, | |
7261 | z10_super_E1, | |
7262 | z10_super_E1, | |
7263 | z10_super_E1, | |
7264 | z10_super_E1, | |
7265 | z10_super_E1, | |
65b1d8ea | 7266 | *, |
9381e3f1 WG |
7267 | z10_super_E1, |
7268 | *, | |
7269 | *")]) | |
0dfa6c5e UW |
7270 | |
7271 | (define_split | |
7272 | [(set (match_operand:DI 0 "s_operand" "") | |
7273 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7274 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7275 | "reload_completed" |
7276 | [(parallel | |
7277 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7278 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7279 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7280 | |
9db1d521 HP |
7281 | ; |
7282 | ; iorsi3 instruction pattern(s). | |
7283 | ; | |
7284 | ||
4023fb28 | 7285 | (define_insn "*iorsi3_cc" |
ae156f85 | 7286 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7287 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7288 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7289 | (const_int 0))) |
65b1d8ea | 7290 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7291 | (ior:SI (match_dup 1) (match_dup 2)))] |
7292 | "s390_match_ccmode(insn, CCTmode)" | |
7293 | "@ | |
ec24698e | 7294 | oilf\t%0,%o2 |
d40c829f | 7295 | or\t%0,%2 |
65b1d8ea | 7296 | ork\t%0,%1,%2 |
d40c829f UW |
7297 | o\t%0,%2 |
7298 | oy\t%0,%2" | |
65b1d8ea AK |
7299 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
7300 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7301 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
7302 | |
7303 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 7304 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7305 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7306 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7307 | (const_int 0))) |
65b1d8ea | 7308 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7309 | "s390_match_ccmode(insn, CCTmode)" |
7310 | "@ | |
ec24698e | 7311 | oilf\t%0,%o2 |
d40c829f | 7312 | or\t%0,%2 |
65b1d8ea | 7313 | ork\t%0,%1,%2 |
d40c829f UW |
7314 | o\t%0,%2 |
7315 | oy\t%0,%2" | |
65b1d8ea AK |
7316 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
7317 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7318 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
4023fb28 | 7319 | |
8cb66696 | 7320 | (define_insn "*iorsi3_zarch" |
65b1d8ea AK |
7321 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") |
7322 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") | |
7323 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7324 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7325 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7326 | "@ |
f19a9af7 AK |
7327 | oilh\t%0,%i2 |
7328 | oill\t%0,%i2 | |
ec24698e | 7329 | oilf\t%0,%o2 |
d40c829f | 7330 | or\t%0,%2 |
65b1d8ea | 7331 | ork\t%0,%1,%2 |
d40c829f | 7332 | o\t%0,%2 |
8cb66696 | 7333 | oy\t%0,%2 |
0dfa6c5e | 7334 | # |
19b63d8e | 7335 | #" |
65b1d8ea AK |
7336 | [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
7337 | (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*") | |
9381e3f1 WG |
7338 | (set_attr "z10prop" "z10_super_E1, |
7339 | z10_super_E1, | |
7340 | z10_super_E1, | |
7341 | z10_super_E1, | |
65b1d8ea | 7342 | *, |
9381e3f1 WG |
7343 | z10_super_E1, |
7344 | z10_super_E1, | |
7345 | *, | |
7346 | *")]) | |
8cb66696 UW |
7347 | |
7348 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 7349 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 7350 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 7351 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 7352 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7353 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7354 | "@ |
7355 | or\t%0,%2 | |
8cb66696 | 7356 | o\t%0,%2 |
0dfa6c5e | 7357 | # |
19b63d8e | 7358 | #" |
9381e3f1 WG |
7359 | [(set_attr "op_type" "RR,RX,SI,SS") |
7360 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7361 | |
7362 | (define_split | |
7363 | [(set (match_operand:SI 0 "s_operand" "") | |
7364 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7365 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7366 | "reload_completed" |
7367 | [(parallel | |
7368 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7369 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7370 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7371 | |
4023fb28 UW |
7372 | ; |
7373 | ; iorhi3 instruction pattern(s). | |
7374 | ; | |
7375 | ||
8cb66696 | 7376 | (define_insn "*iorhi3_zarch" |
65b1d8ea AK |
7377 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7378 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7379 | (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) | |
ae156f85 | 7380 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7381 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7382 | "@ |
d40c829f | 7383 | or\t%0,%2 |
65b1d8ea | 7384 | ork\t%0,%1,%2 |
8cb66696 | 7385 | oill\t%0,%x2 |
0dfa6c5e | 7386 | # |
19b63d8e | 7387 | #" |
65b1d8ea AK |
7388 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7389 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7390 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) | |
8cb66696 UW |
7391 | |
7392 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
7393 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7394 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7395 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 7396 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7397 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7398 | "@ | |
7399 | or\t%0,%2 | |
0dfa6c5e | 7400 | # |
19b63d8e | 7401 | #" |
9381e3f1 WG |
7402 | [(set_attr "op_type" "RR,SI,SS") |
7403 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7404 | |
7405 | (define_split | |
7406 | [(set (match_operand:HI 0 "s_operand" "") | |
7407 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7408 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7409 | "reload_completed" |
7410 | [(parallel | |
7411 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7412 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7413 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 7414 | |
9db1d521 | 7415 | ; |
4023fb28 | 7416 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
7417 | ; |
7418 | ||
8cb66696 | 7419 | (define_insn "*iorqi3_zarch" |
65b1d8ea AK |
7420 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7421 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7422 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7423 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7424 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7425 | "@ |
d40c829f | 7426 | or\t%0,%2 |
65b1d8ea | 7427 | ork\t%0,%1,%2 |
8cb66696 | 7428 | oill\t%0,%b2 |
fc0ea003 UW |
7429 | oi\t%S0,%b2 |
7430 | oiy\t%S0,%b2 | |
19b63d8e | 7431 | #" |
65b1d8ea AK |
7432 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
7433 | (set_attr "cpu_facility" "*,z196,*,*,*,*") | |
7434 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, | |
7435 | z10_super,z10_super,*")]) | |
8cb66696 UW |
7436 | |
7437 | (define_insn "*iorqi3_esa" | |
7438 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7439 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7440 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7441 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7442 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7443 | "@ |
8cb66696 | 7444 | or\t%0,%2 |
fc0ea003 | 7445 | oi\t%S0,%b2 |
19b63d8e | 7446 | #" |
9381e3f1 WG |
7447 | [(set_attr "op_type" "RR,SI,SS") |
7448 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 7449 | |
19b63d8e UW |
7450 | ; |
7451 | ; Block inclusive or (OC) patterns. | |
7452 | ; | |
7453 | ||
7454 | (define_insn "*oc" | |
7455 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7456 | (ior:BLK (match_dup 0) | |
7457 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7458 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7459 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7460 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7461 | "oc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7462 | [(set_attr "op_type" "SS") |
7463 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7464 | |
7465 | (define_split | |
7466 | [(set (match_operand 0 "memory_operand" "") | |
7467 | (ior (match_dup 0) | |
7468 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7469 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7470 | "reload_completed |
7471 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7472 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7473 | [(parallel | |
7474 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
7475 | (use (match_dup 2)) | |
ae156f85 | 7476 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7477 | { |
7478 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7479 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7480 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7481 | }) | |
7482 | ||
7483 | (define_peephole2 | |
7484 | [(parallel | |
7485 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7486 | (ior:BLK (match_dup 0) | |
7487 | (match_operand:BLK 1 "memory_operand" ""))) | |
7488 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7489 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7490 | (parallel |
7491 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7492 | (ior:BLK (match_dup 3) | |
7493 | (match_operand:BLK 4 "memory_operand" ""))) | |
7494 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7495 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7496 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7497 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7498 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7499 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7500 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7501 | [(parallel | |
7502 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
7503 | (use (match_dup 8)) | |
ae156f85 | 7504 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7505 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7506 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7507 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7508 | ||
9db1d521 HP |
7509 | |
7510 | ;; | |
7511 | ;;- Xor instructions. | |
7512 | ;; | |
7513 | ||
047d35ed AS |
7514 | (define_expand "xor<mode>3" |
7515 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7516 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7517 | (match_operand:INT 2 "general_operand" ""))) | |
7518 | (clobber (reg:CC CC_REGNUM))] | |
7519 | "" | |
7520 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
7521 | ||
3c91f126 AK |
7522 | ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing |
7523 | ; simplifications. So its better to have something matching. | |
7524 | (define_split | |
7525 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7526 | (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))] | |
7527 | "" | |
7528 | [(parallel | |
7529 | [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2))) | |
7530 | (clobber (reg:CC CC_REGNUM))])] | |
7531 | { | |
7532 | operands[2] = constm1_rtx; | |
7533 | if (!s390_logical_operator_ok_p (operands)) | |
7534 | FAIL; | |
7535 | }) | |
7536 | ||
9db1d521 HP |
7537 | ; |
7538 | ; xordi3 instruction pattern(s). | |
7539 | ; | |
7540 | ||
4023fb28 | 7541 | (define_insn "*xordi3_cc" |
ae156f85 | 7542 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7543 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
7544 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 7545 | (const_int 0))) |
65b1d8ea | 7546 | (set (match_operand:DI 0 "register_operand" "=d,d, d") |
4023fb28 | 7547 | (xor:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7548 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7549 | "@ |
d40c829f | 7550 | xgr\t%0,%2 |
65b1d8ea | 7551 | xgrk\t%0,%1,%2 |
d40c829f | 7552 | xg\t%0,%2" |
65b1d8ea | 7553 | [(set_attr "op_type" "RRE,RRF,RXY") |
5490de28 | 7554 | (set_attr "cpu_facility" "*,z196,*") |
65b1d8ea | 7555 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) |
4023fb28 UW |
7556 | |
7557 | (define_insn "*xordi3_cconly" | |
ae156f85 | 7558 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7559 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") |
7560 | (match_operand:DI 2 "general_operand" " d,d,RT")) | |
4023fb28 | 7561 | (const_int 0))) |
65b1d8ea | 7562 | (clobber (match_scratch:DI 0 "=d,d, d"))] |
9602b6a1 | 7563 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7564 | "@ |
d40c829f | 7565 | xgr\t%0,%2 |
65b1d8ea | 7566 | xgrk\t%0,%1,%2 |
c7fd8cd8 | 7567 | xg\t%0,%2" |
65b1d8ea AK |
7568 | [(set_attr "op_type" "RRE,RRF,RXY") |
7569 | (set_attr "cpu_facility" "*,z196,*") | |
7570 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7571 | |
3af8e996 | 7572 | (define_insn "*xordi3" |
65b1d8ea AK |
7573 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q") |
7574 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0") | |
7575 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) | |
ec24698e | 7576 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7577 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7578 | "@ |
7579 | xihf\t%0,%k2 | |
7580 | xilf\t%0,%k2 | |
7581 | xgr\t%0,%2 | |
65b1d8ea | 7582 | xgrk\t%0,%1,%2 |
ec24698e UW |
7583 | xg\t%0,%2 |
7584 | # | |
7585 | #" | |
65b1d8ea AK |
7586 | [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") |
7587 | (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") | |
7588 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, | |
7589 | *,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7590 | |
7591 | (define_split | |
7592 | [(set (match_operand:DI 0 "s_operand" "") | |
7593 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7594 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7595 | "reload_completed" |
7596 | [(parallel | |
7597 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7598 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7599 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 7600 | |
9db1d521 HP |
7601 | ; |
7602 | ; xorsi3 instruction pattern(s). | |
7603 | ; | |
7604 | ||
4023fb28 | 7605 | (define_insn "*xorsi3_cc" |
ae156f85 | 7606 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7607 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7608 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7609 | (const_int 0))) |
65b1d8ea | 7610 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7611 | (xor:SI (match_dup 1) (match_dup 2)))] |
7612 | "s390_match_ccmode(insn, CCTmode)" | |
7613 | "@ | |
ec24698e | 7614 | xilf\t%0,%o2 |
d40c829f | 7615 | xr\t%0,%2 |
65b1d8ea | 7616 | xrk\t%0,%1,%2 |
d40c829f UW |
7617 | x\t%0,%2 |
7618 | xy\t%0,%2" | |
65b1d8ea AK |
7619 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
7620 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7621 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
7622 | z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
7623 | |
7624 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 7625 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7626 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7627 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7628 | (const_int 0))) |
65b1d8ea | 7629 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7630 | "s390_match_ccmode(insn, CCTmode)" |
7631 | "@ | |
ec24698e | 7632 | xilf\t%0,%o2 |
d40c829f | 7633 | xr\t%0,%2 |
65b1d8ea | 7634 | xrk\t%0,%1,%2 |
d40c829f UW |
7635 | x\t%0,%2 |
7636 | xy\t%0,%2" | |
65b1d8ea AK |
7637 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
7638 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7639 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
7640 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 7641 | |
8cb66696 | 7642 | (define_insn "*xorsi3" |
65b1d8ea AK |
7643 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") |
7644 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") | |
7645 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7646 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7647 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 7648 | "@ |
ec24698e | 7649 | xilf\t%0,%o2 |
d40c829f | 7650 | xr\t%0,%2 |
65b1d8ea | 7651 | xrk\t%0,%1,%2 |
d40c829f | 7652 | x\t%0,%2 |
8cb66696 | 7653 | xy\t%0,%2 |
0dfa6c5e | 7654 | # |
19b63d8e | 7655 | #" |
65b1d8ea AK |
7656 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") |
7657 | (set_attr "cpu_facility" "*,*,z196,*,*,*,*") | |
7658 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, | |
7659 | z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7660 | |
7661 | (define_split | |
7662 | [(set (match_operand:SI 0 "s_operand" "") | |
7663 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7664 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7665 | "reload_completed" |
7666 | [(parallel | |
7667 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7668 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7669 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 7670 | |
9db1d521 HP |
7671 | ; |
7672 | ; xorhi3 instruction pattern(s). | |
7673 | ; | |
7674 | ||
8cb66696 | 7675 | (define_insn "*xorhi3" |
65b1d8ea AK |
7676 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7677 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") | |
7678 | (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) | |
ae156f85 | 7679 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7680 | "s390_logical_operator_ok_p (operands)" |
7681 | "@ | |
ec24698e | 7682 | xilf\t%0,%x2 |
8cb66696 | 7683 | xr\t%0,%2 |
65b1d8ea | 7684 | xrk\t%0,%1,%2 |
0dfa6c5e | 7685 | # |
19b63d8e | 7686 | #" |
65b1d8ea AK |
7687 | [(set_attr "op_type" "RIL,RR,RRF,SI,SS") |
7688 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
7689 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) | |
0dfa6c5e UW |
7690 | |
7691 | (define_split | |
7692 | [(set (match_operand:HI 0 "s_operand" "") | |
7693 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7694 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7695 | "reload_completed" |
7696 | [(parallel | |
7697 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7698 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7699 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 7700 | |
9db1d521 HP |
7701 | ; |
7702 | ; xorqi3 instruction pattern(s). | |
7703 | ; | |
7704 | ||
8cb66696 | 7705 | (define_insn "*xorqi3" |
65b1d8ea AK |
7706 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7707 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") | |
7708 | (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) | |
ae156f85 | 7709 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7710 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 7711 | "@ |
ec24698e | 7712 | xilf\t%0,%b2 |
8cb66696 | 7713 | xr\t%0,%2 |
65b1d8ea | 7714 | xrk\t%0,%1,%2 |
fc0ea003 UW |
7715 | xi\t%S0,%b2 |
7716 | xiy\t%S0,%b2 | |
19b63d8e | 7717 | #" |
65b1d8ea AK |
7718 | [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") |
7719 | (set_attr "cpu_facility" "*,*,z196,*,*,*") | |
7720 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) | |
9381e3f1 | 7721 | |
4023fb28 | 7722 | |
19b63d8e UW |
7723 | ; |
7724 | ; Block exclusive or (XC) patterns. | |
7725 | ; | |
7726 | ||
7727 | (define_insn "*xc" | |
7728 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7729 | (xor:BLK (match_dup 0) | |
7730 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7731 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7732 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7733 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7734 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 7735 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
7736 | |
7737 | (define_split | |
7738 | [(set (match_operand 0 "memory_operand" "") | |
7739 | (xor (match_dup 0) | |
7740 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7741 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7742 | "reload_completed |
7743 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7744 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7745 | [(parallel | |
7746 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
7747 | (use (match_dup 2)) | |
ae156f85 | 7748 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7749 | { |
7750 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7751 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7752 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7753 | }) | |
7754 | ||
7755 | (define_peephole2 | |
7756 | [(parallel | |
7757 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7758 | (xor:BLK (match_dup 0) | |
7759 | (match_operand:BLK 1 "memory_operand" ""))) | |
7760 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7761 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7762 | (parallel |
7763 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7764 | (xor:BLK (match_dup 3) | |
7765 | (match_operand:BLK 4 "memory_operand" ""))) | |
7766 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7767 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7768 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7769 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7770 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7771 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7772 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7773 | [(parallel | |
7774 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
7775 | (use (match_dup 8)) | |
ae156f85 | 7776 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7777 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7778 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7779 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7780 | ||
7781 | ; | |
7782 | ; Block xor (XC) patterns with src == dest. | |
7783 | ; | |
7784 | ||
7785 | (define_insn "*xc_zero" | |
7786 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7787 | (const_int 0)) | |
7788 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 7789 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7790 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 7791 | "xc\t%O0(%1,%R0),%S0" |
65b1d8ea AK |
7792 | [(set_attr "op_type" "SS") |
7793 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7794 | |
7795 | (define_peephole2 | |
7796 | [(parallel | |
7797 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7798 | (const_int 0)) | |
7799 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 7800 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7801 | (parallel |
7802 | [(set (match_operand:BLK 2 "memory_operand" "") | |
7803 | (const_int 0)) | |
7804 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 7805 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7806 | "s390_offset_p (operands[0], operands[2], operands[1]) |
7807 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
7808 | [(parallel | |
7809 | [(set (match_dup 4) (const_int 0)) | |
7810 | (use (match_dup 5)) | |
ae156f85 | 7811 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7812 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7813 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
7814 | ||
9db1d521 HP |
7815 | |
7816 | ;; | |
7817 | ;;- Negate instructions. | |
7818 | ;; | |
7819 | ||
7820 | ; | |
9a91a21f | 7821 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
7822 | ; |
7823 | ||
9a91a21f | 7824 | (define_expand "neg<mode>2" |
9db1d521 | 7825 | [(parallel |
9a91a21f AS |
7826 | [(set (match_operand:DSI 0 "register_operand" "=d") |
7827 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 7828 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7829 | "" |
7830 | "") | |
7831 | ||
26a89301 | 7832 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 7833 | [(set (reg CC_REGNUM) |
26a89301 UW |
7834 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
7835 | (match_operand:SI 1 "register_operand" "d") 0) | |
7836 | (const_int 32)) (const_int 32))) | |
7837 | (const_int 0))) | |
7838 | (set (match_operand:DI 0 "register_operand" "=d") | |
7839 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 7840 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 7841 | "lcgfr\t%0,%1" |
729e750f WG |
7842 | [(set_attr "op_type" "RRE") |
7843 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 7844 | |
26a89301 UW |
7845 | (define_insn "*negdi2_sign" |
7846 | [(set (match_operand:DI 0 "register_operand" "=d") | |
7847 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 7848 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7849 | "TARGET_ZARCH" |
26a89301 | 7850 | "lcgfr\t%0,%1" |
729e750f WG |
7851 | [(set_attr "op_type" "RRE") |
7852 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 7853 | |
43a09b63 | 7854 | ; lcr, lcgr |
9a91a21f | 7855 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 7856 | [(set (reg CC_REGNUM) |
9a91a21f | 7857 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 7858 | (const_int 0))) |
9a91a21f AS |
7859 | (set (match_operand:GPR 0 "register_operand" "=d") |
7860 | (neg:GPR (match_dup 1)))] | |
7861 | "s390_match_ccmode (insn, CCAmode)" | |
7862 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
7863 | [(set_attr "op_type" "RR<E>") |
7864 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
7865 | |
7866 | ; lcr, lcgr | |
9a91a21f | 7867 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 7868 | [(set (reg CC_REGNUM) |
9a91a21f | 7869 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 7870 | (const_int 0))) |
9a91a21f AS |
7871 | (clobber (match_scratch:GPR 0 "=d"))] |
7872 | "s390_match_ccmode (insn, CCAmode)" | |
7873 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
7874 | [(set_attr "op_type" "RR<E>") |
7875 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
7876 | |
7877 | ; lcr, lcgr | |
9a91a21f AS |
7878 | (define_insn "*neg<mode>2" |
7879 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
7880 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 7881 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
7882 | "" |
7883 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
7884 | [(set_attr "op_type" "RR<E>") |
7885 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 7886 | |
b7d19263 | 7887 | (define_insn "*negdi2_31" |
9db1d521 HP |
7888 | [(set (match_operand:DI 0 "register_operand" "=d") |
7889 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 7890 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7891 | "!TARGET_ZARCH" |
b7d19263 AK |
7892 | "#") |
7893 | ||
7894 | ; Split a DImode NEG on 31bit into 2 SImode NEGs | |
7895 | ||
7896 | ; Doing the twos complement separately on the SImode parts does an | |
7897 | ; unwanted +1 on the high part which needs to be subtracted afterwards | |
7898 | ; ... unless the +1 on the low part created an overflow. | |
7899 | ||
7900 | (define_split | |
7901 | [(set (match_operand:DI 0 "register_operand" "") | |
7902 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
7903 | (clobber (reg:CC CC_REGNUM))] | |
7904 | "!TARGET_ZARCH | |
7905 | && (REGNO (operands[0]) == REGNO (operands[1]) | |
7906 | || s390_split_ok_p (operands[0], operands[1], DImode, 0)) | |
7907 | && reload_completed" | |
26a89301 UW |
7908 | [(parallel |
7909 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 7910 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 7911 | (parallel |
ae156f85 | 7912 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
7913 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
7914 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
7915 | (set (pc) | |
ae156f85 | 7916 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
7917 | (pc) |
7918 | (label_ref (match_dup 6)))) | |
7919 | (parallel | |
7920 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 7921 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
7922 | (match_dup 6)] |
7923 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
7924 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
7925 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
7926 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
7927 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 7928 | |
b7d19263 AK |
7929 | ; Like above but first make a copy of the low part of the src operand |
7930 | ; since it might overlap with the high part of the destination. | |
7931 | ||
7932 | (define_split | |
7933 | [(set (match_operand:DI 0 "register_operand" "") | |
7934 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
7935 | (clobber (reg:CC CC_REGNUM))] | |
7936 | "!TARGET_ZARCH | |
7937 | && s390_split_ok_p (operands[0], operands[1], DImode, 1) | |
7938 | && reload_completed" | |
7939 | [; Make a backup of op5 first | |
7940 | (set (match_dup 4) (match_dup 5)) | |
7941 | ; Setting op2 here might clobber op5 | |
7942 | (parallel | |
7943 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
7944 | (clobber (reg:CC CC_REGNUM))]) | |
7945 | (parallel | |
7946 | [(set (reg:CCAP CC_REGNUM) | |
7947 | (compare:CCAP (neg:SI (match_dup 4)) (const_int 0))) | |
7948 | (set (match_dup 4) (neg:SI (match_dup 4)))]) | |
7949 | (set (pc) | |
7950 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) | |
7951 | (pc) | |
7952 | (label_ref (match_dup 6)))) | |
7953 | (parallel | |
7954 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
7955 | (clobber (reg:CC CC_REGNUM))]) | |
7956 | (match_dup 6)] | |
7957 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
7958 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
7959 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
7960 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
7961 | operands[6] = gen_label_rtx ();") | |
7962 | ||
9db1d521 | 7963 | ; |
f5905b37 | 7964 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
7965 | ; |
7966 | ||
f5905b37 | 7967 | (define_expand "neg<mode>2" |
9db1d521 | 7968 | [(parallel |
7b6baae1 AK |
7969 | [(set (match_operand:BFP 0 "register_operand" "=f") |
7970 | (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 7971 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
7972 | "TARGET_HARD_FLOAT" |
7973 | "") | |
7974 | ||
43a09b63 | 7975 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 7976 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 7977 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7978 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
7979 | (match_operand:BFP 2 "const0_operand" ""))) | |
7980 | (set (match_operand:BFP 0 "register_operand" "=f") | |
7981 | (neg:BFP (match_dup 1)))] | |
142cd70f | 7982 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7983 | "lc<xde>br\t%0,%1" |
26a89301 | 7984 | [(set_attr "op_type" "RRE") |
f5905b37 | 7985 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
7986 | |
7987 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 7988 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 7989 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
7990 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
7991 | (match_operand:BFP 2 "const0_operand" ""))) | |
7992 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 7993 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 7994 | "lc<xde>br\t%0,%1" |
26a89301 | 7995 | [(set_attr "op_type" "RRE") |
f5905b37 | 7996 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 7997 | |
85dae55a AK |
7998 | ; lcdfr |
7999 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
8000 | [(set (match_operand:FP 0 "register_operand" "=f") |
8001 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8002 | "TARGET_DFP" |
85dae55a AK |
8003 | "lcdfr\t%0,%1" |
8004 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8005 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8006 | |
43a09b63 | 8007 | ; lcxbr, lcdbr, lcebr |
6e5b5de8 | 8008 | ; FIXME: wflcdb does not clobber cc |
f5905b37 | 8009 | (define_insn "*neg<mode>2" |
6e5b5de8 AK |
8010 | [(set (match_operand:BFP 0 "register_operand" "=f,<vf>") |
8011 | (neg:BFP (match_operand:BFP 1 "register_operand" "f,<vf>"))) | |
ae156f85 | 8012 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8013 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8014 | "@ |
8015 | lc<xde>br\t%0,%1 | |
8016 | wflcdb\t%0,%1" | |
8017 | [(set_attr "op_type" "RRE,VRR") | |
8018 | (set_attr "cpu_facility" "*,vec") | |
8019 | (set_attr "type" "fsimp<mode>,*")]) | |
9db1d521 | 8020 | |
9db1d521 HP |
8021 | |
8022 | ;; | |
8023 | ;;- Absolute value instructions. | |
8024 | ;; | |
8025 | ||
8026 | ; | |
9a91a21f | 8027 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
8028 | ; |
8029 | ||
26a89301 | 8030 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 8031 | [(set (reg CC_REGNUM) |
26a89301 UW |
8032 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8033 | (match_operand:SI 1 "register_operand" "d") 0) | |
8034 | (const_int 32)) (const_int 32))) | |
8035 | (const_int 0))) | |
8036 | (set (match_operand:DI 0 "register_operand" "=d") | |
8037 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8038 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8039 | "lpgfr\t%0,%1" |
729e750f WG |
8040 | [(set_attr "op_type" "RRE") |
8041 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
8042 | |
8043 | (define_insn "*absdi2_sign" | |
8044 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8045 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8046 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8047 | "TARGET_ZARCH" |
26a89301 | 8048 | "lpgfr\t%0,%1" |
729e750f WG |
8049 | [(set_attr "op_type" "RRE") |
8050 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8051 | |
43a09b63 | 8052 | ; lpr, lpgr |
9a91a21f | 8053 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8054 | [(set (reg CC_REGNUM) |
9a91a21f | 8055 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 8056 | (const_int 0))) |
9a91a21f AS |
8057 | (set (match_operand:GPR 0 "register_operand" "=d") |
8058 | (abs:GPR (match_dup 1)))] | |
26a89301 | 8059 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8060 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8061 | [(set_attr "op_type" "RR<E>") |
8062 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 8063 | |
9381e3f1 | 8064 | ; lpr, lpgr |
9a91a21f | 8065 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8066 | [(set (reg CC_REGNUM) |
9a91a21f | 8067 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8068 | (const_int 0))) |
9a91a21f | 8069 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8070 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8071 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8072 | [(set_attr "op_type" "RR<E>") |
8073 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8074 | |
8075 | ; lpr, lpgr | |
9a91a21f AS |
8076 | (define_insn "abs<mode>2" |
8077 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8078 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8079 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 8080 | "" |
9a91a21f | 8081 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8082 | [(set_attr "op_type" "RR<E>") |
8083 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 8084 | |
9db1d521 | 8085 | ; |
f5905b37 | 8086 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8087 | ; |
8088 | ||
f5905b37 | 8089 | (define_expand "abs<mode>2" |
9db1d521 | 8090 | [(parallel |
7b6baae1 AK |
8091 | [(set (match_operand:BFP 0 "register_operand" "=f") |
8092 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 8093 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8094 | "TARGET_HARD_FLOAT" |
8095 | "") | |
8096 | ||
43a09b63 | 8097 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 8098 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8099 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8100 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8101 | (match_operand:BFP 2 "const0_operand" ""))) | |
8102 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8103 | (abs:BFP (match_dup 1)))] | |
142cd70f | 8104 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8105 | "lp<xde>br\t%0,%1" |
26a89301 | 8106 | [(set_attr "op_type" "RRE") |
f5905b37 | 8107 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8108 | |
8109 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 8110 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8111 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8112 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8113 | (match_operand:BFP 2 "const0_operand" ""))) | |
8114 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8115 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8116 | "lp<xde>br\t%0,%1" |
26a89301 | 8117 | [(set_attr "op_type" "RRE") |
f5905b37 | 8118 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8119 | |
85dae55a AK |
8120 | ; lpdfr |
8121 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
8122 | [(set (match_operand:FP 0 "register_operand" "=f") |
8123 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8124 | "TARGET_DFP" |
85dae55a AK |
8125 | "lpdfr\t%0,%1" |
8126 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8127 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8128 | |
43a09b63 | 8129 | ; lpxbr, lpdbr, lpebr |
6e5b5de8 | 8130 | ; FIXME: wflpdb does not clobber cc |
f5905b37 | 8131 | (define_insn "*abs<mode>2" |
6e5b5de8 AK |
8132 | [(set (match_operand:BFP 0 "register_operand" "=f,<vf>") |
8133 | (abs:BFP (match_operand:BFP 1 "register_operand" "f,<vf>"))) | |
ae156f85 | 8134 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8135 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8136 | "@ |
8137 | lp<xde>br\t%0,%1 | |
8138 | wflpdb\t%0,%1" | |
8139 | [(set_attr "op_type" "RRE,VRR") | |
8140 | (set_attr "cpu_facility" "*,vec") | |
8141 | (set_attr "type" "fsimp<mode>,*")]) | |
9db1d521 | 8142 | |
9db1d521 | 8143 | |
3ef093a8 AK |
8144 | ;; |
8145 | ;;- Negated absolute value instructions | |
8146 | ;; | |
8147 | ||
8148 | ; | |
8149 | ; Integer | |
8150 | ; | |
8151 | ||
26a89301 | 8152 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 8153 | [(set (reg CC_REGNUM) |
26a89301 UW |
8154 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8155 | (match_operand:SI 1 "register_operand" "d") 0) | |
8156 | (const_int 32)) (const_int 32)))) | |
8157 | (const_int 0))) | |
8158 | (set (match_operand:DI 0 "register_operand" "=d") | |
8159 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
9602b6a1 | 8160 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8161 | "lngfr\t%0,%1" |
729e750f WG |
8162 | [(set_attr "op_type" "RRE") |
8163 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8164 | |
26a89301 UW |
8165 | (define_insn "*negabsdi2_sign" |
8166 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8167 | (neg:DI (abs:DI (sign_extend:DI | |
8168 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 8169 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8170 | "TARGET_ZARCH" |
26a89301 | 8171 | "lngfr\t%0,%1" |
729e750f WG |
8172 | [(set_attr "op_type" "RRE") |
8173 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 8174 | |
43a09b63 | 8175 | ; lnr, lngr |
9a91a21f | 8176 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8177 | [(set (reg CC_REGNUM) |
9a91a21f | 8178 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8179 | (const_int 0))) |
9a91a21f AS |
8180 | (set (match_operand:GPR 0 "register_operand" "=d") |
8181 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 8182 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8183 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8184 | [(set_attr "op_type" "RR<E>") |
8185 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8186 | |
8187 | ; lnr, lngr | |
9a91a21f | 8188 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8189 | [(set (reg CC_REGNUM) |
9a91a21f | 8190 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8191 | (const_int 0))) |
9a91a21f | 8192 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8193 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8194 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8195 | [(set_attr "op_type" "RR<E>") |
8196 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8197 | |
8198 | ; lnr, lngr | |
9a91a21f AS |
8199 | (define_insn "*negabs<mode>2" |
8200 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8201 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 8202 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 8203 | "" |
9a91a21f | 8204 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8205 | [(set_attr "op_type" "RR<E>") |
8206 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8207 | |
3ef093a8 AK |
8208 | ; |
8209 | ; Floating point | |
8210 | ; | |
8211 | ||
43a09b63 | 8212 | ; lnxbr, lndbr, lnebr |
f5905b37 | 8213 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8214 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8215 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8216 | (match_operand:BFP 2 "const0_operand" ""))) | |
8217 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8218 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 8219 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8220 | "ln<xde>br\t%0,%1" |
26a89301 | 8221 | [(set_attr "op_type" "RRE") |
f5905b37 | 8222 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8223 | |
8224 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 8225 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8226 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8227 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8228 | (match_operand:BFP 2 "const0_operand" ""))) | |
8229 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8230 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8231 | "ln<xde>br\t%0,%1" |
26a89301 | 8232 | [(set_attr "op_type" "RRE") |
f5905b37 | 8233 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8234 | |
85dae55a AK |
8235 | ; lndfr |
8236 | (define_insn "*negabs<mode>2_nocc" | |
609e7e80 AK |
8237 | [(set (match_operand:FP 0 "register_operand" "=f") |
8238 | (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 8239 | "TARGET_DFP" |
85dae55a AK |
8240 | "lndfr\t%0,%1" |
8241 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8242 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8243 | |
43a09b63 | 8244 | ; lnxbr, lndbr, lnebr |
6e5b5de8 | 8245 | ; FIXME: wflndb does not clobber cc |
f5905b37 | 8246 | (define_insn "*negabs<mode>2" |
6e5b5de8 AK |
8247 | [(set (match_operand:BFP 0 "register_operand" "=f,<vf>") |
8248 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,<vf>")))) | |
ae156f85 | 8249 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8250 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8251 | "@ |
8252 | ln<xde>br\t%0,%1 | |
8253 | wflndb\t%0,%1" | |
8254 | [(set_attr "op_type" "RRE,VRR") | |
8255 | (set_attr "cpu_facility" "*,vec") | |
8256 | (set_attr "type" "fsimp<mode>,*")]) | |
26a89301 | 8257 | |
4023fb28 UW |
8258 | ;; |
8259 | ;;- Square root instructions. | |
8260 | ;; | |
8261 | ||
8262 | ; | |
f5905b37 | 8263 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
8264 | ; |
8265 | ||
9381e3f1 | 8266 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 8267 | (define_insn "sqrt<mode>2" |
6e5b5de8 AK |
8268 | [(set (match_operand:BFP 0 "register_operand" "=f, f,<vf>") |
8269 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>,<vf>")))] | |
142cd70f | 8270 | "TARGET_HARD_FLOAT" |
4023fb28 | 8271 | "@ |
f61a2c7d | 8272 | sq<xde>br\t%0,%1 |
6e5b5de8 AK |
8273 | sq<xde>b\t%0,%1 |
8274 | wfsqdb\t%v0,%v1" | |
8275 | [(set_attr "op_type" "RRE,RXE,VRR") | |
8276 | (set_attr "type" "fsqrt<mode>") | |
8277 | (set_attr "cpu_facility" "*,*,vec")]) | |
4023fb28 | 8278 | |
9db1d521 HP |
8279 | |
8280 | ;; | |
8281 | ;;- One complement instructions. | |
8282 | ;; | |
8283 | ||
8284 | ; | |
342cf42b | 8285 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 8286 | ; |
c7453384 | 8287 | |
342cf42b | 8288 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 8289 | [(parallel |
342cf42b AS |
8290 | [(set (match_operand:INT 0 "register_operand" "") |
8291 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
8292 | (const_int -1))) | |
ae156f85 | 8293 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 8294 | "" |
4023fb28 | 8295 | "") |
9db1d521 HP |
8296 | |
8297 | ||
ec24698e UW |
8298 | ;; |
8299 | ;; Find leftmost bit instructions. | |
8300 | ;; | |
8301 | ||
8302 | (define_expand "clzdi2" | |
8303 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8304 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 8305 | "TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
8306 | { |
8307 | rtx insn, clz_equal; | |
8308 | rtx wide_reg = gen_reg_rtx (TImode); | |
8309 | rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63); | |
8310 | ||
8311 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
8312 | ||
8313 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
8314 | ||
9381e3f1 | 8315 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 8316 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
8317 | |
8318 | DONE; | |
8319 | }) | |
8320 | ||
8321 | (define_insn "clztidi2" | |
8322 | [(set (match_operand:TI 0 "register_operand" "=d") | |
8323 | (ior:TI | |
9381e3f1 WG |
8324 | (ashift:TI |
8325 | (zero_extend:TI | |
ec24698e UW |
8326 | (xor:DI (match_operand:DI 1 "register_operand" "d") |
8327 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
8328 | (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
9381e3f1 | 8329 | |
ec24698e UW |
8330 | (const_int 64)) |
8331 | (zero_extend:TI (clz:DI (match_dup 1))))) | |
8332 | (clobber (reg:CC CC_REGNUM))] | |
9381e3f1 | 8333 | "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) |
ec24698e | 8334 | == (unsigned HOST_WIDE_INT) 1 << 63 |
9602b6a1 | 8335 | && TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
8336 | "flogr\t%0,%1" |
8337 | [(set_attr "op_type" "RRE")]) | |
8338 | ||
8339 | ||
9db1d521 HP |
8340 | ;; |
8341 | ;;- Rotate instructions. | |
8342 | ;; | |
8343 | ||
8344 | ; | |
9a91a21f | 8345 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
8346 | ; |
8347 | ||
43a09b63 | 8348 | ; rll, rllg |
9a91a21f AS |
8349 | (define_insn "rotl<mode>3" |
8350 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8351 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
4989e88a | 8352 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9e8327e3 | 8353 | "TARGET_CPU_ZARCH" |
9a91a21f | 8354 | "rll<g>\t%0,%1,%Y2" |
077dab3b | 8355 | [(set_attr "op_type" "RSE") |
9381e3f1 WG |
8356 | (set_attr "atype" "reg") |
8357 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 8358 | |
43a09b63 | 8359 | ; rll, rllg |
4989e88a AK |
8360 | (define_insn "*rotl<mode>3_and" |
8361 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8362 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
8363 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
8364 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
8365 | "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63" | |
8366 | "rll<g>\t%0,%1,%Y2" | |
8367 | [(set_attr "op_type" "RSE") | |
9381e3f1 WG |
8368 | (set_attr "atype" "reg") |
8369 | (set_attr "z10prop" "z10_super_E1")]) | |
4989e88a | 8370 | |
9db1d521 HP |
8371 | |
8372 | ;; | |
f337b930 | 8373 | ;;- Shift instructions. |
9db1d521 | 8374 | ;; |
9db1d521 HP |
8375 | |
8376 | ; | |
1b48c8cc | 8377 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
65b1d8ea | 8378 | ; Left shifts and logical right shifts |
9db1d521 | 8379 | |
1b48c8cc AS |
8380 | (define_expand "<shift><mode>3" |
8381 | [(set (match_operand:DSI 0 "register_operand" "") | |
8382 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
8383 | (match_operand:SI 2 "shift_count_or_setmem_operand" "")))] | |
9db1d521 HP |
8384 | "" |
8385 | "") | |
8386 | ||
43a09b63 | 8387 | ; sldl, srdl |
f337b930 | 8388 | (define_insn "*<shift>di3_31" |
ac32b25e | 8389 | [(set (match_operand:DI 0 "register_operand" "=d") |
f337b930 | 8390 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 8391 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] |
9602b6a1 | 8392 | "!TARGET_ZARCH" |
f337b930 | 8393 | "s<lr>dl\t%0,%Y2" |
077dab3b | 8394 | [(set_attr "op_type" "RS") |
65b1d8ea AK |
8395 | (set_attr "atype" "reg") |
8396 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8397 | |
65b1d8ea | 8398 | ; sll, srl, sllg, srlg, sllk, srlk |
1b48c8cc | 8399 | (define_insn "*<shift><mode>3" |
65b1d8ea AK |
8400 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
8401 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
8402 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))] | |
1b48c8cc | 8403 | "" |
65b1d8ea AK |
8404 | "@ |
8405 | s<lr>l<g>\t%0,<1>%Y2 | |
8406 | s<lr>l<gk>\t%0,%1,%Y2" | |
8407 | [(set_attr "op_type" "RS<E>,RSY") | |
8408 | (set_attr "atype" "reg,reg") | |
8409 | (set_attr "cpu_facility" "*,z196") | |
8410 | (set_attr "z10prop" "z10_super_E1,*")]) | |
9db1d521 | 8411 | |
43a09b63 | 8412 | ; sldl, srdl |
4989e88a AK |
8413 | (define_insn "*<shift>di3_31_and" |
8414 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8415 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
8416 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
8417 | (match_operand:SI 3 "const_int_operand" "n"))))] | |
9602b6a1 | 8418 | "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" |
4989e88a AK |
8419 | "s<lr>dl\t%0,%Y2" |
8420 | [(set_attr "op_type" "RS") | |
8421 | (set_attr "atype" "reg")]) | |
8422 | ||
65b1d8ea | 8423 | ; sll, srl, sllg, srlg, sllk, srlk |
1b48c8cc | 8424 | (define_insn "*<shift><mode>3_and" |
65b1d8ea AK |
8425 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
8426 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
8427 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
8428 | (match_operand:SI 3 "const_int_operand" "n,n"))))] | |
1b48c8cc | 8429 | "(INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
8430 | "@ |
8431 | s<lr>l<g>\t%0,<1>%Y2 | |
8432 | s<lr>l<gk>\t%0,%1,%Y2" | |
8433 | [(set_attr "op_type" "RS<E>,RSY") | |
8434 | (set_attr "atype" "reg,reg") | |
8435 | (set_attr "cpu_facility" "*,z196") | |
8436 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 8437 | |
9db1d521 | 8438 | ; |
1b48c8cc | 8439 | ; ashr(di|si)3 instruction pattern(s). |
65b1d8ea | 8440 | ; Arithmetic right shifts |
9db1d521 | 8441 | |
1b48c8cc | 8442 | (define_expand "ashr<mode>3" |
9db1d521 | 8443 | [(parallel |
1b48c8cc AS |
8444 | [(set (match_operand:DSI 0 "register_operand" "") |
8445 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
8446 | (match_operand:SI 2 "shift_count_or_setmem_operand" ""))) | |
ae156f85 | 8447 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8448 | "" |
8449 | "") | |
8450 | ||
ecbe845e | 8451 | (define_insn "*ashrdi3_cc_31" |
ae156f85 | 8452 | [(set (reg CC_REGNUM) |
ac32b25e | 8453 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 8454 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 8455 | (const_int 0))) |
ac32b25e | 8456 | (set (match_operand:DI 0 "register_operand" "=d") |
ecbe845e | 8457 | (ashiftrt:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 8458 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 8459 | "srda\t%0,%Y2" |
077dab3b HP |
8460 | [(set_attr "op_type" "RS") |
8461 | (set_attr "atype" "reg")]) | |
ecbe845e UW |
8462 | |
8463 | (define_insn "*ashrdi3_cconly_31" | |
ae156f85 | 8464 | [(set (reg CC_REGNUM) |
ac32b25e | 8465 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") |
4989e88a | 8466 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) |
ecbe845e | 8467 | (const_int 0))) |
ac32b25e | 8468 | (clobber (match_scratch:DI 0 "=d"))] |
9602b6a1 | 8469 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" |
ac32b25e | 8470 | "srda\t%0,%Y2" |
077dab3b HP |
8471 | [(set_attr "op_type" "RS") |
8472 | (set_attr "atype" "reg")]) | |
ecbe845e | 8473 | |
9db1d521 | 8474 | (define_insn "*ashrdi3_31" |
ac32b25e UW |
8475 | [(set (match_operand:DI 0 "register_operand" "=d") |
8476 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
4989e88a | 8477 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) |
ae156f85 | 8478 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8479 | "!TARGET_ZARCH" |
ac32b25e | 8480 | "srda\t%0,%Y2" |
077dab3b HP |
8481 | [(set_attr "op_type" "RS") |
8482 | (set_attr "atype" "reg")]) | |
c7453384 | 8483 | |
65b1d8ea | 8484 | ; sra, srag, srak |
1b48c8cc | 8485 | (define_insn "*ashr<mode>3_cc" |
ae156f85 | 8486 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8487 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
8488 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) | |
ecbe845e | 8489 | (const_int 0))) |
65b1d8ea | 8490 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
1b48c8cc AS |
8491 | (ashiftrt:GPR (match_dup 1) (match_dup 2)))] |
8492 | "s390_match_ccmode(insn, CCSmode)" | |
65b1d8ea AK |
8493 | "@ |
8494 | sra<g>\t%0,<1>%Y2 | |
8495 | sra<gk>\t%0,%1,%Y2" | |
8496 | [(set_attr "op_type" "RS<E>,RSY") | |
8497 | (set_attr "atype" "reg,reg") | |
8498 | (set_attr "cpu_facility" "*,z196") | |
8499 | (set_attr "z10prop" "z10_super_E1,*")]) | |
ecbe845e | 8500 | |
65b1d8ea | 8501 | ; sra, srag, srak |
1b48c8cc | 8502 | (define_insn "*ashr<mode>3_cconly" |
ae156f85 | 8503 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8504 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
8505 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) | |
ecbe845e | 8506 | (const_int 0))) |
65b1d8ea | 8507 | (clobber (match_scratch:GPR 0 "=d,d"))] |
1b48c8cc | 8508 | "s390_match_ccmode(insn, CCSmode)" |
65b1d8ea AK |
8509 | "@ |
8510 | sra<g>\t%0,<1>%Y2 | |
8511 | sra<gk>\t%0,%1,%Y2" | |
8512 | [(set_attr "op_type" "RS<E>,RSY") | |
8513 | (set_attr "atype" "reg,reg") | |
8514 | (set_attr "cpu_facility" "*,z196") | |
8515 | (set_attr "z10prop" "z10_super_E1,*")]) | |
ecbe845e | 8516 | |
43a09b63 | 8517 | ; sra, srag |
1b48c8cc | 8518 | (define_insn "*ashr<mode>3" |
65b1d8ea AK |
8519 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
8520 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
8521 | (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))) | |
ae156f85 | 8522 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc | 8523 | "" |
65b1d8ea AK |
8524 | "@ |
8525 | sra<g>\t%0,<1>%Y2 | |
8526 | sra<gk>\t%0,%1,%Y2" | |
8527 | [(set_attr "op_type" "RS<E>,RSY") | |
8528 | (set_attr "atype" "reg,reg") | |
8529 | (set_attr "cpu_facility" "*,z196") | |
8530 | (set_attr "z10prop" "z10_super_E1,*")]) | |
077dab3b | 8531 | |
9db1d521 | 8532 | |
4989e88a AK |
8533 | ; shift pattern with implicit ANDs |
8534 | ||
8535 | (define_insn "*ashrdi3_cc_31_and" | |
8536 | [(set (reg CC_REGNUM) | |
8537 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
8538 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
8539 | (match_operand:SI 3 "const_int_operand" "n"))) | |
8540 | (const_int 0))) | |
8541 | (set (match_operand:DI 0 "register_operand" "=d") | |
8542 | (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] | |
9602b6a1 | 8543 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) |
4989e88a AK |
8544 | && (INTVAL (operands[3]) & 63) == 63" |
8545 | "srda\t%0,%Y2" | |
8546 | [(set_attr "op_type" "RS") | |
8547 | (set_attr "atype" "reg")]) | |
8548 | ||
8549 | (define_insn "*ashrdi3_cconly_31_and" | |
8550 | [(set (reg CC_REGNUM) | |
8551 | (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
8552 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
8553 | (match_operand:SI 3 "const_int_operand" "n"))) | |
8554 | (const_int 0))) | |
8555 | (clobber (match_scratch:DI 0 "=d"))] | |
9602b6a1 | 8556 | "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) |
4989e88a AK |
8557 | && (INTVAL (operands[3]) & 63) == 63" |
8558 | "srda\t%0,%Y2" | |
8559 | [(set_attr "op_type" "RS") | |
8560 | (set_attr "atype" "reg")]) | |
8561 | ||
8562 | (define_insn "*ashrdi3_31_and" | |
8563 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8564 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") | |
8565 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") | |
8566 | (match_operand:SI 3 "const_int_operand" "n")))) | |
8567 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8568 | "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" |
4989e88a AK |
8569 | "srda\t%0,%Y2" |
8570 | [(set_attr "op_type" "RS") | |
8571 | (set_attr "atype" "reg")]) | |
8572 | ||
65b1d8ea | 8573 | ; sra, srag, srak |
1b48c8cc | 8574 | (define_insn "*ashr<mode>3_cc_and" |
4989e88a | 8575 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8576 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
8577 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
8578 | (match_operand:SI 3 "const_int_operand" "n,n"))) | |
4989e88a | 8579 | (const_int 0))) |
65b1d8ea | 8580 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
1b48c8cc | 8581 | (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] |
4989e88a | 8582 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
8583 | "@ |
8584 | sra<g>\t%0,<1>%Y2 | |
8585 | sra<gk>\t%0,%1,%Y2" | |
8586 | [(set_attr "op_type" "RS<E>,RSY") | |
8587 | (set_attr "atype" "reg,reg") | |
8588 | (set_attr "cpu_facility" "*,z196") | |
8589 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 8590 | |
65b1d8ea | 8591 | ; sra, srag, srak |
1b48c8cc | 8592 | (define_insn "*ashr<mode>3_cconly_and" |
4989e88a | 8593 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8594 | (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") |
8595 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
8596 | (match_operand:SI 3 "const_int_operand" "n,n"))) | |
4989e88a | 8597 | (const_int 0))) |
65b1d8ea | 8598 | (clobber (match_scratch:GPR 0 "=d,d"))] |
4989e88a | 8599 | "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" |
65b1d8ea AK |
8600 | "@ |
8601 | sra<g>\t%0,<1>%Y2 | |
8602 | sra<gk>\t%0,%1,%Y2" | |
8603 | [(set_attr "op_type" "RS<E>,RSY") | |
8604 | (set_attr "atype" "reg,reg") | |
8605 | (set_attr "cpu_facility" "*,z196") | |
8606 | (set_attr "z10prop" "z10_super_E1,*")]) | |
4989e88a | 8607 | |
65b1d8ea | 8608 | ; sra, srag, srak |
1b48c8cc | 8609 | (define_insn "*ashr<mode>3_and" |
65b1d8ea AK |
8610 | [(set (match_operand:GPR 0 "register_operand" "=d,d") |
8611 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") | |
8612 | (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") | |
8613 | (match_operand:SI 3 "const_int_operand" "n,n")))) | |
4989e88a AK |
8614 | (clobber (reg:CC CC_REGNUM))] |
8615 | "(INTVAL (operands[3]) & 63) == 63" | |
65b1d8ea AK |
8616 | "@ |
8617 | sra<g>\t%0,<1>%Y2 | |
8618 | sra<gk>\t%0,%1,%Y2" | |
8619 | [(set_attr "op_type" "RS<E>,RSY") | |
8620 | (set_attr "atype" "reg,reg") | |
01496eca | 8621 | (set_attr "cpu_facility" "*,z196") |
65b1d8ea | 8622 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8623 | |
9db1d521 | 8624 | |
9db1d521 HP |
8625 | ;; |
8626 | ;; Branch instruction patterns. | |
8627 | ;; | |
8628 | ||
f90b7a5a | 8629 | (define_expand "cbranch<mode>4" |
fa77b251 | 8630 | [(set (pc) |
f90b7a5a PB |
8631 | (if_then_else (match_operator 0 "comparison_operator" |
8632 | [(match_operand:GPR 1 "register_operand" "") | |
8633 | (match_operand:GPR 2 "general_operand" "")]) | |
8634 | (label_ref (match_operand 3 "" "")) | |
fa77b251 | 8635 | (pc)))] |
ba956982 | 8636 | "" |
f90b7a5a PB |
8637 | "s390_emit_jump (operands[3], |
8638 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8639 | DONE;") | |
8640 | ||
8641 | (define_expand "cbranch<mode>4" | |
8642 | [(set (pc) | |
8643 | (if_then_else (match_operator 0 "comparison_operator" | |
8644 | [(match_operand:FP 1 "register_operand" "") | |
8645 | (match_operand:FP 2 "general_operand" "")]) | |
8646 | (label_ref (match_operand 3 "" "")) | |
8647 | (pc)))] | |
8648 | "TARGET_HARD_FLOAT" | |
8649 | "s390_emit_jump (operands[3], | |
8650 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8651 | DONE;") | |
8652 | ||
8653 | (define_expand "cbranchcc4" | |
8654 | [(set (pc) | |
de6fba39 | 8655 | (if_then_else (match_operator 0 "s390_comparison" |
f90b7a5a | 8656 | [(match_operand 1 "cc_reg_operand" "") |
de6fba39 | 8657 | (match_operand 2 "const_int_operand" "")]) |
f90b7a5a PB |
8658 | (label_ref (match_operand 3 "" "")) |
8659 | (pc)))] | |
de6fba39 UW |
8660 | "" |
8661 | "") | |
ba956982 | 8662 | |
9db1d521 HP |
8663 | |
8664 | ;; | |
8665 | ;;- Conditional jump instructions. | |
8666 | ;; | |
8667 | ||
6590e19a UW |
8668 | (define_insn "*cjump_64" |
8669 | [(set (pc) | |
8670 | (if_then_else | |
5a3fe9b6 AK |
8671 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
8672 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
8673 | (label_ref (match_operand 0 "" "")) |
8674 | (pc)))] | |
8675 | "TARGET_CPU_ZARCH" | |
9db1d521 | 8676 | { |
13e58269 | 8677 | if (get_attr_length (insn) == 4) |
d40c829f | 8678 | return "j%C1\t%l0"; |
6590e19a | 8679 | else |
d40c829f | 8680 | return "jg%C1\t%l0"; |
6590e19a UW |
8681 | } |
8682 | [(set_attr "op_type" "RI") | |
8683 | (set_attr "type" "branch") | |
8684 | (set (attr "length") | |
8685 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8686 | (const_int 4) (const_int 6)))]) | |
8687 | ||
8688 | (define_insn "*cjump_31" | |
8689 | [(set (pc) | |
8690 | (if_then_else | |
5a3fe9b6 AK |
8691 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
8692 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
8693 | (label_ref (match_operand 0 "" "")) |
8694 | (pc)))] | |
8695 | "!TARGET_CPU_ZARCH" | |
8696 | { | |
8d933e31 AS |
8697 | gcc_assert (get_attr_length (insn) == 4); |
8698 | return "j%C1\t%l0"; | |
10bbf137 | 8699 | } |
9db1d521 | 8700 | [(set_attr "op_type" "RI") |
077dab3b | 8701 | (set_attr "type" "branch") |
13e58269 | 8702 | (set (attr "length") |
d7f99b2c | 8703 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8704 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8705 | (const_int 4) (const_int 6)) | |
8706 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8707 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 8708 | |
f314b9b1 | 8709 | (define_insn "*cjump_long" |
6590e19a UW |
8710 | [(set (pc) |
8711 | (if_then_else | |
ae156f85 | 8712 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4fe6dea8 | 8713 | (match_operand 0 "address_operand" "ZQZR") |
6590e19a | 8714 | (pc)))] |
9db1d521 | 8715 | "" |
f314b9b1 UW |
8716 | { |
8717 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8718 | return "b%C1r\t%0"; |
f314b9b1 | 8719 | else |
d40c829f | 8720 | return "b%C1\t%a0"; |
10bbf137 | 8721 | } |
c7453384 | 8722 | [(set (attr "op_type") |
f314b9b1 UW |
8723 | (if_then_else (match_operand 0 "register_operand" "") |
8724 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 8725 | (set_attr "type" "branch") |
077dab3b | 8726 | (set_attr "atype" "agen")]) |
9db1d521 | 8727 | |
177bc204 RS |
8728 | ;; A conditional return instruction. |
8729 | (define_insn "*c<code>" | |
8730 | [(set (pc) | |
8731 | (if_then_else | |
8732 | (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
8733 | (ANY_RETURN) | |
8734 | (pc)))] | |
8735 | "s390_can_use_<code>_insn ()" | |
8736 | "b%C0r\t%%r14" | |
8737 | [(set_attr "op_type" "RR") | |
8738 | (set_attr "type" "jsr") | |
8739 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
8740 | |
8741 | ;; | |
8742 | ;;- Negated conditional jump instructions. | |
8743 | ;; | |
8744 | ||
6590e19a UW |
8745 | (define_insn "*icjump_64" |
8746 | [(set (pc) | |
8747 | (if_then_else | |
ae156f85 | 8748 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
8749 | (pc) |
8750 | (label_ref (match_operand 0 "" ""))))] | |
8751 | "TARGET_CPU_ZARCH" | |
c7453384 | 8752 | { |
13e58269 | 8753 | if (get_attr_length (insn) == 4) |
d40c829f | 8754 | return "j%D1\t%l0"; |
6590e19a | 8755 | else |
d40c829f | 8756 | return "jg%D1\t%l0"; |
6590e19a UW |
8757 | } |
8758 | [(set_attr "op_type" "RI") | |
8759 | (set_attr "type" "branch") | |
8760 | (set (attr "length") | |
8761 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8762 | (const_int 4) (const_int 6)))]) | |
8763 | ||
8764 | (define_insn "*icjump_31" | |
8765 | [(set (pc) | |
8766 | (if_then_else | |
ae156f85 | 8767 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
8768 | (pc) |
8769 | (label_ref (match_operand 0 "" ""))))] | |
8770 | "!TARGET_CPU_ZARCH" | |
8771 | { | |
8d933e31 AS |
8772 | gcc_assert (get_attr_length (insn) == 4); |
8773 | return "j%D1\t%l0"; | |
10bbf137 | 8774 | } |
9db1d521 | 8775 | [(set_attr "op_type" "RI") |
077dab3b | 8776 | (set_attr "type" "branch") |
13e58269 | 8777 | (set (attr "length") |
d7f99b2c | 8778 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8779 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8780 | (const_int 4) (const_int 6)) | |
8781 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8782 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 8783 | |
f314b9b1 | 8784 | (define_insn "*icjump_long" |
6590e19a UW |
8785 | [(set (pc) |
8786 | (if_then_else | |
ae156f85 | 8787 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a | 8788 | (pc) |
4fe6dea8 | 8789 | (match_operand 0 "address_operand" "ZQZR")))] |
9db1d521 | 8790 | "" |
f314b9b1 UW |
8791 | { |
8792 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8793 | return "b%D1r\t%0"; |
f314b9b1 | 8794 | else |
d40c829f | 8795 | return "b%D1\t%a0"; |
10bbf137 | 8796 | } |
c7453384 | 8797 | [(set (attr "op_type") |
f314b9b1 UW |
8798 | (if_then_else (match_operand 0 "register_operand" "") |
8799 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
8800 | (set_attr "type" "branch") |
8801 | (set_attr "atype" "agen")]) | |
9db1d521 | 8802 | |
4456530d HP |
8803 | ;; |
8804 | ;;- Trap instructions. | |
8805 | ;; | |
8806 | ||
8807 | (define_insn "trap" | |
8808 | [(trap_if (const_int 1) (const_int 0))] | |
8809 | "" | |
d40c829f | 8810 | "j\t.+2" |
6590e19a | 8811 | [(set_attr "op_type" "RI") |
077dab3b | 8812 | (set_attr "type" "branch")]) |
4456530d | 8813 | |
f90b7a5a PB |
8814 | (define_expand "ctrap<mode>4" |
8815 | [(trap_if (match_operator 0 "comparison_operator" | |
8816 | [(match_operand:GPR 1 "register_operand" "") | |
8817 | (match_operand:GPR 2 "general_operand" "")]) | |
8818 | (match_operand 3 "const0_operand" ""))] | |
4456530d | 8819 | "" |
f90b7a5a PB |
8820 | { |
8821 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
8822 | operands[1], operands[2]); | |
8823 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
8824 | DONE; | |
8825 | }) | |
8826 | ||
8827 | (define_expand "ctrap<mode>4" | |
8828 | [(trap_if (match_operator 0 "comparison_operator" | |
8829 | [(match_operand:FP 1 "register_operand" "") | |
8830 | (match_operand:FP 2 "general_operand" "")]) | |
8831 | (match_operand 3 "const0_operand" ""))] | |
8832 | "" | |
8833 | { | |
8834 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
8835 | operands[1], operands[2]); | |
8836 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
8837 | DONE; | |
8838 | }) | |
4456530d | 8839 | |
f90b7a5a PB |
8840 | (define_insn "condtrap" |
8841 | [(trap_if (match_operator 0 "s390_comparison" | |
8842 | [(match_operand 1 "cc_reg_operand" "c") | |
8843 | (const_int 0)]) | |
4456530d HP |
8844 | (const_int 0))] |
8845 | "" | |
d40c829f | 8846 | "j%C0\t.+2"; |
077dab3b HP |
8847 | [(set_attr "op_type" "RI") |
8848 | (set_attr "type" "branch")]) | |
9db1d521 | 8849 | |
963fc8d0 AK |
8850 | ; crt, cgrt, cit, cgit |
8851 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
8852 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
8853 | [(match_operand:GPR 1 "register_operand" "d,d") | |
8854 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
8855 | (const_int 0))] | |
8856 | "TARGET_Z10" | |
8857 | "@ | |
8858 | c<g>rt%C0\t%1,%2 | |
8859 | c<g>it%C0\t%1,%h2" | |
8860 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 8861 | (set_attr "type" "branch") |
729e750f | 8862 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 8863 | |
22ac2c2f | 8864 | ; clrt, clgrt, clfit, clgit, clt, clgt |
963fc8d0 AK |
8865 | (define_insn "*cmp_and_trap_unsigned_int<mode>" |
8866 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
22ac2c2f AK |
8867 | [(match_operand:GPR 1 "register_operand" "d,d, d") |
8868 | (match_operand:GPR 2 "general_operand" "d,D,RT")]) | |
963fc8d0 AK |
8869 | (const_int 0))] |
8870 | "TARGET_Z10" | |
8871 | "@ | |
8872 | cl<g>rt%C0\t%1,%2 | |
22ac2c2f AK |
8873 | cl<gf>it%C0\t%1,%x2 |
8874 | cl<g>t%C0\t%1,%2" | |
8875 | [(set_attr "op_type" "RRF,RIE,RSY") | |
8876 | (set_attr "type" "branch") | |
8877 | (set_attr "z10prop" "z10_super_c,z10_super,*") | |
8878 | (set_attr "cpu_facility" "z10,z10,zEC12")]) | |
8879 | ||
8880 | ; lat, lgat | |
8881 | (define_insn "*load_and_trap<mode>" | |
8882 | [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT") | |
8883 | (const_int 0)) | |
8884 | (const_int 0)) | |
8885 | (set (match_operand:GPR 1 "register_operand" "=d") | |
8886 | (match_dup 0))] | |
8887 | "TARGET_ZEC12" | |
8888 | "l<g>at\t%1,%0" | |
8889 | [(set_attr "op_type" "RXY")]) | |
8890 | ||
963fc8d0 | 8891 | |
9db1d521 | 8892 | ;; |
0a3bdf9d | 8893 | ;;- Loop instructions. |
9db1d521 | 8894 | ;; |
0a3bdf9d UW |
8895 | ;; This is all complicated by the fact that since this is a jump insn |
8896 | ;; we must handle our own output reloads. | |
c7453384 | 8897 | |
f1149235 AK |
8898 | ;; branch on index |
8899 | ||
8900 | ; This splitter will be matched by combine and has to add the 2 moves | |
8901 | ; necessary to load the compare and the increment values into a | |
8902 | ; register pair as needed by brxle. | |
8903 | ||
8904 | (define_insn_and_split "*brx_stage1_<GPR:mode>" | |
8905 | [(set (pc) | |
8906 | (if_then_else | |
8907 | (match_operator 6 "s390_brx_operator" | |
8908 | [(plus:GPR (match_operand:GPR 1 "register_operand" "") | |
8909 | (match_operand:GPR 2 "general_operand" "")) | |
8910 | (match_operand:GPR 3 "register_operand" "")]) | |
8911 | (label_ref (match_operand 0 "" "")) | |
8912 | (pc))) | |
8913 | (set (match_operand:GPR 4 "nonimmediate_operand" "") | |
8914 | (plus:GPR (match_dup 1) (match_dup 2))) | |
8915 | (clobber (match_scratch:GPR 5 ""))] | |
8916 | "TARGET_CPU_ZARCH" | |
8917 | "#" | |
8918 | "!reload_completed && !reload_in_progress" | |
8919 | [(set (match_dup 7) (match_dup 2)) ; the increment | |
8920 | (set (match_dup 8) (match_dup 3)) ; the comparison value | |
8921 | (parallel [(set (pc) | |
8922 | (if_then_else | |
8923 | (match_op_dup 6 | |
8924 | [(plus:GPR (match_dup 1) (match_dup 7)) | |
8925 | (match_dup 8)]) | |
8926 | (label_ref (match_dup 0)) | |
8927 | (pc))) | |
8928 | (set (match_dup 4) | |
8929 | (plus:GPR (match_dup 1) (match_dup 7))) | |
8930 | (clobber (match_dup 5)) | |
8931 | (clobber (reg:CC CC_REGNUM))])] | |
8932 | { | |
8933 | rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); | |
8934 | operands[7] = gen_lowpart (<GPR:MODE>mode, | |
8935 | gen_highpart (word_mode, dreg)); | |
8936 | operands[8] = gen_lowpart (<GPR:MODE>mode, | |
8937 | gen_lowpart (word_mode, dreg)); | |
8938 | }) | |
8939 | ||
8940 | ; brxlg, brxhg | |
8941 | ||
8942 | (define_insn_and_split "*brxg_64bit" | |
8943 | [(set (pc) | |
8944 | (if_then_else | |
8945 | (match_operator 5 "s390_brx_operator" | |
8946 | [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") | |
8947 | (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) | |
8948 | (subreg:DI (match_dup 2) 8)]) | |
8949 | (label_ref (match_operand 0 "" "")) | |
8950 | (pc))) | |
8951 | (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") | |
8952 | (plus:DI (match_dup 1) | |
8953 | (subreg:DI (match_dup 2) 0))) | |
8954 | (clobber (match_scratch:DI 4 "=X,&1,&?d")) | |
8955 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8956 | "TARGET_ZARCH" |
f1149235 AK |
8957 | { |
8958 | if (which_alternative != 0) | |
8959 | return "#"; | |
8960 | else if (get_attr_length (insn) == 6) | |
8961 | return "brx%E5g\t%1,%2,%l0"; | |
8962 | else | |
8963 | return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; | |
8964 | } | |
8965 | "&& reload_completed | |
8966 | && (!REG_P (operands[3]) | |
8967 | || !rtx_equal_p (operands[1], operands[3]))" | |
8968 | [(set (match_dup 4) (match_dup 1)) | |
8969 | (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) | |
8970 | (clobber (reg:CC CC_REGNUM))]) | |
8971 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) | |
8972 | (set (match_dup 3) (match_dup 4)) | |
8973 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
8974 | (label_ref (match_dup 0)) | |
8975 | (pc)))] | |
8976 | "" | |
8977 | [(set_attr "op_type" "RIE") | |
8978 | (set_attr "type" "branch") | |
8979 | (set (attr "length") | |
8980 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8981 | (const_int 6) (const_int 16)))]) | |
8982 | ||
8983 | ; brxle, brxh | |
8984 | ||
8985 | (define_insn_and_split "*brx_64bit" | |
8986 | [(set (pc) | |
8987 | (if_then_else | |
8988 | (match_operator 5 "s390_brx_operator" | |
8989 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
8990 | (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) | |
8991 | (subreg:SI (match_dup 2) 12)]) | |
8992 | (label_ref (match_operand 0 "" "")) | |
8993 | (pc))) | |
8994 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
8995 | (plus:SI (match_dup 1) | |
8996 | (subreg:SI (match_dup 2) 4))) | |
8997 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
8998 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 8999 | "TARGET_ZARCH" |
f1149235 AK |
9000 | { |
9001 | if (which_alternative != 0) | |
9002 | return "#"; | |
9003 | else if (get_attr_length (insn) == 6) | |
9004 | return "brx%C5\t%1,%2,%l0"; | |
9005 | else | |
9006 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9007 | } | |
9008 | "&& reload_completed | |
9009 | && (!REG_P (operands[3]) | |
9010 | || !rtx_equal_p (operands[1], operands[3]))" | |
9011 | [(set (match_dup 4) (match_dup 1)) | |
9012 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9013 | (clobber (reg:CC CC_REGNUM))]) | |
9014 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) | |
9015 | (set (match_dup 3) (match_dup 4)) | |
9016 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9017 | (label_ref (match_dup 0)) | |
9018 | (pc)))] | |
9019 | "" | |
9020 | [(set_attr "op_type" "RSI") | |
9021 | (set_attr "type" "branch") | |
9022 | (set (attr "length") | |
9023 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9024 | (const_int 6) (const_int 14)))]) | |
9025 | ||
9026 | ; brxle, brxh | |
9027 | ||
9028 | (define_insn_and_split "*brx_31bit" | |
9029 | [(set (pc) | |
9030 | (if_then_else | |
9031 | (match_operator 5 "s390_brx_operator" | |
9032 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9033 | (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) | |
9034 | (subreg:SI (match_dup 2) 4)]) | |
9035 | (label_ref (match_operand 0 "" "")) | |
9036 | (pc))) | |
9037 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9038 | (plus:SI (match_dup 1) | |
9039 | (subreg:SI (match_dup 2) 0))) | |
9040 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9041 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9042 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1149235 AK |
9043 | { |
9044 | if (which_alternative != 0) | |
9045 | return "#"; | |
9046 | else if (get_attr_length (insn) == 6) | |
9047 | return "brx%C5\t%1,%2,%l0"; | |
9048 | else | |
9049 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9050 | } | |
9051 | "&& reload_completed | |
9052 | && (!REG_P (operands[3]) | |
9053 | || !rtx_equal_p (operands[1], operands[3]))" | |
9054 | [(set (match_dup 4) (match_dup 1)) | |
9055 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) | |
9056 | (clobber (reg:CC CC_REGNUM))]) | |
9057 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9058 | (set (match_dup 3) (match_dup 4)) | |
9059 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9060 | (label_ref (match_dup 0)) | |
9061 | (pc)))] | |
9062 | "" | |
9063 | [(set_attr "op_type" "RSI") | |
9064 | (set_attr "type" "branch") | |
9065 | (set (attr "length") | |
9066 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9067 | (const_int 6) (const_int 14)))]) | |
9068 | ||
9069 | ||
9070 | ;; branch on count | |
9071 | ||
0a3bdf9d UW |
9072 | (define_expand "doloop_end" |
9073 | [(use (match_operand 0 "" "")) ; loop pseudo | |
1d0216c8 | 9074 | (use (match_operand 1 "" ""))] ; label |
0a3bdf9d | 9075 | "" |
0a3bdf9d | 9076 | { |
6590e19a | 9077 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
1d0216c8 | 9078 | emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0])); |
6590e19a | 9079 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) |
1d0216c8 | 9080 | emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0])); |
9602b6a1 | 9081 | else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) |
1d0216c8 | 9082 | emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0])); |
0a3bdf9d UW |
9083 | else |
9084 | FAIL; | |
9085 | ||
9086 | DONE; | |
10bbf137 | 9087 | }) |
0a3bdf9d | 9088 | |
6590e19a | 9089 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
9090 | [(set (pc) |
9091 | (if_then_else | |
7e665d18 | 9092 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9093 | (const_int 1)) |
9094 | (label_ref (match_operand 0 "" "")) | |
9095 | (pc))) | |
7e665d18 | 9096 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9097 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9098 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9099 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 9100 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
9101 | { |
9102 | if (which_alternative != 0) | |
10bbf137 | 9103 | return "#"; |
0a3bdf9d | 9104 | else if (get_attr_length (insn) == 4) |
d40c829f | 9105 | return "brct\t%1,%l0"; |
6590e19a | 9106 | else |
545d16ff | 9107 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
9108 | } |
9109 | "&& reload_completed | |
9110 | && (! REG_P (operands[2]) | |
9111 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9112 | [(set (match_dup 3) (match_dup 1)) |
9113 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9114 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9115 | (const_int 0))) | |
9116 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9117 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9118 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9119 | (label_ref (match_dup 0)) |
9120 | (pc)))] | |
9121 | "" | |
9122 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9123 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9124 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9125 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9126 | (set_attr "type" "branch") |
9127 | (set (attr "length") | |
9128 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9129 | (const_int 4) (const_int 10)))]) | |
9130 | ||
9131 | (define_insn_and_split "doloop_si31" | |
9132 | [(set (pc) | |
9133 | (if_then_else | |
7e665d18 | 9134 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
6590e19a UW |
9135 | (const_int 1)) |
9136 | (label_ref (match_operand 0 "" "")) | |
9137 | (pc))) | |
7e665d18 | 9138 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
6590e19a | 9139 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9140 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9141 | (clobber (reg:CC CC_REGNUM))] |
6590e19a UW |
9142 | "!TARGET_CPU_ZARCH" |
9143 | { | |
9144 | if (which_alternative != 0) | |
9145 | return "#"; | |
9146 | else if (get_attr_length (insn) == 4) | |
9147 | return "brct\t%1,%l0"; | |
0a3bdf9d | 9148 | else |
8d933e31 | 9149 | gcc_unreachable (); |
10bbf137 | 9150 | } |
6590e19a UW |
9151 | "&& reload_completed |
9152 | && (! REG_P (operands[2]) | |
9153 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9154 | [(set (match_dup 3) (match_dup 1)) |
9155 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9156 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9157 | (const_int 0))) | |
9158 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9159 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9160 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9161 | (label_ref (match_dup 0)) |
9162 | (pc)))] | |
9163 | "" | |
0a3bdf9d | 9164 | [(set_attr "op_type" "RI") |
9381e3f1 WG |
9165 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9166 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9167 | (set_attr "z10prop" "z10_super_E1") |
077dab3b | 9168 | (set_attr "type" "branch") |
0a3bdf9d | 9169 | (set (attr "length") |
d7f99b2c | 9170 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
9171 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9172 | (const_int 4) (const_int 6)) | |
9173 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9174 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 9175 | |
0a3bdf9d UW |
9176 | (define_insn "*doloop_si_long" |
9177 | [(set (pc) | |
9178 | (if_then_else | |
7e665d18 | 9179 | (ne (match_operand:SI 1 "register_operand" "d") |
0a3bdf9d | 9180 | (const_int 1)) |
4fe6dea8 | 9181 | (match_operand 0 "address_operand" "ZQZR") |
0a3bdf9d | 9182 | (pc))) |
7e665d18 | 9183 | (set (match_operand:SI 2 "register_operand" "=1") |
0a3bdf9d | 9184 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9185 | (clobber (match_scratch:SI 3 "=X")) |
ae156f85 | 9186 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 9187 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
9188 | { |
9189 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9190 | return "bctr\t%1,%0"; |
0a3bdf9d | 9191 | else |
d40c829f | 9192 | return "bct\t%1,%a0"; |
10bbf137 | 9193 | } |
c7453384 | 9194 | [(set (attr "op_type") |
0a3bdf9d UW |
9195 | (if_then_else (match_operand 0 "register_operand" "") |
9196 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 9197 | (set_attr "type" "branch") |
729e750f | 9198 | (set_attr "atype" "agen") |
65b1d8ea AK |
9199 | (set_attr "z10prop" "z10_c") |
9200 | (set_attr "z196prop" "z196_cracked")]) | |
0a3bdf9d | 9201 | |
6590e19a | 9202 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
9203 | [(set (pc) |
9204 | (if_then_else | |
7e665d18 | 9205 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9206 | (const_int 1)) |
9207 | (label_ref (match_operand 0 "" "")) | |
9208 | (pc))) | |
7e665d18 | 9209 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9210 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 9211 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 9212 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 9213 | "TARGET_ZARCH" |
0a3bdf9d UW |
9214 | { |
9215 | if (which_alternative != 0) | |
10bbf137 | 9216 | return "#"; |
0a3bdf9d | 9217 | else if (get_attr_length (insn) == 4) |
d40c829f | 9218 | return "brctg\t%1,%l0"; |
0a3bdf9d | 9219 | else |
545d16ff | 9220 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 9221 | } |
6590e19a | 9222 | "&& reload_completed |
0a3bdf9d UW |
9223 | && (! REG_P (operands[2]) |
9224 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9225 | [(set (match_dup 3) (match_dup 1)) |
9226 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
9227 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
9228 | (const_int 0))) | |
9229 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
9230 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9231 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 9232 | (label_ref (match_dup 0)) |
0a3bdf9d | 9233 | (pc)))] |
6590e19a UW |
9234 | "" |
9235 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9236 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9237 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9238 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9239 | (set_attr "type" "branch") |
9240 | (set (attr "length") | |
9241 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9242 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
9243 | |
9244 | ;; | |
9245 | ;;- Unconditional jump instructions. | |
9246 | ;; | |
9247 | ||
9248 | ; | |
9249 | ; jump instruction pattern(s). | |
9250 | ; | |
9251 | ||
6590e19a UW |
9252 | (define_expand "jump" |
9253 | [(match_operand 0 "" "")] | |
9db1d521 | 9254 | "" |
6590e19a UW |
9255 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
9256 | ||
9257 | (define_insn "*jump64" | |
9258 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
9259 | "TARGET_CPU_ZARCH" | |
9db1d521 | 9260 | { |
13e58269 | 9261 | if (get_attr_length (insn) == 4) |
d40c829f | 9262 | return "j\t%l0"; |
6590e19a | 9263 | else |
d40c829f | 9264 | return "jg\t%l0"; |
6590e19a UW |
9265 | } |
9266 | [(set_attr "op_type" "RI") | |
9267 | (set_attr "type" "branch") | |
9268 | (set (attr "length") | |
9269 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9270 | (const_int 4) (const_int 6)))]) | |
9271 | ||
9272 | (define_insn "*jump31" | |
9273 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
9274 | "!TARGET_CPU_ZARCH" | |
9275 | { | |
8d933e31 AS |
9276 | gcc_assert (get_attr_length (insn) == 4); |
9277 | return "j\t%l0"; | |
10bbf137 | 9278 | } |
9db1d521 | 9279 | [(set_attr "op_type" "RI") |
077dab3b | 9280 | (set_attr "type" "branch") |
13e58269 | 9281 | (set (attr "length") |
d7f99b2c | 9282 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
9283 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9284 | (const_int 4) (const_int 6)) | |
9285 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9286 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
9287 | |
9288 | ; | |
9289 | ; indirect-jump instruction pattern(s). | |
9290 | ; | |
9291 | ||
9292 | (define_insn "indirect_jump" | |
4fe6dea8 | 9293 | [(set (pc) (match_operand 0 "address_operand" "ZQZR"))] |
9db1d521 | 9294 | "" |
f314b9b1 UW |
9295 | { |
9296 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9297 | return "br\t%0"; |
f314b9b1 | 9298 | else |
d40c829f | 9299 | return "b\t%a0"; |
10bbf137 | 9300 | } |
c7453384 | 9301 | [(set (attr "op_type") |
f314b9b1 UW |
9302 | (if_then_else (match_operand 0 "register_operand" "") |
9303 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 9304 | (set_attr "type" "branch") |
729e750f | 9305 | (set_attr "atype" "agen")]) |
9db1d521 HP |
9306 | |
9307 | ; | |
f314b9b1 | 9308 | ; casesi instruction pattern(s). |
9db1d521 HP |
9309 | ; |
9310 | ||
f314b9b1 | 9311 | (define_insn "casesi_jump" |
4fe6dea8 | 9312 | [(set (pc) (match_operand 0 "address_operand" "ZQZR")) |
f314b9b1 | 9313 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 9314 | "" |
9db1d521 | 9315 | { |
f314b9b1 | 9316 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 9317 | return "br\t%0"; |
f314b9b1 | 9318 | else |
d40c829f | 9319 | return "b\t%a0"; |
10bbf137 | 9320 | } |
c7453384 | 9321 | [(set (attr "op_type") |
f314b9b1 UW |
9322 | (if_then_else (match_operand 0 "register_operand" "") |
9323 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
9324 | (set_attr "type" "branch") |
9325 | (set_attr "atype" "agen")]) | |
9db1d521 | 9326 | |
f314b9b1 UW |
9327 | (define_expand "casesi" |
9328 | [(match_operand:SI 0 "general_operand" "") | |
9329 | (match_operand:SI 1 "general_operand" "") | |
9330 | (match_operand:SI 2 "general_operand" "") | |
9331 | (label_ref (match_operand 3 "" "")) | |
9332 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 9333 | "" |
f314b9b1 UW |
9334 | { |
9335 | rtx index = gen_reg_rtx (SImode); | |
9336 | rtx base = gen_reg_rtx (Pmode); | |
9337 | rtx target = gen_reg_rtx (Pmode); | |
9338 | ||
9339 | emit_move_insn (index, operands[0]); | |
9340 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
9341 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 9342 | operands[4]); |
f314b9b1 UW |
9343 | |
9344 | if (Pmode != SImode) | |
9345 | index = convert_to_mode (Pmode, index, 1); | |
9346 | if (GET_CODE (index) != REG) | |
9347 | index = copy_to_mode_reg (Pmode, index); | |
9348 | ||
9349 | if (TARGET_64BIT) | |
9350 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
9351 | else | |
a556fd39 | 9352 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 9353 | |
f314b9b1 UW |
9354 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
9355 | ||
542a8afa | 9356 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
9357 | emit_move_insn (target, index); |
9358 | ||
9359 | if (flag_pic) | |
9360 | target = gen_rtx_PLUS (Pmode, base, target); | |
9361 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
9362 | ||
9363 | DONE; | |
10bbf137 | 9364 | }) |
9db1d521 HP |
9365 | |
9366 | ||
9367 | ;; | |
9368 | ;;- Jump to subroutine. | |
9369 | ;; | |
9370 | ;; | |
9371 | ||
9372 | ; | |
9373 | ; untyped call instruction pattern(s). | |
9374 | ; | |
9375 | ||
9376 | ;; Call subroutine returning any type. | |
9377 | (define_expand "untyped_call" | |
9378 | [(parallel [(call (match_operand 0 "" "") | |
9379 | (const_int 0)) | |
9380 | (match_operand 1 "" "") | |
9381 | (match_operand 2 "" "")])] | |
9382 | "" | |
9db1d521 HP |
9383 | { |
9384 | int i; | |
9385 | ||
9386 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
9387 | ||
9388 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
9389 | { | |
9390 | rtx set = XVECEXP (operands[2], 0, i); | |
9391 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
9392 | } | |
9393 | ||
9394 | /* The optimizer does not know that the call sets the function value | |
9395 | registers we stored in the result block. We avoid problems by | |
9396 | claiming that all hard registers are used and clobbered at this | |
9397 | point. */ | |
9398 | emit_insn (gen_blockage ()); | |
9399 | ||
9400 | DONE; | |
10bbf137 | 9401 | }) |
9db1d521 HP |
9402 | |
9403 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
9404 | ;; all of memory. This blocks insns from being moved across this point. | |
9405 | ||
9406 | (define_insn "blockage" | |
10bbf137 | 9407 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 9408 | "" |
4023fb28 | 9409 | "" |
d5869ca0 UW |
9410 | [(set_attr "type" "none") |
9411 | (set_attr "length" "0")]) | |
4023fb28 | 9412 | |
9db1d521 | 9413 | ; |
ed9676cf | 9414 | ; sibcall patterns |
9db1d521 HP |
9415 | ; |
9416 | ||
ed9676cf | 9417 | (define_expand "sibcall" |
44b8152b | 9418 | [(call (match_operand 0 "" "") |
ed9676cf | 9419 | (match_operand 1 "" ""))] |
9db1d521 | 9420 | "" |
9db1d521 | 9421 | { |
ed9676cf AK |
9422 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
9423 | DONE; | |
9424 | }) | |
9db1d521 | 9425 | |
ed9676cf | 9426 | (define_insn "*sibcall_br" |
ae156f85 | 9427 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9428 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 9429 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
9430 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
9431 | "br\t%%r1" | |
9432 | [(set_attr "op_type" "RR") | |
9433 | (set_attr "type" "branch") | |
9434 | (set_attr "atype" "agen")]) | |
9db1d521 | 9435 | |
ed9676cf AK |
9436 | (define_insn "*sibcall_brc" |
9437 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9438 | (match_operand 1 "const_int_operand" "n"))] | |
9439 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9440 | "j\t%0" | |
9441 | [(set_attr "op_type" "RI") | |
9442 | (set_attr "type" "branch")]) | |
9db1d521 | 9443 | |
ed9676cf AK |
9444 | (define_insn "*sibcall_brcl" |
9445 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9446 | (match_operand 1 "const_int_operand" "n"))] | |
9447 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
9448 | "jg\t%0" | |
9449 | [(set_attr "op_type" "RIL") | |
9450 | (set_attr "type" "branch")]) | |
44b8152b | 9451 | |
ed9676cf AK |
9452 | ; |
9453 | ; sibcall_value patterns | |
9454 | ; | |
9e8327e3 | 9455 | |
ed9676cf AK |
9456 | (define_expand "sibcall_value" |
9457 | [(set (match_operand 0 "" "") | |
9458 | (call (match_operand 1 "" "") | |
9459 | (match_operand 2 "" "")))] | |
9460 | "" | |
9461 | { | |
9462 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 9463 | DONE; |
10bbf137 | 9464 | }) |
9db1d521 | 9465 | |
ed9676cf AK |
9466 | (define_insn "*sibcall_value_br" |
9467 | [(set (match_operand 0 "" "") | |
ae156f85 | 9468 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9469 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 9470 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
9471 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
9472 | "br\t%%r1" | |
9473 | [(set_attr "op_type" "RR") | |
9474 | (set_attr "type" "branch") | |
9475 | (set_attr "atype" "agen")]) | |
9476 | ||
9477 | (define_insn "*sibcall_value_brc" | |
9478 | [(set (match_operand 0 "" "") | |
9479 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9480 | (match_operand 2 "const_int_operand" "n")))] | |
9481 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9482 | "j\t%1" | |
9483 | [(set_attr "op_type" "RI") | |
9484 | (set_attr "type" "branch")]) | |
9485 | ||
9486 | (define_insn "*sibcall_value_brcl" | |
9487 | [(set (match_operand 0 "" "") | |
9488 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9489 | (match_operand 2 "const_int_operand" "n")))] | |
9490 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
9491 | "jg\t%1" | |
9492 | [(set_attr "op_type" "RIL") | |
9493 | (set_attr "type" "branch")]) | |
9494 | ||
9495 | ||
9496 | ; | |
9497 | ; call instruction pattern(s). | |
9498 | ; | |
9499 | ||
9500 | (define_expand "call" | |
9501 | [(call (match_operand 0 "" "") | |
9502 | (match_operand 1 "" "")) | |
9503 | (use (match_operand 2 "" ""))] | |
44b8152b | 9504 | "" |
ed9676cf | 9505 | { |
2f7e5a0d | 9506 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
9507 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
9508 | DONE; | |
9509 | }) | |
44b8152b | 9510 | |
9e8327e3 UW |
9511 | (define_insn "*bras" |
9512 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9513 | (match_operand 1 "const_int_operand" "n")) | |
9514 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
9515 | "!SIBLING_CALL_P (insn) |
9516 | && TARGET_SMALL_EXEC | |
ed9676cf | 9517 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 9518 | "bras\t%2,%0" |
9db1d521 | 9519 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9520 | (set_attr "type" "jsr") |
9521 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9522 | |
9e8327e3 UW |
9523 | (define_insn "*brasl" |
9524 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9525 | (match_operand 1 "const_int_operand" "n")) | |
9526 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
9527 | "!SIBLING_CALL_P (insn) |
9528 | && TARGET_CPU_ZARCH | |
ed9676cf | 9529 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
9530 | "brasl\t%2,%0" |
9531 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9532 | (set_attr "type" "jsr") |
9533 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9534 | |
9e8327e3 | 9535 | (define_insn "*basr" |
4fe6dea8 | 9536 | [(call (mem:QI (match_operand 0 "address_operand" "ZQZR")) |
9e8327e3 UW |
9537 | (match_operand 1 "const_int_operand" "n")) |
9538 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 9539 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
9540 | { |
9541 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9542 | return "basr\t%2,%0"; | |
9543 | else | |
9544 | return "bas\t%2,%a0"; | |
9545 | } | |
9546 | [(set (attr "op_type") | |
9547 | (if_then_else (match_operand 0 "register_operand" "") | |
9548 | (const_string "RR") (const_string "RX"))) | |
9549 | (set_attr "type" "jsr") | |
65b1d8ea AK |
9550 | (set_attr "atype" "agen") |
9551 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 HP |
9552 | |
9553 | ; | |
9554 | ; call_value instruction pattern(s). | |
9555 | ; | |
9556 | ||
9557 | (define_expand "call_value" | |
44b8152b UW |
9558 | [(set (match_operand 0 "" "") |
9559 | (call (match_operand 1 "" "") | |
9560 | (match_operand 2 "" ""))) | |
9561 | (use (match_operand 3 "" ""))] | |
9db1d521 | 9562 | "" |
9db1d521 | 9563 | { |
2f7e5a0d | 9564 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 9565 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 9566 | DONE; |
10bbf137 | 9567 | }) |
9db1d521 | 9568 | |
9e8327e3 | 9569 | (define_insn "*bras_r" |
c19ec8f9 | 9570 | [(set (match_operand 0 "" "") |
9e8327e3 | 9571 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 9572 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 9573 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
9574 | "!SIBLING_CALL_P (insn) |
9575 | && TARGET_SMALL_EXEC | |
ed9676cf | 9576 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 9577 | "bras\t%3,%1" |
9db1d521 | 9578 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9579 | (set_attr "type" "jsr") |
9580 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9581 | |
9e8327e3 | 9582 | (define_insn "*brasl_r" |
c19ec8f9 | 9583 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9584 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9585 | (match_operand 2 "const_int_operand" "n"))) | |
9586 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
9587 | "!SIBLING_CALL_P (insn) |
9588 | && TARGET_CPU_ZARCH | |
ed9676cf | 9589 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9590 | "brasl\t%3,%1" |
9591 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9592 | (set_attr "type" "jsr") |
9593 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9594 | |
9e8327e3 | 9595 | (define_insn "*basr_r" |
c19ec8f9 | 9596 | [(set (match_operand 0 "" "") |
4fe6dea8 | 9597 | (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
9e8327e3 UW |
9598 | (match_operand 2 "const_int_operand" "n"))) |
9599 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 9600 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9601 | { |
9602 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9603 | return "basr\t%3,%1"; | |
9604 | else | |
9605 | return "bas\t%3,%a1"; | |
9606 | } | |
9607 | [(set (attr "op_type") | |
9608 | (if_then_else (match_operand 1 "register_operand" "") | |
9609 | (const_string "RR") (const_string "RX"))) | |
9610 | (set_attr "type" "jsr") | |
65b1d8ea AK |
9611 | (set_attr "atype" "agen") |
9612 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9613 | |
fd3cd001 UW |
9614 | ;; |
9615 | ;;- Thread-local storage support. | |
9616 | ;; | |
9617 | ||
f959607b CLT |
9618 | (define_expand "get_thread_pointer<mode>" |
9619 | [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))] | |
9620 | "" | |
c5aa1d12 | 9621 | "") |
fd3cd001 | 9622 | |
f959607b CLT |
9623 | (define_expand "set_thread_pointer<mode>" |
9624 | [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) | |
9625 | (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] | |
9626 | "" | |
c5aa1d12 UW |
9627 | "") |
9628 | ||
9629 | (define_insn "*set_tp" | |
ae156f85 | 9630 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
9631 | "" |
9632 | "" | |
9633 | [(set_attr "type" "none") | |
9634 | (set_attr "length" "0")]) | |
c7453384 | 9635 | |
fd3cd001 UW |
9636 | (define_insn "*tls_load_64" |
9637 | [(set (match_operand:DI 0 "register_operand" "=d") | |
fb492564 | 9638 | (unspec:DI [(match_operand:DI 1 "memory_operand" "RT") |
fd3cd001 UW |
9639 | (match_operand:DI 2 "" "")] |
9640 | UNSPEC_TLS_LOAD))] | |
9641 | "TARGET_64BIT" | |
d40c829f | 9642 | "lg\t%0,%1%J2" |
9381e3f1 WG |
9643 | [(set_attr "op_type" "RXE") |
9644 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
9645 | |
9646 | (define_insn "*tls_load_31" | |
d3632d41 UW |
9647 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
9648 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
9649 | (match_operand:SI 2 "" "")] |
9650 | UNSPEC_TLS_LOAD))] | |
9651 | "!TARGET_64BIT" | |
d3632d41 | 9652 | "@ |
d40c829f UW |
9653 | l\t%0,%1%J2 |
9654 | ly\t%0,%1%J2" | |
9381e3f1 | 9655 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 9656 | (set_attr "type" "load") |
9381e3f1 | 9657 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 9658 | |
9e8327e3 | 9659 | (define_insn "*bras_tls" |
c19ec8f9 | 9660 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9661 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9662 | (match_operand 2 "const_int_operand" "n"))) | |
9663 | (clobber (match_operand 3 "register_operand" "=r")) | |
9664 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
9665 | "!SIBLING_CALL_P (insn) |
9666 | && TARGET_SMALL_EXEC | |
ed9676cf | 9667 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 9668 | "bras\t%3,%1%J4" |
fd3cd001 | 9669 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9670 | (set_attr "type" "jsr") |
9671 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9672 | |
9e8327e3 | 9673 | (define_insn "*brasl_tls" |
c19ec8f9 | 9674 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9675 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9676 | (match_operand 2 "const_int_operand" "n"))) | |
9677 | (clobber (match_operand 3 "register_operand" "=r")) | |
9678 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
9679 | "!SIBLING_CALL_P (insn) |
9680 | && TARGET_CPU_ZARCH | |
ed9676cf | 9681 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9682 | "brasl\t%3,%1%J4" |
9683 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9684 | (set_attr "type" "jsr") |
9685 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9686 | |
9e8327e3 | 9687 | (define_insn "*basr_tls" |
c19ec8f9 | 9688 | [(set (match_operand 0 "" "") |
4fe6dea8 | 9689 | (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) |
9e8327e3 UW |
9690 | (match_operand 2 "const_int_operand" "n"))) |
9691 | (clobber (match_operand 3 "register_operand" "=r")) | |
9692 | (use (match_operand 4 "" ""))] | |
ed9676cf | 9693 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9694 | { |
9695 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9696 | return "basr\t%3,%1%J4"; | |
9697 | else | |
9698 | return "bas\t%3,%a1%J4"; | |
9699 | } | |
9700 | [(set (attr "op_type") | |
9701 | (if_then_else (match_operand 1 "register_operand" "") | |
9702 | (const_string "RR") (const_string "RX"))) | |
9703 | (set_attr "type" "jsr") | |
65b1d8ea AK |
9704 | (set_attr "atype" "agen") |
9705 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9706 | |
e0374221 AS |
9707 | ;; |
9708 | ;;- Atomic operations | |
9709 | ;; | |
9710 | ||
9711 | ; | |
78ce265b | 9712 | ; memory barrier patterns. |
e0374221 AS |
9713 | ; |
9714 | ||
78ce265b RH |
9715 | (define_expand "mem_signal_fence" |
9716 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
e0374221 AS |
9717 | "" |
9718 | { | |
78ce265b RH |
9719 | /* The s390 memory model is strong enough not to require any |
9720 | barrier in order to synchronize a thread with itself. */ | |
9721 | DONE; | |
9722 | }) | |
9723 | ||
9724 | (define_expand "mem_thread_fence" | |
9725 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
9726 | "" | |
9727 | { | |
9728 | /* Unless this is a SEQ_CST fence, the s390 memory model is strong | |
9729 | enough not to require barriers of any kind. */ | |
46b35980 | 9730 | if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0])))) |
78ce265b RH |
9731 | { |
9732 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
9733 | MEM_VOLATILE_P (mem) = 1; | |
9734 | emit_insn (gen_mem_thread_fence_1 (mem)); | |
9735 | } | |
9736 | DONE; | |
e0374221 AS |
9737 | }) |
9738 | ||
78ce265b RH |
9739 | ; Although bcr is superscalar on Z10, this variant will never |
9740 | ; become part of an execution group. | |
a9cc3f58 AK |
9741 | ; With z196 we can make use of the fast-BCR-serialization facility. |
9742 | ; This allows for a slightly faster sync which is sufficient for our | |
9743 | ; purposes. | |
78ce265b | 9744 | (define_insn "mem_thread_fence_1" |
e0374221 | 9745 | [(set (match_operand:BLK 0 "" "") |
1a8c13b3 | 9746 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 | 9747 | "" |
a9cc3f58 AK |
9748 | { |
9749 | if (TARGET_Z196) | |
9750 | return "bcr\t14,0"; | |
9751 | else | |
9752 | return "bcr\t15,0"; | |
9753 | } | |
9754 | [(set_attr "op_type" "RR") | |
9755 | (set_attr "mnemonic" "bcr_flush") | |
9756 | (set_attr "z196prop" "z196_alone")]) | |
1a8c13b3 | 9757 | |
78ce265b RH |
9758 | ; |
9759 | ; atomic load/store operations | |
9760 | ; | |
9761 | ||
9762 | ; Atomic loads need not examine the memory model at all. | |
9763 | (define_expand "atomic_load<mode>" | |
9764 | [(match_operand:DINT 0 "register_operand") ;; output | |
9765 | (match_operand:DINT 1 "memory_operand") ;; memory | |
9766 | (match_operand:SI 2 "const_int_operand")] ;; model | |
9767 | "" | |
9768 | { | |
75cc21e2 AK |
9769 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
9770 | FAIL; | |
9771 | ||
78ce265b RH |
9772 | if (<MODE>mode == TImode) |
9773 | emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); | |
9774 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
9775 | emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); | |
9776 | else | |
9777 | emit_move_insn (operands[0], operands[1]); | |
9778 | DONE; | |
9779 | }) | |
9780 | ||
9781 | ; Different from movdi_31 in that we want no splitters. | |
9782 | (define_insn "atomic_loaddi_1" | |
9783 | [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") | |
9784 | (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] | |
9785 | UNSPEC_MOVA))] | |
9786 | "!TARGET_ZARCH" | |
9787 | "@ | |
9788 | lm\t%0,%M0,%S1 | |
9789 | lmy\t%0,%M0,%S1 | |
9790 | ld\t%0,%1 | |
9791 | ldy\t%0,%1" | |
9792 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
9793 | (set_attr "type" "lm,lm,floaddf,floaddf")]) | |
9794 | ||
9795 | (define_insn "atomic_loadti_1" | |
9796 | [(set (match_operand:TI 0 "register_operand" "=r") | |
9797 | (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")] | |
9798 | UNSPEC_MOVA))] | |
9799 | "TARGET_ZARCH" | |
9800 | "lpq\t%0,%1" | |
9801 | [(set_attr "op_type" "RXY") | |
9802 | (set_attr "type" "other")]) | |
9803 | ||
9804 | ; Atomic stores must(?) enforce sequential consistency. | |
9805 | (define_expand "atomic_store<mode>" | |
9806 | [(match_operand:DINT 0 "memory_operand") ;; memory | |
9807 | (match_operand:DINT 1 "register_operand") ;; input | |
9808 | (match_operand:SI 2 "const_int_operand")] ;; model | |
9809 | "" | |
9810 | { | |
46b35980 | 9811 | enum memmodel model = memmodel_from_int (INTVAL (operands[2])); |
78ce265b | 9812 | |
75cc21e2 AK |
9813 | if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0]))) |
9814 | FAIL; | |
9815 | ||
78ce265b RH |
9816 | if (<MODE>mode == TImode) |
9817 | emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); | |
9818 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
9819 | emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); | |
9820 | else | |
9821 | emit_move_insn (operands[0], operands[1]); | |
46b35980 | 9822 | if (is_mm_seq_cst (model)) |
78ce265b RH |
9823 | emit_insn (gen_mem_thread_fence (operands[2])); |
9824 | DONE; | |
9825 | }) | |
9826 | ||
9827 | ; Different from movdi_31 in that we want no splitters. | |
9828 | (define_insn "atomic_storedi_1" | |
9829 | [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") | |
9830 | (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] | |
9831 | UNSPEC_MOVA))] | |
9832 | "!TARGET_ZARCH" | |
9833 | "@ | |
9834 | stm\t%1,%N1,%S0 | |
9835 | stmy\t%1,%N1,%S0 | |
9836 | std %1,%0 | |
9837 | stdy %1,%0" | |
9838 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
9839 | (set_attr "type" "stm,stm,fstoredf,fstoredf")]) | |
9840 | ||
9841 | (define_insn "atomic_storeti_1" | |
9842 | [(set (match_operand:TI 0 "memory_operand" "=RT") | |
9843 | (unspec:TI [(match_operand:TI 1 "register_operand" "r")] | |
9844 | UNSPEC_MOVA))] | |
9845 | "TARGET_ZARCH" | |
9846 | "stpq\t%1,%0" | |
9847 | [(set_attr "op_type" "RXY") | |
9848 | (set_attr "type" "other")]) | |
e0374221 AS |
9849 | |
9850 | ; | |
9851 | ; compare and swap patterns. | |
9852 | ; | |
9853 | ||
78ce265b RH |
9854 | (define_expand "atomic_compare_and_swap<mode>" |
9855 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
215770ad | 9856 | (match_operand:DGPR 1 "nonimmediate_operand");; oldval output |
78ce265b RH |
9857 | (match_operand:DGPR 2 "memory_operand") ;; memory |
9858 | (match_operand:DGPR 3 "register_operand") ;; expected intput | |
9859 | (match_operand:DGPR 4 "register_operand") ;; newval intput | |
9860 | (match_operand:SI 5 "const_int_operand") ;; is_weak | |
9861 | (match_operand:SI 6 "const_int_operand") ;; success model | |
9862 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
9863 | "" | |
9864 | { | |
215770ad UW |
9865 | rtx cc, cmp, output = operands[1]; |
9866 | ||
9867 | if (!register_operand (output, <MODE>mode)) | |
9868 | output = gen_reg_rtx (<MODE>mode); | |
9869 | ||
75cc21e2 AK |
9870 | if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2]))) |
9871 | FAIL; | |
9872 | ||
78ce265b | 9873 | emit_insn (gen_atomic_compare_and_swap<mode>_internal |
215770ad UW |
9874 | (output, operands[2], operands[3], operands[4])); |
9875 | ||
9876 | /* We deliberately accept non-register operands in the predicate | |
9877 | to ensure the write back to the output operand happens *before* | |
9878 | the store-flags code below. This makes it easier for combine | |
9879 | to merge the store-flags code with a potential test-and-branch | |
9880 | pattern following (immediately!) afterwards. */ | |
9881 | if (output != operands[1]) | |
9882 | emit_move_insn (operands[1], output); | |
9883 | ||
78ce265b RH |
9884 | cc = gen_rtx_REG (CCZ1mode, CC_REGNUM); |
9885 | cmp = gen_rtx_EQ (SImode, cc, const0_rtx); | |
9886 | emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx)); | |
9887 | DONE; | |
9888 | }) | |
e0374221 | 9889 | |
78ce265b RH |
9890 | (define_expand "atomic_compare_and_swap<mode>" |
9891 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
215770ad | 9892 | (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output |
78ce265b RH |
9893 | (match_operand:HQI 2 "memory_operand") ;; memory |
9894 | (match_operand:HQI 3 "general_operand") ;; expected intput | |
9895 | (match_operand:HQI 4 "general_operand") ;; newval intput | |
9896 | (match_operand:SI 5 "const_int_operand") ;; is_weak | |
9897 | (match_operand:SI 6 "const_int_operand") ;; success model | |
9898 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
3093f076 | 9899 | "" |
78ce265b RH |
9900 | { |
9901 | s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2], | |
9902 | operands[3], operands[4], INTVAL (operands[5])); | |
9903 | DONE; | |
9904 | }) | |
3093f076 | 9905 | |
78ce265b RH |
9906 | (define_expand "atomic_compare_and_swap<mode>_internal" |
9907 | [(parallel | |
9908 | [(set (match_operand:DGPR 0 "register_operand") | |
9909 | (match_operand:DGPR 1 "memory_operand")) | |
9910 | (set (match_dup 1) | |
9911 | (unspec_volatile:DGPR | |
9912 | [(match_dup 1) | |
9913 | (match_operand:DGPR 2 "register_operand") | |
9914 | (match_operand:DGPR 3 "register_operand")] | |
9915 | UNSPECV_CAS)) | |
9916 | (set (reg:CCZ1 CC_REGNUM) | |
9917 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
9918 | "") | |
9919 | ||
9920 | ; cdsg, csg | |
9921 | (define_insn "*atomic_compare_and_swap<mode>_1" | |
9922 | [(set (match_operand:TDI 0 "register_operand" "=r") | |
9923 | (match_operand:TDI 1 "memory_operand" "+QS")) | |
8006eaa6 | 9924 | (set (match_dup 1) |
78ce265b | 9925 | (unspec_volatile:TDI |
8006eaa6 | 9926 | [(match_dup 1) |
78ce265b RH |
9927 | (match_operand:TDI 2 "register_operand" "0") |
9928 | (match_operand:TDI 3 "register_operand" "r")] | |
8006eaa6 AS |
9929 | UNSPECV_CAS)) |
9930 | (set (reg:CCZ1 CC_REGNUM) | |
9931 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
78ce265b RH |
9932 | "TARGET_ZARCH" |
9933 | "c<td>sg\t%0,%3,%S1" | |
9934 | [(set_attr "op_type" "RSY") | |
8006eaa6 AS |
9935 | (set_attr "type" "sem")]) |
9936 | ||
78ce265b RH |
9937 | ; cds, cdsy |
9938 | (define_insn "*atomic_compare_and_swapdi_2" | |
9939 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
9940 | (match_operand:DI 1 "memory_operand" "+Q,S")) | |
e0374221 | 9941 | (set (match_dup 1) |
78ce265b RH |
9942 | (unspec_volatile:DI |
9943 | [(match_dup 1) | |
9944 | (match_operand:DI 2 "register_operand" "0,0") | |
9945 | (match_operand:DI 3 "register_operand" "r,r")] | |
9946 | UNSPECV_CAS)) | |
9947 | (set (reg:CCZ1 CC_REGNUM) | |
9948 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
9949 | "!TARGET_ZARCH" | |
9950 | "@ | |
9951 | cds\t%0,%3,%S1 | |
9952 | cdsy\t%0,%3,%S1" | |
9953 | [(set_attr "op_type" "RS,RSY") | |
9954 | (set_attr "type" "sem")]) | |
9955 | ||
9956 | ; cs, csy | |
9957 | (define_insn "*atomic_compare_and_swapsi_3" | |
9958 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
9959 | (match_operand:SI 1 "memory_operand" "+Q,S")) | |
9960 | (set (match_dup 1) | |
9961 | (unspec_volatile:SI | |
e0374221 | 9962 | [(match_dup 1) |
78ce265b RH |
9963 | (match_operand:SI 2 "register_operand" "0,0") |
9964 | (match_operand:SI 3 "register_operand" "r,r")] | |
e0374221 | 9965 | UNSPECV_CAS)) |
69950452 AS |
9966 | (set (reg:CCZ1 CC_REGNUM) |
9967 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
9381e3f1 | 9968 | "" |
78ce265b RH |
9969 | "@ |
9970 | cs\t%0,%3,%S1 | |
9971 | csy\t%0,%3,%S1" | |
9972 | [(set_attr "op_type" "RS,RSY") | |
e0374221 AS |
9973 | (set_attr "type" "sem")]) |
9974 | ||
45d18331 AS |
9975 | ; |
9976 | ; Other atomic instruction patterns. | |
9977 | ; | |
9978 | ||
65b1d8ea AK |
9979 | ; z196 load and add, xor, or and and instructions |
9980 | ||
78ce265b RH |
9981 | (define_expand "atomic_fetch_<atomic><mode>" |
9982 | [(match_operand:GPR 0 "register_operand") ;; val out | |
9983 | (ATOMIC_Z196:GPR | |
9984 | (match_operand:GPR 1 "memory_operand") ;; memory | |
9985 | (match_operand:GPR 2 "register_operand")) ;; val in | |
9986 | (match_operand:SI 3 "const_int_operand")] ;; model | |
65b1d8ea | 9987 | "TARGET_Z196" |
78ce265b | 9988 | { |
75cc21e2 AK |
9989 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
9990 | FAIL; | |
9991 | ||
78ce265b RH |
9992 | emit_insn (gen_atomic_fetch_<atomic><mode>_iaf |
9993 | (operands[0], operands[1], operands[2])); | |
9994 | DONE; | |
9995 | }) | |
65b1d8ea AK |
9996 | |
9997 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
78ce265b RH |
9998 | (define_insn "atomic_fetch_<atomic><mode>_iaf" |
9999 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
10000 | (match_operand:GPR 1 "memory_operand" "+QS")) | |
10001 | (set (match_dup 1) | |
10002 | (unspec_volatile:GPR | |
10003 | [(ATOMIC_Z196:GPR (match_dup 1) | |
10004 | (match_operand:GPR 2 "general_operand" "d"))] | |
10005 | UNSPECV_ATOMIC_OP)) | |
10006 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 10007 | "TARGET_Z196" |
78ce265b RH |
10008 | "la<noxa><g>\t%0,%2,%1" |
10009 | [(set_attr "op_type" "RSY") | |
10010 | (set_attr "type" "sem")]) | |
65b1d8ea | 10011 | |
78ce265b RH |
10012 | ;; For SImode and larger, the optabs.c code will do just fine in |
10013 | ;; expanding a compare-and-swap loop. For QI/HImode, we can do | |
10014 | ;; better by expanding our own loop. | |
65b1d8ea | 10015 | |
78ce265b RH |
10016 | (define_expand "atomic_<atomic><mode>" |
10017 | [(ATOMIC:HQI | |
10018 | (match_operand:HQI 0 "memory_operand") ;; memory | |
10019 | (match_operand:HQI 1 "general_operand")) ;; val in | |
10020 | (match_operand:SI 2 "const_int_operand")] ;; model | |
45d18331 | 10021 | "" |
78ce265b RH |
10022 | { |
10023 | s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], | |
10024 | operands[1], false); | |
10025 | DONE; | |
10026 | }) | |
45d18331 | 10027 | |
78ce265b RH |
10028 | (define_expand "atomic_fetch_<atomic><mode>" |
10029 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10030 | (ATOMIC:HQI | |
10031 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10032 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10033 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 10034 | "" |
78ce265b RH |
10035 | { |
10036 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10037 | operands[2], false); | |
10038 | DONE; | |
10039 | }) | |
10040 | ||
10041 | (define_expand "atomic_<atomic>_fetch<mode>" | |
10042 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10043 | (ATOMIC:HQI | |
10044 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10045 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10046 | (match_operand:SI 3 "const_int_operand")] ;; model | |
10047 | "" | |
10048 | { | |
10049 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10050 | operands[2], true); | |
10051 | DONE; | |
10052 | }) | |
10053 | ||
10054 | (define_expand "atomic_exchange<mode>" | |
10055 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10056 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10057 | (match_operand:HQI 2 "general_operand") ;; val in | |
10058 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 10059 | "" |
78ce265b RH |
10060 | { |
10061 | s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], | |
10062 | operands[2], false); | |
10063 | DONE; | |
10064 | }) | |
45d18331 | 10065 | |
9db1d521 HP |
10066 | ;; |
10067 | ;;- Miscellaneous instructions. | |
10068 | ;; | |
10069 | ||
10070 | ; | |
10071 | ; allocate stack instruction pattern(s). | |
10072 | ; | |
10073 | ||
10074 | (define_expand "allocate_stack" | |
ef44a6ff UW |
10075 | [(match_operand 0 "general_operand" "") |
10076 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 10077 | "TARGET_BACKCHAIN" |
9db1d521 | 10078 | { |
ef44a6ff | 10079 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 10080 | |
ef44a6ff UW |
10081 | emit_move_insn (temp, s390_back_chain_rtx ()); |
10082 | anti_adjust_stack (operands[1]); | |
10083 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 10084 | |
ef44a6ff UW |
10085 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
10086 | DONE; | |
10bbf137 | 10087 | }) |
9db1d521 HP |
10088 | |
10089 | ||
10090 | ; | |
43ab026f | 10091 | ; setjmp instruction pattern. |
9db1d521 HP |
10092 | ; |
10093 | ||
9db1d521 | 10094 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 10095 | [(match_operand 0 "" "")] |
f314b9b1 | 10096 | "flag_pic" |
9db1d521 | 10097 | { |
585539a1 | 10098 | emit_insn (s390_load_got ()); |
c41c1387 | 10099 | emit_use (pic_offset_table_rtx); |
9db1d521 | 10100 | DONE; |
fd7643fb | 10101 | }) |
9db1d521 | 10102 | |
9db1d521 HP |
10103 | ;; These patterns say how to save and restore the stack pointer. We need not |
10104 | ;; save the stack pointer at function level since we are careful to | |
10105 | ;; preserve the backchain. At block level, we have to restore the backchain | |
10106 | ;; when we restore the stack pointer. | |
10107 | ;; | |
10108 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
10109 | ;; backchain and restore both. Note that in the nonlocal case, the | |
10110 | ;; save area is a memory location. | |
10111 | ||
10112 | (define_expand "save_stack_function" | |
10113 | [(match_operand 0 "general_operand" "") | |
10114 | (match_operand 1 "general_operand" "")] | |
10115 | "" | |
10116 | "DONE;") | |
10117 | ||
10118 | (define_expand "restore_stack_function" | |
10119 | [(match_operand 0 "general_operand" "") | |
10120 | (match_operand 1 "general_operand" "")] | |
10121 | "" | |
10122 | "DONE;") | |
10123 | ||
10124 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
10125 | [(match_operand 0 "register_operand" "") |
10126 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 10127 | "TARGET_BACKCHAIN" |
9db1d521 | 10128 | { |
ef44a6ff UW |
10129 | rtx temp = gen_reg_rtx (Pmode); |
10130 | ||
10131 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
10132 | emit_move_insn (operands[0], operands[1]); | |
10133 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10134 | ||
10135 | DONE; | |
10bbf137 | 10136 | }) |
9db1d521 HP |
10137 | |
10138 | (define_expand "save_stack_nonlocal" | |
10139 | [(match_operand 0 "memory_operand" "") | |
10140 | (match_operand 1 "register_operand" "")] | |
10141 | "" | |
9db1d521 | 10142 | { |
ef44a6ff UW |
10143 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
10144 | ||
10145 | /* Copy the backchain to the first word, sp to the second and the | |
10146 | literal pool base to the third. */ | |
10147 | ||
9602b6a1 AK |
10148 | rtx save_bc = adjust_address (operands[0], Pmode, 0); |
10149 | rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); | |
10150 | rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10151 | ||
b3d31392 | 10152 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10153 | emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); |
ef44a6ff | 10154 | |
9602b6a1 AK |
10155 | emit_move_insn (save_sp, operands[1]); |
10156 | emit_move_insn (save_bp, base); | |
9db1d521 | 10157 | |
9db1d521 | 10158 | DONE; |
10bbf137 | 10159 | }) |
9db1d521 HP |
10160 | |
10161 | (define_expand "restore_stack_nonlocal" | |
10162 | [(match_operand 0 "register_operand" "") | |
10163 | (match_operand 1 "memory_operand" "")] | |
10164 | "" | |
9db1d521 | 10165 | { |
490ceeb4 | 10166 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 10167 | rtx temp = NULL_RTX; |
9db1d521 | 10168 | |
43ab026f | 10169 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 10170 | literal pool base from the third. */ |
43ab026f | 10171 | |
9602b6a1 AK |
10172 | rtx save_bc = adjust_address (operands[1], Pmode, 0); |
10173 | rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); | |
10174 | rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10175 | ||
b3d31392 | 10176 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10177 | temp = force_reg (Pmode, save_bc); |
9381e3f1 | 10178 | |
9602b6a1 AK |
10179 | emit_move_insn (base, save_bp); |
10180 | emit_move_insn (operands[0], save_sp); | |
ef44a6ff UW |
10181 | |
10182 | if (temp) | |
10183 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10184 | ||
c41c1387 | 10185 | emit_use (base); |
9db1d521 | 10186 | DONE; |
10bbf137 | 10187 | }) |
9db1d521 | 10188 | |
7bcebb25 AK |
10189 | (define_expand "exception_receiver" |
10190 | [(const_int 0)] | |
10191 | "" | |
10192 | { | |
10193 | s390_set_has_landing_pad_p (true); | |
10194 | DONE; | |
10195 | }) | |
9db1d521 HP |
10196 | |
10197 | ; | |
10198 | ; nop instruction pattern(s). | |
10199 | ; | |
10200 | ||
10201 | (define_insn "nop" | |
10202 | [(const_int 0)] | |
10203 | "" | |
d40c829f | 10204 | "lr\t0,0" |
729e750f WG |
10205 | [(set_attr "op_type" "RR") |
10206 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 10207 | |
d277db6b WG |
10208 | (define_insn "nop1" |
10209 | [(const_int 1)] | |
10210 | "" | |
10211 | "lr\t1,1" | |
10212 | [(set_attr "op_type" "RR")]) | |
10213 | ||
f8af0e30 DV |
10214 | ;;- Undeletable nops (used for hotpatching) |
10215 | ||
10216 | (define_insn "nop_2_byte" | |
10217 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)] | |
10218 | "" | |
10219 | "nopr\t%%r7" | |
10220 | [(set_attr "op_type" "RR")]) | |
10221 | ||
10222 | (define_insn "nop_4_byte" | |
10223 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)] | |
10224 | "" | |
10225 | "nop\t0" | |
10226 | [(set_attr "op_type" "RX")]) | |
10227 | ||
10228 | (define_insn "nop_6_byte" | |
10229 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)] | |
10230 | "TARGET_CPU_ZARCH" | |
10231 | "brcl\t0, 0" | |
10232 | [(set_attr "op_type" "RIL")]) | |
10233 | ||
9db1d521 HP |
10234 | |
10235 | ; | |
10236 | ; Special literal pool access instruction pattern(s). | |
10237 | ; | |
10238 | ||
416cf582 UW |
10239 | (define_insn "*pool_entry" |
10240 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
10241 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 10242 | "" |
9db1d521 | 10243 | { |
ef4bddc2 | 10244 | machine_mode mode = GET_MODE (PATTERN (insn)); |
416cf582 | 10245 | unsigned int align = GET_MODE_BITSIZE (mode); |
faeb9bb6 | 10246 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
10247 | return ""; |
10248 | } | |
b628bd8e | 10249 | [(set (attr "length") |
416cf582 | 10250 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 10251 | |
9bb86f41 UW |
10252 | (define_insn "pool_align" |
10253 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
10254 | UNSPECV_POOL_ALIGN)] | |
10255 | "" | |
10256 | ".align\t%0" | |
b628bd8e | 10257 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 10258 | |
9bb86f41 UW |
10259 | (define_insn "pool_section_start" |
10260 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
10261 | "" | |
b929b470 MK |
10262 | { |
10263 | switch_to_section (targetm.asm_out.function_rodata_section | |
10264 | (current_function_decl)); | |
10265 | return ""; | |
10266 | } | |
b628bd8e | 10267 | [(set_attr "length" "0")]) |
b2ccb744 | 10268 | |
9bb86f41 UW |
10269 | (define_insn "pool_section_end" |
10270 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
10271 | "" | |
b929b470 MK |
10272 | { |
10273 | switch_to_section (current_function_section ()); | |
10274 | return ""; | |
10275 | } | |
b628bd8e | 10276 | [(set_attr "length" "0")]) |
b2ccb744 | 10277 | |
5af2f3d3 | 10278 | (define_insn "main_base_31_small" |
9e8327e3 UW |
10279 | [(set (match_operand 0 "register_operand" "=a") |
10280 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
10281 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
10282 | "basr\t%0,0" |
10283 | [(set_attr "op_type" "RR") | |
65b1d8ea AK |
10284 | (set_attr "type" "la") |
10285 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
10286 | |
10287 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
10288 | [(set (match_operand 0 "register_operand" "=a") |
10289 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 10290 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 10291 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 | 10292 | "bras\t%0,%2" |
65b1d8ea AK |
10293 | [(set_attr "op_type" "RI") |
10294 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
10295 | |
10296 | (define_insn "main_base_64" | |
9e8327e3 UW |
10297 | [(set (match_operand 0 "register_operand" "=a") |
10298 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
10299 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
10300 | "larl\t%0,%1" |
10301 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 10302 | (set_attr "type" "larl") |
729e750f | 10303 | (set_attr "z10prop" "z10_fwd_A1")]) |
5af2f3d3 UW |
10304 | |
10305 | (define_insn "main_pool" | |
585539a1 UW |
10306 | [(set (match_operand 0 "register_operand" "=a") |
10307 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
10308 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
10309 | { |
10310 | gcc_unreachable (); | |
10311 | } | |
9381e3f1 | 10312 | [(set (attr "type") |
d7f99b2c | 10313 | (if_then_else (match_test "TARGET_CPU_ZARCH") |
ea77e738 | 10314 | (const_string "larl") (const_string "la")))]) |
5af2f3d3 | 10315 | |
aee4e0db | 10316 | (define_insn "reload_base_31" |
9e8327e3 UW |
10317 | [(set (match_operand 0 "register_operand" "=a") |
10318 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
10319 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10320 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e | 10321 | [(set_attr "length" "6") |
65b1d8ea AK |
10322 | (set_attr "type" "la") |
10323 | (set_attr "z196prop" "z196_cracked")]) | |
b2ccb744 | 10324 | |
aee4e0db | 10325 | (define_insn "reload_base_64" |
9e8327e3 UW |
10326 | [(set (match_operand 0 "register_operand" "=a") |
10327 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
10328 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10329 | "larl\t%0,%1" |
aee4e0db | 10330 | [(set_attr "op_type" "RIL") |
9381e3f1 | 10331 | (set_attr "type" "larl") |
729e750f | 10332 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 10333 | |
aee4e0db | 10334 | (define_insn "pool" |
fd7643fb | 10335 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 10336 | "" |
8d933e31 AS |
10337 | { |
10338 | gcc_unreachable (); | |
10339 | } | |
b628bd8e | 10340 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 10341 | |
4023fb28 UW |
10342 | ;; |
10343 | ;; Insns related to generating the function prologue and epilogue. | |
10344 | ;; | |
10345 | ||
10346 | ||
10347 | (define_expand "prologue" | |
10348 | [(use (const_int 0))] | |
10349 | "" | |
10bbf137 | 10350 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
10351 | |
10352 | (define_expand "epilogue" | |
10353 | [(use (const_int 1))] | |
10354 | "" | |
ed9676cf AK |
10355 | "s390_emit_epilogue (false); DONE;") |
10356 | ||
10357 | (define_expand "sibcall_epilogue" | |
10358 | [(use (const_int 0))] | |
10359 | "" | |
10360 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 10361 | |
177bc204 RS |
10362 | ;; A direct return instruction, without using an epilogue. |
10363 | (define_insn "<code>" | |
10364 | [(ANY_RETURN)] | |
10365 | "s390_can_use_<code>_insn ()" | |
10366 | "br\t%%r14" | |
10367 | [(set_attr "op_type" "RR") | |
10368 | (set_attr "type" "jsr") | |
10369 | (set_attr "atype" "agen")]) | |
10370 | ||
9e8327e3 | 10371 | (define_insn "*return" |
4023fb28 | 10372 | [(return) |
9e8327e3 UW |
10373 | (use (match_operand 0 "register_operand" "a"))] |
10374 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10375 | "br\t%0" |
4023fb28 | 10376 | [(set_attr "op_type" "RR") |
c7453384 | 10377 | (set_attr "type" "jsr") |
077dab3b | 10378 | (set_attr "atype" "agen")]) |
4023fb28 | 10379 | |
4023fb28 | 10380 | |
c7453384 | 10381 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 10382 | ;; pointer. This is used for compatibility. |
c7453384 EC |
10383 | |
10384 | (define_expand "ptr_extend" | |
10385 | [(set (match_operand:DI 0 "register_operand" "=r") | |
10386 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 10387 | "TARGET_64BIT" |
c7453384 | 10388 | { |
c7453384 EC |
10389 | emit_insn (gen_anddi3 (operands[0], |
10390 | gen_lowpart (DImode, operands[1]), | |
10391 | GEN_INT (0x7fffffff))); | |
c7453384 | 10392 | DONE; |
10bbf137 | 10393 | }) |
4798630c D |
10394 | |
10395 | ;; Instruction definition to expand eh_return macro to support | |
10396 | ;; swapping in special linkage return addresses. | |
10397 | ||
10398 | (define_expand "eh_return" | |
10399 | [(use (match_operand 0 "register_operand" ""))] | |
10400 | "TARGET_TPF" | |
10401 | { | |
10402 | s390_emit_tpf_eh_return (operands[0]); | |
10403 | DONE; | |
10404 | }) | |
10405 | ||
7b8acc34 AK |
10406 | ; |
10407 | ; Stack Protector Patterns | |
10408 | ; | |
10409 | ||
10410 | (define_expand "stack_protect_set" | |
10411 | [(set (match_operand 0 "memory_operand" "") | |
10412 | (match_operand 1 "memory_operand" ""))] | |
10413 | "" | |
10414 | { | |
10415 | #ifdef TARGET_THREAD_SSP_OFFSET | |
10416 | operands[1] | |
10417 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
10418 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
10419 | #endif | |
10420 | if (TARGET_64BIT) | |
10421 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
10422 | else | |
10423 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
10424 | ||
10425 | DONE; | |
10426 | }) | |
10427 | ||
10428 | (define_insn "stack_protect_set<mode>" | |
10429 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
10430 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
10431 | "" | |
10432 | "mvc\t%O0(%G0,%R0),%S1" | |
10433 | [(set_attr "op_type" "SS")]) | |
10434 | ||
10435 | (define_expand "stack_protect_test" | |
10436 | [(set (reg:CC CC_REGNUM) | |
10437 | (compare (match_operand 0 "memory_operand" "") | |
10438 | (match_operand 1 "memory_operand" ""))) | |
10439 | (match_operand 2 "" "")] | |
10440 | "" | |
10441 | { | |
f90b7a5a | 10442 | rtx cc_reg, test; |
7b8acc34 AK |
10443 | #ifdef TARGET_THREAD_SSP_OFFSET |
10444 | operands[1] | |
10445 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
10446 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
10447 | #endif | |
7b8acc34 AK |
10448 | if (TARGET_64BIT) |
10449 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
10450 | else | |
10451 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
10452 | ||
f90b7a5a PB |
10453 | cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); |
10454 | test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); | |
10455 | emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); | |
7b8acc34 AK |
10456 | DONE; |
10457 | }) | |
10458 | ||
10459 | (define_insn "stack_protect_test<mode>" | |
10460 | [(set (reg:CCZ CC_REGNUM) | |
10461 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
10462 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
10463 | "" | |
10464 | "clc\t%O0(%G0,%R0),%S1" | |
10465 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
10466 | |
10467 | ; This is used in s390_emit_prologue in order to prevent insns | |
10468 | ; adjusting the stack pointer to be moved over insns writing stack | |
10469 | ; slots using a copy of the stack pointer in a different register. | |
10470 | (define_insn "stack_tie" | |
10471 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
10472 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
10473 | "" | |
10474 | "" | |
10475 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
10476 | |
10477 | ||
10478 | ; | |
10479 | ; Data prefetch patterns | |
10480 | ; | |
10481 | ||
10482 | (define_insn "prefetch" | |
22d72dbc AK |
10483 | [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X") |
10484 | (match_operand:SI 1 "const_int_operand" " n,n") | |
10485 | (match_operand:SI 2 "const_int_operand" " n,n"))] | |
10486 | "TARGET_Z10" | |
963fc8d0 | 10487 | { |
4fe6dea8 AK |
10488 | switch (which_alternative) |
10489 | { | |
10490 | case 0: | |
4fe6dea8 | 10491 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; |
22d72dbc | 10492 | case 1: |
4fe6dea8 AK |
10493 | if (larl_operand (operands[0], Pmode)) |
10494 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
10495 | default: | |
10496 | ||
10497 | /* This might be reached for symbolic operands with an odd | |
10498 | addend. We simply omit the prefetch for such rare cases. */ | |
10499 | ||
10500 | return ""; | |
10501 | } | |
9381e3f1 | 10502 | } |
22d72dbc AK |
10503 | [(set_attr "type" "load,larl") |
10504 | (set_attr "op_type" "RXY,RIL") | |
65b1d8ea AK |
10505 | (set_attr "z10prop" "z10_super") |
10506 | (set_attr "z196prop" "z196_alone")]) | |
07da44ab AK |
10507 | |
10508 | ||
10509 | ; | |
10510 | ; Byte swap instructions | |
10511 | ; | |
10512 | ||
511f5bb1 AK |
10513 | ; FIXME: There is also mvcin but we cannot use it since src and target |
10514 | ; may overlap. | |
07da44ab | 10515 | (define_insn "bswap<mode>2" |
6f5a59d1 AK |
10516 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,RT") |
10517 | (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT, d")))] | |
677fbff4 | 10518 | "TARGET_CPU_ZARCH" |
07da44ab AK |
10519 | "@ |
10520 | lrv<g>r\t%0,%1 | |
6f5a59d1 AK |
10521 | lrv<g>\t%0,%1 |
10522 | strv<g>\t%1,%0" | |
10523 | [(set_attr "type" "*,load,store") | |
10524 | (set_attr "op_type" "RRE,RXY,RXY") | |
07da44ab | 10525 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 10526 | |
511f5bb1 | 10527 | (define_insn "bswaphi2" |
6f5a59d1 AK |
10528 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d, d,RT") |
10529 | (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,RT, d")))] | |
511f5bb1 | 10530 | "TARGET_CPU_ZARCH" |
6f5a59d1 AK |
10531 | "@ |
10532 | # | |
10533 | lrvh\t%0,%1 | |
10534 | strvh\t%1,%0" | |
10535 | [(set_attr "type" "*,load,store") | |
10536 | (set_attr "op_type" "RRE,RXY,RXY") | |
511f5bb1 | 10537 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 10538 | |
6f5a59d1 AK |
10539 | (define_split |
10540 | [(set (match_operand:HI 0 "register_operand" "") | |
10541 | (bswap:HI (match_operand:HI 1 "register_operand" "")))] | |
10542 | "TARGET_CPU_ZARCH" | |
10543 | [(set (match_dup 2) (bswap:SI (match_dup 3))) | |
9060e335 | 10544 | (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))] |
6f5a59d1 | 10545 | { |
9060e335 | 10546 | operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0); |
6f5a59d1 AK |
10547 | operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0); |
10548 | }) | |
10549 | ||
10550 | ||
65b1d8ea AK |
10551 | ; |
10552 | ; Population count instruction | |
10553 | ; | |
10554 | ||
10555 | ; The S/390 popcount instruction counts the bits of op1 in 8 byte | |
10556 | ; portions and stores the result in the corresponding bytes in op0. | |
10557 | (define_insn "*popcount<mode>" | |
10558 | [(set (match_operand:INT 0 "register_operand" "=d") | |
10559 | (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) | |
10560 | (clobber (reg:CC CC_REGNUM))] | |
10561 | "TARGET_Z196" | |
10562 | "popcnt\t%0,%1" | |
10563 | [(set_attr "op_type" "RRE")]) | |
10564 | ||
10565 | (define_expand "popcountdi2" | |
10566 | [; popcnt op0, op1 | |
10567 | (parallel [(set (match_operand:DI 0 "register_operand" "") | |
10568 | (unspec:DI [(match_operand:DI 1 "register_operand")] | |
10569 | UNSPEC_POPCNT)) | |
10570 | (clobber (reg:CC CC_REGNUM))]) | |
10571 | ; sllg op2, op0, 32 | |
10572 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) | |
10573 | ; agr op0, op2 | |
10574 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10575 | (clobber (reg:CC CC_REGNUM))]) | |
10576 | ; sllg op2, op0, 16 | |
17465c6e | 10577 | (set (match_dup 2) |
65b1d8ea AK |
10578 | (ashift:DI (match_dup 0) (const_int 16))) |
10579 | ; agr op0, op2 | |
10580 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10581 | (clobber (reg:CC CC_REGNUM))]) | |
10582 | ; sllg op2, op0, 8 | |
10583 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) | |
10584 | ; agr op0, op2 | |
10585 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10586 | (clobber (reg:CC CC_REGNUM))]) | |
10587 | ; srlg op0, op0, 56 | |
10588 | (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] | |
10589 | "TARGET_Z196 && TARGET_64BIT" | |
10590 | "operands[2] = gen_reg_rtx (DImode);") | |
10591 | ||
10592 | (define_expand "popcountsi2" | |
10593 | [; popcnt op0, op1 | |
10594 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
10595 | (unspec:SI [(match_operand:SI 1 "register_operand")] | |
10596 | UNSPEC_POPCNT)) | |
10597 | (clobber (reg:CC CC_REGNUM))]) | |
10598 | ; sllk op2, op0, 16 | |
17465c6e | 10599 | (set (match_dup 2) |
65b1d8ea AK |
10600 | (ashift:SI (match_dup 0) (const_int 16))) |
10601 | ; ar op0, op2 | |
10602 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
10603 | (clobber (reg:CC CC_REGNUM))]) | |
10604 | ; sllk op2, op0, 8 | |
10605 | (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) | |
10606 | ; ar op0, op2 | |
10607 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
10608 | (clobber (reg:CC CC_REGNUM))]) | |
10609 | ; srl op0, op0, 24 | |
10610 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | |
10611 | "TARGET_Z196" | |
10612 | "operands[2] = gen_reg_rtx (SImode);") | |
10613 | ||
10614 | (define_expand "popcounthi2" | |
10615 | [; popcnt op0, op1 | |
10616 | (parallel [(set (match_operand:HI 0 "register_operand" "") | |
10617 | (unspec:HI [(match_operand:HI 1 "register_operand")] | |
10618 | UNSPEC_POPCNT)) | |
10619 | (clobber (reg:CC CC_REGNUM))]) | |
10620 | ; sllk op2, op0, 8 | |
17465c6e | 10621 | (set (match_dup 2) |
65b1d8ea AK |
10622 | (ashift:SI (match_dup 0) (const_int 8))) |
10623 | ; ar op0, op2 | |
10624 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
10625 | (clobber (reg:CC CC_REGNUM))]) | |
10626 | ; srl op0, op0, 8 | |
10627 | (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] | |
10628 | "TARGET_Z196" | |
10629 | "operands[2] = gen_reg_rtx (SImode);") | |
10630 | ||
10631 | (define_expand "popcountqi2" | |
10632 | [; popcnt op0, op1 | |
10633 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
10634 | (unspec:QI [(match_operand:QI 1 "register_operand")] | |
10635 | UNSPEC_POPCNT)) | |
10636 | (clobber (reg:CC CC_REGNUM))])] | |
10637 | "TARGET_Z196" | |
10638 | "") | |
10639 | ||
10640 | ;; | |
10641 | ;;- Copy sign instructions | |
10642 | ;; | |
10643 | ||
10644 | (define_insn "copysign<mode>3" | |
10645 | [(set (match_operand:FP 0 "register_operand" "=f") | |
10646 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
10647 | (match_operand:FP 2 "register_operand" "f")] | |
10648 | UNSPEC_COPYSIGN))] | |
10649 | "TARGET_Z196" | |
10650 | "cpsdr\t%0,%2,%1" | |
10651 | [(set_attr "op_type" "RRF") | |
10652 | (set_attr "type" "fsimp<mode>")]) | |
5a3fe9b6 AK |
10653 | |
10654 | ||
10655 | ;; | |
10656 | ;;- Transactional execution instructions | |
10657 | ;; | |
10658 | ||
10659 | ; This splitter helps combine to make use of CC directly when | |
10660 | ; comparing the integer result of a tbegin builtin with a constant. | |
10661 | ; The unspec is already removed by canonicalize_comparison. So this | |
10662 | ; splitters only job is to turn the PARALLEL into separate insns | |
10663 | ; again. Unfortunately this only works with the very first cc/int | |
10664 | ; compare since combine is not able to deal with data flow across | |
10665 | ; basic block boundaries. | |
10666 | ||
10667 | ; It needs to be an insn pattern as well since combine does not apply | |
10668 | ; the splitter directly. Combine would only use it if it actually | |
10669 | ; would reduce the number of instructions. | |
10670 | (define_insn_and_split "*ccraw_to_int" | |
10671 | [(set (pc) | |
10672 | (if_then_else | |
10673 | (match_operator 0 "s390_eqne_operator" | |
10674 | [(reg:CCRAW CC_REGNUM) | |
10675 | (match_operand 1 "const_int_operand" "")]) | |
10676 | (label_ref (match_operand 2 "" "")) | |
10677 | (pc))) | |
10678 | (set (match_operand:SI 3 "register_operand" "=d") | |
10679 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] | |
10680 | "" | |
10681 | "#" | |
10682 | "" | |
10683 | [(set (match_dup 3) | |
10684 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) | |
10685 | (set (pc) | |
10686 | (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)]) | |
10687 | (label_ref (match_dup 2)) | |
10688 | (pc)))] | |
10689 | "") | |
10690 | ||
10691 | ; Non-constrained transaction begin | |
10692 | ||
10693 | (define_expand "tbegin" | |
ee163e72 AK |
10694 | [(match_operand:SI 0 "register_operand" "") |
10695 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
10696 | "TARGET_HTM" |
10697 | { | |
10698 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true); | |
10699 | DONE; | |
10700 | }) | |
10701 | ||
10702 | (define_expand "tbegin_nofloat" | |
ee163e72 AK |
10703 | [(match_operand:SI 0 "register_operand" "") |
10704 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
10705 | "TARGET_HTM" |
10706 | { | |
10707 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false); | |
10708 | DONE; | |
10709 | }) | |
10710 | ||
10711 | (define_expand "tbegin_retry" | |
ee163e72 AK |
10712 | [(match_operand:SI 0 "register_operand" "") |
10713 | (match_operand:BLK 1 "memory_operand" "") | |
10714 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
10715 | "TARGET_HTM" |
10716 | { | |
10717 | s390_expand_tbegin (operands[0], operands[1], operands[2], true); | |
10718 | DONE; | |
10719 | }) | |
10720 | ||
10721 | (define_expand "tbegin_retry_nofloat" | |
ee163e72 AK |
10722 | [(match_operand:SI 0 "register_operand" "") |
10723 | (match_operand:BLK 1 "memory_operand" "") | |
10724 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
10725 | "TARGET_HTM" |
10726 | { | |
10727 | s390_expand_tbegin (operands[0], operands[1], operands[2], false); | |
10728 | DONE; | |
10729 | }) | |
10730 | ||
c914ac45 AK |
10731 | ; Clobber VRs since they don't get restored |
10732 | (define_insn "tbegin_1_z13" | |
10733 | [(set (reg:CCRAW CC_REGNUM) | |
10734 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] | |
10735 | UNSPECV_TBEGIN)) | |
10736 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
10737 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
10738 | (clobber (reg:TI 16)) (clobber (reg:TI 38)) | |
10739 | (clobber (reg:TI 17)) (clobber (reg:TI 39)) | |
10740 | (clobber (reg:TI 18)) (clobber (reg:TI 40)) | |
10741 | (clobber (reg:TI 19)) (clobber (reg:TI 41)) | |
10742 | (clobber (reg:TI 20)) (clobber (reg:TI 42)) | |
10743 | (clobber (reg:TI 21)) (clobber (reg:TI 43)) | |
10744 | (clobber (reg:TI 22)) (clobber (reg:TI 44)) | |
10745 | (clobber (reg:TI 23)) (clobber (reg:TI 45)) | |
10746 | (clobber (reg:TI 24)) (clobber (reg:TI 46)) | |
10747 | (clobber (reg:TI 25)) (clobber (reg:TI 47)) | |
10748 | (clobber (reg:TI 26)) (clobber (reg:TI 48)) | |
10749 | (clobber (reg:TI 27)) (clobber (reg:TI 49)) | |
10750 | (clobber (reg:TI 28)) (clobber (reg:TI 50)) | |
10751 | (clobber (reg:TI 29)) (clobber (reg:TI 51)) | |
10752 | (clobber (reg:TI 30)) (clobber (reg:TI 52)) | |
10753 | (clobber (reg:TI 31)) (clobber (reg:TI 53))] | |
10754 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
10755 | ; not supposed to be used for immediates (see genpreds.c). | |
10756 | "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
10757 | "tbegin\t%1,%x0" | |
10758 | [(set_attr "op_type" "SIL")]) | |
10759 | ||
5a3fe9b6 AK |
10760 | (define_insn "tbegin_1" |
10761 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d | 10762 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
5a3fe9b6 | 10763 | UNSPECV_TBEGIN)) |
2561451d AK |
10764 | (set (match_operand:BLK 1 "memory_operand" "=Q") |
10765 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
5a3fe9b6 AK |
10766 | (clobber (reg:DF 16)) |
10767 | (clobber (reg:DF 17)) | |
10768 | (clobber (reg:DF 18)) | |
10769 | (clobber (reg:DF 19)) | |
10770 | (clobber (reg:DF 20)) | |
10771 | (clobber (reg:DF 21)) | |
10772 | (clobber (reg:DF 22)) | |
10773 | (clobber (reg:DF 23)) | |
10774 | (clobber (reg:DF 24)) | |
10775 | (clobber (reg:DF 25)) | |
10776 | (clobber (reg:DF 26)) | |
10777 | (clobber (reg:DF 27)) | |
10778 | (clobber (reg:DF 28)) | |
10779 | (clobber (reg:DF 29)) | |
10780 | (clobber (reg:DF 30)) | |
10781 | (clobber (reg:DF 31))] | |
10782 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
10783 | ; not supposed to be used for immediates (see genpreds.c). | |
2561451d AK |
10784 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" |
10785 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
10786 | [(set_attr "op_type" "SIL")]) |
10787 | ||
10788 | ; Same as above but without the FPR clobbers | |
10789 | (define_insn "tbegin_nofloat_1" | |
10790 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d AK |
10791 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
10792 | UNSPECV_TBEGIN)) | |
10793 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
10794 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))] | |
10795 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
10796 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
10797 | [(set_attr "op_type" "SIL")]) |
10798 | ||
10799 | ||
10800 | ; Constrained transaction begin | |
10801 | ||
10802 | (define_expand "tbeginc" | |
10803 | [(set (reg:CCRAW CC_REGNUM) | |
10804 | (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)] | |
10805 | UNSPECV_TBEGINC))] | |
10806 | "TARGET_HTM" | |
10807 | "") | |
10808 | ||
10809 | (define_insn "*tbeginc_1" | |
10810 | [(set (reg:CCRAW CC_REGNUM) | |
10811 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")] | |
10812 | UNSPECV_TBEGINC))] | |
10813 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
10814 | "tbeginc\t0,%x0" | |
10815 | [(set_attr "op_type" "SIL")]) | |
10816 | ||
10817 | ; Transaction end | |
10818 | ||
10819 | (define_expand "tend" | |
10820 | [(set (reg:CCRAW CC_REGNUM) | |
10821 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND)) | |
ee163e72 | 10822 | (set (match_operand:SI 0 "register_operand" "") |
5a3fe9b6 AK |
10823 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] |
10824 | "TARGET_HTM" | |
10825 | "") | |
10826 | ||
10827 | (define_insn "*tend_1" | |
10828 | [(set (reg:CCRAW CC_REGNUM) | |
10829 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))] | |
10830 | "TARGET_HTM" | |
10831 | "tend" | |
10832 | [(set_attr "op_type" "S")]) | |
10833 | ||
10834 | ; Transaction abort | |
10835 | ||
10836 | (define_expand "tabort" | |
ee163e72 | 10837 | [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "")] |
5a3fe9b6 AK |
10838 | UNSPECV_TABORT)] |
10839 | "TARGET_HTM && operands != NULL" | |
10840 | { | |
10841 | if (CONST_INT_P (operands[0]) | |
10842 | && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255) | |
10843 | { | |
10844 | error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC | |
10845 | ". Values in range 0 through 255 are reserved.", | |
10846 | INTVAL (operands[0])); | |
10847 | FAIL; | |
10848 | } | |
10849 | }) | |
10850 | ||
10851 | (define_insn "*tabort_1" | |
ee163e72 | 10852 | [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "Y")] |
5a3fe9b6 AK |
10853 | UNSPECV_TABORT)] |
10854 | "TARGET_HTM && operands != NULL" | |
10855 | "tabort\t%Y0" | |
10856 | [(set_attr "op_type" "S")]) | |
10857 | ||
10858 | ; Transaction extract nesting depth | |
10859 | ||
10860 | (define_insn "etnd" | |
10861 | [(set (match_operand:SI 0 "register_operand" "=d") | |
10862 | (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))] | |
10863 | "TARGET_HTM" | |
10864 | "etnd\t%0" | |
10865 | [(set_attr "op_type" "RRE")]) | |
10866 | ||
10867 | ; Non-transactional store | |
10868 | ||
10869 | (define_insn "ntstg" | |
10870 | [(set (match_operand:DI 0 "memory_operand" "=RT") | |
10871 | (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] | |
10872 | UNSPECV_NTSTG))] | |
10873 | "TARGET_HTM" | |
10874 | "ntstg\t%1,%0" | |
10875 | [(set_attr "op_type" "RXY")]) | |
10876 | ||
10877 | ; Transaction perform processor assist | |
10878 | ||
10879 | (define_expand "tx_assist" | |
2561451d AK |
10880 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "") |
10881 | (reg:SI GPR0_REGNUM) | |
5a3fe9b6 AK |
10882 | (const_int 1)] |
10883 | UNSPECV_PPA)] | |
10884 | "TARGET_HTM" | |
2561451d | 10885 | "") |
5a3fe9b6 AK |
10886 | |
10887 | (define_insn "*ppa" | |
10888 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") | |
10889 | (match_operand:SI 1 "register_operand" "d") | |
10890 | (match_operand 2 "const_int_operand" "I")] | |
10891 | UNSPECV_PPA)] | |
10892 | "TARGET_HTM && INTVAL (operands[2]) < 16" | |
2561451d | 10893 | "ppa\t%0,%1,%2" |
5a3fe9b6 | 10894 | [(set_attr "op_type" "RRF")]) |
004f64e1 AK |
10895 | |
10896 | ||
10897 | ; Set and get floating point control register | |
10898 | ||
3af82a61 | 10899 | (define_insn "sfpc" |
004f64e1 AK |
10900 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] |
10901 | UNSPECV_SFPC)] | |
10902 | "TARGET_HARD_FLOAT" | |
10903 | "sfpc\t%0") | |
10904 | ||
3af82a61 | 10905 | (define_insn "efpc" |
004f64e1 AK |
10906 | [(set (match_operand:SI 0 "register_operand" "=d") |
10907 | (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))] | |
10908 | "TARGET_HARD_FLOAT" | |
10909 | "efpc\t%0") | |
3af82a61 AK |
10910 | |
10911 | ||
10912 | ; Load count to block boundary | |
10913 | ||
10914 | (define_insn "lcbb" | |
10915 | [(set (match_operand:SI 0 "register_operand" "=d") | |
10916 | (unspec:SI [(match_operand:SI 1 "address_operand" "ZQZR") | |
10917 | (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB)) | |
10918 | (clobber (reg:CC CC_REGNUM))] | |
10919 | "TARGET_Z13" | |
10920 | "lcbb\t%0,%1,%b2" | |
10921 | [(set_attr "op_type" "VRX")]) | |
4cb4721f MK |
10922 | |
10923 | ; Handle -fsplit-stack. | |
10924 | ||
10925 | (define_expand "split_stack_prologue" | |
10926 | [(const_int 0)] | |
10927 | "" | |
10928 | { | |
10929 | s390_expand_split_stack_prologue (); | |
10930 | DONE; | |
10931 | }) | |
10932 | ||
10933 | ;; If there are operand 0 bytes available on the stack, jump to | |
10934 | ;; operand 1. | |
10935 | ||
10936 | (define_expand "split_stack_space_check" | |
10937 | [(set (pc) (if_then_else | |
10938 | (ltu (minus (reg 15) | |
10939 | (match_operand 0 "register_operand")) | |
10940 | (unspec [(const_int 0)] UNSPEC_STACK_CHECK)) | |
10941 | (label_ref (match_operand 1)) | |
10942 | (pc)))] | |
10943 | "" | |
10944 | { | |
10945 | /* Offset from thread pointer to __private_ss. */ | |
10946 | int psso = TARGET_64BIT ? 0x38 : 0x20; | |
10947 | rtx tp = s390_get_thread_pointer (); | |
10948 | rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso)); | |
10949 | rtx reg = gen_reg_rtx (Pmode); | |
10950 | rtx cc; | |
10951 | if (TARGET_64BIT) | |
10952 | emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0])); | |
10953 | else | |
10954 | emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0])); | |
10955 | cc = s390_emit_compare (GT, reg, guard); | |
10956 | s390_emit_jump (operands[1], cc); | |
10957 | ||
10958 | DONE; | |
10959 | }) | |
10960 | ||
10961 | ;; __morestack parameter block for split stack prologue. Parameters are: | |
10962 | ;; parameter block label, label to be called by __morestack, frame size, | |
10963 | ;; stack parameter size. | |
10964 | ||
10965 | (define_insn "split_stack_data" | |
10966 | [(unspec_volatile [(match_operand 0 "" "X") | |
10967 | (match_operand 1 "" "X") | |
10968 | (match_operand 2 "const_int_operand" "X") | |
10969 | (match_operand 3 "const_int_operand" "X")] | |
10970 | UNSPECV_SPLIT_STACK_DATA)] | |
10971 | "TARGET_CPU_ZARCH" | |
10972 | { | |
10973 | switch_to_section (targetm.asm_out.function_rodata_section | |
10974 | (current_function_decl)); | |
10975 | ||
10976 | if (TARGET_64BIT) | |
10977 | output_asm_insn (".align\t8", operands); | |
10978 | else | |
10979 | output_asm_insn (".align\t4", operands); | |
10980 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
10981 | CODE_LABEL_NUMBER (operands[0])); | |
10982 | if (TARGET_64BIT) | |
10983 | { | |
10984 | output_asm_insn (".quad\t%2", operands); | |
10985 | output_asm_insn (".quad\t%3", operands); | |
10986 | output_asm_insn (".quad\t%1-%0", operands); | |
10987 | } | |
10988 | else | |
10989 | { | |
10990 | output_asm_insn (".long\t%2", operands); | |
10991 | output_asm_insn (".long\t%3", operands); | |
10992 | output_asm_insn (".long\t%1-%0", operands); | |
10993 | } | |
10994 | ||
10995 | switch_to_section (current_function_section ()); | |
10996 | return ""; | |
10997 | } | |
10998 | [(set_attr "length" "0")]) | |
10999 | ||
11000 | ||
11001 | ;; A jg with minimal fuss for use in split stack prologue. | |
11002 | ||
11003 | (define_expand "split_stack_call" | |
11004 | [(match_operand 0 "bras_sym_operand" "X") | |
11005 | (match_operand 1 "" "")] | |
11006 | "TARGET_CPU_ZARCH" | |
11007 | { | |
11008 | if (TARGET_64BIT) | |
11009 | emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1])); | |
11010 | else | |
11011 | emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1])); | |
11012 | DONE; | |
11013 | }) | |
11014 | ||
11015 | (define_insn "split_stack_call_<mode>" | |
11016 | [(set (pc) (label_ref (match_operand 1 "" ""))) | |
11017 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
11018 | (reg:P 1)] | |
11019 | UNSPECV_SPLIT_STACK_CALL))] | |
11020 | "TARGET_CPU_ZARCH" | |
11021 | "jg\t%0" | |
11022 | [(set_attr "op_type" "RIL") | |
11023 | (set_attr "type" "branch")]) | |
11024 | ||
11025 | ;; Also a conditional one. | |
11026 | ||
11027 | (define_expand "split_stack_cond_call" | |
11028 | [(match_operand 0 "bras_sym_operand" "X") | |
11029 | (match_operand 1 "" "") | |
11030 | (match_operand 2 "" "")] | |
11031 | "TARGET_CPU_ZARCH" | |
11032 | { | |
11033 | if (TARGET_64BIT) | |
11034 | emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2])); | |
11035 | else | |
11036 | emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2])); | |
11037 | DONE; | |
11038 | }) | |
11039 | ||
11040 | (define_insn "split_stack_cond_call_<mode>" | |
11041 | [(set (pc) | |
11042 | (if_then_else | |
11043 | (match_operand 1 "" "") | |
11044 | (label_ref (match_operand 2 "" "")) | |
11045 | (pc))) | |
11046 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
11047 | (reg:P 1)] | |
11048 | UNSPECV_SPLIT_STACK_CALL))] | |
11049 | "TARGET_CPU_ZARCH" | |
11050 | "jg%C1\t%0" | |
11051 | [(set_attr "op_type" "RIL") | |
11052 | (set_attr "type" "branch")]) |