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Commit | Line | Data |
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9db1d521 | 1 | ;;- Machine description for GNU compiler -- S/390 / zSeries version. |
cbe34bb5 | 2 | ;; Copyright (C) 1999-2017 Free Software Foundation, Inc. |
9db1d521 | 3 | ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and |
963fc8d0 AK |
4 | ;; Ulrich Weigand (uweigand@de.ibm.com) and |
5 | ;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) | |
9db1d521 | 6 | |
58add37a UW |
7 | ;; This file is part of GCC. |
8 | ||
9 | ;; GCC is free software; you can redistribute it and/or modify it under | |
10 | ;; the terms of the GNU General Public License as published by the Free | |
2f83c7d6 | 11 | ;; Software Foundation; either version 3, or (at your option) any later |
58add37a UW |
12 | ;; version. |
13 | ||
14 | ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY | |
15 | ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
17 | ;; for more details. | |
9db1d521 HP |
18 | |
19 | ;; You should have received a copy of the GNU General Public License | |
2f83c7d6 NC |
20 | ;; along with GCC; see the file COPYING3. If not see |
21 | ;; <http://www.gnu.org/licenses/>. | |
9db1d521 HP |
22 | |
23 | ;; | |
cd8dc1f9 | 24 | ;; See constraints.md for a description of constraints specific to s390. |
9db1d521 | 25 | ;; |
cd8dc1f9 | 26 | |
9db1d521 HP |
27 | ;; Special formats used for outputting 390 instructions. |
28 | ;; | |
f19a9af7 AK |
29 | ;; %C: print opcode suffix for branch condition. |
30 | ;; %D: print opcode suffix for inverse branch condition. | |
31 | ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix | |
da48f5ec | 32 | ;; %G: print the size of the operand in bytes. |
f19a9af7 AK |
33 | ;; %O: print only the displacement of a memory reference. |
34 | ;; %R: print only the base register of a memory reference. | |
fc0ea003 | 35 | ;; %S: print S-type memory reference (base+displacement). |
f19a9af7 AK |
36 | ;; %N: print the second word of a DImode operand. |
37 | ;; %M: print the second word of a TImode operand. | |
da48f5ec | 38 | ;; %Y: print shift count operand. |
f4aa3848 | 39 | ;; |
f19a9af7 | 40 | ;; %b: print integer X as if it's an unsigned byte. |
963fc8d0 | 41 | ;; %c: print integer X as if it's an signed byte. |
da48f5ec AK |
42 | ;; %x: print integer X as if it's an unsigned halfword. |
43 | ;; %h: print integer X as if it's a signed halfword. | |
44 | ;; %i: print the first nonzero HImode part of X. | |
45 | ;; %j: print the first HImode part unequal to -1 of X. | |
46 | ;; %k: print the first nonzero SImode part of X. | |
47 | ;; %m: print the first SImode part unequal to -1 of X. | |
48 | ;; %o: print integer X as if it's an unsigned 32bit word. | |
9db1d521 HP |
49 | ;; |
50 | ;; We have a special constraint for pattern matching. | |
51 | ;; | |
52 | ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. | |
53 | ;; | |
9db1d521 | 54 | |
fd3cd001 UW |
55 | ;; |
56 | ;; UNSPEC usage | |
57 | ;; | |
58 | ||
30a49b23 AK |
59 | (define_c_enum "unspec" [ |
60 | ; Miscellaneous | |
61 | UNSPEC_ROUND | |
30a49b23 AK |
62 | UNSPEC_ICM |
63 | UNSPEC_TIE | |
10bbf137 | 64 | |
5a3fe9b6 AK |
65 | ; Convert CC into a str comparison result and copy it into an |
66 | ; integer register | |
67 | ; cc0->0, cc1->1, cc2->-1, (cc3->-1) | |
68 | UNSPEC_STRCMPCC_TO_INT | |
69 | ||
70 | ; Copy CC as is into the lower 2 bits of an integer register | |
71 | UNSPEC_CC_TO_INT | |
72 | ||
da0dcab1 DV |
73 | ; The right hand side of an setmem |
74 | UNSPEC_REPLICATE_BYTE | |
75 | ||
10bbf137 | 76 | ; GOT/PLT and lt-relative accesses |
30a49b23 AK |
77 | UNSPEC_LTREL_OFFSET |
78 | UNSPEC_LTREL_BASE | |
79 | UNSPEC_POOL_OFFSET | |
80 | UNSPEC_GOTENT | |
81 | UNSPEC_GOT | |
82 | UNSPEC_GOTOFF | |
83 | UNSPEC_PLT | |
84 | UNSPEC_PLTOFF | |
fd7643fb UW |
85 | |
86 | ; Literal pool | |
30a49b23 AK |
87 | UNSPEC_RELOAD_BASE |
88 | UNSPEC_MAIN_BASE | |
89 | UNSPEC_LTREF | |
90 | UNSPEC_INSN | |
91 | UNSPEC_EXECUTE | |
fd7643fb | 92 | |
1a8c13b3 | 93 | ; Atomic Support |
30a49b23 | 94 | UNSPEC_MB |
78ce265b | 95 | UNSPEC_MOVA |
1a8c13b3 | 96 | |
fd7643fb | 97 | ; TLS relocation specifiers |
30a49b23 AK |
98 | UNSPEC_TLSGD |
99 | UNSPEC_TLSLDM | |
100 | UNSPEC_NTPOFF | |
101 | UNSPEC_DTPOFF | |
102 | UNSPEC_GOTNTPOFF | |
103 | UNSPEC_INDNTPOFF | |
fd3cd001 UW |
104 | |
105 | ; TLS support | |
30a49b23 AK |
106 | UNSPEC_TLSLDM_NTPOFF |
107 | UNSPEC_TLS_LOAD | |
91d39d71 UW |
108 | |
109 | ; String Functions | |
30a49b23 AK |
110 | UNSPEC_SRST |
111 | UNSPEC_MVST | |
638e37c2 | 112 | |
7b8acc34 | 113 | ; Stack Smashing Protector |
30a49b23 AK |
114 | UNSPEC_SP_SET |
115 | UNSPEC_SP_TEST | |
85dae55a | 116 | |
4cb4721f MK |
117 | ; Split stack support |
118 | UNSPEC_STACK_CHECK | |
119 | ||
638e37c2 | 120 | ; Test Data Class (TDC) |
30a49b23 | 121 | UNSPEC_TDC_INSN |
65b1d8ea AK |
122 | |
123 | ; Population Count | |
30a49b23 AK |
124 | UNSPEC_POPCNT |
125 | UNSPEC_COPYSIGN | |
d12a76f3 AK |
126 | |
127 | ; Load FP Integer | |
128 | UNSPEC_FPINT_FLOOR | |
129 | UNSPEC_FPINT_BTRUNC | |
130 | UNSPEC_FPINT_ROUND | |
131 | UNSPEC_FPINT_CEIL | |
132 | UNSPEC_FPINT_NEARBYINT | |
133 | UNSPEC_FPINT_RINT | |
085261c8 | 134 | |
3af82a61 AK |
135 | UNSPEC_LCBB |
136 | ||
085261c8 | 137 | ; Vector |
3af82a61 AK |
138 | UNSPEC_VEC_SMULT_HI |
139 | UNSPEC_VEC_UMULT_HI | |
140 | UNSPEC_VEC_SMULT_LO | |
085261c8 AK |
141 | UNSPEC_VEC_SMULT_EVEN |
142 | UNSPEC_VEC_UMULT_EVEN | |
143 | UNSPEC_VEC_SMULT_ODD | |
144 | UNSPEC_VEC_UMULT_ODD | |
3af82a61 AK |
145 | |
146 | UNSPEC_VEC_VMAL | |
147 | UNSPEC_VEC_VMAH | |
148 | UNSPEC_VEC_VMALH | |
149 | UNSPEC_VEC_VMAE | |
150 | UNSPEC_VEC_VMALE | |
151 | UNSPEC_VEC_VMAO | |
152 | UNSPEC_VEC_VMALO | |
153 | ||
154 | UNSPEC_VEC_GATHER | |
155 | UNSPEC_VEC_EXTRACT | |
156 | UNSPEC_VEC_INSERT_AND_ZERO | |
157 | UNSPEC_VEC_LOAD_BNDRY | |
085261c8 | 158 | UNSPEC_VEC_LOAD_LEN |
3af82a61 AK |
159 | UNSPEC_VEC_MERGEH |
160 | UNSPEC_VEC_MERGEL | |
161 | UNSPEC_VEC_PACK | |
162 | UNSPEC_VEC_PACK_SATURATE | |
163 | UNSPEC_VEC_PACK_SATURATE_CC | |
164 | UNSPEC_VEC_PACK_SATURATE_GENCC | |
165 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE | |
166 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC | |
167 | UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC | |
168 | UNSPEC_VEC_PERM | |
169 | UNSPEC_VEC_PERMI | |
170 | UNSPEC_VEC_EXTEND | |
171 | UNSPEC_VEC_STORE_LEN | |
172 | UNSPEC_VEC_UNPACKH | |
173 | UNSPEC_VEC_UNPACKH_L | |
174 | UNSPEC_VEC_UNPACKL | |
175 | UNSPEC_VEC_UNPACKL_L | |
176 | UNSPEC_VEC_ADDC | |
3af82a61 AK |
177 | UNSPEC_VEC_ADDE_U128 |
178 | UNSPEC_VEC_ADDEC_U128 | |
179 | UNSPEC_VEC_AVG | |
180 | UNSPEC_VEC_AVGU | |
181 | UNSPEC_VEC_CHECKSUM | |
182 | UNSPEC_VEC_GFMSUM | |
183 | UNSPEC_VEC_GFMSUM_128 | |
184 | UNSPEC_VEC_GFMSUM_ACCUM | |
185 | UNSPEC_VEC_GFMSUM_ACCUM_128 | |
186 | UNSPEC_VEC_SET | |
187 | ||
188 | UNSPEC_VEC_VSUMG | |
189 | UNSPEC_VEC_VSUMQ | |
190 | UNSPEC_VEC_VSUM | |
191 | UNSPEC_VEC_RL_MASK | |
192 | UNSPEC_VEC_SLL | |
193 | UNSPEC_VEC_SLB | |
194 | UNSPEC_VEC_SLDB | |
195 | UNSPEC_VEC_SRAL | |
196 | UNSPEC_VEC_SRAB | |
197 | UNSPEC_VEC_SRL | |
198 | UNSPEC_VEC_SRLB | |
199 | ||
3af82a61 | 200 | UNSPEC_VEC_SUBC |
3af82a61 AK |
201 | UNSPEC_VEC_SUBE_U128 |
202 | UNSPEC_VEC_SUBEC_U128 | |
203 | ||
204 | UNSPEC_VEC_TEST_MASK | |
205 | ||
206 | UNSPEC_VEC_VFAE | |
207 | UNSPEC_VEC_VFAECC | |
208 | ||
209 | UNSPEC_VEC_VFEE | |
210 | UNSPEC_VEC_VFEECC | |
085261c8 AK |
211 | UNSPEC_VEC_VFENE |
212 | UNSPEC_VEC_VFENECC | |
3af82a61 AK |
213 | |
214 | UNSPEC_VEC_VISTR | |
215 | UNSPEC_VEC_VISTRCC | |
216 | ||
217 | UNSPEC_VEC_VSTRC | |
218 | UNSPEC_VEC_VSTRCCC | |
219 | ||
220 | UNSPEC_VEC_VCDGB | |
221 | UNSPEC_VEC_VCDLGB | |
222 | ||
223 | UNSPEC_VEC_VCGDB | |
224 | UNSPEC_VEC_VCLGDB | |
225 | ||
226 | UNSPEC_VEC_VFIDB | |
227 | ||
228 | UNSPEC_VEC_VLDEB | |
229 | UNSPEC_VEC_VLEDB | |
230 | ||
231 | UNSPEC_VEC_VFTCIDB | |
232 | UNSPEC_VEC_VFTCIDBCC | |
085261c8 | 233 | ]) |
fd3cd001 UW |
234 | |
235 | ;; | |
236 | ;; UNSPEC_VOLATILE usage | |
237 | ;; | |
238 | ||
30a49b23 AK |
239 | (define_c_enum "unspecv" [ |
240 | ; Blockage | |
241 | UNSPECV_BLOCKAGE | |
10bbf137 | 242 | |
2f7e5a0d | 243 | ; TPF Support |
30a49b23 AK |
244 | UNSPECV_TPF_PROLOGUE |
245 | UNSPECV_TPF_EPILOGUE | |
2f7e5a0d | 246 | |
10bbf137 | 247 | ; Literal pool |
30a49b23 AK |
248 | UNSPECV_POOL |
249 | UNSPECV_POOL_SECTION | |
250 | UNSPECV_POOL_ALIGN | |
251 | UNSPECV_POOL_ENTRY | |
252 | UNSPECV_MAIN_POOL | |
fd7643fb UW |
253 | |
254 | ; TLS support | |
30a49b23 | 255 | UNSPECV_SET_TP |
e0374221 AS |
256 | |
257 | ; Atomic Support | |
30a49b23 AK |
258 | UNSPECV_CAS |
259 | UNSPECV_ATOMIC_OP | |
5a3fe9b6 | 260 | |
f8af0e30 DV |
261 | ; Hotpatching (unremovable NOPs) |
262 | UNSPECV_NOP_2_BYTE | |
263 | UNSPECV_NOP_4_BYTE | |
264 | UNSPECV_NOP_6_BYTE | |
265 | ||
5a3fe9b6 AK |
266 | ; Transactional Execution support |
267 | UNSPECV_TBEGIN | |
2561451d | 268 | UNSPECV_TBEGIN_TDB |
5a3fe9b6 AK |
269 | UNSPECV_TBEGINC |
270 | UNSPECV_TEND | |
271 | UNSPECV_TABORT | |
272 | UNSPECV_ETND | |
273 | UNSPECV_NTSTG | |
274 | UNSPECV_PPA | |
004f64e1 AK |
275 | |
276 | ; Set and get floating point control register | |
277 | UNSPECV_SFPC | |
278 | UNSPECV_EFPC | |
4cb4721f MK |
279 | |
280 | ; Split stack support | |
281 | UNSPECV_SPLIT_STACK_CALL | |
282 | UNSPECV_SPLIT_STACK_DATA | |
539405d5 AK |
283 | |
284 | UNSPECV_OSC_BREAK | |
fd3cd001 UW |
285 | ]) |
286 | ||
ae156f85 AS |
287 | ;; |
288 | ;; Registers | |
289 | ;; | |
290 | ||
35dd9a0e AK |
291 | ; Registers with special meaning |
292 | ||
ae156f85 AS |
293 | (define_constants |
294 | [ | |
295 | ; Sibling call register. | |
296 | (SIBCALL_REGNUM 1) | |
297 | ; Literal pool base register. | |
298 | (BASE_REGNUM 13) | |
299 | ; Return address register. | |
300 | (RETURN_REGNUM 14) | |
82c6f58a AK |
301 | ; Stack pointer register. |
302 | (STACK_REGNUM 15) | |
ae156f85 AS |
303 | ; Condition code register. |
304 | (CC_REGNUM 33) | |
f4aa3848 | 305 | ; Thread local storage pointer register. |
ae156f85 AS |
306 | (TP_REGNUM 36) |
307 | ]) | |
308 | ||
35dd9a0e AK |
309 | ; Hardware register names |
310 | ||
311 | (define_constants | |
312 | [ | |
313 | ; General purpose registers | |
314 | (GPR0_REGNUM 0) | |
af344a30 | 315 | (GPR1_REGNUM 1) |
82379bdf AK |
316 | (GPR2_REGNUM 2) |
317 | (GPR6_REGNUM 6) | |
35dd9a0e AK |
318 | ; Floating point registers. |
319 | (FPR0_REGNUM 16) | |
2cf4c39e AK |
320 | (FPR1_REGNUM 20) |
321 | (FPR2_REGNUM 17) | |
322 | (FPR3_REGNUM 21) | |
323 | (FPR4_REGNUM 18) | |
324 | (FPR5_REGNUM 22) | |
325 | (FPR6_REGNUM 19) | |
326 | (FPR7_REGNUM 23) | |
327 | (FPR8_REGNUM 24) | |
328 | (FPR9_REGNUM 28) | |
329 | (FPR10_REGNUM 25) | |
330 | (FPR11_REGNUM 29) | |
331 | (FPR12_REGNUM 26) | |
332 | (FPR13_REGNUM 30) | |
333 | (FPR14_REGNUM 27) | |
334 | (FPR15_REGNUM 31) | |
085261c8 AK |
335 | (VR0_REGNUM 16) |
336 | (VR16_REGNUM 38) | |
337 | (VR23_REGNUM 45) | |
338 | (VR24_REGNUM 46) | |
339 | (VR31_REGNUM 53) | |
35dd9a0e AK |
340 | ]) |
341 | ||
ae8e301e AK |
342 | ; Rounding modes for binary floating point numbers |
343 | (define_constants | |
344 | [(BFP_RND_CURRENT 0) | |
345 | (BFP_RND_NEAREST_TIE_AWAY_FROM_0 1) | |
346 | (BFP_RND_PREP_FOR_SHORT_PREC 3) | |
347 | (BFP_RND_NEAREST_TIE_TO_EVEN 4) | |
348 | (BFP_RND_TOWARD_0 5) | |
349 | (BFP_RND_TOWARD_INF 6) | |
350 | (BFP_RND_TOWARD_MINF 7)]) | |
351 | ||
352 | ; Rounding modes for decimal floating point numbers | |
353 | ; 1-7 were introduced with the floating point extension facility | |
354 | ; available with z196 | |
355 | ; With these rounding modes (1-7) a quantum exception might occur | |
356 | ; which is suppressed for the other modes. | |
357 | (define_constants | |
358 | [(DFP_RND_CURRENT 0) | |
359 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0_QUANTEXC 1) | |
360 | (DFP_RND_CURRENT_QUANTEXC 2) | |
361 | (DFP_RND_PREP_FOR_SHORT_PREC_QUANTEXC 3) | |
362 | (DFP_RND_NEAREST_TIE_TO_EVEN_QUANTEXC 4) | |
363 | (DFP_RND_TOWARD_0_QUANTEXC 5) | |
364 | (DFP_RND_TOWARD_INF_QUANTEXC 6) | |
365 | (DFP_RND_TOWARD_MINF_QUANTEXC 7) | |
366 | (DFP_RND_NEAREST_TIE_TO_EVEN 8) | |
367 | (DFP_RND_TOWARD_0 9) | |
368 | (DFP_RND_TOWARD_INF 10) | |
369 | (DFP_RND_TOWARD_MINF 11) | |
370 | (DFP_RND_NEAREST_TIE_AWAY_FROM_0 12) | |
371 | (DFP_RND_NEAREST_TIE_TO_0 13) | |
372 | (DFP_RND_AWAY_FROM_0 14) | |
373 | (DFP_RND_PREP_FOR_SHORT_PREC 15)]) | |
374 | ||
35dd9a0e AK |
375 | ;; |
376 | ;; PFPO GPR0 argument format | |
377 | ;; | |
378 | ||
379 | (define_constants | |
380 | [ | |
381 | ; PFPO operation type | |
382 | (PFPO_CONVERT 0x1000000) | |
383 | ; PFPO operand types | |
384 | (PFPO_OP_TYPE_SF 0x5) | |
385 | (PFPO_OP_TYPE_DF 0x6) | |
386 | (PFPO_OP_TYPE_TF 0x7) | |
387 | (PFPO_OP_TYPE_SD 0x8) | |
388 | (PFPO_OP_TYPE_DD 0x9) | |
389 | (PFPO_OP_TYPE_TD 0xa) | |
390 | ; Bitposition of operand types | |
391 | (PFPO_OP0_TYPE_SHIFT 16) | |
392 | (PFPO_OP1_TYPE_SHIFT 8) | |
393 | ]) | |
394 | ||
5a3fe9b6 AK |
395 | ; Immediate operands for tbegin and tbeginc |
396 | (define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c | |
397 | (define_constants [(TBEGINC_MASK 65288)]) ; 0xff08 | |
fd3cd001 | 398 | |
29a74354 UW |
399 | ;; Instruction operand type as used in the Principles of Operation. |
400 | ;; Used to determine defaults for length and other attribute values. | |
1fec52be | 401 | |
29a74354 | 402 | (define_attr "op_type" |
62d3f261 | 403 | "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX" |
b628bd8e | 404 | (const_string "NN")) |
9db1d521 | 405 | |
29a74354 | 406 | ;; Instruction type attribute used for scheduling. |
9db1d521 | 407 | |
077dab3b | 408 | (define_attr "type" "none,integer,load,lr,la,larl,lm,stm, |
e0374221 | 409 | cs,vs,store,sem,idiv, |
ed0e512a | 410 | imulhi,imulsi,imuldi, |
2cdece44 | 411 | branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, |
f61a2c7d AK |
412 | floadtf,floaddf,floadsf,fstoredf,fstoresf, |
413 | fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, | |
9381e3f1 | 414 | ftoi,fsqrttf,fsqrtdf,fsqrtsf, |
65b1d8ea | 415 | fmadddf,fmaddsf, |
9381e3f1 WG |
416 | ftrunctf,ftruncdf, ftruncsd, ftruncdd, |
417 | itoftf, itofdf, itofsf, itofdd, itoftd, | |
418 | fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, | |
419 | fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, | |
420 | ftoidfp, other" | |
29a74354 UW |
421 | (cond [(eq_attr "op_type" "NN") (const_string "other") |
422 | (eq_attr "op_type" "SS") (const_string "cs")] | |
423 | (const_string "integer"))) | |
9db1d521 | 424 | |
29a74354 UW |
425 | ;; Another attribute used for scheduling purposes: |
426 | ;; agen: Instruction uses the address generation unit | |
427 | ;; reg: Instruction does not use the agen unit | |
077dab3b HP |
428 | |
429 | (define_attr "atype" "agen,reg" | |
62d3f261 | 430 | (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF") |
0101708c AS |
431 | (const_string "reg") |
432 | (const_string "agen"))) | |
9db1d521 | 433 | |
9381e3f1 WG |
434 | ;; Properties concerning Z10 execution grouping and value forwarding. |
435 | ;; z10_super: instruction is superscalar. | |
436 | ;; z10_super_c: instruction is superscalar and meets the condition of z10_c. | |
437 | ;; z10_fwd: The instruction reads the value of an operand and stores it into a | |
438 | ;; target register. It can forward this value to a second instruction that reads | |
439 | ;; the same register if that second instruction is issued in the same group. | |
440 | ;; z10_rec: The instruction is in the T pipeline and reads a register. If the | |
441 | ;; instruction in the S pipe writes to the register, then the T instruction | |
442 | ;; can immediately read the new value. | |
443 | ;; z10_fr: union of Z10_fwd and z10_rec. | |
444 | ;; z10_c: second operand of instruction is a register and read with complemented bits. | |
9381e3f1 WG |
445 | ;; |
446 | ;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. | |
447 | ||
448 | ||
449 | (define_attr "z10prop" "none, | |
450 | z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, | |
451 | z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, | |
452 | z10_rec, | |
453 | z10_fr, z10_fr_A3, z10_fr_E1, | |
e3cba5e5 | 454 | z10_c" |
9381e3f1 WG |
455 | (const_string "none")) |
456 | ||
65b1d8ea AK |
457 | ;; Properties concerning Z196 decoding |
458 | ;; z196_alone: must group alone | |
459 | ;; z196_end: ends a group | |
460 | ;; z196_cracked: instruction is cracked or expanded | |
461 | (define_attr "z196prop" "none, | |
462 | z196_alone, z196_ends, | |
463 | z196_cracked" | |
464 | (const_string "none")) | |
9381e3f1 | 465 | |
a9cc3f58 | 466 | (define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown")) |
22ac2c2f | 467 | |
9db1d521 HP |
468 | ;; Length in bytes. |
469 | ||
470 | (define_attr "length" "" | |
62d3f261 AK |
471 | (cond [(eq_attr "op_type" "E,RR") (const_int 2) |
472 | (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF") (const_int 4)] | |
b628bd8e | 473 | (const_int 6))) |
9db1d521 | 474 | |
29a74354 UW |
475 | |
476 | ;; Processor type. This attribute must exactly match the processor_type | |
477 | ;; enumeration in s390.h. The current machine description does not | |
478 | ;; distinguish between g5 and g6, but there are differences between the two | |
479 | ;; CPUs could in theory be modeled. | |
480 | ||
6654e96f | 481 | (define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13,arch12" |
90c6fd8a | 482 | (const (symbol_ref "s390_tune_attr"))) |
29a74354 | 483 | |
b5e0425c | 484 | (define_attr "cpu_facility" |
6654e96f | 485 | "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vx,z13,arch12,vxe" |
3af8e996 AK |
486 | (const_string "standard")) |
487 | ||
488 | (define_attr "enabled" "" | |
489 | (cond [(eq_attr "cpu_facility" "standard") | |
490 | (const_int 1) | |
491 | ||
492 | (and (eq_attr "cpu_facility" "ieee") | |
d7f99b2c | 493 | (match_test "TARGET_CPU_IEEE_FLOAT")) |
3af8e996 AK |
494 | (const_int 1) |
495 | ||
496 | (and (eq_attr "cpu_facility" "zarch") | |
d7f99b2c | 497 | (match_test "TARGET_ZARCH")) |
3af8e996 AK |
498 | (const_int 1) |
499 | ||
500 | (and (eq_attr "cpu_facility" "longdisp") | |
d7f99b2c | 501 | (match_test "TARGET_LONG_DISPLACEMENT")) |
3af8e996 AK |
502 | (const_int 1) |
503 | ||
504 | (and (eq_attr "cpu_facility" "extimm") | |
d7f99b2c | 505 | (match_test "TARGET_EXTIMM")) |
3af8e996 AK |
506 | (const_int 1) |
507 | ||
508 | (and (eq_attr "cpu_facility" "dfp") | |
d7f99b2c | 509 | (match_test "TARGET_DFP")) |
93538e8e AK |
510 | (const_int 1) |
511 | ||
b5e0425c AK |
512 | (and (eq_attr "cpu_facility" "cpu_zarch") |
513 | (match_test "TARGET_CPU_ZARCH")) | |
514 | (const_int 1) | |
515 | ||
93538e8e | 516 | (and (eq_attr "cpu_facility" "z10") |
d7f99b2c | 517 | (match_test "TARGET_Z10")) |
65b1d8ea AK |
518 | (const_int 1) |
519 | ||
520 | (and (eq_attr "cpu_facility" "z196") | |
d7f99b2c | 521 | (match_test "TARGET_Z196")) |
22ac2c2f AK |
522 | (const_int 1) |
523 | ||
524 | (and (eq_attr "cpu_facility" "zEC12") | |
525 | (match_test "TARGET_ZEC12")) | |
55ac540c AK |
526 | (const_int 1) |
527 | ||
285363a1 | 528 | (and (eq_attr "cpu_facility" "vx") |
55ac540c | 529 | (match_test "TARGET_VX")) |
bf749919 DV |
530 | (const_int 1) |
531 | ||
532 | (and (eq_attr "cpu_facility" "z13") | |
533 | (match_test "TARGET_Z13")) | |
534 | (const_int 1) | |
6654e96f AK |
535 | |
536 | (and (eq_attr "cpu_facility" "arch12") | |
537 | (match_test "TARGET_ARCH12")) | |
538 | (const_int 1) | |
539 | ||
540 | (and (eq_attr "cpu_facility" "vxe") | |
541 | (match_test "TARGET_VXE")) | |
542 | (const_int 1) | |
bf749919 | 543 | ] |
3af8e996 AK |
544 | (const_int 0))) |
545 | ||
29a74354 UW |
546 | ;; Pipeline description for z900. For lack of anything better, |
547 | ;; this description is also used for the g5 and g6. | |
548 | (include "2064.md") | |
549 | ||
3443392a | 550 | ;; Pipeline description for z990, z9-109 and z9-ec. |
29a74354 UW |
551 | (include "2084.md") |
552 | ||
9381e3f1 WG |
553 | ;; Pipeline description for z10 |
554 | (include "2097.md") | |
555 | ||
65b1d8ea AK |
556 | ;; Pipeline description for z196 |
557 | (include "2817.md") | |
558 | ||
22ac2c2f AK |
559 | ;; Pipeline description for zEC12 |
560 | (include "2827.md") | |
561 | ||
23902021 AK |
562 | ;; Pipeline description for z13 |
563 | (include "2964.md") | |
564 | ||
0bfc3f69 AS |
565 | ;; Predicates |
566 | (include "predicates.md") | |
567 | ||
cd8dc1f9 WG |
568 | ;; Constraint definitions |
569 | (include "constraints.md") | |
570 | ||
a8ba31f2 EC |
571 | ;; Other includes |
572 | (include "tpf.md") | |
f52c81dd | 573 | |
3abcb3a7 | 574 | ;; Iterators |
f52c81dd | 575 | |
085261c8 AK |
576 | (define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF]) |
577 | ||
3abcb3a7 | 578 | ;; These mode iterators allow floating point patterns to be generated from the |
f5905b37 | 579 | ;; same template. |
f4aa3848 | 580 | (define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") |
0387c142 | 581 | (SD "TARGET_HARD_DFP")]) |
3abcb3a7 HPN |
582 | (define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) |
583 | (define_mode_iterator BFP [TF DF SF]) | |
584 | (define_mode_iterator DFP [TD DD]) | |
585 | (define_mode_iterator DFP_ALL [TD DD SD]) | |
586 | (define_mode_iterator DSF [DF SF]) | |
587 | (define_mode_iterator SD_SF [SF SD]) | |
588 | (define_mode_iterator DD_DF [DF DD]) | |
589 | (define_mode_iterator TD_TF [TF TD]) | |
590 | ||
3abcb3a7 | 591 | ;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated |
9db2f16d | 592 | ;; from the same template. |
9602b6a1 | 593 | (define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) |
78ce265b | 594 | (define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) |
3abcb3a7 | 595 | (define_mode_iterator DSI [DI SI]) |
78ce265b | 596 | (define_mode_iterator TDI [TI DI]) |
9db2f16d | 597 | |
3abcb3a7 | 598 | ;; These mode iterators allow :P to be used for patterns that operate on |
9db2f16d | 599 | ;; pointer-sized quantities. Exactly one of the two alternatives will match. |
3abcb3a7 | 600 | (define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) |
9db2f16d | 601 | |
78ce265b RH |
602 | ;; These macros refer to the actual word_mode of the configuration. |
603 | ;; This is equal to Pmode except on 31-bit machines in zarch mode. | |
9602b6a1 AK |
604 | (define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) |
605 | (define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) | |
606 | ||
6e0d70c9 AK |
607 | ;; Used by the umul pattern to express modes having half the size. |
608 | (define_mode_attr DWH [(TI "DI") (DI "SI")]) | |
609 | (define_mode_attr dwh [(TI "di") (DI "si")]) | |
610 | ||
3abcb3a7 | 611 | ;; This mode iterator allows the QI and HI patterns to be defined from |
f52c81dd | 612 | ;; the same template. |
3abcb3a7 | 613 | (define_mode_iterator HQI [HI QI]) |
f52c81dd | 614 | |
3abcb3a7 | 615 | ;; This mode iterator allows the integer patterns to be defined from the |
342cf42b | 616 | ;; same template. |
9602b6a1 | 617 | (define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) |
78ce265b | 618 | (define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) |
64c744b9 | 619 | (define_mode_iterator SINT [SI HI QI]) |
342cf42b | 620 | |
3abcb3a7 | 621 | ;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from |
f337b930 | 622 | ;; the same template. |
3abcb3a7 | 623 | (define_code_iterator SHIFT [ashift lshiftrt]) |
f337b930 | 624 | |
d12a76f3 | 625 | ;; This iterator allows r[ox]sbg to be defined with the same template |
571e408a RH |
626 | (define_code_iterator IXOR [ior xor]) |
627 | ||
d12a76f3 AK |
628 | ;; This iterator is used to expand the patterns for the nearest |
629 | ;; integer functions. | |
630 | (define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC | |
631 | UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL | |
632 | UNSPEC_FPINT_NEARBYINT]) | |
633 | (define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor") | |
634 | (UNSPEC_FPINT_BTRUNC "btrunc") | |
635 | (UNSPEC_FPINT_ROUND "round") | |
636 | (UNSPEC_FPINT_CEIL "ceil") | |
637 | (UNSPEC_FPINT_NEARBYINT "nearbyint")]) | |
638 | (define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7") | |
639 | (UNSPEC_FPINT_BTRUNC "5") | |
640 | (UNSPEC_FPINT_ROUND "1") | |
641 | (UNSPEC_FPINT_CEIL "6") | |
642 | (UNSPEC_FPINT_NEARBYINT "0")]) | |
643 | ||
3abcb3a7 HPN |
644 | ;; This iterator and attribute allow to combine most atomic operations. |
645 | (define_code_iterator ATOMIC [and ior xor plus minus mult]) | |
65b1d8ea | 646 | (define_code_iterator ATOMIC_Z196 [and ior xor plus]) |
cf5b43b0 | 647 | (define_code_attr atomic [(and "and") (ior "or") (xor "xor") |
45d18331 | 648 | (plus "add") (minus "sub") (mult "nand")]) |
65b1d8ea | 649 | (define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) |
45d18331 | 650 | |
f4aa3848 | 651 | ;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in |
609e7e80 AK |
652 | ;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. |
653 | (define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) | |
f337b930 | 654 | |
f4aa3848 AK |
655 | ;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in |
656 | ;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in | |
609e7e80 AK |
657 | ;; SDmode. |
658 | (define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) | |
f5905b37 | 659 | |
609e7e80 | 660 | ;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. |
f61a2c7d AK |
661 | ;; Likewise for "<RXe>". |
662 | (define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) | |
663 | (define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) | |
664 | ||
609e7e80 | 665 | ;; The decimal floating point variants of add, sub, div and mul support 3 |
3abcb3a7 | 666 | ;; fp register operands. The following attributes allow to merge the bfp and |
609e7e80 AK |
667 | ;; dfp variants in a single insn definition. |
668 | ||
62d3f261 AK |
669 | ;; These mode attributes are supposed to be used in the `enabled' insn |
670 | ;; attribute to disable certain alternatives for certain modes. | |
671 | (define_mode_attr nBFP [(TF "0") (DF "0") (SF "0") (TD "*") (DD "*") (DD "*")]) | |
672 | (define_mode_attr nDFP [(TF "*") (DF "*") (SF "*") (TD "0") (DD "0") (DD "0")]) | |
673 | (define_mode_attr DSF [(TF "0") (DF "*") (SF "*") (TD "0") (DD "0") (SD "0")]) | |
674 | (define_mode_attr DFDI [(TF "0") (DF "*") (SF "0") | |
675 | (TD "0") (DD "0") (DD "0") | |
676 | (TI "0") (DI "*") (SI "0")]) | |
f5905b37 | 677 | |
85dae55a AK |
678 | ;; This attribute is used in the operand constraint list |
679 | ;; for instructions dealing with the sign bit of 32 or 64bit fp values. | |
680 | ;; TFmode values are represented by a fp register pair. Since the | |
681 | ;; sign bit instructions only handle single source and target fp registers | |
682 | ;; these instructions can only be used for TFmode values if the source and | |
683 | ;; target operand uses the same fp register. | |
684 | (define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) | |
685 | ||
3abcb3a7 | 686 | ;; This attribute adds b for bfp instructions and t for dfp instructions and is used |
609e7e80 AK |
687 | ;; within instruction mnemonics. |
688 | (define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) | |
689 | ||
0387c142 WG |
690 | ;; This attribute is used within instruction mnemonics. It evaluates to d for dfp |
691 | ;; modes and to an empty string for bfp modes. | |
692 | (define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) | |
693 | ||
1b48c8cc AS |
694 | ;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode |
695 | ;; and "0" in SImode. This allows to combine instructions of which the 31bit | |
696 | ;; version only operates on one register. | |
697 | (define_mode_attr d0 [(DI "d") (SI "0")]) | |
698 | ||
699 | ;; In combination with d0 this allows to combine instructions of which the 31bit | |
700 | ;; version only operates on one register. The DImode version needs an additional | |
701 | ;; register for the assembler output. | |
702 | (define_mode_attr 1 [(DI "%1,") (SI "")]) | |
9381e3f1 WG |
703 | |
704 | ;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in | |
f337b930 AS |
705 | ;; 'ashift' and "srdl" in 'lshiftrt'. |
706 | (define_code_attr lr [(ashift "l") (lshiftrt "r")]) | |
707 | ||
708 | ;; In SHIFT templates, this attribute holds the correct standard name for the | |
9381e3f1 | 709 | ;; pattern itself and the corresponding function calls. |
f337b930 | 710 | (define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) |
9a91a21f AS |
711 | |
712 | ;; This attribute handles differences in the instruction 'type' and will result | |
713 | ;; in "RRE" for DImode and "RR" for SImode. | |
714 | (define_mode_attr E [(DI "E") (SI "")]) | |
715 | ||
3298c037 AK |
716 | ;; This attribute handles differences in the instruction 'type' and makes RX<Y> |
717 | ;; to result in "RXY" for DImode and "RX" for SImode. | |
718 | (define_mode_attr Y [(DI "Y") (SI "")]) | |
719 | ||
8006eaa6 AS |
720 | ;; This attribute handles differences in the instruction 'type' and will result |
721 | ;; in "RSE" for TImode and "RS" for DImode. | |
722 | (define_mode_attr TE [(TI "E") (DI "")]) | |
723 | ||
9a91a21f AS |
724 | ;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode |
725 | ;; and "lcr" in SImode. | |
726 | (define_mode_attr g [(DI "g") (SI "")]) | |
f52c81dd | 727 | |
3298c037 AK |
728 | ;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode |
729 | ;; and "sly" in SImode. This is useful because on 64bit the ..g instructions | |
730 | ;; were enhanced with long displacements whereas 31bit instructions got a ..y | |
731 | ;; variant for long displacements. | |
732 | (define_mode_attr y [(DI "g") (SI "y")]) | |
733 | ||
9602b6a1 | 734 | ;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode |
8006eaa6 AS |
735 | ;; and "cds" in DImode. |
736 | (define_mode_attr tg [(TI "g") (DI "")]) | |
737 | ||
78ce265b RH |
738 | ;; In TDI templates, a string like "c<d>sg". |
739 | (define_mode_attr td [(TI "d") (DI "")]) | |
740 | ||
2f8f8434 AS |
741 | ;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode |
742 | ;; and "cfdbr" in SImode. | |
743 | (define_mode_attr gf [(DI "g") (SI "f")]) | |
744 | ||
65b1d8ea AK |
745 | ;; In GPR templates, a string like sll<gk> will expand to sllg for DI |
746 | ;; and sllk for SI. This way it is possible to merge the new z196 SI | |
747 | ;; 3 operands shift instructions into the existing patterns. | |
748 | (define_mode_attr gk [(DI "g") (SI "k")]) | |
749 | ||
f52c81dd AS |
750 | ;; ICM mask required to load MODE value into the lowest subreg |
751 | ;; of a SImode register. | |
752 | (define_mode_attr icm_lo [(HI "3") (QI "1")]) | |
753 | ||
f6ee577c AS |
754 | ;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in |
755 | ;; HImode and "llgc" in QImode. | |
756 | (define_mode_attr hc [(HI "h") (QI "c")]) | |
757 | ||
a1aed706 AS |
758 | ;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" |
759 | ;; in SImode. | |
760 | (define_mode_attr DBL [(DI "TI") (SI "DI")]) | |
761 | ||
609e7e80 AK |
762 | ;; This attribute expands to DF for TFmode and to DD for TDmode . It is |
763 | ;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. | |
764 | (define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) | |
765 | ||
f52c81dd AS |
766 | ;; Maximum unsigned integer that fits in MODE. |
767 | (define_mode_attr max_uint [(HI "65535") (QI "255")]) | |
768 | ||
75ca1b39 RH |
769 | ;; Start and end field computations for RISBG et al. |
770 | (define_mode_attr bfstart [(DI "s") (SI "t")]) | |
771 | (define_mode_attr bfend [(DI "e") (SI "f")]) | |
772 | ||
2542ef05 RH |
773 | ;; In place of GET_MODE_BITSIZE (<MODE>mode) |
774 | (define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) | |
576987fc DV |
775 | ;; 64 - bitsize |
776 | (define_mode_attr bitoff [(DI "0") (SI "32") (HI "48") (QI "56")]) | |
777 | (define_mode_attr bitoff_plus [(DI "") (SI "32+") (HI "48+") (QI "56+")]) | |
2542ef05 | 778 | |
da0dcab1 DV |
779 | ;; In place of GET_MODE_SIZE (<MODE>mode) |
780 | (define_mode_attr modesize [(DI "8") (SI "4")]) | |
781 | ||
177bc204 RS |
782 | ;; Allow return and simple_return to be defined from a single template. |
783 | (define_code_iterator ANY_RETURN [return simple_return]) | |
784 | ||
6e5b5de8 AK |
785 | |
786 | ||
787 | ; Condition code modes generated by vector fp comparisons. These will | |
788 | ; be used also in single element mode. | |
789 | (define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE]) | |
790 | ; Used with VFCMP to expand part of the mnemonic | |
791 | ; For fp we have a mismatch: eq in the insn name - e in asm | |
792 | (define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) | |
a6a2b532 | 793 | (define_mode_attr insn_cmp [(CCVEQ "eq") (CCVIH "h") (CCVIHU "hl") (CCVFH "h") (CCVFHE "he")]) |
6e5b5de8 | 794 | |
191eb16d AK |
795 | ;; Subst pattern definitions |
796 | (include "subst.md") | |
6e5b5de8 | 797 | |
085261c8 AK |
798 | (include "vector.md") |
799 | ||
9db1d521 HP |
800 | ;; |
801 | ;;- Compare instructions. | |
802 | ;; | |
803 | ||
07893d4f | 804 | ; Test-under-Mask instructions |
9db1d521 | 805 | |
07893d4f | 806 | (define_insn "*tmqi_mem" |
ae156f85 | 807 | [(set (reg CC_REGNUM) |
68f9c5e2 UW |
808 | (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") |
809 | (match_operand:QI 1 "immediate_operand" "n,n")) | |
810 | (match_operand:QI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 811 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" |
d3632d41 | 812 | "@ |
fc0ea003 UW |
813 | tm\t%S0,%b1 |
814 | tmy\t%S0,%b1" | |
9381e3f1 | 815 | [(set_attr "op_type" "SI,SIY") |
3e4be43f | 816 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 817 | (set_attr "z10prop" "z10_super,z10_super")]) |
9db1d521 | 818 | |
05b9aaaa | 819 | (define_insn "*tmdi_reg" |
ae156f85 | 820 | [(set (reg CC_REGNUM) |
f19a9af7 | 821 | (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") |
2f7e5a0d | 822 | (match_operand:DI 1 "immediate_operand" |
f19a9af7 AK |
823 | "N0HD0,N1HD0,N2HD0,N3HD0")) |
824 | (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] | |
9602b6a1 | 825 | "TARGET_ZARCH |
3ed99cc9 | 826 | && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
827 | && s390_single_part (operands[1], DImode, HImode, 0) >= 0" |
828 | "@ | |
829 | tmhh\t%0,%i1 | |
830 | tmhl\t%0,%i1 | |
831 | tmlh\t%0,%i1 | |
832 | tmll\t%0,%i1" | |
9381e3f1 WG |
833 | [(set_attr "op_type" "RI") |
834 | (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) | |
05b9aaaa UW |
835 | |
836 | (define_insn "*tmsi_reg" | |
ae156f85 | 837 | [(set (reg CC_REGNUM) |
f19a9af7 AK |
838 | (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") |
839 | (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) | |
840 | (match_operand:SI 2 "immediate_operand" "n,n")))] | |
3ed99cc9 | 841 | "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) |
f19a9af7 AK |
842 | && s390_single_part (operands[1], SImode, HImode, 0) >= 0" |
843 | "@ | |
844 | tmh\t%0,%i1 | |
845 | tml\t%0,%i1" | |
729e750f WG |
846 | [(set_attr "op_type" "RI") |
847 | (set_attr "z10prop" "z10_super,z10_super")]) | |
05b9aaaa | 848 | |
f52c81dd | 849 | (define_insn "*tm<mode>_full" |
ae156f85 | 850 | [(set (reg CC_REGNUM) |
f52c81dd AS |
851 | (compare (match_operand:HQI 0 "register_operand" "d") |
852 | (match_operand:HQI 1 "immediate_operand" "n")))] | |
3ed99cc9 | 853 | "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" |
f52c81dd | 854 | "tml\t%0,<max_uint>" |
729e750f WG |
855 | [(set_attr "op_type" "RI") |
856 | (set_attr "z10prop" "z10_super")]) | |
9db1d521 | 857 | |
07893d4f | 858 | |
08a5aaa2 | 859 | ; |
07893d4f | 860 | ; Load-and-Test instructions |
08a5aaa2 AS |
861 | ; |
862 | ||
c0220ea4 | 863 | ; tst(di|si) instruction pattern(s). |
07893d4f UW |
864 | |
865 | (define_insn "*tstdi_sign" | |
ae156f85 | 866 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
867 | (compare |
868 | (ashiftrt:DI | |
869 | (ashift:DI | |
3e4be43f | 870 | (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,T") 0) |
963fc8d0 AK |
871 | (const_int 32)) (const_int 32)) |
872 | (match_operand:DI 1 "const0_operand" ""))) | |
873 | (set (match_operand:DI 2 "register_operand" "=d,d") | |
07893d4f | 874 | (sign_extend:DI (match_dup 0)))] |
9602b6a1 | 875 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" |
963fc8d0 AK |
876 | "ltgfr\t%2,%0 |
877 | ltgf\t%2,%0" | |
878 | [(set_attr "op_type" "RRE,RXY") | |
9381e3f1 WG |
879 | (set_attr "cpu_facility" "*,z10") |
880 | (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) | |
07893d4f | 881 | |
43a09b63 | 882 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 883 | (define_insn "*tst<mode>_extimm" |
ec24698e | 884 | [(set (reg CC_REGNUM) |
3e4be43f | 885 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") |
08a5aaa2 AS |
886 | (match_operand:GPR 1 "const0_operand" ""))) |
887 | (set (match_operand:GPR 2 "register_operand" "=d,d") | |
ec24698e | 888 | (match_dup 0))] |
08a5aaa2 | 889 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" |
ec24698e | 890 | "@ |
08a5aaa2 AS |
891 | lt<g>r\t%2,%0 |
892 | lt<g>\t%2,%0" | |
9381e3f1 | 893 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 894 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) |
ec24698e | 895 | |
43a09b63 | 896 | ; ltr, lt, ltgr, ltg |
08a5aaa2 | 897 | (define_insn "*tst<mode>_cconly_extimm" |
ec24698e | 898 | [(set (reg CC_REGNUM) |
3e4be43f | 899 | (compare (match_operand:GPR 0 "nonimmediate_operand" "d,T") |
08a5aaa2 AS |
900 | (match_operand:GPR 1 "const0_operand" ""))) |
901 | (clobber (match_scratch:GPR 2 "=X,d"))] | |
902 | "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" | |
ec24698e | 903 | "@ |
08a5aaa2 AS |
904 | lt<g>r\t%0,%0 |
905 | lt<g>\t%2,%0" | |
9381e3f1 | 906 | [(set_attr "op_type" "RR<E>,RXY") |
729e750f | 907 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) |
ec24698e | 908 | |
07893d4f | 909 | (define_insn "*tstdi" |
ae156f85 | 910 | [(set (reg CC_REGNUM) |
07893d4f UW |
911 | (compare (match_operand:DI 0 "register_operand" "d") |
912 | (match_operand:DI 1 "const0_operand" ""))) | |
913 | (set (match_operand:DI 2 "register_operand" "=d") | |
914 | (match_dup 0))] | |
9602b6a1 | 915 | "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 916 | "ltgr\t%2,%0" |
9381e3f1 WG |
917 | [(set_attr "op_type" "RRE") |
918 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 919 | |
07893d4f | 920 | (define_insn "*tstsi" |
ae156f85 | 921 | [(set (reg CC_REGNUM) |
d3632d41 | 922 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 923 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 924 | (set (match_operand:SI 2 "register_operand" "=d,d,d") |
07893d4f | 925 | (match_dup 0))] |
ec24698e | 926 | "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" |
07893d4f | 927 | "@ |
d40c829f | 928 | ltr\t%2,%0 |
fc0ea003 UW |
929 | icm\t%2,15,%S0 |
930 | icmy\t%2,15,%S0" | |
9381e3f1 | 931 | [(set_attr "op_type" "RR,RS,RSY") |
3e4be43f | 932 | (set_attr "cpu_facility" "*,*,longdisp") |
9381e3f1 | 933 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 934 | |
07893d4f | 935 | (define_insn "*tstsi_cconly" |
ae156f85 | 936 | [(set (reg CC_REGNUM) |
d3632d41 | 937 | (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") |
07893d4f | 938 | (match_operand:SI 1 "const0_operand" ""))) |
d3632d41 | 939 | (clobber (match_scratch:SI 2 "=X,d,d"))] |
07893d4f UW |
940 | "s390_match_ccmode(insn, CCSmode)" |
941 | "@ | |
d40c829f | 942 | ltr\t%0,%0 |
fc0ea003 UW |
943 | icm\t%2,15,%S0 |
944 | icmy\t%2,15,%S0" | |
9381e3f1 | 945 | [(set_attr "op_type" "RR,RS,RSY") |
3e4be43f | 946 | (set_attr "cpu_facility" "*,*,longdisp") |
9381e3f1 | 947 | (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) |
4023fb28 | 948 | |
08a5aaa2 AS |
949 | (define_insn "*tstdi_cconly_31" |
950 | [(set (reg CC_REGNUM) | |
951 | (compare (match_operand:DI 0 "register_operand" "d") | |
952 | (match_operand:DI 1 "const0_operand" "")))] | |
9602b6a1 | 953 | "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" |
08a5aaa2 AS |
954 | "srda\t%0,0" |
955 | [(set_attr "op_type" "RS") | |
956 | (set_attr "atype" "reg")]) | |
957 | ||
43a09b63 | 958 | ; ltr, ltgr |
08a5aaa2 | 959 | (define_insn "*tst<mode>_cconly2" |
ae156f85 | 960 | [(set (reg CC_REGNUM) |
08a5aaa2 AS |
961 | (compare (match_operand:GPR 0 "register_operand" "d") |
962 | (match_operand:GPR 1 "const0_operand" "")))] | |
07893d4f | 963 | "s390_match_ccmode(insn, CCSmode)" |
08a5aaa2 | 964 | "lt<g>r\t%0,%0" |
9381e3f1 WG |
965 | [(set_attr "op_type" "RR<E>") |
966 | (set_attr "z10prop" "z10_fr_E1")]) | |
08a5aaa2 | 967 | |
c0220ea4 | 968 | ; tst(hi|qi) instruction pattern(s). |
4023fb28 | 969 | |
f52c81dd | 970 | (define_insn "*tst<mode>CCT" |
ae156f85 | 971 | [(set (reg CC_REGNUM) |
f52c81dd AS |
972 | (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") |
973 | (match_operand:HQI 1 "const0_operand" ""))) | |
974 | (set (match_operand:HQI 2 "register_operand" "=d,d,0") | |
3af97654 UW |
975 | (match_dup 0))] |
976 | "s390_match_ccmode(insn, CCTmode)" | |
977 | "@ | |
f52c81dd AS |
978 | icm\t%2,<icm_lo>,%S0 |
979 | icmy\t%2,<icm_lo>,%S0 | |
980 | tml\t%0,<max_uint>" | |
9381e3f1 | 981 | [(set_attr "op_type" "RS,RSY,RI") |
3e4be43f | 982 | (set_attr "cpu_facility" "*,longdisp,*") |
9381e3f1 | 983 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) |
3af97654 UW |
984 | |
985 | (define_insn "*tsthiCCT_cconly" | |
ae156f85 | 986 | [(set (reg CC_REGNUM) |
d3632d41 | 987 | (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") |
3af97654 | 988 | (match_operand:HI 1 "const0_operand" ""))) |
d3632d41 | 989 | (clobber (match_scratch:HI 2 "=d,d,X"))] |
3af97654 UW |
990 | "s390_match_ccmode(insn, CCTmode)" |
991 | "@ | |
fc0ea003 UW |
992 | icm\t%2,3,%S0 |
993 | icmy\t%2,3,%S0 | |
d40c829f | 994 | tml\t%0,65535" |
9381e3f1 | 995 | [(set_attr "op_type" "RS,RSY,RI") |
3e4be43f | 996 | (set_attr "cpu_facility" "*,longdisp,*") |
9381e3f1 | 997 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) |
3af97654 | 998 | |
3af97654 | 999 | (define_insn "*tstqiCCT_cconly" |
ae156f85 | 1000 | [(set (reg CC_REGNUM) |
d3632d41 | 1001 | (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") |
3af97654 UW |
1002 | (match_operand:QI 1 "const0_operand" "")))] |
1003 | "s390_match_ccmode(insn, CCTmode)" | |
1004 | "@ | |
fc0ea003 UW |
1005 | cli\t%S0,0 |
1006 | cliy\t%S0,0 | |
d40c829f | 1007 | tml\t%0,255" |
9381e3f1 | 1008 | [(set_attr "op_type" "SI,SIY,RI") |
3e4be43f | 1009 | (set_attr "cpu_facility" "*,longdisp,*") |
729e750f | 1010 | (set_attr "z10prop" "z10_super,z10_super,z10_super")]) |
3af97654 | 1011 | |
f52c81dd | 1012 | (define_insn "*tst<mode>" |
ae156f85 | 1013 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1014 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1015 | (match_operand:HQI 1 "const0_operand" ""))) | |
1016 | (set (match_operand:HQI 2 "register_operand" "=d,d") | |
07893d4f UW |
1017 | (match_dup 0))] |
1018 | "s390_match_ccmode(insn, CCSmode)" | |
d3632d41 | 1019 | "@ |
f52c81dd AS |
1020 | icm\t%2,<icm_lo>,%S0 |
1021 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 | 1022 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 1023 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1024 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 | 1025 | |
f52c81dd | 1026 | (define_insn "*tst<mode>_cconly" |
ae156f85 | 1027 | [(set (reg CC_REGNUM) |
f52c81dd AS |
1028 | (compare (match_operand:HQI 0 "s_operand" "Q,S") |
1029 | (match_operand:HQI 1 "const0_operand" ""))) | |
1030 | (clobber (match_scratch:HQI 2 "=d,d"))] | |
07893d4f | 1031 | "s390_match_ccmode(insn, CCSmode)" |
d3632d41 | 1032 | "@ |
f52c81dd AS |
1033 | icm\t%2,<icm_lo>,%S0 |
1034 | icmy\t%2,<icm_lo>,%S0" | |
9381e3f1 | 1035 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 1036 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1037 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
d3632d41 | 1038 | |
9db1d521 | 1039 | |
575f7c2b UW |
1040 | ; Compare (equality) instructions |
1041 | ||
1042 | (define_insn "*cmpdi_cct" | |
ae156f85 | 1043 | [(set (reg CC_REGNUM) |
ec24698e | 1044 | (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") |
3e4be43f | 1045 | (match_operand:DI 1 "general_operand" "d,K,Os,T,BQ")))] |
9602b6a1 | 1046 | "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" |
575f7c2b UW |
1047 | "@ |
1048 | cgr\t%0,%1 | |
f4f41b4e | 1049 | cghi\t%0,%h1 |
ec24698e | 1050 | cgfi\t%0,%1 |
575f7c2b | 1051 | cg\t%0,%1 |
19b63d8e | 1052 | #" |
9381e3f1 WG |
1053 | [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") |
1054 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) | |
575f7c2b UW |
1055 | |
1056 | (define_insn "*cmpsi_cct" | |
ae156f85 | 1057 | [(set (reg CC_REGNUM) |
ec24698e UW |
1058 | (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") |
1059 | (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] | |
e221ef54 | 1060 | "s390_match_ccmode (insn, CCTmode)" |
575f7c2b UW |
1061 | "@ |
1062 | cr\t%0,%1 | |
f4f41b4e | 1063 | chi\t%0,%h1 |
ec24698e | 1064 | cfi\t%0,%1 |
575f7c2b UW |
1065 | c\t%0,%1 |
1066 | cy\t%0,%1 | |
19b63d8e | 1067 | #" |
9381e3f1 | 1068 | [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") |
3e4be43f | 1069 | (set_attr "cpu_facility" "*,*,*,*,longdisp,*") |
e3cba5e5 | 1070 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) |
575f7c2b | 1071 | |
07893d4f | 1072 | ; Compare (signed) instructions |
4023fb28 | 1073 | |
07893d4f | 1074 | (define_insn "*cmpdi_ccs_sign" |
ae156f85 | 1075 | [(set (reg CC_REGNUM) |
963fc8d0 | 1076 | (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
3e4be43f | 1077 | "d,T,b")) |
963fc8d0 | 1078 | (match_operand:DI 0 "register_operand" "d, d,d")))] |
9602b6a1 | 1079 | "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" |
4023fb28 | 1080 | "@ |
d40c829f | 1081 | cgfr\t%0,%1 |
963fc8d0 AK |
1082 | cgf\t%0,%1 |
1083 | cgfrl\t%0,%1" | |
1084 | [(set_attr "op_type" "RRE,RXY,RIL") | |
9381e3f1 | 1085 | (set_attr "z10prop" "z10_c,*,*") |
963fc8d0 | 1086 | (set_attr "type" "*,*,larl")]) |
4023fb28 | 1087 | |
9381e3f1 WG |
1088 | |
1089 | ||
07893d4f | 1090 | (define_insn "*cmpsi_ccs_sign" |
ae156f85 | 1091 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1092 | (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) |
1093 | (match_operand:SI 0 "register_operand" "d,d,d")))] | |
07893d4f | 1094 | "s390_match_ccmode(insn, CCSRmode)" |
d3632d41 | 1095 | "@ |
d40c829f | 1096 | ch\t%0,%1 |
963fc8d0 AK |
1097 | chy\t%0,%1 |
1098 | chrl\t%0,%1" | |
1099 | [(set_attr "op_type" "RX,RXY,RIL") | |
3e4be43f | 1100 | (set_attr "cpu_facility" "*,longdisp,z10") |
65b1d8ea AK |
1101 | (set_attr "type" "*,*,larl") |
1102 | (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")]) | |
963fc8d0 AK |
1103 | |
1104 | (define_insn "*cmphi_ccs_z10" | |
1105 | [(set (reg CC_REGNUM) | |
1106 | (compare (match_operand:HI 0 "s_operand" "Q") | |
1107 | (match_operand:HI 1 "immediate_operand" "K")))] | |
1108 | "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" | |
1109 | "chhsi\t%0,%1" | |
65b1d8ea AK |
1110 | [(set_attr "op_type" "SIL") |
1111 | (set_attr "z196prop" "z196_cracked")]) | |
963fc8d0 AK |
1112 | |
1113 | (define_insn "*cmpdi_ccs_signhi_rl" | |
1114 | [(set (reg CC_REGNUM) | |
3e4be43f | 1115 | (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "T,b")) |
963fc8d0 AK |
1116 | (match_operand:GPR 0 "register_operand" "d,d")))] |
1117 | "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" | |
1118 | "@ | |
1119 | cgh\t%0,%1 | |
1120 | cghrl\t%0,%1" | |
1121 | [(set_attr "op_type" "RXY,RIL") | |
1122 | (set_attr "type" "*,larl")]) | |
4023fb28 | 1123 | |
963fc8d0 | 1124 | ; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl |
3298c037 | 1125 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1126 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1127 | (compare (match_operand:GPR 0 "nonimmediate_operand" |
1128 | "d,d,Q, d,d,d,d") | |
1129 | (match_operand:GPR 1 "general_operand" | |
1130 | "d,K,K,Os,R,T,b")))] | |
9db1d521 | 1131 | "s390_match_ccmode(insn, CCSmode)" |
07893d4f | 1132 | "@ |
3298c037 AK |
1133 | c<g>r\t%0,%1 |
1134 | c<g>hi\t%0,%h1 | |
963fc8d0 | 1135 | c<g>hsi\t%0,%h1 |
3298c037 AK |
1136 | c<g>fi\t%0,%1 |
1137 | c<g>\t%0,%1 | |
963fc8d0 AK |
1138 | c<y>\t%0,%1 |
1139 | c<g>rl\t%0,%1" | |
1140 | [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") | |
3e4be43f | 1141 | (set_attr "cpu_facility" "*,*,z10,extimm,*,longdisp,z10") |
9381e3f1 WG |
1142 | (set_attr "type" "*,*,*,*,*,*,larl") |
1143 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) | |
c7453384 | 1144 | |
07893d4f UW |
1145 | |
1146 | ; Compare (unsigned) instructions | |
9db1d521 | 1147 | |
963fc8d0 AK |
1148 | (define_insn "*cmpsi_ccu_zerohi_rlsi" |
1149 | [(set (reg CC_REGNUM) | |
1150 | (compare (zero_extend:SI (mem:HI (match_operand:SI 1 | |
1151 | "larl_operand" "X"))) | |
1152 | (match_operand:SI 0 "register_operand" "d")))] | |
1153 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1154 | "clhrl\t%0,%1" | |
1155 | [(set_attr "op_type" "RIL") | |
729e750f WG |
1156 | (set_attr "type" "larl") |
1157 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 AK |
1158 | |
1159 | ; clhrl, clghrl | |
1160 | (define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" | |
1161 | [(set (reg CC_REGNUM) | |
1162 | (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 | |
1163 | "larl_operand" "X"))) | |
1164 | (match_operand:GPR 0 "register_operand" "d")))] | |
1165 | "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" | |
1166 | "cl<g>hrl\t%0,%1" | |
1167 | [(set_attr "op_type" "RIL") | |
9381e3f1 WG |
1168 | (set_attr "type" "larl") |
1169 | (set_attr "z10prop" "z10_super")]) | |
963fc8d0 | 1170 | |
07893d4f | 1171 | (define_insn "*cmpdi_ccu_zero" |
ae156f85 | 1172 | [(set (reg CC_REGNUM) |
963fc8d0 | 1173 | (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" |
3e4be43f UW |
1174 | "d,T,b")) |
1175 | (match_operand:DI 0 "register_operand" "d,d,d")))] | |
9602b6a1 | 1176 | "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" |
07893d4f | 1177 | "@ |
d40c829f | 1178 | clgfr\t%0,%1 |
963fc8d0 AK |
1179 | clgf\t%0,%1 |
1180 | clgfrl\t%0,%1" | |
1181 | [(set_attr "op_type" "RRE,RXY,RIL") | |
1182 | (set_attr "cpu_facility" "*,*,z10") | |
9381e3f1 WG |
1183 | (set_attr "type" "*,*,larl") |
1184 | (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) | |
9db1d521 | 1185 | |
07893d4f | 1186 | (define_insn "*cmpdi_ccu" |
ae156f85 | 1187 | [(set (reg CC_REGNUM) |
963fc8d0 | 1188 | (compare (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1189 | "d, d,d,Q,d, Q,BQ") |
963fc8d0 | 1190 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1191 | "d,Op,b,D,T,BQ,Q")))] |
9602b6a1 | 1192 | "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" |
07893d4f | 1193 | "@ |
d40c829f | 1194 | clgr\t%0,%1 |
ec24698e | 1195 | clgfi\t%0,%1 |
963fc8d0 AK |
1196 | clgrl\t%0,%1 |
1197 | clghsi\t%0,%x1 | |
575f7c2b | 1198 | clg\t%0,%1 |
e221ef54 | 1199 | # |
19b63d8e | 1200 | #" |
963fc8d0 AK |
1201 | [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") |
1202 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") | |
9381e3f1 WG |
1203 | (set_attr "type" "*,*,larl,*,*,*,*") |
1204 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 1205 | |
07893d4f | 1206 | (define_insn "*cmpsi_ccu" |
ae156f85 | 1207 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1208 | (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") |
1209 | (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] | |
e221ef54 | 1210 | "s390_match_ccmode (insn, CCUmode)" |
07893d4f | 1211 | "@ |
d40c829f | 1212 | clr\t%0,%1 |
ec24698e | 1213 | clfi\t%0,%o1 |
963fc8d0 AK |
1214 | clrl\t%0,%1 |
1215 | clfhsi\t%0,%x1 | |
d40c829f | 1216 | cl\t%0,%1 |
575f7c2b | 1217 | cly\t%0,%1 |
e221ef54 | 1218 | # |
19b63d8e | 1219 | #" |
963fc8d0 | 1220 | [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") |
3e4be43f | 1221 | (set_attr "cpu_facility" "*,extimm,z10,z10,*,longdisp,*,*") |
9381e3f1 WG |
1222 | (set_attr "type" "*,*,larl,*,*,*,*,*") |
1223 | (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) | |
9db1d521 | 1224 | |
07893d4f | 1225 | (define_insn "*cmphi_ccu" |
ae156f85 | 1226 | [(set (reg CC_REGNUM) |
963fc8d0 AK |
1227 | (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") |
1228 | (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] | |
575f7c2b | 1229 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1230 | && !register_operand (operands[1], HImode)" |
d3632d41 | 1231 | "@ |
fc0ea003 UW |
1232 | clm\t%0,3,%S1 |
1233 | clmy\t%0,3,%S1 | |
963fc8d0 | 1234 | clhhsi\t%0,%1 |
e221ef54 | 1235 | # |
19b63d8e | 1236 | #" |
963fc8d0 | 1237 | [(set_attr "op_type" "RS,RSY,SIL,SS,SS") |
3e4be43f | 1238 | (set_attr "cpu_facility" "*,longdisp,z10,*,*") |
9381e3f1 | 1239 | (set_attr "z10prop" "*,*,z10_super,*,*")]) |
9db1d521 HP |
1240 | |
1241 | (define_insn "*cmpqi_ccu" | |
ae156f85 | 1242 | [(set (reg CC_REGNUM) |
e221ef54 UW |
1243 | (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") |
1244 | (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] | |
575f7c2b | 1245 | "s390_match_ccmode (insn, CCUmode) |
575f7c2b | 1246 | && !register_operand (operands[1], QImode)" |
d3632d41 | 1247 | "@ |
fc0ea003 UW |
1248 | clm\t%0,1,%S1 |
1249 | clmy\t%0,1,%S1 | |
1250 | cli\t%S0,%b1 | |
1251 | cliy\t%S0,%b1 | |
e221ef54 | 1252 | # |
19b63d8e | 1253 | #" |
9381e3f1 | 1254 | [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") |
3e4be43f | 1255 | (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*") |
9381e3f1 | 1256 | (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) |
9db1d521 HP |
1257 | |
1258 | ||
19b63d8e UW |
1259 | ; Block compare (CLC) instruction patterns. |
1260 | ||
1261 | (define_insn "*clc" | |
ae156f85 | 1262 | [(set (reg CC_REGNUM) |
d4f52f0e | 1263 | (compare (match_operand:BLK 0 "memory_operand" "Q") |
19b63d8e UW |
1264 | (match_operand:BLK 1 "memory_operand" "Q"))) |
1265 | (use (match_operand 2 "const_int_operand" "n"))] | |
1266 | "s390_match_ccmode (insn, CCUmode) | |
1267 | && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 1268 | "clc\t%O0(%2,%R0),%S1" |
b628bd8e | 1269 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
1270 | |
1271 | (define_split | |
ae156f85 | 1272 | [(set (reg CC_REGNUM) |
19b63d8e UW |
1273 | (compare (match_operand 0 "memory_operand" "") |
1274 | (match_operand 1 "memory_operand" "")))] | |
1275 | "reload_completed | |
1276 | && s390_match_ccmode (insn, CCUmode) | |
1277 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
1278 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
1279 | [(parallel | |
1280 | [(set (match_dup 0) (match_dup 1)) | |
1281 | (use (match_dup 2))])] | |
1282 | { | |
1283 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
1284 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
1285 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
1286 | ||
1287 | operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), | |
1288 | operands[0], operands[1]); | |
1289 | operands[0] = SET_DEST (PATTERN (curr_insn)); | |
1290 | }) | |
1291 | ||
1292 | ||
609e7e80 | 1293 | ; (TF|DF|SF|TD|DD|SD) instructions |
9db1d521 | 1294 | |
e325aba2 AK |
1295 | |
1296 | ; load and test instructions turn SNaN into QNaN what is not | |
1297 | ; acceptable if the target will be used afterwards. On the other hand | |
1298 | ; they are quite convenient for implementing comparisons with 0.0. So | |
1299 | ; try to enable them via splitter if the value isn't needed anymore. | |
1300 | ||
609e7e80 | 1301 | ; ltxbr, ltdbr, ltebr, ltxtr, ltdtr |
f5905b37 | 1302 | (define_insn "*cmp<mode>_ccs_0" |
ae156f85 | 1303 | [(set (reg CC_REGNUM) |
e325aba2 AK |
1304 | (compare (match_operand:FP 0 "register_operand" "f") |
1305 | (match_operand:FP 1 "const0_operand" ""))) | |
1306 | (clobber (match_operand:FP 2 "register_operand" "=0"))] | |
142cd70f | 1307 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
609e7e80 | 1308 | "lt<xde><bt>r\t%0,%0" |
077dab3b | 1309 | [(set_attr "op_type" "RRE") |
9381e3f1 | 1310 | (set_attr "type" "fsimp<mode>")]) |
9db1d521 | 1311 | |
e325aba2 AK |
1312 | (define_split |
1313 | [(set (match_operand 0 "cc_reg_operand") | |
1314 | (compare (match_operand:FP 1 "register_operand") | |
1315 | (match_operand:FP 2 "const0_operand")))] | |
1316 | "TARGET_HARD_FLOAT && REG_P (operands[1]) && dead_or_set_p (insn, operands[1])" | |
1317 | [(parallel | |
1318 | [(set (match_dup 0) (match_dup 3)) | |
1319 | (clobber (match_dup 1))])] | |
1320 | { | |
1321 | /* s390_match_ccmode requires the compare to have the same CC mode | |
1322 | as the CC destination register. */ | |
1323 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[0]), | |
1324 | operands[1], operands[2]); | |
1325 | }) | |
1326 | ||
1327 | ||
77c585ca | 1328 | ; cxtr, cdtr, cxbr, cdbr, cebr, cdb, ceb, wfcdb |
f5905b37 | 1329 | (define_insn "*cmp<mode>_ccs" |
ae156f85 | 1330 | [(set (reg CC_REGNUM) |
77c585ca AK |
1331 | (compare (match_operand:FP 0 "register_operand" "f,f,v") |
1332 | (match_operand:FP 1 "general_operand" "f,R,v")))] | |
142cd70f | 1333 | "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" |
9db1d521 | 1334 | "@ |
609e7e80 | 1335 | c<xde><bt>r\t%0,%1 |
77c585ca AK |
1336 | c<xde>b\t%0,%1 |
1337 | wfcdb\t%0,%1" | |
1338 | [(set_attr "op_type" "RRE,RXE,VRR") | |
1339 | (set_attr "cpu_facility" "*,*,vx") | |
1340 | (set_attr "enabled" "*,<DSF>,<DFDI>")]) | |
1341 | ||
963fc8d0 AK |
1342 | |
1343 | ; Compare and Branch instructions | |
1344 | ||
1345 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
9381e3f1 WG |
1346 | ; The following instructions do a complementary access of their second |
1347 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
963fc8d0 AK |
1348 | (define_insn "*cmp_and_br_signed_<mode>" |
1349 | [(set (pc) | |
1350 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1351 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1352 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1353 | (label_ref (match_operand 3 "" "")) | |
1354 | (pc))) | |
1355 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1356 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1357 | { |
1358 | if (get_attr_length (insn) == 6) | |
1359 | return which_alternative ? | |
1360 | "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; | |
1361 | else | |
1362 | return which_alternative ? | |
1363 | "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; | |
1364 | } | |
1365 | [(set_attr "op_type" "RIE") | |
1366 | (set_attr "type" "branch") | |
e3cba5e5 | 1367 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1368 | (set (attr "length") |
1369 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1370 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1371 | ; 10 byte for cgr/jg | |
1372 | ||
1373 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
9381e3f1 WG |
1374 | ; The following instructions do a complementary access of their second |
1375 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
963fc8d0 AK |
1376 | (define_insn "*cmp_and_br_unsigned_<mode>" |
1377 | [(set (pc) | |
1378 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1379 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1380 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1381 | (label_ref (match_operand 3 "" "")) | |
1382 | (pc))) | |
1383 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1384 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
963fc8d0 AK |
1385 | { |
1386 | if (get_attr_length (insn) == 6) | |
1387 | return which_alternative ? | |
1388 | "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; | |
1389 | else | |
1390 | return which_alternative ? | |
1391 | "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; | |
1392 | } | |
1393 | [(set_attr "op_type" "RIE") | |
1394 | (set_attr "type" "branch") | |
e3cba5e5 | 1395 | (set_attr "z10prop" "z10_super_c,z10_super") |
963fc8d0 AK |
1396 | (set (attr "length") |
1397 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1398 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1399 | ; 10 byte for clgr/jg | |
1400 | ||
b0f86a7e AK |
1401 | ; And now the same two patterns as above but with a negated CC mask. |
1402 | ||
1403 | ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr | |
1404 | ; The following instructions do a complementary access of their second | |
1405 | ; operand (z01 only): crj_c, cgrjc, cr, cgr | |
1406 | (define_insn "*icmp_and_br_signed_<mode>" | |
1407 | [(set (pc) | |
1408 | (if_then_else (match_operator 0 "s390_signed_integer_comparison" | |
1409 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1410 | (match_operand:GPR 2 "nonmemory_operand" "d,C")]) | |
1411 | (pc) | |
1412 | (label_ref (match_operand 3 "" "")))) | |
1413 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1414 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1415 | { |
1416 | if (get_attr_length (insn) == 6) | |
1417 | return which_alternative ? | |
1418 | "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; | |
1419 | else | |
1420 | return which_alternative ? | |
1421 | "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; | |
1422 | } | |
1423 | [(set_attr "op_type" "RIE") | |
1424 | (set_attr "type" "branch") | |
1425 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1426 | (set (attr "length") | |
1427 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1428 | (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg | |
1429 | ; 10 byte for cgr/jg | |
1430 | ||
1431 | ; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr | |
1432 | ; The following instructions do a complementary access of their second | |
1433 | ; operand (z10 only): clrj, clgrj, clr, clgr | |
1434 | (define_insn "*icmp_and_br_unsigned_<mode>" | |
1435 | [(set (pc) | |
1436 | (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" | |
1437 | [(match_operand:GPR 1 "register_operand" "d,d") | |
1438 | (match_operand:GPR 2 "nonmemory_operand" "d,I")]) | |
1439 | (pc) | |
1440 | (label_ref (match_operand 3 "" "")))) | |
1441 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 1442 | "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" |
b0f86a7e AK |
1443 | { |
1444 | if (get_attr_length (insn) == 6) | |
1445 | return which_alternative ? | |
1446 | "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; | |
1447 | else | |
1448 | return which_alternative ? | |
1449 | "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; | |
1450 | } | |
1451 | [(set_attr "op_type" "RIE") | |
1452 | (set_attr "type" "branch") | |
1453 | (set_attr "z10prop" "z10_super_c,z10_super") | |
1454 | (set (attr "length") | |
1455 | (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) | |
1456 | (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg | |
1457 | ; 10 byte for clgr/jg | |
1458 | ||
9db1d521 HP |
1459 | ;; |
1460 | ;;- Move instructions. | |
1461 | ;; | |
1462 | ||
1463 | ; | |
1464 | ; movti instruction pattern(s). | |
1465 | ; | |
1466 | ||
085261c8 AK |
1467 | ; FIXME: More constants are possible by enabling jxx, jyy constraints |
1468 | ; for TImode (use double-int for the calculations) | |
9db1d521 | 1469 | (define_insn "movti" |
3e4be43f UW |
1470 | [(set (match_operand:TI 0 "nonimmediate_operand" "=d,S,v, v, v,v,d,v,R, d,o") |
1471 | (match_operand:TI 1 "general_operand" " S,d,v,j00,jm1,d,v,R,v,dPT,d"))] | |
9602b6a1 | 1472 | "TARGET_ZARCH" |
4023fb28 | 1473 | "@ |
fc0ea003 UW |
1474 | lmg\t%0,%N0,%S1 |
1475 | stmg\t%1,%N1,%S0 | |
085261c8 AK |
1476 | vlr\t%v0,%v1 |
1477 | vzero\t%v0 | |
1478 | vone\t%v0 | |
1479 | vlvgp\t%v0,%1,%N1 | |
1480 | # | |
1481 | vl\t%v0,%1 | |
1482 | vst\t%v1,%0 | |
4023fb28 | 1483 | # |
19b63d8e | 1484 | #" |
085261c8 AK |
1485 | [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*") |
1486 | (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*") | |
285363a1 | 1487 | (set_attr "cpu_facility" "*,*,vx,vx,vx,vx,vx,vx,vx,*,*")]) |
4023fb28 UW |
1488 | |
1489 | (define_split | |
1490 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1491 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1492 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
1493 | && !s_operand (operands[0], TImode) |
1494 | && !s_operand (operands[1], TImode) | |
dc65c307 | 1495 | && s390_split_ok_p (operands[0], operands[1], TImode, 0)" |
4023fb28 UW |
1496 | [(set (match_dup 2) (match_dup 4)) |
1497 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1498 | { |
dc65c307 UW |
1499 | operands[2] = operand_subword (operands[0], 0, 0, TImode); |
1500 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1501 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
1502 | operands[5] = operand_subword (operands[1], 1, 0, TImode); | |
1503 | }) | |
1504 | ||
1505 | (define_split | |
1506 | [(set (match_operand:TI 0 "nonimmediate_operand" "") | |
1507 | (match_operand:TI 1 "general_operand" ""))] | |
9602b6a1 | 1508 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
1509 | && !s_operand (operands[0], TImode) |
1510 | && !s_operand (operands[1], TImode) | |
dc65c307 UW |
1511 | && s390_split_ok_p (operands[0], operands[1], TImode, 1)" |
1512 | [(set (match_dup 2) (match_dup 4)) | |
1513 | (set (match_dup 3) (match_dup 5))] | |
1514 | { | |
1515 | operands[2] = operand_subword (operands[0], 1, 0, TImode); | |
1516 | operands[3] = operand_subword (operands[0], 0, 0, TImode); | |
1517 | operands[4] = operand_subword (operands[1], 1, 0, TImode); | |
1518 | operands[5] = operand_subword (operands[1], 0, 0, TImode); | |
1519 | }) | |
4023fb28 | 1520 | |
085261c8 AK |
1521 | ; Use part of the TImode target reg to perform the address |
1522 | ; calculation. If the TImode value is supposed to be copied into a VR | |
1523 | ; this splitter is not necessary. | |
4023fb28 UW |
1524 | (define_split |
1525 | [(set (match_operand:TI 0 "register_operand" "") | |
1526 | (match_operand:TI 1 "memory_operand" ""))] | |
9602b6a1 | 1527 | "TARGET_ZARCH && reload_completed |
085261c8 | 1528 | && !VECTOR_REG_P (operands[0]) |
4023fb28 | 1529 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1530 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1531 | { |
1532 | rtx addr = operand_subword (operands[0], 1, 0, TImode); | |
9602b6a1 | 1533 | addr = gen_lowpart (Pmode, addr); |
a41c6c53 UW |
1534 | s390_load_address (addr, XEXP (operands[1], 0)); |
1535 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1536 | }) |
1537 | ||
833cd70a | 1538 | |
085261c8 AK |
1539 | ; Split a VR -> GPR TImode move into 2 vector load GR from VR element. |
1540 | ; For the higher order bits we do simply a DImode move while the | |
1541 | ; second part is done via vec extract. Both will end up as vlgvg. | |
1542 | (define_split | |
1543 | [(set (match_operand:TI 0 "register_operand" "") | |
1544 | (match_operand:TI 1 "register_operand" ""))] | |
1545 | "TARGET_VX && reload_completed | |
1546 | && GENERAL_REG_P (operands[0]) | |
1547 | && VECTOR_REG_P (operands[1])" | |
1548 | [(set (match_dup 2) (match_dup 4)) | |
1549 | (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)] | |
1550 | UNSPEC_VEC_EXTRACT))] | |
1551 | { | |
1552 | operands[2] = operand_subword (operands[0], 0, 0, TImode); | |
1553 | operands[3] = operand_subword (operands[0], 1, 0, TImode); | |
1554 | operands[4] = gen_rtx_REG (DImode, REGNO (operands[1])); | |
1555 | operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1])); | |
1556 | }) | |
1557 | ||
833cd70a AK |
1558 | ; |
1559 | ; Patterns used for secondary reloads | |
1560 | ; | |
1561 | ||
963fc8d0 AK |
1562 | ; z10 provides move instructions accepting larl memory operands. |
1563 | ; Unfortunately there is no such variant for QI, TI and FP mode moves. | |
1564 | ; These patterns are also used for unaligned SI and DI accesses. | |
1565 | ||
085261c8 AK |
1566 | (define_expand "reload<ALL:mode><P:mode>_tomem_z10" |
1567 | [(parallel [(match_operand:ALL 0 "memory_operand" "") | |
1568 | (match_operand:ALL 1 "register_operand" "=d") | |
1569 | (match_operand:P 2 "register_operand" "=&a")])] | |
963fc8d0 AK |
1570 | "TARGET_Z10" |
1571 | { | |
1572 | s390_reload_symref_address (operands[1], operands[0], operands[2], 1); | |
1573 | DONE; | |
1574 | }) | |
1575 | ||
085261c8 AK |
1576 | (define_expand "reload<ALL:mode><P:mode>_toreg_z10" |
1577 | [(parallel [(match_operand:ALL 0 "register_operand" "=d") | |
1578 | (match_operand:ALL 1 "memory_operand" "") | |
1579 | (match_operand:P 2 "register_operand" "=a")])] | |
963fc8d0 AK |
1580 | "TARGET_Z10" |
1581 | { | |
1582 | s390_reload_symref_address (operands[0], operands[1], operands[2], 0); | |
1583 | DONE; | |
1584 | }) | |
1585 | ||
1586 | (define_expand "reload<P:mode>_larl_odd_addend_z10" | |
1587 | [(parallel [(match_operand:P 0 "register_operand" "=d") | |
1588 | (match_operand:P 1 "larl_operand" "") | |
1589 | (match_operand:P 2 "register_operand" "=a")])] | |
1590 | "TARGET_Z10" | |
1591 | { | |
1592 | s390_reload_larl_operand (operands[0], operands[1], operands[2]); | |
1593 | DONE; | |
1594 | }) | |
1595 | ||
833cd70a AK |
1596 | ; Handles loading a PLUS (load address) expression |
1597 | ||
1598 | (define_expand "reload<mode>_plus" | |
1599 | [(parallel [(match_operand:P 0 "register_operand" "=a") | |
1600 | (match_operand:P 1 "s390_plus_operand" "") | |
1601 | (match_operand:P 2 "register_operand" "=&a")])] | |
1602 | "" | |
1603 | { | |
1604 | s390_expand_plus_operand (operands[0], operands[1], operands[2]); | |
1605 | DONE; | |
1606 | }) | |
1607 | ||
085261c8 AK |
1608 | ; Not all the indirect memory access instructions support the full |
1609 | ; format (long disp + index + base). So whenever a move from/to such | |
1610 | ; an address is required and the instruction cannot deal with it we do | |
1611 | ; a load address into a scratch register first and use this as the new | |
1612 | ; base register. | |
1613 | ; This in particular is used for: | |
1614 | ; - non-offsetable memory accesses for multiword moves | |
1615 | ; - full vector reg moves with long displacements | |
833cd70a | 1616 | |
085261c8 | 1617 | (define_expand "reload<mode>_la_in" |
833cd70a AK |
1618 | [(parallel [(match_operand 0 "register_operand" "") |
1619 | (match_operand 1 "" "") | |
1620 | (match_operand:P 2 "register_operand" "=&a")])] | |
1621 | "" | |
1622 | { | |
1623 | gcc_assert (MEM_P (operands[1])); | |
1624 | s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); | |
1625 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1626 | emit_move_insn (operands[0], operands[1]); | |
1627 | DONE; | |
1628 | }) | |
1629 | ||
085261c8 | 1630 | (define_expand "reload<mode>_la_out" |
833cd70a AK |
1631 | [(parallel [(match_operand 0 "" "") |
1632 | (match_operand 1 "register_operand" "") | |
1633 | (match_operand:P 2 "register_operand" "=&a")])] | |
1634 | "" | |
dc65c307 | 1635 | { |
9c3c3dcc | 1636 | gcc_assert (MEM_P (operands[0])); |
9c90a97e | 1637 | s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); |
dc65c307 UW |
1638 | operands[0] = replace_equiv_address (operands[0], operands[2]); |
1639 | emit_move_insn (operands[0], operands[1]); | |
1640 | DONE; | |
1641 | }) | |
9db1d521 | 1642 | |
1f9e1fc6 AK |
1643 | (define_expand "reload<mode>_PIC_addr" |
1644 | [(parallel [(match_operand 0 "register_operand" "=d") | |
1645 | (match_operand 1 "larl_operand" "") | |
1646 | (match_operand:P 2 "register_operand" "=a")])] | |
1647 | "" | |
1648 | { | |
0a2aaacc KG |
1649 | rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); |
1650 | emit_move_insn (operands[0], new_rtx); | |
1f9e1fc6 AK |
1651 | }) |
1652 | ||
9db1d521 HP |
1653 | ; |
1654 | ; movdi instruction pattern(s). | |
1655 | ; | |
1656 | ||
9db1d521 HP |
1657 | (define_expand "movdi" |
1658 | [(set (match_operand:DI 0 "general_operand" "") | |
1659 | (match_operand:DI 1 "general_operand" ""))] | |
1660 | "" | |
9db1d521 | 1661 | { |
fd3cd001 | 1662 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1663 | if (TARGET_64BIT |
1664 | && (SYMBOLIC_CONST (operands[1]) | |
1665 | || (GET_CODE (operands[1]) == PLUS | |
1666 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1667 | && SYMBOLIC_CONST (XEXP (operands[1], 1))))) | |
fd3cd001 | 1668 | emit_symbolic_move (operands); |
10bbf137 | 1669 | }) |
9db1d521 | 1670 | |
4023fb28 UW |
1671 | (define_insn "*movdi_larl" |
1672 | [(set (match_operand:DI 0 "register_operand" "=d") | |
1673 | (match_operand:DI 1 "larl_operand" "X"))] | |
1674 | "TARGET_64BIT | |
8e509cf9 | 1675 | && !FP_REG_P (operands[0])" |
d40c829f | 1676 | "larl\t%0,%1" |
4023fb28 | 1677 | [(set_attr "op_type" "RIL") |
9381e3f1 WG |
1678 | (set_attr "type" "larl") |
1679 | (set_attr "z10prop" "z10_super_A1")]) | |
4023fb28 | 1680 | |
3af8e996 | 1681 | (define_insn "*movdi_64" |
85dae55a | 1682 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1683 | "=d, d, d, d, d, d, d, d,f,d,d,d,d,d,T,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d,v,R") |
85dae55a | 1684 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1685 | " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,T,d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,R,v"))] |
9602b6a1 | 1686 | "TARGET_ZARCH" |
85dae55a AK |
1687 | "@ |
1688 | lghi\t%0,%h1 | |
1689 | llihh\t%0,%i1 | |
1690 | llihl\t%0,%i1 | |
1691 | llilh\t%0,%i1 | |
1692 | llill\t%0,%i1 | |
1693 | lgfi\t%0,%1 | |
1694 | llihf\t%0,%k1 | |
1695 | llilf\t%0,%k1 | |
1696 | ldgr\t%0,%1 | |
1697 | lgdr\t%0,%1 | |
1698 | lay\t%0,%a1 | |
963fc8d0 | 1699 | lgrl\t%0,%1 |
85dae55a AK |
1700 | lgr\t%0,%1 |
1701 | lg\t%0,%1 | |
1702 | stg\t%1,%0 | |
1703 | ldr\t%0,%1 | |
1704 | ld\t%0,%1 | |
1705 | ldy\t%0,%1 | |
1706 | std\t%1,%0 | |
1707 | stdy\t%1,%0 | |
963fc8d0 AK |
1708 | stgrl\t%1,%0 |
1709 | mvghi\t%0,%1 | |
85dae55a AK |
1710 | # |
1711 | # | |
1712 | stam\t%1,%N1,%S0 | |
085261c8 AK |
1713 | lam\t%0,%N0,%S1 |
1714 | vleig\t%v0,%h1,0 | |
1715 | vlr\t%v0,%v1 | |
1716 | vlvgg\t%v0,%1,0 | |
1717 | vlgvg\t%0,%v1,0 | |
1718 | vleg\t%v0,%1,0 | |
1719 | vsteg\t%v1,%0,0" | |
963fc8d0 | 1720 | [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, |
085261c8 | 1721 | RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
963fc8d0 | 1722 | (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, |
085261c8 AK |
1723 | floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*, |
1724 | *,*,*,*,*,*,*") | |
3af8e996 | 1725 | (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, |
963fc8d0 | 1726 | z10,*,*,*,*,*,longdisp,*,longdisp, |
285363a1 | 1727 | z10,z10,*,*,*,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
1728 | (set_attr "z10prop" "z10_fwd_A1, |
1729 | z10_fwd_E1, | |
1730 | z10_fwd_E1, | |
1731 | z10_fwd_E1, | |
1732 | z10_fwd_E1, | |
1733 | z10_fwd_A1, | |
1734 | z10_fwd_E1, | |
1735 | z10_fwd_E1, | |
1736 | *, | |
1737 | *, | |
1738 | z10_fwd_A1, | |
1739 | z10_fwd_A3, | |
1740 | z10_fr_E1, | |
1741 | z10_fwd_A3, | |
1742 | z10_rec, | |
1743 | *, | |
1744 | *, | |
1745 | *, | |
1746 | *, | |
1747 | *, | |
1748 | z10_rec, | |
1749 | z10_super, | |
1750 | *, | |
1751 | *, | |
1752 | *, | |
085261c8 | 1753 | *,*,*,*,*,*,*") |
9381e3f1 | 1754 | ]) |
c5aa1d12 UW |
1755 | |
1756 | (define_split | |
1757 | [(set (match_operand:DI 0 "register_operand" "") | |
1758 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1759 | "TARGET_ZARCH && ACCESS_REG_P (operands[1])" |
c5aa1d12 UW |
1760 | [(set (match_dup 2) (match_dup 3)) |
1761 | (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) | |
1762 | (set (strict_low_part (match_dup 2)) (match_dup 4))] | |
1763 | "operands[2] = gen_lowpart (SImode, operands[0]); | |
1764 | s390_split_access_reg (operands[1], &operands[4], &operands[3]);") | |
1765 | ||
1766 | (define_split | |
1767 | [(set (match_operand:DI 0 "register_operand" "") | |
1768 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1769 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1770 | && dead_or_set_p (insn, operands[1])" |
1771 | [(set (match_dup 3) (match_dup 2)) | |
1772 | (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) | |
1773 | (set (match_dup 4) (match_dup 2))] | |
1774 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1775 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
1776 | ||
1777 | (define_split | |
1778 | [(set (match_operand:DI 0 "register_operand" "") | |
1779 | (match_operand:DI 1 "register_operand" ""))] | |
9602b6a1 | 1780 | "TARGET_ZARCH && ACCESS_REG_P (operands[0]) |
c5aa1d12 UW |
1781 | && !dead_or_set_p (insn, operands[1])" |
1782 | [(set (match_dup 3) (match_dup 2)) | |
1783 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) | |
1784 | (set (match_dup 4) (match_dup 2)) | |
1785 | (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] | |
1786 | "operands[2] = gen_lowpart (SImode, operands[1]); | |
1787 | s390_split_access_reg (operands[0], &operands[3], &operands[4]);") | |
9db1d521 HP |
1788 | |
1789 | (define_insn "*movdi_31" | |
963fc8d0 | 1790 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 1791 | "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") |
963fc8d0 | 1792 | (match_operand:DI 1 "general_operand" |
3e4be43f | 1793 | " Q,S,d,d,dPT,d, *f, R, T,*f,*f,b"))] |
9602b6a1 | 1794 | "!TARGET_ZARCH" |
4023fb28 | 1795 | "@ |
fc0ea003 | 1796 | lm\t%0,%N0,%S1 |
c4d50129 | 1797 | lmy\t%0,%N0,%S1 |
fc0ea003 | 1798 | stm\t%1,%N1,%S0 |
c4d50129 | 1799 | stmy\t%1,%N1,%S0 |
4023fb28 UW |
1800 | # |
1801 | # | |
d40c829f UW |
1802 | ldr\t%0,%1 |
1803 | ld\t%0,%1 | |
1804 | ldy\t%0,%1 | |
1805 | std\t%1,%0 | |
1806 | stdy\t%1,%0 | |
19b63d8e | 1807 | #" |
f2dc2f86 AK |
1808 | [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") |
1809 | (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") | |
3e4be43f | 1810 | (set_attr "cpu_facility" "*,longdisp,*,longdisp,*,*,*,*,longdisp,*,longdisp,z10")]) |
963fc8d0 AK |
1811 | |
1812 | ; For a load from a symbol ref we can use one of the target registers | |
1813 | ; together with larl to load the address. | |
1814 | (define_split | |
1815 | [(set (match_operand:DI 0 "register_operand" "") | |
1816 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1817 | "!TARGET_ZARCH && reload_completed && TARGET_Z10 |
963fc8d0 AK |
1818 | && larl_operand (XEXP (operands[1], 0), SImode)" |
1819 | [(set (match_dup 2) (match_dup 3)) | |
1820 | (set (match_dup 0) (match_dup 1))] | |
1821 | { | |
1822 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1823 | operands[3] = XEXP (operands[1], 0); | |
1824 | operands[1] = replace_equiv_address (operands[1], operands[2]); | |
1825 | }) | |
4023fb28 UW |
1826 | |
1827 | (define_split | |
1828 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1829 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1830 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
1831 | && !s_operand (operands[0], DImode) |
1832 | && !s_operand (operands[1], DImode) | |
dc65c307 | 1833 | && s390_split_ok_p (operands[0], operands[1], DImode, 0)" |
4023fb28 UW |
1834 | [(set (match_dup 2) (match_dup 4)) |
1835 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 1836 | { |
dc65c307 UW |
1837 | operands[2] = operand_subword (operands[0], 0, 0, DImode); |
1838 | operands[3] = operand_subword (operands[0], 1, 0, DImode); | |
1839 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
1840 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
1841 | }) | |
1842 | ||
1843 | (define_split | |
1844 | [(set (match_operand:DI 0 "nonimmediate_operand" "") | |
1845 | (match_operand:DI 1 "general_operand" ""))] | |
9602b6a1 | 1846 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
1847 | && !s_operand (operands[0], DImode) |
1848 | && !s_operand (operands[1], DImode) | |
dc65c307 UW |
1849 | && s390_split_ok_p (operands[0], operands[1], DImode, 1)" |
1850 | [(set (match_dup 2) (match_dup 4)) | |
1851 | (set (match_dup 3) (match_dup 5))] | |
1852 | { | |
1853 | operands[2] = operand_subword (operands[0], 1, 0, DImode); | |
1854 | operands[3] = operand_subword (operands[0], 0, 0, DImode); | |
1855 | operands[4] = operand_subword (operands[1], 1, 0, DImode); | |
1856 | operands[5] = operand_subword (operands[1], 0, 0, DImode); | |
1857 | }) | |
9db1d521 | 1858 | |
4023fb28 UW |
1859 | (define_split |
1860 | [(set (match_operand:DI 0 "register_operand" "") | |
1861 | (match_operand:DI 1 "memory_operand" ""))] | |
9602b6a1 | 1862 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 1863 | && !FP_REG_P (operands[0]) |
4023fb28 | 1864 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 1865 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 UW |
1866 | { |
1867 | rtx addr = operand_subword (operands[0], 1, 0, DImode); | |
1868 | s390_load_address (addr, XEXP (operands[1], 0)); | |
1869 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
1870 | }) |
1871 | ||
84817c5d UW |
1872 | (define_peephole2 |
1873 | [(set (match_operand:DI 0 "register_operand" "") | |
1874 | (mem:DI (match_operand 1 "address_operand" "")))] | |
9602b6a1 | 1875 | "TARGET_ZARCH |
84817c5d UW |
1876 | && !FP_REG_P (operands[0]) |
1877 | && GET_CODE (operands[1]) == SYMBOL_REF | |
1878 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
1879 | && get_pool_mode (operands[1]) == DImode | |
1880 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
1881 | [(set (match_dup 0) (match_dup 2))] | |
1882 | "operands[2] = get_pool_constant (operands[1]);") | |
1883 | ||
7bdff56f UW |
1884 | (define_insn "*la_64" |
1885 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 1886 | (match_operand:QI 1 "address_operand" "ZR,ZT"))] |
7bdff56f UW |
1887 | "TARGET_64BIT" |
1888 | "@ | |
1889 | la\t%0,%a1 | |
1890 | lay\t%0,%a1" | |
1891 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 1892 | (set_attr "type" "la") |
3e4be43f | 1893 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 1894 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
1895 | |
1896 | (define_peephole2 | |
1897 | [(parallel | |
1898 | [(set (match_operand:DI 0 "register_operand" "") | |
1899 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 1900 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 1901 | "TARGET_64BIT |
e1d5ee28 | 1902 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
1903 | [(set (match_dup 0) (match_dup 1))] |
1904 | "") | |
1905 | ||
1906 | (define_peephole2 | |
1907 | [(set (match_operand:DI 0 "register_operand" "") | |
1908 | (match_operand:DI 1 "register_operand" "")) | |
1909 | (parallel | |
1910 | [(set (match_dup 0) | |
1911 | (plus:DI (match_dup 0) | |
1912 | (match_operand:DI 2 "nonmemory_operand" ""))) | |
ae156f85 | 1913 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
1914 | "TARGET_64BIT |
1915 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 1916 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
1917 | [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] |
1918 | "") | |
1919 | ||
9db1d521 HP |
1920 | ; |
1921 | ; movsi instruction pattern(s). | |
1922 | ; | |
1923 | ||
9db1d521 HP |
1924 | (define_expand "movsi" |
1925 | [(set (match_operand:SI 0 "general_operand" "") | |
1926 | (match_operand:SI 1 "general_operand" ""))] | |
1927 | "" | |
9db1d521 | 1928 | { |
fd3cd001 | 1929 | /* Handle symbolic constants. */ |
e4f2cd43 AK |
1930 | if (!TARGET_64BIT |
1931 | && (SYMBOLIC_CONST (operands[1]) | |
1932 | || (GET_CODE (operands[1]) == PLUS | |
1933 | && XEXP (operands[1], 0) == pic_offset_table_rtx | |
1934 | && SYMBOLIC_CONST (XEXP(operands[1], 1))))) | |
fd3cd001 | 1935 | emit_symbolic_move (operands); |
10bbf137 | 1936 | }) |
9db1d521 | 1937 | |
9e8327e3 UW |
1938 | (define_insn "*movsi_larl" |
1939 | [(set (match_operand:SI 0 "register_operand" "=d") | |
1940 | (match_operand:SI 1 "larl_operand" "X"))] | |
1941 | "!TARGET_64BIT && TARGET_CPU_ZARCH | |
1942 | && !FP_REG_P (operands[0])" | |
1943 | "larl\t%0,%1" | |
1944 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 1945 | (set_attr "type" "larl") |
729e750f | 1946 | (set_attr "z10prop" "z10_fwd_A1")]) |
9e8327e3 | 1947 | |
f19a9af7 | 1948 | (define_insn "*movsi_zarch" |
2f7e5a0d | 1949 | [(set (match_operand:SI 0 "nonimmediate_operand" |
3e4be43f | 1950 | "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d,v,R") |
2f7e5a0d | 1951 | (match_operand:SI 1 "general_operand" |
3e4be43f | 1952 | " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,R,v"))] |
f19a9af7 | 1953 | "TARGET_ZARCH" |
9db1d521 | 1954 | "@ |
f19a9af7 AK |
1955 | lhi\t%0,%h1 |
1956 | llilh\t%0,%i1 | |
1957 | llill\t%0,%i1 | |
ec24698e | 1958 | iilf\t%0,%o1 |
f19a9af7 | 1959 | lay\t%0,%a1 |
963fc8d0 | 1960 | lrl\t%0,%1 |
d40c829f UW |
1961 | lr\t%0,%1 |
1962 | l\t%0,%1 | |
1963 | ly\t%0,%1 | |
1964 | st\t%1,%0 | |
1965 | sty\t%1,%0 | |
ae1c6198 | 1966 | ldr\t%0,%1 |
d40c829f | 1967 | ler\t%0,%1 |
085261c8 | 1968 | lde\t%0,%1 |
d40c829f UW |
1969 | le\t%0,%1 |
1970 | ley\t%0,%1 | |
1971 | ste\t%1,%0 | |
1972 | stey\t%1,%0 | |
c5aa1d12 UW |
1973 | ear\t%0,%1 |
1974 | sar\t%0,%1 | |
1975 | stam\t%1,%1,%S0 | |
963fc8d0 AK |
1976 | strl\t%1,%0 |
1977 | mvhi\t%0,%1 | |
085261c8 AK |
1978 | lam\t%0,%0,%S1 |
1979 | vleif\t%v0,%h1,0 | |
1980 | vlr\t%v0,%v1 | |
1981 | vlvgf\t%v0,%1,0 | |
1982 | vlgvf\t%0,%v1,0 | |
1983 | vlef\t%v0,%1,0 | |
1984 | vstef\t%v1,%0,0" | |
963fc8d0 | 1985 | [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, |
ae1c6198 | 1986 | RR,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX") |
9381e3f1 WG |
1987 | (set_attr "type" "*, |
1988 | *, | |
1989 | *, | |
1990 | *, | |
1991 | la, | |
1992 | larl, | |
1993 | lr, | |
1994 | load, | |
1995 | load, | |
1996 | store, | |
1997 | store, | |
1998 | floadsf, | |
1999 | floadsf, | |
2000 | floadsf, | |
085261c8 AK |
2001 | floadsf, |
2002 | floadsf, | |
9381e3f1 WG |
2003 | fstoresf, |
2004 | fstoresf, | |
2005 | *, | |
2006 | *, | |
2007 | *, | |
2008 | larl, | |
2009 | *, | |
085261c8 | 2010 | *,*,*,*,*,*,*") |
963fc8d0 | 2011 | (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, |
285363a1 | 2012 | vx,*,vx,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2013 | (set_attr "z10prop" "z10_fwd_A1, |
2014 | z10_fwd_E1, | |
2015 | z10_fwd_E1, | |
2016 | z10_fwd_A1, | |
2017 | z10_fwd_A1, | |
2018 | z10_fwd_A3, | |
2019 | z10_fr_E1, | |
2020 | z10_fwd_A3, | |
2021 | z10_fwd_A3, | |
729e750f | 2022 | z10_rec, |
9381e3f1 WG |
2023 | z10_rec, |
2024 | *, | |
2025 | *, | |
2026 | *, | |
2027 | *, | |
2028 | *, | |
085261c8 AK |
2029 | *, |
2030 | *, | |
9381e3f1 WG |
2031 | z10_super_E1, |
2032 | z10_super, | |
2033 | *, | |
2034 | z10_rec, | |
2035 | z10_super, | |
085261c8 | 2036 | *,*,*,*,*,*,*")]) |
f19a9af7 AK |
2037 | |
2038 | (define_insn "*movsi_esa" | |
085261c8 AK |
2039 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t") |
2040 | (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))] | |
f19a9af7 AK |
2041 | "!TARGET_ZARCH" |
2042 | "@ | |
2043 | lhi\t%0,%h1 | |
2044 | lr\t%0,%1 | |
2045 | l\t%0,%1 | |
2046 | st\t%1,%0 | |
ae1c6198 | 2047 | ldr\t%0,%1 |
f19a9af7 | 2048 | ler\t%0,%1 |
085261c8 | 2049 | lde\t%0,%1 |
f19a9af7 AK |
2050 | le\t%0,%1 |
2051 | ste\t%1,%0 | |
c5aa1d12 UW |
2052 | ear\t%0,%1 |
2053 | sar\t%0,%1 | |
2054 | stam\t%1,%1,%S0 | |
f2dc2f86 | 2055 | lam\t%0,%0,%S1" |
ae1c6198 | 2056 | [(set_attr "op_type" "RI,RR,RX,RX,RR,RR,RXE,RX,RX,RRE,RRE,RS,RS") |
085261c8 AK |
2057 | (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*") |
2058 | (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1, | |
2059 | z10_super,*,*") | |
285363a1 | 2060 | (set_attr "cpu_facility" "*,*,*,*,vx,*,vx,*,*,*,*,*,*") |
9381e3f1 | 2061 | ]) |
9db1d521 | 2062 | |
84817c5d UW |
2063 | (define_peephole2 |
2064 | [(set (match_operand:SI 0 "register_operand" "") | |
2065 | (mem:SI (match_operand 1 "address_operand" "")))] | |
2066 | "!FP_REG_P (operands[0]) | |
2067 | && GET_CODE (operands[1]) == SYMBOL_REF | |
2068 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2069 | && get_pool_mode (operands[1]) == SImode | |
2070 | && legitimate_reload_constant_p (get_pool_constant (operands[1]))" | |
2071 | [(set (match_dup 0) (match_dup 2))] | |
2072 | "operands[2] = get_pool_constant (operands[1]);") | |
9db1d521 | 2073 | |
7bdff56f UW |
2074 | (define_insn "*la_31" |
2075 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2076 | (match_operand:QI 1 "address_operand" "ZR,ZT"))] |
7bdff56f UW |
2077 | "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" |
2078 | "@ | |
2079 | la\t%0,%a1 | |
2080 | lay\t%0,%a1" | |
2081 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2082 | (set_attr "type" "la") |
3e4be43f | 2083 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2084 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2085 | |
2086 | (define_peephole2 | |
2087 | [(parallel | |
2088 | [(set (match_operand:SI 0 "register_operand" "") | |
2089 | (match_operand:QI 1 "address_operand" "")) | |
ae156f85 | 2090 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f | 2091 | "!TARGET_64BIT |
e1d5ee28 | 2092 | && preferred_la_operand_p (operands[1], const0_rtx)" |
7bdff56f UW |
2093 | [(set (match_dup 0) (match_dup 1))] |
2094 | "") | |
2095 | ||
2096 | (define_peephole2 | |
2097 | [(set (match_operand:SI 0 "register_operand" "") | |
2098 | (match_operand:SI 1 "register_operand" "")) | |
2099 | (parallel | |
2100 | [(set (match_dup 0) | |
2101 | (plus:SI (match_dup 0) | |
2102 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
ae156f85 | 2103 | (clobber (reg:CC CC_REGNUM))])] |
7bdff56f UW |
2104 | "!TARGET_64BIT |
2105 | && !reg_overlap_mentioned_p (operands[0], operands[2]) | |
e1d5ee28 | 2106 | && preferred_la_operand_p (operands[1], operands[2])" |
7bdff56f UW |
2107 | [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] |
2108 | "") | |
2109 | ||
2110 | (define_insn "*la_31_and" | |
2111 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2112 | (and:SI (match_operand:QI 1 "address_operand" "ZR,ZT") |
7bdff56f UW |
2113 | (const_int 2147483647)))] |
2114 | "!TARGET_64BIT" | |
2115 | "@ | |
2116 | la\t%0,%a1 | |
2117 | lay\t%0,%a1" | |
2118 | [(set_attr "op_type" "RX,RXY") | |
9381e3f1 | 2119 | (set_attr "type" "la") |
3e4be43f | 2120 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2121 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f UW |
2122 | |
2123 | (define_insn_and_split "*la_31_and_cc" | |
2124 | [(set (match_operand:SI 0 "register_operand" "=d") | |
2125 | (and:SI (match_operand:QI 1 "address_operand" "p") | |
2126 | (const_int 2147483647))) | |
ae156f85 | 2127 | (clobber (reg:CC CC_REGNUM))] |
7bdff56f UW |
2128 | "!TARGET_64BIT" |
2129 | "#" | |
2130 | "&& reload_completed" | |
2131 | [(set (match_dup 0) | |
2132 | (and:SI (match_dup 1) (const_int 2147483647)))] | |
2133 | "" | |
2134 | [(set_attr "op_type" "RX") | |
2135 | (set_attr "type" "la")]) | |
2136 | ||
2137 | (define_insn "force_la_31" | |
2138 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 2139 | (match_operand:QI 1 "address_operand" "ZR,ZT")) |
7bdff56f UW |
2140 | (use (const_int 0))] |
2141 | "!TARGET_64BIT" | |
2142 | "@ | |
2143 | la\t%0,%a1 | |
2144 | lay\t%0,%a1" | |
2145 | [(set_attr "op_type" "RX") | |
9381e3f1 | 2146 | (set_attr "type" "la") |
3e4be43f | 2147 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2148 | (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) |
7bdff56f | 2149 | |
9db1d521 HP |
2150 | ; |
2151 | ; movhi instruction pattern(s). | |
2152 | ; | |
2153 | ||
02ed3c5e UW |
2154 | (define_expand "movhi" |
2155 | [(set (match_operand:HI 0 "nonimmediate_operand" "") | |
2156 | (match_operand:HI 1 "general_operand" ""))] | |
2157 | "" | |
2158 | { | |
2f7e5a0d | 2159 | /* Make it explicit that loading a register from memory |
02ed3c5e | 2160 | always sign-extends (at least) to SImode. */ |
b3a13419 | 2161 | if (optimize && can_create_pseudo_p () |
02ed3c5e | 2162 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2163 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e UW |
2164 | { |
2165 | rtx tmp = gen_reg_rtx (SImode); | |
2166 | rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); | |
f7df4a84 | 2167 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2168 | operands[1] = gen_lowpart (HImode, tmp); |
2169 | } | |
2170 | }) | |
2171 | ||
2172 | (define_insn "*movhi" | |
3e4be43f UW |
2173 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d,v,R") |
2174 | (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,R,v"))] | |
9db1d521 HP |
2175 | "" |
2176 | "@ | |
d40c829f UW |
2177 | lr\t%0,%1 |
2178 | lhi\t%0,%h1 | |
2179 | lh\t%0,%1 | |
2180 | lhy\t%0,%1 | |
963fc8d0 | 2181 | lhrl\t%0,%1 |
d40c829f UW |
2182 | sth\t%1,%0 |
2183 | sthy\t%1,%0 | |
963fc8d0 | 2184 | sthrl\t%1,%0 |
085261c8 AK |
2185 | mvhhi\t%0,%1 |
2186 | vleih\t%v0,%h1,0 | |
2187 | vlr\t%v0,%v1 | |
2188 | vlvgh\t%v0,%1,0 | |
2189 | vlgvh\t%0,%v1,0 | |
2190 | vleh\t%v0,%1,0 | |
2191 | vsteh\t%v1,%0,0" | |
2192 | [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX") | |
2193 | (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*") | |
285363a1 | 2194 | (set_attr "cpu_facility" "*,*,*,longdisp,z10,*,longdisp,z10,z10,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2195 | (set_attr "z10prop" "z10_fr_E1, |
2196 | z10_fwd_A1, | |
2197 | z10_super_E1, | |
2198 | z10_super_E1, | |
2199 | z10_super_E1, | |
729e750f | 2200 | z10_rec, |
9381e3f1 WG |
2201 | z10_rec, |
2202 | z10_rec, | |
085261c8 | 2203 | z10_super,*,*,*,*,*,*")]) |
9db1d521 | 2204 | |
84817c5d UW |
2205 | (define_peephole2 |
2206 | [(set (match_operand:HI 0 "register_operand" "") | |
2207 | (mem:HI (match_operand 1 "address_operand" "")))] | |
2208 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2209 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2210 | && get_pool_mode (operands[1]) == HImode | |
2211 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2212 | [(set (match_dup 0) (match_dup 2))] | |
2213 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2214 | |
9db1d521 HP |
2215 | ; |
2216 | ; movqi instruction pattern(s). | |
2217 | ; | |
2218 | ||
02ed3c5e UW |
2219 | (define_expand "movqi" |
2220 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2221 | (match_operand:QI 1 "general_operand" ""))] | |
2222 | "" | |
2223 | { | |
c19ec8f9 | 2224 | /* On z/Architecture, zero-extending from memory to register |
02ed3c5e | 2225 | is just as fast as a QImode load. */ |
b3a13419 | 2226 | if (TARGET_ZARCH && optimize && can_create_pseudo_p () |
02ed3c5e | 2227 | && register_operand (operands[0], VOIDmode) |
8fff4fc1 | 2228 | && GET_CODE (operands[1]) == MEM) |
02ed3c5e | 2229 | { |
9602b6a1 AK |
2230 | rtx tmp = gen_reg_rtx (DImode); |
2231 | rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); | |
f7df4a84 | 2232 | emit_insn (gen_rtx_SET (tmp, ext)); |
02ed3c5e UW |
2233 | operands[1] = gen_lowpart (QImode, tmp); |
2234 | } | |
2235 | }) | |
4023fb28 | 2236 | |
02ed3c5e | 2237 | (define_insn "*movqi" |
3e4be43f UW |
2238 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d,v,R") |
2239 | (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,R,v"))] | |
9db1d521 HP |
2240 | "" |
2241 | "@ | |
d40c829f UW |
2242 | lr\t%0,%1 |
2243 | lhi\t%0,%b1 | |
2244 | ic\t%0,%1 | |
2245 | icy\t%0,%1 | |
2246 | stc\t%1,%0 | |
2247 | stcy\t%1,%0 | |
fc0ea003 | 2248 | mvi\t%S0,%b1 |
0a88561f | 2249 | mviy\t%S0,%b1 |
085261c8 AK |
2250 | # |
2251 | vleib\t%v0,%b1,0 | |
2252 | vlr\t%v0,%v1 | |
2253 | vlvgb\t%v0,%1,0 | |
2254 | vlgvb\t%0,%v1,0 | |
2255 | vleb\t%v0,%1,0 | |
2256 | vsteb\t%v1,%0,0" | |
2257 | [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX") | |
2258 | (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*") | |
285363a1 | 2259 | (set_attr "cpu_facility" "*,*,*,longdisp,*,longdisp,*,longdisp,*,vx,vx,vx,vx,vx,vx") |
9381e3f1 WG |
2260 | (set_attr "z10prop" "z10_fr_E1, |
2261 | z10_fwd_A1, | |
2262 | z10_super_E1, | |
2263 | z10_super_E1, | |
729e750f | 2264 | z10_rec, |
9381e3f1 WG |
2265 | z10_rec, |
2266 | z10_super, | |
0a88561f | 2267 | z10_super, |
085261c8 | 2268 | *,*,*,*,*,*,*")]) |
9db1d521 | 2269 | |
84817c5d UW |
2270 | (define_peephole2 |
2271 | [(set (match_operand:QI 0 "nonimmediate_operand" "") | |
2272 | (mem:QI (match_operand 1 "address_operand" "")))] | |
2273 | "GET_CODE (operands[1]) == SYMBOL_REF | |
2274 | && CONSTANT_POOL_ADDRESS_P (operands[1]) | |
2275 | && get_pool_mode (operands[1]) == QImode | |
2276 | && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" | |
2277 | [(set (match_dup 0) (match_dup 2))] | |
2278 | "operands[2] = get_pool_constant (operands[1]);") | |
4023fb28 | 2279 | |
9db1d521 | 2280 | ; |
05b9aaaa | 2281 | ; movstrictqi instruction pattern(s). |
9db1d521 HP |
2282 | ; |
2283 | ||
2284 | (define_insn "*movstrictqi" | |
d3632d41 UW |
2285 | [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) |
2286 | (match_operand:QI 1 "memory_operand" "R,T"))] | |
9db1d521 | 2287 | "" |
d3632d41 | 2288 | "@ |
d40c829f UW |
2289 | ic\t%0,%1 |
2290 | icy\t%0,%1" | |
9381e3f1 | 2291 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 2292 | (set_attr "cpu_facility" "*,longdisp") |
729e750f | 2293 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2294 | |
2295 | ; | |
2296 | ; movstricthi instruction pattern(s). | |
2297 | ; | |
2298 | ||
2299 | (define_insn "*movstricthi" | |
d3632d41 | 2300 | [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) |
575f7c2b | 2301 | (match_operand:HI 1 "memory_operand" "Q,S")) |
ae156f85 | 2302 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 2303 | "" |
d3632d41 | 2304 | "@ |
fc0ea003 UW |
2305 | icm\t%0,3,%S1 |
2306 | icmy\t%0,3,%S1" | |
9381e3f1 | 2307 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2308 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 2309 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 HP |
2310 | |
2311 | ; | |
2312 | ; movstrictsi instruction pattern(s). | |
2313 | ; | |
2314 | ||
05b9aaaa | 2315 | (define_insn "movstrictsi" |
c5aa1d12 UW |
2316 | [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) |
2317 | (match_operand:SI 1 "general_operand" "d,R,T,t"))] | |
9602b6a1 | 2318 | "TARGET_ZARCH" |
9db1d521 | 2319 | "@ |
d40c829f UW |
2320 | lr\t%0,%1 |
2321 | l\t%0,%1 | |
c5aa1d12 UW |
2322 | ly\t%0,%1 |
2323 | ear\t%0,%1" | |
2324 | [(set_attr "op_type" "RR,RX,RXY,RRE") | |
9381e3f1 | 2325 | (set_attr "type" "lr,load,load,*") |
3e4be43f | 2326 | (set_attr "cpu_facility" "*,*,longdisp,*") |
9381e3f1 | 2327 | (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) |
9db1d521 | 2328 | |
f61a2c7d | 2329 | ; |
609e7e80 | 2330 | ; mov(tf|td) instruction pattern(s). |
f61a2c7d AK |
2331 | ; |
2332 | ||
609e7e80 AK |
2333 | (define_expand "mov<mode>" |
2334 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") | |
2335 | (match_operand:TD_TF 1 "general_operand" ""))] | |
f61a2c7d AK |
2336 | "" |
2337 | "") | |
2338 | ||
609e7e80 | 2339 | (define_insn "*mov<mode>_64" |
3e4be43f UW |
2340 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o,d,S, d,o") |
2341 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f,S,d,dT,d"))] | |
9602b6a1 | 2342 | "TARGET_ZARCH" |
f61a2c7d | 2343 | "@ |
65b1d8ea | 2344 | lzxr\t%0 |
f61a2c7d AK |
2345 | lxr\t%0,%1 |
2346 | # | |
2347 | # | |
2348 | lmg\t%0,%N0,%S1 | |
2349 | stmg\t%1,%N1,%S0 | |
2350 | # | |
f61a2c7d | 2351 | #" |
65b1d8ea AK |
2352 | [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") |
2353 | (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") | |
2354 | (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) | |
f61a2c7d | 2355 | |
609e7e80 | 2356 | (define_insn "*mov<mode>_31" |
65b1d8ea AK |
2357 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") |
2358 | (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] | |
9602b6a1 | 2359 | "!TARGET_ZARCH" |
f61a2c7d | 2360 | "@ |
65b1d8ea | 2361 | lzxr\t%0 |
f61a2c7d AK |
2362 | lxr\t%0,%1 |
2363 | # | |
f61a2c7d | 2364 | #" |
65b1d8ea AK |
2365 | [(set_attr "op_type" "RRE,RRE,*,*") |
2366 | (set_attr "type" "fsimptf,fsimptf,*,*") | |
2367 | (set_attr "cpu_facility" "z196,*,*,*")]) | |
f61a2c7d AK |
2368 | |
2369 | ; TFmode in GPRs splitters | |
2370 | ||
2371 | (define_split | |
609e7e80 AK |
2372 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2373 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2374 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
2375 | && !s_operand (operands[0], <MODE>mode) |
2376 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2377 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
f61a2c7d AK |
2378 | [(set (match_dup 2) (match_dup 4)) |
2379 | (set (match_dup 3) (match_dup 5))] | |
2380 | { | |
609e7e80 AK |
2381 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2382 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2383 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2384 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
f61a2c7d AK |
2385 | }) |
2386 | ||
2387 | (define_split | |
609e7e80 AK |
2388 | [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") |
2389 | (match_operand:TD_TF 1 "general_operand" ""))] | |
9602b6a1 | 2390 | "TARGET_ZARCH && reload_completed |
9d605427 AK |
2391 | && !s_operand (operands[0], <MODE>mode) |
2392 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2393 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
f61a2c7d AK |
2394 | [(set (match_dup 2) (match_dup 4)) |
2395 | (set (match_dup 3) (match_dup 5))] | |
2396 | { | |
609e7e80 AK |
2397 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2398 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2399 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2400 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
f61a2c7d AK |
2401 | }) |
2402 | ||
2403 | (define_split | |
609e7e80 AK |
2404 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2405 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9602b6a1 | 2406 | "TARGET_ZARCH && reload_completed |
085261c8 | 2407 | && GENERAL_REG_P (operands[0]) |
f61a2c7d AK |
2408 | && !s_operand (operands[1], VOIDmode)" |
2409 | [(set (match_dup 0) (match_dup 1))] | |
2410 | { | |
609e7e80 | 2411 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a9e6994a | 2412 | addr = gen_lowpart (Pmode, addr); |
f61a2c7d AK |
2413 | s390_load_address (addr, XEXP (operands[1], 0)); |
2414 | operands[1] = replace_equiv_address (operands[1], addr); | |
2415 | }) | |
2416 | ||
7b6baae1 | 2417 | ; TFmode in BFPs splitters |
f61a2c7d AK |
2418 | |
2419 | (define_split | |
609e7e80 AK |
2420 | [(set (match_operand:TD_TF 0 "register_operand" "") |
2421 | (match_operand:TD_TF 1 "memory_operand" ""))] | |
9381e3f1 | 2422 | "reload_completed && offsettable_memref_p (operands[1]) |
f61a2c7d AK |
2423 | && FP_REG_P (operands[0])" |
2424 | [(set (match_dup 2) (match_dup 4)) | |
2425 | (set (match_dup 3) (match_dup 5))] | |
2426 | { | |
609e7e80 AK |
2427 | operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], |
2428 | <MODE>mode, 0); | |
2429 | operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], | |
2430 | <MODE>mode, 8); | |
2431 | operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); | |
2432 | operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); | |
f61a2c7d AK |
2433 | }) |
2434 | ||
2435 | (define_split | |
609e7e80 AK |
2436 | [(set (match_operand:TD_TF 0 "memory_operand" "") |
2437 | (match_operand:TD_TF 1 "register_operand" ""))] | |
f61a2c7d AK |
2438 | "reload_completed && offsettable_memref_p (operands[0]) |
2439 | && FP_REG_P (operands[1])" | |
2440 | [(set (match_dup 2) (match_dup 4)) | |
2441 | (set (match_dup 3) (match_dup 5))] | |
2442 | { | |
609e7e80 AK |
2443 | operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); |
2444 | operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); | |
2445 | operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2446 | <MODE>mode, 0); | |
2447 | operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], | |
2448 | <MODE>mode, 8); | |
f61a2c7d AK |
2449 | }) |
2450 | ||
9db1d521 | 2451 | ; |
609e7e80 | 2452 | ; mov(df|dd) instruction pattern(s). |
9db1d521 HP |
2453 | ; |
2454 | ||
609e7e80 AK |
2455 | (define_expand "mov<mode>" |
2456 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") | |
2457 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9db1d521 | 2458 | "" |
13c025c1 | 2459 | "") |
9db1d521 | 2460 | |
609e7e80 AK |
2461 | (define_insn "*mov<mode>_64dfp" |
2462 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
590961cf | 2463 | "=f,f,f,d,f,f,R,T,d,d,d,d,b,T,v,v,v,d,v,R") |
609e7e80 | 2464 | (match_operand:DD_DF 1 "general_operand" |
590961cf | 2465 | " G,f,d,f,R,T,f,f,G,d,b,T,d,d,v,G,d,v,R,v"))] |
9602b6a1 | 2466 | "TARGET_DFP" |
85dae55a | 2467 | "@ |
65b1d8ea | 2468 | lzdr\t%0 |
85dae55a AK |
2469 | ldr\t%0,%1 |
2470 | ldgr\t%0,%1 | |
2471 | lgdr\t%0,%1 | |
2472 | ld\t%0,%1 | |
2473 | ldy\t%0,%1 | |
2474 | std\t%1,%0 | |
2475 | stdy\t%1,%0 | |
45e5214c | 2476 | lghi\t%0,0 |
85dae55a | 2477 | lgr\t%0,%1 |
085261c8 | 2478 | lgrl\t%0,%1 |
85dae55a | 2479 | lg\t%0,%1 |
085261c8 AK |
2480 | stgrl\t%1,%0 |
2481 | stg\t%1,%0 | |
2482 | vlr\t%v0,%v1 | |
590961cf | 2483 | vleig\t%v0,0,0 |
085261c8 AK |
2484 | vlvgg\t%v0,%1,0 |
2485 | vlgvg\t%0,%v1,0 | |
2486 | vleg\t%0,%1,0 | |
2487 | vsteg\t%1,%0,0" | |
590961cf | 2488 | [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRI,VRS,VRS,VRX,VRX") |
65b1d8ea | 2489 | (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, |
590961cf AK |
2490 | fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,*,load,store") |
2491 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*,*") | |
2492 | (set_attr "cpu_facility" "z196,*,*,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*,vx,vx,vx,vx,vx,vx")]) | |
85dae55a | 2493 | |
609e7e80 | 2494 | (define_insn "*mov<mode>_64" |
590961cf AK |
2495 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d,d,b,T") |
2496 | (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,T,d,d"))] | |
9602b6a1 | 2497 | "TARGET_ZARCH" |
9db1d521 | 2498 | "@ |
65b1d8ea | 2499 | lzdr\t%0 |
d40c829f UW |
2500 | ldr\t%0,%1 |
2501 | ld\t%0,%1 | |
2502 | ldy\t%0,%1 | |
2503 | std\t%1,%0 | |
2504 | stdy\t%1,%0 | |
45e5214c | 2505 | lghi\t%0,0 |
d40c829f | 2506 | lgr\t%0,%1 |
085261c8 | 2507 | lgrl\t%0,%1 |
d40c829f | 2508 | lg\t%0,%1 |
085261c8 | 2509 | stgrl\t%1,%0 |
590961cf AK |
2510 | stg\t%1,%0" |
2511 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY") | |
65b1d8ea | 2512 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, |
590961cf AK |
2513 | fstore<mode>,fstore<mode>,*,lr,load,load,store,store") |
2514 | (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") | |
2515 | (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,*,z10,*,z10,*")]) | |
609e7e80 AK |
2516 | |
2517 | (define_insn "*mov<mode>_31" | |
2518 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" | |
3e4be43f | 2519 | "=f,f,f,f,R,T,d,d,Q,S, d,o") |
609e7e80 | 2520 | (match_operand:DD_DF 1 "general_operand" |
3e4be43f | 2521 | " G,f,R,T,f,f,Q,S,d,d,dPT,d"))] |
9602b6a1 | 2522 | "!TARGET_ZARCH" |
9db1d521 | 2523 | "@ |
65b1d8ea | 2524 | lzdr\t%0 |
d40c829f UW |
2525 | ldr\t%0,%1 |
2526 | ld\t%0,%1 | |
2527 | ldy\t%0,%1 | |
2528 | std\t%1,%0 | |
2529 | stdy\t%1,%0 | |
fc0ea003 | 2530 | lm\t%0,%N0,%S1 |
c4d50129 | 2531 | lmy\t%0,%N0,%S1 |
fc0ea003 | 2532 | stm\t%1,%N1,%S0 |
c4d50129 | 2533 | stmy\t%1,%N1,%S0 |
4023fb28 | 2534 | # |
19b63d8e | 2535 | #" |
65b1d8ea AK |
2536 | [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") |
2537 | (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, | |
2538 | fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") | |
3e4be43f | 2539 | (set_attr "cpu_facility" "z196,*,*,longdisp,*,longdisp,*,longdisp,*,longdisp,*,*")]) |
4023fb28 UW |
2540 | |
2541 | (define_split | |
609e7e80 AK |
2542 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2543 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2544 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
2545 | && !s_operand (operands[0], <MODE>mode) |
2546 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2547 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" |
4023fb28 UW |
2548 | [(set (match_dup 2) (match_dup 4)) |
2549 | (set (match_dup 3) (match_dup 5))] | |
9db1d521 | 2550 | { |
609e7e80 AK |
2551 | operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); |
2552 | operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); | |
2553 | operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
2554 | operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
dc65c307 UW |
2555 | }) |
2556 | ||
2557 | (define_split | |
609e7e80 AK |
2558 | [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") |
2559 | (match_operand:DD_DF 1 "general_operand" ""))] | |
9602b6a1 | 2560 | "!TARGET_ZARCH && reload_completed |
9d605427 AK |
2561 | && !s_operand (operands[0], <MODE>mode) |
2562 | && !s_operand (operands[1], <MODE>mode) | |
609e7e80 | 2563 | && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" |
dc65c307 UW |
2564 | [(set (match_dup 2) (match_dup 4)) |
2565 | (set (match_dup 3) (match_dup 5))] | |
2566 | { | |
609e7e80 AK |
2567 | operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); |
2568 | operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); | |
2569 | operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); | |
2570 | operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); | |
dc65c307 | 2571 | }) |
9db1d521 | 2572 | |
4023fb28 | 2573 | (define_split |
609e7e80 AK |
2574 | [(set (match_operand:DD_DF 0 "register_operand" "") |
2575 | (match_operand:DD_DF 1 "memory_operand" ""))] | |
9602b6a1 | 2576 | "!TARGET_ZARCH && reload_completed |
8e509cf9 | 2577 | && !FP_REG_P (operands[0]) |
4023fb28 | 2578 | && !s_operand (operands[1], VOIDmode)" |
a41c6c53 | 2579 | [(set (match_dup 0) (match_dup 1))] |
a41c6c53 | 2580 | { |
609e7e80 | 2581 | rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); |
a41c6c53 UW |
2582 | s390_load_address (addr, XEXP (operands[1], 0)); |
2583 | operands[1] = replace_equiv_address (operands[1], addr); | |
dc65c307 UW |
2584 | }) |
2585 | ||
9db1d521 | 2586 | ; |
609e7e80 | 2587 | ; mov(sf|sd) instruction pattern(s). |
9db1d521 HP |
2588 | ; |
2589 | ||
609e7e80 AK |
2590 | (define_insn "mov<mode>" |
2591 | [(set (match_operand:SD_SF 0 "nonimmediate_operand" | |
3e4be43f | 2592 | "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,R") |
609e7e80 | 2593 | (match_operand:SD_SF 1 "general_operand" |
3e4be43f | 2594 | " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,R,v"))] |
4023fb28 | 2595 | "" |
9db1d521 | 2596 | "@ |
65b1d8ea | 2597 | lzer\t%0 |
ae1c6198 | 2598 | ldr\t%0,%1 |
d40c829f | 2599 | ler\t%0,%1 |
085261c8 | 2600 | lde\t%0,%1 |
d40c829f UW |
2601 | le\t%0,%1 |
2602 | ley\t%0,%1 | |
2603 | ste\t%1,%0 | |
2604 | stey\t%1,%0 | |
45e5214c | 2605 | lhi\t%0,0 |
d40c829f | 2606 | lr\t%0,%1 |
085261c8 | 2607 | lrl\t%0,%1 |
d40c829f UW |
2608 | l\t%0,%1 |
2609 | ly\t%0,%1 | |
085261c8 | 2610 | strl\t%1,%0 |
d40c829f | 2611 | st\t%1,%0 |
085261c8 AK |
2612 | sty\t%1,%0 |
2613 | vlr\t%v0,%v1 | |
298f4647 | 2614 | vleif\t%v0,0,0 |
085261c8 AK |
2615 | vlvgf\t%v0,%1,0 |
2616 | vlgvf\t%0,%v1,0 | |
298f4647 AK |
2617 | vlef\t%0,%1,0 |
2618 | vstef\t%1,%0,0" | |
ae1c6198 | 2619 | [(set_attr "op_type" "RRE,RR,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX") |
085261c8 AK |
2620 | (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>, |
2621 | fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store") | |
2622 | (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*") | |
285363a1 | 2623 | (set_attr "cpu_facility" "z196,vx,*,vx,*,longdisp,*,longdisp,*,*,z10,*,longdisp,z10,*,longdisp,vx,vx,vx,vx,vx,vx")]) |
4023fb28 | 2624 | |
9dc62c00 AK |
2625 | ; |
2626 | ; movcc instruction pattern | |
2627 | ; | |
2628 | ||
2629 | (define_insn "movcc" | |
2630 | [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") | |
5a3fe9b6 | 2631 | (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))] |
9dc62c00 AK |
2632 | "" |
2633 | "@ | |
2634 | lr\t%0,%1 | |
2635 | tmh\t%1,12288 | |
2636 | ipm\t%0 | |
a71f0749 DV |
2637 | l\t%0,%1 |
2638 | ly\t%0,%1 | |
2639 | st\t%1,%0 | |
2640 | sty\t%1,%0" | |
8dd3b235 | 2641 | [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") |
a71f0749 | 2642 | (set_attr "type" "lr,*,*,load,load,store,store") |
3e4be43f | 2643 | (set_attr "cpu_facility" "*,*,*,*,longdisp,*,longdisp") |
a71f0749 | 2644 | (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") |
65b1d8ea | 2645 | (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) |
9dc62c00 | 2646 | |
19b63d8e UW |
2647 | ; |
2648 | ; Block move (MVC) patterns. | |
2649 | ; | |
2650 | ||
2651 | (define_insn "*mvc" | |
2652 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
2653 | (match_operand:BLK 1 "memory_operand" "Q")) | |
2654 | (use (match_operand 2 "const_int_operand" "n"))] | |
2655 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" | |
fc0ea003 | 2656 | "mvc\t%O0(%2,%R0),%S1" |
b628bd8e | 2657 | [(set_attr "op_type" "SS")]) |
19b63d8e | 2658 | |
0a88561f AK |
2659 | ; This splitter converts a QI to QI mode copy into a BLK mode copy in |
2660 | ; order to have it implemented with mvc. | |
2661 | ||
2662 | (define_split | |
2663 | [(set (match_operand:QI 0 "memory_operand" "") | |
2664 | (match_operand:QI 1 "memory_operand" ""))] | |
2665 | "reload_completed" | |
2666 | [(parallel | |
2667 | [(set (match_dup 0) (match_dup 1)) | |
2668 | (use (const_int 1))])] | |
2669 | { | |
2670 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
2671 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
2672 | }) | |
2673 | ||
2674 | ||
19b63d8e UW |
2675 | (define_peephole2 |
2676 | [(parallel | |
2677 | [(set (match_operand:BLK 0 "memory_operand" "") | |
2678 | (match_operand:BLK 1 "memory_operand" "")) | |
2679 | (use (match_operand 2 "const_int_operand" ""))]) | |
2680 | (parallel | |
2681 | [(set (match_operand:BLK 3 "memory_operand" "") | |
2682 | (match_operand:BLK 4 "memory_operand" "")) | |
2683 | (use (match_operand 5 "const_int_operand" ""))])] | |
2684 | "s390_offset_p (operands[0], operands[3], operands[2]) | |
2685 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 2686 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 2687 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
2688 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
2689 | [(parallel | |
2690 | [(set (match_dup 6) (match_dup 7)) | |
2691 | (use (match_dup 8))])] | |
2692 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); | |
2693 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
2694 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
2695 | ||
2696 | ||
9db1d521 HP |
2697 | ; |
2698 | ; load_multiple pattern(s). | |
2699 | ; | |
22ea6b4f UW |
2700 | ; ??? Due to reload problems with replacing registers inside match_parallel |
2701 | ; we currently support load_multiple/store_multiple only after reload. | |
2702 | ; | |
9db1d521 HP |
2703 | |
2704 | (define_expand "load_multiple" | |
2705 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2706 | (match_operand 1 "" "")) | |
2707 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2708 | "reload_completed" |
9db1d521 | 2709 | { |
ef4bddc2 | 2710 | machine_mode mode; |
9db1d521 HP |
2711 | int regno; |
2712 | int count; | |
2713 | rtx from; | |
4023fb28 | 2714 | int i, off; |
9db1d521 HP |
2715 | |
2716 | /* Support only loading a constant number of fixed-point registers from | |
2717 | memory and only bother with this if more than two */ | |
2718 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2719 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2720 | || INTVAL (operands[2]) > 16 |
2721 | || GET_CODE (operands[1]) != MEM | |
2722 | || GET_CODE (operands[0]) != REG | |
2723 | || REGNO (operands[0]) >= 16) | |
2724 | FAIL; | |
2725 | ||
2726 | count = INTVAL (operands[2]); | |
2727 | regno = REGNO (operands[0]); | |
c19ec8f9 | 2728 | mode = GET_MODE (operands[0]); |
9602b6a1 | 2729 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2730 | FAIL; |
9db1d521 HP |
2731 | |
2732 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
b3a13419 | 2733 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2734 | { |
2735 | if (GET_CODE (XEXP (operands[1], 0)) == REG) | |
2736 | { | |
2737 | from = XEXP (operands[1], 0); | |
2738 | off = 0; | |
2739 | } | |
2740 | else if (GET_CODE (XEXP (operands[1], 0)) == PLUS | |
2741 | && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG | |
2742 | && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) | |
2743 | { | |
2744 | from = XEXP (XEXP (operands[1], 0), 0); | |
2745 | off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); | |
2746 | } | |
2747 | else | |
2748 | FAIL; | |
4023fb28 UW |
2749 | } |
2750 | else | |
2751 | { | |
2752 | from = force_reg (Pmode, XEXP (operands[1], 0)); | |
2753 | off = 0; | |
2754 | } | |
9db1d521 HP |
2755 | |
2756 | for (i = 0; i < count; i++) | |
2757 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2758 | = gen_rtx_SET (gen_rtx_REG (mode, regno + i), |
c19ec8f9 | 2759 | change_address (operands[1], mode, |
0a81f074 RS |
2760 | plus_constant (Pmode, from, |
2761 | off + i * GET_MODE_SIZE (mode)))); | |
10bbf137 | 2762 | }) |
9db1d521 HP |
2763 | |
2764 | (define_insn "*load_multiple_di" | |
2765 | [(match_parallel 0 "load_multiple_operation" | |
2766 | [(set (match_operand:DI 1 "register_operand" "=r") | |
3e4be43f | 2767 | (match_operand:DI 2 "s_operand" "S"))])] |
9602b6a1 | 2768 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2769 | { |
2770 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2771 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2772 | return "lmg\t%1,%0,%S2"; |
10bbf137 | 2773 | } |
d3632d41 | 2774 | [(set_attr "op_type" "RSY") |
4023fb28 | 2775 | (set_attr "type" "lm")]) |
9db1d521 HP |
2776 | |
2777 | (define_insn "*load_multiple_si" | |
2778 | [(match_parallel 0 "load_multiple_operation" | |
d3632d41 UW |
2779 | [(set (match_operand:SI 1 "register_operand" "=r,r") |
2780 | (match_operand:SI 2 "s_operand" "Q,S"))])] | |
22ea6b4f | 2781 | "reload_completed" |
9db1d521 HP |
2782 | { |
2783 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2784 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); |
fc0ea003 | 2785 | return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; |
10bbf137 | 2786 | } |
d3632d41 | 2787 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2788 | (set_attr "cpu_facility" "*,longdisp") |
4023fb28 | 2789 | (set_attr "type" "lm")]) |
9db1d521 HP |
2790 | |
2791 | ; | |
c7453384 | 2792 | ; store multiple pattern(s). |
9db1d521 HP |
2793 | ; |
2794 | ||
2795 | (define_expand "store_multiple" | |
2796 | [(match_par_dup 3 [(set (match_operand 0 "" "") | |
2797 | (match_operand 1 "" "")) | |
2798 | (use (match_operand 2 "" ""))])] | |
22ea6b4f | 2799 | "reload_completed" |
9db1d521 | 2800 | { |
ef4bddc2 | 2801 | machine_mode mode; |
9db1d521 HP |
2802 | int regno; |
2803 | int count; | |
2804 | rtx to; | |
4023fb28 | 2805 | int i, off; |
9db1d521 HP |
2806 | |
2807 | /* Support only storing a constant number of fixed-point registers to | |
2808 | memory and only bother with this if more than two. */ | |
2809 | if (GET_CODE (operands[2]) != CONST_INT | |
4023fb28 | 2810 | || INTVAL (operands[2]) < 2 |
9db1d521 HP |
2811 | || INTVAL (operands[2]) > 16 |
2812 | || GET_CODE (operands[0]) != MEM | |
2813 | || GET_CODE (operands[1]) != REG | |
2814 | || REGNO (operands[1]) >= 16) | |
2815 | FAIL; | |
2816 | ||
2817 | count = INTVAL (operands[2]); | |
2818 | regno = REGNO (operands[1]); | |
c19ec8f9 | 2819 | mode = GET_MODE (operands[1]); |
9602b6a1 | 2820 | if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) |
c19ec8f9 | 2821 | FAIL; |
9db1d521 HP |
2822 | |
2823 | operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); | |
4023fb28 | 2824 | |
b3a13419 | 2825 | if (!can_create_pseudo_p ()) |
4023fb28 UW |
2826 | { |
2827 | if (GET_CODE (XEXP (operands[0], 0)) == REG) | |
2828 | { | |
2829 | to = XEXP (operands[0], 0); | |
2830 | off = 0; | |
2831 | } | |
2832 | else if (GET_CODE (XEXP (operands[0], 0)) == PLUS | |
2833 | && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG | |
2834 | && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) | |
2835 | { | |
2836 | to = XEXP (XEXP (operands[0], 0), 0); | |
2837 | off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); | |
2838 | } | |
2839 | else | |
2840 | FAIL; | |
4023fb28 | 2841 | } |
c7453384 | 2842 | else |
4023fb28 UW |
2843 | { |
2844 | to = force_reg (Pmode, XEXP (operands[0], 0)); | |
2845 | off = 0; | |
2846 | } | |
9db1d521 HP |
2847 | |
2848 | for (i = 0; i < count; i++) | |
2849 | XVECEXP (operands[3], 0, i) | |
f7df4a84 | 2850 | = gen_rtx_SET (change_address (operands[0], mode, |
0a81f074 RS |
2851 | plus_constant (Pmode, to, |
2852 | off + i * GET_MODE_SIZE (mode))), | |
c19ec8f9 | 2853 | gen_rtx_REG (mode, regno + i)); |
10bbf137 | 2854 | }) |
9db1d521 HP |
2855 | |
2856 | (define_insn "*store_multiple_di" | |
2857 | [(match_parallel 0 "store_multiple_operation" | |
3e4be43f | 2858 | [(set (match_operand:DI 1 "s_operand" "=S") |
9db1d521 | 2859 | (match_operand:DI 2 "register_operand" "r"))])] |
9602b6a1 | 2860 | "reload_completed && TARGET_ZARCH" |
9db1d521 HP |
2861 | { |
2862 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2863 | operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2864 | return "stmg\t%2,%0,%S1"; |
10bbf137 | 2865 | } |
d3632d41 | 2866 | [(set_attr "op_type" "RSY") |
4023fb28 | 2867 | (set_attr "type" "stm")]) |
9db1d521 HP |
2868 | |
2869 | ||
2870 | (define_insn "*store_multiple_si" | |
2871 | [(match_parallel 0 "store_multiple_operation" | |
d3632d41 UW |
2872 | [(set (match_operand:SI 1 "s_operand" "=Q,S") |
2873 | (match_operand:SI 2 "register_operand" "r,r"))])] | |
22ea6b4f | 2874 | "reload_completed" |
9db1d521 HP |
2875 | { |
2876 | int words = XVECLEN (operands[0], 0); | |
9db1d521 | 2877 | operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); |
fc0ea003 | 2878 | return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; |
10bbf137 | 2879 | } |
d3632d41 | 2880 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 2881 | (set_attr "cpu_facility" "*,longdisp") |
4023fb28 | 2882 | (set_attr "type" "stm")]) |
9db1d521 HP |
2883 | |
2884 | ;; | |
2885 | ;; String instructions. | |
2886 | ;; | |
2887 | ||
963fc8d0 | 2888 | (define_insn "*execute_rl" |
2771c2f9 | 2889 | [(match_parallel 0 "execute_operation" |
963fc8d0 AK |
2890 | [(unspec [(match_operand 1 "register_operand" "a") |
2891 | (match_operand 2 "" "") | |
2892 | (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] | |
2893 | "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2894 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2895 | "exrl\t%1,%3" | |
2896 | [(set_attr "op_type" "RIL") | |
2897 | (set_attr "type" "cs")]) | |
2898 | ||
9bb86f41 | 2899 | (define_insn "*execute" |
2771c2f9 | 2900 | [(match_parallel 0 "execute_operation" |
9bb86f41 UW |
2901 | [(unspec [(match_operand 1 "register_operand" "a") |
2902 | (match_operand:BLK 2 "memory_operand" "R") | |
2903 | (match_operand 3 "" "")] UNSPEC_EXECUTE)])] | |
2904 | "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT | |
2905 | && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" | |
2906 | "ex\t%1,%2" | |
29a74354 UW |
2907 | [(set_attr "op_type" "RX") |
2908 | (set_attr "type" "cs")]) | |
9bb86f41 UW |
2909 | |
2910 | ||
91d39d71 UW |
2911 | ; |
2912 | ; strlenM instruction pattern(s). | |
2913 | ; | |
2914 | ||
9db2f16d | 2915 | (define_expand "strlen<mode>" |
085261c8 AK |
2916 | [(match_operand:P 0 "register_operand" "") ; result |
2917 | (match_operand:BLK 1 "memory_operand" "") ; input string | |
2918 | (match_operand:SI 2 "immediate_operand" "") ; search character | |
2919 | (match_operand:SI 3 "immediate_operand" "")] ; known alignment | |
2920 | "" | |
2921 | { | |
2922 | if (!TARGET_VX || operands[2] != const0_rtx) | |
2923 | emit_insn (gen_strlen_srst<mode> (operands[0], operands[1], | |
2924 | operands[2], operands[3])); | |
2925 | else | |
2926 | s390_expand_vec_strlen (operands[0], operands[1], operands[3]); | |
2927 | ||
2928 | DONE; | |
2929 | }) | |
2930 | ||
2931 | (define_expand "strlen_srst<mode>" | |
ccbdc0d4 | 2932 | [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) |
2f7e5a0d | 2933 | (parallel |
91d39d71 | 2934 | [(set (match_dup 4) |
9db2f16d | 2935 | (unspec:P [(const_int 0) |
91d39d71 | 2936 | (match_operand:BLK 1 "memory_operand" "") |
ccbdc0d4 | 2937 | (reg:SI 0) |
91d39d71 | 2938 | (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2939 | (clobber (scratch:P)) |
ae156f85 | 2940 | (clobber (reg:CC CC_REGNUM))]) |
91d39d71 | 2941 | (parallel |
9db2f16d AS |
2942 | [(set (match_operand:P 0 "register_operand" "") |
2943 | (minus:P (match_dup 4) (match_dup 5))) | |
ae156f85 | 2944 | (clobber (reg:CC CC_REGNUM))])] |
9db2f16d | 2945 | "" |
91d39d71 | 2946 | { |
9db2f16d AS |
2947 | operands[4] = gen_reg_rtx (Pmode); |
2948 | operands[5] = gen_reg_rtx (Pmode); | |
91d39d71 UW |
2949 | emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); |
2950 | operands[1] = replace_equiv_address (operands[1], operands[5]); | |
2951 | }) | |
2952 | ||
9db2f16d AS |
2953 | (define_insn "*strlen<mode>" |
2954 | [(set (match_operand:P 0 "register_operand" "=a") | |
2955 | (unspec:P [(match_operand:P 2 "general_operand" "0") | |
2956 | (mem:BLK (match_operand:P 3 "register_operand" "1")) | |
ccbdc0d4 | 2957 | (reg:SI 0) |
91d39d71 | 2958 | (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) |
9db2f16d | 2959 | (clobber (match_scratch:P 1 "=a")) |
ae156f85 | 2960 | (clobber (reg:CC CC_REGNUM))] |
9db2f16d | 2961 | "" |
91d39d71 | 2962 | "srst\t%0,%1\;jo\t.-4" |
b628bd8e UW |
2963 | [(set_attr "length" "8") |
2964 | (set_attr "type" "vs")]) | |
91d39d71 | 2965 | |
ccbdc0d4 AS |
2966 | ; |
2967 | ; cmpstrM instruction pattern(s). | |
2968 | ; | |
2969 | ||
2970 | (define_expand "cmpstrsi" | |
2971 | [(set (reg:SI 0) (const_int 0)) | |
2972 | (parallel | |
2973 | [(clobber (match_operand 3 "" "")) | |
2974 | (clobber (match_dup 4)) | |
2975 | (set (reg:CCU CC_REGNUM) | |
2976 | (compare:CCU (match_operand:BLK 1 "memory_operand" "") | |
2977 | (match_operand:BLK 2 "memory_operand" ""))) | |
2978 | (use (reg:SI 0))]) | |
2979 | (parallel | |
2980 | [(set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 2981 | (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT)) |
ccbdc0d4 AS |
2982 | (clobber (reg:CC CC_REGNUM))])] |
2983 | "" | |
2984 | { | |
2985 | /* As the result of CMPINT is inverted compared to what we need, | |
2986 | we have to swap the operands. */ | |
2987 | rtx op1 = operands[2]; | |
2988 | rtx op2 = operands[1]; | |
2989 | rtx addr1 = gen_reg_rtx (Pmode); | |
2990 | rtx addr2 = gen_reg_rtx (Pmode); | |
2991 | ||
2992 | emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); | |
2993 | emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); | |
2994 | operands[1] = replace_equiv_address_nv (op1, addr1); | |
2995 | operands[2] = replace_equiv_address_nv (op2, addr2); | |
2996 | operands[3] = addr1; | |
2997 | operands[4] = addr2; | |
2998 | }) | |
2999 | ||
3000 | (define_insn "*cmpstr<mode>" | |
3001 | [(clobber (match_operand:P 0 "register_operand" "=d")) | |
3002 | (clobber (match_operand:P 1 "register_operand" "=d")) | |
3003 | (set (reg:CCU CC_REGNUM) | |
3004 | (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) | |
3005 | (mem:BLK (match_operand:P 3 "register_operand" "1")))) | |
3006 | (use (reg:SI 0))] | |
3007 | "" | |
3008 | "clst\t%0,%1\;jo\t.-4" | |
3009 | [(set_attr "length" "8") | |
3010 | (set_attr "type" "vs")]) | |
9381e3f1 | 3011 | |
742090fc AS |
3012 | ; |
3013 | ; movstr instruction pattern. | |
3014 | ; | |
3015 | ||
3016 | (define_expand "movstr" | |
4a7dec25 DV |
3017 | [(match_operand 0 "register_operand" "") |
3018 | (match_operand 1 "memory_operand" "") | |
3019 | (match_operand 2 "memory_operand" "")] | |
3020 | "" | |
3021 | { | |
3022 | if (TARGET_64BIT) | |
3023 | emit_insn (gen_movstrdi (operands[0], operands[1], operands[2])); | |
3024 | else | |
3025 | emit_insn (gen_movstrsi (operands[0], operands[1], operands[2])); | |
3026 | DONE; | |
3027 | }) | |
3028 | ||
3029 | (define_expand "movstr<P:mode>" | |
742090fc | 3030 | [(set (reg:SI 0) (const_int 0)) |
9381e3f1 | 3031 | (parallel |
742090fc AS |
3032 | [(clobber (match_dup 3)) |
3033 | (set (match_operand:BLK 1 "memory_operand" "") | |
3034 | (match_operand:BLK 2 "memory_operand" "")) | |
4a7dec25 DV |
3035 | (set (match_operand:P 0 "register_operand" "") |
3036 | (unspec:P [(match_dup 1) | |
742090fc AS |
3037 | (match_dup 2) |
3038 | (reg:SI 0)] UNSPEC_MVST)) | |
3039 | (clobber (reg:CC CC_REGNUM))])] | |
3040 | "" | |
3041 | { | |
859a4c0e AK |
3042 | rtx addr1, addr2; |
3043 | ||
3044 | if (TARGET_VX && optimize_function_for_speed_p (cfun)) | |
3045 | { | |
3046 | s390_expand_vec_movstr (operands[0], operands[1], operands[2]); | |
3047 | DONE; | |
3048 | } | |
3049 | ||
3050 | addr1 = gen_reg_rtx (Pmode); | |
3051 | addr2 = gen_reg_rtx (Pmode); | |
742090fc AS |
3052 | |
3053 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); | |
3054 | emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); | |
3055 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3056 | operands[2] = replace_equiv_address_nv (operands[2], addr2); | |
3057 | operands[3] = addr2; | |
3058 | }) | |
3059 | ||
3060 | (define_insn "*movstr" | |
3061 | [(clobber (match_operand:P 2 "register_operand" "=d")) | |
3062 | (set (mem:BLK (match_operand:P 1 "register_operand" "0")) | |
3063 | (mem:BLK (match_operand:P 3 "register_operand" "2"))) | |
3064 | (set (match_operand:P 0 "register_operand" "=d") | |
4a7dec25 | 3065 | (unspec:P [(mem:BLK (match_dup 1)) |
742090fc AS |
3066 | (mem:BLK (match_dup 3)) |
3067 | (reg:SI 0)] UNSPEC_MVST)) | |
3068 | (clobber (reg:CC CC_REGNUM))] | |
3069 | "" | |
3070 | "mvst\t%1,%2\;jo\t.-4" | |
3071 | [(set_attr "length" "8") | |
3072 | (set_attr "type" "vs")]) | |
9381e3f1 | 3073 | |
742090fc | 3074 | |
9db1d521 | 3075 | ; |
70128ad9 | 3076 | ; movmemM instruction pattern(s). |
9db1d521 HP |
3077 | ; |
3078 | ||
9db2f16d | 3079 | (define_expand "movmem<mode>" |
963fc8d0 AK |
3080 | [(set (match_operand:BLK 0 "memory_operand" "") ; destination |
3081 | (match_operand:BLK 1 "memory_operand" "")) ; source | |
3082 | (use (match_operand:GPR 2 "general_operand" "")) ; count | |
a41c6c53 UW |
3083 | (match_operand 3 "" "")] |
3084 | "" | |
367d32f3 AK |
3085 | { |
3086 | if (s390_expand_movmem (operands[0], operands[1], operands[2])) | |
3087 | DONE; | |
3088 | else | |
3089 | FAIL; | |
3090 | }) | |
9db1d521 | 3091 | |
ecbe845e UW |
3092 | ; Move a block that is up to 256 bytes in length. |
3093 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3094 | |
70128ad9 | 3095 | (define_expand "movmem_short" |
b9404c99 UW |
3096 | [(parallel |
3097 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3098 | (match_operand:BLK 1 "memory_operand" "")) | |
3099 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3100 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3101 | (clobber (match_dup 3))])] |
3102 | "" | |
3103 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
ecbe845e | 3104 | |
70128ad9 | 3105 | (define_insn "*movmem_short" |
963fc8d0 AK |
3106 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
3107 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) | |
3108 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3109 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3110 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3111 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3112 | "#" |
963fc8d0 | 3113 | [(set_attr "type" "cs") |
b5e0425c | 3114 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
ecbe845e | 3115 | |
9bb86f41 UW |
3116 | (define_split |
3117 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3118 | (match_operand:BLK 1 "memory_operand" "")) | |
3119 | (use (match_operand 2 "const_int_operand" "")) | |
3120 | (use (match_operand 3 "immediate_operand" "")) | |
3121 | (clobber (scratch))] | |
3122 | "reload_completed" | |
3123 | [(parallel | |
3124 | [(set (match_dup 0) (match_dup 1)) | |
3125 | (use (match_dup 2))])] | |
3126 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3127 | |
9bb86f41 UW |
3128 | (define_split |
3129 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3130 | (match_operand:BLK 1 "memory_operand" "")) | |
3131 | (use (match_operand 2 "register_operand" "")) | |
3132 | (use (match_operand 3 "memory_operand" "")) | |
3133 | (clobber (scratch))] | |
3134 | "reload_completed" | |
3135 | [(parallel | |
3136 | [(unspec [(match_dup 2) (match_dup 3) | |
3137 | (const_int 0)] UNSPEC_EXECUTE) | |
3138 | (set (match_dup 0) (match_dup 1)) | |
3139 | (use (const_int 1))])] | |
3140 | "") | |
3141 | ||
963fc8d0 AK |
3142 | (define_split |
3143 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3144 | (match_operand:BLK 1 "memory_operand" "")) | |
3145 | (use (match_operand 2 "register_operand" "")) | |
3146 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3147 | (clobber (scratch))] | |
3148 | "TARGET_Z10 && reload_completed" | |
3149 | [(parallel | |
3150 | [(unspec [(match_dup 2) (const_int 0) | |
3151 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3152 | (set (match_dup 0) (match_dup 1)) | |
3153 | (use (const_int 1))])] | |
3154 | "operands[3] = gen_label_rtx ();") | |
3155 | ||
9bb86f41 UW |
3156 | (define_split |
3157 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3158 | (match_operand:BLK 1 "memory_operand" "")) | |
3159 | (use (match_operand 2 "register_operand" "")) | |
3160 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3161 | (clobber (match_operand 3 "register_operand" ""))] | |
3162 | "reload_completed && TARGET_CPU_ZARCH" | |
3163 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3164 | (parallel | |
9381e3f1 | 3165 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 UW |
3166 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
3167 | (set (match_dup 0) (match_dup 1)) | |
3168 | (use (const_int 1))])] | |
3169 | "operands[4] = gen_label_rtx ();") | |
3170 | ||
a41c6c53 | 3171 | ; Move a block of arbitrary length. |
9db1d521 | 3172 | |
70128ad9 | 3173 | (define_expand "movmem_long" |
b9404c99 UW |
3174 | [(parallel |
3175 | [(clobber (match_dup 2)) | |
3176 | (clobber (match_dup 3)) | |
3177 | (set (match_operand:BLK 0 "memory_operand" "") | |
3178 | (match_operand:BLK 1 "memory_operand" "")) | |
3179 | (use (match_operand 2 "general_operand" "")) | |
3180 | (use (match_dup 3)) | |
ae156f85 | 3181 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3182 | "" |
3183 | { | |
ef4bddc2 RS |
3184 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3185 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3186 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3187 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3188 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3189 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3190 | rtx len0 = gen_lowpart (Pmode, reg0); |
3191 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3192 | ||
c41c1387 | 3193 | emit_clobber (reg0); |
b9404c99 UW |
3194 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3195 | emit_move_insn (len0, operands[2]); | |
3196 | ||
c41c1387 | 3197 | emit_clobber (reg1); |
b9404c99 UW |
3198 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3199 | emit_move_insn (len1, operands[2]); | |
3200 | ||
3201 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3202 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3203 | operands[2] = reg0; | |
3204 | operands[3] = reg1; | |
3205 | }) | |
3206 | ||
a1aed706 AS |
3207 | (define_insn "*movmem_long" |
3208 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3209 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
3210 | (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) | |
3211 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) | |
b9404c99 UW |
3212 | (use (match_dup 2)) |
3213 | (use (match_dup 3)) | |
ae156f85 | 3214 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 AK |
3215 | "TARGET_64BIT || !TARGET_ZARCH" |
3216 | "mvcle\t%0,%1,0\;jo\t.-4" | |
3217 | [(set_attr "length" "8") | |
3218 | (set_attr "type" "vs")]) | |
3219 | ||
3220 | (define_insn "*movmem_long_31z" | |
3221 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3222 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3223 | (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3224 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) | |
3225 | (use (match_dup 2)) | |
3226 | (use (match_dup 3)) | |
3227 | (clobber (reg:CC CC_REGNUM))] | |
3228 | "!TARGET_64BIT && TARGET_ZARCH" | |
d40c829f | 3229 | "mvcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3230 | [(set_attr "length" "8") |
3231 | (set_attr "type" "vs")]) | |
9db1d521 | 3232 | |
638e37c2 WG |
3233 | |
3234 | ; | |
3235 | ; Test data class. | |
3236 | ; | |
3237 | ||
0f67fa83 WG |
3238 | (define_expand "signbit<mode>2" |
3239 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3240 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3241 | (match_dup 2)] | |
0f67fa83 WG |
3242 | UNSPEC_TDC_INSN)) |
3243 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3244 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
0f67fa83 WG |
3245 | "TARGET_HARD_FLOAT" |
3246 | { | |
3247 | operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); | |
3248 | }) | |
3249 | ||
638e37c2 WG |
3250 | (define_expand "isinf<mode>2" |
3251 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 WG |
3252 | (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") |
3253 | (match_dup 2)] | |
638e37c2 WG |
3254 | UNSPEC_TDC_INSN)) |
3255 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3256 | (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] |
142cd70f | 3257 | "TARGET_HARD_FLOAT" |
638e37c2 WG |
3258 | { |
3259 | operands[2] = GEN_INT (S390_TDC_INFINITY); | |
3260 | }) | |
3261 | ||
085261c8 AK |
3262 | ; This extracts CC into a GPR properly shifted. The actual IPM |
3263 | ; instruction will be issued by reload. The constraint of operand 1 | |
3264 | ; forces reload to use a GPR. So reload will issue a movcc insn for | |
3265 | ; copying CC into a GPR first. | |
5a3fe9b6 | 3266 | (define_insn_and_split "*cc_to_int" |
085261c8 | 3267 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d") |
5a3fe9b6 AK |
3268 | (unspec:SI [(match_operand 1 "register_operand" "0")] |
3269 | UNSPEC_CC_TO_INT))] | |
3270 | "operands != NULL" | |
3271 | "#" | |
3272 | "reload_completed" | |
3273 | [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) | |
3274 | ||
638e37c2 WG |
3275 | ; This insn is used to generate all variants of the Test Data Class |
3276 | ; instruction, namely tcxb, tcdb, and tceb. The insn's first operand | |
3277 | ; is the register to be tested and the second one is the bit mask | |
9381e3f1 | 3278 | ; specifying the required test(s). |
638e37c2 | 3279 | ; |
be5de7a1 | 3280 | ; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet |
638e37c2 WG |
3281 | (define_insn "*TDC_insn_<mode>" |
3282 | [(set (reg:CCZ CC_REGNUM) | |
9381e3f1 | 3283 | (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") |
638e37c2 | 3284 | (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] |
142cd70f | 3285 | "TARGET_HARD_FLOAT" |
0387c142 | 3286 | "t<_d>c<xde><bt>\t%0,%1" |
638e37c2 | 3287 | [(set_attr "op_type" "RXE") |
9381e3f1 | 3288 | (set_attr "type" "fsimp<mode>")]) |
638e37c2 | 3289 | |
638e37c2 WG |
3290 | |
3291 | ||
9db1d521 | 3292 | ; |
57e84f18 | 3293 | ; setmemM instruction pattern(s). |
9db1d521 HP |
3294 | ; |
3295 | ||
57e84f18 | 3296 | (define_expand "setmem<mode>" |
a41c6c53 | 3297 | [(set (match_operand:BLK 0 "memory_operand" "") |
6d057022 | 3298 | (match_operand:QI 2 "general_operand" "")) |
9db2f16d | 3299 | (use (match_operand:GPR 1 "general_operand" "")) |
57e84f18 | 3300 | (match_operand 3 "" "")] |
a41c6c53 | 3301 | "" |
6d057022 | 3302 | "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") |
9db1d521 | 3303 | |
a41c6c53 | 3304 | ; Clear a block that is up to 256 bytes in length. |
b9404c99 UW |
3305 | ; The block length is taken as (operands[1] % 256) + 1. |
3306 | ||
70128ad9 | 3307 | (define_expand "clrmem_short" |
b9404c99 UW |
3308 | [(parallel |
3309 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3310 | (const_int 0)) | |
3311 | (use (match_operand 1 "nonmemory_operand" "")) | |
9bb86f41 | 3312 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 | 3313 | (clobber (match_dup 2)) |
ae156f85 | 3314 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 UW |
3315 | "" |
3316 | "operands[2] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3317 | |
70128ad9 | 3318 | (define_insn "*clrmem_short" |
963fc8d0 | 3319 | [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") |
a41c6c53 | 3320 | (const_int 0)) |
963fc8d0 AK |
3321 | (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) |
3322 | (use (match_operand 2 "immediate_operand" "X,R,X,X")) | |
1eae36f0 | 3323 | (clobber (match_scratch:P 3 "=X,X,X,&a")) |
ae156f85 | 3324 | (clobber (reg:CC CC_REGNUM))] |
1eae36f0 | 3325 | "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" |
9bb86f41 | 3326 | "#" |
963fc8d0 | 3327 | [(set_attr "type" "cs") |
b5e0425c | 3328 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9bb86f41 UW |
3329 | |
3330 | (define_split | |
3331 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3332 | (const_int 0)) | |
3333 | (use (match_operand 1 "const_int_operand" "")) | |
3334 | (use (match_operand 2 "immediate_operand" "")) | |
3335 | (clobber (scratch)) | |
ae156f85 | 3336 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3337 | "reload_completed" |
3338 | [(parallel | |
3339 | [(set (match_dup 0) (const_int 0)) | |
3340 | (use (match_dup 1)) | |
ae156f85 | 3341 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3342 | "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") |
9db1d521 | 3343 | |
9bb86f41 UW |
3344 | (define_split |
3345 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3346 | (const_int 0)) | |
3347 | (use (match_operand 1 "register_operand" "")) | |
3348 | (use (match_operand 2 "memory_operand" "")) | |
3349 | (clobber (scratch)) | |
ae156f85 | 3350 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3351 | "reload_completed" |
3352 | [(parallel | |
3353 | [(unspec [(match_dup 1) (match_dup 2) | |
3354 | (const_int 0)] UNSPEC_EXECUTE) | |
3355 | (set (match_dup 0) (const_int 0)) | |
3356 | (use (const_int 1)) | |
ae156f85 | 3357 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 | 3358 | "") |
9db1d521 | 3359 | |
963fc8d0 AK |
3360 | (define_split |
3361 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3362 | (const_int 0)) | |
3363 | (use (match_operand 1 "register_operand" "")) | |
3364 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3365 | (clobber (scratch)) | |
3366 | (clobber (reg:CC CC_REGNUM))] | |
3367 | "TARGET_Z10 && reload_completed" | |
3368 | [(parallel | |
3369 | [(unspec [(match_dup 1) (const_int 0) | |
3370 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) | |
3371 | (set (match_dup 0) (const_int 0)) | |
3372 | (use (const_int 1)) | |
3373 | (clobber (reg:CC CC_REGNUM))])] | |
3374 | "operands[3] = gen_label_rtx ();") | |
3375 | ||
9bb86f41 UW |
3376 | (define_split |
3377 | [(set (match_operand:BLK 0 "memory_operand" "") | |
3378 | (const_int 0)) | |
3379 | (use (match_operand 1 "register_operand" "")) | |
3380 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3381 | (clobber (match_operand 2 "register_operand" "")) | |
ae156f85 | 3382 | (clobber (reg:CC CC_REGNUM))] |
9bb86f41 UW |
3383 | "reload_completed && TARGET_CPU_ZARCH" |
3384 | [(set (match_dup 2) (label_ref (match_dup 3))) | |
3385 | (parallel | |
9381e3f1 | 3386 | [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) |
9bb86f41 UW |
3387 | (label_ref (match_dup 3))] UNSPEC_EXECUTE) |
3388 | (set (match_dup 0) (const_int 0)) | |
3389 | (use (const_int 1)) | |
ae156f85 | 3390 | (clobber (reg:CC CC_REGNUM))])] |
9bb86f41 UW |
3391 | "operands[3] = gen_label_rtx ();") |
3392 | ||
9381e3f1 | 3393 | ; Initialize a block of arbitrary length with (operands[2] % 256). |
b9404c99 | 3394 | |
da0dcab1 | 3395 | (define_expand "setmem_long_<P:mode>" |
b9404c99 UW |
3396 | [(parallel |
3397 | [(clobber (match_dup 1)) | |
3398 | (set (match_operand:BLK 0 "memory_operand" "") | |
dd95128b | 3399 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "") |
da0dcab1 | 3400 | (match_dup 4)] UNSPEC_REPLICATE_BYTE)) |
6d057022 | 3401 | (use (match_dup 3)) |
ae156f85 | 3402 | (clobber (reg:CC CC_REGNUM))])] |
b9404c99 | 3403 | "" |
a41c6c53 | 3404 | { |
ef4bddc2 RS |
3405 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3406 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3407 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3408 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3409 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
b9404c99 | 3410 | rtx len0 = gen_lowpart (Pmode, reg0); |
9db1d521 | 3411 | |
c41c1387 | 3412 | emit_clobber (reg0); |
b9404c99 UW |
3413 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3414 | emit_move_insn (len0, operands[1]); | |
9db1d521 | 3415 | |
b9404c99 | 3416 | emit_move_insn (reg1, const0_rtx); |
a41c6c53 | 3417 | |
b9404c99 UW |
3418 | operands[0] = replace_equiv_address_nv (operands[0], addr0); |
3419 | operands[1] = reg0; | |
6d057022 | 3420 | operands[3] = reg1; |
da0dcab1 | 3421 | operands[4] = gen_lowpart (Pmode, operands[1]); |
b9404c99 | 3422 | }) |
a41c6c53 | 3423 | |
da0dcab1 DV |
3424 | ; Patterns for 31 bit + Esa and 64 bit + Zarch. |
3425 | ||
db340c73 | 3426 | (define_insn "*setmem_long" |
a1aed706 | 3427 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) |
6d057022 | 3428 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) |
dd95128b | 3429 | (unspec:BLK [(match_operand:P 2 "setmem_operand" "Y") |
da0dcab1 DV |
3430 | (subreg:P (match_dup 3) <modesize>)] |
3431 | UNSPEC_REPLICATE_BYTE)) | |
a1aed706 | 3432 | (use (match_operand:<DBL> 1 "register_operand" "d")) |
ae156f85 | 3433 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3434 | "TARGET_64BIT || !TARGET_ZARCH" |
6d057022 | 3435 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
b628bd8e UW |
3436 | [(set_attr "length" "8") |
3437 | (set_attr "type" "vs")]) | |
9db1d521 | 3438 | |
db340c73 AK |
3439 | (define_insn "*setmem_long_and" |
3440 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3441 | (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) | |
d876f5cd | 3442 | (unspec:BLK [(zero_extend:P (match_operand:QI 2 "setmem_operand" "Y")) |
db340c73 AK |
3443 | (subreg:P (match_dup 3) <modesize>)] |
3444 | UNSPEC_REPLICATE_BYTE)) | |
3445 | (use (match_operand:<DBL> 1 "register_operand" "d")) | |
3446 | (clobber (reg:CC CC_REGNUM))] | |
d876f5cd | 3447 | "(TARGET_64BIT || !TARGET_ZARCH)" |
db340c73 AK |
3448 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3449 | [(set_attr "length" "8") | |
3450 | (set_attr "type" "vs")]) | |
3451 | ||
da0dcab1 DV |
3452 | ; Variants for 31 bit + Zarch, necessary because of the odd in-register offsets |
3453 | ; of the SImode subregs. | |
3454 | ||
db340c73 | 3455 | (define_insn "*setmem_long_31z" |
9602b6a1 AK |
3456 | [(clobber (match_operand:TI 0 "register_operand" "=d")) |
3457 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
dd95128b | 3458 | (unspec:BLK [(match_operand:SI 2 "setmem_operand" "Y") |
da0dcab1 | 3459 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
9602b6a1 AK |
3460 | (use (match_operand:TI 1 "register_operand" "d")) |
3461 | (clobber (reg:CC CC_REGNUM))] | |
3462 | "!TARGET_64BIT && TARGET_ZARCH" | |
4989e88a AK |
3463 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3464 | [(set_attr "length" "8") | |
3465 | (set_attr "type" "vs")]) | |
9602b6a1 | 3466 | |
db340c73 AK |
3467 | (define_insn "*setmem_long_and_31z" |
3468 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3469 | (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) | |
d876f5cd | 3470 | (unspec:BLK [(zero_extend:SI (match_operand:QI 2 "setmem_operand" "Y")) |
db340c73 AK |
3471 | (subreg:SI (match_dup 3) 12)] UNSPEC_REPLICATE_BYTE)) |
3472 | (use (match_operand:TI 1 "register_operand" "d")) | |
3473 | (clobber (reg:CC CC_REGNUM))] | |
d876f5cd | 3474 | "(!TARGET_64BIT && TARGET_ZARCH)" |
db340c73 AK |
3475 | "mvcle\t%0,%1,%Y2\;jo\t.-4" |
3476 | [(set_attr "length" "8") | |
3477 | (set_attr "type" "vs")]) | |
3478 | ||
9db1d521 | 3479 | ; |
358b8f01 | 3480 | ; cmpmemM instruction pattern(s). |
9db1d521 HP |
3481 | ; |
3482 | ||
358b8f01 | 3483 | (define_expand "cmpmemsi" |
a41c6c53 UW |
3484 | [(set (match_operand:SI 0 "register_operand" "") |
3485 | (compare:SI (match_operand:BLK 1 "memory_operand" "") | |
3486 | (match_operand:BLK 2 "memory_operand" "") ) ) | |
3487 | (use (match_operand:SI 3 "general_operand" "")) | |
3488 | (use (match_operand:SI 4 "" ""))] | |
3489 | "" | |
367d32f3 AK |
3490 | { |
3491 | if (s390_expand_cmpmem (operands[0], operands[1], | |
3492 | operands[2], operands[3])) | |
3493 | DONE; | |
3494 | else | |
3495 | FAIL; | |
3496 | }) | |
9db1d521 | 3497 | |
a41c6c53 UW |
3498 | ; Compare a block that is up to 256 bytes in length. |
3499 | ; The block length is taken as (operands[2] % 256) + 1. | |
9db1d521 | 3500 | |
b9404c99 UW |
3501 | (define_expand "cmpmem_short" |
3502 | [(parallel | |
ae156f85 | 3503 | [(set (reg:CCU CC_REGNUM) |
5b022de5 | 3504 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3505 | (match_operand:BLK 1 "memory_operand" ""))) |
3506 | (use (match_operand 2 "nonmemory_operand" "")) | |
9bb86f41 | 3507 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) |
b9404c99 UW |
3508 | (clobber (match_dup 3))])] |
3509 | "" | |
3510 | "operands[3] = gen_rtx_SCRATCH (Pmode);") | |
9db1d521 | 3511 | |
b9404c99 | 3512 | (define_insn "*cmpmem_short" |
ae156f85 | 3513 | [(set (reg:CCU CC_REGNUM) |
963fc8d0 AK |
3514 | (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") |
3515 | (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) | |
3516 | (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) | |
3517 | (use (match_operand 3 "immediate_operand" "X,R,X,X")) | |
1eae36f0 AK |
3518 | (clobber (match_scratch:P 4 "=X,X,X,&a"))] |
3519 | "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" | |
9bb86f41 | 3520 | "#" |
963fc8d0 | 3521 | [(set_attr "type" "cs") |
b5e0425c | 3522 | (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) |
9db1d521 | 3523 | |
9bb86f41 | 3524 | (define_split |
ae156f85 | 3525 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3526 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3527 | (match_operand:BLK 1 "memory_operand" ""))) | |
3528 | (use (match_operand 2 "const_int_operand" "")) | |
3529 | (use (match_operand 3 "immediate_operand" "")) | |
3530 | (clobber (scratch))] | |
3531 | "reload_completed" | |
3532 | [(parallel | |
ae156f85 | 3533 | [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3534 | (use (match_dup 2))])] |
3535 | "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") | |
9db1d521 | 3536 | |
9bb86f41 | 3537 | (define_split |
ae156f85 | 3538 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3539 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3540 | (match_operand:BLK 1 "memory_operand" ""))) | |
3541 | (use (match_operand 2 "register_operand" "")) | |
3542 | (use (match_operand 3 "memory_operand" "")) | |
3543 | (clobber (scratch))] | |
3544 | "reload_completed" | |
3545 | [(parallel | |
3546 | [(unspec [(match_dup 2) (match_dup 3) | |
3547 | (const_int 0)] UNSPEC_EXECUTE) | |
ae156f85 | 3548 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3549 | (use (const_int 1))])] |
3550 | "") | |
3551 | ||
963fc8d0 AK |
3552 | (define_split |
3553 | [(set (reg:CCU CC_REGNUM) | |
3554 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") | |
3555 | (match_operand:BLK 1 "memory_operand" ""))) | |
3556 | (use (match_operand 2 "register_operand" "")) | |
3557 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3558 | (clobber (scratch))] | |
3559 | "TARGET_Z10 && reload_completed" | |
3560 | [(parallel | |
3561 | [(unspec [(match_dup 2) (const_int 0) | |
3562 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) | |
3563 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) | |
3564 | (use (const_int 1))])] | |
3565 | "operands[4] = gen_label_rtx ();") | |
3566 | ||
9bb86f41 | 3567 | (define_split |
ae156f85 | 3568 | [(set (reg:CCU CC_REGNUM) |
9bb86f41 UW |
3569 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
3570 | (match_operand:BLK 1 "memory_operand" ""))) | |
3571 | (use (match_operand 2 "register_operand" "")) | |
3572 | (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) | |
3573 | (clobber (match_operand 3 "register_operand" ""))] | |
3574 | "reload_completed && TARGET_CPU_ZARCH" | |
3575 | [(set (match_dup 3) (label_ref (match_dup 4))) | |
3576 | (parallel | |
9381e3f1 | 3577 | [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) |
9bb86f41 | 3578 | (label_ref (match_dup 4))] UNSPEC_EXECUTE) |
ae156f85 | 3579 | (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) |
9bb86f41 UW |
3580 | (use (const_int 1))])] |
3581 | "operands[4] = gen_label_rtx ();") | |
3582 | ||
a41c6c53 | 3583 | ; Compare a block of arbitrary length. |
9db1d521 | 3584 | |
b9404c99 UW |
3585 | (define_expand "cmpmem_long" |
3586 | [(parallel | |
3587 | [(clobber (match_dup 2)) | |
3588 | (clobber (match_dup 3)) | |
ae156f85 | 3589 | (set (reg:CCU CC_REGNUM) |
5b022de5 | 3590 | (compare:CCU (match_operand:BLK 0 "memory_operand" "") |
b9404c99 UW |
3591 | (match_operand:BLK 1 "memory_operand" ""))) |
3592 | (use (match_operand 2 "general_operand" "")) | |
3593 | (use (match_dup 3))])] | |
3594 | "" | |
3595 | { | |
ef4bddc2 RS |
3596 | machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; |
3597 | machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; | |
9602b6a1 AK |
3598 | rtx reg0 = gen_reg_rtx (dreg_mode); |
3599 | rtx reg1 = gen_reg_rtx (dreg_mode); | |
3600 | rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); | |
3601 | rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); | |
b9404c99 UW |
3602 | rtx len0 = gen_lowpart (Pmode, reg0); |
3603 | rtx len1 = gen_lowpart (Pmode, reg1); | |
3604 | ||
c41c1387 | 3605 | emit_clobber (reg0); |
b9404c99 UW |
3606 | emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); |
3607 | emit_move_insn (len0, operands[2]); | |
3608 | ||
c41c1387 | 3609 | emit_clobber (reg1); |
b9404c99 UW |
3610 | emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); |
3611 | emit_move_insn (len1, operands[2]); | |
3612 | ||
3613 | operands[0] = replace_equiv_address_nv (operands[0], addr0); | |
3614 | operands[1] = replace_equiv_address_nv (operands[1], addr1); | |
3615 | operands[2] = reg0; | |
3616 | operands[3] = reg1; | |
3617 | }) | |
3618 | ||
a1aed706 AS |
3619 | (define_insn "*cmpmem_long" |
3620 | [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) | |
3621 | (clobber (match_operand:<DBL> 1 "register_operand" "=d")) | |
ae156f85 | 3622 | (set (reg:CCU CC_REGNUM) |
a1aed706 AS |
3623 | (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) |
3624 | (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) | |
f8766020 HP |
3625 | (use (match_dup 2)) |
3626 | (use (match_dup 3))] | |
9602b6a1 | 3627 | "TARGET_64BIT || !TARGET_ZARCH" |
287ff198 | 3628 | "clcle\t%0,%1,0\;jo\t.-4" |
b628bd8e UW |
3629 | [(set_attr "length" "8") |
3630 | (set_attr "type" "vs")]) | |
9db1d521 | 3631 | |
9602b6a1 AK |
3632 | (define_insn "*cmpmem_long_31z" |
3633 | [(clobber (match_operand:TI 0 "register_operand" "=d")) | |
3634 | (clobber (match_operand:TI 1 "register_operand" "=d")) | |
3635 | (set (reg:CCU CC_REGNUM) | |
3636 | (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) | |
3637 | (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) | |
3638 | (use (match_dup 2)) | |
3639 | (use (match_dup 3))] | |
3640 | "!TARGET_64BIT && TARGET_ZARCH" | |
3641 | "clcle\t%0,%1,0\;jo\t.-4" | |
3642 | [(set_attr "op_type" "NN") | |
3643 | (set_attr "type" "vs") | |
3644 | (set_attr "length" "8")]) | |
3645 | ||
02887425 UW |
3646 | ; Convert CCUmode condition code to integer. |
3647 | ; Result is zero if EQ, positive if LTU, negative if GTU. | |
9db1d521 | 3648 | |
02887425 | 3649 | (define_insn_and_split "cmpint" |
9db1d521 | 3650 | [(set (match_operand:SI 0 "register_operand" "=d") |
02887425 | 3651 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3652 | UNSPEC_STRCMPCC_TO_INT)) |
ae156f85 | 3653 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 3654 | "" |
02887425 UW |
3655 | "#" |
3656 | "reload_completed" | |
3657 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3658 | (parallel | |
3659 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) | |
ae156f85 | 3660 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3661 | |
3662 | (define_insn_and_split "*cmpint_cc" | |
ae156f85 | 3663 | [(set (reg CC_REGNUM) |
02887425 | 3664 | (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3665 | UNSPEC_STRCMPCC_TO_INT) |
02887425 UW |
3666 | (const_int 0))) |
3667 | (set (match_operand:SI 0 "register_operand" "=d") | |
5a3fe9b6 | 3668 | (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))] |
02887425 UW |
3669 | "s390_match_ccmode (insn, CCSmode)" |
3670 | "#" | |
3671 | "&& reload_completed" | |
3672 | [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) | |
3673 | (parallel | |
3674 | [(set (match_dup 2) (match_dup 3)) | |
3675 | (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] | |
9db1d521 | 3676 | { |
02887425 UW |
3677 | rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); |
3678 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3679 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3680 | }) | |
9db1d521 | 3681 | |
02887425 | 3682 | (define_insn_and_split "*cmpint_sign" |
9db1d521 | 3683 | [(set (match_operand:DI 0 "register_operand" "=d") |
02887425 | 3684 | (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3685 | UNSPEC_STRCMPCC_TO_INT))) |
ae156f85 | 3686 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3687 | "TARGET_ZARCH" |
02887425 UW |
3688 | "#" |
3689 | "&& reload_completed" | |
3690 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3691 | (parallel | |
3692 | [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) | |
ae156f85 | 3693 | (clobber (reg:CC CC_REGNUM))])]) |
02887425 UW |
3694 | |
3695 | (define_insn_and_split "*cmpint_sign_cc" | |
ae156f85 | 3696 | [(set (reg CC_REGNUM) |
9381e3f1 | 3697 | (compare (ashiftrt:DI (ashift:DI (subreg:DI |
02887425 | 3698 | (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] |
5a3fe9b6 | 3699 | UNSPEC_STRCMPCC_TO_INT) 0) |
02887425 UW |
3700 | (const_int 32)) (const_int 32)) |
3701 | (const_int 0))) | |
3702 | (set (match_operand:DI 0 "register_operand" "=d") | |
5a3fe9b6 | 3703 | (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))] |
9602b6a1 | 3704 | "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" |
02887425 UW |
3705 | "#" |
3706 | "&& reload_completed" | |
3707 | [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) | |
3708 | (parallel | |
3709 | [(set (match_dup 2) (match_dup 3)) | |
3710 | (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] | |
9db1d521 | 3711 | { |
02887425 UW |
3712 | rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); |
3713 | operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); | |
3714 | operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); | |
3715 | }) | |
9db1d521 | 3716 | |
4023fb28 | 3717 | |
9db1d521 HP |
3718 | ;; |
3719 | ;;- Conversion instructions. | |
3720 | ;; | |
3721 | ||
6fa05db6 | 3722 | (define_insn "*sethighpartsi" |
d3632d41 | 3723 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3724 | (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") |
3725 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3726 | (clobber (reg:CC CC_REGNUM))] |
4023fb28 | 3727 | "" |
d3632d41 | 3728 | "@ |
6fa05db6 AS |
3729 | icm\t%0,%2,%S1 |
3730 | icmy\t%0,%2,%S1" | |
9381e3f1 | 3731 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3732 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 3733 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
4023fb28 | 3734 | |
6fa05db6 | 3735 | (define_insn "*sethighpartdi_64" |
4023fb28 | 3736 | [(set (match_operand:DI 0 "register_operand" "=d") |
3e4be43f | 3737 | (unspec:DI [(match_operand:BLK 1 "s_operand" "S") |
6fa05db6 | 3738 | (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) |
ae156f85 | 3739 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3740 | "TARGET_ZARCH" |
6fa05db6 | 3741 | "icmh\t%0,%2,%S1" |
729e750f WG |
3742 | [(set_attr "op_type" "RSY") |
3743 | (set_attr "z10prop" "z10_super")]) | |
4023fb28 | 3744 | |
6fa05db6 | 3745 | (define_insn "*sethighpartdi_31" |
d3632d41 | 3746 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
6fa05db6 AS |
3747 | (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") |
3748 | (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) | |
ae156f85 | 3749 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 3750 | "!TARGET_ZARCH" |
d3632d41 | 3751 | "@ |
6fa05db6 AS |
3752 | icm\t%0,%2,%S1 |
3753 | icmy\t%0,%2,%S1" | |
9381e3f1 | 3754 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 3755 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 WG |
3756 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
3757 | ||
1a2e356e RH |
3758 | ; |
3759 | ; extv instruction patterns | |
3760 | ; | |
3761 | ||
3762 | ; FIXME: This expander needs to be converted from DI to GPR as well | |
3763 | ; after resolving some issues with it. | |
3764 | ||
3765 | (define_expand "extzv" | |
3766 | [(parallel | |
3767 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3768 | (zero_extract:DI | |
3769 | (match_operand:DI 1 "register_operand" "d") | |
3770 | (match_operand 2 "const_int_operand" "") ; size | |
3771 | (match_operand 3 "const_int_operand" ""))) ; start | |
3772 | (clobber (reg:CC CC_REGNUM))])] | |
3773 | "TARGET_Z10" | |
3774 | { | |
0f6f72e8 DV |
3775 | if (! EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), 64)) |
3776 | FAIL; | |
1a2e356e RH |
3777 | /* Starting with zEC12 there is risbgn not clobbering CC. */ |
3778 | if (TARGET_ZEC12) | |
3779 | { | |
3780 | emit_move_insn (operands[0], | |
3781 | gen_rtx_ZERO_EXTRACT (DImode, | |
3782 | operands[1], | |
3783 | operands[2], | |
3784 | operands[3])); | |
3785 | DONE; | |
3786 | } | |
3787 | }) | |
3788 | ||
64c744b9 | 3789 | (define_insn "*extzv<mode><clobbercc_or_nocc>" |
1a2e356e RH |
3790 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3791 | (zero_extract:GPR | |
3792 | (match_operand:GPR 1 "register_operand" "d") | |
3793 | (match_operand 2 "const_int_operand" "") ; size | |
64c744b9 DV |
3794 | (match_operand 3 "const_int_operand" ""))) ; start |
3795 | ] | |
0f6f72e8 DV |
3796 | "<z10_or_zEC12_cond> |
3797 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[2]), INTVAL (operands[3]), | |
3798 | GET_MODE_BITSIZE (<MODE>mode))" | |
64c744b9 DV |
3799 | "<risbg_n>\t%0,%1,64-%2,128+63,<bitoff_plus>%3+%2" ; dst, src, start, end, shift |
3800 | [(set_attr "op_type" "RIE") | |
3801 | (set_attr "z10prop" "z10_super_E1")]) | |
1a2e356e | 3802 | |
64c744b9 DV |
3803 | ; 64 bit: (a & -16) | ((b >> 8) & 15) |
3804 | (define_insn "*extzvdi<clobbercc_or_nocc>_lshiftrt" | |
3805 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
3806 | (match_operand 1 "const_int_operand" "") ; size | |
3807 | (match_operand 2 "const_int_operand" "")) ; start | |
3808 | (lshiftrt:DI (match_operand:DI 3 "register_operand" "d") | |
3809 | (match_operand:DI 4 "nonzero_shift_count_operand" "")))] | |
3810 | "<z10_or_zEC12_cond> | |
0f6f72e8 | 3811 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
64c744b9 DV |
3812 | && 64 - UINTVAL (operands[4]) >= UINTVAL (operands[1])" |
3813 | "<risbg_n>\t%0,%3,%2,%2+%1-1,128-%2-%1-%4" | |
3814 | [(set_attr "op_type" "RIE") | |
3815 | (set_attr "z10prop" "z10_super_E1")]) | |
3816 | ||
3817 | ; 32 bit: (a & -16) | ((b >> 8) & 15) | |
3818 | (define_insn "*<risbg_n>_ior_and_sr_ze" | |
3819 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3820 | (ior:SI (and:SI | |
3821 | (match_operand:SI 1 "register_operand" "0") | |
3822 | (match_operand:SI 2 "const_int_operand" "")) | |
3823 | (subreg:SI | |
3824 | (zero_extract:DI | |
3825 | (match_operand:DI 3 "register_operand" "d") | |
3826 | (match_operand 4 "const_int_operand" "") ; size | |
3827 | (match_operand 5 "const_int_operand" "")) ; start | |
3828 | 4)))] | |
3829 | "<z10_or_zEC12_cond> | |
0f6f72e8 | 3830 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[4]), INTVAL (operands[5]), 64) |
64c744b9 DV |
3831 | && UINTVAL (operands[2]) == (~(0ULL) << UINTVAL (operands[4]))" |
3832 | "<risbg_n>\t%0,%3,64-%4,63,%4+%5" | |
3833 | [(set_attr "op_type" "RIE") | |
3834 | (set_attr "z10prop" "z10_super_E1")]) | |
3835 | ||
3836 | ; ((int)foo >> 10) & 1; | |
3837 | (define_insn "*extract1bitdi<clobbercc_or_nocc>" | |
3838 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3839 | (ne:DI (zero_extract:DI | |
3840 | (match_operand:DI 1 "register_operand" "d") | |
3841 | (const_int 1) ; size | |
3842 | (match_operand 2 "const_int_operand" "")) ; start | |
3843 | (const_int 0)))] | |
0f6f72e8 DV |
3844 | "<z10_or_zEC12_cond> |
3845 | && EXTRACT_ARGS_IN_RANGE (1, INTVAL (operands[2]), 64)" | |
64c744b9 DV |
3846 | "<risbg_n>\t%0,%1,64-1,128+63,%2+1" ; dst, src, start, end, shift |
3847 | [(set_attr "op_type" "RIE") | |
3848 | (set_attr "z10prop" "z10_super_E1")]) | |
3849 | ||
3850 | (define_insn "*<risbg_n>_and_subregdi_rotr" | |
3851 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3852 | (and:DI (subreg:DI | |
3853 | (rotate:SINT (match_operand:SINT 1 "register_operand" "d") | |
3854 | (match_operand:SINT 2 "const_int_operand" "")) 0) | |
3855 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3856 | "<z10_or_zEC12_cond> | |
3857 | && UINTVAL (operands[3]) < (1ULL << (UINTVAL (operands[2]) & 0x3f))" | |
3858 | "<risbg_n>\t%0,%1,%s3,128+%e3,<bitoff_plus>%2" ; dst, src, start, end, shift | |
3859 | [(set_attr "op_type" "RIE") | |
3860 | (set_attr "z10prop" "z10_super_E1")]) | |
3861 | ||
3862 | (define_insn "*<risbg_n>_and_subregdi_rotl" | |
3863 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3864 | (and:DI (subreg:DI | |
3865 | (rotate:SINT (match_operand:SINT 1 "register_operand" "d") | |
3866 | (match_operand:SINT 2 "const_int_operand" "")) 0) | |
3867 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3868 | "<z10_or_zEC12_cond> | |
3869 | && !(UINTVAL (operands[3]) & ((1ULL << (UINTVAL (operands[2]) & 0x3f)) - 1))" | |
3870 | "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift | |
3871 | [(set_attr "op_type" "RIE") | |
3872 | (set_attr "z10prop" "z10_super_E1")]) | |
3873 | ||
3874 | (define_insn "*<risbg_n>_di_and_rot" | |
3875 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3876 | (and:DI (rotate:DI (match_operand:DI 1 "register_operand" "d") | |
3877 | (match_operand:DI 2 "const_int_operand" "")) | |
3878 | (match_operand:DI 3 "contiguous_bitmask_operand" "")))] | |
3879 | "<z10_or_zEC12_cond>" | |
3880 | "<risbg_n>\t%0,%1,%s3,128+%e3,%2" ; dst, src, start, end, shift | |
1a2e356e RH |
3881 | [(set_attr "op_type" "RIE") |
3882 | (set_attr "z10prop" "z10_super_E1")]) | |
4023fb28 | 3883 | |
1a2e356e | 3884 | (define_insn_and_split "*pre_z10_extzv<mode>" |
6fa05db6 | 3885 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3e4be43f | 3886 | (zero_extract:GPR (match_operand:QI 1 "s_operand" "S") |
1a2e356e | 3887 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3888 | (const_int 0))) |
ae156f85 | 3889 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3890 | "!TARGET_Z10" |
cc7ab9b7 UW |
3891 | "#" |
3892 | "&& reload_completed" | |
4023fb28 | 3893 | [(parallel |
6fa05db6 | 3894 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3895 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 | 3896 | (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] |
4023fb28 | 3897 | { |
6fa05db6 AS |
3898 | int bitsize = INTVAL (operands[2]); |
3899 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3900 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3901 | ||
3902 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3903 | set_mem_size (operands[1], size); |
2542ef05 | 3904 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 | 3905 | operands[3] = GEN_INT (mask); |
b628bd8e | 3906 | }) |
4023fb28 | 3907 | |
1a2e356e | 3908 | (define_insn_and_split "*pre_z10_extv<mode>" |
6fa05db6 | 3909 | [(set (match_operand:GPR 0 "register_operand" "=d") |
3e4be43f | 3910 | (sign_extract:GPR (match_operand:QI 1 "s_operand" "S") |
1a2e356e | 3911 | (match_operand 2 "nonzero_shift_count_operand" "") |
6fa05db6 | 3912 | (const_int 0))) |
ae156f85 | 3913 | (clobber (reg:CC CC_REGNUM))] |
1a2e356e | 3914 | "" |
cc7ab9b7 UW |
3915 | "#" |
3916 | "&& reload_completed" | |
4023fb28 | 3917 | [(parallel |
6fa05db6 | 3918 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) |
ae156f85 | 3919 | (clobber (reg:CC CC_REGNUM))]) |
6fa05db6 AS |
3920 | (parallel |
3921 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) | |
3922 | (clobber (reg:CC CC_REGNUM))])] | |
3923 | { | |
3924 | int bitsize = INTVAL (operands[2]); | |
3925 | int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ | |
3926 | int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); | |
3927 | ||
3928 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 3929 | set_mem_size (operands[1], size); |
2542ef05 | 3930 | operands[2] = GEN_INT (<GPR:bitsize> - bitsize); |
6fa05db6 AS |
3931 | operands[3] = GEN_INT (mask); |
3932 | }) | |
3933 | ||
3934 | ; | |
3935 | ; insv instruction patterns | |
3936 | ; | |
3937 | ||
3938 | (define_expand "insv" | |
3939 | [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") | |
3940 | (match_operand 1 "const_int_operand" "") | |
3941 | (match_operand 2 "const_int_operand" "")) | |
3942 | (match_operand 3 "general_operand" ""))] | |
3943 | "" | |
4023fb28 | 3944 | { |
6fa05db6 AS |
3945 | if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) |
3946 | DONE; | |
3947 | FAIL; | |
b628bd8e | 3948 | }) |
4023fb28 | 3949 | |
2542ef05 RH |
3950 | |
3951 | ; The normal RTL expansion will never generate a zero_extract where | |
3952 | ; the location operand isn't word mode. However, we do this in the | |
3953 | ; back-end when generating atomic operations. See s390_two_part_insv. | |
64c744b9 | 3954 | (define_insn "*insv<mode><clobbercc_or_nocc>" |
22ac2c2f | 3955 | [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") |
2542ef05 RH |
3956 | (match_operand 1 "const_int_operand" "I") ; size |
3957 | (match_operand 2 "const_int_operand" "I")) ; pos | |
22ac2c2f | 3958 | (match_operand:GPR 3 "nonimmediate_operand" "d"))] |
64c744b9 | 3959 | "<z10_or_zEC12_cond> |
0f6f72e8 DV |
3960 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), |
3961 | GET_MODE_BITSIZE (<MODE>mode)) | |
2542ef05 | 3962 | && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" |
64c744b9 | 3963 | "<risbg_n>\t%0,%3,<bitoff_plus>%2,<bitoff_plus>%2+%1-1,<bitsize>-%2-%1" |
9381e3f1 WG |
3964 | [(set_attr "op_type" "RIE") |
3965 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 3966 | |
22ac2c2f AK |
3967 | ; and op1 with a mask being 1 for the selected bits and 0 for the rest |
3968 | ; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest | |
64c744b9 DV |
3969 | (define_insn "*insv<mode><clobbercc_or_nocc>_noshift" |
3970 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d") | |
3971 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d,0") | |
75ca1b39 | 3972 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) |
64c744b9 | 3973 | (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0,d") |
75ca1b39 | 3974 | (match_operand:GPR 4 "const_int_operand" ""))))] |
64c744b9 DV |
3975 | "<z10_or_zEC12_cond> && INTVAL (operands[2]) == ~INTVAL (operands[4])" |
3976 | "@ | |
3977 | <risbg_n>\t%0,%1,%<bfstart>2,%<bfend>2,0 | |
3978 | <risbg_n>\t%0,%3,%<bfstart>4,%<bfend>4,0" | |
3979 | [(set_attr "op_type" "RIE") | |
3980 | (set_attr "z10prop" "z10_super_E1")]) | |
22ac2c2f | 3981 | |
64c744b9 DV |
3982 | (define_insn "*insv_z10_noshift_cc" |
3983 | [(set (reg CC_REGNUM) | |
3984 | (compare | |
3985 | (ior:DI | |
3986 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") | |
3987 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
3988 | (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") | |
3989 | (match_operand:DI 4 "const_int_operand" ""))) | |
3990 | (const_int 0))) | |
3991 | (set (match_operand:DI 0 "nonimmediate_operand" "=d,d") | |
3992 | (ior:DI (and:DI (match_dup 1) (match_dup 2)) | |
3993 | (and:DI (match_dup 3) (match_dup 4))))] | |
3994 | "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) | |
3995 | && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
3996 | "@ | |
3997 | risbg\t%0,%1,%s2,%e2,0 | |
3998 | risbg\t%0,%3,%s4,%e4,0" | |
3999 | [(set_attr "op_type" "RIE") | |
4000 | (set_attr "z10prop" "z10_super_E1")]) | |
4001 | ||
4002 | (define_insn "*insv_z10_noshift_cconly" | |
4003 | [(set | |
4004 | (reg CC_REGNUM) | |
4005 | (compare | |
4006 | (ior:DI | |
4007 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,0") | |
4008 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4009 | (and:DI (match_operand:DI 3 "nonimmediate_operand" "0,d") | |
4010 | (match_operand:DI 4 "const_int_operand" ""))) | |
4011 | (const_int 0))) | |
4012 | (clobber (match_scratch:DI 0 "=d,d"))] | |
4013 | "TARGET_Z10 && s390_match_ccmode (insn, CCSmode) | |
4014 | && INTVAL (operands[2]) == ~INTVAL (operands[4])" | |
4015 | "@ | |
4016 | risbg\t%0,%1,%s2,%e2,0 | |
4017 | risbg\t%0,%3,%s4,%e4,0" | |
9381e3f1 WG |
4018 | [(set_attr "op_type" "RIE") |
4019 | (set_attr "z10prop" "z10_super_E1")]) | |
963fc8d0 | 4020 | |
3d44ff99 AK |
4021 | ; Implement appending Y on the left of S bits of X |
4022 | ; x = (y << s) | (x & ((1 << s) - 1)) | |
64c744b9 | 4023 | (define_insn "*insv<mode><clobbercc_or_nocc>_appendbitsleft" |
3d44ff99 AK |
4024 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4025 | (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "0") | |
4026 | (match_operand:GPR 2 "immediate_operand" "")) | |
4027 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "d") | |
4028 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
64c744b9 DV |
4029 | "<z10_or_zEC12_cond> |
4030 | && UINTVAL (operands[2]) == (1UL << UINTVAL (operands[4])) - 1" | |
4031 | "<risbg_n>\t%0,%3,<bitoff>,64-%4-1,%4" | |
3d44ff99 AK |
4032 | [(set_attr "op_type" "RIE") |
4033 | (set_attr "z10prop" "z10_super_E1")]) | |
4034 | ||
64c744b9 DV |
4035 | ; a = ((i32)a & -16777216) | (((ui32)b) >> 8) |
4036 | (define_insn "*<risbg_n>_<mode>_ior_and_lshiftrt" | |
4037 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4038 | (ior:GPR (and:GPR | |
4039 | (match_operand:GPR 1 "register_operand" "0") | |
4040 | (match_operand:GPR 2 "const_int_operand" "")) | |
4041 | (lshiftrt:GPR | |
4042 | (match_operand:GPR 3 "register_operand" "d") | |
4043 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
4044 | "<z10_or_zEC12_cond> && UINTVAL (operands[2]) | |
4045 | == (~(0ULL) << (GET_MODE_BITSIZE (<MODE>mode) - UINTVAL (operands[4])))" | |
4046 | "<risbg_n>\t%0,%3,<bitoff_plus>%4,63,64-%4" | |
4047 | [(set_attr "op_type" "RIE") | |
4048 | (set_attr "z10prop" "z10_super_E1")]) | |
4049 | ||
4050 | ; (ui32)(((ui64)x) >> 48) | ((i32)y & -65536); | |
4051 | (define_insn "*<risbg_n>_sidi_ior_and_lshiftrt" | |
4052 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4053 | (ior:SI (and:SI | |
4054 | (match_operand:SI 1 "register_operand" "0") | |
4055 | (match_operand:SI 2 "const_int_operand" "")) | |
4056 | (subreg:SI | |
4057 | (lshiftrt:DI | |
4058 | (match_operand:DI 3 "register_operand" "d") | |
4059 | (match_operand:DI 4 "nonzero_shift_count_operand" "")) 4)))] | |
4060 | "<z10_or_zEC12_cond> | |
4061 | && UINTVAL (operands[2]) == ~(~(0ULL) >> UINTVAL (operands[4]))" | |
4062 | "<risbg_n>\t%0,%3,%4,63,64-%4" | |
4063 | [(set_attr "op_type" "RIE") | |
4064 | (set_attr "z10prop" "z10_super_E1")]) | |
4065 | ||
4066 | ; (ui32)(((ui64)x) >> 12) & -4 | |
4067 | (define_insn "*trunc_sidi_and_subreg_lshrt<clobbercc_or_nocc>" | |
4068 | [(set (match_operand:SI 0 "register_operand" "=d") | |
4069 | (and:SI | |
4070 | (subreg:SI (lshiftrt:DI | |
4071 | (match_operand:DI 1 "register_operand" "d") | |
4072 | (match_operand:DI 2 "nonzero_shift_count_operand" "")) 4) | |
4073 | (match_operand:SI 3 "contiguous_bitmask_nowrap_operand" "")))] | |
4074 | "<z10_or_zEC12_cond>" | |
4075 | "<risbg_n>\t%0,%1,%t3,128+%f3,64-%2" | |
3d44ff99 AK |
4076 | [(set_attr "op_type" "RIE") |
4077 | (set_attr "z10prop" "z10_super_E1")]) | |
4078 | ||
4079 | ; z = (x << c) | (y >> d) with (x << c) and (y >> d) not overlapping after shifting | |
4080 | ; -> z = y >> d; z = (x << c) | (z & ((1 << c) - 1)) | |
4081 | ; -> z = y >> d; z = risbg; | |
4082 | ||
4083 | (define_split | |
4084 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
4085 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
4086 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4087 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
4088 | (match_operand:GPR 4 "nonzero_shift_count_operand" ""))))] | |
4089 | "TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 4090 | [(set (match_dup 6) |
3d44ff99 AK |
4091 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
4092 | (set (match_dup 0) | |
1d11f7ce | 4093 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
4094 | (ashift:GPR (match_dup 3) (match_dup 4))))] |
4095 | { | |
4096 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
3168e073 | 4097 | if (reg_overlap_mentioned_p (operands[0], operands[3])) |
1d11f7ce AK |
4098 | { |
4099 | if (!can_create_pseudo_p ()) | |
4100 | FAIL; | |
4101 | operands[6] = gen_reg_rtx (<MODE>mode); | |
4102 | } | |
4103 | else | |
4104 | operands[6] = operands[0]; | |
3d44ff99 AK |
4105 | }) |
4106 | ||
4107 | (define_split | |
4108 | [(parallel | |
4109 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
4110 | (ior:GPR (lshiftrt:GPR (match_operand:GPR 1 "nonimmediate_operand" "") | |
4111 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4112 | (ashift:GPR (match_operand:GPR 3 "nonimmediate_operand" "") | |
4113 | (match_operand:GPR 4 "nonzero_shift_count_operand" "")))) | |
4114 | (clobber (reg:CC CC_REGNUM))])] | |
4115 | "TARGET_Z10 && !TARGET_ZEC12 && UINTVAL (operands[2]) + UINTVAL (operands[4]) >= <bitsize>" | |
1d11f7ce | 4116 | [(set (match_dup 6) |
3d44ff99 AK |
4117 | (lshiftrt:GPR (match_dup 1) (match_dup 2))) |
4118 | (parallel | |
4119 | [(set (match_dup 0) | |
1d11f7ce | 4120 | (ior:GPR (and:GPR (match_dup 6) (match_dup 5)) |
3d44ff99 AK |
4121 | (ashift:GPR (match_dup 3) (match_dup 4)))) |
4122 | (clobber (reg:CC CC_REGNUM))])] | |
4123 | { | |
4124 | operands[5] = GEN_INT ((1UL << UINTVAL (operands[4])) - 1); | |
3168e073 | 4125 | if (reg_overlap_mentioned_p (operands[0], operands[3])) |
1d11f7ce AK |
4126 | { |
4127 | if (!can_create_pseudo_p ()) | |
4128 | FAIL; | |
4129 | operands[6] = gen_reg_rtx (<MODE>mode); | |
4130 | } | |
4131 | else | |
4132 | operands[6] = operands[0]; | |
3d44ff99 AK |
4133 | }) |
4134 | ||
50dc4eed | 4135 | ; rosbg, rxsbg |
571e408a | 4136 | (define_insn "*r<noxa>sbg_<mode>_noshift" |
963fc8d0 | 4137 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
571e408a RH |
4138 | (IXOR:GPR |
4139 | (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4140 | (match_operand:GPR 2 "contiguous_bitmask_operand" "")) | |
4141 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
963fc8d0 | 4142 | (clobber (reg:CC CC_REGNUM))] |
75ca1b39 | 4143 | "TARGET_Z10" |
571e408a RH |
4144 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0" |
4145 | [(set_attr "op_type" "RIE")]) | |
4146 | ||
50dc4eed | 4147 | ; rosbg, rxsbg |
571e408a RH |
4148 | (define_insn "*r<noxa>sbg_di_rotl" |
4149 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d") | |
4150 | (IXOR:DI | |
4151 | (and:DI | |
4152 | (rotate:DI | |
4153 | (match_operand:DI 1 "nonimmediate_operand" "d") | |
4154 | (match_operand:DI 3 "const_int_operand" "")) | |
4155 | (match_operand:DI 2 "contiguous_bitmask_operand" "")) | |
4156 | (match_operand:DI 4 "nonimmediate_operand" "0"))) | |
4157 | (clobber (reg:CC CC_REGNUM))] | |
4158 | "TARGET_Z10" | |
4159 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3" | |
4160 | [(set_attr "op_type" "RIE")]) | |
4161 | ||
50dc4eed | 4162 | ; rosbg, rxsbg |
f3d90045 | 4163 | (define_insn "*r<noxa>sbg_<mode>_srl_bitmask" |
571e408a RH |
4164 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4165 | (IXOR:GPR | |
4166 | (and:GPR | |
4167 | (lshiftrt:GPR | |
4168 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4169 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 4170 | (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) |
571e408a RH |
4171 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) |
4172 | (clobber (reg:CC CC_REGNUM))] | |
4173 | "TARGET_Z10 | |
4174 | && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), | |
4175 | INTVAL (operands[2]))" | |
4176 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3" | |
4177 | [(set_attr "op_type" "RIE")]) | |
4178 | ||
50dc4eed | 4179 | ; rosbg, rxsbg |
f3d90045 | 4180 | (define_insn "*r<noxa>sbg_<mode>_sll_bitmask" |
571e408a RH |
4181 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") |
4182 | (IXOR:GPR | |
4183 | (and:GPR | |
4184 | (ashift:GPR | |
4185 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4186 | (match_operand:GPR 3 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 4187 | (match_operand:GPR 2 "contiguous_bitmask_nowrap_operand" "")) |
571e408a RH |
4188 | (match_operand:GPR 4 "nonimmediate_operand" "0"))) |
4189 | (clobber (reg:CC CC_REGNUM))] | |
4190 | "TARGET_Z10 | |
4191 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]), | |
4192 | INTVAL (operands[2]))" | |
4193 | "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3" | |
963fc8d0 AK |
4194 | [(set_attr "op_type" "RIE")]) |
4195 | ||
f3d90045 DV |
4196 | ;; unsigned {int,long} a, b |
4197 | ;; a = a | (b << const_int) | |
4198 | ;; a = a ^ (b << const_int) | |
50dc4eed | 4199 | ; rosbg, rxsbg |
f3d90045 DV |
4200 | (define_insn "*r<noxa>sbg_<mode>_sll" |
4201 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
4202 | (IXOR:GPR | |
4203 | (ashift:GPR | |
4204 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4205 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4206 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
4207 | (clobber (reg:CC CC_REGNUM))] | |
4208 | "TARGET_Z10" | |
576987fc | 4209 | "r<noxa>sbg\t%0,%1,<bitoff>,63-%2,%2" |
f3d90045 DV |
4210 | [(set_attr "op_type" "RIE")]) |
4211 | ||
4212 | ;; unsigned {int,long} a, b | |
4213 | ;; a = a | (b >> const_int) | |
4214 | ;; a = a ^ (b >> const_int) | |
50dc4eed | 4215 | ; rosbg, rxsbg |
f3d90045 DV |
4216 | (define_insn "*r<noxa>sbg_<mode>_srl" |
4217 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") | |
4218 | (IXOR:GPR | |
4219 | (lshiftrt:GPR | |
4220 | (match_operand:GPR 1 "nonimmediate_operand" "d") | |
4221 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
4222 | (match_operand:GPR 3 "nonimmediate_operand" "0"))) | |
4223 | (clobber (reg:CC CC_REGNUM))] | |
4224 | "TARGET_Z10" | |
576987fc | 4225 | "r<noxa>sbg\t%0,%1,<bitoff_plus>%2,63,64-%2" |
f3d90045 DV |
4226 | [(set_attr "op_type" "RIE")]) |
4227 | ||
5bb33936 RH |
4228 | ;; These two are generated by combine for s.bf &= val. |
4229 | ;; ??? For bitfields smaller than 32-bits, we wind up with SImode | |
4230 | ;; shifts and ands, which results in some truly awful patterns | |
4231 | ;; including subregs of operations. Rather unnecessisarily, IMO. | |
4232 | ;; Instead of | |
4233 | ;; | |
4234 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4235 | ;; (const_int 24 [0x18]) | |
4236 | ;; (const_int 0 [0])) | |
4237 | ;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4238 | ;; (const_int 40 [0x28])) 4) | |
4239 | ;; (reg:SI 4 %r4 [ y+4 ])) 0)) | |
4240 | ;; | |
4241 | ;; we should instead generate | |
4242 | ;; | |
4243 | ;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) | |
4244 | ;; (const_int 24 [0x18]) | |
4245 | ;; (const_int 0 [0])) | |
4246 | ;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ]) | |
4247 | ;; (const_int 40 [0x28])) | |
4248 | ;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0))) | |
4249 | ;; | |
4250 | ;; by noticing that we can push down the outer paradoxical subreg | |
4251 | ;; into the operation. | |
4252 | ||
4253 | (define_insn "*insv_rnsbg_noshift" | |
4254 | [(set (zero_extract:DI | |
4255 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4256 | (match_operand 1 "const_int_operand" "") | |
4257 | (match_operand 2 "const_int_operand" "")) | |
4258 | (and:DI | |
4259 | (match_dup 0) | |
4260 | (match_operand:DI 3 "nonimmediate_operand" "d"))) | |
4261 | (clobber (reg:CC CC_REGNUM))] | |
4262 | "TARGET_Z10 | |
0f6f72e8 | 4263 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
5bb33936 RH |
4264 | && INTVAL (operands[1]) + INTVAL (operands[2]) == 64" |
4265 | "rnsbg\t%0,%3,%2,63,0" | |
4266 | [(set_attr "op_type" "RIE")]) | |
4267 | ||
4268 | (define_insn "*insv_rnsbg_srl" | |
4269 | [(set (zero_extract:DI | |
4270 | (match_operand:DI 0 "nonimmediate_operand" "+d") | |
4271 | (match_operand 1 "const_int_operand" "") | |
4272 | (match_operand 2 "const_int_operand" "")) | |
4273 | (and:DI | |
4274 | (lshiftrt:DI | |
4275 | (match_dup 0) | |
4276 | (match_operand 3 "const_int_operand" "")) | |
4277 | (match_operand:DI 4 "nonimmediate_operand" "d"))) | |
4278 | (clobber (reg:CC CC_REGNUM))] | |
4279 | "TARGET_Z10 | |
0f6f72e8 | 4280 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), INTVAL (operands[2]), 64) |
5bb33936 RH |
4281 | && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])" |
4282 | "rnsbg\t%0,%4,%2,%2+%1-1,%3" | |
4283 | [(set_attr "op_type" "RIE")]) | |
4284 | ||
6fa05db6 | 4285 | (define_insn "*insv<mode>_mem_reg" |
9602b6a1 | 4286 | [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") |
6fa05db6 AS |
4287 | (match_operand 1 "const_int_operand" "n,n") |
4288 | (const_int 0)) | |
9602b6a1 | 4289 | (match_operand:W 2 "register_operand" "d,d"))] |
0f6f72e8 DV |
4290 | "EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) |
4291 | && INTVAL (operands[1]) > 0 | |
6fa05db6 AS |
4292 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) |
4293 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4294 | { | |
4295 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4296 | ||
4297 | operands[1] = GEN_INT ((1ul << size) - 1); | |
9381e3f1 | 4298 | return (which_alternative == 0) ? "stcm\t%2,%1,%S0" |
6fa05db6 AS |
4299 | : "stcmy\t%2,%1,%S0"; |
4300 | } | |
9381e3f1 | 4301 | [(set_attr "op_type" "RS,RSY") |
3e4be43f | 4302 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 4303 | (set_attr "z10prop" "z10_super,z10_super")]) |
6fa05db6 AS |
4304 | |
4305 | (define_insn "*insvdi_mem_reghigh" | |
3e4be43f | 4306 | [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+S") |
6fa05db6 AS |
4307 | (match_operand 1 "const_int_operand" "n") |
4308 | (const_int 0)) | |
4309 | (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") | |
4310 | (const_int 32)))] | |
9602b6a1 | 4311 | "TARGET_ZARCH |
0f6f72e8 | 4312 | && EXTRACT_ARGS_IN_RANGE (INTVAL (operands[1]), 0, 64) |
6fa05db6 AS |
4313 | && INTVAL (operands[1]) > 0 |
4314 | && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) | |
4315 | && INTVAL (operands[1]) % BITS_PER_UNIT == 0" | |
4316 | { | |
4317 | int size = INTVAL (operands[1]) / BITS_PER_UNIT; | |
4318 | ||
4319 | operands[1] = GEN_INT ((1ul << size) - 1); | |
4320 | return "stcmh\t%2,%1,%S0"; | |
4321 | } | |
9381e3f1 WG |
4322 | [(set_attr "op_type" "RSY") |
4323 | (set_attr "z10prop" "z10_super")]) | |
6fa05db6 | 4324 | |
9602b6a1 AK |
4325 | (define_insn "*insvdi_reg_imm" |
4326 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4327 | (const_int 16) | |
4328 | (match_operand 1 "const_int_operand" "n")) | |
4329 | (match_operand:DI 2 "const_int_operand" "n"))] | |
6fa05db6 | 4330 | "TARGET_ZARCH |
0f6f72e8 | 4331 | && EXTRACT_ARGS_IN_RANGE (16, INTVAL (operands[1]), 64) |
6fa05db6 AS |
4332 | && INTVAL (operands[1]) >= 0 |
4333 | && INTVAL (operands[1]) < BITS_PER_WORD | |
4334 | && INTVAL (operands[1]) % 16 == 0" | |
4335 | { | |
4336 | switch (BITS_PER_WORD - INTVAL (operands[1])) | |
4337 | { | |
4338 | case 64: return "iihh\t%0,%x2"; break; | |
4339 | case 48: return "iihl\t%0,%x2"; break; | |
4340 | case 32: return "iilh\t%0,%x2"; break; | |
4341 | case 16: return "iill\t%0,%x2"; break; | |
4342 | default: gcc_unreachable(); | |
4343 | } | |
4344 | } | |
9381e3f1 WG |
4345 | [(set_attr "op_type" "RI") |
4346 | (set_attr "z10prop" "z10_super_E1")]) | |
4347 | ||
9fec758d WG |
4348 | ; Update the left-most 32 bit of a DI. |
4349 | (define_insn "*insv_h_di_reg_extimm" | |
4350 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4351 | (const_int 32) | |
4352 | (const_int 0)) | |
4353 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4354 | "TARGET_EXTIMM" | |
4355 | "iihf\t%0,%o1" | |
4356 | [(set_attr "op_type" "RIL") | |
4357 | (set_attr "z10prop" "z10_fwd_E1")]) | |
6fa05db6 | 4358 | |
d378b983 RH |
4359 | ; Update the right-most 32 bit of a DI. |
4360 | (define_insn "*insv_l_di_reg_extimm" | |
4361 | [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") | |
4362 | (const_int 32) | |
4363 | (const_int 32)) | |
4364 | (match_operand:DI 1 "const_int_operand" "n"))] | |
4365 | "TARGET_EXTIMM" | |
4366 | "iilf\t%0,%o1" | |
9381e3f1 | 4367 | [(set_attr "op_type" "RIL") |
9fec758d | 4368 | (set_attr "z10prop" "z10_fwd_A1")]) |
6fa05db6 | 4369 | |
9db1d521 HP |
4370 | ; |
4371 | ; extendsidi2 instruction pattern(s). | |
4372 | ; | |
4373 | ||
4023fb28 UW |
4374 | (define_expand "extendsidi2" |
4375 | [(set (match_operand:DI 0 "register_operand" "") | |
4376 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4377 | "" | |
4023fb28 | 4378 | { |
9602b6a1 | 4379 | if (!TARGET_ZARCH) |
4023fb28 | 4380 | { |
c41c1387 | 4381 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4382 | emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); |
4383 | emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); | |
4384 | emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); | |
4023fb28 UW |
4385 | DONE; |
4386 | } | |
ec24698e | 4387 | }) |
4023fb28 UW |
4388 | |
4389 | (define_insn "*extendsidi2" | |
963fc8d0 | 4390 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4391 | (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] |
9602b6a1 | 4392 | "TARGET_ZARCH" |
9db1d521 | 4393 | "@ |
d40c829f | 4394 | lgfr\t%0,%1 |
963fc8d0 AK |
4395 | lgf\t%0,%1 |
4396 | lgfrl\t%0,%1" | |
4397 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4398 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4399 | (set_attr "cpu_facility" "*,*,z10") |
4400 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4401 | |
9db1d521 | 4402 | ; |
56477c21 | 4403 | ; extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4404 | ; |
4405 | ||
56477c21 AS |
4406 | (define_expand "extend<HQI:mode><DSI:mode>2" |
4407 | [(set (match_operand:DSI 0 "register_operand" "") | |
4408 | (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4023fb28 | 4409 | "" |
4023fb28 | 4410 | { |
9602b6a1 | 4411 | if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) |
4023fb28 UW |
4412 | { |
4413 | rtx tmp = gen_reg_rtx (SImode); | |
56477c21 | 4414 | emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); |
4023fb28 UW |
4415 | emit_insn (gen_extendsidi2 (operands[0], tmp)); |
4416 | DONE; | |
4417 | } | |
ec24698e | 4418 | else if (!TARGET_EXTIMM) |
4023fb28 | 4419 | { |
2542ef05 | 4420 | rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>); |
56477c21 AS |
4421 | |
4422 | operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); | |
4423 | emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); | |
4424 | emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); | |
4023fb28 UW |
4425 | DONE; |
4426 | } | |
ec24698e UW |
4427 | }) |
4428 | ||
56477c21 AS |
4429 | ; |
4430 | ; extendhidi2 instruction pattern(s). | |
4431 | ; | |
4432 | ||
ec24698e | 4433 | (define_insn "*extendhidi2_extimm" |
963fc8d0 | 4434 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4435 | (sign_extend:DI (match_operand:HI 1 "general_operand" "d,T,b")))] |
9602b6a1 | 4436 | "TARGET_ZARCH && TARGET_EXTIMM" |
ec24698e UW |
4437 | "@ |
4438 | lghr\t%0,%1 | |
963fc8d0 AK |
4439 | lgh\t%0,%1 |
4440 | lghrl\t%0,%1" | |
4441 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4442 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4443 | (set_attr "cpu_facility" "extimm,extimm,z10") |
4444 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
4445 | |
4446 | (define_insn "*extendhidi2" | |
9db1d521 | 4447 | [(set (match_operand:DI 0 "register_operand" "=d") |
3e4be43f | 4448 | (sign_extend:DI (match_operand:HI 1 "memory_operand" "T")))] |
9602b6a1 | 4449 | "TARGET_ZARCH" |
d40c829f | 4450 | "lgh\t%0,%1" |
9381e3f1 WG |
4451 | [(set_attr "op_type" "RXY") |
4452 | (set_attr "z10prop" "z10_super_E1")]) | |
9db1d521 | 4453 | |
9db1d521 | 4454 | ; |
56477c21 | 4455 | ; extendhisi2 instruction pattern(s). |
9db1d521 HP |
4456 | ; |
4457 | ||
ec24698e | 4458 | (define_insn "*extendhisi2_extimm" |
963fc8d0 AK |
4459 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") |
4460 | (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] | |
ec24698e UW |
4461 | "TARGET_EXTIMM" |
4462 | "@ | |
4463 | lhr\t%0,%1 | |
4464 | lh\t%0,%1 | |
963fc8d0 AK |
4465 | lhy\t%0,%1 |
4466 | lhrl\t%0,%1" | |
4467 | [(set_attr "op_type" "RRE,RX,RXY,RIL") | |
4468 | (set_attr "type" "*,*,*,larl") | |
9381e3f1 WG |
4469 | (set_attr "cpu_facility" "extimm,extimm,extimm,z10") |
4470 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 4471 | |
4023fb28 | 4472 | (define_insn "*extendhisi2" |
d3632d41 UW |
4473 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
4474 | (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] | |
ec24698e | 4475 | "!TARGET_EXTIMM" |
d3632d41 | 4476 | "@ |
d40c829f UW |
4477 | lh\t%0,%1 |
4478 | lhy\t%0,%1" | |
9381e3f1 | 4479 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 4480 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 4481 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) |
9db1d521 | 4482 | |
56477c21 AS |
4483 | ; |
4484 | ; extendqi(si|di)2 instruction pattern(s). | |
4485 | ; | |
4486 | ||
43a09b63 | 4487 | ; lbr, lgbr, lb, lgb |
56477c21 AS |
4488 | (define_insn "*extendqi<mode>2_extimm" |
4489 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3e4be43f | 4490 | (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,T")))] |
ec24698e UW |
4491 | "TARGET_EXTIMM" |
4492 | "@ | |
56477c21 AS |
4493 | l<g>br\t%0,%1 |
4494 | l<g>b\t%0,%1" | |
9381e3f1 WG |
4495 | [(set_attr "op_type" "RRE,RXY") |
4496 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
ec24698e | 4497 | |
43a09b63 | 4498 | ; lb, lgb |
56477c21 AS |
4499 | (define_insn "*extendqi<mode>2" |
4500 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 4501 | (sign_extend:GPR (match_operand:QI 1 "memory_operand" "T")))] |
56477c21 AS |
4502 | "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" |
4503 | "l<g>b\t%0,%1" | |
9381e3f1 WG |
4504 | [(set_attr "op_type" "RXY") |
4505 | (set_attr "z10prop" "z10_super_E1")]) | |
d3632d41 | 4506 | |
56477c21 AS |
4507 | (define_insn_and_split "*extendqi<mode>2_short_displ" |
4508 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4509 | (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) | |
ae156f85 | 4510 | (clobber (reg:CC CC_REGNUM))] |
56477c21 | 4511 | "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" |
19796784 AK |
4512 | "#" |
4513 | "&& reload_completed" | |
4023fb28 | 4514 | [(parallel |
56477c21 | 4515 | [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) |
ae156f85 | 4516 | (clobber (reg:CC CC_REGNUM))]) |
4023fb28 | 4517 | (parallel |
56477c21 | 4518 | [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) |
ae156f85 | 4519 | (clobber (reg:CC CC_REGNUM))])] |
6fa05db6 AS |
4520 | { |
4521 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
f5541398 | 4522 | set_mem_size (operands[1], GET_MODE_SIZE (QImode)); |
2542ef05 | 4523 | operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT); |
6fa05db6 | 4524 | }) |
9db1d521 | 4525 | |
9db1d521 HP |
4526 | ; |
4527 | ; zero_extendsidi2 instruction pattern(s). | |
4528 | ; | |
4529 | ||
4023fb28 UW |
4530 | (define_expand "zero_extendsidi2" |
4531 | [(set (match_operand:DI 0 "register_operand" "") | |
4532 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] | |
4533 | "" | |
4023fb28 | 4534 | { |
9602b6a1 | 4535 | if (!TARGET_ZARCH) |
4023fb28 | 4536 | { |
c41c1387 | 4537 | emit_clobber (operands[0]); |
9f37ccb1 UW |
4538 | emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); |
4539 | emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); | |
4023fb28 UW |
4540 | DONE; |
4541 | } | |
ec24698e | 4542 | }) |
4023fb28 UW |
4543 | |
4544 | (define_insn "*zero_extendsidi2" | |
963fc8d0 | 4545 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
3e4be43f | 4546 | (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,T,b")))] |
9602b6a1 | 4547 | "TARGET_ZARCH" |
9db1d521 | 4548 | "@ |
d40c829f | 4549 | llgfr\t%0,%1 |
963fc8d0 AK |
4550 | llgf\t%0,%1 |
4551 | llgfrl\t%0,%1" | |
4552 | [(set_attr "op_type" "RRE,RXY,RIL") | |
4553 | (set_attr "type" "*,*,larl") | |
9381e3f1 WG |
4554 | (set_attr "cpu_facility" "*,*,z10") |
4555 | (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) | |
9db1d521 | 4556 | |
288e517f AK |
4557 | ; |
4558 | ; LLGT-type instructions (zero-extend from 31 bit to 64 bit). | |
4559 | ; | |
4560 | ||
d6083c7d UW |
4561 | (define_insn "*llgt_sidi" |
4562 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 4563 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) |
d6083c7d | 4564 | (const_int 2147483647)))] |
9602b6a1 | 4565 | "TARGET_ZARCH" |
d6083c7d | 4566 | "llgt\t%0,%1" |
9381e3f1 WG |
4567 | [(set_attr "op_type" "RXE") |
4568 | (set_attr "z10prop" "z10_super_E1")]) | |
d6083c7d UW |
4569 | |
4570 | (define_insn_and_split "*llgt_sidi_split" | |
4571 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 4572 | (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "T") 0) |
d6083c7d | 4573 | (const_int 2147483647))) |
ae156f85 | 4574 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 4575 | "TARGET_ZARCH" |
d6083c7d UW |
4576 | "#" |
4577 | "&& reload_completed" | |
4578 | [(set (match_dup 0) | |
4579 | (and:DI (subreg:DI (match_dup 1) 0) | |
4580 | (const_int 2147483647)))] | |
4581 | "") | |
4582 | ||
288e517f AK |
4583 | (define_insn "*llgt_sisi" |
4584 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
3e4be43f | 4585 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,T") |
288e517f | 4586 | (const_int 2147483647)))] |
c4d50129 | 4587 | "TARGET_ZARCH" |
288e517f AK |
4588 | "@ |
4589 | llgtr\t%0,%1 | |
4590 | llgt\t%0,%1" | |
9381e3f1 WG |
4591 | [(set_attr "op_type" "RRE,RXE") |
4592 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4593 | |
288e517f AK |
4594 | (define_insn "*llgt_didi" |
4595 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
4596 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") | |
4597 | (const_int 2147483647)))] | |
9602b6a1 | 4598 | "TARGET_ZARCH" |
288e517f AK |
4599 | "@ |
4600 | llgtr\t%0,%1 | |
4601 | llgt\t%0,%N1" | |
9381e3f1 WG |
4602 | [(set_attr "op_type" "RRE,RXE") |
4603 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
288e517f | 4604 | |
f19a9af7 | 4605 | (define_split |
9602b6a1 AK |
4606 | [(set (match_operand:DSI 0 "register_operand" "") |
4607 | (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") | |
f6ee577c | 4608 | (const_int 2147483647))) |
ae156f85 | 4609 | (clobber (reg:CC CC_REGNUM))] |
c4d50129 | 4610 | "TARGET_ZARCH && reload_completed" |
288e517f | 4611 | [(set (match_dup 0) |
9602b6a1 | 4612 | (and:DSI (match_dup 1) |
f6ee577c | 4613 | (const_int 2147483647)))] |
288e517f AK |
4614 | "") |
4615 | ||
9db1d521 | 4616 | ; |
56477c21 | 4617 | ; zero_extend(hi|qi)(si|di)2 instruction pattern(s). |
9db1d521 HP |
4618 | ; |
4619 | ||
56477c21 AS |
4620 | (define_expand "zero_extend<mode>di2" |
4621 | [(set (match_operand:DI 0 "register_operand" "") | |
4622 | (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] | |
4623 | "" | |
4624 | { | |
9602b6a1 | 4625 | if (!TARGET_ZARCH) |
56477c21 AS |
4626 | { |
4627 | rtx tmp = gen_reg_rtx (SImode); | |
4628 | emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); | |
4629 | emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); | |
4630 | DONE; | |
4631 | } | |
4632 | else if (!TARGET_EXTIMM) | |
4633 | { | |
2542ef05 | 4634 | rtx bitcount = GEN_INT (64 - <HQI:bitsize>); |
56477c21 AS |
4635 | operands[1] = gen_lowpart (DImode, operands[1]); |
4636 | emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); | |
4637 | emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); | |
4638 | DONE; | |
4639 | } | |
4640 | }) | |
4641 | ||
f6ee577c | 4642 | (define_expand "zero_extend<mode>si2" |
4023fb28 | 4643 | [(set (match_operand:SI 0 "register_operand" "") |
ec24698e | 4644 | (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] |
9db1d521 | 4645 | "" |
4023fb28 | 4646 | { |
ec24698e UW |
4647 | if (!TARGET_EXTIMM) |
4648 | { | |
4649 | operands[1] = gen_lowpart (SImode, operands[1]); | |
9381e3f1 | 4650 | emit_insn (gen_andsi3 (operands[0], operands[1], |
2542ef05 | 4651 | GEN_INT ((1 << <HQI:bitsize>) - 1))); |
ec24698e | 4652 | DONE; |
56477c21 | 4653 | } |
ec24698e UW |
4654 | }) |
4655 | ||
963fc8d0 AK |
4656 | ; llhrl, llghrl |
4657 | (define_insn "*zero_extendhi<mode>2_z10" | |
4658 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d") | |
3e4be43f | 4659 | (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,T,b")))] |
963fc8d0 AK |
4660 | "TARGET_Z10" |
4661 | "@ | |
4662 | ll<g>hr\t%0,%1 | |
4663 | ll<g>h\t%0,%1 | |
4664 | ll<g>hrl\t%0,%1" | |
4665 | [(set_attr "op_type" "RXY,RRE,RIL") | |
4666 | (set_attr "type" "*,*,larl") | |
9381e3f1 | 4667 | (set_attr "cpu_facility" "*,*,z10") |
729e750f | 4668 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) |
963fc8d0 | 4669 | |
43a09b63 | 4670 | ; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc |
56477c21 AS |
4671 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" |
4672 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
3e4be43f | 4673 | (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,T")))] |
ec24698e UW |
4674 | "TARGET_EXTIMM" |
4675 | "@ | |
56477c21 AS |
4676 | ll<g><hc>r\t%0,%1 |
4677 | ll<g><hc>\t%0,%1" | |
9381e3f1 WG |
4678 | [(set_attr "op_type" "RRE,RXY") |
4679 | (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) | |
9db1d521 | 4680 | |
43a09b63 | 4681 | ; llgh, llgc |
56477c21 AS |
4682 | (define_insn "*zero_extend<HQI:mode><GPR:mode>2" |
4683 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 4684 | (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "T")))] |
ec24698e | 4685 | "TARGET_ZARCH && !TARGET_EXTIMM" |
f6ee577c | 4686 | "llg<hc>\t%0,%1" |
9381e3f1 WG |
4687 | [(set_attr "op_type" "RXY") |
4688 | (set_attr "z10prop" "z10_fwd_A3")]) | |
cc7ab9b7 UW |
4689 | |
4690 | (define_insn_and_split "*zero_extendhisi2_31" | |
4691 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3e4be43f | 4692 | (zero_extend:SI (match_operand:HI 1 "s_operand" "S"))) |
ae156f85 | 4693 | (clobber (reg:CC CC_REGNUM))] |
f4f41b4e | 4694 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4695 | "#" |
4696 | "&& reload_completed" | |
4697 | [(set (match_dup 0) (const_int 0)) | |
4698 | (parallel | |
4699 | [(set (strict_low_part (match_dup 2)) (match_dup 1)) | |
ae156f85 | 4700 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 4701 | "operands[2] = gen_lowpart (HImode, operands[0]);") |
c7453384 | 4702 | |
cc7ab9b7 UW |
4703 | (define_insn_and_split "*zero_extendqisi2_31" |
4704 | [(set (match_operand:SI 0 "register_operand" "=&d") | |
3e4be43f | 4705 | (zero_extend:SI (match_operand:QI 1 "memory_operand" "T")))] |
9e8327e3 | 4706 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4707 | "#" |
4708 | "&& reload_completed" | |
4709 | [(set (match_dup 0) (const_int 0)) | |
4710 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4711 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
c7453384 | 4712 | |
9db1d521 HP |
4713 | ; |
4714 | ; zero_extendqihi2 instruction pattern(s). | |
4715 | ; | |
4716 | ||
9db1d521 HP |
4717 | (define_expand "zero_extendqihi2" |
4718 | [(set (match_operand:HI 0 "register_operand" "") | |
4023fb28 | 4719 | (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] |
ec24698e | 4720 | "TARGET_ZARCH && !TARGET_EXTIMM" |
9db1d521 | 4721 | { |
4023fb28 UW |
4722 | operands[1] = gen_lowpart (HImode, operands[1]); |
4723 | emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); | |
4724 | DONE; | |
ec24698e | 4725 | }) |
9db1d521 | 4726 | |
4023fb28 | 4727 | (define_insn "*zero_extendqihi2_64" |
9db1d521 | 4728 | [(set (match_operand:HI 0 "register_operand" "=d") |
3e4be43f | 4729 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] |
ec24698e | 4730 | "TARGET_ZARCH && !TARGET_EXTIMM" |
d40c829f | 4731 | "llgc\t%0,%1" |
9381e3f1 WG |
4732 | [(set_attr "op_type" "RXY") |
4733 | (set_attr "z10prop" "z10_fwd_A3")]) | |
9db1d521 | 4734 | |
cc7ab9b7 UW |
4735 | (define_insn_and_split "*zero_extendqihi2_31" |
4736 | [(set (match_operand:HI 0 "register_operand" "=&d") | |
3e4be43f | 4737 | (zero_extend:HI (match_operand:QI 1 "memory_operand" "T")))] |
9e8327e3 | 4738 | "!TARGET_ZARCH" |
cc7ab9b7 UW |
4739 | "#" |
4740 | "&& reload_completed" | |
4741 | [(set (match_dup 0) (const_int 0)) | |
4742 | (set (strict_low_part (match_dup 2)) (match_dup 1))] | |
b628bd8e | 4743 | "operands[2] = gen_lowpart (QImode, operands[0]);") |
cc7ab9b7 | 4744 | |
609e7e80 | 4745 | ; |
9751ad6e | 4746 | ; fixuns_trunc(dd|td|sf|df|tf)(si|di)2 expander |
609e7e80 AK |
4747 | ; |
4748 | ||
9751ad6e AK |
4749 | ; This is the only entry point for fixuns_trunc. It multiplexes the |
4750 | ; expansion to either the *_emu expanders below for pre z196 machines | |
4751 | ; or emits the default pattern otherwise. | |
4752 | (define_expand "fixuns_trunc<FP:mode><GPR:mode>2" | |
609e7e80 | 4753 | [(parallel |
9751ad6e AK |
4754 | [(set (match_operand:GPR 0 "register_operand" "") |
4755 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" ""))) | |
4756 | (unspec:GPR [(match_dup 2)] UNSPEC_ROUND) | |
65b1d8ea | 4757 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e | 4758 | "TARGET_HARD_FLOAT" |
609e7e80 | 4759 | { |
65b1d8ea AK |
4760 | if (!TARGET_Z196) |
4761 | { | |
9751ad6e AK |
4762 | /* We don't provide emulation for TD|DD->SI. */ |
4763 | if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT | |
4764 | && <GPR:MODE>mode == SImode) | |
4765 | FAIL; | |
4766 | emit_insn (gen_fixuns_trunc<FP:mode><GPR:mode>2_emu (operands[0], | |
4767 | operands[1])); | |
65b1d8ea AK |
4768 | DONE; |
4769 | } | |
9751ad6e AK |
4770 | |
4771 | if (GET_MODE_CLASS (<FP:MODE>mode) == MODE_DECIMAL_FLOAT) | |
4772 | operands[2] = GEN_INT (DFP_RND_TOWARD_0); | |
4773 | else | |
4774 | operands[2] = GEN_INT (BFP_RND_TOWARD_0); | |
609e7e80 AK |
4775 | }) |
4776 | ||
9751ad6e AK |
4777 | ; (sf|df|tf)->unsigned (si|di) |
4778 | ||
4779 | ; Emulate the unsigned conversion with the signed version for pre z196 | |
4780 | ; machines. | |
4781 | (define_expand "fixuns_trunc<BFP:mode><GPR:mode>2_emu" | |
4782 | [(parallel | |
4783 | [(set (match_operand:GPR 0 "register_operand" "") | |
4784 | (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) | |
4785 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) | |
4786 | (clobber (reg:CC CC_REGNUM))])] | |
4787 | "!TARGET_Z196 && TARGET_HARD_FLOAT" | |
4788 | { | |
4789 | rtx_code_label *label1 = gen_label_rtx (); | |
4790 | rtx_code_label *label2 = gen_label_rtx (); | |
4791 | rtx temp = gen_reg_rtx (<BFP:MODE>mode); | |
4792 | REAL_VALUE_TYPE cmp, sub; | |
4793 | ||
4794 | operands[1] = force_reg (<BFP:MODE>mode, operands[1]); | |
4795 | real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode); | |
4796 | real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode); | |
4797 | ||
4798 | emit_cmp_and_jump_insns (operands[1], | |
4799 | const_double_from_real_value (cmp, <BFP:MODE>mode), | |
4800 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4801 | emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], | |
4802 | const_double_from_real_value (sub, <BFP:MODE>mode))); | |
4803 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, | |
4804 | GEN_INT (BFP_RND_TOWARD_MINF))); | |
4805 | emit_jump (label2); | |
4806 | ||
4807 | emit_label (label1); | |
4808 | emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], | |
4809 | operands[1], | |
4810 | GEN_INT (BFP_RND_TOWARD_0))); | |
4811 | emit_label (label2); | |
4812 | DONE; | |
4813 | }) | |
4814 | ||
4815 | ; dd->unsigned di | |
4816 | ||
4817 | ; Emulate the unsigned conversion with the signed version for pre z196 | |
4818 | ; machines. | |
4819 | (define_expand "fixuns_truncdddi2_emu" | |
65b1d8ea AK |
4820 | [(parallel |
4821 | [(set (match_operand:DI 0 "register_operand" "") | |
9751ad6e | 4822 | (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) |
ae8e301e | 4823 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea AK |
4824 | (clobber (reg:CC CC_REGNUM))])] |
4825 | ||
9751ad6e | 4826 | "!TARGET_Z196 && TARGET_HARD_DFP" |
609e7e80 | 4827 | { |
9751ad6e AK |
4828 | rtx_code_label *label1 = gen_label_rtx (); |
4829 | rtx_code_label *label2 = gen_label_rtx (); | |
4830 | rtx temp = gen_reg_rtx (TDmode); | |
4831 | REAL_VALUE_TYPE cmp, sub; | |
4832 | ||
4833 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4834 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4835 | ||
4836 | /* 2^63 can't be represented as 64bit DFP number with full precision. The | |
4837 | solution is doing the check and the subtraction in TD mode and using a | |
4838 | TD -> DI convert afterwards. */ | |
4839 | emit_insn (gen_extendddtd2 (temp, operands[1])); | |
4840 | temp = force_reg (TDmode, temp); | |
4841 | emit_cmp_and_jump_insns (temp, | |
4842 | const_double_from_real_value (cmp, TDmode), | |
4843 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4844 | emit_insn (gen_subtd3 (temp, temp, | |
4845 | const_double_from_real_value (sub, TDmode))); | |
4846 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, | |
4847 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
4848 | emit_jump (label2); | |
4849 | ||
4850 | emit_label (label1); | |
4851 | emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], | |
4852 | GEN_INT (DFP_RND_TOWARD_0))); | |
4853 | emit_label (label2); | |
4854 | DONE; | |
609e7e80 | 4855 | }) |
cc7ab9b7 | 4856 | |
9751ad6e | 4857 | ; td->unsigned di |
9db1d521 | 4858 | |
9751ad6e AK |
4859 | ; Emulate the unsigned conversion with the signed version for pre z196 |
4860 | ; machines. | |
4861 | (define_expand "fixuns_trunctddi2_emu" | |
65b1d8ea | 4862 | [(parallel |
9751ad6e AK |
4863 | [(set (match_operand:DI 0 "register_operand" "") |
4864 | (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) | |
4865 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) | |
65b1d8ea | 4866 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e AK |
4867 | |
4868 | "!TARGET_Z196 && TARGET_HARD_DFP" | |
9db1d521 | 4869 | { |
9751ad6e AK |
4870 | rtx_code_label *label1 = gen_label_rtx (); |
4871 | rtx_code_label *label2 = gen_label_rtx (); | |
4872 | rtx temp = gen_reg_rtx (TDmode); | |
4873 | REAL_VALUE_TYPE cmp, sub; | |
4874 | ||
4875 | operands[1] = force_reg (TDmode, operands[1]); | |
4876 | decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ | |
4877 | decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ | |
4878 | ||
4879 | emit_cmp_and_jump_insns (operands[1], | |
4880 | const_double_from_real_value (cmp, TDmode), | |
4881 | LT, NULL_RTX, VOIDmode, 0, label1); | |
4882 | emit_insn (gen_subtd3 (temp, operands[1], | |
4883 | const_double_from_real_value (sub, TDmode))); | |
4884 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, | |
4885 | GEN_INT (DFP_RND_TOWARD_MINF))); | |
4886 | emit_jump (label2); | |
4887 | ||
4888 | emit_label (label1); | |
4889 | emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], | |
4890 | GEN_INT (DFP_RND_TOWARD_0))); | |
4891 | emit_label (label2); | |
4892 | DONE; | |
10bbf137 | 4893 | }) |
9db1d521 | 4894 | |
9751ad6e AK |
4895 | ; Just a dummy to make the code in the first expander a bit easier. |
4896 | (define_expand "fixuns_trunc<mode>si2_emu" | |
65b1d8ea AK |
4897 | [(parallel |
4898 | [(set (match_operand:SI 0 "register_operand" "") | |
4899 | (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) | |
9751ad6e | 4900 | (unspec:DI [(const_int DFP_RND_TOWARD_0)] UNSPEC_ROUND) |
65b1d8ea | 4901 | (clobber (reg:CC CC_REGNUM))])] |
9751ad6e AK |
4902 | |
4903 | "!TARGET_Z196 && TARGET_HARD_DFP" | |
4904 | { | |
4905 | FAIL; | |
4906 | }) | |
4907 | ||
65b1d8ea AK |
4908 | |
4909 | ; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. | |
4910 | ||
9751ad6e AK |
4911 | ; df -> unsigned di |
4912 | (define_insn "*fixuns_truncdfdi2_vx" | |
6e5b5de8 AK |
4913 | [(set (match_operand:DI 0 "register_operand" "=d,v") |
4914 | (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
4915 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
4916 | (clobber (reg:CC CC_REGNUM))] | |
9751ad6e AK |
4917 | "TARGET_VX && TARGET_HARD_FLOAT" |
4918 | "@ | |
4919 | clgdbr\t%0,%h2,%1,0 | |
4920 | wclgdb\t%v0,%v1,0,%h2" | |
4921 | [(set_attr "op_type" "RRF,VRR") | |
4922 | (set_attr "type" "ftoi")]) | |
6e5b5de8 | 4923 | |
9751ad6e | 4924 | ; (dd|td|sf|df|tf)->unsigned (di|si) |
65b1d8ea AK |
4925 | ; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr |
4926 | ; clfdtr, clfxtr, clgdtr, clgxtr | |
4927 | (define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" | |
6e5b5de8 AK |
4928 | [(set (match_operand:GPR 0 "register_operand" "=d") |
4929 | (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) | |
4930 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
65b1d8ea | 4931 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 | 4932 | "TARGET_Z196 && TARGET_HARD_FLOAT |
a579871b | 4933 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)" |
65b1d8ea AK |
4934 | "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" |
4935 | [(set_attr "op_type" "RRF") | |
4936 | (set_attr "type" "ftoi")]) | |
4937 | ||
b60cb710 AK |
4938 | (define_expand "fix_trunc<DSF:mode><GPR:mode>2" |
4939 | [(set (match_operand:GPR 0 "register_operand" "") | |
4940 | (fix:GPR (match_operand:DSF 1 "register_operand" "")))] | |
4941 | "TARGET_HARD_FLOAT" | |
9db1d521 | 4942 | { |
b60cb710 | 4943 | emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], |
ae8e301e | 4944 | GEN_INT (BFP_RND_TOWARD_0))); |
9db1d521 | 4945 | DONE; |
10bbf137 | 4946 | }) |
9db1d521 | 4947 | |
6e5b5de8 AK |
4948 | (define_insn "*fix_truncdfdi2_bfp_z13" |
4949 | [(set (match_operand:DI 0 "register_operand" "=d,v") | |
4950 | (fix:DI (match_operand:DF 1 "register_operand" "f,v"))) | |
4951 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) | |
4952 | (clobber (reg:CC CC_REGNUM))] | |
a579871b | 4953 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
4954 | "@ |
4955 | cgdbr\t%0,%h2,%1 | |
4956 | wcgdb\t%v0,%v1,0,%h2" | |
4957 | [(set_attr "op_type" "RRE,VRR") | |
4958 | (set_attr "type" "ftoi")]) | |
4959 | ||
43a09b63 | 4960 | ; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr |
6e5b5de8 AK |
4961 | (define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp" |
4962 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4963 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
4964 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
ae156f85 | 4965 | (clobber (reg:CC CC_REGNUM))] |
6e5b5de8 AK |
4966 | "TARGET_HARD_FLOAT |
4967 | && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)" | |
7b6baae1 | 4968 | "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" |
9db1d521 | 4969 | [(set_attr "op_type" "RRE") |
077dab3b | 4970 | (set_attr "type" "ftoi")]) |
9db1d521 | 4971 | |
6e5b5de8 AK |
4972 | (define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp" |
4973 | [(parallel | |
4974 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
4975 | (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) | |
4976 | (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4977 | (clobber (reg:CC CC_REGNUM))])] | |
4978 | "TARGET_HARD_FLOAT") | |
609e7e80 AK |
4979 | ; |
4980 | ; fix_trunc(td|dd)di2 instruction pattern(s). | |
4981 | ; | |
4982 | ||
99cd7dd0 AK |
4983 | (define_expand "fix_trunc<mode>di2" |
4984 | [(set (match_operand:DI 0 "register_operand" "") | |
4985 | (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] | |
9602b6a1 | 4986 | "TARGET_ZARCH && TARGET_HARD_DFP" |
99cd7dd0 AK |
4987 | { |
4988 | operands[1] = force_reg (<MODE>mode, operands[1]); | |
4989 | emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], | |
ae8e301e | 4990 | GEN_INT (DFP_RND_TOWARD_0))); |
99cd7dd0 AK |
4991 | DONE; |
4992 | }) | |
4993 | ||
609e7e80 | 4994 | ; cgxtr, cgdtr |
99cd7dd0 | 4995 | (define_insn "fix_trunc<DFP:mode>di2_dfp" |
609e7e80 AK |
4996 | [(set (match_operand:DI 0 "register_operand" "=d") |
4997 | (fix:DI (match_operand:DFP 1 "register_operand" "f"))) | |
4998 | (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) | |
4999 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 5000 | "TARGET_ZARCH && TARGET_HARD_DFP" |
609e7e80 AK |
5001 | "cg<DFP:xde>tr\t%0,%h2,%1" |
5002 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 5003 | (set_attr "type" "ftoidfp")]) |
609e7e80 AK |
5004 | |
5005 | ||
f61a2c7d AK |
5006 | ; |
5007 | ; fix_trunctf(si|di)2 instruction pattern(s). | |
5008 | ; | |
5009 | ||
5010 | (define_expand "fix_trunctf<mode>2" | |
5011 | [(parallel [(set (match_operand:GPR 0 "register_operand" "") | |
5012 | (fix:GPR (match_operand:TF 1 "register_operand" ""))) | |
ae8e301e | 5013 | (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) |
f61a2c7d | 5014 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5015 | "TARGET_HARD_FLOAT" |
142cd70f | 5016 | "") |
9db1d521 | 5017 | |
9db1d521 | 5018 | |
9db1d521 | 5019 | ; |
142cd70f | 5020 | ; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). |
9db1d521 HP |
5021 | ; |
5022 | ||
609e7e80 | 5023 | ; cxgbr, cdgbr, cegbr, cxgtr, cdgtr |
f5905b37 | 5024 | (define_insn "floatdi<mode>2" |
62d3f261 AK |
5025 | [(set (match_operand:FP 0 "register_operand" "=f,v") |
5026 | (float:FP (match_operand:DI 1 "register_operand" "d,v")))] | |
9602b6a1 | 5027 | "TARGET_ZARCH && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5028 | "@ |
5029 | c<xde>g<bt>r\t%0,%1 | |
5030 | wcdgb\t%v0,%v1,0,0" | |
5031 | [(set_attr "op_type" "RRE,VRR") | |
5032 | (set_attr "type" "itof<mode>" ) | |
285363a1 | 5033 | (set_attr "cpu_facility" "*,vx") |
62d3f261 | 5034 | (set_attr "enabled" "*,<DFDI>")]) |
9db1d521 | 5035 | |
43a09b63 | 5036 | ; cxfbr, cdfbr, cefbr |
142cd70f | 5037 | (define_insn "floatsi<mode>2" |
7b6baae1 AK |
5038 | [(set (match_operand:BFP 0 "register_operand" "=f") |
5039 | (float:BFP (match_operand:SI 1 "register_operand" "d")))] | |
142cd70f | 5040 | "TARGET_HARD_FLOAT" |
f61a2c7d AK |
5041 | "c<xde>fbr\t%0,%1" |
5042 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 5043 | (set_attr "type" "itof<mode>" )]) |
f61a2c7d | 5044 | |
65b1d8ea AK |
5045 | ; cxftr, cdftr |
5046 | (define_insn "floatsi<mode>2" | |
5047 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5048 | (float:DFP (match_operand:SI 1 "register_operand" "d")))] | |
5049 | "TARGET_Z196 && TARGET_HARD_FLOAT" | |
5050 | "c<xde>ftr\t%0,0,%1,0" | |
5051 | [(set_attr "op_type" "RRE") | |
5052 | (set_attr "type" "itof<mode>" )]) | |
5053 | ||
5054 | ; | |
5055 | ; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). | |
5056 | ; | |
5057 | ||
6e5b5de8 AK |
5058 | (define_insn "*floatunsdidf2_z13" |
5059 | [(set (match_operand:DF 0 "register_operand" "=f,v") | |
5060 | (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))] | |
a579871b | 5061 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5062 | "@ |
5063 | cdlgbr\t%0,0,%1,0 | |
5064 | wcdlgb\t%v0,%v1,0,0" | |
5065 | [(set_attr "op_type" "RRE,VRR") | |
5066 | (set_attr "type" "itofdf")]) | |
5067 | ||
65b1d8ea AK |
5068 | ; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr |
5069 | ; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr | |
6e5b5de8 AK |
5070 | (define_insn "*floatuns<GPR:mode><FP:mode>2" |
5071 | [(set (match_operand:FP 0 "register_operand" "=f") | |
5072 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] | |
5073 | "TARGET_Z196 && TARGET_HARD_FLOAT | |
5074 | && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)" | |
65b1d8ea AK |
5075 | "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" |
5076 | [(set_attr "op_type" "RRE") | |
6e5b5de8 AK |
5077 | (set_attr "type" "itof<FP:mode>")]) |
5078 | ||
5079 | (define_expand "floatuns<GPR:mode><FP:mode>2" | |
5080 | [(set (match_operand:FP 0 "register_operand" "") | |
5081 | (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))] | |
5082 | "TARGET_Z196 && TARGET_HARD_FLOAT") | |
f61a2c7d | 5083 | |
9db1d521 HP |
5084 | ; |
5085 | ; truncdfsf2 instruction pattern(s). | |
5086 | ; | |
5087 | ||
142cd70f | 5088 | (define_insn "truncdfsf2" |
6e5b5de8 AK |
5089 | [(set (match_operand:SF 0 "register_operand" "=f,v") |
5090 | (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))] | |
142cd70f | 5091 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5092 | "@ |
5093 | ledbr\t%0,%1 | |
5094 | wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed | |
5095 | ; According to BFP rounding mode | |
5096 | [(set_attr "op_type" "RRE,VRR") | |
5097 | (set_attr "type" "ftruncdf") | |
285363a1 | 5098 | (set_attr "cpu_facility" "*,vx")]) |
9db1d521 | 5099 | |
f61a2c7d | 5100 | ; |
142cd70f | 5101 | ; trunctf(df|sf)2 instruction pattern(s). |
f61a2c7d AK |
5102 | ; |
5103 | ||
142cd70f AK |
5104 | ; ldxbr, lexbr |
5105 | (define_insn "trunctf<mode>2" | |
5106 | [(set (match_operand:DSF 0 "register_operand" "=f") | |
5107 | (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) | |
f61a2c7d | 5108 | (clobber (match_scratch:TF 2 "=f"))] |
142cd70f AK |
5109 | "TARGET_HARD_FLOAT" |
5110 | "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" | |
f61a2c7d | 5111 | [(set_attr "length" "6") |
9381e3f1 | 5112 | (set_attr "type" "ftrunctf")]) |
f61a2c7d | 5113 | |
609e7e80 AK |
5114 | ; |
5115 | ; trunctddd2 and truncddsd2 instruction pattern(s). | |
5116 | ; | |
5117 | ||
432d4670 AK |
5118 | |
5119 | (define_expand "trunctddd2" | |
5120 | [(parallel | |
5121 | [(set (match_operand:DD 0 "register_operand" "") | |
5122 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) | |
5123 | (unspec:DI [(const_int DFP_RND_CURRENT)] UNSPEC_ROUND) | |
5124 | (clobber (scratch:TD))])] | |
5125 | "TARGET_HARD_DFP") | |
5126 | ||
5127 | (define_insn "*trunctddd2" | |
609e7e80 | 5128 | [(set (match_operand:DD 0 "register_operand" "=f") |
bf259a77 | 5129 | (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) |
432d4670 AK |
5130 | (unspec:DI [(match_operand:DI 2 "const_mask_operand" "I")] UNSPEC_ROUND) |
5131 | (clobber (match_scratch:TD 3 "=f"))] | |
fb068247 | 5132 | "TARGET_HARD_DFP" |
432d4670 | 5133 | "ldxtr\t%3,%2,%1,0\;ldr\t%0,%3" |
bf259a77 | 5134 | [(set_attr "length" "6") |
9381e3f1 | 5135 | (set_attr "type" "ftruncdd")]) |
609e7e80 AK |
5136 | |
5137 | (define_insn "truncddsd2" | |
5138 | [(set (match_operand:SD 0 "register_operand" "=f") | |
5139 | (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 5140 | "TARGET_HARD_DFP" |
609e7e80 AK |
5141 | "ledtr\t%0,0,%1,0" |
5142 | [(set_attr "op_type" "RRF") | |
9381e3f1 | 5143 | (set_attr "type" "ftruncsd")]) |
609e7e80 | 5144 | |
feade5a8 AK |
5145 | (define_expand "trunctdsd2" |
5146 | [(parallel | |
d5a216fa | 5147 | [(set (match_dup 2) |
feade5a8 | 5148 | (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) |
432d4670 | 5149 | (unspec:DI [(const_int DFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND) |
d5a216fa | 5150 | (clobber (match_scratch:TD 3 ""))]) |
feade5a8 | 5151 | (set (match_operand:SD 0 "register_operand" "") |
d5a216fa | 5152 | (float_truncate:SD (match_dup 2)))] |
feade5a8 AK |
5153 | "TARGET_HARD_DFP" |
5154 | { | |
d5a216fa | 5155 | operands[2] = gen_reg_rtx (DDmode); |
feade5a8 AK |
5156 | }) |
5157 | ||
9db1d521 | 5158 | ; |
142cd70f | 5159 | ; extend(sf|df)(df|tf)2 instruction pattern(s). |
f61a2c7d AK |
5160 | ; |
5161 | ||
6e5b5de8 AK |
5162 | (define_insn "*extendsfdf2_z13" |
5163 | [(set (match_operand:DF 0 "register_operand" "=f,f,v") | |
5164 | (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))] | |
a579871b | 5165 | "TARGET_VX && TARGET_HARD_FLOAT" |
6e5b5de8 AK |
5166 | "@ |
5167 | ldebr\t%0,%1 | |
5168 | ldeb\t%0,%1 | |
5169 | wldeb\t%v0,%v1" | |
5170 | [(set_attr "op_type" "RRE,RXE,VRR") | |
5171 | (set_attr "type" "fsimpdf, floaddf,fsimpdf")]) | |
5172 | ||
142cd70f | 5173 | ; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb |
6e5b5de8 AK |
5174 | (define_insn "*extend<DSF:mode><BFP:mode>2" |
5175 | [(set (match_operand:BFP 0 "register_operand" "=f,f") | |
142cd70f AK |
5176 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] |
5177 | "TARGET_HARD_FLOAT | |
6e5b5de8 AK |
5178 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode) |
5179 | && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)" | |
f61a2c7d | 5180 | "@ |
142cd70f AK |
5181 | l<BFP:xde><DSF:xde>br\t%0,%1 |
5182 | l<BFP:xde><DSF:xde>b\t%0,%1" | |
6e5b5de8 AK |
5183 | [(set_attr "op_type" "RRE,RXE") |
5184 | (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) | |
5185 | ||
5186 | (define_expand "extend<DSF:mode><BFP:mode>2" | |
5187 | [(set (match_operand:BFP 0 "register_operand" "") | |
5188 | (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))] | |
5189 | "TARGET_HARD_FLOAT | |
5190 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)") | |
f61a2c7d | 5191 | |
609e7e80 AK |
5192 | ; |
5193 | ; extendddtd2 and extendsddd2 instruction pattern(s). | |
5194 | ; | |
5195 | ||
5196 | (define_insn "extendddtd2" | |
5197 | [(set (match_operand:TD 0 "register_operand" "=f") | |
5198 | (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] | |
fb068247 | 5199 | "TARGET_HARD_DFP" |
609e7e80 AK |
5200 | "lxdtr\t%0,%1,0" |
5201 | [(set_attr "op_type" "RRF") | |
5202 | (set_attr "type" "fsimptf")]) | |
5203 | ||
5204 | (define_insn "extendsddd2" | |
5205 | [(set (match_operand:DD 0 "register_operand" "=f") | |
5206 | (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] | |
fb068247 | 5207 | "TARGET_HARD_DFP" |
609e7e80 AK |
5208 | "ldetr\t%0,%1,0" |
5209 | [(set_attr "op_type" "RRF") | |
5210 | (set_attr "type" "fsimptf")]) | |
9db1d521 | 5211 | |
feade5a8 AK |
5212 | (define_expand "extendsdtd2" |
5213 | [(set (match_dup 2) | |
5214 | (float_extend:DD (match_operand:SD 1 "register_operand" ""))) | |
5215 | (set (match_operand:TD 0 "register_operand" "") | |
5216 | (float_extend:TD (match_dup 2)))] | |
5217 | "TARGET_HARD_DFP" | |
5218 | { | |
5219 | operands[2] = gen_reg_rtx (DDmode); | |
5220 | }) | |
5221 | ||
d12a76f3 AK |
5222 | ; Binary Floating Point - load fp integer |
5223 | ||
5224 | ; Expanders for: floor, btrunc, round, ceil, and nearbyint | |
5225 | ; For all of them the inexact exceptions are suppressed. | |
5226 | ||
5227 | ; fiebra, fidbra, fixbra | |
5228 | (define_insn "<FPINT:fpint_name><BFP:mode>2" | |
5229 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
5230 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
5231 | FPINT))] | |
5232 | "TARGET_Z196" | |
5233 | "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
5234 | [(set_attr "op_type" "RRF") | |
5235 | (set_attr "type" "fsimp<BFP:mode>")]) | |
5236 | ||
5237 | ; rint is supposed to raise an inexact exception so we can use the | |
5238 | ; older instructions. | |
5239 | ||
5240 | ; fiebr, fidbr, fixbr | |
5241 | (define_insn "rint<BFP:mode>2" | |
5242 | [(set (match_operand:BFP 0 "register_operand" "=f") | |
5243 | (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] | |
5244 | UNSPEC_FPINT_RINT))] | |
5245 | "" | |
5246 | "fi<BFP:xde>br\t%0,0,%1" | |
5247 | [(set_attr "op_type" "RRF") | |
5248 | (set_attr "type" "fsimp<BFP:mode>")]) | |
5249 | ||
5250 | ||
5251 | ; Decimal Floating Point - load fp integer | |
5252 | ||
5253 | ; fidtr, fixtr | |
5254 | (define_insn "<FPINT:fpint_name><DFP:mode>2" | |
5255 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5256 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5257 | FPINT))] | |
5258 | "TARGET_HARD_DFP" | |
5259 | "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4" | |
5260 | [(set_attr "op_type" "RRF") | |
5261 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5262 | ||
5263 | ; fidtr, fixtr | |
5264 | (define_insn "rint<DFP:mode>2" | |
5265 | [(set (match_operand:DFP 0 "register_operand" "=f") | |
5266 | (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] | |
5267 | UNSPEC_FPINT_RINT))] | |
5268 | "TARGET_HARD_DFP" | |
5269 | "fi<DFP:xde>tr\t%0,0,%1,0" | |
5270 | [(set_attr "op_type" "RRF") | |
5271 | (set_attr "type" "fsimp<DFP:mode>")]) | |
5272 | ||
5273 | ; | |
35dd9a0e AK |
5274 | ; Binary <-> Decimal floating point trunc patterns |
5275 | ; | |
5276 | ||
5277 | (define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" | |
5278 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5279 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5280 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5281 | (clobber (reg:CC CC_REGNUM)) |
5282 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5283 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5284 | "pfpo") |
5285 | ||
5286 | (define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" | |
5287 | [(set (reg:BFP FPR0_REGNUM) | |
2cf4c39e | 5288 | (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5289 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5290 | (clobber (reg:CC CC_REGNUM)) |
5291 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5292 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5293 | "pfpo") |
5294 | ||
5295 | (define_expand "trunc<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5296 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5297 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5298 | (parallel | |
5299 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5300 | (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5301 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5302 | (clobber (reg:CC CC_REGNUM)) |
5303 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5304 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5305 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5306 | "TARGET_HARD_DFP |
35dd9a0e AK |
5307 | && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5308 | { | |
5309 | HOST_WIDE_INT flags; | |
5310 | ||
5311 | flags = (PFPO_CONVERT | | |
5312 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5313 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5314 | ||
5315 | operands[2] = GEN_INT (flags); | |
5316 | }) | |
5317 | ||
5318 | (define_expand "trunc<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5319 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5320 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5321 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5322 | (parallel | |
2cf4c39e | 5323 | [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5324 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5325 | (clobber (reg:CC CC_REGNUM)) |
5326 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5327 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5328 | "TARGET_HARD_DFP |
35dd9a0e AK |
5329 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" |
5330 | { | |
5331 | HOST_WIDE_INT flags; | |
5332 | ||
5333 | flags = (PFPO_CONVERT | | |
5334 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5335 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5336 | ||
5337 | operands[2] = GEN_INT (flags); | |
5338 | }) | |
5339 | ||
5340 | ; | |
5341 | ; Binary <-> Decimal floating point extend patterns | |
5342 | ; | |
5343 | ||
5344 | (define_insn "*extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5345 | [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5346 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5347 | (clobber (reg:CC CC_REGNUM)) |
5348 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5349 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5350 | "pfpo") |
5351 | ||
5352 | (define_insn "*extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5353 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5354 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5355 | (clobber (reg:CC CC_REGNUM)) |
5356 | (clobber (reg:SI GPR1_REGNUM))] | |
fb068247 | 5357 | "TARGET_HARD_DFP" |
35dd9a0e AK |
5358 | "pfpo") |
5359 | ||
5360 | (define_expand "extend<BFP:mode><DFP_ALL:mode>2" | |
2cf4c39e | 5361 | [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) |
35dd9a0e AK |
5362 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) |
5363 | (parallel | |
5364 | [(set (reg:DFP_ALL FPR0_REGNUM) | |
2cf4c39e | 5365 | (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) |
35dd9a0e | 5366 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5367 | (clobber (reg:CC CC_REGNUM)) |
5368 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e AK |
5369 | (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") |
5370 | (reg:DFP_ALL FPR0_REGNUM))] | |
fb068247 | 5371 | "TARGET_HARD_DFP |
35dd9a0e AK |
5372 | && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" |
5373 | { | |
5374 | HOST_WIDE_INT flags; | |
5375 | ||
5376 | flags = (PFPO_CONVERT | | |
5377 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5378 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5379 | ||
5380 | operands[2] = GEN_INT (flags); | |
5381 | }) | |
5382 | ||
5383 | (define_expand "extend<DFP_ALL:mode><BFP:mode>2" | |
2cf4c39e | 5384 | [(set (reg:DFP_ALL FPR4_REGNUM) |
35dd9a0e AK |
5385 | (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) |
5386 | (set (reg:SI GPR0_REGNUM) (match_dup 2)) | |
5387 | (parallel | |
2cf4c39e | 5388 | [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) |
35dd9a0e | 5389 | (use (reg:SI GPR0_REGNUM)) |
af344a30 DV |
5390 | (clobber (reg:CC CC_REGNUM)) |
5391 | (clobber (reg:SI GPR1_REGNUM))]) | |
35dd9a0e | 5392 | (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] |
fb068247 | 5393 | "TARGET_HARD_DFP |
35dd9a0e AK |
5394 | && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" |
5395 | { | |
5396 | HOST_WIDE_INT flags; | |
5397 | ||
5398 | flags = (PFPO_CONVERT | | |
5399 | PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | | |
5400 | PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); | |
5401 | ||
5402 | operands[2] = GEN_INT (flags); | |
5403 | }) | |
5404 | ||
5405 | ||
9db1d521 | 5406 | ;; |
fae778eb | 5407 | ;; ARITHMETIC OPERATIONS |
9db1d521 | 5408 | ;; |
fae778eb | 5409 | ; arithmetic operations set the ConditionCode, |
9db1d521 HP |
5410 | ; because of unpredictable Bits in Register for Halfword and Byte |
5411 | ; the ConditionCode can be set wrong in operations for Halfword and Byte | |
5412 | ||
07893d4f UW |
5413 | ;; |
5414 | ;;- Add instructions. | |
5415 | ;; | |
5416 | ||
1c7b1b7e UW |
5417 | ; |
5418 | ; addti3 instruction pattern(s). | |
5419 | ; | |
5420 | ||
085261c8 AK |
5421 | (define_expand "addti3" |
5422 | [(parallel | |
5423 | [(set (match_operand:TI 0 "register_operand" "") | |
5424 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "") | |
5425 | (match_operand:TI 2 "general_operand" "") ) ) | |
5426 | (clobber (reg:CC CC_REGNUM))])] | |
5427 | "TARGET_ZARCH" | |
5428 | { | |
5429 | /* For z13 we have vaq which doesn't set CC. */ | |
5430 | if (TARGET_VX) | |
5431 | { | |
5432 | emit_insn (gen_rtx_SET (operands[0], | |
5433 | gen_rtx_PLUS (TImode, | |
5434 | copy_to_mode_reg (TImode, operands[1]), | |
5435 | copy_to_mode_reg (TImode, operands[2])))); | |
5436 | DONE; | |
5437 | } | |
5438 | }) | |
5439 | ||
5440 | (define_insn_and_split "*addti3" | |
5441 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
1c7b1b7e | 5442 | (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") |
085261c8 | 5443 | (match_operand:TI 2 "general_operand" "do") ) ) |
ae156f85 | 5444 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5445 | "TARGET_ZARCH" |
1c7b1b7e UW |
5446 | "#" |
5447 | "&& reload_completed" | |
5448 | [(parallel | |
ae156f85 | 5449 | [(set (reg:CCL1 CC_REGNUM) |
1c7b1b7e UW |
5450 | (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) |
5451 | (match_dup 7))) | |
5452 | (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) | |
5453 | (parallel | |
a94a76a7 UW |
5454 | [(set (match_dup 3) (plus:DI |
5455 | (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5456 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5457 | (clobber (reg:CC CC_REGNUM))])] |
1c7b1b7e UW |
5458 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5459 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5460 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5461 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5462 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5463 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5464 | [(set_attr "op_type" "*") | |
5465 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 5466 | |
07893d4f UW |
5467 | ; |
5468 | ; adddi3 instruction pattern(s). | |
5469 | ; | |
5470 | ||
3298c037 AK |
5471 | (define_expand "adddi3" |
5472 | [(parallel | |
963fc8d0 | 5473 | [(set (match_operand:DI 0 "nonimmediate_operand" "") |
3298c037 AK |
5474 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") |
5475 | (match_operand:DI 2 "general_operand" ""))) | |
5476 | (clobber (reg:CC CC_REGNUM))])] | |
5477 | "" | |
5478 | "") | |
5479 | ||
07893d4f UW |
5480 | (define_insn "*adddi3_sign" |
5481 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 5482 | (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 5483 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5484 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5485 | "TARGET_ZARCH" |
07893d4f | 5486 | "@ |
d40c829f UW |
5487 | agfr\t%0,%2 |
5488 | agf\t%0,%2" | |
65b1d8ea AK |
5489 | [(set_attr "op_type" "RRE,RXY") |
5490 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) | |
07893d4f UW |
5491 | |
5492 | (define_insn "*adddi3_zero_cc" | |
ae156f85 | 5493 | [(set (reg CC_REGNUM) |
3e4be43f | 5494 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f UW |
5495 | (match_operand:DI 1 "register_operand" "0,0")) |
5496 | (const_int 0))) | |
5497 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5498 | (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] | |
9602b6a1 | 5499 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5500 | "@ |
d40c829f UW |
5501 | algfr\t%0,%2 |
5502 | algf\t%0,%2" | |
9381e3f1 WG |
5503 | [(set_attr "op_type" "RRE,RXY") |
5504 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5505 | |
5506 | (define_insn "*adddi3_zero_cconly" | |
ae156f85 | 5507 | [(set (reg CC_REGNUM) |
3e4be43f | 5508 | (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f UW |
5509 | (match_operand:DI 1 "register_operand" "0,0")) |
5510 | (const_int 0))) | |
5511 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 5512 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5513 | "@ |
d40c829f UW |
5514 | algfr\t%0,%2 |
5515 | algf\t%0,%2" | |
9381e3f1 WG |
5516 | [(set_attr "op_type" "RRE,RXY") |
5517 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f UW |
5518 | |
5519 | (define_insn "*adddi3_zero" | |
5520 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 5521 | (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 5522 | (match_operand:DI 1 "register_operand" "0,0"))) |
ae156f85 | 5523 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5524 | "TARGET_ZARCH" |
07893d4f | 5525 | "@ |
d40c829f UW |
5526 | algfr\t%0,%2 |
5527 | algf\t%0,%2" | |
9381e3f1 WG |
5528 | [(set_attr "op_type" "RRE,RXY") |
5529 | (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) | |
07893d4f | 5530 | |
e69166de | 5531 | (define_insn_and_split "*adddi3_31z" |
963fc8d0 | 5532 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
e69166de UW |
5533 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
5534 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 5535 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5536 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
5537 | "#" |
5538 | "&& reload_completed" | |
5539 | [(parallel | |
ae156f85 | 5540 | [(set (reg:CCL1 CC_REGNUM) |
e69166de UW |
5541 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5542 | (match_dup 7))) | |
5543 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5544 | (parallel | |
a94a76a7 UW |
5545 | [(set (match_dup 3) (plus:SI |
5546 | (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) | |
5547 | (match_dup 4)) (match_dup 5))) | |
ae156f85 | 5548 | (clobber (reg:CC CC_REGNUM))])] |
e69166de UW |
5549 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5550 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5551 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5552 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5553 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 5554 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 5555 | |
07893d4f | 5556 | (define_insn_and_split "*adddi3_31" |
963fc8d0 | 5557 | [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") |
96fd3851 | 5558 | (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") |
97c6f7ad | 5559 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 5560 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 5561 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
5562 | "#" |
5563 | "&& reload_completed" | |
5564 | [(parallel | |
5565 | [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 5566 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5567 | (parallel |
ae156f85 | 5568 | [(set (reg:CCL1 CC_REGNUM) |
07893d4f UW |
5569 | (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) |
5570 | (match_dup 7))) | |
5571 | (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) | |
5572 | (set (pc) | |
ae156f85 | 5573 | (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) |
07893d4f UW |
5574 | (pc) |
5575 | (label_ref (match_dup 9)))) | |
5576 | (parallel | |
5577 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) | |
ae156f85 | 5578 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 5579 | (match_dup 9)] |
97c6f7ad UW |
5580 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
5581 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
5582 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
5583 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
5584 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
5585 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 5586 | operands[9] = gen_label_rtx ();") |
9db1d521 | 5587 | |
3298c037 AK |
5588 | ; |
5589 | ; addsi3 instruction pattern(s). | |
5590 | ; | |
5591 | ||
5592 | (define_expand "addsi3" | |
07893d4f | 5593 | [(parallel |
963fc8d0 | 5594 | [(set (match_operand:SI 0 "nonimmediate_operand" "") |
3298c037 AK |
5595 | (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") |
5596 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 5597 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 5598 | "" |
07893d4f | 5599 | "") |
9db1d521 | 5600 | |
3298c037 AK |
5601 | (define_insn "*addsi3_sign" |
5602 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
5603 | (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
5604 | (match_operand:SI 1 "register_operand" "0,0"))) | |
5605 | (clobber (reg:CC CC_REGNUM))] | |
5606 | "" | |
5607 | "@ | |
5608 | ah\t%0,%2 | |
5609 | ahy\t%0,%2" | |
65b1d8ea | 5610 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 5611 | (set_attr "cpu_facility" "*,longdisp") |
65b1d8ea | 5612 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) |
3298c037 | 5613 | |
9db1d521 | 5614 | ; |
3298c037 | 5615 | ; add(di|si)3 instruction pattern(s). |
9db1d521 | 5616 | ; |
9db1d521 | 5617 | |
65b1d8ea | 5618 | ; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi |
3298c037 | 5619 | (define_insn "*add<mode>3" |
3e4be43f UW |
5620 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,S") |
5621 | (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0,0") | |
5622 | (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T,C") ) ) | |
3298c037 AK |
5623 | (clobber (reg:CC CC_REGNUM))] |
5624 | "" | |
ec24698e | 5625 | "@ |
3298c037 | 5626 | a<g>r\t%0,%2 |
65b1d8ea | 5627 | a<g>rk\t%0,%1,%2 |
3298c037 | 5628 | a<g>hi\t%0,%h2 |
65b1d8ea | 5629 | a<g>hik\t%0,%1,%h2 |
3298c037 AK |
5630 | al<g>fi\t%0,%2 |
5631 | sl<g>fi\t%0,%n2 | |
5632 | a<g>\t%0,%2 | |
963fc8d0 AK |
5633 | a<y>\t%0,%2 |
5634 | a<g>si\t%0,%c2" | |
65b1d8ea | 5635 | [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") |
3e4be43f | 5636 | (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,longdisp,z10") |
65b1d8ea AK |
5637 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, |
5638 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
0a3bdf9d | 5639 | |
65b1d8ea | 5640 | ; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik |
3298c037 | 5641 | (define_insn "*add<mode>3_carry1_cc" |
ae156f85 | 5642 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5643 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5644 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5645 | (match_dup 1))) |
65b1d8ea | 5646 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") |
3298c037 | 5647 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5648 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5649 | "@ |
3298c037 | 5650 | al<g>r\t%0,%2 |
65b1d8ea | 5651 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5652 | al<g>fi\t%0,%2 |
5653 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5654 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5655 | al<g>\t%0,%2 |
963fc8d0 AK |
5656 | al<y>\t%0,%2 |
5657 | al<g>si\t%0,%c2" | |
65b1d8ea | 5658 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5659 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5660 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, |
5661 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5662 | |
65b1d8ea | 5663 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5664 | (define_insn "*add<mode>3_carry1_cconly" |
ae156f85 | 5665 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5666 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5667 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5668 | (match_dup 1))) |
65b1d8ea | 5669 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5670 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5671 | "@ |
3298c037 | 5672 | al<g>r\t%0,%2 |
65b1d8ea | 5673 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5674 | al<g>\t%0,%2 |
5675 | al<y>\t%0,%2" | |
65b1d8ea | 5676 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5677 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5678 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5679 | |
65b1d8ea | 5680 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5681 | (define_insn "*add<mode>3_carry2_cc" |
ae156f85 | 5682 | [(set (reg CC_REGNUM) |
3e4be43f UW |
5683 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5684 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
07893d4f | 5685 | (match_dup 2))) |
3e4be43f | 5686 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") |
3298c037 | 5687 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5688 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5689 | "@ |
3298c037 | 5690 | al<g>r\t%0,%2 |
65b1d8ea | 5691 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5692 | al<g>fi\t%0,%2 |
5693 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5694 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5695 | al<g>\t%0,%2 |
963fc8d0 AK |
5696 | al<y>\t%0,%2 |
5697 | al<g>si\t%0,%c2" | |
65b1d8ea | 5698 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5699 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5700 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, |
5701 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
07893d4f | 5702 | |
65b1d8ea | 5703 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5704 | (define_insn "*add<mode>3_carry2_cconly" |
ae156f85 | 5705 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5706 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5707 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 5708 | (match_dup 2))) |
65b1d8ea | 5709 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5710 | "s390_match_ccmode (insn, CCL1mode)" |
07893d4f | 5711 | "@ |
3298c037 | 5712 | al<g>r\t%0,%2 |
65b1d8ea | 5713 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5714 | al<g>\t%0,%2 |
5715 | al<y>\t%0,%2" | |
65b1d8ea | 5716 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5717 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5718 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5719 | |
65b1d8ea | 5720 | ; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik |
3298c037 | 5721 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5722 | [(set (reg CC_REGNUM) |
3e4be43f UW |
5723 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") |
5724 | (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) | |
9db1d521 | 5725 | (const_int 0))) |
3e4be43f | 5726 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,S") |
3298c037 | 5727 | (plus:GPR (match_dup 1) (match_dup 2)))] |
c7453384 | 5728 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5729 | "@ |
3298c037 | 5730 | al<g>r\t%0,%2 |
65b1d8ea | 5731 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5732 | al<g>fi\t%0,%2 |
5733 | sl<g>fi\t%0,%n2 | |
65b1d8ea | 5734 | al<g>hsik\t%0,%1,%h2 |
3298c037 | 5735 | al<g>\t%0,%2 |
963fc8d0 AK |
5736 | al<y>\t%0,%2 |
5737 | al<g>si\t%0,%c2" | |
65b1d8ea | 5738 | [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") |
3e4be43f | 5739 | (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,longdisp,z10") |
65b1d8ea AK |
5740 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, |
5741 | *,z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5742 | |
65b1d8ea | 5743 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5744 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5745 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5746 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5747 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 5748 | (const_int 0))) |
65b1d8ea | 5749 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
c7453384 | 5750 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 5751 | "@ |
3298c037 | 5752 | al<g>r\t%0,%2 |
65b1d8ea | 5753 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5754 | al<g>\t%0,%2 |
5755 | al<y>\t%0,%2" | |
65b1d8ea | 5756 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5757 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5758 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
9db1d521 | 5759 | |
65b1d8ea | 5760 | ; alr, al, aly, algr, alg, alrk, algrk |
3298c037 | 5761 | (define_insn "*add<mode>3_cconly2" |
ae156f85 | 5762 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
5763 | (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") |
5764 | (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) | |
5765 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
3298c037 | 5766 | "s390_match_ccmode(insn, CCLmode)" |
d3632d41 | 5767 | "@ |
3298c037 | 5768 | al<g>r\t%0,%2 |
65b1d8ea | 5769 | al<g>rk\t%0,%1,%2 |
3298c037 AK |
5770 | al<g>\t%0,%2 |
5771 | al<y>\t%0,%2" | |
65b1d8ea | 5772 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 5773 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 5774 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 5775 | |
963fc8d0 | 5776 | ; ahi, afi, aghi, agfi, asi, agsi |
3298c037 AK |
5777 | (define_insn "*add<mode>3_imm_cc" |
5778 | [(set (reg CC_REGNUM) | |
65b1d8ea | 5779 | (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") |
3e4be43f | 5780 | (match_operand:GPR 2 "const_int_operand" " K, K,Os,C")) |
3298c037 | 5781 | (const_int 0))) |
3e4be43f | 5782 | (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d, S") |
3298c037 AK |
5783 | (plus:GPR (match_dup 1) (match_dup 2)))] |
5784 | "s390_match_ccmode (insn, CCAmode) | |
5785 | && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") | |
2542ef05 RH |
5786 | || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") |
5787 | /* Avoid INT32_MIN on 32 bit. */ | |
5788 | && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" | |
9db1d521 | 5789 | "@ |
3298c037 | 5790 | a<g>hi\t%0,%h2 |
65b1d8ea | 5791 | a<g>hik\t%0,%1,%h2 |
963fc8d0 AK |
5792 | a<g>fi\t%0,%2 |
5793 | a<g>si\t%0,%c2" | |
65b1d8ea AK |
5794 | [(set_attr "op_type" "RI,RIE,RIL,SIY") |
5795 | (set_attr "cpu_facility" "*,z196,extimm,z10") | |
5796 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 5797 | |
9db1d521 | 5798 | ; |
609e7e80 | 5799 | ; add(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
5800 | ; |
5801 | ||
609e7e80 | 5802 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
6e5b5de8 | 5803 | ; FIXME: wfadb does not clobber cc |
142cd70f | 5804 | (define_insn "add<mode>3" |
62d3f261 AK |
5805 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v") |
5806 | (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v") | |
5807 | (match_operand:FP 2 "general_operand" "f,f,R,v"))) | |
ae156f85 | 5808 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 5809 | "TARGET_HARD_FLOAT" |
9db1d521 | 5810 | "@ |
62d3f261 AK |
5811 | a<xde>tr\t%0,%1,%2 |
5812 | a<xde>br\t%0,%2 | |
6e5b5de8 AK |
5813 | a<xde>b\t%0,%2 |
5814 | wfadb\t%v0,%v1,%v2" | |
62d3f261 | 5815 | [(set_attr "op_type" "RRF,RRE,RXE,VRR") |
6e5b5de8 | 5816 | (set_attr "type" "fsimp<mode>") |
285363a1 | 5817 | (set_attr "cpu_facility" "*,*,*,vx") |
62d3f261 | 5818 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")]) |
9db1d521 | 5819 | |
609e7e80 | 5820 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5821 | (define_insn "*add<mode>3_cc" |
ae156f85 | 5822 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5823 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
5824 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5825 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5826 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 5827 | (plus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 5828 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5829 | "@ |
62d3f261 AK |
5830 | a<xde>tr\t%0,%1,%2 |
5831 | a<xde>br\t%0,%2 | |
f61a2c7d | 5832 | a<xde>b\t%0,%2" |
62d3f261 AK |
5833 | [(set_attr "op_type" "RRF,RRE,RXE") |
5834 | (set_attr "type" "fsimp<mode>") | |
5835 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5836 | |
609e7e80 | 5837 | ; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr |
f5905b37 | 5838 | (define_insn "*add<mode>3_cconly" |
ae156f85 | 5839 | [(set (reg CC_REGNUM) |
62d3f261 AK |
5840 | (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0") |
5841 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 5842 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 5843 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 5844 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 5845 | "@ |
62d3f261 AK |
5846 | a<xde>tr\t%0,%1,%2 |
5847 | a<xde>br\t%0,%2 | |
f61a2c7d | 5848 | a<xde>b\t%0,%2" |
62d3f261 AK |
5849 | [(set_attr "op_type" "RRF,RRE,RXE") |
5850 | (set_attr "type" "fsimp<mode>") | |
5851 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 5852 | |
72a4ddf2 AK |
5853 | ; |
5854 | ; Pointer add instruction patterns | |
5855 | ; | |
5856 | ||
5857 | ; This will match "*la_64" | |
5858 | (define_expand "addptrdi3" | |
5859 | [(set (match_operand:DI 0 "register_operand" "") | |
5860 | (plus:DI (match_operand:DI 1 "register_operand" "") | |
5861 | (match_operand:DI 2 "nonmemory_operand" "")))] | |
5862 | "TARGET_64BIT" | |
5863 | { | |
72a4ddf2 AK |
5864 | if (GET_CODE (operands[2]) == CONST_INT) |
5865 | { | |
357ddc7d TV |
5866 | HOST_WIDE_INT c = INTVAL (operands[2]); |
5867 | ||
72a4ddf2 AK |
5868 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
5869 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
5870 | { | |
5871 | operands[2] = force_const_mem (DImode, operands[2]); | |
5872 | operands[2] = force_reg (DImode, operands[2]); | |
5873 | } | |
5874 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
5875 | operands[2] = force_reg (DImode, operands[2]); | |
5876 | } | |
5877 | }) | |
5878 | ||
5879 | ; For 31 bit we have to prevent the generated pattern from matching | |
5880 | ; normal ADDs since la only does a 31 bit add. This is supposed to | |
5881 | ; match "force_la_31". | |
5882 | (define_expand "addptrsi3" | |
5883 | [(parallel | |
5884 | [(set (match_operand:SI 0 "register_operand" "") | |
5885 | (plus:SI (match_operand:SI 1 "register_operand" "") | |
5886 | (match_operand:SI 2 "nonmemory_operand" ""))) | |
5887 | (use (const_int 0))])] | |
5888 | "!TARGET_64BIT" | |
5889 | { | |
72a4ddf2 AK |
5890 | if (GET_CODE (operands[2]) == CONST_INT) |
5891 | { | |
357ddc7d TV |
5892 | HOST_WIDE_INT c = INTVAL (operands[2]); |
5893 | ||
72a4ddf2 AK |
5894 | if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") |
5895 | && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) | |
5896 | { | |
5897 | operands[2] = force_const_mem (SImode, operands[2]); | |
5898 | operands[2] = force_reg (SImode, operands[2]); | |
5899 | } | |
5900 | else if (!DISP_IN_RANGE (INTVAL (operands[2]))) | |
5901 | operands[2] = force_reg (SImode, operands[2]); | |
5902 | } | |
5903 | }) | |
9db1d521 HP |
5904 | |
5905 | ;; | |
5906 | ;;- Subtract instructions. | |
5907 | ;; | |
5908 | ||
1c7b1b7e UW |
5909 | ; |
5910 | ; subti3 instruction pattern(s). | |
5911 | ; | |
5912 | ||
085261c8 AK |
5913 | (define_expand "subti3" |
5914 | [(parallel | |
5915 | [(set (match_operand:TI 0 "register_operand" "") | |
5916 | (minus:TI (match_operand:TI 1 "register_operand" "") | |
5917 | (match_operand:TI 2 "general_operand" "") ) ) | |
5918 | (clobber (reg:CC CC_REGNUM))])] | |
5919 | "TARGET_ZARCH" | |
5920 | { | |
2d71f118 | 5921 | /* For z13 we have vsq which doesn't set CC. */ |
085261c8 AK |
5922 | if (TARGET_VX) |
5923 | { | |
5924 | emit_insn (gen_rtx_SET (operands[0], | |
5925 | gen_rtx_MINUS (TImode, | |
5926 | operands[1], | |
5927 | copy_to_mode_reg (TImode, operands[2])))); | |
5928 | DONE; | |
5929 | } | |
5930 | }) | |
5931 | ||
5932 | (define_insn_and_split "*subti3" | |
5933 | [(set (match_operand:TI 0 "register_operand" "=&d") | |
5934 | (minus:TI (match_operand:TI 1 "register_operand" "0") | |
5935 | (match_operand:TI 2 "general_operand" "do") ) ) | |
ae156f85 | 5936 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5937 | "TARGET_ZARCH" |
1c7b1b7e UW |
5938 | "#" |
5939 | "&& reload_completed" | |
5940 | [(parallel | |
ae156f85 | 5941 | [(set (reg:CCL2 CC_REGNUM) |
1c7b1b7e UW |
5942 | (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) |
5943 | (match_dup 7))) | |
5944 | (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) | |
5945 | (parallel | |
5946 | [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
5947 | (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
5948 | (clobber (reg:CC CC_REGNUM))])] | |
1c7b1b7e UW |
5949 | "operands[3] = operand_subword (operands[0], 0, 0, TImode); |
5950 | operands[4] = operand_subword (operands[1], 0, 0, TImode); | |
5951 | operands[5] = operand_subword (operands[2], 0, 0, TImode); | |
5952 | operands[6] = operand_subword (operands[0], 1, 0, TImode); | |
5953 | operands[7] = operand_subword (operands[1], 1, 0, TImode); | |
085261c8 AK |
5954 | operands[8] = operand_subword (operands[2], 1, 0, TImode);" |
5955 | [(set_attr "op_type" "*") | |
5956 | (set_attr "cpu_facility" "*")]) | |
1c7b1b7e | 5957 | |
9db1d521 HP |
5958 | ; |
5959 | ; subdi3 instruction pattern(s). | |
5960 | ; | |
5961 | ||
3298c037 AK |
5962 | (define_expand "subdi3" |
5963 | [(parallel | |
5964 | [(set (match_operand:DI 0 "register_operand" "") | |
5965 | (minus:DI (match_operand:DI 1 "register_operand" "") | |
5966 | (match_operand:DI 2 "general_operand" ""))) | |
5967 | (clobber (reg:CC CC_REGNUM))])] | |
5968 | "" | |
5969 | "") | |
5970 | ||
07893d4f UW |
5971 | (define_insn "*subdi3_sign" |
5972 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
5973 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3e4be43f | 5974 | (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) |
ae156f85 | 5975 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 5976 | "TARGET_ZARCH" |
07893d4f | 5977 | "@ |
d40c829f UW |
5978 | sgfr\t%0,%2 |
5979 | sgf\t%0,%2" | |
9381e3f1 | 5980 | [(set_attr "op_type" "RRE,RXY") |
65b1d8ea AK |
5981 | (set_attr "z10prop" "z10_c,*") |
5982 | (set_attr "z196prop" "z196_cracked")]) | |
07893d4f UW |
5983 | |
5984 | (define_insn "*subdi3_zero_cc" | |
ae156f85 | 5985 | [(set (reg CC_REGNUM) |
07893d4f | 5986 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 5987 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) |
07893d4f UW |
5988 | (const_int 0))) |
5989 | (set (match_operand:DI 0 "register_operand" "=d,d") | |
5990 | (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] | |
9602b6a1 | 5991 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 5992 | "@ |
d40c829f UW |
5993 | slgfr\t%0,%2 |
5994 | slgf\t%0,%2" | |
9381e3f1 WG |
5995 | [(set_attr "op_type" "RRE,RXY") |
5996 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
5997 | |
5998 | (define_insn "*subdi3_zero_cconly" | |
ae156f85 | 5999 | [(set (reg CC_REGNUM) |
07893d4f | 6000 | (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6001 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T"))) |
07893d4f UW |
6002 | (const_int 0))) |
6003 | (clobber (match_scratch:DI 0 "=d,d"))] | |
9602b6a1 | 6004 | "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" |
07893d4f | 6005 | "@ |
d40c829f UW |
6006 | slgfr\t%0,%2 |
6007 | slgf\t%0,%2" | |
9381e3f1 WG |
6008 | [(set_attr "op_type" "RRE,RXY") |
6009 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f UW |
6010 | |
6011 | (define_insn "*subdi3_zero" | |
6012 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
6013 | (minus:DI (match_operand:DI 1 "register_operand" "0,0") | |
3e4be43f | 6014 | (zero_extend:DI (match_operand:SI 2 "general_operand" "d,T")))) |
ae156f85 | 6015 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6016 | "TARGET_ZARCH" |
07893d4f | 6017 | "@ |
d40c829f UW |
6018 | slgfr\t%0,%2 |
6019 | slgf\t%0,%2" | |
9381e3f1 WG |
6020 | [(set_attr "op_type" "RRE,RXY") |
6021 | (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) | |
07893d4f | 6022 | |
e69166de UW |
6023 | (define_insn_and_split "*subdi3_31z" |
6024 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
6025 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
6026 | (match_operand:DI 2 "general_operand" "do") ) ) | |
ae156f85 | 6027 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 6028 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
e69166de UW |
6029 | "#" |
6030 | "&& reload_completed" | |
6031 | [(parallel | |
ae156f85 | 6032 | [(set (reg:CCL2 CC_REGNUM) |
e69166de UW |
6033 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
6034 | (match_dup 7))) | |
6035 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
6036 | (parallel | |
6037 | [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) | |
ae156f85 AS |
6038 | (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) |
6039 | (clobber (reg:CC CC_REGNUM))])] | |
e69166de UW |
6040 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
6041 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
6042 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
6043 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
6044 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
b628bd8e | 6045 | operands[8] = operand_subword (operands[2], 1, 0, DImode);") |
e69166de | 6046 | |
07893d4f UW |
6047 | (define_insn_and_split "*subdi3_31" |
6048 | [(set (match_operand:DI 0 "register_operand" "=&d") | |
6049 | (minus:DI (match_operand:DI 1 "register_operand" "0") | |
97c6f7ad | 6050 | (match_operand:DI 2 "general_operand" "do") ) ) |
ae156f85 | 6051 | (clobber (reg:CC CC_REGNUM))] |
e69166de | 6052 | "!TARGET_CPU_ZARCH" |
07893d4f UW |
6053 | "#" |
6054 | "&& reload_completed" | |
6055 | [(parallel | |
6056 | [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) | |
ae156f85 | 6057 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 6058 | (parallel |
ae156f85 | 6059 | [(set (reg:CCL2 CC_REGNUM) |
07893d4f UW |
6060 | (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) |
6061 | (match_dup 7))) | |
6062 | (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) | |
6063 | (set (pc) | |
ae156f85 | 6064 | (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) |
07893d4f UW |
6065 | (pc) |
6066 | (label_ref (match_dup 9)))) | |
6067 | (parallel | |
6068 | [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) | |
ae156f85 | 6069 | (clobber (reg:CC CC_REGNUM))]) |
07893d4f | 6070 | (match_dup 9)] |
97c6f7ad UW |
6071 | "operands[3] = operand_subword (operands[0], 0, 0, DImode); |
6072 | operands[4] = operand_subword (operands[1], 0, 0, DImode); | |
6073 | operands[5] = operand_subword (operands[2], 0, 0, DImode); | |
6074 | operands[6] = operand_subword (operands[0], 1, 0, DImode); | |
6075 | operands[7] = operand_subword (operands[1], 1, 0, DImode); | |
6076 | operands[8] = operand_subword (operands[2], 1, 0, DImode); | |
b628bd8e | 6077 | operands[9] = gen_label_rtx ();") |
07893d4f | 6078 | |
3298c037 AK |
6079 | ; |
6080 | ; subsi3 instruction pattern(s). | |
6081 | ; | |
6082 | ||
6083 | (define_expand "subsi3" | |
07893d4f | 6084 | [(parallel |
3298c037 AK |
6085 | [(set (match_operand:SI 0 "register_operand" "") |
6086 | (minus:SI (match_operand:SI 1 "register_operand" "") | |
6087 | (match_operand:SI 2 "general_operand" ""))) | |
ae156f85 | 6088 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 6089 | "" |
07893d4f | 6090 | "") |
9db1d521 | 6091 | |
3298c037 AK |
6092 | (define_insn "*subsi3_sign" |
6093 | [(set (match_operand:SI 0 "register_operand" "=d,d") | |
6094 | (minus:SI (match_operand:SI 1 "register_operand" "0,0") | |
6095 | (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) | |
6096 | (clobber (reg:CC CC_REGNUM))] | |
6097 | "" | |
6098 | "@ | |
6099 | sh\t%0,%2 | |
6100 | shy\t%0,%2" | |
65b1d8ea | 6101 | [(set_attr "op_type" "RX,RXY") |
3e4be43f | 6102 | (set_attr "cpu_facility" "*,longdisp") |
65b1d8ea | 6103 | (set_attr "z196prop" "z196_cracked,z196_cracked")]) |
3298c037 | 6104 | |
9db1d521 | 6105 | ; |
3298c037 | 6106 | ; sub(di|si)3 instruction pattern(s). |
9db1d521 HP |
6107 | ; |
6108 | ||
65b1d8ea | 6109 | ; sr, s, sy, sgr, sg, srk, sgrk |
3298c037 | 6110 | (define_insn "*sub<mode>3" |
65b1d8ea AK |
6111 | [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
6112 | (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") | |
6113 | (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) | |
3298c037 AK |
6114 | (clobber (reg:CC CC_REGNUM))] |
6115 | "" | |
6116 | "@ | |
6117 | s<g>r\t%0,%2 | |
65b1d8ea | 6118 | s<g>rk\t%0,%1,%2 |
3298c037 AK |
6119 | s<g>\t%0,%2 |
6120 | s<y>\t%0,%2" | |
65b1d8ea | 6121 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6122 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6123 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
3298c037 | 6124 | |
65b1d8ea | 6125 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6126 | (define_insn "*sub<mode>3_borrow_cc" |
ae156f85 | 6127 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6128 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6129 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 6130 | (match_dup 1))) |
65b1d8ea | 6131 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 6132 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 6133 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 6134 | "@ |
3298c037 | 6135 | sl<g>r\t%0,%2 |
65b1d8ea | 6136 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6137 | sl<g>\t%0,%2 |
6138 | sl<y>\t%0,%2" | |
65b1d8ea | 6139 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6140 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6141 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 6142 | |
65b1d8ea | 6143 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6144 | (define_insn "*sub<mode>3_borrow_cconly" |
ae156f85 | 6145 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6146 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6147 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
07893d4f | 6148 | (match_dup 1))) |
65b1d8ea | 6149 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 6150 | "s390_match_ccmode (insn, CCL2mode)" |
07893d4f | 6151 | "@ |
3298c037 | 6152 | sl<g>r\t%0,%2 |
65b1d8ea | 6153 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6154 | sl<g>\t%0,%2 |
6155 | sl<y>\t%0,%2" | |
65b1d8ea | 6156 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6157 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6158 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
07893d4f | 6159 | |
65b1d8ea | 6160 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6161 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 6162 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6163 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6164 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 6165 | (const_int 0))) |
65b1d8ea | 6166 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") |
3298c037 | 6167 | (minus:GPR (match_dup 1) (match_dup 2)))] |
b2ba71ca | 6168 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 6169 | "@ |
3298c037 | 6170 | sl<g>r\t%0,%2 |
65b1d8ea | 6171 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6172 | sl<g>\t%0,%2 |
6173 | sl<y>\t%0,%2" | |
65b1d8ea | 6174 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6175 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6176 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9db1d521 | 6177 | |
65b1d8ea | 6178 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6179 | (define_insn "*sub<mode>3_cc2" |
ae156f85 | 6180 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6181 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6182 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
6183 | (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") | |
3298c037 | 6184 | (minus:GPR (match_dup 1) (match_dup 2)))] |
5d880bd2 UW |
6185 | "s390_match_ccmode (insn, CCL3mode)" |
6186 | "@ | |
3298c037 | 6187 | sl<g>r\t%0,%2 |
65b1d8ea | 6188 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6189 | sl<g>\t%0,%2 |
6190 | sl<y>\t%0,%2" | |
65b1d8ea | 6191 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6192 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6193 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
5d880bd2 | 6194 | |
65b1d8ea | 6195 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6196 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6197 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6198 | (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6199 | (match_operand:GPR 2 "general_operand" "d,d,R,T")) | |
9db1d521 | 6200 | (const_int 0))) |
65b1d8ea | 6201 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] |
b2ba71ca | 6202 | "s390_match_ccmode (insn, CCLmode)" |
9db1d521 | 6203 | "@ |
3298c037 | 6204 | sl<g>r\t%0,%2 |
65b1d8ea | 6205 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6206 | sl<g>\t%0,%2 |
6207 | sl<y>\t%0,%2" | |
65b1d8ea | 6208 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6209 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6210 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9381e3f1 | 6211 | |
9db1d521 | 6212 | |
65b1d8ea | 6213 | ; slr, sl, sly, slgr, slg, slrk, slgrk |
3298c037 | 6214 | (define_insn "*sub<mode>3_cconly2" |
ae156f85 | 6215 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
6216 | (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") |
6217 | (match_operand:GPR 2 "general_operand" "d,d,R,T"))) | |
6218 | (clobber (match_scratch:GPR 0 "=d,d,d,d"))] | |
5d880bd2 UW |
6219 | "s390_match_ccmode (insn, CCL3mode)" |
6220 | "@ | |
3298c037 | 6221 | sl<g>r\t%0,%2 |
65b1d8ea | 6222 | sl<g>rk\t%0,%1,%2 |
3298c037 AK |
6223 | sl<g>\t%0,%2 |
6224 | sl<y>\t%0,%2" | |
65b1d8ea | 6225 | [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") |
3e4be43f | 6226 | (set_attr "cpu_facility" "*,z196,*,longdisp") |
65b1d8ea | 6227 | (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) |
9381e3f1 | 6228 | |
9db1d521 HP |
6229 | |
6230 | ; | |
609e7e80 | 6231 | ; sub(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6232 | ; |
6233 | ||
d46f24b6 | 6234 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
142cd70f | 6235 | (define_insn "sub<mode>3" |
62d3f261 AK |
6236 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v") |
6237 | (minus:FP (match_operand:FP 1 "register_operand" "f,0,0,v") | |
6238 | (match_operand:FP 2 "general_operand" "f,f,R,v"))) | |
ae156f85 | 6239 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 6240 | "TARGET_HARD_FLOAT" |
9db1d521 | 6241 | "@ |
62d3f261 AK |
6242 | s<xde>tr\t%0,%1,%2 |
6243 | s<xde>br\t%0,%2 | |
6e5b5de8 AK |
6244 | s<xde>b\t%0,%2 |
6245 | wfsdb\t%v0,%v1,%v2" | |
62d3f261 | 6246 | [(set_attr "op_type" "RRF,RRE,RXE,VRR") |
6e5b5de8 | 6247 | (set_attr "type" "fsimp<mode>") |
285363a1 | 6248 | (set_attr "cpu_facility" "*,*,*,vx") |
62d3f261 | 6249 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")]) |
9db1d521 | 6250 | |
d46f24b6 | 6251 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6252 | (define_insn "*sub<mode>3_cc" |
ae156f85 | 6253 | [(set (reg CC_REGNUM) |
62d3f261 AK |
6254 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
6255 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 6256 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6257 | (set (match_operand:FP 0 "register_operand" "=f,f,f") |
609e7e80 | 6258 | (minus:FP (match_dup 1) (match_dup 2)))] |
142cd70f | 6259 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6260 | "@ |
62d3f261 AK |
6261 | s<xde>tr\t%0,%1,%2 |
6262 | s<xde>br\t%0,%2 | |
f61a2c7d | 6263 | s<xde>b\t%0,%2" |
62d3f261 AK |
6264 | [(set_attr "op_type" "RRF,RRE,RXE") |
6265 | (set_attr "type" "fsimp<mode>") | |
6266 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6267 | |
d46f24b6 | 6268 | ; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr |
f5905b37 | 6269 | (define_insn "*sub<mode>3_cconly" |
ae156f85 | 6270 | [(set (reg CC_REGNUM) |
62d3f261 AK |
6271 | (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "f,0,0") |
6272 | (match_operand:FP 2 "general_operand" "f,f,R")) | |
609e7e80 | 6273 | (match_operand:FP 3 "const0_operand" ""))) |
62d3f261 | 6274 | (clobber (match_scratch:FP 0 "=f,f,f"))] |
142cd70f | 6275 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
3ef093a8 | 6276 | "@ |
62d3f261 AK |
6277 | s<xde>tr\t%0,%1,%2 |
6278 | s<xde>br\t%0,%2 | |
f61a2c7d | 6279 | s<xde>b\t%0,%2" |
62d3f261 AK |
6280 | [(set_attr "op_type" "RRF,RRE,RXE") |
6281 | (set_attr "type" "fsimp<mode>") | |
6282 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>")]) | |
3ef093a8 | 6283 | |
9db1d521 | 6284 | |
e69166de UW |
6285 | ;; |
6286 | ;;- Conditional add/subtract instructions. | |
6287 | ;; | |
6288 | ||
6289 | ; | |
9a91a21f | 6290 | ; add(di|si)cc instruction pattern(s). |
e69166de UW |
6291 | ; |
6292 | ||
a996720c UW |
6293 | ; the following 4 patterns are used when the result of an add with |
6294 | ; carry is checked for an overflow condition | |
6295 | ||
6296 | ; op1 + op2 + c < op1 | |
6297 | ||
6298 | ; alcr, alc, alcgr, alcg | |
6299 | (define_insn "*add<mode>3_alc_carry1_cc" | |
6300 | [(set (reg CC_REGNUM) | |
6301 | (compare | |
6302 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6303 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6304 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6305 | (match_dup 1))) |
6306 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6307 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
6308 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6309 | "@ | |
6310 | alc<g>r\t%0,%2 | |
6311 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6312 | [(set_attr "op_type" "RRE,RXY") |
6313 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6314 | |
6315 | ; alcr, alc, alcgr, alcg | |
6316 | (define_insn "*add<mode>3_alc_carry1_cconly" | |
6317 | [(set (reg CC_REGNUM) | |
6318 | (compare | |
6319 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6320 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6321 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6322 | (match_dup 1))) |
6323 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
6324 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6325 | "@ | |
6326 | alc<g>r\t%0,%2 | |
6327 | alc<g>\t%0,%2" | |
65b1d8ea AK |
6328 | [(set_attr "op_type" "RRE,RXY") |
6329 | (set_attr "z196prop" "z196_alone,z196_alone")]) | |
a996720c UW |
6330 | |
6331 | ; op1 + op2 + c < op2 | |
6332 | ||
6333 | ; alcr, alc, alcgr, alcg | |
6334 | (define_insn "*add<mode>3_alc_carry2_cc" | |
6335 | [(set (reg CC_REGNUM) | |
6336 | (compare | |
6337 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6338 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6339 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6340 | (match_dup 2))) |
6341 | (set (match_operand:GPR 0 "register_operand" "=d,d") | |
6342 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] | |
6343 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6344 | "@ | |
6345 | alc<g>r\t%0,%2 | |
6346 | alc<g>\t%0,%2" | |
6347 | [(set_attr "op_type" "RRE,RXY")]) | |
6348 | ||
6349 | ; alcr, alc, alcgr, alcg | |
6350 | (define_insn "*add<mode>3_alc_carry2_cconly" | |
6351 | [(set (reg CC_REGNUM) | |
6352 | (compare | |
6353 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") | |
6354 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6355 | (match_operand:GPR 2 "general_operand" "d,T")) |
a996720c UW |
6356 | (match_dup 2))) |
6357 | (clobber (match_scratch:GPR 0 "=d,d"))] | |
6358 | "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" | |
6359 | "@ | |
6360 | alc<g>r\t%0,%2 | |
6361 | alc<g>\t%0,%2" | |
6362 | [(set_attr "op_type" "RRE,RXY")]) | |
6363 | ||
43a09b63 | 6364 | ; alcr, alc, alcgr, alcg |
9a91a21f | 6365 | (define_insn "*add<mode>3_alc_cc" |
ae156f85 | 6366 | [(set (reg CC_REGNUM) |
e69166de | 6367 | (compare |
a94a76a7 UW |
6368 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6369 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6370 | (match_operand:GPR 2 "general_operand" "d,T")) |
e69166de | 6371 | (const_int 0))) |
9a91a21f | 6372 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
a94a76a7 | 6373 | (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] |
2f7e5a0d | 6374 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 6375 | "@ |
9a91a21f AS |
6376 | alc<g>r\t%0,%2 |
6377 | alc<g>\t%0,%2" | |
e69166de UW |
6378 | [(set_attr "op_type" "RRE,RXY")]) |
6379 | ||
43a09b63 | 6380 | ; alcr, alc, alcgr, alcg |
9a91a21f AS |
6381 | (define_insn "*add<mode>3_alc" |
6382 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
a94a76a7 UW |
6383 | (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") |
6384 | (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) | |
3e4be43f | 6385 | (match_operand:GPR 2 "general_operand" "d,T"))) |
ae156f85 | 6386 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 6387 | "TARGET_CPU_ZARCH" |
e69166de | 6388 | "@ |
9a91a21f AS |
6389 | alc<g>r\t%0,%2 |
6390 | alc<g>\t%0,%2" | |
e69166de UW |
6391 | [(set_attr "op_type" "RRE,RXY")]) |
6392 | ||
43a09b63 | 6393 | ; slbr, slb, slbgr, slbg |
9a91a21f | 6394 | (define_insn "*sub<mode>3_slb_cc" |
ae156f85 | 6395 | [(set (reg CC_REGNUM) |
e69166de | 6396 | (compare |
9a91a21f | 6397 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") |
3e4be43f | 6398 | (match_operand:GPR 2 "general_operand" "d,T")) |
9a91a21f | 6399 | (match_operand:GPR 3 "s390_slb_comparison" "")) |
e69166de | 6400 | (const_int 0))) |
9a91a21f AS |
6401 | (set (match_operand:GPR 0 "register_operand" "=d,d") |
6402 | (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] | |
2f7e5a0d | 6403 | "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" |
e69166de | 6404 | "@ |
9a91a21f AS |
6405 | slb<g>r\t%0,%2 |
6406 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6407 | [(set_attr "op_type" "RRE,RXY") |
6408 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6409 | |
43a09b63 | 6410 | ; slbr, slb, slbgr, slbg |
9a91a21f AS |
6411 | (define_insn "*sub<mode>3_slb" |
6412 | [(set (match_operand:GPR 0 "register_operand" "=d,d") | |
6413 | (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") | |
3e4be43f | 6414 | (match_operand:GPR 2 "general_operand" "d,T")) |
9a91a21f | 6415 | (match_operand:GPR 3 "s390_slb_comparison" ""))) |
ae156f85 | 6416 | (clobber (reg:CC CC_REGNUM))] |
2f7e5a0d | 6417 | "TARGET_CPU_ZARCH" |
e69166de | 6418 | "@ |
9a91a21f AS |
6419 | slb<g>r\t%0,%2 |
6420 | slb<g>\t%0,%2" | |
9381e3f1 WG |
6421 | [(set_attr "op_type" "RRE,RXY") |
6422 | (set_attr "z10prop" "z10_c,*")]) | |
e69166de | 6423 | |
9a91a21f AS |
6424 | (define_expand "add<mode>cc" |
6425 | [(match_operand:GPR 0 "register_operand" "") | |
5d880bd2 | 6426 | (match_operand 1 "comparison_operator" "") |
9a91a21f AS |
6427 | (match_operand:GPR 2 "register_operand" "") |
6428 | (match_operand:GPR 3 "const_int_operand" "")] | |
5d880bd2 | 6429 | "TARGET_CPU_ZARCH" |
9381e3f1 | 6430 | "if (!s390_expand_addcc (GET_CODE (operands[1]), |
f90b7a5a | 6431 | XEXP (operands[1], 0), XEXP (operands[1], 1), |
9381e3f1 | 6432 | operands[0], operands[2], |
5d880bd2 UW |
6433 | operands[3])) FAIL; DONE;") |
6434 | ||
6435 | ; | |
6436 | ; scond instruction pattern(s). | |
6437 | ; | |
6438 | ||
9a91a21f AS |
6439 | (define_insn_and_split "*scond<mode>" |
6440 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6441 | (match_operand:GPR 1 "s390_alc_comparison" "")) | |
ae156f85 | 6442 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
6443 | "TARGET_CPU_ZARCH" |
6444 | "#" | |
6445 | "&& reload_completed" | |
6446 | [(set (match_dup 0) (const_int 0)) | |
6447 | (parallel | |
a94a76a7 UW |
6448 | [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) |
6449 | (match_dup 0))) | |
ae156f85 | 6450 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6451 | "") |
5d880bd2 | 6452 | |
9a91a21f AS |
6453 | (define_insn_and_split "*scond<mode>_neg" |
6454 | [(set (match_operand:GPR 0 "register_operand" "=&d") | |
6455 | (match_operand:GPR 1 "s390_slb_comparison" "")) | |
ae156f85 | 6456 | (clobber (reg:CC CC_REGNUM))] |
5d880bd2 UW |
6457 | "TARGET_CPU_ZARCH" |
6458 | "#" | |
6459 | "&& reload_completed" | |
6460 | [(set (match_dup 0) (const_int 0)) | |
6461 | (parallel | |
9a91a21f AS |
6462 | [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) |
6463 | (match_dup 1))) | |
ae156f85 | 6464 | (clobber (reg:CC CC_REGNUM))]) |
5d880bd2 | 6465 | (parallel |
9a91a21f | 6466 | [(set (match_dup 0) (neg:GPR (match_dup 0))) |
ae156f85 | 6467 | (clobber (reg:CC CC_REGNUM))])] |
b628bd8e | 6468 | "") |
5d880bd2 | 6469 | |
5d880bd2 | 6470 | |
f90b7a5a | 6471 | (define_expand "cstore<mode>4" |
9a91a21f | 6472 | [(set (match_operand:SI 0 "register_operand" "") |
f90b7a5a PB |
6473 | (match_operator:SI 1 "s390_scond_operator" |
6474 | [(match_operand:GPR 2 "register_operand" "") | |
6475 | (match_operand:GPR 3 "general_operand" "")]))] | |
5d880bd2 | 6476 | "TARGET_CPU_ZARCH" |
f90b7a5a | 6477 | "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], |
5d880bd2 UW |
6478 | operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") |
6479 | ||
f90b7a5a | 6480 | (define_expand "cstorecc4" |
69950452 | 6481 | [(parallel |
f90b7a5a PB |
6482 | [(set (match_operand:SI 0 "register_operand" "") |
6483 | (match_operator:SI 1 "s390_eqne_operator" | |
6484 | [(match_operand:CCZ1 2 "register_operand") | |
6485 | (match_operand 3 "const0_operand")])) | |
69950452 AS |
6486 | (clobber (reg:CC CC_REGNUM))])] |
6487 | "" | |
f90b7a5a PB |
6488 | "emit_insn (gen_sne (operands[0], operands[2])); |
6489 | if (GET_CODE (operands[1]) == EQ) | |
6490 | emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); | |
6491 | DONE;") | |
69950452 | 6492 | |
f90b7a5a | 6493 | (define_insn_and_split "sne" |
69950452 | 6494 | [(set (match_operand:SI 0 "register_operand" "=d") |
9381e3f1 | 6495 | (ne:SI (match_operand:CCZ1 1 "register_operand" "0") |
69950452 AS |
6496 | (const_int 0))) |
6497 | (clobber (reg:CC CC_REGNUM))] | |
6498 | "" | |
6499 | "#" | |
6500 | "reload_completed" | |
6501 | [(parallel | |
6502 | [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) | |
6503 | (clobber (reg:CC CC_REGNUM))])]) | |
6504 | ||
e69166de | 6505 | |
65b1d8ea AK |
6506 | ;; |
6507 | ;; - Conditional move instructions (introduced with z196) | |
6508 | ;; | |
6509 | ||
6510 | (define_expand "mov<mode>cc" | |
6511 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
6512 | (if_then_else:GPR (match_operand 1 "comparison_operator" "") | |
6513 | (match_operand:GPR 2 "nonimmediate_operand" "") | |
6514 | (match_operand:GPR 3 "nonimmediate_operand" "")))] | |
6515 | "TARGET_Z196" | |
7477de01 AK |
6516 | { |
6517 | /* Emit the comparison insn in case we do not already have a comparison result. */ | |
6518 | if (!s390_comparison (operands[1], VOIDmode)) | |
6519 | operands[1] = s390_emit_compare (GET_CODE (operands[1]), | |
6520 | XEXP (operands[1], 0), | |
6521 | XEXP (operands[1], 1)); | |
6522 | }) | |
65b1d8ea | 6523 | |
bf749919 | 6524 | ; locr, loc, stoc, locgr, locg, stocg, lochi, locghi |
65b1d8ea | 6525 | (define_insn_and_split "*mov<mode>cc" |
bf749919 | 6526 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d,d,d,S,S,&d") |
65b1d8ea AK |
6527 | (if_then_else:GPR |
6528 | (match_operator 1 "s390_comparison" | |
bf749919 | 6529 | [(match_operand 2 "cc_reg_operand" " c,c,c,c,c,c,c,c,c") |
5a3fe9b6 | 6530 | (match_operand 5 "const_int_operand" "")]) |
bf749919 DV |
6531 | (match_operand:GPR 3 "loc_operand" " d,0,S,0,K,0,d,0,S") |
6532 | (match_operand:GPR 4 "loc_operand" " 0,d,0,S,0,K,0,d,S")))] | |
65b1d8ea AK |
6533 | "TARGET_Z196" |
6534 | "@ | |
6535 | loc<g>r%C1\t%0,%3 | |
6536 | loc<g>r%D1\t%0,%4 | |
a6510374 AK |
6537 | loc<g>%C1\t%0,%3 |
6538 | loc<g>%D1\t%0,%4 | |
bf749919 DV |
6539 | loc<g>hi%C1\t%0,%h3 |
6540 | loc<g>hi%D1\t%0,%h4 | |
a6510374 AK |
6541 | stoc<g>%C1\t%3,%0 |
6542 | stoc<g>%D1\t%4,%0 | |
65b1d8ea AK |
6543 | #" |
6544 | "&& reload_completed | |
6545 | && MEM_P (operands[3]) && MEM_P (operands[4])" | |
6546 | [(set (match_dup 0) | |
6547 | (if_then_else:GPR | |
6548 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
6549 | (match_dup 3) | |
6550 | (match_dup 0))) | |
6551 | (set (match_dup 0) | |
6552 | (if_then_else:GPR | |
6553 | (match_op_dup 1 [(match_dup 2) (const_int 0)]) | |
6554 | (match_dup 0) | |
6555 | (match_dup 4)))] | |
6556 | "" | |
bf749919 DV |
6557 | [(set_attr "op_type" "RRF,RRF,RSY,RSY,RIE,RIE,RSY,RSY,*") |
6558 | (set_attr "cpu_facility" "*,*,*,*,z13,z13,*,*,*")]) | |
65b1d8ea | 6559 | |
9db1d521 HP |
6560 | ;; |
6561 | ;;- Multiply instructions. | |
6562 | ;; | |
6563 | ||
4023fb28 UW |
6564 | ; |
6565 | ; muldi3 instruction pattern(s). | |
6566 | ; | |
9db1d521 | 6567 | |
07893d4f UW |
6568 | (define_insn "*muldi3_sign" |
6569 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
3e4be43f | 6570 | (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,T")) |
07893d4f | 6571 | (match_operand:DI 1 "register_operand" "0,0")))] |
9602b6a1 | 6572 | "TARGET_ZARCH" |
07893d4f | 6573 | "@ |
d40c829f UW |
6574 | msgfr\t%0,%2 |
6575 | msgf\t%0,%2" | |
963fc8d0 AK |
6576 | [(set_attr "op_type" "RRE,RXY") |
6577 | (set_attr "type" "imuldi")]) | |
07893d4f | 6578 | |
4023fb28 | 6579 | (define_insn "muldi3" |
963fc8d0 AK |
6580 | [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") |
6581 | (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") | |
3e4be43f | 6582 | (match_operand:DI 2 "general_operand" "d,K,T,Os")))] |
9602b6a1 | 6583 | "TARGET_ZARCH" |
9db1d521 | 6584 | "@ |
d40c829f UW |
6585 | msgr\t%0,%2 |
6586 | mghi\t%0,%h2 | |
963fc8d0 AK |
6587 | msg\t%0,%2 |
6588 | msgfi\t%0,%2" | |
6589 | [(set_attr "op_type" "RRE,RI,RXY,RIL") | |
6590 | (set_attr "type" "imuldi") | |
6591 | (set_attr "cpu_facility" "*,*,*,z10")]) | |
f2d3c02a | 6592 | |
9db1d521 HP |
6593 | ; |
6594 | ; mulsi3 instruction pattern(s). | |
6595 | ; | |
6596 | ||
f1e77d83 | 6597 | (define_insn "*mulsi3_sign" |
963fc8d0 AK |
6598 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
6599 | (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) | |
6600 | (match_operand:SI 1 "register_operand" "0,0")))] | |
f1e77d83 | 6601 | "" |
963fc8d0 AK |
6602 | "@ |
6603 | mh\t%0,%2 | |
6604 | mhy\t%0,%2" | |
6605 | [(set_attr "op_type" "RX,RXY") | |
6606 | (set_attr "type" "imulhi") | |
6607 | (set_attr "cpu_facility" "*,z10")]) | |
f1e77d83 | 6608 | |
9db1d521 | 6609 | (define_insn "mulsi3" |
963fc8d0 AK |
6610 | [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
6611 | (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") | |
6612 | (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))] | |
9db1d521 HP |
6613 | "" |
6614 | "@ | |
d40c829f UW |
6615 | msr\t%0,%2 |
6616 | mhi\t%0,%h2 | |
6617 | ms\t%0,%2 | |
963fc8d0 AK |
6618 | msy\t%0,%2 |
6619 | msfi\t%0,%2" | |
6620 | [(set_attr "op_type" "RRE,RI,RX,RXY,RIL") | |
6621 | (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi") | |
3e4be43f | 6622 | (set_attr "cpu_facility" "*,*,*,longdisp,z10")]) |
9db1d521 | 6623 | |
4023fb28 UW |
6624 | ; |
6625 | ; mulsidi3 instruction pattern(s). | |
6626 | ; | |
6627 | ||
f1e77d83 | 6628 | (define_insn "mulsidi3" |
963fc8d0 | 6629 | [(set (match_operand:DI 0 "register_operand" "=d,d,d") |
f1e77d83 | 6630 | (mult:DI (sign_extend:DI |
963fc8d0 | 6631 | (match_operand:SI 1 "register_operand" "%0,0,0")) |
f1e77d83 | 6632 | (sign_extend:DI |
963fc8d0 | 6633 | (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] |
9602b6a1 | 6634 | "!TARGET_ZARCH" |
f1e77d83 UW |
6635 | "@ |
6636 | mr\t%0,%2 | |
963fc8d0 AK |
6637 | m\t%0,%2 |
6638 | mfy\t%0,%2" | |
6639 | [(set_attr "op_type" "RR,RX,RXY") | |
6640 | (set_attr "type" "imulsi") | |
6641 | (set_attr "cpu_facility" "*,*,z10")]) | |
4023fb28 | 6642 | |
f1e77d83 | 6643 | ; |
6e0d70c9 | 6644 | ; umul instruction pattern(s). |
f1e77d83 | 6645 | ; |
c7453384 | 6646 | |
6e0d70c9 AK |
6647 | ; mlr, ml, mlgr, mlg |
6648 | (define_insn "umul<dwh><mode>3" | |
3e4be43f | 6649 | [(set (match_operand:DW 0 "register_operand" "=d,d") |
6e0d70c9 | 6650 | (mult:DW (zero_extend:DW |
3e4be43f | 6651 | (match_operand:<DWH> 1 "register_operand" "%0,0")) |
6e0d70c9 | 6652 | (zero_extend:DW |
3e4be43f | 6653 | (match_operand:<DWH> 2 "nonimmediate_operand" " d,T"))))] |
6e0d70c9 | 6654 | "TARGET_CPU_ZARCH" |
f1e77d83 | 6655 | "@ |
6e0d70c9 AK |
6656 | ml<tg>r\t%0,%2 |
6657 | ml<tg>\t%0,%2" | |
f1e77d83 | 6658 | [(set_attr "op_type" "RRE,RXY") |
6e0d70c9 | 6659 | (set_attr "type" "imul<dwh>")]) |
c7453384 | 6660 | |
9db1d521 | 6661 | ; |
609e7e80 | 6662 | ; mul(tf|df|sf|td|dd)3 instruction pattern(s). |
9db1d521 HP |
6663 | ; |
6664 | ||
9381e3f1 | 6665 | ; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr |
142cd70f | 6666 | (define_insn "mul<mode>3" |
62d3f261 AK |
6667 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v") |
6668 | (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%f,0,0,v") | |
6669 | (match_operand:FP 2 "general_operand" "f,f,R,v")))] | |
142cd70f | 6670 | "TARGET_HARD_FLOAT" |
9db1d521 | 6671 | "@ |
62d3f261 AK |
6672 | m<xdee>tr\t%0,%1,%2 |
6673 | m<xdee>br\t%0,%2 | |
6e5b5de8 AK |
6674 | m<xdee>b\t%0,%2 |
6675 | wfmdb\t%v0,%v1,%v2" | |
62d3f261 | 6676 | [(set_attr "op_type" "RRF,RRE,RXE,VRR") |
6e5b5de8 | 6677 | (set_attr "type" "fmul<mode>") |
285363a1 | 6678 | (set_attr "cpu_facility" "*,*,*,vx") |
62d3f261 | 6679 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")]) |
9db1d521 | 6680 | |
9381e3f1 | 6681 | ; madbr, maebr, maxb, madb, maeb |
d7ecb504 | 6682 | (define_insn "fma<mode>4" |
62d3f261 AK |
6683 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v") |
6684 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v") | |
6685 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v") | |
6686 | (match_operand:DSF 3 "register_operand" "0,0,v")))] | |
d7ecb504 | 6687 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6688 | "@ |
f61a2c7d | 6689 | ma<xde>br\t%0,%1,%2 |
6e5b5de8 AK |
6690 | ma<xde>b\t%0,%1,%2 |
6691 | wfmadb\t%v0,%v1,%v2,%v3" | |
6692 | [(set_attr "op_type" "RRE,RXE,VRR") | |
6693 | (set_attr "type" "fmadd<mode>") | |
285363a1 | 6694 | (set_attr "cpu_facility" "*,*,vx") |
62d3f261 | 6695 | (set_attr "enabled" "*,*,<DFDI>")]) |
a1b892b5 | 6696 | |
43a09b63 | 6697 | ; msxbr, msdbr, msebr, msxb, msdb, mseb |
d7ecb504 | 6698 | (define_insn "fms<mode>4" |
62d3f261 AK |
6699 | [(set (match_operand:DSF 0 "register_operand" "=f,f,v") |
6700 | (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,v") | |
6701 | (match_operand:DSF 2 "nonimmediate_operand" "f,R,v") | |
6702 | (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,v"))))] | |
d7ecb504 | 6703 | "TARGET_HARD_FLOAT" |
a1b892b5 | 6704 | "@ |
f61a2c7d | 6705 | ms<xde>br\t%0,%1,%2 |
6e5b5de8 AK |
6706 | ms<xde>b\t%0,%1,%2 |
6707 | wfmsdb\t%v0,%v1,%v2,%v3" | |
6708 | [(set_attr "op_type" "RRE,RXE,VRR") | |
6709 | (set_attr "type" "fmadd<mode>") | |
285363a1 | 6710 | (set_attr "cpu_facility" "*,*,vx") |
62d3f261 | 6711 | (set_attr "enabled" "*,*,<DFDI>")]) |
9db1d521 HP |
6712 | |
6713 | ;; | |
6714 | ;;- Divide and modulo instructions. | |
6715 | ;; | |
6716 | ||
6717 | ; | |
4023fb28 | 6718 | ; divmoddi4 instruction pattern(s). |
9db1d521 HP |
6719 | ; |
6720 | ||
4023fb28 UW |
6721 | (define_expand "divmoddi4" |
6722 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
f1e77d83 | 6723 | (div:DI (match_operand:DI 1 "register_operand" "") |
4023fb28 UW |
6724 | (match_operand:DI 2 "general_operand" ""))) |
6725 | (set (match_operand:DI 3 "general_operand" "") | |
6726 | (mod:DI (match_dup 1) (match_dup 2)))]) | |
6727 | (clobber (match_dup 4))] | |
9602b6a1 | 6728 | "TARGET_ZARCH" |
9db1d521 | 6729 | { |
d8485bdb TS |
6730 | rtx div_equal, mod_equal; |
6731 | rtx_insn *insn; | |
4023fb28 UW |
6732 | |
6733 | div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); | |
6734 | mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); | |
4023fb28 UW |
6735 | |
6736 | operands[4] = gen_reg_rtx(TImode); | |
f1e77d83 | 6737 | emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); |
4023fb28 UW |
6738 | |
6739 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6740 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6741 | |
6742 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6743 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6744 | |
9db1d521 | 6745 | DONE; |
10bbf137 | 6746 | }) |
9db1d521 HP |
6747 | |
6748 | (define_insn "divmodtidi3" | |
4023fb28 UW |
6749 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
6750 | (ior:TI | |
4023fb28 UW |
6751 | (ashift:TI |
6752 | (zero_extend:TI | |
5665e398 | 6753 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
3e4be43f | 6754 | (match_operand:DI 2 "general_operand" "d,T"))) |
5665e398 UW |
6755 | (const_int 64)) |
6756 | (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] | |
9602b6a1 | 6757 | "TARGET_ZARCH" |
9db1d521 | 6758 | "@ |
d40c829f UW |
6759 | dsgr\t%0,%2 |
6760 | dsg\t%0,%2" | |
d3632d41 | 6761 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6762 | (set_attr "type" "idiv")]) |
9db1d521 | 6763 | |
4023fb28 UW |
6764 | (define_insn "divmodtisi3" |
6765 | [(set (match_operand:TI 0 "register_operand" "=d,d") | |
6766 | (ior:TI | |
4023fb28 UW |
6767 | (ashift:TI |
6768 | (zero_extend:TI | |
5665e398 | 6769 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
2f7e5a0d | 6770 | (sign_extend:DI |
3e4be43f | 6771 | (match_operand:SI 2 "nonimmediate_operand" "d,T")))) |
5665e398 UW |
6772 | (const_int 64)) |
6773 | (zero_extend:TI | |
6774 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] | |
9602b6a1 | 6775 | "TARGET_ZARCH" |
4023fb28 | 6776 | "@ |
d40c829f UW |
6777 | dsgfr\t%0,%2 |
6778 | dsgf\t%0,%2" | |
d3632d41 | 6779 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6780 | (set_attr "type" "idiv")]) |
9db1d521 | 6781 | |
4023fb28 UW |
6782 | ; |
6783 | ; udivmoddi4 instruction pattern(s). | |
6784 | ; | |
9db1d521 | 6785 | |
4023fb28 UW |
6786 | (define_expand "udivmoddi4" |
6787 | [(parallel [(set (match_operand:DI 0 "general_operand" "") | |
6788 | (udiv:DI (match_operand:DI 1 "general_operand" "") | |
6789 | (match_operand:DI 2 "nonimmediate_operand" ""))) | |
6790 | (set (match_operand:DI 3 "general_operand" "") | |
6791 | (umod:DI (match_dup 1) (match_dup 2)))]) | |
6792 | (clobber (match_dup 4))] | |
9602b6a1 | 6793 | "TARGET_ZARCH" |
9db1d521 | 6794 | { |
d8485bdb TS |
6795 | rtx div_equal, mod_equal, equal; |
6796 | rtx_insn *insn; | |
4023fb28 UW |
6797 | |
6798 | div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); | |
6799 | mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); | |
6800 | equal = gen_rtx_IOR (TImode, | |
4023fb28 UW |
6801 | gen_rtx_ASHIFT (TImode, |
6802 | gen_rtx_ZERO_EXTEND (TImode, mod_equal), | |
5665e398 UW |
6803 | GEN_INT (64)), |
6804 | gen_rtx_ZERO_EXTEND (TImode, div_equal)); | |
4023fb28 UW |
6805 | |
6806 | operands[4] = gen_reg_rtx(TImode); | |
c41c1387 | 6807 | emit_clobber (operands[4]); |
4023fb28 UW |
6808 | emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); |
6809 | emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); | |
bd94cb6e | 6810 | |
4023fb28 | 6811 | insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6812 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
6813 | |
6814 | insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); | |
bd94cb6e | 6815 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6816 | |
6817 | insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); | |
bd94cb6e | 6818 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6819 | |
9db1d521 | 6820 | DONE; |
10bbf137 | 6821 | }) |
9db1d521 HP |
6822 | |
6823 | (define_insn "udivmodtidi3" | |
4023fb28 | 6824 | [(set (match_operand:TI 0 "register_operand" "=d,d") |
2f7e5a0d | 6825 | (ior:TI |
5665e398 UW |
6826 | (ashift:TI |
6827 | (zero_extend:TI | |
6828 | (truncate:DI | |
2f7e5a0d EC |
6829 | (umod:TI (match_operand:TI 1 "register_operand" "0,0") |
6830 | (zero_extend:TI | |
3e4be43f | 6831 | (match_operand:DI 2 "nonimmediate_operand" "d,T"))))) |
5665e398 UW |
6832 | (const_int 64)) |
6833 | (zero_extend:TI | |
6834 | (truncate:DI | |
6835 | (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] | |
9602b6a1 | 6836 | "TARGET_ZARCH" |
9db1d521 | 6837 | "@ |
d40c829f UW |
6838 | dlgr\t%0,%2 |
6839 | dlg\t%0,%2" | |
d3632d41 | 6840 | [(set_attr "op_type" "RRE,RXY") |
077dab3b | 6841 | (set_attr "type" "idiv")]) |
9db1d521 HP |
6842 | |
6843 | ; | |
4023fb28 | 6844 | ; divmodsi4 instruction pattern(s). |
9db1d521 HP |
6845 | ; |
6846 | ||
4023fb28 UW |
6847 | (define_expand "divmodsi4" |
6848 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
6849 | (div:SI (match_operand:SI 1 "general_operand" "") | |
6850 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
6851 | (set (match_operand:SI 3 "general_operand" "") | |
6852 | (mod:SI (match_dup 1) (match_dup 2)))]) | |
6853 | (clobber (match_dup 4))] | |
9602b6a1 | 6854 | "!TARGET_ZARCH" |
9db1d521 | 6855 | { |
d8485bdb TS |
6856 | rtx div_equal, mod_equal, equal; |
6857 | rtx_insn *insn; | |
4023fb28 UW |
6858 | |
6859 | div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); | |
6860 | mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); | |
6861 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
6862 | gen_rtx_ASHIFT (DImode, |
6863 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
6864 | GEN_INT (32)), |
6865 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
4023fb28 UW |
6866 | |
6867 | operands[4] = gen_reg_rtx(DImode); | |
6868 | emit_insn (gen_extendsidi2 (operands[4], operands[1])); | |
bd94cb6e | 6869 | |
4023fb28 | 6870 | insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6871 | set_unique_reg_note (insn, REG_EQUAL, equal); |
4023fb28 UW |
6872 | |
6873 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 6874 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
4023fb28 UW |
6875 | |
6876 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 6877 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
9db1d521 | 6878 | |
9db1d521 | 6879 | DONE; |
10bbf137 | 6880 | }) |
9db1d521 HP |
6881 | |
6882 | (define_insn "divmoddisi3" | |
4023fb28 | 6883 | [(set (match_operand:DI 0 "register_operand" "=d,d") |
2f7e5a0d | 6884 | (ior:DI |
5665e398 UW |
6885 | (ashift:DI |
6886 | (zero_extend:DI | |
6887 | (truncate:SI | |
2f7e5a0d EC |
6888 | (mod:DI (match_operand:DI 1 "register_operand" "0,0") |
6889 | (sign_extend:DI | |
5665e398 UW |
6890 | (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) |
6891 | (const_int 32)) | |
6892 | (zero_extend:DI | |
6893 | (truncate:SI | |
6894 | (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 6895 | "!TARGET_ZARCH" |
9db1d521 | 6896 | "@ |
d40c829f UW |
6897 | dr\t%0,%2 |
6898 | d\t%0,%2" | |
9db1d521 | 6899 | [(set_attr "op_type" "RR,RX") |
077dab3b | 6900 | (set_attr "type" "idiv")]) |
9db1d521 HP |
6901 | |
6902 | ; | |
6903 | ; udivsi3 and umodsi3 instruction pattern(s). | |
6904 | ; | |
6905 | ||
f1e77d83 UW |
6906 | (define_expand "udivmodsi4" |
6907 | [(parallel [(set (match_operand:SI 0 "general_operand" "") | |
6908 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
6909 | (match_operand:SI 2 "nonimmediate_operand" ""))) | |
6910 | (set (match_operand:SI 3 "general_operand" "") | |
6911 | (umod:SI (match_dup 1) (match_dup 2)))]) | |
6912 | (clobber (match_dup 4))] | |
9602b6a1 | 6913 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 | 6914 | { |
d8485bdb TS |
6915 | rtx div_equal, mod_equal, equal; |
6916 | rtx_insn *insn; | |
f1e77d83 UW |
6917 | |
6918 | div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
6919 | mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
6920 | equal = gen_rtx_IOR (DImode, | |
f1e77d83 UW |
6921 | gen_rtx_ASHIFT (DImode, |
6922 | gen_rtx_ZERO_EXTEND (DImode, mod_equal), | |
5665e398 UW |
6923 | GEN_INT (32)), |
6924 | gen_rtx_ZERO_EXTEND (DImode, div_equal)); | |
f1e77d83 UW |
6925 | |
6926 | operands[4] = gen_reg_rtx(DImode); | |
c41c1387 | 6927 | emit_clobber (operands[4]); |
f1e77d83 UW |
6928 | emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); |
6929 | emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); | |
bd94cb6e | 6930 | |
f1e77d83 | 6931 | insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); |
bd94cb6e | 6932 | set_unique_reg_note (insn, REG_EQUAL, equal); |
f1e77d83 UW |
6933 | |
6934 | insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); | |
bd94cb6e | 6935 | set_unique_reg_note (insn, REG_EQUAL, div_equal); |
f1e77d83 UW |
6936 | |
6937 | insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); | |
bd94cb6e | 6938 | set_unique_reg_note (insn, REG_EQUAL, mod_equal); |
f1e77d83 UW |
6939 | |
6940 | DONE; | |
6941 | }) | |
6942 | ||
6943 | (define_insn "udivmoddisi3" | |
6944 | [(set (match_operand:DI 0 "register_operand" "=d,d") | |
2f7e5a0d | 6945 | (ior:DI |
5665e398 UW |
6946 | (ashift:DI |
6947 | (zero_extend:DI | |
6948 | (truncate:SI | |
2f7e5a0d EC |
6949 | (umod:DI (match_operand:DI 1 "register_operand" "0,0") |
6950 | (zero_extend:DI | |
3e4be43f | 6951 | (match_operand:SI 2 "nonimmediate_operand" "d,T"))))) |
5665e398 UW |
6952 | (const_int 32)) |
6953 | (zero_extend:DI | |
6954 | (truncate:SI | |
6955 | (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] | |
9602b6a1 | 6956 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1e77d83 UW |
6957 | "@ |
6958 | dlr\t%0,%2 | |
6959 | dl\t%0,%2" | |
6960 | [(set_attr "op_type" "RRE,RXY") | |
6961 | (set_attr "type" "idiv")]) | |
4023fb28 | 6962 | |
9db1d521 HP |
6963 | (define_expand "udivsi3" |
6964 | [(set (match_operand:SI 0 "register_operand" "=d") | |
6965 | (udiv:SI (match_operand:SI 1 "general_operand" "") | |
4023fb28 UW |
6966 | (match_operand:SI 2 "general_operand" ""))) |
6967 | (clobber (match_dup 3))] | |
9602b6a1 | 6968 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 6969 | { |
d8485bdb TS |
6970 | rtx udiv_equal, umod_equal, equal; |
6971 | rtx_insn *insn; | |
4023fb28 UW |
6972 | |
6973 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
6974 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
6975 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
6976 | gen_rtx_ASHIFT (DImode, |
6977 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
6978 | GEN_INT (32)), |
6979 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 6980 | |
4023fb28 | 6981 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
6982 | |
6983 | if (CONSTANT_P (operands[2])) | |
6984 | { | |
6985 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) | |
6986 | { | |
19f8b229 | 6987 | rtx_code_label *label1 = gen_label_rtx (); |
9db1d521 | 6988 | |
4023fb28 UW |
6989 | operands[1] = make_safe_from (operands[1], operands[0]); |
6990 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
6991 | emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX, |
6992 | SImode, 1, label1); | |
4023fb28 | 6993 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
6994 | emit_label (label1); |
6995 | } | |
6996 | else | |
6997 | { | |
c7453384 EC |
6998 | operands[2] = force_reg (SImode, operands[2]); |
6999 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
7000 | |
7001 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
7002 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
7003 | operands[2])); | |
bd94cb6e | 7004 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
7005 | |
7006 | insn = emit_move_insn (operands[0], | |
4023fb28 | 7007 | gen_lowpart (SImode, operands[3])); |
bd94cb6e | 7008 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
9db1d521 HP |
7009 | } |
7010 | } | |
7011 | else | |
c7453384 | 7012 | { |
19f8b229 TS |
7013 | rtx_code_label *label1 = gen_label_rtx (); |
7014 | rtx_code_label *label2 = gen_label_rtx (); | |
7015 | rtx_code_label *label3 = gen_label_rtx (); | |
9db1d521 | 7016 | |
c7453384 EC |
7017 | operands[1] = force_reg (SImode, operands[1]); |
7018 | operands[1] = make_safe_from (operands[1], operands[0]); | |
7019 | operands[2] = force_reg (SImode, operands[2]); | |
7020 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
7021 | |
7022 | emit_move_insn (operands[0], const0_rtx); | |
f90b7a5a PB |
7023 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
7024 | SImode, 1, label3); | |
7025 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
7026 | SImode, 0, label2); | |
7027 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
7028 | SImode, 0, label1); | |
4023fb28 UW |
7029 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
7030 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
7031 | operands[2])); | |
bd94cb6e | 7032 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
7033 | |
7034 | insn = emit_move_insn (operands[0], | |
4023fb28 | 7035 | gen_lowpart (SImode, operands[3])); |
bd94cb6e SB |
7036 | set_unique_reg_note (insn, REG_EQUAL, udiv_equal); |
7037 | ||
f314b9b1 | 7038 | emit_jump (label3); |
9db1d521 | 7039 | emit_label (label1); |
4023fb28 | 7040 | emit_move_insn (operands[0], operands[1]); |
f314b9b1 | 7041 | emit_jump (label3); |
9db1d521 | 7042 | emit_label (label2); |
4023fb28 | 7043 | emit_move_insn (operands[0], const1_rtx); |
9db1d521 HP |
7044 | emit_label (label3); |
7045 | } | |
c7453384 | 7046 | emit_move_insn (operands[0], operands[0]); |
9db1d521 | 7047 | DONE; |
10bbf137 | 7048 | }) |
9db1d521 HP |
7049 | |
7050 | (define_expand "umodsi3" | |
7051 | [(set (match_operand:SI 0 "register_operand" "=d") | |
7052 | (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") | |
4023fb28 UW |
7053 | (match_operand:SI 2 "nonimmediate_operand" ""))) |
7054 | (clobber (match_dup 3))] | |
9602b6a1 | 7055 | "!TARGET_ZARCH && !TARGET_CPU_ZARCH" |
9db1d521 | 7056 | { |
d8485bdb TS |
7057 | rtx udiv_equal, umod_equal, equal; |
7058 | rtx_insn *insn; | |
4023fb28 UW |
7059 | |
7060 | udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); | |
7061 | umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); | |
7062 | equal = gen_rtx_IOR (DImode, | |
4023fb28 UW |
7063 | gen_rtx_ASHIFT (DImode, |
7064 | gen_rtx_ZERO_EXTEND (DImode, umod_equal), | |
5665e398 UW |
7065 | GEN_INT (32)), |
7066 | gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); | |
9db1d521 | 7067 | |
4023fb28 | 7068 | operands[3] = gen_reg_rtx (DImode); |
9db1d521 HP |
7069 | |
7070 | if (CONSTANT_P (operands[2])) | |
7071 | { | |
7072 | if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) | |
7073 | { | |
19f8b229 | 7074 | rtx_code_label *label1 = gen_label_rtx (); |
9db1d521 | 7075 | |
4023fb28 UW |
7076 | operands[1] = make_safe_from (operands[1], operands[0]); |
7077 | emit_move_insn (operands[0], operands[1]); | |
f90b7a5a PB |
7078 | emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX, |
7079 | SImode, 1, label1); | |
4023fb28 UW |
7080 | emit_insn (gen_abssi2 (operands[0], operands[2])); |
7081 | emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); | |
9db1d521 HP |
7082 | emit_label (label1); |
7083 | } | |
7084 | else | |
7085 | { | |
c7453384 EC |
7086 | operands[2] = force_reg (SImode, operands[2]); |
7087 | operands[2] = make_safe_from (operands[2], operands[0]); | |
4023fb28 UW |
7088 | |
7089 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); | |
7090 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
7091 | operands[2])); | |
bd94cb6e | 7092 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
7093 | |
7094 | insn = emit_move_insn (operands[0], | |
4023fb28 | 7095 | gen_highpart (SImode, operands[3])); |
bd94cb6e | 7096 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
9db1d521 HP |
7097 | } |
7098 | } | |
7099 | else | |
7100 | { | |
19f8b229 TS |
7101 | rtx_code_label *label1 = gen_label_rtx (); |
7102 | rtx_code_label *label2 = gen_label_rtx (); | |
7103 | rtx_code_label *label3 = gen_label_rtx (); | |
9db1d521 | 7104 | |
c7453384 EC |
7105 | operands[1] = force_reg (SImode, operands[1]); |
7106 | operands[1] = make_safe_from (operands[1], operands[0]); | |
7107 | operands[2] = force_reg (SImode, operands[2]); | |
7108 | operands[2] = make_safe_from (operands[2], operands[0]); | |
9db1d521 | 7109 | |
c7453384 | 7110 | emit_move_insn(operands[0], operands[1]); |
f90b7a5a PB |
7111 | emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, |
7112 | SImode, 1, label3); | |
7113 | emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, | |
7114 | SImode, 0, label2); | |
7115 | emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, | |
7116 | SImode, 0, label1); | |
4023fb28 UW |
7117 | emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); |
7118 | insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], | |
7119 | operands[2])); | |
bd94cb6e | 7120 | set_unique_reg_note (insn, REG_EQUAL, equal); |
c7453384 EC |
7121 | |
7122 | insn = emit_move_insn (operands[0], | |
4023fb28 | 7123 | gen_highpart (SImode, operands[3])); |
bd94cb6e SB |
7124 | set_unique_reg_note (insn, REG_EQUAL, umod_equal); |
7125 | ||
f314b9b1 | 7126 | emit_jump (label3); |
9db1d521 | 7127 | emit_label (label1); |
4023fb28 | 7128 | emit_move_insn (operands[0], const0_rtx); |
f314b9b1 | 7129 | emit_jump (label3); |
9db1d521 | 7130 | emit_label (label2); |
4023fb28 | 7131 | emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); |
9db1d521 HP |
7132 | emit_label (label3); |
7133 | } | |
9db1d521 | 7134 | DONE; |
10bbf137 | 7135 | }) |
9db1d521 HP |
7136 | |
7137 | ; | |
f5905b37 | 7138 | ; div(df|sf)3 instruction pattern(s). |
9db1d521 HP |
7139 | ; |
7140 | ||
609e7e80 | 7141 | ; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr |
142cd70f | 7142 | (define_insn "div<mode>3" |
62d3f261 AK |
7143 | [(set (match_operand:FP 0 "register_operand" "=f,f,f,v") |
7144 | (div:FP (match_operand:FP 1 "register_operand" "f,0,0,v") | |
7145 | (match_operand:FP 2 "general_operand" "f,f,R,v")))] | |
142cd70f | 7146 | "TARGET_HARD_FLOAT" |
9db1d521 | 7147 | "@ |
62d3f261 AK |
7148 | d<xde>tr\t%0,%1,%2 |
7149 | d<xde>br\t%0,%2 | |
6e5b5de8 AK |
7150 | d<xde>b\t%0,%2 |
7151 | wfddb\t%v0,%v1,%v2" | |
62d3f261 | 7152 | [(set_attr "op_type" "RRF,RRE,RXE,VRR") |
6e5b5de8 | 7153 | (set_attr "type" "fdiv<mode>") |
285363a1 | 7154 | (set_attr "cpu_facility" "*,*,*,vx") |
62d3f261 | 7155 | (set_attr "enabled" "<nBFP>,<nDFP>,<DSF>,<DFDI>")]) |
9db1d521 | 7156 | |
9db1d521 HP |
7157 | |
7158 | ;; | |
7159 | ;;- And instructions. | |
7160 | ;; | |
7161 | ||
047d35ed AS |
7162 | (define_expand "and<mode>3" |
7163 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7164 | (and:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7165 | (match_operand:INT 2 "general_operand" ""))) | |
7166 | (clobber (reg:CC CC_REGNUM))] | |
7167 | "" | |
7168 | "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") | |
7169 | ||
9db1d521 HP |
7170 | ; |
7171 | ; anddi3 instruction pattern(s). | |
7172 | ; | |
7173 | ||
7174 | (define_insn "*anddi3_cc" | |
ae156f85 | 7175 | [(set (reg CC_REGNUM) |
e3140518 | 7176 | (compare |
3e4be43f | 7177 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") |
c2586c82 | 7178 | (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) |
e3140518 | 7179 | (const_int 0))) |
3e4be43f | 7180 | (set (match_operand:DI 0 "register_operand" "=d,d,d, d") |
9db1d521 | 7181 | (and:DI (match_dup 1) (match_dup 2)))] |
e3140518 | 7182 | "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" |
9db1d521 | 7183 | "@ |
d40c829f | 7184 | ngr\t%0,%2 |
65b1d8ea | 7185 | ngrk\t%0,%1,%2 |
e3140518 RH |
7186 | ng\t%0,%2 |
7187 | risbg\t%0,%1,%s2,128+%e2,0" | |
7188 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
7189 | (set_attr "cpu_facility" "*,z196,*,z10") | |
7190 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7191 | |
7192 | (define_insn "*anddi3_cconly" | |
ae156f85 | 7193 | [(set (reg CC_REGNUM) |
e3140518 | 7194 | (compare |
3e4be43f | 7195 | (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0, d") |
c2586c82 | 7196 | (match_operand:DI 2 "general_operand" " d,d,T,NxxDw")) |
9db1d521 | 7197 | (const_int 0))) |
3e4be43f | 7198 | (clobber (match_scratch:DI 0 "=d,d,d, d"))] |
e3140518 RH |
7199 | "TARGET_ZARCH |
7200 | && s390_match_ccmode(insn, CCTmode) | |
68f9c5e2 UW |
7201 | /* Do not steal TM patterns. */ |
7202 | && s390_single_part (operands[2], DImode, HImode, 0) < 0" | |
9db1d521 | 7203 | "@ |
d40c829f | 7204 | ngr\t%0,%2 |
65b1d8ea | 7205 | ngrk\t%0,%1,%2 |
e3140518 RH |
7206 | ng\t%0,%2 |
7207 | risbg\t%0,%1,%s2,128+%e2,0" | |
7208 | [(set_attr "op_type" "RRE,RRF,RXY,RIE") | |
7209 | (set_attr "cpu_facility" "*,z196,*,z10") | |
7210 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) | |
9db1d521 | 7211 | |
3af8e996 | 7212 | (define_insn "*anddi3" |
65b1d8ea | 7213 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 7214 | "=d,d, d, d, d, d, d, d,d,d,d, d, AQ,Q") |
e3140518 RH |
7215 | (and:DI |
7216 | (match_operand:DI 1 "nonimmediate_operand" | |
3e4be43f | 7217 | "%d,o, 0, 0, 0, 0, 0, 0,0,d,0, d, 0,0") |
e3140518 | 7218 | (match_operand:DI 2 "general_operand" |
c2586c82 | 7219 | "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,T,NxxDw,NxQDF,Q"))) |
ec24698e | 7220 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7221 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7222 | "@ |
7223 | # | |
7224 | # | |
7225 | nihh\t%0,%j2 | |
7226 | nihl\t%0,%j2 | |
7227 | nilh\t%0,%j2 | |
7228 | nill\t%0,%j2 | |
7229 | nihf\t%0,%m2 | |
7230 | nilf\t%0,%m2 | |
7231 | ngr\t%0,%2 | |
65b1d8ea | 7232 | ngrk\t%0,%1,%2 |
ec24698e | 7233 | ng\t%0,%2 |
e3140518 | 7234 | risbg\t%0,%1,%s2,128+%e2,0 |
ec24698e UW |
7235 | # |
7236 | #" | |
e3140518 RH |
7237 | [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS") |
7238 | (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*") | |
9381e3f1 WG |
7239 | (set_attr "z10prop" "*, |
7240 | *, | |
7241 | z10_super_E1, | |
7242 | z10_super_E1, | |
7243 | z10_super_E1, | |
7244 | z10_super_E1, | |
7245 | z10_super_E1, | |
7246 | z10_super_E1, | |
7247 | z10_super_E1, | |
65b1d8ea | 7248 | *, |
9381e3f1 | 7249 | z10_super_E1, |
e3140518 | 7250 | z10_super_E1, |
9381e3f1 WG |
7251 | *, |
7252 | *")]) | |
0dfa6c5e UW |
7253 | |
7254 | (define_split | |
7255 | [(set (match_operand:DI 0 "s_operand" "") | |
7256 | (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7257 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7258 | "reload_completed" |
7259 | [(parallel | |
7260 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7261 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7262 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7263 | |
1a2e356e | 7264 | ;; These two are what combine generates for (ashift (zero_extract)). |
64c744b9 | 7265 | (define_insn "*extzv_<mode>_srl<clobbercc_or_nocc>" |
1a2e356e RH |
7266 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7267 | (and:GPR (lshiftrt:GPR | |
7268 | (match_operand:GPR 1 "register_operand" "d") | |
7269 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 7270 | (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] |
64c744b9 | 7271 | "<z10_or_zEC12_cond> |
1a2e356e RH |
7272 | /* Note that even for the SImode pattern, the rotate is always DImode. */ |
7273 | && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]), | |
7274 | INTVAL (operands[3]))" | |
64c744b9 | 7275 | "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2" |
1a2e356e RH |
7276 | [(set_attr "op_type" "RIE") |
7277 | (set_attr "z10prop" "z10_super_E1")]) | |
7278 | ||
64c744b9 | 7279 | (define_insn "*extzv_<mode>_sll<clobbercc_or_nocc>" |
1a2e356e RH |
7280 | [(set (match_operand:GPR 0 "register_operand" "=d") |
7281 | (and:GPR (ashift:GPR | |
7282 | (match_operand:GPR 1 "register_operand" "d") | |
7283 | (match_operand:GPR 2 "nonzero_shift_count_operand" "")) | |
ab4be5d1 | 7284 | (match_operand:GPR 3 "contiguous_bitmask_nowrap_operand" "")))] |
64c744b9 | 7285 | "<z10_or_zEC12_cond> |
1a2e356e RH |
7286 | && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]), |
7287 | INTVAL (operands[3]))" | |
64c744b9 | 7288 | "<risbg_n>\t%0,%1,%<bfstart>3,128+%<bfend>3,%2" |
1a2e356e RH |
7289 | [(set_attr "op_type" "RIE") |
7290 | (set_attr "z10prop" "z10_super_E1")]) | |
7291 | ||
9db1d521 HP |
7292 | |
7293 | ; | |
7294 | ; andsi3 instruction pattern(s). | |
7295 | ; | |
7296 | ||
7297 | (define_insn "*andsi3_cc" | |
ae156f85 | 7298 | [(set (reg CC_REGNUM) |
e3140518 RH |
7299 | (compare |
7300 | (and:SI | |
7301 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7302 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7303 | (const_int 0))) | |
7304 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d") | |
9db1d521 HP |
7305 | (and:SI (match_dup 1) (match_dup 2)))] |
7306 | "s390_match_ccmode(insn, CCTmode)" | |
7307 | "@ | |
ec24698e | 7308 | nilf\t%0,%o2 |
d40c829f | 7309 | nr\t%0,%2 |
65b1d8ea | 7310 | nrk\t%0,%1,%2 |
d40c829f | 7311 | n\t%0,%2 |
e3140518 RH |
7312 | ny\t%0,%2 |
7313 | risbg\t%0,%1,%t2,128+%f2,0" | |
7314 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
3e4be43f | 7315 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") |
e3140518 RH |
7316 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
7317 | z10_super_E1,z10_super_E1,z10_super_E1")]) | |
9db1d521 HP |
7318 | |
7319 | (define_insn "*andsi3_cconly" | |
ae156f85 | 7320 | [(set (reg CC_REGNUM) |
e3140518 RH |
7321 | (compare |
7322 | (and:SI | |
7323 | (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") | |
7324 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) | |
7325 | (const_int 0))) | |
7326 | (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))] | |
68f9c5e2 UW |
7327 | "s390_match_ccmode(insn, CCTmode) |
7328 | /* Do not steal TM patterns. */ | |
7329 | && s390_single_part (operands[2], SImode, HImode, 0) < 0" | |
9db1d521 | 7330 | "@ |
ec24698e | 7331 | nilf\t%0,%o2 |
d40c829f | 7332 | nr\t%0,%2 |
65b1d8ea | 7333 | nrk\t%0,%1,%2 |
d40c829f | 7334 | n\t%0,%2 |
e3140518 RH |
7335 | ny\t%0,%2 |
7336 | risbg\t%0,%1,%t2,128+%f2,0" | |
7337 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") | |
3e4be43f | 7338 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,z10") |
65b1d8ea | 7339 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
e3140518 | 7340 | z10_super_E1,z10_super_E1,z10_super_E1")]) |
9db1d521 | 7341 | |
f19a9af7 | 7342 | (define_insn "*andsi3_zarch" |
65b1d8ea | 7343 | [(set (match_operand:SI 0 "nonimmediate_operand" |
e3140518 | 7344 | "=d,d, d, d, d,d,d,d,d, d, AQ,Q") |
0dfa6c5e | 7345 | (and:SI (match_operand:SI 1 "nonimmediate_operand" |
e3140518 | 7346 | "%d,o, 0, 0, 0,0,d,0,0, d, 0,0") |
0dfa6c5e | 7347 | (match_operand:SI 2 "general_operand" |
c2586c82 | 7348 | " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSw,NxQSF,Q"))) |
ae156f85 | 7349 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7350 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7351 | "@ |
f19a9af7 AK |
7352 | # |
7353 | # | |
7354 | nilh\t%0,%j2 | |
2f7e5a0d | 7355 | nill\t%0,%j2 |
ec24698e | 7356 | nilf\t%0,%o2 |
d40c829f | 7357 | nr\t%0,%2 |
65b1d8ea | 7358 | nrk\t%0,%1,%2 |
d40c829f | 7359 | n\t%0,%2 |
8cb66696 | 7360 | ny\t%0,%2 |
e3140518 | 7361 | risbg\t%0,%1,%t2,128+%f2,0 |
0dfa6c5e | 7362 | # |
19b63d8e | 7363 | #" |
e3140518 | 7364 | [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") |
3e4be43f | 7365 | (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,longdisp,z10,*,*") |
9381e3f1 WG |
7366 | (set_attr "z10prop" "*, |
7367 | *, | |
7368 | z10_super_E1, | |
7369 | z10_super_E1, | |
7370 | z10_super_E1, | |
7371 | z10_super_E1, | |
65b1d8ea | 7372 | *, |
9381e3f1 WG |
7373 | z10_super_E1, |
7374 | z10_super_E1, | |
e3140518 | 7375 | z10_super_E1, |
9381e3f1 WG |
7376 | *, |
7377 | *")]) | |
f19a9af7 AK |
7378 | |
7379 | (define_insn "*andsi3_esa" | |
65b1d8ea AK |
7380 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") |
7381 | (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") | |
7382 | (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) | |
ae156f85 | 7383 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7384 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7385 | "@ |
7386 | nr\t%0,%2 | |
8cb66696 | 7387 | n\t%0,%2 |
0dfa6c5e | 7388 | # |
19b63d8e | 7389 | #" |
9381e3f1 WG |
7390 | [(set_attr "op_type" "RR,RX,SI,SS") |
7391 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
7392 | ||
0dfa6c5e UW |
7393 | |
7394 | (define_split | |
7395 | [(set (match_operand:SI 0 "s_operand" "") | |
7396 | (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7397 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7398 | "reload_completed" |
7399 | [(parallel | |
7400 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7401 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7402 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
4023fb28 | 7403 | |
9db1d521 HP |
7404 | ; |
7405 | ; andhi3 instruction pattern(s). | |
7406 | ; | |
7407 | ||
8cb66696 | 7408 | (define_insn "*andhi3_zarch" |
65b1d8ea AK |
7409 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7410 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7411 | (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) | |
ae156f85 | 7412 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7413 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7414 | "@ |
d40c829f | 7415 | nr\t%0,%2 |
65b1d8ea | 7416 | nrk\t%0,%1,%2 |
8cb66696 | 7417 | nill\t%0,%x2 |
0dfa6c5e | 7418 | # |
19b63d8e | 7419 | #" |
65b1d8ea AK |
7420 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7421 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7422 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") | |
9381e3f1 | 7423 | ]) |
8cb66696 UW |
7424 | |
7425 | (define_insn "*andhi3_esa" | |
0dfa6c5e UW |
7426 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7427 | (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7428 | (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) | |
ae156f85 | 7429 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7430 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7431 | "@ | |
7432 | nr\t%0,%2 | |
0dfa6c5e | 7433 | # |
19b63d8e | 7434 | #" |
9381e3f1 WG |
7435 | [(set_attr "op_type" "RR,SI,SS") |
7436 | (set_attr "z10prop" "z10_super_E1,*,*") | |
7437 | ]) | |
0dfa6c5e UW |
7438 | |
7439 | (define_split | |
7440 | [(set (match_operand:HI 0 "s_operand" "") | |
7441 | (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7442 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7443 | "reload_completed" |
7444 | [(parallel | |
7445 | [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7446 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7447 | "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") |
9db1d521 | 7448 | |
9db1d521 HP |
7449 | ; |
7450 | ; andqi3 instruction pattern(s). | |
7451 | ; | |
7452 | ||
8cb66696 | 7453 | (define_insn "*andqi3_zarch" |
65b1d8ea AK |
7454 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7455 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7456 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7457 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7458 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7459 | "@ |
d40c829f | 7460 | nr\t%0,%2 |
65b1d8ea | 7461 | nrk\t%0,%1,%2 |
8cb66696 | 7462 | nill\t%0,%b2 |
fc0ea003 UW |
7463 | ni\t%S0,%b2 |
7464 | niy\t%S0,%b2 | |
19b63d8e | 7465 | #" |
65b1d8ea | 7466 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
3e4be43f | 7467 | (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") |
65b1d8ea | 7468 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) |
8cb66696 UW |
7469 | |
7470 | (define_insn "*andqi3_esa" | |
7471 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7472 | (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7473 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7474 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7475 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7476 | "@ |
8cb66696 | 7477 | nr\t%0,%2 |
fc0ea003 | 7478 | ni\t%S0,%b2 |
19b63d8e | 7479 | #" |
9381e3f1 WG |
7480 | [(set_attr "op_type" "RR,SI,SS") |
7481 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
4023fb28 | 7482 | |
deb9351f DV |
7483 | ; |
7484 | ; And with complement | |
7485 | ; | |
7486 | ; c = ~b & a = (b & a) ^ a | |
7487 | ||
7488 | (define_insn_and_split "*andc_split_<mode>" | |
7489 | [(set (match_operand:GPR 0 "nonimmediate_operand" "") | |
7490 | (and:GPR (not:GPR (match_operand:GPR 1 "nonimmediate_operand" "")) | |
7491 | (match_operand:GPR 2 "general_operand" ""))) | |
7492 | (clobber (reg:CC CC_REGNUM))] | |
ad7ab32e DV |
7493 | "! reload_completed |
7494 | && (GET_CODE (operands[0]) != MEM | |
7495 | /* Ensure that s390_logical_operator_ok_p will succeed even | |
7496 | on the split xor if (b & a) is stored into a pseudo. */ | |
7497 | || rtx_equal_p (operands[0], operands[2]))" | |
deb9351f DV |
7498 | "#" |
7499 | "&& 1" | |
7500 | [ | |
7501 | (parallel | |
7502 | [(set (match_dup 3) (and:GPR (match_dup 1) (match_dup 2))) | |
7503 | (clobber (reg:CC CC_REGNUM))]) | |
7504 | (parallel | |
7505 | [(set (match_dup 0) (xor:GPR (match_dup 3) (match_dup 2))) | |
7506 | (clobber (reg:CC CC_REGNUM))])] | |
7507 | { | |
7508 | if (reg_overlap_mentioned_p (operands[0], operands[2])) | |
7509 | operands[3] = gen_reg_rtx (<MODE>mode); | |
7510 | else | |
7511 | operands[3] = operands[0]; | |
7512 | }) | |
7513 | ||
19b63d8e UW |
7514 | ; |
7515 | ; Block and (NC) patterns. | |
7516 | ; | |
7517 | ||
7518 | (define_insn "*nc" | |
7519 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7520 | (and:BLK (match_dup 0) | |
7521 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7522 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7523 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7524 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7525 | "nc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7526 | [(set_attr "op_type" "SS") |
7527 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7528 | |
7529 | (define_split | |
7530 | [(set (match_operand 0 "memory_operand" "") | |
7531 | (and (match_dup 0) | |
7532 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7533 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7534 | "reload_completed |
7535 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7536 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7537 | [(parallel | |
7538 | [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) | |
7539 | (use (match_dup 2)) | |
ae156f85 | 7540 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7541 | { |
7542 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7543 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7544 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7545 | }) | |
7546 | ||
7547 | (define_peephole2 | |
7548 | [(parallel | |
7549 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7550 | (and:BLK (match_dup 0) | |
7551 | (match_operand:BLK 1 "memory_operand" ""))) | |
7552 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7553 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7554 | (parallel |
7555 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7556 | (and:BLK (match_dup 3) | |
7557 | (match_operand:BLK 4 "memory_operand" ""))) | |
7558 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7559 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7560 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7561 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7562 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7563 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7564 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7565 | [(parallel | |
7566 | [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) | |
7567 | (use (match_dup 8)) | |
ae156f85 | 7568 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7569 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7570 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7571 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7572 | ||
9db1d521 HP |
7573 | |
7574 | ;; | |
7575 | ;;- Bit set (inclusive or) instructions. | |
7576 | ;; | |
7577 | ||
047d35ed AS |
7578 | (define_expand "ior<mode>3" |
7579 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7580 | (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7581 | (match_operand:INT 2 "general_operand" ""))) | |
7582 | (clobber (reg:CC CC_REGNUM))] | |
7583 | "" | |
7584 | "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") | |
7585 | ||
9db1d521 HP |
7586 | ; |
7587 | ; iordi3 instruction pattern(s). | |
7588 | ; | |
7589 | ||
4023fb28 | 7590 | (define_insn "*iordi3_cc" |
ae156f85 | 7591 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7592 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7593 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7594 | (const_int 0))) |
3e4be43f | 7595 | (set (match_operand:DI 0 "register_operand" "=d,d,d") |
4023fb28 | 7596 | (ior:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7597 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7598 | "@ |
d40c829f | 7599 | ogr\t%0,%2 |
65b1d8ea | 7600 | ogrk\t%0,%1,%2 |
d40c829f | 7601 | og\t%0,%2" |
65b1d8ea AK |
7602 | [(set_attr "op_type" "RRE,RRF,RXY") |
7603 | (set_attr "cpu_facility" "*,z196,*") | |
7604 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 UW |
7605 | |
7606 | (define_insn "*iordi3_cconly" | |
ae156f85 | 7607 | [(set (reg CC_REGNUM) |
65b1d8ea | 7608 | (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
3e4be43f | 7609 | (match_operand:DI 2 "general_operand" " d,d,T")) |
4023fb28 | 7610 | (const_int 0))) |
65b1d8ea | 7611 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 7612 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7613 | "@ |
d40c829f | 7614 | ogr\t%0,%2 |
65b1d8ea | 7615 | ogrk\t%0,%1,%2 |
d40c829f | 7616 | og\t%0,%2" |
65b1d8ea AK |
7617 | [(set_attr "op_type" "RRE,RRF,RXY") |
7618 | (set_attr "cpu_facility" "*,z196,*") | |
7619 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7620 | |
3af8e996 | 7621 | (define_insn "*iordi3" |
65b1d8ea | 7622 | [(set (match_operand:DI 0 "nonimmediate_operand" |
3e4be43f | 7623 | "=d, d, d, d, d, d,d,d,d, AQ,Q") |
65b1d8ea | 7624 | (ior:DI (match_operand:DI 1 "nonimmediate_operand" |
3e4be43f | 7625 | " %0, 0, 0, 0, 0, 0,0,d,0, 0,0") |
ec24698e | 7626 | (match_operand:DI 2 "general_operand" |
3e4be43f | 7627 | "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,T,NxQD0,Q"))) |
ec24698e | 7628 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7629 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7630 | "@ |
7631 | oihh\t%0,%i2 | |
7632 | oihl\t%0,%i2 | |
7633 | oilh\t%0,%i2 | |
7634 | oill\t%0,%i2 | |
7635 | oihf\t%0,%k2 | |
7636 | oilf\t%0,%k2 | |
7637 | ogr\t%0,%2 | |
65b1d8ea | 7638 | ogrk\t%0,%1,%2 |
ec24698e UW |
7639 | og\t%0,%2 |
7640 | # | |
7641 | #" | |
65b1d8ea AK |
7642 | [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") |
7643 | (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") | |
9381e3f1 WG |
7644 | (set_attr "z10prop" "z10_super_E1, |
7645 | z10_super_E1, | |
7646 | z10_super_E1, | |
7647 | z10_super_E1, | |
7648 | z10_super_E1, | |
7649 | z10_super_E1, | |
7650 | z10_super_E1, | |
65b1d8ea | 7651 | *, |
9381e3f1 WG |
7652 | z10_super_E1, |
7653 | *, | |
7654 | *")]) | |
0dfa6c5e UW |
7655 | |
7656 | (define_split | |
7657 | [(set (match_operand:DI 0 "s_operand" "") | |
7658 | (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7659 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7660 | "reload_completed" |
7661 | [(parallel | |
7662 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7663 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7664 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7665 | |
9db1d521 HP |
7666 | ; |
7667 | ; iorsi3 instruction pattern(s). | |
7668 | ; | |
7669 | ||
4023fb28 | 7670 | (define_insn "*iorsi3_cc" |
ae156f85 | 7671 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7672 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7673 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7674 | (const_int 0))) |
65b1d8ea | 7675 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7676 | (ior:SI (match_dup 1) (match_dup 2)))] |
7677 | "s390_match_ccmode(insn, CCTmode)" | |
7678 | "@ | |
ec24698e | 7679 | oilf\t%0,%o2 |
d40c829f | 7680 | or\t%0,%2 |
65b1d8ea | 7681 | ork\t%0,%1,%2 |
d40c829f UW |
7682 | o\t%0,%2 |
7683 | oy\t%0,%2" | |
65b1d8ea | 7684 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7685 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea | 7686 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
4023fb28 UW |
7687 | |
7688 | (define_insn "*iorsi3_cconly" | |
ae156f85 | 7689 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7690 | (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7691 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7692 | (const_int 0))) |
65b1d8ea | 7693 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
7694 | "s390_match_ccmode(insn, CCTmode)" |
7695 | "@ | |
ec24698e | 7696 | oilf\t%0,%o2 |
d40c829f | 7697 | or\t%0,%2 |
65b1d8ea | 7698 | ork\t%0,%1,%2 |
d40c829f UW |
7699 | o\t%0,%2 |
7700 | oy\t%0,%2" | |
65b1d8ea | 7701 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 7702 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea | 7703 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) |
4023fb28 | 7704 | |
8cb66696 | 7705 | (define_insn "*iorsi3_zarch" |
65b1d8ea AK |
7706 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") |
7707 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") | |
7708 | (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 7709 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7710 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7711 | "@ |
f19a9af7 AK |
7712 | oilh\t%0,%i2 |
7713 | oill\t%0,%i2 | |
ec24698e | 7714 | oilf\t%0,%o2 |
d40c829f | 7715 | or\t%0,%2 |
65b1d8ea | 7716 | ork\t%0,%1,%2 |
d40c829f | 7717 | o\t%0,%2 |
8cb66696 | 7718 | oy\t%0,%2 |
0dfa6c5e | 7719 | # |
19b63d8e | 7720 | #" |
65b1d8ea | 7721 | [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") |
3e4be43f | 7722 | (set_attr "cpu_facility" "*,*,*,*,z196,*,longdisp,*,*") |
9381e3f1 WG |
7723 | (set_attr "z10prop" "z10_super_E1, |
7724 | z10_super_E1, | |
7725 | z10_super_E1, | |
7726 | z10_super_E1, | |
65b1d8ea | 7727 | *, |
9381e3f1 WG |
7728 | z10_super_E1, |
7729 | z10_super_E1, | |
7730 | *, | |
7731 | *")]) | |
8cb66696 UW |
7732 | |
7733 | (define_insn "*iorsi3_esa" | |
0dfa6c5e | 7734 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") |
bad82153 | 7735 | (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") |
0dfa6c5e | 7736 | (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) |
ae156f85 | 7737 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7738 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
f19a9af7 AK |
7739 | "@ |
7740 | or\t%0,%2 | |
8cb66696 | 7741 | o\t%0,%2 |
0dfa6c5e | 7742 | # |
19b63d8e | 7743 | #" |
9381e3f1 WG |
7744 | [(set_attr "op_type" "RR,RX,SI,SS") |
7745 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7746 | |
7747 | (define_split | |
7748 | [(set (match_operand:SI 0 "s_operand" "") | |
7749 | (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 7750 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7751 | "reload_completed" |
7752 | [(parallel | |
7753 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7754 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7755 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
4023fb28 | 7756 | |
4023fb28 UW |
7757 | ; |
7758 | ; iorhi3 instruction pattern(s). | |
7759 | ; | |
7760 | ||
8cb66696 | 7761 | (define_insn "*iorhi3_zarch" |
65b1d8ea AK |
7762 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
7763 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") | |
7764 | (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) | |
ae156f85 | 7765 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7766 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7767 | "@ |
d40c829f | 7768 | or\t%0,%2 |
65b1d8ea | 7769 | ork\t%0,%1,%2 |
8cb66696 | 7770 | oill\t%0,%x2 |
0dfa6c5e | 7771 | # |
19b63d8e | 7772 | #" |
65b1d8ea AK |
7773 | [(set_attr "op_type" "RR,RRF,RI,SI,SS") |
7774 | (set_attr "cpu_facility" "*,z196,*,*,*") | |
7775 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) | |
8cb66696 UW |
7776 | |
7777 | (define_insn "*iorhi3_esa" | |
0dfa6c5e UW |
7778 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") |
7779 | (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") | |
7780 | (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) | |
ae156f85 | 7781 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
7782 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
7783 | "@ | |
7784 | or\t%0,%2 | |
0dfa6c5e | 7785 | # |
19b63d8e | 7786 | #" |
9381e3f1 WG |
7787 | [(set_attr "op_type" "RR,SI,SS") |
7788 | (set_attr "z10prop" "z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7789 | |
7790 | (define_split | |
7791 | [(set (match_operand:HI 0 "s_operand" "") | |
7792 | (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 7793 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7794 | "reload_completed" |
7795 | [(parallel | |
7796 | [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7797 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7798 | "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") |
9db1d521 | 7799 | |
9db1d521 | 7800 | ; |
4023fb28 | 7801 | ; iorqi3 instruction pattern(s). |
9db1d521 HP |
7802 | ; |
7803 | ||
8cb66696 | 7804 | (define_insn "*iorqi3_zarch" |
65b1d8ea AK |
7805 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
7806 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") | |
7807 | (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) | |
ae156f85 | 7808 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7809 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
4023fb28 | 7810 | "@ |
d40c829f | 7811 | or\t%0,%2 |
65b1d8ea | 7812 | ork\t%0,%1,%2 |
8cb66696 | 7813 | oill\t%0,%b2 |
fc0ea003 UW |
7814 | oi\t%S0,%b2 |
7815 | oiy\t%S0,%b2 | |
19b63d8e | 7816 | #" |
65b1d8ea | 7817 | [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") |
3e4be43f | 7818 | (set_attr "cpu_facility" "*,z196,*,*,longdisp,*") |
65b1d8ea AK |
7819 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, |
7820 | z10_super,z10_super,*")]) | |
8cb66696 UW |
7821 | |
7822 | (define_insn "*iorqi3_esa" | |
7823 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") | |
7824 | (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") | |
7825 | (match_operand:QI 2 "general_operand" "d,n,Q"))) | |
ae156f85 | 7826 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 7827 | "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
9db1d521 | 7828 | "@ |
8cb66696 | 7829 | or\t%0,%2 |
fc0ea003 | 7830 | oi\t%S0,%b2 |
19b63d8e | 7831 | #" |
9381e3f1 WG |
7832 | [(set_attr "op_type" "RR,SI,SS") |
7833 | (set_attr "z10prop" "z10_super_E1,z10_super,*")]) | |
9db1d521 | 7834 | |
19b63d8e UW |
7835 | ; |
7836 | ; Block inclusive or (OC) patterns. | |
7837 | ; | |
7838 | ||
7839 | (define_insn "*oc" | |
7840 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
7841 | (ior:BLK (match_dup 0) | |
7842 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
7843 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 7844 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 7845 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 7846 | "oc\t%O0(%2,%R0),%S1" |
65b1d8ea AK |
7847 | [(set_attr "op_type" "SS") |
7848 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
7849 | |
7850 | (define_split | |
7851 | [(set (match_operand 0 "memory_operand" "") | |
7852 | (ior (match_dup 0) | |
7853 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 7854 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
7855 | "reload_completed |
7856 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
7857 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
7858 | [(parallel | |
7859 | [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) | |
7860 | (use (match_dup 2)) | |
ae156f85 | 7861 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7862 | { |
7863 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
7864 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
7865 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
7866 | }) | |
7867 | ||
7868 | (define_peephole2 | |
7869 | [(parallel | |
7870 | [(set (match_operand:BLK 0 "memory_operand" "") | |
7871 | (ior:BLK (match_dup 0) | |
7872 | (match_operand:BLK 1 "memory_operand" ""))) | |
7873 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 7874 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
7875 | (parallel |
7876 | [(set (match_operand:BLK 3 "memory_operand" "") | |
7877 | (ior:BLK (match_dup 3) | |
7878 | (match_operand:BLK 4 "memory_operand" ""))) | |
7879 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 7880 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7881 | "s390_offset_p (operands[0], operands[3], operands[2]) |
7882 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 7883 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 7884 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
7885 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
7886 | [(parallel | |
7887 | [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) | |
7888 | (use (match_dup 8)) | |
ae156f85 | 7889 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
7890 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
7891 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
7892 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
7893 | ||
9db1d521 HP |
7894 | |
7895 | ;; | |
7896 | ;;- Xor instructions. | |
7897 | ;; | |
7898 | ||
047d35ed AS |
7899 | (define_expand "xor<mode>3" |
7900 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7901 | (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") | |
7902 | (match_operand:INT 2 "general_operand" ""))) | |
7903 | (clobber (reg:CC CC_REGNUM))] | |
7904 | "" | |
7905 | "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") | |
7906 | ||
3c91f126 AK |
7907 | ; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing |
7908 | ; simplifications. So its better to have something matching. | |
7909 | (define_split | |
7910 | [(set (match_operand:INT 0 "nonimmediate_operand" "") | |
7911 | (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))] | |
7912 | "" | |
7913 | [(parallel | |
7914 | [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2))) | |
7915 | (clobber (reg:CC CC_REGNUM))])] | |
7916 | { | |
7917 | operands[2] = constm1_rtx; | |
7918 | if (!s390_logical_operator_ok_p (operands)) | |
7919 | FAIL; | |
7920 | }) | |
7921 | ||
9db1d521 HP |
7922 | ; |
7923 | ; xordi3 instruction pattern(s). | |
7924 | ; | |
7925 | ||
4023fb28 | 7926 | (define_insn "*xordi3_cc" |
ae156f85 | 7927 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7928 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7929 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7930 | (const_int 0))) |
3e4be43f | 7931 | (set (match_operand:DI 0 "register_operand" "=d,d,d") |
4023fb28 | 7932 | (xor:DI (match_dup 1) (match_dup 2)))] |
9602b6a1 | 7933 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7934 | "@ |
d40c829f | 7935 | xgr\t%0,%2 |
65b1d8ea | 7936 | xgrk\t%0,%1,%2 |
d40c829f | 7937 | xg\t%0,%2" |
65b1d8ea | 7938 | [(set_attr "op_type" "RRE,RRF,RXY") |
5490de28 | 7939 | (set_attr "cpu_facility" "*,z196,*") |
65b1d8ea | 7940 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) |
4023fb28 UW |
7941 | |
7942 | (define_insn "*xordi3_cconly" | |
ae156f85 | 7943 | [(set (reg CC_REGNUM) |
3e4be43f UW |
7944 | (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") |
7945 | (match_operand:DI 2 "general_operand" " d,d,T")) | |
4023fb28 | 7946 | (const_int 0))) |
3e4be43f | 7947 | (clobber (match_scratch:DI 0 "=d,d,d"))] |
9602b6a1 | 7948 | "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" |
4023fb28 | 7949 | "@ |
d40c829f | 7950 | xgr\t%0,%2 |
65b1d8ea | 7951 | xgrk\t%0,%1,%2 |
c7fd8cd8 | 7952 | xg\t%0,%2" |
65b1d8ea AK |
7953 | [(set_attr "op_type" "RRE,RRF,RXY") |
7954 | (set_attr "cpu_facility" "*,z196,*") | |
7955 | (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) | |
4023fb28 | 7956 | |
3af8e996 | 7957 | (define_insn "*xordi3" |
3e4be43f UW |
7958 | [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d,d, AQ,Q") |
7959 | (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d,0, 0,0") | |
7960 | (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,T,NxQD0,Q"))) | |
ec24698e | 7961 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 7962 | "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" |
ec24698e UW |
7963 | "@ |
7964 | xihf\t%0,%k2 | |
7965 | xilf\t%0,%k2 | |
7966 | xgr\t%0,%2 | |
65b1d8ea | 7967 | xgrk\t%0,%1,%2 |
ec24698e UW |
7968 | xg\t%0,%2 |
7969 | # | |
7970 | #" | |
65b1d8ea AK |
7971 | [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") |
7972 | (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") | |
7973 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, | |
7974 | *,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
7975 | |
7976 | (define_split | |
7977 | [(set (match_operand:DI 0 "s_operand" "") | |
7978 | (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) | |
ae156f85 | 7979 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
7980 | "reload_completed" |
7981 | [(parallel | |
7982 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 7983 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 7984 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
4023fb28 | 7985 | |
9db1d521 HP |
7986 | ; |
7987 | ; xorsi3 instruction pattern(s). | |
7988 | ; | |
7989 | ||
4023fb28 | 7990 | (define_insn "*xorsi3_cc" |
ae156f85 | 7991 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
7992 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
7993 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 7994 | (const_int 0))) |
65b1d8ea | 7995 | (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") |
4023fb28 UW |
7996 | (xor:SI (match_dup 1) (match_dup 2)))] |
7997 | "s390_match_ccmode(insn, CCTmode)" | |
7998 | "@ | |
ec24698e | 7999 | xilf\t%0,%o2 |
d40c829f | 8000 | xr\t%0,%2 |
65b1d8ea | 8001 | xrk\t%0,%1,%2 |
d40c829f UW |
8002 | x\t%0,%2 |
8003 | xy\t%0,%2" | |
65b1d8ea | 8004 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 8005 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea AK |
8006 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8007 | z10_super_E1,z10_super_E1")]) | |
4023fb28 UW |
8008 | |
8009 | (define_insn "*xorsi3_cconly" | |
ae156f85 | 8010 | [(set (reg CC_REGNUM) |
65b1d8ea AK |
8011 | (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") |
8012 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) | |
4023fb28 | 8013 | (const_int 0))) |
65b1d8ea | 8014 | (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] |
4023fb28 UW |
8015 | "s390_match_ccmode(insn, CCTmode)" |
8016 | "@ | |
ec24698e | 8017 | xilf\t%0,%o2 |
d40c829f | 8018 | xr\t%0,%2 |
65b1d8ea | 8019 | xrk\t%0,%1,%2 |
d40c829f UW |
8020 | x\t%0,%2 |
8021 | xy\t%0,%2" | |
65b1d8ea | 8022 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") |
3e4be43f | 8023 | (set_attr "cpu_facility" "*,*,z196,*,longdisp") |
65b1d8ea AK |
8024 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8025 | z10_super_E1,z10_super_E1")]) | |
9db1d521 | 8026 | |
8cb66696 | 8027 | (define_insn "*xorsi3" |
65b1d8ea AK |
8028 | [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") |
8029 | (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") | |
8030 | (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) | |
ae156f85 | 8031 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8032 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 8033 | "@ |
ec24698e | 8034 | xilf\t%0,%o2 |
d40c829f | 8035 | xr\t%0,%2 |
65b1d8ea | 8036 | xrk\t%0,%1,%2 |
d40c829f | 8037 | x\t%0,%2 |
8cb66696 | 8038 | xy\t%0,%2 |
0dfa6c5e | 8039 | # |
19b63d8e | 8040 | #" |
65b1d8ea | 8041 | [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") |
3e4be43f | 8042 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,*,*") |
65b1d8ea AK |
8043 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, |
8044 | z10_super_E1,z10_super_E1,*,*")]) | |
0dfa6c5e UW |
8045 | |
8046 | (define_split | |
8047 | [(set (match_operand:SI 0 "s_operand" "") | |
8048 | (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) | |
ae156f85 | 8049 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8050 | "reload_completed" |
8051 | [(parallel | |
8052 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8053 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8054 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
8cb66696 | 8055 | |
9db1d521 HP |
8056 | ; |
8057 | ; xorhi3 instruction pattern(s). | |
8058 | ; | |
8059 | ||
8cb66696 | 8060 | (define_insn "*xorhi3" |
65b1d8ea AK |
8061 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") |
8062 | (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") | |
8063 | (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) | |
ae156f85 | 8064 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 UW |
8065 | "s390_logical_operator_ok_p (operands)" |
8066 | "@ | |
ec24698e | 8067 | xilf\t%0,%x2 |
8cb66696 | 8068 | xr\t%0,%2 |
65b1d8ea | 8069 | xrk\t%0,%1,%2 |
0dfa6c5e | 8070 | # |
19b63d8e | 8071 | #" |
65b1d8ea AK |
8072 | [(set_attr "op_type" "RIL,RR,RRF,SI,SS") |
8073 | (set_attr "cpu_facility" "*,*,z196,*,*") | |
8074 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) | |
0dfa6c5e UW |
8075 | |
8076 | (define_split | |
8077 | [(set (match_operand:HI 0 "s_operand" "") | |
8078 | (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) | |
ae156f85 | 8079 | (clobber (reg:CC CC_REGNUM))] |
0dfa6c5e UW |
8080 | "reload_completed" |
8081 | [(parallel | |
8082 | [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) | |
ae156f85 | 8083 | (clobber (reg:CC CC_REGNUM))])] |
0dfa6c5e | 8084 | "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") |
9db1d521 | 8085 | |
9db1d521 HP |
8086 | ; |
8087 | ; xorqi3 instruction pattern(s). | |
8088 | ; | |
8089 | ||
8cb66696 | 8090 | (define_insn "*xorqi3" |
65b1d8ea AK |
8091 | [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") |
8092 | (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") | |
8093 | (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) | |
ae156f85 | 8094 | (clobber (reg:CC CC_REGNUM))] |
8cb66696 | 8095 | "s390_logical_operator_ok_p (operands)" |
9db1d521 | 8096 | "@ |
ec24698e | 8097 | xilf\t%0,%b2 |
8cb66696 | 8098 | xr\t%0,%2 |
65b1d8ea | 8099 | xrk\t%0,%1,%2 |
fc0ea003 UW |
8100 | xi\t%S0,%b2 |
8101 | xiy\t%S0,%b2 | |
19b63d8e | 8102 | #" |
65b1d8ea | 8103 | [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") |
3e4be43f | 8104 | (set_attr "cpu_facility" "*,*,z196,*,longdisp,*") |
65b1d8ea | 8105 | (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) |
9381e3f1 | 8106 | |
4023fb28 | 8107 | |
19b63d8e UW |
8108 | ; |
8109 | ; Block exclusive or (XC) patterns. | |
8110 | ; | |
8111 | ||
8112 | (define_insn "*xc" | |
8113 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8114 | (xor:BLK (match_dup 0) | |
8115 | (match_operand:BLK 1 "memory_operand" "Q"))) | |
8116 | (use (match_operand 2 "const_int_operand" "n")) | |
ae156f85 | 8117 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8118 | "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" |
fc0ea003 | 8119 | "xc\t%O0(%2,%R0),%S1" |
b628bd8e | 8120 | [(set_attr "op_type" "SS")]) |
19b63d8e UW |
8121 | |
8122 | (define_split | |
8123 | [(set (match_operand 0 "memory_operand" "") | |
8124 | (xor (match_dup 0) | |
8125 | (match_operand 1 "memory_operand" ""))) | |
ae156f85 | 8126 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e UW |
8127 | "reload_completed |
8128 | && GET_MODE (operands[0]) == GET_MODE (operands[1]) | |
8129 | && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" | |
8130 | [(parallel | |
8131 | [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) | |
8132 | (use (match_dup 2)) | |
ae156f85 | 8133 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8134 | { |
8135 | operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); | |
8136 | operands[0] = adjust_address (operands[0], BLKmode, 0); | |
8137 | operands[1] = adjust_address (operands[1], BLKmode, 0); | |
8138 | }) | |
8139 | ||
8140 | (define_peephole2 | |
8141 | [(parallel | |
8142 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8143 | (xor:BLK (match_dup 0) | |
8144 | (match_operand:BLK 1 "memory_operand" ""))) | |
8145 | (use (match_operand 2 "const_int_operand" "")) | |
ae156f85 | 8146 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8147 | (parallel |
8148 | [(set (match_operand:BLK 3 "memory_operand" "") | |
8149 | (xor:BLK (match_dup 3) | |
8150 | (match_operand:BLK 4 "memory_operand" ""))) | |
8151 | (use (match_operand 5 "const_int_operand" "")) | |
ae156f85 | 8152 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8153 | "s390_offset_p (operands[0], operands[3], operands[2]) |
8154 | && s390_offset_p (operands[1], operands[4], operands[2]) | |
9381e3f1 | 8155 | && !s390_overlap_p (operands[0], operands[1], |
bcf8c1cc | 8156 | INTVAL (operands[2]) + INTVAL (operands[5])) |
19b63d8e UW |
8157 | && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" |
8158 | [(parallel | |
8159 | [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) | |
8160 | (use (match_dup 8)) | |
ae156f85 | 8161 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8162 | "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8163 | operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); | |
8164 | operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") | |
8165 | ||
8166 | ; | |
8167 | ; Block xor (XC) patterns with src == dest. | |
8168 | ; | |
8169 | ||
8170 | (define_insn "*xc_zero" | |
8171 | [(set (match_operand:BLK 0 "memory_operand" "=Q") | |
8172 | (const_int 0)) | |
8173 | (use (match_operand 1 "const_int_operand" "n")) | |
ae156f85 | 8174 | (clobber (reg:CC CC_REGNUM))] |
19b63d8e | 8175 | "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" |
fc0ea003 | 8176 | "xc\t%O0(%1,%R0),%S0" |
65b1d8ea AK |
8177 | [(set_attr "op_type" "SS") |
8178 | (set_attr "z196prop" "z196_cracked")]) | |
19b63d8e UW |
8179 | |
8180 | (define_peephole2 | |
8181 | [(parallel | |
8182 | [(set (match_operand:BLK 0 "memory_operand" "") | |
8183 | (const_int 0)) | |
8184 | (use (match_operand 1 "const_int_operand" "")) | |
ae156f85 | 8185 | (clobber (reg:CC CC_REGNUM))]) |
19b63d8e UW |
8186 | (parallel |
8187 | [(set (match_operand:BLK 2 "memory_operand" "") | |
8188 | (const_int 0)) | |
8189 | (use (match_operand 3 "const_int_operand" "")) | |
ae156f85 | 8190 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8191 | "s390_offset_p (operands[0], operands[2], operands[1]) |
8192 | && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" | |
8193 | [(parallel | |
8194 | [(set (match_dup 4) (const_int 0)) | |
8195 | (use (match_dup 5)) | |
ae156f85 | 8196 | (clobber (reg:CC CC_REGNUM))])] |
19b63d8e UW |
8197 | "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); |
8198 | operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") | |
8199 | ||
9db1d521 HP |
8200 | |
8201 | ;; | |
8202 | ;;- Negate instructions. | |
8203 | ;; | |
8204 | ||
8205 | ; | |
9a91a21f | 8206 | ; neg(di|si)2 instruction pattern(s). |
9db1d521 HP |
8207 | ; |
8208 | ||
9a91a21f | 8209 | (define_expand "neg<mode>2" |
9db1d521 | 8210 | [(parallel |
9a91a21f AS |
8211 | [(set (match_operand:DSI 0 "register_operand" "=d") |
8212 | (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) | |
ae156f85 | 8213 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8214 | "" |
8215 | "") | |
8216 | ||
26a89301 | 8217 | (define_insn "*negdi2_sign_cc" |
ae156f85 | 8218 | [(set (reg CC_REGNUM) |
26a89301 UW |
8219 | (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8220 | (match_operand:SI 1 "register_operand" "d") 0) | |
8221 | (const_int 32)) (const_int 32))) | |
8222 | (const_int 0))) | |
8223 | (set (match_operand:DI 0 "register_operand" "=d") | |
8224 | (neg:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8225 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8226 | "lcgfr\t%0,%1" |
729e750f WG |
8227 | [(set_attr "op_type" "RRE") |
8228 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8229 | |
26a89301 UW |
8230 | (define_insn "*negdi2_sign" |
8231 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8232 | (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8233 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8234 | "TARGET_ZARCH" |
26a89301 | 8235 | "lcgfr\t%0,%1" |
729e750f WG |
8236 | [(set_attr "op_type" "RRE") |
8237 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8238 | |
43a09b63 | 8239 | ; lcr, lcgr |
9a91a21f | 8240 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8241 | [(set (reg CC_REGNUM) |
9a91a21f | 8242 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8243 | (const_int 0))) |
9a91a21f AS |
8244 | (set (match_operand:GPR 0 "register_operand" "=d") |
8245 | (neg:GPR (match_dup 1)))] | |
8246 | "s390_match_ccmode (insn, CCAmode)" | |
8247 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8248 | [(set_attr "op_type" "RR<E>") |
8249 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
8250 | |
8251 | ; lcr, lcgr | |
9a91a21f | 8252 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8253 | [(set (reg CC_REGNUM) |
9a91a21f | 8254 | (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8255 | (const_int 0))) |
9a91a21f AS |
8256 | (clobber (match_scratch:GPR 0 "=d"))] |
8257 | "s390_match_ccmode (insn, CCAmode)" | |
8258 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8259 | [(set_attr "op_type" "RR<E>") |
8260 | (set_attr "z10prop" "z10_super_c_E1")]) | |
43a09b63 AK |
8261 | |
8262 | ; lcr, lcgr | |
9a91a21f AS |
8263 | (define_insn "*neg<mode>2" |
8264 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8265 | (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8266 | (clobber (reg:CC CC_REGNUM))] |
9a91a21f AS |
8267 | "" |
8268 | "lc<g>r\t%0,%1" | |
9381e3f1 WG |
8269 | [(set_attr "op_type" "RR<E>") |
8270 | (set_attr "z10prop" "z10_super_c_E1")]) | |
9db1d521 | 8271 | |
b7d19263 | 8272 | (define_insn "*negdi2_31" |
9db1d521 HP |
8273 | [(set (match_operand:DI 0 "register_operand" "=d") |
8274 | (neg:DI (match_operand:DI 1 "register_operand" "d"))) | |
ae156f85 | 8275 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8276 | "!TARGET_ZARCH" |
b7d19263 AK |
8277 | "#") |
8278 | ||
8279 | ; Split a DImode NEG on 31bit into 2 SImode NEGs | |
8280 | ||
8281 | ; Doing the twos complement separately on the SImode parts does an | |
8282 | ; unwanted +1 on the high part which needs to be subtracted afterwards | |
8283 | ; ... unless the +1 on the low part created an overflow. | |
8284 | ||
8285 | (define_split | |
8286 | [(set (match_operand:DI 0 "register_operand" "") | |
8287 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8288 | (clobber (reg:CC CC_REGNUM))] | |
8289 | "!TARGET_ZARCH | |
8290 | && (REGNO (operands[0]) == REGNO (operands[1]) | |
8291 | || s390_split_ok_p (operands[0], operands[1], DImode, 0)) | |
8292 | && reload_completed" | |
26a89301 UW |
8293 | [(parallel |
8294 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
ae156f85 | 8295 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 | 8296 | (parallel |
ae156f85 | 8297 | [(set (reg:CCAP CC_REGNUM) |
26a89301 UW |
8298 | (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) |
8299 | (set (match_dup 4) (neg:SI (match_dup 5)))]) | |
8300 | (set (pc) | |
ae156f85 | 8301 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) |
26a89301 UW |
8302 | (pc) |
8303 | (label_ref (match_dup 6)))) | |
8304 | (parallel | |
8305 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
ae156f85 | 8306 | (clobber (reg:CC CC_REGNUM))]) |
26a89301 UW |
8307 | (match_dup 6)] |
8308 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8309 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8310 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8311 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8312 | operands[6] = gen_label_rtx ();") | |
9db1d521 | 8313 | |
b7d19263 AK |
8314 | ; Like above but first make a copy of the low part of the src operand |
8315 | ; since it might overlap with the high part of the destination. | |
8316 | ||
8317 | (define_split | |
8318 | [(set (match_operand:DI 0 "register_operand" "") | |
8319 | (neg:DI (match_operand:DI 1 "register_operand" ""))) | |
8320 | (clobber (reg:CC CC_REGNUM))] | |
8321 | "!TARGET_ZARCH | |
8322 | && s390_split_ok_p (operands[0], operands[1], DImode, 1) | |
8323 | && reload_completed" | |
8324 | [; Make a backup of op5 first | |
8325 | (set (match_dup 4) (match_dup 5)) | |
8326 | ; Setting op2 here might clobber op5 | |
8327 | (parallel | |
8328 | [(set (match_dup 2) (neg:SI (match_dup 3))) | |
8329 | (clobber (reg:CC CC_REGNUM))]) | |
8330 | (parallel | |
8331 | [(set (reg:CCAP CC_REGNUM) | |
8332 | (compare:CCAP (neg:SI (match_dup 4)) (const_int 0))) | |
8333 | (set (match_dup 4) (neg:SI (match_dup 4)))]) | |
8334 | (set (pc) | |
8335 | (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) | |
8336 | (pc) | |
8337 | (label_ref (match_dup 6)))) | |
8338 | (parallel | |
8339 | [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) | |
8340 | (clobber (reg:CC CC_REGNUM))]) | |
8341 | (match_dup 6)] | |
8342 | "operands[2] = operand_subword (operands[0], 0, 0, DImode); | |
8343 | operands[3] = operand_subword (operands[1], 0, 0, DImode); | |
8344 | operands[4] = operand_subword (operands[0], 1, 0, DImode); | |
8345 | operands[5] = operand_subword (operands[1], 1, 0, DImode); | |
8346 | operands[6] = gen_label_rtx ();") | |
8347 | ||
9db1d521 | 8348 | ; |
f5905b37 | 8349 | ; neg(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8350 | ; |
8351 | ||
f5905b37 | 8352 | (define_expand "neg<mode>2" |
9db1d521 | 8353 | [(parallel |
7b6baae1 AK |
8354 | [(set (match_operand:BFP 0 "register_operand" "=f") |
8355 | (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 8356 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8357 | "TARGET_HARD_FLOAT" |
8358 | "") | |
8359 | ||
43a09b63 | 8360 | ; lcxbr, lcdbr, lcebr |
f5905b37 | 8361 | (define_insn "*neg<mode>2_cc" |
ae156f85 | 8362 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8363 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8364 | (match_operand:BFP 2 "const0_operand" ""))) | |
8365 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8366 | (neg:BFP (match_dup 1)))] | |
142cd70f | 8367 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8368 | "lc<xde>br\t%0,%1" |
26a89301 | 8369 | [(set_attr "op_type" "RRE") |
f5905b37 | 8370 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8371 | |
8372 | ; lcxbr, lcdbr, lcebr | |
f5905b37 | 8373 | (define_insn "*neg<mode>2_cconly" |
ae156f85 | 8374 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8375 | (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) |
8376 | (match_operand:BFP 2 "const0_operand" ""))) | |
8377 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8378 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8379 | "lc<xde>br\t%0,%1" |
26a89301 | 8380 | [(set_attr "op_type" "RRE") |
f5905b37 | 8381 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8382 | |
85dae55a AK |
8383 | ; lcdfr |
8384 | (define_insn "*neg<mode>2_nocc" | |
609e7e80 AK |
8385 | [(set (match_operand:FP 0 "register_operand" "=f") |
8386 | (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8387 | "TARGET_DFP" |
85dae55a AK |
8388 | "lcdfr\t%0,%1" |
8389 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8390 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8391 | |
43a09b63 | 8392 | ; lcxbr, lcdbr, lcebr |
6e5b5de8 | 8393 | ; FIXME: wflcdb does not clobber cc |
f5905b37 | 8394 | (define_insn "*neg<mode>2" |
62d3f261 AK |
8395 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8396 | (neg:BFP (match_operand:BFP 1 "register_operand" "f,v"))) | |
ae156f85 | 8397 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8398 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8399 | "@ |
8400 | lc<xde>br\t%0,%1 | |
8401 | wflcdb\t%0,%1" | |
8402 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8403 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8404 | (set_attr "type" "fsimp<mode>,*") |
8405 | (set_attr "enabled" "*,<DFDI>")]) | |
9db1d521 | 8406 | |
9db1d521 HP |
8407 | |
8408 | ;; | |
8409 | ;;- Absolute value instructions. | |
8410 | ;; | |
8411 | ||
8412 | ; | |
9a91a21f | 8413 | ; abs(di|si)2 instruction pattern(s). |
9db1d521 HP |
8414 | ; |
8415 | ||
26a89301 | 8416 | (define_insn "*absdi2_sign_cc" |
ae156f85 | 8417 | [(set (reg CC_REGNUM) |
26a89301 UW |
8418 | (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8419 | (match_operand:SI 1 "register_operand" "d") 0) | |
8420 | (const_int 32)) (const_int 32))) | |
8421 | (const_int 0))) | |
8422 | (set (match_operand:DI 0 "register_operand" "=d") | |
8423 | (abs:DI (sign_extend:DI (match_dup 1))))] | |
9602b6a1 | 8424 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8425 | "lpgfr\t%0,%1" |
729e750f WG |
8426 | [(set_attr "op_type" "RRE") |
8427 | (set_attr "z10prop" "z10_c")]) | |
26a89301 UW |
8428 | |
8429 | (define_insn "*absdi2_sign" | |
8430 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8431 | (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) | |
ae156f85 | 8432 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8433 | "TARGET_ZARCH" |
26a89301 | 8434 | "lpgfr\t%0,%1" |
729e750f WG |
8435 | [(set_attr "op_type" "RRE") |
8436 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8437 | |
43a09b63 | 8438 | ; lpr, lpgr |
9a91a21f | 8439 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8440 | [(set (reg CC_REGNUM) |
9a91a21f | 8441 | (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) |
26a89301 | 8442 | (const_int 0))) |
9a91a21f AS |
8443 | (set (match_operand:GPR 0 "register_operand" "=d") |
8444 | (abs:GPR (match_dup 1)))] | |
26a89301 | 8445 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8446 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8447 | [(set_attr "op_type" "RR<E>") |
8448 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 | 8449 | |
9381e3f1 | 8450 | ; lpr, lpgr |
9a91a21f | 8451 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8452 | [(set (reg CC_REGNUM) |
9a91a21f | 8453 | (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) |
26a89301 | 8454 | (const_int 0))) |
9a91a21f | 8455 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8456 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8457 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8458 | [(set_attr "op_type" "RR<E>") |
8459 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8460 | |
8461 | ; lpr, lpgr | |
9a91a21f AS |
8462 | (define_insn "abs<mode>2" |
8463 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8464 | (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) | |
ae156f85 | 8465 | (clobber (reg:CC CC_REGNUM))] |
9db1d521 | 8466 | "" |
9a91a21f | 8467 | "lp<g>r\t%0,%1" |
9381e3f1 WG |
8468 | [(set_attr "op_type" "RR<E>") |
8469 | (set_attr "z10prop" "z10_c")]) | |
9db1d521 | 8470 | |
9db1d521 | 8471 | ; |
f5905b37 | 8472 | ; abs(df|sf)2 instruction pattern(s). |
9db1d521 HP |
8473 | ; |
8474 | ||
f5905b37 | 8475 | (define_expand "abs<mode>2" |
9db1d521 | 8476 | [(parallel |
7b6baae1 AK |
8477 | [(set (match_operand:BFP 0 "register_operand" "=f") |
8478 | (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) | |
ae156f85 | 8479 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8480 | "TARGET_HARD_FLOAT" |
8481 | "") | |
8482 | ||
43a09b63 | 8483 | ; lpxbr, lpdbr, lpebr |
f5905b37 | 8484 | (define_insn "*abs<mode>2_cc" |
ae156f85 | 8485 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8486 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8487 | (match_operand:BFP 2 "const0_operand" ""))) | |
8488 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8489 | (abs:BFP (match_dup 1)))] | |
142cd70f | 8490 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8491 | "lp<xde>br\t%0,%1" |
26a89301 | 8492 | [(set_attr "op_type" "RRE") |
f5905b37 | 8493 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8494 | |
8495 | ; lpxbr, lpdbr, lpebr | |
f5905b37 | 8496 | (define_insn "*abs<mode>2_cconly" |
ae156f85 | 8497 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8498 | (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) |
8499 | (match_operand:BFP 2 "const0_operand" ""))) | |
8500 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8501 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8502 | "lp<xde>br\t%0,%1" |
26a89301 | 8503 | [(set_attr "op_type" "RRE") |
f5905b37 | 8504 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8505 | |
85dae55a AK |
8506 | ; lpdfr |
8507 | (define_insn "*abs<mode>2_nocc" | |
609e7e80 AK |
8508 | [(set (match_operand:FP 0 "register_operand" "=f") |
8509 | (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] | |
fb068247 | 8510 | "TARGET_DFP" |
85dae55a AK |
8511 | "lpdfr\t%0,%1" |
8512 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8513 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8514 | |
43a09b63 | 8515 | ; lpxbr, lpdbr, lpebr |
6e5b5de8 | 8516 | ; FIXME: wflpdb does not clobber cc |
f5905b37 | 8517 | (define_insn "*abs<mode>2" |
62d3f261 AK |
8518 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8519 | (abs:BFP (match_operand:BFP 1 "register_operand" "f,v"))) | |
ae156f85 | 8520 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8521 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8522 | "@ |
8523 | lp<xde>br\t%0,%1 | |
8524 | wflpdb\t%0,%1" | |
8525 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8526 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8527 | (set_attr "type" "fsimp<mode>,*") |
8528 | (set_attr "enabled" "*,<DFDI>")]) | |
9db1d521 | 8529 | |
9db1d521 | 8530 | |
3ef093a8 AK |
8531 | ;; |
8532 | ;;- Negated absolute value instructions | |
8533 | ;; | |
8534 | ||
8535 | ; | |
8536 | ; Integer | |
8537 | ; | |
8538 | ||
26a89301 | 8539 | (define_insn "*negabsdi2_sign_cc" |
ae156f85 | 8540 | [(set (reg CC_REGNUM) |
26a89301 UW |
8541 | (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI |
8542 | (match_operand:SI 1 "register_operand" "d") 0) | |
8543 | (const_int 32)) (const_int 32)))) | |
8544 | (const_int 0))) | |
8545 | (set (match_operand:DI 0 "register_operand" "=d") | |
8546 | (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] | |
9602b6a1 | 8547 | "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" |
26a89301 | 8548 | "lngfr\t%0,%1" |
729e750f WG |
8549 | [(set_attr "op_type" "RRE") |
8550 | (set_attr "z10prop" "z10_c")]) | |
9381e3f1 | 8551 | |
26a89301 UW |
8552 | (define_insn "*negabsdi2_sign" |
8553 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8554 | (neg:DI (abs:DI (sign_extend:DI | |
8555 | (match_operand:SI 1 "register_operand" "d"))))) | |
ae156f85 | 8556 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8557 | "TARGET_ZARCH" |
26a89301 | 8558 | "lngfr\t%0,%1" |
729e750f WG |
8559 | [(set_attr "op_type" "RRE") |
8560 | (set_attr "z10prop" "z10_c")]) | |
3ef093a8 | 8561 | |
43a09b63 | 8562 | ; lnr, lngr |
9a91a21f | 8563 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8564 | [(set (reg CC_REGNUM) |
9a91a21f | 8565 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8566 | (const_int 0))) |
9a91a21f AS |
8567 | (set (match_operand:GPR 0 "register_operand" "=d") |
8568 | (neg:GPR (abs:GPR (match_dup 1))))] | |
26a89301 | 8569 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8570 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8571 | [(set_attr "op_type" "RR<E>") |
8572 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8573 | |
8574 | ; lnr, lngr | |
9a91a21f | 8575 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8576 | [(set (reg CC_REGNUM) |
9a91a21f | 8577 | (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) |
26a89301 | 8578 | (const_int 0))) |
9a91a21f | 8579 | (clobber (match_scratch:GPR 0 "=d"))] |
26a89301 | 8580 | "s390_match_ccmode (insn, CCAmode)" |
9a91a21f | 8581 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8582 | [(set_attr "op_type" "RR<E>") |
8583 | (set_attr "z10prop" "z10_c")]) | |
43a09b63 AK |
8584 | |
8585 | ; lnr, lngr | |
9a91a21f AS |
8586 | (define_insn "*negabs<mode>2" |
8587 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8588 | (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) | |
ae156f85 | 8589 | (clobber (reg:CC CC_REGNUM))] |
26a89301 | 8590 | "" |
9a91a21f | 8591 | "ln<g>r\t%0,%1" |
9381e3f1 WG |
8592 | [(set_attr "op_type" "RR<E>") |
8593 | (set_attr "z10prop" "z10_c")]) | |
26a89301 | 8594 | |
3ef093a8 AK |
8595 | ; |
8596 | ; Floating point | |
8597 | ; | |
8598 | ||
43a09b63 | 8599 | ; lnxbr, lndbr, lnebr |
f5905b37 | 8600 | (define_insn "*negabs<mode>2_cc" |
ae156f85 | 8601 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8602 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8603 | (match_operand:BFP 2 "const0_operand" ""))) | |
8604 | (set (match_operand:BFP 0 "register_operand" "=f") | |
8605 | (neg:BFP (abs:BFP (match_dup 1))))] | |
142cd70f | 8606 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8607 | "ln<xde>br\t%0,%1" |
26a89301 | 8608 | [(set_attr "op_type" "RRE") |
f5905b37 | 8609 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 AK |
8610 | |
8611 | ; lnxbr, lndbr, lnebr | |
f5905b37 | 8612 | (define_insn "*negabs<mode>2_cconly" |
ae156f85 | 8613 | [(set (reg CC_REGNUM) |
7b6baae1 AK |
8614 | (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) |
8615 | (match_operand:BFP 2 "const0_operand" ""))) | |
8616 | (clobber (match_scratch:BFP 0 "=f"))] | |
142cd70f | 8617 | "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" |
f61a2c7d | 8618 | "ln<xde>br\t%0,%1" |
26a89301 | 8619 | [(set_attr "op_type" "RRE") |
f5905b37 | 8620 | (set_attr "type" "fsimp<mode>")]) |
43a09b63 | 8621 | |
85dae55a AK |
8622 | ; lndfr |
8623 | (define_insn "*negabs<mode>2_nocc" | |
609e7e80 AK |
8624 | [(set (match_operand:FP 0 "register_operand" "=f") |
8625 | (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] | |
fb068247 | 8626 | "TARGET_DFP" |
85dae55a AK |
8627 | "lndfr\t%0,%1" |
8628 | [(set_attr "op_type" "RRE") | |
9381e3f1 | 8629 | (set_attr "type" "fsimp<mode>")]) |
85dae55a | 8630 | |
43a09b63 | 8631 | ; lnxbr, lndbr, lnebr |
6e5b5de8 | 8632 | ; FIXME: wflndb does not clobber cc |
f5905b37 | 8633 | (define_insn "*negabs<mode>2" |
62d3f261 AK |
8634 | [(set (match_operand:BFP 0 "register_operand" "=f,v") |
8635 | (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,v")))) | |
ae156f85 | 8636 | (clobber (reg:CC CC_REGNUM))] |
142cd70f | 8637 | "TARGET_HARD_FLOAT" |
6e5b5de8 AK |
8638 | "@ |
8639 | ln<xde>br\t%0,%1 | |
8640 | wflndb\t%0,%1" | |
8641 | [(set_attr "op_type" "RRE,VRR") | |
285363a1 | 8642 | (set_attr "cpu_facility" "*,vx") |
62d3f261 AK |
8643 | (set_attr "type" "fsimp<mode>,*") |
8644 | (set_attr "enabled" "*,<DFDI>")]) | |
26a89301 | 8645 | |
4023fb28 UW |
8646 | ;; |
8647 | ;;- Square root instructions. | |
8648 | ;; | |
8649 | ||
8650 | ; | |
f5905b37 | 8651 | ; sqrt(df|sf)2 instruction pattern(s). |
4023fb28 UW |
8652 | ; |
8653 | ||
9381e3f1 | 8654 | ; sqxbr, sqdbr, sqebr, sqdb, sqeb |
f5905b37 | 8655 | (define_insn "sqrt<mode>2" |
62d3f261 AK |
8656 | [(set (match_operand:BFP 0 "register_operand" "=f,f,v") |
8657 | (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,R,v")))] | |
142cd70f | 8658 | "TARGET_HARD_FLOAT" |
4023fb28 | 8659 | "@ |
f61a2c7d | 8660 | sq<xde>br\t%0,%1 |
6e5b5de8 AK |
8661 | sq<xde>b\t%0,%1 |
8662 | wfsqdb\t%v0,%v1" | |
8663 | [(set_attr "op_type" "RRE,RXE,VRR") | |
8664 | (set_attr "type" "fsqrt<mode>") | |
285363a1 | 8665 | (set_attr "cpu_facility" "*,*,vx") |
62d3f261 | 8666 | (set_attr "enabled" "*,<DSF>,<DFDI>")]) |
4023fb28 | 8667 | |
9db1d521 HP |
8668 | |
8669 | ;; | |
8670 | ;;- One complement instructions. | |
8671 | ;; | |
8672 | ||
8673 | ; | |
342cf42b | 8674 | ; one_cmpl(di|si|hi|qi)2 instruction pattern(s). |
9db1d521 | 8675 | ; |
c7453384 | 8676 | |
342cf42b | 8677 | (define_expand "one_cmpl<mode>2" |
4023fb28 | 8678 | [(parallel |
342cf42b AS |
8679 | [(set (match_operand:INT 0 "register_operand" "") |
8680 | (xor:INT (match_operand:INT 1 "register_operand" "") | |
8681 | (const_int -1))) | |
ae156f85 | 8682 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 | 8683 | "" |
4023fb28 | 8684 | "") |
9db1d521 HP |
8685 | |
8686 | ||
ec24698e UW |
8687 | ;; |
8688 | ;; Find leftmost bit instructions. | |
8689 | ;; | |
8690 | ||
8691 | (define_expand "clzdi2" | |
8692 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8693 | (clz:DI (match_operand:DI 1 "register_operand" "d")))] | |
9602b6a1 | 8694 | "TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e | 8695 | { |
d8485bdb TS |
8696 | rtx_insn *insn; |
8697 | rtx clz_equal; | |
ec24698e | 8698 | rtx wide_reg = gen_reg_rtx (TImode); |
406fde6e | 8699 | rtx msb = gen_rtx_CONST_INT (DImode, HOST_WIDE_INT_1U << 63); |
ec24698e UW |
8700 | |
8701 | clz_equal = gen_rtx_CLZ (DImode, operands[1]); | |
8702 | ||
8703 | emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); | |
8704 | ||
9381e3f1 | 8705 | insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); |
bd94cb6e | 8706 | set_unique_reg_note (insn, REG_EQUAL, clz_equal); |
ec24698e UW |
8707 | |
8708 | DONE; | |
8709 | }) | |
8710 | ||
8711 | (define_insn "clztidi2" | |
8712 | [(set (match_operand:TI 0 "register_operand" "=d") | |
8713 | (ior:TI | |
9381e3f1 WG |
8714 | (ashift:TI |
8715 | (zero_extend:TI | |
ec24698e UW |
8716 | (xor:DI (match_operand:DI 1 "register_operand" "d") |
8717 | (lshiftrt (match_operand:DI 2 "const_int_operand" "") | |
8718 | (subreg:SI (clz:DI (match_dup 1)) 4)))) | |
9381e3f1 | 8719 | |
ec24698e UW |
8720 | (const_int 64)) |
8721 | (zero_extend:TI (clz:DI (match_dup 1))))) | |
8722 | (clobber (reg:CC CC_REGNUM))] | |
406fde6e | 8723 | "UINTVAL (operands[2]) == HOST_WIDE_INT_1U << 63 |
9602b6a1 | 8724 | && TARGET_EXTIMM && TARGET_ZARCH" |
ec24698e UW |
8725 | "flogr\t%0,%1" |
8726 | [(set_attr "op_type" "RRE")]) | |
8727 | ||
8728 | ||
9db1d521 HP |
8729 | ;; |
8730 | ;;- Rotate instructions. | |
8731 | ;; | |
8732 | ||
8733 | ; | |
9a91a21f | 8734 | ; rotl(di|si)3 instruction pattern(s). |
9db1d521 HP |
8735 | ; |
8736 | ||
191eb16d AK |
8737 | (define_expand "rotl<mode>3" |
8738 | [(set (match_operand:GPR 0 "register_operand" "") | |
8739 | (rotate:GPR (match_operand:GPR 1 "register_operand" "") | |
8740 | (match_operand:SI 2 "nonmemory_operand" "")))] | |
9e8327e3 | 8741 | "TARGET_CPU_ZARCH" |
191eb16d | 8742 | "") |
9db1d521 | 8743 | |
43a09b63 | 8744 | ; rll, rllg |
191eb16d AK |
8745 | (define_insn "*rotl<mode>3<addr_style_op><masked_op>" |
8746 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
8747 | (rotate:GPR (match_operand:GPR 1 "register_operand" "d") | |
8748 | (match_operand:SI 2 "nonmemory_operand" "an")))] | |
8749 | "TARGET_CPU_ZARCH" | |
8750 | "rll<g>\t%0,%1,<addr_style_op_ops>" | |
4989e88a | 8751 | [(set_attr "op_type" "RSE") |
9381e3f1 | 8752 | (set_attr "atype" "reg") |
191eb16d | 8753 | (set_attr "z10prop" "z10_super_E1")]) |
4989e88a | 8754 | |
9db1d521 HP |
8755 | |
8756 | ;; | |
f337b930 | 8757 | ;;- Shift instructions. |
9db1d521 | 8758 | ;; |
9db1d521 HP |
8759 | |
8760 | ; | |
1b48c8cc | 8761 | ; (ashl|lshr)(di|si)3 instruction pattern(s). |
65b1d8ea | 8762 | ; Left shifts and logical right shifts |
9db1d521 | 8763 | |
1b48c8cc AS |
8764 | (define_expand "<shift><mode>3" |
8765 | [(set (match_operand:DSI 0 "register_operand" "") | |
8766 | (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") | |
adf22b3f | 8767 | (match_operand:SI 2 "nonmemory_operand" "")))] |
9db1d521 HP |
8768 | "" |
8769 | "") | |
8770 | ||
adf22b3f | 8771 | ; ESA 64 bit register pair shift with reg or imm shift count |
43a09b63 | 8772 | ; sldl, srdl |
adf22b3f AK |
8773 | (define_insn "*<shift>di3_31<addr_style_op><masked_op>" |
8774 | [(set (match_operand:DI 0 "register_operand" "=d") | |
8775 | (SHIFT:DI (match_operand:DI 1 "register_operand" "0") | |
8776 | (match_operand:SI 2 "nonmemory_operand" "an")))] | |
9602b6a1 | 8777 | "!TARGET_ZARCH" |
adf22b3f | 8778 | "s<lr>dl\t%0,<addr_style_op_ops>" |
077dab3b | 8779 | [(set_attr "op_type" "RS") |
65b1d8ea AK |
8780 | (set_attr "atype" "reg") |
8781 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 8782 | |
adf22b3f AK |
8783 | |
8784 | ; 64 bit register shift with reg or imm shift count | |
65b1d8ea | 8785 | ; sll, srl, sllg, srlg, sllk, srlk |
adf22b3f AK |
8786 | (define_insn "*<shift><mode>3<addr_style_op><masked_op>" |
8787 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
8788 | (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
8789 | (match_operand:SI 2 "nonmemory_operand" "an,an")))] | |
1b48c8cc | 8790 | "" |
65b1d8ea | 8791 | "@ |
adf22b3f AK |
8792 | s<lr>l<g>\t%0,<1><addr_style_op_ops> |
8793 | s<lr>l<gk>\t%0,%1,<addr_style_op_ops>" | |
65b1d8ea AK |
8794 | [(set_attr "op_type" "RS<E>,RSY") |
8795 | (set_attr "atype" "reg,reg") | |
8796 | (set_attr "cpu_facility" "*,z196") | |
adf22b3f | 8797 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8798 | |
9db1d521 | 8799 | ; |
1b48c8cc | 8800 | ; ashr(di|si)3 instruction pattern(s). |
65b1d8ea | 8801 | ; Arithmetic right shifts |
9db1d521 | 8802 | |
1b48c8cc | 8803 | (define_expand "ashr<mode>3" |
9db1d521 | 8804 | [(parallel |
1b48c8cc AS |
8805 | [(set (match_operand:DSI 0 "register_operand" "") |
8806 | (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") | |
a9fcf821 | 8807 | (match_operand:SI 2 "nonmemory_operand" ""))) |
ae156f85 | 8808 | (clobber (reg:CC CC_REGNUM))])] |
9db1d521 HP |
8809 | "" |
8810 | "") | |
8811 | ||
a9fcf821 AK |
8812 | ; FIXME: The number of alternatives is doubled here to match the fix |
8813 | ; number of 2 in the subst pattern for the (clobber (match_scratch... | |
8814 | ; The right fix should be to support match_scratch in the output | |
8815 | ; pattern of a define_subst. | |
8816 | (define_insn "*ashrdi3_31<addr_style_op_cc><masked_op_cc><setcc><cconly>" | |
8817 | [(set (match_operand:DI 0 "register_operand" "=d, d") | |
8818 | (ashiftrt:DI (match_operand:DI 1 "register_operand" "0, 0") | |
8819 | (match_operand:SI 2 "nonmemory_operand" "an,an"))) | |
ae156f85 | 8820 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 8821 | "!TARGET_ZARCH" |
65b1d8ea | 8822 | "@ |
a9fcf821 AK |
8823 | srda\t%0,<addr_style_op_cc_ops> |
8824 | srda\t%0,<addr_style_op_cc_ops>" | |
8825 | [(set_attr "op_type" "RS") | |
8826 | (set_attr "atype" "reg")]) | |
ecbe845e | 8827 | |
ecbe845e | 8828 | |
43a09b63 | 8829 | ; sra, srag |
a9fcf821 AK |
8830 | (define_insn "*ashr<mode>3<addr_style_op_cc><masked_op_cc><setcc><cconly>" |
8831 | [(set (match_operand:GPR 0 "register_operand" "=d, d") | |
8832 | (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>, d") | |
8833 | (match_operand:SI 2 "nonmemory_operand" "an,an"))) | |
ae156f85 | 8834 | (clobber (reg:CC CC_REGNUM))] |
1b48c8cc | 8835 | "" |
65b1d8ea | 8836 | "@ |
a9fcf821 AK |
8837 | sra<g>\t%0,<1><addr_style_op_cc_ops> |
8838 | sra<gk>\t%0,%1,<addr_style_op_cc_ops>" | |
65b1d8ea | 8839 | [(set_attr "op_type" "RS<E>,RSY") |
a9fcf821 | 8840 | (set_attr "atype" "reg") |
01496eca | 8841 | (set_attr "cpu_facility" "*,z196") |
65b1d8ea | 8842 | (set_attr "z10prop" "z10_super_E1,*")]) |
4989e88a | 8843 | |
9db1d521 | 8844 | |
9db1d521 HP |
8845 | ;; |
8846 | ;; Branch instruction patterns. | |
8847 | ;; | |
8848 | ||
f90b7a5a | 8849 | (define_expand "cbranch<mode>4" |
fa77b251 | 8850 | [(set (pc) |
f90b7a5a PB |
8851 | (if_then_else (match_operator 0 "comparison_operator" |
8852 | [(match_operand:GPR 1 "register_operand" "") | |
8853 | (match_operand:GPR 2 "general_operand" "")]) | |
8854 | (label_ref (match_operand 3 "" "")) | |
fa77b251 | 8855 | (pc)))] |
ba956982 | 8856 | "" |
f90b7a5a PB |
8857 | "s390_emit_jump (operands[3], |
8858 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8859 | DONE;") | |
8860 | ||
8861 | (define_expand "cbranch<mode>4" | |
8862 | [(set (pc) | |
8863 | (if_then_else (match_operator 0 "comparison_operator" | |
8864 | [(match_operand:FP 1 "register_operand" "") | |
8865 | (match_operand:FP 2 "general_operand" "")]) | |
8866 | (label_ref (match_operand 3 "" "")) | |
8867 | (pc)))] | |
8868 | "TARGET_HARD_FLOAT" | |
8869 | "s390_emit_jump (operands[3], | |
8870 | s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); | |
8871 | DONE;") | |
8872 | ||
8873 | (define_expand "cbranchcc4" | |
8874 | [(set (pc) | |
de6fba39 | 8875 | (if_then_else (match_operator 0 "s390_comparison" |
f90b7a5a | 8876 | [(match_operand 1 "cc_reg_operand" "") |
de6fba39 | 8877 | (match_operand 2 "const_int_operand" "")]) |
f90b7a5a PB |
8878 | (label_ref (match_operand 3 "" "")) |
8879 | (pc)))] | |
de6fba39 UW |
8880 | "" |
8881 | "") | |
ba956982 | 8882 | |
9db1d521 HP |
8883 | |
8884 | ;; | |
8885 | ;;- Conditional jump instructions. | |
8886 | ;; | |
8887 | ||
6590e19a UW |
8888 | (define_insn "*cjump_64" |
8889 | [(set (pc) | |
8890 | (if_then_else | |
5a3fe9b6 AK |
8891 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
8892 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
8893 | (label_ref (match_operand 0 "" "")) |
8894 | (pc)))] | |
8895 | "TARGET_CPU_ZARCH" | |
9db1d521 | 8896 | { |
13e58269 | 8897 | if (get_attr_length (insn) == 4) |
d40c829f | 8898 | return "j%C1\t%l0"; |
6590e19a | 8899 | else |
d40c829f | 8900 | return "jg%C1\t%l0"; |
6590e19a UW |
8901 | } |
8902 | [(set_attr "op_type" "RI") | |
8903 | (set_attr "type" "branch") | |
8904 | (set (attr "length") | |
8905 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8906 | (const_int 4) (const_int 6)))]) | |
8907 | ||
8908 | (define_insn "*cjump_31" | |
8909 | [(set (pc) | |
8910 | (if_then_else | |
5a3fe9b6 AK |
8911 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) |
8912 | (match_operand 2 "const_int_operand" "")]) | |
6590e19a UW |
8913 | (label_ref (match_operand 0 "" "")) |
8914 | (pc)))] | |
8915 | "!TARGET_CPU_ZARCH" | |
8916 | { | |
8d933e31 AS |
8917 | gcc_assert (get_attr_length (insn) == 4); |
8918 | return "j%C1\t%l0"; | |
10bbf137 | 8919 | } |
9db1d521 | 8920 | [(set_attr "op_type" "RI") |
077dab3b | 8921 | (set_attr "type" "branch") |
13e58269 | 8922 | (set (attr "length") |
d7f99b2c | 8923 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8924 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
8925 | (const_int 4) (const_int 6)) | |
8926 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8927 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 8928 | |
f314b9b1 | 8929 | (define_insn "*cjump_long" |
6590e19a UW |
8930 | [(set (pc) |
8931 | (if_then_else | |
ae156f85 | 8932 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
4fe6dea8 | 8933 | (match_operand 0 "address_operand" "ZQZR") |
6590e19a | 8934 | (pc)))] |
9db1d521 | 8935 | "" |
f314b9b1 UW |
8936 | { |
8937 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 8938 | return "b%C1r\t%0"; |
f314b9b1 | 8939 | else |
d40c829f | 8940 | return "b%C1\t%a0"; |
10bbf137 | 8941 | } |
c7453384 | 8942 | [(set (attr "op_type") |
f314b9b1 UW |
8943 | (if_then_else (match_operand 0 "register_operand" "") |
8944 | (const_string "RR") (const_string "RX"))) | |
6590e19a | 8945 | (set_attr "type" "branch") |
077dab3b | 8946 | (set_attr "atype" "agen")]) |
9db1d521 | 8947 | |
177bc204 RS |
8948 | ;; A conditional return instruction. |
8949 | (define_insn "*c<code>" | |
8950 | [(set (pc) | |
8951 | (if_then_else | |
8952 | (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) | |
8953 | (ANY_RETURN) | |
8954 | (pc)))] | |
8955 | "s390_can_use_<code>_insn ()" | |
8956 | "b%C0r\t%%r14" | |
8957 | [(set_attr "op_type" "RR") | |
8958 | (set_attr "type" "jsr") | |
8959 | (set_attr "atype" "agen")]) | |
9db1d521 HP |
8960 | |
8961 | ;; | |
8962 | ;;- Negated conditional jump instructions. | |
8963 | ;; | |
8964 | ||
6590e19a UW |
8965 | (define_insn "*icjump_64" |
8966 | [(set (pc) | |
8967 | (if_then_else | |
ae156f85 | 8968 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
8969 | (pc) |
8970 | (label_ref (match_operand 0 "" ""))))] | |
8971 | "TARGET_CPU_ZARCH" | |
c7453384 | 8972 | { |
13e58269 | 8973 | if (get_attr_length (insn) == 4) |
d40c829f | 8974 | return "j%D1\t%l0"; |
6590e19a | 8975 | else |
d40c829f | 8976 | return "jg%D1\t%l0"; |
6590e19a UW |
8977 | } |
8978 | [(set_attr "op_type" "RI") | |
8979 | (set_attr "type" "branch") | |
8980 | (set (attr "length") | |
8981 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
8982 | (const_int 4) (const_int 6)))]) | |
8983 | ||
8984 | (define_insn "*icjump_31" | |
8985 | [(set (pc) | |
8986 | (if_then_else | |
ae156f85 | 8987 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a UW |
8988 | (pc) |
8989 | (label_ref (match_operand 0 "" ""))))] | |
8990 | "!TARGET_CPU_ZARCH" | |
8991 | { | |
8d933e31 AS |
8992 | gcc_assert (get_attr_length (insn) == 4); |
8993 | return "j%D1\t%l0"; | |
10bbf137 | 8994 | } |
9db1d521 | 8995 | [(set_attr "op_type" "RI") |
077dab3b | 8996 | (set_attr "type" "branch") |
13e58269 | 8997 | (set (attr "length") |
d7f99b2c | 8998 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
8999 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9000 | (const_int 4) (const_int 6)) | |
9001 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9002 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 9003 | |
f314b9b1 | 9004 | (define_insn "*icjump_long" |
6590e19a UW |
9005 | [(set (pc) |
9006 | (if_then_else | |
ae156f85 | 9007 | (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) |
6590e19a | 9008 | (pc) |
4fe6dea8 | 9009 | (match_operand 0 "address_operand" "ZQZR")))] |
9db1d521 | 9010 | "" |
f314b9b1 UW |
9011 | { |
9012 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9013 | return "b%D1r\t%0"; |
f314b9b1 | 9014 | else |
d40c829f | 9015 | return "b%D1\t%a0"; |
10bbf137 | 9016 | } |
c7453384 | 9017 | [(set (attr "op_type") |
f314b9b1 UW |
9018 | (if_then_else (match_operand 0 "register_operand" "") |
9019 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
9020 | (set_attr "type" "branch") |
9021 | (set_attr "atype" "agen")]) | |
9db1d521 | 9022 | |
4456530d HP |
9023 | ;; |
9024 | ;;- Trap instructions. | |
9025 | ;; | |
9026 | ||
9027 | (define_insn "trap" | |
9028 | [(trap_if (const_int 1) (const_int 0))] | |
9029 | "" | |
d40c829f | 9030 | "j\t.+2" |
6590e19a | 9031 | [(set_attr "op_type" "RI") |
077dab3b | 9032 | (set_attr "type" "branch")]) |
4456530d | 9033 | |
f90b7a5a PB |
9034 | (define_expand "ctrap<mode>4" |
9035 | [(trap_if (match_operator 0 "comparison_operator" | |
9036 | [(match_operand:GPR 1 "register_operand" "") | |
9037 | (match_operand:GPR 2 "general_operand" "")]) | |
9038 | (match_operand 3 "const0_operand" ""))] | |
4456530d | 9039 | "" |
f90b7a5a PB |
9040 | { |
9041 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
9042 | operands[1], operands[2]); | |
9043 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
9044 | DONE; | |
9045 | }) | |
9046 | ||
9047 | (define_expand "ctrap<mode>4" | |
9048 | [(trap_if (match_operator 0 "comparison_operator" | |
9049 | [(match_operand:FP 1 "register_operand" "") | |
9050 | (match_operand:FP 2 "general_operand" "")]) | |
9051 | (match_operand 3 "const0_operand" ""))] | |
9052 | "" | |
9053 | { | |
9054 | rtx cond = s390_emit_compare (GET_CODE (operands[0]), | |
9055 | operands[1], operands[2]); | |
9056 | emit_insn (gen_condtrap (cond, XEXP (cond, 0))); | |
9057 | DONE; | |
9058 | }) | |
4456530d | 9059 | |
f90b7a5a PB |
9060 | (define_insn "condtrap" |
9061 | [(trap_if (match_operator 0 "s390_comparison" | |
9062 | [(match_operand 1 "cc_reg_operand" "c") | |
9063 | (const_int 0)]) | |
4456530d HP |
9064 | (const_int 0))] |
9065 | "" | |
d40c829f | 9066 | "j%C0\t.+2"; |
077dab3b HP |
9067 | [(set_attr "op_type" "RI") |
9068 | (set_attr "type" "branch")]) | |
9db1d521 | 9069 | |
963fc8d0 AK |
9070 | ; crt, cgrt, cit, cgit |
9071 | (define_insn "*cmp_and_trap_signed_int<mode>" | |
9072 | [(trap_if (match_operator 0 "s390_signed_integer_comparison" | |
9073 | [(match_operand:GPR 1 "register_operand" "d,d") | |
9074 | (match_operand:GPR 2 "nonmemory_operand" "d,K")]) | |
9075 | (const_int 0))] | |
9076 | "TARGET_Z10" | |
9077 | "@ | |
9078 | c<g>rt%C0\t%1,%2 | |
9079 | c<g>it%C0\t%1,%h2" | |
9080 | [(set_attr "op_type" "RRF,RIE") | |
9381e3f1 | 9081 | (set_attr "type" "branch") |
729e750f | 9082 | (set_attr "z10prop" "z10_super_c,z10_super")]) |
963fc8d0 | 9083 | |
22ac2c2f | 9084 | ; clrt, clgrt, clfit, clgit, clt, clgt |
963fc8d0 AK |
9085 | (define_insn "*cmp_and_trap_unsigned_int<mode>" |
9086 | [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" | |
3e4be43f UW |
9087 | [(match_operand:GPR 1 "register_operand" "d,d,d") |
9088 | (match_operand:GPR 2 "general_operand" "d,D,T")]) | |
963fc8d0 AK |
9089 | (const_int 0))] |
9090 | "TARGET_Z10" | |
9091 | "@ | |
9092 | cl<g>rt%C0\t%1,%2 | |
22ac2c2f AK |
9093 | cl<gf>it%C0\t%1,%x2 |
9094 | cl<g>t%C0\t%1,%2" | |
9095 | [(set_attr "op_type" "RRF,RIE,RSY") | |
9096 | (set_attr "type" "branch") | |
9097 | (set_attr "z10prop" "z10_super_c,z10_super,*") | |
9098 | (set_attr "cpu_facility" "z10,z10,zEC12")]) | |
9099 | ||
9100 | ; lat, lgat | |
9101 | (define_insn "*load_and_trap<mode>" | |
3e4be43f | 9102 | [(trap_if (eq (match_operand:GPR 0 "memory_operand" "T") |
22ac2c2f AK |
9103 | (const_int 0)) |
9104 | (const_int 0)) | |
9105 | (set (match_operand:GPR 1 "register_operand" "=d") | |
9106 | (match_dup 0))] | |
9107 | "TARGET_ZEC12" | |
9108 | "l<g>at\t%1,%0" | |
9109 | [(set_attr "op_type" "RXY")]) | |
9110 | ||
963fc8d0 | 9111 | |
9db1d521 | 9112 | ;; |
0a3bdf9d | 9113 | ;;- Loop instructions. |
9db1d521 | 9114 | ;; |
0a3bdf9d UW |
9115 | ;; This is all complicated by the fact that since this is a jump insn |
9116 | ;; we must handle our own output reloads. | |
c7453384 | 9117 | |
f1149235 AK |
9118 | ;; branch on index |
9119 | ||
9120 | ; This splitter will be matched by combine and has to add the 2 moves | |
9121 | ; necessary to load the compare and the increment values into a | |
9122 | ; register pair as needed by brxle. | |
9123 | ||
9124 | (define_insn_and_split "*brx_stage1_<GPR:mode>" | |
9125 | [(set (pc) | |
9126 | (if_then_else | |
9127 | (match_operator 6 "s390_brx_operator" | |
9128 | [(plus:GPR (match_operand:GPR 1 "register_operand" "") | |
9129 | (match_operand:GPR 2 "general_operand" "")) | |
9130 | (match_operand:GPR 3 "register_operand" "")]) | |
9131 | (label_ref (match_operand 0 "" "")) | |
9132 | (pc))) | |
9133 | (set (match_operand:GPR 4 "nonimmediate_operand" "") | |
9134 | (plus:GPR (match_dup 1) (match_dup 2))) | |
9135 | (clobber (match_scratch:GPR 5 ""))] | |
9136 | "TARGET_CPU_ZARCH" | |
9137 | "#" | |
9138 | "!reload_completed && !reload_in_progress" | |
9139 | [(set (match_dup 7) (match_dup 2)) ; the increment | |
9140 | (set (match_dup 8) (match_dup 3)) ; the comparison value | |
9141 | (parallel [(set (pc) | |
9142 | (if_then_else | |
9143 | (match_op_dup 6 | |
9144 | [(plus:GPR (match_dup 1) (match_dup 7)) | |
9145 | (match_dup 8)]) | |
9146 | (label_ref (match_dup 0)) | |
9147 | (pc))) | |
9148 | (set (match_dup 4) | |
9149 | (plus:GPR (match_dup 1) (match_dup 7))) | |
9150 | (clobber (match_dup 5)) | |
9151 | (clobber (reg:CC CC_REGNUM))])] | |
9152 | { | |
9153 | rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); | |
9154 | operands[7] = gen_lowpart (<GPR:MODE>mode, | |
9155 | gen_highpart (word_mode, dreg)); | |
9156 | operands[8] = gen_lowpart (<GPR:MODE>mode, | |
9157 | gen_lowpart (word_mode, dreg)); | |
9158 | }) | |
9159 | ||
9160 | ; brxlg, brxhg | |
9161 | ||
9162 | (define_insn_and_split "*brxg_64bit" | |
9163 | [(set (pc) | |
9164 | (if_then_else | |
9165 | (match_operator 5 "s390_brx_operator" | |
9166 | [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") | |
9167 | (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) | |
9168 | (subreg:DI (match_dup 2) 8)]) | |
9169 | (label_ref (match_operand 0 "" "")) | |
9170 | (pc))) | |
9171 | (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") | |
9172 | (plus:DI (match_dup 1) | |
9173 | (subreg:DI (match_dup 2) 0))) | |
9174 | (clobber (match_scratch:DI 4 "=X,&1,&?d")) | |
9175 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9176 | "TARGET_ZARCH" |
f1149235 AK |
9177 | { |
9178 | if (which_alternative != 0) | |
9179 | return "#"; | |
9180 | else if (get_attr_length (insn) == 6) | |
9181 | return "brx%E5g\t%1,%2,%l0"; | |
9182 | else | |
9183 | return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; | |
9184 | } | |
9185 | "&& reload_completed | |
9186 | && (!REG_P (operands[3]) | |
9187 | || !rtx_equal_p (operands[1], operands[3]))" | |
9188 | [(set (match_dup 4) (match_dup 1)) | |
9189 | (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) | |
9190 | (clobber (reg:CC CC_REGNUM))]) | |
9191 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) | |
9192 | (set (match_dup 3) (match_dup 4)) | |
9193 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9194 | (label_ref (match_dup 0)) | |
9195 | (pc)))] | |
9196 | "" | |
9197 | [(set_attr "op_type" "RIE") | |
9198 | (set_attr "type" "branch") | |
9199 | (set (attr "length") | |
9200 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9201 | (const_int 6) (const_int 16)))]) | |
9202 | ||
9203 | ; brxle, brxh | |
9204 | ||
9205 | (define_insn_and_split "*brx_64bit" | |
9206 | [(set (pc) | |
9207 | (if_then_else | |
9208 | (match_operator 5 "s390_brx_operator" | |
9209 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9210 | (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) | |
9211 | (subreg:SI (match_dup 2) 12)]) | |
9212 | (label_ref (match_operand 0 "" "")) | |
9213 | (pc))) | |
9214 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9215 | (plus:SI (match_dup 1) | |
9216 | (subreg:SI (match_dup 2) 4))) | |
9217 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9218 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9219 | "TARGET_ZARCH" |
f1149235 AK |
9220 | { |
9221 | if (which_alternative != 0) | |
9222 | return "#"; | |
9223 | else if (get_attr_length (insn) == 6) | |
9224 | return "brx%C5\t%1,%2,%l0"; | |
9225 | else | |
9226 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9227 | } | |
9228 | "&& reload_completed | |
9229 | && (!REG_P (operands[3]) | |
9230 | || !rtx_equal_p (operands[1], operands[3]))" | |
9231 | [(set (match_dup 4) (match_dup 1)) | |
9232 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9233 | (clobber (reg:CC CC_REGNUM))]) | |
9234 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) | |
9235 | (set (match_dup 3) (match_dup 4)) | |
9236 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9237 | (label_ref (match_dup 0)) | |
9238 | (pc)))] | |
9239 | "" | |
9240 | [(set_attr "op_type" "RSI") | |
9241 | (set_attr "type" "branch") | |
9242 | (set (attr "length") | |
9243 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9244 | (const_int 6) (const_int 14)))]) | |
9245 | ||
9246 | ; brxle, brxh | |
9247 | ||
9248 | (define_insn_and_split "*brx_31bit" | |
9249 | [(set (pc) | |
9250 | (if_then_else | |
9251 | (match_operator 5 "s390_brx_operator" | |
9252 | [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") | |
9253 | (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) | |
9254 | (subreg:SI (match_dup 2) 4)]) | |
9255 | (label_ref (match_operand 0 "" "")) | |
9256 | (pc))) | |
9257 | (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") | |
9258 | (plus:SI (match_dup 1) | |
9259 | (subreg:SI (match_dup 2) 0))) | |
9260 | (clobber (match_scratch:SI 4 "=X,&1,&?d")) | |
9261 | (clobber (reg:CC CC_REGNUM))] | |
9602b6a1 | 9262 | "!TARGET_ZARCH && TARGET_CPU_ZARCH" |
f1149235 AK |
9263 | { |
9264 | if (which_alternative != 0) | |
9265 | return "#"; | |
9266 | else if (get_attr_length (insn) == 6) | |
9267 | return "brx%C5\t%1,%2,%l0"; | |
9268 | else | |
9269 | return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; | |
9270 | } | |
9271 | "&& reload_completed | |
9272 | && (!REG_P (operands[3]) | |
9273 | || !rtx_equal_p (operands[1], operands[3]))" | |
9274 | [(set (match_dup 4) (match_dup 1)) | |
9275 | (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) | |
9276 | (clobber (reg:CC CC_REGNUM))]) | |
9277 | (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) | |
9278 | (set (match_dup 3) (match_dup 4)) | |
9279 | (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) | |
9280 | (label_ref (match_dup 0)) | |
9281 | (pc)))] | |
9282 | "" | |
9283 | [(set_attr "op_type" "RSI") | |
9284 | (set_attr "type" "branch") | |
9285 | (set (attr "length") | |
9286 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9287 | (const_int 6) (const_int 14)))]) | |
9288 | ||
9289 | ||
9290 | ;; branch on count | |
9291 | ||
0a3bdf9d UW |
9292 | (define_expand "doloop_end" |
9293 | [(use (match_operand 0 "" "")) ; loop pseudo | |
1d0216c8 | 9294 | (use (match_operand 1 "" ""))] ; label |
0a3bdf9d | 9295 | "" |
0a3bdf9d | 9296 | { |
6590e19a | 9297 | if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) |
1d0216c8 | 9298 | emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0])); |
6590e19a | 9299 | else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) |
1d0216c8 | 9300 | emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0])); |
9602b6a1 | 9301 | else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) |
1d0216c8 | 9302 | emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0])); |
0a3bdf9d UW |
9303 | else |
9304 | FAIL; | |
9305 | ||
9306 | DONE; | |
10bbf137 | 9307 | }) |
0a3bdf9d | 9308 | |
6590e19a | 9309 | (define_insn_and_split "doloop_si64" |
0a3bdf9d UW |
9310 | [(set (pc) |
9311 | (if_then_else | |
7e665d18 | 9312 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9313 | (const_int 1)) |
9314 | (label_ref (match_operand 0 "" "")) | |
9315 | (pc))) | |
7e665d18 | 9316 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9317 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9318 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9319 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 9320 | "TARGET_CPU_ZARCH" |
0a3bdf9d UW |
9321 | { |
9322 | if (which_alternative != 0) | |
10bbf137 | 9323 | return "#"; |
0a3bdf9d | 9324 | else if (get_attr_length (insn) == 4) |
d40c829f | 9325 | return "brct\t%1,%l0"; |
6590e19a | 9326 | else |
545d16ff | 9327 | return "ahi\t%1,-1\;jgne\t%l0"; |
6590e19a UW |
9328 | } |
9329 | "&& reload_completed | |
9330 | && (! REG_P (operands[2]) | |
9331 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9332 | [(set (match_dup 3) (match_dup 1)) |
9333 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9334 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9335 | (const_int 0))) | |
9336 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9337 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9338 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9339 | (label_ref (match_dup 0)) |
9340 | (pc)))] | |
9341 | "" | |
9342 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9343 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9344 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9345 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9346 | (set_attr "type" "branch") |
9347 | (set (attr "length") | |
9348 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9349 | (const_int 4) (const_int 10)))]) | |
9350 | ||
9351 | (define_insn_and_split "doloop_si31" | |
9352 | [(set (pc) | |
9353 | (if_then_else | |
7e665d18 | 9354 | (ne (match_operand:SI 1 "register_operand" "d,d,d") |
6590e19a UW |
9355 | (const_int 1)) |
9356 | (label_ref (match_operand 0 "" "")) | |
9357 | (pc))) | |
7e665d18 | 9358 | (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") |
6590e19a | 9359 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9360 | (clobber (match_scratch:SI 3 "=X,&1,&?d")) |
ae156f85 | 9361 | (clobber (reg:CC CC_REGNUM))] |
6590e19a UW |
9362 | "!TARGET_CPU_ZARCH" |
9363 | { | |
9364 | if (which_alternative != 0) | |
9365 | return "#"; | |
9366 | else if (get_attr_length (insn) == 4) | |
9367 | return "brct\t%1,%l0"; | |
0a3bdf9d | 9368 | else |
8d933e31 | 9369 | gcc_unreachable (); |
10bbf137 | 9370 | } |
6590e19a UW |
9371 | "&& reload_completed |
9372 | && (! REG_P (operands[2]) | |
9373 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9374 | [(set (match_dup 3) (match_dup 1)) |
9375 | (parallel [(set (reg:CCAN CC_REGNUM) | |
6590e19a UW |
9376 | (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) |
9377 | (const_int 0))) | |
9378 | (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) | |
9379 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9380 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a UW |
9381 | (label_ref (match_dup 0)) |
9382 | (pc)))] | |
9383 | "" | |
0a3bdf9d | 9384 | [(set_attr "op_type" "RI") |
9381e3f1 WG |
9385 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9386 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9387 | (set_attr "z10prop" "z10_super_E1") |
077dab3b | 9388 | (set_attr "type" "branch") |
0a3bdf9d | 9389 | (set (attr "length") |
d7f99b2c | 9390 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
9391 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9392 | (const_int 4) (const_int 6)) | |
9393 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9394 | (const_int 4) (const_int 8))))]) | |
9db1d521 | 9395 | |
0a3bdf9d UW |
9396 | (define_insn "*doloop_si_long" |
9397 | [(set (pc) | |
9398 | (if_then_else | |
7e665d18 | 9399 | (ne (match_operand:SI 1 "register_operand" "d") |
0a3bdf9d | 9400 | (const_int 1)) |
3e4be43f | 9401 | (match_operand 0 "address_operand" "ZR") |
0a3bdf9d | 9402 | (pc))) |
7e665d18 | 9403 | (set (match_operand:SI 2 "register_operand" "=1") |
0a3bdf9d | 9404 | (plus:SI (match_dup 1) (const_int -1))) |
7e665d18 | 9405 | (clobber (match_scratch:SI 3 "=X")) |
ae156f85 | 9406 | (clobber (reg:CC CC_REGNUM))] |
6590e19a | 9407 | "!TARGET_CPU_ZARCH" |
0a3bdf9d UW |
9408 | { |
9409 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
d40c829f | 9410 | return "bctr\t%1,%0"; |
0a3bdf9d | 9411 | else |
d40c829f | 9412 | return "bct\t%1,%a0"; |
10bbf137 | 9413 | } |
c7453384 | 9414 | [(set (attr "op_type") |
0a3bdf9d UW |
9415 | (if_then_else (match_operand 0 "register_operand" "") |
9416 | (const_string "RR") (const_string "RX"))) | |
077dab3b | 9417 | (set_attr "type" "branch") |
729e750f | 9418 | (set_attr "atype" "agen") |
65b1d8ea AK |
9419 | (set_attr "z10prop" "z10_c") |
9420 | (set_attr "z196prop" "z196_cracked")]) | |
0a3bdf9d | 9421 | |
6590e19a | 9422 | (define_insn_and_split "doloop_di" |
0a3bdf9d UW |
9423 | [(set (pc) |
9424 | (if_then_else | |
7e665d18 | 9425 | (ne (match_operand:DI 1 "register_operand" "d,d,d") |
0a3bdf9d UW |
9426 | (const_int 1)) |
9427 | (label_ref (match_operand 0 "" "")) | |
9428 | (pc))) | |
7e665d18 | 9429 | (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") |
0a3bdf9d | 9430 | (plus:DI (match_dup 1) (const_int -1))) |
7e665d18 | 9431 | (clobber (match_scratch:DI 3 "=X,&1,&?d")) |
ae156f85 | 9432 | (clobber (reg:CC CC_REGNUM))] |
9602b6a1 | 9433 | "TARGET_ZARCH" |
0a3bdf9d UW |
9434 | { |
9435 | if (which_alternative != 0) | |
10bbf137 | 9436 | return "#"; |
0a3bdf9d | 9437 | else if (get_attr_length (insn) == 4) |
d40c829f | 9438 | return "brctg\t%1,%l0"; |
0a3bdf9d | 9439 | else |
545d16ff | 9440 | return "aghi\t%1,-1\;jgne\t%l0"; |
10bbf137 | 9441 | } |
6590e19a | 9442 | "&& reload_completed |
0a3bdf9d UW |
9443 | && (! REG_P (operands[2]) |
9444 | || ! rtx_equal_p (operands[1], operands[2]))" | |
7e665d18 AK |
9445 | [(set (match_dup 3) (match_dup 1)) |
9446 | (parallel [(set (reg:CCAN CC_REGNUM) | |
0a3bdf9d UW |
9447 | (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) |
9448 | (const_int 0))) | |
9449 | (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) | |
9450 | (set (match_dup 2) (match_dup 3)) | |
ae156f85 | 9451 | (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) |
6590e19a | 9452 | (label_ref (match_dup 0)) |
0a3bdf9d | 9453 | (pc)))] |
6590e19a UW |
9454 | "" |
9455 | [(set_attr "op_type" "RI") | |
9381e3f1 WG |
9456 | ; Strictly speaking, the z10 properties are valid for brct only, however, it does not |
9457 | ; hurt us in the (rare) case of ahi. | |
729e750f | 9458 | (set_attr "z10prop" "z10_super_E1") |
6590e19a UW |
9459 | (set_attr "type" "branch") |
9460 | (set (attr "length") | |
9461 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9462 | (const_int 4) (const_int 10)))]) | |
9db1d521 HP |
9463 | |
9464 | ;; | |
9465 | ;;- Unconditional jump instructions. | |
9466 | ;; | |
9467 | ||
9468 | ; | |
9469 | ; jump instruction pattern(s). | |
9470 | ; | |
9471 | ||
6590e19a UW |
9472 | (define_expand "jump" |
9473 | [(match_operand 0 "" "")] | |
9db1d521 | 9474 | "" |
6590e19a UW |
9475 | "s390_emit_jump (operands[0], NULL_RTX); DONE;") |
9476 | ||
9477 | (define_insn "*jump64" | |
9478 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
9479 | "TARGET_CPU_ZARCH" | |
9db1d521 | 9480 | { |
13e58269 | 9481 | if (get_attr_length (insn) == 4) |
d40c829f | 9482 | return "j\t%l0"; |
6590e19a | 9483 | else |
d40c829f | 9484 | return "jg\t%l0"; |
6590e19a UW |
9485 | } |
9486 | [(set_attr "op_type" "RI") | |
9487 | (set_attr "type" "branch") | |
9488 | (set (attr "length") | |
9489 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9490 | (const_int 4) (const_int 6)))]) | |
9491 | ||
9492 | (define_insn "*jump31" | |
9493 | [(set (pc) (label_ref (match_operand 0 "" "")))] | |
9494 | "!TARGET_CPU_ZARCH" | |
9495 | { | |
8d933e31 AS |
9496 | gcc_assert (get_attr_length (insn) == 4); |
9497 | return "j\t%l0"; | |
10bbf137 | 9498 | } |
9db1d521 | 9499 | [(set_attr "op_type" "RI") |
077dab3b | 9500 | (set_attr "type" "branch") |
13e58269 | 9501 | (set (attr "length") |
d7f99b2c | 9502 | (if_then_else (not (match_test "flag_pic")) |
6590e19a UW |
9503 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) |
9504 | (const_int 4) (const_int 6)) | |
9505 | (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) | |
9506 | (const_int 4) (const_int 8))))]) | |
9db1d521 HP |
9507 | |
9508 | ; | |
9509 | ; indirect-jump instruction pattern(s). | |
9510 | ; | |
9511 | ||
2841f550 AK |
9512 | (define_expand "indirect_jump" |
9513 | [(set (pc) (match_operand 0 "nonimmediate_operand" ""))] | |
9db1d521 | 9514 | "" |
f314b9b1 | 9515 | { |
2841f550 AK |
9516 | if (address_operand (operands[0], GET_MODE (operands[0]))) |
9517 | ; | |
9518 | else if (TARGET_ARCH12 | |
9519 | && GET_MODE (operands[0]) == Pmode | |
9520 | && memory_operand (operands[0], Pmode)) | |
9521 | ; | |
f314b9b1 | 9522 | else |
2841f550 AK |
9523 | operands[0] = force_reg (Pmode, operands[0]); |
9524 | }) | |
9525 | ||
9526 | (define_insn "*indirect_jump" | |
9527 | [(set (pc) | |
9528 | (match_operand 0 "address_operand" "a,ZR"))] | |
9529 | "" | |
9530 | "@ | |
9531 | br\t%0 | |
9532 | b\t%a0" | |
9533 | [(set_attr "op_type" "RR,RX") | |
9534 | (set_attr "type" "branch") | |
9535 | (set_attr "atype" "agen") | |
9536 | (set_attr "cpu_facility" "*")]) | |
9537 | ||
9538 | ; FIXME: LRA does not appear to be able to deal with MEMs being | |
9539 | ; checked against address constraints like ZR above. So make this a | |
9540 | ; separate pattern for now. | |
9541 | (define_insn "*indirect2_jump" | |
9542 | [(set (pc) | |
9543 | (match_operand 0 "nonimmediate_operand" "a,T"))] | |
9544 | "" | |
9545 | "@ | |
9546 | br\t%0 | |
9547 | bi\t%0" | |
9548 | [(set_attr "op_type" "RR,RXY") | |
9549 | (set_attr "type" "branch") | |
9550 | (set_attr "atype" "agen") | |
9551 | (set_attr "cpu_facility" "*,arch12")]) | |
9db1d521 HP |
9552 | |
9553 | ; | |
f314b9b1 | 9554 | ; casesi instruction pattern(s). |
9db1d521 HP |
9555 | ; |
9556 | ||
f314b9b1 | 9557 | (define_insn "casesi_jump" |
3e4be43f | 9558 | [(set (pc) (match_operand 0 "address_operand" "ZR")) |
f314b9b1 | 9559 | (use (label_ref (match_operand 1 "" "")))] |
9db1d521 | 9560 | "" |
9db1d521 | 9561 | { |
f314b9b1 | 9562 | if (get_attr_op_type (insn) == OP_TYPE_RR) |
d40c829f | 9563 | return "br\t%0"; |
f314b9b1 | 9564 | else |
d40c829f | 9565 | return "b\t%a0"; |
10bbf137 | 9566 | } |
c7453384 | 9567 | [(set (attr "op_type") |
f314b9b1 UW |
9568 | (if_then_else (match_operand 0 "register_operand" "") |
9569 | (const_string "RR") (const_string "RX"))) | |
077dab3b HP |
9570 | (set_attr "type" "branch") |
9571 | (set_attr "atype" "agen")]) | |
9db1d521 | 9572 | |
f314b9b1 UW |
9573 | (define_expand "casesi" |
9574 | [(match_operand:SI 0 "general_operand" "") | |
9575 | (match_operand:SI 1 "general_operand" "") | |
9576 | (match_operand:SI 2 "general_operand" "") | |
9577 | (label_ref (match_operand 3 "" "")) | |
9578 | (label_ref (match_operand 4 "" ""))] | |
9db1d521 | 9579 | "" |
f314b9b1 UW |
9580 | { |
9581 | rtx index = gen_reg_rtx (SImode); | |
9582 | rtx base = gen_reg_rtx (Pmode); | |
9583 | rtx target = gen_reg_rtx (Pmode); | |
9584 | ||
9585 | emit_move_insn (index, operands[0]); | |
9586 | emit_insn (gen_subsi3 (index, index, operands[1])); | |
9587 | emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, | |
e790b36a | 9588 | operands[4]); |
f314b9b1 UW |
9589 | |
9590 | if (Pmode != SImode) | |
9591 | index = convert_to_mode (Pmode, index, 1); | |
9592 | if (GET_CODE (index) != REG) | |
9593 | index = copy_to_mode_reg (Pmode, index); | |
9594 | ||
9595 | if (TARGET_64BIT) | |
9596 | emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); | |
9597 | else | |
a556fd39 | 9598 | emit_insn (gen_ashlsi3 (index, index, const2_rtx)); |
9db1d521 | 9599 | |
f314b9b1 UW |
9600 | emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); |
9601 | ||
542a8afa | 9602 | index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); |
f314b9b1 UW |
9603 | emit_move_insn (target, index); |
9604 | ||
9605 | if (flag_pic) | |
9606 | target = gen_rtx_PLUS (Pmode, base, target); | |
9607 | emit_jump_insn (gen_casesi_jump (target, operands[3])); | |
9608 | ||
9609 | DONE; | |
10bbf137 | 9610 | }) |
9db1d521 HP |
9611 | |
9612 | ||
9613 | ;; | |
9614 | ;;- Jump to subroutine. | |
9615 | ;; | |
9616 | ;; | |
9617 | ||
9618 | ; | |
9619 | ; untyped call instruction pattern(s). | |
9620 | ; | |
9621 | ||
9622 | ;; Call subroutine returning any type. | |
9623 | (define_expand "untyped_call" | |
9624 | [(parallel [(call (match_operand 0 "" "") | |
9625 | (const_int 0)) | |
9626 | (match_operand 1 "" "") | |
9627 | (match_operand 2 "" "")])] | |
9628 | "" | |
9db1d521 HP |
9629 | { |
9630 | int i; | |
9631 | ||
9632 | emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); | |
9633 | ||
9634 | for (i = 0; i < XVECLEN (operands[2], 0); i++) | |
9635 | { | |
9636 | rtx set = XVECEXP (operands[2], 0, i); | |
9637 | emit_move_insn (SET_DEST (set), SET_SRC (set)); | |
9638 | } | |
9639 | ||
9640 | /* The optimizer does not know that the call sets the function value | |
9641 | registers we stored in the result block. We avoid problems by | |
9642 | claiming that all hard registers are used and clobbered at this | |
9643 | point. */ | |
9644 | emit_insn (gen_blockage ()); | |
9645 | ||
9646 | DONE; | |
10bbf137 | 9647 | }) |
9db1d521 HP |
9648 | |
9649 | ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and | |
9650 | ;; all of memory. This blocks insns from being moved across this point. | |
9651 | ||
9652 | (define_insn "blockage" | |
10bbf137 | 9653 | [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] |
9db1d521 | 9654 | "" |
4023fb28 | 9655 | "" |
d5869ca0 UW |
9656 | [(set_attr "type" "none") |
9657 | (set_attr "length" "0")]) | |
4023fb28 | 9658 | |
9db1d521 | 9659 | ; |
ed9676cf | 9660 | ; sibcall patterns |
9db1d521 HP |
9661 | ; |
9662 | ||
ed9676cf | 9663 | (define_expand "sibcall" |
44b8152b | 9664 | [(call (match_operand 0 "" "") |
ed9676cf | 9665 | (match_operand 1 "" ""))] |
9db1d521 | 9666 | "" |
9db1d521 | 9667 | { |
ed9676cf AK |
9668 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); |
9669 | DONE; | |
9670 | }) | |
9db1d521 | 9671 | |
ed9676cf | 9672 | (define_insn "*sibcall_br" |
ae156f85 | 9673 | [(call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9674 | (match_operand 0 "const_int_operand" "n"))] |
2f7e5a0d | 9675 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
9676 | && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" |
9677 | "br\t%%r1" | |
9678 | [(set_attr "op_type" "RR") | |
9679 | (set_attr "type" "branch") | |
9680 | (set_attr "atype" "agen")]) | |
9db1d521 | 9681 | |
ed9676cf AK |
9682 | (define_insn "*sibcall_brc" |
9683 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9684 | (match_operand 1 "const_int_operand" "n"))] | |
9685 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9686 | "j\t%0" | |
9687 | [(set_attr "op_type" "RI") | |
9688 | (set_attr "type" "branch")]) | |
9db1d521 | 9689 | |
ed9676cf AK |
9690 | (define_insn "*sibcall_brcl" |
9691 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9692 | (match_operand 1 "const_int_operand" "n"))] | |
9693 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
9694 | "jg\t%0" | |
9695 | [(set_attr "op_type" "RIL") | |
9696 | (set_attr "type" "branch")]) | |
44b8152b | 9697 | |
ed9676cf AK |
9698 | ; |
9699 | ; sibcall_value patterns | |
9700 | ; | |
9e8327e3 | 9701 | |
ed9676cf AK |
9702 | (define_expand "sibcall_value" |
9703 | [(set (match_operand 0 "" "") | |
9704 | (call (match_operand 1 "" "") | |
9705 | (match_operand 2 "" "")))] | |
9706 | "" | |
9707 | { | |
9708 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); | |
44b8152b | 9709 | DONE; |
10bbf137 | 9710 | }) |
9db1d521 | 9711 | |
ed9676cf AK |
9712 | (define_insn "*sibcall_value_br" |
9713 | [(set (match_operand 0 "" "") | |
ae156f85 | 9714 | (call (mem:QI (reg SIBCALL_REGNUM)) |
ed9676cf | 9715 | (match_operand 1 "const_int_operand" "n")))] |
2f7e5a0d | 9716 | "SIBLING_CALL_P (insn) |
ed9676cf AK |
9717 | && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" |
9718 | "br\t%%r1" | |
9719 | [(set_attr "op_type" "RR") | |
9720 | (set_attr "type" "branch") | |
9721 | (set_attr "atype" "agen")]) | |
9722 | ||
9723 | (define_insn "*sibcall_value_brc" | |
9724 | [(set (match_operand 0 "" "") | |
9725 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9726 | (match_operand 2 "const_int_operand" "n")))] | |
9727 | "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" | |
9728 | "j\t%1" | |
9729 | [(set_attr "op_type" "RI") | |
9730 | (set_attr "type" "branch")]) | |
9731 | ||
9732 | (define_insn "*sibcall_value_brcl" | |
9733 | [(set (match_operand 0 "" "") | |
9734 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) | |
9735 | (match_operand 2 "const_int_operand" "n")))] | |
9736 | "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" | |
9737 | "jg\t%1" | |
9738 | [(set_attr "op_type" "RIL") | |
9739 | (set_attr "type" "branch")]) | |
9740 | ||
9741 | ||
9742 | ; | |
9743 | ; call instruction pattern(s). | |
9744 | ; | |
9745 | ||
9746 | (define_expand "call" | |
9747 | [(call (match_operand 0 "" "") | |
9748 | (match_operand 1 "" "")) | |
9749 | (use (match_operand 2 "" ""))] | |
44b8152b | 9750 | "" |
ed9676cf | 9751 | { |
2f7e5a0d | 9752 | s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, |
ed9676cf AK |
9753 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
9754 | DONE; | |
9755 | }) | |
44b8152b | 9756 | |
9e8327e3 UW |
9757 | (define_insn "*bras" |
9758 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9759 | (match_operand 1 "const_int_operand" "n")) | |
9760 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
9761 | "!SIBLING_CALL_P (insn) |
9762 | && TARGET_SMALL_EXEC | |
ed9676cf | 9763 | && GET_MODE (operands[2]) == Pmode" |
d40c829f | 9764 | "bras\t%2,%0" |
9db1d521 | 9765 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9766 | (set_attr "type" "jsr") |
9767 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9768 | |
9e8327e3 UW |
9769 | (define_insn "*brasl" |
9770 | [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) | |
9771 | (match_operand 1 "const_int_operand" "n")) | |
9772 | (clobber (match_operand 2 "register_operand" "=r"))] | |
2f7e5a0d EC |
9773 | "!SIBLING_CALL_P (insn) |
9774 | && TARGET_CPU_ZARCH | |
ed9676cf | 9775 | && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
9776 | "brasl\t%2,%0" |
9777 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9778 | (set_attr "type" "jsr") |
9779 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9780 | |
9e8327e3 | 9781 | (define_insn "*basr" |
3e4be43f | 9782 | [(call (mem:QI (match_operand 0 "address_operand" "ZR")) |
9e8327e3 UW |
9783 | (match_operand 1 "const_int_operand" "n")) |
9784 | (clobber (match_operand 2 "register_operand" "=r"))] | |
ed9676cf | 9785 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" |
9e8327e3 UW |
9786 | { |
9787 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9788 | return "basr\t%2,%0"; | |
9789 | else | |
9790 | return "bas\t%2,%a0"; | |
9791 | } | |
9792 | [(set (attr "op_type") | |
9793 | (if_then_else (match_operand 0 "register_operand" "") | |
9794 | (const_string "RR") (const_string "RX"))) | |
9795 | (set_attr "type" "jsr") | |
65b1d8ea AK |
9796 | (set_attr "atype" "agen") |
9797 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 HP |
9798 | |
9799 | ; | |
9800 | ; call_value instruction pattern(s). | |
9801 | ; | |
9802 | ||
9803 | (define_expand "call_value" | |
44b8152b UW |
9804 | [(set (match_operand 0 "" "") |
9805 | (call (match_operand 1 "" "") | |
9806 | (match_operand 2 "" ""))) | |
9807 | (use (match_operand 3 "" ""))] | |
9db1d521 | 9808 | "" |
9db1d521 | 9809 | { |
2f7e5a0d | 9810 | s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], |
ed9676cf | 9811 | gen_rtx_REG (Pmode, RETURN_REGNUM)); |
44b8152b | 9812 | DONE; |
10bbf137 | 9813 | }) |
9db1d521 | 9814 | |
9e8327e3 | 9815 | (define_insn "*bras_r" |
c19ec8f9 | 9816 | [(set (match_operand 0 "" "") |
9e8327e3 | 9817 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9db1d521 | 9818 | (match_operand:SI 2 "const_int_operand" "n"))) |
9e8327e3 | 9819 | (clobber (match_operand 3 "register_operand" "=r"))] |
2f7e5a0d EC |
9820 | "!SIBLING_CALL_P (insn) |
9821 | && TARGET_SMALL_EXEC | |
ed9676cf | 9822 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 9823 | "bras\t%3,%1" |
9db1d521 | 9824 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9825 | (set_attr "type" "jsr") |
9826 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9827 | |
9e8327e3 | 9828 | (define_insn "*brasl_r" |
c19ec8f9 | 9829 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9830 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9831 | (match_operand 2 "const_int_operand" "n"))) | |
9832 | (clobber (match_operand 3 "register_operand" "=r"))] | |
2f7e5a0d EC |
9833 | "!SIBLING_CALL_P (insn) |
9834 | && TARGET_CPU_ZARCH | |
ed9676cf | 9835 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9836 | "brasl\t%3,%1" |
9837 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9838 | (set_attr "type" "jsr") |
9839 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9840 | |
9e8327e3 | 9841 | (define_insn "*basr_r" |
c19ec8f9 | 9842 | [(set (match_operand 0 "" "") |
3e4be43f | 9843 | (call (mem:QI (match_operand 1 "address_operand" "ZR")) |
9e8327e3 UW |
9844 | (match_operand 2 "const_int_operand" "n"))) |
9845 | (clobber (match_operand 3 "register_operand" "=r"))] | |
ed9676cf | 9846 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9847 | { |
9848 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9849 | return "basr\t%3,%1"; | |
9850 | else | |
9851 | return "bas\t%3,%a1"; | |
9852 | } | |
9853 | [(set (attr "op_type") | |
9854 | (if_then_else (match_operand 1 "register_operand" "") | |
9855 | (const_string "RR") (const_string "RX"))) | |
9856 | (set_attr "type" "jsr") | |
65b1d8ea AK |
9857 | (set_attr "atype" "agen") |
9858 | (set_attr "z196prop" "z196_cracked")]) | |
9db1d521 | 9859 | |
fd3cd001 UW |
9860 | ;; |
9861 | ;;- Thread-local storage support. | |
9862 | ;; | |
9863 | ||
f959607b CLT |
9864 | (define_expand "get_thread_pointer<mode>" |
9865 | [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))] | |
9866 | "" | |
c5aa1d12 | 9867 | "") |
fd3cd001 | 9868 | |
f959607b CLT |
9869 | (define_expand "set_thread_pointer<mode>" |
9870 | [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) | |
9871 | (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] | |
9872 | "" | |
c5aa1d12 UW |
9873 | "") |
9874 | ||
9875 | (define_insn "*set_tp" | |
ae156f85 | 9876 | [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] |
c5aa1d12 UW |
9877 | "" |
9878 | "" | |
9879 | [(set_attr "type" "none") | |
9880 | (set_attr "length" "0")]) | |
c7453384 | 9881 | |
fd3cd001 UW |
9882 | (define_insn "*tls_load_64" |
9883 | [(set (match_operand:DI 0 "register_operand" "=d") | |
3e4be43f | 9884 | (unspec:DI [(match_operand:DI 1 "memory_operand" "T") |
fd3cd001 UW |
9885 | (match_operand:DI 2 "" "")] |
9886 | UNSPEC_TLS_LOAD))] | |
9887 | "TARGET_64BIT" | |
d40c829f | 9888 | "lg\t%0,%1%J2" |
9381e3f1 WG |
9889 | [(set_attr "op_type" "RXE") |
9890 | (set_attr "z10prop" "z10_fwd_A3")]) | |
fd3cd001 UW |
9891 | |
9892 | (define_insn "*tls_load_31" | |
d3632d41 UW |
9893 | [(set (match_operand:SI 0 "register_operand" "=d,d") |
9894 | (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") | |
fd3cd001 UW |
9895 | (match_operand:SI 2 "" "")] |
9896 | UNSPEC_TLS_LOAD))] | |
9897 | "!TARGET_64BIT" | |
d3632d41 | 9898 | "@ |
d40c829f UW |
9899 | l\t%0,%1%J2 |
9900 | ly\t%0,%1%J2" | |
9381e3f1 | 9901 | [(set_attr "op_type" "RX,RXY") |
cdc15d23 | 9902 | (set_attr "type" "load") |
3e4be43f | 9903 | (set_attr "cpu_facility" "*,longdisp") |
9381e3f1 | 9904 | (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) |
fd3cd001 | 9905 | |
9e8327e3 | 9906 | (define_insn "*bras_tls" |
c19ec8f9 | 9907 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9908 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9909 | (match_operand 2 "const_int_operand" "n"))) | |
9910 | (clobber (match_operand 3 "register_operand" "=r")) | |
9911 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
9912 | "!SIBLING_CALL_P (insn) |
9913 | && TARGET_SMALL_EXEC | |
ed9676cf | 9914 | && GET_MODE (operands[3]) == Pmode" |
d40c829f | 9915 | "bras\t%3,%1%J4" |
fd3cd001 | 9916 | [(set_attr "op_type" "RI") |
65b1d8ea AK |
9917 | (set_attr "type" "jsr") |
9918 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9919 | |
9e8327e3 | 9920 | (define_insn "*brasl_tls" |
c19ec8f9 | 9921 | [(set (match_operand 0 "" "") |
9e8327e3 UW |
9922 | (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) |
9923 | (match_operand 2 "const_int_operand" "n"))) | |
9924 | (clobber (match_operand 3 "register_operand" "=r")) | |
9925 | (use (match_operand 4 "" ""))] | |
2f7e5a0d EC |
9926 | "!SIBLING_CALL_P (insn) |
9927 | && TARGET_CPU_ZARCH | |
ed9676cf | 9928 | && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9929 | "brasl\t%3,%1%J4" |
9930 | [(set_attr "op_type" "RIL") | |
65b1d8ea AK |
9931 | (set_attr "type" "jsr") |
9932 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9933 | |
9e8327e3 | 9934 | (define_insn "*basr_tls" |
c19ec8f9 | 9935 | [(set (match_operand 0 "" "") |
3e4be43f | 9936 | (call (mem:QI (match_operand 1 "address_operand" "ZR")) |
9e8327e3 UW |
9937 | (match_operand 2 "const_int_operand" "n"))) |
9938 | (clobber (match_operand 3 "register_operand" "=r")) | |
9939 | (use (match_operand 4 "" ""))] | |
ed9676cf | 9940 | "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" |
9e8327e3 UW |
9941 | { |
9942 | if (get_attr_op_type (insn) == OP_TYPE_RR) | |
9943 | return "basr\t%3,%1%J4"; | |
9944 | else | |
9945 | return "bas\t%3,%a1%J4"; | |
9946 | } | |
9947 | [(set (attr "op_type") | |
9948 | (if_then_else (match_operand 1 "register_operand" "") | |
9949 | (const_string "RR") (const_string "RX"))) | |
9950 | (set_attr "type" "jsr") | |
65b1d8ea AK |
9951 | (set_attr "atype" "agen") |
9952 | (set_attr "z196prop" "z196_cracked")]) | |
fd3cd001 | 9953 | |
e0374221 AS |
9954 | ;; |
9955 | ;;- Atomic operations | |
9956 | ;; | |
9957 | ||
9958 | ; | |
78ce265b | 9959 | ; memory barrier patterns. |
e0374221 AS |
9960 | ; |
9961 | ||
78ce265b RH |
9962 | (define_expand "mem_signal_fence" |
9963 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
e0374221 AS |
9964 | "" |
9965 | { | |
78ce265b RH |
9966 | /* The s390 memory model is strong enough not to require any |
9967 | barrier in order to synchronize a thread with itself. */ | |
9968 | DONE; | |
9969 | }) | |
9970 | ||
9971 | (define_expand "mem_thread_fence" | |
9972 | [(match_operand:SI 0 "const_int_operand")] ;; model | |
9973 | "" | |
9974 | { | |
9975 | /* Unless this is a SEQ_CST fence, the s390 memory model is strong | |
9976 | enough not to require barriers of any kind. */ | |
46b35980 | 9977 | if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0])))) |
78ce265b RH |
9978 | { |
9979 | rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); | |
9980 | MEM_VOLATILE_P (mem) = 1; | |
9981 | emit_insn (gen_mem_thread_fence_1 (mem)); | |
9982 | } | |
9983 | DONE; | |
e0374221 AS |
9984 | }) |
9985 | ||
78ce265b RH |
9986 | ; Although bcr is superscalar on Z10, this variant will never |
9987 | ; become part of an execution group. | |
a9cc3f58 AK |
9988 | ; With z196 we can make use of the fast-BCR-serialization facility. |
9989 | ; This allows for a slightly faster sync which is sufficient for our | |
9990 | ; purposes. | |
78ce265b | 9991 | (define_insn "mem_thread_fence_1" |
e0374221 | 9992 | [(set (match_operand:BLK 0 "" "") |
1a8c13b3 | 9993 | (unspec:BLK [(match_dup 0)] UNSPEC_MB))] |
e0374221 | 9994 | "" |
a9cc3f58 AK |
9995 | { |
9996 | if (TARGET_Z196) | |
9997 | return "bcr\t14,0"; | |
9998 | else | |
9999 | return "bcr\t15,0"; | |
10000 | } | |
10001 | [(set_attr "op_type" "RR") | |
10002 | (set_attr "mnemonic" "bcr_flush") | |
10003 | (set_attr "z196prop" "z196_alone")]) | |
1a8c13b3 | 10004 | |
78ce265b RH |
10005 | ; |
10006 | ; atomic load/store operations | |
10007 | ; | |
10008 | ||
10009 | ; Atomic loads need not examine the memory model at all. | |
10010 | (define_expand "atomic_load<mode>" | |
10011 | [(match_operand:DINT 0 "register_operand") ;; output | |
10012 | (match_operand:DINT 1 "memory_operand") ;; memory | |
10013 | (match_operand:SI 2 "const_int_operand")] ;; model | |
10014 | "" | |
10015 | { | |
75cc21e2 AK |
10016 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
10017 | FAIL; | |
10018 | ||
78ce265b RH |
10019 | if (<MODE>mode == TImode) |
10020 | emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); | |
10021 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
10022 | emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); | |
10023 | else | |
10024 | emit_move_insn (operands[0], operands[1]); | |
10025 | DONE; | |
10026 | }) | |
10027 | ||
10028 | ; Different from movdi_31 in that we want no splitters. | |
10029 | (define_insn "atomic_loaddi_1" | |
10030 | [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") | |
10031 | (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] | |
10032 | UNSPEC_MOVA))] | |
10033 | "!TARGET_ZARCH" | |
10034 | "@ | |
10035 | lm\t%0,%M0,%S1 | |
10036 | lmy\t%0,%M0,%S1 | |
10037 | ld\t%0,%1 | |
10038 | ldy\t%0,%1" | |
10039 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
3e4be43f | 10040 | (set_attr "cpu_facility" "*,longdisp,*,longdisp") |
78ce265b RH |
10041 | (set_attr "type" "lm,lm,floaddf,floaddf")]) |
10042 | ||
10043 | (define_insn "atomic_loadti_1" | |
10044 | [(set (match_operand:TI 0 "register_operand" "=r") | |
3e4be43f | 10045 | (unspec:TI [(match_operand:TI 1 "memory_operand" "T")] |
78ce265b RH |
10046 | UNSPEC_MOVA))] |
10047 | "TARGET_ZARCH" | |
10048 | "lpq\t%0,%1" | |
10049 | [(set_attr "op_type" "RXY") | |
10050 | (set_attr "type" "other")]) | |
10051 | ||
10052 | ; Atomic stores must(?) enforce sequential consistency. | |
10053 | (define_expand "atomic_store<mode>" | |
10054 | [(match_operand:DINT 0 "memory_operand") ;; memory | |
10055 | (match_operand:DINT 1 "register_operand") ;; input | |
10056 | (match_operand:SI 2 "const_int_operand")] ;; model | |
10057 | "" | |
10058 | { | |
46b35980 | 10059 | enum memmodel model = memmodel_from_int (INTVAL (operands[2])); |
78ce265b | 10060 | |
75cc21e2 AK |
10061 | if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0]))) |
10062 | FAIL; | |
10063 | ||
78ce265b RH |
10064 | if (<MODE>mode == TImode) |
10065 | emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); | |
10066 | else if (<MODE>mode == DImode && !TARGET_ZARCH) | |
10067 | emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); | |
10068 | else | |
10069 | emit_move_insn (operands[0], operands[1]); | |
46b35980 | 10070 | if (is_mm_seq_cst (model)) |
78ce265b RH |
10071 | emit_insn (gen_mem_thread_fence (operands[2])); |
10072 | DONE; | |
10073 | }) | |
10074 | ||
10075 | ; Different from movdi_31 in that we want no splitters. | |
10076 | (define_insn "atomic_storedi_1" | |
10077 | [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") | |
10078 | (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] | |
10079 | UNSPEC_MOVA))] | |
10080 | "!TARGET_ZARCH" | |
10081 | "@ | |
10082 | stm\t%1,%N1,%S0 | |
10083 | stmy\t%1,%N1,%S0 | |
10084 | std %1,%0 | |
10085 | stdy %1,%0" | |
10086 | [(set_attr "op_type" "RS,RSY,RS,RSY") | |
3e4be43f | 10087 | (set_attr "cpu_facility" "*,longdisp,*,longdisp") |
78ce265b RH |
10088 | (set_attr "type" "stm,stm,fstoredf,fstoredf")]) |
10089 | ||
10090 | (define_insn "atomic_storeti_1" | |
3e4be43f | 10091 | [(set (match_operand:TI 0 "memory_operand" "=T") |
78ce265b RH |
10092 | (unspec:TI [(match_operand:TI 1 "register_operand" "r")] |
10093 | UNSPEC_MOVA))] | |
10094 | "TARGET_ZARCH" | |
10095 | "stpq\t%1,%0" | |
10096 | [(set_attr "op_type" "RXY") | |
10097 | (set_attr "type" "other")]) | |
e0374221 AS |
10098 | |
10099 | ; | |
10100 | ; compare and swap patterns. | |
10101 | ; | |
10102 | ||
78ce265b RH |
10103 | (define_expand "atomic_compare_and_swap<mode>" |
10104 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
215770ad | 10105 | (match_operand:DGPR 1 "nonimmediate_operand");; oldval output |
78ce265b RH |
10106 | (match_operand:DGPR 2 "memory_operand") ;; memory |
10107 | (match_operand:DGPR 3 "register_operand") ;; expected intput | |
10108 | (match_operand:DGPR 4 "register_operand") ;; newval intput | |
10109 | (match_operand:SI 5 "const_int_operand") ;; is_weak | |
10110 | (match_operand:SI 6 "const_int_operand") ;; success model | |
10111 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
10112 | "" | |
10113 | { | |
215770ad UW |
10114 | rtx cc, cmp, output = operands[1]; |
10115 | ||
10116 | if (!register_operand (output, <MODE>mode)) | |
10117 | output = gen_reg_rtx (<MODE>mode); | |
10118 | ||
75cc21e2 AK |
10119 | if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2]))) |
10120 | FAIL; | |
10121 | ||
78ce265b | 10122 | emit_insn (gen_atomic_compare_and_swap<mode>_internal |
215770ad UW |
10123 | (output, operands[2], operands[3], operands[4])); |
10124 | ||
10125 | /* We deliberately accept non-register operands in the predicate | |
10126 | to ensure the write back to the output operand happens *before* | |
10127 | the store-flags code below. This makes it easier for combine | |
10128 | to merge the store-flags code with a potential test-and-branch | |
10129 | pattern following (immediately!) afterwards. */ | |
10130 | if (output != operands[1]) | |
10131 | emit_move_insn (operands[1], output); | |
10132 | ||
78ce265b RH |
10133 | cc = gen_rtx_REG (CCZ1mode, CC_REGNUM); |
10134 | cmp = gen_rtx_EQ (SImode, cc, const0_rtx); | |
10135 | emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx)); | |
10136 | DONE; | |
10137 | }) | |
e0374221 | 10138 | |
78ce265b RH |
10139 | (define_expand "atomic_compare_and_swap<mode>" |
10140 | [(match_operand:SI 0 "register_operand") ;; bool success output | |
215770ad | 10141 | (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output |
78ce265b RH |
10142 | (match_operand:HQI 2 "memory_operand") ;; memory |
10143 | (match_operand:HQI 3 "general_operand") ;; expected intput | |
10144 | (match_operand:HQI 4 "general_operand") ;; newval intput | |
10145 | (match_operand:SI 5 "const_int_operand") ;; is_weak | |
10146 | (match_operand:SI 6 "const_int_operand") ;; success model | |
10147 | (match_operand:SI 7 "const_int_operand")] ;; failure model | |
3093f076 | 10148 | "" |
78ce265b RH |
10149 | { |
10150 | s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2], | |
10151 | operands[3], operands[4], INTVAL (operands[5])); | |
10152 | DONE; | |
10153 | }) | |
3093f076 | 10154 | |
78ce265b RH |
10155 | (define_expand "atomic_compare_and_swap<mode>_internal" |
10156 | [(parallel | |
10157 | [(set (match_operand:DGPR 0 "register_operand") | |
10158 | (match_operand:DGPR 1 "memory_operand")) | |
10159 | (set (match_dup 1) | |
10160 | (unspec_volatile:DGPR | |
10161 | [(match_dup 1) | |
10162 | (match_operand:DGPR 2 "register_operand") | |
10163 | (match_operand:DGPR 3 "register_operand")] | |
10164 | UNSPECV_CAS)) | |
10165 | (set (reg:CCZ1 CC_REGNUM) | |
10166 | (compare:CCZ1 (match_dup 1) (match_dup 2)))])] | |
10167 | "") | |
10168 | ||
10169 | ; cdsg, csg | |
10170 | (define_insn "*atomic_compare_and_swap<mode>_1" | |
10171 | [(set (match_operand:TDI 0 "register_operand" "=r") | |
3e4be43f | 10172 | (match_operand:TDI 1 "memory_operand" "+S")) |
8006eaa6 | 10173 | (set (match_dup 1) |
78ce265b | 10174 | (unspec_volatile:TDI |
8006eaa6 | 10175 | [(match_dup 1) |
78ce265b RH |
10176 | (match_operand:TDI 2 "register_operand" "0") |
10177 | (match_operand:TDI 3 "register_operand" "r")] | |
8006eaa6 AS |
10178 | UNSPECV_CAS)) |
10179 | (set (reg:CCZ1 CC_REGNUM) | |
10180 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
78ce265b RH |
10181 | "TARGET_ZARCH" |
10182 | "c<td>sg\t%0,%3,%S1" | |
10183 | [(set_attr "op_type" "RSY") | |
8006eaa6 AS |
10184 | (set_attr "type" "sem")]) |
10185 | ||
78ce265b RH |
10186 | ; cds, cdsy |
10187 | (define_insn "*atomic_compare_and_swapdi_2" | |
10188 | [(set (match_operand:DI 0 "register_operand" "=r,r") | |
10189 | (match_operand:DI 1 "memory_operand" "+Q,S")) | |
e0374221 | 10190 | (set (match_dup 1) |
78ce265b RH |
10191 | (unspec_volatile:DI |
10192 | [(match_dup 1) | |
10193 | (match_operand:DI 2 "register_operand" "0,0") | |
10194 | (match_operand:DI 3 "register_operand" "r,r")] | |
10195 | UNSPECV_CAS)) | |
10196 | (set (reg:CCZ1 CC_REGNUM) | |
10197 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
10198 | "!TARGET_ZARCH" | |
10199 | "@ | |
10200 | cds\t%0,%3,%S1 | |
10201 | cdsy\t%0,%3,%S1" | |
10202 | [(set_attr "op_type" "RS,RSY") | |
3e4be43f | 10203 | (set_attr "cpu_facility" "*,longdisp") |
78ce265b RH |
10204 | (set_attr "type" "sem")]) |
10205 | ||
10206 | ; cs, csy | |
10207 | (define_insn "*atomic_compare_and_swapsi_3" | |
10208 | [(set (match_operand:SI 0 "register_operand" "=r,r") | |
10209 | (match_operand:SI 1 "memory_operand" "+Q,S")) | |
10210 | (set (match_dup 1) | |
10211 | (unspec_volatile:SI | |
e0374221 | 10212 | [(match_dup 1) |
78ce265b RH |
10213 | (match_operand:SI 2 "register_operand" "0,0") |
10214 | (match_operand:SI 3 "register_operand" "r,r")] | |
e0374221 | 10215 | UNSPECV_CAS)) |
69950452 AS |
10216 | (set (reg:CCZ1 CC_REGNUM) |
10217 | (compare:CCZ1 (match_dup 1) (match_dup 2)))] | |
9381e3f1 | 10218 | "" |
78ce265b RH |
10219 | "@ |
10220 | cs\t%0,%3,%S1 | |
10221 | csy\t%0,%3,%S1" | |
10222 | [(set_attr "op_type" "RS,RSY") | |
3e4be43f | 10223 | (set_attr "cpu_facility" "*,longdisp") |
e0374221 AS |
10224 | (set_attr "type" "sem")]) |
10225 | ||
45d18331 AS |
10226 | ; |
10227 | ; Other atomic instruction patterns. | |
10228 | ; | |
10229 | ||
65b1d8ea AK |
10230 | ; z196 load and add, xor, or and and instructions |
10231 | ||
78ce265b RH |
10232 | (define_expand "atomic_fetch_<atomic><mode>" |
10233 | [(match_operand:GPR 0 "register_operand") ;; val out | |
10234 | (ATOMIC_Z196:GPR | |
10235 | (match_operand:GPR 1 "memory_operand") ;; memory | |
10236 | (match_operand:GPR 2 "register_operand")) ;; val in | |
10237 | (match_operand:SI 3 "const_int_operand")] ;; model | |
65b1d8ea | 10238 | "TARGET_Z196" |
78ce265b | 10239 | { |
75cc21e2 AK |
10240 | if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) |
10241 | FAIL; | |
10242 | ||
78ce265b RH |
10243 | emit_insn (gen_atomic_fetch_<atomic><mode>_iaf |
10244 | (operands[0], operands[1], operands[2])); | |
10245 | DONE; | |
10246 | }) | |
65b1d8ea AK |
10247 | |
10248 | ; lan, lang, lao, laog, lax, laxg, laa, laag | |
78ce265b RH |
10249 | (define_insn "atomic_fetch_<atomic><mode>_iaf" |
10250 | [(set (match_operand:GPR 0 "register_operand" "=d") | |
3e4be43f | 10251 | (match_operand:GPR 1 "memory_operand" "+S")) |
78ce265b RH |
10252 | (set (match_dup 1) |
10253 | (unspec_volatile:GPR | |
10254 | [(ATOMIC_Z196:GPR (match_dup 1) | |
10255 | (match_operand:GPR 2 "general_operand" "d"))] | |
10256 | UNSPECV_ATOMIC_OP)) | |
10257 | (clobber (reg:CC CC_REGNUM))] | |
65b1d8ea | 10258 | "TARGET_Z196" |
78ce265b RH |
10259 | "la<noxa><g>\t%0,%2,%1" |
10260 | [(set_attr "op_type" "RSY") | |
10261 | (set_attr "type" "sem")]) | |
65b1d8ea | 10262 | |
78ce265b RH |
10263 | ;; For SImode and larger, the optabs.c code will do just fine in |
10264 | ;; expanding a compare-and-swap loop. For QI/HImode, we can do | |
10265 | ;; better by expanding our own loop. | |
65b1d8ea | 10266 | |
78ce265b RH |
10267 | (define_expand "atomic_<atomic><mode>" |
10268 | [(ATOMIC:HQI | |
10269 | (match_operand:HQI 0 "memory_operand") ;; memory | |
10270 | (match_operand:HQI 1 "general_operand")) ;; val in | |
10271 | (match_operand:SI 2 "const_int_operand")] ;; model | |
45d18331 | 10272 | "" |
78ce265b RH |
10273 | { |
10274 | s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], | |
10275 | operands[1], false); | |
10276 | DONE; | |
10277 | }) | |
45d18331 | 10278 | |
78ce265b RH |
10279 | (define_expand "atomic_fetch_<atomic><mode>" |
10280 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10281 | (ATOMIC:HQI | |
10282 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10283 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10284 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 10285 | "" |
78ce265b RH |
10286 | { |
10287 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10288 | operands[2], false); | |
10289 | DONE; | |
10290 | }) | |
10291 | ||
10292 | (define_expand "atomic_<atomic>_fetch<mode>" | |
10293 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10294 | (ATOMIC:HQI | |
10295 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10296 | (match_operand:HQI 2 "general_operand")) ;; val in | |
10297 | (match_operand:SI 3 "const_int_operand")] ;; model | |
10298 | "" | |
10299 | { | |
10300 | s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], | |
10301 | operands[2], true); | |
10302 | DONE; | |
10303 | }) | |
10304 | ||
10305 | (define_expand "atomic_exchange<mode>" | |
10306 | [(match_operand:HQI 0 "register_operand") ;; val out | |
10307 | (match_operand:HQI 1 "memory_operand") ;; memory | |
10308 | (match_operand:HQI 2 "general_operand") ;; val in | |
10309 | (match_operand:SI 3 "const_int_operand")] ;; model | |
45d18331 | 10310 | "" |
78ce265b RH |
10311 | { |
10312 | s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], | |
10313 | operands[2], false); | |
10314 | DONE; | |
10315 | }) | |
45d18331 | 10316 | |
9db1d521 HP |
10317 | ;; |
10318 | ;;- Miscellaneous instructions. | |
10319 | ;; | |
10320 | ||
10321 | ; | |
10322 | ; allocate stack instruction pattern(s). | |
10323 | ; | |
10324 | ||
10325 | (define_expand "allocate_stack" | |
ef44a6ff UW |
10326 | [(match_operand 0 "general_operand" "") |
10327 | (match_operand 1 "general_operand" "")] | |
b3d31392 | 10328 | "TARGET_BACKCHAIN" |
9db1d521 | 10329 | { |
ef44a6ff | 10330 | rtx temp = gen_reg_rtx (Pmode); |
9db1d521 | 10331 | |
ef44a6ff UW |
10332 | emit_move_insn (temp, s390_back_chain_rtx ()); |
10333 | anti_adjust_stack (operands[1]); | |
10334 | emit_move_insn (s390_back_chain_rtx (), temp); | |
9db1d521 | 10335 | |
ef44a6ff UW |
10336 | emit_move_insn (operands[0], virtual_stack_dynamic_rtx); |
10337 | DONE; | |
10bbf137 | 10338 | }) |
9db1d521 HP |
10339 | |
10340 | ||
10341 | ; | |
43ab026f | 10342 | ; setjmp instruction pattern. |
9db1d521 HP |
10343 | ; |
10344 | ||
9db1d521 | 10345 | (define_expand "builtin_setjmp_receiver" |
fd7643fb | 10346 | [(match_operand 0 "" "")] |
f314b9b1 | 10347 | "flag_pic" |
9db1d521 | 10348 | { |
585539a1 | 10349 | emit_insn (s390_load_got ()); |
c41c1387 | 10350 | emit_use (pic_offset_table_rtx); |
9db1d521 | 10351 | DONE; |
fd7643fb | 10352 | }) |
9db1d521 | 10353 | |
9db1d521 HP |
10354 | ;; These patterns say how to save and restore the stack pointer. We need not |
10355 | ;; save the stack pointer at function level since we are careful to | |
10356 | ;; preserve the backchain. At block level, we have to restore the backchain | |
10357 | ;; when we restore the stack pointer. | |
10358 | ;; | |
10359 | ;; For nonlocal gotos, we must save both the stack pointer and its | |
10360 | ;; backchain and restore both. Note that in the nonlocal case, the | |
10361 | ;; save area is a memory location. | |
10362 | ||
10363 | (define_expand "save_stack_function" | |
10364 | [(match_operand 0 "general_operand" "") | |
10365 | (match_operand 1 "general_operand" "")] | |
10366 | "" | |
10367 | "DONE;") | |
10368 | ||
10369 | (define_expand "restore_stack_function" | |
10370 | [(match_operand 0 "general_operand" "") | |
10371 | (match_operand 1 "general_operand" "")] | |
10372 | "" | |
10373 | "DONE;") | |
10374 | ||
10375 | (define_expand "restore_stack_block" | |
ef44a6ff UW |
10376 | [(match_operand 0 "register_operand" "") |
10377 | (match_operand 1 "register_operand" "")] | |
b3d31392 | 10378 | "TARGET_BACKCHAIN" |
9db1d521 | 10379 | { |
ef44a6ff UW |
10380 | rtx temp = gen_reg_rtx (Pmode); |
10381 | ||
10382 | emit_move_insn (temp, s390_back_chain_rtx ()); | |
10383 | emit_move_insn (operands[0], operands[1]); | |
10384 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10385 | ||
10386 | DONE; | |
10bbf137 | 10387 | }) |
9db1d521 HP |
10388 | |
10389 | (define_expand "save_stack_nonlocal" | |
10390 | [(match_operand 0 "memory_operand" "") | |
10391 | (match_operand 1 "register_operand" "")] | |
10392 | "" | |
9db1d521 | 10393 | { |
ef44a6ff UW |
10394 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
10395 | ||
10396 | /* Copy the backchain to the first word, sp to the second and the | |
10397 | literal pool base to the third. */ | |
10398 | ||
9602b6a1 AK |
10399 | rtx save_bc = adjust_address (operands[0], Pmode, 0); |
10400 | rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); | |
10401 | rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10402 | ||
b3d31392 | 10403 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10404 | emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); |
ef44a6ff | 10405 | |
9602b6a1 AK |
10406 | emit_move_insn (save_sp, operands[1]); |
10407 | emit_move_insn (save_bp, base); | |
9db1d521 | 10408 | |
9db1d521 | 10409 | DONE; |
10bbf137 | 10410 | }) |
9db1d521 HP |
10411 | |
10412 | (define_expand "restore_stack_nonlocal" | |
10413 | [(match_operand 0 "register_operand" "") | |
10414 | (match_operand 1 "memory_operand" "")] | |
10415 | "" | |
9db1d521 | 10416 | { |
490ceeb4 | 10417 | rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); |
ef44a6ff | 10418 | rtx temp = NULL_RTX; |
9db1d521 | 10419 | |
43ab026f | 10420 | /* Restore the backchain from the first word, sp from the second and the |
ff482c8d | 10421 | literal pool base from the third. */ |
43ab026f | 10422 | |
9602b6a1 AK |
10423 | rtx save_bc = adjust_address (operands[1], Pmode, 0); |
10424 | rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); | |
10425 | rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); | |
10426 | ||
b3d31392 | 10427 | if (TARGET_BACKCHAIN) |
9602b6a1 | 10428 | temp = force_reg (Pmode, save_bc); |
9381e3f1 | 10429 | |
9602b6a1 AK |
10430 | emit_move_insn (base, save_bp); |
10431 | emit_move_insn (operands[0], save_sp); | |
ef44a6ff UW |
10432 | |
10433 | if (temp) | |
10434 | emit_move_insn (s390_back_chain_rtx (), temp); | |
10435 | ||
c41c1387 | 10436 | emit_use (base); |
9db1d521 | 10437 | DONE; |
10bbf137 | 10438 | }) |
9db1d521 | 10439 | |
7bcebb25 AK |
10440 | (define_expand "exception_receiver" |
10441 | [(const_int 0)] | |
10442 | "" | |
10443 | { | |
10444 | s390_set_has_landing_pad_p (true); | |
10445 | DONE; | |
10446 | }) | |
9db1d521 HP |
10447 | |
10448 | ; | |
10449 | ; nop instruction pattern(s). | |
10450 | ; | |
10451 | ||
10452 | (define_insn "nop" | |
10453 | [(const_int 0)] | |
10454 | "" | |
d40c829f | 10455 | "lr\t0,0" |
729e750f WG |
10456 | [(set_attr "op_type" "RR") |
10457 | (set_attr "z10prop" "z10_fr_E1")]) | |
9db1d521 | 10458 | |
d277db6b WG |
10459 | (define_insn "nop1" |
10460 | [(const_int 1)] | |
10461 | "" | |
10462 | "lr\t1,1" | |
10463 | [(set_attr "op_type" "RR")]) | |
10464 | ||
f8af0e30 DV |
10465 | ;;- Undeletable nops (used for hotpatching) |
10466 | ||
10467 | (define_insn "nop_2_byte" | |
10468 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)] | |
10469 | "" | |
4bbc8970 | 10470 | "nopr\t%%r0" |
f8af0e30 DV |
10471 | [(set_attr "op_type" "RR")]) |
10472 | ||
10473 | (define_insn "nop_4_byte" | |
10474 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)] | |
10475 | "" | |
10476 | "nop\t0" | |
10477 | [(set_attr "op_type" "RX")]) | |
10478 | ||
10479 | (define_insn "nop_6_byte" | |
10480 | [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)] | |
10481 | "TARGET_CPU_ZARCH" | |
10482 | "brcl\t0, 0" | |
10483 | [(set_attr "op_type" "RIL")]) | |
10484 | ||
9db1d521 HP |
10485 | |
10486 | ; | |
10487 | ; Special literal pool access instruction pattern(s). | |
10488 | ; | |
10489 | ||
416cf582 UW |
10490 | (define_insn "*pool_entry" |
10491 | [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] | |
10492 | UNSPECV_POOL_ENTRY)] | |
9db1d521 | 10493 | "" |
9db1d521 | 10494 | { |
ef4bddc2 | 10495 | machine_mode mode = GET_MODE (PATTERN (insn)); |
416cf582 | 10496 | unsigned int align = GET_MODE_BITSIZE (mode); |
faeb9bb6 | 10497 | s390_output_pool_entry (operands[0], mode, align); |
fd7643fb UW |
10498 | return ""; |
10499 | } | |
b628bd8e | 10500 | [(set (attr "length") |
416cf582 | 10501 | (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) |
b2ccb744 | 10502 | |
9bb86f41 UW |
10503 | (define_insn "pool_align" |
10504 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] | |
10505 | UNSPECV_POOL_ALIGN)] | |
10506 | "" | |
10507 | ".align\t%0" | |
b628bd8e | 10508 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
b2ccb744 | 10509 | |
9bb86f41 UW |
10510 | (define_insn "pool_section_start" |
10511 | [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] | |
10512 | "" | |
b929b470 MK |
10513 | { |
10514 | switch_to_section (targetm.asm_out.function_rodata_section | |
10515 | (current_function_decl)); | |
10516 | return ""; | |
10517 | } | |
b628bd8e | 10518 | [(set_attr "length" "0")]) |
b2ccb744 | 10519 | |
9bb86f41 UW |
10520 | (define_insn "pool_section_end" |
10521 | [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] | |
10522 | "" | |
b929b470 MK |
10523 | { |
10524 | switch_to_section (current_function_section ()); | |
10525 | return ""; | |
10526 | } | |
b628bd8e | 10527 | [(set_attr "length" "0")]) |
b2ccb744 | 10528 | |
5af2f3d3 | 10529 | (define_insn "main_base_31_small" |
9e8327e3 UW |
10530 | [(set (match_operand 0 "register_operand" "=a") |
10531 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
10532 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
10533 | "basr\t%0,0" |
10534 | [(set_attr "op_type" "RR") | |
65b1d8ea AK |
10535 | (set_attr "type" "la") |
10536 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
10537 | |
10538 | (define_insn "main_base_31_large" | |
9e8327e3 UW |
10539 | [(set (match_operand 0 "register_operand" "=a") |
10540 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) | |
5af2f3d3 | 10541 | (set (pc) (label_ref (match_operand 2 "" "")))] |
9e8327e3 | 10542 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" |
5af2f3d3 | 10543 | "bras\t%0,%2" |
65b1d8ea AK |
10544 | [(set_attr "op_type" "RI") |
10545 | (set_attr "z196prop" "z196_cracked")]) | |
5af2f3d3 UW |
10546 | |
10547 | (define_insn "main_base_64" | |
9e8327e3 UW |
10548 | [(set (match_operand 0 "register_operand" "=a") |
10549 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] | |
10550 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
5af2f3d3 UW |
10551 | "larl\t%0,%1" |
10552 | [(set_attr "op_type" "RIL") | |
9381e3f1 | 10553 | (set_attr "type" "larl") |
729e750f | 10554 | (set_attr "z10prop" "z10_fwd_A1")]) |
5af2f3d3 UW |
10555 | |
10556 | (define_insn "main_pool" | |
585539a1 UW |
10557 | [(set (match_operand 0 "register_operand" "=a") |
10558 | (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] | |
10559 | "GET_MODE (operands[0]) == Pmode" | |
8d933e31 AS |
10560 | { |
10561 | gcc_unreachable (); | |
10562 | } | |
9381e3f1 | 10563 | [(set (attr "type") |
d7f99b2c | 10564 | (if_then_else (match_test "TARGET_CPU_ZARCH") |
ea77e738 | 10565 | (const_string "larl") (const_string "la")))]) |
5af2f3d3 | 10566 | |
aee4e0db | 10567 | (define_insn "reload_base_31" |
9e8327e3 UW |
10568 | [(set (match_operand 0 "register_operand" "=a") |
10569 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
10570 | "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10571 | "basr\t%0,0\;la\t%0,%1-.(%0)" |
b628bd8e | 10572 | [(set_attr "length" "6") |
65b1d8ea AK |
10573 | (set_attr "type" "la") |
10574 | (set_attr "z196prop" "z196_cracked")]) | |
b2ccb744 | 10575 | |
aee4e0db | 10576 | (define_insn "reload_base_64" |
9e8327e3 UW |
10577 | [(set (match_operand 0 "register_operand" "=a") |
10578 | (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] | |
10579 | "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10580 | "larl\t%0,%1" |
aee4e0db | 10581 | [(set_attr "op_type" "RIL") |
9381e3f1 | 10582 | (set_attr "type" "larl") |
729e750f | 10583 | (set_attr "z10prop" "z10_fwd_A1")]) |
aee4e0db | 10584 | |
aee4e0db | 10585 | (define_insn "pool" |
fd7643fb | 10586 | [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] |
aee4e0db | 10587 | "" |
8d933e31 AS |
10588 | { |
10589 | gcc_unreachable (); | |
10590 | } | |
b628bd8e | 10591 | [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) |
9db1d521 | 10592 | |
4023fb28 UW |
10593 | ;; |
10594 | ;; Insns related to generating the function prologue and epilogue. | |
10595 | ;; | |
10596 | ||
10597 | ||
10598 | (define_expand "prologue" | |
10599 | [(use (const_int 0))] | |
10600 | "" | |
10bbf137 | 10601 | "s390_emit_prologue (); DONE;") |
4023fb28 UW |
10602 | |
10603 | (define_expand "epilogue" | |
10604 | [(use (const_int 1))] | |
10605 | "" | |
ed9676cf AK |
10606 | "s390_emit_epilogue (false); DONE;") |
10607 | ||
10608 | (define_expand "sibcall_epilogue" | |
10609 | [(use (const_int 0))] | |
10610 | "" | |
10611 | "s390_emit_epilogue (true); DONE;") | |
4023fb28 | 10612 | |
177bc204 RS |
10613 | ;; A direct return instruction, without using an epilogue. |
10614 | (define_insn "<code>" | |
10615 | [(ANY_RETURN)] | |
10616 | "s390_can_use_<code>_insn ()" | |
10617 | "br\t%%r14" | |
10618 | [(set_attr "op_type" "RR") | |
10619 | (set_attr "type" "jsr") | |
10620 | (set_attr "atype" "agen")]) | |
10621 | ||
9e8327e3 | 10622 | (define_insn "*return" |
4023fb28 | 10623 | [(return) |
9e8327e3 UW |
10624 | (use (match_operand 0 "register_operand" "a"))] |
10625 | "GET_MODE (operands[0]) == Pmode" | |
d40c829f | 10626 | "br\t%0" |
4023fb28 | 10627 | [(set_attr "op_type" "RR") |
c7453384 | 10628 | (set_attr "type" "jsr") |
077dab3b | 10629 | (set_attr "atype" "agen")]) |
4023fb28 | 10630 | |
4023fb28 | 10631 | |
c7453384 | 10632 | ;; Instruction definition to extend a 31-bit pointer into a 64-bit |
839a4992 | 10633 | ;; pointer. This is used for compatibility. |
c7453384 EC |
10634 | |
10635 | (define_expand "ptr_extend" | |
10636 | [(set (match_operand:DI 0 "register_operand" "=r") | |
10637 | (match_operand:SI 1 "register_operand" "r"))] | |
9e8327e3 | 10638 | "TARGET_64BIT" |
c7453384 | 10639 | { |
c7453384 EC |
10640 | emit_insn (gen_anddi3 (operands[0], |
10641 | gen_lowpart (DImode, operands[1]), | |
10642 | GEN_INT (0x7fffffff))); | |
c7453384 | 10643 | DONE; |
10bbf137 | 10644 | }) |
4798630c D |
10645 | |
10646 | ;; Instruction definition to expand eh_return macro to support | |
10647 | ;; swapping in special linkage return addresses. | |
10648 | ||
10649 | (define_expand "eh_return" | |
10650 | [(use (match_operand 0 "register_operand" ""))] | |
10651 | "TARGET_TPF" | |
10652 | { | |
10653 | s390_emit_tpf_eh_return (operands[0]); | |
10654 | DONE; | |
10655 | }) | |
10656 | ||
7b8acc34 AK |
10657 | ; |
10658 | ; Stack Protector Patterns | |
10659 | ; | |
10660 | ||
10661 | (define_expand "stack_protect_set" | |
10662 | [(set (match_operand 0 "memory_operand" "") | |
10663 | (match_operand 1 "memory_operand" ""))] | |
10664 | "" | |
10665 | { | |
10666 | #ifdef TARGET_THREAD_SSP_OFFSET | |
10667 | operands[1] | |
10668 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
10669 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
10670 | #endif | |
10671 | if (TARGET_64BIT) | |
10672 | emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); | |
10673 | else | |
10674 | emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); | |
10675 | ||
10676 | DONE; | |
10677 | }) | |
10678 | ||
10679 | (define_insn "stack_protect_set<mode>" | |
10680 | [(set (match_operand:DSI 0 "memory_operand" "=Q") | |
10681 | (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] | |
10682 | "" | |
10683 | "mvc\t%O0(%G0,%R0),%S1" | |
10684 | [(set_attr "op_type" "SS")]) | |
10685 | ||
10686 | (define_expand "stack_protect_test" | |
10687 | [(set (reg:CC CC_REGNUM) | |
10688 | (compare (match_operand 0 "memory_operand" "") | |
10689 | (match_operand 1 "memory_operand" ""))) | |
10690 | (match_operand 2 "" "")] | |
10691 | "" | |
10692 | { | |
f90b7a5a | 10693 | rtx cc_reg, test; |
7b8acc34 AK |
10694 | #ifdef TARGET_THREAD_SSP_OFFSET |
10695 | operands[1] | |
10696 | = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), | |
10697 | GEN_INT (TARGET_THREAD_SSP_OFFSET))); | |
10698 | #endif | |
7b8acc34 AK |
10699 | if (TARGET_64BIT) |
10700 | emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); | |
10701 | else | |
10702 | emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); | |
10703 | ||
f90b7a5a PB |
10704 | cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); |
10705 | test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); | |
10706 | emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); | |
7b8acc34 AK |
10707 | DONE; |
10708 | }) | |
10709 | ||
10710 | (define_insn "stack_protect_test<mode>" | |
10711 | [(set (reg:CCZ CC_REGNUM) | |
10712 | (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") | |
10713 | (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] | |
10714 | "" | |
10715 | "clc\t%O0(%G0,%R0),%S1" | |
10716 | [(set_attr "op_type" "SS")]) | |
12959abe AK |
10717 | |
10718 | ; This is used in s390_emit_prologue in order to prevent insns | |
10719 | ; adjusting the stack pointer to be moved over insns writing stack | |
10720 | ; slots using a copy of the stack pointer in a different register. | |
10721 | (define_insn "stack_tie" | |
10722 | [(set (match_operand:BLK 0 "memory_operand" "+m") | |
10723 | (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] | |
10724 | "" | |
10725 | "" | |
10726 | [(set_attr "length" "0")]) | |
963fc8d0 AK |
10727 | |
10728 | ||
82c6f58a AK |
10729 | (define_insn "stack_restore_from_fpr" |
10730 | [(set (reg:DI STACK_REGNUM) | |
10731 | (match_operand:DI 0 "register_operand" "f")) | |
10732 | (clobber (mem:BLK (scratch)))] | |
10733 | "TARGET_Z10" | |
10734 | "lgdr\t%%r15,%0" | |
10735 | [(set_attr "op_type" "RRE")]) | |
10736 | ||
963fc8d0 AK |
10737 | ; |
10738 | ; Data prefetch patterns | |
10739 | ; | |
10740 | ||
10741 | (define_insn "prefetch" | |
3e4be43f UW |
10742 | [(prefetch (match_operand 0 "address_operand" "ZT,X") |
10743 | (match_operand:SI 1 "const_int_operand" " n,n") | |
10744 | (match_operand:SI 2 "const_int_operand" " n,n"))] | |
22d72dbc | 10745 | "TARGET_Z10" |
963fc8d0 | 10746 | { |
4fe6dea8 AK |
10747 | switch (which_alternative) |
10748 | { | |
10749 | case 0: | |
4fe6dea8 | 10750 | return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; |
22d72dbc | 10751 | case 1: |
4fe6dea8 AK |
10752 | if (larl_operand (operands[0], Pmode)) |
10753 | return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; | |
a65593a4 | 10754 | /* fallthrough */ |
4fe6dea8 AK |
10755 | default: |
10756 | ||
10757 | /* This might be reached for symbolic operands with an odd | |
10758 | addend. We simply omit the prefetch for such rare cases. */ | |
10759 | ||
10760 | return ""; | |
10761 | } | |
9381e3f1 | 10762 | } |
22d72dbc AK |
10763 | [(set_attr "type" "load,larl") |
10764 | (set_attr "op_type" "RXY,RIL") | |
65b1d8ea AK |
10765 | (set_attr "z10prop" "z10_super") |
10766 | (set_attr "z196prop" "z196_alone")]) | |
07da44ab AK |
10767 | |
10768 | ||
10769 | ; | |
10770 | ; Byte swap instructions | |
10771 | ; | |
10772 | ||
511f5bb1 AK |
10773 | ; FIXME: There is also mvcin but we cannot use it since src and target |
10774 | ; may overlap. | |
50dc4eed | 10775 | ; lrvr, lrv, strv, lrvgr, lrvg, strvg |
07da44ab | 10776 | (define_insn "bswap<mode>2" |
3e4be43f UW |
10777 | [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,T") |
10778 | (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,T,d")))] | |
677fbff4 | 10779 | "TARGET_CPU_ZARCH" |
07da44ab AK |
10780 | "@ |
10781 | lrv<g>r\t%0,%1 | |
6f5a59d1 AK |
10782 | lrv<g>\t%0,%1 |
10783 | strv<g>\t%1,%0" | |
10784 | [(set_attr "type" "*,load,store") | |
10785 | (set_attr "op_type" "RRE,RXY,RXY") | |
07da44ab | 10786 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 10787 | |
511f5bb1 | 10788 | (define_insn "bswaphi2" |
3e4be43f UW |
10789 | [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,T") |
10790 | (bswap:HI (match_operand:HI 1 "nonimmediate_operand" " d,T,d")))] | |
511f5bb1 | 10791 | "TARGET_CPU_ZARCH" |
6f5a59d1 AK |
10792 | "@ |
10793 | # | |
10794 | lrvh\t%0,%1 | |
10795 | strvh\t%1,%0" | |
10796 | [(set_attr "type" "*,load,store") | |
10797 | (set_attr "op_type" "RRE,RXY,RXY") | |
511f5bb1 | 10798 | (set_attr "z10prop" "z10_super")]) |
65b1d8ea | 10799 | |
6f5a59d1 AK |
10800 | (define_split |
10801 | [(set (match_operand:HI 0 "register_operand" "") | |
10802 | (bswap:HI (match_operand:HI 1 "register_operand" "")))] | |
10803 | "TARGET_CPU_ZARCH" | |
10804 | [(set (match_dup 2) (bswap:SI (match_dup 3))) | |
9060e335 | 10805 | (set (match_dup 2) (lshiftrt:SI (match_dup 2) (const_int 16)))] |
6f5a59d1 | 10806 | { |
9060e335 | 10807 | operands[2] = simplify_gen_subreg (SImode, operands[0], HImode, 0); |
6f5a59d1 AK |
10808 | operands[3] = simplify_gen_subreg (SImode, operands[1], HImode, 0); |
10809 | }) | |
10810 | ||
10811 | ||
65b1d8ea AK |
10812 | ; |
10813 | ; Population count instruction | |
10814 | ; | |
10815 | ||
10816 | ; The S/390 popcount instruction counts the bits of op1 in 8 byte | |
10817 | ; portions and stores the result in the corresponding bytes in op0. | |
10818 | (define_insn "*popcount<mode>" | |
10819 | [(set (match_operand:INT 0 "register_operand" "=d") | |
10820 | (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) | |
10821 | (clobber (reg:CC CC_REGNUM))] | |
10822 | "TARGET_Z196" | |
10823 | "popcnt\t%0,%1" | |
10824 | [(set_attr "op_type" "RRE")]) | |
10825 | ||
10826 | (define_expand "popcountdi2" | |
10827 | [; popcnt op0, op1 | |
10828 | (parallel [(set (match_operand:DI 0 "register_operand" "") | |
10829 | (unspec:DI [(match_operand:DI 1 "register_operand")] | |
10830 | UNSPEC_POPCNT)) | |
10831 | (clobber (reg:CC CC_REGNUM))]) | |
10832 | ; sllg op2, op0, 32 | |
10833 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) | |
10834 | ; agr op0, op2 | |
10835 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10836 | (clobber (reg:CC CC_REGNUM))]) | |
10837 | ; sllg op2, op0, 16 | |
17465c6e | 10838 | (set (match_dup 2) |
65b1d8ea AK |
10839 | (ashift:DI (match_dup 0) (const_int 16))) |
10840 | ; agr op0, op2 | |
10841 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10842 | (clobber (reg:CC CC_REGNUM))]) | |
10843 | ; sllg op2, op0, 8 | |
10844 | (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) | |
10845 | ; agr op0, op2 | |
10846 | (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) | |
10847 | (clobber (reg:CC CC_REGNUM))]) | |
10848 | ; srlg op0, op0, 56 | |
10849 | (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] | |
10850 | "TARGET_Z196 && TARGET_64BIT" | |
10851 | "operands[2] = gen_reg_rtx (DImode);") | |
10852 | ||
10853 | (define_expand "popcountsi2" | |
10854 | [; popcnt op0, op1 | |
10855 | (parallel [(set (match_operand:SI 0 "register_operand" "") | |
10856 | (unspec:SI [(match_operand:SI 1 "register_operand")] | |
10857 | UNSPEC_POPCNT)) | |
10858 | (clobber (reg:CC CC_REGNUM))]) | |
10859 | ; sllk op2, op0, 16 | |
17465c6e | 10860 | (set (match_dup 2) |
65b1d8ea AK |
10861 | (ashift:SI (match_dup 0) (const_int 16))) |
10862 | ; ar op0, op2 | |
10863 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
10864 | (clobber (reg:CC CC_REGNUM))]) | |
10865 | ; sllk op2, op0, 8 | |
10866 | (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) | |
10867 | ; ar op0, op2 | |
10868 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
10869 | (clobber (reg:CC CC_REGNUM))]) | |
10870 | ; srl op0, op0, 24 | |
10871 | (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] | |
10872 | "TARGET_Z196" | |
10873 | "operands[2] = gen_reg_rtx (SImode);") | |
10874 | ||
10875 | (define_expand "popcounthi2" | |
10876 | [; popcnt op0, op1 | |
10877 | (parallel [(set (match_operand:HI 0 "register_operand" "") | |
10878 | (unspec:HI [(match_operand:HI 1 "register_operand")] | |
10879 | UNSPEC_POPCNT)) | |
10880 | (clobber (reg:CC CC_REGNUM))]) | |
10881 | ; sllk op2, op0, 8 | |
17465c6e | 10882 | (set (match_dup 2) |
65b1d8ea AK |
10883 | (ashift:SI (match_dup 0) (const_int 8))) |
10884 | ; ar op0, op2 | |
10885 | (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) | |
10886 | (clobber (reg:CC CC_REGNUM))]) | |
10887 | ; srl op0, op0, 8 | |
10888 | (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] | |
10889 | "TARGET_Z196" | |
10890 | "operands[2] = gen_reg_rtx (SImode);") | |
10891 | ||
10892 | (define_expand "popcountqi2" | |
10893 | [; popcnt op0, op1 | |
10894 | (parallel [(set (match_operand:QI 0 "register_operand" "") | |
10895 | (unspec:QI [(match_operand:QI 1 "register_operand")] | |
10896 | UNSPEC_POPCNT)) | |
10897 | (clobber (reg:CC CC_REGNUM))])] | |
10898 | "TARGET_Z196" | |
10899 | "") | |
10900 | ||
10901 | ;; | |
10902 | ;;- Copy sign instructions | |
10903 | ;; | |
10904 | ||
10905 | (define_insn "copysign<mode>3" | |
10906 | [(set (match_operand:FP 0 "register_operand" "=f") | |
10907 | (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") | |
10908 | (match_operand:FP 2 "register_operand" "f")] | |
10909 | UNSPEC_COPYSIGN))] | |
10910 | "TARGET_Z196" | |
10911 | "cpsdr\t%0,%2,%1" | |
10912 | [(set_attr "op_type" "RRF") | |
10913 | (set_attr "type" "fsimp<mode>")]) | |
5a3fe9b6 AK |
10914 | |
10915 | ||
10916 | ;; | |
10917 | ;;- Transactional execution instructions | |
10918 | ;; | |
10919 | ||
10920 | ; This splitter helps combine to make use of CC directly when | |
10921 | ; comparing the integer result of a tbegin builtin with a constant. | |
10922 | ; The unspec is already removed by canonicalize_comparison. So this | |
10923 | ; splitters only job is to turn the PARALLEL into separate insns | |
10924 | ; again. Unfortunately this only works with the very first cc/int | |
10925 | ; compare since combine is not able to deal with data flow across | |
10926 | ; basic block boundaries. | |
10927 | ||
10928 | ; It needs to be an insn pattern as well since combine does not apply | |
10929 | ; the splitter directly. Combine would only use it if it actually | |
10930 | ; would reduce the number of instructions. | |
10931 | (define_insn_and_split "*ccraw_to_int" | |
10932 | [(set (pc) | |
10933 | (if_then_else | |
10934 | (match_operator 0 "s390_eqne_operator" | |
10935 | [(reg:CCRAW CC_REGNUM) | |
10936 | (match_operand 1 "const_int_operand" "")]) | |
10937 | (label_ref (match_operand 2 "" "")) | |
10938 | (pc))) | |
10939 | (set (match_operand:SI 3 "register_operand" "=d") | |
10940 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] | |
10941 | "" | |
10942 | "#" | |
10943 | "" | |
10944 | [(set (match_dup 3) | |
10945 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) | |
10946 | (set (pc) | |
10947 | (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)]) | |
10948 | (label_ref (match_dup 2)) | |
10949 | (pc)))] | |
10950 | "") | |
10951 | ||
10952 | ; Non-constrained transaction begin | |
10953 | ||
10954 | (define_expand "tbegin" | |
ee163e72 AK |
10955 | [(match_operand:SI 0 "register_operand" "") |
10956 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
10957 | "TARGET_HTM" |
10958 | { | |
10959 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true); | |
10960 | DONE; | |
10961 | }) | |
10962 | ||
10963 | (define_expand "tbegin_nofloat" | |
ee163e72 AK |
10964 | [(match_operand:SI 0 "register_operand" "") |
10965 | (match_operand:BLK 1 "memory_operand" "")] | |
5a3fe9b6 AK |
10966 | "TARGET_HTM" |
10967 | { | |
10968 | s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false); | |
10969 | DONE; | |
10970 | }) | |
10971 | ||
10972 | (define_expand "tbegin_retry" | |
ee163e72 AK |
10973 | [(match_operand:SI 0 "register_operand" "") |
10974 | (match_operand:BLK 1 "memory_operand" "") | |
10975 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
10976 | "TARGET_HTM" |
10977 | { | |
10978 | s390_expand_tbegin (operands[0], operands[1], operands[2], true); | |
10979 | DONE; | |
10980 | }) | |
10981 | ||
10982 | (define_expand "tbegin_retry_nofloat" | |
ee163e72 AK |
10983 | [(match_operand:SI 0 "register_operand" "") |
10984 | (match_operand:BLK 1 "memory_operand" "") | |
10985 | (match_operand:SI 2 "general_operand" "")] | |
5a3fe9b6 AK |
10986 | "TARGET_HTM" |
10987 | { | |
10988 | s390_expand_tbegin (operands[0], operands[1], operands[2], false); | |
10989 | DONE; | |
10990 | }) | |
10991 | ||
c914ac45 AK |
10992 | ; Clobber VRs since they don't get restored |
10993 | (define_insn "tbegin_1_z13" | |
10994 | [(set (reg:CCRAW CC_REGNUM) | |
10995 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] | |
10996 | UNSPECV_TBEGIN)) | |
10997 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
10998 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
10999 | (clobber (reg:TI 16)) (clobber (reg:TI 38)) | |
11000 | (clobber (reg:TI 17)) (clobber (reg:TI 39)) | |
11001 | (clobber (reg:TI 18)) (clobber (reg:TI 40)) | |
11002 | (clobber (reg:TI 19)) (clobber (reg:TI 41)) | |
11003 | (clobber (reg:TI 20)) (clobber (reg:TI 42)) | |
11004 | (clobber (reg:TI 21)) (clobber (reg:TI 43)) | |
11005 | (clobber (reg:TI 22)) (clobber (reg:TI 44)) | |
11006 | (clobber (reg:TI 23)) (clobber (reg:TI 45)) | |
11007 | (clobber (reg:TI 24)) (clobber (reg:TI 46)) | |
11008 | (clobber (reg:TI 25)) (clobber (reg:TI 47)) | |
11009 | (clobber (reg:TI 26)) (clobber (reg:TI 48)) | |
11010 | (clobber (reg:TI 27)) (clobber (reg:TI 49)) | |
11011 | (clobber (reg:TI 28)) (clobber (reg:TI 50)) | |
11012 | (clobber (reg:TI 29)) (clobber (reg:TI 51)) | |
11013 | (clobber (reg:TI 30)) (clobber (reg:TI 52)) | |
11014 | (clobber (reg:TI 31)) (clobber (reg:TI 53))] | |
11015 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
11016 | ; not supposed to be used for immediates (see genpreds.c). | |
11017 | "TARGET_VX && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11018 | "tbegin\t%1,%x0" | |
11019 | [(set_attr "op_type" "SIL")]) | |
11020 | ||
5a3fe9b6 AK |
11021 | (define_insn "tbegin_1" |
11022 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d | 11023 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
5a3fe9b6 | 11024 | UNSPECV_TBEGIN)) |
2561451d AK |
11025 | (set (match_operand:BLK 1 "memory_operand" "=Q") |
11026 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) | |
5a3fe9b6 AK |
11027 | (clobber (reg:DF 16)) |
11028 | (clobber (reg:DF 17)) | |
11029 | (clobber (reg:DF 18)) | |
11030 | (clobber (reg:DF 19)) | |
11031 | (clobber (reg:DF 20)) | |
11032 | (clobber (reg:DF 21)) | |
11033 | (clobber (reg:DF 22)) | |
11034 | (clobber (reg:DF 23)) | |
11035 | (clobber (reg:DF 24)) | |
11036 | (clobber (reg:DF 25)) | |
11037 | (clobber (reg:DF 26)) | |
11038 | (clobber (reg:DF 27)) | |
11039 | (clobber (reg:DF 28)) | |
11040 | (clobber (reg:DF 29)) | |
11041 | (clobber (reg:DF 30)) | |
11042 | (clobber (reg:DF 31))] | |
11043 | ; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is | |
11044 | ; not supposed to be used for immediates (see genpreds.c). | |
2561451d AK |
11045 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" |
11046 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
11047 | [(set_attr "op_type" "SIL")]) |
11048 | ||
11049 | ; Same as above but without the FPR clobbers | |
11050 | (define_insn "tbegin_nofloat_1" | |
11051 | [(set (reg:CCRAW CC_REGNUM) | |
2561451d AK |
11052 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] |
11053 | UNSPECV_TBEGIN)) | |
11054 | (set (match_operand:BLK 1 "memory_operand" "=Q") | |
11055 | (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))] | |
11056 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11057 | "tbegin\t%1,%x0" | |
5a3fe9b6 AK |
11058 | [(set_attr "op_type" "SIL")]) |
11059 | ||
11060 | ||
11061 | ; Constrained transaction begin | |
11062 | ||
11063 | (define_expand "tbeginc" | |
11064 | [(set (reg:CCRAW CC_REGNUM) | |
11065 | (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)] | |
11066 | UNSPECV_TBEGINC))] | |
11067 | "TARGET_HTM" | |
11068 | "") | |
11069 | ||
11070 | (define_insn "*tbeginc_1" | |
11071 | [(set (reg:CCRAW CC_REGNUM) | |
11072 | (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")] | |
11073 | UNSPECV_TBEGINC))] | |
11074 | "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" | |
11075 | "tbeginc\t0,%x0" | |
11076 | [(set_attr "op_type" "SIL")]) | |
11077 | ||
11078 | ; Transaction end | |
11079 | ||
11080 | (define_expand "tend" | |
11081 | [(set (reg:CCRAW CC_REGNUM) | |
11082 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND)) | |
ee163e72 | 11083 | (set (match_operand:SI 0 "register_operand" "") |
5a3fe9b6 AK |
11084 | (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] |
11085 | "TARGET_HTM" | |
11086 | "") | |
11087 | ||
11088 | (define_insn "*tend_1" | |
11089 | [(set (reg:CCRAW CC_REGNUM) | |
11090 | (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))] | |
11091 | "TARGET_HTM" | |
11092 | "tend" | |
11093 | [(set_attr "op_type" "S")]) | |
11094 | ||
11095 | ; Transaction abort | |
11096 | ||
11097 | (define_expand "tabort" | |
eae48192 | 11098 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "")] |
5a3fe9b6 AK |
11099 | UNSPECV_TABORT)] |
11100 | "TARGET_HTM && operands != NULL" | |
11101 | { | |
11102 | if (CONST_INT_P (operands[0]) | |
11103 | && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255) | |
11104 | { | |
f3981e7e | 11105 | error ("invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC |
5a3fe9b6 AK |
11106 | ". Values in range 0 through 255 are reserved.", |
11107 | INTVAL (operands[0])); | |
11108 | FAIL; | |
11109 | } | |
11110 | }) | |
11111 | ||
11112 | (define_insn "*tabort_1" | |
eae48192 | 11113 | [(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "aJ")] |
5a3fe9b6 AK |
11114 | UNSPECV_TABORT)] |
11115 | "TARGET_HTM && operands != NULL" | |
11116 | "tabort\t%Y0" | |
11117 | [(set_attr "op_type" "S")]) | |
11118 | ||
eae48192 AK |
11119 | (define_insn "*tabort_1_plus" |
11120 | [(unspec_volatile [(plus:SI (match_operand:SI 0 "register_operand" "a") | |
11121 | (match_operand:SI 1 "const_int_operand" "J"))] | |
11122 | UNSPECV_TABORT)] | |
11123 | "TARGET_HTM && operands != NULL | |
11124 | && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")" | |
11125 | "tabort\t%1(%0)" | |
11126 | [(set_attr "op_type" "S")]) | |
11127 | ||
5a3fe9b6 AK |
11128 | ; Transaction extract nesting depth |
11129 | ||
11130 | (define_insn "etnd" | |
11131 | [(set (match_operand:SI 0 "register_operand" "=d") | |
11132 | (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))] | |
11133 | "TARGET_HTM" | |
11134 | "etnd\t%0" | |
11135 | [(set_attr "op_type" "RRE")]) | |
11136 | ||
11137 | ; Non-transactional store | |
11138 | ||
11139 | (define_insn "ntstg" | |
3e4be43f | 11140 | [(set (match_operand:DI 0 "memory_operand" "=T") |
5a3fe9b6 AK |
11141 | (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] |
11142 | UNSPECV_NTSTG))] | |
11143 | "TARGET_HTM" | |
11144 | "ntstg\t%1,%0" | |
11145 | [(set_attr "op_type" "RXY")]) | |
11146 | ||
11147 | ; Transaction perform processor assist | |
11148 | ||
11149 | (define_expand "tx_assist" | |
2561451d AK |
11150 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "") |
11151 | (reg:SI GPR0_REGNUM) | |
5a3fe9b6 AK |
11152 | (const_int 1)] |
11153 | UNSPECV_PPA)] | |
11154 | "TARGET_HTM" | |
2561451d | 11155 | "") |
5a3fe9b6 AK |
11156 | |
11157 | (define_insn "*ppa" | |
11158 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") | |
11159 | (match_operand:SI 1 "register_operand" "d") | |
11160 | (match_operand 2 "const_int_operand" "I")] | |
11161 | UNSPECV_PPA)] | |
11162 | "TARGET_HTM && INTVAL (operands[2]) < 16" | |
2561451d | 11163 | "ppa\t%0,%1,%2" |
5a3fe9b6 | 11164 | [(set_attr "op_type" "RRF")]) |
004f64e1 AK |
11165 | |
11166 | ||
11167 | ; Set and get floating point control register | |
11168 | ||
3af82a61 | 11169 | (define_insn "sfpc" |
004f64e1 AK |
11170 | [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] |
11171 | UNSPECV_SFPC)] | |
11172 | "TARGET_HARD_FLOAT" | |
11173 | "sfpc\t%0") | |
11174 | ||
3af82a61 | 11175 | (define_insn "efpc" |
004f64e1 AK |
11176 | [(set (match_operand:SI 0 "register_operand" "=d") |
11177 | (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))] | |
11178 | "TARGET_HARD_FLOAT" | |
11179 | "efpc\t%0") | |
3af82a61 AK |
11180 | |
11181 | ||
11182 | ; Load count to block boundary | |
11183 | ||
11184 | (define_insn "lcbb" | |
11185 | [(set (match_operand:SI 0 "register_operand" "=d") | |
3e4be43f | 11186 | (unspec:SI [(match_operand 1 "address_operand" "ZR") |
3af82a61 AK |
11187 | (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB)) |
11188 | (clobber (reg:CC CC_REGNUM))] | |
11189 | "TARGET_Z13" | |
9a36359e | 11190 | "lcbb\t%0,%a1,%b2" |
3af82a61 | 11191 | [(set_attr "op_type" "VRX")]) |
4cb4721f MK |
11192 | |
11193 | ; Handle -fsplit-stack. | |
11194 | ||
11195 | (define_expand "split_stack_prologue" | |
11196 | [(const_int 0)] | |
11197 | "" | |
11198 | { | |
11199 | s390_expand_split_stack_prologue (); | |
11200 | DONE; | |
11201 | }) | |
11202 | ||
11203 | ;; If there are operand 0 bytes available on the stack, jump to | |
11204 | ;; operand 1. | |
11205 | ||
11206 | (define_expand "split_stack_space_check" | |
11207 | [(set (pc) (if_then_else | |
11208 | (ltu (minus (reg 15) | |
11209 | (match_operand 0 "register_operand")) | |
11210 | (unspec [(const_int 0)] UNSPEC_STACK_CHECK)) | |
11211 | (label_ref (match_operand 1)) | |
11212 | (pc)))] | |
11213 | "" | |
11214 | { | |
11215 | /* Offset from thread pointer to __private_ss. */ | |
11216 | int psso = TARGET_64BIT ? 0x38 : 0x20; | |
11217 | rtx tp = s390_get_thread_pointer (); | |
11218 | rtx guard = gen_rtx_MEM (Pmode, plus_constant (Pmode, tp, psso)); | |
11219 | rtx reg = gen_reg_rtx (Pmode); | |
11220 | rtx cc; | |
11221 | if (TARGET_64BIT) | |
11222 | emit_insn (gen_subdi3 (reg, stack_pointer_rtx, operands[0])); | |
11223 | else | |
11224 | emit_insn (gen_subsi3 (reg, stack_pointer_rtx, operands[0])); | |
11225 | cc = s390_emit_compare (GT, reg, guard); | |
11226 | s390_emit_jump (operands[1], cc); | |
11227 | ||
11228 | DONE; | |
11229 | }) | |
11230 | ||
11231 | ;; __morestack parameter block for split stack prologue. Parameters are: | |
11232 | ;; parameter block label, label to be called by __morestack, frame size, | |
11233 | ;; stack parameter size. | |
11234 | ||
11235 | (define_insn "split_stack_data" | |
11236 | [(unspec_volatile [(match_operand 0 "" "X") | |
11237 | (match_operand 1 "" "X") | |
11238 | (match_operand 2 "const_int_operand" "X") | |
11239 | (match_operand 3 "const_int_operand" "X")] | |
11240 | UNSPECV_SPLIT_STACK_DATA)] | |
11241 | "TARGET_CPU_ZARCH" | |
11242 | { | |
11243 | switch_to_section (targetm.asm_out.function_rodata_section | |
11244 | (current_function_decl)); | |
11245 | ||
11246 | if (TARGET_64BIT) | |
11247 | output_asm_insn (".align\t8", operands); | |
11248 | else | |
11249 | output_asm_insn (".align\t4", operands); | |
11250 | (*targetm.asm_out.internal_label) (asm_out_file, "L", | |
11251 | CODE_LABEL_NUMBER (operands[0])); | |
11252 | if (TARGET_64BIT) | |
11253 | { | |
11254 | output_asm_insn (".quad\t%2", operands); | |
11255 | output_asm_insn (".quad\t%3", operands); | |
11256 | output_asm_insn (".quad\t%1-%0", operands); | |
11257 | } | |
11258 | else | |
11259 | { | |
11260 | output_asm_insn (".long\t%2", operands); | |
11261 | output_asm_insn (".long\t%3", operands); | |
11262 | output_asm_insn (".long\t%1-%0", operands); | |
11263 | } | |
11264 | ||
11265 | switch_to_section (current_function_section ()); | |
11266 | return ""; | |
11267 | } | |
11268 | [(set_attr "length" "0")]) | |
11269 | ||
11270 | ||
11271 | ;; A jg with minimal fuss for use in split stack prologue. | |
11272 | ||
11273 | (define_expand "split_stack_call" | |
11274 | [(match_operand 0 "bras_sym_operand" "X") | |
11275 | (match_operand 1 "" "")] | |
11276 | "TARGET_CPU_ZARCH" | |
11277 | { | |
11278 | if (TARGET_64BIT) | |
11279 | emit_jump_insn (gen_split_stack_call_di (operands[0], operands[1])); | |
11280 | else | |
11281 | emit_jump_insn (gen_split_stack_call_si (operands[0], operands[1])); | |
11282 | DONE; | |
11283 | }) | |
11284 | ||
11285 | (define_insn "split_stack_call_<mode>" | |
11286 | [(set (pc) (label_ref (match_operand 1 "" ""))) | |
11287 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
11288 | (reg:P 1)] | |
11289 | UNSPECV_SPLIT_STACK_CALL))] | |
11290 | "TARGET_CPU_ZARCH" | |
11291 | "jg\t%0" | |
11292 | [(set_attr "op_type" "RIL") | |
11293 | (set_attr "type" "branch")]) | |
11294 | ||
11295 | ;; Also a conditional one. | |
11296 | ||
11297 | (define_expand "split_stack_cond_call" | |
11298 | [(match_operand 0 "bras_sym_operand" "X") | |
11299 | (match_operand 1 "" "") | |
11300 | (match_operand 2 "" "")] | |
11301 | "TARGET_CPU_ZARCH" | |
11302 | { | |
11303 | if (TARGET_64BIT) | |
11304 | emit_jump_insn (gen_split_stack_cond_call_di (operands[0], operands[1], operands[2])); | |
11305 | else | |
11306 | emit_jump_insn (gen_split_stack_cond_call_si (operands[0], operands[1], operands[2])); | |
11307 | DONE; | |
11308 | }) | |
11309 | ||
11310 | (define_insn "split_stack_cond_call_<mode>" | |
11311 | [(set (pc) | |
11312 | (if_then_else | |
11313 | (match_operand 1 "" "") | |
11314 | (label_ref (match_operand 2 "" "")) | |
11315 | (pc))) | |
11316 | (set (reg:P 1) (unspec_volatile [(match_operand 0 "bras_sym_operand" "X") | |
11317 | (reg:P 1)] | |
11318 | UNSPECV_SPLIT_STACK_CALL))] | |
11319 | "TARGET_CPU_ZARCH" | |
11320 | "jg%C1\t%0" | |
11321 | [(set_attr "op_type" "RIL") | |
11322 | (set_attr "type" "branch")]) | |
539405d5 AK |
11323 | |
11324 | (define_insn "osc_break" | |
11325 | [(unspec_volatile [(const_int 0)] UNSPECV_OSC_BREAK)] | |
11326 | "" | |
11327 | "bcr\t7,%%r0" | |
11328 | [(set_attr "op_type" "RR")]) |